1 /* Broadcom NetXtreme-C/E network driver. 2 * 3 * Copyright (c) 2014-2016 Broadcom Corporation 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation. 8 */ 9 10 #ifndef BNXT_H 11 #define BNXT_H 12 13 #define DRV_MODULE_NAME "bnxt_en" 14 #define DRV_MODULE_VERSION "1.5.0" 15 16 #define DRV_VER_MAJ 1 17 #define DRV_VER_MIN 5 18 #define DRV_VER_UPD 0 19 20 struct tx_bd { 21 __le32 tx_bd_len_flags_type; 22 #define TX_BD_TYPE (0x3f << 0) 23 #define TX_BD_TYPE_SHORT_TX_BD (0x00 << 0) 24 #define TX_BD_TYPE_LONG_TX_BD (0x10 << 0) 25 #define TX_BD_FLAGS_PACKET_END (1 << 6) 26 #define TX_BD_FLAGS_NO_CMPL (1 << 7) 27 #define TX_BD_FLAGS_BD_CNT (0x1f << 8) 28 #define TX_BD_FLAGS_BD_CNT_SHIFT 8 29 #define TX_BD_FLAGS_LHINT (3 << 13) 30 #define TX_BD_FLAGS_LHINT_SHIFT 13 31 #define TX_BD_FLAGS_LHINT_512_AND_SMALLER (0 << 13) 32 #define TX_BD_FLAGS_LHINT_512_TO_1023 (1 << 13) 33 #define TX_BD_FLAGS_LHINT_1024_TO_2047 (2 << 13) 34 #define TX_BD_FLAGS_LHINT_2048_AND_LARGER (3 << 13) 35 #define TX_BD_FLAGS_COAL_NOW (1 << 15) 36 #define TX_BD_LEN (0xffff << 16) 37 #define TX_BD_LEN_SHIFT 16 38 39 u32 tx_bd_opaque; 40 __le64 tx_bd_haddr; 41 } __packed; 42 43 struct tx_bd_ext { 44 __le32 tx_bd_hsize_lflags; 45 #define TX_BD_FLAGS_TCP_UDP_CHKSUM (1 << 0) 46 #define TX_BD_FLAGS_IP_CKSUM (1 << 1) 47 #define TX_BD_FLAGS_NO_CRC (1 << 2) 48 #define TX_BD_FLAGS_STAMP (1 << 3) 49 #define TX_BD_FLAGS_T_IP_CHKSUM (1 << 4) 50 #define TX_BD_FLAGS_LSO (1 << 5) 51 #define TX_BD_FLAGS_IPID_FMT (1 << 6) 52 #define TX_BD_FLAGS_T_IPID (1 << 7) 53 #define TX_BD_HSIZE (0xff << 16) 54 #define TX_BD_HSIZE_SHIFT 16 55 56 __le32 tx_bd_mss; 57 __le32 tx_bd_cfa_action; 58 #define TX_BD_CFA_ACTION (0xffff << 16) 59 #define TX_BD_CFA_ACTION_SHIFT 16 60 61 __le32 tx_bd_cfa_meta; 62 #define TX_BD_CFA_META_MASK 0xfffffff 63 #define TX_BD_CFA_META_VID_MASK 0xfff 64 #define TX_BD_CFA_META_PRI_MASK (0xf << 12) 65 #define TX_BD_CFA_META_PRI_SHIFT 12 66 #define TX_BD_CFA_META_TPID_MASK (3 << 16) 67 #define TX_BD_CFA_META_TPID_SHIFT 16 68 #define TX_BD_CFA_META_KEY (0xf << 28) 69 #define TX_BD_CFA_META_KEY_SHIFT 28 70 #define TX_BD_CFA_META_KEY_VLAN (1 << 28) 71 }; 72 73 struct rx_bd { 74 __le32 rx_bd_len_flags_type; 75 #define RX_BD_TYPE (0x3f << 0) 76 #define RX_BD_TYPE_RX_PACKET_BD 0x4 77 #define RX_BD_TYPE_RX_BUFFER_BD 0x5 78 #define RX_BD_TYPE_RX_AGG_BD 0x6 79 #define RX_BD_TYPE_16B_BD_SIZE (0 << 4) 80 #define RX_BD_TYPE_32B_BD_SIZE (1 << 4) 81 #define RX_BD_TYPE_48B_BD_SIZE (2 << 4) 82 #define RX_BD_TYPE_64B_BD_SIZE (3 << 4) 83 #define RX_BD_FLAGS_SOP (1 << 6) 84 #define RX_BD_FLAGS_EOP (1 << 7) 85 #define RX_BD_FLAGS_BUFFERS (3 << 8) 86 #define RX_BD_FLAGS_1_BUFFER_PACKET (0 << 8) 87 #define RX_BD_FLAGS_2_BUFFER_PACKET (1 << 8) 88 #define RX_BD_FLAGS_3_BUFFER_PACKET (2 << 8) 89 #define RX_BD_FLAGS_4_BUFFER_PACKET (3 << 8) 90 #define RX_BD_LEN (0xffff << 16) 91 #define RX_BD_LEN_SHIFT 16 92 93 u32 rx_bd_opaque; 94 __le64 rx_bd_haddr; 95 }; 96 97 struct tx_cmp { 98 __le32 tx_cmp_flags_type; 99 #define CMP_TYPE (0x3f << 0) 100 #define CMP_TYPE_TX_L2_CMP 0 101 #define CMP_TYPE_RX_L2_CMP 17 102 #define CMP_TYPE_RX_AGG_CMP 18 103 #define CMP_TYPE_RX_L2_TPA_START_CMP 19 104 #define CMP_TYPE_RX_L2_TPA_END_CMP 21 105 #define CMP_TYPE_STATUS_CMP 32 106 #define CMP_TYPE_REMOTE_DRIVER_REQ 34 107 #define CMP_TYPE_REMOTE_DRIVER_RESP 36 108 #define CMP_TYPE_ERROR_STATUS 48 109 #define CMPL_BASE_TYPE_STAT_EJECT 0x1aUL 110 #define CMPL_BASE_TYPE_HWRM_DONE 0x20UL 111 #define CMPL_BASE_TYPE_HWRM_FWD_REQ 0x22UL 112 #define CMPL_BASE_TYPE_HWRM_FWD_RESP 0x24UL 113 #define CMPL_BASE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 114 115 #define TX_CMP_FLAGS_ERROR (1 << 6) 116 #define TX_CMP_FLAGS_PUSH (1 << 7) 117 118 u32 tx_cmp_opaque; 119 __le32 tx_cmp_errors_v; 120 #define TX_CMP_V (1 << 0) 121 #define TX_CMP_ERRORS_BUFFER_ERROR (7 << 1) 122 #define TX_CMP_ERRORS_BUFFER_ERROR_NO_ERROR 0 123 #define TX_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT 2 124 #define TX_CMP_ERRORS_BUFFER_ERROR_INVALID_STAG 4 125 #define TX_CMP_ERRORS_BUFFER_ERROR_STAG_BOUNDS 5 126 #define TX_CMP_ERRORS_ZERO_LENGTH_PKT (1 << 4) 127 #define TX_CMP_ERRORS_EXCESSIVE_BD_LEN (1 << 5) 128 #define TX_CMP_ERRORS_DMA_ERROR (1 << 6) 129 #define TX_CMP_ERRORS_HINT_TOO_SHORT (1 << 7) 130 131 __le32 tx_cmp_unsed_3; 132 }; 133 134 struct rx_cmp { 135 __le32 rx_cmp_len_flags_type; 136 #define RX_CMP_CMP_TYPE (0x3f << 0) 137 #define RX_CMP_FLAGS_ERROR (1 << 6) 138 #define RX_CMP_FLAGS_PLACEMENT (7 << 7) 139 #define RX_CMP_FLAGS_RSS_VALID (1 << 10) 140 #define RX_CMP_FLAGS_UNUSED (1 << 11) 141 #define RX_CMP_FLAGS_ITYPES_SHIFT 12 142 #define RX_CMP_FLAGS_ITYPE_UNKNOWN (0 << 12) 143 #define RX_CMP_FLAGS_ITYPE_IP (1 << 12) 144 #define RX_CMP_FLAGS_ITYPE_TCP (2 << 12) 145 #define RX_CMP_FLAGS_ITYPE_UDP (3 << 12) 146 #define RX_CMP_FLAGS_ITYPE_FCOE (4 << 12) 147 #define RX_CMP_FLAGS_ITYPE_ROCE (5 << 12) 148 #define RX_CMP_FLAGS_ITYPE_PTP_WO_TS (8 << 12) 149 #define RX_CMP_FLAGS_ITYPE_PTP_W_TS (9 << 12) 150 #define RX_CMP_LEN (0xffff << 16) 151 #define RX_CMP_LEN_SHIFT 16 152 153 u32 rx_cmp_opaque; 154 __le32 rx_cmp_misc_v1; 155 #define RX_CMP_V1 (1 << 0) 156 #define RX_CMP_AGG_BUFS (0x1f << 1) 157 #define RX_CMP_AGG_BUFS_SHIFT 1 158 #define RX_CMP_RSS_HASH_TYPE (0x7f << 9) 159 #define RX_CMP_RSS_HASH_TYPE_SHIFT 9 160 #define RX_CMP_PAYLOAD_OFFSET (0xff << 16) 161 #define RX_CMP_PAYLOAD_OFFSET_SHIFT 16 162 163 __le32 rx_cmp_rss_hash; 164 }; 165 166 #define RX_CMP_HASH_VALID(rxcmp) \ 167 ((rxcmp)->rx_cmp_len_flags_type & cpu_to_le32(RX_CMP_FLAGS_RSS_VALID)) 168 169 #define RSS_PROFILE_ID_MASK 0x1f 170 171 #define RX_CMP_HASH_TYPE(rxcmp) \ 172 (((le32_to_cpu((rxcmp)->rx_cmp_misc_v1) & RX_CMP_RSS_HASH_TYPE) >>\ 173 RX_CMP_RSS_HASH_TYPE_SHIFT) & RSS_PROFILE_ID_MASK) 174 175 struct rx_cmp_ext { 176 __le32 rx_cmp_flags2; 177 #define RX_CMP_FLAGS2_IP_CS_CALC 0x1 178 #define RX_CMP_FLAGS2_L4_CS_CALC (0x1 << 1) 179 #define RX_CMP_FLAGS2_T_IP_CS_CALC (0x1 << 2) 180 #define RX_CMP_FLAGS2_T_L4_CS_CALC (0x1 << 3) 181 #define RX_CMP_FLAGS2_META_FORMAT_VLAN (0x1 << 4) 182 __le32 rx_cmp_meta_data; 183 #define RX_CMP_FLAGS2_METADATA_VID_MASK 0xfff 184 #define RX_CMP_FLAGS2_METADATA_TPID_MASK 0xffff0000 185 #define RX_CMP_FLAGS2_METADATA_TPID_SFT 16 186 __le32 rx_cmp_cfa_code_errors_v2; 187 #define RX_CMP_V (1 << 0) 188 #define RX_CMPL_ERRORS_MASK (0x7fff << 1) 189 #define RX_CMPL_ERRORS_SFT 1 190 #define RX_CMPL_ERRORS_BUFFER_ERROR_MASK (0x7 << 1) 191 #define RX_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0 << 1) 192 #define RX_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT (0x1 << 1) 193 #define RX_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP (0x2 << 1) 194 #define RX_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3 << 1) 195 #define RX_CMPL_ERRORS_IP_CS_ERROR (0x1 << 4) 196 #define RX_CMPL_ERRORS_L4_CS_ERROR (0x1 << 5) 197 #define RX_CMPL_ERRORS_T_IP_CS_ERROR (0x1 << 6) 198 #define RX_CMPL_ERRORS_T_L4_CS_ERROR (0x1 << 7) 199 #define RX_CMPL_ERRORS_CRC_ERROR (0x1 << 8) 200 #define RX_CMPL_ERRORS_T_PKT_ERROR_MASK (0x7 << 9) 201 #define RX_CMPL_ERRORS_T_PKT_ERROR_NO_ERROR (0x0 << 9) 202 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION (0x1 << 9) 203 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN (0x2 << 9) 204 #define RX_CMPL_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR (0x3 << 9) 205 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR (0x4 << 9) 206 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR (0x5 << 9) 207 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL (0x6 << 9) 208 #define RX_CMPL_ERRORS_PKT_ERROR_MASK (0xf << 12) 209 #define RX_CMPL_ERRORS_PKT_ERROR_NO_ERROR (0x0 << 12) 210 #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_VERSION (0x1 << 12) 211 #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN (0x2 << 12) 212 #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_TTL (0x3 << 12) 213 #define RX_CMPL_ERRORS_PKT_ERROR_IP_TOTAL_ERROR (0x4 << 12) 214 #define RX_CMPL_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR (0x5 << 12) 215 #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN (0x6 << 12) 216 #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL (0x7 << 12) 217 #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN (0x8 << 12) 218 219 #define RX_CMPL_CFA_CODE_MASK (0xffff << 16) 220 #define RX_CMPL_CFA_CODE_SFT 16 221 222 __le32 rx_cmp_unused3; 223 }; 224 225 #define RX_CMP_L2_ERRORS \ 226 cpu_to_le32(RX_CMPL_ERRORS_BUFFER_ERROR_MASK | RX_CMPL_ERRORS_CRC_ERROR) 227 228 #define RX_CMP_L4_CS_BITS \ 229 (cpu_to_le32(RX_CMP_FLAGS2_L4_CS_CALC | RX_CMP_FLAGS2_T_L4_CS_CALC)) 230 231 #define RX_CMP_L4_CS_ERR_BITS \ 232 (cpu_to_le32(RX_CMPL_ERRORS_L4_CS_ERROR | RX_CMPL_ERRORS_T_L4_CS_ERROR)) 233 234 #define RX_CMP_L4_CS_OK(rxcmp1) \ 235 (((rxcmp1)->rx_cmp_flags2 & RX_CMP_L4_CS_BITS) && \ 236 !((rxcmp1)->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS)) 237 238 #define RX_CMP_ENCAP(rxcmp1) \ 239 ((le32_to_cpu((rxcmp1)->rx_cmp_flags2) & \ 240 RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3) 241 242 struct rx_agg_cmp { 243 __le32 rx_agg_cmp_len_flags_type; 244 #define RX_AGG_CMP_TYPE (0x3f << 0) 245 #define RX_AGG_CMP_LEN (0xffff << 16) 246 #define RX_AGG_CMP_LEN_SHIFT 16 247 u32 rx_agg_cmp_opaque; 248 __le32 rx_agg_cmp_v; 249 #define RX_AGG_CMP_V (1 << 0) 250 __le32 rx_agg_cmp_unused; 251 }; 252 253 struct rx_tpa_start_cmp { 254 __le32 rx_tpa_start_cmp_len_flags_type; 255 #define RX_TPA_START_CMP_TYPE (0x3f << 0) 256 #define RX_TPA_START_CMP_FLAGS (0x3ff << 6) 257 #define RX_TPA_START_CMP_FLAGS_SHIFT 6 258 #define RX_TPA_START_CMP_FLAGS_PLACEMENT (0x7 << 7) 259 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_SHIFT 7 260 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_JUMBO (0x1 << 7) 261 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_HDS (0x2 << 7) 262 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_GRO_JUMBO (0x5 << 7) 263 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_GRO_HDS (0x6 << 7) 264 #define RX_TPA_START_CMP_FLAGS_RSS_VALID (0x1 << 10) 265 #define RX_TPA_START_CMP_FLAGS_ITYPES (0xf << 12) 266 #define RX_TPA_START_CMP_FLAGS_ITYPES_SHIFT 12 267 #define RX_TPA_START_CMP_FLAGS_ITYPE_TCP (0x2 << 12) 268 #define RX_TPA_START_CMP_LEN (0xffff << 16) 269 #define RX_TPA_START_CMP_LEN_SHIFT 16 270 271 u32 rx_tpa_start_cmp_opaque; 272 __le32 rx_tpa_start_cmp_misc_v1; 273 #define RX_TPA_START_CMP_V1 (0x1 << 0) 274 #define RX_TPA_START_CMP_RSS_HASH_TYPE (0x7f << 9) 275 #define RX_TPA_START_CMP_RSS_HASH_TYPE_SHIFT 9 276 #define RX_TPA_START_CMP_AGG_ID (0x7f << 25) 277 #define RX_TPA_START_CMP_AGG_ID_SHIFT 25 278 279 __le32 rx_tpa_start_cmp_rss_hash; 280 }; 281 282 #define TPA_START_HASH_VALID(rx_tpa_start) \ 283 ((rx_tpa_start)->rx_tpa_start_cmp_len_flags_type & \ 284 cpu_to_le32(RX_TPA_START_CMP_FLAGS_RSS_VALID)) 285 286 #define TPA_START_HASH_TYPE(rx_tpa_start) \ 287 (((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) & \ 288 RX_TPA_START_CMP_RSS_HASH_TYPE) >> \ 289 RX_TPA_START_CMP_RSS_HASH_TYPE_SHIFT) & RSS_PROFILE_ID_MASK) 290 291 #define TPA_START_AGG_ID(rx_tpa_start) \ 292 ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) & \ 293 RX_TPA_START_CMP_AGG_ID) >> RX_TPA_START_CMP_AGG_ID_SHIFT) 294 295 struct rx_tpa_start_cmp_ext { 296 __le32 rx_tpa_start_cmp_flags2; 297 #define RX_TPA_START_CMP_FLAGS2_IP_CS_CALC (0x1 << 0) 298 #define RX_TPA_START_CMP_FLAGS2_L4_CS_CALC (0x1 << 1) 299 #define RX_TPA_START_CMP_FLAGS2_T_IP_CS_CALC (0x1 << 2) 300 #define RX_TPA_START_CMP_FLAGS2_T_L4_CS_CALC (0x1 << 3) 301 #define RX_TPA_START_CMP_FLAGS2_IP_TYPE (0x1 << 8) 302 303 __le32 rx_tpa_start_cmp_metadata; 304 __le32 rx_tpa_start_cmp_cfa_code_v2; 305 #define RX_TPA_START_CMP_V2 (0x1 << 0) 306 #define RX_TPA_START_CMP_CFA_CODE (0xffff << 16) 307 #define RX_TPA_START_CMPL_CFA_CODE_SHIFT 16 308 __le32 rx_tpa_start_cmp_hdr_info; 309 }; 310 311 struct rx_tpa_end_cmp { 312 __le32 rx_tpa_end_cmp_len_flags_type; 313 #define RX_TPA_END_CMP_TYPE (0x3f << 0) 314 #define RX_TPA_END_CMP_FLAGS (0x3ff << 6) 315 #define RX_TPA_END_CMP_FLAGS_SHIFT 6 316 #define RX_TPA_END_CMP_FLAGS_PLACEMENT (0x7 << 7) 317 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_SHIFT 7 318 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_JUMBO (0x1 << 7) 319 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_HDS (0x2 << 7) 320 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_JUMBO (0x5 << 7) 321 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_HDS (0x6 << 7) 322 #define RX_TPA_END_CMP_FLAGS_RSS_VALID (0x1 << 10) 323 #define RX_TPA_END_CMP_FLAGS_ITYPES (0xf << 12) 324 #define RX_TPA_END_CMP_FLAGS_ITYPES_SHIFT 12 325 #define RX_TPA_END_CMP_FLAGS_ITYPE_TCP (0x2 << 12) 326 #define RX_TPA_END_CMP_LEN (0xffff << 16) 327 #define RX_TPA_END_CMP_LEN_SHIFT 16 328 329 u32 rx_tpa_end_cmp_opaque; 330 __le32 rx_tpa_end_cmp_misc_v1; 331 #define RX_TPA_END_CMP_V1 (0x1 << 0) 332 #define RX_TPA_END_CMP_AGG_BUFS (0x3f << 1) 333 #define RX_TPA_END_CMP_AGG_BUFS_SHIFT 1 334 #define RX_TPA_END_CMP_TPA_SEGS (0xff << 8) 335 #define RX_TPA_END_CMP_TPA_SEGS_SHIFT 8 336 #define RX_TPA_END_CMP_PAYLOAD_OFFSET (0xff << 16) 337 #define RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT 16 338 #define RX_TPA_END_CMP_AGG_ID (0x7f << 25) 339 #define RX_TPA_END_CMP_AGG_ID_SHIFT 25 340 341 __le32 rx_tpa_end_cmp_tsdelta; 342 #define RX_TPA_END_GRO_TS (0x1 << 31) 343 }; 344 345 #define TPA_END_AGG_ID(rx_tpa_end) \ 346 ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \ 347 RX_TPA_END_CMP_AGG_ID) >> RX_TPA_END_CMP_AGG_ID_SHIFT) 348 349 #define TPA_END_TPA_SEGS(rx_tpa_end) \ 350 ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \ 351 RX_TPA_END_CMP_TPA_SEGS) >> RX_TPA_END_CMP_TPA_SEGS_SHIFT) 352 353 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_ANY_GRO \ 354 cpu_to_le32(RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_JUMBO & \ 355 RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_HDS) 356 357 #define TPA_END_GRO(rx_tpa_end) \ 358 ((rx_tpa_end)->rx_tpa_end_cmp_len_flags_type & \ 359 RX_TPA_END_CMP_FLAGS_PLACEMENT_ANY_GRO) 360 361 #define TPA_END_GRO_TS(rx_tpa_end) \ 362 (!!((rx_tpa_end)->rx_tpa_end_cmp_tsdelta & \ 363 cpu_to_le32(RX_TPA_END_GRO_TS))) 364 365 struct rx_tpa_end_cmp_ext { 366 __le32 rx_tpa_end_cmp_dup_acks; 367 #define RX_TPA_END_CMP_TPA_DUP_ACKS (0xf << 0) 368 369 __le32 rx_tpa_end_cmp_seg_len; 370 #define RX_TPA_END_CMP_TPA_SEG_LEN (0xffff << 0) 371 372 __le32 rx_tpa_end_cmp_errors_v2; 373 #define RX_TPA_END_CMP_V2 (0x1 << 0) 374 #define RX_TPA_END_CMP_ERRORS (0x7fff << 1) 375 #define RX_TPA_END_CMPL_ERRORS_SHIFT 1 376 377 u32 rx_tpa_end_cmp_start_opaque; 378 }; 379 380 #define DB_IDX_MASK 0xffffff 381 #define DB_IDX_VALID (0x1 << 26) 382 #define DB_IRQ_DIS (0x1 << 27) 383 #define DB_KEY_TX (0x0 << 28) 384 #define DB_KEY_RX (0x1 << 28) 385 #define DB_KEY_CP (0x2 << 28) 386 #define DB_KEY_ST (0x3 << 28) 387 #define DB_KEY_TX_PUSH (0x4 << 28) 388 #define DB_LONG_TX_PUSH (0x2 << 24) 389 390 #define INVALID_HW_RING_ID ((u16)-1) 391 392 /* The hardware supports certain page sizes. Use the supported page sizes 393 * to allocate the rings. 394 */ 395 #if (PAGE_SHIFT < 12) 396 #define BNXT_PAGE_SHIFT 12 397 #elif (PAGE_SHIFT <= 13) 398 #define BNXT_PAGE_SHIFT PAGE_SHIFT 399 #elif (PAGE_SHIFT < 16) 400 #define BNXT_PAGE_SHIFT 13 401 #else 402 #define BNXT_PAGE_SHIFT 16 403 #endif 404 405 #define BNXT_PAGE_SIZE (1 << BNXT_PAGE_SHIFT) 406 407 /* The RXBD length is 16-bit so we can only support page sizes < 64K */ 408 #if (PAGE_SHIFT > 15) 409 #define BNXT_RX_PAGE_SHIFT 15 410 #else 411 #define BNXT_RX_PAGE_SHIFT PAGE_SHIFT 412 #endif 413 414 #define BNXT_RX_PAGE_SIZE (1 << BNXT_RX_PAGE_SHIFT) 415 416 #define BNXT_MIN_PKT_SIZE 52 417 418 #define BNXT_NUM_TESTS(bp) 0 419 420 #define BNXT_DEFAULT_RX_RING_SIZE 511 421 #define BNXT_DEFAULT_TX_RING_SIZE 511 422 423 #define MAX_TPA 64 424 425 #if (BNXT_PAGE_SHIFT == 16) 426 #define MAX_RX_PAGES 1 427 #define MAX_RX_AGG_PAGES 4 428 #define MAX_TX_PAGES 1 429 #define MAX_CP_PAGES 8 430 #else 431 #define MAX_RX_PAGES 8 432 #define MAX_RX_AGG_PAGES 32 433 #define MAX_TX_PAGES 8 434 #define MAX_CP_PAGES 64 435 #endif 436 437 #define RX_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct rx_bd)) 438 #define TX_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct tx_bd)) 439 #define CP_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct tx_cmp)) 440 441 #define SW_RXBD_RING_SIZE (sizeof(struct bnxt_sw_rx_bd) * RX_DESC_CNT) 442 #define HW_RXBD_RING_SIZE (sizeof(struct rx_bd) * RX_DESC_CNT) 443 444 #define SW_RXBD_AGG_RING_SIZE (sizeof(struct bnxt_sw_rx_agg_bd) * RX_DESC_CNT) 445 446 #define SW_TXBD_RING_SIZE (sizeof(struct bnxt_sw_tx_bd) * TX_DESC_CNT) 447 #define HW_TXBD_RING_SIZE (sizeof(struct tx_bd) * TX_DESC_CNT) 448 449 #define HW_CMPD_RING_SIZE (sizeof(struct tx_cmp) * CP_DESC_CNT) 450 451 #define BNXT_MAX_RX_DESC_CNT (RX_DESC_CNT * MAX_RX_PAGES - 1) 452 #define BNXT_MAX_RX_JUM_DESC_CNT (RX_DESC_CNT * MAX_RX_AGG_PAGES - 1) 453 #define BNXT_MAX_TX_DESC_CNT (TX_DESC_CNT * MAX_TX_PAGES - 1) 454 455 #define RX_RING(x) (((x) & ~(RX_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4)) 456 #define RX_IDX(x) ((x) & (RX_DESC_CNT - 1)) 457 458 #define TX_RING(x) (((x) & ~(TX_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4)) 459 #define TX_IDX(x) ((x) & (TX_DESC_CNT - 1)) 460 461 #define CP_RING(x) (((x) & ~(CP_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4)) 462 #define CP_IDX(x) ((x) & (CP_DESC_CNT - 1)) 463 464 #define TX_CMP_VALID(txcmp, raw_cons) \ 465 (!!((txcmp)->tx_cmp_errors_v & cpu_to_le32(TX_CMP_V)) == \ 466 !((raw_cons) & bp->cp_bit)) 467 468 #define RX_CMP_VALID(rxcmp1, raw_cons) \ 469 (!!((rxcmp1)->rx_cmp_cfa_code_errors_v2 & cpu_to_le32(RX_CMP_V)) ==\ 470 !((raw_cons) & bp->cp_bit)) 471 472 #define RX_AGG_CMP_VALID(agg, raw_cons) \ 473 (!!((agg)->rx_agg_cmp_v & cpu_to_le32(RX_AGG_CMP_V)) == \ 474 !((raw_cons) & bp->cp_bit)) 475 476 #define TX_CMP_TYPE(txcmp) \ 477 (le32_to_cpu((txcmp)->tx_cmp_flags_type) & CMP_TYPE) 478 479 #define RX_CMP_TYPE(rxcmp) \ 480 (le32_to_cpu((rxcmp)->rx_cmp_len_flags_type) & RX_CMP_CMP_TYPE) 481 482 #define NEXT_RX(idx) (((idx) + 1) & bp->rx_ring_mask) 483 484 #define NEXT_RX_AGG(idx) (((idx) + 1) & bp->rx_agg_ring_mask) 485 486 #define NEXT_TX(idx) (((idx) + 1) & bp->tx_ring_mask) 487 488 #define ADV_RAW_CMP(idx, n) ((idx) + (n)) 489 #define NEXT_RAW_CMP(idx) ADV_RAW_CMP(idx, 1) 490 #define RING_CMP(idx) ((idx) & bp->cp_ring_mask) 491 #define NEXT_CMP(idx) RING_CMP(ADV_RAW_CMP(idx, 1)) 492 493 #define BNXT_HWRM_MAX_REQ_LEN (bp->hwrm_max_req_len) 494 #define DFLT_HWRM_CMD_TIMEOUT 500 495 #define HWRM_CMD_TIMEOUT (bp->hwrm_cmd_timeout) 496 #define HWRM_RESET_TIMEOUT ((HWRM_CMD_TIMEOUT) * 4) 497 #define HWRM_RESP_ERR_CODE_MASK 0xffff 498 #define HWRM_RESP_LEN_OFFSET 4 499 #define HWRM_RESP_LEN_MASK 0xffff0000 500 #define HWRM_RESP_LEN_SFT 16 501 #define HWRM_RESP_VALID_MASK 0xff000000 502 #define HWRM_SEQ_ID_INVALID -1 503 #define BNXT_HWRM_REQ_MAX_SIZE 128 504 #define BNXT_HWRM_REQS_PER_PAGE (BNXT_PAGE_SIZE / \ 505 BNXT_HWRM_REQ_MAX_SIZE) 506 507 struct bnxt_sw_tx_bd { 508 struct sk_buff *skb; 509 DEFINE_DMA_UNMAP_ADDR(mapping); 510 u8 is_gso; 511 u8 is_push; 512 unsigned short nr_frags; 513 }; 514 515 struct bnxt_sw_rx_bd { 516 u8 *data; 517 DEFINE_DMA_UNMAP_ADDR(mapping); 518 }; 519 520 struct bnxt_sw_rx_agg_bd { 521 struct page *page; 522 unsigned int offset; 523 dma_addr_t mapping; 524 }; 525 526 struct bnxt_ring_struct { 527 int nr_pages; 528 int page_size; 529 void **pg_arr; 530 dma_addr_t *dma_arr; 531 532 __le64 *pg_tbl; 533 dma_addr_t pg_tbl_map; 534 535 int vmem_size; 536 void **vmem; 537 538 u16 fw_ring_id; /* Ring id filled by Chimp FW */ 539 u8 queue_id; 540 }; 541 542 struct tx_push_bd { 543 __le32 doorbell; 544 __le32 tx_bd_len_flags_type; 545 u32 tx_bd_opaque; 546 struct tx_bd_ext txbd2; 547 }; 548 549 struct tx_push_buffer { 550 struct tx_push_bd push_bd; 551 u32 data[25]; 552 }; 553 554 struct bnxt_tx_ring_info { 555 struct bnxt_napi *bnapi; 556 u16 tx_prod; 557 u16 tx_cons; 558 void __iomem *tx_doorbell; 559 560 struct tx_bd *tx_desc_ring[MAX_TX_PAGES]; 561 struct bnxt_sw_tx_bd *tx_buf_ring; 562 563 dma_addr_t tx_desc_mapping[MAX_TX_PAGES]; 564 565 struct tx_push_buffer *tx_push; 566 dma_addr_t tx_push_mapping; 567 __le64 data_mapping; 568 569 #define BNXT_DEV_STATE_CLOSING 0x1 570 u32 dev_state; 571 572 struct bnxt_ring_struct tx_ring_struct; 573 }; 574 575 struct bnxt_tpa_info { 576 u8 *data; 577 dma_addr_t mapping; 578 u16 len; 579 unsigned short gso_type; 580 u32 flags2; 581 u32 metadata; 582 enum pkt_hash_types hash_type; 583 u32 rss_hash; 584 u32 hdr_info; 585 586 #define BNXT_TPA_L4_SIZE(hdr_info) \ 587 (((hdr_info) & 0xf8000000) ? ((hdr_info) >> 27) : 32) 588 589 #define BNXT_TPA_INNER_L3_OFF(hdr_info) \ 590 (((hdr_info) >> 18) & 0x1ff) 591 592 #define BNXT_TPA_INNER_L2_OFF(hdr_info) \ 593 (((hdr_info) >> 9) & 0x1ff) 594 595 #define BNXT_TPA_OUTER_L3_OFF(hdr_info) \ 596 ((hdr_info) & 0x1ff) 597 }; 598 599 struct bnxt_rx_ring_info { 600 struct bnxt_napi *bnapi; 601 u16 rx_prod; 602 u16 rx_agg_prod; 603 u16 rx_sw_agg_prod; 604 u16 rx_next_cons; 605 void __iomem *rx_doorbell; 606 void __iomem *rx_agg_doorbell; 607 608 struct rx_bd *rx_desc_ring[MAX_RX_PAGES]; 609 struct bnxt_sw_rx_bd *rx_buf_ring; 610 611 struct rx_bd *rx_agg_desc_ring[MAX_RX_AGG_PAGES]; 612 struct bnxt_sw_rx_agg_bd *rx_agg_ring; 613 614 unsigned long *rx_agg_bmap; 615 u16 rx_agg_bmap_size; 616 617 struct page *rx_page; 618 unsigned int rx_page_offset; 619 620 dma_addr_t rx_desc_mapping[MAX_RX_PAGES]; 621 dma_addr_t rx_agg_desc_mapping[MAX_RX_AGG_PAGES]; 622 623 struct bnxt_tpa_info *rx_tpa; 624 625 struct bnxt_ring_struct rx_ring_struct; 626 struct bnxt_ring_struct rx_agg_ring_struct; 627 }; 628 629 struct bnxt_cp_ring_info { 630 u32 cp_raw_cons; 631 void __iomem *cp_doorbell; 632 633 struct tx_cmp *cp_desc_ring[MAX_CP_PAGES]; 634 635 dma_addr_t cp_desc_mapping[MAX_CP_PAGES]; 636 637 struct ctx_hw_stats *hw_stats; 638 dma_addr_t hw_stats_map; 639 u32 hw_stats_ctx_id; 640 u64 rx_l4_csum_errors; 641 642 struct bnxt_ring_struct cp_ring_struct; 643 }; 644 645 struct bnxt_napi { 646 struct napi_struct napi; 647 struct bnxt *bp; 648 649 int index; 650 struct bnxt_cp_ring_info cp_ring; 651 struct bnxt_rx_ring_info *rx_ring; 652 struct bnxt_tx_ring_info *tx_ring; 653 654 #ifdef CONFIG_NET_RX_BUSY_POLL 655 atomic_t poll_state; 656 #endif 657 bool in_reset; 658 }; 659 660 #ifdef CONFIG_NET_RX_BUSY_POLL 661 enum bnxt_poll_state_t { 662 BNXT_STATE_IDLE = 0, 663 BNXT_STATE_NAPI, 664 BNXT_STATE_POLL, 665 BNXT_STATE_DISABLE, 666 }; 667 #endif 668 669 struct bnxt_irq { 670 irq_handler_t handler; 671 unsigned int vector; 672 u8 requested; 673 char name[IFNAMSIZ + 2]; 674 }; 675 676 #define HWRM_RING_ALLOC_TX 0x1 677 #define HWRM_RING_ALLOC_RX 0x2 678 #define HWRM_RING_ALLOC_AGG 0x4 679 #define HWRM_RING_ALLOC_CMPL 0x8 680 681 #define INVALID_STATS_CTX_ID -1 682 683 struct bnxt_ring_grp_info { 684 u16 fw_stats_ctx; 685 u16 fw_grp_id; 686 u16 rx_fw_ring_id; 687 u16 agg_fw_ring_id; 688 u16 cp_fw_ring_id; 689 }; 690 691 struct bnxt_vnic_info { 692 u16 fw_vnic_id; /* returned by Chimp during alloc */ 693 #define BNXT_MAX_CTX_PER_VNIC 2 694 u16 fw_rss_cos_lb_ctx[BNXT_MAX_CTX_PER_VNIC]; 695 u16 fw_l2_ctx_id; 696 #define BNXT_MAX_UC_ADDRS 4 697 __le64 fw_l2_filter_id[BNXT_MAX_UC_ADDRS]; 698 /* index 0 always dev_addr */ 699 u16 uc_filter_count; 700 u8 *uc_list; 701 702 u16 *fw_grp_ids; 703 u16 hash_type; 704 dma_addr_t rss_table_dma_addr; 705 __le16 *rss_table; 706 dma_addr_t rss_hash_key_dma_addr; 707 u64 *rss_hash_key; 708 u32 rx_mask; 709 710 u8 *mc_list; 711 int mc_list_size; 712 int mc_list_count; 713 dma_addr_t mc_list_mapping; 714 #define BNXT_MAX_MC_ADDRS 16 715 716 u32 flags; 717 #define BNXT_VNIC_RSS_FLAG 1 718 #define BNXT_VNIC_RFS_FLAG 2 719 #define BNXT_VNIC_MCAST_FLAG 4 720 #define BNXT_VNIC_UCAST_FLAG 8 721 }; 722 723 #if defined(CONFIG_BNXT_SRIOV) 724 struct bnxt_vf_info { 725 u16 fw_fid; 726 u8 mac_addr[ETH_ALEN]; 727 u16 max_rsscos_ctxs; 728 u16 max_cp_rings; 729 u16 max_tx_rings; 730 u16 max_rx_rings; 731 u16 max_hw_ring_grps; 732 u16 max_l2_ctxs; 733 u16 max_irqs; 734 u16 max_vnics; 735 u16 max_stat_ctxs; 736 u16 vlan; 737 u32 flags; 738 #define BNXT_VF_QOS 0x1 739 #define BNXT_VF_SPOOFCHK 0x2 740 #define BNXT_VF_LINK_FORCED 0x4 741 #define BNXT_VF_LINK_UP 0x8 742 u32 func_flags; /* func cfg flags */ 743 u32 min_tx_rate; 744 u32 max_tx_rate; 745 void *hwrm_cmd_req_addr; 746 dma_addr_t hwrm_cmd_req_dma_addr; 747 }; 748 #endif 749 750 struct bnxt_pf_info { 751 #define BNXT_FIRST_PF_FID 1 752 #define BNXT_FIRST_VF_FID 128 753 u16 fw_fid; 754 u16 port_id; 755 u8 mac_addr[ETH_ALEN]; 756 u16 max_rsscos_ctxs; 757 u16 max_cp_rings; 758 u16 max_tx_rings; /* HW assigned max tx rings for this PF */ 759 u16 max_rx_rings; /* HW assigned max rx rings for this PF */ 760 u16 max_hw_ring_grps; 761 u16 max_irqs; 762 u16 max_l2_ctxs; 763 u16 max_vnics; 764 u16 max_stat_ctxs; 765 u32 first_vf_id; 766 u16 active_vfs; 767 u16 max_vfs; 768 u32 max_encap_records; 769 u32 max_decap_records; 770 u32 max_tx_em_flows; 771 u32 max_tx_wm_flows; 772 u32 max_rx_em_flows; 773 u32 max_rx_wm_flows; 774 unsigned long *vf_event_bmap; 775 u16 hwrm_cmd_req_pages; 776 void *hwrm_cmd_req_addr[4]; 777 dma_addr_t hwrm_cmd_req_dma_addr[4]; 778 struct bnxt_vf_info *vf; 779 }; 780 781 struct bnxt_ntuple_filter { 782 struct hlist_node hash; 783 u8 dst_mac_addr[ETH_ALEN]; 784 u8 src_mac_addr[ETH_ALEN]; 785 struct flow_keys fkeys; 786 __le64 filter_id; 787 u16 sw_id; 788 u8 l2_fltr_idx; 789 u16 rxq; 790 u32 flow_id; 791 unsigned long state; 792 #define BNXT_FLTR_VALID 0 793 #define BNXT_FLTR_UPDATE 1 794 }; 795 796 struct bnxt_link_info { 797 u8 phy_type; 798 u8 media_type; 799 u8 transceiver; 800 u8 phy_addr; 801 u8 phy_link_status; 802 #define BNXT_LINK_NO_LINK PORT_PHY_QCFG_RESP_LINK_NO_LINK 803 #define BNXT_LINK_SIGNAL PORT_PHY_QCFG_RESP_LINK_SIGNAL 804 #define BNXT_LINK_LINK PORT_PHY_QCFG_RESP_LINK_LINK 805 u8 wire_speed; 806 u8 loop_back; 807 u8 link_up; 808 u8 duplex; 809 #define BNXT_LINK_DUPLEX_HALF PORT_PHY_QCFG_RESP_DUPLEX_HALF 810 #define BNXT_LINK_DUPLEX_FULL PORT_PHY_QCFG_RESP_DUPLEX_FULL 811 u8 pause; 812 #define BNXT_LINK_PAUSE_TX PORT_PHY_QCFG_RESP_PAUSE_TX 813 #define BNXT_LINK_PAUSE_RX PORT_PHY_QCFG_RESP_PAUSE_RX 814 #define BNXT_LINK_PAUSE_BOTH (PORT_PHY_QCFG_RESP_PAUSE_RX | \ 815 PORT_PHY_QCFG_RESP_PAUSE_TX) 816 u8 lp_pause; 817 u8 auto_pause_setting; 818 u8 force_pause_setting; 819 u8 duplex_setting; 820 u8 auto_mode; 821 #define BNXT_AUTO_MODE(mode) ((mode) > BNXT_LINK_AUTO_NONE && \ 822 (mode) <= BNXT_LINK_AUTO_MSK) 823 #define BNXT_LINK_AUTO_NONE PORT_PHY_QCFG_RESP_AUTO_MODE_NONE 824 #define BNXT_LINK_AUTO_ALLSPDS PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS 825 #define BNXT_LINK_AUTO_ONESPD PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED 826 #define BNXT_LINK_AUTO_ONEORBELOW PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW 827 #define BNXT_LINK_AUTO_MSK PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK 828 #define PHY_VER_LEN 3 829 u8 phy_ver[PHY_VER_LEN]; 830 u16 link_speed; 831 #define BNXT_LINK_SPEED_100MB PORT_PHY_QCFG_RESP_LINK_SPEED_100MB 832 #define BNXT_LINK_SPEED_1GB PORT_PHY_QCFG_RESP_LINK_SPEED_1GB 833 #define BNXT_LINK_SPEED_2GB PORT_PHY_QCFG_RESP_LINK_SPEED_2GB 834 #define BNXT_LINK_SPEED_2_5GB PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB 835 #define BNXT_LINK_SPEED_10GB PORT_PHY_QCFG_RESP_LINK_SPEED_10GB 836 #define BNXT_LINK_SPEED_20GB PORT_PHY_QCFG_RESP_LINK_SPEED_20GB 837 #define BNXT_LINK_SPEED_25GB PORT_PHY_QCFG_RESP_LINK_SPEED_25GB 838 #define BNXT_LINK_SPEED_40GB PORT_PHY_QCFG_RESP_LINK_SPEED_40GB 839 #define BNXT_LINK_SPEED_50GB PORT_PHY_QCFG_RESP_LINK_SPEED_50GB 840 u16 support_speeds; 841 u16 auto_link_speeds; 842 #define BNXT_LINK_SPEED_MSK_100MB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB 843 #define BNXT_LINK_SPEED_MSK_1GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB 844 #define BNXT_LINK_SPEED_MSK_2GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB 845 #define BNXT_LINK_SPEED_MSK_10GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB 846 #define BNXT_LINK_SPEED_MSK_2_5GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB 847 #define BNXT_LINK_SPEED_MSK_20GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB 848 #define BNXT_LINK_SPEED_MSK_25GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB 849 #define BNXT_LINK_SPEED_MSK_40GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB 850 #define BNXT_LINK_SPEED_MSK_50GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB 851 u16 support_auto_speeds; 852 u16 lp_auto_link_speeds; 853 u16 force_link_speed; 854 u32 preemphasis; 855 u8 module_status; 856 857 /* copy of requested setting from ethtool cmd */ 858 u8 autoneg; 859 #define BNXT_AUTONEG_SPEED 1 860 #define BNXT_AUTONEG_FLOW_CTRL 2 861 u8 req_duplex; 862 u8 req_flow_ctrl; 863 u16 req_link_speed; 864 u32 advertising; 865 bool force_link_chng; 866 867 /* a copy of phy_qcfg output used to report link 868 * info to VF 869 */ 870 struct hwrm_port_phy_qcfg_output phy_qcfg_resp; 871 }; 872 873 #define BNXT_MAX_QUEUE 8 874 875 struct bnxt_queue_info { 876 u8 queue_id; 877 u8 queue_profile; 878 }; 879 880 #define BNXT_GRCPF_REG_WINDOW_BASE_OUT 0x400 881 #define BNXT_CAG_REG_LEGACY_INT_STATUS 0x4014 882 #define BNXT_CAG_REG_BASE 0x300000 883 884 struct bnxt { 885 void __iomem *bar0; 886 void __iomem *bar1; 887 void __iomem *bar2; 888 889 u32 reg_base; 890 u16 chip_num; 891 #define CHIP_NUM_57301 0x16c8 892 #define CHIP_NUM_57302 0x16c9 893 #define CHIP_NUM_57304 0x16ca 894 #define CHIP_NUM_58700 0x16cd 895 #define CHIP_NUM_57402 0x16d0 896 #define CHIP_NUM_57404 0x16d1 897 #define CHIP_NUM_57406 0x16d2 898 899 #define CHIP_NUM_57311 0x16ce 900 #define CHIP_NUM_57312 0x16cf 901 #define CHIP_NUM_57314 0x16df 902 #define CHIP_NUM_57412 0x16d6 903 #define CHIP_NUM_57414 0x16d7 904 #define CHIP_NUM_57416 0x16d8 905 #define CHIP_NUM_57417 0x16d9 906 907 #define BNXT_CHIP_NUM_5730X(chip_num) \ 908 ((chip_num) >= CHIP_NUM_57301 && \ 909 (chip_num) <= CHIP_NUM_57304) 910 911 #define BNXT_CHIP_NUM_5740X(chip_num) \ 912 ((chip_num) >= CHIP_NUM_57402 && \ 913 (chip_num) <= CHIP_NUM_57406) 914 915 #define BNXT_CHIP_NUM_5731X(chip_num) \ 916 ((chip_num) == CHIP_NUM_57311 || \ 917 (chip_num) == CHIP_NUM_57312 || \ 918 (chip_num) == CHIP_NUM_57314) 919 920 #define BNXT_CHIP_NUM_5741X(chip_num) \ 921 ((chip_num) >= CHIP_NUM_57412 && \ 922 (chip_num) <= CHIP_NUM_57417) 923 924 #define BNXT_CHIP_NUM_57X0X(chip_num) \ 925 (BNXT_CHIP_NUM_5730X(chip_num) || BNXT_CHIP_NUM_5740X(chip_num)) 926 927 #define BNXT_CHIP_NUM_57X1X(chip_num) \ 928 (BNXT_CHIP_NUM_5731X(chip_num) || BNXT_CHIP_NUM_5741X(chip_num)) 929 930 struct net_device *dev; 931 struct pci_dev *pdev; 932 933 atomic_t intr_sem; 934 935 u32 flags; 936 #define BNXT_FLAG_DCB_ENABLED 0x1 937 #define BNXT_FLAG_VF 0x2 938 #define BNXT_FLAG_LRO 0x4 939 #ifdef CONFIG_INET 940 #define BNXT_FLAG_GRO 0x8 941 #else 942 /* Cannot support hardware GRO if CONFIG_INET is not set */ 943 #define BNXT_FLAG_GRO 0x0 944 #endif 945 #define BNXT_FLAG_TPA (BNXT_FLAG_LRO | BNXT_FLAG_GRO) 946 #define BNXT_FLAG_JUMBO 0x10 947 #define BNXT_FLAG_STRIP_VLAN 0x20 948 #define BNXT_FLAG_AGG_RINGS (BNXT_FLAG_JUMBO | BNXT_FLAG_GRO | \ 949 BNXT_FLAG_LRO) 950 #define BNXT_FLAG_USING_MSIX 0x40 951 #define BNXT_FLAG_MSIX_CAP 0x80 952 #define BNXT_FLAG_RFS 0x100 953 #define BNXT_FLAG_SHARED_RINGS 0x200 954 #define BNXT_FLAG_PORT_STATS 0x400 955 #define BNXT_FLAG_EEE_CAP 0x1000 956 #define BNXT_FLAG_CHIP_NITRO_A0 0x1000000 957 958 #define BNXT_FLAG_ALL_CONFIG_FEATS (BNXT_FLAG_TPA | \ 959 BNXT_FLAG_RFS | \ 960 BNXT_FLAG_STRIP_VLAN) 961 962 #define BNXT_PF(bp) (!((bp)->flags & BNXT_FLAG_VF)) 963 #define BNXT_VF(bp) ((bp)->flags & BNXT_FLAG_VF) 964 #define BNXT_NPAR(bp) ((bp)->port_partition_type) 965 #define BNXT_SINGLE_PF(bp) (BNXT_PF(bp) && !BNXT_NPAR(bp)) 966 #define BNXT_CHIP_TYPE_NITRO_A0(bp) ((bp)->flags & BNXT_FLAG_CHIP_NITRO_A0) 967 968 struct bnxt_napi **bnapi; 969 970 struct bnxt_rx_ring_info *rx_ring; 971 struct bnxt_tx_ring_info *tx_ring; 972 973 struct sk_buff * (*gro_func)(struct bnxt_tpa_info *, int, int, 974 struct sk_buff *); 975 976 u32 rx_buf_size; 977 u32 rx_buf_use_size; /* useable size */ 978 u32 rx_ring_size; 979 u32 rx_agg_ring_size; 980 u32 rx_copy_thresh; 981 u32 rx_ring_mask; 982 u32 rx_agg_ring_mask; 983 int rx_nr_pages; 984 int rx_agg_nr_pages; 985 int rx_nr_rings; 986 int rsscos_nr_ctxs; 987 988 u32 tx_ring_size; 989 u32 tx_ring_mask; 990 int tx_nr_pages; 991 int tx_nr_rings; 992 int tx_nr_rings_per_tc; 993 994 int tx_wake_thresh; 995 int tx_push_thresh; 996 int tx_push_size; 997 998 u32 cp_ring_size; 999 u32 cp_ring_mask; 1000 u32 cp_bit; 1001 int cp_nr_pages; 1002 int cp_nr_rings; 1003 1004 int num_stat_ctxs; 1005 1006 /* grp_info indexed by completion ring index */ 1007 struct bnxt_ring_grp_info *grp_info; 1008 struct bnxt_vnic_info *vnic_info; 1009 int nr_vnics; 1010 1011 u8 max_tc; 1012 struct bnxt_queue_info q_info[BNXT_MAX_QUEUE]; 1013 1014 unsigned int current_interval; 1015 #define BNXT_TIMER_INTERVAL HZ 1016 1017 struct timer_list timer; 1018 1019 unsigned long state; 1020 #define BNXT_STATE_OPEN 0 1021 #define BNXT_STATE_IN_SP_TASK 1 1022 #define BNXT_STATE_FN_RST_DONE 2 1023 1024 struct bnxt_irq *irq_tbl; 1025 u8 mac_addr[ETH_ALEN]; 1026 1027 u32 msg_enable; 1028 1029 u32 hwrm_spec_code; 1030 u16 hwrm_cmd_seq; 1031 u32 hwrm_intr_seq_id; 1032 void *hwrm_cmd_resp_addr; 1033 dma_addr_t hwrm_cmd_resp_dma_addr; 1034 void *hwrm_dbg_resp_addr; 1035 dma_addr_t hwrm_dbg_resp_dma_addr; 1036 #define HWRM_DBG_REG_BUF_SIZE 128 1037 1038 struct rx_port_stats *hw_rx_port_stats; 1039 struct tx_port_stats *hw_tx_port_stats; 1040 dma_addr_t hw_rx_port_stats_map; 1041 dma_addr_t hw_tx_port_stats_map; 1042 int hw_port_stats_size; 1043 1044 u16 hwrm_max_req_len; 1045 int hwrm_cmd_timeout; 1046 struct mutex hwrm_cmd_lock; /* serialize hwrm messages */ 1047 struct hwrm_ver_get_output ver_resp; 1048 #define FW_VER_STR_LEN 32 1049 #define BC_HWRM_STR_LEN 21 1050 #define PHY_VER_STR_LEN (FW_VER_STR_LEN - BC_HWRM_STR_LEN) 1051 char fw_ver_str[FW_VER_STR_LEN]; 1052 __be16 vxlan_port; 1053 u8 vxlan_port_cnt; 1054 __le16 vxlan_fw_dst_port_id; 1055 __be16 nge_port; 1056 u8 nge_port_cnt; 1057 __le16 nge_fw_dst_port_id; 1058 u8 port_partition_type; 1059 1060 u16 rx_coal_ticks; 1061 u16 rx_coal_ticks_irq; 1062 u16 rx_coal_bufs; 1063 u16 rx_coal_bufs_irq; 1064 u16 tx_coal_ticks; 1065 u16 tx_coal_ticks_irq; 1066 u16 tx_coal_bufs; 1067 u16 tx_coal_bufs_irq; 1068 1069 #define BNXT_USEC_TO_COAL_TIMER(x) ((x) * 25 / 2) 1070 1071 u32 stats_coal_ticks; 1072 #define BNXT_DEF_STATS_COAL_TICKS 1000000 1073 #define BNXT_MIN_STATS_COAL_TICKS 250000 1074 #define BNXT_MAX_STATS_COAL_TICKS 1000000 1075 1076 struct work_struct sp_task; 1077 unsigned long sp_event; 1078 #define BNXT_RX_MASK_SP_EVENT 0 1079 #define BNXT_RX_NTP_FLTR_SP_EVENT 1 1080 #define BNXT_LINK_CHNG_SP_EVENT 2 1081 #define BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT 3 1082 #define BNXT_VXLAN_ADD_PORT_SP_EVENT 4 1083 #define BNXT_VXLAN_DEL_PORT_SP_EVENT 5 1084 #define BNXT_RESET_TASK_SP_EVENT 6 1085 #define BNXT_RST_RING_SP_EVENT 7 1086 #define BNXT_HWRM_PF_UNLOAD_SP_EVENT 8 1087 #define BNXT_PERIODIC_STATS_SP_EVENT 9 1088 #define BNXT_HWRM_PORT_MODULE_SP_EVENT 10 1089 #define BNXT_RESET_TASK_SILENT_SP_EVENT 11 1090 #define BNXT_GENEVE_ADD_PORT_SP_EVENT 12 1091 #define BNXT_GENEVE_DEL_PORT_SP_EVENT 13 1092 1093 struct bnxt_pf_info pf; 1094 #ifdef CONFIG_BNXT_SRIOV 1095 int nr_vfs; 1096 struct bnxt_vf_info vf; 1097 wait_queue_head_t sriov_cfg_wait; 1098 bool sriov_cfg; 1099 #define BNXT_SRIOV_CFG_WAIT_TMO msecs_to_jiffies(10000) 1100 #endif 1101 1102 #define BNXT_NTP_FLTR_MAX_FLTR 4096 1103 #define BNXT_NTP_FLTR_HASH_SIZE 512 1104 #define BNXT_NTP_FLTR_HASH_MASK (BNXT_NTP_FLTR_HASH_SIZE - 1) 1105 struct hlist_head ntp_fltr_hash_tbl[BNXT_NTP_FLTR_HASH_SIZE]; 1106 spinlock_t ntp_fltr_lock; /* for hash table add, del */ 1107 1108 unsigned long *ntp_fltr_bmap; 1109 int ntp_fltr_count; 1110 1111 struct bnxt_link_info link_info; 1112 struct ethtool_eee eee; 1113 u32 lpi_tmr_lo; 1114 u32 lpi_tmr_hi; 1115 }; 1116 1117 #ifdef CONFIG_NET_RX_BUSY_POLL 1118 static inline void bnxt_enable_poll(struct bnxt_napi *bnapi) 1119 { 1120 atomic_set(&bnapi->poll_state, BNXT_STATE_IDLE); 1121 } 1122 1123 /* called from the NAPI poll routine to get ownership of a bnapi */ 1124 static inline bool bnxt_lock_napi(struct bnxt_napi *bnapi) 1125 { 1126 int rc = atomic_cmpxchg(&bnapi->poll_state, BNXT_STATE_IDLE, 1127 BNXT_STATE_NAPI); 1128 1129 return rc == BNXT_STATE_IDLE; 1130 } 1131 1132 static inline void bnxt_unlock_napi(struct bnxt_napi *bnapi) 1133 { 1134 atomic_set(&bnapi->poll_state, BNXT_STATE_IDLE); 1135 } 1136 1137 /* called from the busy poll routine to get ownership of a bnapi */ 1138 static inline bool bnxt_lock_poll(struct bnxt_napi *bnapi) 1139 { 1140 int rc = atomic_cmpxchg(&bnapi->poll_state, BNXT_STATE_IDLE, 1141 BNXT_STATE_POLL); 1142 1143 return rc == BNXT_STATE_IDLE; 1144 } 1145 1146 static inline void bnxt_unlock_poll(struct bnxt_napi *bnapi) 1147 { 1148 atomic_set(&bnapi->poll_state, BNXT_STATE_IDLE); 1149 } 1150 1151 static inline bool bnxt_busy_polling(struct bnxt_napi *bnapi) 1152 { 1153 return atomic_read(&bnapi->poll_state) == BNXT_STATE_POLL; 1154 } 1155 1156 static inline void bnxt_disable_poll(struct bnxt_napi *bnapi) 1157 { 1158 int old; 1159 1160 while (1) { 1161 old = atomic_cmpxchg(&bnapi->poll_state, BNXT_STATE_IDLE, 1162 BNXT_STATE_DISABLE); 1163 if (old == BNXT_STATE_IDLE) 1164 break; 1165 usleep_range(500, 5000); 1166 } 1167 } 1168 1169 #else 1170 1171 static inline void bnxt_enable_poll(struct bnxt_napi *bnapi) 1172 { 1173 } 1174 1175 static inline bool bnxt_lock_napi(struct bnxt_napi *bnapi) 1176 { 1177 return true; 1178 } 1179 1180 static inline void bnxt_unlock_napi(struct bnxt_napi *bnapi) 1181 { 1182 } 1183 1184 static inline bool bnxt_lock_poll(struct bnxt_napi *bnapi) 1185 { 1186 return false; 1187 } 1188 1189 static inline void bnxt_unlock_poll(struct bnxt_napi *bnapi) 1190 { 1191 } 1192 1193 static inline bool bnxt_busy_polling(struct bnxt_napi *bnapi) 1194 { 1195 return false; 1196 } 1197 1198 static inline void bnxt_disable_poll(struct bnxt_napi *bnapi) 1199 { 1200 } 1201 1202 #endif 1203 1204 #define I2C_DEV_ADDR_A0 0xa0 1205 #define I2C_DEV_ADDR_A2 0xa2 1206 #define SFP_EEPROM_SFF_8472_COMP_ADDR 0x5e 1207 #define SFP_EEPROM_SFF_8472_COMP_SIZE 1 1208 #define SFF_MODULE_ID_SFP 0x3 1209 #define SFF_MODULE_ID_QSFP 0xc 1210 #define SFF_MODULE_ID_QSFP_PLUS 0xd 1211 #define SFF_MODULE_ID_QSFP28 0x11 1212 #define BNXT_MAX_PHY_I2C_RESP_SIZE 64 1213 1214 void bnxt_set_ring_params(struct bnxt *); 1215 void bnxt_hwrm_cmd_hdr_init(struct bnxt *, void *, u16, u16, u16); 1216 int _hwrm_send_message(struct bnxt *, void *, u32, int); 1217 int hwrm_send_message(struct bnxt *, void *, u32, int); 1218 int hwrm_send_message_silent(struct bnxt *, void *, u32, int); 1219 int bnxt_hwrm_set_coal(struct bnxt *); 1220 int bnxt_hwrm_func_qcaps(struct bnxt *); 1221 int bnxt_hwrm_set_pause(struct bnxt *); 1222 int bnxt_hwrm_set_link_setting(struct bnxt *, bool, bool); 1223 int bnxt_hwrm_fw_set_time(struct bnxt *); 1224 int bnxt_open_nic(struct bnxt *, bool, bool); 1225 int bnxt_close_nic(struct bnxt *, bool, bool); 1226 int bnxt_get_max_rings(struct bnxt *, int *, int *, bool); 1227 #endif 1228