1 /* Broadcom NetXtreme-C/E network driver. 2 * 3 * Copyright (c) 2014-2016 Broadcom Corporation 4 * Copyright (c) 2016-2018 Broadcom Limited 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation. 9 */ 10 11 #ifndef BNXT_H 12 #define BNXT_H 13 14 #define DRV_MODULE_NAME "bnxt_en" 15 16 /* DO NOT CHANGE DRV_VER_* defines 17 * FIXME: Delete them 18 */ 19 #define DRV_VER_MAJ 1 20 #define DRV_VER_MIN 10 21 #define DRV_VER_UPD 2 22 23 #include <linux/ethtool.h> 24 #include <linux/interrupt.h> 25 #include <linux/rhashtable.h> 26 #include <linux/crash_dump.h> 27 #include <net/devlink.h> 28 #include <net/dst_metadata.h> 29 #include <net/xdp.h> 30 #include <linux/dim.h> 31 #include <linux/io-64-nonatomic-lo-hi.h> 32 #ifdef CONFIG_TEE_BNXT_FW 33 #include <linux/firmware/broadcom/tee_bnxt_fw.h> 34 #endif 35 36 extern struct list_head bnxt_block_cb_list; 37 38 struct page_pool; 39 40 struct tx_bd { 41 __le32 tx_bd_len_flags_type; 42 #define TX_BD_TYPE (0x3f << 0) 43 #define TX_BD_TYPE_SHORT_TX_BD (0x00 << 0) 44 #define TX_BD_TYPE_LONG_TX_BD (0x10 << 0) 45 #define TX_BD_FLAGS_PACKET_END (1 << 6) 46 #define TX_BD_FLAGS_NO_CMPL (1 << 7) 47 #define TX_BD_FLAGS_BD_CNT (0x1f << 8) 48 #define TX_BD_FLAGS_BD_CNT_SHIFT 8 49 #define TX_BD_FLAGS_LHINT (3 << 13) 50 #define TX_BD_FLAGS_LHINT_SHIFT 13 51 #define TX_BD_FLAGS_LHINT_512_AND_SMALLER (0 << 13) 52 #define TX_BD_FLAGS_LHINT_512_TO_1023 (1 << 13) 53 #define TX_BD_FLAGS_LHINT_1024_TO_2047 (2 << 13) 54 #define TX_BD_FLAGS_LHINT_2048_AND_LARGER (3 << 13) 55 #define TX_BD_FLAGS_COAL_NOW (1 << 15) 56 #define TX_BD_LEN (0xffff << 16) 57 #define TX_BD_LEN_SHIFT 16 58 59 u32 tx_bd_opaque; 60 __le64 tx_bd_haddr; 61 } __packed; 62 63 struct tx_bd_ext { 64 __le32 tx_bd_hsize_lflags; 65 #define TX_BD_FLAGS_TCP_UDP_CHKSUM (1 << 0) 66 #define TX_BD_FLAGS_IP_CKSUM (1 << 1) 67 #define TX_BD_FLAGS_NO_CRC (1 << 2) 68 #define TX_BD_FLAGS_STAMP (1 << 3) 69 #define TX_BD_FLAGS_T_IP_CHKSUM (1 << 4) 70 #define TX_BD_FLAGS_LSO (1 << 5) 71 #define TX_BD_FLAGS_IPID_FMT (1 << 6) 72 #define TX_BD_FLAGS_T_IPID (1 << 7) 73 #define TX_BD_HSIZE (0xff << 16) 74 #define TX_BD_HSIZE_SHIFT 16 75 76 __le32 tx_bd_mss; 77 __le32 tx_bd_cfa_action; 78 #define TX_BD_CFA_ACTION (0xffff << 16) 79 #define TX_BD_CFA_ACTION_SHIFT 16 80 81 __le32 tx_bd_cfa_meta; 82 #define TX_BD_CFA_META_MASK 0xfffffff 83 #define TX_BD_CFA_META_VID_MASK 0xfff 84 #define TX_BD_CFA_META_PRI_MASK (0xf << 12) 85 #define TX_BD_CFA_META_PRI_SHIFT 12 86 #define TX_BD_CFA_META_TPID_MASK (3 << 16) 87 #define TX_BD_CFA_META_TPID_SHIFT 16 88 #define TX_BD_CFA_META_KEY (0xf << 28) 89 #define TX_BD_CFA_META_KEY_SHIFT 28 90 #define TX_BD_CFA_META_KEY_VLAN (1 << 28) 91 }; 92 93 #define BNXT_TX_PTP_IS_SET(lflags) ((lflags) & cpu_to_le32(TX_BD_FLAGS_STAMP)) 94 95 struct rx_bd { 96 __le32 rx_bd_len_flags_type; 97 #define RX_BD_TYPE (0x3f << 0) 98 #define RX_BD_TYPE_RX_PACKET_BD 0x4 99 #define RX_BD_TYPE_RX_BUFFER_BD 0x5 100 #define RX_BD_TYPE_RX_AGG_BD 0x6 101 #define RX_BD_TYPE_16B_BD_SIZE (0 << 4) 102 #define RX_BD_TYPE_32B_BD_SIZE (1 << 4) 103 #define RX_BD_TYPE_48B_BD_SIZE (2 << 4) 104 #define RX_BD_TYPE_64B_BD_SIZE (3 << 4) 105 #define RX_BD_FLAGS_SOP (1 << 6) 106 #define RX_BD_FLAGS_EOP (1 << 7) 107 #define RX_BD_FLAGS_BUFFERS (3 << 8) 108 #define RX_BD_FLAGS_1_BUFFER_PACKET (0 << 8) 109 #define RX_BD_FLAGS_2_BUFFER_PACKET (1 << 8) 110 #define RX_BD_FLAGS_3_BUFFER_PACKET (2 << 8) 111 #define RX_BD_FLAGS_4_BUFFER_PACKET (3 << 8) 112 #define RX_BD_LEN (0xffff << 16) 113 #define RX_BD_LEN_SHIFT 16 114 115 u32 rx_bd_opaque; 116 __le64 rx_bd_haddr; 117 }; 118 119 struct tx_cmp { 120 __le32 tx_cmp_flags_type; 121 #define CMP_TYPE (0x3f << 0) 122 #define CMP_TYPE_TX_L2_CMP 0 123 #define CMP_TYPE_RX_L2_CMP 17 124 #define CMP_TYPE_RX_AGG_CMP 18 125 #define CMP_TYPE_RX_L2_TPA_START_CMP 19 126 #define CMP_TYPE_RX_L2_TPA_END_CMP 21 127 #define CMP_TYPE_RX_TPA_AGG_CMP 22 128 #define CMP_TYPE_STATUS_CMP 32 129 #define CMP_TYPE_REMOTE_DRIVER_REQ 34 130 #define CMP_TYPE_REMOTE_DRIVER_RESP 36 131 #define CMP_TYPE_ERROR_STATUS 48 132 #define CMPL_BASE_TYPE_STAT_EJECT 0x1aUL 133 #define CMPL_BASE_TYPE_HWRM_DONE 0x20UL 134 #define CMPL_BASE_TYPE_HWRM_FWD_REQ 0x22UL 135 #define CMPL_BASE_TYPE_HWRM_FWD_RESP 0x24UL 136 #define CMPL_BASE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 137 138 #define TX_CMP_FLAGS_ERROR (1 << 6) 139 #define TX_CMP_FLAGS_PUSH (1 << 7) 140 141 u32 tx_cmp_opaque; 142 __le32 tx_cmp_errors_v; 143 #define TX_CMP_V (1 << 0) 144 #define TX_CMP_ERRORS_BUFFER_ERROR (7 << 1) 145 #define TX_CMP_ERRORS_BUFFER_ERROR_NO_ERROR 0 146 #define TX_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT 2 147 #define TX_CMP_ERRORS_BUFFER_ERROR_INVALID_STAG 4 148 #define TX_CMP_ERRORS_BUFFER_ERROR_STAG_BOUNDS 5 149 #define TX_CMP_ERRORS_ZERO_LENGTH_PKT (1 << 4) 150 #define TX_CMP_ERRORS_EXCESSIVE_BD_LEN (1 << 5) 151 #define TX_CMP_ERRORS_DMA_ERROR (1 << 6) 152 #define TX_CMP_ERRORS_HINT_TOO_SHORT (1 << 7) 153 154 __le32 tx_cmp_unsed_3; 155 }; 156 157 struct rx_cmp { 158 __le32 rx_cmp_len_flags_type; 159 #define RX_CMP_CMP_TYPE (0x3f << 0) 160 #define RX_CMP_FLAGS_ERROR (1 << 6) 161 #define RX_CMP_FLAGS_PLACEMENT (7 << 7) 162 #define RX_CMP_FLAGS_RSS_VALID (1 << 10) 163 #define RX_CMP_FLAGS_UNUSED (1 << 11) 164 #define RX_CMP_FLAGS_ITYPES_SHIFT 12 165 #define RX_CMP_FLAGS_ITYPES_MASK 0xf000 166 #define RX_CMP_FLAGS_ITYPE_UNKNOWN (0 << 12) 167 #define RX_CMP_FLAGS_ITYPE_IP (1 << 12) 168 #define RX_CMP_FLAGS_ITYPE_TCP (2 << 12) 169 #define RX_CMP_FLAGS_ITYPE_UDP (3 << 12) 170 #define RX_CMP_FLAGS_ITYPE_FCOE (4 << 12) 171 #define RX_CMP_FLAGS_ITYPE_ROCE (5 << 12) 172 #define RX_CMP_FLAGS_ITYPE_PTP_WO_TS (8 << 12) 173 #define RX_CMP_FLAGS_ITYPE_PTP_W_TS (9 << 12) 174 #define RX_CMP_LEN (0xffff << 16) 175 #define RX_CMP_LEN_SHIFT 16 176 177 u32 rx_cmp_opaque; 178 __le32 rx_cmp_misc_v1; 179 #define RX_CMP_V1 (1 << 0) 180 #define RX_CMP_AGG_BUFS (0x1f << 1) 181 #define RX_CMP_AGG_BUFS_SHIFT 1 182 #define RX_CMP_RSS_HASH_TYPE (0x7f << 9) 183 #define RX_CMP_RSS_HASH_TYPE_SHIFT 9 184 #define RX_CMP_PAYLOAD_OFFSET (0xff << 16) 185 #define RX_CMP_PAYLOAD_OFFSET_SHIFT 16 186 187 __le32 rx_cmp_rss_hash; 188 }; 189 190 #define RX_CMP_HASH_VALID(rxcmp) \ 191 ((rxcmp)->rx_cmp_len_flags_type & cpu_to_le32(RX_CMP_FLAGS_RSS_VALID)) 192 193 #define RSS_PROFILE_ID_MASK 0x1f 194 195 #define RX_CMP_HASH_TYPE(rxcmp) \ 196 (((le32_to_cpu((rxcmp)->rx_cmp_misc_v1) & RX_CMP_RSS_HASH_TYPE) >>\ 197 RX_CMP_RSS_HASH_TYPE_SHIFT) & RSS_PROFILE_ID_MASK) 198 199 struct rx_cmp_ext { 200 __le32 rx_cmp_flags2; 201 #define RX_CMP_FLAGS2_IP_CS_CALC 0x1 202 #define RX_CMP_FLAGS2_L4_CS_CALC (0x1 << 1) 203 #define RX_CMP_FLAGS2_T_IP_CS_CALC (0x1 << 2) 204 #define RX_CMP_FLAGS2_T_L4_CS_CALC (0x1 << 3) 205 #define RX_CMP_FLAGS2_META_FORMAT_VLAN (0x1 << 4) 206 __le32 rx_cmp_meta_data; 207 #define RX_CMP_FLAGS2_METADATA_TCI_MASK 0xffff 208 #define RX_CMP_FLAGS2_METADATA_VID_MASK 0xfff 209 #define RX_CMP_FLAGS2_METADATA_TPID_MASK 0xffff0000 210 #define RX_CMP_FLAGS2_METADATA_TPID_SFT 16 211 __le32 rx_cmp_cfa_code_errors_v2; 212 #define RX_CMP_V (1 << 0) 213 #define RX_CMPL_ERRORS_MASK (0x7fff << 1) 214 #define RX_CMPL_ERRORS_SFT 1 215 #define RX_CMPL_ERRORS_BUFFER_ERROR_MASK (0x7 << 1) 216 #define RX_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0 << 1) 217 #define RX_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT (0x1 << 1) 218 #define RX_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP (0x2 << 1) 219 #define RX_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3 << 1) 220 #define RX_CMPL_ERRORS_IP_CS_ERROR (0x1 << 4) 221 #define RX_CMPL_ERRORS_L4_CS_ERROR (0x1 << 5) 222 #define RX_CMPL_ERRORS_T_IP_CS_ERROR (0x1 << 6) 223 #define RX_CMPL_ERRORS_T_L4_CS_ERROR (0x1 << 7) 224 #define RX_CMPL_ERRORS_CRC_ERROR (0x1 << 8) 225 #define RX_CMPL_ERRORS_T_PKT_ERROR_MASK (0x7 << 9) 226 #define RX_CMPL_ERRORS_T_PKT_ERROR_NO_ERROR (0x0 << 9) 227 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION (0x1 << 9) 228 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN (0x2 << 9) 229 #define RX_CMPL_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR (0x3 << 9) 230 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR (0x4 << 9) 231 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR (0x5 << 9) 232 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL (0x6 << 9) 233 #define RX_CMPL_ERRORS_PKT_ERROR_MASK (0xf << 12) 234 #define RX_CMPL_ERRORS_PKT_ERROR_NO_ERROR (0x0 << 12) 235 #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_VERSION (0x1 << 12) 236 #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN (0x2 << 12) 237 #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_TTL (0x3 << 12) 238 #define RX_CMPL_ERRORS_PKT_ERROR_IP_TOTAL_ERROR (0x4 << 12) 239 #define RX_CMPL_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR (0x5 << 12) 240 #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN (0x6 << 12) 241 #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL (0x7 << 12) 242 #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN (0x8 << 12) 243 244 #define RX_CMPL_CFA_CODE_MASK (0xffff << 16) 245 #define RX_CMPL_CFA_CODE_SFT 16 246 247 __le32 rx_cmp_timestamp; 248 }; 249 250 #define RX_CMP_L2_ERRORS \ 251 cpu_to_le32(RX_CMPL_ERRORS_BUFFER_ERROR_MASK | RX_CMPL_ERRORS_CRC_ERROR) 252 253 #define RX_CMP_L4_CS_BITS \ 254 (cpu_to_le32(RX_CMP_FLAGS2_L4_CS_CALC | RX_CMP_FLAGS2_T_L4_CS_CALC)) 255 256 #define RX_CMP_L4_CS_ERR_BITS \ 257 (cpu_to_le32(RX_CMPL_ERRORS_L4_CS_ERROR | RX_CMPL_ERRORS_T_L4_CS_ERROR)) 258 259 #define RX_CMP_L4_CS_OK(rxcmp1) \ 260 (((rxcmp1)->rx_cmp_flags2 & RX_CMP_L4_CS_BITS) && \ 261 !((rxcmp1)->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS)) 262 263 #define RX_CMP_ENCAP(rxcmp1) \ 264 ((le32_to_cpu((rxcmp1)->rx_cmp_flags2) & \ 265 RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3) 266 267 #define RX_CMP_CFA_CODE(rxcmpl1) \ 268 ((le32_to_cpu((rxcmpl1)->rx_cmp_cfa_code_errors_v2) & \ 269 RX_CMPL_CFA_CODE_MASK) >> RX_CMPL_CFA_CODE_SFT) 270 271 struct rx_agg_cmp { 272 __le32 rx_agg_cmp_len_flags_type; 273 #define RX_AGG_CMP_TYPE (0x3f << 0) 274 #define RX_AGG_CMP_LEN (0xffff << 16) 275 #define RX_AGG_CMP_LEN_SHIFT 16 276 u32 rx_agg_cmp_opaque; 277 __le32 rx_agg_cmp_v; 278 #define RX_AGG_CMP_V (1 << 0) 279 #define RX_AGG_CMP_AGG_ID (0xffff << 16) 280 #define RX_AGG_CMP_AGG_ID_SHIFT 16 281 __le32 rx_agg_cmp_unused; 282 }; 283 284 #define TPA_AGG_AGG_ID(rx_agg) \ 285 ((le32_to_cpu((rx_agg)->rx_agg_cmp_v) & \ 286 RX_AGG_CMP_AGG_ID) >> RX_AGG_CMP_AGG_ID_SHIFT) 287 288 struct rx_tpa_start_cmp { 289 __le32 rx_tpa_start_cmp_len_flags_type; 290 #define RX_TPA_START_CMP_TYPE (0x3f << 0) 291 #define RX_TPA_START_CMP_FLAGS (0x3ff << 6) 292 #define RX_TPA_START_CMP_FLAGS_SHIFT 6 293 #define RX_TPA_START_CMP_FLAGS_ERROR (0x1 << 6) 294 #define RX_TPA_START_CMP_FLAGS_PLACEMENT (0x7 << 7) 295 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_SHIFT 7 296 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_JUMBO (0x1 << 7) 297 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_HDS (0x2 << 7) 298 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_GRO_JUMBO (0x5 << 7) 299 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_GRO_HDS (0x6 << 7) 300 #define RX_TPA_START_CMP_FLAGS_RSS_VALID (0x1 << 10) 301 #define RX_TPA_START_CMP_FLAGS_TIMESTAMP (0x1 << 11) 302 #define RX_TPA_START_CMP_FLAGS_ITYPES (0xf << 12) 303 #define RX_TPA_START_CMP_FLAGS_ITYPES_SHIFT 12 304 #define RX_TPA_START_CMP_FLAGS_ITYPE_TCP (0x2 << 12) 305 #define RX_TPA_START_CMP_LEN (0xffff << 16) 306 #define RX_TPA_START_CMP_LEN_SHIFT 16 307 308 u32 rx_tpa_start_cmp_opaque; 309 __le32 rx_tpa_start_cmp_misc_v1; 310 #define RX_TPA_START_CMP_V1 (0x1 << 0) 311 #define RX_TPA_START_CMP_RSS_HASH_TYPE (0x7f << 9) 312 #define RX_TPA_START_CMP_RSS_HASH_TYPE_SHIFT 9 313 #define RX_TPA_START_CMP_AGG_ID (0x7f << 25) 314 #define RX_TPA_START_CMP_AGG_ID_SHIFT 25 315 #define RX_TPA_START_CMP_AGG_ID_P5 (0xffff << 16) 316 #define RX_TPA_START_CMP_AGG_ID_SHIFT_P5 16 317 318 __le32 rx_tpa_start_cmp_rss_hash; 319 }; 320 321 #define TPA_START_HASH_VALID(rx_tpa_start) \ 322 ((rx_tpa_start)->rx_tpa_start_cmp_len_flags_type & \ 323 cpu_to_le32(RX_TPA_START_CMP_FLAGS_RSS_VALID)) 324 325 #define TPA_START_HASH_TYPE(rx_tpa_start) \ 326 (((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) & \ 327 RX_TPA_START_CMP_RSS_HASH_TYPE) >> \ 328 RX_TPA_START_CMP_RSS_HASH_TYPE_SHIFT) & RSS_PROFILE_ID_MASK) 329 330 #define TPA_START_AGG_ID(rx_tpa_start) \ 331 ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) & \ 332 RX_TPA_START_CMP_AGG_ID) >> RX_TPA_START_CMP_AGG_ID_SHIFT) 333 334 #define TPA_START_AGG_ID_P5(rx_tpa_start) \ 335 ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) & \ 336 RX_TPA_START_CMP_AGG_ID_P5) >> RX_TPA_START_CMP_AGG_ID_SHIFT_P5) 337 338 #define TPA_START_ERROR(rx_tpa_start) \ 339 ((rx_tpa_start)->rx_tpa_start_cmp_len_flags_type & \ 340 cpu_to_le32(RX_TPA_START_CMP_FLAGS_ERROR)) 341 342 struct rx_tpa_start_cmp_ext { 343 __le32 rx_tpa_start_cmp_flags2; 344 #define RX_TPA_START_CMP_FLAGS2_IP_CS_CALC (0x1 << 0) 345 #define RX_TPA_START_CMP_FLAGS2_L4_CS_CALC (0x1 << 1) 346 #define RX_TPA_START_CMP_FLAGS2_T_IP_CS_CALC (0x1 << 2) 347 #define RX_TPA_START_CMP_FLAGS2_T_L4_CS_CALC (0x1 << 3) 348 #define RX_TPA_START_CMP_FLAGS2_IP_TYPE (0x1 << 8) 349 #define RX_TPA_START_CMP_FLAGS2_CSUM_CMPL_VALID (0x1 << 9) 350 #define RX_TPA_START_CMP_FLAGS2_EXT_META_FORMAT (0x3 << 10) 351 #define RX_TPA_START_CMP_FLAGS2_EXT_META_FORMAT_SHIFT 10 352 #define RX_TPA_START_CMP_FLAGS2_CSUM_CMPL (0xffff << 16) 353 #define RX_TPA_START_CMP_FLAGS2_CSUM_CMPL_SHIFT 16 354 355 __le32 rx_tpa_start_cmp_metadata; 356 __le32 rx_tpa_start_cmp_cfa_code_v2; 357 #define RX_TPA_START_CMP_V2 (0x1 << 0) 358 #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_MASK (0x7 << 1) 359 #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_SHIFT 1 360 #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0 << 1) 361 #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3 << 1) 362 #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_FLUSH (0x5 << 1) 363 #define RX_TPA_START_CMP_CFA_CODE (0xffff << 16) 364 #define RX_TPA_START_CMPL_CFA_CODE_SHIFT 16 365 __le32 rx_tpa_start_cmp_hdr_info; 366 }; 367 368 #define TPA_START_CFA_CODE(rx_tpa_start) \ 369 ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_cfa_code_v2) & \ 370 RX_TPA_START_CMP_CFA_CODE) >> RX_TPA_START_CMPL_CFA_CODE_SHIFT) 371 372 #define TPA_START_IS_IPV6(rx_tpa_start) \ 373 (!!((rx_tpa_start)->rx_tpa_start_cmp_flags2 & \ 374 cpu_to_le32(RX_TPA_START_CMP_FLAGS2_IP_TYPE))) 375 376 #define TPA_START_ERROR_CODE(rx_tpa_start) \ 377 ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_cfa_code_v2) & \ 378 RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_MASK) >> \ 379 RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_SHIFT) 380 381 struct rx_tpa_end_cmp { 382 __le32 rx_tpa_end_cmp_len_flags_type; 383 #define RX_TPA_END_CMP_TYPE (0x3f << 0) 384 #define RX_TPA_END_CMP_FLAGS (0x3ff << 6) 385 #define RX_TPA_END_CMP_FLAGS_SHIFT 6 386 #define RX_TPA_END_CMP_FLAGS_PLACEMENT (0x7 << 7) 387 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_SHIFT 7 388 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_JUMBO (0x1 << 7) 389 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_HDS (0x2 << 7) 390 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_JUMBO (0x5 << 7) 391 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_HDS (0x6 << 7) 392 #define RX_TPA_END_CMP_FLAGS_RSS_VALID (0x1 << 10) 393 #define RX_TPA_END_CMP_FLAGS_ITYPES (0xf << 12) 394 #define RX_TPA_END_CMP_FLAGS_ITYPES_SHIFT 12 395 #define RX_TPA_END_CMP_FLAGS_ITYPE_TCP (0x2 << 12) 396 #define RX_TPA_END_CMP_LEN (0xffff << 16) 397 #define RX_TPA_END_CMP_LEN_SHIFT 16 398 399 u32 rx_tpa_end_cmp_opaque; 400 __le32 rx_tpa_end_cmp_misc_v1; 401 #define RX_TPA_END_CMP_V1 (0x1 << 0) 402 #define RX_TPA_END_CMP_AGG_BUFS (0x3f << 1) 403 #define RX_TPA_END_CMP_AGG_BUFS_SHIFT 1 404 #define RX_TPA_END_CMP_TPA_SEGS (0xff << 8) 405 #define RX_TPA_END_CMP_TPA_SEGS_SHIFT 8 406 #define RX_TPA_END_CMP_PAYLOAD_OFFSET (0xff << 16) 407 #define RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT 16 408 #define RX_TPA_END_CMP_AGG_ID (0x7f << 25) 409 #define RX_TPA_END_CMP_AGG_ID_SHIFT 25 410 #define RX_TPA_END_CMP_AGG_ID_P5 (0xffff << 16) 411 #define RX_TPA_END_CMP_AGG_ID_SHIFT_P5 16 412 413 __le32 rx_tpa_end_cmp_tsdelta; 414 #define RX_TPA_END_GRO_TS (0x1 << 31) 415 }; 416 417 #define TPA_END_AGG_ID(rx_tpa_end) \ 418 ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \ 419 RX_TPA_END_CMP_AGG_ID) >> RX_TPA_END_CMP_AGG_ID_SHIFT) 420 421 #define TPA_END_AGG_ID_P5(rx_tpa_end) \ 422 ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \ 423 RX_TPA_END_CMP_AGG_ID_P5) >> RX_TPA_END_CMP_AGG_ID_SHIFT_P5) 424 425 #define TPA_END_PAYLOAD_OFF(rx_tpa_end) \ 426 ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \ 427 RX_TPA_END_CMP_PAYLOAD_OFFSET) >> RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT) 428 429 #define TPA_END_AGG_BUFS(rx_tpa_end) \ 430 ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \ 431 RX_TPA_END_CMP_AGG_BUFS) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT) 432 433 #define TPA_END_TPA_SEGS(rx_tpa_end) \ 434 ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \ 435 RX_TPA_END_CMP_TPA_SEGS) >> RX_TPA_END_CMP_TPA_SEGS_SHIFT) 436 437 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_ANY_GRO \ 438 cpu_to_le32(RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_JUMBO & \ 439 RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_HDS) 440 441 #define TPA_END_GRO(rx_tpa_end) \ 442 ((rx_tpa_end)->rx_tpa_end_cmp_len_flags_type & \ 443 RX_TPA_END_CMP_FLAGS_PLACEMENT_ANY_GRO) 444 445 #define TPA_END_GRO_TS(rx_tpa_end) \ 446 (!!((rx_tpa_end)->rx_tpa_end_cmp_tsdelta & \ 447 cpu_to_le32(RX_TPA_END_GRO_TS))) 448 449 struct rx_tpa_end_cmp_ext { 450 __le32 rx_tpa_end_cmp_dup_acks; 451 #define RX_TPA_END_CMP_TPA_DUP_ACKS (0xf << 0) 452 #define RX_TPA_END_CMP_PAYLOAD_OFFSET_P5 (0xff << 16) 453 #define RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT_P5 16 454 #define RX_TPA_END_CMP_AGG_BUFS_P5 (0xff << 24) 455 #define RX_TPA_END_CMP_AGG_BUFS_SHIFT_P5 24 456 457 __le32 rx_tpa_end_cmp_seg_len; 458 #define RX_TPA_END_CMP_TPA_SEG_LEN (0xffff << 0) 459 460 __le32 rx_tpa_end_cmp_errors_v2; 461 #define RX_TPA_END_CMP_V2 (0x1 << 0) 462 #define RX_TPA_END_CMP_ERRORS (0x3 << 1) 463 #define RX_TPA_END_CMP_ERRORS_P5 (0x7 << 1) 464 #define RX_TPA_END_CMPL_ERRORS_SHIFT 1 465 #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0 << 1) 466 #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_NOT_ON_CHIP (0x2 << 1) 467 #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3 << 1) 468 #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_RSV_ERROR (0x4 << 1) 469 #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_FLUSH (0x5 << 1) 470 471 u32 rx_tpa_end_cmp_start_opaque; 472 }; 473 474 #define TPA_END_ERRORS(rx_tpa_end_ext) \ 475 ((rx_tpa_end_ext)->rx_tpa_end_cmp_errors_v2 & \ 476 cpu_to_le32(RX_TPA_END_CMP_ERRORS)) 477 478 #define TPA_END_PAYLOAD_OFF_P5(rx_tpa_end_ext) \ 479 ((le32_to_cpu((rx_tpa_end_ext)->rx_tpa_end_cmp_dup_acks) & \ 480 RX_TPA_END_CMP_PAYLOAD_OFFSET_P5) >> \ 481 RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT_P5) 482 483 #define TPA_END_AGG_BUFS_P5(rx_tpa_end_ext) \ 484 ((le32_to_cpu((rx_tpa_end_ext)->rx_tpa_end_cmp_dup_acks) & \ 485 RX_TPA_END_CMP_AGG_BUFS_P5) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT_P5) 486 487 #define EVENT_DATA1_RESET_NOTIFY_FATAL(data1) \ 488 (((data1) & \ 489 ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK) ==\ 490 ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_FATAL) 491 492 #define EVENT_DATA1_RECOVERY_MASTER_FUNC(data1) \ 493 !!((data1) & \ 494 ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASTER_FUNC) 495 496 #define EVENT_DATA1_RECOVERY_ENABLED(data1) \ 497 !!((data1) & \ 498 ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_RECOVERY_ENABLED) 499 500 #define BNXT_EVENT_ERROR_REPORT_TYPE(data1) \ 501 (((data1) & \ 502 ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_MASK) >>\ 503 ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_SFT) 504 505 #define BNXT_EVENT_INVALID_SIGNAL_DATA(data2) \ 506 (((data2) & \ 507 ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA2_PIN_ID_MASK) >>\ 508 ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA2_PIN_ID_SFT) 509 510 struct nqe_cn { 511 __le16 type; 512 #define NQ_CN_TYPE_MASK 0x3fUL 513 #define NQ_CN_TYPE_SFT 0 514 #define NQ_CN_TYPE_CQ_NOTIFICATION 0x30UL 515 #define NQ_CN_TYPE_LAST NQ_CN_TYPE_CQ_NOTIFICATION 516 __le16 reserved16; 517 __le32 cq_handle_low; 518 __le32 v; 519 #define NQ_CN_V 0x1UL 520 __le32 cq_handle_high; 521 }; 522 523 #define DB_IDX_MASK 0xffffff 524 #define DB_IDX_VALID (0x1 << 26) 525 #define DB_IRQ_DIS (0x1 << 27) 526 #define DB_KEY_TX (0x0 << 28) 527 #define DB_KEY_RX (0x1 << 28) 528 #define DB_KEY_CP (0x2 << 28) 529 #define DB_KEY_ST (0x3 << 28) 530 #define DB_KEY_TX_PUSH (0x4 << 28) 531 #define DB_LONG_TX_PUSH (0x2 << 24) 532 533 #define BNXT_MIN_ROCE_CP_RINGS 2 534 #define BNXT_MIN_ROCE_STAT_CTXS 1 535 536 /* 64-bit doorbell */ 537 #define DBR_INDEX_MASK 0x0000000000ffffffULL 538 #define DBR_XID_MASK 0x000fffff00000000ULL 539 #define DBR_XID_SFT 32 540 #define DBR_PATH_L2 (0x1ULL << 56) 541 #define DBR_TYPE_SQ (0x0ULL << 60) 542 #define DBR_TYPE_RQ (0x1ULL << 60) 543 #define DBR_TYPE_SRQ (0x2ULL << 60) 544 #define DBR_TYPE_SRQ_ARM (0x3ULL << 60) 545 #define DBR_TYPE_CQ (0x4ULL << 60) 546 #define DBR_TYPE_CQ_ARMSE (0x5ULL << 60) 547 #define DBR_TYPE_CQ_ARMALL (0x6ULL << 60) 548 #define DBR_TYPE_CQ_ARMENA (0x7ULL << 60) 549 #define DBR_TYPE_SRQ_ARMENA (0x8ULL << 60) 550 #define DBR_TYPE_CQ_CUTOFF_ACK (0x9ULL << 60) 551 #define DBR_TYPE_NQ (0xaULL << 60) 552 #define DBR_TYPE_NQ_ARM (0xbULL << 60) 553 #define DBR_TYPE_NULL (0xfULL << 60) 554 555 #define DB_PF_OFFSET_P5 0x10000 556 #define DB_VF_OFFSET_P5 0x4000 557 558 #define INVALID_HW_RING_ID ((u16)-1) 559 560 /* The hardware supports certain page sizes. Use the supported page sizes 561 * to allocate the rings. 562 */ 563 #if (PAGE_SHIFT < 12) 564 #define BNXT_PAGE_SHIFT 12 565 #elif (PAGE_SHIFT <= 13) 566 #define BNXT_PAGE_SHIFT PAGE_SHIFT 567 #elif (PAGE_SHIFT < 16) 568 #define BNXT_PAGE_SHIFT 13 569 #else 570 #define BNXT_PAGE_SHIFT 16 571 #endif 572 573 #define BNXT_PAGE_SIZE (1 << BNXT_PAGE_SHIFT) 574 575 /* The RXBD length is 16-bit so we can only support page sizes < 64K */ 576 #if (PAGE_SHIFT > 15) 577 #define BNXT_RX_PAGE_SHIFT 15 578 #else 579 #define BNXT_RX_PAGE_SHIFT PAGE_SHIFT 580 #endif 581 582 #define BNXT_RX_PAGE_SIZE (1 << BNXT_RX_PAGE_SHIFT) 583 584 #define BNXT_MAX_MTU 9500 585 #define BNXT_MAX_PAGE_MODE_MTU \ 586 ((unsigned int)PAGE_SIZE - VLAN_ETH_HLEN - NET_IP_ALIGN - \ 587 XDP_PACKET_HEADROOM) 588 589 #define BNXT_MIN_PKT_SIZE 52 590 591 #define BNXT_DEFAULT_RX_RING_SIZE 511 592 #define BNXT_DEFAULT_TX_RING_SIZE 511 593 594 #define MAX_TPA 64 595 #define MAX_TPA_P5 256 596 #define MAX_TPA_P5_MASK (MAX_TPA_P5 - 1) 597 #define MAX_TPA_SEGS_P5 0x3f 598 599 #if (BNXT_PAGE_SHIFT == 16) 600 #define MAX_RX_PAGES_AGG_ENA 1 601 #define MAX_RX_PAGES 4 602 #define MAX_RX_AGG_PAGES 4 603 #define MAX_TX_PAGES 1 604 #define MAX_CP_PAGES 16 605 #else 606 #define MAX_RX_PAGES_AGG_ENA 8 607 #define MAX_RX_PAGES 32 608 #define MAX_RX_AGG_PAGES 32 609 #define MAX_TX_PAGES 8 610 #define MAX_CP_PAGES 128 611 #endif 612 613 #define RX_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct rx_bd)) 614 #define TX_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct tx_bd)) 615 #define CP_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct tx_cmp)) 616 617 #define SW_RXBD_RING_SIZE (sizeof(struct bnxt_sw_rx_bd) * RX_DESC_CNT) 618 #define HW_RXBD_RING_SIZE (sizeof(struct rx_bd) * RX_DESC_CNT) 619 620 #define SW_RXBD_AGG_RING_SIZE (sizeof(struct bnxt_sw_rx_agg_bd) * RX_DESC_CNT) 621 622 #define SW_TXBD_RING_SIZE (sizeof(struct bnxt_sw_tx_bd) * TX_DESC_CNT) 623 #define HW_TXBD_RING_SIZE (sizeof(struct tx_bd) * TX_DESC_CNT) 624 625 #define HW_CMPD_RING_SIZE (sizeof(struct tx_cmp) * CP_DESC_CNT) 626 627 #define BNXT_MAX_RX_DESC_CNT (RX_DESC_CNT * MAX_RX_PAGES - 1) 628 #define BNXT_MAX_RX_DESC_CNT_JUM_ENA (RX_DESC_CNT * MAX_RX_PAGES_AGG_ENA - 1) 629 #define BNXT_MAX_RX_JUM_DESC_CNT (RX_DESC_CNT * MAX_RX_AGG_PAGES - 1) 630 #define BNXT_MAX_TX_DESC_CNT (TX_DESC_CNT * MAX_TX_PAGES - 1) 631 632 #define RX_RING(x) (((x) & ~(RX_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4)) 633 #define RX_IDX(x) ((x) & (RX_DESC_CNT - 1)) 634 635 #define TX_RING(x) (((x) & ~(TX_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4)) 636 #define TX_IDX(x) ((x) & (TX_DESC_CNT - 1)) 637 638 #define CP_RING(x) (((x) & ~(CP_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4)) 639 #define CP_IDX(x) ((x) & (CP_DESC_CNT - 1)) 640 641 #define TX_CMP_VALID(txcmp, raw_cons) \ 642 (!!((txcmp)->tx_cmp_errors_v & cpu_to_le32(TX_CMP_V)) == \ 643 !((raw_cons) & bp->cp_bit)) 644 645 #define RX_CMP_VALID(rxcmp1, raw_cons) \ 646 (!!((rxcmp1)->rx_cmp_cfa_code_errors_v2 & cpu_to_le32(RX_CMP_V)) ==\ 647 !((raw_cons) & bp->cp_bit)) 648 649 #define RX_AGG_CMP_VALID(agg, raw_cons) \ 650 (!!((agg)->rx_agg_cmp_v & cpu_to_le32(RX_AGG_CMP_V)) == \ 651 !((raw_cons) & bp->cp_bit)) 652 653 #define NQ_CMP_VALID(nqcmp, raw_cons) \ 654 (!!((nqcmp)->v & cpu_to_le32(NQ_CN_V)) == !((raw_cons) & bp->cp_bit)) 655 656 #define TX_CMP_TYPE(txcmp) \ 657 (le32_to_cpu((txcmp)->tx_cmp_flags_type) & CMP_TYPE) 658 659 #define RX_CMP_TYPE(rxcmp) \ 660 (le32_to_cpu((rxcmp)->rx_cmp_len_flags_type) & RX_CMP_CMP_TYPE) 661 662 #define NEXT_RX(idx) (((idx) + 1) & bp->rx_ring_mask) 663 664 #define NEXT_RX_AGG(idx) (((idx) + 1) & bp->rx_agg_ring_mask) 665 666 #define NEXT_TX(idx) (((idx) + 1) & bp->tx_ring_mask) 667 668 #define ADV_RAW_CMP(idx, n) ((idx) + (n)) 669 #define NEXT_RAW_CMP(idx) ADV_RAW_CMP(idx, 1) 670 #define RING_CMP(idx) ((idx) & bp->cp_ring_mask) 671 #define NEXT_CMP(idx) RING_CMP(ADV_RAW_CMP(idx, 1)) 672 673 #define DFLT_HWRM_CMD_TIMEOUT 500 674 675 #define BNXT_RX_EVENT 1 676 #define BNXT_AGG_EVENT 2 677 #define BNXT_TX_EVENT 4 678 #define BNXT_REDIRECT_EVENT 8 679 680 struct bnxt_sw_tx_bd { 681 union { 682 struct sk_buff *skb; 683 struct xdp_frame *xdpf; 684 }; 685 DEFINE_DMA_UNMAP_ADDR(mapping); 686 DEFINE_DMA_UNMAP_LEN(len); 687 u8 is_gso; 688 u8 is_push; 689 u8 action; 690 union { 691 unsigned short nr_frags; 692 u16 rx_prod; 693 }; 694 }; 695 696 struct bnxt_sw_rx_bd { 697 void *data; 698 u8 *data_ptr; 699 dma_addr_t mapping; 700 }; 701 702 struct bnxt_sw_rx_agg_bd { 703 struct page *page; 704 unsigned int offset; 705 dma_addr_t mapping; 706 }; 707 708 struct bnxt_mem_init { 709 u8 init_val; 710 u16 offset; 711 #define BNXT_MEM_INVALID_OFFSET 0xffff 712 u16 size; 713 }; 714 715 struct bnxt_ring_mem_info { 716 int nr_pages; 717 int page_size; 718 u16 flags; 719 #define BNXT_RMEM_VALID_PTE_FLAG 1 720 #define BNXT_RMEM_RING_PTE_FLAG 2 721 #define BNXT_RMEM_USE_FULL_PAGE_FLAG 4 722 723 u16 depth; 724 struct bnxt_mem_init *mem_init; 725 726 void **pg_arr; 727 dma_addr_t *dma_arr; 728 729 __le64 *pg_tbl; 730 dma_addr_t pg_tbl_map; 731 732 int vmem_size; 733 void **vmem; 734 }; 735 736 struct bnxt_ring_struct { 737 struct bnxt_ring_mem_info ring_mem; 738 739 u16 fw_ring_id; /* Ring id filled by Chimp FW */ 740 union { 741 u16 grp_idx; 742 u16 map_idx; /* Used by cmpl rings */ 743 }; 744 u32 handle; 745 u8 queue_id; 746 }; 747 748 struct tx_push_bd { 749 __le32 doorbell; 750 __le32 tx_bd_len_flags_type; 751 u32 tx_bd_opaque; 752 struct tx_bd_ext txbd2; 753 }; 754 755 struct tx_push_buffer { 756 struct tx_push_bd push_bd; 757 u32 data[25]; 758 }; 759 760 struct bnxt_db_info { 761 void __iomem *doorbell; 762 union { 763 u64 db_key64; 764 u32 db_key32; 765 }; 766 }; 767 768 struct bnxt_tx_ring_info { 769 struct bnxt_napi *bnapi; 770 u16 tx_prod; 771 u16 tx_cons; 772 u16 txq_index; 773 u8 kick_pending; 774 struct bnxt_db_info tx_db; 775 776 struct tx_bd *tx_desc_ring[MAX_TX_PAGES]; 777 struct bnxt_sw_tx_bd *tx_buf_ring; 778 779 dma_addr_t tx_desc_mapping[MAX_TX_PAGES]; 780 781 struct tx_push_buffer *tx_push; 782 dma_addr_t tx_push_mapping; 783 __le64 data_mapping; 784 785 #define BNXT_DEV_STATE_CLOSING 0x1 786 u32 dev_state; 787 788 struct bnxt_ring_struct tx_ring_struct; 789 }; 790 791 #define BNXT_LEGACY_COAL_CMPL_PARAMS \ 792 (RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN | \ 793 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MAX | \ 794 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET | \ 795 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE | \ 796 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR | \ 797 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT | \ 798 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR | \ 799 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT | \ 800 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_AGGR_INT) 801 802 #define BNXT_COAL_CMPL_ENABLES \ 803 (RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR | \ 804 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_CMPL_AGGR_DMA_TMR | \ 805 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MAX | \ 806 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_AGGR_INT) 807 808 #define BNXT_COAL_CMPL_MIN_TMR_ENABLE \ 809 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MIN 810 811 #define BNXT_COAL_CMPL_AGGR_TMR_DURING_INT_ENABLE \ 812 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT 813 814 struct bnxt_coal_cap { 815 u32 cmpl_params; 816 u32 nq_params; 817 u16 num_cmpl_dma_aggr_max; 818 u16 num_cmpl_dma_aggr_during_int_max; 819 u16 cmpl_aggr_dma_tmr_max; 820 u16 cmpl_aggr_dma_tmr_during_int_max; 821 u16 int_lat_tmr_min_max; 822 u16 int_lat_tmr_max_max; 823 u16 num_cmpl_aggr_int_max; 824 u16 timer_units; 825 }; 826 827 struct bnxt_coal { 828 u16 coal_ticks; 829 u16 coal_ticks_irq; 830 u16 coal_bufs; 831 u16 coal_bufs_irq; 832 /* RING_IDLE enabled when coal ticks < idle_thresh */ 833 u16 idle_thresh; 834 u8 bufs_per_record; 835 u8 budget; 836 }; 837 838 struct bnxt_tpa_info { 839 void *data; 840 u8 *data_ptr; 841 dma_addr_t mapping; 842 u16 len; 843 unsigned short gso_type; 844 u32 flags2; 845 u32 metadata; 846 enum pkt_hash_types hash_type; 847 u32 rss_hash; 848 u32 hdr_info; 849 850 #define BNXT_TPA_L4_SIZE(hdr_info) \ 851 (((hdr_info) & 0xf8000000) ? ((hdr_info) >> 27) : 32) 852 853 #define BNXT_TPA_INNER_L3_OFF(hdr_info) \ 854 (((hdr_info) >> 18) & 0x1ff) 855 856 #define BNXT_TPA_INNER_L2_OFF(hdr_info) \ 857 (((hdr_info) >> 9) & 0x1ff) 858 859 #define BNXT_TPA_OUTER_L3_OFF(hdr_info) \ 860 ((hdr_info) & 0x1ff) 861 862 u16 cfa_code; /* cfa_code in TPA start compl */ 863 u8 agg_count; 864 struct rx_agg_cmp *agg_arr; 865 }; 866 867 #define BNXT_AGG_IDX_BMAP_SIZE (MAX_TPA_P5 / BITS_PER_LONG) 868 869 struct bnxt_tpa_idx_map { 870 u16 agg_id_tbl[1024]; 871 unsigned long agg_idx_bmap[BNXT_AGG_IDX_BMAP_SIZE]; 872 }; 873 874 struct bnxt_rx_ring_info { 875 struct bnxt_napi *bnapi; 876 u16 rx_prod; 877 u16 rx_agg_prod; 878 u16 rx_sw_agg_prod; 879 u16 rx_next_cons; 880 struct bnxt_db_info rx_db; 881 struct bnxt_db_info rx_agg_db; 882 883 struct bpf_prog *xdp_prog; 884 885 struct rx_bd *rx_desc_ring[MAX_RX_PAGES]; 886 struct bnxt_sw_rx_bd *rx_buf_ring; 887 888 struct rx_bd *rx_agg_desc_ring[MAX_RX_AGG_PAGES]; 889 struct bnxt_sw_rx_agg_bd *rx_agg_ring; 890 891 unsigned long *rx_agg_bmap; 892 u16 rx_agg_bmap_size; 893 894 struct page *rx_page; 895 unsigned int rx_page_offset; 896 897 dma_addr_t rx_desc_mapping[MAX_RX_PAGES]; 898 dma_addr_t rx_agg_desc_mapping[MAX_RX_AGG_PAGES]; 899 900 struct bnxt_tpa_info *rx_tpa; 901 struct bnxt_tpa_idx_map *rx_tpa_idx_map; 902 903 struct bnxt_ring_struct rx_ring_struct; 904 struct bnxt_ring_struct rx_agg_ring_struct; 905 struct xdp_rxq_info xdp_rxq; 906 struct page_pool *page_pool; 907 }; 908 909 struct bnxt_rx_sw_stats { 910 u64 rx_l4_csum_errors; 911 u64 rx_resets; 912 u64 rx_buf_errors; 913 u64 rx_oom_discards; 914 u64 rx_netpoll_discards; 915 }; 916 917 struct bnxt_cmn_sw_stats { 918 u64 missed_irqs; 919 }; 920 921 struct bnxt_sw_stats { 922 struct bnxt_rx_sw_stats rx; 923 struct bnxt_cmn_sw_stats cmn; 924 }; 925 926 struct bnxt_stats_mem { 927 u64 *sw_stats; 928 u64 *hw_masks; 929 void *hw_stats; 930 dma_addr_t hw_stats_map; 931 int len; 932 }; 933 934 struct bnxt_cp_ring_info { 935 struct bnxt_napi *bnapi; 936 u32 cp_raw_cons; 937 struct bnxt_db_info cp_db; 938 939 u8 had_work_done:1; 940 u8 has_more_work:1; 941 942 u32 last_cp_raw_cons; 943 944 struct bnxt_coal rx_ring_coal; 945 u64 rx_packets; 946 u64 rx_bytes; 947 u64 event_ctr; 948 949 struct dim dim; 950 951 union { 952 struct tx_cmp **cp_desc_ring; 953 struct nqe_cn **nq_desc_ring; 954 }; 955 956 dma_addr_t *cp_desc_mapping; 957 958 struct bnxt_stats_mem stats; 959 u32 hw_stats_ctx_id; 960 961 struct bnxt_sw_stats sw_stats; 962 963 struct bnxt_ring_struct cp_ring_struct; 964 965 struct bnxt_cp_ring_info *cp_ring_arr[2]; 966 #define BNXT_RX_HDL 0 967 #define BNXT_TX_HDL 1 968 }; 969 970 struct bnxt_napi { 971 struct napi_struct napi; 972 struct bnxt *bp; 973 974 int index; 975 struct bnxt_cp_ring_info cp_ring; 976 struct bnxt_rx_ring_info *rx_ring; 977 struct bnxt_tx_ring_info *tx_ring; 978 979 void (*tx_int)(struct bnxt *, struct bnxt_napi *, 980 int); 981 int tx_pkts; 982 u8 events; 983 984 u32 flags; 985 #define BNXT_NAPI_FLAG_XDP 0x1 986 987 bool in_reset; 988 }; 989 990 struct bnxt_irq { 991 irq_handler_t handler; 992 unsigned int vector; 993 u8 requested:1; 994 u8 have_cpumask:1; 995 char name[IFNAMSIZ + 2]; 996 cpumask_var_t cpu_mask; 997 }; 998 999 #define HWRM_RING_ALLOC_TX 0x1 1000 #define HWRM_RING_ALLOC_RX 0x2 1001 #define HWRM_RING_ALLOC_AGG 0x4 1002 #define HWRM_RING_ALLOC_CMPL 0x8 1003 #define HWRM_RING_ALLOC_NQ 0x10 1004 1005 #define INVALID_STATS_CTX_ID -1 1006 1007 struct bnxt_ring_grp_info { 1008 u16 fw_stats_ctx; 1009 u16 fw_grp_id; 1010 u16 rx_fw_ring_id; 1011 u16 agg_fw_ring_id; 1012 u16 cp_fw_ring_id; 1013 }; 1014 1015 struct bnxt_vnic_info { 1016 u16 fw_vnic_id; /* returned by Chimp during alloc */ 1017 #define BNXT_MAX_CTX_PER_VNIC 8 1018 u16 fw_rss_cos_lb_ctx[BNXT_MAX_CTX_PER_VNIC]; 1019 u16 fw_l2_ctx_id; 1020 #define BNXT_MAX_UC_ADDRS 4 1021 __le64 fw_l2_filter_id[BNXT_MAX_UC_ADDRS]; 1022 /* index 0 always dev_addr */ 1023 u16 uc_filter_count; 1024 u8 *uc_list; 1025 1026 u16 *fw_grp_ids; 1027 dma_addr_t rss_table_dma_addr; 1028 __le16 *rss_table; 1029 dma_addr_t rss_hash_key_dma_addr; 1030 u64 *rss_hash_key; 1031 int rss_table_size; 1032 #define BNXT_RSS_TABLE_ENTRIES_P5 64 1033 #define BNXT_RSS_TABLE_SIZE_P5 (BNXT_RSS_TABLE_ENTRIES_P5 * 4) 1034 #define BNXT_RSS_TABLE_MAX_TBL_P5 8 1035 #define BNXT_MAX_RSS_TABLE_SIZE_P5 \ 1036 (BNXT_RSS_TABLE_SIZE_P5 * BNXT_RSS_TABLE_MAX_TBL_P5) 1037 #define BNXT_MAX_RSS_TABLE_ENTRIES_P5 \ 1038 (BNXT_RSS_TABLE_ENTRIES_P5 * BNXT_RSS_TABLE_MAX_TBL_P5) 1039 1040 u32 rx_mask; 1041 1042 u8 *mc_list; 1043 int mc_list_size; 1044 int mc_list_count; 1045 dma_addr_t mc_list_mapping; 1046 #define BNXT_MAX_MC_ADDRS 16 1047 1048 u32 flags; 1049 #define BNXT_VNIC_RSS_FLAG 1 1050 #define BNXT_VNIC_RFS_FLAG 2 1051 #define BNXT_VNIC_MCAST_FLAG 4 1052 #define BNXT_VNIC_UCAST_FLAG 8 1053 #define BNXT_VNIC_RFS_NEW_RSS_FLAG 0x10 1054 }; 1055 1056 struct bnxt_hw_resc { 1057 u16 min_rsscos_ctxs; 1058 u16 max_rsscos_ctxs; 1059 u16 min_cp_rings; 1060 u16 max_cp_rings; 1061 u16 resv_cp_rings; 1062 u16 min_tx_rings; 1063 u16 max_tx_rings; 1064 u16 resv_tx_rings; 1065 u16 max_tx_sch_inputs; 1066 u16 min_rx_rings; 1067 u16 max_rx_rings; 1068 u16 resv_rx_rings; 1069 u16 min_hw_ring_grps; 1070 u16 max_hw_ring_grps; 1071 u16 resv_hw_ring_grps; 1072 u16 min_l2_ctxs; 1073 u16 max_l2_ctxs; 1074 u16 min_vnics; 1075 u16 max_vnics; 1076 u16 resv_vnics; 1077 u16 min_stat_ctxs; 1078 u16 max_stat_ctxs; 1079 u16 resv_stat_ctxs; 1080 u16 max_nqs; 1081 u16 max_irqs; 1082 u16 resv_irqs; 1083 }; 1084 1085 #if defined(CONFIG_BNXT_SRIOV) 1086 struct bnxt_vf_info { 1087 u16 fw_fid; 1088 u8 mac_addr[ETH_ALEN]; /* PF assigned MAC Address */ 1089 u8 vf_mac_addr[ETH_ALEN]; /* VF assigned MAC address, only 1090 * stored by PF. 1091 */ 1092 u16 vlan; 1093 u16 func_qcfg_flags; 1094 u32 flags; 1095 #define BNXT_VF_QOS 0x1 1096 #define BNXT_VF_SPOOFCHK 0x2 1097 #define BNXT_VF_LINK_FORCED 0x4 1098 #define BNXT_VF_LINK_UP 0x8 1099 #define BNXT_VF_TRUST 0x10 1100 u32 min_tx_rate; 1101 u32 max_tx_rate; 1102 void *hwrm_cmd_req_addr; 1103 dma_addr_t hwrm_cmd_req_dma_addr; 1104 }; 1105 #endif 1106 1107 struct bnxt_pf_info { 1108 #define BNXT_FIRST_PF_FID 1 1109 #define BNXT_FIRST_VF_FID 128 1110 u16 fw_fid; 1111 u16 port_id; 1112 u8 mac_addr[ETH_ALEN]; 1113 u32 first_vf_id; 1114 u16 active_vfs; 1115 u16 registered_vfs; 1116 u16 max_vfs; 1117 u32 max_encap_records; 1118 u32 max_decap_records; 1119 u32 max_tx_em_flows; 1120 u32 max_tx_wm_flows; 1121 u32 max_rx_em_flows; 1122 u32 max_rx_wm_flows; 1123 unsigned long *vf_event_bmap; 1124 u16 hwrm_cmd_req_pages; 1125 u8 vf_resv_strategy; 1126 #define BNXT_VF_RESV_STRATEGY_MAXIMAL 0 1127 #define BNXT_VF_RESV_STRATEGY_MINIMAL 1 1128 #define BNXT_VF_RESV_STRATEGY_MINIMAL_STATIC 2 1129 void *hwrm_cmd_req_addr[4]; 1130 dma_addr_t hwrm_cmd_req_dma_addr[4]; 1131 struct bnxt_vf_info *vf; 1132 }; 1133 1134 struct bnxt_ntuple_filter { 1135 struct hlist_node hash; 1136 u8 dst_mac_addr[ETH_ALEN]; 1137 u8 src_mac_addr[ETH_ALEN]; 1138 struct flow_keys fkeys; 1139 __le64 filter_id; 1140 u16 sw_id; 1141 u8 l2_fltr_idx; 1142 u16 rxq; 1143 u32 flow_id; 1144 unsigned long state; 1145 #define BNXT_FLTR_VALID 0 1146 #define BNXT_FLTR_UPDATE 1 1147 }; 1148 1149 struct bnxt_link_info { 1150 u8 phy_type; 1151 u8 media_type; 1152 u8 transceiver; 1153 u8 phy_addr; 1154 u8 phy_link_status; 1155 #define BNXT_LINK_NO_LINK PORT_PHY_QCFG_RESP_LINK_NO_LINK 1156 #define BNXT_LINK_SIGNAL PORT_PHY_QCFG_RESP_LINK_SIGNAL 1157 #define BNXT_LINK_LINK PORT_PHY_QCFG_RESP_LINK_LINK 1158 u8 wire_speed; 1159 u8 phy_state; 1160 #define BNXT_PHY_STATE_ENABLED 0 1161 #define BNXT_PHY_STATE_DISABLED 1 1162 1163 u8 link_up; 1164 u8 duplex; 1165 #define BNXT_LINK_DUPLEX_HALF PORT_PHY_QCFG_RESP_DUPLEX_STATE_HALF 1166 #define BNXT_LINK_DUPLEX_FULL PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL 1167 u8 pause; 1168 #define BNXT_LINK_PAUSE_TX PORT_PHY_QCFG_RESP_PAUSE_TX 1169 #define BNXT_LINK_PAUSE_RX PORT_PHY_QCFG_RESP_PAUSE_RX 1170 #define BNXT_LINK_PAUSE_BOTH (PORT_PHY_QCFG_RESP_PAUSE_RX | \ 1171 PORT_PHY_QCFG_RESP_PAUSE_TX) 1172 u8 lp_pause; 1173 u8 auto_pause_setting; 1174 u8 force_pause_setting; 1175 u8 duplex_setting; 1176 u8 auto_mode; 1177 #define BNXT_AUTO_MODE(mode) ((mode) > BNXT_LINK_AUTO_NONE && \ 1178 (mode) <= BNXT_LINK_AUTO_MSK) 1179 #define BNXT_LINK_AUTO_NONE PORT_PHY_QCFG_RESP_AUTO_MODE_NONE 1180 #define BNXT_LINK_AUTO_ALLSPDS PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS 1181 #define BNXT_LINK_AUTO_ONESPD PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED 1182 #define BNXT_LINK_AUTO_ONEORBELOW PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW 1183 #define BNXT_LINK_AUTO_MSK PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK 1184 #define PHY_VER_LEN 3 1185 u8 phy_ver[PHY_VER_LEN]; 1186 u16 link_speed; 1187 #define BNXT_LINK_SPEED_100MB PORT_PHY_QCFG_RESP_LINK_SPEED_100MB 1188 #define BNXT_LINK_SPEED_1GB PORT_PHY_QCFG_RESP_LINK_SPEED_1GB 1189 #define BNXT_LINK_SPEED_2GB PORT_PHY_QCFG_RESP_LINK_SPEED_2GB 1190 #define BNXT_LINK_SPEED_2_5GB PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB 1191 #define BNXT_LINK_SPEED_10GB PORT_PHY_QCFG_RESP_LINK_SPEED_10GB 1192 #define BNXT_LINK_SPEED_20GB PORT_PHY_QCFG_RESP_LINK_SPEED_20GB 1193 #define BNXT_LINK_SPEED_25GB PORT_PHY_QCFG_RESP_LINK_SPEED_25GB 1194 #define BNXT_LINK_SPEED_40GB PORT_PHY_QCFG_RESP_LINK_SPEED_40GB 1195 #define BNXT_LINK_SPEED_50GB PORT_PHY_QCFG_RESP_LINK_SPEED_50GB 1196 #define BNXT_LINK_SPEED_100GB PORT_PHY_QCFG_RESP_LINK_SPEED_100GB 1197 u16 support_speeds; 1198 u16 support_pam4_speeds; 1199 u16 auto_link_speeds; /* fw adv setting */ 1200 #define BNXT_LINK_SPEED_MSK_100MB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB 1201 #define BNXT_LINK_SPEED_MSK_1GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB 1202 #define BNXT_LINK_SPEED_MSK_2GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB 1203 #define BNXT_LINK_SPEED_MSK_10GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB 1204 #define BNXT_LINK_SPEED_MSK_2_5GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB 1205 #define BNXT_LINK_SPEED_MSK_20GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB 1206 #define BNXT_LINK_SPEED_MSK_25GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB 1207 #define BNXT_LINK_SPEED_MSK_40GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB 1208 #define BNXT_LINK_SPEED_MSK_50GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB 1209 #define BNXT_LINK_SPEED_MSK_100GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100GB 1210 u16 auto_pam4_link_speeds; 1211 #define BNXT_LINK_PAM4_SPEED_MSK_50GB PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_50G 1212 #define BNXT_LINK_PAM4_SPEED_MSK_100GB PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_100G 1213 #define BNXT_LINK_PAM4_SPEED_MSK_200GB PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_200G 1214 u16 support_auto_speeds; 1215 u16 support_pam4_auto_speeds; 1216 u16 lp_auto_link_speeds; 1217 u16 lp_auto_pam4_link_speeds; 1218 u16 force_link_speed; 1219 u16 force_pam4_link_speed; 1220 u32 preemphasis; 1221 u8 module_status; 1222 u8 active_fec_sig_mode; 1223 u16 fec_cfg; 1224 #define BNXT_FEC_NONE PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED 1225 #define BNXT_FEC_AUTONEG_CAP PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_SUPPORTED 1226 #define BNXT_FEC_AUTONEG PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_ENABLED 1227 #define BNXT_FEC_ENC_BASE_R_CAP \ 1228 PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_SUPPORTED 1229 #define BNXT_FEC_ENC_BASE_R PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_ENABLED 1230 #define BNXT_FEC_ENC_RS_CAP \ 1231 PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_SUPPORTED 1232 #define BNXT_FEC_ENC_LLRS_CAP \ 1233 (PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_SUPPORTED | \ 1234 PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_SUPPORTED) 1235 #define BNXT_FEC_ENC_RS \ 1236 (PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED | \ 1237 PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_1XN_ENABLED | \ 1238 PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_IEEE_ENABLED) 1239 #define BNXT_FEC_ENC_LLRS \ 1240 (PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_ENABLED | \ 1241 PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_ENABLED) 1242 1243 /* copy of requested setting from ethtool cmd */ 1244 u8 autoneg; 1245 #define BNXT_AUTONEG_SPEED 1 1246 #define BNXT_AUTONEG_FLOW_CTRL 2 1247 u8 req_signal_mode; 1248 #define BNXT_SIG_MODE_NRZ PORT_PHY_QCFG_RESP_SIGNAL_MODE_NRZ 1249 #define BNXT_SIG_MODE_PAM4 PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4 1250 u8 req_duplex; 1251 u8 req_flow_ctrl; 1252 u16 req_link_speed; 1253 u16 advertising; /* user adv setting */ 1254 u16 advertising_pam4; 1255 bool force_link_chng; 1256 1257 bool phy_retry; 1258 unsigned long phy_retry_expires; 1259 1260 /* a copy of phy_qcfg output used to report link 1261 * info to VF 1262 */ 1263 struct hwrm_port_phy_qcfg_output phy_qcfg_resp; 1264 }; 1265 1266 #define BNXT_FEC_RS544_ON \ 1267 (PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_ENABLE | \ 1268 PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_ENABLE) 1269 1270 #define BNXT_FEC_RS544_OFF \ 1271 (PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_DISABLE | \ 1272 PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_DISABLE) 1273 1274 #define BNXT_FEC_RS272_ON \ 1275 (PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_ENABLE | \ 1276 PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_ENABLE) 1277 1278 #define BNXT_FEC_RS272_OFF \ 1279 (PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_DISABLE | \ 1280 PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_DISABLE) 1281 1282 #define BNXT_PAM4_SUPPORTED(link_info) \ 1283 ((link_info)->support_pam4_speeds) 1284 1285 #define BNXT_FEC_RS_ON(link_info) \ 1286 (PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE | \ 1287 PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE | \ 1288 (BNXT_PAM4_SUPPORTED(link_info) ? \ 1289 (BNXT_FEC_RS544_ON | BNXT_FEC_RS272_OFF) : 0)) 1290 1291 #define BNXT_FEC_LLRS_ON \ 1292 (PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE | \ 1293 PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE | \ 1294 BNXT_FEC_RS272_ON | BNXT_FEC_RS544_OFF) 1295 1296 #define BNXT_FEC_RS_OFF(link_info) \ 1297 (PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_DISABLE | \ 1298 (BNXT_PAM4_SUPPORTED(link_info) ? \ 1299 (BNXT_FEC_RS544_OFF | BNXT_FEC_RS272_OFF) : 0)) 1300 1301 #define BNXT_FEC_BASE_R_ON(link_info) \ 1302 (PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_ENABLE | \ 1303 BNXT_FEC_RS_OFF(link_info)) 1304 1305 #define BNXT_FEC_ALL_OFF(link_info) \ 1306 (PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE | \ 1307 BNXT_FEC_RS_OFF(link_info)) 1308 1309 #define BNXT_MAX_QUEUE 8 1310 1311 struct bnxt_queue_info { 1312 u8 queue_id; 1313 u8 queue_profile; 1314 }; 1315 1316 #define BNXT_MAX_LED 4 1317 1318 struct bnxt_led_info { 1319 u8 led_id; 1320 u8 led_type; 1321 u8 led_group_id; 1322 u8 unused; 1323 __le16 led_state_caps; 1324 #define BNXT_LED_ALT_BLINK_CAP(x) ((x) & \ 1325 cpu_to_le16(PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED)) 1326 1327 __le16 led_color_caps; 1328 }; 1329 1330 #define BNXT_MAX_TEST 8 1331 1332 struct bnxt_test_info { 1333 u8 offline_mask; 1334 u16 timeout; 1335 char string[BNXT_MAX_TEST][ETH_GSTRING_LEN]; 1336 }; 1337 1338 #define CHIMP_REG_VIEW_ADDR \ 1339 ((bp->flags & BNXT_FLAG_CHIP_P5) ? 0x80000000 : 0xb1000000) 1340 1341 #define BNXT_GRCPF_REG_CHIMP_COMM 0x0 1342 #define BNXT_GRCPF_REG_CHIMP_COMM_TRIGGER 0x100 1343 #define BNXT_GRCPF_REG_WINDOW_BASE_OUT 0x400 1344 #define BNXT_CAG_REG_LEGACY_INT_STATUS 0x4014 1345 #define BNXT_CAG_REG_BASE 0x300000 1346 1347 #define BNXT_GRC_REG_STATUS_P5 0x520 1348 1349 #define BNXT_GRCPF_REG_KONG_COMM 0xA00 1350 #define BNXT_GRCPF_REG_KONG_COMM_TRIGGER 0xB00 1351 1352 #define BNXT_GRC_REG_CHIP_NUM 0x48 1353 #define BNXT_GRC_REG_BASE 0x260000 1354 1355 #define BNXT_TS_REG_TIMESYNC_TS0_LOWER 0x640180c 1356 #define BNXT_TS_REG_TIMESYNC_TS0_UPPER 0x6401810 1357 1358 #define BNXT_GRC_BASE_MASK 0xfffff000 1359 #define BNXT_GRC_OFFSET_MASK 0x00000ffc 1360 1361 struct bnxt_tc_flow_stats { 1362 u64 packets; 1363 u64 bytes; 1364 }; 1365 1366 #ifdef CONFIG_BNXT_FLOWER_OFFLOAD 1367 struct bnxt_flower_indr_block_cb_priv { 1368 struct net_device *tunnel_netdev; 1369 struct bnxt *bp; 1370 struct list_head list; 1371 }; 1372 #endif 1373 1374 struct bnxt_tc_info { 1375 bool enabled; 1376 1377 /* hash table to store TC offloaded flows */ 1378 struct rhashtable flow_table; 1379 struct rhashtable_params flow_ht_params; 1380 1381 /* hash table to store L2 keys of TC flows */ 1382 struct rhashtable l2_table; 1383 struct rhashtable_params l2_ht_params; 1384 /* hash table to store L2 keys for TC tunnel decap */ 1385 struct rhashtable decap_l2_table; 1386 struct rhashtable_params decap_l2_ht_params; 1387 /* hash table to store tunnel decap entries */ 1388 struct rhashtable decap_table; 1389 struct rhashtable_params decap_ht_params; 1390 /* hash table to store tunnel encap entries */ 1391 struct rhashtable encap_table; 1392 struct rhashtable_params encap_ht_params; 1393 1394 /* lock to atomically add/del an l2 node when a flow is 1395 * added or deleted. 1396 */ 1397 struct mutex lock; 1398 1399 /* Fields used for batching stats query */ 1400 struct rhashtable_iter iter; 1401 #define BNXT_FLOW_STATS_BATCH_MAX 10 1402 struct bnxt_tc_stats_batch { 1403 void *flow_node; 1404 struct bnxt_tc_flow_stats hw_stats; 1405 } stats_batch[BNXT_FLOW_STATS_BATCH_MAX]; 1406 1407 /* Stat counter mask (width) */ 1408 u64 bytes_mask; 1409 u64 packets_mask; 1410 }; 1411 1412 struct bnxt_vf_rep_stats { 1413 u64 packets; 1414 u64 bytes; 1415 u64 dropped; 1416 }; 1417 1418 struct bnxt_vf_rep { 1419 struct bnxt *bp; 1420 struct net_device *dev; 1421 struct metadata_dst *dst; 1422 u16 vf_idx; 1423 u16 tx_cfa_action; 1424 u16 rx_cfa_code; 1425 1426 struct bnxt_vf_rep_stats rx_stats; 1427 struct bnxt_vf_rep_stats tx_stats; 1428 }; 1429 1430 #define PTU_PTE_VALID 0x1UL 1431 #define PTU_PTE_LAST 0x2UL 1432 #define PTU_PTE_NEXT_TO_LAST 0x4UL 1433 1434 #define MAX_CTX_PAGES (BNXT_PAGE_SIZE / 8) 1435 #define MAX_CTX_TOTAL_PAGES (MAX_CTX_PAGES * MAX_CTX_PAGES) 1436 1437 struct bnxt_ctx_pg_info { 1438 u32 entries; 1439 u32 nr_pages; 1440 void *ctx_pg_arr[MAX_CTX_PAGES]; 1441 dma_addr_t ctx_dma_arr[MAX_CTX_PAGES]; 1442 struct bnxt_ring_mem_info ring_mem; 1443 struct bnxt_ctx_pg_info **ctx_pg_tbl; 1444 }; 1445 1446 #define BNXT_MAX_TQM_SP_RINGS 1 1447 #define BNXT_MAX_TQM_FP_RINGS 8 1448 #define BNXT_MAX_TQM_RINGS \ 1449 (BNXT_MAX_TQM_SP_RINGS + BNXT_MAX_TQM_FP_RINGS) 1450 1451 #define BNXT_BACKING_STORE_CFG_LEGACY_LEN 256 1452 1453 #define BNXT_SET_CTX_PAGE_ATTR(attr) \ 1454 do { \ 1455 if (BNXT_PAGE_SIZE == 0x2000) \ 1456 attr = FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8K; \ 1457 else if (BNXT_PAGE_SIZE == 0x10000) \ 1458 attr = FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_64K; \ 1459 else \ 1460 attr = FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_4K; \ 1461 } while (0) 1462 1463 struct bnxt_ctx_mem_info { 1464 u32 qp_max_entries; 1465 u16 qp_min_qp1_entries; 1466 u16 qp_max_l2_entries; 1467 u16 qp_entry_size; 1468 u16 srq_max_l2_entries; 1469 u32 srq_max_entries; 1470 u16 srq_entry_size; 1471 u16 cq_max_l2_entries; 1472 u32 cq_max_entries; 1473 u16 cq_entry_size; 1474 u16 vnic_max_vnic_entries; 1475 u16 vnic_max_ring_table_entries; 1476 u16 vnic_entry_size; 1477 u32 stat_max_entries; 1478 u16 stat_entry_size; 1479 u16 tqm_entry_size; 1480 u32 tqm_min_entries_per_ring; 1481 u32 tqm_max_entries_per_ring; 1482 u32 mrav_max_entries; 1483 u16 mrav_entry_size; 1484 u16 tim_entry_size; 1485 u32 tim_max_entries; 1486 u16 mrav_num_entries_units; 1487 u8 tqm_entries_multiple; 1488 u8 tqm_fp_rings_count; 1489 1490 u32 flags; 1491 #define BNXT_CTX_FLAG_INITED 0x01 1492 1493 struct bnxt_ctx_pg_info qp_mem; 1494 struct bnxt_ctx_pg_info srq_mem; 1495 struct bnxt_ctx_pg_info cq_mem; 1496 struct bnxt_ctx_pg_info vnic_mem; 1497 struct bnxt_ctx_pg_info stat_mem; 1498 struct bnxt_ctx_pg_info mrav_mem; 1499 struct bnxt_ctx_pg_info tim_mem; 1500 struct bnxt_ctx_pg_info *tqm_mem[BNXT_MAX_TQM_RINGS]; 1501 1502 #define BNXT_CTX_MEM_INIT_QP 0 1503 #define BNXT_CTX_MEM_INIT_SRQ 1 1504 #define BNXT_CTX_MEM_INIT_CQ 2 1505 #define BNXT_CTX_MEM_INIT_VNIC 3 1506 #define BNXT_CTX_MEM_INIT_STAT 4 1507 #define BNXT_CTX_MEM_INIT_MRAV 5 1508 #define BNXT_CTX_MEM_INIT_MAX 6 1509 struct bnxt_mem_init mem_init[BNXT_CTX_MEM_INIT_MAX]; 1510 }; 1511 1512 struct bnxt_fw_health { 1513 u32 flags; 1514 u32 polling_dsecs; 1515 u32 master_func_wait_dsecs; 1516 u32 normal_func_wait_dsecs; 1517 u32 post_reset_wait_dsecs; 1518 u32 post_reset_max_wait_dsecs; 1519 u32 regs[4]; 1520 u32 mapped_regs[4]; 1521 #define BNXT_FW_HEALTH_REG 0 1522 #define BNXT_FW_HEARTBEAT_REG 1 1523 #define BNXT_FW_RESET_CNT_REG 2 1524 #define BNXT_FW_RESET_INPROG_REG 3 1525 u32 fw_reset_inprog_reg_mask; 1526 u32 last_fw_heartbeat; 1527 u32 last_fw_reset_cnt; 1528 u8 enabled:1; 1529 u8 master:1; 1530 u8 fatal:1; 1531 u8 status_reliable:1; 1532 u8 tmr_multiplier; 1533 u8 tmr_counter; 1534 u8 fw_reset_seq_cnt; 1535 u32 fw_reset_seq_regs[16]; 1536 u32 fw_reset_seq_vals[16]; 1537 u32 fw_reset_seq_delay_msec[16]; 1538 u32 echo_req_data1; 1539 u32 echo_req_data2; 1540 struct devlink_health_reporter *fw_reporter; 1541 struct devlink_health_reporter *fw_reset_reporter; 1542 struct devlink_health_reporter *fw_fatal_reporter; 1543 }; 1544 1545 struct bnxt_fw_reporter_ctx { 1546 unsigned long sp_event; 1547 }; 1548 1549 #define BNXT_FW_HEALTH_REG_TYPE_MASK 3 1550 #define BNXT_FW_HEALTH_REG_TYPE_CFG 0 1551 #define BNXT_FW_HEALTH_REG_TYPE_GRC 1 1552 #define BNXT_FW_HEALTH_REG_TYPE_BAR0 2 1553 #define BNXT_FW_HEALTH_REG_TYPE_BAR1 3 1554 1555 #define BNXT_FW_HEALTH_REG_TYPE(reg) ((reg) & BNXT_FW_HEALTH_REG_TYPE_MASK) 1556 #define BNXT_FW_HEALTH_REG_OFF(reg) ((reg) & ~BNXT_FW_HEALTH_REG_TYPE_MASK) 1557 1558 #define BNXT_FW_HEALTH_WIN_BASE 0x3000 1559 #define BNXT_FW_HEALTH_WIN_MAP_OFF 8 1560 1561 #define BNXT_FW_HEALTH_WIN_OFF(reg) (BNXT_FW_HEALTH_WIN_BASE + \ 1562 ((reg) & BNXT_GRC_OFFSET_MASK)) 1563 1564 #define BNXT_FW_STATUS_HEALTH_MSK 0xffff 1565 #define BNXT_FW_STATUS_HEALTHY 0x8000 1566 #define BNXT_FW_STATUS_SHUTDOWN 0x100000 1567 #define BNXT_FW_STATUS_RECOVERING 0x400000 1568 1569 #define BNXT_FW_IS_HEALTHY(sts) (((sts) & BNXT_FW_STATUS_HEALTH_MSK) ==\ 1570 BNXT_FW_STATUS_HEALTHY) 1571 1572 #define BNXT_FW_IS_BOOTING(sts) (((sts) & BNXT_FW_STATUS_HEALTH_MSK) < \ 1573 BNXT_FW_STATUS_HEALTHY) 1574 1575 #define BNXT_FW_IS_ERR(sts) (((sts) & BNXT_FW_STATUS_HEALTH_MSK) > \ 1576 BNXT_FW_STATUS_HEALTHY) 1577 1578 #define BNXT_FW_IS_RECOVERING(sts) (BNXT_FW_IS_ERR(sts) && \ 1579 ((sts) & BNXT_FW_STATUS_RECOVERING)) 1580 1581 #define BNXT_FW_RETRY 5 1582 #define BNXT_FW_IF_RETRY 10 1583 1584 struct bnxt { 1585 void __iomem *bar0; 1586 void __iomem *bar1; 1587 void __iomem *bar2; 1588 1589 u32 reg_base; 1590 u16 chip_num; 1591 #define CHIP_NUM_57301 0x16c8 1592 #define CHIP_NUM_57302 0x16c9 1593 #define CHIP_NUM_57304 0x16ca 1594 #define CHIP_NUM_58700 0x16cd 1595 #define CHIP_NUM_57402 0x16d0 1596 #define CHIP_NUM_57404 0x16d1 1597 #define CHIP_NUM_57406 0x16d2 1598 #define CHIP_NUM_57407 0x16d5 1599 1600 #define CHIP_NUM_57311 0x16ce 1601 #define CHIP_NUM_57312 0x16cf 1602 #define CHIP_NUM_57314 0x16df 1603 #define CHIP_NUM_57317 0x16e0 1604 #define CHIP_NUM_57412 0x16d6 1605 #define CHIP_NUM_57414 0x16d7 1606 #define CHIP_NUM_57416 0x16d8 1607 #define CHIP_NUM_57417 0x16d9 1608 #define CHIP_NUM_57412L 0x16da 1609 #define CHIP_NUM_57414L 0x16db 1610 1611 #define CHIP_NUM_5745X 0xd730 1612 #define CHIP_NUM_57452 0xc452 1613 #define CHIP_NUM_57454 0xc454 1614 1615 #define CHIP_NUM_57508 0x1750 1616 #define CHIP_NUM_57504 0x1751 1617 #define CHIP_NUM_57502 0x1752 1618 1619 #define CHIP_NUM_58802 0xd802 1620 #define CHIP_NUM_58804 0xd804 1621 #define CHIP_NUM_58808 0xd808 1622 1623 u8 chip_rev; 1624 1625 #define CHIP_NUM_58818 0xd818 1626 1627 #define BNXT_CHIP_NUM_5730X(chip_num) \ 1628 ((chip_num) >= CHIP_NUM_57301 && \ 1629 (chip_num) <= CHIP_NUM_57304) 1630 1631 #define BNXT_CHIP_NUM_5740X(chip_num) \ 1632 (((chip_num) >= CHIP_NUM_57402 && \ 1633 (chip_num) <= CHIP_NUM_57406) || \ 1634 (chip_num) == CHIP_NUM_57407) 1635 1636 #define BNXT_CHIP_NUM_5731X(chip_num) \ 1637 ((chip_num) == CHIP_NUM_57311 || \ 1638 (chip_num) == CHIP_NUM_57312 || \ 1639 (chip_num) == CHIP_NUM_57314 || \ 1640 (chip_num) == CHIP_NUM_57317) 1641 1642 #define BNXT_CHIP_NUM_5741X(chip_num) \ 1643 ((chip_num) >= CHIP_NUM_57412 && \ 1644 (chip_num) <= CHIP_NUM_57414L) 1645 1646 #define BNXT_CHIP_NUM_58700(chip_num) \ 1647 ((chip_num) == CHIP_NUM_58700) 1648 1649 #define BNXT_CHIP_NUM_5745X(chip_num) \ 1650 ((chip_num) == CHIP_NUM_5745X || \ 1651 (chip_num) == CHIP_NUM_57452 || \ 1652 (chip_num) == CHIP_NUM_57454) 1653 1654 1655 #define BNXT_CHIP_NUM_57X0X(chip_num) \ 1656 (BNXT_CHIP_NUM_5730X(chip_num) || BNXT_CHIP_NUM_5740X(chip_num)) 1657 1658 #define BNXT_CHIP_NUM_57X1X(chip_num) \ 1659 (BNXT_CHIP_NUM_5731X(chip_num) || BNXT_CHIP_NUM_5741X(chip_num)) 1660 1661 #define BNXT_CHIP_NUM_588XX(chip_num) \ 1662 ((chip_num) == CHIP_NUM_58802 || \ 1663 (chip_num) == CHIP_NUM_58804 || \ 1664 (chip_num) == CHIP_NUM_58808) 1665 1666 #define BNXT_VPD_FLD_LEN 32 1667 char board_partno[BNXT_VPD_FLD_LEN]; 1668 char board_serialno[BNXT_VPD_FLD_LEN]; 1669 1670 struct net_device *dev; 1671 struct pci_dev *pdev; 1672 1673 atomic_t intr_sem; 1674 1675 u32 flags; 1676 #define BNXT_FLAG_CHIP_P5 0x1 1677 #define BNXT_FLAG_VF 0x2 1678 #define BNXT_FLAG_LRO 0x4 1679 #ifdef CONFIG_INET 1680 #define BNXT_FLAG_GRO 0x8 1681 #else 1682 /* Cannot support hardware GRO if CONFIG_INET is not set */ 1683 #define BNXT_FLAG_GRO 0x0 1684 #endif 1685 #define BNXT_FLAG_TPA (BNXT_FLAG_LRO | BNXT_FLAG_GRO) 1686 #define BNXT_FLAG_JUMBO 0x10 1687 #define BNXT_FLAG_STRIP_VLAN 0x20 1688 #define BNXT_FLAG_AGG_RINGS (BNXT_FLAG_JUMBO | BNXT_FLAG_GRO | \ 1689 BNXT_FLAG_LRO) 1690 #define BNXT_FLAG_USING_MSIX 0x40 1691 #define BNXT_FLAG_MSIX_CAP 0x80 1692 #define BNXT_FLAG_RFS 0x100 1693 #define BNXT_FLAG_SHARED_RINGS 0x200 1694 #define BNXT_FLAG_PORT_STATS 0x400 1695 #define BNXT_FLAG_UDP_RSS_CAP 0x800 1696 #define BNXT_FLAG_NEW_RSS_CAP 0x2000 1697 #define BNXT_FLAG_WOL_CAP 0x4000 1698 #define BNXT_FLAG_ROCEV1_CAP 0x8000 1699 #define BNXT_FLAG_ROCEV2_CAP 0x10000 1700 #define BNXT_FLAG_ROCE_CAP (BNXT_FLAG_ROCEV1_CAP | \ 1701 BNXT_FLAG_ROCEV2_CAP) 1702 #define BNXT_FLAG_NO_AGG_RINGS 0x20000 1703 #define BNXT_FLAG_RX_PAGE_MODE 0x40000 1704 #define BNXT_FLAG_CHIP_SR2 0x80000 1705 #define BNXT_FLAG_MULTI_HOST 0x100000 1706 #define BNXT_FLAG_DSN_VALID 0x200000 1707 #define BNXT_FLAG_DOUBLE_DB 0x400000 1708 #define BNXT_FLAG_CHIP_NITRO_A0 0x1000000 1709 #define BNXT_FLAG_DIM 0x2000000 1710 #define BNXT_FLAG_ROCE_MIRROR_CAP 0x4000000 1711 #define BNXT_FLAG_PORT_STATS_EXT 0x10000000 1712 1713 #define BNXT_FLAG_ALL_CONFIG_FEATS (BNXT_FLAG_TPA | \ 1714 BNXT_FLAG_RFS | \ 1715 BNXT_FLAG_STRIP_VLAN) 1716 1717 #define BNXT_PF(bp) (!((bp)->flags & BNXT_FLAG_VF)) 1718 #define BNXT_VF(bp) ((bp)->flags & BNXT_FLAG_VF) 1719 #define BNXT_NPAR(bp) ((bp)->port_partition_type) 1720 #define BNXT_MH(bp) ((bp)->flags & BNXT_FLAG_MULTI_HOST) 1721 #define BNXT_SINGLE_PF(bp) (BNXT_PF(bp) && !BNXT_NPAR(bp) && !BNXT_MH(bp)) 1722 #define BNXT_SH_PORT_CFG_OK(bp) (BNXT_PF(bp) && \ 1723 ((bp)->phy_flags & BNXT_PHY_FL_SHARED_PORT_CFG)) 1724 #define BNXT_PHY_CFG_ABLE(bp) ((BNXT_SINGLE_PF(bp) || \ 1725 BNXT_SH_PORT_CFG_OK(bp)) && \ 1726 (bp)->link_info.phy_state == BNXT_PHY_STATE_ENABLED) 1727 #define BNXT_CHIP_TYPE_NITRO_A0(bp) ((bp)->flags & BNXT_FLAG_CHIP_NITRO_A0) 1728 #define BNXT_RX_PAGE_MODE(bp) ((bp)->flags & BNXT_FLAG_RX_PAGE_MODE) 1729 #define BNXT_SUPPORTS_TPA(bp) (!BNXT_CHIP_TYPE_NITRO_A0(bp) && \ 1730 (!((bp)->flags & BNXT_FLAG_CHIP_P5) || \ 1731 (bp)->max_tpa_v2) && !is_kdump_kernel()) 1732 1733 #define BNXT_CHIP_SR2(bp) \ 1734 ((bp)->chip_num == CHIP_NUM_58818) 1735 1736 #define BNXT_CHIP_P5_THOR(bp) \ 1737 ((bp)->chip_num == CHIP_NUM_57508 || \ 1738 (bp)->chip_num == CHIP_NUM_57504 || \ 1739 (bp)->chip_num == CHIP_NUM_57502) 1740 1741 /* Chip class phase 5 */ 1742 #define BNXT_CHIP_P5(bp) \ 1743 (BNXT_CHIP_P5_THOR(bp) || BNXT_CHIP_SR2(bp)) 1744 1745 /* Chip class phase 4.x */ 1746 #define BNXT_CHIP_P4(bp) \ 1747 (BNXT_CHIP_NUM_57X1X((bp)->chip_num) || \ 1748 BNXT_CHIP_NUM_5745X((bp)->chip_num) || \ 1749 BNXT_CHIP_NUM_588XX((bp)->chip_num) || \ 1750 (BNXT_CHIP_NUM_58700((bp)->chip_num) && \ 1751 !BNXT_CHIP_TYPE_NITRO_A0(bp))) 1752 1753 #define BNXT_CHIP_P4_PLUS(bp) \ 1754 (BNXT_CHIP_P4(bp) || BNXT_CHIP_P5(bp)) 1755 1756 struct bnxt_en_dev *edev; 1757 1758 struct bnxt_napi **bnapi; 1759 1760 struct bnxt_rx_ring_info *rx_ring; 1761 struct bnxt_tx_ring_info *tx_ring; 1762 u16 *tx_ring_map; 1763 1764 struct sk_buff * (*gro_func)(struct bnxt_tpa_info *, int, int, 1765 struct sk_buff *); 1766 1767 struct sk_buff * (*rx_skb_func)(struct bnxt *, 1768 struct bnxt_rx_ring_info *, 1769 u16, void *, u8 *, dma_addr_t, 1770 unsigned int); 1771 1772 u16 max_tpa_v2; 1773 u16 max_tpa; 1774 u32 rx_buf_size; 1775 u32 rx_buf_use_size; /* useable size */ 1776 u16 rx_offset; 1777 u16 rx_dma_offset; 1778 enum dma_data_direction rx_dir; 1779 u32 rx_ring_size; 1780 u32 rx_agg_ring_size; 1781 u32 rx_copy_thresh; 1782 u32 rx_ring_mask; 1783 u32 rx_agg_ring_mask; 1784 int rx_nr_pages; 1785 int rx_agg_nr_pages; 1786 int rx_nr_rings; 1787 int rsscos_nr_ctxs; 1788 1789 u32 tx_ring_size; 1790 u32 tx_ring_mask; 1791 int tx_nr_pages; 1792 int tx_nr_rings; 1793 int tx_nr_rings_per_tc; 1794 int tx_nr_rings_xdp; 1795 1796 int tx_wake_thresh; 1797 int tx_push_thresh; 1798 int tx_push_size; 1799 1800 u32 cp_ring_size; 1801 u32 cp_ring_mask; 1802 u32 cp_bit; 1803 int cp_nr_pages; 1804 int cp_nr_rings; 1805 1806 /* grp_info indexed by completion ring index */ 1807 struct bnxt_ring_grp_info *grp_info; 1808 struct bnxt_vnic_info *vnic_info; 1809 int nr_vnics; 1810 u16 *rss_indir_tbl; 1811 u16 rss_indir_tbl_entries; 1812 u32 rss_hash_cfg; 1813 1814 u16 max_mtu; 1815 u8 max_tc; 1816 u8 max_lltc; /* lossless TCs */ 1817 struct bnxt_queue_info q_info[BNXT_MAX_QUEUE]; 1818 u8 tc_to_qidx[BNXT_MAX_QUEUE]; 1819 u8 q_ids[BNXT_MAX_QUEUE]; 1820 u8 max_q; 1821 1822 unsigned int current_interval; 1823 #define BNXT_TIMER_INTERVAL HZ 1824 1825 struct timer_list timer; 1826 1827 unsigned long state; 1828 #define BNXT_STATE_OPEN 0 1829 #define BNXT_STATE_IN_SP_TASK 1 1830 #define BNXT_STATE_READ_STATS 2 1831 #define BNXT_STATE_FW_RESET_DET 3 1832 #define BNXT_STATE_IN_FW_RESET 4 1833 #define BNXT_STATE_ABORT_ERR 5 1834 #define BNXT_STATE_FW_FATAL_COND 6 1835 #define BNXT_STATE_DRV_REGISTERED 7 1836 #define BNXT_STATE_PCI_CHANNEL_IO_FROZEN 8 1837 #define BNXT_STATE_NAPI_DISABLED 9 1838 1839 #define BNXT_NO_FW_ACCESS(bp) \ 1840 (test_bit(BNXT_STATE_FW_FATAL_COND, &(bp)->state) || \ 1841 pci_channel_offline((bp)->pdev)) 1842 1843 struct bnxt_irq *irq_tbl; 1844 int total_irqs; 1845 u8 mac_addr[ETH_ALEN]; 1846 1847 #ifdef CONFIG_BNXT_DCB 1848 struct ieee_pfc *ieee_pfc; 1849 struct ieee_ets *ieee_ets; 1850 u8 dcbx_cap; 1851 u8 default_pri; 1852 u8 max_dscp_value; 1853 #endif /* CONFIG_BNXT_DCB */ 1854 1855 u32 msg_enable; 1856 1857 u32 fw_cap; 1858 #define BNXT_FW_CAP_SHORT_CMD 0x00000001 1859 #define BNXT_FW_CAP_LLDP_AGENT 0x00000002 1860 #define BNXT_FW_CAP_DCBX_AGENT 0x00000004 1861 #define BNXT_FW_CAP_NEW_RM 0x00000008 1862 #define BNXT_FW_CAP_IF_CHANGE 0x00000010 1863 #define BNXT_FW_CAP_KONG_MB_CHNL 0x00000080 1864 #define BNXT_FW_CAP_OVS_64BIT_HANDLE 0x00000400 1865 #define BNXT_FW_CAP_TRUSTED_VF 0x00000800 1866 #define BNXT_FW_CAP_ERROR_RECOVERY 0x00002000 1867 #define BNXT_FW_CAP_PKG_VER 0x00004000 1868 #define BNXT_FW_CAP_CFA_ADV_FLOW 0x00008000 1869 #define BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V2 0x00010000 1870 #define BNXT_FW_CAP_PCIE_STATS_SUPPORTED 0x00020000 1871 #define BNXT_FW_CAP_EXT_STATS_SUPPORTED 0x00040000 1872 #define BNXT_FW_CAP_ERR_RECOVER_RELOAD 0x00100000 1873 #define BNXT_FW_CAP_HOT_RESET 0x00200000 1874 #define BNXT_FW_CAP_VLAN_RX_STRIP 0x01000000 1875 #define BNXT_FW_CAP_VLAN_TX_INSERT 0x02000000 1876 #define BNXT_FW_CAP_EXT_HW_STATS_SUPPORTED 0x04000000 1877 #define BNXT_FW_CAP_PTP_PPS 0x10000000 1878 #define BNXT_FW_CAP_RING_MONITOR 0x40000000 1879 1880 #define BNXT_NEW_RM(bp) ((bp)->fw_cap & BNXT_FW_CAP_NEW_RM) 1881 u32 hwrm_spec_code; 1882 u16 hwrm_cmd_seq; 1883 u16 hwrm_cmd_kong_seq; 1884 struct dma_pool *hwrm_dma_pool; 1885 struct hlist_head hwrm_pending_list; 1886 1887 struct rtnl_link_stats64 net_stats_prev; 1888 struct bnxt_stats_mem port_stats; 1889 struct bnxt_stats_mem rx_port_stats_ext; 1890 struct bnxt_stats_mem tx_port_stats_ext; 1891 u16 fw_rx_stats_ext_size; 1892 u16 fw_tx_stats_ext_size; 1893 u16 hw_ring_stats_size; 1894 u8 pri2cos_idx[8]; 1895 u8 pri2cos_valid; 1896 1897 u16 hwrm_max_req_len; 1898 u16 hwrm_max_ext_req_len; 1899 int hwrm_cmd_timeout; 1900 struct mutex hwrm_cmd_lock; /* serialize hwrm messages */ 1901 struct hwrm_ver_get_output ver_resp; 1902 #define FW_VER_STR_LEN 32 1903 #define BC_HWRM_STR_LEN 21 1904 #define PHY_VER_STR_LEN (FW_VER_STR_LEN - BC_HWRM_STR_LEN) 1905 char fw_ver_str[FW_VER_STR_LEN]; 1906 char hwrm_ver_supp[FW_VER_STR_LEN]; 1907 char nvm_cfg_ver[FW_VER_STR_LEN]; 1908 u64 fw_ver_code; 1909 #define BNXT_FW_VER_CODE(maj, min, bld, rsv) \ 1910 ((u64)(maj) << 48 | (u64)(min) << 32 | (u64)(bld) << 16 | (rsv)) 1911 #define BNXT_FW_MAJ(bp) ((bp)->fw_ver_code >> 48) 1912 1913 u16 vxlan_fw_dst_port_id; 1914 u16 nge_fw_dst_port_id; 1915 __be16 vxlan_port; 1916 __be16 nge_port; 1917 u8 port_partition_type; 1918 u8 port_count; 1919 u16 br_mode; 1920 1921 struct bnxt_coal_cap coal_cap; 1922 struct bnxt_coal rx_coal; 1923 struct bnxt_coal tx_coal; 1924 1925 u32 stats_coal_ticks; 1926 #define BNXT_DEF_STATS_COAL_TICKS 1000000 1927 #define BNXT_MIN_STATS_COAL_TICKS 250000 1928 #define BNXT_MAX_STATS_COAL_TICKS 1000000 1929 1930 struct work_struct sp_task; 1931 unsigned long sp_event; 1932 #define BNXT_RX_MASK_SP_EVENT 0 1933 #define BNXT_RX_NTP_FLTR_SP_EVENT 1 1934 #define BNXT_LINK_CHNG_SP_EVENT 2 1935 #define BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT 3 1936 #define BNXT_RESET_TASK_SP_EVENT 6 1937 #define BNXT_RST_RING_SP_EVENT 7 1938 #define BNXT_HWRM_PF_UNLOAD_SP_EVENT 8 1939 #define BNXT_PERIODIC_STATS_SP_EVENT 9 1940 #define BNXT_HWRM_PORT_MODULE_SP_EVENT 10 1941 #define BNXT_RESET_TASK_SILENT_SP_EVENT 11 1942 #define BNXT_LINK_SPEED_CHNG_SP_EVENT 14 1943 #define BNXT_FLOW_STATS_SP_EVENT 15 1944 #define BNXT_UPDATE_PHY_SP_EVENT 16 1945 #define BNXT_RING_COAL_NOW_SP_EVENT 17 1946 #define BNXT_FW_RESET_NOTIFY_SP_EVENT 18 1947 #define BNXT_FW_EXCEPTION_SP_EVENT 19 1948 #define BNXT_LINK_CFG_CHANGE_SP_EVENT 21 1949 #define BNXT_FW_ECHO_REQUEST_SP_EVENT 23 1950 1951 struct delayed_work fw_reset_task; 1952 int fw_reset_state; 1953 #define BNXT_FW_RESET_STATE_POLL_VF 1 1954 #define BNXT_FW_RESET_STATE_RESET_FW 2 1955 #define BNXT_FW_RESET_STATE_ENABLE_DEV 3 1956 #define BNXT_FW_RESET_STATE_POLL_FW 4 1957 #define BNXT_FW_RESET_STATE_OPENING 5 1958 #define BNXT_FW_RESET_STATE_POLL_FW_DOWN 6 1959 1960 u16 fw_reset_min_dsecs; 1961 #define BNXT_DFLT_FW_RST_MIN_DSECS 20 1962 u16 fw_reset_max_dsecs; 1963 #define BNXT_DFLT_FW_RST_MAX_DSECS 60 1964 unsigned long fw_reset_timestamp; 1965 1966 struct bnxt_fw_health *fw_health; 1967 1968 struct bnxt_hw_resc hw_resc; 1969 struct bnxt_pf_info pf; 1970 struct bnxt_ctx_mem_info *ctx; 1971 #ifdef CONFIG_BNXT_SRIOV 1972 int nr_vfs; 1973 struct bnxt_vf_info vf; 1974 wait_queue_head_t sriov_cfg_wait; 1975 bool sriov_cfg; 1976 #define BNXT_SRIOV_CFG_WAIT_TMO msecs_to_jiffies(10000) 1977 1978 /* lock to protect VF-rep creation/cleanup via 1979 * multiple paths such as ->sriov_configure() and 1980 * devlink ->eswitch_mode_set() 1981 */ 1982 struct mutex sriov_lock; 1983 #endif 1984 1985 #if BITS_PER_LONG == 32 1986 /* ensure atomic 64-bit doorbell writes on 32-bit systems. */ 1987 spinlock_t db_lock; 1988 #endif 1989 int db_size; 1990 1991 #define BNXT_NTP_FLTR_MAX_FLTR 4096 1992 #define BNXT_NTP_FLTR_HASH_SIZE 512 1993 #define BNXT_NTP_FLTR_HASH_MASK (BNXT_NTP_FLTR_HASH_SIZE - 1) 1994 struct hlist_head ntp_fltr_hash_tbl[BNXT_NTP_FLTR_HASH_SIZE]; 1995 spinlock_t ntp_fltr_lock; /* for hash table add, del */ 1996 1997 unsigned long *ntp_fltr_bmap; 1998 int ntp_fltr_count; 1999 2000 /* To protect link related settings during link changes and 2001 * ethtool settings changes. 2002 */ 2003 struct mutex link_lock; 2004 struct bnxt_link_info link_info; 2005 struct ethtool_eee eee; 2006 u32 lpi_tmr_lo; 2007 u32 lpi_tmr_hi; 2008 2009 /* copied from flags in hwrm_port_phy_qcaps_output */ 2010 u8 phy_flags; 2011 #define BNXT_PHY_FL_EEE_CAP PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED 2012 #define BNXT_PHY_FL_EXT_LPBK PORT_PHY_QCAPS_RESP_FLAGS_EXTERNAL_LPBK_SUPPORTED 2013 #define BNXT_PHY_FL_AN_PHY_LPBK PORT_PHY_QCAPS_RESP_FLAGS_AUTONEG_LPBK_SUPPORTED 2014 #define BNXT_PHY_FL_SHARED_PORT_CFG PORT_PHY_QCAPS_RESP_FLAGS_SHARED_PHY_CFG_SUPPORTED 2015 #define BNXT_PHY_FL_PORT_STATS_NO_RESET PORT_PHY_QCAPS_RESP_FLAGS_CUMULATIVE_COUNTERS_ON_RESET 2016 #define BNXT_PHY_FL_NO_PHY_LPBK PORT_PHY_QCAPS_RESP_FLAGS_LOCAL_LPBK_NOT_SUPPORTED 2017 #define BNXT_PHY_FL_FW_MANAGED_LKDN PORT_PHY_QCAPS_RESP_FLAGS_FW_MANAGED_LINK_DOWN 2018 #define BNXT_PHY_FL_NO_FCS PORT_PHY_QCAPS_RESP_FLAGS_NO_FCS 2019 2020 u8 num_tests; 2021 struct bnxt_test_info *test_info; 2022 2023 u8 wol_filter_id; 2024 u8 wol; 2025 2026 u8 num_leds; 2027 struct bnxt_led_info leds[BNXT_MAX_LED]; 2028 u16 dump_flag; 2029 #define BNXT_DUMP_LIVE 0 2030 #define BNXT_DUMP_CRASH 1 2031 2032 struct bpf_prog *xdp_prog; 2033 2034 struct bnxt_ptp_cfg *ptp_cfg; 2035 2036 /* devlink interface and vf-rep structs */ 2037 struct devlink *dl; 2038 struct devlink_port dl_port; 2039 enum devlink_eswitch_mode eswitch_mode; 2040 struct bnxt_vf_rep **vf_reps; /* array of vf-rep ptrs */ 2041 u16 *cfa_code_map; /* cfa_code -> vf_idx map */ 2042 u8 dsn[8]; 2043 struct bnxt_tc_info *tc_info; 2044 struct list_head tc_indr_block_list; 2045 struct dentry *debugfs_pdev; 2046 struct device *hwmon_dev; 2047 }; 2048 2049 #define BNXT_NUM_RX_RING_STATS 8 2050 #define BNXT_NUM_TX_RING_STATS 8 2051 #define BNXT_NUM_TPA_RING_STATS 4 2052 #define BNXT_NUM_TPA_RING_STATS_P5 5 2053 #define BNXT_NUM_TPA_RING_STATS_P5_SR2 6 2054 2055 #define BNXT_RING_STATS_SIZE_P5 \ 2056 ((BNXT_NUM_RX_RING_STATS + BNXT_NUM_TX_RING_STATS + \ 2057 BNXT_NUM_TPA_RING_STATS_P5) * 8) 2058 2059 #define BNXT_RING_STATS_SIZE_P5_SR2 \ 2060 ((BNXT_NUM_RX_RING_STATS + BNXT_NUM_TX_RING_STATS + \ 2061 BNXT_NUM_TPA_RING_STATS_P5_SR2) * 8) 2062 2063 #define BNXT_GET_RING_STATS64(sw, counter) \ 2064 (*((sw) + offsetof(struct ctx_hw_stats, counter) / 8)) 2065 2066 #define BNXT_GET_RX_PORT_STATS64(sw, counter) \ 2067 (*((sw) + offsetof(struct rx_port_stats, counter) / 8)) 2068 2069 #define BNXT_GET_TX_PORT_STATS64(sw, counter) \ 2070 (*((sw) + offsetof(struct tx_port_stats, counter) / 8)) 2071 2072 #define BNXT_PORT_STATS_SIZE \ 2073 (sizeof(struct rx_port_stats) + sizeof(struct tx_port_stats) + 1024) 2074 2075 #define BNXT_TX_PORT_STATS_BYTE_OFFSET \ 2076 (sizeof(struct rx_port_stats) + 512) 2077 2078 #define BNXT_RX_STATS_OFFSET(counter) \ 2079 (offsetof(struct rx_port_stats, counter) / 8) 2080 2081 #define BNXT_TX_STATS_OFFSET(counter) \ 2082 ((offsetof(struct tx_port_stats, counter) + \ 2083 BNXT_TX_PORT_STATS_BYTE_OFFSET) / 8) 2084 2085 #define BNXT_RX_STATS_EXT_OFFSET(counter) \ 2086 (offsetof(struct rx_port_stats_ext, counter) / 8) 2087 2088 #define BNXT_TX_STATS_EXT_OFFSET(counter) \ 2089 (offsetof(struct tx_port_stats_ext, counter) / 8) 2090 2091 #define BNXT_HW_FEATURE_VLAN_ALL_RX \ 2092 (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX) 2093 #define BNXT_HW_FEATURE_VLAN_ALL_TX \ 2094 (NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_STAG_TX) 2095 2096 #define I2C_DEV_ADDR_A0 0xa0 2097 #define I2C_DEV_ADDR_A2 0xa2 2098 #define SFF_DIAG_SUPPORT_OFFSET 0x5c 2099 #define SFF_MODULE_ID_SFP 0x3 2100 #define SFF_MODULE_ID_QSFP 0xc 2101 #define SFF_MODULE_ID_QSFP_PLUS 0xd 2102 #define SFF_MODULE_ID_QSFP28 0x11 2103 #define BNXT_MAX_PHY_I2C_RESP_SIZE 64 2104 2105 static inline u32 bnxt_tx_avail(struct bnxt *bp, struct bnxt_tx_ring_info *txr) 2106 { 2107 /* Tell compiler to fetch tx indices from memory. */ 2108 barrier(); 2109 2110 return bp->tx_ring_size - 2111 ((txr->tx_prod - txr->tx_cons) & bp->tx_ring_mask); 2112 } 2113 2114 static inline void bnxt_writeq(struct bnxt *bp, u64 val, 2115 volatile void __iomem *addr) 2116 { 2117 #if BITS_PER_LONG == 32 2118 spin_lock(&bp->db_lock); 2119 lo_hi_writeq(val, addr); 2120 spin_unlock(&bp->db_lock); 2121 #else 2122 writeq(val, addr); 2123 #endif 2124 } 2125 2126 static inline void bnxt_writeq_relaxed(struct bnxt *bp, u64 val, 2127 volatile void __iomem *addr) 2128 { 2129 #if BITS_PER_LONG == 32 2130 spin_lock(&bp->db_lock); 2131 lo_hi_writeq_relaxed(val, addr); 2132 spin_unlock(&bp->db_lock); 2133 #else 2134 writeq_relaxed(val, addr); 2135 #endif 2136 } 2137 2138 /* For TX and RX ring doorbells with no ordering guarantee*/ 2139 static inline void bnxt_db_write_relaxed(struct bnxt *bp, 2140 struct bnxt_db_info *db, u32 idx) 2141 { 2142 if (bp->flags & BNXT_FLAG_CHIP_P5) { 2143 bnxt_writeq_relaxed(bp, db->db_key64 | idx, db->doorbell); 2144 } else { 2145 u32 db_val = db->db_key32 | idx; 2146 2147 writel_relaxed(db_val, db->doorbell); 2148 if (bp->flags & BNXT_FLAG_DOUBLE_DB) 2149 writel_relaxed(db_val, db->doorbell); 2150 } 2151 } 2152 2153 /* For TX and RX ring doorbells */ 2154 static inline void bnxt_db_write(struct bnxt *bp, struct bnxt_db_info *db, 2155 u32 idx) 2156 { 2157 if (bp->flags & BNXT_FLAG_CHIP_P5) { 2158 bnxt_writeq(bp, db->db_key64 | idx, db->doorbell); 2159 } else { 2160 u32 db_val = db->db_key32 | idx; 2161 2162 writel(db_val, db->doorbell); 2163 if (bp->flags & BNXT_FLAG_DOUBLE_DB) 2164 writel(db_val, db->doorbell); 2165 } 2166 } 2167 2168 extern const u16 bnxt_lhint_arr[]; 2169 2170 int bnxt_alloc_rx_data(struct bnxt *bp, struct bnxt_rx_ring_info *rxr, 2171 u16 prod, gfp_t gfp); 2172 void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons, void *data); 2173 u32 bnxt_fw_health_readl(struct bnxt *bp, int reg_idx); 2174 void bnxt_set_tpa_flags(struct bnxt *bp); 2175 void bnxt_set_ring_params(struct bnxt *); 2176 int bnxt_set_rx_skb_mode(struct bnxt *bp, bool page_mode); 2177 int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp, unsigned long *bmap, 2178 int bmap_size, bool async_only); 2179 int bnxt_get_nr_rss_ctxs(struct bnxt *bp, int rx_rings); 2180 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id); 2181 int __bnxt_hwrm_get_tx_rings(struct bnxt *bp, u16 fid, int *tx_rings); 2182 int bnxt_nq_rings_in_use(struct bnxt *bp); 2183 int bnxt_hwrm_set_coal(struct bnxt *); 2184 unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt *bp); 2185 unsigned int bnxt_get_avail_stat_ctxs_for_en(struct bnxt *bp); 2186 unsigned int bnxt_get_max_func_cp_rings(struct bnxt *bp); 2187 unsigned int bnxt_get_avail_cp_rings_for_en(struct bnxt *bp); 2188 int bnxt_get_avail_msix(struct bnxt *bp, int num); 2189 int bnxt_reserve_rings(struct bnxt *bp, bool irq_re_init); 2190 void bnxt_tx_disable(struct bnxt *bp); 2191 void bnxt_tx_enable(struct bnxt *bp); 2192 int bnxt_update_link(struct bnxt *bp, bool chng_link_state); 2193 int bnxt_hwrm_set_pause(struct bnxt *); 2194 int bnxt_hwrm_set_link_setting(struct bnxt *, bool, bool); 2195 int bnxt_hwrm_alloc_wol_fltr(struct bnxt *bp); 2196 int bnxt_hwrm_free_wol_fltr(struct bnxt *bp); 2197 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp, bool all); 2198 bool bnxt_is_fw_healthy(struct bnxt *bp); 2199 int bnxt_hwrm_fw_set_time(struct bnxt *); 2200 int bnxt_open_nic(struct bnxt *, bool, bool); 2201 int bnxt_half_open_nic(struct bnxt *bp); 2202 void bnxt_half_close_nic(struct bnxt *bp); 2203 int bnxt_close_nic(struct bnxt *, bool, bool); 2204 int bnxt_dbg_hwrm_rd_reg(struct bnxt *bp, u32 reg_off, u16 num_words, 2205 u32 *reg_buf); 2206 void bnxt_fw_exception(struct bnxt *bp); 2207 void bnxt_fw_reset(struct bnxt *bp); 2208 int bnxt_check_rings(struct bnxt *bp, int tx, int rx, bool sh, int tcs, 2209 int tx_xdp); 2210 int bnxt_setup_mq_tc(struct net_device *dev, u8 tc); 2211 int bnxt_get_max_rings(struct bnxt *, int *, int *, bool); 2212 int bnxt_restore_pf_fw_resources(struct bnxt *bp); 2213 int bnxt_get_port_parent_id(struct net_device *dev, 2214 struct netdev_phys_item_id *ppid); 2215 void bnxt_dim_work(struct work_struct *work); 2216 int bnxt_hwrm_set_ring_coal(struct bnxt *bp, struct bnxt_napi *bnapi); 2217 2218 #endif 2219