1 /* Broadcom NetXtreme-C/E network driver.
2  *
3  * Copyright (c) 2014-2016 Broadcom Corporation
4  * Copyright (c) 2016-2018 Broadcom Limited
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation.
9  */
10 
11 #ifndef BNXT_H
12 #define BNXT_H
13 
14 #define DRV_MODULE_NAME		"bnxt_en"
15 
16 /* DO NOT CHANGE DRV_VER_* defines
17  * FIXME: Delete them
18  */
19 #define DRV_VER_MAJ	1
20 #define DRV_VER_MIN	10
21 #define DRV_VER_UPD	2
22 
23 #include <linux/ethtool.h>
24 #include <linux/interrupt.h>
25 #include <linux/rhashtable.h>
26 #include <linux/crash_dump.h>
27 #include <linux/auxiliary_bus.h>
28 #include <net/devlink.h>
29 #include <net/dst_metadata.h>
30 #include <net/xdp.h>
31 #include <linux/dim.h>
32 #include <linux/io-64-nonatomic-lo-hi.h>
33 #ifdef CONFIG_TEE_BNXT_FW
34 #include <linux/firmware/broadcom/tee_bnxt_fw.h>
35 #endif
36 
37 extern struct list_head bnxt_block_cb_list;
38 
39 struct page_pool;
40 
41 struct tx_bd {
42 	__le32 tx_bd_len_flags_type;
43 	#define TX_BD_TYPE					(0x3f << 0)
44 	 #define TX_BD_TYPE_SHORT_TX_BD				 (0x00 << 0)
45 	 #define TX_BD_TYPE_LONG_TX_BD				 (0x10 << 0)
46 	#define TX_BD_FLAGS_PACKET_END				(1 << 6)
47 	#define TX_BD_FLAGS_NO_CMPL				(1 << 7)
48 	#define TX_BD_FLAGS_BD_CNT				(0x1f << 8)
49 	 #define TX_BD_FLAGS_BD_CNT_SHIFT			 8
50 	#define TX_BD_FLAGS_LHINT				(3 << 13)
51 	 #define TX_BD_FLAGS_LHINT_SHIFT			 13
52 	 #define TX_BD_FLAGS_LHINT_512_AND_SMALLER		 (0 << 13)
53 	 #define TX_BD_FLAGS_LHINT_512_TO_1023			 (1 << 13)
54 	 #define TX_BD_FLAGS_LHINT_1024_TO_2047			 (2 << 13)
55 	 #define TX_BD_FLAGS_LHINT_2048_AND_LARGER		 (3 << 13)
56 	#define TX_BD_FLAGS_COAL_NOW				(1 << 15)
57 	#define TX_BD_LEN					(0xffff << 16)
58 	 #define TX_BD_LEN_SHIFT				 16
59 
60 	u32 tx_bd_opaque;
61 	__le64 tx_bd_haddr;
62 } __packed;
63 
64 struct tx_bd_ext {
65 	__le32 tx_bd_hsize_lflags;
66 	#define TX_BD_FLAGS_TCP_UDP_CHKSUM			(1 << 0)
67 	#define TX_BD_FLAGS_IP_CKSUM				(1 << 1)
68 	#define TX_BD_FLAGS_NO_CRC				(1 << 2)
69 	#define TX_BD_FLAGS_STAMP				(1 << 3)
70 	#define TX_BD_FLAGS_T_IP_CHKSUM				(1 << 4)
71 	#define TX_BD_FLAGS_LSO					(1 << 5)
72 	#define TX_BD_FLAGS_IPID_FMT				(1 << 6)
73 	#define TX_BD_FLAGS_T_IPID				(1 << 7)
74 	#define TX_BD_HSIZE					(0xff << 16)
75 	 #define TX_BD_HSIZE_SHIFT				 16
76 
77 	__le32 tx_bd_mss;
78 	__le32 tx_bd_cfa_action;
79 	#define TX_BD_CFA_ACTION				(0xffff << 16)
80 	 #define TX_BD_CFA_ACTION_SHIFT				 16
81 
82 	__le32 tx_bd_cfa_meta;
83 	#define TX_BD_CFA_META_MASK                             0xfffffff
84 	#define TX_BD_CFA_META_VID_MASK                         0xfff
85 	#define TX_BD_CFA_META_PRI_MASK                         (0xf << 12)
86 	 #define TX_BD_CFA_META_PRI_SHIFT                        12
87 	#define TX_BD_CFA_META_TPID_MASK                        (3 << 16)
88 	 #define TX_BD_CFA_META_TPID_SHIFT                       16
89 	#define TX_BD_CFA_META_KEY                              (0xf << 28)
90 	 #define TX_BD_CFA_META_KEY_SHIFT			 28
91 	#define TX_BD_CFA_META_KEY_VLAN                         (1 << 28)
92 };
93 
94 #define BNXT_TX_PTP_IS_SET(lflags) ((lflags) & cpu_to_le32(TX_BD_FLAGS_STAMP))
95 
96 struct rx_bd {
97 	__le32 rx_bd_len_flags_type;
98 	#define RX_BD_TYPE					(0x3f << 0)
99 	 #define RX_BD_TYPE_RX_PACKET_BD			 0x4
100 	 #define RX_BD_TYPE_RX_BUFFER_BD			 0x5
101 	 #define RX_BD_TYPE_RX_AGG_BD				 0x6
102 	 #define RX_BD_TYPE_16B_BD_SIZE				 (0 << 4)
103 	 #define RX_BD_TYPE_32B_BD_SIZE				 (1 << 4)
104 	 #define RX_BD_TYPE_48B_BD_SIZE				 (2 << 4)
105 	 #define RX_BD_TYPE_64B_BD_SIZE				 (3 << 4)
106 	#define RX_BD_FLAGS_SOP					(1 << 6)
107 	#define RX_BD_FLAGS_EOP					(1 << 7)
108 	#define RX_BD_FLAGS_BUFFERS				(3 << 8)
109 	 #define RX_BD_FLAGS_1_BUFFER_PACKET			 (0 << 8)
110 	 #define RX_BD_FLAGS_2_BUFFER_PACKET			 (1 << 8)
111 	 #define RX_BD_FLAGS_3_BUFFER_PACKET			 (2 << 8)
112 	 #define RX_BD_FLAGS_4_BUFFER_PACKET			 (3 << 8)
113 	#define RX_BD_LEN					(0xffff << 16)
114 	 #define RX_BD_LEN_SHIFT				 16
115 
116 	u32 rx_bd_opaque;
117 	__le64 rx_bd_haddr;
118 };
119 
120 struct tx_cmp {
121 	__le32 tx_cmp_flags_type;
122 	#define CMP_TYPE					(0x3f << 0)
123 	 #define CMP_TYPE_TX_L2_CMP				 0
124 	 #define CMP_TYPE_RX_L2_CMP				 17
125 	 #define CMP_TYPE_RX_AGG_CMP				 18
126 	 #define CMP_TYPE_RX_L2_TPA_START_CMP			 19
127 	 #define CMP_TYPE_RX_L2_TPA_END_CMP			 21
128 	 #define CMP_TYPE_RX_TPA_AGG_CMP			 22
129 	 #define CMP_TYPE_STATUS_CMP				 32
130 	 #define CMP_TYPE_REMOTE_DRIVER_REQ			 34
131 	 #define CMP_TYPE_REMOTE_DRIVER_RESP			 36
132 	 #define CMP_TYPE_ERROR_STATUS				 48
133 	 #define CMPL_BASE_TYPE_STAT_EJECT			 0x1aUL
134 	 #define CMPL_BASE_TYPE_HWRM_DONE			 0x20UL
135 	 #define CMPL_BASE_TYPE_HWRM_FWD_REQ			 0x22UL
136 	 #define CMPL_BASE_TYPE_HWRM_FWD_RESP			 0x24UL
137 	 #define CMPL_BASE_TYPE_HWRM_ASYNC_EVENT		 0x2eUL
138 
139 	#define TX_CMP_FLAGS_ERROR				(1 << 6)
140 	#define TX_CMP_FLAGS_PUSH				(1 << 7)
141 
142 	u32 tx_cmp_opaque;
143 	__le32 tx_cmp_errors_v;
144 	#define TX_CMP_V					(1 << 0)
145 	#define TX_CMP_ERRORS_BUFFER_ERROR			(7 << 1)
146 	 #define TX_CMP_ERRORS_BUFFER_ERROR_NO_ERROR		 0
147 	 #define TX_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT		 2
148 	 #define TX_CMP_ERRORS_BUFFER_ERROR_INVALID_STAG	 4
149 	 #define TX_CMP_ERRORS_BUFFER_ERROR_STAG_BOUNDS		 5
150 	 #define TX_CMP_ERRORS_ZERO_LENGTH_PKT			 (1 << 4)
151 	 #define TX_CMP_ERRORS_EXCESSIVE_BD_LEN			 (1 << 5)
152 	 #define TX_CMP_ERRORS_DMA_ERROR			 (1 << 6)
153 	 #define TX_CMP_ERRORS_HINT_TOO_SHORT			 (1 << 7)
154 
155 	__le32 tx_cmp_unsed_3;
156 };
157 
158 struct rx_cmp {
159 	__le32 rx_cmp_len_flags_type;
160 	#define RX_CMP_CMP_TYPE					(0x3f << 0)
161 	#define RX_CMP_FLAGS_ERROR				(1 << 6)
162 	#define RX_CMP_FLAGS_PLACEMENT				(7 << 7)
163 	#define RX_CMP_FLAGS_RSS_VALID				(1 << 10)
164 	#define RX_CMP_FLAGS_PKT_METADATA_PRESENT		(1 << 11)
165 	 #define RX_CMP_FLAGS_ITYPES_SHIFT			 12
166 	 #define RX_CMP_FLAGS_ITYPES_MASK			 0xf000
167 	 #define RX_CMP_FLAGS_ITYPE_UNKNOWN			 (0 << 12)
168 	 #define RX_CMP_FLAGS_ITYPE_IP				 (1 << 12)
169 	 #define RX_CMP_FLAGS_ITYPE_TCP				 (2 << 12)
170 	 #define RX_CMP_FLAGS_ITYPE_UDP				 (3 << 12)
171 	 #define RX_CMP_FLAGS_ITYPE_FCOE			 (4 << 12)
172 	 #define RX_CMP_FLAGS_ITYPE_ROCE			 (5 << 12)
173 	 #define RX_CMP_FLAGS_ITYPE_PTP_WO_TS			 (8 << 12)
174 	 #define RX_CMP_FLAGS_ITYPE_PTP_W_TS			 (9 << 12)
175 	#define RX_CMP_LEN					(0xffff << 16)
176 	 #define RX_CMP_LEN_SHIFT				 16
177 
178 	u32 rx_cmp_opaque;
179 	__le32 rx_cmp_misc_v1;
180 	#define RX_CMP_V1					(1 << 0)
181 	#define RX_CMP_AGG_BUFS					(0x1f << 1)
182 	 #define RX_CMP_AGG_BUFS_SHIFT				 1
183 	#define RX_CMP_RSS_HASH_TYPE				(0x7f << 9)
184 	 #define RX_CMP_RSS_HASH_TYPE_SHIFT			 9
185 	#define RX_CMP_PAYLOAD_OFFSET				(0xff << 16)
186 	 #define RX_CMP_PAYLOAD_OFFSET_SHIFT			 16
187 
188 	__le32 rx_cmp_rss_hash;
189 };
190 
191 #define BNXT_PTP_RX_TS_VALID(flags)				\
192 	(((flags) & RX_CMP_FLAGS_ITYPES_MASK) == RX_CMP_FLAGS_ITYPE_PTP_W_TS)
193 
194 #define BNXT_ALL_RX_TS_VALID(flags)				\
195 	!((flags) & RX_CMP_FLAGS_PKT_METADATA_PRESENT)
196 
197 #define RX_CMP_HASH_VALID(rxcmp)				\
198 	((rxcmp)->rx_cmp_len_flags_type & cpu_to_le32(RX_CMP_FLAGS_RSS_VALID))
199 
200 #define RSS_PROFILE_ID_MASK	0x1f
201 
202 #define RX_CMP_HASH_TYPE(rxcmp)					\
203 	(((le32_to_cpu((rxcmp)->rx_cmp_misc_v1) & RX_CMP_RSS_HASH_TYPE) >>\
204 	  RX_CMP_RSS_HASH_TYPE_SHIFT) & RSS_PROFILE_ID_MASK)
205 
206 struct rx_cmp_ext {
207 	__le32 rx_cmp_flags2;
208 	#define RX_CMP_FLAGS2_IP_CS_CALC			0x1
209 	#define RX_CMP_FLAGS2_L4_CS_CALC			(0x1 << 1)
210 	#define RX_CMP_FLAGS2_T_IP_CS_CALC			(0x1 << 2)
211 	#define RX_CMP_FLAGS2_T_L4_CS_CALC			(0x1 << 3)
212 	#define RX_CMP_FLAGS2_META_FORMAT_VLAN			(0x1 << 4)
213 	__le32 rx_cmp_meta_data;
214 	#define RX_CMP_FLAGS2_METADATA_TCI_MASK			0xffff
215 	#define RX_CMP_FLAGS2_METADATA_VID_MASK			0xfff
216 	#define RX_CMP_FLAGS2_METADATA_TPID_MASK		0xffff0000
217 	 #define RX_CMP_FLAGS2_METADATA_TPID_SFT		 16
218 	__le32 rx_cmp_cfa_code_errors_v2;
219 	#define RX_CMP_V					(1 << 0)
220 	#define RX_CMPL_ERRORS_MASK				(0x7fff << 1)
221 	 #define RX_CMPL_ERRORS_SFT				 1
222 	#define RX_CMPL_ERRORS_BUFFER_ERROR_MASK		(0x7 << 1)
223 	 #define RX_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER		 (0x0 << 1)
224 	 #define RX_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT	 (0x1 << 1)
225 	 #define RX_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP	 (0x2 << 1)
226 	 #define RX_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT		 (0x3 << 1)
227 	#define RX_CMPL_ERRORS_IP_CS_ERROR			(0x1 << 4)
228 	#define RX_CMPL_ERRORS_L4_CS_ERROR			(0x1 << 5)
229 	#define RX_CMPL_ERRORS_T_IP_CS_ERROR			(0x1 << 6)
230 	#define RX_CMPL_ERRORS_T_L4_CS_ERROR			(0x1 << 7)
231 	#define RX_CMPL_ERRORS_CRC_ERROR			(0x1 << 8)
232 	#define RX_CMPL_ERRORS_T_PKT_ERROR_MASK			(0x7 << 9)
233 	 #define RX_CMPL_ERRORS_T_PKT_ERROR_NO_ERROR		 (0x0 << 9)
234 	 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION	 (0x1 << 9)
235 	 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN	 (0x2 << 9)
236 	 #define RX_CMPL_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR	 (0x3 << 9)
237 	 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR	 (0x4 << 9)
238 	 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR	 (0x5 << 9)
239 	 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL	 (0x6 << 9)
240 	#define RX_CMPL_ERRORS_PKT_ERROR_MASK			(0xf << 12)
241 	 #define RX_CMPL_ERRORS_PKT_ERROR_NO_ERROR		 (0x0 << 12)
242 	 #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_VERSION	 (0x1 << 12)
243 	 #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN	 (0x2 << 12)
244 	 #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_TTL		 (0x3 << 12)
245 	 #define RX_CMPL_ERRORS_PKT_ERROR_IP_TOTAL_ERROR	 (0x4 << 12)
246 	 #define RX_CMPL_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR	 (0x5 << 12)
247 	 #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN	 (0x6 << 12)
248 	 #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL (0x7 << 12)
249 	 #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN	 (0x8 << 12)
250 
251 	#define RX_CMPL_CFA_CODE_MASK				(0xffff << 16)
252 	 #define RX_CMPL_CFA_CODE_SFT				 16
253 
254 	__le32 rx_cmp_timestamp;
255 };
256 
257 #define RX_CMP_L2_ERRORS						\
258 	cpu_to_le32(RX_CMPL_ERRORS_BUFFER_ERROR_MASK | RX_CMPL_ERRORS_CRC_ERROR)
259 
260 #define RX_CMP_L4_CS_BITS						\
261 	(cpu_to_le32(RX_CMP_FLAGS2_L4_CS_CALC | RX_CMP_FLAGS2_T_L4_CS_CALC))
262 
263 #define RX_CMP_L4_CS_ERR_BITS						\
264 	(cpu_to_le32(RX_CMPL_ERRORS_L4_CS_ERROR | RX_CMPL_ERRORS_T_L4_CS_ERROR))
265 
266 #define RX_CMP_L4_CS_OK(rxcmp1)						\
267 	    (((rxcmp1)->rx_cmp_flags2 &	RX_CMP_L4_CS_BITS) &&		\
268 	     !((rxcmp1)->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS))
269 
270 #define RX_CMP_ENCAP(rxcmp1)						\
271 	    ((le32_to_cpu((rxcmp1)->rx_cmp_flags2) &			\
272 	     RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3)
273 
274 #define RX_CMP_CFA_CODE(rxcmpl1)					\
275 	((le32_to_cpu((rxcmpl1)->rx_cmp_cfa_code_errors_v2) &		\
276 	  RX_CMPL_CFA_CODE_MASK) >> RX_CMPL_CFA_CODE_SFT)
277 
278 struct rx_agg_cmp {
279 	__le32 rx_agg_cmp_len_flags_type;
280 	#define RX_AGG_CMP_TYPE					(0x3f << 0)
281 	#define RX_AGG_CMP_LEN					(0xffff << 16)
282 	 #define RX_AGG_CMP_LEN_SHIFT				 16
283 	u32 rx_agg_cmp_opaque;
284 	__le32 rx_agg_cmp_v;
285 	#define RX_AGG_CMP_V					(1 << 0)
286 	#define RX_AGG_CMP_AGG_ID				(0xffff << 16)
287 	 #define RX_AGG_CMP_AGG_ID_SHIFT			 16
288 	__le32 rx_agg_cmp_unused;
289 };
290 
291 #define TPA_AGG_AGG_ID(rx_agg)				\
292 	((le32_to_cpu((rx_agg)->rx_agg_cmp_v) &		\
293 	 RX_AGG_CMP_AGG_ID) >> RX_AGG_CMP_AGG_ID_SHIFT)
294 
295 struct rx_tpa_start_cmp {
296 	__le32 rx_tpa_start_cmp_len_flags_type;
297 	#define RX_TPA_START_CMP_TYPE				(0x3f << 0)
298 	#define RX_TPA_START_CMP_FLAGS				(0x3ff << 6)
299 	 #define RX_TPA_START_CMP_FLAGS_SHIFT			 6
300 	#define RX_TPA_START_CMP_FLAGS_ERROR			(0x1 << 6)
301 	#define RX_TPA_START_CMP_FLAGS_PLACEMENT		(0x7 << 7)
302 	 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_SHIFT		 7
303 	 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_JUMBO		 (0x1 << 7)
304 	 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_HDS		 (0x2 << 7)
305 	 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_GRO_JUMBO	 (0x5 << 7)
306 	 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_GRO_HDS	 (0x6 << 7)
307 	#define RX_TPA_START_CMP_FLAGS_RSS_VALID		(0x1 << 10)
308 	#define RX_TPA_START_CMP_FLAGS_TIMESTAMP		(0x1 << 11)
309 	#define RX_TPA_START_CMP_FLAGS_ITYPES			(0xf << 12)
310 	 #define RX_TPA_START_CMP_FLAGS_ITYPES_SHIFT		 12
311 	 #define RX_TPA_START_CMP_FLAGS_ITYPE_TCP		 (0x2 << 12)
312 	#define RX_TPA_START_CMP_LEN				(0xffff << 16)
313 	 #define RX_TPA_START_CMP_LEN_SHIFT			 16
314 
315 	u32 rx_tpa_start_cmp_opaque;
316 	__le32 rx_tpa_start_cmp_misc_v1;
317 	#define RX_TPA_START_CMP_V1				(0x1 << 0)
318 	#define RX_TPA_START_CMP_RSS_HASH_TYPE			(0x7f << 9)
319 	 #define RX_TPA_START_CMP_RSS_HASH_TYPE_SHIFT		 9
320 	#define RX_TPA_START_CMP_AGG_ID				(0x7f << 25)
321 	 #define RX_TPA_START_CMP_AGG_ID_SHIFT			 25
322 	#define RX_TPA_START_CMP_AGG_ID_P5			(0xffff << 16)
323 	 #define RX_TPA_START_CMP_AGG_ID_SHIFT_P5		 16
324 
325 	__le32 rx_tpa_start_cmp_rss_hash;
326 };
327 
328 #define TPA_START_HASH_VALID(rx_tpa_start)				\
329 	((rx_tpa_start)->rx_tpa_start_cmp_len_flags_type &		\
330 	 cpu_to_le32(RX_TPA_START_CMP_FLAGS_RSS_VALID))
331 
332 #define TPA_START_HASH_TYPE(rx_tpa_start)				\
333 	(((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) &	\
334 	   RX_TPA_START_CMP_RSS_HASH_TYPE) >>				\
335 	  RX_TPA_START_CMP_RSS_HASH_TYPE_SHIFT) & RSS_PROFILE_ID_MASK)
336 
337 #define TPA_START_AGG_ID(rx_tpa_start)					\
338 	((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) &	\
339 	 RX_TPA_START_CMP_AGG_ID) >> RX_TPA_START_CMP_AGG_ID_SHIFT)
340 
341 #define TPA_START_AGG_ID_P5(rx_tpa_start)				\
342 	((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) &	\
343 	 RX_TPA_START_CMP_AGG_ID_P5) >> RX_TPA_START_CMP_AGG_ID_SHIFT_P5)
344 
345 #define TPA_START_ERROR(rx_tpa_start)					\
346 	((rx_tpa_start)->rx_tpa_start_cmp_len_flags_type &		\
347 	 cpu_to_le32(RX_TPA_START_CMP_FLAGS_ERROR))
348 
349 struct rx_tpa_start_cmp_ext {
350 	__le32 rx_tpa_start_cmp_flags2;
351 	#define RX_TPA_START_CMP_FLAGS2_IP_CS_CALC		(0x1 << 0)
352 	#define RX_TPA_START_CMP_FLAGS2_L4_CS_CALC		(0x1 << 1)
353 	#define RX_TPA_START_CMP_FLAGS2_T_IP_CS_CALC		(0x1 << 2)
354 	#define RX_TPA_START_CMP_FLAGS2_T_L4_CS_CALC		(0x1 << 3)
355 	#define RX_TPA_START_CMP_FLAGS2_IP_TYPE			(0x1 << 8)
356 	#define RX_TPA_START_CMP_FLAGS2_CSUM_CMPL_VALID		(0x1 << 9)
357 	#define RX_TPA_START_CMP_FLAGS2_EXT_META_FORMAT		(0x3 << 10)
358 	 #define RX_TPA_START_CMP_FLAGS2_EXT_META_FORMAT_SHIFT	 10
359 	#define RX_TPA_START_CMP_FLAGS2_CSUM_CMPL		(0xffff << 16)
360 	 #define RX_TPA_START_CMP_FLAGS2_CSUM_CMPL_SHIFT	 16
361 
362 	__le32 rx_tpa_start_cmp_metadata;
363 	__le32 rx_tpa_start_cmp_cfa_code_v2;
364 	#define RX_TPA_START_CMP_V2				(0x1 << 0)
365 	#define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_MASK	(0x7 << 1)
366 	 #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_SHIFT	 1
367 	 #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_NO_BUFFER	 (0x0 << 1)
368 	 #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3 << 1)
369 	 #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_FLUSH	 (0x5 << 1)
370 	#define RX_TPA_START_CMP_CFA_CODE			(0xffff << 16)
371 	 #define RX_TPA_START_CMPL_CFA_CODE_SHIFT		 16
372 	__le32 rx_tpa_start_cmp_hdr_info;
373 };
374 
375 #define TPA_START_CFA_CODE(rx_tpa_start)				\
376 	((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_cfa_code_v2) &	\
377 	 RX_TPA_START_CMP_CFA_CODE) >> RX_TPA_START_CMPL_CFA_CODE_SHIFT)
378 
379 #define TPA_START_IS_IPV6(rx_tpa_start)				\
380 	(!!((rx_tpa_start)->rx_tpa_start_cmp_flags2 &		\
381 	    cpu_to_le32(RX_TPA_START_CMP_FLAGS2_IP_TYPE)))
382 
383 #define TPA_START_ERROR_CODE(rx_tpa_start)				\
384 	((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_cfa_code_v2) &	\
385 	  RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_MASK) >>			\
386 	 RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_SHIFT)
387 
388 struct rx_tpa_end_cmp {
389 	__le32 rx_tpa_end_cmp_len_flags_type;
390 	#define RX_TPA_END_CMP_TYPE				(0x3f << 0)
391 	#define RX_TPA_END_CMP_FLAGS				(0x3ff << 6)
392 	 #define RX_TPA_END_CMP_FLAGS_SHIFT			 6
393 	#define RX_TPA_END_CMP_FLAGS_PLACEMENT			(0x7 << 7)
394 	 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_SHIFT		 7
395 	 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_JUMBO		 (0x1 << 7)
396 	 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_HDS		 (0x2 << 7)
397 	 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_JUMBO	 (0x5 << 7)
398 	 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_HDS		 (0x6 << 7)
399 	#define RX_TPA_END_CMP_FLAGS_RSS_VALID			(0x1 << 10)
400 	#define RX_TPA_END_CMP_FLAGS_ITYPES			(0xf << 12)
401 	 #define RX_TPA_END_CMP_FLAGS_ITYPES_SHIFT		 12
402 	 #define RX_TPA_END_CMP_FLAGS_ITYPE_TCP			 (0x2 << 12)
403 	#define RX_TPA_END_CMP_LEN				(0xffff << 16)
404 	 #define RX_TPA_END_CMP_LEN_SHIFT			 16
405 
406 	u32 rx_tpa_end_cmp_opaque;
407 	__le32 rx_tpa_end_cmp_misc_v1;
408 	#define RX_TPA_END_CMP_V1				(0x1 << 0)
409 	#define RX_TPA_END_CMP_AGG_BUFS				(0x3f << 1)
410 	 #define RX_TPA_END_CMP_AGG_BUFS_SHIFT			 1
411 	#define RX_TPA_END_CMP_TPA_SEGS				(0xff << 8)
412 	 #define RX_TPA_END_CMP_TPA_SEGS_SHIFT			 8
413 	#define RX_TPA_END_CMP_PAYLOAD_OFFSET			(0xff << 16)
414 	 #define RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT		 16
415 	#define RX_TPA_END_CMP_AGG_ID				(0x7f << 25)
416 	 #define RX_TPA_END_CMP_AGG_ID_SHIFT			 25
417 	#define RX_TPA_END_CMP_AGG_ID_P5			(0xffff << 16)
418 	 #define RX_TPA_END_CMP_AGG_ID_SHIFT_P5			 16
419 
420 	__le32 rx_tpa_end_cmp_tsdelta;
421 	#define RX_TPA_END_GRO_TS				(0x1 << 31)
422 };
423 
424 #define TPA_END_AGG_ID(rx_tpa_end)					\
425 	((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) &		\
426 	 RX_TPA_END_CMP_AGG_ID) >> RX_TPA_END_CMP_AGG_ID_SHIFT)
427 
428 #define TPA_END_AGG_ID_P5(rx_tpa_end)					\
429 	((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) &		\
430 	 RX_TPA_END_CMP_AGG_ID_P5) >> RX_TPA_END_CMP_AGG_ID_SHIFT_P5)
431 
432 #define TPA_END_PAYLOAD_OFF(rx_tpa_end)					\
433 	((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) &		\
434 	 RX_TPA_END_CMP_PAYLOAD_OFFSET) >> RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT)
435 
436 #define TPA_END_AGG_BUFS(rx_tpa_end)					\
437 	((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) &		\
438 	 RX_TPA_END_CMP_AGG_BUFS) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT)
439 
440 #define TPA_END_TPA_SEGS(rx_tpa_end)					\
441 	((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) &		\
442 	 RX_TPA_END_CMP_TPA_SEGS) >> RX_TPA_END_CMP_TPA_SEGS_SHIFT)
443 
444 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_ANY_GRO				\
445 	cpu_to_le32(RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_JUMBO &		\
446 		    RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_HDS)
447 
448 #define TPA_END_GRO(rx_tpa_end)						\
449 	((rx_tpa_end)->rx_tpa_end_cmp_len_flags_type &			\
450 	 RX_TPA_END_CMP_FLAGS_PLACEMENT_ANY_GRO)
451 
452 #define TPA_END_GRO_TS(rx_tpa_end)					\
453 	(!!((rx_tpa_end)->rx_tpa_end_cmp_tsdelta &			\
454 	    cpu_to_le32(RX_TPA_END_GRO_TS)))
455 
456 struct rx_tpa_end_cmp_ext {
457 	__le32 rx_tpa_end_cmp_dup_acks;
458 	#define RX_TPA_END_CMP_TPA_DUP_ACKS			(0xf << 0)
459 	#define RX_TPA_END_CMP_PAYLOAD_OFFSET_P5		(0xff << 16)
460 	 #define RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT_P5		 16
461 	#define RX_TPA_END_CMP_AGG_BUFS_P5			(0xff << 24)
462 	 #define RX_TPA_END_CMP_AGG_BUFS_SHIFT_P5		 24
463 
464 	__le32 rx_tpa_end_cmp_seg_len;
465 	#define RX_TPA_END_CMP_TPA_SEG_LEN			(0xffff << 0)
466 
467 	__le32 rx_tpa_end_cmp_errors_v2;
468 	#define RX_TPA_END_CMP_V2				(0x1 << 0)
469 	#define RX_TPA_END_CMP_ERRORS				(0x3 << 1)
470 	#define RX_TPA_END_CMP_ERRORS_P5			(0x7 << 1)
471 	#define RX_TPA_END_CMPL_ERRORS_SHIFT			 1
472 	 #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_NO_BUFFER	 (0x0 << 1)
473 	 #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_NOT_ON_CHIP	 (0x2 << 1)
474 	 #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT	 (0x3 << 1)
475 	 #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_RSV_ERROR	 (0x4 << 1)
476 	 #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_FLUSH	 (0x5 << 1)
477 
478 	u32 rx_tpa_end_cmp_start_opaque;
479 };
480 
481 #define TPA_END_ERRORS(rx_tpa_end_ext)					\
482 	((rx_tpa_end_ext)->rx_tpa_end_cmp_errors_v2 &			\
483 	 cpu_to_le32(RX_TPA_END_CMP_ERRORS))
484 
485 #define TPA_END_PAYLOAD_OFF_P5(rx_tpa_end_ext)				\
486 	((le32_to_cpu((rx_tpa_end_ext)->rx_tpa_end_cmp_dup_acks) &	\
487 	 RX_TPA_END_CMP_PAYLOAD_OFFSET_P5) >>				\
488 	RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT_P5)
489 
490 #define TPA_END_AGG_BUFS_P5(rx_tpa_end_ext)				\
491 	((le32_to_cpu((rx_tpa_end_ext)->rx_tpa_end_cmp_dup_acks) &	\
492 	 RX_TPA_END_CMP_AGG_BUFS_P5) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT_P5)
493 
494 #define EVENT_DATA1_RESET_NOTIFY_FATAL(data1)				\
495 	(((data1) &							\
496 	  ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK) ==\
497 	 ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_FATAL)
498 
499 #define EVENT_DATA1_RESET_NOTIFY_FW_ACTIVATION(data1)			\
500 	(((data1) &							\
501 	  ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK) ==\
502 	ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_ACTIVATION)
503 
504 #define EVENT_DATA2_RESET_NOTIFY_FW_STATUS_CODE(data2)			\
505 	((data2) &							\
506 	ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA2_FW_STATUS_CODE_MASK)
507 
508 #define EVENT_DATA1_RECOVERY_MASTER_FUNC(data1)				\
509 	!!((data1) &							\
510 	   ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASTER_FUNC)
511 
512 #define EVENT_DATA1_RECOVERY_ENABLED(data1)				\
513 	!!((data1) &							\
514 	   ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_RECOVERY_ENABLED)
515 
516 #define BNXT_EVENT_ERROR_REPORT_TYPE(data1)				\
517 	(((data1) &							\
518 	  ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_MASK) >>\
519 	 ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_SFT)
520 
521 #define BNXT_EVENT_INVALID_SIGNAL_DATA(data2)				\
522 	(((data2) &							\
523 	  ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA2_PIN_ID_MASK) >>\
524 	 ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA2_PIN_ID_SFT)
525 
526 struct nqe_cn {
527 	__le16	type;
528 	#define NQ_CN_TYPE_MASK           0x3fUL
529 	#define NQ_CN_TYPE_SFT            0
530 	#define NQ_CN_TYPE_CQ_NOTIFICATION  0x30UL
531 	#define NQ_CN_TYPE_LAST            NQ_CN_TYPE_CQ_NOTIFICATION
532 	__le16	reserved16;
533 	__le32	cq_handle_low;
534 	__le32	v;
535 	#define NQ_CN_V     0x1UL
536 	__le32	cq_handle_high;
537 };
538 
539 #define DB_IDX_MASK						0xffffff
540 #define DB_IDX_VALID						(0x1 << 26)
541 #define DB_IRQ_DIS						(0x1 << 27)
542 #define DB_KEY_TX						(0x0 << 28)
543 #define DB_KEY_RX						(0x1 << 28)
544 #define DB_KEY_CP						(0x2 << 28)
545 #define DB_KEY_ST						(0x3 << 28)
546 #define DB_KEY_TX_PUSH						(0x4 << 28)
547 #define DB_LONG_TX_PUSH						(0x2 << 24)
548 
549 #define BNXT_MIN_ROCE_CP_RINGS	2
550 #define BNXT_MIN_ROCE_STAT_CTXS	1
551 
552 /* 64-bit doorbell */
553 #define DBR_INDEX_MASK					0x0000000000ffffffULL
554 #define DBR_XID_MASK					0x000fffff00000000ULL
555 #define DBR_XID_SFT					32
556 #define DBR_PATH_L2					(0x1ULL << 56)
557 #define DBR_TYPE_SQ					(0x0ULL << 60)
558 #define DBR_TYPE_RQ					(0x1ULL << 60)
559 #define DBR_TYPE_SRQ					(0x2ULL << 60)
560 #define DBR_TYPE_SRQ_ARM				(0x3ULL << 60)
561 #define DBR_TYPE_CQ					(0x4ULL << 60)
562 #define DBR_TYPE_CQ_ARMSE				(0x5ULL << 60)
563 #define DBR_TYPE_CQ_ARMALL				(0x6ULL << 60)
564 #define DBR_TYPE_CQ_ARMENA				(0x7ULL << 60)
565 #define DBR_TYPE_SRQ_ARMENA				(0x8ULL << 60)
566 #define DBR_TYPE_CQ_CUTOFF_ACK				(0x9ULL << 60)
567 #define DBR_TYPE_NQ					(0xaULL << 60)
568 #define DBR_TYPE_NQ_ARM					(0xbULL << 60)
569 #define DBR_TYPE_NULL					(0xfULL << 60)
570 
571 #define DB_PF_OFFSET_P5					0x10000
572 #define DB_VF_OFFSET_P5					0x4000
573 
574 #define INVALID_HW_RING_ID	((u16)-1)
575 
576 /* The hardware supports certain page sizes.  Use the supported page sizes
577  * to allocate the rings.
578  */
579 #if (PAGE_SHIFT < 12)
580 #define BNXT_PAGE_SHIFT	12
581 #elif (PAGE_SHIFT <= 13)
582 #define BNXT_PAGE_SHIFT	PAGE_SHIFT
583 #elif (PAGE_SHIFT < 16)
584 #define BNXT_PAGE_SHIFT	13
585 #else
586 #define BNXT_PAGE_SHIFT	16
587 #endif
588 
589 #define BNXT_PAGE_SIZE	(1 << BNXT_PAGE_SHIFT)
590 
591 /* The RXBD length is 16-bit so we can only support page sizes < 64K */
592 #if (PAGE_SHIFT > 15)
593 #define BNXT_RX_PAGE_SHIFT 15
594 #else
595 #define BNXT_RX_PAGE_SHIFT PAGE_SHIFT
596 #endif
597 
598 #define BNXT_RX_PAGE_SIZE (1 << BNXT_RX_PAGE_SHIFT)
599 
600 #define BNXT_MAX_MTU		9500
601 
602 /* First RX buffer page in XDP multi-buf mode
603  *
604  * +-------------------------------------------------------------------------+
605  * | XDP_PACKET_HEADROOM | bp->rx_buf_use_size              | skb_shared_info|
606  * | (bp->rx_dma_offset) |                                  |                |
607  * +-------------------------------------------------------------------------+
608  */
609 #define BNXT_MAX_PAGE_MODE_MTU_SBUF \
610 	((unsigned int)PAGE_SIZE - VLAN_ETH_HLEN - NET_IP_ALIGN -	\
611 	 XDP_PACKET_HEADROOM)
612 #define BNXT_MAX_PAGE_MODE_MTU	\
613 	(BNXT_MAX_PAGE_MODE_MTU_SBUF - \
614 	 SKB_DATA_ALIGN((unsigned int)sizeof(struct skb_shared_info)))
615 
616 #define BNXT_MIN_PKT_SIZE	52
617 
618 #define BNXT_DEFAULT_RX_RING_SIZE	511
619 #define BNXT_DEFAULT_TX_RING_SIZE	511
620 
621 #define MAX_TPA		64
622 #define MAX_TPA_P5	256
623 #define MAX_TPA_P5_MASK	(MAX_TPA_P5 - 1)
624 #define MAX_TPA_SEGS_P5	0x3f
625 
626 #if (BNXT_PAGE_SHIFT == 16)
627 #define MAX_RX_PAGES_AGG_ENA	1
628 #define MAX_RX_PAGES	4
629 #define MAX_RX_AGG_PAGES	4
630 #define MAX_TX_PAGES	1
631 #define MAX_CP_PAGES	16
632 #else
633 #define MAX_RX_PAGES_AGG_ENA	8
634 #define MAX_RX_PAGES	32
635 #define MAX_RX_AGG_PAGES	32
636 #define MAX_TX_PAGES	8
637 #define MAX_CP_PAGES	128
638 #endif
639 
640 #define RX_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct rx_bd))
641 #define TX_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct tx_bd))
642 #define CP_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct tx_cmp))
643 
644 #define SW_RXBD_RING_SIZE (sizeof(struct bnxt_sw_rx_bd) * RX_DESC_CNT)
645 #define HW_RXBD_RING_SIZE (sizeof(struct rx_bd) * RX_DESC_CNT)
646 
647 #define SW_RXBD_AGG_RING_SIZE (sizeof(struct bnxt_sw_rx_agg_bd) * RX_DESC_CNT)
648 
649 #define SW_TXBD_RING_SIZE (sizeof(struct bnxt_sw_tx_bd) * TX_DESC_CNT)
650 #define HW_TXBD_RING_SIZE (sizeof(struct tx_bd) * TX_DESC_CNT)
651 
652 #define HW_CMPD_RING_SIZE (sizeof(struct tx_cmp) * CP_DESC_CNT)
653 
654 #define BNXT_MAX_RX_DESC_CNT		(RX_DESC_CNT * MAX_RX_PAGES - 1)
655 #define BNXT_MAX_RX_DESC_CNT_JUM_ENA	(RX_DESC_CNT * MAX_RX_PAGES_AGG_ENA - 1)
656 #define BNXT_MAX_RX_JUM_DESC_CNT	(RX_DESC_CNT * MAX_RX_AGG_PAGES - 1)
657 #define BNXT_MAX_TX_DESC_CNT		(TX_DESC_CNT * MAX_TX_PAGES - 1)
658 
659 /* Minimum TX BDs for a TX packet with MAX_SKB_FRAGS + 1.  We need one extra
660  * BD because the first TX BD is always a long BD.
661  */
662 #define BNXT_MIN_TX_DESC_CNT		(MAX_SKB_FRAGS + 2)
663 
664 #define RX_RING(x)	(((x) & ~(RX_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4))
665 #define RX_IDX(x)	((x) & (RX_DESC_CNT - 1))
666 
667 #define TX_RING(x)	(((x) & ~(TX_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4))
668 #define TX_IDX(x)	((x) & (TX_DESC_CNT - 1))
669 
670 #define CP_RING(x)	(((x) & ~(CP_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4))
671 #define CP_IDX(x)	((x) & (CP_DESC_CNT - 1))
672 
673 #define TX_CMP_VALID(txcmp, raw_cons)					\
674 	(!!((txcmp)->tx_cmp_errors_v & cpu_to_le32(TX_CMP_V)) ==	\
675 	 !((raw_cons) & bp->cp_bit))
676 
677 #define RX_CMP_VALID(rxcmp1, raw_cons)					\
678 	(!!((rxcmp1)->rx_cmp_cfa_code_errors_v2 & cpu_to_le32(RX_CMP_V)) ==\
679 	 !((raw_cons) & bp->cp_bit))
680 
681 #define RX_AGG_CMP_VALID(agg, raw_cons)				\
682 	(!!((agg)->rx_agg_cmp_v & cpu_to_le32(RX_AGG_CMP_V)) ==	\
683 	 !((raw_cons) & bp->cp_bit))
684 
685 #define NQ_CMP_VALID(nqcmp, raw_cons)				\
686 	(!!((nqcmp)->v & cpu_to_le32(NQ_CN_V)) == !((raw_cons) & bp->cp_bit))
687 
688 #define TX_CMP_TYPE(txcmp)					\
689 	(le32_to_cpu((txcmp)->tx_cmp_flags_type) & CMP_TYPE)
690 
691 #define RX_CMP_TYPE(rxcmp)					\
692 	(le32_to_cpu((rxcmp)->rx_cmp_len_flags_type) & RX_CMP_CMP_TYPE)
693 
694 #define NEXT_RX(idx)		(((idx) + 1) & bp->rx_ring_mask)
695 
696 #define NEXT_RX_AGG(idx)	(((idx) + 1) & bp->rx_agg_ring_mask)
697 
698 #define NEXT_TX(idx)		(((idx) + 1) & bp->tx_ring_mask)
699 
700 #define ADV_RAW_CMP(idx, n)	((idx) + (n))
701 #define NEXT_RAW_CMP(idx)	ADV_RAW_CMP(idx, 1)
702 #define RING_CMP(idx)		((idx) & bp->cp_ring_mask)
703 #define NEXT_CMP(idx)		RING_CMP(ADV_RAW_CMP(idx, 1))
704 
705 #define DFLT_HWRM_CMD_TIMEOUT		500
706 
707 #define BNXT_RX_EVENT		1
708 #define BNXT_AGG_EVENT		2
709 #define BNXT_TX_EVENT		4
710 #define BNXT_REDIRECT_EVENT	8
711 
712 struct bnxt_sw_tx_bd {
713 	union {
714 		struct sk_buff		*skb;
715 		struct xdp_frame	*xdpf;
716 	};
717 	DEFINE_DMA_UNMAP_ADDR(mapping);
718 	DEFINE_DMA_UNMAP_LEN(len);
719 	struct page		*page;
720 	u8			is_gso;
721 	u8			is_push;
722 	u8			action;
723 	unsigned short		nr_frags;
724 	u16			rx_prod;
725 };
726 
727 struct bnxt_sw_rx_bd {
728 	void			*data;
729 	u8			*data_ptr;
730 	dma_addr_t		mapping;
731 };
732 
733 struct bnxt_sw_rx_agg_bd {
734 	struct page		*page;
735 	unsigned int		offset;
736 	dma_addr_t		mapping;
737 };
738 
739 struct bnxt_mem_init {
740 	u8	init_val;
741 	u16	offset;
742 #define	BNXT_MEM_INVALID_OFFSET	0xffff
743 	u16	size;
744 };
745 
746 struct bnxt_ring_mem_info {
747 	int			nr_pages;
748 	int			page_size;
749 	u16			flags;
750 #define BNXT_RMEM_VALID_PTE_FLAG	1
751 #define BNXT_RMEM_RING_PTE_FLAG		2
752 #define BNXT_RMEM_USE_FULL_PAGE_FLAG	4
753 
754 	u16			depth;
755 	struct bnxt_mem_init	*mem_init;
756 
757 	void			**pg_arr;
758 	dma_addr_t		*dma_arr;
759 
760 	__le64			*pg_tbl;
761 	dma_addr_t		pg_tbl_map;
762 
763 	int			vmem_size;
764 	void			**vmem;
765 };
766 
767 struct bnxt_ring_struct {
768 	struct bnxt_ring_mem_info	ring_mem;
769 
770 	u16			fw_ring_id; /* Ring id filled by Chimp FW */
771 	union {
772 		u16		grp_idx;
773 		u16		map_idx; /* Used by cmpl rings */
774 	};
775 	u32			handle;
776 	u8			queue_id;
777 };
778 
779 struct tx_push_bd {
780 	__le32			doorbell;
781 	__le32			tx_bd_len_flags_type;
782 	u32			tx_bd_opaque;
783 	struct tx_bd_ext	txbd2;
784 };
785 
786 struct tx_push_buffer {
787 	struct tx_push_bd	push_bd;
788 	u32			data[25];
789 };
790 
791 struct bnxt_db_info {
792 	void __iomem		*doorbell;
793 	union {
794 		u64		db_key64;
795 		u32		db_key32;
796 	};
797 };
798 
799 struct bnxt_tx_ring_info {
800 	struct bnxt_napi	*bnapi;
801 	u16			tx_prod;
802 	u16			tx_cons;
803 	u16			txq_index;
804 	u8			kick_pending;
805 	struct bnxt_db_info	tx_db;
806 
807 	struct tx_bd		*tx_desc_ring[MAX_TX_PAGES];
808 	struct bnxt_sw_tx_bd	*tx_buf_ring;
809 
810 	dma_addr_t		tx_desc_mapping[MAX_TX_PAGES];
811 
812 	struct tx_push_buffer	*tx_push;
813 	dma_addr_t		tx_push_mapping;
814 	__le64			data_mapping;
815 
816 #define BNXT_DEV_STATE_CLOSING	0x1
817 	u32			dev_state;
818 
819 	struct bnxt_ring_struct	tx_ring_struct;
820 	/* Synchronize simultaneous xdp_xmit on same ring */
821 	spinlock_t		xdp_tx_lock;
822 };
823 
824 #define BNXT_LEGACY_COAL_CMPL_PARAMS					\
825 	(RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN |		\
826 	 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MAX |		\
827 	 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET |		\
828 	 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE |			\
829 	 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR |		\
830 	 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT | \
831 	 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR |		\
832 	 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT | \
833 	 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_AGGR_INT)
834 
835 #define BNXT_COAL_CMPL_ENABLES						\
836 	(RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR | \
837 	 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_CMPL_AGGR_DMA_TMR | \
838 	 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MAX | \
839 	 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_AGGR_INT)
840 
841 #define BNXT_COAL_CMPL_MIN_TMR_ENABLE					\
842 	RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MIN
843 
844 #define BNXT_COAL_CMPL_AGGR_TMR_DURING_INT_ENABLE			\
845 	RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT
846 
847 struct bnxt_coal_cap {
848 	u32			cmpl_params;
849 	u32			nq_params;
850 	u16			num_cmpl_dma_aggr_max;
851 	u16			num_cmpl_dma_aggr_during_int_max;
852 	u16			cmpl_aggr_dma_tmr_max;
853 	u16			cmpl_aggr_dma_tmr_during_int_max;
854 	u16			int_lat_tmr_min_max;
855 	u16			int_lat_tmr_max_max;
856 	u16			num_cmpl_aggr_int_max;
857 	u16			timer_units;
858 };
859 
860 struct bnxt_coal {
861 	u16			coal_ticks;
862 	u16			coal_ticks_irq;
863 	u16			coal_bufs;
864 	u16			coal_bufs_irq;
865 			/* RING_IDLE enabled when coal ticks < idle_thresh  */
866 	u16			idle_thresh;
867 	u8			bufs_per_record;
868 	u8			budget;
869 	u16			flags;
870 };
871 
872 struct bnxt_tpa_info {
873 	void			*data;
874 	u8			*data_ptr;
875 	dma_addr_t		mapping;
876 	u16			len;
877 	unsigned short		gso_type;
878 	u32			flags2;
879 	u32			metadata;
880 	enum pkt_hash_types	hash_type;
881 	u32			rss_hash;
882 	u32			hdr_info;
883 
884 #define BNXT_TPA_L4_SIZE(hdr_info)	\
885 	(((hdr_info) & 0xf8000000) ? ((hdr_info) >> 27) : 32)
886 
887 #define BNXT_TPA_INNER_L3_OFF(hdr_info)	\
888 	(((hdr_info) >> 18) & 0x1ff)
889 
890 #define BNXT_TPA_INNER_L2_OFF(hdr_info)	\
891 	(((hdr_info) >> 9) & 0x1ff)
892 
893 #define BNXT_TPA_OUTER_L3_OFF(hdr_info)	\
894 	((hdr_info) & 0x1ff)
895 
896 	u16			cfa_code; /* cfa_code in TPA start compl */
897 	u8			agg_count;
898 	struct rx_agg_cmp	*agg_arr;
899 };
900 
901 #define BNXT_AGG_IDX_BMAP_SIZE	(MAX_TPA_P5 / BITS_PER_LONG)
902 
903 struct bnxt_tpa_idx_map {
904 	u16		agg_id_tbl[1024];
905 	unsigned long	agg_idx_bmap[BNXT_AGG_IDX_BMAP_SIZE];
906 };
907 
908 struct bnxt_rx_ring_info {
909 	struct bnxt_napi	*bnapi;
910 	u16			rx_prod;
911 	u16			rx_agg_prod;
912 	u16			rx_sw_agg_prod;
913 	u16			rx_next_cons;
914 	struct bnxt_db_info	rx_db;
915 	struct bnxt_db_info	rx_agg_db;
916 
917 	struct bpf_prog		*xdp_prog;
918 
919 	struct rx_bd		*rx_desc_ring[MAX_RX_PAGES];
920 	struct bnxt_sw_rx_bd	*rx_buf_ring;
921 
922 	struct rx_bd		*rx_agg_desc_ring[MAX_RX_AGG_PAGES];
923 	struct bnxt_sw_rx_agg_bd	*rx_agg_ring;
924 
925 	unsigned long		*rx_agg_bmap;
926 	u16			rx_agg_bmap_size;
927 
928 	dma_addr_t		rx_desc_mapping[MAX_RX_PAGES];
929 	dma_addr_t		rx_agg_desc_mapping[MAX_RX_AGG_PAGES];
930 
931 	struct bnxt_tpa_info	*rx_tpa;
932 	struct bnxt_tpa_idx_map *rx_tpa_idx_map;
933 
934 	struct bnxt_ring_struct	rx_ring_struct;
935 	struct bnxt_ring_struct	rx_agg_ring_struct;
936 	struct xdp_rxq_info	xdp_rxq;
937 	struct page_pool	*page_pool;
938 };
939 
940 struct bnxt_rx_sw_stats {
941 	u64			rx_l4_csum_errors;
942 	u64			rx_resets;
943 	u64			rx_buf_errors;
944 	u64			rx_oom_discards;
945 	u64			rx_netpoll_discards;
946 };
947 
948 struct bnxt_tx_sw_stats {
949 	u64			tx_resets;
950 };
951 
952 struct bnxt_cmn_sw_stats {
953 	u64			missed_irqs;
954 };
955 
956 struct bnxt_sw_stats {
957 	struct bnxt_rx_sw_stats rx;
958 	struct bnxt_tx_sw_stats tx;
959 	struct bnxt_cmn_sw_stats cmn;
960 };
961 
962 struct bnxt_total_ring_err_stats {
963 	u64			rx_total_l4_csum_errors;
964 	u64			rx_total_resets;
965 	u64			rx_total_buf_errors;
966 	u64			rx_total_oom_discards;
967 	u64			rx_total_netpoll_discards;
968 	u64			rx_total_ring_discards;
969 	u64			tx_total_resets;
970 	u64			tx_total_ring_discards;
971 	u64			total_missed_irqs;
972 };
973 
974 struct bnxt_stats_mem {
975 	u64		*sw_stats;
976 	u64		*hw_masks;
977 	void		*hw_stats;
978 	dma_addr_t	hw_stats_map;
979 	int		len;
980 };
981 
982 struct bnxt_cp_ring_info {
983 	struct bnxt_napi	*bnapi;
984 	u32			cp_raw_cons;
985 	struct bnxt_db_info	cp_db;
986 
987 	u8			had_work_done:1;
988 	u8			has_more_work:1;
989 
990 	u32			last_cp_raw_cons;
991 
992 	struct bnxt_coal	rx_ring_coal;
993 	u64			rx_packets;
994 	u64			rx_bytes;
995 	u64			event_ctr;
996 
997 	struct dim		dim;
998 
999 	union {
1000 		struct tx_cmp	**cp_desc_ring;
1001 		struct nqe_cn	**nq_desc_ring;
1002 	};
1003 
1004 	dma_addr_t		*cp_desc_mapping;
1005 
1006 	struct bnxt_stats_mem	stats;
1007 	u32			hw_stats_ctx_id;
1008 
1009 	struct bnxt_sw_stats	sw_stats;
1010 
1011 	struct bnxt_ring_struct	cp_ring_struct;
1012 
1013 	struct bnxt_cp_ring_info *cp_ring_arr[2];
1014 #define BNXT_RX_HDL	0
1015 #define BNXT_TX_HDL	1
1016 };
1017 
1018 struct bnxt_napi {
1019 	struct napi_struct	napi;
1020 	struct bnxt		*bp;
1021 
1022 	int			index;
1023 	struct bnxt_cp_ring_info	cp_ring;
1024 	struct bnxt_rx_ring_info	*rx_ring;
1025 	struct bnxt_tx_ring_info	*tx_ring;
1026 
1027 	void			(*tx_int)(struct bnxt *, struct bnxt_napi *,
1028 					  int budget);
1029 	int			tx_pkts;
1030 	u8			events;
1031 	u8			tx_fault:1;
1032 
1033 	u32			flags;
1034 #define BNXT_NAPI_FLAG_XDP	0x1
1035 
1036 	bool			in_reset;
1037 };
1038 
1039 struct bnxt_irq {
1040 	irq_handler_t	handler;
1041 	unsigned int	vector;
1042 	u8		requested:1;
1043 	u8		have_cpumask:1;
1044 	char		name[IFNAMSIZ + 2];
1045 	cpumask_var_t	cpu_mask;
1046 };
1047 
1048 #define HWRM_RING_ALLOC_TX	0x1
1049 #define HWRM_RING_ALLOC_RX	0x2
1050 #define HWRM_RING_ALLOC_AGG	0x4
1051 #define HWRM_RING_ALLOC_CMPL	0x8
1052 #define HWRM_RING_ALLOC_NQ	0x10
1053 
1054 #define INVALID_STATS_CTX_ID	-1
1055 
1056 struct bnxt_ring_grp_info {
1057 	u16	fw_stats_ctx;
1058 	u16	fw_grp_id;
1059 	u16	rx_fw_ring_id;
1060 	u16	agg_fw_ring_id;
1061 	u16	cp_fw_ring_id;
1062 };
1063 
1064 struct bnxt_vnic_info {
1065 	u16		fw_vnic_id; /* returned by Chimp during alloc */
1066 #define BNXT_MAX_CTX_PER_VNIC	8
1067 	u16		fw_rss_cos_lb_ctx[BNXT_MAX_CTX_PER_VNIC];
1068 	u16		fw_l2_ctx_id;
1069 #define BNXT_MAX_UC_ADDRS	4
1070 	__le64		fw_l2_filter_id[BNXT_MAX_UC_ADDRS];
1071 				/* index 0 always dev_addr */
1072 	u16		uc_filter_count;
1073 	u8		*uc_list;
1074 
1075 	u16		*fw_grp_ids;
1076 	dma_addr_t	rss_table_dma_addr;
1077 	__le16		*rss_table;
1078 	dma_addr_t	rss_hash_key_dma_addr;
1079 	u64		*rss_hash_key;
1080 	int		rss_table_size;
1081 #define BNXT_RSS_TABLE_ENTRIES_P5	64
1082 #define BNXT_RSS_TABLE_SIZE_P5		(BNXT_RSS_TABLE_ENTRIES_P5 * 4)
1083 #define BNXT_RSS_TABLE_MAX_TBL_P5	8
1084 #define BNXT_MAX_RSS_TABLE_SIZE_P5				\
1085 	(BNXT_RSS_TABLE_SIZE_P5 * BNXT_RSS_TABLE_MAX_TBL_P5)
1086 #define BNXT_MAX_RSS_TABLE_ENTRIES_P5				\
1087 	(BNXT_RSS_TABLE_ENTRIES_P5 * BNXT_RSS_TABLE_MAX_TBL_P5)
1088 
1089 	u32		rx_mask;
1090 
1091 	u8		*mc_list;
1092 	int		mc_list_size;
1093 	int		mc_list_count;
1094 	dma_addr_t	mc_list_mapping;
1095 #define BNXT_MAX_MC_ADDRS	16
1096 
1097 	u32		flags;
1098 #define BNXT_VNIC_RSS_FLAG	1
1099 #define BNXT_VNIC_RFS_FLAG	2
1100 #define BNXT_VNIC_MCAST_FLAG	4
1101 #define BNXT_VNIC_UCAST_FLAG	8
1102 #define BNXT_VNIC_RFS_NEW_RSS_FLAG	0x10
1103 };
1104 
1105 struct bnxt_hw_resc {
1106 	u16	min_rsscos_ctxs;
1107 	u16	max_rsscos_ctxs;
1108 	u16	min_cp_rings;
1109 	u16	max_cp_rings;
1110 	u16	resv_cp_rings;
1111 	u16	min_tx_rings;
1112 	u16	max_tx_rings;
1113 	u16	resv_tx_rings;
1114 	u16	max_tx_sch_inputs;
1115 	u16	min_rx_rings;
1116 	u16	max_rx_rings;
1117 	u16	resv_rx_rings;
1118 	u16	min_hw_ring_grps;
1119 	u16	max_hw_ring_grps;
1120 	u16	resv_hw_ring_grps;
1121 	u16	min_l2_ctxs;
1122 	u16	max_l2_ctxs;
1123 	u16	min_vnics;
1124 	u16	max_vnics;
1125 	u16	resv_vnics;
1126 	u16	min_stat_ctxs;
1127 	u16	max_stat_ctxs;
1128 	u16	resv_stat_ctxs;
1129 	u16	max_nqs;
1130 	u16	max_irqs;
1131 	u16	resv_irqs;
1132 };
1133 
1134 #if defined(CONFIG_BNXT_SRIOV)
1135 struct bnxt_vf_info {
1136 	u16	fw_fid;
1137 	u8	mac_addr[ETH_ALEN];	/* PF assigned MAC Address */
1138 	u8	vf_mac_addr[ETH_ALEN];	/* VF assigned MAC address, only
1139 					 * stored by PF.
1140 					 */
1141 	u16	vlan;
1142 	u16	func_qcfg_flags;
1143 	u32	flags;
1144 #define BNXT_VF_QOS		0x1
1145 #define BNXT_VF_SPOOFCHK	0x2
1146 #define BNXT_VF_LINK_FORCED	0x4
1147 #define BNXT_VF_LINK_UP		0x8
1148 #define BNXT_VF_TRUST		0x10
1149 	u32	min_tx_rate;
1150 	u32	max_tx_rate;
1151 	void	*hwrm_cmd_req_addr;
1152 	dma_addr_t	hwrm_cmd_req_dma_addr;
1153 };
1154 #endif
1155 
1156 struct bnxt_pf_info {
1157 #define BNXT_FIRST_PF_FID	1
1158 #define BNXT_FIRST_VF_FID	128
1159 	u16	fw_fid;
1160 	u16	port_id;
1161 	u8	mac_addr[ETH_ALEN];
1162 	u32	first_vf_id;
1163 	u16	active_vfs;
1164 	u16	registered_vfs;
1165 	u16	max_vfs;
1166 	u32	max_encap_records;
1167 	u32	max_decap_records;
1168 	u32	max_tx_em_flows;
1169 	u32	max_tx_wm_flows;
1170 	u32	max_rx_em_flows;
1171 	u32	max_rx_wm_flows;
1172 	unsigned long	*vf_event_bmap;
1173 	u16	hwrm_cmd_req_pages;
1174 	u8	vf_resv_strategy;
1175 #define BNXT_VF_RESV_STRATEGY_MAXIMAL	0
1176 #define BNXT_VF_RESV_STRATEGY_MINIMAL	1
1177 #define BNXT_VF_RESV_STRATEGY_MINIMAL_STATIC	2
1178 	void			*hwrm_cmd_req_addr[4];
1179 	dma_addr_t		hwrm_cmd_req_dma_addr[4];
1180 	struct bnxt_vf_info	*vf;
1181 };
1182 
1183 struct bnxt_ntuple_filter {
1184 	struct hlist_node	hash;
1185 	u8			dst_mac_addr[ETH_ALEN];
1186 	u8			src_mac_addr[ETH_ALEN];
1187 	struct flow_keys	fkeys;
1188 	__le64			filter_id;
1189 	u16			sw_id;
1190 	u8			l2_fltr_idx;
1191 	u16			rxq;
1192 	u32			flow_id;
1193 	unsigned long		state;
1194 #define BNXT_FLTR_VALID		0
1195 #define BNXT_FLTR_UPDATE	1
1196 };
1197 
1198 struct bnxt_link_info {
1199 	u8			phy_type;
1200 	u8			media_type;
1201 	u8			transceiver;
1202 	u8			phy_addr;
1203 	u8			phy_link_status;
1204 #define BNXT_LINK_NO_LINK	PORT_PHY_QCFG_RESP_LINK_NO_LINK
1205 #define BNXT_LINK_SIGNAL	PORT_PHY_QCFG_RESP_LINK_SIGNAL
1206 #define BNXT_LINK_LINK		PORT_PHY_QCFG_RESP_LINK_LINK
1207 	u8			wire_speed;
1208 	u8			phy_state;
1209 #define BNXT_PHY_STATE_ENABLED		0
1210 #define BNXT_PHY_STATE_DISABLED		1
1211 
1212 	u8			link_state;
1213 #define BNXT_LINK_STATE_UNKNOWN	0
1214 #define BNXT_LINK_STATE_DOWN	1
1215 #define BNXT_LINK_STATE_UP	2
1216 #define BNXT_LINK_IS_UP(bp)	((bp)->link_info.link_state == BNXT_LINK_STATE_UP)
1217 	u8			duplex;
1218 #define BNXT_LINK_DUPLEX_HALF	PORT_PHY_QCFG_RESP_DUPLEX_STATE_HALF
1219 #define BNXT_LINK_DUPLEX_FULL	PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL
1220 	u8			pause;
1221 #define BNXT_LINK_PAUSE_TX	PORT_PHY_QCFG_RESP_PAUSE_TX
1222 #define BNXT_LINK_PAUSE_RX	PORT_PHY_QCFG_RESP_PAUSE_RX
1223 #define BNXT_LINK_PAUSE_BOTH	(PORT_PHY_QCFG_RESP_PAUSE_RX | \
1224 				 PORT_PHY_QCFG_RESP_PAUSE_TX)
1225 	u8			lp_pause;
1226 	u8			auto_pause_setting;
1227 	u8			force_pause_setting;
1228 	u8			duplex_setting;
1229 	u8			auto_mode;
1230 #define BNXT_AUTO_MODE(mode)	((mode) > BNXT_LINK_AUTO_NONE && \
1231 				 (mode) <= BNXT_LINK_AUTO_MSK)
1232 #define BNXT_LINK_AUTO_NONE     PORT_PHY_QCFG_RESP_AUTO_MODE_NONE
1233 #define BNXT_LINK_AUTO_ALLSPDS	PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS
1234 #define BNXT_LINK_AUTO_ONESPD	PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED
1235 #define BNXT_LINK_AUTO_ONEORBELOW PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW
1236 #define BNXT_LINK_AUTO_MSK	PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK
1237 #define PHY_VER_LEN		3
1238 	u8			phy_ver[PHY_VER_LEN];
1239 	u16			link_speed;
1240 #define BNXT_LINK_SPEED_100MB	PORT_PHY_QCFG_RESP_LINK_SPEED_100MB
1241 #define BNXT_LINK_SPEED_1GB	PORT_PHY_QCFG_RESP_LINK_SPEED_1GB
1242 #define BNXT_LINK_SPEED_2GB	PORT_PHY_QCFG_RESP_LINK_SPEED_2GB
1243 #define BNXT_LINK_SPEED_2_5GB	PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB
1244 #define BNXT_LINK_SPEED_10GB	PORT_PHY_QCFG_RESP_LINK_SPEED_10GB
1245 #define BNXT_LINK_SPEED_20GB	PORT_PHY_QCFG_RESP_LINK_SPEED_20GB
1246 #define BNXT_LINK_SPEED_25GB	PORT_PHY_QCFG_RESP_LINK_SPEED_25GB
1247 #define BNXT_LINK_SPEED_40GB	PORT_PHY_QCFG_RESP_LINK_SPEED_40GB
1248 #define BNXT_LINK_SPEED_50GB	PORT_PHY_QCFG_RESP_LINK_SPEED_50GB
1249 #define BNXT_LINK_SPEED_100GB	PORT_PHY_QCFG_RESP_LINK_SPEED_100GB
1250 #define BNXT_LINK_SPEED_200GB	PORT_PHY_QCFG_RESP_LINK_SPEED_200GB
1251 	u16			support_speeds;
1252 	u16			support_pam4_speeds;
1253 	u16			auto_link_speeds;	/* fw adv setting */
1254 #define BNXT_LINK_SPEED_MSK_100MB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB
1255 #define BNXT_LINK_SPEED_MSK_1GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB
1256 #define BNXT_LINK_SPEED_MSK_2GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB
1257 #define BNXT_LINK_SPEED_MSK_10GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB
1258 #define BNXT_LINK_SPEED_MSK_2_5GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB
1259 #define BNXT_LINK_SPEED_MSK_20GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB
1260 #define BNXT_LINK_SPEED_MSK_25GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB
1261 #define BNXT_LINK_SPEED_MSK_40GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB
1262 #define BNXT_LINK_SPEED_MSK_50GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB
1263 #define BNXT_LINK_SPEED_MSK_100GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100GB
1264 	u16			auto_pam4_link_speeds;
1265 #define BNXT_LINK_PAM4_SPEED_MSK_50GB PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_50G
1266 #define BNXT_LINK_PAM4_SPEED_MSK_100GB PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_100G
1267 #define BNXT_LINK_PAM4_SPEED_MSK_200GB PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_200G
1268 	u16			support_auto_speeds;
1269 	u16			support_pam4_auto_speeds;
1270 	u16			lp_auto_link_speeds;
1271 	u16			lp_auto_pam4_link_speeds;
1272 	u16			force_link_speed;
1273 	u16			force_pam4_link_speed;
1274 	u32			preemphasis;
1275 	u8			module_status;
1276 	u8			active_fec_sig_mode;
1277 	u16			fec_cfg;
1278 #define BNXT_FEC_NONE		PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED
1279 #define BNXT_FEC_AUTONEG_CAP	PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_SUPPORTED
1280 #define BNXT_FEC_AUTONEG	PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_ENABLED
1281 #define BNXT_FEC_ENC_BASE_R_CAP	\
1282 	PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_SUPPORTED
1283 #define BNXT_FEC_ENC_BASE_R	PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_ENABLED
1284 #define BNXT_FEC_ENC_RS_CAP	\
1285 	PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_SUPPORTED
1286 #define BNXT_FEC_ENC_LLRS_CAP	\
1287 	(PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_SUPPORTED |	\
1288 	 PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_SUPPORTED)
1289 #define BNXT_FEC_ENC_RS		\
1290 	(PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED |	\
1291 	 PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_1XN_ENABLED |	\
1292 	 PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_IEEE_ENABLED)
1293 #define BNXT_FEC_ENC_LLRS	\
1294 	(PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_ENABLED |	\
1295 	 PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_ENABLED)
1296 
1297 	/* copy of requested setting from ethtool cmd */
1298 	u8			autoneg;
1299 #define BNXT_AUTONEG_SPEED		1
1300 #define BNXT_AUTONEG_FLOW_CTRL		2
1301 	u8			req_signal_mode;
1302 #define BNXT_SIG_MODE_NRZ	PORT_PHY_QCFG_RESP_SIGNAL_MODE_NRZ
1303 #define BNXT_SIG_MODE_PAM4	PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4
1304 	u8			req_duplex;
1305 	u8			req_flow_ctrl;
1306 	u16			req_link_speed;
1307 	u16			advertising;	/* user adv setting */
1308 	u16			advertising_pam4;
1309 	bool			force_link_chng;
1310 
1311 	bool			phy_retry;
1312 	unsigned long		phy_retry_expires;
1313 
1314 	/* a copy of phy_qcfg output used to report link
1315 	 * info to VF
1316 	 */
1317 	struct hwrm_port_phy_qcfg_output phy_qcfg_resp;
1318 };
1319 
1320 #define BNXT_FEC_RS544_ON					\
1321 	 (PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_ENABLE |		\
1322 	  PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_ENABLE)
1323 
1324 #define BNXT_FEC_RS544_OFF					\
1325 	 (PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_DISABLE |	\
1326 	  PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_DISABLE)
1327 
1328 #define BNXT_FEC_RS272_ON					\
1329 	 (PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_ENABLE |		\
1330 	  PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_ENABLE)
1331 
1332 #define BNXT_FEC_RS272_OFF					\
1333 	 (PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_DISABLE |	\
1334 	  PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_DISABLE)
1335 
1336 #define BNXT_PAM4_SUPPORTED(link_info)				\
1337 	((link_info)->support_pam4_speeds)
1338 
1339 #define BNXT_FEC_RS_ON(link_info)				\
1340 	(PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE |		\
1341 	 PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE |		\
1342 	 (BNXT_PAM4_SUPPORTED(link_info) ?			\
1343 	  (BNXT_FEC_RS544_ON | BNXT_FEC_RS272_OFF) : 0))
1344 
1345 #define BNXT_FEC_LLRS_ON					\
1346 	(PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE |		\
1347 	 PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE |		\
1348 	 BNXT_FEC_RS272_ON | BNXT_FEC_RS544_OFF)
1349 
1350 #define BNXT_FEC_RS_OFF(link_info)				\
1351 	(PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_DISABLE |		\
1352 	 (BNXT_PAM4_SUPPORTED(link_info) ?			\
1353 	  (BNXT_FEC_RS544_OFF | BNXT_FEC_RS272_OFF) : 0))
1354 
1355 #define BNXT_FEC_BASE_R_ON(link_info)				\
1356 	(PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_ENABLE |		\
1357 	 BNXT_FEC_RS_OFF(link_info))
1358 
1359 #define BNXT_FEC_ALL_OFF(link_info)				\
1360 	(PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE |		\
1361 	 BNXT_FEC_RS_OFF(link_info))
1362 
1363 #define BNXT_MAX_QUEUE	8
1364 
1365 struct bnxt_queue_info {
1366 	u8	queue_id;
1367 	u8	queue_profile;
1368 };
1369 
1370 #define BNXT_MAX_LED			4
1371 
1372 struct bnxt_led_info {
1373 	u8	led_id;
1374 	u8	led_type;
1375 	u8	led_group_id;
1376 	u8	unused;
1377 	__le16	led_state_caps;
1378 #define BNXT_LED_ALT_BLINK_CAP(x)	((x) &	\
1379 	cpu_to_le16(PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED))
1380 
1381 	__le16	led_color_caps;
1382 };
1383 
1384 #define BNXT_MAX_TEST	8
1385 
1386 struct bnxt_test_info {
1387 	u8 offline_mask;
1388 	u16 timeout;
1389 	char string[BNXT_MAX_TEST][ETH_GSTRING_LEN];
1390 };
1391 
1392 #define CHIMP_REG_VIEW_ADDR				\
1393 	((bp->flags & BNXT_FLAG_CHIP_P5) ? 0x80000000 : 0xb1000000)
1394 
1395 #define BNXT_GRCPF_REG_CHIMP_COMM		0x0
1396 #define BNXT_GRCPF_REG_CHIMP_COMM_TRIGGER	0x100
1397 #define BNXT_GRCPF_REG_WINDOW_BASE_OUT		0x400
1398 #define BNXT_CAG_REG_LEGACY_INT_STATUS		0x4014
1399 #define BNXT_CAG_REG_BASE			0x300000
1400 
1401 #define BNXT_GRC_REG_STATUS_P5			0x520
1402 
1403 #define BNXT_GRCPF_REG_KONG_COMM		0xA00
1404 #define BNXT_GRCPF_REG_KONG_COMM_TRIGGER	0xB00
1405 
1406 #define BNXT_GRC_REG_CHIP_NUM			0x48
1407 #define BNXT_GRC_REG_BASE			0x260000
1408 
1409 #define BNXT_TS_REG_TIMESYNC_TS0_LOWER		0x640180c
1410 #define BNXT_TS_REG_TIMESYNC_TS0_UPPER		0x6401810
1411 
1412 #define BNXT_GRC_BASE_MASK			0xfffff000
1413 #define BNXT_GRC_OFFSET_MASK			0x00000ffc
1414 
1415 struct bnxt_tc_flow_stats {
1416 	u64		packets;
1417 	u64		bytes;
1418 };
1419 
1420 #ifdef CONFIG_BNXT_FLOWER_OFFLOAD
1421 struct bnxt_flower_indr_block_cb_priv {
1422 	struct net_device *tunnel_netdev;
1423 	struct bnxt *bp;
1424 	struct list_head list;
1425 };
1426 #endif
1427 
1428 struct bnxt_tc_info {
1429 	bool				enabled;
1430 
1431 	/* hash table to store TC offloaded flows */
1432 	struct rhashtable		flow_table;
1433 	struct rhashtable_params	flow_ht_params;
1434 
1435 	/* hash table to store L2 keys of TC flows */
1436 	struct rhashtable		l2_table;
1437 	struct rhashtable_params	l2_ht_params;
1438 	/* hash table to store L2 keys for TC tunnel decap */
1439 	struct rhashtable		decap_l2_table;
1440 	struct rhashtable_params	decap_l2_ht_params;
1441 	/* hash table to store tunnel decap entries */
1442 	struct rhashtable		decap_table;
1443 	struct rhashtable_params	decap_ht_params;
1444 	/* hash table to store tunnel encap entries */
1445 	struct rhashtable		encap_table;
1446 	struct rhashtable_params	encap_ht_params;
1447 
1448 	/* lock to atomically add/del an l2 node when a flow is
1449 	 * added or deleted.
1450 	 */
1451 	struct mutex			lock;
1452 
1453 	/* Fields used for batching stats query */
1454 	struct rhashtable_iter		iter;
1455 #define BNXT_FLOW_STATS_BATCH_MAX	10
1456 	struct bnxt_tc_stats_batch {
1457 		void			  *flow_node;
1458 		struct bnxt_tc_flow_stats hw_stats;
1459 	} stats_batch[BNXT_FLOW_STATS_BATCH_MAX];
1460 
1461 	/* Stat counter mask (width) */
1462 	u64				bytes_mask;
1463 	u64				packets_mask;
1464 };
1465 
1466 struct bnxt_vf_rep_stats {
1467 	u64			packets;
1468 	u64			bytes;
1469 	u64			dropped;
1470 };
1471 
1472 struct bnxt_vf_rep {
1473 	struct bnxt			*bp;
1474 	struct net_device		*dev;
1475 	struct metadata_dst		*dst;
1476 	u16				vf_idx;
1477 	u16				tx_cfa_action;
1478 	u16				rx_cfa_code;
1479 
1480 	struct bnxt_vf_rep_stats	rx_stats;
1481 	struct bnxt_vf_rep_stats	tx_stats;
1482 };
1483 
1484 #define PTU_PTE_VALID             0x1UL
1485 #define PTU_PTE_LAST              0x2UL
1486 #define PTU_PTE_NEXT_TO_LAST      0x4UL
1487 
1488 #define MAX_CTX_PAGES	(BNXT_PAGE_SIZE / 8)
1489 #define MAX_CTX_TOTAL_PAGES	(MAX_CTX_PAGES * MAX_CTX_PAGES)
1490 
1491 struct bnxt_ctx_pg_info {
1492 	u32		entries;
1493 	u32		nr_pages;
1494 	void		*ctx_pg_arr[MAX_CTX_PAGES];
1495 	dma_addr_t	ctx_dma_arr[MAX_CTX_PAGES];
1496 	struct bnxt_ring_mem_info ring_mem;
1497 	struct bnxt_ctx_pg_info **ctx_pg_tbl;
1498 };
1499 
1500 #define BNXT_MAX_TQM_SP_RINGS		1
1501 #define BNXT_MAX_TQM_FP_RINGS		8
1502 #define BNXT_MAX_TQM_RINGS		\
1503 	(BNXT_MAX_TQM_SP_RINGS + BNXT_MAX_TQM_FP_RINGS)
1504 
1505 #define BNXT_BACKING_STORE_CFG_LEGACY_LEN	256
1506 
1507 #define BNXT_SET_CTX_PAGE_ATTR(attr)					\
1508 do {									\
1509 	if (BNXT_PAGE_SIZE == 0x2000)					\
1510 		attr = FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8K;	\
1511 	else if (BNXT_PAGE_SIZE == 0x10000)				\
1512 		attr = FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_64K;	\
1513 	else								\
1514 		attr = FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_4K;	\
1515 } while (0)
1516 
1517 struct bnxt_ctx_mem_info {
1518 	u32	qp_max_entries;
1519 	u16	qp_min_qp1_entries;
1520 	u16	qp_max_l2_entries;
1521 	u16	qp_entry_size;
1522 	u16	srq_max_l2_entries;
1523 	u32	srq_max_entries;
1524 	u16	srq_entry_size;
1525 	u16	cq_max_l2_entries;
1526 	u32	cq_max_entries;
1527 	u16	cq_entry_size;
1528 	u16	vnic_max_vnic_entries;
1529 	u16	vnic_max_ring_table_entries;
1530 	u16	vnic_entry_size;
1531 	u32	stat_max_entries;
1532 	u16	stat_entry_size;
1533 	u16	tqm_entry_size;
1534 	u32	tqm_min_entries_per_ring;
1535 	u32	tqm_max_entries_per_ring;
1536 	u32	mrav_max_entries;
1537 	u16	mrav_entry_size;
1538 	u16	tim_entry_size;
1539 	u32	tim_max_entries;
1540 	u16	mrav_num_entries_units;
1541 	u8	tqm_entries_multiple;
1542 	u8	tqm_fp_rings_count;
1543 
1544 	u32	flags;
1545 	#define BNXT_CTX_FLAG_INITED	0x01
1546 
1547 	struct bnxt_ctx_pg_info qp_mem;
1548 	struct bnxt_ctx_pg_info srq_mem;
1549 	struct bnxt_ctx_pg_info cq_mem;
1550 	struct bnxt_ctx_pg_info vnic_mem;
1551 	struct bnxt_ctx_pg_info stat_mem;
1552 	struct bnxt_ctx_pg_info mrav_mem;
1553 	struct bnxt_ctx_pg_info tim_mem;
1554 	struct bnxt_ctx_pg_info *tqm_mem[BNXT_MAX_TQM_RINGS];
1555 
1556 #define BNXT_CTX_MEM_INIT_QP	0
1557 #define BNXT_CTX_MEM_INIT_SRQ	1
1558 #define BNXT_CTX_MEM_INIT_CQ	2
1559 #define BNXT_CTX_MEM_INIT_VNIC	3
1560 #define BNXT_CTX_MEM_INIT_STAT	4
1561 #define BNXT_CTX_MEM_INIT_MRAV	5
1562 #define BNXT_CTX_MEM_INIT_MAX	6
1563 	struct bnxt_mem_init	mem_init[BNXT_CTX_MEM_INIT_MAX];
1564 };
1565 
1566 enum bnxt_health_severity {
1567 	SEVERITY_NORMAL = 0,
1568 	SEVERITY_WARNING,
1569 	SEVERITY_RECOVERABLE,
1570 	SEVERITY_FATAL,
1571 };
1572 
1573 enum bnxt_health_remedy {
1574 	REMEDY_DEVLINK_RECOVER,
1575 	REMEDY_POWER_CYCLE_DEVICE,
1576 	REMEDY_POWER_CYCLE_HOST,
1577 	REMEDY_FW_UPDATE,
1578 	REMEDY_HW_REPLACE,
1579 };
1580 
1581 struct bnxt_fw_health {
1582 	u32 flags;
1583 	u32 polling_dsecs;
1584 	u32 master_func_wait_dsecs;
1585 	u32 normal_func_wait_dsecs;
1586 	u32 post_reset_wait_dsecs;
1587 	u32 post_reset_max_wait_dsecs;
1588 	u32 regs[4];
1589 	u32 mapped_regs[4];
1590 #define BNXT_FW_HEALTH_REG		0
1591 #define BNXT_FW_HEARTBEAT_REG		1
1592 #define BNXT_FW_RESET_CNT_REG		2
1593 #define BNXT_FW_RESET_INPROG_REG	3
1594 	u32 fw_reset_inprog_reg_mask;
1595 	u32 last_fw_heartbeat;
1596 	u32 last_fw_reset_cnt;
1597 	u8 enabled:1;
1598 	u8 primary:1;
1599 	u8 status_reliable:1;
1600 	u8 resets_reliable:1;
1601 	u8 tmr_multiplier;
1602 	u8 tmr_counter;
1603 	u8 fw_reset_seq_cnt;
1604 	u32 fw_reset_seq_regs[16];
1605 	u32 fw_reset_seq_vals[16];
1606 	u32 fw_reset_seq_delay_msec[16];
1607 	u32 echo_req_data1;
1608 	u32 echo_req_data2;
1609 	struct devlink_health_reporter	*fw_reporter;
1610 	/* Protects severity and remedy */
1611 	struct mutex lock;
1612 	enum bnxt_health_severity severity;
1613 	enum bnxt_health_remedy remedy;
1614 	u32 arrests;
1615 	u32 discoveries;
1616 	u32 survivals;
1617 	u32 fatalities;
1618 	u32 diagnoses;
1619 };
1620 
1621 #define BNXT_FW_HEALTH_REG_TYPE_MASK	3
1622 #define BNXT_FW_HEALTH_REG_TYPE_CFG	0
1623 #define BNXT_FW_HEALTH_REG_TYPE_GRC	1
1624 #define BNXT_FW_HEALTH_REG_TYPE_BAR0	2
1625 #define BNXT_FW_HEALTH_REG_TYPE_BAR1	3
1626 
1627 #define BNXT_FW_HEALTH_REG_TYPE(reg)	((reg) & BNXT_FW_HEALTH_REG_TYPE_MASK)
1628 #define BNXT_FW_HEALTH_REG_OFF(reg)	((reg) & ~BNXT_FW_HEALTH_REG_TYPE_MASK)
1629 
1630 #define BNXT_FW_HEALTH_WIN_BASE		0x3000
1631 #define BNXT_FW_HEALTH_WIN_MAP_OFF	8
1632 
1633 #define BNXT_FW_HEALTH_WIN_OFF(reg)	(BNXT_FW_HEALTH_WIN_BASE +	\
1634 					 ((reg) & BNXT_GRC_OFFSET_MASK))
1635 
1636 #define BNXT_FW_STATUS_HEALTH_MSK	0xffff
1637 #define BNXT_FW_STATUS_HEALTHY		0x8000
1638 #define BNXT_FW_STATUS_SHUTDOWN		0x100000
1639 #define BNXT_FW_STATUS_RECOVERING	0x400000
1640 
1641 #define BNXT_FW_IS_HEALTHY(sts)		(((sts) & BNXT_FW_STATUS_HEALTH_MSK) ==\
1642 					 BNXT_FW_STATUS_HEALTHY)
1643 
1644 #define BNXT_FW_IS_BOOTING(sts)		(((sts) & BNXT_FW_STATUS_HEALTH_MSK) < \
1645 					 BNXT_FW_STATUS_HEALTHY)
1646 
1647 #define BNXT_FW_IS_ERR(sts)		(((sts) & BNXT_FW_STATUS_HEALTH_MSK) > \
1648 					 BNXT_FW_STATUS_HEALTHY)
1649 
1650 #define BNXT_FW_IS_RECOVERING(sts)	(BNXT_FW_IS_ERR(sts) &&		       \
1651 					 ((sts) & BNXT_FW_STATUS_RECOVERING))
1652 
1653 #define BNXT_FW_RETRY			5
1654 #define BNXT_FW_IF_RETRY		10
1655 #define BNXT_FW_SLOT_RESET_RETRY	4
1656 
1657 struct bnxt_aux_priv {
1658 	struct auxiliary_device aux_dev;
1659 	struct bnxt_en_dev *edev;
1660 	int id;
1661 };
1662 
1663 enum board_idx {
1664 	BCM57301,
1665 	BCM57302,
1666 	BCM57304,
1667 	BCM57417_NPAR,
1668 	BCM58700,
1669 	BCM57311,
1670 	BCM57312,
1671 	BCM57402,
1672 	BCM57404,
1673 	BCM57406,
1674 	BCM57402_NPAR,
1675 	BCM57407,
1676 	BCM57412,
1677 	BCM57414,
1678 	BCM57416,
1679 	BCM57417,
1680 	BCM57412_NPAR,
1681 	BCM57314,
1682 	BCM57417_SFP,
1683 	BCM57416_SFP,
1684 	BCM57404_NPAR,
1685 	BCM57406_NPAR,
1686 	BCM57407_SFP,
1687 	BCM57407_NPAR,
1688 	BCM57414_NPAR,
1689 	BCM57416_NPAR,
1690 	BCM57452,
1691 	BCM57454,
1692 	BCM5745x_NPAR,
1693 	BCM57508,
1694 	BCM57504,
1695 	BCM57502,
1696 	BCM57508_NPAR,
1697 	BCM57504_NPAR,
1698 	BCM57502_NPAR,
1699 	BCM58802,
1700 	BCM58804,
1701 	BCM58808,
1702 	NETXTREME_E_VF,
1703 	NETXTREME_C_VF,
1704 	NETXTREME_S_VF,
1705 	NETXTREME_C_VF_HV,
1706 	NETXTREME_E_VF_HV,
1707 	NETXTREME_E_P5_VF,
1708 	NETXTREME_E_P5_VF_HV,
1709 };
1710 
1711 struct bnxt {
1712 	void __iomem		*bar0;
1713 	void __iomem		*bar1;
1714 	void __iomem		*bar2;
1715 
1716 	u32			reg_base;
1717 	u16			chip_num;
1718 #define CHIP_NUM_57301		0x16c8
1719 #define CHIP_NUM_57302		0x16c9
1720 #define CHIP_NUM_57304		0x16ca
1721 #define CHIP_NUM_58700		0x16cd
1722 #define CHIP_NUM_57402		0x16d0
1723 #define CHIP_NUM_57404		0x16d1
1724 #define CHIP_NUM_57406		0x16d2
1725 #define CHIP_NUM_57407		0x16d5
1726 
1727 #define CHIP_NUM_57311		0x16ce
1728 #define CHIP_NUM_57312		0x16cf
1729 #define CHIP_NUM_57314		0x16df
1730 #define CHIP_NUM_57317		0x16e0
1731 #define CHIP_NUM_57412		0x16d6
1732 #define CHIP_NUM_57414		0x16d7
1733 #define CHIP_NUM_57416		0x16d8
1734 #define CHIP_NUM_57417		0x16d9
1735 #define CHIP_NUM_57412L		0x16da
1736 #define CHIP_NUM_57414L		0x16db
1737 
1738 #define CHIP_NUM_5745X		0xd730
1739 #define CHIP_NUM_57452		0xc452
1740 #define CHIP_NUM_57454		0xc454
1741 
1742 #define CHIP_NUM_57508		0x1750
1743 #define CHIP_NUM_57504		0x1751
1744 #define CHIP_NUM_57502		0x1752
1745 
1746 #define CHIP_NUM_58802		0xd802
1747 #define CHIP_NUM_58804		0xd804
1748 #define CHIP_NUM_58808		0xd808
1749 
1750 	u8			chip_rev;
1751 
1752 #define CHIP_NUM_58818		0xd818
1753 
1754 #define BNXT_CHIP_NUM_5730X(chip_num)		\
1755 	((chip_num) >= CHIP_NUM_57301 &&	\
1756 	 (chip_num) <= CHIP_NUM_57304)
1757 
1758 #define BNXT_CHIP_NUM_5740X(chip_num)		\
1759 	(((chip_num) >= CHIP_NUM_57402 &&	\
1760 	  (chip_num) <= CHIP_NUM_57406) ||	\
1761 	 (chip_num) == CHIP_NUM_57407)
1762 
1763 #define BNXT_CHIP_NUM_5731X(chip_num)		\
1764 	((chip_num) == CHIP_NUM_57311 ||	\
1765 	 (chip_num) == CHIP_NUM_57312 ||	\
1766 	 (chip_num) == CHIP_NUM_57314 ||	\
1767 	 (chip_num) == CHIP_NUM_57317)
1768 
1769 #define BNXT_CHIP_NUM_5741X(chip_num)		\
1770 	((chip_num) >= CHIP_NUM_57412 &&	\
1771 	 (chip_num) <= CHIP_NUM_57414L)
1772 
1773 #define BNXT_CHIP_NUM_58700(chip_num)		\
1774 	 ((chip_num) == CHIP_NUM_58700)
1775 
1776 #define BNXT_CHIP_NUM_5745X(chip_num)		\
1777 	((chip_num) == CHIP_NUM_5745X ||	\
1778 	 (chip_num) == CHIP_NUM_57452 ||	\
1779 	 (chip_num) == CHIP_NUM_57454)
1780 
1781 
1782 #define BNXT_CHIP_NUM_57X0X(chip_num)		\
1783 	(BNXT_CHIP_NUM_5730X(chip_num) || BNXT_CHIP_NUM_5740X(chip_num))
1784 
1785 #define BNXT_CHIP_NUM_57X1X(chip_num)		\
1786 	(BNXT_CHIP_NUM_5731X(chip_num) || BNXT_CHIP_NUM_5741X(chip_num))
1787 
1788 #define BNXT_CHIP_NUM_588XX(chip_num)		\
1789 	((chip_num) == CHIP_NUM_58802 ||	\
1790 	 (chip_num) == CHIP_NUM_58804 ||        \
1791 	 (chip_num) == CHIP_NUM_58808)
1792 
1793 #define BNXT_VPD_FLD_LEN	32
1794 	char			board_partno[BNXT_VPD_FLD_LEN];
1795 	char			board_serialno[BNXT_VPD_FLD_LEN];
1796 
1797 	struct net_device	*dev;
1798 	struct pci_dev		*pdev;
1799 
1800 	atomic_t		intr_sem;
1801 
1802 	u32			flags;
1803 	#define BNXT_FLAG_CHIP_P5	0x1
1804 	#define BNXT_FLAG_VF		0x2
1805 	#define BNXT_FLAG_LRO		0x4
1806 #ifdef CONFIG_INET
1807 	#define BNXT_FLAG_GRO		0x8
1808 #else
1809 	/* Cannot support hardware GRO if CONFIG_INET is not set */
1810 	#define BNXT_FLAG_GRO		0x0
1811 #endif
1812 	#define BNXT_FLAG_TPA		(BNXT_FLAG_LRO | BNXT_FLAG_GRO)
1813 	#define BNXT_FLAG_JUMBO		0x10
1814 	#define BNXT_FLAG_STRIP_VLAN	0x20
1815 	#define BNXT_FLAG_AGG_RINGS	(BNXT_FLAG_JUMBO | BNXT_FLAG_GRO | \
1816 					 BNXT_FLAG_LRO)
1817 	#define BNXT_FLAG_USING_MSIX	0x40
1818 	#define BNXT_FLAG_MSIX_CAP	0x80
1819 	#define BNXT_FLAG_RFS		0x100
1820 	#define BNXT_FLAG_SHARED_RINGS	0x200
1821 	#define BNXT_FLAG_PORT_STATS	0x400
1822 	#define BNXT_FLAG_UDP_RSS_CAP	0x800
1823 	#define BNXT_FLAG_NEW_RSS_CAP	0x2000
1824 	#define BNXT_FLAG_WOL_CAP	0x4000
1825 	#define BNXT_FLAG_ROCEV1_CAP	0x8000
1826 	#define BNXT_FLAG_ROCEV2_CAP	0x10000
1827 	#define BNXT_FLAG_ROCE_CAP	(BNXT_FLAG_ROCEV1_CAP |	\
1828 					 BNXT_FLAG_ROCEV2_CAP)
1829 	#define BNXT_FLAG_NO_AGG_RINGS	0x20000
1830 	#define BNXT_FLAG_RX_PAGE_MODE	0x40000
1831 	#define BNXT_FLAG_CHIP_SR2	0x80000
1832 	#define BNXT_FLAG_MULTI_HOST	0x100000
1833 	#define BNXT_FLAG_DSN_VALID	0x200000
1834 	#define BNXT_FLAG_DOUBLE_DB	0x400000
1835 	#define BNXT_FLAG_CHIP_NITRO_A0	0x1000000
1836 	#define BNXT_FLAG_DIM		0x2000000
1837 	#define BNXT_FLAG_ROCE_MIRROR_CAP	0x4000000
1838 	#define BNXT_FLAG_PORT_STATS_EXT	0x10000000
1839 
1840 	#define BNXT_FLAG_ALL_CONFIG_FEATS (BNXT_FLAG_TPA |		\
1841 					    BNXT_FLAG_RFS |		\
1842 					    BNXT_FLAG_STRIP_VLAN)
1843 
1844 #define BNXT_PF(bp)		(!((bp)->flags & BNXT_FLAG_VF))
1845 #define BNXT_VF(bp)		((bp)->flags & BNXT_FLAG_VF)
1846 #define BNXT_NPAR(bp)		((bp)->port_partition_type)
1847 #define BNXT_MH(bp)		((bp)->flags & BNXT_FLAG_MULTI_HOST)
1848 #define BNXT_SINGLE_PF(bp)	(BNXT_PF(bp) && !BNXT_NPAR(bp) && !BNXT_MH(bp))
1849 #define BNXT_SH_PORT_CFG_OK(bp)	(BNXT_PF(bp) &&				\
1850 				 ((bp)->phy_flags & BNXT_PHY_FL_SHARED_PORT_CFG))
1851 #define BNXT_PHY_CFG_ABLE(bp)	((BNXT_SINGLE_PF(bp) ||			\
1852 				  BNXT_SH_PORT_CFG_OK(bp)) &&		\
1853 				 (bp)->link_info.phy_state == BNXT_PHY_STATE_ENABLED)
1854 #define BNXT_CHIP_TYPE_NITRO_A0(bp) ((bp)->flags & BNXT_FLAG_CHIP_NITRO_A0)
1855 #define BNXT_RX_PAGE_MODE(bp)	((bp)->flags & BNXT_FLAG_RX_PAGE_MODE)
1856 #define BNXT_SUPPORTS_TPA(bp)	(!BNXT_CHIP_TYPE_NITRO_A0(bp) &&	\
1857 				 (!((bp)->flags & BNXT_FLAG_CHIP_P5) ||	\
1858 				  (bp)->max_tpa_v2) && !is_kdump_kernel())
1859 #define BNXT_RX_JUMBO_MODE(bp)	((bp)->flags & BNXT_FLAG_JUMBO)
1860 
1861 #define BNXT_CHIP_SR2(bp)			\
1862 	((bp)->chip_num == CHIP_NUM_58818)
1863 
1864 #define BNXT_CHIP_P5_THOR(bp)			\
1865 	((bp)->chip_num == CHIP_NUM_57508 ||	\
1866 	 (bp)->chip_num == CHIP_NUM_57504 ||	\
1867 	 (bp)->chip_num == CHIP_NUM_57502)
1868 
1869 /* Chip class phase 5 */
1870 #define BNXT_CHIP_P5(bp)			\
1871 	(BNXT_CHIP_P5_THOR(bp) || BNXT_CHIP_SR2(bp))
1872 
1873 /* Chip class phase 4.x */
1874 #define BNXT_CHIP_P4(bp)			\
1875 	(BNXT_CHIP_NUM_57X1X((bp)->chip_num) ||	\
1876 	 BNXT_CHIP_NUM_5745X((bp)->chip_num) ||	\
1877 	 BNXT_CHIP_NUM_588XX((bp)->chip_num) ||	\
1878 	 (BNXT_CHIP_NUM_58700((bp)->chip_num) &&	\
1879 	  !BNXT_CHIP_TYPE_NITRO_A0(bp)))
1880 
1881 #define BNXT_CHIP_P4_PLUS(bp)			\
1882 	(BNXT_CHIP_P4(bp) || BNXT_CHIP_P5(bp))
1883 
1884 	struct bnxt_aux_priv	*aux_priv;
1885 	struct bnxt_en_dev	*edev;
1886 
1887 	struct bnxt_napi	**bnapi;
1888 
1889 	struct bnxt_rx_ring_info	*rx_ring;
1890 	struct bnxt_tx_ring_info	*tx_ring;
1891 	u16			*tx_ring_map;
1892 
1893 	struct sk_buff *	(*gro_func)(struct bnxt_tpa_info *, int, int,
1894 					    struct sk_buff *);
1895 
1896 	struct sk_buff *	(*rx_skb_func)(struct bnxt *,
1897 					       struct bnxt_rx_ring_info *,
1898 					       u16, void *, u8 *, dma_addr_t,
1899 					       unsigned int);
1900 
1901 	u16			max_tpa_v2;
1902 	u16			max_tpa;
1903 	u32			rx_buf_size;
1904 	u32			rx_buf_use_size;	/* useable size */
1905 	u16			rx_offset;
1906 	u16			rx_dma_offset;
1907 	enum dma_data_direction	rx_dir;
1908 	u32			rx_ring_size;
1909 	u32			rx_agg_ring_size;
1910 	u32			rx_copy_thresh;
1911 	u32			rx_ring_mask;
1912 	u32			rx_agg_ring_mask;
1913 	int			rx_nr_pages;
1914 	int			rx_agg_nr_pages;
1915 	int			rx_nr_rings;
1916 	int			rsscos_nr_ctxs;
1917 
1918 	u32			tx_ring_size;
1919 	u32			tx_ring_mask;
1920 	int			tx_nr_pages;
1921 	int			tx_nr_rings;
1922 	int			tx_nr_rings_per_tc;
1923 	int			tx_nr_rings_xdp;
1924 
1925 	int			tx_wake_thresh;
1926 	int			tx_push_thresh;
1927 	int			tx_push_size;
1928 
1929 	u32			cp_ring_size;
1930 	u32			cp_ring_mask;
1931 	u32			cp_bit;
1932 	int			cp_nr_pages;
1933 	int			cp_nr_rings;
1934 
1935 	/* grp_info indexed by completion ring index */
1936 	struct bnxt_ring_grp_info	*grp_info;
1937 	struct bnxt_vnic_info	*vnic_info;
1938 	int			nr_vnics;
1939 	u16			*rss_indir_tbl;
1940 	u16			rss_indir_tbl_entries;
1941 	u32			rss_hash_cfg;
1942 	u32			rss_hash_delta;
1943 
1944 	u16			max_mtu;
1945 	u8			max_tc;
1946 	u8			max_lltc;	/* lossless TCs */
1947 	struct bnxt_queue_info	q_info[BNXT_MAX_QUEUE];
1948 	u8			tc_to_qidx[BNXT_MAX_QUEUE];
1949 	u8			q_ids[BNXT_MAX_QUEUE];
1950 	u8			max_q;
1951 
1952 	unsigned int		current_interval;
1953 #define BNXT_TIMER_INTERVAL	HZ
1954 
1955 	struct timer_list	timer;
1956 
1957 	unsigned long		state;
1958 #define BNXT_STATE_OPEN		0
1959 #define BNXT_STATE_IN_SP_TASK	1
1960 #define BNXT_STATE_READ_STATS	2
1961 #define BNXT_STATE_FW_RESET_DET 3
1962 #define BNXT_STATE_IN_FW_RESET	4
1963 #define BNXT_STATE_ABORT_ERR	5
1964 #define BNXT_STATE_FW_FATAL_COND	6
1965 #define BNXT_STATE_DRV_REGISTERED	7
1966 #define BNXT_STATE_PCI_CHANNEL_IO_FROZEN	8
1967 #define BNXT_STATE_NAPI_DISABLED	9
1968 #define BNXT_STATE_L2_FILTER_RETRY	10
1969 #define BNXT_STATE_FW_ACTIVATE		11
1970 #define BNXT_STATE_RECOVER		12
1971 #define BNXT_STATE_FW_NON_FATAL_COND	13
1972 #define BNXT_STATE_FW_ACTIVATE_RESET	14
1973 #define BNXT_STATE_HALF_OPEN		15	/* For offline ethtool tests */
1974 
1975 #define BNXT_NO_FW_ACCESS(bp)					\
1976 	(test_bit(BNXT_STATE_FW_FATAL_COND, &(bp)->state) ||	\
1977 	 pci_channel_offline((bp)->pdev))
1978 
1979 	struct bnxt_irq	*irq_tbl;
1980 	int			total_irqs;
1981 	u8			mac_addr[ETH_ALEN];
1982 
1983 #ifdef CONFIG_BNXT_DCB
1984 	struct ieee_pfc		*ieee_pfc;
1985 	struct ieee_ets		*ieee_ets;
1986 	u8			dcbx_cap;
1987 	u8			default_pri;
1988 	u8			max_dscp_value;
1989 #endif /* CONFIG_BNXT_DCB */
1990 
1991 	u32			msg_enable;
1992 
1993 	u64			fw_cap;
1994 	#define BNXT_FW_CAP_SHORT_CMD			BIT_ULL(0)
1995 	#define BNXT_FW_CAP_LLDP_AGENT			BIT_ULL(1)
1996 	#define BNXT_FW_CAP_DCBX_AGENT			BIT_ULL(2)
1997 	#define BNXT_FW_CAP_NEW_RM			BIT_ULL(3)
1998 	#define BNXT_FW_CAP_IF_CHANGE			BIT_ULL(4)
1999 	#define BNXT_FW_CAP_KONG_MB_CHNL		BIT_ULL(7)
2000 	#define BNXT_FW_CAP_OVS_64BIT_HANDLE		BIT_ULL(10)
2001 	#define BNXT_FW_CAP_TRUSTED_VF			BIT_ULL(11)
2002 	#define BNXT_FW_CAP_ERROR_RECOVERY		BIT_ULL(13)
2003 	#define BNXT_FW_CAP_PKG_VER			BIT_ULL(14)
2004 	#define BNXT_FW_CAP_CFA_ADV_FLOW		BIT_ULL(15)
2005 	#define BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V2	BIT_ULL(16)
2006 	#define BNXT_FW_CAP_PCIE_STATS_SUPPORTED	BIT_ULL(17)
2007 	#define BNXT_FW_CAP_EXT_STATS_SUPPORTED		BIT_ULL(18)
2008 	#define BNXT_FW_CAP_RSS_HASH_TYPE_DELTA		BIT_ULL(19)
2009 	#define BNXT_FW_CAP_ERR_RECOVER_RELOAD		BIT_ULL(20)
2010 	#define BNXT_FW_CAP_HOT_RESET			BIT_ULL(21)
2011 	#define BNXT_FW_CAP_PTP_RTC			BIT_ULL(22)
2012 	#define BNXT_FW_CAP_RX_ALL_PKT_TS		BIT_ULL(23)
2013 	#define BNXT_FW_CAP_VLAN_RX_STRIP		BIT_ULL(24)
2014 	#define BNXT_FW_CAP_VLAN_TX_INSERT		BIT_ULL(25)
2015 	#define BNXT_FW_CAP_EXT_HW_STATS_SUPPORTED	BIT_ULL(26)
2016 	#define BNXT_FW_CAP_LIVEPATCH			BIT_ULL(27)
2017 	#define BNXT_FW_CAP_PTP_PPS			BIT_ULL(28)
2018 	#define BNXT_FW_CAP_HOT_RESET_IF		BIT_ULL(29)
2019 	#define BNXT_FW_CAP_RING_MONITOR		BIT_ULL(30)
2020 	#define BNXT_FW_CAP_DBG_QCAPS			BIT_ULL(31)
2021 	#define BNXT_FW_CAP_PTP				BIT_ULL(32)
2022 
2023 	u32			fw_dbg_cap;
2024 
2025 #define BNXT_NEW_RM(bp)		((bp)->fw_cap & BNXT_FW_CAP_NEW_RM)
2026 #define BNXT_PTP_USE_RTC(bp)	(!BNXT_MH(bp) && \
2027 				 ((bp)->fw_cap & BNXT_FW_CAP_PTP_RTC))
2028 	u32			hwrm_spec_code;
2029 	u16			hwrm_cmd_seq;
2030 	u16                     hwrm_cmd_kong_seq;
2031 	struct dma_pool		*hwrm_dma_pool;
2032 	struct hlist_head	hwrm_pending_list;
2033 
2034 	struct rtnl_link_stats64	net_stats_prev;
2035 	struct bnxt_stats_mem	port_stats;
2036 	struct bnxt_stats_mem	rx_port_stats_ext;
2037 	struct bnxt_stats_mem	tx_port_stats_ext;
2038 	u16			fw_rx_stats_ext_size;
2039 	u16			fw_tx_stats_ext_size;
2040 	u16			hw_ring_stats_size;
2041 	u8			pri2cos_idx[8];
2042 	u8			pri2cos_valid;
2043 
2044 	struct bnxt_total_ring_err_stats ring_err_stats_prev;
2045 
2046 	u16			hwrm_max_req_len;
2047 	u16			hwrm_max_ext_req_len;
2048 	unsigned int		hwrm_cmd_timeout;
2049 	unsigned int		hwrm_cmd_max_timeout;
2050 	struct mutex		hwrm_cmd_lock;	/* serialize hwrm messages */
2051 	struct hwrm_ver_get_output	ver_resp;
2052 #define FW_VER_STR_LEN		32
2053 #define BC_HWRM_STR_LEN		21
2054 #define PHY_VER_STR_LEN         (FW_VER_STR_LEN - BC_HWRM_STR_LEN)
2055 	char			fw_ver_str[FW_VER_STR_LEN];
2056 	char			hwrm_ver_supp[FW_VER_STR_LEN];
2057 	char			nvm_cfg_ver[FW_VER_STR_LEN];
2058 	u64			fw_ver_code;
2059 #define BNXT_FW_VER_CODE(maj, min, bld, rsv)			\
2060 	((u64)(maj) << 48 | (u64)(min) << 32 | (u64)(bld) << 16 | (rsv))
2061 #define BNXT_FW_MAJ(bp)		((bp)->fw_ver_code >> 48)
2062 
2063 	u16			vxlan_fw_dst_port_id;
2064 	u16			nge_fw_dst_port_id;
2065 	__be16			vxlan_port;
2066 	__be16			nge_port;
2067 	u8			port_partition_type;
2068 	u8			port_count;
2069 	u16			br_mode;
2070 
2071 	struct bnxt_coal_cap	coal_cap;
2072 	struct bnxt_coal	rx_coal;
2073 	struct bnxt_coal	tx_coal;
2074 
2075 	u32			stats_coal_ticks;
2076 #define BNXT_DEF_STATS_COAL_TICKS	 1000000
2077 #define BNXT_MIN_STATS_COAL_TICKS	  250000
2078 #define BNXT_MAX_STATS_COAL_TICKS	 1000000
2079 
2080 	struct work_struct	sp_task;
2081 	unsigned long		sp_event;
2082 #define BNXT_RX_MASK_SP_EVENT		0
2083 #define BNXT_RX_NTP_FLTR_SP_EVENT	1
2084 #define BNXT_LINK_CHNG_SP_EVENT		2
2085 #define BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT	3
2086 #define BNXT_RESET_TASK_SP_EVENT	6
2087 #define BNXT_RST_RING_SP_EVENT		7
2088 #define BNXT_HWRM_PF_UNLOAD_SP_EVENT	8
2089 #define BNXT_PERIODIC_STATS_SP_EVENT	9
2090 #define BNXT_HWRM_PORT_MODULE_SP_EVENT	10
2091 #define BNXT_RESET_TASK_SILENT_SP_EVENT	11
2092 #define BNXT_LINK_SPEED_CHNG_SP_EVENT	14
2093 #define BNXT_FLOW_STATS_SP_EVENT	15
2094 #define BNXT_UPDATE_PHY_SP_EVENT	16
2095 #define BNXT_RING_COAL_NOW_SP_EVENT	17
2096 #define BNXT_FW_RESET_NOTIFY_SP_EVENT	18
2097 #define BNXT_FW_EXCEPTION_SP_EVENT	19
2098 #define BNXT_LINK_CFG_CHANGE_SP_EVENT	21
2099 #define BNXT_FW_ECHO_REQUEST_SP_EVENT	23
2100 
2101 	struct delayed_work	fw_reset_task;
2102 	int			fw_reset_state;
2103 #define BNXT_FW_RESET_STATE_POLL_VF	1
2104 #define BNXT_FW_RESET_STATE_RESET_FW	2
2105 #define BNXT_FW_RESET_STATE_ENABLE_DEV	3
2106 #define BNXT_FW_RESET_STATE_POLL_FW	4
2107 #define BNXT_FW_RESET_STATE_OPENING	5
2108 #define BNXT_FW_RESET_STATE_POLL_FW_DOWN	6
2109 
2110 	u16			fw_reset_min_dsecs;
2111 #define BNXT_DFLT_FW_RST_MIN_DSECS	20
2112 	u16			fw_reset_max_dsecs;
2113 #define BNXT_DFLT_FW_RST_MAX_DSECS	60
2114 	unsigned long		fw_reset_timestamp;
2115 
2116 	struct bnxt_fw_health	*fw_health;
2117 
2118 	struct bnxt_hw_resc	hw_resc;
2119 	struct bnxt_pf_info	pf;
2120 	struct bnxt_ctx_mem_info	*ctx;
2121 #ifdef CONFIG_BNXT_SRIOV
2122 	int			nr_vfs;
2123 	struct bnxt_vf_info	vf;
2124 	wait_queue_head_t	sriov_cfg_wait;
2125 	bool			sriov_cfg;
2126 #define BNXT_SRIOV_CFG_WAIT_TMO	msecs_to_jiffies(10000)
2127 #endif
2128 
2129 #if BITS_PER_LONG == 32
2130 	/* ensure atomic 64-bit doorbell writes on 32-bit systems. */
2131 	spinlock_t		db_lock;
2132 #endif
2133 	int			db_size;
2134 
2135 #define BNXT_NTP_FLTR_MAX_FLTR	4096
2136 #define BNXT_NTP_FLTR_HASH_SIZE	512
2137 #define BNXT_NTP_FLTR_HASH_MASK	(BNXT_NTP_FLTR_HASH_SIZE - 1)
2138 	struct hlist_head	ntp_fltr_hash_tbl[BNXT_NTP_FLTR_HASH_SIZE];
2139 	spinlock_t		ntp_fltr_lock;	/* for hash table add, del */
2140 
2141 	unsigned long		*ntp_fltr_bmap;
2142 	int			ntp_fltr_count;
2143 
2144 	/* To protect link related settings during link changes and
2145 	 * ethtool settings changes.
2146 	 */
2147 	struct mutex		link_lock;
2148 	struct bnxt_link_info	link_info;
2149 	struct ethtool_eee	eee;
2150 	u32			lpi_tmr_lo;
2151 	u32			lpi_tmr_hi;
2152 
2153 	/* copied from flags and flags2 in hwrm_port_phy_qcaps_output */
2154 	u32			phy_flags;
2155 #define BNXT_PHY_FL_EEE_CAP		PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED
2156 #define BNXT_PHY_FL_EXT_LPBK		PORT_PHY_QCAPS_RESP_FLAGS_EXTERNAL_LPBK_SUPPORTED
2157 #define BNXT_PHY_FL_AN_PHY_LPBK		PORT_PHY_QCAPS_RESP_FLAGS_AUTONEG_LPBK_SUPPORTED
2158 #define BNXT_PHY_FL_SHARED_PORT_CFG	PORT_PHY_QCAPS_RESP_FLAGS_SHARED_PHY_CFG_SUPPORTED
2159 #define BNXT_PHY_FL_PORT_STATS_NO_RESET	PORT_PHY_QCAPS_RESP_FLAGS_CUMULATIVE_COUNTERS_ON_RESET
2160 #define BNXT_PHY_FL_NO_PHY_LPBK		PORT_PHY_QCAPS_RESP_FLAGS_LOCAL_LPBK_NOT_SUPPORTED
2161 #define BNXT_PHY_FL_FW_MANAGED_LKDN	PORT_PHY_QCAPS_RESP_FLAGS_FW_MANAGED_LINK_DOWN
2162 #define BNXT_PHY_FL_NO_FCS		PORT_PHY_QCAPS_RESP_FLAGS_NO_FCS
2163 #define BNXT_PHY_FL_NO_PAUSE		(PORT_PHY_QCAPS_RESP_FLAGS2_PAUSE_UNSUPPORTED << 8)
2164 #define BNXT_PHY_FL_NO_PFC		(PORT_PHY_QCAPS_RESP_FLAGS2_PFC_UNSUPPORTED << 8)
2165 #define BNXT_PHY_FL_BANK_SEL		(PORT_PHY_QCAPS_RESP_FLAGS2_BANK_ADDR_SUPPORTED << 8)
2166 
2167 	u8			num_tests;
2168 	struct bnxt_test_info	*test_info;
2169 
2170 	u8			wol_filter_id;
2171 	u8			wol;
2172 
2173 	u8			num_leds;
2174 	struct bnxt_led_info	leds[BNXT_MAX_LED];
2175 	u16			dump_flag;
2176 #define BNXT_DUMP_LIVE		0
2177 #define BNXT_DUMP_CRASH		1
2178 
2179 	struct bpf_prog		*xdp_prog;
2180 
2181 	struct bnxt_ptp_cfg	*ptp_cfg;
2182 	u8			ptp_all_rx_tstamp;
2183 
2184 	/* devlink interface and vf-rep structs */
2185 	struct devlink		*dl;
2186 	struct devlink_port	dl_port;
2187 	enum devlink_eswitch_mode eswitch_mode;
2188 	struct bnxt_vf_rep	**vf_reps; /* array of vf-rep ptrs */
2189 	u16			*cfa_code_map; /* cfa_code -> vf_idx map */
2190 	u8			dsn[8];
2191 	struct bnxt_tc_info	*tc_info;
2192 	struct list_head	tc_indr_block_list;
2193 	struct dentry		*debugfs_pdev;
2194 	struct device		*hwmon_dev;
2195 	enum board_idx		board_idx;
2196 };
2197 
2198 #define BNXT_NUM_RX_RING_STATS			8
2199 #define BNXT_NUM_TX_RING_STATS			8
2200 #define BNXT_NUM_TPA_RING_STATS			4
2201 #define BNXT_NUM_TPA_RING_STATS_P5		5
2202 #define BNXT_NUM_TPA_RING_STATS_P5_SR2		6
2203 
2204 #define BNXT_RING_STATS_SIZE_P5					\
2205 	((BNXT_NUM_RX_RING_STATS + BNXT_NUM_TX_RING_STATS +	\
2206 	  BNXT_NUM_TPA_RING_STATS_P5) * 8)
2207 
2208 #define BNXT_RING_STATS_SIZE_P5_SR2				\
2209 	((BNXT_NUM_RX_RING_STATS + BNXT_NUM_TX_RING_STATS +	\
2210 	  BNXT_NUM_TPA_RING_STATS_P5_SR2) * 8)
2211 
2212 #define BNXT_GET_RING_STATS64(sw, counter)		\
2213 	(*((sw) + offsetof(struct ctx_hw_stats, counter) / 8))
2214 
2215 #define BNXT_GET_RX_PORT_STATS64(sw, counter)		\
2216 	(*((sw) + offsetof(struct rx_port_stats, counter) / 8))
2217 
2218 #define BNXT_GET_TX_PORT_STATS64(sw, counter)		\
2219 	(*((sw) + offsetof(struct tx_port_stats, counter) / 8))
2220 
2221 #define BNXT_PORT_STATS_SIZE				\
2222 	(sizeof(struct rx_port_stats) + sizeof(struct tx_port_stats) + 1024)
2223 
2224 #define BNXT_TX_PORT_STATS_BYTE_OFFSET			\
2225 	(sizeof(struct rx_port_stats) + 512)
2226 
2227 #define BNXT_RX_STATS_OFFSET(counter)			\
2228 	(offsetof(struct rx_port_stats, counter) / 8)
2229 
2230 #define BNXT_TX_STATS_OFFSET(counter)			\
2231 	((offsetof(struct tx_port_stats, counter) +	\
2232 	  BNXT_TX_PORT_STATS_BYTE_OFFSET) / 8)
2233 
2234 #define BNXT_RX_STATS_EXT_OFFSET(counter)		\
2235 	(offsetof(struct rx_port_stats_ext, counter) / 8)
2236 
2237 #define BNXT_RX_STATS_EXT_NUM_LEGACY                   \
2238 	BNXT_RX_STATS_EXT_OFFSET(rx_fec_corrected_blocks)
2239 
2240 #define BNXT_TX_STATS_EXT_OFFSET(counter)		\
2241 	(offsetof(struct tx_port_stats_ext, counter) / 8)
2242 
2243 #define BNXT_HW_FEATURE_VLAN_ALL_RX				\
2244 	(NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)
2245 #define BNXT_HW_FEATURE_VLAN_ALL_TX				\
2246 	(NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_STAG_TX)
2247 
2248 #define I2C_DEV_ADDR_A0				0xa0
2249 #define I2C_DEV_ADDR_A2				0xa2
2250 #define SFF_DIAG_SUPPORT_OFFSET			0x5c
2251 #define SFF_MODULE_ID_SFP			0x3
2252 #define SFF_MODULE_ID_QSFP			0xc
2253 #define SFF_MODULE_ID_QSFP_PLUS			0xd
2254 #define SFF_MODULE_ID_QSFP28			0x11
2255 #define BNXT_MAX_PHY_I2C_RESP_SIZE		64
2256 
2257 static inline u32 bnxt_tx_avail(struct bnxt *bp,
2258 				const struct bnxt_tx_ring_info *txr)
2259 {
2260 	u32 used = READ_ONCE(txr->tx_prod) - READ_ONCE(txr->tx_cons);
2261 
2262 	return bp->tx_ring_size - (used & bp->tx_ring_mask);
2263 }
2264 
2265 static inline void bnxt_writeq(struct bnxt *bp, u64 val,
2266 			       volatile void __iomem *addr)
2267 {
2268 #if BITS_PER_LONG == 32
2269 	spin_lock(&bp->db_lock);
2270 	lo_hi_writeq(val, addr);
2271 	spin_unlock(&bp->db_lock);
2272 #else
2273 	writeq(val, addr);
2274 #endif
2275 }
2276 
2277 static inline void bnxt_writeq_relaxed(struct bnxt *bp, u64 val,
2278 				       volatile void __iomem *addr)
2279 {
2280 #if BITS_PER_LONG == 32
2281 	spin_lock(&bp->db_lock);
2282 	lo_hi_writeq_relaxed(val, addr);
2283 	spin_unlock(&bp->db_lock);
2284 #else
2285 	writeq_relaxed(val, addr);
2286 #endif
2287 }
2288 
2289 /* For TX and RX ring doorbells with no ordering guarantee*/
2290 static inline void bnxt_db_write_relaxed(struct bnxt *bp,
2291 					 struct bnxt_db_info *db, u32 idx)
2292 {
2293 	if (bp->flags & BNXT_FLAG_CHIP_P5) {
2294 		bnxt_writeq_relaxed(bp, db->db_key64 | idx, db->doorbell);
2295 	} else {
2296 		u32 db_val = db->db_key32 | idx;
2297 
2298 		writel_relaxed(db_val, db->doorbell);
2299 		if (bp->flags & BNXT_FLAG_DOUBLE_DB)
2300 			writel_relaxed(db_val, db->doorbell);
2301 	}
2302 }
2303 
2304 /* For TX and RX ring doorbells */
2305 static inline void bnxt_db_write(struct bnxt *bp, struct bnxt_db_info *db,
2306 				 u32 idx)
2307 {
2308 	if (bp->flags & BNXT_FLAG_CHIP_P5) {
2309 		bnxt_writeq(bp, db->db_key64 | idx, db->doorbell);
2310 	} else {
2311 		u32 db_val = db->db_key32 | idx;
2312 
2313 		writel(db_val, db->doorbell);
2314 		if (bp->flags & BNXT_FLAG_DOUBLE_DB)
2315 			writel(db_val, db->doorbell);
2316 	}
2317 }
2318 
2319 /* Must hold rtnl_lock */
2320 static inline bool bnxt_sriov_cfg(struct bnxt *bp)
2321 {
2322 #if defined(CONFIG_BNXT_SRIOV)
2323 	return BNXT_PF(bp) && (bp->pf.active_vfs || bp->sriov_cfg);
2324 #else
2325 	return false;
2326 #endif
2327 }
2328 
2329 extern const u16 bnxt_lhint_arr[];
2330 
2331 int bnxt_alloc_rx_data(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
2332 		       u16 prod, gfp_t gfp);
2333 void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons, void *data);
2334 u32 bnxt_fw_health_readl(struct bnxt *bp, int reg_idx);
2335 void bnxt_set_tpa_flags(struct bnxt *bp);
2336 void bnxt_set_ring_params(struct bnxt *);
2337 int bnxt_set_rx_skb_mode(struct bnxt *bp, bool page_mode);
2338 int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp, unsigned long *bmap,
2339 			    int bmap_size, bool async_only);
2340 int bnxt_hwrm_func_drv_unrgtr(struct bnxt *bp);
2341 int bnxt_get_nr_rss_ctxs(struct bnxt *bp, int rx_rings);
2342 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id);
2343 int __bnxt_hwrm_get_tx_rings(struct bnxt *bp, u16 fid, int *tx_rings);
2344 int bnxt_nq_rings_in_use(struct bnxt *bp);
2345 int bnxt_hwrm_set_coal(struct bnxt *);
2346 void bnxt_free_ctx_mem(struct bnxt *bp);
2347 unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt *bp);
2348 unsigned int bnxt_get_avail_stat_ctxs_for_en(struct bnxt *bp);
2349 unsigned int bnxt_get_max_func_cp_rings(struct bnxt *bp);
2350 unsigned int bnxt_get_avail_cp_rings_for_en(struct bnxt *bp);
2351 int bnxt_get_avail_msix(struct bnxt *bp, int num);
2352 int bnxt_reserve_rings(struct bnxt *bp, bool irq_re_init);
2353 void bnxt_tx_disable(struct bnxt *bp);
2354 void bnxt_tx_enable(struct bnxt *bp);
2355 void bnxt_sched_reset_txr(struct bnxt *bp, struct bnxt_tx_ring_info *txr,
2356 			  int idx);
2357 void bnxt_report_link(struct bnxt *bp);
2358 int bnxt_update_link(struct bnxt *bp, bool chng_link_state);
2359 int bnxt_hwrm_set_pause(struct bnxt *);
2360 int bnxt_hwrm_set_link_setting(struct bnxt *, bool, bool);
2361 int bnxt_cancel_reservations(struct bnxt *bp, bool fw_reset);
2362 int bnxt_hwrm_alloc_wol_fltr(struct bnxt *bp);
2363 int bnxt_hwrm_free_wol_fltr(struct bnxt *bp);
2364 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp, bool all);
2365 int bnxt_hwrm_func_qcaps(struct bnxt *bp);
2366 int bnxt_hwrm_fw_set_time(struct bnxt *);
2367 int bnxt_open_nic(struct bnxt *, bool, bool);
2368 int bnxt_half_open_nic(struct bnxt *bp);
2369 void bnxt_half_close_nic(struct bnxt *bp);
2370 void bnxt_reenable_sriov(struct bnxt *bp);
2371 void bnxt_close_nic(struct bnxt *, bool, bool);
2372 void bnxt_get_ring_err_stats(struct bnxt *bp,
2373 			     struct bnxt_total_ring_err_stats *stats);
2374 int bnxt_dbg_hwrm_rd_reg(struct bnxt *bp, u32 reg_off, u16 num_words,
2375 			 u32 *reg_buf);
2376 void bnxt_fw_exception(struct bnxt *bp);
2377 void bnxt_fw_reset(struct bnxt *bp);
2378 int bnxt_check_rings(struct bnxt *bp, int tx, int rx, bool sh, int tcs,
2379 		     int tx_xdp);
2380 int bnxt_fw_init_one(struct bnxt *bp);
2381 bool bnxt_hwrm_reset_permitted(struct bnxt *bp);
2382 int bnxt_setup_mq_tc(struct net_device *dev, u8 tc);
2383 int bnxt_get_max_rings(struct bnxt *, int *, int *, bool);
2384 int bnxt_restore_pf_fw_resources(struct bnxt *bp);
2385 int bnxt_get_port_parent_id(struct net_device *dev,
2386 			    struct netdev_phys_item_id *ppid);
2387 void bnxt_dim_work(struct work_struct *work);
2388 int bnxt_hwrm_set_ring_coal(struct bnxt *bp, struct bnxt_napi *bnapi);
2389 void bnxt_print_device_info(struct bnxt *bp);
2390 #endif
2391