1 /* Broadcom NetXtreme-C/E network driver. 2 * 3 * Copyright (c) 2014-2016 Broadcom Corporation 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation. 8 */ 9 10 #include <linux/module.h> 11 12 #include <linux/stringify.h> 13 #include <linux/kernel.h> 14 #include <linux/timer.h> 15 #include <linux/errno.h> 16 #include <linux/ioport.h> 17 #include <linux/slab.h> 18 #include <linux/vmalloc.h> 19 #include <linux/interrupt.h> 20 #include <linux/pci.h> 21 #include <linux/netdevice.h> 22 #include <linux/etherdevice.h> 23 #include <linux/skbuff.h> 24 #include <linux/dma-mapping.h> 25 #include <linux/bitops.h> 26 #include <linux/io.h> 27 #include <linux/irq.h> 28 #include <linux/delay.h> 29 #include <asm/byteorder.h> 30 #include <asm/page.h> 31 #include <linux/time.h> 32 #include <linux/mii.h> 33 #include <linux/if.h> 34 #include <linux/if_vlan.h> 35 #include <linux/rtc.h> 36 #include <net/ip.h> 37 #include <net/tcp.h> 38 #include <net/udp.h> 39 #include <net/checksum.h> 40 #include <net/ip6_checksum.h> 41 #include <net/udp_tunnel.h> 42 #ifdef CONFIG_NET_RX_BUSY_POLL 43 #include <net/busy_poll.h> 44 #endif 45 #include <linux/workqueue.h> 46 #include <linux/prefetch.h> 47 #include <linux/cache.h> 48 #include <linux/log2.h> 49 #include <linux/aer.h> 50 #include <linux/bitmap.h> 51 #include <linux/cpu_rmap.h> 52 53 #include "bnxt_hsi.h" 54 #include "bnxt.h" 55 #include "bnxt_sriov.h" 56 #include "bnxt_ethtool.h" 57 58 #define BNXT_TX_TIMEOUT (5 * HZ) 59 60 static const char version[] = 61 "Broadcom NetXtreme-C/E driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION "\n"; 62 63 MODULE_LICENSE("GPL"); 64 MODULE_DESCRIPTION("Broadcom BCM573xx network driver"); 65 MODULE_VERSION(DRV_MODULE_VERSION); 66 67 #define BNXT_RX_OFFSET (NET_SKB_PAD + NET_IP_ALIGN) 68 #define BNXT_RX_DMA_OFFSET NET_SKB_PAD 69 #define BNXT_RX_COPY_THRESH 256 70 71 #define BNXT_TX_PUSH_THRESH 164 72 73 enum board_idx { 74 BCM57301, 75 BCM57302, 76 BCM57304, 77 BCM57417_NPAR, 78 BCM58700, 79 BCM57311, 80 BCM57312, 81 BCM57402, 82 BCM57404, 83 BCM57406, 84 BCM57402_NPAR, 85 BCM57407, 86 BCM57412, 87 BCM57414, 88 BCM57416, 89 BCM57417, 90 BCM57412_NPAR, 91 BCM57314, 92 BCM57417_SFP, 93 BCM57416_SFP, 94 BCM57404_NPAR, 95 BCM57406_NPAR, 96 BCM57407_SFP, 97 BCM57407_NPAR, 98 BCM57414_NPAR, 99 BCM57416_NPAR, 100 NETXTREME_E_VF, 101 NETXTREME_C_VF, 102 }; 103 104 /* indexed by enum above */ 105 static const struct { 106 char *name; 107 } board_info[] = { 108 { "Broadcom BCM57301 NetXtreme-C 10Gb Ethernet" }, 109 { "Broadcom BCM57302 NetXtreme-C 10Gb/25Gb Ethernet" }, 110 { "Broadcom BCM57304 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" }, 111 { "Broadcom BCM57417 NetXtreme-E Ethernet Partition" }, 112 { "Broadcom BCM58700 Nitro 1Gb/2.5Gb/10Gb Ethernet" }, 113 { "Broadcom BCM57311 NetXtreme-C 10Gb Ethernet" }, 114 { "Broadcom BCM57312 NetXtreme-C 10Gb/25Gb Ethernet" }, 115 { "Broadcom BCM57402 NetXtreme-E 10Gb Ethernet" }, 116 { "Broadcom BCM57404 NetXtreme-E 10Gb/25Gb Ethernet" }, 117 { "Broadcom BCM57406 NetXtreme-E 10GBase-T Ethernet" }, 118 { "Broadcom BCM57402 NetXtreme-E Ethernet Partition" }, 119 { "Broadcom BCM57407 NetXtreme-E 10GBase-T Ethernet" }, 120 { "Broadcom BCM57412 NetXtreme-E 10Gb Ethernet" }, 121 { "Broadcom BCM57414 NetXtreme-E 10Gb/25Gb Ethernet" }, 122 { "Broadcom BCM57416 NetXtreme-E 10GBase-T Ethernet" }, 123 { "Broadcom BCM57417 NetXtreme-E 10GBase-T Ethernet" }, 124 { "Broadcom BCM57412 NetXtreme-E Ethernet Partition" }, 125 { "Broadcom BCM57314 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" }, 126 { "Broadcom BCM57417 NetXtreme-E 10Gb/25Gb Ethernet" }, 127 { "Broadcom BCM57416 NetXtreme-E 10Gb Ethernet" }, 128 { "Broadcom BCM57404 NetXtreme-E Ethernet Partition" }, 129 { "Broadcom BCM57406 NetXtreme-E Ethernet Partition" }, 130 { "Broadcom BCM57407 NetXtreme-E 25Gb Ethernet" }, 131 { "Broadcom BCM57407 NetXtreme-E Ethernet Partition" }, 132 { "Broadcom BCM57414 NetXtreme-E Ethernet Partition" }, 133 { "Broadcom BCM57416 NetXtreme-E Ethernet Partition" }, 134 { "Broadcom NetXtreme-E Ethernet Virtual Function" }, 135 { "Broadcom NetXtreme-C Ethernet Virtual Function" }, 136 }; 137 138 static const struct pci_device_id bnxt_pci_tbl[] = { 139 { PCI_VDEVICE(BROADCOM, 0x16c0), .driver_data = BCM57417_NPAR }, 140 { PCI_VDEVICE(BROADCOM, 0x16c8), .driver_data = BCM57301 }, 141 { PCI_VDEVICE(BROADCOM, 0x16c9), .driver_data = BCM57302 }, 142 { PCI_VDEVICE(BROADCOM, 0x16ca), .driver_data = BCM57304 }, 143 { PCI_VDEVICE(BROADCOM, 0x16cc), .driver_data = BCM57417_NPAR }, 144 { PCI_VDEVICE(BROADCOM, 0x16cd), .driver_data = BCM58700 }, 145 { PCI_VDEVICE(BROADCOM, 0x16ce), .driver_data = BCM57311 }, 146 { PCI_VDEVICE(BROADCOM, 0x16cf), .driver_data = BCM57312 }, 147 { PCI_VDEVICE(BROADCOM, 0x16d0), .driver_data = BCM57402 }, 148 { PCI_VDEVICE(BROADCOM, 0x16d1), .driver_data = BCM57404 }, 149 { PCI_VDEVICE(BROADCOM, 0x16d2), .driver_data = BCM57406 }, 150 { PCI_VDEVICE(BROADCOM, 0x16d4), .driver_data = BCM57402_NPAR }, 151 { PCI_VDEVICE(BROADCOM, 0x16d5), .driver_data = BCM57407 }, 152 { PCI_VDEVICE(BROADCOM, 0x16d6), .driver_data = BCM57412 }, 153 { PCI_VDEVICE(BROADCOM, 0x16d7), .driver_data = BCM57414 }, 154 { PCI_VDEVICE(BROADCOM, 0x16d8), .driver_data = BCM57416 }, 155 { PCI_VDEVICE(BROADCOM, 0x16d9), .driver_data = BCM57417 }, 156 { PCI_VDEVICE(BROADCOM, 0x16de), .driver_data = BCM57412_NPAR }, 157 { PCI_VDEVICE(BROADCOM, 0x16df), .driver_data = BCM57314 }, 158 { PCI_VDEVICE(BROADCOM, 0x16e2), .driver_data = BCM57417_SFP }, 159 { PCI_VDEVICE(BROADCOM, 0x16e3), .driver_data = BCM57416_SFP }, 160 { PCI_VDEVICE(BROADCOM, 0x16e7), .driver_data = BCM57404_NPAR }, 161 { PCI_VDEVICE(BROADCOM, 0x16e8), .driver_data = BCM57406_NPAR }, 162 { PCI_VDEVICE(BROADCOM, 0x16e9), .driver_data = BCM57407_SFP }, 163 { PCI_VDEVICE(BROADCOM, 0x16ea), .driver_data = BCM57407_NPAR }, 164 { PCI_VDEVICE(BROADCOM, 0x16eb), .driver_data = BCM57412_NPAR }, 165 { PCI_VDEVICE(BROADCOM, 0x16ec), .driver_data = BCM57414_NPAR }, 166 { PCI_VDEVICE(BROADCOM, 0x16ed), .driver_data = BCM57414_NPAR }, 167 { PCI_VDEVICE(BROADCOM, 0x16ee), .driver_data = BCM57416_NPAR }, 168 { PCI_VDEVICE(BROADCOM, 0x16ef), .driver_data = BCM57416_NPAR }, 169 #ifdef CONFIG_BNXT_SRIOV 170 { PCI_VDEVICE(BROADCOM, 0x16c1), .driver_data = NETXTREME_E_VF }, 171 { PCI_VDEVICE(BROADCOM, 0x16cb), .driver_data = NETXTREME_C_VF }, 172 { PCI_VDEVICE(BROADCOM, 0x16d3), .driver_data = NETXTREME_E_VF }, 173 { PCI_VDEVICE(BROADCOM, 0x16dc), .driver_data = NETXTREME_E_VF }, 174 { PCI_VDEVICE(BROADCOM, 0x16e1), .driver_data = NETXTREME_C_VF }, 175 { PCI_VDEVICE(BROADCOM, 0x16e5), .driver_data = NETXTREME_C_VF }, 176 #endif 177 { 0 } 178 }; 179 180 MODULE_DEVICE_TABLE(pci, bnxt_pci_tbl); 181 182 static const u16 bnxt_vf_req_snif[] = { 183 HWRM_FUNC_CFG, 184 HWRM_PORT_PHY_QCFG, 185 HWRM_CFA_L2_FILTER_ALLOC, 186 }; 187 188 static const u16 bnxt_async_events_arr[] = { 189 HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE, 190 HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD, 191 HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED, 192 HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE, 193 HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE, 194 }; 195 196 static bool bnxt_vf_pciid(enum board_idx idx) 197 { 198 return (idx == NETXTREME_C_VF || idx == NETXTREME_E_VF); 199 } 200 201 #define DB_CP_REARM_FLAGS (DB_KEY_CP | DB_IDX_VALID) 202 #define DB_CP_FLAGS (DB_KEY_CP | DB_IDX_VALID | DB_IRQ_DIS) 203 #define DB_CP_IRQ_DIS_FLAGS (DB_KEY_CP | DB_IRQ_DIS) 204 205 #define BNXT_CP_DB_REARM(db, raw_cons) \ 206 writel(DB_CP_REARM_FLAGS | RING_CMP(raw_cons), db) 207 208 #define BNXT_CP_DB(db, raw_cons) \ 209 writel(DB_CP_FLAGS | RING_CMP(raw_cons), db) 210 211 #define BNXT_CP_DB_IRQ_DIS(db) \ 212 writel(DB_CP_IRQ_DIS_FLAGS, db) 213 214 static inline u32 bnxt_tx_avail(struct bnxt *bp, struct bnxt_tx_ring_info *txr) 215 { 216 /* Tell compiler to fetch tx indices from memory. */ 217 barrier(); 218 219 return bp->tx_ring_size - 220 ((txr->tx_prod - txr->tx_cons) & bp->tx_ring_mask); 221 } 222 223 static const u16 bnxt_lhint_arr[] = { 224 TX_BD_FLAGS_LHINT_512_AND_SMALLER, 225 TX_BD_FLAGS_LHINT_512_TO_1023, 226 TX_BD_FLAGS_LHINT_1024_TO_2047, 227 TX_BD_FLAGS_LHINT_1024_TO_2047, 228 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 229 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 230 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 231 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 232 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 233 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 234 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 235 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 236 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 237 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 238 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 239 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 240 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 241 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 242 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 243 }; 244 245 static netdev_tx_t bnxt_start_xmit(struct sk_buff *skb, struct net_device *dev) 246 { 247 struct bnxt *bp = netdev_priv(dev); 248 struct tx_bd *txbd; 249 struct tx_bd_ext *txbd1; 250 struct netdev_queue *txq; 251 int i; 252 dma_addr_t mapping; 253 unsigned int length, pad = 0; 254 u32 len, free_size, vlan_tag_flags, cfa_action, flags; 255 u16 prod, last_frag; 256 struct pci_dev *pdev = bp->pdev; 257 struct bnxt_tx_ring_info *txr; 258 struct bnxt_sw_tx_bd *tx_buf; 259 260 i = skb_get_queue_mapping(skb); 261 if (unlikely(i >= bp->tx_nr_rings)) { 262 dev_kfree_skb_any(skb); 263 return NETDEV_TX_OK; 264 } 265 266 txr = &bp->tx_ring[i]; 267 txq = netdev_get_tx_queue(dev, i); 268 prod = txr->tx_prod; 269 270 free_size = bnxt_tx_avail(bp, txr); 271 if (unlikely(free_size < skb_shinfo(skb)->nr_frags + 2)) { 272 netif_tx_stop_queue(txq); 273 return NETDEV_TX_BUSY; 274 } 275 276 length = skb->len; 277 len = skb_headlen(skb); 278 last_frag = skb_shinfo(skb)->nr_frags; 279 280 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)]; 281 282 txbd->tx_bd_opaque = prod; 283 284 tx_buf = &txr->tx_buf_ring[prod]; 285 tx_buf->skb = skb; 286 tx_buf->nr_frags = last_frag; 287 288 vlan_tag_flags = 0; 289 cfa_action = 0; 290 if (skb_vlan_tag_present(skb)) { 291 vlan_tag_flags = TX_BD_CFA_META_KEY_VLAN | 292 skb_vlan_tag_get(skb); 293 /* Currently supports 8021Q, 8021AD vlan offloads 294 * QINQ1, QINQ2, QINQ3 vlan headers are deprecated 295 */ 296 if (skb->vlan_proto == htons(ETH_P_8021Q)) 297 vlan_tag_flags |= 1 << TX_BD_CFA_META_TPID_SHIFT; 298 } 299 300 if (free_size == bp->tx_ring_size && length <= bp->tx_push_thresh) { 301 struct tx_push_buffer *tx_push_buf = txr->tx_push; 302 struct tx_push_bd *tx_push = &tx_push_buf->push_bd; 303 struct tx_bd_ext *tx_push1 = &tx_push->txbd2; 304 void *pdata = tx_push_buf->data; 305 u64 *end; 306 int j, push_len; 307 308 /* Set COAL_NOW to be ready quickly for the next push */ 309 tx_push->tx_bd_len_flags_type = 310 cpu_to_le32((length << TX_BD_LEN_SHIFT) | 311 TX_BD_TYPE_LONG_TX_BD | 312 TX_BD_FLAGS_LHINT_512_AND_SMALLER | 313 TX_BD_FLAGS_COAL_NOW | 314 TX_BD_FLAGS_PACKET_END | 315 (2 << TX_BD_FLAGS_BD_CNT_SHIFT)); 316 317 if (skb->ip_summed == CHECKSUM_PARTIAL) 318 tx_push1->tx_bd_hsize_lflags = 319 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM); 320 else 321 tx_push1->tx_bd_hsize_lflags = 0; 322 323 tx_push1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags); 324 tx_push1->tx_bd_cfa_action = cpu_to_le32(cfa_action); 325 326 end = pdata + length; 327 end = PTR_ALIGN(end, 8) - 1; 328 *end = 0; 329 330 skb_copy_from_linear_data(skb, pdata, len); 331 pdata += len; 332 for (j = 0; j < last_frag; j++) { 333 skb_frag_t *frag = &skb_shinfo(skb)->frags[j]; 334 void *fptr; 335 336 fptr = skb_frag_address_safe(frag); 337 if (!fptr) 338 goto normal_tx; 339 340 memcpy(pdata, fptr, skb_frag_size(frag)); 341 pdata += skb_frag_size(frag); 342 } 343 344 txbd->tx_bd_len_flags_type = tx_push->tx_bd_len_flags_type; 345 txbd->tx_bd_haddr = txr->data_mapping; 346 prod = NEXT_TX(prod); 347 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)]; 348 memcpy(txbd, tx_push1, sizeof(*txbd)); 349 prod = NEXT_TX(prod); 350 tx_push->doorbell = 351 cpu_to_le32(DB_KEY_TX_PUSH | DB_LONG_TX_PUSH | prod); 352 txr->tx_prod = prod; 353 354 tx_buf->is_push = 1; 355 netdev_tx_sent_queue(txq, skb->len); 356 wmb(); /* Sync is_push and byte queue before pushing data */ 357 358 push_len = (length + sizeof(*tx_push) + 7) / 8; 359 if (push_len > 16) { 360 __iowrite64_copy(txr->tx_doorbell, tx_push_buf, 16); 361 __iowrite32_copy(txr->tx_doorbell + 4, tx_push_buf + 1, 362 (push_len - 16) << 1); 363 } else { 364 __iowrite64_copy(txr->tx_doorbell, tx_push_buf, 365 push_len); 366 } 367 368 goto tx_done; 369 } 370 371 normal_tx: 372 if (length < BNXT_MIN_PKT_SIZE) { 373 pad = BNXT_MIN_PKT_SIZE - length; 374 if (skb_pad(skb, pad)) { 375 /* SKB already freed. */ 376 tx_buf->skb = NULL; 377 return NETDEV_TX_OK; 378 } 379 length = BNXT_MIN_PKT_SIZE; 380 } 381 382 mapping = dma_map_single(&pdev->dev, skb->data, len, DMA_TO_DEVICE); 383 384 if (unlikely(dma_mapping_error(&pdev->dev, mapping))) { 385 dev_kfree_skb_any(skb); 386 tx_buf->skb = NULL; 387 return NETDEV_TX_OK; 388 } 389 390 dma_unmap_addr_set(tx_buf, mapping, mapping); 391 flags = (len << TX_BD_LEN_SHIFT) | TX_BD_TYPE_LONG_TX_BD | 392 ((last_frag + 2) << TX_BD_FLAGS_BD_CNT_SHIFT); 393 394 txbd->tx_bd_haddr = cpu_to_le64(mapping); 395 396 prod = NEXT_TX(prod); 397 txbd1 = (struct tx_bd_ext *) 398 &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)]; 399 400 txbd1->tx_bd_hsize_lflags = 0; 401 if (skb_is_gso(skb)) { 402 u32 hdr_len; 403 404 if (skb->encapsulation) 405 hdr_len = skb_inner_network_offset(skb) + 406 skb_inner_network_header_len(skb) + 407 inner_tcp_hdrlen(skb); 408 else 409 hdr_len = skb_transport_offset(skb) + 410 tcp_hdrlen(skb); 411 412 txbd1->tx_bd_hsize_lflags = cpu_to_le32(TX_BD_FLAGS_LSO | 413 TX_BD_FLAGS_T_IPID | 414 (hdr_len << (TX_BD_HSIZE_SHIFT - 1))); 415 length = skb_shinfo(skb)->gso_size; 416 txbd1->tx_bd_mss = cpu_to_le32(length); 417 length += hdr_len; 418 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 419 txbd1->tx_bd_hsize_lflags = 420 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM); 421 txbd1->tx_bd_mss = 0; 422 } 423 424 length >>= 9; 425 flags |= bnxt_lhint_arr[length]; 426 txbd->tx_bd_len_flags_type = cpu_to_le32(flags); 427 428 txbd1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags); 429 txbd1->tx_bd_cfa_action = cpu_to_le32(cfa_action); 430 for (i = 0; i < last_frag; i++) { 431 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 432 433 prod = NEXT_TX(prod); 434 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)]; 435 436 len = skb_frag_size(frag); 437 mapping = skb_frag_dma_map(&pdev->dev, frag, 0, len, 438 DMA_TO_DEVICE); 439 440 if (unlikely(dma_mapping_error(&pdev->dev, mapping))) 441 goto tx_dma_error; 442 443 tx_buf = &txr->tx_buf_ring[prod]; 444 dma_unmap_addr_set(tx_buf, mapping, mapping); 445 446 txbd->tx_bd_haddr = cpu_to_le64(mapping); 447 448 flags = len << TX_BD_LEN_SHIFT; 449 txbd->tx_bd_len_flags_type = cpu_to_le32(flags); 450 } 451 452 flags &= ~TX_BD_LEN; 453 txbd->tx_bd_len_flags_type = 454 cpu_to_le32(((len + pad) << TX_BD_LEN_SHIFT) | flags | 455 TX_BD_FLAGS_PACKET_END); 456 457 netdev_tx_sent_queue(txq, skb->len); 458 459 /* Sync BD data before updating doorbell */ 460 wmb(); 461 462 prod = NEXT_TX(prod); 463 txr->tx_prod = prod; 464 465 writel(DB_KEY_TX | prod, txr->tx_doorbell); 466 writel(DB_KEY_TX | prod, txr->tx_doorbell); 467 468 tx_done: 469 470 mmiowb(); 471 472 if (unlikely(bnxt_tx_avail(bp, txr) <= MAX_SKB_FRAGS + 1)) { 473 netif_tx_stop_queue(txq); 474 475 /* netif_tx_stop_queue() must be done before checking 476 * tx index in bnxt_tx_avail() below, because in 477 * bnxt_tx_int(), we update tx index before checking for 478 * netif_tx_queue_stopped(). 479 */ 480 smp_mb(); 481 if (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh) 482 netif_tx_wake_queue(txq); 483 } 484 return NETDEV_TX_OK; 485 486 tx_dma_error: 487 last_frag = i; 488 489 /* start back at beginning and unmap skb */ 490 prod = txr->tx_prod; 491 tx_buf = &txr->tx_buf_ring[prod]; 492 tx_buf->skb = NULL; 493 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping), 494 skb_headlen(skb), PCI_DMA_TODEVICE); 495 prod = NEXT_TX(prod); 496 497 /* unmap remaining mapped pages */ 498 for (i = 0; i < last_frag; i++) { 499 prod = NEXT_TX(prod); 500 tx_buf = &txr->tx_buf_ring[prod]; 501 dma_unmap_page(&pdev->dev, dma_unmap_addr(tx_buf, mapping), 502 skb_frag_size(&skb_shinfo(skb)->frags[i]), 503 PCI_DMA_TODEVICE); 504 } 505 506 dev_kfree_skb_any(skb); 507 return NETDEV_TX_OK; 508 } 509 510 static void bnxt_tx_int(struct bnxt *bp, struct bnxt_napi *bnapi, int nr_pkts) 511 { 512 struct bnxt_tx_ring_info *txr = bnapi->tx_ring; 513 int index = txr - &bp->tx_ring[0]; 514 struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, index); 515 u16 cons = txr->tx_cons; 516 struct pci_dev *pdev = bp->pdev; 517 int i; 518 unsigned int tx_bytes = 0; 519 520 for (i = 0; i < nr_pkts; i++) { 521 struct bnxt_sw_tx_bd *tx_buf; 522 struct sk_buff *skb; 523 int j, last; 524 525 tx_buf = &txr->tx_buf_ring[cons]; 526 cons = NEXT_TX(cons); 527 skb = tx_buf->skb; 528 tx_buf->skb = NULL; 529 530 if (tx_buf->is_push) { 531 tx_buf->is_push = 0; 532 goto next_tx_int; 533 } 534 535 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping), 536 skb_headlen(skb), PCI_DMA_TODEVICE); 537 last = tx_buf->nr_frags; 538 539 for (j = 0; j < last; j++) { 540 cons = NEXT_TX(cons); 541 tx_buf = &txr->tx_buf_ring[cons]; 542 dma_unmap_page( 543 &pdev->dev, 544 dma_unmap_addr(tx_buf, mapping), 545 skb_frag_size(&skb_shinfo(skb)->frags[j]), 546 PCI_DMA_TODEVICE); 547 } 548 549 next_tx_int: 550 cons = NEXT_TX(cons); 551 552 tx_bytes += skb->len; 553 dev_kfree_skb_any(skb); 554 } 555 556 netdev_tx_completed_queue(txq, nr_pkts, tx_bytes); 557 txr->tx_cons = cons; 558 559 /* Need to make the tx_cons update visible to bnxt_start_xmit() 560 * before checking for netif_tx_queue_stopped(). Without the 561 * memory barrier, there is a small possibility that bnxt_start_xmit() 562 * will miss it and cause the queue to be stopped forever. 563 */ 564 smp_mb(); 565 566 if (unlikely(netif_tx_queue_stopped(txq)) && 567 (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)) { 568 __netif_tx_lock(txq, smp_processor_id()); 569 if (netif_tx_queue_stopped(txq) && 570 bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh && 571 txr->dev_state != BNXT_DEV_STATE_CLOSING) 572 netif_tx_wake_queue(txq); 573 __netif_tx_unlock(txq); 574 } 575 } 576 577 static inline u8 *__bnxt_alloc_rx_data(struct bnxt *bp, dma_addr_t *mapping, 578 gfp_t gfp) 579 { 580 u8 *data; 581 struct pci_dev *pdev = bp->pdev; 582 583 data = kmalloc(bp->rx_buf_size, gfp); 584 if (!data) 585 return NULL; 586 587 *mapping = dma_map_single(&pdev->dev, data + BNXT_RX_DMA_OFFSET, 588 bp->rx_buf_use_size, PCI_DMA_FROMDEVICE); 589 590 if (dma_mapping_error(&pdev->dev, *mapping)) { 591 kfree(data); 592 data = NULL; 593 } 594 return data; 595 } 596 597 static inline int bnxt_alloc_rx_data(struct bnxt *bp, 598 struct bnxt_rx_ring_info *rxr, 599 u16 prod, gfp_t gfp) 600 { 601 struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)]; 602 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[prod]; 603 u8 *data; 604 dma_addr_t mapping; 605 606 data = __bnxt_alloc_rx_data(bp, &mapping, gfp); 607 if (!data) 608 return -ENOMEM; 609 610 rx_buf->data = data; 611 dma_unmap_addr_set(rx_buf, mapping, mapping); 612 613 rxbd->rx_bd_haddr = cpu_to_le64(mapping); 614 615 return 0; 616 } 617 618 static void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons, 619 u8 *data) 620 { 621 u16 prod = rxr->rx_prod; 622 struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf; 623 struct rx_bd *cons_bd, *prod_bd; 624 625 prod_rx_buf = &rxr->rx_buf_ring[prod]; 626 cons_rx_buf = &rxr->rx_buf_ring[cons]; 627 628 prod_rx_buf->data = data; 629 630 dma_unmap_addr_set(prod_rx_buf, mapping, 631 dma_unmap_addr(cons_rx_buf, mapping)); 632 633 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)]; 634 cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)]; 635 636 prod_bd->rx_bd_haddr = cons_bd->rx_bd_haddr; 637 } 638 639 static inline u16 bnxt_find_next_agg_idx(struct bnxt_rx_ring_info *rxr, u16 idx) 640 { 641 u16 next, max = rxr->rx_agg_bmap_size; 642 643 next = find_next_zero_bit(rxr->rx_agg_bmap, max, idx); 644 if (next >= max) 645 next = find_first_zero_bit(rxr->rx_agg_bmap, max); 646 return next; 647 } 648 649 static inline int bnxt_alloc_rx_page(struct bnxt *bp, 650 struct bnxt_rx_ring_info *rxr, 651 u16 prod, gfp_t gfp) 652 { 653 struct rx_bd *rxbd = 654 &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)]; 655 struct bnxt_sw_rx_agg_bd *rx_agg_buf; 656 struct pci_dev *pdev = bp->pdev; 657 struct page *page; 658 dma_addr_t mapping; 659 u16 sw_prod = rxr->rx_sw_agg_prod; 660 unsigned int offset = 0; 661 662 if (PAGE_SIZE > BNXT_RX_PAGE_SIZE) { 663 page = rxr->rx_page; 664 if (!page) { 665 page = alloc_page(gfp); 666 if (!page) 667 return -ENOMEM; 668 rxr->rx_page = page; 669 rxr->rx_page_offset = 0; 670 } 671 offset = rxr->rx_page_offset; 672 rxr->rx_page_offset += BNXT_RX_PAGE_SIZE; 673 if (rxr->rx_page_offset == PAGE_SIZE) 674 rxr->rx_page = NULL; 675 else 676 get_page(page); 677 } else { 678 page = alloc_page(gfp); 679 if (!page) 680 return -ENOMEM; 681 } 682 683 mapping = dma_map_page(&pdev->dev, page, offset, BNXT_RX_PAGE_SIZE, 684 PCI_DMA_FROMDEVICE); 685 if (dma_mapping_error(&pdev->dev, mapping)) { 686 __free_page(page); 687 return -EIO; 688 } 689 690 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap))) 691 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod); 692 693 __set_bit(sw_prod, rxr->rx_agg_bmap); 694 rx_agg_buf = &rxr->rx_agg_ring[sw_prod]; 695 rxr->rx_sw_agg_prod = NEXT_RX_AGG(sw_prod); 696 697 rx_agg_buf->page = page; 698 rx_agg_buf->offset = offset; 699 rx_agg_buf->mapping = mapping; 700 rxbd->rx_bd_haddr = cpu_to_le64(mapping); 701 rxbd->rx_bd_opaque = sw_prod; 702 return 0; 703 } 704 705 static void bnxt_reuse_rx_agg_bufs(struct bnxt_napi *bnapi, u16 cp_cons, 706 u32 agg_bufs) 707 { 708 struct bnxt *bp = bnapi->bp; 709 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 710 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 711 u16 prod = rxr->rx_agg_prod; 712 u16 sw_prod = rxr->rx_sw_agg_prod; 713 u32 i; 714 715 for (i = 0; i < agg_bufs; i++) { 716 u16 cons; 717 struct rx_agg_cmp *agg; 718 struct bnxt_sw_rx_agg_bd *cons_rx_buf, *prod_rx_buf; 719 struct rx_bd *prod_bd; 720 struct page *page; 721 722 agg = (struct rx_agg_cmp *) 723 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 724 cons = agg->rx_agg_cmp_opaque; 725 __clear_bit(cons, rxr->rx_agg_bmap); 726 727 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap))) 728 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod); 729 730 __set_bit(sw_prod, rxr->rx_agg_bmap); 731 prod_rx_buf = &rxr->rx_agg_ring[sw_prod]; 732 cons_rx_buf = &rxr->rx_agg_ring[cons]; 733 734 /* It is possible for sw_prod to be equal to cons, so 735 * set cons_rx_buf->page to NULL first. 736 */ 737 page = cons_rx_buf->page; 738 cons_rx_buf->page = NULL; 739 prod_rx_buf->page = page; 740 prod_rx_buf->offset = cons_rx_buf->offset; 741 742 prod_rx_buf->mapping = cons_rx_buf->mapping; 743 744 prod_bd = &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)]; 745 746 prod_bd->rx_bd_haddr = cpu_to_le64(cons_rx_buf->mapping); 747 prod_bd->rx_bd_opaque = sw_prod; 748 749 prod = NEXT_RX_AGG(prod); 750 sw_prod = NEXT_RX_AGG(sw_prod); 751 cp_cons = NEXT_CMP(cp_cons); 752 } 753 rxr->rx_agg_prod = prod; 754 rxr->rx_sw_agg_prod = sw_prod; 755 } 756 757 static struct sk_buff *bnxt_rx_skb(struct bnxt *bp, 758 struct bnxt_rx_ring_info *rxr, u16 cons, 759 u16 prod, u8 *data, dma_addr_t dma_addr, 760 unsigned int len) 761 { 762 int err; 763 struct sk_buff *skb; 764 765 err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC); 766 if (unlikely(err)) { 767 bnxt_reuse_rx_data(rxr, cons, data); 768 return NULL; 769 } 770 771 skb = build_skb(data, 0); 772 dma_unmap_single(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size, 773 PCI_DMA_FROMDEVICE); 774 if (!skb) { 775 kfree(data); 776 return NULL; 777 } 778 779 skb_reserve(skb, BNXT_RX_OFFSET); 780 skb_put(skb, len); 781 return skb; 782 } 783 784 static struct sk_buff *bnxt_rx_pages(struct bnxt *bp, struct bnxt_napi *bnapi, 785 struct sk_buff *skb, u16 cp_cons, 786 u32 agg_bufs) 787 { 788 struct pci_dev *pdev = bp->pdev; 789 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 790 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 791 u16 prod = rxr->rx_agg_prod; 792 u32 i; 793 794 for (i = 0; i < agg_bufs; i++) { 795 u16 cons, frag_len; 796 struct rx_agg_cmp *agg; 797 struct bnxt_sw_rx_agg_bd *cons_rx_buf; 798 struct page *page; 799 dma_addr_t mapping; 800 801 agg = (struct rx_agg_cmp *) 802 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 803 cons = agg->rx_agg_cmp_opaque; 804 frag_len = (le32_to_cpu(agg->rx_agg_cmp_len_flags_type) & 805 RX_AGG_CMP_LEN) >> RX_AGG_CMP_LEN_SHIFT; 806 807 cons_rx_buf = &rxr->rx_agg_ring[cons]; 808 skb_fill_page_desc(skb, i, cons_rx_buf->page, 809 cons_rx_buf->offset, frag_len); 810 __clear_bit(cons, rxr->rx_agg_bmap); 811 812 /* It is possible for bnxt_alloc_rx_page() to allocate 813 * a sw_prod index that equals the cons index, so we 814 * need to clear the cons entry now. 815 */ 816 mapping = dma_unmap_addr(cons_rx_buf, mapping); 817 page = cons_rx_buf->page; 818 cons_rx_buf->page = NULL; 819 820 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_ATOMIC) != 0) { 821 struct skb_shared_info *shinfo; 822 unsigned int nr_frags; 823 824 shinfo = skb_shinfo(skb); 825 nr_frags = --shinfo->nr_frags; 826 __skb_frag_set_page(&shinfo->frags[nr_frags], NULL); 827 828 dev_kfree_skb(skb); 829 830 cons_rx_buf->page = page; 831 832 /* Update prod since possibly some pages have been 833 * allocated already. 834 */ 835 rxr->rx_agg_prod = prod; 836 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs - i); 837 return NULL; 838 } 839 840 dma_unmap_page(&pdev->dev, mapping, BNXT_RX_PAGE_SIZE, 841 PCI_DMA_FROMDEVICE); 842 843 skb->data_len += frag_len; 844 skb->len += frag_len; 845 skb->truesize += PAGE_SIZE; 846 847 prod = NEXT_RX_AGG(prod); 848 cp_cons = NEXT_CMP(cp_cons); 849 } 850 rxr->rx_agg_prod = prod; 851 return skb; 852 } 853 854 static int bnxt_agg_bufs_valid(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, 855 u8 agg_bufs, u32 *raw_cons) 856 { 857 u16 last; 858 struct rx_agg_cmp *agg; 859 860 *raw_cons = ADV_RAW_CMP(*raw_cons, agg_bufs); 861 last = RING_CMP(*raw_cons); 862 agg = (struct rx_agg_cmp *) 863 &cpr->cp_desc_ring[CP_RING(last)][CP_IDX(last)]; 864 return RX_AGG_CMP_VALID(agg, *raw_cons); 865 } 866 867 static inline struct sk_buff *bnxt_copy_skb(struct bnxt_napi *bnapi, u8 *data, 868 unsigned int len, 869 dma_addr_t mapping) 870 { 871 struct bnxt *bp = bnapi->bp; 872 struct pci_dev *pdev = bp->pdev; 873 struct sk_buff *skb; 874 875 skb = napi_alloc_skb(&bnapi->napi, len); 876 if (!skb) 877 return NULL; 878 879 dma_sync_single_for_cpu(&pdev->dev, mapping, 880 bp->rx_copy_thresh, PCI_DMA_FROMDEVICE); 881 882 memcpy(skb->data - BNXT_RX_OFFSET, data, len + BNXT_RX_OFFSET); 883 884 dma_sync_single_for_device(&pdev->dev, mapping, 885 bp->rx_copy_thresh, 886 PCI_DMA_FROMDEVICE); 887 888 skb_put(skb, len); 889 return skb; 890 } 891 892 static int bnxt_discard_rx(struct bnxt *bp, struct bnxt_napi *bnapi, 893 u32 *raw_cons, void *cmp) 894 { 895 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 896 struct rx_cmp *rxcmp = cmp; 897 u32 tmp_raw_cons = *raw_cons; 898 u8 cmp_type, agg_bufs = 0; 899 900 cmp_type = RX_CMP_TYPE(rxcmp); 901 902 if (cmp_type == CMP_TYPE_RX_L2_CMP) { 903 agg_bufs = (le32_to_cpu(rxcmp->rx_cmp_misc_v1) & 904 RX_CMP_AGG_BUFS) >> 905 RX_CMP_AGG_BUFS_SHIFT; 906 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) { 907 struct rx_tpa_end_cmp *tpa_end = cmp; 908 909 agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) & 910 RX_TPA_END_CMP_AGG_BUFS) >> 911 RX_TPA_END_CMP_AGG_BUFS_SHIFT; 912 } 913 914 if (agg_bufs) { 915 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons)) 916 return -EBUSY; 917 } 918 *raw_cons = tmp_raw_cons; 919 return 0; 920 } 921 922 static void bnxt_sched_reset(struct bnxt *bp, struct bnxt_rx_ring_info *rxr) 923 { 924 if (!rxr->bnapi->in_reset) { 925 rxr->bnapi->in_reset = true; 926 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event); 927 schedule_work(&bp->sp_task); 928 } 929 rxr->rx_next_cons = 0xffff; 930 } 931 932 static void bnxt_tpa_start(struct bnxt *bp, struct bnxt_rx_ring_info *rxr, 933 struct rx_tpa_start_cmp *tpa_start, 934 struct rx_tpa_start_cmp_ext *tpa_start1) 935 { 936 u8 agg_id = TPA_START_AGG_ID(tpa_start); 937 u16 cons, prod; 938 struct bnxt_tpa_info *tpa_info; 939 struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf; 940 struct rx_bd *prod_bd; 941 dma_addr_t mapping; 942 943 cons = tpa_start->rx_tpa_start_cmp_opaque; 944 prod = rxr->rx_prod; 945 cons_rx_buf = &rxr->rx_buf_ring[cons]; 946 prod_rx_buf = &rxr->rx_buf_ring[prod]; 947 tpa_info = &rxr->rx_tpa[agg_id]; 948 949 if (unlikely(cons != rxr->rx_next_cons)) { 950 bnxt_sched_reset(bp, rxr); 951 return; 952 } 953 954 prod_rx_buf->data = tpa_info->data; 955 956 mapping = tpa_info->mapping; 957 dma_unmap_addr_set(prod_rx_buf, mapping, mapping); 958 959 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)]; 960 961 prod_bd->rx_bd_haddr = cpu_to_le64(mapping); 962 963 tpa_info->data = cons_rx_buf->data; 964 cons_rx_buf->data = NULL; 965 tpa_info->mapping = dma_unmap_addr(cons_rx_buf, mapping); 966 967 tpa_info->len = 968 le32_to_cpu(tpa_start->rx_tpa_start_cmp_len_flags_type) >> 969 RX_TPA_START_CMP_LEN_SHIFT; 970 if (likely(TPA_START_HASH_VALID(tpa_start))) { 971 u32 hash_type = TPA_START_HASH_TYPE(tpa_start); 972 973 tpa_info->hash_type = PKT_HASH_TYPE_L4; 974 tpa_info->gso_type = SKB_GSO_TCPV4; 975 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */ 976 if (hash_type == 3) 977 tpa_info->gso_type = SKB_GSO_TCPV6; 978 tpa_info->rss_hash = 979 le32_to_cpu(tpa_start->rx_tpa_start_cmp_rss_hash); 980 } else { 981 tpa_info->hash_type = PKT_HASH_TYPE_NONE; 982 tpa_info->gso_type = 0; 983 if (netif_msg_rx_err(bp)) 984 netdev_warn(bp->dev, "TPA packet without valid hash\n"); 985 } 986 tpa_info->flags2 = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_flags2); 987 tpa_info->metadata = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_metadata); 988 tpa_info->hdr_info = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_hdr_info); 989 990 rxr->rx_prod = NEXT_RX(prod); 991 cons = NEXT_RX(cons); 992 rxr->rx_next_cons = NEXT_RX(cons); 993 cons_rx_buf = &rxr->rx_buf_ring[cons]; 994 995 bnxt_reuse_rx_data(rxr, cons, cons_rx_buf->data); 996 rxr->rx_prod = NEXT_RX(rxr->rx_prod); 997 cons_rx_buf->data = NULL; 998 } 999 1000 static void bnxt_abort_tpa(struct bnxt *bp, struct bnxt_napi *bnapi, 1001 u16 cp_cons, u32 agg_bufs) 1002 { 1003 if (agg_bufs) 1004 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs); 1005 } 1006 1007 static struct sk_buff *bnxt_gro_func_5731x(struct bnxt_tpa_info *tpa_info, 1008 int payload_off, int tcp_ts, 1009 struct sk_buff *skb) 1010 { 1011 #ifdef CONFIG_INET 1012 struct tcphdr *th; 1013 int len, nw_off; 1014 u16 outer_ip_off, inner_ip_off, inner_mac_off; 1015 u32 hdr_info = tpa_info->hdr_info; 1016 bool loopback = false; 1017 1018 inner_ip_off = BNXT_TPA_INNER_L3_OFF(hdr_info); 1019 inner_mac_off = BNXT_TPA_INNER_L2_OFF(hdr_info); 1020 outer_ip_off = BNXT_TPA_OUTER_L3_OFF(hdr_info); 1021 1022 /* If the packet is an internal loopback packet, the offsets will 1023 * have an extra 4 bytes. 1024 */ 1025 if (inner_mac_off == 4) { 1026 loopback = true; 1027 } else if (inner_mac_off > 4) { 1028 __be16 proto = *((__be16 *)(skb->data + inner_ip_off - 1029 ETH_HLEN - 2)); 1030 1031 /* We only support inner iPv4/ipv6. If we don't see the 1032 * correct protocol ID, it must be a loopback packet where 1033 * the offsets are off by 4. 1034 */ 1035 if (proto != htons(ETH_P_IP) && proto != htons(ETH_P_IPV6)) 1036 loopback = true; 1037 } 1038 if (loopback) { 1039 /* internal loopback packet, subtract all offsets by 4 */ 1040 inner_ip_off -= 4; 1041 inner_mac_off -= 4; 1042 outer_ip_off -= 4; 1043 } 1044 1045 nw_off = inner_ip_off - ETH_HLEN; 1046 skb_set_network_header(skb, nw_off); 1047 if (tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_IP_TYPE) { 1048 struct ipv6hdr *iph = ipv6_hdr(skb); 1049 1050 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr)); 1051 len = skb->len - skb_transport_offset(skb); 1052 th = tcp_hdr(skb); 1053 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0); 1054 } else { 1055 struct iphdr *iph = ip_hdr(skb); 1056 1057 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr)); 1058 len = skb->len - skb_transport_offset(skb); 1059 th = tcp_hdr(skb); 1060 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0); 1061 } 1062 1063 if (inner_mac_off) { /* tunnel */ 1064 struct udphdr *uh = NULL; 1065 __be16 proto = *((__be16 *)(skb->data + outer_ip_off - 1066 ETH_HLEN - 2)); 1067 1068 if (proto == htons(ETH_P_IP)) { 1069 struct iphdr *iph = (struct iphdr *)skb->data; 1070 1071 if (iph->protocol == IPPROTO_UDP) 1072 uh = (struct udphdr *)(iph + 1); 1073 } else { 1074 struct ipv6hdr *iph = (struct ipv6hdr *)skb->data; 1075 1076 if (iph->nexthdr == IPPROTO_UDP) 1077 uh = (struct udphdr *)(iph + 1); 1078 } 1079 if (uh) { 1080 if (uh->check) 1081 skb_shinfo(skb)->gso_type |= 1082 SKB_GSO_UDP_TUNNEL_CSUM; 1083 else 1084 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL; 1085 } 1086 } 1087 #endif 1088 return skb; 1089 } 1090 1091 #define BNXT_IPV4_HDR_SIZE (sizeof(struct iphdr) + sizeof(struct tcphdr)) 1092 #define BNXT_IPV6_HDR_SIZE (sizeof(struct ipv6hdr) + sizeof(struct tcphdr)) 1093 1094 static struct sk_buff *bnxt_gro_func_5730x(struct bnxt_tpa_info *tpa_info, 1095 int payload_off, int tcp_ts, 1096 struct sk_buff *skb) 1097 { 1098 #ifdef CONFIG_INET 1099 struct tcphdr *th; 1100 int len, nw_off, tcp_opt_len; 1101 1102 if (tcp_ts) 1103 tcp_opt_len = 12; 1104 1105 if (tpa_info->gso_type == SKB_GSO_TCPV4) { 1106 struct iphdr *iph; 1107 1108 nw_off = payload_off - BNXT_IPV4_HDR_SIZE - tcp_opt_len - 1109 ETH_HLEN; 1110 skb_set_network_header(skb, nw_off); 1111 iph = ip_hdr(skb); 1112 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr)); 1113 len = skb->len - skb_transport_offset(skb); 1114 th = tcp_hdr(skb); 1115 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0); 1116 } else if (tpa_info->gso_type == SKB_GSO_TCPV6) { 1117 struct ipv6hdr *iph; 1118 1119 nw_off = payload_off - BNXT_IPV6_HDR_SIZE - tcp_opt_len - 1120 ETH_HLEN; 1121 skb_set_network_header(skb, nw_off); 1122 iph = ipv6_hdr(skb); 1123 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr)); 1124 len = skb->len - skb_transport_offset(skb); 1125 th = tcp_hdr(skb); 1126 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0); 1127 } else { 1128 dev_kfree_skb_any(skb); 1129 return NULL; 1130 } 1131 tcp_gro_complete(skb); 1132 1133 if (nw_off) { /* tunnel */ 1134 struct udphdr *uh = NULL; 1135 1136 if (skb->protocol == htons(ETH_P_IP)) { 1137 struct iphdr *iph = (struct iphdr *)skb->data; 1138 1139 if (iph->protocol == IPPROTO_UDP) 1140 uh = (struct udphdr *)(iph + 1); 1141 } else { 1142 struct ipv6hdr *iph = (struct ipv6hdr *)skb->data; 1143 1144 if (iph->nexthdr == IPPROTO_UDP) 1145 uh = (struct udphdr *)(iph + 1); 1146 } 1147 if (uh) { 1148 if (uh->check) 1149 skb_shinfo(skb)->gso_type |= 1150 SKB_GSO_UDP_TUNNEL_CSUM; 1151 else 1152 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL; 1153 } 1154 } 1155 #endif 1156 return skb; 1157 } 1158 1159 static inline struct sk_buff *bnxt_gro_skb(struct bnxt *bp, 1160 struct bnxt_tpa_info *tpa_info, 1161 struct rx_tpa_end_cmp *tpa_end, 1162 struct rx_tpa_end_cmp_ext *tpa_end1, 1163 struct sk_buff *skb) 1164 { 1165 #ifdef CONFIG_INET 1166 int payload_off; 1167 u16 segs; 1168 1169 segs = TPA_END_TPA_SEGS(tpa_end); 1170 if (segs == 1) 1171 return skb; 1172 1173 NAPI_GRO_CB(skb)->count = segs; 1174 skb_shinfo(skb)->gso_size = 1175 le32_to_cpu(tpa_end1->rx_tpa_end_cmp_seg_len); 1176 skb_shinfo(skb)->gso_type = tpa_info->gso_type; 1177 payload_off = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) & 1178 RX_TPA_END_CMP_PAYLOAD_OFFSET) >> 1179 RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT; 1180 skb = bp->gro_func(tpa_info, payload_off, TPA_END_GRO_TS(tpa_end), skb); 1181 #endif 1182 return skb; 1183 } 1184 1185 static inline struct sk_buff *bnxt_tpa_end(struct bnxt *bp, 1186 struct bnxt_napi *bnapi, 1187 u32 *raw_cons, 1188 struct rx_tpa_end_cmp *tpa_end, 1189 struct rx_tpa_end_cmp_ext *tpa_end1, 1190 bool *agg_event) 1191 { 1192 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 1193 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 1194 u8 agg_id = TPA_END_AGG_ID(tpa_end); 1195 u8 *data, agg_bufs; 1196 u16 cp_cons = RING_CMP(*raw_cons); 1197 unsigned int len; 1198 struct bnxt_tpa_info *tpa_info; 1199 dma_addr_t mapping; 1200 struct sk_buff *skb; 1201 1202 if (unlikely(bnapi->in_reset)) { 1203 int rc = bnxt_discard_rx(bp, bnapi, raw_cons, tpa_end); 1204 1205 if (rc < 0) 1206 return ERR_PTR(-EBUSY); 1207 return NULL; 1208 } 1209 1210 tpa_info = &rxr->rx_tpa[agg_id]; 1211 data = tpa_info->data; 1212 prefetch(data); 1213 len = tpa_info->len; 1214 mapping = tpa_info->mapping; 1215 1216 agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) & 1217 RX_TPA_END_CMP_AGG_BUFS) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT; 1218 1219 if (agg_bufs) { 1220 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, raw_cons)) 1221 return ERR_PTR(-EBUSY); 1222 1223 *agg_event = true; 1224 cp_cons = NEXT_CMP(cp_cons); 1225 } 1226 1227 if (unlikely(agg_bufs > MAX_SKB_FRAGS)) { 1228 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs); 1229 netdev_warn(bp->dev, "TPA frags %d exceeded MAX_SKB_FRAGS %d\n", 1230 agg_bufs, (int)MAX_SKB_FRAGS); 1231 return NULL; 1232 } 1233 1234 if (len <= bp->rx_copy_thresh) { 1235 skb = bnxt_copy_skb(bnapi, data, len, mapping); 1236 if (!skb) { 1237 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs); 1238 return NULL; 1239 } 1240 } else { 1241 u8 *new_data; 1242 dma_addr_t new_mapping; 1243 1244 new_data = __bnxt_alloc_rx_data(bp, &new_mapping, GFP_ATOMIC); 1245 if (!new_data) { 1246 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs); 1247 return NULL; 1248 } 1249 1250 tpa_info->data = new_data; 1251 tpa_info->mapping = new_mapping; 1252 1253 skb = build_skb(data, 0); 1254 dma_unmap_single(&bp->pdev->dev, mapping, bp->rx_buf_use_size, 1255 PCI_DMA_FROMDEVICE); 1256 1257 if (!skb) { 1258 kfree(data); 1259 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs); 1260 return NULL; 1261 } 1262 skb_reserve(skb, BNXT_RX_OFFSET); 1263 skb_put(skb, len); 1264 } 1265 1266 if (agg_bufs) { 1267 skb = bnxt_rx_pages(bp, bnapi, skb, cp_cons, agg_bufs); 1268 if (!skb) { 1269 /* Page reuse already handled by bnxt_rx_pages(). */ 1270 return NULL; 1271 } 1272 } 1273 skb->protocol = eth_type_trans(skb, bp->dev); 1274 1275 if (tpa_info->hash_type != PKT_HASH_TYPE_NONE) 1276 skb_set_hash(skb, tpa_info->rss_hash, tpa_info->hash_type); 1277 1278 if ((tpa_info->flags2 & RX_CMP_FLAGS2_META_FORMAT_VLAN) && 1279 (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) { 1280 u16 vlan_proto = tpa_info->metadata >> 1281 RX_CMP_FLAGS2_METADATA_TPID_SFT; 1282 u16 vtag = tpa_info->metadata & RX_CMP_FLAGS2_METADATA_VID_MASK; 1283 1284 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag); 1285 } 1286 1287 skb_checksum_none_assert(skb); 1288 if (likely(tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_L4_CS_CALC)) { 1289 skb->ip_summed = CHECKSUM_UNNECESSARY; 1290 skb->csum_level = 1291 (tpa_info->flags2 & RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3; 1292 } 1293 1294 if (TPA_END_GRO(tpa_end)) 1295 skb = bnxt_gro_skb(bp, tpa_info, tpa_end, tpa_end1, skb); 1296 1297 return skb; 1298 } 1299 1300 /* returns the following: 1301 * 1 - 1 packet successfully received 1302 * 0 - successful TPA_START, packet not completed yet 1303 * -EBUSY - completion ring does not have all the agg buffers yet 1304 * -ENOMEM - packet aborted due to out of memory 1305 * -EIO - packet aborted due to hw error indicated in BD 1306 */ 1307 static int bnxt_rx_pkt(struct bnxt *bp, struct bnxt_napi *bnapi, u32 *raw_cons, 1308 bool *agg_event) 1309 { 1310 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 1311 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 1312 struct net_device *dev = bp->dev; 1313 struct rx_cmp *rxcmp; 1314 struct rx_cmp_ext *rxcmp1; 1315 u32 tmp_raw_cons = *raw_cons; 1316 u16 cons, prod, cp_cons = RING_CMP(tmp_raw_cons); 1317 struct bnxt_sw_rx_bd *rx_buf; 1318 unsigned int len; 1319 u8 *data, agg_bufs, cmp_type; 1320 dma_addr_t dma_addr; 1321 struct sk_buff *skb; 1322 int rc = 0; 1323 1324 rxcmp = (struct rx_cmp *) 1325 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 1326 1327 tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons); 1328 cp_cons = RING_CMP(tmp_raw_cons); 1329 rxcmp1 = (struct rx_cmp_ext *) 1330 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 1331 1332 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons)) 1333 return -EBUSY; 1334 1335 cmp_type = RX_CMP_TYPE(rxcmp); 1336 1337 prod = rxr->rx_prod; 1338 1339 if (cmp_type == CMP_TYPE_RX_L2_TPA_START_CMP) { 1340 bnxt_tpa_start(bp, rxr, (struct rx_tpa_start_cmp *)rxcmp, 1341 (struct rx_tpa_start_cmp_ext *)rxcmp1); 1342 1343 goto next_rx_no_prod; 1344 1345 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) { 1346 skb = bnxt_tpa_end(bp, bnapi, &tmp_raw_cons, 1347 (struct rx_tpa_end_cmp *)rxcmp, 1348 (struct rx_tpa_end_cmp_ext *)rxcmp1, 1349 agg_event); 1350 1351 if (unlikely(IS_ERR(skb))) 1352 return -EBUSY; 1353 1354 rc = -ENOMEM; 1355 if (likely(skb)) { 1356 skb_record_rx_queue(skb, bnapi->index); 1357 skb_mark_napi_id(skb, &bnapi->napi); 1358 if (bnxt_busy_polling(bnapi)) 1359 netif_receive_skb(skb); 1360 else 1361 napi_gro_receive(&bnapi->napi, skb); 1362 rc = 1; 1363 } 1364 goto next_rx_no_prod; 1365 } 1366 1367 cons = rxcmp->rx_cmp_opaque; 1368 rx_buf = &rxr->rx_buf_ring[cons]; 1369 data = rx_buf->data; 1370 if (unlikely(cons != rxr->rx_next_cons)) { 1371 int rc1 = bnxt_discard_rx(bp, bnapi, raw_cons, rxcmp); 1372 1373 bnxt_sched_reset(bp, rxr); 1374 return rc1; 1375 } 1376 prefetch(data); 1377 1378 agg_bufs = (le32_to_cpu(rxcmp->rx_cmp_misc_v1) & RX_CMP_AGG_BUFS) >> 1379 RX_CMP_AGG_BUFS_SHIFT; 1380 1381 if (agg_bufs) { 1382 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons)) 1383 return -EBUSY; 1384 1385 cp_cons = NEXT_CMP(cp_cons); 1386 *agg_event = true; 1387 } 1388 1389 rx_buf->data = NULL; 1390 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L2_ERRORS) { 1391 bnxt_reuse_rx_data(rxr, cons, data); 1392 if (agg_bufs) 1393 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs); 1394 1395 rc = -EIO; 1396 goto next_rx; 1397 } 1398 1399 len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT; 1400 dma_addr = dma_unmap_addr(rx_buf, mapping); 1401 1402 if (len <= bp->rx_copy_thresh) { 1403 skb = bnxt_copy_skb(bnapi, data, len, dma_addr); 1404 bnxt_reuse_rx_data(rxr, cons, data); 1405 if (!skb) { 1406 rc = -ENOMEM; 1407 goto next_rx; 1408 } 1409 } else { 1410 skb = bnxt_rx_skb(bp, rxr, cons, prod, data, dma_addr, len); 1411 if (!skb) { 1412 rc = -ENOMEM; 1413 goto next_rx; 1414 } 1415 } 1416 1417 if (agg_bufs) { 1418 skb = bnxt_rx_pages(bp, bnapi, skb, cp_cons, agg_bufs); 1419 if (!skb) { 1420 rc = -ENOMEM; 1421 goto next_rx; 1422 } 1423 } 1424 1425 if (RX_CMP_HASH_VALID(rxcmp)) { 1426 u32 hash_type = RX_CMP_HASH_TYPE(rxcmp); 1427 enum pkt_hash_types type = PKT_HASH_TYPE_L4; 1428 1429 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */ 1430 if (hash_type != 1 && hash_type != 3) 1431 type = PKT_HASH_TYPE_L3; 1432 skb_set_hash(skb, le32_to_cpu(rxcmp->rx_cmp_rss_hash), type); 1433 } 1434 1435 skb->protocol = eth_type_trans(skb, dev); 1436 1437 if ((rxcmp1->rx_cmp_flags2 & 1438 cpu_to_le32(RX_CMP_FLAGS2_META_FORMAT_VLAN)) && 1439 (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) { 1440 u32 meta_data = le32_to_cpu(rxcmp1->rx_cmp_meta_data); 1441 u16 vtag = meta_data & RX_CMP_FLAGS2_METADATA_VID_MASK; 1442 u16 vlan_proto = meta_data >> RX_CMP_FLAGS2_METADATA_TPID_SFT; 1443 1444 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag); 1445 } 1446 1447 skb_checksum_none_assert(skb); 1448 if (RX_CMP_L4_CS_OK(rxcmp1)) { 1449 if (dev->features & NETIF_F_RXCSUM) { 1450 skb->ip_summed = CHECKSUM_UNNECESSARY; 1451 skb->csum_level = RX_CMP_ENCAP(rxcmp1); 1452 } 1453 } else { 1454 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS) { 1455 if (dev->features & NETIF_F_RXCSUM) 1456 cpr->rx_l4_csum_errors++; 1457 } 1458 } 1459 1460 skb_record_rx_queue(skb, bnapi->index); 1461 skb_mark_napi_id(skb, &bnapi->napi); 1462 if (bnxt_busy_polling(bnapi)) 1463 netif_receive_skb(skb); 1464 else 1465 napi_gro_receive(&bnapi->napi, skb); 1466 rc = 1; 1467 1468 next_rx: 1469 rxr->rx_prod = NEXT_RX(prod); 1470 rxr->rx_next_cons = NEXT_RX(cons); 1471 1472 next_rx_no_prod: 1473 *raw_cons = tmp_raw_cons; 1474 1475 return rc; 1476 } 1477 1478 #define BNXT_GET_EVENT_PORT(data) \ 1479 ((data) & \ 1480 HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK) 1481 1482 static int bnxt_async_event_process(struct bnxt *bp, 1483 struct hwrm_async_event_cmpl *cmpl) 1484 { 1485 u16 event_id = le16_to_cpu(cmpl->event_id); 1486 1487 /* TODO CHIMP_FW: Define event id's for link change, error etc */ 1488 switch (event_id) { 1489 case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE: { 1490 u32 data1 = le32_to_cpu(cmpl->event_data1); 1491 struct bnxt_link_info *link_info = &bp->link_info; 1492 1493 if (BNXT_VF(bp)) 1494 goto async_event_process_exit; 1495 if (data1 & 0x20000) { 1496 u16 fw_speed = link_info->force_link_speed; 1497 u32 speed = bnxt_fw_to_ethtool_speed(fw_speed); 1498 1499 netdev_warn(bp->dev, "Link speed %d no longer supported\n", 1500 speed); 1501 } 1502 set_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT, &bp->sp_event); 1503 /* fall thru */ 1504 } 1505 case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE: 1506 set_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event); 1507 break; 1508 case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD: 1509 set_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event); 1510 break; 1511 case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED: { 1512 u32 data1 = le32_to_cpu(cmpl->event_data1); 1513 u16 port_id = BNXT_GET_EVENT_PORT(data1); 1514 1515 if (BNXT_VF(bp)) 1516 break; 1517 1518 if (bp->pf.port_id != port_id) 1519 break; 1520 1521 set_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event); 1522 break; 1523 } 1524 case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE: 1525 if (BNXT_PF(bp)) 1526 goto async_event_process_exit; 1527 set_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event); 1528 break; 1529 default: 1530 netdev_err(bp->dev, "unhandled ASYNC event (id 0x%x)\n", 1531 event_id); 1532 goto async_event_process_exit; 1533 } 1534 schedule_work(&bp->sp_task); 1535 async_event_process_exit: 1536 return 0; 1537 } 1538 1539 static int bnxt_hwrm_handler(struct bnxt *bp, struct tx_cmp *txcmp) 1540 { 1541 u16 cmpl_type = TX_CMP_TYPE(txcmp), vf_id, seq_id; 1542 struct hwrm_cmpl *h_cmpl = (struct hwrm_cmpl *)txcmp; 1543 struct hwrm_fwd_req_cmpl *fwd_req_cmpl = 1544 (struct hwrm_fwd_req_cmpl *)txcmp; 1545 1546 switch (cmpl_type) { 1547 case CMPL_BASE_TYPE_HWRM_DONE: 1548 seq_id = le16_to_cpu(h_cmpl->sequence_id); 1549 if (seq_id == bp->hwrm_intr_seq_id) 1550 bp->hwrm_intr_seq_id = HWRM_SEQ_ID_INVALID; 1551 else 1552 netdev_err(bp->dev, "Invalid hwrm seq id %d\n", seq_id); 1553 break; 1554 1555 case CMPL_BASE_TYPE_HWRM_FWD_REQ: 1556 vf_id = le16_to_cpu(fwd_req_cmpl->source_id); 1557 1558 if ((vf_id < bp->pf.first_vf_id) || 1559 (vf_id >= bp->pf.first_vf_id + bp->pf.active_vfs)) { 1560 netdev_err(bp->dev, "Msg contains invalid VF id %x\n", 1561 vf_id); 1562 return -EINVAL; 1563 } 1564 1565 set_bit(vf_id - bp->pf.first_vf_id, bp->pf.vf_event_bmap); 1566 set_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event); 1567 schedule_work(&bp->sp_task); 1568 break; 1569 1570 case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT: 1571 bnxt_async_event_process(bp, 1572 (struct hwrm_async_event_cmpl *)txcmp); 1573 1574 default: 1575 break; 1576 } 1577 1578 return 0; 1579 } 1580 1581 static irqreturn_t bnxt_msix(int irq, void *dev_instance) 1582 { 1583 struct bnxt_napi *bnapi = dev_instance; 1584 struct bnxt *bp = bnapi->bp; 1585 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 1586 u32 cons = RING_CMP(cpr->cp_raw_cons); 1587 1588 prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]); 1589 napi_schedule(&bnapi->napi); 1590 return IRQ_HANDLED; 1591 } 1592 1593 static inline int bnxt_has_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr) 1594 { 1595 u32 raw_cons = cpr->cp_raw_cons; 1596 u16 cons = RING_CMP(raw_cons); 1597 struct tx_cmp *txcmp; 1598 1599 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]; 1600 1601 return TX_CMP_VALID(txcmp, raw_cons); 1602 } 1603 1604 static irqreturn_t bnxt_inta(int irq, void *dev_instance) 1605 { 1606 struct bnxt_napi *bnapi = dev_instance; 1607 struct bnxt *bp = bnapi->bp; 1608 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 1609 u32 cons = RING_CMP(cpr->cp_raw_cons); 1610 u32 int_status; 1611 1612 prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]); 1613 1614 if (!bnxt_has_work(bp, cpr)) { 1615 int_status = readl(bp->bar0 + BNXT_CAG_REG_LEGACY_INT_STATUS); 1616 /* return if erroneous interrupt */ 1617 if (!(int_status & (0x10000 << cpr->cp_ring_struct.fw_ring_id))) 1618 return IRQ_NONE; 1619 } 1620 1621 /* disable ring IRQ */ 1622 BNXT_CP_DB_IRQ_DIS(cpr->cp_doorbell); 1623 1624 /* Return here if interrupt is shared and is disabled. */ 1625 if (unlikely(atomic_read(&bp->intr_sem) != 0)) 1626 return IRQ_HANDLED; 1627 1628 napi_schedule(&bnapi->napi); 1629 return IRQ_HANDLED; 1630 } 1631 1632 static int bnxt_poll_work(struct bnxt *bp, struct bnxt_napi *bnapi, int budget) 1633 { 1634 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 1635 u32 raw_cons = cpr->cp_raw_cons; 1636 u32 cons; 1637 int tx_pkts = 0; 1638 int rx_pkts = 0; 1639 bool rx_event = false; 1640 bool agg_event = false; 1641 struct tx_cmp *txcmp; 1642 1643 while (1) { 1644 int rc; 1645 1646 cons = RING_CMP(raw_cons); 1647 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]; 1648 1649 if (!TX_CMP_VALID(txcmp, raw_cons)) 1650 break; 1651 1652 /* The valid test of the entry must be done first before 1653 * reading any further. 1654 */ 1655 dma_rmb(); 1656 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_TX_L2_CMP) { 1657 tx_pkts++; 1658 /* return full budget so NAPI will complete. */ 1659 if (unlikely(tx_pkts > bp->tx_wake_thresh)) 1660 rx_pkts = budget; 1661 } else if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) { 1662 rc = bnxt_rx_pkt(bp, bnapi, &raw_cons, &agg_event); 1663 if (likely(rc >= 0)) 1664 rx_pkts += rc; 1665 else if (rc == -EBUSY) /* partial completion */ 1666 break; 1667 rx_event = true; 1668 } else if (unlikely((TX_CMP_TYPE(txcmp) == 1669 CMPL_BASE_TYPE_HWRM_DONE) || 1670 (TX_CMP_TYPE(txcmp) == 1671 CMPL_BASE_TYPE_HWRM_FWD_REQ) || 1672 (TX_CMP_TYPE(txcmp) == 1673 CMPL_BASE_TYPE_HWRM_ASYNC_EVENT))) { 1674 bnxt_hwrm_handler(bp, txcmp); 1675 } 1676 raw_cons = NEXT_RAW_CMP(raw_cons); 1677 1678 if (rx_pkts == budget) 1679 break; 1680 } 1681 1682 cpr->cp_raw_cons = raw_cons; 1683 /* ACK completion ring before freeing tx ring and producing new 1684 * buffers in rx/agg rings to prevent overflowing the completion 1685 * ring. 1686 */ 1687 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons); 1688 1689 if (tx_pkts) 1690 bnxt_tx_int(bp, bnapi, tx_pkts); 1691 1692 if (rx_event) { 1693 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 1694 1695 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell); 1696 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell); 1697 if (agg_event) { 1698 writel(DB_KEY_RX | rxr->rx_agg_prod, 1699 rxr->rx_agg_doorbell); 1700 writel(DB_KEY_RX | rxr->rx_agg_prod, 1701 rxr->rx_agg_doorbell); 1702 } 1703 } 1704 return rx_pkts; 1705 } 1706 1707 static int bnxt_poll_nitroa0(struct napi_struct *napi, int budget) 1708 { 1709 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi); 1710 struct bnxt *bp = bnapi->bp; 1711 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 1712 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 1713 struct tx_cmp *txcmp; 1714 struct rx_cmp_ext *rxcmp1; 1715 u32 cp_cons, tmp_raw_cons; 1716 u32 raw_cons = cpr->cp_raw_cons; 1717 u32 rx_pkts = 0; 1718 bool agg_event = false; 1719 1720 while (1) { 1721 int rc; 1722 1723 cp_cons = RING_CMP(raw_cons); 1724 txcmp = &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 1725 1726 if (!TX_CMP_VALID(txcmp, raw_cons)) 1727 break; 1728 1729 if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) { 1730 tmp_raw_cons = NEXT_RAW_CMP(raw_cons); 1731 cp_cons = RING_CMP(tmp_raw_cons); 1732 rxcmp1 = (struct rx_cmp_ext *) 1733 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 1734 1735 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons)) 1736 break; 1737 1738 /* force an error to recycle the buffer */ 1739 rxcmp1->rx_cmp_cfa_code_errors_v2 |= 1740 cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR); 1741 1742 rc = bnxt_rx_pkt(bp, bnapi, &raw_cons, &agg_event); 1743 if (likely(rc == -EIO)) 1744 rx_pkts++; 1745 else if (rc == -EBUSY) /* partial completion */ 1746 break; 1747 } else if (unlikely(TX_CMP_TYPE(txcmp) == 1748 CMPL_BASE_TYPE_HWRM_DONE)) { 1749 bnxt_hwrm_handler(bp, txcmp); 1750 } else { 1751 netdev_err(bp->dev, 1752 "Invalid completion received on special ring\n"); 1753 } 1754 raw_cons = NEXT_RAW_CMP(raw_cons); 1755 1756 if (rx_pkts == budget) 1757 break; 1758 } 1759 1760 cpr->cp_raw_cons = raw_cons; 1761 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons); 1762 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell); 1763 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell); 1764 1765 if (agg_event) { 1766 writel(DB_KEY_RX | rxr->rx_agg_prod, rxr->rx_agg_doorbell); 1767 writel(DB_KEY_RX | rxr->rx_agg_prod, rxr->rx_agg_doorbell); 1768 } 1769 1770 if (!bnxt_has_work(bp, cpr) && rx_pkts < budget) { 1771 napi_complete(napi); 1772 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons); 1773 } 1774 return rx_pkts; 1775 } 1776 1777 static int bnxt_poll(struct napi_struct *napi, int budget) 1778 { 1779 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi); 1780 struct bnxt *bp = bnapi->bp; 1781 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 1782 int work_done = 0; 1783 1784 if (!bnxt_lock_napi(bnapi)) 1785 return budget; 1786 1787 while (1) { 1788 work_done += bnxt_poll_work(bp, bnapi, budget - work_done); 1789 1790 if (work_done >= budget) 1791 break; 1792 1793 if (!bnxt_has_work(bp, cpr)) { 1794 napi_complete(napi); 1795 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons); 1796 break; 1797 } 1798 } 1799 mmiowb(); 1800 bnxt_unlock_napi(bnapi); 1801 return work_done; 1802 } 1803 1804 #ifdef CONFIG_NET_RX_BUSY_POLL 1805 static int bnxt_busy_poll(struct napi_struct *napi) 1806 { 1807 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi); 1808 struct bnxt *bp = bnapi->bp; 1809 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 1810 int rx_work, budget = 4; 1811 1812 if (atomic_read(&bp->intr_sem) != 0) 1813 return LL_FLUSH_FAILED; 1814 1815 if (!bp->link_info.link_up) 1816 return LL_FLUSH_FAILED; 1817 1818 if (!bnxt_lock_poll(bnapi)) 1819 return LL_FLUSH_BUSY; 1820 1821 rx_work = bnxt_poll_work(bp, bnapi, budget); 1822 1823 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons); 1824 1825 bnxt_unlock_poll(bnapi); 1826 return rx_work; 1827 } 1828 #endif 1829 1830 static void bnxt_free_tx_skbs(struct bnxt *bp) 1831 { 1832 int i, max_idx; 1833 struct pci_dev *pdev = bp->pdev; 1834 1835 if (!bp->tx_ring) 1836 return; 1837 1838 max_idx = bp->tx_nr_pages * TX_DESC_CNT; 1839 for (i = 0; i < bp->tx_nr_rings; i++) { 1840 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; 1841 int j; 1842 1843 for (j = 0; j < max_idx;) { 1844 struct bnxt_sw_tx_bd *tx_buf = &txr->tx_buf_ring[j]; 1845 struct sk_buff *skb = tx_buf->skb; 1846 int k, last; 1847 1848 if (!skb) { 1849 j++; 1850 continue; 1851 } 1852 1853 tx_buf->skb = NULL; 1854 1855 if (tx_buf->is_push) { 1856 dev_kfree_skb(skb); 1857 j += 2; 1858 continue; 1859 } 1860 1861 dma_unmap_single(&pdev->dev, 1862 dma_unmap_addr(tx_buf, mapping), 1863 skb_headlen(skb), 1864 PCI_DMA_TODEVICE); 1865 1866 last = tx_buf->nr_frags; 1867 j += 2; 1868 for (k = 0; k < last; k++, j++) { 1869 int ring_idx = j & bp->tx_ring_mask; 1870 skb_frag_t *frag = &skb_shinfo(skb)->frags[k]; 1871 1872 tx_buf = &txr->tx_buf_ring[ring_idx]; 1873 dma_unmap_page( 1874 &pdev->dev, 1875 dma_unmap_addr(tx_buf, mapping), 1876 skb_frag_size(frag), PCI_DMA_TODEVICE); 1877 } 1878 dev_kfree_skb(skb); 1879 } 1880 netdev_tx_reset_queue(netdev_get_tx_queue(bp->dev, i)); 1881 } 1882 } 1883 1884 static void bnxt_free_rx_skbs(struct bnxt *bp) 1885 { 1886 int i, max_idx, max_agg_idx; 1887 struct pci_dev *pdev = bp->pdev; 1888 1889 if (!bp->rx_ring) 1890 return; 1891 1892 max_idx = bp->rx_nr_pages * RX_DESC_CNT; 1893 max_agg_idx = bp->rx_agg_nr_pages * RX_DESC_CNT; 1894 for (i = 0; i < bp->rx_nr_rings; i++) { 1895 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 1896 int j; 1897 1898 if (rxr->rx_tpa) { 1899 for (j = 0; j < MAX_TPA; j++) { 1900 struct bnxt_tpa_info *tpa_info = 1901 &rxr->rx_tpa[j]; 1902 u8 *data = tpa_info->data; 1903 1904 if (!data) 1905 continue; 1906 1907 dma_unmap_single( 1908 &pdev->dev, 1909 dma_unmap_addr(tpa_info, mapping), 1910 bp->rx_buf_use_size, 1911 PCI_DMA_FROMDEVICE); 1912 1913 tpa_info->data = NULL; 1914 1915 kfree(data); 1916 } 1917 } 1918 1919 for (j = 0; j < max_idx; j++) { 1920 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[j]; 1921 u8 *data = rx_buf->data; 1922 1923 if (!data) 1924 continue; 1925 1926 dma_unmap_single(&pdev->dev, 1927 dma_unmap_addr(rx_buf, mapping), 1928 bp->rx_buf_use_size, 1929 PCI_DMA_FROMDEVICE); 1930 1931 rx_buf->data = NULL; 1932 1933 kfree(data); 1934 } 1935 1936 for (j = 0; j < max_agg_idx; j++) { 1937 struct bnxt_sw_rx_agg_bd *rx_agg_buf = 1938 &rxr->rx_agg_ring[j]; 1939 struct page *page = rx_agg_buf->page; 1940 1941 if (!page) 1942 continue; 1943 1944 dma_unmap_page(&pdev->dev, 1945 dma_unmap_addr(rx_agg_buf, mapping), 1946 BNXT_RX_PAGE_SIZE, PCI_DMA_FROMDEVICE); 1947 1948 rx_agg_buf->page = NULL; 1949 __clear_bit(j, rxr->rx_agg_bmap); 1950 1951 __free_page(page); 1952 } 1953 if (rxr->rx_page) { 1954 __free_page(rxr->rx_page); 1955 rxr->rx_page = NULL; 1956 } 1957 } 1958 } 1959 1960 static void bnxt_free_skbs(struct bnxt *bp) 1961 { 1962 bnxt_free_tx_skbs(bp); 1963 bnxt_free_rx_skbs(bp); 1964 } 1965 1966 static void bnxt_free_ring(struct bnxt *bp, struct bnxt_ring_struct *ring) 1967 { 1968 struct pci_dev *pdev = bp->pdev; 1969 int i; 1970 1971 for (i = 0; i < ring->nr_pages; i++) { 1972 if (!ring->pg_arr[i]) 1973 continue; 1974 1975 dma_free_coherent(&pdev->dev, ring->page_size, 1976 ring->pg_arr[i], ring->dma_arr[i]); 1977 1978 ring->pg_arr[i] = NULL; 1979 } 1980 if (ring->pg_tbl) { 1981 dma_free_coherent(&pdev->dev, ring->nr_pages * 8, 1982 ring->pg_tbl, ring->pg_tbl_map); 1983 ring->pg_tbl = NULL; 1984 } 1985 if (ring->vmem_size && *ring->vmem) { 1986 vfree(*ring->vmem); 1987 *ring->vmem = NULL; 1988 } 1989 } 1990 1991 static int bnxt_alloc_ring(struct bnxt *bp, struct bnxt_ring_struct *ring) 1992 { 1993 int i; 1994 struct pci_dev *pdev = bp->pdev; 1995 1996 if (ring->nr_pages > 1) { 1997 ring->pg_tbl = dma_alloc_coherent(&pdev->dev, 1998 ring->nr_pages * 8, 1999 &ring->pg_tbl_map, 2000 GFP_KERNEL); 2001 if (!ring->pg_tbl) 2002 return -ENOMEM; 2003 } 2004 2005 for (i = 0; i < ring->nr_pages; i++) { 2006 ring->pg_arr[i] = dma_alloc_coherent(&pdev->dev, 2007 ring->page_size, 2008 &ring->dma_arr[i], 2009 GFP_KERNEL); 2010 if (!ring->pg_arr[i]) 2011 return -ENOMEM; 2012 2013 if (ring->nr_pages > 1) 2014 ring->pg_tbl[i] = cpu_to_le64(ring->dma_arr[i]); 2015 } 2016 2017 if (ring->vmem_size) { 2018 *ring->vmem = vzalloc(ring->vmem_size); 2019 if (!(*ring->vmem)) 2020 return -ENOMEM; 2021 } 2022 return 0; 2023 } 2024 2025 static void bnxt_free_rx_rings(struct bnxt *bp) 2026 { 2027 int i; 2028 2029 if (!bp->rx_ring) 2030 return; 2031 2032 for (i = 0; i < bp->rx_nr_rings; i++) { 2033 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 2034 struct bnxt_ring_struct *ring; 2035 2036 kfree(rxr->rx_tpa); 2037 rxr->rx_tpa = NULL; 2038 2039 kfree(rxr->rx_agg_bmap); 2040 rxr->rx_agg_bmap = NULL; 2041 2042 ring = &rxr->rx_ring_struct; 2043 bnxt_free_ring(bp, ring); 2044 2045 ring = &rxr->rx_agg_ring_struct; 2046 bnxt_free_ring(bp, ring); 2047 } 2048 } 2049 2050 static int bnxt_alloc_rx_rings(struct bnxt *bp) 2051 { 2052 int i, rc, agg_rings = 0, tpa_rings = 0; 2053 2054 if (!bp->rx_ring) 2055 return -ENOMEM; 2056 2057 if (bp->flags & BNXT_FLAG_AGG_RINGS) 2058 agg_rings = 1; 2059 2060 if (bp->flags & BNXT_FLAG_TPA) 2061 tpa_rings = 1; 2062 2063 for (i = 0; i < bp->rx_nr_rings; i++) { 2064 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 2065 struct bnxt_ring_struct *ring; 2066 2067 ring = &rxr->rx_ring_struct; 2068 2069 rc = bnxt_alloc_ring(bp, ring); 2070 if (rc) 2071 return rc; 2072 2073 if (agg_rings) { 2074 u16 mem_size; 2075 2076 ring = &rxr->rx_agg_ring_struct; 2077 rc = bnxt_alloc_ring(bp, ring); 2078 if (rc) 2079 return rc; 2080 2081 rxr->rx_agg_bmap_size = bp->rx_agg_ring_mask + 1; 2082 mem_size = rxr->rx_agg_bmap_size / 8; 2083 rxr->rx_agg_bmap = kzalloc(mem_size, GFP_KERNEL); 2084 if (!rxr->rx_agg_bmap) 2085 return -ENOMEM; 2086 2087 if (tpa_rings) { 2088 rxr->rx_tpa = kcalloc(MAX_TPA, 2089 sizeof(struct bnxt_tpa_info), 2090 GFP_KERNEL); 2091 if (!rxr->rx_tpa) 2092 return -ENOMEM; 2093 } 2094 } 2095 } 2096 return 0; 2097 } 2098 2099 static void bnxt_free_tx_rings(struct bnxt *bp) 2100 { 2101 int i; 2102 struct pci_dev *pdev = bp->pdev; 2103 2104 if (!bp->tx_ring) 2105 return; 2106 2107 for (i = 0; i < bp->tx_nr_rings; i++) { 2108 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; 2109 struct bnxt_ring_struct *ring; 2110 2111 if (txr->tx_push) { 2112 dma_free_coherent(&pdev->dev, bp->tx_push_size, 2113 txr->tx_push, txr->tx_push_mapping); 2114 txr->tx_push = NULL; 2115 } 2116 2117 ring = &txr->tx_ring_struct; 2118 2119 bnxt_free_ring(bp, ring); 2120 } 2121 } 2122 2123 static int bnxt_alloc_tx_rings(struct bnxt *bp) 2124 { 2125 int i, j, rc; 2126 struct pci_dev *pdev = bp->pdev; 2127 2128 bp->tx_push_size = 0; 2129 if (bp->tx_push_thresh) { 2130 int push_size; 2131 2132 push_size = L1_CACHE_ALIGN(sizeof(struct tx_push_bd) + 2133 bp->tx_push_thresh); 2134 2135 if (push_size > 256) { 2136 push_size = 0; 2137 bp->tx_push_thresh = 0; 2138 } 2139 2140 bp->tx_push_size = push_size; 2141 } 2142 2143 for (i = 0, j = 0; i < bp->tx_nr_rings; i++) { 2144 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; 2145 struct bnxt_ring_struct *ring; 2146 2147 ring = &txr->tx_ring_struct; 2148 2149 rc = bnxt_alloc_ring(bp, ring); 2150 if (rc) 2151 return rc; 2152 2153 if (bp->tx_push_size) { 2154 dma_addr_t mapping; 2155 2156 /* One pre-allocated DMA buffer to backup 2157 * TX push operation 2158 */ 2159 txr->tx_push = dma_alloc_coherent(&pdev->dev, 2160 bp->tx_push_size, 2161 &txr->tx_push_mapping, 2162 GFP_KERNEL); 2163 2164 if (!txr->tx_push) 2165 return -ENOMEM; 2166 2167 mapping = txr->tx_push_mapping + 2168 sizeof(struct tx_push_bd); 2169 txr->data_mapping = cpu_to_le64(mapping); 2170 2171 memset(txr->tx_push, 0, sizeof(struct tx_push_bd)); 2172 } 2173 ring->queue_id = bp->q_info[j].queue_id; 2174 if (i % bp->tx_nr_rings_per_tc == (bp->tx_nr_rings_per_tc - 1)) 2175 j++; 2176 } 2177 return 0; 2178 } 2179 2180 static void bnxt_free_cp_rings(struct bnxt *bp) 2181 { 2182 int i; 2183 2184 if (!bp->bnapi) 2185 return; 2186 2187 for (i = 0; i < bp->cp_nr_rings; i++) { 2188 struct bnxt_napi *bnapi = bp->bnapi[i]; 2189 struct bnxt_cp_ring_info *cpr; 2190 struct bnxt_ring_struct *ring; 2191 2192 if (!bnapi) 2193 continue; 2194 2195 cpr = &bnapi->cp_ring; 2196 ring = &cpr->cp_ring_struct; 2197 2198 bnxt_free_ring(bp, ring); 2199 } 2200 } 2201 2202 static int bnxt_alloc_cp_rings(struct bnxt *bp) 2203 { 2204 int i, rc; 2205 2206 for (i = 0; i < bp->cp_nr_rings; i++) { 2207 struct bnxt_napi *bnapi = bp->bnapi[i]; 2208 struct bnxt_cp_ring_info *cpr; 2209 struct bnxt_ring_struct *ring; 2210 2211 if (!bnapi) 2212 continue; 2213 2214 cpr = &bnapi->cp_ring; 2215 ring = &cpr->cp_ring_struct; 2216 2217 rc = bnxt_alloc_ring(bp, ring); 2218 if (rc) 2219 return rc; 2220 } 2221 return 0; 2222 } 2223 2224 static void bnxt_init_ring_struct(struct bnxt *bp) 2225 { 2226 int i; 2227 2228 for (i = 0; i < bp->cp_nr_rings; i++) { 2229 struct bnxt_napi *bnapi = bp->bnapi[i]; 2230 struct bnxt_cp_ring_info *cpr; 2231 struct bnxt_rx_ring_info *rxr; 2232 struct bnxt_tx_ring_info *txr; 2233 struct bnxt_ring_struct *ring; 2234 2235 if (!bnapi) 2236 continue; 2237 2238 cpr = &bnapi->cp_ring; 2239 ring = &cpr->cp_ring_struct; 2240 ring->nr_pages = bp->cp_nr_pages; 2241 ring->page_size = HW_CMPD_RING_SIZE; 2242 ring->pg_arr = (void **)cpr->cp_desc_ring; 2243 ring->dma_arr = cpr->cp_desc_mapping; 2244 ring->vmem_size = 0; 2245 2246 rxr = bnapi->rx_ring; 2247 if (!rxr) 2248 goto skip_rx; 2249 2250 ring = &rxr->rx_ring_struct; 2251 ring->nr_pages = bp->rx_nr_pages; 2252 ring->page_size = HW_RXBD_RING_SIZE; 2253 ring->pg_arr = (void **)rxr->rx_desc_ring; 2254 ring->dma_arr = rxr->rx_desc_mapping; 2255 ring->vmem_size = SW_RXBD_RING_SIZE * bp->rx_nr_pages; 2256 ring->vmem = (void **)&rxr->rx_buf_ring; 2257 2258 ring = &rxr->rx_agg_ring_struct; 2259 ring->nr_pages = bp->rx_agg_nr_pages; 2260 ring->page_size = HW_RXBD_RING_SIZE; 2261 ring->pg_arr = (void **)rxr->rx_agg_desc_ring; 2262 ring->dma_arr = rxr->rx_agg_desc_mapping; 2263 ring->vmem_size = SW_RXBD_AGG_RING_SIZE * bp->rx_agg_nr_pages; 2264 ring->vmem = (void **)&rxr->rx_agg_ring; 2265 2266 skip_rx: 2267 txr = bnapi->tx_ring; 2268 if (!txr) 2269 continue; 2270 2271 ring = &txr->tx_ring_struct; 2272 ring->nr_pages = bp->tx_nr_pages; 2273 ring->page_size = HW_RXBD_RING_SIZE; 2274 ring->pg_arr = (void **)txr->tx_desc_ring; 2275 ring->dma_arr = txr->tx_desc_mapping; 2276 ring->vmem_size = SW_TXBD_RING_SIZE * bp->tx_nr_pages; 2277 ring->vmem = (void **)&txr->tx_buf_ring; 2278 } 2279 } 2280 2281 static void bnxt_init_rxbd_pages(struct bnxt_ring_struct *ring, u32 type) 2282 { 2283 int i; 2284 u32 prod; 2285 struct rx_bd **rx_buf_ring; 2286 2287 rx_buf_ring = (struct rx_bd **)ring->pg_arr; 2288 for (i = 0, prod = 0; i < ring->nr_pages; i++) { 2289 int j; 2290 struct rx_bd *rxbd; 2291 2292 rxbd = rx_buf_ring[i]; 2293 if (!rxbd) 2294 continue; 2295 2296 for (j = 0; j < RX_DESC_CNT; j++, rxbd++, prod++) { 2297 rxbd->rx_bd_len_flags_type = cpu_to_le32(type); 2298 rxbd->rx_bd_opaque = prod; 2299 } 2300 } 2301 } 2302 2303 static int bnxt_init_one_rx_ring(struct bnxt *bp, int ring_nr) 2304 { 2305 struct net_device *dev = bp->dev; 2306 struct bnxt_rx_ring_info *rxr; 2307 struct bnxt_ring_struct *ring; 2308 u32 prod, type; 2309 int i; 2310 2311 type = (bp->rx_buf_use_size << RX_BD_LEN_SHIFT) | 2312 RX_BD_TYPE_RX_PACKET_BD | RX_BD_FLAGS_EOP; 2313 2314 if (NET_IP_ALIGN == 2) 2315 type |= RX_BD_FLAGS_SOP; 2316 2317 rxr = &bp->rx_ring[ring_nr]; 2318 ring = &rxr->rx_ring_struct; 2319 bnxt_init_rxbd_pages(ring, type); 2320 2321 prod = rxr->rx_prod; 2322 for (i = 0; i < bp->rx_ring_size; i++) { 2323 if (bnxt_alloc_rx_data(bp, rxr, prod, GFP_KERNEL) != 0) { 2324 netdev_warn(dev, "init'ed rx ring %d with %d/%d skbs only\n", 2325 ring_nr, i, bp->rx_ring_size); 2326 break; 2327 } 2328 prod = NEXT_RX(prod); 2329 } 2330 rxr->rx_prod = prod; 2331 ring->fw_ring_id = INVALID_HW_RING_ID; 2332 2333 ring = &rxr->rx_agg_ring_struct; 2334 ring->fw_ring_id = INVALID_HW_RING_ID; 2335 2336 if (!(bp->flags & BNXT_FLAG_AGG_RINGS)) 2337 return 0; 2338 2339 type = ((u32)BNXT_RX_PAGE_SIZE << RX_BD_LEN_SHIFT) | 2340 RX_BD_TYPE_RX_AGG_BD | RX_BD_FLAGS_SOP; 2341 2342 bnxt_init_rxbd_pages(ring, type); 2343 2344 prod = rxr->rx_agg_prod; 2345 for (i = 0; i < bp->rx_agg_ring_size; i++) { 2346 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_KERNEL) != 0) { 2347 netdev_warn(dev, "init'ed rx ring %d with %d/%d pages only\n", 2348 ring_nr, i, bp->rx_ring_size); 2349 break; 2350 } 2351 prod = NEXT_RX_AGG(prod); 2352 } 2353 rxr->rx_agg_prod = prod; 2354 2355 if (bp->flags & BNXT_FLAG_TPA) { 2356 if (rxr->rx_tpa) { 2357 u8 *data; 2358 dma_addr_t mapping; 2359 2360 for (i = 0; i < MAX_TPA; i++) { 2361 data = __bnxt_alloc_rx_data(bp, &mapping, 2362 GFP_KERNEL); 2363 if (!data) 2364 return -ENOMEM; 2365 2366 rxr->rx_tpa[i].data = data; 2367 rxr->rx_tpa[i].mapping = mapping; 2368 } 2369 } else { 2370 netdev_err(bp->dev, "No resource allocated for LRO/GRO\n"); 2371 return -ENOMEM; 2372 } 2373 } 2374 2375 return 0; 2376 } 2377 2378 static int bnxt_init_rx_rings(struct bnxt *bp) 2379 { 2380 int i, rc = 0; 2381 2382 for (i = 0; i < bp->rx_nr_rings; i++) { 2383 rc = bnxt_init_one_rx_ring(bp, i); 2384 if (rc) 2385 break; 2386 } 2387 2388 return rc; 2389 } 2390 2391 static int bnxt_init_tx_rings(struct bnxt *bp) 2392 { 2393 u16 i; 2394 2395 bp->tx_wake_thresh = max_t(int, bp->tx_ring_size / 2, 2396 MAX_SKB_FRAGS + 1); 2397 2398 for (i = 0; i < bp->tx_nr_rings; i++) { 2399 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; 2400 struct bnxt_ring_struct *ring = &txr->tx_ring_struct; 2401 2402 ring->fw_ring_id = INVALID_HW_RING_ID; 2403 } 2404 2405 return 0; 2406 } 2407 2408 static void bnxt_free_ring_grps(struct bnxt *bp) 2409 { 2410 kfree(bp->grp_info); 2411 bp->grp_info = NULL; 2412 } 2413 2414 static int bnxt_init_ring_grps(struct bnxt *bp, bool irq_re_init) 2415 { 2416 int i; 2417 2418 if (irq_re_init) { 2419 bp->grp_info = kcalloc(bp->cp_nr_rings, 2420 sizeof(struct bnxt_ring_grp_info), 2421 GFP_KERNEL); 2422 if (!bp->grp_info) 2423 return -ENOMEM; 2424 } 2425 for (i = 0; i < bp->cp_nr_rings; i++) { 2426 if (irq_re_init) 2427 bp->grp_info[i].fw_stats_ctx = INVALID_HW_RING_ID; 2428 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID; 2429 bp->grp_info[i].rx_fw_ring_id = INVALID_HW_RING_ID; 2430 bp->grp_info[i].agg_fw_ring_id = INVALID_HW_RING_ID; 2431 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID; 2432 } 2433 return 0; 2434 } 2435 2436 static void bnxt_free_vnics(struct bnxt *bp) 2437 { 2438 kfree(bp->vnic_info); 2439 bp->vnic_info = NULL; 2440 bp->nr_vnics = 0; 2441 } 2442 2443 static int bnxt_alloc_vnics(struct bnxt *bp) 2444 { 2445 int num_vnics = 1; 2446 2447 #ifdef CONFIG_RFS_ACCEL 2448 if (bp->flags & BNXT_FLAG_RFS) 2449 num_vnics += bp->rx_nr_rings; 2450 #endif 2451 2452 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 2453 num_vnics++; 2454 2455 bp->vnic_info = kcalloc(num_vnics, sizeof(struct bnxt_vnic_info), 2456 GFP_KERNEL); 2457 if (!bp->vnic_info) 2458 return -ENOMEM; 2459 2460 bp->nr_vnics = num_vnics; 2461 return 0; 2462 } 2463 2464 static void bnxt_init_vnics(struct bnxt *bp) 2465 { 2466 int i; 2467 2468 for (i = 0; i < bp->nr_vnics; i++) { 2469 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 2470 2471 vnic->fw_vnic_id = INVALID_HW_RING_ID; 2472 vnic->fw_rss_cos_lb_ctx[0] = INVALID_HW_RING_ID; 2473 vnic->fw_rss_cos_lb_ctx[1] = INVALID_HW_RING_ID; 2474 vnic->fw_l2_ctx_id = INVALID_HW_RING_ID; 2475 2476 if (bp->vnic_info[i].rss_hash_key) { 2477 if (i == 0) 2478 prandom_bytes(vnic->rss_hash_key, 2479 HW_HASH_KEY_SIZE); 2480 else 2481 memcpy(vnic->rss_hash_key, 2482 bp->vnic_info[0].rss_hash_key, 2483 HW_HASH_KEY_SIZE); 2484 } 2485 } 2486 } 2487 2488 static int bnxt_calc_nr_ring_pages(u32 ring_size, int desc_per_pg) 2489 { 2490 int pages; 2491 2492 pages = ring_size / desc_per_pg; 2493 2494 if (!pages) 2495 return 1; 2496 2497 pages++; 2498 2499 while (pages & (pages - 1)) 2500 pages++; 2501 2502 return pages; 2503 } 2504 2505 static void bnxt_set_tpa_flags(struct bnxt *bp) 2506 { 2507 bp->flags &= ~BNXT_FLAG_TPA; 2508 if (bp->dev->features & NETIF_F_LRO) 2509 bp->flags |= BNXT_FLAG_LRO; 2510 if (bp->dev->features & NETIF_F_GRO) 2511 bp->flags |= BNXT_FLAG_GRO; 2512 } 2513 2514 /* bp->rx_ring_size, bp->tx_ring_size, dev->mtu, BNXT_FLAG_{G|L}RO flags must 2515 * be set on entry. 2516 */ 2517 void bnxt_set_ring_params(struct bnxt *bp) 2518 { 2519 u32 ring_size, rx_size, rx_space; 2520 u32 agg_factor = 0, agg_ring_size = 0; 2521 2522 /* 8 for CRC and VLAN */ 2523 rx_size = SKB_DATA_ALIGN(bp->dev->mtu + ETH_HLEN + NET_IP_ALIGN + 8); 2524 2525 rx_space = rx_size + NET_SKB_PAD + 2526 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 2527 2528 bp->rx_copy_thresh = BNXT_RX_COPY_THRESH; 2529 ring_size = bp->rx_ring_size; 2530 bp->rx_agg_ring_size = 0; 2531 bp->rx_agg_nr_pages = 0; 2532 2533 if (bp->flags & BNXT_FLAG_TPA) 2534 agg_factor = min_t(u32, 4, 65536 / BNXT_RX_PAGE_SIZE); 2535 2536 bp->flags &= ~BNXT_FLAG_JUMBO; 2537 if (rx_space > PAGE_SIZE) { 2538 u32 jumbo_factor; 2539 2540 bp->flags |= BNXT_FLAG_JUMBO; 2541 jumbo_factor = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT; 2542 if (jumbo_factor > agg_factor) 2543 agg_factor = jumbo_factor; 2544 } 2545 agg_ring_size = ring_size * agg_factor; 2546 2547 if (agg_ring_size) { 2548 bp->rx_agg_nr_pages = bnxt_calc_nr_ring_pages(agg_ring_size, 2549 RX_DESC_CNT); 2550 if (bp->rx_agg_nr_pages > MAX_RX_AGG_PAGES) { 2551 u32 tmp = agg_ring_size; 2552 2553 bp->rx_agg_nr_pages = MAX_RX_AGG_PAGES; 2554 agg_ring_size = MAX_RX_AGG_PAGES * RX_DESC_CNT - 1; 2555 netdev_warn(bp->dev, "rx agg ring size %d reduced to %d.\n", 2556 tmp, agg_ring_size); 2557 } 2558 bp->rx_agg_ring_size = agg_ring_size; 2559 bp->rx_agg_ring_mask = (bp->rx_agg_nr_pages * RX_DESC_CNT) - 1; 2560 rx_size = SKB_DATA_ALIGN(BNXT_RX_COPY_THRESH + NET_IP_ALIGN); 2561 rx_space = rx_size + NET_SKB_PAD + 2562 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 2563 } 2564 2565 bp->rx_buf_use_size = rx_size; 2566 bp->rx_buf_size = rx_space; 2567 2568 bp->rx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, RX_DESC_CNT); 2569 bp->rx_ring_mask = (bp->rx_nr_pages * RX_DESC_CNT) - 1; 2570 2571 ring_size = bp->tx_ring_size; 2572 bp->tx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, TX_DESC_CNT); 2573 bp->tx_ring_mask = (bp->tx_nr_pages * TX_DESC_CNT) - 1; 2574 2575 ring_size = bp->rx_ring_size * (2 + agg_factor) + bp->tx_ring_size; 2576 bp->cp_ring_size = ring_size; 2577 2578 bp->cp_nr_pages = bnxt_calc_nr_ring_pages(ring_size, CP_DESC_CNT); 2579 if (bp->cp_nr_pages > MAX_CP_PAGES) { 2580 bp->cp_nr_pages = MAX_CP_PAGES; 2581 bp->cp_ring_size = MAX_CP_PAGES * CP_DESC_CNT - 1; 2582 netdev_warn(bp->dev, "completion ring size %d reduced to %d.\n", 2583 ring_size, bp->cp_ring_size); 2584 } 2585 bp->cp_bit = bp->cp_nr_pages * CP_DESC_CNT; 2586 bp->cp_ring_mask = bp->cp_bit - 1; 2587 } 2588 2589 static void bnxt_free_vnic_attributes(struct bnxt *bp) 2590 { 2591 int i; 2592 struct bnxt_vnic_info *vnic; 2593 struct pci_dev *pdev = bp->pdev; 2594 2595 if (!bp->vnic_info) 2596 return; 2597 2598 for (i = 0; i < bp->nr_vnics; i++) { 2599 vnic = &bp->vnic_info[i]; 2600 2601 kfree(vnic->fw_grp_ids); 2602 vnic->fw_grp_ids = NULL; 2603 2604 kfree(vnic->uc_list); 2605 vnic->uc_list = NULL; 2606 2607 if (vnic->mc_list) { 2608 dma_free_coherent(&pdev->dev, vnic->mc_list_size, 2609 vnic->mc_list, vnic->mc_list_mapping); 2610 vnic->mc_list = NULL; 2611 } 2612 2613 if (vnic->rss_table) { 2614 dma_free_coherent(&pdev->dev, PAGE_SIZE, 2615 vnic->rss_table, 2616 vnic->rss_table_dma_addr); 2617 vnic->rss_table = NULL; 2618 } 2619 2620 vnic->rss_hash_key = NULL; 2621 vnic->flags = 0; 2622 } 2623 } 2624 2625 static int bnxt_alloc_vnic_attributes(struct bnxt *bp) 2626 { 2627 int i, rc = 0, size; 2628 struct bnxt_vnic_info *vnic; 2629 struct pci_dev *pdev = bp->pdev; 2630 int max_rings; 2631 2632 for (i = 0; i < bp->nr_vnics; i++) { 2633 vnic = &bp->vnic_info[i]; 2634 2635 if (vnic->flags & BNXT_VNIC_UCAST_FLAG) { 2636 int mem_size = (BNXT_MAX_UC_ADDRS - 1) * ETH_ALEN; 2637 2638 if (mem_size > 0) { 2639 vnic->uc_list = kmalloc(mem_size, GFP_KERNEL); 2640 if (!vnic->uc_list) { 2641 rc = -ENOMEM; 2642 goto out; 2643 } 2644 } 2645 } 2646 2647 if (vnic->flags & BNXT_VNIC_MCAST_FLAG) { 2648 vnic->mc_list_size = BNXT_MAX_MC_ADDRS * ETH_ALEN; 2649 vnic->mc_list = 2650 dma_alloc_coherent(&pdev->dev, 2651 vnic->mc_list_size, 2652 &vnic->mc_list_mapping, 2653 GFP_KERNEL); 2654 if (!vnic->mc_list) { 2655 rc = -ENOMEM; 2656 goto out; 2657 } 2658 } 2659 2660 if (vnic->flags & BNXT_VNIC_RSS_FLAG) 2661 max_rings = bp->rx_nr_rings; 2662 else 2663 max_rings = 1; 2664 2665 vnic->fw_grp_ids = kcalloc(max_rings, sizeof(u16), GFP_KERNEL); 2666 if (!vnic->fw_grp_ids) { 2667 rc = -ENOMEM; 2668 goto out; 2669 } 2670 2671 /* Allocate rss table and hash key */ 2672 vnic->rss_table = dma_alloc_coherent(&pdev->dev, PAGE_SIZE, 2673 &vnic->rss_table_dma_addr, 2674 GFP_KERNEL); 2675 if (!vnic->rss_table) { 2676 rc = -ENOMEM; 2677 goto out; 2678 } 2679 2680 size = L1_CACHE_ALIGN(HW_HASH_INDEX_SIZE * sizeof(u16)); 2681 2682 vnic->rss_hash_key = ((void *)vnic->rss_table) + size; 2683 vnic->rss_hash_key_dma_addr = vnic->rss_table_dma_addr + size; 2684 } 2685 return 0; 2686 2687 out: 2688 return rc; 2689 } 2690 2691 static void bnxt_free_hwrm_resources(struct bnxt *bp) 2692 { 2693 struct pci_dev *pdev = bp->pdev; 2694 2695 dma_free_coherent(&pdev->dev, PAGE_SIZE, bp->hwrm_cmd_resp_addr, 2696 bp->hwrm_cmd_resp_dma_addr); 2697 2698 bp->hwrm_cmd_resp_addr = NULL; 2699 if (bp->hwrm_dbg_resp_addr) { 2700 dma_free_coherent(&pdev->dev, HWRM_DBG_REG_BUF_SIZE, 2701 bp->hwrm_dbg_resp_addr, 2702 bp->hwrm_dbg_resp_dma_addr); 2703 2704 bp->hwrm_dbg_resp_addr = NULL; 2705 } 2706 } 2707 2708 static int bnxt_alloc_hwrm_resources(struct bnxt *bp) 2709 { 2710 struct pci_dev *pdev = bp->pdev; 2711 2712 bp->hwrm_cmd_resp_addr = dma_alloc_coherent(&pdev->dev, PAGE_SIZE, 2713 &bp->hwrm_cmd_resp_dma_addr, 2714 GFP_KERNEL); 2715 if (!bp->hwrm_cmd_resp_addr) 2716 return -ENOMEM; 2717 bp->hwrm_dbg_resp_addr = dma_alloc_coherent(&pdev->dev, 2718 HWRM_DBG_REG_BUF_SIZE, 2719 &bp->hwrm_dbg_resp_dma_addr, 2720 GFP_KERNEL); 2721 if (!bp->hwrm_dbg_resp_addr) 2722 netdev_warn(bp->dev, "fail to alloc debug register dma mem\n"); 2723 2724 return 0; 2725 } 2726 2727 static void bnxt_free_stats(struct bnxt *bp) 2728 { 2729 u32 size, i; 2730 struct pci_dev *pdev = bp->pdev; 2731 2732 if (bp->hw_rx_port_stats) { 2733 dma_free_coherent(&pdev->dev, bp->hw_port_stats_size, 2734 bp->hw_rx_port_stats, 2735 bp->hw_rx_port_stats_map); 2736 bp->hw_rx_port_stats = NULL; 2737 bp->flags &= ~BNXT_FLAG_PORT_STATS; 2738 } 2739 2740 if (!bp->bnapi) 2741 return; 2742 2743 size = sizeof(struct ctx_hw_stats); 2744 2745 for (i = 0; i < bp->cp_nr_rings; i++) { 2746 struct bnxt_napi *bnapi = bp->bnapi[i]; 2747 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 2748 2749 if (cpr->hw_stats) { 2750 dma_free_coherent(&pdev->dev, size, cpr->hw_stats, 2751 cpr->hw_stats_map); 2752 cpr->hw_stats = NULL; 2753 } 2754 } 2755 } 2756 2757 static int bnxt_alloc_stats(struct bnxt *bp) 2758 { 2759 u32 size, i; 2760 struct pci_dev *pdev = bp->pdev; 2761 2762 size = sizeof(struct ctx_hw_stats); 2763 2764 for (i = 0; i < bp->cp_nr_rings; i++) { 2765 struct bnxt_napi *bnapi = bp->bnapi[i]; 2766 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 2767 2768 cpr->hw_stats = dma_alloc_coherent(&pdev->dev, size, 2769 &cpr->hw_stats_map, 2770 GFP_KERNEL); 2771 if (!cpr->hw_stats) 2772 return -ENOMEM; 2773 2774 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID; 2775 } 2776 2777 if (BNXT_PF(bp) && bp->chip_num != CHIP_NUM_58700) { 2778 bp->hw_port_stats_size = sizeof(struct rx_port_stats) + 2779 sizeof(struct tx_port_stats) + 1024; 2780 2781 bp->hw_rx_port_stats = 2782 dma_alloc_coherent(&pdev->dev, bp->hw_port_stats_size, 2783 &bp->hw_rx_port_stats_map, 2784 GFP_KERNEL); 2785 if (!bp->hw_rx_port_stats) 2786 return -ENOMEM; 2787 2788 bp->hw_tx_port_stats = (void *)(bp->hw_rx_port_stats + 1) + 2789 512; 2790 bp->hw_tx_port_stats_map = bp->hw_rx_port_stats_map + 2791 sizeof(struct rx_port_stats) + 512; 2792 bp->flags |= BNXT_FLAG_PORT_STATS; 2793 } 2794 return 0; 2795 } 2796 2797 static void bnxt_clear_ring_indices(struct bnxt *bp) 2798 { 2799 int i; 2800 2801 if (!bp->bnapi) 2802 return; 2803 2804 for (i = 0; i < bp->cp_nr_rings; i++) { 2805 struct bnxt_napi *bnapi = bp->bnapi[i]; 2806 struct bnxt_cp_ring_info *cpr; 2807 struct bnxt_rx_ring_info *rxr; 2808 struct bnxt_tx_ring_info *txr; 2809 2810 if (!bnapi) 2811 continue; 2812 2813 cpr = &bnapi->cp_ring; 2814 cpr->cp_raw_cons = 0; 2815 2816 txr = bnapi->tx_ring; 2817 if (txr) { 2818 txr->tx_prod = 0; 2819 txr->tx_cons = 0; 2820 } 2821 2822 rxr = bnapi->rx_ring; 2823 if (rxr) { 2824 rxr->rx_prod = 0; 2825 rxr->rx_agg_prod = 0; 2826 rxr->rx_sw_agg_prod = 0; 2827 rxr->rx_next_cons = 0; 2828 } 2829 } 2830 } 2831 2832 static void bnxt_free_ntp_fltrs(struct bnxt *bp, bool irq_reinit) 2833 { 2834 #ifdef CONFIG_RFS_ACCEL 2835 int i; 2836 2837 /* Under rtnl_lock and all our NAPIs have been disabled. It's 2838 * safe to delete the hash table. 2839 */ 2840 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) { 2841 struct hlist_head *head; 2842 struct hlist_node *tmp; 2843 struct bnxt_ntuple_filter *fltr; 2844 2845 head = &bp->ntp_fltr_hash_tbl[i]; 2846 hlist_for_each_entry_safe(fltr, tmp, head, hash) { 2847 hlist_del(&fltr->hash); 2848 kfree(fltr); 2849 } 2850 } 2851 if (irq_reinit) { 2852 kfree(bp->ntp_fltr_bmap); 2853 bp->ntp_fltr_bmap = NULL; 2854 } 2855 bp->ntp_fltr_count = 0; 2856 #endif 2857 } 2858 2859 static int bnxt_alloc_ntp_fltrs(struct bnxt *bp) 2860 { 2861 #ifdef CONFIG_RFS_ACCEL 2862 int i, rc = 0; 2863 2864 if (!(bp->flags & BNXT_FLAG_RFS)) 2865 return 0; 2866 2867 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) 2868 INIT_HLIST_HEAD(&bp->ntp_fltr_hash_tbl[i]); 2869 2870 bp->ntp_fltr_count = 0; 2871 bp->ntp_fltr_bmap = kzalloc(BITS_TO_LONGS(BNXT_NTP_FLTR_MAX_FLTR), 2872 GFP_KERNEL); 2873 2874 if (!bp->ntp_fltr_bmap) 2875 rc = -ENOMEM; 2876 2877 return rc; 2878 #else 2879 return 0; 2880 #endif 2881 } 2882 2883 static void bnxt_free_mem(struct bnxt *bp, bool irq_re_init) 2884 { 2885 bnxt_free_vnic_attributes(bp); 2886 bnxt_free_tx_rings(bp); 2887 bnxt_free_rx_rings(bp); 2888 bnxt_free_cp_rings(bp); 2889 bnxt_free_ntp_fltrs(bp, irq_re_init); 2890 if (irq_re_init) { 2891 bnxt_free_stats(bp); 2892 bnxt_free_ring_grps(bp); 2893 bnxt_free_vnics(bp); 2894 kfree(bp->tx_ring); 2895 bp->tx_ring = NULL; 2896 kfree(bp->rx_ring); 2897 bp->rx_ring = NULL; 2898 kfree(bp->bnapi); 2899 bp->bnapi = NULL; 2900 } else { 2901 bnxt_clear_ring_indices(bp); 2902 } 2903 } 2904 2905 static int bnxt_alloc_mem(struct bnxt *bp, bool irq_re_init) 2906 { 2907 int i, j, rc, size, arr_size; 2908 void *bnapi; 2909 2910 if (irq_re_init) { 2911 /* Allocate bnapi mem pointer array and mem block for 2912 * all queues 2913 */ 2914 arr_size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi *) * 2915 bp->cp_nr_rings); 2916 size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi)); 2917 bnapi = kzalloc(arr_size + size * bp->cp_nr_rings, GFP_KERNEL); 2918 if (!bnapi) 2919 return -ENOMEM; 2920 2921 bp->bnapi = bnapi; 2922 bnapi += arr_size; 2923 for (i = 0; i < bp->cp_nr_rings; i++, bnapi += size) { 2924 bp->bnapi[i] = bnapi; 2925 bp->bnapi[i]->index = i; 2926 bp->bnapi[i]->bp = bp; 2927 } 2928 2929 bp->rx_ring = kcalloc(bp->rx_nr_rings, 2930 sizeof(struct bnxt_rx_ring_info), 2931 GFP_KERNEL); 2932 if (!bp->rx_ring) 2933 return -ENOMEM; 2934 2935 for (i = 0; i < bp->rx_nr_rings; i++) { 2936 bp->rx_ring[i].bnapi = bp->bnapi[i]; 2937 bp->bnapi[i]->rx_ring = &bp->rx_ring[i]; 2938 } 2939 2940 bp->tx_ring = kcalloc(bp->tx_nr_rings, 2941 sizeof(struct bnxt_tx_ring_info), 2942 GFP_KERNEL); 2943 if (!bp->tx_ring) 2944 return -ENOMEM; 2945 2946 if (bp->flags & BNXT_FLAG_SHARED_RINGS) 2947 j = 0; 2948 else 2949 j = bp->rx_nr_rings; 2950 2951 for (i = 0; i < bp->tx_nr_rings; i++, j++) { 2952 bp->tx_ring[i].bnapi = bp->bnapi[j]; 2953 bp->bnapi[j]->tx_ring = &bp->tx_ring[i]; 2954 } 2955 2956 rc = bnxt_alloc_stats(bp); 2957 if (rc) 2958 goto alloc_mem_err; 2959 2960 rc = bnxt_alloc_ntp_fltrs(bp); 2961 if (rc) 2962 goto alloc_mem_err; 2963 2964 rc = bnxt_alloc_vnics(bp); 2965 if (rc) 2966 goto alloc_mem_err; 2967 } 2968 2969 bnxt_init_ring_struct(bp); 2970 2971 rc = bnxt_alloc_rx_rings(bp); 2972 if (rc) 2973 goto alloc_mem_err; 2974 2975 rc = bnxt_alloc_tx_rings(bp); 2976 if (rc) 2977 goto alloc_mem_err; 2978 2979 rc = bnxt_alloc_cp_rings(bp); 2980 if (rc) 2981 goto alloc_mem_err; 2982 2983 bp->vnic_info[0].flags |= BNXT_VNIC_RSS_FLAG | BNXT_VNIC_MCAST_FLAG | 2984 BNXT_VNIC_UCAST_FLAG; 2985 rc = bnxt_alloc_vnic_attributes(bp); 2986 if (rc) 2987 goto alloc_mem_err; 2988 return 0; 2989 2990 alloc_mem_err: 2991 bnxt_free_mem(bp, true); 2992 return rc; 2993 } 2994 2995 void bnxt_hwrm_cmd_hdr_init(struct bnxt *bp, void *request, u16 req_type, 2996 u16 cmpl_ring, u16 target_id) 2997 { 2998 struct input *req = request; 2999 3000 req->req_type = cpu_to_le16(req_type); 3001 req->cmpl_ring = cpu_to_le16(cmpl_ring); 3002 req->target_id = cpu_to_le16(target_id); 3003 req->resp_addr = cpu_to_le64(bp->hwrm_cmd_resp_dma_addr); 3004 } 3005 3006 static int bnxt_hwrm_do_send_msg(struct bnxt *bp, void *msg, u32 msg_len, 3007 int timeout, bool silent) 3008 { 3009 int i, intr_process, rc, tmo_count; 3010 struct input *req = msg; 3011 u32 *data = msg; 3012 __le32 *resp_len, *valid; 3013 u16 cp_ring_id, len = 0; 3014 struct hwrm_err_output *resp = bp->hwrm_cmd_resp_addr; 3015 3016 req->seq_id = cpu_to_le16(bp->hwrm_cmd_seq++); 3017 memset(resp, 0, PAGE_SIZE); 3018 cp_ring_id = le16_to_cpu(req->cmpl_ring); 3019 intr_process = (cp_ring_id == INVALID_HW_RING_ID) ? 0 : 1; 3020 3021 /* Write request msg to hwrm channel */ 3022 __iowrite32_copy(bp->bar0, data, msg_len / 4); 3023 3024 for (i = msg_len; i < BNXT_HWRM_MAX_REQ_LEN; i += 4) 3025 writel(0, bp->bar0 + i); 3026 3027 /* currently supports only one outstanding message */ 3028 if (intr_process) 3029 bp->hwrm_intr_seq_id = le16_to_cpu(req->seq_id); 3030 3031 /* Ring channel doorbell */ 3032 writel(1, bp->bar0 + 0x100); 3033 3034 if (!timeout) 3035 timeout = DFLT_HWRM_CMD_TIMEOUT; 3036 3037 i = 0; 3038 tmo_count = timeout * 40; 3039 if (intr_process) { 3040 /* Wait until hwrm response cmpl interrupt is processed */ 3041 while (bp->hwrm_intr_seq_id != HWRM_SEQ_ID_INVALID && 3042 i++ < tmo_count) { 3043 usleep_range(25, 40); 3044 } 3045 3046 if (bp->hwrm_intr_seq_id != HWRM_SEQ_ID_INVALID) { 3047 netdev_err(bp->dev, "Resp cmpl intr err msg: 0x%x\n", 3048 le16_to_cpu(req->req_type)); 3049 return -1; 3050 } 3051 } else { 3052 /* Check if response len is updated */ 3053 resp_len = bp->hwrm_cmd_resp_addr + HWRM_RESP_LEN_OFFSET; 3054 for (i = 0; i < tmo_count; i++) { 3055 len = (le32_to_cpu(*resp_len) & HWRM_RESP_LEN_MASK) >> 3056 HWRM_RESP_LEN_SFT; 3057 if (len) 3058 break; 3059 usleep_range(25, 40); 3060 } 3061 3062 if (i >= tmo_count) { 3063 netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d\n", 3064 timeout, le16_to_cpu(req->req_type), 3065 le16_to_cpu(req->seq_id), len); 3066 return -1; 3067 } 3068 3069 /* Last word of resp contains valid bit */ 3070 valid = bp->hwrm_cmd_resp_addr + len - 4; 3071 for (i = 0; i < 5; i++) { 3072 if (le32_to_cpu(*valid) & HWRM_RESP_VALID_MASK) 3073 break; 3074 udelay(1); 3075 } 3076 3077 if (i >= 5) { 3078 netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d v:%d\n", 3079 timeout, le16_to_cpu(req->req_type), 3080 le16_to_cpu(req->seq_id), len, *valid); 3081 return -1; 3082 } 3083 } 3084 3085 rc = le16_to_cpu(resp->error_code); 3086 if (rc && !silent) 3087 netdev_err(bp->dev, "hwrm req_type 0x%x seq id 0x%x error 0x%x\n", 3088 le16_to_cpu(resp->req_type), 3089 le16_to_cpu(resp->seq_id), rc); 3090 return rc; 3091 } 3092 3093 int _hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout) 3094 { 3095 return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, false); 3096 } 3097 3098 int hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout) 3099 { 3100 int rc; 3101 3102 mutex_lock(&bp->hwrm_cmd_lock); 3103 rc = _hwrm_send_message(bp, msg, msg_len, timeout); 3104 mutex_unlock(&bp->hwrm_cmd_lock); 3105 return rc; 3106 } 3107 3108 int hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len, 3109 int timeout) 3110 { 3111 int rc; 3112 3113 mutex_lock(&bp->hwrm_cmd_lock); 3114 rc = bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true); 3115 mutex_unlock(&bp->hwrm_cmd_lock); 3116 return rc; 3117 } 3118 3119 static int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp) 3120 { 3121 struct hwrm_func_drv_rgtr_input req = {0}; 3122 int i; 3123 DECLARE_BITMAP(async_events_bmap, 256); 3124 u32 *events = (u32 *)async_events_bmap; 3125 3126 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1); 3127 3128 req.enables = 3129 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE | 3130 FUNC_DRV_RGTR_REQ_ENABLES_VER | 3131 FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD); 3132 3133 memset(async_events_bmap, 0, sizeof(async_events_bmap)); 3134 for (i = 0; i < ARRAY_SIZE(bnxt_async_events_arr); i++) 3135 __set_bit(bnxt_async_events_arr[i], async_events_bmap); 3136 3137 for (i = 0; i < 8; i++) 3138 req.async_event_fwd[i] |= cpu_to_le32(events[i]); 3139 3140 req.os_type = cpu_to_le16(FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX); 3141 req.ver_maj = DRV_VER_MAJ; 3142 req.ver_min = DRV_VER_MIN; 3143 req.ver_upd = DRV_VER_UPD; 3144 3145 if (BNXT_PF(bp)) { 3146 DECLARE_BITMAP(vf_req_snif_bmap, 256); 3147 u32 *data = (u32 *)vf_req_snif_bmap; 3148 3149 memset(vf_req_snif_bmap, 0, sizeof(vf_req_snif_bmap)); 3150 for (i = 0; i < ARRAY_SIZE(bnxt_vf_req_snif); i++) 3151 __set_bit(bnxt_vf_req_snif[i], vf_req_snif_bmap); 3152 3153 for (i = 0; i < 8; i++) 3154 req.vf_req_fwd[i] = cpu_to_le32(data[i]); 3155 3156 req.enables |= 3157 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD); 3158 } 3159 3160 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 3161 } 3162 3163 static int bnxt_hwrm_func_drv_unrgtr(struct bnxt *bp) 3164 { 3165 struct hwrm_func_drv_unrgtr_input req = {0}; 3166 3167 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_UNRGTR, -1, -1); 3168 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 3169 } 3170 3171 static int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, u8 tunnel_type) 3172 { 3173 u32 rc = 0; 3174 struct hwrm_tunnel_dst_port_free_input req = {0}; 3175 3176 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_FREE, -1, -1); 3177 req.tunnel_type = tunnel_type; 3178 3179 switch (tunnel_type) { 3180 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN: 3181 req.tunnel_dst_port_id = bp->vxlan_fw_dst_port_id; 3182 break; 3183 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE: 3184 req.tunnel_dst_port_id = bp->nge_fw_dst_port_id; 3185 break; 3186 default: 3187 break; 3188 } 3189 3190 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 3191 if (rc) 3192 netdev_err(bp->dev, "hwrm_tunnel_dst_port_free failed. rc:%d\n", 3193 rc); 3194 return rc; 3195 } 3196 3197 static int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, __be16 port, 3198 u8 tunnel_type) 3199 { 3200 u32 rc = 0; 3201 struct hwrm_tunnel_dst_port_alloc_input req = {0}; 3202 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr; 3203 3204 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_ALLOC, -1, -1); 3205 3206 req.tunnel_type = tunnel_type; 3207 req.tunnel_dst_port_val = port; 3208 3209 mutex_lock(&bp->hwrm_cmd_lock); 3210 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 3211 if (rc) { 3212 netdev_err(bp->dev, "hwrm_tunnel_dst_port_alloc failed. rc:%d\n", 3213 rc); 3214 goto err_out; 3215 } 3216 3217 switch (tunnel_type) { 3218 case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN: 3219 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id; 3220 break; 3221 case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE: 3222 bp->nge_fw_dst_port_id = resp->tunnel_dst_port_id; 3223 break; 3224 default: 3225 break; 3226 } 3227 3228 err_out: 3229 mutex_unlock(&bp->hwrm_cmd_lock); 3230 return rc; 3231 } 3232 3233 static int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp, u16 vnic_id) 3234 { 3235 struct hwrm_cfa_l2_set_rx_mask_input req = {0}; 3236 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 3237 3238 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_SET_RX_MASK, -1, -1); 3239 req.vnic_id = cpu_to_le32(vnic->fw_vnic_id); 3240 3241 req.num_mc_entries = cpu_to_le32(vnic->mc_list_count); 3242 req.mc_tbl_addr = cpu_to_le64(vnic->mc_list_mapping); 3243 req.mask = cpu_to_le32(vnic->rx_mask); 3244 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 3245 } 3246 3247 #ifdef CONFIG_RFS_ACCEL 3248 static int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt *bp, 3249 struct bnxt_ntuple_filter *fltr) 3250 { 3251 struct hwrm_cfa_ntuple_filter_free_input req = {0}; 3252 3253 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_FREE, -1, -1); 3254 req.ntuple_filter_id = fltr->filter_id; 3255 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 3256 } 3257 3258 #define BNXT_NTP_FLTR_FLAGS \ 3259 (CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID | \ 3260 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE | \ 3261 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR | \ 3262 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE | \ 3263 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR | \ 3264 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK | \ 3265 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR | \ 3266 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK | \ 3267 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL | \ 3268 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT | \ 3269 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK | \ 3270 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT | \ 3271 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK | \ 3272 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID) 3273 3274 static int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt *bp, 3275 struct bnxt_ntuple_filter *fltr) 3276 { 3277 int rc = 0; 3278 struct hwrm_cfa_ntuple_filter_alloc_input req = {0}; 3279 struct hwrm_cfa_ntuple_filter_alloc_output *resp = 3280 bp->hwrm_cmd_resp_addr; 3281 struct flow_keys *keys = &fltr->fkeys; 3282 struct bnxt_vnic_info *vnic = &bp->vnic_info[fltr->rxq + 1]; 3283 3284 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_ALLOC, -1, -1); 3285 req.l2_filter_id = bp->vnic_info[0].fw_l2_filter_id[fltr->l2_fltr_idx]; 3286 3287 req.enables = cpu_to_le32(BNXT_NTP_FLTR_FLAGS); 3288 3289 req.ethertype = htons(ETH_P_IP); 3290 memcpy(req.src_macaddr, fltr->src_mac_addr, ETH_ALEN); 3291 req.ip_addr_type = CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4; 3292 req.ip_protocol = keys->basic.ip_proto; 3293 3294 req.src_ipaddr[0] = keys->addrs.v4addrs.src; 3295 req.src_ipaddr_mask[0] = cpu_to_be32(0xffffffff); 3296 req.dst_ipaddr[0] = keys->addrs.v4addrs.dst; 3297 req.dst_ipaddr_mask[0] = cpu_to_be32(0xffffffff); 3298 3299 req.src_port = keys->ports.src; 3300 req.src_port_mask = cpu_to_be16(0xffff); 3301 req.dst_port = keys->ports.dst; 3302 req.dst_port_mask = cpu_to_be16(0xffff); 3303 3304 req.dst_id = cpu_to_le16(vnic->fw_vnic_id); 3305 mutex_lock(&bp->hwrm_cmd_lock); 3306 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 3307 if (!rc) 3308 fltr->filter_id = resp->ntuple_filter_id; 3309 mutex_unlock(&bp->hwrm_cmd_lock); 3310 return rc; 3311 } 3312 #endif 3313 3314 static int bnxt_hwrm_set_vnic_filter(struct bnxt *bp, u16 vnic_id, u16 idx, 3315 u8 *mac_addr) 3316 { 3317 u32 rc = 0; 3318 struct hwrm_cfa_l2_filter_alloc_input req = {0}; 3319 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr; 3320 3321 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_ALLOC, -1, -1); 3322 req.flags = cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX); 3323 if (!BNXT_CHIP_TYPE_NITRO_A0(bp)) 3324 req.flags |= 3325 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST); 3326 req.dst_id = cpu_to_le16(bp->vnic_info[vnic_id].fw_vnic_id); 3327 req.enables = 3328 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR | 3329 CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID | 3330 CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK); 3331 memcpy(req.l2_addr, mac_addr, ETH_ALEN); 3332 req.l2_addr_mask[0] = 0xff; 3333 req.l2_addr_mask[1] = 0xff; 3334 req.l2_addr_mask[2] = 0xff; 3335 req.l2_addr_mask[3] = 0xff; 3336 req.l2_addr_mask[4] = 0xff; 3337 req.l2_addr_mask[5] = 0xff; 3338 3339 mutex_lock(&bp->hwrm_cmd_lock); 3340 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 3341 if (!rc) 3342 bp->vnic_info[vnic_id].fw_l2_filter_id[idx] = 3343 resp->l2_filter_id; 3344 mutex_unlock(&bp->hwrm_cmd_lock); 3345 return rc; 3346 } 3347 3348 static int bnxt_hwrm_clear_vnic_filter(struct bnxt *bp) 3349 { 3350 u16 i, j, num_of_vnics = 1; /* only vnic 0 supported */ 3351 int rc = 0; 3352 3353 /* Any associated ntuple filters will also be cleared by firmware. */ 3354 mutex_lock(&bp->hwrm_cmd_lock); 3355 for (i = 0; i < num_of_vnics; i++) { 3356 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 3357 3358 for (j = 0; j < vnic->uc_filter_count; j++) { 3359 struct hwrm_cfa_l2_filter_free_input req = {0}; 3360 3361 bnxt_hwrm_cmd_hdr_init(bp, &req, 3362 HWRM_CFA_L2_FILTER_FREE, -1, -1); 3363 3364 req.l2_filter_id = vnic->fw_l2_filter_id[j]; 3365 3366 rc = _hwrm_send_message(bp, &req, sizeof(req), 3367 HWRM_CMD_TIMEOUT); 3368 } 3369 vnic->uc_filter_count = 0; 3370 } 3371 mutex_unlock(&bp->hwrm_cmd_lock); 3372 3373 return rc; 3374 } 3375 3376 static int bnxt_hwrm_vnic_set_tpa(struct bnxt *bp, u16 vnic_id, u32 tpa_flags) 3377 { 3378 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 3379 struct hwrm_vnic_tpa_cfg_input req = {0}; 3380 3381 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_TPA_CFG, -1, -1); 3382 3383 if (tpa_flags) { 3384 u16 mss = bp->dev->mtu - 40; 3385 u32 nsegs, n, segs = 0, flags; 3386 3387 flags = VNIC_TPA_CFG_REQ_FLAGS_TPA | 3388 VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA | 3389 VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE | 3390 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN | 3391 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ; 3392 if (tpa_flags & BNXT_FLAG_GRO) 3393 flags |= VNIC_TPA_CFG_REQ_FLAGS_GRO; 3394 3395 req.flags = cpu_to_le32(flags); 3396 3397 req.enables = 3398 cpu_to_le32(VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS | 3399 VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS | 3400 VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN); 3401 3402 /* Number of segs are log2 units, and first packet is not 3403 * included as part of this units. 3404 */ 3405 if (mss <= BNXT_RX_PAGE_SIZE) { 3406 n = BNXT_RX_PAGE_SIZE / mss; 3407 nsegs = (MAX_SKB_FRAGS - 1) * n; 3408 } else { 3409 n = mss / BNXT_RX_PAGE_SIZE; 3410 if (mss & (BNXT_RX_PAGE_SIZE - 1)) 3411 n++; 3412 nsegs = (MAX_SKB_FRAGS - n) / n; 3413 } 3414 3415 segs = ilog2(nsegs); 3416 req.max_agg_segs = cpu_to_le16(segs); 3417 req.max_aggs = cpu_to_le16(VNIC_TPA_CFG_REQ_MAX_AGGS_MAX); 3418 3419 req.min_agg_len = cpu_to_le32(512); 3420 } 3421 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id); 3422 3423 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 3424 } 3425 3426 static int bnxt_hwrm_vnic_set_rss(struct bnxt *bp, u16 vnic_id, bool set_rss) 3427 { 3428 u32 i, j, max_rings; 3429 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 3430 struct hwrm_vnic_rss_cfg_input req = {0}; 3431 3432 if (vnic->fw_rss_cos_lb_ctx[0] == INVALID_HW_RING_ID) 3433 return 0; 3434 3435 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1); 3436 if (set_rss) { 3437 req.hash_type = cpu_to_le32(bp->rss_hash_cfg); 3438 if (vnic->flags & BNXT_VNIC_RSS_FLAG) { 3439 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 3440 max_rings = bp->rx_nr_rings - 1; 3441 else 3442 max_rings = bp->rx_nr_rings; 3443 } else { 3444 max_rings = 1; 3445 } 3446 3447 /* Fill the RSS indirection table with ring group ids */ 3448 for (i = 0, j = 0; i < HW_HASH_INDEX_SIZE; i++, j++) { 3449 if (j == max_rings) 3450 j = 0; 3451 vnic->rss_table[i] = cpu_to_le16(vnic->fw_grp_ids[j]); 3452 } 3453 3454 req.ring_grp_tbl_addr = cpu_to_le64(vnic->rss_table_dma_addr); 3455 req.hash_key_tbl_addr = 3456 cpu_to_le64(vnic->rss_hash_key_dma_addr); 3457 } 3458 req.rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]); 3459 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 3460 } 3461 3462 static int bnxt_hwrm_vnic_set_hds(struct bnxt *bp, u16 vnic_id) 3463 { 3464 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 3465 struct hwrm_vnic_plcmodes_cfg_input req = {0}; 3466 3467 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_PLCMODES_CFG, -1, -1); 3468 req.flags = cpu_to_le32(VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT | 3469 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 | 3470 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6); 3471 req.enables = 3472 cpu_to_le32(VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID | 3473 VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID); 3474 /* thresholds not implemented in firmware yet */ 3475 req.jumbo_thresh = cpu_to_le16(bp->rx_copy_thresh); 3476 req.hds_threshold = cpu_to_le16(bp->rx_copy_thresh); 3477 req.vnic_id = cpu_to_le32(vnic->fw_vnic_id); 3478 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 3479 } 3480 3481 static void bnxt_hwrm_vnic_ctx_free_one(struct bnxt *bp, u16 vnic_id, 3482 u16 ctx_idx) 3483 { 3484 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {0}; 3485 3486 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, -1, -1); 3487 req.rss_cos_lb_ctx_id = 3488 cpu_to_le16(bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx]); 3489 3490 hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 3491 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] = INVALID_HW_RING_ID; 3492 } 3493 3494 static void bnxt_hwrm_vnic_ctx_free(struct bnxt *bp) 3495 { 3496 int i, j; 3497 3498 for (i = 0; i < bp->nr_vnics; i++) { 3499 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 3500 3501 for (j = 0; j < BNXT_MAX_CTX_PER_VNIC; j++) { 3502 if (vnic->fw_rss_cos_lb_ctx[j] != INVALID_HW_RING_ID) 3503 bnxt_hwrm_vnic_ctx_free_one(bp, i, j); 3504 } 3505 } 3506 bp->rsscos_nr_ctxs = 0; 3507 } 3508 3509 static int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, u16 vnic_id, u16 ctx_idx) 3510 { 3511 int rc; 3512 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {0}; 3513 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp = 3514 bp->hwrm_cmd_resp_addr; 3515 3516 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, -1, 3517 -1); 3518 3519 mutex_lock(&bp->hwrm_cmd_lock); 3520 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 3521 if (!rc) 3522 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] = 3523 le16_to_cpu(resp->rss_cos_lb_ctx_id); 3524 mutex_unlock(&bp->hwrm_cmd_lock); 3525 3526 return rc; 3527 } 3528 3529 static int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id) 3530 { 3531 unsigned int ring = 0, grp_idx; 3532 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 3533 struct hwrm_vnic_cfg_input req = {0}; 3534 u16 def_vlan = 0; 3535 3536 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_CFG, -1, -1); 3537 3538 req.enables = cpu_to_le32(VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP); 3539 /* Only RSS support for now TBD: COS & LB */ 3540 if (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID) { 3541 req.rss_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]); 3542 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE | 3543 VNIC_CFG_REQ_ENABLES_MRU); 3544 } else { 3545 req.rss_rule = cpu_to_le16(0xffff); 3546 } 3547 3548 if (BNXT_CHIP_TYPE_NITRO_A0(bp) && 3549 (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID)) { 3550 req.cos_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[1]); 3551 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_COS_RULE); 3552 } else { 3553 req.cos_rule = cpu_to_le16(0xffff); 3554 } 3555 3556 if (vnic->flags & BNXT_VNIC_RSS_FLAG) 3557 ring = 0; 3558 else if (vnic->flags & BNXT_VNIC_RFS_FLAG) 3559 ring = vnic_id - 1; 3560 else if ((vnic_id == 1) && BNXT_CHIP_TYPE_NITRO_A0(bp)) 3561 ring = bp->rx_nr_rings - 1; 3562 3563 grp_idx = bp->rx_ring[ring].bnapi->index; 3564 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id); 3565 req.dflt_ring_grp = cpu_to_le16(bp->grp_info[grp_idx].fw_grp_id); 3566 3567 req.lb_rule = cpu_to_le16(0xffff); 3568 req.mru = cpu_to_le16(bp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + 3569 VLAN_HLEN); 3570 3571 #ifdef CONFIG_BNXT_SRIOV 3572 if (BNXT_VF(bp)) 3573 def_vlan = bp->vf.vlan; 3574 #endif 3575 if ((bp->flags & BNXT_FLAG_STRIP_VLAN) || def_vlan) 3576 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE); 3577 3578 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 3579 } 3580 3581 static int bnxt_hwrm_vnic_free_one(struct bnxt *bp, u16 vnic_id) 3582 { 3583 u32 rc = 0; 3584 3585 if (bp->vnic_info[vnic_id].fw_vnic_id != INVALID_HW_RING_ID) { 3586 struct hwrm_vnic_free_input req = {0}; 3587 3588 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_FREE, -1, -1); 3589 req.vnic_id = 3590 cpu_to_le32(bp->vnic_info[vnic_id].fw_vnic_id); 3591 3592 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 3593 if (rc) 3594 return rc; 3595 bp->vnic_info[vnic_id].fw_vnic_id = INVALID_HW_RING_ID; 3596 } 3597 return rc; 3598 } 3599 3600 static void bnxt_hwrm_vnic_free(struct bnxt *bp) 3601 { 3602 u16 i; 3603 3604 for (i = 0; i < bp->nr_vnics; i++) 3605 bnxt_hwrm_vnic_free_one(bp, i); 3606 } 3607 3608 static int bnxt_hwrm_vnic_alloc(struct bnxt *bp, u16 vnic_id, 3609 unsigned int start_rx_ring_idx, 3610 unsigned int nr_rings) 3611 { 3612 int rc = 0; 3613 unsigned int i, j, grp_idx, end_idx = start_rx_ring_idx + nr_rings; 3614 struct hwrm_vnic_alloc_input req = {0}; 3615 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr; 3616 3617 /* map ring groups to this vnic */ 3618 for (i = start_rx_ring_idx, j = 0; i < end_idx; i++, j++) { 3619 grp_idx = bp->rx_ring[i].bnapi->index; 3620 if (bp->grp_info[grp_idx].fw_grp_id == INVALID_HW_RING_ID) { 3621 netdev_err(bp->dev, "Not enough ring groups avail:%x req:%x\n", 3622 j, nr_rings); 3623 break; 3624 } 3625 bp->vnic_info[vnic_id].fw_grp_ids[j] = 3626 bp->grp_info[grp_idx].fw_grp_id; 3627 } 3628 3629 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[0] = INVALID_HW_RING_ID; 3630 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[1] = INVALID_HW_RING_ID; 3631 if (vnic_id == 0) 3632 req.flags = cpu_to_le32(VNIC_ALLOC_REQ_FLAGS_DEFAULT); 3633 3634 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_ALLOC, -1, -1); 3635 3636 mutex_lock(&bp->hwrm_cmd_lock); 3637 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 3638 if (!rc) 3639 bp->vnic_info[vnic_id].fw_vnic_id = le32_to_cpu(resp->vnic_id); 3640 mutex_unlock(&bp->hwrm_cmd_lock); 3641 return rc; 3642 } 3643 3644 static int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp) 3645 { 3646 u16 i; 3647 u32 rc = 0; 3648 3649 mutex_lock(&bp->hwrm_cmd_lock); 3650 for (i = 0; i < bp->rx_nr_rings; i++) { 3651 struct hwrm_ring_grp_alloc_input req = {0}; 3652 struct hwrm_ring_grp_alloc_output *resp = 3653 bp->hwrm_cmd_resp_addr; 3654 unsigned int grp_idx = bp->rx_ring[i].bnapi->index; 3655 3656 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_ALLOC, -1, -1); 3657 3658 req.cr = cpu_to_le16(bp->grp_info[grp_idx].cp_fw_ring_id); 3659 req.rr = cpu_to_le16(bp->grp_info[grp_idx].rx_fw_ring_id); 3660 req.ar = cpu_to_le16(bp->grp_info[grp_idx].agg_fw_ring_id); 3661 req.sc = cpu_to_le16(bp->grp_info[grp_idx].fw_stats_ctx); 3662 3663 rc = _hwrm_send_message(bp, &req, sizeof(req), 3664 HWRM_CMD_TIMEOUT); 3665 if (rc) 3666 break; 3667 3668 bp->grp_info[grp_idx].fw_grp_id = 3669 le32_to_cpu(resp->ring_group_id); 3670 } 3671 mutex_unlock(&bp->hwrm_cmd_lock); 3672 return rc; 3673 } 3674 3675 static int bnxt_hwrm_ring_grp_free(struct bnxt *bp) 3676 { 3677 u16 i; 3678 u32 rc = 0; 3679 struct hwrm_ring_grp_free_input req = {0}; 3680 3681 if (!bp->grp_info) 3682 return 0; 3683 3684 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_FREE, -1, -1); 3685 3686 mutex_lock(&bp->hwrm_cmd_lock); 3687 for (i = 0; i < bp->cp_nr_rings; i++) { 3688 if (bp->grp_info[i].fw_grp_id == INVALID_HW_RING_ID) 3689 continue; 3690 req.ring_group_id = 3691 cpu_to_le32(bp->grp_info[i].fw_grp_id); 3692 3693 rc = _hwrm_send_message(bp, &req, sizeof(req), 3694 HWRM_CMD_TIMEOUT); 3695 if (rc) 3696 break; 3697 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID; 3698 } 3699 mutex_unlock(&bp->hwrm_cmd_lock); 3700 return rc; 3701 } 3702 3703 static int hwrm_ring_alloc_send_msg(struct bnxt *bp, 3704 struct bnxt_ring_struct *ring, 3705 u32 ring_type, u32 map_index, 3706 u32 stats_ctx_id) 3707 { 3708 int rc = 0, err = 0; 3709 struct hwrm_ring_alloc_input req = {0}; 3710 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr; 3711 u16 ring_id; 3712 3713 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_ALLOC, -1, -1); 3714 3715 req.enables = 0; 3716 if (ring->nr_pages > 1) { 3717 req.page_tbl_addr = cpu_to_le64(ring->pg_tbl_map); 3718 /* Page size is in log2 units */ 3719 req.page_size = BNXT_PAGE_SHIFT; 3720 req.page_tbl_depth = 1; 3721 } else { 3722 req.page_tbl_addr = cpu_to_le64(ring->dma_arr[0]); 3723 } 3724 req.fbo = 0; 3725 /* Association of ring index with doorbell index and MSIX number */ 3726 req.logical_id = cpu_to_le16(map_index); 3727 3728 switch (ring_type) { 3729 case HWRM_RING_ALLOC_TX: 3730 req.ring_type = RING_ALLOC_REQ_RING_TYPE_TX; 3731 /* Association of transmit ring with completion ring */ 3732 req.cmpl_ring_id = 3733 cpu_to_le16(bp->grp_info[map_index].cp_fw_ring_id); 3734 req.length = cpu_to_le32(bp->tx_ring_mask + 1); 3735 req.stat_ctx_id = cpu_to_le32(stats_ctx_id); 3736 req.queue_id = cpu_to_le16(ring->queue_id); 3737 break; 3738 case HWRM_RING_ALLOC_RX: 3739 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX; 3740 req.length = cpu_to_le32(bp->rx_ring_mask + 1); 3741 break; 3742 case HWRM_RING_ALLOC_AGG: 3743 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX; 3744 req.length = cpu_to_le32(bp->rx_agg_ring_mask + 1); 3745 break; 3746 case HWRM_RING_ALLOC_CMPL: 3747 req.ring_type = RING_ALLOC_REQ_RING_TYPE_CMPL; 3748 req.length = cpu_to_le32(bp->cp_ring_mask + 1); 3749 if (bp->flags & BNXT_FLAG_USING_MSIX) 3750 req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX; 3751 break; 3752 default: 3753 netdev_err(bp->dev, "hwrm alloc invalid ring type %d\n", 3754 ring_type); 3755 return -1; 3756 } 3757 3758 mutex_lock(&bp->hwrm_cmd_lock); 3759 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 3760 err = le16_to_cpu(resp->error_code); 3761 ring_id = le16_to_cpu(resp->ring_id); 3762 mutex_unlock(&bp->hwrm_cmd_lock); 3763 3764 if (rc || err) { 3765 switch (ring_type) { 3766 case RING_FREE_REQ_RING_TYPE_CMPL: 3767 netdev_err(bp->dev, "hwrm_ring_alloc cp failed. rc:%x err:%x\n", 3768 rc, err); 3769 return -1; 3770 3771 case RING_FREE_REQ_RING_TYPE_RX: 3772 netdev_err(bp->dev, "hwrm_ring_alloc rx failed. rc:%x err:%x\n", 3773 rc, err); 3774 return -1; 3775 3776 case RING_FREE_REQ_RING_TYPE_TX: 3777 netdev_err(bp->dev, "hwrm_ring_alloc tx failed. rc:%x err:%x\n", 3778 rc, err); 3779 return -1; 3780 3781 default: 3782 netdev_err(bp->dev, "Invalid ring\n"); 3783 return -1; 3784 } 3785 } 3786 ring->fw_ring_id = ring_id; 3787 return rc; 3788 } 3789 3790 static int bnxt_hwrm_ring_alloc(struct bnxt *bp) 3791 { 3792 int i, rc = 0; 3793 3794 for (i = 0; i < bp->cp_nr_rings; i++) { 3795 struct bnxt_napi *bnapi = bp->bnapi[i]; 3796 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 3797 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct; 3798 3799 cpr->cp_doorbell = bp->bar1 + i * 0x80; 3800 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_CMPL, i, 3801 INVALID_STATS_CTX_ID); 3802 if (rc) 3803 goto err_out; 3804 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons); 3805 bp->grp_info[i].cp_fw_ring_id = ring->fw_ring_id; 3806 } 3807 3808 for (i = 0; i < bp->tx_nr_rings; i++) { 3809 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; 3810 struct bnxt_ring_struct *ring = &txr->tx_ring_struct; 3811 u32 map_idx = txr->bnapi->index; 3812 u16 fw_stats_ctx = bp->grp_info[map_idx].fw_stats_ctx; 3813 3814 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_TX, 3815 map_idx, fw_stats_ctx); 3816 if (rc) 3817 goto err_out; 3818 txr->tx_doorbell = bp->bar1 + map_idx * 0x80; 3819 } 3820 3821 for (i = 0; i < bp->rx_nr_rings; i++) { 3822 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 3823 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct; 3824 u32 map_idx = rxr->bnapi->index; 3825 3826 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_RX, 3827 map_idx, INVALID_STATS_CTX_ID); 3828 if (rc) 3829 goto err_out; 3830 rxr->rx_doorbell = bp->bar1 + map_idx * 0x80; 3831 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell); 3832 bp->grp_info[map_idx].rx_fw_ring_id = ring->fw_ring_id; 3833 } 3834 3835 if (bp->flags & BNXT_FLAG_AGG_RINGS) { 3836 for (i = 0; i < bp->rx_nr_rings; i++) { 3837 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 3838 struct bnxt_ring_struct *ring = 3839 &rxr->rx_agg_ring_struct; 3840 u32 grp_idx = rxr->bnapi->index; 3841 u32 map_idx = grp_idx + bp->rx_nr_rings; 3842 3843 rc = hwrm_ring_alloc_send_msg(bp, ring, 3844 HWRM_RING_ALLOC_AGG, 3845 map_idx, 3846 INVALID_STATS_CTX_ID); 3847 if (rc) 3848 goto err_out; 3849 3850 rxr->rx_agg_doorbell = bp->bar1 + map_idx * 0x80; 3851 writel(DB_KEY_RX | rxr->rx_agg_prod, 3852 rxr->rx_agg_doorbell); 3853 bp->grp_info[grp_idx].agg_fw_ring_id = ring->fw_ring_id; 3854 } 3855 } 3856 err_out: 3857 return rc; 3858 } 3859 3860 static int hwrm_ring_free_send_msg(struct bnxt *bp, 3861 struct bnxt_ring_struct *ring, 3862 u32 ring_type, int cmpl_ring_id) 3863 { 3864 int rc; 3865 struct hwrm_ring_free_input req = {0}; 3866 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr; 3867 u16 error_code; 3868 3869 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_FREE, cmpl_ring_id, -1); 3870 req.ring_type = ring_type; 3871 req.ring_id = cpu_to_le16(ring->fw_ring_id); 3872 3873 mutex_lock(&bp->hwrm_cmd_lock); 3874 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 3875 error_code = le16_to_cpu(resp->error_code); 3876 mutex_unlock(&bp->hwrm_cmd_lock); 3877 3878 if (rc || error_code) { 3879 switch (ring_type) { 3880 case RING_FREE_REQ_RING_TYPE_CMPL: 3881 netdev_err(bp->dev, "hwrm_ring_free cp failed. rc:%d\n", 3882 rc); 3883 return rc; 3884 case RING_FREE_REQ_RING_TYPE_RX: 3885 netdev_err(bp->dev, "hwrm_ring_free rx failed. rc:%d\n", 3886 rc); 3887 return rc; 3888 case RING_FREE_REQ_RING_TYPE_TX: 3889 netdev_err(bp->dev, "hwrm_ring_free tx failed. rc:%d\n", 3890 rc); 3891 return rc; 3892 default: 3893 netdev_err(bp->dev, "Invalid ring\n"); 3894 return -1; 3895 } 3896 } 3897 return 0; 3898 } 3899 3900 static void bnxt_hwrm_ring_free(struct bnxt *bp, bool close_path) 3901 { 3902 int i; 3903 3904 if (!bp->bnapi) 3905 return; 3906 3907 for (i = 0; i < bp->tx_nr_rings; i++) { 3908 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; 3909 struct bnxt_ring_struct *ring = &txr->tx_ring_struct; 3910 u32 grp_idx = txr->bnapi->index; 3911 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id; 3912 3913 if (ring->fw_ring_id != INVALID_HW_RING_ID) { 3914 hwrm_ring_free_send_msg(bp, ring, 3915 RING_FREE_REQ_RING_TYPE_TX, 3916 close_path ? cmpl_ring_id : 3917 INVALID_HW_RING_ID); 3918 ring->fw_ring_id = INVALID_HW_RING_ID; 3919 } 3920 } 3921 3922 for (i = 0; i < bp->rx_nr_rings; i++) { 3923 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 3924 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct; 3925 u32 grp_idx = rxr->bnapi->index; 3926 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id; 3927 3928 if (ring->fw_ring_id != INVALID_HW_RING_ID) { 3929 hwrm_ring_free_send_msg(bp, ring, 3930 RING_FREE_REQ_RING_TYPE_RX, 3931 close_path ? cmpl_ring_id : 3932 INVALID_HW_RING_ID); 3933 ring->fw_ring_id = INVALID_HW_RING_ID; 3934 bp->grp_info[grp_idx].rx_fw_ring_id = 3935 INVALID_HW_RING_ID; 3936 } 3937 } 3938 3939 for (i = 0; i < bp->rx_nr_rings; i++) { 3940 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 3941 struct bnxt_ring_struct *ring = &rxr->rx_agg_ring_struct; 3942 u32 grp_idx = rxr->bnapi->index; 3943 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id; 3944 3945 if (ring->fw_ring_id != INVALID_HW_RING_ID) { 3946 hwrm_ring_free_send_msg(bp, ring, 3947 RING_FREE_REQ_RING_TYPE_RX, 3948 close_path ? cmpl_ring_id : 3949 INVALID_HW_RING_ID); 3950 ring->fw_ring_id = INVALID_HW_RING_ID; 3951 bp->grp_info[grp_idx].agg_fw_ring_id = 3952 INVALID_HW_RING_ID; 3953 } 3954 } 3955 3956 for (i = 0; i < bp->cp_nr_rings; i++) { 3957 struct bnxt_napi *bnapi = bp->bnapi[i]; 3958 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 3959 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct; 3960 3961 if (ring->fw_ring_id != INVALID_HW_RING_ID) { 3962 hwrm_ring_free_send_msg(bp, ring, 3963 RING_FREE_REQ_RING_TYPE_CMPL, 3964 INVALID_HW_RING_ID); 3965 ring->fw_ring_id = INVALID_HW_RING_ID; 3966 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID; 3967 } 3968 } 3969 } 3970 3971 static void bnxt_hwrm_set_coal_params(struct bnxt *bp, u32 max_bufs, 3972 u32 buf_tmrs, u16 flags, 3973 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req) 3974 { 3975 req->flags = cpu_to_le16(flags); 3976 req->num_cmpl_dma_aggr = cpu_to_le16((u16)max_bufs); 3977 req->num_cmpl_dma_aggr_during_int = cpu_to_le16(max_bufs >> 16); 3978 req->cmpl_aggr_dma_tmr = cpu_to_le16((u16)buf_tmrs); 3979 req->cmpl_aggr_dma_tmr_during_int = cpu_to_le16(buf_tmrs >> 16); 3980 /* Minimum time between 2 interrupts set to buf_tmr x 2 */ 3981 req->int_lat_tmr_min = cpu_to_le16((u16)buf_tmrs * 2); 3982 req->int_lat_tmr_max = cpu_to_le16((u16)buf_tmrs * 4); 3983 req->num_cmpl_aggr_int = cpu_to_le16((u16)max_bufs * 4); 3984 } 3985 3986 int bnxt_hwrm_set_coal(struct bnxt *bp) 3987 { 3988 int i, rc = 0; 3989 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx = {0}, 3990 req_tx = {0}, *req; 3991 u16 max_buf, max_buf_irq; 3992 u16 buf_tmr, buf_tmr_irq; 3993 u32 flags; 3994 3995 bnxt_hwrm_cmd_hdr_init(bp, &req_rx, 3996 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1); 3997 bnxt_hwrm_cmd_hdr_init(bp, &req_tx, 3998 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1); 3999 4000 /* Each rx completion (2 records) should be DMAed immediately. 4001 * DMA 1/4 of the completion buffers at a time. 4002 */ 4003 max_buf = min_t(u16, bp->rx_coal_bufs / 4, 2); 4004 /* max_buf must not be zero */ 4005 max_buf = clamp_t(u16, max_buf, 1, 63); 4006 max_buf_irq = clamp_t(u16, bp->rx_coal_bufs_irq, 1, 63); 4007 buf_tmr = BNXT_USEC_TO_COAL_TIMER(bp->rx_coal_ticks); 4008 /* buf timer set to 1/4 of interrupt timer */ 4009 buf_tmr = max_t(u16, buf_tmr / 4, 1); 4010 buf_tmr_irq = BNXT_USEC_TO_COAL_TIMER(bp->rx_coal_ticks_irq); 4011 buf_tmr_irq = max_t(u16, buf_tmr_irq, 1); 4012 4013 flags = RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET; 4014 4015 /* RING_IDLE generates more IRQs for lower latency. Enable it only 4016 * if coal_ticks is less than 25 us. 4017 */ 4018 if (bp->rx_coal_ticks < 25) 4019 flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE; 4020 4021 bnxt_hwrm_set_coal_params(bp, max_buf_irq << 16 | max_buf, 4022 buf_tmr_irq << 16 | buf_tmr, flags, &req_rx); 4023 4024 /* max_buf must not be zero */ 4025 max_buf = clamp_t(u16, bp->tx_coal_bufs, 1, 63); 4026 max_buf_irq = clamp_t(u16, bp->tx_coal_bufs_irq, 1, 63); 4027 buf_tmr = BNXT_USEC_TO_COAL_TIMER(bp->tx_coal_ticks); 4028 /* buf timer set to 1/4 of interrupt timer */ 4029 buf_tmr = max_t(u16, buf_tmr / 4, 1); 4030 buf_tmr_irq = BNXT_USEC_TO_COAL_TIMER(bp->tx_coal_ticks_irq); 4031 buf_tmr_irq = max_t(u16, buf_tmr_irq, 1); 4032 4033 flags = RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET; 4034 bnxt_hwrm_set_coal_params(bp, max_buf_irq << 16 | max_buf, 4035 buf_tmr_irq << 16 | buf_tmr, flags, &req_tx); 4036 4037 mutex_lock(&bp->hwrm_cmd_lock); 4038 for (i = 0; i < bp->cp_nr_rings; i++) { 4039 struct bnxt_napi *bnapi = bp->bnapi[i]; 4040 4041 req = &req_rx; 4042 if (!bnapi->rx_ring) 4043 req = &req_tx; 4044 req->ring_id = cpu_to_le16(bp->grp_info[i].cp_fw_ring_id); 4045 4046 rc = _hwrm_send_message(bp, req, sizeof(*req), 4047 HWRM_CMD_TIMEOUT); 4048 if (rc) 4049 break; 4050 } 4051 mutex_unlock(&bp->hwrm_cmd_lock); 4052 return rc; 4053 } 4054 4055 static int bnxt_hwrm_stat_ctx_free(struct bnxt *bp) 4056 { 4057 int rc = 0, i; 4058 struct hwrm_stat_ctx_free_input req = {0}; 4059 4060 if (!bp->bnapi) 4061 return 0; 4062 4063 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 4064 return 0; 4065 4066 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_FREE, -1, -1); 4067 4068 mutex_lock(&bp->hwrm_cmd_lock); 4069 for (i = 0; i < bp->cp_nr_rings; i++) { 4070 struct bnxt_napi *bnapi = bp->bnapi[i]; 4071 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 4072 4073 if (cpr->hw_stats_ctx_id != INVALID_STATS_CTX_ID) { 4074 req.stat_ctx_id = cpu_to_le32(cpr->hw_stats_ctx_id); 4075 4076 rc = _hwrm_send_message(bp, &req, sizeof(req), 4077 HWRM_CMD_TIMEOUT); 4078 if (rc) 4079 break; 4080 4081 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID; 4082 } 4083 } 4084 mutex_unlock(&bp->hwrm_cmd_lock); 4085 return rc; 4086 } 4087 4088 static int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp) 4089 { 4090 int rc = 0, i; 4091 struct hwrm_stat_ctx_alloc_input req = {0}; 4092 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr; 4093 4094 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 4095 return 0; 4096 4097 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_ALLOC, -1, -1); 4098 4099 req.update_period_ms = cpu_to_le32(bp->stats_coal_ticks / 1000); 4100 4101 mutex_lock(&bp->hwrm_cmd_lock); 4102 for (i = 0; i < bp->cp_nr_rings; i++) { 4103 struct bnxt_napi *bnapi = bp->bnapi[i]; 4104 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 4105 4106 req.stats_dma_addr = cpu_to_le64(cpr->hw_stats_map); 4107 4108 rc = _hwrm_send_message(bp, &req, sizeof(req), 4109 HWRM_CMD_TIMEOUT); 4110 if (rc) 4111 break; 4112 4113 cpr->hw_stats_ctx_id = le32_to_cpu(resp->stat_ctx_id); 4114 4115 bp->grp_info[i].fw_stats_ctx = cpr->hw_stats_ctx_id; 4116 } 4117 mutex_unlock(&bp->hwrm_cmd_lock); 4118 return 0; 4119 } 4120 4121 static int bnxt_hwrm_func_qcfg(struct bnxt *bp) 4122 { 4123 struct hwrm_func_qcfg_input req = {0}; 4124 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr; 4125 int rc; 4126 4127 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1); 4128 req.fid = cpu_to_le16(0xffff); 4129 mutex_lock(&bp->hwrm_cmd_lock); 4130 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4131 if (rc) 4132 goto func_qcfg_exit; 4133 4134 #ifdef CONFIG_BNXT_SRIOV 4135 if (BNXT_VF(bp)) { 4136 struct bnxt_vf_info *vf = &bp->vf; 4137 4138 vf->vlan = le16_to_cpu(resp->vlan) & VLAN_VID_MASK; 4139 } 4140 #endif 4141 switch (resp->port_partition_type) { 4142 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0: 4143 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5: 4144 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0: 4145 bp->port_partition_type = resp->port_partition_type; 4146 break; 4147 } 4148 4149 func_qcfg_exit: 4150 mutex_unlock(&bp->hwrm_cmd_lock); 4151 return rc; 4152 } 4153 4154 int bnxt_hwrm_func_qcaps(struct bnxt *bp) 4155 { 4156 int rc = 0; 4157 struct hwrm_func_qcaps_input req = {0}; 4158 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr; 4159 4160 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCAPS, -1, -1); 4161 req.fid = cpu_to_le16(0xffff); 4162 4163 mutex_lock(&bp->hwrm_cmd_lock); 4164 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4165 if (rc) 4166 goto hwrm_func_qcaps_exit; 4167 4168 bp->tx_push_thresh = 0; 4169 if (resp->flags & 4170 cpu_to_le32(FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED)) 4171 bp->tx_push_thresh = BNXT_TX_PUSH_THRESH; 4172 4173 if (BNXT_PF(bp)) { 4174 struct bnxt_pf_info *pf = &bp->pf; 4175 4176 pf->fw_fid = le16_to_cpu(resp->fid); 4177 pf->port_id = le16_to_cpu(resp->port_id); 4178 bp->dev->dev_port = pf->port_id; 4179 memcpy(pf->mac_addr, resp->mac_address, ETH_ALEN); 4180 memcpy(bp->dev->dev_addr, pf->mac_addr, ETH_ALEN); 4181 pf->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx); 4182 pf->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings); 4183 pf->max_tx_rings = le16_to_cpu(resp->max_tx_rings); 4184 pf->max_rx_rings = le16_to_cpu(resp->max_rx_rings); 4185 pf->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps); 4186 if (!pf->max_hw_ring_grps) 4187 pf->max_hw_ring_grps = pf->max_tx_rings; 4188 pf->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs); 4189 pf->max_vnics = le16_to_cpu(resp->max_vnics); 4190 pf->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx); 4191 pf->first_vf_id = le16_to_cpu(resp->first_vf_id); 4192 pf->max_vfs = le16_to_cpu(resp->max_vfs); 4193 pf->max_encap_records = le32_to_cpu(resp->max_encap_records); 4194 pf->max_decap_records = le32_to_cpu(resp->max_decap_records); 4195 pf->max_tx_em_flows = le32_to_cpu(resp->max_tx_em_flows); 4196 pf->max_tx_wm_flows = le32_to_cpu(resp->max_tx_wm_flows); 4197 pf->max_rx_em_flows = le32_to_cpu(resp->max_rx_em_flows); 4198 pf->max_rx_wm_flows = le32_to_cpu(resp->max_rx_wm_flows); 4199 } else { 4200 #ifdef CONFIG_BNXT_SRIOV 4201 struct bnxt_vf_info *vf = &bp->vf; 4202 4203 vf->fw_fid = le16_to_cpu(resp->fid); 4204 4205 vf->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx); 4206 vf->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings); 4207 vf->max_tx_rings = le16_to_cpu(resp->max_tx_rings); 4208 vf->max_rx_rings = le16_to_cpu(resp->max_rx_rings); 4209 vf->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps); 4210 if (!vf->max_hw_ring_grps) 4211 vf->max_hw_ring_grps = vf->max_tx_rings; 4212 vf->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs); 4213 vf->max_vnics = le16_to_cpu(resp->max_vnics); 4214 vf->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx); 4215 4216 memcpy(vf->mac_addr, resp->mac_address, ETH_ALEN); 4217 mutex_unlock(&bp->hwrm_cmd_lock); 4218 4219 if (is_valid_ether_addr(vf->mac_addr)) { 4220 /* overwrite netdev dev_adr with admin VF MAC */ 4221 memcpy(bp->dev->dev_addr, vf->mac_addr, ETH_ALEN); 4222 } else { 4223 random_ether_addr(bp->dev->dev_addr); 4224 rc = bnxt_approve_mac(bp, bp->dev->dev_addr); 4225 } 4226 return rc; 4227 #endif 4228 } 4229 4230 hwrm_func_qcaps_exit: 4231 mutex_unlock(&bp->hwrm_cmd_lock); 4232 return rc; 4233 } 4234 4235 static int bnxt_hwrm_func_reset(struct bnxt *bp) 4236 { 4237 struct hwrm_func_reset_input req = {0}; 4238 4239 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESET, -1, -1); 4240 req.enables = 0; 4241 4242 return hwrm_send_message(bp, &req, sizeof(req), HWRM_RESET_TIMEOUT); 4243 } 4244 4245 static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp) 4246 { 4247 int rc = 0; 4248 struct hwrm_queue_qportcfg_input req = {0}; 4249 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr; 4250 u8 i, *qptr; 4251 4252 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_QUEUE_QPORTCFG, -1, -1); 4253 4254 mutex_lock(&bp->hwrm_cmd_lock); 4255 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4256 if (rc) 4257 goto qportcfg_exit; 4258 4259 if (!resp->max_configurable_queues) { 4260 rc = -EINVAL; 4261 goto qportcfg_exit; 4262 } 4263 bp->max_tc = resp->max_configurable_queues; 4264 if (bp->max_tc > BNXT_MAX_QUEUE) 4265 bp->max_tc = BNXT_MAX_QUEUE; 4266 4267 if (resp->queue_cfg_info & QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG) 4268 bp->max_tc = 1; 4269 4270 qptr = &resp->queue_id0; 4271 for (i = 0; i < bp->max_tc; i++) { 4272 bp->q_info[i].queue_id = *qptr++; 4273 bp->q_info[i].queue_profile = *qptr++; 4274 } 4275 4276 qportcfg_exit: 4277 mutex_unlock(&bp->hwrm_cmd_lock); 4278 return rc; 4279 } 4280 4281 static int bnxt_hwrm_ver_get(struct bnxt *bp) 4282 { 4283 int rc; 4284 struct hwrm_ver_get_input req = {0}; 4285 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr; 4286 4287 bp->hwrm_max_req_len = HWRM_MAX_REQ_LEN; 4288 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VER_GET, -1, -1); 4289 req.hwrm_intf_maj = HWRM_VERSION_MAJOR; 4290 req.hwrm_intf_min = HWRM_VERSION_MINOR; 4291 req.hwrm_intf_upd = HWRM_VERSION_UPDATE; 4292 mutex_lock(&bp->hwrm_cmd_lock); 4293 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4294 if (rc) 4295 goto hwrm_ver_get_exit; 4296 4297 memcpy(&bp->ver_resp, resp, sizeof(struct hwrm_ver_get_output)); 4298 4299 bp->hwrm_spec_code = resp->hwrm_intf_maj << 16 | 4300 resp->hwrm_intf_min << 8 | resp->hwrm_intf_upd; 4301 if (resp->hwrm_intf_maj < 1) { 4302 netdev_warn(bp->dev, "HWRM interface %d.%d.%d is older than 1.0.0.\n", 4303 resp->hwrm_intf_maj, resp->hwrm_intf_min, 4304 resp->hwrm_intf_upd); 4305 netdev_warn(bp->dev, "Please update firmware with HWRM interface 1.0.0 or newer.\n"); 4306 } 4307 snprintf(bp->fw_ver_str, BC_HWRM_STR_LEN, "%d.%d.%d/%d.%d.%d", 4308 resp->hwrm_fw_maj, resp->hwrm_fw_min, resp->hwrm_fw_bld, 4309 resp->hwrm_intf_maj, resp->hwrm_intf_min, resp->hwrm_intf_upd); 4310 4311 bp->hwrm_cmd_timeout = le16_to_cpu(resp->def_req_timeout); 4312 if (!bp->hwrm_cmd_timeout) 4313 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT; 4314 4315 if (resp->hwrm_intf_maj >= 1) 4316 bp->hwrm_max_req_len = le16_to_cpu(resp->max_req_win_len); 4317 4318 bp->chip_num = le16_to_cpu(resp->chip_num); 4319 if (bp->chip_num == CHIP_NUM_58700 && !resp->chip_rev && 4320 !resp->chip_metal) 4321 bp->flags |= BNXT_FLAG_CHIP_NITRO_A0; 4322 4323 hwrm_ver_get_exit: 4324 mutex_unlock(&bp->hwrm_cmd_lock); 4325 return rc; 4326 } 4327 4328 int bnxt_hwrm_fw_set_time(struct bnxt *bp) 4329 { 4330 #if IS_ENABLED(CONFIG_RTC_LIB) 4331 struct hwrm_fw_set_time_input req = {0}; 4332 struct rtc_time tm; 4333 struct timeval tv; 4334 4335 if (bp->hwrm_spec_code < 0x10400) 4336 return -EOPNOTSUPP; 4337 4338 do_gettimeofday(&tv); 4339 rtc_time_to_tm(tv.tv_sec, &tm); 4340 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FW_SET_TIME, -1, -1); 4341 req.year = cpu_to_le16(1900 + tm.tm_year); 4342 req.month = 1 + tm.tm_mon; 4343 req.day = tm.tm_mday; 4344 req.hour = tm.tm_hour; 4345 req.minute = tm.tm_min; 4346 req.second = tm.tm_sec; 4347 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4348 #else 4349 return -EOPNOTSUPP; 4350 #endif 4351 } 4352 4353 static int bnxt_hwrm_port_qstats(struct bnxt *bp) 4354 { 4355 int rc; 4356 struct bnxt_pf_info *pf = &bp->pf; 4357 struct hwrm_port_qstats_input req = {0}; 4358 4359 if (!(bp->flags & BNXT_FLAG_PORT_STATS)) 4360 return 0; 4361 4362 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_QSTATS, -1, -1); 4363 req.port_id = cpu_to_le16(pf->port_id); 4364 req.tx_stat_host_addr = cpu_to_le64(bp->hw_tx_port_stats_map); 4365 req.rx_stat_host_addr = cpu_to_le64(bp->hw_rx_port_stats_map); 4366 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4367 return rc; 4368 } 4369 4370 static void bnxt_hwrm_free_tunnel_ports(struct bnxt *bp) 4371 { 4372 if (bp->vxlan_port_cnt) { 4373 bnxt_hwrm_tunnel_dst_port_free( 4374 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN); 4375 } 4376 bp->vxlan_port_cnt = 0; 4377 if (bp->nge_port_cnt) { 4378 bnxt_hwrm_tunnel_dst_port_free( 4379 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE); 4380 } 4381 bp->nge_port_cnt = 0; 4382 } 4383 4384 static int bnxt_set_tpa(struct bnxt *bp, bool set_tpa) 4385 { 4386 int rc, i; 4387 u32 tpa_flags = 0; 4388 4389 if (set_tpa) 4390 tpa_flags = bp->flags & BNXT_FLAG_TPA; 4391 for (i = 0; i < bp->nr_vnics; i++) { 4392 rc = bnxt_hwrm_vnic_set_tpa(bp, i, tpa_flags); 4393 if (rc) { 4394 netdev_err(bp->dev, "hwrm vnic set tpa failure rc for vnic %d: %x\n", 4395 rc, i); 4396 return rc; 4397 } 4398 } 4399 return 0; 4400 } 4401 4402 static void bnxt_hwrm_clear_vnic_rss(struct bnxt *bp) 4403 { 4404 int i; 4405 4406 for (i = 0; i < bp->nr_vnics; i++) 4407 bnxt_hwrm_vnic_set_rss(bp, i, false); 4408 } 4409 4410 static void bnxt_hwrm_resource_free(struct bnxt *bp, bool close_path, 4411 bool irq_re_init) 4412 { 4413 if (bp->vnic_info) { 4414 bnxt_hwrm_clear_vnic_filter(bp); 4415 /* clear all RSS setting before free vnic ctx */ 4416 bnxt_hwrm_clear_vnic_rss(bp); 4417 bnxt_hwrm_vnic_ctx_free(bp); 4418 /* before free the vnic, undo the vnic tpa settings */ 4419 if (bp->flags & BNXT_FLAG_TPA) 4420 bnxt_set_tpa(bp, false); 4421 bnxt_hwrm_vnic_free(bp); 4422 } 4423 bnxt_hwrm_ring_free(bp, close_path); 4424 bnxt_hwrm_ring_grp_free(bp); 4425 if (irq_re_init) { 4426 bnxt_hwrm_stat_ctx_free(bp); 4427 bnxt_hwrm_free_tunnel_ports(bp); 4428 } 4429 } 4430 4431 static int bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id) 4432 { 4433 int rc; 4434 4435 /* allocate context for vnic */ 4436 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 0); 4437 if (rc) { 4438 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n", 4439 vnic_id, rc); 4440 goto vnic_setup_err; 4441 } 4442 bp->rsscos_nr_ctxs++; 4443 4444 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) { 4445 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 1); 4446 if (rc) { 4447 netdev_err(bp->dev, "hwrm vnic %d cos ctx alloc failure rc: %x\n", 4448 vnic_id, rc); 4449 goto vnic_setup_err; 4450 } 4451 bp->rsscos_nr_ctxs++; 4452 } 4453 4454 /* configure default vnic, ring grp */ 4455 rc = bnxt_hwrm_vnic_cfg(bp, vnic_id); 4456 if (rc) { 4457 netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n", 4458 vnic_id, rc); 4459 goto vnic_setup_err; 4460 } 4461 4462 /* Enable RSS hashing on vnic */ 4463 rc = bnxt_hwrm_vnic_set_rss(bp, vnic_id, true); 4464 if (rc) { 4465 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %x\n", 4466 vnic_id, rc); 4467 goto vnic_setup_err; 4468 } 4469 4470 if (bp->flags & BNXT_FLAG_AGG_RINGS) { 4471 rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id); 4472 if (rc) { 4473 netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n", 4474 vnic_id, rc); 4475 } 4476 } 4477 4478 vnic_setup_err: 4479 return rc; 4480 } 4481 4482 static int bnxt_alloc_rfs_vnics(struct bnxt *bp) 4483 { 4484 #ifdef CONFIG_RFS_ACCEL 4485 int i, rc = 0; 4486 4487 for (i = 0; i < bp->rx_nr_rings; i++) { 4488 u16 vnic_id = i + 1; 4489 u16 ring_id = i; 4490 4491 if (vnic_id >= bp->nr_vnics) 4492 break; 4493 4494 bp->vnic_info[vnic_id].flags |= BNXT_VNIC_RFS_FLAG; 4495 rc = bnxt_hwrm_vnic_alloc(bp, vnic_id, ring_id, 1); 4496 if (rc) { 4497 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n", 4498 vnic_id, rc); 4499 break; 4500 } 4501 rc = bnxt_setup_vnic(bp, vnic_id); 4502 if (rc) 4503 break; 4504 } 4505 return rc; 4506 #else 4507 return 0; 4508 #endif 4509 } 4510 4511 /* Allow PF and VF with default VLAN to be in promiscuous mode */ 4512 static bool bnxt_promisc_ok(struct bnxt *bp) 4513 { 4514 #ifdef CONFIG_BNXT_SRIOV 4515 if (BNXT_VF(bp) && !bp->vf.vlan) 4516 return false; 4517 #endif 4518 return true; 4519 } 4520 4521 static int bnxt_setup_nitroa0_vnic(struct bnxt *bp) 4522 { 4523 unsigned int rc = 0; 4524 4525 rc = bnxt_hwrm_vnic_alloc(bp, 1, bp->rx_nr_rings - 1, 1); 4526 if (rc) { 4527 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n", 4528 rc); 4529 return rc; 4530 } 4531 4532 rc = bnxt_hwrm_vnic_cfg(bp, 1); 4533 if (rc) { 4534 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n", 4535 rc); 4536 return rc; 4537 } 4538 return rc; 4539 } 4540 4541 static int bnxt_cfg_rx_mode(struct bnxt *); 4542 static bool bnxt_mc_list_updated(struct bnxt *, u32 *); 4543 4544 static int bnxt_init_chip(struct bnxt *bp, bool irq_re_init) 4545 { 4546 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 4547 int rc = 0; 4548 unsigned int rx_nr_rings = bp->rx_nr_rings; 4549 4550 if (irq_re_init) { 4551 rc = bnxt_hwrm_stat_ctx_alloc(bp); 4552 if (rc) { 4553 netdev_err(bp->dev, "hwrm stat ctx alloc failure rc: %x\n", 4554 rc); 4555 goto err_out; 4556 } 4557 } 4558 4559 rc = bnxt_hwrm_ring_alloc(bp); 4560 if (rc) { 4561 netdev_err(bp->dev, "hwrm ring alloc failure rc: %x\n", rc); 4562 goto err_out; 4563 } 4564 4565 rc = bnxt_hwrm_ring_grp_alloc(bp); 4566 if (rc) { 4567 netdev_err(bp->dev, "hwrm_ring_grp alloc failure: %x\n", rc); 4568 goto err_out; 4569 } 4570 4571 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 4572 rx_nr_rings--; 4573 4574 /* default vnic 0 */ 4575 rc = bnxt_hwrm_vnic_alloc(bp, 0, 0, rx_nr_rings); 4576 if (rc) { 4577 netdev_err(bp->dev, "hwrm vnic alloc failure rc: %x\n", rc); 4578 goto err_out; 4579 } 4580 4581 rc = bnxt_setup_vnic(bp, 0); 4582 if (rc) 4583 goto err_out; 4584 4585 if (bp->flags & BNXT_FLAG_RFS) { 4586 rc = bnxt_alloc_rfs_vnics(bp); 4587 if (rc) 4588 goto err_out; 4589 } 4590 4591 if (bp->flags & BNXT_FLAG_TPA) { 4592 rc = bnxt_set_tpa(bp, true); 4593 if (rc) 4594 goto err_out; 4595 } 4596 4597 if (BNXT_VF(bp)) 4598 bnxt_update_vf_mac(bp); 4599 4600 /* Filter for default vnic 0 */ 4601 rc = bnxt_hwrm_set_vnic_filter(bp, 0, 0, bp->dev->dev_addr); 4602 if (rc) { 4603 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n", rc); 4604 goto err_out; 4605 } 4606 vnic->uc_filter_count = 1; 4607 4608 vnic->rx_mask = CFA_L2_SET_RX_MASK_REQ_MASK_BCAST; 4609 4610 if ((bp->dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp)) 4611 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS; 4612 4613 if (bp->dev->flags & IFF_ALLMULTI) { 4614 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST; 4615 vnic->mc_list_count = 0; 4616 } else { 4617 u32 mask = 0; 4618 4619 bnxt_mc_list_updated(bp, &mask); 4620 vnic->rx_mask |= mask; 4621 } 4622 4623 rc = bnxt_cfg_rx_mode(bp); 4624 if (rc) 4625 goto err_out; 4626 4627 rc = bnxt_hwrm_set_coal(bp); 4628 if (rc) 4629 netdev_warn(bp->dev, "HWRM set coalescing failure rc: %x\n", 4630 rc); 4631 4632 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) { 4633 rc = bnxt_setup_nitroa0_vnic(bp); 4634 if (rc) 4635 netdev_err(bp->dev, "Special vnic setup failure for NS2 A0 rc: %x\n", 4636 rc); 4637 } 4638 4639 if (BNXT_VF(bp)) { 4640 bnxt_hwrm_func_qcfg(bp); 4641 netdev_update_features(bp->dev); 4642 } 4643 4644 return 0; 4645 4646 err_out: 4647 bnxt_hwrm_resource_free(bp, 0, true); 4648 4649 return rc; 4650 } 4651 4652 static int bnxt_shutdown_nic(struct bnxt *bp, bool irq_re_init) 4653 { 4654 bnxt_hwrm_resource_free(bp, 1, irq_re_init); 4655 return 0; 4656 } 4657 4658 static int bnxt_init_nic(struct bnxt *bp, bool irq_re_init) 4659 { 4660 bnxt_init_rx_rings(bp); 4661 bnxt_init_tx_rings(bp); 4662 bnxt_init_ring_grps(bp, irq_re_init); 4663 bnxt_init_vnics(bp); 4664 4665 return bnxt_init_chip(bp, irq_re_init); 4666 } 4667 4668 static void bnxt_disable_int(struct bnxt *bp) 4669 { 4670 int i; 4671 4672 if (!bp->bnapi) 4673 return; 4674 4675 for (i = 0; i < bp->cp_nr_rings; i++) { 4676 struct bnxt_napi *bnapi = bp->bnapi[i]; 4677 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 4678 4679 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons); 4680 } 4681 } 4682 4683 static void bnxt_enable_int(struct bnxt *bp) 4684 { 4685 int i; 4686 4687 atomic_set(&bp->intr_sem, 0); 4688 for (i = 0; i < bp->cp_nr_rings; i++) { 4689 struct bnxt_napi *bnapi = bp->bnapi[i]; 4690 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 4691 4692 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons); 4693 } 4694 } 4695 4696 static int bnxt_set_real_num_queues(struct bnxt *bp) 4697 { 4698 int rc; 4699 struct net_device *dev = bp->dev; 4700 4701 rc = netif_set_real_num_tx_queues(dev, bp->tx_nr_rings); 4702 if (rc) 4703 return rc; 4704 4705 rc = netif_set_real_num_rx_queues(dev, bp->rx_nr_rings); 4706 if (rc) 4707 return rc; 4708 4709 #ifdef CONFIG_RFS_ACCEL 4710 if (bp->flags & BNXT_FLAG_RFS) 4711 dev->rx_cpu_rmap = alloc_irq_cpu_rmap(bp->rx_nr_rings); 4712 #endif 4713 4714 return rc; 4715 } 4716 4717 static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max, 4718 bool shared) 4719 { 4720 int _rx = *rx, _tx = *tx; 4721 4722 if (shared) { 4723 *rx = min_t(int, _rx, max); 4724 *tx = min_t(int, _tx, max); 4725 } else { 4726 if (max < 2) 4727 return -ENOMEM; 4728 4729 while (_rx + _tx > max) { 4730 if (_rx > _tx && _rx > 1) 4731 _rx--; 4732 else if (_tx > 1) 4733 _tx--; 4734 } 4735 *rx = _rx; 4736 *tx = _tx; 4737 } 4738 return 0; 4739 } 4740 4741 static int bnxt_setup_msix(struct bnxt *bp) 4742 { 4743 struct msix_entry *msix_ent; 4744 struct net_device *dev = bp->dev; 4745 int i, total_vecs, rc = 0, min = 1; 4746 const int len = sizeof(bp->irq_tbl[0].name); 4747 4748 bp->flags &= ~BNXT_FLAG_USING_MSIX; 4749 total_vecs = bp->cp_nr_rings; 4750 4751 msix_ent = kcalloc(total_vecs, sizeof(struct msix_entry), GFP_KERNEL); 4752 if (!msix_ent) 4753 return -ENOMEM; 4754 4755 for (i = 0; i < total_vecs; i++) { 4756 msix_ent[i].entry = i; 4757 msix_ent[i].vector = 0; 4758 } 4759 4760 if (!(bp->flags & BNXT_FLAG_SHARED_RINGS)) 4761 min = 2; 4762 4763 total_vecs = pci_enable_msix_range(bp->pdev, msix_ent, min, total_vecs); 4764 if (total_vecs < 0) { 4765 rc = -ENODEV; 4766 goto msix_setup_exit; 4767 } 4768 4769 bp->irq_tbl = kcalloc(total_vecs, sizeof(struct bnxt_irq), GFP_KERNEL); 4770 if (bp->irq_tbl) { 4771 int tcs; 4772 4773 /* Trim rings based upon num of vectors allocated */ 4774 rc = bnxt_trim_rings(bp, &bp->rx_nr_rings, &bp->tx_nr_rings, 4775 total_vecs, min == 1); 4776 if (rc) 4777 goto msix_setup_exit; 4778 4779 bp->tx_nr_rings_per_tc = bp->tx_nr_rings; 4780 tcs = netdev_get_num_tc(dev); 4781 if (tcs > 1) { 4782 bp->tx_nr_rings_per_tc = bp->tx_nr_rings / tcs; 4783 if (bp->tx_nr_rings_per_tc == 0) { 4784 netdev_reset_tc(dev); 4785 bp->tx_nr_rings_per_tc = bp->tx_nr_rings; 4786 } else { 4787 int i, off, count; 4788 4789 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tcs; 4790 for (i = 0; i < tcs; i++) { 4791 count = bp->tx_nr_rings_per_tc; 4792 off = i * count; 4793 netdev_set_tc_queue(dev, i, count, off); 4794 } 4795 } 4796 } 4797 bp->cp_nr_rings = total_vecs; 4798 4799 for (i = 0; i < bp->cp_nr_rings; i++) { 4800 char *attr; 4801 4802 bp->irq_tbl[i].vector = msix_ent[i].vector; 4803 if (bp->flags & BNXT_FLAG_SHARED_RINGS) 4804 attr = "TxRx"; 4805 else if (i < bp->rx_nr_rings) 4806 attr = "rx"; 4807 else 4808 attr = "tx"; 4809 4810 snprintf(bp->irq_tbl[i].name, len, 4811 "%s-%s-%d", dev->name, attr, i); 4812 bp->irq_tbl[i].handler = bnxt_msix; 4813 } 4814 rc = bnxt_set_real_num_queues(bp); 4815 if (rc) 4816 goto msix_setup_exit; 4817 } else { 4818 rc = -ENOMEM; 4819 goto msix_setup_exit; 4820 } 4821 bp->flags |= BNXT_FLAG_USING_MSIX; 4822 kfree(msix_ent); 4823 return 0; 4824 4825 msix_setup_exit: 4826 netdev_err(bp->dev, "bnxt_setup_msix err: %x\n", rc); 4827 pci_disable_msix(bp->pdev); 4828 kfree(msix_ent); 4829 return rc; 4830 } 4831 4832 static int bnxt_setup_inta(struct bnxt *bp) 4833 { 4834 int rc; 4835 const int len = sizeof(bp->irq_tbl[0].name); 4836 4837 if (netdev_get_num_tc(bp->dev)) 4838 netdev_reset_tc(bp->dev); 4839 4840 bp->irq_tbl = kcalloc(1, sizeof(struct bnxt_irq), GFP_KERNEL); 4841 if (!bp->irq_tbl) { 4842 rc = -ENOMEM; 4843 return rc; 4844 } 4845 bp->rx_nr_rings = 1; 4846 bp->tx_nr_rings = 1; 4847 bp->cp_nr_rings = 1; 4848 bp->tx_nr_rings_per_tc = bp->tx_nr_rings; 4849 bp->flags |= BNXT_FLAG_SHARED_RINGS; 4850 bp->irq_tbl[0].vector = bp->pdev->irq; 4851 snprintf(bp->irq_tbl[0].name, len, 4852 "%s-%s-%d", bp->dev->name, "TxRx", 0); 4853 bp->irq_tbl[0].handler = bnxt_inta; 4854 rc = bnxt_set_real_num_queues(bp); 4855 return rc; 4856 } 4857 4858 static int bnxt_setup_int_mode(struct bnxt *bp) 4859 { 4860 int rc = 0; 4861 4862 if (bp->flags & BNXT_FLAG_MSIX_CAP) 4863 rc = bnxt_setup_msix(bp); 4864 4865 if (!(bp->flags & BNXT_FLAG_USING_MSIX) && BNXT_PF(bp)) { 4866 /* fallback to INTA */ 4867 rc = bnxt_setup_inta(bp); 4868 } 4869 return rc; 4870 } 4871 4872 static void bnxt_free_irq(struct bnxt *bp) 4873 { 4874 struct bnxt_irq *irq; 4875 int i; 4876 4877 #ifdef CONFIG_RFS_ACCEL 4878 free_irq_cpu_rmap(bp->dev->rx_cpu_rmap); 4879 bp->dev->rx_cpu_rmap = NULL; 4880 #endif 4881 if (!bp->irq_tbl) 4882 return; 4883 4884 for (i = 0; i < bp->cp_nr_rings; i++) { 4885 irq = &bp->irq_tbl[i]; 4886 if (irq->requested) 4887 free_irq(irq->vector, bp->bnapi[i]); 4888 irq->requested = 0; 4889 } 4890 if (bp->flags & BNXT_FLAG_USING_MSIX) 4891 pci_disable_msix(bp->pdev); 4892 kfree(bp->irq_tbl); 4893 bp->irq_tbl = NULL; 4894 } 4895 4896 static int bnxt_request_irq(struct bnxt *bp) 4897 { 4898 int i, j, rc = 0; 4899 unsigned long flags = 0; 4900 #ifdef CONFIG_RFS_ACCEL 4901 struct cpu_rmap *rmap = bp->dev->rx_cpu_rmap; 4902 #endif 4903 4904 if (!(bp->flags & BNXT_FLAG_USING_MSIX)) 4905 flags = IRQF_SHARED; 4906 4907 for (i = 0, j = 0; i < bp->cp_nr_rings; i++) { 4908 struct bnxt_irq *irq = &bp->irq_tbl[i]; 4909 #ifdef CONFIG_RFS_ACCEL 4910 if (rmap && bp->bnapi[i]->rx_ring) { 4911 rc = irq_cpu_rmap_add(rmap, irq->vector); 4912 if (rc) 4913 netdev_warn(bp->dev, "failed adding irq rmap for ring %d\n", 4914 j); 4915 j++; 4916 } 4917 #endif 4918 rc = request_irq(irq->vector, irq->handler, flags, irq->name, 4919 bp->bnapi[i]); 4920 if (rc) 4921 break; 4922 4923 irq->requested = 1; 4924 } 4925 return rc; 4926 } 4927 4928 static void bnxt_del_napi(struct bnxt *bp) 4929 { 4930 int i; 4931 4932 if (!bp->bnapi) 4933 return; 4934 4935 for (i = 0; i < bp->cp_nr_rings; i++) { 4936 struct bnxt_napi *bnapi = bp->bnapi[i]; 4937 4938 napi_hash_del(&bnapi->napi); 4939 netif_napi_del(&bnapi->napi); 4940 } 4941 /* We called napi_hash_del() before netif_napi_del(), we need 4942 * to respect an RCU grace period before freeing napi structures. 4943 */ 4944 synchronize_net(); 4945 } 4946 4947 static void bnxt_init_napi(struct bnxt *bp) 4948 { 4949 int i; 4950 unsigned int cp_nr_rings = bp->cp_nr_rings; 4951 struct bnxt_napi *bnapi; 4952 4953 if (bp->flags & BNXT_FLAG_USING_MSIX) { 4954 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 4955 cp_nr_rings--; 4956 for (i = 0; i < cp_nr_rings; i++) { 4957 bnapi = bp->bnapi[i]; 4958 netif_napi_add(bp->dev, &bnapi->napi, 4959 bnxt_poll, 64); 4960 } 4961 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) { 4962 bnapi = bp->bnapi[cp_nr_rings]; 4963 netif_napi_add(bp->dev, &bnapi->napi, 4964 bnxt_poll_nitroa0, 64); 4965 } 4966 } else { 4967 bnapi = bp->bnapi[0]; 4968 netif_napi_add(bp->dev, &bnapi->napi, bnxt_poll, 64); 4969 } 4970 } 4971 4972 static void bnxt_disable_napi(struct bnxt *bp) 4973 { 4974 int i; 4975 4976 if (!bp->bnapi) 4977 return; 4978 4979 for (i = 0; i < bp->cp_nr_rings; i++) { 4980 napi_disable(&bp->bnapi[i]->napi); 4981 bnxt_disable_poll(bp->bnapi[i]); 4982 } 4983 } 4984 4985 static void bnxt_enable_napi(struct bnxt *bp) 4986 { 4987 int i; 4988 4989 for (i = 0; i < bp->cp_nr_rings; i++) { 4990 bp->bnapi[i]->in_reset = false; 4991 bnxt_enable_poll(bp->bnapi[i]); 4992 napi_enable(&bp->bnapi[i]->napi); 4993 } 4994 } 4995 4996 static void bnxt_tx_disable(struct bnxt *bp) 4997 { 4998 int i; 4999 struct bnxt_tx_ring_info *txr; 5000 struct netdev_queue *txq; 5001 5002 if (bp->tx_ring) { 5003 for (i = 0; i < bp->tx_nr_rings; i++) { 5004 txr = &bp->tx_ring[i]; 5005 txq = netdev_get_tx_queue(bp->dev, i); 5006 txr->dev_state = BNXT_DEV_STATE_CLOSING; 5007 } 5008 } 5009 /* Stop all TX queues */ 5010 netif_tx_disable(bp->dev); 5011 netif_carrier_off(bp->dev); 5012 } 5013 5014 static void bnxt_tx_enable(struct bnxt *bp) 5015 { 5016 int i; 5017 struct bnxt_tx_ring_info *txr; 5018 struct netdev_queue *txq; 5019 5020 for (i = 0; i < bp->tx_nr_rings; i++) { 5021 txr = &bp->tx_ring[i]; 5022 txq = netdev_get_tx_queue(bp->dev, i); 5023 txr->dev_state = 0; 5024 } 5025 netif_tx_wake_all_queues(bp->dev); 5026 if (bp->link_info.link_up) 5027 netif_carrier_on(bp->dev); 5028 } 5029 5030 static void bnxt_report_link(struct bnxt *bp) 5031 { 5032 if (bp->link_info.link_up) { 5033 const char *duplex; 5034 const char *flow_ctrl; 5035 u16 speed; 5036 5037 netif_carrier_on(bp->dev); 5038 if (bp->link_info.duplex == BNXT_LINK_DUPLEX_FULL) 5039 duplex = "full"; 5040 else 5041 duplex = "half"; 5042 if (bp->link_info.pause == BNXT_LINK_PAUSE_BOTH) 5043 flow_ctrl = "ON - receive & transmit"; 5044 else if (bp->link_info.pause == BNXT_LINK_PAUSE_TX) 5045 flow_ctrl = "ON - transmit"; 5046 else if (bp->link_info.pause == BNXT_LINK_PAUSE_RX) 5047 flow_ctrl = "ON - receive"; 5048 else 5049 flow_ctrl = "none"; 5050 speed = bnxt_fw_to_ethtool_speed(bp->link_info.link_speed); 5051 netdev_info(bp->dev, "NIC Link is Up, %d Mbps %s duplex, Flow control: %s\n", 5052 speed, duplex, flow_ctrl); 5053 if (bp->flags & BNXT_FLAG_EEE_CAP) 5054 netdev_info(bp->dev, "EEE is %s\n", 5055 bp->eee.eee_active ? "active" : 5056 "not active"); 5057 } else { 5058 netif_carrier_off(bp->dev); 5059 netdev_err(bp->dev, "NIC Link is Down\n"); 5060 } 5061 } 5062 5063 static int bnxt_hwrm_phy_qcaps(struct bnxt *bp) 5064 { 5065 int rc = 0; 5066 struct hwrm_port_phy_qcaps_input req = {0}; 5067 struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr; 5068 struct bnxt_link_info *link_info = &bp->link_info; 5069 5070 if (bp->hwrm_spec_code < 0x10201) 5071 return 0; 5072 5073 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCAPS, -1, -1); 5074 5075 mutex_lock(&bp->hwrm_cmd_lock); 5076 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5077 if (rc) 5078 goto hwrm_phy_qcaps_exit; 5079 5080 if (resp->eee_supported & PORT_PHY_QCAPS_RESP_EEE_SUPPORTED) { 5081 struct ethtool_eee *eee = &bp->eee; 5082 u16 fw_speeds = le16_to_cpu(resp->supported_speeds_eee_mode); 5083 5084 bp->flags |= BNXT_FLAG_EEE_CAP; 5085 eee->supported = _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0); 5086 bp->lpi_tmr_lo = le32_to_cpu(resp->tx_lpi_timer_low) & 5087 PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK; 5088 bp->lpi_tmr_hi = le32_to_cpu(resp->valid_tx_lpi_timer_high) & 5089 PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK; 5090 } 5091 link_info->support_auto_speeds = 5092 le16_to_cpu(resp->supported_speeds_auto_mode); 5093 5094 hwrm_phy_qcaps_exit: 5095 mutex_unlock(&bp->hwrm_cmd_lock); 5096 return rc; 5097 } 5098 5099 static int bnxt_update_link(struct bnxt *bp, bool chng_link_state) 5100 { 5101 int rc = 0; 5102 struct bnxt_link_info *link_info = &bp->link_info; 5103 struct hwrm_port_phy_qcfg_input req = {0}; 5104 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr; 5105 u8 link_up = link_info->link_up; 5106 u16 diff; 5107 5108 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCFG, -1, -1); 5109 5110 mutex_lock(&bp->hwrm_cmd_lock); 5111 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5112 if (rc) { 5113 mutex_unlock(&bp->hwrm_cmd_lock); 5114 return rc; 5115 } 5116 5117 memcpy(&link_info->phy_qcfg_resp, resp, sizeof(*resp)); 5118 link_info->phy_link_status = resp->link; 5119 link_info->duplex = resp->duplex; 5120 link_info->pause = resp->pause; 5121 link_info->auto_mode = resp->auto_mode; 5122 link_info->auto_pause_setting = resp->auto_pause; 5123 link_info->lp_pause = resp->link_partner_adv_pause; 5124 link_info->force_pause_setting = resp->force_pause; 5125 link_info->duplex_setting = resp->duplex; 5126 if (link_info->phy_link_status == BNXT_LINK_LINK) 5127 link_info->link_speed = le16_to_cpu(resp->link_speed); 5128 else 5129 link_info->link_speed = 0; 5130 link_info->force_link_speed = le16_to_cpu(resp->force_link_speed); 5131 link_info->support_speeds = le16_to_cpu(resp->support_speeds); 5132 link_info->auto_link_speeds = le16_to_cpu(resp->auto_link_speed_mask); 5133 link_info->lp_auto_link_speeds = 5134 le16_to_cpu(resp->link_partner_adv_speeds); 5135 link_info->preemphasis = le32_to_cpu(resp->preemphasis); 5136 link_info->phy_ver[0] = resp->phy_maj; 5137 link_info->phy_ver[1] = resp->phy_min; 5138 link_info->phy_ver[2] = resp->phy_bld; 5139 link_info->media_type = resp->media_type; 5140 link_info->phy_type = resp->phy_type; 5141 link_info->transceiver = resp->xcvr_pkg_type; 5142 link_info->phy_addr = resp->eee_config_phy_addr & 5143 PORT_PHY_QCFG_RESP_PHY_ADDR_MASK; 5144 link_info->module_status = resp->module_status; 5145 5146 if (bp->flags & BNXT_FLAG_EEE_CAP) { 5147 struct ethtool_eee *eee = &bp->eee; 5148 u16 fw_speeds; 5149 5150 eee->eee_active = 0; 5151 if (resp->eee_config_phy_addr & 5152 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE) { 5153 eee->eee_active = 1; 5154 fw_speeds = le16_to_cpu( 5155 resp->link_partner_adv_eee_link_speed_mask); 5156 eee->lp_advertised = 5157 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0); 5158 } 5159 5160 /* Pull initial EEE config */ 5161 if (!chng_link_state) { 5162 if (resp->eee_config_phy_addr & 5163 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED) 5164 eee->eee_enabled = 1; 5165 5166 fw_speeds = le16_to_cpu(resp->adv_eee_link_speed_mask); 5167 eee->advertised = 5168 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0); 5169 5170 if (resp->eee_config_phy_addr & 5171 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI) { 5172 __le32 tmr; 5173 5174 eee->tx_lpi_enabled = 1; 5175 tmr = resp->xcvr_identifier_type_tx_lpi_timer; 5176 eee->tx_lpi_timer = le32_to_cpu(tmr) & 5177 PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK; 5178 } 5179 } 5180 } 5181 /* TODO: need to add more logic to report VF link */ 5182 if (chng_link_state) { 5183 if (link_info->phy_link_status == BNXT_LINK_LINK) 5184 link_info->link_up = 1; 5185 else 5186 link_info->link_up = 0; 5187 if (link_up != link_info->link_up) 5188 bnxt_report_link(bp); 5189 } else { 5190 /* alwasy link down if not require to update link state */ 5191 link_info->link_up = 0; 5192 } 5193 mutex_unlock(&bp->hwrm_cmd_lock); 5194 5195 diff = link_info->support_auto_speeds ^ link_info->advertising; 5196 if ((link_info->support_auto_speeds | diff) != 5197 link_info->support_auto_speeds) { 5198 /* An advertised speed is no longer supported, so we need to 5199 * update the advertisement settings. See bnxt_reset() for 5200 * comments about the rtnl_lock() sequence below. 5201 */ 5202 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state); 5203 rtnl_lock(); 5204 link_info->advertising = link_info->support_auto_speeds; 5205 if (test_bit(BNXT_STATE_OPEN, &bp->state) && 5206 (link_info->autoneg & BNXT_AUTONEG_SPEED)) 5207 bnxt_hwrm_set_link_setting(bp, true, false); 5208 set_bit(BNXT_STATE_IN_SP_TASK, &bp->state); 5209 rtnl_unlock(); 5210 } 5211 return 0; 5212 } 5213 5214 static void bnxt_get_port_module_status(struct bnxt *bp) 5215 { 5216 struct bnxt_link_info *link_info = &bp->link_info; 5217 struct hwrm_port_phy_qcfg_output *resp = &link_info->phy_qcfg_resp; 5218 u8 module_status; 5219 5220 if (bnxt_update_link(bp, true)) 5221 return; 5222 5223 module_status = link_info->module_status; 5224 switch (module_status) { 5225 case PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX: 5226 case PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN: 5227 case PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG: 5228 netdev_warn(bp->dev, "Unqualified SFP+ module detected on port %d\n", 5229 bp->pf.port_id); 5230 if (bp->hwrm_spec_code >= 0x10201) { 5231 netdev_warn(bp->dev, "Module part number %s\n", 5232 resp->phy_vendor_partnumber); 5233 } 5234 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX) 5235 netdev_warn(bp->dev, "TX is disabled\n"); 5236 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN) 5237 netdev_warn(bp->dev, "SFP+ module is shutdown\n"); 5238 } 5239 } 5240 5241 static void 5242 bnxt_hwrm_set_pause_common(struct bnxt *bp, struct hwrm_port_phy_cfg_input *req) 5243 { 5244 if (bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) { 5245 if (bp->hwrm_spec_code >= 0x10201) 5246 req->auto_pause = 5247 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE; 5248 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX) 5249 req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX; 5250 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX) 5251 req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_TX; 5252 req->enables |= 5253 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE); 5254 } else { 5255 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX) 5256 req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_RX; 5257 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX) 5258 req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_TX; 5259 req->enables |= 5260 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE); 5261 if (bp->hwrm_spec_code >= 0x10201) { 5262 req->auto_pause = req->force_pause; 5263 req->enables |= cpu_to_le32( 5264 PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE); 5265 } 5266 } 5267 } 5268 5269 static void bnxt_hwrm_set_link_common(struct bnxt *bp, 5270 struct hwrm_port_phy_cfg_input *req) 5271 { 5272 u8 autoneg = bp->link_info.autoneg; 5273 u16 fw_link_speed = bp->link_info.req_link_speed; 5274 u32 advertising = bp->link_info.advertising; 5275 5276 if (autoneg & BNXT_AUTONEG_SPEED) { 5277 req->auto_mode |= 5278 PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK; 5279 5280 req->enables |= cpu_to_le32( 5281 PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK); 5282 req->auto_link_speed_mask = cpu_to_le16(advertising); 5283 5284 req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE); 5285 req->flags |= 5286 cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG); 5287 } else { 5288 req->force_link_speed = cpu_to_le16(fw_link_speed); 5289 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE); 5290 } 5291 5292 /* tell chimp that the setting takes effect immediately */ 5293 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESET_PHY); 5294 } 5295 5296 int bnxt_hwrm_set_pause(struct bnxt *bp) 5297 { 5298 struct hwrm_port_phy_cfg_input req = {0}; 5299 int rc; 5300 5301 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1); 5302 bnxt_hwrm_set_pause_common(bp, &req); 5303 5304 if ((bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) || 5305 bp->link_info.force_link_chng) 5306 bnxt_hwrm_set_link_common(bp, &req); 5307 5308 mutex_lock(&bp->hwrm_cmd_lock); 5309 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5310 if (!rc && !(bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL)) { 5311 /* since changing of pause setting doesn't trigger any link 5312 * change event, the driver needs to update the current pause 5313 * result upon successfully return of the phy_cfg command 5314 */ 5315 bp->link_info.pause = 5316 bp->link_info.force_pause_setting = bp->link_info.req_flow_ctrl; 5317 bp->link_info.auto_pause_setting = 0; 5318 if (!bp->link_info.force_link_chng) 5319 bnxt_report_link(bp); 5320 } 5321 bp->link_info.force_link_chng = false; 5322 mutex_unlock(&bp->hwrm_cmd_lock); 5323 return rc; 5324 } 5325 5326 static void bnxt_hwrm_set_eee(struct bnxt *bp, 5327 struct hwrm_port_phy_cfg_input *req) 5328 { 5329 struct ethtool_eee *eee = &bp->eee; 5330 5331 if (eee->eee_enabled) { 5332 u16 eee_speeds; 5333 u32 flags = PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE; 5334 5335 if (eee->tx_lpi_enabled) 5336 flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE; 5337 else 5338 flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE; 5339 5340 req->flags |= cpu_to_le32(flags); 5341 eee_speeds = bnxt_get_fw_auto_link_speeds(eee->advertised); 5342 req->eee_link_speed_mask = cpu_to_le16(eee_speeds); 5343 req->tx_lpi_timer = cpu_to_le32(eee->tx_lpi_timer); 5344 } else { 5345 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE); 5346 } 5347 } 5348 5349 int bnxt_hwrm_set_link_setting(struct bnxt *bp, bool set_pause, bool set_eee) 5350 { 5351 struct hwrm_port_phy_cfg_input req = {0}; 5352 5353 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1); 5354 if (set_pause) 5355 bnxt_hwrm_set_pause_common(bp, &req); 5356 5357 bnxt_hwrm_set_link_common(bp, &req); 5358 5359 if (set_eee) 5360 bnxt_hwrm_set_eee(bp, &req); 5361 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5362 } 5363 5364 static int bnxt_hwrm_shutdown_link(struct bnxt *bp) 5365 { 5366 struct hwrm_port_phy_cfg_input req = {0}; 5367 5368 if (!BNXT_SINGLE_PF(bp)) 5369 return 0; 5370 5371 if (pci_num_vf(bp->pdev)) 5372 return 0; 5373 5374 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1); 5375 req.flags = cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN); 5376 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5377 } 5378 5379 static bool bnxt_eee_config_ok(struct bnxt *bp) 5380 { 5381 struct ethtool_eee *eee = &bp->eee; 5382 struct bnxt_link_info *link_info = &bp->link_info; 5383 5384 if (!(bp->flags & BNXT_FLAG_EEE_CAP)) 5385 return true; 5386 5387 if (eee->eee_enabled) { 5388 u32 advertising = 5389 _bnxt_fw_to_ethtool_adv_spds(link_info->advertising, 0); 5390 5391 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) { 5392 eee->eee_enabled = 0; 5393 return false; 5394 } 5395 if (eee->advertised & ~advertising) { 5396 eee->advertised = advertising & eee->supported; 5397 return false; 5398 } 5399 } 5400 return true; 5401 } 5402 5403 static int bnxt_update_phy_setting(struct bnxt *bp) 5404 { 5405 int rc; 5406 bool update_link = false; 5407 bool update_pause = false; 5408 bool update_eee = false; 5409 struct bnxt_link_info *link_info = &bp->link_info; 5410 5411 rc = bnxt_update_link(bp, true); 5412 if (rc) { 5413 netdev_err(bp->dev, "failed to update link (rc: %x)\n", 5414 rc); 5415 return rc; 5416 } 5417 if ((link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) && 5418 (link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH) != 5419 link_info->req_flow_ctrl) 5420 update_pause = true; 5421 if (!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) && 5422 link_info->force_pause_setting != link_info->req_flow_ctrl) 5423 update_pause = true; 5424 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) { 5425 if (BNXT_AUTO_MODE(link_info->auto_mode)) 5426 update_link = true; 5427 if (link_info->req_link_speed != link_info->force_link_speed) 5428 update_link = true; 5429 if (link_info->req_duplex != link_info->duplex_setting) 5430 update_link = true; 5431 } else { 5432 if (link_info->auto_mode == BNXT_LINK_AUTO_NONE) 5433 update_link = true; 5434 if (link_info->advertising != link_info->auto_link_speeds) 5435 update_link = true; 5436 } 5437 5438 /* The last close may have shutdown the link, so need to call 5439 * PHY_CFG to bring it back up. 5440 */ 5441 if (!netif_carrier_ok(bp->dev)) 5442 update_link = true; 5443 5444 if (!bnxt_eee_config_ok(bp)) 5445 update_eee = true; 5446 5447 if (update_link) 5448 rc = bnxt_hwrm_set_link_setting(bp, update_pause, update_eee); 5449 else if (update_pause) 5450 rc = bnxt_hwrm_set_pause(bp); 5451 if (rc) { 5452 netdev_err(bp->dev, "failed to update phy setting (rc: %x)\n", 5453 rc); 5454 return rc; 5455 } 5456 5457 return rc; 5458 } 5459 5460 /* Common routine to pre-map certain register block to different GRC window. 5461 * A PF has 16 4K windows and a VF has 4 4K windows. However, only 15 windows 5462 * in PF and 3 windows in VF that can be customized to map in different 5463 * register blocks. 5464 */ 5465 static void bnxt_preset_reg_win(struct bnxt *bp) 5466 { 5467 if (BNXT_PF(bp)) { 5468 /* CAG registers map to GRC window #4 */ 5469 writel(BNXT_CAG_REG_BASE, 5470 bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 12); 5471 } 5472 } 5473 5474 static int __bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init) 5475 { 5476 int rc = 0; 5477 5478 bnxt_preset_reg_win(bp); 5479 netif_carrier_off(bp->dev); 5480 if (irq_re_init) { 5481 rc = bnxt_setup_int_mode(bp); 5482 if (rc) { 5483 netdev_err(bp->dev, "bnxt_setup_int_mode err: %x\n", 5484 rc); 5485 return rc; 5486 } 5487 } 5488 if ((bp->flags & BNXT_FLAG_RFS) && 5489 !(bp->flags & BNXT_FLAG_USING_MSIX)) { 5490 /* disable RFS if falling back to INTA */ 5491 bp->dev->hw_features &= ~NETIF_F_NTUPLE; 5492 bp->flags &= ~BNXT_FLAG_RFS; 5493 } 5494 5495 rc = bnxt_alloc_mem(bp, irq_re_init); 5496 if (rc) { 5497 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc); 5498 goto open_err_free_mem; 5499 } 5500 5501 if (irq_re_init) { 5502 bnxt_init_napi(bp); 5503 rc = bnxt_request_irq(bp); 5504 if (rc) { 5505 netdev_err(bp->dev, "bnxt_request_irq err: %x\n", rc); 5506 goto open_err; 5507 } 5508 } 5509 5510 bnxt_enable_napi(bp); 5511 5512 rc = bnxt_init_nic(bp, irq_re_init); 5513 if (rc) { 5514 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc); 5515 goto open_err; 5516 } 5517 5518 if (link_re_init) { 5519 rc = bnxt_update_phy_setting(bp); 5520 if (rc) 5521 netdev_warn(bp->dev, "failed to update phy settings\n"); 5522 } 5523 5524 if (irq_re_init) 5525 udp_tunnel_get_rx_info(bp->dev); 5526 5527 set_bit(BNXT_STATE_OPEN, &bp->state); 5528 bnxt_enable_int(bp); 5529 /* Enable TX queues */ 5530 bnxt_tx_enable(bp); 5531 mod_timer(&bp->timer, jiffies + bp->current_interval); 5532 /* Poll link status and check for SFP+ module status */ 5533 bnxt_get_port_module_status(bp); 5534 5535 return 0; 5536 5537 open_err: 5538 bnxt_disable_napi(bp); 5539 bnxt_del_napi(bp); 5540 5541 open_err_free_mem: 5542 bnxt_free_skbs(bp); 5543 bnxt_free_irq(bp); 5544 bnxt_free_mem(bp, true); 5545 return rc; 5546 } 5547 5548 /* rtnl_lock held */ 5549 int bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init) 5550 { 5551 int rc = 0; 5552 5553 rc = __bnxt_open_nic(bp, irq_re_init, link_re_init); 5554 if (rc) { 5555 netdev_err(bp->dev, "nic open fail (rc: %x)\n", rc); 5556 dev_close(bp->dev); 5557 } 5558 return rc; 5559 } 5560 5561 static int bnxt_open(struct net_device *dev) 5562 { 5563 struct bnxt *bp = netdev_priv(dev); 5564 int rc = 0; 5565 5566 if (!test_bit(BNXT_STATE_FN_RST_DONE, &bp->state)) { 5567 rc = bnxt_hwrm_func_reset(bp); 5568 if (rc) { 5569 netdev_err(bp->dev, "hwrm chip reset failure rc: %x\n", 5570 rc); 5571 rc = -EBUSY; 5572 return rc; 5573 } 5574 /* Do func_reset during the 1st PF open only to prevent killing 5575 * the VFs when the PF is brought down and up. 5576 */ 5577 if (BNXT_PF(bp)) 5578 set_bit(BNXT_STATE_FN_RST_DONE, &bp->state); 5579 } 5580 return __bnxt_open_nic(bp, true, true); 5581 } 5582 5583 static void bnxt_disable_int_sync(struct bnxt *bp) 5584 { 5585 int i; 5586 5587 atomic_inc(&bp->intr_sem); 5588 if (!netif_running(bp->dev)) 5589 return; 5590 5591 bnxt_disable_int(bp); 5592 for (i = 0; i < bp->cp_nr_rings; i++) 5593 synchronize_irq(bp->irq_tbl[i].vector); 5594 } 5595 5596 int bnxt_close_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init) 5597 { 5598 int rc = 0; 5599 5600 #ifdef CONFIG_BNXT_SRIOV 5601 if (bp->sriov_cfg) { 5602 rc = wait_event_interruptible_timeout(bp->sriov_cfg_wait, 5603 !bp->sriov_cfg, 5604 BNXT_SRIOV_CFG_WAIT_TMO); 5605 if (rc) 5606 netdev_warn(bp->dev, "timeout waiting for SRIOV config operation to complete!\n"); 5607 } 5608 #endif 5609 /* Change device state to avoid TX queue wake up's */ 5610 bnxt_tx_disable(bp); 5611 5612 clear_bit(BNXT_STATE_OPEN, &bp->state); 5613 smp_mb__after_atomic(); 5614 while (test_bit(BNXT_STATE_IN_SP_TASK, &bp->state)) 5615 msleep(20); 5616 5617 /* Flush rings before disabling interrupts */ 5618 bnxt_shutdown_nic(bp, irq_re_init); 5619 5620 /* TODO CHIMP_FW: Link/PHY related cleanup if (link_re_init) */ 5621 5622 bnxt_disable_napi(bp); 5623 bnxt_disable_int_sync(bp); 5624 del_timer_sync(&bp->timer); 5625 bnxt_free_skbs(bp); 5626 5627 if (irq_re_init) { 5628 bnxt_free_irq(bp); 5629 bnxt_del_napi(bp); 5630 } 5631 bnxt_free_mem(bp, irq_re_init); 5632 return rc; 5633 } 5634 5635 static int bnxt_close(struct net_device *dev) 5636 { 5637 struct bnxt *bp = netdev_priv(dev); 5638 5639 bnxt_close_nic(bp, true, true); 5640 bnxt_hwrm_shutdown_link(bp); 5641 return 0; 5642 } 5643 5644 /* rtnl_lock held */ 5645 static int bnxt_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 5646 { 5647 switch (cmd) { 5648 case SIOCGMIIPHY: 5649 /* fallthru */ 5650 case SIOCGMIIREG: { 5651 if (!netif_running(dev)) 5652 return -EAGAIN; 5653 5654 return 0; 5655 } 5656 5657 case SIOCSMIIREG: 5658 if (!netif_running(dev)) 5659 return -EAGAIN; 5660 5661 return 0; 5662 5663 default: 5664 /* do nothing */ 5665 break; 5666 } 5667 return -EOPNOTSUPP; 5668 } 5669 5670 static struct rtnl_link_stats64 * 5671 bnxt_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) 5672 { 5673 u32 i; 5674 struct bnxt *bp = netdev_priv(dev); 5675 5676 memset(stats, 0, sizeof(struct rtnl_link_stats64)); 5677 5678 if (!bp->bnapi) 5679 return stats; 5680 5681 /* TODO check if we need to synchronize with bnxt_close path */ 5682 for (i = 0; i < bp->cp_nr_rings; i++) { 5683 struct bnxt_napi *bnapi = bp->bnapi[i]; 5684 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 5685 struct ctx_hw_stats *hw_stats = cpr->hw_stats; 5686 5687 stats->rx_packets += le64_to_cpu(hw_stats->rx_ucast_pkts); 5688 stats->rx_packets += le64_to_cpu(hw_stats->rx_mcast_pkts); 5689 stats->rx_packets += le64_to_cpu(hw_stats->rx_bcast_pkts); 5690 5691 stats->tx_packets += le64_to_cpu(hw_stats->tx_ucast_pkts); 5692 stats->tx_packets += le64_to_cpu(hw_stats->tx_mcast_pkts); 5693 stats->tx_packets += le64_to_cpu(hw_stats->tx_bcast_pkts); 5694 5695 stats->rx_bytes += le64_to_cpu(hw_stats->rx_ucast_bytes); 5696 stats->rx_bytes += le64_to_cpu(hw_stats->rx_mcast_bytes); 5697 stats->rx_bytes += le64_to_cpu(hw_stats->rx_bcast_bytes); 5698 5699 stats->tx_bytes += le64_to_cpu(hw_stats->tx_ucast_bytes); 5700 stats->tx_bytes += le64_to_cpu(hw_stats->tx_mcast_bytes); 5701 stats->tx_bytes += le64_to_cpu(hw_stats->tx_bcast_bytes); 5702 5703 stats->rx_missed_errors += 5704 le64_to_cpu(hw_stats->rx_discard_pkts); 5705 5706 stats->multicast += le64_to_cpu(hw_stats->rx_mcast_pkts); 5707 5708 stats->tx_dropped += le64_to_cpu(hw_stats->tx_drop_pkts); 5709 } 5710 5711 if (bp->flags & BNXT_FLAG_PORT_STATS) { 5712 struct rx_port_stats *rx = bp->hw_rx_port_stats; 5713 struct tx_port_stats *tx = bp->hw_tx_port_stats; 5714 5715 stats->rx_crc_errors = le64_to_cpu(rx->rx_fcs_err_frames); 5716 stats->rx_frame_errors = le64_to_cpu(rx->rx_align_err_frames); 5717 stats->rx_length_errors = le64_to_cpu(rx->rx_undrsz_frames) + 5718 le64_to_cpu(rx->rx_ovrsz_frames) + 5719 le64_to_cpu(rx->rx_runt_frames); 5720 stats->rx_errors = le64_to_cpu(rx->rx_false_carrier_frames) + 5721 le64_to_cpu(rx->rx_jbr_frames); 5722 stats->collisions = le64_to_cpu(tx->tx_total_collisions); 5723 stats->tx_fifo_errors = le64_to_cpu(tx->tx_fifo_underruns); 5724 stats->tx_errors = le64_to_cpu(tx->tx_err); 5725 } 5726 5727 return stats; 5728 } 5729 5730 static bool bnxt_mc_list_updated(struct bnxt *bp, u32 *rx_mask) 5731 { 5732 struct net_device *dev = bp->dev; 5733 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 5734 struct netdev_hw_addr *ha; 5735 u8 *haddr; 5736 int mc_count = 0; 5737 bool update = false; 5738 int off = 0; 5739 5740 netdev_for_each_mc_addr(ha, dev) { 5741 if (mc_count >= BNXT_MAX_MC_ADDRS) { 5742 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST; 5743 vnic->mc_list_count = 0; 5744 return false; 5745 } 5746 haddr = ha->addr; 5747 if (!ether_addr_equal(haddr, vnic->mc_list + off)) { 5748 memcpy(vnic->mc_list + off, haddr, ETH_ALEN); 5749 update = true; 5750 } 5751 off += ETH_ALEN; 5752 mc_count++; 5753 } 5754 if (mc_count) 5755 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_MCAST; 5756 5757 if (mc_count != vnic->mc_list_count) { 5758 vnic->mc_list_count = mc_count; 5759 update = true; 5760 } 5761 return update; 5762 } 5763 5764 static bool bnxt_uc_list_updated(struct bnxt *bp) 5765 { 5766 struct net_device *dev = bp->dev; 5767 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 5768 struct netdev_hw_addr *ha; 5769 int off = 0; 5770 5771 if (netdev_uc_count(dev) != (vnic->uc_filter_count - 1)) 5772 return true; 5773 5774 netdev_for_each_uc_addr(ha, dev) { 5775 if (!ether_addr_equal(ha->addr, vnic->uc_list + off)) 5776 return true; 5777 5778 off += ETH_ALEN; 5779 } 5780 return false; 5781 } 5782 5783 static void bnxt_set_rx_mode(struct net_device *dev) 5784 { 5785 struct bnxt *bp = netdev_priv(dev); 5786 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 5787 u32 mask = vnic->rx_mask; 5788 bool mc_update = false; 5789 bool uc_update; 5790 5791 if (!netif_running(dev)) 5792 return; 5793 5794 mask &= ~(CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS | 5795 CFA_L2_SET_RX_MASK_REQ_MASK_MCAST | 5796 CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST); 5797 5798 if ((dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp)) 5799 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS; 5800 5801 uc_update = bnxt_uc_list_updated(bp); 5802 5803 if (dev->flags & IFF_ALLMULTI) { 5804 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST; 5805 vnic->mc_list_count = 0; 5806 } else { 5807 mc_update = bnxt_mc_list_updated(bp, &mask); 5808 } 5809 5810 if (mask != vnic->rx_mask || uc_update || mc_update) { 5811 vnic->rx_mask = mask; 5812 5813 set_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event); 5814 schedule_work(&bp->sp_task); 5815 } 5816 } 5817 5818 static int bnxt_cfg_rx_mode(struct bnxt *bp) 5819 { 5820 struct net_device *dev = bp->dev; 5821 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 5822 struct netdev_hw_addr *ha; 5823 int i, off = 0, rc; 5824 bool uc_update; 5825 5826 netif_addr_lock_bh(dev); 5827 uc_update = bnxt_uc_list_updated(bp); 5828 netif_addr_unlock_bh(dev); 5829 5830 if (!uc_update) 5831 goto skip_uc; 5832 5833 mutex_lock(&bp->hwrm_cmd_lock); 5834 for (i = 1; i < vnic->uc_filter_count; i++) { 5835 struct hwrm_cfa_l2_filter_free_input req = {0}; 5836 5837 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_FREE, -1, 5838 -1); 5839 5840 req.l2_filter_id = vnic->fw_l2_filter_id[i]; 5841 5842 rc = _hwrm_send_message(bp, &req, sizeof(req), 5843 HWRM_CMD_TIMEOUT); 5844 } 5845 mutex_unlock(&bp->hwrm_cmd_lock); 5846 5847 vnic->uc_filter_count = 1; 5848 5849 netif_addr_lock_bh(dev); 5850 if (netdev_uc_count(dev) > (BNXT_MAX_UC_ADDRS - 1)) { 5851 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS; 5852 } else { 5853 netdev_for_each_uc_addr(ha, dev) { 5854 memcpy(vnic->uc_list + off, ha->addr, ETH_ALEN); 5855 off += ETH_ALEN; 5856 vnic->uc_filter_count++; 5857 } 5858 } 5859 netif_addr_unlock_bh(dev); 5860 5861 for (i = 1, off = 0; i < vnic->uc_filter_count; i++, off += ETH_ALEN) { 5862 rc = bnxt_hwrm_set_vnic_filter(bp, 0, i, vnic->uc_list + off); 5863 if (rc) { 5864 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n", 5865 rc); 5866 vnic->uc_filter_count = i; 5867 return rc; 5868 } 5869 } 5870 5871 skip_uc: 5872 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0); 5873 if (rc) 5874 netdev_err(bp->dev, "HWRM cfa l2 rx mask failure rc: %x\n", 5875 rc); 5876 5877 return rc; 5878 } 5879 5880 static bool bnxt_rfs_capable(struct bnxt *bp) 5881 { 5882 #ifdef CONFIG_RFS_ACCEL 5883 struct bnxt_pf_info *pf = &bp->pf; 5884 int vnics; 5885 5886 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_MSIX_CAP)) 5887 return false; 5888 5889 vnics = 1 + bp->rx_nr_rings; 5890 if (vnics > pf->max_rsscos_ctxs || vnics > pf->max_vnics) { 5891 netdev_warn(bp->dev, 5892 "Not enough resources to support NTUPLE filters, enough resources for up to %d rx rings\n", 5893 min(pf->max_rsscos_ctxs - 1, pf->max_vnics - 1)); 5894 return false; 5895 } 5896 5897 return true; 5898 #else 5899 return false; 5900 #endif 5901 } 5902 5903 static netdev_features_t bnxt_fix_features(struct net_device *dev, 5904 netdev_features_t features) 5905 { 5906 struct bnxt *bp = netdev_priv(dev); 5907 5908 if ((features & NETIF_F_NTUPLE) && !bnxt_rfs_capable(bp)) 5909 features &= ~NETIF_F_NTUPLE; 5910 5911 /* Both CTAG and STAG VLAN accelaration on the RX side have to be 5912 * turned on or off together. 5913 */ 5914 if ((features & (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) != 5915 (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) { 5916 if (dev->features & NETIF_F_HW_VLAN_CTAG_RX) 5917 features &= ~(NETIF_F_HW_VLAN_CTAG_RX | 5918 NETIF_F_HW_VLAN_STAG_RX); 5919 else 5920 features |= NETIF_F_HW_VLAN_CTAG_RX | 5921 NETIF_F_HW_VLAN_STAG_RX; 5922 } 5923 #ifdef CONFIG_BNXT_SRIOV 5924 if (BNXT_VF(bp)) { 5925 if (bp->vf.vlan) { 5926 features &= ~(NETIF_F_HW_VLAN_CTAG_RX | 5927 NETIF_F_HW_VLAN_STAG_RX); 5928 } 5929 } 5930 #endif 5931 return features; 5932 } 5933 5934 static int bnxt_set_features(struct net_device *dev, netdev_features_t features) 5935 { 5936 struct bnxt *bp = netdev_priv(dev); 5937 u32 flags = bp->flags; 5938 u32 changes; 5939 int rc = 0; 5940 bool re_init = false; 5941 bool update_tpa = false; 5942 5943 flags &= ~BNXT_FLAG_ALL_CONFIG_FEATS; 5944 if ((features & NETIF_F_GRO) && !BNXT_CHIP_TYPE_NITRO_A0(bp)) 5945 flags |= BNXT_FLAG_GRO; 5946 if (features & NETIF_F_LRO) 5947 flags |= BNXT_FLAG_LRO; 5948 5949 if (features & NETIF_F_HW_VLAN_CTAG_RX) 5950 flags |= BNXT_FLAG_STRIP_VLAN; 5951 5952 if (features & NETIF_F_NTUPLE) 5953 flags |= BNXT_FLAG_RFS; 5954 5955 changes = flags ^ bp->flags; 5956 if (changes & BNXT_FLAG_TPA) { 5957 update_tpa = true; 5958 if ((bp->flags & BNXT_FLAG_TPA) == 0 || 5959 (flags & BNXT_FLAG_TPA) == 0) 5960 re_init = true; 5961 } 5962 5963 if (changes & ~BNXT_FLAG_TPA) 5964 re_init = true; 5965 5966 if (flags != bp->flags) { 5967 u32 old_flags = bp->flags; 5968 5969 bp->flags = flags; 5970 5971 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) { 5972 if (update_tpa) 5973 bnxt_set_ring_params(bp); 5974 return rc; 5975 } 5976 5977 if (re_init) { 5978 bnxt_close_nic(bp, false, false); 5979 if (update_tpa) 5980 bnxt_set_ring_params(bp); 5981 5982 return bnxt_open_nic(bp, false, false); 5983 } 5984 if (update_tpa) { 5985 rc = bnxt_set_tpa(bp, 5986 (flags & BNXT_FLAG_TPA) ? 5987 true : false); 5988 if (rc) 5989 bp->flags = old_flags; 5990 } 5991 } 5992 return rc; 5993 } 5994 5995 static void bnxt_dump_tx_sw_state(struct bnxt_napi *bnapi) 5996 { 5997 struct bnxt_tx_ring_info *txr = bnapi->tx_ring; 5998 int i = bnapi->index; 5999 6000 if (!txr) 6001 return; 6002 6003 netdev_info(bnapi->bp->dev, "[%d]: tx{fw_ring: %d prod: %x cons: %x}\n", 6004 i, txr->tx_ring_struct.fw_ring_id, txr->tx_prod, 6005 txr->tx_cons); 6006 } 6007 6008 static void bnxt_dump_rx_sw_state(struct bnxt_napi *bnapi) 6009 { 6010 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 6011 int i = bnapi->index; 6012 6013 if (!rxr) 6014 return; 6015 6016 netdev_info(bnapi->bp->dev, "[%d]: rx{fw_ring: %d prod: %x} rx_agg{fw_ring: %d agg_prod: %x sw_agg_prod: %x}\n", 6017 i, rxr->rx_ring_struct.fw_ring_id, rxr->rx_prod, 6018 rxr->rx_agg_ring_struct.fw_ring_id, rxr->rx_agg_prod, 6019 rxr->rx_sw_agg_prod); 6020 } 6021 6022 static void bnxt_dump_cp_sw_state(struct bnxt_napi *bnapi) 6023 { 6024 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 6025 int i = bnapi->index; 6026 6027 netdev_info(bnapi->bp->dev, "[%d]: cp{fw_ring: %d raw_cons: %x}\n", 6028 i, cpr->cp_ring_struct.fw_ring_id, cpr->cp_raw_cons); 6029 } 6030 6031 static void bnxt_dbg_dump_states(struct bnxt *bp) 6032 { 6033 int i; 6034 struct bnxt_napi *bnapi; 6035 6036 for (i = 0; i < bp->cp_nr_rings; i++) { 6037 bnapi = bp->bnapi[i]; 6038 if (netif_msg_drv(bp)) { 6039 bnxt_dump_tx_sw_state(bnapi); 6040 bnxt_dump_rx_sw_state(bnapi); 6041 bnxt_dump_cp_sw_state(bnapi); 6042 } 6043 } 6044 } 6045 6046 static void bnxt_reset_task(struct bnxt *bp, bool silent) 6047 { 6048 if (!silent) 6049 bnxt_dbg_dump_states(bp); 6050 if (netif_running(bp->dev)) { 6051 bnxt_close_nic(bp, false, false); 6052 bnxt_open_nic(bp, false, false); 6053 } 6054 } 6055 6056 static void bnxt_tx_timeout(struct net_device *dev) 6057 { 6058 struct bnxt *bp = netdev_priv(dev); 6059 6060 netdev_err(bp->dev, "TX timeout detected, starting reset task!\n"); 6061 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event); 6062 schedule_work(&bp->sp_task); 6063 } 6064 6065 #ifdef CONFIG_NET_POLL_CONTROLLER 6066 static void bnxt_poll_controller(struct net_device *dev) 6067 { 6068 struct bnxt *bp = netdev_priv(dev); 6069 int i; 6070 6071 for (i = 0; i < bp->cp_nr_rings; i++) { 6072 struct bnxt_irq *irq = &bp->irq_tbl[i]; 6073 6074 disable_irq(irq->vector); 6075 irq->handler(irq->vector, bp->bnapi[i]); 6076 enable_irq(irq->vector); 6077 } 6078 } 6079 #endif 6080 6081 static void bnxt_timer(unsigned long data) 6082 { 6083 struct bnxt *bp = (struct bnxt *)data; 6084 struct net_device *dev = bp->dev; 6085 6086 if (!netif_running(dev)) 6087 return; 6088 6089 if (atomic_read(&bp->intr_sem) != 0) 6090 goto bnxt_restart_timer; 6091 6092 if (bp->link_info.link_up && (bp->flags & BNXT_FLAG_PORT_STATS)) { 6093 set_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event); 6094 schedule_work(&bp->sp_task); 6095 } 6096 bnxt_restart_timer: 6097 mod_timer(&bp->timer, jiffies + bp->current_interval); 6098 } 6099 6100 /* Only called from bnxt_sp_task() */ 6101 static void bnxt_reset(struct bnxt *bp, bool silent) 6102 { 6103 /* bnxt_reset_task() calls bnxt_close_nic() which waits 6104 * for BNXT_STATE_IN_SP_TASK to clear. 6105 * If there is a parallel dev_close(), bnxt_close() may be holding 6106 * rtnl() and waiting for BNXT_STATE_IN_SP_TASK to clear. So we 6107 * must clear BNXT_STATE_IN_SP_TASK before holding rtnl(). 6108 */ 6109 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state); 6110 rtnl_lock(); 6111 if (test_bit(BNXT_STATE_OPEN, &bp->state)) 6112 bnxt_reset_task(bp, silent); 6113 set_bit(BNXT_STATE_IN_SP_TASK, &bp->state); 6114 rtnl_unlock(); 6115 } 6116 6117 static void bnxt_cfg_ntp_filters(struct bnxt *); 6118 6119 static void bnxt_sp_task(struct work_struct *work) 6120 { 6121 struct bnxt *bp = container_of(work, struct bnxt, sp_task); 6122 int rc; 6123 6124 set_bit(BNXT_STATE_IN_SP_TASK, &bp->state); 6125 smp_mb__after_atomic(); 6126 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) { 6127 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state); 6128 return; 6129 } 6130 6131 if (test_and_clear_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event)) 6132 bnxt_cfg_rx_mode(bp); 6133 6134 if (test_and_clear_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event)) 6135 bnxt_cfg_ntp_filters(bp); 6136 if (test_and_clear_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event)) { 6137 if (test_and_clear_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT, 6138 &bp->sp_event)) 6139 bnxt_hwrm_phy_qcaps(bp); 6140 6141 rc = bnxt_update_link(bp, true); 6142 if (rc) 6143 netdev_err(bp->dev, "SP task can't update link (rc: %x)\n", 6144 rc); 6145 } 6146 if (test_and_clear_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event)) 6147 bnxt_hwrm_exec_fwd_req(bp); 6148 if (test_and_clear_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event)) { 6149 bnxt_hwrm_tunnel_dst_port_alloc( 6150 bp, bp->vxlan_port, 6151 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN); 6152 } 6153 if (test_and_clear_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event)) { 6154 bnxt_hwrm_tunnel_dst_port_free( 6155 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN); 6156 } 6157 if (test_and_clear_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event)) { 6158 bnxt_hwrm_tunnel_dst_port_alloc( 6159 bp, bp->nge_port, 6160 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE); 6161 } 6162 if (test_and_clear_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event)) { 6163 bnxt_hwrm_tunnel_dst_port_free( 6164 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE); 6165 } 6166 if (test_and_clear_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event)) 6167 bnxt_reset(bp, false); 6168 6169 if (test_and_clear_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event)) 6170 bnxt_reset(bp, true); 6171 6172 if (test_and_clear_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event)) 6173 bnxt_get_port_module_status(bp); 6174 6175 if (test_and_clear_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event)) 6176 bnxt_hwrm_port_qstats(bp); 6177 6178 smp_mb__before_atomic(); 6179 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state); 6180 } 6181 6182 static int bnxt_init_board(struct pci_dev *pdev, struct net_device *dev) 6183 { 6184 int rc; 6185 struct bnxt *bp = netdev_priv(dev); 6186 6187 SET_NETDEV_DEV(dev, &pdev->dev); 6188 6189 /* enable device (incl. PCI PM wakeup), and bus-mastering */ 6190 rc = pci_enable_device(pdev); 6191 if (rc) { 6192 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n"); 6193 goto init_err; 6194 } 6195 6196 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 6197 dev_err(&pdev->dev, 6198 "Cannot find PCI device base address, aborting\n"); 6199 rc = -ENODEV; 6200 goto init_err_disable; 6201 } 6202 6203 rc = pci_request_regions(pdev, DRV_MODULE_NAME); 6204 if (rc) { 6205 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n"); 6206 goto init_err_disable; 6207 } 6208 6209 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) != 0 && 6210 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)) != 0) { 6211 dev_err(&pdev->dev, "System does not support DMA, aborting\n"); 6212 goto init_err_disable; 6213 } 6214 6215 pci_set_master(pdev); 6216 6217 bp->dev = dev; 6218 bp->pdev = pdev; 6219 6220 bp->bar0 = pci_ioremap_bar(pdev, 0); 6221 if (!bp->bar0) { 6222 dev_err(&pdev->dev, "Cannot map device registers, aborting\n"); 6223 rc = -ENOMEM; 6224 goto init_err_release; 6225 } 6226 6227 bp->bar1 = pci_ioremap_bar(pdev, 2); 6228 if (!bp->bar1) { 6229 dev_err(&pdev->dev, "Cannot map doorbell registers, aborting\n"); 6230 rc = -ENOMEM; 6231 goto init_err_release; 6232 } 6233 6234 bp->bar2 = pci_ioremap_bar(pdev, 4); 6235 if (!bp->bar2) { 6236 dev_err(&pdev->dev, "Cannot map bar4 registers, aborting\n"); 6237 rc = -ENOMEM; 6238 goto init_err_release; 6239 } 6240 6241 pci_enable_pcie_error_reporting(pdev); 6242 6243 INIT_WORK(&bp->sp_task, bnxt_sp_task); 6244 6245 spin_lock_init(&bp->ntp_fltr_lock); 6246 6247 bp->rx_ring_size = BNXT_DEFAULT_RX_RING_SIZE; 6248 bp->tx_ring_size = BNXT_DEFAULT_TX_RING_SIZE; 6249 6250 /* tick values in micro seconds */ 6251 bp->rx_coal_ticks = 12; 6252 bp->rx_coal_bufs = 30; 6253 bp->rx_coal_ticks_irq = 1; 6254 bp->rx_coal_bufs_irq = 2; 6255 6256 bp->tx_coal_ticks = 25; 6257 bp->tx_coal_bufs = 30; 6258 bp->tx_coal_ticks_irq = 2; 6259 bp->tx_coal_bufs_irq = 2; 6260 6261 bp->stats_coal_ticks = BNXT_DEF_STATS_COAL_TICKS; 6262 6263 init_timer(&bp->timer); 6264 bp->timer.data = (unsigned long)bp; 6265 bp->timer.function = bnxt_timer; 6266 bp->current_interval = BNXT_TIMER_INTERVAL; 6267 6268 clear_bit(BNXT_STATE_OPEN, &bp->state); 6269 6270 return 0; 6271 6272 init_err_release: 6273 if (bp->bar2) { 6274 pci_iounmap(pdev, bp->bar2); 6275 bp->bar2 = NULL; 6276 } 6277 6278 if (bp->bar1) { 6279 pci_iounmap(pdev, bp->bar1); 6280 bp->bar1 = NULL; 6281 } 6282 6283 if (bp->bar0) { 6284 pci_iounmap(pdev, bp->bar0); 6285 bp->bar0 = NULL; 6286 } 6287 6288 pci_release_regions(pdev); 6289 6290 init_err_disable: 6291 pci_disable_device(pdev); 6292 6293 init_err: 6294 return rc; 6295 } 6296 6297 /* rtnl_lock held */ 6298 static int bnxt_change_mac_addr(struct net_device *dev, void *p) 6299 { 6300 struct sockaddr *addr = p; 6301 struct bnxt *bp = netdev_priv(dev); 6302 int rc = 0; 6303 6304 if (!is_valid_ether_addr(addr->sa_data)) 6305 return -EADDRNOTAVAIL; 6306 6307 rc = bnxt_approve_mac(bp, addr->sa_data); 6308 if (rc) 6309 return rc; 6310 6311 if (ether_addr_equal(addr->sa_data, dev->dev_addr)) 6312 return 0; 6313 6314 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); 6315 if (netif_running(dev)) { 6316 bnxt_close_nic(bp, false, false); 6317 rc = bnxt_open_nic(bp, false, false); 6318 } 6319 6320 return rc; 6321 } 6322 6323 /* rtnl_lock held */ 6324 static int bnxt_change_mtu(struct net_device *dev, int new_mtu) 6325 { 6326 struct bnxt *bp = netdev_priv(dev); 6327 6328 if (netif_running(dev)) 6329 bnxt_close_nic(bp, false, false); 6330 6331 dev->mtu = new_mtu; 6332 bnxt_set_ring_params(bp); 6333 6334 if (netif_running(dev)) 6335 return bnxt_open_nic(bp, false, false); 6336 6337 return 0; 6338 } 6339 6340 static int bnxt_setup_tc(struct net_device *dev, u32 handle, __be16 proto, 6341 struct tc_to_netdev *ntc) 6342 { 6343 struct bnxt *bp = netdev_priv(dev); 6344 bool sh = false; 6345 u8 tc; 6346 6347 if (ntc->type != TC_SETUP_MQPRIO) 6348 return -EINVAL; 6349 6350 tc = ntc->tc; 6351 6352 if (tc > bp->max_tc) { 6353 netdev_err(dev, "too many traffic classes requested: %d Max supported is %d\n", 6354 tc, bp->max_tc); 6355 return -EINVAL; 6356 } 6357 6358 if (netdev_get_num_tc(dev) == tc) 6359 return 0; 6360 6361 if (bp->flags & BNXT_FLAG_SHARED_RINGS) 6362 sh = true; 6363 6364 if (tc) { 6365 int max_rx_rings, max_tx_rings, rc; 6366 6367 rc = bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, sh); 6368 if (rc || bp->tx_nr_rings_per_tc * tc > max_tx_rings) 6369 return -ENOMEM; 6370 } 6371 6372 /* Needs to close the device and do hw resource re-allocations */ 6373 if (netif_running(bp->dev)) 6374 bnxt_close_nic(bp, true, false); 6375 6376 if (tc) { 6377 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tc; 6378 netdev_set_num_tc(dev, tc); 6379 } else { 6380 bp->tx_nr_rings = bp->tx_nr_rings_per_tc; 6381 netdev_reset_tc(dev); 6382 } 6383 bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) : 6384 bp->tx_nr_rings + bp->rx_nr_rings; 6385 bp->num_stat_ctxs = bp->cp_nr_rings; 6386 6387 if (netif_running(bp->dev)) 6388 return bnxt_open_nic(bp, true, false); 6389 6390 return 0; 6391 } 6392 6393 #ifdef CONFIG_RFS_ACCEL 6394 static bool bnxt_fltr_match(struct bnxt_ntuple_filter *f1, 6395 struct bnxt_ntuple_filter *f2) 6396 { 6397 struct flow_keys *keys1 = &f1->fkeys; 6398 struct flow_keys *keys2 = &f2->fkeys; 6399 6400 if (keys1->addrs.v4addrs.src == keys2->addrs.v4addrs.src && 6401 keys1->addrs.v4addrs.dst == keys2->addrs.v4addrs.dst && 6402 keys1->ports.ports == keys2->ports.ports && 6403 keys1->basic.ip_proto == keys2->basic.ip_proto && 6404 keys1->basic.n_proto == keys2->basic.n_proto && 6405 ether_addr_equal(f1->src_mac_addr, f2->src_mac_addr) && 6406 ether_addr_equal(f1->dst_mac_addr, f2->dst_mac_addr)) 6407 return true; 6408 6409 return false; 6410 } 6411 6412 static int bnxt_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb, 6413 u16 rxq_index, u32 flow_id) 6414 { 6415 struct bnxt *bp = netdev_priv(dev); 6416 struct bnxt_ntuple_filter *fltr, *new_fltr; 6417 struct flow_keys *fkeys; 6418 struct ethhdr *eth = (struct ethhdr *)skb_mac_header(skb); 6419 int rc = 0, idx, bit_id, l2_idx = 0; 6420 struct hlist_head *head; 6421 6422 if (skb->encapsulation) 6423 return -EPROTONOSUPPORT; 6424 6425 if (!ether_addr_equal(dev->dev_addr, eth->h_dest)) { 6426 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 6427 int off = 0, j; 6428 6429 netif_addr_lock_bh(dev); 6430 for (j = 0; j < vnic->uc_filter_count; j++, off += ETH_ALEN) { 6431 if (ether_addr_equal(eth->h_dest, 6432 vnic->uc_list + off)) { 6433 l2_idx = j + 1; 6434 break; 6435 } 6436 } 6437 netif_addr_unlock_bh(dev); 6438 if (!l2_idx) 6439 return -EINVAL; 6440 } 6441 new_fltr = kzalloc(sizeof(*new_fltr), GFP_ATOMIC); 6442 if (!new_fltr) 6443 return -ENOMEM; 6444 6445 fkeys = &new_fltr->fkeys; 6446 if (!skb_flow_dissect_flow_keys(skb, fkeys, 0)) { 6447 rc = -EPROTONOSUPPORT; 6448 goto err_free; 6449 } 6450 6451 if ((fkeys->basic.n_proto != htons(ETH_P_IP)) || 6452 ((fkeys->basic.ip_proto != IPPROTO_TCP) && 6453 (fkeys->basic.ip_proto != IPPROTO_UDP))) { 6454 rc = -EPROTONOSUPPORT; 6455 goto err_free; 6456 } 6457 6458 memcpy(new_fltr->dst_mac_addr, eth->h_dest, ETH_ALEN); 6459 memcpy(new_fltr->src_mac_addr, eth->h_source, ETH_ALEN); 6460 6461 idx = skb_get_hash_raw(skb) & BNXT_NTP_FLTR_HASH_MASK; 6462 head = &bp->ntp_fltr_hash_tbl[idx]; 6463 rcu_read_lock(); 6464 hlist_for_each_entry_rcu(fltr, head, hash) { 6465 if (bnxt_fltr_match(fltr, new_fltr)) { 6466 rcu_read_unlock(); 6467 rc = 0; 6468 goto err_free; 6469 } 6470 } 6471 rcu_read_unlock(); 6472 6473 spin_lock_bh(&bp->ntp_fltr_lock); 6474 bit_id = bitmap_find_free_region(bp->ntp_fltr_bmap, 6475 BNXT_NTP_FLTR_MAX_FLTR, 0); 6476 if (bit_id < 0) { 6477 spin_unlock_bh(&bp->ntp_fltr_lock); 6478 rc = -ENOMEM; 6479 goto err_free; 6480 } 6481 6482 new_fltr->sw_id = (u16)bit_id; 6483 new_fltr->flow_id = flow_id; 6484 new_fltr->l2_fltr_idx = l2_idx; 6485 new_fltr->rxq = rxq_index; 6486 hlist_add_head_rcu(&new_fltr->hash, head); 6487 bp->ntp_fltr_count++; 6488 spin_unlock_bh(&bp->ntp_fltr_lock); 6489 6490 set_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event); 6491 schedule_work(&bp->sp_task); 6492 6493 return new_fltr->sw_id; 6494 6495 err_free: 6496 kfree(new_fltr); 6497 return rc; 6498 } 6499 6500 static void bnxt_cfg_ntp_filters(struct bnxt *bp) 6501 { 6502 int i; 6503 6504 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) { 6505 struct hlist_head *head; 6506 struct hlist_node *tmp; 6507 struct bnxt_ntuple_filter *fltr; 6508 int rc; 6509 6510 head = &bp->ntp_fltr_hash_tbl[i]; 6511 hlist_for_each_entry_safe(fltr, tmp, head, hash) { 6512 bool del = false; 6513 6514 if (test_bit(BNXT_FLTR_VALID, &fltr->state)) { 6515 if (rps_may_expire_flow(bp->dev, fltr->rxq, 6516 fltr->flow_id, 6517 fltr->sw_id)) { 6518 bnxt_hwrm_cfa_ntuple_filter_free(bp, 6519 fltr); 6520 del = true; 6521 } 6522 } else { 6523 rc = bnxt_hwrm_cfa_ntuple_filter_alloc(bp, 6524 fltr); 6525 if (rc) 6526 del = true; 6527 else 6528 set_bit(BNXT_FLTR_VALID, &fltr->state); 6529 } 6530 6531 if (del) { 6532 spin_lock_bh(&bp->ntp_fltr_lock); 6533 hlist_del_rcu(&fltr->hash); 6534 bp->ntp_fltr_count--; 6535 spin_unlock_bh(&bp->ntp_fltr_lock); 6536 synchronize_rcu(); 6537 clear_bit(fltr->sw_id, bp->ntp_fltr_bmap); 6538 kfree(fltr); 6539 } 6540 } 6541 } 6542 if (test_and_clear_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event)) 6543 netdev_info(bp->dev, "Receive PF driver unload event!"); 6544 } 6545 6546 #else 6547 6548 static void bnxt_cfg_ntp_filters(struct bnxt *bp) 6549 { 6550 } 6551 6552 #endif /* CONFIG_RFS_ACCEL */ 6553 6554 static void bnxt_udp_tunnel_add(struct net_device *dev, 6555 struct udp_tunnel_info *ti) 6556 { 6557 struct bnxt *bp = netdev_priv(dev); 6558 6559 if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET) 6560 return; 6561 6562 if (!netif_running(dev)) 6563 return; 6564 6565 switch (ti->type) { 6566 case UDP_TUNNEL_TYPE_VXLAN: 6567 if (bp->vxlan_port_cnt && bp->vxlan_port != ti->port) 6568 return; 6569 6570 bp->vxlan_port_cnt++; 6571 if (bp->vxlan_port_cnt == 1) { 6572 bp->vxlan_port = ti->port; 6573 set_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event); 6574 schedule_work(&bp->sp_task); 6575 } 6576 break; 6577 case UDP_TUNNEL_TYPE_GENEVE: 6578 if (bp->nge_port_cnt && bp->nge_port != ti->port) 6579 return; 6580 6581 bp->nge_port_cnt++; 6582 if (bp->nge_port_cnt == 1) { 6583 bp->nge_port = ti->port; 6584 set_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event); 6585 } 6586 break; 6587 default: 6588 return; 6589 } 6590 6591 schedule_work(&bp->sp_task); 6592 } 6593 6594 static void bnxt_udp_tunnel_del(struct net_device *dev, 6595 struct udp_tunnel_info *ti) 6596 { 6597 struct bnxt *bp = netdev_priv(dev); 6598 6599 if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET) 6600 return; 6601 6602 if (!netif_running(dev)) 6603 return; 6604 6605 switch (ti->type) { 6606 case UDP_TUNNEL_TYPE_VXLAN: 6607 if (!bp->vxlan_port_cnt || bp->vxlan_port != ti->port) 6608 return; 6609 bp->vxlan_port_cnt--; 6610 6611 if (bp->vxlan_port_cnt != 0) 6612 return; 6613 6614 set_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event); 6615 break; 6616 case UDP_TUNNEL_TYPE_GENEVE: 6617 if (!bp->nge_port_cnt || bp->nge_port != ti->port) 6618 return; 6619 bp->nge_port_cnt--; 6620 6621 if (bp->nge_port_cnt != 0) 6622 return; 6623 6624 set_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event); 6625 break; 6626 default: 6627 return; 6628 } 6629 6630 schedule_work(&bp->sp_task); 6631 } 6632 6633 static const struct net_device_ops bnxt_netdev_ops = { 6634 .ndo_open = bnxt_open, 6635 .ndo_start_xmit = bnxt_start_xmit, 6636 .ndo_stop = bnxt_close, 6637 .ndo_get_stats64 = bnxt_get_stats64, 6638 .ndo_set_rx_mode = bnxt_set_rx_mode, 6639 .ndo_do_ioctl = bnxt_ioctl, 6640 .ndo_validate_addr = eth_validate_addr, 6641 .ndo_set_mac_address = bnxt_change_mac_addr, 6642 .ndo_change_mtu = bnxt_change_mtu, 6643 .ndo_fix_features = bnxt_fix_features, 6644 .ndo_set_features = bnxt_set_features, 6645 .ndo_tx_timeout = bnxt_tx_timeout, 6646 #ifdef CONFIG_BNXT_SRIOV 6647 .ndo_get_vf_config = bnxt_get_vf_config, 6648 .ndo_set_vf_mac = bnxt_set_vf_mac, 6649 .ndo_set_vf_vlan = bnxt_set_vf_vlan, 6650 .ndo_set_vf_rate = bnxt_set_vf_bw, 6651 .ndo_set_vf_link_state = bnxt_set_vf_link_state, 6652 .ndo_set_vf_spoofchk = bnxt_set_vf_spoofchk, 6653 #endif 6654 #ifdef CONFIG_NET_POLL_CONTROLLER 6655 .ndo_poll_controller = bnxt_poll_controller, 6656 #endif 6657 .ndo_setup_tc = bnxt_setup_tc, 6658 #ifdef CONFIG_RFS_ACCEL 6659 .ndo_rx_flow_steer = bnxt_rx_flow_steer, 6660 #endif 6661 .ndo_udp_tunnel_add = bnxt_udp_tunnel_add, 6662 .ndo_udp_tunnel_del = bnxt_udp_tunnel_del, 6663 #ifdef CONFIG_NET_RX_BUSY_POLL 6664 .ndo_busy_poll = bnxt_busy_poll, 6665 #endif 6666 }; 6667 6668 static void bnxt_remove_one(struct pci_dev *pdev) 6669 { 6670 struct net_device *dev = pci_get_drvdata(pdev); 6671 struct bnxt *bp = netdev_priv(dev); 6672 6673 if (BNXT_PF(bp)) 6674 bnxt_sriov_disable(bp); 6675 6676 pci_disable_pcie_error_reporting(pdev); 6677 unregister_netdev(dev); 6678 cancel_work_sync(&bp->sp_task); 6679 bp->sp_event = 0; 6680 6681 bnxt_hwrm_func_drv_unrgtr(bp); 6682 bnxt_free_hwrm_resources(bp); 6683 pci_iounmap(pdev, bp->bar2); 6684 pci_iounmap(pdev, bp->bar1); 6685 pci_iounmap(pdev, bp->bar0); 6686 free_netdev(dev); 6687 6688 pci_release_regions(pdev); 6689 pci_disable_device(pdev); 6690 } 6691 6692 static int bnxt_probe_phy(struct bnxt *bp) 6693 { 6694 int rc = 0; 6695 struct bnxt_link_info *link_info = &bp->link_info; 6696 6697 rc = bnxt_hwrm_phy_qcaps(bp); 6698 if (rc) { 6699 netdev_err(bp->dev, "Probe phy can't get phy capabilities (rc: %x)\n", 6700 rc); 6701 return rc; 6702 } 6703 6704 rc = bnxt_update_link(bp, false); 6705 if (rc) { 6706 netdev_err(bp->dev, "Probe phy can't update link (rc: %x)\n", 6707 rc); 6708 return rc; 6709 } 6710 6711 /* Older firmware does not have supported_auto_speeds, so assume 6712 * that all supported speeds can be autonegotiated. 6713 */ 6714 if (link_info->auto_link_speeds && !link_info->support_auto_speeds) 6715 link_info->support_auto_speeds = link_info->support_speeds; 6716 6717 /*initialize the ethool setting copy with NVM settings */ 6718 if (BNXT_AUTO_MODE(link_info->auto_mode)) { 6719 link_info->autoneg = BNXT_AUTONEG_SPEED; 6720 if (bp->hwrm_spec_code >= 0x10201) { 6721 if (link_info->auto_pause_setting & 6722 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE) 6723 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL; 6724 } else { 6725 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL; 6726 } 6727 link_info->advertising = link_info->auto_link_speeds; 6728 } else { 6729 link_info->req_link_speed = link_info->force_link_speed; 6730 link_info->req_duplex = link_info->duplex_setting; 6731 } 6732 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) 6733 link_info->req_flow_ctrl = 6734 link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH; 6735 else 6736 link_info->req_flow_ctrl = link_info->force_pause_setting; 6737 return rc; 6738 } 6739 6740 static int bnxt_get_max_irq(struct pci_dev *pdev) 6741 { 6742 u16 ctrl; 6743 6744 if (!pdev->msix_cap) 6745 return 1; 6746 6747 pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &ctrl); 6748 return (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1; 6749 } 6750 6751 static void _bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx, 6752 int *max_cp) 6753 { 6754 int max_ring_grps = 0; 6755 6756 #ifdef CONFIG_BNXT_SRIOV 6757 if (!BNXT_PF(bp)) { 6758 *max_tx = bp->vf.max_tx_rings; 6759 *max_rx = bp->vf.max_rx_rings; 6760 *max_cp = min_t(int, bp->vf.max_irqs, bp->vf.max_cp_rings); 6761 *max_cp = min_t(int, *max_cp, bp->vf.max_stat_ctxs); 6762 max_ring_grps = bp->vf.max_hw_ring_grps; 6763 } else 6764 #endif 6765 { 6766 *max_tx = bp->pf.max_tx_rings; 6767 *max_rx = bp->pf.max_rx_rings; 6768 *max_cp = min_t(int, bp->pf.max_irqs, bp->pf.max_cp_rings); 6769 *max_cp = min_t(int, *max_cp, bp->pf.max_stat_ctxs); 6770 max_ring_grps = bp->pf.max_hw_ring_grps; 6771 } 6772 if (BNXT_CHIP_TYPE_NITRO_A0(bp) && BNXT_PF(bp)) { 6773 *max_cp -= 1; 6774 *max_rx -= 2; 6775 } 6776 if (bp->flags & BNXT_FLAG_AGG_RINGS) 6777 *max_rx >>= 1; 6778 *max_rx = min_t(int, *max_rx, max_ring_grps); 6779 } 6780 6781 int bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx, bool shared) 6782 { 6783 int rx, tx, cp; 6784 6785 _bnxt_get_max_rings(bp, &rx, &tx, &cp); 6786 if (!rx || !tx || !cp) 6787 return -ENOMEM; 6788 6789 *max_rx = rx; 6790 *max_tx = tx; 6791 return bnxt_trim_rings(bp, max_rx, max_tx, cp, shared); 6792 } 6793 6794 static int bnxt_set_dflt_rings(struct bnxt *bp) 6795 { 6796 int dflt_rings, max_rx_rings, max_tx_rings, rc; 6797 bool sh = true; 6798 6799 if (sh) 6800 bp->flags |= BNXT_FLAG_SHARED_RINGS; 6801 dflt_rings = netif_get_num_default_rss_queues(); 6802 rc = bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, sh); 6803 if (rc) 6804 return rc; 6805 bp->rx_nr_rings = min_t(int, dflt_rings, max_rx_rings); 6806 bp->tx_nr_rings_per_tc = min_t(int, dflt_rings, max_tx_rings); 6807 bp->tx_nr_rings = bp->tx_nr_rings_per_tc; 6808 bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) : 6809 bp->tx_nr_rings + bp->rx_nr_rings; 6810 bp->num_stat_ctxs = bp->cp_nr_rings; 6811 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) { 6812 bp->rx_nr_rings++; 6813 bp->cp_nr_rings++; 6814 } 6815 return rc; 6816 } 6817 6818 static void bnxt_parse_log_pcie_link(struct bnxt *bp) 6819 { 6820 enum pcie_link_width width = PCIE_LNK_WIDTH_UNKNOWN; 6821 enum pci_bus_speed speed = PCI_SPEED_UNKNOWN; 6822 6823 if (pcie_get_minimum_link(bp->pdev, &speed, &width) || 6824 speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN) 6825 netdev_info(bp->dev, "Failed to determine PCIe Link Info\n"); 6826 else 6827 netdev_info(bp->dev, "PCIe: Speed %s Width x%d\n", 6828 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" : 6829 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" : 6830 speed == PCIE_SPEED_8_0GT ? "8.0GT/s" : 6831 "Unknown", width); 6832 } 6833 6834 static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 6835 { 6836 static int version_printed; 6837 struct net_device *dev; 6838 struct bnxt *bp; 6839 int rc, max_irqs; 6840 6841 if (pdev->device == 0x16cd && pci_is_bridge(pdev)) 6842 return -ENODEV; 6843 6844 if (version_printed++ == 0) 6845 pr_info("%s", version); 6846 6847 max_irqs = bnxt_get_max_irq(pdev); 6848 dev = alloc_etherdev_mq(sizeof(*bp), max_irqs); 6849 if (!dev) 6850 return -ENOMEM; 6851 6852 bp = netdev_priv(dev); 6853 6854 if (bnxt_vf_pciid(ent->driver_data)) 6855 bp->flags |= BNXT_FLAG_VF; 6856 6857 if (pdev->msix_cap) 6858 bp->flags |= BNXT_FLAG_MSIX_CAP; 6859 6860 rc = bnxt_init_board(pdev, dev); 6861 if (rc < 0) 6862 goto init_err_free; 6863 6864 dev->netdev_ops = &bnxt_netdev_ops; 6865 dev->watchdog_timeo = BNXT_TX_TIMEOUT; 6866 dev->ethtool_ops = &bnxt_ethtool_ops; 6867 6868 pci_set_drvdata(pdev, dev); 6869 6870 rc = bnxt_alloc_hwrm_resources(bp); 6871 if (rc) 6872 goto init_err; 6873 6874 mutex_init(&bp->hwrm_cmd_lock); 6875 rc = bnxt_hwrm_ver_get(bp); 6876 if (rc) 6877 goto init_err; 6878 6879 bnxt_hwrm_fw_set_time(bp); 6880 6881 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG | 6882 NETIF_F_TSO | NETIF_F_TSO6 | 6883 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE | 6884 NETIF_F_GSO_IPXIP4 | 6885 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM | 6886 NETIF_F_GSO_PARTIAL | NETIF_F_RXHASH | 6887 NETIF_F_RXCSUM | NETIF_F_GRO; 6888 6889 if (!BNXT_CHIP_TYPE_NITRO_A0(bp)) 6890 dev->hw_features |= NETIF_F_LRO; 6891 6892 dev->hw_enc_features = 6893 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG | 6894 NETIF_F_TSO | NETIF_F_TSO6 | 6895 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE | 6896 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM | 6897 NETIF_F_GSO_IPXIP4 | NETIF_F_GSO_PARTIAL; 6898 dev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM | 6899 NETIF_F_GSO_GRE_CSUM; 6900 dev->vlan_features = dev->hw_features | NETIF_F_HIGHDMA; 6901 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX | 6902 NETIF_F_HW_VLAN_STAG_RX | NETIF_F_HW_VLAN_STAG_TX; 6903 dev->features |= dev->hw_features | NETIF_F_HIGHDMA; 6904 dev->priv_flags |= IFF_UNICAST_FLT; 6905 6906 /* MTU range: 60 - 9500 */ 6907 dev->min_mtu = ETH_ZLEN; 6908 dev->max_mtu = 9500; 6909 6910 #ifdef CONFIG_BNXT_SRIOV 6911 init_waitqueue_head(&bp->sriov_cfg_wait); 6912 #endif 6913 bp->gro_func = bnxt_gro_func_5730x; 6914 if (BNXT_CHIP_NUM_57X1X(bp->chip_num)) 6915 bp->gro_func = bnxt_gro_func_5731x; 6916 6917 rc = bnxt_hwrm_func_drv_rgtr(bp); 6918 if (rc) 6919 goto init_err; 6920 6921 /* Get the MAX capabilities for this function */ 6922 rc = bnxt_hwrm_func_qcaps(bp); 6923 if (rc) { 6924 netdev_err(bp->dev, "hwrm query capability failure rc: %x\n", 6925 rc); 6926 rc = -1; 6927 goto init_err; 6928 } 6929 6930 rc = bnxt_hwrm_queue_qportcfg(bp); 6931 if (rc) { 6932 netdev_err(bp->dev, "hwrm query qportcfg failure rc: %x\n", 6933 rc); 6934 rc = -1; 6935 goto init_err; 6936 } 6937 6938 bnxt_hwrm_func_qcfg(bp); 6939 6940 bnxt_set_tpa_flags(bp); 6941 bnxt_set_ring_params(bp); 6942 if (BNXT_PF(bp)) 6943 bp->pf.max_irqs = max_irqs; 6944 #if defined(CONFIG_BNXT_SRIOV) 6945 else 6946 bp->vf.max_irqs = max_irqs; 6947 #endif 6948 bnxt_set_dflt_rings(bp); 6949 6950 /* Default RSS hash cfg. */ 6951 bp->rss_hash_cfg = VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 | 6952 VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 | 6953 VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 | 6954 VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6; 6955 if (!BNXT_CHIP_NUM_57X0X(bp->chip_num) && 6956 !BNXT_CHIP_TYPE_NITRO_A0(bp) && 6957 bp->hwrm_spec_code >= 0x10501) { 6958 bp->flags |= BNXT_FLAG_UDP_RSS_CAP; 6959 bp->rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 | 6960 VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6; 6961 } 6962 6963 if (BNXT_PF(bp) && !BNXT_CHIP_TYPE_NITRO_A0(bp)) { 6964 dev->hw_features |= NETIF_F_NTUPLE; 6965 if (bnxt_rfs_capable(bp)) { 6966 bp->flags |= BNXT_FLAG_RFS; 6967 dev->features |= NETIF_F_NTUPLE; 6968 } 6969 } 6970 6971 if (dev->hw_features & NETIF_F_HW_VLAN_CTAG_RX) 6972 bp->flags |= BNXT_FLAG_STRIP_VLAN; 6973 6974 rc = bnxt_probe_phy(bp); 6975 if (rc) 6976 goto init_err; 6977 6978 rc = register_netdev(dev); 6979 if (rc) 6980 goto init_err; 6981 6982 netdev_info(dev, "%s found at mem %lx, node addr %pM\n", 6983 board_info[ent->driver_data].name, 6984 (long)pci_resource_start(pdev, 0), dev->dev_addr); 6985 6986 bnxt_parse_log_pcie_link(bp); 6987 6988 return 0; 6989 6990 init_err: 6991 pci_iounmap(pdev, bp->bar0); 6992 pci_release_regions(pdev); 6993 pci_disable_device(pdev); 6994 6995 init_err_free: 6996 free_netdev(dev); 6997 return rc; 6998 } 6999 7000 /** 7001 * bnxt_io_error_detected - called when PCI error is detected 7002 * @pdev: Pointer to PCI device 7003 * @state: The current pci connection state 7004 * 7005 * This function is called after a PCI bus error affecting 7006 * this device has been detected. 7007 */ 7008 static pci_ers_result_t bnxt_io_error_detected(struct pci_dev *pdev, 7009 pci_channel_state_t state) 7010 { 7011 struct net_device *netdev = pci_get_drvdata(pdev); 7012 struct bnxt *bp = netdev_priv(netdev); 7013 7014 netdev_info(netdev, "PCI I/O error detected\n"); 7015 7016 rtnl_lock(); 7017 netif_device_detach(netdev); 7018 7019 if (state == pci_channel_io_perm_failure) { 7020 rtnl_unlock(); 7021 return PCI_ERS_RESULT_DISCONNECT; 7022 } 7023 7024 if (netif_running(netdev)) 7025 bnxt_close(netdev); 7026 7027 /* So that func_reset will be done during slot_reset */ 7028 clear_bit(BNXT_STATE_FN_RST_DONE, &bp->state); 7029 pci_disable_device(pdev); 7030 rtnl_unlock(); 7031 7032 /* Request a slot slot reset. */ 7033 return PCI_ERS_RESULT_NEED_RESET; 7034 } 7035 7036 /** 7037 * bnxt_io_slot_reset - called after the pci bus has been reset. 7038 * @pdev: Pointer to PCI device 7039 * 7040 * Restart the card from scratch, as if from a cold-boot. 7041 * At this point, the card has exprienced a hard reset, 7042 * followed by fixups by BIOS, and has its config space 7043 * set up identically to what it was at cold boot. 7044 */ 7045 static pci_ers_result_t bnxt_io_slot_reset(struct pci_dev *pdev) 7046 { 7047 struct net_device *netdev = pci_get_drvdata(pdev); 7048 struct bnxt *bp = netdev_priv(netdev); 7049 int err = 0; 7050 pci_ers_result_t result = PCI_ERS_RESULT_DISCONNECT; 7051 7052 netdev_info(bp->dev, "PCI Slot Reset\n"); 7053 7054 rtnl_lock(); 7055 7056 if (pci_enable_device(pdev)) { 7057 dev_err(&pdev->dev, 7058 "Cannot re-enable PCI device after reset.\n"); 7059 } else { 7060 pci_set_master(pdev); 7061 7062 if (netif_running(netdev)) 7063 err = bnxt_open(netdev); 7064 7065 if (!err) 7066 result = PCI_ERS_RESULT_RECOVERED; 7067 } 7068 7069 if (result != PCI_ERS_RESULT_RECOVERED && netif_running(netdev)) 7070 dev_close(netdev); 7071 7072 rtnl_unlock(); 7073 7074 err = pci_cleanup_aer_uncorrect_error_status(pdev); 7075 if (err) { 7076 dev_err(&pdev->dev, 7077 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", 7078 err); /* non-fatal, continue */ 7079 } 7080 7081 return PCI_ERS_RESULT_RECOVERED; 7082 } 7083 7084 /** 7085 * bnxt_io_resume - called when traffic can start flowing again. 7086 * @pdev: Pointer to PCI device 7087 * 7088 * This callback is called when the error recovery driver tells 7089 * us that its OK to resume normal operation. 7090 */ 7091 static void bnxt_io_resume(struct pci_dev *pdev) 7092 { 7093 struct net_device *netdev = pci_get_drvdata(pdev); 7094 7095 rtnl_lock(); 7096 7097 netif_device_attach(netdev); 7098 7099 rtnl_unlock(); 7100 } 7101 7102 static const struct pci_error_handlers bnxt_err_handler = { 7103 .error_detected = bnxt_io_error_detected, 7104 .slot_reset = bnxt_io_slot_reset, 7105 .resume = bnxt_io_resume 7106 }; 7107 7108 static struct pci_driver bnxt_pci_driver = { 7109 .name = DRV_MODULE_NAME, 7110 .id_table = bnxt_pci_tbl, 7111 .probe = bnxt_init_one, 7112 .remove = bnxt_remove_one, 7113 .err_handler = &bnxt_err_handler, 7114 #if defined(CONFIG_BNXT_SRIOV) 7115 .sriov_configure = bnxt_sriov_configure, 7116 #endif 7117 }; 7118 7119 module_pci_driver(bnxt_pci_driver); 7120