1 /* Broadcom NetXtreme-C/E network driver. 2 * 3 * Copyright (c) 2014-2016 Broadcom Corporation 4 * Copyright (c) 2016-2019 Broadcom Limited 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation. 9 */ 10 11 #include <linux/module.h> 12 13 #include <linux/stringify.h> 14 #include <linux/kernel.h> 15 #include <linux/timer.h> 16 #include <linux/errno.h> 17 #include <linux/ioport.h> 18 #include <linux/slab.h> 19 #include <linux/vmalloc.h> 20 #include <linux/interrupt.h> 21 #include <linux/pci.h> 22 #include <linux/netdevice.h> 23 #include <linux/etherdevice.h> 24 #include <linux/skbuff.h> 25 #include <linux/dma-mapping.h> 26 #include <linux/bitops.h> 27 #include <linux/io.h> 28 #include <linux/irq.h> 29 #include <linux/delay.h> 30 #include <asm/byteorder.h> 31 #include <asm/page.h> 32 #include <linux/time.h> 33 #include <linux/mii.h> 34 #include <linux/mdio.h> 35 #include <linux/if.h> 36 #include <linux/if_vlan.h> 37 #include <linux/if_bridge.h> 38 #include <linux/rtc.h> 39 #include <linux/bpf.h> 40 #include <net/gro.h> 41 #include <net/ip.h> 42 #include <net/tcp.h> 43 #include <net/udp.h> 44 #include <net/checksum.h> 45 #include <net/ip6_checksum.h> 46 #include <net/udp_tunnel.h> 47 #include <linux/workqueue.h> 48 #include <linux/prefetch.h> 49 #include <linux/cache.h> 50 #include <linux/log2.h> 51 #include <linux/bitmap.h> 52 #include <linux/cpu_rmap.h> 53 #include <linux/cpumask.h> 54 #include <net/pkt_cls.h> 55 #include <linux/hwmon.h> 56 #include <linux/hwmon-sysfs.h> 57 #include <net/page_pool.h> 58 #include <linux/align.h> 59 #include <net/netdev_queues.h> 60 61 #include "bnxt_hsi.h" 62 #include "bnxt.h" 63 #include "bnxt_hwrm.h" 64 #include "bnxt_ulp.h" 65 #include "bnxt_sriov.h" 66 #include "bnxt_ethtool.h" 67 #include "bnxt_dcb.h" 68 #include "bnxt_xdp.h" 69 #include "bnxt_ptp.h" 70 #include "bnxt_vfr.h" 71 #include "bnxt_tc.h" 72 #include "bnxt_devlink.h" 73 #include "bnxt_debugfs.h" 74 75 #define BNXT_TX_TIMEOUT (5 * HZ) 76 #define BNXT_DEF_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_HW | \ 77 NETIF_MSG_TX_ERR) 78 79 MODULE_LICENSE("GPL"); 80 MODULE_DESCRIPTION("Broadcom BCM573xx network driver"); 81 82 #define BNXT_RX_OFFSET (NET_SKB_PAD + NET_IP_ALIGN) 83 #define BNXT_RX_DMA_OFFSET NET_SKB_PAD 84 #define BNXT_RX_COPY_THRESH 256 85 86 #define BNXT_TX_PUSH_THRESH 164 87 88 /* indexed by enum board_idx */ 89 static const struct { 90 char *name; 91 } board_info[] = { 92 [BCM57301] = { "Broadcom BCM57301 NetXtreme-C 10Gb Ethernet" }, 93 [BCM57302] = { "Broadcom BCM57302 NetXtreme-C 10Gb/25Gb Ethernet" }, 94 [BCM57304] = { "Broadcom BCM57304 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" }, 95 [BCM57417_NPAR] = { "Broadcom BCM57417 NetXtreme-E Ethernet Partition" }, 96 [BCM58700] = { "Broadcom BCM58700 Nitro 1Gb/2.5Gb/10Gb Ethernet" }, 97 [BCM57311] = { "Broadcom BCM57311 NetXtreme-C 10Gb Ethernet" }, 98 [BCM57312] = { "Broadcom BCM57312 NetXtreme-C 10Gb/25Gb Ethernet" }, 99 [BCM57402] = { "Broadcom BCM57402 NetXtreme-E 10Gb Ethernet" }, 100 [BCM57404] = { "Broadcom BCM57404 NetXtreme-E 10Gb/25Gb Ethernet" }, 101 [BCM57406] = { "Broadcom BCM57406 NetXtreme-E 10GBase-T Ethernet" }, 102 [BCM57402_NPAR] = { "Broadcom BCM57402 NetXtreme-E Ethernet Partition" }, 103 [BCM57407] = { "Broadcom BCM57407 NetXtreme-E 10GBase-T Ethernet" }, 104 [BCM57412] = { "Broadcom BCM57412 NetXtreme-E 10Gb Ethernet" }, 105 [BCM57414] = { "Broadcom BCM57414 NetXtreme-E 10Gb/25Gb Ethernet" }, 106 [BCM57416] = { "Broadcom BCM57416 NetXtreme-E 10GBase-T Ethernet" }, 107 [BCM57417] = { "Broadcom BCM57417 NetXtreme-E 10GBase-T Ethernet" }, 108 [BCM57412_NPAR] = { "Broadcom BCM57412 NetXtreme-E Ethernet Partition" }, 109 [BCM57314] = { "Broadcom BCM57314 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" }, 110 [BCM57417_SFP] = { "Broadcom BCM57417 NetXtreme-E 10Gb/25Gb Ethernet" }, 111 [BCM57416_SFP] = { "Broadcom BCM57416 NetXtreme-E 10Gb Ethernet" }, 112 [BCM57404_NPAR] = { "Broadcom BCM57404 NetXtreme-E Ethernet Partition" }, 113 [BCM57406_NPAR] = { "Broadcom BCM57406 NetXtreme-E Ethernet Partition" }, 114 [BCM57407_SFP] = { "Broadcom BCM57407 NetXtreme-E 25Gb Ethernet" }, 115 [BCM57407_NPAR] = { "Broadcom BCM57407 NetXtreme-E Ethernet Partition" }, 116 [BCM57414_NPAR] = { "Broadcom BCM57414 NetXtreme-E Ethernet Partition" }, 117 [BCM57416_NPAR] = { "Broadcom BCM57416 NetXtreme-E Ethernet Partition" }, 118 [BCM57452] = { "Broadcom BCM57452 NetXtreme-E 10Gb/25Gb/40Gb/50Gb Ethernet" }, 119 [BCM57454] = { "Broadcom BCM57454 NetXtreme-E 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" }, 120 [BCM5745x_NPAR] = { "Broadcom BCM5745x NetXtreme-E Ethernet Partition" }, 121 [BCM57508] = { "Broadcom BCM57508 NetXtreme-E 10Gb/25Gb/50Gb/100Gb/200Gb Ethernet" }, 122 [BCM57504] = { "Broadcom BCM57504 NetXtreme-E 10Gb/25Gb/50Gb/100Gb/200Gb Ethernet" }, 123 [BCM57502] = { "Broadcom BCM57502 NetXtreme-E 10Gb/25Gb/50Gb Ethernet" }, 124 [BCM57508_NPAR] = { "Broadcom BCM57508 NetXtreme-E Ethernet Partition" }, 125 [BCM57504_NPAR] = { "Broadcom BCM57504 NetXtreme-E Ethernet Partition" }, 126 [BCM57502_NPAR] = { "Broadcom BCM57502 NetXtreme-E Ethernet Partition" }, 127 [BCM58802] = { "Broadcom BCM58802 NetXtreme-S 10Gb/25Gb/40Gb/50Gb Ethernet" }, 128 [BCM58804] = { "Broadcom BCM58804 NetXtreme-S 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" }, 129 [BCM58808] = { "Broadcom BCM58808 NetXtreme-S 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" }, 130 [NETXTREME_E_VF] = { "Broadcom NetXtreme-E Ethernet Virtual Function" }, 131 [NETXTREME_C_VF] = { "Broadcom NetXtreme-C Ethernet Virtual Function" }, 132 [NETXTREME_S_VF] = { "Broadcom NetXtreme-S Ethernet Virtual Function" }, 133 [NETXTREME_C_VF_HV] = { "Broadcom NetXtreme-C Virtual Function for Hyper-V" }, 134 [NETXTREME_E_VF_HV] = { "Broadcom NetXtreme-E Virtual Function for Hyper-V" }, 135 [NETXTREME_E_P5_VF] = { "Broadcom BCM5750X NetXtreme-E Ethernet Virtual Function" }, 136 [NETXTREME_E_P5_VF_HV] = { "Broadcom BCM5750X NetXtreme-E Virtual Function for Hyper-V" }, 137 }; 138 139 static const struct pci_device_id bnxt_pci_tbl[] = { 140 { PCI_VDEVICE(BROADCOM, 0x1604), .driver_data = BCM5745x_NPAR }, 141 { PCI_VDEVICE(BROADCOM, 0x1605), .driver_data = BCM5745x_NPAR }, 142 { PCI_VDEVICE(BROADCOM, 0x1614), .driver_data = BCM57454 }, 143 { PCI_VDEVICE(BROADCOM, 0x16c0), .driver_data = BCM57417_NPAR }, 144 { PCI_VDEVICE(BROADCOM, 0x16c8), .driver_data = BCM57301 }, 145 { PCI_VDEVICE(BROADCOM, 0x16c9), .driver_data = BCM57302 }, 146 { PCI_VDEVICE(BROADCOM, 0x16ca), .driver_data = BCM57304 }, 147 { PCI_VDEVICE(BROADCOM, 0x16cc), .driver_data = BCM57417_NPAR }, 148 { PCI_VDEVICE(BROADCOM, 0x16cd), .driver_data = BCM58700 }, 149 { PCI_VDEVICE(BROADCOM, 0x16ce), .driver_data = BCM57311 }, 150 { PCI_VDEVICE(BROADCOM, 0x16cf), .driver_data = BCM57312 }, 151 { PCI_VDEVICE(BROADCOM, 0x16d0), .driver_data = BCM57402 }, 152 { PCI_VDEVICE(BROADCOM, 0x16d1), .driver_data = BCM57404 }, 153 { PCI_VDEVICE(BROADCOM, 0x16d2), .driver_data = BCM57406 }, 154 { PCI_VDEVICE(BROADCOM, 0x16d4), .driver_data = BCM57402_NPAR }, 155 { PCI_VDEVICE(BROADCOM, 0x16d5), .driver_data = BCM57407 }, 156 { PCI_VDEVICE(BROADCOM, 0x16d6), .driver_data = BCM57412 }, 157 { PCI_VDEVICE(BROADCOM, 0x16d7), .driver_data = BCM57414 }, 158 { PCI_VDEVICE(BROADCOM, 0x16d8), .driver_data = BCM57416 }, 159 { PCI_VDEVICE(BROADCOM, 0x16d9), .driver_data = BCM57417 }, 160 { PCI_VDEVICE(BROADCOM, 0x16de), .driver_data = BCM57412_NPAR }, 161 { PCI_VDEVICE(BROADCOM, 0x16df), .driver_data = BCM57314 }, 162 { PCI_VDEVICE(BROADCOM, 0x16e2), .driver_data = BCM57417_SFP }, 163 { PCI_VDEVICE(BROADCOM, 0x16e3), .driver_data = BCM57416_SFP }, 164 { PCI_VDEVICE(BROADCOM, 0x16e7), .driver_data = BCM57404_NPAR }, 165 { PCI_VDEVICE(BROADCOM, 0x16e8), .driver_data = BCM57406_NPAR }, 166 { PCI_VDEVICE(BROADCOM, 0x16e9), .driver_data = BCM57407_SFP }, 167 { PCI_VDEVICE(BROADCOM, 0x16ea), .driver_data = BCM57407_NPAR }, 168 { PCI_VDEVICE(BROADCOM, 0x16eb), .driver_data = BCM57412_NPAR }, 169 { PCI_VDEVICE(BROADCOM, 0x16ec), .driver_data = BCM57414_NPAR }, 170 { PCI_VDEVICE(BROADCOM, 0x16ed), .driver_data = BCM57414_NPAR }, 171 { PCI_VDEVICE(BROADCOM, 0x16ee), .driver_data = BCM57416_NPAR }, 172 { PCI_VDEVICE(BROADCOM, 0x16ef), .driver_data = BCM57416_NPAR }, 173 { PCI_VDEVICE(BROADCOM, 0x16f0), .driver_data = BCM58808 }, 174 { PCI_VDEVICE(BROADCOM, 0x16f1), .driver_data = BCM57452 }, 175 { PCI_VDEVICE(BROADCOM, 0x1750), .driver_data = BCM57508 }, 176 { PCI_VDEVICE(BROADCOM, 0x1751), .driver_data = BCM57504 }, 177 { PCI_VDEVICE(BROADCOM, 0x1752), .driver_data = BCM57502 }, 178 { PCI_VDEVICE(BROADCOM, 0x1800), .driver_data = BCM57502_NPAR }, 179 { PCI_VDEVICE(BROADCOM, 0x1801), .driver_data = BCM57504_NPAR }, 180 { PCI_VDEVICE(BROADCOM, 0x1802), .driver_data = BCM57508_NPAR }, 181 { PCI_VDEVICE(BROADCOM, 0x1803), .driver_data = BCM57502_NPAR }, 182 { PCI_VDEVICE(BROADCOM, 0x1804), .driver_data = BCM57504_NPAR }, 183 { PCI_VDEVICE(BROADCOM, 0x1805), .driver_data = BCM57508_NPAR }, 184 { PCI_VDEVICE(BROADCOM, 0xd802), .driver_data = BCM58802 }, 185 { PCI_VDEVICE(BROADCOM, 0xd804), .driver_data = BCM58804 }, 186 #ifdef CONFIG_BNXT_SRIOV 187 { PCI_VDEVICE(BROADCOM, 0x1606), .driver_data = NETXTREME_E_VF }, 188 { PCI_VDEVICE(BROADCOM, 0x1607), .driver_data = NETXTREME_E_VF_HV }, 189 { PCI_VDEVICE(BROADCOM, 0x1608), .driver_data = NETXTREME_E_VF_HV }, 190 { PCI_VDEVICE(BROADCOM, 0x1609), .driver_data = NETXTREME_E_VF }, 191 { PCI_VDEVICE(BROADCOM, 0x16bd), .driver_data = NETXTREME_E_VF_HV }, 192 { PCI_VDEVICE(BROADCOM, 0x16c1), .driver_data = NETXTREME_E_VF }, 193 { PCI_VDEVICE(BROADCOM, 0x16c2), .driver_data = NETXTREME_C_VF_HV }, 194 { PCI_VDEVICE(BROADCOM, 0x16c3), .driver_data = NETXTREME_C_VF_HV }, 195 { PCI_VDEVICE(BROADCOM, 0x16c4), .driver_data = NETXTREME_E_VF_HV }, 196 { PCI_VDEVICE(BROADCOM, 0x16c5), .driver_data = NETXTREME_E_VF_HV }, 197 { PCI_VDEVICE(BROADCOM, 0x16cb), .driver_data = NETXTREME_C_VF }, 198 { PCI_VDEVICE(BROADCOM, 0x16d3), .driver_data = NETXTREME_E_VF }, 199 { PCI_VDEVICE(BROADCOM, 0x16dc), .driver_data = NETXTREME_E_VF }, 200 { PCI_VDEVICE(BROADCOM, 0x16e1), .driver_data = NETXTREME_C_VF }, 201 { PCI_VDEVICE(BROADCOM, 0x16e5), .driver_data = NETXTREME_C_VF }, 202 { PCI_VDEVICE(BROADCOM, 0x16e6), .driver_data = NETXTREME_C_VF_HV }, 203 { PCI_VDEVICE(BROADCOM, 0x1806), .driver_data = NETXTREME_E_P5_VF }, 204 { PCI_VDEVICE(BROADCOM, 0x1807), .driver_data = NETXTREME_E_P5_VF }, 205 { PCI_VDEVICE(BROADCOM, 0x1808), .driver_data = NETXTREME_E_P5_VF_HV }, 206 { PCI_VDEVICE(BROADCOM, 0x1809), .driver_data = NETXTREME_E_P5_VF_HV }, 207 { PCI_VDEVICE(BROADCOM, 0xd800), .driver_data = NETXTREME_S_VF }, 208 #endif 209 { 0 } 210 }; 211 212 MODULE_DEVICE_TABLE(pci, bnxt_pci_tbl); 213 214 static const u16 bnxt_vf_req_snif[] = { 215 HWRM_FUNC_CFG, 216 HWRM_FUNC_VF_CFG, 217 HWRM_PORT_PHY_QCFG, 218 HWRM_CFA_L2_FILTER_ALLOC, 219 }; 220 221 static const u16 bnxt_async_events_arr[] = { 222 ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE, 223 ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE, 224 ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD, 225 ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED, 226 ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE, 227 ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE, 228 ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE, 229 ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY, 230 ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY, 231 ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION, 232 ASYNC_EVENT_CMPL_EVENT_ID_DEFERRED_RESPONSE, 233 ASYNC_EVENT_CMPL_EVENT_ID_RING_MONITOR_MSG, 234 ASYNC_EVENT_CMPL_EVENT_ID_ECHO_REQUEST, 235 ASYNC_EVENT_CMPL_EVENT_ID_PPS_TIMESTAMP, 236 ASYNC_EVENT_CMPL_EVENT_ID_ERROR_REPORT, 237 ASYNC_EVENT_CMPL_EVENT_ID_PHC_UPDATE, 238 }; 239 240 static struct workqueue_struct *bnxt_pf_wq; 241 242 static bool bnxt_vf_pciid(enum board_idx idx) 243 { 244 return (idx == NETXTREME_C_VF || idx == NETXTREME_E_VF || 245 idx == NETXTREME_S_VF || idx == NETXTREME_C_VF_HV || 246 idx == NETXTREME_E_VF_HV || idx == NETXTREME_E_P5_VF || 247 idx == NETXTREME_E_P5_VF_HV); 248 } 249 250 #define DB_CP_REARM_FLAGS (DB_KEY_CP | DB_IDX_VALID) 251 #define DB_CP_FLAGS (DB_KEY_CP | DB_IDX_VALID | DB_IRQ_DIS) 252 #define DB_CP_IRQ_DIS_FLAGS (DB_KEY_CP | DB_IRQ_DIS) 253 254 #define BNXT_CP_DB_IRQ_DIS(db) \ 255 writel(DB_CP_IRQ_DIS_FLAGS, db) 256 257 #define BNXT_DB_CQ(db, idx) \ 258 writel(DB_CP_FLAGS | RING_CMP(idx), (db)->doorbell) 259 260 #define BNXT_DB_NQ_P5(db, idx) \ 261 bnxt_writeq(bp, (db)->db_key64 | DBR_TYPE_NQ | RING_CMP(idx), \ 262 (db)->doorbell) 263 264 #define BNXT_DB_CQ_ARM(db, idx) \ 265 writel(DB_CP_REARM_FLAGS | RING_CMP(idx), (db)->doorbell) 266 267 #define BNXT_DB_NQ_ARM_P5(db, idx) \ 268 bnxt_writeq(bp, (db)->db_key64 | DBR_TYPE_NQ_ARM | RING_CMP(idx),\ 269 (db)->doorbell) 270 271 static void bnxt_db_nq(struct bnxt *bp, struct bnxt_db_info *db, u32 idx) 272 { 273 if (bp->flags & BNXT_FLAG_CHIP_P5) 274 BNXT_DB_NQ_P5(db, idx); 275 else 276 BNXT_DB_CQ(db, idx); 277 } 278 279 static void bnxt_db_nq_arm(struct bnxt *bp, struct bnxt_db_info *db, u32 idx) 280 { 281 if (bp->flags & BNXT_FLAG_CHIP_P5) 282 BNXT_DB_NQ_ARM_P5(db, idx); 283 else 284 BNXT_DB_CQ_ARM(db, idx); 285 } 286 287 static void bnxt_db_cq(struct bnxt *bp, struct bnxt_db_info *db, u32 idx) 288 { 289 if (bp->flags & BNXT_FLAG_CHIP_P5) 290 bnxt_writeq(bp, db->db_key64 | DBR_TYPE_CQ_ARMALL | 291 RING_CMP(idx), db->doorbell); 292 else 293 BNXT_DB_CQ(db, idx); 294 } 295 296 const u16 bnxt_lhint_arr[] = { 297 TX_BD_FLAGS_LHINT_512_AND_SMALLER, 298 TX_BD_FLAGS_LHINT_512_TO_1023, 299 TX_BD_FLAGS_LHINT_1024_TO_2047, 300 TX_BD_FLAGS_LHINT_1024_TO_2047, 301 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 302 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 303 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 304 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 305 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 306 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 307 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 308 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 309 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 310 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 311 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 312 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 313 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 314 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 315 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 316 }; 317 318 static u16 bnxt_xmit_get_cfa_action(struct sk_buff *skb) 319 { 320 struct metadata_dst *md_dst = skb_metadata_dst(skb); 321 322 if (!md_dst || md_dst->type != METADATA_HW_PORT_MUX) 323 return 0; 324 325 return md_dst->u.port_info.port_id; 326 } 327 328 static void bnxt_txr_db_kick(struct bnxt *bp, struct bnxt_tx_ring_info *txr, 329 u16 prod) 330 { 331 bnxt_db_write(bp, &txr->tx_db, prod); 332 txr->kick_pending = 0; 333 } 334 335 static netdev_tx_t bnxt_start_xmit(struct sk_buff *skb, struct net_device *dev) 336 { 337 struct bnxt *bp = netdev_priv(dev); 338 struct tx_bd *txbd; 339 struct tx_bd_ext *txbd1; 340 struct netdev_queue *txq; 341 int i; 342 dma_addr_t mapping; 343 unsigned int length, pad = 0; 344 u32 len, free_size, vlan_tag_flags, cfa_action, flags; 345 u16 prod, last_frag; 346 struct pci_dev *pdev = bp->pdev; 347 struct bnxt_tx_ring_info *txr; 348 struct bnxt_sw_tx_bd *tx_buf; 349 __le32 lflags = 0; 350 351 i = skb_get_queue_mapping(skb); 352 if (unlikely(i >= bp->tx_nr_rings)) { 353 dev_kfree_skb_any(skb); 354 dev_core_stats_tx_dropped_inc(dev); 355 return NETDEV_TX_OK; 356 } 357 358 txq = netdev_get_tx_queue(dev, i); 359 txr = &bp->tx_ring[bp->tx_ring_map[i]]; 360 prod = txr->tx_prod; 361 362 free_size = bnxt_tx_avail(bp, txr); 363 if (unlikely(free_size < skb_shinfo(skb)->nr_frags + 2)) { 364 /* We must have raced with NAPI cleanup */ 365 if (net_ratelimit() && txr->kick_pending) 366 netif_warn(bp, tx_err, dev, 367 "bnxt: ring busy w/ flush pending!\n"); 368 if (!netif_txq_try_stop(txq, bnxt_tx_avail(bp, txr), 369 bp->tx_wake_thresh)) 370 return NETDEV_TX_BUSY; 371 } 372 373 if (unlikely(ipv6_hopopt_jumbo_remove(skb))) 374 goto tx_free; 375 376 length = skb->len; 377 len = skb_headlen(skb); 378 last_frag = skb_shinfo(skb)->nr_frags; 379 380 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)]; 381 382 txbd->tx_bd_opaque = prod; 383 384 tx_buf = &txr->tx_buf_ring[prod]; 385 tx_buf->skb = skb; 386 tx_buf->nr_frags = last_frag; 387 388 vlan_tag_flags = 0; 389 cfa_action = bnxt_xmit_get_cfa_action(skb); 390 if (skb_vlan_tag_present(skb)) { 391 vlan_tag_flags = TX_BD_CFA_META_KEY_VLAN | 392 skb_vlan_tag_get(skb); 393 /* Currently supports 8021Q, 8021AD vlan offloads 394 * QINQ1, QINQ2, QINQ3 vlan headers are deprecated 395 */ 396 if (skb->vlan_proto == htons(ETH_P_8021Q)) 397 vlan_tag_flags |= 1 << TX_BD_CFA_META_TPID_SHIFT; 398 } 399 400 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) { 401 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 402 403 if (ptp && ptp->tx_tstamp_en && !skb_is_gso(skb) && 404 atomic_dec_if_positive(&ptp->tx_avail) >= 0) { 405 if (!bnxt_ptp_parse(skb, &ptp->tx_seqid, 406 &ptp->tx_hdr_off)) { 407 if (vlan_tag_flags) 408 ptp->tx_hdr_off += VLAN_HLEN; 409 lflags |= cpu_to_le32(TX_BD_FLAGS_STAMP); 410 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 411 } else { 412 atomic_inc(&bp->ptp_cfg->tx_avail); 413 } 414 } 415 } 416 417 if (unlikely(skb->no_fcs)) 418 lflags |= cpu_to_le32(TX_BD_FLAGS_NO_CRC); 419 420 if (free_size == bp->tx_ring_size && length <= bp->tx_push_thresh && 421 !lflags) { 422 struct tx_push_buffer *tx_push_buf = txr->tx_push; 423 struct tx_push_bd *tx_push = &tx_push_buf->push_bd; 424 struct tx_bd_ext *tx_push1 = &tx_push->txbd2; 425 void __iomem *db = txr->tx_db.doorbell; 426 void *pdata = tx_push_buf->data; 427 u64 *end; 428 int j, push_len; 429 430 /* Set COAL_NOW to be ready quickly for the next push */ 431 tx_push->tx_bd_len_flags_type = 432 cpu_to_le32((length << TX_BD_LEN_SHIFT) | 433 TX_BD_TYPE_LONG_TX_BD | 434 TX_BD_FLAGS_LHINT_512_AND_SMALLER | 435 TX_BD_FLAGS_COAL_NOW | 436 TX_BD_FLAGS_PACKET_END | 437 (2 << TX_BD_FLAGS_BD_CNT_SHIFT)); 438 439 if (skb->ip_summed == CHECKSUM_PARTIAL) 440 tx_push1->tx_bd_hsize_lflags = 441 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM); 442 else 443 tx_push1->tx_bd_hsize_lflags = 0; 444 445 tx_push1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags); 446 tx_push1->tx_bd_cfa_action = 447 cpu_to_le32(cfa_action << TX_BD_CFA_ACTION_SHIFT); 448 449 end = pdata + length; 450 end = PTR_ALIGN(end, 8) - 1; 451 *end = 0; 452 453 skb_copy_from_linear_data(skb, pdata, len); 454 pdata += len; 455 for (j = 0; j < last_frag; j++) { 456 skb_frag_t *frag = &skb_shinfo(skb)->frags[j]; 457 void *fptr; 458 459 fptr = skb_frag_address_safe(frag); 460 if (!fptr) 461 goto normal_tx; 462 463 memcpy(pdata, fptr, skb_frag_size(frag)); 464 pdata += skb_frag_size(frag); 465 } 466 467 txbd->tx_bd_len_flags_type = tx_push->tx_bd_len_flags_type; 468 txbd->tx_bd_haddr = txr->data_mapping; 469 prod = NEXT_TX(prod); 470 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)]; 471 memcpy(txbd, tx_push1, sizeof(*txbd)); 472 prod = NEXT_TX(prod); 473 tx_push->doorbell = 474 cpu_to_le32(DB_KEY_TX_PUSH | DB_LONG_TX_PUSH | prod); 475 WRITE_ONCE(txr->tx_prod, prod); 476 477 tx_buf->is_push = 1; 478 netdev_tx_sent_queue(txq, skb->len); 479 wmb(); /* Sync is_push and byte queue before pushing data */ 480 481 push_len = (length + sizeof(*tx_push) + 7) / 8; 482 if (push_len > 16) { 483 __iowrite64_copy(db, tx_push_buf, 16); 484 __iowrite32_copy(db + 4, tx_push_buf + 1, 485 (push_len - 16) << 1); 486 } else { 487 __iowrite64_copy(db, tx_push_buf, push_len); 488 } 489 490 goto tx_done; 491 } 492 493 normal_tx: 494 if (length < BNXT_MIN_PKT_SIZE) { 495 pad = BNXT_MIN_PKT_SIZE - length; 496 if (skb_pad(skb, pad)) 497 /* SKB already freed. */ 498 goto tx_kick_pending; 499 length = BNXT_MIN_PKT_SIZE; 500 } 501 502 mapping = dma_map_single(&pdev->dev, skb->data, len, DMA_TO_DEVICE); 503 504 if (unlikely(dma_mapping_error(&pdev->dev, mapping))) 505 goto tx_free; 506 507 dma_unmap_addr_set(tx_buf, mapping, mapping); 508 flags = (len << TX_BD_LEN_SHIFT) | TX_BD_TYPE_LONG_TX_BD | 509 ((last_frag + 2) << TX_BD_FLAGS_BD_CNT_SHIFT); 510 511 txbd->tx_bd_haddr = cpu_to_le64(mapping); 512 513 prod = NEXT_TX(prod); 514 txbd1 = (struct tx_bd_ext *) 515 &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)]; 516 517 txbd1->tx_bd_hsize_lflags = lflags; 518 if (skb_is_gso(skb)) { 519 u32 hdr_len; 520 521 if (skb->encapsulation) 522 hdr_len = skb_inner_tcp_all_headers(skb); 523 else 524 hdr_len = skb_tcp_all_headers(skb); 525 526 txbd1->tx_bd_hsize_lflags |= cpu_to_le32(TX_BD_FLAGS_LSO | 527 TX_BD_FLAGS_T_IPID | 528 (hdr_len << (TX_BD_HSIZE_SHIFT - 1))); 529 length = skb_shinfo(skb)->gso_size; 530 txbd1->tx_bd_mss = cpu_to_le32(length); 531 length += hdr_len; 532 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 533 txbd1->tx_bd_hsize_lflags |= 534 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM); 535 txbd1->tx_bd_mss = 0; 536 } 537 538 length >>= 9; 539 if (unlikely(length >= ARRAY_SIZE(bnxt_lhint_arr))) { 540 dev_warn_ratelimited(&pdev->dev, "Dropped oversize %d bytes TX packet.\n", 541 skb->len); 542 i = 0; 543 goto tx_dma_error; 544 } 545 flags |= bnxt_lhint_arr[length]; 546 txbd->tx_bd_len_flags_type = cpu_to_le32(flags); 547 548 txbd1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags); 549 txbd1->tx_bd_cfa_action = 550 cpu_to_le32(cfa_action << TX_BD_CFA_ACTION_SHIFT); 551 for (i = 0; i < last_frag; i++) { 552 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 553 554 prod = NEXT_TX(prod); 555 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)]; 556 557 len = skb_frag_size(frag); 558 mapping = skb_frag_dma_map(&pdev->dev, frag, 0, len, 559 DMA_TO_DEVICE); 560 561 if (unlikely(dma_mapping_error(&pdev->dev, mapping))) 562 goto tx_dma_error; 563 564 tx_buf = &txr->tx_buf_ring[prod]; 565 dma_unmap_addr_set(tx_buf, mapping, mapping); 566 567 txbd->tx_bd_haddr = cpu_to_le64(mapping); 568 569 flags = len << TX_BD_LEN_SHIFT; 570 txbd->tx_bd_len_flags_type = cpu_to_le32(flags); 571 } 572 573 flags &= ~TX_BD_LEN; 574 txbd->tx_bd_len_flags_type = 575 cpu_to_le32(((len + pad) << TX_BD_LEN_SHIFT) | flags | 576 TX_BD_FLAGS_PACKET_END); 577 578 netdev_tx_sent_queue(txq, skb->len); 579 580 skb_tx_timestamp(skb); 581 582 /* Sync BD data before updating doorbell */ 583 wmb(); 584 585 prod = NEXT_TX(prod); 586 WRITE_ONCE(txr->tx_prod, prod); 587 588 if (!netdev_xmit_more() || netif_xmit_stopped(txq)) 589 bnxt_txr_db_kick(bp, txr, prod); 590 else 591 txr->kick_pending = 1; 592 593 tx_done: 594 595 if (unlikely(bnxt_tx_avail(bp, txr) <= MAX_SKB_FRAGS + 1)) { 596 if (netdev_xmit_more() && !tx_buf->is_push) 597 bnxt_txr_db_kick(bp, txr, prod); 598 599 netif_txq_try_stop(txq, bnxt_tx_avail(bp, txr), 600 bp->tx_wake_thresh); 601 } 602 return NETDEV_TX_OK; 603 604 tx_dma_error: 605 if (BNXT_TX_PTP_IS_SET(lflags)) 606 atomic_inc(&bp->ptp_cfg->tx_avail); 607 608 last_frag = i; 609 610 /* start back at beginning and unmap skb */ 611 prod = txr->tx_prod; 612 tx_buf = &txr->tx_buf_ring[prod]; 613 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping), 614 skb_headlen(skb), DMA_TO_DEVICE); 615 prod = NEXT_TX(prod); 616 617 /* unmap remaining mapped pages */ 618 for (i = 0; i < last_frag; i++) { 619 prod = NEXT_TX(prod); 620 tx_buf = &txr->tx_buf_ring[prod]; 621 dma_unmap_page(&pdev->dev, dma_unmap_addr(tx_buf, mapping), 622 skb_frag_size(&skb_shinfo(skb)->frags[i]), 623 DMA_TO_DEVICE); 624 } 625 626 tx_free: 627 dev_kfree_skb_any(skb); 628 tx_kick_pending: 629 if (txr->kick_pending) 630 bnxt_txr_db_kick(bp, txr, txr->tx_prod); 631 txr->tx_buf_ring[txr->tx_prod].skb = NULL; 632 dev_core_stats_tx_dropped_inc(dev); 633 return NETDEV_TX_OK; 634 } 635 636 static void bnxt_tx_int(struct bnxt *bp, struct bnxt_napi *bnapi, int nr_pkts) 637 { 638 struct bnxt_tx_ring_info *txr = bnapi->tx_ring; 639 struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, txr->txq_index); 640 u16 cons = txr->tx_cons; 641 struct pci_dev *pdev = bp->pdev; 642 int i; 643 unsigned int tx_bytes = 0; 644 645 for (i = 0; i < nr_pkts; i++) { 646 struct bnxt_sw_tx_bd *tx_buf; 647 struct sk_buff *skb; 648 int j, last; 649 650 tx_buf = &txr->tx_buf_ring[cons]; 651 cons = NEXT_TX(cons); 652 skb = tx_buf->skb; 653 tx_buf->skb = NULL; 654 655 tx_bytes += skb->len; 656 657 if (tx_buf->is_push) { 658 tx_buf->is_push = 0; 659 goto next_tx_int; 660 } 661 662 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping), 663 skb_headlen(skb), DMA_TO_DEVICE); 664 last = tx_buf->nr_frags; 665 666 for (j = 0; j < last; j++) { 667 cons = NEXT_TX(cons); 668 tx_buf = &txr->tx_buf_ring[cons]; 669 dma_unmap_page( 670 &pdev->dev, 671 dma_unmap_addr(tx_buf, mapping), 672 skb_frag_size(&skb_shinfo(skb)->frags[j]), 673 DMA_TO_DEVICE); 674 } 675 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) { 676 if (bp->flags & BNXT_FLAG_CHIP_P5) { 677 /* PTP worker takes ownership of the skb */ 678 if (!bnxt_get_tx_ts_p5(bp, skb)) 679 skb = NULL; 680 else 681 atomic_inc(&bp->ptp_cfg->tx_avail); 682 } 683 } 684 685 next_tx_int: 686 cons = NEXT_TX(cons); 687 688 dev_kfree_skb_any(skb); 689 } 690 691 WRITE_ONCE(txr->tx_cons, cons); 692 693 __netif_txq_completed_wake(txq, nr_pkts, tx_bytes, 694 bnxt_tx_avail(bp, txr), bp->tx_wake_thresh, 695 READ_ONCE(txr->dev_state) != BNXT_DEV_STATE_CLOSING); 696 } 697 698 static struct page *__bnxt_alloc_rx_page(struct bnxt *bp, dma_addr_t *mapping, 699 struct bnxt_rx_ring_info *rxr, 700 gfp_t gfp) 701 { 702 struct device *dev = &bp->pdev->dev; 703 struct page *page; 704 705 page = page_pool_dev_alloc_pages(rxr->page_pool); 706 if (!page) 707 return NULL; 708 709 *mapping = dma_map_page_attrs(dev, page, 0, PAGE_SIZE, bp->rx_dir, 710 DMA_ATTR_WEAK_ORDERING); 711 if (dma_mapping_error(dev, *mapping)) { 712 page_pool_recycle_direct(rxr->page_pool, page); 713 return NULL; 714 } 715 return page; 716 } 717 718 static inline u8 *__bnxt_alloc_rx_frag(struct bnxt *bp, dma_addr_t *mapping, 719 gfp_t gfp) 720 { 721 u8 *data; 722 struct pci_dev *pdev = bp->pdev; 723 724 if (gfp == GFP_ATOMIC) 725 data = napi_alloc_frag(bp->rx_buf_size); 726 else 727 data = netdev_alloc_frag(bp->rx_buf_size); 728 if (!data) 729 return NULL; 730 731 *mapping = dma_map_single_attrs(&pdev->dev, data + bp->rx_dma_offset, 732 bp->rx_buf_use_size, bp->rx_dir, 733 DMA_ATTR_WEAK_ORDERING); 734 735 if (dma_mapping_error(&pdev->dev, *mapping)) { 736 skb_free_frag(data); 737 data = NULL; 738 } 739 return data; 740 } 741 742 int bnxt_alloc_rx_data(struct bnxt *bp, struct bnxt_rx_ring_info *rxr, 743 u16 prod, gfp_t gfp) 744 { 745 struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)]; 746 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[prod]; 747 dma_addr_t mapping; 748 749 if (BNXT_RX_PAGE_MODE(bp)) { 750 struct page *page = 751 __bnxt_alloc_rx_page(bp, &mapping, rxr, gfp); 752 753 if (!page) 754 return -ENOMEM; 755 756 mapping += bp->rx_dma_offset; 757 rx_buf->data = page; 758 rx_buf->data_ptr = page_address(page) + bp->rx_offset; 759 } else { 760 u8 *data = __bnxt_alloc_rx_frag(bp, &mapping, gfp); 761 762 if (!data) 763 return -ENOMEM; 764 765 rx_buf->data = data; 766 rx_buf->data_ptr = data + bp->rx_offset; 767 } 768 rx_buf->mapping = mapping; 769 770 rxbd->rx_bd_haddr = cpu_to_le64(mapping); 771 return 0; 772 } 773 774 void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons, void *data) 775 { 776 u16 prod = rxr->rx_prod; 777 struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf; 778 struct rx_bd *cons_bd, *prod_bd; 779 780 prod_rx_buf = &rxr->rx_buf_ring[prod]; 781 cons_rx_buf = &rxr->rx_buf_ring[cons]; 782 783 prod_rx_buf->data = data; 784 prod_rx_buf->data_ptr = cons_rx_buf->data_ptr; 785 786 prod_rx_buf->mapping = cons_rx_buf->mapping; 787 788 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)]; 789 cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)]; 790 791 prod_bd->rx_bd_haddr = cons_bd->rx_bd_haddr; 792 } 793 794 static inline u16 bnxt_find_next_agg_idx(struct bnxt_rx_ring_info *rxr, u16 idx) 795 { 796 u16 next, max = rxr->rx_agg_bmap_size; 797 798 next = find_next_zero_bit(rxr->rx_agg_bmap, max, idx); 799 if (next >= max) 800 next = find_first_zero_bit(rxr->rx_agg_bmap, max); 801 return next; 802 } 803 804 static inline int bnxt_alloc_rx_page(struct bnxt *bp, 805 struct bnxt_rx_ring_info *rxr, 806 u16 prod, gfp_t gfp) 807 { 808 struct rx_bd *rxbd = 809 &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)]; 810 struct bnxt_sw_rx_agg_bd *rx_agg_buf; 811 struct pci_dev *pdev = bp->pdev; 812 struct page *page; 813 dma_addr_t mapping; 814 u16 sw_prod = rxr->rx_sw_agg_prod; 815 unsigned int offset = 0; 816 817 if (BNXT_RX_PAGE_MODE(bp)) { 818 page = __bnxt_alloc_rx_page(bp, &mapping, rxr, gfp); 819 820 if (!page) 821 return -ENOMEM; 822 823 } else { 824 if (PAGE_SIZE > BNXT_RX_PAGE_SIZE) { 825 page = rxr->rx_page; 826 if (!page) { 827 page = alloc_page(gfp); 828 if (!page) 829 return -ENOMEM; 830 rxr->rx_page = page; 831 rxr->rx_page_offset = 0; 832 } 833 offset = rxr->rx_page_offset; 834 rxr->rx_page_offset += BNXT_RX_PAGE_SIZE; 835 if (rxr->rx_page_offset == PAGE_SIZE) 836 rxr->rx_page = NULL; 837 else 838 get_page(page); 839 } else { 840 page = alloc_page(gfp); 841 if (!page) 842 return -ENOMEM; 843 } 844 845 mapping = dma_map_page_attrs(&pdev->dev, page, offset, 846 BNXT_RX_PAGE_SIZE, DMA_FROM_DEVICE, 847 DMA_ATTR_WEAK_ORDERING); 848 if (dma_mapping_error(&pdev->dev, mapping)) { 849 __free_page(page); 850 return -EIO; 851 } 852 } 853 854 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap))) 855 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod); 856 857 __set_bit(sw_prod, rxr->rx_agg_bmap); 858 rx_agg_buf = &rxr->rx_agg_ring[sw_prod]; 859 rxr->rx_sw_agg_prod = NEXT_RX_AGG(sw_prod); 860 861 rx_agg_buf->page = page; 862 rx_agg_buf->offset = offset; 863 rx_agg_buf->mapping = mapping; 864 rxbd->rx_bd_haddr = cpu_to_le64(mapping); 865 rxbd->rx_bd_opaque = sw_prod; 866 return 0; 867 } 868 869 static struct rx_agg_cmp *bnxt_get_agg(struct bnxt *bp, 870 struct bnxt_cp_ring_info *cpr, 871 u16 cp_cons, u16 curr) 872 { 873 struct rx_agg_cmp *agg; 874 875 cp_cons = RING_CMP(ADV_RAW_CMP(cp_cons, curr)); 876 agg = (struct rx_agg_cmp *) 877 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 878 return agg; 879 } 880 881 static struct rx_agg_cmp *bnxt_get_tpa_agg_p5(struct bnxt *bp, 882 struct bnxt_rx_ring_info *rxr, 883 u16 agg_id, u16 curr) 884 { 885 struct bnxt_tpa_info *tpa_info = &rxr->rx_tpa[agg_id]; 886 887 return &tpa_info->agg_arr[curr]; 888 } 889 890 static void bnxt_reuse_rx_agg_bufs(struct bnxt_cp_ring_info *cpr, u16 idx, 891 u16 start, u32 agg_bufs, bool tpa) 892 { 893 struct bnxt_napi *bnapi = cpr->bnapi; 894 struct bnxt *bp = bnapi->bp; 895 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 896 u16 prod = rxr->rx_agg_prod; 897 u16 sw_prod = rxr->rx_sw_agg_prod; 898 bool p5_tpa = false; 899 u32 i; 900 901 if ((bp->flags & BNXT_FLAG_CHIP_P5) && tpa) 902 p5_tpa = true; 903 904 for (i = 0; i < agg_bufs; i++) { 905 u16 cons; 906 struct rx_agg_cmp *agg; 907 struct bnxt_sw_rx_agg_bd *cons_rx_buf, *prod_rx_buf; 908 struct rx_bd *prod_bd; 909 struct page *page; 910 911 if (p5_tpa) 912 agg = bnxt_get_tpa_agg_p5(bp, rxr, idx, start + i); 913 else 914 agg = bnxt_get_agg(bp, cpr, idx, start + i); 915 cons = agg->rx_agg_cmp_opaque; 916 __clear_bit(cons, rxr->rx_agg_bmap); 917 918 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap))) 919 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod); 920 921 __set_bit(sw_prod, rxr->rx_agg_bmap); 922 prod_rx_buf = &rxr->rx_agg_ring[sw_prod]; 923 cons_rx_buf = &rxr->rx_agg_ring[cons]; 924 925 /* It is possible for sw_prod to be equal to cons, so 926 * set cons_rx_buf->page to NULL first. 927 */ 928 page = cons_rx_buf->page; 929 cons_rx_buf->page = NULL; 930 prod_rx_buf->page = page; 931 prod_rx_buf->offset = cons_rx_buf->offset; 932 933 prod_rx_buf->mapping = cons_rx_buf->mapping; 934 935 prod_bd = &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)]; 936 937 prod_bd->rx_bd_haddr = cpu_to_le64(cons_rx_buf->mapping); 938 prod_bd->rx_bd_opaque = sw_prod; 939 940 prod = NEXT_RX_AGG(prod); 941 sw_prod = NEXT_RX_AGG(sw_prod); 942 } 943 rxr->rx_agg_prod = prod; 944 rxr->rx_sw_agg_prod = sw_prod; 945 } 946 947 static struct sk_buff *bnxt_rx_multi_page_skb(struct bnxt *bp, 948 struct bnxt_rx_ring_info *rxr, 949 u16 cons, void *data, u8 *data_ptr, 950 dma_addr_t dma_addr, 951 unsigned int offset_and_len) 952 { 953 unsigned int len = offset_and_len & 0xffff; 954 struct page *page = data; 955 u16 prod = rxr->rx_prod; 956 struct sk_buff *skb; 957 int err; 958 959 err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC); 960 if (unlikely(err)) { 961 bnxt_reuse_rx_data(rxr, cons, data); 962 return NULL; 963 } 964 dma_addr -= bp->rx_dma_offset; 965 dma_unmap_page_attrs(&bp->pdev->dev, dma_addr, PAGE_SIZE, bp->rx_dir, 966 DMA_ATTR_WEAK_ORDERING); 967 skb = build_skb(page_address(page), PAGE_SIZE); 968 if (!skb) { 969 page_pool_recycle_direct(rxr->page_pool, page); 970 return NULL; 971 } 972 skb_mark_for_recycle(skb); 973 skb_reserve(skb, bp->rx_dma_offset); 974 __skb_put(skb, len); 975 976 return skb; 977 } 978 979 static struct sk_buff *bnxt_rx_page_skb(struct bnxt *bp, 980 struct bnxt_rx_ring_info *rxr, 981 u16 cons, void *data, u8 *data_ptr, 982 dma_addr_t dma_addr, 983 unsigned int offset_and_len) 984 { 985 unsigned int payload = offset_and_len >> 16; 986 unsigned int len = offset_and_len & 0xffff; 987 skb_frag_t *frag; 988 struct page *page = data; 989 u16 prod = rxr->rx_prod; 990 struct sk_buff *skb; 991 int off, err; 992 993 err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC); 994 if (unlikely(err)) { 995 bnxt_reuse_rx_data(rxr, cons, data); 996 return NULL; 997 } 998 dma_addr -= bp->rx_dma_offset; 999 dma_unmap_page_attrs(&bp->pdev->dev, dma_addr, PAGE_SIZE, bp->rx_dir, 1000 DMA_ATTR_WEAK_ORDERING); 1001 1002 if (unlikely(!payload)) 1003 payload = eth_get_headlen(bp->dev, data_ptr, len); 1004 1005 skb = napi_alloc_skb(&rxr->bnapi->napi, payload); 1006 if (!skb) { 1007 page_pool_recycle_direct(rxr->page_pool, page); 1008 return NULL; 1009 } 1010 1011 skb_mark_for_recycle(skb); 1012 off = (void *)data_ptr - page_address(page); 1013 skb_add_rx_frag(skb, 0, page, off, len, PAGE_SIZE); 1014 memcpy(skb->data - NET_IP_ALIGN, data_ptr - NET_IP_ALIGN, 1015 payload + NET_IP_ALIGN); 1016 1017 frag = &skb_shinfo(skb)->frags[0]; 1018 skb_frag_size_sub(frag, payload); 1019 skb_frag_off_add(frag, payload); 1020 skb->data_len -= payload; 1021 skb->tail += payload; 1022 1023 return skb; 1024 } 1025 1026 static struct sk_buff *bnxt_rx_skb(struct bnxt *bp, 1027 struct bnxt_rx_ring_info *rxr, u16 cons, 1028 void *data, u8 *data_ptr, 1029 dma_addr_t dma_addr, 1030 unsigned int offset_and_len) 1031 { 1032 u16 prod = rxr->rx_prod; 1033 struct sk_buff *skb; 1034 int err; 1035 1036 err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC); 1037 if (unlikely(err)) { 1038 bnxt_reuse_rx_data(rxr, cons, data); 1039 return NULL; 1040 } 1041 1042 skb = build_skb(data, bp->rx_buf_size); 1043 dma_unmap_single_attrs(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size, 1044 bp->rx_dir, DMA_ATTR_WEAK_ORDERING); 1045 if (!skb) { 1046 skb_free_frag(data); 1047 return NULL; 1048 } 1049 1050 skb_reserve(skb, bp->rx_offset); 1051 skb_put(skb, offset_and_len & 0xffff); 1052 return skb; 1053 } 1054 1055 static u32 __bnxt_rx_agg_pages(struct bnxt *bp, 1056 struct bnxt_cp_ring_info *cpr, 1057 struct skb_shared_info *shinfo, 1058 u16 idx, u32 agg_bufs, bool tpa, 1059 struct xdp_buff *xdp) 1060 { 1061 struct bnxt_napi *bnapi = cpr->bnapi; 1062 struct pci_dev *pdev = bp->pdev; 1063 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 1064 u16 prod = rxr->rx_agg_prod; 1065 u32 i, total_frag_len = 0; 1066 bool p5_tpa = false; 1067 1068 if ((bp->flags & BNXT_FLAG_CHIP_P5) && tpa) 1069 p5_tpa = true; 1070 1071 for (i = 0; i < agg_bufs; i++) { 1072 skb_frag_t *frag = &shinfo->frags[i]; 1073 u16 cons, frag_len; 1074 struct rx_agg_cmp *agg; 1075 struct bnxt_sw_rx_agg_bd *cons_rx_buf; 1076 struct page *page; 1077 dma_addr_t mapping; 1078 1079 if (p5_tpa) 1080 agg = bnxt_get_tpa_agg_p5(bp, rxr, idx, i); 1081 else 1082 agg = bnxt_get_agg(bp, cpr, idx, i); 1083 cons = agg->rx_agg_cmp_opaque; 1084 frag_len = (le32_to_cpu(agg->rx_agg_cmp_len_flags_type) & 1085 RX_AGG_CMP_LEN) >> RX_AGG_CMP_LEN_SHIFT; 1086 1087 cons_rx_buf = &rxr->rx_agg_ring[cons]; 1088 skb_frag_fill_page_desc(frag, cons_rx_buf->page, 1089 cons_rx_buf->offset, frag_len); 1090 shinfo->nr_frags = i + 1; 1091 __clear_bit(cons, rxr->rx_agg_bmap); 1092 1093 /* It is possible for bnxt_alloc_rx_page() to allocate 1094 * a sw_prod index that equals the cons index, so we 1095 * need to clear the cons entry now. 1096 */ 1097 mapping = cons_rx_buf->mapping; 1098 page = cons_rx_buf->page; 1099 cons_rx_buf->page = NULL; 1100 1101 if (xdp && page_is_pfmemalloc(page)) 1102 xdp_buff_set_frag_pfmemalloc(xdp); 1103 1104 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_ATOMIC) != 0) { 1105 --shinfo->nr_frags; 1106 cons_rx_buf->page = page; 1107 1108 /* Update prod since possibly some pages have been 1109 * allocated already. 1110 */ 1111 rxr->rx_agg_prod = prod; 1112 bnxt_reuse_rx_agg_bufs(cpr, idx, i, agg_bufs - i, tpa); 1113 return 0; 1114 } 1115 1116 dma_unmap_page_attrs(&pdev->dev, mapping, BNXT_RX_PAGE_SIZE, 1117 bp->rx_dir, 1118 DMA_ATTR_WEAK_ORDERING); 1119 1120 total_frag_len += frag_len; 1121 prod = NEXT_RX_AGG(prod); 1122 } 1123 rxr->rx_agg_prod = prod; 1124 return total_frag_len; 1125 } 1126 1127 static struct sk_buff *bnxt_rx_agg_pages_skb(struct bnxt *bp, 1128 struct bnxt_cp_ring_info *cpr, 1129 struct sk_buff *skb, u16 idx, 1130 u32 agg_bufs, bool tpa) 1131 { 1132 struct skb_shared_info *shinfo = skb_shinfo(skb); 1133 u32 total_frag_len = 0; 1134 1135 total_frag_len = __bnxt_rx_agg_pages(bp, cpr, shinfo, idx, 1136 agg_bufs, tpa, NULL); 1137 if (!total_frag_len) { 1138 dev_kfree_skb(skb); 1139 return NULL; 1140 } 1141 1142 skb->data_len += total_frag_len; 1143 skb->len += total_frag_len; 1144 skb->truesize += PAGE_SIZE * agg_bufs; 1145 return skb; 1146 } 1147 1148 static u32 bnxt_rx_agg_pages_xdp(struct bnxt *bp, 1149 struct bnxt_cp_ring_info *cpr, 1150 struct xdp_buff *xdp, u16 idx, 1151 u32 agg_bufs, bool tpa) 1152 { 1153 struct skb_shared_info *shinfo = xdp_get_shared_info_from_buff(xdp); 1154 u32 total_frag_len = 0; 1155 1156 if (!xdp_buff_has_frags(xdp)) 1157 shinfo->nr_frags = 0; 1158 1159 total_frag_len = __bnxt_rx_agg_pages(bp, cpr, shinfo, 1160 idx, agg_bufs, tpa, xdp); 1161 if (total_frag_len) { 1162 xdp_buff_set_frags_flag(xdp); 1163 shinfo->nr_frags = agg_bufs; 1164 shinfo->xdp_frags_size = total_frag_len; 1165 } 1166 return total_frag_len; 1167 } 1168 1169 static int bnxt_agg_bufs_valid(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, 1170 u8 agg_bufs, u32 *raw_cons) 1171 { 1172 u16 last; 1173 struct rx_agg_cmp *agg; 1174 1175 *raw_cons = ADV_RAW_CMP(*raw_cons, agg_bufs); 1176 last = RING_CMP(*raw_cons); 1177 agg = (struct rx_agg_cmp *) 1178 &cpr->cp_desc_ring[CP_RING(last)][CP_IDX(last)]; 1179 return RX_AGG_CMP_VALID(agg, *raw_cons); 1180 } 1181 1182 static inline struct sk_buff *bnxt_copy_skb(struct bnxt_napi *bnapi, u8 *data, 1183 unsigned int len, 1184 dma_addr_t mapping) 1185 { 1186 struct bnxt *bp = bnapi->bp; 1187 struct pci_dev *pdev = bp->pdev; 1188 struct sk_buff *skb; 1189 1190 skb = napi_alloc_skb(&bnapi->napi, len); 1191 if (!skb) 1192 return NULL; 1193 1194 dma_sync_single_for_cpu(&pdev->dev, mapping, bp->rx_copy_thresh, 1195 bp->rx_dir); 1196 1197 memcpy(skb->data - NET_IP_ALIGN, data - NET_IP_ALIGN, 1198 len + NET_IP_ALIGN); 1199 1200 dma_sync_single_for_device(&pdev->dev, mapping, bp->rx_copy_thresh, 1201 bp->rx_dir); 1202 1203 skb_put(skb, len); 1204 return skb; 1205 } 1206 1207 static int bnxt_discard_rx(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, 1208 u32 *raw_cons, void *cmp) 1209 { 1210 struct rx_cmp *rxcmp = cmp; 1211 u32 tmp_raw_cons = *raw_cons; 1212 u8 cmp_type, agg_bufs = 0; 1213 1214 cmp_type = RX_CMP_TYPE(rxcmp); 1215 1216 if (cmp_type == CMP_TYPE_RX_L2_CMP) { 1217 agg_bufs = (le32_to_cpu(rxcmp->rx_cmp_misc_v1) & 1218 RX_CMP_AGG_BUFS) >> 1219 RX_CMP_AGG_BUFS_SHIFT; 1220 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) { 1221 struct rx_tpa_end_cmp *tpa_end = cmp; 1222 1223 if (bp->flags & BNXT_FLAG_CHIP_P5) 1224 return 0; 1225 1226 agg_bufs = TPA_END_AGG_BUFS(tpa_end); 1227 } 1228 1229 if (agg_bufs) { 1230 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons)) 1231 return -EBUSY; 1232 } 1233 *raw_cons = tmp_raw_cons; 1234 return 0; 1235 } 1236 1237 static void bnxt_queue_fw_reset_work(struct bnxt *bp, unsigned long delay) 1238 { 1239 if (!(test_bit(BNXT_STATE_IN_FW_RESET, &bp->state))) 1240 return; 1241 1242 if (BNXT_PF(bp)) 1243 queue_delayed_work(bnxt_pf_wq, &bp->fw_reset_task, delay); 1244 else 1245 schedule_delayed_work(&bp->fw_reset_task, delay); 1246 } 1247 1248 static void bnxt_queue_sp_work(struct bnxt *bp) 1249 { 1250 if (BNXT_PF(bp)) 1251 queue_work(bnxt_pf_wq, &bp->sp_task); 1252 else 1253 schedule_work(&bp->sp_task); 1254 } 1255 1256 static void bnxt_sched_reset(struct bnxt *bp, struct bnxt_rx_ring_info *rxr) 1257 { 1258 if (!rxr->bnapi->in_reset) { 1259 rxr->bnapi->in_reset = true; 1260 if (bp->flags & BNXT_FLAG_CHIP_P5) 1261 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event); 1262 else 1263 set_bit(BNXT_RST_RING_SP_EVENT, &bp->sp_event); 1264 bnxt_queue_sp_work(bp); 1265 } 1266 rxr->rx_next_cons = 0xffff; 1267 } 1268 1269 static u16 bnxt_alloc_agg_idx(struct bnxt_rx_ring_info *rxr, u16 agg_id) 1270 { 1271 struct bnxt_tpa_idx_map *map = rxr->rx_tpa_idx_map; 1272 u16 idx = agg_id & MAX_TPA_P5_MASK; 1273 1274 if (test_bit(idx, map->agg_idx_bmap)) 1275 idx = find_first_zero_bit(map->agg_idx_bmap, 1276 BNXT_AGG_IDX_BMAP_SIZE); 1277 __set_bit(idx, map->agg_idx_bmap); 1278 map->agg_id_tbl[agg_id] = idx; 1279 return idx; 1280 } 1281 1282 static void bnxt_free_agg_idx(struct bnxt_rx_ring_info *rxr, u16 idx) 1283 { 1284 struct bnxt_tpa_idx_map *map = rxr->rx_tpa_idx_map; 1285 1286 __clear_bit(idx, map->agg_idx_bmap); 1287 } 1288 1289 static u16 bnxt_lookup_agg_idx(struct bnxt_rx_ring_info *rxr, u16 agg_id) 1290 { 1291 struct bnxt_tpa_idx_map *map = rxr->rx_tpa_idx_map; 1292 1293 return map->agg_id_tbl[agg_id]; 1294 } 1295 1296 static void bnxt_tpa_start(struct bnxt *bp, struct bnxt_rx_ring_info *rxr, 1297 struct rx_tpa_start_cmp *tpa_start, 1298 struct rx_tpa_start_cmp_ext *tpa_start1) 1299 { 1300 struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf; 1301 struct bnxt_tpa_info *tpa_info; 1302 u16 cons, prod, agg_id; 1303 struct rx_bd *prod_bd; 1304 dma_addr_t mapping; 1305 1306 if (bp->flags & BNXT_FLAG_CHIP_P5) { 1307 agg_id = TPA_START_AGG_ID_P5(tpa_start); 1308 agg_id = bnxt_alloc_agg_idx(rxr, agg_id); 1309 } else { 1310 agg_id = TPA_START_AGG_ID(tpa_start); 1311 } 1312 cons = tpa_start->rx_tpa_start_cmp_opaque; 1313 prod = rxr->rx_prod; 1314 cons_rx_buf = &rxr->rx_buf_ring[cons]; 1315 prod_rx_buf = &rxr->rx_buf_ring[prod]; 1316 tpa_info = &rxr->rx_tpa[agg_id]; 1317 1318 if (unlikely(cons != rxr->rx_next_cons || 1319 TPA_START_ERROR(tpa_start))) { 1320 netdev_warn(bp->dev, "TPA cons %x, expected cons %x, error code %x\n", 1321 cons, rxr->rx_next_cons, 1322 TPA_START_ERROR_CODE(tpa_start1)); 1323 bnxt_sched_reset(bp, rxr); 1324 return; 1325 } 1326 /* Store cfa_code in tpa_info to use in tpa_end 1327 * completion processing. 1328 */ 1329 tpa_info->cfa_code = TPA_START_CFA_CODE(tpa_start1); 1330 prod_rx_buf->data = tpa_info->data; 1331 prod_rx_buf->data_ptr = tpa_info->data_ptr; 1332 1333 mapping = tpa_info->mapping; 1334 prod_rx_buf->mapping = mapping; 1335 1336 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)]; 1337 1338 prod_bd->rx_bd_haddr = cpu_to_le64(mapping); 1339 1340 tpa_info->data = cons_rx_buf->data; 1341 tpa_info->data_ptr = cons_rx_buf->data_ptr; 1342 cons_rx_buf->data = NULL; 1343 tpa_info->mapping = cons_rx_buf->mapping; 1344 1345 tpa_info->len = 1346 le32_to_cpu(tpa_start->rx_tpa_start_cmp_len_flags_type) >> 1347 RX_TPA_START_CMP_LEN_SHIFT; 1348 if (likely(TPA_START_HASH_VALID(tpa_start))) { 1349 u32 hash_type = TPA_START_HASH_TYPE(tpa_start); 1350 1351 tpa_info->hash_type = PKT_HASH_TYPE_L4; 1352 tpa_info->gso_type = SKB_GSO_TCPV4; 1353 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */ 1354 if (hash_type == 3 || TPA_START_IS_IPV6(tpa_start1)) 1355 tpa_info->gso_type = SKB_GSO_TCPV6; 1356 tpa_info->rss_hash = 1357 le32_to_cpu(tpa_start->rx_tpa_start_cmp_rss_hash); 1358 } else { 1359 tpa_info->hash_type = PKT_HASH_TYPE_NONE; 1360 tpa_info->gso_type = 0; 1361 netif_warn(bp, rx_err, bp->dev, "TPA packet without valid hash\n"); 1362 } 1363 tpa_info->flags2 = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_flags2); 1364 tpa_info->metadata = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_metadata); 1365 tpa_info->hdr_info = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_hdr_info); 1366 tpa_info->agg_count = 0; 1367 1368 rxr->rx_prod = NEXT_RX(prod); 1369 cons = NEXT_RX(cons); 1370 rxr->rx_next_cons = NEXT_RX(cons); 1371 cons_rx_buf = &rxr->rx_buf_ring[cons]; 1372 1373 bnxt_reuse_rx_data(rxr, cons, cons_rx_buf->data); 1374 rxr->rx_prod = NEXT_RX(rxr->rx_prod); 1375 cons_rx_buf->data = NULL; 1376 } 1377 1378 static void bnxt_abort_tpa(struct bnxt_cp_ring_info *cpr, u16 idx, u32 agg_bufs) 1379 { 1380 if (agg_bufs) 1381 bnxt_reuse_rx_agg_bufs(cpr, idx, 0, agg_bufs, true); 1382 } 1383 1384 #ifdef CONFIG_INET 1385 static void bnxt_gro_tunnel(struct sk_buff *skb, __be16 ip_proto) 1386 { 1387 struct udphdr *uh = NULL; 1388 1389 if (ip_proto == htons(ETH_P_IP)) { 1390 struct iphdr *iph = (struct iphdr *)skb->data; 1391 1392 if (iph->protocol == IPPROTO_UDP) 1393 uh = (struct udphdr *)(iph + 1); 1394 } else { 1395 struct ipv6hdr *iph = (struct ipv6hdr *)skb->data; 1396 1397 if (iph->nexthdr == IPPROTO_UDP) 1398 uh = (struct udphdr *)(iph + 1); 1399 } 1400 if (uh) { 1401 if (uh->check) 1402 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL_CSUM; 1403 else 1404 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL; 1405 } 1406 } 1407 #endif 1408 1409 static struct sk_buff *bnxt_gro_func_5731x(struct bnxt_tpa_info *tpa_info, 1410 int payload_off, int tcp_ts, 1411 struct sk_buff *skb) 1412 { 1413 #ifdef CONFIG_INET 1414 struct tcphdr *th; 1415 int len, nw_off; 1416 u16 outer_ip_off, inner_ip_off, inner_mac_off; 1417 u32 hdr_info = tpa_info->hdr_info; 1418 bool loopback = false; 1419 1420 inner_ip_off = BNXT_TPA_INNER_L3_OFF(hdr_info); 1421 inner_mac_off = BNXT_TPA_INNER_L2_OFF(hdr_info); 1422 outer_ip_off = BNXT_TPA_OUTER_L3_OFF(hdr_info); 1423 1424 /* If the packet is an internal loopback packet, the offsets will 1425 * have an extra 4 bytes. 1426 */ 1427 if (inner_mac_off == 4) { 1428 loopback = true; 1429 } else if (inner_mac_off > 4) { 1430 __be16 proto = *((__be16 *)(skb->data + inner_ip_off - 1431 ETH_HLEN - 2)); 1432 1433 /* We only support inner iPv4/ipv6. If we don't see the 1434 * correct protocol ID, it must be a loopback packet where 1435 * the offsets are off by 4. 1436 */ 1437 if (proto != htons(ETH_P_IP) && proto != htons(ETH_P_IPV6)) 1438 loopback = true; 1439 } 1440 if (loopback) { 1441 /* internal loopback packet, subtract all offsets by 4 */ 1442 inner_ip_off -= 4; 1443 inner_mac_off -= 4; 1444 outer_ip_off -= 4; 1445 } 1446 1447 nw_off = inner_ip_off - ETH_HLEN; 1448 skb_set_network_header(skb, nw_off); 1449 if (tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_IP_TYPE) { 1450 struct ipv6hdr *iph = ipv6_hdr(skb); 1451 1452 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr)); 1453 len = skb->len - skb_transport_offset(skb); 1454 th = tcp_hdr(skb); 1455 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0); 1456 } else { 1457 struct iphdr *iph = ip_hdr(skb); 1458 1459 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr)); 1460 len = skb->len - skb_transport_offset(skb); 1461 th = tcp_hdr(skb); 1462 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0); 1463 } 1464 1465 if (inner_mac_off) { /* tunnel */ 1466 __be16 proto = *((__be16 *)(skb->data + outer_ip_off - 1467 ETH_HLEN - 2)); 1468 1469 bnxt_gro_tunnel(skb, proto); 1470 } 1471 #endif 1472 return skb; 1473 } 1474 1475 static struct sk_buff *bnxt_gro_func_5750x(struct bnxt_tpa_info *tpa_info, 1476 int payload_off, int tcp_ts, 1477 struct sk_buff *skb) 1478 { 1479 #ifdef CONFIG_INET 1480 u16 outer_ip_off, inner_ip_off, inner_mac_off; 1481 u32 hdr_info = tpa_info->hdr_info; 1482 int iphdr_len, nw_off; 1483 1484 inner_ip_off = BNXT_TPA_INNER_L3_OFF(hdr_info); 1485 inner_mac_off = BNXT_TPA_INNER_L2_OFF(hdr_info); 1486 outer_ip_off = BNXT_TPA_OUTER_L3_OFF(hdr_info); 1487 1488 nw_off = inner_ip_off - ETH_HLEN; 1489 skb_set_network_header(skb, nw_off); 1490 iphdr_len = (tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_IP_TYPE) ? 1491 sizeof(struct ipv6hdr) : sizeof(struct iphdr); 1492 skb_set_transport_header(skb, nw_off + iphdr_len); 1493 1494 if (inner_mac_off) { /* tunnel */ 1495 __be16 proto = *((__be16 *)(skb->data + outer_ip_off - 1496 ETH_HLEN - 2)); 1497 1498 bnxt_gro_tunnel(skb, proto); 1499 } 1500 #endif 1501 return skb; 1502 } 1503 1504 #define BNXT_IPV4_HDR_SIZE (sizeof(struct iphdr) + sizeof(struct tcphdr)) 1505 #define BNXT_IPV6_HDR_SIZE (sizeof(struct ipv6hdr) + sizeof(struct tcphdr)) 1506 1507 static struct sk_buff *bnxt_gro_func_5730x(struct bnxt_tpa_info *tpa_info, 1508 int payload_off, int tcp_ts, 1509 struct sk_buff *skb) 1510 { 1511 #ifdef CONFIG_INET 1512 struct tcphdr *th; 1513 int len, nw_off, tcp_opt_len = 0; 1514 1515 if (tcp_ts) 1516 tcp_opt_len = 12; 1517 1518 if (tpa_info->gso_type == SKB_GSO_TCPV4) { 1519 struct iphdr *iph; 1520 1521 nw_off = payload_off - BNXT_IPV4_HDR_SIZE - tcp_opt_len - 1522 ETH_HLEN; 1523 skb_set_network_header(skb, nw_off); 1524 iph = ip_hdr(skb); 1525 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr)); 1526 len = skb->len - skb_transport_offset(skb); 1527 th = tcp_hdr(skb); 1528 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0); 1529 } else if (tpa_info->gso_type == SKB_GSO_TCPV6) { 1530 struct ipv6hdr *iph; 1531 1532 nw_off = payload_off - BNXT_IPV6_HDR_SIZE - tcp_opt_len - 1533 ETH_HLEN; 1534 skb_set_network_header(skb, nw_off); 1535 iph = ipv6_hdr(skb); 1536 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr)); 1537 len = skb->len - skb_transport_offset(skb); 1538 th = tcp_hdr(skb); 1539 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0); 1540 } else { 1541 dev_kfree_skb_any(skb); 1542 return NULL; 1543 } 1544 1545 if (nw_off) /* tunnel */ 1546 bnxt_gro_tunnel(skb, skb->protocol); 1547 #endif 1548 return skb; 1549 } 1550 1551 static inline struct sk_buff *bnxt_gro_skb(struct bnxt *bp, 1552 struct bnxt_tpa_info *tpa_info, 1553 struct rx_tpa_end_cmp *tpa_end, 1554 struct rx_tpa_end_cmp_ext *tpa_end1, 1555 struct sk_buff *skb) 1556 { 1557 #ifdef CONFIG_INET 1558 int payload_off; 1559 u16 segs; 1560 1561 segs = TPA_END_TPA_SEGS(tpa_end); 1562 if (segs == 1) 1563 return skb; 1564 1565 NAPI_GRO_CB(skb)->count = segs; 1566 skb_shinfo(skb)->gso_size = 1567 le32_to_cpu(tpa_end1->rx_tpa_end_cmp_seg_len); 1568 skb_shinfo(skb)->gso_type = tpa_info->gso_type; 1569 if (bp->flags & BNXT_FLAG_CHIP_P5) 1570 payload_off = TPA_END_PAYLOAD_OFF_P5(tpa_end1); 1571 else 1572 payload_off = TPA_END_PAYLOAD_OFF(tpa_end); 1573 skb = bp->gro_func(tpa_info, payload_off, TPA_END_GRO_TS(tpa_end), skb); 1574 if (likely(skb)) 1575 tcp_gro_complete(skb); 1576 #endif 1577 return skb; 1578 } 1579 1580 /* Given the cfa_code of a received packet determine which 1581 * netdev (vf-rep or PF) the packet is destined to. 1582 */ 1583 static struct net_device *bnxt_get_pkt_dev(struct bnxt *bp, u16 cfa_code) 1584 { 1585 struct net_device *dev = bnxt_get_vf_rep(bp, cfa_code); 1586 1587 /* if vf-rep dev is NULL, the must belongs to the PF */ 1588 return dev ? dev : bp->dev; 1589 } 1590 1591 static inline struct sk_buff *bnxt_tpa_end(struct bnxt *bp, 1592 struct bnxt_cp_ring_info *cpr, 1593 u32 *raw_cons, 1594 struct rx_tpa_end_cmp *tpa_end, 1595 struct rx_tpa_end_cmp_ext *tpa_end1, 1596 u8 *event) 1597 { 1598 struct bnxt_napi *bnapi = cpr->bnapi; 1599 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 1600 u8 *data_ptr, agg_bufs; 1601 unsigned int len; 1602 struct bnxt_tpa_info *tpa_info; 1603 dma_addr_t mapping; 1604 struct sk_buff *skb; 1605 u16 idx = 0, agg_id; 1606 void *data; 1607 bool gro; 1608 1609 if (unlikely(bnapi->in_reset)) { 1610 int rc = bnxt_discard_rx(bp, cpr, raw_cons, tpa_end); 1611 1612 if (rc < 0) 1613 return ERR_PTR(-EBUSY); 1614 return NULL; 1615 } 1616 1617 if (bp->flags & BNXT_FLAG_CHIP_P5) { 1618 agg_id = TPA_END_AGG_ID_P5(tpa_end); 1619 agg_id = bnxt_lookup_agg_idx(rxr, agg_id); 1620 agg_bufs = TPA_END_AGG_BUFS_P5(tpa_end1); 1621 tpa_info = &rxr->rx_tpa[agg_id]; 1622 if (unlikely(agg_bufs != tpa_info->agg_count)) { 1623 netdev_warn(bp->dev, "TPA end agg_buf %d != expected agg_bufs %d\n", 1624 agg_bufs, tpa_info->agg_count); 1625 agg_bufs = tpa_info->agg_count; 1626 } 1627 tpa_info->agg_count = 0; 1628 *event |= BNXT_AGG_EVENT; 1629 bnxt_free_agg_idx(rxr, agg_id); 1630 idx = agg_id; 1631 gro = !!(bp->flags & BNXT_FLAG_GRO); 1632 } else { 1633 agg_id = TPA_END_AGG_ID(tpa_end); 1634 agg_bufs = TPA_END_AGG_BUFS(tpa_end); 1635 tpa_info = &rxr->rx_tpa[agg_id]; 1636 idx = RING_CMP(*raw_cons); 1637 if (agg_bufs) { 1638 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, raw_cons)) 1639 return ERR_PTR(-EBUSY); 1640 1641 *event |= BNXT_AGG_EVENT; 1642 idx = NEXT_CMP(idx); 1643 } 1644 gro = !!TPA_END_GRO(tpa_end); 1645 } 1646 data = tpa_info->data; 1647 data_ptr = tpa_info->data_ptr; 1648 prefetch(data_ptr); 1649 len = tpa_info->len; 1650 mapping = tpa_info->mapping; 1651 1652 if (unlikely(agg_bufs > MAX_SKB_FRAGS || TPA_END_ERRORS(tpa_end1))) { 1653 bnxt_abort_tpa(cpr, idx, agg_bufs); 1654 if (agg_bufs > MAX_SKB_FRAGS) 1655 netdev_warn(bp->dev, "TPA frags %d exceeded MAX_SKB_FRAGS %d\n", 1656 agg_bufs, (int)MAX_SKB_FRAGS); 1657 return NULL; 1658 } 1659 1660 if (len <= bp->rx_copy_thresh) { 1661 skb = bnxt_copy_skb(bnapi, data_ptr, len, mapping); 1662 if (!skb) { 1663 bnxt_abort_tpa(cpr, idx, agg_bufs); 1664 cpr->sw_stats.rx.rx_oom_discards += 1; 1665 return NULL; 1666 } 1667 } else { 1668 u8 *new_data; 1669 dma_addr_t new_mapping; 1670 1671 new_data = __bnxt_alloc_rx_frag(bp, &new_mapping, GFP_ATOMIC); 1672 if (!new_data) { 1673 bnxt_abort_tpa(cpr, idx, agg_bufs); 1674 cpr->sw_stats.rx.rx_oom_discards += 1; 1675 return NULL; 1676 } 1677 1678 tpa_info->data = new_data; 1679 tpa_info->data_ptr = new_data + bp->rx_offset; 1680 tpa_info->mapping = new_mapping; 1681 1682 skb = build_skb(data, bp->rx_buf_size); 1683 dma_unmap_single_attrs(&bp->pdev->dev, mapping, 1684 bp->rx_buf_use_size, bp->rx_dir, 1685 DMA_ATTR_WEAK_ORDERING); 1686 1687 if (!skb) { 1688 skb_free_frag(data); 1689 bnxt_abort_tpa(cpr, idx, agg_bufs); 1690 cpr->sw_stats.rx.rx_oom_discards += 1; 1691 return NULL; 1692 } 1693 skb_reserve(skb, bp->rx_offset); 1694 skb_put(skb, len); 1695 } 1696 1697 if (agg_bufs) { 1698 skb = bnxt_rx_agg_pages_skb(bp, cpr, skb, idx, agg_bufs, true); 1699 if (!skb) { 1700 /* Page reuse already handled by bnxt_rx_pages(). */ 1701 cpr->sw_stats.rx.rx_oom_discards += 1; 1702 return NULL; 1703 } 1704 } 1705 1706 skb->protocol = 1707 eth_type_trans(skb, bnxt_get_pkt_dev(bp, tpa_info->cfa_code)); 1708 1709 if (tpa_info->hash_type != PKT_HASH_TYPE_NONE) 1710 skb_set_hash(skb, tpa_info->rss_hash, tpa_info->hash_type); 1711 1712 if ((tpa_info->flags2 & RX_CMP_FLAGS2_META_FORMAT_VLAN) && 1713 (skb->dev->features & BNXT_HW_FEATURE_VLAN_ALL_RX)) { 1714 __be16 vlan_proto = htons(tpa_info->metadata >> 1715 RX_CMP_FLAGS2_METADATA_TPID_SFT); 1716 u16 vtag = tpa_info->metadata & RX_CMP_FLAGS2_METADATA_TCI_MASK; 1717 1718 if (eth_type_vlan(vlan_proto)) { 1719 __vlan_hwaccel_put_tag(skb, vlan_proto, vtag); 1720 } else { 1721 dev_kfree_skb(skb); 1722 return NULL; 1723 } 1724 } 1725 1726 skb_checksum_none_assert(skb); 1727 if (likely(tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_L4_CS_CALC)) { 1728 skb->ip_summed = CHECKSUM_UNNECESSARY; 1729 skb->csum_level = 1730 (tpa_info->flags2 & RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3; 1731 } 1732 1733 if (gro) 1734 skb = bnxt_gro_skb(bp, tpa_info, tpa_end, tpa_end1, skb); 1735 1736 return skb; 1737 } 1738 1739 static void bnxt_tpa_agg(struct bnxt *bp, struct bnxt_rx_ring_info *rxr, 1740 struct rx_agg_cmp *rx_agg) 1741 { 1742 u16 agg_id = TPA_AGG_AGG_ID(rx_agg); 1743 struct bnxt_tpa_info *tpa_info; 1744 1745 agg_id = bnxt_lookup_agg_idx(rxr, agg_id); 1746 tpa_info = &rxr->rx_tpa[agg_id]; 1747 BUG_ON(tpa_info->agg_count >= MAX_SKB_FRAGS); 1748 tpa_info->agg_arr[tpa_info->agg_count++] = *rx_agg; 1749 } 1750 1751 static void bnxt_deliver_skb(struct bnxt *bp, struct bnxt_napi *bnapi, 1752 struct sk_buff *skb) 1753 { 1754 if (skb->dev != bp->dev) { 1755 /* this packet belongs to a vf-rep */ 1756 bnxt_vf_rep_rx(bp, skb); 1757 return; 1758 } 1759 skb_record_rx_queue(skb, bnapi->index); 1760 napi_gro_receive(&bnapi->napi, skb); 1761 } 1762 1763 /* returns the following: 1764 * 1 - 1 packet successfully received 1765 * 0 - successful TPA_START, packet not completed yet 1766 * -EBUSY - completion ring does not have all the agg buffers yet 1767 * -ENOMEM - packet aborted due to out of memory 1768 * -EIO - packet aborted due to hw error indicated in BD 1769 */ 1770 static int bnxt_rx_pkt(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, 1771 u32 *raw_cons, u8 *event) 1772 { 1773 struct bnxt_napi *bnapi = cpr->bnapi; 1774 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 1775 struct net_device *dev = bp->dev; 1776 struct rx_cmp *rxcmp; 1777 struct rx_cmp_ext *rxcmp1; 1778 u32 tmp_raw_cons = *raw_cons; 1779 u16 cfa_code, cons, prod, cp_cons = RING_CMP(tmp_raw_cons); 1780 struct bnxt_sw_rx_bd *rx_buf; 1781 unsigned int len; 1782 u8 *data_ptr, agg_bufs, cmp_type; 1783 bool xdp_active = false; 1784 dma_addr_t dma_addr; 1785 struct sk_buff *skb; 1786 struct xdp_buff xdp; 1787 u32 flags, misc; 1788 void *data; 1789 int rc = 0; 1790 1791 rxcmp = (struct rx_cmp *) 1792 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 1793 1794 cmp_type = RX_CMP_TYPE(rxcmp); 1795 1796 if (cmp_type == CMP_TYPE_RX_TPA_AGG_CMP) { 1797 bnxt_tpa_agg(bp, rxr, (struct rx_agg_cmp *)rxcmp); 1798 goto next_rx_no_prod_no_len; 1799 } 1800 1801 tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons); 1802 cp_cons = RING_CMP(tmp_raw_cons); 1803 rxcmp1 = (struct rx_cmp_ext *) 1804 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 1805 1806 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons)) 1807 return -EBUSY; 1808 1809 /* The valid test of the entry must be done first before 1810 * reading any further. 1811 */ 1812 dma_rmb(); 1813 prod = rxr->rx_prod; 1814 1815 if (cmp_type == CMP_TYPE_RX_L2_TPA_START_CMP) { 1816 bnxt_tpa_start(bp, rxr, (struct rx_tpa_start_cmp *)rxcmp, 1817 (struct rx_tpa_start_cmp_ext *)rxcmp1); 1818 1819 *event |= BNXT_RX_EVENT; 1820 goto next_rx_no_prod_no_len; 1821 1822 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) { 1823 skb = bnxt_tpa_end(bp, cpr, &tmp_raw_cons, 1824 (struct rx_tpa_end_cmp *)rxcmp, 1825 (struct rx_tpa_end_cmp_ext *)rxcmp1, event); 1826 1827 if (IS_ERR(skb)) 1828 return -EBUSY; 1829 1830 rc = -ENOMEM; 1831 if (likely(skb)) { 1832 bnxt_deliver_skb(bp, bnapi, skb); 1833 rc = 1; 1834 } 1835 *event |= BNXT_RX_EVENT; 1836 goto next_rx_no_prod_no_len; 1837 } 1838 1839 cons = rxcmp->rx_cmp_opaque; 1840 if (unlikely(cons != rxr->rx_next_cons)) { 1841 int rc1 = bnxt_discard_rx(bp, cpr, &tmp_raw_cons, rxcmp); 1842 1843 /* 0xffff is forced error, don't print it */ 1844 if (rxr->rx_next_cons != 0xffff) 1845 netdev_warn(bp->dev, "RX cons %x != expected cons %x\n", 1846 cons, rxr->rx_next_cons); 1847 bnxt_sched_reset(bp, rxr); 1848 if (rc1) 1849 return rc1; 1850 goto next_rx_no_prod_no_len; 1851 } 1852 rx_buf = &rxr->rx_buf_ring[cons]; 1853 data = rx_buf->data; 1854 data_ptr = rx_buf->data_ptr; 1855 prefetch(data_ptr); 1856 1857 misc = le32_to_cpu(rxcmp->rx_cmp_misc_v1); 1858 agg_bufs = (misc & RX_CMP_AGG_BUFS) >> RX_CMP_AGG_BUFS_SHIFT; 1859 1860 if (agg_bufs) { 1861 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons)) 1862 return -EBUSY; 1863 1864 cp_cons = NEXT_CMP(cp_cons); 1865 *event |= BNXT_AGG_EVENT; 1866 } 1867 *event |= BNXT_RX_EVENT; 1868 1869 rx_buf->data = NULL; 1870 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L2_ERRORS) { 1871 u32 rx_err = le32_to_cpu(rxcmp1->rx_cmp_cfa_code_errors_v2); 1872 1873 bnxt_reuse_rx_data(rxr, cons, data); 1874 if (agg_bufs) 1875 bnxt_reuse_rx_agg_bufs(cpr, cp_cons, 0, agg_bufs, 1876 false); 1877 1878 rc = -EIO; 1879 if (rx_err & RX_CMPL_ERRORS_BUFFER_ERROR_MASK) { 1880 bnapi->cp_ring.sw_stats.rx.rx_buf_errors++; 1881 if (!(bp->flags & BNXT_FLAG_CHIP_P5) && 1882 !(bp->fw_cap & BNXT_FW_CAP_RING_MONITOR)) { 1883 netdev_warn_once(bp->dev, "RX buffer error %x\n", 1884 rx_err); 1885 bnxt_sched_reset(bp, rxr); 1886 } 1887 } 1888 goto next_rx_no_len; 1889 } 1890 1891 flags = le32_to_cpu(rxcmp->rx_cmp_len_flags_type); 1892 len = flags >> RX_CMP_LEN_SHIFT; 1893 dma_addr = rx_buf->mapping; 1894 1895 if (bnxt_xdp_attached(bp, rxr)) { 1896 bnxt_xdp_buff_init(bp, rxr, cons, data_ptr, len, &xdp); 1897 if (agg_bufs) { 1898 u32 frag_len = bnxt_rx_agg_pages_xdp(bp, cpr, &xdp, 1899 cp_cons, agg_bufs, 1900 false); 1901 if (!frag_len) { 1902 cpr->sw_stats.rx.rx_oom_discards += 1; 1903 rc = -ENOMEM; 1904 goto next_rx; 1905 } 1906 } 1907 xdp_active = true; 1908 } 1909 1910 if (xdp_active) { 1911 if (bnxt_rx_xdp(bp, rxr, cons, xdp, data, &data_ptr, &len, event)) { 1912 rc = 1; 1913 goto next_rx; 1914 } 1915 } 1916 1917 if (len <= bp->rx_copy_thresh) { 1918 skb = bnxt_copy_skb(bnapi, data_ptr, len, dma_addr); 1919 bnxt_reuse_rx_data(rxr, cons, data); 1920 if (!skb) { 1921 if (agg_bufs) { 1922 if (!xdp_active) 1923 bnxt_reuse_rx_agg_bufs(cpr, cp_cons, 0, 1924 agg_bufs, false); 1925 else 1926 bnxt_xdp_buff_frags_free(rxr, &xdp); 1927 } 1928 cpr->sw_stats.rx.rx_oom_discards += 1; 1929 rc = -ENOMEM; 1930 goto next_rx; 1931 } 1932 } else { 1933 u32 payload; 1934 1935 if (rx_buf->data_ptr == data_ptr) 1936 payload = misc & RX_CMP_PAYLOAD_OFFSET; 1937 else 1938 payload = 0; 1939 skb = bp->rx_skb_func(bp, rxr, cons, data, data_ptr, dma_addr, 1940 payload | len); 1941 if (!skb) { 1942 cpr->sw_stats.rx.rx_oom_discards += 1; 1943 rc = -ENOMEM; 1944 goto next_rx; 1945 } 1946 } 1947 1948 if (agg_bufs) { 1949 if (!xdp_active) { 1950 skb = bnxt_rx_agg_pages_skb(bp, cpr, skb, cp_cons, agg_bufs, false); 1951 if (!skb) { 1952 cpr->sw_stats.rx.rx_oom_discards += 1; 1953 rc = -ENOMEM; 1954 goto next_rx; 1955 } 1956 } else { 1957 skb = bnxt_xdp_build_skb(bp, skb, agg_bufs, rxr->page_pool, &xdp, rxcmp1); 1958 if (!skb) { 1959 /* we should be able to free the old skb here */ 1960 bnxt_xdp_buff_frags_free(rxr, &xdp); 1961 cpr->sw_stats.rx.rx_oom_discards += 1; 1962 rc = -ENOMEM; 1963 goto next_rx; 1964 } 1965 } 1966 } 1967 1968 if (RX_CMP_HASH_VALID(rxcmp)) { 1969 u32 hash_type = RX_CMP_HASH_TYPE(rxcmp); 1970 enum pkt_hash_types type = PKT_HASH_TYPE_L4; 1971 1972 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */ 1973 if (hash_type != 1 && hash_type != 3) 1974 type = PKT_HASH_TYPE_L3; 1975 skb_set_hash(skb, le32_to_cpu(rxcmp->rx_cmp_rss_hash), type); 1976 } 1977 1978 cfa_code = RX_CMP_CFA_CODE(rxcmp1); 1979 skb->protocol = eth_type_trans(skb, bnxt_get_pkt_dev(bp, cfa_code)); 1980 1981 if ((rxcmp1->rx_cmp_flags2 & 1982 cpu_to_le32(RX_CMP_FLAGS2_META_FORMAT_VLAN)) && 1983 (skb->dev->features & BNXT_HW_FEATURE_VLAN_ALL_RX)) { 1984 u32 meta_data = le32_to_cpu(rxcmp1->rx_cmp_meta_data); 1985 u16 vtag = meta_data & RX_CMP_FLAGS2_METADATA_TCI_MASK; 1986 __be16 vlan_proto = htons(meta_data >> 1987 RX_CMP_FLAGS2_METADATA_TPID_SFT); 1988 1989 if (eth_type_vlan(vlan_proto)) { 1990 __vlan_hwaccel_put_tag(skb, vlan_proto, vtag); 1991 } else { 1992 dev_kfree_skb(skb); 1993 goto next_rx; 1994 } 1995 } 1996 1997 skb_checksum_none_assert(skb); 1998 if (RX_CMP_L4_CS_OK(rxcmp1)) { 1999 if (dev->features & NETIF_F_RXCSUM) { 2000 skb->ip_summed = CHECKSUM_UNNECESSARY; 2001 skb->csum_level = RX_CMP_ENCAP(rxcmp1); 2002 } 2003 } else { 2004 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS) { 2005 if (dev->features & NETIF_F_RXCSUM) 2006 bnapi->cp_ring.sw_stats.rx.rx_l4_csum_errors++; 2007 } 2008 } 2009 2010 if (unlikely((flags & RX_CMP_FLAGS_ITYPES_MASK) == 2011 RX_CMP_FLAGS_ITYPE_PTP_W_TS) || bp->ptp_all_rx_tstamp) { 2012 if (bp->flags & BNXT_FLAG_CHIP_P5) { 2013 u32 cmpl_ts = le32_to_cpu(rxcmp1->rx_cmp_timestamp); 2014 u64 ns, ts; 2015 2016 if (!bnxt_get_rx_ts_p5(bp, &ts, cmpl_ts)) { 2017 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 2018 2019 spin_lock_bh(&ptp->ptp_lock); 2020 ns = timecounter_cyc2time(&ptp->tc, ts); 2021 spin_unlock_bh(&ptp->ptp_lock); 2022 memset(skb_hwtstamps(skb), 0, 2023 sizeof(*skb_hwtstamps(skb))); 2024 skb_hwtstamps(skb)->hwtstamp = ns_to_ktime(ns); 2025 } 2026 } 2027 } 2028 bnxt_deliver_skb(bp, bnapi, skb); 2029 rc = 1; 2030 2031 next_rx: 2032 cpr->rx_packets += 1; 2033 cpr->rx_bytes += len; 2034 2035 next_rx_no_len: 2036 rxr->rx_prod = NEXT_RX(prod); 2037 rxr->rx_next_cons = NEXT_RX(cons); 2038 2039 next_rx_no_prod_no_len: 2040 *raw_cons = tmp_raw_cons; 2041 2042 return rc; 2043 } 2044 2045 /* In netpoll mode, if we are using a combined completion ring, we need to 2046 * discard the rx packets and recycle the buffers. 2047 */ 2048 static int bnxt_force_rx_discard(struct bnxt *bp, 2049 struct bnxt_cp_ring_info *cpr, 2050 u32 *raw_cons, u8 *event) 2051 { 2052 u32 tmp_raw_cons = *raw_cons; 2053 struct rx_cmp_ext *rxcmp1; 2054 struct rx_cmp *rxcmp; 2055 u16 cp_cons; 2056 u8 cmp_type; 2057 int rc; 2058 2059 cp_cons = RING_CMP(tmp_raw_cons); 2060 rxcmp = (struct rx_cmp *) 2061 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 2062 2063 tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons); 2064 cp_cons = RING_CMP(tmp_raw_cons); 2065 rxcmp1 = (struct rx_cmp_ext *) 2066 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 2067 2068 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons)) 2069 return -EBUSY; 2070 2071 /* The valid test of the entry must be done first before 2072 * reading any further. 2073 */ 2074 dma_rmb(); 2075 cmp_type = RX_CMP_TYPE(rxcmp); 2076 if (cmp_type == CMP_TYPE_RX_L2_CMP) { 2077 rxcmp1->rx_cmp_cfa_code_errors_v2 |= 2078 cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR); 2079 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) { 2080 struct rx_tpa_end_cmp_ext *tpa_end1; 2081 2082 tpa_end1 = (struct rx_tpa_end_cmp_ext *)rxcmp1; 2083 tpa_end1->rx_tpa_end_cmp_errors_v2 |= 2084 cpu_to_le32(RX_TPA_END_CMP_ERRORS); 2085 } 2086 rc = bnxt_rx_pkt(bp, cpr, raw_cons, event); 2087 if (rc && rc != -EBUSY) 2088 cpr->sw_stats.rx.rx_netpoll_discards += 1; 2089 return rc; 2090 } 2091 2092 u32 bnxt_fw_health_readl(struct bnxt *bp, int reg_idx) 2093 { 2094 struct bnxt_fw_health *fw_health = bp->fw_health; 2095 u32 reg = fw_health->regs[reg_idx]; 2096 u32 reg_type, reg_off, val = 0; 2097 2098 reg_type = BNXT_FW_HEALTH_REG_TYPE(reg); 2099 reg_off = BNXT_FW_HEALTH_REG_OFF(reg); 2100 switch (reg_type) { 2101 case BNXT_FW_HEALTH_REG_TYPE_CFG: 2102 pci_read_config_dword(bp->pdev, reg_off, &val); 2103 break; 2104 case BNXT_FW_HEALTH_REG_TYPE_GRC: 2105 reg_off = fw_health->mapped_regs[reg_idx]; 2106 fallthrough; 2107 case BNXT_FW_HEALTH_REG_TYPE_BAR0: 2108 val = readl(bp->bar0 + reg_off); 2109 break; 2110 case BNXT_FW_HEALTH_REG_TYPE_BAR1: 2111 val = readl(bp->bar1 + reg_off); 2112 break; 2113 } 2114 if (reg_idx == BNXT_FW_RESET_INPROG_REG) 2115 val &= fw_health->fw_reset_inprog_reg_mask; 2116 return val; 2117 } 2118 2119 static u16 bnxt_agg_ring_id_to_grp_idx(struct bnxt *bp, u16 ring_id) 2120 { 2121 int i; 2122 2123 for (i = 0; i < bp->rx_nr_rings; i++) { 2124 u16 grp_idx = bp->rx_ring[i].bnapi->index; 2125 struct bnxt_ring_grp_info *grp_info; 2126 2127 grp_info = &bp->grp_info[grp_idx]; 2128 if (grp_info->agg_fw_ring_id == ring_id) 2129 return grp_idx; 2130 } 2131 return INVALID_HW_RING_ID; 2132 } 2133 2134 static void bnxt_event_error_report(struct bnxt *bp, u32 data1, u32 data2) 2135 { 2136 u32 err_type = BNXT_EVENT_ERROR_REPORT_TYPE(data1); 2137 2138 switch (err_type) { 2139 case ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL: 2140 netdev_err(bp->dev, "1PPS: Received invalid signal on pin%lu from the external source. Please fix the signal and reconfigure the pin\n", 2141 BNXT_EVENT_INVALID_SIGNAL_DATA(data2)); 2142 break; 2143 case ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_PAUSE_STORM: 2144 netdev_warn(bp->dev, "Pause Storm detected!\n"); 2145 break; 2146 case ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD: 2147 netdev_warn(bp->dev, "One or more MMIO doorbells dropped by the device!\n"); 2148 break; 2149 default: 2150 netdev_err(bp->dev, "FW reported unknown error type %u\n", 2151 err_type); 2152 break; 2153 } 2154 } 2155 2156 #define BNXT_GET_EVENT_PORT(data) \ 2157 ((data) & \ 2158 ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK) 2159 2160 #define BNXT_EVENT_RING_TYPE(data2) \ 2161 ((data2) & \ 2162 ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_MASK) 2163 2164 #define BNXT_EVENT_RING_TYPE_RX(data2) \ 2165 (BNXT_EVENT_RING_TYPE(data2) == \ 2166 ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_RX) 2167 2168 #define BNXT_EVENT_PHC_EVENT_TYPE(data1) \ 2169 (((data1) & ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_MASK) >>\ 2170 ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_SFT) 2171 2172 #define BNXT_EVENT_PHC_RTC_UPDATE(data1) \ 2173 (((data1) & ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_PHC_TIME_MSB_MASK) >>\ 2174 ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_PHC_TIME_MSB_SFT) 2175 2176 #define BNXT_PHC_BITS 48 2177 2178 static int bnxt_async_event_process(struct bnxt *bp, 2179 struct hwrm_async_event_cmpl *cmpl) 2180 { 2181 u16 event_id = le16_to_cpu(cmpl->event_id); 2182 u32 data1 = le32_to_cpu(cmpl->event_data1); 2183 u32 data2 = le32_to_cpu(cmpl->event_data2); 2184 2185 netdev_dbg(bp->dev, "hwrm event 0x%x {0x%x, 0x%x}\n", 2186 event_id, data1, data2); 2187 2188 /* TODO CHIMP_FW: Define event id's for link change, error etc */ 2189 switch (event_id) { 2190 case ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE: { 2191 struct bnxt_link_info *link_info = &bp->link_info; 2192 2193 if (BNXT_VF(bp)) 2194 goto async_event_process_exit; 2195 2196 /* print unsupported speed warning in forced speed mode only */ 2197 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED) && 2198 (data1 & 0x20000)) { 2199 u16 fw_speed = link_info->force_link_speed; 2200 u32 speed = bnxt_fw_to_ethtool_speed(fw_speed); 2201 2202 if (speed != SPEED_UNKNOWN) 2203 netdev_warn(bp->dev, "Link speed %d no longer supported\n", 2204 speed); 2205 } 2206 set_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT, &bp->sp_event); 2207 } 2208 fallthrough; 2209 case ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE: 2210 case ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE: 2211 set_bit(BNXT_LINK_CFG_CHANGE_SP_EVENT, &bp->sp_event); 2212 fallthrough; 2213 case ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE: 2214 set_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event); 2215 break; 2216 case ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD: 2217 set_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event); 2218 break; 2219 case ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED: { 2220 u16 port_id = BNXT_GET_EVENT_PORT(data1); 2221 2222 if (BNXT_VF(bp)) 2223 break; 2224 2225 if (bp->pf.port_id != port_id) 2226 break; 2227 2228 set_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event); 2229 break; 2230 } 2231 case ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE: 2232 if (BNXT_PF(bp)) 2233 goto async_event_process_exit; 2234 set_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event); 2235 break; 2236 case ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY: { 2237 char *type_str = "Solicited"; 2238 2239 if (!bp->fw_health) 2240 goto async_event_process_exit; 2241 2242 bp->fw_reset_timestamp = jiffies; 2243 bp->fw_reset_min_dsecs = cmpl->timestamp_lo; 2244 if (!bp->fw_reset_min_dsecs) 2245 bp->fw_reset_min_dsecs = BNXT_DFLT_FW_RST_MIN_DSECS; 2246 bp->fw_reset_max_dsecs = le16_to_cpu(cmpl->timestamp_hi); 2247 if (!bp->fw_reset_max_dsecs) 2248 bp->fw_reset_max_dsecs = BNXT_DFLT_FW_RST_MAX_DSECS; 2249 if (EVENT_DATA1_RESET_NOTIFY_FW_ACTIVATION(data1)) { 2250 set_bit(BNXT_STATE_FW_ACTIVATE_RESET, &bp->state); 2251 } else if (EVENT_DATA1_RESET_NOTIFY_FATAL(data1)) { 2252 type_str = "Fatal"; 2253 bp->fw_health->fatalities++; 2254 set_bit(BNXT_STATE_FW_FATAL_COND, &bp->state); 2255 } else if (data2 && BNXT_FW_STATUS_HEALTHY != 2256 EVENT_DATA2_RESET_NOTIFY_FW_STATUS_CODE(data2)) { 2257 type_str = "Non-fatal"; 2258 bp->fw_health->survivals++; 2259 set_bit(BNXT_STATE_FW_NON_FATAL_COND, &bp->state); 2260 } 2261 netif_warn(bp, hw, bp->dev, 2262 "%s firmware reset event, data1: 0x%x, data2: 0x%x, min wait %u ms, max wait %u ms\n", 2263 type_str, data1, data2, 2264 bp->fw_reset_min_dsecs * 100, 2265 bp->fw_reset_max_dsecs * 100); 2266 set_bit(BNXT_FW_RESET_NOTIFY_SP_EVENT, &bp->sp_event); 2267 break; 2268 } 2269 case ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY: { 2270 struct bnxt_fw_health *fw_health = bp->fw_health; 2271 char *status_desc = "healthy"; 2272 u32 status; 2273 2274 if (!fw_health) 2275 goto async_event_process_exit; 2276 2277 if (!EVENT_DATA1_RECOVERY_ENABLED(data1)) { 2278 fw_health->enabled = false; 2279 netif_info(bp, drv, bp->dev, "Driver recovery watchdog is disabled\n"); 2280 break; 2281 } 2282 fw_health->primary = EVENT_DATA1_RECOVERY_MASTER_FUNC(data1); 2283 fw_health->tmr_multiplier = 2284 DIV_ROUND_UP(fw_health->polling_dsecs * HZ, 2285 bp->current_interval * 10); 2286 fw_health->tmr_counter = fw_health->tmr_multiplier; 2287 if (!fw_health->enabled) 2288 fw_health->last_fw_heartbeat = 2289 bnxt_fw_health_readl(bp, BNXT_FW_HEARTBEAT_REG); 2290 fw_health->last_fw_reset_cnt = 2291 bnxt_fw_health_readl(bp, BNXT_FW_RESET_CNT_REG); 2292 status = bnxt_fw_health_readl(bp, BNXT_FW_HEALTH_REG); 2293 if (status != BNXT_FW_STATUS_HEALTHY) 2294 status_desc = "unhealthy"; 2295 netif_info(bp, drv, bp->dev, 2296 "Driver recovery watchdog, role: %s, firmware status: 0x%x (%s), resets: %u\n", 2297 fw_health->primary ? "primary" : "backup", status, 2298 status_desc, fw_health->last_fw_reset_cnt); 2299 if (!fw_health->enabled) { 2300 /* Make sure tmr_counter is set and visible to 2301 * bnxt_health_check() before setting enabled to true. 2302 */ 2303 smp_wmb(); 2304 fw_health->enabled = true; 2305 } 2306 goto async_event_process_exit; 2307 } 2308 case ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION: 2309 netif_notice(bp, hw, bp->dev, 2310 "Received firmware debug notification, data1: 0x%x, data2: 0x%x\n", 2311 data1, data2); 2312 goto async_event_process_exit; 2313 case ASYNC_EVENT_CMPL_EVENT_ID_RING_MONITOR_MSG: { 2314 struct bnxt_rx_ring_info *rxr; 2315 u16 grp_idx; 2316 2317 if (bp->flags & BNXT_FLAG_CHIP_P5) 2318 goto async_event_process_exit; 2319 2320 netdev_warn(bp->dev, "Ring monitor event, ring type %lu id 0x%x\n", 2321 BNXT_EVENT_RING_TYPE(data2), data1); 2322 if (!BNXT_EVENT_RING_TYPE_RX(data2)) 2323 goto async_event_process_exit; 2324 2325 grp_idx = bnxt_agg_ring_id_to_grp_idx(bp, data1); 2326 if (grp_idx == INVALID_HW_RING_ID) { 2327 netdev_warn(bp->dev, "Unknown RX agg ring id 0x%x\n", 2328 data1); 2329 goto async_event_process_exit; 2330 } 2331 rxr = bp->bnapi[grp_idx]->rx_ring; 2332 bnxt_sched_reset(bp, rxr); 2333 goto async_event_process_exit; 2334 } 2335 case ASYNC_EVENT_CMPL_EVENT_ID_ECHO_REQUEST: { 2336 struct bnxt_fw_health *fw_health = bp->fw_health; 2337 2338 netif_notice(bp, hw, bp->dev, 2339 "Received firmware echo request, data1: 0x%x, data2: 0x%x\n", 2340 data1, data2); 2341 if (fw_health) { 2342 fw_health->echo_req_data1 = data1; 2343 fw_health->echo_req_data2 = data2; 2344 set_bit(BNXT_FW_ECHO_REQUEST_SP_EVENT, &bp->sp_event); 2345 break; 2346 } 2347 goto async_event_process_exit; 2348 } 2349 case ASYNC_EVENT_CMPL_EVENT_ID_PPS_TIMESTAMP: { 2350 bnxt_ptp_pps_event(bp, data1, data2); 2351 goto async_event_process_exit; 2352 } 2353 case ASYNC_EVENT_CMPL_EVENT_ID_ERROR_REPORT: { 2354 bnxt_event_error_report(bp, data1, data2); 2355 goto async_event_process_exit; 2356 } 2357 case ASYNC_EVENT_CMPL_EVENT_ID_PHC_UPDATE: { 2358 switch (BNXT_EVENT_PHC_EVENT_TYPE(data1)) { 2359 case ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_RTC_UPDATE: 2360 if (BNXT_PTP_USE_RTC(bp)) { 2361 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 2362 u64 ns; 2363 2364 spin_lock_bh(&ptp->ptp_lock); 2365 bnxt_ptp_update_current_time(bp); 2366 ns = (((u64)BNXT_EVENT_PHC_RTC_UPDATE(data1) << 2367 BNXT_PHC_BITS) | ptp->current_time); 2368 bnxt_ptp_rtc_timecounter_init(ptp, ns); 2369 spin_unlock_bh(&ptp->ptp_lock); 2370 } 2371 break; 2372 } 2373 goto async_event_process_exit; 2374 } 2375 case ASYNC_EVENT_CMPL_EVENT_ID_DEFERRED_RESPONSE: { 2376 u16 seq_id = le32_to_cpu(cmpl->event_data2) & 0xffff; 2377 2378 hwrm_update_token(bp, seq_id, BNXT_HWRM_DEFERRED); 2379 goto async_event_process_exit; 2380 } 2381 default: 2382 goto async_event_process_exit; 2383 } 2384 bnxt_queue_sp_work(bp); 2385 async_event_process_exit: 2386 return 0; 2387 } 2388 2389 static int bnxt_hwrm_handler(struct bnxt *bp, struct tx_cmp *txcmp) 2390 { 2391 u16 cmpl_type = TX_CMP_TYPE(txcmp), vf_id, seq_id; 2392 struct hwrm_cmpl *h_cmpl = (struct hwrm_cmpl *)txcmp; 2393 struct hwrm_fwd_req_cmpl *fwd_req_cmpl = 2394 (struct hwrm_fwd_req_cmpl *)txcmp; 2395 2396 switch (cmpl_type) { 2397 case CMPL_BASE_TYPE_HWRM_DONE: 2398 seq_id = le16_to_cpu(h_cmpl->sequence_id); 2399 hwrm_update_token(bp, seq_id, BNXT_HWRM_COMPLETE); 2400 break; 2401 2402 case CMPL_BASE_TYPE_HWRM_FWD_REQ: 2403 vf_id = le16_to_cpu(fwd_req_cmpl->source_id); 2404 2405 if ((vf_id < bp->pf.first_vf_id) || 2406 (vf_id >= bp->pf.first_vf_id + bp->pf.active_vfs)) { 2407 netdev_err(bp->dev, "Msg contains invalid VF id %x\n", 2408 vf_id); 2409 return -EINVAL; 2410 } 2411 2412 set_bit(vf_id - bp->pf.first_vf_id, bp->pf.vf_event_bmap); 2413 set_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event); 2414 bnxt_queue_sp_work(bp); 2415 break; 2416 2417 case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT: 2418 bnxt_async_event_process(bp, 2419 (struct hwrm_async_event_cmpl *)txcmp); 2420 break; 2421 2422 default: 2423 break; 2424 } 2425 2426 return 0; 2427 } 2428 2429 static irqreturn_t bnxt_msix(int irq, void *dev_instance) 2430 { 2431 struct bnxt_napi *bnapi = dev_instance; 2432 struct bnxt *bp = bnapi->bp; 2433 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 2434 u32 cons = RING_CMP(cpr->cp_raw_cons); 2435 2436 cpr->event_ctr++; 2437 prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]); 2438 napi_schedule(&bnapi->napi); 2439 return IRQ_HANDLED; 2440 } 2441 2442 static inline int bnxt_has_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr) 2443 { 2444 u32 raw_cons = cpr->cp_raw_cons; 2445 u16 cons = RING_CMP(raw_cons); 2446 struct tx_cmp *txcmp; 2447 2448 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]; 2449 2450 return TX_CMP_VALID(txcmp, raw_cons); 2451 } 2452 2453 static irqreturn_t bnxt_inta(int irq, void *dev_instance) 2454 { 2455 struct bnxt_napi *bnapi = dev_instance; 2456 struct bnxt *bp = bnapi->bp; 2457 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 2458 u32 cons = RING_CMP(cpr->cp_raw_cons); 2459 u32 int_status; 2460 2461 prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]); 2462 2463 if (!bnxt_has_work(bp, cpr)) { 2464 int_status = readl(bp->bar0 + BNXT_CAG_REG_LEGACY_INT_STATUS); 2465 /* return if erroneous interrupt */ 2466 if (!(int_status & (0x10000 << cpr->cp_ring_struct.fw_ring_id))) 2467 return IRQ_NONE; 2468 } 2469 2470 /* disable ring IRQ */ 2471 BNXT_CP_DB_IRQ_DIS(cpr->cp_db.doorbell); 2472 2473 /* Return here if interrupt is shared and is disabled. */ 2474 if (unlikely(atomic_read(&bp->intr_sem) != 0)) 2475 return IRQ_HANDLED; 2476 2477 napi_schedule(&bnapi->napi); 2478 return IRQ_HANDLED; 2479 } 2480 2481 static int __bnxt_poll_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, 2482 int budget) 2483 { 2484 struct bnxt_napi *bnapi = cpr->bnapi; 2485 u32 raw_cons = cpr->cp_raw_cons; 2486 u32 cons; 2487 int tx_pkts = 0; 2488 int rx_pkts = 0; 2489 u8 event = 0; 2490 struct tx_cmp *txcmp; 2491 2492 cpr->has_more_work = 0; 2493 cpr->had_work_done = 1; 2494 while (1) { 2495 int rc; 2496 2497 cons = RING_CMP(raw_cons); 2498 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]; 2499 2500 if (!TX_CMP_VALID(txcmp, raw_cons)) 2501 break; 2502 2503 /* The valid test of the entry must be done first before 2504 * reading any further. 2505 */ 2506 dma_rmb(); 2507 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_TX_L2_CMP) { 2508 tx_pkts++; 2509 /* return full budget so NAPI will complete. */ 2510 if (unlikely(tx_pkts >= bp->tx_wake_thresh)) { 2511 rx_pkts = budget; 2512 raw_cons = NEXT_RAW_CMP(raw_cons); 2513 if (budget) 2514 cpr->has_more_work = 1; 2515 break; 2516 } 2517 } else if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) { 2518 if (likely(budget)) 2519 rc = bnxt_rx_pkt(bp, cpr, &raw_cons, &event); 2520 else 2521 rc = bnxt_force_rx_discard(bp, cpr, &raw_cons, 2522 &event); 2523 if (likely(rc >= 0)) 2524 rx_pkts += rc; 2525 /* Increment rx_pkts when rc is -ENOMEM to count towards 2526 * the NAPI budget. Otherwise, we may potentially loop 2527 * here forever if we consistently cannot allocate 2528 * buffers. 2529 */ 2530 else if (rc == -ENOMEM && budget) 2531 rx_pkts++; 2532 else if (rc == -EBUSY) /* partial completion */ 2533 break; 2534 } else if (unlikely((TX_CMP_TYPE(txcmp) == 2535 CMPL_BASE_TYPE_HWRM_DONE) || 2536 (TX_CMP_TYPE(txcmp) == 2537 CMPL_BASE_TYPE_HWRM_FWD_REQ) || 2538 (TX_CMP_TYPE(txcmp) == 2539 CMPL_BASE_TYPE_HWRM_ASYNC_EVENT))) { 2540 bnxt_hwrm_handler(bp, txcmp); 2541 } 2542 raw_cons = NEXT_RAW_CMP(raw_cons); 2543 2544 if (rx_pkts && rx_pkts == budget) { 2545 cpr->has_more_work = 1; 2546 break; 2547 } 2548 } 2549 2550 if (event & BNXT_REDIRECT_EVENT) 2551 xdp_do_flush(); 2552 2553 if (event & BNXT_TX_EVENT) { 2554 struct bnxt_tx_ring_info *txr = bnapi->tx_ring; 2555 u16 prod = txr->tx_prod; 2556 2557 /* Sync BD data before updating doorbell */ 2558 wmb(); 2559 2560 bnxt_db_write_relaxed(bp, &txr->tx_db, prod); 2561 } 2562 2563 cpr->cp_raw_cons = raw_cons; 2564 bnapi->tx_pkts += tx_pkts; 2565 bnapi->events |= event; 2566 return rx_pkts; 2567 } 2568 2569 static void __bnxt_poll_work_done(struct bnxt *bp, struct bnxt_napi *bnapi) 2570 { 2571 if (bnapi->tx_pkts) { 2572 bnapi->tx_int(bp, bnapi, bnapi->tx_pkts); 2573 bnapi->tx_pkts = 0; 2574 } 2575 2576 if ((bnapi->events & BNXT_RX_EVENT) && !(bnapi->in_reset)) { 2577 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 2578 2579 bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod); 2580 } 2581 if (bnapi->events & BNXT_AGG_EVENT) { 2582 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 2583 2584 bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod); 2585 } 2586 bnapi->events = 0; 2587 } 2588 2589 static int bnxt_poll_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, 2590 int budget) 2591 { 2592 struct bnxt_napi *bnapi = cpr->bnapi; 2593 int rx_pkts; 2594 2595 rx_pkts = __bnxt_poll_work(bp, cpr, budget); 2596 2597 /* ACK completion ring before freeing tx ring and producing new 2598 * buffers in rx/agg rings to prevent overflowing the completion 2599 * ring. 2600 */ 2601 bnxt_db_cq(bp, &cpr->cp_db, cpr->cp_raw_cons); 2602 2603 __bnxt_poll_work_done(bp, bnapi); 2604 return rx_pkts; 2605 } 2606 2607 static int bnxt_poll_nitroa0(struct napi_struct *napi, int budget) 2608 { 2609 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi); 2610 struct bnxt *bp = bnapi->bp; 2611 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 2612 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 2613 struct tx_cmp *txcmp; 2614 struct rx_cmp_ext *rxcmp1; 2615 u32 cp_cons, tmp_raw_cons; 2616 u32 raw_cons = cpr->cp_raw_cons; 2617 u32 rx_pkts = 0; 2618 u8 event = 0; 2619 2620 while (1) { 2621 int rc; 2622 2623 cp_cons = RING_CMP(raw_cons); 2624 txcmp = &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 2625 2626 if (!TX_CMP_VALID(txcmp, raw_cons)) 2627 break; 2628 2629 /* The valid test of the entry must be done first before 2630 * reading any further. 2631 */ 2632 dma_rmb(); 2633 if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) { 2634 tmp_raw_cons = NEXT_RAW_CMP(raw_cons); 2635 cp_cons = RING_CMP(tmp_raw_cons); 2636 rxcmp1 = (struct rx_cmp_ext *) 2637 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 2638 2639 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons)) 2640 break; 2641 2642 /* force an error to recycle the buffer */ 2643 rxcmp1->rx_cmp_cfa_code_errors_v2 |= 2644 cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR); 2645 2646 rc = bnxt_rx_pkt(bp, cpr, &raw_cons, &event); 2647 if (likely(rc == -EIO) && budget) 2648 rx_pkts++; 2649 else if (rc == -EBUSY) /* partial completion */ 2650 break; 2651 } else if (unlikely(TX_CMP_TYPE(txcmp) == 2652 CMPL_BASE_TYPE_HWRM_DONE)) { 2653 bnxt_hwrm_handler(bp, txcmp); 2654 } else { 2655 netdev_err(bp->dev, 2656 "Invalid completion received on special ring\n"); 2657 } 2658 raw_cons = NEXT_RAW_CMP(raw_cons); 2659 2660 if (rx_pkts == budget) 2661 break; 2662 } 2663 2664 cpr->cp_raw_cons = raw_cons; 2665 BNXT_DB_CQ(&cpr->cp_db, cpr->cp_raw_cons); 2666 bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod); 2667 2668 if (event & BNXT_AGG_EVENT) 2669 bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod); 2670 2671 if (!bnxt_has_work(bp, cpr) && rx_pkts < budget) { 2672 napi_complete_done(napi, rx_pkts); 2673 BNXT_DB_CQ_ARM(&cpr->cp_db, cpr->cp_raw_cons); 2674 } 2675 return rx_pkts; 2676 } 2677 2678 static int bnxt_poll(struct napi_struct *napi, int budget) 2679 { 2680 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi); 2681 struct bnxt *bp = bnapi->bp; 2682 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 2683 int work_done = 0; 2684 2685 if (unlikely(test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state))) { 2686 napi_complete(napi); 2687 return 0; 2688 } 2689 while (1) { 2690 work_done += bnxt_poll_work(bp, cpr, budget - work_done); 2691 2692 if (work_done >= budget) { 2693 if (!budget) 2694 BNXT_DB_CQ_ARM(&cpr->cp_db, cpr->cp_raw_cons); 2695 break; 2696 } 2697 2698 if (!bnxt_has_work(bp, cpr)) { 2699 if (napi_complete_done(napi, work_done)) 2700 BNXT_DB_CQ_ARM(&cpr->cp_db, cpr->cp_raw_cons); 2701 break; 2702 } 2703 } 2704 if (bp->flags & BNXT_FLAG_DIM) { 2705 struct dim_sample dim_sample = {}; 2706 2707 dim_update_sample(cpr->event_ctr, 2708 cpr->rx_packets, 2709 cpr->rx_bytes, 2710 &dim_sample); 2711 net_dim(&cpr->dim, dim_sample); 2712 } 2713 return work_done; 2714 } 2715 2716 static int __bnxt_poll_cqs(struct bnxt *bp, struct bnxt_napi *bnapi, int budget) 2717 { 2718 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 2719 int i, work_done = 0; 2720 2721 for (i = 0; i < 2; i++) { 2722 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[i]; 2723 2724 if (cpr2) { 2725 work_done += __bnxt_poll_work(bp, cpr2, 2726 budget - work_done); 2727 cpr->has_more_work |= cpr2->has_more_work; 2728 } 2729 } 2730 return work_done; 2731 } 2732 2733 static void __bnxt_poll_cqs_done(struct bnxt *bp, struct bnxt_napi *bnapi, 2734 u64 dbr_type) 2735 { 2736 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 2737 int i; 2738 2739 for (i = 0; i < 2; i++) { 2740 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[i]; 2741 struct bnxt_db_info *db; 2742 2743 if (cpr2 && cpr2->had_work_done) { 2744 db = &cpr2->cp_db; 2745 bnxt_writeq(bp, db->db_key64 | dbr_type | 2746 RING_CMP(cpr2->cp_raw_cons), db->doorbell); 2747 cpr2->had_work_done = 0; 2748 } 2749 } 2750 __bnxt_poll_work_done(bp, bnapi); 2751 } 2752 2753 static int bnxt_poll_p5(struct napi_struct *napi, int budget) 2754 { 2755 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi); 2756 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 2757 struct bnxt_cp_ring_info *cpr_rx; 2758 u32 raw_cons = cpr->cp_raw_cons; 2759 struct bnxt *bp = bnapi->bp; 2760 struct nqe_cn *nqcmp; 2761 int work_done = 0; 2762 u32 cons; 2763 2764 if (unlikely(test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state))) { 2765 napi_complete(napi); 2766 return 0; 2767 } 2768 if (cpr->has_more_work) { 2769 cpr->has_more_work = 0; 2770 work_done = __bnxt_poll_cqs(bp, bnapi, budget); 2771 } 2772 while (1) { 2773 cons = RING_CMP(raw_cons); 2774 nqcmp = &cpr->nq_desc_ring[CP_RING(cons)][CP_IDX(cons)]; 2775 2776 if (!NQ_CMP_VALID(nqcmp, raw_cons)) { 2777 if (cpr->has_more_work) 2778 break; 2779 2780 __bnxt_poll_cqs_done(bp, bnapi, DBR_TYPE_CQ_ARMALL); 2781 cpr->cp_raw_cons = raw_cons; 2782 if (napi_complete_done(napi, work_done)) 2783 BNXT_DB_NQ_ARM_P5(&cpr->cp_db, 2784 cpr->cp_raw_cons); 2785 goto poll_done; 2786 } 2787 2788 /* The valid test of the entry must be done first before 2789 * reading any further. 2790 */ 2791 dma_rmb(); 2792 2793 if (nqcmp->type == cpu_to_le16(NQ_CN_TYPE_CQ_NOTIFICATION)) { 2794 u32 idx = le32_to_cpu(nqcmp->cq_handle_low); 2795 struct bnxt_cp_ring_info *cpr2; 2796 2797 /* No more budget for RX work */ 2798 if (budget && work_done >= budget && idx == BNXT_RX_HDL) 2799 break; 2800 2801 cpr2 = cpr->cp_ring_arr[idx]; 2802 work_done += __bnxt_poll_work(bp, cpr2, 2803 budget - work_done); 2804 cpr->has_more_work |= cpr2->has_more_work; 2805 } else { 2806 bnxt_hwrm_handler(bp, (struct tx_cmp *)nqcmp); 2807 } 2808 raw_cons = NEXT_RAW_CMP(raw_cons); 2809 } 2810 __bnxt_poll_cqs_done(bp, bnapi, DBR_TYPE_CQ); 2811 if (raw_cons != cpr->cp_raw_cons) { 2812 cpr->cp_raw_cons = raw_cons; 2813 BNXT_DB_NQ_P5(&cpr->cp_db, raw_cons); 2814 } 2815 poll_done: 2816 cpr_rx = cpr->cp_ring_arr[BNXT_RX_HDL]; 2817 if (cpr_rx && (bp->flags & BNXT_FLAG_DIM)) { 2818 struct dim_sample dim_sample = {}; 2819 2820 dim_update_sample(cpr->event_ctr, 2821 cpr_rx->rx_packets, 2822 cpr_rx->rx_bytes, 2823 &dim_sample); 2824 net_dim(&cpr->dim, dim_sample); 2825 } 2826 return work_done; 2827 } 2828 2829 static void bnxt_free_tx_skbs(struct bnxt *bp) 2830 { 2831 int i, max_idx; 2832 struct pci_dev *pdev = bp->pdev; 2833 2834 if (!bp->tx_ring) 2835 return; 2836 2837 max_idx = bp->tx_nr_pages * TX_DESC_CNT; 2838 for (i = 0; i < bp->tx_nr_rings; i++) { 2839 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; 2840 int j; 2841 2842 if (!txr->tx_buf_ring) 2843 continue; 2844 2845 for (j = 0; j < max_idx;) { 2846 struct bnxt_sw_tx_bd *tx_buf = &txr->tx_buf_ring[j]; 2847 struct sk_buff *skb; 2848 int k, last; 2849 2850 if (i < bp->tx_nr_rings_xdp && 2851 tx_buf->action == XDP_REDIRECT) { 2852 dma_unmap_single(&pdev->dev, 2853 dma_unmap_addr(tx_buf, mapping), 2854 dma_unmap_len(tx_buf, len), 2855 DMA_TO_DEVICE); 2856 xdp_return_frame(tx_buf->xdpf); 2857 tx_buf->action = 0; 2858 tx_buf->xdpf = NULL; 2859 j++; 2860 continue; 2861 } 2862 2863 skb = tx_buf->skb; 2864 if (!skb) { 2865 j++; 2866 continue; 2867 } 2868 2869 tx_buf->skb = NULL; 2870 2871 if (tx_buf->is_push) { 2872 dev_kfree_skb(skb); 2873 j += 2; 2874 continue; 2875 } 2876 2877 dma_unmap_single(&pdev->dev, 2878 dma_unmap_addr(tx_buf, mapping), 2879 skb_headlen(skb), 2880 DMA_TO_DEVICE); 2881 2882 last = tx_buf->nr_frags; 2883 j += 2; 2884 for (k = 0; k < last; k++, j++) { 2885 int ring_idx = j & bp->tx_ring_mask; 2886 skb_frag_t *frag = &skb_shinfo(skb)->frags[k]; 2887 2888 tx_buf = &txr->tx_buf_ring[ring_idx]; 2889 dma_unmap_page( 2890 &pdev->dev, 2891 dma_unmap_addr(tx_buf, mapping), 2892 skb_frag_size(frag), DMA_TO_DEVICE); 2893 } 2894 dev_kfree_skb(skb); 2895 } 2896 netdev_tx_reset_queue(netdev_get_tx_queue(bp->dev, i)); 2897 } 2898 } 2899 2900 static void bnxt_free_one_rx_ring_skbs(struct bnxt *bp, int ring_nr) 2901 { 2902 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[ring_nr]; 2903 struct pci_dev *pdev = bp->pdev; 2904 struct bnxt_tpa_idx_map *map; 2905 int i, max_idx, max_agg_idx; 2906 2907 max_idx = bp->rx_nr_pages * RX_DESC_CNT; 2908 max_agg_idx = bp->rx_agg_nr_pages * RX_DESC_CNT; 2909 if (!rxr->rx_tpa) 2910 goto skip_rx_tpa_free; 2911 2912 for (i = 0; i < bp->max_tpa; i++) { 2913 struct bnxt_tpa_info *tpa_info = &rxr->rx_tpa[i]; 2914 u8 *data = tpa_info->data; 2915 2916 if (!data) 2917 continue; 2918 2919 dma_unmap_single_attrs(&pdev->dev, tpa_info->mapping, 2920 bp->rx_buf_use_size, bp->rx_dir, 2921 DMA_ATTR_WEAK_ORDERING); 2922 2923 tpa_info->data = NULL; 2924 2925 skb_free_frag(data); 2926 } 2927 2928 skip_rx_tpa_free: 2929 if (!rxr->rx_buf_ring) 2930 goto skip_rx_buf_free; 2931 2932 for (i = 0; i < max_idx; i++) { 2933 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[i]; 2934 dma_addr_t mapping = rx_buf->mapping; 2935 void *data = rx_buf->data; 2936 2937 if (!data) 2938 continue; 2939 2940 rx_buf->data = NULL; 2941 if (BNXT_RX_PAGE_MODE(bp)) { 2942 mapping -= bp->rx_dma_offset; 2943 dma_unmap_page_attrs(&pdev->dev, mapping, PAGE_SIZE, 2944 bp->rx_dir, 2945 DMA_ATTR_WEAK_ORDERING); 2946 page_pool_recycle_direct(rxr->page_pool, data); 2947 } else { 2948 dma_unmap_single_attrs(&pdev->dev, mapping, 2949 bp->rx_buf_use_size, bp->rx_dir, 2950 DMA_ATTR_WEAK_ORDERING); 2951 skb_free_frag(data); 2952 } 2953 } 2954 2955 skip_rx_buf_free: 2956 if (!rxr->rx_agg_ring) 2957 goto skip_rx_agg_free; 2958 2959 for (i = 0; i < max_agg_idx; i++) { 2960 struct bnxt_sw_rx_agg_bd *rx_agg_buf = &rxr->rx_agg_ring[i]; 2961 struct page *page = rx_agg_buf->page; 2962 2963 if (!page) 2964 continue; 2965 2966 if (BNXT_RX_PAGE_MODE(bp)) { 2967 dma_unmap_page_attrs(&pdev->dev, rx_agg_buf->mapping, 2968 BNXT_RX_PAGE_SIZE, bp->rx_dir, 2969 DMA_ATTR_WEAK_ORDERING); 2970 rx_agg_buf->page = NULL; 2971 __clear_bit(i, rxr->rx_agg_bmap); 2972 2973 page_pool_recycle_direct(rxr->page_pool, page); 2974 } else { 2975 dma_unmap_page_attrs(&pdev->dev, rx_agg_buf->mapping, 2976 BNXT_RX_PAGE_SIZE, DMA_FROM_DEVICE, 2977 DMA_ATTR_WEAK_ORDERING); 2978 rx_agg_buf->page = NULL; 2979 __clear_bit(i, rxr->rx_agg_bmap); 2980 2981 __free_page(page); 2982 } 2983 } 2984 2985 skip_rx_agg_free: 2986 if (rxr->rx_page) { 2987 __free_page(rxr->rx_page); 2988 rxr->rx_page = NULL; 2989 } 2990 map = rxr->rx_tpa_idx_map; 2991 if (map) 2992 memset(map->agg_idx_bmap, 0, sizeof(map->agg_idx_bmap)); 2993 } 2994 2995 static void bnxt_free_rx_skbs(struct bnxt *bp) 2996 { 2997 int i; 2998 2999 if (!bp->rx_ring) 3000 return; 3001 3002 for (i = 0; i < bp->rx_nr_rings; i++) 3003 bnxt_free_one_rx_ring_skbs(bp, i); 3004 } 3005 3006 static void bnxt_free_skbs(struct bnxt *bp) 3007 { 3008 bnxt_free_tx_skbs(bp); 3009 bnxt_free_rx_skbs(bp); 3010 } 3011 3012 static void bnxt_init_ctx_mem(struct bnxt_mem_init *mem_init, void *p, int len) 3013 { 3014 u8 init_val = mem_init->init_val; 3015 u16 offset = mem_init->offset; 3016 u8 *p2 = p; 3017 int i; 3018 3019 if (!init_val) 3020 return; 3021 if (offset == BNXT_MEM_INVALID_OFFSET) { 3022 memset(p, init_val, len); 3023 return; 3024 } 3025 for (i = 0; i < len; i += mem_init->size) 3026 *(p2 + i + offset) = init_val; 3027 } 3028 3029 static void bnxt_free_ring(struct bnxt *bp, struct bnxt_ring_mem_info *rmem) 3030 { 3031 struct pci_dev *pdev = bp->pdev; 3032 int i; 3033 3034 if (!rmem->pg_arr) 3035 goto skip_pages; 3036 3037 for (i = 0; i < rmem->nr_pages; i++) { 3038 if (!rmem->pg_arr[i]) 3039 continue; 3040 3041 dma_free_coherent(&pdev->dev, rmem->page_size, 3042 rmem->pg_arr[i], rmem->dma_arr[i]); 3043 3044 rmem->pg_arr[i] = NULL; 3045 } 3046 skip_pages: 3047 if (rmem->pg_tbl) { 3048 size_t pg_tbl_size = rmem->nr_pages * 8; 3049 3050 if (rmem->flags & BNXT_RMEM_USE_FULL_PAGE_FLAG) 3051 pg_tbl_size = rmem->page_size; 3052 dma_free_coherent(&pdev->dev, pg_tbl_size, 3053 rmem->pg_tbl, rmem->pg_tbl_map); 3054 rmem->pg_tbl = NULL; 3055 } 3056 if (rmem->vmem_size && *rmem->vmem) { 3057 vfree(*rmem->vmem); 3058 *rmem->vmem = NULL; 3059 } 3060 } 3061 3062 static int bnxt_alloc_ring(struct bnxt *bp, struct bnxt_ring_mem_info *rmem) 3063 { 3064 struct pci_dev *pdev = bp->pdev; 3065 u64 valid_bit = 0; 3066 int i; 3067 3068 if (rmem->flags & (BNXT_RMEM_VALID_PTE_FLAG | BNXT_RMEM_RING_PTE_FLAG)) 3069 valid_bit = PTU_PTE_VALID; 3070 if ((rmem->nr_pages > 1 || rmem->depth > 0) && !rmem->pg_tbl) { 3071 size_t pg_tbl_size = rmem->nr_pages * 8; 3072 3073 if (rmem->flags & BNXT_RMEM_USE_FULL_PAGE_FLAG) 3074 pg_tbl_size = rmem->page_size; 3075 rmem->pg_tbl = dma_alloc_coherent(&pdev->dev, pg_tbl_size, 3076 &rmem->pg_tbl_map, 3077 GFP_KERNEL); 3078 if (!rmem->pg_tbl) 3079 return -ENOMEM; 3080 } 3081 3082 for (i = 0; i < rmem->nr_pages; i++) { 3083 u64 extra_bits = valid_bit; 3084 3085 rmem->pg_arr[i] = dma_alloc_coherent(&pdev->dev, 3086 rmem->page_size, 3087 &rmem->dma_arr[i], 3088 GFP_KERNEL); 3089 if (!rmem->pg_arr[i]) 3090 return -ENOMEM; 3091 3092 if (rmem->mem_init) 3093 bnxt_init_ctx_mem(rmem->mem_init, rmem->pg_arr[i], 3094 rmem->page_size); 3095 if (rmem->nr_pages > 1 || rmem->depth > 0) { 3096 if (i == rmem->nr_pages - 2 && 3097 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG)) 3098 extra_bits |= PTU_PTE_NEXT_TO_LAST; 3099 else if (i == rmem->nr_pages - 1 && 3100 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG)) 3101 extra_bits |= PTU_PTE_LAST; 3102 rmem->pg_tbl[i] = 3103 cpu_to_le64(rmem->dma_arr[i] | extra_bits); 3104 } 3105 } 3106 3107 if (rmem->vmem_size) { 3108 *rmem->vmem = vzalloc(rmem->vmem_size); 3109 if (!(*rmem->vmem)) 3110 return -ENOMEM; 3111 } 3112 return 0; 3113 } 3114 3115 static void bnxt_free_tpa_info(struct bnxt *bp) 3116 { 3117 int i, j; 3118 3119 for (i = 0; i < bp->rx_nr_rings; i++) { 3120 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 3121 3122 kfree(rxr->rx_tpa_idx_map); 3123 rxr->rx_tpa_idx_map = NULL; 3124 if (rxr->rx_tpa) { 3125 for (j = 0; j < bp->max_tpa; j++) { 3126 kfree(rxr->rx_tpa[j].agg_arr); 3127 rxr->rx_tpa[j].agg_arr = NULL; 3128 } 3129 } 3130 kfree(rxr->rx_tpa); 3131 rxr->rx_tpa = NULL; 3132 } 3133 } 3134 3135 static int bnxt_alloc_tpa_info(struct bnxt *bp) 3136 { 3137 int i, j; 3138 3139 bp->max_tpa = MAX_TPA; 3140 if (bp->flags & BNXT_FLAG_CHIP_P5) { 3141 if (!bp->max_tpa_v2) 3142 return 0; 3143 bp->max_tpa = max_t(u16, bp->max_tpa_v2, MAX_TPA_P5); 3144 } 3145 3146 for (i = 0; i < bp->rx_nr_rings; i++) { 3147 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 3148 struct rx_agg_cmp *agg; 3149 3150 rxr->rx_tpa = kcalloc(bp->max_tpa, sizeof(struct bnxt_tpa_info), 3151 GFP_KERNEL); 3152 if (!rxr->rx_tpa) 3153 return -ENOMEM; 3154 3155 if (!(bp->flags & BNXT_FLAG_CHIP_P5)) 3156 continue; 3157 for (j = 0; j < bp->max_tpa; j++) { 3158 agg = kcalloc(MAX_SKB_FRAGS, sizeof(*agg), GFP_KERNEL); 3159 if (!agg) 3160 return -ENOMEM; 3161 rxr->rx_tpa[j].agg_arr = agg; 3162 } 3163 rxr->rx_tpa_idx_map = kzalloc(sizeof(*rxr->rx_tpa_idx_map), 3164 GFP_KERNEL); 3165 if (!rxr->rx_tpa_idx_map) 3166 return -ENOMEM; 3167 } 3168 return 0; 3169 } 3170 3171 static void bnxt_free_rx_rings(struct bnxt *bp) 3172 { 3173 int i; 3174 3175 if (!bp->rx_ring) 3176 return; 3177 3178 bnxt_free_tpa_info(bp); 3179 for (i = 0; i < bp->rx_nr_rings; i++) { 3180 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 3181 struct bnxt_ring_struct *ring; 3182 3183 if (rxr->xdp_prog) 3184 bpf_prog_put(rxr->xdp_prog); 3185 3186 if (xdp_rxq_info_is_reg(&rxr->xdp_rxq)) 3187 xdp_rxq_info_unreg(&rxr->xdp_rxq); 3188 3189 page_pool_destroy(rxr->page_pool); 3190 rxr->page_pool = NULL; 3191 3192 kfree(rxr->rx_agg_bmap); 3193 rxr->rx_agg_bmap = NULL; 3194 3195 ring = &rxr->rx_ring_struct; 3196 bnxt_free_ring(bp, &ring->ring_mem); 3197 3198 ring = &rxr->rx_agg_ring_struct; 3199 bnxt_free_ring(bp, &ring->ring_mem); 3200 } 3201 } 3202 3203 static int bnxt_alloc_rx_page_pool(struct bnxt *bp, 3204 struct bnxt_rx_ring_info *rxr) 3205 { 3206 struct page_pool_params pp = { 0 }; 3207 3208 pp.pool_size = bp->rx_ring_size; 3209 pp.nid = dev_to_node(&bp->pdev->dev); 3210 pp.napi = &rxr->bnapi->napi; 3211 pp.dev = &bp->pdev->dev; 3212 pp.dma_dir = DMA_BIDIRECTIONAL; 3213 3214 rxr->page_pool = page_pool_create(&pp); 3215 if (IS_ERR(rxr->page_pool)) { 3216 int err = PTR_ERR(rxr->page_pool); 3217 3218 rxr->page_pool = NULL; 3219 return err; 3220 } 3221 return 0; 3222 } 3223 3224 static int bnxt_alloc_rx_rings(struct bnxt *bp) 3225 { 3226 int i, rc = 0, agg_rings = 0; 3227 3228 if (!bp->rx_ring) 3229 return -ENOMEM; 3230 3231 if (bp->flags & BNXT_FLAG_AGG_RINGS) 3232 agg_rings = 1; 3233 3234 for (i = 0; i < bp->rx_nr_rings; i++) { 3235 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 3236 struct bnxt_ring_struct *ring; 3237 3238 ring = &rxr->rx_ring_struct; 3239 3240 rc = bnxt_alloc_rx_page_pool(bp, rxr); 3241 if (rc) 3242 return rc; 3243 3244 rc = xdp_rxq_info_reg(&rxr->xdp_rxq, bp->dev, i, 0); 3245 if (rc < 0) 3246 return rc; 3247 3248 rc = xdp_rxq_info_reg_mem_model(&rxr->xdp_rxq, 3249 MEM_TYPE_PAGE_POOL, 3250 rxr->page_pool); 3251 if (rc) { 3252 xdp_rxq_info_unreg(&rxr->xdp_rxq); 3253 return rc; 3254 } 3255 3256 rc = bnxt_alloc_ring(bp, &ring->ring_mem); 3257 if (rc) 3258 return rc; 3259 3260 ring->grp_idx = i; 3261 if (agg_rings) { 3262 u16 mem_size; 3263 3264 ring = &rxr->rx_agg_ring_struct; 3265 rc = bnxt_alloc_ring(bp, &ring->ring_mem); 3266 if (rc) 3267 return rc; 3268 3269 ring->grp_idx = i; 3270 rxr->rx_agg_bmap_size = bp->rx_agg_ring_mask + 1; 3271 mem_size = rxr->rx_agg_bmap_size / 8; 3272 rxr->rx_agg_bmap = kzalloc(mem_size, GFP_KERNEL); 3273 if (!rxr->rx_agg_bmap) 3274 return -ENOMEM; 3275 } 3276 } 3277 if (bp->flags & BNXT_FLAG_TPA) 3278 rc = bnxt_alloc_tpa_info(bp); 3279 return rc; 3280 } 3281 3282 static void bnxt_free_tx_rings(struct bnxt *bp) 3283 { 3284 int i; 3285 struct pci_dev *pdev = bp->pdev; 3286 3287 if (!bp->tx_ring) 3288 return; 3289 3290 for (i = 0; i < bp->tx_nr_rings; i++) { 3291 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; 3292 struct bnxt_ring_struct *ring; 3293 3294 if (txr->tx_push) { 3295 dma_free_coherent(&pdev->dev, bp->tx_push_size, 3296 txr->tx_push, txr->tx_push_mapping); 3297 txr->tx_push = NULL; 3298 } 3299 3300 ring = &txr->tx_ring_struct; 3301 3302 bnxt_free_ring(bp, &ring->ring_mem); 3303 } 3304 } 3305 3306 static int bnxt_alloc_tx_rings(struct bnxt *bp) 3307 { 3308 int i, j, rc; 3309 struct pci_dev *pdev = bp->pdev; 3310 3311 bp->tx_push_size = 0; 3312 if (bp->tx_push_thresh) { 3313 int push_size; 3314 3315 push_size = L1_CACHE_ALIGN(sizeof(struct tx_push_bd) + 3316 bp->tx_push_thresh); 3317 3318 if (push_size > 256) { 3319 push_size = 0; 3320 bp->tx_push_thresh = 0; 3321 } 3322 3323 bp->tx_push_size = push_size; 3324 } 3325 3326 for (i = 0, j = 0; i < bp->tx_nr_rings; i++) { 3327 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; 3328 struct bnxt_ring_struct *ring; 3329 u8 qidx; 3330 3331 ring = &txr->tx_ring_struct; 3332 3333 rc = bnxt_alloc_ring(bp, &ring->ring_mem); 3334 if (rc) 3335 return rc; 3336 3337 ring->grp_idx = txr->bnapi->index; 3338 if (bp->tx_push_size) { 3339 dma_addr_t mapping; 3340 3341 /* One pre-allocated DMA buffer to backup 3342 * TX push operation 3343 */ 3344 txr->tx_push = dma_alloc_coherent(&pdev->dev, 3345 bp->tx_push_size, 3346 &txr->tx_push_mapping, 3347 GFP_KERNEL); 3348 3349 if (!txr->tx_push) 3350 return -ENOMEM; 3351 3352 mapping = txr->tx_push_mapping + 3353 sizeof(struct tx_push_bd); 3354 txr->data_mapping = cpu_to_le64(mapping); 3355 } 3356 qidx = bp->tc_to_qidx[j]; 3357 ring->queue_id = bp->q_info[qidx].queue_id; 3358 spin_lock_init(&txr->xdp_tx_lock); 3359 if (i < bp->tx_nr_rings_xdp) 3360 continue; 3361 if (i % bp->tx_nr_rings_per_tc == (bp->tx_nr_rings_per_tc - 1)) 3362 j++; 3363 } 3364 return 0; 3365 } 3366 3367 static void bnxt_free_cp_arrays(struct bnxt_cp_ring_info *cpr) 3368 { 3369 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct; 3370 3371 kfree(cpr->cp_desc_ring); 3372 cpr->cp_desc_ring = NULL; 3373 ring->ring_mem.pg_arr = NULL; 3374 kfree(cpr->cp_desc_mapping); 3375 cpr->cp_desc_mapping = NULL; 3376 ring->ring_mem.dma_arr = NULL; 3377 } 3378 3379 static int bnxt_alloc_cp_arrays(struct bnxt_cp_ring_info *cpr, int n) 3380 { 3381 cpr->cp_desc_ring = kcalloc(n, sizeof(*cpr->cp_desc_ring), GFP_KERNEL); 3382 if (!cpr->cp_desc_ring) 3383 return -ENOMEM; 3384 cpr->cp_desc_mapping = kcalloc(n, sizeof(*cpr->cp_desc_mapping), 3385 GFP_KERNEL); 3386 if (!cpr->cp_desc_mapping) 3387 return -ENOMEM; 3388 return 0; 3389 } 3390 3391 static void bnxt_free_all_cp_arrays(struct bnxt *bp) 3392 { 3393 int i; 3394 3395 if (!bp->bnapi) 3396 return; 3397 for (i = 0; i < bp->cp_nr_rings; i++) { 3398 struct bnxt_napi *bnapi = bp->bnapi[i]; 3399 3400 if (!bnapi) 3401 continue; 3402 bnxt_free_cp_arrays(&bnapi->cp_ring); 3403 } 3404 } 3405 3406 static int bnxt_alloc_all_cp_arrays(struct bnxt *bp) 3407 { 3408 int i, n = bp->cp_nr_pages; 3409 3410 for (i = 0; i < bp->cp_nr_rings; i++) { 3411 struct bnxt_napi *bnapi = bp->bnapi[i]; 3412 int rc; 3413 3414 if (!bnapi) 3415 continue; 3416 rc = bnxt_alloc_cp_arrays(&bnapi->cp_ring, n); 3417 if (rc) 3418 return rc; 3419 } 3420 return 0; 3421 } 3422 3423 static void bnxt_free_cp_rings(struct bnxt *bp) 3424 { 3425 int i; 3426 3427 if (!bp->bnapi) 3428 return; 3429 3430 for (i = 0; i < bp->cp_nr_rings; i++) { 3431 struct bnxt_napi *bnapi = bp->bnapi[i]; 3432 struct bnxt_cp_ring_info *cpr; 3433 struct bnxt_ring_struct *ring; 3434 int j; 3435 3436 if (!bnapi) 3437 continue; 3438 3439 cpr = &bnapi->cp_ring; 3440 ring = &cpr->cp_ring_struct; 3441 3442 bnxt_free_ring(bp, &ring->ring_mem); 3443 3444 for (j = 0; j < 2; j++) { 3445 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j]; 3446 3447 if (cpr2) { 3448 ring = &cpr2->cp_ring_struct; 3449 bnxt_free_ring(bp, &ring->ring_mem); 3450 bnxt_free_cp_arrays(cpr2); 3451 kfree(cpr2); 3452 cpr->cp_ring_arr[j] = NULL; 3453 } 3454 } 3455 } 3456 } 3457 3458 static struct bnxt_cp_ring_info *bnxt_alloc_cp_sub_ring(struct bnxt *bp) 3459 { 3460 struct bnxt_ring_mem_info *rmem; 3461 struct bnxt_ring_struct *ring; 3462 struct bnxt_cp_ring_info *cpr; 3463 int rc; 3464 3465 cpr = kzalloc(sizeof(*cpr), GFP_KERNEL); 3466 if (!cpr) 3467 return NULL; 3468 3469 rc = bnxt_alloc_cp_arrays(cpr, bp->cp_nr_pages); 3470 if (rc) { 3471 bnxt_free_cp_arrays(cpr); 3472 kfree(cpr); 3473 return NULL; 3474 } 3475 ring = &cpr->cp_ring_struct; 3476 rmem = &ring->ring_mem; 3477 rmem->nr_pages = bp->cp_nr_pages; 3478 rmem->page_size = HW_CMPD_RING_SIZE; 3479 rmem->pg_arr = (void **)cpr->cp_desc_ring; 3480 rmem->dma_arr = cpr->cp_desc_mapping; 3481 rmem->flags = BNXT_RMEM_RING_PTE_FLAG; 3482 rc = bnxt_alloc_ring(bp, rmem); 3483 if (rc) { 3484 bnxt_free_ring(bp, rmem); 3485 bnxt_free_cp_arrays(cpr); 3486 kfree(cpr); 3487 cpr = NULL; 3488 } 3489 return cpr; 3490 } 3491 3492 static int bnxt_alloc_cp_rings(struct bnxt *bp) 3493 { 3494 bool sh = !!(bp->flags & BNXT_FLAG_SHARED_RINGS); 3495 int i, rc, ulp_base_vec, ulp_msix; 3496 3497 ulp_msix = bnxt_get_ulp_msix_num(bp); 3498 ulp_base_vec = bnxt_get_ulp_msix_base(bp); 3499 for (i = 0; i < bp->cp_nr_rings; i++) { 3500 struct bnxt_napi *bnapi = bp->bnapi[i]; 3501 struct bnxt_cp_ring_info *cpr; 3502 struct bnxt_ring_struct *ring; 3503 3504 if (!bnapi) 3505 continue; 3506 3507 cpr = &bnapi->cp_ring; 3508 cpr->bnapi = bnapi; 3509 ring = &cpr->cp_ring_struct; 3510 3511 rc = bnxt_alloc_ring(bp, &ring->ring_mem); 3512 if (rc) 3513 return rc; 3514 3515 if (ulp_msix && i >= ulp_base_vec) 3516 ring->map_idx = i + ulp_msix; 3517 else 3518 ring->map_idx = i; 3519 3520 if (!(bp->flags & BNXT_FLAG_CHIP_P5)) 3521 continue; 3522 3523 if (i < bp->rx_nr_rings) { 3524 struct bnxt_cp_ring_info *cpr2 = 3525 bnxt_alloc_cp_sub_ring(bp); 3526 3527 cpr->cp_ring_arr[BNXT_RX_HDL] = cpr2; 3528 if (!cpr2) 3529 return -ENOMEM; 3530 cpr2->bnapi = bnapi; 3531 } 3532 if ((sh && i < bp->tx_nr_rings) || 3533 (!sh && i >= bp->rx_nr_rings)) { 3534 struct bnxt_cp_ring_info *cpr2 = 3535 bnxt_alloc_cp_sub_ring(bp); 3536 3537 cpr->cp_ring_arr[BNXT_TX_HDL] = cpr2; 3538 if (!cpr2) 3539 return -ENOMEM; 3540 cpr2->bnapi = bnapi; 3541 } 3542 } 3543 return 0; 3544 } 3545 3546 static void bnxt_init_ring_struct(struct bnxt *bp) 3547 { 3548 int i; 3549 3550 for (i = 0; i < bp->cp_nr_rings; i++) { 3551 struct bnxt_napi *bnapi = bp->bnapi[i]; 3552 struct bnxt_ring_mem_info *rmem; 3553 struct bnxt_cp_ring_info *cpr; 3554 struct bnxt_rx_ring_info *rxr; 3555 struct bnxt_tx_ring_info *txr; 3556 struct bnxt_ring_struct *ring; 3557 3558 if (!bnapi) 3559 continue; 3560 3561 cpr = &bnapi->cp_ring; 3562 ring = &cpr->cp_ring_struct; 3563 rmem = &ring->ring_mem; 3564 rmem->nr_pages = bp->cp_nr_pages; 3565 rmem->page_size = HW_CMPD_RING_SIZE; 3566 rmem->pg_arr = (void **)cpr->cp_desc_ring; 3567 rmem->dma_arr = cpr->cp_desc_mapping; 3568 rmem->vmem_size = 0; 3569 3570 rxr = bnapi->rx_ring; 3571 if (!rxr) 3572 goto skip_rx; 3573 3574 ring = &rxr->rx_ring_struct; 3575 rmem = &ring->ring_mem; 3576 rmem->nr_pages = bp->rx_nr_pages; 3577 rmem->page_size = HW_RXBD_RING_SIZE; 3578 rmem->pg_arr = (void **)rxr->rx_desc_ring; 3579 rmem->dma_arr = rxr->rx_desc_mapping; 3580 rmem->vmem_size = SW_RXBD_RING_SIZE * bp->rx_nr_pages; 3581 rmem->vmem = (void **)&rxr->rx_buf_ring; 3582 3583 ring = &rxr->rx_agg_ring_struct; 3584 rmem = &ring->ring_mem; 3585 rmem->nr_pages = bp->rx_agg_nr_pages; 3586 rmem->page_size = HW_RXBD_RING_SIZE; 3587 rmem->pg_arr = (void **)rxr->rx_agg_desc_ring; 3588 rmem->dma_arr = rxr->rx_agg_desc_mapping; 3589 rmem->vmem_size = SW_RXBD_AGG_RING_SIZE * bp->rx_agg_nr_pages; 3590 rmem->vmem = (void **)&rxr->rx_agg_ring; 3591 3592 skip_rx: 3593 txr = bnapi->tx_ring; 3594 if (!txr) 3595 continue; 3596 3597 ring = &txr->tx_ring_struct; 3598 rmem = &ring->ring_mem; 3599 rmem->nr_pages = bp->tx_nr_pages; 3600 rmem->page_size = HW_RXBD_RING_SIZE; 3601 rmem->pg_arr = (void **)txr->tx_desc_ring; 3602 rmem->dma_arr = txr->tx_desc_mapping; 3603 rmem->vmem_size = SW_TXBD_RING_SIZE * bp->tx_nr_pages; 3604 rmem->vmem = (void **)&txr->tx_buf_ring; 3605 } 3606 } 3607 3608 static void bnxt_init_rxbd_pages(struct bnxt_ring_struct *ring, u32 type) 3609 { 3610 int i; 3611 u32 prod; 3612 struct rx_bd **rx_buf_ring; 3613 3614 rx_buf_ring = (struct rx_bd **)ring->ring_mem.pg_arr; 3615 for (i = 0, prod = 0; i < ring->ring_mem.nr_pages; i++) { 3616 int j; 3617 struct rx_bd *rxbd; 3618 3619 rxbd = rx_buf_ring[i]; 3620 if (!rxbd) 3621 continue; 3622 3623 for (j = 0; j < RX_DESC_CNT; j++, rxbd++, prod++) { 3624 rxbd->rx_bd_len_flags_type = cpu_to_le32(type); 3625 rxbd->rx_bd_opaque = prod; 3626 } 3627 } 3628 } 3629 3630 static int bnxt_alloc_one_rx_ring(struct bnxt *bp, int ring_nr) 3631 { 3632 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[ring_nr]; 3633 struct net_device *dev = bp->dev; 3634 u32 prod; 3635 int i; 3636 3637 prod = rxr->rx_prod; 3638 for (i = 0; i < bp->rx_ring_size; i++) { 3639 if (bnxt_alloc_rx_data(bp, rxr, prod, GFP_KERNEL)) { 3640 netdev_warn(dev, "init'ed rx ring %d with %d/%d skbs only\n", 3641 ring_nr, i, bp->rx_ring_size); 3642 break; 3643 } 3644 prod = NEXT_RX(prod); 3645 } 3646 rxr->rx_prod = prod; 3647 3648 if (!(bp->flags & BNXT_FLAG_AGG_RINGS)) 3649 return 0; 3650 3651 prod = rxr->rx_agg_prod; 3652 for (i = 0; i < bp->rx_agg_ring_size; i++) { 3653 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_KERNEL)) { 3654 netdev_warn(dev, "init'ed rx ring %d with %d/%d pages only\n", 3655 ring_nr, i, bp->rx_ring_size); 3656 break; 3657 } 3658 prod = NEXT_RX_AGG(prod); 3659 } 3660 rxr->rx_agg_prod = prod; 3661 3662 if (rxr->rx_tpa) { 3663 dma_addr_t mapping; 3664 u8 *data; 3665 3666 for (i = 0; i < bp->max_tpa; i++) { 3667 data = __bnxt_alloc_rx_frag(bp, &mapping, GFP_KERNEL); 3668 if (!data) 3669 return -ENOMEM; 3670 3671 rxr->rx_tpa[i].data = data; 3672 rxr->rx_tpa[i].data_ptr = data + bp->rx_offset; 3673 rxr->rx_tpa[i].mapping = mapping; 3674 } 3675 } 3676 return 0; 3677 } 3678 3679 static int bnxt_init_one_rx_ring(struct bnxt *bp, int ring_nr) 3680 { 3681 struct bnxt_rx_ring_info *rxr; 3682 struct bnxt_ring_struct *ring; 3683 u32 type; 3684 3685 type = (bp->rx_buf_use_size << RX_BD_LEN_SHIFT) | 3686 RX_BD_TYPE_RX_PACKET_BD | RX_BD_FLAGS_EOP; 3687 3688 if (NET_IP_ALIGN == 2) 3689 type |= RX_BD_FLAGS_SOP; 3690 3691 rxr = &bp->rx_ring[ring_nr]; 3692 ring = &rxr->rx_ring_struct; 3693 bnxt_init_rxbd_pages(ring, type); 3694 3695 if (BNXT_RX_PAGE_MODE(bp) && bp->xdp_prog) { 3696 bpf_prog_add(bp->xdp_prog, 1); 3697 rxr->xdp_prog = bp->xdp_prog; 3698 } 3699 ring->fw_ring_id = INVALID_HW_RING_ID; 3700 3701 ring = &rxr->rx_agg_ring_struct; 3702 ring->fw_ring_id = INVALID_HW_RING_ID; 3703 3704 if ((bp->flags & BNXT_FLAG_AGG_RINGS)) { 3705 type = ((u32)BNXT_RX_PAGE_SIZE << RX_BD_LEN_SHIFT) | 3706 RX_BD_TYPE_RX_AGG_BD | RX_BD_FLAGS_SOP; 3707 3708 bnxt_init_rxbd_pages(ring, type); 3709 } 3710 3711 return bnxt_alloc_one_rx_ring(bp, ring_nr); 3712 } 3713 3714 static void bnxt_init_cp_rings(struct bnxt *bp) 3715 { 3716 int i, j; 3717 3718 for (i = 0; i < bp->cp_nr_rings; i++) { 3719 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring; 3720 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct; 3721 3722 ring->fw_ring_id = INVALID_HW_RING_ID; 3723 cpr->rx_ring_coal.coal_ticks = bp->rx_coal.coal_ticks; 3724 cpr->rx_ring_coal.coal_bufs = bp->rx_coal.coal_bufs; 3725 for (j = 0; j < 2; j++) { 3726 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j]; 3727 3728 if (!cpr2) 3729 continue; 3730 3731 ring = &cpr2->cp_ring_struct; 3732 ring->fw_ring_id = INVALID_HW_RING_ID; 3733 cpr2->rx_ring_coal.coal_ticks = bp->rx_coal.coal_ticks; 3734 cpr2->rx_ring_coal.coal_bufs = bp->rx_coal.coal_bufs; 3735 } 3736 } 3737 } 3738 3739 static int bnxt_init_rx_rings(struct bnxt *bp) 3740 { 3741 int i, rc = 0; 3742 3743 if (BNXT_RX_PAGE_MODE(bp)) { 3744 bp->rx_offset = NET_IP_ALIGN + XDP_PACKET_HEADROOM; 3745 bp->rx_dma_offset = XDP_PACKET_HEADROOM; 3746 } else { 3747 bp->rx_offset = BNXT_RX_OFFSET; 3748 bp->rx_dma_offset = BNXT_RX_DMA_OFFSET; 3749 } 3750 3751 for (i = 0; i < bp->rx_nr_rings; i++) { 3752 rc = bnxt_init_one_rx_ring(bp, i); 3753 if (rc) 3754 break; 3755 } 3756 3757 return rc; 3758 } 3759 3760 static int bnxt_init_tx_rings(struct bnxt *bp) 3761 { 3762 u16 i; 3763 3764 bp->tx_wake_thresh = max_t(int, bp->tx_ring_size / 2, 3765 BNXT_MIN_TX_DESC_CNT); 3766 3767 for (i = 0; i < bp->tx_nr_rings; i++) { 3768 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; 3769 struct bnxt_ring_struct *ring = &txr->tx_ring_struct; 3770 3771 ring->fw_ring_id = INVALID_HW_RING_ID; 3772 } 3773 3774 return 0; 3775 } 3776 3777 static void bnxt_free_ring_grps(struct bnxt *bp) 3778 { 3779 kfree(bp->grp_info); 3780 bp->grp_info = NULL; 3781 } 3782 3783 static int bnxt_init_ring_grps(struct bnxt *bp, bool irq_re_init) 3784 { 3785 int i; 3786 3787 if (irq_re_init) { 3788 bp->grp_info = kcalloc(bp->cp_nr_rings, 3789 sizeof(struct bnxt_ring_grp_info), 3790 GFP_KERNEL); 3791 if (!bp->grp_info) 3792 return -ENOMEM; 3793 } 3794 for (i = 0; i < bp->cp_nr_rings; i++) { 3795 if (irq_re_init) 3796 bp->grp_info[i].fw_stats_ctx = INVALID_HW_RING_ID; 3797 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID; 3798 bp->grp_info[i].rx_fw_ring_id = INVALID_HW_RING_ID; 3799 bp->grp_info[i].agg_fw_ring_id = INVALID_HW_RING_ID; 3800 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID; 3801 } 3802 return 0; 3803 } 3804 3805 static void bnxt_free_vnics(struct bnxt *bp) 3806 { 3807 kfree(bp->vnic_info); 3808 bp->vnic_info = NULL; 3809 bp->nr_vnics = 0; 3810 } 3811 3812 static int bnxt_alloc_vnics(struct bnxt *bp) 3813 { 3814 int num_vnics = 1; 3815 3816 #ifdef CONFIG_RFS_ACCEL 3817 if ((bp->flags & (BNXT_FLAG_RFS | BNXT_FLAG_CHIP_P5)) == BNXT_FLAG_RFS) 3818 num_vnics += bp->rx_nr_rings; 3819 #endif 3820 3821 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 3822 num_vnics++; 3823 3824 bp->vnic_info = kcalloc(num_vnics, sizeof(struct bnxt_vnic_info), 3825 GFP_KERNEL); 3826 if (!bp->vnic_info) 3827 return -ENOMEM; 3828 3829 bp->nr_vnics = num_vnics; 3830 return 0; 3831 } 3832 3833 static void bnxt_init_vnics(struct bnxt *bp) 3834 { 3835 int i; 3836 3837 for (i = 0; i < bp->nr_vnics; i++) { 3838 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 3839 int j; 3840 3841 vnic->fw_vnic_id = INVALID_HW_RING_ID; 3842 for (j = 0; j < BNXT_MAX_CTX_PER_VNIC; j++) 3843 vnic->fw_rss_cos_lb_ctx[j] = INVALID_HW_RING_ID; 3844 3845 vnic->fw_l2_ctx_id = INVALID_HW_RING_ID; 3846 3847 if (bp->vnic_info[i].rss_hash_key) { 3848 if (i == 0) 3849 get_random_bytes(vnic->rss_hash_key, 3850 HW_HASH_KEY_SIZE); 3851 else 3852 memcpy(vnic->rss_hash_key, 3853 bp->vnic_info[0].rss_hash_key, 3854 HW_HASH_KEY_SIZE); 3855 } 3856 } 3857 } 3858 3859 static int bnxt_calc_nr_ring_pages(u32 ring_size, int desc_per_pg) 3860 { 3861 int pages; 3862 3863 pages = ring_size / desc_per_pg; 3864 3865 if (!pages) 3866 return 1; 3867 3868 pages++; 3869 3870 while (pages & (pages - 1)) 3871 pages++; 3872 3873 return pages; 3874 } 3875 3876 void bnxt_set_tpa_flags(struct bnxt *bp) 3877 { 3878 bp->flags &= ~BNXT_FLAG_TPA; 3879 if (bp->flags & BNXT_FLAG_NO_AGG_RINGS) 3880 return; 3881 if (bp->dev->features & NETIF_F_LRO) 3882 bp->flags |= BNXT_FLAG_LRO; 3883 else if (bp->dev->features & NETIF_F_GRO_HW) 3884 bp->flags |= BNXT_FLAG_GRO; 3885 } 3886 3887 /* bp->rx_ring_size, bp->tx_ring_size, dev->mtu, BNXT_FLAG_{G|L}RO flags must 3888 * be set on entry. 3889 */ 3890 void bnxt_set_ring_params(struct bnxt *bp) 3891 { 3892 u32 ring_size, rx_size, rx_space, max_rx_cmpl; 3893 u32 agg_factor = 0, agg_ring_size = 0; 3894 3895 /* 8 for CRC and VLAN */ 3896 rx_size = SKB_DATA_ALIGN(bp->dev->mtu + ETH_HLEN + NET_IP_ALIGN + 8); 3897 3898 rx_space = rx_size + ALIGN(max(NET_SKB_PAD, XDP_PACKET_HEADROOM), 8) + 3899 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 3900 3901 bp->rx_copy_thresh = BNXT_RX_COPY_THRESH; 3902 ring_size = bp->rx_ring_size; 3903 bp->rx_agg_ring_size = 0; 3904 bp->rx_agg_nr_pages = 0; 3905 3906 if (bp->flags & BNXT_FLAG_TPA) 3907 agg_factor = min_t(u32, 4, 65536 / BNXT_RX_PAGE_SIZE); 3908 3909 bp->flags &= ~BNXT_FLAG_JUMBO; 3910 if (rx_space > PAGE_SIZE && !(bp->flags & BNXT_FLAG_NO_AGG_RINGS)) { 3911 u32 jumbo_factor; 3912 3913 bp->flags |= BNXT_FLAG_JUMBO; 3914 jumbo_factor = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT; 3915 if (jumbo_factor > agg_factor) 3916 agg_factor = jumbo_factor; 3917 } 3918 if (agg_factor) { 3919 if (ring_size > BNXT_MAX_RX_DESC_CNT_JUM_ENA) { 3920 ring_size = BNXT_MAX_RX_DESC_CNT_JUM_ENA; 3921 netdev_warn(bp->dev, "RX ring size reduced from %d to %d because the jumbo ring is now enabled\n", 3922 bp->rx_ring_size, ring_size); 3923 bp->rx_ring_size = ring_size; 3924 } 3925 agg_ring_size = ring_size * agg_factor; 3926 3927 bp->rx_agg_nr_pages = bnxt_calc_nr_ring_pages(agg_ring_size, 3928 RX_DESC_CNT); 3929 if (bp->rx_agg_nr_pages > MAX_RX_AGG_PAGES) { 3930 u32 tmp = agg_ring_size; 3931 3932 bp->rx_agg_nr_pages = MAX_RX_AGG_PAGES; 3933 agg_ring_size = MAX_RX_AGG_PAGES * RX_DESC_CNT - 1; 3934 netdev_warn(bp->dev, "rx agg ring size %d reduced to %d.\n", 3935 tmp, agg_ring_size); 3936 } 3937 bp->rx_agg_ring_size = agg_ring_size; 3938 bp->rx_agg_ring_mask = (bp->rx_agg_nr_pages * RX_DESC_CNT) - 1; 3939 3940 if (BNXT_RX_PAGE_MODE(bp)) { 3941 rx_space = PAGE_SIZE; 3942 rx_size = PAGE_SIZE - 3943 ALIGN(max(NET_SKB_PAD, XDP_PACKET_HEADROOM), 8) - 3944 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 3945 } else { 3946 rx_size = SKB_DATA_ALIGN(BNXT_RX_COPY_THRESH + NET_IP_ALIGN); 3947 rx_space = rx_size + NET_SKB_PAD + 3948 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 3949 } 3950 } 3951 3952 bp->rx_buf_use_size = rx_size; 3953 bp->rx_buf_size = rx_space; 3954 3955 bp->rx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, RX_DESC_CNT); 3956 bp->rx_ring_mask = (bp->rx_nr_pages * RX_DESC_CNT) - 1; 3957 3958 ring_size = bp->tx_ring_size; 3959 bp->tx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, TX_DESC_CNT); 3960 bp->tx_ring_mask = (bp->tx_nr_pages * TX_DESC_CNT) - 1; 3961 3962 max_rx_cmpl = bp->rx_ring_size; 3963 /* MAX TPA needs to be added because TPA_START completions are 3964 * immediately recycled, so the TPA completions are not bound by 3965 * the RX ring size. 3966 */ 3967 if (bp->flags & BNXT_FLAG_TPA) 3968 max_rx_cmpl += bp->max_tpa; 3969 /* RX and TPA completions are 32-byte, all others are 16-byte */ 3970 ring_size = max_rx_cmpl * 2 + agg_ring_size + bp->tx_ring_size; 3971 bp->cp_ring_size = ring_size; 3972 3973 bp->cp_nr_pages = bnxt_calc_nr_ring_pages(ring_size, CP_DESC_CNT); 3974 if (bp->cp_nr_pages > MAX_CP_PAGES) { 3975 bp->cp_nr_pages = MAX_CP_PAGES; 3976 bp->cp_ring_size = MAX_CP_PAGES * CP_DESC_CNT - 1; 3977 netdev_warn(bp->dev, "completion ring size %d reduced to %d.\n", 3978 ring_size, bp->cp_ring_size); 3979 } 3980 bp->cp_bit = bp->cp_nr_pages * CP_DESC_CNT; 3981 bp->cp_ring_mask = bp->cp_bit - 1; 3982 } 3983 3984 /* Changing allocation mode of RX rings. 3985 * TODO: Update when extending xdp_rxq_info to support allocation modes. 3986 */ 3987 int bnxt_set_rx_skb_mode(struct bnxt *bp, bool page_mode) 3988 { 3989 if (page_mode) { 3990 bp->flags &= ~BNXT_FLAG_AGG_RINGS; 3991 bp->flags |= BNXT_FLAG_RX_PAGE_MODE; 3992 3993 if (bp->dev->mtu > BNXT_MAX_PAGE_MODE_MTU) { 3994 bp->flags |= BNXT_FLAG_JUMBO; 3995 bp->rx_skb_func = bnxt_rx_multi_page_skb; 3996 bp->dev->max_mtu = 3997 min_t(u16, bp->max_mtu, BNXT_MAX_MTU); 3998 } else { 3999 bp->flags |= BNXT_FLAG_NO_AGG_RINGS; 4000 bp->rx_skb_func = bnxt_rx_page_skb; 4001 bp->dev->max_mtu = 4002 min_t(u16, bp->max_mtu, BNXT_MAX_PAGE_MODE_MTU); 4003 } 4004 bp->rx_dir = DMA_BIDIRECTIONAL; 4005 /* Disable LRO or GRO_HW */ 4006 netdev_update_features(bp->dev); 4007 } else { 4008 bp->dev->max_mtu = bp->max_mtu; 4009 bp->flags &= ~BNXT_FLAG_RX_PAGE_MODE; 4010 bp->rx_dir = DMA_FROM_DEVICE; 4011 bp->rx_skb_func = bnxt_rx_skb; 4012 } 4013 return 0; 4014 } 4015 4016 static void bnxt_free_vnic_attributes(struct bnxt *bp) 4017 { 4018 int i; 4019 struct bnxt_vnic_info *vnic; 4020 struct pci_dev *pdev = bp->pdev; 4021 4022 if (!bp->vnic_info) 4023 return; 4024 4025 for (i = 0; i < bp->nr_vnics; i++) { 4026 vnic = &bp->vnic_info[i]; 4027 4028 kfree(vnic->fw_grp_ids); 4029 vnic->fw_grp_ids = NULL; 4030 4031 kfree(vnic->uc_list); 4032 vnic->uc_list = NULL; 4033 4034 if (vnic->mc_list) { 4035 dma_free_coherent(&pdev->dev, vnic->mc_list_size, 4036 vnic->mc_list, vnic->mc_list_mapping); 4037 vnic->mc_list = NULL; 4038 } 4039 4040 if (vnic->rss_table) { 4041 dma_free_coherent(&pdev->dev, vnic->rss_table_size, 4042 vnic->rss_table, 4043 vnic->rss_table_dma_addr); 4044 vnic->rss_table = NULL; 4045 } 4046 4047 vnic->rss_hash_key = NULL; 4048 vnic->flags = 0; 4049 } 4050 } 4051 4052 static int bnxt_alloc_vnic_attributes(struct bnxt *bp) 4053 { 4054 int i, rc = 0, size; 4055 struct bnxt_vnic_info *vnic; 4056 struct pci_dev *pdev = bp->pdev; 4057 int max_rings; 4058 4059 for (i = 0; i < bp->nr_vnics; i++) { 4060 vnic = &bp->vnic_info[i]; 4061 4062 if (vnic->flags & BNXT_VNIC_UCAST_FLAG) { 4063 int mem_size = (BNXT_MAX_UC_ADDRS - 1) * ETH_ALEN; 4064 4065 if (mem_size > 0) { 4066 vnic->uc_list = kmalloc(mem_size, GFP_KERNEL); 4067 if (!vnic->uc_list) { 4068 rc = -ENOMEM; 4069 goto out; 4070 } 4071 } 4072 } 4073 4074 if (vnic->flags & BNXT_VNIC_MCAST_FLAG) { 4075 vnic->mc_list_size = BNXT_MAX_MC_ADDRS * ETH_ALEN; 4076 vnic->mc_list = 4077 dma_alloc_coherent(&pdev->dev, 4078 vnic->mc_list_size, 4079 &vnic->mc_list_mapping, 4080 GFP_KERNEL); 4081 if (!vnic->mc_list) { 4082 rc = -ENOMEM; 4083 goto out; 4084 } 4085 } 4086 4087 if (bp->flags & BNXT_FLAG_CHIP_P5) 4088 goto vnic_skip_grps; 4089 4090 if (vnic->flags & BNXT_VNIC_RSS_FLAG) 4091 max_rings = bp->rx_nr_rings; 4092 else 4093 max_rings = 1; 4094 4095 vnic->fw_grp_ids = kcalloc(max_rings, sizeof(u16), GFP_KERNEL); 4096 if (!vnic->fw_grp_ids) { 4097 rc = -ENOMEM; 4098 goto out; 4099 } 4100 vnic_skip_grps: 4101 if ((bp->flags & BNXT_FLAG_NEW_RSS_CAP) && 4102 !(vnic->flags & BNXT_VNIC_RSS_FLAG)) 4103 continue; 4104 4105 /* Allocate rss table and hash key */ 4106 size = L1_CACHE_ALIGN(HW_HASH_INDEX_SIZE * sizeof(u16)); 4107 if (bp->flags & BNXT_FLAG_CHIP_P5) 4108 size = L1_CACHE_ALIGN(BNXT_MAX_RSS_TABLE_SIZE_P5); 4109 4110 vnic->rss_table_size = size + HW_HASH_KEY_SIZE; 4111 vnic->rss_table = dma_alloc_coherent(&pdev->dev, 4112 vnic->rss_table_size, 4113 &vnic->rss_table_dma_addr, 4114 GFP_KERNEL); 4115 if (!vnic->rss_table) { 4116 rc = -ENOMEM; 4117 goto out; 4118 } 4119 4120 vnic->rss_hash_key = ((void *)vnic->rss_table) + size; 4121 vnic->rss_hash_key_dma_addr = vnic->rss_table_dma_addr + size; 4122 } 4123 return 0; 4124 4125 out: 4126 return rc; 4127 } 4128 4129 static void bnxt_free_hwrm_resources(struct bnxt *bp) 4130 { 4131 struct bnxt_hwrm_wait_token *token; 4132 4133 dma_pool_destroy(bp->hwrm_dma_pool); 4134 bp->hwrm_dma_pool = NULL; 4135 4136 rcu_read_lock(); 4137 hlist_for_each_entry_rcu(token, &bp->hwrm_pending_list, node) 4138 WRITE_ONCE(token->state, BNXT_HWRM_CANCELLED); 4139 rcu_read_unlock(); 4140 } 4141 4142 static int bnxt_alloc_hwrm_resources(struct bnxt *bp) 4143 { 4144 bp->hwrm_dma_pool = dma_pool_create("bnxt_hwrm", &bp->pdev->dev, 4145 BNXT_HWRM_DMA_SIZE, 4146 BNXT_HWRM_DMA_ALIGN, 0); 4147 if (!bp->hwrm_dma_pool) 4148 return -ENOMEM; 4149 4150 INIT_HLIST_HEAD(&bp->hwrm_pending_list); 4151 4152 return 0; 4153 } 4154 4155 static void bnxt_free_stats_mem(struct bnxt *bp, struct bnxt_stats_mem *stats) 4156 { 4157 kfree(stats->hw_masks); 4158 stats->hw_masks = NULL; 4159 kfree(stats->sw_stats); 4160 stats->sw_stats = NULL; 4161 if (stats->hw_stats) { 4162 dma_free_coherent(&bp->pdev->dev, stats->len, stats->hw_stats, 4163 stats->hw_stats_map); 4164 stats->hw_stats = NULL; 4165 } 4166 } 4167 4168 static int bnxt_alloc_stats_mem(struct bnxt *bp, struct bnxt_stats_mem *stats, 4169 bool alloc_masks) 4170 { 4171 stats->hw_stats = dma_alloc_coherent(&bp->pdev->dev, stats->len, 4172 &stats->hw_stats_map, GFP_KERNEL); 4173 if (!stats->hw_stats) 4174 return -ENOMEM; 4175 4176 stats->sw_stats = kzalloc(stats->len, GFP_KERNEL); 4177 if (!stats->sw_stats) 4178 goto stats_mem_err; 4179 4180 if (alloc_masks) { 4181 stats->hw_masks = kzalloc(stats->len, GFP_KERNEL); 4182 if (!stats->hw_masks) 4183 goto stats_mem_err; 4184 } 4185 return 0; 4186 4187 stats_mem_err: 4188 bnxt_free_stats_mem(bp, stats); 4189 return -ENOMEM; 4190 } 4191 4192 static void bnxt_fill_masks(u64 *mask_arr, u64 mask, int count) 4193 { 4194 int i; 4195 4196 for (i = 0; i < count; i++) 4197 mask_arr[i] = mask; 4198 } 4199 4200 static void bnxt_copy_hw_masks(u64 *mask_arr, __le64 *hw_mask_arr, int count) 4201 { 4202 int i; 4203 4204 for (i = 0; i < count; i++) 4205 mask_arr[i] = le64_to_cpu(hw_mask_arr[i]); 4206 } 4207 4208 static int bnxt_hwrm_func_qstat_ext(struct bnxt *bp, 4209 struct bnxt_stats_mem *stats) 4210 { 4211 struct hwrm_func_qstats_ext_output *resp; 4212 struct hwrm_func_qstats_ext_input *req; 4213 __le64 *hw_masks; 4214 int rc; 4215 4216 if (!(bp->fw_cap & BNXT_FW_CAP_EXT_HW_STATS_SUPPORTED) || 4217 !(bp->flags & BNXT_FLAG_CHIP_P5)) 4218 return -EOPNOTSUPP; 4219 4220 rc = hwrm_req_init(bp, req, HWRM_FUNC_QSTATS_EXT); 4221 if (rc) 4222 return rc; 4223 4224 req->fid = cpu_to_le16(0xffff); 4225 req->flags = FUNC_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK; 4226 4227 resp = hwrm_req_hold(bp, req); 4228 rc = hwrm_req_send(bp, req); 4229 if (!rc) { 4230 hw_masks = &resp->rx_ucast_pkts; 4231 bnxt_copy_hw_masks(stats->hw_masks, hw_masks, stats->len / 8); 4232 } 4233 hwrm_req_drop(bp, req); 4234 return rc; 4235 } 4236 4237 static int bnxt_hwrm_port_qstats(struct bnxt *bp, u8 flags); 4238 static int bnxt_hwrm_port_qstats_ext(struct bnxt *bp, u8 flags); 4239 4240 static void bnxt_init_stats(struct bnxt *bp) 4241 { 4242 struct bnxt_napi *bnapi = bp->bnapi[0]; 4243 struct bnxt_cp_ring_info *cpr; 4244 struct bnxt_stats_mem *stats; 4245 __le64 *rx_stats, *tx_stats; 4246 int rc, rx_count, tx_count; 4247 u64 *rx_masks, *tx_masks; 4248 u64 mask; 4249 u8 flags; 4250 4251 cpr = &bnapi->cp_ring; 4252 stats = &cpr->stats; 4253 rc = bnxt_hwrm_func_qstat_ext(bp, stats); 4254 if (rc) { 4255 if (bp->flags & BNXT_FLAG_CHIP_P5) 4256 mask = (1ULL << 48) - 1; 4257 else 4258 mask = -1ULL; 4259 bnxt_fill_masks(stats->hw_masks, mask, stats->len / 8); 4260 } 4261 if (bp->flags & BNXT_FLAG_PORT_STATS) { 4262 stats = &bp->port_stats; 4263 rx_stats = stats->hw_stats; 4264 rx_masks = stats->hw_masks; 4265 rx_count = sizeof(struct rx_port_stats) / 8; 4266 tx_stats = rx_stats + BNXT_TX_PORT_STATS_BYTE_OFFSET / 8; 4267 tx_masks = rx_masks + BNXT_TX_PORT_STATS_BYTE_OFFSET / 8; 4268 tx_count = sizeof(struct tx_port_stats) / 8; 4269 4270 flags = PORT_QSTATS_REQ_FLAGS_COUNTER_MASK; 4271 rc = bnxt_hwrm_port_qstats(bp, flags); 4272 if (rc) { 4273 mask = (1ULL << 40) - 1; 4274 4275 bnxt_fill_masks(rx_masks, mask, rx_count); 4276 bnxt_fill_masks(tx_masks, mask, tx_count); 4277 } else { 4278 bnxt_copy_hw_masks(rx_masks, rx_stats, rx_count); 4279 bnxt_copy_hw_masks(tx_masks, tx_stats, tx_count); 4280 bnxt_hwrm_port_qstats(bp, 0); 4281 } 4282 } 4283 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) { 4284 stats = &bp->rx_port_stats_ext; 4285 rx_stats = stats->hw_stats; 4286 rx_masks = stats->hw_masks; 4287 rx_count = sizeof(struct rx_port_stats_ext) / 8; 4288 stats = &bp->tx_port_stats_ext; 4289 tx_stats = stats->hw_stats; 4290 tx_masks = stats->hw_masks; 4291 tx_count = sizeof(struct tx_port_stats_ext) / 8; 4292 4293 flags = PORT_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK; 4294 rc = bnxt_hwrm_port_qstats_ext(bp, flags); 4295 if (rc) { 4296 mask = (1ULL << 40) - 1; 4297 4298 bnxt_fill_masks(rx_masks, mask, rx_count); 4299 if (tx_stats) 4300 bnxt_fill_masks(tx_masks, mask, tx_count); 4301 } else { 4302 bnxt_copy_hw_masks(rx_masks, rx_stats, rx_count); 4303 if (tx_stats) 4304 bnxt_copy_hw_masks(tx_masks, tx_stats, 4305 tx_count); 4306 bnxt_hwrm_port_qstats_ext(bp, 0); 4307 } 4308 } 4309 } 4310 4311 static void bnxt_free_port_stats(struct bnxt *bp) 4312 { 4313 bp->flags &= ~BNXT_FLAG_PORT_STATS; 4314 bp->flags &= ~BNXT_FLAG_PORT_STATS_EXT; 4315 4316 bnxt_free_stats_mem(bp, &bp->port_stats); 4317 bnxt_free_stats_mem(bp, &bp->rx_port_stats_ext); 4318 bnxt_free_stats_mem(bp, &bp->tx_port_stats_ext); 4319 } 4320 4321 static void bnxt_free_ring_stats(struct bnxt *bp) 4322 { 4323 int i; 4324 4325 if (!bp->bnapi) 4326 return; 4327 4328 for (i = 0; i < bp->cp_nr_rings; i++) { 4329 struct bnxt_napi *bnapi = bp->bnapi[i]; 4330 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 4331 4332 bnxt_free_stats_mem(bp, &cpr->stats); 4333 } 4334 } 4335 4336 static int bnxt_alloc_stats(struct bnxt *bp) 4337 { 4338 u32 size, i; 4339 int rc; 4340 4341 size = bp->hw_ring_stats_size; 4342 4343 for (i = 0; i < bp->cp_nr_rings; i++) { 4344 struct bnxt_napi *bnapi = bp->bnapi[i]; 4345 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 4346 4347 cpr->stats.len = size; 4348 rc = bnxt_alloc_stats_mem(bp, &cpr->stats, !i); 4349 if (rc) 4350 return rc; 4351 4352 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID; 4353 } 4354 4355 if (BNXT_VF(bp) || bp->chip_num == CHIP_NUM_58700) 4356 return 0; 4357 4358 if (bp->port_stats.hw_stats) 4359 goto alloc_ext_stats; 4360 4361 bp->port_stats.len = BNXT_PORT_STATS_SIZE; 4362 rc = bnxt_alloc_stats_mem(bp, &bp->port_stats, true); 4363 if (rc) 4364 return rc; 4365 4366 bp->flags |= BNXT_FLAG_PORT_STATS; 4367 4368 alloc_ext_stats: 4369 /* Display extended statistics only if FW supports it */ 4370 if (bp->hwrm_spec_code < 0x10804 || bp->hwrm_spec_code == 0x10900) 4371 if (!(bp->fw_cap & BNXT_FW_CAP_EXT_STATS_SUPPORTED)) 4372 return 0; 4373 4374 if (bp->rx_port_stats_ext.hw_stats) 4375 goto alloc_tx_ext_stats; 4376 4377 bp->rx_port_stats_ext.len = sizeof(struct rx_port_stats_ext); 4378 rc = bnxt_alloc_stats_mem(bp, &bp->rx_port_stats_ext, true); 4379 /* Extended stats are optional */ 4380 if (rc) 4381 return 0; 4382 4383 alloc_tx_ext_stats: 4384 if (bp->tx_port_stats_ext.hw_stats) 4385 return 0; 4386 4387 if (bp->hwrm_spec_code >= 0x10902 || 4388 (bp->fw_cap & BNXT_FW_CAP_EXT_STATS_SUPPORTED)) { 4389 bp->tx_port_stats_ext.len = sizeof(struct tx_port_stats_ext); 4390 rc = bnxt_alloc_stats_mem(bp, &bp->tx_port_stats_ext, true); 4391 /* Extended stats are optional */ 4392 if (rc) 4393 return 0; 4394 } 4395 bp->flags |= BNXT_FLAG_PORT_STATS_EXT; 4396 return 0; 4397 } 4398 4399 static void bnxt_clear_ring_indices(struct bnxt *bp) 4400 { 4401 int i; 4402 4403 if (!bp->bnapi) 4404 return; 4405 4406 for (i = 0; i < bp->cp_nr_rings; i++) { 4407 struct bnxt_napi *bnapi = bp->bnapi[i]; 4408 struct bnxt_cp_ring_info *cpr; 4409 struct bnxt_rx_ring_info *rxr; 4410 struct bnxt_tx_ring_info *txr; 4411 4412 if (!bnapi) 4413 continue; 4414 4415 cpr = &bnapi->cp_ring; 4416 cpr->cp_raw_cons = 0; 4417 4418 txr = bnapi->tx_ring; 4419 if (txr) { 4420 txr->tx_prod = 0; 4421 txr->tx_cons = 0; 4422 } 4423 4424 rxr = bnapi->rx_ring; 4425 if (rxr) { 4426 rxr->rx_prod = 0; 4427 rxr->rx_agg_prod = 0; 4428 rxr->rx_sw_agg_prod = 0; 4429 rxr->rx_next_cons = 0; 4430 } 4431 } 4432 } 4433 4434 static void bnxt_free_ntp_fltrs(struct bnxt *bp, bool irq_reinit) 4435 { 4436 #ifdef CONFIG_RFS_ACCEL 4437 int i; 4438 4439 /* Under rtnl_lock and all our NAPIs have been disabled. It's 4440 * safe to delete the hash table. 4441 */ 4442 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) { 4443 struct hlist_head *head; 4444 struct hlist_node *tmp; 4445 struct bnxt_ntuple_filter *fltr; 4446 4447 head = &bp->ntp_fltr_hash_tbl[i]; 4448 hlist_for_each_entry_safe(fltr, tmp, head, hash) { 4449 hlist_del(&fltr->hash); 4450 kfree(fltr); 4451 } 4452 } 4453 if (irq_reinit) { 4454 bitmap_free(bp->ntp_fltr_bmap); 4455 bp->ntp_fltr_bmap = NULL; 4456 } 4457 bp->ntp_fltr_count = 0; 4458 #endif 4459 } 4460 4461 static int bnxt_alloc_ntp_fltrs(struct bnxt *bp) 4462 { 4463 #ifdef CONFIG_RFS_ACCEL 4464 int i, rc = 0; 4465 4466 if (!(bp->flags & BNXT_FLAG_RFS)) 4467 return 0; 4468 4469 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) 4470 INIT_HLIST_HEAD(&bp->ntp_fltr_hash_tbl[i]); 4471 4472 bp->ntp_fltr_count = 0; 4473 bp->ntp_fltr_bmap = bitmap_zalloc(BNXT_NTP_FLTR_MAX_FLTR, GFP_KERNEL); 4474 4475 if (!bp->ntp_fltr_bmap) 4476 rc = -ENOMEM; 4477 4478 return rc; 4479 #else 4480 return 0; 4481 #endif 4482 } 4483 4484 static void bnxt_free_mem(struct bnxt *bp, bool irq_re_init) 4485 { 4486 bnxt_free_vnic_attributes(bp); 4487 bnxt_free_tx_rings(bp); 4488 bnxt_free_rx_rings(bp); 4489 bnxt_free_cp_rings(bp); 4490 bnxt_free_all_cp_arrays(bp); 4491 bnxt_free_ntp_fltrs(bp, irq_re_init); 4492 if (irq_re_init) { 4493 bnxt_free_ring_stats(bp); 4494 if (!(bp->phy_flags & BNXT_PHY_FL_PORT_STATS_NO_RESET) || 4495 test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) 4496 bnxt_free_port_stats(bp); 4497 bnxt_free_ring_grps(bp); 4498 bnxt_free_vnics(bp); 4499 kfree(bp->tx_ring_map); 4500 bp->tx_ring_map = NULL; 4501 kfree(bp->tx_ring); 4502 bp->tx_ring = NULL; 4503 kfree(bp->rx_ring); 4504 bp->rx_ring = NULL; 4505 kfree(bp->bnapi); 4506 bp->bnapi = NULL; 4507 } else { 4508 bnxt_clear_ring_indices(bp); 4509 } 4510 } 4511 4512 static int bnxt_alloc_mem(struct bnxt *bp, bool irq_re_init) 4513 { 4514 int i, j, rc, size, arr_size; 4515 void *bnapi; 4516 4517 if (irq_re_init) { 4518 /* Allocate bnapi mem pointer array and mem block for 4519 * all queues 4520 */ 4521 arr_size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi *) * 4522 bp->cp_nr_rings); 4523 size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi)); 4524 bnapi = kzalloc(arr_size + size * bp->cp_nr_rings, GFP_KERNEL); 4525 if (!bnapi) 4526 return -ENOMEM; 4527 4528 bp->bnapi = bnapi; 4529 bnapi += arr_size; 4530 for (i = 0; i < bp->cp_nr_rings; i++, bnapi += size) { 4531 bp->bnapi[i] = bnapi; 4532 bp->bnapi[i]->index = i; 4533 bp->bnapi[i]->bp = bp; 4534 if (bp->flags & BNXT_FLAG_CHIP_P5) { 4535 struct bnxt_cp_ring_info *cpr = 4536 &bp->bnapi[i]->cp_ring; 4537 4538 cpr->cp_ring_struct.ring_mem.flags = 4539 BNXT_RMEM_RING_PTE_FLAG; 4540 } 4541 } 4542 4543 bp->rx_ring = kcalloc(bp->rx_nr_rings, 4544 sizeof(struct bnxt_rx_ring_info), 4545 GFP_KERNEL); 4546 if (!bp->rx_ring) 4547 return -ENOMEM; 4548 4549 for (i = 0; i < bp->rx_nr_rings; i++) { 4550 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 4551 4552 if (bp->flags & BNXT_FLAG_CHIP_P5) { 4553 rxr->rx_ring_struct.ring_mem.flags = 4554 BNXT_RMEM_RING_PTE_FLAG; 4555 rxr->rx_agg_ring_struct.ring_mem.flags = 4556 BNXT_RMEM_RING_PTE_FLAG; 4557 } 4558 rxr->bnapi = bp->bnapi[i]; 4559 bp->bnapi[i]->rx_ring = &bp->rx_ring[i]; 4560 } 4561 4562 bp->tx_ring = kcalloc(bp->tx_nr_rings, 4563 sizeof(struct bnxt_tx_ring_info), 4564 GFP_KERNEL); 4565 if (!bp->tx_ring) 4566 return -ENOMEM; 4567 4568 bp->tx_ring_map = kcalloc(bp->tx_nr_rings, sizeof(u16), 4569 GFP_KERNEL); 4570 4571 if (!bp->tx_ring_map) 4572 return -ENOMEM; 4573 4574 if (bp->flags & BNXT_FLAG_SHARED_RINGS) 4575 j = 0; 4576 else 4577 j = bp->rx_nr_rings; 4578 4579 for (i = 0; i < bp->tx_nr_rings; i++, j++) { 4580 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; 4581 4582 if (bp->flags & BNXT_FLAG_CHIP_P5) 4583 txr->tx_ring_struct.ring_mem.flags = 4584 BNXT_RMEM_RING_PTE_FLAG; 4585 txr->bnapi = bp->bnapi[j]; 4586 bp->bnapi[j]->tx_ring = txr; 4587 bp->tx_ring_map[i] = bp->tx_nr_rings_xdp + i; 4588 if (i >= bp->tx_nr_rings_xdp) { 4589 txr->txq_index = i - bp->tx_nr_rings_xdp; 4590 bp->bnapi[j]->tx_int = bnxt_tx_int; 4591 } else { 4592 bp->bnapi[j]->flags |= BNXT_NAPI_FLAG_XDP; 4593 bp->bnapi[j]->tx_int = bnxt_tx_int_xdp; 4594 } 4595 } 4596 4597 rc = bnxt_alloc_stats(bp); 4598 if (rc) 4599 goto alloc_mem_err; 4600 bnxt_init_stats(bp); 4601 4602 rc = bnxt_alloc_ntp_fltrs(bp); 4603 if (rc) 4604 goto alloc_mem_err; 4605 4606 rc = bnxt_alloc_vnics(bp); 4607 if (rc) 4608 goto alloc_mem_err; 4609 } 4610 4611 rc = bnxt_alloc_all_cp_arrays(bp); 4612 if (rc) 4613 goto alloc_mem_err; 4614 4615 bnxt_init_ring_struct(bp); 4616 4617 rc = bnxt_alloc_rx_rings(bp); 4618 if (rc) 4619 goto alloc_mem_err; 4620 4621 rc = bnxt_alloc_tx_rings(bp); 4622 if (rc) 4623 goto alloc_mem_err; 4624 4625 rc = bnxt_alloc_cp_rings(bp); 4626 if (rc) 4627 goto alloc_mem_err; 4628 4629 bp->vnic_info[0].flags |= BNXT_VNIC_RSS_FLAG | BNXT_VNIC_MCAST_FLAG | 4630 BNXT_VNIC_UCAST_FLAG; 4631 rc = bnxt_alloc_vnic_attributes(bp); 4632 if (rc) 4633 goto alloc_mem_err; 4634 return 0; 4635 4636 alloc_mem_err: 4637 bnxt_free_mem(bp, true); 4638 return rc; 4639 } 4640 4641 static void bnxt_disable_int(struct bnxt *bp) 4642 { 4643 int i; 4644 4645 if (!bp->bnapi) 4646 return; 4647 4648 for (i = 0; i < bp->cp_nr_rings; i++) { 4649 struct bnxt_napi *bnapi = bp->bnapi[i]; 4650 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 4651 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct; 4652 4653 if (ring->fw_ring_id != INVALID_HW_RING_ID) 4654 bnxt_db_nq(bp, &cpr->cp_db, cpr->cp_raw_cons); 4655 } 4656 } 4657 4658 static int bnxt_cp_num_to_irq_num(struct bnxt *bp, int n) 4659 { 4660 struct bnxt_napi *bnapi = bp->bnapi[n]; 4661 struct bnxt_cp_ring_info *cpr; 4662 4663 cpr = &bnapi->cp_ring; 4664 return cpr->cp_ring_struct.map_idx; 4665 } 4666 4667 static void bnxt_disable_int_sync(struct bnxt *bp) 4668 { 4669 int i; 4670 4671 if (!bp->irq_tbl) 4672 return; 4673 4674 atomic_inc(&bp->intr_sem); 4675 4676 bnxt_disable_int(bp); 4677 for (i = 0; i < bp->cp_nr_rings; i++) { 4678 int map_idx = bnxt_cp_num_to_irq_num(bp, i); 4679 4680 synchronize_irq(bp->irq_tbl[map_idx].vector); 4681 } 4682 } 4683 4684 static void bnxt_enable_int(struct bnxt *bp) 4685 { 4686 int i; 4687 4688 atomic_set(&bp->intr_sem, 0); 4689 for (i = 0; i < bp->cp_nr_rings; i++) { 4690 struct bnxt_napi *bnapi = bp->bnapi[i]; 4691 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 4692 4693 bnxt_db_nq_arm(bp, &cpr->cp_db, cpr->cp_raw_cons); 4694 } 4695 } 4696 4697 int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp, unsigned long *bmap, int bmap_size, 4698 bool async_only) 4699 { 4700 DECLARE_BITMAP(async_events_bmap, 256); 4701 u32 *events = (u32 *)async_events_bmap; 4702 struct hwrm_func_drv_rgtr_output *resp; 4703 struct hwrm_func_drv_rgtr_input *req; 4704 u32 flags; 4705 int rc, i; 4706 4707 rc = hwrm_req_init(bp, req, HWRM_FUNC_DRV_RGTR); 4708 if (rc) 4709 return rc; 4710 4711 req->enables = cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE | 4712 FUNC_DRV_RGTR_REQ_ENABLES_VER | 4713 FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD); 4714 4715 req->os_type = cpu_to_le16(FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX); 4716 flags = FUNC_DRV_RGTR_REQ_FLAGS_16BIT_VER_MODE; 4717 if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET) 4718 flags |= FUNC_DRV_RGTR_REQ_FLAGS_HOT_RESET_SUPPORT; 4719 if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY) 4720 flags |= FUNC_DRV_RGTR_REQ_FLAGS_ERROR_RECOVERY_SUPPORT | 4721 FUNC_DRV_RGTR_REQ_FLAGS_MASTER_SUPPORT; 4722 req->flags = cpu_to_le32(flags); 4723 req->ver_maj_8b = DRV_VER_MAJ; 4724 req->ver_min_8b = DRV_VER_MIN; 4725 req->ver_upd_8b = DRV_VER_UPD; 4726 req->ver_maj = cpu_to_le16(DRV_VER_MAJ); 4727 req->ver_min = cpu_to_le16(DRV_VER_MIN); 4728 req->ver_upd = cpu_to_le16(DRV_VER_UPD); 4729 4730 if (BNXT_PF(bp)) { 4731 u32 data[8]; 4732 int i; 4733 4734 memset(data, 0, sizeof(data)); 4735 for (i = 0; i < ARRAY_SIZE(bnxt_vf_req_snif); i++) { 4736 u16 cmd = bnxt_vf_req_snif[i]; 4737 unsigned int bit, idx; 4738 4739 idx = cmd / 32; 4740 bit = cmd % 32; 4741 data[idx] |= 1 << bit; 4742 } 4743 4744 for (i = 0; i < 8; i++) 4745 req->vf_req_fwd[i] = cpu_to_le32(data[i]); 4746 4747 req->enables |= 4748 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD); 4749 } 4750 4751 if (bp->fw_cap & BNXT_FW_CAP_OVS_64BIT_HANDLE) 4752 req->flags |= cpu_to_le32( 4753 FUNC_DRV_RGTR_REQ_FLAGS_FLOW_HANDLE_64BIT_MODE); 4754 4755 memset(async_events_bmap, 0, sizeof(async_events_bmap)); 4756 for (i = 0; i < ARRAY_SIZE(bnxt_async_events_arr); i++) { 4757 u16 event_id = bnxt_async_events_arr[i]; 4758 4759 if (event_id == ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY && 4760 !(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)) 4761 continue; 4762 __set_bit(bnxt_async_events_arr[i], async_events_bmap); 4763 } 4764 if (bmap && bmap_size) { 4765 for (i = 0; i < bmap_size; i++) { 4766 if (test_bit(i, bmap)) 4767 __set_bit(i, async_events_bmap); 4768 } 4769 } 4770 for (i = 0; i < 8; i++) 4771 req->async_event_fwd[i] |= cpu_to_le32(events[i]); 4772 4773 if (async_only) 4774 req->enables = 4775 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD); 4776 4777 resp = hwrm_req_hold(bp, req); 4778 rc = hwrm_req_send(bp, req); 4779 if (!rc) { 4780 set_bit(BNXT_STATE_DRV_REGISTERED, &bp->state); 4781 if (resp->flags & 4782 cpu_to_le32(FUNC_DRV_RGTR_RESP_FLAGS_IF_CHANGE_SUPPORTED)) 4783 bp->fw_cap |= BNXT_FW_CAP_IF_CHANGE; 4784 } 4785 hwrm_req_drop(bp, req); 4786 return rc; 4787 } 4788 4789 int bnxt_hwrm_func_drv_unrgtr(struct bnxt *bp) 4790 { 4791 struct hwrm_func_drv_unrgtr_input *req; 4792 int rc; 4793 4794 if (!test_and_clear_bit(BNXT_STATE_DRV_REGISTERED, &bp->state)) 4795 return 0; 4796 4797 rc = hwrm_req_init(bp, req, HWRM_FUNC_DRV_UNRGTR); 4798 if (rc) 4799 return rc; 4800 return hwrm_req_send(bp, req); 4801 } 4802 4803 static int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, u8 tunnel_type) 4804 { 4805 struct hwrm_tunnel_dst_port_free_input *req; 4806 int rc; 4807 4808 if (tunnel_type == TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN && 4809 bp->vxlan_fw_dst_port_id == INVALID_HW_RING_ID) 4810 return 0; 4811 if (tunnel_type == TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE && 4812 bp->nge_fw_dst_port_id == INVALID_HW_RING_ID) 4813 return 0; 4814 4815 rc = hwrm_req_init(bp, req, HWRM_TUNNEL_DST_PORT_FREE); 4816 if (rc) 4817 return rc; 4818 4819 req->tunnel_type = tunnel_type; 4820 4821 switch (tunnel_type) { 4822 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN: 4823 req->tunnel_dst_port_id = cpu_to_le16(bp->vxlan_fw_dst_port_id); 4824 bp->vxlan_port = 0; 4825 bp->vxlan_fw_dst_port_id = INVALID_HW_RING_ID; 4826 break; 4827 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE: 4828 req->tunnel_dst_port_id = cpu_to_le16(bp->nge_fw_dst_port_id); 4829 bp->nge_port = 0; 4830 bp->nge_fw_dst_port_id = INVALID_HW_RING_ID; 4831 break; 4832 default: 4833 break; 4834 } 4835 4836 rc = hwrm_req_send(bp, req); 4837 if (rc) 4838 netdev_err(bp->dev, "hwrm_tunnel_dst_port_free failed. rc:%d\n", 4839 rc); 4840 return rc; 4841 } 4842 4843 static int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, __be16 port, 4844 u8 tunnel_type) 4845 { 4846 struct hwrm_tunnel_dst_port_alloc_output *resp; 4847 struct hwrm_tunnel_dst_port_alloc_input *req; 4848 int rc; 4849 4850 rc = hwrm_req_init(bp, req, HWRM_TUNNEL_DST_PORT_ALLOC); 4851 if (rc) 4852 return rc; 4853 4854 req->tunnel_type = tunnel_type; 4855 req->tunnel_dst_port_val = port; 4856 4857 resp = hwrm_req_hold(bp, req); 4858 rc = hwrm_req_send(bp, req); 4859 if (rc) { 4860 netdev_err(bp->dev, "hwrm_tunnel_dst_port_alloc failed. rc:%d\n", 4861 rc); 4862 goto err_out; 4863 } 4864 4865 switch (tunnel_type) { 4866 case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN: 4867 bp->vxlan_port = port; 4868 bp->vxlan_fw_dst_port_id = 4869 le16_to_cpu(resp->tunnel_dst_port_id); 4870 break; 4871 case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE: 4872 bp->nge_port = port; 4873 bp->nge_fw_dst_port_id = le16_to_cpu(resp->tunnel_dst_port_id); 4874 break; 4875 default: 4876 break; 4877 } 4878 4879 err_out: 4880 hwrm_req_drop(bp, req); 4881 return rc; 4882 } 4883 4884 static int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp, u16 vnic_id) 4885 { 4886 struct hwrm_cfa_l2_set_rx_mask_input *req; 4887 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 4888 int rc; 4889 4890 rc = hwrm_req_init(bp, req, HWRM_CFA_L2_SET_RX_MASK); 4891 if (rc) 4892 return rc; 4893 4894 req->vnic_id = cpu_to_le32(vnic->fw_vnic_id); 4895 if (vnic->rx_mask & CFA_L2_SET_RX_MASK_REQ_MASK_MCAST) { 4896 req->num_mc_entries = cpu_to_le32(vnic->mc_list_count); 4897 req->mc_tbl_addr = cpu_to_le64(vnic->mc_list_mapping); 4898 } 4899 req->mask = cpu_to_le32(vnic->rx_mask); 4900 return hwrm_req_send_silent(bp, req); 4901 } 4902 4903 #ifdef CONFIG_RFS_ACCEL 4904 static int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt *bp, 4905 struct bnxt_ntuple_filter *fltr) 4906 { 4907 struct hwrm_cfa_ntuple_filter_free_input *req; 4908 int rc; 4909 4910 rc = hwrm_req_init(bp, req, HWRM_CFA_NTUPLE_FILTER_FREE); 4911 if (rc) 4912 return rc; 4913 4914 req->ntuple_filter_id = fltr->filter_id; 4915 return hwrm_req_send(bp, req); 4916 } 4917 4918 #define BNXT_NTP_FLTR_FLAGS \ 4919 (CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID | \ 4920 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE | \ 4921 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR | \ 4922 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE | \ 4923 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR | \ 4924 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK | \ 4925 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR | \ 4926 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK | \ 4927 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL | \ 4928 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT | \ 4929 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK | \ 4930 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT | \ 4931 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK | \ 4932 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID) 4933 4934 #define BNXT_NTP_TUNNEL_FLTR_FLAG \ 4935 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 4936 4937 static int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt *bp, 4938 struct bnxt_ntuple_filter *fltr) 4939 { 4940 struct hwrm_cfa_ntuple_filter_alloc_output *resp; 4941 struct hwrm_cfa_ntuple_filter_alloc_input *req; 4942 struct flow_keys *keys = &fltr->fkeys; 4943 struct bnxt_vnic_info *vnic; 4944 u32 flags = 0; 4945 int rc; 4946 4947 rc = hwrm_req_init(bp, req, HWRM_CFA_NTUPLE_FILTER_ALLOC); 4948 if (rc) 4949 return rc; 4950 4951 req->l2_filter_id = bp->vnic_info[0].fw_l2_filter_id[fltr->l2_fltr_idx]; 4952 4953 if (bp->fw_cap & BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V2) { 4954 flags = CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DEST_RFS_RING_IDX; 4955 req->dst_id = cpu_to_le16(fltr->rxq); 4956 } else { 4957 vnic = &bp->vnic_info[fltr->rxq + 1]; 4958 req->dst_id = cpu_to_le16(vnic->fw_vnic_id); 4959 } 4960 req->flags = cpu_to_le32(flags); 4961 req->enables = cpu_to_le32(BNXT_NTP_FLTR_FLAGS); 4962 4963 req->ethertype = htons(ETH_P_IP); 4964 memcpy(req->src_macaddr, fltr->src_mac_addr, ETH_ALEN); 4965 req->ip_addr_type = CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4; 4966 req->ip_protocol = keys->basic.ip_proto; 4967 4968 if (keys->basic.n_proto == htons(ETH_P_IPV6)) { 4969 int i; 4970 4971 req->ethertype = htons(ETH_P_IPV6); 4972 req->ip_addr_type = 4973 CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6; 4974 *(struct in6_addr *)&req->src_ipaddr[0] = 4975 keys->addrs.v6addrs.src; 4976 *(struct in6_addr *)&req->dst_ipaddr[0] = 4977 keys->addrs.v6addrs.dst; 4978 for (i = 0; i < 4; i++) { 4979 req->src_ipaddr_mask[i] = cpu_to_be32(0xffffffff); 4980 req->dst_ipaddr_mask[i] = cpu_to_be32(0xffffffff); 4981 } 4982 } else { 4983 req->src_ipaddr[0] = keys->addrs.v4addrs.src; 4984 req->src_ipaddr_mask[0] = cpu_to_be32(0xffffffff); 4985 req->dst_ipaddr[0] = keys->addrs.v4addrs.dst; 4986 req->dst_ipaddr_mask[0] = cpu_to_be32(0xffffffff); 4987 } 4988 if (keys->control.flags & FLOW_DIS_ENCAPSULATION) { 4989 req->enables |= cpu_to_le32(BNXT_NTP_TUNNEL_FLTR_FLAG); 4990 req->tunnel_type = 4991 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL; 4992 } 4993 4994 req->src_port = keys->ports.src; 4995 req->src_port_mask = cpu_to_be16(0xffff); 4996 req->dst_port = keys->ports.dst; 4997 req->dst_port_mask = cpu_to_be16(0xffff); 4998 4999 resp = hwrm_req_hold(bp, req); 5000 rc = hwrm_req_send(bp, req); 5001 if (!rc) 5002 fltr->filter_id = resp->ntuple_filter_id; 5003 hwrm_req_drop(bp, req); 5004 return rc; 5005 } 5006 #endif 5007 5008 static int bnxt_hwrm_set_vnic_filter(struct bnxt *bp, u16 vnic_id, u16 idx, 5009 const u8 *mac_addr) 5010 { 5011 struct hwrm_cfa_l2_filter_alloc_output *resp; 5012 struct hwrm_cfa_l2_filter_alloc_input *req; 5013 int rc; 5014 5015 rc = hwrm_req_init(bp, req, HWRM_CFA_L2_FILTER_ALLOC); 5016 if (rc) 5017 return rc; 5018 5019 req->flags = cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX); 5020 if (!BNXT_CHIP_TYPE_NITRO_A0(bp)) 5021 req->flags |= 5022 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST); 5023 req->dst_id = cpu_to_le16(bp->vnic_info[vnic_id].fw_vnic_id); 5024 req->enables = 5025 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR | 5026 CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID | 5027 CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK); 5028 memcpy(req->l2_addr, mac_addr, ETH_ALEN); 5029 req->l2_addr_mask[0] = 0xff; 5030 req->l2_addr_mask[1] = 0xff; 5031 req->l2_addr_mask[2] = 0xff; 5032 req->l2_addr_mask[3] = 0xff; 5033 req->l2_addr_mask[4] = 0xff; 5034 req->l2_addr_mask[5] = 0xff; 5035 5036 resp = hwrm_req_hold(bp, req); 5037 rc = hwrm_req_send(bp, req); 5038 if (!rc) 5039 bp->vnic_info[vnic_id].fw_l2_filter_id[idx] = 5040 resp->l2_filter_id; 5041 hwrm_req_drop(bp, req); 5042 return rc; 5043 } 5044 5045 static int bnxt_hwrm_clear_vnic_filter(struct bnxt *bp) 5046 { 5047 struct hwrm_cfa_l2_filter_free_input *req; 5048 u16 i, j, num_of_vnics = 1; /* only vnic 0 supported */ 5049 int rc; 5050 5051 /* Any associated ntuple filters will also be cleared by firmware. */ 5052 rc = hwrm_req_init(bp, req, HWRM_CFA_L2_FILTER_FREE); 5053 if (rc) 5054 return rc; 5055 hwrm_req_hold(bp, req); 5056 for (i = 0; i < num_of_vnics; i++) { 5057 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 5058 5059 for (j = 0; j < vnic->uc_filter_count; j++) { 5060 req->l2_filter_id = vnic->fw_l2_filter_id[j]; 5061 5062 rc = hwrm_req_send(bp, req); 5063 } 5064 vnic->uc_filter_count = 0; 5065 } 5066 hwrm_req_drop(bp, req); 5067 return rc; 5068 } 5069 5070 static int bnxt_hwrm_vnic_set_tpa(struct bnxt *bp, u16 vnic_id, u32 tpa_flags) 5071 { 5072 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 5073 u16 max_aggs = VNIC_TPA_CFG_REQ_MAX_AGGS_MAX; 5074 struct hwrm_vnic_tpa_cfg_input *req; 5075 int rc; 5076 5077 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) 5078 return 0; 5079 5080 rc = hwrm_req_init(bp, req, HWRM_VNIC_TPA_CFG); 5081 if (rc) 5082 return rc; 5083 5084 if (tpa_flags) { 5085 u16 mss = bp->dev->mtu - 40; 5086 u32 nsegs, n, segs = 0, flags; 5087 5088 flags = VNIC_TPA_CFG_REQ_FLAGS_TPA | 5089 VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA | 5090 VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE | 5091 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN | 5092 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ; 5093 if (tpa_flags & BNXT_FLAG_GRO) 5094 flags |= VNIC_TPA_CFG_REQ_FLAGS_GRO; 5095 5096 req->flags = cpu_to_le32(flags); 5097 5098 req->enables = 5099 cpu_to_le32(VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS | 5100 VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS | 5101 VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN); 5102 5103 /* Number of segs are log2 units, and first packet is not 5104 * included as part of this units. 5105 */ 5106 if (mss <= BNXT_RX_PAGE_SIZE) { 5107 n = BNXT_RX_PAGE_SIZE / mss; 5108 nsegs = (MAX_SKB_FRAGS - 1) * n; 5109 } else { 5110 n = mss / BNXT_RX_PAGE_SIZE; 5111 if (mss & (BNXT_RX_PAGE_SIZE - 1)) 5112 n++; 5113 nsegs = (MAX_SKB_FRAGS - n) / n; 5114 } 5115 5116 if (bp->flags & BNXT_FLAG_CHIP_P5) { 5117 segs = MAX_TPA_SEGS_P5; 5118 max_aggs = bp->max_tpa; 5119 } else { 5120 segs = ilog2(nsegs); 5121 } 5122 req->max_agg_segs = cpu_to_le16(segs); 5123 req->max_aggs = cpu_to_le16(max_aggs); 5124 5125 req->min_agg_len = cpu_to_le32(512); 5126 } 5127 req->vnic_id = cpu_to_le16(vnic->fw_vnic_id); 5128 5129 return hwrm_req_send(bp, req); 5130 } 5131 5132 static u16 bnxt_cp_ring_from_grp(struct bnxt *bp, struct bnxt_ring_struct *ring) 5133 { 5134 struct bnxt_ring_grp_info *grp_info; 5135 5136 grp_info = &bp->grp_info[ring->grp_idx]; 5137 return grp_info->cp_fw_ring_id; 5138 } 5139 5140 static u16 bnxt_cp_ring_for_rx(struct bnxt *bp, struct bnxt_rx_ring_info *rxr) 5141 { 5142 if (bp->flags & BNXT_FLAG_CHIP_P5) { 5143 struct bnxt_napi *bnapi = rxr->bnapi; 5144 struct bnxt_cp_ring_info *cpr; 5145 5146 cpr = bnapi->cp_ring.cp_ring_arr[BNXT_RX_HDL]; 5147 return cpr->cp_ring_struct.fw_ring_id; 5148 } else { 5149 return bnxt_cp_ring_from_grp(bp, &rxr->rx_ring_struct); 5150 } 5151 } 5152 5153 static u16 bnxt_cp_ring_for_tx(struct bnxt *bp, struct bnxt_tx_ring_info *txr) 5154 { 5155 if (bp->flags & BNXT_FLAG_CHIP_P5) { 5156 struct bnxt_napi *bnapi = txr->bnapi; 5157 struct bnxt_cp_ring_info *cpr; 5158 5159 cpr = bnapi->cp_ring.cp_ring_arr[BNXT_TX_HDL]; 5160 return cpr->cp_ring_struct.fw_ring_id; 5161 } else { 5162 return bnxt_cp_ring_from_grp(bp, &txr->tx_ring_struct); 5163 } 5164 } 5165 5166 static int bnxt_alloc_rss_indir_tbl(struct bnxt *bp) 5167 { 5168 int entries; 5169 5170 if (bp->flags & BNXT_FLAG_CHIP_P5) 5171 entries = BNXT_MAX_RSS_TABLE_ENTRIES_P5; 5172 else 5173 entries = HW_HASH_INDEX_SIZE; 5174 5175 bp->rss_indir_tbl_entries = entries; 5176 bp->rss_indir_tbl = kmalloc_array(entries, sizeof(*bp->rss_indir_tbl), 5177 GFP_KERNEL); 5178 if (!bp->rss_indir_tbl) 5179 return -ENOMEM; 5180 return 0; 5181 } 5182 5183 static void bnxt_set_dflt_rss_indir_tbl(struct bnxt *bp) 5184 { 5185 u16 max_rings, max_entries, pad, i; 5186 5187 if (!bp->rx_nr_rings) 5188 return; 5189 5190 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 5191 max_rings = bp->rx_nr_rings - 1; 5192 else 5193 max_rings = bp->rx_nr_rings; 5194 5195 max_entries = bnxt_get_rxfh_indir_size(bp->dev); 5196 5197 for (i = 0; i < max_entries; i++) 5198 bp->rss_indir_tbl[i] = ethtool_rxfh_indir_default(i, max_rings); 5199 5200 pad = bp->rss_indir_tbl_entries - max_entries; 5201 if (pad) 5202 memset(&bp->rss_indir_tbl[i], 0, pad * sizeof(u16)); 5203 } 5204 5205 static u16 bnxt_get_max_rss_ring(struct bnxt *bp) 5206 { 5207 u16 i, tbl_size, max_ring = 0; 5208 5209 if (!bp->rss_indir_tbl) 5210 return 0; 5211 5212 tbl_size = bnxt_get_rxfh_indir_size(bp->dev); 5213 for (i = 0; i < tbl_size; i++) 5214 max_ring = max(max_ring, bp->rss_indir_tbl[i]); 5215 return max_ring; 5216 } 5217 5218 int bnxt_get_nr_rss_ctxs(struct bnxt *bp, int rx_rings) 5219 { 5220 if (bp->flags & BNXT_FLAG_CHIP_P5) 5221 return DIV_ROUND_UP(rx_rings, BNXT_RSS_TABLE_ENTRIES_P5); 5222 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 5223 return 2; 5224 return 1; 5225 } 5226 5227 static void bnxt_fill_hw_rss_tbl(struct bnxt *bp, struct bnxt_vnic_info *vnic) 5228 { 5229 bool no_rss = !(vnic->flags & BNXT_VNIC_RSS_FLAG); 5230 u16 i, j; 5231 5232 /* Fill the RSS indirection table with ring group ids */ 5233 for (i = 0, j = 0; i < HW_HASH_INDEX_SIZE; i++) { 5234 if (!no_rss) 5235 j = bp->rss_indir_tbl[i]; 5236 vnic->rss_table[i] = cpu_to_le16(vnic->fw_grp_ids[j]); 5237 } 5238 } 5239 5240 static void bnxt_fill_hw_rss_tbl_p5(struct bnxt *bp, 5241 struct bnxt_vnic_info *vnic) 5242 { 5243 __le16 *ring_tbl = vnic->rss_table; 5244 struct bnxt_rx_ring_info *rxr; 5245 u16 tbl_size, i; 5246 5247 tbl_size = bnxt_get_rxfh_indir_size(bp->dev); 5248 5249 for (i = 0; i < tbl_size; i++) { 5250 u16 ring_id, j; 5251 5252 j = bp->rss_indir_tbl[i]; 5253 rxr = &bp->rx_ring[j]; 5254 5255 ring_id = rxr->rx_ring_struct.fw_ring_id; 5256 *ring_tbl++ = cpu_to_le16(ring_id); 5257 ring_id = bnxt_cp_ring_for_rx(bp, rxr); 5258 *ring_tbl++ = cpu_to_le16(ring_id); 5259 } 5260 } 5261 5262 static void 5263 __bnxt_hwrm_vnic_set_rss(struct bnxt *bp, struct hwrm_vnic_rss_cfg_input *req, 5264 struct bnxt_vnic_info *vnic) 5265 { 5266 if (bp->flags & BNXT_FLAG_CHIP_P5) 5267 bnxt_fill_hw_rss_tbl_p5(bp, vnic); 5268 else 5269 bnxt_fill_hw_rss_tbl(bp, vnic); 5270 5271 if (bp->rss_hash_delta) { 5272 req->hash_type = cpu_to_le32(bp->rss_hash_delta); 5273 if (bp->rss_hash_cfg & bp->rss_hash_delta) 5274 req->flags |= VNIC_RSS_CFG_REQ_FLAGS_HASH_TYPE_INCLUDE; 5275 else 5276 req->flags |= VNIC_RSS_CFG_REQ_FLAGS_HASH_TYPE_EXCLUDE; 5277 } else { 5278 req->hash_type = cpu_to_le32(bp->rss_hash_cfg); 5279 } 5280 req->hash_mode_flags = VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT; 5281 req->ring_grp_tbl_addr = cpu_to_le64(vnic->rss_table_dma_addr); 5282 req->hash_key_tbl_addr = cpu_to_le64(vnic->rss_hash_key_dma_addr); 5283 } 5284 5285 static int bnxt_hwrm_vnic_set_rss(struct bnxt *bp, u16 vnic_id, bool set_rss) 5286 { 5287 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 5288 struct hwrm_vnic_rss_cfg_input *req; 5289 int rc; 5290 5291 if ((bp->flags & BNXT_FLAG_CHIP_P5) || 5292 vnic->fw_rss_cos_lb_ctx[0] == INVALID_HW_RING_ID) 5293 return 0; 5294 5295 rc = hwrm_req_init(bp, req, HWRM_VNIC_RSS_CFG); 5296 if (rc) 5297 return rc; 5298 5299 if (set_rss) 5300 __bnxt_hwrm_vnic_set_rss(bp, req, vnic); 5301 req->rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]); 5302 return hwrm_req_send(bp, req); 5303 } 5304 5305 static int bnxt_hwrm_vnic_set_rss_p5(struct bnxt *bp, u16 vnic_id, bool set_rss) 5306 { 5307 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 5308 struct hwrm_vnic_rss_cfg_input *req; 5309 dma_addr_t ring_tbl_map; 5310 u32 i, nr_ctxs; 5311 int rc; 5312 5313 rc = hwrm_req_init(bp, req, HWRM_VNIC_RSS_CFG); 5314 if (rc) 5315 return rc; 5316 5317 req->vnic_id = cpu_to_le16(vnic->fw_vnic_id); 5318 if (!set_rss) 5319 return hwrm_req_send(bp, req); 5320 5321 __bnxt_hwrm_vnic_set_rss(bp, req, vnic); 5322 ring_tbl_map = vnic->rss_table_dma_addr; 5323 nr_ctxs = bnxt_get_nr_rss_ctxs(bp, bp->rx_nr_rings); 5324 5325 hwrm_req_hold(bp, req); 5326 for (i = 0; i < nr_ctxs; ring_tbl_map += BNXT_RSS_TABLE_SIZE_P5, i++) { 5327 req->ring_grp_tbl_addr = cpu_to_le64(ring_tbl_map); 5328 req->ring_table_pair_index = i; 5329 req->rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[i]); 5330 rc = hwrm_req_send(bp, req); 5331 if (rc) 5332 goto exit; 5333 } 5334 5335 exit: 5336 hwrm_req_drop(bp, req); 5337 return rc; 5338 } 5339 5340 static void bnxt_hwrm_update_rss_hash_cfg(struct bnxt *bp) 5341 { 5342 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 5343 struct hwrm_vnic_rss_qcfg_output *resp; 5344 struct hwrm_vnic_rss_qcfg_input *req; 5345 5346 if (hwrm_req_init(bp, req, HWRM_VNIC_RSS_QCFG)) 5347 return; 5348 5349 /* all contexts configured to same hash_type, zero always exists */ 5350 req->rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]); 5351 resp = hwrm_req_hold(bp, req); 5352 if (!hwrm_req_send(bp, req)) { 5353 bp->rss_hash_cfg = le32_to_cpu(resp->hash_type) ?: bp->rss_hash_cfg; 5354 bp->rss_hash_delta = 0; 5355 } 5356 hwrm_req_drop(bp, req); 5357 } 5358 5359 static int bnxt_hwrm_vnic_set_hds(struct bnxt *bp, u16 vnic_id) 5360 { 5361 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 5362 struct hwrm_vnic_plcmodes_cfg_input *req; 5363 int rc; 5364 5365 rc = hwrm_req_init(bp, req, HWRM_VNIC_PLCMODES_CFG); 5366 if (rc) 5367 return rc; 5368 5369 req->flags = cpu_to_le32(VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT); 5370 req->enables = cpu_to_le32(VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID); 5371 5372 if (BNXT_RX_PAGE_MODE(bp)) { 5373 req->jumbo_thresh = cpu_to_le16(bp->rx_buf_use_size); 5374 } else { 5375 req->flags |= cpu_to_le32(VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 | 5376 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6); 5377 req->enables |= 5378 cpu_to_le32(VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID); 5379 req->jumbo_thresh = cpu_to_le16(bp->rx_copy_thresh); 5380 req->hds_threshold = cpu_to_le16(bp->rx_copy_thresh); 5381 } 5382 req->vnic_id = cpu_to_le32(vnic->fw_vnic_id); 5383 return hwrm_req_send(bp, req); 5384 } 5385 5386 static void bnxt_hwrm_vnic_ctx_free_one(struct bnxt *bp, u16 vnic_id, 5387 u16 ctx_idx) 5388 { 5389 struct hwrm_vnic_rss_cos_lb_ctx_free_input *req; 5390 5391 if (hwrm_req_init(bp, req, HWRM_VNIC_RSS_COS_LB_CTX_FREE)) 5392 return; 5393 5394 req->rss_cos_lb_ctx_id = 5395 cpu_to_le16(bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx]); 5396 5397 hwrm_req_send(bp, req); 5398 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] = INVALID_HW_RING_ID; 5399 } 5400 5401 static void bnxt_hwrm_vnic_ctx_free(struct bnxt *bp) 5402 { 5403 int i, j; 5404 5405 for (i = 0; i < bp->nr_vnics; i++) { 5406 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 5407 5408 for (j = 0; j < BNXT_MAX_CTX_PER_VNIC; j++) { 5409 if (vnic->fw_rss_cos_lb_ctx[j] != INVALID_HW_RING_ID) 5410 bnxt_hwrm_vnic_ctx_free_one(bp, i, j); 5411 } 5412 } 5413 bp->rsscos_nr_ctxs = 0; 5414 } 5415 5416 static int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, u16 vnic_id, u16 ctx_idx) 5417 { 5418 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp; 5419 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input *req; 5420 int rc; 5421 5422 rc = hwrm_req_init(bp, req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC); 5423 if (rc) 5424 return rc; 5425 5426 resp = hwrm_req_hold(bp, req); 5427 rc = hwrm_req_send(bp, req); 5428 if (!rc) 5429 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] = 5430 le16_to_cpu(resp->rss_cos_lb_ctx_id); 5431 hwrm_req_drop(bp, req); 5432 5433 return rc; 5434 } 5435 5436 static u32 bnxt_get_roce_vnic_mode(struct bnxt *bp) 5437 { 5438 if (bp->flags & BNXT_FLAG_ROCE_MIRROR_CAP) 5439 return VNIC_CFG_REQ_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE; 5440 return VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE; 5441 } 5442 5443 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id) 5444 { 5445 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 5446 struct hwrm_vnic_cfg_input *req; 5447 unsigned int ring = 0, grp_idx; 5448 u16 def_vlan = 0; 5449 int rc; 5450 5451 rc = hwrm_req_init(bp, req, HWRM_VNIC_CFG); 5452 if (rc) 5453 return rc; 5454 5455 if (bp->flags & BNXT_FLAG_CHIP_P5) { 5456 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[0]; 5457 5458 req->default_rx_ring_id = 5459 cpu_to_le16(rxr->rx_ring_struct.fw_ring_id); 5460 req->default_cmpl_ring_id = 5461 cpu_to_le16(bnxt_cp_ring_for_rx(bp, rxr)); 5462 req->enables = 5463 cpu_to_le32(VNIC_CFG_REQ_ENABLES_DEFAULT_RX_RING_ID | 5464 VNIC_CFG_REQ_ENABLES_DEFAULT_CMPL_RING_ID); 5465 goto vnic_mru; 5466 } 5467 req->enables = cpu_to_le32(VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP); 5468 /* Only RSS support for now TBD: COS & LB */ 5469 if (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID) { 5470 req->rss_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]); 5471 req->enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE | 5472 VNIC_CFG_REQ_ENABLES_MRU); 5473 } else if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG) { 5474 req->rss_rule = 5475 cpu_to_le16(bp->vnic_info[0].fw_rss_cos_lb_ctx[0]); 5476 req->enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE | 5477 VNIC_CFG_REQ_ENABLES_MRU); 5478 req->flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE); 5479 } else { 5480 req->rss_rule = cpu_to_le16(0xffff); 5481 } 5482 5483 if (BNXT_CHIP_TYPE_NITRO_A0(bp) && 5484 (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID)) { 5485 req->cos_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[1]); 5486 req->enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_COS_RULE); 5487 } else { 5488 req->cos_rule = cpu_to_le16(0xffff); 5489 } 5490 5491 if (vnic->flags & BNXT_VNIC_RSS_FLAG) 5492 ring = 0; 5493 else if (vnic->flags & BNXT_VNIC_RFS_FLAG) 5494 ring = vnic_id - 1; 5495 else if ((vnic_id == 1) && BNXT_CHIP_TYPE_NITRO_A0(bp)) 5496 ring = bp->rx_nr_rings - 1; 5497 5498 grp_idx = bp->rx_ring[ring].bnapi->index; 5499 req->dflt_ring_grp = cpu_to_le16(bp->grp_info[grp_idx].fw_grp_id); 5500 req->lb_rule = cpu_to_le16(0xffff); 5501 vnic_mru: 5502 req->mru = cpu_to_le16(bp->dev->mtu + ETH_HLEN + VLAN_HLEN); 5503 5504 req->vnic_id = cpu_to_le16(vnic->fw_vnic_id); 5505 #ifdef CONFIG_BNXT_SRIOV 5506 if (BNXT_VF(bp)) 5507 def_vlan = bp->vf.vlan; 5508 #endif 5509 if ((bp->flags & BNXT_FLAG_STRIP_VLAN) || def_vlan) 5510 req->flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE); 5511 if (!vnic_id && bnxt_ulp_registered(bp->edev)) 5512 req->flags |= cpu_to_le32(bnxt_get_roce_vnic_mode(bp)); 5513 5514 return hwrm_req_send(bp, req); 5515 } 5516 5517 static void bnxt_hwrm_vnic_free_one(struct bnxt *bp, u16 vnic_id) 5518 { 5519 if (bp->vnic_info[vnic_id].fw_vnic_id != INVALID_HW_RING_ID) { 5520 struct hwrm_vnic_free_input *req; 5521 5522 if (hwrm_req_init(bp, req, HWRM_VNIC_FREE)) 5523 return; 5524 5525 req->vnic_id = 5526 cpu_to_le32(bp->vnic_info[vnic_id].fw_vnic_id); 5527 5528 hwrm_req_send(bp, req); 5529 bp->vnic_info[vnic_id].fw_vnic_id = INVALID_HW_RING_ID; 5530 } 5531 } 5532 5533 static void bnxt_hwrm_vnic_free(struct bnxt *bp) 5534 { 5535 u16 i; 5536 5537 for (i = 0; i < bp->nr_vnics; i++) 5538 bnxt_hwrm_vnic_free_one(bp, i); 5539 } 5540 5541 static int bnxt_hwrm_vnic_alloc(struct bnxt *bp, u16 vnic_id, 5542 unsigned int start_rx_ring_idx, 5543 unsigned int nr_rings) 5544 { 5545 unsigned int i, j, grp_idx, end_idx = start_rx_ring_idx + nr_rings; 5546 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 5547 struct hwrm_vnic_alloc_output *resp; 5548 struct hwrm_vnic_alloc_input *req; 5549 int rc; 5550 5551 rc = hwrm_req_init(bp, req, HWRM_VNIC_ALLOC); 5552 if (rc) 5553 return rc; 5554 5555 if (bp->flags & BNXT_FLAG_CHIP_P5) 5556 goto vnic_no_ring_grps; 5557 5558 /* map ring groups to this vnic */ 5559 for (i = start_rx_ring_idx, j = 0; i < end_idx; i++, j++) { 5560 grp_idx = bp->rx_ring[i].bnapi->index; 5561 if (bp->grp_info[grp_idx].fw_grp_id == INVALID_HW_RING_ID) { 5562 netdev_err(bp->dev, "Not enough ring groups avail:%x req:%x\n", 5563 j, nr_rings); 5564 break; 5565 } 5566 vnic->fw_grp_ids[j] = bp->grp_info[grp_idx].fw_grp_id; 5567 } 5568 5569 vnic_no_ring_grps: 5570 for (i = 0; i < BNXT_MAX_CTX_PER_VNIC; i++) 5571 vnic->fw_rss_cos_lb_ctx[i] = INVALID_HW_RING_ID; 5572 if (vnic_id == 0) 5573 req->flags = cpu_to_le32(VNIC_ALLOC_REQ_FLAGS_DEFAULT); 5574 5575 resp = hwrm_req_hold(bp, req); 5576 rc = hwrm_req_send(bp, req); 5577 if (!rc) 5578 vnic->fw_vnic_id = le32_to_cpu(resp->vnic_id); 5579 hwrm_req_drop(bp, req); 5580 return rc; 5581 } 5582 5583 static int bnxt_hwrm_vnic_qcaps(struct bnxt *bp) 5584 { 5585 struct hwrm_vnic_qcaps_output *resp; 5586 struct hwrm_vnic_qcaps_input *req; 5587 int rc; 5588 5589 bp->hw_ring_stats_size = sizeof(struct ctx_hw_stats); 5590 bp->flags &= ~(BNXT_FLAG_NEW_RSS_CAP | BNXT_FLAG_ROCE_MIRROR_CAP); 5591 if (bp->hwrm_spec_code < 0x10600) 5592 return 0; 5593 5594 rc = hwrm_req_init(bp, req, HWRM_VNIC_QCAPS); 5595 if (rc) 5596 return rc; 5597 5598 resp = hwrm_req_hold(bp, req); 5599 rc = hwrm_req_send(bp, req); 5600 if (!rc) { 5601 u32 flags = le32_to_cpu(resp->flags); 5602 5603 if (!(bp->flags & BNXT_FLAG_CHIP_P5) && 5604 (flags & VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP)) 5605 bp->flags |= BNXT_FLAG_NEW_RSS_CAP; 5606 if (flags & 5607 VNIC_QCAPS_RESP_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP) 5608 bp->flags |= BNXT_FLAG_ROCE_MIRROR_CAP; 5609 5610 /* Older P5 fw before EXT_HW_STATS support did not set 5611 * VLAN_STRIP_CAP properly. 5612 */ 5613 if ((flags & VNIC_QCAPS_RESP_FLAGS_VLAN_STRIP_CAP) || 5614 (BNXT_CHIP_P5_THOR(bp) && 5615 !(bp->fw_cap & BNXT_FW_CAP_EXT_HW_STATS_SUPPORTED))) 5616 bp->fw_cap |= BNXT_FW_CAP_VLAN_RX_STRIP; 5617 if (flags & VNIC_QCAPS_RESP_FLAGS_RSS_HASH_TYPE_DELTA_CAP) 5618 bp->fw_cap |= BNXT_FW_CAP_RSS_HASH_TYPE_DELTA; 5619 bp->max_tpa_v2 = le16_to_cpu(resp->max_aggs_supported); 5620 if (bp->max_tpa_v2) { 5621 if (BNXT_CHIP_P5_THOR(bp)) 5622 bp->hw_ring_stats_size = BNXT_RING_STATS_SIZE_P5; 5623 else 5624 bp->hw_ring_stats_size = BNXT_RING_STATS_SIZE_P5_SR2; 5625 } 5626 } 5627 hwrm_req_drop(bp, req); 5628 return rc; 5629 } 5630 5631 static int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp) 5632 { 5633 struct hwrm_ring_grp_alloc_output *resp; 5634 struct hwrm_ring_grp_alloc_input *req; 5635 int rc; 5636 u16 i; 5637 5638 if (bp->flags & BNXT_FLAG_CHIP_P5) 5639 return 0; 5640 5641 rc = hwrm_req_init(bp, req, HWRM_RING_GRP_ALLOC); 5642 if (rc) 5643 return rc; 5644 5645 resp = hwrm_req_hold(bp, req); 5646 for (i = 0; i < bp->rx_nr_rings; i++) { 5647 unsigned int grp_idx = bp->rx_ring[i].bnapi->index; 5648 5649 req->cr = cpu_to_le16(bp->grp_info[grp_idx].cp_fw_ring_id); 5650 req->rr = cpu_to_le16(bp->grp_info[grp_idx].rx_fw_ring_id); 5651 req->ar = cpu_to_le16(bp->grp_info[grp_idx].agg_fw_ring_id); 5652 req->sc = cpu_to_le16(bp->grp_info[grp_idx].fw_stats_ctx); 5653 5654 rc = hwrm_req_send(bp, req); 5655 5656 if (rc) 5657 break; 5658 5659 bp->grp_info[grp_idx].fw_grp_id = 5660 le32_to_cpu(resp->ring_group_id); 5661 } 5662 hwrm_req_drop(bp, req); 5663 return rc; 5664 } 5665 5666 static void bnxt_hwrm_ring_grp_free(struct bnxt *bp) 5667 { 5668 struct hwrm_ring_grp_free_input *req; 5669 u16 i; 5670 5671 if (!bp->grp_info || (bp->flags & BNXT_FLAG_CHIP_P5)) 5672 return; 5673 5674 if (hwrm_req_init(bp, req, HWRM_RING_GRP_FREE)) 5675 return; 5676 5677 hwrm_req_hold(bp, req); 5678 for (i = 0; i < bp->cp_nr_rings; i++) { 5679 if (bp->grp_info[i].fw_grp_id == INVALID_HW_RING_ID) 5680 continue; 5681 req->ring_group_id = 5682 cpu_to_le32(bp->grp_info[i].fw_grp_id); 5683 5684 hwrm_req_send(bp, req); 5685 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID; 5686 } 5687 hwrm_req_drop(bp, req); 5688 } 5689 5690 static int hwrm_ring_alloc_send_msg(struct bnxt *bp, 5691 struct bnxt_ring_struct *ring, 5692 u32 ring_type, u32 map_index) 5693 { 5694 struct hwrm_ring_alloc_output *resp; 5695 struct hwrm_ring_alloc_input *req; 5696 struct bnxt_ring_mem_info *rmem = &ring->ring_mem; 5697 struct bnxt_ring_grp_info *grp_info; 5698 int rc, err = 0; 5699 u16 ring_id; 5700 5701 rc = hwrm_req_init(bp, req, HWRM_RING_ALLOC); 5702 if (rc) 5703 goto exit; 5704 5705 req->enables = 0; 5706 if (rmem->nr_pages > 1) { 5707 req->page_tbl_addr = cpu_to_le64(rmem->pg_tbl_map); 5708 /* Page size is in log2 units */ 5709 req->page_size = BNXT_PAGE_SHIFT; 5710 req->page_tbl_depth = 1; 5711 } else { 5712 req->page_tbl_addr = cpu_to_le64(rmem->dma_arr[0]); 5713 } 5714 req->fbo = 0; 5715 /* Association of ring index with doorbell index and MSIX number */ 5716 req->logical_id = cpu_to_le16(map_index); 5717 5718 switch (ring_type) { 5719 case HWRM_RING_ALLOC_TX: { 5720 struct bnxt_tx_ring_info *txr; 5721 5722 txr = container_of(ring, struct bnxt_tx_ring_info, 5723 tx_ring_struct); 5724 req->ring_type = RING_ALLOC_REQ_RING_TYPE_TX; 5725 /* Association of transmit ring with completion ring */ 5726 grp_info = &bp->grp_info[ring->grp_idx]; 5727 req->cmpl_ring_id = cpu_to_le16(bnxt_cp_ring_for_tx(bp, txr)); 5728 req->length = cpu_to_le32(bp->tx_ring_mask + 1); 5729 req->stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx); 5730 req->queue_id = cpu_to_le16(ring->queue_id); 5731 break; 5732 } 5733 case HWRM_RING_ALLOC_RX: 5734 req->ring_type = RING_ALLOC_REQ_RING_TYPE_RX; 5735 req->length = cpu_to_le32(bp->rx_ring_mask + 1); 5736 if (bp->flags & BNXT_FLAG_CHIP_P5) { 5737 u16 flags = 0; 5738 5739 /* Association of rx ring with stats context */ 5740 grp_info = &bp->grp_info[ring->grp_idx]; 5741 req->rx_buf_size = cpu_to_le16(bp->rx_buf_use_size); 5742 req->stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx); 5743 req->enables |= cpu_to_le32( 5744 RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID); 5745 if (NET_IP_ALIGN == 2) 5746 flags = RING_ALLOC_REQ_FLAGS_RX_SOP_PAD; 5747 req->flags = cpu_to_le16(flags); 5748 } 5749 break; 5750 case HWRM_RING_ALLOC_AGG: 5751 if (bp->flags & BNXT_FLAG_CHIP_P5) { 5752 req->ring_type = RING_ALLOC_REQ_RING_TYPE_RX_AGG; 5753 /* Association of agg ring with rx ring */ 5754 grp_info = &bp->grp_info[ring->grp_idx]; 5755 req->rx_ring_id = cpu_to_le16(grp_info->rx_fw_ring_id); 5756 req->rx_buf_size = cpu_to_le16(BNXT_RX_PAGE_SIZE); 5757 req->stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx); 5758 req->enables |= cpu_to_le32( 5759 RING_ALLOC_REQ_ENABLES_RX_RING_ID_VALID | 5760 RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID); 5761 } else { 5762 req->ring_type = RING_ALLOC_REQ_RING_TYPE_RX; 5763 } 5764 req->length = cpu_to_le32(bp->rx_agg_ring_mask + 1); 5765 break; 5766 case HWRM_RING_ALLOC_CMPL: 5767 req->ring_type = RING_ALLOC_REQ_RING_TYPE_L2_CMPL; 5768 req->length = cpu_to_le32(bp->cp_ring_mask + 1); 5769 if (bp->flags & BNXT_FLAG_CHIP_P5) { 5770 /* Association of cp ring with nq */ 5771 grp_info = &bp->grp_info[map_index]; 5772 req->nq_ring_id = cpu_to_le16(grp_info->cp_fw_ring_id); 5773 req->cq_handle = cpu_to_le64(ring->handle); 5774 req->enables |= cpu_to_le32( 5775 RING_ALLOC_REQ_ENABLES_NQ_RING_ID_VALID); 5776 } else if (bp->flags & BNXT_FLAG_USING_MSIX) { 5777 req->int_mode = RING_ALLOC_REQ_INT_MODE_MSIX; 5778 } 5779 break; 5780 case HWRM_RING_ALLOC_NQ: 5781 req->ring_type = RING_ALLOC_REQ_RING_TYPE_NQ; 5782 req->length = cpu_to_le32(bp->cp_ring_mask + 1); 5783 if (bp->flags & BNXT_FLAG_USING_MSIX) 5784 req->int_mode = RING_ALLOC_REQ_INT_MODE_MSIX; 5785 break; 5786 default: 5787 netdev_err(bp->dev, "hwrm alloc invalid ring type %d\n", 5788 ring_type); 5789 return -1; 5790 } 5791 5792 resp = hwrm_req_hold(bp, req); 5793 rc = hwrm_req_send(bp, req); 5794 err = le16_to_cpu(resp->error_code); 5795 ring_id = le16_to_cpu(resp->ring_id); 5796 hwrm_req_drop(bp, req); 5797 5798 exit: 5799 if (rc || err) { 5800 netdev_err(bp->dev, "hwrm_ring_alloc type %d failed. rc:%x err:%x\n", 5801 ring_type, rc, err); 5802 return -EIO; 5803 } 5804 ring->fw_ring_id = ring_id; 5805 return rc; 5806 } 5807 5808 static int bnxt_hwrm_set_async_event_cr(struct bnxt *bp, int idx) 5809 { 5810 int rc; 5811 5812 if (BNXT_PF(bp)) { 5813 struct hwrm_func_cfg_input *req; 5814 5815 rc = hwrm_req_init(bp, req, HWRM_FUNC_CFG); 5816 if (rc) 5817 return rc; 5818 5819 req->fid = cpu_to_le16(0xffff); 5820 req->enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR); 5821 req->async_event_cr = cpu_to_le16(idx); 5822 return hwrm_req_send(bp, req); 5823 } else { 5824 struct hwrm_func_vf_cfg_input *req; 5825 5826 rc = hwrm_req_init(bp, req, HWRM_FUNC_VF_CFG); 5827 if (rc) 5828 return rc; 5829 5830 req->enables = 5831 cpu_to_le32(FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR); 5832 req->async_event_cr = cpu_to_le16(idx); 5833 return hwrm_req_send(bp, req); 5834 } 5835 } 5836 5837 static void bnxt_set_db(struct bnxt *bp, struct bnxt_db_info *db, u32 ring_type, 5838 u32 map_idx, u32 xid) 5839 { 5840 if (bp->flags & BNXT_FLAG_CHIP_P5) { 5841 if (BNXT_PF(bp)) 5842 db->doorbell = bp->bar1 + DB_PF_OFFSET_P5; 5843 else 5844 db->doorbell = bp->bar1 + DB_VF_OFFSET_P5; 5845 switch (ring_type) { 5846 case HWRM_RING_ALLOC_TX: 5847 db->db_key64 = DBR_PATH_L2 | DBR_TYPE_SQ; 5848 break; 5849 case HWRM_RING_ALLOC_RX: 5850 case HWRM_RING_ALLOC_AGG: 5851 db->db_key64 = DBR_PATH_L2 | DBR_TYPE_SRQ; 5852 break; 5853 case HWRM_RING_ALLOC_CMPL: 5854 db->db_key64 = DBR_PATH_L2; 5855 break; 5856 case HWRM_RING_ALLOC_NQ: 5857 db->db_key64 = DBR_PATH_L2; 5858 break; 5859 } 5860 db->db_key64 |= (u64)xid << DBR_XID_SFT; 5861 } else { 5862 db->doorbell = bp->bar1 + map_idx * 0x80; 5863 switch (ring_type) { 5864 case HWRM_RING_ALLOC_TX: 5865 db->db_key32 = DB_KEY_TX; 5866 break; 5867 case HWRM_RING_ALLOC_RX: 5868 case HWRM_RING_ALLOC_AGG: 5869 db->db_key32 = DB_KEY_RX; 5870 break; 5871 case HWRM_RING_ALLOC_CMPL: 5872 db->db_key32 = DB_KEY_CP; 5873 break; 5874 } 5875 } 5876 } 5877 5878 static int bnxt_hwrm_ring_alloc(struct bnxt *bp) 5879 { 5880 bool agg_rings = !!(bp->flags & BNXT_FLAG_AGG_RINGS); 5881 int i, rc = 0; 5882 u32 type; 5883 5884 if (bp->flags & BNXT_FLAG_CHIP_P5) 5885 type = HWRM_RING_ALLOC_NQ; 5886 else 5887 type = HWRM_RING_ALLOC_CMPL; 5888 for (i = 0; i < bp->cp_nr_rings; i++) { 5889 struct bnxt_napi *bnapi = bp->bnapi[i]; 5890 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 5891 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct; 5892 u32 map_idx = ring->map_idx; 5893 unsigned int vector; 5894 5895 vector = bp->irq_tbl[map_idx].vector; 5896 disable_irq_nosync(vector); 5897 rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx); 5898 if (rc) { 5899 enable_irq(vector); 5900 goto err_out; 5901 } 5902 bnxt_set_db(bp, &cpr->cp_db, type, map_idx, ring->fw_ring_id); 5903 bnxt_db_nq(bp, &cpr->cp_db, cpr->cp_raw_cons); 5904 enable_irq(vector); 5905 bp->grp_info[i].cp_fw_ring_id = ring->fw_ring_id; 5906 5907 if (!i) { 5908 rc = bnxt_hwrm_set_async_event_cr(bp, ring->fw_ring_id); 5909 if (rc) 5910 netdev_warn(bp->dev, "Failed to set async event completion ring.\n"); 5911 } 5912 } 5913 5914 type = HWRM_RING_ALLOC_TX; 5915 for (i = 0; i < bp->tx_nr_rings; i++) { 5916 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; 5917 struct bnxt_ring_struct *ring; 5918 u32 map_idx; 5919 5920 if (bp->flags & BNXT_FLAG_CHIP_P5) { 5921 struct bnxt_napi *bnapi = txr->bnapi; 5922 struct bnxt_cp_ring_info *cpr, *cpr2; 5923 u32 type2 = HWRM_RING_ALLOC_CMPL; 5924 5925 cpr = &bnapi->cp_ring; 5926 cpr2 = cpr->cp_ring_arr[BNXT_TX_HDL]; 5927 ring = &cpr2->cp_ring_struct; 5928 ring->handle = BNXT_TX_HDL; 5929 map_idx = bnapi->index; 5930 rc = hwrm_ring_alloc_send_msg(bp, ring, type2, map_idx); 5931 if (rc) 5932 goto err_out; 5933 bnxt_set_db(bp, &cpr2->cp_db, type2, map_idx, 5934 ring->fw_ring_id); 5935 bnxt_db_cq(bp, &cpr2->cp_db, cpr2->cp_raw_cons); 5936 } 5937 ring = &txr->tx_ring_struct; 5938 map_idx = i; 5939 rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx); 5940 if (rc) 5941 goto err_out; 5942 bnxt_set_db(bp, &txr->tx_db, type, map_idx, ring->fw_ring_id); 5943 } 5944 5945 type = HWRM_RING_ALLOC_RX; 5946 for (i = 0; i < bp->rx_nr_rings; i++) { 5947 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 5948 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct; 5949 struct bnxt_napi *bnapi = rxr->bnapi; 5950 u32 map_idx = bnapi->index; 5951 5952 rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx); 5953 if (rc) 5954 goto err_out; 5955 bnxt_set_db(bp, &rxr->rx_db, type, map_idx, ring->fw_ring_id); 5956 /* If we have agg rings, post agg buffers first. */ 5957 if (!agg_rings) 5958 bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod); 5959 bp->grp_info[map_idx].rx_fw_ring_id = ring->fw_ring_id; 5960 if (bp->flags & BNXT_FLAG_CHIP_P5) { 5961 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 5962 u32 type2 = HWRM_RING_ALLOC_CMPL; 5963 struct bnxt_cp_ring_info *cpr2; 5964 5965 cpr2 = cpr->cp_ring_arr[BNXT_RX_HDL]; 5966 ring = &cpr2->cp_ring_struct; 5967 ring->handle = BNXT_RX_HDL; 5968 rc = hwrm_ring_alloc_send_msg(bp, ring, type2, map_idx); 5969 if (rc) 5970 goto err_out; 5971 bnxt_set_db(bp, &cpr2->cp_db, type2, map_idx, 5972 ring->fw_ring_id); 5973 bnxt_db_cq(bp, &cpr2->cp_db, cpr2->cp_raw_cons); 5974 } 5975 } 5976 5977 if (agg_rings) { 5978 type = HWRM_RING_ALLOC_AGG; 5979 for (i = 0; i < bp->rx_nr_rings; i++) { 5980 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 5981 struct bnxt_ring_struct *ring = 5982 &rxr->rx_agg_ring_struct; 5983 u32 grp_idx = ring->grp_idx; 5984 u32 map_idx = grp_idx + bp->rx_nr_rings; 5985 5986 rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx); 5987 if (rc) 5988 goto err_out; 5989 5990 bnxt_set_db(bp, &rxr->rx_agg_db, type, map_idx, 5991 ring->fw_ring_id); 5992 bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod); 5993 bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod); 5994 bp->grp_info[grp_idx].agg_fw_ring_id = ring->fw_ring_id; 5995 } 5996 } 5997 err_out: 5998 return rc; 5999 } 6000 6001 static int hwrm_ring_free_send_msg(struct bnxt *bp, 6002 struct bnxt_ring_struct *ring, 6003 u32 ring_type, int cmpl_ring_id) 6004 { 6005 struct hwrm_ring_free_output *resp; 6006 struct hwrm_ring_free_input *req; 6007 u16 error_code = 0; 6008 int rc; 6009 6010 if (BNXT_NO_FW_ACCESS(bp)) 6011 return 0; 6012 6013 rc = hwrm_req_init(bp, req, HWRM_RING_FREE); 6014 if (rc) 6015 goto exit; 6016 6017 req->cmpl_ring = cpu_to_le16(cmpl_ring_id); 6018 req->ring_type = ring_type; 6019 req->ring_id = cpu_to_le16(ring->fw_ring_id); 6020 6021 resp = hwrm_req_hold(bp, req); 6022 rc = hwrm_req_send(bp, req); 6023 error_code = le16_to_cpu(resp->error_code); 6024 hwrm_req_drop(bp, req); 6025 exit: 6026 if (rc || error_code) { 6027 netdev_err(bp->dev, "hwrm_ring_free type %d failed. rc:%x err:%x\n", 6028 ring_type, rc, error_code); 6029 return -EIO; 6030 } 6031 return 0; 6032 } 6033 6034 static void bnxt_hwrm_ring_free(struct bnxt *bp, bool close_path) 6035 { 6036 u32 type; 6037 int i; 6038 6039 if (!bp->bnapi) 6040 return; 6041 6042 for (i = 0; i < bp->tx_nr_rings; i++) { 6043 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; 6044 struct bnxt_ring_struct *ring = &txr->tx_ring_struct; 6045 6046 if (ring->fw_ring_id != INVALID_HW_RING_ID) { 6047 u32 cmpl_ring_id = bnxt_cp_ring_for_tx(bp, txr); 6048 6049 hwrm_ring_free_send_msg(bp, ring, 6050 RING_FREE_REQ_RING_TYPE_TX, 6051 close_path ? cmpl_ring_id : 6052 INVALID_HW_RING_ID); 6053 ring->fw_ring_id = INVALID_HW_RING_ID; 6054 } 6055 } 6056 6057 for (i = 0; i < bp->rx_nr_rings; i++) { 6058 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 6059 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct; 6060 u32 grp_idx = rxr->bnapi->index; 6061 6062 if (ring->fw_ring_id != INVALID_HW_RING_ID) { 6063 u32 cmpl_ring_id = bnxt_cp_ring_for_rx(bp, rxr); 6064 6065 hwrm_ring_free_send_msg(bp, ring, 6066 RING_FREE_REQ_RING_TYPE_RX, 6067 close_path ? cmpl_ring_id : 6068 INVALID_HW_RING_ID); 6069 ring->fw_ring_id = INVALID_HW_RING_ID; 6070 bp->grp_info[grp_idx].rx_fw_ring_id = 6071 INVALID_HW_RING_ID; 6072 } 6073 } 6074 6075 if (bp->flags & BNXT_FLAG_CHIP_P5) 6076 type = RING_FREE_REQ_RING_TYPE_RX_AGG; 6077 else 6078 type = RING_FREE_REQ_RING_TYPE_RX; 6079 for (i = 0; i < bp->rx_nr_rings; i++) { 6080 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 6081 struct bnxt_ring_struct *ring = &rxr->rx_agg_ring_struct; 6082 u32 grp_idx = rxr->bnapi->index; 6083 6084 if (ring->fw_ring_id != INVALID_HW_RING_ID) { 6085 u32 cmpl_ring_id = bnxt_cp_ring_for_rx(bp, rxr); 6086 6087 hwrm_ring_free_send_msg(bp, ring, type, 6088 close_path ? cmpl_ring_id : 6089 INVALID_HW_RING_ID); 6090 ring->fw_ring_id = INVALID_HW_RING_ID; 6091 bp->grp_info[grp_idx].agg_fw_ring_id = 6092 INVALID_HW_RING_ID; 6093 } 6094 } 6095 6096 /* The completion rings are about to be freed. After that the 6097 * IRQ doorbell will not work anymore. So we need to disable 6098 * IRQ here. 6099 */ 6100 bnxt_disable_int_sync(bp); 6101 6102 if (bp->flags & BNXT_FLAG_CHIP_P5) 6103 type = RING_FREE_REQ_RING_TYPE_NQ; 6104 else 6105 type = RING_FREE_REQ_RING_TYPE_L2_CMPL; 6106 for (i = 0; i < bp->cp_nr_rings; i++) { 6107 struct bnxt_napi *bnapi = bp->bnapi[i]; 6108 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 6109 struct bnxt_ring_struct *ring; 6110 int j; 6111 6112 for (j = 0; j < 2; j++) { 6113 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j]; 6114 6115 if (cpr2) { 6116 ring = &cpr2->cp_ring_struct; 6117 if (ring->fw_ring_id == INVALID_HW_RING_ID) 6118 continue; 6119 hwrm_ring_free_send_msg(bp, ring, 6120 RING_FREE_REQ_RING_TYPE_L2_CMPL, 6121 INVALID_HW_RING_ID); 6122 ring->fw_ring_id = INVALID_HW_RING_ID; 6123 } 6124 } 6125 ring = &cpr->cp_ring_struct; 6126 if (ring->fw_ring_id != INVALID_HW_RING_ID) { 6127 hwrm_ring_free_send_msg(bp, ring, type, 6128 INVALID_HW_RING_ID); 6129 ring->fw_ring_id = INVALID_HW_RING_ID; 6130 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID; 6131 } 6132 } 6133 } 6134 6135 static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max, 6136 bool shared); 6137 6138 static int bnxt_hwrm_get_rings(struct bnxt *bp) 6139 { 6140 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 6141 struct hwrm_func_qcfg_output *resp; 6142 struct hwrm_func_qcfg_input *req; 6143 int rc; 6144 6145 if (bp->hwrm_spec_code < 0x10601) 6146 return 0; 6147 6148 rc = hwrm_req_init(bp, req, HWRM_FUNC_QCFG); 6149 if (rc) 6150 return rc; 6151 6152 req->fid = cpu_to_le16(0xffff); 6153 resp = hwrm_req_hold(bp, req); 6154 rc = hwrm_req_send(bp, req); 6155 if (rc) { 6156 hwrm_req_drop(bp, req); 6157 return rc; 6158 } 6159 6160 hw_resc->resv_tx_rings = le16_to_cpu(resp->alloc_tx_rings); 6161 if (BNXT_NEW_RM(bp)) { 6162 u16 cp, stats; 6163 6164 hw_resc->resv_rx_rings = le16_to_cpu(resp->alloc_rx_rings); 6165 hw_resc->resv_hw_ring_grps = 6166 le32_to_cpu(resp->alloc_hw_ring_grps); 6167 hw_resc->resv_vnics = le16_to_cpu(resp->alloc_vnics); 6168 cp = le16_to_cpu(resp->alloc_cmpl_rings); 6169 stats = le16_to_cpu(resp->alloc_stat_ctx); 6170 hw_resc->resv_irqs = cp; 6171 if (bp->flags & BNXT_FLAG_CHIP_P5) { 6172 int rx = hw_resc->resv_rx_rings; 6173 int tx = hw_resc->resv_tx_rings; 6174 6175 if (bp->flags & BNXT_FLAG_AGG_RINGS) 6176 rx >>= 1; 6177 if (cp < (rx + tx)) { 6178 bnxt_trim_rings(bp, &rx, &tx, cp, false); 6179 if (bp->flags & BNXT_FLAG_AGG_RINGS) 6180 rx <<= 1; 6181 hw_resc->resv_rx_rings = rx; 6182 hw_resc->resv_tx_rings = tx; 6183 } 6184 hw_resc->resv_irqs = le16_to_cpu(resp->alloc_msix); 6185 hw_resc->resv_hw_ring_grps = rx; 6186 } 6187 hw_resc->resv_cp_rings = cp; 6188 hw_resc->resv_stat_ctxs = stats; 6189 } 6190 hwrm_req_drop(bp, req); 6191 return 0; 6192 } 6193 6194 int __bnxt_hwrm_get_tx_rings(struct bnxt *bp, u16 fid, int *tx_rings) 6195 { 6196 struct hwrm_func_qcfg_output *resp; 6197 struct hwrm_func_qcfg_input *req; 6198 int rc; 6199 6200 if (bp->hwrm_spec_code < 0x10601) 6201 return 0; 6202 6203 rc = hwrm_req_init(bp, req, HWRM_FUNC_QCFG); 6204 if (rc) 6205 return rc; 6206 6207 req->fid = cpu_to_le16(fid); 6208 resp = hwrm_req_hold(bp, req); 6209 rc = hwrm_req_send(bp, req); 6210 if (!rc) 6211 *tx_rings = le16_to_cpu(resp->alloc_tx_rings); 6212 6213 hwrm_req_drop(bp, req); 6214 return rc; 6215 } 6216 6217 static bool bnxt_rfs_supported(struct bnxt *bp); 6218 6219 static struct hwrm_func_cfg_input * 6220 __bnxt_hwrm_reserve_pf_rings(struct bnxt *bp, int tx_rings, int rx_rings, 6221 int ring_grps, int cp_rings, int stats, int vnics) 6222 { 6223 struct hwrm_func_cfg_input *req; 6224 u32 enables = 0; 6225 6226 if (hwrm_req_init(bp, req, HWRM_FUNC_CFG)) 6227 return NULL; 6228 6229 req->fid = cpu_to_le16(0xffff); 6230 enables |= tx_rings ? FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS : 0; 6231 req->num_tx_rings = cpu_to_le16(tx_rings); 6232 if (BNXT_NEW_RM(bp)) { 6233 enables |= rx_rings ? FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS : 0; 6234 enables |= stats ? FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0; 6235 if (bp->flags & BNXT_FLAG_CHIP_P5) { 6236 enables |= cp_rings ? FUNC_CFG_REQ_ENABLES_NUM_MSIX : 0; 6237 enables |= tx_rings + ring_grps ? 6238 FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0; 6239 enables |= rx_rings ? 6240 FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0; 6241 } else { 6242 enables |= cp_rings ? 6243 FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0; 6244 enables |= ring_grps ? 6245 FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS | 6246 FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0; 6247 } 6248 enables |= vnics ? FUNC_CFG_REQ_ENABLES_NUM_VNICS : 0; 6249 6250 req->num_rx_rings = cpu_to_le16(rx_rings); 6251 if (bp->flags & BNXT_FLAG_CHIP_P5) { 6252 req->num_cmpl_rings = cpu_to_le16(tx_rings + ring_grps); 6253 req->num_msix = cpu_to_le16(cp_rings); 6254 req->num_rsscos_ctxs = 6255 cpu_to_le16(DIV_ROUND_UP(ring_grps, 64)); 6256 } else { 6257 req->num_cmpl_rings = cpu_to_le16(cp_rings); 6258 req->num_hw_ring_grps = cpu_to_le16(ring_grps); 6259 req->num_rsscos_ctxs = cpu_to_le16(1); 6260 if (!(bp->flags & BNXT_FLAG_NEW_RSS_CAP) && 6261 bnxt_rfs_supported(bp)) 6262 req->num_rsscos_ctxs = 6263 cpu_to_le16(ring_grps + 1); 6264 } 6265 req->num_stat_ctxs = cpu_to_le16(stats); 6266 req->num_vnics = cpu_to_le16(vnics); 6267 } 6268 req->enables = cpu_to_le32(enables); 6269 return req; 6270 } 6271 6272 static struct hwrm_func_vf_cfg_input * 6273 __bnxt_hwrm_reserve_vf_rings(struct bnxt *bp, int tx_rings, int rx_rings, 6274 int ring_grps, int cp_rings, int stats, int vnics) 6275 { 6276 struct hwrm_func_vf_cfg_input *req; 6277 u32 enables = 0; 6278 6279 if (hwrm_req_init(bp, req, HWRM_FUNC_VF_CFG)) 6280 return NULL; 6281 6282 enables |= tx_rings ? FUNC_VF_CFG_REQ_ENABLES_NUM_TX_RINGS : 0; 6283 enables |= rx_rings ? FUNC_VF_CFG_REQ_ENABLES_NUM_RX_RINGS | 6284 FUNC_VF_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0; 6285 enables |= stats ? FUNC_VF_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0; 6286 if (bp->flags & BNXT_FLAG_CHIP_P5) { 6287 enables |= tx_rings + ring_grps ? 6288 FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0; 6289 } else { 6290 enables |= cp_rings ? 6291 FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0; 6292 enables |= ring_grps ? 6293 FUNC_VF_CFG_REQ_ENABLES_NUM_HW_RING_GRPS : 0; 6294 } 6295 enables |= vnics ? FUNC_VF_CFG_REQ_ENABLES_NUM_VNICS : 0; 6296 enables |= FUNC_VF_CFG_REQ_ENABLES_NUM_L2_CTXS; 6297 6298 req->num_l2_ctxs = cpu_to_le16(BNXT_VF_MAX_L2_CTX); 6299 req->num_tx_rings = cpu_to_le16(tx_rings); 6300 req->num_rx_rings = cpu_to_le16(rx_rings); 6301 if (bp->flags & BNXT_FLAG_CHIP_P5) { 6302 req->num_cmpl_rings = cpu_to_le16(tx_rings + ring_grps); 6303 req->num_rsscos_ctxs = cpu_to_le16(DIV_ROUND_UP(ring_grps, 64)); 6304 } else { 6305 req->num_cmpl_rings = cpu_to_le16(cp_rings); 6306 req->num_hw_ring_grps = cpu_to_le16(ring_grps); 6307 req->num_rsscos_ctxs = cpu_to_le16(BNXT_VF_MAX_RSS_CTX); 6308 } 6309 req->num_stat_ctxs = cpu_to_le16(stats); 6310 req->num_vnics = cpu_to_le16(vnics); 6311 6312 req->enables = cpu_to_le32(enables); 6313 return req; 6314 } 6315 6316 static int 6317 bnxt_hwrm_reserve_pf_rings(struct bnxt *bp, int tx_rings, int rx_rings, 6318 int ring_grps, int cp_rings, int stats, int vnics) 6319 { 6320 struct hwrm_func_cfg_input *req; 6321 int rc; 6322 6323 req = __bnxt_hwrm_reserve_pf_rings(bp, tx_rings, rx_rings, ring_grps, 6324 cp_rings, stats, vnics); 6325 if (!req) 6326 return -ENOMEM; 6327 6328 if (!req->enables) { 6329 hwrm_req_drop(bp, req); 6330 return 0; 6331 } 6332 6333 rc = hwrm_req_send(bp, req); 6334 if (rc) 6335 return rc; 6336 6337 if (bp->hwrm_spec_code < 0x10601) 6338 bp->hw_resc.resv_tx_rings = tx_rings; 6339 6340 return bnxt_hwrm_get_rings(bp); 6341 } 6342 6343 static int 6344 bnxt_hwrm_reserve_vf_rings(struct bnxt *bp, int tx_rings, int rx_rings, 6345 int ring_grps, int cp_rings, int stats, int vnics) 6346 { 6347 struct hwrm_func_vf_cfg_input *req; 6348 int rc; 6349 6350 if (!BNXT_NEW_RM(bp)) { 6351 bp->hw_resc.resv_tx_rings = tx_rings; 6352 return 0; 6353 } 6354 6355 req = __bnxt_hwrm_reserve_vf_rings(bp, tx_rings, rx_rings, ring_grps, 6356 cp_rings, stats, vnics); 6357 if (!req) 6358 return -ENOMEM; 6359 6360 rc = hwrm_req_send(bp, req); 6361 if (rc) 6362 return rc; 6363 6364 return bnxt_hwrm_get_rings(bp); 6365 } 6366 6367 static int bnxt_hwrm_reserve_rings(struct bnxt *bp, int tx, int rx, int grp, 6368 int cp, int stat, int vnic) 6369 { 6370 if (BNXT_PF(bp)) 6371 return bnxt_hwrm_reserve_pf_rings(bp, tx, rx, grp, cp, stat, 6372 vnic); 6373 else 6374 return bnxt_hwrm_reserve_vf_rings(bp, tx, rx, grp, cp, stat, 6375 vnic); 6376 } 6377 6378 int bnxt_nq_rings_in_use(struct bnxt *bp) 6379 { 6380 int cp = bp->cp_nr_rings; 6381 int ulp_msix, ulp_base; 6382 6383 ulp_msix = bnxt_get_ulp_msix_num(bp); 6384 if (ulp_msix) { 6385 ulp_base = bnxt_get_ulp_msix_base(bp); 6386 cp += ulp_msix; 6387 if ((ulp_base + ulp_msix) > cp) 6388 cp = ulp_base + ulp_msix; 6389 } 6390 return cp; 6391 } 6392 6393 static int bnxt_cp_rings_in_use(struct bnxt *bp) 6394 { 6395 int cp; 6396 6397 if (!(bp->flags & BNXT_FLAG_CHIP_P5)) 6398 return bnxt_nq_rings_in_use(bp); 6399 6400 cp = bp->tx_nr_rings + bp->rx_nr_rings; 6401 return cp; 6402 } 6403 6404 static int bnxt_get_func_stat_ctxs(struct bnxt *bp) 6405 { 6406 int ulp_stat = bnxt_get_ulp_stat_ctxs(bp); 6407 int cp = bp->cp_nr_rings; 6408 6409 if (!ulp_stat) 6410 return cp; 6411 6412 if (bnxt_nq_rings_in_use(bp) > cp + bnxt_get_ulp_msix_num(bp)) 6413 return bnxt_get_ulp_msix_base(bp) + ulp_stat; 6414 6415 return cp + ulp_stat; 6416 } 6417 6418 /* Check if a default RSS map needs to be setup. This function is only 6419 * used on older firmware that does not require reserving RX rings. 6420 */ 6421 static void bnxt_check_rss_tbl_no_rmgr(struct bnxt *bp) 6422 { 6423 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 6424 6425 /* The RSS map is valid for RX rings set to resv_rx_rings */ 6426 if (hw_resc->resv_rx_rings != bp->rx_nr_rings) { 6427 hw_resc->resv_rx_rings = bp->rx_nr_rings; 6428 if (!netif_is_rxfh_configured(bp->dev)) 6429 bnxt_set_dflt_rss_indir_tbl(bp); 6430 } 6431 } 6432 6433 static bool bnxt_need_reserve_rings(struct bnxt *bp) 6434 { 6435 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 6436 int cp = bnxt_cp_rings_in_use(bp); 6437 int nq = bnxt_nq_rings_in_use(bp); 6438 int rx = bp->rx_nr_rings, stat; 6439 int vnic = 1, grp = rx; 6440 6441 if (hw_resc->resv_tx_rings != bp->tx_nr_rings && 6442 bp->hwrm_spec_code >= 0x10601) 6443 return true; 6444 6445 /* Old firmware does not need RX ring reservations but we still 6446 * need to setup a default RSS map when needed. With new firmware 6447 * we go through RX ring reservations first and then set up the 6448 * RSS map for the successfully reserved RX rings when needed. 6449 */ 6450 if (!BNXT_NEW_RM(bp)) { 6451 bnxt_check_rss_tbl_no_rmgr(bp); 6452 return false; 6453 } 6454 if ((bp->flags & BNXT_FLAG_RFS) && !(bp->flags & BNXT_FLAG_CHIP_P5)) 6455 vnic = rx + 1; 6456 if (bp->flags & BNXT_FLAG_AGG_RINGS) 6457 rx <<= 1; 6458 stat = bnxt_get_func_stat_ctxs(bp); 6459 if (hw_resc->resv_rx_rings != rx || hw_resc->resv_cp_rings != cp || 6460 hw_resc->resv_vnics != vnic || hw_resc->resv_stat_ctxs != stat || 6461 (hw_resc->resv_hw_ring_grps != grp && 6462 !(bp->flags & BNXT_FLAG_CHIP_P5))) 6463 return true; 6464 if ((bp->flags & BNXT_FLAG_CHIP_P5) && BNXT_PF(bp) && 6465 hw_resc->resv_irqs != nq) 6466 return true; 6467 return false; 6468 } 6469 6470 static int __bnxt_reserve_rings(struct bnxt *bp) 6471 { 6472 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 6473 int cp = bnxt_nq_rings_in_use(bp); 6474 int tx = bp->tx_nr_rings; 6475 int rx = bp->rx_nr_rings; 6476 int grp, rx_rings, rc; 6477 int vnic = 1, stat; 6478 bool sh = false; 6479 6480 if (!bnxt_need_reserve_rings(bp)) 6481 return 0; 6482 6483 if (bp->flags & BNXT_FLAG_SHARED_RINGS) 6484 sh = true; 6485 if ((bp->flags & BNXT_FLAG_RFS) && !(bp->flags & BNXT_FLAG_CHIP_P5)) 6486 vnic = rx + 1; 6487 if (bp->flags & BNXT_FLAG_AGG_RINGS) 6488 rx <<= 1; 6489 grp = bp->rx_nr_rings; 6490 stat = bnxt_get_func_stat_ctxs(bp); 6491 6492 rc = bnxt_hwrm_reserve_rings(bp, tx, rx, grp, cp, stat, vnic); 6493 if (rc) 6494 return rc; 6495 6496 tx = hw_resc->resv_tx_rings; 6497 if (BNXT_NEW_RM(bp)) { 6498 rx = hw_resc->resv_rx_rings; 6499 cp = hw_resc->resv_irqs; 6500 grp = hw_resc->resv_hw_ring_grps; 6501 vnic = hw_resc->resv_vnics; 6502 stat = hw_resc->resv_stat_ctxs; 6503 } 6504 6505 rx_rings = rx; 6506 if (bp->flags & BNXT_FLAG_AGG_RINGS) { 6507 if (rx >= 2) { 6508 rx_rings = rx >> 1; 6509 } else { 6510 if (netif_running(bp->dev)) 6511 return -ENOMEM; 6512 6513 bp->flags &= ~BNXT_FLAG_AGG_RINGS; 6514 bp->flags |= BNXT_FLAG_NO_AGG_RINGS; 6515 bp->dev->hw_features &= ~NETIF_F_LRO; 6516 bp->dev->features &= ~NETIF_F_LRO; 6517 bnxt_set_ring_params(bp); 6518 } 6519 } 6520 rx_rings = min_t(int, rx_rings, grp); 6521 cp = min_t(int, cp, bp->cp_nr_rings); 6522 if (stat > bnxt_get_ulp_stat_ctxs(bp)) 6523 stat -= bnxt_get_ulp_stat_ctxs(bp); 6524 cp = min_t(int, cp, stat); 6525 rc = bnxt_trim_rings(bp, &rx_rings, &tx, cp, sh); 6526 if (bp->flags & BNXT_FLAG_AGG_RINGS) 6527 rx = rx_rings << 1; 6528 cp = sh ? max_t(int, tx, rx_rings) : tx + rx_rings; 6529 bp->tx_nr_rings = tx; 6530 6531 /* If we cannot reserve all the RX rings, reset the RSS map only 6532 * if absolutely necessary 6533 */ 6534 if (rx_rings != bp->rx_nr_rings) { 6535 netdev_warn(bp->dev, "Able to reserve only %d out of %d requested RX rings\n", 6536 rx_rings, bp->rx_nr_rings); 6537 if (netif_is_rxfh_configured(bp->dev) && 6538 (bnxt_get_nr_rss_ctxs(bp, bp->rx_nr_rings) != 6539 bnxt_get_nr_rss_ctxs(bp, rx_rings) || 6540 bnxt_get_max_rss_ring(bp) >= rx_rings)) { 6541 netdev_warn(bp->dev, "RSS table entries reverting to default\n"); 6542 bp->dev->priv_flags &= ~IFF_RXFH_CONFIGURED; 6543 } 6544 } 6545 bp->rx_nr_rings = rx_rings; 6546 bp->cp_nr_rings = cp; 6547 6548 if (!tx || !rx || !cp || !grp || !vnic || !stat) 6549 return -ENOMEM; 6550 6551 if (!netif_is_rxfh_configured(bp->dev)) 6552 bnxt_set_dflt_rss_indir_tbl(bp); 6553 6554 return rc; 6555 } 6556 6557 static int bnxt_hwrm_check_vf_rings(struct bnxt *bp, int tx_rings, int rx_rings, 6558 int ring_grps, int cp_rings, int stats, 6559 int vnics) 6560 { 6561 struct hwrm_func_vf_cfg_input *req; 6562 u32 flags; 6563 6564 if (!BNXT_NEW_RM(bp)) 6565 return 0; 6566 6567 req = __bnxt_hwrm_reserve_vf_rings(bp, tx_rings, rx_rings, ring_grps, 6568 cp_rings, stats, vnics); 6569 flags = FUNC_VF_CFG_REQ_FLAGS_TX_ASSETS_TEST | 6570 FUNC_VF_CFG_REQ_FLAGS_RX_ASSETS_TEST | 6571 FUNC_VF_CFG_REQ_FLAGS_CMPL_ASSETS_TEST | 6572 FUNC_VF_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST | 6573 FUNC_VF_CFG_REQ_FLAGS_VNIC_ASSETS_TEST | 6574 FUNC_VF_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST; 6575 if (!(bp->flags & BNXT_FLAG_CHIP_P5)) 6576 flags |= FUNC_VF_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST; 6577 6578 req->flags = cpu_to_le32(flags); 6579 return hwrm_req_send_silent(bp, req); 6580 } 6581 6582 static int bnxt_hwrm_check_pf_rings(struct bnxt *bp, int tx_rings, int rx_rings, 6583 int ring_grps, int cp_rings, int stats, 6584 int vnics) 6585 { 6586 struct hwrm_func_cfg_input *req; 6587 u32 flags; 6588 6589 req = __bnxt_hwrm_reserve_pf_rings(bp, tx_rings, rx_rings, ring_grps, 6590 cp_rings, stats, vnics); 6591 flags = FUNC_CFG_REQ_FLAGS_TX_ASSETS_TEST; 6592 if (BNXT_NEW_RM(bp)) { 6593 flags |= FUNC_CFG_REQ_FLAGS_RX_ASSETS_TEST | 6594 FUNC_CFG_REQ_FLAGS_CMPL_ASSETS_TEST | 6595 FUNC_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST | 6596 FUNC_CFG_REQ_FLAGS_VNIC_ASSETS_TEST; 6597 if (bp->flags & BNXT_FLAG_CHIP_P5) 6598 flags |= FUNC_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST | 6599 FUNC_CFG_REQ_FLAGS_NQ_ASSETS_TEST; 6600 else 6601 flags |= FUNC_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST; 6602 } 6603 6604 req->flags = cpu_to_le32(flags); 6605 return hwrm_req_send_silent(bp, req); 6606 } 6607 6608 static int bnxt_hwrm_check_rings(struct bnxt *bp, int tx_rings, int rx_rings, 6609 int ring_grps, int cp_rings, int stats, 6610 int vnics) 6611 { 6612 if (bp->hwrm_spec_code < 0x10801) 6613 return 0; 6614 6615 if (BNXT_PF(bp)) 6616 return bnxt_hwrm_check_pf_rings(bp, tx_rings, rx_rings, 6617 ring_grps, cp_rings, stats, 6618 vnics); 6619 6620 return bnxt_hwrm_check_vf_rings(bp, tx_rings, rx_rings, ring_grps, 6621 cp_rings, stats, vnics); 6622 } 6623 6624 static void bnxt_hwrm_coal_params_qcaps(struct bnxt *bp) 6625 { 6626 struct bnxt_coal_cap *coal_cap = &bp->coal_cap; 6627 struct hwrm_ring_aggint_qcaps_output *resp; 6628 struct hwrm_ring_aggint_qcaps_input *req; 6629 int rc; 6630 6631 coal_cap->cmpl_params = BNXT_LEGACY_COAL_CMPL_PARAMS; 6632 coal_cap->num_cmpl_dma_aggr_max = 63; 6633 coal_cap->num_cmpl_dma_aggr_during_int_max = 63; 6634 coal_cap->cmpl_aggr_dma_tmr_max = 65535; 6635 coal_cap->cmpl_aggr_dma_tmr_during_int_max = 65535; 6636 coal_cap->int_lat_tmr_min_max = 65535; 6637 coal_cap->int_lat_tmr_max_max = 65535; 6638 coal_cap->num_cmpl_aggr_int_max = 65535; 6639 coal_cap->timer_units = 80; 6640 6641 if (bp->hwrm_spec_code < 0x10902) 6642 return; 6643 6644 if (hwrm_req_init(bp, req, HWRM_RING_AGGINT_QCAPS)) 6645 return; 6646 6647 resp = hwrm_req_hold(bp, req); 6648 rc = hwrm_req_send_silent(bp, req); 6649 if (!rc) { 6650 coal_cap->cmpl_params = le32_to_cpu(resp->cmpl_params); 6651 coal_cap->nq_params = le32_to_cpu(resp->nq_params); 6652 coal_cap->num_cmpl_dma_aggr_max = 6653 le16_to_cpu(resp->num_cmpl_dma_aggr_max); 6654 coal_cap->num_cmpl_dma_aggr_during_int_max = 6655 le16_to_cpu(resp->num_cmpl_dma_aggr_during_int_max); 6656 coal_cap->cmpl_aggr_dma_tmr_max = 6657 le16_to_cpu(resp->cmpl_aggr_dma_tmr_max); 6658 coal_cap->cmpl_aggr_dma_tmr_during_int_max = 6659 le16_to_cpu(resp->cmpl_aggr_dma_tmr_during_int_max); 6660 coal_cap->int_lat_tmr_min_max = 6661 le16_to_cpu(resp->int_lat_tmr_min_max); 6662 coal_cap->int_lat_tmr_max_max = 6663 le16_to_cpu(resp->int_lat_tmr_max_max); 6664 coal_cap->num_cmpl_aggr_int_max = 6665 le16_to_cpu(resp->num_cmpl_aggr_int_max); 6666 coal_cap->timer_units = le16_to_cpu(resp->timer_units); 6667 } 6668 hwrm_req_drop(bp, req); 6669 } 6670 6671 static u16 bnxt_usec_to_coal_tmr(struct bnxt *bp, u16 usec) 6672 { 6673 struct bnxt_coal_cap *coal_cap = &bp->coal_cap; 6674 6675 return usec * 1000 / coal_cap->timer_units; 6676 } 6677 6678 static void bnxt_hwrm_set_coal_params(struct bnxt *bp, 6679 struct bnxt_coal *hw_coal, 6680 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req) 6681 { 6682 struct bnxt_coal_cap *coal_cap = &bp->coal_cap; 6683 u16 val, tmr, max, flags = hw_coal->flags; 6684 u32 cmpl_params = coal_cap->cmpl_params; 6685 6686 max = hw_coal->bufs_per_record * 128; 6687 if (hw_coal->budget) 6688 max = hw_coal->bufs_per_record * hw_coal->budget; 6689 max = min_t(u16, max, coal_cap->num_cmpl_aggr_int_max); 6690 6691 val = clamp_t(u16, hw_coal->coal_bufs, 1, max); 6692 req->num_cmpl_aggr_int = cpu_to_le16(val); 6693 6694 val = min_t(u16, val, coal_cap->num_cmpl_dma_aggr_max); 6695 req->num_cmpl_dma_aggr = cpu_to_le16(val); 6696 6697 val = clamp_t(u16, hw_coal->coal_bufs_irq, 1, 6698 coal_cap->num_cmpl_dma_aggr_during_int_max); 6699 req->num_cmpl_dma_aggr_during_int = cpu_to_le16(val); 6700 6701 tmr = bnxt_usec_to_coal_tmr(bp, hw_coal->coal_ticks); 6702 tmr = clamp_t(u16, tmr, 1, coal_cap->int_lat_tmr_max_max); 6703 req->int_lat_tmr_max = cpu_to_le16(tmr); 6704 6705 /* min timer set to 1/2 of interrupt timer */ 6706 if (cmpl_params & RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN) { 6707 val = tmr / 2; 6708 val = clamp_t(u16, val, 1, coal_cap->int_lat_tmr_min_max); 6709 req->int_lat_tmr_min = cpu_to_le16(val); 6710 req->enables |= cpu_to_le16(BNXT_COAL_CMPL_MIN_TMR_ENABLE); 6711 } 6712 6713 /* buf timer set to 1/4 of interrupt timer */ 6714 val = clamp_t(u16, tmr / 4, 1, coal_cap->cmpl_aggr_dma_tmr_max); 6715 req->cmpl_aggr_dma_tmr = cpu_to_le16(val); 6716 6717 if (cmpl_params & 6718 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT) { 6719 tmr = bnxt_usec_to_coal_tmr(bp, hw_coal->coal_ticks_irq); 6720 val = clamp_t(u16, tmr, 1, 6721 coal_cap->cmpl_aggr_dma_tmr_during_int_max); 6722 req->cmpl_aggr_dma_tmr_during_int = cpu_to_le16(val); 6723 req->enables |= 6724 cpu_to_le16(BNXT_COAL_CMPL_AGGR_TMR_DURING_INT_ENABLE); 6725 } 6726 6727 if ((cmpl_params & RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE) && 6728 hw_coal->idle_thresh && hw_coal->coal_ticks < hw_coal->idle_thresh) 6729 flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE; 6730 req->flags = cpu_to_le16(flags); 6731 req->enables |= cpu_to_le16(BNXT_COAL_CMPL_ENABLES); 6732 } 6733 6734 static int __bnxt_hwrm_set_coal_nq(struct bnxt *bp, struct bnxt_napi *bnapi, 6735 struct bnxt_coal *hw_coal) 6736 { 6737 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req; 6738 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 6739 struct bnxt_coal_cap *coal_cap = &bp->coal_cap; 6740 u32 nq_params = coal_cap->nq_params; 6741 u16 tmr; 6742 int rc; 6743 6744 if (!(nq_params & RING_AGGINT_QCAPS_RESP_NQ_PARAMS_INT_LAT_TMR_MIN)) 6745 return 0; 6746 6747 rc = hwrm_req_init(bp, req, HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS); 6748 if (rc) 6749 return rc; 6750 6751 req->ring_id = cpu_to_le16(cpr->cp_ring_struct.fw_ring_id); 6752 req->flags = 6753 cpu_to_le16(RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_IS_NQ); 6754 6755 tmr = bnxt_usec_to_coal_tmr(bp, hw_coal->coal_ticks) / 2; 6756 tmr = clamp_t(u16, tmr, 1, coal_cap->int_lat_tmr_min_max); 6757 req->int_lat_tmr_min = cpu_to_le16(tmr); 6758 req->enables |= cpu_to_le16(BNXT_COAL_CMPL_MIN_TMR_ENABLE); 6759 return hwrm_req_send(bp, req); 6760 } 6761 6762 int bnxt_hwrm_set_ring_coal(struct bnxt *bp, struct bnxt_napi *bnapi) 6763 { 6764 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req_rx; 6765 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 6766 struct bnxt_coal coal; 6767 int rc; 6768 6769 /* Tick values in micro seconds. 6770 * 1 coal_buf x bufs_per_record = 1 completion record. 6771 */ 6772 memcpy(&coal, &bp->rx_coal, sizeof(struct bnxt_coal)); 6773 6774 coal.coal_ticks = cpr->rx_ring_coal.coal_ticks; 6775 coal.coal_bufs = cpr->rx_ring_coal.coal_bufs; 6776 6777 if (!bnapi->rx_ring) 6778 return -ENODEV; 6779 6780 rc = hwrm_req_init(bp, req_rx, HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS); 6781 if (rc) 6782 return rc; 6783 6784 bnxt_hwrm_set_coal_params(bp, &coal, req_rx); 6785 6786 req_rx->ring_id = cpu_to_le16(bnxt_cp_ring_for_rx(bp, bnapi->rx_ring)); 6787 6788 return hwrm_req_send(bp, req_rx); 6789 } 6790 6791 int bnxt_hwrm_set_coal(struct bnxt *bp) 6792 { 6793 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req_rx, *req_tx, 6794 *req; 6795 int i, rc; 6796 6797 rc = hwrm_req_init(bp, req_rx, HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS); 6798 if (rc) 6799 return rc; 6800 6801 rc = hwrm_req_init(bp, req_tx, HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS); 6802 if (rc) { 6803 hwrm_req_drop(bp, req_rx); 6804 return rc; 6805 } 6806 6807 bnxt_hwrm_set_coal_params(bp, &bp->rx_coal, req_rx); 6808 bnxt_hwrm_set_coal_params(bp, &bp->tx_coal, req_tx); 6809 6810 hwrm_req_hold(bp, req_rx); 6811 hwrm_req_hold(bp, req_tx); 6812 for (i = 0; i < bp->cp_nr_rings; i++) { 6813 struct bnxt_napi *bnapi = bp->bnapi[i]; 6814 struct bnxt_coal *hw_coal; 6815 u16 ring_id; 6816 6817 req = req_rx; 6818 if (!bnapi->rx_ring) { 6819 ring_id = bnxt_cp_ring_for_tx(bp, bnapi->tx_ring); 6820 req = req_tx; 6821 } else { 6822 ring_id = bnxt_cp_ring_for_rx(bp, bnapi->rx_ring); 6823 } 6824 req->ring_id = cpu_to_le16(ring_id); 6825 6826 rc = hwrm_req_send(bp, req); 6827 if (rc) 6828 break; 6829 6830 if (!(bp->flags & BNXT_FLAG_CHIP_P5)) 6831 continue; 6832 6833 if (bnapi->rx_ring && bnapi->tx_ring) { 6834 req = req_tx; 6835 ring_id = bnxt_cp_ring_for_tx(bp, bnapi->tx_ring); 6836 req->ring_id = cpu_to_le16(ring_id); 6837 rc = hwrm_req_send(bp, req); 6838 if (rc) 6839 break; 6840 } 6841 if (bnapi->rx_ring) 6842 hw_coal = &bp->rx_coal; 6843 else 6844 hw_coal = &bp->tx_coal; 6845 __bnxt_hwrm_set_coal_nq(bp, bnapi, hw_coal); 6846 } 6847 hwrm_req_drop(bp, req_rx); 6848 hwrm_req_drop(bp, req_tx); 6849 return rc; 6850 } 6851 6852 static void bnxt_hwrm_stat_ctx_free(struct bnxt *bp) 6853 { 6854 struct hwrm_stat_ctx_clr_stats_input *req0 = NULL; 6855 struct hwrm_stat_ctx_free_input *req; 6856 int i; 6857 6858 if (!bp->bnapi) 6859 return; 6860 6861 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 6862 return; 6863 6864 if (hwrm_req_init(bp, req, HWRM_STAT_CTX_FREE)) 6865 return; 6866 if (BNXT_FW_MAJ(bp) <= 20) { 6867 if (hwrm_req_init(bp, req0, HWRM_STAT_CTX_CLR_STATS)) { 6868 hwrm_req_drop(bp, req); 6869 return; 6870 } 6871 hwrm_req_hold(bp, req0); 6872 } 6873 hwrm_req_hold(bp, req); 6874 for (i = 0; i < bp->cp_nr_rings; i++) { 6875 struct bnxt_napi *bnapi = bp->bnapi[i]; 6876 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 6877 6878 if (cpr->hw_stats_ctx_id != INVALID_STATS_CTX_ID) { 6879 req->stat_ctx_id = cpu_to_le32(cpr->hw_stats_ctx_id); 6880 if (req0) { 6881 req0->stat_ctx_id = req->stat_ctx_id; 6882 hwrm_req_send(bp, req0); 6883 } 6884 hwrm_req_send(bp, req); 6885 6886 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID; 6887 } 6888 } 6889 hwrm_req_drop(bp, req); 6890 if (req0) 6891 hwrm_req_drop(bp, req0); 6892 } 6893 6894 static int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp) 6895 { 6896 struct hwrm_stat_ctx_alloc_output *resp; 6897 struct hwrm_stat_ctx_alloc_input *req; 6898 int rc, i; 6899 6900 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 6901 return 0; 6902 6903 rc = hwrm_req_init(bp, req, HWRM_STAT_CTX_ALLOC); 6904 if (rc) 6905 return rc; 6906 6907 req->stats_dma_length = cpu_to_le16(bp->hw_ring_stats_size); 6908 req->update_period_ms = cpu_to_le32(bp->stats_coal_ticks / 1000); 6909 6910 resp = hwrm_req_hold(bp, req); 6911 for (i = 0; i < bp->cp_nr_rings; i++) { 6912 struct bnxt_napi *bnapi = bp->bnapi[i]; 6913 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 6914 6915 req->stats_dma_addr = cpu_to_le64(cpr->stats.hw_stats_map); 6916 6917 rc = hwrm_req_send(bp, req); 6918 if (rc) 6919 break; 6920 6921 cpr->hw_stats_ctx_id = le32_to_cpu(resp->stat_ctx_id); 6922 6923 bp->grp_info[i].fw_stats_ctx = cpr->hw_stats_ctx_id; 6924 } 6925 hwrm_req_drop(bp, req); 6926 return rc; 6927 } 6928 6929 static int bnxt_hwrm_func_qcfg(struct bnxt *bp) 6930 { 6931 struct hwrm_func_qcfg_output *resp; 6932 struct hwrm_func_qcfg_input *req; 6933 u32 min_db_offset = 0; 6934 u16 flags; 6935 int rc; 6936 6937 rc = hwrm_req_init(bp, req, HWRM_FUNC_QCFG); 6938 if (rc) 6939 return rc; 6940 6941 req->fid = cpu_to_le16(0xffff); 6942 resp = hwrm_req_hold(bp, req); 6943 rc = hwrm_req_send(bp, req); 6944 if (rc) 6945 goto func_qcfg_exit; 6946 6947 #ifdef CONFIG_BNXT_SRIOV 6948 if (BNXT_VF(bp)) { 6949 struct bnxt_vf_info *vf = &bp->vf; 6950 6951 vf->vlan = le16_to_cpu(resp->vlan) & VLAN_VID_MASK; 6952 } else { 6953 bp->pf.registered_vfs = le16_to_cpu(resp->registered_vfs); 6954 } 6955 #endif 6956 flags = le16_to_cpu(resp->flags); 6957 if (flags & (FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED | 6958 FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED)) { 6959 bp->fw_cap |= BNXT_FW_CAP_LLDP_AGENT; 6960 if (flags & FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED) 6961 bp->fw_cap |= BNXT_FW_CAP_DCBX_AGENT; 6962 } 6963 if (BNXT_PF(bp) && (flags & FUNC_QCFG_RESP_FLAGS_MULTI_HOST)) 6964 bp->flags |= BNXT_FLAG_MULTI_HOST; 6965 6966 if (flags & FUNC_QCFG_RESP_FLAGS_RING_MONITOR_ENABLED) 6967 bp->fw_cap |= BNXT_FW_CAP_RING_MONITOR; 6968 6969 switch (resp->port_partition_type) { 6970 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0: 6971 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5: 6972 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0: 6973 bp->port_partition_type = resp->port_partition_type; 6974 break; 6975 } 6976 if (bp->hwrm_spec_code < 0x10707 || 6977 resp->evb_mode == FUNC_QCFG_RESP_EVB_MODE_VEB) 6978 bp->br_mode = BRIDGE_MODE_VEB; 6979 else if (resp->evb_mode == FUNC_QCFG_RESP_EVB_MODE_VEPA) 6980 bp->br_mode = BRIDGE_MODE_VEPA; 6981 else 6982 bp->br_mode = BRIDGE_MODE_UNDEF; 6983 6984 bp->max_mtu = le16_to_cpu(resp->max_mtu_configured); 6985 if (!bp->max_mtu) 6986 bp->max_mtu = BNXT_MAX_MTU; 6987 6988 if (bp->db_size) 6989 goto func_qcfg_exit; 6990 6991 if (bp->flags & BNXT_FLAG_CHIP_P5) { 6992 if (BNXT_PF(bp)) 6993 min_db_offset = DB_PF_OFFSET_P5; 6994 else 6995 min_db_offset = DB_VF_OFFSET_P5; 6996 } 6997 bp->db_size = PAGE_ALIGN(le16_to_cpu(resp->l2_doorbell_bar_size_kb) * 6998 1024); 6999 if (!bp->db_size || bp->db_size > pci_resource_len(bp->pdev, 2) || 7000 bp->db_size <= min_db_offset) 7001 bp->db_size = pci_resource_len(bp->pdev, 2); 7002 7003 func_qcfg_exit: 7004 hwrm_req_drop(bp, req); 7005 return rc; 7006 } 7007 7008 static void bnxt_init_ctx_initializer(struct bnxt_ctx_mem_info *ctx, 7009 struct hwrm_func_backing_store_qcaps_output *resp) 7010 { 7011 struct bnxt_mem_init *mem_init; 7012 u16 init_mask; 7013 u8 init_val; 7014 u8 *offset; 7015 int i; 7016 7017 init_val = resp->ctx_kind_initializer; 7018 init_mask = le16_to_cpu(resp->ctx_init_mask); 7019 offset = &resp->qp_init_offset; 7020 mem_init = &ctx->mem_init[BNXT_CTX_MEM_INIT_QP]; 7021 for (i = 0; i < BNXT_CTX_MEM_INIT_MAX; i++, mem_init++, offset++) { 7022 mem_init->init_val = init_val; 7023 mem_init->offset = BNXT_MEM_INVALID_OFFSET; 7024 if (!init_mask) 7025 continue; 7026 if (i == BNXT_CTX_MEM_INIT_STAT) 7027 offset = &resp->stat_init_offset; 7028 if (init_mask & (1 << i)) 7029 mem_init->offset = *offset * 4; 7030 else 7031 mem_init->init_val = 0; 7032 } 7033 ctx->mem_init[BNXT_CTX_MEM_INIT_QP].size = ctx->qp_entry_size; 7034 ctx->mem_init[BNXT_CTX_MEM_INIT_SRQ].size = ctx->srq_entry_size; 7035 ctx->mem_init[BNXT_CTX_MEM_INIT_CQ].size = ctx->cq_entry_size; 7036 ctx->mem_init[BNXT_CTX_MEM_INIT_VNIC].size = ctx->vnic_entry_size; 7037 ctx->mem_init[BNXT_CTX_MEM_INIT_STAT].size = ctx->stat_entry_size; 7038 ctx->mem_init[BNXT_CTX_MEM_INIT_MRAV].size = ctx->mrav_entry_size; 7039 } 7040 7041 static int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp) 7042 { 7043 struct hwrm_func_backing_store_qcaps_output *resp; 7044 struct hwrm_func_backing_store_qcaps_input *req; 7045 int rc; 7046 7047 if (bp->hwrm_spec_code < 0x10902 || BNXT_VF(bp) || bp->ctx) 7048 return 0; 7049 7050 rc = hwrm_req_init(bp, req, HWRM_FUNC_BACKING_STORE_QCAPS); 7051 if (rc) 7052 return rc; 7053 7054 resp = hwrm_req_hold(bp, req); 7055 rc = hwrm_req_send_silent(bp, req); 7056 if (!rc) { 7057 struct bnxt_ctx_pg_info *ctx_pg; 7058 struct bnxt_ctx_mem_info *ctx; 7059 int i, tqm_rings; 7060 7061 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); 7062 if (!ctx) { 7063 rc = -ENOMEM; 7064 goto ctx_err; 7065 } 7066 ctx->qp_max_entries = le32_to_cpu(resp->qp_max_entries); 7067 ctx->qp_min_qp1_entries = le16_to_cpu(resp->qp_min_qp1_entries); 7068 ctx->qp_max_l2_entries = le16_to_cpu(resp->qp_max_l2_entries); 7069 ctx->qp_entry_size = le16_to_cpu(resp->qp_entry_size); 7070 ctx->srq_max_l2_entries = le16_to_cpu(resp->srq_max_l2_entries); 7071 ctx->srq_max_entries = le32_to_cpu(resp->srq_max_entries); 7072 ctx->srq_entry_size = le16_to_cpu(resp->srq_entry_size); 7073 ctx->cq_max_l2_entries = le16_to_cpu(resp->cq_max_l2_entries); 7074 ctx->cq_max_entries = le32_to_cpu(resp->cq_max_entries); 7075 ctx->cq_entry_size = le16_to_cpu(resp->cq_entry_size); 7076 ctx->vnic_max_vnic_entries = 7077 le16_to_cpu(resp->vnic_max_vnic_entries); 7078 ctx->vnic_max_ring_table_entries = 7079 le16_to_cpu(resp->vnic_max_ring_table_entries); 7080 ctx->vnic_entry_size = le16_to_cpu(resp->vnic_entry_size); 7081 ctx->stat_max_entries = le32_to_cpu(resp->stat_max_entries); 7082 ctx->stat_entry_size = le16_to_cpu(resp->stat_entry_size); 7083 ctx->tqm_entry_size = le16_to_cpu(resp->tqm_entry_size); 7084 ctx->tqm_min_entries_per_ring = 7085 le32_to_cpu(resp->tqm_min_entries_per_ring); 7086 ctx->tqm_max_entries_per_ring = 7087 le32_to_cpu(resp->tqm_max_entries_per_ring); 7088 ctx->tqm_entries_multiple = resp->tqm_entries_multiple; 7089 if (!ctx->tqm_entries_multiple) 7090 ctx->tqm_entries_multiple = 1; 7091 ctx->mrav_max_entries = le32_to_cpu(resp->mrav_max_entries); 7092 ctx->mrav_entry_size = le16_to_cpu(resp->mrav_entry_size); 7093 ctx->mrav_num_entries_units = 7094 le16_to_cpu(resp->mrav_num_entries_units); 7095 ctx->tim_entry_size = le16_to_cpu(resp->tim_entry_size); 7096 ctx->tim_max_entries = le32_to_cpu(resp->tim_max_entries); 7097 7098 bnxt_init_ctx_initializer(ctx, resp); 7099 7100 ctx->tqm_fp_rings_count = resp->tqm_fp_rings_count; 7101 if (!ctx->tqm_fp_rings_count) 7102 ctx->tqm_fp_rings_count = bp->max_q; 7103 else if (ctx->tqm_fp_rings_count > BNXT_MAX_TQM_FP_RINGS) 7104 ctx->tqm_fp_rings_count = BNXT_MAX_TQM_FP_RINGS; 7105 7106 tqm_rings = ctx->tqm_fp_rings_count + BNXT_MAX_TQM_SP_RINGS; 7107 ctx_pg = kcalloc(tqm_rings, sizeof(*ctx_pg), GFP_KERNEL); 7108 if (!ctx_pg) { 7109 kfree(ctx); 7110 rc = -ENOMEM; 7111 goto ctx_err; 7112 } 7113 for (i = 0; i < tqm_rings; i++, ctx_pg++) 7114 ctx->tqm_mem[i] = ctx_pg; 7115 bp->ctx = ctx; 7116 } else { 7117 rc = 0; 7118 } 7119 ctx_err: 7120 hwrm_req_drop(bp, req); 7121 return rc; 7122 } 7123 7124 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem, u8 *pg_attr, 7125 __le64 *pg_dir) 7126 { 7127 if (!rmem->nr_pages) 7128 return; 7129 7130 BNXT_SET_CTX_PAGE_ATTR(*pg_attr); 7131 if (rmem->depth >= 1) { 7132 if (rmem->depth == 2) 7133 *pg_attr |= 2; 7134 else 7135 *pg_attr |= 1; 7136 *pg_dir = cpu_to_le64(rmem->pg_tbl_map); 7137 } else { 7138 *pg_dir = cpu_to_le64(rmem->dma_arr[0]); 7139 } 7140 } 7141 7142 #define FUNC_BACKING_STORE_CFG_REQ_DFLT_ENABLES \ 7143 (FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP | \ 7144 FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ | \ 7145 FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ | \ 7146 FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC | \ 7147 FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT) 7148 7149 static int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, u32 enables) 7150 { 7151 struct hwrm_func_backing_store_cfg_input *req; 7152 struct bnxt_ctx_mem_info *ctx = bp->ctx; 7153 struct bnxt_ctx_pg_info *ctx_pg; 7154 void **__req = (void **)&req; 7155 u32 req_len = sizeof(*req); 7156 __le32 *num_entries; 7157 __le64 *pg_dir; 7158 u32 flags = 0; 7159 u8 *pg_attr; 7160 u32 ena; 7161 int rc; 7162 int i; 7163 7164 if (!ctx) 7165 return 0; 7166 7167 if (req_len > bp->hwrm_max_ext_req_len) 7168 req_len = BNXT_BACKING_STORE_CFG_LEGACY_LEN; 7169 rc = __hwrm_req_init(bp, __req, HWRM_FUNC_BACKING_STORE_CFG, req_len); 7170 if (rc) 7171 return rc; 7172 7173 req->enables = cpu_to_le32(enables); 7174 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP) { 7175 ctx_pg = &ctx->qp_mem; 7176 req->qp_num_entries = cpu_to_le32(ctx_pg->entries); 7177 req->qp_num_qp1_entries = cpu_to_le16(ctx->qp_min_qp1_entries); 7178 req->qp_num_l2_entries = cpu_to_le16(ctx->qp_max_l2_entries); 7179 req->qp_entry_size = cpu_to_le16(ctx->qp_entry_size); 7180 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, 7181 &req->qpc_pg_size_qpc_lvl, 7182 &req->qpc_page_dir); 7183 } 7184 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ) { 7185 ctx_pg = &ctx->srq_mem; 7186 req->srq_num_entries = cpu_to_le32(ctx_pg->entries); 7187 req->srq_num_l2_entries = cpu_to_le16(ctx->srq_max_l2_entries); 7188 req->srq_entry_size = cpu_to_le16(ctx->srq_entry_size); 7189 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, 7190 &req->srq_pg_size_srq_lvl, 7191 &req->srq_page_dir); 7192 } 7193 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ) { 7194 ctx_pg = &ctx->cq_mem; 7195 req->cq_num_entries = cpu_to_le32(ctx_pg->entries); 7196 req->cq_num_l2_entries = cpu_to_le16(ctx->cq_max_l2_entries); 7197 req->cq_entry_size = cpu_to_le16(ctx->cq_entry_size); 7198 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, 7199 &req->cq_pg_size_cq_lvl, 7200 &req->cq_page_dir); 7201 } 7202 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC) { 7203 ctx_pg = &ctx->vnic_mem; 7204 req->vnic_num_vnic_entries = 7205 cpu_to_le16(ctx->vnic_max_vnic_entries); 7206 req->vnic_num_ring_table_entries = 7207 cpu_to_le16(ctx->vnic_max_ring_table_entries); 7208 req->vnic_entry_size = cpu_to_le16(ctx->vnic_entry_size); 7209 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, 7210 &req->vnic_pg_size_vnic_lvl, 7211 &req->vnic_page_dir); 7212 } 7213 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT) { 7214 ctx_pg = &ctx->stat_mem; 7215 req->stat_num_entries = cpu_to_le32(ctx->stat_max_entries); 7216 req->stat_entry_size = cpu_to_le16(ctx->stat_entry_size); 7217 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, 7218 &req->stat_pg_size_stat_lvl, 7219 &req->stat_page_dir); 7220 } 7221 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV) { 7222 ctx_pg = &ctx->mrav_mem; 7223 req->mrav_num_entries = cpu_to_le32(ctx_pg->entries); 7224 if (ctx->mrav_num_entries_units) 7225 flags |= 7226 FUNC_BACKING_STORE_CFG_REQ_FLAGS_MRAV_RESERVATION_SPLIT; 7227 req->mrav_entry_size = cpu_to_le16(ctx->mrav_entry_size); 7228 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, 7229 &req->mrav_pg_size_mrav_lvl, 7230 &req->mrav_page_dir); 7231 } 7232 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM) { 7233 ctx_pg = &ctx->tim_mem; 7234 req->tim_num_entries = cpu_to_le32(ctx_pg->entries); 7235 req->tim_entry_size = cpu_to_le16(ctx->tim_entry_size); 7236 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, 7237 &req->tim_pg_size_tim_lvl, 7238 &req->tim_page_dir); 7239 } 7240 for (i = 0, num_entries = &req->tqm_sp_num_entries, 7241 pg_attr = &req->tqm_sp_pg_size_tqm_sp_lvl, 7242 pg_dir = &req->tqm_sp_page_dir, 7243 ena = FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP; 7244 i < BNXT_MAX_TQM_RINGS; 7245 i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) { 7246 if (!(enables & ena)) 7247 continue; 7248 7249 req->tqm_entry_size = cpu_to_le16(ctx->tqm_entry_size); 7250 ctx_pg = ctx->tqm_mem[i]; 7251 *num_entries = cpu_to_le32(ctx_pg->entries); 7252 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir); 7253 } 7254 req->flags = cpu_to_le32(flags); 7255 return hwrm_req_send(bp, req); 7256 } 7257 7258 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp, 7259 struct bnxt_ctx_pg_info *ctx_pg) 7260 { 7261 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem; 7262 7263 rmem->page_size = BNXT_PAGE_SIZE; 7264 rmem->pg_arr = ctx_pg->ctx_pg_arr; 7265 rmem->dma_arr = ctx_pg->ctx_dma_arr; 7266 rmem->flags = BNXT_RMEM_VALID_PTE_FLAG; 7267 if (rmem->depth >= 1) 7268 rmem->flags |= BNXT_RMEM_USE_FULL_PAGE_FLAG; 7269 return bnxt_alloc_ring(bp, rmem); 7270 } 7271 7272 static int bnxt_alloc_ctx_pg_tbls(struct bnxt *bp, 7273 struct bnxt_ctx_pg_info *ctx_pg, u32 mem_size, 7274 u8 depth, struct bnxt_mem_init *mem_init) 7275 { 7276 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem; 7277 int rc; 7278 7279 if (!mem_size) 7280 return -EINVAL; 7281 7282 ctx_pg->nr_pages = DIV_ROUND_UP(mem_size, BNXT_PAGE_SIZE); 7283 if (ctx_pg->nr_pages > MAX_CTX_TOTAL_PAGES) { 7284 ctx_pg->nr_pages = 0; 7285 return -EINVAL; 7286 } 7287 if (ctx_pg->nr_pages > MAX_CTX_PAGES || depth > 1) { 7288 int nr_tbls, i; 7289 7290 rmem->depth = 2; 7291 ctx_pg->ctx_pg_tbl = kcalloc(MAX_CTX_PAGES, sizeof(ctx_pg), 7292 GFP_KERNEL); 7293 if (!ctx_pg->ctx_pg_tbl) 7294 return -ENOMEM; 7295 nr_tbls = DIV_ROUND_UP(ctx_pg->nr_pages, MAX_CTX_PAGES); 7296 rmem->nr_pages = nr_tbls; 7297 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg); 7298 if (rc) 7299 return rc; 7300 for (i = 0; i < nr_tbls; i++) { 7301 struct bnxt_ctx_pg_info *pg_tbl; 7302 7303 pg_tbl = kzalloc(sizeof(*pg_tbl), GFP_KERNEL); 7304 if (!pg_tbl) 7305 return -ENOMEM; 7306 ctx_pg->ctx_pg_tbl[i] = pg_tbl; 7307 rmem = &pg_tbl->ring_mem; 7308 rmem->pg_tbl = ctx_pg->ctx_pg_arr[i]; 7309 rmem->pg_tbl_map = ctx_pg->ctx_dma_arr[i]; 7310 rmem->depth = 1; 7311 rmem->nr_pages = MAX_CTX_PAGES; 7312 rmem->mem_init = mem_init; 7313 if (i == (nr_tbls - 1)) { 7314 int rem = ctx_pg->nr_pages % MAX_CTX_PAGES; 7315 7316 if (rem) 7317 rmem->nr_pages = rem; 7318 } 7319 rc = bnxt_alloc_ctx_mem_blk(bp, pg_tbl); 7320 if (rc) 7321 break; 7322 } 7323 } else { 7324 rmem->nr_pages = DIV_ROUND_UP(mem_size, BNXT_PAGE_SIZE); 7325 if (rmem->nr_pages > 1 || depth) 7326 rmem->depth = 1; 7327 rmem->mem_init = mem_init; 7328 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg); 7329 } 7330 return rc; 7331 } 7332 7333 static void bnxt_free_ctx_pg_tbls(struct bnxt *bp, 7334 struct bnxt_ctx_pg_info *ctx_pg) 7335 { 7336 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem; 7337 7338 if (rmem->depth > 1 || ctx_pg->nr_pages > MAX_CTX_PAGES || 7339 ctx_pg->ctx_pg_tbl) { 7340 int i, nr_tbls = rmem->nr_pages; 7341 7342 for (i = 0; i < nr_tbls; i++) { 7343 struct bnxt_ctx_pg_info *pg_tbl; 7344 struct bnxt_ring_mem_info *rmem2; 7345 7346 pg_tbl = ctx_pg->ctx_pg_tbl[i]; 7347 if (!pg_tbl) 7348 continue; 7349 rmem2 = &pg_tbl->ring_mem; 7350 bnxt_free_ring(bp, rmem2); 7351 ctx_pg->ctx_pg_arr[i] = NULL; 7352 kfree(pg_tbl); 7353 ctx_pg->ctx_pg_tbl[i] = NULL; 7354 } 7355 kfree(ctx_pg->ctx_pg_tbl); 7356 ctx_pg->ctx_pg_tbl = NULL; 7357 } 7358 bnxt_free_ring(bp, rmem); 7359 ctx_pg->nr_pages = 0; 7360 } 7361 7362 void bnxt_free_ctx_mem(struct bnxt *bp) 7363 { 7364 struct bnxt_ctx_mem_info *ctx = bp->ctx; 7365 int i; 7366 7367 if (!ctx) 7368 return; 7369 7370 if (ctx->tqm_mem[0]) { 7371 for (i = 0; i < ctx->tqm_fp_rings_count + 1; i++) 7372 bnxt_free_ctx_pg_tbls(bp, ctx->tqm_mem[i]); 7373 kfree(ctx->tqm_mem[0]); 7374 ctx->tqm_mem[0] = NULL; 7375 } 7376 7377 bnxt_free_ctx_pg_tbls(bp, &ctx->tim_mem); 7378 bnxt_free_ctx_pg_tbls(bp, &ctx->mrav_mem); 7379 bnxt_free_ctx_pg_tbls(bp, &ctx->stat_mem); 7380 bnxt_free_ctx_pg_tbls(bp, &ctx->vnic_mem); 7381 bnxt_free_ctx_pg_tbls(bp, &ctx->cq_mem); 7382 bnxt_free_ctx_pg_tbls(bp, &ctx->srq_mem); 7383 bnxt_free_ctx_pg_tbls(bp, &ctx->qp_mem); 7384 ctx->flags &= ~BNXT_CTX_FLAG_INITED; 7385 } 7386 7387 static int bnxt_alloc_ctx_mem(struct bnxt *bp) 7388 { 7389 struct bnxt_ctx_pg_info *ctx_pg; 7390 struct bnxt_ctx_mem_info *ctx; 7391 struct bnxt_mem_init *init; 7392 u32 mem_size, ena, entries; 7393 u32 entries_sp, min; 7394 u32 num_mr, num_ah; 7395 u32 extra_srqs = 0; 7396 u32 extra_qps = 0; 7397 u8 pg_lvl = 1; 7398 int i, rc; 7399 7400 rc = bnxt_hwrm_func_backing_store_qcaps(bp); 7401 if (rc) { 7402 netdev_err(bp->dev, "Failed querying context mem capability, rc = %d.\n", 7403 rc); 7404 return rc; 7405 } 7406 ctx = bp->ctx; 7407 if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED)) 7408 return 0; 7409 7410 if ((bp->flags & BNXT_FLAG_ROCE_CAP) && !is_kdump_kernel()) { 7411 pg_lvl = 2; 7412 extra_qps = 65536; 7413 extra_srqs = 8192; 7414 } 7415 7416 ctx_pg = &ctx->qp_mem; 7417 ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries + 7418 extra_qps; 7419 if (ctx->qp_entry_size) { 7420 mem_size = ctx->qp_entry_size * ctx_pg->entries; 7421 init = &ctx->mem_init[BNXT_CTX_MEM_INIT_QP]; 7422 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, pg_lvl, init); 7423 if (rc) 7424 return rc; 7425 } 7426 7427 ctx_pg = &ctx->srq_mem; 7428 ctx_pg->entries = ctx->srq_max_l2_entries + extra_srqs; 7429 if (ctx->srq_entry_size) { 7430 mem_size = ctx->srq_entry_size * ctx_pg->entries; 7431 init = &ctx->mem_init[BNXT_CTX_MEM_INIT_SRQ]; 7432 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, pg_lvl, init); 7433 if (rc) 7434 return rc; 7435 } 7436 7437 ctx_pg = &ctx->cq_mem; 7438 ctx_pg->entries = ctx->cq_max_l2_entries + extra_qps * 2; 7439 if (ctx->cq_entry_size) { 7440 mem_size = ctx->cq_entry_size * ctx_pg->entries; 7441 init = &ctx->mem_init[BNXT_CTX_MEM_INIT_CQ]; 7442 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, pg_lvl, init); 7443 if (rc) 7444 return rc; 7445 } 7446 7447 ctx_pg = &ctx->vnic_mem; 7448 ctx_pg->entries = ctx->vnic_max_vnic_entries + 7449 ctx->vnic_max_ring_table_entries; 7450 if (ctx->vnic_entry_size) { 7451 mem_size = ctx->vnic_entry_size * ctx_pg->entries; 7452 init = &ctx->mem_init[BNXT_CTX_MEM_INIT_VNIC]; 7453 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1, init); 7454 if (rc) 7455 return rc; 7456 } 7457 7458 ctx_pg = &ctx->stat_mem; 7459 ctx_pg->entries = ctx->stat_max_entries; 7460 if (ctx->stat_entry_size) { 7461 mem_size = ctx->stat_entry_size * ctx_pg->entries; 7462 init = &ctx->mem_init[BNXT_CTX_MEM_INIT_STAT]; 7463 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1, init); 7464 if (rc) 7465 return rc; 7466 } 7467 7468 ena = 0; 7469 if (!(bp->flags & BNXT_FLAG_ROCE_CAP)) 7470 goto skip_rdma; 7471 7472 ctx_pg = &ctx->mrav_mem; 7473 /* 128K extra is needed to accommodate static AH context 7474 * allocation by f/w. 7475 */ 7476 num_mr = 1024 * 256; 7477 num_ah = 1024 * 128; 7478 ctx_pg->entries = num_mr + num_ah; 7479 if (ctx->mrav_entry_size) { 7480 mem_size = ctx->mrav_entry_size * ctx_pg->entries; 7481 init = &ctx->mem_init[BNXT_CTX_MEM_INIT_MRAV]; 7482 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 2, init); 7483 if (rc) 7484 return rc; 7485 } 7486 ena = FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV; 7487 if (ctx->mrav_num_entries_units) 7488 ctx_pg->entries = 7489 ((num_mr / ctx->mrav_num_entries_units) << 16) | 7490 (num_ah / ctx->mrav_num_entries_units); 7491 7492 ctx_pg = &ctx->tim_mem; 7493 ctx_pg->entries = ctx->qp_mem.entries; 7494 if (ctx->tim_entry_size) { 7495 mem_size = ctx->tim_entry_size * ctx_pg->entries; 7496 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1, NULL); 7497 if (rc) 7498 return rc; 7499 } 7500 ena |= FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM; 7501 7502 skip_rdma: 7503 min = ctx->tqm_min_entries_per_ring; 7504 entries_sp = ctx->vnic_max_vnic_entries + ctx->qp_max_l2_entries + 7505 2 * (extra_qps + ctx->qp_min_qp1_entries) + min; 7506 entries_sp = roundup(entries_sp, ctx->tqm_entries_multiple); 7507 entries = ctx->qp_max_l2_entries + 2 * (extra_qps + ctx->qp_min_qp1_entries); 7508 entries = roundup(entries, ctx->tqm_entries_multiple); 7509 entries = clamp_t(u32, entries, min, ctx->tqm_max_entries_per_ring); 7510 for (i = 0; i < ctx->tqm_fp_rings_count + 1; i++) { 7511 ctx_pg = ctx->tqm_mem[i]; 7512 ctx_pg->entries = i ? entries : entries_sp; 7513 if (ctx->tqm_entry_size) { 7514 mem_size = ctx->tqm_entry_size * ctx_pg->entries; 7515 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1, 7516 NULL); 7517 if (rc) 7518 return rc; 7519 } 7520 ena |= FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP << i; 7521 } 7522 ena |= FUNC_BACKING_STORE_CFG_REQ_DFLT_ENABLES; 7523 rc = bnxt_hwrm_func_backing_store_cfg(bp, ena); 7524 if (rc) { 7525 netdev_err(bp->dev, "Failed configuring context mem, rc = %d.\n", 7526 rc); 7527 return rc; 7528 } 7529 ctx->flags |= BNXT_CTX_FLAG_INITED; 7530 return 0; 7531 } 7532 7533 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp, bool all) 7534 { 7535 struct hwrm_func_resource_qcaps_output *resp; 7536 struct hwrm_func_resource_qcaps_input *req; 7537 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 7538 int rc; 7539 7540 rc = hwrm_req_init(bp, req, HWRM_FUNC_RESOURCE_QCAPS); 7541 if (rc) 7542 return rc; 7543 7544 req->fid = cpu_to_le16(0xffff); 7545 resp = hwrm_req_hold(bp, req); 7546 rc = hwrm_req_send_silent(bp, req); 7547 if (rc) 7548 goto hwrm_func_resc_qcaps_exit; 7549 7550 hw_resc->max_tx_sch_inputs = le16_to_cpu(resp->max_tx_scheduler_inputs); 7551 if (!all) 7552 goto hwrm_func_resc_qcaps_exit; 7553 7554 hw_resc->min_rsscos_ctxs = le16_to_cpu(resp->min_rsscos_ctx); 7555 hw_resc->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx); 7556 hw_resc->min_cp_rings = le16_to_cpu(resp->min_cmpl_rings); 7557 hw_resc->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings); 7558 hw_resc->min_tx_rings = le16_to_cpu(resp->min_tx_rings); 7559 hw_resc->max_tx_rings = le16_to_cpu(resp->max_tx_rings); 7560 hw_resc->min_rx_rings = le16_to_cpu(resp->min_rx_rings); 7561 hw_resc->max_rx_rings = le16_to_cpu(resp->max_rx_rings); 7562 hw_resc->min_hw_ring_grps = le16_to_cpu(resp->min_hw_ring_grps); 7563 hw_resc->max_hw_ring_grps = le16_to_cpu(resp->max_hw_ring_grps); 7564 hw_resc->min_l2_ctxs = le16_to_cpu(resp->min_l2_ctxs); 7565 hw_resc->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs); 7566 hw_resc->min_vnics = le16_to_cpu(resp->min_vnics); 7567 hw_resc->max_vnics = le16_to_cpu(resp->max_vnics); 7568 hw_resc->min_stat_ctxs = le16_to_cpu(resp->min_stat_ctx); 7569 hw_resc->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx); 7570 7571 if (bp->flags & BNXT_FLAG_CHIP_P5) { 7572 u16 max_msix = le16_to_cpu(resp->max_msix); 7573 7574 hw_resc->max_nqs = max_msix; 7575 hw_resc->max_hw_ring_grps = hw_resc->max_rx_rings; 7576 } 7577 7578 if (BNXT_PF(bp)) { 7579 struct bnxt_pf_info *pf = &bp->pf; 7580 7581 pf->vf_resv_strategy = 7582 le16_to_cpu(resp->vf_reservation_strategy); 7583 if (pf->vf_resv_strategy > BNXT_VF_RESV_STRATEGY_MINIMAL_STATIC) 7584 pf->vf_resv_strategy = BNXT_VF_RESV_STRATEGY_MAXIMAL; 7585 } 7586 hwrm_func_resc_qcaps_exit: 7587 hwrm_req_drop(bp, req); 7588 return rc; 7589 } 7590 7591 static int __bnxt_hwrm_ptp_qcfg(struct bnxt *bp) 7592 { 7593 struct hwrm_port_mac_ptp_qcfg_output *resp; 7594 struct hwrm_port_mac_ptp_qcfg_input *req; 7595 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 7596 bool phc_cfg; 7597 u8 flags; 7598 int rc; 7599 7600 if (bp->hwrm_spec_code < 0x10801 || !BNXT_CHIP_P5_THOR(bp)) { 7601 rc = -ENODEV; 7602 goto no_ptp; 7603 } 7604 7605 rc = hwrm_req_init(bp, req, HWRM_PORT_MAC_PTP_QCFG); 7606 if (rc) 7607 goto no_ptp; 7608 7609 req->port_id = cpu_to_le16(bp->pf.port_id); 7610 resp = hwrm_req_hold(bp, req); 7611 rc = hwrm_req_send(bp, req); 7612 if (rc) 7613 goto exit; 7614 7615 flags = resp->flags; 7616 if (!(flags & PORT_MAC_PTP_QCFG_RESP_FLAGS_HWRM_ACCESS)) { 7617 rc = -ENODEV; 7618 goto exit; 7619 } 7620 if (!ptp) { 7621 ptp = kzalloc(sizeof(*ptp), GFP_KERNEL); 7622 if (!ptp) { 7623 rc = -ENOMEM; 7624 goto exit; 7625 } 7626 ptp->bp = bp; 7627 bp->ptp_cfg = ptp; 7628 } 7629 if (flags & PORT_MAC_PTP_QCFG_RESP_FLAGS_PARTIAL_DIRECT_ACCESS_REF_CLOCK) { 7630 ptp->refclk_regs[0] = le32_to_cpu(resp->ts_ref_clock_reg_lower); 7631 ptp->refclk_regs[1] = le32_to_cpu(resp->ts_ref_clock_reg_upper); 7632 } else if (bp->flags & BNXT_FLAG_CHIP_P5) { 7633 ptp->refclk_regs[0] = BNXT_TS_REG_TIMESYNC_TS0_LOWER; 7634 ptp->refclk_regs[1] = BNXT_TS_REG_TIMESYNC_TS0_UPPER; 7635 } else { 7636 rc = -ENODEV; 7637 goto exit; 7638 } 7639 phc_cfg = (flags & PORT_MAC_PTP_QCFG_RESP_FLAGS_RTC_CONFIGURED) != 0; 7640 rc = bnxt_ptp_init(bp, phc_cfg); 7641 if (rc) 7642 netdev_warn(bp->dev, "PTP initialization failed.\n"); 7643 exit: 7644 hwrm_req_drop(bp, req); 7645 if (!rc) 7646 return 0; 7647 7648 no_ptp: 7649 bnxt_ptp_clear(bp); 7650 kfree(ptp); 7651 bp->ptp_cfg = NULL; 7652 return rc; 7653 } 7654 7655 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp) 7656 { 7657 struct hwrm_func_qcaps_output *resp; 7658 struct hwrm_func_qcaps_input *req; 7659 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 7660 u32 flags, flags_ext, flags_ext2; 7661 int rc; 7662 7663 rc = hwrm_req_init(bp, req, HWRM_FUNC_QCAPS); 7664 if (rc) 7665 return rc; 7666 7667 req->fid = cpu_to_le16(0xffff); 7668 resp = hwrm_req_hold(bp, req); 7669 rc = hwrm_req_send(bp, req); 7670 if (rc) 7671 goto hwrm_func_qcaps_exit; 7672 7673 flags = le32_to_cpu(resp->flags); 7674 if (flags & FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED) 7675 bp->flags |= BNXT_FLAG_ROCEV1_CAP; 7676 if (flags & FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED) 7677 bp->flags |= BNXT_FLAG_ROCEV2_CAP; 7678 if (flags & FUNC_QCAPS_RESP_FLAGS_PCIE_STATS_SUPPORTED) 7679 bp->fw_cap |= BNXT_FW_CAP_PCIE_STATS_SUPPORTED; 7680 if (flags & FUNC_QCAPS_RESP_FLAGS_HOT_RESET_CAPABLE) 7681 bp->fw_cap |= BNXT_FW_CAP_HOT_RESET; 7682 if (flags & FUNC_QCAPS_RESP_FLAGS_EXT_STATS_SUPPORTED) 7683 bp->fw_cap |= BNXT_FW_CAP_EXT_STATS_SUPPORTED; 7684 if (flags & FUNC_QCAPS_RESP_FLAGS_ERROR_RECOVERY_CAPABLE) 7685 bp->fw_cap |= BNXT_FW_CAP_ERROR_RECOVERY; 7686 if (flags & FUNC_QCAPS_RESP_FLAGS_ERR_RECOVER_RELOAD) 7687 bp->fw_cap |= BNXT_FW_CAP_ERR_RECOVER_RELOAD; 7688 if (!(flags & FUNC_QCAPS_RESP_FLAGS_VLAN_ACCELERATION_TX_DISABLED)) 7689 bp->fw_cap |= BNXT_FW_CAP_VLAN_TX_INSERT; 7690 if (flags & FUNC_QCAPS_RESP_FLAGS_DBG_QCAPS_CMD_SUPPORTED) 7691 bp->fw_cap |= BNXT_FW_CAP_DBG_QCAPS; 7692 7693 flags_ext = le32_to_cpu(resp->flags_ext); 7694 if (flags_ext & FUNC_QCAPS_RESP_FLAGS_EXT_EXT_HW_STATS_SUPPORTED) 7695 bp->fw_cap |= BNXT_FW_CAP_EXT_HW_STATS_SUPPORTED; 7696 if (BNXT_PF(bp) && (flags_ext & FUNC_QCAPS_RESP_FLAGS_EXT_PTP_PPS_SUPPORTED)) 7697 bp->fw_cap |= BNXT_FW_CAP_PTP_PPS; 7698 if (flags_ext & FUNC_QCAPS_RESP_FLAGS_EXT_PTP_64BIT_RTC_SUPPORTED) 7699 bp->fw_cap |= BNXT_FW_CAP_PTP_RTC; 7700 if (BNXT_PF(bp) && (flags_ext & FUNC_QCAPS_RESP_FLAGS_EXT_HOT_RESET_IF_SUPPORT)) 7701 bp->fw_cap |= BNXT_FW_CAP_HOT_RESET_IF; 7702 if (BNXT_PF(bp) && (flags_ext & FUNC_QCAPS_RESP_FLAGS_EXT_FW_LIVEPATCH_SUPPORTED)) 7703 bp->fw_cap |= BNXT_FW_CAP_LIVEPATCH; 7704 7705 flags_ext2 = le32_to_cpu(resp->flags_ext2); 7706 if (flags_ext2 & FUNC_QCAPS_RESP_FLAGS_EXT2_RX_ALL_PKTS_TIMESTAMPS_SUPPORTED) 7707 bp->fw_cap |= BNXT_FW_CAP_RX_ALL_PKT_TS; 7708 7709 bp->tx_push_thresh = 0; 7710 if ((flags & FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED) && 7711 BNXT_FW_MAJ(bp) > 217) 7712 bp->tx_push_thresh = BNXT_TX_PUSH_THRESH; 7713 7714 hw_resc->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx); 7715 hw_resc->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings); 7716 hw_resc->max_tx_rings = le16_to_cpu(resp->max_tx_rings); 7717 hw_resc->max_rx_rings = le16_to_cpu(resp->max_rx_rings); 7718 hw_resc->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps); 7719 if (!hw_resc->max_hw_ring_grps) 7720 hw_resc->max_hw_ring_grps = hw_resc->max_tx_rings; 7721 hw_resc->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs); 7722 hw_resc->max_vnics = le16_to_cpu(resp->max_vnics); 7723 hw_resc->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx); 7724 7725 if (BNXT_PF(bp)) { 7726 struct bnxt_pf_info *pf = &bp->pf; 7727 7728 pf->fw_fid = le16_to_cpu(resp->fid); 7729 pf->port_id = le16_to_cpu(resp->port_id); 7730 memcpy(pf->mac_addr, resp->mac_address, ETH_ALEN); 7731 pf->first_vf_id = le16_to_cpu(resp->first_vf_id); 7732 pf->max_vfs = le16_to_cpu(resp->max_vfs); 7733 pf->max_encap_records = le32_to_cpu(resp->max_encap_records); 7734 pf->max_decap_records = le32_to_cpu(resp->max_decap_records); 7735 pf->max_tx_em_flows = le32_to_cpu(resp->max_tx_em_flows); 7736 pf->max_tx_wm_flows = le32_to_cpu(resp->max_tx_wm_flows); 7737 pf->max_rx_em_flows = le32_to_cpu(resp->max_rx_em_flows); 7738 pf->max_rx_wm_flows = le32_to_cpu(resp->max_rx_wm_flows); 7739 bp->flags &= ~BNXT_FLAG_WOL_CAP; 7740 if (flags & FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED) 7741 bp->flags |= BNXT_FLAG_WOL_CAP; 7742 if (flags & FUNC_QCAPS_RESP_FLAGS_PTP_SUPPORTED) { 7743 bp->fw_cap |= BNXT_FW_CAP_PTP; 7744 } else { 7745 bnxt_ptp_clear(bp); 7746 kfree(bp->ptp_cfg); 7747 bp->ptp_cfg = NULL; 7748 } 7749 } else { 7750 #ifdef CONFIG_BNXT_SRIOV 7751 struct bnxt_vf_info *vf = &bp->vf; 7752 7753 vf->fw_fid = le16_to_cpu(resp->fid); 7754 memcpy(vf->mac_addr, resp->mac_address, ETH_ALEN); 7755 #endif 7756 } 7757 7758 hwrm_func_qcaps_exit: 7759 hwrm_req_drop(bp, req); 7760 return rc; 7761 } 7762 7763 static void bnxt_hwrm_dbg_qcaps(struct bnxt *bp) 7764 { 7765 struct hwrm_dbg_qcaps_output *resp; 7766 struct hwrm_dbg_qcaps_input *req; 7767 int rc; 7768 7769 bp->fw_dbg_cap = 0; 7770 if (!(bp->fw_cap & BNXT_FW_CAP_DBG_QCAPS)) 7771 return; 7772 7773 rc = hwrm_req_init(bp, req, HWRM_DBG_QCAPS); 7774 if (rc) 7775 return; 7776 7777 req->fid = cpu_to_le16(0xffff); 7778 resp = hwrm_req_hold(bp, req); 7779 rc = hwrm_req_send(bp, req); 7780 if (rc) 7781 goto hwrm_dbg_qcaps_exit; 7782 7783 bp->fw_dbg_cap = le32_to_cpu(resp->flags); 7784 7785 hwrm_dbg_qcaps_exit: 7786 hwrm_req_drop(bp, req); 7787 } 7788 7789 static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp); 7790 7791 int bnxt_hwrm_func_qcaps(struct bnxt *bp) 7792 { 7793 int rc; 7794 7795 rc = __bnxt_hwrm_func_qcaps(bp); 7796 if (rc) 7797 return rc; 7798 7799 bnxt_hwrm_dbg_qcaps(bp); 7800 7801 rc = bnxt_hwrm_queue_qportcfg(bp); 7802 if (rc) { 7803 netdev_err(bp->dev, "hwrm query qportcfg failure rc: %d\n", rc); 7804 return rc; 7805 } 7806 if (bp->hwrm_spec_code >= 0x10803) { 7807 rc = bnxt_alloc_ctx_mem(bp); 7808 if (rc) 7809 return rc; 7810 rc = bnxt_hwrm_func_resc_qcaps(bp, true); 7811 if (!rc) 7812 bp->fw_cap |= BNXT_FW_CAP_NEW_RM; 7813 } 7814 return 0; 7815 } 7816 7817 static int bnxt_hwrm_cfa_adv_flow_mgnt_qcaps(struct bnxt *bp) 7818 { 7819 struct hwrm_cfa_adv_flow_mgnt_qcaps_output *resp; 7820 struct hwrm_cfa_adv_flow_mgnt_qcaps_input *req; 7821 u32 flags; 7822 int rc; 7823 7824 if (!(bp->fw_cap & BNXT_FW_CAP_CFA_ADV_FLOW)) 7825 return 0; 7826 7827 rc = hwrm_req_init(bp, req, HWRM_CFA_ADV_FLOW_MGNT_QCAPS); 7828 if (rc) 7829 return rc; 7830 7831 resp = hwrm_req_hold(bp, req); 7832 rc = hwrm_req_send(bp, req); 7833 if (rc) 7834 goto hwrm_cfa_adv_qcaps_exit; 7835 7836 flags = le32_to_cpu(resp->flags); 7837 if (flags & 7838 CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RFS_RING_TBL_IDX_V2_SUPPORTED) 7839 bp->fw_cap |= BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V2; 7840 7841 hwrm_cfa_adv_qcaps_exit: 7842 hwrm_req_drop(bp, req); 7843 return rc; 7844 } 7845 7846 static int __bnxt_alloc_fw_health(struct bnxt *bp) 7847 { 7848 if (bp->fw_health) 7849 return 0; 7850 7851 bp->fw_health = kzalloc(sizeof(*bp->fw_health), GFP_KERNEL); 7852 if (!bp->fw_health) 7853 return -ENOMEM; 7854 7855 mutex_init(&bp->fw_health->lock); 7856 return 0; 7857 } 7858 7859 static int bnxt_alloc_fw_health(struct bnxt *bp) 7860 { 7861 int rc; 7862 7863 if (!(bp->fw_cap & BNXT_FW_CAP_HOT_RESET) && 7864 !(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)) 7865 return 0; 7866 7867 rc = __bnxt_alloc_fw_health(bp); 7868 if (rc) { 7869 bp->fw_cap &= ~BNXT_FW_CAP_HOT_RESET; 7870 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY; 7871 return rc; 7872 } 7873 7874 return 0; 7875 } 7876 7877 static void __bnxt_map_fw_health_reg(struct bnxt *bp, u32 reg) 7878 { 7879 writel(reg & BNXT_GRC_BASE_MASK, bp->bar0 + 7880 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 7881 BNXT_FW_HEALTH_WIN_MAP_OFF); 7882 } 7883 7884 static void bnxt_inv_fw_health_reg(struct bnxt *bp) 7885 { 7886 struct bnxt_fw_health *fw_health = bp->fw_health; 7887 u32 reg_type; 7888 7889 if (!fw_health) 7890 return; 7891 7892 reg_type = BNXT_FW_HEALTH_REG_TYPE(fw_health->regs[BNXT_FW_HEALTH_REG]); 7893 if (reg_type == BNXT_FW_HEALTH_REG_TYPE_GRC) 7894 fw_health->status_reliable = false; 7895 7896 reg_type = BNXT_FW_HEALTH_REG_TYPE(fw_health->regs[BNXT_FW_RESET_CNT_REG]); 7897 if (reg_type == BNXT_FW_HEALTH_REG_TYPE_GRC) 7898 fw_health->resets_reliable = false; 7899 } 7900 7901 static void bnxt_try_map_fw_health_reg(struct bnxt *bp) 7902 { 7903 void __iomem *hs; 7904 u32 status_loc; 7905 u32 reg_type; 7906 u32 sig; 7907 7908 if (bp->fw_health) 7909 bp->fw_health->status_reliable = false; 7910 7911 __bnxt_map_fw_health_reg(bp, HCOMM_STATUS_STRUCT_LOC); 7912 hs = bp->bar0 + BNXT_FW_HEALTH_WIN_OFF(HCOMM_STATUS_STRUCT_LOC); 7913 7914 sig = readl(hs + offsetof(struct hcomm_status, sig_ver)); 7915 if ((sig & HCOMM_STATUS_SIGNATURE_MASK) != HCOMM_STATUS_SIGNATURE_VAL) { 7916 if (!bp->chip_num) { 7917 __bnxt_map_fw_health_reg(bp, BNXT_GRC_REG_BASE); 7918 bp->chip_num = readl(bp->bar0 + 7919 BNXT_FW_HEALTH_WIN_BASE + 7920 BNXT_GRC_REG_CHIP_NUM); 7921 } 7922 if (!BNXT_CHIP_P5(bp)) 7923 return; 7924 7925 status_loc = BNXT_GRC_REG_STATUS_P5 | 7926 BNXT_FW_HEALTH_REG_TYPE_BAR0; 7927 } else { 7928 status_loc = readl(hs + offsetof(struct hcomm_status, 7929 fw_status_loc)); 7930 } 7931 7932 if (__bnxt_alloc_fw_health(bp)) { 7933 netdev_warn(bp->dev, "no memory for firmware status checks\n"); 7934 return; 7935 } 7936 7937 bp->fw_health->regs[BNXT_FW_HEALTH_REG] = status_loc; 7938 reg_type = BNXT_FW_HEALTH_REG_TYPE(status_loc); 7939 if (reg_type == BNXT_FW_HEALTH_REG_TYPE_GRC) { 7940 __bnxt_map_fw_health_reg(bp, status_loc); 7941 bp->fw_health->mapped_regs[BNXT_FW_HEALTH_REG] = 7942 BNXT_FW_HEALTH_WIN_OFF(status_loc); 7943 } 7944 7945 bp->fw_health->status_reliable = true; 7946 } 7947 7948 static int bnxt_map_fw_health_regs(struct bnxt *bp) 7949 { 7950 struct bnxt_fw_health *fw_health = bp->fw_health; 7951 u32 reg_base = 0xffffffff; 7952 int i; 7953 7954 bp->fw_health->status_reliable = false; 7955 bp->fw_health->resets_reliable = false; 7956 /* Only pre-map the monitoring GRC registers using window 3 */ 7957 for (i = 0; i < 4; i++) { 7958 u32 reg = fw_health->regs[i]; 7959 7960 if (BNXT_FW_HEALTH_REG_TYPE(reg) != BNXT_FW_HEALTH_REG_TYPE_GRC) 7961 continue; 7962 if (reg_base == 0xffffffff) 7963 reg_base = reg & BNXT_GRC_BASE_MASK; 7964 if ((reg & BNXT_GRC_BASE_MASK) != reg_base) 7965 return -ERANGE; 7966 fw_health->mapped_regs[i] = BNXT_FW_HEALTH_WIN_OFF(reg); 7967 } 7968 bp->fw_health->status_reliable = true; 7969 bp->fw_health->resets_reliable = true; 7970 if (reg_base == 0xffffffff) 7971 return 0; 7972 7973 __bnxt_map_fw_health_reg(bp, reg_base); 7974 return 0; 7975 } 7976 7977 static void bnxt_remap_fw_health_regs(struct bnxt *bp) 7978 { 7979 if (!bp->fw_health) 7980 return; 7981 7982 if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY) { 7983 bp->fw_health->status_reliable = true; 7984 bp->fw_health->resets_reliable = true; 7985 } else { 7986 bnxt_try_map_fw_health_reg(bp); 7987 } 7988 } 7989 7990 static int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp) 7991 { 7992 struct bnxt_fw_health *fw_health = bp->fw_health; 7993 struct hwrm_error_recovery_qcfg_output *resp; 7994 struct hwrm_error_recovery_qcfg_input *req; 7995 int rc, i; 7996 7997 if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)) 7998 return 0; 7999 8000 rc = hwrm_req_init(bp, req, HWRM_ERROR_RECOVERY_QCFG); 8001 if (rc) 8002 return rc; 8003 8004 resp = hwrm_req_hold(bp, req); 8005 rc = hwrm_req_send(bp, req); 8006 if (rc) 8007 goto err_recovery_out; 8008 fw_health->flags = le32_to_cpu(resp->flags); 8009 if ((fw_health->flags & ERROR_RECOVERY_QCFG_RESP_FLAGS_CO_CPU) && 8010 !(bp->fw_cap & BNXT_FW_CAP_KONG_MB_CHNL)) { 8011 rc = -EINVAL; 8012 goto err_recovery_out; 8013 } 8014 fw_health->polling_dsecs = le32_to_cpu(resp->driver_polling_freq); 8015 fw_health->master_func_wait_dsecs = 8016 le32_to_cpu(resp->master_func_wait_period); 8017 fw_health->normal_func_wait_dsecs = 8018 le32_to_cpu(resp->normal_func_wait_period); 8019 fw_health->post_reset_wait_dsecs = 8020 le32_to_cpu(resp->master_func_wait_period_after_reset); 8021 fw_health->post_reset_max_wait_dsecs = 8022 le32_to_cpu(resp->max_bailout_time_after_reset); 8023 fw_health->regs[BNXT_FW_HEALTH_REG] = 8024 le32_to_cpu(resp->fw_health_status_reg); 8025 fw_health->regs[BNXT_FW_HEARTBEAT_REG] = 8026 le32_to_cpu(resp->fw_heartbeat_reg); 8027 fw_health->regs[BNXT_FW_RESET_CNT_REG] = 8028 le32_to_cpu(resp->fw_reset_cnt_reg); 8029 fw_health->regs[BNXT_FW_RESET_INPROG_REG] = 8030 le32_to_cpu(resp->reset_inprogress_reg); 8031 fw_health->fw_reset_inprog_reg_mask = 8032 le32_to_cpu(resp->reset_inprogress_reg_mask); 8033 fw_health->fw_reset_seq_cnt = resp->reg_array_cnt; 8034 if (fw_health->fw_reset_seq_cnt >= 16) { 8035 rc = -EINVAL; 8036 goto err_recovery_out; 8037 } 8038 for (i = 0; i < fw_health->fw_reset_seq_cnt; i++) { 8039 fw_health->fw_reset_seq_regs[i] = 8040 le32_to_cpu(resp->reset_reg[i]); 8041 fw_health->fw_reset_seq_vals[i] = 8042 le32_to_cpu(resp->reset_reg_val[i]); 8043 fw_health->fw_reset_seq_delay_msec[i] = 8044 resp->delay_after_reset[i]; 8045 } 8046 err_recovery_out: 8047 hwrm_req_drop(bp, req); 8048 if (!rc) 8049 rc = bnxt_map_fw_health_regs(bp); 8050 if (rc) 8051 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY; 8052 return rc; 8053 } 8054 8055 static int bnxt_hwrm_func_reset(struct bnxt *bp) 8056 { 8057 struct hwrm_func_reset_input *req; 8058 int rc; 8059 8060 rc = hwrm_req_init(bp, req, HWRM_FUNC_RESET); 8061 if (rc) 8062 return rc; 8063 8064 req->enables = 0; 8065 hwrm_req_timeout(bp, req, HWRM_RESET_TIMEOUT); 8066 return hwrm_req_send(bp, req); 8067 } 8068 8069 static void bnxt_nvm_cfg_ver_get(struct bnxt *bp) 8070 { 8071 struct hwrm_nvm_get_dev_info_output nvm_info; 8072 8073 if (!bnxt_hwrm_nvm_get_dev_info(bp, &nvm_info)) 8074 snprintf(bp->nvm_cfg_ver, FW_VER_STR_LEN, "%d.%d.%d", 8075 nvm_info.nvm_cfg_ver_maj, nvm_info.nvm_cfg_ver_min, 8076 nvm_info.nvm_cfg_ver_upd); 8077 } 8078 8079 static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp) 8080 { 8081 struct hwrm_queue_qportcfg_output *resp; 8082 struct hwrm_queue_qportcfg_input *req; 8083 u8 i, j, *qptr; 8084 bool no_rdma; 8085 int rc = 0; 8086 8087 rc = hwrm_req_init(bp, req, HWRM_QUEUE_QPORTCFG); 8088 if (rc) 8089 return rc; 8090 8091 resp = hwrm_req_hold(bp, req); 8092 rc = hwrm_req_send(bp, req); 8093 if (rc) 8094 goto qportcfg_exit; 8095 8096 if (!resp->max_configurable_queues) { 8097 rc = -EINVAL; 8098 goto qportcfg_exit; 8099 } 8100 bp->max_tc = resp->max_configurable_queues; 8101 bp->max_lltc = resp->max_configurable_lossless_queues; 8102 if (bp->max_tc > BNXT_MAX_QUEUE) 8103 bp->max_tc = BNXT_MAX_QUEUE; 8104 8105 no_rdma = !(bp->flags & BNXT_FLAG_ROCE_CAP); 8106 qptr = &resp->queue_id0; 8107 for (i = 0, j = 0; i < bp->max_tc; i++) { 8108 bp->q_info[j].queue_id = *qptr; 8109 bp->q_ids[i] = *qptr++; 8110 bp->q_info[j].queue_profile = *qptr++; 8111 bp->tc_to_qidx[j] = j; 8112 if (!BNXT_CNPQ(bp->q_info[j].queue_profile) || 8113 (no_rdma && BNXT_PF(bp))) 8114 j++; 8115 } 8116 bp->max_q = bp->max_tc; 8117 bp->max_tc = max_t(u8, j, 1); 8118 8119 if (resp->queue_cfg_info & QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG) 8120 bp->max_tc = 1; 8121 8122 if (bp->max_lltc > bp->max_tc) 8123 bp->max_lltc = bp->max_tc; 8124 8125 qportcfg_exit: 8126 hwrm_req_drop(bp, req); 8127 return rc; 8128 } 8129 8130 static int bnxt_hwrm_poll(struct bnxt *bp) 8131 { 8132 struct hwrm_ver_get_input *req; 8133 int rc; 8134 8135 rc = hwrm_req_init(bp, req, HWRM_VER_GET); 8136 if (rc) 8137 return rc; 8138 8139 req->hwrm_intf_maj = HWRM_VERSION_MAJOR; 8140 req->hwrm_intf_min = HWRM_VERSION_MINOR; 8141 req->hwrm_intf_upd = HWRM_VERSION_UPDATE; 8142 8143 hwrm_req_flags(bp, req, BNXT_HWRM_CTX_SILENT | BNXT_HWRM_FULL_WAIT); 8144 rc = hwrm_req_send(bp, req); 8145 return rc; 8146 } 8147 8148 static int bnxt_hwrm_ver_get(struct bnxt *bp) 8149 { 8150 struct hwrm_ver_get_output *resp; 8151 struct hwrm_ver_get_input *req; 8152 u16 fw_maj, fw_min, fw_bld, fw_rsv; 8153 u32 dev_caps_cfg, hwrm_ver; 8154 int rc, len; 8155 8156 rc = hwrm_req_init(bp, req, HWRM_VER_GET); 8157 if (rc) 8158 return rc; 8159 8160 hwrm_req_flags(bp, req, BNXT_HWRM_FULL_WAIT); 8161 bp->hwrm_max_req_len = HWRM_MAX_REQ_LEN; 8162 req->hwrm_intf_maj = HWRM_VERSION_MAJOR; 8163 req->hwrm_intf_min = HWRM_VERSION_MINOR; 8164 req->hwrm_intf_upd = HWRM_VERSION_UPDATE; 8165 8166 resp = hwrm_req_hold(bp, req); 8167 rc = hwrm_req_send(bp, req); 8168 if (rc) 8169 goto hwrm_ver_get_exit; 8170 8171 memcpy(&bp->ver_resp, resp, sizeof(struct hwrm_ver_get_output)); 8172 8173 bp->hwrm_spec_code = resp->hwrm_intf_maj_8b << 16 | 8174 resp->hwrm_intf_min_8b << 8 | 8175 resp->hwrm_intf_upd_8b; 8176 if (resp->hwrm_intf_maj_8b < 1) { 8177 netdev_warn(bp->dev, "HWRM interface %d.%d.%d is older than 1.0.0.\n", 8178 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b, 8179 resp->hwrm_intf_upd_8b); 8180 netdev_warn(bp->dev, "Please update firmware with HWRM interface 1.0.0 or newer.\n"); 8181 } 8182 8183 hwrm_ver = HWRM_VERSION_MAJOR << 16 | HWRM_VERSION_MINOR << 8 | 8184 HWRM_VERSION_UPDATE; 8185 8186 if (bp->hwrm_spec_code > hwrm_ver) 8187 snprintf(bp->hwrm_ver_supp, FW_VER_STR_LEN, "%d.%d.%d", 8188 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, 8189 HWRM_VERSION_UPDATE); 8190 else 8191 snprintf(bp->hwrm_ver_supp, FW_VER_STR_LEN, "%d.%d.%d", 8192 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b, 8193 resp->hwrm_intf_upd_8b); 8194 8195 fw_maj = le16_to_cpu(resp->hwrm_fw_major); 8196 if (bp->hwrm_spec_code > 0x10803 && fw_maj) { 8197 fw_min = le16_to_cpu(resp->hwrm_fw_minor); 8198 fw_bld = le16_to_cpu(resp->hwrm_fw_build); 8199 fw_rsv = le16_to_cpu(resp->hwrm_fw_patch); 8200 len = FW_VER_STR_LEN; 8201 } else { 8202 fw_maj = resp->hwrm_fw_maj_8b; 8203 fw_min = resp->hwrm_fw_min_8b; 8204 fw_bld = resp->hwrm_fw_bld_8b; 8205 fw_rsv = resp->hwrm_fw_rsvd_8b; 8206 len = BC_HWRM_STR_LEN; 8207 } 8208 bp->fw_ver_code = BNXT_FW_VER_CODE(fw_maj, fw_min, fw_bld, fw_rsv); 8209 snprintf(bp->fw_ver_str, len, "%d.%d.%d.%d", fw_maj, fw_min, fw_bld, 8210 fw_rsv); 8211 8212 if (strlen(resp->active_pkg_name)) { 8213 int fw_ver_len = strlen(bp->fw_ver_str); 8214 8215 snprintf(bp->fw_ver_str + fw_ver_len, 8216 FW_VER_STR_LEN - fw_ver_len - 1, "/pkg %s", 8217 resp->active_pkg_name); 8218 bp->fw_cap |= BNXT_FW_CAP_PKG_VER; 8219 } 8220 8221 bp->hwrm_cmd_timeout = le16_to_cpu(resp->def_req_timeout); 8222 if (!bp->hwrm_cmd_timeout) 8223 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT; 8224 bp->hwrm_cmd_max_timeout = le16_to_cpu(resp->max_req_timeout) * 1000; 8225 if (!bp->hwrm_cmd_max_timeout) 8226 bp->hwrm_cmd_max_timeout = HWRM_CMD_MAX_TIMEOUT; 8227 else if (bp->hwrm_cmd_max_timeout > HWRM_CMD_MAX_TIMEOUT) 8228 netdev_warn(bp->dev, "Device requests max timeout of %d seconds, may trigger hung task watchdog\n", 8229 bp->hwrm_cmd_max_timeout / 1000); 8230 8231 if (resp->hwrm_intf_maj_8b >= 1) { 8232 bp->hwrm_max_req_len = le16_to_cpu(resp->max_req_win_len); 8233 bp->hwrm_max_ext_req_len = le16_to_cpu(resp->max_ext_req_len); 8234 } 8235 if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN) 8236 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN; 8237 8238 bp->chip_num = le16_to_cpu(resp->chip_num); 8239 bp->chip_rev = resp->chip_rev; 8240 if (bp->chip_num == CHIP_NUM_58700 && !resp->chip_rev && 8241 !resp->chip_metal) 8242 bp->flags |= BNXT_FLAG_CHIP_NITRO_A0; 8243 8244 dev_caps_cfg = le32_to_cpu(resp->dev_caps_cfg); 8245 if ((dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) && 8246 (dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) 8247 bp->fw_cap |= BNXT_FW_CAP_SHORT_CMD; 8248 8249 if (dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) 8250 bp->fw_cap |= BNXT_FW_CAP_KONG_MB_CHNL; 8251 8252 if (dev_caps_cfg & 8253 VER_GET_RESP_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED) 8254 bp->fw_cap |= BNXT_FW_CAP_OVS_64BIT_HANDLE; 8255 8256 if (dev_caps_cfg & 8257 VER_GET_RESP_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED) 8258 bp->fw_cap |= BNXT_FW_CAP_TRUSTED_VF; 8259 8260 if (dev_caps_cfg & 8261 VER_GET_RESP_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED) 8262 bp->fw_cap |= BNXT_FW_CAP_CFA_ADV_FLOW; 8263 8264 hwrm_ver_get_exit: 8265 hwrm_req_drop(bp, req); 8266 return rc; 8267 } 8268 8269 int bnxt_hwrm_fw_set_time(struct bnxt *bp) 8270 { 8271 struct hwrm_fw_set_time_input *req; 8272 struct tm tm; 8273 time64_t now = ktime_get_real_seconds(); 8274 int rc; 8275 8276 if ((BNXT_VF(bp) && bp->hwrm_spec_code < 0x10901) || 8277 bp->hwrm_spec_code < 0x10400) 8278 return -EOPNOTSUPP; 8279 8280 time64_to_tm(now, 0, &tm); 8281 rc = hwrm_req_init(bp, req, HWRM_FW_SET_TIME); 8282 if (rc) 8283 return rc; 8284 8285 req->year = cpu_to_le16(1900 + tm.tm_year); 8286 req->month = 1 + tm.tm_mon; 8287 req->day = tm.tm_mday; 8288 req->hour = tm.tm_hour; 8289 req->minute = tm.tm_min; 8290 req->second = tm.tm_sec; 8291 return hwrm_req_send(bp, req); 8292 } 8293 8294 static void bnxt_add_one_ctr(u64 hw, u64 *sw, u64 mask) 8295 { 8296 u64 sw_tmp; 8297 8298 hw &= mask; 8299 sw_tmp = (*sw & ~mask) | hw; 8300 if (hw < (*sw & mask)) 8301 sw_tmp += mask + 1; 8302 WRITE_ONCE(*sw, sw_tmp); 8303 } 8304 8305 static void __bnxt_accumulate_stats(__le64 *hw_stats, u64 *sw_stats, u64 *masks, 8306 int count, bool ignore_zero) 8307 { 8308 int i; 8309 8310 for (i = 0; i < count; i++) { 8311 u64 hw = le64_to_cpu(READ_ONCE(hw_stats[i])); 8312 8313 if (ignore_zero && !hw) 8314 continue; 8315 8316 if (masks[i] == -1ULL) 8317 sw_stats[i] = hw; 8318 else 8319 bnxt_add_one_ctr(hw, &sw_stats[i], masks[i]); 8320 } 8321 } 8322 8323 static void bnxt_accumulate_stats(struct bnxt_stats_mem *stats) 8324 { 8325 if (!stats->hw_stats) 8326 return; 8327 8328 __bnxt_accumulate_stats(stats->hw_stats, stats->sw_stats, 8329 stats->hw_masks, stats->len / 8, false); 8330 } 8331 8332 static void bnxt_accumulate_all_stats(struct bnxt *bp) 8333 { 8334 struct bnxt_stats_mem *ring0_stats; 8335 bool ignore_zero = false; 8336 int i; 8337 8338 /* Chip bug. Counter intermittently becomes 0. */ 8339 if (bp->flags & BNXT_FLAG_CHIP_P5) 8340 ignore_zero = true; 8341 8342 for (i = 0; i < bp->cp_nr_rings; i++) { 8343 struct bnxt_napi *bnapi = bp->bnapi[i]; 8344 struct bnxt_cp_ring_info *cpr; 8345 struct bnxt_stats_mem *stats; 8346 8347 cpr = &bnapi->cp_ring; 8348 stats = &cpr->stats; 8349 if (!i) 8350 ring0_stats = stats; 8351 __bnxt_accumulate_stats(stats->hw_stats, stats->sw_stats, 8352 ring0_stats->hw_masks, 8353 ring0_stats->len / 8, ignore_zero); 8354 } 8355 if (bp->flags & BNXT_FLAG_PORT_STATS) { 8356 struct bnxt_stats_mem *stats = &bp->port_stats; 8357 __le64 *hw_stats = stats->hw_stats; 8358 u64 *sw_stats = stats->sw_stats; 8359 u64 *masks = stats->hw_masks; 8360 int cnt; 8361 8362 cnt = sizeof(struct rx_port_stats) / 8; 8363 __bnxt_accumulate_stats(hw_stats, sw_stats, masks, cnt, false); 8364 8365 hw_stats += BNXT_TX_PORT_STATS_BYTE_OFFSET / 8; 8366 sw_stats += BNXT_TX_PORT_STATS_BYTE_OFFSET / 8; 8367 masks += BNXT_TX_PORT_STATS_BYTE_OFFSET / 8; 8368 cnt = sizeof(struct tx_port_stats) / 8; 8369 __bnxt_accumulate_stats(hw_stats, sw_stats, masks, cnt, false); 8370 } 8371 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) { 8372 bnxt_accumulate_stats(&bp->rx_port_stats_ext); 8373 bnxt_accumulate_stats(&bp->tx_port_stats_ext); 8374 } 8375 } 8376 8377 static int bnxt_hwrm_port_qstats(struct bnxt *bp, u8 flags) 8378 { 8379 struct hwrm_port_qstats_input *req; 8380 struct bnxt_pf_info *pf = &bp->pf; 8381 int rc; 8382 8383 if (!(bp->flags & BNXT_FLAG_PORT_STATS)) 8384 return 0; 8385 8386 if (flags && !(bp->fw_cap & BNXT_FW_CAP_EXT_HW_STATS_SUPPORTED)) 8387 return -EOPNOTSUPP; 8388 8389 rc = hwrm_req_init(bp, req, HWRM_PORT_QSTATS); 8390 if (rc) 8391 return rc; 8392 8393 req->flags = flags; 8394 req->port_id = cpu_to_le16(pf->port_id); 8395 req->tx_stat_host_addr = cpu_to_le64(bp->port_stats.hw_stats_map + 8396 BNXT_TX_PORT_STATS_BYTE_OFFSET); 8397 req->rx_stat_host_addr = cpu_to_le64(bp->port_stats.hw_stats_map); 8398 return hwrm_req_send(bp, req); 8399 } 8400 8401 static int bnxt_hwrm_port_qstats_ext(struct bnxt *bp, u8 flags) 8402 { 8403 struct hwrm_queue_pri2cos_qcfg_output *resp_qc; 8404 struct hwrm_queue_pri2cos_qcfg_input *req_qc; 8405 struct hwrm_port_qstats_ext_output *resp_qs; 8406 struct hwrm_port_qstats_ext_input *req_qs; 8407 struct bnxt_pf_info *pf = &bp->pf; 8408 u32 tx_stat_size; 8409 int rc; 8410 8411 if (!(bp->flags & BNXT_FLAG_PORT_STATS_EXT)) 8412 return 0; 8413 8414 if (flags && !(bp->fw_cap & BNXT_FW_CAP_EXT_HW_STATS_SUPPORTED)) 8415 return -EOPNOTSUPP; 8416 8417 rc = hwrm_req_init(bp, req_qs, HWRM_PORT_QSTATS_EXT); 8418 if (rc) 8419 return rc; 8420 8421 req_qs->flags = flags; 8422 req_qs->port_id = cpu_to_le16(pf->port_id); 8423 req_qs->rx_stat_size = cpu_to_le16(sizeof(struct rx_port_stats_ext)); 8424 req_qs->rx_stat_host_addr = cpu_to_le64(bp->rx_port_stats_ext.hw_stats_map); 8425 tx_stat_size = bp->tx_port_stats_ext.hw_stats ? 8426 sizeof(struct tx_port_stats_ext) : 0; 8427 req_qs->tx_stat_size = cpu_to_le16(tx_stat_size); 8428 req_qs->tx_stat_host_addr = cpu_to_le64(bp->tx_port_stats_ext.hw_stats_map); 8429 resp_qs = hwrm_req_hold(bp, req_qs); 8430 rc = hwrm_req_send(bp, req_qs); 8431 if (!rc) { 8432 bp->fw_rx_stats_ext_size = 8433 le16_to_cpu(resp_qs->rx_stat_size) / 8; 8434 if (BNXT_FW_MAJ(bp) < 220 && 8435 bp->fw_rx_stats_ext_size > BNXT_RX_STATS_EXT_NUM_LEGACY) 8436 bp->fw_rx_stats_ext_size = BNXT_RX_STATS_EXT_NUM_LEGACY; 8437 8438 bp->fw_tx_stats_ext_size = tx_stat_size ? 8439 le16_to_cpu(resp_qs->tx_stat_size) / 8 : 0; 8440 } else { 8441 bp->fw_rx_stats_ext_size = 0; 8442 bp->fw_tx_stats_ext_size = 0; 8443 } 8444 hwrm_req_drop(bp, req_qs); 8445 8446 if (flags) 8447 return rc; 8448 8449 if (bp->fw_tx_stats_ext_size <= 8450 offsetof(struct tx_port_stats_ext, pfc_pri0_tx_duration_us) / 8) { 8451 bp->pri2cos_valid = 0; 8452 return rc; 8453 } 8454 8455 rc = hwrm_req_init(bp, req_qc, HWRM_QUEUE_PRI2COS_QCFG); 8456 if (rc) 8457 return rc; 8458 8459 req_qc->flags = cpu_to_le32(QUEUE_PRI2COS_QCFG_REQ_FLAGS_IVLAN); 8460 8461 resp_qc = hwrm_req_hold(bp, req_qc); 8462 rc = hwrm_req_send(bp, req_qc); 8463 if (!rc) { 8464 u8 *pri2cos; 8465 int i, j; 8466 8467 pri2cos = &resp_qc->pri0_cos_queue_id; 8468 for (i = 0; i < 8; i++) { 8469 u8 queue_id = pri2cos[i]; 8470 u8 queue_idx; 8471 8472 /* Per port queue IDs start from 0, 10, 20, etc */ 8473 queue_idx = queue_id % 10; 8474 if (queue_idx > BNXT_MAX_QUEUE) { 8475 bp->pri2cos_valid = false; 8476 hwrm_req_drop(bp, req_qc); 8477 return rc; 8478 } 8479 for (j = 0; j < bp->max_q; j++) { 8480 if (bp->q_ids[j] == queue_id) 8481 bp->pri2cos_idx[i] = queue_idx; 8482 } 8483 } 8484 bp->pri2cos_valid = true; 8485 } 8486 hwrm_req_drop(bp, req_qc); 8487 8488 return rc; 8489 } 8490 8491 static void bnxt_hwrm_free_tunnel_ports(struct bnxt *bp) 8492 { 8493 bnxt_hwrm_tunnel_dst_port_free(bp, 8494 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN); 8495 bnxt_hwrm_tunnel_dst_port_free(bp, 8496 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE); 8497 } 8498 8499 static int bnxt_set_tpa(struct bnxt *bp, bool set_tpa) 8500 { 8501 int rc, i; 8502 u32 tpa_flags = 0; 8503 8504 if (set_tpa) 8505 tpa_flags = bp->flags & BNXT_FLAG_TPA; 8506 else if (BNXT_NO_FW_ACCESS(bp)) 8507 return 0; 8508 for (i = 0; i < bp->nr_vnics; i++) { 8509 rc = bnxt_hwrm_vnic_set_tpa(bp, i, tpa_flags); 8510 if (rc) { 8511 netdev_err(bp->dev, "hwrm vnic set tpa failure rc for vnic %d: %x\n", 8512 i, rc); 8513 return rc; 8514 } 8515 } 8516 return 0; 8517 } 8518 8519 static void bnxt_hwrm_clear_vnic_rss(struct bnxt *bp) 8520 { 8521 int i; 8522 8523 for (i = 0; i < bp->nr_vnics; i++) 8524 bnxt_hwrm_vnic_set_rss(bp, i, false); 8525 } 8526 8527 static void bnxt_clear_vnic(struct bnxt *bp) 8528 { 8529 if (!bp->vnic_info) 8530 return; 8531 8532 bnxt_hwrm_clear_vnic_filter(bp); 8533 if (!(bp->flags & BNXT_FLAG_CHIP_P5)) { 8534 /* clear all RSS setting before free vnic ctx */ 8535 bnxt_hwrm_clear_vnic_rss(bp); 8536 bnxt_hwrm_vnic_ctx_free(bp); 8537 } 8538 /* before free the vnic, undo the vnic tpa settings */ 8539 if (bp->flags & BNXT_FLAG_TPA) 8540 bnxt_set_tpa(bp, false); 8541 bnxt_hwrm_vnic_free(bp); 8542 if (bp->flags & BNXT_FLAG_CHIP_P5) 8543 bnxt_hwrm_vnic_ctx_free(bp); 8544 } 8545 8546 static void bnxt_hwrm_resource_free(struct bnxt *bp, bool close_path, 8547 bool irq_re_init) 8548 { 8549 bnxt_clear_vnic(bp); 8550 bnxt_hwrm_ring_free(bp, close_path); 8551 bnxt_hwrm_ring_grp_free(bp); 8552 if (irq_re_init) { 8553 bnxt_hwrm_stat_ctx_free(bp); 8554 bnxt_hwrm_free_tunnel_ports(bp); 8555 } 8556 } 8557 8558 static int bnxt_hwrm_set_br_mode(struct bnxt *bp, u16 br_mode) 8559 { 8560 struct hwrm_func_cfg_input *req; 8561 u8 evb_mode; 8562 int rc; 8563 8564 if (br_mode == BRIDGE_MODE_VEB) 8565 evb_mode = FUNC_CFG_REQ_EVB_MODE_VEB; 8566 else if (br_mode == BRIDGE_MODE_VEPA) 8567 evb_mode = FUNC_CFG_REQ_EVB_MODE_VEPA; 8568 else 8569 return -EINVAL; 8570 8571 rc = hwrm_req_init(bp, req, HWRM_FUNC_CFG); 8572 if (rc) 8573 return rc; 8574 8575 req->fid = cpu_to_le16(0xffff); 8576 req->enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_EVB_MODE); 8577 req->evb_mode = evb_mode; 8578 return hwrm_req_send(bp, req); 8579 } 8580 8581 static int bnxt_hwrm_set_cache_line_size(struct bnxt *bp, int size) 8582 { 8583 struct hwrm_func_cfg_input *req; 8584 int rc; 8585 8586 if (BNXT_VF(bp) || bp->hwrm_spec_code < 0x10803) 8587 return 0; 8588 8589 rc = hwrm_req_init(bp, req, HWRM_FUNC_CFG); 8590 if (rc) 8591 return rc; 8592 8593 req->fid = cpu_to_le16(0xffff); 8594 req->enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_CACHE_LINESIZE); 8595 req->options = FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_64; 8596 if (size == 128) 8597 req->options = FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128; 8598 8599 return hwrm_req_send(bp, req); 8600 } 8601 8602 static int __bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id) 8603 { 8604 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 8605 int rc; 8606 8607 if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG) 8608 goto skip_rss_ctx; 8609 8610 /* allocate context for vnic */ 8611 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 0); 8612 if (rc) { 8613 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n", 8614 vnic_id, rc); 8615 goto vnic_setup_err; 8616 } 8617 bp->rsscos_nr_ctxs++; 8618 8619 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) { 8620 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 1); 8621 if (rc) { 8622 netdev_err(bp->dev, "hwrm vnic %d cos ctx alloc failure rc: %x\n", 8623 vnic_id, rc); 8624 goto vnic_setup_err; 8625 } 8626 bp->rsscos_nr_ctxs++; 8627 } 8628 8629 skip_rss_ctx: 8630 /* configure default vnic, ring grp */ 8631 rc = bnxt_hwrm_vnic_cfg(bp, vnic_id); 8632 if (rc) { 8633 netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n", 8634 vnic_id, rc); 8635 goto vnic_setup_err; 8636 } 8637 8638 /* Enable RSS hashing on vnic */ 8639 rc = bnxt_hwrm_vnic_set_rss(bp, vnic_id, true); 8640 if (rc) { 8641 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %x\n", 8642 vnic_id, rc); 8643 goto vnic_setup_err; 8644 } 8645 8646 if (bp->flags & BNXT_FLAG_AGG_RINGS) { 8647 rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id); 8648 if (rc) { 8649 netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n", 8650 vnic_id, rc); 8651 } 8652 } 8653 8654 vnic_setup_err: 8655 return rc; 8656 } 8657 8658 static int __bnxt_setup_vnic_p5(struct bnxt *bp, u16 vnic_id) 8659 { 8660 int rc, i, nr_ctxs; 8661 8662 nr_ctxs = bnxt_get_nr_rss_ctxs(bp, bp->rx_nr_rings); 8663 for (i = 0; i < nr_ctxs; i++) { 8664 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, i); 8665 if (rc) { 8666 netdev_err(bp->dev, "hwrm vnic %d ctx %d alloc failure rc: %x\n", 8667 vnic_id, i, rc); 8668 break; 8669 } 8670 bp->rsscos_nr_ctxs++; 8671 } 8672 if (i < nr_ctxs) 8673 return -ENOMEM; 8674 8675 rc = bnxt_hwrm_vnic_set_rss_p5(bp, vnic_id, true); 8676 if (rc) { 8677 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %d\n", 8678 vnic_id, rc); 8679 return rc; 8680 } 8681 rc = bnxt_hwrm_vnic_cfg(bp, vnic_id); 8682 if (rc) { 8683 netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n", 8684 vnic_id, rc); 8685 return rc; 8686 } 8687 if (bp->flags & BNXT_FLAG_AGG_RINGS) { 8688 rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id); 8689 if (rc) { 8690 netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n", 8691 vnic_id, rc); 8692 } 8693 } 8694 return rc; 8695 } 8696 8697 static int bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id) 8698 { 8699 if (bp->flags & BNXT_FLAG_CHIP_P5) 8700 return __bnxt_setup_vnic_p5(bp, vnic_id); 8701 else 8702 return __bnxt_setup_vnic(bp, vnic_id); 8703 } 8704 8705 static int bnxt_alloc_rfs_vnics(struct bnxt *bp) 8706 { 8707 #ifdef CONFIG_RFS_ACCEL 8708 int i, rc = 0; 8709 8710 if (bp->flags & BNXT_FLAG_CHIP_P5) 8711 return 0; 8712 8713 for (i = 0; i < bp->rx_nr_rings; i++) { 8714 struct bnxt_vnic_info *vnic; 8715 u16 vnic_id = i + 1; 8716 u16 ring_id = i; 8717 8718 if (vnic_id >= bp->nr_vnics) 8719 break; 8720 8721 vnic = &bp->vnic_info[vnic_id]; 8722 vnic->flags |= BNXT_VNIC_RFS_FLAG; 8723 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP) 8724 vnic->flags |= BNXT_VNIC_RFS_NEW_RSS_FLAG; 8725 rc = bnxt_hwrm_vnic_alloc(bp, vnic_id, ring_id, 1); 8726 if (rc) { 8727 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n", 8728 vnic_id, rc); 8729 break; 8730 } 8731 rc = bnxt_setup_vnic(bp, vnic_id); 8732 if (rc) 8733 break; 8734 } 8735 return rc; 8736 #else 8737 return 0; 8738 #endif 8739 } 8740 8741 /* Allow PF, trusted VFs and VFs with default VLAN to be in promiscuous mode */ 8742 static bool bnxt_promisc_ok(struct bnxt *bp) 8743 { 8744 #ifdef CONFIG_BNXT_SRIOV 8745 if (BNXT_VF(bp) && !bp->vf.vlan && !bnxt_is_trusted_vf(bp, &bp->vf)) 8746 return false; 8747 #endif 8748 return true; 8749 } 8750 8751 static int bnxt_setup_nitroa0_vnic(struct bnxt *bp) 8752 { 8753 unsigned int rc = 0; 8754 8755 rc = bnxt_hwrm_vnic_alloc(bp, 1, bp->rx_nr_rings - 1, 1); 8756 if (rc) { 8757 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n", 8758 rc); 8759 return rc; 8760 } 8761 8762 rc = bnxt_hwrm_vnic_cfg(bp, 1); 8763 if (rc) { 8764 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n", 8765 rc); 8766 return rc; 8767 } 8768 return rc; 8769 } 8770 8771 static int bnxt_cfg_rx_mode(struct bnxt *); 8772 static bool bnxt_mc_list_updated(struct bnxt *, u32 *); 8773 8774 static int bnxt_init_chip(struct bnxt *bp, bool irq_re_init) 8775 { 8776 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 8777 int rc = 0; 8778 unsigned int rx_nr_rings = bp->rx_nr_rings; 8779 8780 if (irq_re_init) { 8781 rc = bnxt_hwrm_stat_ctx_alloc(bp); 8782 if (rc) { 8783 netdev_err(bp->dev, "hwrm stat ctx alloc failure rc: %x\n", 8784 rc); 8785 goto err_out; 8786 } 8787 } 8788 8789 rc = bnxt_hwrm_ring_alloc(bp); 8790 if (rc) { 8791 netdev_err(bp->dev, "hwrm ring alloc failure rc: %x\n", rc); 8792 goto err_out; 8793 } 8794 8795 rc = bnxt_hwrm_ring_grp_alloc(bp); 8796 if (rc) { 8797 netdev_err(bp->dev, "hwrm_ring_grp alloc failure: %x\n", rc); 8798 goto err_out; 8799 } 8800 8801 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 8802 rx_nr_rings--; 8803 8804 /* default vnic 0 */ 8805 rc = bnxt_hwrm_vnic_alloc(bp, 0, 0, rx_nr_rings); 8806 if (rc) { 8807 netdev_err(bp->dev, "hwrm vnic alloc failure rc: %x\n", rc); 8808 goto err_out; 8809 } 8810 8811 rc = bnxt_setup_vnic(bp, 0); 8812 if (rc) 8813 goto err_out; 8814 if (bp->fw_cap & BNXT_FW_CAP_RSS_HASH_TYPE_DELTA) 8815 bnxt_hwrm_update_rss_hash_cfg(bp); 8816 8817 if (bp->flags & BNXT_FLAG_RFS) { 8818 rc = bnxt_alloc_rfs_vnics(bp); 8819 if (rc) 8820 goto err_out; 8821 } 8822 8823 if (bp->flags & BNXT_FLAG_TPA) { 8824 rc = bnxt_set_tpa(bp, true); 8825 if (rc) 8826 goto err_out; 8827 } 8828 8829 if (BNXT_VF(bp)) 8830 bnxt_update_vf_mac(bp); 8831 8832 /* Filter for default vnic 0 */ 8833 rc = bnxt_hwrm_set_vnic_filter(bp, 0, 0, bp->dev->dev_addr); 8834 if (rc) { 8835 if (BNXT_VF(bp) && rc == -ENODEV) 8836 netdev_err(bp->dev, "Cannot configure L2 filter while PF is unavailable\n"); 8837 else 8838 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n", rc); 8839 goto err_out; 8840 } 8841 vnic->uc_filter_count = 1; 8842 8843 vnic->rx_mask = 0; 8844 if (test_bit(BNXT_STATE_HALF_OPEN, &bp->state)) 8845 goto skip_rx_mask; 8846 8847 if (bp->dev->flags & IFF_BROADCAST) 8848 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_BCAST; 8849 8850 if (bp->dev->flags & IFF_PROMISC) 8851 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS; 8852 8853 if (bp->dev->flags & IFF_ALLMULTI) { 8854 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST; 8855 vnic->mc_list_count = 0; 8856 } else if (bp->dev->flags & IFF_MULTICAST) { 8857 u32 mask = 0; 8858 8859 bnxt_mc_list_updated(bp, &mask); 8860 vnic->rx_mask |= mask; 8861 } 8862 8863 rc = bnxt_cfg_rx_mode(bp); 8864 if (rc) 8865 goto err_out; 8866 8867 skip_rx_mask: 8868 rc = bnxt_hwrm_set_coal(bp); 8869 if (rc) 8870 netdev_warn(bp->dev, "HWRM set coalescing failure rc: %x\n", 8871 rc); 8872 8873 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) { 8874 rc = bnxt_setup_nitroa0_vnic(bp); 8875 if (rc) 8876 netdev_err(bp->dev, "Special vnic setup failure for NS2 A0 rc: %x\n", 8877 rc); 8878 } 8879 8880 if (BNXT_VF(bp)) { 8881 bnxt_hwrm_func_qcfg(bp); 8882 netdev_update_features(bp->dev); 8883 } 8884 8885 return 0; 8886 8887 err_out: 8888 bnxt_hwrm_resource_free(bp, 0, true); 8889 8890 return rc; 8891 } 8892 8893 static int bnxt_shutdown_nic(struct bnxt *bp, bool irq_re_init) 8894 { 8895 bnxt_hwrm_resource_free(bp, 1, irq_re_init); 8896 return 0; 8897 } 8898 8899 static int bnxt_init_nic(struct bnxt *bp, bool irq_re_init) 8900 { 8901 bnxt_init_cp_rings(bp); 8902 bnxt_init_rx_rings(bp); 8903 bnxt_init_tx_rings(bp); 8904 bnxt_init_ring_grps(bp, irq_re_init); 8905 bnxt_init_vnics(bp); 8906 8907 return bnxt_init_chip(bp, irq_re_init); 8908 } 8909 8910 static int bnxt_set_real_num_queues(struct bnxt *bp) 8911 { 8912 int rc; 8913 struct net_device *dev = bp->dev; 8914 8915 rc = netif_set_real_num_tx_queues(dev, bp->tx_nr_rings - 8916 bp->tx_nr_rings_xdp); 8917 if (rc) 8918 return rc; 8919 8920 rc = netif_set_real_num_rx_queues(dev, bp->rx_nr_rings); 8921 if (rc) 8922 return rc; 8923 8924 #ifdef CONFIG_RFS_ACCEL 8925 if (bp->flags & BNXT_FLAG_RFS) 8926 dev->rx_cpu_rmap = alloc_irq_cpu_rmap(bp->rx_nr_rings); 8927 #endif 8928 8929 return rc; 8930 } 8931 8932 static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max, 8933 bool shared) 8934 { 8935 int _rx = *rx, _tx = *tx; 8936 8937 if (shared) { 8938 *rx = min_t(int, _rx, max); 8939 *tx = min_t(int, _tx, max); 8940 } else { 8941 if (max < 2) 8942 return -ENOMEM; 8943 8944 while (_rx + _tx > max) { 8945 if (_rx > _tx && _rx > 1) 8946 _rx--; 8947 else if (_tx > 1) 8948 _tx--; 8949 } 8950 *rx = _rx; 8951 *tx = _tx; 8952 } 8953 return 0; 8954 } 8955 8956 static void bnxt_setup_msix(struct bnxt *bp) 8957 { 8958 const int len = sizeof(bp->irq_tbl[0].name); 8959 struct net_device *dev = bp->dev; 8960 int tcs, i; 8961 8962 tcs = netdev_get_num_tc(dev); 8963 if (tcs) { 8964 int i, off, count; 8965 8966 for (i = 0; i < tcs; i++) { 8967 count = bp->tx_nr_rings_per_tc; 8968 off = i * count; 8969 netdev_set_tc_queue(dev, i, count, off); 8970 } 8971 } 8972 8973 for (i = 0; i < bp->cp_nr_rings; i++) { 8974 int map_idx = bnxt_cp_num_to_irq_num(bp, i); 8975 char *attr; 8976 8977 if (bp->flags & BNXT_FLAG_SHARED_RINGS) 8978 attr = "TxRx"; 8979 else if (i < bp->rx_nr_rings) 8980 attr = "rx"; 8981 else 8982 attr = "tx"; 8983 8984 snprintf(bp->irq_tbl[map_idx].name, len, "%s-%s-%d", dev->name, 8985 attr, i); 8986 bp->irq_tbl[map_idx].handler = bnxt_msix; 8987 } 8988 } 8989 8990 static void bnxt_setup_inta(struct bnxt *bp) 8991 { 8992 const int len = sizeof(bp->irq_tbl[0].name); 8993 8994 if (netdev_get_num_tc(bp->dev)) 8995 netdev_reset_tc(bp->dev); 8996 8997 snprintf(bp->irq_tbl[0].name, len, "%s-%s-%d", bp->dev->name, "TxRx", 8998 0); 8999 bp->irq_tbl[0].handler = bnxt_inta; 9000 } 9001 9002 static int bnxt_init_int_mode(struct bnxt *bp); 9003 9004 static int bnxt_setup_int_mode(struct bnxt *bp) 9005 { 9006 int rc; 9007 9008 if (!bp->irq_tbl) { 9009 rc = bnxt_init_int_mode(bp); 9010 if (rc || !bp->irq_tbl) 9011 return rc ?: -ENODEV; 9012 } 9013 9014 if (bp->flags & BNXT_FLAG_USING_MSIX) 9015 bnxt_setup_msix(bp); 9016 else 9017 bnxt_setup_inta(bp); 9018 9019 rc = bnxt_set_real_num_queues(bp); 9020 return rc; 9021 } 9022 9023 #ifdef CONFIG_RFS_ACCEL 9024 static unsigned int bnxt_get_max_func_rss_ctxs(struct bnxt *bp) 9025 { 9026 return bp->hw_resc.max_rsscos_ctxs; 9027 } 9028 9029 static unsigned int bnxt_get_max_func_vnics(struct bnxt *bp) 9030 { 9031 return bp->hw_resc.max_vnics; 9032 } 9033 #endif 9034 9035 unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt *bp) 9036 { 9037 return bp->hw_resc.max_stat_ctxs; 9038 } 9039 9040 unsigned int bnxt_get_max_func_cp_rings(struct bnxt *bp) 9041 { 9042 return bp->hw_resc.max_cp_rings; 9043 } 9044 9045 static unsigned int bnxt_get_max_func_cp_rings_for_en(struct bnxt *bp) 9046 { 9047 unsigned int cp = bp->hw_resc.max_cp_rings; 9048 9049 if (!(bp->flags & BNXT_FLAG_CHIP_P5)) 9050 cp -= bnxt_get_ulp_msix_num(bp); 9051 9052 return cp; 9053 } 9054 9055 static unsigned int bnxt_get_max_func_irqs(struct bnxt *bp) 9056 { 9057 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 9058 9059 if (bp->flags & BNXT_FLAG_CHIP_P5) 9060 return min_t(unsigned int, hw_resc->max_irqs, hw_resc->max_nqs); 9061 9062 return min_t(unsigned int, hw_resc->max_irqs, hw_resc->max_cp_rings); 9063 } 9064 9065 static void bnxt_set_max_func_irqs(struct bnxt *bp, unsigned int max_irqs) 9066 { 9067 bp->hw_resc.max_irqs = max_irqs; 9068 } 9069 9070 unsigned int bnxt_get_avail_cp_rings_for_en(struct bnxt *bp) 9071 { 9072 unsigned int cp; 9073 9074 cp = bnxt_get_max_func_cp_rings_for_en(bp); 9075 if (bp->flags & BNXT_FLAG_CHIP_P5) 9076 return cp - bp->rx_nr_rings - bp->tx_nr_rings; 9077 else 9078 return cp - bp->cp_nr_rings; 9079 } 9080 9081 unsigned int bnxt_get_avail_stat_ctxs_for_en(struct bnxt *bp) 9082 { 9083 return bnxt_get_max_func_stat_ctxs(bp) - bnxt_get_func_stat_ctxs(bp); 9084 } 9085 9086 int bnxt_get_avail_msix(struct bnxt *bp, int num) 9087 { 9088 int max_cp = bnxt_get_max_func_cp_rings(bp); 9089 int max_irq = bnxt_get_max_func_irqs(bp); 9090 int total_req = bp->cp_nr_rings + num; 9091 int max_idx, avail_msix; 9092 9093 max_idx = bp->total_irqs; 9094 if (!(bp->flags & BNXT_FLAG_CHIP_P5)) 9095 max_idx = min_t(int, bp->total_irqs, max_cp); 9096 avail_msix = max_idx - bp->cp_nr_rings; 9097 if (!BNXT_NEW_RM(bp) || avail_msix >= num) 9098 return avail_msix; 9099 9100 if (max_irq < total_req) { 9101 num = max_irq - bp->cp_nr_rings; 9102 if (num <= 0) 9103 return 0; 9104 } 9105 return num; 9106 } 9107 9108 static int bnxt_get_num_msix(struct bnxt *bp) 9109 { 9110 if (!BNXT_NEW_RM(bp)) 9111 return bnxt_get_max_func_irqs(bp); 9112 9113 return bnxt_nq_rings_in_use(bp); 9114 } 9115 9116 static int bnxt_init_msix(struct bnxt *bp) 9117 { 9118 int i, total_vecs, max, rc = 0, min = 1, ulp_msix; 9119 struct msix_entry *msix_ent; 9120 9121 total_vecs = bnxt_get_num_msix(bp); 9122 max = bnxt_get_max_func_irqs(bp); 9123 if (total_vecs > max) 9124 total_vecs = max; 9125 9126 if (!total_vecs) 9127 return 0; 9128 9129 msix_ent = kcalloc(total_vecs, sizeof(struct msix_entry), GFP_KERNEL); 9130 if (!msix_ent) 9131 return -ENOMEM; 9132 9133 for (i = 0; i < total_vecs; i++) { 9134 msix_ent[i].entry = i; 9135 msix_ent[i].vector = 0; 9136 } 9137 9138 if (!(bp->flags & BNXT_FLAG_SHARED_RINGS)) 9139 min = 2; 9140 9141 total_vecs = pci_enable_msix_range(bp->pdev, msix_ent, min, total_vecs); 9142 ulp_msix = bnxt_get_ulp_msix_num(bp); 9143 if (total_vecs < 0 || total_vecs < ulp_msix) { 9144 rc = -ENODEV; 9145 goto msix_setup_exit; 9146 } 9147 9148 bp->irq_tbl = kcalloc(total_vecs, sizeof(struct bnxt_irq), GFP_KERNEL); 9149 if (bp->irq_tbl) { 9150 for (i = 0; i < total_vecs; i++) 9151 bp->irq_tbl[i].vector = msix_ent[i].vector; 9152 9153 bp->total_irqs = total_vecs; 9154 /* Trim rings based upon num of vectors allocated */ 9155 rc = bnxt_trim_rings(bp, &bp->rx_nr_rings, &bp->tx_nr_rings, 9156 total_vecs - ulp_msix, min == 1); 9157 if (rc) 9158 goto msix_setup_exit; 9159 9160 bp->cp_nr_rings = (min == 1) ? 9161 max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) : 9162 bp->tx_nr_rings + bp->rx_nr_rings; 9163 9164 } else { 9165 rc = -ENOMEM; 9166 goto msix_setup_exit; 9167 } 9168 bp->flags |= BNXT_FLAG_USING_MSIX; 9169 kfree(msix_ent); 9170 return 0; 9171 9172 msix_setup_exit: 9173 netdev_err(bp->dev, "bnxt_init_msix err: %x\n", rc); 9174 kfree(bp->irq_tbl); 9175 bp->irq_tbl = NULL; 9176 pci_disable_msix(bp->pdev); 9177 kfree(msix_ent); 9178 return rc; 9179 } 9180 9181 static int bnxt_init_inta(struct bnxt *bp) 9182 { 9183 bp->irq_tbl = kzalloc(sizeof(struct bnxt_irq), GFP_KERNEL); 9184 if (!bp->irq_tbl) 9185 return -ENOMEM; 9186 9187 bp->total_irqs = 1; 9188 bp->rx_nr_rings = 1; 9189 bp->tx_nr_rings = 1; 9190 bp->cp_nr_rings = 1; 9191 bp->flags |= BNXT_FLAG_SHARED_RINGS; 9192 bp->irq_tbl[0].vector = bp->pdev->irq; 9193 return 0; 9194 } 9195 9196 static int bnxt_init_int_mode(struct bnxt *bp) 9197 { 9198 int rc = -ENODEV; 9199 9200 if (bp->flags & BNXT_FLAG_MSIX_CAP) 9201 rc = bnxt_init_msix(bp); 9202 9203 if (!(bp->flags & BNXT_FLAG_USING_MSIX) && BNXT_PF(bp)) { 9204 /* fallback to INTA */ 9205 rc = bnxt_init_inta(bp); 9206 } 9207 return rc; 9208 } 9209 9210 static void bnxt_clear_int_mode(struct bnxt *bp) 9211 { 9212 if (bp->flags & BNXT_FLAG_USING_MSIX) 9213 pci_disable_msix(bp->pdev); 9214 9215 kfree(bp->irq_tbl); 9216 bp->irq_tbl = NULL; 9217 bp->flags &= ~BNXT_FLAG_USING_MSIX; 9218 } 9219 9220 int bnxt_reserve_rings(struct bnxt *bp, bool irq_re_init) 9221 { 9222 int tcs = netdev_get_num_tc(bp->dev); 9223 bool irq_cleared = false; 9224 int rc; 9225 9226 if (!bnxt_need_reserve_rings(bp)) 9227 return 0; 9228 9229 if (irq_re_init && BNXT_NEW_RM(bp) && 9230 bnxt_get_num_msix(bp) != bp->total_irqs) { 9231 bnxt_ulp_irq_stop(bp); 9232 bnxt_clear_int_mode(bp); 9233 irq_cleared = true; 9234 } 9235 rc = __bnxt_reserve_rings(bp); 9236 if (irq_cleared) { 9237 if (!rc) 9238 rc = bnxt_init_int_mode(bp); 9239 bnxt_ulp_irq_restart(bp, rc); 9240 } 9241 if (rc) { 9242 netdev_err(bp->dev, "ring reservation/IRQ init failure rc: %d\n", rc); 9243 return rc; 9244 } 9245 if (tcs && (bp->tx_nr_rings_per_tc * tcs != 9246 bp->tx_nr_rings - bp->tx_nr_rings_xdp)) { 9247 netdev_err(bp->dev, "tx ring reservation failure\n"); 9248 netdev_reset_tc(bp->dev); 9249 if (bp->tx_nr_rings_xdp) 9250 bp->tx_nr_rings_per_tc = bp->tx_nr_rings_xdp; 9251 else 9252 bp->tx_nr_rings_per_tc = bp->tx_nr_rings; 9253 return -ENOMEM; 9254 } 9255 return 0; 9256 } 9257 9258 static void bnxt_free_irq(struct bnxt *bp) 9259 { 9260 struct bnxt_irq *irq; 9261 int i; 9262 9263 #ifdef CONFIG_RFS_ACCEL 9264 free_irq_cpu_rmap(bp->dev->rx_cpu_rmap); 9265 bp->dev->rx_cpu_rmap = NULL; 9266 #endif 9267 if (!bp->irq_tbl || !bp->bnapi) 9268 return; 9269 9270 for (i = 0; i < bp->cp_nr_rings; i++) { 9271 int map_idx = bnxt_cp_num_to_irq_num(bp, i); 9272 9273 irq = &bp->irq_tbl[map_idx]; 9274 if (irq->requested) { 9275 if (irq->have_cpumask) { 9276 irq_set_affinity_hint(irq->vector, NULL); 9277 free_cpumask_var(irq->cpu_mask); 9278 irq->have_cpumask = 0; 9279 } 9280 free_irq(irq->vector, bp->bnapi[i]); 9281 } 9282 9283 irq->requested = 0; 9284 } 9285 } 9286 9287 static int bnxt_request_irq(struct bnxt *bp) 9288 { 9289 int i, j, rc = 0; 9290 unsigned long flags = 0; 9291 #ifdef CONFIG_RFS_ACCEL 9292 struct cpu_rmap *rmap; 9293 #endif 9294 9295 rc = bnxt_setup_int_mode(bp); 9296 if (rc) { 9297 netdev_err(bp->dev, "bnxt_setup_int_mode err: %x\n", 9298 rc); 9299 return rc; 9300 } 9301 #ifdef CONFIG_RFS_ACCEL 9302 rmap = bp->dev->rx_cpu_rmap; 9303 #endif 9304 if (!(bp->flags & BNXT_FLAG_USING_MSIX)) 9305 flags = IRQF_SHARED; 9306 9307 for (i = 0, j = 0; i < bp->cp_nr_rings; i++) { 9308 int map_idx = bnxt_cp_num_to_irq_num(bp, i); 9309 struct bnxt_irq *irq = &bp->irq_tbl[map_idx]; 9310 9311 #ifdef CONFIG_RFS_ACCEL 9312 if (rmap && bp->bnapi[i]->rx_ring) { 9313 rc = irq_cpu_rmap_add(rmap, irq->vector); 9314 if (rc) 9315 netdev_warn(bp->dev, "failed adding irq rmap for ring %d\n", 9316 j); 9317 j++; 9318 } 9319 #endif 9320 rc = request_irq(irq->vector, irq->handler, flags, irq->name, 9321 bp->bnapi[i]); 9322 if (rc) 9323 break; 9324 9325 irq->requested = 1; 9326 9327 if (zalloc_cpumask_var(&irq->cpu_mask, GFP_KERNEL)) { 9328 int numa_node = dev_to_node(&bp->pdev->dev); 9329 9330 irq->have_cpumask = 1; 9331 cpumask_set_cpu(cpumask_local_spread(i, numa_node), 9332 irq->cpu_mask); 9333 rc = irq_set_affinity_hint(irq->vector, irq->cpu_mask); 9334 if (rc) { 9335 netdev_warn(bp->dev, 9336 "Set affinity failed, IRQ = %d\n", 9337 irq->vector); 9338 break; 9339 } 9340 } 9341 } 9342 return rc; 9343 } 9344 9345 static void bnxt_del_napi(struct bnxt *bp) 9346 { 9347 int i; 9348 9349 if (!bp->bnapi) 9350 return; 9351 9352 for (i = 0; i < bp->cp_nr_rings; i++) { 9353 struct bnxt_napi *bnapi = bp->bnapi[i]; 9354 9355 __netif_napi_del(&bnapi->napi); 9356 } 9357 /* We called __netif_napi_del(), we need 9358 * to respect an RCU grace period before freeing napi structures. 9359 */ 9360 synchronize_net(); 9361 } 9362 9363 static void bnxt_init_napi(struct bnxt *bp) 9364 { 9365 int i; 9366 unsigned int cp_nr_rings = bp->cp_nr_rings; 9367 struct bnxt_napi *bnapi; 9368 9369 if (bp->flags & BNXT_FLAG_USING_MSIX) { 9370 int (*poll_fn)(struct napi_struct *, int) = bnxt_poll; 9371 9372 if (bp->flags & BNXT_FLAG_CHIP_P5) 9373 poll_fn = bnxt_poll_p5; 9374 else if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 9375 cp_nr_rings--; 9376 for (i = 0; i < cp_nr_rings; i++) { 9377 bnapi = bp->bnapi[i]; 9378 netif_napi_add(bp->dev, &bnapi->napi, poll_fn); 9379 } 9380 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) { 9381 bnapi = bp->bnapi[cp_nr_rings]; 9382 netif_napi_add(bp->dev, &bnapi->napi, 9383 bnxt_poll_nitroa0); 9384 } 9385 } else { 9386 bnapi = bp->bnapi[0]; 9387 netif_napi_add(bp->dev, &bnapi->napi, bnxt_poll); 9388 } 9389 } 9390 9391 static void bnxt_disable_napi(struct bnxt *bp) 9392 { 9393 int i; 9394 9395 if (!bp->bnapi || 9396 test_and_set_bit(BNXT_STATE_NAPI_DISABLED, &bp->state)) 9397 return; 9398 9399 for (i = 0; i < bp->cp_nr_rings; i++) { 9400 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring; 9401 9402 napi_disable(&bp->bnapi[i]->napi); 9403 if (bp->bnapi[i]->rx_ring) 9404 cancel_work_sync(&cpr->dim.work); 9405 } 9406 } 9407 9408 static void bnxt_enable_napi(struct bnxt *bp) 9409 { 9410 int i; 9411 9412 clear_bit(BNXT_STATE_NAPI_DISABLED, &bp->state); 9413 for (i = 0; i < bp->cp_nr_rings; i++) { 9414 struct bnxt_napi *bnapi = bp->bnapi[i]; 9415 struct bnxt_cp_ring_info *cpr; 9416 9417 cpr = &bnapi->cp_ring; 9418 if (bnapi->in_reset) 9419 cpr->sw_stats.rx.rx_resets++; 9420 bnapi->in_reset = false; 9421 9422 if (bnapi->rx_ring) { 9423 INIT_WORK(&cpr->dim.work, bnxt_dim_work); 9424 cpr->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE; 9425 } 9426 napi_enable(&bnapi->napi); 9427 } 9428 } 9429 9430 void bnxt_tx_disable(struct bnxt *bp) 9431 { 9432 int i; 9433 struct bnxt_tx_ring_info *txr; 9434 9435 if (bp->tx_ring) { 9436 for (i = 0; i < bp->tx_nr_rings; i++) { 9437 txr = &bp->tx_ring[i]; 9438 WRITE_ONCE(txr->dev_state, BNXT_DEV_STATE_CLOSING); 9439 } 9440 } 9441 /* Make sure napi polls see @dev_state change */ 9442 synchronize_net(); 9443 /* Drop carrier first to prevent TX timeout */ 9444 netif_carrier_off(bp->dev); 9445 /* Stop all TX queues */ 9446 netif_tx_disable(bp->dev); 9447 } 9448 9449 void bnxt_tx_enable(struct bnxt *bp) 9450 { 9451 int i; 9452 struct bnxt_tx_ring_info *txr; 9453 9454 for (i = 0; i < bp->tx_nr_rings; i++) { 9455 txr = &bp->tx_ring[i]; 9456 WRITE_ONCE(txr->dev_state, 0); 9457 } 9458 /* Make sure napi polls see @dev_state change */ 9459 synchronize_net(); 9460 netif_tx_wake_all_queues(bp->dev); 9461 if (BNXT_LINK_IS_UP(bp)) 9462 netif_carrier_on(bp->dev); 9463 } 9464 9465 static char *bnxt_report_fec(struct bnxt_link_info *link_info) 9466 { 9467 u8 active_fec = link_info->active_fec_sig_mode & 9468 PORT_PHY_QCFG_RESP_ACTIVE_FEC_MASK; 9469 9470 switch (active_fec) { 9471 default: 9472 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_NONE_ACTIVE: 9473 return "None"; 9474 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE74_ACTIVE: 9475 return "Clause 74 BaseR"; 9476 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE91_ACTIVE: 9477 return "Clause 91 RS(528,514)"; 9478 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_1XN_ACTIVE: 9479 return "Clause 91 RS544_1XN"; 9480 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_IEEE_ACTIVE: 9481 return "Clause 91 RS(544,514)"; 9482 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_1XN_ACTIVE: 9483 return "Clause 91 RS272_1XN"; 9484 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE: 9485 return "Clause 91 RS(272,257)"; 9486 } 9487 } 9488 9489 void bnxt_report_link(struct bnxt *bp) 9490 { 9491 if (BNXT_LINK_IS_UP(bp)) { 9492 const char *signal = ""; 9493 const char *flow_ctrl; 9494 const char *duplex; 9495 u32 speed; 9496 u16 fec; 9497 9498 netif_carrier_on(bp->dev); 9499 speed = bnxt_fw_to_ethtool_speed(bp->link_info.link_speed); 9500 if (speed == SPEED_UNKNOWN) { 9501 netdev_info(bp->dev, "NIC Link is Up, speed unknown\n"); 9502 return; 9503 } 9504 if (bp->link_info.duplex == BNXT_LINK_DUPLEX_FULL) 9505 duplex = "full"; 9506 else 9507 duplex = "half"; 9508 if (bp->link_info.pause == BNXT_LINK_PAUSE_BOTH) 9509 flow_ctrl = "ON - receive & transmit"; 9510 else if (bp->link_info.pause == BNXT_LINK_PAUSE_TX) 9511 flow_ctrl = "ON - transmit"; 9512 else if (bp->link_info.pause == BNXT_LINK_PAUSE_RX) 9513 flow_ctrl = "ON - receive"; 9514 else 9515 flow_ctrl = "none"; 9516 if (bp->link_info.phy_qcfg_resp.option_flags & 9517 PORT_PHY_QCFG_RESP_OPTION_FLAGS_SIGNAL_MODE_KNOWN) { 9518 u8 sig_mode = bp->link_info.active_fec_sig_mode & 9519 PORT_PHY_QCFG_RESP_SIGNAL_MODE_MASK; 9520 switch (sig_mode) { 9521 case PORT_PHY_QCFG_RESP_SIGNAL_MODE_NRZ: 9522 signal = "(NRZ) "; 9523 break; 9524 case PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4: 9525 signal = "(PAM4) "; 9526 break; 9527 default: 9528 break; 9529 } 9530 } 9531 netdev_info(bp->dev, "NIC Link is Up, %u Mbps %s%s duplex, Flow control: %s\n", 9532 speed, signal, duplex, flow_ctrl); 9533 if (bp->phy_flags & BNXT_PHY_FL_EEE_CAP) 9534 netdev_info(bp->dev, "EEE is %s\n", 9535 bp->eee.eee_active ? "active" : 9536 "not active"); 9537 fec = bp->link_info.fec_cfg; 9538 if (!(fec & PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED)) 9539 netdev_info(bp->dev, "FEC autoneg %s encoding: %s\n", 9540 (fec & BNXT_FEC_AUTONEG) ? "on" : "off", 9541 bnxt_report_fec(&bp->link_info)); 9542 } else { 9543 netif_carrier_off(bp->dev); 9544 netdev_err(bp->dev, "NIC Link is Down\n"); 9545 } 9546 } 9547 9548 static bool bnxt_phy_qcaps_no_speed(struct hwrm_port_phy_qcaps_output *resp) 9549 { 9550 if (!resp->supported_speeds_auto_mode && 9551 !resp->supported_speeds_force_mode && 9552 !resp->supported_pam4_speeds_auto_mode && 9553 !resp->supported_pam4_speeds_force_mode) 9554 return true; 9555 return false; 9556 } 9557 9558 static int bnxt_hwrm_phy_qcaps(struct bnxt *bp) 9559 { 9560 struct bnxt_link_info *link_info = &bp->link_info; 9561 struct hwrm_port_phy_qcaps_output *resp; 9562 struct hwrm_port_phy_qcaps_input *req; 9563 int rc = 0; 9564 9565 if (bp->hwrm_spec_code < 0x10201) 9566 return 0; 9567 9568 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_QCAPS); 9569 if (rc) 9570 return rc; 9571 9572 resp = hwrm_req_hold(bp, req); 9573 rc = hwrm_req_send(bp, req); 9574 if (rc) 9575 goto hwrm_phy_qcaps_exit; 9576 9577 bp->phy_flags = resp->flags | (le16_to_cpu(resp->flags2) << 8); 9578 if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED) { 9579 struct ethtool_eee *eee = &bp->eee; 9580 u16 fw_speeds = le16_to_cpu(resp->supported_speeds_eee_mode); 9581 9582 eee->supported = _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0); 9583 bp->lpi_tmr_lo = le32_to_cpu(resp->tx_lpi_timer_low) & 9584 PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK; 9585 bp->lpi_tmr_hi = le32_to_cpu(resp->valid_tx_lpi_timer_high) & 9586 PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK; 9587 } 9588 9589 if (bp->hwrm_spec_code >= 0x10a01) { 9590 if (bnxt_phy_qcaps_no_speed(resp)) { 9591 link_info->phy_state = BNXT_PHY_STATE_DISABLED; 9592 netdev_warn(bp->dev, "Ethernet link disabled\n"); 9593 } else if (link_info->phy_state == BNXT_PHY_STATE_DISABLED) { 9594 link_info->phy_state = BNXT_PHY_STATE_ENABLED; 9595 netdev_info(bp->dev, "Ethernet link enabled\n"); 9596 /* Phy re-enabled, reprobe the speeds */ 9597 link_info->support_auto_speeds = 0; 9598 link_info->support_pam4_auto_speeds = 0; 9599 } 9600 } 9601 if (resp->supported_speeds_auto_mode) 9602 link_info->support_auto_speeds = 9603 le16_to_cpu(resp->supported_speeds_auto_mode); 9604 if (resp->supported_pam4_speeds_auto_mode) 9605 link_info->support_pam4_auto_speeds = 9606 le16_to_cpu(resp->supported_pam4_speeds_auto_mode); 9607 9608 bp->port_count = resp->port_cnt; 9609 9610 hwrm_phy_qcaps_exit: 9611 hwrm_req_drop(bp, req); 9612 return rc; 9613 } 9614 9615 static bool bnxt_support_dropped(u16 advertising, u16 supported) 9616 { 9617 u16 diff = advertising ^ supported; 9618 9619 return ((supported | diff) != supported); 9620 } 9621 9622 int bnxt_update_link(struct bnxt *bp, bool chng_link_state) 9623 { 9624 struct bnxt_link_info *link_info = &bp->link_info; 9625 struct hwrm_port_phy_qcfg_output *resp; 9626 struct hwrm_port_phy_qcfg_input *req; 9627 u8 link_state = link_info->link_state; 9628 bool support_changed = false; 9629 int rc; 9630 9631 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_QCFG); 9632 if (rc) 9633 return rc; 9634 9635 resp = hwrm_req_hold(bp, req); 9636 rc = hwrm_req_send(bp, req); 9637 if (rc) { 9638 hwrm_req_drop(bp, req); 9639 if (BNXT_VF(bp) && rc == -ENODEV) { 9640 netdev_warn(bp->dev, "Cannot obtain link state while PF unavailable.\n"); 9641 rc = 0; 9642 } 9643 return rc; 9644 } 9645 9646 memcpy(&link_info->phy_qcfg_resp, resp, sizeof(*resp)); 9647 link_info->phy_link_status = resp->link; 9648 link_info->duplex = resp->duplex_cfg; 9649 if (bp->hwrm_spec_code >= 0x10800) 9650 link_info->duplex = resp->duplex_state; 9651 link_info->pause = resp->pause; 9652 link_info->auto_mode = resp->auto_mode; 9653 link_info->auto_pause_setting = resp->auto_pause; 9654 link_info->lp_pause = resp->link_partner_adv_pause; 9655 link_info->force_pause_setting = resp->force_pause; 9656 link_info->duplex_setting = resp->duplex_cfg; 9657 if (link_info->phy_link_status == BNXT_LINK_LINK) 9658 link_info->link_speed = le16_to_cpu(resp->link_speed); 9659 else 9660 link_info->link_speed = 0; 9661 link_info->force_link_speed = le16_to_cpu(resp->force_link_speed); 9662 link_info->force_pam4_link_speed = 9663 le16_to_cpu(resp->force_pam4_link_speed); 9664 link_info->support_speeds = le16_to_cpu(resp->support_speeds); 9665 link_info->support_pam4_speeds = le16_to_cpu(resp->support_pam4_speeds); 9666 link_info->auto_link_speeds = le16_to_cpu(resp->auto_link_speed_mask); 9667 link_info->auto_pam4_link_speeds = 9668 le16_to_cpu(resp->auto_pam4_link_speed_mask); 9669 link_info->lp_auto_link_speeds = 9670 le16_to_cpu(resp->link_partner_adv_speeds); 9671 link_info->lp_auto_pam4_link_speeds = 9672 resp->link_partner_pam4_adv_speeds; 9673 link_info->preemphasis = le32_to_cpu(resp->preemphasis); 9674 link_info->phy_ver[0] = resp->phy_maj; 9675 link_info->phy_ver[1] = resp->phy_min; 9676 link_info->phy_ver[2] = resp->phy_bld; 9677 link_info->media_type = resp->media_type; 9678 link_info->phy_type = resp->phy_type; 9679 link_info->transceiver = resp->xcvr_pkg_type; 9680 link_info->phy_addr = resp->eee_config_phy_addr & 9681 PORT_PHY_QCFG_RESP_PHY_ADDR_MASK; 9682 link_info->module_status = resp->module_status; 9683 9684 if (bp->phy_flags & BNXT_PHY_FL_EEE_CAP) { 9685 struct ethtool_eee *eee = &bp->eee; 9686 u16 fw_speeds; 9687 9688 eee->eee_active = 0; 9689 if (resp->eee_config_phy_addr & 9690 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE) { 9691 eee->eee_active = 1; 9692 fw_speeds = le16_to_cpu( 9693 resp->link_partner_adv_eee_link_speed_mask); 9694 eee->lp_advertised = 9695 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0); 9696 } 9697 9698 /* Pull initial EEE config */ 9699 if (!chng_link_state) { 9700 if (resp->eee_config_phy_addr & 9701 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED) 9702 eee->eee_enabled = 1; 9703 9704 fw_speeds = le16_to_cpu(resp->adv_eee_link_speed_mask); 9705 eee->advertised = 9706 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0); 9707 9708 if (resp->eee_config_phy_addr & 9709 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI) { 9710 __le32 tmr; 9711 9712 eee->tx_lpi_enabled = 1; 9713 tmr = resp->xcvr_identifier_type_tx_lpi_timer; 9714 eee->tx_lpi_timer = le32_to_cpu(tmr) & 9715 PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK; 9716 } 9717 } 9718 } 9719 9720 link_info->fec_cfg = PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED; 9721 if (bp->hwrm_spec_code >= 0x10504) { 9722 link_info->fec_cfg = le16_to_cpu(resp->fec_cfg); 9723 link_info->active_fec_sig_mode = resp->active_fec_signal_mode; 9724 } 9725 /* TODO: need to add more logic to report VF link */ 9726 if (chng_link_state) { 9727 if (link_info->phy_link_status == BNXT_LINK_LINK) 9728 link_info->link_state = BNXT_LINK_STATE_UP; 9729 else 9730 link_info->link_state = BNXT_LINK_STATE_DOWN; 9731 if (link_state != link_info->link_state) 9732 bnxt_report_link(bp); 9733 } else { 9734 /* always link down if not require to update link state */ 9735 link_info->link_state = BNXT_LINK_STATE_DOWN; 9736 } 9737 hwrm_req_drop(bp, req); 9738 9739 if (!BNXT_PHY_CFG_ABLE(bp)) 9740 return 0; 9741 9742 /* Check if any advertised speeds are no longer supported. The caller 9743 * holds the link_lock mutex, so we can modify link_info settings. 9744 */ 9745 if (bnxt_support_dropped(link_info->advertising, 9746 link_info->support_auto_speeds)) { 9747 link_info->advertising = link_info->support_auto_speeds; 9748 support_changed = true; 9749 } 9750 if (bnxt_support_dropped(link_info->advertising_pam4, 9751 link_info->support_pam4_auto_speeds)) { 9752 link_info->advertising_pam4 = link_info->support_pam4_auto_speeds; 9753 support_changed = true; 9754 } 9755 if (support_changed && (link_info->autoneg & BNXT_AUTONEG_SPEED)) 9756 bnxt_hwrm_set_link_setting(bp, true, false); 9757 return 0; 9758 } 9759 9760 static void bnxt_get_port_module_status(struct bnxt *bp) 9761 { 9762 struct bnxt_link_info *link_info = &bp->link_info; 9763 struct hwrm_port_phy_qcfg_output *resp = &link_info->phy_qcfg_resp; 9764 u8 module_status; 9765 9766 if (bnxt_update_link(bp, true)) 9767 return; 9768 9769 module_status = link_info->module_status; 9770 switch (module_status) { 9771 case PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX: 9772 case PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN: 9773 case PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG: 9774 netdev_warn(bp->dev, "Unqualified SFP+ module detected on port %d\n", 9775 bp->pf.port_id); 9776 if (bp->hwrm_spec_code >= 0x10201) { 9777 netdev_warn(bp->dev, "Module part number %s\n", 9778 resp->phy_vendor_partnumber); 9779 } 9780 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX) 9781 netdev_warn(bp->dev, "TX is disabled\n"); 9782 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN) 9783 netdev_warn(bp->dev, "SFP+ module is shutdown\n"); 9784 } 9785 } 9786 9787 static void 9788 bnxt_hwrm_set_pause_common(struct bnxt *bp, struct hwrm_port_phy_cfg_input *req) 9789 { 9790 if (bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) { 9791 if (bp->hwrm_spec_code >= 0x10201) 9792 req->auto_pause = 9793 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE; 9794 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX) 9795 req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX; 9796 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX) 9797 req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_TX; 9798 req->enables |= 9799 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE); 9800 } else { 9801 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX) 9802 req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_RX; 9803 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX) 9804 req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_TX; 9805 req->enables |= 9806 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE); 9807 if (bp->hwrm_spec_code >= 0x10201) { 9808 req->auto_pause = req->force_pause; 9809 req->enables |= cpu_to_le32( 9810 PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE); 9811 } 9812 } 9813 } 9814 9815 static void bnxt_hwrm_set_link_common(struct bnxt *bp, struct hwrm_port_phy_cfg_input *req) 9816 { 9817 if (bp->link_info.autoneg & BNXT_AUTONEG_SPEED) { 9818 req->auto_mode |= PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK; 9819 if (bp->link_info.advertising) { 9820 req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK); 9821 req->auto_link_speed_mask = cpu_to_le16(bp->link_info.advertising); 9822 } 9823 if (bp->link_info.advertising_pam4) { 9824 req->enables |= 9825 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAM4_LINK_SPEED_MASK); 9826 req->auto_link_pam4_speed_mask = 9827 cpu_to_le16(bp->link_info.advertising_pam4); 9828 } 9829 req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE); 9830 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG); 9831 } else { 9832 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE); 9833 if (bp->link_info.req_signal_mode == BNXT_SIG_MODE_PAM4) { 9834 req->force_pam4_link_speed = cpu_to_le16(bp->link_info.req_link_speed); 9835 req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAM4_LINK_SPEED); 9836 } else { 9837 req->force_link_speed = cpu_to_le16(bp->link_info.req_link_speed); 9838 } 9839 } 9840 9841 /* tell chimp that the setting takes effect immediately */ 9842 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESET_PHY); 9843 } 9844 9845 int bnxt_hwrm_set_pause(struct bnxt *bp) 9846 { 9847 struct hwrm_port_phy_cfg_input *req; 9848 int rc; 9849 9850 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_CFG); 9851 if (rc) 9852 return rc; 9853 9854 bnxt_hwrm_set_pause_common(bp, req); 9855 9856 if ((bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) || 9857 bp->link_info.force_link_chng) 9858 bnxt_hwrm_set_link_common(bp, req); 9859 9860 rc = hwrm_req_send(bp, req); 9861 if (!rc && !(bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL)) { 9862 /* since changing of pause setting doesn't trigger any link 9863 * change event, the driver needs to update the current pause 9864 * result upon successfully return of the phy_cfg command 9865 */ 9866 bp->link_info.pause = 9867 bp->link_info.force_pause_setting = bp->link_info.req_flow_ctrl; 9868 bp->link_info.auto_pause_setting = 0; 9869 if (!bp->link_info.force_link_chng) 9870 bnxt_report_link(bp); 9871 } 9872 bp->link_info.force_link_chng = false; 9873 return rc; 9874 } 9875 9876 static void bnxt_hwrm_set_eee(struct bnxt *bp, 9877 struct hwrm_port_phy_cfg_input *req) 9878 { 9879 struct ethtool_eee *eee = &bp->eee; 9880 9881 if (eee->eee_enabled) { 9882 u16 eee_speeds; 9883 u32 flags = PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE; 9884 9885 if (eee->tx_lpi_enabled) 9886 flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE; 9887 else 9888 flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE; 9889 9890 req->flags |= cpu_to_le32(flags); 9891 eee_speeds = bnxt_get_fw_auto_link_speeds(eee->advertised); 9892 req->eee_link_speed_mask = cpu_to_le16(eee_speeds); 9893 req->tx_lpi_timer = cpu_to_le32(eee->tx_lpi_timer); 9894 } else { 9895 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE); 9896 } 9897 } 9898 9899 int bnxt_hwrm_set_link_setting(struct bnxt *bp, bool set_pause, bool set_eee) 9900 { 9901 struct hwrm_port_phy_cfg_input *req; 9902 int rc; 9903 9904 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_CFG); 9905 if (rc) 9906 return rc; 9907 9908 if (set_pause) 9909 bnxt_hwrm_set_pause_common(bp, req); 9910 9911 bnxt_hwrm_set_link_common(bp, req); 9912 9913 if (set_eee) 9914 bnxt_hwrm_set_eee(bp, req); 9915 return hwrm_req_send(bp, req); 9916 } 9917 9918 static int bnxt_hwrm_shutdown_link(struct bnxt *bp) 9919 { 9920 struct hwrm_port_phy_cfg_input *req; 9921 int rc; 9922 9923 if (!BNXT_SINGLE_PF(bp)) 9924 return 0; 9925 9926 if (pci_num_vf(bp->pdev) && 9927 !(bp->phy_flags & BNXT_PHY_FL_FW_MANAGED_LKDN)) 9928 return 0; 9929 9930 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_CFG); 9931 if (rc) 9932 return rc; 9933 9934 req->flags = cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN); 9935 rc = hwrm_req_send(bp, req); 9936 if (!rc) { 9937 mutex_lock(&bp->link_lock); 9938 /* Device is not obliged link down in certain scenarios, even 9939 * when forced. Setting the state unknown is consistent with 9940 * driver startup and will force link state to be reported 9941 * during subsequent open based on PORT_PHY_QCFG. 9942 */ 9943 bp->link_info.link_state = BNXT_LINK_STATE_UNKNOWN; 9944 mutex_unlock(&bp->link_lock); 9945 } 9946 return rc; 9947 } 9948 9949 static int bnxt_fw_reset_via_optee(struct bnxt *bp) 9950 { 9951 #ifdef CONFIG_TEE_BNXT_FW 9952 int rc = tee_bnxt_fw_load(); 9953 9954 if (rc) 9955 netdev_err(bp->dev, "Failed FW reset via OP-TEE, rc=%d\n", rc); 9956 9957 return rc; 9958 #else 9959 netdev_err(bp->dev, "OP-TEE not supported\n"); 9960 return -ENODEV; 9961 #endif 9962 } 9963 9964 static int bnxt_try_recover_fw(struct bnxt *bp) 9965 { 9966 if (bp->fw_health && bp->fw_health->status_reliable) { 9967 int retry = 0, rc; 9968 u32 sts; 9969 9970 do { 9971 sts = bnxt_fw_health_readl(bp, BNXT_FW_HEALTH_REG); 9972 rc = bnxt_hwrm_poll(bp); 9973 if (!BNXT_FW_IS_BOOTING(sts) && 9974 !BNXT_FW_IS_RECOVERING(sts)) 9975 break; 9976 retry++; 9977 } while (rc == -EBUSY && retry < BNXT_FW_RETRY); 9978 9979 if (!BNXT_FW_IS_HEALTHY(sts)) { 9980 netdev_err(bp->dev, 9981 "Firmware not responding, status: 0x%x\n", 9982 sts); 9983 rc = -ENODEV; 9984 } 9985 if (sts & FW_STATUS_REG_CRASHED_NO_MASTER) { 9986 netdev_warn(bp->dev, "Firmware recover via OP-TEE requested\n"); 9987 return bnxt_fw_reset_via_optee(bp); 9988 } 9989 return rc; 9990 } 9991 9992 return -ENODEV; 9993 } 9994 9995 static void bnxt_clear_reservations(struct bnxt *bp, bool fw_reset) 9996 { 9997 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 9998 9999 if (!BNXT_NEW_RM(bp)) 10000 return; /* no resource reservations required */ 10001 10002 hw_resc->resv_cp_rings = 0; 10003 hw_resc->resv_stat_ctxs = 0; 10004 hw_resc->resv_irqs = 0; 10005 hw_resc->resv_tx_rings = 0; 10006 hw_resc->resv_rx_rings = 0; 10007 hw_resc->resv_hw_ring_grps = 0; 10008 hw_resc->resv_vnics = 0; 10009 if (!fw_reset) { 10010 bp->tx_nr_rings = 0; 10011 bp->rx_nr_rings = 0; 10012 } 10013 } 10014 10015 int bnxt_cancel_reservations(struct bnxt *bp, bool fw_reset) 10016 { 10017 int rc; 10018 10019 if (!BNXT_NEW_RM(bp)) 10020 return 0; /* no resource reservations required */ 10021 10022 rc = bnxt_hwrm_func_resc_qcaps(bp, true); 10023 if (rc) 10024 netdev_err(bp->dev, "resc_qcaps failed\n"); 10025 10026 bnxt_clear_reservations(bp, fw_reset); 10027 10028 return rc; 10029 } 10030 10031 static int bnxt_hwrm_if_change(struct bnxt *bp, bool up) 10032 { 10033 struct hwrm_func_drv_if_change_output *resp; 10034 struct hwrm_func_drv_if_change_input *req; 10035 bool fw_reset = !bp->irq_tbl; 10036 bool resc_reinit = false; 10037 int rc, retry = 0; 10038 u32 flags = 0; 10039 10040 if (!(bp->fw_cap & BNXT_FW_CAP_IF_CHANGE)) 10041 return 0; 10042 10043 rc = hwrm_req_init(bp, req, HWRM_FUNC_DRV_IF_CHANGE); 10044 if (rc) 10045 return rc; 10046 10047 if (up) 10048 req->flags = cpu_to_le32(FUNC_DRV_IF_CHANGE_REQ_FLAGS_UP); 10049 resp = hwrm_req_hold(bp, req); 10050 10051 hwrm_req_flags(bp, req, BNXT_HWRM_FULL_WAIT); 10052 while (retry < BNXT_FW_IF_RETRY) { 10053 rc = hwrm_req_send(bp, req); 10054 if (rc != -EAGAIN) 10055 break; 10056 10057 msleep(50); 10058 retry++; 10059 } 10060 10061 if (rc == -EAGAIN) { 10062 hwrm_req_drop(bp, req); 10063 return rc; 10064 } else if (!rc) { 10065 flags = le32_to_cpu(resp->flags); 10066 } else if (up) { 10067 rc = bnxt_try_recover_fw(bp); 10068 fw_reset = true; 10069 } 10070 hwrm_req_drop(bp, req); 10071 if (rc) 10072 return rc; 10073 10074 if (!up) { 10075 bnxt_inv_fw_health_reg(bp); 10076 return 0; 10077 } 10078 10079 if (flags & FUNC_DRV_IF_CHANGE_RESP_FLAGS_RESC_CHANGE) 10080 resc_reinit = true; 10081 if (flags & FUNC_DRV_IF_CHANGE_RESP_FLAGS_HOT_FW_RESET_DONE || 10082 test_bit(BNXT_STATE_FW_RESET_DET, &bp->state)) 10083 fw_reset = true; 10084 else 10085 bnxt_remap_fw_health_regs(bp); 10086 10087 if (test_bit(BNXT_STATE_IN_FW_RESET, &bp->state) && !fw_reset) { 10088 netdev_err(bp->dev, "RESET_DONE not set during FW reset.\n"); 10089 set_bit(BNXT_STATE_ABORT_ERR, &bp->state); 10090 return -ENODEV; 10091 } 10092 if (resc_reinit || fw_reset) { 10093 if (fw_reset) { 10094 set_bit(BNXT_STATE_FW_RESET_DET, &bp->state); 10095 if (!test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) 10096 bnxt_ulp_stop(bp); 10097 bnxt_free_ctx_mem(bp); 10098 kfree(bp->ctx); 10099 bp->ctx = NULL; 10100 bnxt_dcb_free(bp); 10101 rc = bnxt_fw_init_one(bp); 10102 if (rc) { 10103 clear_bit(BNXT_STATE_FW_RESET_DET, &bp->state); 10104 set_bit(BNXT_STATE_ABORT_ERR, &bp->state); 10105 return rc; 10106 } 10107 bnxt_clear_int_mode(bp); 10108 rc = bnxt_init_int_mode(bp); 10109 if (rc) { 10110 clear_bit(BNXT_STATE_FW_RESET_DET, &bp->state); 10111 netdev_err(bp->dev, "init int mode failed\n"); 10112 return rc; 10113 } 10114 } 10115 rc = bnxt_cancel_reservations(bp, fw_reset); 10116 } 10117 return rc; 10118 } 10119 10120 static int bnxt_hwrm_port_led_qcaps(struct bnxt *bp) 10121 { 10122 struct hwrm_port_led_qcaps_output *resp; 10123 struct hwrm_port_led_qcaps_input *req; 10124 struct bnxt_pf_info *pf = &bp->pf; 10125 int rc; 10126 10127 bp->num_leds = 0; 10128 if (BNXT_VF(bp) || bp->hwrm_spec_code < 0x10601) 10129 return 0; 10130 10131 rc = hwrm_req_init(bp, req, HWRM_PORT_LED_QCAPS); 10132 if (rc) 10133 return rc; 10134 10135 req->port_id = cpu_to_le16(pf->port_id); 10136 resp = hwrm_req_hold(bp, req); 10137 rc = hwrm_req_send(bp, req); 10138 if (rc) { 10139 hwrm_req_drop(bp, req); 10140 return rc; 10141 } 10142 if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) { 10143 int i; 10144 10145 bp->num_leds = resp->num_leds; 10146 memcpy(bp->leds, &resp->led0_id, sizeof(bp->leds[0]) * 10147 bp->num_leds); 10148 for (i = 0; i < bp->num_leds; i++) { 10149 struct bnxt_led_info *led = &bp->leds[i]; 10150 __le16 caps = led->led_state_caps; 10151 10152 if (!led->led_group_id || 10153 !BNXT_LED_ALT_BLINK_CAP(caps)) { 10154 bp->num_leds = 0; 10155 break; 10156 } 10157 } 10158 } 10159 hwrm_req_drop(bp, req); 10160 return 0; 10161 } 10162 10163 int bnxt_hwrm_alloc_wol_fltr(struct bnxt *bp) 10164 { 10165 struct hwrm_wol_filter_alloc_output *resp; 10166 struct hwrm_wol_filter_alloc_input *req; 10167 int rc; 10168 10169 rc = hwrm_req_init(bp, req, HWRM_WOL_FILTER_ALLOC); 10170 if (rc) 10171 return rc; 10172 10173 req->port_id = cpu_to_le16(bp->pf.port_id); 10174 req->wol_type = WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT; 10175 req->enables = cpu_to_le32(WOL_FILTER_ALLOC_REQ_ENABLES_MAC_ADDRESS); 10176 memcpy(req->mac_address, bp->dev->dev_addr, ETH_ALEN); 10177 10178 resp = hwrm_req_hold(bp, req); 10179 rc = hwrm_req_send(bp, req); 10180 if (!rc) 10181 bp->wol_filter_id = resp->wol_filter_id; 10182 hwrm_req_drop(bp, req); 10183 return rc; 10184 } 10185 10186 int bnxt_hwrm_free_wol_fltr(struct bnxt *bp) 10187 { 10188 struct hwrm_wol_filter_free_input *req; 10189 int rc; 10190 10191 rc = hwrm_req_init(bp, req, HWRM_WOL_FILTER_FREE); 10192 if (rc) 10193 return rc; 10194 10195 req->port_id = cpu_to_le16(bp->pf.port_id); 10196 req->enables = cpu_to_le32(WOL_FILTER_FREE_REQ_ENABLES_WOL_FILTER_ID); 10197 req->wol_filter_id = bp->wol_filter_id; 10198 10199 return hwrm_req_send(bp, req); 10200 } 10201 10202 static u16 bnxt_hwrm_get_wol_fltrs(struct bnxt *bp, u16 handle) 10203 { 10204 struct hwrm_wol_filter_qcfg_output *resp; 10205 struct hwrm_wol_filter_qcfg_input *req; 10206 u16 next_handle = 0; 10207 int rc; 10208 10209 rc = hwrm_req_init(bp, req, HWRM_WOL_FILTER_QCFG); 10210 if (rc) 10211 return rc; 10212 10213 req->port_id = cpu_to_le16(bp->pf.port_id); 10214 req->handle = cpu_to_le16(handle); 10215 resp = hwrm_req_hold(bp, req); 10216 rc = hwrm_req_send(bp, req); 10217 if (!rc) { 10218 next_handle = le16_to_cpu(resp->next_handle); 10219 if (next_handle != 0) { 10220 if (resp->wol_type == 10221 WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT) { 10222 bp->wol = 1; 10223 bp->wol_filter_id = resp->wol_filter_id; 10224 } 10225 } 10226 } 10227 hwrm_req_drop(bp, req); 10228 return next_handle; 10229 } 10230 10231 static void bnxt_get_wol_settings(struct bnxt *bp) 10232 { 10233 u16 handle = 0; 10234 10235 bp->wol = 0; 10236 if (!BNXT_PF(bp) || !(bp->flags & BNXT_FLAG_WOL_CAP)) 10237 return; 10238 10239 do { 10240 handle = bnxt_hwrm_get_wol_fltrs(bp, handle); 10241 } while (handle && handle != 0xffff); 10242 } 10243 10244 #ifdef CONFIG_BNXT_HWMON 10245 static ssize_t bnxt_show_temp(struct device *dev, 10246 struct device_attribute *devattr, char *buf) 10247 { 10248 struct hwrm_temp_monitor_query_output *resp; 10249 struct hwrm_temp_monitor_query_input *req; 10250 struct bnxt *bp = dev_get_drvdata(dev); 10251 u32 len = 0; 10252 int rc; 10253 10254 rc = hwrm_req_init(bp, req, HWRM_TEMP_MONITOR_QUERY); 10255 if (rc) 10256 return rc; 10257 resp = hwrm_req_hold(bp, req); 10258 rc = hwrm_req_send(bp, req); 10259 if (!rc) 10260 len = sprintf(buf, "%u\n", resp->temp * 1000); /* display millidegree */ 10261 hwrm_req_drop(bp, req); 10262 if (rc) 10263 return rc; 10264 return len; 10265 } 10266 static SENSOR_DEVICE_ATTR(temp1_input, 0444, bnxt_show_temp, NULL, 0); 10267 10268 static struct attribute *bnxt_attrs[] = { 10269 &sensor_dev_attr_temp1_input.dev_attr.attr, 10270 NULL 10271 }; 10272 ATTRIBUTE_GROUPS(bnxt); 10273 10274 static void bnxt_hwmon_close(struct bnxt *bp) 10275 { 10276 if (bp->hwmon_dev) { 10277 hwmon_device_unregister(bp->hwmon_dev); 10278 bp->hwmon_dev = NULL; 10279 } 10280 } 10281 10282 static void bnxt_hwmon_open(struct bnxt *bp) 10283 { 10284 struct hwrm_temp_monitor_query_input *req; 10285 struct pci_dev *pdev = bp->pdev; 10286 int rc; 10287 10288 rc = hwrm_req_init(bp, req, HWRM_TEMP_MONITOR_QUERY); 10289 if (!rc) 10290 rc = hwrm_req_send_silent(bp, req); 10291 if (rc == -EACCES || rc == -EOPNOTSUPP) { 10292 bnxt_hwmon_close(bp); 10293 return; 10294 } 10295 10296 if (bp->hwmon_dev) 10297 return; 10298 10299 bp->hwmon_dev = hwmon_device_register_with_groups(&pdev->dev, 10300 DRV_MODULE_NAME, bp, 10301 bnxt_groups); 10302 if (IS_ERR(bp->hwmon_dev)) { 10303 bp->hwmon_dev = NULL; 10304 dev_warn(&pdev->dev, "Cannot register hwmon device\n"); 10305 } 10306 } 10307 #else 10308 static void bnxt_hwmon_close(struct bnxt *bp) 10309 { 10310 } 10311 10312 static void bnxt_hwmon_open(struct bnxt *bp) 10313 { 10314 } 10315 #endif 10316 10317 static bool bnxt_eee_config_ok(struct bnxt *bp) 10318 { 10319 struct ethtool_eee *eee = &bp->eee; 10320 struct bnxt_link_info *link_info = &bp->link_info; 10321 10322 if (!(bp->phy_flags & BNXT_PHY_FL_EEE_CAP)) 10323 return true; 10324 10325 if (eee->eee_enabled) { 10326 u32 advertising = 10327 _bnxt_fw_to_ethtool_adv_spds(link_info->advertising, 0); 10328 10329 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) { 10330 eee->eee_enabled = 0; 10331 return false; 10332 } 10333 if (eee->advertised & ~advertising) { 10334 eee->advertised = advertising & eee->supported; 10335 return false; 10336 } 10337 } 10338 return true; 10339 } 10340 10341 static int bnxt_update_phy_setting(struct bnxt *bp) 10342 { 10343 int rc; 10344 bool update_link = false; 10345 bool update_pause = false; 10346 bool update_eee = false; 10347 struct bnxt_link_info *link_info = &bp->link_info; 10348 10349 rc = bnxt_update_link(bp, true); 10350 if (rc) { 10351 netdev_err(bp->dev, "failed to update link (rc: %x)\n", 10352 rc); 10353 return rc; 10354 } 10355 if (!BNXT_SINGLE_PF(bp)) 10356 return 0; 10357 10358 if ((link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) && 10359 (link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH) != 10360 link_info->req_flow_ctrl) 10361 update_pause = true; 10362 if (!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) && 10363 link_info->force_pause_setting != link_info->req_flow_ctrl) 10364 update_pause = true; 10365 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) { 10366 if (BNXT_AUTO_MODE(link_info->auto_mode)) 10367 update_link = true; 10368 if (link_info->req_signal_mode == BNXT_SIG_MODE_NRZ && 10369 link_info->req_link_speed != link_info->force_link_speed) 10370 update_link = true; 10371 else if (link_info->req_signal_mode == BNXT_SIG_MODE_PAM4 && 10372 link_info->req_link_speed != link_info->force_pam4_link_speed) 10373 update_link = true; 10374 if (link_info->req_duplex != link_info->duplex_setting) 10375 update_link = true; 10376 } else { 10377 if (link_info->auto_mode == BNXT_LINK_AUTO_NONE) 10378 update_link = true; 10379 if (link_info->advertising != link_info->auto_link_speeds || 10380 link_info->advertising_pam4 != link_info->auto_pam4_link_speeds) 10381 update_link = true; 10382 } 10383 10384 /* The last close may have shutdown the link, so need to call 10385 * PHY_CFG to bring it back up. 10386 */ 10387 if (!BNXT_LINK_IS_UP(bp)) 10388 update_link = true; 10389 10390 if (!bnxt_eee_config_ok(bp)) 10391 update_eee = true; 10392 10393 if (update_link) 10394 rc = bnxt_hwrm_set_link_setting(bp, update_pause, update_eee); 10395 else if (update_pause) 10396 rc = bnxt_hwrm_set_pause(bp); 10397 if (rc) { 10398 netdev_err(bp->dev, "failed to update phy setting (rc: %x)\n", 10399 rc); 10400 return rc; 10401 } 10402 10403 return rc; 10404 } 10405 10406 /* Common routine to pre-map certain register block to different GRC window. 10407 * A PF has 16 4K windows and a VF has 4 4K windows. However, only 15 windows 10408 * in PF and 3 windows in VF that can be customized to map in different 10409 * register blocks. 10410 */ 10411 static void bnxt_preset_reg_win(struct bnxt *bp) 10412 { 10413 if (BNXT_PF(bp)) { 10414 /* CAG registers map to GRC window #4 */ 10415 writel(BNXT_CAG_REG_BASE, 10416 bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 12); 10417 } 10418 } 10419 10420 static int bnxt_init_dflt_ring_mode(struct bnxt *bp); 10421 10422 static int bnxt_reinit_after_abort(struct bnxt *bp) 10423 { 10424 int rc; 10425 10426 if (test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) 10427 return -EBUSY; 10428 10429 if (bp->dev->reg_state == NETREG_UNREGISTERED) 10430 return -ENODEV; 10431 10432 rc = bnxt_fw_init_one(bp); 10433 if (!rc) { 10434 bnxt_clear_int_mode(bp); 10435 rc = bnxt_init_int_mode(bp); 10436 if (!rc) { 10437 clear_bit(BNXT_STATE_ABORT_ERR, &bp->state); 10438 set_bit(BNXT_STATE_FW_RESET_DET, &bp->state); 10439 } 10440 } 10441 return rc; 10442 } 10443 10444 static int __bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init) 10445 { 10446 int rc = 0; 10447 10448 bnxt_preset_reg_win(bp); 10449 netif_carrier_off(bp->dev); 10450 if (irq_re_init) { 10451 /* Reserve rings now if none were reserved at driver probe. */ 10452 rc = bnxt_init_dflt_ring_mode(bp); 10453 if (rc) { 10454 netdev_err(bp->dev, "Failed to reserve default rings at open\n"); 10455 return rc; 10456 } 10457 } 10458 rc = bnxt_reserve_rings(bp, irq_re_init); 10459 if (rc) 10460 return rc; 10461 if ((bp->flags & BNXT_FLAG_RFS) && 10462 !(bp->flags & BNXT_FLAG_USING_MSIX)) { 10463 /* disable RFS if falling back to INTA */ 10464 bp->dev->hw_features &= ~NETIF_F_NTUPLE; 10465 bp->flags &= ~BNXT_FLAG_RFS; 10466 } 10467 10468 rc = bnxt_alloc_mem(bp, irq_re_init); 10469 if (rc) { 10470 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc); 10471 goto open_err_free_mem; 10472 } 10473 10474 if (irq_re_init) { 10475 bnxt_init_napi(bp); 10476 rc = bnxt_request_irq(bp); 10477 if (rc) { 10478 netdev_err(bp->dev, "bnxt_request_irq err: %x\n", rc); 10479 goto open_err_irq; 10480 } 10481 } 10482 10483 rc = bnxt_init_nic(bp, irq_re_init); 10484 if (rc) { 10485 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc); 10486 goto open_err_irq; 10487 } 10488 10489 bnxt_enable_napi(bp); 10490 bnxt_debug_dev_init(bp); 10491 10492 if (link_re_init) { 10493 mutex_lock(&bp->link_lock); 10494 rc = bnxt_update_phy_setting(bp); 10495 mutex_unlock(&bp->link_lock); 10496 if (rc) { 10497 netdev_warn(bp->dev, "failed to update phy settings\n"); 10498 if (BNXT_SINGLE_PF(bp)) { 10499 bp->link_info.phy_retry = true; 10500 bp->link_info.phy_retry_expires = 10501 jiffies + 5 * HZ; 10502 } 10503 } 10504 } 10505 10506 if (irq_re_init) 10507 udp_tunnel_nic_reset_ntf(bp->dev); 10508 10509 if (bp->tx_nr_rings_xdp < num_possible_cpus()) { 10510 if (!static_key_enabled(&bnxt_xdp_locking_key)) 10511 static_branch_enable(&bnxt_xdp_locking_key); 10512 } else if (static_key_enabled(&bnxt_xdp_locking_key)) { 10513 static_branch_disable(&bnxt_xdp_locking_key); 10514 } 10515 set_bit(BNXT_STATE_OPEN, &bp->state); 10516 bnxt_enable_int(bp); 10517 /* Enable TX queues */ 10518 bnxt_tx_enable(bp); 10519 mod_timer(&bp->timer, jiffies + bp->current_interval); 10520 /* Poll link status and check for SFP+ module status */ 10521 mutex_lock(&bp->link_lock); 10522 bnxt_get_port_module_status(bp); 10523 mutex_unlock(&bp->link_lock); 10524 10525 /* VF-reps may need to be re-opened after the PF is re-opened */ 10526 if (BNXT_PF(bp)) 10527 bnxt_vf_reps_open(bp); 10528 bnxt_ptp_init_rtc(bp, true); 10529 bnxt_ptp_cfg_tstamp_filters(bp); 10530 return 0; 10531 10532 open_err_irq: 10533 bnxt_del_napi(bp); 10534 10535 open_err_free_mem: 10536 bnxt_free_skbs(bp); 10537 bnxt_free_irq(bp); 10538 bnxt_free_mem(bp, true); 10539 return rc; 10540 } 10541 10542 /* rtnl_lock held */ 10543 int bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init) 10544 { 10545 int rc = 0; 10546 10547 if (test_bit(BNXT_STATE_ABORT_ERR, &bp->state)) 10548 rc = -EIO; 10549 if (!rc) 10550 rc = __bnxt_open_nic(bp, irq_re_init, link_re_init); 10551 if (rc) { 10552 netdev_err(bp->dev, "nic open fail (rc: %x)\n", rc); 10553 dev_close(bp->dev); 10554 } 10555 return rc; 10556 } 10557 10558 /* rtnl_lock held, open the NIC half way by allocating all resources, but 10559 * NAPI, IRQ, and TX are not enabled. This is mainly used for offline 10560 * self tests. 10561 */ 10562 int bnxt_half_open_nic(struct bnxt *bp) 10563 { 10564 int rc = 0; 10565 10566 if (test_bit(BNXT_STATE_ABORT_ERR, &bp->state)) { 10567 netdev_err(bp->dev, "A previous firmware reset has not completed, aborting half open\n"); 10568 rc = -ENODEV; 10569 goto half_open_err; 10570 } 10571 10572 rc = bnxt_alloc_mem(bp, true); 10573 if (rc) { 10574 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc); 10575 goto half_open_err; 10576 } 10577 set_bit(BNXT_STATE_HALF_OPEN, &bp->state); 10578 rc = bnxt_init_nic(bp, true); 10579 if (rc) { 10580 clear_bit(BNXT_STATE_HALF_OPEN, &bp->state); 10581 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc); 10582 goto half_open_err; 10583 } 10584 return 0; 10585 10586 half_open_err: 10587 bnxt_free_skbs(bp); 10588 bnxt_free_mem(bp, true); 10589 dev_close(bp->dev); 10590 return rc; 10591 } 10592 10593 /* rtnl_lock held, this call can only be made after a previous successful 10594 * call to bnxt_half_open_nic(). 10595 */ 10596 void bnxt_half_close_nic(struct bnxt *bp) 10597 { 10598 bnxt_hwrm_resource_free(bp, false, true); 10599 bnxt_free_skbs(bp); 10600 bnxt_free_mem(bp, true); 10601 clear_bit(BNXT_STATE_HALF_OPEN, &bp->state); 10602 } 10603 10604 void bnxt_reenable_sriov(struct bnxt *bp) 10605 { 10606 if (BNXT_PF(bp)) { 10607 struct bnxt_pf_info *pf = &bp->pf; 10608 int n = pf->active_vfs; 10609 10610 if (n) 10611 bnxt_cfg_hw_sriov(bp, &n, true); 10612 } 10613 } 10614 10615 static int bnxt_open(struct net_device *dev) 10616 { 10617 struct bnxt *bp = netdev_priv(dev); 10618 int rc; 10619 10620 if (test_bit(BNXT_STATE_ABORT_ERR, &bp->state)) { 10621 rc = bnxt_reinit_after_abort(bp); 10622 if (rc) { 10623 if (rc == -EBUSY) 10624 netdev_err(bp->dev, "A previous firmware reset has not completed, aborting\n"); 10625 else 10626 netdev_err(bp->dev, "Failed to reinitialize after aborted firmware reset\n"); 10627 return -ENODEV; 10628 } 10629 } 10630 10631 rc = bnxt_hwrm_if_change(bp, true); 10632 if (rc) 10633 return rc; 10634 10635 rc = __bnxt_open_nic(bp, true, true); 10636 if (rc) { 10637 bnxt_hwrm_if_change(bp, false); 10638 } else { 10639 if (test_and_clear_bit(BNXT_STATE_FW_RESET_DET, &bp->state)) { 10640 if (!test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) { 10641 bnxt_ulp_start(bp, 0); 10642 bnxt_reenable_sriov(bp); 10643 } 10644 } 10645 bnxt_hwmon_open(bp); 10646 } 10647 10648 return rc; 10649 } 10650 10651 static bool bnxt_drv_busy(struct bnxt *bp) 10652 { 10653 return (test_bit(BNXT_STATE_IN_SP_TASK, &bp->state) || 10654 test_bit(BNXT_STATE_READ_STATS, &bp->state)); 10655 } 10656 10657 static void bnxt_get_ring_stats(struct bnxt *bp, 10658 struct rtnl_link_stats64 *stats); 10659 10660 static void __bnxt_close_nic(struct bnxt *bp, bool irq_re_init, 10661 bool link_re_init) 10662 { 10663 /* Close the VF-reps before closing PF */ 10664 if (BNXT_PF(bp)) 10665 bnxt_vf_reps_close(bp); 10666 10667 /* Change device state to avoid TX queue wake up's */ 10668 bnxt_tx_disable(bp); 10669 10670 clear_bit(BNXT_STATE_OPEN, &bp->state); 10671 smp_mb__after_atomic(); 10672 while (bnxt_drv_busy(bp)) 10673 msleep(20); 10674 10675 /* Flush rings and disable interrupts */ 10676 bnxt_shutdown_nic(bp, irq_re_init); 10677 10678 /* TODO CHIMP_FW: Link/PHY related cleanup if (link_re_init) */ 10679 10680 bnxt_debug_dev_exit(bp); 10681 bnxt_disable_napi(bp); 10682 del_timer_sync(&bp->timer); 10683 bnxt_free_skbs(bp); 10684 10685 /* Save ring stats before shutdown */ 10686 if (bp->bnapi && irq_re_init) 10687 bnxt_get_ring_stats(bp, &bp->net_stats_prev); 10688 if (irq_re_init) { 10689 bnxt_free_irq(bp); 10690 bnxt_del_napi(bp); 10691 } 10692 bnxt_free_mem(bp, irq_re_init); 10693 } 10694 10695 int bnxt_close_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init) 10696 { 10697 int rc = 0; 10698 10699 if (test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) { 10700 /* If we get here, it means firmware reset is in progress 10701 * while we are trying to close. We can safely proceed with 10702 * the close because we are holding rtnl_lock(). Some firmware 10703 * messages may fail as we proceed to close. We set the 10704 * ABORT_ERR flag here so that the FW reset thread will later 10705 * abort when it gets the rtnl_lock() and sees the flag. 10706 */ 10707 netdev_warn(bp->dev, "FW reset in progress during close, FW reset will be aborted\n"); 10708 set_bit(BNXT_STATE_ABORT_ERR, &bp->state); 10709 } 10710 10711 #ifdef CONFIG_BNXT_SRIOV 10712 if (bp->sriov_cfg) { 10713 rc = wait_event_interruptible_timeout(bp->sriov_cfg_wait, 10714 !bp->sriov_cfg, 10715 BNXT_SRIOV_CFG_WAIT_TMO); 10716 if (rc) 10717 netdev_warn(bp->dev, "timeout waiting for SRIOV config operation to complete!\n"); 10718 } 10719 #endif 10720 __bnxt_close_nic(bp, irq_re_init, link_re_init); 10721 return rc; 10722 } 10723 10724 static int bnxt_close(struct net_device *dev) 10725 { 10726 struct bnxt *bp = netdev_priv(dev); 10727 10728 bnxt_hwmon_close(bp); 10729 bnxt_close_nic(bp, true, true); 10730 bnxt_hwrm_shutdown_link(bp); 10731 bnxt_hwrm_if_change(bp, false); 10732 return 0; 10733 } 10734 10735 static int bnxt_hwrm_port_phy_read(struct bnxt *bp, u16 phy_addr, u16 reg, 10736 u16 *val) 10737 { 10738 struct hwrm_port_phy_mdio_read_output *resp; 10739 struct hwrm_port_phy_mdio_read_input *req; 10740 int rc; 10741 10742 if (bp->hwrm_spec_code < 0x10a00) 10743 return -EOPNOTSUPP; 10744 10745 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_MDIO_READ); 10746 if (rc) 10747 return rc; 10748 10749 req->port_id = cpu_to_le16(bp->pf.port_id); 10750 req->phy_addr = phy_addr; 10751 req->reg_addr = cpu_to_le16(reg & 0x1f); 10752 if (mdio_phy_id_is_c45(phy_addr)) { 10753 req->cl45_mdio = 1; 10754 req->phy_addr = mdio_phy_id_prtad(phy_addr); 10755 req->dev_addr = mdio_phy_id_devad(phy_addr); 10756 req->reg_addr = cpu_to_le16(reg); 10757 } 10758 10759 resp = hwrm_req_hold(bp, req); 10760 rc = hwrm_req_send(bp, req); 10761 if (!rc) 10762 *val = le16_to_cpu(resp->reg_data); 10763 hwrm_req_drop(bp, req); 10764 return rc; 10765 } 10766 10767 static int bnxt_hwrm_port_phy_write(struct bnxt *bp, u16 phy_addr, u16 reg, 10768 u16 val) 10769 { 10770 struct hwrm_port_phy_mdio_write_input *req; 10771 int rc; 10772 10773 if (bp->hwrm_spec_code < 0x10a00) 10774 return -EOPNOTSUPP; 10775 10776 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_MDIO_WRITE); 10777 if (rc) 10778 return rc; 10779 10780 req->port_id = cpu_to_le16(bp->pf.port_id); 10781 req->phy_addr = phy_addr; 10782 req->reg_addr = cpu_to_le16(reg & 0x1f); 10783 if (mdio_phy_id_is_c45(phy_addr)) { 10784 req->cl45_mdio = 1; 10785 req->phy_addr = mdio_phy_id_prtad(phy_addr); 10786 req->dev_addr = mdio_phy_id_devad(phy_addr); 10787 req->reg_addr = cpu_to_le16(reg); 10788 } 10789 req->reg_data = cpu_to_le16(val); 10790 10791 return hwrm_req_send(bp, req); 10792 } 10793 10794 /* rtnl_lock held */ 10795 static int bnxt_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 10796 { 10797 struct mii_ioctl_data *mdio = if_mii(ifr); 10798 struct bnxt *bp = netdev_priv(dev); 10799 int rc; 10800 10801 switch (cmd) { 10802 case SIOCGMIIPHY: 10803 mdio->phy_id = bp->link_info.phy_addr; 10804 10805 fallthrough; 10806 case SIOCGMIIREG: { 10807 u16 mii_regval = 0; 10808 10809 if (!netif_running(dev)) 10810 return -EAGAIN; 10811 10812 rc = bnxt_hwrm_port_phy_read(bp, mdio->phy_id, mdio->reg_num, 10813 &mii_regval); 10814 mdio->val_out = mii_regval; 10815 return rc; 10816 } 10817 10818 case SIOCSMIIREG: 10819 if (!netif_running(dev)) 10820 return -EAGAIN; 10821 10822 return bnxt_hwrm_port_phy_write(bp, mdio->phy_id, mdio->reg_num, 10823 mdio->val_in); 10824 10825 case SIOCSHWTSTAMP: 10826 return bnxt_hwtstamp_set(dev, ifr); 10827 10828 case SIOCGHWTSTAMP: 10829 return bnxt_hwtstamp_get(dev, ifr); 10830 10831 default: 10832 /* do nothing */ 10833 break; 10834 } 10835 return -EOPNOTSUPP; 10836 } 10837 10838 static void bnxt_get_ring_stats(struct bnxt *bp, 10839 struct rtnl_link_stats64 *stats) 10840 { 10841 int i; 10842 10843 for (i = 0; i < bp->cp_nr_rings; i++) { 10844 struct bnxt_napi *bnapi = bp->bnapi[i]; 10845 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 10846 u64 *sw = cpr->stats.sw_stats; 10847 10848 stats->rx_packets += BNXT_GET_RING_STATS64(sw, rx_ucast_pkts); 10849 stats->rx_packets += BNXT_GET_RING_STATS64(sw, rx_mcast_pkts); 10850 stats->rx_packets += BNXT_GET_RING_STATS64(sw, rx_bcast_pkts); 10851 10852 stats->tx_packets += BNXT_GET_RING_STATS64(sw, tx_ucast_pkts); 10853 stats->tx_packets += BNXT_GET_RING_STATS64(sw, tx_mcast_pkts); 10854 stats->tx_packets += BNXT_GET_RING_STATS64(sw, tx_bcast_pkts); 10855 10856 stats->rx_bytes += BNXT_GET_RING_STATS64(sw, rx_ucast_bytes); 10857 stats->rx_bytes += BNXT_GET_RING_STATS64(sw, rx_mcast_bytes); 10858 stats->rx_bytes += BNXT_GET_RING_STATS64(sw, rx_bcast_bytes); 10859 10860 stats->tx_bytes += BNXT_GET_RING_STATS64(sw, tx_ucast_bytes); 10861 stats->tx_bytes += BNXT_GET_RING_STATS64(sw, tx_mcast_bytes); 10862 stats->tx_bytes += BNXT_GET_RING_STATS64(sw, tx_bcast_bytes); 10863 10864 stats->rx_missed_errors += 10865 BNXT_GET_RING_STATS64(sw, rx_discard_pkts); 10866 10867 stats->multicast += BNXT_GET_RING_STATS64(sw, rx_mcast_pkts); 10868 10869 stats->tx_dropped += BNXT_GET_RING_STATS64(sw, tx_error_pkts); 10870 10871 stats->rx_dropped += 10872 cpr->sw_stats.rx.rx_netpoll_discards + 10873 cpr->sw_stats.rx.rx_oom_discards; 10874 } 10875 } 10876 10877 static void bnxt_add_prev_stats(struct bnxt *bp, 10878 struct rtnl_link_stats64 *stats) 10879 { 10880 struct rtnl_link_stats64 *prev_stats = &bp->net_stats_prev; 10881 10882 stats->rx_packets += prev_stats->rx_packets; 10883 stats->tx_packets += prev_stats->tx_packets; 10884 stats->rx_bytes += prev_stats->rx_bytes; 10885 stats->tx_bytes += prev_stats->tx_bytes; 10886 stats->rx_missed_errors += prev_stats->rx_missed_errors; 10887 stats->multicast += prev_stats->multicast; 10888 stats->rx_dropped += prev_stats->rx_dropped; 10889 stats->tx_dropped += prev_stats->tx_dropped; 10890 } 10891 10892 static void 10893 bnxt_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) 10894 { 10895 struct bnxt *bp = netdev_priv(dev); 10896 10897 set_bit(BNXT_STATE_READ_STATS, &bp->state); 10898 /* Make sure bnxt_close_nic() sees that we are reading stats before 10899 * we check the BNXT_STATE_OPEN flag. 10900 */ 10901 smp_mb__after_atomic(); 10902 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) { 10903 clear_bit(BNXT_STATE_READ_STATS, &bp->state); 10904 *stats = bp->net_stats_prev; 10905 return; 10906 } 10907 10908 bnxt_get_ring_stats(bp, stats); 10909 bnxt_add_prev_stats(bp, stats); 10910 10911 if (bp->flags & BNXT_FLAG_PORT_STATS) { 10912 u64 *rx = bp->port_stats.sw_stats; 10913 u64 *tx = bp->port_stats.sw_stats + 10914 BNXT_TX_PORT_STATS_BYTE_OFFSET / 8; 10915 10916 stats->rx_crc_errors = 10917 BNXT_GET_RX_PORT_STATS64(rx, rx_fcs_err_frames); 10918 stats->rx_frame_errors = 10919 BNXT_GET_RX_PORT_STATS64(rx, rx_align_err_frames); 10920 stats->rx_length_errors = 10921 BNXT_GET_RX_PORT_STATS64(rx, rx_undrsz_frames) + 10922 BNXT_GET_RX_PORT_STATS64(rx, rx_ovrsz_frames) + 10923 BNXT_GET_RX_PORT_STATS64(rx, rx_runt_frames); 10924 stats->rx_errors = 10925 BNXT_GET_RX_PORT_STATS64(rx, rx_false_carrier_frames) + 10926 BNXT_GET_RX_PORT_STATS64(rx, rx_jbr_frames); 10927 stats->collisions = 10928 BNXT_GET_TX_PORT_STATS64(tx, tx_total_collisions); 10929 stats->tx_fifo_errors = 10930 BNXT_GET_TX_PORT_STATS64(tx, tx_fifo_underruns); 10931 stats->tx_errors = BNXT_GET_TX_PORT_STATS64(tx, tx_err); 10932 } 10933 clear_bit(BNXT_STATE_READ_STATS, &bp->state); 10934 } 10935 10936 static bool bnxt_mc_list_updated(struct bnxt *bp, u32 *rx_mask) 10937 { 10938 struct net_device *dev = bp->dev; 10939 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 10940 struct netdev_hw_addr *ha; 10941 u8 *haddr; 10942 int mc_count = 0; 10943 bool update = false; 10944 int off = 0; 10945 10946 netdev_for_each_mc_addr(ha, dev) { 10947 if (mc_count >= BNXT_MAX_MC_ADDRS) { 10948 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST; 10949 vnic->mc_list_count = 0; 10950 return false; 10951 } 10952 haddr = ha->addr; 10953 if (!ether_addr_equal(haddr, vnic->mc_list + off)) { 10954 memcpy(vnic->mc_list + off, haddr, ETH_ALEN); 10955 update = true; 10956 } 10957 off += ETH_ALEN; 10958 mc_count++; 10959 } 10960 if (mc_count) 10961 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_MCAST; 10962 10963 if (mc_count != vnic->mc_list_count) { 10964 vnic->mc_list_count = mc_count; 10965 update = true; 10966 } 10967 return update; 10968 } 10969 10970 static bool bnxt_uc_list_updated(struct bnxt *bp) 10971 { 10972 struct net_device *dev = bp->dev; 10973 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 10974 struct netdev_hw_addr *ha; 10975 int off = 0; 10976 10977 if (netdev_uc_count(dev) != (vnic->uc_filter_count - 1)) 10978 return true; 10979 10980 netdev_for_each_uc_addr(ha, dev) { 10981 if (!ether_addr_equal(ha->addr, vnic->uc_list + off)) 10982 return true; 10983 10984 off += ETH_ALEN; 10985 } 10986 return false; 10987 } 10988 10989 static void bnxt_set_rx_mode(struct net_device *dev) 10990 { 10991 struct bnxt *bp = netdev_priv(dev); 10992 struct bnxt_vnic_info *vnic; 10993 bool mc_update = false; 10994 bool uc_update; 10995 u32 mask; 10996 10997 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) 10998 return; 10999 11000 vnic = &bp->vnic_info[0]; 11001 mask = vnic->rx_mask; 11002 mask &= ~(CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS | 11003 CFA_L2_SET_RX_MASK_REQ_MASK_MCAST | 11004 CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST | 11005 CFA_L2_SET_RX_MASK_REQ_MASK_BCAST); 11006 11007 if (dev->flags & IFF_PROMISC) 11008 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS; 11009 11010 uc_update = bnxt_uc_list_updated(bp); 11011 11012 if (dev->flags & IFF_BROADCAST) 11013 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_BCAST; 11014 if (dev->flags & IFF_ALLMULTI) { 11015 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST; 11016 vnic->mc_list_count = 0; 11017 } else if (dev->flags & IFF_MULTICAST) { 11018 mc_update = bnxt_mc_list_updated(bp, &mask); 11019 } 11020 11021 if (mask != vnic->rx_mask || uc_update || mc_update) { 11022 vnic->rx_mask = mask; 11023 11024 set_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event); 11025 bnxt_queue_sp_work(bp); 11026 } 11027 } 11028 11029 static int bnxt_cfg_rx_mode(struct bnxt *bp) 11030 { 11031 struct net_device *dev = bp->dev; 11032 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 11033 struct hwrm_cfa_l2_filter_free_input *req; 11034 struct netdev_hw_addr *ha; 11035 int i, off = 0, rc; 11036 bool uc_update; 11037 11038 netif_addr_lock_bh(dev); 11039 uc_update = bnxt_uc_list_updated(bp); 11040 netif_addr_unlock_bh(dev); 11041 11042 if (!uc_update) 11043 goto skip_uc; 11044 11045 rc = hwrm_req_init(bp, req, HWRM_CFA_L2_FILTER_FREE); 11046 if (rc) 11047 return rc; 11048 hwrm_req_hold(bp, req); 11049 for (i = 1; i < vnic->uc_filter_count; i++) { 11050 req->l2_filter_id = vnic->fw_l2_filter_id[i]; 11051 11052 rc = hwrm_req_send(bp, req); 11053 } 11054 hwrm_req_drop(bp, req); 11055 11056 vnic->uc_filter_count = 1; 11057 11058 netif_addr_lock_bh(dev); 11059 if (netdev_uc_count(dev) > (BNXT_MAX_UC_ADDRS - 1)) { 11060 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS; 11061 } else { 11062 netdev_for_each_uc_addr(ha, dev) { 11063 memcpy(vnic->uc_list + off, ha->addr, ETH_ALEN); 11064 off += ETH_ALEN; 11065 vnic->uc_filter_count++; 11066 } 11067 } 11068 netif_addr_unlock_bh(dev); 11069 11070 for (i = 1, off = 0; i < vnic->uc_filter_count; i++, off += ETH_ALEN) { 11071 rc = bnxt_hwrm_set_vnic_filter(bp, 0, i, vnic->uc_list + off); 11072 if (rc) { 11073 if (BNXT_VF(bp) && rc == -ENODEV) { 11074 if (!test_and_set_bit(BNXT_STATE_L2_FILTER_RETRY, &bp->state)) 11075 netdev_warn(bp->dev, "Cannot configure L2 filters while PF is unavailable, will retry\n"); 11076 else 11077 netdev_dbg(bp->dev, "PF still unavailable while configuring L2 filters.\n"); 11078 rc = 0; 11079 } else { 11080 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n", rc); 11081 } 11082 vnic->uc_filter_count = i; 11083 return rc; 11084 } 11085 } 11086 if (test_and_clear_bit(BNXT_STATE_L2_FILTER_RETRY, &bp->state)) 11087 netdev_notice(bp->dev, "Retry of L2 filter configuration successful.\n"); 11088 11089 skip_uc: 11090 if ((vnic->rx_mask & CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS) && 11091 !bnxt_promisc_ok(bp)) 11092 vnic->rx_mask &= ~CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS; 11093 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0); 11094 if (rc && (vnic->rx_mask & CFA_L2_SET_RX_MASK_REQ_MASK_MCAST)) { 11095 netdev_info(bp->dev, "Failed setting MC filters rc: %d, turning on ALL_MCAST mode\n", 11096 rc); 11097 vnic->rx_mask &= ~CFA_L2_SET_RX_MASK_REQ_MASK_MCAST; 11098 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST; 11099 vnic->mc_list_count = 0; 11100 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0); 11101 } 11102 if (rc) 11103 netdev_err(bp->dev, "HWRM cfa l2 rx mask failure rc: %d\n", 11104 rc); 11105 11106 return rc; 11107 } 11108 11109 static bool bnxt_can_reserve_rings(struct bnxt *bp) 11110 { 11111 #ifdef CONFIG_BNXT_SRIOV 11112 if (BNXT_NEW_RM(bp) && BNXT_VF(bp)) { 11113 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 11114 11115 /* No minimum rings were provisioned by the PF. Don't 11116 * reserve rings by default when device is down. 11117 */ 11118 if (hw_resc->min_tx_rings || hw_resc->resv_tx_rings) 11119 return true; 11120 11121 if (!netif_running(bp->dev)) 11122 return false; 11123 } 11124 #endif 11125 return true; 11126 } 11127 11128 /* If the chip and firmware supports RFS */ 11129 static bool bnxt_rfs_supported(struct bnxt *bp) 11130 { 11131 if (bp->flags & BNXT_FLAG_CHIP_P5) { 11132 if (bp->fw_cap & BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V2) 11133 return true; 11134 return false; 11135 } 11136 /* 212 firmware is broken for aRFS */ 11137 if (BNXT_FW_MAJ(bp) == 212) 11138 return false; 11139 if (BNXT_PF(bp) && !BNXT_CHIP_TYPE_NITRO_A0(bp)) 11140 return true; 11141 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP) 11142 return true; 11143 return false; 11144 } 11145 11146 /* If runtime conditions support RFS */ 11147 static bool bnxt_rfs_capable(struct bnxt *bp) 11148 { 11149 #ifdef CONFIG_RFS_ACCEL 11150 int vnics, max_vnics, max_rss_ctxs; 11151 11152 if (bp->flags & BNXT_FLAG_CHIP_P5) 11153 return bnxt_rfs_supported(bp); 11154 if (!(bp->flags & BNXT_FLAG_MSIX_CAP) || !bnxt_can_reserve_rings(bp) || !bp->rx_nr_rings) 11155 return false; 11156 11157 vnics = 1 + bp->rx_nr_rings; 11158 max_vnics = bnxt_get_max_func_vnics(bp); 11159 max_rss_ctxs = bnxt_get_max_func_rss_ctxs(bp); 11160 11161 /* RSS contexts not a limiting factor */ 11162 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP) 11163 max_rss_ctxs = max_vnics; 11164 if (vnics > max_vnics || vnics > max_rss_ctxs) { 11165 if (bp->rx_nr_rings > 1) 11166 netdev_warn(bp->dev, 11167 "Not enough resources to support NTUPLE filters, enough resources for up to %d rx rings\n", 11168 min(max_rss_ctxs - 1, max_vnics - 1)); 11169 return false; 11170 } 11171 11172 if (!BNXT_NEW_RM(bp)) 11173 return true; 11174 11175 if (vnics == bp->hw_resc.resv_vnics) 11176 return true; 11177 11178 bnxt_hwrm_reserve_rings(bp, 0, 0, 0, 0, 0, vnics); 11179 if (vnics <= bp->hw_resc.resv_vnics) 11180 return true; 11181 11182 netdev_warn(bp->dev, "Unable to reserve resources to support NTUPLE filters.\n"); 11183 bnxt_hwrm_reserve_rings(bp, 0, 0, 0, 0, 0, 1); 11184 return false; 11185 #else 11186 return false; 11187 #endif 11188 } 11189 11190 static netdev_features_t bnxt_fix_features(struct net_device *dev, 11191 netdev_features_t features) 11192 { 11193 struct bnxt *bp = netdev_priv(dev); 11194 netdev_features_t vlan_features; 11195 11196 if ((features & NETIF_F_NTUPLE) && !bnxt_rfs_capable(bp)) 11197 features &= ~NETIF_F_NTUPLE; 11198 11199 if ((bp->flags & BNXT_FLAG_NO_AGG_RINGS) || bp->xdp_prog) 11200 features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW); 11201 11202 if (!(features & NETIF_F_GRO)) 11203 features &= ~NETIF_F_GRO_HW; 11204 11205 if (features & NETIF_F_GRO_HW) 11206 features &= ~NETIF_F_LRO; 11207 11208 /* Both CTAG and STAG VLAN accelaration on the RX side have to be 11209 * turned on or off together. 11210 */ 11211 vlan_features = features & BNXT_HW_FEATURE_VLAN_ALL_RX; 11212 if (vlan_features != BNXT_HW_FEATURE_VLAN_ALL_RX) { 11213 if (dev->features & BNXT_HW_FEATURE_VLAN_ALL_RX) 11214 features &= ~BNXT_HW_FEATURE_VLAN_ALL_RX; 11215 else if (vlan_features) 11216 features |= BNXT_HW_FEATURE_VLAN_ALL_RX; 11217 } 11218 #ifdef CONFIG_BNXT_SRIOV 11219 if (BNXT_VF(bp) && bp->vf.vlan) 11220 features &= ~BNXT_HW_FEATURE_VLAN_ALL_RX; 11221 #endif 11222 return features; 11223 } 11224 11225 static int bnxt_set_features(struct net_device *dev, netdev_features_t features) 11226 { 11227 struct bnxt *bp = netdev_priv(dev); 11228 u32 flags = bp->flags; 11229 u32 changes; 11230 int rc = 0; 11231 bool re_init = false; 11232 bool update_tpa = false; 11233 11234 flags &= ~BNXT_FLAG_ALL_CONFIG_FEATS; 11235 if (features & NETIF_F_GRO_HW) 11236 flags |= BNXT_FLAG_GRO; 11237 else if (features & NETIF_F_LRO) 11238 flags |= BNXT_FLAG_LRO; 11239 11240 if (bp->flags & BNXT_FLAG_NO_AGG_RINGS) 11241 flags &= ~BNXT_FLAG_TPA; 11242 11243 if (features & BNXT_HW_FEATURE_VLAN_ALL_RX) 11244 flags |= BNXT_FLAG_STRIP_VLAN; 11245 11246 if (features & NETIF_F_NTUPLE) 11247 flags |= BNXT_FLAG_RFS; 11248 11249 changes = flags ^ bp->flags; 11250 if (changes & BNXT_FLAG_TPA) { 11251 update_tpa = true; 11252 if ((bp->flags & BNXT_FLAG_TPA) == 0 || 11253 (flags & BNXT_FLAG_TPA) == 0 || 11254 (bp->flags & BNXT_FLAG_CHIP_P5)) 11255 re_init = true; 11256 } 11257 11258 if (changes & ~BNXT_FLAG_TPA) 11259 re_init = true; 11260 11261 if (flags != bp->flags) { 11262 u32 old_flags = bp->flags; 11263 11264 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) { 11265 bp->flags = flags; 11266 if (update_tpa) 11267 bnxt_set_ring_params(bp); 11268 return rc; 11269 } 11270 11271 if (re_init) { 11272 bnxt_close_nic(bp, false, false); 11273 bp->flags = flags; 11274 if (update_tpa) 11275 bnxt_set_ring_params(bp); 11276 11277 return bnxt_open_nic(bp, false, false); 11278 } 11279 if (update_tpa) { 11280 bp->flags = flags; 11281 rc = bnxt_set_tpa(bp, 11282 (flags & BNXT_FLAG_TPA) ? 11283 true : false); 11284 if (rc) 11285 bp->flags = old_flags; 11286 } 11287 } 11288 return rc; 11289 } 11290 11291 static bool bnxt_exthdr_check(struct bnxt *bp, struct sk_buff *skb, int nw_off, 11292 u8 **nextp) 11293 { 11294 struct ipv6hdr *ip6h = (struct ipv6hdr *)(skb->data + nw_off); 11295 struct hop_jumbo_hdr *jhdr; 11296 int hdr_count = 0; 11297 u8 *nexthdr; 11298 int start; 11299 11300 /* Check that there are at most 2 IPv6 extension headers, no 11301 * fragment header, and each is <= 64 bytes. 11302 */ 11303 start = nw_off + sizeof(*ip6h); 11304 nexthdr = &ip6h->nexthdr; 11305 while (ipv6_ext_hdr(*nexthdr)) { 11306 struct ipv6_opt_hdr *hp; 11307 int hdrlen; 11308 11309 if (hdr_count >= 3 || *nexthdr == NEXTHDR_NONE || 11310 *nexthdr == NEXTHDR_FRAGMENT) 11311 return false; 11312 hp = __skb_header_pointer(NULL, start, sizeof(*hp), skb->data, 11313 skb_headlen(skb), NULL); 11314 if (!hp) 11315 return false; 11316 if (*nexthdr == NEXTHDR_AUTH) 11317 hdrlen = ipv6_authlen(hp); 11318 else 11319 hdrlen = ipv6_optlen(hp); 11320 11321 if (hdrlen > 64) 11322 return false; 11323 11324 /* The ext header may be a hop-by-hop header inserted for 11325 * big TCP purposes. This will be removed before sending 11326 * from NIC, so do not count it. 11327 */ 11328 if (*nexthdr == NEXTHDR_HOP) { 11329 if (likely(skb->len <= GRO_LEGACY_MAX_SIZE)) 11330 goto increment_hdr; 11331 11332 jhdr = (struct hop_jumbo_hdr *)hp; 11333 if (jhdr->tlv_type != IPV6_TLV_JUMBO || jhdr->hdrlen != 0 || 11334 jhdr->nexthdr != IPPROTO_TCP) 11335 goto increment_hdr; 11336 11337 goto next_hdr; 11338 } 11339 increment_hdr: 11340 hdr_count++; 11341 next_hdr: 11342 nexthdr = &hp->nexthdr; 11343 start += hdrlen; 11344 } 11345 if (nextp) { 11346 /* Caller will check inner protocol */ 11347 if (skb->encapsulation) { 11348 *nextp = nexthdr; 11349 return true; 11350 } 11351 *nextp = NULL; 11352 } 11353 /* Only support TCP/UDP for non-tunneled ipv6 and inner ipv6 */ 11354 return *nexthdr == IPPROTO_TCP || *nexthdr == IPPROTO_UDP; 11355 } 11356 11357 /* For UDP, we can only handle 1 Vxlan port and 1 Geneve port. */ 11358 static bool bnxt_udp_tunl_check(struct bnxt *bp, struct sk_buff *skb) 11359 { 11360 struct udphdr *uh = udp_hdr(skb); 11361 __be16 udp_port = uh->dest; 11362 11363 if (udp_port != bp->vxlan_port && udp_port != bp->nge_port) 11364 return false; 11365 if (skb->inner_protocol_type == ENCAP_TYPE_ETHER) { 11366 struct ethhdr *eh = inner_eth_hdr(skb); 11367 11368 switch (eh->h_proto) { 11369 case htons(ETH_P_IP): 11370 return true; 11371 case htons(ETH_P_IPV6): 11372 return bnxt_exthdr_check(bp, skb, 11373 skb_inner_network_offset(skb), 11374 NULL); 11375 } 11376 } 11377 return false; 11378 } 11379 11380 static bool bnxt_tunl_check(struct bnxt *bp, struct sk_buff *skb, u8 l4_proto) 11381 { 11382 switch (l4_proto) { 11383 case IPPROTO_UDP: 11384 return bnxt_udp_tunl_check(bp, skb); 11385 case IPPROTO_IPIP: 11386 return true; 11387 case IPPROTO_GRE: { 11388 switch (skb->inner_protocol) { 11389 default: 11390 return false; 11391 case htons(ETH_P_IP): 11392 return true; 11393 case htons(ETH_P_IPV6): 11394 fallthrough; 11395 } 11396 } 11397 case IPPROTO_IPV6: 11398 /* Check ext headers of inner ipv6 */ 11399 return bnxt_exthdr_check(bp, skb, skb_inner_network_offset(skb), 11400 NULL); 11401 } 11402 return false; 11403 } 11404 11405 static netdev_features_t bnxt_features_check(struct sk_buff *skb, 11406 struct net_device *dev, 11407 netdev_features_t features) 11408 { 11409 struct bnxt *bp = netdev_priv(dev); 11410 u8 *l4_proto; 11411 11412 features = vlan_features_check(skb, features); 11413 switch (vlan_get_protocol(skb)) { 11414 case htons(ETH_P_IP): 11415 if (!skb->encapsulation) 11416 return features; 11417 l4_proto = &ip_hdr(skb)->protocol; 11418 if (bnxt_tunl_check(bp, skb, *l4_proto)) 11419 return features; 11420 break; 11421 case htons(ETH_P_IPV6): 11422 if (!bnxt_exthdr_check(bp, skb, skb_network_offset(skb), 11423 &l4_proto)) 11424 break; 11425 if (!l4_proto || bnxt_tunl_check(bp, skb, *l4_proto)) 11426 return features; 11427 break; 11428 } 11429 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK); 11430 } 11431 11432 int bnxt_dbg_hwrm_rd_reg(struct bnxt *bp, u32 reg_off, u16 num_words, 11433 u32 *reg_buf) 11434 { 11435 struct hwrm_dbg_read_direct_output *resp; 11436 struct hwrm_dbg_read_direct_input *req; 11437 __le32 *dbg_reg_buf; 11438 dma_addr_t mapping; 11439 int rc, i; 11440 11441 rc = hwrm_req_init(bp, req, HWRM_DBG_READ_DIRECT); 11442 if (rc) 11443 return rc; 11444 11445 dbg_reg_buf = hwrm_req_dma_slice(bp, req, num_words * 4, 11446 &mapping); 11447 if (!dbg_reg_buf) { 11448 rc = -ENOMEM; 11449 goto dbg_rd_reg_exit; 11450 } 11451 11452 req->host_dest_addr = cpu_to_le64(mapping); 11453 11454 resp = hwrm_req_hold(bp, req); 11455 req->read_addr = cpu_to_le32(reg_off + CHIMP_REG_VIEW_ADDR); 11456 req->read_len32 = cpu_to_le32(num_words); 11457 11458 rc = hwrm_req_send(bp, req); 11459 if (rc || resp->error_code) { 11460 rc = -EIO; 11461 goto dbg_rd_reg_exit; 11462 } 11463 for (i = 0; i < num_words; i++) 11464 reg_buf[i] = le32_to_cpu(dbg_reg_buf[i]); 11465 11466 dbg_rd_reg_exit: 11467 hwrm_req_drop(bp, req); 11468 return rc; 11469 } 11470 11471 static int bnxt_dbg_hwrm_ring_info_get(struct bnxt *bp, u8 ring_type, 11472 u32 ring_id, u32 *prod, u32 *cons) 11473 { 11474 struct hwrm_dbg_ring_info_get_output *resp; 11475 struct hwrm_dbg_ring_info_get_input *req; 11476 int rc; 11477 11478 rc = hwrm_req_init(bp, req, HWRM_DBG_RING_INFO_GET); 11479 if (rc) 11480 return rc; 11481 11482 req->ring_type = ring_type; 11483 req->fw_ring_id = cpu_to_le32(ring_id); 11484 resp = hwrm_req_hold(bp, req); 11485 rc = hwrm_req_send(bp, req); 11486 if (!rc) { 11487 *prod = le32_to_cpu(resp->producer_index); 11488 *cons = le32_to_cpu(resp->consumer_index); 11489 } 11490 hwrm_req_drop(bp, req); 11491 return rc; 11492 } 11493 11494 static void bnxt_dump_tx_sw_state(struct bnxt_napi *bnapi) 11495 { 11496 struct bnxt_tx_ring_info *txr = bnapi->tx_ring; 11497 int i = bnapi->index; 11498 11499 if (!txr) 11500 return; 11501 11502 netdev_info(bnapi->bp->dev, "[%d]: tx{fw_ring: %d prod: %x cons: %x}\n", 11503 i, txr->tx_ring_struct.fw_ring_id, txr->tx_prod, 11504 txr->tx_cons); 11505 } 11506 11507 static void bnxt_dump_rx_sw_state(struct bnxt_napi *bnapi) 11508 { 11509 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 11510 int i = bnapi->index; 11511 11512 if (!rxr) 11513 return; 11514 11515 netdev_info(bnapi->bp->dev, "[%d]: rx{fw_ring: %d prod: %x} rx_agg{fw_ring: %d agg_prod: %x sw_agg_prod: %x}\n", 11516 i, rxr->rx_ring_struct.fw_ring_id, rxr->rx_prod, 11517 rxr->rx_agg_ring_struct.fw_ring_id, rxr->rx_agg_prod, 11518 rxr->rx_sw_agg_prod); 11519 } 11520 11521 static void bnxt_dump_cp_sw_state(struct bnxt_napi *bnapi) 11522 { 11523 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 11524 int i = bnapi->index; 11525 11526 netdev_info(bnapi->bp->dev, "[%d]: cp{fw_ring: %d raw_cons: %x}\n", 11527 i, cpr->cp_ring_struct.fw_ring_id, cpr->cp_raw_cons); 11528 } 11529 11530 static void bnxt_dbg_dump_states(struct bnxt *bp) 11531 { 11532 int i; 11533 struct bnxt_napi *bnapi; 11534 11535 for (i = 0; i < bp->cp_nr_rings; i++) { 11536 bnapi = bp->bnapi[i]; 11537 if (netif_msg_drv(bp)) { 11538 bnxt_dump_tx_sw_state(bnapi); 11539 bnxt_dump_rx_sw_state(bnapi); 11540 bnxt_dump_cp_sw_state(bnapi); 11541 } 11542 } 11543 } 11544 11545 static int bnxt_hwrm_rx_ring_reset(struct bnxt *bp, int ring_nr) 11546 { 11547 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[ring_nr]; 11548 struct hwrm_ring_reset_input *req; 11549 struct bnxt_napi *bnapi = rxr->bnapi; 11550 struct bnxt_cp_ring_info *cpr; 11551 u16 cp_ring_id; 11552 int rc; 11553 11554 rc = hwrm_req_init(bp, req, HWRM_RING_RESET); 11555 if (rc) 11556 return rc; 11557 11558 cpr = &bnapi->cp_ring; 11559 cp_ring_id = cpr->cp_ring_struct.fw_ring_id; 11560 req->cmpl_ring = cpu_to_le16(cp_ring_id); 11561 req->ring_type = RING_RESET_REQ_RING_TYPE_RX_RING_GRP; 11562 req->ring_id = cpu_to_le16(bp->grp_info[bnapi->index].fw_grp_id); 11563 return hwrm_req_send_silent(bp, req); 11564 } 11565 11566 static void bnxt_reset_task(struct bnxt *bp, bool silent) 11567 { 11568 if (!silent) 11569 bnxt_dbg_dump_states(bp); 11570 if (netif_running(bp->dev)) { 11571 int rc; 11572 11573 if (silent) { 11574 bnxt_close_nic(bp, false, false); 11575 bnxt_open_nic(bp, false, false); 11576 } else { 11577 bnxt_ulp_stop(bp); 11578 bnxt_close_nic(bp, true, false); 11579 rc = bnxt_open_nic(bp, true, false); 11580 bnxt_ulp_start(bp, rc); 11581 } 11582 } 11583 } 11584 11585 static void bnxt_tx_timeout(struct net_device *dev, unsigned int txqueue) 11586 { 11587 struct bnxt *bp = netdev_priv(dev); 11588 11589 netdev_err(bp->dev, "TX timeout detected, starting reset task!\n"); 11590 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event); 11591 bnxt_queue_sp_work(bp); 11592 } 11593 11594 static void bnxt_fw_health_check(struct bnxt *bp) 11595 { 11596 struct bnxt_fw_health *fw_health = bp->fw_health; 11597 u32 val; 11598 11599 if (!fw_health->enabled || test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) 11600 return; 11601 11602 /* Make sure it is enabled before checking the tmr_counter. */ 11603 smp_rmb(); 11604 if (fw_health->tmr_counter) { 11605 fw_health->tmr_counter--; 11606 return; 11607 } 11608 11609 val = bnxt_fw_health_readl(bp, BNXT_FW_HEARTBEAT_REG); 11610 if (val == fw_health->last_fw_heartbeat) { 11611 fw_health->arrests++; 11612 goto fw_reset; 11613 } 11614 11615 fw_health->last_fw_heartbeat = val; 11616 11617 val = bnxt_fw_health_readl(bp, BNXT_FW_RESET_CNT_REG); 11618 if (val != fw_health->last_fw_reset_cnt) { 11619 fw_health->discoveries++; 11620 goto fw_reset; 11621 } 11622 11623 fw_health->tmr_counter = fw_health->tmr_multiplier; 11624 return; 11625 11626 fw_reset: 11627 set_bit(BNXT_FW_EXCEPTION_SP_EVENT, &bp->sp_event); 11628 bnxt_queue_sp_work(bp); 11629 } 11630 11631 static void bnxt_timer(struct timer_list *t) 11632 { 11633 struct bnxt *bp = from_timer(bp, t, timer); 11634 struct net_device *dev = bp->dev; 11635 11636 if (!netif_running(dev) || !test_bit(BNXT_STATE_OPEN, &bp->state)) 11637 return; 11638 11639 if (atomic_read(&bp->intr_sem) != 0) 11640 goto bnxt_restart_timer; 11641 11642 if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY) 11643 bnxt_fw_health_check(bp); 11644 11645 if (BNXT_LINK_IS_UP(bp) && bp->stats_coal_ticks) { 11646 set_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event); 11647 bnxt_queue_sp_work(bp); 11648 } 11649 11650 if (bnxt_tc_flower_enabled(bp)) { 11651 set_bit(BNXT_FLOW_STATS_SP_EVENT, &bp->sp_event); 11652 bnxt_queue_sp_work(bp); 11653 } 11654 11655 #ifdef CONFIG_RFS_ACCEL 11656 if ((bp->flags & BNXT_FLAG_RFS) && bp->ntp_fltr_count) { 11657 set_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event); 11658 bnxt_queue_sp_work(bp); 11659 } 11660 #endif /*CONFIG_RFS_ACCEL*/ 11661 11662 if (bp->link_info.phy_retry) { 11663 if (time_after(jiffies, bp->link_info.phy_retry_expires)) { 11664 bp->link_info.phy_retry = false; 11665 netdev_warn(bp->dev, "failed to update phy settings after maximum retries.\n"); 11666 } else { 11667 set_bit(BNXT_UPDATE_PHY_SP_EVENT, &bp->sp_event); 11668 bnxt_queue_sp_work(bp); 11669 } 11670 } 11671 11672 if (test_bit(BNXT_STATE_L2_FILTER_RETRY, &bp->state)) { 11673 set_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event); 11674 bnxt_queue_sp_work(bp); 11675 } 11676 11677 if ((bp->flags & BNXT_FLAG_CHIP_P5) && !bp->chip_rev && 11678 netif_carrier_ok(dev)) { 11679 set_bit(BNXT_RING_COAL_NOW_SP_EVENT, &bp->sp_event); 11680 bnxt_queue_sp_work(bp); 11681 } 11682 bnxt_restart_timer: 11683 mod_timer(&bp->timer, jiffies + bp->current_interval); 11684 } 11685 11686 static void bnxt_rtnl_lock_sp(struct bnxt *bp) 11687 { 11688 /* We are called from bnxt_sp_task which has BNXT_STATE_IN_SP_TASK 11689 * set. If the device is being closed, bnxt_close() may be holding 11690 * rtnl() and waiting for BNXT_STATE_IN_SP_TASK to clear. So we 11691 * must clear BNXT_STATE_IN_SP_TASK before holding rtnl(). 11692 */ 11693 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state); 11694 rtnl_lock(); 11695 } 11696 11697 static void bnxt_rtnl_unlock_sp(struct bnxt *bp) 11698 { 11699 set_bit(BNXT_STATE_IN_SP_TASK, &bp->state); 11700 rtnl_unlock(); 11701 } 11702 11703 /* Only called from bnxt_sp_task() */ 11704 static void bnxt_reset(struct bnxt *bp, bool silent) 11705 { 11706 bnxt_rtnl_lock_sp(bp); 11707 if (test_bit(BNXT_STATE_OPEN, &bp->state)) 11708 bnxt_reset_task(bp, silent); 11709 bnxt_rtnl_unlock_sp(bp); 11710 } 11711 11712 /* Only called from bnxt_sp_task() */ 11713 static void bnxt_rx_ring_reset(struct bnxt *bp) 11714 { 11715 int i; 11716 11717 bnxt_rtnl_lock_sp(bp); 11718 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) { 11719 bnxt_rtnl_unlock_sp(bp); 11720 return; 11721 } 11722 /* Disable and flush TPA before resetting the RX ring */ 11723 if (bp->flags & BNXT_FLAG_TPA) 11724 bnxt_set_tpa(bp, false); 11725 for (i = 0; i < bp->rx_nr_rings; i++) { 11726 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 11727 struct bnxt_cp_ring_info *cpr; 11728 int rc; 11729 11730 if (!rxr->bnapi->in_reset) 11731 continue; 11732 11733 rc = bnxt_hwrm_rx_ring_reset(bp, i); 11734 if (rc) { 11735 if (rc == -EINVAL || rc == -EOPNOTSUPP) 11736 netdev_info_once(bp->dev, "RX ring reset not supported by firmware, falling back to global reset\n"); 11737 else 11738 netdev_warn(bp->dev, "RX ring reset failed, rc = %d, falling back to global reset\n", 11739 rc); 11740 bnxt_reset_task(bp, true); 11741 break; 11742 } 11743 bnxt_free_one_rx_ring_skbs(bp, i); 11744 rxr->rx_prod = 0; 11745 rxr->rx_agg_prod = 0; 11746 rxr->rx_sw_agg_prod = 0; 11747 rxr->rx_next_cons = 0; 11748 rxr->bnapi->in_reset = false; 11749 bnxt_alloc_one_rx_ring(bp, i); 11750 cpr = &rxr->bnapi->cp_ring; 11751 cpr->sw_stats.rx.rx_resets++; 11752 if (bp->flags & BNXT_FLAG_AGG_RINGS) 11753 bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod); 11754 bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod); 11755 } 11756 if (bp->flags & BNXT_FLAG_TPA) 11757 bnxt_set_tpa(bp, true); 11758 bnxt_rtnl_unlock_sp(bp); 11759 } 11760 11761 static void bnxt_fw_reset_close(struct bnxt *bp) 11762 { 11763 bnxt_ulp_stop(bp); 11764 /* When firmware is in fatal state, quiesce device and disable 11765 * bus master to prevent any potential bad DMAs before freeing 11766 * kernel memory. 11767 */ 11768 if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state)) { 11769 u16 val = 0; 11770 11771 pci_read_config_word(bp->pdev, PCI_SUBSYSTEM_ID, &val); 11772 if (val == 0xffff) 11773 bp->fw_reset_min_dsecs = 0; 11774 bnxt_tx_disable(bp); 11775 bnxt_disable_napi(bp); 11776 bnxt_disable_int_sync(bp); 11777 bnxt_free_irq(bp); 11778 bnxt_clear_int_mode(bp); 11779 pci_disable_device(bp->pdev); 11780 } 11781 __bnxt_close_nic(bp, true, false); 11782 bnxt_vf_reps_free(bp); 11783 bnxt_clear_int_mode(bp); 11784 bnxt_hwrm_func_drv_unrgtr(bp); 11785 if (pci_is_enabled(bp->pdev)) 11786 pci_disable_device(bp->pdev); 11787 bnxt_free_ctx_mem(bp); 11788 kfree(bp->ctx); 11789 bp->ctx = NULL; 11790 } 11791 11792 static bool is_bnxt_fw_ok(struct bnxt *bp) 11793 { 11794 struct bnxt_fw_health *fw_health = bp->fw_health; 11795 bool no_heartbeat = false, has_reset = false; 11796 u32 val; 11797 11798 val = bnxt_fw_health_readl(bp, BNXT_FW_HEARTBEAT_REG); 11799 if (val == fw_health->last_fw_heartbeat) 11800 no_heartbeat = true; 11801 11802 val = bnxt_fw_health_readl(bp, BNXT_FW_RESET_CNT_REG); 11803 if (val != fw_health->last_fw_reset_cnt) 11804 has_reset = true; 11805 11806 if (!no_heartbeat && has_reset) 11807 return true; 11808 11809 return false; 11810 } 11811 11812 /* rtnl_lock is acquired before calling this function */ 11813 static void bnxt_force_fw_reset(struct bnxt *bp) 11814 { 11815 struct bnxt_fw_health *fw_health = bp->fw_health; 11816 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 11817 u32 wait_dsecs; 11818 11819 if (!test_bit(BNXT_STATE_OPEN, &bp->state) || 11820 test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) 11821 return; 11822 11823 if (ptp) { 11824 spin_lock_bh(&ptp->ptp_lock); 11825 set_bit(BNXT_STATE_IN_FW_RESET, &bp->state); 11826 spin_unlock_bh(&ptp->ptp_lock); 11827 } else { 11828 set_bit(BNXT_STATE_IN_FW_RESET, &bp->state); 11829 } 11830 bnxt_fw_reset_close(bp); 11831 wait_dsecs = fw_health->master_func_wait_dsecs; 11832 if (fw_health->primary) { 11833 if (fw_health->flags & ERROR_RECOVERY_QCFG_RESP_FLAGS_CO_CPU) 11834 wait_dsecs = 0; 11835 bp->fw_reset_state = BNXT_FW_RESET_STATE_RESET_FW; 11836 } else { 11837 bp->fw_reset_timestamp = jiffies + wait_dsecs * HZ / 10; 11838 wait_dsecs = fw_health->normal_func_wait_dsecs; 11839 bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV; 11840 } 11841 11842 bp->fw_reset_min_dsecs = fw_health->post_reset_wait_dsecs; 11843 bp->fw_reset_max_dsecs = fw_health->post_reset_max_wait_dsecs; 11844 bnxt_queue_fw_reset_work(bp, wait_dsecs * HZ / 10); 11845 } 11846 11847 void bnxt_fw_exception(struct bnxt *bp) 11848 { 11849 netdev_warn(bp->dev, "Detected firmware fatal condition, initiating reset\n"); 11850 set_bit(BNXT_STATE_FW_FATAL_COND, &bp->state); 11851 bnxt_rtnl_lock_sp(bp); 11852 bnxt_force_fw_reset(bp); 11853 bnxt_rtnl_unlock_sp(bp); 11854 } 11855 11856 /* Returns the number of registered VFs, or 1 if VF configuration is pending, or 11857 * < 0 on error. 11858 */ 11859 static int bnxt_get_registered_vfs(struct bnxt *bp) 11860 { 11861 #ifdef CONFIG_BNXT_SRIOV 11862 int rc; 11863 11864 if (!BNXT_PF(bp)) 11865 return 0; 11866 11867 rc = bnxt_hwrm_func_qcfg(bp); 11868 if (rc) { 11869 netdev_err(bp->dev, "func_qcfg cmd failed, rc = %d\n", rc); 11870 return rc; 11871 } 11872 if (bp->pf.registered_vfs) 11873 return bp->pf.registered_vfs; 11874 if (bp->sriov_cfg) 11875 return 1; 11876 #endif 11877 return 0; 11878 } 11879 11880 void bnxt_fw_reset(struct bnxt *bp) 11881 { 11882 bnxt_rtnl_lock_sp(bp); 11883 if (test_bit(BNXT_STATE_OPEN, &bp->state) && 11884 !test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) { 11885 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 11886 int n = 0, tmo; 11887 11888 if (ptp) { 11889 spin_lock_bh(&ptp->ptp_lock); 11890 set_bit(BNXT_STATE_IN_FW_RESET, &bp->state); 11891 spin_unlock_bh(&ptp->ptp_lock); 11892 } else { 11893 set_bit(BNXT_STATE_IN_FW_RESET, &bp->state); 11894 } 11895 if (bp->pf.active_vfs && 11896 !test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state)) 11897 n = bnxt_get_registered_vfs(bp); 11898 if (n < 0) { 11899 netdev_err(bp->dev, "Firmware reset aborted, rc = %d\n", 11900 n); 11901 clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state); 11902 dev_close(bp->dev); 11903 goto fw_reset_exit; 11904 } else if (n > 0) { 11905 u16 vf_tmo_dsecs = n * 10; 11906 11907 if (bp->fw_reset_max_dsecs < vf_tmo_dsecs) 11908 bp->fw_reset_max_dsecs = vf_tmo_dsecs; 11909 bp->fw_reset_state = 11910 BNXT_FW_RESET_STATE_POLL_VF; 11911 bnxt_queue_fw_reset_work(bp, HZ / 10); 11912 goto fw_reset_exit; 11913 } 11914 bnxt_fw_reset_close(bp); 11915 if (bp->fw_cap & BNXT_FW_CAP_ERR_RECOVER_RELOAD) { 11916 bp->fw_reset_state = BNXT_FW_RESET_STATE_POLL_FW_DOWN; 11917 tmo = HZ / 10; 11918 } else { 11919 bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV; 11920 tmo = bp->fw_reset_min_dsecs * HZ / 10; 11921 } 11922 bnxt_queue_fw_reset_work(bp, tmo); 11923 } 11924 fw_reset_exit: 11925 bnxt_rtnl_unlock_sp(bp); 11926 } 11927 11928 static void bnxt_chk_missed_irq(struct bnxt *bp) 11929 { 11930 int i; 11931 11932 if (!(bp->flags & BNXT_FLAG_CHIP_P5)) 11933 return; 11934 11935 for (i = 0; i < bp->cp_nr_rings; i++) { 11936 struct bnxt_napi *bnapi = bp->bnapi[i]; 11937 struct bnxt_cp_ring_info *cpr; 11938 u32 fw_ring_id; 11939 int j; 11940 11941 if (!bnapi) 11942 continue; 11943 11944 cpr = &bnapi->cp_ring; 11945 for (j = 0; j < 2; j++) { 11946 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j]; 11947 u32 val[2]; 11948 11949 if (!cpr2 || cpr2->has_more_work || 11950 !bnxt_has_work(bp, cpr2)) 11951 continue; 11952 11953 if (cpr2->cp_raw_cons != cpr2->last_cp_raw_cons) { 11954 cpr2->last_cp_raw_cons = cpr2->cp_raw_cons; 11955 continue; 11956 } 11957 fw_ring_id = cpr2->cp_ring_struct.fw_ring_id; 11958 bnxt_dbg_hwrm_ring_info_get(bp, 11959 DBG_RING_INFO_GET_REQ_RING_TYPE_L2_CMPL, 11960 fw_ring_id, &val[0], &val[1]); 11961 cpr->sw_stats.cmn.missed_irqs++; 11962 } 11963 } 11964 } 11965 11966 static void bnxt_cfg_ntp_filters(struct bnxt *); 11967 11968 static void bnxt_init_ethtool_link_settings(struct bnxt *bp) 11969 { 11970 struct bnxt_link_info *link_info = &bp->link_info; 11971 11972 if (BNXT_AUTO_MODE(link_info->auto_mode)) { 11973 link_info->autoneg = BNXT_AUTONEG_SPEED; 11974 if (bp->hwrm_spec_code >= 0x10201) { 11975 if (link_info->auto_pause_setting & 11976 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE) 11977 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL; 11978 } else { 11979 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL; 11980 } 11981 link_info->advertising = link_info->auto_link_speeds; 11982 link_info->advertising_pam4 = link_info->auto_pam4_link_speeds; 11983 } else { 11984 link_info->req_link_speed = link_info->force_link_speed; 11985 link_info->req_signal_mode = BNXT_SIG_MODE_NRZ; 11986 if (link_info->force_pam4_link_speed) { 11987 link_info->req_link_speed = 11988 link_info->force_pam4_link_speed; 11989 link_info->req_signal_mode = BNXT_SIG_MODE_PAM4; 11990 } 11991 link_info->req_duplex = link_info->duplex_setting; 11992 } 11993 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) 11994 link_info->req_flow_ctrl = 11995 link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH; 11996 else 11997 link_info->req_flow_ctrl = link_info->force_pause_setting; 11998 } 11999 12000 static void bnxt_fw_echo_reply(struct bnxt *bp) 12001 { 12002 struct bnxt_fw_health *fw_health = bp->fw_health; 12003 struct hwrm_func_echo_response_input *req; 12004 int rc; 12005 12006 rc = hwrm_req_init(bp, req, HWRM_FUNC_ECHO_RESPONSE); 12007 if (rc) 12008 return; 12009 req->event_data1 = cpu_to_le32(fw_health->echo_req_data1); 12010 req->event_data2 = cpu_to_le32(fw_health->echo_req_data2); 12011 hwrm_req_send(bp, req); 12012 } 12013 12014 static void bnxt_sp_task(struct work_struct *work) 12015 { 12016 struct bnxt *bp = container_of(work, struct bnxt, sp_task); 12017 12018 set_bit(BNXT_STATE_IN_SP_TASK, &bp->state); 12019 smp_mb__after_atomic(); 12020 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) { 12021 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state); 12022 return; 12023 } 12024 12025 if (test_and_clear_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event)) 12026 bnxt_cfg_rx_mode(bp); 12027 12028 if (test_and_clear_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event)) 12029 bnxt_cfg_ntp_filters(bp); 12030 if (test_and_clear_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event)) 12031 bnxt_hwrm_exec_fwd_req(bp); 12032 if (test_and_clear_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event)) { 12033 bnxt_hwrm_port_qstats(bp, 0); 12034 bnxt_hwrm_port_qstats_ext(bp, 0); 12035 bnxt_accumulate_all_stats(bp); 12036 } 12037 12038 if (test_and_clear_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event)) { 12039 int rc; 12040 12041 mutex_lock(&bp->link_lock); 12042 if (test_and_clear_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT, 12043 &bp->sp_event)) 12044 bnxt_hwrm_phy_qcaps(bp); 12045 12046 rc = bnxt_update_link(bp, true); 12047 if (rc) 12048 netdev_err(bp->dev, "SP task can't update link (rc: %x)\n", 12049 rc); 12050 12051 if (test_and_clear_bit(BNXT_LINK_CFG_CHANGE_SP_EVENT, 12052 &bp->sp_event)) 12053 bnxt_init_ethtool_link_settings(bp); 12054 mutex_unlock(&bp->link_lock); 12055 } 12056 if (test_and_clear_bit(BNXT_UPDATE_PHY_SP_EVENT, &bp->sp_event)) { 12057 int rc; 12058 12059 mutex_lock(&bp->link_lock); 12060 rc = bnxt_update_phy_setting(bp); 12061 mutex_unlock(&bp->link_lock); 12062 if (rc) { 12063 netdev_warn(bp->dev, "update phy settings retry failed\n"); 12064 } else { 12065 bp->link_info.phy_retry = false; 12066 netdev_info(bp->dev, "update phy settings retry succeeded\n"); 12067 } 12068 } 12069 if (test_and_clear_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event)) { 12070 mutex_lock(&bp->link_lock); 12071 bnxt_get_port_module_status(bp); 12072 mutex_unlock(&bp->link_lock); 12073 } 12074 12075 if (test_and_clear_bit(BNXT_FLOW_STATS_SP_EVENT, &bp->sp_event)) 12076 bnxt_tc_flow_stats_work(bp); 12077 12078 if (test_and_clear_bit(BNXT_RING_COAL_NOW_SP_EVENT, &bp->sp_event)) 12079 bnxt_chk_missed_irq(bp); 12080 12081 if (test_and_clear_bit(BNXT_FW_ECHO_REQUEST_SP_EVENT, &bp->sp_event)) 12082 bnxt_fw_echo_reply(bp); 12083 12084 /* These functions below will clear BNXT_STATE_IN_SP_TASK. They 12085 * must be the last functions to be called before exiting. 12086 */ 12087 if (test_and_clear_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event)) 12088 bnxt_reset(bp, false); 12089 12090 if (test_and_clear_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event)) 12091 bnxt_reset(bp, true); 12092 12093 if (test_and_clear_bit(BNXT_RST_RING_SP_EVENT, &bp->sp_event)) 12094 bnxt_rx_ring_reset(bp); 12095 12096 if (test_and_clear_bit(BNXT_FW_RESET_NOTIFY_SP_EVENT, &bp->sp_event)) { 12097 if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state) || 12098 test_bit(BNXT_STATE_FW_NON_FATAL_COND, &bp->state)) 12099 bnxt_devlink_health_fw_report(bp); 12100 else 12101 bnxt_fw_reset(bp); 12102 } 12103 12104 if (test_and_clear_bit(BNXT_FW_EXCEPTION_SP_EVENT, &bp->sp_event)) { 12105 if (!is_bnxt_fw_ok(bp)) 12106 bnxt_devlink_health_fw_report(bp); 12107 } 12108 12109 smp_mb__before_atomic(); 12110 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state); 12111 } 12112 12113 /* Under rtnl_lock */ 12114 int bnxt_check_rings(struct bnxt *bp, int tx, int rx, bool sh, int tcs, 12115 int tx_xdp) 12116 { 12117 int max_rx, max_tx, tx_sets = 1; 12118 int tx_rings_needed, stats; 12119 int rx_rings = rx; 12120 int cp, vnics, rc; 12121 12122 if (tcs) 12123 tx_sets = tcs; 12124 12125 rc = bnxt_get_max_rings(bp, &max_rx, &max_tx, sh); 12126 if (rc) 12127 return rc; 12128 12129 if (max_rx < rx) 12130 return -ENOMEM; 12131 12132 tx_rings_needed = tx * tx_sets + tx_xdp; 12133 if (max_tx < tx_rings_needed) 12134 return -ENOMEM; 12135 12136 vnics = 1; 12137 if ((bp->flags & (BNXT_FLAG_RFS | BNXT_FLAG_CHIP_P5)) == BNXT_FLAG_RFS) 12138 vnics += rx_rings; 12139 12140 if (bp->flags & BNXT_FLAG_AGG_RINGS) 12141 rx_rings <<= 1; 12142 cp = sh ? max_t(int, tx_rings_needed, rx) : tx_rings_needed + rx; 12143 stats = cp; 12144 if (BNXT_NEW_RM(bp)) { 12145 cp += bnxt_get_ulp_msix_num(bp); 12146 stats += bnxt_get_ulp_stat_ctxs(bp); 12147 } 12148 return bnxt_hwrm_check_rings(bp, tx_rings_needed, rx_rings, rx, cp, 12149 stats, vnics); 12150 } 12151 12152 static void bnxt_unmap_bars(struct bnxt *bp, struct pci_dev *pdev) 12153 { 12154 if (bp->bar2) { 12155 pci_iounmap(pdev, bp->bar2); 12156 bp->bar2 = NULL; 12157 } 12158 12159 if (bp->bar1) { 12160 pci_iounmap(pdev, bp->bar1); 12161 bp->bar1 = NULL; 12162 } 12163 12164 if (bp->bar0) { 12165 pci_iounmap(pdev, bp->bar0); 12166 bp->bar0 = NULL; 12167 } 12168 } 12169 12170 static void bnxt_cleanup_pci(struct bnxt *bp) 12171 { 12172 bnxt_unmap_bars(bp, bp->pdev); 12173 pci_release_regions(bp->pdev); 12174 if (pci_is_enabled(bp->pdev)) 12175 pci_disable_device(bp->pdev); 12176 } 12177 12178 static void bnxt_init_dflt_coal(struct bnxt *bp) 12179 { 12180 struct bnxt_coal_cap *coal_cap = &bp->coal_cap; 12181 struct bnxt_coal *coal; 12182 u16 flags = 0; 12183 12184 if (coal_cap->cmpl_params & 12185 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET) 12186 flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET; 12187 12188 /* Tick values in micro seconds. 12189 * 1 coal_buf x bufs_per_record = 1 completion record. 12190 */ 12191 coal = &bp->rx_coal; 12192 coal->coal_ticks = 10; 12193 coal->coal_bufs = 30; 12194 coal->coal_ticks_irq = 1; 12195 coal->coal_bufs_irq = 2; 12196 coal->idle_thresh = 50; 12197 coal->bufs_per_record = 2; 12198 coal->budget = 64; /* NAPI budget */ 12199 coal->flags = flags; 12200 12201 coal = &bp->tx_coal; 12202 coal->coal_ticks = 28; 12203 coal->coal_bufs = 30; 12204 coal->coal_ticks_irq = 2; 12205 coal->coal_bufs_irq = 2; 12206 coal->bufs_per_record = 1; 12207 coal->flags = flags; 12208 12209 bp->stats_coal_ticks = BNXT_DEF_STATS_COAL_TICKS; 12210 } 12211 12212 static int bnxt_fw_init_one_p1(struct bnxt *bp) 12213 { 12214 int rc; 12215 12216 bp->fw_cap = 0; 12217 rc = bnxt_hwrm_ver_get(bp); 12218 bnxt_try_map_fw_health_reg(bp); 12219 if (rc) { 12220 rc = bnxt_try_recover_fw(bp); 12221 if (rc) 12222 return rc; 12223 rc = bnxt_hwrm_ver_get(bp); 12224 if (rc) 12225 return rc; 12226 } 12227 12228 bnxt_nvm_cfg_ver_get(bp); 12229 12230 rc = bnxt_hwrm_func_reset(bp); 12231 if (rc) 12232 return -ENODEV; 12233 12234 bnxt_hwrm_fw_set_time(bp); 12235 return 0; 12236 } 12237 12238 static int bnxt_fw_init_one_p2(struct bnxt *bp) 12239 { 12240 int rc; 12241 12242 /* Get the MAX capabilities for this function */ 12243 rc = bnxt_hwrm_func_qcaps(bp); 12244 if (rc) { 12245 netdev_err(bp->dev, "hwrm query capability failure rc: %x\n", 12246 rc); 12247 return -ENODEV; 12248 } 12249 12250 rc = bnxt_hwrm_cfa_adv_flow_mgnt_qcaps(bp); 12251 if (rc) 12252 netdev_warn(bp->dev, "hwrm query adv flow mgnt failure rc: %d\n", 12253 rc); 12254 12255 if (bnxt_alloc_fw_health(bp)) { 12256 netdev_warn(bp->dev, "no memory for firmware error recovery\n"); 12257 } else { 12258 rc = bnxt_hwrm_error_recovery_qcfg(bp); 12259 if (rc) 12260 netdev_warn(bp->dev, "hwrm query error recovery failure rc: %d\n", 12261 rc); 12262 } 12263 12264 rc = bnxt_hwrm_func_drv_rgtr(bp, NULL, 0, false); 12265 if (rc) 12266 return -ENODEV; 12267 12268 bnxt_hwrm_func_qcfg(bp); 12269 bnxt_hwrm_vnic_qcaps(bp); 12270 bnxt_hwrm_port_led_qcaps(bp); 12271 bnxt_ethtool_init(bp); 12272 if (bp->fw_cap & BNXT_FW_CAP_PTP) 12273 __bnxt_hwrm_ptp_qcfg(bp); 12274 bnxt_dcb_init(bp); 12275 return 0; 12276 } 12277 12278 static void bnxt_set_dflt_rss_hash_type(struct bnxt *bp) 12279 { 12280 bp->flags &= ~BNXT_FLAG_UDP_RSS_CAP; 12281 bp->rss_hash_cfg = VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 | 12282 VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 | 12283 VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 | 12284 VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6; 12285 if (bp->fw_cap & BNXT_FW_CAP_RSS_HASH_TYPE_DELTA) 12286 bp->rss_hash_delta = bp->rss_hash_cfg; 12287 if (BNXT_CHIP_P4_PLUS(bp) && bp->hwrm_spec_code >= 0x10501) { 12288 bp->flags |= BNXT_FLAG_UDP_RSS_CAP; 12289 bp->rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 | 12290 VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6; 12291 } 12292 } 12293 12294 static void bnxt_set_dflt_rfs(struct bnxt *bp) 12295 { 12296 struct net_device *dev = bp->dev; 12297 12298 dev->hw_features &= ~NETIF_F_NTUPLE; 12299 dev->features &= ~NETIF_F_NTUPLE; 12300 bp->flags &= ~BNXT_FLAG_RFS; 12301 if (bnxt_rfs_supported(bp)) { 12302 dev->hw_features |= NETIF_F_NTUPLE; 12303 if (bnxt_rfs_capable(bp)) { 12304 bp->flags |= BNXT_FLAG_RFS; 12305 dev->features |= NETIF_F_NTUPLE; 12306 } 12307 } 12308 } 12309 12310 static void bnxt_fw_init_one_p3(struct bnxt *bp) 12311 { 12312 struct pci_dev *pdev = bp->pdev; 12313 12314 bnxt_set_dflt_rss_hash_type(bp); 12315 bnxt_set_dflt_rfs(bp); 12316 12317 bnxt_get_wol_settings(bp); 12318 if (bp->flags & BNXT_FLAG_WOL_CAP) 12319 device_set_wakeup_enable(&pdev->dev, bp->wol); 12320 else 12321 device_set_wakeup_capable(&pdev->dev, false); 12322 12323 bnxt_hwrm_set_cache_line_size(bp, cache_line_size()); 12324 bnxt_hwrm_coal_params_qcaps(bp); 12325 } 12326 12327 static int bnxt_probe_phy(struct bnxt *bp, bool fw_dflt); 12328 12329 int bnxt_fw_init_one(struct bnxt *bp) 12330 { 12331 int rc; 12332 12333 rc = bnxt_fw_init_one_p1(bp); 12334 if (rc) { 12335 netdev_err(bp->dev, "Firmware init phase 1 failed\n"); 12336 return rc; 12337 } 12338 rc = bnxt_fw_init_one_p2(bp); 12339 if (rc) { 12340 netdev_err(bp->dev, "Firmware init phase 2 failed\n"); 12341 return rc; 12342 } 12343 rc = bnxt_probe_phy(bp, false); 12344 if (rc) 12345 return rc; 12346 rc = bnxt_approve_mac(bp, bp->dev->dev_addr, false); 12347 if (rc) 12348 return rc; 12349 12350 bnxt_fw_init_one_p3(bp); 12351 return 0; 12352 } 12353 12354 static void bnxt_fw_reset_writel(struct bnxt *bp, int reg_idx) 12355 { 12356 struct bnxt_fw_health *fw_health = bp->fw_health; 12357 u32 reg = fw_health->fw_reset_seq_regs[reg_idx]; 12358 u32 val = fw_health->fw_reset_seq_vals[reg_idx]; 12359 u32 reg_type, reg_off, delay_msecs; 12360 12361 delay_msecs = fw_health->fw_reset_seq_delay_msec[reg_idx]; 12362 reg_type = BNXT_FW_HEALTH_REG_TYPE(reg); 12363 reg_off = BNXT_FW_HEALTH_REG_OFF(reg); 12364 switch (reg_type) { 12365 case BNXT_FW_HEALTH_REG_TYPE_CFG: 12366 pci_write_config_dword(bp->pdev, reg_off, val); 12367 break; 12368 case BNXT_FW_HEALTH_REG_TYPE_GRC: 12369 writel(reg_off & BNXT_GRC_BASE_MASK, 12370 bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4); 12371 reg_off = (reg_off & BNXT_GRC_OFFSET_MASK) + 0x2000; 12372 fallthrough; 12373 case BNXT_FW_HEALTH_REG_TYPE_BAR0: 12374 writel(val, bp->bar0 + reg_off); 12375 break; 12376 case BNXT_FW_HEALTH_REG_TYPE_BAR1: 12377 writel(val, bp->bar1 + reg_off); 12378 break; 12379 } 12380 if (delay_msecs) { 12381 pci_read_config_dword(bp->pdev, 0, &val); 12382 msleep(delay_msecs); 12383 } 12384 } 12385 12386 bool bnxt_hwrm_reset_permitted(struct bnxt *bp) 12387 { 12388 struct hwrm_func_qcfg_output *resp; 12389 struct hwrm_func_qcfg_input *req; 12390 bool result = true; /* firmware will enforce if unknown */ 12391 12392 if (~bp->fw_cap & BNXT_FW_CAP_HOT_RESET_IF) 12393 return result; 12394 12395 if (hwrm_req_init(bp, req, HWRM_FUNC_QCFG)) 12396 return result; 12397 12398 req->fid = cpu_to_le16(0xffff); 12399 resp = hwrm_req_hold(bp, req); 12400 if (!hwrm_req_send(bp, req)) 12401 result = !!(le16_to_cpu(resp->flags) & 12402 FUNC_QCFG_RESP_FLAGS_HOT_RESET_ALLOWED); 12403 hwrm_req_drop(bp, req); 12404 return result; 12405 } 12406 12407 static void bnxt_reset_all(struct bnxt *bp) 12408 { 12409 struct bnxt_fw_health *fw_health = bp->fw_health; 12410 int i, rc; 12411 12412 if (bp->fw_cap & BNXT_FW_CAP_ERR_RECOVER_RELOAD) { 12413 bnxt_fw_reset_via_optee(bp); 12414 bp->fw_reset_timestamp = jiffies; 12415 return; 12416 } 12417 12418 if (fw_health->flags & ERROR_RECOVERY_QCFG_RESP_FLAGS_HOST) { 12419 for (i = 0; i < fw_health->fw_reset_seq_cnt; i++) 12420 bnxt_fw_reset_writel(bp, i); 12421 } else if (fw_health->flags & ERROR_RECOVERY_QCFG_RESP_FLAGS_CO_CPU) { 12422 struct hwrm_fw_reset_input *req; 12423 12424 rc = hwrm_req_init(bp, req, HWRM_FW_RESET); 12425 if (!rc) { 12426 req->target_id = cpu_to_le16(HWRM_TARGET_ID_KONG); 12427 req->embedded_proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP; 12428 req->selfrst_status = FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP; 12429 req->flags = FW_RESET_REQ_FLAGS_RESET_GRACEFUL; 12430 rc = hwrm_req_send(bp, req); 12431 } 12432 if (rc != -ENODEV) 12433 netdev_warn(bp->dev, "Unable to reset FW rc=%d\n", rc); 12434 } 12435 bp->fw_reset_timestamp = jiffies; 12436 } 12437 12438 static bool bnxt_fw_reset_timeout(struct bnxt *bp) 12439 { 12440 return time_after(jiffies, bp->fw_reset_timestamp + 12441 (bp->fw_reset_max_dsecs * HZ / 10)); 12442 } 12443 12444 static void bnxt_fw_reset_abort(struct bnxt *bp, int rc) 12445 { 12446 clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state); 12447 if (bp->fw_reset_state != BNXT_FW_RESET_STATE_POLL_VF) { 12448 bnxt_ulp_start(bp, rc); 12449 bnxt_dl_health_fw_status_update(bp, false); 12450 } 12451 bp->fw_reset_state = 0; 12452 dev_close(bp->dev); 12453 } 12454 12455 static void bnxt_fw_reset_task(struct work_struct *work) 12456 { 12457 struct bnxt *bp = container_of(work, struct bnxt, fw_reset_task.work); 12458 int rc = 0; 12459 12460 if (!test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) { 12461 netdev_err(bp->dev, "bnxt_fw_reset_task() called when not in fw reset mode!\n"); 12462 return; 12463 } 12464 12465 switch (bp->fw_reset_state) { 12466 case BNXT_FW_RESET_STATE_POLL_VF: { 12467 int n = bnxt_get_registered_vfs(bp); 12468 int tmo; 12469 12470 if (n < 0) { 12471 netdev_err(bp->dev, "Firmware reset aborted, subsequent func_qcfg cmd failed, rc = %d, %d msecs since reset timestamp\n", 12472 n, jiffies_to_msecs(jiffies - 12473 bp->fw_reset_timestamp)); 12474 goto fw_reset_abort; 12475 } else if (n > 0) { 12476 if (bnxt_fw_reset_timeout(bp)) { 12477 clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state); 12478 bp->fw_reset_state = 0; 12479 netdev_err(bp->dev, "Firmware reset aborted, bnxt_get_registered_vfs() returns %d\n", 12480 n); 12481 return; 12482 } 12483 bnxt_queue_fw_reset_work(bp, HZ / 10); 12484 return; 12485 } 12486 bp->fw_reset_timestamp = jiffies; 12487 rtnl_lock(); 12488 if (test_bit(BNXT_STATE_ABORT_ERR, &bp->state)) { 12489 bnxt_fw_reset_abort(bp, rc); 12490 rtnl_unlock(); 12491 return; 12492 } 12493 bnxt_fw_reset_close(bp); 12494 if (bp->fw_cap & BNXT_FW_CAP_ERR_RECOVER_RELOAD) { 12495 bp->fw_reset_state = BNXT_FW_RESET_STATE_POLL_FW_DOWN; 12496 tmo = HZ / 10; 12497 } else { 12498 bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV; 12499 tmo = bp->fw_reset_min_dsecs * HZ / 10; 12500 } 12501 rtnl_unlock(); 12502 bnxt_queue_fw_reset_work(bp, tmo); 12503 return; 12504 } 12505 case BNXT_FW_RESET_STATE_POLL_FW_DOWN: { 12506 u32 val; 12507 12508 val = bnxt_fw_health_readl(bp, BNXT_FW_HEALTH_REG); 12509 if (!(val & BNXT_FW_STATUS_SHUTDOWN) && 12510 !bnxt_fw_reset_timeout(bp)) { 12511 bnxt_queue_fw_reset_work(bp, HZ / 5); 12512 return; 12513 } 12514 12515 if (!bp->fw_health->primary) { 12516 u32 wait_dsecs = bp->fw_health->normal_func_wait_dsecs; 12517 12518 bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV; 12519 bnxt_queue_fw_reset_work(bp, wait_dsecs * HZ / 10); 12520 return; 12521 } 12522 bp->fw_reset_state = BNXT_FW_RESET_STATE_RESET_FW; 12523 } 12524 fallthrough; 12525 case BNXT_FW_RESET_STATE_RESET_FW: 12526 bnxt_reset_all(bp); 12527 bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV; 12528 bnxt_queue_fw_reset_work(bp, bp->fw_reset_min_dsecs * HZ / 10); 12529 return; 12530 case BNXT_FW_RESET_STATE_ENABLE_DEV: 12531 bnxt_inv_fw_health_reg(bp); 12532 if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state) && 12533 !bp->fw_reset_min_dsecs) { 12534 u16 val; 12535 12536 pci_read_config_word(bp->pdev, PCI_SUBSYSTEM_ID, &val); 12537 if (val == 0xffff) { 12538 if (bnxt_fw_reset_timeout(bp)) { 12539 netdev_err(bp->dev, "Firmware reset aborted, PCI config space invalid\n"); 12540 rc = -ETIMEDOUT; 12541 goto fw_reset_abort; 12542 } 12543 bnxt_queue_fw_reset_work(bp, HZ / 1000); 12544 return; 12545 } 12546 } 12547 clear_bit(BNXT_STATE_FW_FATAL_COND, &bp->state); 12548 clear_bit(BNXT_STATE_FW_NON_FATAL_COND, &bp->state); 12549 if (test_and_clear_bit(BNXT_STATE_FW_ACTIVATE_RESET, &bp->state) && 12550 !test_bit(BNXT_STATE_FW_ACTIVATE, &bp->state)) 12551 bnxt_dl_remote_reload(bp); 12552 if (pci_enable_device(bp->pdev)) { 12553 netdev_err(bp->dev, "Cannot re-enable PCI device\n"); 12554 rc = -ENODEV; 12555 goto fw_reset_abort; 12556 } 12557 pci_set_master(bp->pdev); 12558 bp->fw_reset_state = BNXT_FW_RESET_STATE_POLL_FW; 12559 fallthrough; 12560 case BNXT_FW_RESET_STATE_POLL_FW: 12561 bp->hwrm_cmd_timeout = SHORT_HWRM_CMD_TIMEOUT; 12562 rc = bnxt_hwrm_poll(bp); 12563 if (rc) { 12564 if (bnxt_fw_reset_timeout(bp)) { 12565 netdev_err(bp->dev, "Firmware reset aborted\n"); 12566 goto fw_reset_abort_status; 12567 } 12568 bnxt_queue_fw_reset_work(bp, HZ / 5); 12569 return; 12570 } 12571 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT; 12572 bp->fw_reset_state = BNXT_FW_RESET_STATE_OPENING; 12573 fallthrough; 12574 case BNXT_FW_RESET_STATE_OPENING: 12575 while (!rtnl_trylock()) { 12576 bnxt_queue_fw_reset_work(bp, HZ / 10); 12577 return; 12578 } 12579 rc = bnxt_open(bp->dev); 12580 if (rc) { 12581 netdev_err(bp->dev, "bnxt_open() failed during FW reset\n"); 12582 bnxt_fw_reset_abort(bp, rc); 12583 rtnl_unlock(); 12584 return; 12585 } 12586 12587 if ((bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY) && 12588 bp->fw_health->enabled) { 12589 bp->fw_health->last_fw_reset_cnt = 12590 bnxt_fw_health_readl(bp, BNXT_FW_RESET_CNT_REG); 12591 } 12592 bp->fw_reset_state = 0; 12593 /* Make sure fw_reset_state is 0 before clearing the flag */ 12594 smp_mb__before_atomic(); 12595 clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state); 12596 bnxt_ulp_start(bp, 0); 12597 bnxt_reenable_sriov(bp); 12598 bnxt_vf_reps_alloc(bp); 12599 bnxt_vf_reps_open(bp); 12600 bnxt_ptp_reapply_pps(bp); 12601 clear_bit(BNXT_STATE_FW_ACTIVATE, &bp->state); 12602 if (test_and_clear_bit(BNXT_STATE_RECOVER, &bp->state)) { 12603 bnxt_dl_health_fw_recovery_done(bp); 12604 bnxt_dl_health_fw_status_update(bp, true); 12605 } 12606 rtnl_unlock(); 12607 break; 12608 } 12609 return; 12610 12611 fw_reset_abort_status: 12612 if (bp->fw_health->status_reliable || 12613 (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)) { 12614 u32 sts = bnxt_fw_health_readl(bp, BNXT_FW_HEALTH_REG); 12615 12616 netdev_err(bp->dev, "fw_health_status 0x%x\n", sts); 12617 } 12618 fw_reset_abort: 12619 rtnl_lock(); 12620 bnxt_fw_reset_abort(bp, rc); 12621 rtnl_unlock(); 12622 } 12623 12624 static int bnxt_init_board(struct pci_dev *pdev, struct net_device *dev) 12625 { 12626 int rc; 12627 struct bnxt *bp = netdev_priv(dev); 12628 12629 SET_NETDEV_DEV(dev, &pdev->dev); 12630 12631 /* enable device (incl. PCI PM wakeup), and bus-mastering */ 12632 rc = pci_enable_device(pdev); 12633 if (rc) { 12634 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n"); 12635 goto init_err; 12636 } 12637 12638 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 12639 dev_err(&pdev->dev, 12640 "Cannot find PCI device base address, aborting\n"); 12641 rc = -ENODEV; 12642 goto init_err_disable; 12643 } 12644 12645 rc = pci_request_regions(pdev, DRV_MODULE_NAME); 12646 if (rc) { 12647 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n"); 12648 goto init_err_disable; 12649 } 12650 12651 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) != 0 && 12652 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)) != 0) { 12653 dev_err(&pdev->dev, "System does not support DMA, aborting\n"); 12654 rc = -EIO; 12655 goto init_err_release; 12656 } 12657 12658 pci_set_master(pdev); 12659 12660 bp->dev = dev; 12661 bp->pdev = pdev; 12662 12663 /* Doorbell BAR bp->bar1 is mapped after bnxt_fw_init_one_p2() 12664 * determines the BAR size. 12665 */ 12666 bp->bar0 = pci_ioremap_bar(pdev, 0); 12667 if (!bp->bar0) { 12668 dev_err(&pdev->dev, "Cannot map device registers, aborting\n"); 12669 rc = -ENOMEM; 12670 goto init_err_release; 12671 } 12672 12673 bp->bar2 = pci_ioremap_bar(pdev, 4); 12674 if (!bp->bar2) { 12675 dev_err(&pdev->dev, "Cannot map bar4 registers, aborting\n"); 12676 rc = -ENOMEM; 12677 goto init_err_release; 12678 } 12679 12680 INIT_WORK(&bp->sp_task, bnxt_sp_task); 12681 INIT_DELAYED_WORK(&bp->fw_reset_task, bnxt_fw_reset_task); 12682 12683 spin_lock_init(&bp->ntp_fltr_lock); 12684 #if BITS_PER_LONG == 32 12685 spin_lock_init(&bp->db_lock); 12686 #endif 12687 12688 bp->rx_ring_size = BNXT_DEFAULT_RX_RING_SIZE; 12689 bp->tx_ring_size = BNXT_DEFAULT_TX_RING_SIZE; 12690 12691 timer_setup(&bp->timer, bnxt_timer, 0); 12692 bp->current_interval = BNXT_TIMER_INTERVAL; 12693 12694 bp->vxlan_fw_dst_port_id = INVALID_HW_RING_ID; 12695 bp->nge_fw_dst_port_id = INVALID_HW_RING_ID; 12696 12697 clear_bit(BNXT_STATE_OPEN, &bp->state); 12698 return 0; 12699 12700 init_err_release: 12701 bnxt_unmap_bars(bp, pdev); 12702 pci_release_regions(pdev); 12703 12704 init_err_disable: 12705 pci_disable_device(pdev); 12706 12707 init_err: 12708 return rc; 12709 } 12710 12711 /* rtnl_lock held */ 12712 static int bnxt_change_mac_addr(struct net_device *dev, void *p) 12713 { 12714 struct sockaddr *addr = p; 12715 struct bnxt *bp = netdev_priv(dev); 12716 int rc = 0; 12717 12718 if (!is_valid_ether_addr(addr->sa_data)) 12719 return -EADDRNOTAVAIL; 12720 12721 if (ether_addr_equal(addr->sa_data, dev->dev_addr)) 12722 return 0; 12723 12724 rc = bnxt_approve_mac(bp, addr->sa_data, true); 12725 if (rc) 12726 return rc; 12727 12728 eth_hw_addr_set(dev, addr->sa_data); 12729 if (netif_running(dev)) { 12730 bnxt_close_nic(bp, false, false); 12731 rc = bnxt_open_nic(bp, false, false); 12732 } 12733 12734 return rc; 12735 } 12736 12737 /* rtnl_lock held */ 12738 static int bnxt_change_mtu(struct net_device *dev, int new_mtu) 12739 { 12740 struct bnxt *bp = netdev_priv(dev); 12741 12742 if (netif_running(dev)) 12743 bnxt_close_nic(bp, true, false); 12744 12745 dev->mtu = new_mtu; 12746 bnxt_set_ring_params(bp); 12747 12748 if (netif_running(dev)) 12749 return bnxt_open_nic(bp, true, false); 12750 12751 return 0; 12752 } 12753 12754 int bnxt_setup_mq_tc(struct net_device *dev, u8 tc) 12755 { 12756 struct bnxt *bp = netdev_priv(dev); 12757 bool sh = false; 12758 int rc; 12759 12760 if (tc > bp->max_tc) { 12761 netdev_err(dev, "Too many traffic classes requested: %d. Max supported is %d.\n", 12762 tc, bp->max_tc); 12763 return -EINVAL; 12764 } 12765 12766 if (netdev_get_num_tc(dev) == tc) 12767 return 0; 12768 12769 if (bp->flags & BNXT_FLAG_SHARED_RINGS) 12770 sh = true; 12771 12772 rc = bnxt_check_rings(bp, bp->tx_nr_rings_per_tc, bp->rx_nr_rings, 12773 sh, tc, bp->tx_nr_rings_xdp); 12774 if (rc) 12775 return rc; 12776 12777 /* Needs to close the device and do hw resource re-allocations */ 12778 if (netif_running(bp->dev)) 12779 bnxt_close_nic(bp, true, false); 12780 12781 if (tc) { 12782 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tc; 12783 netdev_set_num_tc(dev, tc); 12784 } else { 12785 bp->tx_nr_rings = bp->tx_nr_rings_per_tc; 12786 netdev_reset_tc(dev); 12787 } 12788 bp->tx_nr_rings += bp->tx_nr_rings_xdp; 12789 bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) : 12790 bp->tx_nr_rings + bp->rx_nr_rings; 12791 12792 if (netif_running(bp->dev)) 12793 return bnxt_open_nic(bp, true, false); 12794 12795 return 0; 12796 } 12797 12798 static int bnxt_setup_tc_block_cb(enum tc_setup_type type, void *type_data, 12799 void *cb_priv) 12800 { 12801 struct bnxt *bp = cb_priv; 12802 12803 if (!bnxt_tc_flower_enabled(bp) || 12804 !tc_cls_can_offload_and_chain0(bp->dev, type_data)) 12805 return -EOPNOTSUPP; 12806 12807 switch (type) { 12808 case TC_SETUP_CLSFLOWER: 12809 return bnxt_tc_setup_flower(bp, bp->pf.fw_fid, type_data); 12810 default: 12811 return -EOPNOTSUPP; 12812 } 12813 } 12814 12815 LIST_HEAD(bnxt_block_cb_list); 12816 12817 static int bnxt_setup_tc(struct net_device *dev, enum tc_setup_type type, 12818 void *type_data) 12819 { 12820 struct bnxt *bp = netdev_priv(dev); 12821 12822 switch (type) { 12823 case TC_SETUP_BLOCK: 12824 return flow_block_cb_setup_simple(type_data, 12825 &bnxt_block_cb_list, 12826 bnxt_setup_tc_block_cb, 12827 bp, bp, true); 12828 case TC_SETUP_QDISC_MQPRIO: { 12829 struct tc_mqprio_qopt *mqprio = type_data; 12830 12831 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS; 12832 12833 return bnxt_setup_mq_tc(dev, mqprio->num_tc); 12834 } 12835 default: 12836 return -EOPNOTSUPP; 12837 } 12838 } 12839 12840 #ifdef CONFIG_RFS_ACCEL 12841 static bool bnxt_fltr_match(struct bnxt_ntuple_filter *f1, 12842 struct bnxt_ntuple_filter *f2) 12843 { 12844 struct flow_keys *keys1 = &f1->fkeys; 12845 struct flow_keys *keys2 = &f2->fkeys; 12846 12847 if (keys1->basic.n_proto != keys2->basic.n_proto || 12848 keys1->basic.ip_proto != keys2->basic.ip_proto) 12849 return false; 12850 12851 if (keys1->basic.n_proto == htons(ETH_P_IP)) { 12852 if (keys1->addrs.v4addrs.src != keys2->addrs.v4addrs.src || 12853 keys1->addrs.v4addrs.dst != keys2->addrs.v4addrs.dst) 12854 return false; 12855 } else { 12856 if (memcmp(&keys1->addrs.v6addrs.src, &keys2->addrs.v6addrs.src, 12857 sizeof(keys1->addrs.v6addrs.src)) || 12858 memcmp(&keys1->addrs.v6addrs.dst, &keys2->addrs.v6addrs.dst, 12859 sizeof(keys1->addrs.v6addrs.dst))) 12860 return false; 12861 } 12862 12863 if (keys1->ports.ports == keys2->ports.ports && 12864 keys1->control.flags == keys2->control.flags && 12865 ether_addr_equal(f1->src_mac_addr, f2->src_mac_addr) && 12866 ether_addr_equal(f1->dst_mac_addr, f2->dst_mac_addr)) 12867 return true; 12868 12869 return false; 12870 } 12871 12872 static int bnxt_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb, 12873 u16 rxq_index, u32 flow_id) 12874 { 12875 struct bnxt *bp = netdev_priv(dev); 12876 struct bnxt_ntuple_filter *fltr, *new_fltr; 12877 struct flow_keys *fkeys; 12878 struct ethhdr *eth = (struct ethhdr *)skb_mac_header(skb); 12879 int rc = 0, idx, bit_id, l2_idx = 0; 12880 struct hlist_head *head; 12881 u32 flags; 12882 12883 if (!ether_addr_equal(dev->dev_addr, eth->h_dest)) { 12884 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 12885 int off = 0, j; 12886 12887 netif_addr_lock_bh(dev); 12888 for (j = 0; j < vnic->uc_filter_count; j++, off += ETH_ALEN) { 12889 if (ether_addr_equal(eth->h_dest, 12890 vnic->uc_list + off)) { 12891 l2_idx = j + 1; 12892 break; 12893 } 12894 } 12895 netif_addr_unlock_bh(dev); 12896 if (!l2_idx) 12897 return -EINVAL; 12898 } 12899 new_fltr = kzalloc(sizeof(*new_fltr), GFP_ATOMIC); 12900 if (!new_fltr) 12901 return -ENOMEM; 12902 12903 fkeys = &new_fltr->fkeys; 12904 if (!skb_flow_dissect_flow_keys(skb, fkeys, 0)) { 12905 rc = -EPROTONOSUPPORT; 12906 goto err_free; 12907 } 12908 12909 if ((fkeys->basic.n_proto != htons(ETH_P_IP) && 12910 fkeys->basic.n_proto != htons(ETH_P_IPV6)) || 12911 ((fkeys->basic.ip_proto != IPPROTO_TCP) && 12912 (fkeys->basic.ip_proto != IPPROTO_UDP))) { 12913 rc = -EPROTONOSUPPORT; 12914 goto err_free; 12915 } 12916 if (fkeys->basic.n_proto == htons(ETH_P_IPV6) && 12917 bp->hwrm_spec_code < 0x10601) { 12918 rc = -EPROTONOSUPPORT; 12919 goto err_free; 12920 } 12921 flags = fkeys->control.flags; 12922 if (((flags & FLOW_DIS_ENCAPSULATION) && 12923 bp->hwrm_spec_code < 0x10601) || (flags & FLOW_DIS_IS_FRAGMENT)) { 12924 rc = -EPROTONOSUPPORT; 12925 goto err_free; 12926 } 12927 12928 memcpy(new_fltr->dst_mac_addr, eth->h_dest, ETH_ALEN); 12929 memcpy(new_fltr->src_mac_addr, eth->h_source, ETH_ALEN); 12930 12931 idx = skb_get_hash_raw(skb) & BNXT_NTP_FLTR_HASH_MASK; 12932 head = &bp->ntp_fltr_hash_tbl[idx]; 12933 rcu_read_lock(); 12934 hlist_for_each_entry_rcu(fltr, head, hash) { 12935 if (bnxt_fltr_match(fltr, new_fltr)) { 12936 rc = fltr->sw_id; 12937 rcu_read_unlock(); 12938 goto err_free; 12939 } 12940 } 12941 rcu_read_unlock(); 12942 12943 spin_lock_bh(&bp->ntp_fltr_lock); 12944 bit_id = bitmap_find_free_region(bp->ntp_fltr_bmap, 12945 BNXT_NTP_FLTR_MAX_FLTR, 0); 12946 if (bit_id < 0) { 12947 spin_unlock_bh(&bp->ntp_fltr_lock); 12948 rc = -ENOMEM; 12949 goto err_free; 12950 } 12951 12952 new_fltr->sw_id = (u16)bit_id; 12953 new_fltr->flow_id = flow_id; 12954 new_fltr->l2_fltr_idx = l2_idx; 12955 new_fltr->rxq = rxq_index; 12956 hlist_add_head_rcu(&new_fltr->hash, head); 12957 bp->ntp_fltr_count++; 12958 spin_unlock_bh(&bp->ntp_fltr_lock); 12959 12960 set_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event); 12961 bnxt_queue_sp_work(bp); 12962 12963 return new_fltr->sw_id; 12964 12965 err_free: 12966 kfree(new_fltr); 12967 return rc; 12968 } 12969 12970 static void bnxt_cfg_ntp_filters(struct bnxt *bp) 12971 { 12972 int i; 12973 12974 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) { 12975 struct hlist_head *head; 12976 struct hlist_node *tmp; 12977 struct bnxt_ntuple_filter *fltr; 12978 int rc; 12979 12980 head = &bp->ntp_fltr_hash_tbl[i]; 12981 hlist_for_each_entry_safe(fltr, tmp, head, hash) { 12982 bool del = false; 12983 12984 if (test_bit(BNXT_FLTR_VALID, &fltr->state)) { 12985 if (rps_may_expire_flow(bp->dev, fltr->rxq, 12986 fltr->flow_id, 12987 fltr->sw_id)) { 12988 bnxt_hwrm_cfa_ntuple_filter_free(bp, 12989 fltr); 12990 del = true; 12991 } 12992 } else { 12993 rc = bnxt_hwrm_cfa_ntuple_filter_alloc(bp, 12994 fltr); 12995 if (rc) 12996 del = true; 12997 else 12998 set_bit(BNXT_FLTR_VALID, &fltr->state); 12999 } 13000 13001 if (del) { 13002 spin_lock_bh(&bp->ntp_fltr_lock); 13003 hlist_del_rcu(&fltr->hash); 13004 bp->ntp_fltr_count--; 13005 spin_unlock_bh(&bp->ntp_fltr_lock); 13006 synchronize_rcu(); 13007 clear_bit(fltr->sw_id, bp->ntp_fltr_bmap); 13008 kfree(fltr); 13009 } 13010 } 13011 } 13012 if (test_and_clear_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event)) 13013 netdev_info(bp->dev, "Receive PF driver unload event!\n"); 13014 } 13015 13016 #else 13017 13018 static void bnxt_cfg_ntp_filters(struct bnxt *bp) 13019 { 13020 } 13021 13022 #endif /* CONFIG_RFS_ACCEL */ 13023 13024 static int bnxt_udp_tunnel_sync(struct net_device *netdev, unsigned int table) 13025 { 13026 struct bnxt *bp = netdev_priv(netdev); 13027 struct udp_tunnel_info ti; 13028 unsigned int cmd; 13029 13030 udp_tunnel_nic_get_port(netdev, table, 0, &ti); 13031 if (ti.type == UDP_TUNNEL_TYPE_VXLAN) 13032 cmd = TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN; 13033 else 13034 cmd = TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE; 13035 13036 if (ti.port) 13037 return bnxt_hwrm_tunnel_dst_port_alloc(bp, ti.port, cmd); 13038 13039 return bnxt_hwrm_tunnel_dst_port_free(bp, cmd); 13040 } 13041 13042 static const struct udp_tunnel_nic_info bnxt_udp_tunnels = { 13043 .sync_table = bnxt_udp_tunnel_sync, 13044 .flags = UDP_TUNNEL_NIC_INFO_MAY_SLEEP | 13045 UDP_TUNNEL_NIC_INFO_OPEN_ONLY, 13046 .tables = { 13047 { .n_entries = 1, .tunnel_types = UDP_TUNNEL_TYPE_VXLAN, }, 13048 { .n_entries = 1, .tunnel_types = UDP_TUNNEL_TYPE_GENEVE, }, 13049 }, 13050 }; 13051 13052 static int bnxt_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq, 13053 struct net_device *dev, u32 filter_mask, 13054 int nlflags) 13055 { 13056 struct bnxt *bp = netdev_priv(dev); 13057 13058 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, bp->br_mode, 0, 0, 13059 nlflags, filter_mask, NULL); 13060 } 13061 13062 static int bnxt_bridge_setlink(struct net_device *dev, struct nlmsghdr *nlh, 13063 u16 flags, struct netlink_ext_ack *extack) 13064 { 13065 struct bnxt *bp = netdev_priv(dev); 13066 struct nlattr *attr, *br_spec; 13067 int rem, rc = 0; 13068 13069 if (bp->hwrm_spec_code < 0x10708 || !BNXT_SINGLE_PF(bp)) 13070 return -EOPNOTSUPP; 13071 13072 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC); 13073 if (!br_spec) 13074 return -EINVAL; 13075 13076 nla_for_each_nested(attr, br_spec, rem) { 13077 u16 mode; 13078 13079 if (nla_type(attr) != IFLA_BRIDGE_MODE) 13080 continue; 13081 13082 if (nla_len(attr) < sizeof(mode)) 13083 return -EINVAL; 13084 13085 mode = nla_get_u16(attr); 13086 if (mode == bp->br_mode) 13087 break; 13088 13089 rc = bnxt_hwrm_set_br_mode(bp, mode); 13090 if (!rc) 13091 bp->br_mode = mode; 13092 break; 13093 } 13094 return rc; 13095 } 13096 13097 int bnxt_get_port_parent_id(struct net_device *dev, 13098 struct netdev_phys_item_id *ppid) 13099 { 13100 struct bnxt *bp = netdev_priv(dev); 13101 13102 if (bp->eswitch_mode != DEVLINK_ESWITCH_MODE_SWITCHDEV) 13103 return -EOPNOTSUPP; 13104 13105 /* The PF and it's VF-reps only support the switchdev framework */ 13106 if (!BNXT_PF(bp) || !(bp->flags & BNXT_FLAG_DSN_VALID)) 13107 return -EOPNOTSUPP; 13108 13109 ppid->id_len = sizeof(bp->dsn); 13110 memcpy(ppid->id, bp->dsn, ppid->id_len); 13111 13112 return 0; 13113 } 13114 13115 static const struct net_device_ops bnxt_netdev_ops = { 13116 .ndo_open = bnxt_open, 13117 .ndo_start_xmit = bnxt_start_xmit, 13118 .ndo_stop = bnxt_close, 13119 .ndo_get_stats64 = bnxt_get_stats64, 13120 .ndo_set_rx_mode = bnxt_set_rx_mode, 13121 .ndo_eth_ioctl = bnxt_ioctl, 13122 .ndo_validate_addr = eth_validate_addr, 13123 .ndo_set_mac_address = bnxt_change_mac_addr, 13124 .ndo_change_mtu = bnxt_change_mtu, 13125 .ndo_fix_features = bnxt_fix_features, 13126 .ndo_set_features = bnxt_set_features, 13127 .ndo_features_check = bnxt_features_check, 13128 .ndo_tx_timeout = bnxt_tx_timeout, 13129 #ifdef CONFIG_BNXT_SRIOV 13130 .ndo_get_vf_config = bnxt_get_vf_config, 13131 .ndo_set_vf_mac = bnxt_set_vf_mac, 13132 .ndo_set_vf_vlan = bnxt_set_vf_vlan, 13133 .ndo_set_vf_rate = bnxt_set_vf_bw, 13134 .ndo_set_vf_link_state = bnxt_set_vf_link_state, 13135 .ndo_set_vf_spoofchk = bnxt_set_vf_spoofchk, 13136 .ndo_set_vf_trust = bnxt_set_vf_trust, 13137 #endif 13138 .ndo_setup_tc = bnxt_setup_tc, 13139 #ifdef CONFIG_RFS_ACCEL 13140 .ndo_rx_flow_steer = bnxt_rx_flow_steer, 13141 #endif 13142 .ndo_bpf = bnxt_xdp, 13143 .ndo_xdp_xmit = bnxt_xdp_xmit, 13144 .ndo_bridge_getlink = bnxt_bridge_getlink, 13145 .ndo_bridge_setlink = bnxt_bridge_setlink, 13146 }; 13147 13148 static void bnxt_remove_one(struct pci_dev *pdev) 13149 { 13150 struct net_device *dev = pci_get_drvdata(pdev); 13151 struct bnxt *bp = netdev_priv(dev); 13152 13153 if (BNXT_PF(bp)) 13154 bnxt_sriov_disable(bp); 13155 13156 bnxt_rdma_aux_device_uninit(bp); 13157 13158 bnxt_ptp_clear(bp); 13159 unregister_netdev(dev); 13160 clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state); 13161 /* Flush any pending tasks */ 13162 cancel_work_sync(&bp->sp_task); 13163 cancel_delayed_work_sync(&bp->fw_reset_task); 13164 bp->sp_event = 0; 13165 13166 bnxt_dl_fw_reporters_destroy(bp); 13167 bnxt_dl_unregister(bp); 13168 bnxt_shutdown_tc(bp); 13169 13170 bnxt_clear_int_mode(bp); 13171 bnxt_hwrm_func_drv_unrgtr(bp); 13172 bnxt_free_hwrm_resources(bp); 13173 bnxt_ethtool_free(bp); 13174 bnxt_dcb_free(bp); 13175 kfree(bp->ptp_cfg); 13176 bp->ptp_cfg = NULL; 13177 kfree(bp->fw_health); 13178 bp->fw_health = NULL; 13179 bnxt_cleanup_pci(bp); 13180 bnxt_free_ctx_mem(bp); 13181 kfree(bp->ctx); 13182 bp->ctx = NULL; 13183 kfree(bp->rss_indir_tbl); 13184 bp->rss_indir_tbl = NULL; 13185 bnxt_free_port_stats(bp); 13186 free_netdev(dev); 13187 } 13188 13189 static int bnxt_probe_phy(struct bnxt *bp, bool fw_dflt) 13190 { 13191 int rc = 0; 13192 struct bnxt_link_info *link_info = &bp->link_info; 13193 13194 bp->phy_flags = 0; 13195 rc = bnxt_hwrm_phy_qcaps(bp); 13196 if (rc) { 13197 netdev_err(bp->dev, "Probe phy can't get phy capabilities (rc: %x)\n", 13198 rc); 13199 return rc; 13200 } 13201 if (bp->phy_flags & BNXT_PHY_FL_NO_FCS) 13202 bp->dev->priv_flags |= IFF_SUPP_NOFCS; 13203 else 13204 bp->dev->priv_flags &= ~IFF_SUPP_NOFCS; 13205 if (!fw_dflt) 13206 return 0; 13207 13208 mutex_lock(&bp->link_lock); 13209 rc = bnxt_update_link(bp, false); 13210 if (rc) { 13211 mutex_unlock(&bp->link_lock); 13212 netdev_err(bp->dev, "Probe phy can't update link (rc: %x)\n", 13213 rc); 13214 return rc; 13215 } 13216 13217 /* Older firmware does not have supported_auto_speeds, so assume 13218 * that all supported speeds can be autonegotiated. 13219 */ 13220 if (link_info->auto_link_speeds && !link_info->support_auto_speeds) 13221 link_info->support_auto_speeds = link_info->support_speeds; 13222 13223 bnxt_init_ethtool_link_settings(bp); 13224 mutex_unlock(&bp->link_lock); 13225 return 0; 13226 } 13227 13228 static int bnxt_get_max_irq(struct pci_dev *pdev) 13229 { 13230 u16 ctrl; 13231 13232 if (!pdev->msix_cap) 13233 return 1; 13234 13235 pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &ctrl); 13236 return (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1; 13237 } 13238 13239 static void _bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx, 13240 int *max_cp) 13241 { 13242 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 13243 int max_ring_grps = 0, max_irq; 13244 13245 *max_tx = hw_resc->max_tx_rings; 13246 *max_rx = hw_resc->max_rx_rings; 13247 *max_cp = bnxt_get_max_func_cp_rings_for_en(bp); 13248 max_irq = min_t(int, bnxt_get_max_func_irqs(bp) - 13249 bnxt_get_ulp_msix_num(bp), 13250 hw_resc->max_stat_ctxs - bnxt_get_ulp_stat_ctxs(bp)); 13251 if (!(bp->flags & BNXT_FLAG_CHIP_P5)) 13252 *max_cp = min_t(int, *max_cp, max_irq); 13253 max_ring_grps = hw_resc->max_hw_ring_grps; 13254 if (BNXT_CHIP_TYPE_NITRO_A0(bp) && BNXT_PF(bp)) { 13255 *max_cp -= 1; 13256 *max_rx -= 2; 13257 } 13258 if (bp->flags & BNXT_FLAG_AGG_RINGS) 13259 *max_rx >>= 1; 13260 if (bp->flags & BNXT_FLAG_CHIP_P5) { 13261 bnxt_trim_rings(bp, max_rx, max_tx, *max_cp, false); 13262 /* On P5 chips, max_cp output param should be available NQs */ 13263 *max_cp = max_irq; 13264 } 13265 *max_rx = min_t(int, *max_rx, max_ring_grps); 13266 } 13267 13268 int bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx, bool shared) 13269 { 13270 int rx, tx, cp; 13271 13272 _bnxt_get_max_rings(bp, &rx, &tx, &cp); 13273 *max_rx = rx; 13274 *max_tx = tx; 13275 if (!rx || !tx || !cp) 13276 return -ENOMEM; 13277 13278 return bnxt_trim_rings(bp, max_rx, max_tx, cp, shared); 13279 } 13280 13281 static int bnxt_get_dflt_rings(struct bnxt *bp, int *max_rx, int *max_tx, 13282 bool shared) 13283 { 13284 int rc; 13285 13286 rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared); 13287 if (rc && (bp->flags & BNXT_FLAG_AGG_RINGS)) { 13288 /* Not enough rings, try disabling agg rings. */ 13289 bp->flags &= ~BNXT_FLAG_AGG_RINGS; 13290 rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared); 13291 if (rc) { 13292 /* set BNXT_FLAG_AGG_RINGS back for consistency */ 13293 bp->flags |= BNXT_FLAG_AGG_RINGS; 13294 return rc; 13295 } 13296 bp->flags |= BNXT_FLAG_NO_AGG_RINGS; 13297 bp->dev->hw_features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW); 13298 bp->dev->features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW); 13299 bnxt_set_ring_params(bp); 13300 } 13301 13302 if (bp->flags & BNXT_FLAG_ROCE_CAP) { 13303 int max_cp, max_stat, max_irq; 13304 13305 /* Reserve minimum resources for RoCE */ 13306 max_cp = bnxt_get_max_func_cp_rings(bp); 13307 max_stat = bnxt_get_max_func_stat_ctxs(bp); 13308 max_irq = bnxt_get_max_func_irqs(bp); 13309 if (max_cp <= BNXT_MIN_ROCE_CP_RINGS || 13310 max_irq <= BNXT_MIN_ROCE_CP_RINGS || 13311 max_stat <= BNXT_MIN_ROCE_STAT_CTXS) 13312 return 0; 13313 13314 max_cp -= BNXT_MIN_ROCE_CP_RINGS; 13315 max_irq -= BNXT_MIN_ROCE_CP_RINGS; 13316 max_stat -= BNXT_MIN_ROCE_STAT_CTXS; 13317 max_cp = min_t(int, max_cp, max_irq); 13318 max_cp = min_t(int, max_cp, max_stat); 13319 rc = bnxt_trim_rings(bp, max_rx, max_tx, max_cp, shared); 13320 if (rc) 13321 rc = 0; 13322 } 13323 return rc; 13324 } 13325 13326 /* In initial default shared ring setting, each shared ring must have a 13327 * RX/TX ring pair. 13328 */ 13329 static void bnxt_trim_dflt_sh_rings(struct bnxt *bp) 13330 { 13331 bp->cp_nr_rings = min_t(int, bp->tx_nr_rings_per_tc, bp->rx_nr_rings); 13332 bp->rx_nr_rings = bp->cp_nr_rings; 13333 bp->tx_nr_rings_per_tc = bp->cp_nr_rings; 13334 bp->tx_nr_rings = bp->tx_nr_rings_per_tc; 13335 } 13336 13337 static int bnxt_set_dflt_rings(struct bnxt *bp, bool sh) 13338 { 13339 int dflt_rings, max_rx_rings, max_tx_rings, rc; 13340 13341 if (!bnxt_can_reserve_rings(bp)) 13342 return 0; 13343 13344 if (sh) 13345 bp->flags |= BNXT_FLAG_SHARED_RINGS; 13346 dflt_rings = is_kdump_kernel() ? 1 : netif_get_num_default_rss_queues(); 13347 /* Reduce default rings on multi-port cards so that total default 13348 * rings do not exceed CPU count. 13349 */ 13350 if (bp->port_count > 1) { 13351 int max_rings = 13352 max_t(int, num_online_cpus() / bp->port_count, 1); 13353 13354 dflt_rings = min_t(int, dflt_rings, max_rings); 13355 } 13356 rc = bnxt_get_dflt_rings(bp, &max_rx_rings, &max_tx_rings, sh); 13357 if (rc) 13358 return rc; 13359 bp->rx_nr_rings = min_t(int, dflt_rings, max_rx_rings); 13360 bp->tx_nr_rings_per_tc = min_t(int, dflt_rings, max_tx_rings); 13361 if (sh) 13362 bnxt_trim_dflt_sh_rings(bp); 13363 else 13364 bp->cp_nr_rings = bp->tx_nr_rings_per_tc + bp->rx_nr_rings; 13365 bp->tx_nr_rings = bp->tx_nr_rings_per_tc; 13366 13367 rc = __bnxt_reserve_rings(bp); 13368 if (rc && rc != -ENODEV) 13369 netdev_warn(bp->dev, "Unable to reserve tx rings\n"); 13370 bp->tx_nr_rings_per_tc = bp->tx_nr_rings; 13371 if (sh) 13372 bnxt_trim_dflt_sh_rings(bp); 13373 13374 /* Rings may have been trimmed, re-reserve the trimmed rings. */ 13375 if (bnxt_need_reserve_rings(bp)) { 13376 rc = __bnxt_reserve_rings(bp); 13377 if (rc && rc != -ENODEV) 13378 netdev_warn(bp->dev, "2nd rings reservation failed.\n"); 13379 bp->tx_nr_rings_per_tc = bp->tx_nr_rings; 13380 } 13381 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) { 13382 bp->rx_nr_rings++; 13383 bp->cp_nr_rings++; 13384 } 13385 if (rc) { 13386 bp->tx_nr_rings = 0; 13387 bp->rx_nr_rings = 0; 13388 } 13389 return rc; 13390 } 13391 13392 static int bnxt_init_dflt_ring_mode(struct bnxt *bp) 13393 { 13394 int rc; 13395 13396 if (bp->tx_nr_rings) 13397 return 0; 13398 13399 bnxt_ulp_irq_stop(bp); 13400 bnxt_clear_int_mode(bp); 13401 rc = bnxt_set_dflt_rings(bp, true); 13402 if (rc) { 13403 if (BNXT_VF(bp) && rc == -ENODEV) 13404 netdev_err(bp->dev, "Cannot configure VF rings while PF is unavailable.\n"); 13405 else 13406 netdev_err(bp->dev, "Not enough rings available.\n"); 13407 goto init_dflt_ring_err; 13408 } 13409 rc = bnxt_init_int_mode(bp); 13410 if (rc) 13411 goto init_dflt_ring_err; 13412 13413 bp->tx_nr_rings_per_tc = bp->tx_nr_rings; 13414 13415 bnxt_set_dflt_rfs(bp); 13416 13417 init_dflt_ring_err: 13418 bnxt_ulp_irq_restart(bp, rc); 13419 return rc; 13420 } 13421 13422 int bnxt_restore_pf_fw_resources(struct bnxt *bp) 13423 { 13424 int rc; 13425 13426 ASSERT_RTNL(); 13427 bnxt_hwrm_func_qcaps(bp); 13428 13429 if (netif_running(bp->dev)) 13430 __bnxt_close_nic(bp, true, false); 13431 13432 bnxt_ulp_irq_stop(bp); 13433 bnxt_clear_int_mode(bp); 13434 rc = bnxt_init_int_mode(bp); 13435 bnxt_ulp_irq_restart(bp, rc); 13436 13437 if (netif_running(bp->dev)) { 13438 if (rc) 13439 dev_close(bp->dev); 13440 else 13441 rc = bnxt_open_nic(bp, true, false); 13442 } 13443 13444 return rc; 13445 } 13446 13447 static int bnxt_init_mac_addr(struct bnxt *bp) 13448 { 13449 int rc = 0; 13450 13451 if (BNXT_PF(bp)) { 13452 eth_hw_addr_set(bp->dev, bp->pf.mac_addr); 13453 } else { 13454 #ifdef CONFIG_BNXT_SRIOV 13455 struct bnxt_vf_info *vf = &bp->vf; 13456 bool strict_approval = true; 13457 13458 if (is_valid_ether_addr(vf->mac_addr)) { 13459 /* overwrite netdev dev_addr with admin VF MAC */ 13460 eth_hw_addr_set(bp->dev, vf->mac_addr); 13461 /* Older PF driver or firmware may not approve this 13462 * correctly. 13463 */ 13464 strict_approval = false; 13465 } else { 13466 eth_hw_addr_random(bp->dev); 13467 } 13468 rc = bnxt_approve_mac(bp, bp->dev->dev_addr, strict_approval); 13469 #endif 13470 } 13471 return rc; 13472 } 13473 13474 static void bnxt_vpd_read_info(struct bnxt *bp) 13475 { 13476 struct pci_dev *pdev = bp->pdev; 13477 unsigned int vpd_size, kw_len; 13478 int pos, size; 13479 u8 *vpd_data; 13480 13481 vpd_data = pci_vpd_alloc(pdev, &vpd_size); 13482 if (IS_ERR(vpd_data)) { 13483 pci_warn(pdev, "Unable to read VPD\n"); 13484 return; 13485 } 13486 13487 pos = pci_vpd_find_ro_info_keyword(vpd_data, vpd_size, 13488 PCI_VPD_RO_KEYWORD_PARTNO, &kw_len); 13489 if (pos < 0) 13490 goto read_sn; 13491 13492 size = min_t(int, kw_len, BNXT_VPD_FLD_LEN - 1); 13493 memcpy(bp->board_partno, &vpd_data[pos], size); 13494 13495 read_sn: 13496 pos = pci_vpd_find_ro_info_keyword(vpd_data, vpd_size, 13497 PCI_VPD_RO_KEYWORD_SERIALNO, 13498 &kw_len); 13499 if (pos < 0) 13500 goto exit; 13501 13502 size = min_t(int, kw_len, BNXT_VPD_FLD_LEN - 1); 13503 memcpy(bp->board_serialno, &vpd_data[pos], size); 13504 exit: 13505 kfree(vpd_data); 13506 } 13507 13508 static int bnxt_pcie_dsn_get(struct bnxt *bp, u8 dsn[]) 13509 { 13510 struct pci_dev *pdev = bp->pdev; 13511 u64 qword; 13512 13513 qword = pci_get_dsn(pdev); 13514 if (!qword) { 13515 netdev_info(bp->dev, "Unable to read adapter's DSN\n"); 13516 return -EOPNOTSUPP; 13517 } 13518 13519 put_unaligned_le64(qword, dsn); 13520 13521 bp->flags |= BNXT_FLAG_DSN_VALID; 13522 return 0; 13523 } 13524 13525 static int bnxt_map_db_bar(struct bnxt *bp) 13526 { 13527 if (!bp->db_size) 13528 return -ENODEV; 13529 bp->bar1 = pci_iomap(bp->pdev, 2, bp->db_size); 13530 if (!bp->bar1) 13531 return -ENOMEM; 13532 return 0; 13533 } 13534 13535 void bnxt_print_device_info(struct bnxt *bp) 13536 { 13537 netdev_info(bp->dev, "%s found at mem %lx, node addr %pM\n", 13538 board_info[bp->board_idx].name, 13539 (long)pci_resource_start(bp->pdev, 0), bp->dev->dev_addr); 13540 13541 pcie_print_link_status(bp->pdev); 13542 } 13543 13544 static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 13545 { 13546 struct net_device *dev; 13547 struct bnxt *bp; 13548 int rc, max_irqs; 13549 13550 if (pci_is_bridge(pdev)) 13551 return -ENODEV; 13552 13553 /* Clear any pending DMA transactions from crash kernel 13554 * while loading driver in capture kernel. 13555 */ 13556 if (is_kdump_kernel()) { 13557 pci_clear_master(pdev); 13558 pcie_flr(pdev); 13559 } 13560 13561 max_irqs = bnxt_get_max_irq(pdev); 13562 dev = alloc_etherdev_mq(sizeof(*bp), max_irqs); 13563 if (!dev) 13564 return -ENOMEM; 13565 13566 bp = netdev_priv(dev); 13567 bp->board_idx = ent->driver_data; 13568 bp->msg_enable = BNXT_DEF_MSG_ENABLE; 13569 bnxt_set_max_func_irqs(bp, max_irqs); 13570 13571 if (bnxt_vf_pciid(bp->board_idx)) 13572 bp->flags |= BNXT_FLAG_VF; 13573 13574 /* No devlink port registration in case of a VF */ 13575 if (BNXT_PF(bp)) 13576 SET_NETDEV_DEVLINK_PORT(dev, &bp->dl_port); 13577 13578 if (pdev->msix_cap) 13579 bp->flags |= BNXT_FLAG_MSIX_CAP; 13580 13581 rc = bnxt_init_board(pdev, dev); 13582 if (rc < 0) 13583 goto init_err_free; 13584 13585 dev->netdev_ops = &bnxt_netdev_ops; 13586 dev->watchdog_timeo = BNXT_TX_TIMEOUT; 13587 dev->ethtool_ops = &bnxt_ethtool_ops; 13588 pci_set_drvdata(pdev, dev); 13589 13590 rc = bnxt_alloc_hwrm_resources(bp); 13591 if (rc) 13592 goto init_err_pci_clean; 13593 13594 mutex_init(&bp->hwrm_cmd_lock); 13595 mutex_init(&bp->link_lock); 13596 13597 rc = bnxt_fw_init_one_p1(bp); 13598 if (rc) 13599 goto init_err_pci_clean; 13600 13601 if (BNXT_PF(bp)) 13602 bnxt_vpd_read_info(bp); 13603 13604 if (BNXT_CHIP_P5(bp)) { 13605 bp->flags |= BNXT_FLAG_CHIP_P5; 13606 if (BNXT_CHIP_SR2(bp)) 13607 bp->flags |= BNXT_FLAG_CHIP_SR2; 13608 } 13609 13610 rc = bnxt_alloc_rss_indir_tbl(bp); 13611 if (rc) 13612 goto init_err_pci_clean; 13613 13614 rc = bnxt_fw_init_one_p2(bp); 13615 if (rc) 13616 goto init_err_pci_clean; 13617 13618 rc = bnxt_map_db_bar(bp); 13619 if (rc) { 13620 dev_err(&pdev->dev, "Cannot map doorbell BAR rc = %d, aborting\n", 13621 rc); 13622 goto init_err_pci_clean; 13623 } 13624 13625 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG | 13626 NETIF_F_TSO | NETIF_F_TSO6 | 13627 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE | 13628 NETIF_F_GSO_IPXIP4 | 13629 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM | 13630 NETIF_F_GSO_PARTIAL | NETIF_F_RXHASH | 13631 NETIF_F_RXCSUM | NETIF_F_GRO; 13632 13633 if (BNXT_SUPPORTS_TPA(bp)) 13634 dev->hw_features |= NETIF_F_LRO; 13635 13636 dev->hw_enc_features = 13637 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG | 13638 NETIF_F_TSO | NETIF_F_TSO6 | 13639 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE | 13640 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM | 13641 NETIF_F_GSO_IPXIP4 | NETIF_F_GSO_PARTIAL; 13642 dev->udp_tunnel_nic_info = &bnxt_udp_tunnels; 13643 13644 dev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM | 13645 NETIF_F_GSO_GRE_CSUM; 13646 dev->vlan_features = dev->hw_features | NETIF_F_HIGHDMA; 13647 if (bp->fw_cap & BNXT_FW_CAP_VLAN_RX_STRIP) 13648 dev->hw_features |= BNXT_HW_FEATURE_VLAN_ALL_RX; 13649 if (bp->fw_cap & BNXT_FW_CAP_VLAN_TX_INSERT) 13650 dev->hw_features |= BNXT_HW_FEATURE_VLAN_ALL_TX; 13651 if (BNXT_SUPPORTS_TPA(bp)) 13652 dev->hw_features |= NETIF_F_GRO_HW; 13653 dev->features |= dev->hw_features | NETIF_F_HIGHDMA; 13654 if (dev->features & NETIF_F_GRO_HW) 13655 dev->features &= ~NETIF_F_LRO; 13656 dev->priv_flags |= IFF_UNICAST_FLT; 13657 13658 netif_set_tso_max_size(dev, GSO_MAX_SIZE); 13659 13660 dev->xdp_features = NETDEV_XDP_ACT_BASIC | NETDEV_XDP_ACT_REDIRECT | 13661 NETDEV_XDP_ACT_RX_SG; 13662 13663 #ifdef CONFIG_BNXT_SRIOV 13664 init_waitqueue_head(&bp->sriov_cfg_wait); 13665 #endif 13666 if (BNXT_SUPPORTS_TPA(bp)) { 13667 bp->gro_func = bnxt_gro_func_5730x; 13668 if (BNXT_CHIP_P4(bp)) 13669 bp->gro_func = bnxt_gro_func_5731x; 13670 else if (BNXT_CHIP_P5(bp)) 13671 bp->gro_func = bnxt_gro_func_5750x; 13672 } 13673 if (!BNXT_CHIP_P4_PLUS(bp)) 13674 bp->flags |= BNXT_FLAG_DOUBLE_DB; 13675 13676 rc = bnxt_init_mac_addr(bp); 13677 if (rc) { 13678 dev_err(&pdev->dev, "Unable to initialize mac address.\n"); 13679 rc = -EADDRNOTAVAIL; 13680 goto init_err_pci_clean; 13681 } 13682 13683 if (BNXT_PF(bp)) { 13684 /* Read the adapter's DSN to use as the eswitch switch_id */ 13685 rc = bnxt_pcie_dsn_get(bp, bp->dsn); 13686 } 13687 13688 /* MTU range: 60 - FW defined max */ 13689 dev->min_mtu = ETH_ZLEN; 13690 dev->max_mtu = bp->max_mtu; 13691 13692 rc = bnxt_probe_phy(bp, true); 13693 if (rc) 13694 goto init_err_pci_clean; 13695 13696 bnxt_set_rx_skb_mode(bp, false); 13697 bnxt_set_tpa_flags(bp); 13698 bnxt_set_ring_params(bp); 13699 rc = bnxt_set_dflt_rings(bp, true); 13700 if (rc) { 13701 if (BNXT_VF(bp) && rc == -ENODEV) { 13702 netdev_err(bp->dev, "Cannot configure VF rings while PF is unavailable.\n"); 13703 } else { 13704 netdev_err(bp->dev, "Not enough rings available.\n"); 13705 rc = -ENOMEM; 13706 } 13707 goto init_err_pci_clean; 13708 } 13709 13710 bnxt_fw_init_one_p3(bp); 13711 13712 bnxt_init_dflt_coal(bp); 13713 13714 if (dev->hw_features & BNXT_HW_FEATURE_VLAN_ALL_RX) 13715 bp->flags |= BNXT_FLAG_STRIP_VLAN; 13716 13717 rc = bnxt_init_int_mode(bp); 13718 if (rc) 13719 goto init_err_pci_clean; 13720 13721 /* No TC has been set yet and rings may have been trimmed due to 13722 * limited MSIX, so we re-initialize the TX rings per TC. 13723 */ 13724 bp->tx_nr_rings_per_tc = bp->tx_nr_rings; 13725 13726 if (BNXT_PF(bp)) { 13727 if (!bnxt_pf_wq) { 13728 bnxt_pf_wq = 13729 create_singlethread_workqueue("bnxt_pf_wq"); 13730 if (!bnxt_pf_wq) { 13731 dev_err(&pdev->dev, "Unable to create workqueue.\n"); 13732 rc = -ENOMEM; 13733 goto init_err_pci_clean; 13734 } 13735 } 13736 rc = bnxt_init_tc(bp); 13737 if (rc) 13738 netdev_err(dev, "Failed to initialize TC flower offload, err = %d.\n", 13739 rc); 13740 } 13741 13742 bnxt_inv_fw_health_reg(bp); 13743 rc = bnxt_dl_register(bp); 13744 if (rc) 13745 goto init_err_dl; 13746 13747 rc = register_netdev(dev); 13748 if (rc) 13749 goto init_err_cleanup; 13750 13751 bnxt_dl_fw_reporters_create(bp); 13752 13753 bnxt_rdma_aux_device_init(bp); 13754 13755 bnxt_print_device_info(bp); 13756 13757 pci_save_state(pdev); 13758 13759 return 0; 13760 init_err_cleanup: 13761 bnxt_dl_unregister(bp); 13762 init_err_dl: 13763 bnxt_shutdown_tc(bp); 13764 bnxt_clear_int_mode(bp); 13765 13766 init_err_pci_clean: 13767 bnxt_hwrm_func_drv_unrgtr(bp); 13768 bnxt_free_hwrm_resources(bp); 13769 bnxt_ethtool_free(bp); 13770 bnxt_ptp_clear(bp); 13771 kfree(bp->ptp_cfg); 13772 bp->ptp_cfg = NULL; 13773 kfree(bp->fw_health); 13774 bp->fw_health = NULL; 13775 bnxt_cleanup_pci(bp); 13776 bnxt_free_ctx_mem(bp); 13777 kfree(bp->ctx); 13778 bp->ctx = NULL; 13779 kfree(bp->rss_indir_tbl); 13780 bp->rss_indir_tbl = NULL; 13781 13782 init_err_free: 13783 free_netdev(dev); 13784 return rc; 13785 } 13786 13787 static void bnxt_shutdown(struct pci_dev *pdev) 13788 { 13789 struct net_device *dev = pci_get_drvdata(pdev); 13790 struct bnxt *bp; 13791 13792 if (!dev) 13793 return; 13794 13795 rtnl_lock(); 13796 bp = netdev_priv(dev); 13797 if (!bp) 13798 goto shutdown_exit; 13799 13800 if (netif_running(dev)) 13801 dev_close(dev); 13802 13803 bnxt_clear_int_mode(bp); 13804 pci_disable_device(pdev); 13805 13806 if (system_state == SYSTEM_POWER_OFF) { 13807 pci_wake_from_d3(pdev, bp->wol); 13808 pci_set_power_state(pdev, PCI_D3hot); 13809 } 13810 13811 shutdown_exit: 13812 rtnl_unlock(); 13813 } 13814 13815 #ifdef CONFIG_PM_SLEEP 13816 static int bnxt_suspend(struct device *device) 13817 { 13818 struct net_device *dev = dev_get_drvdata(device); 13819 struct bnxt *bp = netdev_priv(dev); 13820 int rc = 0; 13821 13822 rtnl_lock(); 13823 bnxt_ulp_stop(bp); 13824 if (netif_running(dev)) { 13825 netif_device_detach(dev); 13826 rc = bnxt_close(dev); 13827 } 13828 bnxt_hwrm_func_drv_unrgtr(bp); 13829 pci_disable_device(bp->pdev); 13830 bnxt_free_ctx_mem(bp); 13831 kfree(bp->ctx); 13832 bp->ctx = NULL; 13833 rtnl_unlock(); 13834 return rc; 13835 } 13836 13837 static int bnxt_resume(struct device *device) 13838 { 13839 struct net_device *dev = dev_get_drvdata(device); 13840 struct bnxt *bp = netdev_priv(dev); 13841 int rc = 0; 13842 13843 rtnl_lock(); 13844 rc = pci_enable_device(bp->pdev); 13845 if (rc) { 13846 netdev_err(dev, "Cannot re-enable PCI device during resume, err = %d\n", 13847 rc); 13848 goto resume_exit; 13849 } 13850 pci_set_master(bp->pdev); 13851 if (bnxt_hwrm_ver_get(bp)) { 13852 rc = -ENODEV; 13853 goto resume_exit; 13854 } 13855 rc = bnxt_hwrm_func_reset(bp); 13856 if (rc) { 13857 rc = -EBUSY; 13858 goto resume_exit; 13859 } 13860 13861 rc = bnxt_hwrm_func_qcaps(bp); 13862 if (rc) 13863 goto resume_exit; 13864 13865 if (bnxt_hwrm_func_drv_rgtr(bp, NULL, 0, false)) { 13866 rc = -ENODEV; 13867 goto resume_exit; 13868 } 13869 13870 bnxt_get_wol_settings(bp); 13871 if (netif_running(dev)) { 13872 rc = bnxt_open(dev); 13873 if (!rc) 13874 netif_device_attach(dev); 13875 } 13876 13877 resume_exit: 13878 bnxt_ulp_start(bp, rc); 13879 if (!rc) 13880 bnxt_reenable_sriov(bp); 13881 rtnl_unlock(); 13882 return rc; 13883 } 13884 13885 static SIMPLE_DEV_PM_OPS(bnxt_pm_ops, bnxt_suspend, bnxt_resume); 13886 #define BNXT_PM_OPS (&bnxt_pm_ops) 13887 13888 #else 13889 13890 #define BNXT_PM_OPS NULL 13891 13892 #endif /* CONFIG_PM_SLEEP */ 13893 13894 /** 13895 * bnxt_io_error_detected - called when PCI error is detected 13896 * @pdev: Pointer to PCI device 13897 * @state: The current pci connection state 13898 * 13899 * This function is called after a PCI bus error affecting 13900 * this device has been detected. 13901 */ 13902 static pci_ers_result_t bnxt_io_error_detected(struct pci_dev *pdev, 13903 pci_channel_state_t state) 13904 { 13905 struct net_device *netdev = pci_get_drvdata(pdev); 13906 struct bnxt *bp = netdev_priv(netdev); 13907 13908 netdev_info(netdev, "PCI I/O error detected\n"); 13909 13910 rtnl_lock(); 13911 netif_device_detach(netdev); 13912 13913 bnxt_ulp_stop(bp); 13914 13915 if (state == pci_channel_io_perm_failure) { 13916 rtnl_unlock(); 13917 return PCI_ERS_RESULT_DISCONNECT; 13918 } 13919 13920 if (state == pci_channel_io_frozen) 13921 set_bit(BNXT_STATE_PCI_CHANNEL_IO_FROZEN, &bp->state); 13922 13923 if (netif_running(netdev)) 13924 bnxt_close(netdev); 13925 13926 if (pci_is_enabled(pdev)) 13927 pci_disable_device(pdev); 13928 bnxt_free_ctx_mem(bp); 13929 kfree(bp->ctx); 13930 bp->ctx = NULL; 13931 rtnl_unlock(); 13932 13933 /* Request a slot slot reset. */ 13934 return PCI_ERS_RESULT_NEED_RESET; 13935 } 13936 13937 /** 13938 * bnxt_io_slot_reset - called after the pci bus has been reset. 13939 * @pdev: Pointer to PCI device 13940 * 13941 * Restart the card from scratch, as if from a cold-boot. 13942 * At this point, the card has exprienced a hard reset, 13943 * followed by fixups by BIOS, and has its config space 13944 * set up identically to what it was at cold boot. 13945 */ 13946 static pci_ers_result_t bnxt_io_slot_reset(struct pci_dev *pdev) 13947 { 13948 pci_ers_result_t result = PCI_ERS_RESULT_DISCONNECT; 13949 struct net_device *netdev = pci_get_drvdata(pdev); 13950 struct bnxt *bp = netdev_priv(netdev); 13951 int retry = 0; 13952 int err = 0; 13953 int off; 13954 13955 netdev_info(bp->dev, "PCI Slot Reset\n"); 13956 13957 rtnl_lock(); 13958 13959 if (pci_enable_device(pdev)) { 13960 dev_err(&pdev->dev, 13961 "Cannot re-enable PCI device after reset.\n"); 13962 } else { 13963 pci_set_master(pdev); 13964 /* Upon fatal error, our device internal logic that latches to 13965 * BAR value is getting reset and will restore only upon 13966 * rewritting the BARs. 13967 * 13968 * As pci_restore_state() does not re-write the BARs if the 13969 * value is same as saved value earlier, driver needs to 13970 * write the BARs to 0 to force restore, in case of fatal error. 13971 */ 13972 if (test_and_clear_bit(BNXT_STATE_PCI_CHANNEL_IO_FROZEN, 13973 &bp->state)) { 13974 for (off = PCI_BASE_ADDRESS_0; 13975 off <= PCI_BASE_ADDRESS_5; off += 4) 13976 pci_write_config_dword(bp->pdev, off, 0); 13977 } 13978 pci_restore_state(pdev); 13979 pci_save_state(pdev); 13980 13981 bnxt_inv_fw_health_reg(bp); 13982 bnxt_try_map_fw_health_reg(bp); 13983 13984 /* In some PCIe AER scenarios, firmware may take up to 13985 * 10 seconds to become ready in the worst case. 13986 */ 13987 do { 13988 err = bnxt_try_recover_fw(bp); 13989 if (!err) 13990 break; 13991 retry++; 13992 } while (retry < BNXT_FW_SLOT_RESET_RETRY); 13993 13994 if (err) { 13995 dev_err(&pdev->dev, "Firmware not ready\n"); 13996 goto reset_exit; 13997 } 13998 13999 err = bnxt_hwrm_func_reset(bp); 14000 if (!err) 14001 result = PCI_ERS_RESULT_RECOVERED; 14002 14003 bnxt_ulp_irq_stop(bp); 14004 bnxt_clear_int_mode(bp); 14005 err = bnxt_init_int_mode(bp); 14006 bnxt_ulp_irq_restart(bp, err); 14007 } 14008 14009 reset_exit: 14010 bnxt_clear_reservations(bp, true); 14011 rtnl_unlock(); 14012 14013 return result; 14014 } 14015 14016 /** 14017 * bnxt_io_resume - called when traffic can start flowing again. 14018 * @pdev: Pointer to PCI device 14019 * 14020 * This callback is called when the error recovery driver tells 14021 * us that its OK to resume normal operation. 14022 */ 14023 static void bnxt_io_resume(struct pci_dev *pdev) 14024 { 14025 struct net_device *netdev = pci_get_drvdata(pdev); 14026 struct bnxt *bp = netdev_priv(netdev); 14027 int err; 14028 14029 netdev_info(bp->dev, "PCI Slot Resume\n"); 14030 rtnl_lock(); 14031 14032 err = bnxt_hwrm_func_qcaps(bp); 14033 if (!err && netif_running(netdev)) 14034 err = bnxt_open(netdev); 14035 14036 bnxt_ulp_start(bp, err); 14037 if (!err) { 14038 bnxt_reenable_sriov(bp); 14039 netif_device_attach(netdev); 14040 } 14041 14042 rtnl_unlock(); 14043 } 14044 14045 static const struct pci_error_handlers bnxt_err_handler = { 14046 .error_detected = bnxt_io_error_detected, 14047 .slot_reset = bnxt_io_slot_reset, 14048 .resume = bnxt_io_resume 14049 }; 14050 14051 static struct pci_driver bnxt_pci_driver = { 14052 .name = DRV_MODULE_NAME, 14053 .id_table = bnxt_pci_tbl, 14054 .probe = bnxt_init_one, 14055 .remove = bnxt_remove_one, 14056 .shutdown = bnxt_shutdown, 14057 .driver.pm = BNXT_PM_OPS, 14058 .err_handler = &bnxt_err_handler, 14059 #if defined(CONFIG_BNXT_SRIOV) 14060 .sriov_configure = bnxt_sriov_configure, 14061 #endif 14062 }; 14063 14064 static int __init bnxt_init(void) 14065 { 14066 int err; 14067 14068 bnxt_debug_init(); 14069 err = pci_register_driver(&bnxt_pci_driver); 14070 if (err) { 14071 bnxt_debug_exit(); 14072 return err; 14073 } 14074 14075 return 0; 14076 } 14077 14078 static void __exit bnxt_exit(void) 14079 { 14080 pci_unregister_driver(&bnxt_pci_driver); 14081 if (bnxt_pf_wq) 14082 destroy_workqueue(bnxt_pf_wq); 14083 bnxt_debug_exit(); 14084 } 14085 14086 module_init(bnxt_init); 14087 module_exit(bnxt_exit); 14088