1 /* Broadcom NetXtreme-C/E network driver. 2 * 3 * Copyright (c) 2014-2016 Broadcom Corporation 4 * Copyright (c) 2016-2019 Broadcom Limited 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation. 9 */ 10 11 #include <linux/module.h> 12 13 #include <linux/stringify.h> 14 #include <linux/kernel.h> 15 #include <linux/timer.h> 16 #include <linux/errno.h> 17 #include <linux/ioport.h> 18 #include <linux/slab.h> 19 #include <linux/vmalloc.h> 20 #include <linux/interrupt.h> 21 #include <linux/pci.h> 22 #include <linux/netdevice.h> 23 #include <linux/etherdevice.h> 24 #include <linux/skbuff.h> 25 #include <linux/dma-mapping.h> 26 #include <linux/bitops.h> 27 #include <linux/io.h> 28 #include <linux/irq.h> 29 #include <linux/delay.h> 30 #include <asm/byteorder.h> 31 #include <asm/page.h> 32 #include <linux/time.h> 33 #include <linux/mii.h> 34 #include <linux/mdio.h> 35 #include <linux/if.h> 36 #include <linux/if_vlan.h> 37 #include <linux/if_bridge.h> 38 #include <linux/rtc.h> 39 #include <linux/bpf.h> 40 #include <net/ip.h> 41 #include <net/tcp.h> 42 #include <net/udp.h> 43 #include <net/checksum.h> 44 #include <net/ip6_checksum.h> 45 #include <net/udp_tunnel.h> 46 #include <linux/workqueue.h> 47 #include <linux/prefetch.h> 48 #include <linux/cache.h> 49 #include <linux/log2.h> 50 #include <linux/aer.h> 51 #include <linux/bitmap.h> 52 #include <linux/cpu_rmap.h> 53 #include <linux/cpumask.h> 54 #include <net/pkt_cls.h> 55 #include <linux/hwmon.h> 56 #include <linux/hwmon-sysfs.h> 57 #include <net/page_pool.h> 58 59 #include "bnxt_hsi.h" 60 #include "bnxt.h" 61 #include "bnxt_ulp.h" 62 #include "bnxt_sriov.h" 63 #include "bnxt_ethtool.h" 64 #include "bnxt_dcb.h" 65 #include "bnxt_xdp.h" 66 #include "bnxt_vfr.h" 67 #include "bnxt_tc.h" 68 #include "bnxt_devlink.h" 69 #include "bnxt_debugfs.h" 70 71 #define BNXT_TX_TIMEOUT (5 * HZ) 72 73 MODULE_LICENSE("GPL"); 74 MODULE_DESCRIPTION("Broadcom BCM573xx network driver"); 75 76 #define BNXT_RX_OFFSET (NET_SKB_PAD + NET_IP_ALIGN) 77 #define BNXT_RX_DMA_OFFSET NET_SKB_PAD 78 #define BNXT_RX_COPY_THRESH 256 79 80 #define BNXT_TX_PUSH_THRESH 164 81 82 enum board_idx { 83 BCM57301, 84 BCM57302, 85 BCM57304, 86 BCM57417_NPAR, 87 BCM58700, 88 BCM57311, 89 BCM57312, 90 BCM57402, 91 BCM57404, 92 BCM57406, 93 BCM57402_NPAR, 94 BCM57407, 95 BCM57412, 96 BCM57414, 97 BCM57416, 98 BCM57417, 99 BCM57412_NPAR, 100 BCM57314, 101 BCM57417_SFP, 102 BCM57416_SFP, 103 BCM57404_NPAR, 104 BCM57406_NPAR, 105 BCM57407_SFP, 106 BCM57407_NPAR, 107 BCM57414_NPAR, 108 BCM57416_NPAR, 109 BCM57452, 110 BCM57454, 111 BCM5745x_NPAR, 112 BCM57508, 113 BCM57504, 114 BCM57502, 115 BCM57508_NPAR, 116 BCM57504_NPAR, 117 BCM57502_NPAR, 118 BCM58802, 119 BCM58804, 120 BCM58808, 121 NETXTREME_E_VF, 122 NETXTREME_C_VF, 123 NETXTREME_S_VF, 124 NETXTREME_E_P5_VF, 125 }; 126 127 /* indexed by enum above */ 128 static const struct { 129 char *name; 130 } board_info[] = { 131 [BCM57301] = { "Broadcom BCM57301 NetXtreme-C 10Gb Ethernet" }, 132 [BCM57302] = { "Broadcom BCM57302 NetXtreme-C 10Gb/25Gb Ethernet" }, 133 [BCM57304] = { "Broadcom BCM57304 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" }, 134 [BCM57417_NPAR] = { "Broadcom BCM57417 NetXtreme-E Ethernet Partition" }, 135 [BCM58700] = { "Broadcom BCM58700 Nitro 1Gb/2.5Gb/10Gb Ethernet" }, 136 [BCM57311] = { "Broadcom BCM57311 NetXtreme-C 10Gb Ethernet" }, 137 [BCM57312] = { "Broadcom BCM57312 NetXtreme-C 10Gb/25Gb Ethernet" }, 138 [BCM57402] = { "Broadcom BCM57402 NetXtreme-E 10Gb Ethernet" }, 139 [BCM57404] = { "Broadcom BCM57404 NetXtreme-E 10Gb/25Gb Ethernet" }, 140 [BCM57406] = { "Broadcom BCM57406 NetXtreme-E 10GBase-T Ethernet" }, 141 [BCM57402_NPAR] = { "Broadcom BCM57402 NetXtreme-E Ethernet Partition" }, 142 [BCM57407] = { "Broadcom BCM57407 NetXtreme-E 10GBase-T Ethernet" }, 143 [BCM57412] = { "Broadcom BCM57412 NetXtreme-E 10Gb Ethernet" }, 144 [BCM57414] = { "Broadcom BCM57414 NetXtreme-E 10Gb/25Gb Ethernet" }, 145 [BCM57416] = { "Broadcom BCM57416 NetXtreme-E 10GBase-T Ethernet" }, 146 [BCM57417] = { "Broadcom BCM57417 NetXtreme-E 10GBase-T Ethernet" }, 147 [BCM57412_NPAR] = { "Broadcom BCM57412 NetXtreme-E Ethernet Partition" }, 148 [BCM57314] = { "Broadcom BCM57314 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" }, 149 [BCM57417_SFP] = { "Broadcom BCM57417 NetXtreme-E 10Gb/25Gb Ethernet" }, 150 [BCM57416_SFP] = { "Broadcom BCM57416 NetXtreme-E 10Gb Ethernet" }, 151 [BCM57404_NPAR] = { "Broadcom BCM57404 NetXtreme-E Ethernet Partition" }, 152 [BCM57406_NPAR] = { "Broadcom BCM57406 NetXtreme-E Ethernet Partition" }, 153 [BCM57407_SFP] = { "Broadcom BCM57407 NetXtreme-E 25Gb Ethernet" }, 154 [BCM57407_NPAR] = { "Broadcom BCM57407 NetXtreme-E Ethernet Partition" }, 155 [BCM57414_NPAR] = { "Broadcom BCM57414 NetXtreme-E Ethernet Partition" }, 156 [BCM57416_NPAR] = { "Broadcom BCM57416 NetXtreme-E Ethernet Partition" }, 157 [BCM57452] = { "Broadcom BCM57452 NetXtreme-E 10Gb/25Gb/40Gb/50Gb Ethernet" }, 158 [BCM57454] = { "Broadcom BCM57454 NetXtreme-E 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" }, 159 [BCM5745x_NPAR] = { "Broadcom BCM5745x NetXtreme-E Ethernet Partition" }, 160 [BCM57508] = { "Broadcom BCM57508 NetXtreme-E 10Gb/25Gb/50Gb/100Gb/200Gb Ethernet" }, 161 [BCM57504] = { "Broadcom BCM57504 NetXtreme-E 10Gb/25Gb/50Gb/100Gb/200Gb Ethernet" }, 162 [BCM57502] = { "Broadcom BCM57502 NetXtreme-E 10Gb/25Gb/50Gb Ethernet" }, 163 [BCM57508_NPAR] = { "Broadcom BCM57508 NetXtreme-E Ethernet Partition" }, 164 [BCM57504_NPAR] = { "Broadcom BCM57504 NetXtreme-E Ethernet Partition" }, 165 [BCM57502_NPAR] = { "Broadcom BCM57502 NetXtreme-E Ethernet Partition" }, 166 [BCM58802] = { "Broadcom BCM58802 NetXtreme-S 10Gb/25Gb/40Gb/50Gb Ethernet" }, 167 [BCM58804] = { "Broadcom BCM58804 NetXtreme-S 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" }, 168 [BCM58808] = { "Broadcom BCM58808 NetXtreme-S 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" }, 169 [NETXTREME_E_VF] = { "Broadcom NetXtreme-E Ethernet Virtual Function" }, 170 [NETXTREME_C_VF] = { "Broadcom NetXtreme-C Ethernet Virtual Function" }, 171 [NETXTREME_S_VF] = { "Broadcom NetXtreme-S Ethernet Virtual Function" }, 172 [NETXTREME_E_P5_VF] = { "Broadcom BCM5750X NetXtreme-E Ethernet Virtual Function" }, 173 }; 174 175 static const struct pci_device_id bnxt_pci_tbl[] = { 176 { PCI_VDEVICE(BROADCOM, 0x1604), .driver_data = BCM5745x_NPAR }, 177 { PCI_VDEVICE(BROADCOM, 0x1605), .driver_data = BCM5745x_NPAR }, 178 { PCI_VDEVICE(BROADCOM, 0x1614), .driver_data = BCM57454 }, 179 { PCI_VDEVICE(BROADCOM, 0x16c0), .driver_data = BCM57417_NPAR }, 180 { PCI_VDEVICE(BROADCOM, 0x16c8), .driver_data = BCM57301 }, 181 { PCI_VDEVICE(BROADCOM, 0x16c9), .driver_data = BCM57302 }, 182 { PCI_VDEVICE(BROADCOM, 0x16ca), .driver_data = BCM57304 }, 183 { PCI_VDEVICE(BROADCOM, 0x16cc), .driver_data = BCM57417_NPAR }, 184 { PCI_VDEVICE(BROADCOM, 0x16cd), .driver_data = BCM58700 }, 185 { PCI_VDEVICE(BROADCOM, 0x16ce), .driver_data = BCM57311 }, 186 { PCI_VDEVICE(BROADCOM, 0x16cf), .driver_data = BCM57312 }, 187 { PCI_VDEVICE(BROADCOM, 0x16d0), .driver_data = BCM57402 }, 188 { PCI_VDEVICE(BROADCOM, 0x16d1), .driver_data = BCM57404 }, 189 { PCI_VDEVICE(BROADCOM, 0x16d2), .driver_data = BCM57406 }, 190 { PCI_VDEVICE(BROADCOM, 0x16d4), .driver_data = BCM57402_NPAR }, 191 { PCI_VDEVICE(BROADCOM, 0x16d5), .driver_data = BCM57407 }, 192 { PCI_VDEVICE(BROADCOM, 0x16d6), .driver_data = BCM57412 }, 193 { PCI_VDEVICE(BROADCOM, 0x16d7), .driver_data = BCM57414 }, 194 { PCI_VDEVICE(BROADCOM, 0x16d8), .driver_data = BCM57416 }, 195 { PCI_VDEVICE(BROADCOM, 0x16d9), .driver_data = BCM57417 }, 196 { PCI_VDEVICE(BROADCOM, 0x16de), .driver_data = BCM57412_NPAR }, 197 { PCI_VDEVICE(BROADCOM, 0x16df), .driver_data = BCM57314 }, 198 { PCI_VDEVICE(BROADCOM, 0x16e2), .driver_data = BCM57417_SFP }, 199 { PCI_VDEVICE(BROADCOM, 0x16e3), .driver_data = BCM57416_SFP }, 200 { PCI_VDEVICE(BROADCOM, 0x16e7), .driver_data = BCM57404_NPAR }, 201 { PCI_VDEVICE(BROADCOM, 0x16e8), .driver_data = BCM57406_NPAR }, 202 { PCI_VDEVICE(BROADCOM, 0x16e9), .driver_data = BCM57407_SFP }, 203 { PCI_VDEVICE(BROADCOM, 0x16ea), .driver_data = BCM57407_NPAR }, 204 { PCI_VDEVICE(BROADCOM, 0x16eb), .driver_data = BCM57412_NPAR }, 205 { PCI_VDEVICE(BROADCOM, 0x16ec), .driver_data = BCM57414_NPAR }, 206 { PCI_VDEVICE(BROADCOM, 0x16ed), .driver_data = BCM57414_NPAR }, 207 { PCI_VDEVICE(BROADCOM, 0x16ee), .driver_data = BCM57416_NPAR }, 208 { PCI_VDEVICE(BROADCOM, 0x16ef), .driver_data = BCM57416_NPAR }, 209 { PCI_VDEVICE(BROADCOM, 0x16f0), .driver_data = BCM58808 }, 210 { PCI_VDEVICE(BROADCOM, 0x16f1), .driver_data = BCM57452 }, 211 { PCI_VDEVICE(BROADCOM, 0x1750), .driver_data = BCM57508 }, 212 { PCI_VDEVICE(BROADCOM, 0x1751), .driver_data = BCM57504 }, 213 { PCI_VDEVICE(BROADCOM, 0x1752), .driver_data = BCM57502 }, 214 { PCI_VDEVICE(BROADCOM, 0x1800), .driver_data = BCM57508_NPAR }, 215 { PCI_VDEVICE(BROADCOM, 0x1801), .driver_data = BCM57504_NPAR }, 216 { PCI_VDEVICE(BROADCOM, 0x1802), .driver_data = BCM57502_NPAR }, 217 { PCI_VDEVICE(BROADCOM, 0x1803), .driver_data = BCM57508_NPAR }, 218 { PCI_VDEVICE(BROADCOM, 0x1804), .driver_data = BCM57504_NPAR }, 219 { PCI_VDEVICE(BROADCOM, 0x1805), .driver_data = BCM57502_NPAR }, 220 { PCI_VDEVICE(BROADCOM, 0xd802), .driver_data = BCM58802 }, 221 { PCI_VDEVICE(BROADCOM, 0xd804), .driver_data = BCM58804 }, 222 #ifdef CONFIG_BNXT_SRIOV 223 { PCI_VDEVICE(BROADCOM, 0x1606), .driver_data = NETXTREME_E_VF }, 224 { PCI_VDEVICE(BROADCOM, 0x1609), .driver_data = NETXTREME_E_VF }, 225 { PCI_VDEVICE(BROADCOM, 0x16c1), .driver_data = NETXTREME_E_VF }, 226 { PCI_VDEVICE(BROADCOM, 0x16cb), .driver_data = NETXTREME_C_VF }, 227 { PCI_VDEVICE(BROADCOM, 0x16d3), .driver_data = NETXTREME_E_VF }, 228 { PCI_VDEVICE(BROADCOM, 0x16dc), .driver_data = NETXTREME_E_VF }, 229 { PCI_VDEVICE(BROADCOM, 0x16e1), .driver_data = NETXTREME_C_VF }, 230 { PCI_VDEVICE(BROADCOM, 0x16e5), .driver_data = NETXTREME_C_VF }, 231 { PCI_VDEVICE(BROADCOM, 0x1806), .driver_data = NETXTREME_E_P5_VF }, 232 { PCI_VDEVICE(BROADCOM, 0x1807), .driver_data = NETXTREME_E_P5_VF }, 233 { PCI_VDEVICE(BROADCOM, 0xd800), .driver_data = NETXTREME_S_VF }, 234 #endif 235 { 0 } 236 }; 237 238 MODULE_DEVICE_TABLE(pci, bnxt_pci_tbl); 239 240 static const u16 bnxt_vf_req_snif[] = { 241 HWRM_FUNC_CFG, 242 HWRM_FUNC_VF_CFG, 243 HWRM_PORT_PHY_QCFG, 244 HWRM_CFA_L2_FILTER_ALLOC, 245 }; 246 247 static const u16 bnxt_async_events_arr[] = { 248 ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE, 249 ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE, 250 ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD, 251 ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED, 252 ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE, 253 ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE, 254 ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE, 255 ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY, 256 ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY, 257 }; 258 259 static struct workqueue_struct *bnxt_pf_wq; 260 261 static bool bnxt_vf_pciid(enum board_idx idx) 262 { 263 return (idx == NETXTREME_C_VF || idx == NETXTREME_E_VF || 264 idx == NETXTREME_S_VF || idx == NETXTREME_E_P5_VF); 265 } 266 267 #define DB_CP_REARM_FLAGS (DB_KEY_CP | DB_IDX_VALID) 268 #define DB_CP_FLAGS (DB_KEY_CP | DB_IDX_VALID | DB_IRQ_DIS) 269 #define DB_CP_IRQ_DIS_FLAGS (DB_KEY_CP | DB_IRQ_DIS) 270 271 #define BNXT_CP_DB_IRQ_DIS(db) \ 272 writel(DB_CP_IRQ_DIS_FLAGS, db) 273 274 #define BNXT_DB_CQ(db, idx) \ 275 writel(DB_CP_FLAGS | RING_CMP(idx), (db)->doorbell) 276 277 #define BNXT_DB_NQ_P5(db, idx) \ 278 writeq((db)->db_key64 | DBR_TYPE_NQ | RING_CMP(idx), (db)->doorbell) 279 280 #define BNXT_DB_CQ_ARM(db, idx) \ 281 writel(DB_CP_REARM_FLAGS | RING_CMP(idx), (db)->doorbell) 282 283 #define BNXT_DB_NQ_ARM_P5(db, idx) \ 284 writeq((db)->db_key64 | DBR_TYPE_NQ_ARM | RING_CMP(idx), (db)->doorbell) 285 286 static void bnxt_db_nq(struct bnxt *bp, struct bnxt_db_info *db, u32 idx) 287 { 288 if (bp->flags & BNXT_FLAG_CHIP_P5) 289 BNXT_DB_NQ_P5(db, idx); 290 else 291 BNXT_DB_CQ(db, idx); 292 } 293 294 static void bnxt_db_nq_arm(struct bnxt *bp, struct bnxt_db_info *db, u32 idx) 295 { 296 if (bp->flags & BNXT_FLAG_CHIP_P5) 297 BNXT_DB_NQ_ARM_P5(db, idx); 298 else 299 BNXT_DB_CQ_ARM(db, idx); 300 } 301 302 static void bnxt_db_cq(struct bnxt *bp, struct bnxt_db_info *db, u32 idx) 303 { 304 if (bp->flags & BNXT_FLAG_CHIP_P5) 305 writeq(db->db_key64 | DBR_TYPE_CQ_ARMALL | RING_CMP(idx), 306 db->doorbell); 307 else 308 BNXT_DB_CQ(db, idx); 309 } 310 311 const u16 bnxt_lhint_arr[] = { 312 TX_BD_FLAGS_LHINT_512_AND_SMALLER, 313 TX_BD_FLAGS_LHINT_512_TO_1023, 314 TX_BD_FLAGS_LHINT_1024_TO_2047, 315 TX_BD_FLAGS_LHINT_1024_TO_2047, 316 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 317 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 318 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 319 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 320 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 321 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 322 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 323 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 324 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 325 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 326 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 327 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 328 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 329 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 330 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 331 }; 332 333 static u16 bnxt_xmit_get_cfa_action(struct sk_buff *skb) 334 { 335 struct metadata_dst *md_dst = skb_metadata_dst(skb); 336 337 if (!md_dst || md_dst->type != METADATA_HW_PORT_MUX) 338 return 0; 339 340 return md_dst->u.port_info.port_id; 341 } 342 343 static netdev_tx_t bnxt_start_xmit(struct sk_buff *skb, struct net_device *dev) 344 { 345 struct bnxt *bp = netdev_priv(dev); 346 struct tx_bd *txbd; 347 struct tx_bd_ext *txbd1; 348 struct netdev_queue *txq; 349 int i; 350 dma_addr_t mapping; 351 unsigned int length, pad = 0; 352 u32 len, free_size, vlan_tag_flags, cfa_action, flags; 353 u16 prod, last_frag; 354 struct pci_dev *pdev = bp->pdev; 355 struct bnxt_tx_ring_info *txr; 356 struct bnxt_sw_tx_bd *tx_buf; 357 358 i = skb_get_queue_mapping(skb); 359 if (unlikely(i >= bp->tx_nr_rings)) { 360 dev_kfree_skb_any(skb); 361 return NETDEV_TX_OK; 362 } 363 364 txq = netdev_get_tx_queue(dev, i); 365 txr = &bp->tx_ring[bp->tx_ring_map[i]]; 366 prod = txr->tx_prod; 367 368 free_size = bnxt_tx_avail(bp, txr); 369 if (unlikely(free_size < skb_shinfo(skb)->nr_frags + 2)) { 370 netif_tx_stop_queue(txq); 371 return NETDEV_TX_BUSY; 372 } 373 374 length = skb->len; 375 len = skb_headlen(skb); 376 last_frag = skb_shinfo(skb)->nr_frags; 377 378 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)]; 379 380 txbd->tx_bd_opaque = prod; 381 382 tx_buf = &txr->tx_buf_ring[prod]; 383 tx_buf->skb = skb; 384 tx_buf->nr_frags = last_frag; 385 386 vlan_tag_flags = 0; 387 cfa_action = bnxt_xmit_get_cfa_action(skb); 388 if (skb_vlan_tag_present(skb)) { 389 vlan_tag_flags = TX_BD_CFA_META_KEY_VLAN | 390 skb_vlan_tag_get(skb); 391 /* Currently supports 8021Q, 8021AD vlan offloads 392 * QINQ1, QINQ2, QINQ3 vlan headers are deprecated 393 */ 394 if (skb->vlan_proto == htons(ETH_P_8021Q)) 395 vlan_tag_flags |= 1 << TX_BD_CFA_META_TPID_SHIFT; 396 } 397 398 if (free_size == bp->tx_ring_size && length <= bp->tx_push_thresh) { 399 struct tx_push_buffer *tx_push_buf = txr->tx_push; 400 struct tx_push_bd *tx_push = &tx_push_buf->push_bd; 401 struct tx_bd_ext *tx_push1 = &tx_push->txbd2; 402 void __iomem *db = txr->tx_db.doorbell; 403 void *pdata = tx_push_buf->data; 404 u64 *end; 405 int j, push_len; 406 407 /* Set COAL_NOW to be ready quickly for the next push */ 408 tx_push->tx_bd_len_flags_type = 409 cpu_to_le32((length << TX_BD_LEN_SHIFT) | 410 TX_BD_TYPE_LONG_TX_BD | 411 TX_BD_FLAGS_LHINT_512_AND_SMALLER | 412 TX_BD_FLAGS_COAL_NOW | 413 TX_BD_FLAGS_PACKET_END | 414 (2 << TX_BD_FLAGS_BD_CNT_SHIFT)); 415 416 if (skb->ip_summed == CHECKSUM_PARTIAL) 417 tx_push1->tx_bd_hsize_lflags = 418 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM); 419 else 420 tx_push1->tx_bd_hsize_lflags = 0; 421 422 tx_push1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags); 423 tx_push1->tx_bd_cfa_action = 424 cpu_to_le32(cfa_action << TX_BD_CFA_ACTION_SHIFT); 425 426 end = pdata + length; 427 end = PTR_ALIGN(end, 8) - 1; 428 *end = 0; 429 430 skb_copy_from_linear_data(skb, pdata, len); 431 pdata += len; 432 for (j = 0; j < last_frag; j++) { 433 skb_frag_t *frag = &skb_shinfo(skb)->frags[j]; 434 void *fptr; 435 436 fptr = skb_frag_address_safe(frag); 437 if (!fptr) 438 goto normal_tx; 439 440 memcpy(pdata, fptr, skb_frag_size(frag)); 441 pdata += skb_frag_size(frag); 442 } 443 444 txbd->tx_bd_len_flags_type = tx_push->tx_bd_len_flags_type; 445 txbd->tx_bd_haddr = txr->data_mapping; 446 prod = NEXT_TX(prod); 447 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)]; 448 memcpy(txbd, tx_push1, sizeof(*txbd)); 449 prod = NEXT_TX(prod); 450 tx_push->doorbell = 451 cpu_to_le32(DB_KEY_TX_PUSH | DB_LONG_TX_PUSH | prod); 452 txr->tx_prod = prod; 453 454 tx_buf->is_push = 1; 455 netdev_tx_sent_queue(txq, skb->len); 456 wmb(); /* Sync is_push and byte queue before pushing data */ 457 458 push_len = (length + sizeof(*tx_push) + 7) / 8; 459 if (push_len > 16) { 460 __iowrite64_copy(db, tx_push_buf, 16); 461 __iowrite32_copy(db + 4, tx_push_buf + 1, 462 (push_len - 16) << 1); 463 } else { 464 __iowrite64_copy(db, tx_push_buf, push_len); 465 } 466 467 goto tx_done; 468 } 469 470 normal_tx: 471 if (length < BNXT_MIN_PKT_SIZE) { 472 pad = BNXT_MIN_PKT_SIZE - length; 473 if (skb_pad(skb, pad)) { 474 /* SKB already freed. */ 475 tx_buf->skb = NULL; 476 return NETDEV_TX_OK; 477 } 478 length = BNXT_MIN_PKT_SIZE; 479 } 480 481 mapping = dma_map_single(&pdev->dev, skb->data, len, DMA_TO_DEVICE); 482 483 if (unlikely(dma_mapping_error(&pdev->dev, mapping))) { 484 dev_kfree_skb_any(skb); 485 tx_buf->skb = NULL; 486 return NETDEV_TX_OK; 487 } 488 489 dma_unmap_addr_set(tx_buf, mapping, mapping); 490 flags = (len << TX_BD_LEN_SHIFT) | TX_BD_TYPE_LONG_TX_BD | 491 ((last_frag + 2) << TX_BD_FLAGS_BD_CNT_SHIFT); 492 493 txbd->tx_bd_haddr = cpu_to_le64(mapping); 494 495 prod = NEXT_TX(prod); 496 txbd1 = (struct tx_bd_ext *) 497 &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)]; 498 499 txbd1->tx_bd_hsize_lflags = 0; 500 if (skb_is_gso(skb)) { 501 u32 hdr_len; 502 503 if (skb->encapsulation) 504 hdr_len = skb_inner_network_offset(skb) + 505 skb_inner_network_header_len(skb) + 506 inner_tcp_hdrlen(skb); 507 else 508 hdr_len = skb_transport_offset(skb) + 509 tcp_hdrlen(skb); 510 511 txbd1->tx_bd_hsize_lflags = cpu_to_le32(TX_BD_FLAGS_LSO | 512 TX_BD_FLAGS_T_IPID | 513 (hdr_len << (TX_BD_HSIZE_SHIFT - 1))); 514 length = skb_shinfo(skb)->gso_size; 515 txbd1->tx_bd_mss = cpu_to_le32(length); 516 length += hdr_len; 517 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 518 txbd1->tx_bd_hsize_lflags = 519 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM); 520 txbd1->tx_bd_mss = 0; 521 } 522 523 length >>= 9; 524 if (unlikely(length >= ARRAY_SIZE(bnxt_lhint_arr))) { 525 dev_warn_ratelimited(&pdev->dev, "Dropped oversize %d bytes TX packet.\n", 526 skb->len); 527 i = 0; 528 goto tx_dma_error; 529 } 530 flags |= bnxt_lhint_arr[length]; 531 txbd->tx_bd_len_flags_type = cpu_to_le32(flags); 532 533 txbd1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags); 534 txbd1->tx_bd_cfa_action = 535 cpu_to_le32(cfa_action << TX_BD_CFA_ACTION_SHIFT); 536 for (i = 0; i < last_frag; i++) { 537 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 538 539 prod = NEXT_TX(prod); 540 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)]; 541 542 len = skb_frag_size(frag); 543 mapping = skb_frag_dma_map(&pdev->dev, frag, 0, len, 544 DMA_TO_DEVICE); 545 546 if (unlikely(dma_mapping_error(&pdev->dev, mapping))) 547 goto tx_dma_error; 548 549 tx_buf = &txr->tx_buf_ring[prod]; 550 dma_unmap_addr_set(tx_buf, mapping, mapping); 551 552 txbd->tx_bd_haddr = cpu_to_le64(mapping); 553 554 flags = len << TX_BD_LEN_SHIFT; 555 txbd->tx_bd_len_flags_type = cpu_to_le32(flags); 556 } 557 558 flags &= ~TX_BD_LEN; 559 txbd->tx_bd_len_flags_type = 560 cpu_to_le32(((len + pad) << TX_BD_LEN_SHIFT) | flags | 561 TX_BD_FLAGS_PACKET_END); 562 563 netdev_tx_sent_queue(txq, skb->len); 564 565 /* Sync BD data before updating doorbell */ 566 wmb(); 567 568 prod = NEXT_TX(prod); 569 txr->tx_prod = prod; 570 571 if (!netdev_xmit_more() || netif_xmit_stopped(txq)) 572 bnxt_db_write(bp, &txr->tx_db, prod); 573 574 tx_done: 575 576 if (unlikely(bnxt_tx_avail(bp, txr) <= MAX_SKB_FRAGS + 1)) { 577 if (netdev_xmit_more() && !tx_buf->is_push) 578 bnxt_db_write(bp, &txr->tx_db, prod); 579 580 netif_tx_stop_queue(txq); 581 582 /* netif_tx_stop_queue() must be done before checking 583 * tx index in bnxt_tx_avail() below, because in 584 * bnxt_tx_int(), we update tx index before checking for 585 * netif_tx_queue_stopped(). 586 */ 587 smp_mb(); 588 if (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh) 589 netif_tx_wake_queue(txq); 590 } 591 return NETDEV_TX_OK; 592 593 tx_dma_error: 594 last_frag = i; 595 596 /* start back at beginning and unmap skb */ 597 prod = txr->tx_prod; 598 tx_buf = &txr->tx_buf_ring[prod]; 599 tx_buf->skb = NULL; 600 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping), 601 skb_headlen(skb), PCI_DMA_TODEVICE); 602 prod = NEXT_TX(prod); 603 604 /* unmap remaining mapped pages */ 605 for (i = 0; i < last_frag; i++) { 606 prod = NEXT_TX(prod); 607 tx_buf = &txr->tx_buf_ring[prod]; 608 dma_unmap_page(&pdev->dev, dma_unmap_addr(tx_buf, mapping), 609 skb_frag_size(&skb_shinfo(skb)->frags[i]), 610 PCI_DMA_TODEVICE); 611 } 612 613 dev_kfree_skb_any(skb); 614 return NETDEV_TX_OK; 615 } 616 617 static void bnxt_tx_int(struct bnxt *bp, struct bnxt_napi *bnapi, int nr_pkts) 618 { 619 struct bnxt_tx_ring_info *txr = bnapi->tx_ring; 620 struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, txr->txq_index); 621 u16 cons = txr->tx_cons; 622 struct pci_dev *pdev = bp->pdev; 623 int i; 624 unsigned int tx_bytes = 0; 625 626 for (i = 0; i < nr_pkts; i++) { 627 struct bnxt_sw_tx_bd *tx_buf; 628 struct sk_buff *skb; 629 int j, last; 630 631 tx_buf = &txr->tx_buf_ring[cons]; 632 cons = NEXT_TX(cons); 633 skb = tx_buf->skb; 634 tx_buf->skb = NULL; 635 636 if (tx_buf->is_push) { 637 tx_buf->is_push = 0; 638 goto next_tx_int; 639 } 640 641 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping), 642 skb_headlen(skb), PCI_DMA_TODEVICE); 643 last = tx_buf->nr_frags; 644 645 for (j = 0; j < last; j++) { 646 cons = NEXT_TX(cons); 647 tx_buf = &txr->tx_buf_ring[cons]; 648 dma_unmap_page( 649 &pdev->dev, 650 dma_unmap_addr(tx_buf, mapping), 651 skb_frag_size(&skb_shinfo(skb)->frags[j]), 652 PCI_DMA_TODEVICE); 653 } 654 655 next_tx_int: 656 cons = NEXT_TX(cons); 657 658 tx_bytes += skb->len; 659 dev_kfree_skb_any(skb); 660 } 661 662 netdev_tx_completed_queue(txq, nr_pkts, tx_bytes); 663 txr->tx_cons = cons; 664 665 /* Need to make the tx_cons update visible to bnxt_start_xmit() 666 * before checking for netif_tx_queue_stopped(). Without the 667 * memory barrier, there is a small possibility that bnxt_start_xmit() 668 * will miss it and cause the queue to be stopped forever. 669 */ 670 smp_mb(); 671 672 if (unlikely(netif_tx_queue_stopped(txq)) && 673 (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)) { 674 __netif_tx_lock(txq, smp_processor_id()); 675 if (netif_tx_queue_stopped(txq) && 676 bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh && 677 txr->dev_state != BNXT_DEV_STATE_CLOSING) 678 netif_tx_wake_queue(txq); 679 __netif_tx_unlock(txq); 680 } 681 } 682 683 static struct page *__bnxt_alloc_rx_page(struct bnxt *bp, dma_addr_t *mapping, 684 struct bnxt_rx_ring_info *rxr, 685 gfp_t gfp) 686 { 687 struct device *dev = &bp->pdev->dev; 688 struct page *page; 689 690 page = page_pool_dev_alloc_pages(rxr->page_pool); 691 if (!page) 692 return NULL; 693 694 *mapping = dma_map_page_attrs(dev, page, 0, PAGE_SIZE, bp->rx_dir, 695 DMA_ATTR_WEAK_ORDERING); 696 if (dma_mapping_error(dev, *mapping)) { 697 page_pool_recycle_direct(rxr->page_pool, page); 698 return NULL; 699 } 700 *mapping += bp->rx_dma_offset; 701 return page; 702 } 703 704 static inline u8 *__bnxt_alloc_rx_data(struct bnxt *bp, dma_addr_t *mapping, 705 gfp_t gfp) 706 { 707 u8 *data; 708 struct pci_dev *pdev = bp->pdev; 709 710 data = kmalloc(bp->rx_buf_size, gfp); 711 if (!data) 712 return NULL; 713 714 *mapping = dma_map_single_attrs(&pdev->dev, data + bp->rx_dma_offset, 715 bp->rx_buf_use_size, bp->rx_dir, 716 DMA_ATTR_WEAK_ORDERING); 717 718 if (dma_mapping_error(&pdev->dev, *mapping)) { 719 kfree(data); 720 data = NULL; 721 } 722 return data; 723 } 724 725 int bnxt_alloc_rx_data(struct bnxt *bp, struct bnxt_rx_ring_info *rxr, 726 u16 prod, gfp_t gfp) 727 { 728 struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)]; 729 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[prod]; 730 dma_addr_t mapping; 731 732 if (BNXT_RX_PAGE_MODE(bp)) { 733 struct page *page = 734 __bnxt_alloc_rx_page(bp, &mapping, rxr, gfp); 735 736 if (!page) 737 return -ENOMEM; 738 739 rx_buf->data = page; 740 rx_buf->data_ptr = page_address(page) + bp->rx_offset; 741 } else { 742 u8 *data = __bnxt_alloc_rx_data(bp, &mapping, gfp); 743 744 if (!data) 745 return -ENOMEM; 746 747 rx_buf->data = data; 748 rx_buf->data_ptr = data + bp->rx_offset; 749 } 750 rx_buf->mapping = mapping; 751 752 rxbd->rx_bd_haddr = cpu_to_le64(mapping); 753 return 0; 754 } 755 756 void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons, void *data) 757 { 758 u16 prod = rxr->rx_prod; 759 struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf; 760 struct rx_bd *cons_bd, *prod_bd; 761 762 prod_rx_buf = &rxr->rx_buf_ring[prod]; 763 cons_rx_buf = &rxr->rx_buf_ring[cons]; 764 765 prod_rx_buf->data = data; 766 prod_rx_buf->data_ptr = cons_rx_buf->data_ptr; 767 768 prod_rx_buf->mapping = cons_rx_buf->mapping; 769 770 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)]; 771 cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)]; 772 773 prod_bd->rx_bd_haddr = cons_bd->rx_bd_haddr; 774 } 775 776 static inline u16 bnxt_find_next_agg_idx(struct bnxt_rx_ring_info *rxr, u16 idx) 777 { 778 u16 next, max = rxr->rx_agg_bmap_size; 779 780 next = find_next_zero_bit(rxr->rx_agg_bmap, max, idx); 781 if (next >= max) 782 next = find_first_zero_bit(rxr->rx_agg_bmap, max); 783 return next; 784 } 785 786 static inline int bnxt_alloc_rx_page(struct bnxt *bp, 787 struct bnxt_rx_ring_info *rxr, 788 u16 prod, gfp_t gfp) 789 { 790 struct rx_bd *rxbd = 791 &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)]; 792 struct bnxt_sw_rx_agg_bd *rx_agg_buf; 793 struct pci_dev *pdev = bp->pdev; 794 struct page *page; 795 dma_addr_t mapping; 796 u16 sw_prod = rxr->rx_sw_agg_prod; 797 unsigned int offset = 0; 798 799 if (PAGE_SIZE > BNXT_RX_PAGE_SIZE) { 800 page = rxr->rx_page; 801 if (!page) { 802 page = alloc_page(gfp); 803 if (!page) 804 return -ENOMEM; 805 rxr->rx_page = page; 806 rxr->rx_page_offset = 0; 807 } 808 offset = rxr->rx_page_offset; 809 rxr->rx_page_offset += BNXT_RX_PAGE_SIZE; 810 if (rxr->rx_page_offset == PAGE_SIZE) 811 rxr->rx_page = NULL; 812 else 813 get_page(page); 814 } else { 815 page = alloc_page(gfp); 816 if (!page) 817 return -ENOMEM; 818 } 819 820 mapping = dma_map_page_attrs(&pdev->dev, page, offset, 821 BNXT_RX_PAGE_SIZE, PCI_DMA_FROMDEVICE, 822 DMA_ATTR_WEAK_ORDERING); 823 if (dma_mapping_error(&pdev->dev, mapping)) { 824 __free_page(page); 825 return -EIO; 826 } 827 828 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap))) 829 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod); 830 831 __set_bit(sw_prod, rxr->rx_agg_bmap); 832 rx_agg_buf = &rxr->rx_agg_ring[sw_prod]; 833 rxr->rx_sw_agg_prod = NEXT_RX_AGG(sw_prod); 834 835 rx_agg_buf->page = page; 836 rx_agg_buf->offset = offset; 837 rx_agg_buf->mapping = mapping; 838 rxbd->rx_bd_haddr = cpu_to_le64(mapping); 839 rxbd->rx_bd_opaque = sw_prod; 840 return 0; 841 } 842 843 static struct rx_agg_cmp *bnxt_get_agg(struct bnxt *bp, 844 struct bnxt_cp_ring_info *cpr, 845 u16 cp_cons, u16 curr) 846 { 847 struct rx_agg_cmp *agg; 848 849 cp_cons = RING_CMP(ADV_RAW_CMP(cp_cons, curr)); 850 agg = (struct rx_agg_cmp *) 851 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 852 return agg; 853 } 854 855 static struct rx_agg_cmp *bnxt_get_tpa_agg_p5(struct bnxt *bp, 856 struct bnxt_rx_ring_info *rxr, 857 u16 agg_id, u16 curr) 858 { 859 struct bnxt_tpa_info *tpa_info = &rxr->rx_tpa[agg_id]; 860 861 return &tpa_info->agg_arr[curr]; 862 } 863 864 static void bnxt_reuse_rx_agg_bufs(struct bnxt_cp_ring_info *cpr, u16 idx, 865 u16 start, u32 agg_bufs, bool tpa) 866 { 867 struct bnxt_napi *bnapi = cpr->bnapi; 868 struct bnxt *bp = bnapi->bp; 869 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 870 u16 prod = rxr->rx_agg_prod; 871 u16 sw_prod = rxr->rx_sw_agg_prod; 872 bool p5_tpa = false; 873 u32 i; 874 875 if ((bp->flags & BNXT_FLAG_CHIP_P5) && tpa) 876 p5_tpa = true; 877 878 for (i = 0; i < agg_bufs; i++) { 879 u16 cons; 880 struct rx_agg_cmp *agg; 881 struct bnxt_sw_rx_agg_bd *cons_rx_buf, *prod_rx_buf; 882 struct rx_bd *prod_bd; 883 struct page *page; 884 885 if (p5_tpa) 886 agg = bnxt_get_tpa_agg_p5(bp, rxr, idx, start + i); 887 else 888 agg = bnxt_get_agg(bp, cpr, idx, start + i); 889 cons = agg->rx_agg_cmp_opaque; 890 __clear_bit(cons, rxr->rx_agg_bmap); 891 892 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap))) 893 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod); 894 895 __set_bit(sw_prod, rxr->rx_agg_bmap); 896 prod_rx_buf = &rxr->rx_agg_ring[sw_prod]; 897 cons_rx_buf = &rxr->rx_agg_ring[cons]; 898 899 /* It is possible for sw_prod to be equal to cons, so 900 * set cons_rx_buf->page to NULL first. 901 */ 902 page = cons_rx_buf->page; 903 cons_rx_buf->page = NULL; 904 prod_rx_buf->page = page; 905 prod_rx_buf->offset = cons_rx_buf->offset; 906 907 prod_rx_buf->mapping = cons_rx_buf->mapping; 908 909 prod_bd = &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)]; 910 911 prod_bd->rx_bd_haddr = cpu_to_le64(cons_rx_buf->mapping); 912 prod_bd->rx_bd_opaque = sw_prod; 913 914 prod = NEXT_RX_AGG(prod); 915 sw_prod = NEXT_RX_AGG(sw_prod); 916 } 917 rxr->rx_agg_prod = prod; 918 rxr->rx_sw_agg_prod = sw_prod; 919 } 920 921 static struct sk_buff *bnxt_rx_page_skb(struct bnxt *bp, 922 struct bnxt_rx_ring_info *rxr, 923 u16 cons, void *data, u8 *data_ptr, 924 dma_addr_t dma_addr, 925 unsigned int offset_and_len) 926 { 927 unsigned int payload = offset_and_len >> 16; 928 unsigned int len = offset_and_len & 0xffff; 929 skb_frag_t *frag; 930 struct page *page = data; 931 u16 prod = rxr->rx_prod; 932 struct sk_buff *skb; 933 int off, err; 934 935 err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC); 936 if (unlikely(err)) { 937 bnxt_reuse_rx_data(rxr, cons, data); 938 return NULL; 939 } 940 dma_addr -= bp->rx_dma_offset; 941 dma_unmap_page_attrs(&bp->pdev->dev, dma_addr, PAGE_SIZE, bp->rx_dir, 942 DMA_ATTR_WEAK_ORDERING); 943 page_pool_release_page(rxr->page_pool, page); 944 945 if (unlikely(!payload)) 946 payload = eth_get_headlen(bp->dev, data_ptr, len); 947 948 skb = napi_alloc_skb(&rxr->bnapi->napi, payload); 949 if (!skb) { 950 __free_page(page); 951 return NULL; 952 } 953 954 off = (void *)data_ptr - page_address(page); 955 skb_add_rx_frag(skb, 0, page, off, len, PAGE_SIZE); 956 memcpy(skb->data - NET_IP_ALIGN, data_ptr - NET_IP_ALIGN, 957 payload + NET_IP_ALIGN); 958 959 frag = &skb_shinfo(skb)->frags[0]; 960 skb_frag_size_sub(frag, payload); 961 skb_frag_off_add(frag, payload); 962 skb->data_len -= payload; 963 skb->tail += payload; 964 965 return skb; 966 } 967 968 static struct sk_buff *bnxt_rx_skb(struct bnxt *bp, 969 struct bnxt_rx_ring_info *rxr, u16 cons, 970 void *data, u8 *data_ptr, 971 dma_addr_t dma_addr, 972 unsigned int offset_and_len) 973 { 974 u16 prod = rxr->rx_prod; 975 struct sk_buff *skb; 976 int err; 977 978 err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC); 979 if (unlikely(err)) { 980 bnxt_reuse_rx_data(rxr, cons, data); 981 return NULL; 982 } 983 984 skb = build_skb(data, 0); 985 dma_unmap_single_attrs(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size, 986 bp->rx_dir, DMA_ATTR_WEAK_ORDERING); 987 if (!skb) { 988 kfree(data); 989 return NULL; 990 } 991 992 skb_reserve(skb, bp->rx_offset); 993 skb_put(skb, offset_and_len & 0xffff); 994 return skb; 995 } 996 997 static struct sk_buff *bnxt_rx_pages(struct bnxt *bp, 998 struct bnxt_cp_ring_info *cpr, 999 struct sk_buff *skb, u16 idx, 1000 u32 agg_bufs, bool tpa) 1001 { 1002 struct bnxt_napi *bnapi = cpr->bnapi; 1003 struct pci_dev *pdev = bp->pdev; 1004 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 1005 u16 prod = rxr->rx_agg_prod; 1006 bool p5_tpa = false; 1007 u32 i; 1008 1009 if ((bp->flags & BNXT_FLAG_CHIP_P5) && tpa) 1010 p5_tpa = true; 1011 1012 for (i = 0; i < agg_bufs; i++) { 1013 u16 cons, frag_len; 1014 struct rx_agg_cmp *agg; 1015 struct bnxt_sw_rx_agg_bd *cons_rx_buf; 1016 struct page *page; 1017 dma_addr_t mapping; 1018 1019 if (p5_tpa) 1020 agg = bnxt_get_tpa_agg_p5(bp, rxr, idx, i); 1021 else 1022 agg = bnxt_get_agg(bp, cpr, idx, i); 1023 cons = agg->rx_agg_cmp_opaque; 1024 frag_len = (le32_to_cpu(agg->rx_agg_cmp_len_flags_type) & 1025 RX_AGG_CMP_LEN) >> RX_AGG_CMP_LEN_SHIFT; 1026 1027 cons_rx_buf = &rxr->rx_agg_ring[cons]; 1028 skb_fill_page_desc(skb, i, cons_rx_buf->page, 1029 cons_rx_buf->offset, frag_len); 1030 __clear_bit(cons, rxr->rx_agg_bmap); 1031 1032 /* It is possible for bnxt_alloc_rx_page() to allocate 1033 * a sw_prod index that equals the cons index, so we 1034 * need to clear the cons entry now. 1035 */ 1036 mapping = cons_rx_buf->mapping; 1037 page = cons_rx_buf->page; 1038 cons_rx_buf->page = NULL; 1039 1040 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_ATOMIC) != 0) { 1041 struct skb_shared_info *shinfo; 1042 unsigned int nr_frags; 1043 1044 shinfo = skb_shinfo(skb); 1045 nr_frags = --shinfo->nr_frags; 1046 __skb_frag_set_page(&shinfo->frags[nr_frags], NULL); 1047 1048 dev_kfree_skb(skb); 1049 1050 cons_rx_buf->page = page; 1051 1052 /* Update prod since possibly some pages have been 1053 * allocated already. 1054 */ 1055 rxr->rx_agg_prod = prod; 1056 bnxt_reuse_rx_agg_bufs(cpr, idx, i, agg_bufs - i, tpa); 1057 return NULL; 1058 } 1059 1060 dma_unmap_page_attrs(&pdev->dev, mapping, BNXT_RX_PAGE_SIZE, 1061 PCI_DMA_FROMDEVICE, 1062 DMA_ATTR_WEAK_ORDERING); 1063 1064 skb->data_len += frag_len; 1065 skb->len += frag_len; 1066 skb->truesize += PAGE_SIZE; 1067 1068 prod = NEXT_RX_AGG(prod); 1069 } 1070 rxr->rx_agg_prod = prod; 1071 return skb; 1072 } 1073 1074 static int bnxt_agg_bufs_valid(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, 1075 u8 agg_bufs, u32 *raw_cons) 1076 { 1077 u16 last; 1078 struct rx_agg_cmp *agg; 1079 1080 *raw_cons = ADV_RAW_CMP(*raw_cons, agg_bufs); 1081 last = RING_CMP(*raw_cons); 1082 agg = (struct rx_agg_cmp *) 1083 &cpr->cp_desc_ring[CP_RING(last)][CP_IDX(last)]; 1084 return RX_AGG_CMP_VALID(agg, *raw_cons); 1085 } 1086 1087 static inline struct sk_buff *bnxt_copy_skb(struct bnxt_napi *bnapi, u8 *data, 1088 unsigned int len, 1089 dma_addr_t mapping) 1090 { 1091 struct bnxt *bp = bnapi->bp; 1092 struct pci_dev *pdev = bp->pdev; 1093 struct sk_buff *skb; 1094 1095 skb = napi_alloc_skb(&bnapi->napi, len); 1096 if (!skb) 1097 return NULL; 1098 1099 dma_sync_single_for_cpu(&pdev->dev, mapping, bp->rx_copy_thresh, 1100 bp->rx_dir); 1101 1102 memcpy(skb->data - NET_IP_ALIGN, data - NET_IP_ALIGN, 1103 len + NET_IP_ALIGN); 1104 1105 dma_sync_single_for_device(&pdev->dev, mapping, bp->rx_copy_thresh, 1106 bp->rx_dir); 1107 1108 skb_put(skb, len); 1109 return skb; 1110 } 1111 1112 static int bnxt_discard_rx(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, 1113 u32 *raw_cons, void *cmp) 1114 { 1115 struct rx_cmp *rxcmp = cmp; 1116 u32 tmp_raw_cons = *raw_cons; 1117 u8 cmp_type, agg_bufs = 0; 1118 1119 cmp_type = RX_CMP_TYPE(rxcmp); 1120 1121 if (cmp_type == CMP_TYPE_RX_L2_CMP) { 1122 agg_bufs = (le32_to_cpu(rxcmp->rx_cmp_misc_v1) & 1123 RX_CMP_AGG_BUFS) >> 1124 RX_CMP_AGG_BUFS_SHIFT; 1125 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) { 1126 struct rx_tpa_end_cmp *tpa_end = cmp; 1127 1128 if (bp->flags & BNXT_FLAG_CHIP_P5) 1129 return 0; 1130 1131 agg_bufs = TPA_END_AGG_BUFS(tpa_end); 1132 } 1133 1134 if (agg_bufs) { 1135 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons)) 1136 return -EBUSY; 1137 } 1138 *raw_cons = tmp_raw_cons; 1139 return 0; 1140 } 1141 1142 static void bnxt_queue_fw_reset_work(struct bnxt *bp, unsigned long delay) 1143 { 1144 if (BNXT_PF(bp)) 1145 queue_delayed_work(bnxt_pf_wq, &bp->fw_reset_task, delay); 1146 else 1147 schedule_delayed_work(&bp->fw_reset_task, delay); 1148 } 1149 1150 static void bnxt_queue_sp_work(struct bnxt *bp) 1151 { 1152 if (BNXT_PF(bp)) 1153 queue_work(bnxt_pf_wq, &bp->sp_task); 1154 else 1155 schedule_work(&bp->sp_task); 1156 } 1157 1158 static void bnxt_cancel_sp_work(struct bnxt *bp) 1159 { 1160 if (BNXT_PF(bp)) 1161 flush_workqueue(bnxt_pf_wq); 1162 else 1163 cancel_work_sync(&bp->sp_task); 1164 } 1165 1166 static void bnxt_sched_reset(struct bnxt *bp, struct bnxt_rx_ring_info *rxr) 1167 { 1168 if (!rxr->bnapi->in_reset) { 1169 rxr->bnapi->in_reset = true; 1170 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event); 1171 bnxt_queue_sp_work(bp); 1172 } 1173 rxr->rx_next_cons = 0xffff; 1174 } 1175 1176 static u16 bnxt_alloc_agg_idx(struct bnxt_rx_ring_info *rxr, u16 agg_id) 1177 { 1178 struct bnxt_tpa_idx_map *map = rxr->rx_tpa_idx_map; 1179 u16 idx = agg_id & MAX_TPA_P5_MASK; 1180 1181 if (test_bit(idx, map->agg_idx_bmap)) 1182 idx = find_first_zero_bit(map->agg_idx_bmap, 1183 BNXT_AGG_IDX_BMAP_SIZE); 1184 __set_bit(idx, map->agg_idx_bmap); 1185 map->agg_id_tbl[agg_id] = idx; 1186 return idx; 1187 } 1188 1189 static void bnxt_free_agg_idx(struct bnxt_rx_ring_info *rxr, u16 idx) 1190 { 1191 struct bnxt_tpa_idx_map *map = rxr->rx_tpa_idx_map; 1192 1193 __clear_bit(idx, map->agg_idx_bmap); 1194 } 1195 1196 static u16 bnxt_lookup_agg_idx(struct bnxt_rx_ring_info *rxr, u16 agg_id) 1197 { 1198 struct bnxt_tpa_idx_map *map = rxr->rx_tpa_idx_map; 1199 1200 return map->agg_id_tbl[agg_id]; 1201 } 1202 1203 static void bnxt_tpa_start(struct bnxt *bp, struct bnxt_rx_ring_info *rxr, 1204 struct rx_tpa_start_cmp *tpa_start, 1205 struct rx_tpa_start_cmp_ext *tpa_start1) 1206 { 1207 struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf; 1208 struct bnxt_tpa_info *tpa_info; 1209 u16 cons, prod, agg_id; 1210 struct rx_bd *prod_bd; 1211 dma_addr_t mapping; 1212 1213 if (bp->flags & BNXT_FLAG_CHIP_P5) { 1214 agg_id = TPA_START_AGG_ID_P5(tpa_start); 1215 agg_id = bnxt_alloc_agg_idx(rxr, agg_id); 1216 } else { 1217 agg_id = TPA_START_AGG_ID(tpa_start); 1218 } 1219 cons = tpa_start->rx_tpa_start_cmp_opaque; 1220 prod = rxr->rx_prod; 1221 cons_rx_buf = &rxr->rx_buf_ring[cons]; 1222 prod_rx_buf = &rxr->rx_buf_ring[prod]; 1223 tpa_info = &rxr->rx_tpa[agg_id]; 1224 1225 if (unlikely(cons != rxr->rx_next_cons || 1226 TPA_START_ERROR(tpa_start))) { 1227 netdev_warn(bp->dev, "TPA cons %x, expected cons %x, error code %x\n", 1228 cons, rxr->rx_next_cons, 1229 TPA_START_ERROR_CODE(tpa_start1)); 1230 bnxt_sched_reset(bp, rxr); 1231 return; 1232 } 1233 /* Store cfa_code in tpa_info to use in tpa_end 1234 * completion processing. 1235 */ 1236 tpa_info->cfa_code = TPA_START_CFA_CODE(tpa_start1); 1237 prod_rx_buf->data = tpa_info->data; 1238 prod_rx_buf->data_ptr = tpa_info->data_ptr; 1239 1240 mapping = tpa_info->mapping; 1241 prod_rx_buf->mapping = mapping; 1242 1243 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)]; 1244 1245 prod_bd->rx_bd_haddr = cpu_to_le64(mapping); 1246 1247 tpa_info->data = cons_rx_buf->data; 1248 tpa_info->data_ptr = cons_rx_buf->data_ptr; 1249 cons_rx_buf->data = NULL; 1250 tpa_info->mapping = cons_rx_buf->mapping; 1251 1252 tpa_info->len = 1253 le32_to_cpu(tpa_start->rx_tpa_start_cmp_len_flags_type) >> 1254 RX_TPA_START_CMP_LEN_SHIFT; 1255 if (likely(TPA_START_HASH_VALID(tpa_start))) { 1256 u32 hash_type = TPA_START_HASH_TYPE(tpa_start); 1257 1258 tpa_info->hash_type = PKT_HASH_TYPE_L4; 1259 tpa_info->gso_type = SKB_GSO_TCPV4; 1260 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */ 1261 if (hash_type == 3 || TPA_START_IS_IPV6(tpa_start1)) 1262 tpa_info->gso_type = SKB_GSO_TCPV6; 1263 tpa_info->rss_hash = 1264 le32_to_cpu(tpa_start->rx_tpa_start_cmp_rss_hash); 1265 } else { 1266 tpa_info->hash_type = PKT_HASH_TYPE_NONE; 1267 tpa_info->gso_type = 0; 1268 if (netif_msg_rx_err(bp)) 1269 netdev_warn(bp->dev, "TPA packet without valid hash\n"); 1270 } 1271 tpa_info->flags2 = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_flags2); 1272 tpa_info->metadata = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_metadata); 1273 tpa_info->hdr_info = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_hdr_info); 1274 tpa_info->agg_count = 0; 1275 1276 rxr->rx_prod = NEXT_RX(prod); 1277 cons = NEXT_RX(cons); 1278 rxr->rx_next_cons = NEXT_RX(cons); 1279 cons_rx_buf = &rxr->rx_buf_ring[cons]; 1280 1281 bnxt_reuse_rx_data(rxr, cons, cons_rx_buf->data); 1282 rxr->rx_prod = NEXT_RX(rxr->rx_prod); 1283 cons_rx_buf->data = NULL; 1284 } 1285 1286 static void bnxt_abort_tpa(struct bnxt_cp_ring_info *cpr, u16 idx, u32 agg_bufs) 1287 { 1288 if (agg_bufs) 1289 bnxt_reuse_rx_agg_bufs(cpr, idx, 0, agg_bufs, true); 1290 } 1291 1292 #ifdef CONFIG_INET 1293 static void bnxt_gro_tunnel(struct sk_buff *skb, __be16 ip_proto) 1294 { 1295 struct udphdr *uh = NULL; 1296 1297 if (ip_proto == htons(ETH_P_IP)) { 1298 struct iphdr *iph = (struct iphdr *)skb->data; 1299 1300 if (iph->protocol == IPPROTO_UDP) 1301 uh = (struct udphdr *)(iph + 1); 1302 } else { 1303 struct ipv6hdr *iph = (struct ipv6hdr *)skb->data; 1304 1305 if (iph->nexthdr == IPPROTO_UDP) 1306 uh = (struct udphdr *)(iph + 1); 1307 } 1308 if (uh) { 1309 if (uh->check) 1310 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL_CSUM; 1311 else 1312 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL; 1313 } 1314 } 1315 #endif 1316 1317 static struct sk_buff *bnxt_gro_func_5731x(struct bnxt_tpa_info *tpa_info, 1318 int payload_off, int tcp_ts, 1319 struct sk_buff *skb) 1320 { 1321 #ifdef CONFIG_INET 1322 struct tcphdr *th; 1323 int len, nw_off; 1324 u16 outer_ip_off, inner_ip_off, inner_mac_off; 1325 u32 hdr_info = tpa_info->hdr_info; 1326 bool loopback = false; 1327 1328 inner_ip_off = BNXT_TPA_INNER_L3_OFF(hdr_info); 1329 inner_mac_off = BNXT_TPA_INNER_L2_OFF(hdr_info); 1330 outer_ip_off = BNXT_TPA_OUTER_L3_OFF(hdr_info); 1331 1332 /* If the packet is an internal loopback packet, the offsets will 1333 * have an extra 4 bytes. 1334 */ 1335 if (inner_mac_off == 4) { 1336 loopback = true; 1337 } else if (inner_mac_off > 4) { 1338 __be16 proto = *((__be16 *)(skb->data + inner_ip_off - 1339 ETH_HLEN - 2)); 1340 1341 /* We only support inner iPv4/ipv6. If we don't see the 1342 * correct protocol ID, it must be a loopback packet where 1343 * the offsets are off by 4. 1344 */ 1345 if (proto != htons(ETH_P_IP) && proto != htons(ETH_P_IPV6)) 1346 loopback = true; 1347 } 1348 if (loopback) { 1349 /* internal loopback packet, subtract all offsets by 4 */ 1350 inner_ip_off -= 4; 1351 inner_mac_off -= 4; 1352 outer_ip_off -= 4; 1353 } 1354 1355 nw_off = inner_ip_off - ETH_HLEN; 1356 skb_set_network_header(skb, nw_off); 1357 if (tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_IP_TYPE) { 1358 struct ipv6hdr *iph = ipv6_hdr(skb); 1359 1360 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr)); 1361 len = skb->len - skb_transport_offset(skb); 1362 th = tcp_hdr(skb); 1363 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0); 1364 } else { 1365 struct iphdr *iph = ip_hdr(skb); 1366 1367 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr)); 1368 len = skb->len - skb_transport_offset(skb); 1369 th = tcp_hdr(skb); 1370 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0); 1371 } 1372 1373 if (inner_mac_off) { /* tunnel */ 1374 __be16 proto = *((__be16 *)(skb->data + outer_ip_off - 1375 ETH_HLEN - 2)); 1376 1377 bnxt_gro_tunnel(skb, proto); 1378 } 1379 #endif 1380 return skb; 1381 } 1382 1383 static struct sk_buff *bnxt_gro_func_5750x(struct bnxt_tpa_info *tpa_info, 1384 int payload_off, int tcp_ts, 1385 struct sk_buff *skb) 1386 { 1387 #ifdef CONFIG_INET 1388 u16 outer_ip_off, inner_ip_off, inner_mac_off; 1389 u32 hdr_info = tpa_info->hdr_info; 1390 int iphdr_len, nw_off; 1391 1392 inner_ip_off = BNXT_TPA_INNER_L3_OFF(hdr_info); 1393 inner_mac_off = BNXT_TPA_INNER_L2_OFF(hdr_info); 1394 outer_ip_off = BNXT_TPA_OUTER_L3_OFF(hdr_info); 1395 1396 nw_off = inner_ip_off - ETH_HLEN; 1397 skb_set_network_header(skb, nw_off); 1398 iphdr_len = (tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_IP_TYPE) ? 1399 sizeof(struct ipv6hdr) : sizeof(struct iphdr); 1400 skb_set_transport_header(skb, nw_off + iphdr_len); 1401 1402 if (inner_mac_off) { /* tunnel */ 1403 __be16 proto = *((__be16 *)(skb->data + outer_ip_off - 1404 ETH_HLEN - 2)); 1405 1406 bnxt_gro_tunnel(skb, proto); 1407 } 1408 #endif 1409 return skb; 1410 } 1411 1412 #define BNXT_IPV4_HDR_SIZE (sizeof(struct iphdr) + sizeof(struct tcphdr)) 1413 #define BNXT_IPV6_HDR_SIZE (sizeof(struct ipv6hdr) + sizeof(struct tcphdr)) 1414 1415 static struct sk_buff *bnxt_gro_func_5730x(struct bnxt_tpa_info *tpa_info, 1416 int payload_off, int tcp_ts, 1417 struct sk_buff *skb) 1418 { 1419 #ifdef CONFIG_INET 1420 struct tcphdr *th; 1421 int len, nw_off, tcp_opt_len = 0; 1422 1423 if (tcp_ts) 1424 tcp_opt_len = 12; 1425 1426 if (tpa_info->gso_type == SKB_GSO_TCPV4) { 1427 struct iphdr *iph; 1428 1429 nw_off = payload_off - BNXT_IPV4_HDR_SIZE - tcp_opt_len - 1430 ETH_HLEN; 1431 skb_set_network_header(skb, nw_off); 1432 iph = ip_hdr(skb); 1433 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr)); 1434 len = skb->len - skb_transport_offset(skb); 1435 th = tcp_hdr(skb); 1436 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0); 1437 } else if (tpa_info->gso_type == SKB_GSO_TCPV6) { 1438 struct ipv6hdr *iph; 1439 1440 nw_off = payload_off - BNXT_IPV6_HDR_SIZE - tcp_opt_len - 1441 ETH_HLEN; 1442 skb_set_network_header(skb, nw_off); 1443 iph = ipv6_hdr(skb); 1444 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr)); 1445 len = skb->len - skb_transport_offset(skb); 1446 th = tcp_hdr(skb); 1447 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0); 1448 } else { 1449 dev_kfree_skb_any(skb); 1450 return NULL; 1451 } 1452 1453 if (nw_off) /* tunnel */ 1454 bnxt_gro_tunnel(skb, skb->protocol); 1455 #endif 1456 return skb; 1457 } 1458 1459 static inline struct sk_buff *bnxt_gro_skb(struct bnxt *bp, 1460 struct bnxt_tpa_info *tpa_info, 1461 struct rx_tpa_end_cmp *tpa_end, 1462 struct rx_tpa_end_cmp_ext *tpa_end1, 1463 struct sk_buff *skb) 1464 { 1465 #ifdef CONFIG_INET 1466 int payload_off; 1467 u16 segs; 1468 1469 segs = TPA_END_TPA_SEGS(tpa_end); 1470 if (segs == 1) 1471 return skb; 1472 1473 NAPI_GRO_CB(skb)->count = segs; 1474 skb_shinfo(skb)->gso_size = 1475 le32_to_cpu(tpa_end1->rx_tpa_end_cmp_seg_len); 1476 skb_shinfo(skb)->gso_type = tpa_info->gso_type; 1477 if (bp->flags & BNXT_FLAG_CHIP_P5) 1478 payload_off = TPA_END_PAYLOAD_OFF_P5(tpa_end1); 1479 else 1480 payload_off = TPA_END_PAYLOAD_OFF(tpa_end); 1481 skb = bp->gro_func(tpa_info, payload_off, TPA_END_GRO_TS(tpa_end), skb); 1482 if (likely(skb)) 1483 tcp_gro_complete(skb); 1484 #endif 1485 return skb; 1486 } 1487 1488 /* Given the cfa_code of a received packet determine which 1489 * netdev (vf-rep or PF) the packet is destined to. 1490 */ 1491 static struct net_device *bnxt_get_pkt_dev(struct bnxt *bp, u16 cfa_code) 1492 { 1493 struct net_device *dev = bnxt_get_vf_rep(bp, cfa_code); 1494 1495 /* if vf-rep dev is NULL, the must belongs to the PF */ 1496 return dev ? dev : bp->dev; 1497 } 1498 1499 static inline struct sk_buff *bnxt_tpa_end(struct bnxt *bp, 1500 struct bnxt_cp_ring_info *cpr, 1501 u32 *raw_cons, 1502 struct rx_tpa_end_cmp *tpa_end, 1503 struct rx_tpa_end_cmp_ext *tpa_end1, 1504 u8 *event) 1505 { 1506 struct bnxt_napi *bnapi = cpr->bnapi; 1507 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 1508 u8 *data_ptr, agg_bufs; 1509 unsigned int len; 1510 struct bnxt_tpa_info *tpa_info; 1511 dma_addr_t mapping; 1512 struct sk_buff *skb; 1513 u16 idx = 0, agg_id; 1514 void *data; 1515 bool gro; 1516 1517 if (unlikely(bnapi->in_reset)) { 1518 int rc = bnxt_discard_rx(bp, cpr, raw_cons, tpa_end); 1519 1520 if (rc < 0) 1521 return ERR_PTR(-EBUSY); 1522 return NULL; 1523 } 1524 1525 if (bp->flags & BNXT_FLAG_CHIP_P5) { 1526 agg_id = TPA_END_AGG_ID_P5(tpa_end); 1527 agg_id = bnxt_lookup_agg_idx(rxr, agg_id); 1528 agg_bufs = TPA_END_AGG_BUFS_P5(tpa_end1); 1529 tpa_info = &rxr->rx_tpa[agg_id]; 1530 if (unlikely(agg_bufs != tpa_info->agg_count)) { 1531 netdev_warn(bp->dev, "TPA end agg_buf %d != expected agg_bufs %d\n", 1532 agg_bufs, tpa_info->agg_count); 1533 agg_bufs = tpa_info->agg_count; 1534 } 1535 tpa_info->agg_count = 0; 1536 *event |= BNXT_AGG_EVENT; 1537 bnxt_free_agg_idx(rxr, agg_id); 1538 idx = agg_id; 1539 gro = !!(bp->flags & BNXT_FLAG_GRO); 1540 } else { 1541 agg_id = TPA_END_AGG_ID(tpa_end); 1542 agg_bufs = TPA_END_AGG_BUFS(tpa_end); 1543 tpa_info = &rxr->rx_tpa[agg_id]; 1544 idx = RING_CMP(*raw_cons); 1545 if (agg_bufs) { 1546 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, raw_cons)) 1547 return ERR_PTR(-EBUSY); 1548 1549 *event |= BNXT_AGG_EVENT; 1550 idx = NEXT_CMP(idx); 1551 } 1552 gro = !!TPA_END_GRO(tpa_end); 1553 } 1554 data = tpa_info->data; 1555 data_ptr = tpa_info->data_ptr; 1556 prefetch(data_ptr); 1557 len = tpa_info->len; 1558 mapping = tpa_info->mapping; 1559 1560 if (unlikely(agg_bufs > MAX_SKB_FRAGS || TPA_END_ERRORS(tpa_end1))) { 1561 bnxt_abort_tpa(cpr, idx, agg_bufs); 1562 if (agg_bufs > MAX_SKB_FRAGS) 1563 netdev_warn(bp->dev, "TPA frags %d exceeded MAX_SKB_FRAGS %d\n", 1564 agg_bufs, (int)MAX_SKB_FRAGS); 1565 return NULL; 1566 } 1567 1568 if (len <= bp->rx_copy_thresh) { 1569 skb = bnxt_copy_skb(bnapi, data_ptr, len, mapping); 1570 if (!skb) { 1571 bnxt_abort_tpa(cpr, idx, agg_bufs); 1572 return NULL; 1573 } 1574 } else { 1575 u8 *new_data; 1576 dma_addr_t new_mapping; 1577 1578 new_data = __bnxt_alloc_rx_data(bp, &new_mapping, GFP_ATOMIC); 1579 if (!new_data) { 1580 bnxt_abort_tpa(cpr, idx, agg_bufs); 1581 return NULL; 1582 } 1583 1584 tpa_info->data = new_data; 1585 tpa_info->data_ptr = new_data + bp->rx_offset; 1586 tpa_info->mapping = new_mapping; 1587 1588 skb = build_skb(data, 0); 1589 dma_unmap_single_attrs(&bp->pdev->dev, mapping, 1590 bp->rx_buf_use_size, bp->rx_dir, 1591 DMA_ATTR_WEAK_ORDERING); 1592 1593 if (!skb) { 1594 kfree(data); 1595 bnxt_abort_tpa(cpr, idx, agg_bufs); 1596 return NULL; 1597 } 1598 skb_reserve(skb, bp->rx_offset); 1599 skb_put(skb, len); 1600 } 1601 1602 if (agg_bufs) { 1603 skb = bnxt_rx_pages(bp, cpr, skb, idx, agg_bufs, true); 1604 if (!skb) { 1605 /* Page reuse already handled by bnxt_rx_pages(). */ 1606 return NULL; 1607 } 1608 } 1609 1610 skb->protocol = 1611 eth_type_trans(skb, bnxt_get_pkt_dev(bp, tpa_info->cfa_code)); 1612 1613 if (tpa_info->hash_type != PKT_HASH_TYPE_NONE) 1614 skb_set_hash(skb, tpa_info->rss_hash, tpa_info->hash_type); 1615 1616 if ((tpa_info->flags2 & RX_CMP_FLAGS2_META_FORMAT_VLAN) && 1617 (skb->dev->features & BNXT_HW_FEATURE_VLAN_ALL_RX)) { 1618 u16 vlan_proto = tpa_info->metadata >> 1619 RX_CMP_FLAGS2_METADATA_TPID_SFT; 1620 u16 vtag = tpa_info->metadata & RX_CMP_FLAGS2_METADATA_TCI_MASK; 1621 1622 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag); 1623 } 1624 1625 skb_checksum_none_assert(skb); 1626 if (likely(tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_L4_CS_CALC)) { 1627 skb->ip_summed = CHECKSUM_UNNECESSARY; 1628 skb->csum_level = 1629 (tpa_info->flags2 & RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3; 1630 } 1631 1632 if (gro) 1633 skb = bnxt_gro_skb(bp, tpa_info, tpa_end, tpa_end1, skb); 1634 1635 return skb; 1636 } 1637 1638 static void bnxt_tpa_agg(struct bnxt *bp, struct bnxt_rx_ring_info *rxr, 1639 struct rx_agg_cmp *rx_agg) 1640 { 1641 u16 agg_id = TPA_AGG_AGG_ID(rx_agg); 1642 struct bnxt_tpa_info *tpa_info; 1643 1644 agg_id = bnxt_lookup_agg_idx(rxr, agg_id); 1645 tpa_info = &rxr->rx_tpa[agg_id]; 1646 BUG_ON(tpa_info->agg_count >= MAX_SKB_FRAGS); 1647 tpa_info->agg_arr[tpa_info->agg_count++] = *rx_agg; 1648 } 1649 1650 static void bnxt_deliver_skb(struct bnxt *bp, struct bnxt_napi *bnapi, 1651 struct sk_buff *skb) 1652 { 1653 if (skb->dev != bp->dev) { 1654 /* this packet belongs to a vf-rep */ 1655 bnxt_vf_rep_rx(bp, skb); 1656 return; 1657 } 1658 skb_record_rx_queue(skb, bnapi->index); 1659 napi_gro_receive(&bnapi->napi, skb); 1660 } 1661 1662 /* returns the following: 1663 * 1 - 1 packet successfully received 1664 * 0 - successful TPA_START, packet not completed yet 1665 * -EBUSY - completion ring does not have all the agg buffers yet 1666 * -ENOMEM - packet aborted due to out of memory 1667 * -EIO - packet aborted due to hw error indicated in BD 1668 */ 1669 static int bnxt_rx_pkt(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, 1670 u32 *raw_cons, u8 *event) 1671 { 1672 struct bnxt_napi *bnapi = cpr->bnapi; 1673 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 1674 struct net_device *dev = bp->dev; 1675 struct rx_cmp *rxcmp; 1676 struct rx_cmp_ext *rxcmp1; 1677 u32 tmp_raw_cons = *raw_cons; 1678 u16 cfa_code, cons, prod, cp_cons = RING_CMP(tmp_raw_cons); 1679 struct bnxt_sw_rx_bd *rx_buf; 1680 unsigned int len; 1681 u8 *data_ptr, agg_bufs, cmp_type; 1682 dma_addr_t dma_addr; 1683 struct sk_buff *skb; 1684 void *data; 1685 int rc = 0; 1686 u32 misc; 1687 1688 rxcmp = (struct rx_cmp *) 1689 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 1690 1691 cmp_type = RX_CMP_TYPE(rxcmp); 1692 1693 if (cmp_type == CMP_TYPE_RX_TPA_AGG_CMP) { 1694 bnxt_tpa_agg(bp, rxr, (struct rx_agg_cmp *)rxcmp); 1695 goto next_rx_no_prod_no_len; 1696 } 1697 1698 tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons); 1699 cp_cons = RING_CMP(tmp_raw_cons); 1700 rxcmp1 = (struct rx_cmp_ext *) 1701 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 1702 1703 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons)) 1704 return -EBUSY; 1705 1706 prod = rxr->rx_prod; 1707 1708 if (cmp_type == CMP_TYPE_RX_L2_TPA_START_CMP) { 1709 bnxt_tpa_start(bp, rxr, (struct rx_tpa_start_cmp *)rxcmp, 1710 (struct rx_tpa_start_cmp_ext *)rxcmp1); 1711 1712 *event |= BNXT_RX_EVENT; 1713 goto next_rx_no_prod_no_len; 1714 1715 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) { 1716 skb = bnxt_tpa_end(bp, cpr, &tmp_raw_cons, 1717 (struct rx_tpa_end_cmp *)rxcmp, 1718 (struct rx_tpa_end_cmp_ext *)rxcmp1, event); 1719 1720 if (IS_ERR(skb)) 1721 return -EBUSY; 1722 1723 rc = -ENOMEM; 1724 if (likely(skb)) { 1725 bnxt_deliver_skb(bp, bnapi, skb); 1726 rc = 1; 1727 } 1728 *event |= BNXT_RX_EVENT; 1729 goto next_rx_no_prod_no_len; 1730 } 1731 1732 cons = rxcmp->rx_cmp_opaque; 1733 if (unlikely(cons != rxr->rx_next_cons)) { 1734 int rc1 = bnxt_discard_rx(bp, cpr, raw_cons, rxcmp); 1735 1736 netdev_warn(bp->dev, "RX cons %x != expected cons %x\n", 1737 cons, rxr->rx_next_cons); 1738 bnxt_sched_reset(bp, rxr); 1739 return rc1; 1740 } 1741 rx_buf = &rxr->rx_buf_ring[cons]; 1742 data = rx_buf->data; 1743 data_ptr = rx_buf->data_ptr; 1744 prefetch(data_ptr); 1745 1746 misc = le32_to_cpu(rxcmp->rx_cmp_misc_v1); 1747 agg_bufs = (misc & RX_CMP_AGG_BUFS) >> RX_CMP_AGG_BUFS_SHIFT; 1748 1749 if (agg_bufs) { 1750 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons)) 1751 return -EBUSY; 1752 1753 cp_cons = NEXT_CMP(cp_cons); 1754 *event |= BNXT_AGG_EVENT; 1755 } 1756 *event |= BNXT_RX_EVENT; 1757 1758 rx_buf->data = NULL; 1759 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L2_ERRORS) { 1760 u32 rx_err = le32_to_cpu(rxcmp1->rx_cmp_cfa_code_errors_v2); 1761 1762 bnxt_reuse_rx_data(rxr, cons, data); 1763 if (agg_bufs) 1764 bnxt_reuse_rx_agg_bufs(cpr, cp_cons, 0, agg_bufs, 1765 false); 1766 1767 rc = -EIO; 1768 if (rx_err & RX_CMPL_ERRORS_BUFFER_ERROR_MASK) { 1769 bnapi->cp_ring.sw_stats.rx.rx_buf_errors++; 1770 if (!(bp->flags & BNXT_FLAG_CHIP_P5)) { 1771 netdev_warn(bp->dev, "RX buffer error %x\n", 1772 rx_err); 1773 bnxt_sched_reset(bp, rxr); 1774 } 1775 } 1776 goto next_rx_no_len; 1777 } 1778 1779 len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT; 1780 dma_addr = rx_buf->mapping; 1781 1782 if (bnxt_rx_xdp(bp, rxr, cons, data, &data_ptr, &len, event)) { 1783 rc = 1; 1784 goto next_rx; 1785 } 1786 1787 if (len <= bp->rx_copy_thresh) { 1788 skb = bnxt_copy_skb(bnapi, data_ptr, len, dma_addr); 1789 bnxt_reuse_rx_data(rxr, cons, data); 1790 if (!skb) { 1791 if (agg_bufs) 1792 bnxt_reuse_rx_agg_bufs(cpr, cp_cons, 0, 1793 agg_bufs, false); 1794 rc = -ENOMEM; 1795 goto next_rx; 1796 } 1797 } else { 1798 u32 payload; 1799 1800 if (rx_buf->data_ptr == data_ptr) 1801 payload = misc & RX_CMP_PAYLOAD_OFFSET; 1802 else 1803 payload = 0; 1804 skb = bp->rx_skb_func(bp, rxr, cons, data, data_ptr, dma_addr, 1805 payload | len); 1806 if (!skb) { 1807 rc = -ENOMEM; 1808 goto next_rx; 1809 } 1810 } 1811 1812 if (agg_bufs) { 1813 skb = bnxt_rx_pages(bp, cpr, skb, cp_cons, agg_bufs, false); 1814 if (!skb) { 1815 rc = -ENOMEM; 1816 goto next_rx; 1817 } 1818 } 1819 1820 if (RX_CMP_HASH_VALID(rxcmp)) { 1821 u32 hash_type = RX_CMP_HASH_TYPE(rxcmp); 1822 enum pkt_hash_types type = PKT_HASH_TYPE_L4; 1823 1824 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */ 1825 if (hash_type != 1 && hash_type != 3) 1826 type = PKT_HASH_TYPE_L3; 1827 skb_set_hash(skb, le32_to_cpu(rxcmp->rx_cmp_rss_hash), type); 1828 } 1829 1830 cfa_code = RX_CMP_CFA_CODE(rxcmp1); 1831 skb->protocol = eth_type_trans(skb, bnxt_get_pkt_dev(bp, cfa_code)); 1832 1833 if ((rxcmp1->rx_cmp_flags2 & 1834 cpu_to_le32(RX_CMP_FLAGS2_META_FORMAT_VLAN)) && 1835 (skb->dev->features & BNXT_HW_FEATURE_VLAN_ALL_RX)) { 1836 u32 meta_data = le32_to_cpu(rxcmp1->rx_cmp_meta_data); 1837 u16 vtag = meta_data & RX_CMP_FLAGS2_METADATA_TCI_MASK; 1838 u16 vlan_proto = meta_data >> RX_CMP_FLAGS2_METADATA_TPID_SFT; 1839 1840 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag); 1841 } 1842 1843 skb_checksum_none_assert(skb); 1844 if (RX_CMP_L4_CS_OK(rxcmp1)) { 1845 if (dev->features & NETIF_F_RXCSUM) { 1846 skb->ip_summed = CHECKSUM_UNNECESSARY; 1847 skb->csum_level = RX_CMP_ENCAP(rxcmp1); 1848 } 1849 } else { 1850 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS) { 1851 if (dev->features & NETIF_F_RXCSUM) 1852 bnapi->cp_ring.sw_stats.rx.rx_l4_csum_errors++; 1853 } 1854 } 1855 1856 bnxt_deliver_skb(bp, bnapi, skb); 1857 rc = 1; 1858 1859 next_rx: 1860 cpr->rx_packets += 1; 1861 cpr->rx_bytes += len; 1862 1863 next_rx_no_len: 1864 rxr->rx_prod = NEXT_RX(prod); 1865 rxr->rx_next_cons = NEXT_RX(cons); 1866 1867 next_rx_no_prod_no_len: 1868 *raw_cons = tmp_raw_cons; 1869 1870 return rc; 1871 } 1872 1873 /* In netpoll mode, if we are using a combined completion ring, we need to 1874 * discard the rx packets and recycle the buffers. 1875 */ 1876 static int bnxt_force_rx_discard(struct bnxt *bp, 1877 struct bnxt_cp_ring_info *cpr, 1878 u32 *raw_cons, u8 *event) 1879 { 1880 u32 tmp_raw_cons = *raw_cons; 1881 struct rx_cmp_ext *rxcmp1; 1882 struct rx_cmp *rxcmp; 1883 u16 cp_cons; 1884 u8 cmp_type; 1885 1886 cp_cons = RING_CMP(tmp_raw_cons); 1887 rxcmp = (struct rx_cmp *) 1888 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 1889 1890 tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons); 1891 cp_cons = RING_CMP(tmp_raw_cons); 1892 rxcmp1 = (struct rx_cmp_ext *) 1893 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 1894 1895 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons)) 1896 return -EBUSY; 1897 1898 cmp_type = RX_CMP_TYPE(rxcmp); 1899 if (cmp_type == CMP_TYPE_RX_L2_CMP) { 1900 rxcmp1->rx_cmp_cfa_code_errors_v2 |= 1901 cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR); 1902 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) { 1903 struct rx_tpa_end_cmp_ext *tpa_end1; 1904 1905 tpa_end1 = (struct rx_tpa_end_cmp_ext *)rxcmp1; 1906 tpa_end1->rx_tpa_end_cmp_errors_v2 |= 1907 cpu_to_le32(RX_TPA_END_CMP_ERRORS); 1908 } 1909 return bnxt_rx_pkt(bp, cpr, raw_cons, event); 1910 } 1911 1912 u32 bnxt_fw_health_readl(struct bnxt *bp, int reg_idx) 1913 { 1914 struct bnxt_fw_health *fw_health = bp->fw_health; 1915 u32 reg = fw_health->regs[reg_idx]; 1916 u32 reg_type, reg_off, val = 0; 1917 1918 reg_type = BNXT_FW_HEALTH_REG_TYPE(reg); 1919 reg_off = BNXT_FW_HEALTH_REG_OFF(reg); 1920 switch (reg_type) { 1921 case BNXT_FW_HEALTH_REG_TYPE_CFG: 1922 pci_read_config_dword(bp->pdev, reg_off, &val); 1923 break; 1924 case BNXT_FW_HEALTH_REG_TYPE_GRC: 1925 reg_off = fw_health->mapped_regs[reg_idx]; 1926 /* fall through */ 1927 case BNXT_FW_HEALTH_REG_TYPE_BAR0: 1928 val = readl(bp->bar0 + reg_off); 1929 break; 1930 case BNXT_FW_HEALTH_REG_TYPE_BAR1: 1931 val = readl(bp->bar1 + reg_off); 1932 break; 1933 } 1934 if (reg_idx == BNXT_FW_RESET_INPROG_REG) 1935 val &= fw_health->fw_reset_inprog_reg_mask; 1936 return val; 1937 } 1938 1939 #define BNXT_GET_EVENT_PORT(data) \ 1940 ((data) & \ 1941 ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK) 1942 1943 static int bnxt_async_event_process(struct bnxt *bp, 1944 struct hwrm_async_event_cmpl *cmpl) 1945 { 1946 u16 event_id = le16_to_cpu(cmpl->event_id); 1947 1948 /* TODO CHIMP_FW: Define event id's for link change, error etc */ 1949 switch (event_id) { 1950 case ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE: { 1951 u32 data1 = le32_to_cpu(cmpl->event_data1); 1952 struct bnxt_link_info *link_info = &bp->link_info; 1953 1954 if (BNXT_VF(bp)) 1955 goto async_event_process_exit; 1956 1957 /* print unsupported speed warning in forced speed mode only */ 1958 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED) && 1959 (data1 & 0x20000)) { 1960 u16 fw_speed = link_info->force_link_speed; 1961 u32 speed = bnxt_fw_to_ethtool_speed(fw_speed); 1962 1963 if (speed != SPEED_UNKNOWN) 1964 netdev_warn(bp->dev, "Link speed %d no longer supported\n", 1965 speed); 1966 } 1967 set_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT, &bp->sp_event); 1968 } 1969 /* fall through */ 1970 case ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE: 1971 case ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE: 1972 set_bit(BNXT_LINK_CFG_CHANGE_SP_EVENT, &bp->sp_event); 1973 /* fall through */ 1974 case ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE: 1975 set_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event); 1976 break; 1977 case ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD: 1978 set_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event); 1979 break; 1980 case ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED: { 1981 u32 data1 = le32_to_cpu(cmpl->event_data1); 1982 u16 port_id = BNXT_GET_EVENT_PORT(data1); 1983 1984 if (BNXT_VF(bp)) 1985 break; 1986 1987 if (bp->pf.port_id != port_id) 1988 break; 1989 1990 set_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event); 1991 break; 1992 } 1993 case ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE: 1994 if (BNXT_PF(bp)) 1995 goto async_event_process_exit; 1996 set_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event); 1997 break; 1998 case ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY: { 1999 u32 data1 = le32_to_cpu(cmpl->event_data1); 2000 2001 if (!bp->fw_health) 2002 goto async_event_process_exit; 2003 2004 bp->fw_reset_timestamp = jiffies; 2005 bp->fw_reset_min_dsecs = cmpl->timestamp_lo; 2006 if (!bp->fw_reset_min_dsecs) 2007 bp->fw_reset_min_dsecs = BNXT_DFLT_FW_RST_MIN_DSECS; 2008 bp->fw_reset_max_dsecs = le16_to_cpu(cmpl->timestamp_hi); 2009 if (!bp->fw_reset_max_dsecs) 2010 bp->fw_reset_max_dsecs = BNXT_DFLT_FW_RST_MAX_DSECS; 2011 if (EVENT_DATA1_RESET_NOTIFY_FATAL(data1)) { 2012 netdev_warn(bp->dev, "Firmware fatal reset event received\n"); 2013 set_bit(BNXT_STATE_FW_FATAL_COND, &bp->state); 2014 } else { 2015 netdev_warn(bp->dev, "Firmware non-fatal reset event received, max wait time %d msec\n", 2016 bp->fw_reset_max_dsecs * 100); 2017 } 2018 set_bit(BNXT_FW_RESET_NOTIFY_SP_EVENT, &bp->sp_event); 2019 break; 2020 } 2021 case ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY: { 2022 struct bnxt_fw_health *fw_health = bp->fw_health; 2023 u32 data1 = le32_to_cpu(cmpl->event_data1); 2024 2025 if (!fw_health) 2026 goto async_event_process_exit; 2027 2028 fw_health->enabled = EVENT_DATA1_RECOVERY_ENABLED(data1); 2029 fw_health->master = EVENT_DATA1_RECOVERY_MASTER_FUNC(data1); 2030 if (!fw_health->enabled) 2031 break; 2032 2033 if (netif_msg_drv(bp)) 2034 netdev_info(bp->dev, "Error recovery info: error recovery[%d], master[%d], reset count[0x%x], health status: 0x%x\n", 2035 fw_health->enabled, fw_health->master, 2036 bnxt_fw_health_readl(bp, 2037 BNXT_FW_RESET_CNT_REG), 2038 bnxt_fw_health_readl(bp, 2039 BNXT_FW_HEALTH_REG)); 2040 fw_health->tmr_multiplier = 2041 DIV_ROUND_UP(fw_health->polling_dsecs * HZ, 2042 bp->current_interval * 10); 2043 fw_health->tmr_counter = fw_health->tmr_multiplier; 2044 fw_health->last_fw_heartbeat = 2045 bnxt_fw_health_readl(bp, BNXT_FW_HEARTBEAT_REG); 2046 fw_health->last_fw_reset_cnt = 2047 bnxt_fw_health_readl(bp, BNXT_FW_RESET_CNT_REG); 2048 goto async_event_process_exit; 2049 } 2050 default: 2051 goto async_event_process_exit; 2052 } 2053 bnxt_queue_sp_work(bp); 2054 async_event_process_exit: 2055 bnxt_ulp_async_events(bp, cmpl); 2056 return 0; 2057 } 2058 2059 static int bnxt_hwrm_handler(struct bnxt *bp, struct tx_cmp *txcmp) 2060 { 2061 u16 cmpl_type = TX_CMP_TYPE(txcmp), vf_id, seq_id; 2062 struct hwrm_cmpl *h_cmpl = (struct hwrm_cmpl *)txcmp; 2063 struct hwrm_fwd_req_cmpl *fwd_req_cmpl = 2064 (struct hwrm_fwd_req_cmpl *)txcmp; 2065 2066 switch (cmpl_type) { 2067 case CMPL_BASE_TYPE_HWRM_DONE: 2068 seq_id = le16_to_cpu(h_cmpl->sequence_id); 2069 if (seq_id == bp->hwrm_intr_seq_id) 2070 bp->hwrm_intr_seq_id = (u16)~bp->hwrm_intr_seq_id; 2071 else 2072 netdev_err(bp->dev, "Invalid hwrm seq id %d\n", seq_id); 2073 break; 2074 2075 case CMPL_BASE_TYPE_HWRM_FWD_REQ: 2076 vf_id = le16_to_cpu(fwd_req_cmpl->source_id); 2077 2078 if ((vf_id < bp->pf.first_vf_id) || 2079 (vf_id >= bp->pf.first_vf_id + bp->pf.active_vfs)) { 2080 netdev_err(bp->dev, "Msg contains invalid VF id %x\n", 2081 vf_id); 2082 return -EINVAL; 2083 } 2084 2085 set_bit(vf_id - bp->pf.first_vf_id, bp->pf.vf_event_bmap); 2086 set_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event); 2087 bnxt_queue_sp_work(bp); 2088 break; 2089 2090 case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT: 2091 bnxt_async_event_process(bp, 2092 (struct hwrm_async_event_cmpl *)txcmp); 2093 2094 default: 2095 break; 2096 } 2097 2098 return 0; 2099 } 2100 2101 static irqreturn_t bnxt_msix(int irq, void *dev_instance) 2102 { 2103 struct bnxt_napi *bnapi = dev_instance; 2104 struct bnxt *bp = bnapi->bp; 2105 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 2106 u32 cons = RING_CMP(cpr->cp_raw_cons); 2107 2108 cpr->event_ctr++; 2109 prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]); 2110 napi_schedule(&bnapi->napi); 2111 return IRQ_HANDLED; 2112 } 2113 2114 static inline int bnxt_has_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr) 2115 { 2116 u32 raw_cons = cpr->cp_raw_cons; 2117 u16 cons = RING_CMP(raw_cons); 2118 struct tx_cmp *txcmp; 2119 2120 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]; 2121 2122 return TX_CMP_VALID(txcmp, raw_cons); 2123 } 2124 2125 static irqreturn_t bnxt_inta(int irq, void *dev_instance) 2126 { 2127 struct bnxt_napi *bnapi = dev_instance; 2128 struct bnxt *bp = bnapi->bp; 2129 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 2130 u32 cons = RING_CMP(cpr->cp_raw_cons); 2131 u32 int_status; 2132 2133 prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]); 2134 2135 if (!bnxt_has_work(bp, cpr)) { 2136 int_status = readl(bp->bar0 + BNXT_CAG_REG_LEGACY_INT_STATUS); 2137 /* return if erroneous interrupt */ 2138 if (!(int_status & (0x10000 << cpr->cp_ring_struct.fw_ring_id))) 2139 return IRQ_NONE; 2140 } 2141 2142 /* disable ring IRQ */ 2143 BNXT_CP_DB_IRQ_DIS(cpr->cp_db.doorbell); 2144 2145 /* Return here if interrupt is shared and is disabled. */ 2146 if (unlikely(atomic_read(&bp->intr_sem) != 0)) 2147 return IRQ_HANDLED; 2148 2149 napi_schedule(&bnapi->napi); 2150 return IRQ_HANDLED; 2151 } 2152 2153 static int __bnxt_poll_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, 2154 int budget) 2155 { 2156 struct bnxt_napi *bnapi = cpr->bnapi; 2157 u32 raw_cons = cpr->cp_raw_cons; 2158 u32 cons; 2159 int tx_pkts = 0; 2160 int rx_pkts = 0; 2161 u8 event = 0; 2162 struct tx_cmp *txcmp; 2163 2164 cpr->has_more_work = 0; 2165 cpr->had_work_done = 1; 2166 while (1) { 2167 int rc; 2168 2169 cons = RING_CMP(raw_cons); 2170 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]; 2171 2172 if (!TX_CMP_VALID(txcmp, raw_cons)) 2173 break; 2174 2175 /* The valid test of the entry must be done first before 2176 * reading any further. 2177 */ 2178 dma_rmb(); 2179 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_TX_L2_CMP) { 2180 tx_pkts++; 2181 /* return full budget so NAPI will complete. */ 2182 if (unlikely(tx_pkts > bp->tx_wake_thresh)) { 2183 rx_pkts = budget; 2184 raw_cons = NEXT_RAW_CMP(raw_cons); 2185 if (budget) 2186 cpr->has_more_work = 1; 2187 break; 2188 } 2189 } else if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) { 2190 if (likely(budget)) 2191 rc = bnxt_rx_pkt(bp, cpr, &raw_cons, &event); 2192 else 2193 rc = bnxt_force_rx_discard(bp, cpr, &raw_cons, 2194 &event); 2195 if (likely(rc >= 0)) 2196 rx_pkts += rc; 2197 /* Increment rx_pkts when rc is -ENOMEM to count towards 2198 * the NAPI budget. Otherwise, we may potentially loop 2199 * here forever if we consistently cannot allocate 2200 * buffers. 2201 */ 2202 else if (rc == -ENOMEM && budget) 2203 rx_pkts++; 2204 else if (rc == -EBUSY) /* partial completion */ 2205 break; 2206 } else if (unlikely((TX_CMP_TYPE(txcmp) == 2207 CMPL_BASE_TYPE_HWRM_DONE) || 2208 (TX_CMP_TYPE(txcmp) == 2209 CMPL_BASE_TYPE_HWRM_FWD_REQ) || 2210 (TX_CMP_TYPE(txcmp) == 2211 CMPL_BASE_TYPE_HWRM_ASYNC_EVENT))) { 2212 bnxt_hwrm_handler(bp, txcmp); 2213 } 2214 raw_cons = NEXT_RAW_CMP(raw_cons); 2215 2216 if (rx_pkts && rx_pkts == budget) { 2217 cpr->has_more_work = 1; 2218 break; 2219 } 2220 } 2221 2222 if (event & BNXT_REDIRECT_EVENT) 2223 xdp_do_flush_map(); 2224 2225 if (event & BNXT_TX_EVENT) { 2226 struct bnxt_tx_ring_info *txr = bnapi->tx_ring; 2227 u16 prod = txr->tx_prod; 2228 2229 /* Sync BD data before updating doorbell */ 2230 wmb(); 2231 2232 bnxt_db_write_relaxed(bp, &txr->tx_db, prod); 2233 } 2234 2235 cpr->cp_raw_cons = raw_cons; 2236 bnapi->tx_pkts += tx_pkts; 2237 bnapi->events |= event; 2238 return rx_pkts; 2239 } 2240 2241 static void __bnxt_poll_work_done(struct bnxt *bp, struct bnxt_napi *bnapi) 2242 { 2243 if (bnapi->tx_pkts) { 2244 bnapi->tx_int(bp, bnapi, bnapi->tx_pkts); 2245 bnapi->tx_pkts = 0; 2246 } 2247 2248 if (bnapi->events & BNXT_RX_EVENT) { 2249 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 2250 2251 if (bnapi->events & BNXT_AGG_EVENT) 2252 bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod); 2253 bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod); 2254 } 2255 bnapi->events = 0; 2256 } 2257 2258 static int bnxt_poll_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, 2259 int budget) 2260 { 2261 struct bnxt_napi *bnapi = cpr->bnapi; 2262 int rx_pkts; 2263 2264 rx_pkts = __bnxt_poll_work(bp, cpr, budget); 2265 2266 /* ACK completion ring before freeing tx ring and producing new 2267 * buffers in rx/agg rings to prevent overflowing the completion 2268 * ring. 2269 */ 2270 bnxt_db_cq(bp, &cpr->cp_db, cpr->cp_raw_cons); 2271 2272 __bnxt_poll_work_done(bp, bnapi); 2273 return rx_pkts; 2274 } 2275 2276 static int bnxt_poll_nitroa0(struct napi_struct *napi, int budget) 2277 { 2278 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi); 2279 struct bnxt *bp = bnapi->bp; 2280 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 2281 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 2282 struct tx_cmp *txcmp; 2283 struct rx_cmp_ext *rxcmp1; 2284 u32 cp_cons, tmp_raw_cons; 2285 u32 raw_cons = cpr->cp_raw_cons; 2286 u32 rx_pkts = 0; 2287 u8 event = 0; 2288 2289 while (1) { 2290 int rc; 2291 2292 cp_cons = RING_CMP(raw_cons); 2293 txcmp = &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 2294 2295 if (!TX_CMP_VALID(txcmp, raw_cons)) 2296 break; 2297 2298 if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) { 2299 tmp_raw_cons = NEXT_RAW_CMP(raw_cons); 2300 cp_cons = RING_CMP(tmp_raw_cons); 2301 rxcmp1 = (struct rx_cmp_ext *) 2302 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 2303 2304 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons)) 2305 break; 2306 2307 /* force an error to recycle the buffer */ 2308 rxcmp1->rx_cmp_cfa_code_errors_v2 |= 2309 cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR); 2310 2311 rc = bnxt_rx_pkt(bp, cpr, &raw_cons, &event); 2312 if (likely(rc == -EIO) && budget) 2313 rx_pkts++; 2314 else if (rc == -EBUSY) /* partial completion */ 2315 break; 2316 } else if (unlikely(TX_CMP_TYPE(txcmp) == 2317 CMPL_BASE_TYPE_HWRM_DONE)) { 2318 bnxt_hwrm_handler(bp, txcmp); 2319 } else { 2320 netdev_err(bp->dev, 2321 "Invalid completion received on special ring\n"); 2322 } 2323 raw_cons = NEXT_RAW_CMP(raw_cons); 2324 2325 if (rx_pkts == budget) 2326 break; 2327 } 2328 2329 cpr->cp_raw_cons = raw_cons; 2330 BNXT_DB_CQ(&cpr->cp_db, cpr->cp_raw_cons); 2331 bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod); 2332 2333 if (event & BNXT_AGG_EVENT) 2334 bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod); 2335 2336 if (!bnxt_has_work(bp, cpr) && rx_pkts < budget) { 2337 napi_complete_done(napi, rx_pkts); 2338 BNXT_DB_CQ_ARM(&cpr->cp_db, cpr->cp_raw_cons); 2339 } 2340 return rx_pkts; 2341 } 2342 2343 static int bnxt_poll(struct napi_struct *napi, int budget) 2344 { 2345 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi); 2346 struct bnxt *bp = bnapi->bp; 2347 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 2348 int work_done = 0; 2349 2350 while (1) { 2351 work_done += bnxt_poll_work(bp, cpr, budget - work_done); 2352 2353 if (work_done >= budget) { 2354 if (!budget) 2355 BNXT_DB_CQ_ARM(&cpr->cp_db, cpr->cp_raw_cons); 2356 break; 2357 } 2358 2359 if (!bnxt_has_work(bp, cpr)) { 2360 if (napi_complete_done(napi, work_done)) 2361 BNXT_DB_CQ_ARM(&cpr->cp_db, cpr->cp_raw_cons); 2362 break; 2363 } 2364 } 2365 if (bp->flags & BNXT_FLAG_DIM) { 2366 struct dim_sample dim_sample = {}; 2367 2368 dim_update_sample(cpr->event_ctr, 2369 cpr->rx_packets, 2370 cpr->rx_bytes, 2371 &dim_sample); 2372 net_dim(&cpr->dim, dim_sample); 2373 } 2374 return work_done; 2375 } 2376 2377 static int __bnxt_poll_cqs(struct bnxt *bp, struct bnxt_napi *bnapi, int budget) 2378 { 2379 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 2380 int i, work_done = 0; 2381 2382 for (i = 0; i < 2; i++) { 2383 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[i]; 2384 2385 if (cpr2) { 2386 work_done += __bnxt_poll_work(bp, cpr2, 2387 budget - work_done); 2388 cpr->has_more_work |= cpr2->has_more_work; 2389 } 2390 } 2391 return work_done; 2392 } 2393 2394 static void __bnxt_poll_cqs_done(struct bnxt *bp, struct bnxt_napi *bnapi, 2395 u64 dbr_type) 2396 { 2397 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 2398 int i; 2399 2400 for (i = 0; i < 2; i++) { 2401 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[i]; 2402 struct bnxt_db_info *db; 2403 2404 if (cpr2 && cpr2->had_work_done) { 2405 db = &cpr2->cp_db; 2406 writeq(db->db_key64 | dbr_type | 2407 RING_CMP(cpr2->cp_raw_cons), db->doorbell); 2408 cpr2->had_work_done = 0; 2409 } 2410 } 2411 __bnxt_poll_work_done(bp, bnapi); 2412 } 2413 2414 static int bnxt_poll_p5(struct napi_struct *napi, int budget) 2415 { 2416 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi); 2417 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 2418 u32 raw_cons = cpr->cp_raw_cons; 2419 struct bnxt *bp = bnapi->bp; 2420 struct nqe_cn *nqcmp; 2421 int work_done = 0; 2422 u32 cons; 2423 2424 if (cpr->has_more_work) { 2425 cpr->has_more_work = 0; 2426 work_done = __bnxt_poll_cqs(bp, bnapi, budget); 2427 } 2428 while (1) { 2429 cons = RING_CMP(raw_cons); 2430 nqcmp = &cpr->nq_desc_ring[CP_RING(cons)][CP_IDX(cons)]; 2431 2432 if (!NQ_CMP_VALID(nqcmp, raw_cons)) { 2433 if (cpr->has_more_work) 2434 break; 2435 2436 __bnxt_poll_cqs_done(bp, bnapi, DBR_TYPE_CQ_ARMALL); 2437 cpr->cp_raw_cons = raw_cons; 2438 if (napi_complete_done(napi, work_done)) 2439 BNXT_DB_NQ_ARM_P5(&cpr->cp_db, 2440 cpr->cp_raw_cons); 2441 return work_done; 2442 } 2443 2444 /* The valid test of the entry must be done first before 2445 * reading any further. 2446 */ 2447 dma_rmb(); 2448 2449 if (nqcmp->type == cpu_to_le16(NQ_CN_TYPE_CQ_NOTIFICATION)) { 2450 u32 idx = le32_to_cpu(nqcmp->cq_handle_low); 2451 struct bnxt_cp_ring_info *cpr2; 2452 2453 cpr2 = cpr->cp_ring_arr[idx]; 2454 work_done += __bnxt_poll_work(bp, cpr2, 2455 budget - work_done); 2456 cpr->has_more_work |= cpr2->has_more_work; 2457 } else { 2458 bnxt_hwrm_handler(bp, (struct tx_cmp *)nqcmp); 2459 } 2460 raw_cons = NEXT_RAW_CMP(raw_cons); 2461 } 2462 __bnxt_poll_cqs_done(bp, bnapi, DBR_TYPE_CQ); 2463 if (raw_cons != cpr->cp_raw_cons) { 2464 cpr->cp_raw_cons = raw_cons; 2465 BNXT_DB_NQ_P5(&cpr->cp_db, raw_cons); 2466 } 2467 return work_done; 2468 } 2469 2470 static void bnxt_free_tx_skbs(struct bnxt *bp) 2471 { 2472 int i, max_idx; 2473 struct pci_dev *pdev = bp->pdev; 2474 2475 if (!bp->tx_ring) 2476 return; 2477 2478 max_idx = bp->tx_nr_pages * TX_DESC_CNT; 2479 for (i = 0; i < bp->tx_nr_rings; i++) { 2480 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; 2481 int j; 2482 2483 for (j = 0; j < max_idx;) { 2484 struct bnxt_sw_tx_bd *tx_buf = &txr->tx_buf_ring[j]; 2485 struct sk_buff *skb; 2486 int k, last; 2487 2488 if (i < bp->tx_nr_rings_xdp && 2489 tx_buf->action == XDP_REDIRECT) { 2490 dma_unmap_single(&pdev->dev, 2491 dma_unmap_addr(tx_buf, mapping), 2492 dma_unmap_len(tx_buf, len), 2493 PCI_DMA_TODEVICE); 2494 xdp_return_frame(tx_buf->xdpf); 2495 tx_buf->action = 0; 2496 tx_buf->xdpf = NULL; 2497 j++; 2498 continue; 2499 } 2500 2501 skb = tx_buf->skb; 2502 if (!skb) { 2503 j++; 2504 continue; 2505 } 2506 2507 tx_buf->skb = NULL; 2508 2509 if (tx_buf->is_push) { 2510 dev_kfree_skb(skb); 2511 j += 2; 2512 continue; 2513 } 2514 2515 dma_unmap_single(&pdev->dev, 2516 dma_unmap_addr(tx_buf, mapping), 2517 skb_headlen(skb), 2518 PCI_DMA_TODEVICE); 2519 2520 last = tx_buf->nr_frags; 2521 j += 2; 2522 for (k = 0; k < last; k++, j++) { 2523 int ring_idx = j & bp->tx_ring_mask; 2524 skb_frag_t *frag = &skb_shinfo(skb)->frags[k]; 2525 2526 tx_buf = &txr->tx_buf_ring[ring_idx]; 2527 dma_unmap_page( 2528 &pdev->dev, 2529 dma_unmap_addr(tx_buf, mapping), 2530 skb_frag_size(frag), PCI_DMA_TODEVICE); 2531 } 2532 dev_kfree_skb(skb); 2533 } 2534 netdev_tx_reset_queue(netdev_get_tx_queue(bp->dev, i)); 2535 } 2536 } 2537 2538 static void bnxt_free_rx_skbs(struct bnxt *bp) 2539 { 2540 int i, max_idx, max_agg_idx; 2541 struct pci_dev *pdev = bp->pdev; 2542 2543 if (!bp->rx_ring) 2544 return; 2545 2546 max_idx = bp->rx_nr_pages * RX_DESC_CNT; 2547 max_agg_idx = bp->rx_agg_nr_pages * RX_DESC_CNT; 2548 for (i = 0; i < bp->rx_nr_rings; i++) { 2549 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 2550 struct bnxt_tpa_idx_map *map; 2551 int j; 2552 2553 if (rxr->rx_tpa) { 2554 for (j = 0; j < bp->max_tpa; j++) { 2555 struct bnxt_tpa_info *tpa_info = 2556 &rxr->rx_tpa[j]; 2557 u8 *data = tpa_info->data; 2558 2559 if (!data) 2560 continue; 2561 2562 dma_unmap_single_attrs(&pdev->dev, 2563 tpa_info->mapping, 2564 bp->rx_buf_use_size, 2565 bp->rx_dir, 2566 DMA_ATTR_WEAK_ORDERING); 2567 2568 tpa_info->data = NULL; 2569 2570 kfree(data); 2571 } 2572 } 2573 2574 for (j = 0; j < max_idx; j++) { 2575 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[j]; 2576 dma_addr_t mapping = rx_buf->mapping; 2577 void *data = rx_buf->data; 2578 2579 if (!data) 2580 continue; 2581 2582 rx_buf->data = NULL; 2583 2584 if (BNXT_RX_PAGE_MODE(bp)) { 2585 mapping -= bp->rx_dma_offset; 2586 dma_unmap_page_attrs(&pdev->dev, mapping, 2587 PAGE_SIZE, bp->rx_dir, 2588 DMA_ATTR_WEAK_ORDERING); 2589 page_pool_recycle_direct(rxr->page_pool, data); 2590 } else { 2591 dma_unmap_single_attrs(&pdev->dev, mapping, 2592 bp->rx_buf_use_size, 2593 bp->rx_dir, 2594 DMA_ATTR_WEAK_ORDERING); 2595 kfree(data); 2596 } 2597 } 2598 2599 for (j = 0; j < max_agg_idx; j++) { 2600 struct bnxt_sw_rx_agg_bd *rx_agg_buf = 2601 &rxr->rx_agg_ring[j]; 2602 struct page *page = rx_agg_buf->page; 2603 2604 if (!page) 2605 continue; 2606 2607 dma_unmap_page_attrs(&pdev->dev, rx_agg_buf->mapping, 2608 BNXT_RX_PAGE_SIZE, 2609 PCI_DMA_FROMDEVICE, 2610 DMA_ATTR_WEAK_ORDERING); 2611 2612 rx_agg_buf->page = NULL; 2613 __clear_bit(j, rxr->rx_agg_bmap); 2614 2615 __free_page(page); 2616 } 2617 if (rxr->rx_page) { 2618 __free_page(rxr->rx_page); 2619 rxr->rx_page = NULL; 2620 } 2621 map = rxr->rx_tpa_idx_map; 2622 if (map) 2623 memset(map->agg_idx_bmap, 0, sizeof(map->agg_idx_bmap)); 2624 } 2625 } 2626 2627 static void bnxt_free_skbs(struct bnxt *bp) 2628 { 2629 bnxt_free_tx_skbs(bp); 2630 bnxt_free_rx_skbs(bp); 2631 } 2632 2633 static void bnxt_free_ring(struct bnxt *bp, struct bnxt_ring_mem_info *rmem) 2634 { 2635 struct pci_dev *pdev = bp->pdev; 2636 int i; 2637 2638 for (i = 0; i < rmem->nr_pages; i++) { 2639 if (!rmem->pg_arr[i]) 2640 continue; 2641 2642 dma_free_coherent(&pdev->dev, rmem->page_size, 2643 rmem->pg_arr[i], rmem->dma_arr[i]); 2644 2645 rmem->pg_arr[i] = NULL; 2646 } 2647 if (rmem->pg_tbl) { 2648 size_t pg_tbl_size = rmem->nr_pages * 8; 2649 2650 if (rmem->flags & BNXT_RMEM_USE_FULL_PAGE_FLAG) 2651 pg_tbl_size = rmem->page_size; 2652 dma_free_coherent(&pdev->dev, pg_tbl_size, 2653 rmem->pg_tbl, rmem->pg_tbl_map); 2654 rmem->pg_tbl = NULL; 2655 } 2656 if (rmem->vmem_size && *rmem->vmem) { 2657 vfree(*rmem->vmem); 2658 *rmem->vmem = NULL; 2659 } 2660 } 2661 2662 static int bnxt_alloc_ring(struct bnxt *bp, struct bnxt_ring_mem_info *rmem) 2663 { 2664 struct pci_dev *pdev = bp->pdev; 2665 u64 valid_bit = 0; 2666 int i; 2667 2668 if (rmem->flags & (BNXT_RMEM_VALID_PTE_FLAG | BNXT_RMEM_RING_PTE_FLAG)) 2669 valid_bit = PTU_PTE_VALID; 2670 if ((rmem->nr_pages > 1 || rmem->depth > 0) && !rmem->pg_tbl) { 2671 size_t pg_tbl_size = rmem->nr_pages * 8; 2672 2673 if (rmem->flags & BNXT_RMEM_USE_FULL_PAGE_FLAG) 2674 pg_tbl_size = rmem->page_size; 2675 rmem->pg_tbl = dma_alloc_coherent(&pdev->dev, pg_tbl_size, 2676 &rmem->pg_tbl_map, 2677 GFP_KERNEL); 2678 if (!rmem->pg_tbl) 2679 return -ENOMEM; 2680 } 2681 2682 for (i = 0; i < rmem->nr_pages; i++) { 2683 u64 extra_bits = valid_bit; 2684 2685 rmem->pg_arr[i] = dma_alloc_coherent(&pdev->dev, 2686 rmem->page_size, 2687 &rmem->dma_arr[i], 2688 GFP_KERNEL); 2689 if (!rmem->pg_arr[i]) 2690 return -ENOMEM; 2691 2692 if (rmem->init_val) 2693 memset(rmem->pg_arr[i], rmem->init_val, 2694 rmem->page_size); 2695 if (rmem->nr_pages > 1 || rmem->depth > 0) { 2696 if (i == rmem->nr_pages - 2 && 2697 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG)) 2698 extra_bits |= PTU_PTE_NEXT_TO_LAST; 2699 else if (i == rmem->nr_pages - 1 && 2700 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG)) 2701 extra_bits |= PTU_PTE_LAST; 2702 rmem->pg_tbl[i] = 2703 cpu_to_le64(rmem->dma_arr[i] | extra_bits); 2704 } 2705 } 2706 2707 if (rmem->vmem_size) { 2708 *rmem->vmem = vzalloc(rmem->vmem_size); 2709 if (!(*rmem->vmem)) 2710 return -ENOMEM; 2711 } 2712 return 0; 2713 } 2714 2715 static void bnxt_free_tpa_info(struct bnxt *bp) 2716 { 2717 int i; 2718 2719 for (i = 0; i < bp->rx_nr_rings; i++) { 2720 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 2721 2722 kfree(rxr->rx_tpa_idx_map); 2723 rxr->rx_tpa_idx_map = NULL; 2724 if (rxr->rx_tpa) { 2725 kfree(rxr->rx_tpa[0].agg_arr); 2726 rxr->rx_tpa[0].agg_arr = NULL; 2727 } 2728 kfree(rxr->rx_tpa); 2729 rxr->rx_tpa = NULL; 2730 } 2731 } 2732 2733 static int bnxt_alloc_tpa_info(struct bnxt *bp) 2734 { 2735 int i, j, total_aggs = 0; 2736 2737 bp->max_tpa = MAX_TPA; 2738 if (bp->flags & BNXT_FLAG_CHIP_P5) { 2739 if (!bp->max_tpa_v2) 2740 return 0; 2741 bp->max_tpa = max_t(u16, bp->max_tpa_v2, MAX_TPA_P5); 2742 total_aggs = bp->max_tpa * MAX_SKB_FRAGS; 2743 } 2744 2745 for (i = 0; i < bp->rx_nr_rings; i++) { 2746 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 2747 struct rx_agg_cmp *agg; 2748 2749 rxr->rx_tpa = kcalloc(bp->max_tpa, sizeof(struct bnxt_tpa_info), 2750 GFP_KERNEL); 2751 if (!rxr->rx_tpa) 2752 return -ENOMEM; 2753 2754 if (!(bp->flags & BNXT_FLAG_CHIP_P5)) 2755 continue; 2756 agg = kcalloc(total_aggs, sizeof(*agg), GFP_KERNEL); 2757 rxr->rx_tpa[0].agg_arr = agg; 2758 if (!agg) 2759 return -ENOMEM; 2760 for (j = 1; j < bp->max_tpa; j++) 2761 rxr->rx_tpa[j].agg_arr = agg + j * MAX_SKB_FRAGS; 2762 rxr->rx_tpa_idx_map = kzalloc(sizeof(*rxr->rx_tpa_idx_map), 2763 GFP_KERNEL); 2764 if (!rxr->rx_tpa_idx_map) 2765 return -ENOMEM; 2766 } 2767 return 0; 2768 } 2769 2770 static void bnxt_free_rx_rings(struct bnxt *bp) 2771 { 2772 int i; 2773 2774 if (!bp->rx_ring) 2775 return; 2776 2777 bnxt_free_tpa_info(bp); 2778 for (i = 0; i < bp->rx_nr_rings; i++) { 2779 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 2780 struct bnxt_ring_struct *ring; 2781 2782 if (rxr->xdp_prog) 2783 bpf_prog_put(rxr->xdp_prog); 2784 2785 if (xdp_rxq_info_is_reg(&rxr->xdp_rxq)) 2786 xdp_rxq_info_unreg(&rxr->xdp_rxq); 2787 2788 page_pool_destroy(rxr->page_pool); 2789 rxr->page_pool = NULL; 2790 2791 kfree(rxr->rx_agg_bmap); 2792 rxr->rx_agg_bmap = NULL; 2793 2794 ring = &rxr->rx_ring_struct; 2795 bnxt_free_ring(bp, &ring->ring_mem); 2796 2797 ring = &rxr->rx_agg_ring_struct; 2798 bnxt_free_ring(bp, &ring->ring_mem); 2799 } 2800 } 2801 2802 static int bnxt_alloc_rx_page_pool(struct bnxt *bp, 2803 struct bnxt_rx_ring_info *rxr) 2804 { 2805 struct page_pool_params pp = { 0 }; 2806 2807 pp.pool_size = bp->rx_ring_size; 2808 pp.nid = dev_to_node(&bp->pdev->dev); 2809 pp.dev = &bp->pdev->dev; 2810 pp.dma_dir = DMA_BIDIRECTIONAL; 2811 2812 rxr->page_pool = page_pool_create(&pp); 2813 if (IS_ERR(rxr->page_pool)) { 2814 int err = PTR_ERR(rxr->page_pool); 2815 2816 rxr->page_pool = NULL; 2817 return err; 2818 } 2819 return 0; 2820 } 2821 2822 static int bnxt_alloc_rx_rings(struct bnxt *bp) 2823 { 2824 int i, rc = 0, agg_rings = 0; 2825 2826 if (!bp->rx_ring) 2827 return -ENOMEM; 2828 2829 if (bp->flags & BNXT_FLAG_AGG_RINGS) 2830 agg_rings = 1; 2831 2832 for (i = 0; i < bp->rx_nr_rings; i++) { 2833 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 2834 struct bnxt_ring_struct *ring; 2835 2836 ring = &rxr->rx_ring_struct; 2837 2838 rc = bnxt_alloc_rx_page_pool(bp, rxr); 2839 if (rc) 2840 return rc; 2841 2842 rc = xdp_rxq_info_reg(&rxr->xdp_rxq, bp->dev, i); 2843 if (rc < 0) 2844 return rc; 2845 2846 rc = xdp_rxq_info_reg_mem_model(&rxr->xdp_rxq, 2847 MEM_TYPE_PAGE_POOL, 2848 rxr->page_pool); 2849 if (rc) { 2850 xdp_rxq_info_unreg(&rxr->xdp_rxq); 2851 return rc; 2852 } 2853 2854 rc = bnxt_alloc_ring(bp, &ring->ring_mem); 2855 if (rc) 2856 return rc; 2857 2858 ring->grp_idx = i; 2859 if (agg_rings) { 2860 u16 mem_size; 2861 2862 ring = &rxr->rx_agg_ring_struct; 2863 rc = bnxt_alloc_ring(bp, &ring->ring_mem); 2864 if (rc) 2865 return rc; 2866 2867 ring->grp_idx = i; 2868 rxr->rx_agg_bmap_size = bp->rx_agg_ring_mask + 1; 2869 mem_size = rxr->rx_agg_bmap_size / 8; 2870 rxr->rx_agg_bmap = kzalloc(mem_size, GFP_KERNEL); 2871 if (!rxr->rx_agg_bmap) 2872 return -ENOMEM; 2873 } 2874 } 2875 if (bp->flags & BNXT_FLAG_TPA) 2876 rc = bnxt_alloc_tpa_info(bp); 2877 return rc; 2878 } 2879 2880 static void bnxt_free_tx_rings(struct bnxt *bp) 2881 { 2882 int i; 2883 struct pci_dev *pdev = bp->pdev; 2884 2885 if (!bp->tx_ring) 2886 return; 2887 2888 for (i = 0; i < bp->tx_nr_rings; i++) { 2889 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; 2890 struct bnxt_ring_struct *ring; 2891 2892 if (txr->tx_push) { 2893 dma_free_coherent(&pdev->dev, bp->tx_push_size, 2894 txr->tx_push, txr->tx_push_mapping); 2895 txr->tx_push = NULL; 2896 } 2897 2898 ring = &txr->tx_ring_struct; 2899 2900 bnxt_free_ring(bp, &ring->ring_mem); 2901 } 2902 } 2903 2904 static int bnxt_alloc_tx_rings(struct bnxt *bp) 2905 { 2906 int i, j, rc; 2907 struct pci_dev *pdev = bp->pdev; 2908 2909 bp->tx_push_size = 0; 2910 if (bp->tx_push_thresh) { 2911 int push_size; 2912 2913 push_size = L1_CACHE_ALIGN(sizeof(struct tx_push_bd) + 2914 bp->tx_push_thresh); 2915 2916 if (push_size > 256) { 2917 push_size = 0; 2918 bp->tx_push_thresh = 0; 2919 } 2920 2921 bp->tx_push_size = push_size; 2922 } 2923 2924 for (i = 0, j = 0; i < bp->tx_nr_rings; i++) { 2925 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; 2926 struct bnxt_ring_struct *ring; 2927 u8 qidx; 2928 2929 ring = &txr->tx_ring_struct; 2930 2931 rc = bnxt_alloc_ring(bp, &ring->ring_mem); 2932 if (rc) 2933 return rc; 2934 2935 ring->grp_idx = txr->bnapi->index; 2936 if (bp->tx_push_size) { 2937 dma_addr_t mapping; 2938 2939 /* One pre-allocated DMA buffer to backup 2940 * TX push operation 2941 */ 2942 txr->tx_push = dma_alloc_coherent(&pdev->dev, 2943 bp->tx_push_size, 2944 &txr->tx_push_mapping, 2945 GFP_KERNEL); 2946 2947 if (!txr->tx_push) 2948 return -ENOMEM; 2949 2950 mapping = txr->tx_push_mapping + 2951 sizeof(struct tx_push_bd); 2952 txr->data_mapping = cpu_to_le64(mapping); 2953 } 2954 qidx = bp->tc_to_qidx[j]; 2955 ring->queue_id = bp->q_info[qidx].queue_id; 2956 if (i < bp->tx_nr_rings_xdp) 2957 continue; 2958 if (i % bp->tx_nr_rings_per_tc == (bp->tx_nr_rings_per_tc - 1)) 2959 j++; 2960 } 2961 return 0; 2962 } 2963 2964 static void bnxt_free_cp_rings(struct bnxt *bp) 2965 { 2966 int i; 2967 2968 if (!bp->bnapi) 2969 return; 2970 2971 for (i = 0; i < bp->cp_nr_rings; i++) { 2972 struct bnxt_napi *bnapi = bp->bnapi[i]; 2973 struct bnxt_cp_ring_info *cpr; 2974 struct bnxt_ring_struct *ring; 2975 int j; 2976 2977 if (!bnapi) 2978 continue; 2979 2980 cpr = &bnapi->cp_ring; 2981 ring = &cpr->cp_ring_struct; 2982 2983 bnxt_free_ring(bp, &ring->ring_mem); 2984 2985 for (j = 0; j < 2; j++) { 2986 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j]; 2987 2988 if (cpr2) { 2989 ring = &cpr2->cp_ring_struct; 2990 bnxt_free_ring(bp, &ring->ring_mem); 2991 kfree(cpr2); 2992 cpr->cp_ring_arr[j] = NULL; 2993 } 2994 } 2995 } 2996 } 2997 2998 static struct bnxt_cp_ring_info *bnxt_alloc_cp_sub_ring(struct bnxt *bp) 2999 { 3000 struct bnxt_ring_mem_info *rmem; 3001 struct bnxt_ring_struct *ring; 3002 struct bnxt_cp_ring_info *cpr; 3003 int rc; 3004 3005 cpr = kzalloc(sizeof(*cpr), GFP_KERNEL); 3006 if (!cpr) 3007 return NULL; 3008 3009 ring = &cpr->cp_ring_struct; 3010 rmem = &ring->ring_mem; 3011 rmem->nr_pages = bp->cp_nr_pages; 3012 rmem->page_size = HW_CMPD_RING_SIZE; 3013 rmem->pg_arr = (void **)cpr->cp_desc_ring; 3014 rmem->dma_arr = cpr->cp_desc_mapping; 3015 rmem->flags = BNXT_RMEM_RING_PTE_FLAG; 3016 rc = bnxt_alloc_ring(bp, rmem); 3017 if (rc) { 3018 bnxt_free_ring(bp, rmem); 3019 kfree(cpr); 3020 cpr = NULL; 3021 } 3022 return cpr; 3023 } 3024 3025 static int bnxt_alloc_cp_rings(struct bnxt *bp) 3026 { 3027 bool sh = !!(bp->flags & BNXT_FLAG_SHARED_RINGS); 3028 int i, rc, ulp_base_vec, ulp_msix; 3029 3030 ulp_msix = bnxt_get_ulp_msix_num(bp); 3031 ulp_base_vec = bnxt_get_ulp_msix_base(bp); 3032 for (i = 0; i < bp->cp_nr_rings; i++) { 3033 struct bnxt_napi *bnapi = bp->bnapi[i]; 3034 struct bnxt_cp_ring_info *cpr; 3035 struct bnxt_ring_struct *ring; 3036 3037 if (!bnapi) 3038 continue; 3039 3040 cpr = &bnapi->cp_ring; 3041 cpr->bnapi = bnapi; 3042 ring = &cpr->cp_ring_struct; 3043 3044 rc = bnxt_alloc_ring(bp, &ring->ring_mem); 3045 if (rc) 3046 return rc; 3047 3048 if (ulp_msix && i >= ulp_base_vec) 3049 ring->map_idx = i + ulp_msix; 3050 else 3051 ring->map_idx = i; 3052 3053 if (!(bp->flags & BNXT_FLAG_CHIP_P5)) 3054 continue; 3055 3056 if (i < bp->rx_nr_rings) { 3057 struct bnxt_cp_ring_info *cpr2 = 3058 bnxt_alloc_cp_sub_ring(bp); 3059 3060 cpr->cp_ring_arr[BNXT_RX_HDL] = cpr2; 3061 if (!cpr2) 3062 return -ENOMEM; 3063 cpr2->bnapi = bnapi; 3064 } 3065 if ((sh && i < bp->tx_nr_rings) || 3066 (!sh && i >= bp->rx_nr_rings)) { 3067 struct bnxt_cp_ring_info *cpr2 = 3068 bnxt_alloc_cp_sub_ring(bp); 3069 3070 cpr->cp_ring_arr[BNXT_TX_HDL] = cpr2; 3071 if (!cpr2) 3072 return -ENOMEM; 3073 cpr2->bnapi = bnapi; 3074 } 3075 } 3076 return 0; 3077 } 3078 3079 static void bnxt_init_ring_struct(struct bnxt *bp) 3080 { 3081 int i; 3082 3083 for (i = 0; i < bp->cp_nr_rings; i++) { 3084 struct bnxt_napi *bnapi = bp->bnapi[i]; 3085 struct bnxt_ring_mem_info *rmem; 3086 struct bnxt_cp_ring_info *cpr; 3087 struct bnxt_rx_ring_info *rxr; 3088 struct bnxt_tx_ring_info *txr; 3089 struct bnxt_ring_struct *ring; 3090 3091 if (!bnapi) 3092 continue; 3093 3094 cpr = &bnapi->cp_ring; 3095 ring = &cpr->cp_ring_struct; 3096 rmem = &ring->ring_mem; 3097 rmem->nr_pages = bp->cp_nr_pages; 3098 rmem->page_size = HW_CMPD_RING_SIZE; 3099 rmem->pg_arr = (void **)cpr->cp_desc_ring; 3100 rmem->dma_arr = cpr->cp_desc_mapping; 3101 rmem->vmem_size = 0; 3102 3103 rxr = bnapi->rx_ring; 3104 if (!rxr) 3105 goto skip_rx; 3106 3107 ring = &rxr->rx_ring_struct; 3108 rmem = &ring->ring_mem; 3109 rmem->nr_pages = bp->rx_nr_pages; 3110 rmem->page_size = HW_RXBD_RING_SIZE; 3111 rmem->pg_arr = (void **)rxr->rx_desc_ring; 3112 rmem->dma_arr = rxr->rx_desc_mapping; 3113 rmem->vmem_size = SW_RXBD_RING_SIZE * bp->rx_nr_pages; 3114 rmem->vmem = (void **)&rxr->rx_buf_ring; 3115 3116 ring = &rxr->rx_agg_ring_struct; 3117 rmem = &ring->ring_mem; 3118 rmem->nr_pages = bp->rx_agg_nr_pages; 3119 rmem->page_size = HW_RXBD_RING_SIZE; 3120 rmem->pg_arr = (void **)rxr->rx_agg_desc_ring; 3121 rmem->dma_arr = rxr->rx_agg_desc_mapping; 3122 rmem->vmem_size = SW_RXBD_AGG_RING_SIZE * bp->rx_agg_nr_pages; 3123 rmem->vmem = (void **)&rxr->rx_agg_ring; 3124 3125 skip_rx: 3126 txr = bnapi->tx_ring; 3127 if (!txr) 3128 continue; 3129 3130 ring = &txr->tx_ring_struct; 3131 rmem = &ring->ring_mem; 3132 rmem->nr_pages = bp->tx_nr_pages; 3133 rmem->page_size = HW_RXBD_RING_SIZE; 3134 rmem->pg_arr = (void **)txr->tx_desc_ring; 3135 rmem->dma_arr = txr->tx_desc_mapping; 3136 rmem->vmem_size = SW_TXBD_RING_SIZE * bp->tx_nr_pages; 3137 rmem->vmem = (void **)&txr->tx_buf_ring; 3138 } 3139 } 3140 3141 static void bnxt_init_rxbd_pages(struct bnxt_ring_struct *ring, u32 type) 3142 { 3143 int i; 3144 u32 prod; 3145 struct rx_bd **rx_buf_ring; 3146 3147 rx_buf_ring = (struct rx_bd **)ring->ring_mem.pg_arr; 3148 for (i = 0, prod = 0; i < ring->ring_mem.nr_pages; i++) { 3149 int j; 3150 struct rx_bd *rxbd; 3151 3152 rxbd = rx_buf_ring[i]; 3153 if (!rxbd) 3154 continue; 3155 3156 for (j = 0; j < RX_DESC_CNT; j++, rxbd++, prod++) { 3157 rxbd->rx_bd_len_flags_type = cpu_to_le32(type); 3158 rxbd->rx_bd_opaque = prod; 3159 } 3160 } 3161 } 3162 3163 static int bnxt_init_one_rx_ring(struct bnxt *bp, int ring_nr) 3164 { 3165 struct net_device *dev = bp->dev; 3166 struct bnxt_rx_ring_info *rxr; 3167 struct bnxt_ring_struct *ring; 3168 u32 prod, type; 3169 int i; 3170 3171 type = (bp->rx_buf_use_size << RX_BD_LEN_SHIFT) | 3172 RX_BD_TYPE_RX_PACKET_BD | RX_BD_FLAGS_EOP; 3173 3174 if (NET_IP_ALIGN == 2) 3175 type |= RX_BD_FLAGS_SOP; 3176 3177 rxr = &bp->rx_ring[ring_nr]; 3178 ring = &rxr->rx_ring_struct; 3179 bnxt_init_rxbd_pages(ring, type); 3180 3181 if (BNXT_RX_PAGE_MODE(bp) && bp->xdp_prog) { 3182 bpf_prog_add(bp->xdp_prog, 1); 3183 rxr->xdp_prog = bp->xdp_prog; 3184 } 3185 prod = rxr->rx_prod; 3186 for (i = 0; i < bp->rx_ring_size; i++) { 3187 if (bnxt_alloc_rx_data(bp, rxr, prod, GFP_KERNEL) != 0) { 3188 netdev_warn(dev, "init'ed rx ring %d with %d/%d skbs only\n", 3189 ring_nr, i, bp->rx_ring_size); 3190 break; 3191 } 3192 prod = NEXT_RX(prod); 3193 } 3194 rxr->rx_prod = prod; 3195 ring->fw_ring_id = INVALID_HW_RING_ID; 3196 3197 ring = &rxr->rx_agg_ring_struct; 3198 ring->fw_ring_id = INVALID_HW_RING_ID; 3199 3200 if (!(bp->flags & BNXT_FLAG_AGG_RINGS)) 3201 return 0; 3202 3203 type = ((u32)BNXT_RX_PAGE_SIZE << RX_BD_LEN_SHIFT) | 3204 RX_BD_TYPE_RX_AGG_BD | RX_BD_FLAGS_SOP; 3205 3206 bnxt_init_rxbd_pages(ring, type); 3207 3208 prod = rxr->rx_agg_prod; 3209 for (i = 0; i < bp->rx_agg_ring_size; i++) { 3210 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_KERNEL) != 0) { 3211 netdev_warn(dev, "init'ed rx ring %d with %d/%d pages only\n", 3212 ring_nr, i, bp->rx_ring_size); 3213 break; 3214 } 3215 prod = NEXT_RX_AGG(prod); 3216 } 3217 rxr->rx_agg_prod = prod; 3218 3219 if (bp->flags & BNXT_FLAG_TPA) { 3220 if (rxr->rx_tpa) { 3221 u8 *data; 3222 dma_addr_t mapping; 3223 3224 for (i = 0; i < bp->max_tpa; i++) { 3225 data = __bnxt_alloc_rx_data(bp, &mapping, 3226 GFP_KERNEL); 3227 if (!data) 3228 return -ENOMEM; 3229 3230 rxr->rx_tpa[i].data = data; 3231 rxr->rx_tpa[i].data_ptr = data + bp->rx_offset; 3232 rxr->rx_tpa[i].mapping = mapping; 3233 } 3234 } else { 3235 netdev_err(bp->dev, "No resource allocated for LRO/GRO\n"); 3236 return -ENOMEM; 3237 } 3238 } 3239 3240 return 0; 3241 } 3242 3243 static void bnxt_init_cp_rings(struct bnxt *bp) 3244 { 3245 int i, j; 3246 3247 for (i = 0; i < bp->cp_nr_rings; i++) { 3248 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring; 3249 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct; 3250 3251 ring->fw_ring_id = INVALID_HW_RING_ID; 3252 cpr->rx_ring_coal.coal_ticks = bp->rx_coal.coal_ticks; 3253 cpr->rx_ring_coal.coal_bufs = bp->rx_coal.coal_bufs; 3254 for (j = 0; j < 2; j++) { 3255 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j]; 3256 3257 if (!cpr2) 3258 continue; 3259 3260 ring = &cpr2->cp_ring_struct; 3261 ring->fw_ring_id = INVALID_HW_RING_ID; 3262 cpr2->rx_ring_coal.coal_ticks = bp->rx_coal.coal_ticks; 3263 cpr2->rx_ring_coal.coal_bufs = bp->rx_coal.coal_bufs; 3264 } 3265 } 3266 } 3267 3268 static int bnxt_init_rx_rings(struct bnxt *bp) 3269 { 3270 int i, rc = 0; 3271 3272 if (BNXT_RX_PAGE_MODE(bp)) { 3273 bp->rx_offset = NET_IP_ALIGN + XDP_PACKET_HEADROOM; 3274 bp->rx_dma_offset = XDP_PACKET_HEADROOM; 3275 } else { 3276 bp->rx_offset = BNXT_RX_OFFSET; 3277 bp->rx_dma_offset = BNXT_RX_DMA_OFFSET; 3278 } 3279 3280 for (i = 0; i < bp->rx_nr_rings; i++) { 3281 rc = bnxt_init_one_rx_ring(bp, i); 3282 if (rc) 3283 break; 3284 } 3285 3286 return rc; 3287 } 3288 3289 static int bnxt_init_tx_rings(struct bnxt *bp) 3290 { 3291 u16 i; 3292 3293 bp->tx_wake_thresh = max_t(int, bp->tx_ring_size / 2, 3294 MAX_SKB_FRAGS + 1); 3295 3296 for (i = 0; i < bp->tx_nr_rings; i++) { 3297 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; 3298 struct bnxt_ring_struct *ring = &txr->tx_ring_struct; 3299 3300 ring->fw_ring_id = INVALID_HW_RING_ID; 3301 } 3302 3303 return 0; 3304 } 3305 3306 static void bnxt_free_ring_grps(struct bnxt *bp) 3307 { 3308 kfree(bp->grp_info); 3309 bp->grp_info = NULL; 3310 } 3311 3312 static int bnxt_init_ring_grps(struct bnxt *bp, bool irq_re_init) 3313 { 3314 int i; 3315 3316 if (irq_re_init) { 3317 bp->grp_info = kcalloc(bp->cp_nr_rings, 3318 sizeof(struct bnxt_ring_grp_info), 3319 GFP_KERNEL); 3320 if (!bp->grp_info) 3321 return -ENOMEM; 3322 } 3323 for (i = 0; i < bp->cp_nr_rings; i++) { 3324 if (irq_re_init) 3325 bp->grp_info[i].fw_stats_ctx = INVALID_HW_RING_ID; 3326 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID; 3327 bp->grp_info[i].rx_fw_ring_id = INVALID_HW_RING_ID; 3328 bp->grp_info[i].agg_fw_ring_id = INVALID_HW_RING_ID; 3329 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID; 3330 } 3331 return 0; 3332 } 3333 3334 static void bnxt_free_vnics(struct bnxt *bp) 3335 { 3336 kfree(bp->vnic_info); 3337 bp->vnic_info = NULL; 3338 bp->nr_vnics = 0; 3339 } 3340 3341 static int bnxt_alloc_vnics(struct bnxt *bp) 3342 { 3343 int num_vnics = 1; 3344 3345 #ifdef CONFIG_RFS_ACCEL 3346 if ((bp->flags & (BNXT_FLAG_RFS | BNXT_FLAG_CHIP_P5)) == BNXT_FLAG_RFS) 3347 num_vnics += bp->rx_nr_rings; 3348 #endif 3349 3350 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 3351 num_vnics++; 3352 3353 bp->vnic_info = kcalloc(num_vnics, sizeof(struct bnxt_vnic_info), 3354 GFP_KERNEL); 3355 if (!bp->vnic_info) 3356 return -ENOMEM; 3357 3358 bp->nr_vnics = num_vnics; 3359 return 0; 3360 } 3361 3362 static void bnxt_init_vnics(struct bnxt *bp) 3363 { 3364 int i; 3365 3366 for (i = 0; i < bp->nr_vnics; i++) { 3367 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 3368 int j; 3369 3370 vnic->fw_vnic_id = INVALID_HW_RING_ID; 3371 for (j = 0; j < BNXT_MAX_CTX_PER_VNIC; j++) 3372 vnic->fw_rss_cos_lb_ctx[j] = INVALID_HW_RING_ID; 3373 3374 vnic->fw_l2_ctx_id = INVALID_HW_RING_ID; 3375 3376 if (bp->vnic_info[i].rss_hash_key) { 3377 if (i == 0) 3378 prandom_bytes(vnic->rss_hash_key, 3379 HW_HASH_KEY_SIZE); 3380 else 3381 memcpy(vnic->rss_hash_key, 3382 bp->vnic_info[0].rss_hash_key, 3383 HW_HASH_KEY_SIZE); 3384 } 3385 } 3386 } 3387 3388 static int bnxt_calc_nr_ring_pages(u32 ring_size, int desc_per_pg) 3389 { 3390 int pages; 3391 3392 pages = ring_size / desc_per_pg; 3393 3394 if (!pages) 3395 return 1; 3396 3397 pages++; 3398 3399 while (pages & (pages - 1)) 3400 pages++; 3401 3402 return pages; 3403 } 3404 3405 void bnxt_set_tpa_flags(struct bnxt *bp) 3406 { 3407 bp->flags &= ~BNXT_FLAG_TPA; 3408 if (bp->flags & BNXT_FLAG_NO_AGG_RINGS) 3409 return; 3410 if (bp->dev->features & NETIF_F_LRO) 3411 bp->flags |= BNXT_FLAG_LRO; 3412 else if (bp->dev->features & NETIF_F_GRO_HW) 3413 bp->flags |= BNXT_FLAG_GRO; 3414 } 3415 3416 /* bp->rx_ring_size, bp->tx_ring_size, dev->mtu, BNXT_FLAG_{G|L}RO flags must 3417 * be set on entry. 3418 */ 3419 void bnxt_set_ring_params(struct bnxt *bp) 3420 { 3421 u32 ring_size, rx_size, rx_space; 3422 u32 agg_factor = 0, agg_ring_size = 0; 3423 3424 /* 8 for CRC and VLAN */ 3425 rx_size = SKB_DATA_ALIGN(bp->dev->mtu + ETH_HLEN + NET_IP_ALIGN + 8); 3426 3427 rx_space = rx_size + NET_SKB_PAD + 3428 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 3429 3430 bp->rx_copy_thresh = BNXT_RX_COPY_THRESH; 3431 ring_size = bp->rx_ring_size; 3432 bp->rx_agg_ring_size = 0; 3433 bp->rx_agg_nr_pages = 0; 3434 3435 if (bp->flags & BNXT_FLAG_TPA) 3436 agg_factor = min_t(u32, 4, 65536 / BNXT_RX_PAGE_SIZE); 3437 3438 bp->flags &= ~BNXT_FLAG_JUMBO; 3439 if (rx_space > PAGE_SIZE && !(bp->flags & BNXT_FLAG_NO_AGG_RINGS)) { 3440 u32 jumbo_factor; 3441 3442 bp->flags |= BNXT_FLAG_JUMBO; 3443 jumbo_factor = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT; 3444 if (jumbo_factor > agg_factor) 3445 agg_factor = jumbo_factor; 3446 } 3447 agg_ring_size = ring_size * agg_factor; 3448 3449 if (agg_ring_size) { 3450 bp->rx_agg_nr_pages = bnxt_calc_nr_ring_pages(agg_ring_size, 3451 RX_DESC_CNT); 3452 if (bp->rx_agg_nr_pages > MAX_RX_AGG_PAGES) { 3453 u32 tmp = agg_ring_size; 3454 3455 bp->rx_agg_nr_pages = MAX_RX_AGG_PAGES; 3456 agg_ring_size = MAX_RX_AGG_PAGES * RX_DESC_CNT - 1; 3457 netdev_warn(bp->dev, "rx agg ring size %d reduced to %d.\n", 3458 tmp, agg_ring_size); 3459 } 3460 bp->rx_agg_ring_size = agg_ring_size; 3461 bp->rx_agg_ring_mask = (bp->rx_agg_nr_pages * RX_DESC_CNT) - 1; 3462 rx_size = SKB_DATA_ALIGN(BNXT_RX_COPY_THRESH + NET_IP_ALIGN); 3463 rx_space = rx_size + NET_SKB_PAD + 3464 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 3465 } 3466 3467 bp->rx_buf_use_size = rx_size; 3468 bp->rx_buf_size = rx_space; 3469 3470 bp->rx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, RX_DESC_CNT); 3471 bp->rx_ring_mask = (bp->rx_nr_pages * RX_DESC_CNT) - 1; 3472 3473 ring_size = bp->tx_ring_size; 3474 bp->tx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, TX_DESC_CNT); 3475 bp->tx_ring_mask = (bp->tx_nr_pages * TX_DESC_CNT) - 1; 3476 3477 ring_size = bp->rx_ring_size * (2 + agg_factor) + bp->tx_ring_size; 3478 bp->cp_ring_size = ring_size; 3479 3480 bp->cp_nr_pages = bnxt_calc_nr_ring_pages(ring_size, CP_DESC_CNT); 3481 if (bp->cp_nr_pages > MAX_CP_PAGES) { 3482 bp->cp_nr_pages = MAX_CP_PAGES; 3483 bp->cp_ring_size = MAX_CP_PAGES * CP_DESC_CNT - 1; 3484 netdev_warn(bp->dev, "completion ring size %d reduced to %d.\n", 3485 ring_size, bp->cp_ring_size); 3486 } 3487 bp->cp_bit = bp->cp_nr_pages * CP_DESC_CNT; 3488 bp->cp_ring_mask = bp->cp_bit - 1; 3489 } 3490 3491 /* Changing allocation mode of RX rings. 3492 * TODO: Update when extending xdp_rxq_info to support allocation modes. 3493 */ 3494 int bnxt_set_rx_skb_mode(struct bnxt *bp, bool page_mode) 3495 { 3496 if (page_mode) { 3497 if (bp->dev->mtu > BNXT_MAX_PAGE_MODE_MTU) 3498 return -EOPNOTSUPP; 3499 bp->dev->max_mtu = 3500 min_t(u16, bp->max_mtu, BNXT_MAX_PAGE_MODE_MTU); 3501 bp->flags &= ~BNXT_FLAG_AGG_RINGS; 3502 bp->flags |= BNXT_FLAG_NO_AGG_RINGS | BNXT_FLAG_RX_PAGE_MODE; 3503 bp->rx_dir = DMA_BIDIRECTIONAL; 3504 bp->rx_skb_func = bnxt_rx_page_skb; 3505 /* Disable LRO or GRO_HW */ 3506 netdev_update_features(bp->dev); 3507 } else { 3508 bp->dev->max_mtu = bp->max_mtu; 3509 bp->flags &= ~BNXT_FLAG_RX_PAGE_MODE; 3510 bp->rx_dir = DMA_FROM_DEVICE; 3511 bp->rx_skb_func = bnxt_rx_skb; 3512 } 3513 return 0; 3514 } 3515 3516 static void bnxt_free_vnic_attributes(struct bnxt *bp) 3517 { 3518 int i; 3519 struct bnxt_vnic_info *vnic; 3520 struct pci_dev *pdev = bp->pdev; 3521 3522 if (!bp->vnic_info) 3523 return; 3524 3525 for (i = 0; i < bp->nr_vnics; i++) { 3526 vnic = &bp->vnic_info[i]; 3527 3528 kfree(vnic->fw_grp_ids); 3529 vnic->fw_grp_ids = NULL; 3530 3531 kfree(vnic->uc_list); 3532 vnic->uc_list = NULL; 3533 3534 if (vnic->mc_list) { 3535 dma_free_coherent(&pdev->dev, vnic->mc_list_size, 3536 vnic->mc_list, vnic->mc_list_mapping); 3537 vnic->mc_list = NULL; 3538 } 3539 3540 if (vnic->rss_table) { 3541 dma_free_coherent(&pdev->dev, vnic->rss_table_size, 3542 vnic->rss_table, 3543 vnic->rss_table_dma_addr); 3544 vnic->rss_table = NULL; 3545 } 3546 3547 vnic->rss_hash_key = NULL; 3548 vnic->flags = 0; 3549 } 3550 } 3551 3552 static int bnxt_alloc_vnic_attributes(struct bnxt *bp) 3553 { 3554 int i, rc = 0, size; 3555 struct bnxt_vnic_info *vnic; 3556 struct pci_dev *pdev = bp->pdev; 3557 int max_rings; 3558 3559 for (i = 0; i < bp->nr_vnics; i++) { 3560 vnic = &bp->vnic_info[i]; 3561 3562 if (vnic->flags & BNXT_VNIC_UCAST_FLAG) { 3563 int mem_size = (BNXT_MAX_UC_ADDRS - 1) * ETH_ALEN; 3564 3565 if (mem_size > 0) { 3566 vnic->uc_list = kmalloc(mem_size, GFP_KERNEL); 3567 if (!vnic->uc_list) { 3568 rc = -ENOMEM; 3569 goto out; 3570 } 3571 } 3572 } 3573 3574 if (vnic->flags & BNXT_VNIC_MCAST_FLAG) { 3575 vnic->mc_list_size = BNXT_MAX_MC_ADDRS * ETH_ALEN; 3576 vnic->mc_list = 3577 dma_alloc_coherent(&pdev->dev, 3578 vnic->mc_list_size, 3579 &vnic->mc_list_mapping, 3580 GFP_KERNEL); 3581 if (!vnic->mc_list) { 3582 rc = -ENOMEM; 3583 goto out; 3584 } 3585 } 3586 3587 if (bp->flags & BNXT_FLAG_CHIP_P5) 3588 goto vnic_skip_grps; 3589 3590 if (vnic->flags & BNXT_VNIC_RSS_FLAG) 3591 max_rings = bp->rx_nr_rings; 3592 else 3593 max_rings = 1; 3594 3595 vnic->fw_grp_ids = kcalloc(max_rings, sizeof(u16), GFP_KERNEL); 3596 if (!vnic->fw_grp_ids) { 3597 rc = -ENOMEM; 3598 goto out; 3599 } 3600 vnic_skip_grps: 3601 if ((bp->flags & BNXT_FLAG_NEW_RSS_CAP) && 3602 !(vnic->flags & BNXT_VNIC_RSS_FLAG)) 3603 continue; 3604 3605 /* Allocate rss table and hash key */ 3606 size = L1_CACHE_ALIGN(HW_HASH_INDEX_SIZE * sizeof(u16)); 3607 if (bp->flags & BNXT_FLAG_CHIP_P5) 3608 size = L1_CACHE_ALIGN(BNXT_MAX_RSS_TABLE_SIZE_P5); 3609 3610 vnic->rss_table_size = size + HW_HASH_KEY_SIZE; 3611 vnic->rss_table = dma_alloc_coherent(&pdev->dev, 3612 vnic->rss_table_size, 3613 &vnic->rss_table_dma_addr, 3614 GFP_KERNEL); 3615 if (!vnic->rss_table) { 3616 rc = -ENOMEM; 3617 goto out; 3618 } 3619 3620 vnic->rss_hash_key = ((void *)vnic->rss_table) + size; 3621 vnic->rss_hash_key_dma_addr = vnic->rss_table_dma_addr + size; 3622 } 3623 return 0; 3624 3625 out: 3626 return rc; 3627 } 3628 3629 static void bnxt_free_hwrm_resources(struct bnxt *bp) 3630 { 3631 struct pci_dev *pdev = bp->pdev; 3632 3633 if (bp->hwrm_cmd_resp_addr) { 3634 dma_free_coherent(&pdev->dev, PAGE_SIZE, bp->hwrm_cmd_resp_addr, 3635 bp->hwrm_cmd_resp_dma_addr); 3636 bp->hwrm_cmd_resp_addr = NULL; 3637 } 3638 3639 if (bp->hwrm_cmd_kong_resp_addr) { 3640 dma_free_coherent(&pdev->dev, PAGE_SIZE, 3641 bp->hwrm_cmd_kong_resp_addr, 3642 bp->hwrm_cmd_kong_resp_dma_addr); 3643 bp->hwrm_cmd_kong_resp_addr = NULL; 3644 } 3645 } 3646 3647 static int bnxt_alloc_kong_hwrm_resources(struct bnxt *bp) 3648 { 3649 struct pci_dev *pdev = bp->pdev; 3650 3651 if (bp->hwrm_cmd_kong_resp_addr) 3652 return 0; 3653 3654 bp->hwrm_cmd_kong_resp_addr = 3655 dma_alloc_coherent(&pdev->dev, PAGE_SIZE, 3656 &bp->hwrm_cmd_kong_resp_dma_addr, 3657 GFP_KERNEL); 3658 if (!bp->hwrm_cmd_kong_resp_addr) 3659 return -ENOMEM; 3660 3661 return 0; 3662 } 3663 3664 static int bnxt_alloc_hwrm_resources(struct bnxt *bp) 3665 { 3666 struct pci_dev *pdev = bp->pdev; 3667 3668 bp->hwrm_cmd_resp_addr = dma_alloc_coherent(&pdev->dev, PAGE_SIZE, 3669 &bp->hwrm_cmd_resp_dma_addr, 3670 GFP_KERNEL); 3671 if (!bp->hwrm_cmd_resp_addr) 3672 return -ENOMEM; 3673 3674 return 0; 3675 } 3676 3677 static void bnxt_free_hwrm_short_cmd_req(struct bnxt *bp) 3678 { 3679 if (bp->hwrm_short_cmd_req_addr) { 3680 struct pci_dev *pdev = bp->pdev; 3681 3682 dma_free_coherent(&pdev->dev, bp->hwrm_max_ext_req_len, 3683 bp->hwrm_short_cmd_req_addr, 3684 bp->hwrm_short_cmd_req_dma_addr); 3685 bp->hwrm_short_cmd_req_addr = NULL; 3686 } 3687 } 3688 3689 static int bnxt_alloc_hwrm_short_cmd_req(struct bnxt *bp) 3690 { 3691 struct pci_dev *pdev = bp->pdev; 3692 3693 if (bp->hwrm_short_cmd_req_addr) 3694 return 0; 3695 3696 bp->hwrm_short_cmd_req_addr = 3697 dma_alloc_coherent(&pdev->dev, bp->hwrm_max_ext_req_len, 3698 &bp->hwrm_short_cmd_req_dma_addr, 3699 GFP_KERNEL); 3700 if (!bp->hwrm_short_cmd_req_addr) 3701 return -ENOMEM; 3702 3703 return 0; 3704 } 3705 3706 static void bnxt_free_port_stats(struct bnxt *bp) 3707 { 3708 struct pci_dev *pdev = bp->pdev; 3709 3710 bp->flags &= ~BNXT_FLAG_PORT_STATS; 3711 bp->flags &= ~BNXT_FLAG_PORT_STATS_EXT; 3712 3713 if (bp->hw_rx_port_stats) { 3714 dma_free_coherent(&pdev->dev, bp->hw_port_stats_size, 3715 bp->hw_rx_port_stats, 3716 bp->hw_rx_port_stats_map); 3717 bp->hw_rx_port_stats = NULL; 3718 } 3719 3720 if (bp->hw_tx_port_stats_ext) { 3721 dma_free_coherent(&pdev->dev, sizeof(struct tx_port_stats_ext), 3722 bp->hw_tx_port_stats_ext, 3723 bp->hw_tx_port_stats_ext_map); 3724 bp->hw_tx_port_stats_ext = NULL; 3725 } 3726 3727 if (bp->hw_rx_port_stats_ext) { 3728 dma_free_coherent(&pdev->dev, sizeof(struct rx_port_stats_ext), 3729 bp->hw_rx_port_stats_ext, 3730 bp->hw_rx_port_stats_ext_map); 3731 bp->hw_rx_port_stats_ext = NULL; 3732 } 3733 3734 if (bp->hw_pcie_stats) { 3735 dma_free_coherent(&pdev->dev, sizeof(struct pcie_ctx_hw_stats), 3736 bp->hw_pcie_stats, bp->hw_pcie_stats_map); 3737 bp->hw_pcie_stats = NULL; 3738 } 3739 } 3740 3741 static void bnxt_free_ring_stats(struct bnxt *bp) 3742 { 3743 struct pci_dev *pdev = bp->pdev; 3744 int size, i; 3745 3746 if (!bp->bnapi) 3747 return; 3748 3749 size = bp->hw_ring_stats_size; 3750 3751 for (i = 0; i < bp->cp_nr_rings; i++) { 3752 struct bnxt_napi *bnapi = bp->bnapi[i]; 3753 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 3754 3755 if (cpr->hw_stats) { 3756 dma_free_coherent(&pdev->dev, size, cpr->hw_stats, 3757 cpr->hw_stats_map); 3758 cpr->hw_stats = NULL; 3759 } 3760 } 3761 } 3762 3763 static int bnxt_alloc_stats(struct bnxt *bp) 3764 { 3765 u32 size, i; 3766 struct pci_dev *pdev = bp->pdev; 3767 3768 size = bp->hw_ring_stats_size; 3769 3770 for (i = 0; i < bp->cp_nr_rings; i++) { 3771 struct bnxt_napi *bnapi = bp->bnapi[i]; 3772 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 3773 3774 cpr->hw_stats = dma_alloc_coherent(&pdev->dev, size, 3775 &cpr->hw_stats_map, 3776 GFP_KERNEL); 3777 if (!cpr->hw_stats) 3778 return -ENOMEM; 3779 3780 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID; 3781 } 3782 3783 if (BNXT_VF(bp) || bp->chip_num == CHIP_NUM_58700) 3784 return 0; 3785 3786 if (bp->hw_rx_port_stats) 3787 goto alloc_ext_stats; 3788 3789 bp->hw_port_stats_size = sizeof(struct rx_port_stats) + 3790 sizeof(struct tx_port_stats) + 1024; 3791 3792 bp->hw_rx_port_stats = 3793 dma_alloc_coherent(&pdev->dev, bp->hw_port_stats_size, 3794 &bp->hw_rx_port_stats_map, 3795 GFP_KERNEL); 3796 if (!bp->hw_rx_port_stats) 3797 return -ENOMEM; 3798 3799 bp->hw_tx_port_stats = (void *)(bp->hw_rx_port_stats + 1) + 512; 3800 bp->hw_tx_port_stats_map = bp->hw_rx_port_stats_map + 3801 sizeof(struct rx_port_stats) + 512; 3802 bp->flags |= BNXT_FLAG_PORT_STATS; 3803 3804 alloc_ext_stats: 3805 /* Display extended statistics only if FW supports it */ 3806 if (bp->hwrm_spec_code < 0x10804 || bp->hwrm_spec_code == 0x10900) 3807 if (!(bp->fw_cap & BNXT_FW_CAP_EXT_STATS_SUPPORTED)) 3808 return 0; 3809 3810 if (bp->hw_rx_port_stats_ext) 3811 goto alloc_tx_ext_stats; 3812 3813 bp->hw_rx_port_stats_ext = 3814 dma_alloc_coherent(&pdev->dev, sizeof(struct rx_port_stats_ext), 3815 &bp->hw_rx_port_stats_ext_map, GFP_KERNEL); 3816 if (!bp->hw_rx_port_stats_ext) 3817 return 0; 3818 3819 alloc_tx_ext_stats: 3820 if (bp->hw_tx_port_stats_ext) 3821 goto alloc_pcie_stats; 3822 3823 if (bp->hwrm_spec_code >= 0x10902 || 3824 (bp->fw_cap & BNXT_FW_CAP_EXT_STATS_SUPPORTED)) { 3825 bp->hw_tx_port_stats_ext = 3826 dma_alloc_coherent(&pdev->dev, 3827 sizeof(struct tx_port_stats_ext), 3828 &bp->hw_tx_port_stats_ext_map, 3829 GFP_KERNEL); 3830 } 3831 bp->flags |= BNXT_FLAG_PORT_STATS_EXT; 3832 3833 alloc_pcie_stats: 3834 if (bp->hw_pcie_stats || 3835 !(bp->fw_cap & BNXT_FW_CAP_PCIE_STATS_SUPPORTED)) 3836 return 0; 3837 3838 bp->hw_pcie_stats = 3839 dma_alloc_coherent(&pdev->dev, sizeof(struct pcie_ctx_hw_stats), 3840 &bp->hw_pcie_stats_map, GFP_KERNEL); 3841 if (!bp->hw_pcie_stats) 3842 return 0; 3843 3844 bp->flags |= BNXT_FLAG_PCIE_STATS; 3845 return 0; 3846 } 3847 3848 static void bnxt_clear_ring_indices(struct bnxt *bp) 3849 { 3850 int i; 3851 3852 if (!bp->bnapi) 3853 return; 3854 3855 for (i = 0; i < bp->cp_nr_rings; i++) { 3856 struct bnxt_napi *bnapi = bp->bnapi[i]; 3857 struct bnxt_cp_ring_info *cpr; 3858 struct bnxt_rx_ring_info *rxr; 3859 struct bnxt_tx_ring_info *txr; 3860 3861 if (!bnapi) 3862 continue; 3863 3864 cpr = &bnapi->cp_ring; 3865 cpr->cp_raw_cons = 0; 3866 3867 txr = bnapi->tx_ring; 3868 if (txr) { 3869 txr->tx_prod = 0; 3870 txr->tx_cons = 0; 3871 } 3872 3873 rxr = bnapi->rx_ring; 3874 if (rxr) { 3875 rxr->rx_prod = 0; 3876 rxr->rx_agg_prod = 0; 3877 rxr->rx_sw_agg_prod = 0; 3878 rxr->rx_next_cons = 0; 3879 } 3880 } 3881 } 3882 3883 static void bnxt_free_ntp_fltrs(struct bnxt *bp, bool irq_reinit) 3884 { 3885 #ifdef CONFIG_RFS_ACCEL 3886 int i; 3887 3888 /* Under rtnl_lock and all our NAPIs have been disabled. It's 3889 * safe to delete the hash table. 3890 */ 3891 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) { 3892 struct hlist_head *head; 3893 struct hlist_node *tmp; 3894 struct bnxt_ntuple_filter *fltr; 3895 3896 head = &bp->ntp_fltr_hash_tbl[i]; 3897 hlist_for_each_entry_safe(fltr, tmp, head, hash) { 3898 hlist_del(&fltr->hash); 3899 kfree(fltr); 3900 } 3901 } 3902 if (irq_reinit) { 3903 kfree(bp->ntp_fltr_bmap); 3904 bp->ntp_fltr_bmap = NULL; 3905 } 3906 bp->ntp_fltr_count = 0; 3907 #endif 3908 } 3909 3910 static int bnxt_alloc_ntp_fltrs(struct bnxt *bp) 3911 { 3912 #ifdef CONFIG_RFS_ACCEL 3913 int i, rc = 0; 3914 3915 if (!(bp->flags & BNXT_FLAG_RFS)) 3916 return 0; 3917 3918 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) 3919 INIT_HLIST_HEAD(&bp->ntp_fltr_hash_tbl[i]); 3920 3921 bp->ntp_fltr_count = 0; 3922 bp->ntp_fltr_bmap = kcalloc(BITS_TO_LONGS(BNXT_NTP_FLTR_MAX_FLTR), 3923 sizeof(long), 3924 GFP_KERNEL); 3925 3926 if (!bp->ntp_fltr_bmap) 3927 rc = -ENOMEM; 3928 3929 return rc; 3930 #else 3931 return 0; 3932 #endif 3933 } 3934 3935 static void bnxt_free_mem(struct bnxt *bp, bool irq_re_init) 3936 { 3937 bnxt_free_vnic_attributes(bp); 3938 bnxt_free_tx_rings(bp); 3939 bnxt_free_rx_rings(bp); 3940 bnxt_free_cp_rings(bp); 3941 bnxt_free_ntp_fltrs(bp, irq_re_init); 3942 if (irq_re_init) { 3943 bnxt_free_ring_stats(bp); 3944 bnxt_free_ring_grps(bp); 3945 bnxt_free_vnics(bp); 3946 kfree(bp->tx_ring_map); 3947 bp->tx_ring_map = NULL; 3948 kfree(bp->tx_ring); 3949 bp->tx_ring = NULL; 3950 kfree(bp->rx_ring); 3951 bp->rx_ring = NULL; 3952 kfree(bp->bnapi); 3953 bp->bnapi = NULL; 3954 } else { 3955 bnxt_clear_ring_indices(bp); 3956 } 3957 } 3958 3959 static int bnxt_alloc_mem(struct bnxt *bp, bool irq_re_init) 3960 { 3961 int i, j, rc, size, arr_size; 3962 void *bnapi; 3963 3964 if (irq_re_init) { 3965 /* Allocate bnapi mem pointer array and mem block for 3966 * all queues 3967 */ 3968 arr_size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi *) * 3969 bp->cp_nr_rings); 3970 size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi)); 3971 bnapi = kzalloc(arr_size + size * bp->cp_nr_rings, GFP_KERNEL); 3972 if (!bnapi) 3973 return -ENOMEM; 3974 3975 bp->bnapi = bnapi; 3976 bnapi += arr_size; 3977 for (i = 0; i < bp->cp_nr_rings; i++, bnapi += size) { 3978 bp->bnapi[i] = bnapi; 3979 bp->bnapi[i]->index = i; 3980 bp->bnapi[i]->bp = bp; 3981 if (bp->flags & BNXT_FLAG_CHIP_P5) { 3982 struct bnxt_cp_ring_info *cpr = 3983 &bp->bnapi[i]->cp_ring; 3984 3985 cpr->cp_ring_struct.ring_mem.flags = 3986 BNXT_RMEM_RING_PTE_FLAG; 3987 } 3988 } 3989 3990 bp->rx_ring = kcalloc(bp->rx_nr_rings, 3991 sizeof(struct bnxt_rx_ring_info), 3992 GFP_KERNEL); 3993 if (!bp->rx_ring) 3994 return -ENOMEM; 3995 3996 for (i = 0; i < bp->rx_nr_rings; i++) { 3997 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 3998 3999 if (bp->flags & BNXT_FLAG_CHIP_P5) { 4000 rxr->rx_ring_struct.ring_mem.flags = 4001 BNXT_RMEM_RING_PTE_FLAG; 4002 rxr->rx_agg_ring_struct.ring_mem.flags = 4003 BNXT_RMEM_RING_PTE_FLAG; 4004 } 4005 rxr->bnapi = bp->bnapi[i]; 4006 bp->bnapi[i]->rx_ring = &bp->rx_ring[i]; 4007 } 4008 4009 bp->tx_ring = kcalloc(bp->tx_nr_rings, 4010 sizeof(struct bnxt_tx_ring_info), 4011 GFP_KERNEL); 4012 if (!bp->tx_ring) 4013 return -ENOMEM; 4014 4015 bp->tx_ring_map = kcalloc(bp->tx_nr_rings, sizeof(u16), 4016 GFP_KERNEL); 4017 4018 if (!bp->tx_ring_map) 4019 return -ENOMEM; 4020 4021 if (bp->flags & BNXT_FLAG_SHARED_RINGS) 4022 j = 0; 4023 else 4024 j = bp->rx_nr_rings; 4025 4026 for (i = 0; i < bp->tx_nr_rings; i++, j++) { 4027 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; 4028 4029 if (bp->flags & BNXT_FLAG_CHIP_P5) 4030 txr->tx_ring_struct.ring_mem.flags = 4031 BNXT_RMEM_RING_PTE_FLAG; 4032 txr->bnapi = bp->bnapi[j]; 4033 bp->bnapi[j]->tx_ring = txr; 4034 bp->tx_ring_map[i] = bp->tx_nr_rings_xdp + i; 4035 if (i >= bp->tx_nr_rings_xdp) { 4036 txr->txq_index = i - bp->tx_nr_rings_xdp; 4037 bp->bnapi[j]->tx_int = bnxt_tx_int; 4038 } else { 4039 bp->bnapi[j]->flags |= BNXT_NAPI_FLAG_XDP; 4040 bp->bnapi[j]->tx_int = bnxt_tx_int_xdp; 4041 } 4042 } 4043 4044 rc = bnxt_alloc_stats(bp); 4045 if (rc) 4046 goto alloc_mem_err; 4047 4048 rc = bnxt_alloc_ntp_fltrs(bp); 4049 if (rc) 4050 goto alloc_mem_err; 4051 4052 rc = bnxt_alloc_vnics(bp); 4053 if (rc) 4054 goto alloc_mem_err; 4055 } 4056 4057 bnxt_init_ring_struct(bp); 4058 4059 rc = bnxt_alloc_rx_rings(bp); 4060 if (rc) 4061 goto alloc_mem_err; 4062 4063 rc = bnxt_alloc_tx_rings(bp); 4064 if (rc) 4065 goto alloc_mem_err; 4066 4067 rc = bnxt_alloc_cp_rings(bp); 4068 if (rc) 4069 goto alloc_mem_err; 4070 4071 bp->vnic_info[0].flags |= BNXT_VNIC_RSS_FLAG | BNXT_VNIC_MCAST_FLAG | 4072 BNXT_VNIC_UCAST_FLAG; 4073 rc = bnxt_alloc_vnic_attributes(bp); 4074 if (rc) 4075 goto alloc_mem_err; 4076 return 0; 4077 4078 alloc_mem_err: 4079 bnxt_free_mem(bp, true); 4080 return rc; 4081 } 4082 4083 static void bnxt_disable_int(struct bnxt *bp) 4084 { 4085 int i; 4086 4087 if (!bp->bnapi) 4088 return; 4089 4090 for (i = 0; i < bp->cp_nr_rings; i++) { 4091 struct bnxt_napi *bnapi = bp->bnapi[i]; 4092 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 4093 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct; 4094 4095 if (ring->fw_ring_id != INVALID_HW_RING_ID) 4096 bnxt_db_nq(bp, &cpr->cp_db, cpr->cp_raw_cons); 4097 } 4098 } 4099 4100 static int bnxt_cp_num_to_irq_num(struct bnxt *bp, int n) 4101 { 4102 struct bnxt_napi *bnapi = bp->bnapi[n]; 4103 struct bnxt_cp_ring_info *cpr; 4104 4105 cpr = &bnapi->cp_ring; 4106 return cpr->cp_ring_struct.map_idx; 4107 } 4108 4109 static void bnxt_disable_int_sync(struct bnxt *bp) 4110 { 4111 int i; 4112 4113 atomic_inc(&bp->intr_sem); 4114 4115 bnxt_disable_int(bp); 4116 for (i = 0; i < bp->cp_nr_rings; i++) { 4117 int map_idx = bnxt_cp_num_to_irq_num(bp, i); 4118 4119 synchronize_irq(bp->irq_tbl[map_idx].vector); 4120 } 4121 } 4122 4123 static void bnxt_enable_int(struct bnxt *bp) 4124 { 4125 int i; 4126 4127 atomic_set(&bp->intr_sem, 0); 4128 for (i = 0; i < bp->cp_nr_rings; i++) { 4129 struct bnxt_napi *bnapi = bp->bnapi[i]; 4130 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 4131 4132 bnxt_db_nq_arm(bp, &cpr->cp_db, cpr->cp_raw_cons); 4133 } 4134 } 4135 4136 void bnxt_hwrm_cmd_hdr_init(struct bnxt *bp, void *request, u16 req_type, 4137 u16 cmpl_ring, u16 target_id) 4138 { 4139 struct input *req = request; 4140 4141 req->req_type = cpu_to_le16(req_type); 4142 req->cmpl_ring = cpu_to_le16(cmpl_ring); 4143 req->target_id = cpu_to_le16(target_id); 4144 if (bnxt_kong_hwrm_message(bp, req)) 4145 req->resp_addr = cpu_to_le64(bp->hwrm_cmd_kong_resp_dma_addr); 4146 else 4147 req->resp_addr = cpu_to_le64(bp->hwrm_cmd_resp_dma_addr); 4148 } 4149 4150 static int bnxt_hwrm_to_stderr(u32 hwrm_err) 4151 { 4152 switch (hwrm_err) { 4153 case HWRM_ERR_CODE_SUCCESS: 4154 return 0; 4155 case HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED: 4156 return -EACCES; 4157 case HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR: 4158 return -ENOSPC; 4159 case HWRM_ERR_CODE_INVALID_PARAMS: 4160 case HWRM_ERR_CODE_INVALID_FLAGS: 4161 case HWRM_ERR_CODE_INVALID_ENABLES: 4162 case HWRM_ERR_CODE_UNSUPPORTED_TLV: 4163 case HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR: 4164 return -EINVAL; 4165 case HWRM_ERR_CODE_NO_BUFFER: 4166 return -ENOMEM; 4167 case HWRM_ERR_CODE_HOT_RESET_PROGRESS: 4168 case HWRM_ERR_CODE_BUSY: 4169 return -EAGAIN; 4170 case HWRM_ERR_CODE_CMD_NOT_SUPPORTED: 4171 return -EOPNOTSUPP; 4172 default: 4173 return -EIO; 4174 } 4175 } 4176 4177 static int bnxt_hwrm_do_send_msg(struct bnxt *bp, void *msg, u32 msg_len, 4178 int timeout, bool silent) 4179 { 4180 int i, intr_process, rc, tmo_count; 4181 struct input *req = msg; 4182 u32 *data = msg; 4183 u8 *valid; 4184 u16 cp_ring_id, len = 0; 4185 struct hwrm_err_output *resp = bp->hwrm_cmd_resp_addr; 4186 u16 max_req_len = BNXT_HWRM_MAX_REQ_LEN; 4187 struct hwrm_short_input short_input = {0}; 4188 u32 doorbell_offset = BNXT_GRCPF_REG_CHIMP_COMM_TRIGGER; 4189 u32 bar_offset = BNXT_GRCPF_REG_CHIMP_COMM; 4190 u16 dst = BNXT_HWRM_CHNL_CHIMP; 4191 4192 if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state)) 4193 return -EBUSY; 4194 4195 if (msg_len > BNXT_HWRM_MAX_REQ_LEN) { 4196 if (msg_len > bp->hwrm_max_ext_req_len || 4197 !bp->hwrm_short_cmd_req_addr) 4198 return -EINVAL; 4199 } 4200 4201 if (bnxt_hwrm_kong_chnl(bp, req)) { 4202 dst = BNXT_HWRM_CHNL_KONG; 4203 bar_offset = BNXT_GRCPF_REG_KONG_COMM; 4204 doorbell_offset = BNXT_GRCPF_REG_KONG_COMM_TRIGGER; 4205 resp = bp->hwrm_cmd_kong_resp_addr; 4206 } 4207 4208 memset(resp, 0, PAGE_SIZE); 4209 cp_ring_id = le16_to_cpu(req->cmpl_ring); 4210 intr_process = (cp_ring_id == INVALID_HW_RING_ID) ? 0 : 1; 4211 4212 req->seq_id = cpu_to_le16(bnxt_get_hwrm_seq_id(bp, dst)); 4213 /* currently supports only one outstanding message */ 4214 if (intr_process) 4215 bp->hwrm_intr_seq_id = le16_to_cpu(req->seq_id); 4216 4217 if ((bp->fw_cap & BNXT_FW_CAP_SHORT_CMD) || 4218 msg_len > BNXT_HWRM_MAX_REQ_LEN) { 4219 void *short_cmd_req = bp->hwrm_short_cmd_req_addr; 4220 u16 max_msg_len; 4221 4222 /* Set boundary for maximum extended request length for short 4223 * cmd format. If passed up from device use the max supported 4224 * internal req length. 4225 */ 4226 max_msg_len = bp->hwrm_max_ext_req_len; 4227 4228 memcpy(short_cmd_req, req, msg_len); 4229 if (msg_len < max_msg_len) 4230 memset(short_cmd_req + msg_len, 0, 4231 max_msg_len - msg_len); 4232 4233 short_input.req_type = req->req_type; 4234 short_input.signature = 4235 cpu_to_le16(SHORT_REQ_SIGNATURE_SHORT_CMD); 4236 short_input.size = cpu_to_le16(msg_len); 4237 short_input.req_addr = 4238 cpu_to_le64(bp->hwrm_short_cmd_req_dma_addr); 4239 4240 data = (u32 *)&short_input; 4241 msg_len = sizeof(short_input); 4242 4243 /* Sync memory write before updating doorbell */ 4244 wmb(); 4245 4246 max_req_len = BNXT_HWRM_SHORT_REQ_LEN; 4247 } 4248 4249 /* Write request msg to hwrm channel */ 4250 __iowrite32_copy(bp->bar0 + bar_offset, data, msg_len / 4); 4251 4252 for (i = msg_len; i < max_req_len; i += 4) 4253 writel(0, bp->bar0 + bar_offset + i); 4254 4255 /* Ring channel doorbell */ 4256 writel(1, bp->bar0 + doorbell_offset); 4257 4258 if (!pci_is_enabled(bp->pdev)) 4259 return 0; 4260 4261 if (!timeout) 4262 timeout = DFLT_HWRM_CMD_TIMEOUT; 4263 /* convert timeout to usec */ 4264 timeout *= 1000; 4265 4266 i = 0; 4267 /* Short timeout for the first few iterations: 4268 * number of loops = number of loops for short timeout + 4269 * number of loops for standard timeout. 4270 */ 4271 tmo_count = HWRM_SHORT_TIMEOUT_COUNTER; 4272 timeout = timeout - HWRM_SHORT_MIN_TIMEOUT * HWRM_SHORT_TIMEOUT_COUNTER; 4273 tmo_count += DIV_ROUND_UP(timeout, HWRM_MIN_TIMEOUT); 4274 4275 if (intr_process) { 4276 u16 seq_id = bp->hwrm_intr_seq_id; 4277 4278 /* Wait until hwrm response cmpl interrupt is processed */ 4279 while (bp->hwrm_intr_seq_id != (u16)~seq_id && 4280 i++ < tmo_count) { 4281 /* Abort the wait for completion if the FW health 4282 * check has failed. 4283 */ 4284 if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state)) 4285 return -EBUSY; 4286 /* on first few passes, just barely sleep */ 4287 if (i < HWRM_SHORT_TIMEOUT_COUNTER) 4288 usleep_range(HWRM_SHORT_MIN_TIMEOUT, 4289 HWRM_SHORT_MAX_TIMEOUT); 4290 else 4291 usleep_range(HWRM_MIN_TIMEOUT, 4292 HWRM_MAX_TIMEOUT); 4293 } 4294 4295 if (bp->hwrm_intr_seq_id != (u16)~seq_id) { 4296 if (!silent) 4297 netdev_err(bp->dev, "Resp cmpl intr err msg: 0x%x\n", 4298 le16_to_cpu(req->req_type)); 4299 return -EBUSY; 4300 } 4301 len = le16_to_cpu(resp->resp_len); 4302 valid = ((u8 *)resp) + len - 1; 4303 } else { 4304 int j; 4305 4306 /* Check if response len is updated */ 4307 for (i = 0; i < tmo_count; i++) { 4308 /* Abort the wait for completion if the FW health 4309 * check has failed. 4310 */ 4311 if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state)) 4312 return -EBUSY; 4313 len = le16_to_cpu(resp->resp_len); 4314 if (len) 4315 break; 4316 /* on first few passes, just barely sleep */ 4317 if (i < HWRM_SHORT_TIMEOUT_COUNTER) 4318 usleep_range(HWRM_SHORT_MIN_TIMEOUT, 4319 HWRM_SHORT_MAX_TIMEOUT); 4320 else 4321 usleep_range(HWRM_MIN_TIMEOUT, 4322 HWRM_MAX_TIMEOUT); 4323 } 4324 4325 if (i >= tmo_count) { 4326 if (!silent) 4327 netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d\n", 4328 HWRM_TOTAL_TIMEOUT(i), 4329 le16_to_cpu(req->req_type), 4330 le16_to_cpu(req->seq_id), len); 4331 return -EBUSY; 4332 } 4333 4334 /* Last byte of resp contains valid bit */ 4335 valid = ((u8 *)resp) + len - 1; 4336 for (j = 0; j < HWRM_VALID_BIT_DELAY_USEC; j++) { 4337 /* make sure we read from updated DMA memory */ 4338 dma_rmb(); 4339 if (*valid) 4340 break; 4341 usleep_range(1, 5); 4342 } 4343 4344 if (j >= HWRM_VALID_BIT_DELAY_USEC) { 4345 if (!silent) 4346 netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d v:%d\n", 4347 HWRM_TOTAL_TIMEOUT(i), 4348 le16_to_cpu(req->req_type), 4349 le16_to_cpu(req->seq_id), len, 4350 *valid); 4351 return -EBUSY; 4352 } 4353 } 4354 4355 /* Zero valid bit for compatibility. Valid bit in an older spec 4356 * may become a new field in a newer spec. We must make sure that 4357 * a new field not implemented by old spec will read zero. 4358 */ 4359 *valid = 0; 4360 rc = le16_to_cpu(resp->error_code); 4361 if (rc && !silent) 4362 netdev_err(bp->dev, "hwrm req_type 0x%x seq id 0x%x error 0x%x\n", 4363 le16_to_cpu(resp->req_type), 4364 le16_to_cpu(resp->seq_id), rc); 4365 return bnxt_hwrm_to_stderr(rc); 4366 } 4367 4368 int _hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout) 4369 { 4370 return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, false); 4371 } 4372 4373 int _hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len, 4374 int timeout) 4375 { 4376 return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true); 4377 } 4378 4379 int hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout) 4380 { 4381 int rc; 4382 4383 mutex_lock(&bp->hwrm_cmd_lock); 4384 rc = _hwrm_send_message(bp, msg, msg_len, timeout); 4385 mutex_unlock(&bp->hwrm_cmd_lock); 4386 return rc; 4387 } 4388 4389 int hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len, 4390 int timeout) 4391 { 4392 int rc; 4393 4394 mutex_lock(&bp->hwrm_cmd_lock); 4395 rc = bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true); 4396 mutex_unlock(&bp->hwrm_cmd_lock); 4397 return rc; 4398 } 4399 4400 int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp, unsigned long *bmap, int bmap_size, 4401 bool async_only) 4402 { 4403 struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr; 4404 struct hwrm_func_drv_rgtr_input req = {0}; 4405 DECLARE_BITMAP(async_events_bmap, 256); 4406 u32 *events = (u32 *)async_events_bmap; 4407 u32 flags; 4408 int rc, i; 4409 4410 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1); 4411 4412 req.enables = 4413 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE | 4414 FUNC_DRV_RGTR_REQ_ENABLES_VER | 4415 FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD); 4416 4417 req.os_type = cpu_to_le16(FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX); 4418 flags = FUNC_DRV_RGTR_REQ_FLAGS_16BIT_VER_MODE; 4419 if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET) 4420 flags |= FUNC_DRV_RGTR_REQ_FLAGS_HOT_RESET_SUPPORT; 4421 if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY) 4422 flags |= FUNC_DRV_RGTR_REQ_FLAGS_ERROR_RECOVERY_SUPPORT | 4423 FUNC_DRV_RGTR_REQ_FLAGS_MASTER_SUPPORT; 4424 req.flags = cpu_to_le32(flags); 4425 req.ver_maj_8b = DRV_VER_MAJ; 4426 req.ver_min_8b = DRV_VER_MIN; 4427 req.ver_upd_8b = DRV_VER_UPD; 4428 req.ver_maj = cpu_to_le16(DRV_VER_MAJ); 4429 req.ver_min = cpu_to_le16(DRV_VER_MIN); 4430 req.ver_upd = cpu_to_le16(DRV_VER_UPD); 4431 4432 if (BNXT_PF(bp)) { 4433 u32 data[8]; 4434 int i; 4435 4436 memset(data, 0, sizeof(data)); 4437 for (i = 0; i < ARRAY_SIZE(bnxt_vf_req_snif); i++) { 4438 u16 cmd = bnxt_vf_req_snif[i]; 4439 unsigned int bit, idx; 4440 4441 idx = cmd / 32; 4442 bit = cmd % 32; 4443 data[idx] |= 1 << bit; 4444 } 4445 4446 for (i = 0; i < 8; i++) 4447 req.vf_req_fwd[i] = cpu_to_le32(data[i]); 4448 4449 req.enables |= 4450 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD); 4451 } 4452 4453 if (bp->fw_cap & BNXT_FW_CAP_OVS_64BIT_HANDLE) 4454 req.flags |= cpu_to_le32( 4455 FUNC_DRV_RGTR_REQ_FLAGS_FLOW_HANDLE_64BIT_MODE); 4456 4457 memset(async_events_bmap, 0, sizeof(async_events_bmap)); 4458 for (i = 0; i < ARRAY_SIZE(bnxt_async_events_arr); i++) { 4459 u16 event_id = bnxt_async_events_arr[i]; 4460 4461 if (event_id == ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY && 4462 !(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)) 4463 continue; 4464 __set_bit(bnxt_async_events_arr[i], async_events_bmap); 4465 } 4466 if (bmap && bmap_size) { 4467 for (i = 0; i < bmap_size; i++) { 4468 if (test_bit(i, bmap)) 4469 __set_bit(i, async_events_bmap); 4470 } 4471 } 4472 for (i = 0; i < 8; i++) 4473 req.async_event_fwd[i] |= cpu_to_le32(events[i]); 4474 4475 if (async_only) 4476 req.enables = 4477 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD); 4478 4479 mutex_lock(&bp->hwrm_cmd_lock); 4480 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4481 if (!rc) { 4482 set_bit(BNXT_STATE_DRV_REGISTERED, &bp->state); 4483 if (resp->flags & 4484 cpu_to_le32(FUNC_DRV_RGTR_RESP_FLAGS_IF_CHANGE_SUPPORTED)) 4485 bp->fw_cap |= BNXT_FW_CAP_IF_CHANGE; 4486 } 4487 mutex_unlock(&bp->hwrm_cmd_lock); 4488 return rc; 4489 } 4490 4491 static int bnxt_hwrm_func_drv_unrgtr(struct bnxt *bp) 4492 { 4493 struct hwrm_func_drv_unrgtr_input req = {0}; 4494 4495 if (!test_and_clear_bit(BNXT_STATE_DRV_REGISTERED, &bp->state)) 4496 return 0; 4497 4498 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_UNRGTR, -1, -1); 4499 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4500 } 4501 4502 static int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, u8 tunnel_type) 4503 { 4504 u32 rc = 0; 4505 struct hwrm_tunnel_dst_port_free_input req = {0}; 4506 4507 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_FREE, -1, -1); 4508 req.tunnel_type = tunnel_type; 4509 4510 switch (tunnel_type) { 4511 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN: 4512 req.tunnel_dst_port_id = cpu_to_le16(bp->vxlan_fw_dst_port_id); 4513 bp->vxlan_fw_dst_port_id = INVALID_HW_RING_ID; 4514 break; 4515 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE: 4516 req.tunnel_dst_port_id = cpu_to_le16(bp->nge_fw_dst_port_id); 4517 bp->nge_fw_dst_port_id = INVALID_HW_RING_ID; 4518 break; 4519 default: 4520 break; 4521 } 4522 4523 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4524 if (rc) 4525 netdev_err(bp->dev, "hwrm_tunnel_dst_port_free failed. rc:%d\n", 4526 rc); 4527 return rc; 4528 } 4529 4530 static int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, __be16 port, 4531 u8 tunnel_type) 4532 { 4533 u32 rc = 0; 4534 struct hwrm_tunnel_dst_port_alloc_input req = {0}; 4535 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr; 4536 4537 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_ALLOC, -1, -1); 4538 4539 req.tunnel_type = tunnel_type; 4540 req.tunnel_dst_port_val = port; 4541 4542 mutex_lock(&bp->hwrm_cmd_lock); 4543 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4544 if (rc) { 4545 netdev_err(bp->dev, "hwrm_tunnel_dst_port_alloc failed. rc:%d\n", 4546 rc); 4547 goto err_out; 4548 } 4549 4550 switch (tunnel_type) { 4551 case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN: 4552 bp->vxlan_fw_dst_port_id = 4553 le16_to_cpu(resp->tunnel_dst_port_id); 4554 break; 4555 case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE: 4556 bp->nge_fw_dst_port_id = le16_to_cpu(resp->tunnel_dst_port_id); 4557 break; 4558 default: 4559 break; 4560 } 4561 4562 err_out: 4563 mutex_unlock(&bp->hwrm_cmd_lock); 4564 return rc; 4565 } 4566 4567 static int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp, u16 vnic_id) 4568 { 4569 struct hwrm_cfa_l2_set_rx_mask_input req = {0}; 4570 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 4571 4572 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_SET_RX_MASK, -1, -1); 4573 req.vnic_id = cpu_to_le32(vnic->fw_vnic_id); 4574 4575 req.num_mc_entries = cpu_to_le32(vnic->mc_list_count); 4576 req.mc_tbl_addr = cpu_to_le64(vnic->mc_list_mapping); 4577 req.mask = cpu_to_le32(vnic->rx_mask); 4578 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4579 } 4580 4581 #ifdef CONFIG_RFS_ACCEL 4582 static int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt *bp, 4583 struct bnxt_ntuple_filter *fltr) 4584 { 4585 struct hwrm_cfa_ntuple_filter_free_input req = {0}; 4586 4587 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_FREE, -1, -1); 4588 req.ntuple_filter_id = fltr->filter_id; 4589 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4590 } 4591 4592 #define BNXT_NTP_FLTR_FLAGS \ 4593 (CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID | \ 4594 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE | \ 4595 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR | \ 4596 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE | \ 4597 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR | \ 4598 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK | \ 4599 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR | \ 4600 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK | \ 4601 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL | \ 4602 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT | \ 4603 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK | \ 4604 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT | \ 4605 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK | \ 4606 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID) 4607 4608 #define BNXT_NTP_TUNNEL_FLTR_FLAG \ 4609 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 4610 4611 static int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt *bp, 4612 struct bnxt_ntuple_filter *fltr) 4613 { 4614 struct hwrm_cfa_ntuple_filter_alloc_input req = {0}; 4615 struct hwrm_cfa_ntuple_filter_alloc_output *resp; 4616 struct flow_keys *keys = &fltr->fkeys; 4617 struct bnxt_vnic_info *vnic; 4618 u32 flags = 0; 4619 int rc = 0; 4620 4621 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_ALLOC, -1, -1); 4622 req.l2_filter_id = bp->vnic_info[0].fw_l2_filter_id[fltr->l2_fltr_idx]; 4623 4624 if (bp->fw_cap & BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V2) { 4625 flags = CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DEST_RFS_RING_IDX; 4626 req.dst_id = cpu_to_le16(fltr->rxq); 4627 } else { 4628 vnic = &bp->vnic_info[fltr->rxq + 1]; 4629 req.dst_id = cpu_to_le16(vnic->fw_vnic_id); 4630 } 4631 req.flags = cpu_to_le32(flags); 4632 req.enables = cpu_to_le32(BNXT_NTP_FLTR_FLAGS); 4633 4634 req.ethertype = htons(ETH_P_IP); 4635 memcpy(req.src_macaddr, fltr->src_mac_addr, ETH_ALEN); 4636 req.ip_addr_type = CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4; 4637 req.ip_protocol = keys->basic.ip_proto; 4638 4639 if (keys->basic.n_proto == htons(ETH_P_IPV6)) { 4640 int i; 4641 4642 req.ethertype = htons(ETH_P_IPV6); 4643 req.ip_addr_type = 4644 CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6; 4645 *(struct in6_addr *)&req.src_ipaddr[0] = 4646 keys->addrs.v6addrs.src; 4647 *(struct in6_addr *)&req.dst_ipaddr[0] = 4648 keys->addrs.v6addrs.dst; 4649 for (i = 0; i < 4; i++) { 4650 req.src_ipaddr_mask[i] = cpu_to_be32(0xffffffff); 4651 req.dst_ipaddr_mask[i] = cpu_to_be32(0xffffffff); 4652 } 4653 } else { 4654 req.src_ipaddr[0] = keys->addrs.v4addrs.src; 4655 req.src_ipaddr_mask[0] = cpu_to_be32(0xffffffff); 4656 req.dst_ipaddr[0] = keys->addrs.v4addrs.dst; 4657 req.dst_ipaddr_mask[0] = cpu_to_be32(0xffffffff); 4658 } 4659 if (keys->control.flags & FLOW_DIS_ENCAPSULATION) { 4660 req.enables |= cpu_to_le32(BNXT_NTP_TUNNEL_FLTR_FLAG); 4661 req.tunnel_type = 4662 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL; 4663 } 4664 4665 req.src_port = keys->ports.src; 4666 req.src_port_mask = cpu_to_be16(0xffff); 4667 req.dst_port = keys->ports.dst; 4668 req.dst_port_mask = cpu_to_be16(0xffff); 4669 4670 mutex_lock(&bp->hwrm_cmd_lock); 4671 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4672 if (!rc) { 4673 resp = bnxt_get_hwrm_resp_addr(bp, &req); 4674 fltr->filter_id = resp->ntuple_filter_id; 4675 } 4676 mutex_unlock(&bp->hwrm_cmd_lock); 4677 return rc; 4678 } 4679 #endif 4680 4681 static int bnxt_hwrm_set_vnic_filter(struct bnxt *bp, u16 vnic_id, u16 idx, 4682 u8 *mac_addr) 4683 { 4684 u32 rc = 0; 4685 struct hwrm_cfa_l2_filter_alloc_input req = {0}; 4686 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr; 4687 4688 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_ALLOC, -1, -1); 4689 req.flags = cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX); 4690 if (!BNXT_CHIP_TYPE_NITRO_A0(bp)) 4691 req.flags |= 4692 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST); 4693 req.dst_id = cpu_to_le16(bp->vnic_info[vnic_id].fw_vnic_id); 4694 req.enables = 4695 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR | 4696 CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID | 4697 CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK); 4698 memcpy(req.l2_addr, mac_addr, ETH_ALEN); 4699 req.l2_addr_mask[0] = 0xff; 4700 req.l2_addr_mask[1] = 0xff; 4701 req.l2_addr_mask[2] = 0xff; 4702 req.l2_addr_mask[3] = 0xff; 4703 req.l2_addr_mask[4] = 0xff; 4704 req.l2_addr_mask[5] = 0xff; 4705 4706 mutex_lock(&bp->hwrm_cmd_lock); 4707 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4708 if (!rc) 4709 bp->vnic_info[vnic_id].fw_l2_filter_id[idx] = 4710 resp->l2_filter_id; 4711 mutex_unlock(&bp->hwrm_cmd_lock); 4712 return rc; 4713 } 4714 4715 static int bnxt_hwrm_clear_vnic_filter(struct bnxt *bp) 4716 { 4717 u16 i, j, num_of_vnics = 1; /* only vnic 0 supported */ 4718 int rc = 0; 4719 4720 /* Any associated ntuple filters will also be cleared by firmware. */ 4721 mutex_lock(&bp->hwrm_cmd_lock); 4722 for (i = 0; i < num_of_vnics; i++) { 4723 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 4724 4725 for (j = 0; j < vnic->uc_filter_count; j++) { 4726 struct hwrm_cfa_l2_filter_free_input req = {0}; 4727 4728 bnxt_hwrm_cmd_hdr_init(bp, &req, 4729 HWRM_CFA_L2_FILTER_FREE, -1, -1); 4730 4731 req.l2_filter_id = vnic->fw_l2_filter_id[j]; 4732 4733 rc = _hwrm_send_message(bp, &req, sizeof(req), 4734 HWRM_CMD_TIMEOUT); 4735 } 4736 vnic->uc_filter_count = 0; 4737 } 4738 mutex_unlock(&bp->hwrm_cmd_lock); 4739 4740 return rc; 4741 } 4742 4743 static int bnxt_hwrm_vnic_set_tpa(struct bnxt *bp, u16 vnic_id, u32 tpa_flags) 4744 { 4745 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 4746 u16 max_aggs = VNIC_TPA_CFG_REQ_MAX_AGGS_MAX; 4747 struct hwrm_vnic_tpa_cfg_input req = {0}; 4748 4749 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) 4750 return 0; 4751 4752 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_TPA_CFG, -1, -1); 4753 4754 if (tpa_flags) { 4755 u16 mss = bp->dev->mtu - 40; 4756 u32 nsegs, n, segs = 0, flags; 4757 4758 flags = VNIC_TPA_CFG_REQ_FLAGS_TPA | 4759 VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA | 4760 VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE | 4761 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN | 4762 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ; 4763 if (tpa_flags & BNXT_FLAG_GRO) 4764 flags |= VNIC_TPA_CFG_REQ_FLAGS_GRO; 4765 4766 req.flags = cpu_to_le32(flags); 4767 4768 req.enables = 4769 cpu_to_le32(VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS | 4770 VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS | 4771 VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN); 4772 4773 /* Number of segs are log2 units, and first packet is not 4774 * included as part of this units. 4775 */ 4776 if (mss <= BNXT_RX_PAGE_SIZE) { 4777 n = BNXT_RX_PAGE_SIZE / mss; 4778 nsegs = (MAX_SKB_FRAGS - 1) * n; 4779 } else { 4780 n = mss / BNXT_RX_PAGE_SIZE; 4781 if (mss & (BNXT_RX_PAGE_SIZE - 1)) 4782 n++; 4783 nsegs = (MAX_SKB_FRAGS - n) / n; 4784 } 4785 4786 if (bp->flags & BNXT_FLAG_CHIP_P5) { 4787 segs = MAX_TPA_SEGS_P5; 4788 max_aggs = bp->max_tpa; 4789 } else { 4790 segs = ilog2(nsegs); 4791 } 4792 req.max_agg_segs = cpu_to_le16(segs); 4793 req.max_aggs = cpu_to_le16(max_aggs); 4794 4795 req.min_agg_len = cpu_to_le32(512); 4796 } 4797 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id); 4798 4799 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4800 } 4801 4802 static u16 bnxt_cp_ring_from_grp(struct bnxt *bp, struct bnxt_ring_struct *ring) 4803 { 4804 struct bnxt_ring_grp_info *grp_info; 4805 4806 grp_info = &bp->grp_info[ring->grp_idx]; 4807 return grp_info->cp_fw_ring_id; 4808 } 4809 4810 static u16 bnxt_cp_ring_for_rx(struct bnxt *bp, struct bnxt_rx_ring_info *rxr) 4811 { 4812 if (bp->flags & BNXT_FLAG_CHIP_P5) { 4813 struct bnxt_napi *bnapi = rxr->bnapi; 4814 struct bnxt_cp_ring_info *cpr; 4815 4816 cpr = bnapi->cp_ring.cp_ring_arr[BNXT_RX_HDL]; 4817 return cpr->cp_ring_struct.fw_ring_id; 4818 } else { 4819 return bnxt_cp_ring_from_grp(bp, &rxr->rx_ring_struct); 4820 } 4821 } 4822 4823 static u16 bnxt_cp_ring_for_tx(struct bnxt *bp, struct bnxt_tx_ring_info *txr) 4824 { 4825 if (bp->flags & BNXT_FLAG_CHIP_P5) { 4826 struct bnxt_napi *bnapi = txr->bnapi; 4827 struct bnxt_cp_ring_info *cpr; 4828 4829 cpr = bnapi->cp_ring.cp_ring_arr[BNXT_TX_HDL]; 4830 return cpr->cp_ring_struct.fw_ring_id; 4831 } else { 4832 return bnxt_cp_ring_from_grp(bp, &txr->tx_ring_struct); 4833 } 4834 } 4835 4836 static int bnxt_alloc_rss_indir_tbl(struct bnxt *bp) 4837 { 4838 int entries; 4839 4840 if (bp->flags & BNXT_FLAG_CHIP_P5) 4841 entries = BNXT_MAX_RSS_TABLE_ENTRIES_P5; 4842 else 4843 entries = HW_HASH_INDEX_SIZE; 4844 4845 bp->rss_indir_tbl_entries = entries; 4846 bp->rss_indir_tbl = kmalloc_array(entries, sizeof(*bp->rss_indir_tbl), 4847 GFP_KERNEL); 4848 if (!bp->rss_indir_tbl) 4849 return -ENOMEM; 4850 return 0; 4851 } 4852 4853 static void bnxt_set_dflt_rss_indir_tbl(struct bnxt *bp) 4854 { 4855 u16 max_rings, max_entries, pad, i; 4856 4857 if (!bp->rx_nr_rings) 4858 return; 4859 4860 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 4861 max_rings = bp->rx_nr_rings - 1; 4862 else 4863 max_rings = bp->rx_nr_rings; 4864 4865 max_entries = bnxt_get_rxfh_indir_size(bp->dev); 4866 4867 for (i = 0; i < max_entries; i++) 4868 bp->rss_indir_tbl[i] = ethtool_rxfh_indir_default(i, max_rings); 4869 4870 pad = bp->rss_indir_tbl_entries - max_entries; 4871 if (pad) 4872 memset(&bp->rss_indir_tbl[i], 0, pad * sizeof(u16)); 4873 } 4874 4875 static u16 bnxt_get_max_rss_ring(struct bnxt *bp) 4876 { 4877 u16 i, tbl_size, max_ring = 0; 4878 4879 if (!bp->rss_indir_tbl) 4880 return 0; 4881 4882 tbl_size = bnxt_get_rxfh_indir_size(bp->dev); 4883 for (i = 0; i < tbl_size; i++) 4884 max_ring = max(max_ring, bp->rss_indir_tbl[i]); 4885 return max_ring; 4886 } 4887 4888 int bnxt_get_nr_rss_ctxs(struct bnxt *bp, int rx_rings) 4889 { 4890 if (bp->flags & BNXT_FLAG_CHIP_P5) 4891 return DIV_ROUND_UP(rx_rings, BNXT_RSS_TABLE_ENTRIES_P5); 4892 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 4893 return 2; 4894 return 1; 4895 } 4896 4897 static void __bnxt_fill_hw_rss_tbl(struct bnxt *bp, struct bnxt_vnic_info *vnic) 4898 { 4899 bool no_rss = !(vnic->flags & BNXT_VNIC_RSS_FLAG); 4900 u16 i, j; 4901 4902 /* Fill the RSS indirection table with ring group ids */ 4903 for (i = 0, j = 0; i < HW_HASH_INDEX_SIZE; i++) { 4904 if (!no_rss) 4905 j = bp->rss_indir_tbl[i]; 4906 vnic->rss_table[i] = cpu_to_le16(vnic->fw_grp_ids[j]); 4907 } 4908 } 4909 4910 static void __bnxt_fill_hw_rss_tbl_p5(struct bnxt *bp, 4911 struct bnxt_vnic_info *vnic) 4912 { 4913 __le16 *ring_tbl = vnic->rss_table; 4914 struct bnxt_rx_ring_info *rxr; 4915 u16 tbl_size, i; 4916 4917 tbl_size = bnxt_get_rxfh_indir_size(bp->dev); 4918 4919 for (i = 0; i < tbl_size; i++) { 4920 u16 ring_id, j; 4921 4922 j = bp->rss_indir_tbl[i]; 4923 rxr = &bp->rx_ring[j]; 4924 4925 ring_id = rxr->rx_ring_struct.fw_ring_id; 4926 *ring_tbl++ = cpu_to_le16(ring_id); 4927 ring_id = bnxt_cp_ring_for_rx(bp, rxr); 4928 *ring_tbl++ = cpu_to_le16(ring_id); 4929 } 4930 } 4931 4932 static void bnxt_fill_hw_rss_tbl(struct bnxt *bp, struct bnxt_vnic_info *vnic) 4933 { 4934 if (bp->flags & BNXT_FLAG_CHIP_P5) 4935 __bnxt_fill_hw_rss_tbl_p5(bp, vnic); 4936 else 4937 __bnxt_fill_hw_rss_tbl(bp, vnic); 4938 } 4939 4940 static int bnxt_hwrm_vnic_set_rss(struct bnxt *bp, u16 vnic_id, bool set_rss) 4941 { 4942 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 4943 struct hwrm_vnic_rss_cfg_input req = {0}; 4944 4945 if ((bp->flags & BNXT_FLAG_CHIP_P5) || 4946 vnic->fw_rss_cos_lb_ctx[0] == INVALID_HW_RING_ID) 4947 return 0; 4948 4949 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1); 4950 if (set_rss) { 4951 bnxt_fill_hw_rss_tbl(bp, vnic); 4952 req.hash_type = cpu_to_le32(bp->rss_hash_cfg); 4953 req.hash_mode_flags = VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT; 4954 req.ring_grp_tbl_addr = cpu_to_le64(vnic->rss_table_dma_addr); 4955 req.hash_key_tbl_addr = 4956 cpu_to_le64(vnic->rss_hash_key_dma_addr); 4957 } 4958 req.rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]); 4959 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4960 } 4961 4962 static int bnxt_hwrm_vnic_set_rss_p5(struct bnxt *bp, u16 vnic_id, bool set_rss) 4963 { 4964 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 4965 struct hwrm_vnic_rss_cfg_input req = {0}; 4966 dma_addr_t ring_tbl_map; 4967 u32 i, nr_ctxs; 4968 4969 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1); 4970 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id); 4971 if (!set_rss) { 4972 hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4973 return 0; 4974 } 4975 bnxt_fill_hw_rss_tbl(bp, vnic); 4976 req.hash_type = cpu_to_le32(bp->rss_hash_cfg); 4977 req.hash_mode_flags = VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT; 4978 req.hash_key_tbl_addr = cpu_to_le64(vnic->rss_hash_key_dma_addr); 4979 ring_tbl_map = vnic->rss_table_dma_addr; 4980 nr_ctxs = bnxt_get_nr_rss_ctxs(bp, bp->rx_nr_rings); 4981 for (i = 0; i < nr_ctxs; ring_tbl_map += BNXT_RSS_TABLE_SIZE_P5, i++) { 4982 int rc; 4983 4984 req.ring_grp_tbl_addr = cpu_to_le64(ring_tbl_map); 4985 req.ring_table_pair_index = i; 4986 req.rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[i]); 4987 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4988 if (rc) 4989 return rc; 4990 } 4991 return 0; 4992 } 4993 4994 static int bnxt_hwrm_vnic_set_hds(struct bnxt *bp, u16 vnic_id) 4995 { 4996 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 4997 struct hwrm_vnic_plcmodes_cfg_input req = {0}; 4998 4999 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_PLCMODES_CFG, -1, -1); 5000 req.flags = cpu_to_le32(VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT | 5001 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 | 5002 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6); 5003 req.enables = 5004 cpu_to_le32(VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID | 5005 VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID); 5006 /* thresholds not implemented in firmware yet */ 5007 req.jumbo_thresh = cpu_to_le16(bp->rx_copy_thresh); 5008 req.hds_threshold = cpu_to_le16(bp->rx_copy_thresh); 5009 req.vnic_id = cpu_to_le32(vnic->fw_vnic_id); 5010 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5011 } 5012 5013 static void bnxt_hwrm_vnic_ctx_free_one(struct bnxt *bp, u16 vnic_id, 5014 u16 ctx_idx) 5015 { 5016 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {0}; 5017 5018 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, -1, -1); 5019 req.rss_cos_lb_ctx_id = 5020 cpu_to_le16(bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx]); 5021 5022 hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5023 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] = INVALID_HW_RING_ID; 5024 } 5025 5026 static void bnxt_hwrm_vnic_ctx_free(struct bnxt *bp) 5027 { 5028 int i, j; 5029 5030 for (i = 0; i < bp->nr_vnics; i++) { 5031 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 5032 5033 for (j = 0; j < BNXT_MAX_CTX_PER_VNIC; j++) { 5034 if (vnic->fw_rss_cos_lb_ctx[j] != INVALID_HW_RING_ID) 5035 bnxt_hwrm_vnic_ctx_free_one(bp, i, j); 5036 } 5037 } 5038 bp->rsscos_nr_ctxs = 0; 5039 } 5040 5041 static int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, u16 vnic_id, u16 ctx_idx) 5042 { 5043 int rc; 5044 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {0}; 5045 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp = 5046 bp->hwrm_cmd_resp_addr; 5047 5048 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, -1, 5049 -1); 5050 5051 mutex_lock(&bp->hwrm_cmd_lock); 5052 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5053 if (!rc) 5054 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] = 5055 le16_to_cpu(resp->rss_cos_lb_ctx_id); 5056 mutex_unlock(&bp->hwrm_cmd_lock); 5057 5058 return rc; 5059 } 5060 5061 static u32 bnxt_get_roce_vnic_mode(struct bnxt *bp) 5062 { 5063 if (bp->flags & BNXT_FLAG_ROCE_MIRROR_CAP) 5064 return VNIC_CFG_REQ_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE; 5065 return VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE; 5066 } 5067 5068 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id) 5069 { 5070 unsigned int ring = 0, grp_idx; 5071 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 5072 struct hwrm_vnic_cfg_input req = {0}; 5073 u16 def_vlan = 0; 5074 5075 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_CFG, -1, -1); 5076 5077 if (bp->flags & BNXT_FLAG_CHIP_P5) { 5078 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[0]; 5079 5080 req.default_rx_ring_id = 5081 cpu_to_le16(rxr->rx_ring_struct.fw_ring_id); 5082 req.default_cmpl_ring_id = 5083 cpu_to_le16(bnxt_cp_ring_for_rx(bp, rxr)); 5084 req.enables = 5085 cpu_to_le32(VNIC_CFG_REQ_ENABLES_DEFAULT_RX_RING_ID | 5086 VNIC_CFG_REQ_ENABLES_DEFAULT_CMPL_RING_ID); 5087 goto vnic_mru; 5088 } 5089 req.enables = cpu_to_le32(VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP); 5090 /* Only RSS support for now TBD: COS & LB */ 5091 if (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID) { 5092 req.rss_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]); 5093 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE | 5094 VNIC_CFG_REQ_ENABLES_MRU); 5095 } else if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG) { 5096 req.rss_rule = 5097 cpu_to_le16(bp->vnic_info[0].fw_rss_cos_lb_ctx[0]); 5098 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE | 5099 VNIC_CFG_REQ_ENABLES_MRU); 5100 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE); 5101 } else { 5102 req.rss_rule = cpu_to_le16(0xffff); 5103 } 5104 5105 if (BNXT_CHIP_TYPE_NITRO_A0(bp) && 5106 (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID)) { 5107 req.cos_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[1]); 5108 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_COS_RULE); 5109 } else { 5110 req.cos_rule = cpu_to_le16(0xffff); 5111 } 5112 5113 if (vnic->flags & BNXT_VNIC_RSS_FLAG) 5114 ring = 0; 5115 else if (vnic->flags & BNXT_VNIC_RFS_FLAG) 5116 ring = vnic_id - 1; 5117 else if ((vnic_id == 1) && BNXT_CHIP_TYPE_NITRO_A0(bp)) 5118 ring = bp->rx_nr_rings - 1; 5119 5120 grp_idx = bp->rx_ring[ring].bnapi->index; 5121 req.dflt_ring_grp = cpu_to_le16(bp->grp_info[grp_idx].fw_grp_id); 5122 req.lb_rule = cpu_to_le16(0xffff); 5123 vnic_mru: 5124 req.mru = cpu_to_le16(bp->dev->mtu + ETH_HLEN + VLAN_HLEN); 5125 5126 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id); 5127 #ifdef CONFIG_BNXT_SRIOV 5128 if (BNXT_VF(bp)) 5129 def_vlan = bp->vf.vlan; 5130 #endif 5131 if ((bp->flags & BNXT_FLAG_STRIP_VLAN) || def_vlan) 5132 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE); 5133 if (!vnic_id && bnxt_ulp_registered(bp->edev, BNXT_ROCE_ULP)) 5134 req.flags |= cpu_to_le32(bnxt_get_roce_vnic_mode(bp)); 5135 5136 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5137 } 5138 5139 static void bnxt_hwrm_vnic_free_one(struct bnxt *bp, u16 vnic_id) 5140 { 5141 if (bp->vnic_info[vnic_id].fw_vnic_id != INVALID_HW_RING_ID) { 5142 struct hwrm_vnic_free_input req = {0}; 5143 5144 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_FREE, -1, -1); 5145 req.vnic_id = 5146 cpu_to_le32(bp->vnic_info[vnic_id].fw_vnic_id); 5147 5148 hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5149 bp->vnic_info[vnic_id].fw_vnic_id = INVALID_HW_RING_ID; 5150 } 5151 } 5152 5153 static void bnxt_hwrm_vnic_free(struct bnxt *bp) 5154 { 5155 u16 i; 5156 5157 for (i = 0; i < bp->nr_vnics; i++) 5158 bnxt_hwrm_vnic_free_one(bp, i); 5159 } 5160 5161 static int bnxt_hwrm_vnic_alloc(struct bnxt *bp, u16 vnic_id, 5162 unsigned int start_rx_ring_idx, 5163 unsigned int nr_rings) 5164 { 5165 int rc = 0; 5166 unsigned int i, j, grp_idx, end_idx = start_rx_ring_idx + nr_rings; 5167 struct hwrm_vnic_alloc_input req = {0}; 5168 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr; 5169 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 5170 5171 if (bp->flags & BNXT_FLAG_CHIP_P5) 5172 goto vnic_no_ring_grps; 5173 5174 /* map ring groups to this vnic */ 5175 for (i = start_rx_ring_idx, j = 0; i < end_idx; i++, j++) { 5176 grp_idx = bp->rx_ring[i].bnapi->index; 5177 if (bp->grp_info[grp_idx].fw_grp_id == INVALID_HW_RING_ID) { 5178 netdev_err(bp->dev, "Not enough ring groups avail:%x req:%x\n", 5179 j, nr_rings); 5180 break; 5181 } 5182 vnic->fw_grp_ids[j] = bp->grp_info[grp_idx].fw_grp_id; 5183 } 5184 5185 vnic_no_ring_grps: 5186 for (i = 0; i < BNXT_MAX_CTX_PER_VNIC; i++) 5187 vnic->fw_rss_cos_lb_ctx[i] = INVALID_HW_RING_ID; 5188 if (vnic_id == 0) 5189 req.flags = cpu_to_le32(VNIC_ALLOC_REQ_FLAGS_DEFAULT); 5190 5191 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_ALLOC, -1, -1); 5192 5193 mutex_lock(&bp->hwrm_cmd_lock); 5194 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5195 if (!rc) 5196 vnic->fw_vnic_id = le32_to_cpu(resp->vnic_id); 5197 mutex_unlock(&bp->hwrm_cmd_lock); 5198 return rc; 5199 } 5200 5201 static int bnxt_hwrm_vnic_qcaps(struct bnxt *bp) 5202 { 5203 struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr; 5204 struct hwrm_vnic_qcaps_input req = {0}; 5205 int rc; 5206 5207 bp->hw_ring_stats_size = sizeof(struct ctx_hw_stats); 5208 bp->flags &= ~(BNXT_FLAG_NEW_RSS_CAP | BNXT_FLAG_ROCE_MIRROR_CAP); 5209 if (bp->hwrm_spec_code < 0x10600) 5210 return 0; 5211 5212 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_QCAPS, -1, -1); 5213 mutex_lock(&bp->hwrm_cmd_lock); 5214 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5215 if (!rc) { 5216 u32 flags = le32_to_cpu(resp->flags); 5217 5218 if (!(bp->flags & BNXT_FLAG_CHIP_P5) && 5219 (flags & VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP)) 5220 bp->flags |= BNXT_FLAG_NEW_RSS_CAP; 5221 if (flags & 5222 VNIC_QCAPS_RESP_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP) 5223 bp->flags |= BNXT_FLAG_ROCE_MIRROR_CAP; 5224 5225 /* Older P5 fw before EXT_HW_STATS support did not set 5226 * VLAN_STRIP_CAP properly. 5227 */ 5228 if ((flags & VNIC_QCAPS_RESP_FLAGS_VLAN_STRIP_CAP) || 5229 ((bp->flags & BNXT_FLAG_CHIP_P5) && 5230 !(bp->fw_cap & BNXT_FW_CAP_EXT_HW_STATS_SUPPORTED))) 5231 bp->fw_cap |= BNXT_FW_CAP_VLAN_RX_STRIP; 5232 bp->max_tpa_v2 = le16_to_cpu(resp->max_aggs_supported); 5233 if (bp->max_tpa_v2) 5234 bp->hw_ring_stats_size = 5235 sizeof(struct ctx_hw_stats_ext); 5236 } 5237 mutex_unlock(&bp->hwrm_cmd_lock); 5238 return rc; 5239 } 5240 5241 static int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp) 5242 { 5243 u16 i; 5244 u32 rc = 0; 5245 5246 if (bp->flags & BNXT_FLAG_CHIP_P5) 5247 return 0; 5248 5249 mutex_lock(&bp->hwrm_cmd_lock); 5250 for (i = 0; i < bp->rx_nr_rings; i++) { 5251 struct hwrm_ring_grp_alloc_input req = {0}; 5252 struct hwrm_ring_grp_alloc_output *resp = 5253 bp->hwrm_cmd_resp_addr; 5254 unsigned int grp_idx = bp->rx_ring[i].bnapi->index; 5255 5256 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_ALLOC, -1, -1); 5257 5258 req.cr = cpu_to_le16(bp->grp_info[grp_idx].cp_fw_ring_id); 5259 req.rr = cpu_to_le16(bp->grp_info[grp_idx].rx_fw_ring_id); 5260 req.ar = cpu_to_le16(bp->grp_info[grp_idx].agg_fw_ring_id); 5261 req.sc = cpu_to_le16(bp->grp_info[grp_idx].fw_stats_ctx); 5262 5263 rc = _hwrm_send_message(bp, &req, sizeof(req), 5264 HWRM_CMD_TIMEOUT); 5265 if (rc) 5266 break; 5267 5268 bp->grp_info[grp_idx].fw_grp_id = 5269 le32_to_cpu(resp->ring_group_id); 5270 } 5271 mutex_unlock(&bp->hwrm_cmd_lock); 5272 return rc; 5273 } 5274 5275 static void bnxt_hwrm_ring_grp_free(struct bnxt *bp) 5276 { 5277 u16 i; 5278 struct hwrm_ring_grp_free_input req = {0}; 5279 5280 if (!bp->grp_info || (bp->flags & BNXT_FLAG_CHIP_P5)) 5281 return; 5282 5283 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_FREE, -1, -1); 5284 5285 mutex_lock(&bp->hwrm_cmd_lock); 5286 for (i = 0; i < bp->cp_nr_rings; i++) { 5287 if (bp->grp_info[i].fw_grp_id == INVALID_HW_RING_ID) 5288 continue; 5289 req.ring_group_id = 5290 cpu_to_le32(bp->grp_info[i].fw_grp_id); 5291 5292 _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5293 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID; 5294 } 5295 mutex_unlock(&bp->hwrm_cmd_lock); 5296 } 5297 5298 static int hwrm_ring_alloc_send_msg(struct bnxt *bp, 5299 struct bnxt_ring_struct *ring, 5300 u32 ring_type, u32 map_index) 5301 { 5302 int rc = 0, err = 0; 5303 struct hwrm_ring_alloc_input req = {0}; 5304 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr; 5305 struct bnxt_ring_mem_info *rmem = &ring->ring_mem; 5306 struct bnxt_ring_grp_info *grp_info; 5307 u16 ring_id; 5308 5309 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_ALLOC, -1, -1); 5310 5311 req.enables = 0; 5312 if (rmem->nr_pages > 1) { 5313 req.page_tbl_addr = cpu_to_le64(rmem->pg_tbl_map); 5314 /* Page size is in log2 units */ 5315 req.page_size = BNXT_PAGE_SHIFT; 5316 req.page_tbl_depth = 1; 5317 } else { 5318 req.page_tbl_addr = cpu_to_le64(rmem->dma_arr[0]); 5319 } 5320 req.fbo = 0; 5321 /* Association of ring index with doorbell index and MSIX number */ 5322 req.logical_id = cpu_to_le16(map_index); 5323 5324 switch (ring_type) { 5325 case HWRM_RING_ALLOC_TX: { 5326 struct bnxt_tx_ring_info *txr; 5327 5328 txr = container_of(ring, struct bnxt_tx_ring_info, 5329 tx_ring_struct); 5330 req.ring_type = RING_ALLOC_REQ_RING_TYPE_TX; 5331 /* Association of transmit ring with completion ring */ 5332 grp_info = &bp->grp_info[ring->grp_idx]; 5333 req.cmpl_ring_id = cpu_to_le16(bnxt_cp_ring_for_tx(bp, txr)); 5334 req.length = cpu_to_le32(bp->tx_ring_mask + 1); 5335 req.stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx); 5336 req.queue_id = cpu_to_le16(ring->queue_id); 5337 break; 5338 } 5339 case HWRM_RING_ALLOC_RX: 5340 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX; 5341 req.length = cpu_to_le32(bp->rx_ring_mask + 1); 5342 if (bp->flags & BNXT_FLAG_CHIP_P5) { 5343 u16 flags = 0; 5344 5345 /* Association of rx ring with stats context */ 5346 grp_info = &bp->grp_info[ring->grp_idx]; 5347 req.rx_buf_size = cpu_to_le16(bp->rx_buf_use_size); 5348 req.stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx); 5349 req.enables |= cpu_to_le32( 5350 RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID); 5351 if (NET_IP_ALIGN == 2) 5352 flags = RING_ALLOC_REQ_FLAGS_RX_SOP_PAD; 5353 req.flags = cpu_to_le16(flags); 5354 } 5355 break; 5356 case HWRM_RING_ALLOC_AGG: 5357 if (bp->flags & BNXT_FLAG_CHIP_P5) { 5358 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX_AGG; 5359 /* Association of agg ring with rx ring */ 5360 grp_info = &bp->grp_info[ring->grp_idx]; 5361 req.rx_ring_id = cpu_to_le16(grp_info->rx_fw_ring_id); 5362 req.rx_buf_size = cpu_to_le16(BNXT_RX_PAGE_SIZE); 5363 req.stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx); 5364 req.enables |= cpu_to_le32( 5365 RING_ALLOC_REQ_ENABLES_RX_RING_ID_VALID | 5366 RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID); 5367 } else { 5368 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX; 5369 } 5370 req.length = cpu_to_le32(bp->rx_agg_ring_mask + 1); 5371 break; 5372 case HWRM_RING_ALLOC_CMPL: 5373 req.ring_type = RING_ALLOC_REQ_RING_TYPE_L2_CMPL; 5374 req.length = cpu_to_le32(bp->cp_ring_mask + 1); 5375 if (bp->flags & BNXT_FLAG_CHIP_P5) { 5376 /* Association of cp ring with nq */ 5377 grp_info = &bp->grp_info[map_index]; 5378 req.nq_ring_id = cpu_to_le16(grp_info->cp_fw_ring_id); 5379 req.cq_handle = cpu_to_le64(ring->handle); 5380 req.enables |= cpu_to_le32( 5381 RING_ALLOC_REQ_ENABLES_NQ_RING_ID_VALID); 5382 } else if (bp->flags & BNXT_FLAG_USING_MSIX) { 5383 req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX; 5384 } 5385 break; 5386 case HWRM_RING_ALLOC_NQ: 5387 req.ring_type = RING_ALLOC_REQ_RING_TYPE_NQ; 5388 req.length = cpu_to_le32(bp->cp_ring_mask + 1); 5389 if (bp->flags & BNXT_FLAG_USING_MSIX) 5390 req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX; 5391 break; 5392 default: 5393 netdev_err(bp->dev, "hwrm alloc invalid ring type %d\n", 5394 ring_type); 5395 return -1; 5396 } 5397 5398 mutex_lock(&bp->hwrm_cmd_lock); 5399 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5400 err = le16_to_cpu(resp->error_code); 5401 ring_id = le16_to_cpu(resp->ring_id); 5402 mutex_unlock(&bp->hwrm_cmd_lock); 5403 5404 if (rc || err) { 5405 netdev_err(bp->dev, "hwrm_ring_alloc type %d failed. rc:%x err:%x\n", 5406 ring_type, rc, err); 5407 return -EIO; 5408 } 5409 ring->fw_ring_id = ring_id; 5410 return rc; 5411 } 5412 5413 static int bnxt_hwrm_set_async_event_cr(struct bnxt *bp, int idx) 5414 { 5415 int rc; 5416 5417 if (BNXT_PF(bp)) { 5418 struct hwrm_func_cfg_input req = {0}; 5419 5420 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1); 5421 req.fid = cpu_to_le16(0xffff); 5422 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR); 5423 req.async_event_cr = cpu_to_le16(idx); 5424 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5425 } else { 5426 struct hwrm_func_vf_cfg_input req = {0}; 5427 5428 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_VF_CFG, -1, -1); 5429 req.enables = 5430 cpu_to_le32(FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR); 5431 req.async_event_cr = cpu_to_le16(idx); 5432 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5433 } 5434 return rc; 5435 } 5436 5437 static void bnxt_set_db(struct bnxt *bp, struct bnxt_db_info *db, u32 ring_type, 5438 u32 map_idx, u32 xid) 5439 { 5440 if (bp->flags & BNXT_FLAG_CHIP_P5) { 5441 if (BNXT_PF(bp)) 5442 db->doorbell = bp->bar1 + DB_PF_OFFSET_P5; 5443 else 5444 db->doorbell = bp->bar1 + DB_VF_OFFSET_P5; 5445 switch (ring_type) { 5446 case HWRM_RING_ALLOC_TX: 5447 db->db_key64 = DBR_PATH_L2 | DBR_TYPE_SQ; 5448 break; 5449 case HWRM_RING_ALLOC_RX: 5450 case HWRM_RING_ALLOC_AGG: 5451 db->db_key64 = DBR_PATH_L2 | DBR_TYPE_SRQ; 5452 break; 5453 case HWRM_RING_ALLOC_CMPL: 5454 db->db_key64 = DBR_PATH_L2; 5455 break; 5456 case HWRM_RING_ALLOC_NQ: 5457 db->db_key64 = DBR_PATH_L2; 5458 break; 5459 } 5460 db->db_key64 |= (u64)xid << DBR_XID_SFT; 5461 } else { 5462 db->doorbell = bp->bar1 + map_idx * 0x80; 5463 switch (ring_type) { 5464 case HWRM_RING_ALLOC_TX: 5465 db->db_key32 = DB_KEY_TX; 5466 break; 5467 case HWRM_RING_ALLOC_RX: 5468 case HWRM_RING_ALLOC_AGG: 5469 db->db_key32 = DB_KEY_RX; 5470 break; 5471 case HWRM_RING_ALLOC_CMPL: 5472 db->db_key32 = DB_KEY_CP; 5473 break; 5474 } 5475 } 5476 } 5477 5478 static int bnxt_hwrm_ring_alloc(struct bnxt *bp) 5479 { 5480 bool agg_rings = !!(bp->flags & BNXT_FLAG_AGG_RINGS); 5481 int i, rc = 0; 5482 u32 type; 5483 5484 if (bp->flags & BNXT_FLAG_CHIP_P5) 5485 type = HWRM_RING_ALLOC_NQ; 5486 else 5487 type = HWRM_RING_ALLOC_CMPL; 5488 for (i = 0; i < bp->cp_nr_rings; i++) { 5489 struct bnxt_napi *bnapi = bp->bnapi[i]; 5490 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 5491 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct; 5492 u32 map_idx = ring->map_idx; 5493 unsigned int vector; 5494 5495 vector = bp->irq_tbl[map_idx].vector; 5496 disable_irq_nosync(vector); 5497 rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx); 5498 if (rc) { 5499 enable_irq(vector); 5500 goto err_out; 5501 } 5502 bnxt_set_db(bp, &cpr->cp_db, type, map_idx, ring->fw_ring_id); 5503 bnxt_db_nq(bp, &cpr->cp_db, cpr->cp_raw_cons); 5504 enable_irq(vector); 5505 bp->grp_info[i].cp_fw_ring_id = ring->fw_ring_id; 5506 5507 if (!i) { 5508 rc = bnxt_hwrm_set_async_event_cr(bp, ring->fw_ring_id); 5509 if (rc) 5510 netdev_warn(bp->dev, "Failed to set async event completion ring.\n"); 5511 } 5512 } 5513 5514 type = HWRM_RING_ALLOC_TX; 5515 for (i = 0; i < bp->tx_nr_rings; i++) { 5516 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; 5517 struct bnxt_ring_struct *ring; 5518 u32 map_idx; 5519 5520 if (bp->flags & BNXT_FLAG_CHIP_P5) { 5521 struct bnxt_napi *bnapi = txr->bnapi; 5522 struct bnxt_cp_ring_info *cpr, *cpr2; 5523 u32 type2 = HWRM_RING_ALLOC_CMPL; 5524 5525 cpr = &bnapi->cp_ring; 5526 cpr2 = cpr->cp_ring_arr[BNXT_TX_HDL]; 5527 ring = &cpr2->cp_ring_struct; 5528 ring->handle = BNXT_TX_HDL; 5529 map_idx = bnapi->index; 5530 rc = hwrm_ring_alloc_send_msg(bp, ring, type2, map_idx); 5531 if (rc) 5532 goto err_out; 5533 bnxt_set_db(bp, &cpr2->cp_db, type2, map_idx, 5534 ring->fw_ring_id); 5535 bnxt_db_cq(bp, &cpr2->cp_db, cpr2->cp_raw_cons); 5536 } 5537 ring = &txr->tx_ring_struct; 5538 map_idx = i; 5539 rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx); 5540 if (rc) 5541 goto err_out; 5542 bnxt_set_db(bp, &txr->tx_db, type, map_idx, ring->fw_ring_id); 5543 } 5544 5545 type = HWRM_RING_ALLOC_RX; 5546 for (i = 0; i < bp->rx_nr_rings; i++) { 5547 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 5548 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct; 5549 struct bnxt_napi *bnapi = rxr->bnapi; 5550 u32 map_idx = bnapi->index; 5551 5552 rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx); 5553 if (rc) 5554 goto err_out; 5555 bnxt_set_db(bp, &rxr->rx_db, type, map_idx, ring->fw_ring_id); 5556 /* If we have agg rings, post agg buffers first. */ 5557 if (!agg_rings) 5558 bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod); 5559 bp->grp_info[map_idx].rx_fw_ring_id = ring->fw_ring_id; 5560 if (bp->flags & BNXT_FLAG_CHIP_P5) { 5561 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 5562 u32 type2 = HWRM_RING_ALLOC_CMPL; 5563 struct bnxt_cp_ring_info *cpr2; 5564 5565 cpr2 = cpr->cp_ring_arr[BNXT_RX_HDL]; 5566 ring = &cpr2->cp_ring_struct; 5567 ring->handle = BNXT_RX_HDL; 5568 rc = hwrm_ring_alloc_send_msg(bp, ring, type2, map_idx); 5569 if (rc) 5570 goto err_out; 5571 bnxt_set_db(bp, &cpr2->cp_db, type2, map_idx, 5572 ring->fw_ring_id); 5573 bnxt_db_cq(bp, &cpr2->cp_db, cpr2->cp_raw_cons); 5574 } 5575 } 5576 5577 if (agg_rings) { 5578 type = HWRM_RING_ALLOC_AGG; 5579 for (i = 0; i < bp->rx_nr_rings; i++) { 5580 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 5581 struct bnxt_ring_struct *ring = 5582 &rxr->rx_agg_ring_struct; 5583 u32 grp_idx = ring->grp_idx; 5584 u32 map_idx = grp_idx + bp->rx_nr_rings; 5585 5586 rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx); 5587 if (rc) 5588 goto err_out; 5589 5590 bnxt_set_db(bp, &rxr->rx_agg_db, type, map_idx, 5591 ring->fw_ring_id); 5592 bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod); 5593 bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod); 5594 bp->grp_info[grp_idx].agg_fw_ring_id = ring->fw_ring_id; 5595 } 5596 } 5597 err_out: 5598 return rc; 5599 } 5600 5601 static int hwrm_ring_free_send_msg(struct bnxt *bp, 5602 struct bnxt_ring_struct *ring, 5603 u32 ring_type, int cmpl_ring_id) 5604 { 5605 int rc; 5606 struct hwrm_ring_free_input req = {0}; 5607 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr; 5608 u16 error_code; 5609 5610 if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state)) 5611 return 0; 5612 5613 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_FREE, cmpl_ring_id, -1); 5614 req.ring_type = ring_type; 5615 req.ring_id = cpu_to_le16(ring->fw_ring_id); 5616 5617 mutex_lock(&bp->hwrm_cmd_lock); 5618 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5619 error_code = le16_to_cpu(resp->error_code); 5620 mutex_unlock(&bp->hwrm_cmd_lock); 5621 5622 if (rc || error_code) { 5623 netdev_err(bp->dev, "hwrm_ring_free type %d failed. rc:%x err:%x\n", 5624 ring_type, rc, error_code); 5625 return -EIO; 5626 } 5627 return 0; 5628 } 5629 5630 static void bnxt_hwrm_ring_free(struct bnxt *bp, bool close_path) 5631 { 5632 u32 type; 5633 int i; 5634 5635 if (!bp->bnapi) 5636 return; 5637 5638 for (i = 0; i < bp->tx_nr_rings; i++) { 5639 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; 5640 struct bnxt_ring_struct *ring = &txr->tx_ring_struct; 5641 5642 if (ring->fw_ring_id != INVALID_HW_RING_ID) { 5643 u32 cmpl_ring_id = bnxt_cp_ring_for_tx(bp, txr); 5644 5645 hwrm_ring_free_send_msg(bp, ring, 5646 RING_FREE_REQ_RING_TYPE_TX, 5647 close_path ? cmpl_ring_id : 5648 INVALID_HW_RING_ID); 5649 ring->fw_ring_id = INVALID_HW_RING_ID; 5650 } 5651 } 5652 5653 for (i = 0; i < bp->rx_nr_rings; i++) { 5654 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 5655 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct; 5656 u32 grp_idx = rxr->bnapi->index; 5657 5658 if (ring->fw_ring_id != INVALID_HW_RING_ID) { 5659 u32 cmpl_ring_id = bnxt_cp_ring_for_rx(bp, rxr); 5660 5661 hwrm_ring_free_send_msg(bp, ring, 5662 RING_FREE_REQ_RING_TYPE_RX, 5663 close_path ? cmpl_ring_id : 5664 INVALID_HW_RING_ID); 5665 ring->fw_ring_id = INVALID_HW_RING_ID; 5666 bp->grp_info[grp_idx].rx_fw_ring_id = 5667 INVALID_HW_RING_ID; 5668 } 5669 } 5670 5671 if (bp->flags & BNXT_FLAG_CHIP_P5) 5672 type = RING_FREE_REQ_RING_TYPE_RX_AGG; 5673 else 5674 type = RING_FREE_REQ_RING_TYPE_RX; 5675 for (i = 0; i < bp->rx_nr_rings; i++) { 5676 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 5677 struct bnxt_ring_struct *ring = &rxr->rx_agg_ring_struct; 5678 u32 grp_idx = rxr->bnapi->index; 5679 5680 if (ring->fw_ring_id != INVALID_HW_RING_ID) { 5681 u32 cmpl_ring_id = bnxt_cp_ring_for_rx(bp, rxr); 5682 5683 hwrm_ring_free_send_msg(bp, ring, type, 5684 close_path ? cmpl_ring_id : 5685 INVALID_HW_RING_ID); 5686 ring->fw_ring_id = INVALID_HW_RING_ID; 5687 bp->grp_info[grp_idx].agg_fw_ring_id = 5688 INVALID_HW_RING_ID; 5689 } 5690 } 5691 5692 /* The completion rings are about to be freed. After that the 5693 * IRQ doorbell will not work anymore. So we need to disable 5694 * IRQ here. 5695 */ 5696 bnxt_disable_int_sync(bp); 5697 5698 if (bp->flags & BNXT_FLAG_CHIP_P5) 5699 type = RING_FREE_REQ_RING_TYPE_NQ; 5700 else 5701 type = RING_FREE_REQ_RING_TYPE_L2_CMPL; 5702 for (i = 0; i < bp->cp_nr_rings; i++) { 5703 struct bnxt_napi *bnapi = bp->bnapi[i]; 5704 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 5705 struct bnxt_ring_struct *ring; 5706 int j; 5707 5708 for (j = 0; j < 2; j++) { 5709 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j]; 5710 5711 if (cpr2) { 5712 ring = &cpr2->cp_ring_struct; 5713 if (ring->fw_ring_id == INVALID_HW_RING_ID) 5714 continue; 5715 hwrm_ring_free_send_msg(bp, ring, 5716 RING_FREE_REQ_RING_TYPE_L2_CMPL, 5717 INVALID_HW_RING_ID); 5718 ring->fw_ring_id = INVALID_HW_RING_ID; 5719 } 5720 } 5721 ring = &cpr->cp_ring_struct; 5722 if (ring->fw_ring_id != INVALID_HW_RING_ID) { 5723 hwrm_ring_free_send_msg(bp, ring, type, 5724 INVALID_HW_RING_ID); 5725 ring->fw_ring_id = INVALID_HW_RING_ID; 5726 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID; 5727 } 5728 } 5729 } 5730 5731 static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max, 5732 bool shared); 5733 5734 static int bnxt_hwrm_get_rings(struct bnxt *bp) 5735 { 5736 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr; 5737 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 5738 struct hwrm_func_qcfg_input req = {0}; 5739 int rc; 5740 5741 if (bp->hwrm_spec_code < 0x10601) 5742 return 0; 5743 5744 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1); 5745 req.fid = cpu_to_le16(0xffff); 5746 mutex_lock(&bp->hwrm_cmd_lock); 5747 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5748 if (rc) { 5749 mutex_unlock(&bp->hwrm_cmd_lock); 5750 return rc; 5751 } 5752 5753 hw_resc->resv_tx_rings = le16_to_cpu(resp->alloc_tx_rings); 5754 if (BNXT_NEW_RM(bp)) { 5755 u16 cp, stats; 5756 5757 hw_resc->resv_rx_rings = le16_to_cpu(resp->alloc_rx_rings); 5758 hw_resc->resv_hw_ring_grps = 5759 le32_to_cpu(resp->alloc_hw_ring_grps); 5760 hw_resc->resv_vnics = le16_to_cpu(resp->alloc_vnics); 5761 cp = le16_to_cpu(resp->alloc_cmpl_rings); 5762 stats = le16_to_cpu(resp->alloc_stat_ctx); 5763 hw_resc->resv_irqs = cp; 5764 if (bp->flags & BNXT_FLAG_CHIP_P5) { 5765 int rx = hw_resc->resv_rx_rings; 5766 int tx = hw_resc->resv_tx_rings; 5767 5768 if (bp->flags & BNXT_FLAG_AGG_RINGS) 5769 rx >>= 1; 5770 if (cp < (rx + tx)) { 5771 bnxt_trim_rings(bp, &rx, &tx, cp, false); 5772 if (bp->flags & BNXT_FLAG_AGG_RINGS) 5773 rx <<= 1; 5774 hw_resc->resv_rx_rings = rx; 5775 hw_resc->resv_tx_rings = tx; 5776 } 5777 hw_resc->resv_irqs = le16_to_cpu(resp->alloc_msix); 5778 hw_resc->resv_hw_ring_grps = rx; 5779 } 5780 hw_resc->resv_cp_rings = cp; 5781 hw_resc->resv_stat_ctxs = stats; 5782 } 5783 mutex_unlock(&bp->hwrm_cmd_lock); 5784 return 0; 5785 } 5786 5787 /* Caller must hold bp->hwrm_cmd_lock */ 5788 int __bnxt_hwrm_get_tx_rings(struct bnxt *bp, u16 fid, int *tx_rings) 5789 { 5790 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr; 5791 struct hwrm_func_qcfg_input req = {0}; 5792 int rc; 5793 5794 if (bp->hwrm_spec_code < 0x10601) 5795 return 0; 5796 5797 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1); 5798 req.fid = cpu_to_le16(fid); 5799 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5800 if (!rc) 5801 *tx_rings = le16_to_cpu(resp->alloc_tx_rings); 5802 5803 return rc; 5804 } 5805 5806 static bool bnxt_rfs_supported(struct bnxt *bp); 5807 5808 static void 5809 __bnxt_hwrm_reserve_pf_rings(struct bnxt *bp, struct hwrm_func_cfg_input *req, 5810 int tx_rings, int rx_rings, int ring_grps, 5811 int cp_rings, int stats, int vnics) 5812 { 5813 u32 enables = 0; 5814 5815 bnxt_hwrm_cmd_hdr_init(bp, req, HWRM_FUNC_CFG, -1, -1); 5816 req->fid = cpu_to_le16(0xffff); 5817 enables |= tx_rings ? FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS : 0; 5818 req->num_tx_rings = cpu_to_le16(tx_rings); 5819 if (BNXT_NEW_RM(bp)) { 5820 enables |= rx_rings ? FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS : 0; 5821 enables |= stats ? FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0; 5822 if (bp->flags & BNXT_FLAG_CHIP_P5) { 5823 enables |= cp_rings ? FUNC_CFG_REQ_ENABLES_NUM_MSIX : 0; 5824 enables |= tx_rings + ring_grps ? 5825 FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0; 5826 enables |= rx_rings ? 5827 FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0; 5828 } else { 5829 enables |= cp_rings ? 5830 FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0; 5831 enables |= ring_grps ? 5832 FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS | 5833 FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0; 5834 } 5835 enables |= vnics ? FUNC_CFG_REQ_ENABLES_NUM_VNICS : 0; 5836 5837 req->num_rx_rings = cpu_to_le16(rx_rings); 5838 if (bp->flags & BNXT_FLAG_CHIP_P5) { 5839 req->num_cmpl_rings = cpu_to_le16(tx_rings + ring_grps); 5840 req->num_msix = cpu_to_le16(cp_rings); 5841 req->num_rsscos_ctxs = 5842 cpu_to_le16(DIV_ROUND_UP(ring_grps, 64)); 5843 } else { 5844 req->num_cmpl_rings = cpu_to_le16(cp_rings); 5845 req->num_hw_ring_grps = cpu_to_le16(ring_grps); 5846 req->num_rsscos_ctxs = cpu_to_le16(1); 5847 if (!(bp->flags & BNXT_FLAG_NEW_RSS_CAP) && 5848 bnxt_rfs_supported(bp)) 5849 req->num_rsscos_ctxs = 5850 cpu_to_le16(ring_grps + 1); 5851 } 5852 req->num_stat_ctxs = cpu_to_le16(stats); 5853 req->num_vnics = cpu_to_le16(vnics); 5854 } 5855 req->enables = cpu_to_le32(enables); 5856 } 5857 5858 static void 5859 __bnxt_hwrm_reserve_vf_rings(struct bnxt *bp, 5860 struct hwrm_func_vf_cfg_input *req, int tx_rings, 5861 int rx_rings, int ring_grps, int cp_rings, 5862 int stats, int vnics) 5863 { 5864 u32 enables = 0; 5865 5866 bnxt_hwrm_cmd_hdr_init(bp, req, HWRM_FUNC_VF_CFG, -1, -1); 5867 enables |= tx_rings ? FUNC_VF_CFG_REQ_ENABLES_NUM_TX_RINGS : 0; 5868 enables |= rx_rings ? FUNC_VF_CFG_REQ_ENABLES_NUM_RX_RINGS | 5869 FUNC_VF_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0; 5870 enables |= stats ? FUNC_VF_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0; 5871 if (bp->flags & BNXT_FLAG_CHIP_P5) { 5872 enables |= tx_rings + ring_grps ? 5873 FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0; 5874 } else { 5875 enables |= cp_rings ? 5876 FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0; 5877 enables |= ring_grps ? 5878 FUNC_VF_CFG_REQ_ENABLES_NUM_HW_RING_GRPS : 0; 5879 } 5880 enables |= vnics ? FUNC_VF_CFG_REQ_ENABLES_NUM_VNICS : 0; 5881 enables |= FUNC_VF_CFG_REQ_ENABLES_NUM_L2_CTXS; 5882 5883 req->num_l2_ctxs = cpu_to_le16(BNXT_VF_MAX_L2_CTX); 5884 req->num_tx_rings = cpu_to_le16(tx_rings); 5885 req->num_rx_rings = cpu_to_le16(rx_rings); 5886 if (bp->flags & BNXT_FLAG_CHIP_P5) { 5887 req->num_cmpl_rings = cpu_to_le16(tx_rings + ring_grps); 5888 req->num_rsscos_ctxs = cpu_to_le16(DIV_ROUND_UP(ring_grps, 64)); 5889 } else { 5890 req->num_cmpl_rings = cpu_to_le16(cp_rings); 5891 req->num_hw_ring_grps = cpu_to_le16(ring_grps); 5892 req->num_rsscos_ctxs = cpu_to_le16(BNXT_VF_MAX_RSS_CTX); 5893 } 5894 req->num_stat_ctxs = cpu_to_le16(stats); 5895 req->num_vnics = cpu_to_le16(vnics); 5896 5897 req->enables = cpu_to_le32(enables); 5898 } 5899 5900 static int 5901 bnxt_hwrm_reserve_pf_rings(struct bnxt *bp, int tx_rings, int rx_rings, 5902 int ring_grps, int cp_rings, int stats, int vnics) 5903 { 5904 struct hwrm_func_cfg_input req = {0}; 5905 int rc; 5906 5907 __bnxt_hwrm_reserve_pf_rings(bp, &req, tx_rings, rx_rings, ring_grps, 5908 cp_rings, stats, vnics); 5909 if (!req.enables) 5910 return 0; 5911 5912 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5913 if (rc) 5914 return rc; 5915 5916 if (bp->hwrm_spec_code < 0x10601) 5917 bp->hw_resc.resv_tx_rings = tx_rings; 5918 5919 return bnxt_hwrm_get_rings(bp); 5920 } 5921 5922 static int 5923 bnxt_hwrm_reserve_vf_rings(struct bnxt *bp, int tx_rings, int rx_rings, 5924 int ring_grps, int cp_rings, int stats, int vnics) 5925 { 5926 struct hwrm_func_vf_cfg_input req = {0}; 5927 int rc; 5928 5929 if (!BNXT_NEW_RM(bp)) { 5930 bp->hw_resc.resv_tx_rings = tx_rings; 5931 return 0; 5932 } 5933 5934 __bnxt_hwrm_reserve_vf_rings(bp, &req, tx_rings, rx_rings, ring_grps, 5935 cp_rings, stats, vnics); 5936 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5937 if (rc) 5938 return rc; 5939 5940 return bnxt_hwrm_get_rings(bp); 5941 } 5942 5943 static int bnxt_hwrm_reserve_rings(struct bnxt *bp, int tx, int rx, int grp, 5944 int cp, int stat, int vnic) 5945 { 5946 if (BNXT_PF(bp)) 5947 return bnxt_hwrm_reserve_pf_rings(bp, tx, rx, grp, cp, stat, 5948 vnic); 5949 else 5950 return bnxt_hwrm_reserve_vf_rings(bp, tx, rx, grp, cp, stat, 5951 vnic); 5952 } 5953 5954 int bnxt_nq_rings_in_use(struct bnxt *bp) 5955 { 5956 int cp = bp->cp_nr_rings; 5957 int ulp_msix, ulp_base; 5958 5959 ulp_msix = bnxt_get_ulp_msix_num(bp); 5960 if (ulp_msix) { 5961 ulp_base = bnxt_get_ulp_msix_base(bp); 5962 cp += ulp_msix; 5963 if ((ulp_base + ulp_msix) > cp) 5964 cp = ulp_base + ulp_msix; 5965 } 5966 return cp; 5967 } 5968 5969 static int bnxt_cp_rings_in_use(struct bnxt *bp) 5970 { 5971 int cp; 5972 5973 if (!(bp->flags & BNXT_FLAG_CHIP_P5)) 5974 return bnxt_nq_rings_in_use(bp); 5975 5976 cp = bp->tx_nr_rings + bp->rx_nr_rings; 5977 return cp; 5978 } 5979 5980 static int bnxt_get_func_stat_ctxs(struct bnxt *bp) 5981 { 5982 int ulp_stat = bnxt_get_ulp_stat_ctxs(bp); 5983 int cp = bp->cp_nr_rings; 5984 5985 if (!ulp_stat) 5986 return cp; 5987 5988 if (bnxt_nq_rings_in_use(bp) > cp + bnxt_get_ulp_msix_num(bp)) 5989 return bnxt_get_ulp_msix_base(bp) + ulp_stat; 5990 5991 return cp + ulp_stat; 5992 } 5993 5994 static bool bnxt_need_reserve_rings(struct bnxt *bp) 5995 { 5996 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 5997 int cp = bnxt_cp_rings_in_use(bp); 5998 int nq = bnxt_nq_rings_in_use(bp); 5999 int rx = bp->rx_nr_rings, stat; 6000 int vnic = 1, grp = rx; 6001 6002 if (bp->hwrm_spec_code < 0x10601) 6003 return false; 6004 6005 if (hw_resc->resv_tx_rings != bp->tx_nr_rings) 6006 return true; 6007 6008 if ((bp->flags & BNXT_FLAG_RFS) && !(bp->flags & BNXT_FLAG_CHIP_P5)) 6009 vnic = rx + 1; 6010 if (bp->flags & BNXT_FLAG_AGG_RINGS) 6011 rx <<= 1; 6012 stat = bnxt_get_func_stat_ctxs(bp); 6013 if (BNXT_NEW_RM(bp) && 6014 (hw_resc->resv_rx_rings != rx || hw_resc->resv_cp_rings != cp || 6015 hw_resc->resv_vnics != vnic || hw_resc->resv_stat_ctxs != stat || 6016 (hw_resc->resv_hw_ring_grps != grp && 6017 !(bp->flags & BNXT_FLAG_CHIP_P5)))) 6018 return true; 6019 if ((bp->flags & BNXT_FLAG_CHIP_P5) && BNXT_PF(bp) && 6020 hw_resc->resv_irqs != nq) 6021 return true; 6022 return false; 6023 } 6024 6025 static int __bnxt_reserve_rings(struct bnxt *bp) 6026 { 6027 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 6028 int cp = bnxt_nq_rings_in_use(bp); 6029 int tx = bp->tx_nr_rings; 6030 int rx = bp->rx_nr_rings; 6031 int grp, rx_rings, rc; 6032 int vnic = 1, stat; 6033 bool sh = false; 6034 6035 if (!bnxt_need_reserve_rings(bp)) 6036 return 0; 6037 6038 if (bp->flags & BNXT_FLAG_SHARED_RINGS) 6039 sh = true; 6040 if ((bp->flags & BNXT_FLAG_RFS) && !(bp->flags & BNXT_FLAG_CHIP_P5)) 6041 vnic = rx + 1; 6042 if (bp->flags & BNXT_FLAG_AGG_RINGS) 6043 rx <<= 1; 6044 grp = bp->rx_nr_rings; 6045 stat = bnxt_get_func_stat_ctxs(bp); 6046 6047 rc = bnxt_hwrm_reserve_rings(bp, tx, rx, grp, cp, stat, vnic); 6048 if (rc) 6049 return rc; 6050 6051 tx = hw_resc->resv_tx_rings; 6052 if (BNXT_NEW_RM(bp)) { 6053 rx = hw_resc->resv_rx_rings; 6054 cp = hw_resc->resv_irqs; 6055 grp = hw_resc->resv_hw_ring_grps; 6056 vnic = hw_resc->resv_vnics; 6057 stat = hw_resc->resv_stat_ctxs; 6058 } 6059 6060 rx_rings = rx; 6061 if (bp->flags & BNXT_FLAG_AGG_RINGS) { 6062 if (rx >= 2) { 6063 rx_rings = rx >> 1; 6064 } else { 6065 if (netif_running(bp->dev)) 6066 return -ENOMEM; 6067 6068 bp->flags &= ~BNXT_FLAG_AGG_RINGS; 6069 bp->flags |= BNXT_FLAG_NO_AGG_RINGS; 6070 bp->dev->hw_features &= ~NETIF_F_LRO; 6071 bp->dev->features &= ~NETIF_F_LRO; 6072 bnxt_set_ring_params(bp); 6073 } 6074 } 6075 rx_rings = min_t(int, rx_rings, grp); 6076 cp = min_t(int, cp, bp->cp_nr_rings); 6077 if (stat > bnxt_get_ulp_stat_ctxs(bp)) 6078 stat -= bnxt_get_ulp_stat_ctxs(bp); 6079 cp = min_t(int, cp, stat); 6080 rc = bnxt_trim_rings(bp, &rx_rings, &tx, cp, sh); 6081 if (bp->flags & BNXT_FLAG_AGG_RINGS) 6082 rx = rx_rings << 1; 6083 cp = sh ? max_t(int, tx, rx_rings) : tx + rx_rings; 6084 bp->tx_nr_rings = tx; 6085 6086 /* If we cannot reserve all the RX rings, reset the RSS map only 6087 * if absolutely necessary 6088 */ 6089 if (rx_rings != bp->rx_nr_rings) { 6090 netdev_warn(bp->dev, "Able to reserve only %d out of %d requested RX rings\n", 6091 rx_rings, bp->rx_nr_rings); 6092 if ((bp->dev->priv_flags & IFF_RXFH_CONFIGURED) && 6093 (bnxt_get_nr_rss_ctxs(bp, bp->rx_nr_rings) != 6094 bnxt_get_nr_rss_ctxs(bp, rx_rings) || 6095 bnxt_get_max_rss_ring(bp) >= rx_rings)) { 6096 netdev_warn(bp->dev, "RSS table entries reverting to default\n"); 6097 bp->dev->priv_flags &= ~IFF_RXFH_CONFIGURED; 6098 } 6099 } 6100 bp->rx_nr_rings = rx_rings; 6101 bp->cp_nr_rings = cp; 6102 6103 if (!tx || !rx || !cp || !grp || !vnic || !stat) 6104 return -ENOMEM; 6105 6106 return rc; 6107 } 6108 6109 static int bnxt_hwrm_check_vf_rings(struct bnxt *bp, int tx_rings, int rx_rings, 6110 int ring_grps, int cp_rings, int stats, 6111 int vnics) 6112 { 6113 struct hwrm_func_vf_cfg_input req = {0}; 6114 u32 flags; 6115 6116 if (!BNXT_NEW_RM(bp)) 6117 return 0; 6118 6119 __bnxt_hwrm_reserve_vf_rings(bp, &req, tx_rings, rx_rings, ring_grps, 6120 cp_rings, stats, vnics); 6121 flags = FUNC_VF_CFG_REQ_FLAGS_TX_ASSETS_TEST | 6122 FUNC_VF_CFG_REQ_FLAGS_RX_ASSETS_TEST | 6123 FUNC_VF_CFG_REQ_FLAGS_CMPL_ASSETS_TEST | 6124 FUNC_VF_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST | 6125 FUNC_VF_CFG_REQ_FLAGS_VNIC_ASSETS_TEST | 6126 FUNC_VF_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST; 6127 if (!(bp->flags & BNXT_FLAG_CHIP_P5)) 6128 flags |= FUNC_VF_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST; 6129 6130 req.flags = cpu_to_le32(flags); 6131 return hwrm_send_message_silent(bp, &req, sizeof(req), 6132 HWRM_CMD_TIMEOUT); 6133 } 6134 6135 static int bnxt_hwrm_check_pf_rings(struct bnxt *bp, int tx_rings, int rx_rings, 6136 int ring_grps, int cp_rings, int stats, 6137 int vnics) 6138 { 6139 struct hwrm_func_cfg_input req = {0}; 6140 u32 flags; 6141 6142 __bnxt_hwrm_reserve_pf_rings(bp, &req, tx_rings, rx_rings, ring_grps, 6143 cp_rings, stats, vnics); 6144 flags = FUNC_CFG_REQ_FLAGS_TX_ASSETS_TEST; 6145 if (BNXT_NEW_RM(bp)) { 6146 flags |= FUNC_CFG_REQ_FLAGS_RX_ASSETS_TEST | 6147 FUNC_CFG_REQ_FLAGS_CMPL_ASSETS_TEST | 6148 FUNC_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST | 6149 FUNC_CFG_REQ_FLAGS_VNIC_ASSETS_TEST; 6150 if (bp->flags & BNXT_FLAG_CHIP_P5) 6151 flags |= FUNC_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST | 6152 FUNC_CFG_REQ_FLAGS_NQ_ASSETS_TEST; 6153 else 6154 flags |= FUNC_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST; 6155 } 6156 6157 req.flags = cpu_to_le32(flags); 6158 return hwrm_send_message_silent(bp, &req, sizeof(req), 6159 HWRM_CMD_TIMEOUT); 6160 } 6161 6162 static int bnxt_hwrm_check_rings(struct bnxt *bp, int tx_rings, int rx_rings, 6163 int ring_grps, int cp_rings, int stats, 6164 int vnics) 6165 { 6166 if (bp->hwrm_spec_code < 0x10801) 6167 return 0; 6168 6169 if (BNXT_PF(bp)) 6170 return bnxt_hwrm_check_pf_rings(bp, tx_rings, rx_rings, 6171 ring_grps, cp_rings, stats, 6172 vnics); 6173 6174 return bnxt_hwrm_check_vf_rings(bp, tx_rings, rx_rings, ring_grps, 6175 cp_rings, stats, vnics); 6176 } 6177 6178 static void bnxt_hwrm_coal_params_qcaps(struct bnxt *bp) 6179 { 6180 struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr; 6181 struct bnxt_coal_cap *coal_cap = &bp->coal_cap; 6182 struct hwrm_ring_aggint_qcaps_input req = {0}; 6183 int rc; 6184 6185 coal_cap->cmpl_params = BNXT_LEGACY_COAL_CMPL_PARAMS; 6186 coal_cap->num_cmpl_dma_aggr_max = 63; 6187 coal_cap->num_cmpl_dma_aggr_during_int_max = 63; 6188 coal_cap->cmpl_aggr_dma_tmr_max = 65535; 6189 coal_cap->cmpl_aggr_dma_tmr_during_int_max = 65535; 6190 coal_cap->int_lat_tmr_min_max = 65535; 6191 coal_cap->int_lat_tmr_max_max = 65535; 6192 coal_cap->num_cmpl_aggr_int_max = 65535; 6193 coal_cap->timer_units = 80; 6194 6195 if (bp->hwrm_spec_code < 0x10902) 6196 return; 6197 6198 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_AGGINT_QCAPS, -1, -1); 6199 mutex_lock(&bp->hwrm_cmd_lock); 6200 rc = _hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 6201 if (!rc) { 6202 coal_cap->cmpl_params = le32_to_cpu(resp->cmpl_params); 6203 coal_cap->nq_params = le32_to_cpu(resp->nq_params); 6204 coal_cap->num_cmpl_dma_aggr_max = 6205 le16_to_cpu(resp->num_cmpl_dma_aggr_max); 6206 coal_cap->num_cmpl_dma_aggr_during_int_max = 6207 le16_to_cpu(resp->num_cmpl_dma_aggr_during_int_max); 6208 coal_cap->cmpl_aggr_dma_tmr_max = 6209 le16_to_cpu(resp->cmpl_aggr_dma_tmr_max); 6210 coal_cap->cmpl_aggr_dma_tmr_during_int_max = 6211 le16_to_cpu(resp->cmpl_aggr_dma_tmr_during_int_max); 6212 coal_cap->int_lat_tmr_min_max = 6213 le16_to_cpu(resp->int_lat_tmr_min_max); 6214 coal_cap->int_lat_tmr_max_max = 6215 le16_to_cpu(resp->int_lat_tmr_max_max); 6216 coal_cap->num_cmpl_aggr_int_max = 6217 le16_to_cpu(resp->num_cmpl_aggr_int_max); 6218 coal_cap->timer_units = le16_to_cpu(resp->timer_units); 6219 } 6220 mutex_unlock(&bp->hwrm_cmd_lock); 6221 } 6222 6223 static u16 bnxt_usec_to_coal_tmr(struct bnxt *bp, u16 usec) 6224 { 6225 struct bnxt_coal_cap *coal_cap = &bp->coal_cap; 6226 6227 return usec * 1000 / coal_cap->timer_units; 6228 } 6229 6230 static void bnxt_hwrm_set_coal_params(struct bnxt *bp, 6231 struct bnxt_coal *hw_coal, 6232 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req) 6233 { 6234 struct bnxt_coal_cap *coal_cap = &bp->coal_cap; 6235 u32 cmpl_params = coal_cap->cmpl_params; 6236 u16 val, tmr, max, flags = 0; 6237 6238 max = hw_coal->bufs_per_record * 128; 6239 if (hw_coal->budget) 6240 max = hw_coal->bufs_per_record * hw_coal->budget; 6241 max = min_t(u16, max, coal_cap->num_cmpl_aggr_int_max); 6242 6243 val = clamp_t(u16, hw_coal->coal_bufs, 1, max); 6244 req->num_cmpl_aggr_int = cpu_to_le16(val); 6245 6246 val = min_t(u16, val, coal_cap->num_cmpl_dma_aggr_max); 6247 req->num_cmpl_dma_aggr = cpu_to_le16(val); 6248 6249 val = clamp_t(u16, hw_coal->coal_bufs_irq, 1, 6250 coal_cap->num_cmpl_dma_aggr_during_int_max); 6251 req->num_cmpl_dma_aggr_during_int = cpu_to_le16(val); 6252 6253 tmr = bnxt_usec_to_coal_tmr(bp, hw_coal->coal_ticks); 6254 tmr = clamp_t(u16, tmr, 1, coal_cap->int_lat_tmr_max_max); 6255 req->int_lat_tmr_max = cpu_to_le16(tmr); 6256 6257 /* min timer set to 1/2 of interrupt timer */ 6258 if (cmpl_params & RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN) { 6259 val = tmr / 2; 6260 val = clamp_t(u16, val, 1, coal_cap->int_lat_tmr_min_max); 6261 req->int_lat_tmr_min = cpu_to_le16(val); 6262 req->enables |= cpu_to_le16(BNXT_COAL_CMPL_MIN_TMR_ENABLE); 6263 } 6264 6265 /* buf timer set to 1/4 of interrupt timer */ 6266 val = clamp_t(u16, tmr / 4, 1, coal_cap->cmpl_aggr_dma_tmr_max); 6267 req->cmpl_aggr_dma_tmr = cpu_to_le16(val); 6268 6269 if (cmpl_params & 6270 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT) { 6271 tmr = bnxt_usec_to_coal_tmr(bp, hw_coal->coal_ticks_irq); 6272 val = clamp_t(u16, tmr, 1, 6273 coal_cap->cmpl_aggr_dma_tmr_during_int_max); 6274 req->cmpl_aggr_dma_tmr_during_int = cpu_to_le16(val); 6275 req->enables |= 6276 cpu_to_le16(BNXT_COAL_CMPL_AGGR_TMR_DURING_INT_ENABLE); 6277 } 6278 6279 if (cmpl_params & RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET) 6280 flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET; 6281 if ((cmpl_params & RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE) && 6282 hw_coal->idle_thresh && hw_coal->coal_ticks < hw_coal->idle_thresh) 6283 flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE; 6284 req->flags = cpu_to_le16(flags); 6285 req->enables |= cpu_to_le16(BNXT_COAL_CMPL_ENABLES); 6286 } 6287 6288 /* Caller holds bp->hwrm_cmd_lock */ 6289 static int __bnxt_hwrm_set_coal_nq(struct bnxt *bp, struct bnxt_napi *bnapi, 6290 struct bnxt_coal *hw_coal) 6291 { 6292 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0}; 6293 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 6294 struct bnxt_coal_cap *coal_cap = &bp->coal_cap; 6295 u32 nq_params = coal_cap->nq_params; 6296 u16 tmr; 6297 6298 if (!(nq_params & RING_AGGINT_QCAPS_RESP_NQ_PARAMS_INT_LAT_TMR_MIN)) 6299 return 0; 6300 6301 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, 6302 -1, -1); 6303 req.ring_id = cpu_to_le16(cpr->cp_ring_struct.fw_ring_id); 6304 req.flags = 6305 cpu_to_le16(RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_IS_NQ); 6306 6307 tmr = bnxt_usec_to_coal_tmr(bp, hw_coal->coal_ticks) / 2; 6308 tmr = clamp_t(u16, tmr, 1, coal_cap->int_lat_tmr_min_max); 6309 req.int_lat_tmr_min = cpu_to_le16(tmr); 6310 req.enables |= cpu_to_le16(BNXT_COAL_CMPL_MIN_TMR_ENABLE); 6311 return _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 6312 } 6313 6314 int bnxt_hwrm_set_ring_coal(struct bnxt *bp, struct bnxt_napi *bnapi) 6315 { 6316 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx = {0}; 6317 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 6318 struct bnxt_coal coal; 6319 6320 /* Tick values in micro seconds. 6321 * 1 coal_buf x bufs_per_record = 1 completion record. 6322 */ 6323 memcpy(&coal, &bp->rx_coal, sizeof(struct bnxt_coal)); 6324 6325 coal.coal_ticks = cpr->rx_ring_coal.coal_ticks; 6326 coal.coal_bufs = cpr->rx_ring_coal.coal_bufs; 6327 6328 if (!bnapi->rx_ring) 6329 return -ENODEV; 6330 6331 bnxt_hwrm_cmd_hdr_init(bp, &req_rx, 6332 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1); 6333 6334 bnxt_hwrm_set_coal_params(bp, &coal, &req_rx); 6335 6336 req_rx.ring_id = cpu_to_le16(bnxt_cp_ring_for_rx(bp, bnapi->rx_ring)); 6337 6338 return hwrm_send_message(bp, &req_rx, sizeof(req_rx), 6339 HWRM_CMD_TIMEOUT); 6340 } 6341 6342 int bnxt_hwrm_set_coal(struct bnxt *bp) 6343 { 6344 int i, rc = 0; 6345 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx = {0}, 6346 req_tx = {0}, *req; 6347 6348 bnxt_hwrm_cmd_hdr_init(bp, &req_rx, 6349 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1); 6350 bnxt_hwrm_cmd_hdr_init(bp, &req_tx, 6351 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1); 6352 6353 bnxt_hwrm_set_coal_params(bp, &bp->rx_coal, &req_rx); 6354 bnxt_hwrm_set_coal_params(bp, &bp->tx_coal, &req_tx); 6355 6356 mutex_lock(&bp->hwrm_cmd_lock); 6357 for (i = 0; i < bp->cp_nr_rings; i++) { 6358 struct bnxt_napi *bnapi = bp->bnapi[i]; 6359 struct bnxt_coal *hw_coal; 6360 u16 ring_id; 6361 6362 req = &req_rx; 6363 if (!bnapi->rx_ring) { 6364 ring_id = bnxt_cp_ring_for_tx(bp, bnapi->tx_ring); 6365 req = &req_tx; 6366 } else { 6367 ring_id = bnxt_cp_ring_for_rx(bp, bnapi->rx_ring); 6368 } 6369 req->ring_id = cpu_to_le16(ring_id); 6370 6371 rc = _hwrm_send_message(bp, req, sizeof(*req), 6372 HWRM_CMD_TIMEOUT); 6373 if (rc) 6374 break; 6375 6376 if (!(bp->flags & BNXT_FLAG_CHIP_P5)) 6377 continue; 6378 6379 if (bnapi->rx_ring && bnapi->tx_ring) { 6380 req = &req_tx; 6381 ring_id = bnxt_cp_ring_for_tx(bp, bnapi->tx_ring); 6382 req->ring_id = cpu_to_le16(ring_id); 6383 rc = _hwrm_send_message(bp, req, sizeof(*req), 6384 HWRM_CMD_TIMEOUT); 6385 if (rc) 6386 break; 6387 } 6388 if (bnapi->rx_ring) 6389 hw_coal = &bp->rx_coal; 6390 else 6391 hw_coal = &bp->tx_coal; 6392 __bnxt_hwrm_set_coal_nq(bp, bnapi, hw_coal); 6393 } 6394 mutex_unlock(&bp->hwrm_cmd_lock); 6395 return rc; 6396 } 6397 6398 static void bnxt_hwrm_stat_ctx_free(struct bnxt *bp) 6399 { 6400 struct hwrm_stat_ctx_clr_stats_input req0 = {0}; 6401 struct hwrm_stat_ctx_free_input req = {0}; 6402 int i; 6403 6404 if (!bp->bnapi) 6405 return; 6406 6407 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 6408 return; 6409 6410 bnxt_hwrm_cmd_hdr_init(bp, &req0, HWRM_STAT_CTX_CLR_STATS, -1, -1); 6411 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_FREE, -1, -1); 6412 6413 mutex_lock(&bp->hwrm_cmd_lock); 6414 for (i = 0; i < bp->cp_nr_rings; i++) { 6415 struct bnxt_napi *bnapi = bp->bnapi[i]; 6416 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 6417 6418 if (cpr->hw_stats_ctx_id != INVALID_STATS_CTX_ID) { 6419 req.stat_ctx_id = cpu_to_le32(cpr->hw_stats_ctx_id); 6420 if (BNXT_FW_MAJ(bp) <= 20) { 6421 req0.stat_ctx_id = req.stat_ctx_id; 6422 _hwrm_send_message(bp, &req0, sizeof(req0), 6423 HWRM_CMD_TIMEOUT); 6424 } 6425 _hwrm_send_message(bp, &req, sizeof(req), 6426 HWRM_CMD_TIMEOUT); 6427 6428 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID; 6429 } 6430 } 6431 mutex_unlock(&bp->hwrm_cmd_lock); 6432 } 6433 6434 static int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp) 6435 { 6436 int rc = 0, i; 6437 struct hwrm_stat_ctx_alloc_input req = {0}; 6438 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr; 6439 6440 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 6441 return 0; 6442 6443 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_ALLOC, -1, -1); 6444 6445 req.stats_dma_length = cpu_to_le16(bp->hw_ring_stats_size); 6446 req.update_period_ms = cpu_to_le32(bp->stats_coal_ticks / 1000); 6447 6448 mutex_lock(&bp->hwrm_cmd_lock); 6449 for (i = 0; i < bp->cp_nr_rings; i++) { 6450 struct bnxt_napi *bnapi = bp->bnapi[i]; 6451 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 6452 6453 req.stats_dma_addr = cpu_to_le64(cpr->hw_stats_map); 6454 6455 rc = _hwrm_send_message(bp, &req, sizeof(req), 6456 HWRM_CMD_TIMEOUT); 6457 if (rc) 6458 break; 6459 6460 cpr->hw_stats_ctx_id = le32_to_cpu(resp->stat_ctx_id); 6461 6462 bp->grp_info[i].fw_stats_ctx = cpr->hw_stats_ctx_id; 6463 } 6464 mutex_unlock(&bp->hwrm_cmd_lock); 6465 return rc; 6466 } 6467 6468 static int bnxt_hwrm_func_qcfg(struct bnxt *bp) 6469 { 6470 struct hwrm_func_qcfg_input req = {0}; 6471 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr; 6472 u32 min_db_offset = 0; 6473 u16 flags; 6474 int rc; 6475 6476 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1); 6477 req.fid = cpu_to_le16(0xffff); 6478 mutex_lock(&bp->hwrm_cmd_lock); 6479 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 6480 if (rc) 6481 goto func_qcfg_exit; 6482 6483 #ifdef CONFIG_BNXT_SRIOV 6484 if (BNXT_VF(bp)) { 6485 struct bnxt_vf_info *vf = &bp->vf; 6486 6487 vf->vlan = le16_to_cpu(resp->vlan) & VLAN_VID_MASK; 6488 } else { 6489 bp->pf.registered_vfs = le16_to_cpu(resp->registered_vfs); 6490 } 6491 #endif 6492 flags = le16_to_cpu(resp->flags); 6493 if (flags & (FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED | 6494 FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED)) { 6495 bp->fw_cap |= BNXT_FW_CAP_LLDP_AGENT; 6496 if (flags & FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED) 6497 bp->fw_cap |= BNXT_FW_CAP_DCBX_AGENT; 6498 } 6499 if (BNXT_PF(bp) && (flags & FUNC_QCFG_RESP_FLAGS_MULTI_HOST)) 6500 bp->flags |= BNXT_FLAG_MULTI_HOST; 6501 6502 switch (resp->port_partition_type) { 6503 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0: 6504 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5: 6505 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0: 6506 bp->port_partition_type = resp->port_partition_type; 6507 break; 6508 } 6509 if (bp->hwrm_spec_code < 0x10707 || 6510 resp->evb_mode == FUNC_QCFG_RESP_EVB_MODE_VEB) 6511 bp->br_mode = BRIDGE_MODE_VEB; 6512 else if (resp->evb_mode == FUNC_QCFG_RESP_EVB_MODE_VEPA) 6513 bp->br_mode = BRIDGE_MODE_VEPA; 6514 else 6515 bp->br_mode = BRIDGE_MODE_UNDEF; 6516 6517 bp->max_mtu = le16_to_cpu(resp->max_mtu_configured); 6518 if (!bp->max_mtu) 6519 bp->max_mtu = BNXT_MAX_MTU; 6520 6521 if (bp->db_size) 6522 goto func_qcfg_exit; 6523 6524 if (bp->flags & BNXT_FLAG_CHIP_P5) { 6525 if (BNXT_PF(bp)) 6526 min_db_offset = DB_PF_OFFSET_P5; 6527 else 6528 min_db_offset = DB_VF_OFFSET_P5; 6529 } 6530 bp->db_size = PAGE_ALIGN(le16_to_cpu(resp->l2_doorbell_bar_size_kb) * 6531 1024); 6532 if (!bp->db_size || bp->db_size > pci_resource_len(bp->pdev, 2) || 6533 bp->db_size <= min_db_offset) 6534 bp->db_size = pci_resource_len(bp->pdev, 2); 6535 6536 func_qcfg_exit: 6537 mutex_unlock(&bp->hwrm_cmd_lock); 6538 return rc; 6539 } 6540 6541 static int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp) 6542 { 6543 struct hwrm_func_backing_store_qcaps_input req = {0}; 6544 struct hwrm_func_backing_store_qcaps_output *resp = 6545 bp->hwrm_cmd_resp_addr; 6546 int rc; 6547 6548 if (bp->hwrm_spec_code < 0x10902 || BNXT_VF(bp) || bp->ctx) 6549 return 0; 6550 6551 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_BACKING_STORE_QCAPS, -1, -1); 6552 mutex_lock(&bp->hwrm_cmd_lock); 6553 rc = _hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 6554 if (!rc) { 6555 struct bnxt_ctx_pg_info *ctx_pg; 6556 struct bnxt_ctx_mem_info *ctx; 6557 int i, tqm_rings; 6558 6559 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); 6560 if (!ctx) { 6561 rc = -ENOMEM; 6562 goto ctx_err; 6563 } 6564 ctx->qp_max_entries = le32_to_cpu(resp->qp_max_entries); 6565 ctx->qp_min_qp1_entries = le16_to_cpu(resp->qp_min_qp1_entries); 6566 ctx->qp_max_l2_entries = le16_to_cpu(resp->qp_max_l2_entries); 6567 ctx->qp_entry_size = le16_to_cpu(resp->qp_entry_size); 6568 ctx->srq_max_l2_entries = le16_to_cpu(resp->srq_max_l2_entries); 6569 ctx->srq_max_entries = le32_to_cpu(resp->srq_max_entries); 6570 ctx->srq_entry_size = le16_to_cpu(resp->srq_entry_size); 6571 ctx->cq_max_l2_entries = le16_to_cpu(resp->cq_max_l2_entries); 6572 ctx->cq_max_entries = le32_to_cpu(resp->cq_max_entries); 6573 ctx->cq_entry_size = le16_to_cpu(resp->cq_entry_size); 6574 ctx->vnic_max_vnic_entries = 6575 le16_to_cpu(resp->vnic_max_vnic_entries); 6576 ctx->vnic_max_ring_table_entries = 6577 le16_to_cpu(resp->vnic_max_ring_table_entries); 6578 ctx->vnic_entry_size = le16_to_cpu(resp->vnic_entry_size); 6579 ctx->stat_max_entries = le32_to_cpu(resp->stat_max_entries); 6580 ctx->stat_entry_size = le16_to_cpu(resp->stat_entry_size); 6581 ctx->tqm_entry_size = le16_to_cpu(resp->tqm_entry_size); 6582 ctx->tqm_min_entries_per_ring = 6583 le32_to_cpu(resp->tqm_min_entries_per_ring); 6584 ctx->tqm_max_entries_per_ring = 6585 le32_to_cpu(resp->tqm_max_entries_per_ring); 6586 ctx->tqm_entries_multiple = resp->tqm_entries_multiple; 6587 if (!ctx->tqm_entries_multiple) 6588 ctx->tqm_entries_multiple = 1; 6589 ctx->mrav_max_entries = le32_to_cpu(resp->mrav_max_entries); 6590 ctx->mrav_entry_size = le16_to_cpu(resp->mrav_entry_size); 6591 ctx->mrav_num_entries_units = 6592 le16_to_cpu(resp->mrav_num_entries_units); 6593 ctx->tim_entry_size = le16_to_cpu(resp->tim_entry_size); 6594 ctx->tim_max_entries = le32_to_cpu(resp->tim_max_entries); 6595 ctx->ctx_kind_initializer = resp->ctx_kind_initializer; 6596 ctx->tqm_fp_rings_count = resp->tqm_fp_rings_count; 6597 if (!ctx->tqm_fp_rings_count) 6598 ctx->tqm_fp_rings_count = bp->max_q; 6599 6600 tqm_rings = ctx->tqm_fp_rings_count + 1; 6601 ctx_pg = kcalloc(tqm_rings, sizeof(*ctx_pg), GFP_KERNEL); 6602 if (!ctx_pg) { 6603 kfree(ctx); 6604 rc = -ENOMEM; 6605 goto ctx_err; 6606 } 6607 for (i = 0; i < tqm_rings; i++, ctx_pg++) 6608 ctx->tqm_mem[i] = ctx_pg; 6609 bp->ctx = ctx; 6610 } else { 6611 rc = 0; 6612 } 6613 ctx_err: 6614 mutex_unlock(&bp->hwrm_cmd_lock); 6615 return rc; 6616 } 6617 6618 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem, u8 *pg_attr, 6619 __le64 *pg_dir) 6620 { 6621 u8 pg_size = 0; 6622 6623 if (BNXT_PAGE_SHIFT == 13) 6624 pg_size = 1 << 4; 6625 else if (BNXT_PAGE_SIZE == 16) 6626 pg_size = 2 << 4; 6627 6628 *pg_attr = pg_size; 6629 if (rmem->depth >= 1) { 6630 if (rmem->depth == 2) 6631 *pg_attr |= 2; 6632 else 6633 *pg_attr |= 1; 6634 *pg_dir = cpu_to_le64(rmem->pg_tbl_map); 6635 } else { 6636 *pg_dir = cpu_to_le64(rmem->dma_arr[0]); 6637 } 6638 } 6639 6640 #define FUNC_BACKING_STORE_CFG_REQ_DFLT_ENABLES \ 6641 (FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP | \ 6642 FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ | \ 6643 FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ | \ 6644 FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC | \ 6645 FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT) 6646 6647 static int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, u32 enables) 6648 { 6649 struct hwrm_func_backing_store_cfg_input req = {0}; 6650 struct bnxt_ctx_mem_info *ctx = bp->ctx; 6651 struct bnxt_ctx_pg_info *ctx_pg; 6652 __le32 *num_entries; 6653 __le64 *pg_dir; 6654 u32 flags = 0; 6655 u8 *pg_attr; 6656 u32 ena; 6657 int i; 6658 6659 if (!ctx) 6660 return 0; 6661 6662 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_BACKING_STORE_CFG, -1, -1); 6663 req.enables = cpu_to_le32(enables); 6664 6665 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP) { 6666 ctx_pg = &ctx->qp_mem; 6667 req.qp_num_entries = cpu_to_le32(ctx_pg->entries); 6668 req.qp_num_qp1_entries = cpu_to_le16(ctx->qp_min_qp1_entries); 6669 req.qp_num_l2_entries = cpu_to_le16(ctx->qp_max_l2_entries); 6670 req.qp_entry_size = cpu_to_le16(ctx->qp_entry_size); 6671 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, 6672 &req.qpc_pg_size_qpc_lvl, 6673 &req.qpc_page_dir); 6674 } 6675 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ) { 6676 ctx_pg = &ctx->srq_mem; 6677 req.srq_num_entries = cpu_to_le32(ctx_pg->entries); 6678 req.srq_num_l2_entries = cpu_to_le16(ctx->srq_max_l2_entries); 6679 req.srq_entry_size = cpu_to_le16(ctx->srq_entry_size); 6680 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, 6681 &req.srq_pg_size_srq_lvl, 6682 &req.srq_page_dir); 6683 } 6684 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ) { 6685 ctx_pg = &ctx->cq_mem; 6686 req.cq_num_entries = cpu_to_le32(ctx_pg->entries); 6687 req.cq_num_l2_entries = cpu_to_le16(ctx->cq_max_l2_entries); 6688 req.cq_entry_size = cpu_to_le16(ctx->cq_entry_size); 6689 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, &req.cq_pg_size_cq_lvl, 6690 &req.cq_page_dir); 6691 } 6692 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC) { 6693 ctx_pg = &ctx->vnic_mem; 6694 req.vnic_num_vnic_entries = 6695 cpu_to_le16(ctx->vnic_max_vnic_entries); 6696 req.vnic_num_ring_table_entries = 6697 cpu_to_le16(ctx->vnic_max_ring_table_entries); 6698 req.vnic_entry_size = cpu_to_le16(ctx->vnic_entry_size); 6699 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, 6700 &req.vnic_pg_size_vnic_lvl, 6701 &req.vnic_page_dir); 6702 } 6703 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT) { 6704 ctx_pg = &ctx->stat_mem; 6705 req.stat_num_entries = cpu_to_le32(ctx->stat_max_entries); 6706 req.stat_entry_size = cpu_to_le16(ctx->stat_entry_size); 6707 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, 6708 &req.stat_pg_size_stat_lvl, 6709 &req.stat_page_dir); 6710 } 6711 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV) { 6712 ctx_pg = &ctx->mrav_mem; 6713 req.mrav_num_entries = cpu_to_le32(ctx_pg->entries); 6714 if (ctx->mrav_num_entries_units) 6715 flags |= 6716 FUNC_BACKING_STORE_CFG_REQ_FLAGS_MRAV_RESERVATION_SPLIT; 6717 req.mrav_entry_size = cpu_to_le16(ctx->mrav_entry_size); 6718 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, 6719 &req.mrav_pg_size_mrav_lvl, 6720 &req.mrav_page_dir); 6721 } 6722 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM) { 6723 ctx_pg = &ctx->tim_mem; 6724 req.tim_num_entries = cpu_to_le32(ctx_pg->entries); 6725 req.tim_entry_size = cpu_to_le16(ctx->tim_entry_size); 6726 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, 6727 &req.tim_pg_size_tim_lvl, 6728 &req.tim_page_dir); 6729 } 6730 for (i = 0, num_entries = &req.tqm_sp_num_entries, 6731 pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl, 6732 pg_dir = &req.tqm_sp_page_dir, 6733 ena = FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP; 6734 i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) { 6735 if (!(enables & ena)) 6736 continue; 6737 6738 req.tqm_entry_size = cpu_to_le16(ctx->tqm_entry_size); 6739 ctx_pg = ctx->tqm_mem[i]; 6740 *num_entries = cpu_to_le32(ctx_pg->entries); 6741 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir); 6742 } 6743 req.flags = cpu_to_le32(flags); 6744 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 6745 } 6746 6747 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp, 6748 struct bnxt_ctx_pg_info *ctx_pg) 6749 { 6750 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem; 6751 6752 rmem->page_size = BNXT_PAGE_SIZE; 6753 rmem->pg_arr = ctx_pg->ctx_pg_arr; 6754 rmem->dma_arr = ctx_pg->ctx_dma_arr; 6755 rmem->flags = BNXT_RMEM_VALID_PTE_FLAG; 6756 if (rmem->depth >= 1) 6757 rmem->flags |= BNXT_RMEM_USE_FULL_PAGE_FLAG; 6758 return bnxt_alloc_ring(bp, rmem); 6759 } 6760 6761 static int bnxt_alloc_ctx_pg_tbls(struct bnxt *bp, 6762 struct bnxt_ctx_pg_info *ctx_pg, u32 mem_size, 6763 u8 depth, bool use_init_val) 6764 { 6765 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem; 6766 int rc; 6767 6768 if (!mem_size) 6769 return -EINVAL; 6770 6771 ctx_pg->nr_pages = DIV_ROUND_UP(mem_size, BNXT_PAGE_SIZE); 6772 if (ctx_pg->nr_pages > MAX_CTX_TOTAL_PAGES) { 6773 ctx_pg->nr_pages = 0; 6774 return -EINVAL; 6775 } 6776 if (ctx_pg->nr_pages > MAX_CTX_PAGES || depth > 1) { 6777 int nr_tbls, i; 6778 6779 rmem->depth = 2; 6780 ctx_pg->ctx_pg_tbl = kcalloc(MAX_CTX_PAGES, sizeof(ctx_pg), 6781 GFP_KERNEL); 6782 if (!ctx_pg->ctx_pg_tbl) 6783 return -ENOMEM; 6784 nr_tbls = DIV_ROUND_UP(ctx_pg->nr_pages, MAX_CTX_PAGES); 6785 rmem->nr_pages = nr_tbls; 6786 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg); 6787 if (rc) 6788 return rc; 6789 for (i = 0; i < nr_tbls; i++) { 6790 struct bnxt_ctx_pg_info *pg_tbl; 6791 6792 pg_tbl = kzalloc(sizeof(*pg_tbl), GFP_KERNEL); 6793 if (!pg_tbl) 6794 return -ENOMEM; 6795 ctx_pg->ctx_pg_tbl[i] = pg_tbl; 6796 rmem = &pg_tbl->ring_mem; 6797 rmem->pg_tbl = ctx_pg->ctx_pg_arr[i]; 6798 rmem->pg_tbl_map = ctx_pg->ctx_dma_arr[i]; 6799 rmem->depth = 1; 6800 rmem->nr_pages = MAX_CTX_PAGES; 6801 if (use_init_val) 6802 rmem->init_val = bp->ctx->ctx_kind_initializer; 6803 if (i == (nr_tbls - 1)) { 6804 int rem = ctx_pg->nr_pages % MAX_CTX_PAGES; 6805 6806 if (rem) 6807 rmem->nr_pages = rem; 6808 } 6809 rc = bnxt_alloc_ctx_mem_blk(bp, pg_tbl); 6810 if (rc) 6811 break; 6812 } 6813 } else { 6814 rmem->nr_pages = DIV_ROUND_UP(mem_size, BNXT_PAGE_SIZE); 6815 if (rmem->nr_pages > 1 || depth) 6816 rmem->depth = 1; 6817 if (use_init_val) 6818 rmem->init_val = bp->ctx->ctx_kind_initializer; 6819 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg); 6820 } 6821 return rc; 6822 } 6823 6824 static void bnxt_free_ctx_pg_tbls(struct bnxt *bp, 6825 struct bnxt_ctx_pg_info *ctx_pg) 6826 { 6827 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem; 6828 6829 if (rmem->depth > 1 || ctx_pg->nr_pages > MAX_CTX_PAGES || 6830 ctx_pg->ctx_pg_tbl) { 6831 int i, nr_tbls = rmem->nr_pages; 6832 6833 for (i = 0; i < nr_tbls; i++) { 6834 struct bnxt_ctx_pg_info *pg_tbl; 6835 struct bnxt_ring_mem_info *rmem2; 6836 6837 pg_tbl = ctx_pg->ctx_pg_tbl[i]; 6838 if (!pg_tbl) 6839 continue; 6840 rmem2 = &pg_tbl->ring_mem; 6841 bnxt_free_ring(bp, rmem2); 6842 ctx_pg->ctx_pg_arr[i] = NULL; 6843 kfree(pg_tbl); 6844 ctx_pg->ctx_pg_tbl[i] = NULL; 6845 } 6846 kfree(ctx_pg->ctx_pg_tbl); 6847 ctx_pg->ctx_pg_tbl = NULL; 6848 } 6849 bnxt_free_ring(bp, rmem); 6850 ctx_pg->nr_pages = 0; 6851 } 6852 6853 static void bnxt_free_ctx_mem(struct bnxt *bp) 6854 { 6855 struct bnxt_ctx_mem_info *ctx = bp->ctx; 6856 int i; 6857 6858 if (!ctx) 6859 return; 6860 6861 if (ctx->tqm_mem[0]) { 6862 for (i = 0; i < ctx->tqm_fp_rings_count + 1; i++) 6863 bnxt_free_ctx_pg_tbls(bp, ctx->tqm_mem[i]); 6864 kfree(ctx->tqm_mem[0]); 6865 ctx->tqm_mem[0] = NULL; 6866 } 6867 6868 bnxt_free_ctx_pg_tbls(bp, &ctx->tim_mem); 6869 bnxt_free_ctx_pg_tbls(bp, &ctx->mrav_mem); 6870 bnxt_free_ctx_pg_tbls(bp, &ctx->stat_mem); 6871 bnxt_free_ctx_pg_tbls(bp, &ctx->vnic_mem); 6872 bnxt_free_ctx_pg_tbls(bp, &ctx->cq_mem); 6873 bnxt_free_ctx_pg_tbls(bp, &ctx->srq_mem); 6874 bnxt_free_ctx_pg_tbls(bp, &ctx->qp_mem); 6875 ctx->flags &= ~BNXT_CTX_FLAG_INITED; 6876 } 6877 6878 static int bnxt_alloc_ctx_mem(struct bnxt *bp) 6879 { 6880 struct bnxt_ctx_pg_info *ctx_pg; 6881 struct bnxt_ctx_mem_info *ctx; 6882 u32 mem_size, ena, entries; 6883 u32 entries_sp, min; 6884 u32 num_mr, num_ah; 6885 u32 extra_srqs = 0; 6886 u32 extra_qps = 0; 6887 u8 pg_lvl = 1; 6888 int i, rc; 6889 6890 rc = bnxt_hwrm_func_backing_store_qcaps(bp); 6891 if (rc) { 6892 netdev_err(bp->dev, "Failed querying context mem capability, rc = %d.\n", 6893 rc); 6894 return rc; 6895 } 6896 ctx = bp->ctx; 6897 if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED)) 6898 return 0; 6899 6900 if ((bp->flags & BNXT_FLAG_ROCE_CAP) && !is_kdump_kernel()) { 6901 pg_lvl = 2; 6902 extra_qps = 65536; 6903 extra_srqs = 8192; 6904 } 6905 6906 ctx_pg = &ctx->qp_mem; 6907 ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries + 6908 extra_qps; 6909 mem_size = ctx->qp_entry_size * ctx_pg->entries; 6910 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, pg_lvl, true); 6911 if (rc) 6912 return rc; 6913 6914 ctx_pg = &ctx->srq_mem; 6915 ctx_pg->entries = ctx->srq_max_l2_entries + extra_srqs; 6916 mem_size = ctx->srq_entry_size * ctx_pg->entries; 6917 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, pg_lvl, true); 6918 if (rc) 6919 return rc; 6920 6921 ctx_pg = &ctx->cq_mem; 6922 ctx_pg->entries = ctx->cq_max_l2_entries + extra_qps * 2; 6923 mem_size = ctx->cq_entry_size * ctx_pg->entries; 6924 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, pg_lvl, true); 6925 if (rc) 6926 return rc; 6927 6928 ctx_pg = &ctx->vnic_mem; 6929 ctx_pg->entries = ctx->vnic_max_vnic_entries + 6930 ctx->vnic_max_ring_table_entries; 6931 mem_size = ctx->vnic_entry_size * ctx_pg->entries; 6932 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1, true); 6933 if (rc) 6934 return rc; 6935 6936 ctx_pg = &ctx->stat_mem; 6937 ctx_pg->entries = ctx->stat_max_entries; 6938 mem_size = ctx->stat_entry_size * ctx_pg->entries; 6939 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1, true); 6940 if (rc) 6941 return rc; 6942 6943 ena = 0; 6944 if (!(bp->flags & BNXT_FLAG_ROCE_CAP)) 6945 goto skip_rdma; 6946 6947 ctx_pg = &ctx->mrav_mem; 6948 /* 128K extra is needed to accommodate static AH context 6949 * allocation by f/w. 6950 */ 6951 num_mr = 1024 * 256; 6952 num_ah = 1024 * 128; 6953 ctx_pg->entries = num_mr + num_ah; 6954 mem_size = ctx->mrav_entry_size * ctx_pg->entries; 6955 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 2, true); 6956 if (rc) 6957 return rc; 6958 ena = FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV; 6959 if (ctx->mrav_num_entries_units) 6960 ctx_pg->entries = 6961 ((num_mr / ctx->mrav_num_entries_units) << 16) | 6962 (num_ah / ctx->mrav_num_entries_units); 6963 6964 ctx_pg = &ctx->tim_mem; 6965 ctx_pg->entries = ctx->qp_mem.entries; 6966 mem_size = ctx->tim_entry_size * ctx_pg->entries; 6967 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1, false); 6968 if (rc) 6969 return rc; 6970 ena |= FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM; 6971 6972 skip_rdma: 6973 min = ctx->tqm_min_entries_per_ring; 6974 entries_sp = ctx->vnic_max_vnic_entries + ctx->qp_max_l2_entries + 6975 2 * (extra_qps + ctx->qp_min_qp1_entries) + min; 6976 entries_sp = roundup(entries_sp, ctx->tqm_entries_multiple); 6977 entries = ctx->qp_max_l2_entries + extra_qps + ctx->qp_min_qp1_entries; 6978 entries = roundup(entries, ctx->tqm_entries_multiple); 6979 entries = clamp_t(u32, entries, min, ctx->tqm_max_entries_per_ring); 6980 for (i = 0; i < ctx->tqm_fp_rings_count + 1; i++) { 6981 ctx_pg = ctx->tqm_mem[i]; 6982 ctx_pg->entries = i ? entries : entries_sp; 6983 mem_size = ctx->tqm_entry_size * ctx_pg->entries; 6984 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1, false); 6985 if (rc) 6986 return rc; 6987 ena |= FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP << i; 6988 } 6989 ena |= FUNC_BACKING_STORE_CFG_REQ_DFLT_ENABLES; 6990 rc = bnxt_hwrm_func_backing_store_cfg(bp, ena); 6991 if (rc) { 6992 netdev_err(bp->dev, "Failed configuring context mem, rc = %d.\n", 6993 rc); 6994 return rc; 6995 } 6996 ctx->flags |= BNXT_CTX_FLAG_INITED; 6997 return 0; 6998 } 6999 7000 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp, bool all) 7001 { 7002 struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr; 7003 struct hwrm_func_resource_qcaps_input req = {0}; 7004 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 7005 int rc; 7006 7007 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESOURCE_QCAPS, -1, -1); 7008 req.fid = cpu_to_le16(0xffff); 7009 7010 mutex_lock(&bp->hwrm_cmd_lock); 7011 rc = _hwrm_send_message_silent(bp, &req, sizeof(req), 7012 HWRM_CMD_TIMEOUT); 7013 if (rc) 7014 goto hwrm_func_resc_qcaps_exit; 7015 7016 hw_resc->max_tx_sch_inputs = le16_to_cpu(resp->max_tx_scheduler_inputs); 7017 if (!all) 7018 goto hwrm_func_resc_qcaps_exit; 7019 7020 hw_resc->min_rsscos_ctxs = le16_to_cpu(resp->min_rsscos_ctx); 7021 hw_resc->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx); 7022 hw_resc->min_cp_rings = le16_to_cpu(resp->min_cmpl_rings); 7023 hw_resc->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings); 7024 hw_resc->min_tx_rings = le16_to_cpu(resp->min_tx_rings); 7025 hw_resc->max_tx_rings = le16_to_cpu(resp->max_tx_rings); 7026 hw_resc->min_rx_rings = le16_to_cpu(resp->min_rx_rings); 7027 hw_resc->max_rx_rings = le16_to_cpu(resp->max_rx_rings); 7028 hw_resc->min_hw_ring_grps = le16_to_cpu(resp->min_hw_ring_grps); 7029 hw_resc->max_hw_ring_grps = le16_to_cpu(resp->max_hw_ring_grps); 7030 hw_resc->min_l2_ctxs = le16_to_cpu(resp->min_l2_ctxs); 7031 hw_resc->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs); 7032 hw_resc->min_vnics = le16_to_cpu(resp->min_vnics); 7033 hw_resc->max_vnics = le16_to_cpu(resp->max_vnics); 7034 hw_resc->min_stat_ctxs = le16_to_cpu(resp->min_stat_ctx); 7035 hw_resc->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx); 7036 7037 if (bp->flags & BNXT_FLAG_CHIP_P5) { 7038 u16 max_msix = le16_to_cpu(resp->max_msix); 7039 7040 hw_resc->max_nqs = max_msix; 7041 hw_resc->max_hw_ring_grps = hw_resc->max_rx_rings; 7042 } 7043 7044 if (BNXT_PF(bp)) { 7045 struct bnxt_pf_info *pf = &bp->pf; 7046 7047 pf->vf_resv_strategy = 7048 le16_to_cpu(resp->vf_reservation_strategy); 7049 if (pf->vf_resv_strategy > BNXT_VF_RESV_STRATEGY_MINIMAL_STATIC) 7050 pf->vf_resv_strategy = BNXT_VF_RESV_STRATEGY_MAXIMAL; 7051 } 7052 hwrm_func_resc_qcaps_exit: 7053 mutex_unlock(&bp->hwrm_cmd_lock); 7054 return rc; 7055 } 7056 7057 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp) 7058 { 7059 int rc = 0; 7060 struct hwrm_func_qcaps_input req = {0}; 7061 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr; 7062 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 7063 u32 flags, flags_ext; 7064 7065 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCAPS, -1, -1); 7066 req.fid = cpu_to_le16(0xffff); 7067 7068 mutex_lock(&bp->hwrm_cmd_lock); 7069 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 7070 if (rc) 7071 goto hwrm_func_qcaps_exit; 7072 7073 flags = le32_to_cpu(resp->flags); 7074 if (flags & FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED) 7075 bp->flags |= BNXT_FLAG_ROCEV1_CAP; 7076 if (flags & FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED) 7077 bp->flags |= BNXT_FLAG_ROCEV2_CAP; 7078 if (flags & FUNC_QCAPS_RESP_FLAGS_PCIE_STATS_SUPPORTED) 7079 bp->fw_cap |= BNXT_FW_CAP_PCIE_STATS_SUPPORTED; 7080 if (flags & FUNC_QCAPS_RESP_FLAGS_HOT_RESET_CAPABLE) 7081 bp->fw_cap |= BNXT_FW_CAP_HOT_RESET; 7082 if (flags & FUNC_QCAPS_RESP_FLAGS_EXT_STATS_SUPPORTED) 7083 bp->fw_cap |= BNXT_FW_CAP_EXT_STATS_SUPPORTED; 7084 if (flags & FUNC_QCAPS_RESP_FLAGS_ERROR_RECOVERY_CAPABLE) 7085 bp->fw_cap |= BNXT_FW_CAP_ERROR_RECOVERY; 7086 if (flags & FUNC_QCAPS_RESP_FLAGS_ERR_RECOVER_RELOAD) 7087 bp->fw_cap |= BNXT_FW_CAP_ERR_RECOVER_RELOAD; 7088 if (!(flags & FUNC_QCAPS_RESP_FLAGS_VLAN_ACCELERATION_TX_DISABLED)) 7089 bp->fw_cap |= BNXT_FW_CAP_VLAN_TX_INSERT; 7090 7091 flags_ext = le32_to_cpu(resp->flags_ext); 7092 if (flags_ext & FUNC_QCAPS_RESP_FLAGS_EXT_EXT_HW_STATS_SUPPORTED) 7093 bp->fw_cap |= BNXT_FW_CAP_EXT_HW_STATS_SUPPORTED; 7094 7095 bp->tx_push_thresh = 0; 7096 if ((flags & FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED) && 7097 BNXT_FW_MAJ(bp) > 217) 7098 bp->tx_push_thresh = BNXT_TX_PUSH_THRESH; 7099 7100 hw_resc->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx); 7101 hw_resc->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings); 7102 hw_resc->max_tx_rings = le16_to_cpu(resp->max_tx_rings); 7103 hw_resc->max_rx_rings = le16_to_cpu(resp->max_rx_rings); 7104 hw_resc->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps); 7105 if (!hw_resc->max_hw_ring_grps) 7106 hw_resc->max_hw_ring_grps = hw_resc->max_tx_rings; 7107 hw_resc->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs); 7108 hw_resc->max_vnics = le16_to_cpu(resp->max_vnics); 7109 hw_resc->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx); 7110 7111 if (BNXT_PF(bp)) { 7112 struct bnxt_pf_info *pf = &bp->pf; 7113 7114 pf->fw_fid = le16_to_cpu(resp->fid); 7115 pf->port_id = le16_to_cpu(resp->port_id); 7116 memcpy(pf->mac_addr, resp->mac_address, ETH_ALEN); 7117 pf->first_vf_id = le16_to_cpu(resp->first_vf_id); 7118 pf->max_vfs = le16_to_cpu(resp->max_vfs); 7119 pf->max_encap_records = le32_to_cpu(resp->max_encap_records); 7120 pf->max_decap_records = le32_to_cpu(resp->max_decap_records); 7121 pf->max_tx_em_flows = le32_to_cpu(resp->max_tx_em_flows); 7122 pf->max_tx_wm_flows = le32_to_cpu(resp->max_tx_wm_flows); 7123 pf->max_rx_em_flows = le32_to_cpu(resp->max_rx_em_flows); 7124 pf->max_rx_wm_flows = le32_to_cpu(resp->max_rx_wm_flows); 7125 bp->flags &= ~BNXT_FLAG_WOL_CAP; 7126 if (flags & FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED) 7127 bp->flags |= BNXT_FLAG_WOL_CAP; 7128 } else { 7129 #ifdef CONFIG_BNXT_SRIOV 7130 struct bnxt_vf_info *vf = &bp->vf; 7131 7132 vf->fw_fid = le16_to_cpu(resp->fid); 7133 memcpy(vf->mac_addr, resp->mac_address, ETH_ALEN); 7134 #endif 7135 } 7136 7137 hwrm_func_qcaps_exit: 7138 mutex_unlock(&bp->hwrm_cmd_lock); 7139 return rc; 7140 } 7141 7142 static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp); 7143 7144 static int bnxt_hwrm_func_qcaps(struct bnxt *bp) 7145 { 7146 int rc; 7147 7148 rc = __bnxt_hwrm_func_qcaps(bp); 7149 if (rc) 7150 return rc; 7151 rc = bnxt_hwrm_queue_qportcfg(bp); 7152 if (rc) { 7153 netdev_err(bp->dev, "hwrm query qportcfg failure rc: %d\n", rc); 7154 return rc; 7155 } 7156 if (bp->hwrm_spec_code >= 0x10803) { 7157 rc = bnxt_alloc_ctx_mem(bp); 7158 if (rc) 7159 return rc; 7160 rc = bnxt_hwrm_func_resc_qcaps(bp, true); 7161 if (!rc) 7162 bp->fw_cap |= BNXT_FW_CAP_NEW_RM; 7163 } 7164 return 0; 7165 } 7166 7167 static int bnxt_hwrm_cfa_adv_flow_mgnt_qcaps(struct bnxt *bp) 7168 { 7169 struct hwrm_cfa_adv_flow_mgnt_qcaps_input req = {0}; 7170 struct hwrm_cfa_adv_flow_mgnt_qcaps_output *resp; 7171 int rc = 0; 7172 u32 flags; 7173 7174 if (!(bp->fw_cap & BNXT_FW_CAP_CFA_ADV_FLOW)) 7175 return 0; 7176 7177 resp = bp->hwrm_cmd_resp_addr; 7178 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_ADV_FLOW_MGNT_QCAPS, -1, -1); 7179 7180 mutex_lock(&bp->hwrm_cmd_lock); 7181 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 7182 if (rc) 7183 goto hwrm_cfa_adv_qcaps_exit; 7184 7185 flags = le32_to_cpu(resp->flags); 7186 if (flags & 7187 CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RFS_RING_TBL_IDX_V2_SUPPORTED) 7188 bp->fw_cap |= BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V2; 7189 7190 hwrm_cfa_adv_qcaps_exit: 7191 mutex_unlock(&bp->hwrm_cmd_lock); 7192 return rc; 7193 } 7194 7195 static int bnxt_map_fw_health_regs(struct bnxt *bp) 7196 { 7197 struct bnxt_fw_health *fw_health = bp->fw_health; 7198 u32 reg_base = 0xffffffff; 7199 int i; 7200 7201 /* Only pre-map the monitoring GRC registers using window 3 */ 7202 for (i = 0; i < 4; i++) { 7203 u32 reg = fw_health->regs[i]; 7204 7205 if (BNXT_FW_HEALTH_REG_TYPE(reg) != BNXT_FW_HEALTH_REG_TYPE_GRC) 7206 continue; 7207 if (reg_base == 0xffffffff) 7208 reg_base = reg & BNXT_GRC_BASE_MASK; 7209 if ((reg & BNXT_GRC_BASE_MASK) != reg_base) 7210 return -ERANGE; 7211 fw_health->mapped_regs[i] = BNXT_FW_HEALTH_WIN_BASE + 7212 (reg & BNXT_GRC_OFFSET_MASK); 7213 } 7214 if (reg_base == 0xffffffff) 7215 return 0; 7216 7217 writel(reg_base, bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 7218 BNXT_FW_HEALTH_WIN_MAP_OFF); 7219 return 0; 7220 } 7221 7222 static int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp) 7223 { 7224 struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr; 7225 struct bnxt_fw_health *fw_health = bp->fw_health; 7226 struct hwrm_error_recovery_qcfg_input req = {0}; 7227 int rc, i; 7228 7229 if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)) 7230 return 0; 7231 7232 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_ERROR_RECOVERY_QCFG, -1, -1); 7233 mutex_lock(&bp->hwrm_cmd_lock); 7234 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 7235 if (rc) 7236 goto err_recovery_out; 7237 fw_health->flags = le32_to_cpu(resp->flags); 7238 if ((fw_health->flags & ERROR_RECOVERY_QCFG_RESP_FLAGS_CO_CPU) && 7239 !(bp->fw_cap & BNXT_FW_CAP_KONG_MB_CHNL)) { 7240 rc = -EINVAL; 7241 goto err_recovery_out; 7242 } 7243 fw_health->polling_dsecs = le32_to_cpu(resp->driver_polling_freq); 7244 fw_health->master_func_wait_dsecs = 7245 le32_to_cpu(resp->master_func_wait_period); 7246 fw_health->normal_func_wait_dsecs = 7247 le32_to_cpu(resp->normal_func_wait_period); 7248 fw_health->post_reset_wait_dsecs = 7249 le32_to_cpu(resp->master_func_wait_period_after_reset); 7250 fw_health->post_reset_max_wait_dsecs = 7251 le32_to_cpu(resp->max_bailout_time_after_reset); 7252 fw_health->regs[BNXT_FW_HEALTH_REG] = 7253 le32_to_cpu(resp->fw_health_status_reg); 7254 fw_health->regs[BNXT_FW_HEARTBEAT_REG] = 7255 le32_to_cpu(resp->fw_heartbeat_reg); 7256 fw_health->regs[BNXT_FW_RESET_CNT_REG] = 7257 le32_to_cpu(resp->fw_reset_cnt_reg); 7258 fw_health->regs[BNXT_FW_RESET_INPROG_REG] = 7259 le32_to_cpu(resp->reset_inprogress_reg); 7260 fw_health->fw_reset_inprog_reg_mask = 7261 le32_to_cpu(resp->reset_inprogress_reg_mask); 7262 fw_health->fw_reset_seq_cnt = resp->reg_array_cnt; 7263 if (fw_health->fw_reset_seq_cnt >= 16) { 7264 rc = -EINVAL; 7265 goto err_recovery_out; 7266 } 7267 for (i = 0; i < fw_health->fw_reset_seq_cnt; i++) { 7268 fw_health->fw_reset_seq_regs[i] = 7269 le32_to_cpu(resp->reset_reg[i]); 7270 fw_health->fw_reset_seq_vals[i] = 7271 le32_to_cpu(resp->reset_reg_val[i]); 7272 fw_health->fw_reset_seq_delay_msec[i] = 7273 resp->delay_after_reset[i]; 7274 } 7275 err_recovery_out: 7276 mutex_unlock(&bp->hwrm_cmd_lock); 7277 if (!rc) 7278 rc = bnxt_map_fw_health_regs(bp); 7279 if (rc) 7280 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY; 7281 return rc; 7282 } 7283 7284 static int bnxt_hwrm_func_reset(struct bnxt *bp) 7285 { 7286 struct hwrm_func_reset_input req = {0}; 7287 7288 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESET, -1, -1); 7289 req.enables = 0; 7290 7291 return hwrm_send_message(bp, &req, sizeof(req), HWRM_RESET_TIMEOUT); 7292 } 7293 7294 static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp) 7295 { 7296 int rc = 0; 7297 struct hwrm_queue_qportcfg_input req = {0}; 7298 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr; 7299 u8 i, j, *qptr; 7300 bool no_rdma; 7301 7302 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_QUEUE_QPORTCFG, -1, -1); 7303 7304 mutex_lock(&bp->hwrm_cmd_lock); 7305 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 7306 if (rc) 7307 goto qportcfg_exit; 7308 7309 if (!resp->max_configurable_queues) { 7310 rc = -EINVAL; 7311 goto qportcfg_exit; 7312 } 7313 bp->max_tc = resp->max_configurable_queues; 7314 bp->max_lltc = resp->max_configurable_lossless_queues; 7315 if (bp->max_tc > BNXT_MAX_QUEUE) 7316 bp->max_tc = BNXT_MAX_QUEUE; 7317 7318 no_rdma = !(bp->flags & BNXT_FLAG_ROCE_CAP); 7319 qptr = &resp->queue_id0; 7320 for (i = 0, j = 0; i < bp->max_tc; i++) { 7321 bp->q_info[j].queue_id = *qptr; 7322 bp->q_ids[i] = *qptr++; 7323 bp->q_info[j].queue_profile = *qptr++; 7324 bp->tc_to_qidx[j] = j; 7325 if (!BNXT_CNPQ(bp->q_info[j].queue_profile) || 7326 (no_rdma && BNXT_PF(bp))) 7327 j++; 7328 } 7329 bp->max_q = bp->max_tc; 7330 bp->max_tc = max_t(u8, j, 1); 7331 7332 if (resp->queue_cfg_info & QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG) 7333 bp->max_tc = 1; 7334 7335 if (bp->max_lltc > bp->max_tc) 7336 bp->max_lltc = bp->max_tc; 7337 7338 qportcfg_exit: 7339 mutex_unlock(&bp->hwrm_cmd_lock); 7340 return rc; 7341 } 7342 7343 static int __bnxt_hwrm_ver_get(struct bnxt *bp, bool silent) 7344 { 7345 struct hwrm_ver_get_input req = {0}; 7346 int rc; 7347 7348 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VER_GET, -1, -1); 7349 req.hwrm_intf_maj = HWRM_VERSION_MAJOR; 7350 req.hwrm_intf_min = HWRM_VERSION_MINOR; 7351 req.hwrm_intf_upd = HWRM_VERSION_UPDATE; 7352 7353 rc = bnxt_hwrm_do_send_msg(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT, 7354 silent); 7355 return rc; 7356 } 7357 7358 static int bnxt_hwrm_ver_get(struct bnxt *bp) 7359 { 7360 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr; 7361 u16 fw_maj, fw_min, fw_bld, fw_rsv; 7362 u32 dev_caps_cfg, hwrm_ver; 7363 int rc, len; 7364 7365 bp->hwrm_max_req_len = HWRM_MAX_REQ_LEN; 7366 mutex_lock(&bp->hwrm_cmd_lock); 7367 rc = __bnxt_hwrm_ver_get(bp, false); 7368 if (rc) 7369 goto hwrm_ver_get_exit; 7370 7371 memcpy(&bp->ver_resp, resp, sizeof(struct hwrm_ver_get_output)); 7372 7373 bp->hwrm_spec_code = resp->hwrm_intf_maj_8b << 16 | 7374 resp->hwrm_intf_min_8b << 8 | 7375 resp->hwrm_intf_upd_8b; 7376 if (resp->hwrm_intf_maj_8b < 1) { 7377 netdev_warn(bp->dev, "HWRM interface %d.%d.%d is older than 1.0.0.\n", 7378 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b, 7379 resp->hwrm_intf_upd_8b); 7380 netdev_warn(bp->dev, "Please update firmware with HWRM interface 1.0.0 or newer.\n"); 7381 } 7382 7383 hwrm_ver = HWRM_VERSION_MAJOR << 16 | HWRM_VERSION_MINOR << 8 | 7384 HWRM_VERSION_UPDATE; 7385 7386 if (bp->hwrm_spec_code > hwrm_ver) 7387 snprintf(bp->hwrm_ver_supp, FW_VER_STR_LEN, "%d.%d.%d", 7388 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, 7389 HWRM_VERSION_UPDATE); 7390 else 7391 snprintf(bp->hwrm_ver_supp, FW_VER_STR_LEN, "%d.%d.%d", 7392 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b, 7393 resp->hwrm_intf_upd_8b); 7394 7395 fw_maj = le16_to_cpu(resp->hwrm_fw_major); 7396 if (bp->hwrm_spec_code > 0x10803 && fw_maj) { 7397 fw_min = le16_to_cpu(resp->hwrm_fw_minor); 7398 fw_bld = le16_to_cpu(resp->hwrm_fw_build); 7399 fw_rsv = le16_to_cpu(resp->hwrm_fw_patch); 7400 len = FW_VER_STR_LEN; 7401 } else { 7402 fw_maj = resp->hwrm_fw_maj_8b; 7403 fw_min = resp->hwrm_fw_min_8b; 7404 fw_bld = resp->hwrm_fw_bld_8b; 7405 fw_rsv = resp->hwrm_fw_rsvd_8b; 7406 len = BC_HWRM_STR_LEN; 7407 } 7408 bp->fw_ver_code = BNXT_FW_VER_CODE(fw_maj, fw_min, fw_bld, fw_rsv); 7409 snprintf(bp->fw_ver_str, len, "%d.%d.%d.%d", fw_maj, fw_min, fw_bld, 7410 fw_rsv); 7411 7412 if (strlen(resp->active_pkg_name)) { 7413 int fw_ver_len = strlen(bp->fw_ver_str); 7414 7415 snprintf(bp->fw_ver_str + fw_ver_len, 7416 FW_VER_STR_LEN - fw_ver_len - 1, "/pkg %s", 7417 resp->active_pkg_name); 7418 bp->fw_cap |= BNXT_FW_CAP_PKG_VER; 7419 } 7420 7421 bp->hwrm_cmd_timeout = le16_to_cpu(resp->def_req_timeout); 7422 if (!bp->hwrm_cmd_timeout) 7423 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT; 7424 7425 if (resp->hwrm_intf_maj_8b >= 1) { 7426 bp->hwrm_max_req_len = le16_to_cpu(resp->max_req_win_len); 7427 bp->hwrm_max_ext_req_len = le16_to_cpu(resp->max_ext_req_len); 7428 } 7429 if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN) 7430 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN; 7431 7432 bp->chip_num = le16_to_cpu(resp->chip_num); 7433 bp->chip_rev = resp->chip_rev; 7434 if (bp->chip_num == CHIP_NUM_58700 && !resp->chip_rev && 7435 !resp->chip_metal) 7436 bp->flags |= BNXT_FLAG_CHIP_NITRO_A0; 7437 7438 dev_caps_cfg = le32_to_cpu(resp->dev_caps_cfg); 7439 if ((dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) && 7440 (dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) 7441 bp->fw_cap |= BNXT_FW_CAP_SHORT_CMD; 7442 7443 if (dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) 7444 bp->fw_cap |= BNXT_FW_CAP_KONG_MB_CHNL; 7445 7446 if (dev_caps_cfg & 7447 VER_GET_RESP_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED) 7448 bp->fw_cap |= BNXT_FW_CAP_OVS_64BIT_HANDLE; 7449 7450 if (dev_caps_cfg & 7451 VER_GET_RESP_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED) 7452 bp->fw_cap |= BNXT_FW_CAP_TRUSTED_VF; 7453 7454 if (dev_caps_cfg & 7455 VER_GET_RESP_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED) 7456 bp->fw_cap |= BNXT_FW_CAP_CFA_ADV_FLOW; 7457 7458 hwrm_ver_get_exit: 7459 mutex_unlock(&bp->hwrm_cmd_lock); 7460 return rc; 7461 } 7462 7463 int bnxt_hwrm_fw_set_time(struct bnxt *bp) 7464 { 7465 struct hwrm_fw_set_time_input req = {0}; 7466 struct tm tm; 7467 time64_t now = ktime_get_real_seconds(); 7468 7469 if ((BNXT_VF(bp) && bp->hwrm_spec_code < 0x10901) || 7470 bp->hwrm_spec_code < 0x10400) 7471 return -EOPNOTSUPP; 7472 7473 time64_to_tm(now, 0, &tm); 7474 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FW_SET_TIME, -1, -1); 7475 req.year = cpu_to_le16(1900 + tm.tm_year); 7476 req.month = 1 + tm.tm_mon; 7477 req.day = tm.tm_mday; 7478 req.hour = tm.tm_hour; 7479 req.minute = tm.tm_min; 7480 req.second = tm.tm_sec; 7481 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 7482 } 7483 7484 static int bnxt_hwrm_port_qstats(struct bnxt *bp) 7485 { 7486 struct bnxt_pf_info *pf = &bp->pf; 7487 struct hwrm_port_qstats_input req = {0}; 7488 7489 if (!(bp->flags & BNXT_FLAG_PORT_STATS)) 7490 return 0; 7491 7492 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_QSTATS, -1, -1); 7493 req.port_id = cpu_to_le16(pf->port_id); 7494 req.tx_stat_host_addr = cpu_to_le64(bp->hw_tx_port_stats_map); 7495 req.rx_stat_host_addr = cpu_to_le64(bp->hw_rx_port_stats_map); 7496 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 7497 } 7498 7499 static int bnxt_hwrm_port_qstats_ext(struct bnxt *bp) 7500 { 7501 struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr; 7502 struct hwrm_queue_pri2cos_qcfg_input req2 = {0}; 7503 struct hwrm_port_qstats_ext_input req = {0}; 7504 struct bnxt_pf_info *pf = &bp->pf; 7505 u32 tx_stat_size; 7506 int rc; 7507 7508 if (!(bp->flags & BNXT_FLAG_PORT_STATS_EXT)) 7509 return 0; 7510 7511 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_QSTATS_EXT, -1, -1); 7512 req.port_id = cpu_to_le16(pf->port_id); 7513 req.rx_stat_size = cpu_to_le16(sizeof(struct rx_port_stats_ext)); 7514 req.rx_stat_host_addr = cpu_to_le64(bp->hw_rx_port_stats_ext_map); 7515 tx_stat_size = bp->hw_tx_port_stats_ext ? 7516 sizeof(*bp->hw_tx_port_stats_ext) : 0; 7517 req.tx_stat_size = cpu_to_le16(tx_stat_size); 7518 req.tx_stat_host_addr = cpu_to_le64(bp->hw_tx_port_stats_ext_map); 7519 mutex_lock(&bp->hwrm_cmd_lock); 7520 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 7521 if (!rc) { 7522 bp->fw_rx_stats_ext_size = le16_to_cpu(resp->rx_stat_size) / 8; 7523 bp->fw_tx_stats_ext_size = tx_stat_size ? 7524 le16_to_cpu(resp->tx_stat_size) / 8 : 0; 7525 } else { 7526 bp->fw_rx_stats_ext_size = 0; 7527 bp->fw_tx_stats_ext_size = 0; 7528 } 7529 if (bp->fw_tx_stats_ext_size <= 7530 offsetof(struct tx_port_stats_ext, pfc_pri0_tx_duration_us) / 8) { 7531 mutex_unlock(&bp->hwrm_cmd_lock); 7532 bp->pri2cos_valid = 0; 7533 return rc; 7534 } 7535 7536 bnxt_hwrm_cmd_hdr_init(bp, &req2, HWRM_QUEUE_PRI2COS_QCFG, -1, -1); 7537 req2.flags = cpu_to_le32(QUEUE_PRI2COS_QCFG_REQ_FLAGS_IVLAN); 7538 7539 rc = _hwrm_send_message(bp, &req2, sizeof(req2), HWRM_CMD_TIMEOUT); 7540 if (!rc) { 7541 struct hwrm_queue_pri2cos_qcfg_output *resp2; 7542 u8 *pri2cos; 7543 int i, j; 7544 7545 resp2 = bp->hwrm_cmd_resp_addr; 7546 pri2cos = &resp2->pri0_cos_queue_id; 7547 for (i = 0; i < 8; i++) { 7548 u8 queue_id = pri2cos[i]; 7549 u8 queue_idx; 7550 7551 /* Per port queue IDs start from 0, 10, 20, etc */ 7552 queue_idx = queue_id % 10; 7553 if (queue_idx > BNXT_MAX_QUEUE) { 7554 bp->pri2cos_valid = false; 7555 goto qstats_done; 7556 } 7557 for (j = 0; j < bp->max_q; j++) { 7558 if (bp->q_ids[j] == queue_id) 7559 bp->pri2cos_idx[i] = queue_idx; 7560 } 7561 } 7562 bp->pri2cos_valid = 1; 7563 } 7564 qstats_done: 7565 mutex_unlock(&bp->hwrm_cmd_lock); 7566 return rc; 7567 } 7568 7569 static int bnxt_hwrm_pcie_qstats(struct bnxt *bp) 7570 { 7571 struct hwrm_pcie_qstats_input req = {0}; 7572 7573 if (!(bp->flags & BNXT_FLAG_PCIE_STATS)) 7574 return 0; 7575 7576 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PCIE_QSTATS, -1, -1); 7577 req.pcie_stat_size = cpu_to_le16(sizeof(struct pcie_ctx_hw_stats)); 7578 req.pcie_stat_host_addr = cpu_to_le64(bp->hw_pcie_stats_map); 7579 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 7580 } 7581 7582 static void bnxt_hwrm_free_tunnel_ports(struct bnxt *bp) 7583 { 7584 if (bp->vxlan_fw_dst_port_id != INVALID_HW_RING_ID) 7585 bnxt_hwrm_tunnel_dst_port_free( 7586 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN); 7587 if (bp->nge_fw_dst_port_id != INVALID_HW_RING_ID) 7588 bnxt_hwrm_tunnel_dst_port_free( 7589 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE); 7590 } 7591 7592 static int bnxt_set_tpa(struct bnxt *bp, bool set_tpa) 7593 { 7594 int rc, i; 7595 u32 tpa_flags = 0; 7596 7597 if (set_tpa) 7598 tpa_flags = bp->flags & BNXT_FLAG_TPA; 7599 else if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state)) 7600 return 0; 7601 for (i = 0; i < bp->nr_vnics; i++) { 7602 rc = bnxt_hwrm_vnic_set_tpa(bp, i, tpa_flags); 7603 if (rc) { 7604 netdev_err(bp->dev, "hwrm vnic set tpa failure rc for vnic %d: %x\n", 7605 i, rc); 7606 return rc; 7607 } 7608 } 7609 return 0; 7610 } 7611 7612 static void bnxt_hwrm_clear_vnic_rss(struct bnxt *bp) 7613 { 7614 int i; 7615 7616 for (i = 0; i < bp->nr_vnics; i++) 7617 bnxt_hwrm_vnic_set_rss(bp, i, false); 7618 } 7619 7620 static void bnxt_clear_vnic(struct bnxt *bp) 7621 { 7622 if (!bp->vnic_info) 7623 return; 7624 7625 bnxt_hwrm_clear_vnic_filter(bp); 7626 if (!(bp->flags & BNXT_FLAG_CHIP_P5)) { 7627 /* clear all RSS setting before free vnic ctx */ 7628 bnxt_hwrm_clear_vnic_rss(bp); 7629 bnxt_hwrm_vnic_ctx_free(bp); 7630 } 7631 /* before free the vnic, undo the vnic tpa settings */ 7632 if (bp->flags & BNXT_FLAG_TPA) 7633 bnxt_set_tpa(bp, false); 7634 bnxt_hwrm_vnic_free(bp); 7635 if (bp->flags & BNXT_FLAG_CHIP_P5) 7636 bnxt_hwrm_vnic_ctx_free(bp); 7637 } 7638 7639 static void bnxt_hwrm_resource_free(struct bnxt *bp, bool close_path, 7640 bool irq_re_init) 7641 { 7642 bnxt_clear_vnic(bp); 7643 bnxt_hwrm_ring_free(bp, close_path); 7644 bnxt_hwrm_ring_grp_free(bp); 7645 if (irq_re_init) { 7646 bnxt_hwrm_stat_ctx_free(bp); 7647 bnxt_hwrm_free_tunnel_ports(bp); 7648 } 7649 } 7650 7651 static int bnxt_hwrm_set_br_mode(struct bnxt *bp, u16 br_mode) 7652 { 7653 struct hwrm_func_cfg_input req = {0}; 7654 7655 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1); 7656 req.fid = cpu_to_le16(0xffff); 7657 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_EVB_MODE); 7658 if (br_mode == BRIDGE_MODE_VEB) 7659 req.evb_mode = FUNC_CFG_REQ_EVB_MODE_VEB; 7660 else if (br_mode == BRIDGE_MODE_VEPA) 7661 req.evb_mode = FUNC_CFG_REQ_EVB_MODE_VEPA; 7662 else 7663 return -EINVAL; 7664 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 7665 } 7666 7667 static int bnxt_hwrm_set_cache_line_size(struct bnxt *bp, int size) 7668 { 7669 struct hwrm_func_cfg_input req = {0}; 7670 7671 if (BNXT_VF(bp) || bp->hwrm_spec_code < 0x10803) 7672 return 0; 7673 7674 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1); 7675 req.fid = cpu_to_le16(0xffff); 7676 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_CACHE_LINESIZE); 7677 req.options = FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_64; 7678 if (size == 128) 7679 req.options = FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128; 7680 7681 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 7682 } 7683 7684 static int __bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id) 7685 { 7686 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 7687 int rc; 7688 7689 if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG) 7690 goto skip_rss_ctx; 7691 7692 /* allocate context for vnic */ 7693 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 0); 7694 if (rc) { 7695 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n", 7696 vnic_id, rc); 7697 goto vnic_setup_err; 7698 } 7699 bp->rsscos_nr_ctxs++; 7700 7701 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) { 7702 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 1); 7703 if (rc) { 7704 netdev_err(bp->dev, "hwrm vnic %d cos ctx alloc failure rc: %x\n", 7705 vnic_id, rc); 7706 goto vnic_setup_err; 7707 } 7708 bp->rsscos_nr_ctxs++; 7709 } 7710 7711 skip_rss_ctx: 7712 /* configure default vnic, ring grp */ 7713 rc = bnxt_hwrm_vnic_cfg(bp, vnic_id); 7714 if (rc) { 7715 netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n", 7716 vnic_id, rc); 7717 goto vnic_setup_err; 7718 } 7719 7720 /* Enable RSS hashing on vnic */ 7721 rc = bnxt_hwrm_vnic_set_rss(bp, vnic_id, true); 7722 if (rc) { 7723 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %x\n", 7724 vnic_id, rc); 7725 goto vnic_setup_err; 7726 } 7727 7728 if (bp->flags & BNXT_FLAG_AGG_RINGS) { 7729 rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id); 7730 if (rc) { 7731 netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n", 7732 vnic_id, rc); 7733 } 7734 } 7735 7736 vnic_setup_err: 7737 return rc; 7738 } 7739 7740 static int __bnxt_setup_vnic_p5(struct bnxt *bp, u16 vnic_id) 7741 { 7742 int rc, i, nr_ctxs; 7743 7744 nr_ctxs = bnxt_get_nr_rss_ctxs(bp, bp->rx_nr_rings); 7745 for (i = 0; i < nr_ctxs; i++) { 7746 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, i); 7747 if (rc) { 7748 netdev_err(bp->dev, "hwrm vnic %d ctx %d alloc failure rc: %x\n", 7749 vnic_id, i, rc); 7750 break; 7751 } 7752 bp->rsscos_nr_ctxs++; 7753 } 7754 if (i < nr_ctxs) 7755 return -ENOMEM; 7756 7757 rc = bnxt_hwrm_vnic_set_rss_p5(bp, vnic_id, true); 7758 if (rc) { 7759 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %d\n", 7760 vnic_id, rc); 7761 return rc; 7762 } 7763 rc = bnxt_hwrm_vnic_cfg(bp, vnic_id); 7764 if (rc) { 7765 netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n", 7766 vnic_id, rc); 7767 return rc; 7768 } 7769 if (bp->flags & BNXT_FLAG_AGG_RINGS) { 7770 rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id); 7771 if (rc) { 7772 netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n", 7773 vnic_id, rc); 7774 } 7775 } 7776 return rc; 7777 } 7778 7779 static int bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id) 7780 { 7781 if (bp->flags & BNXT_FLAG_CHIP_P5) 7782 return __bnxt_setup_vnic_p5(bp, vnic_id); 7783 else 7784 return __bnxt_setup_vnic(bp, vnic_id); 7785 } 7786 7787 static int bnxt_alloc_rfs_vnics(struct bnxt *bp) 7788 { 7789 #ifdef CONFIG_RFS_ACCEL 7790 int i, rc = 0; 7791 7792 if (bp->flags & BNXT_FLAG_CHIP_P5) 7793 return 0; 7794 7795 for (i = 0; i < bp->rx_nr_rings; i++) { 7796 struct bnxt_vnic_info *vnic; 7797 u16 vnic_id = i + 1; 7798 u16 ring_id = i; 7799 7800 if (vnic_id >= bp->nr_vnics) 7801 break; 7802 7803 vnic = &bp->vnic_info[vnic_id]; 7804 vnic->flags |= BNXT_VNIC_RFS_FLAG; 7805 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP) 7806 vnic->flags |= BNXT_VNIC_RFS_NEW_RSS_FLAG; 7807 rc = bnxt_hwrm_vnic_alloc(bp, vnic_id, ring_id, 1); 7808 if (rc) { 7809 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n", 7810 vnic_id, rc); 7811 break; 7812 } 7813 rc = bnxt_setup_vnic(bp, vnic_id); 7814 if (rc) 7815 break; 7816 } 7817 return rc; 7818 #else 7819 return 0; 7820 #endif 7821 } 7822 7823 /* Allow PF and VF with default VLAN to be in promiscuous mode */ 7824 static bool bnxt_promisc_ok(struct bnxt *bp) 7825 { 7826 #ifdef CONFIG_BNXT_SRIOV 7827 if (BNXT_VF(bp) && !bp->vf.vlan) 7828 return false; 7829 #endif 7830 return true; 7831 } 7832 7833 static int bnxt_setup_nitroa0_vnic(struct bnxt *bp) 7834 { 7835 unsigned int rc = 0; 7836 7837 rc = bnxt_hwrm_vnic_alloc(bp, 1, bp->rx_nr_rings - 1, 1); 7838 if (rc) { 7839 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n", 7840 rc); 7841 return rc; 7842 } 7843 7844 rc = bnxt_hwrm_vnic_cfg(bp, 1); 7845 if (rc) { 7846 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n", 7847 rc); 7848 return rc; 7849 } 7850 return rc; 7851 } 7852 7853 static int bnxt_cfg_rx_mode(struct bnxt *); 7854 static bool bnxt_mc_list_updated(struct bnxt *, u32 *); 7855 7856 static int bnxt_init_chip(struct bnxt *bp, bool irq_re_init) 7857 { 7858 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 7859 int rc = 0; 7860 unsigned int rx_nr_rings = bp->rx_nr_rings; 7861 7862 if (irq_re_init) { 7863 rc = bnxt_hwrm_stat_ctx_alloc(bp); 7864 if (rc) { 7865 netdev_err(bp->dev, "hwrm stat ctx alloc failure rc: %x\n", 7866 rc); 7867 goto err_out; 7868 } 7869 } 7870 7871 rc = bnxt_hwrm_ring_alloc(bp); 7872 if (rc) { 7873 netdev_err(bp->dev, "hwrm ring alloc failure rc: %x\n", rc); 7874 goto err_out; 7875 } 7876 7877 rc = bnxt_hwrm_ring_grp_alloc(bp); 7878 if (rc) { 7879 netdev_err(bp->dev, "hwrm_ring_grp alloc failure: %x\n", rc); 7880 goto err_out; 7881 } 7882 7883 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 7884 rx_nr_rings--; 7885 7886 /* default vnic 0 */ 7887 rc = bnxt_hwrm_vnic_alloc(bp, 0, 0, rx_nr_rings); 7888 if (rc) { 7889 netdev_err(bp->dev, "hwrm vnic alloc failure rc: %x\n", rc); 7890 goto err_out; 7891 } 7892 7893 rc = bnxt_setup_vnic(bp, 0); 7894 if (rc) 7895 goto err_out; 7896 7897 if (bp->flags & BNXT_FLAG_RFS) { 7898 rc = bnxt_alloc_rfs_vnics(bp); 7899 if (rc) 7900 goto err_out; 7901 } 7902 7903 if (bp->flags & BNXT_FLAG_TPA) { 7904 rc = bnxt_set_tpa(bp, true); 7905 if (rc) 7906 goto err_out; 7907 } 7908 7909 if (BNXT_VF(bp)) 7910 bnxt_update_vf_mac(bp); 7911 7912 /* Filter for default vnic 0 */ 7913 rc = bnxt_hwrm_set_vnic_filter(bp, 0, 0, bp->dev->dev_addr); 7914 if (rc) { 7915 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n", rc); 7916 goto err_out; 7917 } 7918 vnic->uc_filter_count = 1; 7919 7920 vnic->rx_mask = 0; 7921 if (bp->dev->flags & IFF_BROADCAST) 7922 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_BCAST; 7923 7924 if ((bp->dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp)) 7925 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS; 7926 7927 if (bp->dev->flags & IFF_ALLMULTI) { 7928 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST; 7929 vnic->mc_list_count = 0; 7930 } else { 7931 u32 mask = 0; 7932 7933 bnxt_mc_list_updated(bp, &mask); 7934 vnic->rx_mask |= mask; 7935 } 7936 7937 rc = bnxt_cfg_rx_mode(bp); 7938 if (rc) 7939 goto err_out; 7940 7941 rc = bnxt_hwrm_set_coal(bp); 7942 if (rc) 7943 netdev_warn(bp->dev, "HWRM set coalescing failure rc: %x\n", 7944 rc); 7945 7946 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) { 7947 rc = bnxt_setup_nitroa0_vnic(bp); 7948 if (rc) 7949 netdev_err(bp->dev, "Special vnic setup failure for NS2 A0 rc: %x\n", 7950 rc); 7951 } 7952 7953 if (BNXT_VF(bp)) { 7954 bnxt_hwrm_func_qcfg(bp); 7955 netdev_update_features(bp->dev); 7956 } 7957 7958 return 0; 7959 7960 err_out: 7961 bnxt_hwrm_resource_free(bp, 0, true); 7962 7963 return rc; 7964 } 7965 7966 static int bnxt_shutdown_nic(struct bnxt *bp, bool irq_re_init) 7967 { 7968 bnxt_hwrm_resource_free(bp, 1, irq_re_init); 7969 return 0; 7970 } 7971 7972 static int bnxt_init_nic(struct bnxt *bp, bool irq_re_init) 7973 { 7974 bnxt_init_cp_rings(bp); 7975 bnxt_init_rx_rings(bp); 7976 bnxt_init_tx_rings(bp); 7977 bnxt_init_ring_grps(bp, irq_re_init); 7978 bnxt_init_vnics(bp); 7979 7980 return bnxt_init_chip(bp, irq_re_init); 7981 } 7982 7983 static int bnxt_set_real_num_queues(struct bnxt *bp) 7984 { 7985 int rc; 7986 struct net_device *dev = bp->dev; 7987 7988 rc = netif_set_real_num_tx_queues(dev, bp->tx_nr_rings - 7989 bp->tx_nr_rings_xdp); 7990 if (rc) 7991 return rc; 7992 7993 rc = netif_set_real_num_rx_queues(dev, bp->rx_nr_rings); 7994 if (rc) 7995 return rc; 7996 7997 #ifdef CONFIG_RFS_ACCEL 7998 if (bp->flags & BNXT_FLAG_RFS) 7999 dev->rx_cpu_rmap = alloc_irq_cpu_rmap(bp->rx_nr_rings); 8000 #endif 8001 8002 return rc; 8003 } 8004 8005 static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max, 8006 bool shared) 8007 { 8008 int _rx = *rx, _tx = *tx; 8009 8010 if (shared) { 8011 *rx = min_t(int, _rx, max); 8012 *tx = min_t(int, _tx, max); 8013 } else { 8014 if (max < 2) 8015 return -ENOMEM; 8016 8017 while (_rx + _tx > max) { 8018 if (_rx > _tx && _rx > 1) 8019 _rx--; 8020 else if (_tx > 1) 8021 _tx--; 8022 } 8023 *rx = _rx; 8024 *tx = _tx; 8025 } 8026 return 0; 8027 } 8028 8029 static void bnxt_setup_msix(struct bnxt *bp) 8030 { 8031 const int len = sizeof(bp->irq_tbl[0].name); 8032 struct net_device *dev = bp->dev; 8033 int tcs, i; 8034 8035 tcs = netdev_get_num_tc(dev); 8036 if (tcs) { 8037 int i, off, count; 8038 8039 for (i = 0; i < tcs; i++) { 8040 count = bp->tx_nr_rings_per_tc; 8041 off = i * count; 8042 netdev_set_tc_queue(dev, i, count, off); 8043 } 8044 } 8045 8046 for (i = 0; i < bp->cp_nr_rings; i++) { 8047 int map_idx = bnxt_cp_num_to_irq_num(bp, i); 8048 char *attr; 8049 8050 if (bp->flags & BNXT_FLAG_SHARED_RINGS) 8051 attr = "TxRx"; 8052 else if (i < bp->rx_nr_rings) 8053 attr = "rx"; 8054 else 8055 attr = "tx"; 8056 8057 snprintf(bp->irq_tbl[map_idx].name, len, "%s-%s-%d", dev->name, 8058 attr, i); 8059 bp->irq_tbl[map_idx].handler = bnxt_msix; 8060 } 8061 } 8062 8063 static void bnxt_setup_inta(struct bnxt *bp) 8064 { 8065 const int len = sizeof(bp->irq_tbl[0].name); 8066 8067 if (netdev_get_num_tc(bp->dev)) 8068 netdev_reset_tc(bp->dev); 8069 8070 snprintf(bp->irq_tbl[0].name, len, "%s-%s-%d", bp->dev->name, "TxRx", 8071 0); 8072 bp->irq_tbl[0].handler = bnxt_inta; 8073 } 8074 8075 static int bnxt_setup_int_mode(struct bnxt *bp) 8076 { 8077 int rc; 8078 8079 if (bp->flags & BNXT_FLAG_USING_MSIX) 8080 bnxt_setup_msix(bp); 8081 else 8082 bnxt_setup_inta(bp); 8083 8084 rc = bnxt_set_real_num_queues(bp); 8085 return rc; 8086 } 8087 8088 #ifdef CONFIG_RFS_ACCEL 8089 static unsigned int bnxt_get_max_func_rss_ctxs(struct bnxt *bp) 8090 { 8091 return bp->hw_resc.max_rsscos_ctxs; 8092 } 8093 8094 static unsigned int bnxt_get_max_func_vnics(struct bnxt *bp) 8095 { 8096 return bp->hw_resc.max_vnics; 8097 } 8098 #endif 8099 8100 unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt *bp) 8101 { 8102 return bp->hw_resc.max_stat_ctxs; 8103 } 8104 8105 unsigned int bnxt_get_max_func_cp_rings(struct bnxt *bp) 8106 { 8107 return bp->hw_resc.max_cp_rings; 8108 } 8109 8110 static unsigned int bnxt_get_max_func_cp_rings_for_en(struct bnxt *bp) 8111 { 8112 unsigned int cp = bp->hw_resc.max_cp_rings; 8113 8114 if (!(bp->flags & BNXT_FLAG_CHIP_P5)) 8115 cp -= bnxt_get_ulp_msix_num(bp); 8116 8117 return cp; 8118 } 8119 8120 static unsigned int bnxt_get_max_func_irqs(struct bnxt *bp) 8121 { 8122 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 8123 8124 if (bp->flags & BNXT_FLAG_CHIP_P5) 8125 return min_t(unsigned int, hw_resc->max_irqs, hw_resc->max_nqs); 8126 8127 return min_t(unsigned int, hw_resc->max_irqs, hw_resc->max_cp_rings); 8128 } 8129 8130 static void bnxt_set_max_func_irqs(struct bnxt *bp, unsigned int max_irqs) 8131 { 8132 bp->hw_resc.max_irqs = max_irqs; 8133 } 8134 8135 unsigned int bnxt_get_avail_cp_rings_for_en(struct bnxt *bp) 8136 { 8137 unsigned int cp; 8138 8139 cp = bnxt_get_max_func_cp_rings_for_en(bp); 8140 if (bp->flags & BNXT_FLAG_CHIP_P5) 8141 return cp - bp->rx_nr_rings - bp->tx_nr_rings; 8142 else 8143 return cp - bp->cp_nr_rings; 8144 } 8145 8146 unsigned int bnxt_get_avail_stat_ctxs_for_en(struct bnxt *bp) 8147 { 8148 return bnxt_get_max_func_stat_ctxs(bp) - bnxt_get_func_stat_ctxs(bp); 8149 } 8150 8151 int bnxt_get_avail_msix(struct bnxt *bp, int num) 8152 { 8153 int max_cp = bnxt_get_max_func_cp_rings(bp); 8154 int max_irq = bnxt_get_max_func_irqs(bp); 8155 int total_req = bp->cp_nr_rings + num; 8156 int max_idx, avail_msix; 8157 8158 max_idx = bp->total_irqs; 8159 if (!(bp->flags & BNXT_FLAG_CHIP_P5)) 8160 max_idx = min_t(int, bp->total_irqs, max_cp); 8161 avail_msix = max_idx - bp->cp_nr_rings; 8162 if (!BNXT_NEW_RM(bp) || avail_msix >= num) 8163 return avail_msix; 8164 8165 if (max_irq < total_req) { 8166 num = max_irq - bp->cp_nr_rings; 8167 if (num <= 0) 8168 return 0; 8169 } 8170 return num; 8171 } 8172 8173 static int bnxt_get_num_msix(struct bnxt *bp) 8174 { 8175 if (!BNXT_NEW_RM(bp)) 8176 return bnxt_get_max_func_irqs(bp); 8177 8178 return bnxt_nq_rings_in_use(bp); 8179 } 8180 8181 static int bnxt_init_msix(struct bnxt *bp) 8182 { 8183 int i, total_vecs, max, rc = 0, min = 1, ulp_msix; 8184 struct msix_entry *msix_ent; 8185 8186 total_vecs = bnxt_get_num_msix(bp); 8187 max = bnxt_get_max_func_irqs(bp); 8188 if (total_vecs > max) 8189 total_vecs = max; 8190 8191 if (!total_vecs) 8192 return 0; 8193 8194 msix_ent = kcalloc(total_vecs, sizeof(struct msix_entry), GFP_KERNEL); 8195 if (!msix_ent) 8196 return -ENOMEM; 8197 8198 for (i = 0; i < total_vecs; i++) { 8199 msix_ent[i].entry = i; 8200 msix_ent[i].vector = 0; 8201 } 8202 8203 if (!(bp->flags & BNXT_FLAG_SHARED_RINGS)) 8204 min = 2; 8205 8206 total_vecs = pci_enable_msix_range(bp->pdev, msix_ent, min, total_vecs); 8207 ulp_msix = bnxt_get_ulp_msix_num(bp); 8208 if (total_vecs < 0 || total_vecs < ulp_msix) { 8209 rc = -ENODEV; 8210 goto msix_setup_exit; 8211 } 8212 8213 bp->irq_tbl = kcalloc(total_vecs, sizeof(struct bnxt_irq), GFP_KERNEL); 8214 if (bp->irq_tbl) { 8215 for (i = 0; i < total_vecs; i++) 8216 bp->irq_tbl[i].vector = msix_ent[i].vector; 8217 8218 bp->total_irqs = total_vecs; 8219 /* Trim rings based upon num of vectors allocated */ 8220 rc = bnxt_trim_rings(bp, &bp->rx_nr_rings, &bp->tx_nr_rings, 8221 total_vecs - ulp_msix, min == 1); 8222 if (rc) 8223 goto msix_setup_exit; 8224 8225 bp->cp_nr_rings = (min == 1) ? 8226 max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) : 8227 bp->tx_nr_rings + bp->rx_nr_rings; 8228 8229 } else { 8230 rc = -ENOMEM; 8231 goto msix_setup_exit; 8232 } 8233 bp->flags |= BNXT_FLAG_USING_MSIX; 8234 kfree(msix_ent); 8235 return 0; 8236 8237 msix_setup_exit: 8238 netdev_err(bp->dev, "bnxt_init_msix err: %x\n", rc); 8239 kfree(bp->irq_tbl); 8240 bp->irq_tbl = NULL; 8241 pci_disable_msix(bp->pdev); 8242 kfree(msix_ent); 8243 return rc; 8244 } 8245 8246 static int bnxt_init_inta(struct bnxt *bp) 8247 { 8248 bp->irq_tbl = kcalloc(1, sizeof(struct bnxt_irq), GFP_KERNEL); 8249 if (!bp->irq_tbl) 8250 return -ENOMEM; 8251 8252 bp->total_irqs = 1; 8253 bp->rx_nr_rings = 1; 8254 bp->tx_nr_rings = 1; 8255 bp->cp_nr_rings = 1; 8256 bp->flags |= BNXT_FLAG_SHARED_RINGS; 8257 bp->irq_tbl[0].vector = bp->pdev->irq; 8258 return 0; 8259 } 8260 8261 static int bnxt_init_int_mode(struct bnxt *bp) 8262 { 8263 int rc = 0; 8264 8265 if (bp->flags & BNXT_FLAG_MSIX_CAP) 8266 rc = bnxt_init_msix(bp); 8267 8268 if (!(bp->flags & BNXT_FLAG_USING_MSIX) && BNXT_PF(bp)) { 8269 /* fallback to INTA */ 8270 rc = bnxt_init_inta(bp); 8271 } 8272 return rc; 8273 } 8274 8275 static void bnxt_clear_int_mode(struct bnxt *bp) 8276 { 8277 if (bp->flags & BNXT_FLAG_USING_MSIX) 8278 pci_disable_msix(bp->pdev); 8279 8280 kfree(bp->irq_tbl); 8281 bp->irq_tbl = NULL; 8282 bp->flags &= ~BNXT_FLAG_USING_MSIX; 8283 } 8284 8285 int bnxt_reserve_rings(struct bnxt *bp, bool irq_re_init) 8286 { 8287 int tcs = netdev_get_num_tc(bp->dev); 8288 bool irq_cleared = false; 8289 int rc; 8290 8291 if (!bnxt_need_reserve_rings(bp)) 8292 return 0; 8293 8294 if (irq_re_init && BNXT_NEW_RM(bp) && 8295 bnxt_get_num_msix(bp) != bp->total_irqs) { 8296 bnxt_ulp_irq_stop(bp); 8297 bnxt_clear_int_mode(bp); 8298 irq_cleared = true; 8299 } 8300 rc = __bnxt_reserve_rings(bp); 8301 if (irq_cleared) { 8302 if (!rc) 8303 rc = bnxt_init_int_mode(bp); 8304 bnxt_ulp_irq_restart(bp, rc); 8305 } 8306 if (!netif_is_rxfh_configured(bp->dev)) 8307 bnxt_set_dflt_rss_indir_tbl(bp); 8308 8309 if (rc) { 8310 netdev_err(bp->dev, "ring reservation/IRQ init failure rc: %d\n", rc); 8311 return rc; 8312 } 8313 if (tcs && (bp->tx_nr_rings_per_tc * tcs != bp->tx_nr_rings)) { 8314 netdev_err(bp->dev, "tx ring reservation failure\n"); 8315 netdev_reset_tc(bp->dev); 8316 bp->tx_nr_rings_per_tc = bp->tx_nr_rings; 8317 return -ENOMEM; 8318 } 8319 return 0; 8320 } 8321 8322 static void bnxt_free_irq(struct bnxt *bp) 8323 { 8324 struct bnxt_irq *irq; 8325 int i; 8326 8327 #ifdef CONFIG_RFS_ACCEL 8328 free_irq_cpu_rmap(bp->dev->rx_cpu_rmap); 8329 bp->dev->rx_cpu_rmap = NULL; 8330 #endif 8331 if (!bp->irq_tbl || !bp->bnapi) 8332 return; 8333 8334 for (i = 0; i < bp->cp_nr_rings; i++) { 8335 int map_idx = bnxt_cp_num_to_irq_num(bp, i); 8336 8337 irq = &bp->irq_tbl[map_idx]; 8338 if (irq->requested) { 8339 if (irq->have_cpumask) { 8340 irq_set_affinity_hint(irq->vector, NULL); 8341 free_cpumask_var(irq->cpu_mask); 8342 irq->have_cpumask = 0; 8343 } 8344 free_irq(irq->vector, bp->bnapi[i]); 8345 } 8346 8347 irq->requested = 0; 8348 } 8349 } 8350 8351 static int bnxt_request_irq(struct bnxt *bp) 8352 { 8353 int i, j, rc = 0; 8354 unsigned long flags = 0; 8355 #ifdef CONFIG_RFS_ACCEL 8356 struct cpu_rmap *rmap; 8357 #endif 8358 8359 rc = bnxt_setup_int_mode(bp); 8360 if (rc) { 8361 netdev_err(bp->dev, "bnxt_setup_int_mode err: %x\n", 8362 rc); 8363 return rc; 8364 } 8365 #ifdef CONFIG_RFS_ACCEL 8366 rmap = bp->dev->rx_cpu_rmap; 8367 #endif 8368 if (!(bp->flags & BNXT_FLAG_USING_MSIX)) 8369 flags = IRQF_SHARED; 8370 8371 for (i = 0, j = 0; i < bp->cp_nr_rings; i++) { 8372 int map_idx = bnxt_cp_num_to_irq_num(bp, i); 8373 struct bnxt_irq *irq = &bp->irq_tbl[map_idx]; 8374 8375 #ifdef CONFIG_RFS_ACCEL 8376 if (rmap && bp->bnapi[i]->rx_ring) { 8377 rc = irq_cpu_rmap_add(rmap, irq->vector); 8378 if (rc) 8379 netdev_warn(bp->dev, "failed adding irq rmap for ring %d\n", 8380 j); 8381 j++; 8382 } 8383 #endif 8384 rc = request_irq(irq->vector, irq->handler, flags, irq->name, 8385 bp->bnapi[i]); 8386 if (rc) 8387 break; 8388 8389 irq->requested = 1; 8390 8391 if (zalloc_cpumask_var(&irq->cpu_mask, GFP_KERNEL)) { 8392 int numa_node = dev_to_node(&bp->pdev->dev); 8393 8394 irq->have_cpumask = 1; 8395 cpumask_set_cpu(cpumask_local_spread(i, numa_node), 8396 irq->cpu_mask); 8397 rc = irq_set_affinity_hint(irq->vector, irq->cpu_mask); 8398 if (rc) { 8399 netdev_warn(bp->dev, 8400 "Set affinity failed, IRQ = %d\n", 8401 irq->vector); 8402 break; 8403 } 8404 } 8405 } 8406 return rc; 8407 } 8408 8409 static void bnxt_del_napi(struct bnxt *bp) 8410 { 8411 int i; 8412 8413 if (!bp->bnapi) 8414 return; 8415 8416 for (i = 0; i < bp->cp_nr_rings; i++) { 8417 struct bnxt_napi *bnapi = bp->bnapi[i]; 8418 8419 napi_hash_del(&bnapi->napi); 8420 netif_napi_del(&bnapi->napi); 8421 } 8422 /* We called napi_hash_del() before netif_napi_del(), we need 8423 * to respect an RCU grace period before freeing napi structures. 8424 */ 8425 synchronize_net(); 8426 } 8427 8428 static void bnxt_init_napi(struct bnxt *bp) 8429 { 8430 int i; 8431 unsigned int cp_nr_rings = bp->cp_nr_rings; 8432 struct bnxt_napi *bnapi; 8433 8434 if (bp->flags & BNXT_FLAG_USING_MSIX) { 8435 int (*poll_fn)(struct napi_struct *, int) = bnxt_poll; 8436 8437 if (bp->flags & BNXT_FLAG_CHIP_P5) 8438 poll_fn = bnxt_poll_p5; 8439 else if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 8440 cp_nr_rings--; 8441 for (i = 0; i < cp_nr_rings; i++) { 8442 bnapi = bp->bnapi[i]; 8443 netif_napi_add(bp->dev, &bnapi->napi, poll_fn, 64); 8444 } 8445 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) { 8446 bnapi = bp->bnapi[cp_nr_rings]; 8447 netif_napi_add(bp->dev, &bnapi->napi, 8448 bnxt_poll_nitroa0, 64); 8449 } 8450 } else { 8451 bnapi = bp->bnapi[0]; 8452 netif_napi_add(bp->dev, &bnapi->napi, bnxt_poll, 64); 8453 } 8454 } 8455 8456 static void bnxt_disable_napi(struct bnxt *bp) 8457 { 8458 int i; 8459 8460 if (!bp->bnapi) 8461 return; 8462 8463 for (i = 0; i < bp->cp_nr_rings; i++) { 8464 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring; 8465 8466 if (bp->bnapi[i]->rx_ring) 8467 cancel_work_sync(&cpr->dim.work); 8468 8469 napi_disable(&bp->bnapi[i]->napi); 8470 } 8471 } 8472 8473 static void bnxt_enable_napi(struct bnxt *bp) 8474 { 8475 int i; 8476 8477 for (i = 0; i < bp->cp_nr_rings; i++) { 8478 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring; 8479 bp->bnapi[i]->in_reset = false; 8480 8481 if (bp->bnapi[i]->rx_ring) { 8482 INIT_WORK(&cpr->dim.work, bnxt_dim_work); 8483 cpr->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE; 8484 } 8485 napi_enable(&bp->bnapi[i]->napi); 8486 } 8487 } 8488 8489 void bnxt_tx_disable(struct bnxt *bp) 8490 { 8491 int i; 8492 struct bnxt_tx_ring_info *txr; 8493 8494 if (bp->tx_ring) { 8495 for (i = 0; i < bp->tx_nr_rings; i++) { 8496 txr = &bp->tx_ring[i]; 8497 txr->dev_state = BNXT_DEV_STATE_CLOSING; 8498 } 8499 } 8500 /* Stop all TX queues */ 8501 netif_tx_disable(bp->dev); 8502 netif_carrier_off(bp->dev); 8503 } 8504 8505 void bnxt_tx_enable(struct bnxt *bp) 8506 { 8507 int i; 8508 struct bnxt_tx_ring_info *txr; 8509 8510 for (i = 0; i < bp->tx_nr_rings; i++) { 8511 txr = &bp->tx_ring[i]; 8512 txr->dev_state = 0; 8513 } 8514 netif_tx_wake_all_queues(bp->dev); 8515 if (bp->link_info.link_up) 8516 netif_carrier_on(bp->dev); 8517 } 8518 8519 static void bnxt_report_link(struct bnxt *bp) 8520 { 8521 if (bp->link_info.link_up) { 8522 const char *duplex; 8523 const char *flow_ctrl; 8524 u32 speed; 8525 u16 fec; 8526 8527 netif_carrier_on(bp->dev); 8528 if (bp->link_info.duplex == BNXT_LINK_DUPLEX_FULL) 8529 duplex = "full"; 8530 else 8531 duplex = "half"; 8532 if (bp->link_info.pause == BNXT_LINK_PAUSE_BOTH) 8533 flow_ctrl = "ON - receive & transmit"; 8534 else if (bp->link_info.pause == BNXT_LINK_PAUSE_TX) 8535 flow_ctrl = "ON - transmit"; 8536 else if (bp->link_info.pause == BNXT_LINK_PAUSE_RX) 8537 flow_ctrl = "ON - receive"; 8538 else 8539 flow_ctrl = "none"; 8540 speed = bnxt_fw_to_ethtool_speed(bp->link_info.link_speed); 8541 netdev_info(bp->dev, "NIC Link is Up, %u Mbps %s duplex, Flow control: %s\n", 8542 speed, duplex, flow_ctrl); 8543 if (bp->flags & BNXT_FLAG_EEE_CAP) 8544 netdev_info(bp->dev, "EEE is %s\n", 8545 bp->eee.eee_active ? "active" : 8546 "not active"); 8547 fec = bp->link_info.fec_cfg; 8548 if (!(fec & PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED)) 8549 netdev_info(bp->dev, "FEC autoneg %s encodings: %s\n", 8550 (fec & BNXT_FEC_AUTONEG) ? "on" : "off", 8551 (fec & BNXT_FEC_ENC_BASE_R) ? "BaseR" : 8552 (fec & BNXT_FEC_ENC_RS) ? "RS" : "None"); 8553 } else { 8554 netif_carrier_off(bp->dev); 8555 netdev_err(bp->dev, "NIC Link is Down\n"); 8556 } 8557 } 8558 8559 static int bnxt_hwrm_phy_qcaps(struct bnxt *bp) 8560 { 8561 int rc = 0; 8562 struct hwrm_port_phy_qcaps_input req = {0}; 8563 struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr; 8564 struct bnxt_link_info *link_info = &bp->link_info; 8565 8566 bp->flags &= ~BNXT_FLAG_EEE_CAP; 8567 if (bp->test_info) 8568 bp->test_info->flags &= ~(BNXT_TEST_FL_EXT_LPBK | 8569 BNXT_TEST_FL_AN_PHY_LPBK); 8570 if (bp->hwrm_spec_code < 0x10201) 8571 return 0; 8572 8573 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCAPS, -1, -1); 8574 8575 mutex_lock(&bp->hwrm_cmd_lock); 8576 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 8577 if (rc) 8578 goto hwrm_phy_qcaps_exit; 8579 8580 if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED) { 8581 struct ethtool_eee *eee = &bp->eee; 8582 u16 fw_speeds = le16_to_cpu(resp->supported_speeds_eee_mode); 8583 8584 bp->flags |= BNXT_FLAG_EEE_CAP; 8585 eee->supported = _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0); 8586 bp->lpi_tmr_lo = le32_to_cpu(resp->tx_lpi_timer_low) & 8587 PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK; 8588 bp->lpi_tmr_hi = le32_to_cpu(resp->valid_tx_lpi_timer_high) & 8589 PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK; 8590 } 8591 if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_EXTERNAL_LPBK_SUPPORTED) { 8592 if (bp->test_info) 8593 bp->test_info->flags |= BNXT_TEST_FL_EXT_LPBK; 8594 } 8595 if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_AUTONEG_LPBK_SUPPORTED) { 8596 if (bp->test_info) 8597 bp->test_info->flags |= BNXT_TEST_FL_AN_PHY_LPBK; 8598 } 8599 if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_SHARED_PHY_CFG_SUPPORTED) { 8600 if (BNXT_PF(bp)) 8601 bp->fw_cap |= BNXT_FW_CAP_SHARED_PORT_CFG; 8602 } 8603 if (resp->supported_speeds_auto_mode) 8604 link_info->support_auto_speeds = 8605 le16_to_cpu(resp->supported_speeds_auto_mode); 8606 8607 bp->port_count = resp->port_cnt; 8608 8609 hwrm_phy_qcaps_exit: 8610 mutex_unlock(&bp->hwrm_cmd_lock); 8611 return rc; 8612 } 8613 8614 static int bnxt_update_link(struct bnxt *bp, bool chng_link_state) 8615 { 8616 int rc = 0; 8617 struct bnxt_link_info *link_info = &bp->link_info; 8618 struct hwrm_port_phy_qcfg_input req = {0}; 8619 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr; 8620 u8 link_up = link_info->link_up; 8621 u16 diff; 8622 8623 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCFG, -1, -1); 8624 8625 mutex_lock(&bp->hwrm_cmd_lock); 8626 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 8627 if (rc) { 8628 mutex_unlock(&bp->hwrm_cmd_lock); 8629 return rc; 8630 } 8631 8632 memcpy(&link_info->phy_qcfg_resp, resp, sizeof(*resp)); 8633 link_info->phy_link_status = resp->link; 8634 link_info->duplex = resp->duplex_cfg; 8635 if (bp->hwrm_spec_code >= 0x10800) 8636 link_info->duplex = resp->duplex_state; 8637 link_info->pause = resp->pause; 8638 link_info->auto_mode = resp->auto_mode; 8639 link_info->auto_pause_setting = resp->auto_pause; 8640 link_info->lp_pause = resp->link_partner_adv_pause; 8641 link_info->force_pause_setting = resp->force_pause; 8642 link_info->duplex_setting = resp->duplex_cfg; 8643 if (link_info->phy_link_status == BNXT_LINK_LINK) 8644 link_info->link_speed = le16_to_cpu(resp->link_speed); 8645 else 8646 link_info->link_speed = 0; 8647 link_info->force_link_speed = le16_to_cpu(resp->force_link_speed); 8648 link_info->support_speeds = le16_to_cpu(resp->support_speeds); 8649 link_info->auto_link_speeds = le16_to_cpu(resp->auto_link_speed_mask); 8650 link_info->lp_auto_link_speeds = 8651 le16_to_cpu(resp->link_partner_adv_speeds); 8652 link_info->preemphasis = le32_to_cpu(resp->preemphasis); 8653 link_info->phy_ver[0] = resp->phy_maj; 8654 link_info->phy_ver[1] = resp->phy_min; 8655 link_info->phy_ver[2] = resp->phy_bld; 8656 link_info->media_type = resp->media_type; 8657 link_info->phy_type = resp->phy_type; 8658 link_info->transceiver = resp->xcvr_pkg_type; 8659 link_info->phy_addr = resp->eee_config_phy_addr & 8660 PORT_PHY_QCFG_RESP_PHY_ADDR_MASK; 8661 link_info->module_status = resp->module_status; 8662 8663 if (bp->flags & BNXT_FLAG_EEE_CAP) { 8664 struct ethtool_eee *eee = &bp->eee; 8665 u16 fw_speeds; 8666 8667 eee->eee_active = 0; 8668 if (resp->eee_config_phy_addr & 8669 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE) { 8670 eee->eee_active = 1; 8671 fw_speeds = le16_to_cpu( 8672 resp->link_partner_adv_eee_link_speed_mask); 8673 eee->lp_advertised = 8674 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0); 8675 } 8676 8677 /* Pull initial EEE config */ 8678 if (!chng_link_state) { 8679 if (resp->eee_config_phy_addr & 8680 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED) 8681 eee->eee_enabled = 1; 8682 8683 fw_speeds = le16_to_cpu(resp->adv_eee_link_speed_mask); 8684 eee->advertised = 8685 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0); 8686 8687 if (resp->eee_config_phy_addr & 8688 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI) { 8689 __le32 tmr; 8690 8691 eee->tx_lpi_enabled = 1; 8692 tmr = resp->xcvr_identifier_type_tx_lpi_timer; 8693 eee->tx_lpi_timer = le32_to_cpu(tmr) & 8694 PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK; 8695 } 8696 } 8697 } 8698 8699 link_info->fec_cfg = PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED; 8700 if (bp->hwrm_spec_code >= 0x10504) 8701 link_info->fec_cfg = le16_to_cpu(resp->fec_cfg); 8702 8703 /* TODO: need to add more logic to report VF link */ 8704 if (chng_link_state) { 8705 if (link_info->phy_link_status == BNXT_LINK_LINK) 8706 link_info->link_up = 1; 8707 else 8708 link_info->link_up = 0; 8709 if (link_up != link_info->link_up) 8710 bnxt_report_link(bp); 8711 } else { 8712 /* alwasy link down if not require to update link state */ 8713 link_info->link_up = 0; 8714 } 8715 mutex_unlock(&bp->hwrm_cmd_lock); 8716 8717 if (!BNXT_PHY_CFG_ABLE(bp)) 8718 return 0; 8719 8720 diff = link_info->support_auto_speeds ^ link_info->advertising; 8721 if ((link_info->support_auto_speeds | diff) != 8722 link_info->support_auto_speeds) { 8723 /* An advertised speed is no longer supported, so we need to 8724 * update the advertisement settings. Caller holds RTNL 8725 * so we can modify link settings. 8726 */ 8727 link_info->advertising = link_info->support_auto_speeds; 8728 if (link_info->autoneg & BNXT_AUTONEG_SPEED) 8729 bnxt_hwrm_set_link_setting(bp, true, false); 8730 } 8731 return 0; 8732 } 8733 8734 static void bnxt_get_port_module_status(struct bnxt *bp) 8735 { 8736 struct bnxt_link_info *link_info = &bp->link_info; 8737 struct hwrm_port_phy_qcfg_output *resp = &link_info->phy_qcfg_resp; 8738 u8 module_status; 8739 8740 if (bnxt_update_link(bp, true)) 8741 return; 8742 8743 module_status = link_info->module_status; 8744 switch (module_status) { 8745 case PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX: 8746 case PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN: 8747 case PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG: 8748 netdev_warn(bp->dev, "Unqualified SFP+ module detected on port %d\n", 8749 bp->pf.port_id); 8750 if (bp->hwrm_spec_code >= 0x10201) { 8751 netdev_warn(bp->dev, "Module part number %s\n", 8752 resp->phy_vendor_partnumber); 8753 } 8754 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX) 8755 netdev_warn(bp->dev, "TX is disabled\n"); 8756 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN) 8757 netdev_warn(bp->dev, "SFP+ module is shutdown\n"); 8758 } 8759 } 8760 8761 static void 8762 bnxt_hwrm_set_pause_common(struct bnxt *bp, struct hwrm_port_phy_cfg_input *req) 8763 { 8764 if (bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) { 8765 if (bp->hwrm_spec_code >= 0x10201) 8766 req->auto_pause = 8767 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE; 8768 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX) 8769 req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX; 8770 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX) 8771 req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_TX; 8772 req->enables |= 8773 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE); 8774 } else { 8775 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX) 8776 req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_RX; 8777 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX) 8778 req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_TX; 8779 req->enables |= 8780 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE); 8781 if (bp->hwrm_spec_code >= 0x10201) { 8782 req->auto_pause = req->force_pause; 8783 req->enables |= cpu_to_le32( 8784 PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE); 8785 } 8786 } 8787 } 8788 8789 static void bnxt_hwrm_set_link_common(struct bnxt *bp, 8790 struct hwrm_port_phy_cfg_input *req) 8791 { 8792 u8 autoneg = bp->link_info.autoneg; 8793 u16 fw_link_speed = bp->link_info.req_link_speed; 8794 u16 advertising = bp->link_info.advertising; 8795 8796 if (autoneg & BNXT_AUTONEG_SPEED) { 8797 req->auto_mode |= 8798 PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK; 8799 8800 req->enables |= cpu_to_le32( 8801 PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK); 8802 req->auto_link_speed_mask = cpu_to_le16(advertising); 8803 8804 req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE); 8805 req->flags |= 8806 cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG); 8807 } else { 8808 req->force_link_speed = cpu_to_le16(fw_link_speed); 8809 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE); 8810 } 8811 8812 /* tell chimp that the setting takes effect immediately */ 8813 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESET_PHY); 8814 } 8815 8816 int bnxt_hwrm_set_pause(struct bnxt *bp) 8817 { 8818 struct hwrm_port_phy_cfg_input req = {0}; 8819 int rc; 8820 8821 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1); 8822 bnxt_hwrm_set_pause_common(bp, &req); 8823 8824 if ((bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) || 8825 bp->link_info.force_link_chng) 8826 bnxt_hwrm_set_link_common(bp, &req); 8827 8828 mutex_lock(&bp->hwrm_cmd_lock); 8829 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 8830 if (!rc && !(bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL)) { 8831 /* since changing of pause setting doesn't trigger any link 8832 * change event, the driver needs to update the current pause 8833 * result upon successfully return of the phy_cfg command 8834 */ 8835 bp->link_info.pause = 8836 bp->link_info.force_pause_setting = bp->link_info.req_flow_ctrl; 8837 bp->link_info.auto_pause_setting = 0; 8838 if (!bp->link_info.force_link_chng) 8839 bnxt_report_link(bp); 8840 } 8841 bp->link_info.force_link_chng = false; 8842 mutex_unlock(&bp->hwrm_cmd_lock); 8843 return rc; 8844 } 8845 8846 static void bnxt_hwrm_set_eee(struct bnxt *bp, 8847 struct hwrm_port_phy_cfg_input *req) 8848 { 8849 struct ethtool_eee *eee = &bp->eee; 8850 8851 if (eee->eee_enabled) { 8852 u16 eee_speeds; 8853 u32 flags = PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE; 8854 8855 if (eee->tx_lpi_enabled) 8856 flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE; 8857 else 8858 flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE; 8859 8860 req->flags |= cpu_to_le32(flags); 8861 eee_speeds = bnxt_get_fw_auto_link_speeds(eee->advertised); 8862 req->eee_link_speed_mask = cpu_to_le16(eee_speeds); 8863 req->tx_lpi_timer = cpu_to_le32(eee->tx_lpi_timer); 8864 } else { 8865 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE); 8866 } 8867 } 8868 8869 int bnxt_hwrm_set_link_setting(struct bnxt *bp, bool set_pause, bool set_eee) 8870 { 8871 struct hwrm_port_phy_cfg_input req = {0}; 8872 8873 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1); 8874 if (set_pause) 8875 bnxt_hwrm_set_pause_common(bp, &req); 8876 8877 bnxt_hwrm_set_link_common(bp, &req); 8878 8879 if (set_eee) 8880 bnxt_hwrm_set_eee(bp, &req); 8881 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 8882 } 8883 8884 static int bnxt_hwrm_shutdown_link(struct bnxt *bp) 8885 { 8886 struct hwrm_port_phy_cfg_input req = {0}; 8887 8888 if (!BNXT_SINGLE_PF(bp)) 8889 return 0; 8890 8891 if (pci_num_vf(bp->pdev)) 8892 return 0; 8893 8894 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1); 8895 req.flags = cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN); 8896 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 8897 } 8898 8899 static int bnxt_fw_init_one(struct bnxt *bp); 8900 8901 static int bnxt_hwrm_if_change(struct bnxt *bp, bool up) 8902 { 8903 struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr; 8904 struct hwrm_func_drv_if_change_input req = {0}; 8905 bool resc_reinit = false, fw_reset = false; 8906 u32 flags = 0; 8907 int rc; 8908 8909 if (!(bp->fw_cap & BNXT_FW_CAP_IF_CHANGE)) 8910 return 0; 8911 8912 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_IF_CHANGE, -1, -1); 8913 if (up) 8914 req.flags = cpu_to_le32(FUNC_DRV_IF_CHANGE_REQ_FLAGS_UP); 8915 mutex_lock(&bp->hwrm_cmd_lock); 8916 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 8917 if (!rc) 8918 flags = le32_to_cpu(resp->flags); 8919 mutex_unlock(&bp->hwrm_cmd_lock); 8920 if (rc) 8921 return rc; 8922 8923 if (!up) 8924 return 0; 8925 8926 if (flags & FUNC_DRV_IF_CHANGE_RESP_FLAGS_RESC_CHANGE) 8927 resc_reinit = true; 8928 if (flags & FUNC_DRV_IF_CHANGE_RESP_FLAGS_HOT_FW_RESET_DONE) 8929 fw_reset = true; 8930 8931 if (test_bit(BNXT_STATE_IN_FW_RESET, &bp->state) && !fw_reset) { 8932 netdev_err(bp->dev, "RESET_DONE not set during FW reset.\n"); 8933 return -ENODEV; 8934 } 8935 if (resc_reinit || fw_reset) { 8936 if (fw_reset) { 8937 if (!test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) 8938 bnxt_ulp_stop(bp); 8939 bnxt_free_ctx_mem(bp); 8940 kfree(bp->ctx); 8941 bp->ctx = NULL; 8942 bnxt_dcb_free(bp); 8943 rc = bnxt_fw_init_one(bp); 8944 if (rc) { 8945 set_bit(BNXT_STATE_ABORT_ERR, &bp->state); 8946 return rc; 8947 } 8948 bnxt_clear_int_mode(bp); 8949 rc = bnxt_init_int_mode(bp); 8950 if (rc) { 8951 netdev_err(bp->dev, "init int mode failed\n"); 8952 return rc; 8953 } 8954 set_bit(BNXT_STATE_FW_RESET_DET, &bp->state); 8955 } 8956 if (BNXT_NEW_RM(bp)) { 8957 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 8958 8959 rc = bnxt_hwrm_func_resc_qcaps(bp, true); 8960 hw_resc->resv_cp_rings = 0; 8961 hw_resc->resv_stat_ctxs = 0; 8962 hw_resc->resv_irqs = 0; 8963 hw_resc->resv_tx_rings = 0; 8964 hw_resc->resv_rx_rings = 0; 8965 hw_resc->resv_hw_ring_grps = 0; 8966 hw_resc->resv_vnics = 0; 8967 if (!fw_reset) { 8968 bp->tx_nr_rings = 0; 8969 bp->rx_nr_rings = 0; 8970 } 8971 } 8972 } 8973 return 0; 8974 } 8975 8976 static int bnxt_hwrm_port_led_qcaps(struct bnxt *bp) 8977 { 8978 struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr; 8979 struct hwrm_port_led_qcaps_input req = {0}; 8980 struct bnxt_pf_info *pf = &bp->pf; 8981 int rc; 8982 8983 bp->num_leds = 0; 8984 if (BNXT_VF(bp) || bp->hwrm_spec_code < 0x10601) 8985 return 0; 8986 8987 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_LED_QCAPS, -1, -1); 8988 req.port_id = cpu_to_le16(pf->port_id); 8989 mutex_lock(&bp->hwrm_cmd_lock); 8990 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 8991 if (rc) { 8992 mutex_unlock(&bp->hwrm_cmd_lock); 8993 return rc; 8994 } 8995 if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) { 8996 int i; 8997 8998 bp->num_leds = resp->num_leds; 8999 memcpy(bp->leds, &resp->led0_id, sizeof(bp->leds[0]) * 9000 bp->num_leds); 9001 for (i = 0; i < bp->num_leds; i++) { 9002 struct bnxt_led_info *led = &bp->leds[i]; 9003 __le16 caps = led->led_state_caps; 9004 9005 if (!led->led_group_id || 9006 !BNXT_LED_ALT_BLINK_CAP(caps)) { 9007 bp->num_leds = 0; 9008 break; 9009 } 9010 } 9011 } 9012 mutex_unlock(&bp->hwrm_cmd_lock); 9013 return 0; 9014 } 9015 9016 int bnxt_hwrm_alloc_wol_fltr(struct bnxt *bp) 9017 { 9018 struct hwrm_wol_filter_alloc_input req = {0}; 9019 struct hwrm_wol_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr; 9020 int rc; 9021 9022 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_ALLOC, -1, -1); 9023 req.port_id = cpu_to_le16(bp->pf.port_id); 9024 req.wol_type = WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT; 9025 req.enables = cpu_to_le32(WOL_FILTER_ALLOC_REQ_ENABLES_MAC_ADDRESS); 9026 memcpy(req.mac_address, bp->dev->dev_addr, ETH_ALEN); 9027 mutex_lock(&bp->hwrm_cmd_lock); 9028 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 9029 if (!rc) 9030 bp->wol_filter_id = resp->wol_filter_id; 9031 mutex_unlock(&bp->hwrm_cmd_lock); 9032 return rc; 9033 } 9034 9035 int bnxt_hwrm_free_wol_fltr(struct bnxt *bp) 9036 { 9037 struct hwrm_wol_filter_free_input req = {0}; 9038 9039 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_FREE, -1, -1); 9040 req.port_id = cpu_to_le16(bp->pf.port_id); 9041 req.enables = cpu_to_le32(WOL_FILTER_FREE_REQ_ENABLES_WOL_FILTER_ID); 9042 req.wol_filter_id = bp->wol_filter_id; 9043 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 9044 } 9045 9046 static u16 bnxt_hwrm_get_wol_fltrs(struct bnxt *bp, u16 handle) 9047 { 9048 struct hwrm_wol_filter_qcfg_input req = {0}; 9049 struct hwrm_wol_filter_qcfg_output *resp = bp->hwrm_cmd_resp_addr; 9050 u16 next_handle = 0; 9051 int rc; 9052 9053 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_QCFG, -1, -1); 9054 req.port_id = cpu_to_le16(bp->pf.port_id); 9055 req.handle = cpu_to_le16(handle); 9056 mutex_lock(&bp->hwrm_cmd_lock); 9057 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 9058 if (!rc) { 9059 next_handle = le16_to_cpu(resp->next_handle); 9060 if (next_handle != 0) { 9061 if (resp->wol_type == 9062 WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT) { 9063 bp->wol = 1; 9064 bp->wol_filter_id = resp->wol_filter_id; 9065 } 9066 } 9067 } 9068 mutex_unlock(&bp->hwrm_cmd_lock); 9069 return next_handle; 9070 } 9071 9072 static void bnxt_get_wol_settings(struct bnxt *bp) 9073 { 9074 u16 handle = 0; 9075 9076 bp->wol = 0; 9077 if (!BNXT_PF(bp) || !(bp->flags & BNXT_FLAG_WOL_CAP)) 9078 return; 9079 9080 do { 9081 handle = bnxt_hwrm_get_wol_fltrs(bp, handle); 9082 } while (handle && handle != 0xffff); 9083 } 9084 9085 #ifdef CONFIG_BNXT_HWMON 9086 static ssize_t bnxt_show_temp(struct device *dev, 9087 struct device_attribute *devattr, char *buf) 9088 { 9089 struct hwrm_temp_monitor_query_input req = {0}; 9090 struct hwrm_temp_monitor_query_output *resp; 9091 struct bnxt *bp = dev_get_drvdata(dev); 9092 u32 temp = 0; 9093 9094 resp = bp->hwrm_cmd_resp_addr; 9095 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TEMP_MONITOR_QUERY, -1, -1); 9096 mutex_lock(&bp->hwrm_cmd_lock); 9097 if (!_hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT)) 9098 temp = resp->temp * 1000; /* display millidegree */ 9099 mutex_unlock(&bp->hwrm_cmd_lock); 9100 9101 return sprintf(buf, "%u\n", temp); 9102 } 9103 static SENSOR_DEVICE_ATTR(temp1_input, 0444, bnxt_show_temp, NULL, 0); 9104 9105 static struct attribute *bnxt_attrs[] = { 9106 &sensor_dev_attr_temp1_input.dev_attr.attr, 9107 NULL 9108 }; 9109 ATTRIBUTE_GROUPS(bnxt); 9110 9111 static void bnxt_hwmon_close(struct bnxt *bp) 9112 { 9113 if (bp->hwmon_dev) { 9114 hwmon_device_unregister(bp->hwmon_dev); 9115 bp->hwmon_dev = NULL; 9116 } 9117 } 9118 9119 static void bnxt_hwmon_open(struct bnxt *bp) 9120 { 9121 struct pci_dev *pdev = bp->pdev; 9122 9123 if (bp->hwmon_dev) 9124 return; 9125 9126 bp->hwmon_dev = hwmon_device_register_with_groups(&pdev->dev, 9127 DRV_MODULE_NAME, bp, 9128 bnxt_groups); 9129 if (IS_ERR(bp->hwmon_dev)) { 9130 bp->hwmon_dev = NULL; 9131 dev_warn(&pdev->dev, "Cannot register hwmon device\n"); 9132 } 9133 } 9134 #else 9135 static void bnxt_hwmon_close(struct bnxt *bp) 9136 { 9137 } 9138 9139 static void bnxt_hwmon_open(struct bnxt *bp) 9140 { 9141 } 9142 #endif 9143 9144 static bool bnxt_eee_config_ok(struct bnxt *bp) 9145 { 9146 struct ethtool_eee *eee = &bp->eee; 9147 struct bnxt_link_info *link_info = &bp->link_info; 9148 9149 if (!(bp->flags & BNXT_FLAG_EEE_CAP)) 9150 return true; 9151 9152 if (eee->eee_enabled) { 9153 u32 advertising = 9154 _bnxt_fw_to_ethtool_adv_spds(link_info->advertising, 0); 9155 9156 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) { 9157 eee->eee_enabled = 0; 9158 return false; 9159 } 9160 if (eee->advertised & ~advertising) { 9161 eee->advertised = advertising & eee->supported; 9162 return false; 9163 } 9164 } 9165 return true; 9166 } 9167 9168 static int bnxt_update_phy_setting(struct bnxt *bp) 9169 { 9170 int rc; 9171 bool update_link = false; 9172 bool update_pause = false; 9173 bool update_eee = false; 9174 struct bnxt_link_info *link_info = &bp->link_info; 9175 9176 rc = bnxt_update_link(bp, true); 9177 if (rc) { 9178 netdev_err(bp->dev, "failed to update link (rc: %x)\n", 9179 rc); 9180 return rc; 9181 } 9182 if (!BNXT_SINGLE_PF(bp)) 9183 return 0; 9184 9185 if ((link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) && 9186 (link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH) != 9187 link_info->req_flow_ctrl) 9188 update_pause = true; 9189 if (!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) && 9190 link_info->force_pause_setting != link_info->req_flow_ctrl) 9191 update_pause = true; 9192 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) { 9193 if (BNXT_AUTO_MODE(link_info->auto_mode)) 9194 update_link = true; 9195 if (link_info->req_link_speed != link_info->force_link_speed) 9196 update_link = true; 9197 if (link_info->req_duplex != link_info->duplex_setting) 9198 update_link = true; 9199 } else { 9200 if (link_info->auto_mode == BNXT_LINK_AUTO_NONE) 9201 update_link = true; 9202 if (link_info->advertising != link_info->auto_link_speeds) 9203 update_link = true; 9204 } 9205 9206 /* The last close may have shutdown the link, so need to call 9207 * PHY_CFG to bring it back up. 9208 */ 9209 if (!bp->link_info.link_up) 9210 update_link = true; 9211 9212 if (!bnxt_eee_config_ok(bp)) 9213 update_eee = true; 9214 9215 if (update_link) 9216 rc = bnxt_hwrm_set_link_setting(bp, update_pause, update_eee); 9217 else if (update_pause) 9218 rc = bnxt_hwrm_set_pause(bp); 9219 if (rc) { 9220 netdev_err(bp->dev, "failed to update phy setting (rc: %x)\n", 9221 rc); 9222 return rc; 9223 } 9224 9225 return rc; 9226 } 9227 9228 /* Common routine to pre-map certain register block to different GRC window. 9229 * A PF has 16 4K windows and a VF has 4 4K windows. However, only 15 windows 9230 * in PF and 3 windows in VF that can be customized to map in different 9231 * register blocks. 9232 */ 9233 static void bnxt_preset_reg_win(struct bnxt *bp) 9234 { 9235 if (BNXT_PF(bp)) { 9236 /* CAG registers map to GRC window #4 */ 9237 writel(BNXT_CAG_REG_BASE, 9238 bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 12); 9239 } 9240 } 9241 9242 static int bnxt_init_dflt_ring_mode(struct bnxt *bp); 9243 9244 static int __bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init) 9245 { 9246 int rc = 0; 9247 9248 bnxt_preset_reg_win(bp); 9249 netif_carrier_off(bp->dev); 9250 if (irq_re_init) { 9251 /* Reserve rings now if none were reserved at driver probe. */ 9252 rc = bnxt_init_dflt_ring_mode(bp); 9253 if (rc) { 9254 netdev_err(bp->dev, "Failed to reserve default rings at open\n"); 9255 return rc; 9256 } 9257 } 9258 rc = bnxt_reserve_rings(bp, irq_re_init); 9259 if (rc) 9260 return rc; 9261 if ((bp->flags & BNXT_FLAG_RFS) && 9262 !(bp->flags & BNXT_FLAG_USING_MSIX)) { 9263 /* disable RFS if falling back to INTA */ 9264 bp->dev->hw_features &= ~NETIF_F_NTUPLE; 9265 bp->flags &= ~BNXT_FLAG_RFS; 9266 } 9267 9268 rc = bnxt_alloc_mem(bp, irq_re_init); 9269 if (rc) { 9270 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc); 9271 goto open_err_free_mem; 9272 } 9273 9274 if (irq_re_init) { 9275 bnxt_init_napi(bp); 9276 rc = bnxt_request_irq(bp); 9277 if (rc) { 9278 netdev_err(bp->dev, "bnxt_request_irq err: %x\n", rc); 9279 goto open_err_irq; 9280 } 9281 } 9282 9283 bnxt_enable_napi(bp); 9284 bnxt_debug_dev_init(bp); 9285 9286 rc = bnxt_init_nic(bp, irq_re_init); 9287 if (rc) { 9288 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc); 9289 goto open_err; 9290 } 9291 9292 if (link_re_init) { 9293 mutex_lock(&bp->link_lock); 9294 rc = bnxt_update_phy_setting(bp); 9295 mutex_unlock(&bp->link_lock); 9296 if (rc) { 9297 netdev_warn(bp->dev, "failed to update phy settings\n"); 9298 if (BNXT_SINGLE_PF(bp)) { 9299 bp->link_info.phy_retry = true; 9300 bp->link_info.phy_retry_expires = 9301 jiffies + 5 * HZ; 9302 } 9303 } 9304 } 9305 9306 if (irq_re_init) 9307 udp_tunnel_nic_reset_ntf(bp->dev); 9308 9309 set_bit(BNXT_STATE_OPEN, &bp->state); 9310 bnxt_enable_int(bp); 9311 /* Enable TX queues */ 9312 bnxt_tx_enable(bp); 9313 mod_timer(&bp->timer, jiffies + bp->current_interval); 9314 /* Poll link status and check for SFP+ module status */ 9315 bnxt_get_port_module_status(bp); 9316 9317 /* VF-reps may need to be re-opened after the PF is re-opened */ 9318 if (BNXT_PF(bp)) 9319 bnxt_vf_reps_open(bp); 9320 return 0; 9321 9322 open_err: 9323 bnxt_debug_dev_exit(bp); 9324 bnxt_disable_napi(bp); 9325 9326 open_err_irq: 9327 bnxt_del_napi(bp); 9328 9329 open_err_free_mem: 9330 bnxt_free_skbs(bp); 9331 bnxt_free_irq(bp); 9332 bnxt_free_mem(bp, true); 9333 return rc; 9334 } 9335 9336 /* rtnl_lock held */ 9337 int bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init) 9338 { 9339 int rc = 0; 9340 9341 rc = __bnxt_open_nic(bp, irq_re_init, link_re_init); 9342 if (rc) { 9343 netdev_err(bp->dev, "nic open fail (rc: %x)\n", rc); 9344 dev_close(bp->dev); 9345 } 9346 return rc; 9347 } 9348 9349 /* rtnl_lock held, open the NIC half way by allocating all resources, but 9350 * NAPI, IRQ, and TX are not enabled. This is mainly used for offline 9351 * self tests. 9352 */ 9353 int bnxt_half_open_nic(struct bnxt *bp) 9354 { 9355 int rc = 0; 9356 9357 rc = bnxt_alloc_mem(bp, false); 9358 if (rc) { 9359 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc); 9360 goto half_open_err; 9361 } 9362 rc = bnxt_init_nic(bp, false); 9363 if (rc) { 9364 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc); 9365 goto half_open_err; 9366 } 9367 return 0; 9368 9369 half_open_err: 9370 bnxt_free_skbs(bp); 9371 bnxt_free_mem(bp, false); 9372 dev_close(bp->dev); 9373 return rc; 9374 } 9375 9376 /* rtnl_lock held, this call can only be made after a previous successful 9377 * call to bnxt_half_open_nic(). 9378 */ 9379 void bnxt_half_close_nic(struct bnxt *bp) 9380 { 9381 bnxt_hwrm_resource_free(bp, false, false); 9382 bnxt_free_skbs(bp); 9383 bnxt_free_mem(bp, false); 9384 } 9385 9386 static void bnxt_reenable_sriov(struct bnxt *bp) 9387 { 9388 if (BNXT_PF(bp)) { 9389 struct bnxt_pf_info *pf = &bp->pf; 9390 int n = pf->active_vfs; 9391 9392 if (n) 9393 bnxt_cfg_hw_sriov(bp, &n, true); 9394 } 9395 } 9396 9397 static int bnxt_open(struct net_device *dev) 9398 { 9399 struct bnxt *bp = netdev_priv(dev); 9400 int rc; 9401 9402 if (test_bit(BNXT_STATE_ABORT_ERR, &bp->state)) { 9403 netdev_err(bp->dev, "A previous firmware reset did not complete, aborting\n"); 9404 return -ENODEV; 9405 } 9406 9407 rc = bnxt_hwrm_if_change(bp, true); 9408 if (rc) 9409 return rc; 9410 rc = __bnxt_open_nic(bp, true, true); 9411 if (rc) { 9412 bnxt_hwrm_if_change(bp, false); 9413 } else { 9414 if (test_and_clear_bit(BNXT_STATE_FW_RESET_DET, &bp->state)) { 9415 if (!test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) { 9416 bnxt_ulp_start(bp, 0); 9417 bnxt_reenable_sriov(bp); 9418 } 9419 } 9420 bnxt_hwmon_open(bp); 9421 } 9422 9423 return rc; 9424 } 9425 9426 static bool bnxt_drv_busy(struct bnxt *bp) 9427 { 9428 return (test_bit(BNXT_STATE_IN_SP_TASK, &bp->state) || 9429 test_bit(BNXT_STATE_READ_STATS, &bp->state)); 9430 } 9431 9432 static void bnxt_get_ring_stats(struct bnxt *bp, 9433 struct rtnl_link_stats64 *stats); 9434 9435 static void __bnxt_close_nic(struct bnxt *bp, bool irq_re_init, 9436 bool link_re_init) 9437 { 9438 /* Close the VF-reps before closing PF */ 9439 if (BNXT_PF(bp)) 9440 bnxt_vf_reps_close(bp); 9441 9442 /* Change device state to avoid TX queue wake up's */ 9443 bnxt_tx_disable(bp); 9444 9445 clear_bit(BNXT_STATE_OPEN, &bp->state); 9446 smp_mb__after_atomic(); 9447 while (bnxt_drv_busy(bp)) 9448 msleep(20); 9449 9450 /* Flush rings and and disable interrupts */ 9451 bnxt_shutdown_nic(bp, irq_re_init); 9452 9453 /* TODO CHIMP_FW: Link/PHY related cleanup if (link_re_init) */ 9454 9455 bnxt_debug_dev_exit(bp); 9456 bnxt_disable_napi(bp); 9457 del_timer_sync(&bp->timer); 9458 bnxt_free_skbs(bp); 9459 9460 /* Save ring stats before shutdown */ 9461 if (bp->bnapi && irq_re_init) 9462 bnxt_get_ring_stats(bp, &bp->net_stats_prev); 9463 if (irq_re_init) { 9464 bnxt_free_irq(bp); 9465 bnxt_del_napi(bp); 9466 } 9467 bnxt_free_mem(bp, irq_re_init); 9468 } 9469 9470 int bnxt_close_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init) 9471 { 9472 int rc = 0; 9473 9474 if (test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) { 9475 /* If we get here, it means firmware reset is in progress 9476 * while we are trying to close. We can safely proceed with 9477 * the close because we are holding rtnl_lock(). Some firmware 9478 * messages may fail as we proceed to close. We set the 9479 * ABORT_ERR flag here so that the FW reset thread will later 9480 * abort when it gets the rtnl_lock() and sees the flag. 9481 */ 9482 netdev_warn(bp->dev, "FW reset in progress during close, FW reset will be aborted\n"); 9483 set_bit(BNXT_STATE_ABORT_ERR, &bp->state); 9484 } 9485 9486 #ifdef CONFIG_BNXT_SRIOV 9487 if (bp->sriov_cfg) { 9488 rc = wait_event_interruptible_timeout(bp->sriov_cfg_wait, 9489 !bp->sriov_cfg, 9490 BNXT_SRIOV_CFG_WAIT_TMO); 9491 if (rc) 9492 netdev_warn(bp->dev, "timeout waiting for SRIOV config operation to complete!\n"); 9493 } 9494 #endif 9495 __bnxt_close_nic(bp, irq_re_init, link_re_init); 9496 return rc; 9497 } 9498 9499 static int bnxt_close(struct net_device *dev) 9500 { 9501 struct bnxt *bp = netdev_priv(dev); 9502 9503 bnxt_hwmon_close(bp); 9504 bnxt_close_nic(bp, true, true); 9505 bnxt_hwrm_shutdown_link(bp); 9506 bnxt_hwrm_if_change(bp, false); 9507 return 0; 9508 } 9509 9510 static int bnxt_hwrm_port_phy_read(struct bnxt *bp, u16 phy_addr, u16 reg, 9511 u16 *val) 9512 { 9513 struct hwrm_port_phy_mdio_read_output *resp = bp->hwrm_cmd_resp_addr; 9514 struct hwrm_port_phy_mdio_read_input req = {0}; 9515 int rc; 9516 9517 if (bp->hwrm_spec_code < 0x10a00) 9518 return -EOPNOTSUPP; 9519 9520 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_MDIO_READ, -1, -1); 9521 req.port_id = cpu_to_le16(bp->pf.port_id); 9522 req.phy_addr = phy_addr; 9523 req.reg_addr = cpu_to_le16(reg & 0x1f); 9524 if (mdio_phy_id_is_c45(phy_addr)) { 9525 req.cl45_mdio = 1; 9526 req.phy_addr = mdio_phy_id_prtad(phy_addr); 9527 req.dev_addr = mdio_phy_id_devad(phy_addr); 9528 req.reg_addr = cpu_to_le16(reg); 9529 } 9530 9531 mutex_lock(&bp->hwrm_cmd_lock); 9532 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 9533 if (!rc) 9534 *val = le16_to_cpu(resp->reg_data); 9535 mutex_unlock(&bp->hwrm_cmd_lock); 9536 return rc; 9537 } 9538 9539 static int bnxt_hwrm_port_phy_write(struct bnxt *bp, u16 phy_addr, u16 reg, 9540 u16 val) 9541 { 9542 struct hwrm_port_phy_mdio_write_input req = {0}; 9543 9544 if (bp->hwrm_spec_code < 0x10a00) 9545 return -EOPNOTSUPP; 9546 9547 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_MDIO_WRITE, -1, -1); 9548 req.port_id = cpu_to_le16(bp->pf.port_id); 9549 req.phy_addr = phy_addr; 9550 req.reg_addr = cpu_to_le16(reg & 0x1f); 9551 if (mdio_phy_id_is_c45(phy_addr)) { 9552 req.cl45_mdio = 1; 9553 req.phy_addr = mdio_phy_id_prtad(phy_addr); 9554 req.dev_addr = mdio_phy_id_devad(phy_addr); 9555 req.reg_addr = cpu_to_le16(reg); 9556 } 9557 req.reg_data = cpu_to_le16(val); 9558 9559 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 9560 } 9561 9562 /* rtnl_lock held */ 9563 static int bnxt_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 9564 { 9565 struct mii_ioctl_data *mdio = if_mii(ifr); 9566 struct bnxt *bp = netdev_priv(dev); 9567 int rc; 9568 9569 switch (cmd) { 9570 case SIOCGMIIPHY: 9571 mdio->phy_id = bp->link_info.phy_addr; 9572 9573 /* fallthru */ 9574 case SIOCGMIIREG: { 9575 u16 mii_regval = 0; 9576 9577 if (!netif_running(dev)) 9578 return -EAGAIN; 9579 9580 rc = bnxt_hwrm_port_phy_read(bp, mdio->phy_id, mdio->reg_num, 9581 &mii_regval); 9582 mdio->val_out = mii_regval; 9583 return rc; 9584 } 9585 9586 case SIOCSMIIREG: 9587 if (!netif_running(dev)) 9588 return -EAGAIN; 9589 9590 return bnxt_hwrm_port_phy_write(bp, mdio->phy_id, mdio->reg_num, 9591 mdio->val_in); 9592 9593 default: 9594 /* do nothing */ 9595 break; 9596 } 9597 return -EOPNOTSUPP; 9598 } 9599 9600 static void bnxt_get_ring_stats(struct bnxt *bp, 9601 struct rtnl_link_stats64 *stats) 9602 { 9603 int i; 9604 9605 9606 for (i = 0; i < bp->cp_nr_rings; i++) { 9607 struct bnxt_napi *bnapi = bp->bnapi[i]; 9608 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 9609 struct ctx_hw_stats *hw_stats = cpr->hw_stats; 9610 9611 stats->rx_packets += le64_to_cpu(hw_stats->rx_ucast_pkts); 9612 stats->rx_packets += le64_to_cpu(hw_stats->rx_mcast_pkts); 9613 stats->rx_packets += le64_to_cpu(hw_stats->rx_bcast_pkts); 9614 9615 stats->tx_packets += le64_to_cpu(hw_stats->tx_ucast_pkts); 9616 stats->tx_packets += le64_to_cpu(hw_stats->tx_mcast_pkts); 9617 stats->tx_packets += le64_to_cpu(hw_stats->tx_bcast_pkts); 9618 9619 stats->rx_bytes += le64_to_cpu(hw_stats->rx_ucast_bytes); 9620 stats->rx_bytes += le64_to_cpu(hw_stats->rx_mcast_bytes); 9621 stats->rx_bytes += le64_to_cpu(hw_stats->rx_bcast_bytes); 9622 9623 stats->tx_bytes += le64_to_cpu(hw_stats->tx_ucast_bytes); 9624 stats->tx_bytes += le64_to_cpu(hw_stats->tx_mcast_bytes); 9625 stats->tx_bytes += le64_to_cpu(hw_stats->tx_bcast_bytes); 9626 9627 stats->rx_missed_errors += 9628 le64_to_cpu(hw_stats->rx_discard_pkts); 9629 9630 stats->multicast += le64_to_cpu(hw_stats->rx_mcast_pkts); 9631 9632 stats->tx_dropped += le64_to_cpu(hw_stats->tx_drop_pkts); 9633 } 9634 } 9635 9636 static void bnxt_add_prev_stats(struct bnxt *bp, 9637 struct rtnl_link_stats64 *stats) 9638 { 9639 struct rtnl_link_stats64 *prev_stats = &bp->net_stats_prev; 9640 9641 stats->rx_packets += prev_stats->rx_packets; 9642 stats->tx_packets += prev_stats->tx_packets; 9643 stats->rx_bytes += prev_stats->rx_bytes; 9644 stats->tx_bytes += prev_stats->tx_bytes; 9645 stats->rx_missed_errors += prev_stats->rx_missed_errors; 9646 stats->multicast += prev_stats->multicast; 9647 stats->tx_dropped += prev_stats->tx_dropped; 9648 } 9649 9650 static void 9651 bnxt_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) 9652 { 9653 struct bnxt *bp = netdev_priv(dev); 9654 9655 set_bit(BNXT_STATE_READ_STATS, &bp->state); 9656 /* Make sure bnxt_close_nic() sees that we are reading stats before 9657 * we check the BNXT_STATE_OPEN flag. 9658 */ 9659 smp_mb__after_atomic(); 9660 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) { 9661 clear_bit(BNXT_STATE_READ_STATS, &bp->state); 9662 *stats = bp->net_stats_prev; 9663 return; 9664 } 9665 9666 bnxt_get_ring_stats(bp, stats); 9667 bnxt_add_prev_stats(bp, stats); 9668 9669 if (bp->flags & BNXT_FLAG_PORT_STATS) { 9670 struct rx_port_stats *rx = bp->hw_rx_port_stats; 9671 struct tx_port_stats *tx = bp->hw_tx_port_stats; 9672 9673 stats->rx_crc_errors = le64_to_cpu(rx->rx_fcs_err_frames); 9674 stats->rx_frame_errors = le64_to_cpu(rx->rx_align_err_frames); 9675 stats->rx_length_errors = le64_to_cpu(rx->rx_undrsz_frames) + 9676 le64_to_cpu(rx->rx_ovrsz_frames) + 9677 le64_to_cpu(rx->rx_runt_frames); 9678 stats->rx_errors = le64_to_cpu(rx->rx_false_carrier_frames) + 9679 le64_to_cpu(rx->rx_jbr_frames); 9680 stats->collisions = le64_to_cpu(tx->tx_total_collisions); 9681 stats->tx_fifo_errors = le64_to_cpu(tx->tx_fifo_underruns); 9682 stats->tx_errors = le64_to_cpu(tx->tx_err); 9683 } 9684 clear_bit(BNXT_STATE_READ_STATS, &bp->state); 9685 } 9686 9687 static bool bnxt_mc_list_updated(struct bnxt *bp, u32 *rx_mask) 9688 { 9689 struct net_device *dev = bp->dev; 9690 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 9691 struct netdev_hw_addr *ha; 9692 u8 *haddr; 9693 int mc_count = 0; 9694 bool update = false; 9695 int off = 0; 9696 9697 netdev_for_each_mc_addr(ha, dev) { 9698 if (mc_count >= BNXT_MAX_MC_ADDRS) { 9699 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST; 9700 vnic->mc_list_count = 0; 9701 return false; 9702 } 9703 haddr = ha->addr; 9704 if (!ether_addr_equal(haddr, vnic->mc_list + off)) { 9705 memcpy(vnic->mc_list + off, haddr, ETH_ALEN); 9706 update = true; 9707 } 9708 off += ETH_ALEN; 9709 mc_count++; 9710 } 9711 if (mc_count) 9712 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_MCAST; 9713 9714 if (mc_count != vnic->mc_list_count) { 9715 vnic->mc_list_count = mc_count; 9716 update = true; 9717 } 9718 return update; 9719 } 9720 9721 static bool bnxt_uc_list_updated(struct bnxt *bp) 9722 { 9723 struct net_device *dev = bp->dev; 9724 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 9725 struct netdev_hw_addr *ha; 9726 int off = 0; 9727 9728 if (netdev_uc_count(dev) != (vnic->uc_filter_count - 1)) 9729 return true; 9730 9731 netdev_for_each_uc_addr(ha, dev) { 9732 if (!ether_addr_equal(ha->addr, vnic->uc_list + off)) 9733 return true; 9734 9735 off += ETH_ALEN; 9736 } 9737 return false; 9738 } 9739 9740 static void bnxt_set_rx_mode(struct net_device *dev) 9741 { 9742 struct bnxt *bp = netdev_priv(dev); 9743 struct bnxt_vnic_info *vnic; 9744 bool mc_update = false; 9745 bool uc_update; 9746 u32 mask; 9747 9748 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) 9749 return; 9750 9751 vnic = &bp->vnic_info[0]; 9752 mask = vnic->rx_mask; 9753 mask &= ~(CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS | 9754 CFA_L2_SET_RX_MASK_REQ_MASK_MCAST | 9755 CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST | 9756 CFA_L2_SET_RX_MASK_REQ_MASK_BCAST); 9757 9758 if ((dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp)) 9759 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS; 9760 9761 uc_update = bnxt_uc_list_updated(bp); 9762 9763 if (dev->flags & IFF_BROADCAST) 9764 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_BCAST; 9765 if (dev->flags & IFF_ALLMULTI) { 9766 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST; 9767 vnic->mc_list_count = 0; 9768 } else { 9769 mc_update = bnxt_mc_list_updated(bp, &mask); 9770 } 9771 9772 if (mask != vnic->rx_mask || uc_update || mc_update) { 9773 vnic->rx_mask = mask; 9774 9775 set_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event); 9776 bnxt_queue_sp_work(bp); 9777 } 9778 } 9779 9780 static int bnxt_cfg_rx_mode(struct bnxt *bp) 9781 { 9782 struct net_device *dev = bp->dev; 9783 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 9784 struct netdev_hw_addr *ha; 9785 int i, off = 0, rc; 9786 bool uc_update; 9787 9788 netif_addr_lock_bh(dev); 9789 uc_update = bnxt_uc_list_updated(bp); 9790 netif_addr_unlock_bh(dev); 9791 9792 if (!uc_update) 9793 goto skip_uc; 9794 9795 mutex_lock(&bp->hwrm_cmd_lock); 9796 for (i = 1; i < vnic->uc_filter_count; i++) { 9797 struct hwrm_cfa_l2_filter_free_input req = {0}; 9798 9799 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_FREE, -1, 9800 -1); 9801 9802 req.l2_filter_id = vnic->fw_l2_filter_id[i]; 9803 9804 rc = _hwrm_send_message(bp, &req, sizeof(req), 9805 HWRM_CMD_TIMEOUT); 9806 } 9807 mutex_unlock(&bp->hwrm_cmd_lock); 9808 9809 vnic->uc_filter_count = 1; 9810 9811 netif_addr_lock_bh(dev); 9812 if (netdev_uc_count(dev) > (BNXT_MAX_UC_ADDRS - 1)) { 9813 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS; 9814 } else { 9815 netdev_for_each_uc_addr(ha, dev) { 9816 memcpy(vnic->uc_list + off, ha->addr, ETH_ALEN); 9817 off += ETH_ALEN; 9818 vnic->uc_filter_count++; 9819 } 9820 } 9821 netif_addr_unlock_bh(dev); 9822 9823 for (i = 1, off = 0; i < vnic->uc_filter_count; i++, off += ETH_ALEN) { 9824 rc = bnxt_hwrm_set_vnic_filter(bp, 0, i, vnic->uc_list + off); 9825 if (rc) { 9826 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n", 9827 rc); 9828 vnic->uc_filter_count = i; 9829 return rc; 9830 } 9831 } 9832 9833 skip_uc: 9834 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0); 9835 if (rc && vnic->mc_list_count) { 9836 netdev_info(bp->dev, "Failed setting MC filters rc: %d, turning on ALL_MCAST mode\n", 9837 rc); 9838 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST; 9839 vnic->mc_list_count = 0; 9840 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0); 9841 } 9842 if (rc) 9843 netdev_err(bp->dev, "HWRM cfa l2 rx mask failure rc: %d\n", 9844 rc); 9845 9846 return rc; 9847 } 9848 9849 static bool bnxt_can_reserve_rings(struct bnxt *bp) 9850 { 9851 #ifdef CONFIG_BNXT_SRIOV 9852 if (BNXT_NEW_RM(bp) && BNXT_VF(bp)) { 9853 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 9854 9855 /* No minimum rings were provisioned by the PF. Don't 9856 * reserve rings by default when device is down. 9857 */ 9858 if (hw_resc->min_tx_rings || hw_resc->resv_tx_rings) 9859 return true; 9860 9861 if (!netif_running(bp->dev)) 9862 return false; 9863 } 9864 #endif 9865 return true; 9866 } 9867 9868 /* If the chip and firmware supports RFS */ 9869 static bool bnxt_rfs_supported(struct bnxt *bp) 9870 { 9871 if (bp->flags & BNXT_FLAG_CHIP_P5) { 9872 if (bp->fw_cap & BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V2) 9873 return true; 9874 return false; 9875 } 9876 if (BNXT_PF(bp) && !BNXT_CHIP_TYPE_NITRO_A0(bp)) 9877 return true; 9878 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP) 9879 return true; 9880 return false; 9881 } 9882 9883 /* If runtime conditions support RFS */ 9884 static bool bnxt_rfs_capable(struct bnxt *bp) 9885 { 9886 #ifdef CONFIG_RFS_ACCEL 9887 int vnics, max_vnics, max_rss_ctxs; 9888 9889 if (bp->flags & BNXT_FLAG_CHIP_P5) 9890 return bnxt_rfs_supported(bp); 9891 if (!(bp->flags & BNXT_FLAG_MSIX_CAP) || !bnxt_can_reserve_rings(bp)) 9892 return false; 9893 9894 vnics = 1 + bp->rx_nr_rings; 9895 max_vnics = bnxt_get_max_func_vnics(bp); 9896 max_rss_ctxs = bnxt_get_max_func_rss_ctxs(bp); 9897 9898 /* RSS contexts not a limiting factor */ 9899 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP) 9900 max_rss_ctxs = max_vnics; 9901 if (vnics > max_vnics || vnics > max_rss_ctxs) { 9902 if (bp->rx_nr_rings > 1) 9903 netdev_warn(bp->dev, 9904 "Not enough resources to support NTUPLE filters, enough resources for up to %d rx rings\n", 9905 min(max_rss_ctxs - 1, max_vnics - 1)); 9906 return false; 9907 } 9908 9909 if (!BNXT_NEW_RM(bp)) 9910 return true; 9911 9912 if (vnics == bp->hw_resc.resv_vnics) 9913 return true; 9914 9915 bnxt_hwrm_reserve_rings(bp, 0, 0, 0, 0, 0, vnics); 9916 if (vnics <= bp->hw_resc.resv_vnics) 9917 return true; 9918 9919 netdev_warn(bp->dev, "Unable to reserve resources to support NTUPLE filters.\n"); 9920 bnxt_hwrm_reserve_rings(bp, 0, 0, 0, 0, 0, 1); 9921 return false; 9922 #else 9923 return false; 9924 #endif 9925 } 9926 9927 static netdev_features_t bnxt_fix_features(struct net_device *dev, 9928 netdev_features_t features) 9929 { 9930 struct bnxt *bp = netdev_priv(dev); 9931 netdev_features_t vlan_features; 9932 9933 if ((features & NETIF_F_NTUPLE) && !bnxt_rfs_capable(bp)) 9934 features &= ~NETIF_F_NTUPLE; 9935 9936 if (bp->flags & BNXT_FLAG_NO_AGG_RINGS) 9937 features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW); 9938 9939 if (!(features & NETIF_F_GRO)) 9940 features &= ~NETIF_F_GRO_HW; 9941 9942 if (features & NETIF_F_GRO_HW) 9943 features &= ~NETIF_F_LRO; 9944 9945 /* Both CTAG and STAG VLAN accelaration on the RX side have to be 9946 * turned on or off together. 9947 */ 9948 vlan_features = features & BNXT_HW_FEATURE_VLAN_ALL_RX; 9949 if (vlan_features != BNXT_HW_FEATURE_VLAN_ALL_RX) { 9950 if (dev->features & BNXT_HW_FEATURE_VLAN_ALL_RX) 9951 features &= ~BNXT_HW_FEATURE_VLAN_ALL_RX; 9952 else if (vlan_features) 9953 features |= BNXT_HW_FEATURE_VLAN_ALL_RX; 9954 } 9955 #ifdef CONFIG_BNXT_SRIOV 9956 if (BNXT_VF(bp) && bp->vf.vlan) 9957 features &= ~BNXT_HW_FEATURE_VLAN_ALL_RX; 9958 #endif 9959 return features; 9960 } 9961 9962 static int bnxt_set_features(struct net_device *dev, netdev_features_t features) 9963 { 9964 struct bnxt *bp = netdev_priv(dev); 9965 u32 flags = bp->flags; 9966 u32 changes; 9967 int rc = 0; 9968 bool re_init = false; 9969 bool update_tpa = false; 9970 9971 flags &= ~BNXT_FLAG_ALL_CONFIG_FEATS; 9972 if (features & NETIF_F_GRO_HW) 9973 flags |= BNXT_FLAG_GRO; 9974 else if (features & NETIF_F_LRO) 9975 flags |= BNXT_FLAG_LRO; 9976 9977 if (bp->flags & BNXT_FLAG_NO_AGG_RINGS) 9978 flags &= ~BNXT_FLAG_TPA; 9979 9980 if (features & BNXT_HW_FEATURE_VLAN_ALL_RX) 9981 flags |= BNXT_FLAG_STRIP_VLAN; 9982 9983 if (features & NETIF_F_NTUPLE) 9984 flags |= BNXT_FLAG_RFS; 9985 9986 changes = flags ^ bp->flags; 9987 if (changes & BNXT_FLAG_TPA) { 9988 update_tpa = true; 9989 if ((bp->flags & BNXT_FLAG_TPA) == 0 || 9990 (flags & BNXT_FLAG_TPA) == 0 || 9991 (bp->flags & BNXT_FLAG_CHIP_P5)) 9992 re_init = true; 9993 } 9994 9995 if (changes & ~BNXT_FLAG_TPA) 9996 re_init = true; 9997 9998 if (flags != bp->flags) { 9999 u32 old_flags = bp->flags; 10000 10001 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) { 10002 bp->flags = flags; 10003 if (update_tpa) 10004 bnxt_set_ring_params(bp); 10005 return rc; 10006 } 10007 10008 if (re_init) { 10009 bnxt_close_nic(bp, false, false); 10010 bp->flags = flags; 10011 if (update_tpa) 10012 bnxt_set_ring_params(bp); 10013 10014 return bnxt_open_nic(bp, false, false); 10015 } 10016 if (update_tpa) { 10017 bp->flags = flags; 10018 rc = bnxt_set_tpa(bp, 10019 (flags & BNXT_FLAG_TPA) ? 10020 true : false); 10021 if (rc) 10022 bp->flags = old_flags; 10023 } 10024 } 10025 return rc; 10026 } 10027 10028 static int bnxt_dbg_hwrm_ring_info_get(struct bnxt *bp, u8 ring_type, 10029 u32 ring_id, u32 *prod, u32 *cons) 10030 { 10031 struct hwrm_dbg_ring_info_get_output *resp = bp->hwrm_cmd_resp_addr; 10032 struct hwrm_dbg_ring_info_get_input req = {0}; 10033 int rc; 10034 10035 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_DBG_RING_INFO_GET, -1, -1); 10036 req.ring_type = ring_type; 10037 req.fw_ring_id = cpu_to_le32(ring_id); 10038 mutex_lock(&bp->hwrm_cmd_lock); 10039 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 10040 if (!rc) { 10041 *prod = le32_to_cpu(resp->producer_index); 10042 *cons = le32_to_cpu(resp->consumer_index); 10043 } 10044 mutex_unlock(&bp->hwrm_cmd_lock); 10045 return rc; 10046 } 10047 10048 static void bnxt_dump_tx_sw_state(struct bnxt_napi *bnapi) 10049 { 10050 struct bnxt_tx_ring_info *txr = bnapi->tx_ring; 10051 int i = bnapi->index; 10052 10053 if (!txr) 10054 return; 10055 10056 netdev_info(bnapi->bp->dev, "[%d]: tx{fw_ring: %d prod: %x cons: %x}\n", 10057 i, txr->tx_ring_struct.fw_ring_id, txr->tx_prod, 10058 txr->tx_cons); 10059 } 10060 10061 static void bnxt_dump_rx_sw_state(struct bnxt_napi *bnapi) 10062 { 10063 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 10064 int i = bnapi->index; 10065 10066 if (!rxr) 10067 return; 10068 10069 netdev_info(bnapi->bp->dev, "[%d]: rx{fw_ring: %d prod: %x} rx_agg{fw_ring: %d agg_prod: %x sw_agg_prod: %x}\n", 10070 i, rxr->rx_ring_struct.fw_ring_id, rxr->rx_prod, 10071 rxr->rx_agg_ring_struct.fw_ring_id, rxr->rx_agg_prod, 10072 rxr->rx_sw_agg_prod); 10073 } 10074 10075 static void bnxt_dump_cp_sw_state(struct bnxt_napi *bnapi) 10076 { 10077 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 10078 int i = bnapi->index; 10079 10080 netdev_info(bnapi->bp->dev, "[%d]: cp{fw_ring: %d raw_cons: %x}\n", 10081 i, cpr->cp_ring_struct.fw_ring_id, cpr->cp_raw_cons); 10082 } 10083 10084 static void bnxt_dbg_dump_states(struct bnxt *bp) 10085 { 10086 int i; 10087 struct bnxt_napi *bnapi; 10088 10089 for (i = 0; i < bp->cp_nr_rings; i++) { 10090 bnapi = bp->bnapi[i]; 10091 if (netif_msg_drv(bp)) { 10092 bnxt_dump_tx_sw_state(bnapi); 10093 bnxt_dump_rx_sw_state(bnapi); 10094 bnxt_dump_cp_sw_state(bnapi); 10095 } 10096 } 10097 } 10098 10099 static void bnxt_reset_task(struct bnxt *bp, bool silent) 10100 { 10101 if (!silent) 10102 bnxt_dbg_dump_states(bp); 10103 if (netif_running(bp->dev)) { 10104 int rc; 10105 10106 if (silent) { 10107 bnxt_close_nic(bp, false, false); 10108 bnxt_open_nic(bp, false, false); 10109 } else { 10110 bnxt_ulp_stop(bp); 10111 bnxt_close_nic(bp, true, false); 10112 rc = bnxt_open_nic(bp, true, false); 10113 bnxt_ulp_start(bp, rc); 10114 } 10115 } 10116 } 10117 10118 static void bnxt_tx_timeout(struct net_device *dev, unsigned int txqueue) 10119 { 10120 struct bnxt *bp = netdev_priv(dev); 10121 10122 netdev_err(bp->dev, "TX timeout detected, starting reset task!\n"); 10123 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event); 10124 bnxt_queue_sp_work(bp); 10125 } 10126 10127 static void bnxt_fw_health_check(struct bnxt *bp) 10128 { 10129 struct bnxt_fw_health *fw_health = bp->fw_health; 10130 u32 val; 10131 10132 if (!fw_health->enabled || test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) 10133 return; 10134 10135 if (fw_health->tmr_counter) { 10136 fw_health->tmr_counter--; 10137 return; 10138 } 10139 10140 val = bnxt_fw_health_readl(bp, BNXT_FW_HEARTBEAT_REG); 10141 if (val == fw_health->last_fw_heartbeat) 10142 goto fw_reset; 10143 10144 fw_health->last_fw_heartbeat = val; 10145 10146 val = bnxt_fw_health_readl(bp, BNXT_FW_RESET_CNT_REG); 10147 if (val != fw_health->last_fw_reset_cnt) 10148 goto fw_reset; 10149 10150 fw_health->tmr_counter = fw_health->tmr_multiplier; 10151 return; 10152 10153 fw_reset: 10154 set_bit(BNXT_FW_EXCEPTION_SP_EVENT, &bp->sp_event); 10155 bnxt_queue_sp_work(bp); 10156 } 10157 10158 static void bnxt_timer(struct timer_list *t) 10159 { 10160 struct bnxt *bp = from_timer(bp, t, timer); 10161 struct net_device *dev = bp->dev; 10162 10163 if (!netif_running(dev) || !test_bit(BNXT_STATE_OPEN, &bp->state)) 10164 return; 10165 10166 if (atomic_read(&bp->intr_sem) != 0) 10167 goto bnxt_restart_timer; 10168 10169 if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY) 10170 bnxt_fw_health_check(bp); 10171 10172 if (bp->link_info.link_up && (bp->flags & BNXT_FLAG_PORT_STATS) && 10173 bp->stats_coal_ticks) { 10174 set_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event); 10175 bnxt_queue_sp_work(bp); 10176 } 10177 10178 if (bnxt_tc_flower_enabled(bp)) { 10179 set_bit(BNXT_FLOW_STATS_SP_EVENT, &bp->sp_event); 10180 bnxt_queue_sp_work(bp); 10181 } 10182 10183 #ifdef CONFIG_RFS_ACCEL 10184 if ((bp->flags & BNXT_FLAG_RFS) && bp->ntp_fltr_count) { 10185 set_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event); 10186 bnxt_queue_sp_work(bp); 10187 } 10188 #endif /*CONFIG_RFS_ACCEL*/ 10189 10190 if (bp->link_info.phy_retry) { 10191 if (time_after(jiffies, bp->link_info.phy_retry_expires)) { 10192 bp->link_info.phy_retry = false; 10193 netdev_warn(bp->dev, "failed to update phy settings after maximum retries.\n"); 10194 } else { 10195 set_bit(BNXT_UPDATE_PHY_SP_EVENT, &bp->sp_event); 10196 bnxt_queue_sp_work(bp); 10197 } 10198 } 10199 10200 if ((bp->flags & BNXT_FLAG_CHIP_P5) && !bp->chip_rev && 10201 netif_carrier_ok(dev)) { 10202 set_bit(BNXT_RING_COAL_NOW_SP_EVENT, &bp->sp_event); 10203 bnxt_queue_sp_work(bp); 10204 } 10205 bnxt_restart_timer: 10206 mod_timer(&bp->timer, jiffies + bp->current_interval); 10207 } 10208 10209 static void bnxt_rtnl_lock_sp(struct bnxt *bp) 10210 { 10211 /* We are called from bnxt_sp_task which has BNXT_STATE_IN_SP_TASK 10212 * set. If the device is being closed, bnxt_close() may be holding 10213 * rtnl() and waiting for BNXT_STATE_IN_SP_TASK to clear. So we 10214 * must clear BNXT_STATE_IN_SP_TASK before holding rtnl(). 10215 */ 10216 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state); 10217 rtnl_lock(); 10218 } 10219 10220 static void bnxt_rtnl_unlock_sp(struct bnxt *bp) 10221 { 10222 set_bit(BNXT_STATE_IN_SP_TASK, &bp->state); 10223 rtnl_unlock(); 10224 } 10225 10226 /* Only called from bnxt_sp_task() */ 10227 static void bnxt_reset(struct bnxt *bp, bool silent) 10228 { 10229 bnxt_rtnl_lock_sp(bp); 10230 if (test_bit(BNXT_STATE_OPEN, &bp->state)) 10231 bnxt_reset_task(bp, silent); 10232 bnxt_rtnl_unlock_sp(bp); 10233 } 10234 10235 static void bnxt_fw_reset_close(struct bnxt *bp) 10236 { 10237 bnxt_ulp_stop(bp); 10238 /* When firmware is fatal state, disable PCI device to prevent 10239 * any potential bad DMAs before freeing kernel memory. 10240 */ 10241 if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state)) 10242 pci_disable_device(bp->pdev); 10243 __bnxt_close_nic(bp, true, false); 10244 bnxt_clear_int_mode(bp); 10245 bnxt_hwrm_func_drv_unrgtr(bp); 10246 if (pci_is_enabled(bp->pdev)) 10247 pci_disable_device(bp->pdev); 10248 bnxt_free_ctx_mem(bp); 10249 kfree(bp->ctx); 10250 bp->ctx = NULL; 10251 } 10252 10253 static bool is_bnxt_fw_ok(struct bnxt *bp) 10254 { 10255 struct bnxt_fw_health *fw_health = bp->fw_health; 10256 bool no_heartbeat = false, has_reset = false; 10257 u32 val; 10258 10259 val = bnxt_fw_health_readl(bp, BNXT_FW_HEARTBEAT_REG); 10260 if (val == fw_health->last_fw_heartbeat) 10261 no_heartbeat = true; 10262 10263 val = bnxt_fw_health_readl(bp, BNXT_FW_RESET_CNT_REG); 10264 if (val != fw_health->last_fw_reset_cnt) 10265 has_reset = true; 10266 10267 if (!no_heartbeat && has_reset) 10268 return true; 10269 10270 return false; 10271 } 10272 10273 /* rtnl_lock is acquired before calling this function */ 10274 static void bnxt_force_fw_reset(struct bnxt *bp) 10275 { 10276 struct bnxt_fw_health *fw_health = bp->fw_health; 10277 u32 wait_dsecs; 10278 10279 if (!test_bit(BNXT_STATE_OPEN, &bp->state) || 10280 test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) 10281 return; 10282 10283 set_bit(BNXT_STATE_IN_FW_RESET, &bp->state); 10284 bnxt_fw_reset_close(bp); 10285 wait_dsecs = fw_health->master_func_wait_dsecs; 10286 if (fw_health->master) { 10287 if (fw_health->flags & ERROR_RECOVERY_QCFG_RESP_FLAGS_CO_CPU) 10288 wait_dsecs = 0; 10289 bp->fw_reset_state = BNXT_FW_RESET_STATE_RESET_FW; 10290 } else { 10291 bp->fw_reset_timestamp = jiffies + wait_dsecs * HZ / 10; 10292 wait_dsecs = fw_health->normal_func_wait_dsecs; 10293 bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV; 10294 } 10295 10296 bp->fw_reset_min_dsecs = fw_health->post_reset_wait_dsecs; 10297 bp->fw_reset_max_dsecs = fw_health->post_reset_max_wait_dsecs; 10298 bnxt_queue_fw_reset_work(bp, wait_dsecs * HZ / 10); 10299 } 10300 10301 void bnxt_fw_exception(struct bnxt *bp) 10302 { 10303 netdev_warn(bp->dev, "Detected firmware fatal condition, initiating reset\n"); 10304 set_bit(BNXT_STATE_FW_FATAL_COND, &bp->state); 10305 bnxt_rtnl_lock_sp(bp); 10306 bnxt_force_fw_reset(bp); 10307 bnxt_rtnl_unlock_sp(bp); 10308 } 10309 10310 /* Returns the number of registered VFs, or 1 if VF configuration is pending, or 10311 * < 0 on error. 10312 */ 10313 static int bnxt_get_registered_vfs(struct bnxt *bp) 10314 { 10315 #ifdef CONFIG_BNXT_SRIOV 10316 int rc; 10317 10318 if (!BNXT_PF(bp)) 10319 return 0; 10320 10321 rc = bnxt_hwrm_func_qcfg(bp); 10322 if (rc) { 10323 netdev_err(bp->dev, "func_qcfg cmd failed, rc = %d\n", rc); 10324 return rc; 10325 } 10326 if (bp->pf.registered_vfs) 10327 return bp->pf.registered_vfs; 10328 if (bp->sriov_cfg) 10329 return 1; 10330 #endif 10331 return 0; 10332 } 10333 10334 void bnxt_fw_reset(struct bnxt *bp) 10335 { 10336 bnxt_rtnl_lock_sp(bp); 10337 if (test_bit(BNXT_STATE_OPEN, &bp->state) && 10338 !test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) { 10339 int n = 0, tmo; 10340 10341 set_bit(BNXT_STATE_IN_FW_RESET, &bp->state); 10342 if (bp->pf.active_vfs && 10343 !test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state)) 10344 n = bnxt_get_registered_vfs(bp); 10345 if (n < 0) { 10346 netdev_err(bp->dev, "Firmware reset aborted, rc = %d\n", 10347 n); 10348 clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state); 10349 dev_close(bp->dev); 10350 goto fw_reset_exit; 10351 } else if (n > 0) { 10352 u16 vf_tmo_dsecs = n * 10; 10353 10354 if (bp->fw_reset_max_dsecs < vf_tmo_dsecs) 10355 bp->fw_reset_max_dsecs = vf_tmo_dsecs; 10356 bp->fw_reset_state = 10357 BNXT_FW_RESET_STATE_POLL_VF; 10358 bnxt_queue_fw_reset_work(bp, HZ / 10); 10359 goto fw_reset_exit; 10360 } 10361 bnxt_fw_reset_close(bp); 10362 if (bp->fw_cap & BNXT_FW_CAP_ERR_RECOVER_RELOAD) { 10363 bp->fw_reset_state = BNXT_FW_RESET_STATE_POLL_FW_DOWN; 10364 tmo = HZ / 10; 10365 } else { 10366 bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV; 10367 tmo = bp->fw_reset_min_dsecs * HZ / 10; 10368 } 10369 bnxt_queue_fw_reset_work(bp, tmo); 10370 } 10371 fw_reset_exit: 10372 bnxt_rtnl_unlock_sp(bp); 10373 } 10374 10375 static void bnxt_chk_missed_irq(struct bnxt *bp) 10376 { 10377 int i; 10378 10379 if (!(bp->flags & BNXT_FLAG_CHIP_P5)) 10380 return; 10381 10382 for (i = 0; i < bp->cp_nr_rings; i++) { 10383 struct bnxt_napi *bnapi = bp->bnapi[i]; 10384 struct bnxt_cp_ring_info *cpr; 10385 u32 fw_ring_id; 10386 int j; 10387 10388 if (!bnapi) 10389 continue; 10390 10391 cpr = &bnapi->cp_ring; 10392 for (j = 0; j < 2; j++) { 10393 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j]; 10394 u32 val[2]; 10395 10396 if (!cpr2 || cpr2->has_more_work || 10397 !bnxt_has_work(bp, cpr2)) 10398 continue; 10399 10400 if (cpr2->cp_raw_cons != cpr2->last_cp_raw_cons) { 10401 cpr2->last_cp_raw_cons = cpr2->cp_raw_cons; 10402 continue; 10403 } 10404 fw_ring_id = cpr2->cp_ring_struct.fw_ring_id; 10405 bnxt_dbg_hwrm_ring_info_get(bp, 10406 DBG_RING_INFO_GET_REQ_RING_TYPE_L2_CMPL, 10407 fw_ring_id, &val[0], &val[1]); 10408 cpr->sw_stats.cmn.missed_irqs++; 10409 } 10410 } 10411 } 10412 10413 static void bnxt_cfg_ntp_filters(struct bnxt *); 10414 10415 static void bnxt_init_ethtool_link_settings(struct bnxt *bp) 10416 { 10417 struct bnxt_link_info *link_info = &bp->link_info; 10418 10419 if (BNXT_AUTO_MODE(link_info->auto_mode)) { 10420 link_info->autoneg = BNXT_AUTONEG_SPEED; 10421 if (bp->hwrm_spec_code >= 0x10201) { 10422 if (link_info->auto_pause_setting & 10423 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE) 10424 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL; 10425 } else { 10426 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL; 10427 } 10428 link_info->advertising = link_info->auto_link_speeds; 10429 } else { 10430 link_info->req_link_speed = link_info->force_link_speed; 10431 link_info->req_duplex = link_info->duplex_setting; 10432 } 10433 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) 10434 link_info->req_flow_ctrl = 10435 link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH; 10436 else 10437 link_info->req_flow_ctrl = link_info->force_pause_setting; 10438 } 10439 10440 static void bnxt_sp_task(struct work_struct *work) 10441 { 10442 struct bnxt *bp = container_of(work, struct bnxt, sp_task); 10443 10444 set_bit(BNXT_STATE_IN_SP_TASK, &bp->state); 10445 smp_mb__after_atomic(); 10446 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) { 10447 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state); 10448 return; 10449 } 10450 10451 if (test_and_clear_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event)) 10452 bnxt_cfg_rx_mode(bp); 10453 10454 if (test_and_clear_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event)) 10455 bnxt_cfg_ntp_filters(bp); 10456 if (test_and_clear_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event)) 10457 bnxt_hwrm_exec_fwd_req(bp); 10458 if (test_and_clear_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event)) { 10459 bnxt_hwrm_port_qstats(bp); 10460 bnxt_hwrm_port_qstats_ext(bp); 10461 bnxt_hwrm_pcie_qstats(bp); 10462 } 10463 10464 if (test_and_clear_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event)) { 10465 int rc; 10466 10467 mutex_lock(&bp->link_lock); 10468 if (test_and_clear_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT, 10469 &bp->sp_event)) 10470 bnxt_hwrm_phy_qcaps(bp); 10471 10472 if (test_and_clear_bit(BNXT_LINK_CFG_CHANGE_SP_EVENT, 10473 &bp->sp_event)) 10474 bnxt_init_ethtool_link_settings(bp); 10475 10476 rc = bnxt_update_link(bp, true); 10477 mutex_unlock(&bp->link_lock); 10478 if (rc) 10479 netdev_err(bp->dev, "SP task can't update link (rc: %x)\n", 10480 rc); 10481 } 10482 if (test_and_clear_bit(BNXT_UPDATE_PHY_SP_EVENT, &bp->sp_event)) { 10483 int rc; 10484 10485 mutex_lock(&bp->link_lock); 10486 rc = bnxt_update_phy_setting(bp); 10487 mutex_unlock(&bp->link_lock); 10488 if (rc) { 10489 netdev_warn(bp->dev, "update phy settings retry failed\n"); 10490 } else { 10491 bp->link_info.phy_retry = false; 10492 netdev_info(bp->dev, "update phy settings retry succeeded\n"); 10493 } 10494 } 10495 if (test_and_clear_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event)) { 10496 mutex_lock(&bp->link_lock); 10497 bnxt_get_port_module_status(bp); 10498 mutex_unlock(&bp->link_lock); 10499 } 10500 10501 if (test_and_clear_bit(BNXT_FLOW_STATS_SP_EVENT, &bp->sp_event)) 10502 bnxt_tc_flow_stats_work(bp); 10503 10504 if (test_and_clear_bit(BNXT_RING_COAL_NOW_SP_EVENT, &bp->sp_event)) 10505 bnxt_chk_missed_irq(bp); 10506 10507 /* These functions below will clear BNXT_STATE_IN_SP_TASK. They 10508 * must be the last functions to be called before exiting. 10509 */ 10510 if (test_and_clear_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event)) 10511 bnxt_reset(bp, false); 10512 10513 if (test_and_clear_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event)) 10514 bnxt_reset(bp, true); 10515 10516 if (test_and_clear_bit(BNXT_FW_RESET_NOTIFY_SP_EVENT, &bp->sp_event)) 10517 bnxt_devlink_health_report(bp, BNXT_FW_RESET_NOTIFY_SP_EVENT); 10518 10519 if (test_and_clear_bit(BNXT_FW_EXCEPTION_SP_EVENT, &bp->sp_event)) { 10520 if (!is_bnxt_fw_ok(bp)) 10521 bnxt_devlink_health_report(bp, 10522 BNXT_FW_EXCEPTION_SP_EVENT); 10523 } 10524 10525 smp_mb__before_atomic(); 10526 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state); 10527 } 10528 10529 /* Under rtnl_lock */ 10530 int bnxt_check_rings(struct bnxt *bp, int tx, int rx, bool sh, int tcs, 10531 int tx_xdp) 10532 { 10533 int max_rx, max_tx, tx_sets = 1; 10534 int tx_rings_needed, stats; 10535 int rx_rings = rx; 10536 int cp, vnics, rc; 10537 10538 if (tcs) 10539 tx_sets = tcs; 10540 10541 rc = bnxt_get_max_rings(bp, &max_rx, &max_tx, sh); 10542 if (rc) 10543 return rc; 10544 10545 if (max_rx < rx) 10546 return -ENOMEM; 10547 10548 tx_rings_needed = tx * tx_sets + tx_xdp; 10549 if (max_tx < tx_rings_needed) 10550 return -ENOMEM; 10551 10552 vnics = 1; 10553 if ((bp->flags & (BNXT_FLAG_RFS | BNXT_FLAG_CHIP_P5)) == BNXT_FLAG_RFS) 10554 vnics += rx_rings; 10555 10556 if (bp->flags & BNXT_FLAG_AGG_RINGS) 10557 rx_rings <<= 1; 10558 cp = sh ? max_t(int, tx_rings_needed, rx) : tx_rings_needed + rx; 10559 stats = cp; 10560 if (BNXT_NEW_RM(bp)) { 10561 cp += bnxt_get_ulp_msix_num(bp); 10562 stats += bnxt_get_ulp_stat_ctxs(bp); 10563 } 10564 return bnxt_hwrm_check_rings(bp, tx_rings_needed, rx_rings, rx, cp, 10565 stats, vnics); 10566 } 10567 10568 static void bnxt_unmap_bars(struct bnxt *bp, struct pci_dev *pdev) 10569 { 10570 if (bp->bar2) { 10571 pci_iounmap(pdev, bp->bar2); 10572 bp->bar2 = NULL; 10573 } 10574 10575 if (bp->bar1) { 10576 pci_iounmap(pdev, bp->bar1); 10577 bp->bar1 = NULL; 10578 } 10579 10580 if (bp->bar0) { 10581 pci_iounmap(pdev, bp->bar0); 10582 bp->bar0 = NULL; 10583 } 10584 } 10585 10586 static void bnxt_cleanup_pci(struct bnxt *bp) 10587 { 10588 bnxt_unmap_bars(bp, bp->pdev); 10589 pci_release_regions(bp->pdev); 10590 if (pci_is_enabled(bp->pdev)) 10591 pci_disable_device(bp->pdev); 10592 } 10593 10594 static void bnxt_init_dflt_coal(struct bnxt *bp) 10595 { 10596 struct bnxt_coal *coal; 10597 10598 /* Tick values in micro seconds. 10599 * 1 coal_buf x bufs_per_record = 1 completion record. 10600 */ 10601 coal = &bp->rx_coal; 10602 coal->coal_ticks = 10; 10603 coal->coal_bufs = 30; 10604 coal->coal_ticks_irq = 1; 10605 coal->coal_bufs_irq = 2; 10606 coal->idle_thresh = 50; 10607 coal->bufs_per_record = 2; 10608 coal->budget = 64; /* NAPI budget */ 10609 10610 coal = &bp->tx_coal; 10611 coal->coal_ticks = 28; 10612 coal->coal_bufs = 30; 10613 coal->coal_ticks_irq = 2; 10614 coal->coal_bufs_irq = 2; 10615 coal->bufs_per_record = 1; 10616 10617 bp->stats_coal_ticks = BNXT_DEF_STATS_COAL_TICKS; 10618 } 10619 10620 static void bnxt_alloc_fw_health(struct bnxt *bp) 10621 { 10622 if (bp->fw_health) 10623 return; 10624 10625 if (!(bp->fw_cap & BNXT_FW_CAP_HOT_RESET) && 10626 !(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)) 10627 return; 10628 10629 bp->fw_health = kzalloc(sizeof(*bp->fw_health), GFP_KERNEL); 10630 if (!bp->fw_health) { 10631 netdev_warn(bp->dev, "Failed to allocate fw_health\n"); 10632 bp->fw_cap &= ~BNXT_FW_CAP_HOT_RESET; 10633 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY; 10634 } 10635 } 10636 10637 static int bnxt_fw_init_one_p1(struct bnxt *bp) 10638 { 10639 int rc; 10640 10641 bp->fw_cap = 0; 10642 rc = bnxt_hwrm_ver_get(bp); 10643 if (rc) 10644 return rc; 10645 10646 if (bp->fw_cap & BNXT_FW_CAP_KONG_MB_CHNL) { 10647 rc = bnxt_alloc_kong_hwrm_resources(bp); 10648 if (rc) 10649 bp->fw_cap &= ~BNXT_FW_CAP_KONG_MB_CHNL; 10650 } 10651 10652 if ((bp->fw_cap & BNXT_FW_CAP_SHORT_CMD) || 10653 bp->hwrm_max_ext_req_len > BNXT_HWRM_MAX_REQ_LEN) { 10654 rc = bnxt_alloc_hwrm_short_cmd_req(bp); 10655 if (rc) 10656 return rc; 10657 } 10658 rc = bnxt_hwrm_func_reset(bp); 10659 if (rc) 10660 return -ENODEV; 10661 10662 bnxt_hwrm_fw_set_time(bp); 10663 return 0; 10664 } 10665 10666 static int bnxt_fw_init_one_p2(struct bnxt *bp) 10667 { 10668 int rc; 10669 10670 /* Get the MAX capabilities for this function */ 10671 rc = bnxt_hwrm_func_qcaps(bp); 10672 if (rc) { 10673 netdev_err(bp->dev, "hwrm query capability failure rc: %x\n", 10674 rc); 10675 return -ENODEV; 10676 } 10677 10678 rc = bnxt_hwrm_cfa_adv_flow_mgnt_qcaps(bp); 10679 if (rc) 10680 netdev_warn(bp->dev, "hwrm query adv flow mgnt failure rc: %d\n", 10681 rc); 10682 10683 bnxt_alloc_fw_health(bp); 10684 rc = bnxt_hwrm_error_recovery_qcfg(bp); 10685 if (rc) 10686 netdev_warn(bp->dev, "hwrm query error recovery failure rc: %d\n", 10687 rc); 10688 10689 rc = bnxt_hwrm_func_drv_rgtr(bp, NULL, 0, false); 10690 if (rc) 10691 return -ENODEV; 10692 10693 bnxt_hwrm_func_qcfg(bp); 10694 bnxt_hwrm_vnic_qcaps(bp); 10695 bnxt_hwrm_port_led_qcaps(bp); 10696 bnxt_ethtool_init(bp); 10697 bnxt_dcb_init(bp); 10698 return 0; 10699 } 10700 10701 static void bnxt_set_dflt_rss_hash_type(struct bnxt *bp) 10702 { 10703 bp->flags &= ~BNXT_FLAG_UDP_RSS_CAP; 10704 bp->rss_hash_cfg = VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 | 10705 VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 | 10706 VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 | 10707 VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6; 10708 if (BNXT_CHIP_P4_PLUS(bp) && bp->hwrm_spec_code >= 0x10501) { 10709 bp->flags |= BNXT_FLAG_UDP_RSS_CAP; 10710 bp->rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 | 10711 VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6; 10712 } 10713 } 10714 10715 static void bnxt_set_dflt_rfs(struct bnxt *bp) 10716 { 10717 struct net_device *dev = bp->dev; 10718 10719 dev->hw_features &= ~NETIF_F_NTUPLE; 10720 dev->features &= ~NETIF_F_NTUPLE; 10721 bp->flags &= ~BNXT_FLAG_RFS; 10722 if (bnxt_rfs_supported(bp)) { 10723 dev->hw_features |= NETIF_F_NTUPLE; 10724 if (bnxt_rfs_capable(bp)) { 10725 bp->flags |= BNXT_FLAG_RFS; 10726 dev->features |= NETIF_F_NTUPLE; 10727 } 10728 } 10729 } 10730 10731 static void bnxt_fw_init_one_p3(struct bnxt *bp) 10732 { 10733 struct pci_dev *pdev = bp->pdev; 10734 10735 bnxt_set_dflt_rss_hash_type(bp); 10736 bnxt_set_dflt_rfs(bp); 10737 10738 bnxt_get_wol_settings(bp); 10739 if (bp->flags & BNXT_FLAG_WOL_CAP) 10740 device_set_wakeup_enable(&pdev->dev, bp->wol); 10741 else 10742 device_set_wakeup_capable(&pdev->dev, false); 10743 10744 bnxt_hwrm_set_cache_line_size(bp, cache_line_size()); 10745 bnxt_hwrm_coal_params_qcaps(bp); 10746 } 10747 10748 static int bnxt_fw_init_one(struct bnxt *bp) 10749 { 10750 int rc; 10751 10752 rc = bnxt_fw_init_one_p1(bp); 10753 if (rc) { 10754 netdev_err(bp->dev, "Firmware init phase 1 failed\n"); 10755 return rc; 10756 } 10757 rc = bnxt_fw_init_one_p2(bp); 10758 if (rc) { 10759 netdev_err(bp->dev, "Firmware init phase 2 failed\n"); 10760 return rc; 10761 } 10762 rc = bnxt_approve_mac(bp, bp->dev->dev_addr, false); 10763 if (rc) 10764 return rc; 10765 10766 /* In case fw capabilities have changed, destroy the unneeded 10767 * reporters and create newly capable ones. 10768 */ 10769 bnxt_dl_fw_reporters_destroy(bp, false); 10770 bnxt_dl_fw_reporters_create(bp); 10771 bnxt_fw_init_one_p3(bp); 10772 return 0; 10773 } 10774 10775 static void bnxt_fw_reset_writel(struct bnxt *bp, int reg_idx) 10776 { 10777 struct bnxt_fw_health *fw_health = bp->fw_health; 10778 u32 reg = fw_health->fw_reset_seq_regs[reg_idx]; 10779 u32 val = fw_health->fw_reset_seq_vals[reg_idx]; 10780 u32 reg_type, reg_off, delay_msecs; 10781 10782 delay_msecs = fw_health->fw_reset_seq_delay_msec[reg_idx]; 10783 reg_type = BNXT_FW_HEALTH_REG_TYPE(reg); 10784 reg_off = BNXT_FW_HEALTH_REG_OFF(reg); 10785 switch (reg_type) { 10786 case BNXT_FW_HEALTH_REG_TYPE_CFG: 10787 pci_write_config_dword(bp->pdev, reg_off, val); 10788 break; 10789 case BNXT_FW_HEALTH_REG_TYPE_GRC: 10790 writel(reg_off & BNXT_GRC_BASE_MASK, 10791 bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4); 10792 reg_off = (reg_off & BNXT_GRC_OFFSET_MASK) + 0x2000; 10793 /* fall through */ 10794 case BNXT_FW_HEALTH_REG_TYPE_BAR0: 10795 writel(val, bp->bar0 + reg_off); 10796 break; 10797 case BNXT_FW_HEALTH_REG_TYPE_BAR1: 10798 writel(val, bp->bar1 + reg_off); 10799 break; 10800 } 10801 if (delay_msecs) { 10802 pci_read_config_dword(bp->pdev, 0, &val); 10803 msleep(delay_msecs); 10804 } 10805 } 10806 10807 static void bnxt_reset_all(struct bnxt *bp) 10808 { 10809 struct bnxt_fw_health *fw_health = bp->fw_health; 10810 int i, rc; 10811 10812 if (bp->fw_cap & BNXT_FW_CAP_ERR_RECOVER_RELOAD) { 10813 #ifdef CONFIG_TEE_BNXT_FW 10814 rc = tee_bnxt_fw_load(); 10815 if (rc) 10816 netdev_err(bp->dev, "Unable to reset FW rc=%d\n", rc); 10817 bp->fw_reset_timestamp = jiffies; 10818 #endif 10819 return; 10820 } 10821 10822 if (fw_health->flags & ERROR_RECOVERY_QCFG_RESP_FLAGS_HOST) { 10823 for (i = 0; i < fw_health->fw_reset_seq_cnt; i++) 10824 bnxt_fw_reset_writel(bp, i); 10825 } else if (fw_health->flags & ERROR_RECOVERY_QCFG_RESP_FLAGS_CO_CPU) { 10826 struct hwrm_fw_reset_input req = {0}; 10827 10828 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FW_RESET, -1, -1); 10829 req.resp_addr = cpu_to_le64(bp->hwrm_cmd_kong_resp_dma_addr); 10830 req.embedded_proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP; 10831 req.selfrst_status = FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP; 10832 req.flags = FW_RESET_REQ_FLAGS_RESET_GRACEFUL; 10833 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 10834 if (rc) 10835 netdev_warn(bp->dev, "Unable to reset FW rc=%d\n", rc); 10836 } 10837 bp->fw_reset_timestamp = jiffies; 10838 } 10839 10840 static void bnxt_fw_reset_task(struct work_struct *work) 10841 { 10842 struct bnxt *bp = container_of(work, struct bnxt, fw_reset_task.work); 10843 int rc; 10844 10845 if (!test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) { 10846 netdev_err(bp->dev, "bnxt_fw_reset_task() called when not in fw reset mode!\n"); 10847 return; 10848 } 10849 10850 switch (bp->fw_reset_state) { 10851 case BNXT_FW_RESET_STATE_POLL_VF: { 10852 int n = bnxt_get_registered_vfs(bp); 10853 int tmo; 10854 10855 if (n < 0) { 10856 netdev_err(bp->dev, "Firmware reset aborted, subsequent func_qcfg cmd failed, rc = %d, %d msecs since reset timestamp\n", 10857 n, jiffies_to_msecs(jiffies - 10858 bp->fw_reset_timestamp)); 10859 goto fw_reset_abort; 10860 } else if (n > 0) { 10861 if (time_after(jiffies, bp->fw_reset_timestamp + 10862 (bp->fw_reset_max_dsecs * HZ / 10))) { 10863 clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state); 10864 bp->fw_reset_state = 0; 10865 netdev_err(bp->dev, "Firmware reset aborted, bnxt_get_registered_vfs() returns %d\n", 10866 n); 10867 return; 10868 } 10869 bnxt_queue_fw_reset_work(bp, HZ / 10); 10870 return; 10871 } 10872 bp->fw_reset_timestamp = jiffies; 10873 rtnl_lock(); 10874 bnxt_fw_reset_close(bp); 10875 if (bp->fw_cap & BNXT_FW_CAP_ERR_RECOVER_RELOAD) { 10876 bp->fw_reset_state = BNXT_FW_RESET_STATE_POLL_FW_DOWN; 10877 tmo = HZ / 10; 10878 } else { 10879 bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV; 10880 tmo = bp->fw_reset_min_dsecs * HZ / 10; 10881 } 10882 rtnl_unlock(); 10883 bnxt_queue_fw_reset_work(bp, tmo); 10884 return; 10885 } 10886 case BNXT_FW_RESET_STATE_POLL_FW_DOWN: { 10887 u32 val; 10888 10889 val = bnxt_fw_health_readl(bp, BNXT_FW_HEALTH_REG); 10890 if (!(val & BNXT_FW_STATUS_SHUTDOWN) && 10891 !time_after(jiffies, bp->fw_reset_timestamp + 10892 (bp->fw_reset_max_dsecs * HZ / 10))) { 10893 bnxt_queue_fw_reset_work(bp, HZ / 5); 10894 return; 10895 } 10896 10897 if (!bp->fw_health->master) { 10898 u32 wait_dsecs = bp->fw_health->normal_func_wait_dsecs; 10899 10900 bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV; 10901 bnxt_queue_fw_reset_work(bp, wait_dsecs * HZ / 10); 10902 return; 10903 } 10904 bp->fw_reset_state = BNXT_FW_RESET_STATE_RESET_FW; 10905 } 10906 /* fall through */ 10907 case BNXT_FW_RESET_STATE_RESET_FW: 10908 bnxt_reset_all(bp); 10909 bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV; 10910 bnxt_queue_fw_reset_work(bp, bp->fw_reset_min_dsecs * HZ / 10); 10911 return; 10912 case BNXT_FW_RESET_STATE_ENABLE_DEV: 10913 if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state)) { 10914 u32 val; 10915 10916 val = bnxt_fw_health_readl(bp, 10917 BNXT_FW_RESET_INPROG_REG); 10918 if (val) 10919 netdev_warn(bp->dev, "FW reset inprog %x after min wait time.\n", 10920 val); 10921 } 10922 clear_bit(BNXT_STATE_FW_FATAL_COND, &bp->state); 10923 if (pci_enable_device(bp->pdev)) { 10924 netdev_err(bp->dev, "Cannot re-enable PCI device\n"); 10925 goto fw_reset_abort; 10926 } 10927 pci_set_master(bp->pdev); 10928 bp->fw_reset_state = BNXT_FW_RESET_STATE_POLL_FW; 10929 /* fall through */ 10930 case BNXT_FW_RESET_STATE_POLL_FW: 10931 bp->hwrm_cmd_timeout = SHORT_HWRM_CMD_TIMEOUT; 10932 rc = __bnxt_hwrm_ver_get(bp, true); 10933 if (rc) { 10934 if (time_after(jiffies, bp->fw_reset_timestamp + 10935 (bp->fw_reset_max_dsecs * HZ / 10))) { 10936 netdev_err(bp->dev, "Firmware reset aborted\n"); 10937 goto fw_reset_abort; 10938 } 10939 bnxt_queue_fw_reset_work(bp, HZ / 5); 10940 return; 10941 } 10942 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT; 10943 bp->fw_reset_state = BNXT_FW_RESET_STATE_OPENING; 10944 /* fall through */ 10945 case BNXT_FW_RESET_STATE_OPENING: 10946 while (!rtnl_trylock()) { 10947 bnxt_queue_fw_reset_work(bp, HZ / 10); 10948 return; 10949 } 10950 rc = bnxt_open(bp->dev); 10951 if (rc) { 10952 netdev_err(bp->dev, "bnxt_open_nic() failed\n"); 10953 clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state); 10954 dev_close(bp->dev); 10955 } 10956 10957 bp->fw_reset_state = 0; 10958 /* Make sure fw_reset_state is 0 before clearing the flag */ 10959 smp_mb__before_atomic(); 10960 clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state); 10961 bnxt_ulp_start(bp, rc); 10962 if (!rc) 10963 bnxt_reenable_sriov(bp); 10964 bnxt_dl_health_recovery_done(bp); 10965 bnxt_dl_health_status_update(bp, true); 10966 rtnl_unlock(); 10967 break; 10968 } 10969 return; 10970 10971 fw_reset_abort: 10972 clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state); 10973 if (bp->fw_reset_state != BNXT_FW_RESET_STATE_POLL_VF) 10974 bnxt_dl_health_status_update(bp, false); 10975 bp->fw_reset_state = 0; 10976 rtnl_lock(); 10977 dev_close(bp->dev); 10978 rtnl_unlock(); 10979 } 10980 10981 static int bnxt_init_board(struct pci_dev *pdev, struct net_device *dev) 10982 { 10983 int rc; 10984 struct bnxt *bp = netdev_priv(dev); 10985 10986 SET_NETDEV_DEV(dev, &pdev->dev); 10987 10988 /* enable device (incl. PCI PM wakeup), and bus-mastering */ 10989 rc = pci_enable_device(pdev); 10990 if (rc) { 10991 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n"); 10992 goto init_err; 10993 } 10994 10995 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 10996 dev_err(&pdev->dev, 10997 "Cannot find PCI device base address, aborting\n"); 10998 rc = -ENODEV; 10999 goto init_err_disable; 11000 } 11001 11002 rc = pci_request_regions(pdev, DRV_MODULE_NAME); 11003 if (rc) { 11004 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n"); 11005 goto init_err_disable; 11006 } 11007 11008 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) != 0 && 11009 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)) != 0) { 11010 dev_err(&pdev->dev, "System does not support DMA, aborting\n"); 11011 goto init_err_disable; 11012 } 11013 11014 pci_set_master(pdev); 11015 11016 bp->dev = dev; 11017 bp->pdev = pdev; 11018 11019 /* Doorbell BAR bp->bar1 is mapped after bnxt_fw_init_one_p2() 11020 * determines the BAR size. 11021 */ 11022 bp->bar0 = pci_ioremap_bar(pdev, 0); 11023 if (!bp->bar0) { 11024 dev_err(&pdev->dev, "Cannot map device registers, aborting\n"); 11025 rc = -ENOMEM; 11026 goto init_err_release; 11027 } 11028 11029 bp->bar2 = pci_ioremap_bar(pdev, 4); 11030 if (!bp->bar2) { 11031 dev_err(&pdev->dev, "Cannot map bar4 registers, aborting\n"); 11032 rc = -ENOMEM; 11033 goto init_err_release; 11034 } 11035 11036 pci_enable_pcie_error_reporting(pdev); 11037 11038 INIT_WORK(&bp->sp_task, bnxt_sp_task); 11039 INIT_DELAYED_WORK(&bp->fw_reset_task, bnxt_fw_reset_task); 11040 11041 spin_lock_init(&bp->ntp_fltr_lock); 11042 #if BITS_PER_LONG == 32 11043 spin_lock_init(&bp->db_lock); 11044 #endif 11045 11046 bp->rx_ring_size = BNXT_DEFAULT_RX_RING_SIZE; 11047 bp->tx_ring_size = BNXT_DEFAULT_TX_RING_SIZE; 11048 11049 bnxt_init_dflt_coal(bp); 11050 11051 timer_setup(&bp->timer, bnxt_timer, 0); 11052 bp->current_interval = BNXT_TIMER_INTERVAL; 11053 11054 bp->vxlan_fw_dst_port_id = INVALID_HW_RING_ID; 11055 bp->nge_fw_dst_port_id = INVALID_HW_RING_ID; 11056 11057 clear_bit(BNXT_STATE_OPEN, &bp->state); 11058 return 0; 11059 11060 init_err_release: 11061 bnxt_unmap_bars(bp, pdev); 11062 pci_release_regions(pdev); 11063 11064 init_err_disable: 11065 pci_disable_device(pdev); 11066 11067 init_err: 11068 return rc; 11069 } 11070 11071 /* rtnl_lock held */ 11072 static int bnxt_change_mac_addr(struct net_device *dev, void *p) 11073 { 11074 struct sockaddr *addr = p; 11075 struct bnxt *bp = netdev_priv(dev); 11076 int rc = 0; 11077 11078 if (!is_valid_ether_addr(addr->sa_data)) 11079 return -EADDRNOTAVAIL; 11080 11081 if (ether_addr_equal(addr->sa_data, dev->dev_addr)) 11082 return 0; 11083 11084 rc = bnxt_approve_mac(bp, addr->sa_data, true); 11085 if (rc) 11086 return rc; 11087 11088 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); 11089 if (netif_running(dev)) { 11090 bnxt_close_nic(bp, false, false); 11091 rc = bnxt_open_nic(bp, false, false); 11092 } 11093 11094 return rc; 11095 } 11096 11097 /* rtnl_lock held */ 11098 static int bnxt_change_mtu(struct net_device *dev, int new_mtu) 11099 { 11100 struct bnxt *bp = netdev_priv(dev); 11101 11102 if (netif_running(dev)) 11103 bnxt_close_nic(bp, true, false); 11104 11105 dev->mtu = new_mtu; 11106 bnxt_set_ring_params(bp); 11107 11108 if (netif_running(dev)) 11109 return bnxt_open_nic(bp, true, false); 11110 11111 return 0; 11112 } 11113 11114 int bnxt_setup_mq_tc(struct net_device *dev, u8 tc) 11115 { 11116 struct bnxt *bp = netdev_priv(dev); 11117 bool sh = false; 11118 int rc; 11119 11120 if (tc > bp->max_tc) { 11121 netdev_err(dev, "Too many traffic classes requested: %d. Max supported is %d.\n", 11122 tc, bp->max_tc); 11123 return -EINVAL; 11124 } 11125 11126 if (netdev_get_num_tc(dev) == tc) 11127 return 0; 11128 11129 if (bp->flags & BNXT_FLAG_SHARED_RINGS) 11130 sh = true; 11131 11132 rc = bnxt_check_rings(bp, bp->tx_nr_rings_per_tc, bp->rx_nr_rings, 11133 sh, tc, bp->tx_nr_rings_xdp); 11134 if (rc) 11135 return rc; 11136 11137 /* Needs to close the device and do hw resource re-allocations */ 11138 if (netif_running(bp->dev)) 11139 bnxt_close_nic(bp, true, false); 11140 11141 if (tc) { 11142 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tc; 11143 netdev_set_num_tc(dev, tc); 11144 } else { 11145 bp->tx_nr_rings = bp->tx_nr_rings_per_tc; 11146 netdev_reset_tc(dev); 11147 } 11148 bp->tx_nr_rings += bp->tx_nr_rings_xdp; 11149 bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) : 11150 bp->tx_nr_rings + bp->rx_nr_rings; 11151 11152 if (netif_running(bp->dev)) 11153 return bnxt_open_nic(bp, true, false); 11154 11155 return 0; 11156 } 11157 11158 static int bnxt_setup_tc_block_cb(enum tc_setup_type type, void *type_data, 11159 void *cb_priv) 11160 { 11161 struct bnxt *bp = cb_priv; 11162 11163 if (!bnxt_tc_flower_enabled(bp) || 11164 !tc_cls_can_offload_and_chain0(bp->dev, type_data)) 11165 return -EOPNOTSUPP; 11166 11167 switch (type) { 11168 case TC_SETUP_CLSFLOWER: 11169 return bnxt_tc_setup_flower(bp, bp->pf.fw_fid, type_data); 11170 default: 11171 return -EOPNOTSUPP; 11172 } 11173 } 11174 11175 LIST_HEAD(bnxt_block_cb_list); 11176 11177 static int bnxt_setup_tc(struct net_device *dev, enum tc_setup_type type, 11178 void *type_data) 11179 { 11180 struct bnxt *bp = netdev_priv(dev); 11181 11182 switch (type) { 11183 case TC_SETUP_BLOCK: 11184 return flow_block_cb_setup_simple(type_data, 11185 &bnxt_block_cb_list, 11186 bnxt_setup_tc_block_cb, 11187 bp, bp, true); 11188 case TC_SETUP_QDISC_MQPRIO: { 11189 struct tc_mqprio_qopt *mqprio = type_data; 11190 11191 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS; 11192 11193 return bnxt_setup_mq_tc(dev, mqprio->num_tc); 11194 } 11195 default: 11196 return -EOPNOTSUPP; 11197 } 11198 } 11199 11200 #ifdef CONFIG_RFS_ACCEL 11201 static bool bnxt_fltr_match(struct bnxt_ntuple_filter *f1, 11202 struct bnxt_ntuple_filter *f2) 11203 { 11204 struct flow_keys *keys1 = &f1->fkeys; 11205 struct flow_keys *keys2 = &f2->fkeys; 11206 11207 if (keys1->basic.n_proto != keys2->basic.n_proto || 11208 keys1->basic.ip_proto != keys2->basic.ip_proto) 11209 return false; 11210 11211 if (keys1->basic.n_proto == htons(ETH_P_IP)) { 11212 if (keys1->addrs.v4addrs.src != keys2->addrs.v4addrs.src || 11213 keys1->addrs.v4addrs.dst != keys2->addrs.v4addrs.dst) 11214 return false; 11215 } else { 11216 if (memcmp(&keys1->addrs.v6addrs.src, &keys2->addrs.v6addrs.src, 11217 sizeof(keys1->addrs.v6addrs.src)) || 11218 memcmp(&keys1->addrs.v6addrs.dst, &keys2->addrs.v6addrs.dst, 11219 sizeof(keys1->addrs.v6addrs.dst))) 11220 return false; 11221 } 11222 11223 if (keys1->ports.ports == keys2->ports.ports && 11224 keys1->control.flags == keys2->control.flags && 11225 ether_addr_equal(f1->src_mac_addr, f2->src_mac_addr) && 11226 ether_addr_equal(f1->dst_mac_addr, f2->dst_mac_addr)) 11227 return true; 11228 11229 return false; 11230 } 11231 11232 static int bnxt_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb, 11233 u16 rxq_index, u32 flow_id) 11234 { 11235 struct bnxt *bp = netdev_priv(dev); 11236 struct bnxt_ntuple_filter *fltr, *new_fltr; 11237 struct flow_keys *fkeys; 11238 struct ethhdr *eth = (struct ethhdr *)skb_mac_header(skb); 11239 int rc = 0, idx, bit_id, l2_idx = 0; 11240 struct hlist_head *head; 11241 u32 flags; 11242 11243 if (!ether_addr_equal(dev->dev_addr, eth->h_dest)) { 11244 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 11245 int off = 0, j; 11246 11247 netif_addr_lock_bh(dev); 11248 for (j = 0; j < vnic->uc_filter_count; j++, off += ETH_ALEN) { 11249 if (ether_addr_equal(eth->h_dest, 11250 vnic->uc_list + off)) { 11251 l2_idx = j + 1; 11252 break; 11253 } 11254 } 11255 netif_addr_unlock_bh(dev); 11256 if (!l2_idx) 11257 return -EINVAL; 11258 } 11259 new_fltr = kzalloc(sizeof(*new_fltr), GFP_ATOMIC); 11260 if (!new_fltr) 11261 return -ENOMEM; 11262 11263 fkeys = &new_fltr->fkeys; 11264 if (!skb_flow_dissect_flow_keys(skb, fkeys, 0)) { 11265 rc = -EPROTONOSUPPORT; 11266 goto err_free; 11267 } 11268 11269 if ((fkeys->basic.n_proto != htons(ETH_P_IP) && 11270 fkeys->basic.n_proto != htons(ETH_P_IPV6)) || 11271 ((fkeys->basic.ip_proto != IPPROTO_TCP) && 11272 (fkeys->basic.ip_proto != IPPROTO_UDP))) { 11273 rc = -EPROTONOSUPPORT; 11274 goto err_free; 11275 } 11276 if (fkeys->basic.n_proto == htons(ETH_P_IPV6) && 11277 bp->hwrm_spec_code < 0x10601) { 11278 rc = -EPROTONOSUPPORT; 11279 goto err_free; 11280 } 11281 flags = fkeys->control.flags; 11282 if (((flags & FLOW_DIS_ENCAPSULATION) && 11283 bp->hwrm_spec_code < 0x10601) || (flags & FLOW_DIS_IS_FRAGMENT)) { 11284 rc = -EPROTONOSUPPORT; 11285 goto err_free; 11286 } 11287 11288 memcpy(new_fltr->dst_mac_addr, eth->h_dest, ETH_ALEN); 11289 memcpy(new_fltr->src_mac_addr, eth->h_source, ETH_ALEN); 11290 11291 idx = skb_get_hash_raw(skb) & BNXT_NTP_FLTR_HASH_MASK; 11292 head = &bp->ntp_fltr_hash_tbl[idx]; 11293 rcu_read_lock(); 11294 hlist_for_each_entry_rcu(fltr, head, hash) { 11295 if (bnxt_fltr_match(fltr, new_fltr)) { 11296 rcu_read_unlock(); 11297 rc = 0; 11298 goto err_free; 11299 } 11300 } 11301 rcu_read_unlock(); 11302 11303 spin_lock_bh(&bp->ntp_fltr_lock); 11304 bit_id = bitmap_find_free_region(bp->ntp_fltr_bmap, 11305 BNXT_NTP_FLTR_MAX_FLTR, 0); 11306 if (bit_id < 0) { 11307 spin_unlock_bh(&bp->ntp_fltr_lock); 11308 rc = -ENOMEM; 11309 goto err_free; 11310 } 11311 11312 new_fltr->sw_id = (u16)bit_id; 11313 new_fltr->flow_id = flow_id; 11314 new_fltr->l2_fltr_idx = l2_idx; 11315 new_fltr->rxq = rxq_index; 11316 hlist_add_head_rcu(&new_fltr->hash, head); 11317 bp->ntp_fltr_count++; 11318 spin_unlock_bh(&bp->ntp_fltr_lock); 11319 11320 set_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event); 11321 bnxt_queue_sp_work(bp); 11322 11323 return new_fltr->sw_id; 11324 11325 err_free: 11326 kfree(new_fltr); 11327 return rc; 11328 } 11329 11330 static void bnxt_cfg_ntp_filters(struct bnxt *bp) 11331 { 11332 int i; 11333 11334 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) { 11335 struct hlist_head *head; 11336 struct hlist_node *tmp; 11337 struct bnxt_ntuple_filter *fltr; 11338 int rc; 11339 11340 head = &bp->ntp_fltr_hash_tbl[i]; 11341 hlist_for_each_entry_safe(fltr, tmp, head, hash) { 11342 bool del = false; 11343 11344 if (test_bit(BNXT_FLTR_VALID, &fltr->state)) { 11345 if (rps_may_expire_flow(bp->dev, fltr->rxq, 11346 fltr->flow_id, 11347 fltr->sw_id)) { 11348 bnxt_hwrm_cfa_ntuple_filter_free(bp, 11349 fltr); 11350 del = true; 11351 } 11352 } else { 11353 rc = bnxt_hwrm_cfa_ntuple_filter_alloc(bp, 11354 fltr); 11355 if (rc) 11356 del = true; 11357 else 11358 set_bit(BNXT_FLTR_VALID, &fltr->state); 11359 } 11360 11361 if (del) { 11362 spin_lock_bh(&bp->ntp_fltr_lock); 11363 hlist_del_rcu(&fltr->hash); 11364 bp->ntp_fltr_count--; 11365 spin_unlock_bh(&bp->ntp_fltr_lock); 11366 synchronize_rcu(); 11367 clear_bit(fltr->sw_id, bp->ntp_fltr_bmap); 11368 kfree(fltr); 11369 } 11370 } 11371 } 11372 if (test_and_clear_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event)) 11373 netdev_info(bp->dev, "Receive PF driver unload event!\n"); 11374 } 11375 11376 #else 11377 11378 static void bnxt_cfg_ntp_filters(struct bnxt *bp) 11379 { 11380 } 11381 11382 #endif /* CONFIG_RFS_ACCEL */ 11383 11384 static int bnxt_udp_tunnel_sync(struct net_device *netdev, unsigned int table) 11385 { 11386 struct bnxt *bp = netdev_priv(netdev); 11387 struct udp_tunnel_info ti; 11388 unsigned int cmd; 11389 11390 udp_tunnel_nic_get_port(netdev, table, 0, &ti); 11391 if (ti.type == UDP_TUNNEL_TYPE_VXLAN) 11392 cmd = TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN; 11393 else 11394 cmd = TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE; 11395 11396 if (ti.port) 11397 return bnxt_hwrm_tunnel_dst_port_alloc(bp, ti.port, cmd); 11398 11399 return bnxt_hwrm_tunnel_dst_port_free(bp, cmd); 11400 } 11401 11402 static const struct udp_tunnel_nic_info bnxt_udp_tunnels = { 11403 .sync_table = bnxt_udp_tunnel_sync, 11404 .flags = UDP_TUNNEL_NIC_INFO_MAY_SLEEP | 11405 UDP_TUNNEL_NIC_INFO_OPEN_ONLY, 11406 .tables = { 11407 { .n_entries = 1, .tunnel_types = UDP_TUNNEL_TYPE_VXLAN, }, 11408 { .n_entries = 1, .tunnel_types = UDP_TUNNEL_TYPE_GENEVE, }, 11409 }, 11410 }; 11411 11412 static int bnxt_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq, 11413 struct net_device *dev, u32 filter_mask, 11414 int nlflags) 11415 { 11416 struct bnxt *bp = netdev_priv(dev); 11417 11418 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, bp->br_mode, 0, 0, 11419 nlflags, filter_mask, NULL); 11420 } 11421 11422 static int bnxt_bridge_setlink(struct net_device *dev, struct nlmsghdr *nlh, 11423 u16 flags, struct netlink_ext_ack *extack) 11424 { 11425 struct bnxt *bp = netdev_priv(dev); 11426 struct nlattr *attr, *br_spec; 11427 int rem, rc = 0; 11428 11429 if (bp->hwrm_spec_code < 0x10708 || !BNXT_SINGLE_PF(bp)) 11430 return -EOPNOTSUPP; 11431 11432 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC); 11433 if (!br_spec) 11434 return -EINVAL; 11435 11436 nla_for_each_nested(attr, br_spec, rem) { 11437 u16 mode; 11438 11439 if (nla_type(attr) != IFLA_BRIDGE_MODE) 11440 continue; 11441 11442 if (nla_len(attr) < sizeof(mode)) 11443 return -EINVAL; 11444 11445 mode = nla_get_u16(attr); 11446 if (mode == bp->br_mode) 11447 break; 11448 11449 rc = bnxt_hwrm_set_br_mode(bp, mode); 11450 if (!rc) 11451 bp->br_mode = mode; 11452 break; 11453 } 11454 return rc; 11455 } 11456 11457 int bnxt_get_port_parent_id(struct net_device *dev, 11458 struct netdev_phys_item_id *ppid) 11459 { 11460 struct bnxt *bp = netdev_priv(dev); 11461 11462 if (bp->eswitch_mode != DEVLINK_ESWITCH_MODE_SWITCHDEV) 11463 return -EOPNOTSUPP; 11464 11465 /* The PF and it's VF-reps only support the switchdev framework */ 11466 if (!BNXT_PF(bp) || !(bp->flags & BNXT_FLAG_DSN_VALID)) 11467 return -EOPNOTSUPP; 11468 11469 ppid->id_len = sizeof(bp->dsn); 11470 memcpy(ppid->id, bp->dsn, ppid->id_len); 11471 11472 return 0; 11473 } 11474 11475 static struct devlink_port *bnxt_get_devlink_port(struct net_device *dev) 11476 { 11477 struct bnxt *bp = netdev_priv(dev); 11478 11479 return &bp->dl_port; 11480 } 11481 11482 static const struct net_device_ops bnxt_netdev_ops = { 11483 .ndo_open = bnxt_open, 11484 .ndo_start_xmit = bnxt_start_xmit, 11485 .ndo_stop = bnxt_close, 11486 .ndo_get_stats64 = bnxt_get_stats64, 11487 .ndo_set_rx_mode = bnxt_set_rx_mode, 11488 .ndo_do_ioctl = bnxt_ioctl, 11489 .ndo_validate_addr = eth_validate_addr, 11490 .ndo_set_mac_address = bnxt_change_mac_addr, 11491 .ndo_change_mtu = bnxt_change_mtu, 11492 .ndo_fix_features = bnxt_fix_features, 11493 .ndo_set_features = bnxt_set_features, 11494 .ndo_tx_timeout = bnxt_tx_timeout, 11495 #ifdef CONFIG_BNXT_SRIOV 11496 .ndo_get_vf_config = bnxt_get_vf_config, 11497 .ndo_set_vf_mac = bnxt_set_vf_mac, 11498 .ndo_set_vf_vlan = bnxt_set_vf_vlan, 11499 .ndo_set_vf_rate = bnxt_set_vf_bw, 11500 .ndo_set_vf_link_state = bnxt_set_vf_link_state, 11501 .ndo_set_vf_spoofchk = bnxt_set_vf_spoofchk, 11502 .ndo_set_vf_trust = bnxt_set_vf_trust, 11503 #endif 11504 .ndo_setup_tc = bnxt_setup_tc, 11505 #ifdef CONFIG_RFS_ACCEL 11506 .ndo_rx_flow_steer = bnxt_rx_flow_steer, 11507 #endif 11508 .ndo_udp_tunnel_add = udp_tunnel_nic_add_port, 11509 .ndo_udp_tunnel_del = udp_tunnel_nic_del_port, 11510 .ndo_bpf = bnxt_xdp, 11511 .ndo_xdp_xmit = bnxt_xdp_xmit, 11512 .ndo_bridge_getlink = bnxt_bridge_getlink, 11513 .ndo_bridge_setlink = bnxt_bridge_setlink, 11514 .ndo_get_devlink_port = bnxt_get_devlink_port, 11515 }; 11516 11517 static void bnxt_remove_one(struct pci_dev *pdev) 11518 { 11519 struct net_device *dev = pci_get_drvdata(pdev); 11520 struct bnxt *bp = netdev_priv(dev); 11521 11522 if (BNXT_PF(bp)) 11523 bnxt_sriov_disable(bp); 11524 11525 bnxt_dl_fw_reporters_destroy(bp, true); 11526 if (BNXT_PF(bp)) 11527 devlink_port_type_clear(&bp->dl_port); 11528 pci_disable_pcie_error_reporting(pdev); 11529 unregister_netdev(dev); 11530 bnxt_dl_unregister(bp); 11531 bnxt_shutdown_tc(bp); 11532 bnxt_cancel_sp_work(bp); 11533 bp->sp_event = 0; 11534 11535 bnxt_clear_int_mode(bp); 11536 bnxt_hwrm_func_drv_unrgtr(bp); 11537 bnxt_free_hwrm_resources(bp); 11538 bnxt_free_hwrm_short_cmd_req(bp); 11539 bnxt_ethtool_free(bp); 11540 bnxt_dcb_free(bp); 11541 kfree(bp->edev); 11542 bp->edev = NULL; 11543 kfree(bp->fw_health); 11544 bp->fw_health = NULL; 11545 bnxt_cleanup_pci(bp); 11546 bnxt_free_ctx_mem(bp); 11547 kfree(bp->ctx); 11548 bp->ctx = NULL; 11549 kfree(bp->rss_indir_tbl); 11550 bp->rss_indir_tbl = NULL; 11551 bnxt_free_port_stats(bp); 11552 free_netdev(dev); 11553 } 11554 11555 static int bnxt_probe_phy(struct bnxt *bp, bool fw_dflt) 11556 { 11557 int rc = 0; 11558 struct bnxt_link_info *link_info = &bp->link_info; 11559 11560 rc = bnxt_hwrm_phy_qcaps(bp); 11561 if (rc) { 11562 netdev_err(bp->dev, "Probe phy can't get phy capabilities (rc: %x)\n", 11563 rc); 11564 return rc; 11565 } 11566 if (!fw_dflt) 11567 return 0; 11568 11569 rc = bnxt_update_link(bp, false); 11570 if (rc) { 11571 netdev_err(bp->dev, "Probe phy can't update link (rc: %x)\n", 11572 rc); 11573 return rc; 11574 } 11575 11576 /* Older firmware does not have supported_auto_speeds, so assume 11577 * that all supported speeds can be autonegotiated. 11578 */ 11579 if (link_info->auto_link_speeds && !link_info->support_auto_speeds) 11580 link_info->support_auto_speeds = link_info->support_speeds; 11581 11582 bnxt_init_ethtool_link_settings(bp); 11583 return 0; 11584 } 11585 11586 static int bnxt_get_max_irq(struct pci_dev *pdev) 11587 { 11588 u16 ctrl; 11589 11590 if (!pdev->msix_cap) 11591 return 1; 11592 11593 pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &ctrl); 11594 return (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1; 11595 } 11596 11597 static void _bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx, 11598 int *max_cp) 11599 { 11600 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 11601 int max_ring_grps = 0, max_irq; 11602 11603 *max_tx = hw_resc->max_tx_rings; 11604 *max_rx = hw_resc->max_rx_rings; 11605 *max_cp = bnxt_get_max_func_cp_rings_for_en(bp); 11606 max_irq = min_t(int, bnxt_get_max_func_irqs(bp) - 11607 bnxt_get_ulp_msix_num(bp), 11608 hw_resc->max_stat_ctxs - bnxt_get_ulp_stat_ctxs(bp)); 11609 if (!(bp->flags & BNXT_FLAG_CHIP_P5)) 11610 *max_cp = min_t(int, *max_cp, max_irq); 11611 max_ring_grps = hw_resc->max_hw_ring_grps; 11612 if (BNXT_CHIP_TYPE_NITRO_A0(bp) && BNXT_PF(bp)) { 11613 *max_cp -= 1; 11614 *max_rx -= 2; 11615 } 11616 if (bp->flags & BNXT_FLAG_AGG_RINGS) 11617 *max_rx >>= 1; 11618 if (bp->flags & BNXT_FLAG_CHIP_P5) { 11619 bnxt_trim_rings(bp, max_rx, max_tx, *max_cp, false); 11620 /* On P5 chips, max_cp output param should be available NQs */ 11621 *max_cp = max_irq; 11622 } 11623 *max_rx = min_t(int, *max_rx, max_ring_grps); 11624 } 11625 11626 int bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx, bool shared) 11627 { 11628 int rx, tx, cp; 11629 11630 _bnxt_get_max_rings(bp, &rx, &tx, &cp); 11631 *max_rx = rx; 11632 *max_tx = tx; 11633 if (!rx || !tx || !cp) 11634 return -ENOMEM; 11635 11636 return bnxt_trim_rings(bp, max_rx, max_tx, cp, shared); 11637 } 11638 11639 static int bnxt_get_dflt_rings(struct bnxt *bp, int *max_rx, int *max_tx, 11640 bool shared) 11641 { 11642 int rc; 11643 11644 rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared); 11645 if (rc && (bp->flags & BNXT_FLAG_AGG_RINGS)) { 11646 /* Not enough rings, try disabling agg rings. */ 11647 bp->flags &= ~BNXT_FLAG_AGG_RINGS; 11648 rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared); 11649 if (rc) { 11650 /* set BNXT_FLAG_AGG_RINGS back for consistency */ 11651 bp->flags |= BNXT_FLAG_AGG_RINGS; 11652 return rc; 11653 } 11654 bp->flags |= BNXT_FLAG_NO_AGG_RINGS; 11655 bp->dev->hw_features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW); 11656 bp->dev->features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW); 11657 bnxt_set_ring_params(bp); 11658 } 11659 11660 if (bp->flags & BNXT_FLAG_ROCE_CAP) { 11661 int max_cp, max_stat, max_irq; 11662 11663 /* Reserve minimum resources for RoCE */ 11664 max_cp = bnxt_get_max_func_cp_rings(bp); 11665 max_stat = bnxt_get_max_func_stat_ctxs(bp); 11666 max_irq = bnxt_get_max_func_irqs(bp); 11667 if (max_cp <= BNXT_MIN_ROCE_CP_RINGS || 11668 max_irq <= BNXT_MIN_ROCE_CP_RINGS || 11669 max_stat <= BNXT_MIN_ROCE_STAT_CTXS) 11670 return 0; 11671 11672 max_cp -= BNXT_MIN_ROCE_CP_RINGS; 11673 max_irq -= BNXT_MIN_ROCE_CP_RINGS; 11674 max_stat -= BNXT_MIN_ROCE_STAT_CTXS; 11675 max_cp = min_t(int, max_cp, max_irq); 11676 max_cp = min_t(int, max_cp, max_stat); 11677 rc = bnxt_trim_rings(bp, max_rx, max_tx, max_cp, shared); 11678 if (rc) 11679 rc = 0; 11680 } 11681 return rc; 11682 } 11683 11684 /* In initial default shared ring setting, each shared ring must have a 11685 * RX/TX ring pair. 11686 */ 11687 static void bnxt_trim_dflt_sh_rings(struct bnxt *bp) 11688 { 11689 bp->cp_nr_rings = min_t(int, bp->tx_nr_rings_per_tc, bp->rx_nr_rings); 11690 bp->rx_nr_rings = bp->cp_nr_rings; 11691 bp->tx_nr_rings_per_tc = bp->cp_nr_rings; 11692 bp->tx_nr_rings = bp->tx_nr_rings_per_tc; 11693 } 11694 11695 static int bnxt_set_dflt_rings(struct bnxt *bp, bool sh) 11696 { 11697 int dflt_rings, max_rx_rings, max_tx_rings, rc; 11698 11699 if (!bnxt_can_reserve_rings(bp)) 11700 return 0; 11701 11702 if (sh) 11703 bp->flags |= BNXT_FLAG_SHARED_RINGS; 11704 dflt_rings = is_kdump_kernel() ? 1 : netif_get_num_default_rss_queues(); 11705 /* Reduce default rings on multi-port cards so that total default 11706 * rings do not exceed CPU count. 11707 */ 11708 if (bp->port_count > 1) { 11709 int max_rings = 11710 max_t(int, num_online_cpus() / bp->port_count, 1); 11711 11712 dflt_rings = min_t(int, dflt_rings, max_rings); 11713 } 11714 rc = bnxt_get_dflt_rings(bp, &max_rx_rings, &max_tx_rings, sh); 11715 if (rc) 11716 return rc; 11717 bp->rx_nr_rings = min_t(int, dflt_rings, max_rx_rings); 11718 bp->tx_nr_rings_per_tc = min_t(int, dflt_rings, max_tx_rings); 11719 if (sh) 11720 bnxt_trim_dflt_sh_rings(bp); 11721 else 11722 bp->cp_nr_rings = bp->tx_nr_rings_per_tc + bp->rx_nr_rings; 11723 bp->tx_nr_rings = bp->tx_nr_rings_per_tc; 11724 11725 rc = __bnxt_reserve_rings(bp); 11726 if (rc) 11727 netdev_warn(bp->dev, "Unable to reserve tx rings\n"); 11728 bp->tx_nr_rings_per_tc = bp->tx_nr_rings; 11729 if (sh) 11730 bnxt_trim_dflt_sh_rings(bp); 11731 11732 /* Rings may have been trimmed, re-reserve the trimmed rings. */ 11733 if (bnxt_need_reserve_rings(bp)) { 11734 rc = __bnxt_reserve_rings(bp); 11735 if (rc) 11736 netdev_warn(bp->dev, "2nd rings reservation failed.\n"); 11737 bp->tx_nr_rings_per_tc = bp->tx_nr_rings; 11738 } 11739 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) { 11740 bp->rx_nr_rings++; 11741 bp->cp_nr_rings++; 11742 } 11743 if (rc) { 11744 bp->tx_nr_rings = 0; 11745 bp->rx_nr_rings = 0; 11746 } 11747 return rc; 11748 } 11749 11750 static int bnxt_init_dflt_ring_mode(struct bnxt *bp) 11751 { 11752 int rc; 11753 11754 if (bp->tx_nr_rings) 11755 return 0; 11756 11757 bnxt_ulp_irq_stop(bp); 11758 bnxt_clear_int_mode(bp); 11759 rc = bnxt_set_dflt_rings(bp, true); 11760 if (rc) { 11761 netdev_err(bp->dev, "Not enough rings available.\n"); 11762 goto init_dflt_ring_err; 11763 } 11764 rc = bnxt_init_int_mode(bp); 11765 if (rc) 11766 goto init_dflt_ring_err; 11767 11768 bp->tx_nr_rings_per_tc = bp->tx_nr_rings; 11769 if (bnxt_rfs_supported(bp) && bnxt_rfs_capable(bp)) { 11770 bp->flags |= BNXT_FLAG_RFS; 11771 bp->dev->features |= NETIF_F_NTUPLE; 11772 } 11773 init_dflt_ring_err: 11774 bnxt_ulp_irq_restart(bp, rc); 11775 return rc; 11776 } 11777 11778 int bnxt_restore_pf_fw_resources(struct bnxt *bp) 11779 { 11780 int rc; 11781 11782 ASSERT_RTNL(); 11783 bnxt_hwrm_func_qcaps(bp); 11784 11785 if (netif_running(bp->dev)) 11786 __bnxt_close_nic(bp, true, false); 11787 11788 bnxt_ulp_irq_stop(bp); 11789 bnxt_clear_int_mode(bp); 11790 rc = bnxt_init_int_mode(bp); 11791 bnxt_ulp_irq_restart(bp, rc); 11792 11793 if (netif_running(bp->dev)) { 11794 if (rc) 11795 dev_close(bp->dev); 11796 else 11797 rc = bnxt_open_nic(bp, true, false); 11798 } 11799 11800 return rc; 11801 } 11802 11803 static int bnxt_init_mac_addr(struct bnxt *bp) 11804 { 11805 int rc = 0; 11806 11807 if (BNXT_PF(bp)) { 11808 memcpy(bp->dev->dev_addr, bp->pf.mac_addr, ETH_ALEN); 11809 } else { 11810 #ifdef CONFIG_BNXT_SRIOV 11811 struct bnxt_vf_info *vf = &bp->vf; 11812 bool strict_approval = true; 11813 11814 if (is_valid_ether_addr(vf->mac_addr)) { 11815 /* overwrite netdev dev_addr with admin VF MAC */ 11816 memcpy(bp->dev->dev_addr, vf->mac_addr, ETH_ALEN); 11817 /* Older PF driver or firmware may not approve this 11818 * correctly. 11819 */ 11820 strict_approval = false; 11821 } else { 11822 eth_hw_addr_random(bp->dev); 11823 } 11824 rc = bnxt_approve_mac(bp, bp->dev->dev_addr, strict_approval); 11825 #endif 11826 } 11827 return rc; 11828 } 11829 11830 #define BNXT_VPD_LEN 512 11831 static void bnxt_vpd_read_info(struct bnxt *bp) 11832 { 11833 struct pci_dev *pdev = bp->pdev; 11834 int i, len, pos, ro_size; 11835 ssize_t vpd_size; 11836 u8 *vpd_data; 11837 11838 vpd_data = kmalloc(BNXT_VPD_LEN, GFP_KERNEL); 11839 if (!vpd_data) 11840 return; 11841 11842 vpd_size = pci_read_vpd(pdev, 0, BNXT_VPD_LEN, vpd_data); 11843 if (vpd_size <= 0) { 11844 netdev_err(bp->dev, "Unable to read VPD\n"); 11845 goto exit; 11846 } 11847 11848 i = pci_vpd_find_tag(vpd_data, 0, vpd_size, PCI_VPD_LRDT_RO_DATA); 11849 if (i < 0) { 11850 netdev_err(bp->dev, "VPD READ-Only not found\n"); 11851 goto exit; 11852 } 11853 11854 ro_size = pci_vpd_lrdt_size(&vpd_data[i]); 11855 i += PCI_VPD_LRDT_TAG_SIZE; 11856 if (i + ro_size > vpd_size) 11857 goto exit; 11858 11859 pos = pci_vpd_find_info_keyword(vpd_data, i, ro_size, 11860 PCI_VPD_RO_KEYWORD_PARTNO); 11861 if (pos < 0) 11862 goto read_sn; 11863 11864 len = pci_vpd_info_field_size(&vpd_data[pos]); 11865 pos += PCI_VPD_INFO_FLD_HDR_SIZE; 11866 if (len + pos > vpd_size) 11867 goto read_sn; 11868 11869 strlcpy(bp->board_partno, &vpd_data[pos], min(len, BNXT_VPD_FLD_LEN)); 11870 11871 read_sn: 11872 pos = pci_vpd_find_info_keyword(vpd_data, i, ro_size, 11873 PCI_VPD_RO_KEYWORD_SERIALNO); 11874 if (pos < 0) 11875 goto exit; 11876 11877 len = pci_vpd_info_field_size(&vpd_data[pos]); 11878 pos += PCI_VPD_INFO_FLD_HDR_SIZE; 11879 if (len + pos > vpd_size) 11880 goto exit; 11881 11882 strlcpy(bp->board_serialno, &vpd_data[pos], min(len, BNXT_VPD_FLD_LEN)); 11883 exit: 11884 kfree(vpd_data); 11885 } 11886 11887 static int bnxt_pcie_dsn_get(struct bnxt *bp, u8 dsn[]) 11888 { 11889 struct pci_dev *pdev = bp->pdev; 11890 u64 qword; 11891 11892 qword = pci_get_dsn(pdev); 11893 if (!qword) { 11894 netdev_info(bp->dev, "Unable to read adapter's DSN\n"); 11895 return -EOPNOTSUPP; 11896 } 11897 11898 put_unaligned_le64(qword, dsn); 11899 11900 bp->flags |= BNXT_FLAG_DSN_VALID; 11901 return 0; 11902 } 11903 11904 static int bnxt_map_db_bar(struct bnxt *bp) 11905 { 11906 if (!bp->db_size) 11907 return -ENODEV; 11908 bp->bar1 = pci_iomap(bp->pdev, 2, bp->db_size); 11909 if (!bp->bar1) 11910 return -ENOMEM; 11911 return 0; 11912 } 11913 11914 static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 11915 { 11916 struct net_device *dev; 11917 struct bnxt *bp; 11918 int rc, max_irqs; 11919 11920 if (pci_is_bridge(pdev)) 11921 return -ENODEV; 11922 11923 /* Clear any pending DMA transactions from crash kernel 11924 * while loading driver in capture kernel. 11925 */ 11926 if (is_kdump_kernel()) { 11927 pci_clear_master(pdev); 11928 pcie_flr(pdev); 11929 } 11930 11931 max_irqs = bnxt_get_max_irq(pdev); 11932 dev = alloc_etherdev_mq(sizeof(*bp), max_irqs); 11933 if (!dev) 11934 return -ENOMEM; 11935 11936 bp = netdev_priv(dev); 11937 bnxt_set_max_func_irqs(bp, max_irqs); 11938 11939 if (bnxt_vf_pciid(ent->driver_data)) 11940 bp->flags |= BNXT_FLAG_VF; 11941 11942 if (pdev->msix_cap) 11943 bp->flags |= BNXT_FLAG_MSIX_CAP; 11944 11945 rc = bnxt_init_board(pdev, dev); 11946 if (rc < 0) 11947 goto init_err_free; 11948 11949 dev->netdev_ops = &bnxt_netdev_ops; 11950 dev->watchdog_timeo = BNXT_TX_TIMEOUT; 11951 dev->ethtool_ops = &bnxt_ethtool_ops; 11952 pci_set_drvdata(pdev, dev); 11953 11954 if (BNXT_PF(bp)) 11955 bnxt_vpd_read_info(bp); 11956 11957 rc = bnxt_alloc_hwrm_resources(bp); 11958 if (rc) 11959 goto init_err_pci_clean; 11960 11961 mutex_init(&bp->hwrm_cmd_lock); 11962 mutex_init(&bp->link_lock); 11963 11964 rc = bnxt_fw_init_one_p1(bp); 11965 if (rc) 11966 goto init_err_pci_clean; 11967 11968 if (BNXT_CHIP_P5(bp)) 11969 bp->flags |= BNXT_FLAG_CHIP_P5; 11970 11971 rc = bnxt_fw_init_one_p2(bp); 11972 if (rc) 11973 goto init_err_pci_clean; 11974 11975 rc = bnxt_map_db_bar(bp); 11976 if (rc) { 11977 dev_err(&pdev->dev, "Cannot map doorbell BAR rc = %d, aborting\n", 11978 rc); 11979 goto init_err_pci_clean; 11980 } 11981 11982 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG | 11983 NETIF_F_TSO | NETIF_F_TSO6 | 11984 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE | 11985 NETIF_F_GSO_IPXIP4 | 11986 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM | 11987 NETIF_F_GSO_PARTIAL | NETIF_F_RXHASH | 11988 NETIF_F_RXCSUM | NETIF_F_GRO; 11989 11990 if (BNXT_SUPPORTS_TPA(bp)) 11991 dev->hw_features |= NETIF_F_LRO; 11992 11993 dev->hw_enc_features = 11994 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG | 11995 NETIF_F_TSO | NETIF_F_TSO6 | 11996 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE | 11997 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM | 11998 NETIF_F_GSO_IPXIP4 | NETIF_F_GSO_PARTIAL; 11999 dev->udp_tunnel_nic_info = &bnxt_udp_tunnels; 12000 12001 dev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM | 12002 NETIF_F_GSO_GRE_CSUM; 12003 dev->vlan_features = dev->hw_features | NETIF_F_HIGHDMA; 12004 if (bp->fw_cap & BNXT_FW_CAP_VLAN_RX_STRIP) 12005 dev->hw_features |= BNXT_HW_FEATURE_VLAN_ALL_RX; 12006 if (bp->fw_cap & BNXT_FW_CAP_VLAN_TX_INSERT) 12007 dev->hw_features |= BNXT_HW_FEATURE_VLAN_ALL_TX; 12008 if (BNXT_SUPPORTS_TPA(bp)) 12009 dev->hw_features |= NETIF_F_GRO_HW; 12010 dev->features |= dev->hw_features | NETIF_F_HIGHDMA; 12011 if (dev->features & NETIF_F_GRO_HW) 12012 dev->features &= ~NETIF_F_LRO; 12013 dev->priv_flags |= IFF_UNICAST_FLT; 12014 12015 #ifdef CONFIG_BNXT_SRIOV 12016 init_waitqueue_head(&bp->sriov_cfg_wait); 12017 mutex_init(&bp->sriov_lock); 12018 #endif 12019 if (BNXT_SUPPORTS_TPA(bp)) { 12020 bp->gro_func = bnxt_gro_func_5730x; 12021 if (BNXT_CHIP_P4(bp)) 12022 bp->gro_func = bnxt_gro_func_5731x; 12023 else if (BNXT_CHIP_P5(bp)) 12024 bp->gro_func = bnxt_gro_func_5750x; 12025 } 12026 if (!BNXT_CHIP_P4_PLUS(bp)) 12027 bp->flags |= BNXT_FLAG_DOUBLE_DB; 12028 12029 bp->ulp_probe = bnxt_ulp_probe; 12030 12031 rc = bnxt_init_mac_addr(bp); 12032 if (rc) { 12033 dev_err(&pdev->dev, "Unable to initialize mac address.\n"); 12034 rc = -EADDRNOTAVAIL; 12035 goto init_err_pci_clean; 12036 } 12037 12038 if (BNXT_PF(bp)) { 12039 /* Read the adapter's DSN to use as the eswitch switch_id */ 12040 rc = bnxt_pcie_dsn_get(bp, bp->dsn); 12041 } 12042 12043 /* MTU range: 60 - FW defined max */ 12044 dev->min_mtu = ETH_ZLEN; 12045 dev->max_mtu = bp->max_mtu; 12046 12047 rc = bnxt_probe_phy(bp, true); 12048 if (rc) 12049 goto init_err_pci_clean; 12050 12051 bnxt_set_rx_skb_mode(bp, false); 12052 bnxt_set_tpa_flags(bp); 12053 bnxt_set_ring_params(bp); 12054 rc = bnxt_set_dflt_rings(bp, true); 12055 if (rc) { 12056 netdev_err(bp->dev, "Not enough rings available.\n"); 12057 rc = -ENOMEM; 12058 goto init_err_pci_clean; 12059 } 12060 12061 bnxt_fw_init_one_p3(bp); 12062 12063 if (dev->hw_features & BNXT_HW_FEATURE_VLAN_ALL_RX) 12064 bp->flags |= BNXT_FLAG_STRIP_VLAN; 12065 12066 rc = bnxt_init_int_mode(bp); 12067 if (rc) 12068 goto init_err_pci_clean; 12069 12070 /* No TC has been set yet and rings may have been trimmed due to 12071 * limited MSIX, so we re-initialize the TX rings per TC. 12072 */ 12073 bp->tx_nr_rings_per_tc = bp->tx_nr_rings; 12074 12075 rc = bnxt_alloc_rss_indir_tbl(bp); 12076 if (rc) 12077 goto init_err_pci_clean; 12078 bnxt_set_dflt_rss_indir_tbl(bp); 12079 12080 if (BNXT_PF(bp)) { 12081 if (!bnxt_pf_wq) { 12082 bnxt_pf_wq = 12083 create_singlethread_workqueue("bnxt_pf_wq"); 12084 if (!bnxt_pf_wq) { 12085 dev_err(&pdev->dev, "Unable to create workqueue.\n"); 12086 goto init_err_pci_clean; 12087 } 12088 } 12089 rc = bnxt_init_tc(bp); 12090 if (rc) 12091 netdev_err(dev, "Failed to initialize TC flower offload, err = %d.\n", 12092 rc); 12093 } 12094 12095 bnxt_dl_register(bp); 12096 12097 rc = register_netdev(dev); 12098 if (rc) 12099 goto init_err_cleanup; 12100 12101 if (BNXT_PF(bp)) 12102 devlink_port_type_eth_set(&bp->dl_port, bp->dev); 12103 bnxt_dl_fw_reporters_create(bp); 12104 12105 netdev_info(dev, "%s found at mem %lx, node addr %pM\n", 12106 board_info[ent->driver_data].name, 12107 (long)pci_resource_start(pdev, 0), dev->dev_addr); 12108 pcie_print_link_status(pdev); 12109 12110 return 0; 12111 12112 init_err_cleanup: 12113 bnxt_dl_unregister(bp); 12114 bnxt_shutdown_tc(bp); 12115 bnxt_clear_int_mode(bp); 12116 12117 init_err_pci_clean: 12118 bnxt_hwrm_func_drv_unrgtr(bp); 12119 bnxt_free_hwrm_short_cmd_req(bp); 12120 bnxt_free_hwrm_resources(bp); 12121 kfree(bp->fw_health); 12122 bp->fw_health = NULL; 12123 bnxt_cleanup_pci(bp); 12124 bnxt_free_ctx_mem(bp); 12125 kfree(bp->ctx); 12126 bp->ctx = NULL; 12127 kfree(bp->rss_indir_tbl); 12128 bp->rss_indir_tbl = NULL; 12129 12130 init_err_free: 12131 free_netdev(dev); 12132 return rc; 12133 } 12134 12135 static void bnxt_shutdown(struct pci_dev *pdev) 12136 { 12137 struct net_device *dev = pci_get_drvdata(pdev); 12138 struct bnxt *bp; 12139 12140 if (!dev) 12141 return; 12142 12143 rtnl_lock(); 12144 bp = netdev_priv(dev); 12145 if (!bp) 12146 goto shutdown_exit; 12147 12148 if (netif_running(dev)) 12149 dev_close(dev); 12150 12151 bnxt_ulp_shutdown(bp); 12152 bnxt_clear_int_mode(bp); 12153 pci_disable_device(pdev); 12154 12155 if (system_state == SYSTEM_POWER_OFF) { 12156 pci_wake_from_d3(pdev, bp->wol); 12157 pci_set_power_state(pdev, PCI_D3hot); 12158 } 12159 12160 shutdown_exit: 12161 rtnl_unlock(); 12162 } 12163 12164 #ifdef CONFIG_PM_SLEEP 12165 static int bnxt_suspend(struct device *device) 12166 { 12167 struct net_device *dev = dev_get_drvdata(device); 12168 struct bnxt *bp = netdev_priv(dev); 12169 int rc = 0; 12170 12171 rtnl_lock(); 12172 bnxt_ulp_stop(bp); 12173 if (netif_running(dev)) { 12174 netif_device_detach(dev); 12175 rc = bnxt_close(dev); 12176 } 12177 bnxt_hwrm_func_drv_unrgtr(bp); 12178 pci_disable_device(bp->pdev); 12179 bnxt_free_ctx_mem(bp); 12180 kfree(bp->ctx); 12181 bp->ctx = NULL; 12182 rtnl_unlock(); 12183 return rc; 12184 } 12185 12186 static int bnxt_resume(struct device *device) 12187 { 12188 struct net_device *dev = dev_get_drvdata(device); 12189 struct bnxt *bp = netdev_priv(dev); 12190 int rc = 0; 12191 12192 rtnl_lock(); 12193 rc = pci_enable_device(bp->pdev); 12194 if (rc) { 12195 netdev_err(dev, "Cannot re-enable PCI device during resume, err = %d\n", 12196 rc); 12197 goto resume_exit; 12198 } 12199 pci_set_master(bp->pdev); 12200 if (bnxt_hwrm_ver_get(bp)) { 12201 rc = -ENODEV; 12202 goto resume_exit; 12203 } 12204 rc = bnxt_hwrm_func_reset(bp); 12205 if (rc) { 12206 rc = -EBUSY; 12207 goto resume_exit; 12208 } 12209 12210 rc = bnxt_hwrm_func_qcaps(bp); 12211 if (rc) 12212 goto resume_exit; 12213 12214 if (bnxt_hwrm_func_drv_rgtr(bp, NULL, 0, false)) { 12215 rc = -ENODEV; 12216 goto resume_exit; 12217 } 12218 12219 bnxt_get_wol_settings(bp); 12220 if (netif_running(dev)) { 12221 rc = bnxt_open(dev); 12222 if (!rc) 12223 netif_device_attach(dev); 12224 } 12225 12226 resume_exit: 12227 bnxt_ulp_start(bp, rc); 12228 if (!rc) 12229 bnxt_reenable_sriov(bp); 12230 rtnl_unlock(); 12231 return rc; 12232 } 12233 12234 static SIMPLE_DEV_PM_OPS(bnxt_pm_ops, bnxt_suspend, bnxt_resume); 12235 #define BNXT_PM_OPS (&bnxt_pm_ops) 12236 12237 #else 12238 12239 #define BNXT_PM_OPS NULL 12240 12241 #endif /* CONFIG_PM_SLEEP */ 12242 12243 /** 12244 * bnxt_io_error_detected - called when PCI error is detected 12245 * @pdev: Pointer to PCI device 12246 * @state: The current pci connection state 12247 * 12248 * This function is called after a PCI bus error affecting 12249 * this device has been detected. 12250 */ 12251 static pci_ers_result_t bnxt_io_error_detected(struct pci_dev *pdev, 12252 pci_channel_state_t state) 12253 { 12254 struct net_device *netdev = pci_get_drvdata(pdev); 12255 struct bnxt *bp = netdev_priv(netdev); 12256 12257 netdev_info(netdev, "PCI I/O error detected\n"); 12258 12259 rtnl_lock(); 12260 netif_device_detach(netdev); 12261 12262 bnxt_ulp_stop(bp); 12263 12264 if (state == pci_channel_io_perm_failure) { 12265 rtnl_unlock(); 12266 return PCI_ERS_RESULT_DISCONNECT; 12267 } 12268 12269 if (netif_running(netdev)) 12270 bnxt_close(netdev); 12271 12272 pci_disable_device(pdev); 12273 bnxt_free_ctx_mem(bp); 12274 kfree(bp->ctx); 12275 bp->ctx = NULL; 12276 rtnl_unlock(); 12277 12278 /* Request a slot slot reset. */ 12279 return PCI_ERS_RESULT_NEED_RESET; 12280 } 12281 12282 /** 12283 * bnxt_io_slot_reset - called after the pci bus has been reset. 12284 * @pdev: Pointer to PCI device 12285 * 12286 * Restart the card from scratch, as if from a cold-boot. 12287 * At this point, the card has exprienced a hard reset, 12288 * followed by fixups by BIOS, and has its config space 12289 * set up identically to what it was at cold boot. 12290 */ 12291 static pci_ers_result_t bnxt_io_slot_reset(struct pci_dev *pdev) 12292 { 12293 struct net_device *netdev = pci_get_drvdata(pdev); 12294 struct bnxt *bp = netdev_priv(netdev); 12295 int err = 0; 12296 pci_ers_result_t result = PCI_ERS_RESULT_DISCONNECT; 12297 12298 netdev_info(bp->dev, "PCI Slot Reset\n"); 12299 12300 rtnl_lock(); 12301 12302 if (pci_enable_device(pdev)) { 12303 dev_err(&pdev->dev, 12304 "Cannot re-enable PCI device after reset.\n"); 12305 } else { 12306 pci_set_master(pdev); 12307 12308 err = bnxt_hwrm_func_reset(bp); 12309 if (!err) { 12310 err = bnxt_hwrm_func_qcaps(bp); 12311 if (!err && netif_running(netdev)) 12312 err = bnxt_open(netdev); 12313 } 12314 bnxt_ulp_start(bp, err); 12315 if (!err) { 12316 bnxt_reenable_sriov(bp); 12317 result = PCI_ERS_RESULT_RECOVERED; 12318 } 12319 } 12320 12321 if (result != PCI_ERS_RESULT_RECOVERED) { 12322 if (netif_running(netdev)) 12323 dev_close(netdev); 12324 pci_disable_device(pdev); 12325 } 12326 12327 rtnl_unlock(); 12328 12329 return result; 12330 } 12331 12332 /** 12333 * bnxt_io_resume - called when traffic can start flowing again. 12334 * @pdev: Pointer to PCI device 12335 * 12336 * This callback is called when the error recovery driver tells 12337 * us that its OK to resume normal operation. 12338 */ 12339 static void bnxt_io_resume(struct pci_dev *pdev) 12340 { 12341 struct net_device *netdev = pci_get_drvdata(pdev); 12342 12343 rtnl_lock(); 12344 12345 netif_device_attach(netdev); 12346 12347 rtnl_unlock(); 12348 } 12349 12350 static const struct pci_error_handlers bnxt_err_handler = { 12351 .error_detected = bnxt_io_error_detected, 12352 .slot_reset = bnxt_io_slot_reset, 12353 .resume = bnxt_io_resume 12354 }; 12355 12356 static struct pci_driver bnxt_pci_driver = { 12357 .name = DRV_MODULE_NAME, 12358 .id_table = bnxt_pci_tbl, 12359 .probe = bnxt_init_one, 12360 .remove = bnxt_remove_one, 12361 .shutdown = bnxt_shutdown, 12362 .driver.pm = BNXT_PM_OPS, 12363 .err_handler = &bnxt_err_handler, 12364 #if defined(CONFIG_BNXT_SRIOV) 12365 .sriov_configure = bnxt_sriov_configure, 12366 #endif 12367 }; 12368 12369 static int __init bnxt_init(void) 12370 { 12371 bnxt_debug_init(); 12372 return pci_register_driver(&bnxt_pci_driver); 12373 } 12374 12375 static void __exit bnxt_exit(void) 12376 { 12377 pci_unregister_driver(&bnxt_pci_driver); 12378 if (bnxt_pf_wq) 12379 destroy_workqueue(bnxt_pf_wq); 12380 bnxt_debug_exit(); 12381 } 12382 12383 module_init(bnxt_init); 12384 module_exit(bnxt_exit); 12385