1 /* Broadcom NetXtreme-C/E network driver. 2 * 3 * Copyright (c) 2014-2016 Broadcom Corporation 4 * Copyright (c) 2016-2018 Broadcom Limited 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation. 9 */ 10 11 #include <linux/module.h> 12 13 #include <linux/stringify.h> 14 #include <linux/kernel.h> 15 #include <linux/timer.h> 16 #include <linux/errno.h> 17 #include <linux/ioport.h> 18 #include <linux/slab.h> 19 #include <linux/vmalloc.h> 20 #include <linux/interrupt.h> 21 #include <linux/pci.h> 22 #include <linux/netdevice.h> 23 #include <linux/etherdevice.h> 24 #include <linux/skbuff.h> 25 #include <linux/dma-mapping.h> 26 #include <linux/bitops.h> 27 #include <linux/io.h> 28 #include <linux/irq.h> 29 #include <linux/delay.h> 30 #include <asm/byteorder.h> 31 #include <asm/page.h> 32 #include <linux/time.h> 33 #include <linux/mii.h> 34 #include <linux/if.h> 35 #include <linux/if_vlan.h> 36 #include <linux/if_bridge.h> 37 #include <linux/rtc.h> 38 #include <linux/bpf.h> 39 #include <net/ip.h> 40 #include <net/tcp.h> 41 #include <net/udp.h> 42 #include <net/checksum.h> 43 #include <net/ip6_checksum.h> 44 #include <net/udp_tunnel.h> 45 #include <linux/workqueue.h> 46 #include <linux/prefetch.h> 47 #include <linux/cache.h> 48 #include <linux/log2.h> 49 #include <linux/aer.h> 50 #include <linux/bitmap.h> 51 #include <linux/cpu_rmap.h> 52 #include <linux/cpumask.h> 53 #include <net/pkt_cls.h> 54 #include <linux/hwmon.h> 55 #include <linux/hwmon-sysfs.h> 56 57 #include "bnxt_hsi.h" 58 #include "bnxt.h" 59 #include "bnxt_ulp.h" 60 #include "bnxt_sriov.h" 61 #include "bnxt_ethtool.h" 62 #include "bnxt_dcb.h" 63 #include "bnxt_xdp.h" 64 #include "bnxt_vfr.h" 65 #include "bnxt_tc.h" 66 #include "bnxt_devlink.h" 67 #include "bnxt_debugfs.h" 68 69 #define BNXT_TX_TIMEOUT (5 * HZ) 70 71 static const char version[] = 72 "Broadcom NetXtreme-C/E driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION "\n"; 73 74 MODULE_LICENSE("GPL"); 75 MODULE_DESCRIPTION("Broadcom BCM573xx network driver"); 76 MODULE_VERSION(DRV_MODULE_VERSION); 77 78 #define BNXT_RX_OFFSET (NET_SKB_PAD + NET_IP_ALIGN) 79 #define BNXT_RX_DMA_OFFSET NET_SKB_PAD 80 #define BNXT_RX_COPY_THRESH 256 81 82 #define BNXT_TX_PUSH_THRESH 164 83 84 enum board_idx { 85 BCM57301, 86 BCM57302, 87 BCM57304, 88 BCM57417_NPAR, 89 BCM58700, 90 BCM57311, 91 BCM57312, 92 BCM57402, 93 BCM57404, 94 BCM57406, 95 BCM57402_NPAR, 96 BCM57407, 97 BCM57412, 98 BCM57414, 99 BCM57416, 100 BCM57417, 101 BCM57412_NPAR, 102 BCM57314, 103 BCM57417_SFP, 104 BCM57416_SFP, 105 BCM57404_NPAR, 106 BCM57406_NPAR, 107 BCM57407_SFP, 108 BCM57407_NPAR, 109 BCM57414_NPAR, 110 BCM57416_NPAR, 111 BCM57452, 112 BCM57454, 113 BCM5745x_NPAR, 114 BCM58802, 115 BCM58804, 116 BCM58808, 117 NETXTREME_E_VF, 118 NETXTREME_C_VF, 119 NETXTREME_S_VF, 120 }; 121 122 /* indexed by enum above */ 123 static const struct { 124 char *name; 125 } board_info[] = { 126 [BCM57301] = { "Broadcom BCM57301 NetXtreme-C 10Gb Ethernet" }, 127 [BCM57302] = { "Broadcom BCM57302 NetXtreme-C 10Gb/25Gb Ethernet" }, 128 [BCM57304] = { "Broadcom BCM57304 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" }, 129 [BCM57417_NPAR] = { "Broadcom BCM57417 NetXtreme-E Ethernet Partition" }, 130 [BCM58700] = { "Broadcom BCM58700 Nitro 1Gb/2.5Gb/10Gb Ethernet" }, 131 [BCM57311] = { "Broadcom BCM57311 NetXtreme-C 10Gb Ethernet" }, 132 [BCM57312] = { "Broadcom BCM57312 NetXtreme-C 10Gb/25Gb Ethernet" }, 133 [BCM57402] = { "Broadcom BCM57402 NetXtreme-E 10Gb Ethernet" }, 134 [BCM57404] = { "Broadcom BCM57404 NetXtreme-E 10Gb/25Gb Ethernet" }, 135 [BCM57406] = { "Broadcom BCM57406 NetXtreme-E 10GBase-T Ethernet" }, 136 [BCM57402_NPAR] = { "Broadcom BCM57402 NetXtreme-E Ethernet Partition" }, 137 [BCM57407] = { "Broadcom BCM57407 NetXtreme-E 10GBase-T Ethernet" }, 138 [BCM57412] = { "Broadcom BCM57412 NetXtreme-E 10Gb Ethernet" }, 139 [BCM57414] = { "Broadcom BCM57414 NetXtreme-E 10Gb/25Gb Ethernet" }, 140 [BCM57416] = { "Broadcom BCM57416 NetXtreme-E 10GBase-T Ethernet" }, 141 [BCM57417] = { "Broadcom BCM57417 NetXtreme-E 10GBase-T Ethernet" }, 142 [BCM57412_NPAR] = { "Broadcom BCM57412 NetXtreme-E Ethernet Partition" }, 143 [BCM57314] = { "Broadcom BCM57314 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" }, 144 [BCM57417_SFP] = { "Broadcom BCM57417 NetXtreme-E 10Gb/25Gb Ethernet" }, 145 [BCM57416_SFP] = { "Broadcom BCM57416 NetXtreme-E 10Gb Ethernet" }, 146 [BCM57404_NPAR] = { "Broadcom BCM57404 NetXtreme-E Ethernet Partition" }, 147 [BCM57406_NPAR] = { "Broadcom BCM57406 NetXtreme-E Ethernet Partition" }, 148 [BCM57407_SFP] = { "Broadcom BCM57407 NetXtreme-E 25Gb Ethernet" }, 149 [BCM57407_NPAR] = { "Broadcom BCM57407 NetXtreme-E Ethernet Partition" }, 150 [BCM57414_NPAR] = { "Broadcom BCM57414 NetXtreme-E Ethernet Partition" }, 151 [BCM57416_NPAR] = { "Broadcom BCM57416 NetXtreme-E Ethernet Partition" }, 152 [BCM57452] = { "Broadcom BCM57452 NetXtreme-E 10Gb/25Gb/40Gb/50Gb Ethernet" }, 153 [BCM57454] = { "Broadcom BCM57454 NetXtreme-E 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" }, 154 [BCM5745x_NPAR] = { "Broadcom BCM5745x NetXtreme-E Ethernet Partition" }, 155 [BCM58802] = { "Broadcom BCM58802 NetXtreme-S 10Gb/25Gb/40Gb/50Gb Ethernet" }, 156 [BCM58804] = { "Broadcom BCM58804 NetXtreme-S 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" }, 157 [BCM58808] = { "Broadcom BCM58808 NetXtreme-S 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" }, 158 [NETXTREME_E_VF] = { "Broadcom NetXtreme-E Ethernet Virtual Function" }, 159 [NETXTREME_C_VF] = { "Broadcom NetXtreme-C Ethernet Virtual Function" }, 160 [NETXTREME_S_VF] = { "Broadcom NetXtreme-S Ethernet Virtual Function" }, 161 }; 162 163 static const struct pci_device_id bnxt_pci_tbl[] = { 164 { PCI_VDEVICE(BROADCOM, 0x1604), .driver_data = BCM5745x_NPAR }, 165 { PCI_VDEVICE(BROADCOM, 0x1605), .driver_data = BCM5745x_NPAR }, 166 { PCI_VDEVICE(BROADCOM, 0x1614), .driver_data = BCM57454 }, 167 { PCI_VDEVICE(BROADCOM, 0x16c0), .driver_data = BCM57417_NPAR }, 168 { PCI_VDEVICE(BROADCOM, 0x16c8), .driver_data = BCM57301 }, 169 { PCI_VDEVICE(BROADCOM, 0x16c9), .driver_data = BCM57302 }, 170 { PCI_VDEVICE(BROADCOM, 0x16ca), .driver_data = BCM57304 }, 171 { PCI_VDEVICE(BROADCOM, 0x16cc), .driver_data = BCM57417_NPAR }, 172 { PCI_VDEVICE(BROADCOM, 0x16cd), .driver_data = BCM58700 }, 173 { PCI_VDEVICE(BROADCOM, 0x16ce), .driver_data = BCM57311 }, 174 { PCI_VDEVICE(BROADCOM, 0x16cf), .driver_data = BCM57312 }, 175 { PCI_VDEVICE(BROADCOM, 0x16d0), .driver_data = BCM57402 }, 176 { PCI_VDEVICE(BROADCOM, 0x16d1), .driver_data = BCM57404 }, 177 { PCI_VDEVICE(BROADCOM, 0x16d2), .driver_data = BCM57406 }, 178 { PCI_VDEVICE(BROADCOM, 0x16d4), .driver_data = BCM57402_NPAR }, 179 { PCI_VDEVICE(BROADCOM, 0x16d5), .driver_data = BCM57407 }, 180 { PCI_VDEVICE(BROADCOM, 0x16d6), .driver_data = BCM57412 }, 181 { PCI_VDEVICE(BROADCOM, 0x16d7), .driver_data = BCM57414 }, 182 { PCI_VDEVICE(BROADCOM, 0x16d8), .driver_data = BCM57416 }, 183 { PCI_VDEVICE(BROADCOM, 0x16d9), .driver_data = BCM57417 }, 184 { PCI_VDEVICE(BROADCOM, 0x16de), .driver_data = BCM57412_NPAR }, 185 { PCI_VDEVICE(BROADCOM, 0x16df), .driver_data = BCM57314 }, 186 { PCI_VDEVICE(BROADCOM, 0x16e2), .driver_data = BCM57417_SFP }, 187 { PCI_VDEVICE(BROADCOM, 0x16e3), .driver_data = BCM57416_SFP }, 188 { PCI_VDEVICE(BROADCOM, 0x16e7), .driver_data = BCM57404_NPAR }, 189 { PCI_VDEVICE(BROADCOM, 0x16e8), .driver_data = BCM57406_NPAR }, 190 { PCI_VDEVICE(BROADCOM, 0x16e9), .driver_data = BCM57407_SFP }, 191 { PCI_VDEVICE(BROADCOM, 0x16ea), .driver_data = BCM57407_NPAR }, 192 { PCI_VDEVICE(BROADCOM, 0x16eb), .driver_data = BCM57412_NPAR }, 193 { PCI_VDEVICE(BROADCOM, 0x16ec), .driver_data = BCM57414_NPAR }, 194 { PCI_VDEVICE(BROADCOM, 0x16ed), .driver_data = BCM57414_NPAR }, 195 { PCI_VDEVICE(BROADCOM, 0x16ee), .driver_data = BCM57416_NPAR }, 196 { PCI_VDEVICE(BROADCOM, 0x16ef), .driver_data = BCM57416_NPAR }, 197 { PCI_VDEVICE(BROADCOM, 0x16f0), .driver_data = BCM58808 }, 198 { PCI_VDEVICE(BROADCOM, 0x16f1), .driver_data = BCM57452 }, 199 { PCI_VDEVICE(BROADCOM, 0xd802), .driver_data = BCM58802 }, 200 { PCI_VDEVICE(BROADCOM, 0xd804), .driver_data = BCM58804 }, 201 #ifdef CONFIG_BNXT_SRIOV 202 { PCI_VDEVICE(BROADCOM, 0x1606), .driver_data = NETXTREME_E_VF }, 203 { PCI_VDEVICE(BROADCOM, 0x1609), .driver_data = NETXTREME_E_VF }, 204 { PCI_VDEVICE(BROADCOM, 0x16c1), .driver_data = NETXTREME_E_VF }, 205 { PCI_VDEVICE(BROADCOM, 0x16cb), .driver_data = NETXTREME_C_VF }, 206 { PCI_VDEVICE(BROADCOM, 0x16d3), .driver_data = NETXTREME_E_VF }, 207 { PCI_VDEVICE(BROADCOM, 0x16dc), .driver_data = NETXTREME_E_VF }, 208 { PCI_VDEVICE(BROADCOM, 0x16e1), .driver_data = NETXTREME_C_VF }, 209 { PCI_VDEVICE(BROADCOM, 0x16e5), .driver_data = NETXTREME_C_VF }, 210 { PCI_VDEVICE(BROADCOM, 0xd800), .driver_data = NETXTREME_S_VF }, 211 #endif 212 { 0 } 213 }; 214 215 MODULE_DEVICE_TABLE(pci, bnxt_pci_tbl); 216 217 static const u16 bnxt_vf_req_snif[] = { 218 HWRM_FUNC_CFG, 219 HWRM_FUNC_VF_CFG, 220 HWRM_PORT_PHY_QCFG, 221 HWRM_CFA_L2_FILTER_ALLOC, 222 }; 223 224 static const u16 bnxt_async_events_arr[] = { 225 ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE, 226 ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD, 227 ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED, 228 ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE, 229 ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE, 230 }; 231 232 static struct workqueue_struct *bnxt_pf_wq; 233 234 static bool bnxt_vf_pciid(enum board_idx idx) 235 { 236 return (idx == NETXTREME_C_VF || idx == NETXTREME_E_VF || 237 idx == NETXTREME_S_VF); 238 } 239 240 #define DB_CP_REARM_FLAGS (DB_KEY_CP | DB_IDX_VALID) 241 #define DB_CP_FLAGS (DB_KEY_CP | DB_IDX_VALID | DB_IRQ_DIS) 242 #define DB_CP_IRQ_DIS_FLAGS (DB_KEY_CP | DB_IRQ_DIS) 243 244 #define BNXT_CP_DB_REARM(db, raw_cons) \ 245 writel(DB_CP_REARM_FLAGS | RING_CMP(raw_cons), db) 246 247 #define BNXT_CP_DB(db, raw_cons) \ 248 writel(DB_CP_FLAGS | RING_CMP(raw_cons), db) 249 250 #define BNXT_CP_DB_IRQ_DIS(db) \ 251 writel(DB_CP_IRQ_DIS_FLAGS, db) 252 253 const u16 bnxt_lhint_arr[] = { 254 TX_BD_FLAGS_LHINT_512_AND_SMALLER, 255 TX_BD_FLAGS_LHINT_512_TO_1023, 256 TX_BD_FLAGS_LHINT_1024_TO_2047, 257 TX_BD_FLAGS_LHINT_1024_TO_2047, 258 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 259 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 260 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 261 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 262 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 263 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 264 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 265 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 266 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 267 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 268 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 269 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 270 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 271 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 272 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 273 }; 274 275 static u16 bnxt_xmit_get_cfa_action(struct sk_buff *skb) 276 { 277 struct metadata_dst *md_dst = skb_metadata_dst(skb); 278 279 if (!md_dst || md_dst->type != METADATA_HW_PORT_MUX) 280 return 0; 281 282 return md_dst->u.port_info.port_id; 283 } 284 285 static netdev_tx_t bnxt_start_xmit(struct sk_buff *skb, struct net_device *dev) 286 { 287 struct bnxt *bp = netdev_priv(dev); 288 struct tx_bd *txbd; 289 struct tx_bd_ext *txbd1; 290 struct netdev_queue *txq; 291 int i; 292 dma_addr_t mapping; 293 unsigned int length, pad = 0; 294 u32 len, free_size, vlan_tag_flags, cfa_action, flags; 295 u16 prod, last_frag; 296 struct pci_dev *pdev = bp->pdev; 297 struct bnxt_tx_ring_info *txr; 298 struct bnxt_sw_tx_bd *tx_buf; 299 300 i = skb_get_queue_mapping(skb); 301 if (unlikely(i >= bp->tx_nr_rings)) { 302 dev_kfree_skb_any(skb); 303 return NETDEV_TX_OK; 304 } 305 306 txq = netdev_get_tx_queue(dev, i); 307 txr = &bp->tx_ring[bp->tx_ring_map[i]]; 308 prod = txr->tx_prod; 309 310 free_size = bnxt_tx_avail(bp, txr); 311 if (unlikely(free_size < skb_shinfo(skb)->nr_frags + 2)) { 312 netif_tx_stop_queue(txq); 313 return NETDEV_TX_BUSY; 314 } 315 316 length = skb->len; 317 len = skb_headlen(skb); 318 last_frag = skb_shinfo(skb)->nr_frags; 319 320 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)]; 321 322 txbd->tx_bd_opaque = prod; 323 324 tx_buf = &txr->tx_buf_ring[prod]; 325 tx_buf->skb = skb; 326 tx_buf->nr_frags = last_frag; 327 328 vlan_tag_flags = 0; 329 cfa_action = bnxt_xmit_get_cfa_action(skb); 330 if (skb_vlan_tag_present(skb)) { 331 vlan_tag_flags = TX_BD_CFA_META_KEY_VLAN | 332 skb_vlan_tag_get(skb); 333 /* Currently supports 8021Q, 8021AD vlan offloads 334 * QINQ1, QINQ2, QINQ3 vlan headers are deprecated 335 */ 336 if (skb->vlan_proto == htons(ETH_P_8021Q)) 337 vlan_tag_flags |= 1 << TX_BD_CFA_META_TPID_SHIFT; 338 } 339 340 if (free_size == bp->tx_ring_size && length <= bp->tx_push_thresh) { 341 struct tx_push_buffer *tx_push_buf = txr->tx_push; 342 struct tx_push_bd *tx_push = &tx_push_buf->push_bd; 343 struct tx_bd_ext *tx_push1 = &tx_push->txbd2; 344 void *pdata = tx_push_buf->data; 345 u64 *end; 346 int j, push_len; 347 348 /* Set COAL_NOW to be ready quickly for the next push */ 349 tx_push->tx_bd_len_flags_type = 350 cpu_to_le32((length << TX_BD_LEN_SHIFT) | 351 TX_BD_TYPE_LONG_TX_BD | 352 TX_BD_FLAGS_LHINT_512_AND_SMALLER | 353 TX_BD_FLAGS_COAL_NOW | 354 TX_BD_FLAGS_PACKET_END | 355 (2 << TX_BD_FLAGS_BD_CNT_SHIFT)); 356 357 if (skb->ip_summed == CHECKSUM_PARTIAL) 358 tx_push1->tx_bd_hsize_lflags = 359 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM); 360 else 361 tx_push1->tx_bd_hsize_lflags = 0; 362 363 tx_push1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags); 364 tx_push1->tx_bd_cfa_action = 365 cpu_to_le32(cfa_action << TX_BD_CFA_ACTION_SHIFT); 366 367 end = pdata + length; 368 end = PTR_ALIGN(end, 8) - 1; 369 *end = 0; 370 371 skb_copy_from_linear_data(skb, pdata, len); 372 pdata += len; 373 for (j = 0; j < last_frag; j++) { 374 skb_frag_t *frag = &skb_shinfo(skb)->frags[j]; 375 void *fptr; 376 377 fptr = skb_frag_address_safe(frag); 378 if (!fptr) 379 goto normal_tx; 380 381 memcpy(pdata, fptr, skb_frag_size(frag)); 382 pdata += skb_frag_size(frag); 383 } 384 385 txbd->tx_bd_len_flags_type = tx_push->tx_bd_len_flags_type; 386 txbd->tx_bd_haddr = txr->data_mapping; 387 prod = NEXT_TX(prod); 388 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)]; 389 memcpy(txbd, tx_push1, sizeof(*txbd)); 390 prod = NEXT_TX(prod); 391 tx_push->doorbell = 392 cpu_to_le32(DB_KEY_TX_PUSH | DB_LONG_TX_PUSH | prod); 393 txr->tx_prod = prod; 394 395 tx_buf->is_push = 1; 396 netdev_tx_sent_queue(txq, skb->len); 397 wmb(); /* Sync is_push and byte queue before pushing data */ 398 399 push_len = (length + sizeof(*tx_push) + 7) / 8; 400 if (push_len > 16) { 401 __iowrite64_copy(txr->tx_doorbell, tx_push_buf, 16); 402 __iowrite32_copy(txr->tx_doorbell + 4, tx_push_buf + 1, 403 (push_len - 16) << 1); 404 } else { 405 __iowrite64_copy(txr->tx_doorbell, tx_push_buf, 406 push_len); 407 } 408 409 goto tx_done; 410 } 411 412 normal_tx: 413 if (length < BNXT_MIN_PKT_SIZE) { 414 pad = BNXT_MIN_PKT_SIZE - length; 415 if (skb_pad(skb, pad)) { 416 /* SKB already freed. */ 417 tx_buf->skb = NULL; 418 return NETDEV_TX_OK; 419 } 420 length = BNXT_MIN_PKT_SIZE; 421 } 422 423 mapping = dma_map_single(&pdev->dev, skb->data, len, DMA_TO_DEVICE); 424 425 if (unlikely(dma_mapping_error(&pdev->dev, mapping))) { 426 dev_kfree_skb_any(skb); 427 tx_buf->skb = NULL; 428 return NETDEV_TX_OK; 429 } 430 431 dma_unmap_addr_set(tx_buf, mapping, mapping); 432 flags = (len << TX_BD_LEN_SHIFT) | TX_BD_TYPE_LONG_TX_BD | 433 ((last_frag + 2) << TX_BD_FLAGS_BD_CNT_SHIFT); 434 435 txbd->tx_bd_haddr = cpu_to_le64(mapping); 436 437 prod = NEXT_TX(prod); 438 txbd1 = (struct tx_bd_ext *) 439 &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)]; 440 441 txbd1->tx_bd_hsize_lflags = 0; 442 if (skb_is_gso(skb)) { 443 u32 hdr_len; 444 445 if (skb->encapsulation) 446 hdr_len = skb_inner_network_offset(skb) + 447 skb_inner_network_header_len(skb) + 448 inner_tcp_hdrlen(skb); 449 else 450 hdr_len = skb_transport_offset(skb) + 451 tcp_hdrlen(skb); 452 453 txbd1->tx_bd_hsize_lflags = cpu_to_le32(TX_BD_FLAGS_LSO | 454 TX_BD_FLAGS_T_IPID | 455 (hdr_len << (TX_BD_HSIZE_SHIFT - 1))); 456 length = skb_shinfo(skb)->gso_size; 457 txbd1->tx_bd_mss = cpu_to_le32(length); 458 length += hdr_len; 459 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 460 txbd1->tx_bd_hsize_lflags = 461 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM); 462 txbd1->tx_bd_mss = 0; 463 } 464 465 length >>= 9; 466 flags |= bnxt_lhint_arr[length]; 467 txbd->tx_bd_len_flags_type = cpu_to_le32(flags); 468 469 txbd1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags); 470 txbd1->tx_bd_cfa_action = 471 cpu_to_le32(cfa_action << TX_BD_CFA_ACTION_SHIFT); 472 for (i = 0; i < last_frag; i++) { 473 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 474 475 prod = NEXT_TX(prod); 476 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)]; 477 478 len = skb_frag_size(frag); 479 mapping = skb_frag_dma_map(&pdev->dev, frag, 0, len, 480 DMA_TO_DEVICE); 481 482 if (unlikely(dma_mapping_error(&pdev->dev, mapping))) 483 goto tx_dma_error; 484 485 tx_buf = &txr->tx_buf_ring[prod]; 486 dma_unmap_addr_set(tx_buf, mapping, mapping); 487 488 txbd->tx_bd_haddr = cpu_to_le64(mapping); 489 490 flags = len << TX_BD_LEN_SHIFT; 491 txbd->tx_bd_len_flags_type = cpu_to_le32(flags); 492 } 493 494 flags &= ~TX_BD_LEN; 495 txbd->tx_bd_len_flags_type = 496 cpu_to_le32(((len + pad) << TX_BD_LEN_SHIFT) | flags | 497 TX_BD_FLAGS_PACKET_END); 498 499 netdev_tx_sent_queue(txq, skb->len); 500 501 /* Sync BD data before updating doorbell */ 502 wmb(); 503 504 prod = NEXT_TX(prod); 505 txr->tx_prod = prod; 506 507 if (!skb->xmit_more || netif_xmit_stopped(txq)) 508 bnxt_db_write(bp, txr->tx_doorbell, DB_KEY_TX | prod); 509 510 tx_done: 511 512 mmiowb(); 513 514 if (unlikely(bnxt_tx_avail(bp, txr) <= MAX_SKB_FRAGS + 1)) { 515 if (skb->xmit_more && !tx_buf->is_push) 516 bnxt_db_write(bp, txr->tx_doorbell, DB_KEY_TX | prod); 517 518 netif_tx_stop_queue(txq); 519 520 /* netif_tx_stop_queue() must be done before checking 521 * tx index in bnxt_tx_avail() below, because in 522 * bnxt_tx_int(), we update tx index before checking for 523 * netif_tx_queue_stopped(). 524 */ 525 smp_mb(); 526 if (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh) 527 netif_tx_wake_queue(txq); 528 } 529 return NETDEV_TX_OK; 530 531 tx_dma_error: 532 last_frag = i; 533 534 /* start back at beginning and unmap skb */ 535 prod = txr->tx_prod; 536 tx_buf = &txr->tx_buf_ring[prod]; 537 tx_buf->skb = NULL; 538 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping), 539 skb_headlen(skb), PCI_DMA_TODEVICE); 540 prod = NEXT_TX(prod); 541 542 /* unmap remaining mapped pages */ 543 for (i = 0; i < last_frag; i++) { 544 prod = NEXT_TX(prod); 545 tx_buf = &txr->tx_buf_ring[prod]; 546 dma_unmap_page(&pdev->dev, dma_unmap_addr(tx_buf, mapping), 547 skb_frag_size(&skb_shinfo(skb)->frags[i]), 548 PCI_DMA_TODEVICE); 549 } 550 551 dev_kfree_skb_any(skb); 552 return NETDEV_TX_OK; 553 } 554 555 static void bnxt_tx_int(struct bnxt *bp, struct bnxt_napi *bnapi, int nr_pkts) 556 { 557 struct bnxt_tx_ring_info *txr = bnapi->tx_ring; 558 struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, txr->txq_index); 559 u16 cons = txr->tx_cons; 560 struct pci_dev *pdev = bp->pdev; 561 int i; 562 unsigned int tx_bytes = 0; 563 564 for (i = 0; i < nr_pkts; i++) { 565 struct bnxt_sw_tx_bd *tx_buf; 566 struct sk_buff *skb; 567 int j, last; 568 569 tx_buf = &txr->tx_buf_ring[cons]; 570 cons = NEXT_TX(cons); 571 skb = tx_buf->skb; 572 tx_buf->skb = NULL; 573 574 if (tx_buf->is_push) { 575 tx_buf->is_push = 0; 576 goto next_tx_int; 577 } 578 579 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping), 580 skb_headlen(skb), PCI_DMA_TODEVICE); 581 last = tx_buf->nr_frags; 582 583 for (j = 0; j < last; j++) { 584 cons = NEXT_TX(cons); 585 tx_buf = &txr->tx_buf_ring[cons]; 586 dma_unmap_page( 587 &pdev->dev, 588 dma_unmap_addr(tx_buf, mapping), 589 skb_frag_size(&skb_shinfo(skb)->frags[j]), 590 PCI_DMA_TODEVICE); 591 } 592 593 next_tx_int: 594 cons = NEXT_TX(cons); 595 596 tx_bytes += skb->len; 597 dev_kfree_skb_any(skb); 598 } 599 600 netdev_tx_completed_queue(txq, nr_pkts, tx_bytes); 601 txr->tx_cons = cons; 602 603 /* Need to make the tx_cons update visible to bnxt_start_xmit() 604 * before checking for netif_tx_queue_stopped(). Without the 605 * memory barrier, there is a small possibility that bnxt_start_xmit() 606 * will miss it and cause the queue to be stopped forever. 607 */ 608 smp_mb(); 609 610 if (unlikely(netif_tx_queue_stopped(txq)) && 611 (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)) { 612 __netif_tx_lock(txq, smp_processor_id()); 613 if (netif_tx_queue_stopped(txq) && 614 bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh && 615 txr->dev_state != BNXT_DEV_STATE_CLOSING) 616 netif_tx_wake_queue(txq); 617 __netif_tx_unlock(txq); 618 } 619 } 620 621 static struct page *__bnxt_alloc_rx_page(struct bnxt *bp, dma_addr_t *mapping, 622 gfp_t gfp) 623 { 624 struct device *dev = &bp->pdev->dev; 625 struct page *page; 626 627 page = alloc_page(gfp); 628 if (!page) 629 return NULL; 630 631 *mapping = dma_map_page_attrs(dev, page, 0, PAGE_SIZE, bp->rx_dir, 632 DMA_ATTR_WEAK_ORDERING); 633 if (dma_mapping_error(dev, *mapping)) { 634 __free_page(page); 635 return NULL; 636 } 637 *mapping += bp->rx_dma_offset; 638 return page; 639 } 640 641 static inline u8 *__bnxt_alloc_rx_data(struct bnxt *bp, dma_addr_t *mapping, 642 gfp_t gfp) 643 { 644 u8 *data; 645 struct pci_dev *pdev = bp->pdev; 646 647 data = kmalloc(bp->rx_buf_size, gfp); 648 if (!data) 649 return NULL; 650 651 *mapping = dma_map_single_attrs(&pdev->dev, data + bp->rx_dma_offset, 652 bp->rx_buf_use_size, bp->rx_dir, 653 DMA_ATTR_WEAK_ORDERING); 654 655 if (dma_mapping_error(&pdev->dev, *mapping)) { 656 kfree(data); 657 data = NULL; 658 } 659 return data; 660 } 661 662 int bnxt_alloc_rx_data(struct bnxt *bp, struct bnxt_rx_ring_info *rxr, 663 u16 prod, gfp_t gfp) 664 { 665 struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)]; 666 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[prod]; 667 dma_addr_t mapping; 668 669 if (BNXT_RX_PAGE_MODE(bp)) { 670 struct page *page = __bnxt_alloc_rx_page(bp, &mapping, gfp); 671 672 if (!page) 673 return -ENOMEM; 674 675 rx_buf->data = page; 676 rx_buf->data_ptr = page_address(page) + bp->rx_offset; 677 } else { 678 u8 *data = __bnxt_alloc_rx_data(bp, &mapping, gfp); 679 680 if (!data) 681 return -ENOMEM; 682 683 rx_buf->data = data; 684 rx_buf->data_ptr = data + bp->rx_offset; 685 } 686 rx_buf->mapping = mapping; 687 688 rxbd->rx_bd_haddr = cpu_to_le64(mapping); 689 return 0; 690 } 691 692 void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons, void *data) 693 { 694 u16 prod = rxr->rx_prod; 695 struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf; 696 struct rx_bd *cons_bd, *prod_bd; 697 698 prod_rx_buf = &rxr->rx_buf_ring[prod]; 699 cons_rx_buf = &rxr->rx_buf_ring[cons]; 700 701 prod_rx_buf->data = data; 702 prod_rx_buf->data_ptr = cons_rx_buf->data_ptr; 703 704 prod_rx_buf->mapping = cons_rx_buf->mapping; 705 706 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)]; 707 cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)]; 708 709 prod_bd->rx_bd_haddr = cons_bd->rx_bd_haddr; 710 } 711 712 static inline u16 bnxt_find_next_agg_idx(struct bnxt_rx_ring_info *rxr, u16 idx) 713 { 714 u16 next, max = rxr->rx_agg_bmap_size; 715 716 next = find_next_zero_bit(rxr->rx_agg_bmap, max, idx); 717 if (next >= max) 718 next = find_first_zero_bit(rxr->rx_agg_bmap, max); 719 return next; 720 } 721 722 static inline int bnxt_alloc_rx_page(struct bnxt *bp, 723 struct bnxt_rx_ring_info *rxr, 724 u16 prod, gfp_t gfp) 725 { 726 struct rx_bd *rxbd = 727 &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)]; 728 struct bnxt_sw_rx_agg_bd *rx_agg_buf; 729 struct pci_dev *pdev = bp->pdev; 730 struct page *page; 731 dma_addr_t mapping; 732 u16 sw_prod = rxr->rx_sw_agg_prod; 733 unsigned int offset = 0; 734 735 if (PAGE_SIZE > BNXT_RX_PAGE_SIZE) { 736 page = rxr->rx_page; 737 if (!page) { 738 page = alloc_page(gfp); 739 if (!page) 740 return -ENOMEM; 741 rxr->rx_page = page; 742 rxr->rx_page_offset = 0; 743 } 744 offset = rxr->rx_page_offset; 745 rxr->rx_page_offset += BNXT_RX_PAGE_SIZE; 746 if (rxr->rx_page_offset == PAGE_SIZE) 747 rxr->rx_page = NULL; 748 else 749 get_page(page); 750 } else { 751 page = alloc_page(gfp); 752 if (!page) 753 return -ENOMEM; 754 } 755 756 mapping = dma_map_page_attrs(&pdev->dev, page, offset, 757 BNXT_RX_PAGE_SIZE, PCI_DMA_FROMDEVICE, 758 DMA_ATTR_WEAK_ORDERING); 759 if (dma_mapping_error(&pdev->dev, mapping)) { 760 __free_page(page); 761 return -EIO; 762 } 763 764 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap))) 765 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod); 766 767 __set_bit(sw_prod, rxr->rx_agg_bmap); 768 rx_agg_buf = &rxr->rx_agg_ring[sw_prod]; 769 rxr->rx_sw_agg_prod = NEXT_RX_AGG(sw_prod); 770 771 rx_agg_buf->page = page; 772 rx_agg_buf->offset = offset; 773 rx_agg_buf->mapping = mapping; 774 rxbd->rx_bd_haddr = cpu_to_le64(mapping); 775 rxbd->rx_bd_opaque = sw_prod; 776 return 0; 777 } 778 779 static void bnxt_reuse_rx_agg_bufs(struct bnxt_napi *bnapi, u16 cp_cons, 780 u32 agg_bufs) 781 { 782 struct bnxt *bp = bnapi->bp; 783 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 784 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 785 u16 prod = rxr->rx_agg_prod; 786 u16 sw_prod = rxr->rx_sw_agg_prod; 787 u32 i; 788 789 for (i = 0; i < agg_bufs; i++) { 790 u16 cons; 791 struct rx_agg_cmp *agg; 792 struct bnxt_sw_rx_agg_bd *cons_rx_buf, *prod_rx_buf; 793 struct rx_bd *prod_bd; 794 struct page *page; 795 796 agg = (struct rx_agg_cmp *) 797 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 798 cons = agg->rx_agg_cmp_opaque; 799 __clear_bit(cons, rxr->rx_agg_bmap); 800 801 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap))) 802 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod); 803 804 __set_bit(sw_prod, rxr->rx_agg_bmap); 805 prod_rx_buf = &rxr->rx_agg_ring[sw_prod]; 806 cons_rx_buf = &rxr->rx_agg_ring[cons]; 807 808 /* It is possible for sw_prod to be equal to cons, so 809 * set cons_rx_buf->page to NULL first. 810 */ 811 page = cons_rx_buf->page; 812 cons_rx_buf->page = NULL; 813 prod_rx_buf->page = page; 814 prod_rx_buf->offset = cons_rx_buf->offset; 815 816 prod_rx_buf->mapping = cons_rx_buf->mapping; 817 818 prod_bd = &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)]; 819 820 prod_bd->rx_bd_haddr = cpu_to_le64(cons_rx_buf->mapping); 821 prod_bd->rx_bd_opaque = sw_prod; 822 823 prod = NEXT_RX_AGG(prod); 824 sw_prod = NEXT_RX_AGG(sw_prod); 825 cp_cons = NEXT_CMP(cp_cons); 826 } 827 rxr->rx_agg_prod = prod; 828 rxr->rx_sw_agg_prod = sw_prod; 829 } 830 831 static struct sk_buff *bnxt_rx_page_skb(struct bnxt *bp, 832 struct bnxt_rx_ring_info *rxr, 833 u16 cons, void *data, u8 *data_ptr, 834 dma_addr_t dma_addr, 835 unsigned int offset_and_len) 836 { 837 unsigned int payload = offset_and_len >> 16; 838 unsigned int len = offset_and_len & 0xffff; 839 struct skb_frag_struct *frag; 840 struct page *page = data; 841 u16 prod = rxr->rx_prod; 842 struct sk_buff *skb; 843 int off, err; 844 845 err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC); 846 if (unlikely(err)) { 847 bnxt_reuse_rx_data(rxr, cons, data); 848 return NULL; 849 } 850 dma_addr -= bp->rx_dma_offset; 851 dma_unmap_page_attrs(&bp->pdev->dev, dma_addr, PAGE_SIZE, bp->rx_dir, 852 DMA_ATTR_WEAK_ORDERING); 853 854 if (unlikely(!payload)) 855 payload = eth_get_headlen(data_ptr, len); 856 857 skb = napi_alloc_skb(&rxr->bnapi->napi, payload); 858 if (!skb) { 859 __free_page(page); 860 return NULL; 861 } 862 863 off = (void *)data_ptr - page_address(page); 864 skb_add_rx_frag(skb, 0, page, off, len, PAGE_SIZE); 865 memcpy(skb->data - NET_IP_ALIGN, data_ptr - NET_IP_ALIGN, 866 payload + NET_IP_ALIGN); 867 868 frag = &skb_shinfo(skb)->frags[0]; 869 skb_frag_size_sub(frag, payload); 870 frag->page_offset += payload; 871 skb->data_len -= payload; 872 skb->tail += payload; 873 874 return skb; 875 } 876 877 static struct sk_buff *bnxt_rx_skb(struct bnxt *bp, 878 struct bnxt_rx_ring_info *rxr, u16 cons, 879 void *data, u8 *data_ptr, 880 dma_addr_t dma_addr, 881 unsigned int offset_and_len) 882 { 883 u16 prod = rxr->rx_prod; 884 struct sk_buff *skb; 885 int err; 886 887 err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC); 888 if (unlikely(err)) { 889 bnxt_reuse_rx_data(rxr, cons, data); 890 return NULL; 891 } 892 893 skb = build_skb(data, 0); 894 dma_unmap_single_attrs(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size, 895 bp->rx_dir, DMA_ATTR_WEAK_ORDERING); 896 if (!skb) { 897 kfree(data); 898 return NULL; 899 } 900 901 skb_reserve(skb, bp->rx_offset); 902 skb_put(skb, offset_and_len & 0xffff); 903 return skb; 904 } 905 906 static struct sk_buff *bnxt_rx_pages(struct bnxt *bp, struct bnxt_napi *bnapi, 907 struct sk_buff *skb, u16 cp_cons, 908 u32 agg_bufs) 909 { 910 struct pci_dev *pdev = bp->pdev; 911 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 912 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 913 u16 prod = rxr->rx_agg_prod; 914 u32 i; 915 916 for (i = 0; i < agg_bufs; i++) { 917 u16 cons, frag_len; 918 struct rx_agg_cmp *agg; 919 struct bnxt_sw_rx_agg_bd *cons_rx_buf; 920 struct page *page; 921 dma_addr_t mapping; 922 923 agg = (struct rx_agg_cmp *) 924 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 925 cons = agg->rx_agg_cmp_opaque; 926 frag_len = (le32_to_cpu(agg->rx_agg_cmp_len_flags_type) & 927 RX_AGG_CMP_LEN) >> RX_AGG_CMP_LEN_SHIFT; 928 929 cons_rx_buf = &rxr->rx_agg_ring[cons]; 930 skb_fill_page_desc(skb, i, cons_rx_buf->page, 931 cons_rx_buf->offset, frag_len); 932 __clear_bit(cons, rxr->rx_agg_bmap); 933 934 /* It is possible for bnxt_alloc_rx_page() to allocate 935 * a sw_prod index that equals the cons index, so we 936 * need to clear the cons entry now. 937 */ 938 mapping = cons_rx_buf->mapping; 939 page = cons_rx_buf->page; 940 cons_rx_buf->page = NULL; 941 942 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_ATOMIC) != 0) { 943 struct skb_shared_info *shinfo; 944 unsigned int nr_frags; 945 946 shinfo = skb_shinfo(skb); 947 nr_frags = --shinfo->nr_frags; 948 __skb_frag_set_page(&shinfo->frags[nr_frags], NULL); 949 950 dev_kfree_skb(skb); 951 952 cons_rx_buf->page = page; 953 954 /* Update prod since possibly some pages have been 955 * allocated already. 956 */ 957 rxr->rx_agg_prod = prod; 958 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs - i); 959 return NULL; 960 } 961 962 dma_unmap_page_attrs(&pdev->dev, mapping, BNXT_RX_PAGE_SIZE, 963 PCI_DMA_FROMDEVICE, 964 DMA_ATTR_WEAK_ORDERING); 965 966 skb->data_len += frag_len; 967 skb->len += frag_len; 968 skb->truesize += PAGE_SIZE; 969 970 prod = NEXT_RX_AGG(prod); 971 cp_cons = NEXT_CMP(cp_cons); 972 } 973 rxr->rx_agg_prod = prod; 974 return skb; 975 } 976 977 static int bnxt_agg_bufs_valid(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, 978 u8 agg_bufs, u32 *raw_cons) 979 { 980 u16 last; 981 struct rx_agg_cmp *agg; 982 983 *raw_cons = ADV_RAW_CMP(*raw_cons, agg_bufs); 984 last = RING_CMP(*raw_cons); 985 agg = (struct rx_agg_cmp *) 986 &cpr->cp_desc_ring[CP_RING(last)][CP_IDX(last)]; 987 return RX_AGG_CMP_VALID(agg, *raw_cons); 988 } 989 990 static inline struct sk_buff *bnxt_copy_skb(struct bnxt_napi *bnapi, u8 *data, 991 unsigned int len, 992 dma_addr_t mapping) 993 { 994 struct bnxt *bp = bnapi->bp; 995 struct pci_dev *pdev = bp->pdev; 996 struct sk_buff *skb; 997 998 skb = napi_alloc_skb(&bnapi->napi, len); 999 if (!skb) 1000 return NULL; 1001 1002 dma_sync_single_for_cpu(&pdev->dev, mapping, bp->rx_copy_thresh, 1003 bp->rx_dir); 1004 1005 memcpy(skb->data - NET_IP_ALIGN, data - NET_IP_ALIGN, 1006 len + NET_IP_ALIGN); 1007 1008 dma_sync_single_for_device(&pdev->dev, mapping, bp->rx_copy_thresh, 1009 bp->rx_dir); 1010 1011 skb_put(skb, len); 1012 return skb; 1013 } 1014 1015 static int bnxt_discard_rx(struct bnxt *bp, struct bnxt_napi *bnapi, 1016 u32 *raw_cons, void *cmp) 1017 { 1018 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 1019 struct rx_cmp *rxcmp = cmp; 1020 u32 tmp_raw_cons = *raw_cons; 1021 u8 cmp_type, agg_bufs = 0; 1022 1023 cmp_type = RX_CMP_TYPE(rxcmp); 1024 1025 if (cmp_type == CMP_TYPE_RX_L2_CMP) { 1026 agg_bufs = (le32_to_cpu(rxcmp->rx_cmp_misc_v1) & 1027 RX_CMP_AGG_BUFS) >> 1028 RX_CMP_AGG_BUFS_SHIFT; 1029 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) { 1030 struct rx_tpa_end_cmp *tpa_end = cmp; 1031 1032 agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) & 1033 RX_TPA_END_CMP_AGG_BUFS) >> 1034 RX_TPA_END_CMP_AGG_BUFS_SHIFT; 1035 } 1036 1037 if (agg_bufs) { 1038 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons)) 1039 return -EBUSY; 1040 } 1041 *raw_cons = tmp_raw_cons; 1042 return 0; 1043 } 1044 1045 static void bnxt_queue_sp_work(struct bnxt *bp) 1046 { 1047 if (BNXT_PF(bp)) 1048 queue_work(bnxt_pf_wq, &bp->sp_task); 1049 else 1050 schedule_work(&bp->sp_task); 1051 } 1052 1053 static void bnxt_cancel_sp_work(struct bnxt *bp) 1054 { 1055 if (BNXT_PF(bp)) 1056 flush_workqueue(bnxt_pf_wq); 1057 else 1058 cancel_work_sync(&bp->sp_task); 1059 } 1060 1061 static void bnxt_sched_reset(struct bnxt *bp, struct bnxt_rx_ring_info *rxr) 1062 { 1063 if (!rxr->bnapi->in_reset) { 1064 rxr->bnapi->in_reset = true; 1065 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event); 1066 bnxt_queue_sp_work(bp); 1067 } 1068 rxr->rx_next_cons = 0xffff; 1069 } 1070 1071 static void bnxt_tpa_start(struct bnxt *bp, struct bnxt_rx_ring_info *rxr, 1072 struct rx_tpa_start_cmp *tpa_start, 1073 struct rx_tpa_start_cmp_ext *tpa_start1) 1074 { 1075 u8 agg_id = TPA_START_AGG_ID(tpa_start); 1076 u16 cons, prod; 1077 struct bnxt_tpa_info *tpa_info; 1078 struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf; 1079 struct rx_bd *prod_bd; 1080 dma_addr_t mapping; 1081 1082 cons = tpa_start->rx_tpa_start_cmp_opaque; 1083 prod = rxr->rx_prod; 1084 cons_rx_buf = &rxr->rx_buf_ring[cons]; 1085 prod_rx_buf = &rxr->rx_buf_ring[prod]; 1086 tpa_info = &rxr->rx_tpa[agg_id]; 1087 1088 if (unlikely(cons != rxr->rx_next_cons)) { 1089 bnxt_sched_reset(bp, rxr); 1090 return; 1091 } 1092 /* Store cfa_code in tpa_info to use in tpa_end 1093 * completion processing. 1094 */ 1095 tpa_info->cfa_code = TPA_START_CFA_CODE(tpa_start1); 1096 prod_rx_buf->data = tpa_info->data; 1097 prod_rx_buf->data_ptr = tpa_info->data_ptr; 1098 1099 mapping = tpa_info->mapping; 1100 prod_rx_buf->mapping = mapping; 1101 1102 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)]; 1103 1104 prod_bd->rx_bd_haddr = cpu_to_le64(mapping); 1105 1106 tpa_info->data = cons_rx_buf->data; 1107 tpa_info->data_ptr = cons_rx_buf->data_ptr; 1108 cons_rx_buf->data = NULL; 1109 tpa_info->mapping = cons_rx_buf->mapping; 1110 1111 tpa_info->len = 1112 le32_to_cpu(tpa_start->rx_tpa_start_cmp_len_flags_type) >> 1113 RX_TPA_START_CMP_LEN_SHIFT; 1114 if (likely(TPA_START_HASH_VALID(tpa_start))) { 1115 u32 hash_type = TPA_START_HASH_TYPE(tpa_start); 1116 1117 tpa_info->hash_type = PKT_HASH_TYPE_L4; 1118 tpa_info->gso_type = SKB_GSO_TCPV4; 1119 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */ 1120 if (hash_type == 3 || TPA_START_IS_IPV6(tpa_start1)) 1121 tpa_info->gso_type = SKB_GSO_TCPV6; 1122 tpa_info->rss_hash = 1123 le32_to_cpu(tpa_start->rx_tpa_start_cmp_rss_hash); 1124 } else { 1125 tpa_info->hash_type = PKT_HASH_TYPE_NONE; 1126 tpa_info->gso_type = 0; 1127 if (netif_msg_rx_err(bp)) 1128 netdev_warn(bp->dev, "TPA packet without valid hash\n"); 1129 } 1130 tpa_info->flags2 = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_flags2); 1131 tpa_info->metadata = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_metadata); 1132 tpa_info->hdr_info = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_hdr_info); 1133 1134 rxr->rx_prod = NEXT_RX(prod); 1135 cons = NEXT_RX(cons); 1136 rxr->rx_next_cons = NEXT_RX(cons); 1137 cons_rx_buf = &rxr->rx_buf_ring[cons]; 1138 1139 bnxt_reuse_rx_data(rxr, cons, cons_rx_buf->data); 1140 rxr->rx_prod = NEXT_RX(rxr->rx_prod); 1141 cons_rx_buf->data = NULL; 1142 } 1143 1144 static void bnxt_abort_tpa(struct bnxt *bp, struct bnxt_napi *bnapi, 1145 u16 cp_cons, u32 agg_bufs) 1146 { 1147 if (agg_bufs) 1148 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs); 1149 } 1150 1151 static struct sk_buff *bnxt_gro_func_5731x(struct bnxt_tpa_info *tpa_info, 1152 int payload_off, int tcp_ts, 1153 struct sk_buff *skb) 1154 { 1155 #ifdef CONFIG_INET 1156 struct tcphdr *th; 1157 int len, nw_off; 1158 u16 outer_ip_off, inner_ip_off, inner_mac_off; 1159 u32 hdr_info = tpa_info->hdr_info; 1160 bool loopback = false; 1161 1162 inner_ip_off = BNXT_TPA_INNER_L3_OFF(hdr_info); 1163 inner_mac_off = BNXT_TPA_INNER_L2_OFF(hdr_info); 1164 outer_ip_off = BNXT_TPA_OUTER_L3_OFF(hdr_info); 1165 1166 /* If the packet is an internal loopback packet, the offsets will 1167 * have an extra 4 bytes. 1168 */ 1169 if (inner_mac_off == 4) { 1170 loopback = true; 1171 } else if (inner_mac_off > 4) { 1172 __be16 proto = *((__be16 *)(skb->data + inner_ip_off - 1173 ETH_HLEN - 2)); 1174 1175 /* We only support inner iPv4/ipv6. If we don't see the 1176 * correct protocol ID, it must be a loopback packet where 1177 * the offsets are off by 4. 1178 */ 1179 if (proto != htons(ETH_P_IP) && proto != htons(ETH_P_IPV6)) 1180 loopback = true; 1181 } 1182 if (loopback) { 1183 /* internal loopback packet, subtract all offsets by 4 */ 1184 inner_ip_off -= 4; 1185 inner_mac_off -= 4; 1186 outer_ip_off -= 4; 1187 } 1188 1189 nw_off = inner_ip_off - ETH_HLEN; 1190 skb_set_network_header(skb, nw_off); 1191 if (tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_IP_TYPE) { 1192 struct ipv6hdr *iph = ipv6_hdr(skb); 1193 1194 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr)); 1195 len = skb->len - skb_transport_offset(skb); 1196 th = tcp_hdr(skb); 1197 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0); 1198 } else { 1199 struct iphdr *iph = ip_hdr(skb); 1200 1201 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr)); 1202 len = skb->len - skb_transport_offset(skb); 1203 th = tcp_hdr(skb); 1204 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0); 1205 } 1206 1207 if (inner_mac_off) { /* tunnel */ 1208 struct udphdr *uh = NULL; 1209 __be16 proto = *((__be16 *)(skb->data + outer_ip_off - 1210 ETH_HLEN - 2)); 1211 1212 if (proto == htons(ETH_P_IP)) { 1213 struct iphdr *iph = (struct iphdr *)skb->data; 1214 1215 if (iph->protocol == IPPROTO_UDP) 1216 uh = (struct udphdr *)(iph + 1); 1217 } else { 1218 struct ipv6hdr *iph = (struct ipv6hdr *)skb->data; 1219 1220 if (iph->nexthdr == IPPROTO_UDP) 1221 uh = (struct udphdr *)(iph + 1); 1222 } 1223 if (uh) { 1224 if (uh->check) 1225 skb_shinfo(skb)->gso_type |= 1226 SKB_GSO_UDP_TUNNEL_CSUM; 1227 else 1228 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL; 1229 } 1230 } 1231 #endif 1232 return skb; 1233 } 1234 1235 #define BNXT_IPV4_HDR_SIZE (sizeof(struct iphdr) + sizeof(struct tcphdr)) 1236 #define BNXT_IPV6_HDR_SIZE (sizeof(struct ipv6hdr) + sizeof(struct tcphdr)) 1237 1238 static struct sk_buff *bnxt_gro_func_5730x(struct bnxt_tpa_info *tpa_info, 1239 int payload_off, int tcp_ts, 1240 struct sk_buff *skb) 1241 { 1242 #ifdef CONFIG_INET 1243 struct tcphdr *th; 1244 int len, nw_off, tcp_opt_len = 0; 1245 1246 if (tcp_ts) 1247 tcp_opt_len = 12; 1248 1249 if (tpa_info->gso_type == SKB_GSO_TCPV4) { 1250 struct iphdr *iph; 1251 1252 nw_off = payload_off - BNXT_IPV4_HDR_SIZE - tcp_opt_len - 1253 ETH_HLEN; 1254 skb_set_network_header(skb, nw_off); 1255 iph = ip_hdr(skb); 1256 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr)); 1257 len = skb->len - skb_transport_offset(skb); 1258 th = tcp_hdr(skb); 1259 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0); 1260 } else if (tpa_info->gso_type == SKB_GSO_TCPV6) { 1261 struct ipv6hdr *iph; 1262 1263 nw_off = payload_off - BNXT_IPV6_HDR_SIZE - tcp_opt_len - 1264 ETH_HLEN; 1265 skb_set_network_header(skb, nw_off); 1266 iph = ipv6_hdr(skb); 1267 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr)); 1268 len = skb->len - skb_transport_offset(skb); 1269 th = tcp_hdr(skb); 1270 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0); 1271 } else { 1272 dev_kfree_skb_any(skb); 1273 return NULL; 1274 } 1275 1276 if (nw_off) { /* tunnel */ 1277 struct udphdr *uh = NULL; 1278 1279 if (skb->protocol == htons(ETH_P_IP)) { 1280 struct iphdr *iph = (struct iphdr *)skb->data; 1281 1282 if (iph->protocol == IPPROTO_UDP) 1283 uh = (struct udphdr *)(iph + 1); 1284 } else { 1285 struct ipv6hdr *iph = (struct ipv6hdr *)skb->data; 1286 1287 if (iph->nexthdr == IPPROTO_UDP) 1288 uh = (struct udphdr *)(iph + 1); 1289 } 1290 if (uh) { 1291 if (uh->check) 1292 skb_shinfo(skb)->gso_type |= 1293 SKB_GSO_UDP_TUNNEL_CSUM; 1294 else 1295 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL; 1296 } 1297 } 1298 #endif 1299 return skb; 1300 } 1301 1302 static inline struct sk_buff *bnxt_gro_skb(struct bnxt *bp, 1303 struct bnxt_tpa_info *tpa_info, 1304 struct rx_tpa_end_cmp *tpa_end, 1305 struct rx_tpa_end_cmp_ext *tpa_end1, 1306 struct sk_buff *skb) 1307 { 1308 #ifdef CONFIG_INET 1309 int payload_off; 1310 u16 segs; 1311 1312 segs = TPA_END_TPA_SEGS(tpa_end); 1313 if (segs == 1) 1314 return skb; 1315 1316 NAPI_GRO_CB(skb)->count = segs; 1317 skb_shinfo(skb)->gso_size = 1318 le32_to_cpu(tpa_end1->rx_tpa_end_cmp_seg_len); 1319 skb_shinfo(skb)->gso_type = tpa_info->gso_type; 1320 payload_off = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) & 1321 RX_TPA_END_CMP_PAYLOAD_OFFSET) >> 1322 RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT; 1323 skb = bp->gro_func(tpa_info, payload_off, TPA_END_GRO_TS(tpa_end), skb); 1324 if (likely(skb)) 1325 tcp_gro_complete(skb); 1326 #endif 1327 return skb; 1328 } 1329 1330 /* Given the cfa_code of a received packet determine which 1331 * netdev (vf-rep or PF) the packet is destined to. 1332 */ 1333 static struct net_device *bnxt_get_pkt_dev(struct bnxt *bp, u16 cfa_code) 1334 { 1335 struct net_device *dev = bnxt_get_vf_rep(bp, cfa_code); 1336 1337 /* if vf-rep dev is NULL, the must belongs to the PF */ 1338 return dev ? dev : bp->dev; 1339 } 1340 1341 static inline struct sk_buff *bnxt_tpa_end(struct bnxt *bp, 1342 struct bnxt_napi *bnapi, 1343 u32 *raw_cons, 1344 struct rx_tpa_end_cmp *tpa_end, 1345 struct rx_tpa_end_cmp_ext *tpa_end1, 1346 u8 *event) 1347 { 1348 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 1349 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 1350 u8 agg_id = TPA_END_AGG_ID(tpa_end); 1351 u8 *data_ptr, agg_bufs; 1352 u16 cp_cons = RING_CMP(*raw_cons); 1353 unsigned int len; 1354 struct bnxt_tpa_info *tpa_info; 1355 dma_addr_t mapping; 1356 struct sk_buff *skb; 1357 void *data; 1358 1359 if (unlikely(bnapi->in_reset)) { 1360 int rc = bnxt_discard_rx(bp, bnapi, raw_cons, tpa_end); 1361 1362 if (rc < 0) 1363 return ERR_PTR(-EBUSY); 1364 return NULL; 1365 } 1366 1367 tpa_info = &rxr->rx_tpa[agg_id]; 1368 data = tpa_info->data; 1369 data_ptr = tpa_info->data_ptr; 1370 prefetch(data_ptr); 1371 len = tpa_info->len; 1372 mapping = tpa_info->mapping; 1373 1374 agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) & 1375 RX_TPA_END_CMP_AGG_BUFS) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT; 1376 1377 if (agg_bufs) { 1378 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, raw_cons)) 1379 return ERR_PTR(-EBUSY); 1380 1381 *event |= BNXT_AGG_EVENT; 1382 cp_cons = NEXT_CMP(cp_cons); 1383 } 1384 1385 if (unlikely(agg_bufs > MAX_SKB_FRAGS || TPA_END_ERRORS(tpa_end1))) { 1386 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs); 1387 if (agg_bufs > MAX_SKB_FRAGS) 1388 netdev_warn(bp->dev, "TPA frags %d exceeded MAX_SKB_FRAGS %d\n", 1389 agg_bufs, (int)MAX_SKB_FRAGS); 1390 return NULL; 1391 } 1392 1393 if (len <= bp->rx_copy_thresh) { 1394 skb = bnxt_copy_skb(bnapi, data_ptr, len, mapping); 1395 if (!skb) { 1396 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs); 1397 return NULL; 1398 } 1399 } else { 1400 u8 *new_data; 1401 dma_addr_t new_mapping; 1402 1403 new_data = __bnxt_alloc_rx_data(bp, &new_mapping, GFP_ATOMIC); 1404 if (!new_data) { 1405 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs); 1406 return NULL; 1407 } 1408 1409 tpa_info->data = new_data; 1410 tpa_info->data_ptr = new_data + bp->rx_offset; 1411 tpa_info->mapping = new_mapping; 1412 1413 skb = build_skb(data, 0); 1414 dma_unmap_single_attrs(&bp->pdev->dev, mapping, 1415 bp->rx_buf_use_size, bp->rx_dir, 1416 DMA_ATTR_WEAK_ORDERING); 1417 1418 if (!skb) { 1419 kfree(data); 1420 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs); 1421 return NULL; 1422 } 1423 skb_reserve(skb, bp->rx_offset); 1424 skb_put(skb, len); 1425 } 1426 1427 if (agg_bufs) { 1428 skb = bnxt_rx_pages(bp, bnapi, skb, cp_cons, agg_bufs); 1429 if (!skb) { 1430 /* Page reuse already handled by bnxt_rx_pages(). */ 1431 return NULL; 1432 } 1433 } 1434 1435 skb->protocol = 1436 eth_type_trans(skb, bnxt_get_pkt_dev(bp, tpa_info->cfa_code)); 1437 1438 if (tpa_info->hash_type != PKT_HASH_TYPE_NONE) 1439 skb_set_hash(skb, tpa_info->rss_hash, tpa_info->hash_type); 1440 1441 if ((tpa_info->flags2 & RX_CMP_FLAGS2_META_FORMAT_VLAN) && 1442 (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) { 1443 u16 vlan_proto = tpa_info->metadata >> 1444 RX_CMP_FLAGS2_METADATA_TPID_SFT; 1445 u16 vtag = tpa_info->metadata & RX_CMP_FLAGS2_METADATA_TCI_MASK; 1446 1447 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag); 1448 } 1449 1450 skb_checksum_none_assert(skb); 1451 if (likely(tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_L4_CS_CALC)) { 1452 skb->ip_summed = CHECKSUM_UNNECESSARY; 1453 skb->csum_level = 1454 (tpa_info->flags2 & RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3; 1455 } 1456 1457 if (TPA_END_GRO(tpa_end)) 1458 skb = bnxt_gro_skb(bp, tpa_info, tpa_end, tpa_end1, skb); 1459 1460 return skb; 1461 } 1462 1463 static void bnxt_deliver_skb(struct bnxt *bp, struct bnxt_napi *bnapi, 1464 struct sk_buff *skb) 1465 { 1466 if (skb->dev != bp->dev) { 1467 /* this packet belongs to a vf-rep */ 1468 bnxt_vf_rep_rx(bp, skb); 1469 return; 1470 } 1471 skb_record_rx_queue(skb, bnapi->index); 1472 napi_gro_receive(&bnapi->napi, skb); 1473 } 1474 1475 /* returns the following: 1476 * 1 - 1 packet successfully received 1477 * 0 - successful TPA_START, packet not completed yet 1478 * -EBUSY - completion ring does not have all the agg buffers yet 1479 * -ENOMEM - packet aborted due to out of memory 1480 * -EIO - packet aborted due to hw error indicated in BD 1481 */ 1482 static int bnxt_rx_pkt(struct bnxt *bp, struct bnxt_napi *bnapi, u32 *raw_cons, 1483 u8 *event) 1484 { 1485 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 1486 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 1487 struct net_device *dev = bp->dev; 1488 struct rx_cmp *rxcmp; 1489 struct rx_cmp_ext *rxcmp1; 1490 u32 tmp_raw_cons = *raw_cons; 1491 u16 cfa_code, cons, prod, cp_cons = RING_CMP(tmp_raw_cons); 1492 struct bnxt_sw_rx_bd *rx_buf; 1493 unsigned int len; 1494 u8 *data_ptr, agg_bufs, cmp_type; 1495 dma_addr_t dma_addr; 1496 struct sk_buff *skb; 1497 void *data; 1498 int rc = 0; 1499 u32 misc; 1500 1501 rxcmp = (struct rx_cmp *) 1502 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 1503 1504 tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons); 1505 cp_cons = RING_CMP(tmp_raw_cons); 1506 rxcmp1 = (struct rx_cmp_ext *) 1507 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 1508 1509 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons)) 1510 return -EBUSY; 1511 1512 cmp_type = RX_CMP_TYPE(rxcmp); 1513 1514 prod = rxr->rx_prod; 1515 1516 if (cmp_type == CMP_TYPE_RX_L2_TPA_START_CMP) { 1517 bnxt_tpa_start(bp, rxr, (struct rx_tpa_start_cmp *)rxcmp, 1518 (struct rx_tpa_start_cmp_ext *)rxcmp1); 1519 1520 *event |= BNXT_RX_EVENT; 1521 goto next_rx_no_prod_no_len; 1522 1523 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) { 1524 skb = bnxt_tpa_end(bp, bnapi, &tmp_raw_cons, 1525 (struct rx_tpa_end_cmp *)rxcmp, 1526 (struct rx_tpa_end_cmp_ext *)rxcmp1, event); 1527 1528 if (IS_ERR(skb)) 1529 return -EBUSY; 1530 1531 rc = -ENOMEM; 1532 if (likely(skb)) { 1533 bnxt_deliver_skb(bp, bnapi, skb); 1534 rc = 1; 1535 } 1536 *event |= BNXT_RX_EVENT; 1537 goto next_rx_no_prod_no_len; 1538 } 1539 1540 cons = rxcmp->rx_cmp_opaque; 1541 rx_buf = &rxr->rx_buf_ring[cons]; 1542 data = rx_buf->data; 1543 data_ptr = rx_buf->data_ptr; 1544 if (unlikely(cons != rxr->rx_next_cons)) { 1545 int rc1 = bnxt_discard_rx(bp, bnapi, raw_cons, rxcmp); 1546 1547 bnxt_sched_reset(bp, rxr); 1548 return rc1; 1549 } 1550 prefetch(data_ptr); 1551 1552 misc = le32_to_cpu(rxcmp->rx_cmp_misc_v1); 1553 agg_bufs = (misc & RX_CMP_AGG_BUFS) >> RX_CMP_AGG_BUFS_SHIFT; 1554 1555 if (agg_bufs) { 1556 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons)) 1557 return -EBUSY; 1558 1559 cp_cons = NEXT_CMP(cp_cons); 1560 *event |= BNXT_AGG_EVENT; 1561 } 1562 *event |= BNXT_RX_EVENT; 1563 1564 rx_buf->data = NULL; 1565 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L2_ERRORS) { 1566 bnxt_reuse_rx_data(rxr, cons, data); 1567 if (agg_bufs) 1568 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs); 1569 1570 rc = -EIO; 1571 goto next_rx; 1572 } 1573 1574 len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT; 1575 dma_addr = rx_buf->mapping; 1576 1577 if (bnxt_rx_xdp(bp, rxr, cons, data, &data_ptr, &len, event)) { 1578 rc = 1; 1579 goto next_rx; 1580 } 1581 1582 if (len <= bp->rx_copy_thresh) { 1583 skb = bnxt_copy_skb(bnapi, data_ptr, len, dma_addr); 1584 bnxt_reuse_rx_data(rxr, cons, data); 1585 if (!skb) { 1586 rc = -ENOMEM; 1587 goto next_rx; 1588 } 1589 } else { 1590 u32 payload; 1591 1592 if (rx_buf->data_ptr == data_ptr) 1593 payload = misc & RX_CMP_PAYLOAD_OFFSET; 1594 else 1595 payload = 0; 1596 skb = bp->rx_skb_func(bp, rxr, cons, data, data_ptr, dma_addr, 1597 payload | len); 1598 if (!skb) { 1599 rc = -ENOMEM; 1600 goto next_rx; 1601 } 1602 } 1603 1604 if (agg_bufs) { 1605 skb = bnxt_rx_pages(bp, bnapi, skb, cp_cons, agg_bufs); 1606 if (!skb) { 1607 rc = -ENOMEM; 1608 goto next_rx; 1609 } 1610 } 1611 1612 if (RX_CMP_HASH_VALID(rxcmp)) { 1613 u32 hash_type = RX_CMP_HASH_TYPE(rxcmp); 1614 enum pkt_hash_types type = PKT_HASH_TYPE_L4; 1615 1616 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */ 1617 if (hash_type != 1 && hash_type != 3) 1618 type = PKT_HASH_TYPE_L3; 1619 skb_set_hash(skb, le32_to_cpu(rxcmp->rx_cmp_rss_hash), type); 1620 } 1621 1622 cfa_code = RX_CMP_CFA_CODE(rxcmp1); 1623 skb->protocol = eth_type_trans(skb, bnxt_get_pkt_dev(bp, cfa_code)); 1624 1625 if ((rxcmp1->rx_cmp_flags2 & 1626 cpu_to_le32(RX_CMP_FLAGS2_META_FORMAT_VLAN)) && 1627 (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) { 1628 u32 meta_data = le32_to_cpu(rxcmp1->rx_cmp_meta_data); 1629 u16 vtag = meta_data & RX_CMP_FLAGS2_METADATA_TCI_MASK; 1630 u16 vlan_proto = meta_data >> RX_CMP_FLAGS2_METADATA_TPID_SFT; 1631 1632 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag); 1633 } 1634 1635 skb_checksum_none_assert(skb); 1636 if (RX_CMP_L4_CS_OK(rxcmp1)) { 1637 if (dev->features & NETIF_F_RXCSUM) { 1638 skb->ip_summed = CHECKSUM_UNNECESSARY; 1639 skb->csum_level = RX_CMP_ENCAP(rxcmp1); 1640 } 1641 } else { 1642 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS) { 1643 if (dev->features & NETIF_F_RXCSUM) 1644 cpr->rx_l4_csum_errors++; 1645 } 1646 } 1647 1648 bnxt_deliver_skb(bp, bnapi, skb); 1649 rc = 1; 1650 1651 next_rx: 1652 rxr->rx_prod = NEXT_RX(prod); 1653 rxr->rx_next_cons = NEXT_RX(cons); 1654 1655 cpr->rx_packets += 1; 1656 cpr->rx_bytes += len; 1657 1658 next_rx_no_prod_no_len: 1659 *raw_cons = tmp_raw_cons; 1660 1661 return rc; 1662 } 1663 1664 /* In netpoll mode, if we are using a combined completion ring, we need to 1665 * discard the rx packets and recycle the buffers. 1666 */ 1667 static int bnxt_force_rx_discard(struct bnxt *bp, struct bnxt_napi *bnapi, 1668 u32 *raw_cons, u8 *event) 1669 { 1670 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 1671 u32 tmp_raw_cons = *raw_cons; 1672 struct rx_cmp_ext *rxcmp1; 1673 struct rx_cmp *rxcmp; 1674 u16 cp_cons; 1675 u8 cmp_type; 1676 1677 cp_cons = RING_CMP(tmp_raw_cons); 1678 rxcmp = (struct rx_cmp *) 1679 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 1680 1681 tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons); 1682 cp_cons = RING_CMP(tmp_raw_cons); 1683 rxcmp1 = (struct rx_cmp_ext *) 1684 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 1685 1686 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons)) 1687 return -EBUSY; 1688 1689 cmp_type = RX_CMP_TYPE(rxcmp); 1690 if (cmp_type == CMP_TYPE_RX_L2_CMP) { 1691 rxcmp1->rx_cmp_cfa_code_errors_v2 |= 1692 cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR); 1693 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) { 1694 struct rx_tpa_end_cmp_ext *tpa_end1; 1695 1696 tpa_end1 = (struct rx_tpa_end_cmp_ext *)rxcmp1; 1697 tpa_end1->rx_tpa_end_cmp_errors_v2 |= 1698 cpu_to_le32(RX_TPA_END_CMP_ERRORS); 1699 } 1700 return bnxt_rx_pkt(bp, bnapi, raw_cons, event); 1701 } 1702 1703 #define BNXT_GET_EVENT_PORT(data) \ 1704 ((data) & \ 1705 ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK) 1706 1707 static int bnxt_async_event_process(struct bnxt *bp, 1708 struct hwrm_async_event_cmpl *cmpl) 1709 { 1710 u16 event_id = le16_to_cpu(cmpl->event_id); 1711 1712 /* TODO CHIMP_FW: Define event id's for link change, error etc */ 1713 switch (event_id) { 1714 case ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE: { 1715 u32 data1 = le32_to_cpu(cmpl->event_data1); 1716 struct bnxt_link_info *link_info = &bp->link_info; 1717 1718 if (BNXT_VF(bp)) 1719 goto async_event_process_exit; 1720 1721 /* print unsupported speed warning in forced speed mode only */ 1722 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED) && 1723 (data1 & 0x20000)) { 1724 u16 fw_speed = link_info->force_link_speed; 1725 u32 speed = bnxt_fw_to_ethtool_speed(fw_speed); 1726 1727 if (speed != SPEED_UNKNOWN) 1728 netdev_warn(bp->dev, "Link speed %d no longer supported\n", 1729 speed); 1730 } 1731 set_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT, &bp->sp_event); 1732 } 1733 /* fall through */ 1734 case ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE: 1735 set_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event); 1736 break; 1737 case ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD: 1738 set_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event); 1739 break; 1740 case ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED: { 1741 u32 data1 = le32_to_cpu(cmpl->event_data1); 1742 u16 port_id = BNXT_GET_EVENT_PORT(data1); 1743 1744 if (BNXT_VF(bp)) 1745 break; 1746 1747 if (bp->pf.port_id != port_id) 1748 break; 1749 1750 set_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event); 1751 break; 1752 } 1753 case ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE: 1754 if (BNXT_PF(bp)) 1755 goto async_event_process_exit; 1756 set_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event); 1757 break; 1758 default: 1759 goto async_event_process_exit; 1760 } 1761 bnxt_queue_sp_work(bp); 1762 async_event_process_exit: 1763 bnxt_ulp_async_events(bp, cmpl); 1764 return 0; 1765 } 1766 1767 static int bnxt_hwrm_handler(struct bnxt *bp, struct tx_cmp *txcmp) 1768 { 1769 u16 cmpl_type = TX_CMP_TYPE(txcmp), vf_id, seq_id; 1770 struct hwrm_cmpl *h_cmpl = (struct hwrm_cmpl *)txcmp; 1771 struct hwrm_fwd_req_cmpl *fwd_req_cmpl = 1772 (struct hwrm_fwd_req_cmpl *)txcmp; 1773 1774 switch (cmpl_type) { 1775 case CMPL_BASE_TYPE_HWRM_DONE: 1776 seq_id = le16_to_cpu(h_cmpl->sequence_id); 1777 if (seq_id == bp->hwrm_intr_seq_id) 1778 bp->hwrm_intr_seq_id = HWRM_SEQ_ID_INVALID; 1779 else 1780 netdev_err(bp->dev, "Invalid hwrm seq id %d\n", seq_id); 1781 break; 1782 1783 case CMPL_BASE_TYPE_HWRM_FWD_REQ: 1784 vf_id = le16_to_cpu(fwd_req_cmpl->source_id); 1785 1786 if ((vf_id < bp->pf.first_vf_id) || 1787 (vf_id >= bp->pf.first_vf_id + bp->pf.active_vfs)) { 1788 netdev_err(bp->dev, "Msg contains invalid VF id %x\n", 1789 vf_id); 1790 return -EINVAL; 1791 } 1792 1793 set_bit(vf_id - bp->pf.first_vf_id, bp->pf.vf_event_bmap); 1794 set_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event); 1795 bnxt_queue_sp_work(bp); 1796 break; 1797 1798 case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT: 1799 bnxt_async_event_process(bp, 1800 (struct hwrm_async_event_cmpl *)txcmp); 1801 1802 default: 1803 break; 1804 } 1805 1806 return 0; 1807 } 1808 1809 static irqreturn_t bnxt_msix(int irq, void *dev_instance) 1810 { 1811 struct bnxt_napi *bnapi = dev_instance; 1812 struct bnxt *bp = bnapi->bp; 1813 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 1814 u32 cons = RING_CMP(cpr->cp_raw_cons); 1815 1816 cpr->event_ctr++; 1817 prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]); 1818 napi_schedule(&bnapi->napi); 1819 return IRQ_HANDLED; 1820 } 1821 1822 static inline int bnxt_has_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr) 1823 { 1824 u32 raw_cons = cpr->cp_raw_cons; 1825 u16 cons = RING_CMP(raw_cons); 1826 struct tx_cmp *txcmp; 1827 1828 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]; 1829 1830 return TX_CMP_VALID(txcmp, raw_cons); 1831 } 1832 1833 static irqreturn_t bnxt_inta(int irq, void *dev_instance) 1834 { 1835 struct bnxt_napi *bnapi = dev_instance; 1836 struct bnxt *bp = bnapi->bp; 1837 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 1838 u32 cons = RING_CMP(cpr->cp_raw_cons); 1839 u32 int_status; 1840 1841 prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]); 1842 1843 if (!bnxt_has_work(bp, cpr)) { 1844 int_status = readl(bp->bar0 + BNXT_CAG_REG_LEGACY_INT_STATUS); 1845 /* return if erroneous interrupt */ 1846 if (!(int_status & (0x10000 << cpr->cp_ring_struct.fw_ring_id))) 1847 return IRQ_NONE; 1848 } 1849 1850 /* disable ring IRQ */ 1851 BNXT_CP_DB_IRQ_DIS(cpr->cp_doorbell); 1852 1853 /* Return here if interrupt is shared and is disabled. */ 1854 if (unlikely(atomic_read(&bp->intr_sem) != 0)) 1855 return IRQ_HANDLED; 1856 1857 napi_schedule(&bnapi->napi); 1858 return IRQ_HANDLED; 1859 } 1860 1861 static int bnxt_poll_work(struct bnxt *bp, struct bnxt_napi *bnapi, int budget) 1862 { 1863 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 1864 u32 raw_cons = cpr->cp_raw_cons; 1865 u32 cons; 1866 int tx_pkts = 0; 1867 int rx_pkts = 0; 1868 u8 event = 0; 1869 struct tx_cmp *txcmp; 1870 1871 while (1) { 1872 int rc; 1873 1874 cons = RING_CMP(raw_cons); 1875 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]; 1876 1877 if (!TX_CMP_VALID(txcmp, raw_cons)) 1878 break; 1879 1880 /* The valid test of the entry must be done first before 1881 * reading any further. 1882 */ 1883 dma_rmb(); 1884 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_TX_L2_CMP) { 1885 tx_pkts++; 1886 /* return full budget so NAPI will complete. */ 1887 if (unlikely(tx_pkts > bp->tx_wake_thresh)) { 1888 rx_pkts = budget; 1889 raw_cons = NEXT_RAW_CMP(raw_cons); 1890 break; 1891 } 1892 } else if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) { 1893 if (likely(budget)) 1894 rc = bnxt_rx_pkt(bp, bnapi, &raw_cons, &event); 1895 else 1896 rc = bnxt_force_rx_discard(bp, bnapi, &raw_cons, 1897 &event); 1898 if (likely(rc >= 0)) 1899 rx_pkts += rc; 1900 /* Increment rx_pkts when rc is -ENOMEM to count towards 1901 * the NAPI budget. Otherwise, we may potentially loop 1902 * here forever if we consistently cannot allocate 1903 * buffers. 1904 */ 1905 else if (rc == -ENOMEM && budget) 1906 rx_pkts++; 1907 else if (rc == -EBUSY) /* partial completion */ 1908 break; 1909 } else if (unlikely((TX_CMP_TYPE(txcmp) == 1910 CMPL_BASE_TYPE_HWRM_DONE) || 1911 (TX_CMP_TYPE(txcmp) == 1912 CMPL_BASE_TYPE_HWRM_FWD_REQ) || 1913 (TX_CMP_TYPE(txcmp) == 1914 CMPL_BASE_TYPE_HWRM_ASYNC_EVENT))) { 1915 bnxt_hwrm_handler(bp, txcmp); 1916 } 1917 raw_cons = NEXT_RAW_CMP(raw_cons); 1918 1919 if (rx_pkts && rx_pkts == budget) 1920 break; 1921 } 1922 1923 if (event & BNXT_TX_EVENT) { 1924 struct bnxt_tx_ring_info *txr = bnapi->tx_ring; 1925 void __iomem *db = txr->tx_doorbell; 1926 u16 prod = txr->tx_prod; 1927 1928 /* Sync BD data before updating doorbell */ 1929 wmb(); 1930 1931 bnxt_db_write_relaxed(bp, db, DB_KEY_TX | prod); 1932 } 1933 1934 cpr->cp_raw_cons = raw_cons; 1935 /* ACK completion ring before freeing tx ring and producing new 1936 * buffers in rx/agg rings to prevent overflowing the completion 1937 * ring. 1938 */ 1939 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons); 1940 1941 if (tx_pkts) 1942 bnapi->tx_int(bp, bnapi, tx_pkts); 1943 1944 if (event & BNXT_RX_EVENT) { 1945 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 1946 1947 bnxt_db_write(bp, rxr->rx_doorbell, DB_KEY_RX | rxr->rx_prod); 1948 if (event & BNXT_AGG_EVENT) 1949 bnxt_db_write(bp, rxr->rx_agg_doorbell, 1950 DB_KEY_RX | rxr->rx_agg_prod); 1951 } 1952 return rx_pkts; 1953 } 1954 1955 static int bnxt_poll_nitroa0(struct napi_struct *napi, int budget) 1956 { 1957 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi); 1958 struct bnxt *bp = bnapi->bp; 1959 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 1960 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 1961 struct tx_cmp *txcmp; 1962 struct rx_cmp_ext *rxcmp1; 1963 u32 cp_cons, tmp_raw_cons; 1964 u32 raw_cons = cpr->cp_raw_cons; 1965 u32 rx_pkts = 0; 1966 u8 event = 0; 1967 1968 while (1) { 1969 int rc; 1970 1971 cp_cons = RING_CMP(raw_cons); 1972 txcmp = &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 1973 1974 if (!TX_CMP_VALID(txcmp, raw_cons)) 1975 break; 1976 1977 if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) { 1978 tmp_raw_cons = NEXT_RAW_CMP(raw_cons); 1979 cp_cons = RING_CMP(tmp_raw_cons); 1980 rxcmp1 = (struct rx_cmp_ext *) 1981 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 1982 1983 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons)) 1984 break; 1985 1986 /* force an error to recycle the buffer */ 1987 rxcmp1->rx_cmp_cfa_code_errors_v2 |= 1988 cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR); 1989 1990 rc = bnxt_rx_pkt(bp, bnapi, &raw_cons, &event); 1991 if (likely(rc == -EIO) && budget) 1992 rx_pkts++; 1993 else if (rc == -EBUSY) /* partial completion */ 1994 break; 1995 } else if (unlikely(TX_CMP_TYPE(txcmp) == 1996 CMPL_BASE_TYPE_HWRM_DONE)) { 1997 bnxt_hwrm_handler(bp, txcmp); 1998 } else { 1999 netdev_err(bp->dev, 2000 "Invalid completion received on special ring\n"); 2001 } 2002 raw_cons = NEXT_RAW_CMP(raw_cons); 2003 2004 if (rx_pkts == budget) 2005 break; 2006 } 2007 2008 cpr->cp_raw_cons = raw_cons; 2009 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons); 2010 bnxt_db_write(bp, rxr->rx_doorbell, DB_KEY_RX | rxr->rx_prod); 2011 2012 if (event & BNXT_AGG_EVENT) 2013 bnxt_db_write(bp, rxr->rx_agg_doorbell, 2014 DB_KEY_RX | rxr->rx_agg_prod); 2015 2016 if (!bnxt_has_work(bp, cpr) && rx_pkts < budget) { 2017 napi_complete_done(napi, rx_pkts); 2018 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons); 2019 } 2020 return rx_pkts; 2021 } 2022 2023 static int bnxt_poll(struct napi_struct *napi, int budget) 2024 { 2025 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi); 2026 struct bnxt *bp = bnapi->bp; 2027 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 2028 int work_done = 0; 2029 2030 while (1) { 2031 work_done += bnxt_poll_work(bp, bnapi, budget - work_done); 2032 2033 if (work_done >= budget) { 2034 if (!budget) 2035 BNXT_CP_DB_REARM(cpr->cp_doorbell, 2036 cpr->cp_raw_cons); 2037 break; 2038 } 2039 2040 if (!bnxt_has_work(bp, cpr)) { 2041 if (napi_complete_done(napi, work_done)) 2042 BNXT_CP_DB_REARM(cpr->cp_doorbell, 2043 cpr->cp_raw_cons); 2044 break; 2045 } 2046 } 2047 if (bp->flags & BNXT_FLAG_DIM) { 2048 struct net_dim_sample dim_sample; 2049 2050 net_dim_sample(cpr->event_ctr, 2051 cpr->rx_packets, 2052 cpr->rx_bytes, 2053 &dim_sample); 2054 net_dim(&cpr->dim, dim_sample); 2055 } 2056 mmiowb(); 2057 return work_done; 2058 } 2059 2060 static void bnxt_free_tx_skbs(struct bnxt *bp) 2061 { 2062 int i, max_idx; 2063 struct pci_dev *pdev = bp->pdev; 2064 2065 if (!bp->tx_ring) 2066 return; 2067 2068 max_idx = bp->tx_nr_pages * TX_DESC_CNT; 2069 for (i = 0; i < bp->tx_nr_rings; i++) { 2070 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; 2071 int j; 2072 2073 for (j = 0; j < max_idx;) { 2074 struct bnxt_sw_tx_bd *tx_buf = &txr->tx_buf_ring[j]; 2075 struct sk_buff *skb = tx_buf->skb; 2076 int k, last; 2077 2078 if (!skb) { 2079 j++; 2080 continue; 2081 } 2082 2083 tx_buf->skb = NULL; 2084 2085 if (tx_buf->is_push) { 2086 dev_kfree_skb(skb); 2087 j += 2; 2088 continue; 2089 } 2090 2091 dma_unmap_single(&pdev->dev, 2092 dma_unmap_addr(tx_buf, mapping), 2093 skb_headlen(skb), 2094 PCI_DMA_TODEVICE); 2095 2096 last = tx_buf->nr_frags; 2097 j += 2; 2098 for (k = 0; k < last; k++, j++) { 2099 int ring_idx = j & bp->tx_ring_mask; 2100 skb_frag_t *frag = &skb_shinfo(skb)->frags[k]; 2101 2102 tx_buf = &txr->tx_buf_ring[ring_idx]; 2103 dma_unmap_page( 2104 &pdev->dev, 2105 dma_unmap_addr(tx_buf, mapping), 2106 skb_frag_size(frag), PCI_DMA_TODEVICE); 2107 } 2108 dev_kfree_skb(skb); 2109 } 2110 netdev_tx_reset_queue(netdev_get_tx_queue(bp->dev, i)); 2111 } 2112 } 2113 2114 static void bnxt_free_rx_skbs(struct bnxt *bp) 2115 { 2116 int i, max_idx, max_agg_idx; 2117 struct pci_dev *pdev = bp->pdev; 2118 2119 if (!bp->rx_ring) 2120 return; 2121 2122 max_idx = bp->rx_nr_pages * RX_DESC_CNT; 2123 max_agg_idx = bp->rx_agg_nr_pages * RX_DESC_CNT; 2124 for (i = 0; i < bp->rx_nr_rings; i++) { 2125 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 2126 int j; 2127 2128 if (rxr->rx_tpa) { 2129 for (j = 0; j < MAX_TPA; j++) { 2130 struct bnxt_tpa_info *tpa_info = 2131 &rxr->rx_tpa[j]; 2132 u8 *data = tpa_info->data; 2133 2134 if (!data) 2135 continue; 2136 2137 dma_unmap_single_attrs(&pdev->dev, 2138 tpa_info->mapping, 2139 bp->rx_buf_use_size, 2140 bp->rx_dir, 2141 DMA_ATTR_WEAK_ORDERING); 2142 2143 tpa_info->data = NULL; 2144 2145 kfree(data); 2146 } 2147 } 2148 2149 for (j = 0; j < max_idx; j++) { 2150 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[j]; 2151 dma_addr_t mapping = rx_buf->mapping; 2152 void *data = rx_buf->data; 2153 2154 if (!data) 2155 continue; 2156 2157 rx_buf->data = NULL; 2158 2159 if (BNXT_RX_PAGE_MODE(bp)) { 2160 mapping -= bp->rx_dma_offset; 2161 dma_unmap_page_attrs(&pdev->dev, mapping, 2162 PAGE_SIZE, bp->rx_dir, 2163 DMA_ATTR_WEAK_ORDERING); 2164 __free_page(data); 2165 } else { 2166 dma_unmap_single_attrs(&pdev->dev, mapping, 2167 bp->rx_buf_use_size, 2168 bp->rx_dir, 2169 DMA_ATTR_WEAK_ORDERING); 2170 kfree(data); 2171 } 2172 } 2173 2174 for (j = 0; j < max_agg_idx; j++) { 2175 struct bnxt_sw_rx_agg_bd *rx_agg_buf = 2176 &rxr->rx_agg_ring[j]; 2177 struct page *page = rx_agg_buf->page; 2178 2179 if (!page) 2180 continue; 2181 2182 dma_unmap_page_attrs(&pdev->dev, rx_agg_buf->mapping, 2183 BNXT_RX_PAGE_SIZE, 2184 PCI_DMA_FROMDEVICE, 2185 DMA_ATTR_WEAK_ORDERING); 2186 2187 rx_agg_buf->page = NULL; 2188 __clear_bit(j, rxr->rx_agg_bmap); 2189 2190 __free_page(page); 2191 } 2192 if (rxr->rx_page) { 2193 __free_page(rxr->rx_page); 2194 rxr->rx_page = NULL; 2195 } 2196 } 2197 } 2198 2199 static void bnxt_free_skbs(struct bnxt *bp) 2200 { 2201 bnxt_free_tx_skbs(bp); 2202 bnxt_free_rx_skbs(bp); 2203 } 2204 2205 static void bnxt_free_ring(struct bnxt *bp, struct bnxt_ring_struct *ring) 2206 { 2207 struct pci_dev *pdev = bp->pdev; 2208 int i; 2209 2210 for (i = 0; i < ring->nr_pages; i++) { 2211 if (!ring->pg_arr[i]) 2212 continue; 2213 2214 dma_free_coherent(&pdev->dev, ring->page_size, 2215 ring->pg_arr[i], ring->dma_arr[i]); 2216 2217 ring->pg_arr[i] = NULL; 2218 } 2219 if (ring->pg_tbl) { 2220 dma_free_coherent(&pdev->dev, ring->nr_pages * 8, 2221 ring->pg_tbl, ring->pg_tbl_map); 2222 ring->pg_tbl = NULL; 2223 } 2224 if (ring->vmem_size && *ring->vmem) { 2225 vfree(*ring->vmem); 2226 *ring->vmem = NULL; 2227 } 2228 } 2229 2230 static int bnxt_alloc_ring(struct bnxt *bp, struct bnxt_ring_struct *ring) 2231 { 2232 int i; 2233 struct pci_dev *pdev = bp->pdev; 2234 2235 if (ring->nr_pages > 1) { 2236 ring->pg_tbl = dma_alloc_coherent(&pdev->dev, 2237 ring->nr_pages * 8, 2238 &ring->pg_tbl_map, 2239 GFP_KERNEL); 2240 if (!ring->pg_tbl) 2241 return -ENOMEM; 2242 } 2243 2244 for (i = 0; i < ring->nr_pages; i++) { 2245 ring->pg_arr[i] = dma_alloc_coherent(&pdev->dev, 2246 ring->page_size, 2247 &ring->dma_arr[i], 2248 GFP_KERNEL); 2249 if (!ring->pg_arr[i]) 2250 return -ENOMEM; 2251 2252 if (ring->nr_pages > 1) 2253 ring->pg_tbl[i] = cpu_to_le64(ring->dma_arr[i]); 2254 } 2255 2256 if (ring->vmem_size) { 2257 *ring->vmem = vzalloc(ring->vmem_size); 2258 if (!(*ring->vmem)) 2259 return -ENOMEM; 2260 } 2261 return 0; 2262 } 2263 2264 static void bnxt_free_rx_rings(struct bnxt *bp) 2265 { 2266 int i; 2267 2268 if (!bp->rx_ring) 2269 return; 2270 2271 for (i = 0; i < bp->rx_nr_rings; i++) { 2272 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 2273 struct bnxt_ring_struct *ring; 2274 2275 if (rxr->xdp_prog) 2276 bpf_prog_put(rxr->xdp_prog); 2277 2278 if (xdp_rxq_info_is_reg(&rxr->xdp_rxq)) 2279 xdp_rxq_info_unreg(&rxr->xdp_rxq); 2280 2281 kfree(rxr->rx_tpa); 2282 rxr->rx_tpa = NULL; 2283 2284 kfree(rxr->rx_agg_bmap); 2285 rxr->rx_agg_bmap = NULL; 2286 2287 ring = &rxr->rx_ring_struct; 2288 bnxt_free_ring(bp, ring); 2289 2290 ring = &rxr->rx_agg_ring_struct; 2291 bnxt_free_ring(bp, ring); 2292 } 2293 } 2294 2295 static int bnxt_alloc_rx_rings(struct bnxt *bp) 2296 { 2297 int i, rc, agg_rings = 0, tpa_rings = 0; 2298 2299 if (!bp->rx_ring) 2300 return -ENOMEM; 2301 2302 if (bp->flags & BNXT_FLAG_AGG_RINGS) 2303 agg_rings = 1; 2304 2305 if (bp->flags & BNXT_FLAG_TPA) 2306 tpa_rings = 1; 2307 2308 for (i = 0; i < bp->rx_nr_rings; i++) { 2309 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 2310 struct bnxt_ring_struct *ring; 2311 2312 ring = &rxr->rx_ring_struct; 2313 2314 rc = xdp_rxq_info_reg(&rxr->xdp_rxq, bp->dev, i); 2315 if (rc < 0) 2316 return rc; 2317 2318 rc = bnxt_alloc_ring(bp, ring); 2319 if (rc) 2320 return rc; 2321 2322 if (agg_rings) { 2323 u16 mem_size; 2324 2325 ring = &rxr->rx_agg_ring_struct; 2326 rc = bnxt_alloc_ring(bp, ring); 2327 if (rc) 2328 return rc; 2329 2330 ring->grp_idx = i; 2331 rxr->rx_agg_bmap_size = bp->rx_agg_ring_mask + 1; 2332 mem_size = rxr->rx_agg_bmap_size / 8; 2333 rxr->rx_agg_bmap = kzalloc(mem_size, GFP_KERNEL); 2334 if (!rxr->rx_agg_bmap) 2335 return -ENOMEM; 2336 2337 if (tpa_rings) { 2338 rxr->rx_tpa = kcalloc(MAX_TPA, 2339 sizeof(struct bnxt_tpa_info), 2340 GFP_KERNEL); 2341 if (!rxr->rx_tpa) 2342 return -ENOMEM; 2343 } 2344 } 2345 } 2346 return 0; 2347 } 2348 2349 static void bnxt_free_tx_rings(struct bnxt *bp) 2350 { 2351 int i; 2352 struct pci_dev *pdev = bp->pdev; 2353 2354 if (!bp->tx_ring) 2355 return; 2356 2357 for (i = 0; i < bp->tx_nr_rings; i++) { 2358 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; 2359 struct bnxt_ring_struct *ring; 2360 2361 if (txr->tx_push) { 2362 dma_free_coherent(&pdev->dev, bp->tx_push_size, 2363 txr->tx_push, txr->tx_push_mapping); 2364 txr->tx_push = NULL; 2365 } 2366 2367 ring = &txr->tx_ring_struct; 2368 2369 bnxt_free_ring(bp, ring); 2370 } 2371 } 2372 2373 static int bnxt_alloc_tx_rings(struct bnxt *bp) 2374 { 2375 int i, j, rc; 2376 struct pci_dev *pdev = bp->pdev; 2377 2378 bp->tx_push_size = 0; 2379 if (bp->tx_push_thresh) { 2380 int push_size; 2381 2382 push_size = L1_CACHE_ALIGN(sizeof(struct tx_push_bd) + 2383 bp->tx_push_thresh); 2384 2385 if (push_size > 256) { 2386 push_size = 0; 2387 bp->tx_push_thresh = 0; 2388 } 2389 2390 bp->tx_push_size = push_size; 2391 } 2392 2393 for (i = 0, j = 0; i < bp->tx_nr_rings; i++) { 2394 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; 2395 struct bnxt_ring_struct *ring; 2396 u8 qidx; 2397 2398 ring = &txr->tx_ring_struct; 2399 2400 rc = bnxt_alloc_ring(bp, ring); 2401 if (rc) 2402 return rc; 2403 2404 ring->grp_idx = txr->bnapi->index; 2405 if (bp->tx_push_size) { 2406 dma_addr_t mapping; 2407 2408 /* One pre-allocated DMA buffer to backup 2409 * TX push operation 2410 */ 2411 txr->tx_push = dma_alloc_coherent(&pdev->dev, 2412 bp->tx_push_size, 2413 &txr->tx_push_mapping, 2414 GFP_KERNEL); 2415 2416 if (!txr->tx_push) 2417 return -ENOMEM; 2418 2419 mapping = txr->tx_push_mapping + 2420 sizeof(struct tx_push_bd); 2421 txr->data_mapping = cpu_to_le64(mapping); 2422 2423 memset(txr->tx_push, 0, sizeof(struct tx_push_bd)); 2424 } 2425 qidx = bp->tc_to_qidx[j]; 2426 ring->queue_id = bp->q_info[qidx].queue_id; 2427 if (i < bp->tx_nr_rings_xdp) 2428 continue; 2429 if (i % bp->tx_nr_rings_per_tc == (bp->tx_nr_rings_per_tc - 1)) 2430 j++; 2431 } 2432 return 0; 2433 } 2434 2435 static void bnxt_free_cp_rings(struct bnxt *bp) 2436 { 2437 int i; 2438 2439 if (!bp->bnapi) 2440 return; 2441 2442 for (i = 0; i < bp->cp_nr_rings; i++) { 2443 struct bnxt_napi *bnapi = bp->bnapi[i]; 2444 struct bnxt_cp_ring_info *cpr; 2445 struct bnxt_ring_struct *ring; 2446 2447 if (!bnapi) 2448 continue; 2449 2450 cpr = &bnapi->cp_ring; 2451 ring = &cpr->cp_ring_struct; 2452 2453 bnxt_free_ring(bp, ring); 2454 } 2455 } 2456 2457 static int bnxt_alloc_cp_rings(struct bnxt *bp) 2458 { 2459 int i, rc, ulp_base_vec, ulp_msix; 2460 2461 ulp_msix = bnxt_get_ulp_msix_num(bp); 2462 ulp_base_vec = bnxt_get_ulp_msix_base(bp); 2463 for (i = 0; i < bp->cp_nr_rings; i++) { 2464 struct bnxt_napi *bnapi = bp->bnapi[i]; 2465 struct bnxt_cp_ring_info *cpr; 2466 struct bnxt_ring_struct *ring; 2467 2468 if (!bnapi) 2469 continue; 2470 2471 cpr = &bnapi->cp_ring; 2472 ring = &cpr->cp_ring_struct; 2473 2474 rc = bnxt_alloc_ring(bp, ring); 2475 if (rc) 2476 return rc; 2477 2478 if (ulp_msix && i >= ulp_base_vec) 2479 ring->map_idx = i + ulp_msix; 2480 else 2481 ring->map_idx = i; 2482 } 2483 return 0; 2484 } 2485 2486 static void bnxt_init_ring_struct(struct bnxt *bp) 2487 { 2488 int i; 2489 2490 for (i = 0; i < bp->cp_nr_rings; i++) { 2491 struct bnxt_napi *bnapi = bp->bnapi[i]; 2492 struct bnxt_cp_ring_info *cpr; 2493 struct bnxt_rx_ring_info *rxr; 2494 struct bnxt_tx_ring_info *txr; 2495 struct bnxt_ring_struct *ring; 2496 2497 if (!bnapi) 2498 continue; 2499 2500 cpr = &bnapi->cp_ring; 2501 ring = &cpr->cp_ring_struct; 2502 ring->nr_pages = bp->cp_nr_pages; 2503 ring->page_size = HW_CMPD_RING_SIZE; 2504 ring->pg_arr = (void **)cpr->cp_desc_ring; 2505 ring->dma_arr = cpr->cp_desc_mapping; 2506 ring->vmem_size = 0; 2507 2508 rxr = bnapi->rx_ring; 2509 if (!rxr) 2510 goto skip_rx; 2511 2512 ring = &rxr->rx_ring_struct; 2513 ring->nr_pages = bp->rx_nr_pages; 2514 ring->page_size = HW_RXBD_RING_SIZE; 2515 ring->pg_arr = (void **)rxr->rx_desc_ring; 2516 ring->dma_arr = rxr->rx_desc_mapping; 2517 ring->vmem_size = SW_RXBD_RING_SIZE * bp->rx_nr_pages; 2518 ring->vmem = (void **)&rxr->rx_buf_ring; 2519 2520 ring = &rxr->rx_agg_ring_struct; 2521 ring->nr_pages = bp->rx_agg_nr_pages; 2522 ring->page_size = HW_RXBD_RING_SIZE; 2523 ring->pg_arr = (void **)rxr->rx_agg_desc_ring; 2524 ring->dma_arr = rxr->rx_agg_desc_mapping; 2525 ring->vmem_size = SW_RXBD_AGG_RING_SIZE * bp->rx_agg_nr_pages; 2526 ring->vmem = (void **)&rxr->rx_agg_ring; 2527 2528 skip_rx: 2529 txr = bnapi->tx_ring; 2530 if (!txr) 2531 continue; 2532 2533 ring = &txr->tx_ring_struct; 2534 ring->nr_pages = bp->tx_nr_pages; 2535 ring->page_size = HW_RXBD_RING_SIZE; 2536 ring->pg_arr = (void **)txr->tx_desc_ring; 2537 ring->dma_arr = txr->tx_desc_mapping; 2538 ring->vmem_size = SW_TXBD_RING_SIZE * bp->tx_nr_pages; 2539 ring->vmem = (void **)&txr->tx_buf_ring; 2540 } 2541 } 2542 2543 static void bnxt_init_rxbd_pages(struct bnxt_ring_struct *ring, u32 type) 2544 { 2545 int i; 2546 u32 prod; 2547 struct rx_bd **rx_buf_ring; 2548 2549 rx_buf_ring = (struct rx_bd **)ring->pg_arr; 2550 for (i = 0, prod = 0; i < ring->nr_pages; i++) { 2551 int j; 2552 struct rx_bd *rxbd; 2553 2554 rxbd = rx_buf_ring[i]; 2555 if (!rxbd) 2556 continue; 2557 2558 for (j = 0; j < RX_DESC_CNT; j++, rxbd++, prod++) { 2559 rxbd->rx_bd_len_flags_type = cpu_to_le32(type); 2560 rxbd->rx_bd_opaque = prod; 2561 } 2562 } 2563 } 2564 2565 static int bnxt_init_one_rx_ring(struct bnxt *bp, int ring_nr) 2566 { 2567 struct net_device *dev = bp->dev; 2568 struct bnxt_rx_ring_info *rxr; 2569 struct bnxt_ring_struct *ring; 2570 u32 prod, type; 2571 int i; 2572 2573 type = (bp->rx_buf_use_size << RX_BD_LEN_SHIFT) | 2574 RX_BD_TYPE_RX_PACKET_BD | RX_BD_FLAGS_EOP; 2575 2576 if (NET_IP_ALIGN == 2) 2577 type |= RX_BD_FLAGS_SOP; 2578 2579 rxr = &bp->rx_ring[ring_nr]; 2580 ring = &rxr->rx_ring_struct; 2581 bnxt_init_rxbd_pages(ring, type); 2582 2583 if (BNXT_RX_PAGE_MODE(bp) && bp->xdp_prog) { 2584 rxr->xdp_prog = bpf_prog_add(bp->xdp_prog, 1); 2585 if (IS_ERR(rxr->xdp_prog)) { 2586 int rc = PTR_ERR(rxr->xdp_prog); 2587 2588 rxr->xdp_prog = NULL; 2589 return rc; 2590 } 2591 } 2592 prod = rxr->rx_prod; 2593 for (i = 0; i < bp->rx_ring_size; i++) { 2594 if (bnxt_alloc_rx_data(bp, rxr, prod, GFP_KERNEL) != 0) { 2595 netdev_warn(dev, "init'ed rx ring %d with %d/%d skbs only\n", 2596 ring_nr, i, bp->rx_ring_size); 2597 break; 2598 } 2599 prod = NEXT_RX(prod); 2600 } 2601 rxr->rx_prod = prod; 2602 ring->fw_ring_id = INVALID_HW_RING_ID; 2603 2604 ring = &rxr->rx_agg_ring_struct; 2605 ring->fw_ring_id = INVALID_HW_RING_ID; 2606 2607 if (!(bp->flags & BNXT_FLAG_AGG_RINGS)) 2608 return 0; 2609 2610 type = ((u32)BNXT_RX_PAGE_SIZE << RX_BD_LEN_SHIFT) | 2611 RX_BD_TYPE_RX_AGG_BD | RX_BD_FLAGS_SOP; 2612 2613 bnxt_init_rxbd_pages(ring, type); 2614 2615 prod = rxr->rx_agg_prod; 2616 for (i = 0; i < bp->rx_agg_ring_size; i++) { 2617 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_KERNEL) != 0) { 2618 netdev_warn(dev, "init'ed rx ring %d with %d/%d pages only\n", 2619 ring_nr, i, bp->rx_ring_size); 2620 break; 2621 } 2622 prod = NEXT_RX_AGG(prod); 2623 } 2624 rxr->rx_agg_prod = prod; 2625 2626 if (bp->flags & BNXT_FLAG_TPA) { 2627 if (rxr->rx_tpa) { 2628 u8 *data; 2629 dma_addr_t mapping; 2630 2631 for (i = 0; i < MAX_TPA; i++) { 2632 data = __bnxt_alloc_rx_data(bp, &mapping, 2633 GFP_KERNEL); 2634 if (!data) 2635 return -ENOMEM; 2636 2637 rxr->rx_tpa[i].data = data; 2638 rxr->rx_tpa[i].data_ptr = data + bp->rx_offset; 2639 rxr->rx_tpa[i].mapping = mapping; 2640 } 2641 } else { 2642 netdev_err(bp->dev, "No resource allocated for LRO/GRO\n"); 2643 return -ENOMEM; 2644 } 2645 } 2646 2647 return 0; 2648 } 2649 2650 static void bnxt_init_cp_rings(struct bnxt *bp) 2651 { 2652 int i; 2653 2654 for (i = 0; i < bp->cp_nr_rings; i++) { 2655 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring; 2656 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct; 2657 2658 ring->fw_ring_id = INVALID_HW_RING_ID; 2659 cpr->rx_ring_coal.coal_ticks = bp->rx_coal.coal_ticks; 2660 cpr->rx_ring_coal.coal_bufs = bp->rx_coal.coal_bufs; 2661 } 2662 } 2663 2664 static int bnxt_init_rx_rings(struct bnxt *bp) 2665 { 2666 int i, rc = 0; 2667 2668 if (BNXT_RX_PAGE_MODE(bp)) { 2669 bp->rx_offset = NET_IP_ALIGN + XDP_PACKET_HEADROOM; 2670 bp->rx_dma_offset = XDP_PACKET_HEADROOM; 2671 } else { 2672 bp->rx_offset = BNXT_RX_OFFSET; 2673 bp->rx_dma_offset = BNXT_RX_DMA_OFFSET; 2674 } 2675 2676 for (i = 0; i < bp->rx_nr_rings; i++) { 2677 rc = bnxt_init_one_rx_ring(bp, i); 2678 if (rc) 2679 break; 2680 } 2681 2682 return rc; 2683 } 2684 2685 static int bnxt_init_tx_rings(struct bnxt *bp) 2686 { 2687 u16 i; 2688 2689 bp->tx_wake_thresh = max_t(int, bp->tx_ring_size / 2, 2690 MAX_SKB_FRAGS + 1); 2691 2692 for (i = 0; i < bp->tx_nr_rings; i++) { 2693 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; 2694 struct bnxt_ring_struct *ring = &txr->tx_ring_struct; 2695 2696 ring->fw_ring_id = INVALID_HW_RING_ID; 2697 } 2698 2699 return 0; 2700 } 2701 2702 static void bnxt_free_ring_grps(struct bnxt *bp) 2703 { 2704 kfree(bp->grp_info); 2705 bp->grp_info = NULL; 2706 } 2707 2708 static int bnxt_init_ring_grps(struct bnxt *bp, bool irq_re_init) 2709 { 2710 int i; 2711 2712 if (irq_re_init) { 2713 bp->grp_info = kcalloc(bp->cp_nr_rings, 2714 sizeof(struct bnxt_ring_grp_info), 2715 GFP_KERNEL); 2716 if (!bp->grp_info) 2717 return -ENOMEM; 2718 } 2719 for (i = 0; i < bp->cp_nr_rings; i++) { 2720 if (irq_re_init) 2721 bp->grp_info[i].fw_stats_ctx = INVALID_HW_RING_ID; 2722 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID; 2723 bp->grp_info[i].rx_fw_ring_id = INVALID_HW_RING_ID; 2724 bp->grp_info[i].agg_fw_ring_id = INVALID_HW_RING_ID; 2725 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID; 2726 } 2727 return 0; 2728 } 2729 2730 static void bnxt_free_vnics(struct bnxt *bp) 2731 { 2732 kfree(bp->vnic_info); 2733 bp->vnic_info = NULL; 2734 bp->nr_vnics = 0; 2735 } 2736 2737 static int bnxt_alloc_vnics(struct bnxt *bp) 2738 { 2739 int num_vnics = 1; 2740 2741 #ifdef CONFIG_RFS_ACCEL 2742 if (bp->flags & BNXT_FLAG_RFS) 2743 num_vnics += bp->rx_nr_rings; 2744 #endif 2745 2746 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 2747 num_vnics++; 2748 2749 bp->vnic_info = kcalloc(num_vnics, sizeof(struct bnxt_vnic_info), 2750 GFP_KERNEL); 2751 if (!bp->vnic_info) 2752 return -ENOMEM; 2753 2754 bp->nr_vnics = num_vnics; 2755 return 0; 2756 } 2757 2758 static void bnxt_init_vnics(struct bnxt *bp) 2759 { 2760 int i; 2761 2762 for (i = 0; i < bp->nr_vnics; i++) { 2763 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 2764 2765 vnic->fw_vnic_id = INVALID_HW_RING_ID; 2766 vnic->fw_rss_cos_lb_ctx[0] = INVALID_HW_RING_ID; 2767 vnic->fw_rss_cos_lb_ctx[1] = INVALID_HW_RING_ID; 2768 vnic->fw_l2_ctx_id = INVALID_HW_RING_ID; 2769 2770 if (bp->vnic_info[i].rss_hash_key) { 2771 if (i == 0) 2772 prandom_bytes(vnic->rss_hash_key, 2773 HW_HASH_KEY_SIZE); 2774 else 2775 memcpy(vnic->rss_hash_key, 2776 bp->vnic_info[0].rss_hash_key, 2777 HW_HASH_KEY_SIZE); 2778 } 2779 } 2780 } 2781 2782 static int bnxt_calc_nr_ring_pages(u32 ring_size, int desc_per_pg) 2783 { 2784 int pages; 2785 2786 pages = ring_size / desc_per_pg; 2787 2788 if (!pages) 2789 return 1; 2790 2791 pages++; 2792 2793 while (pages & (pages - 1)) 2794 pages++; 2795 2796 return pages; 2797 } 2798 2799 void bnxt_set_tpa_flags(struct bnxt *bp) 2800 { 2801 bp->flags &= ~BNXT_FLAG_TPA; 2802 if (bp->flags & BNXT_FLAG_NO_AGG_RINGS) 2803 return; 2804 if (bp->dev->features & NETIF_F_LRO) 2805 bp->flags |= BNXT_FLAG_LRO; 2806 else if (bp->dev->features & NETIF_F_GRO_HW) 2807 bp->flags |= BNXT_FLAG_GRO; 2808 } 2809 2810 /* bp->rx_ring_size, bp->tx_ring_size, dev->mtu, BNXT_FLAG_{G|L}RO flags must 2811 * be set on entry. 2812 */ 2813 void bnxt_set_ring_params(struct bnxt *bp) 2814 { 2815 u32 ring_size, rx_size, rx_space; 2816 u32 agg_factor = 0, agg_ring_size = 0; 2817 2818 /* 8 for CRC and VLAN */ 2819 rx_size = SKB_DATA_ALIGN(bp->dev->mtu + ETH_HLEN + NET_IP_ALIGN + 8); 2820 2821 rx_space = rx_size + NET_SKB_PAD + 2822 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 2823 2824 bp->rx_copy_thresh = BNXT_RX_COPY_THRESH; 2825 ring_size = bp->rx_ring_size; 2826 bp->rx_agg_ring_size = 0; 2827 bp->rx_agg_nr_pages = 0; 2828 2829 if (bp->flags & BNXT_FLAG_TPA) 2830 agg_factor = min_t(u32, 4, 65536 / BNXT_RX_PAGE_SIZE); 2831 2832 bp->flags &= ~BNXT_FLAG_JUMBO; 2833 if (rx_space > PAGE_SIZE && !(bp->flags & BNXT_FLAG_NO_AGG_RINGS)) { 2834 u32 jumbo_factor; 2835 2836 bp->flags |= BNXT_FLAG_JUMBO; 2837 jumbo_factor = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT; 2838 if (jumbo_factor > agg_factor) 2839 agg_factor = jumbo_factor; 2840 } 2841 agg_ring_size = ring_size * agg_factor; 2842 2843 if (agg_ring_size) { 2844 bp->rx_agg_nr_pages = bnxt_calc_nr_ring_pages(agg_ring_size, 2845 RX_DESC_CNT); 2846 if (bp->rx_agg_nr_pages > MAX_RX_AGG_PAGES) { 2847 u32 tmp = agg_ring_size; 2848 2849 bp->rx_agg_nr_pages = MAX_RX_AGG_PAGES; 2850 agg_ring_size = MAX_RX_AGG_PAGES * RX_DESC_CNT - 1; 2851 netdev_warn(bp->dev, "rx agg ring size %d reduced to %d.\n", 2852 tmp, agg_ring_size); 2853 } 2854 bp->rx_agg_ring_size = agg_ring_size; 2855 bp->rx_agg_ring_mask = (bp->rx_agg_nr_pages * RX_DESC_CNT) - 1; 2856 rx_size = SKB_DATA_ALIGN(BNXT_RX_COPY_THRESH + NET_IP_ALIGN); 2857 rx_space = rx_size + NET_SKB_PAD + 2858 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 2859 } 2860 2861 bp->rx_buf_use_size = rx_size; 2862 bp->rx_buf_size = rx_space; 2863 2864 bp->rx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, RX_DESC_CNT); 2865 bp->rx_ring_mask = (bp->rx_nr_pages * RX_DESC_CNT) - 1; 2866 2867 ring_size = bp->tx_ring_size; 2868 bp->tx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, TX_DESC_CNT); 2869 bp->tx_ring_mask = (bp->tx_nr_pages * TX_DESC_CNT) - 1; 2870 2871 ring_size = bp->rx_ring_size * (2 + agg_factor) + bp->tx_ring_size; 2872 bp->cp_ring_size = ring_size; 2873 2874 bp->cp_nr_pages = bnxt_calc_nr_ring_pages(ring_size, CP_DESC_CNT); 2875 if (bp->cp_nr_pages > MAX_CP_PAGES) { 2876 bp->cp_nr_pages = MAX_CP_PAGES; 2877 bp->cp_ring_size = MAX_CP_PAGES * CP_DESC_CNT - 1; 2878 netdev_warn(bp->dev, "completion ring size %d reduced to %d.\n", 2879 ring_size, bp->cp_ring_size); 2880 } 2881 bp->cp_bit = bp->cp_nr_pages * CP_DESC_CNT; 2882 bp->cp_ring_mask = bp->cp_bit - 1; 2883 } 2884 2885 /* Changing allocation mode of RX rings. 2886 * TODO: Update when extending xdp_rxq_info to support allocation modes. 2887 */ 2888 int bnxt_set_rx_skb_mode(struct bnxt *bp, bool page_mode) 2889 { 2890 if (page_mode) { 2891 if (bp->dev->mtu > BNXT_MAX_PAGE_MODE_MTU) 2892 return -EOPNOTSUPP; 2893 bp->dev->max_mtu = 2894 min_t(u16, bp->max_mtu, BNXT_MAX_PAGE_MODE_MTU); 2895 bp->flags &= ~BNXT_FLAG_AGG_RINGS; 2896 bp->flags |= BNXT_FLAG_NO_AGG_RINGS | BNXT_FLAG_RX_PAGE_MODE; 2897 bp->rx_dir = DMA_BIDIRECTIONAL; 2898 bp->rx_skb_func = bnxt_rx_page_skb; 2899 /* Disable LRO or GRO_HW */ 2900 netdev_update_features(bp->dev); 2901 } else { 2902 bp->dev->max_mtu = bp->max_mtu; 2903 bp->flags &= ~BNXT_FLAG_RX_PAGE_MODE; 2904 bp->rx_dir = DMA_FROM_DEVICE; 2905 bp->rx_skb_func = bnxt_rx_skb; 2906 } 2907 return 0; 2908 } 2909 2910 static void bnxt_free_vnic_attributes(struct bnxt *bp) 2911 { 2912 int i; 2913 struct bnxt_vnic_info *vnic; 2914 struct pci_dev *pdev = bp->pdev; 2915 2916 if (!bp->vnic_info) 2917 return; 2918 2919 for (i = 0; i < bp->nr_vnics; i++) { 2920 vnic = &bp->vnic_info[i]; 2921 2922 kfree(vnic->fw_grp_ids); 2923 vnic->fw_grp_ids = NULL; 2924 2925 kfree(vnic->uc_list); 2926 vnic->uc_list = NULL; 2927 2928 if (vnic->mc_list) { 2929 dma_free_coherent(&pdev->dev, vnic->mc_list_size, 2930 vnic->mc_list, vnic->mc_list_mapping); 2931 vnic->mc_list = NULL; 2932 } 2933 2934 if (vnic->rss_table) { 2935 dma_free_coherent(&pdev->dev, PAGE_SIZE, 2936 vnic->rss_table, 2937 vnic->rss_table_dma_addr); 2938 vnic->rss_table = NULL; 2939 } 2940 2941 vnic->rss_hash_key = NULL; 2942 vnic->flags = 0; 2943 } 2944 } 2945 2946 static int bnxt_alloc_vnic_attributes(struct bnxt *bp) 2947 { 2948 int i, rc = 0, size; 2949 struct bnxt_vnic_info *vnic; 2950 struct pci_dev *pdev = bp->pdev; 2951 int max_rings; 2952 2953 for (i = 0; i < bp->nr_vnics; i++) { 2954 vnic = &bp->vnic_info[i]; 2955 2956 if (vnic->flags & BNXT_VNIC_UCAST_FLAG) { 2957 int mem_size = (BNXT_MAX_UC_ADDRS - 1) * ETH_ALEN; 2958 2959 if (mem_size > 0) { 2960 vnic->uc_list = kmalloc(mem_size, GFP_KERNEL); 2961 if (!vnic->uc_list) { 2962 rc = -ENOMEM; 2963 goto out; 2964 } 2965 } 2966 } 2967 2968 if (vnic->flags & BNXT_VNIC_MCAST_FLAG) { 2969 vnic->mc_list_size = BNXT_MAX_MC_ADDRS * ETH_ALEN; 2970 vnic->mc_list = 2971 dma_alloc_coherent(&pdev->dev, 2972 vnic->mc_list_size, 2973 &vnic->mc_list_mapping, 2974 GFP_KERNEL); 2975 if (!vnic->mc_list) { 2976 rc = -ENOMEM; 2977 goto out; 2978 } 2979 } 2980 2981 if (vnic->flags & BNXT_VNIC_RSS_FLAG) 2982 max_rings = bp->rx_nr_rings; 2983 else 2984 max_rings = 1; 2985 2986 vnic->fw_grp_ids = kcalloc(max_rings, sizeof(u16), GFP_KERNEL); 2987 if (!vnic->fw_grp_ids) { 2988 rc = -ENOMEM; 2989 goto out; 2990 } 2991 2992 if ((bp->flags & BNXT_FLAG_NEW_RSS_CAP) && 2993 !(vnic->flags & BNXT_VNIC_RSS_FLAG)) 2994 continue; 2995 2996 /* Allocate rss table and hash key */ 2997 vnic->rss_table = dma_alloc_coherent(&pdev->dev, PAGE_SIZE, 2998 &vnic->rss_table_dma_addr, 2999 GFP_KERNEL); 3000 if (!vnic->rss_table) { 3001 rc = -ENOMEM; 3002 goto out; 3003 } 3004 3005 size = L1_CACHE_ALIGN(HW_HASH_INDEX_SIZE * sizeof(u16)); 3006 3007 vnic->rss_hash_key = ((void *)vnic->rss_table) + size; 3008 vnic->rss_hash_key_dma_addr = vnic->rss_table_dma_addr + size; 3009 } 3010 return 0; 3011 3012 out: 3013 return rc; 3014 } 3015 3016 static void bnxt_free_hwrm_resources(struct bnxt *bp) 3017 { 3018 struct pci_dev *pdev = bp->pdev; 3019 3020 if (bp->hwrm_cmd_resp_addr) { 3021 dma_free_coherent(&pdev->dev, PAGE_SIZE, bp->hwrm_cmd_resp_addr, 3022 bp->hwrm_cmd_resp_dma_addr); 3023 bp->hwrm_cmd_resp_addr = NULL; 3024 } 3025 } 3026 3027 static int bnxt_alloc_hwrm_resources(struct bnxt *bp) 3028 { 3029 struct pci_dev *pdev = bp->pdev; 3030 3031 bp->hwrm_cmd_resp_addr = dma_alloc_coherent(&pdev->dev, PAGE_SIZE, 3032 &bp->hwrm_cmd_resp_dma_addr, 3033 GFP_KERNEL); 3034 if (!bp->hwrm_cmd_resp_addr) 3035 return -ENOMEM; 3036 3037 return 0; 3038 } 3039 3040 static void bnxt_free_hwrm_short_cmd_req(struct bnxt *bp) 3041 { 3042 if (bp->hwrm_short_cmd_req_addr) { 3043 struct pci_dev *pdev = bp->pdev; 3044 3045 dma_free_coherent(&pdev->dev, BNXT_HWRM_MAX_REQ_LEN, 3046 bp->hwrm_short_cmd_req_addr, 3047 bp->hwrm_short_cmd_req_dma_addr); 3048 bp->hwrm_short_cmd_req_addr = NULL; 3049 } 3050 } 3051 3052 static int bnxt_alloc_hwrm_short_cmd_req(struct bnxt *bp) 3053 { 3054 struct pci_dev *pdev = bp->pdev; 3055 3056 bp->hwrm_short_cmd_req_addr = 3057 dma_alloc_coherent(&pdev->dev, BNXT_HWRM_MAX_REQ_LEN, 3058 &bp->hwrm_short_cmd_req_dma_addr, 3059 GFP_KERNEL); 3060 if (!bp->hwrm_short_cmd_req_addr) 3061 return -ENOMEM; 3062 3063 return 0; 3064 } 3065 3066 static void bnxt_free_stats(struct bnxt *bp) 3067 { 3068 u32 size, i; 3069 struct pci_dev *pdev = bp->pdev; 3070 3071 bp->flags &= ~BNXT_FLAG_PORT_STATS; 3072 bp->flags &= ~BNXT_FLAG_PORT_STATS_EXT; 3073 3074 if (bp->hw_rx_port_stats) { 3075 dma_free_coherent(&pdev->dev, bp->hw_port_stats_size, 3076 bp->hw_rx_port_stats, 3077 bp->hw_rx_port_stats_map); 3078 bp->hw_rx_port_stats = NULL; 3079 } 3080 3081 if (bp->hw_rx_port_stats_ext) { 3082 dma_free_coherent(&pdev->dev, sizeof(struct rx_port_stats_ext), 3083 bp->hw_rx_port_stats_ext, 3084 bp->hw_rx_port_stats_ext_map); 3085 bp->hw_rx_port_stats_ext = NULL; 3086 } 3087 3088 if (!bp->bnapi) 3089 return; 3090 3091 size = sizeof(struct ctx_hw_stats); 3092 3093 for (i = 0; i < bp->cp_nr_rings; i++) { 3094 struct bnxt_napi *bnapi = bp->bnapi[i]; 3095 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 3096 3097 if (cpr->hw_stats) { 3098 dma_free_coherent(&pdev->dev, size, cpr->hw_stats, 3099 cpr->hw_stats_map); 3100 cpr->hw_stats = NULL; 3101 } 3102 } 3103 } 3104 3105 static int bnxt_alloc_stats(struct bnxt *bp) 3106 { 3107 u32 size, i; 3108 struct pci_dev *pdev = bp->pdev; 3109 3110 size = sizeof(struct ctx_hw_stats); 3111 3112 for (i = 0; i < bp->cp_nr_rings; i++) { 3113 struct bnxt_napi *bnapi = bp->bnapi[i]; 3114 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 3115 3116 cpr->hw_stats = dma_alloc_coherent(&pdev->dev, size, 3117 &cpr->hw_stats_map, 3118 GFP_KERNEL); 3119 if (!cpr->hw_stats) 3120 return -ENOMEM; 3121 3122 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID; 3123 } 3124 3125 if (BNXT_PF(bp) && bp->chip_num != CHIP_NUM_58700) { 3126 bp->hw_port_stats_size = sizeof(struct rx_port_stats) + 3127 sizeof(struct tx_port_stats) + 1024; 3128 3129 bp->hw_rx_port_stats = 3130 dma_alloc_coherent(&pdev->dev, bp->hw_port_stats_size, 3131 &bp->hw_rx_port_stats_map, 3132 GFP_KERNEL); 3133 if (!bp->hw_rx_port_stats) 3134 return -ENOMEM; 3135 3136 bp->hw_tx_port_stats = (void *)(bp->hw_rx_port_stats + 1) + 3137 512; 3138 bp->hw_tx_port_stats_map = bp->hw_rx_port_stats_map + 3139 sizeof(struct rx_port_stats) + 512; 3140 bp->flags |= BNXT_FLAG_PORT_STATS; 3141 3142 /* Display extended statistics only if FW supports it */ 3143 if (bp->hwrm_spec_code < 0x10804 || 3144 bp->hwrm_spec_code == 0x10900) 3145 return 0; 3146 3147 bp->hw_rx_port_stats_ext = 3148 dma_zalloc_coherent(&pdev->dev, 3149 sizeof(struct rx_port_stats_ext), 3150 &bp->hw_rx_port_stats_ext_map, 3151 GFP_KERNEL); 3152 if (!bp->hw_rx_port_stats_ext) 3153 return 0; 3154 3155 bp->flags |= BNXT_FLAG_PORT_STATS_EXT; 3156 } 3157 return 0; 3158 } 3159 3160 static void bnxt_clear_ring_indices(struct bnxt *bp) 3161 { 3162 int i; 3163 3164 if (!bp->bnapi) 3165 return; 3166 3167 for (i = 0; i < bp->cp_nr_rings; i++) { 3168 struct bnxt_napi *bnapi = bp->bnapi[i]; 3169 struct bnxt_cp_ring_info *cpr; 3170 struct bnxt_rx_ring_info *rxr; 3171 struct bnxt_tx_ring_info *txr; 3172 3173 if (!bnapi) 3174 continue; 3175 3176 cpr = &bnapi->cp_ring; 3177 cpr->cp_raw_cons = 0; 3178 3179 txr = bnapi->tx_ring; 3180 if (txr) { 3181 txr->tx_prod = 0; 3182 txr->tx_cons = 0; 3183 } 3184 3185 rxr = bnapi->rx_ring; 3186 if (rxr) { 3187 rxr->rx_prod = 0; 3188 rxr->rx_agg_prod = 0; 3189 rxr->rx_sw_agg_prod = 0; 3190 rxr->rx_next_cons = 0; 3191 } 3192 } 3193 } 3194 3195 static void bnxt_free_ntp_fltrs(struct bnxt *bp, bool irq_reinit) 3196 { 3197 #ifdef CONFIG_RFS_ACCEL 3198 int i; 3199 3200 /* Under rtnl_lock and all our NAPIs have been disabled. It's 3201 * safe to delete the hash table. 3202 */ 3203 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) { 3204 struct hlist_head *head; 3205 struct hlist_node *tmp; 3206 struct bnxt_ntuple_filter *fltr; 3207 3208 head = &bp->ntp_fltr_hash_tbl[i]; 3209 hlist_for_each_entry_safe(fltr, tmp, head, hash) { 3210 hlist_del(&fltr->hash); 3211 kfree(fltr); 3212 } 3213 } 3214 if (irq_reinit) { 3215 kfree(bp->ntp_fltr_bmap); 3216 bp->ntp_fltr_bmap = NULL; 3217 } 3218 bp->ntp_fltr_count = 0; 3219 #endif 3220 } 3221 3222 static int bnxt_alloc_ntp_fltrs(struct bnxt *bp) 3223 { 3224 #ifdef CONFIG_RFS_ACCEL 3225 int i, rc = 0; 3226 3227 if (!(bp->flags & BNXT_FLAG_RFS)) 3228 return 0; 3229 3230 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) 3231 INIT_HLIST_HEAD(&bp->ntp_fltr_hash_tbl[i]); 3232 3233 bp->ntp_fltr_count = 0; 3234 bp->ntp_fltr_bmap = kcalloc(BITS_TO_LONGS(BNXT_NTP_FLTR_MAX_FLTR), 3235 sizeof(long), 3236 GFP_KERNEL); 3237 3238 if (!bp->ntp_fltr_bmap) 3239 rc = -ENOMEM; 3240 3241 return rc; 3242 #else 3243 return 0; 3244 #endif 3245 } 3246 3247 static void bnxt_free_mem(struct bnxt *bp, bool irq_re_init) 3248 { 3249 bnxt_free_vnic_attributes(bp); 3250 bnxt_free_tx_rings(bp); 3251 bnxt_free_rx_rings(bp); 3252 bnxt_free_cp_rings(bp); 3253 bnxt_free_ntp_fltrs(bp, irq_re_init); 3254 if (irq_re_init) { 3255 bnxt_free_stats(bp); 3256 bnxt_free_ring_grps(bp); 3257 bnxt_free_vnics(bp); 3258 kfree(bp->tx_ring_map); 3259 bp->tx_ring_map = NULL; 3260 kfree(bp->tx_ring); 3261 bp->tx_ring = NULL; 3262 kfree(bp->rx_ring); 3263 bp->rx_ring = NULL; 3264 kfree(bp->bnapi); 3265 bp->bnapi = NULL; 3266 } else { 3267 bnxt_clear_ring_indices(bp); 3268 } 3269 } 3270 3271 static int bnxt_alloc_mem(struct bnxt *bp, bool irq_re_init) 3272 { 3273 int i, j, rc, size, arr_size; 3274 void *bnapi; 3275 3276 if (irq_re_init) { 3277 /* Allocate bnapi mem pointer array and mem block for 3278 * all queues 3279 */ 3280 arr_size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi *) * 3281 bp->cp_nr_rings); 3282 size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi)); 3283 bnapi = kzalloc(arr_size + size * bp->cp_nr_rings, GFP_KERNEL); 3284 if (!bnapi) 3285 return -ENOMEM; 3286 3287 bp->bnapi = bnapi; 3288 bnapi += arr_size; 3289 for (i = 0; i < bp->cp_nr_rings; i++, bnapi += size) { 3290 bp->bnapi[i] = bnapi; 3291 bp->bnapi[i]->index = i; 3292 bp->bnapi[i]->bp = bp; 3293 } 3294 3295 bp->rx_ring = kcalloc(bp->rx_nr_rings, 3296 sizeof(struct bnxt_rx_ring_info), 3297 GFP_KERNEL); 3298 if (!bp->rx_ring) 3299 return -ENOMEM; 3300 3301 for (i = 0; i < bp->rx_nr_rings; i++) { 3302 bp->rx_ring[i].bnapi = bp->bnapi[i]; 3303 bp->bnapi[i]->rx_ring = &bp->rx_ring[i]; 3304 } 3305 3306 bp->tx_ring = kcalloc(bp->tx_nr_rings, 3307 sizeof(struct bnxt_tx_ring_info), 3308 GFP_KERNEL); 3309 if (!bp->tx_ring) 3310 return -ENOMEM; 3311 3312 bp->tx_ring_map = kcalloc(bp->tx_nr_rings, sizeof(u16), 3313 GFP_KERNEL); 3314 3315 if (!bp->tx_ring_map) 3316 return -ENOMEM; 3317 3318 if (bp->flags & BNXT_FLAG_SHARED_RINGS) 3319 j = 0; 3320 else 3321 j = bp->rx_nr_rings; 3322 3323 for (i = 0; i < bp->tx_nr_rings; i++, j++) { 3324 bp->tx_ring[i].bnapi = bp->bnapi[j]; 3325 bp->bnapi[j]->tx_ring = &bp->tx_ring[i]; 3326 bp->tx_ring_map[i] = bp->tx_nr_rings_xdp + i; 3327 if (i >= bp->tx_nr_rings_xdp) { 3328 bp->tx_ring[i].txq_index = i - 3329 bp->tx_nr_rings_xdp; 3330 bp->bnapi[j]->tx_int = bnxt_tx_int; 3331 } else { 3332 bp->bnapi[j]->flags |= BNXT_NAPI_FLAG_XDP; 3333 bp->bnapi[j]->tx_int = bnxt_tx_int_xdp; 3334 } 3335 } 3336 3337 rc = bnxt_alloc_stats(bp); 3338 if (rc) 3339 goto alloc_mem_err; 3340 3341 rc = bnxt_alloc_ntp_fltrs(bp); 3342 if (rc) 3343 goto alloc_mem_err; 3344 3345 rc = bnxt_alloc_vnics(bp); 3346 if (rc) 3347 goto alloc_mem_err; 3348 } 3349 3350 bnxt_init_ring_struct(bp); 3351 3352 rc = bnxt_alloc_rx_rings(bp); 3353 if (rc) 3354 goto alloc_mem_err; 3355 3356 rc = bnxt_alloc_tx_rings(bp); 3357 if (rc) 3358 goto alloc_mem_err; 3359 3360 rc = bnxt_alloc_cp_rings(bp); 3361 if (rc) 3362 goto alloc_mem_err; 3363 3364 bp->vnic_info[0].flags |= BNXT_VNIC_RSS_FLAG | BNXT_VNIC_MCAST_FLAG | 3365 BNXT_VNIC_UCAST_FLAG; 3366 rc = bnxt_alloc_vnic_attributes(bp); 3367 if (rc) 3368 goto alloc_mem_err; 3369 return 0; 3370 3371 alloc_mem_err: 3372 bnxt_free_mem(bp, true); 3373 return rc; 3374 } 3375 3376 static void bnxt_disable_int(struct bnxt *bp) 3377 { 3378 int i; 3379 3380 if (!bp->bnapi) 3381 return; 3382 3383 for (i = 0; i < bp->cp_nr_rings; i++) { 3384 struct bnxt_napi *bnapi = bp->bnapi[i]; 3385 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 3386 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct; 3387 3388 if (ring->fw_ring_id != INVALID_HW_RING_ID) 3389 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons); 3390 } 3391 } 3392 3393 static int bnxt_cp_num_to_irq_num(struct bnxt *bp, int n) 3394 { 3395 struct bnxt_napi *bnapi = bp->bnapi[n]; 3396 struct bnxt_cp_ring_info *cpr; 3397 3398 cpr = &bnapi->cp_ring; 3399 return cpr->cp_ring_struct.map_idx; 3400 } 3401 3402 static void bnxt_disable_int_sync(struct bnxt *bp) 3403 { 3404 int i; 3405 3406 atomic_inc(&bp->intr_sem); 3407 3408 bnxt_disable_int(bp); 3409 for (i = 0; i < bp->cp_nr_rings; i++) { 3410 int map_idx = bnxt_cp_num_to_irq_num(bp, i); 3411 3412 synchronize_irq(bp->irq_tbl[map_idx].vector); 3413 } 3414 } 3415 3416 static void bnxt_enable_int(struct bnxt *bp) 3417 { 3418 int i; 3419 3420 atomic_set(&bp->intr_sem, 0); 3421 for (i = 0; i < bp->cp_nr_rings; i++) { 3422 struct bnxt_napi *bnapi = bp->bnapi[i]; 3423 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 3424 3425 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons); 3426 } 3427 } 3428 3429 void bnxt_hwrm_cmd_hdr_init(struct bnxt *bp, void *request, u16 req_type, 3430 u16 cmpl_ring, u16 target_id) 3431 { 3432 struct input *req = request; 3433 3434 req->req_type = cpu_to_le16(req_type); 3435 req->cmpl_ring = cpu_to_le16(cmpl_ring); 3436 req->target_id = cpu_to_le16(target_id); 3437 req->resp_addr = cpu_to_le64(bp->hwrm_cmd_resp_dma_addr); 3438 } 3439 3440 static int bnxt_hwrm_do_send_msg(struct bnxt *bp, void *msg, u32 msg_len, 3441 int timeout, bool silent) 3442 { 3443 int i, intr_process, rc, tmo_count; 3444 struct input *req = msg; 3445 u32 *data = msg; 3446 __le32 *resp_len; 3447 u8 *valid; 3448 u16 cp_ring_id, len = 0; 3449 struct hwrm_err_output *resp = bp->hwrm_cmd_resp_addr; 3450 u16 max_req_len = BNXT_HWRM_MAX_REQ_LEN; 3451 struct hwrm_short_input short_input = {0}; 3452 3453 req->seq_id = cpu_to_le16(bp->hwrm_cmd_seq++); 3454 memset(resp, 0, PAGE_SIZE); 3455 cp_ring_id = le16_to_cpu(req->cmpl_ring); 3456 intr_process = (cp_ring_id == INVALID_HW_RING_ID) ? 0 : 1; 3457 3458 if (bp->fw_cap & BNXT_FW_CAP_SHORT_CMD) { 3459 void *short_cmd_req = bp->hwrm_short_cmd_req_addr; 3460 3461 memcpy(short_cmd_req, req, msg_len); 3462 memset(short_cmd_req + msg_len, 0, BNXT_HWRM_MAX_REQ_LEN - 3463 msg_len); 3464 3465 short_input.req_type = req->req_type; 3466 short_input.signature = 3467 cpu_to_le16(SHORT_REQ_SIGNATURE_SHORT_CMD); 3468 short_input.size = cpu_to_le16(msg_len); 3469 short_input.req_addr = 3470 cpu_to_le64(bp->hwrm_short_cmd_req_dma_addr); 3471 3472 data = (u32 *)&short_input; 3473 msg_len = sizeof(short_input); 3474 3475 /* Sync memory write before updating doorbell */ 3476 wmb(); 3477 3478 max_req_len = BNXT_HWRM_SHORT_REQ_LEN; 3479 } 3480 3481 /* Write request msg to hwrm channel */ 3482 __iowrite32_copy(bp->bar0, data, msg_len / 4); 3483 3484 for (i = msg_len; i < max_req_len; i += 4) 3485 writel(0, bp->bar0 + i); 3486 3487 /* currently supports only one outstanding message */ 3488 if (intr_process) 3489 bp->hwrm_intr_seq_id = le16_to_cpu(req->seq_id); 3490 3491 /* Ring channel doorbell */ 3492 writel(1, bp->bar0 + 0x100); 3493 3494 if (!timeout) 3495 timeout = DFLT_HWRM_CMD_TIMEOUT; 3496 /* convert timeout to usec */ 3497 timeout *= 1000; 3498 3499 i = 0; 3500 /* Short timeout for the first few iterations: 3501 * number of loops = number of loops for short timeout + 3502 * number of loops for standard timeout. 3503 */ 3504 tmo_count = HWRM_SHORT_TIMEOUT_COUNTER; 3505 timeout = timeout - HWRM_SHORT_MIN_TIMEOUT * HWRM_SHORT_TIMEOUT_COUNTER; 3506 tmo_count += DIV_ROUND_UP(timeout, HWRM_MIN_TIMEOUT); 3507 resp_len = bp->hwrm_cmd_resp_addr + HWRM_RESP_LEN_OFFSET; 3508 if (intr_process) { 3509 /* Wait until hwrm response cmpl interrupt is processed */ 3510 while (bp->hwrm_intr_seq_id != HWRM_SEQ_ID_INVALID && 3511 i++ < tmo_count) { 3512 /* on first few passes, just barely sleep */ 3513 if (i < HWRM_SHORT_TIMEOUT_COUNTER) 3514 usleep_range(HWRM_SHORT_MIN_TIMEOUT, 3515 HWRM_SHORT_MAX_TIMEOUT); 3516 else 3517 usleep_range(HWRM_MIN_TIMEOUT, 3518 HWRM_MAX_TIMEOUT); 3519 } 3520 3521 if (bp->hwrm_intr_seq_id != HWRM_SEQ_ID_INVALID) { 3522 netdev_err(bp->dev, "Resp cmpl intr err msg: 0x%x\n", 3523 le16_to_cpu(req->req_type)); 3524 return -1; 3525 } 3526 len = (le32_to_cpu(*resp_len) & HWRM_RESP_LEN_MASK) >> 3527 HWRM_RESP_LEN_SFT; 3528 valid = bp->hwrm_cmd_resp_addr + len - 1; 3529 } else { 3530 int j; 3531 3532 /* Check if response len is updated */ 3533 for (i = 0; i < tmo_count; i++) { 3534 len = (le32_to_cpu(*resp_len) & HWRM_RESP_LEN_MASK) >> 3535 HWRM_RESP_LEN_SFT; 3536 if (len) 3537 break; 3538 /* on first few passes, just barely sleep */ 3539 if (i < DFLT_HWRM_CMD_TIMEOUT) 3540 usleep_range(HWRM_SHORT_MIN_TIMEOUT, 3541 HWRM_SHORT_MAX_TIMEOUT); 3542 else 3543 usleep_range(HWRM_MIN_TIMEOUT, 3544 HWRM_MAX_TIMEOUT); 3545 } 3546 3547 if (i >= tmo_count) { 3548 netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d\n", 3549 HWRM_TOTAL_TIMEOUT(i), 3550 le16_to_cpu(req->req_type), 3551 le16_to_cpu(req->seq_id), len); 3552 return -1; 3553 } 3554 3555 /* Last byte of resp contains valid bit */ 3556 valid = bp->hwrm_cmd_resp_addr + len - 1; 3557 for (j = 0; j < HWRM_VALID_BIT_DELAY_USEC; j++) { 3558 /* make sure we read from updated DMA memory */ 3559 dma_rmb(); 3560 if (*valid) 3561 break; 3562 udelay(1); 3563 } 3564 3565 if (j >= HWRM_VALID_BIT_DELAY_USEC) { 3566 netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d v:%d\n", 3567 HWRM_TOTAL_TIMEOUT(i), 3568 le16_to_cpu(req->req_type), 3569 le16_to_cpu(req->seq_id), len, *valid); 3570 return -1; 3571 } 3572 } 3573 3574 /* Zero valid bit for compatibility. Valid bit in an older spec 3575 * may become a new field in a newer spec. We must make sure that 3576 * a new field not implemented by old spec will read zero. 3577 */ 3578 *valid = 0; 3579 rc = le16_to_cpu(resp->error_code); 3580 if (rc && !silent) 3581 netdev_err(bp->dev, "hwrm req_type 0x%x seq id 0x%x error 0x%x\n", 3582 le16_to_cpu(resp->req_type), 3583 le16_to_cpu(resp->seq_id), rc); 3584 return rc; 3585 } 3586 3587 int _hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout) 3588 { 3589 return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, false); 3590 } 3591 3592 int _hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len, 3593 int timeout) 3594 { 3595 return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true); 3596 } 3597 3598 int hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout) 3599 { 3600 int rc; 3601 3602 mutex_lock(&bp->hwrm_cmd_lock); 3603 rc = _hwrm_send_message(bp, msg, msg_len, timeout); 3604 mutex_unlock(&bp->hwrm_cmd_lock); 3605 return rc; 3606 } 3607 3608 int hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len, 3609 int timeout) 3610 { 3611 int rc; 3612 3613 mutex_lock(&bp->hwrm_cmd_lock); 3614 rc = bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true); 3615 mutex_unlock(&bp->hwrm_cmd_lock); 3616 return rc; 3617 } 3618 3619 int bnxt_hwrm_func_rgtr_async_events(struct bnxt *bp, unsigned long *bmap, 3620 int bmap_size) 3621 { 3622 struct hwrm_func_drv_rgtr_input req = {0}; 3623 DECLARE_BITMAP(async_events_bmap, 256); 3624 u32 *events = (u32 *)async_events_bmap; 3625 int i; 3626 3627 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1); 3628 3629 req.enables = 3630 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD); 3631 3632 memset(async_events_bmap, 0, sizeof(async_events_bmap)); 3633 for (i = 0; i < ARRAY_SIZE(bnxt_async_events_arr); i++) 3634 __set_bit(bnxt_async_events_arr[i], async_events_bmap); 3635 3636 if (bmap && bmap_size) { 3637 for (i = 0; i < bmap_size; i++) { 3638 if (test_bit(i, bmap)) 3639 __set_bit(i, async_events_bmap); 3640 } 3641 } 3642 3643 for (i = 0; i < 8; i++) 3644 req.async_event_fwd[i] |= cpu_to_le32(events[i]); 3645 3646 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 3647 } 3648 3649 static int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp) 3650 { 3651 struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr; 3652 struct hwrm_func_drv_rgtr_input req = {0}; 3653 int rc; 3654 3655 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1); 3656 3657 req.enables = 3658 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE | 3659 FUNC_DRV_RGTR_REQ_ENABLES_VER); 3660 3661 req.os_type = cpu_to_le16(FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX); 3662 req.flags = cpu_to_le32(FUNC_DRV_RGTR_REQ_FLAGS_16BIT_VER_MODE); 3663 req.ver_maj_8b = DRV_VER_MAJ; 3664 req.ver_min_8b = DRV_VER_MIN; 3665 req.ver_upd_8b = DRV_VER_UPD; 3666 req.ver_maj = cpu_to_le16(DRV_VER_MAJ); 3667 req.ver_min = cpu_to_le16(DRV_VER_MIN); 3668 req.ver_upd = cpu_to_le16(DRV_VER_UPD); 3669 3670 if (BNXT_PF(bp)) { 3671 u32 data[8]; 3672 int i; 3673 3674 memset(data, 0, sizeof(data)); 3675 for (i = 0; i < ARRAY_SIZE(bnxt_vf_req_snif); i++) { 3676 u16 cmd = bnxt_vf_req_snif[i]; 3677 unsigned int bit, idx; 3678 3679 idx = cmd / 32; 3680 bit = cmd % 32; 3681 data[idx] |= 1 << bit; 3682 } 3683 3684 for (i = 0; i < 8; i++) 3685 req.vf_req_fwd[i] = cpu_to_le32(data[i]); 3686 3687 req.enables |= 3688 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD); 3689 } 3690 3691 mutex_lock(&bp->hwrm_cmd_lock); 3692 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 3693 if (rc) 3694 rc = -EIO; 3695 else if (resp->flags & 3696 cpu_to_le32(FUNC_DRV_RGTR_RESP_FLAGS_IF_CHANGE_SUPPORTED)) 3697 bp->fw_cap |= BNXT_FW_CAP_IF_CHANGE; 3698 mutex_unlock(&bp->hwrm_cmd_lock); 3699 return rc; 3700 } 3701 3702 static int bnxt_hwrm_func_drv_unrgtr(struct bnxt *bp) 3703 { 3704 struct hwrm_func_drv_unrgtr_input req = {0}; 3705 3706 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_UNRGTR, -1, -1); 3707 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 3708 } 3709 3710 static int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, u8 tunnel_type) 3711 { 3712 u32 rc = 0; 3713 struct hwrm_tunnel_dst_port_free_input req = {0}; 3714 3715 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_FREE, -1, -1); 3716 req.tunnel_type = tunnel_type; 3717 3718 switch (tunnel_type) { 3719 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN: 3720 req.tunnel_dst_port_id = bp->vxlan_fw_dst_port_id; 3721 break; 3722 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE: 3723 req.tunnel_dst_port_id = bp->nge_fw_dst_port_id; 3724 break; 3725 default: 3726 break; 3727 } 3728 3729 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 3730 if (rc) 3731 netdev_err(bp->dev, "hwrm_tunnel_dst_port_free failed. rc:%d\n", 3732 rc); 3733 return rc; 3734 } 3735 3736 static int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, __be16 port, 3737 u8 tunnel_type) 3738 { 3739 u32 rc = 0; 3740 struct hwrm_tunnel_dst_port_alloc_input req = {0}; 3741 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr; 3742 3743 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_ALLOC, -1, -1); 3744 3745 req.tunnel_type = tunnel_type; 3746 req.tunnel_dst_port_val = port; 3747 3748 mutex_lock(&bp->hwrm_cmd_lock); 3749 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 3750 if (rc) { 3751 netdev_err(bp->dev, "hwrm_tunnel_dst_port_alloc failed. rc:%d\n", 3752 rc); 3753 goto err_out; 3754 } 3755 3756 switch (tunnel_type) { 3757 case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN: 3758 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id; 3759 break; 3760 case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE: 3761 bp->nge_fw_dst_port_id = resp->tunnel_dst_port_id; 3762 break; 3763 default: 3764 break; 3765 } 3766 3767 err_out: 3768 mutex_unlock(&bp->hwrm_cmd_lock); 3769 return rc; 3770 } 3771 3772 static int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp, u16 vnic_id) 3773 { 3774 struct hwrm_cfa_l2_set_rx_mask_input req = {0}; 3775 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 3776 3777 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_SET_RX_MASK, -1, -1); 3778 req.vnic_id = cpu_to_le32(vnic->fw_vnic_id); 3779 3780 req.num_mc_entries = cpu_to_le32(vnic->mc_list_count); 3781 req.mc_tbl_addr = cpu_to_le64(vnic->mc_list_mapping); 3782 req.mask = cpu_to_le32(vnic->rx_mask); 3783 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 3784 } 3785 3786 #ifdef CONFIG_RFS_ACCEL 3787 static int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt *bp, 3788 struct bnxt_ntuple_filter *fltr) 3789 { 3790 struct hwrm_cfa_ntuple_filter_free_input req = {0}; 3791 3792 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_FREE, -1, -1); 3793 req.ntuple_filter_id = fltr->filter_id; 3794 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 3795 } 3796 3797 #define BNXT_NTP_FLTR_FLAGS \ 3798 (CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID | \ 3799 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE | \ 3800 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR | \ 3801 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE | \ 3802 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR | \ 3803 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK | \ 3804 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR | \ 3805 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK | \ 3806 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL | \ 3807 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT | \ 3808 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK | \ 3809 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT | \ 3810 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK | \ 3811 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID) 3812 3813 #define BNXT_NTP_TUNNEL_FLTR_FLAG \ 3814 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 3815 3816 static int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt *bp, 3817 struct bnxt_ntuple_filter *fltr) 3818 { 3819 int rc = 0; 3820 struct hwrm_cfa_ntuple_filter_alloc_input req = {0}; 3821 struct hwrm_cfa_ntuple_filter_alloc_output *resp = 3822 bp->hwrm_cmd_resp_addr; 3823 struct flow_keys *keys = &fltr->fkeys; 3824 struct bnxt_vnic_info *vnic = &bp->vnic_info[fltr->rxq + 1]; 3825 3826 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_ALLOC, -1, -1); 3827 req.l2_filter_id = bp->vnic_info[0].fw_l2_filter_id[fltr->l2_fltr_idx]; 3828 3829 req.enables = cpu_to_le32(BNXT_NTP_FLTR_FLAGS); 3830 3831 req.ethertype = htons(ETH_P_IP); 3832 memcpy(req.src_macaddr, fltr->src_mac_addr, ETH_ALEN); 3833 req.ip_addr_type = CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4; 3834 req.ip_protocol = keys->basic.ip_proto; 3835 3836 if (keys->basic.n_proto == htons(ETH_P_IPV6)) { 3837 int i; 3838 3839 req.ethertype = htons(ETH_P_IPV6); 3840 req.ip_addr_type = 3841 CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6; 3842 *(struct in6_addr *)&req.src_ipaddr[0] = 3843 keys->addrs.v6addrs.src; 3844 *(struct in6_addr *)&req.dst_ipaddr[0] = 3845 keys->addrs.v6addrs.dst; 3846 for (i = 0; i < 4; i++) { 3847 req.src_ipaddr_mask[i] = cpu_to_be32(0xffffffff); 3848 req.dst_ipaddr_mask[i] = cpu_to_be32(0xffffffff); 3849 } 3850 } else { 3851 req.src_ipaddr[0] = keys->addrs.v4addrs.src; 3852 req.src_ipaddr_mask[0] = cpu_to_be32(0xffffffff); 3853 req.dst_ipaddr[0] = keys->addrs.v4addrs.dst; 3854 req.dst_ipaddr_mask[0] = cpu_to_be32(0xffffffff); 3855 } 3856 if (keys->control.flags & FLOW_DIS_ENCAPSULATION) { 3857 req.enables |= cpu_to_le32(BNXT_NTP_TUNNEL_FLTR_FLAG); 3858 req.tunnel_type = 3859 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL; 3860 } 3861 3862 req.src_port = keys->ports.src; 3863 req.src_port_mask = cpu_to_be16(0xffff); 3864 req.dst_port = keys->ports.dst; 3865 req.dst_port_mask = cpu_to_be16(0xffff); 3866 3867 req.dst_id = cpu_to_le16(vnic->fw_vnic_id); 3868 mutex_lock(&bp->hwrm_cmd_lock); 3869 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 3870 if (!rc) 3871 fltr->filter_id = resp->ntuple_filter_id; 3872 mutex_unlock(&bp->hwrm_cmd_lock); 3873 return rc; 3874 } 3875 #endif 3876 3877 static int bnxt_hwrm_set_vnic_filter(struct bnxt *bp, u16 vnic_id, u16 idx, 3878 u8 *mac_addr) 3879 { 3880 u32 rc = 0; 3881 struct hwrm_cfa_l2_filter_alloc_input req = {0}; 3882 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr; 3883 3884 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_ALLOC, -1, -1); 3885 req.flags = cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX); 3886 if (!BNXT_CHIP_TYPE_NITRO_A0(bp)) 3887 req.flags |= 3888 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST); 3889 req.dst_id = cpu_to_le16(bp->vnic_info[vnic_id].fw_vnic_id); 3890 req.enables = 3891 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR | 3892 CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID | 3893 CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK); 3894 memcpy(req.l2_addr, mac_addr, ETH_ALEN); 3895 req.l2_addr_mask[0] = 0xff; 3896 req.l2_addr_mask[1] = 0xff; 3897 req.l2_addr_mask[2] = 0xff; 3898 req.l2_addr_mask[3] = 0xff; 3899 req.l2_addr_mask[4] = 0xff; 3900 req.l2_addr_mask[5] = 0xff; 3901 3902 mutex_lock(&bp->hwrm_cmd_lock); 3903 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 3904 if (!rc) 3905 bp->vnic_info[vnic_id].fw_l2_filter_id[idx] = 3906 resp->l2_filter_id; 3907 mutex_unlock(&bp->hwrm_cmd_lock); 3908 return rc; 3909 } 3910 3911 static int bnxt_hwrm_clear_vnic_filter(struct bnxt *bp) 3912 { 3913 u16 i, j, num_of_vnics = 1; /* only vnic 0 supported */ 3914 int rc = 0; 3915 3916 /* Any associated ntuple filters will also be cleared by firmware. */ 3917 mutex_lock(&bp->hwrm_cmd_lock); 3918 for (i = 0; i < num_of_vnics; i++) { 3919 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 3920 3921 for (j = 0; j < vnic->uc_filter_count; j++) { 3922 struct hwrm_cfa_l2_filter_free_input req = {0}; 3923 3924 bnxt_hwrm_cmd_hdr_init(bp, &req, 3925 HWRM_CFA_L2_FILTER_FREE, -1, -1); 3926 3927 req.l2_filter_id = vnic->fw_l2_filter_id[j]; 3928 3929 rc = _hwrm_send_message(bp, &req, sizeof(req), 3930 HWRM_CMD_TIMEOUT); 3931 } 3932 vnic->uc_filter_count = 0; 3933 } 3934 mutex_unlock(&bp->hwrm_cmd_lock); 3935 3936 return rc; 3937 } 3938 3939 static int bnxt_hwrm_vnic_set_tpa(struct bnxt *bp, u16 vnic_id, u32 tpa_flags) 3940 { 3941 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 3942 struct hwrm_vnic_tpa_cfg_input req = {0}; 3943 3944 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) 3945 return 0; 3946 3947 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_TPA_CFG, -1, -1); 3948 3949 if (tpa_flags) { 3950 u16 mss = bp->dev->mtu - 40; 3951 u32 nsegs, n, segs = 0, flags; 3952 3953 flags = VNIC_TPA_CFG_REQ_FLAGS_TPA | 3954 VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA | 3955 VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE | 3956 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN | 3957 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ; 3958 if (tpa_flags & BNXT_FLAG_GRO) 3959 flags |= VNIC_TPA_CFG_REQ_FLAGS_GRO; 3960 3961 req.flags = cpu_to_le32(flags); 3962 3963 req.enables = 3964 cpu_to_le32(VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS | 3965 VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS | 3966 VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN); 3967 3968 /* Number of segs are log2 units, and first packet is not 3969 * included as part of this units. 3970 */ 3971 if (mss <= BNXT_RX_PAGE_SIZE) { 3972 n = BNXT_RX_PAGE_SIZE / mss; 3973 nsegs = (MAX_SKB_FRAGS - 1) * n; 3974 } else { 3975 n = mss / BNXT_RX_PAGE_SIZE; 3976 if (mss & (BNXT_RX_PAGE_SIZE - 1)) 3977 n++; 3978 nsegs = (MAX_SKB_FRAGS - n) / n; 3979 } 3980 3981 segs = ilog2(nsegs); 3982 req.max_agg_segs = cpu_to_le16(segs); 3983 req.max_aggs = cpu_to_le16(VNIC_TPA_CFG_REQ_MAX_AGGS_MAX); 3984 3985 req.min_agg_len = cpu_to_le32(512); 3986 } 3987 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id); 3988 3989 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 3990 } 3991 3992 static int bnxt_hwrm_vnic_set_rss(struct bnxt *bp, u16 vnic_id, bool set_rss) 3993 { 3994 u32 i, j, max_rings; 3995 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 3996 struct hwrm_vnic_rss_cfg_input req = {0}; 3997 3998 if (vnic->fw_rss_cos_lb_ctx[0] == INVALID_HW_RING_ID) 3999 return 0; 4000 4001 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1); 4002 if (set_rss) { 4003 req.hash_type = cpu_to_le32(bp->rss_hash_cfg); 4004 req.hash_mode_flags = VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT; 4005 if (vnic->flags & BNXT_VNIC_RSS_FLAG) { 4006 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 4007 max_rings = bp->rx_nr_rings - 1; 4008 else 4009 max_rings = bp->rx_nr_rings; 4010 } else { 4011 max_rings = 1; 4012 } 4013 4014 /* Fill the RSS indirection table with ring group ids */ 4015 for (i = 0, j = 0; i < HW_HASH_INDEX_SIZE; i++, j++) { 4016 if (j == max_rings) 4017 j = 0; 4018 vnic->rss_table[i] = cpu_to_le16(vnic->fw_grp_ids[j]); 4019 } 4020 4021 req.ring_grp_tbl_addr = cpu_to_le64(vnic->rss_table_dma_addr); 4022 req.hash_key_tbl_addr = 4023 cpu_to_le64(vnic->rss_hash_key_dma_addr); 4024 } 4025 req.rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]); 4026 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4027 } 4028 4029 static int bnxt_hwrm_vnic_set_hds(struct bnxt *bp, u16 vnic_id) 4030 { 4031 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 4032 struct hwrm_vnic_plcmodes_cfg_input req = {0}; 4033 4034 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_PLCMODES_CFG, -1, -1); 4035 req.flags = cpu_to_le32(VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT | 4036 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 | 4037 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6); 4038 req.enables = 4039 cpu_to_le32(VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID | 4040 VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID); 4041 /* thresholds not implemented in firmware yet */ 4042 req.jumbo_thresh = cpu_to_le16(bp->rx_copy_thresh); 4043 req.hds_threshold = cpu_to_le16(bp->rx_copy_thresh); 4044 req.vnic_id = cpu_to_le32(vnic->fw_vnic_id); 4045 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4046 } 4047 4048 static void bnxt_hwrm_vnic_ctx_free_one(struct bnxt *bp, u16 vnic_id, 4049 u16 ctx_idx) 4050 { 4051 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {0}; 4052 4053 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, -1, -1); 4054 req.rss_cos_lb_ctx_id = 4055 cpu_to_le16(bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx]); 4056 4057 hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4058 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] = INVALID_HW_RING_ID; 4059 } 4060 4061 static void bnxt_hwrm_vnic_ctx_free(struct bnxt *bp) 4062 { 4063 int i, j; 4064 4065 for (i = 0; i < bp->nr_vnics; i++) { 4066 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 4067 4068 for (j = 0; j < BNXT_MAX_CTX_PER_VNIC; j++) { 4069 if (vnic->fw_rss_cos_lb_ctx[j] != INVALID_HW_RING_ID) 4070 bnxt_hwrm_vnic_ctx_free_one(bp, i, j); 4071 } 4072 } 4073 bp->rsscos_nr_ctxs = 0; 4074 } 4075 4076 static int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, u16 vnic_id, u16 ctx_idx) 4077 { 4078 int rc; 4079 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {0}; 4080 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp = 4081 bp->hwrm_cmd_resp_addr; 4082 4083 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, -1, 4084 -1); 4085 4086 mutex_lock(&bp->hwrm_cmd_lock); 4087 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4088 if (!rc) 4089 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] = 4090 le16_to_cpu(resp->rss_cos_lb_ctx_id); 4091 mutex_unlock(&bp->hwrm_cmd_lock); 4092 4093 return rc; 4094 } 4095 4096 static u32 bnxt_get_roce_vnic_mode(struct bnxt *bp) 4097 { 4098 if (bp->flags & BNXT_FLAG_ROCE_MIRROR_CAP) 4099 return VNIC_CFG_REQ_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE; 4100 return VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE; 4101 } 4102 4103 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id) 4104 { 4105 unsigned int ring = 0, grp_idx; 4106 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 4107 struct hwrm_vnic_cfg_input req = {0}; 4108 u16 def_vlan = 0; 4109 4110 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_CFG, -1, -1); 4111 4112 req.enables = cpu_to_le32(VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP); 4113 /* Only RSS support for now TBD: COS & LB */ 4114 if (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID) { 4115 req.rss_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]); 4116 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE | 4117 VNIC_CFG_REQ_ENABLES_MRU); 4118 } else if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG) { 4119 req.rss_rule = 4120 cpu_to_le16(bp->vnic_info[0].fw_rss_cos_lb_ctx[0]); 4121 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE | 4122 VNIC_CFG_REQ_ENABLES_MRU); 4123 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE); 4124 } else { 4125 req.rss_rule = cpu_to_le16(0xffff); 4126 } 4127 4128 if (BNXT_CHIP_TYPE_NITRO_A0(bp) && 4129 (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID)) { 4130 req.cos_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[1]); 4131 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_COS_RULE); 4132 } else { 4133 req.cos_rule = cpu_to_le16(0xffff); 4134 } 4135 4136 if (vnic->flags & BNXT_VNIC_RSS_FLAG) 4137 ring = 0; 4138 else if (vnic->flags & BNXT_VNIC_RFS_FLAG) 4139 ring = vnic_id - 1; 4140 else if ((vnic_id == 1) && BNXT_CHIP_TYPE_NITRO_A0(bp)) 4141 ring = bp->rx_nr_rings - 1; 4142 4143 grp_idx = bp->rx_ring[ring].bnapi->index; 4144 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id); 4145 req.dflt_ring_grp = cpu_to_le16(bp->grp_info[grp_idx].fw_grp_id); 4146 4147 req.lb_rule = cpu_to_le16(0xffff); 4148 req.mru = cpu_to_le16(bp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + 4149 VLAN_HLEN); 4150 4151 #ifdef CONFIG_BNXT_SRIOV 4152 if (BNXT_VF(bp)) 4153 def_vlan = bp->vf.vlan; 4154 #endif 4155 if ((bp->flags & BNXT_FLAG_STRIP_VLAN) || def_vlan) 4156 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE); 4157 if (!vnic_id && bnxt_ulp_registered(bp->edev, BNXT_ROCE_ULP)) 4158 req.flags |= cpu_to_le32(bnxt_get_roce_vnic_mode(bp)); 4159 4160 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4161 } 4162 4163 static int bnxt_hwrm_vnic_free_one(struct bnxt *bp, u16 vnic_id) 4164 { 4165 u32 rc = 0; 4166 4167 if (bp->vnic_info[vnic_id].fw_vnic_id != INVALID_HW_RING_ID) { 4168 struct hwrm_vnic_free_input req = {0}; 4169 4170 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_FREE, -1, -1); 4171 req.vnic_id = 4172 cpu_to_le32(bp->vnic_info[vnic_id].fw_vnic_id); 4173 4174 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4175 if (rc) 4176 return rc; 4177 bp->vnic_info[vnic_id].fw_vnic_id = INVALID_HW_RING_ID; 4178 } 4179 return rc; 4180 } 4181 4182 static void bnxt_hwrm_vnic_free(struct bnxt *bp) 4183 { 4184 u16 i; 4185 4186 for (i = 0; i < bp->nr_vnics; i++) 4187 bnxt_hwrm_vnic_free_one(bp, i); 4188 } 4189 4190 static int bnxt_hwrm_vnic_alloc(struct bnxt *bp, u16 vnic_id, 4191 unsigned int start_rx_ring_idx, 4192 unsigned int nr_rings) 4193 { 4194 int rc = 0; 4195 unsigned int i, j, grp_idx, end_idx = start_rx_ring_idx + nr_rings; 4196 struct hwrm_vnic_alloc_input req = {0}; 4197 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr; 4198 4199 /* map ring groups to this vnic */ 4200 for (i = start_rx_ring_idx, j = 0; i < end_idx; i++, j++) { 4201 grp_idx = bp->rx_ring[i].bnapi->index; 4202 if (bp->grp_info[grp_idx].fw_grp_id == INVALID_HW_RING_ID) { 4203 netdev_err(bp->dev, "Not enough ring groups avail:%x req:%x\n", 4204 j, nr_rings); 4205 break; 4206 } 4207 bp->vnic_info[vnic_id].fw_grp_ids[j] = 4208 bp->grp_info[grp_idx].fw_grp_id; 4209 } 4210 4211 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[0] = INVALID_HW_RING_ID; 4212 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[1] = INVALID_HW_RING_ID; 4213 if (vnic_id == 0) 4214 req.flags = cpu_to_le32(VNIC_ALLOC_REQ_FLAGS_DEFAULT); 4215 4216 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_ALLOC, -1, -1); 4217 4218 mutex_lock(&bp->hwrm_cmd_lock); 4219 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4220 if (!rc) 4221 bp->vnic_info[vnic_id].fw_vnic_id = le32_to_cpu(resp->vnic_id); 4222 mutex_unlock(&bp->hwrm_cmd_lock); 4223 return rc; 4224 } 4225 4226 static int bnxt_hwrm_vnic_qcaps(struct bnxt *bp) 4227 { 4228 struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr; 4229 struct hwrm_vnic_qcaps_input req = {0}; 4230 int rc; 4231 4232 if (bp->hwrm_spec_code < 0x10600) 4233 return 0; 4234 4235 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_QCAPS, -1, -1); 4236 mutex_lock(&bp->hwrm_cmd_lock); 4237 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4238 if (!rc) { 4239 u32 flags = le32_to_cpu(resp->flags); 4240 4241 if (flags & VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP) 4242 bp->flags |= BNXT_FLAG_NEW_RSS_CAP; 4243 if (flags & 4244 VNIC_QCAPS_RESP_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP) 4245 bp->flags |= BNXT_FLAG_ROCE_MIRROR_CAP; 4246 } 4247 mutex_unlock(&bp->hwrm_cmd_lock); 4248 return rc; 4249 } 4250 4251 static int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp) 4252 { 4253 u16 i; 4254 u32 rc = 0; 4255 4256 mutex_lock(&bp->hwrm_cmd_lock); 4257 for (i = 0; i < bp->rx_nr_rings; i++) { 4258 struct hwrm_ring_grp_alloc_input req = {0}; 4259 struct hwrm_ring_grp_alloc_output *resp = 4260 bp->hwrm_cmd_resp_addr; 4261 unsigned int grp_idx = bp->rx_ring[i].bnapi->index; 4262 4263 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_ALLOC, -1, -1); 4264 4265 req.cr = cpu_to_le16(bp->grp_info[grp_idx].cp_fw_ring_id); 4266 req.rr = cpu_to_le16(bp->grp_info[grp_idx].rx_fw_ring_id); 4267 req.ar = cpu_to_le16(bp->grp_info[grp_idx].agg_fw_ring_id); 4268 req.sc = cpu_to_le16(bp->grp_info[grp_idx].fw_stats_ctx); 4269 4270 rc = _hwrm_send_message(bp, &req, sizeof(req), 4271 HWRM_CMD_TIMEOUT); 4272 if (rc) 4273 break; 4274 4275 bp->grp_info[grp_idx].fw_grp_id = 4276 le32_to_cpu(resp->ring_group_id); 4277 } 4278 mutex_unlock(&bp->hwrm_cmd_lock); 4279 return rc; 4280 } 4281 4282 static int bnxt_hwrm_ring_grp_free(struct bnxt *bp) 4283 { 4284 u16 i; 4285 u32 rc = 0; 4286 struct hwrm_ring_grp_free_input req = {0}; 4287 4288 if (!bp->grp_info) 4289 return 0; 4290 4291 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_FREE, -1, -1); 4292 4293 mutex_lock(&bp->hwrm_cmd_lock); 4294 for (i = 0; i < bp->cp_nr_rings; i++) { 4295 if (bp->grp_info[i].fw_grp_id == INVALID_HW_RING_ID) 4296 continue; 4297 req.ring_group_id = 4298 cpu_to_le32(bp->grp_info[i].fw_grp_id); 4299 4300 rc = _hwrm_send_message(bp, &req, sizeof(req), 4301 HWRM_CMD_TIMEOUT); 4302 if (rc) 4303 break; 4304 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID; 4305 } 4306 mutex_unlock(&bp->hwrm_cmd_lock); 4307 return rc; 4308 } 4309 4310 static int hwrm_ring_alloc_send_msg(struct bnxt *bp, 4311 struct bnxt_ring_struct *ring, 4312 u32 ring_type, u32 map_index) 4313 { 4314 int rc = 0, err = 0; 4315 struct hwrm_ring_alloc_input req = {0}; 4316 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr; 4317 struct bnxt_ring_grp_info *grp_info; 4318 u16 ring_id; 4319 4320 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_ALLOC, -1, -1); 4321 4322 req.enables = 0; 4323 if (ring->nr_pages > 1) { 4324 req.page_tbl_addr = cpu_to_le64(ring->pg_tbl_map); 4325 /* Page size is in log2 units */ 4326 req.page_size = BNXT_PAGE_SHIFT; 4327 req.page_tbl_depth = 1; 4328 } else { 4329 req.page_tbl_addr = cpu_to_le64(ring->dma_arr[0]); 4330 } 4331 req.fbo = 0; 4332 /* Association of ring index with doorbell index and MSIX number */ 4333 req.logical_id = cpu_to_le16(map_index); 4334 4335 switch (ring_type) { 4336 case HWRM_RING_ALLOC_TX: 4337 req.ring_type = RING_ALLOC_REQ_RING_TYPE_TX; 4338 /* Association of transmit ring with completion ring */ 4339 grp_info = &bp->grp_info[ring->grp_idx]; 4340 req.cmpl_ring_id = cpu_to_le16(grp_info->cp_fw_ring_id); 4341 req.length = cpu_to_le32(bp->tx_ring_mask + 1); 4342 req.stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx); 4343 req.queue_id = cpu_to_le16(ring->queue_id); 4344 break; 4345 case HWRM_RING_ALLOC_RX: 4346 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX; 4347 req.length = cpu_to_le32(bp->rx_ring_mask + 1); 4348 break; 4349 case HWRM_RING_ALLOC_AGG: 4350 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX; 4351 req.length = cpu_to_le32(bp->rx_agg_ring_mask + 1); 4352 break; 4353 case HWRM_RING_ALLOC_CMPL: 4354 req.ring_type = RING_ALLOC_REQ_RING_TYPE_L2_CMPL; 4355 req.length = cpu_to_le32(bp->cp_ring_mask + 1); 4356 if (bp->flags & BNXT_FLAG_USING_MSIX) 4357 req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX; 4358 break; 4359 default: 4360 netdev_err(bp->dev, "hwrm alloc invalid ring type %d\n", 4361 ring_type); 4362 return -1; 4363 } 4364 4365 mutex_lock(&bp->hwrm_cmd_lock); 4366 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4367 err = le16_to_cpu(resp->error_code); 4368 ring_id = le16_to_cpu(resp->ring_id); 4369 mutex_unlock(&bp->hwrm_cmd_lock); 4370 4371 if (rc || err) { 4372 netdev_err(bp->dev, "hwrm_ring_alloc type %d failed. rc:%x err:%x\n", 4373 ring_type, rc, err); 4374 return -EIO; 4375 } 4376 ring->fw_ring_id = ring_id; 4377 return rc; 4378 } 4379 4380 static int bnxt_hwrm_set_async_event_cr(struct bnxt *bp, int idx) 4381 { 4382 int rc; 4383 4384 if (BNXT_PF(bp)) { 4385 struct hwrm_func_cfg_input req = {0}; 4386 4387 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1); 4388 req.fid = cpu_to_le16(0xffff); 4389 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR); 4390 req.async_event_cr = cpu_to_le16(idx); 4391 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4392 } else { 4393 struct hwrm_func_vf_cfg_input req = {0}; 4394 4395 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_VF_CFG, -1, -1); 4396 req.enables = 4397 cpu_to_le32(FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR); 4398 req.async_event_cr = cpu_to_le16(idx); 4399 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4400 } 4401 return rc; 4402 } 4403 4404 static int bnxt_hwrm_ring_alloc(struct bnxt *bp) 4405 { 4406 int i, rc = 0; 4407 4408 for (i = 0; i < bp->cp_nr_rings; i++) { 4409 struct bnxt_napi *bnapi = bp->bnapi[i]; 4410 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 4411 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct; 4412 u32 map_idx = ring->map_idx; 4413 4414 cpr->cp_doorbell = bp->bar1 + map_idx * 0x80; 4415 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_CMPL, 4416 map_idx); 4417 if (rc) 4418 goto err_out; 4419 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons); 4420 bp->grp_info[i].cp_fw_ring_id = ring->fw_ring_id; 4421 4422 if (!i) { 4423 rc = bnxt_hwrm_set_async_event_cr(bp, ring->fw_ring_id); 4424 if (rc) 4425 netdev_warn(bp->dev, "Failed to set async event completion ring.\n"); 4426 } 4427 } 4428 4429 for (i = 0; i < bp->tx_nr_rings; i++) { 4430 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; 4431 struct bnxt_ring_struct *ring = &txr->tx_ring_struct; 4432 u32 map_idx = i; 4433 4434 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_TX, 4435 map_idx); 4436 if (rc) 4437 goto err_out; 4438 txr->tx_doorbell = bp->bar1 + map_idx * 0x80; 4439 } 4440 4441 for (i = 0; i < bp->rx_nr_rings; i++) { 4442 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 4443 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct; 4444 u32 map_idx = rxr->bnapi->index; 4445 4446 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_RX, 4447 map_idx); 4448 if (rc) 4449 goto err_out; 4450 rxr->rx_doorbell = bp->bar1 + map_idx * 0x80; 4451 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell); 4452 bp->grp_info[map_idx].rx_fw_ring_id = ring->fw_ring_id; 4453 } 4454 4455 if (bp->flags & BNXT_FLAG_AGG_RINGS) { 4456 for (i = 0; i < bp->rx_nr_rings; i++) { 4457 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 4458 struct bnxt_ring_struct *ring = 4459 &rxr->rx_agg_ring_struct; 4460 u32 grp_idx = ring->grp_idx; 4461 u32 map_idx = grp_idx + bp->rx_nr_rings; 4462 4463 rc = hwrm_ring_alloc_send_msg(bp, ring, 4464 HWRM_RING_ALLOC_AGG, 4465 map_idx); 4466 if (rc) 4467 goto err_out; 4468 4469 rxr->rx_agg_doorbell = bp->bar1 + map_idx * 0x80; 4470 writel(DB_KEY_RX | rxr->rx_agg_prod, 4471 rxr->rx_agg_doorbell); 4472 bp->grp_info[grp_idx].agg_fw_ring_id = ring->fw_ring_id; 4473 } 4474 } 4475 err_out: 4476 return rc; 4477 } 4478 4479 static int hwrm_ring_free_send_msg(struct bnxt *bp, 4480 struct bnxt_ring_struct *ring, 4481 u32 ring_type, int cmpl_ring_id) 4482 { 4483 int rc; 4484 struct hwrm_ring_free_input req = {0}; 4485 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr; 4486 u16 error_code; 4487 4488 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_FREE, cmpl_ring_id, -1); 4489 req.ring_type = ring_type; 4490 req.ring_id = cpu_to_le16(ring->fw_ring_id); 4491 4492 mutex_lock(&bp->hwrm_cmd_lock); 4493 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4494 error_code = le16_to_cpu(resp->error_code); 4495 mutex_unlock(&bp->hwrm_cmd_lock); 4496 4497 if (rc || error_code) { 4498 netdev_err(bp->dev, "hwrm_ring_free type %d failed. rc:%x err:%x\n", 4499 ring_type, rc, error_code); 4500 return -EIO; 4501 } 4502 return 0; 4503 } 4504 4505 static void bnxt_hwrm_ring_free(struct bnxt *bp, bool close_path) 4506 { 4507 int i; 4508 4509 if (!bp->bnapi) 4510 return; 4511 4512 for (i = 0; i < bp->tx_nr_rings; i++) { 4513 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; 4514 struct bnxt_ring_struct *ring = &txr->tx_ring_struct; 4515 u32 grp_idx = txr->bnapi->index; 4516 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id; 4517 4518 if (ring->fw_ring_id != INVALID_HW_RING_ID) { 4519 hwrm_ring_free_send_msg(bp, ring, 4520 RING_FREE_REQ_RING_TYPE_TX, 4521 close_path ? cmpl_ring_id : 4522 INVALID_HW_RING_ID); 4523 ring->fw_ring_id = INVALID_HW_RING_ID; 4524 } 4525 } 4526 4527 for (i = 0; i < bp->rx_nr_rings; i++) { 4528 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 4529 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct; 4530 u32 grp_idx = rxr->bnapi->index; 4531 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id; 4532 4533 if (ring->fw_ring_id != INVALID_HW_RING_ID) { 4534 hwrm_ring_free_send_msg(bp, ring, 4535 RING_FREE_REQ_RING_TYPE_RX, 4536 close_path ? cmpl_ring_id : 4537 INVALID_HW_RING_ID); 4538 ring->fw_ring_id = INVALID_HW_RING_ID; 4539 bp->grp_info[grp_idx].rx_fw_ring_id = 4540 INVALID_HW_RING_ID; 4541 } 4542 } 4543 4544 for (i = 0; i < bp->rx_nr_rings; i++) { 4545 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 4546 struct bnxt_ring_struct *ring = &rxr->rx_agg_ring_struct; 4547 u32 grp_idx = rxr->bnapi->index; 4548 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id; 4549 4550 if (ring->fw_ring_id != INVALID_HW_RING_ID) { 4551 hwrm_ring_free_send_msg(bp, ring, 4552 RING_FREE_REQ_RING_TYPE_RX, 4553 close_path ? cmpl_ring_id : 4554 INVALID_HW_RING_ID); 4555 ring->fw_ring_id = INVALID_HW_RING_ID; 4556 bp->grp_info[grp_idx].agg_fw_ring_id = 4557 INVALID_HW_RING_ID; 4558 } 4559 } 4560 4561 /* The completion rings are about to be freed. After that the 4562 * IRQ doorbell will not work anymore. So we need to disable 4563 * IRQ here. 4564 */ 4565 bnxt_disable_int_sync(bp); 4566 4567 for (i = 0; i < bp->cp_nr_rings; i++) { 4568 struct bnxt_napi *bnapi = bp->bnapi[i]; 4569 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 4570 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct; 4571 4572 if (ring->fw_ring_id != INVALID_HW_RING_ID) { 4573 hwrm_ring_free_send_msg(bp, ring, 4574 RING_FREE_REQ_RING_TYPE_L2_CMPL, 4575 INVALID_HW_RING_ID); 4576 ring->fw_ring_id = INVALID_HW_RING_ID; 4577 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID; 4578 } 4579 } 4580 } 4581 4582 static int bnxt_hwrm_get_rings(struct bnxt *bp) 4583 { 4584 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr; 4585 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 4586 struct hwrm_func_qcfg_input req = {0}; 4587 int rc; 4588 4589 if (bp->hwrm_spec_code < 0x10601) 4590 return 0; 4591 4592 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1); 4593 req.fid = cpu_to_le16(0xffff); 4594 mutex_lock(&bp->hwrm_cmd_lock); 4595 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4596 if (rc) { 4597 mutex_unlock(&bp->hwrm_cmd_lock); 4598 return -EIO; 4599 } 4600 4601 hw_resc->resv_tx_rings = le16_to_cpu(resp->alloc_tx_rings); 4602 if (BNXT_NEW_RM(bp)) { 4603 u16 cp, stats; 4604 4605 hw_resc->resv_rx_rings = le16_to_cpu(resp->alloc_rx_rings); 4606 hw_resc->resv_hw_ring_grps = 4607 le32_to_cpu(resp->alloc_hw_ring_grps); 4608 hw_resc->resv_vnics = le16_to_cpu(resp->alloc_vnics); 4609 cp = le16_to_cpu(resp->alloc_cmpl_rings); 4610 stats = le16_to_cpu(resp->alloc_stat_ctx); 4611 cp = min_t(u16, cp, stats); 4612 hw_resc->resv_cp_rings = cp; 4613 } 4614 mutex_unlock(&bp->hwrm_cmd_lock); 4615 return 0; 4616 } 4617 4618 /* Caller must hold bp->hwrm_cmd_lock */ 4619 int __bnxt_hwrm_get_tx_rings(struct bnxt *bp, u16 fid, int *tx_rings) 4620 { 4621 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr; 4622 struct hwrm_func_qcfg_input req = {0}; 4623 int rc; 4624 4625 if (bp->hwrm_spec_code < 0x10601) 4626 return 0; 4627 4628 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1); 4629 req.fid = cpu_to_le16(fid); 4630 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4631 if (!rc) 4632 *tx_rings = le16_to_cpu(resp->alloc_tx_rings); 4633 4634 return rc; 4635 } 4636 4637 static void 4638 __bnxt_hwrm_reserve_pf_rings(struct bnxt *bp, struct hwrm_func_cfg_input *req, 4639 int tx_rings, int rx_rings, int ring_grps, 4640 int cp_rings, int vnics) 4641 { 4642 u32 enables = 0; 4643 4644 bnxt_hwrm_cmd_hdr_init(bp, req, HWRM_FUNC_CFG, -1, -1); 4645 req->fid = cpu_to_le16(0xffff); 4646 enables |= tx_rings ? FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS : 0; 4647 req->num_tx_rings = cpu_to_le16(tx_rings); 4648 if (BNXT_NEW_RM(bp)) { 4649 enables |= rx_rings ? FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS : 0; 4650 enables |= cp_rings ? FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS | 4651 FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0; 4652 enables |= ring_grps ? 4653 FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS : 0; 4654 enables |= vnics ? FUNC_CFG_REQ_ENABLES_NUM_VNICS : 0; 4655 4656 req->num_rx_rings = cpu_to_le16(rx_rings); 4657 req->num_hw_ring_grps = cpu_to_le16(ring_grps); 4658 req->num_cmpl_rings = cpu_to_le16(cp_rings); 4659 req->num_stat_ctxs = req->num_cmpl_rings; 4660 req->num_vnics = cpu_to_le16(vnics); 4661 } 4662 req->enables = cpu_to_le32(enables); 4663 } 4664 4665 static void 4666 __bnxt_hwrm_reserve_vf_rings(struct bnxt *bp, 4667 struct hwrm_func_vf_cfg_input *req, int tx_rings, 4668 int rx_rings, int ring_grps, int cp_rings, 4669 int vnics) 4670 { 4671 u32 enables = 0; 4672 4673 bnxt_hwrm_cmd_hdr_init(bp, req, HWRM_FUNC_VF_CFG, -1, -1); 4674 enables |= tx_rings ? FUNC_VF_CFG_REQ_ENABLES_NUM_TX_RINGS : 0; 4675 enables |= rx_rings ? FUNC_VF_CFG_REQ_ENABLES_NUM_RX_RINGS : 0; 4676 enables |= cp_rings ? FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS | 4677 FUNC_VF_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0; 4678 enables |= ring_grps ? FUNC_VF_CFG_REQ_ENABLES_NUM_HW_RING_GRPS : 0; 4679 enables |= vnics ? FUNC_VF_CFG_REQ_ENABLES_NUM_VNICS : 0; 4680 4681 req->num_tx_rings = cpu_to_le16(tx_rings); 4682 req->num_rx_rings = cpu_to_le16(rx_rings); 4683 req->num_hw_ring_grps = cpu_to_le16(ring_grps); 4684 req->num_cmpl_rings = cpu_to_le16(cp_rings); 4685 req->num_stat_ctxs = req->num_cmpl_rings; 4686 req->num_vnics = cpu_to_le16(vnics); 4687 4688 req->enables = cpu_to_le32(enables); 4689 } 4690 4691 static int 4692 bnxt_hwrm_reserve_pf_rings(struct bnxt *bp, int tx_rings, int rx_rings, 4693 int ring_grps, int cp_rings, int vnics) 4694 { 4695 struct hwrm_func_cfg_input req = {0}; 4696 int rc; 4697 4698 __bnxt_hwrm_reserve_pf_rings(bp, &req, tx_rings, rx_rings, ring_grps, 4699 cp_rings, vnics); 4700 if (!req.enables) 4701 return 0; 4702 4703 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4704 if (rc) 4705 return -ENOMEM; 4706 4707 if (bp->hwrm_spec_code < 0x10601) 4708 bp->hw_resc.resv_tx_rings = tx_rings; 4709 4710 rc = bnxt_hwrm_get_rings(bp); 4711 return rc; 4712 } 4713 4714 static int 4715 bnxt_hwrm_reserve_vf_rings(struct bnxt *bp, int tx_rings, int rx_rings, 4716 int ring_grps, int cp_rings, int vnics) 4717 { 4718 struct hwrm_func_vf_cfg_input req = {0}; 4719 int rc; 4720 4721 if (!BNXT_NEW_RM(bp)) { 4722 bp->hw_resc.resv_tx_rings = tx_rings; 4723 return 0; 4724 } 4725 4726 __bnxt_hwrm_reserve_vf_rings(bp, &req, tx_rings, rx_rings, ring_grps, 4727 cp_rings, vnics); 4728 req.enables |= cpu_to_le32(FUNC_VF_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS | 4729 FUNC_VF_CFG_REQ_ENABLES_NUM_L2_CTXS); 4730 req.num_rsscos_ctxs = cpu_to_le16(BNXT_VF_MAX_RSS_CTX); 4731 req.num_l2_ctxs = cpu_to_le16(BNXT_VF_MAX_L2_CTX); 4732 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4733 if (rc) 4734 return -ENOMEM; 4735 4736 rc = bnxt_hwrm_get_rings(bp); 4737 return rc; 4738 } 4739 4740 static int bnxt_hwrm_reserve_rings(struct bnxt *bp, int tx, int rx, int grp, 4741 int cp, int vnic) 4742 { 4743 if (BNXT_PF(bp)) 4744 return bnxt_hwrm_reserve_pf_rings(bp, tx, rx, grp, cp, vnic); 4745 else 4746 return bnxt_hwrm_reserve_vf_rings(bp, tx, rx, grp, cp, vnic); 4747 } 4748 4749 static int bnxt_cp_rings_in_use(struct bnxt *bp) 4750 { 4751 int cp = bp->cp_nr_rings; 4752 int ulp_msix, ulp_base; 4753 4754 ulp_msix = bnxt_get_ulp_msix_num(bp); 4755 if (ulp_msix) { 4756 ulp_base = bnxt_get_ulp_msix_base(bp); 4757 cp += ulp_msix; 4758 if ((ulp_base + ulp_msix) > cp) 4759 cp = ulp_base + ulp_msix; 4760 } 4761 return cp; 4762 } 4763 4764 static bool bnxt_need_reserve_rings(struct bnxt *bp) 4765 { 4766 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 4767 int cp = bnxt_cp_rings_in_use(bp); 4768 int rx = bp->rx_nr_rings; 4769 int vnic = 1, grp = rx; 4770 4771 if (bp->hwrm_spec_code < 0x10601) 4772 return false; 4773 4774 if (hw_resc->resv_tx_rings != bp->tx_nr_rings) 4775 return true; 4776 4777 if (bp->flags & BNXT_FLAG_RFS) 4778 vnic = rx + 1; 4779 if (bp->flags & BNXT_FLAG_AGG_RINGS) 4780 rx <<= 1; 4781 if (BNXT_NEW_RM(bp) && 4782 (hw_resc->resv_rx_rings != rx || hw_resc->resv_cp_rings != cp || 4783 hw_resc->resv_hw_ring_grps != grp || hw_resc->resv_vnics != vnic)) 4784 return true; 4785 return false; 4786 } 4787 4788 static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max, 4789 bool shared); 4790 4791 static int __bnxt_reserve_rings(struct bnxt *bp) 4792 { 4793 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 4794 int cp = bnxt_cp_rings_in_use(bp); 4795 int tx = bp->tx_nr_rings; 4796 int rx = bp->rx_nr_rings; 4797 int grp, rx_rings, rc; 4798 bool sh = false; 4799 int vnic = 1; 4800 4801 if (!bnxt_need_reserve_rings(bp)) 4802 return 0; 4803 4804 if (bp->flags & BNXT_FLAG_SHARED_RINGS) 4805 sh = true; 4806 if (bp->flags & BNXT_FLAG_RFS) 4807 vnic = rx + 1; 4808 if (bp->flags & BNXT_FLAG_AGG_RINGS) 4809 rx <<= 1; 4810 grp = bp->rx_nr_rings; 4811 4812 rc = bnxt_hwrm_reserve_rings(bp, tx, rx, grp, cp, vnic); 4813 if (rc) 4814 return rc; 4815 4816 tx = hw_resc->resv_tx_rings; 4817 if (BNXT_NEW_RM(bp)) { 4818 rx = hw_resc->resv_rx_rings; 4819 cp = hw_resc->resv_cp_rings; 4820 grp = hw_resc->resv_hw_ring_grps; 4821 vnic = hw_resc->resv_vnics; 4822 } 4823 4824 rx_rings = rx; 4825 if (bp->flags & BNXT_FLAG_AGG_RINGS) { 4826 if (rx >= 2) { 4827 rx_rings = rx >> 1; 4828 } else { 4829 if (netif_running(bp->dev)) 4830 return -ENOMEM; 4831 4832 bp->flags &= ~BNXT_FLAG_AGG_RINGS; 4833 bp->flags |= BNXT_FLAG_NO_AGG_RINGS; 4834 bp->dev->hw_features &= ~NETIF_F_LRO; 4835 bp->dev->features &= ~NETIF_F_LRO; 4836 bnxt_set_ring_params(bp); 4837 } 4838 } 4839 rx_rings = min_t(int, rx_rings, grp); 4840 rc = bnxt_trim_rings(bp, &rx_rings, &tx, cp, sh); 4841 if (bp->flags & BNXT_FLAG_AGG_RINGS) 4842 rx = rx_rings << 1; 4843 cp = sh ? max_t(int, tx, rx_rings) : tx + rx_rings; 4844 bp->tx_nr_rings = tx; 4845 bp->rx_nr_rings = rx_rings; 4846 bp->cp_nr_rings = cp; 4847 4848 if (!tx || !rx || !cp || !grp || !vnic) 4849 return -ENOMEM; 4850 4851 return rc; 4852 } 4853 4854 static int bnxt_hwrm_check_vf_rings(struct bnxt *bp, int tx_rings, int rx_rings, 4855 int ring_grps, int cp_rings, int vnics) 4856 { 4857 struct hwrm_func_vf_cfg_input req = {0}; 4858 u32 flags; 4859 int rc; 4860 4861 if (!BNXT_NEW_RM(bp)) 4862 return 0; 4863 4864 __bnxt_hwrm_reserve_vf_rings(bp, &req, tx_rings, rx_rings, ring_grps, 4865 cp_rings, vnics); 4866 flags = FUNC_VF_CFG_REQ_FLAGS_TX_ASSETS_TEST | 4867 FUNC_VF_CFG_REQ_FLAGS_RX_ASSETS_TEST | 4868 FUNC_VF_CFG_REQ_FLAGS_CMPL_ASSETS_TEST | 4869 FUNC_VF_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST | 4870 FUNC_VF_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST | 4871 FUNC_VF_CFG_REQ_FLAGS_VNIC_ASSETS_TEST; 4872 4873 req.flags = cpu_to_le32(flags); 4874 rc = hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4875 if (rc) 4876 return -ENOMEM; 4877 return 0; 4878 } 4879 4880 static int bnxt_hwrm_check_pf_rings(struct bnxt *bp, int tx_rings, int rx_rings, 4881 int ring_grps, int cp_rings, int vnics) 4882 { 4883 struct hwrm_func_cfg_input req = {0}; 4884 u32 flags; 4885 int rc; 4886 4887 __bnxt_hwrm_reserve_pf_rings(bp, &req, tx_rings, rx_rings, ring_grps, 4888 cp_rings, vnics); 4889 flags = FUNC_CFG_REQ_FLAGS_TX_ASSETS_TEST; 4890 if (BNXT_NEW_RM(bp)) 4891 flags |= FUNC_CFG_REQ_FLAGS_RX_ASSETS_TEST | 4892 FUNC_CFG_REQ_FLAGS_CMPL_ASSETS_TEST | 4893 FUNC_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST | 4894 FUNC_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST | 4895 FUNC_CFG_REQ_FLAGS_VNIC_ASSETS_TEST; 4896 4897 req.flags = cpu_to_le32(flags); 4898 rc = hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4899 if (rc) 4900 return -ENOMEM; 4901 return 0; 4902 } 4903 4904 static int bnxt_hwrm_check_rings(struct bnxt *bp, int tx_rings, int rx_rings, 4905 int ring_grps, int cp_rings, int vnics) 4906 { 4907 if (bp->hwrm_spec_code < 0x10801) 4908 return 0; 4909 4910 if (BNXT_PF(bp)) 4911 return bnxt_hwrm_check_pf_rings(bp, tx_rings, rx_rings, 4912 ring_grps, cp_rings, vnics); 4913 4914 return bnxt_hwrm_check_vf_rings(bp, tx_rings, rx_rings, ring_grps, 4915 cp_rings, vnics); 4916 } 4917 4918 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal, 4919 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req) 4920 { 4921 u16 val, tmr, max, flags; 4922 4923 max = hw_coal->bufs_per_record * 128; 4924 if (hw_coal->budget) 4925 max = hw_coal->bufs_per_record * hw_coal->budget; 4926 4927 val = clamp_t(u16, hw_coal->coal_bufs, 1, max); 4928 req->num_cmpl_aggr_int = cpu_to_le16(val); 4929 4930 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */ 4931 val = min_t(u16, val, 63); 4932 req->num_cmpl_dma_aggr = cpu_to_le16(val); 4933 4934 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */ 4935 val = clamp_t(u16, hw_coal->coal_bufs_irq, 1, 63); 4936 req->num_cmpl_dma_aggr_during_int = cpu_to_le16(val); 4937 4938 tmr = BNXT_USEC_TO_COAL_TIMER(hw_coal->coal_ticks); 4939 tmr = max_t(u16, tmr, 1); 4940 req->int_lat_tmr_max = cpu_to_le16(tmr); 4941 4942 /* min timer set to 1/2 of interrupt timer */ 4943 val = tmr / 2; 4944 req->int_lat_tmr_min = cpu_to_le16(val); 4945 4946 /* buf timer set to 1/4 of interrupt timer */ 4947 val = max_t(u16, tmr / 4, 1); 4948 req->cmpl_aggr_dma_tmr = cpu_to_le16(val); 4949 4950 tmr = BNXT_USEC_TO_COAL_TIMER(hw_coal->coal_ticks_irq); 4951 tmr = max_t(u16, tmr, 1); 4952 req->cmpl_aggr_dma_tmr_during_int = cpu_to_le16(tmr); 4953 4954 flags = RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET; 4955 if (hw_coal->idle_thresh && hw_coal->coal_ticks < hw_coal->idle_thresh) 4956 flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE; 4957 req->flags = cpu_to_le16(flags); 4958 } 4959 4960 int bnxt_hwrm_set_ring_coal(struct bnxt *bp, struct bnxt_napi *bnapi) 4961 { 4962 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx = {0}; 4963 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 4964 struct bnxt_coal coal; 4965 unsigned int grp_idx; 4966 4967 /* Tick values in micro seconds. 4968 * 1 coal_buf x bufs_per_record = 1 completion record. 4969 */ 4970 memcpy(&coal, &bp->rx_coal, sizeof(struct bnxt_coal)); 4971 4972 coal.coal_ticks = cpr->rx_ring_coal.coal_ticks; 4973 coal.coal_bufs = cpr->rx_ring_coal.coal_bufs; 4974 4975 if (!bnapi->rx_ring) 4976 return -ENODEV; 4977 4978 bnxt_hwrm_cmd_hdr_init(bp, &req_rx, 4979 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1); 4980 4981 bnxt_hwrm_set_coal_params(&coal, &req_rx); 4982 4983 grp_idx = bnapi->index; 4984 req_rx.ring_id = cpu_to_le16(bp->grp_info[grp_idx].cp_fw_ring_id); 4985 4986 return hwrm_send_message(bp, &req_rx, sizeof(req_rx), 4987 HWRM_CMD_TIMEOUT); 4988 } 4989 4990 int bnxt_hwrm_set_coal(struct bnxt *bp) 4991 { 4992 int i, rc = 0; 4993 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx = {0}, 4994 req_tx = {0}, *req; 4995 4996 bnxt_hwrm_cmd_hdr_init(bp, &req_rx, 4997 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1); 4998 bnxt_hwrm_cmd_hdr_init(bp, &req_tx, 4999 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1); 5000 5001 bnxt_hwrm_set_coal_params(&bp->rx_coal, &req_rx); 5002 bnxt_hwrm_set_coal_params(&bp->tx_coal, &req_tx); 5003 5004 mutex_lock(&bp->hwrm_cmd_lock); 5005 for (i = 0; i < bp->cp_nr_rings; i++) { 5006 struct bnxt_napi *bnapi = bp->bnapi[i]; 5007 5008 req = &req_rx; 5009 if (!bnapi->rx_ring) 5010 req = &req_tx; 5011 req->ring_id = cpu_to_le16(bp->grp_info[i].cp_fw_ring_id); 5012 5013 rc = _hwrm_send_message(bp, req, sizeof(*req), 5014 HWRM_CMD_TIMEOUT); 5015 if (rc) 5016 break; 5017 } 5018 mutex_unlock(&bp->hwrm_cmd_lock); 5019 return rc; 5020 } 5021 5022 static int bnxt_hwrm_stat_ctx_free(struct bnxt *bp) 5023 { 5024 int rc = 0, i; 5025 struct hwrm_stat_ctx_free_input req = {0}; 5026 5027 if (!bp->bnapi) 5028 return 0; 5029 5030 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 5031 return 0; 5032 5033 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_FREE, -1, -1); 5034 5035 mutex_lock(&bp->hwrm_cmd_lock); 5036 for (i = 0; i < bp->cp_nr_rings; i++) { 5037 struct bnxt_napi *bnapi = bp->bnapi[i]; 5038 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 5039 5040 if (cpr->hw_stats_ctx_id != INVALID_STATS_CTX_ID) { 5041 req.stat_ctx_id = cpu_to_le32(cpr->hw_stats_ctx_id); 5042 5043 rc = _hwrm_send_message(bp, &req, sizeof(req), 5044 HWRM_CMD_TIMEOUT); 5045 if (rc) 5046 break; 5047 5048 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID; 5049 } 5050 } 5051 mutex_unlock(&bp->hwrm_cmd_lock); 5052 return rc; 5053 } 5054 5055 static int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp) 5056 { 5057 int rc = 0, i; 5058 struct hwrm_stat_ctx_alloc_input req = {0}; 5059 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr; 5060 5061 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 5062 return 0; 5063 5064 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_ALLOC, -1, -1); 5065 5066 req.update_period_ms = cpu_to_le32(bp->stats_coal_ticks / 1000); 5067 5068 mutex_lock(&bp->hwrm_cmd_lock); 5069 for (i = 0; i < bp->cp_nr_rings; i++) { 5070 struct bnxt_napi *bnapi = bp->bnapi[i]; 5071 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 5072 5073 req.stats_dma_addr = cpu_to_le64(cpr->hw_stats_map); 5074 5075 rc = _hwrm_send_message(bp, &req, sizeof(req), 5076 HWRM_CMD_TIMEOUT); 5077 if (rc) 5078 break; 5079 5080 cpr->hw_stats_ctx_id = le32_to_cpu(resp->stat_ctx_id); 5081 5082 bp->grp_info[i].fw_stats_ctx = cpr->hw_stats_ctx_id; 5083 } 5084 mutex_unlock(&bp->hwrm_cmd_lock); 5085 return rc; 5086 } 5087 5088 static int bnxt_hwrm_func_qcfg(struct bnxt *bp) 5089 { 5090 struct hwrm_func_qcfg_input req = {0}; 5091 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr; 5092 u16 flags; 5093 int rc; 5094 5095 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1); 5096 req.fid = cpu_to_le16(0xffff); 5097 mutex_lock(&bp->hwrm_cmd_lock); 5098 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5099 if (rc) 5100 goto func_qcfg_exit; 5101 5102 #ifdef CONFIG_BNXT_SRIOV 5103 if (BNXT_VF(bp)) { 5104 struct bnxt_vf_info *vf = &bp->vf; 5105 5106 vf->vlan = le16_to_cpu(resp->vlan) & VLAN_VID_MASK; 5107 } 5108 #endif 5109 flags = le16_to_cpu(resp->flags); 5110 if (flags & (FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED | 5111 FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED)) { 5112 bp->fw_cap |= BNXT_FW_CAP_LLDP_AGENT; 5113 if (flags & FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED) 5114 bp->fw_cap |= BNXT_FW_CAP_DCBX_AGENT; 5115 } 5116 if (BNXT_PF(bp) && (flags & FUNC_QCFG_RESP_FLAGS_MULTI_HOST)) 5117 bp->flags |= BNXT_FLAG_MULTI_HOST; 5118 5119 switch (resp->port_partition_type) { 5120 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0: 5121 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5: 5122 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0: 5123 bp->port_partition_type = resp->port_partition_type; 5124 break; 5125 } 5126 if (bp->hwrm_spec_code < 0x10707 || 5127 resp->evb_mode == FUNC_QCFG_RESP_EVB_MODE_VEB) 5128 bp->br_mode = BRIDGE_MODE_VEB; 5129 else if (resp->evb_mode == FUNC_QCFG_RESP_EVB_MODE_VEPA) 5130 bp->br_mode = BRIDGE_MODE_VEPA; 5131 else 5132 bp->br_mode = BRIDGE_MODE_UNDEF; 5133 5134 bp->max_mtu = le16_to_cpu(resp->max_mtu_configured); 5135 if (!bp->max_mtu) 5136 bp->max_mtu = BNXT_MAX_MTU; 5137 5138 func_qcfg_exit: 5139 mutex_unlock(&bp->hwrm_cmd_lock); 5140 return rc; 5141 } 5142 5143 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp, bool all) 5144 { 5145 struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr; 5146 struct hwrm_func_resource_qcaps_input req = {0}; 5147 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 5148 int rc; 5149 5150 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESOURCE_QCAPS, -1, -1); 5151 req.fid = cpu_to_le16(0xffff); 5152 5153 mutex_lock(&bp->hwrm_cmd_lock); 5154 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5155 if (rc) { 5156 rc = -EIO; 5157 goto hwrm_func_resc_qcaps_exit; 5158 } 5159 5160 hw_resc->max_tx_sch_inputs = le16_to_cpu(resp->max_tx_scheduler_inputs); 5161 if (!all) 5162 goto hwrm_func_resc_qcaps_exit; 5163 5164 hw_resc->min_rsscos_ctxs = le16_to_cpu(resp->min_rsscos_ctx); 5165 hw_resc->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx); 5166 hw_resc->min_cp_rings = le16_to_cpu(resp->min_cmpl_rings); 5167 hw_resc->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings); 5168 hw_resc->min_tx_rings = le16_to_cpu(resp->min_tx_rings); 5169 hw_resc->max_tx_rings = le16_to_cpu(resp->max_tx_rings); 5170 hw_resc->min_rx_rings = le16_to_cpu(resp->min_rx_rings); 5171 hw_resc->max_rx_rings = le16_to_cpu(resp->max_rx_rings); 5172 hw_resc->min_hw_ring_grps = le16_to_cpu(resp->min_hw_ring_grps); 5173 hw_resc->max_hw_ring_grps = le16_to_cpu(resp->max_hw_ring_grps); 5174 hw_resc->min_l2_ctxs = le16_to_cpu(resp->min_l2_ctxs); 5175 hw_resc->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs); 5176 hw_resc->min_vnics = le16_to_cpu(resp->min_vnics); 5177 hw_resc->max_vnics = le16_to_cpu(resp->max_vnics); 5178 hw_resc->min_stat_ctxs = le16_to_cpu(resp->min_stat_ctx); 5179 hw_resc->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx); 5180 5181 if (BNXT_PF(bp)) { 5182 struct bnxt_pf_info *pf = &bp->pf; 5183 5184 pf->vf_resv_strategy = 5185 le16_to_cpu(resp->vf_reservation_strategy); 5186 if (pf->vf_resv_strategy > BNXT_VF_RESV_STRATEGY_MINIMAL_STATIC) 5187 pf->vf_resv_strategy = BNXT_VF_RESV_STRATEGY_MAXIMAL; 5188 } 5189 hwrm_func_resc_qcaps_exit: 5190 mutex_unlock(&bp->hwrm_cmd_lock); 5191 return rc; 5192 } 5193 5194 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp) 5195 { 5196 int rc = 0; 5197 struct hwrm_func_qcaps_input req = {0}; 5198 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr; 5199 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 5200 u32 flags; 5201 5202 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCAPS, -1, -1); 5203 req.fid = cpu_to_le16(0xffff); 5204 5205 mutex_lock(&bp->hwrm_cmd_lock); 5206 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5207 if (rc) 5208 goto hwrm_func_qcaps_exit; 5209 5210 flags = le32_to_cpu(resp->flags); 5211 if (flags & FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED) 5212 bp->flags |= BNXT_FLAG_ROCEV1_CAP; 5213 if (flags & FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED) 5214 bp->flags |= BNXT_FLAG_ROCEV2_CAP; 5215 5216 bp->tx_push_thresh = 0; 5217 if (flags & FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED) 5218 bp->tx_push_thresh = BNXT_TX_PUSH_THRESH; 5219 5220 hw_resc->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx); 5221 hw_resc->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings); 5222 hw_resc->max_tx_rings = le16_to_cpu(resp->max_tx_rings); 5223 hw_resc->max_rx_rings = le16_to_cpu(resp->max_rx_rings); 5224 hw_resc->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps); 5225 if (!hw_resc->max_hw_ring_grps) 5226 hw_resc->max_hw_ring_grps = hw_resc->max_tx_rings; 5227 hw_resc->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs); 5228 hw_resc->max_vnics = le16_to_cpu(resp->max_vnics); 5229 hw_resc->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx); 5230 5231 if (BNXT_PF(bp)) { 5232 struct bnxt_pf_info *pf = &bp->pf; 5233 5234 pf->fw_fid = le16_to_cpu(resp->fid); 5235 pf->port_id = le16_to_cpu(resp->port_id); 5236 bp->dev->dev_port = pf->port_id; 5237 memcpy(pf->mac_addr, resp->mac_address, ETH_ALEN); 5238 pf->first_vf_id = le16_to_cpu(resp->first_vf_id); 5239 pf->max_vfs = le16_to_cpu(resp->max_vfs); 5240 pf->max_encap_records = le32_to_cpu(resp->max_encap_records); 5241 pf->max_decap_records = le32_to_cpu(resp->max_decap_records); 5242 pf->max_tx_em_flows = le32_to_cpu(resp->max_tx_em_flows); 5243 pf->max_tx_wm_flows = le32_to_cpu(resp->max_tx_wm_flows); 5244 pf->max_rx_em_flows = le32_to_cpu(resp->max_rx_em_flows); 5245 pf->max_rx_wm_flows = le32_to_cpu(resp->max_rx_wm_flows); 5246 if (flags & FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED) 5247 bp->flags |= BNXT_FLAG_WOL_CAP; 5248 } else { 5249 #ifdef CONFIG_BNXT_SRIOV 5250 struct bnxt_vf_info *vf = &bp->vf; 5251 5252 vf->fw_fid = le16_to_cpu(resp->fid); 5253 memcpy(vf->mac_addr, resp->mac_address, ETH_ALEN); 5254 #endif 5255 } 5256 5257 hwrm_func_qcaps_exit: 5258 mutex_unlock(&bp->hwrm_cmd_lock); 5259 return rc; 5260 } 5261 5262 static int bnxt_hwrm_func_qcaps(struct bnxt *bp) 5263 { 5264 int rc; 5265 5266 rc = __bnxt_hwrm_func_qcaps(bp); 5267 if (rc) 5268 return rc; 5269 if (bp->hwrm_spec_code >= 0x10803) { 5270 rc = bnxt_hwrm_func_resc_qcaps(bp, true); 5271 if (!rc) 5272 bp->fw_cap |= BNXT_FW_CAP_NEW_RM; 5273 } 5274 return 0; 5275 } 5276 5277 static int bnxt_hwrm_func_reset(struct bnxt *bp) 5278 { 5279 struct hwrm_func_reset_input req = {0}; 5280 5281 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESET, -1, -1); 5282 req.enables = 0; 5283 5284 return hwrm_send_message(bp, &req, sizeof(req), HWRM_RESET_TIMEOUT); 5285 } 5286 5287 static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp) 5288 { 5289 int rc = 0; 5290 struct hwrm_queue_qportcfg_input req = {0}; 5291 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr; 5292 u8 i, j, *qptr; 5293 bool no_rdma; 5294 5295 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_QUEUE_QPORTCFG, -1, -1); 5296 5297 mutex_lock(&bp->hwrm_cmd_lock); 5298 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5299 if (rc) 5300 goto qportcfg_exit; 5301 5302 if (!resp->max_configurable_queues) { 5303 rc = -EINVAL; 5304 goto qportcfg_exit; 5305 } 5306 bp->max_tc = resp->max_configurable_queues; 5307 bp->max_lltc = resp->max_configurable_lossless_queues; 5308 if (bp->max_tc > BNXT_MAX_QUEUE) 5309 bp->max_tc = BNXT_MAX_QUEUE; 5310 5311 no_rdma = !(bp->flags & BNXT_FLAG_ROCE_CAP); 5312 qptr = &resp->queue_id0; 5313 for (i = 0, j = 0; i < bp->max_tc; i++) { 5314 bp->q_info[j].queue_id = *qptr++; 5315 bp->q_info[j].queue_profile = *qptr++; 5316 bp->tc_to_qidx[j] = j; 5317 if (!BNXT_CNPQ(bp->q_info[j].queue_profile) || 5318 (no_rdma && BNXT_PF(bp))) 5319 j++; 5320 } 5321 bp->max_tc = max_t(u8, j, 1); 5322 5323 if (resp->queue_cfg_info & QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG) 5324 bp->max_tc = 1; 5325 5326 if (bp->max_lltc > bp->max_tc) 5327 bp->max_lltc = bp->max_tc; 5328 5329 qportcfg_exit: 5330 mutex_unlock(&bp->hwrm_cmd_lock); 5331 return rc; 5332 } 5333 5334 static int bnxt_hwrm_ver_get(struct bnxt *bp) 5335 { 5336 int rc; 5337 struct hwrm_ver_get_input req = {0}; 5338 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr; 5339 u32 dev_caps_cfg; 5340 5341 bp->hwrm_max_req_len = HWRM_MAX_REQ_LEN; 5342 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VER_GET, -1, -1); 5343 req.hwrm_intf_maj = HWRM_VERSION_MAJOR; 5344 req.hwrm_intf_min = HWRM_VERSION_MINOR; 5345 req.hwrm_intf_upd = HWRM_VERSION_UPDATE; 5346 mutex_lock(&bp->hwrm_cmd_lock); 5347 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5348 if (rc) 5349 goto hwrm_ver_get_exit; 5350 5351 memcpy(&bp->ver_resp, resp, sizeof(struct hwrm_ver_get_output)); 5352 5353 bp->hwrm_spec_code = resp->hwrm_intf_maj_8b << 16 | 5354 resp->hwrm_intf_min_8b << 8 | 5355 resp->hwrm_intf_upd_8b; 5356 if (resp->hwrm_intf_maj_8b < 1) { 5357 netdev_warn(bp->dev, "HWRM interface %d.%d.%d is older than 1.0.0.\n", 5358 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b, 5359 resp->hwrm_intf_upd_8b); 5360 netdev_warn(bp->dev, "Please update firmware with HWRM interface 1.0.0 or newer.\n"); 5361 } 5362 snprintf(bp->fw_ver_str, BC_HWRM_STR_LEN, "%d.%d.%d.%d", 5363 resp->hwrm_fw_maj_8b, resp->hwrm_fw_min_8b, 5364 resp->hwrm_fw_bld_8b, resp->hwrm_fw_rsvd_8b); 5365 5366 bp->hwrm_cmd_timeout = le16_to_cpu(resp->def_req_timeout); 5367 if (!bp->hwrm_cmd_timeout) 5368 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT; 5369 5370 if (resp->hwrm_intf_maj_8b >= 1) 5371 bp->hwrm_max_req_len = le16_to_cpu(resp->max_req_win_len); 5372 5373 bp->chip_num = le16_to_cpu(resp->chip_num); 5374 if (bp->chip_num == CHIP_NUM_58700 && !resp->chip_rev && 5375 !resp->chip_metal) 5376 bp->flags |= BNXT_FLAG_CHIP_NITRO_A0; 5377 5378 dev_caps_cfg = le32_to_cpu(resp->dev_caps_cfg); 5379 if ((dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) && 5380 (dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) 5381 bp->fw_cap |= BNXT_FW_CAP_SHORT_CMD; 5382 5383 hwrm_ver_get_exit: 5384 mutex_unlock(&bp->hwrm_cmd_lock); 5385 return rc; 5386 } 5387 5388 int bnxt_hwrm_fw_set_time(struct bnxt *bp) 5389 { 5390 struct hwrm_fw_set_time_input req = {0}; 5391 struct tm tm; 5392 time64_t now = ktime_get_real_seconds(); 5393 5394 if ((BNXT_VF(bp) && bp->hwrm_spec_code < 0x10901) || 5395 bp->hwrm_spec_code < 0x10400) 5396 return -EOPNOTSUPP; 5397 5398 time64_to_tm(now, 0, &tm); 5399 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FW_SET_TIME, -1, -1); 5400 req.year = cpu_to_le16(1900 + tm.tm_year); 5401 req.month = 1 + tm.tm_mon; 5402 req.day = tm.tm_mday; 5403 req.hour = tm.tm_hour; 5404 req.minute = tm.tm_min; 5405 req.second = tm.tm_sec; 5406 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5407 } 5408 5409 static int bnxt_hwrm_port_qstats(struct bnxt *bp) 5410 { 5411 int rc; 5412 struct bnxt_pf_info *pf = &bp->pf; 5413 struct hwrm_port_qstats_input req = {0}; 5414 5415 if (!(bp->flags & BNXT_FLAG_PORT_STATS)) 5416 return 0; 5417 5418 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_QSTATS, -1, -1); 5419 req.port_id = cpu_to_le16(pf->port_id); 5420 req.tx_stat_host_addr = cpu_to_le64(bp->hw_tx_port_stats_map); 5421 req.rx_stat_host_addr = cpu_to_le64(bp->hw_rx_port_stats_map); 5422 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5423 return rc; 5424 } 5425 5426 static int bnxt_hwrm_port_qstats_ext(struct bnxt *bp) 5427 { 5428 struct hwrm_port_qstats_ext_input req = {0}; 5429 struct bnxt_pf_info *pf = &bp->pf; 5430 5431 if (!(bp->flags & BNXT_FLAG_PORT_STATS_EXT)) 5432 return 0; 5433 5434 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_QSTATS_EXT, -1, -1); 5435 req.port_id = cpu_to_le16(pf->port_id); 5436 req.rx_stat_size = cpu_to_le16(sizeof(struct rx_port_stats_ext)); 5437 req.rx_stat_host_addr = cpu_to_le64(bp->hw_rx_port_stats_ext_map); 5438 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5439 } 5440 5441 static void bnxt_hwrm_free_tunnel_ports(struct bnxt *bp) 5442 { 5443 if (bp->vxlan_port_cnt) { 5444 bnxt_hwrm_tunnel_dst_port_free( 5445 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN); 5446 } 5447 bp->vxlan_port_cnt = 0; 5448 if (bp->nge_port_cnt) { 5449 bnxt_hwrm_tunnel_dst_port_free( 5450 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE); 5451 } 5452 bp->nge_port_cnt = 0; 5453 } 5454 5455 static int bnxt_set_tpa(struct bnxt *bp, bool set_tpa) 5456 { 5457 int rc, i; 5458 u32 tpa_flags = 0; 5459 5460 if (set_tpa) 5461 tpa_flags = bp->flags & BNXT_FLAG_TPA; 5462 for (i = 0; i < bp->nr_vnics; i++) { 5463 rc = bnxt_hwrm_vnic_set_tpa(bp, i, tpa_flags); 5464 if (rc) { 5465 netdev_err(bp->dev, "hwrm vnic set tpa failure rc for vnic %d: %x\n", 5466 i, rc); 5467 return rc; 5468 } 5469 } 5470 return 0; 5471 } 5472 5473 static void bnxt_hwrm_clear_vnic_rss(struct bnxt *bp) 5474 { 5475 int i; 5476 5477 for (i = 0; i < bp->nr_vnics; i++) 5478 bnxt_hwrm_vnic_set_rss(bp, i, false); 5479 } 5480 5481 static void bnxt_hwrm_resource_free(struct bnxt *bp, bool close_path, 5482 bool irq_re_init) 5483 { 5484 if (bp->vnic_info) { 5485 bnxt_hwrm_clear_vnic_filter(bp); 5486 /* clear all RSS setting before free vnic ctx */ 5487 bnxt_hwrm_clear_vnic_rss(bp); 5488 bnxt_hwrm_vnic_ctx_free(bp); 5489 /* before free the vnic, undo the vnic tpa settings */ 5490 if (bp->flags & BNXT_FLAG_TPA) 5491 bnxt_set_tpa(bp, false); 5492 bnxt_hwrm_vnic_free(bp); 5493 } 5494 bnxt_hwrm_ring_free(bp, close_path); 5495 bnxt_hwrm_ring_grp_free(bp); 5496 if (irq_re_init) { 5497 bnxt_hwrm_stat_ctx_free(bp); 5498 bnxt_hwrm_free_tunnel_ports(bp); 5499 } 5500 } 5501 5502 static int bnxt_hwrm_set_br_mode(struct bnxt *bp, u16 br_mode) 5503 { 5504 struct hwrm_func_cfg_input req = {0}; 5505 int rc; 5506 5507 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1); 5508 req.fid = cpu_to_le16(0xffff); 5509 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_EVB_MODE); 5510 if (br_mode == BRIDGE_MODE_VEB) 5511 req.evb_mode = FUNC_CFG_REQ_EVB_MODE_VEB; 5512 else if (br_mode == BRIDGE_MODE_VEPA) 5513 req.evb_mode = FUNC_CFG_REQ_EVB_MODE_VEPA; 5514 else 5515 return -EINVAL; 5516 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5517 if (rc) 5518 rc = -EIO; 5519 return rc; 5520 } 5521 5522 static int bnxt_hwrm_set_cache_line_size(struct bnxt *bp, int size) 5523 { 5524 struct hwrm_func_cfg_input req = {0}; 5525 int rc; 5526 5527 if (BNXT_VF(bp) || bp->hwrm_spec_code < 0x10803) 5528 return 0; 5529 5530 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1); 5531 req.fid = cpu_to_le16(0xffff); 5532 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_CACHE_LINESIZE); 5533 req.options = FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_64; 5534 if (size == 128) 5535 req.options = FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128; 5536 5537 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5538 if (rc) 5539 rc = -EIO; 5540 return rc; 5541 } 5542 5543 static int bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id) 5544 { 5545 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 5546 int rc; 5547 5548 if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG) 5549 goto skip_rss_ctx; 5550 5551 /* allocate context for vnic */ 5552 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 0); 5553 if (rc) { 5554 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n", 5555 vnic_id, rc); 5556 goto vnic_setup_err; 5557 } 5558 bp->rsscos_nr_ctxs++; 5559 5560 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) { 5561 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 1); 5562 if (rc) { 5563 netdev_err(bp->dev, "hwrm vnic %d cos ctx alloc failure rc: %x\n", 5564 vnic_id, rc); 5565 goto vnic_setup_err; 5566 } 5567 bp->rsscos_nr_ctxs++; 5568 } 5569 5570 skip_rss_ctx: 5571 /* configure default vnic, ring grp */ 5572 rc = bnxt_hwrm_vnic_cfg(bp, vnic_id); 5573 if (rc) { 5574 netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n", 5575 vnic_id, rc); 5576 goto vnic_setup_err; 5577 } 5578 5579 /* Enable RSS hashing on vnic */ 5580 rc = bnxt_hwrm_vnic_set_rss(bp, vnic_id, true); 5581 if (rc) { 5582 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %x\n", 5583 vnic_id, rc); 5584 goto vnic_setup_err; 5585 } 5586 5587 if (bp->flags & BNXT_FLAG_AGG_RINGS) { 5588 rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id); 5589 if (rc) { 5590 netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n", 5591 vnic_id, rc); 5592 } 5593 } 5594 5595 vnic_setup_err: 5596 return rc; 5597 } 5598 5599 static int bnxt_alloc_rfs_vnics(struct bnxt *bp) 5600 { 5601 #ifdef CONFIG_RFS_ACCEL 5602 int i, rc = 0; 5603 5604 for (i = 0; i < bp->rx_nr_rings; i++) { 5605 struct bnxt_vnic_info *vnic; 5606 u16 vnic_id = i + 1; 5607 u16 ring_id = i; 5608 5609 if (vnic_id >= bp->nr_vnics) 5610 break; 5611 5612 vnic = &bp->vnic_info[vnic_id]; 5613 vnic->flags |= BNXT_VNIC_RFS_FLAG; 5614 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP) 5615 vnic->flags |= BNXT_VNIC_RFS_NEW_RSS_FLAG; 5616 rc = bnxt_hwrm_vnic_alloc(bp, vnic_id, ring_id, 1); 5617 if (rc) { 5618 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n", 5619 vnic_id, rc); 5620 break; 5621 } 5622 rc = bnxt_setup_vnic(bp, vnic_id); 5623 if (rc) 5624 break; 5625 } 5626 return rc; 5627 #else 5628 return 0; 5629 #endif 5630 } 5631 5632 /* Allow PF and VF with default VLAN to be in promiscuous mode */ 5633 static bool bnxt_promisc_ok(struct bnxt *bp) 5634 { 5635 #ifdef CONFIG_BNXT_SRIOV 5636 if (BNXT_VF(bp) && !bp->vf.vlan) 5637 return false; 5638 #endif 5639 return true; 5640 } 5641 5642 static int bnxt_setup_nitroa0_vnic(struct bnxt *bp) 5643 { 5644 unsigned int rc = 0; 5645 5646 rc = bnxt_hwrm_vnic_alloc(bp, 1, bp->rx_nr_rings - 1, 1); 5647 if (rc) { 5648 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n", 5649 rc); 5650 return rc; 5651 } 5652 5653 rc = bnxt_hwrm_vnic_cfg(bp, 1); 5654 if (rc) { 5655 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n", 5656 rc); 5657 return rc; 5658 } 5659 return rc; 5660 } 5661 5662 static int bnxt_cfg_rx_mode(struct bnxt *); 5663 static bool bnxt_mc_list_updated(struct bnxt *, u32 *); 5664 5665 static int bnxt_init_chip(struct bnxt *bp, bool irq_re_init) 5666 { 5667 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 5668 int rc = 0; 5669 unsigned int rx_nr_rings = bp->rx_nr_rings; 5670 5671 if (irq_re_init) { 5672 rc = bnxt_hwrm_stat_ctx_alloc(bp); 5673 if (rc) { 5674 netdev_err(bp->dev, "hwrm stat ctx alloc failure rc: %x\n", 5675 rc); 5676 goto err_out; 5677 } 5678 } 5679 5680 rc = bnxt_hwrm_ring_alloc(bp); 5681 if (rc) { 5682 netdev_err(bp->dev, "hwrm ring alloc failure rc: %x\n", rc); 5683 goto err_out; 5684 } 5685 5686 rc = bnxt_hwrm_ring_grp_alloc(bp); 5687 if (rc) { 5688 netdev_err(bp->dev, "hwrm_ring_grp alloc failure: %x\n", rc); 5689 goto err_out; 5690 } 5691 5692 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 5693 rx_nr_rings--; 5694 5695 /* default vnic 0 */ 5696 rc = bnxt_hwrm_vnic_alloc(bp, 0, 0, rx_nr_rings); 5697 if (rc) { 5698 netdev_err(bp->dev, "hwrm vnic alloc failure rc: %x\n", rc); 5699 goto err_out; 5700 } 5701 5702 rc = bnxt_setup_vnic(bp, 0); 5703 if (rc) 5704 goto err_out; 5705 5706 if (bp->flags & BNXT_FLAG_RFS) { 5707 rc = bnxt_alloc_rfs_vnics(bp); 5708 if (rc) 5709 goto err_out; 5710 } 5711 5712 if (bp->flags & BNXT_FLAG_TPA) { 5713 rc = bnxt_set_tpa(bp, true); 5714 if (rc) 5715 goto err_out; 5716 } 5717 5718 if (BNXT_VF(bp)) 5719 bnxt_update_vf_mac(bp); 5720 5721 /* Filter for default vnic 0 */ 5722 rc = bnxt_hwrm_set_vnic_filter(bp, 0, 0, bp->dev->dev_addr); 5723 if (rc) { 5724 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n", rc); 5725 goto err_out; 5726 } 5727 vnic->uc_filter_count = 1; 5728 5729 vnic->rx_mask = 0; 5730 if (bp->dev->flags & IFF_BROADCAST) 5731 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_BCAST; 5732 5733 if ((bp->dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp)) 5734 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS; 5735 5736 if (bp->dev->flags & IFF_ALLMULTI) { 5737 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST; 5738 vnic->mc_list_count = 0; 5739 } else { 5740 u32 mask = 0; 5741 5742 bnxt_mc_list_updated(bp, &mask); 5743 vnic->rx_mask |= mask; 5744 } 5745 5746 rc = bnxt_cfg_rx_mode(bp); 5747 if (rc) 5748 goto err_out; 5749 5750 rc = bnxt_hwrm_set_coal(bp); 5751 if (rc) 5752 netdev_warn(bp->dev, "HWRM set coalescing failure rc: %x\n", 5753 rc); 5754 5755 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) { 5756 rc = bnxt_setup_nitroa0_vnic(bp); 5757 if (rc) 5758 netdev_err(bp->dev, "Special vnic setup failure for NS2 A0 rc: %x\n", 5759 rc); 5760 } 5761 5762 if (BNXT_VF(bp)) { 5763 bnxt_hwrm_func_qcfg(bp); 5764 netdev_update_features(bp->dev); 5765 } 5766 5767 return 0; 5768 5769 err_out: 5770 bnxt_hwrm_resource_free(bp, 0, true); 5771 5772 return rc; 5773 } 5774 5775 static int bnxt_shutdown_nic(struct bnxt *bp, bool irq_re_init) 5776 { 5777 bnxt_hwrm_resource_free(bp, 1, irq_re_init); 5778 return 0; 5779 } 5780 5781 static int bnxt_init_nic(struct bnxt *bp, bool irq_re_init) 5782 { 5783 bnxt_init_cp_rings(bp); 5784 bnxt_init_rx_rings(bp); 5785 bnxt_init_tx_rings(bp); 5786 bnxt_init_ring_grps(bp, irq_re_init); 5787 bnxt_init_vnics(bp); 5788 5789 return bnxt_init_chip(bp, irq_re_init); 5790 } 5791 5792 static int bnxt_set_real_num_queues(struct bnxt *bp) 5793 { 5794 int rc; 5795 struct net_device *dev = bp->dev; 5796 5797 rc = netif_set_real_num_tx_queues(dev, bp->tx_nr_rings - 5798 bp->tx_nr_rings_xdp); 5799 if (rc) 5800 return rc; 5801 5802 rc = netif_set_real_num_rx_queues(dev, bp->rx_nr_rings); 5803 if (rc) 5804 return rc; 5805 5806 #ifdef CONFIG_RFS_ACCEL 5807 if (bp->flags & BNXT_FLAG_RFS) 5808 dev->rx_cpu_rmap = alloc_irq_cpu_rmap(bp->rx_nr_rings); 5809 #endif 5810 5811 return rc; 5812 } 5813 5814 static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max, 5815 bool shared) 5816 { 5817 int _rx = *rx, _tx = *tx; 5818 5819 if (shared) { 5820 *rx = min_t(int, _rx, max); 5821 *tx = min_t(int, _tx, max); 5822 } else { 5823 if (max < 2) 5824 return -ENOMEM; 5825 5826 while (_rx + _tx > max) { 5827 if (_rx > _tx && _rx > 1) 5828 _rx--; 5829 else if (_tx > 1) 5830 _tx--; 5831 } 5832 *rx = _rx; 5833 *tx = _tx; 5834 } 5835 return 0; 5836 } 5837 5838 static void bnxt_setup_msix(struct bnxt *bp) 5839 { 5840 const int len = sizeof(bp->irq_tbl[0].name); 5841 struct net_device *dev = bp->dev; 5842 int tcs, i; 5843 5844 tcs = netdev_get_num_tc(dev); 5845 if (tcs > 1) { 5846 int i, off, count; 5847 5848 for (i = 0; i < tcs; i++) { 5849 count = bp->tx_nr_rings_per_tc; 5850 off = i * count; 5851 netdev_set_tc_queue(dev, i, count, off); 5852 } 5853 } 5854 5855 for (i = 0; i < bp->cp_nr_rings; i++) { 5856 int map_idx = bnxt_cp_num_to_irq_num(bp, i); 5857 char *attr; 5858 5859 if (bp->flags & BNXT_FLAG_SHARED_RINGS) 5860 attr = "TxRx"; 5861 else if (i < bp->rx_nr_rings) 5862 attr = "rx"; 5863 else 5864 attr = "tx"; 5865 5866 snprintf(bp->irq_tbl[map_idx].name, len, "%s-%s-%d", dev->name, 5867 attr, i); 5868 bp->irq_tbl[map_idx].handler = bnxt_msix; 5869 } 5870 } 5871 5872 static void bnxt_setup_inta(struct bnxt *bp) 5873 { 5874 const int len = sizeof(bp->irq_tbl[0].name); 5875 5876 if (netdev_get_num_tc(bp->dev)) 5877 netdev_reset_tc(bp->dev); 5878 5879 snprintf(bp->irq_tbl[0].name, len, "%s-%s-%d", bp->dev->name, "TxRx", 5880 0); 5881 bp->irq_tbl[0].handler = bnxt_inta; 5882 } 5883 5884 static int bnxt_setup_int_mode(struct bnxt *bp) 5885 { 5886 int rc; 5887 5888 if (bp->flags & BNXT_FLAG_USING_MSIX) 5889 bnxt_setup_msix(bp); 5890 else 5891 bnxt_setup_inta(bp); 5892 5893 rc = bnxt_set_real_num_queues(bp); 5894 return rc; 5895 } 5896 5897 #ifdef CONFIG_RFS_ACCEL 5898 static unsigned int bnxt_get_max_func_rss_ctxs(struct bnxt *bp) 5899 { 5900 return bp->hw_resc.max_rsscos_ctxs; 5901 } 5902 5903 static unsigned int bnxt_get_max_func_vnics(struct bnxt *bp) 5904 { 5905 return bp->hw_resc.max_vnics; 5906 } 5907 #endif 5908 5909 unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt *bp) 5910 { 5911 return bp->hw_resc.max_stat_ctxs; 5912 } 5913 5914 void bnxt_set_max_func_stat_ctxs(struct bnxt *bp, unsigned int max) 5915 { 5916 bp->hw_resc.max_stat_ctxs = max; 5917 } 5918 5919 unsigned int bnxt_get_max_func_cp_rings(struct bnxt *bp) 5920 { 5921 return bp->hw_resc.max_cp_rings; 5922 } 5923 5924 unsigned int bnxt_get_max_func_cp_rings_for_en(struct bnxt *bp) 5925 { 5926 return bp->hw_resc.max_cp_rings - bnxt_get_ulp_msix_num(bp); 5927 } 5928 5929 static unsigned int bnxt_get_max_func_irqs(struct bnxt *bp) 5930 { 5931 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 5932 5933 return min_t(unsigned int, hw_resc->max_irqs, hw_resc->max_cp_rings); 5934 } 5935 5936 static void bnxt_set_max_func_irqs(struct bnxt *bp, unsigned int max_irqs) 5937 { 5938 bp->hw_resc.max_irqs = max_irqs; 5939 } 5940 5941 int bnxt_get_avail_msix(struct bnxt *bp, int num) 5942 { 5943 int max_cp = bnxt_get_max_func_cp_rings(bp); 5944 int max_irq = bnxt_get_max_func_irqs(bp); 5945 int total_req = bp->cp_nr_rings + num; 5946 int max_idx, avail_msix; 5947 5948 max_idx = min_t(int, bp->total_irqs, max_cp); 5949 avail_msix = max_idx - bp->cp_nr_rings; 5950 if (!BNXT_NEW_RM(bp) || avail_msix >= num) 5951 return avail_msix; 5952 5953 if (max_irq < total_req) { 5954 num = max_irq - bp->cp_nr_rings; 5955 if (num <= 0) 5956 return 0; 5957 } 5958 return num; 5959 } 5960 5961 static int bnxt_get_num_msix(struct bnxt *bp) 5962 { 5963 if (!BNXT_NEW_RM(bp)) 5964 return bnxt_get_max_func_irqs(bp); 5965 5966 return bnxt_cp_rings_in_use(bp); 5967 } 5968 5969 static int bnxt_init_msix(struct bnxt *bp) 5970 { 5971 int i, total_vecs, max, rc = 0, min = 1, ulp_msix; 5972 struct msix_entry *msix_ent; 5973 5974 total_vecs = bnxt_get_num_msix(bp); 5975 max = bnxt_get_max_func_irqs(bp); 5976 if (total_vecs > max) 5977 total_vecs = max; 5978 5979 if (!total_vecs) 5980 return 0; 5981 5982 msix_ent = kcalloc(total_vecs, sizeof(struct msix_entry), GFP_KERNEL); 5983 if (!msix_ent) 5984 return -ENOMEM; 5985 5986 for (i = 0; i < total_vecs; i++) { 5987 msix_ent[i].entry = i; 5988 msix_ent[i].vector = 0; 5989 } 5990 5991 if (!(bp->flags & BNXT_FLAG_SHARED_RINGS)) 5992 min = 2; 5993 5994 total_vecs = pci_enable_msix_range(bp->pdev, msix_ent, min, total_vecs); 5995 ulp_msix = bnxt_get_ulp_msix_num(bp); 5996 if (total_vecs < 0 || total_vecs < ulp_msix) { 5997 rc = -ENODEV; 5998 goto msix_setup_exit; 5999 } 6000 6001 bp->irq_tbl = kcalloc(total_vecs, sizeof(struct bnxt_irq), GFP_KERNEL); 6002 if (bp->irq_tbl) { 6003 for (i = 0; i < total_vecs; i++) 6004 bp->irq_tbl[i].vector = msix_ent[i].vector; 6005 6006 bp->total_irqs = total_vecs; 6007 /* Trim rings based upon num of vectors allocated */ 6008 rc = bnxt_trim_rings(bp, &bp->rx_nr_rings, &bp->tx_nr_rings, 6009 total_vecs - ulp_msix, min == 1); 6010 if (rc) 6011 goto msix_setup_exit; 6012 6013 bp->cp_nr_rings = (min == 1) ? 6014 max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) : 6015 bp->tx_nr_rings + bp->rx_nr_rings; 6016 6017 } else { 6018 rc = -ENOMEM; 6019 goto msix_setup_exit; 6020 } 6021 bp->flags |= BNXT_FLAG_USING_MSIX; 6022 kfree(msix_ent); 6023 return 0; 6024 6025 msix_setup_exit: 6026 netdev_err(bp->dev, "bnxt_init_msix err: %x\n", rc); 6027 kfree(bp->irq_tbl); 6028 bp->irq_tbl = NULL; 6029 pci_disable_msix(bp->pdev); 6030 kfree(msix_ent); 6031 return rc; 6032 } 6033 6034 static int bnxt_init_inta(struct bnxt *bp) 6035 { 6036 bp->irq_tbl = kcalloc(1, sizeof(struct bnxt_irq), GFP_KERNEL); 6037 if (!bp->irq_tbl) 6038 return -ENOMEM; 6039 6040 bp->total_irqs = 1; 6041 bp->rx_nr_rings = 1; 6042 bp->tx_nr_rings = 1; 6043 bp->cp_nr_rings = 1; 6044 bp->flags |= BNXT_FLAG_SHARED_RINGS; 6045 bp->irq_tbl[0].vector = bp->pdev->irq; 6046 return 0; 6047 } 6048 6049 static int bnxt_init_int_mode(struct bnxt *bp) 6050 { 6051 int rc = 0; 6052 6053 if (bp->flags & BNXT_FLAG_MSIX_CAP) 6054 rc = bnxt_init_msix(bp); 6055 6056 if (!(bp->flags & BNXT_FLAG_USING_MSIX) && BNXT_PF(bp)) { 6057 /* fallback to INTA */ 6058 rc = bnxt_init_inta(bp); 6059 } 6060 return rc; 6061 } 6062 6063 static void bnxt_clear_int_mode(struct bnxt *bp) 6064 { 6065 if (bp->flags & BNXT_FLAG_USING_MSIX) 6066 pci_disable_msix(bp->pdev); 6067 6068 kfree(bp->irq_tbl); 6069 bp->irq_tbl = NULL; 6070 bp->flags &= ~BNXT_FLAG_USING_MSIX; 6071 } 6072 6073 int bnxt_reserve_rings(struct bnxt *bp) 6074 { 6075 int tcs = netdev_get_num_tc(bp->dev); 6076 int rc; 6077 6078 if (!bnxt_need_reserve_rings(bp)) 6079 return 0; 6080 6081 rc = __bnxt_reserve_rings(bp); 6082 if (rc) { 6083 netdev_err(bp->dev, "ring reservation failure rc: %d\n", rc); 6084 return rc; 6085 } 6086 if (BNXT_NEW_RM(bp) && (bnxt_get_num_msix(bp) != bp->total_irqs)) { 6087 bnxt_ulp_irq_stop(bp); 6088 bnxt_clear_int_mode(bp); 6089 rc = bnxt_init_int_mode(bp); 6090 bnxt_ulp_irq_restart(bp, rc); 6091 if (rc) 6092 return rc; 6093 } 6094 if (tcs && (bp->tx_nr_rings_per_tc * tcs != bp->tx_nr_rings)) { 6095 netdev_err(bp->dev, "tx ring reservation failure\n"); 6096 netdev_reset_tc(bp->dev); 6097 bp->tx_nr_rings_per_tc = bp->tx_nr_rings; 6098 return -ENOMEM; 6099 } 6100 bp->num_stat_ctxs = bp->cp_nr_rings; 6101 return 0; 6102 } 6103 6104 static void bnxt_free_irq(struct bnxt *bp) 6105 { 6106 struct bnxt_irq *irq; 6107 int i; 6108 6109 #ifdef CONFIG_RFS_ACCEL 6110 free_irq_cpu_rmap(bp->dev->rx_cpu_rmap); 6111 bp->dev->rx_cpu_rmap = NULL; 6112 #endif 6113 if (!bp->irq_tbl || !bp->bnapi) 6114 return; 6115 6116 for (i = 0; i < bp->cp_nr_rings; i++) { 6117 int map_idx = bnxt_cp_num_to_irq_num(bp, i); 6118 6119 irq = &bp->irq_tbl[map_idx]; 6120 if (irq->requested) { 6121 if (irq->have_cpumask) { 6122 irq_set_affinity_hint(irq->vector, NULL); 6123 free_cpumask_var(irq->cpu_mask); 6124 irq->have_cpumask = 0; 6125 } 6126 free_irq(irq->vector, bp->bnapi[i]); 6127 } 6128 6129 irq->requested = 0; 6130 } 6131 } 6132 6133 static int bnxt_request_irq(struct bnxt *bp) 6134 { 6135 int i, j, rc = 0; 6136 unsigned long flags = 0; 6137 #ifdef CONFIG_RFS_ACCEL 6138 struct cpu_rmap *rmap; 6139 #endif 6140 6141 rc = bnxt_setup_int_mode(bp); 6142 if (rc) { 6143 netdev_err(bp->dev, "bnxt_setup_int_mode err: %x\n", 6144 rc); 6145 return rc; 6146 } 6147 #ifdef CONFIG_RFS_ACCEL 6148 rmap = bp->dev->rx_cpu_rmap; 6149 #endif 6150 if (!(bp->flags & BNXT_FLAG_USING_MSIX)) 6151 flags = IRQF_SHARED; 6152 6153 for (i = 0, j = 0; i < bp->cp_nr_rings; i++) { 6154 int map_idx = bnxt_cp_num_to_irq_num(bp, i); 6155 struct bnxt_irq *irq = &bp->irq_tbl[map_idx]; 6156 6157 #ifdef CONFIG_RFS_ACCEL 6158 if (rmap && bp->bnapi[i]->rx_ring) { 6159 rc = irq_cpu_rmap_add(rmap, irq->vector); 6160 if (rc) 6161 netdev_warn(bp->dev, "failed adding irq rmap for ring %d\n", 6162 j); 6163 j++; 6164 } 6165 #endif 6166 rc = request_irq(irq->vector, irq->handler, flags, irq->name, 6167 bp->bnapi[i]); 6168 if (rc) 6169 break; 6170 6171 irq->requested = 1; 6172 6173 if (zalloc_cpumask_var(&irq->cpu_mask, GFP_KERNEL)) { 6174 int numa_node = dev_to_node(&bp->pdev->dev); 6175 6176 irq->have_cpumask = 1; 6177 cpumask_set_cpu(cpumask_local_spread(i, numa_node), 6178 irq->cpu_mask); 6179 rc = irq_set_affinity_hint(irq->vector, irq->cpu_mask); 6180 if (rc) { 6181 netdev_warn(bp->dev, 6182 "Set affinity failed, IRQ = %d\n", 6183 irq->vector); 6184 break; 6185 } 6186 } 6187 } 6188 return rc; 6189 } 6190 6191 static void bnxt_del_napi(struct bnxt *bp) 6192 { 6193 int i; 6194 6195 if (!bp->bnapi) 6196 return; 6197 6198 for (i = 0; i < bp->cp_nr_rings; i++) { 6199 struct bnxt_napi *bnapi = bp->bnapi[i]; 6200 6201 napi_hash_del(&bnapi->napi); 6202 netif_napi_del(&bnapi->napi); 6203 } 6204 /* We called napi_hash_del() before netif_napi_del(), we need 6205 * to respect an RCU grace period before freeing napi structures. 6206 */ 6207 synchronize_net(); 6208 } 6209 6210 static void bnxt_init_napi(struct bnxt *bp) 6211 { 6212 int i; 6213 unsigned int cp_nr_rings = bp->cp_nr_rings; 6214 struct bnxt_napi *bnapi; 6215 6216 if (bp->flags & BNXT_FLAG_USING_MSIX) { 6217 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 6218 cp_nr_rings--; 6219 for (i = 0; i < cp_nr_rings; i++) { 6220 bnapi = bp->bnapi[i]; 6221 netif_napi_add(bp->dev, &bnapi->napi, 6222 bnxt_poll, 64); 6223 } 6224 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) { 6225 bnapi = bp->bnapi[cp_nr_rings]; 6226 netif_napi_add(bp->dev, &bnapi->napi, 6227 bnxt_poll_nitroa0, 64); 6228 } 6229 } else { 6230 bnapi = bp->bnapi[0]; 6231 netif_napi_add(bp->dev, &bnapi->napi, bnxt_poll, 64); 6232 } 6233 } 6234 6235 static void bnxt_disable_napi(struct bnxt *bp) 6236 { 6237 int i; 6238 6239 if (!bp->bnapi) 6240 return; 6241 6242 for (i = 0; i < bp->cp_nr_rings; i++) { 6243 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring; 6244 6245 if (bp->bnapi[i]->rx_ring) 6246 cancel_work_sync(&cpr->dim.work); 6247 6248 napi_disable(&bp->bnapi[i]->napi); 6249 } 6250 } 6251 6252 static void bnxt_enable_napi(struct bnxt *bp) 6253 { 6254 int i; 6255 6256 for (i = 0; i < bp->cp_nr_rings; i++) { 6257 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring; 6258 bp->bnapi[i]->in_reset = false; 6259 6260 if (bp->bnapi[i]->rx_ring) { 6261 INIT_WORK(&cpr->dim.work, bnxt_dim_work); 6262 cpr->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE; 6263 } 6264 napi_enable(&bp->bnapi[i]->napi); 6265 } 6266 } 6267 6268 void bnxt_tx_disable(struct bnxt *bp) 6269 { 6270 int i; 6271 struct bnxt_tx_ring_info *txr; 6272 6273 if (bp->tx_ring) { 6274 for (i = 0; i < bp->tx_nr_rings; i++) { 6275 txr = &bp->tx_ring[i]; 6276 txr->dev_state = BNXT_DEV_STATE_CLOSING; 6277 } 6278 } 6279 /* Stop all TX queues */ 6280 netif_tx_disable(bp->dev); 6281 netif_carrier_off(bp->dev); 6282 } 6283 6284 void bnxt_tx_enable(struct bnxt *bp) 6285 { 6286 int i; 6287 struct bnxt_tx_ring_info *txr; 6288 6289 for (i = 0; i < bp->tx_nr_rings; i++) { 6290 txr = &bp->tx_ring[i]; 6291 txr->dev_state = 0; 6292 } 6293 netif_tx_wake_all_queues(bp->dev); 6294 if (bp->link_info.link_up) 6295 netif_carrier_on(bp->dev); 6296 } 6297 6298 static void bnxt_report_link(struct bnxt *bp) 6299 { 6300 if (bp->link_info.link_up) { 6301 const char *duplex; 6302 const char *flow_ctrl; 6303 u32 speed; 6304 u16 fec; 6305 6306 netif_carrier_on(bp->dev); 6307 if (bp->link_info.duplex == BNXT_LINK_DUPLEX_FULL) 6308 duplex = "full"; 6309 else 6310 duplex = "half"; 6311 if (bp->link_info.pause == BNXT_LINK_PAUSE_BOTH) 6312 flow_ctrl = "ON - receive & transmit"; 6313 else if (bp->link_info.pause == BNXT_LINK_PAUSE_TX) 6314 flow_ctrl = "ON - transmit"; 6315 else if (bp->link_info.pause == BNXT_LINK_PAUSE_RX) 6316 flow_ctrl = "ON - receive"; 6317 else 6318 flow_ctrl = "none"; 6319 speed = bnxt_fw_to_ethtool_speed(bp->link_info.link_speed); 6320 netdev_info(bp->dev, "NIC Link is Up, %u Mbps %s duplex, Flow control: %s\n", 6321 speed, duplex, flow_ctrl); 6322 if (bp->flags & BNXT_FLAG_EEE_CAP) 6323 netdev_info(bp->dev, "EEE is %s\n", 6324 bp->eee.eee_active ? "active" : 6325 "not active"); 6326 fec = bp->link_info.fec_cfg; 6327 if (!(fec & PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED)) 6328 netdev_info(bp->dev, "FEC autoneg %s encodings: %s\n", 6329 (fec & BNXT_FEC_AUTONEG) ? "on" : "off", 6330 (fec & BNXT_FEC_ENC_BASE_R) ? "BaseR" : 6331 (fec & BNXT_FEC_ENC_RS) ? "RS" : "None"); 6332 } else { 6333 netif_carrier_off(bp->dev); 6334 netdev_err(bp->dev, "NIC Link is Down\n"); 6335 } 6336 } 6337 6338 static int bnxt_hwrm_phy_qcaps(struct bnxt *bp) 6339 { 6340 int rc = 0; 6341 struct hwrm_port_phy_qcaps_input req = {0}; 6342 struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr; 6343 struct bnxt_link_info *link_info = &bp->link_info; 6344 6345 if (bp->hwrm_spec_code < 0x10201) 6346 return 0; 6347 6348 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCAPS, -1, -1); 6349 6350 mutex_lock(&bp->hwrm_cmd_lock); 6351 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 6352 if (rc) 6353 goto hwrm_phy_qcaps_exit; 6354 6355 if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED) { 6356 struct ethtool_eee *eee = &bp->eee; 6357 u16 fw_speeds = le16_to_cpu(resp->supported_speeds_eee_mode); 6358 6359 bp->flags |= BNXT_FLAG_EEE_CAP; 6360 eee->supported = _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0); 6361 bp->lpi_tmr_lo = le32_to_cpu(resp->tx_lpi_timer_low) & 6362 PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK; 6363 bp->lpi_tmr_hi = le32_to_cpu(resp->valid_tx_lpi_timer_high) & 6364 PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK; 6365 } 6366 if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_EXTERNAL_LPBK_SUPPORTED) { 6367 if (bp->test_info) 6368 bp->test_info->flags |= BNXT_TEST_FL_EXT_LPBK; 6369 } 6370 if (resp->supported_speeds_auto_mode) 6371 link_info->support_auto_speeds = 6372 le16_to_cpu(resp->supported_speeds_auto_mode); 6373 6374 bp->port_count = resp->port_cnt; 6375 6376 hwrm_phy_qcaps_exit: 6377 mutex_unlock(&bp->hwrm_cmd_lock); 6378 return rc; 6379 } 6380 6381 static int bnxt_update_link(struct bnxt *bp, bool chng_link_state) 6382 { 6383 int rc = 0; 6384 struct bnxt_link_info *link_info = &bp->link_info; 6385 struct hwrm_port_phy_qcfg_input req = {0}; 6386 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr; 6387 u8 link_up = link_info->link_up; 6388 u16 diff; 6389 6390 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCFG, -1, -1); 6391 6392 mutex_lock(&bp->hwrm_cmd_lock); 6393 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 6394 if (rc) { 6395 mutex_unlock(&bp->hwrm_cmd_lock); 6396 return rc; 6397 } 6398 6399 memcpy(&link_info->phy_qcfg_resp, resp, sizeof(*resp)); 6400 link_info->phy_link_status = resp->link; 6401 link_info->duplex = resp->duplex_cfg; 6402 if (bp->hwrm_spec_code >= 0x10800) 6403 link_info->duplex = resp->duplex_state; 6404 link_info->pause = resp->pause; 6405 link_info->auto_mode = resp->auto_mode; 6406 link_info->auto_pause_setting = resp->auto_pause; 6407 link_info->lp_pause = resp->link_partner_adv_pause; 6408 link_info->force_pause_setting = resp->force_pause; 6409 link_info->duplex_setting = resp->duplex_cfg; 6410 if (link_info->phy_link_status == BNXT_LINK_LINK) 6411 link_info->link_speed = le16_to_cpu(resp->link_speed); 6412 else 6413 link_info->link_speed = 0; 6414 link_info->force_link_speed = le16_to_cpu(resp->force_link_speed); 6415 link_info->support_speeds = le16_to_cpu(resp->support_speeds); 6416 link_info->auto_link_speeds = le16_to_cpu(resp->auto_link_speed_mask); 6417 link_info->lp_auto_link_speeds = 6418 le16_to_cpu(resp->link_partner_adv_speeds); 6419 link_info->preemphasis = le32_to_cpu(resp->preemphasis); 6420 link_info->phy_ver[0] = resp->phy_maj; 6421 link_info->phy_ver[1] = resp->phy_min; 6422 link_info->phy_ver[2] = resp->phy_bld; 6423 link_info->media_type = resp->media_type; 6424 link_info->phy_type = resp->phy_type; 6425 link_info->transceiver = resp->xcvr_pkg_type; 6426 link_info->phy_addr = resp->eee_config_phy_addr & 6427 PORT_PHY_QCFG_RESP_PHY_ADDR_MASK; 6428 link_info->module_status = resp->module_status; 6429 6430 if (bp->flags & BNXT_FLAG_EEE_CAP) { 6431 struct ethtool_eee *eee = &bp->eee; 6432 u16 fw_speeds; 6433 6434 eee->eee_active = 0; 6435 if (resp->eee_config_phy_addr & 6436 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE) { 6437 eee->eee_active = 1; 6438 fw_speeds = le16_to_cpu( 6439 resp->link_partner_adv_eee_link_speed_mask); 6440 eee->lp_advertised = 6441 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0); 6442 } 6443 6444 /* Pull initial EEE config */ 6445 if (!chng_link_state) { 6446 if (resp->eee_config_phy_addr & 6447 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED) 6448 eee->eee_enabled = 1; 6449 6450 fw_speeds = le16_to_cpu(resp->adv_eee_link_speed_mask); 6451 eee->advertised = 6452 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0); 6453 6454 if (resp->eee_config_phy_addr & 6455 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI) { 6456 __le32 tmr; 6457 6458 eee->tx_lpi_enabled = 1; 6459 tmr = resp->xcvr_identifier_type_tx_lpi_timer; 6460 eee->tx_lpi_timer = le32_to_cpu(tmr) & 6461 PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK; 6462 } 6463 } 6464 } 6465 6466 link_info->fec_cfg = PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED; 6467 if (bp->hwrm_spec_code >= 0x10504) 6468 link_info->fec_cfg = le16_to_cpu(resp->fec_cfg); 6469 6470 /* TODO: need to add more logic to report VF link */ 6471 if (chng_link_state) { 6472 if (link_info->phy_link_status == BNXT_LINK_LINK) 6473 link_info->link_up = 1; 6474 else 6475 link_info->link_up = 0; 6476 if (link_up != link_info->link_up) 6477 bnxt_report_link(bp); 6478 } else { 6479 /* alwasy link down if not require to update link state */ 6480 link_info->link_up = 0; 6481 } 6482 mutex_unlock(&bp->hwrm_cmd_lock); 6483 6484 if (!BNXT_SINGLE_PF(bp)) 6485 return 0; 6486 6487 diff = link_info->support_auto_speeds ^ link_info->advertising; 6488 if ((link_info->support_auto_speeds | diff) != 6489 link_info->support_auto_speeds) { 6490 /* An advertised speed is no longer supported, so we need to 6491 * update the advertisement settings. Caller holds RTNL 6492 * so we can modify link settings. 6493 */ 6494 link_info->advertising = link_info->support_auto_speeds; 6495 if (link_info->autoneg & BNXT_AUTONEG_SPEED) 6496 bnxt_hwrm_set_link_setting(bp, true, false); 6497 } 6498 return 0; 6499 } 6500 6501 static void bnxt_get_port_module_status(struct bnxt *bp) 6502 { 6503 struct bnxt_link_info *link_info = &bp->link_info; 6504 struct hwrm_port_phy_qcfg_output *resp = &link_info->phy_qcfg_resp; 6505 u8 module_status; 6506 6507 if (bnxt_update_link(bp, true)) 6508 return; 6509 6510 module_status = link_info->module_status; 6511 switch (module_status) { 6512 case PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX: 6513 case PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN: 6514 case PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG: 6515 netdev_warn(bp->dev, "Unqualified SFP+ module detected on port %d\n", 6516 bp->pf.port_id); 6517 if (bp->hwrm_spec_code >= 0x10201) { 6518 netdev_warn(bp->dev, "Module part number %s\n", 6519 resp->phy_vendor_partnumber); 6520 } 6521 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX) 6522 netdev_warn(bp->dev, "TX is disabled\n"); 6523 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN) 6524 netdev_warn(bp->dev, "SFP+ module is shutdown\n"); 6525 } 6526 } 6527 6528 static void 6529 bnxt_hwrm_set_pause_common(struct bnxt *bp, struct hwrm_port_phy_cfg_input *req) 6530 { 6531 if (bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) { 6532 if (bp->hwrm_spec_code >= 0x10201) 6533 req->auto_pause = 6534 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE; 6535 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX) 6536 req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX; 6537 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX) 6538 req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_TX; 6539 req->enables |= 6540 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE); 6541 } else { 6542 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX) 6543 req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_RX; 6544 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX) 6545 req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_TX; 6546 req->enables |= 6547 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE); 6548 if (bp->hwrm_spec_code >= 0x10201) { 6549 req->auto_pause = req->force_pause; 6550 req->enables |= cpu_to_le32( 6551 PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE); 6552 } 6553 } 6554 } 6555 6556 static void bnxt_hwrm_set_link_common(struct bnxt *bp, 6557 struct hwrm_port_phy_cfg_input *req) 6558 { 6559 u8 autoneg = bp->link_info.autoneg; 6560 u16 fw_link_speed = bp->link_info.req_link_speed; 6561 u16 advertising = bp->link_info.advertising; 6562 6563 if (autoneg & BNXT_AUTONEG_SPEED) { 6564 req->auto_mode |= 6565 PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK; 6566 6567 req->enables |= cpu_to_le32( 6568 PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK); 6569 req->auto_link_speed_mask = cpu_to_le16(advertising); 6570 6571 req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE); 6572 req->flags |= 6573 cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG); 6574 } else { 6575 req->force_link_speed = cpu_to_le16(fw_link_speed); 6576 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE); 6577 } 6578 6579 /* tell chimp that the setting takes effect immediately */ 6580 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESET_PHY); 6581 } 6582 6583 int bnxt_hwrm_set_pause(struct bnxt *bp) 6584 { 6585 struct hwrm_port_phy_cfg_input req = {0}; 6586 int rc; 6587 6588 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1); 6589 bnxt_hwrm_set_pause_common(bp, &req); 6590 6591 if ((bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) || 6592 bp->link_info.force_link_chng) 6593 bnxt_hwrm_set_link_common(bp, &req); 6594 6595 mutex_lock(&bp->hwrm_cmd_lock); 6596 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 6597 if (!rc && !(bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL)) { 6598 /* since changing of pause setting doesn't trigger any link 6599 * change event, the driver needs to update the current pause 6600 * result upon successfully return of the phy_cfg command 6601 */ 6602 bp->link_info.pause = 6603 bp->link_info.force_pause_setting = bp->link_info.req_flow_ctrl; 6604 bp->link_info.auto_pause_setting = 0; 6605 if (!bp->link_info.force_link_chng) 6606 bnxt_report_link(bp); 6607 } 6608 bp->link_info.force_link_chng = false; 6609 mutex_unlock(&bp->hwrm_cmd_lock); 6610 return rc; 6611 } 6612 6613 static void bnxt_hwrm_set_eee(struct bnxt *bp, 6614 struct hwrm_port_phy_cfg_input *req) 6615 { 6616 struct ethtool_eee *eee = &bp->eee; 6617 6618 if (eee->eee_enabled) { 6619 u16 eee_speeds; 6620 u32 flags = PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE; 6621 6622 if (eee->tx_lpi_enabled) 6623 flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE; 6624 else 6625 flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE; 6626 6627 req->flags |= cpu_to_le32(flags); 6628 eee_speeds = bnxt_get_fw_auto_link_speeds(eee->advertised); 6629 req->eee_link_speed_mask = cpu_to_le16(eee_speeds); 6630 req->tx_lpi_timer = cpu_to_le32(eee->tx_lpi_timer); 6631 } else { 6632 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE); 6633 } 6634 } 6635 6636 int bnxt_hwrm_set_link_setting(struct bnxt *bp, bool set_pause, bool set_eee) 6637 { 6638 struct hwrm_port_phy_cfg_input req = {0}; 6639 6640 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1); 6641 if (set_pause) 6642 bnxt_hwrm_set_pause_common(bp, &req); 6643 6644 bnxt_hwrm_set_link_common(bp, &req); 6645 6646 if (set_eee) 6647 bnxt_hwrm_set_eee(bp, &req); 6648 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 6649 } 6650 6651 static int bnxt_hwrm_shutdown_link(struct bnxt *bp) 6652 { 6653 struct hwrm_port_phy_cfg_input req = {0}; 6654 6655 if (!BNXT_SINGLE_PF(bp)) 6656 return 0; 6657 6658 if (pci_num_vf(bp->pdev)) 6659 return 0; 6660 6661 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1); 6662 req.flags = cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN); 6663 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 6664 } 6665 6666 static int bnxt_hwrm_if_change(struct bnxt *bp, bool up) 6667 { 6668 struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr; 6669 struct hwrm_func_drv_if_change_input req = {0}; 6670 bool resc_reinit = false; 6671 int rc; 6672 6673 if (!(bp->fw_cap & BNXT_FW_CAP_IF_CHANGE)) 6674 return 0; 6675 6676 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_IF_CHANGE, -1, -1); 6677 if (up) 6678 req.flags = cpu_to_le32(FUNC_DRV_IF_CHANGE_REQ_FLAGS_UP); 6679 mutex_lock(&bp->hwrm_cmd_lock); 6680 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 6681 if (!rc && (resp->flags & 6682 cpu_to_le32(FUNC_DRV_IF_CHANGE_RESP_FLAGS_RESC_CHANGE))) 6683 resc_reinit = true; 6684 mutex_unlock(&bp->hwrm_cmd_lock); 6685 6686 if (up && resc_reinit && BNXT_NEW_RM(bp)) { 6687 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 6688 6689 rc = bnxt_hwrm_func_resc_qcaps(bp, true); 6690 hw_resc->resv_cp_rings = 0; 6691 hw_resc->resv_tx_rings = 0; 6692 hw_resc->resv_rx_rings = 0; 6693 hw_resc->resv_hw_ring_grps = 0; 6694 hw_resc->resv_vnics = 0; 6695 bp->tx_nr_rings = 0; 6696 bp->rx_nr_rings = 0; 6697 } 6698 return rc; 6699 } 6700 6701 static int bnxt_hwrm_port_led_qcaps(struct bnxt *bp) 6702 { 6703 struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr; 6704 struct hwrm_port_led_qcaps_input req = {0}; 6705 struct bnxt_pf_info *pf = &bp->pf; 6706 int rc; 6707 6708 if (BNXT_VF(bp) || bp->hwrm_spec_code < 0x10601) 6709 return 0; 6710 6711 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_LED_QCAPS, -1, -1); 6712 req.port_id = cpu_to_le16(pf->port_id); 6713 mutex_lock(&bp->hwrm_cmd_lock); 6714 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 6715 if (rc) { 6716 mutex_unlock(&bp->hwrm_cmd_lock); 6717 return rc; 6718 } 6719 if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) { 6720 int i; 6721 6722 bp->num_leds = resp->num_leds; 6723 memcpy(bp->leds, &resp->led0_id, sizeof(bp->leds[0]) * 6724 bp->num_leds); 6725 for (i = 0; i < bp->num_leds; i++) { 6726 struct bnxt_led_info *led = &bp->leds[i]; 6727 __le16 caps = led->led_state_caps; 6728 6729 if (!led->led_group_id || 6730 !BNXT_LED_ALT_BLINK_CAP(caps)) { 6731 bp->num_leds = 0; 6732 break; 6733 } 6734 } 6735 } 6736 mutex_unlock(&bp->hwrm_cmd_lock); 6737 return 0; 6738 } 6739 6740 int bnxt_hwrm_alloc_wol_fltr(struct bnxt *bp) 6741 { 6742 struct hwrm_wol_filter_alloc_input req = {0}; 6743 struct hwrm_wol_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr; 6744 int rc; 6745 6746 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_ALLOC, -1, -1); 6747 req.port_id = cpu_to_le16(bp->pf.port_id); 6748 req.wol_type = WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT; 6749 req.enables = cpu_to_le32(WOL_FILTER_ALLOC_REQ_ENABLES_MAC_ADDRESS); 6750 memcpy(req.mac_address, bp->dev->dev_addr, ETH_ALEN); 6751 mutex_lock(&bp->hwrm_cmd_lock); 6752 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 6753 if (!rc) 6754 bp->wol_filter_id = resp->wol_filter_id; 6755 mutex_unlock(&bp->hwrm_cmd_lock); 6756 return rc; 6757 } 6758 6759 int bnxt_hwrm_free_wol_fltr(struct bnxt *bp) 6760 { 6761 struct hwrm_wol_filter_free_input req = {0}; 6762 int rc; 6763 6764 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_FREE, -1, -1); 6765 req.port_id = cpu_to_le16(bp->pf.port_id); 6766 req.enables = cpu_to_le32(WOL_FILTER_FREE_REQ_ENABLES_WOL_FILTER_ID); 6767 req.wol_filter_id = bp->wol_filter_id; 6768 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 6769 return rc; 6770 } 6771 6772 static u16 bnxt_hwrm_get_wol_fltrs(struct bnxt *bp, u16 handle) 6773 { 6774 struct hwrm_wol_filter_qcfg_input req = {0}; 6775 struct hwrm_wol_filter_qcfg_output *resp = bp->hwrm_cmd_resp_addr; 6776 u16 next_handle = 0; 6777 int rc; 6778 6779 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_QCFG, -1, -1); 6780 req.port_id = cpu_to_le16(bp->pf.port_id); 6781 req.handle = cpu_to_le16(handle); 6782 mutex_lock(&bp->hwrm_cmd_lock); 6783 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 6784 if (!rc) { 6785 next_handle = le16_to_cpu(resp->next_handle); 6786 if (next_handle != 0) { 6787 if (resp->wol_type == 6788 WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT) { 6789 bp->wol = 1; 6790 bp->wol_filter_id = resp->wol_filter_id; 6791 } 6792 } 6793 } 6794 mutex_unlock(&bp->hwrm_cmd_lock); 6795 return next_handle; 6796 } 6797 6798 static void bnxt_get_wol_settings(struct bnxt *bp) 6799 { 6800 u16 handle = 0; 6801 6802 if (!BNXT_PF(bp) || !(bp->flags & BNXT_FLAG_WOL_CAP)) 6803 return; 6804 6805 do { 6806 handle = bnxt_hwrm_get_wol_fltrs(bp, handle); 6807 } while (handle && handle != 0xffff); 6808 } 6809 6810 #ifdef CONFIG_BNXT_HWMON 6811 static ssize_t bnxt_show_temp(struct device *dev, 6812 struct device_attribute *devattr, char *buf) 6813 { 6814 struct hwrm_temp_monitor_query_input req = {0}; 6815 struct hwrm_temp_monitor_query_output *resp; 6816 struct bnxt *bp = dev_get_drvdata(dev); 6817 u32 temp = 0; 6818 6819 resp = bp->hwrm_cmd_resp_addr; 6820 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TEMP_MONITOR_QUERY, -1, -1); 6821 mutex_lock(&bp->hwrm_cmd_lock); 6822 if (!_hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT)) 6823 temp = resp->temp * 1000; /* display millidegree */ 6824 mutex_unlock(&bp->hwrm_cmd_lock); 6825 6826 return sprintf(buf, "%u\n", temp); 6827 } 6828 static SENSOR_DEVICE_ATTR(temp1_input, 0444, bnxt_show_temp, NULL, 0); 6829 6830 static struct attribute *bnxt_attrs[] = { 6831 &sensor_dev_attr_temp1_input.dev_attr.attr, 6832 NULL 6833 }; 6834 ATTRIBUTE_GROUPS(bnxt); 6835 6836 static void bnxt_hwmon_close(struct bnxt *bp) 6837 { 6838 if (bp->hwmon_dev) { 6839 hwmon_device_unregister(bp->hwmon_dev); 6840 bp->hwmon_dev = NULL; 6841 } 6842 } 6843 6844 static void bnxt_hwmon_open(struct bnxt *bp) 6845 { 6846 struct pci_dev *pdev = bp->pdev; 6847 6848 bp->hwmon_dev = hwmon_device_register_with_groups(&pdev->dev, 6849 DRV_MODULE_NAME, bp, 6850 bnxt_groups); 6851 if (IS_ERR(bp->hwmon_dev)) { 6852 bp->hwmon_dev = NULL; 6853 dev_warn(&pdev->dev, "Cannot register hwmon device\n"); 6854 } 6855 } 6856 #else 6857 static void bnxt_hwmon_close(struct bnxt *bp) 6858 { 6859 } 6860 6861 static void bnxt_hwmon_open(struct bnxt *bp) 6862 { 6863 } 6864 #endif 6865 6866 static bool bnxt_eee_config_ok(struct bnxt *bp) 6867 { 6868 struct ethtool_eee *eee = &bp->eee; 6869 struct bnxt_link_info *link_info = &bp->link_info; 6870 6871 if (!(bp->flags & BNXT_FLAG_EEE_CAP)) 6872 return true; 6873 6874 if (eee->eee_enabled) { 6875 u32 advertising = 6876 _bnxt_fw_to_ethtool_adv_spds(link_info->advertising, 0); 6877 6878 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) { 6879 eee->eee_enabled = 0; 6880 return false; 6881 } 6882 if (eee->advertised & ~advertising) { 6883 eee->advertised = advertising & eee->supported; 6884 return false; 6885 } 6886 } 6887 return true; 6888 } 6889 6890 static int bnxt_update_phy_setting(struct bnxt *bp) 6891 { 6892 int rc; 6893 bool update_link = false; 6894 bool update_pause = false; 6895 bool update_eee = false; 6896 struct bnxt_link_info *link_info = &bp->link_info; 6897 6898 rc = bnxt_update_link(bp, true); 6899 if (rc) { 6900 netdev_err(bp->dev, "failed to update link (rc: %x)\n", 6901 rc); 6902 return rc; 6903 } 6904 if (!BNXT_SINGLE_PF(bp)) 6905 return 0; 6906 6907 if ((link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) && 6908 (link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH) != 6909 link_info->req_flow_ctrl) 6910 update_pause = true; 6911 if (!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) && 6912 link_info->force_pause_setting != link_info->req_flow_ctrl) 6913 update_pause = true; 6914 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) { 6915 if (BNXT_AUTO_MODE(link_info->auto_mode)) 6916 update_link = true; 6917 if (link_info->req_link_speed != link_info->force_link_speed) 6918 update_link = true; 6919 if (link_info->req_duplex != link_info->duplex_setting) 6920 update_link = true; 6921 } else { 6922 if (link_info->auto_mode == BNXT_LINK_AUTO_NONE) 6923 update_link = true; 6924 if (link_info->advertising != link_info->auto_link_speeds) 6925 update_link = true; 6926 } 6927 6928 /* The last close may have shutdown the link, so need to call 6929 * PHY_CFG to bring it back up. 6930 */ 6931 if (!netif_carrier_ok(bp->dev)) 6932 update_link = true; 6933 6934 if (!bnxt_eee_config_ok(bp)) 6935 update_eee = true; 6936 6937 if (update_link) 6938 rc = bnxt_hwrm_set_link_setting(bp, update_pause, update_eee); 6939 else if (update_pause) 6940 rc = bnxt_hwrm_set_pause(bp); 6941 if (rc) { 6942 netdev_err(bp->dev, "failed to update phy setting (rc: %x)\n", 6943 rc); 6944 return rc; 6945 } 6946 6947 return rc; 6948 } 6949 6950 /* Common routine to pre-map certain register block to different GRC window. 6951 * A PF has 16 4K windows and a VF has 4 4K windows. However, only 15 windows 6952 * in PF and 3 windows in VF that can be customized to map in different 6953 * register blocks. 6954 */ 6955 static void bnxt_preset_reg_win(struct bnxt *bp) 6956 { 6957 if (BNXT_PF(bp)) { 6958 /* CAG registers map to GRC window #4 */ 6959 writel(BNXT_CAG_REG_BASE, 6960 bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 12); 6961 } 6962 } 6963 6964 static int bnxt_init_dflt_ring_mode(struct bnxt *bp); 6965 6966 static int __bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init) 6967 { 6968 int rc = 0; 6969 6970 bnxt_preset_reg_win(bp); 6971 netif_carrier_off(bp->dev); 6972 if (irq_re_init) { 6973 /* Reserve rings now if none were reserved at driver probe. */ 6974 rc = bnxt_init_dflt_ring_mode(bp); 6975 if (rc) { 6976 netdev_err(bp->dev, "Failed to reserve default rings at open\n"); 6977 return rc; 6978 } 6979 rc = bnxt_reserve_rings(bp); 6980 if (rc) 6981 return rc; 6982 } 6983 if ((bp->flags & BNXT_FLAG_RFS) && 6984 !(bp->flags & BNXT_FLAG_USING_MSIX)) { 6985 /* disable RFS if falling back to INTA */ 6986 bp->dev->hw_features &= ~NETIF_F_NTUPLE; 6987 bp->flags &= ~BNXT_FLAG_RFS; 6988 } 6989 6990 rc = bnxt_alloc_mem(bp, irq_re_init); 6991 if (rc) { 6992 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc); 6993 goto open_err_free_mem; 6994 } 6995 6996 if (irq_re_init) { 6997 bnxt_init_napi(bp); 6998 rc = bnxt_request_irq(bp); 6999 if (rc) { 7000 netdev_err(bp->dev, "bnxt_request_irq err: %x\n", rc); 7001 goto open_err_irq; 7002 } 7003 } 7004 7005 bnxt_enable_napi(bp); 7006 bnxt_debug_dev_init(bp); 7007 7008 rc = bnxt_init_nic(bp, irq_re_init); 7009 if (rc) { 7010 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc); 7011 goto open_err; 7012 } 7013 7014 if (link_re_init) { 7015 mutex_lock(&bp->link_lock); 7016 rc = bnxt_update_phy_setting(bp); 7017 mutex_unlock(&bp->link_lock); 7018 if (rc) { 7019 netdev_warn(bp->dev, "failed to update phy settings\n"); 7020 if (BNXT_SINGLE_PF(bp)) { 7021 bp->link_info.phy_retry = true; 7022 bp->link_info.phy_retry_expires = 7023 jiffies + 5 * HZ; 7024 } 7025 } 7026 } 7027 7028 if (irq_re_init) 7029 udp_tunnel_get_rx_info(bp->dev); 7030 7031 set_bit(BNXT_STATE_OPEN, &bp->state); 7032 bnxt_enable_int(bp); 7033 /* Enable TX queues */ 7034 bnxt_tx_enable(bp); 7035 mod_timer(&bp->timer, jiffies + bp->current_interval); 7036 /* Poll link status and check for SFP+ module status */ 7037 bnxt_get_port_module_status(bp); 7038 7039 /* VF-reps may need to be re-opened after the PF is re-opened */ 7040 if (BNXT_PF(bp)) 7041 bnxt_vf_reps_open(bp); 7042 return 0; 7043 7044 open_err: 7045 bnxt_debug_dev_exit(bp); 7046 bnxt_disable_napi(bp); 7047 7048 open_err_irq: 7049 bnxt_del_napi(bp); 7050 7051 open_err_free_mem: 7052 bnxt_free_skbs(bp); 7053 bnxt_free_irq(bp); 7054 bnxt_free_mem(bp, true); 7055 return rc; 7056 } 7057 7058 /* rtnl_lock held */ 7059 int bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init) 7060 { 7061 int rc = 0; 7062 7063 rc = __bnxt_open_nic(bp, irq_re_init, link_re_init); 7064 if (rc) { 7065 netdev_err(bp->dev, "nic open fail (rc: %x)\n", rc); 7066 dev_close(bp->dev); 7067 } 7068 return rc; 7069 } 7070 7071 /* rtnl_lock held, open the NIC half way by allocating all resources, but 7072 * NAPI, IRQ, and TX are not enabled. This is mainly used for offline 7073 * self tests. 7074 */ 7075 int bnxt_half_open_nic(struct bnxt *bp) 7076 { 7077 int rc = 0; 7078 7079 rc = bnxt_alloc_mem(bp, false); 7080 if (rc) { 7081 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc); 7082 goto half_open_err; 7083 } 7084 rc = bnxt_init_nic(bp, false); 7085 if (rc) { 7086 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc); 7087 goto half_open_err; 7088 } 7089 return 0; 7090 7091 half_open_err: 7092 bnxt_free_skbs(bp); 7093 bnxt_free_mem(bp, false); 7094 dev_close(bp->dev); 7095 return rc; 7096 } 7097 7098 /* rtnl_lock held, this call can only be made after a previous successful 7099 * call to bnxt_half_open_nic(). 7100 */ 7101 void bnxt_half_close_nic(struct bnxt *bp) 7102 { 7103 bnxt_hwrm_resource_free(bp, false, false); 7104 bnxt_free_skbs(bp); 7105 bnxt_free_mem(bp, false); 7106 } 7107 7108 static int bnxt_open(struct net_device *dev) 7109 { 7110 struct bnxt *bp = netdev_priv(dev); 7111 int rc; 7112 7113 bnxt_hwrm_if_change(bp, true); 7114 rc = __bnxt_open_nic(bp, true, true); 7115 if (rc) 7116 bnxt_hwrm_if_change(bp, false); 7117 7118 bnxt_hwmon_open(bp); 7119 7120 return rc; 7121 } 7122 7123 static bool bnxt_drv_busy(struct bnxt *bp) 7124 { 7125 return (test_bit(BNXT_STATE_IN_SP_TASK, &bp->state) || 7126 test_bit(BNXT_STATE_READ_STATS, &bp->state)); 7127 } 7128 7129 static void __bnxt_close_nic(struct bnxt *bp, bool irq_re_init, 7130 bool link_re_init) 7131 { 7132 /* Close the VF-reps before closing PF */ 7133 if (BNXT_PF(bp)) 7134 bnxt_vf_reps_close(bp); 7135 7136 /* Change device state to avoid TX queue wake up's */ 7137 bnxt_tx_disable(bp); 7138 7139 clear_bit(BNXT_STATE_OPEN, &bp->state); 7140 smp_mb__after_atomic(); 7141 while (bnxt_drv_busy(bp)) 7142 msleep(20); 7143 7144 /* Flush rings and and disable interrupts */ 7145 bnxt_shutdown_nic(bp, irq_re_init); 7146 7147 /* TODO CHIMP_FW: Link/PHY related cleanup if (link_re_init) */ 7148 7149 bnxt_debug_dev_exit(bp); 7150 bnxt_disable_napi(bp); 7151 del_timer_sync(&bp->timer); 7152 bnxt_free_skbs(bp); 7153 7154 if (irq_re_init) { 7155 bnxt_free_irq(bp); 7156 bnxt_del_napi(bp); 7157 } 7158 bnxt_free_mem(bp, irq_re_init); 7159 } 7160 7161 int bnxt_close_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init) 7162 { 7163 int rc = 0; 7164 7165 #ifdef CONFIG_BNXT_SRIOV 7166 if (bp->sriov_cfg) { 7167 rc = wait_event_interruptible_timeout(bp->sriov_cfg_wait, 7168 !bp->sriov_cfg, 7169 BNXT_SRIOV_CFG_WAIT_TMO); 7170 if (rc) 7171 netdev_warn(bp->dev, "timeout waiting for SRIOV config operation to complete!\n"); 7172 } 7173 #endif 7174 __bnxt_close_nic(bp, irq_re_init, link_re_init); 7175 return rc; 7176 } 7177 7178 static int bnxt_close(struct net_device *dev) 7179 { 7180 struct bnxt *bp = netdev_priv(dev); 7181 7182 bnxt_hwmon_close(bp); 7183 bnxt_close_nic(bp, true, true); 7184 bnxt_hwrm_shutdown_link(bp); 7185 bnxt_hwrm_if_change(bp, false); 7186 return 0; 7187 } 7188 7189 /* rtnl_lock held */ 7190 static int bnxt_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 7191 { 7192 switch (cmd) { 7193 case SIOCGMIIPHY: 7194 /* fallthru */ 7195 case SIOCGMIIREG: { 7196 if (!netif_running(dev)) 7197 return -EAGAIN; 7198 7199 return 0; 7200 } 7201 7202 case SIOCSMIIREG: 7203 if (!netif_running(dev)) 7204 return -EAGAIN; 7205 7206 return 0; 7207 7208 default: 7209 /* do nothing */ 7210 break; 7211 } 7212 return -EOPNOTSUPP; 7213 } 7214 7215 static void 7216 bnxt_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) 7217 { 7218 u32 i; 7219 struct bnxt *bp = netdev_priv(dev); 7220 7221 set_bit(BNXT_STATE_READ_STATS, &bp->state); 7222 /* Make sure bnxt_close_nic() sees that we are reading stats before 7223 * we check the BNXT_STATE_OPEN flag. 7224 */ 7225 smp_mb__after_atomic(); 7226 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) { 7227 clear_bit(BNXT_STATE_READ_STATS, &bp->state); 7228 return; 7229 } 7230 7231 /* TODO check if we need to synchronize with bnxt_close path */ 7232 for (i = 0; i < bp->cp_nr_rings; i++) { 7233 struct bnxt_napi *bnapi = bp->bnapi[i]; 7234 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 7235 struct ctx_hw_stats *hw_stats = cpr->hw_stats; 7236 7237 stats->rx_packets += le64_to_cpu(hw_stats->rx_ucast_pkts); 7238 stats->rx_packets += le64_to_cpu(hw_stats->rx_mcast_pkts); 7239 stats->rx_packets += le64_to_cpu(hw_stats->rx_bcast_pkts); 7240 7241 stats->tx_packets += le64_to_cpu(hw_stats->tx_ucast_pkts); 7242 stats->tx_packets += le64_to_cpu(hw_stats->tx_mcast_pkts); 7243 stats->tx_packets += le64_to_cpu(hw_stats->tx_bcast_pkts); 7244 7245 stats->rx_bytes += le64_to_cpu(hw_stats->rx_ucast_bytes); 7246 stats->rx_bytes += le64_to_cpu(hw_stats->rx_mcast_bytes); 7247 stats->rx_bytes += le64_to_cpu(hw_stats->rx_bcast_bytes); 7248 7249 stats->tx_bytes += le64_to_cpu(hw_stats->tx_ucast_bytes); 7250 stats->tx_bytes += le64_to_cpu(hw_stats->tx_mcast_bytes); 7251 stats->tx_bytes += le64_to_cpu(hw_stats->tx_bcast_bytes); 7252 7253 stats->rx_missed_errors += 7254 le64_to_cpu(hw_stats->rx_discard_pkts); 7255 7256 stats->multicast += le64_to_cpu(hw_stats->rx_mcast_pkts); 7257 7258 stats->tx_dropped += le64_to_cpu(hw_stats->tx_drop_pkts); 7259 } 7260 7261 if (bp->flags & BNXT_FLAG_PORT_STATS) { 7262 struct rx_port_stats *rx = bp->hw_rx_port_stats; 7263 struct tx_port_stats *tx = bp->hw_tx_port_stats; 7264 7265 stats->rx_crc_errors = le64_to_cpu(rx->rx_fcs_err_frames); 7266 stats->rx_frame_errors = le64_to_cpu(rx->rx_align_err_frames); 7267 stats->rx_length_errors = le64_to_cpu(rx->rx_undrsz_frames) + 7268 le64_to_cpu(rx->rx_ovrsz_frames) + 7269 le64_to_cpu(rx->rx_runt_frames); 7270 stats->rx_errors = le64_to_cpu(rx->rx_false_carrier_frames) + 7271 le64_to_cpu(rx->rx_jbr_frames); 7272 stats->collisions = le64_to_cpu(tx->tx_total_collisions); 7273 stats->tx_fifo_errors = le64_to_cpu(tx->tx_fifo_underruns); 7274 stats->tx_errors = le64_to_cpu(tx->tx_err); 7275 } 7276 clear_bit(BNXT_STATE_READ_STATS, &bp->state); 7277 } 7278 7279 static bool bnxt_mc_list_updated(struct bnxt *bp, u32 *rx_mask) 7280 { 7281 struct net_device *dev = bp->dev; 7282 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 7283 struct netdev_hw_addr *ha; 7284 u8 *haddr; 7285 int mc_count = 0; 7286 bool update = false; 7287 int off = 0; 7288 7289 netdev_for_each_mc_addr(ha, dev) { 7290 if (mc_count >= BNXT_MAX_MC_ADDRS) { 7291 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST; 7292 vnic->mc_list_count = 0; 7293 return false; 7294 } 7295 haddr = ha->addr; 7296 if (!ether_addr_equal(haddr, vnic->mc_list + off)) { 7297 memcpy(vnic->mc_list + off, haddr, ETH_ALEN); 7298 update = true; 7299 } 7300 off += ETH_ALEN; 7301 mc_count++; 7302 } 7303 if (mc_count) 7304 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_MCAST; 7305 7306 if (mc_count != vnic->mc_list_count) { 7307 vnic->mc_list_count = mc_count; 7308 update = true; 7309 } 7310 return update; 7311 } 7312 7313 static bool bnxt_uc_list_updated(struct bnxt *bp) 7314 { 7315 struct net_device *dev = bp->dev; 7316 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 7317 struct netdev_hw_addr *ha; 7318 int off = 0; 7319 7320 if (netdev_uc_count(dev) != (vnic->uc_filter_count - 1)) 7321 return true; 7322 7323 netdev_for_each_uc_addr(ha, dev) { 7324 if (!ether_addr_equal(ha->addr, vnic->uc_list + off)) 7325 return true; 7326 7327 off += ETH_ALEN; 7328 } 7329 return false; 7330 } 7331 7332 static void bnxt_set_rx_mode(struct net_device *dev) 7333 { 7334 struct bnxt *bp = netdev_priv(dev); 7335 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 7336 u32 mask = vnic->rx_mask; 7337 bool mc_update = false; 7338 bool uc_update; 7339 7340 if (!netif_running(dev)) 7341 return; 7342 7343 mask &= ~(CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS | 7344 CFA_L2_SET_RX_MASK_REQ_MASK_MCAST | 7345 CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST | 7346 CFA_L2_SET_RX_MASK_REQ_MASK_BCAST); 7347 7348 if ((dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp)) 7349 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS; 7350 7351 uc_update = bnxt_uc_list_updated(bp); 7352 7353 if (dev->flags & IFF_BROADCAST) 7354 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_BCAST; 7355 if (dev->flags & IFF_ALLMULTI) { 7356 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST; 7357 vnic->mc_list_count = 0; 7358 } else { 7359 mc_update = bnxt_mc_list_updated(bp, &mask); 7360 } 7361 7362 if (mask != vnic->rx_mask || uc_update || mc_update) { 7363 vnic->rx_mask = mask; 7364 7365 set_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event); 7366 bnxt_queue_sp_work(bp); 7367 } 7368 } 7369 7370 static int bnxt_cfg_rx_mode(struct bnxt *bp) 7371 { 7372 struct net_device *dev = bp->dev; 7373 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 7374 struct netdev_hw_addr *ha; 7375 int i, off = 0, rc; 7376 bool uc_update; 7377 7378 netif_addr_lock_bh(dev); 7379 uc_update = bnxt_uc_list_updated(bp); 7380 netif_addr_unlock_bh(dev); 7381 7382 if (!uc_update) 7383 goto skip_uc; 7384 7385 mutex_lock(&bp->hwrm_cmd_lock); 7386 for (i = 1; i < vnic->uc_filter_count; i++) { 7387 struct hwrm_cfa_l2_filter_free_input req = {0}; 7388 7389 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_FREE, -1, 7390 -1); 7391 7392 req.l2_filter_id = vnic->fw_l2_filter_id[i]; 7393 7394 rc = _hwrm_send_message(bp, &req, sizeof(req), 7395 HWRM_CMD_TIMEOUT); 7396 } 7397 mutex_unlock(&bp->hwrm_cmd_lock); 7398 7399 vnic->uc_filter_count = 1; 7400 7401 netif_addr_lock_bh(dev); 7402 if (netdev_uc_count(dev) > (BNXT_MAX_UC_ADDRS - 1)) { 7403 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS; 7404 } else { 7405 netdev_for_each_uc_addr(ha, dev) { 7406 memcpy(vnic->uc_list + off, ha->addr, ETH_ALEN); 7407 off += ETH_ALEN; 7408 vnic->uc_filter_count++; 7409 } 7410 } 7411 netif_addr_unlock_bh(dev); 7412 7413 for (i = 1, off = 0; i < vnic->uc_filter_count; i++, off += ETH_ALEN) { 7414 rc = bnxt_hwrm_set_vnic_filter(bp, 0, i, vnic->uc_list + off); 7415 if (rc) { 7416 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n", 7417 rc); 7418 vnic->uc_filter_count = i; 7419 return rc; 7420 } 7421 } 7422 7423 skip_uc: 7424 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0); 7425 if (rc) 7426 netdev_err(bp->dev, "HWRM cfa l2 rx mask failure rc: %x\n", 7427 rc); 7428 7429 return rc; 7430 } 7431 7432 static bool bnxt_can_reserve_rings(struct bnxt *bp) 7433 { 7434 #ifdef CONFIG_BNXT_SRIOV 7435 if (BNXT_NEW_RM(bp) && BNXT_VF(bp)) { 7436 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 7437 7438 /* No minimum rings were provisioned by the PF. Don't 7439 * reserve rings by default when device is down. 7440 */ 7441 if (hw_resc->min_tx_rings || hw_resc->resv_tx_rings) 7442 return true; 7443 7444 if (!netif_running(bp->dev)) 7445 return false; 7446 } 7447 #endif 7448 return true; 7449 } 7450 7451 /* If the chip and firmware supports RFS */ 7452 static bool bnxt_rfs_supported(struct bnxt *bp) 7453 { 7454 if (BNXT_PF(bp) && !BNXT_CHIP_TYPE_NITRO_A0(bp)) 7455 return true; 7456 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP) 7457 return true; 7458 return false; 7459 } 7460 7461 /* If runtime conditions support RFS */ 7462 static bool bnxt_rfs_capable(struct bnxt *bp) 7463 { 7464 #ifdef CONFIG_RFS_ACCEL 7465 int vnics, max_vnics, max_rss_ctxs; 7466 7467 if (!(bp->flags & BNXT_FLAG_MSIX_CAP) || !bnxt_can_reserve_rings(bp)) 7468 return false; 7469 7470 vnics = 1 + bp->rx_nr_rings; 7471 max_vnics = bnxt_get_max_func_vnics(bp); 7472 max_rss_ctxs = bnxt_get_max_func_rss_ctxs(bp); 7473 7474 /* RSS contexts not a limiting factor */ 7475 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP) 7476 max_rss_ctxs = max_vnics; 7477 if (vnics > max_vnics || vnics > max_rss_ctxs) { 7478 if (bp->rx_nr_rings > 1) 7479 netdev_warn(bp->dev, 7480 "Not enough resources to support NTUPLE filters, enough resources for up to %d rx rings\n", 7481 min(max_rss_ctxs - 1, max_vnics - 1)); 7482 return false; 7483 } 7484 7485 if (!BNXT_NEW_RM(bp)) 7486 return true; 7487 7488 if (vnics == bp->hw_resc.resv_vnics) 7489 return true; 7490 7491 bnxt_hwrm_reserve_rings(bp, 0, 0, 0, 0, vnics); 7492 if (vnics <= bp->hw_resc.resv_vnics) 7493 return true; 7494 7495 netdev_warn(bp->dev, "Unable to reserve resources to support NTUPLE filters.\n"); 7496 bnxt_hwrm_reserve_rings(bp, 0, 0, 0, 0, 1); 7497 return false; 7498 #else 7499 return false; 7500 #endif 7501 } 7502 7503 static netdev_features_t bnxt_fix_features(struct net_device *dev, 7504 netdev_features_t features) 7505 { 7506 struct bnxt *bp = netdev_priv(dev); 7507 7508 if ((features & NETIF_F_NTUPLE) && !bnxt_rfs_capable(bp)) 7509 features &= ~NETIF_F_NTUPLE; 7510 7511 if (bp->flags & BNXT_FLAG_NO_AGG_RINGS) 7512 features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW); 7513 7514 if (!(features & NETIF_F_GRO)) 7515 features &= ~NETIF_F_GRO_HW; 7516 7517 if (features & NETIF_F_GRO_HW) 7518 features &= ~NETIF_F_LRO; 7519 7520 /* Both CTAG and STAG VLAN accelaration on the RX side have to be 7521 * turned on or off together. 7522 */ 7523 if ((features & (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) != 7524 (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) { 7525 if (dev->features & NETIF_F_HW_VLAN_CTAG_RX) 7526 features &= ~(NETIF_F_HW_VLAN_CTAG_RX | 7527 NETIF_F_HW_VLAN_STAG_RX); 7528 else 7529 features |= NETIF_F_HW_VLAN_CTAG_RX | 7530 NETIF_F_HW_VLAN_STAG_RX; 7531 } 7532 #ifdef CONFIG_BNXT_SRIOV 7533 if (BNXT_VF(bp)) { 7534 if (bp->vf.vlan) { 7535 features &= ~(NETIF_F_HW_VLAN_CTAG_RX | 7536 NETIF_F_HW_VLAN_STAG_RX); 7537 } 7538 } 7539 #endif 7540 return features; 7541 } 7542 7543 static int bnxt_set_features(struct net_device *dev, netdev_features_t features) 7544 { 7545 struct bnxt *bp = netdev_priv(dev); 7546 u32 flags = bp->flags; 7547 u32 changes; 7548 int rc = 0; 7549 bool re_init = false; 7550 bool update_tpa = false; 7551 7552 flags &= ~BNXT_FLAG_ALL_CONFIG_FEATS; 7553 if (features & NETIF_F_GRO_HW) 7554 flags |= BNXT_FLAG_GRO; 7555 else if (features & NETIF_F_LRO) 7556 flags |= BNXT_FLAG_LRO; 7557 7558 if (bp->flags & BNXT_FLAG_NO_AGG_RINGS) 7559 flags &= ~BNXT_FLAG_TPA; 7560 7561 if (features & NETIF_F_HW_VLAN_CTAG_RX) 7562 flags |= BNXT_FLAG_STRIP_VLAN; 7563 7564 if (features & NETIF_F_NTUPLE) 7565 flags |= BNXT_FLAG_RFS; 7566 7567 changes = flags ^ bp->flags; 7568 if (changes & BNXT_FLAG_TPA) { 7569 update_tpa = true; 7570 if ((bp->flags & BNXT_FLAG_TPA) == 0 || 7571 (flags & BNXT_FLAG_TPA) == 0) 7572 re_init = true; 7573 } 7574 7575 if (changes & ~BNXT_FLAG_TPA) 7576 re_init = true; 7577 7578 if (flags != bp->flags) { 7579 u32 old_flags = bp->flags; 7580 7581 bp->flags = flags; 7582 7583 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) { 7584 if (update_tpa) 7585 bnxt_set_ring_params(bp); 7586 return rc; 7587 } 7588 7589 if (re_init) { 7590 bnxt_close_nic(bp, false, false); 7591 if (update_tpa) 7592 bnxt_set_ring_params(bp); 7593 7594 return bnxt_open_nic(bp, false, false); 7595 } 7596 if (update_tpa) { 7597 rc = bnxt_set_tpa(bp, 7598 (flags & BNXT_FLAG_TPA) ? 7599 true : false); 7600 if (rc) 7601 bp->flags = old_flags; 7602 } 7603 } 7604 return rc; 7605 } 7606 7607 static void bnxt_dump_tx_sw_state(struct bnxt_napi *bnapi) 7608 { 7609 struct bnxt_tx_ring_info *txr = bnapi->tx_ring; 7610 int i = bnapi->index; 7611 7612 if (!txr) 7613 return; 7614 7615 netdev_info(bnapi->bp->dev, "[%d]: tx{fw_ring: %d prod: %x cons: %x}\n", 7616 i, txr->tx_ring_struct.fw_ring_id, txr->tx_prod, 7617 txr->tx_cons); 7618 } 7619 7620 static void bnxt_dump_rx_sw_state(struct bnxt_napi *bnapi) 7621 { 7622 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 7623 int i = bnapi->index; 7624 7625 if (!rxr) 7626 return; 7627 7628 netdev_info(bnapi->bp->dev, "[%d]: rx{fw_ring: %d prod: %x} rx_agg{fw_ring: %d agg_prod: %x sw_agg_prod: %x}\n", 7629 i, rxr->rx_ring_struct.fw_ring_id, rxr->rx_prod, 7630 rxr->rx_agg_ring_struct.fw_ring_id, rxr->rx_agg_prod, 7631 rxr->rx_sw_agg_prod); 7632 } 7633 7634 static void bnxt_dump_cp_sw_state(struct bnxt_napi *bnapi) 7635 { 7636 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 7637 int i = bnapi->index; 7638 7639 netdev_info(bnapi->bp->dev, "[%d]: cp{fw_ring: %d raw_cons: %x}\n", 7640 i, cpr->cp_ring_struct.fw_ring_id, cpr->cp_raw_cons); 7641 } 7642 7643 static void bnxt_dbg_dump_states(struct bnxt *bp) 7644 { 7645 int i; 7646 struct bnxt_napi *bnapi; 7647 7648 for (i = 0; i < bp->cp_nr_rings; i++) { 7649 bnapi = bp->bnapi[i]; 7650 if (netif_msg_drv(bp)) { 7651 bnxt_dump_tx_sw_state(bnapi); 7652 bnxt_dump_rx_sw_state(bnapi); 7653 bnxt_dump_cp_sw_state(bnapi); 7654 } 7655 } 7656 } 7657 7658 static void bnxt_reset_task(struct bnxt *bp, bool silent) 7659 { 7660 if (!silent) 7661 bnxt_dbg_dump_states(bp); 7662 if (netif_running(bp->dev)) { 7663 int rc; 7664 7665 if (!silent) 7666 bnxt_ulp_stop(bp); 7667 bnxt_close_nic(bp, false, false); 7668 rc = bnxt_open_nic(bp, false, false); 7669 if (!silent && !rc) 7670 bnxt_ulp_start(bp); 7671 } 7672 } 7673 7674 static void bnxt_tx_timeout(struct net_device *dev) 7675 { 7676 struct bnxt *bp = netdev_priv(dev); 7677 7678 netdev_err(bp->dev, "TX timeout detected, starting reset task!\n"); 7679 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event); 7680 bnxt_queue_sp_work(bp); 7681 } 7682 7683 static void bnxt_timer(struct timer_list *t) 7684 { 7685 struct bnxt *bp = from_timer(bp, t, timer); 7686 struct net_device *dev = bp->dev; 7687 7688 if (!netif_running(dev)) 7689 return; 7690 7691 if (atomic_read(&bp->intr_sem) != 0) 7692 goto bnxt_restart_timer; 7693 7694 if (bp->link_info.link_up && (bp->flags & BNXT_FLAG_PORT_STATS) && 7695 bp->stats_coal_ticks) { 7696 set_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event); 7697 bnxt_queue_sp_work(bp); 7698 } 7699 7700 if (bnxt_tc_flower_enabled(bp)) { 7701 set_bit(BNXT_FLOW_STATS_SP_EVENT, &bp->sp_event); 7702 bnxt_queue_sp_work(bp); 7703 } 7704 7705 if (bp->link_info.phy_retry) { 7706 if (time_after(jiffies, bp->link_info.phy_retry_expires)) { 7707 bp->link_info.phy_retry = 0; 7708 netdev_warn(bp->dev, "failed to update phy settings after maximum retries.\n"); 7709 } else { 7710 set_bit(BNXT_UPDATE_PHY_SP_EVENT, &bp->sp_event); 7711 bnxt_queue_sp_work(bp); 7712 } 7713 } 7714 bnxt_restart_timer: 7715 mod_timer(&bp->timer, jiffies + bp->current_interval); 7716 } 7717 7718 static void bnxt_rtnl_lock_sp(struct bnxt *bp) 7719 { 7720 /* We are called from bnxt_sp_task which has BNXT_STATE_IN_SP_TASK 7721 * set. If the device is being closed, bnxt_close() may be holding 7722 * rtnl() and waiting for BNXT_STATE_IN_SP_TASK to clear. So we 7723 * must clear BNXT_STATE_IN_SP_TASK before holding rtnl(). 7724 */ 7725 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state); 7726 rtnl_lock(); 7727 } 7728 7729 static void bnxt_rtnl_unlock_sp(struct bnxt *bp) 7730 { 7731 set_bit(BNXT_STATE_IN_SP_TASK, &bp->state); 7732 rtnl_unlock(); 7733 } 7734 7735 /* Only called from bnxt_sp_task() */ 7736 static void bnxt_reset(struct bnxt *bp, bool silent) 7737 { 7738 bnxt_rtnl_lock_sp(bp); 7739 if (test_bit(BNXT_STATE_OPEN, &bp->state)) 7740 bnxt_reset_task(bp, silent); 7741 bnxt_rtnl_unlock_sp(bp); 7742 } 7743 7744 static void bnxt_cfg_ntp_filters(struct bnxt *); 7745 7746 static void bnxt_sp_task(struct work_struct *work) 7747 { 7748 struct bnxt *bp = container_of(work, struct bnxt, sp_task); 7749 7750 set_bit(BNXT_STATE_IN_SP_TASK, &bp->state); 7751 smp_mb__after_atomic(); 7752 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) { 7753 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state); 7754 return; 7755 } 7756 7757 if (test_and_clear_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event)) 7758 bnxt_cfg_rx_mode(bp); 7759 7760 if (test_and_clear_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event)) 7761 bnxt_cfg_ntp_filters(bp); 7762 if (test_and_clear_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event)) 7763 bnxt_hwrm_exec_fwd_req(bp); 7764 if (test_and_clear_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event)) { 7765 bnxt_hwrm_tunnel_dst_port_alloc( 7766 bp, bp->vxlan_port, 7767 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN); 7768 } 7769 if (test_and_clear_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event)) { 7770 bnxt_hwrm_tunnel_dst_port_free( 7771 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN); 7772 } 7773 if (test_and_clear_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event)) { 7774 bnxt_hwrm_tunnel_dst_port_alloc( 7775 bp, bp->nge_port, 7776 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE); 7777 } 7778 if (test_and_clear_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event)) { 7779 bnxt_hwrm_tunnel_dst_port_free( 7780 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE); 7781 } 7782 if (test_and_clear_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event)) { 7783 bnxt_hwrm_port_qstats(bp); 7784 bnxt_hwrm_port_qstats_ext(bp); 7785 } 7786 7787 if (test_and_clear_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event)) { 7788 int rc; 7789 7790 mutex_lock(&bp->link_lock); 7791 if (test_and_clear_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT, 7792 &bp->sp_event)) 7793 bnxt_hwrm_phy_qcaps(bp); 7794 7795 rc = bnxt_update_link(bp, true); 7796 mutex_unlock(&bp->link_lock); 7797 if (rc) 7798 netdev_err(bp->dev, "SP task can't update link (rc: %x)\n", 7799 rc); 7800 } 7801 if (test_and_clear_bit(BNXT_UPDATE_PHY_SP_EVENT, &bp->sp_event)) { 7802 int rc; 7803 7804 mutex_lock(&bp->link_lock); 7805 rc = bnxt_update_phy_setting(bp); 7806 mutex_unlock(&bp->link_lock); 7807 if (rc) { 7808 netdev_warn(bp->dev, "update phy settings retry failed\n"); 7809 } else { 7810 bp->link_info.phy_retry = false; 7811 netdev_info(bp->dev, "update phy settings retry succeeded\n"); 7812 } 7813 } 7814 if (test_and_clear_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event)) { 7815 mutex_lock(&bp->link_lock); 7816 bnxt_get_port_module_status(bp); 7817 mutex_unlock(&bp->link_lock); 7818 } 7819 7820 if (test_and_clear_bit(BNXT_FLOW_STATS_SP_EVENT, &bp->sp_event)) 7821 bnxt_tc_flow_stats_work(bp); 7822 7823 /* These functions below will clear BNXT_STATE_IN_SP_TASK. They 7824 * must be the last functions to be called before exiting. 7825 */ 7826 if (test_and_clear_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event)) 7827 bnxt_reset(bp, false); 7828 7829 if (test_and_clear_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event)) 7830 bnxt_reset(bp, true); 7831 7832 smp_mb__before_atomic(); 7833 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state); 7834 } 7835 7836 /* Under rtnl_lock */ 7837 int bnxt_check_rings(struct bnxt *bp, int tx, int rx, bool sh, int tcs, 7838 int tx_xdp) 7839 { 7840 int max_rx, max_tx, tx_sets = 1; 7841 int tx_rings_needed; 7842 int rx_rings = rx; 7843 int cp, vnics, rc; 7844 7845 if (tcs) 7846 tx_sets = tcs; 7847 7848 rc = bnxt_get_max_rings(bp, &max_rx, &max_tx, sh); 7849 if (rc) 7850 return rc; 7851 7852 if (max_rx < rx) 7853 return -ENOMEM; 7854 7855 tx_rings_needed = tx * tx_sets + tx_xdp; 7856 if (max_tx < tx_rings_needed) 7857 return -ENOMEM; 7858 7859 vnics = 1; 7860 if (bp->flags & BNXT_FLAG_RFS) 7861 vnics += rx_rings; 7862 7863 if (bp->flags & BNXT_FLAG_AGG_RINGS) 7864 rx_rings <<= 1; 7865 cp = sh ? max_t(int, tx_rings_needed, rx) : tx_rings_needed + rx; 7866 if (BNXT_NEW_RM(bp)) 7867 cp += bnxt_get_ulp_msix_num(bp); 7868 return bnxt_hwrm_check_rings(bp, tx_rings_needed, rx_rings, rx, cp, 7869 vnics); 7870 } 7871 7872 static void bnxt_unmap_bars(struct bnxt *bp, struct pci_dev *pdev) 7873 { 7874 if (bp->bar2) { 7875 pci_iounmap(pdev, bp->bar2); 7876 bp->bar2 = NULL; 7877 } 7878 7879 if (bp->bar1) { 7880 pci_iounmap(pdev, bp->bar1); 7881 bp->bar1 = NULL; 7882 } 7883 7884 if (bp->bar0) { 7885 pci_iounmap(pdev, bp->bar0); 7886 bp->bar0 = NULL; 7887 } 7888 } 7889 7890 static void bnxt_cleanup_pci(struct bnxt *bp) 7891 { 7892 bnxt_unmap_bars(bp, bp->pdev); 7893 pci_release_regions(bp->pdev); 7894 pci_disable_device(bp->pdev); 7895 } 7896 7897 static void bnxt_init_dflt_coal(struct bnxt *bp) 7898 { 7899 struct bnxt_coal *coal; 7900 7901 /* Tick values in micro seconds. 7902 * 1 coal_buf x bufs_per_record = 1 completion record. 7903 */ 7904 coal = &bp->rx_coal; 7905 coal->coal_ticks = 14; 7906 coal->coal_bufs = 30; 7907 coal->coal_ticks_irq = 1; 7908 coal->coal_bufs_irq = 2; 7909 coal->idle_thresh = 50; 7910 coal->bufs_per_record = 2; 7911 coal->budget = 64; /* NAPI budget */ 7912 7913 coal = &bp->tx_coal; 7914 coal->coal_ticks = 28; 7915 coal->coal_bufs = 30; 7916 coal->coal_ticks_irq = 2; 7917 coal->coal_bufs_irq = 2; 7918 coal->bufs_per_record = 1; 7919 7920 bp->stats_coal_ticks = BNXT_DEF_STATS_COAL_TICKS; 7921 } 7922 7923 static int bnxt_init_board(struct pci_dev *pdev, struct net_device *dev) 7924 { 7925 int rc; 7926 struct bnxt *bp = netdev_priv(dev); 7927 7928 SET_NETDEV_DEV(dev, &pdev->dev); 7929 7930 /* enable device (incl. PCI PM wakeup), and bus-mastering */ 7931 rc = pci_enable_device(pdev); 7932 if (rc) { 7933 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n"); 7934 goto init_err; 7935 } 7936 7937 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 7938 dev_err(&pdev->dev, 7939 "Cannot find PCI device base address, aborting\n"); 7940 rc = -ENODEV; 7941 goto init_err_disable; 7942 } 7943 7944 rc = pci_request_regions(pdev, DRV_MODULE_NAME); 7945 if (rc) { 7946 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n"); 7947 goto init_err_disable; 7948 } 7949 7950 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) != 0 && 7951 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)) != 0) { 7952 dev_err(&pdev->dev, "System does not support DMA, aborting\n"); 7953 goto init_err_disable; 7954 } 7955 7956 pci_set_master(pdev); 7957 7958 bp->dev = dev; 7959 bp->pdev = pdev; 7960 7961 bp->bar0 = pci_ioremap_bar(pdev, 0); 7962 if (!bp->bar0) { 7963 dev_err(&pdev->dev, "Cannot map device registers, aborting\n"); 7964 rc = -ENOMEM; 7965 goto init_err_release; 7966 } 7967 7968 bp->bar1 = pci_ioremap_bar(pdev, 2); 7969 if (!bp->bar1) { 7970 dev_err(&pdev->dev, "Cannot map doorbell registers, aborting\n"); 7971 rc = -ENOMEM; 7972 goto init_err_release; 7973 } 7974 7975 bp->bar2 = pci_ioremap_bar(pdev, 4); 7976 if (!bp->bar2) { 7977 dev_err(&pdev->dev, "Cannot map bar4 registers, aborting\n"); 7978 rc = -ENOMEM; 7979 goto init_err_release; 7980 } 7981 7982 pci_enable_pcie_error_reporting(pdev); 7983 7984 INIT_WORK(&bp->sp_task, bnxt_sp_task); 7985 7986 spin_lock_init(&bp->ntp_fltr_lock); 7987 7988 bp->rx_ring_size = BNXT_DEFAULT_RX_RING_SIZE; 7989 bp->tx_ring_size = BNXT_DEFAULT_TX_RING_SIZE; 7990 7991 bnxt_init_dflt_coal(bp); 7992 7993 timer_setup(&bp->timer, bnxt_timer, 0); 7994 bp->current_interval = BNXT_TIMER_INTERVAL; 7995 7996 clear_bit(BNXT_STATE_OPEN, &bp->state); 7997 return 0; 7998 7999 init_err_release: 8000 bnxt_unmap_bars(bp, pdev); 8001 pci_release_regions(pdev); 8002 8003 init_err_disable: 8004 pci_disable_device(pdev); 8005 8006 init_err: 8007 return rc; 8008 } 8009 8010 /* rtnl_lock held */ 8011 static int bnxt_change_mac_addr(struct net_device *dev, void *p) 8012 { 8013 struct sockaddr *addr = p; 8014 struct bnxt *bp = netdev_priv(dev); 8015 int rc = 0; 8016 8017 if (!is_valid_ether_addr(addr->sa_data)) 8018 return -EADDRNOTAVAIL; 8019 8020 if (ether_addr_equal(addr->sa_data, dev->dev_addr)) 8021 return 0; 8022 8023 rc = bnxt_approve_mac(bp, addr->sa_data, true); 8024 if (rc) 8025 return rc; 8026 8027 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); 8028 if (netif_running(dev)) { 8029 bnxt_close_nic(bp, false, false); 8030 rc = bnxt_open_nic(bp, false, false); 8031 } 8032 8033 return rc; 8034 } 8035 8036 /* rtnl_lock held */ 8037 static int bnxt_change_mtu(struct net_device *dev, int new_mtu) 8038 { 8039 struct bnxt *bp = netdev_priv(dev); 8040 8041 if (netif_running(dev)) 8042 bnxt_close_nic(bp, false, false); 8043 8044 dev->mtu = new_mtu; 8045 bnxt_set_ring_params(bp); 8046 8047 if (netif_running(dev)) 8048 return bnxt_open_nic(bp, false, false); 8049 8050 return 0; 8051 } 8052 8053 int bnxt_setup_mq_tc(struct net_device *dev, u8 tc) 8054 { 8055 struct bnxt *bp = netdev_priv(dev); 8056 bool sh = false; 8057 int rc; 8058 8059 if (tc > bp->max_tc) { 8060 netdev_err(dev, "Too many traffic classes requested: %d. Max supported is %d.\n", 8061 tc, bp->max_tc); 8062 return -EINVAL; 8063 } 8064 8065 if (netdev_get_num_tc(dev) == tc) 8066 return 0; 8067 8068 if (bp->flags & BNXT_FLAG_SHARED_RINGS) 8069 sh = true; 8070 8071 rc = bnxt_check_rings(bp, bp->tx_nr_rings_per_tc, bp->rx_nr_rings, 8072 sh, tc, bp->tx_nr_rings_xdp); 8073 if (rc) 8074 return rc; 8075 8076 /* Needs to close the device and do hw resource re-allocations */ 8077 if (netif_running(bp->dev)) 8078 bnxt_close_nic(bp, true, false); 8079 8080 if (tc) { 8081 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tc; 8082 netdev_set_num_tc(dev, tc); 8083 } else { 8084 bp->tx_nr_rings = bp->tx_nr_rings_per_tc; 8085 netdev_reset_tc(dev); 8086 } 8087 bp->tx_nr_rings += bp->tx_nr_rings_xdp; 8088 bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) : 8089 bp->tx_nr_rings + bp->rx_nr_rings; 8090 bp->num_stat_ctxs = bp->cp_nr_rings; 8091 8092 if (netif_running(bp->dev)) 8093 return bnxt_open_nic(bp, true, false); 8094 8095 return 0; 8096 } 8097 8098 static int bnxt_setup_tc_block_cb(enum tc_setup_type type, void *type_data, 8099 void *cb_priv) 8100 { 8101 struct bnxt *bp = cb_priv; 8102 8103 if (!bnxt_tc_flower_enabled(bp) || 8104 !tc_cls_can_offload_and_chain0(bp->dev, type_data)) 8105 return -EOPNOTSUPP; 8106 8107 switch (type) { 8108 case TC_SETUP_CLSFLOWER: 8109 return bnxt_tc_setup_flower(bp, bp->pf.fw_fid, type_data); 8110 default: 8111 return -EOPNOTSUPP; 8112 } 8113 } 8114 8115 static int bnxt_setup_tc_block(struct net_device *dev, 8116 struct tc_block_offload *f) 8117 { 8118 struct bnxt *bp = netdev_priv(dev); 8119 8120 if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS) 8121 return -EOPNOTSUPP; 8122 8123 switch (f->command) { 8124 case TC_BLOCK_BIND: 8125 return tcf_block_cb_register(f->block, bnxt_setup_tc_block_cb, 8126 bp, bp, f->extack); 8127 case TC_BLOCK_UNBIND: 8128 tcf_block_cb_unregister(f->block, bnxt_setup_tc_block_cb, bp); 8129 return 0; 8130 default: 8131 return -EOPNOTSUPP; 8132 } 8133 } 8134 8135 static int bnxt_setup_tc(struct net_device *dev, enum tc_setup_type type, 8136 void *type_data) 8137 { 8138 switch (type) { 8139 case TC_SETUP_BLOCK: 8140 return bnxt_setup_tc_block(dev, type_data); 8141 case TC_SETUP_QDISC_MQPRIO: { 8142 struct tc_mqprio_qopt *mqprio = type_data; 8143 8144 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS; 8145 8146 return bnxt_setup_mq_tc(dev, mqprio->num_tc); 8147 } 8148 default: 8149 return -EOPNOTSUPP; 8150 } 8151 } 8152 8153 #ifdef CONFIG_RFS_ACCEL 8154 static bool bnxt_fltr_match(struct bnxt_ntuple_filter *f1, 8155 struct bnxt_ntuple_filter *f2) 8156 { 8157 struct flow_keys *keys1 = &f1->fkeys; 8158 struct flow_keys *keys2 = &f2->fkeys; 8159 8160 if (keys1->addrs.v4addrs.src == keys2->addrs.v4addrs.src && 8161 keys1->addrs.v4addrs.dst == keys2->addrs.v4addrs.dst && 8162 keys1->ports.ports == keys2->ports.ports && 8163 keys1->basic.ip_proto == keys2->basic.ip_proto && 8164 keys1->basic.n_proto == keys2->basic.n_proto && 8165 keys1->control.flags == keys2->control.flags && 8166 ether_addr_equal(f1->src_mac_addr, f2->src_mac_addr) && 8167 ether_addr_equal(f1->dst_mac_addr, f2->dst_mac_addr)) 8168 return true; 8169 8170 return false; 8171 } 8172 8173 static int bnxt_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb, 8174 u16 rxq_index, u32 flow_id) 8175 { 8176 struct bnxt *bp = netdev_priv(dev); 8177 struct bnxt_ntuple_filter *fltr, *new_fltr; 8178 struct flow_keys *fkeys; 8179 struct ethhdr *eth = (struct ethhdr *)skb_mac_header(skb); 8180 int rc = 0, idx, bit_id, l2_idx = 0; 8181 struct hlist_head *head; 8182 8183 if (!ether_addr_equal(dev->dev_addr, eth->h_dest)) { 8184 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 8185 int off = 0, j; 8186 8187 netif_addr_lock_bh(dev); 8188 for (j = 0; j < vnic->uc_filter_count; j++, off += ETH_ALEN) { 8189 if (ether_addr_equal(eth->h_dest, 8190 vnic->uc_list + off)) { 8191 l2_idx = j + 1; 8192 break; 8193 } 8194 } 8195 netif_addr_unlock_bh(dev); 8196 if (!l2_idx) 8197 return -EINVAL; 8198 } 8199 new_fltr = kzalloc(sizeof(*new_fltr), GFP_ATOMIC); 8200 if (!new_fltr) 8201 return -ENOMEM; 8202 8203 fkeys = &new_fltr->fkeys; 8204 if (!skb_flow_dissect_flow_keys(skb, fkeys, 0)) { 8205 rc = -EPROTONOSUPPORT; 8206 goto err_free; 8207 } 8208 8209 if ((fkeys->basic.n_proto != htons(ETH_P_IP) && 8210 fkeys->basic.n_proto != htons(ETH_P_IPV6)) || 8211 ((fkeys->basic.ip_proto != IPPROTO_TCP) && 8212 (fkeys->basic.ip_proto != IPPROTO_UDP))) { 8213 rc = -EPROTONOSUPPORT; 8214 goto err_free; 8215 } 8216 if (fkeys->basic.n_proto == htons(ETH_P_IPV6) && 8217 bp->hwrm_spec_code < 0x10601) { 8218 rc = -EPROTONOSUPPORT; 8219 goto err_free; 8220 } 8221 if ((fkeys->control.flags & FLOW_DIS_ENCAPSULATION) && 8222 bp->hwrm_spec_code < 0x10601) { 8223 rc = -EPROTONOSUPPORT; 8224 goto err_free; 8225 } 8226 8227 memcpy(new_fltr->dst_mac_addr, eth->h_dest, ETH_ALEN); 8228 memcpy(new_fltr->src_mac_addr, eth->h_source, ETH_ALEN); 8229 8230 idx = skb_get_hash_raw(skb) & BNXT_NTP_FLTR_HASH_MASK; 8231 head = &bp->ntp_fltr_hash_tbl[idx]; 8232 rcu_read_lock(); 8233 hlist_for_each_entry_rcu(fltr, head, hash) { 8234 if (bnxt_fltr_match(fltr, new_fltr)) { 8235 rcu_read_unlock(); 8236 rc = 0; 8237 goto err_free; 8238 } 8239 } 8240 rcu_read_unlock(); 8241 8242 spin_lock_bh(&bp->ntp_fltr_lock); 8243 bit_id = bitmap_find_free_region(bp->ntp_fltr_bmap, 8244 BNXT_NTP_FLTR_MAX_FLTR, 0); 8245 if (bit_id < 0) { 8246 spin_unlock_bh(&bp->ntp_fltr_lock); 8247 rc = -ENOMEM; 8248 goto err_free; 8249 } 8250 8251 new_fltr->sw_id = (u16)bit_id; 8252 new_fltr->flow_id = flow_id; 8253 new_fltr->l2_fltr_idx = l2_idx; 8254 new_fltr->rxq = rxq_index; 8255 hlist_add_head_rcu(&new_fltr->hash, head); 8256 bp->ntp_fltr_count++; 8257 spin_unlock_bh(&bp->ntp_fltr_lock); 8258 8259 set_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event); 8260 bnxt_queue_sp_work(bp); 8261 8262 return new_fltr->sw_id; 8263 8264 err_free: 8265 kfree(new_fltr); 8266 return rc; 8267 } 8268 8269 static void bnxt_cfg_ntp_filters(struct bnxt *bp) 8270 { 8271 int i; 8272 8273 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) { 8274 struct hlist_head *head; 8275 struct hlist_node *tmp; 8276 struct bnxt_ntuple_filter *fltr; 8277 int rc; 8278 8279 head = &bp->ntp_fltr_hash_tbl[i]; 8280 hlist_for_each_entry_safe(fltr, tmp, head, hash) { 8281 bool del = false; 8282 8283 if (test_bit(BNXT_FLTR_VALID, &fltr->state)) { 8284 if (rps_may_expire_flow(bp->dev, fltr->rxq, 8285 fltr->flow_id, 8286 fltr->sw_id)) { 8287 bnxt_hwrm_cfa_ntuple_filter_free(bp, 8288 fltr); 8289 del = true; 8290 } 8291 } else { 8292 rc = bnxt_hwrm_cfa_ntuple_filter_alloc(bp, 8293 fltr); 8294 if (rc) 8295 del = true; 8296 else 8297 set_bit(BNXT_FLTR_VALID, &fltr->state); 8298 } 8299 8300 if (del) { 8301 spin_lock_bh(&bp->ntp_fltr_lock); 8302 hlist_del_rcu(&fltr->hash); 8303 bp->ntp_fltr_count--; 8304 spin_unlock_bh(&bp->ntp_fltr_lock); 8305 synchronize_rcu(); 8306 clear_bit(fltr->sw_id, bp->ntp_fltr_bmap); 8307 kfree(fltr); 8308 } 8309 } 8310 } 8311 if (test_and_clear_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event)) 8312 netdev_info(bp->dev, "Receive PF driver unload event!"); 8313 } 8314 8315 #else 8316 8317 static void bnxt_cfg_ntp_filters(struct bnxt *bp) 8318 { 8319 } 8320 8321 #endif /* CONFIG_RFS_ACCEL */ 8322 8323 static void bnxt_udp_tunnel_add(struct net_device *dev, 8324 struct udp_tunnel_info *ti) 8325 { 8326 struct bnxt *bp = netdev_priv(dev); 8327 8328 if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET) 8329 return; 8330 8331 if (!netif_running(dev)) 8332 return; 8333 8334 switch (ti->type) { 8335 case UDP_TUNNEL_TYPE_VXLAN: 8336 if (bp->vxlan_port_cnt && bp->vxlan_port != ti->port) 8337 return; 8338 8339 bp->vxlan_port_cnt++; 8340 if (bp->vxlan_port_cnt == 1) { 8341 bp->vxlan_port = ti->port; 8342 set_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event); 8343 bnxt_queue_sp_work(bp); 8344 } 8345 break; 8346 case UDP_TUNNEL_TYPE_GENEVE: 8347 if (bp->nge_port_cnt && bp->nge_port != ti->port) 8348 return; 8349 8350 bp->nge_port_cnt++; 8351 if (bp->nge_port_cnt == 1) { 8352 bp->nge_port = ti->port; 8353 set_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event); 8354 } 8355 break; 8356 default: 8357 return; 8358 } 8359 8360 bnxt_queue_sp_work(bp); 8361 } 8362 8363 static void bnxt_udp_tunnel_del(struct net_device *dev, 8364 struct udp_tunnel_info *ti) 8365 { 8366 struct bnxt *bp = netdev_priv(dev); 8367 8368 if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET) 8369 return; 8370 8371 if (!netif_running(dev)) 8372 return; 8373 8374 switch (ti->type) { 8375 case UDP_TUNNEL_TYPE_VXLAN: 8376 if (!bp->vxlan_port_cnt || bp->vxlan_port != ti->port) 8377 return; 8378 bp->vxlan_port_cnt--; 8379 8380 if (bp->vxlan_port_cnt != 0) 8381 return; 8382 8383 set_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event); 8384 break; 8385 case UDP_TUNNEL_TYPE_GENEVE: 8386 if (!bp->nge_port_cnt || bp->nge_port != ti->port) 8387 return; 8388 bp->nge_port_cnt--; 8389 8390 if (bp->nge_port_cnt != 0) 8391 return; 8392 8393 set_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event); 8394 break; 8395 default: 8396 return; 8397 } 8398 8399 bnxt_queue_sp_work(bp); 8400 } 8401 8402 static int bnxt_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq, 8403 struct net_device *dev, u32 filter_mask, 8404 int nlflags) 8405 { 8406 struct bnxt *bp = netdev_priv(dev); 8407 8408 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, bp->br_mode, 0, 0, 8409 nlflags, filter_mask, NULL); 8410 } 8411 8412 static int bnxt_bridge_setlink(struct net_device *dev, struct nlmsghdr *nlh, 8413 u16 flags) 8414 { 8415 struct bnxt *bp = netdev_priv(dev); 8416 struct nlattr *attr, *br_spec; 8417 int rem, rc = 0; 8418 8419 if (bp->hwrm_spec_code < 0x10708 || !BNXT_SINGLE_PF(bp)) 8420 return -EOPNOTSUPP; 8421 8422 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC); 8423 if (!br_spec) 8424 return -EINVAL; 8425 8426 nla_for_each_nested(attr, br_spec, rem) { 8427 u16 mode; 8428 8429 if (nla_type(attr) != IFLA_BRIDGE_MODE) 8430 continue; 8431 8432 if (nla_len(attr) < sizeof(mode)) 8433 return -EINVAL; 8434 8435 mode = nla_get_u16(attr); 8436 if (mode == bp->br_mode) 8437 break; 8438 8439 rc = bnxt_hwrm_set_br_mode(bp, mode); 8440 if (!rc) 8441 bp->br_mode = mode; 8442 break; 8443 } 8444 return rc; 8445 } 8446 8447 static int bnxt_get_phys_port_name(struct net_device *dev, char *buf, 8448 size_t len) 8449 { 8450 struct bnxt *bp = netdev_priv(dev); 8451 int rc; 8452 8453 /* The PF and it's VF-reps only support the switchdev framework */ 8454 if (!BNXT_PF(bp)) 8455 return -EOPNOTSUPP; 8456 8457 rc = snprintf(buf, len, "p%d", bp->pf.port_id); 8458 8459 if (rc >= len) 8460 return -EOPNOTSUPP; 8461 return 0; 8462 } 8463 8464 int bnxt_port_attr_get(struct bnxt *bp, struct switchdev_attr *attr) 8465 { 8466 if (bp->eswitch_mode != DEVLINK_ESWITCH_MODE_SWITCHDEV) 8467 return -EOPNOTSUPP; 8468 8469 /* The PF and it's VF-reps only support the switchdev framework */ 8470 if (!BNXT_PF(bp)) 8471 return -EOPNOTSUPP; 8472 8473 switch (attr->id) { 8474 case SWITCHDEV_ATTR_ID_PORT_PARENT_ID: 8475 attr->u.ppid.id_len = sizeof(bp->switch_id); 8476 memcpy(attr->u.ppid.id, bp->switch_id, attr->u.ppid.id_len); 8477 break; 8478 default: 8479 return -EOPNOTSUPP; 8480 } 8481 return 0; 8482 } 8483 8484 static int bnxt_swdev_port_attr_get(struct net_device *dev, 8485 struct switchdev_attr *attr) 8486 { 8487 return bnxt_port_attr_get(netdev_priv(dev), attr); 8488 } 8489 8490 static const struct switchdev_ops bnxt_switchdev_ops = { 8491 .switchdev_port_attr_get = bnxt_swdev_port_attr_get 8492 }; 8493 8494 static const struct net_device_ops bnxt_netdev_ops = { 8495 .ndo_open = bnxt_open, 8496 .ndo_start_xmit = bnxt_start_xmit, 8497 .ndo_stop = bnxt_close, 8498 .ndo_get_stats64 = bnxt_get_stats64, 8499 .ndo_set_rx_mode = bnxt_set_rx_mode, 8500 .ndo_do_ioctl = bnxt_ioctl, 8501 .ndo_validate_addr = eth_validate_addr, 8502 .ndo_set_mac_address = bnxt_change_mac_addr, 8503 .ndo_change_mtu = bnxt_change_mtu, 8504 .ndo_fix_features = bnxt_fix_features, 8505 .ndo_set_features = bnxt_set_features, 8506 .ndo_tx_timeout = bnxt_tx_timeout, 8507 #ifdef CONFIG_BNXT_SRIOV 8508 .ndo_get_vf_config = bnxt_get_vf_config, 8509 .ndo_set_vf_mac = bnxt_set_vf_mac, 8510 .ndo_set_vf_vlan = bnxt_set_vf_vlan, 8511 .ndo_set_vf_rate = bnxt_set_vf_bw, 8512 .ndo_set_vf_link_state = bnxt_set_vf_link_state, 8513 .ndo_set_vf_spoofchk = bnxt_set_vf_spoofchk, 8514 .ndo_set_vf_trust = bnxt_set_vf_trust, 8515 #endif 8516 .ndo_setup_tc = bnxt_setup_tc, 8517 #ifdef CONFIG_RFS_ACCEL 8518 .ndo_rx_flow_steer = bnxt_rx_flow_steer, 8519 #endif 8520 .ndo_udp_tunnel_add = bnxt_udp_tunnel_add, 8521 .ndo_udp_tunnel_del = bnxt_udp_tunnel_del, 8522 .ndo_bpf = bnxt_xdp, 8523 .ndo_bridge_getlink = bnxt_bridge_getlink, 8524 .ndo_bridge_setlink = bnxt_bridge_setlink, 8525 .ndo_get_phys_port_name = bnxt_get_phys_port_name 8526 }; 8527 8528 static void bnxt_remove_one(struct pci_dev *pdev) 8529 { 8530 struct net_device *dev = pci_get_drvdata(pdev); 8531 struct bnxt *bp = netdev_priv(dev); 8532 8533 if (BNXT_PF(bp)) { 8534 bnxt_sriov_disable(bp); 8535 bnxt_dl_unregister(bp); 8536 } 8537 8538 pci_disable_pcie_error_reporting(pdev); 8539 unregister_netdev(dev); 8540 bnxt_shutdown_tc(bp); 8541 bnxt_cancel_sp_work(bp); 8542 bp->sp_event = 0; 8543 8544 bnxt_clear_int_mode(bp); 8545 bnxt_hwrm_func_drv_unrgtr(bp); 8546 bnxt_free_hwrm_resources(bp); 8547 bnxt_free_hwrm_short_cmd_req(bp); 8548 bnxt_ethtool_free(bp); 8549 bnxt_dcb_free(bp); 8550 kfree(bp->edev); 8551 bp->edev = NULL; 8552 bnxt_cleanup_pci(bp); 8553 free_netdev(dev); 8554 } 8555 8556 static int bnxt_probe_phy(struct bnxt *bp) 8557 { 8558 int rc = 0; 8559 struct bnxt_link_info *link_info = &bp->link_info; 8560 8561 rc = bnxt_hwrm_phy_qcaps(bp); 8562 if (rc) { 8563 netdev_err(bp->dev, "Probe phy can't get phy capabilities (rc: %x)\n", 8564 rc); 8565 return rc; 8566 } 8567 mutex_init(&bp->link_lock); 8568 8569 rc = bnxt_update_link(bp, false); 8570 if (rc) { 8571 netdev_err(bp->dev, "Probe phy can't update link (rc: %x)\n", 8572 rc); 8573 return rc; 8574 } 8575 8576 /* Older firmware does not have supported_auto_speeds, so assume 8577 * that all supported speeds can be autonegotiated. 8578 */ 8579 if (link_info->auto_link_speeds && !link_info->support_auto_speeds) 8580 link_info->support_auto_speeds = link_info->support_speeds; 8581 8582 /*initialize the ethool setting copy with NVM settings */ 8583 if (BNXT_AUTO_MODE(link_info->auto_mode)) { 8584 link_info->autoneg = BNXT_AUTONEG_SPEED; 8585 if (bp->hwrm_spec_code >= 0x10201) { 8586 if (link_info->auto_pause_setting & 8587 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE) 8588 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL; 8589 } else { 8590 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL; 8591 } 8592 link_info->advertising = link_info->auto_link_speeds; 8593 } else { 8594 link_info->req_link_speed = link_info->force_link_speed; 8595 link_info->req_duplex = link_info->duplex_setting; 8596 } 8597 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) 8598 link_info->req_flow_ctrl = 8599 link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH; 8600 else 8601 link_info->req_flow_ctrl = link_info->force_pause_setting; 8602 return rc; 8603 } 8604 8605 static int bnxt_get_max_irq(struct pci_dev *pdev) 8606 { 8607 u16 ctrl; 8608 8609 if (!pdev->msix_cap) 8610 return 1; 8611 8612 pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &ctrl); 8613 return (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1; 8614 } 8615 8616 static void _bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx, 8617 int *max_cp) 8618 { 8619 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 8620 int max_ring_grps = 0; 8621 8622 *max_tx = hw_resc->max_tx_rings; 8623 *max_rx = hw_resc->max_rx_rings; 8624 *max_cp = min_t(int, bnxt_get_max_func_cp_rings_for_en(bp), 8625 hw_resc->max_irqs - bnxt_get_ulp_msix_num(bp)); 8626 *max_cp = min_t(int, *max_cp, hw_resc->max_stat_ctxs); 8627 max_ring_grps = hw_resc->max_hw_ring_grps; 8628 if (BNXT_CHIP_TYPE_NITRO_A0(bp) && BNXT_PF(bp)) { 8629 *max_cp -= 1; 8630 *max_rx -= 2; 8631 } 8632 if (bp->flags & BNXT_FLAG_AGG_RINGS) 8633 *max_rx >>= 1; 8634 *max_rx = min_t(int, *max_rx, max_ring_grps); 8635 } 8636 8637 int bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx, bool shared) 8638 { 8639 int rx, tx, cp; 8640 8641 _bnxt_get_max_rings(bp, &rx, &tx, &cp); 8642 *max_rx = rx; 8643 *max_tx = tx; 8644 if (!rx || !tx || !cp) 8645 return -ENOMEM; 8646 8647 return bnxt_trim_rings(bp, max_rx, max_tx, cp, shared); 8648 } 8649 8650 static int bnxt_get_dflt_rings(struct bnxt *bp, int *max_rx, int *max_tx, 8651 bool shared) 8652 { 8653 int rc; 8654 8655 rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared); 8656 if (rc && (bp->flags & BNXT_FLAG_AGG_RINGS)) { 8657 /* Not enough rings, try disabling agg rings. */ 8658 bp->flags &= ~BNXT_FLAG_AGG_RINGS; 8659 rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared); 8660 if (rc) { 8661 /* set BNXT_FLAG_AGG_RINGS back for consistency */ 8662 bp->flags |= BNXT_FLAG_AGG_RINGS; 8663 return rc; 8664 } 8665 bp->flags |= BNXT_FLAG_NO_AGG_RINGS; 8666 bp->dev->hw_features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW); 8667 bp->dev->features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW); 8668 bnxt_set_ring_params(bp); 8669 } 8670 8671 if (bp->flags & BNXT_FLAG_ROCE_CAP) { 8672 int max_cp, max_stat, max_irq; 8673 8674 /* Reserve minimum resources for RoCE */ 8675 max_cp = bnxt_get_max_func_cp_rings(bp); 8676 max_stat = bnxt_get_max_func_stat_ctxs(bp); 8677 max_irq = bnxt_get_max_func_irqs(bp); 8678 if (max_cp <= BNXT_MIN_ROCE_CP_RINGS || 8679 max_irq <= BNXT_MIN_ROCE_CP_RINGS || 8680 max_stat <= BNXT_MIN_ROCE_STAT_CTXS) 8681 return 0; 8682 8683 max_cp -= BNXT_MIN_ROCE_CP_RINGS; 8684 max_irq -= BNXT_MIN_ROCE_CP_RINGS; 8685 max_stat -= BNXT_MIN_ROCE_STAT_CTXS; 8686 max_cp = min_t(int, max_cp, max_irq); 8687 max_cp = min_t(int, max_cp, max_stat); 8688 rc = bnxt_trim_rings(bp, max_rx, max_tx, max_cp, shared); 8689 if (rc) 8690 rc = 0; 8691 } 8692 return rc; 8693 } 8694 8695 /* In initial default shared ring setting, each shared ring must have a 8696 * RX/TX ring pair. 8697 */ 8698 static void bnxt_trim_dflt_sh_rings(struct bnxt *bp) 8699 { 8700 bp->cp_nr_rings = min_t(int, bp->tx_nr_rings_per_tc, bp->rx_nr_rings); 8701 bp->rx_nr_rings = bp->cp_nr_rings; 8702 bp->tx_nr_rings_per_tc = bp->cp_nr_rings; 8703 bp->tx_nr_rings = bp->tx_nr_rings_per_tc; 8704 } 8705 8706 static int bnxt_set_dflt_rings(struct bnxt *bp, bool sh) 8707 { 8708 int dflt_rings, max_rx_rings, max_tx_rings, rc; 8709 8710 if (!bnxt_can_reserve_rings(bp)) 8711 return 0; 8712 8713 if (sh) 8714 bp->flags |= BNXT_FLAG_SHARED_RINGS; 8715 dflt_rings = netif_get_num_default_rss_queues(); 8716 /* Reduce default rings on multi-port cards so that total default 8717 * rings do not exceed CPU count. 8718 */ 8719 if (bp->port_count > 1) { 8720 int max_rings = 8721 max_t(int, num_online_cpus() / bp->port_count, 1); 8722 8723 dflt_rings = min_t(int, dflt_rings, max_rings); 8724 } 8725 rc = bnxt_get_dflt_rings(bp, &max_rx_rings, &max_tx_rings, sh); 8726 if (rc) 8727 return rc; 8728 bp->rx_nr_rings = min_t(int, dflt_rings, max_rx_rings); 8729 bp->tx_nr_rings_per_tc = min_t(int, dflt_rings, max_tx_rings); 8730 if (sh) 8731 bnxt_trim_dflt_sh_rings(bp); 8732 else 8733 bp->cp_nr_rings = bp->tx_nr_rings_per_tc + bp->rx_nr_rings; 8734 bp->tx_nr_rings = bp->tx_nr_rings_per_tc; 8735 8736 rc = __bnxt_reserve_rings(bp); 8737 if (rc) 8738 netdev_warn(bp->dev, "Unable to reserve tx rings\n"); 8739 bp->tx_nr_rings_per_tc = bp->tx_nr_rings; 8740 if (sh) 8741 bnxt_trim_dflt_sh_rings(bp); 8742 8743 /* Rings may have been trimmed, re-reserve the trimmed rings. */ 8744 if (bnxt_need_reserve_rings(bp)) { 8745 rc = __bnxt_reserve_rings(bp); 8746 if (rc) 8747 netdev_warn(bp->dev, "2nd rings reservation failed.\n"); 8748 bp->tx_nr_rings_per_tc = bp->tx_nr_rings; 8749 } 8750 bp->num_stat_ctxs = bp->cp_nr_rings; 8751 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) { 8752 bp->rx_nr_rings++; 8753 bp->cp_nr_rings++; 8754 } 8755 return rc; 8756 } 8757 8758 static int bnxt_init_dflt_ring_mode(struct bnxt *bp) 8759 { 8760 int rc; 8761 8762 if (bp->tx_nr_rings) 8763 return 0; 8764 8765 bnxt_ulp_irq_stop(bp); 8766 bnxt_clear_int_mode(bp); 8767 rc = bnxt_set_dflt_rings(bp, true); 8768 if (rc) { 8769 netdev_err(bp->dev, "Not enough rings available.\n"); 8770 goto init_dflt_ring_err; 8771 } 8772 rc = bnxt_init_int_mode(bp); 8773 if (rc) 8774 goto init_dflt_ring_err; 8775 8776 bp->tx_nr_rings_per_tc = bp->tx_nr_rings; 8777 if (bnxt_rfs_supported(bp) && bnxt_rfs_capable(bp)) { 8778 bp->flags |= BNXT_FLAG_RFS; 8779 bp->dev->features |= NETIF_F_NTUPLE; 8780 } 8781 init_dflt_ring_err: 8782 bnxt_ulp_irq_restart(bp, rc); 8783 return rc; 8784 } 8785 8786 int bnxt_restore_pf_fw_resources(struct bnxt *bp) 8787 { 8788 int rc; 8789 8790 ASSERT_RTNL(); 8791 bnxt_hwrm_func_qcaps(bp); 8792 8793 if (netif_running(bp->dev)) 8794 __bnxt_close_nic(bp, true, false); 8795 8796 bnxt_ulp_irq_stop(bp); 8797 bnxt_clear_int_mode(bp); 8798 rc = bnxt_init_int_mode(bp); 8799 bnxt_ulp_irq_restart(bp, rc); 8800 8801 if (netif_running(bp->dev)) { 8802 if (rc) 8803 dev_close(bp->dev); 8804 else 8805 rc = bnxt_open_nic(bp, true, false); 8806 } 8807 8808 return rc; 8809 } 8810 8811 static int bnxt_init_mac_addr(struct bnxt *bp) 8812 { 8813 int rc = 0; 8814 8815 if (BNXT_PF(bp)) { 8816 memcpy(bp->dev->dev_addr, bp->pf.mac_addr, ETH_ALEN); 8817 } else { 8818 #ifdef CONFIG_BNXT_SRIOV 8819 struct bnxt_vf_info *vf = &bp->vf; 8820 bool strict_approval = true; 8821 8822 if (is_valid_ether_addr(vf->mac_addr)) { 8823 /* overwrite netdev dev_addr with admin VF MAC */ 8824 memcpy(bp->dev->dev_addr, vf->mac_addr, ETH_ALEN); 8825 /* Older PF driver or firmware may not approve this 8826 * correctly. 8827 */ 8828 strict_approval = false; 8829 } else { 8830 eth_hw_addr_random(bp->dev); 8831 } 8832 rc = bnxt_approve_mac(bp, bp->dev->dev_addr, strict_approval); 8833 #endif 8834 } 8835 return rc; 8836 } 8837 8838 static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 8839 { 8840 static int version_printed; 8841 struct net_device *dev; 8842 struct bnxt *bp; 8843 int rc, max_irqs; 8844 8845 if (pci_is_bridge(pdev)) 8846 return -ENODEV; 8847 8848 if (version_printed++ == 0) 8849 pr_info("%s", version); 8850 8851 max_irqs = bnxt_get_max_irq(pdev); 8852 dev = alloc_etherdev_mq(sizeof(*bp), max_irqs); 8853 if (!dev) 8854 return -ENOMEM; 8855 8856 bp = netdev_priv(dev); 8857 8858 if (bnxt_vf_pciid(ent->driver_data)) 8859 bp->flags |= BNXT_FLAG_VF; 8860 8861 if (pdev->msix_cap) 8862 bp->flags |= BNXT_FLAG_MSIX_CAP; 8863 8864 rc = bnxt_init_board(pdev, dev); 8865 if (rc < 0) 8866 goto init_err_free; 8867 8868 dev->netdev_ops = &bnxt_netdev_ops; 8869 dev->watchdog_timeo = BNXT_TX_TIMEOUT; 8870 dev->ethtool_ops = &bnxt_ethtool_ops; 8871 SWITCHDEV_SET_OPS(dev, &bnxt_switchdev_ops); 8872 pci_set_drvdata(pdev, dev); 8873 8874 rc = bnxt_alloc_hwrm_resources(bp); 8875 if (rc) 8876 goto init_err_pci_clean; 8877 8878 mutex_init(&bp->hwrm_cmd_lock); 8879 rc = bnxt_hwrm_ver_get(bp); 8880 if (rc) 8881 goto init_err_pci_clean; 8882 8883 if (bp->fw_cap & BNXT_FW_CAP_SHORT_CMD) { 8884 rc = bnxt_alloc_hwrm_short_cmd_req(bp); 8885 if (rc) 8886 goto init_err_pci_clean; 8887 } 8888 8889 rc = bnxt_hwrm_func_reset(bp); 8890 if (rc) 8891 goto init_err_pci_clean; 8892 8893 bnxt_hwrm_fw_set_time(bp); 8894 8895 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG | 8896 NETIF_F_TSO | NETIF_F_TSO6 | 8897 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE | 8898 NETIF_F_GSO_IPXIP4 | 8899 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM | 8900 NETIF_F_GSO_PARTIAL | NETIF_F_RXHASH | 8901 NETIF_F_RXCSUM | NETIF_F_GRO; 8902 8903 if (!BNXT_CHIP_TYPE_NITRO_A0(bp)) 8904 dev->hw_features |= NETIF_F_LRO; 8905 8906 dev->hw_enc_features = 8907 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG | 8908 NETIF_F_TSO | NETIF_F_TSO6 | 8909 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE | 8910 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM | 8911 NETIF_F_GSO_IPXIP4 | NETIF_F_GSO_PARTIAL; 8912 dev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM | 8913 NETIF_F_GSO_GRE_CSUM; 8914 dev->vlan_features = dev->hw_features | NETIF_F_HIGHDMA; 8915 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX | 8916 NETIF_F_HW_VLAN_STAG_RX | NETIF_F_HW_VLAN_STAG_TX; 8917 if (!BNXT_CHIP_TYPE_NITRO_A0(bp)) 8918 dev->hw_features |= NETIF_F_GRO_HW; 8919 dev->features |= dev->hw_features | NETIF_F_HIGHDMA; 8920 if (dev->features & NETIF_F_GRO_HW) 8921 dev->features &= ~NETIF_F_LRO; 8922 dev->priv_flags |= IFF_UNICAST_FLT; 8923 8924 #ifdef CONFIG_BNXT_SRIOV 8925 init_waitqueue_head(&bp->sriov_cfg_wait); 8926 mutex_init(&bp->sriov_lock); 8927 #endif 8928 bp->gro_func = bnxt_gro_func_5730x; 8929 if (BNXT_CHIP_P4_PLUS(bp)) 8930 bp->gro_func = bnxt_gro_func_5731x; 8931 else 8932 bp->flags |= BNXT_FLAG_DOUBLE_DB; 8933 8934 rc = bnxt_hwrm_func_drv_rgtr(bp); 8935 if (rc) 8936 goto init_err_pci_clean; 8937 8938 rc = bnxt_hwrm_func_rgtr_async_events(bp, NULL, 0); 8939 if (rc) 8940 goto init_err_pci_clean; 8941 8942 bp->ulp_probe = bnxt_ulp_probe; 8943 8944 /* Get the MAX capabilities for this function */ 8945 rc = bnxt_hwrm_func_qcaps(bp); 8946 if (rc) { 8947 netdev_err(bp->dev, "hwrm query capability failure rc: %x\n", 8948 rc); 8949 rc = -1; 8950 goto init_err_pci_clean; 8951 } 8952 rc = bnxt_init_mac_addr(bp); 8953 if (rc) { 8954 dev_err(&pdev->dev, "Unable to initialize mac address.\n"); 8955 rc = -EADDRNOTAVAIL; 8956 goto init_err_pci_clean; 8957 } 8958 rc = bnxt_hwrm_queue_qportcfg(bp); 8959 if (rc) { 8960 netdev_err(bp->dev, "hwrm query qportcfg failure rc: %x\n", 8961 rc); 8962 rc = -1; 8963 goto init_err_pci_clean; 8964 } 8965 8966 bnxt_hwrm_func_qcfg(bp); 8967 bnxt_hwrm_port_led_qcaps(bp); 8968 bnxt_ethtool_init(bp); 8969 bnxt_dcb_init(bp); 8970 8971 /* MTU range: 60 - FW defined max */ 8972 dev->min_mtu = ETH_ZLEN; 8973 dev->max_mtu = bp->max_mtu; 8974 8975 rc = bnxt_probe_phy(bp); 8976 if (rc) 8977 goto init_err_pci_clean; 8978 8979 bnxt_set_rx_skb_mode(bp, false); 8980 bnxt_set_tpa_flags(bp); 8981 bnxt_set_ring_params(bp); 8982 bnxt_set_max_func_irqs(bp, max_irqs); 8983 rc = bnxt_set_dflt_rings(bp, true); 8984 if (rc) { 8985 netdev_err(bp->dev, "Not enough rings available.\n"); 8986 rc = -ENOMEM; 8987 goto init_err_pci_clean; 8988 } 8989 8990 /* Default RSS hash cfg. */ 8991 bp->rss_hash_cfg = VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 | 8992 VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 | 8993 VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 | 8994 VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6; 8995 if (BNXT_CHIP_P4_PLUS(bp) && bp->hwrm_spec_code >= 0x10501) { 8996 bp->flags |= BNXT_FLAG_UDP_RSS_CAP; 8997 bp->rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 | 8998 VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6; 8999 } 9000 9001 bnxt_hwrm_vnic_qcaps(bp); 9002 if (bnxt_rfs_supported(bp)) { 9003 dev->hw_features |= NETIF_F_NTUPLE; 9004 if (bnxt_rfs_capable(bp)) { 9005 bp->flags |= BNXT_FLAG_RFS; 9006 dev->features |= NETIF_F_NTUPLE; 9007 } 9008 } 9009 9010 if (dev->hw_features & NETIF_F_HW_VLAN_CTAG_RX) 9011 bp->flags |= BNXT_FLAG_STRIP_VLAN; 9012 9013 rc = bnxt_init_int_mode(bp); 9014 if (rc) 9015 goto init_err_pci_clean; 9016 9017 /* No TC has been set yet and rings may have been trimmed due to 9018 * limited MSIX, so we re-initialize the TX rings per TC. 9019 */ 9020 bp->tx_nr_rings_per_tc = bp->tx_nr_rings; 9021 9022 bnxt_get_wol_settings(bp); 9023 if (bp->flags & BNXT_FLAG_WOL_CAP) 9024 device_set_wakeup_enable(&pdev->dev, bp->wol); 9025 else 9026 device_set_wakeup_capable(&pdev->dev, false); 9027 9028 bnxt_hwrm_set_cache_line_size(bp, cache_line_size()); 9029 9030 if (BNXT_PF(bp)) { 9031 if (!bnxt_pf_wq) { 9032 bnxt_pf_wq = 9033 create_singlethread_workqueue("bnxt_pf_wq"); 9034 if (!bnxt_pf_wq) { 9035 dev_err(&pdev->dev, "Unable to create workqueue.\n"); 9036 goto init_err_pci_clean; 9037 } 9038 } 9039 bnxt_init_tc(bp); 9040 } 9041 9042 rc = register_netdev(dev); 9043 if (rc) 9044 goto init_err_cleanup_tc; 9045 9046 if (BNXT_PF(bp)) 9047 bnxt_dl_register(bp); 9048 9049 netdev_info(dev, "%s found at mem %lx, node addr %pM\n", 9050 board_info[ent->driver_data].name, 9051 (long)pci_resource_start(pdev, 0), dev->dev_addr); 9052 pcie_print_link_status(pdev); 9053 9054 return 0; 9055 9056 init_err_cleanup_tc: 9057 bnxt_shutdown_tc(bp); 9058 bnxt_clear_int_mode(bp); 9059 9060 init_err_pci_clean: 9061 bnxt_free_hwrm_resources(bp); 9062 bnxt_cleanup_pci(bp); 9063 9064 init_err_free: 9065 free_netdev(dev); 9066 return rc; 9067 } 9068 9069 static void bnxt_shutdown(struct pci_dev *pdev) 9070 { 9071 struct net_device *dev = pci_get_drvdata(pdev); 9072 struct bnxt *bp; 9073 9074 if (!dev) 9075 return; 9076 9077 rtnl_lock(); 9078 bp = netdev_priv(dev); 9079 if (!bp) 9080 goto shutdown_exit; 9081 9082 if (netif_running(dev)) 9083 dev_close(dev); 9084 9085 bnxt_ulp_shutdown(bp); 9086 9087 if (system_state == SYSTEM_POWER_OFF) { 9088 bnxt_clear_int_mode(bp); 9089 pci_wake_from_d3(pdev, bp->wol); 9090 pci_set_power_state(pdev, PCI_D3hot); 9091 } 9092 9093 shutdown_exit: 9094 rtnl_unlock(); 9095 } 9096 9097 #ifdef CONFIG_PM_SLEEP 9098 static int bnxt_suspend(struct device *device) 9099 { 9100 struct pci_dev *pdev = to_pci_dev(device); 9101 struct net_device *dev = pci_get_drvdata(pdev); 9102 struct bnxt *bp = netdev_priv(dev); 9103 int rc = 0; 9104 9105 rtnl_lock(); 9106 if (netif_running(dev)) { 9107 netif_device_detach(dev); 9108 rc = bnxt_close(dev); 9109 } 9110 bnxt_hwrm_func_drv_unrgtr(bp); 9111 rtnl_unlock(); 9112 return rc; 9113 } 9114 9115 static int bnxt_resume(struct device *device) 9116 { 9117 struct pci_dev *pdev = to_pci_dev(device); 9118 struct net_device *dev = pci_get_drvdata(pdev); 9119 struct bnxt *bp = netdev_priv(dev); 9120 int rc = 0; 9121 9122 rtnl_lock(); 9123 if (bnxt_hwrm_ver_get(bp) || bnxt_hwrm_func_drv_rgtr(bp)) { 9124 rc = -ENODEV; 9125 goto resume_exit; 9126 } 9127 rc = bnxt_hwrm_func_reset(bp); 9128 if (rc) { 9129 rc = -EBUSY; 9130 goto resume_exit; 9131 } 9132 bnxt_get_wol_settings(bp); 9133 if (netif_running(dev)) { 9134 rc = bnxt_open(dev); 9135 if (!rc) 9136 netif_device_attach(dev); 9137 } 9138 9139 resume_exit: 9140 rtnl_unlock(); 9141 return rc; 9142 } 9143 9144 static SIMPLE_DEV_PM_OPS(bnxt_pm_ops, bnxt_suspend, bnxt_resume); 9145 #define BNXT_PM_OPS (&bnxt_pm_ops) 9146 9147 #else 9148 9149 #define BNXT_PM_OPS NULL 9150 9151 #endif /* CONFIG_PM_SLEEP */ 9152 9153 /** 9154 * bnxt_io_error_detected - called when PCI error is detected 9155 * @pdev: Pointer to PCI device 9156 * @state: The current pci connection state 9157 * 9158 * This function is called after a PCI bus error affecting 9159 * this device has been detected. 9160 */ 9161 static pci_ers_result_t bnxt_io_error_detected(struct pci_dev *pdev, 9162 pci_channel_state_t state) 9163 { 9164 struct net_device *netdev = pci_get_drvdata(pdev); 9165 struct bnxt *bp = netdev_priv(netdev); 9166 9167 netdev_info(netdev, "PCI I/O error detected\n"); 9168 9169 rtnl_lock(); 9170 netif_device_detach(netdev); 9171 9172 bnxt_ulp_stop(bp); 9173 9174 if (state == pci_channel_io_perm_failure) { 9175 rtnl_unlock(); 9176 return PCI_ERS_RESULT_DISCONNECT; 9177 } 9178 9179 if (netif_running(netdev)) 9180 bnxt_close(netdev); 9181 9182 pci_disable_device(pdev); 9183 rtnl_unlock(); 9184 9185 /* Request a slot slot reset. */ 9186 return PCI_ERS_RESULT_NEED_RESET; 9187 } 9188 9189 /** 9190 * bnxt_io_slot_reset - called after the pci bus has been reset. 9191 * @pdev: Pointer to PCI device 9192 * 9193 * Restart the card from scratch, as if from a cold-boot. 9194 * At this point, the card has exprienced a hard reset, 9195 * followed by fixups by BIOS, and has its config space 9196 * set up identically to what it was at cold boot. 9197 */ 9198 static pci_ers_result_t bnxt_io_slot_reset(struct pci_dev *pdev) 9199 { 9200 struct net_device *netdev = pci_get_drvdata(pdev); 9201 struct bnxt *bp = netdev_priv(netdev); 9202 int err = 0; 9203 pci_ers_result_t result = PCI_ERS_RESULT_DISCONNECT; 9204 9205 netdev_info(bp->dev, "PCI Slot Reset\n"); 9206 9207 rtnl_lock(); 9208 9209 if (pci_enable_device(pdev)) { 9210 dev_err(&pdev->dev, 9211 "Cannot re-enable PCI device after reset.\n"); 9212 } else { 9213 pci_set_master(pdev); 9214 9215 err = bnxt_hwrm_func_reset(bp); 9216 if (!err && netif_running(netdev)) 9217 err = bnxt_open(netdev); 9218 9219 if (!err) { 9220 result = PCI_ERS_RESULT_RECOVERED; 9221 bnxt_ulp_start(bp); 9222 } 9223 } 9224 9225 if (result != PCI_ERS_RESULT_RECOVERED && netif_running(netdev)) 9226 dev_close(netdev); 9227 9228 rtnl_unlock(); 9229 9230 err = pci_cleanup_aer_uncorrect_error_status(pdev); 9231 if (err) { 9232 dev_err(&pdev->dev, 9233 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", 9234 err); /* non-fatal, continue */ 9235 } 9236 9237 return PCI_ERS_RESULT_RECOVERED; 9238 } 9239 9240 /** 9241 * bnxt_io_resume - called when traffic can start flowing again. 9242 * @pdev: Pointer to PCI device 9243 * 9244 * This callback is called when the error recovery driver tells 9245 * us that its OK to resume normal operation. 9246 */ 9247 static void bnxt_io_resume(struct pci_dev *pdev) 9248 { 9249 struct net_device *netdev = pci_get_drvdata(pdev); 9250 9251 rtnl_lock(); 9252 9253 netif_device_attach(netdev); 9254 9255 rtnl_unlock(); 9256 } 9257 9258 static const struct pci_error_handlers bnxt_err_handler = { 9259 .error_detected = bnxt_io_error_detected, 9260 .slot_reset = bnxt_io_slot_reset, 9261 .resume = bnxt_io_resume 9262 }; 9263 9264 static struct pci_driver bnxt_pci_driver = { 9265 .name = DRV_MODULE_NAME, 9266 .id_table = bnxt_pci_tbl, 9267 .probe = bnxt_init_one, 9268 .remove = bnxt_remove_one, 9269 .shutdown = bnxt_shutdown, 9270 .driver.pm = BNXT_PM_OPS, 9271 .err_handler = &bnxt_err_handler, 9272 #if defined(CONFIG_BNXT_SRIOV) 9273 .sriov_configure = bnxt_sriov_configure, 9274 #endif 9275 }; 9276 9277 static int __init bnxt_init(void) 9278 { 9279 bnxt_debug_init(); 9280 return pci_register_driver(&bnxt_pci_driver); 9281 } 9282 9283 static void __exit bnxt_exit(void) 9284 { 9285 pci_unregister_driver(&bnxt_pci_driver); 9286 if (bnxt_pf_wq) 9287 destroy_workqueue(bnxt_pf_wq); 9288 bnxt_debug_exit(); 9289 } 9290 9291 module_init(bnxt_init); 9292 module_exit(bnxt_exit); 9293