1 /* Broadcom NetXtreme-C/E network driver. 2 * 3 * Copyright (c) 2014-2016 Broadcom Corporation 4 * Copyright (c) 2016-2019 Broadcom Limited 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation. 9 */ 10 11 #include <linux/module.h> 12 13 #include <linux/stringify.h> 14 #include <linux/kernel.h> 15 #include <linux/timer.h> 16 #include <linux/errno.h> 17 #include <linux/ioport.h> 18 #include <linux/slab.h> 19 #include <linux/vmalloc.h> 20 #include <linux/interrupt.h> 21 #include <linux/pci.h> 22 #include <linux/netdevice.h> 23 #include <linux/etherdevice.h> 24 #include <linux/skbuff.h> 25 #include <linux/dma-mapping.h> 26 #include <linux/bitops.h> 27 #include <linux/io.h> 28 #include <linux/irq.h> 29 #include <linux/delay.h> 30 #include <asm/byteorder.h> 31 #include <asm/page.h> 32 #include <linux/time.h> 33 #include <linux/mii.h> 34 #include <linux/mdio.h> 35 #include <linux/if.h> 36 #include <linux/if_vlan.h> 37 #include <linux/if_bridge.h> 38 #include <linux/rtc.h> 39 #include <linux/bpf.h> 40 #include <net/ip.h> 41 #include <net/tcp.h> 42 #include <net/udp.h> 43 #include <net/checksum.h> 44 #include <net/ip6_checksum.h> 45 #include <net/udp_tunnel.h> 46 #include <linux/workqueue.h> 47 #include <linux/prefetch.h> 48 #include <linux/cache.h> 49 #include <linux/log2.h> 50 #include <linux/aer.h> 51 #include <linux/bitmap.h> 52 #include <linux/cpu_rmap.h> 53 #include <linux/cpumask.h> 54 #include <net/pkt_cls.h> 55 #include <linux/hwmon.h> 56 #include <linux/hwmon-sysfs.h> 57 #include <net/page_pool.h> 58 59 #include "bnxt_hsi.h" 60 #include "bnxt.h" 61 #include "bnxt_ulp.h" 62 #include "bnxt_sriov.h" 63 #include "bnxt_ethtool.h" 64 #include "bnxt_dcb.h" 65 #include "bnxt_xdp.h" 66 #include "bnxt_vfr.h" 67 #include "bnxt_tc.h" 68 #include "bnxt_devlink.h" 69 #include "bnxt_debugfs.h" 70 71 #define BNXT_TX_TIMEOUT (5 * HZ) 72 73 MODULE_LICENSE("GPL"); 74 MODULE_DESCRIPTION("Broadcom BCM573xx network driver"); 75 76 #define BNXT_RX_OFFSET (NET_SKB_PAD + NET_IP_ALIGN) 77 #define BNXT_RX_DMA_OFFSET NET_SKB_PAD 78 #define BNXT_RX_COPY_THRESH 256 79 80 #define BNXT_TX_PUSH_THRESH 164 81 82 enum board_idx { 83 BCM57301, 84 BCM57302, 85 BCM57304, 86 BCM57417_NPAR, 87 BCM58700, 88 BCM57311, 89 BCM57312, 90 BCM57402, 91 BCM57404, 92 BCM57406, 93 BCM57402_NPAR, 94 BCM57407, 95 BCM57412, 96 BCM57414, 97 BCM57416, 98 BCM57417, 99 BCM57412_NPAR, 100 BCM57314, 101 BCM57417_SFP, 102 BCM57416_SFP, 103 BCM57404_NPAR, 104 BCM57406_NPAR, 105 BCM57407_SFP, 106 BCM57407_NPAR, 107 BCM57414_NPAR, 108 BCM57416_NPAR, 109 BCM57452, 110 BCM57454, 111 BCM5745x_NPAR, 112 BCM57508, 113 BCM57504, 114 BCM57502, 115 BCM57508_NPAR, 116 BCM57504_NPAR, 117 BCM57502_NPAR, 118 BCM58802, 119 BCM58804, 120 BCM58808, 121 NETXTREME_E_VF, 122 NETXTREME_C_VF, 123 NETXTREME_S_VF, 124 NETXTREME_E_P5_VF, 125 }; 126 127 /* indexed by enum above */ 128 static const struct { 129 char *name; 130 } board_info[] = { 131 [BCM57301] = { "Broadcom BCM57301 NetXtreme-C 10Gb Ethernet" }, 132 [BCM57302] = { "Broadcom BCM57302 NetXtreme-C 10Gb/25Gb Ethernet" }, 133 [BCM57304] = { "Broadcom BCM57304 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" }, 134 [BCM57417_NPAR] = { "Broadcom BCM57417 NetXtreme-E Ethernet Partition" }, 135 [BCM58700] = { "Broadcom BCM58700 Nitro 1Gb/2.5Gb/10Gb Ethernet" }, 136 [BCM57311] = { "Broadcom BCM57311 NetXtreme-C 10Gb Ethernet" }, 137 [BCM57312] = { "Broadcom BCM57312 NetXtreme-C 10Gb/25Gb Ethernet" }, 138 [BCM57402] = { "Broadcom BCM57402 NetXtreme-E 10Gb Ethernet" }, 139 [BCM57404] = { "Broadcom BCM57404 NetXtreme-E 10Gb/25Gb Ethernet" }, 140 [BCM57406] = { "Broadcom BCM57406 NetXtreme-E 10GBase-T Ethernet" }, 141 [BCM57402_NPAR] = { "Broadcom BCM57402 NetXtreme-E Ethernet Partition" }, 142 [BCM57407] = { "Broadcom BCM57407 NetXtreme-E 10GBase-T Ethernet" }, 143 [BCM57412] = { "Broadcom BCM57412 NetXtreme-E 10Gb Ethernet" }, 144 [BCM57414] = { "Broadcom BCM57414 NetXtreme-E 10Gb/25Gb Ethernet" }, 145 [BCM57416] = { "Broadcom BCM57416 NetXtreme-E 10GBase-T Ethernet" }, 146 [BCM57417] = { "Broadcom BCM57417 NetXtreme-E 10GBase-T Ethernet" }, 147 [BCM57412_NPAR] = { "Broadcom BCM57412 NetXtreme-E Ethernet Partition" }, 148 [BCM57314] = { "Broadcom BCM57314 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" }, 149 [BCM57417_SFP] = { "Broadcom BCM57417 NetXtreme-E 10Gb/25Gb Ethernet" }, 150 [BCM57416_SFP] = { "Broadcom BCM57416 NetXtreme-E 10Gb Ethernet" }, 151 [BCM57404_NPAR] = { "Broadcom BCM57404 NetXtreme-E Ethernet Partition" }, 152 [BCM57406_NPAR] = { "Broadcom BCM57406 NetXtreme-E Ethernet Partition" }, 153 [BCM57407_SFP] = { "Broadcom BCM57407 NetXtreme-E 25Gb Ethernet" }, 154 [BCM57407_NPAR] = { "Broadcom BCM57407 NetXtreme-E Ethernet Partition" }, 155 [BCM57414_NPAR] = { "Broadcom BCM57414 NetXtreme-E Ethernet Partition" }, 156 [BCM57416_NPAR] = { "Broadcom BCM57416 NetXtreme-E Ethernet Partition" }, 157 [BCM57452] = { "Broadcom BCM57452 NetXtreme-E 10Gb/25Gb/40Gb/50Gb Ethernet" }, 158 [BCM57454] = { "Broadcom BCM57454 NetXtreme-E 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" }, 159 [BCM5745x_NPAR] = { "Broadcom BCM5745x NetXtreme-E Ethernet Partition" }, 160 [BCM57508] = { "Broadcom BCM57508 NetXtreme-E 10Gb/25Gb/50Gb/100Gb/200Gb Ethernet" }, 161 [BCM57504] = { "Broadcom BCM57504 NetXtreme-E 10Gb/25Gb/50Gb/100Gb/200Gb Ethernet" }, 162 [BCM57502] = { "Broadcom BCM57502 NetXtreme-E 10Gb/25Gb/50Gb Ethernet" }, 163 [BCM57508_NPAR] = { "Broadcom BCM57508 NetXtreme-E Ethernet Partition" }, 164 [BCM57504_NPAR] = { "Broadcom BCM57504 NetXtreme-E Ethernet Partition" }, 165 [BCM57502_NPAR] = { "Broadcom BCM57502 NetXtreme-E Ethernet Partition" }, 166 [BCM58802] = { "Broadcom BCM58802 NetXtreme-S 10Gb/25Gb/40Gb/50Gb Ethernet" }, 167 [BCM58804] = { "Broadcom BCM58804 NetXtreme-S 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" }, 168 [BCM58808] = { "Broadcom BCM58808 NetXtreme-S 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" }, 169 [NETXTREME_E_VF] = { "Broadcom NetXtreme-E Ethernet Virtual Function" }, 170 [NETXTREME_C_VF] = { "Broadcom NetXtreme-C Ethernet Virtual Function" }, 171 [NETXTREME_S_VF] = { "Broadcom NetXtreme-S Ethernet Virtual Function" }, 172 [NETXTREME_E_P5_VF] = { "Broadcom BCM5750X NetXtreme-E Ethernet Virtual Function" }, 173 }; 174 175 static const struct pci_device_id bnxt_pci_tbl[] = { 176 { PCI_VDEVICE(BROADCOM, 0x1604), .driver_data = BCM5745x_NPAR }, 177 { PCI_VDEVICE(BROADCOM, 0x1605), .driver_data = BCM5745x_NPAR }, 178 { PCI_VDEVICE(BROADCOM, 0x1614), .driver_data = BCM57454 }, 179 { PCI_VDEVICE(BROADCOM, 0x16c0), .driver_data = BCM57417_NPAR }, 180 { PCI_VDEVICE(BROADCOM, 0x16c8), .driver_data = BCM57301 }, 181 { PCI_VDEVICE(BROADCOM, 0x16c9), .driver_data = BCM57302 }, 182 { PCI_VDEVICE(BROADCOM, 0x16ca), .driver_data = BCM57304 }, 183 { PCI_VDEVICE(BROADCOM, 0x16cc), .driver_data = BCM57417_NPAR }, 184 { PCI_VDEVICE(BROADCOM, 0x16cd), .driver_data = BCM58700 }, 185 { PCI_VDEVICE(BROADCOM, 0x16ce), .driver_data = BCM57311 }, 186 { PCI_VDEVICE(BROADCOM, 0x16cf), .driver_data = BCM57312 }, 187 { PCI_VDEVICE(BROADCOM, 0x16d0), .driver_data = BCM57402 }, 188 { PCI_VDEVICE(BROADCOM, 0x16d1), .driver_data = BCM57404 }, 189 { PCI_VDEVICE(BROADCOM, 0x16d2), .driver_data = BCM57406 }, 190 { PCI_VDEVICE(BROADCOM, 0x16d4), .driver_data = BCM57402_NPAR }, 191 { PCI_VDEVICE(BROADCOM, 0x16d5), .driver_data = BCM57407 }, 192 { PCI_VDEVICE(BROADCOM, 0x16d6), .driver_data = BCM57412 }, 193 { PCI_VDEVICE(BROADCOM, 0x16d7), .driver_data = BCM57414 }, 194 { PCI_VDEVICE(BROADCOM, 0x16d8), .driver_data = BCM57416 }, 195 { PCI_VDEVICE(BROADCOM, 0x16d9), .driver_data = BCM57417 }, 196 { PCI_VDEVICE(BROADCOM, 0x16de), .driver_data = BCM57412_NPAR }, 197 { PCI_VDEVICE(BROADCOM, 0x16df), .driver_data = BCM57314 }, 198 { PCI_VDEVICE(BROADCOM, 0x16e2), .driver_data = BCM57417_SFP }, 199 { PCI_VDEVICE(BROADCOM, 0x16e3), .driver_data = BCM57416_SFP }, 200 { PCI_VDEVICE(BROADCOM, 0x16e7), .driver_data = BCM57404_NPAR }, 201 { PCI_VDEVICE(BROADCOM, 0x16e8), .driver_data = BCM57406_NPAR }, 202 { PCI_VDEVICE(BROADCOM, 0x16e9), .driver_data = BCM57407_SFP }, 203 { PCI_VDEVICE(BROADCOM, 0x16ea), .driver_data = BCM57407_NPAR }, 204 { PCI_VDEVICE(BROADCOM, 0x16eb), .driver_data = BCM57412_NPAR }, 205 { PCI_VDEVICE(BROADCOM, 0x16ec), .driver_data = BCM57414_NPAR }, 206 { PCI_VDEVICE(BROADCOM, 0x16ed), .driver_data = BCM57414_NPAR }, 207 { PCI_VDEVICE(BROADCOM, 0x16ee), .driver_data = BCM57416_NPAR }, 208 { PCI_VDEVICE(BROADCOM, 0x16ef), .driver_data = BCM57416_NPAR }, 209 { PCI_VDEVICE(BROADCOM, 0x16f0), .driver_data = BCM58808 }, 210 { PCI_VDEVICE(BROADCOM, 0x16f1), .driver_data = BCM57452 }, 211 { PCI_VDEVICE(BROADCOM, 0x1750), .driver_data = BCM57508 }, 212 { PCI_VDEVICE(BROADCOM, 0x1751), .driver_data = BCM57504 }, 213 { PCI_VDEVICE(BROADCOM, 0x1752), .driver_data = BCM57502 }, 214 { PCI_VDEVICE(BROADCOM, 0x1800), .driver_data = BCM57508_NPAR }, 215 { PCI_VDEVICE(BROADCOM, 0x1801), .driver_data = BCM57504_NPAR }, 216 { PCI_VDEVICE(BROADCOM, 0x1802), .driver_data = BCM57502_NPAR }, 217 { PCI_VDEVICE(BROADCOM, 0x1803), .driver_data = BCM57508_NPAR }, 218 { PCI_VDEVICE(BROADCOM, 0x1804), .driver_data = BCM57504_NPAR }, 219 { PCI_VDEVICE(BROADCOM, 0x1805), .driver_data = BCM57502_NPAR }, 220 { PCI_VDEVICE(BROADCOM, 0xd802), .driver_data = BCM58802 }, 221 { PCI_VDEVICE(BROADCOM, 0xd804), .driver_data = BCM58804 }, 222 #ifdef CONFIG_BNXT_SRIOV 223 { PCI_VDEVICE(BROADCOM, 0x1606), .driver_data = NETXTREME_E_VF }, 224 { PCI_VDEVICE(BROADCOM, 0x1609), .driver_data = NETXTREME_E_VF }, 225 { PCI_VDEVICE(BROADCOM, 0x16c1), .driver_data = NETXTREME_E_VF }, 226 { PCI_VDEVICE(BROADCOM, 0x16cb), .driver_data = NETXTREME_C_VF }, 227 { PCI_VDEVICE(BROADCOM, 0x16d3), .driver_data = NETXTREME_E_VF }, 228 { PCI_VDEVICE(BROADCOM, 0x16dc), .driver_data = NETXTREME_E_VF }, 229 { PCI_VDEVICE(BROADCOM, 0x16e1), .driver_data = NETXTREME_C_VF }, 230 { PCI_VDEVICE(BROADCOM, 0x16e5), .driver_data = NETXTREME_C_VF }, 231 { PCI_VDEVICE(BROADCOM, 0x1806), .driver_data = NETXTREME_E_P5_VF }, 232 { PCI_VDEVICE(BROADCOM, 0x1807), .driver_data = NETXTREME_E_P5_VF }, 233 { PCI_VDEVICE(BROADCOM, 0xd800), .driver_data = NETXTREME_S_VF }, 234 #endif 235 { 0 } 236 }; 237 238 MODULE_DEVICE_TABLE(pci, bnxt_pci_tbl); 239 240 static const u16 bnxt_vf_req_snif[] = { 241 HWRM_FUNC_CFG, 242 HWRM_FUNC_VF_CFG, 243 HWRM_PORT_PHY_QCFG, 244 HWRM_CFA_L2_FILTER_ALLOC, 245 }; 246 247 static const u16 bnxt_async_events_arr[] = { 248 ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE, 249 ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE, 250 ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD, 251 ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED, 252 ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE, 253 ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE, 254 ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE, 255 ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY, 256 ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY, 257 }; 258 259 static struct workqueue_struct *bnxt_pf_wq; 260 261 static bool bnxt_vf_pciid(enum board_idx idx) 262 { 263 return (idx == NETXTREME_C_VF || idx == NETXTREME_E_VF || 264 idx == NETXTREME_S_VF || idx == NETXTREME_E_P5_VF); 265 } 266 267 #define DB_CP_REARM_FLAGS (DB_KEY_CP | DB_IDX_VALID) 268 #define DB_CP_FLAGS (DB_KEY_CP | DB_IDX_VALID | DB_IRQ_DIS) 269 #define DB_CP_IRQ_DIS_FLAGS (DB_KEY_CP | DB_IRQ_DIS) 270 271 #define BNXT_CP_DB_IRQ_DIS(db) \ 272 writel(DB_CP_IRQ_DIS_FLAGS, db) 273 274 #define BNXT_DB_CQ(db, idx) \ 275 writel(DB_CP_FLAGS | RING_CMP(idx), (db)->doorbell) 276 277 #define BNXT_DB_NQ_P5(db, idx) \ 278 writeq((db)->db_key64 | DBR_TYPE_NQ | RING_CMP(idx), (db)->doorbell) 279 280 #define BNXT_DB_CQ_ARM(db, idx) \ 281 writel(DB_CP_REARM_FLAGS | RING_CMP(idx), (db)->doorbell) 282 283 #define BNXT_DB_NQ_ARM_P5(db, idx) \ 284 writeq((db)->db_key64 | DBR_TYPE_NQ_ARM | RING_CMP(idx), (db)->doorbell) 285 286 static void bnxt_db_nq(struct bnxt *bp, struct bnxt_db_info *db, u32 idx) 287 { 288 if (bp->flags & BNXT_FLAG_CHIP_P5) 289 BNXT_DB_NQ_P5(db, idx); 290 else 291 BNXT_DB_CQ(db, idx); 292 } 293 294 static void bnxt_db_nq_arm(struct bnxt *bp, struct bnxt_db_info *db, u32 idx) 295 { 296 if (bp->flags & BNXT_FLAG_CHIP_P5) 297 BNXT_DB_NQ_ARM_P5(db, idx); 298 else 299 BNXT_DB_CQ_ARM(db, idx); 300 } 301 302 static void bnxt_db_cq(struct bnxt *bp, struct bnxt_db_info *db, u32 idx) 303 { 304 if (bp->flags & BNXT_FLAG_CHIP_P5) 305 writeq(db->db_key64 | DBR_TYPE_CQ_ARMALL | RING_CMP(idx), 306 db->doorbell); 307 else 308 BNXT_DB_CQ(db, idx); 309 } 310 311 const u16 bnxt_lhint_arr[] = { 312 TX_BD_FLAGS_LHINT_512_AND_SMALLER, 313 TX_BD_FLAGS_LHINT_512_TO_1023, 314 TX_BD_FLAGS_LHINT_1024_TO_2047, 315 TX_BD_FLAGS_LHINT_1024_TO_2047, 316 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 317 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 318 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 319 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 320 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 321 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 322 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 323 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 324 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 325 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 326 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 327 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 328 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 329 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 330 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 331 }; 332 333 static u16 bnxt_xmit_get_cfa_action(struct sk_buff *skb) 334 { 335 struct metadata_dst *md_dst = skb_metadata_dst(skb); 336 337 if (!md_dst || md_dst->type != METADATA_HW_PORT_MUX) 338 return 0; 339 340 return md_dst->u.port_info.port_id; 341 } 342 343 static netdev_tx_t bnxt_start_xmit(struct sk_buff *skb, struct net_device *dev) 344 { 345 struct bnxt *bp = netdev_priv(dev); 346 struct tx_bd *txbd; 347 struct tx_bd_ext *txbd1; 348 struct netdev_queue *txq; 349 int i; 350 dma_addr_t mapping; 351 unsigned int length, pad = 0; 352 u32 len, free_size, vlan_tag_flags, cfa_action, flags; 353 u16 prod, last_frag; 354 struct pci_dev *pdev = bp->pdev; 355 struct bnxt_tx_ring_info *txr; 356 struct bnxt_sw_tx_bd *tx_buf; 357 358 i = skb_get_queue_mapping(skb); 359 if (unlikely(i >= bp->tx_nr_rings)) { 360 dev_kfree_skb_any(skb); 361 return NETDEV_TX_OK; 362 } 363 364 txq = netdev_get_tx_queue(dev, i); 365 txr = &bp->tx_ring[bp->tx_ring_map[i]]; 366 prod = txr->tx_prod; 367 368 free_size = bnxt_tx_avail(bp, txr); 369 if (unlikely(free_size < skb_shinfo(skb)->nr_frags + 2)) { 370 netif_tx_stop_queue(txq); 371 return NETDEV_TX_BUSY; 372 } 373 374 length = skb->len; 375 len = skb_headlen(skb); 376 last_frag = skb_shinfo(skb)->nr_frags; 377 378 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)]; 379 380 txbd->tx_bd_opaque = prod; 381 382 tx_buf = &txr->tx_buf_ring[prod]; 383 tx_buf->skb = skb; 384 tx_buf->nr_frags = last_frag; 385 386 vlan_tag_flags = 0; 387 cfa_action = bnxt_xmit_get_cfa_action(skb); 388 if (skb_vlan_tag_present(skb)) { 389 vlan_tag_flags = TX_BD_CFA_META_KEY_VLAN | 390 skb_vlan_tag_get(skb); 391 /* Currently supports 8021Q, 8021AD vlan offloads 392 * QINQ1, QINQ2, QINQ3 vlan headers are deprecated 393 */ 394 if (skb->vlan_proto == htons(ETH_P_8021Q)) 395 vlan_tag_flags |= 1 << TX_BD_CFA_META_TPID_SHIFT; 396 } 397 398 if (free_size == bp->tx_ring_size && length <= bp->tx_push_thresh) { 399 struct tx_push_buffer *tx_push_buf = txr->tx_push; 400 struct tx_push_bd *tx_push = &tx_push_buf->push_bd; 401 struct tx_bd_ext *tx_push1 = &tx_push->txbd2; 402 void __iomem *db = txr->tx_db.doorbell; 403 void *pdata = tx_push_buf->data; 404 u64 *end; 405 int j, push_len; 406 407 /* Set COAL_NOW to be ready quickly for the next push */ 408 tx_push->tx_bd_len_flags_type = 409 cpu_to_le32((length << TX_BD_LEN_SHIFT) | 410 TX_BD_TYPE_LONG_TX_BD | 411 TX_BD_FLAGS_LHINT_512_AND_SMALLER | 412 TX_BD_FLAGS_COAL_NOW | 413 TX_BD_FLAGS_PACKET_END | 414 (2 << TX_BD_FLAGS_BD_CNT_SHIFT)); 415 416 if (skb->ip_summed == CHECKSUM_PARTIAL) 417 tx_push1->tx_bd_hsize_lflags = 418 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM); 419 else 420 tx_push1->tx_bd_hsize_lflags = 0; 421 422 tx_push1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags); 423 tx_push1->tx_bd_cfa_action = 424 cpu_to_le32(cfa_action << TX_BD_CFA_ACTION_SHIFT); 425 426 end = pdata + length; 427 end = PTR_ALIGN(end, 8) - 1; 428 *end = 0; 429 430 skb_copy_from_linear_data(skb, pdata, len); 431 pdata += len; 432 for (j = 0; j < last_frag; j++) { 433 skb_frag_t *frag = &skb_shinfo(skb)->frags[j]; 434 void *fptr; 435 436 fptr = skb_frag_address_safe(frag); 437 if (!fptr) 438 goto normal_tx; 439 440 memcpy(pdata, fptr, skb_frag_size(frag)); 441 pdata += skb_frag_size(frag); 442 } 443 444 txbd->tx_bd_len_flags_type = tx_push->tx_bd_len_flags_type; 445 txbd->tx_bd_haddr = txr->data_mapping; 446 prod = NEXT_TX(prod); 447 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)]; 448 memcpy(txbd, tx_push1, sizeof(*txbd)); 449 prod = NEXT_TX(prod); 450 tx_push->doorbell = 451 cpu_to_le32(DB_KEY_TX_PUSH | DB_LONG_TX_PUSH | prod); 452 txr->tx_prod = prod; 453 454 tx_buf->is_push = 1; 455 netdev_tx_sent_queue(txq, skb->len); 456 wmb(); /* Sync is_push and byte queue before pushing data */ 457 458 push_len = (length + sizeof(*tx_push) + 7) / 8; 459 if (push_len > 16) { 460 __iowrite64_copy(db, tx_push_buf, 16); 461 __iowrite32_copy(db + 4, tx_push_buf + 1, 462 (push_len - 16) << 1); 463 } else { 464 __iowrite64_copy(db, tx_push_buf, push_len); 465 } 466 467 goto tx_done; 468 } 469 470 normal_tx: 471 if (length < BNXT_MIN_PKT_SIZE) { 472 pad = BNXT_MIN_PKT_SIZE - length; 473 if (skb_pad(skb, pad)) { 474 /* SKB already freed. */ 475 tx_buf->skb = NULL; 476 return NETDEV_TX_OK; 477 } 478 length = BNXT_MIN_PKT_SIZE; 479 } 480 481 mapping = dma_map_single(&pdev->dev, skb->data, len, DMA_TO_DEVICE); 482 483 if (unlikely(dma_mapping_error(&pdev->dev, mapping))) { 484 dev_kfree_skb_any(skb); 485 tx_buf->skb = NULL; 486 return NETDEV_TX_OK; 487 } 488 489 dma_unmap_addr_set(tx_buf, mapping, mapping); 490 flags = (len << TX_BD_LEN_SHIFT) | TX_BD_TYPE_LONG_TX_BD | 491 ((last_frag + 2) << TX_BD_FLAGS_BD_CNT_SHIFT); 492 493 txbd->tx_bd_haddr = cpu_to_le64(mapping); 494 495 prod = NEXT_TX(prod); 496 txbd1 = (struct tx_bd_ext *) 497 &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)]; 498 499 txbd1->tx_bd_hsize_lflags = 0; 500 if (skb_is_gso(skb)) { 501 u32 hdr_len; 502 503 if (skb->encapsulation) 504 hdr_len = skb_inner_network_offset(skb) + 505 skb_inner_network_header_len(skb) + 506 inner_tcp_hdrlen(skb); 507 else 508 hdr_len = skb_transport_offset(skb) + 509 tcp_hdrlen(skb); 510 511 txbd1->tx_bd_hsize_lflags = cpu_to_le32(TX_BD_FLAGS_LSO | 512 TX_BD_FLAGS_T_IPID | 513 (hdr_len << (TX_BD_HSIZE_SHIFT - 1))); 514 length = skb_shinfo(skb)->gso_size; 515 txbd1->tx_bd_mss = cpu_to_le32(length); 516 length += hdr_len; 517 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 518 txbd1->tx_bd_hsize_lflags = 519 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM); 520 txbd1->tx_bd_mss = 0; 521 } 522 523 length >>= 9; 524 if (unlikely(length >= ARRAY_SIZE(bnxt_lhint_arr))) { 525 dev_warn_ratelimited(&pdev->dev, "Dropped oversize %d bytes TX packet.\n", 526 skb->len); 527 i = 0; 528 goto tx_dma_error; 529 } 530 flags |= bnxt_lhint_arr[length]; 531 txbd->tx_bd_len_flags_type = cpu_to_le32(flags); 532 533 txbd1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags); 534 txbd1->tx_bd_cfa_action = 535 cpu_to_le32(cfa_action << TX_BD_CFA_ACTION_SHIFT); 536 for (i = 0; i < last_frag; i++) { 537 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 538 539 prod = NEXT_TX(prod); 540 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)]; 541 542 len = skb_frag_size(frag); 543 mapping = skb_frag_dma_map(&pdev->dev, frag, 0, len, 544 DMA_TO_DEVICE); 545 546 if (unlikely(dma_mapping_error(&pdev->dev, mapping))) 547 goto tx_dma_error; 548 549 tx_buf = &txr->tx_buf_ring[prod]; 550 dma_unmap_addr_set(tx_buf, mapping, mapping); 551 552 txbd->tx_bd_haddr = cpu_to_le64(mapping); 553 554 flags = len << TX_BD_LEN_SHIFT; 555 txbd->tx_bd_len_flags_type = cpu_to_le32(flags); 556 } 557 558 flags &= ~TX_BD_LEN; 559 txbd->tx_bd_len_flags_type = 560 cpu_to_le32(((len + pad) << TX_BD_LEN_SHIFT) | flags | 561 TX_BD_FLAGS_PACKET_END); 562 563 netdev_tx_sent_queue(txq, skb->len); 564 565 /* Sync BD data before updating doorbell */ 566 wmb(); 567 568 prod = NEXT_TX(prod); 569 txr->tx_prod = prod; 570 571 if (!netdev_xmit_more() || netif_xmit_stopped(txq)) 572 bnxt_db_write(bp, &txr->tx_db, prod); 573 574 tx_done: 575 576 if (unlikely(bnxt_tx_avail(bp, txr) <= MAX_SKB_FRAGS + 1)) { 577 if (netdev_xmit_more() && !tx_buf->is_push) 578 bnxt_db_write(bp, &txr->tx_db, prod); 579 580 netif_tx_stop_queue(txq); 581 582 /* netif_tx_stop_queue() must be done before checking 583 * tx index in bnxt_tx_avail() below, because in 584 * bnxt_tx_int(), we update tx index before checking for 585 * netif_tx_queue_stopped(). 586 */ 587 smp_mb(); 588 if (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh) 589 netif_tx_wake_queue(txq); 590 } 591 return NETDEV_TX_OK; 592 593 tx_dma_error: 594 last_frag = i; 595 596 /* start back at beginning and unmap skb */ 597 prod = txr->tx_prod; 598 tx_buf = &txr->tx_buf_ring[prod]; 599 tx_buf->skb = NULL; 600 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping), 601 skb_headlen(skb), PCI_DMA_TODEVICE); 602 prod = NEXT_TX(prod); 603 604 /* unmap remaining mapped pages */ 605 for (i = 0; i < last_frag; i++) { 606 prod = NEXT_TX(prod); 607 tx_buf = &txr->tx_buf_ring[prod]; 608 dma_unmap_page(&pdev->dev, dma_unmap_addr(tx_buf, mapping), 609 skb_frag_size(&skb_shinfo(skb)->frags[i]), 610 PCI_DMA_TODEVICE); 611 } 612 613 dev_kfree_skb_any(skb); 614 return NETDEV_TX_OK; 615 } 616 617 static void bnxt_tx_int(struct bnxt *bp, struct bnxt_napi *bnapi, int nr_pkts) 618 { 619 struct bnxt_tx_ring_info *txr = bnapi->tx_ring; 620 struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, txr->txq_index); 621 u16 cons = txr->tx_cons; 622 struct pci_dev *pdev = bp->pdev; 623 int i; 624 unsigned int tx_bytes = 0; 625 626 for (i = 0; i < nr_pkts; i++) { 627 struct bnxt_sw_tx_bd *tx_buf; 628 struct sk_buff *skb; 629 int j, last; 630 631 tx_buf = &txr->tx_buf_ring[cons]; 632 cons = NEXT_TX(cons); 633 skb = tx_buf->skb; 634 tx_buf->skb = NULL; 635 636 if (tx_buf->is_push) { 637 tx_buf->is_push = 0; 638 goto next_tx_int; 639 } 640 641 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping), 642 skb_headlen(skb), PCI_DMA_TODEVICE); 643 last = tx_buf->nr_frags; 644 645 for (j = 0; j < last; j++) { 646 cons = NEXT_TX(cons); 647 tx_buf = &txr->tx_buf_ring[cons]; 648 dma_unmap_page( 649 &pdev->dev, 650 dma_unmap_addr(tx_buf, mapping), 651 skb_frag_size(&skb_shinfo(skb)->frags[j]), 652 PCI_DMA_TODEVICE); 653 } 654 655 next_tx_int: 656 cons = NEXT_TX(cons); 657 658 tx_bytes += skb->len; 659 dev_kfree_skb_any(skb); 660 } 661 662 netdev_tx_completed_queue(txq, nr_pkts, tx_bytes); 663 txr->tx_cons = cons; 664 665 /* Need to make the tx_cons update visible to bnxt_start_xmit() 666 * before checking for netif_tx_queue_stopped(). Without the 667 * memory barrier, there is a small possibility that bnxt_start_xmit() 668 * will miss it and cause the queue to be stopped forever. 669 */ 670 smp_mb(); 671 672 if (unlikely(netif_tx_queue_stopped(txq)) && 673 (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)) { 674 __netif_tx_lock(txq, smp_processor_id()); 675 if (netif_tx_queue_stopped(txq) && 676 bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh && 677 txr->dev_state != BNXT_DEV_STATE_CLOSING) 678 netif_tx_wake_queue(txq); 679 __netif_tx_unlock(txq); 680 } 681 } 682 683 static struct page *__bnxt_alloc_rx_page(struct bnxt *bp, dma_addr_t *mapping, 684 struct bnxt_rx_ring_info *rxr, 685 gfp_t gfp) 686 { 687 struct device *dev = &bp->pdev->dev; 688 struct page *page; 689 690 page = page_pool_dev_alloc_pages(rxr->page_pool); 691 if (!page) 692 return NULL; 693 694 *mapping = dma_map_page_attrs(dev, page, 0, PAGE_SIZE, bp->rx_dir, 695 DMA_ATTR_WEAK_ORDERING); 696 if (dma_mapping_error(dev, *mapping)) { 697 page_pool_recycle_direct(rxr->page_pool, page); 698 return NULL; 699 } 700 *mapping += bp->rx_dma_offset; 701 return page; 702 } 703 704 static inline u8 *__bnxt_alloc_rx_data(struct bnxt *bp, dma_addr_t *mapping, 705 gfp_t gfp) 706 { 707 u8 *data; 708 struct pci_dev *pdev = bp->pdev; 709 710 data = kmalloc(bp->rx_buf_size, gfp); 711 if (!data) 712 return NULL; 713 714 *mapping = dma_map_single_attrs(&pdev->dev, data + bp->rx_dma_offset, 715 bp->rx_buf_use_size, bp->rx_dir, 716 DMA_ATTR_WEAK_ORDERING); 717 718 if (dma_mapping_error(&pdev->dev, *mapping)) { 719 kfree(data); 720 data = NULL; 721 } 722 return data; 723 } 724 725 int bnxt_alloc_rx_data(struct bnxt *bp, struct bnxt_rx_ring_info *rxr, 726 u16 prod, gfp_t gfp) 727 { 728 struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)]; 729 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[prod]; 730 dma_addr_t mapping; 731 732 if (BNXT_RX_PAGE_MODE(bp)) { 733 struct page *page = 734 __bnxt_alloc_rx_page(bp, &mapping, rxr, gfp); 735 736 if (!page) 737 return -ENOMEM; 738 739 rx_buf->data = page; 740 rx_buf->data_ptr = page_address(page) + bp->rx_offset; 741 } else { 742 u8 *data = __bnxt_alloc_rx_data(bp, &mapping, gfp); 743 744 if (!data) 745 return -ENOMEM; 746 747 rx_buf->data = data; 748 rx_buf->data_ptr = data + bp->rx_offset; 749 } 750 rx_buf->mapping = mapping; 751 752 rxbd->rx_bd_haddr = cpu_to_le64(mapping); 753 return 0; 754 } 755 756 void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons, void *data) 757 { 758 u16 prod = rxr->rx_prod; 759 struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf; 760 struct rx_bd *cons_bd, *prod_bd; 761 762 prod_rx_buf = &rxr->rx_buf_ring[prod]; 763 cons_rx_buf = &rxr->rx_buf_ring[cons]; 764 765 prod_rx_buf->data = data; 766 prod_rx_buf->data_ptr = cons_rx_buf->data_ptr; 767 768 prod_rx_buf->mapping = cons_rx_buf->mapping; 769 770 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)]; 771 cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)]; 772 773 prod_bd->rx_bd_haddr = cons_bd->rx_bd_haddr; 774 } 775 776 static inline u16 bnxt_find_next_agg_idx(struct bnxt_rx_ring_info *rxr, u16 idx) 777 { 778 u16 next, max = rxr->rx_agg_bmap_size; 779 780 next = find_next_zero_bit(rxr->rx_agg_bmap, max, idx); 781 if (next >= max) 782 next = find_first_zero_bit(rxr->rx_agg_bmap, max); 783 return next; 784 } 785 786 static inline int bnxt_alloc_rx_page(struct bnxt *bp, 787 struct bnxt_rx_ring_info *rxr, 788 u16 prod, gfp_t gfp) 789 { 790 struct rx_bd *rxbd = 791 &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)]; 792 struct bnxt_sw_rx_agg_bd *rx_agg_buf; 793 struct pci_dev *pdev = bp->pdev; 794 struct page *page; 795 dma_addr_t mapping; 796 u16 sw_prod = rxr->rx_sw_agg_prod; 797 unsigned int offset = 0; 798 799 if (PAGE_SIZE > BNXT_RX_PAGE_SIZE) { 800 page = rxr->rx_page; 801 if (!page) { 802 page = alloc_page(gfp); 803 if (!page) 804 return -ENOMEM; 805 rxr->rx_page = page; 806 rxr->rx_page_offset = 0; 807 } 808 offset = rxr->rx_page_offset; 809 rxr->rx_page_offset += BNXT_RX_PAGE_SIZE; 810 if (rxr->rx_page_offset == PAGE_SIZE) 811 rxr->rx_page = NULL; 812 else 813 get_page(page); 814 } else { 815 page = alloc_page(gfp); 816 if (!page) 817 return -ENOMEM; 818 } 819 820 mapping = dma_map_page_attrs(&pdev->dev, page, offset, 821 BNXT_RX_PAGE_SIZE, PCI_DMA_FROMDEVICE, 822 DMA_ATTR_WEAK_ORDERING); 823 if (dma_mapping_error(&pdev->dev, mapping)) { 824 __free_page(page); 825 return -EIO; 826 } 827 828 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap))) 829 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod); 830 831 __set_bit(sw_prod, rxr->rx_agg_bmap); 832 rx_agg_buf = &rxr->rx_agg_ring[sw_prod]; 833 rxr->rx_sw_agg_prod = NEXT_RX_AGG(sw_prod); 834 835 rx_agg_buf->page = page; 836 rx_agg_buf->offset = offset; 837 rx_agg_buf->mapping = mapping; 838 rxbd->rx_bd_haddr = cpu_to_le64(mapping); 839 rxbd->rx_bd_opaque = sw_prod; 840 return 0; 841 } 842 843 static struct rx_agg_cmp *bnxt_get_agg(struct bnxt *bp, 844 struct bnxt_cp_ring_info *cpr, 845 u16 cp_cons, u16 curr) 846 { 847 struct rx_agg_cmp *agg; 848 849 cp_cons = RING_CMP(ADV_RAW_CMP(cp_cons, curr)); 850 agg = (struct rx_agg_cmp *) 851 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 852 return agg; 853 } 854 855 static struct rx_agg_cmp *bnxt_get_tpa_agg_p5(struct bnxt *bp, 856 struct bnxt_rx_ring_info *rxr, 857 u16 agg_id, u16 curr) 858 { 859 struct bnxt_tpa_info *tpa_info = &rxr->rx_tpa[agg_id]; 860 861 return &tpa_info->agg_arr[curr]; 862 } 863 864 static void bnxt_reuse_rx_agg_bufs(struct bnxt_cp_ring_info *cpr, u16 idx, 865 u16 start, u32 agg_bufs, bool tpa) 866 { 867 struct bnxt_napi *bnapi = cpr->bnapi; 868 struct bnxt *bp = bnapi->bp; 869 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 870 u16 prod = rxr->rx_agg_prod; 871 u16 sw_prod = rxr->rx_sw_agg_prod; 872 bool p5_tpa = false; 873 u32 i; 874 875 if ((bp->flags & BNXT_FLAG_CHIP_P5) && tpa) 876 p5_tpa = true; 877 878 for (i = 0; i < agg_bufs; i++) { 879 u16 cons; 880 struct rx_agg_cmp *agg; 881 struct bnxt_sw_rx_agg_bd *cons_rx_buf, *prod_rx_buf; 882 struct rx_bd *prod_bd; 883 struct page *page; 884 885 if (p5_tpa) 886 agg = bnxt_get_tpa_agg_p5(bp, rxr, idx, start + i); 887 else 888 agg = bnxt_get_agg(bp, cpr, idx, start + i); 889 cons = agg->rx_agg_cmp_opaque; 890 __clear_bit(cons, rxr->rx_agg_bmap); 891 892 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap))) 893 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod); 894 895 __set_bit(sw_prod, rxr->rx_agg_bmap); 896 prod_rx_buf = &rxr->rx_agg_ring[sw_prod]; 897 cons_rx_buf = &rxr->rx_agg_ring[cons]; 898 899 /* It is possible for sw_prod to be equal to cons, so 900 * set cons_rx_buf->page to NULL first. 901 */ 902 page = cons_rx_buf->page; 903 cons_rx_buf->page = NULL; 904 prod_rx_buf->page = page; 905 prod_rx_buf->offset = cons_rx_buf->offset; 906 907 prod_rx_buf->mapping = cons_rx_buf->mapping; 908 909 prod_bd = &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)]; 910 911 prod_bd->rx_bd_haddr = cpu_to_le64(cons_rx_buf->mapping); 912 prod_bd->rx_bd_opaque = sw_prod; 913 914 prod = NEXT_RX_AGG(prod); 915 sw_prod = NEXT_RX_AGG(sw_prod); 916 } 917 rxr->rx_agg_prod = prod; 918 rxr->rx_sw_agg_prod = sw_prod; 919 } 920 921 static struct sk_buff *bnxt_rx_page_skb(struct bnxt *bp, 922 struct bnxt_rx_ring_info *rxr, 923 u16 cons, void *data, u8 *data_ptr, 924 dma_addr_t dma_addr, 925 unsigned int offset_and_len) 926 { 927 unsigned int payload = offset_and_len >> 16; 928 unsigned int len = offset_and_len & 0xffff; 929 skb_frag_t *frag; 930 struct page *page = data; 931 u16 prod = rxr->rx_prod; 932 struct sk_buff *skb; 933 int off, err; 934 935 err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC); 936 if (unlikely(err)) { 937 bnxt_reuse_rx_data(rxr, cons, data); 938 return NULL; 939 } 940 dma_addr -= bp->rx_dma_offset; 941 dma_unmap_page_attrs(&bp->pdev->dev, dma_addr, PAGE_SIZE, bp->rx_dir, 942 DMA_ATTR_WEAK_ORDERING); 943 page_pool_release_page(rxr->page_pool, page); 944 945 if (unlikely(!payload)) 946 payload = eth_get_headlen(bp->dev, data_ptr, len); 947 948 skb = napi_alloc_skb(&rxr->bnapi->napi, payload); 949 if (!skb) { 950 __free_page(page); 951 return NULL; 952 } 953 954 off = (void *)data_ptr - page_address(page); 955 skb_add_rx_frag(skb, 0, page, off, len, PAGE_SIZE); 956 memcpy(skb->data - NET_IP_ALIGN, data_ptr - NET_IP_ALIGN, 957 payload + NET_IP_ALIGN); 958 959 frag = &skb_shinfo(skb)->frags[0]; 960 skb_frag_size_sub(frag, payload); 961 skb_frag_off_add(frag, payload); 962 skb->data_len -= payload; 963 skb->tail += payload; 964 965 return skb; 966 } 967 968 static struct sk_buff *bnxt_rx_skb(struct bnxt *bp, 969 struct bnxt_rx_ring_info *rxr, u16 cons, 970 void *data, u8 *data_ptr, 971 dma_addr_t dma_addr, 972 unsigned int offset_and_len) 973 { 974 u16 prod = rxr->rx_prod; 975 struct sk_buff *skb; 976 int err; 977 978 err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC); 979 if (unlikely(err)) { 980 bnxt_reuse_rx_data(rxr, cons, data); 981 return NULL; 982 } 983 984 skb = build_skb(data, 0); 985 dma_unmap_single_attrs(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size, 986 bp->rx_dir, DMA_ATTR_WEAK_ORDERING); 987 if (!skb) { 988 kfree(data); 989 return NULL; 990 } 991 992 skb_reserve(skb, bp->rx_offset); 993 skb_put(skb, offset_and_len & 0xffff); 994 return skb; 995 } 996 997 static struct sk_buff *bnxt_rx_pages(struct bnxt *bp, 998 struct bnxt_cp_ring_info *cpr, 999 struct sk_buff *skb, u16 idx, 1000 u32 agg_bufs, bool tpa) 1001 { 1002 struct bnxt_napi *bnapi = cpr->bnapi; 1003 struct pci_dev *pdev = bp->pdev; 1004 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 1005 u16 prod = rxr->rx_agg_prod; 1006 bool p5_tpa = false; 1007 u32 i; 1008 1009 if ((bp->flags & BNXT_FLAG_CHIP_P5) && tpa) 1010 p5_tpa = true; 1011 1012 for (i = 0; i < agg_bufs; i++) { 1013 u16 cons, frag_len; 1014 struct rx_agg_cmp *agg; 1015 struct bnxt_sw_rx_agg_bd *cons_rx_buf; 1016 struct page *page; 1017 dma_addr_t mapping; 1018 1019 if (p5_tpa) 1020 agg = bnxt_get_tpa_agg_p5(bp, rxr, idx, i); 1021 else 1022 agg = bnxt_get_agg(bp, cpr, idx, i); 1023 cons = agg->rx_agg_cmp_opaque; 1024 frag_len = (le32_to_cpu(agg->rx_agg_cmp_len_flags_type) & 1025 RX_AGG_CMP_LEN) >> RX_AGG_CMP_LEN_SHIFT; 1026 1027 cons_rx_buf = &rxr->rx_agg_ring[cons]; 1028 skb_fill_page_desc(skb, i, cons_rx_buf->page, 1029 cons_rx_buf->offset, frag_len); 1030 __clear_bit(cons, rxr->rx_agg_bmap); 1031 1032 /* It is possible for bnxt_alloc_rx_page() to allocate 1033 * a sw_prod index that equals the cons index, so we 1034 * need to clear the cons entry now. 1035 */ 1036 mapping = cons_rx_buf->mapping; 1037 page = cons_rx_buf->page; 1038 cons_rx_buf->page = NULL; 1039 1040 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_ATOMIC) != 0) { 1041 struct skb_shared_info *shinfo; 1042 unsigned int nr_frags; 1043 1044 shinfo = skb_shinfo(skb); 1045 nr_frags = --shinfo->nr_frags; 1046 __skb_frag_set_page(&shinfo->frags[nr_frags], NULL); 1047 1048 dev_kfree_skb(skb); 1049 1050 cons_rx_buf->page = page; 1051 1052 /* Update prod since possibly some pages have been 1053 * allocated already. 1054 */ 1055 rxr->rx_agg_prod = prod; 1056 bnxt_reuse_rx_agg_bufs(cpr, idx, i, agg_bufs - i, tpa); 1057 return NULL; 1058 } 1059 1060 dma_unmap_page_attrs(&pdev->dev, mapping, BNXT_RX_PAGE_SIZE, 1061 PCI_DMA_FROMDEVICE, 1062 DMA_ATTR_WEAK_ORDERING); 1063 1064 skb->data_len += frag_len; 1065 skb->len += frag_len; 1066 skb->truesize += PAGE_SIZE; 1067 1068 prod = NEXT_RX_AGG(prod); 1069 } 1070 rxr->rx_agg_prod = prod; 1071 return skb; 1072 } 1073 1074 static int bnxt_agg_bufs_valid(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, 1075 u8 agg_bufs, u32 *raw_cons) 1076 { 1077 u16 last; 1078 struct rx_agg_cmp *agg; 1079 1080 *raw_cons = ADV_RAW_CMP(*raw_cons, agg_bufs); 1081 last = RING_CMP(*raw_cons); 1082 agg = (struct rx_agg_cmp *) 1083 &cpr->cp_desc_ring[CP_RING(last)][CP_IDX(last)]; 1084 return RX_AGG_CMP_VALID(agg, *raw_cons); 1085 } 1086 1087 static inline struct sk_buff *bnxt_copy_skb(struct bnxt_napi *bnapi, u8 *data, 1088 unsigned int len, 1089 dma_addr_t mapping) 1090 { 1091 struct bnxt *bp = bnapi->bp; 1092 struct pci_dev *pdev = bp->pdev; 1093 struct sk_buff *skb; 1094 1095 skb = napi_alloc_skb(&bnapi->napi, len); 1096 if (!skb) 1097 return NULL; 1098 1099 dma_sync_single_for_cpu(&pdev->dev, mapping, bp->rx_copy_thresh, 1100 bp->rx_dir); 1101 1102 memcpy(skb->data - NET_IP_ALIGN, data - NET_IP_ALIGN, 1103 len + NET_IP_ALIGN); 1104 1105 dma_sync_single_for_device(&pdev->dev, mapping, bp->rx_copy_thresh, 1106 bp->rx_dir); 1107 1108 skb_put(skb, len); 1109 return skb; 1110 } 1111 1112 static int bnxt_discard_rx(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, 1113 u32 *raw_cons, void *cmp) 1114 { 1115 struct rx_cmp *rxcmp = cmp; 1116 u32 tmp_raw_cons = *raw_cons; 1117 u8 cmp_type, agg_bufs = 0; 1118 1119 cmp_type = RX_CMP_TYPE(rxcmp); 1120 1121 if (cmp_type == CMP_TYPE_RX_L2_CMP) { 1122 agg_bufs = (le32_to_cpu(rxcmp->rx_cmp_misc_v1) & 1123 RX_CMP_AGG_BUFS) >> 1124 RX_CMP_AGG_BUFS_SHIFT; 1125 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) { 1126 struct rx_tpa_end_cmp *tpa_end = cmp; 1127 1128 if (bp->flags & BNXT_FLAG_CHIP_P5) 1129 return 0; 1130 1131 agg_bufs = TPA_END_AGG_BUFS(tpa_end); 1132 } 1133 1134 if (agg_bufs) { 1135 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons)) 1136 return -EBUSY; 1137 } 1138 *raw_cons = tmp_raw_cons; 1139 return 0; 1140 } 1141 1142 static void bnxt_queue_fw_reset_work(struct bnxt *bp, unsigned long delay) 1143 { 1144 if (BNXT_PF(bp)) 1145 queue_delayed_work(bnxt_pf_wq, &bp->fw_reset_task, delay); 1146 else 1147 schedule_delayed_work(&bp->fw_reset_task, delay); 1148 } 1149 1150 static void bnxt_queue_sp_work(struct bnxt *bp) 1151 { 1152 if (BNXT_PF(bp)) 1153 queue_work(bnxt_pf_wq, &bp->sp_task); 1154 else 1155 schedule_work(&bp->sp_task); 1156 } 1157 1158 static void bnxt_cancel_sp_work(struct bnxt *bp) 1159 { 1160 if (BNXT_PF(bp)) 1161 flush_workqueue(bnxt_pf_wq); 1162 else 1163 cancel_work_sync(&bp->sp_task); 1164 } 1165 1166 static void bnxt_sched_reset(struct bnxt *bp, struct bnxt_rx_ring_info *rxr) 1167 { 1168 if (!rxr->bnapi->in_reset) { 1169 rxr->bnapi->in_reset = true; 1170 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event); 1171 bnxt_queue_sp_work(bp); 1172 } 1173 rxr->rx_next_cons = 0xffff; 1174 } 1175 1176 static u16 bnxt_alloc_agg_idx(struct bnxt_rx_ring_info *rxr, u16 agg_id) 1177 { 1178 struct bnxt_tpa_idx_map *map = rxr->rx_tpa_idx_map; 1179 u16 idx = agg_id & MAX_TPA_P5_MASK; 1180 1181 if (test_bit(idx, map->agg_idx_bmap)) 1182 idx = find_first_zero_bit(map->agg_idx_bmap, 1183 BNXT_AGG_IDX_BMAP_SIZE); 1184 __set_bit(idx, map->agg_idx_bmap); 1185 map->agg_id_tbl[agg_id] = idx; 1186 return idx; 1187 } 1188 1189 static void bnxt_free_agg_idx(struct bnxt_rx_ring_info *rxr, u16 idx) 1190 { 1191 struct bnxt_tpa_idx_map *map = rxr->rx_tpa_idx_map; 1192 1193 __clear_bit(idx, map->agg_idx_bmap); 1194 } 1195 1196 static u16 bnxt_lookup_agg_idx(struct bnxt_rx_ring_info *rxr, u16 agg_id) 1197 { 1198 struct bnxt_tpa_idx_map *map = rxr->rx_tpa_idx_map; 1199 1200 return map->agg_id_tbl[agg_id]; 1201 } 1202 1203 static void bnxt_tpa_start(struct bnxt *bp, struct bnxt_rx_ring_info *rxr, 1204 struct rx_tpa_start_cmp *tpa_start, 1205 struct rx_tpa_start_cmp_ext *tpa_start1) 1206 { 1207 struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf; 1208 struct bnxt_tpa_info *tpa_info; 1209 u16 cons, prod, agg_id; 1210 struct rx_bd *prod_bd; 1211 dma_addr_t mapping; 1212 1213 if (bp->flags & BNXT_FLAG_CHIP_P5) { 1214 agg_id = TPA_START_AGG_ID_P5(tpa_start); 1215 agg_id = bnxt_alloc_agg_idx(rxr, agg_id); 1216 } else { 1217 agg_id = TPA_START_AGG_ID(tpa_start); 1218 } 1219 cons = tpa_start->rx_tpa_start_cmp_opaque; 1220 prod = rxr->rx_prod; 1221 cons_rx_buf = &rxr->rx_buf_ring[cons]; 1222 prod_rx_buf = &rxr->rx_buf_ring[prod]; 1223 tpa_info = &rxr->rx_tpa[agg_id]; 1224 1225 if (unlikely(cons != rxr->rx_next_cons || 1226 TPA_START_ERROR(tpa_start))) { 1227 netdev_warn(bp->dev, "TPA cons %x, expected cons %x, error code %x\n", 1228 cons, rxr->rx_next_cons, 1229 TPA_START_ERROR_CODE(tpa_start1)); 1230 bnxt_sched_reset(bp, rxr); 1231 return; 1232 } 1233 /* Store cfa_code in tpa_info to use in tpa_end 1234 * completion processing. 1235 */ 1236 tpa_info->cfa_code = TPA_START_CFA_CODE(tpa_start1); 1237 prod_rx_buf->data = tpa_info->data; 1238 prod_rx_buf->data_ptr = tpa_info->data_ptr; 1239 1240 mapping = tpa_info->mapping; 1241 prod_rx_buf->mapping = mapping; 1242 1243 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)]; 1244 1245 prod_bd->rx_bd_haddr = cpu_to_le64(mapping); 1246 1247 tpa_info->data = cons_rx_buf->data; 1248 tpa_info->data_ptr = cons_rx_buf->data_ptr; 1249 cons_rx_buf->data = NULL; 1250 tpa_info->mapping = cons_rx_buf->mapping; 1251 1252 tpa_info->len = 1253 le32_to_cpu(tpa_start->rx_tpa_start_cmp_len_flags_type) >> 1254 RX_TPA_START_CMP_LEN_SHIFT; 1255 if (likely(TPA_START_HASH_VALID(tpa_start))) { 1256 u32 hash_type = TPA_START_HASH_TYPE(tpa_start); 1257 1258 tpa_info->hash_type = PKT_HASH_TYPE_L4; 1259 tpa_info->gso_type = SKB_GSO_TCPV4; 1260 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */ 1261 if (hash_type == 3 || TPA_START_IS_IPV6(tpa_start1)) 1262 tpa_info->gso_type = SKB_GSO_TCPV6; 1263 tpa_info->rss_hash = 1264 le32_to_cpu(tpa_start->rx_tpa_start_cmp_rss_hash); 1265 } else { 1266 tpa_info->hash_type = PKT_HASH_TYPE_NONE; 1267 tpa_info->gso_type = 0; 1268 if (netif_msg_rx_err(bp)) 1269 netdev_warn(bp->dev, "TPA packet without valid hash\n"); 1270 } 1271 tpa_info->flags2 = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_flags2); 1272 tpa_info->metadata = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_metadata); 1273 tpa_info->hdr_info = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_hdr_info); 1274 tpa_info->agg_count = 0; 1275 1276 rxr->rx_prod = NEXT_RX(prod); 1277 cons = NEXT_RX(cons); 1278 rxr->rx_next_cons = NEXT_RX(cons); 1279 cons_rx_buf = &rxr->rx_buf_ring[cons]; 1280 1281 bnxt_reuse_rx_data(rxr, cons, cons_rx_buf->data); 1282 rxr->rx_prod = NEXT_RX(rxr->rx_prod); 1283 cons_rx_buf->data = NULL; 1284 } 1285 1286 static void bnxt_abort_tpa(struct bnxt_cp_ring_info *cpr, u16 idx, u32 agg_bufs) 1287 { 1288 if (agg_bufs) 1289 bnxt_reuse_rx_agg_bufs(cpr, idx, 0, agg_bufs, true); 1290 } 1291 1292 #ifdef CONFIG_INET 1293 static void bnxt_gro_tunnel(struct sk_buff *skb, __be16 ip_proto) 1294 { 1295 struct udphdr *uh = NULL; 1296 1297 if (ip_proto == htons(ETH_P_IP)) { 1298 struct iphdr *iph = (struct iphdr *)skb->data; 1299 1300 if (iph->protocol == IPPROTO_UDP) 1301 uh = (struct udphdr *)(iph + 1); 1302 } else { 1303 struct ipv6hdr *iph = (struct ipv6hdr *)skb->data; 1304 1305 if (iph->nexthdr == IPPROTO_UDP) 1306 uh = (struct udphdr *)(iph + 1); 1307 } 1308 if (uh) { 1309 if (uh->check) 1310 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL_CSUM; 1311 else 1312 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL; 1313 } 1314 } 1315 #endif 1316 1317 static struct sk_buff *bnxt_gro_func_5731x(struct bnxt_tpa_info *tpa_info, 1318 int payload_off, int tcp_ts, 1319 struct sk_buff *skb) 1320 { 1321 #ifdef CONFIG_INET 1322 struct tcphdr *th; 1323 int len, nw_off; 1324 u16 outer_ip_off, inner_ip_off, inner_mac_off; 1325 u32 hdr_info = tpa_info->hdr_info; 1326 bool loopback = false; 1327 1328 inner_ip_off = BNXT_TPA_INNER_L3_OFF(hdr_info); 1329 inner_mac_off = BNXT_TPA_INNER_L2_OFF(hdr_info); 1330 outer_ip_off = BNXT_TPA_OUTER_L3_OFF(hdr_info); 1331 1332 /* If the packet is an internal loopback packet, the offsets will 1333 * have an extra 4 bytes. 1334 */ 1335 if (inner_mac_off == 4) { 1336 loopback = true; 1337 } else if (inner_mac_off > 4) { 1338 __be16 proto = *((__be16 *)(skb->data + inner_ip_off - 1339 ETH_HLEN - 2)); 1340 1341 /* We only support inner iPv4/ipv6. If we don't see the 1342 * correct protocol ID, it must be a loopback packet where 1343 * the offsets are off by 4. 1344 */ 1345 if (proto != htons(ETH_P_IP) && proto != htons(ETH_P_IPV6)) 1346 loopback = true; 1347 } 1348 if (loopback) { 1349 /* internal loopback packet, subtract all offsets by 4 */ 1350 inner_ip_off -= 4; 1351 inner_mac_off -= 4; 1352 outer_ip_off -= 4; 1353 } 1354 1355 nw_off = inner_ip_off - ETH_HLEN; 1356 skb_set_network_header(skb, nw_off); 1357 if (tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_IP_TYPE) { 1358 struct ipv6hdr *iph = ipv6_hdr(skb); 1359 1360 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr)); 1361 len = skb->len - skb_transport_offset(skb); 1362 th = tcp_hdr(skb); 1363 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0); 1364 } else { 1365 struct iphdr *iph = ip_hdr(skb); 1366 1367 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr)); 1368 len = skb->len - skb_transport_offset(skb); 1369 th = tcp_hdr(skb); 1370 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0); 1371 } 1372 1373 if (inner_mac_off) { /* tunnel */ 1374 __be16 proto = *((__be16 *)(skb->data + outer_ip_off - 1375 ETH_HLEN - 2)); 1376 1377 bnxt_gro_tunnel(skb, proto); 1378 } 1379 #endif 1380 return skb; 1381 } 1382 1383 static struct sk_buff *bnxt_gro_func_5750x(struct bnxt_tpa_info *tpa_info, 1384 int payload_off, int tcp_ts, 1385 struct sk_buff *skb) 1386 { 1387 #ifdef CONFIG_INET 1388 u16 outer_ip_off, inner_ip_off, inner_mac_off; 1389 u32 hdr_info = tpa_info->hdr_info; 1390 int iphdr_len, nw_off; 1391 1392 inner_ip_off = BNXT_TPA_INNER_L3_OFF(hdr_info); 1393 inner_mac_off = BNXT_TPA_INNER_L2_OFF(hdr_info); 1394 outer_ip_off = BNXT_TPA_OUTER_L3_OFF(hdr_info); 1395 1396 nw_off = inner_ip_off - ETH_HLEN; 1397 skb_set_network_header(skb, nw_off); 1398 iphdr_len = (tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_IP_TYPE) ? 1399 sizeof(struct ipv6hdr) : sizeof(struct iphdr); 1400 skb_set_transport_header(skb, nw_off + iphdr_len); 1401 1402 if (inner_mac_off) { /* tunnel */ 1403 __be16 proto = *((__be16 *)(skb->data + outer_ip_off - 1404 ETH_HLEN - 2)); 1405 1406 bnxt_gro_tunnel(skb, proto); 1407 } 1408 #endif 1409 return skb; 1410 } 1411 1412 #define BNXT_IPV4_HDR_SIZE (sizeof(struct iphdr) + sizeof(struct tcphdr)) 1413 #define BNXT_IPV6_HDR_SIZE (sizeof(struct ipv6hdr) + sizeof(struct tcphdr)) 1414 1415 static struct sk_buff *bnxt_gro_func_5730x(struct bnxt_tpa_info *tpa_info, 1416 int payload_off, int tcp_ts, 1417 struct sk_buff *skb) 1418 { 1419 #ifdef CONFIG_INET 1420 struct tcphdr *th; 1421 int len, nw_off, tcp_opt_len = 0; 1422 1423 if (tcp_ts) 1424 tcp_opt_len = 12; 1425 1426 if (tpa_info->gso_type == SKB_GSO_TCPV4) { 1427 struct iphdr *iph; 1428 1429 nw_off = payload_off - BNXT_IPV4_HDR_SIZE - tcp_opt_len - 1430 ETH_HLEN; 1431 skb_set_network_header(skb, nw_off); 1432 iph = ip_hdr(skb); 1433 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr)); 1434 len = skb->len - skb_transport_offset(skb); 1435 th = tcp_hdr(skb); 1436 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0); 1437 } else if (tpa_info->gso_type == SKB_GSO_TCPV6) { 1438 struct ipv6hdr *iph; 1439 1440 nw_off = payload_off - BNXT_IPV6_HDR_SIZE - tcp_opt_len - 1441 ETH_HLEN; 1442 skb_set_network_header(skb, nw_off); 1443 iph = ipv6_hdr(skb); 1444 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr)); 1445 len = skb->len - skb_transport_offset(skb); 1446 th = tcp_hdr(skb); 1447 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0); 1448 } else { 1449 dev_kfree_skb_any(skb); 1450 return NULL; 1451 } 1452 1453 if (nw_off) /* tunnel */ 1454 bnxt_gro_tunnel(skb, skb->protocol); 1455 #endif 1456 return skb; 1457 } 1458 1459 static inline struct sk_buff *bnxt_gro_skb(struct bnxt *bp, 1460 struct bnxt_tpa_info *tpa_info, 1461 struct rx_tpa_end_cmp *tpa_end, 1462 struct rx_tpa_end_cmp_ext *tpa_end1, 1463 struct sk_buff *skb) 1464 { 1465 #ifdef CONFIG_INET 1466 int payload_off; 1467 u16 segs; 1468 1469 segs = TPA_END_TPA_SEGS(tpa_end); 1470 if (segs == 1) 1471 return skb; 1472 1473 NAPI_GRO_CB(skb)->count = segs; 1474 skb_shinfo(skb)->gso_size = 1475 le32_to_cpu(tpa_end1->rx_tpa_end_cmp_seg_len); 1476 skb_shinfo(skb)->gso_type = tpa_info->gso_type; 1477 if (bp->flags & BNXT_FLAG_CHIP_P5) 1478 payload_off = TPA_END_PAYLOAD_OFF_P5(tpa_end1); 1479 else 1480 payload_off = TPA_END_PAYLOAD_OFF(tpa_end); 1481 skb = bp->gro_func(tpa_info, payload_off, TPA_END_GRO_TS(tpa_end), skb); 1482 if (likely(skb)) 1483 tcp_gro_complete(skb); 1484 #endif 1485 return skb; 1486 } 1487 1488 /* Given the cfa_code of a received packet determine which 1489 * netdev (vf-rep or PF) the packet is destined to. 1490 */ 1491 static struct net_device *bnxt_get_pkt_dev(struct bnxt *bp, u16 cfa_code) 1492 { 1493 struct net_device *dev = bnxt_get_vf_rep(bp, cfa_code); 1494 1495 /* if vf-rep dev is NULL, the must belongs to the PF */ 1496 return dev ? dev : bp->dev; 1497 } 1498 1499 static inline struct sk_buff *bnxt_tpa_end(struct bnxt *bp, 1500 struct bnxt_cp_ring_info *cpr, 1501 u32 *raw_cons, 1502 struct rx_tpa_end_cmp *tpa_end, 1503 struct rx_tpa_end_cmp_ext *tpa_end1, 1504 u8 *event) 1505 { 1506 struct bnxt_napi *bnapi = cpr->bnapi; 1507 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 1508 u8 *data_ptr, agg_bufs; 1509 unsigned int len; 1510 struct bnxt_tpa_info *tpa_info; 1511 dma_addr_t mapping; 1512 struct sk_buff *skb; 1513 u16 idx = 0, agg_id; 1514 void *data; 1515 bool gro; 1516 1517 if (unlikely(bnapi->in_reset)) { 1518 int rc = bnxt_discard_rx(bp, cpr, raw_cons, tpa_end); 1519 1520 if (rc < 0) 1521 return ERR_PTR(-EBUSY); 1522 return NULL; 1523 } 1524 1525 if (bp->flags & BNXT_FLAG_CHIP_P5) { 1526 agg_id = TPA_END_AGG_ID_P5(tpa_end); 1527 agg_id = bnxt_lookup_agg_idx(rxr, agg_id); 1528 agg_bufs = TPA_END_AGG_BUFS_P5(tpa_end1); 1529 tpa_info = &rxr->rx_tpa[agg_id]; 1530 if (unlikely(agg_bufs != tpa_info->agg_count)) { 1531 netdev_warn(bp->dev, "TPA end agg_buf %d != expected agg_bufs %d\n", 1532 agg_bufs, tpa_info->agg_count); 1533 agg_bufs = tpa_info->agg_count; 1534 } 1535 tpa_info->agg_count = 0; 1536 *event |= BNXT_AGG_EVENT; 1537 bnxt_free_agg_idx(rxr, agg_id); 1538 idx = agg_id; 1539 gro = !!(bp->flags & BNXT_FLAG_GRO); 1540 } else { 1541 agg_id = TPA_END_AGG_ID(tpa_end); 1542 agg_bufs = TPA_END_AGG_BUFS(tpa_end); 1543 tpa_info = &rxr->rx_tpa[agg_id]; 1544 idx = RING_CMP(*raw_cons); 1545 if (agg_bufs) { 1546 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, raw_cons)) 1547 return ERR_PTR(-EBUSY); 1548 1549 *event |= BNXT_AGG_EVENT; 1550 idx = NEXT_CMP(idx); 1551 } 1552 gro = !!TPA_END_GRO(tpa_end); 1553 } 1554 data = tpa_info->data; 1555 data_ptr = tpa_info->data_ptr; 1556 prefetch(data_ptr); 1557 len = tpa_info->len; 1558 mapping = tpa_info->mapping; 1559 1560 if (unlikely(agg_bufs > MAX_SKB_FRAGS || TPA_END_ERRORS(tpa_end1))) { 1561 bnxt_abort_tpa(cpr, idx, agg_bufs); 1562 if (agg_bufs > MAX_SKB_FRAGS) 1563 netdev_warn(bp->dev, "TPA frags %d exceeded MAX_SKB_FRAGS %d\n", 1564 agg_bufs, (int)MAX_SKB_FRAGS); 1565 return NULL; 1566 } 1567 1568 if (len <= bp->rx_copy_thresh) { 1569 skb = bnxt_copy_skb(bnapi, data_ptr, len, mapping); 1570 if (!skb) { 1571 bnxt_abort_tpa(cpr, idx, agg_bufs); 1572 return NULL; 1573 } 1574 } else { 1575 u8 *new_data; 1576 dma_addr_t new_mapping; 1577 1578 new_data = __bnxt_alloc_rx_data(bp, &new_mapping, GFP_ATOMIC); 1579 if (!new_data) { 1580 bnxt_abort_tpa(cpr, idx, agg_bufs); 1581 return NULL; 1582 } 1583 1584 tpa_info->data = new_data; 1585 tpa_info->data_ptr = new_data + bp->rx_offset; 1586 tpa_info->mapping = new_mapping; 1587 1588 skb = build_skb(data, 0); 1589 dma_unmap_single_attrs(&bp->pdev->dev, mapping, 1590 bp->rx_buf_use_size, bp->rx_dir, 1591 DMA_ATTR_WEAK_ORDERING); 1592 1593 if (!skb) { 1594 kfree(data); 1595 bnxt_abort_tpa(cpr, idx, agg_bufs); 1596 return NULL; 1597 } 1598 skb_reserve(skb, bp->rx_offset); 1599 skb_put(skb, len); 1600 } 1601 1602 if (agg_bufs) { 1603 skb = bnxt_rx_pages(bp, cpr, skb, idx, agg_bufs, true); 1604 if (!skb) { 1605 /* Page reuse already handled by bnxt_rx_pages(). */ 1606 return NULL; 1607 } 1608 } 1609 1610 skb->protocol = 1611 eth_type_trans(skb, bnxt_get_pkt_dev(bp, tpa_info->cfa_code)); 1612 1613 if (tpa_info->hash_type != PKT_HASH_TYPE_NONE) 1614 skb_set_hash(skb, tpa_info->rss_hash, tpa_info->hash_type); 1615 1616 if ((tpa_info->flags2 & RX_CMP_FLAGS2_META_FORMAT_VLAN) && 1617 (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) { 1618 u16 vlan_proto = tpa_info->metadata >> 1619 RX_CMP_FLAGS2_METADATA_TPID_SFT; 1620 u16 vtag = tpa_info->metadata & RX_CMP_FLAGS2_METADATA_TCI_MASK; 1621 1622 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag); 1623 } 1624 1625 skb_checksum_none_assert(skb); 1626 if (likely(tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_L4_CS_CALC)) { 1627 skb->ip_summed = CHECKSUM_UNNECESSARY; 1628 skb->csum_level = 1629 (tpa_info->flags2 & RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3; 1630 } 1631 1632 if (gro) 1633 skb = bnxt_gro_skb(bp, tpa_info, tpa_end, tpa_end1, skb); 1634 1635 return skb; 1636 } 1637 1638 static void bnxt_tpa_agg(struct bnxt *bp, struct bnxt_rx_ring_info *rxr, 1639 struct rx_agg_cmp *rx_agg) 1640 { 1641 u16 agg_id = TPA_AGG_AGG_ID(rx_agg); 1642 struct bnxt_tpa_info *tpa_info; 1643 1644 agg_id = bnxt_lookup_agg_idx(rxr, agg_id); 1645 tpa_info = &rxr->rx_tpa[agg_id]; 1646 BUG_ON(tpa_info->agg_count >= MAX_SKB_FRAGS); 1647 tpa_info->agg_arr[tpa_info->agg_count++] = *rx_agg; 1648 } 1649 1650 static void bnxt_deliver_skb(struct bnxt *bp, struct bnxt_napi *bnapi, 1651 struct sk_buff *skb) 1652 { 1653 if (skb->dev != bp->dev) { 1654 /* this packet belongs to a vf-rep */ 1655 bnxt_vf_rep_rx(bp, skb); 1656 return; 1657 } 1658 skb_record_rx_queue(skb, bnapi->index); 1659 napi_gro_receive(&bnapi->napi, skb); 1660 } 1661 1662 /* returns the following: 1663 * 1 - 1 packet successfully received 1664 * 0 - successful TPA_START, packet not completed yet 1665 * -EBUSY - completion ring does not have all the agg buffers yet 1666 * -ENOMEM - packet aborted due to out of memory 1667 * -EIO - packet aborted due to hw error indicated in BD 1668 */ 1669 static int bnxt_rx_pkt(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, 1670 u32 *raw_cons, u8 *event) 1671 { 1672 struct bnxt_napi *bnapi = cpr->bnapi; 1673 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 1674 struct net_device *dev = bp->dev; 1675 struct rx_cmp *rxcmp; 1676 struct rx_cmp_ext *rxcmp1; 1677 u32 tmp_raw_cons = *raw_cons; 1678 u16 cfa_code, cons, prod, cp_cons = RING_CMP(tmp_raw_cons); 1679 struct bnxt_sw_rx_bd *rx_buf; 1680 unsigned int len; 1681 u8 *data_ptr, agg_bufs, cmp_type; 1682 dma_addr_t dma_addr; 1683 struct sk_buff *skb; 1684 void *data; 1685 int rc = 0; 1686 u32 misc; 1687 1688 rxcmp = (struct rx_cmp *) 1689 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 1690 1691 cmp_type = RX_CMP_TYPE(rxcmp); 1692 1693 if (cmp_type == CMP_TYPE_RX_TPA_AGG_CMP) { 1694 bnxt_tpa_agg(bp, rxr, (struct rx_agg_cmp *)rxcmp); 1695 goto next_rx_no_prod_no_len; 1696 } 1697 1698 tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons); 1699 cp_cons = RING_CMP(tmp_raw_cons); 1700 rxcmp1 = (struct rx_cmp_ext *) 1701 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 1702 1703 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons)) 1704 return -EBUSY; 1705 1706 prod = rxr->rx_prod; 1707 1708 if (cmp_type == CMP_TYPE_RX_L2_TPA_START_CMP) { 1709 bnxt_tpa_start(bp, rxr, (struct rx_tpa_start_cmp *)rxcmp, 1710 (struct rx_tpa_start_cmp_ext *)rxcmp1); 1711 1712 *event |= BNXT_RX_EVENT; 1713 goto next_rx_no_prod_no_len; 1714 1715 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) { 1716 skb = bnxt_tpa_end(bp, cpr, &tmp_raw_cons, 1717 (struct rx_tpa_end_cmp *)rxcmp, 1718 (struct rx_tpa_end_cmp_ext *)rxcmp1, event); 1719 1720 if (IS_ERR(skb)) 1721 return -EBUSY; 1722 1723 rc = -ENOMEM; 1724 if (likely(skb)) { 1725 bnxt_deliver_skb(bp, bnapi, skb); 1726 rc = 1; 1727 } 1728 *event |= BNXT_RX_EVENT; 1729 goto next_rx_no_prod_no_len; 1730 } 1731 1732 cons = rxcmp->rx_cmp_opaque; 1733 if (unlikely(cons != rxr->rx_next_cons)) { 1734 int rc1 = bnxt_discard_rx(bp, cpr, raw_cons, rxcmp); 1735 1736 netdev_warn(bp->dev, "RX cons %x != expected cons %x\n", 1737 cons, rxr->rx_next_cons); 1738 bnxt_sched_reset(bp, rxr); 1739 return rc1; 1740 } 1741 rx_buf = &rxr->rx_buf_ring[cons]; 1742 data = rx_buf->data; 1743 data_ptr = rx_buf->data_ptr; 1744 prefetch(data_ptr); 1745 1746 misc = le32_to_cpu(rxcmp->rx_cmp_misc_v1); 1747 agg_bufs = (misc & RX_CMP_AGG_BUFS) >> RX_CMP_AGG_BUFS_SHIFT; 1748 1749 if (agg_bufs) { 1750 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons)) 1751 return -EBUSY; 1752 1753 cp_cons = NEXT_CMP(cp_cons); 1754 *event |= BNXT_AGG_EVENT; 1755 } 1756 *event |= BNXT_RX_EVENT; 1757 1758 rx_buf->data = NULL; 1759 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L2_ERRORS) { 1760 u32 rx_err = le32_to_cpu(rxcmp1->rx_cmp_cfa_code_errors_v2); 1761 1762 bnxt_reuse_rx_data(rxr, cons, data); 1763 if (agg_bufs) 1764 bnxt_reuse_rx_agg_bufs(cpr, cp_cons, 0, agg_bufs, 1765 false); 1766 1767 rc = -EIO; 1768 if (rx_err & RX_CMPL_ERRORS_BUFFER_ERROR_MASK) { 1769 bnapi->cp_ring.rx_buf_errors++; 1770 if (!(bp->flags & BNXT_FLAG_CHIP_P5)) { 1771 netdev_warn(bp->dev, "RX buffer error %x\n", 1772 rx_err); 1773 bnxt_sched_reset(bp, rxr); 1774 } 1775 } 1776 goto next_rx_no_len; 1777 } 1778 1779 len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT; 1780 dma_addr = rx_buf->mapping; 1781 1782 if (bnxt_rx_xdp(bp, rxr, cons, data, &data_ptr, &len, event)) { 1783 rc = 1; 1784 goto next_rx; 1785 } 1786 1787 if (len <= bp->rx_copy_thresh) { 1788 skb = bnxt_copy_skb(bnapi, data_ptr, len, dma_addr); 1789 bnxt_reuse_rx_data(rxr, cons, data); 1790 if (!skb) { 1791 if (agg_bufs) 1792 bnxt_reuse_rx_agg_bufs(cpr, cp_cons, 0, 1793 agg_bufs, false); 1794 rc = -ENOMEM; 1795 goto next_rx; 1796 } 1797 } else { 1798 u32 payload; 1799 1800 if (rx_buf->data_ptr == data_ptr) 1801 payload = misc & RX_CMP_PAYLOAD_OFFSET; 1802 else 1803 payload = 0; 1804 skb = bp->rx_skb_func(bp, rxr, cons, data, data_ptr, dma_addr, 1805 payload | len); 1806 if (!skb) { 1807 rc = -ENOMEM; 1808 goto next_rx; 1809 } 1810 } 1811 1812 if (agg_bufs) { 1813 skb = bnxt_rx_pages(bp, cpr, skb, cp_cons, agg_bufs, false); 1814 if (!skb) { 1815 rc = -ENOMEM; 1816 goto next_rx; 1817 } 1818 } 1819 1820 if (RX_CMP_HASH_VALID(rxcmp)) { 1821 u32 hash_type = RX_CMP_HASH_TYPE(rxcmp); 1822 enum pkt_hash_types type = PKT_HASH_TYPE_L4; 1823 1824 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */ 1825 if (hash_type != 1 && hash_type != 3) 1826 type = PKT_HASH_TYPE_L3; 1827 skb_set_hash(skb, le32_to_cpu(rxcmp->rx_cmp_rss_hash), type); 1828 } 1829 1830 cfa_code = RX_CMP_CFA_CODE(rxcmp1); 1831 skb->protocol = eth_type_trans(skb, bnxt_get_pkt_dev(bp, cfa_code)); 1832 1833 if ((rxcmp1->rx_cmp_flags2 & 1834 cpu_to_le32(RX_CMP_FLAGS2_META_FORMAT_VLAN)) && 1835 (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) { 1836 u32 meta_data = le32_to_cpu(rxcmp1->rx_cmp_meta_data); 1837 u16 vtag = meta_data & RX_CMP_FLAGS2_METADATA_TCI_MASK; 1838 u16 vlan_proto = meta_data >> RX_CMP_FLAGS2_METADATA_TPID_SFT; 1839 1840 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag); 1841 } 1842 1843 skb_checksum_none_assert(skb); 1844 if (RX_CMP_L4_CS_OK(rxcmp1)) { 1845 if (dev->features & NETIF_F_RXCSUM) { 1846 skb->ip_summed = CHECKSUM_UNNECESSARY; 1847 skb->csum_level = RX_CMP_ENCAP(rxcmp1); 1848 } 1849 } else { 1850 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS) { 1851 if (dev->features & NETIF_F_RXCSUM) 1852 bnapi->cp_ring.rx_l4_csum_errors++; 1853 } 1854 } 1855 1856 bnxt_deliver_skb(bp, bnapi, skb); 1857 rc = 1; 1858 1859 next_rx: 1860 cpr->rx_packets += 1; 1861 cpr->rx_bytes += len; 1862 1863 next_rx_no_len: 1864 rxr->rx_prod = NEXT_RX(prod); 1865 rxr->rx_next_cons = NEXT_RX(cons); 1866 1867 next_rx_no_prod_no_len: 1868 *raw_cons = tmp_raw_cons; 1869 1870 return rc; 1871 } 1872 1873 /* In netpoll mode, if we are using a combined completion ring, we need to 1874 * discard the rx packets and recycle the buffers. 1875 */ 1876 static int bnxt_force_rx_discard(struct bnxt *bp, 1877 struct bnxt_cp_ring_info *cpr, 1878 u32 *raw_cons, u8 *event) 1879 { 1880 u32 tmp_raw_cons = *raw_cons; 1881 struct rx_cmp_ext *rxcmp1; 1882 struct rx_cmp *rxcmp; 1883 u16 cp_cons; 1884 u8 cmp_type; 1885 1886 cp_cons = RING_CMP(tmp_raw_cons); 1887 rxcmp = (struct rx_cmp *) 1888 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 1889 1890 tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons); 1891 cp_cons = RING_CMP(tmp_raw_cons); 1892 rxcmp1 = (struct rx_cmp_ext *) 1893 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 1894 1895 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons)) 1896 return -EBUSY; 1897 1898 cmp_type = RX_CMP_TYPE(rxcmp); 1899 if (cmp_type == CMP_TYPE_RX_L2_CMP) { 1900 rxcmp1->rx_cmp_cfa_code_errors_v2 |= 1901 cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR); 1902 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) { 1903 struct rx_tpa_end_cmp_ext *tpa_end1; 1904 1905 tpa_end1 = (struct rx_tpa_end_cmp_ext *)rxcmp1; 1906 tpa_end1->rx_tpa_end_cmp_errors_v2 |= 1907 cpu_to_le32(RX_TPA_END_CMP_ERRORS); 1908 } 1909 return bnxt_rx_pkt(bp, cpr, raw_cons, event); 1910 } 1911 1912 u32 bnxt_fw_health_readl(struct bnxt *bp, int reg_idx) 1913 { 1914 struct bnxt_fw_health *fw_health = bp->fw_health; 1915 u32 reg = fw_health->regs[reg_idx]; 1916 u32 reg_type, reg_off, val = 0; 1917 1918 reg_type = BNXT_FW_HEALTH_REG_TYPE(reg); 1919 reg_off = BNXT_FW_HEALTH_REG_OFF(reg); 1920 switch (reg_type) { 1921 case BNXT_FW_HEALTH_REG_TYPE_CFG: 1922 pci_read_config_dword(bp->pdev, reg_off, &val); 1923 break; 1924 case BNXT_FW_HEALTH_REG_TYPE_GRC: 1925 reg_off = fw_health->mapped_regs[reg_idx]; 1926 /* fall through */ 1927 case BNXT_FW_HEALTH_REG_TYPE_BAR0: 1928 val = readl(bp->bar0 + reg_off); 1929 break; 1930 case BNXT_FW_HEALTH_REG_TYPE_BAR1: 1931 val = readl(bp->bar1 + reg_off); 1932 break; 1933 } 1934 if (reg_idx == BNXT_FW_RESET_INPROG_REG) 1935 val &= fw_health->fw_reset_inprog_reg_mask; 1936 return val; 1937 } 1938 1939 #define BNXT_GET_EVENT_PORT(data) \ 1940 ((data) & \ 1941 ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK) 1942 1943 static int bnxt_async_event_process(struct bnxt *bp, 1944 struct hwrm_async_event_cmpl *cmpl) 1945 { 1946 u16 event_id = le16_to_cpu(cmpl->event_id); 1947 1948 /* TODO CHIMP_FW: Define event id's for link change, error etc */ 1949 switch (event_id) { 1950 case ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE: { 1951 u32 data1 = le32_to_cpu(cmpl->event_data1); 1952 struct bnxt_link_info *link_info = &bp->link_info; 1953 1954 if (BNXT_VF(bp)) 1955 goto async_event_process_exit; 1956 1957 /* print unsupported speed warning in forced speed mode only */ 1958 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED) && 1959 (data1 & 0x20000)) { 1960 u16 fw_speed = link_info->force_link_speed; 1961 u32 speed = bnxt_fw_to_ethtool_speed(fw_speed); 1962 1963 if (speed != SPEED_UNKNOWN) 1964 netdev_warn(bp->dev, "Link speed %d no longer supported\n", 1965 speed); 1966 } 1967 set_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT, &bp->sp_event); 1968 } 1969 /* fall through */ 1970 case ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE: 1971 case ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE: 1972 set_bit(BNXT_LINK_CFG_CHANGE_SP_EVENT, &bp->sp_event); 1973 /* fall through */ 1974 case ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE: 1975 set_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event); 1976 break; 1977 case ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD: 1978 set_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event); 1979 break; 1980 case ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED: { 1981 u32 data1 = le32_to_cpu(cmpl->event_data1); 1982 u16 port_id = BNXT_GET_EVENT_PORT(data1); 1983 1984 if (BNXT_VF(bp)) 1985 break; 1986 1987 if (bp->pf.port_id != port_id) 1988 break; 1989 1990 set_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event); 1991 break; 1992 } 1993 case ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE: 1994 if (BNXT_PF(bp)) 1995 goto async_event_process_exit; 1996 set_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event); 1997 break; 1998 case ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY: { 1999 u32 data1 = le32_to_cpu(cmpl->event_data1); 2000 2001 if (!bp->fw_health) 2002 goto async_event_process_exit; 2003 2004 bp->fw_reset_timestamp = jiffies; 2005 bp->fw_reset_min_dsecs = cmpl->timestamp_lo; 2006 if (!bp->fw_reset_min_dsecs) 2007 bp->fw_reset_min_dsecs = BNXT_DFLT_FW_RST_MIN_DSECS; 2008 bp->fw_reset_max_dsecs = le16_to_cpu(cmpl->timestamp_hi); 2009 if (!bp->fw_reset_max_dsecs) 2010 bp->fw_reset_max_dsecs = BNXT_DFLT_FW_RST_MAX_DSECS; 2011 if (EVENT_DATA1_RESET_NOTIFY_FATAL(data1)) { 2012 netdev_warn(bp->dev, "Firmware fatal reset event received\n"); 2013 set_bit(BNXT_STATE_FW_FATAL_COND, &bp->state); 2014 } else { 2015 netdev_warn(bp->dev, "Firmware non-fatal reset event received, max wait time %d msec\n", 2016 bp->fw_reset_max_dsecs * 100); 2017 } 2018 set_bit(BNXT_FW_RESET_NOTIFY_SP_EVENT, &bp->sp_event); 2019 break; 2020 } 2021 case ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY: { 2022 struct bnxt_fw_health *fw_health = bp->fw_health; 2023 u32 data1 = le32_to_cpu(cmpl->event_data1); 2024 2025 if (!fw_health) 2026 goto async_event_process_exit; 2027 2028 fw_health->enabled = EVENT_DATA1_RECOVERY_ENABLED(data1); 2029 fw_health->master = EVENT_DATA1_RECOVERY_MASTER_FUNC(data1); 2030 if (!fw_health->enabled) 2031 break; 2032 2033 if (netif_msg_drv(bp)) 2034 netdev_info(bp->dev, "Error recovery info: error recovery[%d], master[%d], reset count[0x%x], health status: 0x%x\n", 2035 fw_health->enabled, fw_health->master, 2036 bnxt_fw_health_readl(bp, 2037 BNXT_FW_RESET_CNT_REG), 2038 bnxt_fw_health_readl(bp, 2039 BNXT_FW_HEALTH_REG)); 2040 fw_health->tmr_multiplier = 2041 DIV_ROUND_UP(fw_health->polling_dsecs * HZ, 2042 bp->current_interval * 10); 2043 fw_health->tmr_counter = fw_health->tmr_multiplier; 2044 fw_health->last_fw_heartbeat = 2045 bnxt_fw_health_readl(bp, BNXT_FW_HEARTBEAT_REG); 2046 fw_health->last_fw_reset_cnt = 2047 bnxt_fw_health_readl(bp, BNXT_FW_RESET_CNT_REG); 2048 goto async_event_process_exit; 2049 } 2050 default: 2051 goto async_event_process_exit; 2052 } 2053 bnxt_queue_sp_work(bp); 2054 async_event_process_exit: 2055 bnxt_ulp_async_events(bp, cmpl); 2056 return 0; 2057 } 2058 2059 static int bnxt_hwrm_handler(struct bnxt *bp, struct tx_cmp *txcmp) 2060 { 2061 u16 cmpl_type = TX_CMP_TYPE(txcmp), vf_id, seq_id; 2062 struct hwrm_cmpl *h_cmpl = (struct hwrm_cmpl *)txcmp; 2063 struct hwrm_fwd_req_cmpl *fwd_req_cmpl = 2064 (struct hwrm_fwd_req_cmpl *)txcmp; 2065 2066 switch (cmpl_type) { 2067 case CMPL_BASE_TYPE_HWRM_DONE: 2068 seq_id = le16_to_cpu(h_cmpl->sequence_id); 2069 if (seq_id == bp->hwrm_intr_seq_id) 2070 bp->hwrm_intr_seq_id = (u16)~bp->hwrm_intr_seq_id; 2071 else 2072 netdev_err(bp->dev, "Invalid hwrm seq id %d\n", seq_id); 2073 break; 2074 2075 case CMPL_BASE_TYPE_HWRM_FWD_REQ: 2076 vf_id = le16_to_cpu(fwd_req_cmpl->source_id); 2077 2078 if ((vf_id < bp->pf.first_vf_id) || 2079 (vf_id >= bp->pf.first_vf_id + bp->pf.active_vfs)) { 2080 netdev_err(bp->dev, "Msg contains invalid VF id %x\n", 2081 vf_id); 2082 return -EINVAL; 2083 } 2084 2085 set_bit(vf_id - bp->pf.first_vf_id, bp->pf.vf_event_bmap); 2086 set_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event); 2087 bnxt_queue_sp_work(bp); 2088 break; 2089 2090 case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT: 2091 bnxt_async_event_process(bp, 2092 (struct hwrm_async_event_cmpl *)txcmp); 2093 2094 default: 2095 break; 2096 } 2097 2098 return 0; 2099 } 2100 2101 static irqreturn_t bnxt_msix(int irq, void *dev_instance) 2102 { 2103 struct bnxt_napi *bnapi = dev_instance; 2104 struct bnxt *bp = bnapi->bp; 2105 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 2106 u32 cons = RING_CMP(cpr->cp_raw_cons); 2107 2108 cpr->event_ctr++; 2109 prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]); 2110 napi_schedule(&bnapi->napi); 2111 return IRQ_HANDLED; 2112 } 2113 2114 static inline int bnxt_has_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr) 2115 { 2116 u32 raw_cons = cpr->cp_raw_cons; 2117 u16 cons = RING_CMP(raw_cons); 2118 struct tx_cmp *txcmp; 2119 2120 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]; 2121 2122 return TX_CMP_VALID(txcmp, raw_cons); 2123 } 2124 2125 static irqreturn_t bnxt_inta(int irq, void *dev_instance) 2126 { 2127 struct bnxt_napi *bnapi = dev_instance; 2128 struct bnxt *bp = bnapi->bp; 2129 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 2130 u32 cons = RING_CMP(cpr->cp_raw_cons); 2131 u32 int_status; 2132 2133 prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]); 2134 2135 if (!bnxt_has_work(bp, cpr)) { 2136 int_status = readl(bp->bar0 + BNXT_CAG_REG_LEGACY_INT_STATUS); 2137 /* return if erroneous interrupt */ 2138 if (!(int_status & (0x10000 << cpr->cp_ring_struct.fw_ring_id))) 2139 return IRQ_NONE; 2140 } 2141 2142 /* disable ring IRQ */ 2143 BNXT_CP_DB_IRQ_DIS(cpr->cp_db.doorbell); 2144 2145 /* Return here if interrupt is shared and is disabled. */ 2146 if (unlikely(atomic_read(&bp->intr_sem) != 0)) 2147 return IRQ_HANDLED; 2148 2149 napi_schedule(&bnapi->napi); 2150 return IRQ_HANDLED; 2151 } 2152 2153 static int __bnxt_poll_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, 2154 int budget) 2155 { 2156 struct bnxt_napi *bnapi = cpr->bnapi; 2157 u32 raw_cons = cpr->cp_raw_cons; 2158 u32 cons; 2159 int tx_pkts = 0; 2160 int rx_pkts = 0; 2161 u8 event = 0; 2162 struct tx_cmp *txcmp; 2163 2164 cpr->has_more_work = 0; 2165 cpr->had_work_done = 1; 2166 while (1) { 2167 int rc; 2168 2169 cons = RING_CMP(raw_cons); 2170 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]; 2171 2172 if (!TX_CMP_VALID(txcmp, raw_cons)) 2173 break; 2174 2175 /* The valid test of the entry must be done first before 2176 * reading any further. 2177 */ 2178 dma_rmb(); 2179 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_TX_L2_CMP) { 2180 tx_pkts++; 2181 /* return full budget so NAPI will complete. */ 2182 if (unlikely(tx_pkts > bp->tx_wake_thresh)) { 2183 rx_pkts = budget; 2184 raw_cons = NEXT_RAW_CMP(raw_cons); 2185 if (budget) 2186 cpr->has_more_work = 1; 2187 break; 2188 } 2189 } else if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) { 2190 if (likely(budget)) 2191 rc = bnxt_rx_pkt(bp, cpr, &raw_cons, &event); 2192 else 2193 rc = bnxt_force_rx_discard(bp, cpr, &raw_cons, 2194 &event); 2195 if (likely(rc >= 0)) 2196 rx_pkts += rc; 2197 /* Increment rx_pkts when rc is -ENOMEM to count towards 2198 * the NAPI budget. Otherwise, we may potentially loop 2199 * here forever if we consistently cannot allocate 2200 * buffers. 2201 */ 2202 else if (rc == -ENOMEM && budget) 2203 rx_pkts++; 2204 else if (rc == -EBUSY) /* partial completion */ 2205 break; 2206 } else if (unlikely((TX_CMP_TYPE(txcmp) == 2207 CMPL_BASE_TYPE_HWRM_DONE) || 2208 (TX_CMP_TYPE(txcmp) == 2209 CMPL_BASE_TYPE_HWRM_FWD_REQ) || 2210 (TX_CMP_TYPE(txcmp) == 2211 CMPL_BASE_TYPE_HWRM_ASYNC_EVENT))) { 2212 bnxt_hwrm_handler(bp, txcmp); 2213 } 2214 raw_cons = NEXT_RAW_CMP(raw_cons); 2215 2216 if (rx_pkts && rx_pkts == budget) { 2217 cpr->has_more_work = 1; 2218 break; 2219 } 2220 } 2221 2222 if (event & BNXT_REDIRECT_EVENT) 2223 xdp_do_flush_map(); 2224 2225 if (event & BNXT_TX_EVENT) { 2226 struct bnxt_tx_ring_info *txr = bnapi->tx_ring; 2227 u16 prod = txr->tx_prod; 2228 2229 /* Sync BD data before updating doorbell */ 2230 wmb(); 2231 2232 bnxt_db_write_relaxed(bp, &txr->tx_db, prod); 2233 } 2234 2235 cpr->cp_raw_cons = raw_cons; 2236 bnapi->tx_pkts += tx_pkts; 2237 bnapi->events |= event; 2238 return rx_pkts; 2239 } 2240 2241 static void __bnxt_poll_work_done(struct bnxt *bp, struct bnxt_napi *bnapi) 2242 { 2243 if (bnapi->tx_pkts) { 2244 bnapi->tx_int(bp, bnapi, bnapi->tx_pkts); 2245 bnapi->tx_pkts = 0; 2246 } 2247 2248 if (bnapi->events & BNXT_RX_EVENT) { 2249 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 2250 2251 if (bnapi->events & BNXT_AGG_EVENT) 2252 bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod); 2253 bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod); 2254 } 2255 bnapi->events = 0; 2256 } 2257 2258 static int bnxt_poll_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, 2259 int budget) 2260 { 2261 struct bnxt_napi *bnapi = cpr->bnapi; 2262 int rx_pkts; 2263 2264 rx_pkts = __bnxt_poll_work(bp, cpr, budget); 2265 2266 /* ACK completion ring before freeing tx ring and producing new 2267 * buffers in rx/agg rings to prevent overflowing the completion 2268 * ring. 2269 */ 2270 bnxt_db_cq(bp, &cpr->cp_db, cpr->cp_raw_cons); 2271 2272 __bnxt_poll_work_done(bp, bnapi); 2273 return rx_pkts; 2274 } 2275 2276 static int bnxt_poll_nitroa0(struct napi_struct *napi, int budget) 2277 { 2278 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi); 2279 struct bnxt *bp = bnapi->bp; 2280 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 2281 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 2282 struct tx_cmp *txcmp; 2283 struct rx_cmp_ext *rxcmp1; 2284 u32 cp_cons, tmp_raw_cons; 2285 u32 raw_cons = cpr->cp_raw_cons; 2286 u32 rx_pkts = 0; 2287 u8 event = 0; 2288 2289 while (1) { 2290 int rc; 2291 2292 cp_cons = RING_CMP(raw_cons); 2293 txcmp = &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 2294 2295 if (!TX_CMP_VALID(txcmp, raw_cons)) 2296 break; 2297 2298 if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) { 2299 tmp_raw_cons = NEXT_RAW_CMP(raw_cons); 2300 cp_cons = RING_CMP(tmp_raw_cons); 2301 rxcmp1 = (struct rx_cmp_ext *) 2302 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 2303 2304 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons)) 2305 break; 2306 2307 /* force an error to recycle the buffer */ 2308 rxcmp1->rx_cmp_cfa_code_errors_v2 |= 2309 cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR); 2310 2311 rc = bnxt_rx_pkt(bp, cpr, &raw_cons, &event); 2312 if (likely(rc == -EIO) && budget) 2313 rx_pkts++; 2314 else if (rc == -EBUSY) /* partial completion */ 2315 break; 2316 } else if (unlikely(TX_CMP_TYPE(txcmp) == 2317 CMPL_BASE_TYPE_HWRM_DONE)) { 2318 bnxt_hwrm_handler(bp, txcmp); 2319 } else { 2320 netdev_err(bp->dev, 2321 "Invalid completion received on special ring\n"); 2322 } 2323 raw_cons = NEXT_RAW_CMP(raw_cons); 2324 2325 if (rx_pkts == budget) 2326 break; 2327 } 2328 2329 cpr->cp_raw_cons = raw_cons; 2330 BNXT_DB_CQ(&cpr->cp_db, cpr->cp_raw_cons); 2331 bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod); 2332 2333 if (event & BNXT_AGG_EVENT) 2334 bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod); 2335 2336 if (!bnxt_has_work(bp, cpr) && rx_pkts < budget) { 2337 napi_complete_done(napi, rx_pkts); 2338 BNXT_DB_CQ_ARM(&cpr->cp_db, cpr->cp_raw_cons); 2339 } 2340 return rx_pkts; 2341 } 2342 2343 static int bnxt_poll(struct napi_struct *napi, int budget) 2344 { 2345 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi); 2346 struct bnxt *bp = bnapi->bp; 2347 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 2348 int work_done = 0; 2349 2350 while (1) { 2351 work_done += bnxt_poll_work(bp, cpr, budget - work_done); 2352 2353 if (work_done >= budget) { 2354 if (!budget) 2355 BNXT_DB_CQ_ARM(&cpr->cp_db, cpr->cp_raw_cons); 2356 break; 2357 } 2358 2359 if (!bnxt_has_work(bp, cpr)) { 2360 if (napi_complete_done(napi, work_done)) 2361 BNXT_DB_CQ_ARM(&cpr->cp_db, cpr->cp_raw_cons); 2362 break; 2363 } 2364 } 2365 if (bp->flags & BNXT_FLAG_DIM) { 2366 struct dim_sample dim_sample = {}; 2367 2368 dim_update_sample(cpr->event_ctr, 2369 cpr->rx_packets, 2370 cpr->rx_bytes, 2371 &dim_sample); 2372 net_dim(&cpr->dim, dim_sample); 2373 } 2374 return work_done; 2375 } 2376 2377 static int __bnxt_poll_cqs(struct bnxt *bp, struct bnxt_napi *bnapi, int budget) 2378 { 2379 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 2380 int i, work_done = 0; 2381 2382 for (i = 0; i < 2; i++) { 2383 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[i]; 2384 2385 if (cpr2) { 2386 work_done += __bnxt_poll_work(bp, cpr2, 2387 budget - work_done); 2388 cpr->has_more_work |= cpr2->has_more_work; 2389 } 2390 } 2391 return work_done; 2392 } 2393 2394 static void __bnxt_poll_cqs_done(struct bnxt *bp, struct bnxt_napi *bnapi, 2395 u64 dbr_type) 2396 { 2397 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 2398 int i; 2399 2400 for (i = 0; i < 2; i++) { 2401 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[i]; 2402 struct bnxt_db_info *db; 2403 2404 if (cpr2 && cpr2->had_work_done) { 2405 db = &cpr2->cp_db; 2406 writeq(db->db_key64 | dbr_type | 2407 RING_CMP(cpr2->cp_raw_cons), db->doorbell); 2408 cpr2->had_work_done = 0; 2409 } 2410 } 2411 __bnxt_poll_work_done(bp, bnapi); 2412 } 2413 2414 static int bnxt_poll_p5(struct napi_struct *napi, int budget) 2415 { 2416 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi); 2417 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 2418 u32 raw_cons = cpr->cp_raw_cons; 2419 struct bnxt *bp = bnapi->bp; 2420 struct nqe_cn *nqcmp; 2421 int work_done = 0; 2422 u32 cons; 2423 2424 if (cpr->has_more_work) { 2425 cpr->has_more_work = 0; 2426 work_done = __bnxt_poll_cqs(bp, bnapi, budget); 2427 } 2428 while (1) { 2429 cons = RING_CMP(raw_cons); 2430 nqcmp = &cpr->nq_desc_ring[CP_RING(cons)][CP_IDX(cons)]; 2431 2432 if (!NQ_CMP_VALID(nqcmp, raw_cons)) { 2433 if (cpr->has_more_work) 2434 break; 2435 2436 __bnxt_poll_cqs_done(bp, bnapi, DBR_TYPE_CQ_ARMALL); 2437 cpr->cp_raw_cons = raw_cons; 2438 if (napi_complete_done(napi, work_done)) 2439 BNXT_DB_NQ_ARM_P5(&cpr->cp_db, 2440 cpr->cp_raw_cons); 2441 return work_done; 2442 } 2443 2444 /* The valid test of the entry must be done first before 2445 * reading any further. 2446 */ 2447 dma_rmb(); 2448 2449 if (nqcmp->type == cpu_to_le16(NQ_CN_TYPE_CQ_NOTIFICATION)) { 2450 u32 idx = le32_to_cpu(nqcmp->cq_handle_low); 2451 struct bnxt_cp_ring_info *cpr2; 2452 2453 cpr2 = cpr->cp_ring_arr[idx]; 2454 work_done += __bnxt_poll_work(bp, cpr2, 2455 budget - work_done); 2456 cpr->has_more_work |= cpr2->has_more_work; 2457 } else { 2458 bnxt_hwrm_handler(bp, (struct tx_cmp *)nqcmp); 2459 } 2460 raw_cons = NEXT_RAW_CMP(raw_cons); 2461 } 2462 __bnxt_poll_cqs_done(bp, bnapi, DBR_TYPE_CQ); 2463 if (raw_cons != cpr->cp_raw_cons) { 2464 cpr->cp_raw_cons = raw_cons; 2465 BNXT_DB_NQ_P5(&cpr->cp_db, raw_cons); 2466 } 2467 return work_done; 2468 } 2469 2470 static void bnxt_free_tx_skbs(struct bnxt *bp) 2471 { 2472 int i, max_idx; 2473 struct pci_dev *pdev = bp->pdev; 2474 2475 if (!bp->tx_ring) 2476 return; 2477 2478 max_idx = bp->tx_nr_pages * TX_DESC_CNT; 2479 for (i = 0; i < bp->tx_nr_rings; i++) { 2480 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; 2481 int j; 2482 2483 for (j = 0; j < max_idx;) { 2484 struct bnxt_sw_tx_bd *tx_buf = &txr->tx_buf_ring[j]; 2485 struct sk_buff *skb; 2486 int k, last; 2487 2488 if (i < bp->tx_nr_rings_xdp && 2489 tx_buf->action == XDP_REDIRECT) { 2490 dma_unmap_single(&pdev->dev, 2491 dma_unmap_addr(tx_buf, mapping), 2492 dma_unmap_len(tx_buf, len), 2493 PCI_DMA_TODEVICE); 2494 xdp_return_frame(tx_buf->xdpf); 2495 tx_buf->action = 0; 2496 tx_buf->xdpf = NULL; 2497 j++; 2498 continue; 2499 } 2500 2501 skb = tx_buf->skb; 2502 if (!skb) { 2503 j++; 2504 continue; 2505 } 2506 2507 tx_buf->skb = NULL; 2508 2509 if (tx_buf->is_push) { 2510 dev_kfree_skb(skb); 2511 j += 2; 2512 continue; 2513 } 2514 2515 dma_unmap_single(&pdev->dev, 2516 dma_unmap_addr(tx_buf, mapping), 2517 skb_headlen(skb), 2518 PCI_DMA_TODEVICE); 2519 2520 last = tx_buf->nr_frags; 2521 j += 2; 2522 for (k = 0; k < last; k++, j++) { 2523 int ring_idx = j & bp->tx_ring_mask; 2524 skb_frag_t *frag = &skb_shinfo(skb)->frags[k]; 2525 2526 tx_buf = &txr->tx_buf_ring[ring_idx]; 2527 dma_unmap_page( 2528 &pdev->dev, 2529 dma_unmap_addr(tx_buf, mapping), 2530 skb_frag_size(frag), PCI_DMA_TODEVICE); 2531 } 2532 dev_kfree_skb(skb); 2533 } 2534 netdev_tx_reset_queue(netdev_get_tx_queue(bp->dev, i)); 2535 } 2536 } 2537 2538 static void bnxt_free_rx_skbs(struct bnxt *bp) 2539 { 2540 int i, max_idx, max_agg_idx; 2541 struct pci_dev *pdev = bp->pdev; 2542 2543 if (!bp->rx_ring) 2544 return; 2545 2546 max_idx = bp->rx_nr_pages * RX_DESC_CNT; 2547 max_agg_idx = bp->rx_agg_nr_pages * RX_DESC_CNT; 2548 for (i = 0; i < bp->rx_nr_rings; i++) { 2549 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 2550 struct bnxt_tpa_idx_map *map; 2551 int j; 2552 2553 if (rxr->rx_tpa) { 2554 for (j = 0; j < bp->max_tpa; j++) { 2555 struct bnxt_tpa_info *tpa_info = 2556 &rxr->rx_tpa[j]; 2557 u8 *data = tpa_info->data; 2558 2559 if (!data) 2560 continue; 2561 2562 dma_unmap_single_attrs(&pdev->dev, 2563 tpa_info->mapping, 2564 bp->rx_buf_use_size, 2565 bp->rx_dir, 2566 DMA_ATTR_WEAK_ORDERING); 2567 2568 tpa_info->data = NULL; 2569 2570 kfree(data); 2571 } 2572 } 2573 2574 for (j = 0; j < max_idx; j++) { 2575 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[j]; 2576 dma_addr_t mapping = rx_buf->mapping; 2577 void *data = rx_buf->data; 2578 2579 if (!data) 2580 continue; 2581 2582 rx_buf->data = NULL; 2583 2584 if (BNXT_RX_PAGE_MODE(bp)) { 2585 mapping -= bp->rx_dma_offset; 2586 dma_unmap_page_attrs(&pdev->dev, mapping, 2587 PAGE_SIZE, bp->rx_dir, 2588 DMA_ATTR_WEAK_ORDERING); 2589 page_pool_recycle_direct(rxr->page_pool, data); 2590 } else { 2591 dma_unmap_single_attrs(&pdev->dev, mapping, 2592 bp->rx_buf_use_size, 2593 bp->rx_dir, 2594 DMA_ATTR_WEAK_ORDERING); 2595 kfree(data); 2596 } 2597 } 2598 2599 for (j = 0; j < max_agg_idx; j++) { 2600 struct bnxt_sw_rx_agg_bd *rx_agg_buf = 2601 &rxr->rx_agg_ring[j]; 2602 struct page *page = rx_agg_buf->page; 2603 2604 if (!page) 2605 continue; 2606 2607 dma_unmap_page_attrs(&pdev->dev, rx_agg_buf->mapping, 2608 BNXT_RX_PAGE_SIZE, 2609 PCI_DMA_FROMDEVICE, 2610 DMA_ATTR_WEAK_ORDERING); 2611 2612 rx_agg_buf->page = NULL; 2613 __clear_bit(j, rxr->rx_agg_bmap); 2614 2615 __free_page(page); 2616 } 2617 if (rxr->rx_page) { 2618 __free_page(rxr->rx_page); 2619 rxr->rx_page = NULL; 2620 } 2621 map = rxr->rx_tpa_idx_map; 2622 if (map) 2623 memset(map->agg_idx_bmap, 0, sizeof(map->agg_idx_bmap)); 2624 } 2625 } 2626 2627 static void bnxt_free_skbs(struct bnxt *bp) 2628 { 2629 bnxt_free_tx_skbs(bp); 2630 bnxt_free_rx_skbs(bp); 2631 } 2632 2633 static void bnxt_free_ring(struct bnxt *bp, struct bnxt_ring_mem_info *rmem) 2634 { 2635 struct pci_dev *pdev = bp->pdev; 2636 int i; 2637 2638 for (i = 0; i < rmem->nr_pages; i++) { 2639 if (!rmem->pg_arr[i]) 2640 continue; 2641 2642 dma_free_coherent(&pdev->dev, rmem->page_size, 2643 rmem->pg_arr[i], rmem->dma_arr[i]); 2644 2645 rmem->pg_arr[i] = NULL; 2646 } 2647 if (rmem->pg_tbl) { 2648 size_t pg_tbl_size = rmem->nr_pages * 8; 2649 2650 if (rmem->flags & BNXT_RMEM_USE_FULL_PAGE_FLAG) 2651 pg_tbl_size = rmem->page_size; 2652 dma_free_coherent(&pdev->dev, pg_tbl_size, 2653 rmem->pg_tbl, rmem->pg_tbl_map); 2654 rmem->pg_tbl = NULL; 2655 } 2656 if (rmem->vmem_size && *rmem->vmem) { 2657 vfree(*rmem->vmem); 2658 *rmem->vmem = NULL; 2659 } 2660 } 2661 2662 static int bnxt_alloc_ring(struct bnxt *bp, struct bnxt_ring_mem_info *rmem) 2663 { 2664 struct pci_dev *pdev = bp->pdev; 2665 u64 valid_bit = 0; 2666 int i; 2667 2668 if (rmem->flags & (BNXT_RMEM_VALID_PTE_FLAG | BNXT_RMEM_RING_PTE_FLAG)) 2669 valid_bit = PTU_PTE_VALID; 2670 if ((rmem->nr_pages > 1 || rmem->depth > 0) && !rmem->pg_tbl) { 2671 size_t pg_tbl_size = rmem->nr_pages * 8; 2672 2673 if (rmem->flags & BNXT_RMEM_USE_FULL_PAGE_FLAG) 2674 pg_tbl_size = rmem->page_size; 2675 rmem->pg_tbl = dma_alloc_coherent(&pdev->dev, pg_tbl_size, 2676 &rmem->pg_tbl_map, 2677 GFP_KERNEL); 2678 if (!rmem->pg_tbl) 2679 return -ENOMEM; 2680 } 2681 2682 for (i = 0; i < rmem->nr_pages; i++) { 2683 u64 extra_bits = valid_bit; 2684 2685 rmem->pg_arr[i] = dma_alloc_coherent(&pdev->dev, 2686 rmem->page_size, 2687 &rmem->dma_arr[i], 2688 GFP_KERNEL); 2689 if (!rmem->pg_arr[i]) 2690 return -ENOMEM; 2691 2692 if (rmem->init_val) 2693 memset(rmem->pg_arr[i], rmem->init_val, 2694 rmem->page_size); 2695 if (rmem->nr_pages > 1 || rmem->depth > 0) { 2696 if (i == rmem->nr_pages - 2 && 2697 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG)) 2698 extra_bits |= PTU_PTE_NEXT_TO_LAST; 2699 else if (i == rmem->nr_pages - 1 && 2700 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG)) 2701 extra_bits |= PTU_PTE_LAST; 2702 rmem->pg_tbl[i] = 2703 cpu_to_le64(rmem->dma_arr[i] | extra_bits); 2704 } 2705 } 2706 2707 if (rmem->vmem_size) { 2708 *rmem->vmem = vzalloc(rmem->vmem_size); 2709 if (!(*rmem->vmem)) 2710 return -ENOMEM; 2711 } 2712 return 0; 2713 } 2714 2715 static void bnxt_free_tpa_info(struct bnxt *bp) 2716 { 2717 int i; 2718 2719 for (i = 0; i < bp->rx_nr_rings; i++) { 2720 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 2721 2722 kfree(rxr->rx_tpa_idx_map); 2723 rxr->rx_tpa_idx_map = NULL; 2724 if (rxr->rx_tpa) { 2725 kfree(rxr->rx_tpa[0].agg_arr); 2726 rxr->rx_tpa[0].agg_arr = NULL; 2727 } 2728 kfree(rxr->rx_tpa); 2729 rxr->rx_tpa = NULL; 2730 } 2731 } 2732 2733 static int bnxt_alloc_tpa_info(struct bnxt *bp) 2734 { 2735 int i, j, total_aggs = 0; 2736 2737 bp->max_tpa = MAX_TPA; 2738 if (bp->flags & BNXT_FLAG_CHIP_P5) { 2739 if (!bp->max_tpa_v2) 2740 return 0; 2741 bp->max_tpa = max_t(u16, bp->max_tpa_v2, MAX_TPA_P5); 2742 total_aggs = bp->max_tpa * MAX_SKB_FRAGS; 2743 } 2744 2745 for (i = 0; i < bp->rx_nr_rings; i++) { 2746 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 2747 struct rx_agg_cmp *agg; 2748 2749 rxr->rx_tpa = kcalloc(bp->max_tpa, sizeof(struct bnxt_tpa_info), 2750 GFP_KERNEL); 2751 if (!rxr->rx_tpa) 2752 return -ENOMEM; 2753 2754 if (!(bp->flags & BNXT_FLAG_CHIP_P5)) 2755 continue; 2756 agg = kcalloc(total_aggs, sizeof(*agg), GFP_KERNEL); 2757 rxr->rx_tpa[0].agg_arr = agg; 2758 if (!agg) 2759 return -ENOMEM; 2760 for (j = 1; j < bp->max_tpa; j++) 2761 rxr->rx_tpa[j].agg_arr = agg + j * MAX_SKB_FRAGS; 2762 rxr->rx_tpa_idx_map = kzalloc(sizeof(*rxr->rx_tpa_idx_map), 2763 GFP_KERNEL); 2764 if (!rxr->rx_tpa_idx_map) 2765 return -ENOMEM; 2766 } 2767 return 0; 2768 } 2769 2770 static void bnxt_free_rx_rings(struct bnxt *bp) 2771 { 2772 int i; 2773 2774 if (!bp->rx_ring) 2775 return; 2776 2777 bnxt_free_tpa_info(bp); 2778 for (i = 0; i < bp->rx_nr_rings; i++) { 2779 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 2780 struct bnxt_ring_struct *ring; 2781 2782 if (rxr->xdp_prog) 2783 bpf_prog_put(rxr->xdp_prog); 2784 2785 if (xdp_rxq_info_is_reg(&rxr->xdp_rxq)) 2786 xdp_rxq_info_unreg(&rxr->xdp_rxq); 2787 2788 page_pool_destroy(rxr->page_pool); 2789 rxr->page_pool = NULL; 2790 2791 kfree(rxr->rx_agg_bmap); 2792 rxr->rx_agg_bmap = NULL; 2793 2794 ring = &rxr->rx_ring_struct; 2795 bnxt_free_ring(bp, &ring->ring_mem); 2796 2797 ring = &rxr->rx_agg_ring_struct; 2798 bnxt_free_ring(bp, &ring->ring_mem); 2799 } 2800 } 2801 2802 static int bnxt_alloc_rx_page_pool(struct bnxt *bp, 2803 struct bnxt_rx_ring_info *rxr) 2804 { 2805 struct page_pool_params pp = { 0 }; 2806 2807 pp.pool_size = bp->rx_ring_size; 2808 pp.nid = dev_to_node(&bp->pdev->dev); 2809 pp.dev = &bp->pdev->dev; 2810 pp.dma_dir = DMA_BIDIRECTIONAL; 2811 2812 rxr->page_pool = page_pool_create(&pp); 2813 if (IS_ERR(rxr->page_pool)) { 2814 int err = PTR_ERR(rxr->page_pool); 2815 2816 rxr->page_pool = NULL; 2817 return err; 2818 } 2819 return 0; 2820 } 2821 2822 static int bnxt_alloc_rx_rings(struct bnxt *bp) 2823 { 2824 int i, rc = 0, agg_rings = 0; 2825 2826 if (!bp->rx_ring) 2827 return -ENOMEM; 2828 2829 if (bp->flags & BNXT_FLAG_AGG_RINGS) 2830 agg_rings = 1; 2831 2832 for (i = 0; i < bp->rx_nr_rings; i++) { 2833 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 2834 struct bnxt_ring_struct *ring; 2835 2836 ring = &rxr->rx_ring_struct; 2837 2838 rc = bnxt_alloc_rx_page_pool(bp, rxr); 2839 if (rc) 2840 return rc; 2841 2842 rc = xdp_rxq_info_reg(&rxr->xdp_rxq, bp->dev, i); 2843 if (rc < 0) 2844 return rc; 2845 2846 rc = xdp_rxq_info_reg_mem_model(&rxr->xdp_rxq, 2847 MEM_TYPE_PAGE_POOL, 2848 rxr->page_pool); 2849 if (rc) { 2850 xdp_rxq_info_unreg(&rxr->xdp_rxq); 2851 return rc; 2852 } 2853 2854 rc = bnxt_alloc_ring(bp, &ring->ring_mem); 2855 if (rc) 2856 return rc; 2857 2858 ring->grp_idx = i; 2859 if (agg_rings) { 2860 u16 mem_size; 2861 2862 ring = &rxr->rx_agg_ring_struct; 2863 rc = bnxt_alloc_ring(bp, &ring->ring_mem); 2864 if (rc) 2865 return rc; 2866 2867 ring->grp_idx = i; 2868 rxr->rx_agg_bmap_size = bp->rx_agg_ring_mask + 1; 2869 mem_size = rxr->rx_agg_bmap_size / 8; 2870 rxr->rx_agg_bmap = kzalloc(mem_size, GFP_KERNEL); 2871 if (!rxr->rx_agg_bmap) 2872 return -ENOMEM; 2873 } 2874 } 2875 if (bp->flags & BNXT_FLAG_TPA) 2876 rc = bnxt_alloc_tpa_info(bp); 2877 return rc; 2878 } 2879 2880 static void bnxt_free_tx_rings(struct bnxt *bp) 2881 { 2882 int i; 2883 struct pci_dev *pdev = bp->pdev; 2884 2885 if (!bp->tx_ring) 2886 return; 2887 2888 for (i = 0; i < bp->tx_nr_rings; i++) { 2889 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; 2890 struct bnxt_ring_struct *ring; 2891 2892 if (txr->tx_push) { 2893 dma_free_coherent(&pdev->dev, bp->tx_push_size, 2894 txr->tx_push, txr->tx_push_mapping); 2895 txr->tx_push = NULL; 2896 } 2897 2898 ring = &txr->tx_ring_struct; 2899 2900 bnxt_free_ring(bp, &ring->ring_mem); 2901 } 2902 } 2903 2904 static int bnxt_alloc_tx_rings(struct bnxt *bp) 2905 { 2906 int i, j, rc; 2907 struct pci_dev *pdev = bp->pdev; 2908 2909 bp->tx_push_size = 0; 2910 if (bp->tx_push_thresh) { 2911 int push_size; 2912 2913 push_size = L1_CACHE_ALIGN(sizeof(struct tx_push_bd) + 2914 bp->tx_push_thresh); 2915 2916 if (push_size > 256) { 2917 push_size = 0; 2918 bp->tx_push_thresh = 0; 2919 } 2920 2921 bp->tx_push_size = push_size; 2922 } 2923 2924 for (i = 0, j = 0; i < bp->tx_nr_rings; i++) { 2925 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; 2926 struct bnxt_ring_struct *ring; 2927 u8 qidx; 2928 2929 ring = &txr->tx_ring_struct; 2930 2931 rc = bnxt_alloc_ring(bp, &ring->ring_mem); 2932 if (rc) 2933 return rc; 2934 2935 ring->grp_idx = txr->bnapi->index; 2936 if (bp->tx_push_size) { 2937 dma_addr_t mapping; 2938 2939 /* One pre-allocated DMA buffer to backup 2940 * TX push operation 2941 */ 2942 txr->tx_push = dma_alloc_coherent(&pdev->dev, 2943 bp->tx_push_size, 2944 &txr->tx_push_mapping, 2945 GFP_KERNEL); 2946 2947 if (!txr->tx_push) 2948 return -ENOMEM; 2949 2950 mapping = txr->tx_push_mapping + 2951 sizeof(struct tx_push_bd); 2952 txr->data_mapping = cpu_to_le64(mapping); 2953 } 2954 qidx = bp->tc_to_qidx[j]; 2955 ring->queue_id = bp->q_info[qidx].queue_id; 2956 if (i < bp->tx_nr_rings_xdp) 2957 continue; 2958 if (i % bp->tx_nr_rings_per_tc == (bp->tx_nr_rings_per_tc - 1)) 2959 j++; 2960 } 2961 return 0; 2962 } 2963 2964 static void bnxt_free_cp_rings(struct bnxt *bp) 2965 { 2966 int i; 2967 2968 if (!bp->bnapi) 2969 return; 2970 2971 for (i = 0; i < bp->cp_nr_rings; i++) { 2972 struct bnxt_napi *bnapi = bp->bnapi[i]; 2973 struct bnxt_cp_ring_info *cpr; 2974 struct bnxt_ring_struct *ring; 2975 int j; 2976 2977 if (!bnapi) 2978 continue; 2979 2980 cpr = &bnapi->cp_ring; 2981 ring = &cpr->cp_ring_struct; 2982 2983 bnxt_free_ring(bp, &ring->ring_mem); 2984 2985 for (j = 0; j < 2; j++) { 2986 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j]; 2987 2988 if (cpr2) { 2989 ring = &cpr2->cp_ring_struct; 2990 bnxt_free_ring(bp, &ring->ring_mem); 2991 kfree(cpr2); 2992 cpr->cp_ring_arr[j] = NULL; 2993 } 2994 } 2995 } 2996 } 2997 2998 static struct bnxt_cp_ring_info *bnxt_alloc_cp_sub_ring(struct bnxt *bp) 2999 { 3000 struct bnxt_ring_mem_info *rmem; 3001 struct bnxt_ring_struct *ring; 3002 struct bnxt_cp_ring_info *cpr; 3003 int rc; 3004 3005 cpr = kzalloc(sizeof(*cpr), GFP_KERNEL); 3006 if (!cpr) 3007 return NULL; 3008 3009 ring = &cpr->cp_ring_struct; 3010 rmem = &ring->ring_mem; 3011 rmem->nr_pages = bp->cp_nr_pages; 3012 rmem->page_size = HW_CMPD_RING_SIZE; 3013 rmem->pg_arr = (void **)cpr->cp_desc_ring; 3014 rmem->dma_arr = cpr->cp_desc_mapping; 3015 rmem->flags = BNXT_RMEM_RING_PTE_FLAG; 3016 rc = bnxt_alloc_ring(bp, rmem); 3017 if (rc) { 3018 bnxt_free_ring(bp, rmem); 3019 kfree(cpr); 3020 cpr = NULL; 3021 } 3022 return cpr; 3023 } 3024 3025 static int bnxt_alloc_cp_rings(struct bnxt *bp) 3026 { 3027 bool sh = !!(bp->flags & BNXT_FLAG_SHARED_RINGS); 3028 int i, rc, ulp_base_vec, ulp_msix; 3029 3030 ulp_msix = bnxt_get_ulp_msix_num(bp); 3031 ulp_base_vec = bnxt_get_ulp_msix_base(bp); 3032 for (i = 0; i < bp->cp_nr_rings; i++) { 3033 struct bnxt_napi *bnapi = bp->bnapi[i]; 3034 struct bnxt_cp_ring_info *cpr; 3035 struct bnxt_ring_struct *ring; 3036 3037 if (!bnapi) 3038 continue; 3039 3040 cpr = &bnapi->cp_ring; 3041 cpr->bnapi = bnapi; 3042 ring = &cpr->cp_ring_struct; 3043 3044 rc = bnxt_alloc_ring(bp, &ring->ring_mem); 3045 if (rc) 3046 return rc; 3047 3048 if (ulp_msix && i >= ulp_base_vec) 3049 ring->map_idx = i + ulp_msix; 3050 else 3051 ring->map_idx = i; 3052 3053 if (!(bp->flags & BNXT_FLAG_CHIP_P5)) 3054 continue; 3055 3056 if (i < bp->rx_nr_rings) { 3057 struct bnxt_cp_ring_info *cpr2 = 3058 bnxt_alloc_cp_sub_ring(bp); 3059 3060 cpr->cp_ring_arr[BNXT_RX_HDL] = cpr2; 3061 if (!cpr2) 3062 return -ENOMEM; 3063 cpr2->bnapi = bnapi; 3064 } 3065 if ((sh && i < bp->tx_nr_rings) || 3066 (!sh && i >= bp->rx_nr_rings)) { 3067 struct bnxt_cp_ring_info *cpr2 = 3068 bnxt_alloc_cp_sub_ring(bp); 3069 3070 cpr->cp_ring_arr[BNXT_TX_HDL] = cpr2; 3071 if (!cpr2) 3072 return -ENOMEM; 3073 cpr2->bnapi = bnapi; 3074 } 3075 } 3076 return 0; 3077 } 3078 3079 static void bnxt_init_ring_struct(struct bnxt *bp) 3080 { 3081 int i; 3082 3083 for (i = 0; i < bp->cp_nr_rings; i++) { 3084 struct bnxt_napi *bnapi = bp->bnapi[i]; 3085 struct bnxt_ring_mem_info *rmem; 3086 struct bnxt_cp_ring_info *cpr; 3087 struct bnxt_rx_ring_info *rxr; 3088 struct bnxt_tx_ring_info *txr; 3089 struct bnxt_ring_struct *ring; 3090 3091 if (!bnapi) 3092 continue; 3093 3094 cpr = &bnapi->cp_ring; 3095 ring = &cpr->cp_ring_struct; 3096 rmem = &ring->ring_mem; 3097 rmem->nr_pages = bp->cp_nr_pages; 3098 rmem->page_size = HW_CMPD_RING_SIZE; 3099 rmem->pg_arr = (void **)cpr->cp_desc_ring; 3100 rmem->dma_arr = cpr->cp_desc_mapping; 3101 rmem->vmem_size = 0; 3102 3103 rxr = bnapi->rx_ring; 3104 if (!rxr) 3105 goto skip_rx; 3106 3107 ring = &rxr->rx_ring_struct; 3108 rmem = &ring->ring_mem; 3109 rmem->nr_pages = bp->rx_nr_pages; 3110 rmem->page_size = HW_RXBD_RING_SIZE; 3111 rmem->pg_arr = (void **)rxr->rx_desc_ring; 3112 rmem->dma_arr = rxr->rx_desc_mapping; 3113 rmem->vmem_size = SW_RXBD_RING_SIZE * bp->rx_nr_pages; 3114 rmem->vmem = (void **)&rxr->rx_buf_ring; 3115 3116 ring = &rxr->rx_agg_ring_struct; 3117 rmem = &ring->ring_mem; 3118 rmem->nr_pages = bp->rx_agg_nr_pages; 3119 rmem->page_size = HW_RXBD_RING_SIZE; 3120 rmem->pg_arr = (void **)rxr->rx_agg_desc_ring; 3121 rmem->dma_arr = rxr->rx_agg_desc_mapping; 3122 rmem->vmem_size = SW_RXBD_AGG_RING_SIZE * bp->rx_agg_nr_pages; 3123 rmem->vmem = (void **)&rxr->rx_agg_ring; 3124 3125 skip_rx: 3126 txr = bnapi->tx_ring; 3127 if (!txr) 3128 continue; 3129 3130 ring = &txr->tx_ring_struct; 3131 rmem = &ring->ring_mem; 3132 rmem->nr_pages = bp->tx_nr_pages; 3133 rmem->page_size = HW_RXBD_RING_SIZE; 3134 rmem->pg_arr = (void **)txr->tx_desc_ring; 3135 rmem->dma_arr = txr->tx_desc_mapping; 3136 rmem->vmem_size = SW_TXBD_RING_SIZE * bp->tx_nr_pages; 3137 rmem->vmem = (void **)&txr->tx_buf_ring; 3138 } 3139 } 3140 3141 static void bnxt_init_rxbd_pages(struct bnxt_ring_struct *ring, u32 type) 3142 { 3143 int i; 3144 u32 prod; 3145 struct rx_bd **rx_buf_ring; 3146 3147 rx_buf_ring = (struct rx_bd **)ring->ring_mem.pg_arr; 3148 for (i = 0, prod = 0; i < ring->ring_mem.nr_pages; i++) { 3149 int j; 3150 struct rx_bd *rxbd; 3151 3152 rxbd = rx_buf_ring[i]; 3153 if (!rxbd) 3154 continue; 3155 3156 for (j = 0; j < RX_DESC_CNT; j++, rxbd++, prod++) { 3157 rxbd->rx_bd_len_flags_type = cpu_to_le32(type); 3158 rxbd->rx_bd_opaque = prod; 3159 } 3160 } 3161 } 3162 3163 static int bnxt_init_one_rx_ring(struct bnxt *bp, int ring_nr) 3164 { 3165 struct net_device *dev = bp->dev; 3166 struct bnxt_rx_ring_info *rxr; 3167 struct bnxt_ring_struct *ring; 3168 u32 prod, type; 3169 int i; 3170 3171 type = (bp->rx_buf_use_size << RX_BD_LEN_SHIFT) | 3172 RX_BD_TYPE_RX_PACKET_BD | RX_BD_FLAGS_EOP; 3173 3174 if (NET_IP_ALIGN == 2) 3175 type |= RX_BD_FLAGS_SOP; 3176 3177 rxr = &bp->rx_ring[ring_nr]; 3178 ring = &rxr->rx_ring_struct; 3179 bnxt_init_rxbd_pages(ring, type); 3180 3181 if (BNXT_RX_PAGE_MODE(bp) && bp->xdp_prog) { 3182 bpf_prog_add(bp->xdp_prog, 1); 3183 rxr->xdp_prog = bp->xdp_prog; 3184 } 3185 prod = rxr->rx_prod; 3186 for (i = 0; i < bp->rx_ring_size; i++) { 3187 if (bnxt_alloc_rx_data(bp, rxr, prod, GFP_KERNEL) != 0) { 3188 netdev_warn(dev, "init'ed rx ring %d with %d/%d skbs only\n", 3189 ring_nr, i, bp->rx_ring_size); 3190 break; 3191 } 3192 prod = NEXT_RX(prod); 3193 } 3194 rxr->rx_prod = prod; 3195 ring->fw_ring_id = INVALID_HW_RING_ID; 3196 3197 ring = &rxr->rx_agg_ring_struct; 3198 ring->fw_ring_id = INVALID_HW_RING_ID; 3199 3200 if (!(bp->flags & BNXT_FLAG_AGG_RINGS)) 3201 return 0; 3202 3203 type = ((u32)BNXT_RX_PAGE_SIZE << RX_BD_LEN_SHIFT) | 3204 RX_BD_TYPE_RX_AGG_BD | RX_BD_FLAGS_SOP; 3205 3206 bnxt_init_rxbd_pages(ring, type); 3207 3208 prod = rxr->rx_agg_prod; 3209 for (i = 0; i < bp->rx_agg_ring_size; i++) { 3210 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_KERNEL) != 0) { 3211 netdev_warn(dev, "init'ed rx ring %d with %d/%d pages only\n", 3212 ring_nr, i, bp->rx_ring_size); 3213 break; 3214 } 3215 prod = NEXT_RX_AGG(prod); 3216 } 3217 rxr->rx_agg_prod = prod; 3218 3219 if (bp->flags & BNXT_FLAG_TPA) { 3220 if (rxr->rx_tpa) { 3221 u8 *data; 3222 dma_addr_t mapping; 3223 3224 for (i = 0; i < bp->max_tpa; i++) { 3225 data = __bnxt_alloc_rx_data(bp, &mapping, 3226 GFP_KERNEL); 3227 if (!data) 3228 return -ENOMEM; 3229 3230 rxr->rx_tpa[i].data = data; 3231 rxr->rx_tpa[i].data_ptr = data + bp->rx_offset; 3232 rxr->rx_tpa[i].mapping = mapping; 3233 } 3234 } else { 3235 netdev_err(bp->dev, "No resource allocated for LRO/GRO\n"); 3236 return -ENOMEM; 3237 } 3238 } 3239 3240 return 0; 3241 } 3242 3243 static void bnxt_init_cp_rings(struct bnxt *bp) 3244 { 3245 int i, j; 3246 3247 for (i = 0; i < bp->cp_nr_rings; i++) { 3248 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring; 3249 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct; 3250 3251 ring->fw_ring_id = INVALID_HW_RING_ID; 3252 cpr->rx_ring_coal.coal_ticks = bp->rx_coal.coal_ticks; 3253 cpr->rx_ring_coal.coal_bufs = bp->rx_coal.coal_bufs; 3254 for (j = 0; j < 2; j++) { 3255 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j]; 3256 3257 if (!cpr2) 3258 continue; 3259 3260 ring = &cpr2->cp_ring_struct; 3261 ring->fw_ring_id = INVALID_HW_RING_ID; 3262 cpr2->rx_ring_coal.coal_ticks = bp->rx_coal.coal_ticks; 3263 cpr2->rx_ring_coal.coal_bufs = bp->rx_coal.coal_bufs; 3264 } 3265 } 3266 } 3267 3268 static int bnxt_init_rx_rings(struct bnxt *bp) 3269 { 3270 int i, rc = 0; 3271 3272 if (BNXT_RX_PAGE_MODE(bp)) { 3273 bp->rx_offset = NET_IP_ALIGN + XDP_PACKET_HEADROOM; 3274 bp->rx_dma_offset = XDP_PACKET_HEADROOM; 3275 } else { 3276 bp->rx_offset = BNXT_RX_OFFSET; 3277 bp->rx_dma_offset = BNXT_RX_DMA_OFFSET; 3278 } 3279 3280 for (i = 0; i < bp->rx_nr_rings; i++) { 3281 rc = bnxt_init_one_rx_ring(bp, i); 3282 if (rc) 3283 break; 3284 } 3285 3286 return rc; 3287 } 3288 3289 static int bnxt_init_tx_rings(struct bnxt *bp) 3290 { 3291 u16 i; 3292 3293 bp->tx_wake_thresh = max_t(int, bp->tx_ring_size / 2, 3294 MAX_SKB_FRAGS + 1); 3295 3296 for (i = 0; i < bp->tx_nr_rings; i++) { 3297 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; 3298 struct bnxt_ring_struct *ring = &txr->tx_ring_struct; 3299 3300 ring->fw_ring_id = INVALID_HW_RING_ID; 3301 } 3302 3303 return 0; 3304 } 3305 3306 static void bnxt_free_ring_grps(struct bnxt *bp) 3307 { 3308 kfree(bp->grp_info); 3309 bp->grp_info = NULL; 3310 } 3311 3312 static int bnxt_init_ring_grps(struct bnxt *bp, bool irq_re_init) 3313 { 3314 int i; 3315 3316 if (irq_re_init) { 3317 bp->grp_info = kcalloc(bp->cp_nr_rings, 3318 sizeof(struct bnxt_ring_grp_info), 3319 GFP_KERNEL); 3320 if (!bp->grp_info) 3321 return -ENOMEM; 3322 } 3323 for (i = 0; i < bp->cp_nr_rings; i++) { 3324 if (irq_re_init) 3325 bp->grp_info[i].fw_stats_ctx = INVALID_HW_RING_ID; 3326 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID; 3327 bp->grp_info[i].rx_fw_ring_id = INVALID_HW_RING_ID; 3328 bp->grp_info[i].agg_fw_ring_id = INVALID_HW_RING_ID; 3329 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID; 3330 } 3331 return 0; 3332 } 3333 3334 static void bnxt_free_vnics(struct bnxt *bp) 3335 { 3336 kfree(bp->vnic_info); 3337 bp->vnic_info = NULL; 3338 bp->nr_vnics = 0; 3339 } 3340 3341 static int bnxt_alloc_vnics(struct bnxt *bp) 3342 { 3343 int num_vnics = 1; 3344 3345 #ifdef CONFIG_RFS_ACCEL 3346 if ((bp->flags & (BNXT_FLAG_RFS | BNXT_FLAG_CHIP_P5)) == BNXT_FLAG_RFS) 3347 num_vnics += bp->rx_nr_rings; 3348 #endif 3349 3350 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 3351 num_vnics++; 3352 3353 bp->vnic_info = kcalloc(num_vnics, sizeof(struct bnxt_vnic_info), 3354 GFP_KERNEL); 3355 if (!bp->vnic_info) 3356 return -ENOMEM; 3357 3358 bp->nr_vnics = num_vnics; 3359 return 0; 3360 } 3361 3362 static void bnxt_init_vnics(struct bnxt *bp) 3363 { 3364 int i; 3365 3366 for (i = 0; i < bp->nr_vnics; i++) { 3367 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 3368 int j; 3369 3370 vnic->fw_vnic_id = INVALID_HW_RING_ID; 3371 for (j = 0; j < BNXT_MAX_CTX_PER_VNIC; j++) 3372 vnic->fw_rss_cos_lb_ctx[j] = INVALID_HW_RING_ID; 3373 3374 vnic->fw_l2_ctx_id = INVALID_HW_RING_ID; 3375 3376 if (bp->vnic_info[i].rss_hash_key) { 3377 if (i == 0) 3378 prandom_bytes(vnic->rss_hash_key, 3379 HW_HASH_KEY_SIZE); 3380 else 3381 memcpy(vnic->rss_hash_key, 3382 bp->vnic_info[0].rss_hash_key, 3383 HW_HASH_KEY_SIZE); 3384 } 3385 } 3386 } 3387 3388 static int bnxt_calc_nr_ring_pages(u32 ring_size, int desc_per_pg) 3389 { 3390 int pages; 3391 3392 pages = ring_size / desc_per_pg; 3393 3394 if (!pages) 3395 return 1; 3396 3397 pages++; 3398 3399 while (pages & (pages - 1)) 3400 pages++; 3401 3402 return pages; 3403 } 3404 3405 void bnxt_set_tpa_flags(struct bnxt *bp) 3406 { 3407 bp->flags &= ~BNXT_FLAG_TPA; 3408 if (bp->flags & BNXT_FLAG_NO_AGG_RINGS) 3409 return; 3410 if (bp->dev->features & NETIF_F_LRO) 3411 bp->flags |= BNXT_FLAG_LRO; 3412 else if (bp->dev->features & NETIF_F_GRO_HW) 3413 bp->flags |= BNXT_FLAG_GRO; 3414 } 3415 3416 /* bp->rx_ring_size, bp->tx_ring_size, dev->mtu, BNXT_FLAG_{G|L}RO flags must 3417 * be set on entry. 3418 */ 3419 void bnxt_set_ring_params(struct bnxt *bp) 3420 { 3421 u32 ring_size, rx_size, rx_space; 3422 u32 agg_factor = 0, agg_ring_size = 0; 3423 3424 /* 8 for CRC and VLAN */ 3425 rx_size = SKB_DATA_ALIGN(bp->dev->mtu + ETH_HLEN + NET_IP_ALIGN + 8); 3426 3427 rx_space = rx_size + NET_SKB_PAD + 3428 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 3429 3430 bp->rx_copy_thresh = BNXT_RX_COPY_THRESH; 3431 ring_size = bp->rx_ring_size; 3432 bp->rx_agg_ring_size = 0; 3433 bp->rx_agg_nr_pages = 0; 3434 3435 if (bp->flags & BNXT_FLAG_TPA) 3436 agg_factor = min_t(u32, 4, 65536 / BNXT_RX_PAGE_SIZE); 3437 3438 bp->flags &= ~BNXT_FLAG_JUMBO; 3439 if (rx_space > PAGE_SIZE && !(bp->flags & BNXT_FLAG_NO_AGG_RINGS)) { 3440 u32 jumbo_factor; 3441 3442 bp->flags |= BNXT_FLAG_JUMBO; 3443 jumbo_factor = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT; 3444 if (jumbo_factor > agg_factor) 3445 agg_factor = jumbo_factor; 3446 } 3447 agg_ring_size = ring_size * agg_factor; 3448 3449 if (agg_ring_size) { 3450 bp->rx_agg_nr_pages = bnxt_calc_nr_ring_pages(agg_ring_size, 3451 RX_DESC_CNT); 3452 if (bp->rx_agg_nr_pages > MAX_RX_AGG_PAGES) { 3453 u32 tmp = agg_ring_size; 3454 3455 bp->rx_agg_nr_pages = MAX_RX_AGG_PAGES; 3456 agg_ring_size = MAX_RX_AGG_PAGES * RX_DESC_CNT - 1; 3457 netdev_warn(bp->dev, "rx agg ring size %d reduced to %d.\n", 3458 tmp, agg_ring_size); 3459 } 3460 bp->rx_agg_ring_size = agg_ring_size; 3461 bp->rx_agg_ring_mask = (bp->rx_agg_nr_pages * RX_DESC_CNT) - 1; 3462 rx_size = SKB_DATA_ALIGN(BNXT_RX_COPY_THRESH + NET_IP_ALIGN); 3463 rx_space = rx_size + NET_SKB_PAD + 3464 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 3465 } 3466 3467 bp->rx_buf_use_size = rx_size; 3468 bp->rx_buf_size = rx_space; 3469 3470 bp->rx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, RX_DESC_CNT); 3471 bp->rx_ring_mask = (bp->rx_nr_pages * RX_DESC_CNT) - 1; 3472 3473 ring_size = bp->tx_ring_size; 3474 bp->tx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, TX_DESC_CNT); 3475 bp->tx_ring_mask = (bp->tx_nr_pages * TX_DESC_CNT) - 1; 3476 3477 ring_size = bp->rx_ring_size * (2 + agg_factor) + bp->tx_ring_size; 3478 bp->cp_ring_size = ring_size; 3479 3480 bp->cp_nr_pages = bnxt_calc_nr_ring_pages(ring_size, CP_DESC_CNT); 3481 if (bp->cp_nr_pages > MAX_CP_PAGES) { 3482 bp->cp_nr_pages = MAX_CP_PAGES; 3483 bp->cp_ring_size = MAX_CP_PAGES * CP_DESC_CNT - 1; 3484 netdev_warn(bp->dev, "completion ring size %d reduced to %d.\n", 3485 ring_size, bp->cp_ring_size); 3486 } 3487 bp->cp_bit = bp->cp_nr_pages * CP_DESC_CNT; 3488 bp->cp_ring_mask = bp->cp_bit - 1; 3489 } 3490 3491 /* Changing allocation mode of RX rings. 3492 * TODO: Update when extending xdp_rxq_info to support allocation modes. 3493 */ 3494 int bnxt_set_rx_skb_mode(struct bnxt *bp, bool page_mode) 3495 { 3496 if (page_mode) { 3497 if (bp->dev->mtu > BNXT_MAX_PAGE_MODE_MTU) 3498 return -EOPNOTSUPP; 3499 bp->dev->max_mtu = 3500 min_t(u16, bp->max_mtu, BNXT_MAX_PAGE_MODE_MTU); 3501 bp->flags &= ~BNXT_FLAG_AGG_RINGS; 3502 bp->flags |= BNXT_FLAG_NO_AGG_RINGS | BNXT_FLAG_RX_PAGE_MODE; 3503 bp->rx_dir = DMA_BIDIRECTIONAL; 3504 bp->rx_skb_func = bnxt_rx_page_skb; 3505 /* Disable LRO or GRO_HW */ 3506 netdev_update_features(bp->dev); 3507 } else { 3508 bp->dev->max_mtu = bp->max_mtu; 3509 bp->flags &= ~BNXT_FLAG_RX_PAGE_MODE; 3510 bp->rx_dir = DMA_FROM_DEVICE; 3511 bp->rx_skb_func = bnxt_rx_skb; 3512 } 3513 return 0; 3514 } 3515 3516 static void bnxt_free_vnic_attributes(struct bnxt *bp) 3517 { 3518 int i; 3519 struct bnxt_vnic_info *vnic; 3520 struct pci_dev *pdev = bp->pdev; 3521 3522 if (!bp->vnic_info) 3523 return; 3524 3525 for (i = 0; i < bp->nr_vnics; i++) { 3526 vnic = &bp->vnic_info[i]; 3527 3528 kfree(vnic->fw_grp_ids); 3529 vnic->fw_grp_ids = NULL; 3530 3531 kfree(vnic->uc_list); 3532 vnic->uc_list = NULL; 3533 3534 if (vnic->mc_list) { 3535 dma_free_coherent(&pdev->dev, vnic->mc_list_size, 3536 vnic->mc_list, vnic->mc_list_mapping); 3537 vnic->mc_list = NULL; 3538 } 3539 3540 if (vnic->rss_table) { 3541 dma_free_coherent(&pdev->dev, PAGE_SIZE, 3542 vnic->rss_table, 3543 vnic->rss_table_dma_addr); 3544 vnic->rss_table = NULL; 3545 } 3546 3547 vnic->rss_hash_key = NULL; 3548 vnic->flags = 0; 3549 } 3550 } 3551 3552 static int bnxt_alloc_vnic_attributes(struct bnxt *bp) 3553 { 3554 int i, rc = 0, size; 3555 struct bnxt_vnic_info *vnic; 3556 struct pci_dev *pdev = bp->pdev; 3557 int max_rings; 3558 3559 for (i = 0; i < bp->nr_vnics; i++) { 3560 vnic = &bp->vnic_info[i]; 3561 3562 if (vnic->flags & BNXT_VNIC_UCAST_FLAG) { 3563 int mem_size = (BNXT_MAX_UC_ADDRS - 1) * ETH_ALEN; 3564 3565 if (mem_size > 0) { 3566 vnic->uc_list = kmalloc(mem_size, GFP_KERNEL); 3567 if (!vnic->uc_list) { 3568 rc = -ENOMEM; 3569 goto out; 3570 } 3571 } 3572 } 3573 3574 if (vnic->flags & BNXT_VNIC_MCAST_FLAG) { 3575 vnic->mc_list_size = BNXT_MAX_MC_ADDRS * ETH_ALEN; 3576 vnic->mc_list = 3577 dma_alloc_coherent(&pdev->dev, 3578 vnic->mc_list_size, 3579 &vnic->mc_list_mapping, 3580 GFP_KERNEL); 3581 if (!vnic->mc_list) { 3582 rc = -ENOMEM; 3583 goto out; 3584 } 3585 } 3586 3587 if (bp->flags & BNXT_FLAG_CHIP_P5) 3588 goto vnic_skip_grps; 3589 3590 if (vnic->flags & BNXT_VNIC_RSS_FLAG) 3591 max_rings = bp->rx_nr_rings; 3592 else 3593 max_rings = 1; 3594 3595 vnic->fw_grp_ids = kcalloc(max_rings, sizeof(u16), GFP_KERNEL); 3596 if (!vnic->fw_grp_ids) { 3597 rc = -ENOMEM; 3598 goto out; 3599 } 3600 vnic_skip_grps: 3601 if ((bp->flags & BNXT_FLAG_NEW_RSS_CAP) && 3602 !(vnic->flags & BNXT_VNIC_RSS_FLAG)) 3603 continue; 3604 3605 /* Allocate rss table and hash key */ 3606 vnic->rss_table = dma_alloc_coherent(&pdev->dev, PAGE_SIZE, 3607 &vnic->rss_table_dma_addr, 3608 GFP_KERNEL); 3609 if (!vnic->rss_table) { 3610 rc = -ENOMEM; 3611 goto out; 3612 } 3613 3614 size = L1_CACHE_ALIGN(HW_HASH_INDEX_SIZE * sizeof(u16)); 3615 3616 vnic->rss_hash_key = ((void *)vnic->rss_table) + size; 3617 vnic->rss_hash_key_dma_addr = vnic->rss_table_dma_addr + size; 3618 } 3619 return 0; 3620 3621 out: 3622 return rc; 3623 } 3624 3625 static void bnxt_free_hwrm_resources(struct bnxt *bp) 3626 { 3627 struct pci_dev *pdev = bp->pdev; 3628 3629 if (bp->hwrm_cmd_resp_addr) { 3630 dma_free_coherent(&pdev->dev, PAGE_SIZE, bp->hwrm_cmd_resp_addr, 3631 bp->hwrm_cmd_resp_dma_addr); 3632 bp->hwrm_cmd_resp_addr = NULL; 3633 } 3634 3635 if (bp->hwrm_cmd_kong_resp_addr) { 3636 dma_free_coherent(&pdev->dev, PAGE_SIZE, 3637 bp->hwrm_cmd_kong_resp_addr, 3638 bp->hwrm_cmd_kong_resp_dma_addr); 3639 bp->hwrm_cmd_kong_resp_addr = NULL; 3640 } 3641 } 3642 3643 static int bnxt_alloc_kong_hwrm_resources(struct bnxt *bp) 3644 { 3645 struct pci_dev *pdev = bp->pdev; 3646 3647 if (bp->hwrm_cmd_kong_resp_addr) 3648 return 0; 3649 3650 bp->hwrm_cmd_kong_resp_addr = 3651 dma_alloc_coherent(&pdev->dev, PAGE_SIZE, 3652 &bp->hwrm_cmd_kong_resp_dma_addr, 3653 GFP_KERNEL); 3654 if (!bp->hwrm_cmd_kong_resp_addr) 3655 return -ENOMEM; 3656 3657 return 0; 3658 } 3659 3660 static int bnxt_alloc_hwrm_resources(struct bnxt *bp) 3661 { 3662 struct pci_dev *pdev = bp->pdev; 3663 3664 bp->hwrm_cmd_resp_addr = dma_alloc_coherent(&pdev->dev, PAGE_SIZE, 3665 &bp->hwrm_cmd_resp_dma_addr, 3666 GFP_KERNEL); 3667 if (!bp->hwrm_cmd_resp_addr) 3668 return -ENOMEM; 3669 3670 return 0; 3671 } 3672 3673 static void bnxt_free_hwrm_short_cmd_req(struct bnxt *bp) 3674 { 3675 if (bp->hwrm_short_cmd_req_addr) { 3676 struct pci_dev *pdev = bp->pdev; 3677 3678 dma_free_coherent(&pdev->dev, bp->hwrm_max_ext_req_len, 3679 bp->hwrm_short_cmd_req_addr, 3680 bp->hwrm_short_cmd_req_dma_addr); 3681 bp->hwrm_short_cmd_req_addr = NULL; 3682 } 3683 } 3684 3685 static int bnxt_alloc_hwrm_short_cmd_req(struct bnxt *bp) 3686 { 3687 struct pci_dev *pdev = bp->pdev; 3688 3689 if (bp->hwrm_short_cmd_req_addr) 3690 return 0; 3691 3692 bp->hwrm_short_cmd_req_addr = 3693 dma_alloc_coherent(&pdev->dev, bp->hwrm_max_ext_req_len, 3694 &bp->hwrm_short_cmd_req_dma_addr, 3695 GFP_KERNEL); 3696 if (!bp->hwrm_short_cmd_req_addr) 3697 return -ENOMEM; 3698 3699 return 0; 3700 } 3701 3702 static void bnxt_free_port_stats(struct bnxt *bp) 3703 { 3704 struct pci_dev *pdev = bp->pdev; 3705 3706 bp->flags &= ~BNXT_FLAG_PORT_STATS; 3707 bp->flags &= ~BNXT_FLAG_PORT_STATS_EXT; 3708 3709 if (bp->hw_rx_port_stats) { 3710 dma_free_coherent(&pdev->dev, bp->hw_port_stats_size, 3711 bp->hw_rx_port_stats, 3712 bp->hw_rx_port_stats_map); 3713 bp->hw_rx_port_stats = NULL; 3714 } 3715 3716 if (bp->hw_tx_port_stats_ext) { 3717 dma_free_coherent(&pdev->dev, sizeof(struct tx_port_stats_ext), 3718 bp->hw_tx_port_stats_ext, 3719 bp->hw_tx_port_stats_ext_map); 3720 bp->hw_tx_port_stats_ext = NULL; 3721 } 3722 3723 if (bp->hw_rx_port_stats_ext) { 3724 dma_free_coherent(&pdev->dev, sizeof(struct rx_port_stats_ext), 3725 bp->hw_rx_port_stats_ext, 3726 bp->hw_rx_port_stats_ext_map); 3727 bp->hw_rx_port_stats_ext = NULL; 3728 } 3729 3730 if (bp->hw_pcie_stats) { 3731 dma_free_coherent(&pdev->dev, sizeof(struct pcie_ctx_hw_stats), 3732 bp->hw_pcie_stats, bp->hw_pcie_stats_map); 3733 bp->hw_pcie_stats = NULL; 3734 } 3735 } 3736 3737 static void bnxt_free_ring_stats(struct bnxt *bp) 3738 { 3739 struct pci_dev *pdev = bp->pdev; 3740 int size, i; 3741 3742 if (!bp->bnapi) 3743 return; 3744 3745 size = bp->hw_ring_stats_size; 3746 3747 for (i = 0; i < bp->cp_nr_rings; i++) { 3748 struct bnxt_napi *bnapi = bp->bnapi[i]; 3749 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 3750 3751 if (cpr->hw_stats) { 3752 dma_free_coherent(&pdev->dev, size, cpr->hw_stats, 3753 cpr->hw_stats_map); 3754 cpr->hw_stats = NULL; 3755 } 3756 } 3757 } 3758 3759 static int bnxt_alloc_stats(struct bnxt *bp) 3760 { 3761 u32 size, i; 3762 struct pci_dev *pdev = bp->pdev; 3763 3764 size = bp->hw_ring_stats_size; 3765 3766 for (i = 0; i < bp->cp_nr_rings; i++) { 3767 struct bnxt_napi *bnapi = bp->bnapi[i]; 3768 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 3769 3770 cpr->hw_stats = dma_alloc_coherent(&pdev->dev, size, 3771 &cpr->hw_stats_map, 3772 GFP_KERNEL); 3773 if (!cpr->hw_stats) 3774 return -ENOMEM; 3775 3776 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID; 3777 } 3778 3779 if (BNXT_VF(bp) || bp->chip_num == CHIP_NUM_58700) 3780 return 0; 3781 3782 if (bp->hw_rx_port_stats) 3783 goto alloc_ext_stats; 3784 3785 bp->hw_port_stats_size = sizeof(struct rx_port_stats) + 3786 sizeof(struct tx_port_stats) + 1024; 3787 3788 bp->hw_rx_port_stats = 3789 dma_alloc_coherent(&pdev->dev, bp->hw_port_stats_size, 3790 &bp->hw_rx_port_stats_map, 3791 GFP_KERNEL); 3792 if (!bp->hw_rx_port_stats) 3793 return -ENOMEM; 3794 3795 bp->hw_tx_port_stats = (void *)(bp->hw_rx_port_stats + 1) + 512; 3796 bp->hw_tx_port_stats_map = bp->hw_rx_port_stats_map + 3797 sizeof(struct rx_port_stats) + 512; 3798 bp->flags |= BNXT_FLAG_PORT_STATS; 3799 3800 alloc_ext_stats: 3801 /* Display extended statistics only if FW supports it */ 3802 if (bp->hwrm_spec_code < 0x10804 || bp->hwrm_spec_code == 0x10900) 3803 if (!(bp->fw_cap & BNXT_FW_CAP_EXT_STATS_SUPPORTED)) 3804 return 0; 3805 3806 if (bp->hw_rx_port_stats_ext) 3807 goto alloc_tx_ext_stats; 3808 3809 bp->hw_rx_port_stats_ext = 3810 dma_alloc_coherent(&pdev->dev, sizeof(struct rx_port_stats_ext), 3811 &bp->hw_rx_port_stats_ext_map, GFP_KERNEL); 3812 if (!bp->hw_rx_port_stats_ext) 3813 return 0; 3814 3815 alloc_tx_ext_stats: 3816 if (bp->hw_tx_port_stats_ext) 3817 goto alloc_pcie_stats; 3818 3819 if (bp->hwrm_spec_code >= 0x10902 || 3820 (bp->fw_cap & BNXT_FW_CAP_EXT_STATS_SUPPORTED)) { 3821 bp->hw_tx_port_stats_ext = 3822 dma_alloc_coherent(&pdev->dev, 3823 sizeof(struct tx_port_stats_ext), 3824 &bp->hw_tx_port_stats_ext_map, 3825 GFP_KERNEL); 3826 } 3827 bp->flags |= BNXT_FLAG_PORT_STATS_EXT; 3828 3829 alloc_pcie_stats: 3830 if (bp->hw_pcie_stats || 3831 !(bp->fw_cap & BNXT_FW_CAP_PCIE_STATS_SUPPORTED)) 3832 return 0; 3833 3834 bp->hw_pcie_stats = 3835 dma_alloc_coherent(&pdev->dev, sizeof(struct pcie_ctx_hw_stats), 3836 &bp->hw_pcie_stats_map, GFP_KERNEL); 3837 if (!bp->hw_pcie_stats) 3838 return 0; 3839 3840 bp->flags |= BNXT_FLAG_PCIE_STATS; 3841 return 0; 3842 } 3843 3844 static void bnxt_clear_ring_indices(struct bnxt *bp) 3845 { 3846 int i; 3847 3848 if (!bp->bnapi) 3849 return; 3850 3851 for (i = 0; i < bp->cp_nr_rings; i++) { 3852 struct bnxt_napi *bnapi = bp->bnapi[i]; 3853 struct bnxt_cp_ring_info *cpr; 3854 struct bnxt_rx_ring_info *rxr; 3855 struct bnxt_tx_ring_info *txr; 3856 3857 if (!bnapi) 3858 continue; 3859 3860 cpr = &bnapi->cp_ring; 3861 cpr->cp_raw_cons = 0; 3862 3863 txr = bnapi->tx_ring; 3864 if (txr) { 3865 txr->tx_prod = 0; 3866 txr->tx_cons = 0; 3867 } 3868 3869 rxr = bnapi->rx_ring; 3870 if (rxr) { 3871 rxr->rx_prod = 0; 3872 rxr->rx_agg_prod = 0; 3873 rxr->rx_sw_agg_prod = 0; 3874 rxr->rx_next_cons = 0; 3875 } 3876 } 3877 } 3878 3879 static void bnxt_free_ntp_fltrs(struct bnxt *bp, bool irq_reinit) 3880 { 3881 #ifdef CONFIG_RFS_ACCEL 3882 int i; 3883 3884 /* Under rtnl_lock and all our NAPIs have been disabled. It's 3885 * safe to delete the hash table. 3886 */ 3887 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) { 3888 struct hlist_head *head; 3889 struct hlist_node *tmp; 3890 struct bnxt_ntuple_filter *fltr; 3891 3892 head = &bp->ntp_fltr_hash_tbl[i]; 3893 hlist_for_each_entry_safe(fltr, tmp, head, hash) { 3894 hlist_del(&fltr->hash); 3895 kfree(fltr); 3896 } 3897 } 3898 if (irq_reinit) { 3899 kfree(bp->ntp_fltr_bmap); 3900 bp->ntp_fltr_bmap = NULL; 3901 } 3902 bp->ntp_fltr_count = 0; 3903 #endif 3904 } 3905 3906 static int bnxt_alloc_ntp_fltrs(struct bnxt *bp) 3907 { 3908 #ifdef CONFIG_RFS_ACCEL 3909 int i, rc = 0; 3910 3911 if (!(bp->flags & BNXT_FLAG_RFS)) 3912 return 0; 3913 3914 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) 3915 INIT_HLIST_HEAD(&bp->ntp_fltr_hash_tbl[i]); 3916 3917 bp->ntp_fltr_count = 0; 3918 bp->ntp_fltr_bmap = kcalloc(BITS_TO_LONGS(BNXT_NTP_FLTR_MAX_FLTR), 3919 sizeof(long), 3920 GFP_KERNEL); 3921 3922 if (!bp->ntp_fltr_bmap) 3923 rc = -ENOMEM; 3924 3925 return rc; 3926 #else 3927 return 0; 3928 #endif 3929 } 3930 3931 static void bnxt_free_mem(struct bnxt *bp, bool irq_re_init) 3932 { 3933 bnxt_free_vnic_attributes(bp); 3934 bnxt_free_tx_rings(bp); 3935 bnxt_free_rx_rings(bp); 3936 bnxt_free_cp_rings(bp); 3937 bnxt_free_ntp_fltrs(bp, irq_re_init); 3938 if (irq_re_init) { 3939 bnxt_free_ring_stats(bp); 3940 bnxt_free_ring_grps(bp); 3941 bnxt_free_vnics(bp); 3942 kfree(bp->tx_ring_map); 3943 bp->tx_ring_map = NULL; 3944 kfree(bp->tx_ring); 3945 bp->tx_ring = NULL; 3946 kfree(bp->rx_ring); 3947 bp->rx_ring = NULL; 3948 kfree(bp->bnapi); 3949 bp->bnapi = NULL; 3950 } else { 3951 bnxt_clear_ring_indices(bp); 3952 } 3953 } 3954 3955 static int bnxt_alloc_mem(struct bnxt *bp, bool irq_re_init) 3956 { 3957 int i, j, rc, size, arr_size; 3958 void *bnapi; 3959 3960 if (irq_re_init) { 3961 /* Allocate bnapi mem pointer array and mem block for 3962 * all queues 3963 */ 3964 arr_size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi *) * 3965 bp->cp_nr_rings); 3966 size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi)); 3967 bnapi = kzalloc(arr_size + size * bp->cp_nr_rings, GFP_KERNEL); 3968 if (!bnapi) 3969 return -ENOMEM; 3970 3971 bp->bnapi = bnapi; 3972 bnapi += arr_size; 3973 for (i = 0; i < bp->cp_nr_rings; i++, bnapi += size) { 3974 bp->bnapi[i] = bnapi; 3975 bp->bnapi[i]->index = i; 3976 bp->bnapi[i]->bp = bp; 3977 if (bp->flags & BNXT_FLAG_CHIP_P5) { 3978 struct bnxt_cp_ring_info *cpr = 3979 &bp->bnapi[i]->cp_ring; 3980 3981 cpr->cp_ring_struct.ring_mem.flags = 3982 BNXT_RMEM_RING_PTE_FLAG; 3983 } 3984 } 3985 3986 bp->rx_ring = kcalloc(bp->rx_nr_rings, 3987 sizeof(struct bnxt_rx_ring_info), 3988 GFP_KERNEL); 3989 if (!bp->rx_ring) 3990 return -ENOMEM; 3991 3992 for (i = 0; i < bp->rx_nr_rings; i++) { 3993 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 3994 3995 if (bp->flags & BNXT_FLAG_CHIP_P5) { 3996 rxr->rx_ring_struct.ring_mem.flags = 3997 BNXT_RMEM_RING_PTE_FLAG; 3998 rxr->rx_agg_ring_struct.ring_mem.flags = 3999 BNXT_RMEM_RING_PTE_FLAG; 4000 } 4001 rxr->bnapi = bp->bnapi[i]; 4002 bp->bnapi[i]->rx_ring = &bp->rx_ring[i]; 4003 } 4004 4005 bp->tx_ring = kcalloc(bp->tx_nr_rings, 4006 sizeof(struct bnxt_tx_ring_info), 4007 GFP_KERNEL); 4008 if (!bp->tx_ring) 4009 return -ENOMEM; 4010 4011 bp->tx_ring_map = kcalloc(bp->tx_nr_rings, sizeof(u16), 4012 GFP_KERNEL); 4013 4014 if (!bp->tx_ring_map) 4015 return -ENOMEM; 4016 4017 if (bp->flags & BNXT_FLAG_SHARED_RINGS) 4018 j = 0; 4019 else 4020 j = bp->rx_nr_rings; 4021 4022 for (i = 0; i < bp->tx_nr_rings; i++, j++) { 4023 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; 4024 4025 if (bp->flags & BNXT_FLAG_CHIP_P5) 4026 txr->tx_ring_struct.ring_mem.flags = 4027 BNXT_RMEM_RING_PTE_FLAG; 4028 txr->bnapi = bp->bnapi[j]; 4029 bp->bnapi[j]->tx_ring = txr; 4030 bp->tx_ring_map[i] = bp->tx_nr_rings_xdp + i; 4031 if (i >= bp->tx_nr_rings_xdp) { 4032 txr->txq_index = i - bp->tx_nr_rings_xdp; 4033 bp->bnapi[j]->tx_int = bnxt_tx_int; 4034 } else { 4035 bp->bnapi[j]->flags |= BNXT_NAPI_FLAG_XDP; 4036 bp->bnapi[j]->tx_int = bnxt_tx_int_xdp; 4037 } 4038 } 4039 4040 rc = bnxt_alloc_stats(bp); 4041 if (rc) 4042 goto alloc_mem_err; 4043 4044 rc = bnxt_alloc_ntp_fltrs(bp); 4045 if (rc) 4046 goto alloc_mem_err; 4047 4048 rc = bnxt_alloc_vnics(bp); 4049 if (rc) 4050 goto alloc_mem_err; 4051 } 4052 4053 bnxt_init_ring_struct(bp); 4054 4055 rc = bnxt_alloc_rx_rings(bp); 4056 if (rc) 4057 goto alloc_mem_err; 4058 4059 rc = bnxt_alloc_tx_rings(bp); 4060 if (rc) 4061 goto alloc_mem_err; 4062 4063 rc = bnxt_alloc_cp_rings(bp); 4064 if (rc) 4065 goto alloc_mem_err; 4066 4067 bp->vnic_info[0].flags |= BNXT_VNIC_RSS_FLAG | BNXT_VNIC_MCAST_FLAG | 4068 BNXT_VNIC_UCAST_FLAG; 4069 rc = bnxt_alloc_vnic_attributes(bp); 4070 if (rc) 4071 goto alloc_mem_err; 4072 return 0; 4073 4074 alloc_mem_err: 4075 bnxt_free_mem(bp, true); 4076 return rc; 4077 } 4078 4079 static void bnxt_disable_int(struct bnxt *bp) 4080 { 4081 int i; 4082 4083 if (!bp->bnapi) 4084 return; 4085 4086 for (i = 0; i < bp->cp_nr_rings; i++) { 4087 struct bnxt_napi *bnapi = bp->bnapi[i]; 4088 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 4089 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct; 4090 4091 if (ring->fw_ring_id != INVALID_HW_RING_ID) 4092 bnxt_db_nq(bp, &cpr->cp_db, cpr->cp_raw_cons); 4093 } 4094 } 4095 4096 static int bnxt_cp_num_to_irq_num(struct bnxt *bp, int n) 4097 { 4098 struct bnxt_napi *bnapi = bp->bnapi[n]; 4099 struct bnxt_cp_ring_info *cpr; 4100 4101 cpr = &bnapi->cp_ring; 4102 return cpr->cp_ring_struct.map_idx; 4103 } 4104 4105 static void bnxt_disable_int_sync(struct bnxt *bp) 4106 { 4107 int i; 4108 4109 atomic_inc(&bp->intr_sem); 4110 4111 bnxt_disable_int(bp); 4112 for (i = 0; i < bp->cp_nr_rings; i++) { 4113 int map_idx = bnxt_cp_num_to_irq_num(bp, i); 4114 4115 synchronize_irq(bp->irq_tbl[map_idx].vector); 4116 } 4117 } 4118 4119 static void bnxt_enable_int(struct bnxt *bp) 4120 { 4121 int i; 4122 4123 atomic_set(&bp->intr_sem, 0); 4124 for (i = 0; i < bp->cp_nr_rings; i++) { 4125 struct bnxt_napi *bnapi = bp->bnapi[i]; 4126 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 4127 4128 bnxt_db_nq_arm(bp, &cpr->cp_db, cpr->cp_raw_cons); 4129 } 4130 } 4131 4132 void bnxt_hwrm_cmd_hdr_init(struct bnxt *bp, void *request, u16 req_type, 4133 u16 cmpl_ring, u16 target_id) 4134 { 4135 struct input *req = request; 4136 4137 req->req_type = cpu_to_le16(req_type); 4138 req->cmpl_ring = cpu_to_le16(cmpl_ring); 4139 req->target_id = cpu_to_le16(target_id); 4140 if (bnxt_kong_hwrm_message(bp, req)) 4141 req->resp_addr = cpu_to_le64(bp->hwrm_cmd_kong_resp_dma_addr); 4142 else 4143 req->resp_addr = cpu_to_le64(bp->hwrm_cmd_resp_dma_addr); 4144 } 4145 4146 static int bnxt_hwrm_to_stderr(u32 hwrm_err) 4147 { 4148 switch (hwrm_err) { 4149 case HWRM_ERR_CODE_SUCCESS: 4150 return 0; 4151 case HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED: 4152 return -EACCES; 4153 case HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR: 4154 return -ENOSPC; 4155 case HWRM_ERR_CODE_INVALID_PARAMS: 4156 case HWRM_ERR_CODE_INVALID_FLAGS: 4157 case HWRM_ERR_CODE_INVALID_ENABLES: 4158 case HWRM_ERR_CODE_UNSUPPORTED_TLV: 4159 case HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR: 4160 return -EINVAL; 4161 case HWRM_ERR_CODE_NO_BUFFER: 4162 return -ENOMEM; 4163 case HWRM_ERR_CODE_HOT_RESET_PROGRESS: 4164 case HWRM_ERR_CODE_BUSY: 4165 return -EAGAIN; 4166 case HWRM_ERR_CODE_CMD_NOT_SUPPORTED: 4167 return -EOPNOTSUPP; 4168 default: 4169 return -EIO; 4170 } 4171 } 4172 4173 static int bnxt_hwrm_do_send_msg(struct bnxt *bp, void *msg, u32 msg_len, 4174 int timeout, bool silent) 4175 { 4176 int i, intr_process, rc, tmo_count; 4177 struct input *req = msg; 4178 u32 *data = msg; 4179 __le32 *resp_len; 4180 u8 *valid; 4181 u16 cp_ring_id, len = 0; 4182 struct hwrm_err_output *resp = bp->hwrm_cmd_resp_addr; 4183 u16 max_req_len = BNXT_HWRM_MAX_REQ_LEN; 4184 struct hwrm_short_input short_input = {0}; 4185 u32 doorbell_offset = BNXT_GRCPF_REG_CHIMP_COMM_TRIGGER; 4186 u8 *resp_addr = (u8 *)bp->hwrm_cmd_resp_addr; 4187 u32 bar_offset = BNXT_GRCPF_REG_CHIMP_COMM; 4188 u16 dst = BNXT_HWRM_CHNL_CHIMP; 4189 4190 if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state)) 4191 return -EBUSY; 4192 4193 if (msg_len > BNXT_HWRM_MAX_REQ_LEN) { 4194 if (msg_len > bp->hwrm_max_ext_req_len || 4195 !bp->hwrm_short_cmd_req_addr) 4196 return -EINVAL; 4197 } 4198 4199 if (bnxt_hwrm_kong_chnl(bp, req)) { 4200 dst = BNXT_HWRM_CHNL_KONG; 4201 bar_offset = BNXT_GRCPF_REG_KONG_COMM; 4202 doorbell_offset = BNXT_GRCPF_REG_KONG_COMM_TRIGGER; 4203 resp = bp->hwrm_cmd_kong_resp_addr; 4204 resp_addr = (u8 *)bp->hwrm_cmd_kong_resp_addr; 4205 } 4206 4207 memset(resp, 0, PAGE_SIZE); 4208 cp_ring_id = le16_to_cpu(req->cmpl_ring); 4209 intr_process = (cp_ring_id == INVALID_HW_RING_ID) ? 0 : 1; 4210 4211 req->seq_id = cpu_to_le16(bnxt_get_hwrm_seq_id(bp, dst)); 4212 /* currently supports only one outstanding message */ 4213 if (intr_process) 4214 bp->hwrm_intr_seq_id = le16_to_cpu(req->seq_id); 4215 4216 if ((bp->fw_cap & BNXT_FW_CAP_SHORT_CMD) || 4217 msg_len > BNXT_HWRM_MAX_REQ_LEN) { 4218 void *short_cmd_req = bp->hwrm_short_cmd_req_addr; 4219 u16 max_msg_len; 4220 4221 /* Set boundary for maximum extended request length for short 4222 * cmd format. If passed up from device use the max supported 4223 * internal req length. 4224 */ 4225 max_msg_len = bp->hwrm_max_ext_req_len; 4226 4227 memcpy(short_cmd_req, req, msg_len); 4228 if (msg_len < max_msg_len) 4229 memset(short_cmd_req + msg_len, 0, 4230 max_msg_len - msg_len); 4231 4232 short_input.req_type = req->req_type; 4233 short_input.signature = 4234 cpu_to_le16(SHORT_REQ_SIGNATURE_SHORT_CMD); 4235 short_input.size = cpu_to_le16(msg_len); 4236 short_input.req_addr = 4237 cpu_to_le64(bp->hwrm_short_cmd_req_dma_addr); 4238 4239 data = (u32 *)&short_input; 4240 msg_len = sizeof(short_input); 4241 4242 /* Sync memory write before updating doorbell */ 4243 wmb(); 4244 4245 max_req_len = BNXT_HWRM_SHORT_REQ_LEN; 4246 } 4247 4248 /* Write request msg to hwrm channel */ 4249 __iowrite32_copy(bp->bar0 + bar_offset, data, msg_len / 4); 4250 4251 for (i = msg_len; i < max_req_len; i += 4) 4252 writel(0, bp->bar0 + bar_offset + i); 4253 4254 /* Ring channel doorbell */ 4255 writel(1, bp->bar0 + doorbell_offset); 4256 4257 if (!pci_is_enabled(bp->pdev)) 4258 return 0; 4259 4260 if (!timeout) 4261 timeout = DFLT_HWRM_CMD_TIMEOUT; 4262 /* convert timeout to usec */ 4263 timeout *= 1000; 4264 4265 i = 0; 4266 /* Short timeout for the first few iterations: 4267 * number of loops = number of loops for short timeout + 4268 * number of loops for standard timeout. 4269 */ 4270 tmo_count = HWRM_SHORT_TIMEOUT_COUNTER; 4271 timeout = timeout - HWRM_SHORT_MIN_TIMEOUT * HWRM_SHORT_TIMEOUT_COUNTER; 4272 tmo_count += DIV_ROUND_UP(timeout, HWRM_MIN_TIMEOUT); 4273 resp_len = (__le32 *)(resp_addr + HWRM_RESP_LEN_OFFSET); 4274 4275 if (intr_process) { 4276 u16 seq_id = bp->hwrm_intr_seq_id; 4277 4278 /* Wait until hwrm response cmpl interrupt is processed */ 4279 while (bp->hwrm_intr_seq_id != (u16)~seq_id && 4280 i++ < tmo_count) { 4281 /* Abort the wait for completion if the FW health 4282 * check has failed. 4283 */ 4284 if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state)) 4285 return -EBUSY; 4286 /* on first few passes, just barely sleep */ 4287 if (i < HWRM_SHORT_TIMEOUT_COUNTER) 4288 usleep_range(HWRM_SHORT_MIN_TIMEOUT, 4289 HWRM_SHORT_MAX_TIMEOUT); 4290 else 4291 usleep_range(HWRM_MIN_TIMEOUT, 4292 HWRM_MAX_TIMEOUT); 4293 } 4294 4295 if (bp->hwrm_intr_seq_id != (u16)~seq_id) { 4296 if (!silent) 4297 netdev_err(bp->dev, "Resp cmpl intr err msg: 0x%x\n", 4298 le16_to_cpu(req->req_type)); 4299 return -EBUSY; 4300 } 4301 len = (le32_to_cpu(*resp_len) & HWRM_RESP_LEN_MASK) >> 4302 HWRM_RESP_LEN_SFT; 4303 valid = resp_addr + len - 1; 4304 } else { 4305 int j; 4306 4307 /* Check if response len is updated */ 4308 for (i = 0; i < tmo_count; i++) { 4309 /* Abort the wait for completion if the FW health 4310 * check has failed. 4311 */ 4312 if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state)) 4313 return -EBUSY; 4314 len = (le32_to_cpu(*resp_len) & HWRM_RESP_LEN_MASK) >> 4315 HWRM_RESP_LEN_SFT; 4316 if (len) 4317 break; 4318 /* on first few passes, just barely sleep */ 4319 if (i < HWRM_SHORT_TIMEOUT_COUNTER) 4320 usleep_range(HWRM_SHORT_MIN_TIMEOUT, 4321 HWRM_SHORT_MAX_TIMEOUT); 4322 else 4323 usleep_range(HWRM_MIN_TIMEOUT, 4324 HWRM_MAX_TIMEOUT); 4325 } 4326 4327 if (i >= tmo_count) { 4328 if (!silent) 4329 netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d\n", 4330 HWRM_TOTAL_TIMEOUT(i), 4331 le16_to_cpu(req->req_type), 4332 le16_to_cpu(req->seq_id), len); 4333 return -EBUSY; 4334 } 4335 4336 /* Last byte of resp contains valid bit */ 4337 valid = resp_addr + len - 1; 4338 for (j = 0; j < HWRM_VALID_BIT_DELAY_USEC; j++) { 4339 /* make sure we read from updated DMA memory */ 4340 dma_rmb(); 4341 if (*valid) 4342 break; 4343 usleep_range(1, 5); 4344 } 4345 4346 if (j >= HWRM_VALID_BIT_DELAY_USEC) { 4347 if (!silent) 4348 netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d v:%d\n", 4349 HWRM_TOTAL_TIMEOUT(i), 4350 le16_to_cpu(req->req_type), 4351 le16_to_cpu(req->seq_id), len, 4352 *valid); 4353 return -EBUSY; 4354 } 4355 } 4356 4357 /* Zero valid bit for compatibility. Valid bit in an older spec 4358 * may become a new field in a newer spec. We must make sure that 4359 * a new field not implemented by old spec will read zero. 4360 */ 4361 *valid = 0; 4362 rc = le16_to_cpu(resp->error_code); 4363 if (rc && !silent) 4364 netdev_err(bp->dev, "hwrm req_type 0x%x seq id 0x%x error 0x%x\n", 4365 le16_to_cpu(resp->req_type), 4366 le16_to_cpu(resp->seq_id), rc); 4367 return bnxt_hwrm_to_stderr(rc); 4368 } 4369 4370 int _hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout) 4371 { 4372 return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, false); 4373 } 4374 4375 int _hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len, 4376 int timeout) 4377 { 4378 return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true); 4379 } 4380 4381 int hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout) 4382 { 4383 int rc; 4384 4385 mutex_lock(&bp->hwrm_cmd_lock); 4386 rc = _hwrm_send_message(bp, msg, msg_len, timeout); 4387 mutex_unlock(&bp->hwrm_cmd_lock); 4388 return rc; 4389 } 4390 4391 int hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len, 4392 int timeout) 4393 { 4394 int rc; 4395 4396 mutex_lock(&bp->hwrm_cmd_lock); 4397 rc = bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true); 4398 mutex_unlock(&bp->hwrm_cmd_lock); 4399 return rc; 4400 } 4401 4402 int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp, unsigned long *bmap, int bmap_size, 4403 bool async_only) 4404 { 4405 struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr; 4406 struct hwrm_func_drv_rgtr_input req = {0}; 4407 DECLARE_BITMAP(async_events_bmap, 256); 4408 u32 *events = (u32 *)async_events_bmap; 4409 u32 flags; 4410 int rc, i; 4411 4412 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1); 4413 4414 req.enables = 4415 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE | 4416 FUNC_DRV_RGTR_REQ_ENABLES_VER | 4417 FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD); 4418 4419 req.os_type = cpu_to_le16(FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX); 4420 flags = FUNC_DRV_RGTR_REQ_FLAGS_16BIT_VER_MODE; 4421 if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET) 4422 flags |= FUNC_DRV_RGTR_REQ_FLAGS_HOT_RESET_SUPPORT; 4423 if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY) 4424 flags |= FUNC_DRV_RGTR_REQ_FLAGS_ERROR_RECOVERY_SUPPORT | 4425 FUNC_DRV_RGTR_REQ_FLAGS_MASTER_SUPPORT; 4426 req.flags = cpu_to_le32(flags); 4427 req.ver_maj_8b = DRV_VER_MAJ; 4428 req.ver_min_8b = DRV_VER_MIN; 4429 req.ver_upd_8b = DRV_VER_UPD; 4430 req.ver_maj = cpu_to_le16(DRV_VER_MAJ); 4431 req.ver_min = cpu_to_le16(DRV_VER_MIN); 4432 req.ver_upd = cpu_to_le16(DRV_VER_UPD); 4433 4434 if (BNXT_PF(bp)) { 4435 u32 data[8]; 4436 int i; 4437 4438 memset(data, 0, sizeof(data)); 4439 for (i = 0; i < ARRAY_SIZE(bnxt_vf_req_snif); i++) { 4440 u16 cmd = bnxt_vf_req_snif[i]; 4441 unsigned int bit, idx; 4442 4443 idx = cmd / 32; 4444 bit = cmd % 32; 4445 data[idx] |= 1 << bit; 4446 } 4447 4448 for (i = 0; i < 8; i++) 4449 req.vf_req_fwd[i] = cpu_to_le32(data[i]); 4450 4451 req.enables |= 4452 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD); 4453 } 4454 4455 if (bp->fw_cap & BNXT_FW_CAP_OVS_64BIT_HANDLE) 4456 req.flags |= cpu_to_le32( 4457 FUNC_DRV_RGTR_REQ_FLAGS_FLOW_HANDLE_64BIT_MODE); 4458 4459 memset(async_events_bmap, 0, sizeof(async_events_bmap)); 4460 for (i = 0; i < ARRAY_SIZE(bnxt_async_events_arr); i++) { 4461 u16 event_id = bnxt_async_events_arr[i]; 4462 4463 if (event_id == ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY && 4464 !(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)) 4465 continue; 4466 __set_bit(bnxt_async_events_arr[i], async_events_bmap); 4467 } 4468 if (bmap && bmap_size) { 4469 for (i = 0; i < bmap_size; i++) { 4470 if (test_bit(i, bmap)) 4471 __set_bit(i, async_events_bmap); 4472 } 4473 } 4474 for (i = 0; i < 8; i++) 4475 req.async_event_fwd[i] |= cpu_to_le32(events[i]); 4476 4477 if (async_only) 4478 req.enables = 4479 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD); 4480 4481 mutex_lock(&bp->hwrm_cmd_lock); 4482 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4483 if (!rc) { 4484 set_bit(BNXT_STATE_DRV_REGISTERED, &bp->state); 4485 if (resp->flags & 4486 cpu_to_le32(FUNC_DRV_RGTR_RESP_FLAGS_IF_CHANGE_SUPPORTED)) 4487 bp->fw_cap |= BNXT_FW_CAP_IF_CHANGE; 4488 } 4489 mutex_unlock(&bp->hwrm_cmd_lock); 4490 return rc; 4491 } 4492 4493 static int bnxt_hwrm_func_drv_unrgtr(struct bnxt *bp) 4494 { 4495 struct hwrm_func_drv_unrgtr_input req = {0}; 4496 4497 if (!test_and_clear_bit(BNXT_STATE_DRV_REGISTERED, &bp->state)) 4498 return 0; 4499 4500 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_UNRGTR, -1, -1); 4501 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4502 } 4503 4504 static int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, u8 tunnel_type) 4505 { 4506 u32 rc = 0; 4507 struct hwrm_tunnel_dst_port_free_input req = {0}; 4508 4509 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_FREE, -1, -1); 4510 req.tunnel_type = tunnel_type; 4511 4512 switch (tunnel_type) { 4513 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN: 4514 req.tunnel_dst_port_id = bp->vxlan_fw_dst_port_id; 4515 break; 4516 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE: 4517 req.tunnel_dst_port_id = bp->nge_fw_dst_port_id; 4518 break; 4519 default: 4520 break; 4521 } 4522 4523 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4524 if (rc) 4525 netdev_err(bp->dev, "hwrm_tunnel_dst_port_free failed. rc:%d\n", 4526 rc); 4527 return rc; 4528 } 4529 4530 static int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, __be16 port, 4531 u8 tunnel_type) 4532 { 4533 u32 rc = 0; 4534 struct hwrm_tunnel_dst_port_alloc_input req = {0}; 4535 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr; 4536 4537 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_ALLOC, -1, -1); 4538 4539 req.tunnel_type = tunnel_type; 4540 req.tunnel_dst_port_val = port; 4541 4542 mutex_lock(&bp->hwrm_cmd_lock); 4543 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4544 if (rc) { 4545 netdev_err(bp->dev, "hwrm_tunnel_dst_port_alloc failed. rc:%d\n", 4546 rc); 4547 goto err_out; 4548 } 4549 4550 switch (tunnel_type) { 4551 case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN: 4552 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id; 4553 break; 4554 case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE: 4555 bp->nge_fw_dst_port_id = resp->tunnel_dst_port_id; 4556 break; 4557 default: 4558 break; 4559 } 4560 4561 err_out: 4562 mutex_unlock(&bp->hwrm_cmd_lock); 4563 return rc; 4564 } 4565 4566 static int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp, u16 vnic_id) 4567 { 4568 struct hwrm_cfa_l2_set_rx_mask_input req = {0}; 4569 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 4570 4571 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_SET_RX_MASK, -1, -1); 4572 req.vnic_id = cpu_to_le32(vnic->fw_vnic_id); 4573 4574 req.num_mc_entries = cpu_to_le32(vnic->mc_list_count); 4575 req.mc_tbl_addr = cpu_to_le64(vnic->mc_list_mapping); 4576 req.mask = cpu_to_le32(vnic->rx_mask); 4577 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4578 } 4579 4580 #ifdef CONFIG_RFS_ACCEL 4581 static int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt *bp, 4582 struct bnxt_ntuple_filter *fltr) 4583 { 4584 struct hwrm_cfa_ntuple_filter_free_input req = {0}; 4585 4586 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_FREE, -1, -1); 4587 req.ntuple_filter_id = fltr->filter_id; 4588 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4589 } 4590 4591 #define BNXT_NTP_FLTR_FLAGS \ 4592 (CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID | \ 4593 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE | \ 4594 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR | \ 4595 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE | \ 4596 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR | \ 4597 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK | \ 4598 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR | \ 4599 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK | \ 4600 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL | \ 4601 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT | \ 4602 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK | \ 4603 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT | \ 4604 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK | \ 4605 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID) 4606 4607 #define BNXT_NTP_TUNNEL_FLTR_FLAG \ 4608 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 4609 4610 static int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt *bp, 4611 struct bnxt_ntuple_filter *fltr) 4612 { 4613 struct hwrm_cfa_ntuple_filter_alloc_input req = {0}; 4614 struct hwrm_cfa_ntuple_filter_alloc_output *resp; 4615 struct flow_keys *keys = &fltr->fkeys; 4616 struct bnxt_vnic_info *vnic; 4617 u32 flags = 0; 4618 int rc = 0; 4619 4620 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_ALLOC, -1, -1); 4621 req.l2_filter_id = bp->vnic_info[0].fw_l2_filter_id[fltr->l2_fltr_idx]; 4622 4623 if (bp->fw_cap & BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V2) { 4624 flags = CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DEST_RFS_RING_IDX; 4625 req.dst_id = cpu_to_le16(fltr->rxq); 4626 } else { 4627 vnic = &bp->vnic_info[fltr->rxq + 1]; 4628 req.dst_id = cpu_to_le16(vnic->fw_vnic_id); 4629 } 4630 req.flags = cpu_to_le32(flags); 4631 req.enables = cpu_to_le32(BNXT_NTP_FLTR_FLAGS); 4632 4633 req.ethertype = htons(ETH_P_IP); 4634 memcpy(req.src_macaddr, fltr->src_mac_addr, ETH_ALEN); 4635 req.ip_addr_type = CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4; 4636 req.ip_protocol = keys->basic.ip_proto; 4637 4638 if (keys->basic.n_proto == htons(ETH_P_IPV6)) { 4639 int i; 4640 4641 req.ethertype = htons(ETH_P_IPV6); 4642 req.ip_addr_type = 4643 CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6; 4644 *(struct in6_addr *)&req.src_ipaddr[0] = 4645 keys->addrs.v6addrs.src; 4646 *(struct in6_addr *)&req.dst_ipaddr[0] = 4647 keys->addrs.v6addrs.dst; 4648 for (i = 0; i < 4; i++) { 4649 req.src_ipaddr_mask[i] = cpu_to_be32(0xffffffff); 4650 req.dst_ipaddr_mask[i] = cpu_to_be32(0xffffffff); 4651 } 4652 } else { 4653 req.src_ipaddr[0] = keys->addrs.v4addrs.src; 4654 req.src_ipaddr_mask[0] = cpu_to_be32(0xffffffff); 4655 req.dst_ipaddr[0] = keys->addrs.v4addrs.dst; 4656 req.dst_ipaddr_mask[0] = cpu_to_be32(0xffffffff); 4657 } 4658 if (keys->control.flags & FLOW_DIS_ENCAPSULATION) { 4659 req.enables |= cpu_to_le32(BNXT_NTP_TUNNEL_FLTR_FLAG); 4660 req.tunnel_type = 4661 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL; 4662 } 4663 4664 req.src_port = keys->ports.src; 4665 req.src_port_mask = cpu_to_be16(0xffff); 4666 req.dst_port = keys->ports.dst; 4667 req.dst_port_mask = cpu_to_be16(0xffff); 4668 4669 mutex_lock(&bp->hwrm_cmd_lock); 4670 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4671 if (!rc) { 4672 resp = bnxt_get_hwrm_resp_addr(bp, &req); 4673 fltr->filter_id = resp->ntuple_filter_id; 4674 } 4675 mutex_unlock(&bp->hwrm_cmd_lock); 4676 return rc; 4677 } 4678 #endif 4679 4680 static int bnxt_hwrm_set_vnic_filter(struct bnxt *bp, u16 vnic_id, u16 idx, 4681 u8 *mac_addr) 4682 { 4683 u32 rc = 0; 4684 struct hwrm_cfa_l2_filter_alloc_input req = {0}; 4685 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr; 4686 4687 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_ALLOC, -1, -1); 4688 req.flags = cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX); 4689 if (!BNXT_CHIP_TYPE_NITRO_A0(bp)) 4690 req.flags |= 4691 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST); 4692 req.dst_id = cpu_to_le16(bp->vnic_info[vnic_id].fw_vnic_id); 4693 req.enables = 4694 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR | 4695 CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID | 4696 CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK); 4697 memcpy(req.l2_addr, mac_addr, ETH_ALEN); 4698 req.l2_addr_mask[0] = 0xff; 4699 req.l2_addr_mask[1] = 0xff; 4700 req.l2_addr_mask[2] = 0xff; 4701 req.l2_addr_mask[3] = 0xff; 4702 req.l2_addr_mask[4] = 0xff; 4703 req.l2_addr_mask[5] = 0xff; 4704 4705 mutex_lock(&bp->hwrm_cmd_lock); 4706 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4707 if (!rc) 4708 bp->vnic_info[vnic_id].fw_l2_filter_id[idx] = 4709 resp->l2_filter_id; 4710 mutex_unlock(&bp->hwrm_cmd_lock); 4711 return rc; 4712 } 4713 4714 static int bnxt_hwrm_clear_vnic_filter(struct bnxt *bp) 4715 { 4716 u16 i, j, num_of_vnics = 1; /* only vnic 0 supported */ 4717 int rc = 0; 4718 4719 /* Any associated ntuple filters will also be cleared by firmware. */ 4720 mutex_lock(&bp->hwrm_cmd_lock); 4721 for (i = 0; i < num_of_vnics; i++) { 4722 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 4723 4724 for (j = 0; j < vnic->uc_filter_count; j++) { 4725 struct hwrm_cfa_l2_filter_free_input req = {0}; 4726 4727 bnxt_hwrm_cmd_hdr_init(bp, &req, 4728 HWRM_CFA_L2_FILTER_FREE, -1, -1); 4729 4730 req.l2_filter_id = vnic->fw_l2_filter_id[j]; 4731 4732 rc = _hwrm_send_message(bp, &req, sizeof(req), 4733 HWRM_CMD_TIMEOUT); 4734 } 4735 vnic->uc_filter_count = 0; 4736 } 4737 mutex_unlock(&bp->hwrm_cmd_lock); 4738 4739 return rc; 4740 } 4741 4742 static int bnxt_hwrm_vnic_set_tpa(struct bnxt *bp, u16 vnic_id, u32 tpa_flags) 4743 { 4744 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 4745 u16 max_aggs = VNIC_TPA_CFG_REQ_MAX_AGGS_MAX; 4746 struct hwrm_vnic_tpa_cfg_input req = {0}; 4747 4748 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) 4749 return 0; 4750 4751 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_TPA_CFG, -1, -1); 4752 4753 if (tpa_flags) { 4754 u16 mss = bp->dev->mtu - 40; 4755 u32 nsegs, n, segs = 0, flags; 4756 4757 flags = VNIC_TPA_CFG_REQ_FLAGS_TPA | 4758 VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA | 4759 VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE | 4760 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN | 4761 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ; 4762 if (tpa_flags & BNXT_FLAG_GRO) 4763 flags |= VNIC_TPA_CFG_REQ_FLAGS_GRO; 4764 4765 req.flags = cpu_to_le32(flags); 4766 4767 req.enables = 4768 cpu_to_le32(VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS | 4769 VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS | 4770 VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN); 4771 4772 /* Number of segs are log2 units, and first packet is not 4773 * included as part of this units. 4774 */ 4775 if (mss <= BNXT_RX_PAGE_SIZE) { 4776 n = BNXT_RX_PAGE_SIZE / mss; 4777 nsegs = (MAX_SKB_FRAGS - 1) * n; 4778 } else { 4779 n = mss / BNXT_RX_PAGE_SIZE; 4780 if (mss & (BNXT_RX_PAGE_SIZE - 1)) 4781 n++; 4782 nsegs = (MAX_SKB_FRAGS - n) / n; 4783 } 4784 4785 if (bp->flags & BNXT_FLAG_CHIP_P5) { 4786 segs = MAX_TPA_SEGS_P5; 4787 max_aggs = bp->max_tpa; 4788 } else { 4789 segs = ilog2(nsegs); 4790 } 4791 req.max_agg_segs = cpu_to_le16(segs); 4792 req.max_aggs = cpu_to_le16(max_aggs); 4793 4794 req.min_agg_len = cpu_to_le32(512); 4795 } 4796 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id); 4797 4798 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4799 } 4800 4801 static u16 bnxt_cp_ring_from_grp(struct bnxt *bp, struct bnxt_ring_struct *ring) 4802 { 4803 struct bnxt_ring_grp_info *grp_info; 4804 4805 grp_info = &bp->grp_info[ring->grp_idx]; 4806 return grp_info->cp_fw_ring_id; 4807 } 4808 4809 static u16 bnxt_cp_ring_for_rx(struct bnxt *bp, struct bnxt_rx_ring_info *rxr) 4810 { 4811 if (bp->flags & BNXT_FLAG_CHIP_P5) { 4812 struct bnxt_napi *bnapi = rxr->bnapi; 4813 struct bnxt_cp_ring_info *cpr; 4814 4815 cpr = bnapi->cp_ring.cp_ring_arr[BNXT_RX_HDL]; 4816 return cpr->cp_ring_struct.fw_ring_id; 4817 } else { 4818 return bnxt_cp_ring_from_grp(bp, &rxr->rx_ring_struct); 4819 } 4820 } 4821 4822 static u16 bnxt_cp_ring_for_tx(struct bnxt *bp, struct bnxt_tx_ring_info *txr) 4823 { 4824 if (bp->flags & BNXT_FLAG_CHIP_P5) { 4825 struct bnxt_napi *bnapi = txr->bnapi; 4826 struct bnxt_cp_ring_info *cpr; 4827 4828 cpr = bnapi->cp_ring.cp_ring_arr[BNXT_TX_HDL]; 4829 return cpr->cp_ring_struct.fw_ring_id; 4830 } else { 4831 return bnxt_cp_ring_from_grp(bp, &txr->tx_ring_struct); 4832 } 4833 } 4834 4835 static int bnxt_hwrm_vnic_set_rss(struct bnxt *bp, u16 vnic_id, bool set_rss) 4836 { 4837 u32 i, j, max_rings; 4838 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 4839 struct hwrm_vnic_rss_cfg_input req = {0}; 4840 4841 if ((bp->flags & BNXT_FLAG_CHIP_P5) || 4842 vnic->fw_rss_cos_lb_ctx[0] == INVALID_HW_RING_ID) 4843 return 0; 4844 4845 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1); 4846 if (set_rss) { 4847 req.hash_type = cpu_to_le32(bp->rss_hash_cfg); 4848 req.hash_mode_flags = VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT; 4849 if (vnic->flags & BNXT_VNIC_RSS_FLAG) { 4850 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 4851 max_rings = bp->rx_nr_rings - 1; 4852 else 4853 max_rings = bp->rx_nr_rings; 4854 } else { 4855 max_rings = 1; 4856 } 4857 4858 /* Fill the RSS indirection table with ring group ids */ 4859 for (i = 0, j = 0; i < HW_HASH_INDEX_SIZE; i++, j++) { 4860 if (j == max_rings) 4861 j = 0; 4862 vnic->rss_table[i] = cpu_to_le16(vnic->fw_grp_ids[j]); 4863 } 4864 4865 req.ring_grp_tbl_addr = cpu_to_le64(vnic->rss_table_dma_addr); 4866 req.hash_key_tbl_addr = 4867 cpu_to_le64(vnic->rss_hash_key_dma_addr); 4868 } 4869 req.rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]); 4870 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4871 } 4872 4873 static int bnxt_hwrm_vnic_set_rss_p5(struct bnxt *bp, u16 vnic_id, bool set_rss) 4874 { 4875 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 4876 u32 i, j, k, nr_ctxs, max_rings = bp->rx_nr_rings; 4877 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[0]; 4878 struct hwrm_vnic_rss_cfg_input req = {0}; 4879 4880 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1); 4881 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id); 4882 if (!set_rss) { 4883 hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4884 return 0; 4885 } 4886 req.hash_type = cpu_to_le32(bp->rss_hash_cfg); 4887 req.hash_mode_flags = VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT; 4888 req.ring_grp_tbl_addr = cpu_to_le64(vnic->rss_table_dma_addr); 4889 req.hash_key_tbl_addr = cpu_to_le64(vnic->rss_hash_key_dma_addr); 4890 nr_ctxs = DIV_ROUND_UP(bp->rx_nr_rings, 64); 4891 for (i = 0, k = 0; i < nr_ctxs; i++) { 4892 __le16 *ring_tbl = vnic->rss_table; 4893 int rc; 4894 4895 req.ring_table_pair_index = i; 4896 req.rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[i]); 4897 for (j = 0; j < 64; j++) { 4898 u16 ring_id; 4899 4900 ring_id = rxr->rx_ring_struct.fw_ring_id; 4901 *ring_tbl++ = cpu_to_le16(ring_id); 4902 ring_id = bnxt_cp_ring_for_rx(bp, rxr); 4903 *ring_tbl++ = cpu_to_le16(ring_id); 4904 rxr++; 4905 k++; 4906 if (k == max_rings) { 4907 k = 0; 4908 rxr = &bp->rx_ring[0]; 4909 } 4910 } 4911 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4912 if (rc) 4913 return rc; 4914 } 4915 return 0; 4916 } 4917 4918 static int bnxt_hwrm_vnic_set_hds(struct bnxt *bp, u16 vnic_id) 4919 { 4920 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 4921 struct hwrm_vnic_plcmodes_cfg_input req = {0}; 4922 4923 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_PLCMODES_CFG, -1, -1); 4924 req.flags = cpu_to_le32(VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT | 4925 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 | 4926 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6); 4927 req.enables = 4928 cpu_to_le32(VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID | 4929 VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID); 4930 /* thresholds not implemented in firmware yet */ 4931 req.jumbo_thresh = cpu_to_le16(bp->rx_copy_thresh); 4932 req.hds_threshold = cpu_to_le16(bp->rx_copy_thresh); 4933 req.vnic_id = cpu_to_le32(vnic->fw_vnic_id); 4934 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4935 } 4936 4937 static void bnxt_hwrm_vnic_ctx_free_one(struct bnxt *bp, u16 vnic_id, 4938 u16 ctx_idx) 4939 { 4940 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {0}; 4941 4942 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, -1, -1); 4943 req.rss_cos_lb_ctx_id = 4944 cpu_to_le16(bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx]); 4945 4946 hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4947 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] = INVALID_HW_RING_ID; 4948 } 4949 4950 static void bnxt_hwrm_vnic_ctx_free(struct bnxt *bp) 4951 { 4952 int i, j; 4953 4954 for (i = 0; i < bp->nr_vnics; i++) { 4955 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 4956 4957 for (j = 0; j < BNXT_MAX_CTX_PER_VNIC; j++) { 4958 if (vnic->fw_rss_cos_lb_ctx[j] != INVALID_HW_RING_ID) 4959 bnxt_hwrm_vnic_ctx_free_one(bp, i, j); 4960 } 4961 } 4962 bp->rsscos_nr_ctxs = 0; 4963 } 4964 4965 static int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, u16 vnic_id, u16 ctx_idx) 4966 { 4967 int rc; 4968 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {0}; 4969 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp = 4970 bp->hwrm_cmd_resp_addr; 4971 4972 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, -1, 4973 -1); 4974 4975 mutex_lock(&bp->hwrm_cmd_lock); 4976 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4977 if (!rc) 4978 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] = 4979 le16_to_cpu(resp->rss_cos_lb_ctx_id); 4980 mutex_unlock(&bp->hwrm_cmd_lock); 4981 4982 return rc; 4983 } 4984 4985 static u32 bnxt_get_roce_vnic_mode(struct bnxt *bp) 4986 { 4987 if (bp->flags & BNXT_FLAG_ROCE_MIRROR_CAP) 4988 return VNIC_CFG_REQ_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE; 4989 return VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE; 4990 } 4991 4992 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id) 4993 { 4994 unsigned int ring = 0, grp_idx; 4995 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 4996 struct hwrm_vnic_cfg_input req = {0}; 4997 u16 def_vlan = 0; 4998 4999 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_CFG, -1, -1); 5000 5001 if (bp->flags & BNXT_FLAG_CHIP_P5) { 5002 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[0]; 5003 5004 req.default_rx_ring_id = 5005 cpu_to_le16(rxr->rx_ring_struct.fw_ring_id); 5006 req.default_cmpl_ring_id = 5007 cpu_to_le16(bnxt_cp_ring_for_rx(bp, rxr)); 5008 req.enables = 5009 cpu_to_le32(VNIC_CFG_REQ_ENABLES_DEFAULT_RX_RING_ID | 5010 VNIC_CFG_REQ_ENABLES_DEFAULT_CMPL_RING_ID); 5011 goto vnic_mru; 5012 } 5013 req.enables = cpu_to_le32(VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP); 5014 /* Only RSS support for now TBD: COS & LB */ 5015 if (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID) { 5016 req.rss_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]); 5017 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE | 5018 VNIC_CFG_REQ_ENABLES_MRU); 5019 } else if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG) { 5020 req.rss_rule = 5021 cpu_to_le16(bp->vnic_info[0].fw_rss_cos_lb_ctx[0]); 5022 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE | 5023 VNIC_CFG_REQ_ENABLES_MRU); 5024 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE); 5025 } else { 5026 req.rss_rule = cpu_to_le16(0xffff); 5027 } 5028 5029 if (BNXT_CHIP_TYPE_NITRO_A0(bp) && 5030 (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID)) { 5031 req.cos_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[1]); 5032 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_COS_RULE); 5033 } else { 5034 req.cos_rule = cpu_to_le16(0xffff); 5035 } 5036 5037 if (vnic->flags & BNXT_VNIC_RSS_FLAG) 5038 ring = 0; 5039 else if (vnic->flags & BNXT_VNIC_RFS_FLAG) 5040 ring = vnic_id - 1; 5041 else if ((vnic_id == 1) && BNXT_CHIP_TYPE_NITRO_A0(bp)) 5042 ring = bp->rx_nr_rings - 1; 5043 5044 grp_idx = bp->rx_ring[ring].bnapi->index; 5045 req.dflt_ring_grp = cpu_to_le16(bp->grp_info[grp_idx].fw_grp_id); 5046 req.lb_rule = cpu_to_le16(0xffff); 5047 vnic_mru: 5048 req.mru = cpu_to_le16(bp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + 5049 VLAN_HLEN); 5050 5051 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id); 5052 #ifdef CONFIG_BNXT_SRIOV 5053 if (BNXT_VF(bp)) 5054 def_vlan = bp->vf.vlan; 5055 #endif 5056 if ((bp->flags & BNXT_FLAG_STRIP_VLAN) || def_vlan) 5057 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE); 5058 if (!vnic_id && bnxt_ulp_registered(bp->edev, BNXT_ROCE_ULP)) 5059 req.flags |= cpu_to_le32(bnxt_get_roce_vnic_mode(bp)); 5060 5061 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5062 } 5063 5064 static void bnxt_hwrm_vnic_free_one(struct bnxt *bp, u16 vnic_id) 5065 { 5066 if (bp->vnic_info[vnic_id].fw_vnic_id != INVALID_HW_RING_ID) { 5067 struct hwrm_vnic_free_input req = {0}; 5068 5069 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_FREE, -1, -1); 5070 req.vnic_id = 5071 cpu_to_le32(bp->vnic_info[vnic_id].fw_vnic_id); 5072 5073 hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5074 bp->vnic_info[vnic_id].fw_vnic_id = INVALID_HW_RING_ID; 5075 } 5076 } 5077 5078 static void bnxt_hwrm_vnic_free(struct bnxt *bp) 5079 { 5080 u16 i; 5081 5082 for (i = 0; i < bp->nr_vnics; i++) 5083 bnxt_hwrm_vnic_free_one(bp, i); 5084 } 5085 5086 static int bnxt_hwrm_vnic_alloc(struct bnxt *bp, u16 vnic_id, 5087 unsigned int start_rx_ring_idx, 5088 unsigned int nr_rings) 5089 { 5090 int rc = 0; 5091 unsigned int i, j, grp_idx, end_idx = start_rx_ring_idx + nr_rings; 5092 struct hwrm_vnic_alloc_input req = {0}; 5093 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr; 5094 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 5095 5096 if (bp->flags & BNXT_FLAG_CHIP_P5) 5097 goto vnic_no_ring_grps; 5098 5099 /* map ring groups to this vnic */ 5100 for (i = start_rx_ring_idx, j = 0; i < end_idx; i++, j++) { 5101 grp_idx = bp->rx_ring[i].bnapi->index; 5102 if (bp->grp_info[grp_idx].fw_grp_id == INVALID_HW_RING_ID) { 5103 netdev_err(bp->dev, "Not enough ring groups avail:%x req:%x\n", 5104 j, nr_rings); 5105 break; 5106 } 5107 vnic->fw_grp_ids[j] = bp->grp_info[grp_idx].fw_grp_id; 5108 } 5109 5110 vnic_no_ring_grps: 5111 for (i = 0; i < BNXT_MAX_CTX_PER_VNIC; i++) 5112 vnic->fw_rss_cos_lb_ctx[i] = INVALID_HW_RING_ID; 5113 if (vnic_id == 0) 5114 req.flags = cpu_to_le32(VNIC_ALLOC_REQ_FLAGS_DEFAULT); 5115 5116 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_ALLOC, -1, -1); 5117 5118 mutex_lock(&bp->hwrm_cmd_lock); 5119 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5120 if (!rc) 5121 vnic->fw_vnic_id = le32_to_cpu(resp->vnic_id); 5122 mutex_unlock(&bp->hwrm_cmd_lock); 5123 return rc; 5124 } 5125 5126 static int bnxt_hwrm_vnic_qcaps(struct bnxt *bp) 5127 { 5128 struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr; 5129 struct hwrm_vnic_qcaps_input req = {0}; 5130 int rc; 5131 5132 bp->hw_ring_stats_size = sizeof(struct ctx_hw_stats); 5133 bp->flags &= ~(BNXT_FLAG_NEW_RSS_CAP | BNXT_FLAG_ROCE_MIRROR_CAP); 5134 if (bp->hwrm_spec_code < 0x10600) 5135 return 0; 5136 5137 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_QCAPS, -1, -1); 5138 mutex_lock(&bp->hwrm_cmd_lock); 5139 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5140 if (!rc) { 5141 u32 flags = le32_to_cpu(resp->flags); 5142 5143 if (!(bp->flags & BNXT_FLAG_CHIP_P5) && 5144 (flags & VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP)) 5145 bp->flags |= BNXT_FLAG_NEW_RSS_CAP; 5146 if (flags & 5147 VNIC_QCAPS_RESP_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP) 5148 bp->flags |= BNXT_FLAG_ROCE_MIRROR_CAP; 5149 bp->max_tpa_v2 = le16_to_cpu(resp->max_aggs_supported); 5150 if (bp->max_tpa_v2) 5151 bp->hw_ring_stats_size = 5152 sizeof(struct ctx_hw_stats_ext); 5153 } 5154 mutex_unlock(&bp->hwrm_cmd_lock); 5155 return rc; 5156 } 5157 5158 static int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp) 5159 { 5160 u16 i; 5161 u32 rc = 0; 5162 5163 if (bp->flags & BNXT_FLAG_CHIP_P5) 5164 return 0; 5165 5166 mutex_lock(&bp->hwrm_cmd_lock); 5167 for (i = 0; i < bp->rx_nr_rings; i++) { 5168 struct hwrm_ring_grp_alloc_input req = {0}; 5169 struct hwrm_ring_grp_alloc_output *resp = 5170 bp->hwrm_cmd_resp_addr; 5171 unsigned int grp_idx = bp->rx_ring[i].bnapi->index; 5172 5173 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_ALLOC, -1, -1); 5174 5175 req.cr = cpu_to_le16(bp->grp_info[grp_idx].cp_fw_ring_id); 5176 req.rr = cpu_to_le16(bp->grp_info[grp_idx].rx_fw_ring_id); 5177 req.ar = cpu_to_le16(bp->grp_info[grp_idx].agg_fw_ring_id); 5178 req.sc = cpu_to_le16(bp->grp_info[grp_idx].fw_stats_ctx); 5179 5180 rc = _hwrm_send_message(bp, &req, sizeof(req), 5181 HWRM_CMD_TIMEOUT); 5182 if (rc) 5183 break; 5184 5185 bp->grp_info[grp_idx].fw_grp_id = 5186 le32_to_cpu(resp->ring_group_id); 5187 } 5188 mutex_unlock(&bp->hwrm_cmd_lock); 5189 return rc; 5190 } 5191 5192 static void bnxt_hwrm_ring_grp_free(struct bnxt *bp) 5193 { 5194 u16 i; 5195 struct hwrm_ring_grp_free_input req = {0}; 5196 5197 if (!bp->grp_info || (bp->flags & BNXT_FLAG_CHIP_P5)) 5198 return; 5199 5200 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_FREE, -1, -1); 5201 5202 mutex_lock(&bp->hwrm_cmd_lock); 5203 for (i = 0; i < bp->cp_nr_rings; i++) { 5204 if (bp->grp_info[i].fw_grp_id == INVALID_HW_RING_ID) 5205 continue; 5206 req.ring_group_id = 5207 cpu_to_le32(bp->grp_info[i].fw_grp_id); 5208 5209 _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5210 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID; 5211 } 5212 mutex_unlock(&bp->hwrm_cmd_lock); 5213 } 5214 5215 static int hwrm_ring_alloc_send_msg(struct bnxt *bp, 5216 struct bnxt_ring_struct *ring, 5217 u32 ring_type, u32 map_index) 5218 { 5219 int rc = 0, err = 0; 5220 struct hwrm_ring_alloc_input req = {0}; 5221 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr; 5222 struct bnxt_ring_mem_info *rmem = &ring->ring_mem; 5223 struct bnxt_ring_grp_info *grp_info; 5224 u16 ring_id; 5225 5226 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_ALLOC, -1, -1); 5227 5228 req.enables = 0; 5229 if (rmem->nr_pages > 1) { 5230 req.page_tbl_addr = cpu_to_le64(rmem->pg_tbl_map); 5231 /* Page size is in log2 units */ 5232 req.page_size = BNXT_PAGE_SHIFT; 5233 req.page_tbl_depth = 1; 5234 } else { 5235 req.page_tbl_addr = cpu_to_le64(rmem->dma_arr[0]); 5236 } 5237 req.fbo = 0; 5238 /* Association of ring index with doorbell index and MSIX number */ 5239 req.logical_id = cpu_to_le16(map_index); 5240 5241 switch (ring_type) { 5242 case HWRM_RING_ALLOC_TX: { 5243 struct bnxt_tx_ring_info *txr; 5244 5245 txr = container_of(ring, struct bnxt_tx_ring_info, 5246 tx_ring_struct); 5247 req.ring_type = RING_ALLOC_REQ_RING_TYPE_TX; 5248 /* Association of transmit ring with completion ring */ 5249 grp_info = &bp->grp_info[ring->grp_idx]; 5250 req.cmpl_ring_id = cpu_to_le16(bnxt_cp_ring_for_tx(bp, txr)); 5251 req.length = cpu_to_le32(bp->tx_ring_mask + 1); 5252 req.stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx); 5253 req.queue_id = cpu_to_le16(ring->queue_id); 5254 break; 5255 } 5256 case HWRM_RING_ALLOC_RX: 5257 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX; 5258 req.length = cpu_to_le32(bp->rx_ring_mask + 1); 5259 if (bp->flags & BNXT_FLAG_CHIP_P5) { 5260 u16 flags = 0; 5261 5262 /* Association of rx ring with stats context */ 5263 grp_info = &bp->grp_info[ring->grp_idx]; 5264 req.rx_buf_size = cpu_to_le16(bp->rx_buf_use_size); 5265 req.stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx); 5266 req.enables |= cpu_to_le32( 5267 RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID); 5268 if (NET_IP_ALIGN == 2) 5269 flags = RING_ALLOC_REQ_FLAGS_RX_SOP_PAD; 5270 req.flags = cpu_to_le16(flags); 5271 } 5272 break; 5273 case HWRM_RING_ALLOC_AGG: 5274 if (bp->flags & BNXT_FLAG_CHIP_P5) { 5275 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX_AGG; 5276 /* Association of agg ring with rx ring */ 5277 grp_info = &bp->grp_info[ring->grp_idx]; 5278 req.rx_ring_id = cpu_to_le16(grp_info->rx_fw_ring_id); 5279 req.rx_buf_size = cpu_to_le16(BNXT_RX_PAGE_SIZE); 5280 req.stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx); 5281 req.enables |= cpu_to_le32( 5282 RING_ALLOC_REQ_ENABLES_RX_RING_ID_VALID | 5283 RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID); 5284 } else { 5285 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX; 5286 } 5287 req.length = cpu_to_le32(bp->rx_agg_ring_mask + 1); 5288 break; 5289 case HWRM_RING_ALLOC_CMPL: 5290 req.ring_type = RING_ALLOC_REQ_RING_TYPE_L2_CMPL; 5291 req.length = cpu_to_le32(bp->cp_ring_mask + 1); 5292 if (bp->flags & BNXT_FLAG_CHIP_P5) { 5293 /* Association of cp ring with nq */ 5294 grp_info = &bp->grp_info[map_index]; 5295 req.nq_ring_id = cpu_to_le16(grp_info->cp_fw_ring_id); 5296 req.cq_handle = cpu_to_le64(ring->handle); 5297 req.enables |= cpu_to_le32( 5298 RING_ALLOC_REQ_ENABLES_NQ_RING_ID_VALID); 5299 } else if (bp->flags & BNXT_FLAG_USING_MSIX) { 5300 req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX; 5301 } 5302 break; 5303 case HWRM_RING_ALLOC_NQ: 5304 req.ring_type = RING_ALLOC_REQ_RING_TYPE_NQ; 5305 req.length = cpu_to_le32(bp->cp_ring_mask + 1); 5306 if (bp->flags & BNXT_FLAG_USING_MSIX) 5307 req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX; 5308 break; 5309 default: 5310 netdev_err(bp->dev, "hwrm alloc invalid ring type %d\n", 5311 ring_type); 5312 return -1; 5313 } 5314 5315 mutex_lock(&bp->hwrm_cmd_lock); 5316 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5317 err = le16_to_cpu(resp->error_code); 5318 ring_id = le16_to_cpu(resp->ring_id); 5319 mutex_unlock(&bp->hwrm_cmd_lock); 5320 5321 if (rc || err) { 5322 netdev_err(bp->dev, "hwrm_ring_alloc type %d failed. rc:%x err:%x\n", 5323 ring_type, rc, err); 5324 return -EIO; 5325 } 5326 ring->fw_ring_id = ring_id; 5327 return rc; 5328 } 5329 5330 static int bnxt_hwrm_set_async_event_cr(struct bnxt *bp, int idx) 5331 { 5332 int rc; 5333 5334 if (BNXT_PF(bp)) { 5335 struct hwrm_func_cfg_input req = {0}; 5336 5337 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1); 5338 req.fid = cpu_to_le16(0xffff); 5339 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR); 5340 req.async_event_cr = cpu_to_le16(idx); 5341 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5342 } else { 5343 struct hwrm_func_vf_cfg_input req = {0}; 5344 5345 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_VF_CFG, -1, -1); 5346 req.enables = 5347 cpu_to_le32(FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR); 5348 req.async_event_cr = cpu_to_le16(idx); 5349 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5350 } 5351 return rc; 5352 } 5353 5354 static void bnxt_set_db(struct bnxt *bp, struct bnxt_db_info *db, u32 ring_type, 5355 u32 map_idx, u32 xid) 5356 { 5357 if (bp->flags & BNXT_FLAG_CHIP_P5) { 5358 if (BNXT_PF(bp)) 5359 db->doorbell = bp->bar1 + 0x10000; 5360 else 5361 db->doorbell = bp->bar1 + 0x4000; 5362 switch (ring_type) { 5363 case HWRM_RING_ALLOC_TX: 5364 db->db_key64 = DBR_PATH_L2 | DBR_TYPE_SQ; 5365 break; 5366 case HWRM_RING_ALLOC_RX: 5367 case HWRM_RING_ALLOC_AGG: 5368 db->db_key64 = DBR_PATH_L2 | DBR_TYPE_SRQ; 5369 break; 5370 case HWRM_RING_ALLOC_CMPL: 5371 db->db_key64 = DBR_PATH_L2; 5372 break; 5373 case HWRM_RING_ALLOC_NQ: 5374 db->db_key64 = DBR_PATH_L2; 5375 break; 5376 } 5377 db->db_key64 |= (u64)xid << DBR_XID_SFT; 5378 } else { 5379 db->doorbell = bp->bar1 + map_idx * 0x80; 5380 switch (ring_type) { 5381 case HWRM_RING_ALLOC_TX: 5382 db->db_key32 = DB_KEY_TX; 5383 break; 5384 case HWRM_RING_ALLOC_RX: 5385 case HWRM_RING_ALLOC_AGG: 5386 db->db_key32 = DB_KEY_RX; 5387 break; 5388 case HWRM_RING_ALLOC_CMPL: 5389 db->db_key32 = DB_KEY_CP; 5390 break; 5391 } 5392 } 5393 } 5394 5395 static int bnxt_hwrm_ring_alloc(struct bnxt *bp) 5396 { 5397 bool agg_rings = !!(bp->flags & BNXT_FLAG_AGG_RINGS); 5398 int i, rc = 0; 5399 u32 type; 5400 5401 if (bp->flags & BNXT_FLAG_CHIP_P5) 5402 type = HWRM_RING_ALLOC_NQ; 5403 else 5404 type = HWRM_RING_ALLOC_CMPL; 5405 for (i = 0; i < bp->cp_nr_rings; i++) { 5406 struct bnxt_napi *bnapi = bp->bnapi[i]; 5407 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 5408 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct; 5409 u32 map_idx = ring->map_idx; 5410 unsigned int vector; 5411 5412 vector = bp->irq_tbl[map_idx].vector; 5413 disable_irq_nosync(vector); 5414 rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx); 5415 if (rc) { 5416 enable_irq(vector); 5417 goto err_out; 5418 } 5419 bnxt_set_db(bp, &cpr->cp_db, type, map_idx, ring->fw_ring_id); 5420 bnxt_db_nq(bp, &cpr->cp_db, cpr->cp_raw_cons); 5421 enable_irq(vector); 5422 bp->grp_info[i].cp_fw_ring_id = ring->fw_ring_id; 5423 5424 if (!i) { 5425 rc = bnxt_hwrm_set_async_event_cr(bp, ring->fw_ring_id); 5426 if (rc) 5427 netdev_warn(bp->dev, "Failed to set async event completion ring.\n"); 5428 } 5429 } 5430 5431 type = HWRM_RING_ALLOC_TX; 5432 for (i = 0; i < bp->tx_nr_rings; i++) { 5433 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; 5434 struct bnxt_ring_struct *ring; 5435 u32 map_idx; 5436 5437 if (bp->flags & BNXT_FLAG_CHIP_P5) { 5438 struct bnxt_napi *bnapi = txr->bnapi; 5439 struct bnxt_cp_ring_info *cpr, *cpr2; 5440 u32 type2 = HWRM_RING_ALLOC_CMPL; 5441 5442 cpr = &bnapi->cp_ring; 5443 cpr2 = cpr->cp_ring_arr[BNXT_TX_HDL]; 5444 ring = &cpr2->cp_ring_struct; 5445 ring->handle = BNXT_TX_HDL; 5446 map_idx = bnapi->index; 5447 rc = hwrm_ring_alloc_send_msg(bp, ring, type2, map_idx); 5448 if (rc) 5449 goto err_out; 5450 bnxt_set_db(bp, &cpr2->cp_db, type2, map_idx, 5451 ring->fw_ring_id); 5452 bnxt_db_cq(bp, &cpr2->cp_db, cpr2->cp_raw_cons); 5453 } 5454 ring = &txr->tx_ring_struct; 5455 map_idx = i; 5456 rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx); 5457 if (rc) 5458 goto err_out; 5459 bnxt_set_db(bp, &txr->tx_db, type, map_idx, ring->fw_ring_id); 5460 } 5461 5462 type = HWRM_RING_ALLOC_RX; 5463 for (i = 0; i < bp->rx_nr_rings; i++) { 5464 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 5465 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct; 5466 struct bnxt_napi *bnapi = rxr->bnapi; 5467 u32 map_idx = bnapi->index; 5468 5469 rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx); 5470 if (rc) 5471 goto err_out; 5472 bnxt_set_db(bp, &rxr->rx_db, type, map_idx, ring->fw_ring_id); 5473 /* If we have agg rings, post agg buffers first. */ 5474 if (!agg_rings) 5475 bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod); 5476 bp->grp_info[map_idx].rx_fw_ring_id = ring->fw_ring_id; 5477 if (bp->flags & BNXT_FLAG_CHIP_P5) { 5478 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 5479 u32 type2 = HWRM_RING_ALLOC_CMPL; 5480 struct bnxt_cp_ring_info *cpr2; 5481 5482 cpr2 = cpr->cp_ring_arr[BNXT_RX_HDL]; 5483 ring = &cpr2->cp_ring_struct; 5484 ring->handle = BNXT_RX_HDL; 5485 rc = hwrm_ring_alloc_send_msg(bp, ring, type2, map_idx); 5486 if (rc) 5487 goto err_out; 5488 bnxt_set_db(bp, &cpr2->cp_db, type2, map_idx, 5489 ring->fw_ring_id); 5490 bnxt_db_cq(bp, &cpr2->cp_db, cpr2->cp_raw_cons); 5491 } 5492 } 5493 5494 if (agg_rings) { 5495 type = HWRM_RING_ALLOC_AGG; 5496 for (i = 0; i < bp->rx_nr_rings; i++) { 5497 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 5498 struct bnxt_ring_struct *ring = 5499 &rxr->rx_agg_ring_struct; 5500 u32 grp_idx = ring->grp_idx; 5501 u32 map_idx = grp_idx + bp->rx_nr_rings; 5502 5503 rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx); 5504 if (rc) 5505 goto err_out; 5506 5507 bnxt_set_db(bp, &rxr->rx_agg_db, type, map_idx, 5508 ring->fw_ring_id); 5509 bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod); 5510 bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod); 5511 bp->grp_info[grp_idx].agg_fw_ring_id = ring->fw_ring_id; 5512 } 5513 } 5514 err_out: 5515 return rc; 5516 } 5517 5518 static int hwrm_ring_free_send_msg(struct bnxt *bp, 5519 struct bnxt_ring_struct *ring, 5520 u32 ring_type, int cmpl_ring_id) 5521 { 5522 int rc; 5523 struct hwrm_ring_free_input req = {0}; 5524 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr; 5525 u16 error_code; 5526 5527 if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state)) 5528 return 0; 5529 5530 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_FREE, cmpl_ring_id, -1); 5531 req.ring_type = ring_type; 5532 req.ring_id = cpu_to_le16(ring->fw_ring_id); 5533 5534 mutex_lock(&bp->hwrm_cmd_lock); 5535 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5536 error_code = le16_to_cpu(resp->error_code); 5537 mutex_unlock(&bp->hwrm_cmd_lock); 5538 5539 if (rc || error_code) { 5540 netdev_err(bp->dev, "hwrm_ring_free type %d failed. rc:%x err:%x\n", 5541 ring_type, rc, error_code); 5542 return -EIO; 5543 } 5544 return 0; 5545 } 5546 5547 static void bnxt_hwrm_ring_free(struct bnxt *bp, bool close_path) 5548 { 5549 u32 type; 5550 int i; 5551 5552 if (!bp->bnapi) 5553 return; 5554 5555 for (i = 0; i < bp->tx_nr_rings; i++) { 5556 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; 5557 struct bnxt_ring_struct *ring = &txr->tx_ring_struct; 5558 5559 if (ring->fw_ring_id != INVALID_HW_RING_ID) { 5560 u32 cmpl_ring_id = bnxt_cp_ring_for_tx(bp, txr); 5561 5562 hwrm_ring_free_send_msg(bp, ring, 5563 RING_FREE_REQ_RING_TYPE_TX, 5564 close_path ? cmpl_ring_id : 5565 INVALID_HW_RING_ID); 5566 ring->fw_ring_id = INVALID_HW_RING_ID; 5567 } 5568 } 5569 5570 for (i = 0; i < bp->rx_nr_rings; i++) { 5571 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 5572 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct; 5573 u32 grp_idx = rxr->bnapi->index; 5574 5575 if (ring->fw_ring_id != INVALID_HW_RING_ID) { 5576 u32 cmpl_ring_id = bnxt_cp_ring_for_rx(bp, rxr); 5577 5578 hwrm_ring_free_send_msg(bp, ring, 5579 RING_FREE_REQ_RING_TYPE_RX, 5580 close_path ? cmpl_ring_id : 5581 INVALID_HW_RING_ID); 5582 ring->fw_ring_id = INVALID_HW_RING_ID; 5583 bp->grp_info[grp_idx].rx_fw_ring_id = 5584 INVALID_HW_RING_ID; 5585 } 5586 } 5587 5588 if (bp->flags & BNXT_FLAG_CHIP_P5) 5589 type = RING_FREE_REQ_RING_TYPE_RX_AGG; 5590 else 5591 type = RING_FREE_REQ_RING_TYPE_RX; 5592 for (i = 0; i < bp->rx_nr_rings; i++) { 5593 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 5594 struct bnxt_ring_struct *ring = &rxr->rx_agg_ring_struct; 5595 u32 grp_idx = rxr->bnapi->index; 5596 5597 if (ring->fw_ring_id != INVALID_HW_RING_ID) { 5598 u32 cmpl_ring_id = bnxt_cp_ring_for_rx(bp, rxr); 5599 5600 hwrm_ring_free_send_msg(bp, ring, type, 5601 close_path ? cmpl_ring_id : 5602 INVALID_HW_RING_ID); 5603 ring->fw_ring_id = INVALID_HW_RING_ID; 5604 bp->grp_info[grp_idx].agg_fw_ring_id = 5605 INVALID_HW_RING_ID; 5606 } 5607 } 5608 5609 /* The completion rings are about to be freed. After that the 5610 * IRQ doorbell will not work anymore. So we need to disable 5611 * IRQ here. 5612 */ 5613 bnxt_disable_int_sync(bp); 5614 5615 if (bp->flags & BNXT_FLAG_CHIP_P5) 5616 type = RING_FREE_REQ_RING_TYPE_NQ; 5617 else 5618 type = RING_FREE_REQ_RING_TYPE_L2_CMPL; 5619 for (i = 0; i < bp->cp_nr_rings; i++) { 5620 struct bnxt_napi *bnapi = bp->bnapi[i]; 5621 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 5622 struct bnxt_ring_struct *ring; 5623 int j; 5624 5625 for (j = 0; j < 2; j++) { 5626 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j]; 5627 5628 if (cpr2) { 5629 ring = &cpr2->cp_ring_struct; 5630 if (ring->fw_ring_id == INVALID_HW_RING_ID) 5631 continue; 5632 hwrm_ring_free_send_msg(bp, ring, 5633 RING_FREE_REQ_RING_TYPE_L2_CMPL, 5634 INVALID_HW_RING_ID); 5635 ring->fw_ring_id = INVALID_HW_RING_ID; 5636 } 5637 } 5638 ring = &cpr->cp_ring_struct; 5639 if (ring->fw_ring_id != INVALID_HW_RING_ID) { 5640 hwrm_ring_free_send_msg(bp, ring, type, 5641 INVALID_HW_RING_ID); 5642 ring->fw_ring_id = INVALID_HW_RING_ID; 5643 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID; 5644 } 5645 } 5646 } 5647 5648 static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max, 5649 bool shared); 5650 5651 static int bnxt_hwrm_get_rings(struct bnxt *bp) 5652 { 5653 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr; 5654 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 5655 struct hwrm_func_qcfg_input req = {0}; 5656 int rc; 5657 5658 if (bp->hwrm_spec_code < 0x10601) 5659 return 0; 5660 5661 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1); 5662 req.fid = cpu_to_le16(0xffff); 5663 mutex_lock(&bp->hwrm_cmd_lock); 5664 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5665 if (rc) { 5666 mutex_unlock(&bp->hwrm_cmd_lock); 5667 return rc; 5668 } 5669 5670 hw_resc->resv_tx_rings = le16_to_cpu(resp->alloc_tx_rings); 5671 if (BNXT_NEW_RM(bp)) { 5672 u16 cp, stats; 5673 5674 hw_resc->resv_rx_rings = le16_to_cpu(resp->alloc_rx_rings); 5675 hw_resc->resv_hw_ring_grps = 5676 le32_to_cpu(resp->alloc_hw_ring_grps); 5677 hw_resc->resv_vnics = le16_to_cpu(resp->alloc_vnics); 5678 cp = le16_to_cpu(resp->alloc_cmpl_rings); 5679 stats = le16_to_cpu(resp->alloc_stat_ctx); 5680 hw_resc->resv_irqs = cp; 5681 if (bp->flags & BNXT_FLAG_CHIP_P5) { 5682 int rx = hw_resc->resv_rx_rings; 5683 int tx = hw_resc->resv_tx_rings; 5684 5685 if (bp->flags & BNXT_FLAG_AGG_RINGS) 5686 rx >>= 1; 5687 if (cp < (rx + tx)) { 5688 bnxt_trim_rings(bp, &rx, &tx, cp, false); 5689 if (bp->flags & BNXT_FLAG_AGG_RINGS) 5690 rx <<= 1; 5691 hw_resc->resv_rx_rings = rx; 5692 hw_resc->resv_tx_rings = tx; 5693 } 5694 hw_resc->resv_irqs = le16_to_cpu(resp->alloc_msix); 5695 hw_resc->resv_hw_ring_grps = rx; 5696 } 5697 hw_resc->resv_cp_rings = cp; 5698 hw_resc->resv_stat_ctxs = stats; 5699 } 5700 mutex_unlock(&bp->hwrm_cmd_lock); 5701 return 0; 5702 } 5703 5704 /* Caller must hold bp->hwrm_cmd_lock */ 5705 int __bnxt_hwrm_get_tx_rings(struct bnxt *bp, u16 fid, int *tx_rings) 5706 { 5707 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr; 5708 struct hwrm_func_qcfg_input req = {0}; 5709 int rc; 5710 5711 if (bp->hwrm_spec_code < 0x10601) 5712 return 0; 5713 5714 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1); 5715 req.fid = cpu_to_le16(fid); 5716 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5717 if (!rc) 5718 *tx_rings = le16_to_cpu(resp->alloc_tx_rings); 5719 5720 return rc; 5721 } 5722 5723 static bool bnxt_rfs_supported(struct bnxt *bp); 5724 5725 static void 5726 __bnxt_hwrm_reserve_pf_rings(struct bnxt *bp, struct hwrm_func_cfg_input *req, 5727 int tx_rings, int rx_rings, int ring_grps, 5728 int cp_rings, int stats, int vnics) 5729 { 5730 u32 enables = 0; 5731 5732 bnxt_hwrm_cmd_hdr_init(bp, req, HWRM_FUNC_CFG, -1, -1); 5733 req->fid = cpu_to_le16(0xffff); 5734 enables |= tx_rings ? FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS : 0; 5735 req->num_tx_rings = cpu_to_le16(tx_rings); 5736 if (BNXT_NEW_RM(bp)) { 5737 enables |= rx_rings ? FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS : 0; 5738 enables |= stats ? FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0; 5739 if (bp->flags & BNXT_FLAG_CHIP_P5) { 5740 enables |= cp_rings ? FUNC_CFG_REQ_ENABLES_NUM_MSIX : 0; 5741 enables |= tx_rings + ring_grps ? 5742 FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0; 5743 enables |= rx_rings ? 5744 FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0; 5745 } else { 5746 enables |= cp_rings ? 5747 FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0; 5748 enables |= ring_grps ? 5749 FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS | 5750 FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0; 5751 } 5752 enables |= vnics ? FUNC_CFG_REQ_ENABLES_NUM_VNICS : 0; 5753 5754 req->num_rx_rings = cpu_to_le16(rx_rings); 5755 if (bp->flags & BNXT_FLAG_CHIP_P5) { 5756 req->num_cmpl_rings = cpu_to_le16(tx_rings + ring_grps); 5757 req->num_msix = cpu_to_le16(cp_rings); 5758 req->num_rsscos_ctxs = 5759 cpu_to_le16(DIV_ROUND_UP(ring_grps, 64)); 5760 } else { 5761 req->num_cmpl_rings = cpu_to_le16(cp_rings); 5762 req->num_hw_ring_grps = cpu_to_le16(ring_grps); 5763 req->num_rsscos_ctxs = cpu_to_le16(1); 5764 if (!(bp->flags & BNXT_FLAG_NEW_RSS_CAP) && 5765 bnxt_rfs_supported(bp)) 5766 req->num_rsscos_ctxs = 5767 cpu_to_le16(ring_grps + 1); 5768 } 5769 req->num_stat_ctxs = cpu_to_le16(stats); 5770 req->num_vnics = cpu_to_le16(vnics); 5771 } 5772 req->enables = cpu_to_le32(enables); 5773 } 5774 5775 static void 5776 __bnxt_hwrm_reserve_vf_rings(struct bnxt *bp, 5777 struct hwrm_func_vf_cfg_input *req, int tx_rings, 5778 int rx_rings, int ring_grps, int cp_rings, 5779 int stats, int vnics) 5780 { 5781 u32 enables = 0; 5782 5783 bnxt_hwrm_cmd_hdr_init(bp, req, HWRM_FUNC_VF_CFG, -1, -1); 5784 enables |= tx_rings ? FUNC_VF_CFG_REQ_ENABLES_NUM_TX_RINGS : 0; 5785 enables |= rx_rings ? FUNC_VF_CFG_REQ_ENABLES_NUM_RX_RINGS | 5786 FUNC_VF_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0; 5787 enables |= stats ? FUNC_VF_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0; 5788 if (bp->flags & BNXT_FLAG_CHIP_P5) { 5789 enables |= tx_rings + ring_grps ? 5790 FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0; 5791 } else { 5792 enables |= cp_rings ? 5793 FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0; 5794 enables |= ring_grps ? 5795 FUNC_VF_CFG_REQ_ENABLES_NUM_HW_RING_GRPS : 0; 5796 } 5797 enables |= vnics ? FUNC_VF_CFG_REQ_ENABLES_NUM_VNICS : 0; 5798 enables |= FUNC_VF_CFG_REQ_ENABLES_NUM_L2_CTXS; 5799 5800 req->num_l2_ctxs = cpu_to_le16(BNXT_VF_MAX_L2_CTX); 5801 req->num_tx_rings = cpu_to_le16(tx_rings); 5802 req->num_rx_rings = cpu_to_le16(rx_rings); 5803 if (bp->flags & BNXT_FLAG_CHIP_P5) { 5804 req->num_cmpl_rings = cpu_to_le16(tx_rings + ring_grps); 5805 req->num_rsscos_ctxs = cpu_to_le16(DIV_ROUND_UP(ring_grps, 64)); 5806 } else { 5807 req->num_cmpl_rings = cpu_to_le16(cp_rings); 5808 req->num_hw_ring_grps = cpu_to_le16(ring_grps); 5809 req->num_rsscos_ctxs = cpu_to_le16(BNXT_VF_MAX_RSS_CTX); 5810 } 5811 req->num_stat_ctxs = cpu_to_le16(stats); 5812 req->num_vnics = cpu_to_le16(vnics); 5813 5814 req->enables = cpu_to_le32(enables); 5815 } 5816 5817 static int 5818 bnxt_hwrm_reserve_pf_rings(struct bnxt *bp, int tx_rings, int rx_rings, 5819 int ring_grps, int cp_rings, int stats, int vnics) 5820 { 5821 struct hwrm_func_cfg_input req = {0}; 5822 int rc; 5823 5824 __bnxt_hwrm_reserve_pf_rings(bp, &req, tx_rings, rx_rings, ring_grps, 5825 cp_rings, stats, vnics); 5826 if (!req.enables) 5827 return 0; 5828 5829 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5830 if (rc) 5831 return rc; 5832 5833 if (bp->hwrm_spec_code < 0x10601) 5834 bp->hw_resc.resv_tx_rings = tx_rings; 5835 5836 return bnxt_hwrm_get_rings(bp); 5837 } 5838 5839 static int 5840 bnxt_hwrm_reserve_vf_rings(struct bnxt *bp, int tx_rings, int rx_rings, 5841 int ring_grps, int cp_rings, int stats, int vnics) 5842 { 5843 struct hwrm_func_vf_cfg_input req = {0}; 5844 int rc; 5845 5846 if (!BNXT_NEW_RM(bp)) { 5847 bp->hw_resc.resv_tx_rings = tx_rings; 5848 return 0; 5849 } 5850 5851 __bnxt_hwrm_reserve_vf_rings(bp, &req, tx_rings, rx_rings, ring_grps, 5852 cp_rings, stats, vnics); 5853 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5854 if (rc) 5855 return rc; 5856 5857 return bnxt_hwrm_get_rings(bp); 5858 } 5859 5860 static int bnxt_hwrm_reserve_rings(struct bnxt *bp, int tx, int rx, int grp, 5861 int cp, int stat, int vnic) 5862 { 5863 if (BNXT_PF(bp)) 5864 return bnxt_hwrm_reserve_pf_rings(bp, tx, rx, grp, cp, stat, 5865 vnic); 5866 else 5867 return bnxt_hwrm_reserve_vf_rings(bp, tx, rx, grp, cp, stat, 5868 vnic); 5869 } 5870 5871 int bnxt_nq_rings_in_use(struct bnxt *bp) 5872 { 5873 int cp = bp->cp_nr_rings; 5874 int ulp_msix, ulp_base; 5875 5876 ulp_msix = bnxt_get_ulp_msix_num(bp); 5877 if (ulp_msix) { 5878 ulp_base = bnxt_get_ulp_msix_base(bp); 5879 cp += ulp_msix; 5880 if ((ulp_base + ulp_msix) > cp) 5881 cp = ulp_base + ulp_msix; 5882 } 5883 return cp; 5884 } 5885 5886 static int bnxt_cp_rings_in_use(struct bnxt *bp) 5887 { 5888 int cp; 5889 5890 if (!(bp->flags & BNXT_FLAG_CHIP_P5)) 5891 return bnxt_nq_rings_in_use(bp); 5892 5893 cp = bp->tx_nr_rings + bp->rx_nr_rings; 5894 return cp; 5895 } 5896 5897 static int bnxt_get_func_stat_ctxs(struct bnxt *bp) 5898 { 5899 int ulp_stat = bnxt_get_ulp_stat_ctxs(bp); 5900 int cp = bp->cp_nr_rings; 5901 5902 if (!ulp_stat) 5903 return cp; 5904 5905 if (bnxt_nq_rings_in_use(bp) > cp + bnxt_get_ulp_msix_num(bp)) 5906 return bnxt_get_ulp_msix_base(bp) + ulp_stat; 5907 5908 return cp + ulp_stat; 5909 } 5910 5911 static bool bnxt_need_reserve_rings(struct bnxt *bp) 5912 { 5913 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 5914 int cp = bnxt_cp_rings_in_use(bp); 5915 int nq = bnxt_nq_rings_in_use(bp); 5916 int rx = bp->rx_nr_rings, stat; 5917 int vnic = 1, grp = rx; 5918 5919 if (bp->hwrm_spec_code < 0x10601) 5920 return false; 5921 5922 if (hw_resc->resv_tx_rings != bp->tx_nr_rings) 5923 return true; 5924 5925 if ((bp->flags & BNXT_FLAG_RFS) && !(bp->flags & BNXT_FLAG_CHIP_P5)) 5926 vnic = rx + 1; 5927 if (bp->flags & BNXT_FLAG_AGG_RINGS) 5928 rx <<= 1; 5929 stat = bnxt_get_func_stat_ctxs(bp); 5930 if (BNXT_NEW_RM(bp) && 5931 (hw_resc->resv_rx_rings != rx || hw_resc->resv_cp_rings != cp || 5932 hw_resc->resv_vnics != vnic || hw_resc->resv_stat_ctxs != stat || 5933 (hw_resc->resv_hw_ring_grps != grp && 5934 !(bp->flags & BNXT_FLAG_CHIP_P5)))) 5935 return true; 5936 if ((bp->flags & BNXT_FLAG_CHIP_P5) && BNXT_PF(bp) && 5937 hw_resc->resv_irqs != nq) 5938 return true; 5939 return false; 5940 } 5941 5942 static int __bnxt_reserve_rings(struct bnxt *bp) 5943 { 5944 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 5945 int cp = bnxt_nq_rings_in_use(bp); 5946 int tx = bp->tx_nr_rings; 5947 int rx = bp->rx_nr_rings; 5948 int grp, rx_rings, rc; 5949 int vnic = 1, stat; 5950 bool sh = false; 5951 5952 if (!bnxt_need_reserve_rings(bp)) 5953 return 0; 5954 5955 if (bp->flags & BNXT_FLAG_SHARED_RINGS) 5956 sh = true; 5957 if ((bp->flags & BNXT_FLAG_RFS) && !(bp->flags & BNXT_FLAG_CHIP_P5)) 5958 vnic = rx + 1; 5959 if (bp->flags & BNXT_FLAG_AGG_RINGS) 5960 rx <<= 1; 5961 grp = bp->rx_nr_rings; 5962 stat = bnxt_get_func_stat_ctxs(bp); 5963 5964 rc = bnxt_hwrm_reserve_rings(bp, tx, rx, grp, cp, stat, vnic); 5965 if (rc) 5966 return rc; 5967 5968 tx = hw_resc->resv_tx_rings; 5969 if (BNXT_NEW_RM(bp)) { 5970 rx = hw_resc->resv_rx_rings; 5971 cp = hw_resc->resv_irqs; 5972 grp = hw_resc->resv_hw_ring_grps; 5973 vnic = hw_resc->resv_vnics; 5974 stat = hw_resc->resv_stat_ctxs; 5975 } 5976 5977 rx_rings = rx; 5978 if (bp->flags & BNXT_FLAG_AGG_RINGS) { 5979 if (rx >= 2) { 5980 rx_rings = rx >> 1; 5981 } else { 5982 if (netif_running(bp->dev)) 5983 return -ENOMEM; 5984 5985 bp->flags &= ~BNXT_FLAG_AGG_RINGS; 5986 bp->flags |= BNXT_FLAG_NO_AGG_RINGS; 5987 bp->dev->hw_features &= ~NETIF_F_LRO; 5988 bp->dev->features &= ~NETIF_F_LRO; 5989 bnxt_set_ring_params(bp); 5990 } 5991 } 5992 rx_rings = min_t(int, rx_rings, grp); 5993 cp = min_t(int, cp, bp->cp_nr_rings); 5994 if (stat > bnxt_get_ulp_stat_ctxs(bp)) 5995 stat -= bnxt_get_ulp_stat_ctxs(bp); 5996 cp = min_t(int, cp, stat); 5997 rc = bnxt_trim_rings(bp, &rx_rings, &tx, cp, sh); 5998 if (bp->flags & BNXT_FLAG_AGG_RINGS) 5999 rx = rx_rings << 1; 6000 cp = sh ? max_t(int, tx, rx_rings) : tx + rx_rings; 6001 bp->tx_nr_rings = tx; 6002 bp->rx_nr_rings = rx_rings; 6003 bp->cp_nr_rings = cp; 6004 6005 if (!tx || !rx || !cp || !grp || !vnic || !stat) 6006 return -ENOMEM; 6007 6008 return rc; 6009 } 6010 6011 static int bnxt_hwrm_check_vf_rings(struct bnxt *bp, int tx_rings, int rx_rings, 6012 int ring_grps, int cp_rings, int stats, 6013 int vnics) 6014 { 6015 struct hwrm_func_vf_cfg_input req = {0}; 6016 u32 flags; 6017 6018 if (!BNXT_NEW_RM(bp)) 6019 return 0; 6020 6021 __bnxt_hwrm_reserve_vf_rings(bp, &req, tx_rings, rx_rings, ring_grps, 6022 cp_rings, stats, vnics); 6023 flags = FUNC_VF_CFG_REQ_FLAGS_TX_ASSETS_TEST | 6024 FUNC_VF_CFG_REQ_FLAGS_RX_ASSETS_TEST | 6025 FUNC_VF_CFG_REQ_FLAGS_CMPL_ASSETS_TEST | 6026 FUNC_VF_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST | 6027 FUNC_VF_CFG_REQ_FLAGS_VNIC_ASSETS_TEST | 6028 FUNC_VF_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST; 6029 if (!(bp->flags & BNXT_FLAG_CHIP_P5)) 6030 flags |= FUNC_VF_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST; 6031 6032 req.flags = cpu_to_le32(flags); 6033 return hwrm_send_message_silent(bp, &req, sizeof(req), 6034 HWRM_CMD_TIMEOUT); 6035 } 6036 6037 static int bnxt_hwrm_check_pf_rings(struct bnxt *bp, int tx_rings, int rx_rings, 6038 int ring_grps, int cp_rings, int stats, 6039 int vnics) 6040 { 6041 struct hwrm_func_cfg_input req = {0}; 6042 u32 flags; 6043 6044 __bnxt_hwrm_reserve_pf_rings(bp, &req, tx_rings, rx_rings, ring_grps, 6045 cp_rings, stats, vnics); 6046 flags = FUNC_CFG_REQ_FLAGS_TX_ASSETS_TEST; 6047 if (BNXT_NEW_RM(bp)) { 6048 flags |= FUNC_CFG_REQ_FLAGS_RX_ASSETS_TEST | 6049 FUNC_CFG_REQ_FLAGS_CMPL_ASSETS_TEST | 6050 FUNC_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST | 6051 FUNC_CFG_REQ_FLAGS_VNIC_ASSETS_TEST; 6052 if (bp->flags & BNXT_FLAG_CHIP_P5) 6053 flags |= FUNC_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST | 6054 FUNC_CFG_REQ_FLAGS_NQ_ASSETS_TEST; 6055 else 6056 flags |= FUNC_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST; 6057 } 6058 6059 req.flags = cpu_to_le32(flags); 6060 return hwrm_send_message_silent(bp, &req, sizeof(req), 6061 HWRM_CMD_TIMEOUT); 6062 } 6063 6064 static int bnxt_hwrm_check_rings(struct bnxt *bp, int tx_rings, int rx_rings, 6065 int ring_grps, int cp_rings, int stats, 6066 int vnics) 6067 { 6068 if (bp->hwrm_spec_code < 0x10801) 6069 return 0; 6070 6071 if (BNXT_PF(bp)) 6072 return bnxt_hwrm_check_pf_rings(bp, tx_rings, rx_rings, 6073 ring_grps, cp_rings, stats, 6074 vnics); 6075 6076 return bnxt_hwrm_check_vf_rings(bp, tx_rings, rx_rings, ring_grps, 6077 cp_rings, stats, vnics); 6078 } 6079 6080 static void bnxt_hwrm_coal_params_qcaps(struct bnxt *bp) 6081 { 6082 struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr; 6083 struct bnxt_coal_cap *coal_cap = &bp->coal_cap; 6084 struct hwrm_ring_aggint_qcaps_input req = {0}; 6085 int rc; 6086 6087 coal_cap->cmpl_params = BNXT_LEGACY_COAL_CMPL_PARAMS; 6088 coal_cap->num_cmpl_dma_aggr_max = 63; 6089 coal_cap->num_cmpl_dma_aggr_during_int_max = 63; 6090 coal_cap->cmpl_aggr_dma_tmr_max = 65535; 6091 coal_cap->cmpl_aggr_dma_tmr_during_int_max = 65535; 6092 coal_cap->int_lat_tmr_min_max = 65535; 6093 coal_cap->int_lat_tmr_max_max = 65535; 6094 coal_cap->num_cmpl_aggr_int_max = 65535; 6095 coal_cap->timer_units = 80; 6096 6097 if (bp->hwrm_spec_code < 0x10902) 6098 return; 6099 6100 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_AGGINT_QCAPS, -1, -1); 6101 mutex_lock(&bp->hwrm_cmd_lock); 6102 rc = _hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 6103 if (!rc) { 6104 coal_cap->cmpl_params = le32_to_cpu(resp->cmpl_params); 6105 coal_cap->nq_params = le32_to_cpu(resp->nq_params); 6106 coal_cap->num_cmpl_dma_aggr_max = 6107 le16_to_cpu(resp->num_cmpl_dma_aggr_max); 6108 coal_cap->num_cmpl_dma_aggr_during_int_max = 6109 le16_to_cpu(resp->num_cmpl_dma_aggr_during_int_max); 6110 coal_cap->cmpl_aggr_dma_tmr_max = 6111 le16_to_cpu(resp->cmpl_aggr_dma_tmr_max); 6112 coal_cap->cmpl_aggr_dma_tmr_during_int_max = 6113 le16_to_cpu(resp->cmpl_aggr_dma_tmr_during_int_max); 6114 coal_cap->int_lat_tmr_min_max = 6115 le16_to_cpu(resp->int_lat_tmr_min_max); 6116 coal_cap->int_lat_tmr_max_max = 6117 le16_to_cpu(resp->int_lat_tmr_max_max); 6118 coal_cap->num_cmpl_aggr_int_max = 6119 le16_to_cpu(resp->num_cmpl_aggr_int_max); 6120 coal_cap->timer_units = le16_to_cpu(resp->timer_units); 6121 } 6122 mutex_unlock(&bp->hwrm_cmd_lock); 6123 } 6124 6125 static u16 bnxt_usec_to_coal_tmr(struct bnxt *bp, u16 usec) 6126 { 6127 struct bnxt_coal_cap *coal_cap = &bp->coal_cap; 6128 6129 return usec * 1000 / coal_cap->timer_units; 6130 } 6131 6132 static void bnxt_hwrm_set_coal_params(struct bnxt *bp, 6133 struct bnxt_coal *hw_coal, 6134 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req) 6135 { 6136 struct bnxt_coal_cap *coal_cap = &bp->coal_cap; 6137 u32 cmpl_params = coal_cap->cmpl_params; 6138 u16 val, tmr, max, flags = 0; 6139 6140 max = hw_coal->bufs_per_record * 128; 6141 if (hw_coal->budget) 6142 max = hw_coal->bufs_per_record * hw_coal->budget; 6143 max = min_t(u16, max, coal_cap->num_cmpl_aggr_int_max); 6144 6145 val = clamp_t(u16, hw_coal->coal_bufs, 1, max); 6146 req->num_cmpl_aggr_int = cpu_to_le16(val); 6147 6148 val = min_t(u16, val, coal_cap->num_cmpl_dma_aggr_max); 6149 req->num_cmpl_dma_aggr = cpu_to_le16(val); 6150 6151 val = clamp_t(u16, hw_coal->coal_bufs_irq, 1, 6152 coal_cap->num_cmpl_dma_aggr_during_int_max); 6153 req->num_cmpl_dma_aggr_during_int = cpu_to_le16(val); 6154 6155 tmr = bnxt_usec_to_coal_tmr(bp, hw_coal->coal_ticks); 6156 tmr = clamp_t(u16, tmr, 1, coal_cap->int_lat_tmr_max_max); 6157 req->int_lat_tmr_max = cpu_to_le16(tmr); 6158 6159 /* min timer set to 1/2 of interrupt timer */ 6160 if (cmpl_params & RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN) { 6161 val = tmr / 2; 6162 val = clamp_t(u16, val, 1, coal_cap->int_lat_tmr_min_max); 6163 req->int_lat_tmr_min = cpu_to_le16(val); 6164 req->enables |= cpu_to_le16(BNXT_COAL_CMPL_MIN_TMR_ENABLE); 6165 } 6166 6167 /* buf timer set to 1/4 of interrupt timer */ 6168 val = clamp_t(u16, tmr / 4, 1, coal_cap->cmpl_aggr_dma_tmr_max); 6169 req->cmpl_aggr_dma_tmr = cpu_to_le16(val); 6170 6171 if (cmpl_params & 6172 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT) { 6173 tmr = bnxt_usec_to_coal_tmr(bp, hw_coal->coal_ticks_irq); 6174 val = clamp_t(u16, tmr, 1, 6175 coal_cap->cmpl_aggr_dma_tmr_during_int_max); 6176 req->cmpl_aggr_dma_tmr_during_int = cpu_to_le16(val); 6177 req->enables |= 6178 cpu_to_le16(BNXT_COAL_CMPL_AGGR_TMR_DURING_INT_ENABLE); 6179 } 6180 6181 if (cmpl_params & RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET) 6182 flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET; 6183 if ((cmpl_params & RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE) && 6184 hw_coal->idle_thresh && hw_coal->coal_ticks < hw_coal->idle_thresh) 6185 flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE; 6186 req->flags = cpu_to_le16(flags); 6187 req->enables |= cpu_to_le16(BNXT_COAL_CMPL_ENABLES); 6188 } 6189 6190 /* Caller holds bp->hwrm_cmd_lock */ 6191 static int __bnxt_hwrm_set_coal_nq(struct bnxt *bp, struct bnxt_napi *bnapi, 6192 struct bnxt_coal *hw_coal) 6193 { 6194 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0}; 6195 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 6196 struct bnxt_coal_cap *coal_cap = &bp->coal_cap; 6197 u32 nq_params = coal_cap->nq_params; 6198 u16 tmr; 6199 6200 if (!(nq_params & RING_AGGINT_QCAPS_RESP_NQ_PARAMS_INT_LAT_TMR_MIN)) 6201 return 0; 6202 6203 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, 6204 -1, -1); 6205 req.ring_id = cpu_to_le16(cpr->cp_ring_struct.fw_ring_id); 6206 req.flags = 6207 cpu_to_le16(RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_IS_NQ); 6208 6209 tmr = bnxt_usec_to_coal_tmr(bp, hw_coal->coal_ticks) / 2; 6210 tmr = clamp_t(u16, tmr, 1, coal_cap->int_lat_tmr_min_max); 6211 req.int_lat_tmr_min = cpu_to_le16(tmr); 6212 req.enables |= cpu_to_le16(BNXT_COAL_CMPL_MIN_TMR_ENABLE); 6213 return _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 6214 } 6215 6216 int bnxt_hwrm_set_ring_coal(struct bnxt *bp, struct bnxt_napi *bnapi) 6217 { 6218 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx = {0}; 6219 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 6220 struct bnxt_coal coal; 6221 6222 /* Tick values in micro seconds. 6223 * 1 coal_buf x bufs_per_record = 1 completion record. 6224 */ 6225 memcpy(&coal, &bp->rx_coal, sizeof(struct bnxt_coal)); 6226 6227 coal.coal_ticks = cpr->rx_ring_coal.coal_ticks; 6228 coal.coal_bufs = cpr->rx_ring_coal.coal_bufs; 6229 6230 if (!bnapi->rx_ring) 6231 return -ENODEV; 6232 6233 bnxt_hwrm_cmd_hdr_init(bp, &req_rx, 6234 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1); 6235 6236 bnxt_hwrm_set_coal_params(bp, &coal, &req_rx); 6237 6238 req_rx.ring_id = cpu_to_le16(bnxt_cp_ring_for_rx(bp, bnapi->rx_ring)); 6239 6240 return hwrm_send_message(bp, &req_rx, sizeof(req_rx), 6241 HWRM_CMD_TIMEOUT); 6242 } 6243 6244 int bnxt_hwrm_set_coal(struct bnxt *bp) 6245 { 6246 int i, rc = 0; 6247 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx = {0}, 6248 req_tx = {0}, *req; 6249 6250 bnxt_hwrm_cmd_hdr_init(bp, &req_rx, 6251 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1); 6252 bnxt_hwrm_cmd_hdr_init(bp, &req_tx, 6253 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1); 6254 6255 bnxt_hwrm_set_coal_params(bp, &bp->rx_coal, &req_rx); 6256 bnxt_hwrm_set_coal_params(bp, &bp->tx_coal, &req_tx); 6257 6258 mutex_lock(&bp->hwrm_cmd_lock); 6259 for (i = 0; i < bp->cp_nr_rings; i++) { 6260 struct bnxt_napi *bnapi = bp->bnapi[i]; 6261 struct bnxt_coal *hw_coal; 6262 u16 ring_id; 6263 6264 req = &req_rx; 6265 if (!bnapi->rx_ring) { 6266 ring_id = bnxt_cp_ring_for_tx(bp, bnapi->tx_ring); 6267 req = &req_tx; 6268 } else { 6269 ring_id = bnxt_cp_ring_for_rx(bp, bnapi->rx_ring); 6270 } 6271 req->ring_id = cpu_to_le16(ring_id); 6272 6273 rc = _hwrm_send_message(bp, req, sizeof(*req), 6274 HWRM_CMD_TIMEOUT); 6275 if (rc) 6276 break; 6277 6278 if (!(bp->flags & BNXT_FLAG_CHIP_P5)) 6279 continue; 6280 6281 if (bnapi->rx_ring && bnapi->tx_ring) { 6282 req = &req_tx; 6283 ring_id = bnxt_cp_ring_for_tx(bp, bnapi->tx_ring); 6284 req->ring_id = cpu_to_le16(ring_id); 6285 rc = _hwrm_send_message(bp, req, sizeof(*req), 6286 HWRM_CMD_TIMEOUT); 6287 if (rc) 6288 break; 6289 } 6290 if (bnapi->rx_ring) 6291 hw_coal = &bp->rx_coal; 6292 else 6293 hw_coal = &bp->tx_coal; 6294 __bnxt_hwrm_set_coal_nq(bp, bnapi, hw_coal); 6295 } 6296 mutex_unlock(&bp->hwrm_cmd_lock); 6297 return rc; 6298 } 6299 6300 static void bnxt_hwrm_stat_ctx_free(struct bnxt *bp) 6301 { 6302 struct hwrm_stat_ctx_free_input req = {0}; 6303 int i; 6304 6305 if (!bp->bnapi) 6306 return; 6307 6308 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 6309 return; 6310 6311 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_FREE, -1, -1); 6312 6313 mutex_lock(&bp->hwrm_cmd_lock); 6314 for (i = 0; i < bp->cp_nr_rings; i++) { 6315 struct bnxt_napi *bnapi = bp->bnapi[i]; 6316 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 6317 6318 if (cpr->hw_stats_ctx_id != INVALID_STATS_CTX_ID) { 6319 req.stat_ctx_id = cpu_to_le32(cpr->hw_stats_ctx_id); 6320 6321 _hwrm_send_message(bp, &req, sizeof(req), 6322 HWRM_CMD_TIMEOUT); 6323 6324 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID; 6325 } 6326 } 6327 mutex_unlock(&bp->hwrm_cmd_lock); 6328 } 6329 6330 static int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp) 6331 { 6332 int rc = 0, i; 6333 struct hwrm_stat_ctx_alloc_input req = {0}; 6334 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr; 6335 6336 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 6337 return 0; 6338 6339 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_ALLOC, -1, -1); 6340 6341 req.stats_dma_length = cpu_to_le16(bp->hw_ring_stats_size); 6342 req.update_period_ms = cpu_to_le32(bp->stats_coal_ticks / 1000); 6343 6344 mutex_lock(&bp->hwrm_cmd_lock); 6345 for (i = 0; i < bp->cp_nr_rings; i++) { 6346 struct bnxt_napi *bnapi = bp->bnapi[i]; 6347 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 6348 6349 req.stats_dma_addr = cpu_to_le64(cpr->hw_stats_map); 6350 6351 rc = _hwrm_send_message(bp, &req, sizeof(req), 6352 HWRM_CMD_TIMEOUT); 6353 if (rc) 6354 break; 6355 6356 cpr->hw_stats_ctx_id = le32_to_cpu(resp->stat_ctx_id); 6357 6358 bp->grp_info[i].fw_stats_ctx = cpr->hw_stats_ctx_id; 6359 } 6360 mutex_unlock(&bp->hwrm_cmd_lock); 6361 return rc; 6362 } 6363 6364 static int bnxt_hwrm_func_qcfg(struct bnxt *bp) 6365 { 6366 struct hwrm_func_qcfg_input req = {0}; 6367 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr; 6368 u16 flags; 6369 int rc; 6370 6371 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1); 6372 req.fid = cpu_to_le16(0xffff); 6373 mutex_lock(&bp->hwrm_cmd_lock); 6374 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 6375 if (rc) 6376 goto func_qcfg_exit; 6377 6378 #ifdef CONFIG_BNXT_SRIOV 6379 if (BNXT_VF(bp)) { 6380 struct bnxt_vf_info *vf = &bp->vf; 6381 6382 vf->vlan = le16_to_cpu(resp->vlan) & VLAN_VID_MASK; 6383 } else { 6384 bp->pf.registered_vfs = le16_to_cpu(resp->registered_vfs); 6385 } 6386 #endif 6387 flags = le16_to_cpu(resp->flags); 6388 if (flags & (FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED | 6389 FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED)) { 6390 bp->fw_cap |= BNXT_FW_CAP_LLDP_AGENT; 6391 if (flags & FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED) 6392 bp->fw_cap |= BNXT_FW_CAP_DCBX_AGENT; 6393 } 6394 if (BNXT_PF(bp) && (flags & FUNC_QCFG_RESP_FLAGS_MULTI_HOST)) 6395 bp->flags |= BNXT_FLAG_MULTI_HOST; 6396 6397 switch (resp->port_partition_type) { 6398 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0: 6399 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5: 6400 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0: 6401 bp->port_partition_type = resp->port_partition_type; 6402 break; 6403 } 6404 if (bp->hwrm_spec_code < 0x10707 || 6405 resp->evb_mode == FUNC_QCFG_RESP_EVB_MODE_VEB) 6406 bp->br_mode = BRIDGE_MODE_VEB; 6407 else if (resp->evb_mode == FUNC_QCFG_RESP_EVB_MODE_VEPA) 6408 bp->br_mode = BRIDGE_MODE_VEPA; 6409 else 6410 bp->br_mode = BRIDGE_MODE_UNDEF; 6411 6412 bp->max_mtu = le16_to_cpu(resp->max_mtu_configured); 6413 if (!bp->max_mtu) 6414 bp->max_mtu = BNXT_MAX_MTU; 6415 6416 func_qcfg_exit: 6417 mutex_unlock(&bp->hwrm_cmd_lock); 6418 return rc; 6419 } 6420 6421 static int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp) 6422 { 6423 struct hwrm_func_backing_store_qcaps_input req = {0}; 6424 struct hwrm_func_backing_store_qcaps_output *resp = 6425 bp->hwrm_cmd_resp_addr; 6426 int rc; 6427 6428 if (bp->hwrm_spec_code < 0x10902 || BNXT_VF(bp) || bp->ctx) 6429 return 0; 6430 6431 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_BACKING_STORE_QCAPS, -1, -1); 6432 mutex_lock(&bp->hwrm_cmd_lock); 6433 rc = _hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 6434 if (!rc) { 6435 struct bnxt_ctx_pg_info *ctx_pg; 6436 struct bnxt_ctx_mem_info *ctx; 6437 int i; 6438 6439 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); 6440 if (!ctx) { 6441 rc = -ENOMEM; 6442 goto ctx_err; 6443 } 6444 ctx_pg = kzalloc(sizeof(*ctx_pg) * (bp->max_q + 1), GFP_KERNEL); 6445 if (!ctx_pg) { 6446 kfree(ctx); 6447 rc = -ENOMEM; 6448 goto ctx_err; 6449 } 6450 for (i = 0; i < bp->max_q + 1; i++, ctx_pg++) 6451 ctx->tqm_mem[i] = ctx_pg; 6452 6453 bp->ctx = ctx; 6454 ctx->qp_max_entries = le32_to_cpu(resp->qp_max_entries); 6455 ctx->qp_min_qp1_entries = le16_to_cpu(resp->qp_min_qp1_entries); 6456 ctx->qp_max_l2_entries = le16_to_cpu(resp->qp_max_l2_entries); 6457 ctx->qp_entry_size = le16_to_cpu(resp->qp_entry_size); 6458 ctx->srq_max_l2_entries = le16_to_cpu(resp->srq_max_l2_entries); 6459 ctx->srq_max_entries = le32_to_cpu(resp->srq_max_entries); 6460 ctx->srq_entry_size = le16_to_cpu(resp->srq_entry_size); 6461 ctx->cq_max_l2_entries = le16_to_cpu(resp->cq_max_l2_entries); 6462 ctx->cq_max_entries = le32_to_cpu(resp->cq_max_entries); 6463 ctx->cq_entry_size = le16_to_cpu(resp->cq_entry_size); 6464 ctx->vnic_max_vnic_entries = 6465 le16_to_cpu(resp->vnic_max_vnic_entries); 6466 ctx->vnic_max_ring_table_entries = 6467 le16_to_cpu(resp->vnic_max_ring_table_entries); 6468 ctx->vnic_entry_size = le16_to_cpu(resp->vnic_entry_size); 6469 ctx->stat_max_entries = le32_to_cpu(resp->stat_max_entries); 6470 ctx->stat_entry_size = le16_to_cpu(resp->stat_entry_size); 6471 ctx->tqm_entry_size = le16_to_cpu(resp->tqm_entry_size); 6472 ctx->tqm_min_entries_per_ring = 6473 le32_to_cpu(resp->tqm_min_entries_per_ring); 6474 ctx->tqm_max_entries_per_ring = 6475 le32_to_cpu(resp->tqm_max_entries_per_ring); 6476 ctx->tqm_entries_multiple = resp->tqm_entries_multiple; 6477 if (!ctx->tqm_entries_multiple) 6478 ctx->tqm_entries_multiple = 1; 6479 ctx->mrav_max_entries = le32_to_cpu(resp->mrav_max_entries); 6480 ctx->mrav_entry_size = le16_to_cpu(resp->mrav_entry_size); 6481 ctx->mrav_num_entries_units = 6482 le16_to_cpu(resp->mrav_num_entries_units); 6483 ctx->tim_entry_size = le16_to_cpu(resp->tim_entry_size); 6484 ctx->tim_max_entries = le32_to_cpu(resp->tim_max_entries); 6485 ctx->ctx_kind_initializer = resp->ctx_kind_initializer; 6486 } else { 6487 rc = 0; 6488 } 6489 ctx_err: 6490 mutex_unlock(&bp->hwrm_cmd_lock); 6491 return rc; 6492 } 6493 6494 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem, u8 *pg_attr, 6495 __le64 *pg_dir) 6496 { 6497 u8 pg_size = 0; 6498 6499 if (BNXT_PAGE_SHIFT == 13) 6500 pg_size = 1 << 4; 6501 else if (BNXT_PAGE_SIZE == 16) 6502 pg_size = 2 << 4; 6503 6504 *pg_attr = pg_size; 6505 if (rmem->depth >= 1) { 6506 if (rmem->depth == 2) 6507 *pg_attr |= 2; 6508 else 6509 *pg_attr |= 1; 6510 *pg_dir = cpu_to_le64(rmem->pg_tbl_map); 6511 } else { 6512 *pg_dir = cpu_to_le64(rmem->dma_arr[0]); 6513 } 6514 } 6515 6516 #define FUNC_BACKING_STORE_CFG_REQ_DFLT_ENABLES \ 6517 (FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP | \ 6518 FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ | \ 6519 FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ | \ 6520 FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC | \ 6521 FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT) 6522 6523 static int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, u32 enables) 6524 { 6525 struct hwrm_func_backing_store_cfg_input req = {0}; 6526 struct bnxt_ctx_mem_info *ctx = bp->ctx; 6527 struct bnxt_ctx_pg_info *ctx_pg; 6528 __le32 *num_entries; 6529 __le64 *pg_dir; 6530 u32 flags = 0; 6531 u8 *pg_attr; 6532 u32 ena; 6533 int i; 6534 6535 if (!ctx) 6536 return 0; 6537 6538 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_BACKING_STORE_CFG, -1, -1); 6539 req.enables = cpu_to_le32(enables); 6540 6541 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP) { 6542 ctx_pg = &ctx->qp_mem; 6543 req.qp_num_entries = cpu_to_le32(ctx_pg->entries); 6544 req.qp_num_qp1_entries = cpu_to_le16(ctx->qp_min_qp1_entries); 6545 req.qp_num_l2_entries = cpu_to_le16(ctx->qp_max_l2_entries); 6546 req.qp_entry_size = cpu_to_le16(ctx->qp_entry_size); 6547 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, 6548 &req.qpc_pg_size_qpc_lvl, 6549 &req.qpc_page_dir); 6550 } 6551 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ) { 6552 ctx_pg = &ctx->srq_mem; 6553 req.srq_num_entries = cpu_to_le32(ctx_pg->entries); 6554 req.srq_num_l2_entries = cpu_to_le16(ctx->srq_max_l2_entries); 6555 req.srq_entry_size = cpu_to_le16(ctx->srq_entry_size); 6556 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, 6557 &req.srq_pg_size_srq_lvl, 6558 &req.srq_page_dir); 6559 } 6560 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ) { 6561 ctx_pg = &ctx->cq_mem; 6562 req.cq_num_entries = cpu_to_le32(ctx_pg->entries); 6563 req.cq_num_l2_entries = cpu_to_le16(ctx->cq_max_l2_entries); 6564 req.cq_entry_size = cpu_to_le16(ctx->cq_entry_size); 6565 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, &req.cq_pg_size_cq_lvl, 6566 &req.cq_page_dir); 6567 } 6568 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC) { 6569 ctx_pg = &ctx->vnic_mem; 6570 req.vnic_num_vnic_entries = 6571 cpu_to_le16(ctx->vnic_max_vnic_entries); 6572 req.vnic_num_ring_table_entries = 6573 cpu_to_le16(ctx->vnic_max_ring_table_entries); 6574 req.vnic_entry_size = cpu_to_le16(ctx->vnic_entry_size); 6575 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, 6576 &req.vnic_pg_size_vnic_lvl, 6577 &req.vnic_page_dir); 6578 } 6579 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT) { 6580 ctx_pg = &ctx->stat_mem; 6581 req.stat_num_entries = cpu_to_le32(ctx->stat_max_entries); 6582 req.stat_entry_size = cpu_to_le16(ctx->stat_entry_size); 6583 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, 6584 &req.stat_pg_size_stat_lvl, 6585 &req.stat_page_dir); 6586 } 6587 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV) { 6588 ctx_pg = &ctx->mrav_mem; 6589 req.mrav_num_entries = cpu_to_le32(ctx_pg->entries); 6590 if (ctx->mrav_num_entries_units) 6591 flags |= 6592 FUNC_BACKING_STORE_CFG_REQ_FLAGS_MRAV_RESERVATION_SPLIT; 6593 req.mrav_entry_size = cpu_to_le16(ctx->mrav_entry_size); 6594 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, 6595 &req.mrav_pg_size_mrav_lvl, 6596 &req.mrav_page_dir); 6597 } 6598 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM) { 6599 ctx_pg = &ctx->tim_mem; 6600 req.tim_num_entries = cpu_to_le32(ctx_pg->entries); 6601 req.tim_entry_size = cpu_to_le16(ctx->tim_entry_size); 6602 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, 6603 &req.tim_pg_size_tim_lvl, 6604 &req.tim_page_dir); 6605 } 6606 for (i = 0, num_entries = &req.tqm_sp_num_entries, 6607 pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl, 6608 pg_dir = &req.tqm_sp_page_dir, 6609 ena = FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP; 6610 i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) { 6611 if (!(enables & ena)) 6612 continue; 6613 6614 req.tqm_entry_size = cpu_to_le16(ctx->tqm_entry_size); 6615 ctx_pg = ctx->tqm_mem[i]; 6616 *num_entries = cpu_to_le32(ctx_pg->entries); 6617 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir); 6618 } 6619 req.flags = cpu_to_le32(flags); 6620 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 6621 } 6622 6623 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp, 6624 struct bnxt_ctx_pg_info *ctx_pg) 6625 { 6626 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem; 6627 6628 rmem->page_size = BNXT_PAGE_SIZE; 6629 rmem->pg_arr = ctx_pg->ctx_pg_arr; 6630 rmem->dma_arr = ctx_pg->ctx_dma_arr; 6631 rmem->flags = BNXT_RMEM_VALID_PTE_FLAG; 6632 if (rmem->depth >= 1) 6633 rmem->flags |= BNXT_RMEM_USE_FULL_PAGE_FLAG; 6634 return bnxt_alloc_ring(bp, rmem); 6635 } 6636 6637 static int bnxt_alloc_ctx_pg_tbls(struct bnxt *bp, 6638 struct bnxt_ctx_pg_info *ctx_pg, u32 mem_size, 6639 u8 depth, bool use_init_val) 6640 { 6641 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem; 6642 int rc; 6643 6644 if (!mem_size) 6645 return 0; 6646 6647 ctx_pg->nr_pages = DIV_ROUND_UP(mem_size, BNXT_PAGE_SIZE); 6648 if (ctx_pg->nr_pages > MAX_CTX_TOTAL_PAGES) { 6649 ctx_pg->nr_pages = 0; 6650 return -EINVAL; 6651 } 6652 if (ctx_pg->nr_pages > MAX_CTX_PAGES || depth > 1) { 6653 int nr_tbls, i; 6654 6655 rmem->depth = 2; 6656 ctx_pg->ctx_pg_tbl = kcalloc(MAX_CTX_PAGES, sizeof(ctx_pg), 6657 GFP_KERNEL); 6658 if (!ctx_pg->ctx_pg_tbl) 6659 return -ENOMEM; 6660 nr_tbls = DIV_ROUND_UP(ctx_pg->nr_pages, MAX_CTX_PAGES); 6661 rmem->nr_pages = nr_tbls; 6662 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg); 6663 if (rc) 6664 return rc; 6665 for (i = 0; i < nr_tbls; i++) { 6666 struct bnxt_ctx_pg_info *pg_tbl; 6667 6668 pg_tbl = kzalloc(sizeof(*pg_tbl), GFP_KERNEL); 6669 if (!pg_tbl) 6670 return -ENOMEM; 6671 ctx_pg->ctx_pg_tbl[i] = pg_tbl; 6672 rmem = &pg_tbl->ring_mem; 6673 rmem->pg_tbl = ctx_pg->ctx_pg_arr[i]; 6674 rmem->pg_tbl_map = ctx_pg->ctx_dma_arr[i]; 6675 rmem->depth = 1; 6676 rmem->nr_pages = MAX_CTX_PAGES; 6677 if (use_init_val) 6678 rmem->init_val = bp->ctx->ctx_kind_initializer; 6679 if (i == (nr_tbls - 1)) { 6680 int rem = ctx_pg->nr_pages % MAX_CTX_PAGES; 6681 6682 if (rem) 6683 rmem->nr_pages = rem; 6684 } 6685 rc = bnxt_alloc_ctx_mem_blk(bp, pg_tbl); 6686 if (rc) 6687 break; 6688 } 6689 } else { 6690 rmem->nr_pages = DIV_ROUND_UP(mem_size, BNXT_PAGE_SIZE); 6691 if (rmem->nr_pages > 1 || depth) 6692 rmem->depth = 1; 6693 if (use_init_val) 6694 rmem->init_val = bp->ctx->ctx_kind_initializer; 6695 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg); 6696 } 6697 return rc; 6698 } 6699 6700 static void bnxt_free_ctx_pg_tbls(struct bnxt *bp, 6701 struct bnxt_ctx_pg_info *ctx_pg) 6702 { 6703 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem; 6704 6705 if (rmem->depth > 1 || ctx_pg->nr_pages > MAX_CTX_PAGES || 6706 ctx_pg->ctx_pg_tbl) { 6707 int i, nr_tbls = rmem->nr_pages; 6708 6709 for (i = 0; i < nr_tbls; i++) { 6710 struct bnxt_ctx_pg_info *pg_tbl; 6711 struct bnxt_ring_mem_info *rmem2; 6712 6713 pg_tbl = ctx_pg->ctx_pg_tbl[i]; 6714 if (!pg_tbl) 6715 continue; 6716 rmem2 = &pg_tbl->ring_mem; 6717 bnxt_free_ring(bp, rmem2); 6718 ctx_pg->ctx_pg_arr[i] = NULL; 6719 kfree(pg_tbl); 6720 ctx_pg->ctx_pg_tbl[i] = NULL; 6721 } 6722 kfree(ctx_pg->ctx_pg_tbl); 6723 ctx_pg->ctx_pg_tbl = NULL; 6724 } 6725 bnxt_free_ring(bp, rmem); 6726 ctx_pg->nr_pages = 0; 6727 } 6728 6729 static void bnxt_free_ctx_mem(struct bnxt *bp) 6730 { 6731 struct bnxt_ctx_mem_info *ctx = bp->ctx; 6732 int i; 6733 6734 if (!ctx) 6735 return; 6736 6737 if (ctx->tqm_mem[0]) { 6738 for (i = 0; i < bp->max_q + 1; i++) 6739 bnxt_free_ctx_pg_tbls(bp, ctx->tqm_mem[i]); 6740 kfree(ctx->tqm_mem[0]); 6741 ctx->tqm_mem[0] = NULL; 6742 } 6743 6744 bnxt_free_ctx_pg_tbls(bp, &ctx->tim_mem); 6745 bnxt_free_ctx_pg_tbls(bp, &ctx->mrav_mem); 6746 bnxt_free_ctx_pg_tbls(bp, &ctx->stat_mem); 6747 bnxt_free_ctx_pg_tbls(bp, &ctx->vnic_mem); 6748 bnxt_free_ctx_pg_tbls(bp, &ctx->cq_mem); 6749 bnxt_free_ctx_pg_tbls(bp, &ctx->srq_mem); 6750 bnxt_free_ctx_pg_tbls(bp, &ctx->qp_mem); 6751 ctx->flags &= ~BNXT_CTX_FLAG_INITED; 6752 } 6753 6754 static int bnxt_alloc_ctx_mem(struct bnxt *bp) 6755 { 6756 struct bnxt_ctx_pg_info *ctx_pg; 6757 struct bnxt_ctx_mem_info *ctx; 6758 u32 mem_size, ena, entries; 6759 u32 num_mr, num_ah; 6760 u32 extra_srqs = 0; 6761 u32 extra_qps = 0; 6762 u8 pg_lvl = 1; 6763 int i, rc; 6764 6765 rc = bnxt_hwrm_func_backing_store_qcaps(bp); 6766 if (rc) { 6767 netdev_err(bp->dev, "Failed querying context mem capability, rc = %d.\n", 6768 rc); 6769 return rc; 6770 } 6771 ctx = bp->ctx; 6772 if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED)) 6773 return 0; 6774 6775 if ((bp->flags & BNXT_FLAG_ROCE_CAP) && !is_kdump_kernel()) { 6776 pg_lvl = 2; 6777 extra_qps = 65536; 6778 extra_srqs = 8192; 6779 } 6780 6781 ctx_pg = &ctx->qp_mem; 6782 ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries + 6783 extra_qps; 6784 mem_size = ctx->qp_entry_size * ctx_pg->entries; 6785 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, pg_lvl, true); 6786 if (rc) 6787 return rc; 6788 6789 ctx_pg = &ctx->srq_mem; 6790 ctx_pg->entries = ctx->srq_max_l2_entries + extra_srqs; 6791 mem_size = ctx->srq_entry_size * ctx_pg->entries; 6792 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, pg_lvl, true); 6793 if (rc) 6794 return rc; 6795 6796 ctx_pg = &ctx->cq_mem; 6797 ctx_pg->entries = ctx->cq_max_l2_entries + extra_qps * 2; 6798 mem_size = ctx->cq_entry_size * ctx_pg->entries; 6799 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, pg_lvl, true); 6800 if (rc) 6801 return rc; 6802 6803 ctx_pg = &ctx->vnic_mem; 6804 ctx_pg->entries = ctx->vnic_max_vnic_entries + 6805 ctx->vnic_max_ring_table_entries; 6806 mem_size = ctx->vnic_entry_size * ctx_pg->entries; 6807 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1, true); 6808 if (rc) 6809 return rc; 6810 6811 ctx_pg = &ctx->stat_mem; 6812 ctx_pg->entries = ctx->stat_max_entries; 6813 mem_size = ctx->stat_entry_size * ctx_pg->entries; 6814 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1, true); 6815 if (rc) 6816 return rc; 6817 6818 ena = 0; 6819 if (!(bp->flags & BNXT_FLAG_ROCE_CAP)) 6820 goto skip_rdma; 6821 6822 ctx_pg = &ctx->mrav_mem; 6823 /* 128K extra is needed to accommodate static AH context 6824 * allocation by f/w. 6825 */ 6826 num_mr = 1024 * 256; 6827 num_ah = 1024 * 128; 6828 ctx_pg->entries = num_mr + num_ah; 6829 mem_size = ctx->mrav_entry_size * ctx_pg->entries; 6830 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 2, true); 6831 if (rc) 6832 return rc; 6833 ena = FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV; 6834 if (ctx->mrav_num_entries_units) 6835 ctx_pg->entries = 6836 ((num_mr / ctx->mrav_num_entries_units) << 16) | 6837 (num_ah / ctx->mrav_num_entries_units); 6838 6839 ctx_pg = &ctx->tim_mem; 6840 ctx_pg->entries = ctx->qp_mem.entries; 6841 mem_size = ctx->tim_entry_size * ctx_pg->entries; 6842 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1, false); 6843 if (rc) 6844 return rc; 6845 ena |= FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM; 6846 6847 skip_rdma: 6848 entries = ctx->qp_max_l2_entries + extra_qps; 6849 entries = roundup(entries, ctx->tqm_entries_multiple); 6850 entries = clamp_t(u32, entries, ctx->tqm_min_entries_per_ring, 6851 ctx->tqm_max_entries_per_ring); 6852 for (i = 0; i < bp->max_q + 1; i++) { 6853 ctx_pg = ctx->tqm_mem[i]; 6854 ctx_pg->entries = entries; 6855 mem_size = ctx->tqm_entry_size * entries; 6856 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1, false); 6857 if (rc) 6858 return rc; 6859 ena |= FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP << i; 6860 } 6861 ena |= FUNC_BACKING_STORE_CFG_REQ_DFLT_ENABLES; 6862 rc = bnxt_hwrm_func_backing_store_cfg(bp, ena); 6863 if (rc) 6864 netdev_err(bp->dev, "Failed configuring context mem, rc = %d.\n", 6865 rc); 6866 else 6867 ctx->flags |= BNXT_CTX_FLAG_INITED; 6868 6869 return 0; 6870 } 6871 6872 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp, bool all) 6873 { 6874 struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr; 6875 struct hwrm_func_resource_qcaps_input req = {0}; 6876 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 6877 int rc; 6878 6879 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESOURCE_QCAPS, -1, -1); 6880 req.fid = cpu_to_le16(0xffff); 6881 6882 mutex_lock(&bp->hwrm_cmd_lock); 6883 rc = _hwrm_send_message_silent(bp, &req, sizeof(req), 6884 HWRM_CMD_TIMEOUT); 6885 if (rc) 6886 goto hwrm_func_resc_qcaps_exit; 6887 6888 hw_resc->max_tx_sch_inputs = le16_to_cpu(resp->max_tx_scheduler_inputs); 6889 if (!all) 6890 goto hwrm_func_resc_qcaps_exit; 6891 6892 hw_resc->min_rsscos_ctxs = le16_to_cpu(resp->min_rsscos_ctx); 6893 hw_resc->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx); 6894 hw_resc->min_cp_rings = le16_to_cpu(resp->min_cmpl_rings); 6895 hw_resc->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings); 6896 hw_resc->min_tx_rings = le16_to_cpu(resp->min_tx_rings); 6897 hw_resc->max_tx_rings = le16_to_cpu(resp->max_tx_rings); 6898 hw_resc->min_rx_rings = le16_to_cpu(resp->min_rx_rings); 6899 hw_resc->max_rx_rings = le16_to_cpu(resp->max_rx_rings); 6900 hw_resc->min_hw_ring_grps = le16_to_cpu(resp->min_hw_ring_grps); 6901 hw_resc->max_hw_ring_grps = le16_to_cpu(resp->max_hw_ring_grps); 6902 hw_resc->min_l2_ctxs = le16_to_cpu(resp->min_l2_ctxs); 6903 hw_resc->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs); 6904 hw_resc->min_vnics = le16_to_cpu(resp->min_vnics); 6905 hw_resc->max_vnics = le16_to_cpu(resp->max_vnics); 6906 hw_resc->min_stat_ctxs = le16_to_cpu(resp->min_stat_ctx); 6907 hw_resc->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx); 6908 6909 if (bp->flags & BNXT_FLAG_CHIP_P5) { 6910 u16 max_msix = le16_to_cpu(resp->max_msix); 6911 6912 hw_resc->max_nqs = max_msix; 6913 hw_resc->max_hw_ring_grps = hw_resc->max_rx_rings; 6914 } 6915 6916 if (BNXT_PF(bp)) { 6917 struct bnxt_pf_info *pf = &bp->pf; 6918 6919 pf->vf_resv_strategy = 6920 le16_to_cpu(resp->vf_reservation_strategy); 6921 if (pf->vf_resv_strategy > BNXT_VF_RESV_STRATEGY_MINIMAL_STATIC) 6922 pf->vf_resv_strategy = BNXT_VF_RESV_STRATEGY_MAXIMAL; 6923 } 6924 hwrm_func_resc_qcaps_exit: 6925 mutex_unlock(&bp->hwrm_cmd_lock); 6926 return rc; 6927 } 6928 6929 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp) 6930 { 6931 int rc = 0; 6932 struct hwrm_func_qcaps_input req = {0}; 6933 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr; 6934 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 6935 u32 flags; 6936 6937 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCAPS, -1, -1); 6938 req.fid = cpu_to_le16(0xffff); 6939 6940 mutex_lock(&bp->hwrm_cmd_lock); 6941 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 6942 if (rc) 6943 goto hwrm_func_qcaps_exit; 6944 6945 flags = le32_to_cpu(resp->flags); 6946 if (flags & FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED) 6947 bp->flags |= BNXT_FLAG_ROCEV1_CAP; 6948 if (flags & FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED) 6949 bp->flags |= BNXT_FLAG_ROCEV2_CAP; 6950 if (flags & FUNC_QCAPS_RESP_FLAGS_PCIE_STATS_SUPPORTED) 6951 bp->fw_cap |= BNXT_FW_CAP_PCIE_STATS_SUPPORTED; 6952 if (flags & FUNC_QCAPS_RESP_FLAGS_HOT_RESET_CAPABLE) 6953 bp->fw_cap |= BNXT_FW_CAP_HOT_RESET; 6954 if (flags & FUNC_QCAPS_RESP_FLAGS_EXT_STATS_SUPPORTED) 6955 bp->fw_cap |= BNXT_FW_CAP_EXT_STATS_SUPPORTED; 6956 if (flags & FUNC_QCAPS_RESP_FLAGS_ERROR_RECOVERY_CAPABLE) 6957 bp->fw_cap |= BNXT_FW_CAP_ERROR_RECOVERY; 6958 if (flags & FUNC_QCAPS_RESP_FLAGS_ERR_RECOVER_RELOAD) 6959 bp->fw_cap |= BNXT_FW_CAP_ERR_RECOVER_RELOAD; 6960 6961 bp->tx_push_thresh = 0; 6962 if (flags & FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED) 6963 bp->tx_push_thresh = BNXT_TX_PUSH_THRESH; 6964 6965 hw_resc->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx); 6966 hw_resc->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings); 6967 hw_resc->max_tx_rings = le16_to_cpu(resp->max_tx_rings); 6968 hw_resc->max_rx_rings = le16_to_cpu(resp->max_rx_rings); 6969 hw_resc->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps); 6970 if (!hw_resc->max_hw_ring_grps) 6971 hw_resc->max_hw_ring_grps = hw_resc->max_tx_rings; 6972 hw_resc->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs); 6973 hw_resc->max_vnics = le16_to_cpu(resp->max_vnics); 6974 hw_resc->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx); 6975 6976 if (BNXT_PF(bp)) { 6977 struct bnxt_pf_info *pf = &bp->pf; 6978 6979 pf->fw_fid = le16_to_cpu(resp->fid); 6980 pf->port_id = le16_to_cpu(resp->port_id); 6981 memcpy(pf->mac_addr, resp->mac_address, ETH_ALEN); 6982 pf->first_vf_id = le16_to_cpu(resp->first_vf_id); 6983 pf->max_vfs = le16_to_cpu(resp->max_vfs); 6984 pf->max_encap_records = le32_to_cpu(resp->max_encap_records); 6985 pf->max_decap_records = le32_to_cpu(resp->max_decap_records); 6986 pf->max_tx_em_flows = le32_to_cpu(resp->max_tx_em_flows); 6987 pf->max_tx_wm_flows = le32_to_cpu(resp->max_tx_wm_flows); 6988 pf->max_rx_em_flows = le32_to_cpu(resp->max_rx_em_flows); 6989 pf->max_rx_wm_flows = le32_to_cpu(resp->max_rx_wm_flows); 6990 bp->flags &= ~BNXT_FLAG_WOL_CAP; 6991 if (flags & FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED) 6992 bp->flags |= BNXT_FLAG_WOL_CAP; 6993 } else { 6994 #ifdef CONFIG_BNXT_SRIOV 6995 struct bnxt_vf_info *vf = &bp->vf; 6996 6997 vf->fw_fid = le16_to_cpu(resp->fid); 6998 memcpy(vf->mac_addr, resp->mac_address, ETH_ALEN); 6999 #endif 7000 } 7001 7002 hwrm_func_qcaps_exit: 7003 mutex_unlock(&bp->hwrm_cmd_lock); 7004 return rc; 7005 } 7006 7007 static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp); 7008 7009 static int bnxt_hwrm_func_qcaps(struct bnxt *bp) 7010 { 7011 int rc; 7012 7013 rc = __bnxt_hwrm_func_qcaps(bp); 7014 if (rc) 7015 return rc; 7016 rc = bnxt_hwrm_queue_qportcfg(bp); 7017 if (rc) { 7018 netdev_err(bp->dev, "hwrm query qportcfg failure rc: %d\n", rc); 7019 return rc; 7020 } 7021 if (bp->hwrm_spec_code >= 0x10803) { 7022 rc = bnxt_alloc_ctx_mem(bp); 7023 if (rc) 7024 return rc; 7025 rc = bnxt_hwrm_func_resc_qcaps(bp, true); 7026 if (!rc) 7027 bp->fw_cap |= BNXT_FW_CAP_NEW_RM; 7028 } 7029 return 0; 7030 } 7031 7032 static int bnxt_hwrm_cfa_adv_flow_mgnt_qcaps(struct bnxt *bp) 7033 { 7034 struct hwrm_cfa_adv_flow_mgnt_qcaps_input req = {0}; 7035 struct hwrm_cfa_adv_flow_mgnt_qcaps_output *resp; 7036 int rc = 0; 7037 u32 flags; 7038 7039 if (!(bp->fw_cap & BNXT_FW_CAP_CFA_ADV_FLOW)) 7040 return 0; 7041 7042 resp = bp->hwrm_cmd_resp_addr; 7043 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_ADV_FLOW_MGNT_QCAPS, -1, -1); 7044 7045 mutex_lock(&bp->hwrm_cmd_lock); 7046 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 7047 if (rc) 7048 goto hwrm_cfa_adv_qcaps_exit; 7049 7050 flags = le32_to_cpu(resp->flags); 7051 if (flags & 7052 CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RFS_RING_TBL_IDX_V2_SUPPORTED) 7053 bp->fw_cap |= BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V2; 7054 7055 hwrm_cfa_adv_qcaps_exit: 7056 mutex_unlock(&bp->hwrm_cmd_lock); 7057 return rc; 7058 } 7059 7060 static int bnxt_map_fw_health_regs(struct bnxt *bp) 7061 { 7062 struct bnxt_fw_health *fw_health = bp->fw_health; 7063 u32 reg_base = 0xffffffff; 7064 int i; 7065 7066 /* Only pre-map the monitoring GRC registers using window 3 */ 7067 for (i = 0; i < 4; i++) { 7068 u32 reg = fw_health->regs[i]; 7069 7070 if (BNXT_FW_HEALTH_REG_TYPE(reg) != BNXT_FW_HEALTH_REG_TYPE_GRC) 7071 continue; 7072 if (reg_base == 0xffffffff) 7073 reg_base = reg & BNXT_GRC_BASE_MASK; 7074 if ((reg & BNXT_GRC_BASE_MASK) != reg_base) 7075 return -ERANGE; 7076 fw_health->mapped_regs[i] = BNXT_FW_HEALTH_WIN_BASE + 7077 (reg & BNXT_GRC_OFFSET_MASK); 7078 } 7079 if (reg_base == 0xffffffff) 7080 return 0; 7081 7082 writel(reg_base, bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 7083 BNXT_FW_HEALTH_WIN_MAP_OFF); 7084 return 0; 7085 } 7086 7087 static int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp) 7088 { 7089 struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr; 7090 struct bnxt_fw_health *fw_health = bp->fw_health; 7091 struct hwrm_error_recovery_qcfg_input req = {0}; 7092 int rc, i; 7093 7094 if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)) 7095 return 0; 7096 7097 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_ERROR_RECOVERY_QCFG, -1, -1); 7098 mutex_lock(&bp->hwrm_cmd_lock); 7099 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 7100 if (rc) 7101 goto err_recovery_out; 7102 fw_health->flags = le32_to_cpu(resp->flags); 7103 if ((fw_health->flags & ERROR_RECOVERY_QCFG_RESP_FLAGS_CO_CPU) && 7104 !(bp->fw_cap & BNXT_FW_CAP_KONG_MB_CHNL)) { 7105 rc = -EINVAL; 7106 goto err_recovery_out; 7107 } 7108 fw_health->polling_dsecs = le32_to_cpu(resp->driver_polling_freq); 7109 fw_health->master_func_wait_dsecs = 7110 le32_to_cpu(resp->master_func_wait_period); 7111 fw_health->normal_func_wait_dsecs = 7112 le32_to_cpu(resp->normal_func_wait_period); 7113 fw_health->post_reset_wait_dsecs = 7114 le32_to_cpu(resp->master_func_wait_period_after_reset); 7115 fw_health->post_reset_max_wait_dsecs = 7116 le32_to_cpu(resp->max_bailout_time_after_reset); 7117 fw_health->regs[BNXT_FW_HEALTH_REG] = 7118 le32_to_cpu(resp->fw_health_status_reg); 7119 fw_health->regs[BNXT_FW_HEARTBEAT_REG] = 7120 le32_to_cpu(resp->fw_heartbeat_reg); 7121 fw_health->regs[BNXT_FW_RESET_CNT_REG] = 7122 le32_to_cpu(resp->fw_reset_cnt_reg); 7123 fw_health->regs[BNXT_FW_RESET_INPROG_REG] = 7124 le32_to_cpu(resp->reset_inprogress_reg); 7125 fw_health->fw_reset_inprog_reg_mask = 7126 le32_to_cpu(resp->reset_inprogress_reg_mask); 7127 fw_health->fw_reset_seq_cnt = resp->reg_array_cnt; 7128 if (fw_health->fw_reset_seq_cnt >= 16) { 7129 rc = -EINVAL; 7130 goto err_recovery_out; 7131 } 7132 for (i = 0; i < fw_health->fw_reset_seq_cnt; i++) { 7133 fw_health->fw_reset_seq_regs[i] = 7134 le32_to_cpu(resp->reset_reg[i]); 7135 fw_health->fw_reset_seq_vals[i] = 7136 le32_to_cpu(resp->reset_reg_val[i]); 7137 fw_health->fw_reset_seq_delay_msec[i] = 7138 resp->delay_after_reset[i]; 7139 } 7140 err_recovery_out: 7141 mutex_unlock(&bp->hwrm_cmd_lock); 7142 if (!rc) 7143 rc = bnxt_map_fw_health_regs(bp); 7144 if (rc) 7145 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY; 7146 return rc; 7147 } 7148 7149 static int bnxt_hwrm_func_reset(struct bnxt *bp) 7150 { 7151 struct hwrm_func_reset_input req = {0}; 7152 7153 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESET, -1, -1); 7154 req.enables = 0; 7155 7156 return hwrm_send_message(bp, &req, sizeof(req), HWRM_RESET_TIMEOUT); 7157 } 7158 7159 static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp) 7160 { 7161 int rc = 0; 7162 struct hwrm_queue_qportcfg_input req = {0}; 7163 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr; 7164 u8 i, j, *qptr; 7165 bool no_rdma; 7166 7167 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_QUEUE_QPORTCFG, -1, -1); 7168 7169 mutex_lock(&bp->hwrm_cmd_lock); 7170 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 7171 if (rc) 7172 goto qportcfg_exit; 7173 7174 if (!resp->max_configurable_queues) { 7175 rc = -EINVAL; 7176 goto qportcfg_exit; 7177 } 7178 bp->max_tc = resp->max_configurable_queues; 7179 bp->max_lltc = resp->max_configurable_lossless_queues; 7180 if (bp->max_tc > BNXT_MAX_QUEUE) 7181 bp->max_tc = BNXT_MAX_QUEUE; 7182 7183 no_rdma = !(bp->flags & BNXT_FLAG_ROCE_CAP); 7184 qptr = &resp->queue_id0; 7185 for (i = 0, j = 0; i < bp->max_tc; i++) { 7186 bp->q_info[j].queue_id = *qptr; 7187 bp->q_ids[i] = *qptr++; 7188 bp->q_info[j].queue_profile = *qptr++; 7189 bp->tc_to_qidx[j] = j; 7190 if (!BNXT_CNPQ(bp->q_info[j].queue_profile) || 7191 (no_rdma && BNXT_PF(bp))) 7192 j++; 7193 } 7194 bp->max_q = bp->max_tc; 7195 bp->max_tc = max_t(u8, j, 1); 7196 7197 if (resp->queue_cfg_info & QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG) 7198 bp->max_tc = 1; 7199 7200 if (bp->max_lltc > bp->max_tc) 7201 bp->max_lltc = bp->max_tc; 7202 7203 qportcfg_exit: 7204 mutex_unlock(&bp->hwrm_cmd_lock); 7205 return rc; 7206 } 7207 7208 static int __bnxt_hwrm_ver_get(struct bnxt *bp, bool silent) 7209 { 7210 struct hwrm_ver_get_input req = {0}; 7211 int rc; 7212 7213 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VER_GET, -1, -1); 7214 req.hwrm_intf_maj = HWRM_VERSION_MAJOR; 7215 req.hwrm_intf_min = HWRM_VERSION_MINOR; 7216 req.hwrm_intf_upd = HWRM_VERSION_UPDATE; 7217 7218 rc = bnxt_hwrm_do_send_msg(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT, 7219 silent); 7220 return rc; 7221 } 7222 7223 static int bnxt_hwrm_ver_get(struct bnxt *bp) 7224 { 7225 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr; 7226 u32 dev_caps_cfg; 7227 int rc; 7228 7229 bp->hwrm_max_req_len = HWRM_MAX_REQ_LEN; 7230 mutex_lock(&bp->hwrm_cmd_lock); 7231 rc = __bnxt_hwrm_ver_get(bp, false); 7232 if (rc) 7233 goto hwrm_ver_get_exit; 7234 7235 memcpy(&bp->ver_resp, resp, sizeof(struct hwrm_ver_get_output)); 7236 7237 bp->hwrm_spec_code = resp->hwrm_intf_maj_8b << 16 | 7238 resp->hwrm_intf_min_8b << 8 | 7239 resp->hwrm_intf_upd_8b; 7240 if (resp->hwrm_intf_maj_8b < 1) { 7241 netdev_warn(bp->dev, "HWRM interface %d.%d.%d is older than 1.0.0.\n", 7242 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b, 7243 resp->hwrm_intf_upd_8b); 7244 netdev_warn(bp->dev, "Please update firmware with HWRM interface 1.0.0 or newer.\n"); 7245 } 7246 snprintf(bp->fw_ver_str, BC_HWRM_STR_LEN, "%d.%d.%d.%d", 7247 resp->hwrm_fw_maj_8b, resp->hwrm_fw_min_8b, 7248 resp->hwrm_fw_bld_8b, resp->hwrm_fw_rsvd_8b); 7249 7250 if (strlen(resp->active_pkg_name)) { 7251 int fw_ver_len = strlen(bp->fw_ver_str); 7252 7253 snprintf(bp->fw_ver_str + fw_ver_len, 7254 FW_VER_STR_LEN - fw_ver_len - 1, "/pkg %s", 7255 resp->active_pkg_name); 7256 bp->fw_cap |= BNXT_FW_CAP_PKG_VER; 7257 } 7258 7259 bp->hwrm_cmd_timeout = le16_to_cpu(resp->def_req_timeout); 7260 if (!bp->hwrm_cmd_timeout) 7261 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT; 7262 7263 if (resp->hwrm_intf_maj_8b >= 1) { 7264 bp->hwrm_max_req_len = le16_to_cpu(resp->max_req_win_len); 7265 bp->hwrm_max_ext_req_len = le16_to_cpu(resp->max_ext_req_len); 7266 } 7267 if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN) 7268 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN; 7269 7270 bp->chip_num = le16_to_cpu(resp->chip_num); 7271 bp->chip_rev = resp->chip_rev; 7272 if (bp->chip_num == CHIP_NUM_58700 && !resp->chip_rev && 7273 !resp->chip_metal) 7274 bp->flags |= BNXT_FLAG_CHIP_NITRO_A0; 7275 7276 dev_caps_cfg = le32_to_cpu(resp->dev_caps_cfg); 7277 if ((dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) && 7278 (dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) 7279 bp->fw_cap |= BNXT_FW_CAP_SHORT_CMD; 7280 7281 if (dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) 7282 bp->fw_cap |= BNXT_FW_CAP_KONG_MB_CHNL; 7283 7284 if (dev_caps_cfg & 7285 VER_GET_RESP_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED) 7286 bp->fw_cap |= BNXT_FW_CAP_OVS_64BIT_HANDLE; 7287 7288 if (dev_caps_cfg & 7289 VER_GET_RESP_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED) 7290 bp->fw_cap |= BNXT_FW_CAP_TRUSTED_VF; 7291 7292 if (dev_caps_cfg & 7293 VER_GET_RESP_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED) 7294 bp->fw_cap |= BNXT_FW_CAP_CFA_ADV_FLOW; 7295 7296 hwrm_ver_get_exit: 7297 mutex_unlock(&bp->hwrm_cmd_lock); 7298 return rc; 7299 } 7300 7301 int bnxt_hwrm_fw_set_time(struct bnxt *bp) 7302 { 7303 struct hwrm_fw_set_time_input req = {0}; 7304 struct tm tm; 7305 time64_t now = ktime_get_real_seconds(); 7306 7307 if ((BNXT_VF(bp) && bp->hwrm_spec_code < 0x10901) || 7308 bp->hwrm_spec_code < 0x10400) 7309 return -EOPNOTSUPP; 7310 7311 time64_to_tm(now, 0, &tm); 7312 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FW_SET_TIME, -1, -1); 7313 req.year = cpu_to_le16(1900 + tm.tm_year); 7314 req.month = 1 + tm.tm_mon; 7315 req.day = tm.tm_mday; 7316 req.hour = tm.tm_hour; 7317 req.minute = tm.tm_min; 7318 req.second = tm.tm_sec; 7319 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 7320 } 7321 7322 static int bnxt_hwrm_port_qstats(struct bnxt *bp) 7323 { 7324 struct bnxt_pf_info *pf = &bp->pf; 7325 struct hwrm_port_qstats_input req = {0}; 7326 7327 if (!(bp->flags & BNXT_FLAG_PORT_STATS)) 7328 return 0; 7329 7330 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_QSTATS, -1, -1); 7331 req.port_id = cpu_to_le16(pf->port_id); 7332 req.tx_stat_host_addr = cpu_to_le64(bp->hw_tx_port_stats_map); 7333 req.rx_stat_host_addr = cpu_to_le64(bp->hw_rx_port_stats_map); 7334 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 7335 } 7336 7337 static int bnxt_hwrm_port_qstats_ext(struct bnxt *bp) 7338 { 7339 struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr; 7340 struct hwrm_queue_pri2cos_qcfg_input req2 = {0}; 7341 struct hwrm_port_qstats_ext_input req = {0}; 7342 struct bnxt_pf_info *pf = &bp->pf; 7343 u32 tx_stat_size; 7344 int rc; 7345 7346 if (!(bp->flags & BNXT_FLAG_PORT_STATS_EXT)) 7347 return 0; 7348 7349 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_QSTATS_EXT, -1, -1); 7350 req.port_id = cpu_to_le16(pf->port_id); 7351 req.rx_stat_size = cpu_to_le16(sizeof(struct rx_port_stats_ext)); 7352 req.rx_stat_host_addr = cpu_to_le64(bp->hw_rx_port_stats_ext_map); 7353 tx_stat_size = bp->hw_tx_port_stats_ext ? 7354 sizeof(*bp->hw_tx_port_stats_ext) : 0; 7355 req.tx_stat_size = cpu_to_le16(tx_stat_size); 7356 req.tx_stat_host_addr = cpu_to_le64(bp->hw_tx_port_stats_ext_map); 7357 mutex_lock(&bp->hwrm_cmd_lock); 7358 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 7359 if (!rc) { 7360 bp->fw_rx_stats_ext_size = le16_to_cpu(resp->rx_stat_size) / 8; 7361 bp->fw_tx_stats_ext_size = tx_stat_size ? 7362 le16_to_cpu(resp->tx_stat_size) / 8 : 0; 7363 } else { 7364 bp->fw_rx_stats_ext_size = 0; 7365 bp->fw_tx_stats_ext_size = 0; 7366 } 7367 if (bp->fw_tx_stats_ext_size <= 7368 offsetof(struct tx_port_stats_ext, pfc_pri0_tx_duration_us) / 8) { 7369 mutex_unlock(&bp->hwrm_cmd_lock); 7370 bp->pri2cos_valid = 0; 7371 return rc; 7372 } 7373 7374 bnxt_hwrm_cmd_hdr_init(bp, &req2, HWRM_QUEUE_PRI2COS_QCFG, -1, -1); 7375 req2.flags = cpu_to_le32(QUEUE_PRI2COS_QCFG_REQ_FLAGS_IVLAN); 7376 7377 rc = _hwrm_send_message(bp, &req2, sizeof(req2), HWRM_CMD_TIMEOUT); 7378 if (!rc) { 7379 struct hwrm_queue_pri2cos_qcfg_output *resp2; 7380 u8 *pri2cos; 7381 int i, j; 7382 7383 resp2 = bp->hwrm_cmd_resp_addr; 7384 pri2cos = &resp2->pri0_cos_queue_id; 7385 for (i = 0; i < 8; i++) { 7386 u8 queue_id = pri2cos[i]; 7387 7388 for (j = 0; j < bp->max_q; j++) { 7389 if (bp->q_ids[j] == queue_id) 7390 bp->pri2cos[i] = j; 7391 } 7392 } 7393 bp->pri2cos_valid = 1; 7394 } 7395 mutex_unlock(&bp->hwrm_cmd_lock); 7396 return rc; 7397 } 7398 7399 static int bnxt_hwrm_pcie_qstats(struct bnxt *bp) 7400 { 7401 struct hwrm_pcie_qstats_input req = {0}; 7402 7403 if (!(bp->flags & BNXT_FLAG_PCIE_STATS)) 7404 return 0; 7405 7406 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PCIE_QSTATS, -1, -1); 7407 req.pcie_stat_size = cpu_to_le16(sizeof(struct pcie_ctx_hw_stats)); 7408 req.pcie_stat_host_addr = cpu_to_le64(bp->hw_pcie_stats_map); 7409 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 7410 } 7411 7412 static void bnxt_hwrm_free_tunnel_ports(struct bnxt *bp) 7413 { 7414 if (bp->vxlan_port_cnt) { 7415 bnxt_hwrm_tunnel_dst_port_free( 7416 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN); 7417 } 7418 bp->vxlan_port_cnt = 0; 7419 if (bp->nge_port_cnt) { 7420 bnxt_hwrm_tunnel_dst_port_free( 7421 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE); 7422 } 7423 bp->nge_port_cnt = 0; 7424 } 7425 7426 static int bnxt_set_tpa(struct bnxt *bp, bool set_tpa) 7427 { 7428 int rc, i; 7429 u32 tpa_flags = 0; 7430 7431 if (set_tpa) 7432 tpa_flags = bp->flags & BNXT_FLAG_TPA; 7433 else if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state)) 7434 return 0; 7435 for (i = 0; i < bp->nr_vnics; i++) { 7436 rc = bnxt_hwrm_vnic_set_tpa(bp, i, tpa_flags); 7437 if (rc) { 7438 netdev_err(bp->dev, "hwrm vnic set tpa failure rc for vnic %d: %x\n", 7439 i, rc); 7440 return rc; 7441 } 7442 } 7443 return 0; 7444 } 7445 7446 static void bnxt_hwrm_clear_vnic_rss(struct bnxt *bp) 7447 { 7448 int i; 7449 7450 for (i = 0; i < bp->nr_vnics; i++) 7451 bnxt_hwrm_vnic_set_rss(bp, i, false); 7452 } 7453 7454 static void bnxt_clear_vnic(struct bnxt *bp) 7455 { 7456 if (!bp->vnic_info) 7457 return; 7458 7459 bnxt_hwrm_clear_vnic_filter(bp); 7460 if (!(bp->flags & BNXT_FLAG_CHIP_P5)) { 7461 /* clear all RSS setting before free vnic ctx */ 7462 bnxt_hwrm_clear_vnic_rss(bp); 7463 bnxt_hwrm_vnic_ctx_free(bp); 7464 } 7465 /* before free the vnic, undo the vnic tpa settings */ 7466 if (bp->flags & BNXT_FLAG_TPA) 7467 bnxt_set_tpa(bp, false); 7468 bnxt_hwrm_vnic_free(bp); 7469 if (bp->flags & BNXT_FLAG_CHIP_P5) 7470 bnxt_hwrm_vnic_ctx_free(bp); 7471 } 7472 7473 static void bnxt_hwrm_resource_free(struct bnxt *bp, bool close_path, 7474 bool irq_re_init) 7475 { 7476 bnxt_clear_vnic(bp); 7477 bnxt_hwrm_ring_free(bp, close_path); 7478 bnxt_hwrm_ring_grp_free(bp); 7479 if (irq_re_init) { 7480 bnxt_hwrm_stat_ctx_free(bp); 7481 bnxt_hwrm_free_tunnel_ports(bp); 7482 } 7483 } 7484 7485 static int bnxt_hwrm_set_br_mode(struct bnxt *bp, u16 br_mode) 7486 { 7487 struct hwrm_func_cfg_input req = {0}; 7488 7489 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1); 7490 req.fid = cpu_to_le16(0xffff); 7491 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_EVB_MODE); 7492 if (br_mode == BRIDGE_MODE_VEB) 7493 req.evb_mode = FUNC_CFG_REQ_EVB_MODE_VEB; 7494 else if (br_mode == BRIDGE_MODE_VEPA) 7495 req.evb_mode = FUNC_CFG_REQ_EVB_MODE_VEPA; 7496 else 7497 return -EINVAL; 7498 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 7499 } 7500 7501 static int bnxt_hwrm_set_cache_line_size(struct bnxt *bp, int size) 7502 { 7503 struct hwrm_func_cfg_input req = {0}; 7504 7505 if (BNXT_VF(bp) || bp->hwrm_spec_code < 0x10803) 7506 return 0; 7507 7508 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1); 7509 req.fid = cpu_to_le16(0xffff); 7510 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_CACHE_LINESIZE); 7511 req.options = FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_64; 7512 if (size == 128) 7513 req.options = FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128; 7514 7515 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 7516 } 7517 7518 static int __bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id) 7519 { 7520 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 7521 int rc; 7522 7523 if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG) 7524 goto skip_rss_ctx; 7525 7526 /* allocate context for vnic */ 7527 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 0); 7528 if (rc) { 7529 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n", 7530 vnic_id, rc); 7531 goto vnic_setup_err; 7532 } 7533 bp->rsscos_nr_ctxs++; 7534 7535 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) { 7536 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 1); 7537 if (rc) { 7538 netdev_err(bp->dev, "hwrm vnic %d cos ctx alloc failure rc: %x\n", 7539 vnic_id, rc); 7540 goto vnic_setup_err; 7541 } 7542 bp->rsscos_nr_ctxs++; 7543 } 7544 7545 skip_rss_ctx: 7546 /* configure default vnic, ring grp */ 7547 rc = bnxt_hwrm_vnic_cfg(bp, vnic_id); 7548 if (rc) { 7549 netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n", 7550 vnic_id, rc); 7551 goto vnic_setup_err; 7552 } 7553 7554 /* Enable RSS hashing on vnic */ 7555 rc = bnxt_hwrm_vnic_set_rss(bp, vnic_id, true); 7556 if (rc) { 7557 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %x\n", 7558 vnic_id, rc); 7559 goto vnic_setup_err; 7560 } 7561 7562 if (bp->flags & BNXT_FLAG_AGG_RINGS) { 7563 rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id); 7564 if (rc) { 7565 netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n", 7566 vnic_id, rc); 7567 } 7568 } 7569 7570 vnic_setup_err: 7571 return rc; 7572 } 7573 7574 static int __bnxt_setup_vnic_p5(struct bnxt *bp, u16 vnic_id) 7575 { 7576 int rc, i, nr_ctxs; 7577 7578 nr_ctxs = DIV_ROUND_UP(bp->rx_nr_rings, 64); 7579 for (i = 0; i < nr_ctxs; i++) { 7580 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, i); 7581 if (rc) { 7582 netdev_err(bp->dev, "hwrm vnic %d ctx %d alloc failure rc: %x\n", 7583 vnic_id, i, rc); 7584 break; 7585 } 7586 bp->rsscos_nr_ctxs++; 7587 } 7588 if (i < nr_ctxs) 7589 return -ENOMEM; 7590 7591 rc = bnxt_hwrm_vnic_set_rss_p5(bp, vnic_id, true); 7592 if (rc) { 7593 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %d\n", 7594 vnic_id, rc); 7595 return rc; 7596 } 7597 rc = bnxt_hwrm_vnic_cfg(bp, vnic_id); 7598 if (rc) { 7599 netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n", 7600 vnic_id, rc); 7601 return rc; 7602 } 7603 if (bp->flags & BNXT_FLAG_AGG_RINGS) { 7604 rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id); 7605 if (rc) { 7606 netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n", 7607 vnic_id, rc); 7608 } 7609 } 7610 return rc; 7611 } 7612 7613 static int bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id) 7614 { 7615 if (bp->flags & BNXT_FLAG_CHIP_P5) 7616 return __bnxt_setup_vnic_p5(bp, vnic_id); 7617 else 7618 return __bnxt_setup_vnic(bp, vnic_id); 7619 } 7620 7621 static int bnxt_alloc_rfs_vnics(struct bnxt *bp) 7622 { 7623 #ifdef CONFIG_RFS_ACCEL 7624 int i, rc = 0; 7625 7626 if (bp->flags & BNXT_FLAG_CHIP_P5) 7627 return 0; 7628 7629 for (i = 0; i < bp->rx_nr_rings; i++) { 7630 struct bnxt_vnic_info *vnic; 7631 u16 vnic_id = i + 1; 7632 u16 ring_id = i; 7633 7634 if (vnic_id >= bp->nr_vnics) 7635 break; 7636 7637 vnic = &bp->vnic_info[vnic_id]; 7638 vnic->flags |= BNXT_VNIC_RFS_FLAG; 7639 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP) 7640 vnic->flags |= BNXT_VNIC_RFS_NEW_RSS_FLAG; 7641 rc = bnxt_hwrm_vnic_alloc(bp, vnic_id, ring_id, 1); 7642 if (rc) { 7643 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n", 7644 vnic_id, rc); 7645 break; 7646 } 7647 rc = bnxt_setup_vnic(bp, vnic_id); 7648 if (rc) 7649 break; 7650 } 7651 return rc; 7652 #else 7653 return 0; 7654 #endif 7655 } 7656 7657 /* Allow PF and VF with default VLAN to be in promiscuous mode */ 7658 static bool bnxt_promisc_ok(struct bnxt *bp) 7659 { 7660 #ifdef CONFIG_BNXT_SRIOV 7661 if (BNXT_VF(bp) && !bp->vf.vlan) 7662 return false; 7663 #endif 7664 return true; 7665 } 7666 7667 static int bnxt_setup_nitroa0_vnic(struct bnxt *bp) 7668 { 7669 unsigned int rc = 0; 7670 7671 rc = bnxt_hwrm_vnic_alloc(bp, 1, bp->rx_nr_rings - 1, 1); 7672 if (rc) { 7673 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n", 7674 rc); 7675 return rc; 7676 } 7677 7678 rc = bnxt_hwrm_vnic_cfg(bp, 1); 7679 if (rc) { 7680 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n", 7681 rc); 7682 return rc; 7683 } 7684 return rc; 7685 } 7686 7687 static int bnxt_cfg_rx_mode(struct bnxt *); 7688 static bool bnxt_mc_list_updated(struct bnxt *, u32 *); 7689 7690 static int bnxt_init_chip(struct bnxt *bp, bool irq_re_init) 7691 { 7692 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 7693 int rc = 0; 7694 unsigned int rx_nr_rings = bp->rx_nr_rings; 7695 7696 if (irq_re_init) { 7697 rc = bnxt_hwrm_stat_ctx_alloc(bp); 7698 if (rc) { 7699 netdev_err(bp->dev, "hwrm stat ctx alloc failure rc: %x\n", 7700 rc); 7701 goto err_out; 7702 } 7703 } 7704 7705 rc = bnxt_hwrm_ring_alloc(bp); 7706 if (rc) { 7707 netdev_err(bp->dev, "hwrm ring alloc failure rc: %x\n", rc); 7708 goto err_out; 7709 } 7710 7711 rc = bnxt_hwrm_ring_grp_alloc(bp); 7712 if (rc) { 7713 netdev_err(bp->dev, "hwrm_ring_grp alloc failure: %x\n", rc); 7714 goto err_out; 7715 } 7716 7717 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 7718 rx_nr_rings--; 7719 7720 /* default vnic 0 */ 7721 rc = bnxt_hwrm_vnic_alloc(bp, 0, 0, rx_nr_rings); 7722 if (rc) { 7723 netdev_err(bp->dev, "hwrm vnic alloc failure rc: %x\n", rc); 7724 goto err_out; 7725 } 7726 7727 rc = bnxt_setup_vnic(bp, 0); 7728 if (rc) 7729 goto err_out; 7730 7731 if (bp->flags & BNXT_FLAG_RFS) { 7732 rc = bnxt_alloc_rfs_vnics(bp); 7733 if (rc) 7734 goto err_out; 7735 } 7736 7737 if (bp->flags & BNXT_FLAG_TPA) { 7738 rc = bnxt_set_tpa(bp, true); 7739 if (rc) 7740 goto err_out; 7741 } 7742 7743 if (BNXT_VF(bp)) 7744 bnxt_update_vf_mac(bp); 7745 7746 /* Filter for default vnic 0 */ 7747 rc = bnxt_hwrm_set_vnic_filter(bp, 0, 0, bp->dev->dev_addr); 7748 if (rc) { 7749 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n", rc); 7750 goto err_out; 7751 } 7752 vnic->uc_filter_count = 1; 7753 7754 vnic->rx_mask = 0; 7755 if (bp->dev->flags & IFF_BROADCAST) 7756 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_BCAST; 7757 7758 if ((bp->dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp)) 7759 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS; 7760 7761 if (bp->dev->flags & IFF_ALLMULTI) { 7762 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST; 7763 vnic->mc_list_count = 0; 7764 } else { 7765 u32 mask = 0; 7766 7767 bnxt_mc_list_updated(bp, &mask); 7768 vnic->rx_mask |= mask; 7769 } 7770 7771 rc = bnxt_cfg_rx_mode(bp); 7772 if (rc) 7773 goto err_out; 7774 7775 rc = bnxt_hwrm_set_coal(bp); 7776 if (rc) 7777 netdev_warn(bp->dev, "HWRM set coalescing failure rc: %x\n", 7778 rc); 7779 7780 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) { 7781 rc = bnxt_setup_nitroa0_vnic(bp); 7782 if (rc) 7783 netdev_err(bp->dev, "Special vnic setup failure for NS2 A0 rc: %x\n", 7784 rc); 7785 } 7786 7787 if (BNXT_VF(bp)) { 7788 bnxt_hwrm_func_qcfg(bp); 7789 netdev_update_features(bp->dev); 7790 } 7791 7792 return 0; 7793 7794 err_out: 7795 bnxt_hwrm_resource_free(bp, 0, true); 7796 7797 return rc; 7798 } 7799 7800 static int bnxt_shutdown_nic(struct bnxt *bp, bool irq_re_init) 7801 { 7802 bnxt_hwrm_resource_free(bp, 1, irq_re_init); 7803 return 0; 7804 } 7805 7806 static int bnxt_init_nic(struct bnxt *bp, bool irq_re_init) 7807 { 7808 bnxt_init_cp_rings(bp); 7809 bnxt_init_rx_rings(bp); 7810 bnxt_init_tx_rings(bp); 7811 bnxt_init_ring_grps(bp, irq_re_init); 7812 bnxt_init_vnics(bp); 7813 7814 return bnxt_init_chip(bp, irq_re_init); 7815 } 7816 7817 static int bnxt_set_real_num_queues(struct bnxt *bp) 7818 { 7819 int rc; 7820 struct net_device *dev = bp->dev; 7821 7822 rc = netif_set_real_num_tx_queues(dev, bp->tx_nr_rings - 7823 bp->tx_nr_rings_xdp); 7824 if (rc) 7825 return rc; 7826 7827 rc = netif_set_real_num_rx_queues(dev, bp->rx_nr_rings); 7828 if (rc) 7829 return rc; 7830 7831 #ifdef CONFIG_RFS_ACCEL 7832 if (bp->flags & BNXT_FLAG_RFS) 7833 dev->rx_cpu_rmap = alloc_irq_cpu_rmap(bp->rx_nr_rings); 7834 #endif 7835 7836 return rc; 7837 } 7838 7839 static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max, 7840 bool shared) 7841 { 7842 int _rx = *rx, _tx = *tx; 7843 7844 if (shared) { 7845 *rx = min_t(int, _rx, max); 7846 *tx = min_t(int, _tx, max); 7847 } else { 7848 if (max < 2) 7849 return -ENOMEM; 7850 7851 while (_rx + _tx > max) { 7852 if (_rx > _tx && _rx > 1) 7853 _rx--; 7854 else if (_tx > 1) 7855 _tx--; 7856 } 7857 *rx = _rx; 7858 *tx = _tx; 7859 } 7860 return 0; 7861 } 7862 7863 static void bnxt_setup_msix(struct bnxt *bp) 7864 { 7865 const int len = sizeof(bp->irq_tbl[0].name); 7866 struct net_device *dev = bp->dev; 7867 int tcs, i; 7868 7869 tcs = netdev_get_num_tc(dev); 7870 if (tcs) { 7871 int i, off, count; 7872 7873 for (i = 0; i < tcs; i++) { 7874 count = bp->tx_nr_rings_per_tc; 7875 off = i * count; 7876 netdev_set_tc_queue(dev, i, count, off); 7877 } 7878 } 7879 7880 for (i = 0; i < bp->cp_nr_rings; i++) { 7881 int map_idx = bnxt_cp_num_to_irq_num(bp, i); 7882 char *attr; 7883 7884 if (bp->flags & BNXT_FLAG_SHARED_RINGS) 7885 attr = "TxRx"; 7886 else if (i < bp->rx_nr_rings) 7887 attr = "rx"; 7888 else 7889 attr = "tx"; 7890 7891 snprintf(bp->irq_tbl[map_idx].name, len, "%s-%s-%d", dev->name, 7892 attr, i); 7893 bp->irq_tbl[map_idx].handler = bnxt_msix; 7894 } 7895 } 7896 7897 static void bnxt_setup_inta(struct bnxt *bp) 7898 { 7899 const int len = sizeof(bp->irq_tbl[0].name); 7900 7901 if (netdev_get_num_tc(bp->dev)) 7902 netdev_reset_tc(bp->dev); 7903 7904 snprintf(bp->irq_tbl[0].name, len, "%s-%s-%d", bp->dev->name, "TxRx", 7905 0); 7906 bp->irq_tbl[0].handler = bnxt_inta; 7907 } 7908 7909 static int bnxt_setup_int_mode(struct bnxt *bp) 7910 { 7911 int rc; 7912 7913 if (bp->flags & BNXT_FLAG_USING_MSIX) 7914 bnxt_setup_msix(bp); 7915 else 7916 bnxt_setup_inta(bp); 7917 7918 rc = bnxt_set_real_num_queues(bp); 7919 return rc; 7920 } 7921 7922 #ifdef CONFIG_RFS_ACCEL 7923 static unsigned int bnxt_get_max_func_rss_ctxs(struct bnxt *bp) 7924 { 7925 return bp->hw_resc.max_rsscos_ctxs; 7926 } 7927 7928 static unsigned int bnxt_get_max_func_vnics(struct bnxt *bp) 7929 { 7930 return bp->hw_resc.max_vnics; 7931 } 7932 #endif 7933 7934 unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt *bp) 7935 { 7936 return bp->hw_resc.max_stat_ctxs; 7937 } 7938 7939 unsigned int bnxt_get_max_func_cp_rings(struct bnxt *bp) 7940 { 7941 return bp->hw_resc.max_cp_rings; 7942 } 7943 7944 static unsigned int bnxt_get_max_func_cp_rings_for_en(struct bnxt *bp) 7945 { 7946 unsigned int cp = bp->hw_resc.max_cp_rings; 7947 7948 if (!(bp->flags & BNXT_FLAG_CHIP_P5)) 7949 cp -= bnxt_get_ulp_msix_num(bp); 7950 7951 return cp; 7952 } 7953 7954 static unsigned int bnxt_get_max_func_irqs(struct bnxt *bp) 7955 { 7956 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 7957 7958 if (bp->flags & BNXT_FLAG_CHIP_P5) 7959 return min_t(unsigned int, hw_resc->max_irqs, hw_resc->max_nqs); 7960 7961 return min_t(unsigned int, hw_resc->max_irqs, hw_resc->max_cp_rings); 7962 } 7963 7964 static void bnxt_set_max_func_irqs(struct bnxt *bp, unsigned int max_irqs) 7965 { 7966 bp->hw_resc.max_irqs = max_irqs; 7967 } 7968 7969 unsigned int bnxt_get_avail_cp_rings_for_en(struct bnxt *bp) 7970 { 7971 unsigned int cp; 7972 7973 cp = bnxt_get_max_func_cp_rings_for_en(bp); 7974 if (bp->flags & BNXT_FLAG_CHIP_P5) 7975 return cp - bp->rx_nr_rings - bp->tx_nr_rings; 7976 else 7977 return cp - bp->cp_nr_rings; 7978 } 7979 7980 unsigned int bnxt_get_avail_stat_ctxs_for_en(struct bnxt *bp) 7981 { 7982 return bnxt_get_max_func_stat_ctxs(bp) - bnxt_get_func_stat_ctxs(bp); 7983 } 7984 7985 int bnxt_get_avail_msix(struct bnxt *bp, int num) 7986 { 7987 int max_cp = bnxt_get_max_func_cp_rings(bp); 7988 int max_irq = bnxt_get_max_func_irqs(bp); 7989 int total_req = bp->cp_nr_rings + num; 7990 int max_idx, avail_msix; 7991 7992 max_idx = bp->total_irqs; 7993 if (!(bp->flags & BNXT_FLAG_CHIP_P5)) 7994 max_idx = min_t(int, bp->total_irqs, max_cp); 7995 avail_msix = max_idx - bp->cp_nr_rings; 7996 if (!BNXT_NEW_RM(bp) || avail_msix >= num) 7997 return avail_msix; 7998 7999 if (max_irq < total_req) { 8000 num = max_irq - bp->cp_nr_rings; 8001 if (num <= 0) 8002 return 0; 8003 } 8004 return num; 8005 } 8006 8007 static int bnxt_get_num_msix(struct bnxt *bp) 8008 { 8009 if (!BNXT_NEW_RM(bp)) 8010 return bnxt_get_max_func_irqs(bp); 8011 8012 return bnxt_nq_rings_in_use(bp); 8013 } 8014 8015 static int bnxt_init_msix(struct bnxt *bp) 8016 { 8017 int i, total_vecs, max, rc = 0, min = 1, ulp_msix; 8018 struct msix_entry *msix_ent; 8019 8020 total_vecs = bnxt_get_num_msix(bp); 8021 max = bnxt_get_max_func_irqs(bp); 8022 if (total_vecs > max) 8023 total_vecs = max; 8024 8025 if (!total_vecs) 8026 return 0; 8027 8028 msix_ent = kcalloc(total_vecs, sizeof(struct msix_entry), GFP_KERNEL); 8029 if (!msix_ent) 8030 return -ENOMEM; 8031 8032 for (i = 0; i < total_vecs; i++) { 8033 msix_ent[i].entry = i; 8034 msix_ent[i].vector = 0; 8035 } 8036 8037 if (!(bp->flags & BNXT_FLAG_SHARED_RINGS)) 8038 min = 2; 8039 8040 total_vecs = pci_enable_msix_range(bp->pdev, msix_ent, min, total_vecs); 8041 ulp_msix = bnxt_get_ulp_msix_num(bp); 8042 if (total_vecs < 0 || total_vecs < ulp_msix) { 8043 rc = -ENODEV; 8044 goto msix_setup_exit; 8045 } 8046 8047 bp->irq_tbl = kcalloc(total_vecs, sizeof(struct bnxt_irq), GFP_KERNEL); 8048 if (bp->irq_tbl) { 8049 for (i = 0; i < total_vecs; i++) 8050 bp->irq_tbl[i].vector = msix_ent[i].vector; 8051 8052 bp->total_irqs = total_vecs; 8053 /* Trim rings based upon num of vectors allocated */ 8054 rc = bnxt_trim_rings(bp, &bp->rx_nr_rings, &bp->tx_nr_rings, 8055 total_vecs - ulp_msix, min == 1); 8056 if (rc) 8057 goto msix_setup_exit; 8058 8059 bp->cp_nr_rings = (min == 1) ? 8060 max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) : 8061 bp->tx_nr_rings + bp->rx_nr_rings; 8062 8063 } else { 8064 rc = -ENOMEM; 8065 goto msix_setup_exit; 8066 } 8067 bp->flags |= BNXT_FLAG_USING_MSIX; 8068 kfree(msix_ent); 8069 return 0; 8070 8071 msix_setup_exit: 8072 netdev_err(bp->dev, "bnxt_init_msix err: %x\n", rc); 8073 kfree(bp->irq_tbl); 8074 bp->irq_tbl = NULL; 8075 pci_disable_msix(bp->pdev); 8076 kfree(msix_ent); 8077 return rc; 8078 } 8079 8080 static int bnxt_init_inta(struct bnxt *bp) 8081 { 8082 bp->irq_tbl = kcalloc(1, sizeof(struct bnxt_irq), GFP_KERNEL); 8083 if (!bp->irq_tbl) 8084 return -ENOMEM; 8085 8086 bp->total_irqs = 1; 8087 bp->rx_nr_rings = 1; 8088 bp->tx_nr_rings = 1; 8089 bp->cp_nr_rings = 1; 8090 bp->flags |= BNXT_FLAG_SHARED_RINGS; 8091 bp->irq_tbl[0].vector = bp->pdev->irq; 8092 return 0; 8093 } 8094 8095 static int bnxt_init_int_mode(struct bnxt *bp) 8096 { 8097 int rc = 0; 8098 8099 if (bp->flags & BNXT_FLAG_MSIX_CAP) 8100 rc = bnxt_init_msix(bp); 8101 8102 if (!(bp->flags & BNXT_FLAG_USING_MSIX) && BNXT_PF(bp)) { 8103 /* fallback to INTA */ 8104 rc = bnxt_init_inta(bp); 8105 } 8106 return rc; 8107 } 8108 8109 static void bnxt_clear_int_mode(struct bnxt *bp) 8110 { 8111 if (bp->flags & BNXT_FLAG_USING_MSIX) 8112 pci_disable_msix(bp->pdev); 8113 8114 kfree(bp->irq_tbl); 8115 bp->irq_tbl = NULL; 8116 bp->flags &= ~BNXT_FLAG_USING_MSIX; 8117 } 8118 8119 int bnxt_reserve_rings(struct bnxt *bp, bool irq_re_init) 8120 { 8121 int tcs = netdev_get_num_tc(bp->dev); 8122 bool irq_cleared = false; 8123 int rc; 8124 8125 if (!bnxt_need_reserve_rings(bp)) 8126 return 0; 8127 8128 if (irq_re_init && BNXT_NEW_RM(bp) && 8129 bnxt_get_num_msix(bp) != bp->total_irqs) { 8130 bnxt_ulp_irq_stop(bp); 8131 bnxt_clear_int_mode(bp); 8132 irq_cleared = true; 8133 } 8134 rc = __bnxt_reserve_rings(bp); 8135 if (irq_cleared) { 8136 if (!rc) 8137 rc = bnxt_init_int_mode(bp); 8138 bnxt_ulp_irq_restart(bp, rc); 8139 } 8140 if (rc) { 8141 netdev_err(bp->dev, "ring reservation/IRQ init failure rc: %d\n", rc); 8142 return rc; 8143 } 8144 if (tcs && (bp->tx_nr_rings_per_tc * tcs != bp->tx_nr_rings)) { 8145 netdev_err(bp->dev, "tx ring reservation failure\n"); 8146 netdev_reset_tc(bp->dev); 8147 bp->tx_nr_rings_per_tc = bp->tx_nr_rings; 8148 return -ENOMEM; 8149 } 8150 return 0; 8151 } 8152 8153 static void bnxt_free_irq(struct bnxt *bp) 8154 { 8155 struct bnxt_irq *irq; 8156 int i; 8157 8158 #ifdef CONFIG_RFS_ACCEL 8159 free_irq_cpu_rmap(bp->dev->rx_cpu_rmap); 8160 bp->dev->rx_cpu_rmap = NULL; 8161 #endif 8162 if (!bp->irq_tbl || !bp->bnapi) 8163 return; 8164 8165 for (i = 0; i < bp->cp_nr_rings; i++) { 8166 int map_idx = bnxt_cp_num_to_irq_num(bp, i); 8167 8168 irq = &bp->irq_tbl[map_idx]; 8169 if (irq->requested) { 8170 if (irq->have_cpumask) { 8171 irq_set_affinity_hint(irq->vector, NULL); 8172 free_cpumask_var(irq->cpu_mask); 8173 irq->have_cpumask = 0; 8174 } 8175 free_irq(irq->vector, bp->bnapi[i]); 8176 } 8177 8178 irq->requested = 0; 8179 } 8180 } 8181 8182 static int bnxt_request_irq(struct bnxt *bp) 8183 { 8184 int i, j, rc = 0; 8185 unsigned long flags = 0; 8186 #ifdef CONFIG_RFS_ACCEL 8187 struct cpu_rmap *rmap; 8188 #endif 8189 8190 rc = bnxt_setup_int_mode(bp); 8191 if (rc) { 8192 netdev_err(bp->dev, "bnxt_setup_int_mode err: %x\n", 8193 rc); 8194 return rc; 8195 } 8196 #ifdef CONFIG_RFS_ACCEL 8197 rmap = bp->dev->rx_cpu_rmap; 8198 #endif 8199 if (!(bp->flags & BNXT_FLAG_USING_MSIX)) 8200 flags = IRQF_SHARED; 8201 8202 for (i = 0, j = 0; i < bp->cp_nr_rings; i++) { 8203 int map_idx = bnxt_cp_num_to_irq_num(bp, i); 8204 struct bnxt_irq *irq = &bp->irq_tbl[map_idx]; 8205 8206 #ifdef CONFIG_RFS_ACCEL 8207 if (rmap && bp->bnapi[i]->rx_ring) { 8208 rc = irq_cpu_rmap_add(rmap, irq->vector); 8209 if (rc) 8210 netdev_warn(bp->dev, "failed adding irq rmap for ring %d\n", 8211 j); 8212 j++; 8213 } 8214 #endif 8215 rc = request_irq(irq->vector, irq->handler, flags, irq->name, 8216 bp->bnapi[i]); 8217 if (rc) 8218 break; 8219 8220 irq->requested = 1; 8221 8222 if (zalloc_cpumask_var(&irq->cpu_mask, GFP_KERNEL)) { 8223 int numa_node = dev_to_node(&bp->pdev->dev); 8224 8225 irq->have_cpumask = 1; 8226 cpumask_set_cpu(cpumask_local_spread(i, numa_node), 8227 irq->cpu_mask); 8228 rc = irq_set_affinity_hint(irq->vector, irq->cpu_mask); 8229 if (rc) { 8230 netdev_warn(bp->dev, 8231 "Set affinity failed, IRQ = %d\n", 8232 irq->vector); 8233 break; 8234 } 8235 } 8236 } 8237 return rc; 8238 } 8239 8240 static void bnxt_del_napi(struct bnxt *bp) 8241 { 8242 int i; 8243 8244 if (!bp->bnapi) 8245 return; 8246 8247 for (i = 0; i < bp->cp_nr_rings; i++) { 8248 struct bnxt_napi *bnapi = bp->bnapi[i]; 8249 8250 napi_hash_del(&bnapi->napi); 8251 netif_napi_del(&bnapi->napi); 8252 } 8253 /* We called napi_hash_del() before netif_napi_del(), we need 8254 * to respect an RCU grace period before freeing napi structures. 8255 */ 8256 synchronize_net(); 8257 } 8258 8259 static void bnxt_init_napi(struct bnxt *bp) 8260 { 8261 int i; 8262 unsigned int cp_nr_rings = bp->cp_nr_rings; 8263 struct bnxt_napi *bnapi; 8264 8265 if (bp->flags & BNXT_FLAG_USING_MSIX) { 8266 int (*poll_fn)(struct napi_struct *, int) = bnxt_poll; 8267 8268 if (bp->flags & BNXT_FLAG_CHIP_P5) 8269 poll_fn = bnxt_poll_p5; 8270 else if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 8271 cp_nr_rings--; 8272 for (i = 0; i < cp_nr_rings; i++) { 8273 bnapi = bp->bnapi[i]; 8274 netif_napi_add(bp->dev, &bnapi->napi, poll_fn, 64); 8275 } 8276 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) { 8277 bnapi = bp->bnapi[cp_nr_rings]; 8278 netif_napi_add(bp->dev, &bnapi->napi, 8279 bnxt_poll_nitroa0, 64); 8280 } 8281 } else { 8282 bnapi = bp->bnapi[0]; 8283 netif_napi_add(bp->dev, &bnapi->napi, bnxt_poll, 64); 8284 } 8285 } 8286 8287 static void bnxt_disable_napi(struct bnxt *bp) 8288 { 8289 int i; 8290 8291 if (!bp->bnapi) 8292 return; 8293 8294 for (i = 0; i < bp->cp_nr_rings; i++) { 8295 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring; 8296 8297 if (bp->bnapi[i]->rx_ring) 8298 cancel_work_sync(&cpr->dim.work); 8299 8300 napi_disable(&bp->bnapi[i]->napi); 8301 } 8302 } 8303 8304 static void bnxt_enable_napi(struct bnxt *bp) 8305 { 8306 int i; 8307 8308 for (i = 0; i < bp->cp_nr_rings; i++) { 8309 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring; 8310 bp->bnapi[i]->in_reset = false; 8311 8312 if (bp->bnapi[i]->rx_ring) { 8313 INIT_WORK(&cpr->dim.work, bnxt_dim_work); 8314 cpr->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE; 8315 } 8316 napi_enable(&bp->bnapi[i]->napi); 8317 } 8318 } 8319 8320 void bnxt_tx_disable(struct bnxt *bp) 8321 { 8322 int i; 8323 struct bnxt_tx_ring_info *txr; 8324 8325 if (bp->tx_ring) { 8326 for (i = 0; i < bp->tx_nr_rings; i++) { 8327 txr = &bp->tx_ring[i]; 8328 txr->dev_state = BNXT_DEV_STATE_CLOSING; 8329 } 8330 } 8331 /* Stop all TX queues */ 8332 netif_tx_disable(bp->dev); 8333 netif_carrier_off(bp->dev); 8334 } 8335 8336 void bnxt_tx_enable(struct bnxt *bp) 8337 { 8338 int i; 8339 struct bnxt_tx_ring_info *txr; 8340 8341 for (i = 0; i < bp->tx_nr_rings; i++) { 8342 txr = &bp->tx_ring[i]; 8343 txr->dev_state = 0; 8344 } 8345 netif_tx_wake_all_queues(bp->dev); 8346 if (bp->link_info.link_up) 8347 netif_carrier_on(bp->dev); 8348 } 8349 8350 static void bnxt_report_link(struct bnxt *bp) 8351 { 8352 if (bp->link_info.link_up) { 8353 const char *duplex; 8354 const char *flow_ctrl; 8355 u32 speed; 8356 u16 fec; 8357 8358 netif_carrier_on(bp->dev); 8359 if (bp->link_info.duplex == BNXT_LINK_DUPLEX_FULL) 8360 duplex = "full"; 8361 else 8362 duplex = "half"; 8363 if (bp->link_info.pause == BNXT_LINK_PAUSE_BOTH) 8364 flow_ctrl = "ON - receive & transmit"; 8365 else if (bp->link_info.pause == BNXT_LINK_PAUSE_TX) 8366 flow_ctrl = "ON - transmit"; 8367 else if (bp->link_info.pause == BNXT_LINK_PAUSE_RX) 8368 flow_ctrl = "ON - receive"; 8369 else 8370 flow_ctrl = "none"; 8371 speed = bnxt_fw_to_ethtool_speed(bp->link_info.link_speed); 8372 netdev_info(bp->dev, "NIC Link is Up, %u Mbps %s duplex, Flow control: %s\n", 8373 speed, duplex, flow_ctrl); 8374 if (bp->flags & BNXT_FLAG_EEE_CAP) 8375 netdev_info(bp->dev, "EEE is %s\n", 8376 bp->eee.eee_active ? "active" : 8377 "not active"); 8378 fec = bp->link_info.fec_cfg; 8379 if (!(fec & PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED)) 8380 netdev_info(bp->dev, "FEC autoneg %s encodings: %s\n", 8381 (fec & BNXT_FEC_AUTONEG) ? "on" : "off", 8382 (fec & BNXT_FEC_ENC_BASE_R) ? "BaseR" : 8383 (fec & BNXT_FEC_ENC_RS) ? "RS" : "None"); 8384 } else { 8385 netif_carrier_off(bp->dev); 8386 netdev_err(bp->dev, "NIC Link is Down\n"); 8387 } 8388 } 8389 8390 static int bnxt_hwrm_phy_qcaps(struct bnxt *bp) 8391 { 8392 int rc = 0; 8393 struct hwrm_port_phy_qcaps_input req = {0}; 8394 struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr; 8395 struct bnxt_link_info *link_info = &bp->link_info; 8396 8397 bp->flags &= ~BNXT_FLAG_EEE_CAP; 8398 if (bp->test_info) 8399 bp->test_info->flags &= ~(BNXT_TEST_FL_EXT_LPBK | 8400 BNXT_TEST_FL_AN_PHY_LPBK); 8401 if (bp->hwrm_spec_code < 0x10201) 8402 return 0; 8403 8404 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCAPS, -1, -1); 8405 8406 mutex_lock(&bp->hwrm_cmd_lock); 8407 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 8408 if (rc) 8409 goto hwrm_phy_qcaps_exit; 8410 8411 if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED) { 8412 struct ethtool_eee *eee = &bp->eee; 8413 u16 fw_speeds = le16_to_cpu(resp->supported_speeds_eee_mode); 8414 8415 bp->flags |= BNXT_FLAG_EEE_CAP; 8416 eee->supported = _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0); 8417 bp->lpi_tmr_lo = le32_to_cpu(resp->tx_lpi_timer_low) & 8418 PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK; 8419 bp->lpi_tmr_hi = le32_to_cpu(resp->valid_tx_lpi_timer_high) & 8420 PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK; 8421 } 8422 if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_EXTERNAL_LPBK_SUPPORTED) { 8423 if (bp->test_info) 8424 bp->test_info->flags |= BNXT_TEST_FL_EXT_LPBK; 8425 } 8426 if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_AUTONEG_LPBK_SUPPORTED) { 8427 if (bp->test_info) 8428 bp->test_info->flags |= BNXT_TEST_FL_AN_PHY_LPBK; 8429 } 8430 if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_SHARED_PHY_CFG_SUPPORTED) { 8431 if (BNXT_PF(bp)) 8432 bp->fw_cap |= BNXT_FW_CAP_SHARED_PORT_CFG; 8433 } 8434 if (resp->supported_speeds_auto_mode) 8435 link_info->support_auto_speeds = 8436 le16_to_cpu(resp->supported_speeds_auto_mode); 8437 8438 bp->port_count = resp->port_cnt; 8439 8440 hwrm_phy_qcaps_exit: 8441 mutex_unlock(&bp->hwrm_cmd_lock); 8442 return rc; 8443 } 8444 8445 static int bnxt_update_link(struct bnxt *bp, bool chng_link_state) 8446 { 8447 int rc = 0; 8448 struct bnxt_link_info *link_info = &bp->link_info; 8449 struct hwrm_port_phy_qcfg_input req = {0}; 8450 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr; 8451 u8 link_up = link_info->link_up; 8452 u16 diff; 8453 8454 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCFG, -1, -1); 8455 8456 mutex_lock(&bp->hwrm_cmd_lock); 8457 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 8458 if (rc) { 8459 mutex_unlock(&bp->hwrm_cmd_lock); 8460 return rc; 8461 } 8462 8463 memcpy(&link_info->phy_qcfg_resp, resp, sizeof(*resp)); 8464 link_info->phy_link_status = resp->link; 8465 link_info->duplex = resp->duplex_cfg; 8466 if (bp->hwrm_spec_code >= 0x10800) 8467 link_info->duplex = resp->duplex_state; 8468 link_info->pause = resp->pause; 8469 link_info->auto_mode = resp->auto_mode; 8470 link_info->auto_pause_setting = resp->auto_pause; 8471 link_info->lp_pause = resp->link_partner_adv_pause; 8472 link_info->force_pause_setting = resp->force_pause; 8473 link_info->duplex_setting = resp->duplex_cfg; 8474 if (link_info->phy_link_status == BNXT_LINK_LINK) 8475 link_info->link_speed = le16_to_cpu(resp->link_speed); 8476 else 8477 link_info->link_speed = 0; 8478 link_info->force_link_speed = le16_to_cpu(resp->force_link_speed); 8479 link_info->support_speeds = le16_to_cpu(resp->support_speeds); 8480 link_info->auto_link_speeds = le16_to_cpu(resp->auto_link_speed_mask); 8481 link_info->lp_auto_link_speeds = 8482 le16_to_cpu(resp->link_partner_adv_speeds); 8483 link_info->preemphasis = le32_to_cpu(resp->preemphasis); 8484 link_info->phy_ver[0] = resp->phy_maj; 8485 link_info->phy_ver[1] = resp->phy_min; 8486 link_info->phy_ver[2] = resp->phy_bld; 8487 link_info->media_type = resp->media_type; 8488 link_info->phy_type = resp->phy_type; 8489 link_info->transceiver = resp->xcvr_pkg_type; 8490 link_info->phy_addr = resp->eee_config_phy_addr & 8491 PORT_PHY_QCFG_RESP_PHY_ADDR_MASK; 8492 link_info->module_status = resp->module_status; 8493 8494 if (bp->flags & BNXT_FLAG_EEE_CAP) { 8495 struct ethtool_eee *eee = &bp->eee; 8496 u16 fw_speeds; 8497 8498 eee->eee_active = 0; 8499 if (resp->eee_config_phy_addr & 8500 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE) { 8501 eee->eee_active = 1; 8502 fw_speeds = le16_to_cpu( 8503 resp->link_partner_adv_eee_link_speed_mask); 8504 eee->lp_advertised = 8505 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0); 8506 } 8507 8508 /* Pull initial EEE config */ 8509 if (!chng_link_state) { 8510 if (resp->eee_config_phy_addr & 8511 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED) 8512 eee->eee_enabled = 1; 8513 8514 fw_speeds = le16_to_cpu(resp->adv_eee_link_speed_mask); 8515 eee->advertised = 8516 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0); 8517 8518 if (resp->eee_config_phy_addr & 8519 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI) { 8520 __le32 tmr; 8521 8522 eee->tx_lpi_enabled = 1; 8523 tmr = resp->xcvr_identifier_type_tx_lpi_timer; 8524 eee->tx_lpi_timer = le32_to_cpu(tmr) & 8525 PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK; 8526 } 8527 } 8528 } 8529 8530 link_info->fec_cfg = PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED; 8531 if (bp->hwrm_spec_code >= 0x10504) 8532 link_info->fec_cfg = le16_to_cpu(resp->fec_cfg); 8533 8534 /* TODO: need to add more logic to report VF link */ 8535 if (chng_link_state) { 8536 if (link_info->phy_link_status == BNXT_LINK_LINK) 8537 link_info->link_up = 1; 8538 else 8539 link_info->link_up = 0; 8540 if (link_up != link_info->link_up) 8541 bnxt_report_link(bp); 8542 } else { 8543 /* alwasy link down if not require to update link state */ 8544 link_info->link_up = 0; 8545 } 8546 mutex_unlock(&bp->hwrm_cmd_lock); 8547 8548 if (!BNXT_PHY_CFG_ABLE(bp)) 8549 return 0; 8550 8551 diff = link_info->support_auto_speeds ^ link_info->advertising; 8552 if ((link_info->support_auto_speeds | diff) != 8553 link_info->support_auto_speeds) { 8554 /* An advertised speed is no longer supported, so we need to 8555 * update the advertisement settings. Caller holds RTNL 8556 * so we can modify link settings. 8557 */ 8558 link_info->advertising = link_info->support_auto_speeds; 8559 if (link_info->autoneg & BNXT_AUTONEG_SPEED) 8560 bnxt_hwrm_set_link_setting(bp, true, false); 8561 } 8562 return 0; 8563 } 8564 8565 static void bnxt_get_port_module_status(struct bnxt *bp) 8566 { 8567 struct bnxt_link_info *link_info = &bp->link_info; 8568 struct hwrm_port_phy_qcfg_output *resp = &link_info->phy_qcfg_resp; 8569 u8 module_status; 8570 8571 if (bnxt_update_link(bp, true)) 8572 return; 8573 8574 module_status = link_info->module_status; 8575 switch (module_status) { 8576 case PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX: 8577 case PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN: 8578 case PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG: 8579 netdev_warn(bp->dev, "Unqualified SFP+ module detected on port %d\n", 8580 bp->pf.port_id); 8581 if (bp->hwrm_spec_code >= 0x10201) { 8582 netdev_warn(bp->dev, "Module part number %s\n", 8583 resp->phy_vendor_partnumber); 8584 } 8585 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX) 8586 netdev_warn(bp->dev, "TX is disabled\n"); 8587 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN) 8588 netdev_warn(bp->dev, "SFP+ module is shutdown\n"); 8589 } 8590 } 8591 8592 static void 8593 bnxt_hwrm_set_pause_common(struct bnxt *bp, struct hwrm_port_phy_cfg_input *req) 8594 { 8595 if (bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) { 8596 if (bp->hwrm_spec_code >= 0x10201) 8597 req->auto_pause = 8598 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE; 8599 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX) 8600 req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX; 8601 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX) 8602 req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_TX; 8603 req->enables |= 8604 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE); 8605 } else { 8606 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX) 8607 req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_RX; 8608 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX) 8609 req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_TX; 8610 req->enables |= 8611 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE); 8612 if (bp->hwrm_spec_code >= 0x10201) { 8613 req->auto_pause = req->force_pause; 8614 req->enables |= cpu_to_le32( 8615 PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE); 8616 } 8617 } 8618 } 8619 8620 static void bnxt_hwrm_set_link_common(struct bnxt *bp, 8621 struct hwrm_port_phy_cfg_input *req) 8622 { 8623 u8 autoneg = bp->link_info.autoneg; 8624 u16 fw_link_speed = bp->link_info.req_link_speed; 8625 u16 advertising = bp->link_info.advertising; 8626 8627 if (autoneg & BNXT_AUTONEG_SPEED) { 8628 req->auto_mode |= 8629 PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK; 8630 8631 req->enables |= cpu_to_le32( 8632 PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK); 8633 req->auto_link_speed_mask = cpu_to_le16(advertising); 8634 8635 req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE); 8636 req->flags |= 8637 cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG); 8638 } else { 8639 req->force_link_speed = cpu_to_le16(fw_link_speed); 8640 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE); 8641 } 8642 8643 /* tell chimp that the setting takes effect immediately */ 8644 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESET_PHY); 8645 } 8646 8647 int bnxt_hwrm_set_pause(struct bnxt *bp) 8648 { 8649 struct hwrm_port_phy_cfg_input req = {0}; 8650 int rc; 8651 8652 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1); 8653 bnxt_hwrm_set_pause_common(bp, &req); 8654 8655 if ((bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) || 8656 bp->link_info.force_link_chng) 8657 bnxt_hwrm_set_link_common(bp, &req); 8658 8659 mutex_lock(&bp->hwrm_cmd_lock); 8660 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 8661 if (!rc && !(bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL)) { 8662 /* since changing of pause setting doesn't trigger any link 8663 * change event, the driver needs to update the current pause 8664 * result upon successfully return of the phy_cfg command 8665 */ 8666 bp->link_info.pause = 8667 bp->link_info.force_pause_setting = bp->link_info.req_flow_ctrl; 8668 bp->link_info.auto_pause_setting = 0; 8669 if (!bp->link_info.force_link_chng) 8670 bnxt_report_link(bp); 8671 } 8672 bp->link_info.force_link_chng = false; 8673 mutex_unlock(&bp->hwrm_cmd_lock); 8674 return rc; 8675 } 8676 8677 static void bnxt_hwrm_set_eee(struct bnxt *bp, 8678 struct hwrm_port_phy_cfg_input *req) 8679 { 8680 struct ethtool_eee *eee = &bp->eee; 8681 8682 if (eee->eee_enabled) { 8683 u16 eee_speeds; 8684 u32 flags = PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE; 8685 8686 if (eee->tx_lpi_enabled) 8687 flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE; 8688 else 8689 flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE; 8690 8691 req->flags |= cpu_to_le32(flags); 8692 eee_speeds = bnxt_get_fw_auto_link_speeds(eee->advertised); 8693 req->eee_link_speed_mask = cpu_to_le16(eee_speeds); 8694 req->tx_lpi_timer = cpu_to_le32(eee->tx_lpi_timer); 8695 } else { 8696 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE); 8697 } 8698 } 8699 8700 int bnxt_hwrm_set_link_setting(struct bnxt *bp, bool set_pause, bool set_eee) 8701 { 8702 struct hwrm_port_phy_cfg_input req = {0}; 8703 8704 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1); 8705 if (set_pause) 8706 bnxt_hwrm_set_pause_common(bp, &req); 8707 8708 bnxt_hwrm_set_link_common(bp, &req); 8709 8710 if (set_eee) 8711 bnxt_hwrm_set_eee(bp, &req); 8712 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 8713 } 8714 8715 static int bnxt_hwrm_shutdown_link(struct bnxt *bp) 8716 { 8717 struct hwrm_port_phy_cfg_input req = {0}; 8718 8719 if (!BNXT_SINGLE_PF(bp)) 8720 return 0; 8721 8722 if (pci_num_vf(bp->pdev)) 8723 return 0; 8724 8725 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1); 8726 req.flags = cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN); 8727 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 8728 } 8729 8730 static int bnxt_fw_init_one(struct bnxt *bp); 8731 8732 static int bnxt_hwrm_if_change(struct bnxt *bp, bool up) 8733 { 8734 struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr; 8735 struct hwrm_func_drv_if_change_input req = {0}; 8736 bool resc_reinit = false, fw_reset = false; 8737 u32 flags = 0; 8738 int rc; 8739 8740 if (!(bp->fw_cap & BNXT_FW_CAP_IF_CHANGE)) 8741 return 0; 8742 8743 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_IF_CHANGE, -1, -1); 8744 if (up) 8745 req.flags = cpu_to_le32(FUNC_DRV_IF_CHANGE_REQ_FLAGS_UP); 8746 mutex_lock(&bp->hwrm_cmd_lock); 8747 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 8748 if (!rc) 8749 flags = le32_to_cpu(resp->flags); 8750 mutex_unlock(&bp->hwrm_cmd_lock); 8751 if (rc) 8752 return rc; 8753 8754 if (!up) 8755 return 0; 8756 8757 if (flags & FUNC_DRV_IF_CHANGE_RESP_FLAGS_RESC_CHANGE) 8758 resc_reinit = true; 8759 if (flags & FUNC_DRV_IF_CHANGE_RESP_FLAGS_HOT_FW_RESET_DONE) 8760 fw_reset = true; 8761 8762 if (test_bit(BNXT_STATE_IN_FW_RESET, &bp->state) && !fw_reset) { 8763 netdev_err(bp->dev, "RESET_DONE not set during FW reset.\n"); 8764 return -ENODEV; 8765 } 8766 if (resc_reinit || fw_reset) { 8767 if (fw_reset) { 8768 if (!test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) 8769 bnxt_ulp_stop(bp); 8770 bnxt_free_ctx_mem(bp); 8771 kfree(bp->ctx); 8772 bp->ctx = NULL; 8773 bnxt_dcb_free(bp); 8774 rc = bnxt_fw_init_one(bp); 8775 if (rc) { 8776 set_bit(BNXT_STATE_ABORT_ERR, &bp->state); 8777 return rc; 8778 } 8779 bnxt_clear_int_mode(bp); 8780 rc = bnxt_init_int_mode(bp); 8781 if (rc) { 8782 netdev_err(bp->dev, "init int mode failed\n"); 8783 return rc; 8784 } 8785 set_bit(BNXT_STATE_FW_RESET_DET, &bp->state); 8786 } 8787 if (BNXT_NEW_RM(bp)) { 8788 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 8789 8790 rc = bnxt_hwrm_func_resc_qcaps(bp, true); 8791 hw_resc->resv_cp_rings = 0; 8792 hw_resc->resv_stat_ctxs = 0; 8793 hw_resc->resv_irqs = 0; 8794 hw_resc->resv_tx_rings = 0; 8795 hw_resc->resv_rx_rings = 0; 8796 hw_resc->resv_hw_ring_grps = 0; 8797 hw_resc->resv_vnics = 0; 8798 if (!fw_reset) { 8799 bp->tx_nr_rings = 0; 8800 bp->rx_nr_rings = 0; 8801 } 8802 } 8803 } 8804 return 0; 8805 } 8806 8807 static int bnxt_hwrm_port_led_qcaps(struct bnxt *bp) 8808 { 8809 struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr; 8810 struct hwrm_port_led_qcaps_input req = {0}; 8811 struct bnxt_pf_info *pf = &bp->pf; 8812 int rc; 8813 8814 bp->num_leds = 0; 8815 if (BNXT_VF(bp) || bp->hwrm_spec_code < 0x10601) 8816 return 0; 8817 8818 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_LED_QCAPS, -1, -1); 8819 req.port_id = cpu_to_le16(pf->port_id); 8820 mutex_lock(&bp->hwrm_cmd_lock); 8821 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 8822 if (rc) { 8823 mutex_unlock(&bp->hwrm_cmd_lock); 8824 return rc; 8825 } 8826 if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) { 8827 int i; 8828 8829 bp->num_leds = resp->num_leds; 8830 memcpy(bp->leds, &resp->led0_id, sizeof(bp->leds[0]) * 8831 bp->num_leds); 8832 for (i = 0; i < bp->num_leds; i++) { 8833 struct bnxt_led_info *led = &bp->leds[i]; 8834 __le16 caps = led->led_state_caps; 8835 8836 if (!led->led_group_id || 8837 !BNXT_LED_ALT_BLINK_CAP(caps)) { 8838 bp->num_leds = 0; 8839 break; 8840 } 8841 } 8842 } 8843 mutex_unlock(&bp->hwrm_cmd_lock); 8844 return 0; 8845 } 8846 8847 int bnxt_hwrm_alloc_wol_fltr(struct bnxt *bp) 8848 { 8849 struct hwrm_wol_filter_alloc_input req = {0}; 8850 struct hwrm_wol_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr; 8851 int rc; 8852 8853 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_ALLOC, -1, -1); 8854 req.port_id = cpu_to_le16(bp->pf.port_id); 8855 req.wol_type = WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT; 8856 req.enables = cpu_to_le32(WOL_FILTER_ALLOC_REQ_ENABLES_MAC_ADDRESS); 8857 memcpy(req.mac_address, bp->dev->dev_addr, ETH_ALEN); 8858 mutex_lock(&bp->hwrm_cmd_lock); 8859 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 8860 if (!rc) 8861 bp->wol_filter_id = resp->wol_filter_id; 8862 mutex_unlock(&bp->hwrm_cmd_lock); 8863 return rc; 8864 } 8865 8866 int bnxt_hwrm_free_wol_fltr(struct bnxt *bp) 8867 { 8868 struct hwrm_wol_filter_free_input req = {0}; 8869 8870 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_FREE, -1, -1); 8871 req.port_id = cpu_to_le16(bp->pf.port_id); 8872 req.enables = cpu_to_le32(WOL_FILTER_FREE_REQ_ENABLES_WOL_FILTER_ID); 8873 req.wol_filter_id = bp->wol_filter_id; 8874 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 8875 } 8876 8877 static u16 bnxt_hwrm_get_wol_fltrs(struct bnxt *bp, u16 handle) 8878 { 8879 struct hwrm_wol_filter_qcfg_input req = {0}; 8880 struct hwrm_wol_filter_qcfg_output *resp = bp->hwrm_cmd_resp_addr; 8881 u16 next_handle = 0; 8882 int rc; 8883 8884 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_QCFG, -1, -1); 8885 req.port_id = cpu_to_le16(bp->pf.port_id); 8886 req.handle = cpu_to_le16(handle); 8887 mutex_lock(&bp->hwrm_cmd_lock); 8888 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 8889 if (!rc) { 8890 next_handle = le16_to_cpu(resp->next_handle); 8891 if (next_handle != 0) { 8892 if (resp->wol_type == 8893 WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT) { 8894 bp->wol = 1; 8895 bp->wol_filter_id = resp->wol_filter_id; 8896 } 8897 } 8898 } 8899 mutex_unlock(&bp->hwrm_cmd_lock); 8900 return next_handle; 8901 } 8902 8903 static void bnxt_get_wol_settings(struct bnxt *bp) 8904 { 8905 u16 handle = 0; 8906 8907 bp->wol = 0; 8908 if (!BNXT_PF(bp) || !(bp->flags & BNXT_FLAG_WOL_CAP)) 8909 return; 8910 8911 do { 8912 handle = bnxt_hwrm_get_wol_fltrs(bp, handle); 8913 } while (handle && handle != 0xffff); 8914 } 8915 8916 #ifdef CONFIG_BNXT_HWMON 8917 static ssize_t bnxt_show_temp(struct device *dev, 8918 struct device_attribute *devattr, char *buf) 8919 { 8920 struct hwrm_temp_monitor_query_input req = {0}; 8921 struct hwrm_temp_monitor_query_output *resp; 8922 struct bnxt *bp = dev_get_drvdata(dev); 8923 u32 temp = 0; 8924 8925 resp = bp->hwrm_cmd_resp_addr; 8926 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TEMP_MONITOR_QUERY, -1, -1); 8927 mutex_lock(&bp->hwrm_cmd_lock); 8928 if (!_hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT)) 8929 temp = resp->temp * 1000; /* display millidegree */ 8930 mutex_unlock(&bp->hwrm_cmd_lock); 8931 8932 return sprintf(buf, "%u\n", temp); 8933 } 8934 static SENSOR_DEVICE_ATTR(temp1_input, 0444, bnxt_show_temp, NULL, 0); 8935 8936 static struct attribute *bnxt_attrs[] = { 8937 &sensor_dev_attr_temp1_input.dev_attr.attr, 8938 NULL 8939 }; 8940 ATTRIBUTE_GROUPS(bnxt); 8941 8942 static void bnxt_hwmon_close(struct bnxt *bp) 8943 { 8944 if (bp->hwmon_dev) { 8945 hwmon_device_unregister(bp->hwmon_dev); 8946 bp->hwmon_dev = NULL; 8947 } 8948 } 8949 8950 static void bnxt_hwmon_open(struct bnxt *bp) 8951 { 8952 struct pci_dev *pdev = bp->pdev; 8953 8954 if (bp->hwmon_dev) 8955 return; 8956 8957 bp->hwmon_dev = hwmon_device_register_with_groups(&pdev->dev, 8958 DRV_MODULE_NAME, bp, 8959 bnxt_groups); 8960 if (IS_ERR(bp->hwmon_dev)) { 8961 bp->hwmon_dev = NULL; 8962 dev_warn(&pdev->dev, "Cannot register hwmon device\n"); 8963 } 8964 } 8965 #else 8966 static void bnxt_hwmon_close(struct bnxt *bp) 8967 { 8968 } 8969 8970 static void bnxt_hwmon_open(struct bnxt *bp) 8971 { 8972 } 8973 #endif 8974 8975 static bool bnxt_eee_config_ok(struct bnxt *bp) 8976 { 8977 struct ethtool_eee *eee = &bp->eee; 8978 struct bnxt_link_info *link_info = &bp->link_info; 8979 8980 if (!(bp->flags & BNXT_FLAG_EEE_CAP)) 8981 return true; 8982 8983 if (eee->eee_enabled) { 8984 u32 advertising = 8985 _bnxt_fw_to_ethtool_adv_spds(link_info->advertising, 0); 8986 8987 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) { 8988 eee->eee_enabled = 0; 8989 return false; 8990 } 8991 if (eee->advertised & ~advertising) { 8992 eee->advertised = advertising & eee->supported; 8993 return false; 8994 } 8995 } 8996 return true; 8997 } 8998 8999 static int bnxt_update_phy_setting(struct bnxt *bp) 9000 { 9001 int rc; 9002 bool update_link = false; 9003 bool update_pause = false; 9004 bool update_eee = false; 9005 struct bnxt_link_info *link_info = &bp->link_info; 9006 9007 rc = bnxt_update_link(bp, true); 9008 if (rc) { 9009 netdev_err(bp->dev, "failed to update link (rc: %x)\n", 9010 rc); 9011 return rc; 9012 } 9013 if (!BNXT_SINGLE_PF(bp)) 9014 return 0; 9015 9016 if ((link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) && 9017 (link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH) != 9018 link_info->req_flow_ctrl) 9019 update_pause = true; 9020 if (!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) && 9021 link_info->force_pause_setting != link_info->req_flow_ctrl) 9022 update_pause = true; 9023 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) { 9024 if (BNXT_AUTO_MODE(link_info->auto_mode)) 9025 update_link = true; 9026 if (link_info->req_link_speed != link_info->force_link_speed) 9027 update_link = true; 9028 if (link_info->req_duplex != link_info->duplex_setting) 9029 update_link = true; 9030 } else { 9031 if (link_info->auto_mode == BNXT_LINK_AUTO_NONE) 9032 update_link = true; 9033 if (link_info->advertising != link_info->auto_link_speeds) 9034 update_link = true; 9035 } 9036 9037 /* The last close may have shutdown the link, so need to call 9038 * PHY_CFG to bring it back up. 9039 */ 9040 if (!bp->link_info.link_up) 9041 update_link = true; 9042 9043 if (!bnxt_eee_config_ok(bp)) 9044 update_eee = true; 9045 9046 if (update_link) 9047 rc = bnxt_hwrm_set_link_setting(bp, update_pause, update_eee); 9048 else if (update_pause) 9049 rc = bnxt_hwrm_set_pause(bp); 9050 if (rc) { 9051 netdev_err(bp->dev, "failed to update phy setting (rc: %x)\n", 9052 rc); 9053 return rc; 9054 } 9055 9056 return rc; 9057 } 9058 9059 /* Common routine to pre-map certain register block to different GRC window. 9060 * A PF has 16 4K windows and a VF has 4 4K windows. However, only 15 windows 9061 * in PF and 3 windows in VF that can be customized to map in different 9062 * register blocks. 9063 */ 9064 static void bnxt_preset_reg_win(struct bnxt *bp) 9065 { 9066 if (BNXT_PF(bp)) { 9067 /* CAG registers map to GRC window #4 */ 9068 writel(BNXT_CAG_REG_BASE, 9069 bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 12); 9070 } 9071 } 9072 9073 static int bnxt_init_dflt_ring_mode(struct bnxt *bp); 9074 9075 static int __bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init) 9076 { 9077 int rc = 0; 9078 9079 bnxt_preset_reg_win(bp); 9080 netif_carrier_off(bp->dev); 9081 if (irq_re_init) { 9082 /* Reserve rings now if none were reserved at driver probe. */ 9083 rc = bnxt_init_dflt_ring_mode(bp); 9084 if (rc) { 9085 netdev_err(bp->dev, "Failed to reserve default rings at open\n"); 9086 return rc; 9087 } 9088 } 9089 rc = bnxt_reserve_rings(bp, irq_re_init); 9090 if (rc) 9091 return rc; 9092 if ((bp->flags & BNXT_FLAG_RFS) && 9093 !(bp->flags & BNXT_FLAG_USING_MSIX)) { 9094 /* disable RFS if falling back to INTA */ 9095 bp->dev->hw_features &= ~NETIF_F_NTUPLE; 9096 bp->flags &= ~BNXT_FLAG_RFS; 9097 } 9098 9099 rc = bnxt_alloc_mem(bp, irq_re_init); 9100 if (rc) { 9101 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc); 9102 goto open_err_free_mem; 9103 } 9104 9105 if (irq_re_init) { 9106 bnxt_init_napi(bp); 9107 rc = bnxt_request_irq(bp); 9108 if (rc) { 9109 netdev_err(bp->dev, "bnxt_request_irq err: %x\n", rc); 9110 goto open_err_irq; 9111 } 9112 } 9113 9114 bnxt_enable_napi(bp); 9115 bnxt_debug_dev_init(bp); 9116 9117 rc = bnxt_init_nic(bp, irq_re_init); 9118 if (rc) { 9119 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc); 9120 goto open_err; 9121 } 9122 9123 if (link_re_init) { 9124 mutex_lock(&bp->link_lock); 9125 rc = bnxt_update_phy_setting(bp); 9126 mutex_unlock(&bp->link_lock); 9127 if (rc) { 9128 netdev_warn(bp->dev, "failed to update phy settings\n"); 9129 if (BNXT_SINGLE_PF(bp)) { 9130 bp->link_info.phy_retry = true; 9131 bp->link_info.phy_retry_expires = 9132 jiffies + 5 * HZ; 9133 } 9134 } 9135 } 9136 9137 if (irq_re_init) 9138 udp_tunnel_get_rx_info(bp->dev); 9139 9140 set_bit(BNXT_STATE_OPEN, &bp->state); 9141 bnxt_enable_int(bp); 9142 /* Enable TX queues */ 9143 bnxt_tx_enable(bp); 9144 mod_timer(&bp->timer, jiffies + bp->current_interval); 9145 /* Poll link status and check for SFP+ module status */ 9146 bnxt_get_port_module_status(bp); 9147 9148 /* VF-reps may need to be re-opened after the PF is re-opened */ 9149 if (BNXT_PF(bp)) 9150 bnxt_vf_reps_open(bp); 9151 return 0; 9152 9153 open_err: 9154 bnxt_debug_dev_exit(bp); 9155 bnxt_disable_napi(bp); 9156 9157 open_err_irq: 9158 bnxt_del_napi(bp); 9159 9160 open_err_free_mem: 9161 bnxt_free_skbs(bp); 9162 bnxt_free_irq(bp); 9163 bnxt_free_mem(bp, true); 9164 return rc; 9165 } 9166 9167 /* rtnl_lock held */ 9168 int bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init) 9169 { 9170 int rc = 0; 9171 9172 rc = __bnxt_open_nic(bp, irq_re_init, link_re_init); 9173 if (rc) { 9174 netdev_err(bp->dev, "nic open fail (rc: %x)\n", rc); 9175 dev_close(bp->dev); 9176 } 9177 return rc; 9178 } 9179 9180 /* rtnl_lock held, open the NIC half way by allocating all resources, but 9181 * NAPI, IRQ, and TX are not enabled. This is mainly used for offline 9182 * self tests. 9183 */ 9184 int bnxt_half_open_nic(struct bnxt *bp) 9185 { 9186 int rc = 0; 9187 9188 rc = bnxt_alloc_mem(bp, false); 9189 if (rc) { 9190 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc); 9191 goto half_open_err; 9192 } 9193 rc = bnxt_init_nic(bp, false); 9194 if (rc) { 9195 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc); 9196 goto half_open_err; 9197 } 9198 return 0; 9199 9200 half_open_err: 9201 bnxt_free_skbs(bp); 9202 bnxt_free_mem(bp, false); 9203 dev_close(bp->dev); 9204 return rc; 9205 } 9206 9207 /* rtnl_lock held, this call can only be made after a previous successful 9208 * call to bnxt_half_open_nic(). 9209 */ 9210 void bnxt_half_close_nic(struct bnxt *bp) 9211 { 9212 bnxt_hwrm_resource_free(bp, false, false); 9213 bnxt_free_skbs(bp); 9214 bnxt_free_mem(bp, false); 9215 } 9216 9217 static void bnxt_reenable_sriov(struct bnxt *bp) 9218 { 9219 if (BNXT_PF(bp)) { 9220 struct bnxt_pf_info *pf = &bp->pf; 9221 int n = pf->active_vfs; 9222 9223 if (n) 9224 bnxt_cfg_hw_sriov(bp, &n, true); 9225 } 9226 } 9227 9228 static int bnxt_open(struct net_device *dev) 9229 { 9230 struct bnxt *bp = netdev_priv(dev); 9231 int rc; 9232 9233 if (test_bit(BNXT_STATE_ABORT_ERR, &bp->state)) { 9234 netdev_err(bp->dev, "A previous firmware reset did not complete, aborting\n"); 9235 return -ENODEV; 9236 } 9237 9238 rc = bnxt_hwrm_if_change(bp, true); 9239 if (rc) 9240 return rc; 9241 rc = __bnxt_open_nic(bp, true, true); 9242 if (rc) { 9243 bnxt_hwrm_if_change(bp, false); 9244 } else { 9245 if (test_and_clear_bit(BNXT_STATE_FW_RESET_DET, &bp->state)) { 9246 if (!test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) { 9247 bnxt_ulp_start(bp, 0); 9248 bnxt_reenable_sriov(bp); 9249 } 9250 } 9251 bnxt_hwmon_open(bp); 9252 } 9253 9254 return rc; 9255 } 9256 9257 static bool bnxt_drv_busy(struct bnxt *bp) 9258 { 9259 return (test_bit(BNXT_STATE_IN_SP_TASK, &bp->state) || 9260 test_bit(BNXT_STATE_READ_STATS, &bp->state)); 9261 } 9262 9263 static void bnxt_get_ring_stats(struct bnxt *bp, 9264 struct rtnl_link_stats64 *stats); 9265 9266 static void __bnxt_close_nic(struct bnxt *bp, bool irq_re_init, 9267 bool link_re_init) 9268 { 9269 /* Close the VF-reps before closing PF */ 9270 if (BNXT_PF(bp)) 9271 bnxt_vf_reps_close(bp); 9272 9273 /* Change device state to avoid TX queue wake up's */ 9274 bnxt_tx_disable(bp); 9275 9276 clear_bit(BNXT_STATE_OPEN, &bp->state); 9277 smp_mb__after_atomic(); 9278 while (bnxt_drv_busy(bp)) 9279 msleep(20); 9280 9281 /* Flush rings and and disable interrupts */ 9282 bnxt_shutdown_nic(bp, irq_re_init); 9283 9284 /* TODO CHIMP_FW: Link/PHY related cleanup if (link_re_init) */ 9285 9286 bnxt_debug_dev_exit(bp); 9287 bnxt_disable_napi(bp); 9288 del_timer_sync(&bp->timer); 9289 bnxt_free_skbs(bp); 9290 9291 /* Save ring stats before shutdown */ 9292 if (bp->bnapi) 9293 bnxt_get_ring_stats(bp, &bp->net_stats_prev); 9294 if (irq_re_init) { 9295 bnxt_free_irq(bp); 9296 bnxt_del_napi(bp); 9297 } 9298 bnxt_free_mem(bp, irq_re_init); 9299 } 9300 9301 int bnxt_close_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init) 9302 { 9303 int rc = 0; 9304 9305 if (test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) { 9306 /* If we get here, it means firmware reset is in progress 9307 * while we are trying to close. We can safely proceed with 9308 * the close because we are holding rtnl_lock(). Some firmware 9309 * messages may fail as we proceed to close. We set the 9310 * ABORT_ERR flag here so that the FW reset thread will later 9311 * abort when it gets the rtnl_lock() and sees the flag. 9312 */ 9313 netdev_warn(bp->dev, "FW reset in progress during close, FW reset will be aborted\n"); 9314 set_bit(BNXT_STATE_ABORT_ERR, &bp->state); 9315 } 9316 9317 #ifdef CONFIG_BNXT_SRIOV 9318 if (bp->sriov_cfg) { 9319 rc = wait_event_interruptible_timeout(bp->sriov_cfg_wait, 9320 !bp->sriov_cfg, 9321 BNXT_SRIOV_CFG_WAIT_TMO); 9322 if (rc) 9323 netdev_warn(bp->dev, "timeout waiting for SRIOV config operation to complete!\n"); 9324 } 9325 #endif 9326 __bnxt_close_nic(bp, irq_re_init, link_re_init); 9327 return rc; 9328 } 9329 9330 static int bnxt_close(struct net_device *dev) 9331 { 9332 struct bnxt *bp = netdev_priv(dev); 9333 9334 bnxt_hwmon_close(bp); 9335 bnxt_close_nic(bp, true, true); 9336 bnxt_hwrm_shutdown_link(bp); 9337 bnxt_hwrm_if_change(bp, false); 9338 return 0; 9339 } 9340 9341 static int bnxt_hwrm_port_phy_read(struct bnxt *bp, u16 phy_addr, u16 reg, 9342 u16 *val) 9343 { 9344 struct hwrm_port_phy_mdio_read_output *resp = bp->hwrm_cmd_resp_addr; 9345 struct hwrm_port_phy_mdio_read_input req = {0}; 9346 int rc; 9347 9348 if (bp->hwrm_spec_code < 0x10a00) 9349 return -EOPNOTSUPP; 9350 9351 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_MDIO_READ, -1, -1); 9352 req.port_id = cpu_to_le16(bp->pf.port_id); 9353 req.phy_addr = phy_addr; 9354 req.reg_addr = cpu_to_le16(reg & 0x1f); 9355 if (mdio_phy_id_is_c45(phy_addr)) { 9356 req.cl45_mdio = 1; 9357 req.phy_addr = mdio_phy_id_prtad(phy_addr); 9358 req.dev_addr = mdio_phy_id_devad(phy_addr); 9359 req.reg_addr = cpu_to_le16(reg); 9360 } 9361 9362 mutex_lock(&bp->hwrm_cmd_lock); 9363 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 9364 if (!rc) 9365 *val = le16_to_cpu(resp->reg_data); 9366 mutex_unlock(&bp->hwrm_cmd_lock); 9367 return rc; 9368 } 9369 9370 static int bnxt_hwrm_port_phy_write(struct bnxt *bp, u16 phy_addr, u16 reg, 9371 u16 val) 9372 { 9373 struct hwrm_port_phy_mdio_write_input req = {0}; 9374 9375 if (bp->hwrm_spec_code < 0x10a00) 9376 return -EOPNOTSUPP; 9377 9378 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_MDIO_WRITE, -1, -1); 9379 req.port_id = cpu_to_le16(bp->pf.port_id); 9380 req.phy_addr = phy_addr; 9381 req.reg_addr = cpu_to_le16(reg & 0x1f); 9382 if (mdio_phy_id_is_c45(phy_addr)) { 9383 req.cl45_mdio = 1; 9384 req.phy_addr = mdio_phy_id_prtad(phy_addr); 9385 req.dev_addr = mdio_phy_id_devad(phy_addr); 9386 req.reg_addr = cpu_to_le16(reg); 9387 } 9388 req.reg_data = cpu_to_le16(val); 9389 9390 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 9391 } 9392 9393 /* rtnl_lock held */ 9394 static int bnxt_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 9395 { 9396 struct mii_ioctl_data *mdio = if_mii(ifr); 9397 struct bnxt *bp = netdev_priv(dev); 9398 int rc; 9399 9400 switch (cmd) { 9401 case SIOCGMIIPHY: 9402 mdio->phy_id = bp->link_info.phy_addr; 9403 9404 /* fallthru */ 9405 case SIOCGMIIREG: { 9406 u16 mii_regval = 0; 9407 9408 if (!netif_running(dev)) 9409 return -EAGAIN; 9410 9411 rc = bnxt_hwrm_port_phy_read(bp, mdio->phy_id, mdio->reg_num, 9412 &mii_regval); 9413 mdio->val_out = mii_regval; 9414 return rc; 9415 } 9416 9417 case SIOCSMIIREG: 9418 if (!netif_running(dev)) 9419 return -EAGAIN; 9420 9421 return bnxt_hwrm_port_phy_write(bp, mdio->phy_id, mdio->reg_num, 9422 mdio->val_in); 9423 9424 default: 9425 /* do nothing */ 9426 break; 9427 } 9428 return -EOPNOTSUPP; 9429 } 9430 9431 static void bnxt_get_ring_stats(struct bnxt *bp, 9432 struct rtnl_link_stats64 *stats) 9433 { 9434 int i; 9435 9436 9437 for (i = 0; i < bp->cp_nr_rings; i++) { 9438 struct bnxt_napi *bnapi = bp->bnapi[i]; 9439 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 9440 struct ctx_hw_stats *hw_stats = cpr->hw_stats; 9441 9442 stats->rx_packets += le64_to_cpu(hw_stats->rx_ucast_pkts); 9443 stats->rx_packets += le64_to_cpu(hw_stats->rx_mcast_pkts); 9444 stats->rx_packets += le64_to_cpu(hw_stats->rx_bcast_pkts); 9445 9446 stats->tx_packets += le64_to_cpu(hw_stats->tx_ucast_pkts); 9447 stats->tx_packets += le64_to_cpu(hw_stats->tx_mcast_pkts); 9448 stats->tx_packets += le64_to_cpu(hw_stats->tx_bcast_pkts); 9449 9450 stats->rx_bytes += le64_to_cpu(hw_stats->rx_ucast_bytes); 9451 stats->rx_bytes += le64_to_cpu(hw_stats->rx_mcast_bytes); 9452 stats->rx_bytes += le64_to_cpu(hw_stats->rx_bcast_bytes); 9453 9454 stats->tx_bytes += le64_to_cpu(hw_stats->tx_ucast_bytes); 9455 stats->tx_bytes += le64_to_cpu(hw_stats->tx_mcast_bytes); 9456 stats->tx_bytes += le64_to_cpu(hw_stats->tx_bcast_bytes); 9457 9458 stats->rx_missed_errors += 9459 le64_to_cpu(hw_stats->rx_discard_pkts); 9460 9461 stats->multicast += le64_to_cpu(hw_stats->rx_mcast_pkts); 9462 9463 stats->tx_dropped += le64_to_cpu(hw_stats->tx_drop_pkts); 9464 } 9465 } 9466 9467 static void bnxt_add_prev_stats(struct bnxt *bp, 9468 struct rtnl_link_stats64 *stats) 9469 { 9470 struct rtnl_link_stats64 *prev_stats = &bp->net_stats_prev; 9471 9472 stats->rx_packets += prev_stats->rx_packets; 9473 stats->tx_packets += prev_stats->tx_packets; 9474 stats->rx_bytes += prev_stats->rx_bytes; 9475 stats->tx_bytes += prev_stats->tx_bytes; 9476 stats->rx_missed_errors += prev_stats->rx_missed_errors; 9477 stats->multicast += prev_stats->multicast; 9478 stats->tx_dropped += prev_stats->tx_dropped; 9479 } 9480 9481 static void 9482 bnxt_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) 9483 { 9484 struct bnxt *bp = netdev_priv(dev); 9485 9486 set_bit(BNXT_STATE_READ_STATS, &bp->state); 9487 /* Make sure bnxt_close_nic() sees that we are reading stats before 9488 * we check the BNXT_STATE_OPEN flag. 9489 */ 9490 smp_mb__after_atomic(); 9491 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) { 9492 clear_bit(BNXT_STATE_READ_STATS, &bp->state); 9493 *stats = bp->net_stats_prev; 9494 return; 9495 } 9496 9497 bnxt_get_ring_stats(bp, stats); 9498 bnxt_add_prev_stats(bp, stats); 9499 9500 if (bp->flags & BNXT_FLAG_PORT_STATS) { 9501 struct rx_port_stats *rx = bp->hw_rx_port_stats; 9502 struct tx_port_stats *tx = bp->hw_tx_port_stats; 9503 9504 stats->rx_crc_errors = le64_to_cpu(rx->rx_fcs_err_frames); 9505 stats->rx_frame_errors = le64_to_cpu(rx->rx_align_err_frames); 9506 stats->rx_length_errors = le64_to_cpu(rx->rx_undrsz_frames) + 9507 le64_to_cpu(rx->rx_ovrsz_frames) + 9508 le64_to_cpu(rx->rx_runt_frames); 9509 stats->rx_errors = le64_to_cpu(rx->rx_false_carrier_frames) + 9510 le64_to_cpu(rx->rx_jbr_frames); 9511 stats->collisions = le64_to_cpu(tx->tx_total_collisions); 9512 stats->tx_fifo_errors = le64_to_cpu(tx->tx_fifo_underruns); 9513 stats->tx_errors = le64_to_cpu(tx->tx_err); 9514 } 9515 clear_bit(BNXT_STATE_READ_STATS, &bp->state); 9516 } 9517 9518 static bool bnxt_mc_list_updated(struct bnxt *bp, u32 *rx_mask) 9519 { 9520 struct net_device *dev = bp->dev; 9521 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 9522 struct netdev_hw_addr *ha; 9523 u8 *haddr; 9524 int mc_count = 0; 9525 bool update = false; 9526 int off = 0; 9527 9528 netdev_for_each_mc_addr(ha, dev) { 9529 if (mc_count >= BNXT_MAX_MC_ADDRS) { 9530 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST; 9531 vnic->mc_list_count = 0; 9532 return false; 9533 } 9534 haddr = ha->addr; 9535 if (!ether_addr_equal(haddr, vnic->mc_list + off)) { 9536 memcpy(vnic->mc_list + off, haddr, ETH_ALEN); 9537 update = true; 9538 } 9539 off += ETH_ALEN; 9540 mc_count++; 9541 } 9542 if (mc_count) 9543 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_MCAST; 9544 9545 if (mc_count != vnic->mc_list_count) { 9546 vnic->mc_list_count = mc_count; 9547 update = true; 9548 } 9549 return update; 9550 } 9551 9552 static bool bnxt_uc_list_updated(struct bnxt *bp) 9553 { 9554 struct net_device *dev = bp->dev; 9555 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 9556 struct netdev_hw_addr *ha; 9557 int off = 0; 9558 9559 if (netdev_uc_count(dev) != (vnic->uc_filter_count - 1)) 9560 return true; 9561 9562 netdev_for_each_uc_addr(ha, dev) { 9563 if (!ether_addr_equal(ha->addr, vnic->uc_list + off)) 9564 return true; 9565 9566 off += ETH_ALEN; 9567 } 9568 return false; 9569 } 9570 9571 static void bnxt_set_rx_mode(struct net_device *dev) 9572 { 9573 struct bnxt *bp = netdev_priv(dev); 9574 struct bnxt_vnic_info *vnic; 9575 bool mc_update = false; 9576 bool uc_update; 9577 u32 mask; 9578 9579 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) 9580 return; 9581 9582 vnic = &bp->vnic_info[0]; 9583 mask = vnic->rx_mask; 9584 mask &= ~(CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS | 9585 CFA_L2_SET_RX_MASK_REQ_MASK_MCAST | 9586 CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST | 9587 CFA_L2_SET_RX_MASK_REQ_MASK_BCAST); 9588 9589 if ((dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp)) 9590 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS; 9591 9592 uc_update = bnxt_uc_list_updated(bp); 9593 9594 if (dev->flags & IFF_BROADCAST) 9595 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_BCAST; 9596 if (dev->flags & IFF_ALLMULTI) { 9597 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST; 9598 vnic->mc_list_count = 0; 9599 } else { 9600 mc_update = bnxt_mc_list_updated(bp, &mask); 9601 } 9602 9603 if (mask != vnic->rx_mask || uc_update || mc_update) { 9604 vnic->rx_mask = mask; 9605 9606 set_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event); 9607 bnxt_queue_sp_work(bp); 9608 } 9609 } 9610 9611 static int bnxt_cfg_rx_mode(struct bnxt *bp) 9612 { 9613 struct net_device *dev = bp->dev; 9614 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 9615 struct netdev_hw_addr *ha; 9616 int i, off = 0, rc; 9617 bool uc_update; 9618 9619 netif_addr_lock_bh(dev); 9620 uc_update = bnxt_uc_list_updated(bp); 9621 netif_addr_unlock_bh(dev); 9622 9623 if (!uc_update) 9624 goto skip_uc; 9625 9626 mutex_lock(&bp->hwrm_cmd_lock); 9627 for (i = 1; i < vnic->uc_filter_count; i++) { 9628 struct hwrm_cfa_l2_filter_free_input req = {0}; 9629 9630 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_FREE, -1, 9631 -1); 9632 9633 req.l2_filter_id = vnic->fw_l2_filter_id[i]; 9634 9635 rc = _hwrm_send_message(bp, &req, sizeof(req), 9636 HWRM_CMD_TIMEOUT); 9637 } 9638 mutex_unlock(&bp->hwrm_cmd_lock); 9639 9640 vnic->uc_filter_count = 1; 9641 9642 netif_addr_lock_bh(dev); 9643 if (netdev_uc_count(dev) > (BNXT_MAX_UC_ADDRS - 1)) { 9644 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS; 9645 } else { 9646 netdev_for_each_uc_addr(ha, dev) { 9647 memcpy(vnic->uc_list + off, ha->addr, ETH_ALEN); 9648 off += ETH_ALEN; 9649 vnic->uc_filter_count++; 9650 } 9651 } 9652 netif_addr_unlock_bh(dev); 9653 9654 for (i = 1, off = 0; i < vnic->uc_filter_count; i++, off += ETH_ALEN) { 9655 rc = bnxt_hwrm_set_vnic_filter(bp, 0, i, vnic->uc_list + off); 9656 if (rc) { 9657 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n", 9658 rc); 9659 vnic->uc_filter_count = i; 9660 return rc; 9661 } 9662 } 9663 9664 skip_uc: 9665 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0); 9666 if (rc && vnic->mc_list_count) { 9667 netdev_info(bp->dev, "Failed setting MC filters rc: %d, turning on ALL_MCAST mode\n", 9668 rc); 9669 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST; 9670 vnic->mc_list_count = 0; 9671 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0); 9672 } 9673 if (rc) 9674 netdev_err(bp->dev, "HWRM cfa l2 rx mask failure rc: %d\n", 9675 rc); 9676 9677 return rc; 9678 } 9679 9680 static bool bnxt_can_reserve_rings(struct bnxt *bp) 9681 { 9682 #ifdef CONFIG_BNXT_SRIOV 9683 if (BNXT_NEW_RM(bp) && BNXT_VF(bp)) { 9684 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 9685 9686 /* No minimum rings were provisioned by the PF. Don't 9687 * reserve rings by default when device is down. 9688 */ 9689 if (hw_resc->min_tx_rings || hw_resc->resv_tx_rings) 9690 return true; 9691 9692 if (!netif_running(bp->dev)) 9693 return false; 9694 } 9695 #endif 9696 return true; 9697 } 9698 9699 /* If the chip and firmware supports RFS */ 9700 static bool bnxt_rfs_supported(struct bnxt *bp) 9701 { 9702 if (bp->flags & BNXT_FLAG_CHIP_P5) { 9703 if (bp->fw_cap & BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V2) 9704 return true; 9705 return false; 9706 } 9707 if (BNXT_PF(bp) && !BNXT_CHIP_TYPE_NITRO_A0(bp)) 9708 return true; 9709 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP) 9710 return true; 9711 return false; 9712 } 9713 9714 /* If runtime conditions support RFS */ 9715 static bool bnxt_rfs_capable(struct bnxt *bp) 9716 { 9717 #ifdef CONFIG_RFS_ACCEL 9718 int vnics, max_vnics, max_rss_ctxs; 9719 9720 if (bp->flags & BNXT_FLAG_CHIP_P5) 9721 return bnxt_rfs_supported(bp); 9722 if (!(bp->flags & BNXT_FLAG_MSIX_CAP) || !bnxt_can_reserve_rings(bp)) 9723 return false; 9724 9725 vnics = 1 + bp->rx_nr_rings; 9726 max_vnics = bnxt_get_max_func_vnics(bp); 9727 max_rss_ctxs = bnxt_get_max_func_rss_ctxs(bp); 9728 9729 /* RSS contexts not a limiting factor */ 9730 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP) 9731 max_rss_ctxs = max_vnics; 9732 if (vnics > max_vnics || vnics > max_rss_ctxs) { 9733 if (bp->rx_nr_rings > 1) 9734 netdev_warn(bp->dev, 9735 "Not enough resources to support NTUPLE filters, enough resources for up to %d rx rings\n", 9736 min(max_rss_ctxs - 1, max_vnics - 1)); 9737 return false; 9738 } 9739 9740 if (!BNXT_NEW_RM(bp)) 9741 return true; 9742 9743 if (vnics == bp->hw_resc.resv_vnics) 9744 return true; 9745 9746 bnxt_hwrm_reserve_rings(bp, 0, 0, 0, 0, 0, vnics); 9747 if (vnics <= bp->hw_resc.resv_vnics) 9748 return true; 9749 9750 netdev_warn(bp->dev, "Unable to reserve resources to support NTUPLE filters.\n"); 9751 bnxt_hwrm_reserve_rings(bp, 0, 0, 0, 0, 0, 1); 9752 return false; 9753 #else 9754 return false; 9755 #endif 9756 } 9757 9758 static netdev_features_t bnxt_fix_features(struct net_device *dev, 9759 netdev_features_t features) 9760 { 9761 struct bnxt *bp = netdev_priv(dev); 9762 9763 if ((features & NETIF_F_NTUPLE) && !bnxt_rfs_capable(bp)) 9764 features &= ~NETIF_F_NTUPLE; 9765 9766 if (bp->flags & BNXT_FLAG_NO_AGG_RINGS) 9767 features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW); 9768 9769 if (!(features & NETIF_F_GRO)) 9770 features &= ~NETIF_F_GRO_HW; 9771 9772 if (features & NETIF_F_GRO_HW) 9773 features &= ~NETIF_F_LRO; 9774 9775 /* Both CTAG and STAG VLAN accelaration on the RX side have to be 9776 * turned on or off together. 9777 */ 9778 if ((features & (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) != 9779 (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) { 9780 if (dev->features & NETIF_F_HW_VLAN_CTAG_RX) 9781 features &= ~(NETIF_F_HW_VLAN_CTAG_RX | 9782 NETIF_F_HW_VLAN_STAG_RX); 9783 else 9784 features |= NETIF_F_HW_VLAN_CTAG_RX | 9785 NETIF_F_HW_VLAN_STAG_RX; 9786 } 9787 #ifdef CONFIG_BNXT_SRIOV 9788 if (BNXT_VF(bp)) { 9789 if (bp->vf.vlan) { 9790 features &= ~(NETIF_F_HW_VLAN_CTAG_RX | 9791 NETIF_F_HW_VLAN_STAG_RX); 9792 } 9793 } 9794 #endif 9795 return features; 9796 } 9797 9798 static int bnxt_set_features(struct net_device *dev, netdev_features_t features) 9799 { 9800 struct bnxt *bp = netdev_priv(dev); 9801 u32 flags = bp->flags; 9802 u32 changes; 9803 int rc = 0; 9804 bool re_init = false; 9805 bool update_tpa = false; 9806 9807 flags &= ~BNXT_FLAG_ALL_CONFIG_FEATS; 9808 if (features & NETIF_F_GRO_HW) 9809 flags |= BNXT_FLAG_GRO; 9810 else if (features & NETIF_F_LRO) 9811 flags |= BNXT_FLAG_LRO; 9812 9813 if (bp->flags & BNXT_FLAG_NO_AGG_RINGS) 9814 flags &= ~BNXT_FLAG_TPA; 9815 9816 if (features & NETIF_F_HW_VLAN_CTAG_RX) 9817 flags |= BNXT_FLAG_STRIP_VLAN; 9818 9819 if (features & NETIF_F_NTUPLE) 9820 flags |= BNXT_FLAG_RFS; 9821 9822 changes = flags ^ bp->flags; 9823 if (changes & BNXT_FLAG_TPA) { 9824 update_tpa = true; 9825 if ((bp->flags & BNXT_FLAG_TPA) == 0 || 9826 (flags & BNXT_FLAG_TPA) == 0 || 9827 (bp->flags & BNXT_FLAG_CHIP_P5)) 9828 re_init = true; 9829 } 9830 9831 if (changes & ~BNXT_FLAG_TPA) 9832 re_init = true; 9833 9834 if (flags != bp->flags) { 9835 u32 old_flags = bp->flags; 9836 9837 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) { 9838 bp->flags = flags; 9839 if (update_tpa) 9840 bnxt_set_ring_params(bp); 9841 return rc; 9842 } 9843 9844 if (re_init) { 9845 bnxt_close_nic(bp, false, false); 9846 bp->flags = flags; 9847 if (update_tpa) 9848 bnxt_set_ring_params(bp); 9849 9850 return bnxt_open_nic(bp, false, false); 9851 } 9852 if (update_tpa) { 9853 bp->flags = flags; 9854 rc = bnxt_set_tpa(bp, 9855 (flags & BNXT_FLAG_TPA) ? 9856 true : false); 9857 if (rc) 9858 bp->flags = old_flags; 9859 } 9860 } 9861 return rc; 9862 } 9863 9864 static int bnxt_dbg_hwrm_ring_info_get(struct bnxt *bp, u8 ring_type, 9865 u32 ring_id, u32 *prod, u32 *cons) 9866 { 9867 struct hwrm_dbg_ring_info_get_output *resp = bp->hwrm_cmd_resp_addr; 9868 struct hwrm_dbg_ring_info_get_input req = {0}; 9869 int rc; 9870 9871 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_DBG_RING_INFO_GET, -1, -1); 9872 req.ring_type = ring_type; 9873 req.fw_ring_id = cpu_to_le32(ring_id); 9874 mutex_lock(&bp->hwrm_cmd_lock); 9875 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 9876 if (!rc) { 9877 *prod = le32_to_cpu(resp->producer_index); 9878 *cons = le32_to_cpu(resp->consumer_index); 9879 } 9880 mutex_unlock(&bp->hwrm_cmd_lock); 9881 return rc; 9882 } 9883 9884 static void bnxt_dump_tx_sw_state(struct bnxt_napi *bnapi) 9885 { 9886 struct bnxt_tx_ring_info *txr = bnapi->tx_ring; 9887 int i = bnapi->index; 9888 9889 if (!txr) 9890 return; 9891 9892 netdev_info(bnapi->bp->dev, "[%d]: tx{fw_ring: %d prod: %x cons: %x}\n", 9893 i, txr->tx_ring_struct.fw_ring_id, txr->tx_prod, 9894 txr->tx_cons); 9895 } 9896 9897 static void bnxt_dump_rx_sw_state(struct bnxt_napi *bnapi) 9898 { 9899 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 9900 int i = bnapi->index; 9901 9902 if (!rxr) 9903 return; 9904 9905 netdev_info(bnapi->bp->dev, "[%d]: rx{fw_ring: %d prod: %x} rx_agg{fw_ring: %d agg_prod: %x sw_agg_prod: %x}\n", 9906 i, rxr->rx_ring_struct.fw_ring_id, rxr->rx_prod, 9907 rxr->rx_agg_ring_struct.fw_ring_id, rxr->rx_agg_prod, 9908 rxr->rx_sw_agg_prod); 9909 } 9910 9911 static void bnxt_dump_cp_sw_state(struct bnxt_napi *bnapi) 9912 { 9913 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 9914 int i = bnapi->index; 9915 9916 netdev_info(bnapi->bp->dev, "[%d]: cp{fw_ring: %d raw_cons: %x}\n", 9917 i, cpr->cp_ring_struct.fw_ring_id, cpr->cp_raw_cons); 9918 } 9919 9920 static void bnxt_dbg_dump_states(struct bnxt *bp) 9921 { 9922 int i; 9923 struct bnxt_napi *bnapi; 9924 9925 for (i = 0; i < bp->cp_nr_rings; i++) { 9926 bnapi = bp->bnapi[i]; 9927 if (netif_msg_drv(bp)) { 9928 bnxt_dump_tx_sw_state(bnapi); 9929 bnxt_dump_rx_sw_state(bnapi); 9930 bnxt_dump_cp_sw_state(bnapi); 9931 } 9932 } 9933 } 9934 9935 static void bnxt_reset_task(struct bnxt *bp, bool silent) 9936 { 9937 if (!silent) 9938 bnxt_dbg_dump_states(bp); 9939 if (netif_running(bp->dev)) { 9940 int rc; 9941 9942 if (silent) { 9943 bnxt_close_nic(bp, false, false); 9944 bnxt_open_nic(bp, false, false); 9945 } else { 9946 bnxt_ulp_stop(bp); 9947 bnxt_close_nic(bp, true, false); 9948 rc = bnxt_open_nic(bp, true, false); 9949 bnxt_ulp_start(bp, rc); 9950 } 9951 } 9952 } 9953 9954 static void bnxt_tx_timeout(struct net_device *dev, unsigned int txqueue) 9955 { 9956 struct bnxt *bp = netdev_priv(dev); 9957 9958 netdev_err(bp->dev, "TX timeout detected, starting reset task!\n"); 9959 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event); 9960 bnxt_queue_sp_work(bp); 9961 } 9962 9963 static void bnxt_fw_health_check(struct bnxt *bp) 9964 { 9965 struct bnxt_fw_health *fw_health = bp->fw_health; 9966 u32 val; 9967 9968 if (!fw_health->enabled || test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) 9969 return; 9970 9971 if (fw_health->tmr_counter) { 9972 fw_health->tmr_counter--; 9973 return; 9974 } 9975 9976 val = bnxt_fw_health_readl(bp, BNXT_FW_HEARTBEAT_REG); 9977 if (val == fw_health->last_fw_heartbeat) 9978 goto fw_reset; 9979 9980 fw_health->last_fw_heartbeat = val; 9981 9982 val = bnxt_fw_health_readl(bp, BNXT_FW_RESET_CNT_REG); 9983 if (val != fw_health->last_fw_reset_cnt) 9984 goto fw_reset; 9985 9986 fw_health->tmr_counter = fw_health->tmr_multiplier; 9987 return; 9988 9989 fw_reset: 9990 set_bit(BNXT_FW_EXCEPTION_SP_EVENT, &bp->sp_event); 9991 bnxt_queue_sp_work(bp); 9992 } 9993 9994 static void bnxt_timer(struct timer_list *t) 9995 { 9996 struct bnxt *bp = from_timer(bp, t, timer); 9997 struct net_device *dev = bp->dev; 9998 9999 if (!netif_running(dev)) 10000 return; 10001 10002 if (atomic_read(&bp->intr_sem) != 0) 10003 goto bnxt_restart_timer; 10004 10005 if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY) 10006 bnxt_fw_health_check(bp); 10007 10008 if (bp->link_info.link_up && (bp->flags & BNXT_FLAG_PORT_STATS) && 10009 bp->stats_coal_ticks) { 10010 set_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event); 10011 bnxt_queue_sp_work(bp); 10012 } 10013 10014 if (bnxt_tc_flower_enabled(bp)) { 10015 set_bit(BNXT_FLOW_STATS_SP_EVENT, &bp->sp_event); 10016 bnxt_queue_sp_work(bp); 10017 } 10018 10019 #ifdef CONFIG_RFS_ACCEL 10020 if ((bp->flags & BNXT_FLAG_RFS) && bp->ntp_fltr_count) { 10021 set_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event); 10022 bnxt_queue_sp_work(bp); 10023 } 10024 #endif /*CONFIG_RFS_ACCEL*/ 10025 10026 if (bp->link_info.phy_retry) { 10027 if (time_after(jiffies, bp->link_info.phy_retry_expires)) { 10028 bp->link_info.phy_retry = false; 10029 netdev_warn(bp->dev, "failed to update phy settings after maximum retries.\n"); 10030 } else { 10031 set_bit(BNXT_UPDATE_PHY_SP_EVENT, &bp->sp_event); 10032 bnxt_queue_sp_work(bp); 10033 } 10034 } 10035 10036 if ((bp->flags & BNXT_FLAG_CHIP_P5) && !bp->chip_rev && 10037 netif_carrier_ok(dev)) { 10038 set_bit(BNXT_RING_COAL_NOW_SP_EVENT, &bp->sp_event); 10039 bnxt_queue_sp_work(bp); 10040 } 10041 bnxt_restart_timer: 10042 mod_timer(&bp->timer, jiffies + bp->current_interval); 10043 } 10044 10045 static void bnxt_rtnl_lock_sp(struct bnxt *bp) 10046 { 10047 /* We are called from bnxt_sp_task which has BNXT_STATE_IN_SP_TASK 10048 * set. If the device is being closed, bnxt_close() may be holding 10049 * rtnl() and waiting for BNXT_STATE_IN_SP_TASK to clear. So we 10050 * must clear BNXT_STATE_IN_SP_TASK before holding rtnl(). 10051 */ 10052 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state); 10053 rtnl_lock(); 10054 } 10055 10056 static void bnxt_rtnl_unlock_sp(struct bnxt *bp) 10057 { 10058 set_bit(BNXT_STATE_IN_SP_TASK, &bp->state); 10059 rtnl_unlock(); 10060 } 10061 10062 /* Only called from bnxt_sp_task() */ 10063 static void bnxt_reset(struct bnxt *bp, bool silent) 10064 { 10065 bnxt_rtnl_lock_sp(bp); 10066 if (test_bit(BNXT_STATE_OPEN, &bp->state)) 10067 bnxt_reset_task(bp, silent); 10068 bnxt_rtnl_unlock_sp(bp); 10069 } 10070 10071 static void bnxt_fw_reset_close(struct bnxt *bp) 10072 { 10073 bnxt_ulp_stop(bp); 10074 /* When firmware is fatal state, disable PCI device to prevent 10075 * any potential bad DMAs before freeing kernel memory. 10076 */ 10077 if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state)) 10078 pci_disable_device(bp->pdev); 10079 __bnxt_close_nic(bp, true, false); 10080 bnxt_clear_int_mode(bp); 10081 bnxt_hwrm_func_drv_unrgtr(bp); 10082 if (pci_is_enabled(bp->pdev)) 10083 pci_disable_device(bp->pdev); 10084 bnxt_free_ctx_mem(bp); 10085 kfree(bp->ctx); 10086 bp->ctx = NULL; 10087 } 10088 10089 static bool is_bnxt_fw_ok(struct bnxt *bp) 10090 { 10091 struct bnxt_fw_health *fw_health = bp->fw_health; 10092 bool no_heartbeat = false, has_reset = false; 10093 u32 val; 10094 10095 val = bnxt_fw_health_readl(bp, BNXT_FW_HEARTBEAT_REG); 10096 if (val == fw_health->last_fw_heartbeat) 10097 no_heartbeat = true; 10098 10099 val = bnxt_fw_health_readl(bp, BNXT_FW_RESET_CNT_REG); 10100 if (val != fw_health->last_fw_reset_cnt) 10101 has_reset = true; 10102 10103 if (!no_heartbeat && has_reset) 10104 return true; 10105 10106 return false; 10107 } 10108 10109 /* rtnl_lock is acquired before calling this function */ 10110 static void bnxt_force_fw_reset(struct bnxt *bp) 10111 { 10112 struct bnxt_fw_health *fw_health = bp->fw_health; 10113 u32 wait_dsecs; 10114 10115 if (!test_bit(BNXT_STATE_OPEN, &bp->state) || 10116 test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) 10117 return; 10118 10119 set_bit(BNXT_STATE_IN_FW_RESET, &bp->state); 10120 bnxt_fw_reset_close(bp); 10121 wait_dsecs = fw_health->master_func_wait_dsecs; 10122 if (fw_health->master) { 10123 if (fw_health->flags & ERROR_RECOVERY_QCFG_RESP_FLAGS_CO_CPU) 10124 wait_dsecs = 0; 10125 bp->fw_reset_state = BNXT_FW_RESET_STATE_RESET_FW; 10126 } else { 10127 bp->fw_reset_timestamp = jiffies + wait_dsecs * HZ / 10; 10128 wait_dsecs = fw_health->normal_func_wait_dsecs; 10129 bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV; 10130 } 10131 10132 bp->fw_reset_min_dsecs = fw_health->post_reset_wait_dsecs; 10133 bp->fw_reset_max_dsecs = fw_health->post_reset_max_wait_dsecs; 10134 bnxt_queue_fw_reset_work(bp, wait_dsecs * HZ / 10); 10135 } 10136 10137 void bnxt_fw_exception(struct bnxt *bp) 10138 { 10139 netdev_warn(bp->dev, "Detected firmware fatal condition, initiating reset\n"); 10140 set_bit(BNXT_STATE_FW_FATAL_COND, &bp->state); 10141 bnxt_rtnl_lock_sp(bp); 10142 bnxt_force_fw_reset(bp); 10143 bnxt_rtnl_unlock_sp(bp); 10144 } 10145 10146 /* Returns the number of registered VFs, or 1 if VF configuration is pending, or 10147 * < 0 on error. 10148 */ 10149 static int bnxt_get_registered_vfs(struct bnxt *bp) 10150 { 10151 #ifdef CONFIG_BNXT_SRIOV 10152 int rc; 10153 10154 if (!BNXT_PF(bp)) 10155 return 0; 10156 10157 rc = bnxt_hwrm_func_qcfg(bp); 10158 if (rc) { 10159 netdev_err(bp->dev, "func_qcfg cmd failed, rc = %d\n", rc); 10160 return rc; 10161 } 10162 if (bp->pf.registered_vfs) 10163 return bp->pf.registered_vfs; 10164 if (bp->sriov_cfg) 10165 return 1; 10166 #endif 10167 return 0; 10168 } 10169 10170 void bnxt_fw_reset(struct bnxt *bp) 10171 { 10172 bnxt_rtnl_lock_sp(bp); 10173 if (test_bit(BNXT_STATE_OPEN, &bp->state) && 10174 !test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) { 10175 int n = 0, tmo; 10176 10177 set_bit(BNXT_STATE_IN_FW_RESET, &bp->state); 10178 if (bp->pf.active_vfs && 10179 !test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state)) 10180 n = bnxt_get_registered_vfs(bp); 10181 if (n < 0) { 10182 netdev_err(bp->dev, "Firmware reset aborted, rc = %d\n", 10183 n); 10184 clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state); 10185 dev_close(bp->dev); 10186 goto fw_reset_exit; 10187 } else if (n > 0) { 10188 u16 vf_tmo_dsecs = n * 10; 10189 10190 if (bp->fw_reset_max_dsecs < vf_tmo_dsecs) 10191 bp->fw_reset_max_dsecs = vf_tmo_dsecs; 10192 bp->fw_reset_state = 10193 BNXT_FW_RESET_STATE_POLL_VF; 10194 bnxt_queue_fw_reset_work(bp, HZ / 10); 10195 goto fw_reset_exit; 10196 } 10197 bnxt_fw_reset_close(bp); 10198 if (bp->fw_cap & BNXT_FW_CAP_ERR_RECOVER_RELOAD) { 10199 bp->fw_reset_state = BNXT_FW_RESET_STATE_POLL_FW_DOWN; 10200 tmo = HZ / 10; 10201 } else { 10202 bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV; 10203 tmo = bp->fw_reset_min_dsecs * HZ / 10; 10204 } 10205 bnxt_queue_fw_reset_work(bp, tmo); 10206 } 10207 fw_reset_exit: 10208 bnxt_rtnl_unlock_sp(bp); 10209 } 10210 10211 static void bnxt_chk_missed_irq(struct bnxt *bp) 10212 { 10213 int i; 10214 10215 if (!(bp->flags & BNXT_FLAG_CHIP_P5)) 10216 return; 10217 10218 for (i = 0; i < bp->cp_nr_rings; i++) { 10219 struct bnxt_napi *bnapi = bp->bnapi[i]; 10220 struct bnxt_cp_ring_info *cpr; 10221 u32 fw_ring_id; 10222 int j; 10223 10224 if (!bnapi) 10225 continue; 10226 10227 cpr = &bnapi->cp_ring; 10228 for (j = 0; j < 2; j++) { 10229 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j]; 10230 u32 val[2]; 10231 10232 if (!cpr2 || cpr2->has_more_work || 10233 !bnxt_has_work(bp, cpr2)) 10234 continue; 10235 10236 if (cpr2->cp_raw_cons != cpr2->last_cp_raw_cons) { 10237 cpr2->last_cp_raw_cons = cpr2->cp_raw_cons; 10238 continue; 10239 } 10240 fw_ring_id = cpr2->cp_ring_struct.fw_ring_id; 10241 bnxt_dbg_hwrm_ring_info_get(bp, 10242 DBG_RING_INFO_GET_REQ_RING_TYPE_L2_CMPL, 10243 fw_ring_id, &val[0], &val[1]); 10244 cpr->missed_irqs++; 10245 } 10246 } 10247 } 10248 10249 static void bnxt_cfg_ntp_filters(struct bnxt *); 10250 10251 static void bnxt_init_ethtool_link_settings(struct bnxt *bp) 10252 { 10253 struct bnxt_link_info *link_info = &bp->link_info; 10254 10255 if (BNXT_AUTO_MODE(link_info->auto_mode)) { 10256 link_info->autoneg = BNXT_AUTONEG_SPEED; 10257 if (bp->hwrm_spec_code >= 0x10201) { 10258 if (link_info->auto_pause_setting & 10259 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE) 10260 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL; 10261 } else { 10262 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL; 10263 } 10264 link_info->advertising = link_info->auto_link_speeds; 10265 } else { 10266 link_info->req_link_speed = link_info->force_link_speed; 10267 link_info->req_duplex = link_info->duplex_setting; 10268 } 10269 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) 10270 link_info->req_flow_ctrl = 10271 link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH; 10272 else 10273 link_info->req_flow_ctrl = link_info->force_pause_setting; 10274 } 10275 10276 static void bnxt_sp_task(struct work_struct *work) 10277 { 10278 struct bnxt *bp = container_of(work, struct bnxt, sp_task); 10279 10280 set_bit(BNXT_STATE_IN_SP_TASK, &bp->state); 10281 smp_mb__after_atomic(); 10282 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) { 10283 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state); 10284 return; 10285 } 10286 10287 if (test_and_clear_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event)) 10288 bnxt_cfg_rx_mode(bp); 10289 10290 if (test_and_clear_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event)) 10291 bnxt_cfg_ntp_filters(bp); 10292 if (test_and_clear_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event)) 10293 bnxt_hwrm_exec_fwd_req(bp); 10294 if (test_and_clear_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event)) { 10295 bnxt_hwrm_tunnel_dst_port_alloc( 10296 bp, bp->vxlan_port, 10297 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN); 10298 } 10299 if (test_and_clear_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event)) { 10300 bnxt_hwrm_tunnel_dst_port_free( 10301 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN); 10302 } 10303 if (test_and_clear_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event)) { 10304 bnxt_hwrm_tunnel_dst_port_alloc( 10305 bp, bp->nge_port, 10306 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE); 10307 } 10308 if (test_and_clear_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event)) { 10309 bnxt_hwrm_tunnel_dst_port_free( 10310 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE); 10311 } 10312 if (test_and_clear_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event)) { 10313 bnxt_hwrm_port_qstats(bp); 10314 bnxt_hwrm_port_qstats_ext(bp); 10315 bnxt_hwrm_pcie_qstats(bp); 10316 } 10317 10318 if (test_and_clear_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event)) { 10319 int rc; 10320 10321 mutex_lock(&bp->link_lock); 10322 if (test_and_clear_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT, 10323 &bp->sp_event)) 10324 bnxt_hwrm_phy_qcaps(bp); 10325 10326 if (test_and_clear_bit(BNXT_LINK_CFG_CHANGE_SP_EVENT, 10327 &bp->sp_event)) 10328 bnxt_init_ethtool_link_settings(bp); 10329 10330 rc = bnxt_update_link(bp, true); 10331 mutex_unlock(&bp->link_lock); 10332 if (rc) 10333 netdev_err(bp->dev, "SP task can't update link (rc: %x)\n", 10334 rc); 10335 } 10336 if (test_and_clear_bit(BNXT_UPDATE_PHY_SP_EVENT, &bp->sp_event)) { 10337 int rc; 10338 10339 mutex_lock(&bp->link_lock); 10340 rc = bnxt_update_phy_setting(bp); 10341 mutex_unlock(&bp->link_lock); 10342 if (rc) { 10343 netdev_warn(bp->dev, "update phy settings retry failed\n"); 10344 } else { 10345 bp->link_info.phy_retry = false; 10346 netdev_info(bp->dev, "update phy settings retry succeeded\n"); 10347 } 10348 } 10349 if (test_and_clear_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event)) { 10350 mutex_lock(&bp->link_lock); 10351 bnxt_get_port_module_status(bp); 10352 mutex_unlock(&bp->link_lock); 10353 } 10354 10355 if (test_and_clear_bit(BNXT_FLOW_STATS_SP_EVENT, &bp->sp_event)) 10356 bnxt_tc_flow_stats_work(bp); 10357 10358 if (test_and_clear_bit(BNXT_RING_COAL_NOW_SP_EVENT, &bp->sp_event)) 10359 bnxt_chk_missed_irq(bp); 10360 10361 /* These functions below will clear BNXT_STATE_IN_SP_TASK. They 10362 * must be the last functions to be called before exiting. 10363 */ 10364 if (test_and_clear_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event)) 10365 bnxt_reset(bp, false); 10366 10367 if (test_and_clear_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event)) 10368 bnxt_reset(bp, true); 10369 10370 if (test_and_clear_bit(BNXT_FW_RESET_NOTIFY_SP_EVENT, &bp->sp_event)) 10371 bnxt_devlink_health_report(bp, BNXT_FW_RESET_NOTIFY_SP_EVENT); 10372 10373 if (test_and_clear_bit(BNXT_FW_EXCEPTION_SP_EVENT, &bp->sp_event)) { 10374 if (!is_bnxt_fw_ok(bp)) 10375 bnxt_devlink_health_report(bp, 10376 BNXT_FW_EXCEPTION_SP_EVENT); 10377 } 10378 10379 smp_mb__before_atomic(); 10380 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state); 10381 } 10382 10383 /* Under rtnl_lock */ 10384 int bnxt_check_rings(struct bnxt *bp, int tx, int rx, bool sh, int tcs, 10385 int tx_xdp) 10386 { 10387 int max_rx, max_tx, tx_sets = 1; 10388 int tx_rings_needed, stats; 10389 int rx_rings = rx; 10390 int cp, vnics, rc; 10391 10392 if (tcs) 10393 tx_sets = tcs; 10394 10395 rc = bnxt_get_max_rings(bp, &max_rx, &max_tx, sh); 10396 if (rc) 10397 return rc; 10398 10399 if (max_rx < rx) 10400 return -ENOMEM; 10401 10402 tx_rings_needed = tx * tx_sets + tx_xdp; 10403 if (max_tx < tx_rings_needed) 10404 return -ENOMEM; 10405 10406 vnics = 1; 10407 if ((bp->flags & (BNXT_FLAG_RFS | BNXT_FLAG_CHIP_P5)) == BNXT_FLAG_RFS) 10408 vnics += rx_rings; 10409 10410 if (bp->flags & BNXT_FLAG_AGG_RINGS) 10411 rx_rings <<= 1; 10412 cp = sh ? max_t(int, tx_rings_needed, rx) : tx_rings_needed + rx; 10413 stats = cp; 10414 if (BNXT_NEW_RM(bp)) { 10415 cp += bnxt_get_ulp_msix_num(bp); 10416 stats += bnxt_get_ulp_stat_ctxs(bp); 10417 } 10418 return bnxt_hwrm_check_rings(bp, tx_rings_needed, rx_rings, rx, cp, 10419 stats, vnics); 10420 } 10421 10422 static void bnxt_unmap_bars(struct bnxt *bp, struct pci_dev *pdev) 10423 { 10424 if (bp->bar2) { 10425 pci_iounmap(pdev, bp->bar2); 10426 bp->bar2 = NULL; 10427 } 10428 10429 if (bp->bar1) { 10430 pci_iounmap(pdev, bp->bar1); 10431 bp->bar1 = NULL; 10432 } 10433 10434 if (bp->bar0) { 10435 pci_iounmap(pdev, bp->bar0); 10436 bp->bar0 = NULL; 10437 } 10438 } 10439 10440 static void bnxt_cleanup_pci(struct bnxt *bp) 10441 { 10442 bnxt_unmap_bars(bp, bp->pdev); 10443 pci_release_regions(bp->pdev); 10444 if (pci_is_enabled(bp->pdev)) 10445 pci_disable_device(bp->pdev); 10446 } 10447 10448 static void bnxt_init_dflt_coal(struct bnxt *bp) 10449 { 10450 struct bnxt_coal *coal; 10451 10452 /* Tick values in micro seconds. 10453 * 1 coal_buf x bufs_per_record = 1 completion record. 10454 */ 10455 coal = &bp->rx_coal; 10456 coal->coal_ticks = 10; 10457 coal->coal_bufs = 30; 10458 coal->coal_ticks_irq = 1; 10459 coal->coal_bufs_irq = 2; 10460 coal->idle_thresh = 50; 10461 coal->bufs_per_record = 2; 10462 coal->budget = 64; /* NAPI budget */ 10463 10464 coal = &bp->tx_coal; 10465 coal->coal_ticks = 28; 10466 coal->coal_bufs = 30; 10467 coal->coal_ticks_irq = 2; 10468 coal->coal_bufs_irq = 2; 10469 coal->bufs_per_record = 1; 10470 10471 bp->stats_coal_ticks = BNXT_DEF_STATS_COAL_TICKS; 10472 } 10473 10474 static void bnxt_alloc_fw_health(struct bnxt *bp) 10475 { 10476 if (bp->fw_health) 10477 return; 10478 10479 if (!(bp->fw_cap & BNXT_FW_CAP_HOT_RESET) && 10480 !(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)) 10481 return; 10482 10483 bp->fw_health = kzalloc(sizeof(*bp->fw_health), GFP_KERNEL); 10484 if (!bp->fw_health) { 10485 netdev_warn(bp->dev, "Failed to allocate fw_health\n"); 10486 bp->fw_cap &= ~BNXT_FW_CAP_HOT_RESET; 10487 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY; 10488 } 10489 } 10490 10491 static int bnxt_fw_init_one_p1(struct bnxt *bp) 10492 { 10493 int rc; 10494 10495 bp->fw_cap = 0; 10496 rc = bnxt_hwrm_ver_get(bp); 10497 if (rc) 10498 return rc; 10499 10500 if (bp->fw_cap & BNXT_FW_CAP_KONG_MB_CHNL) { 10501 rc = bnxt_alloc_kong_hwrm_resources(bp); 10502 if (rc) 10503 bp->fw_cap &= ~BNXT_FW_CAP_KONG_MB_CHNL; 10504 } 10505 10506 if ((bp->fw_cap & BNXT_FW_CAP_SHORT_CMD) || 10507 bp->hwrm_max_ext_req_len > BNXT_HWRM_MAX_REQ_LEN) { 10508 rc = bnxt_alloc_hwrm_short_cmd_req(bp); 10509 if (rc) 10510 return rc; 10511 } 10512 rc = bnxt_hwrm_func_reset(bp); 10513 if (rc) 10514 return -ENODEV; 10515 10516 bnxt_hwrm_fw_set_time(bp); 10517 return 0; 10518 } 10519 10520 static int bnxt_fw_init_one_p2(struct bnxt *bp) 10521 { 10522 int rc; 10523 10524 /* Get the MAX capabilities for this function */ 10525 rc = bnxt_hwrm_func_qcaps(bp); 10526 if (rc) { 10527 netdev_err(bp->dev, "hwrm query capability failure rc: %x\n", 10528 rc); 10529 return -ENODEV; 10530 } 10531 10532 rc = bnxt_hwrm_cfa_adv_flow_mgnt_qcaps(bp); 10533 if (rc) 10534 netdev_warn(bp->dev, "hwrm query adv flow mgnt failure rc: %d\n", 10535 rc); 10536 10537 bnxt_alloc_fw_health(bp); 10538 rc = bnxt_hwrm_error_recovery_qcfg(bp); 10539 if (rc) 10540 netdev_warn(bp->dev, "hwrm query error recovery failure rc: %d\n", 10541 rc); 10542 10543 rc = bnxt_hwrm_func_drv_rgtr(bp, NULL, 0, false); 10544 if (rc) 10545 return -ENODEV; 10546 10547 bnxt_hwrm_func_qcfg(bp); 10548 bnxt_hwrm_vnic_qcaps(bp); 10549 bnxt_hwrm_port_led_qcaps(bp); 10550 bnxt_ethtool_init(bp); 10551 bnxt_dcb_init(bp); 10552 return 0; 10553 } 10554 10555 static void bnxt_set_dflt_rss_hash_type(struct bnxt *bp) 10556 { 10557 bp->flags &= ~BNXT_FLAG_UDP_RSS_CAP; 10558 bp->rss_hash_cfg = VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 | 10559 VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 | 10560 VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 | 10561 VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6; 10562 if (BNXT_CHIP_P4_PLUS(bp) && bp->hwrm_spec_code >= 0x10501) { 10563 bp->flags |= BNXT_FLAG_UDP_RSS_CAP; 10564 bp->rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 | 10565 VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6; 10566 } 10567 } 10568 10569 static void bnxt_set_dflt_rfs(struct bnxt *bp) 10570 { 10571 struct net_device *dev = bp->dev; 10572 10573 dev->hw_features &= ~NETIF_F_NTUPLE; 10574 dev->features &= ~NETIF_F_NTUPLE; 10575 bp->flags &= ~BNXT_FLAG_RFS; 10576 if (bnxt_rfs_supported(bp)) { 10577 dev->hw_features |= NETIF_F_NTUPLE; 10578 if (bnxt_rfs_capable(bp)) { 10579 bp->flags |= BNXT_FLAG_RFS; 10580 dev->features |= NETIF_F_NTUPLE; 10581 } 10582 } 10583 } 10584 10585 static void bnxt_fw_init_one_p3(struct bnxt *bp) 10586 { 10587 struct pci_dev *pdev = bp->pdev; 10588 10589 bnxt_set_dflt_rss_hash_type(bp); 10590 bnxt_set_dflt_rfs(bp); 10591 10592 bnxt_get_wol_settings(bp); 10593 if (bp->flags & BNXT_FLAG_WOL_CAP) 10594 device_set_wakeup_enable(&pdev->dev, bp->wol); 10595 else 10596 device_set_wakeup_capable(&pdev->dev, false); 10597 10598 bnxt_hwrm_set_cache_line_size(bp, cache_line_size()); 10599 bnxt_hwrm_coal_params_qcaps(bp); 10600 } 10601 10602 static int bnxt_fw_init_one(struct bnxt *bp) 10603 { 10604 int rc; 10605 10606 rc = bnxt_fw_init_one_p1(bp); 10607 if (rc) { 10608 netdev_err(bp->dev, "Firmware init phase 1 failed\n"); 10609 return rc; 10610 } 10611 rc = bnxt_fw_init_one_p2(bp); 10612 if (rc) { 10613 netdev_err(bp->dev, "Firmware init phase 2 failed\n"); 10614 return rc; 10615 } 10616 rc = bnxt_approve_mac(bp, bp->dev->dev_addr, false); 10617 if (rc) 10618 return rc; 10619 10620 /* In case fw capabilities have changed, destroy the unneeded 10621 * reporters and create newly capable ones. 10622 */ 10623 bnxt_dl_fw_reporters_destroy(bp, false); 10624 bnxt_dl_fw_reporters_create(bp); 10625 bnxt_fw_init_one_p3(bp); 10626 return 0; 10627 } 10628 10629 static void bnxt_fw_reset_writel(struct bnxt *bp, int reg_idx) 10630 { 10631 struct bnxt_fw_health *fw_health = bp->fw_health; 10632 u32 reg = fw_health->fw_reset_seq_regs[reg_idx]; 10633 u32 val = fw_health->fw_reset_seq_vals[reg_idx]; 10634 u32 reg_type, reg_off, delay_msecs; 10635 10636 delay_msecs = fw_health->fw_reset_seq_delay_msec[reg_idx]; 10637 reg_type = BNXT_FW_HEALTH_REG_TYPE(reg); 10638 reg_off = BNXT_FW_HEALTH_REG_OFF(reg); 10639 switch (reg_type) { 10640 case BNXT_FW_HEALTH_REG_TYPE_CFG: 10641 pci_write_config_dword(bp->pdev, reg_off, val); 10642 break; 10643 case BNXT_FW_HEALTH_REG_TYPE_GRC: 10644 writel(reg_off & BNXT_GRC_BASE_MASK, 10645 bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4); 10646 reg_off = (reg_off & BNXT_GRC_OFFSET_MASK) + 0x2000; 10647 /* fall through */ 10648 case BNXT_FW_HEALTH_REG_TYPE_BAR0: 10649 writel(val, bp->bar0 + reg_off); 10650 break; 10651 case BNXT_FW_HEALTH_REG_TYPE_BAR1: 10652 writel(val, bp->bar1 + reg_off); 10653 break; 10654 } 10655 if (delay_msecs) { 10656 pci_read_config_dword(bp->pdev, 0, &val); 10657 msleep(delay_msecs); 10658 } 10659 } 10660 10661 static void bnxt_reset_all(struct bnxt *bp) 10662 { 10663 struct bnxt_fw_health *fw_health = bp->fw_health; 10664 int i, rc; 10665 10666 if (bp->fw_cap & BNXT_FW_CAP_ERR_RECOVER_RELOAD) { 10667 #ifdef CONFIG_TEE_BNXT_FW 10668 rc = tee_bnxt_fw_load(); 10669 if (rc) 10670 netdev_err(bp->dev, "Unable to reset FW rc=%d\n", rc); 10671 bp->fw_reset_timestamp = jiffies; 10672 #endif 10673 return; 10674 } 10675 10676 if (fw_health->flags & ERROR_RECOVERY_QCFG_RESP_FLAGS_HOST) { 10677 for (i = 0; i < fw_health->fw_reset_seq_cnt; i++) 10678 bnxt_fw_reset_writel(bp, i); 10679 } else if (fw_health->flags & ERROR_RECOVERY_QCFG_RESP_FLAGS_CO_CPU) { 10680 struct hwrm_fw_reset_input req = {0}; 10681 10682 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FW_RESET, -1, -1); 10683 req.resp_addr = cpu_to_le64(bp->hwrm_cmd_kong_resp_dma_addr); 10684 req.embedded_proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP; 10685 req.selfrst_status = FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP; 10686 req.flags = FW_RESET_REQ_FLAGS_RESET_GRACEFUL; 10687 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 10688 if (rc) 10689 netdev_warn(bp->dev, "Unable to reset FW rc=%d\n", rc); 10690 } 10691 bp->fw_reset_timestamp = jiffies; 10692 } 10693 10694 static void bnxt_fw_reset_task(struct work_struct *work) 10695 { 10696 struct bnxt *bp = container_of(work, struct bnxt, fw_reset_task.work); 10697 int rc; 10698 10699 if (!test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) { 10700 netdev_err(bp->dev, "bnxt_fw_reset_task() called when not in fw reset mode!\n"); 10701 return; 10702 } 10703 10704 switch (bp->fw_reset_state) { 10705 case BNXT_FW_RESET_STATE_POLL_VF: { 10706 int n = bnxt_get_registered_vfs(bp); 10707 int tmo; 10708 10709 if (n < 0) { 10710 netdev_err(bp->dev, "Firmware reset aborted, subsequent func_qcfg cmd failed, rc = %d, %d msecs since reset timestamp\n", 10711 n, jiffies_to_msecs(jiffies - 10712 bp->fw_reset_timestamp)); 10713 goto fw_reset_abort; 10714 } else if (n > 0) { 10715 if (time_after(jiffies, bp->fw_reset_timestamp + 10716 (bp->fw_reset_max_dsecs * HZ / 10))) { 10717 clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state); 10718 bp->fw_reset_state = 0; 10719 netdev_err(bp->dev, "Firmware reset aborted, bnxt_get_registered_vfs() returns %d\n", 10720 n); 10721 return; 10722 } 10723 bnxt_queue_fw_reset_work(bp, HZ / 10); 10724 return; 10725 } 10726 bp->fw_reset_timestamp = jiffies; 10727 rtnl_lock(); 10728 bnxt_fw_reset_close(bp); 10729 if (bp->fw_cap & BNXT_FW_CAP_ERR_RECOVER_RELOAD) { 10730 bp->fw_reset_state = BNXT_FW_RESET_STATE_POLL_FW_DOWN; 10731 tmo = HZ / 10; 10732 } else { 10733 bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV; 10734 tmo = bp->fw_reset_min_dsecs * HZ / 10; 10735 } 10736 rtnl_unlock(); 10737 bnxt_queue_fw_reset_work(bp, tmo); 10738 return; 10739 } 10740 case BNXT_FW_RESET_STATE_POLL_FW_DOWN: { 10741 u32 val; 10742 10743 val = bnxt_fw_health_readl(bp, BNXT_FW_HEALTH_REG); 10744 if (!(val & BNXT_FW_STATUS_SHUTDOWN) && 10745 !time_after(jiffies, bp->fw_reset_timestamp + 10746 (bp->fw_reset_max_dsecs * HZ / 10))) { 10747 bnxt_queue_fw_reset_work(bp, HZ / 5); 10748 return; 10749 } 10750 10751 if (!bp->fw_health->master) { 10752 u32 wait_dsecs = bp->fw_health->normal_func_wait_dsecs; 10753 10754 bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV; 10755 bnxt_queue_fw_reset_work(bp, wait_dsecs * HZ / 10); 10756 return; 10757 } 10758 bp->fw_reset_state = BNXT_FW_RESET_STATE_RESET_FW; 10759 } 10760 /* fall through */ 10761 case BNXT_FW_RESET_STATE_RESET_FW: 10762 bnxt_reset_all(bp); 10763 bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV; 10764 bnxt_queue_fw_reset_work(bp, bp->fw_reset_min_dsecs * HZ / 10); 10765 return; 10766 case BNXT_FW_RESET_STATE_ENABLE_DEV: 10767 if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state)) { 10768 u32 val; 10769 10770 val = bnxt_fw_health_readl(bp, 10771 BNXT_FW_RESET_INPROG_REG); 10772 if (val) 10773 netdev_warn(bp->dev, "FW reset inprog %x after min wait time.\n", 10774 val); 10775 } 10776 clear_bit(BNXT_STATE_FW_FATAL_COND, &bp->state); 10777 if (pci_enable_device(bp->pdev)) { 10778 netdev_err(bp->dev, "Cannot re-enable PCI device\n"); 10779 goto fw_reset_abort; 10780 } 10781 pci_set_master(bp->pdev); 10782 bp->fw_reset_state = BNXT_FW_RESET_STATE_POLL_FW; 10783 /* fall through */ 10784 case BNXT_FW_RESET_STATE_POLL_FW: 10785 bp->hwrm_cmd_timeout = SHORT_HWRM_CMD_TIMEOUT; 10786 rc = __bnxt_hwrm_ver_get(bp, true); 10787 if (rc) { 10788 if (time_after(jiffies, bp->fw_reset_timestamp + 10789 (bp->fw_reset_max_dsecs * HZ / 10))) { 10790 netdev_err(bp->dev, "Firmware reset aborted\n"); 10791 goto fw_reset_abort; 10792 } 10793 bnxt_queue_fw_reset_work(bp, HZ / 5); 10794 return; 10795 } 10796 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT; 10797 bp->fw_reset_state = BNXT_FW_RESET_STATE_OPENING; 10798 /* fall through */ 10799 case BNXT_FW_RESET_STATE_OPENING: 10800 while (!rtnl_trylock()) { 10801 bnxt_queue_fw_reset_work(bp, HZ / 10); 10802 return; 10803 } 10804 rc = bnxt_open(bp->dev); 10805 if (rc) { 10806 netdev_err(bp->dev, "bnxt_open_nic() failed\n"); 10807 clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state); 10808 dev_close(bp->dev); 10809 } 10810 10811 bp->fw_reset_state = 0; 10812 /* Make sure fw_reset_state is 0 before clearing the flag */ 10813 smp_mb__before_atomic(); 10814 clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state); 10815 bnxt_ulp_start(bp, rc); 10816 if (!rc) 10817 bnxt_reenable_sriov(bp); 10818 bnxt_dl_health_recovery_done(bp); 10819 bnxt_dl_health_status_update(bp, true); 10820 rtnl_unlock(); 10821 break; 10822 } 10823 return; 10824 10825 fw_reset_abort: 10826 clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state); 10827 if (bp->fw_reset_state != BNXT_FW_RESET_STATE_POLL_VF) 10828 bnxt_dl_health_status_update(bp, false); 10829 bp->fw_reset_state = 0; 10830 rtnl_lock(); 10831 dev_close(bp->dev); 10832 rtnl_unlock(); 10833 } 10834 10835 static int bnxt_init_board(struct pci_dev *pdev, struct net_device *dev) 10836 { 10837 int rc; 10838 struct bnxt *bp = netdev_priv(dev); 10839 10840 SET_NETDEV_DEV(dev, &pdev->dev); 10841 10842 /* enable device (incl. PCI PM wakeup), and bus-mastering */ 10843 rc = pci_enable_device(pdev); 10844 if (rc) { 10845 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n"); 10846 goto init_err; 10847 } 10848 10849 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 10850 dev_err(&pdev->dev, 10851 "Cannot find PCI device base address, aborting\n"); 10852 rc = -ENODEV; 10853 goto init_err_disable; 10854 } 10855 10856 rc = pci_request_regions(pdev, DRV_MODULE_NAME); 10857 if (rc) { 10858 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n"); 10859 goto init_err_disable; 10860 } 10861 10862 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) != 0 && 10863 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)) != 0) { 10864 dev_err(&pdev->dev, "System does not support DMA, aborting\n"); 10865 goto init_err_disable; 10866 } 10867 10868 pci_set_master(pdev); 10869 10870 bp->dev = dev; 10871 bp->pdev = pdev; 10872 10873 bp->bar0 = pci_ioremap_bar(pdev, 0); 10874 if (!bp->bar0) { 10875 dev_err(&pdev->dev, "Cannot map device registers, aborting\n"); 10876 rc = -ENOMEM; 10877 goto init_err_release; 10878 } 10879 10880 bp->bar1 = pci_ioremap_bar(pdev, 2); 10881 if (!bp->bar1) { 10882 dev_err(&pdev->dev, "Cannot map doorbell registers, aborting\n"); 10883 rc = -ENOMEM; 10884 goto init_err_release; 10885 } 10886 10887 bp->bar2 = pci_ioremap_bar(pdev, 4); 10888 if (!bp->bar2) { 10889 dev_err(&pdev->dev, "Cannot map bar4 registers, aborting\n"); 10890 rc = -ENOMEM; 10891 goto init_err_release; 10892 } 10893 10894 pci_enable_pcie_error_reporting(pdev); 10895 10896 INIT_WORK(&bp->sp_task, bnxt_sp_task); 10897 INIT_DELAYED_WORK(&bp->fw_reset_task, bnxt_fw_reset_task); 10898 10899 spin_lock_init(&bp->ntp_fltr_lock); 10900 #if BITS_PER_LONG == 32 10901 spin_lock_init(&bp->db_lock); 10902 #endif 10903 10904 bp->rx_ring_size = BNXT_DEFAULT_RX_RING_SIZE; 10905 bp->tx_ring_size = BNXT_DEFAULT_TX_RING_SIZE; 10906 10907 bnxt_init_dflt_coal(bp); 10908 10909 timer_setup(&bp->timer, bnxt_timer, 0); 10910 bp->current_interval = BNXT_TIMER_INTERVAL; 10911 10912 clear_bit(BNXT_STATE_OPEN, &bp->state); 10913 return 0; 10914 10915 init_err_release: 10916 bnxt_unmap_bars(bp, pdev); 10917 pci_release_regions(pdev); 10918 10919 init_err_disable: 10920 pci_disable_device(pdev); 10921 10922 init_err: 10923 return rc; 10924 } 10925 10926 /* rtnl_lock held */ 10927 static int bnxt_change_mac_addr(struct net_device *dev, void *p) 10928 { 10929 struct sockaddr *addr = p; 10930 struct bnxt *bp = netdev_priv(dev); 10931 int rc = 0; 10932 10933 if (!is_valid_ether_addr(addr->sa_data)) 10934 return -EADDRNOTAVAIL; 10935 10936 if (ether_addr_equal(addr->sa_data, dev->dev_addr)) 10937 return 0; 10938 10939 rc = bnxt_approve_mac(bp, addr->sa_data, true); 10940 if (rc) 10941 return rc; 10942 10943 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); 10944 if (netif_running(dev)) { 10945 bnxt_close_nic(bp, false, false); 10946 rc = bnxt_open_nic(bp, false, false); 10947 } 10948 10949 return rc; 10950 } 10951 10952 /* rtnl_lock held */ 10953 static int bnxt_change_mtu(struct net_device *dev, int new_mtu) 10954 { 10955 struct bnxt *bp = netdev_priv(dev); 10956 10957 if (netif_running(dev)) 10958 bnxt_close_nic(bp, false, false); 10959 10960 dev->mtu = new_mtu; 10961 bnxt_set_ring_params(bp); 10962 10963 if (netif_running(dev)) 10964 return bnxt_open_nic(bp, false, false); 10965 10966 return 0; 10967 } 10968 10969 int bnxt_setup_mq_tc(struct net_device *dev, u8 tc) 10970 { 10971 struct bnxt *bp = netdev_priv(dev); 10972 bool sh = false; 10973 int rc; 10974 10975 if (tc > bp->max_tc) { 10976 netdev_err(dev, "Too many traffic classes requested: %d. Max supported is %d.\n", 10977 tc, bp->max_tc); 10978 return -EINVAL; 10979 } 10980 10981 if (netdev_get_num_tc(dev) == tc) 10982 return 0; 10983 10984 if (bp->flags & BNXT_FLAG_SHARED_RINGS) 10985 sh = true; 10986 10987 rc = bnxt_check_rings(bp, bp->tx_nr_rings_per_tc, bp->rx_nr_rings, 10988 sh, tc, bp->tx_nr_rings_xdp); 10989 if (rc) 10990 return rc; 10991 10992 /* Needs to close the device and do hw resource re-allocations */ 10993 if (netif_running(bp->dev)) 10994 bnxt_close_nic(bp, true, false); 10995 10996 if (tc) { 10997 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tc; 10998 netdev_set_num_tc(dev, tc); 10999 } else { 11000 bp->tx_nr_rings = bp->tx_nr_rings_per_tc; 11001 netdev_reset_tc(dev); 11002 } 11003 bp->tx_nr_rings += bp->tx_nr_rings_xdp; 11004 bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) : 11005 bp->tx_nr_rings + bp->rx_nr_rings; 11006 11007 if (netif_running(bp->dev)) 11008 return bnxt_open_nic(bp, true, false); 11009 11010 return 0; 11011 } 11012 11013 static int bnxt_setup_tc_block_cb(enum tc_setup_type type, void *type_data, 11014 void *cb_priv) 11015 { 11016 struct bnxt *bp = cb_priv; 11017 11018 if (!bnxt_tc_flower_enabled(bp) || 11019 !tc_cls_can_offload_and_chain0(bp->dev, type_data)) 11020 return -EOPNOTSUPP; 11021 11022 switch (type) { 11023 case TC_SETUP_CLSFLOWER: 11024 return bnxt_tc_setup_flower(bp, bp->pf.fw_fid, type_data); 11025 default: 11026 return -EOPNOTSUPP; 11027 } 11028 } 11029 11030 LIST_HEAD(bnxt_block_cb_list); 11031 11032 static int bnxt_setup_tc(struct net_device *dev, enum tc_setup_type type, 11033 void *type_data) 11034 { 11035 struct bnxt *bp = netdev_priv(dev); 11036 11037 switch (type) { 11038 case TC_SETUP_BLOCK: 11039 return flow_block_cb_setup_simple(type_data, 11040 &bnxt_block_cb_list, 11041 bnxt_setup_tc_block_cb, 11042 bp, bp, true); 11043 case TC_SETUP_QDISC_MQPRIO: { 11044 struct tc_mqprio_qopt *mqprio = type_data; 11045 11046 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS; 11047 11048 return bnxt_setup_mq_tc(dev, mqprio->num_tc); 11049 } 11050 default: 11051 return -EOPNOTSUPP; 11052 } 11053 } 11054 11055 #ifdef CONFIG_RFS_ACCEL 11056 static bool bnxt_fltr_match(struct bnxt_ntuple_filter *f1, 11057 struct bnxt_ntuple_filter *f2) 11058 { 11059 struct flow_keys *keys1 = &f1->fkeys; 11060 struct flow_keys *keys2 = &f2->fkeys; 11061 11062 if (keys1->basic.n_proto != keys2->basic.n_proto || 11063 keys1->basic.ip_proto != keys2->basic.ip_proto) 11064 return false; 11065 11066 if (keys1->basic.n_proto == htons(ETH_P_IP)) { 11067 if (keys1->addrs.v4addrs.src != keys2->addrs.v4addrs.src || 11068 keys1->addrs.v4addrs.dst != keys2->addrs.v4addrs.dst) 11069 return false; 11070 } else { 11071 if (memcmp(&keys1->addrs.v6addrs.src, &keys2->addrs.v6addrs.src, 11072 sizeof(keys1->addrs.v6addrs.src)) || 11073 memcmp(&keys1->addrs.v6addrs.dst, &keys2->addrs.v6addrs.dst, 11074 sizeof(keys1->addrs.v6addrs.dst))) 11075 return false; 11076 } 11077 11078 if (keys1->ports.ports == keys2->ports.ports && 11079 keys1->control.flags == keys2->control.flags && 11080 ether_addr_equal(f1->src_mac_addr, f2->src_mac_addr) && 11081 ether_addr_equal(f1->dst_mac_addr, f2->dst_mac_addr)) 11082 return true; 11083 11084 return false; 11085 } 11086 11087 static int bnxt_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb, 11088 u16 rxq_index, u32 flow_id) 11089 { 11090 struct bnxt *bp = netdev_priv(dev); 11091 struct bnxt_ntuple_filter *fltr, *new_fltr; 11092 struct flow_keys *fkeys; 11093 struct ethhdr *eth = (struct ethhdr *)skb_mac_header(skb); 11094 int rc = 0, idx, bit_id, l2_idx = 0; 11095 struct hlist_head *head; 11096 u32 flags; 11097 11098 if (!ether_addr_equal(dev->dev_addr, eth->h_dest)) { 11099 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 11100 int off = 0, j; 11101 11102 netif_addr_lock_bh(dev); 11103 for (j = 0; j < vnic->uc_filter_count; j++, off += ETH_ALEN) { 11104 if (ether_addr_equal(eth->h_dest, 11105 vnic->uc_list + off)) { 11106 l2_idx = j + 1; 11107 break; 11108 } 11109 } 11110 netif_addr_unlock_bh(dev); 11111 if (!l2_idx) 11112 return -EINVAL; 11113 } 11114 new_fltr = kzalloc(sizeof(*new_fltr), GFP_ATOMIC); 11115 if (!new_fltr) 11116 return -ENOMEM; 11117 11118 fkeys = &new_fltr->fkeys; 11119 if (!skb_flow_dissect_flow_keys(skb, fkeys, 0)) { 11120 rc = -EPROTONOSUPPORT; 11121 goto err_free; 11122 } 11123 11124 if ((fkeys->basic.n_proto != htons(ETH_P_IP) && 11125 fkeys->basic.n_proto != htons(ETH_P_IPV6)) || 11126 ((fkeys->basic.ip_proto != IPPROTO_TCP) && 11127 (fkeys->basic.ip_proto != IPPROTO_UDP))) { 11128 rc = -EPROTONOSUPPORT; 11129 goto err_free; 11130 } 11131 if (fkeys->basic.n_proto == htons(ETH_P_IPV6) && 11132 bp->hwrm_spec_code < 0x10601) { 11133 rc = -EPROTONOSUPPORT; 11134 goto err_free; 11135 } 11136 flags = fkeys->control.flags; 11137 if (((flags & FLOW_DIS_ENCAPSULATION) && 11138 bp->hwrm_spec_code < 0x10601) || (flags & FLOW_DIS_IS_FRAGMENT)) { 11139 rc = -EPROTONOSUPPORT; 11140 goto err_free; 11141 } 11142 11143 memcpy(new_fltr->dst_mac_addr, eth->h_dest, ETH_ALEN); 11144 memcpy(new_fltr->src_mac_addr, eth->h_source, ETH_ALEN); 11145 11146 idx = skb_get_hash_raw(skb) & BNXT_NTP_FLTR_HASH_MASK; 11147 head = &bp->ntp_fltr_hash_tbl[idx]; 11148 rcu_read_lock(); 11149 hlist_for_each_entry_rcu(fltr, head, hash) { 11150 if (bnxt_fltr_match(fltr, new_fltr)) { 11151 rcu_read_unlock(); 11152 rc = 0; 11153 goto err_free; 11154 } 11155 } 11156 rcu_read_unlock(); 11157 11158 spin_lock_bh(&bp->ntp_fltr_lock); 11159 bit_id = bitmap_find_free_region(bp->ntp_fltr_bmap, 11160 BNXT_NTP_FLTR_MAX_FLTR, 0); 11161 if (bit_id < 0) { 11162 spin_unlock_bh(&bp->ntp_fltr_lock); 11163 rc = -ENOMEM; 11164 goto err_free; 11165 } 11166 11167 new_fltr->sw_id = (u16)bit_id; 11168 new_fltr->flow_id = flow_id; 11169 new_fltr->l2_fltr_idx = l2_idx; 11170 new_fltr->rxq = rxq_index; 11171 hlist_add_head_rcu(&new_fltr->hash, head); 11172 bp->ntp_fltr_count++; 11173 spin_unlock_bh(&bp->ntp_fltr_lock); 11174 11175 set_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event); 11176 bnxt_queue_sp_work(bp); 11177 11178 return new_fltr->sw_id; 11179 11180 err_free: 11181 kfree(new_fltr); 11182 return rc; 11183 } 11184 11185 static void bnxt_cfg_ntp_filters(struct bnxt *bp) 11186 { 11187 int i; 11188 11189 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) { 11190 struct hlist_head *head; 11191 struct hlist_node *tmp; 11192 struct bnxt_ntuple_filter *fltr; 11193 int rc; 11194 11195 head = &bp->ntp_fltr_hash_tbl[i]; 11196 hlist_for_each_entry_safe(fltr, tmp, head, hash) { 11197 bool del = false; 11198 11199 if (test_bit(BNXT_FLTR_VALID, &fltr->state)) { 11200 if (rps_may_expire_flow(bp->dev, fltr->rxq, 11201 fltr->flow_id, 11202 fltr->sw_id)) { 11203 bnxt_hwrm_cfa_ntuple_filter_free(bp, 11204 fltr); 11205 del = true; 11206 } 11207 } else { 11208 rc = bnxt_hwrm_cfa_ntuple_filter_alloc(bp, 11209 fltr); 11210 if (rc) 11211 del = true; 11212 else 11213 set_bit(BNXT_FLTR_VALID, &fltr->state); 11214 } 11215 11216 if (del) { 11217 spin_lock_bh(&bp->ntp_fltr_lock); 11218 hlist_del_rcu(&fltr->hash); 11219 bp->ntp_fltr_count--; 11220 spin_unlock_bh(&bp->ntp_fltr_lock); 11221 synchronize_rcu(); 11222 clear_bit(fltr->sw_id, bp->ntp_fltr_bmap); 11223 kfree(fltr); 11224 } 11225 } 11226 } 11227 if (test_and_clear_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event)) 11228 netdev_info(bp->dev, "Receive PF driver unload event!\n"); 11229 } 11230 11231 #else 11232 11233 static void bnxt_cfg_ntp_filters(struct bnxt *bp) 11234 { 11235 } 11236 11237 #endif /* CONFIG_RFS_ACCEL */ 11238 11239 static void bnxt_udp_tunnel_add(struct net_device *dev, 11240 struct udp_tunnel_info *ti) 11241 { 11242 struct bnxt *bp = netdev_priv(dev); 11243 11244 if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET) 11245 return; 11246 11247 if (!netif_running(dev)) 11248 return; 11249 11250 switch (ti->type) { 11251 case UDP_TUNNEL_TYPE_VXLAN: 11252 if (bp->vxlan_port_cnt && bp->vxlan_port != ti->port) 11253 return; 11254 11255 bp->vxlan_port_cnt++; 11256 if (bp->vxlan_port_cnt == 1) { 11257 bp->vxlan_port = ti->port; 11258 set_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event); 11259 bnxt_queue_sp_work(bp); 11260 } 11261 break; 11262 case UDP_TUNNEL_TYPE_GENEVE: 11263 if (bp->nge_port_cnt && bp->nge_port != ti->port) 11264 return; 11265 11266 bp->nge_port_cnt++; 11267 if (bp->nge_port_cnt == 1) { 11268 bp->nge_port = ti->port; 11269 set_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event); 11270 } 11271 break; 11272 default: 11273 return; 11274 } 11275 11276 bnxt_queue_sp_work(bp); 11277 } 11278 11279 static void bnxt_udp_tunnel_del(struct net_device *dev, 11280 struct udp_tunnel_info *ti) 11281 { 11282 struct bnxt *bp = netdev_priv(dev); 11283 11284 if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET) 11285 return; 11286 11287 if (!netif_running(dev)) 11288 return; 11289 11290 switch (ti->type) { 11291 case UDP_TUNNEL_TYPE_VXLAN: 11292 if (!bp->vxlan_port_cnt || bp->vxlan_port != ti->port) 11293 return; 11294 bp->vxlan_port_cnt--; 11295 11296 if (bp->vxlan_port_cnt != 0) 11297 return; 11298 11299 set_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event); 11300 break; 11301 case UDP_TUNNEL_TYPE_GENEVE: 11302 if (!bp->nge_port_cnt || bp->nge_port != ti->port) 11303 return; 11304 bp->nge_port_cnt--; 11305 11306 if (bp->nge_port_cnt != 0) 11307 return; 11308 11309 set_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event); 11310 break; 11311 default: 11312 return; 11313 } 11314 11315 bnxt_queue_sp_work(bp); 11316 } 11317 11318 static int bnxt_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq, 11319 struct net_device *dev, u32 filter_mask, 11320 int nlflags) 11321 { 11322 struct bnxt *bp = netdev_priv(dev); 11323 11324 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, bp->br_mode, 0, 0, 11325 nlflags, filter_mask, NULL); 11326 } 11327 11328 static int bnxt_bridge_setlink(struct net_device *dev, struct nlmsghdr *nlh, 11329 u16 flags, struct netlink_ext_ack *extack) 11330 { 11331 struct bnxt *bp = netdev_priv(dev); 11332 struct nlattr *attr, *br_spec; 11333 int rem, rc = 0; 11334 11335 if (bp->hwrm_spec_code < 0x10708 || !BNXT_SINGLE_PF(bp)) 11336 return -EOPNOTSUPP; 11337 11338 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC); 11339 if (!br_spec) 11340 return -EINVAL; 11341 11342 nla_for_each_nested(attr, br_spec, rem) { 11343 u16 mode; 11344 11345 if (nla_type(attr) != IFLA_BRIDGE_MODE) 11346 continue; 11347 11348 if (nla_len(attr) < sizeof(mode)) 11349 return -EINVAL; 11350 11351 mode = nla_get_u16(attr); 11352 if (mode == bp->br_mode) 11353 break; 11354 11355 rc = bnxt_hwrm_set_br_mode(bp, mode); 11356 if (!rc) 11357 bp->br_mode = mode; 11358 break; 11359 } 11360 return rc; 11361 } 11362 11363 int bnxt_get_port_parent_id(struct net_device *dev, 11364 struct netdev_phys_item_id *ppid) 11365 { 11366 struct bnxt *bp = netdev_priv(dev); 11367 11368 if (bp->eswitch_mode != DEVLINK_ESWITCH_MODE_SWITCHDEV) 11369 return -EOPNOTSUPP; 11370 11371 /* The PF and it's VF-reps only support the switchdev framework */ 11372 if (!BNXT_PF(bp) || !(bp->flags & BNXT_FLAG_DSN_VALID)) 11373 return -EOPNOTSUPP; 11374 11375 ppid->id_len = sizeof(bp->dsn); 11376 memcpy(ppid->id, bp->dsn, ppid->id_len); 11377 11378 return 0; 11379 } 11380 11381 static struct devlink_port *bnxt_get_devlink_port(struct net_device *dev) 11382 { 11383 struct bnxt *bp = netdev_priv(dev); 11384 11385 return &bp->dl_port; 11386 } 11387 11388 static const struct net_device_ops bnxt_netdev_ops = { 11389 .ndo_open = bnxt_open, 11390 .ndo_start_xmit = bnxt_start_xmit, 11391 .ndo_stop = bnxt_close, 11392 .ndo_get_stats64 = bnxt_get_stats64, 11393 .ndo_set_rx_mode = bnxt_set_rx_mode, 11394 .ndo_do_ioctl = bnxt_ioctl, 11395 .ndo_validate_addr = eth_validate_addr, 11396 .ndo_set_mac_address = bnxt_change_mac_addr, 11397 .ndo_change_mtu = bnxt_change_mtu, 11398 .ndo_fix_features = bnxt_fix_features, 11399 .ndo_set_features = bnxt_set_features, 11400 .ndo_tx_timeout = bnxt_tx_timeout, 11401 #ifdef CONFIG_BNXT_SRIOV 11402 .ndo_get_vf_config = bnxt_get_vf_config, 11403 .ndo_set_vf_mac = bnxt_set_vf_mac, 11404 .ndo_set_vf_vlan = bnxt_set_vf_vlan, 11405 .ndo_set_vf_rate = bnxt_set_vf_bw, 11406 .ndo_set_vf_link_state = bnxt_set_vf_link_state, 11407 .ndo_set_vf_spoofchk = bnxt_set_vf_spoofchk, 11408 .ndo_set_vf_trust = bnxt_set_vf_trust, 11409 #endif 11410 .ndo_setup_tc = bnxt_setup_tc, 11411 #ifdef CONFIG_RFS_ACCEL 11412 .ndo_rx_flow_steer = bnxt_rx_flow_steer, 11413 #endif 11414 .ndo_udp_tunnel_add = bnxt_udp_tunnel_add, 11415 .ndo_udp_tunnel_del = bnxt_udp_tunnel_del, 11416 .ndo_bpf = bnxt_xdp, 11417 .ndo_xdp_xmit = bnxt_xdp_xmit, 11418 .ndo_bridge_getlink = bnxt_bridge_getlink, 11419 .ndo_bridge_setlink = bnxt_bridge_setlink, 11420 .ndo_get_devlink_port = bnxt_get_devlink_port, 11421 }; 11422 11423 static void bnxt_remove_one(struct pci_dev *pdev) 11424 { 11425 struct net_device *dev = pci_get_drvdata(pdev); 11426 struct bnxt *bp = netdev_priv(dev); 11427 11428 if (BNXT_PF(bp)) 11429 bnxt_sriov_disable(bp); 11430 11431 bnxt_dl_fw_reporters_destroy(bp, true); 11432 if (BNXT_PF(bp)) 11433 devlink_port_type_clear(&bp->dl_port); 11434 pci_disable_pcie_error_reporting(pdev); 11435 unregister_netdev(dev); 11436 bnxt_dl_unregister(bp); 11437 bnxt_shutdown_tc(bp); 11438 bnxt_cancel_sp_work(bp); 11439 bp->sp_event = 0; 11440 11441 bnxt_clear_int_mode(bp); 11442 bnxt_hwrm_func_drv_unrgtr(bp); 11443 bnxt_free_hwrm_resources(bp); 11444 bnxt_free_hwrm_short_cmd_req(bp); 11445 bnxt_ethtool_free(bp); 11446 bnxt_dcb_free(bp); 11447 kfree(bp->edev); 11448 bp->edev = NULL; 11449 kfree(bp->fw_health); 11450 bp->fw_health = NULL; 11451 bnxt_cleanup_pci(bp); 11452 bnxt_free_ctx_mem(bp); 11453 kfree(bp->ctx); 11454 bp->ctx = NULL; 11455 bnxt_free_port_stats(bp); 11456 free_netdev(dev); 11457 } 11458 11459 static int bnxt_probe_phy(struct bnxt *bp, bool fw_dflt) 11460 { 11461 int rc = 0; 11462 struct bnxt_link_info *link_info = &bp->link_info; 11463 11464 rc = bnxt_hwrm_phy_qcaps(bp); 11465 if (rc) { 11466 netdev_err(bp->dev, "Probe phy can't get phy capabilities (rc: %x)\n", 11467 rc); 11468 return rc; 11469 } 11470 if (!fw_dflt) 11471 return 0; 11472 11473 rc = bnxt_update_link(bp, false); 11474 if (rc) { 11475 netdev_err(bp->dev, "Probe phy can't update link (rc: %x)\n", 11476 rc); 11477 return rc; 11478 } 11479 11480 /* Older firmware does not have supported_auto_speeds, so assume 11481 * that all supported speeds can be autonegotiated. 11482 */ 11483 if (link_info->auto_link_speeds && !link_info->support_auto_speeds) 11484 link_info->support_auto_speeds = link_info->support_speeds; 11485 11486 bnxt_init_ethtool_link_settings(bp); 11487 return 0; 11488 } 11489 11490 static int bnxt_get_max_irq(struct pci_dev *pdev) 11491 { 11492 u16 ctrl; 11493 11494 if (!pdev->msix_cap) 11495 return 1; 11496 11497 pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &ctrl); 11498 return (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1; 11499 } 11500 11501 static void _bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx, 11502 int *max_cp) 11503 { 11504 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 11505 int max_ring_grps = 0, max_irq; 11506 11507 *max_tx = hw_resc->max_tx_rings; 11508 *max_rx = hw_resc->max_rx_rings; 11509 *max_cp = bnxt_get_max_func_cp_rings_for_en(bp); 11510 max_irq = min_t(int, bnxt_get_max_func_irqs(bp) - 11511 bnxt_get_ulp_msix_num(bp), 11512 hw_resc->max_stat_ctxs - bnxt_get_ulp_stat_ctxs(bp)); 11513 if (!(bp->flags & BNXT_FLAG_CHIP_P5)) 11514 *max_cp = min_t(int, *max_cp, max_irq); 11515 max_ring_grps = hw_resc->max_hw_ring_grps; 11516 if (BNXT_CHIP_TYPE_NITRO_A0(bp) && BNXT_PF(bp)) { 11517 *max_cp -= 1; 11518 *max_rx -= 2; 11519 } 11520 if (bp->flags & BNXT_FLAG_AGG_RINGS) 11521 *max_rx >>= 1; 11522 if (bp->flags & BNXT_FLAG_CHIP_P5) { 11523 bnxt_trim_rings(bp, max_rx, max_tx, *max_cp, false); 11524 /* On P5 chips, max_cp output param should be available NQs */ 11525 *max_cp = max_irq; 11526 } 11527 *max_rx = min_t(int, *max_rx, max_ring_grps); 11528 } 11529 11530 int bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx, bool shared) 11531 { 11532 int rx, tx, cp; 11533 11534 _bnxt_get_max_rings(bp, &rx, &tx, &cp); 11535 *max_rx = rx; 11536 *max_tx = tx; 11537 if (!rx || !tx || !cp) 11538 return -ENOMEM; 11539 11540 return bnxt_trim_rings(bp, max_rx, max_tx, cp, shared); 11541 } 11542 11543 static int bnxt_get_dflt_rings(struct bnxt *bp, int *max_rx, int *max_tx, 11544 bool shared) 11545 { 11546 int rc; 11547 11548 rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared); 11549 if (rc && (bp->flags & BNXT_FLAG_AGG_RINGS)) { 11550 /* Not enough rings, try disabling agg rings. */ 11551 bp->flags &= ~BNXT_FLAG_AGG_RINGS; 11552 rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared); 11553 if (rc) { 11554 /* set BNXT_FLAG_AGG_RINGS back for consistency */ 11555 bp->flags |= BNXT_FLAG_AGG_RINGS; 11556 return rc; 11557 } 11558 bp->flags |= BNXT_FLAG_NO_AGG_RINGS; 11559 bp->dev->hw_features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW); 11560 bp->dev->features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW); 11561 bnxt_set_ring_params(bp); 11562 } 11563 11564 if (bp->flags & BNXT_FLAG_ROCE_CAP) { 11565 int max_cp, max_stat, max_irq; 11566 11567 /* Reserve minimum resources for RoCE */ 11568 max_cp = bnxt_get_max_func_cp_rings(bp); 11569 max_stat = bnxt_get_max_func_stat_ctxs(bp); 11570 max_irq = bnxt_get_max_func_irqs(bp); 11571 if (max_cp <= BNXT_MIN_ROCE_CP_RINGS || 11572 max_irq <= BNXT_MIN_ROCE_CP_RINGS || 11573 max_stat <= BNXT_MIN_ROCE_STAT_CTXS) 11574 return 0; 11575 11576 max_cp -= BNXT_MIN_ROCE_CP_RINGS; 11577 max_irq -= BNXT_MIN_ROCE_CP_RINGS; 11578 max_stat -= BNXT_MIN_ROCE_STAT_CTXS; 11579 max_cp = min_t(int, max_cp, max_irq); 11580 max_cp = min_t(int, max_cp, max_stat); 11581 rc = bnxt_trim_rings(bp, max_rx, max_tx, max_cp, shared); 11582 if (rc) 11583 rc = 0; 11584 } 11585 return rc; 11586 } 11587 11588 /* In initial default shared ring setting, each shared ring must have a 11589 * RX/TX ring pair. 11590 */ 11591 static void bnxt_trim_dflt_sh_rings(struct bnxt *bp) 11592 { 11593 bp->cp_nr_rings = min_t(int, bp->tx_nr_rings_per_tc, bp->rx_nr_rings); 11594 bp->rx_nr_rings = bp->cp_nr_rings; 11595 bp->tx_nr_rings_per_tc = bp->cp_nr_rings; 11596 bp->tx_nr_rings = bp->tx_nr_rings_per_tc; 11597 } 11598 11599 static int bnxt_set_dflt_rings(struct bnxt *bp, bool sh) 11600 { 11601 int dflt_rings, max_rx_rings, max_tx_rings, rc; 11602 11603 if (!bnxt_can_reserve_rings(bp)) 11604 return 0; 11605 11606 if (sh) 11607 bp->flags |= BNXT_FLAG_SHARED_RINGS; 11608 dflt_rings = is_kdump_kernel() ? 1 : netif_get_num_default_rss_queues(); 11609 /* Reduce default rings on multi-port cards so that total default 11610 * rings do not exceed CPU count. 11611 */ 11612 if (bp->port_count > 1) { 11613 int max_rings = 11614 max_t(int, num_online_cpus() / bp->port_count, 1); 11615 11616 dflt_rings = min_t(int, dflt_rings, max_rings); 11617 } 11618 rc = bnxt_get_dflt_rings(bp, &max_rx_rings, &max_tx_rings, sh); 11619 if (rc) 11620 return rc; 11621 bp->rx_nr_rings = min_t(int, dflt_rings, max_rx_rings); 11622 bp->tx_nr_rings_per_tc = min_t(int, dflt_rings, max_tx_rings); 11623 if (sh) 11624 bnxt_trim_dflt_sh_rings(bp); 11625 else 11626 bp->cp_nr_rings = bp->tx_nr_rings_per_tc + bp->rx_nr_rings; 11627 bp->tx_nr_rings = bp->tx_nr_rings_per_tc; 11628 11629 rc = __bnxt_reserve_rings(bp); 11630 if (rc) 11631 netdev_warn(bp->dev, "Unable to reserve tx rings\n"); 11632 bp->tx_nr_rings_per_tc = bp->tx_nr_rings; 11633 if (sh) 11634 bnxt_trim_dflt_sh_rings(bp); 11635 11636 /* Rings may have been trimmed, re-reserve the trimmed rings. */ 11637 if (bnxt_need_reserve_rings(bp)) { 11638 rc = __bnxt_reserve_rings(bp); 11639 if (rc) 11640 netdev_warn(bp->dev, "2nd rings reservation failed.\n"); 11641 bp->tx_nr_rings_per_tc = bp->tx_nr_rings; 11642 } 11643 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) { 11644 bp->rx_nr_rings++; 11645 bp->cp_nr_rings++; 11646 } 11647 return rc; 11648 } 11649 11650 static int bnxt_init_dflt_ring_mode(struct bnxt *bp) 11651 { 11652 int rc; 11653 11654 if (bp->tx_nr_rings) 11655 return 0; 11656 11657 bnxt_ulp_irq_stop(bp); 11658 bnxt_clear_int_mode(bp); 11659 rc = bnxt_set_dflt_rings(bp, true); 11660 if (rc) { 11661 netdev_err(bp->dev, "Not enough rings available.\n"); 11662 goto init_dflt_ring_err; 11663 } 11664 rc = bnxt_init_int_mode(bp); 11665 if (rc) 11666 goto init_dflt_ring_err; 11667 11668 bp->tx_nr_rings_per_tc = bp->tx_nr_rings; 11669 if (bnxt_rfs_supported(bp) && bnxt_rfs_capable(bp)) { 11670 bp->flags |= BNXT_FLAG_RFS; 11671 bp->dev->features |= NETIF_F_NTUPLE; 11672 } 11673 init_dflt_ring_err: 11674 bnxt_ulp_irq_restart(bp, rc); 11675 return rc; 11676 } 11677 11678 int bnxt_restore_pf_fw_resources(struct bnxt *bp) 11679 { 11680 int rc; 11681 11682 ASSERT_RTNL(); 11683 bnxt_hwrm_func_qcaps(bp); 11684 11685 if (netif_running(bp->dev)) 11686 __bnxt_close_nic(bp, true, false); 11687 11688 bnxt_ulp_irq_stop(bp); 11689 bnxt_clear_int_mode(bp); 11690 rc = bnxt_init_int_mode(bp); 11691 bnxt_ulp_irq_restart(bp, rc); 11692 11693 if (netif_running(bp->dev)) { 11694 if (rc) 11695 dev_close(bp->dev); 11696 else 11697 rc = bnxt_open_nic(bp, true, false); 11698 } 11699 11700 return rc; 11701 } 11702 11703 static int bnxt_init_mac_addr(struct bnxt *bp) 11704 { 11705 int rc = 0; 11706 11707 if (BNXT_PF(bp)) { 11708 memcpy(bp->dev->dev_addr, bp->pf.mac_addr, ETH_ALEN); 11709 } else { 11710 #ifdef CONFIG_BNXT_SRIOV 11711 struct bnxt_vf_info *vf = &bp->vf; 11712 bool strict_approval = true; 11713 11714 if (is_valid_ether_addr(vf->mac_addr)) { 11715 /* overwrite netdev dev_addr with admin VF MAC */ 11716 memcpy(bp->dev->dev_addr, vf->mac_addr, ETH_ALEN); 11717 /* Older PF driver or firmware may not approve this 11718 * correctly. 11719 */ 11720 strict_approval = false; 11721 } else { 11722 eth_hw_addr_random(bp->dev); 11723 } 11724 rc = bnxt_approve_mac(bp, bp->dev->dev_addr, strict_approval); 11725 #endif 11726 } 11727 return rc; 11728 } 11729 11730 static int bnxt_pcie_dsn_get(struct bnxt *bp, u8 dsn[]) 11731 { 11732 struct pci_dev *pdev = bp->pdev; 11733 u64 qword; 11734 11735 qword = pci_get_dsn(pdev); 11736 if (!qword) { 11737 netdev_info(bp->dev, "Unable to read adapter's DSN\n"); 11738 return -EOPNOTSUPP; 11739 } 11740 11741 put_unaligned_le64(qword, dsn); 11742 11743 bp->flags |= BNXT_FLAG_DSN_VALID; 11744 return 0; 11745 } 11746 11747 static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 11748 { 11749 struct net_device *dev; 11750 struct bnxt *bp; 11751 int rc, max_irqs; 11752 11753 if (pci_is_bridge(pdev)) 11754 return -ENODEV; 11755 11756 /* Clear any pending DMA transactions from crash kernel 11757 * while loading driver in capture kernel. 11758 */ 11759 if (is_kdump_kernel()) { 11760 pci_clear_master(pdev); 11761 pcie_flr(pdev); 11762 } 11763 11764 max_irqs = bnxt_get_max_irq(pdev); 11765 dev = alloc_etherdev_mq(sizeof(*bp), max_irqs); 11766 if (!dev) 11767 return -ENOMEM; 11768 11769 bp = netdev_priv(dev); 11770 bnxt_set_max_func_irqs(bp, max_irqs); 11771 11772 if (bnxt_vf_pciid(ent->driver_data)) 11773 bp->flags |= BNXT_FLAG_VF; 11774 11775 if (pdev->msix_cap) 11776 bp->flags |= BNXT_FLAG_MSIX_CAP; 11777 11778 rc = bnxt_init_board(pdev, dev); 11779 if (rc < 0) 11780 goto init_err_free; 11781 11782 dev->netdev_ops = &bnxt_netdev_ops; 11783 dev->watchdog_timeo = BNXT_TX_TIMEOUT; 11784 dev->ethtool_ops = &bnxt_ethtool_ops; 11785 pci_set_drvdata(pdev, dev); 11786 11787 rc = bnxt_alloc_hwrm_resources(bp); 11788 if (rc) 11789 goto init_err_pci_clean; 11790 11791 mutex_init(&bp->hwrm_cmd_lock); 11792 mutex_init(&bp->link_lock); 11793 11794 rc = bnxt_fw_init_one_p1(bp); 11795 if (rc) 11796 goto init_err_pci_clean; 11797 11798 if (BNXT_CHIP_P5(bp)) 11799 bp->flags |= BNXT_FLAG_CHIP_P5; 11800 11801 rc = bnxt_fw_init_one_p2(bp); 11802 if (rc) 11803 goto init_err_pci_clean; 11804 11805 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG | 11806 NETIF_F_TSO | NETIF_F_TSO6 | 11807 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE | 11808 NETIF_F_GSO_IPXIP4 | 11809 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM | 11810 NETIF_F_GSO_PARTIAL | NETIF_F_RXHASH | 11811 NETIF_F_RXCSUM | NETIF_F_GRO; 11812 11813 if (BNXT_SUPPORTS_TPA(bp)) 11814 dev->hw_features |= NETIF_F_LRO; 11815 11816 dev->hw_enc_features = 11817 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG | 11818 NETIF_F_TSO | NETIF_F_TSO6 | 11819 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE | 11820 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM | 11821 NETIF_F_GSO_IPXIP4 | NETIF_F_GSO_PARTIAL; 11822 dev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM | 11823 NETIF_F_GSO_GRE_CSUM; 11824 dev->vlan_features = dev->hw_features | NETIF_F_HIGHDMA; 11825 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX | 11826 NETIF_F_HW_VLAN_STAG_RX | NETIF_F_HW_VLAN_STAG_TX; 11827 if (BNXT_SUPPORTS_TPA(bp)) 11828 dev->hw_features |= NETIF_F_GRO_HW; 11829 dev->features |= dev->hw_features | NETIF_F_HIGHDMA; 11830 if (dev->features & NETIF_F_GRO_HW) 11831 dev->features &= ~NETIF_F_LRO; 11832 dev->priv_flags |= IFF_UNICAST_FLT; 11833 11834 #ifdef CONFIG_BNXT_SRIOV 11835 init_waitqueue_head(&bp->sriov_cfg_wait); 11836 mutex_init(&bp->sriov_lock); 11837 #endif 11838 if (BNXT_SUPPORTS_TPA(bp)) { 11839 bp->gro_func = bnxt_gro_func_5730x; 11840 if (BNXT_CHIP_P4(bp)) 11841 bp->gro_func = bnxt_gro_func_5731x; 11842 else if (BNXT_CHIP_P5(bp)) 11843 bp->gro_func = bnxt_gro_func_5750x; 11844 } 11845 if (!BNXT_CHIP_P4_PLUS(bp)) 11846 bp->flags |= BNXT_FLAG_DOUBLE_DB; 11847 11848 bp->ulp_probe = bnxt_ulp_probe; 11849 11850 rc = bnxt_init_mac_addr(bp); 11851 if (rc) { 11852 dev_err(&pdev->dev, "Unable to initialize mac address.\n"); 11853 rc = -EADDRNOTAVAIL; 11854 goto init_err_pci_clean; 11855 } 11856 11857 if (BNXT_PF(bp)) { 11858 /* Read the adapter's DSN to use as the eswitch switch_id */ 11859 rc = bnxt_pcie_dsn_get(bp, bp->dsn); 11860 } 11861 11862 /* MTU range: 60 - FW defined max */ 11863 dev->min_mtu = ETH_ZLEN; 11864 dev->max_mtu = bp->max_mtu; 11865 11866 rc = bnxt_probe_phy(bp, true); 11867 if (rc) 11868 goto init_err_pci_clean; 11869 11870 bnxt_set_rx_skb_mode(bp, false); 11871 bnxt_set_tpa_flags(bp); 11872 bnxt_set_ring_params(bp); 11873 rc = bnxt_set_dflt_rings(bp, true); 11874 if (rc) { 11875 netdev_err(bp->dev, "Not enough rings available.\n"); 11876 rc = -ENOMEM; 11877 goto init_err_pci_clean; 11878 } 11879 11880 bnxt_fw_init_one_p3(bp); 11881 11882 if (dev->hw_features & NETIF_F_HW_VLAN_CTAG_RX) 11883 bp->flags |= BNXT_FLAG_STRIP_VLAN; 11884 11885 rc = bnxt_init_int_mode(bp); 11886 if (rc) 11887 goto init_err_pci_clean; 11888 11889 /* No TC has been set yet and rings may have been trimmed due to 11890 * limited MSIX, so we re-initialize the TX rings per TC. 11891 */ 11892 bp->tx_nr_rings_per_tc = bp->tx_nr_rings; 11893 11894 if (BNXT_PF(bp)) { 11895 if (!bnxt_pf_wq) { 11896 bnxt_pf_wq = 11897 create_singlethread_workqueue("bnxt_pf_wq"); 11898 if (!bnxt_pf_wq) { 11899 dev_err(&pdev->dev, "Unable to create workqueue.\n"); 11900 goto init_err_pci_clean; 11901 } 11902 } 11903 bnxt_init_tc(bp); 11904 } 11905 11906 bnxt_dl_register(bp); 11907 11908 rc = register_netdev(dev); 11909 if (rc) 11910 goto init_err_cleanup; 11911 11912 if (BNXT_PF(bp)) 11913 devlink_port_type_eth_set(&bp->dl_port, bp->dev); 11914 bnxt_dl_fw_reporters_create(bp); 11915 11916 netdev_info(dev, "%s found at mem %lx, node addr %pM\n", 11917 board_info[ent->driver_data].name, 11918 (long)pci_resource_start(pdev, 0), dev->dev_addr); 11919 pcie_print_link_status(pdev); 11920 11921 return 0; 11922 11923 init_err_cleanup: 11924 bnxt_dl_unregister(bp); 11925 bnxt_shutdown_tc(bp); 11926 bnxt_clear_int_mode(bp); 11927 11928 init_err_pci_clean: 11929 bnxt_hwrm_func_drv_unrgtr(bp); 11930 bnxt_free_hwrm_short_cmd_req(bp); 11931 bnxt_free_hwrm_resources(bp); 11932 bnxt_free_ctx_mem(bp); 11933 kfree(bp->ctx); 11934 bp->ctx = NULL; 11935 kfree(bp->fw_health); 11936 bp->fw_health = NULL; 11937 bnxt_cleanup_pci(bp); 11938 11939 init_err_free: 11940 free_netdev(dev); 11941 return rc; 11942 } 11943 11944 static void bnxt_shutdown(struct pci_dev *pdev) 11945 { 11946 struct net_device *dev = pci_get_drvdata(pdev); 11947 struct bnxt *bp; 11948 11949 if (!dev) 11950 return; 11951 11952 rtnl_lock(); 11953 bp = netdev_priv(dev); 11954 if (!bp) 11955 goto shutdown_exit; 11956 11957 if (netif_running(dev)) 11958 dev_close(dev); 11959 11960 bnxt_ulp_shutdown(bp); 11961 bnxt_clear_int_mode(bp); 11962 pci_disable_device(pdev); 11963 11964 if (system_state == SYSTEM_POWER_OFF) { 11965 pci_wake_from_d3(pdev, bp->wol); 11966 pci_set_power_state(pdev, PCI_D3hot); 11967 } 11968 11969 shutdown_exit: 11970 rtnl_unlock(); 11971 } 11972 11973 #ifdef CONFIG_PM_SLEEP 11974 static int bnxt_suspend(struct device *device) 11975 { 11976 struct net_device *dev = dev_get_drvdata(device); 11977 struct bnxt *bp = netdev_priv(dev); 11978 int rc = 0; 11979 11980 rtnl_lock(); 11981 bnxt_ulp_stop(bp); 11982 if (netif_running(dev)) { 11983 netif_device_detach(dev); 11984 rc = bnxt_close(dev); 11985 } 11986 bnxt_hwrm_func_drv_unrgtr(bp); 11987 pci_disable_device(bp->pdev); 11988 bnxt_free_ctx_mem(bp); 11989 kfree(bp->ctx); 11990 bp->ctx = NULL; 11991 rtnl_unlock(); 11992 return rc; 11993 } 11994 11995 static int bnxt_resume(struct device *device) 11996 { 11997 struct net_device *dev = dev_get_drvdata(device); 11998 struct bnxt *bp = netdev_priv(dev); 11999 int rc = 0; 12000 12001 rtnl_lock(); 12002 rc = pci_enable_device(bp->pdev); 12003 if (rc) { 12004 netdev_err(dev, "Cannot re-enable PCI device during resume, err = %d\n", 12005 rc); 12006 goto resume_exit; 12007 } 12008 pci_set_master(bp->pdev); 12009 if (bnxt_hwrm_ver_get(bp)) { 12010 rc = -ENODEV; 12011 goto resume_exit; 12012 } 12013 rc = bnxt_hwrm_func_reset(bp); 12014 if (rc) { 12015 rc = -EBUSY; 12016 goto resume_exit; 12017 } 12018 12019 if (bnxt_hwrm_queue_qportcfg(bp)) { 12020 rc = -ENODEV; 12021 goto resume_exit; 12022 } 12023 12024 if (bp->hwrm_spec_code >= 0x10803) { 12025 if (bnxt_alloc_ctx_mem(bp)) { 12026 rc = -ENODEV; 12027 goto resume_exit; 12028 } 12029 } 12030 if (BNXT_NEW_RM(bp)) 12031 bnxt_hwrm_func_resc_qcaps(bp, false); 12032 12033 if (bnxt_hwrm_func_drv_rgtr(bp, NULL, 0, false)) { 12034 rc = -ENODEV; 12035 goto resume_exit; 12036 } 12037 12038 bnxt_get_wol_settings(bp); 12039 if (netif_running(dev)) { 12040 rc = bnxt_open(dev); 12041 if (!rc) 12042 netif_device_attach(dev); 12043 } 12044 12045 resume_exit: 12046 bnxt_ulp_start(bp, rc); 12047 rtnl_unlock(); 12048 return rc; 12049 } 12050 12051 static SIMPLE_DEV_PM_OPS(bnxt_pm_ops, bnxt_suspend, bnxt_resume); 12052 #define BNXT_PM_OPS (&bnxt_pm_ops) 12053 12054 #else 12055 12056 #define BNXT_PM_OPS NULL 12057 12058 #endif /* CONFIG_PM_SLEEP */ 12059 12060 /** 12061 * bnxt_io_error_detected - called when PCI error is detected 12062 * @pdev: Pointer to PCI device 12063 * @state: The current pci connection state 12064 * 12065 * This function is called after a PCI bus error affecting 12066 * this device has been detected. 12067 */ 12068 static pci_ers_result_t bnxt_io_error_detected(struct pci_dev *pdev, 12069 pci_channel_state_t state) 12070 { 12071 struct net_device *netdev = pci_get_drvdata(pdev); 12072 struct bnxt *bp = netdev_priv(netdev); 12073 12074 netdev_info(netdev, "PCI I/O error detected\n"); 12075 12076 rtnl_lock(); 12077 netif_device_detach(netdev); 12078 12079 bnxt_ulp_stop(bp); 12080 12081 if (state == pci_channel_io_perm_failure) { 12082 rtnl_unlock(); 12083 return PCI_ERS_RESULT_DISCONNECT; 12084 } 12085 12086 if (netif_running(netdev)) 12087 bnxt_close(netdev); 12088 12089 pci_disable_device(pdev); 12090 rtnl_unlock(); 12091 12092 /* Request a slot slot reset. */ 12093 return PCI_ERS_RESULT_NEED_RESET; 12094 } 12095 12096 /** 12097 * bnxt_io_slot_reset - called after the pci bus has been reset. 12098 * @pdev: Pointer to PCI device 12099 * 12100 * Restart the card from scratch, as if from a cold-boot. 12101 * At this point, the card has exprienced a hard reset, 12102 * followed by fixups by BIOS, and has its config space 12103 * set up identically to what it was at cold boot. 12104 */ 12105 static pci_ers_result_t bnxt_io_slot_reset(struct pci_dev *pdev) 12106 { 12107 struct net_device *netdev = pci_get_drvdata(pdev); 12108 struct bnxt *bp = netdev_priv(netdev); 12109 int err = 0; 12110 pci_ers_result_t result = PCI_ERS_RESULT_DISCONNECT; 12111 12112 netdev_info(bp->dev, "PCI Slot Reset\n"); 12113 12114 rtnl_lock(); 12115 12116 if (pci_enable_device(pdev)) { 12117 dev_err(&pdev->dev, 12118 "Cannot re-enable PCI device after reset.\n"); 12119 } else { 12120 pci_set_master(pdev); 12121 12122 err = bnxt_hwrm_func_reset(bp); 12123 if (!err && netif_running(netdev)) 12124 err = bnxt_open(netdev); 12125 12126 if (!err) 12127 result = PCI_ERS_RESULT_RECOVERED; 12128 bnxt_ulp_start(bp, err); 12129 } 12130 12131 if (result != PCI_ERS_RESULT_RECOVERED && netif_running(netdev)) 12132 dev_close(netdev); 12133 12134 rtnl_unlock(); 12135 12136 return PCI_ERS_RESULT_RECOVERED; 12137 } 12138 12139 /** 12140 * bnxt_io_resume - called when traffic can start flowing again. 12141 * @pdev: Pointer to PCI device 12142 * 12143 * This callback is called when the error recovery driver tells 12144 * us that its OK to resume normal operation. 12145 */ 12146 static void bnxt_io_resume(struct pci_dev *pdev) 12147 { 12148 struct net_device *netdev = pci_get_drvdata(pdev); 12149 12150 rtnl_lock(); 12151 12152 netif_device_attach(netdev); 12153 12154 rtnl_unlock(); 12155 } 12156 12157 static const struct pci_error_handlers bnxt_err_handler = { 12158 .error_detected = bnxt_io_error_detected, 12159 .slot_reset = bnxt_io_slot_reset, 12160 .resume = bnxt_io_resume 12161 }; 12162 12163 static struct pci_driver bnxt_pci_driver = { 12164 .name = DRV_MODULE_NAME, 12165 .id_table = bnxt_pci_tbl, 12166 .probe = bnxt_init_one, 12167 .remove = bnxt_remove_one, 12168 .shutdown = bnxt_shutdown, 12169 .driver.pm = BNXT_PM_OPS, 12170 .err_handler = &bnxt_err_handler, 12171 #if defined(CONFIG_BNXT_SRIOV) 12172 .sriov_configure = bnxt_sriov_configure, 12173 #endif 12174 }; 12175 12176 static int __init bnxt_init(void) 12177 { 12178 bnxt_debug_init(); 12179 return pci_register_driver(&bnxt_pci_driver); 12180 } 12181 12182 static void __exit bnxt_exit(void) 12183 { 12184 pci_unregister_driver(&bnxt_pci_driver); 12185 if (bnxt_pf_wq) 12186 destroy_workqueue(bnxt_pf_wq); 12187 bnxt_debug_exit(); 12188 } 12189 12190 module_init(bnxt_init); 12191 module_exit(bnxt_exit); 12192