1 /* Broadcom NetXtreme-C/E network driver. 2 * 3 * Copyright (c) 2014-2016 Broadcom Corporation 4 * Copyright (c) 2016-2019 Broadcom Limited 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation. 9 */ 10 11 #include <linux/module.h> 12 13 #include <linux/stringify.h> 14 #include <linux/kernel.h> 15 #include <linux/timer.h> 16 #include <linux/errno.h> 17 #include <linux/ioport.h> 18 #include <linux/slab.h> 19 #include <linux/vmalloc.h> 20 #include <linux/interrupt.h> 21 #include <linux/pci.h> 22 #include <linux/netdevice.h> 23 #include <linux/etherdevice.h> 24 #include <linux/skbuff.h> 25 #include <linux/dma-mapping.h> 26 #include <linux/bitops.h> 27 #include <linux/io.h> 28 #include <linux/irq.h> 29 #include <linux/delay.h> 30 #include <asm/byteorder.h> 31 #include <asm/page.h> 32 #include <linux/time.h> 33 #include <linux/mii.h> 34 #include <linux/mdio.h> 35 #include <linux/if.h> 36 #include <linux/if_vlan.h> 37 #include <linux/if_bridge.h> 38 #include <linux/rtc.h> 39 #include <linux/bpf.h> 40 #include <net/ip.h> 41 #include <net/tcp.h> 42 #include <net/udp.h> 43 #include <net/checksum.h> 44 #include <net/ip6_checksum.h> 45 #include <net/udp_tunnel.h> 46 #include <linux/workqueue.h> 47 #include <linux/prefetch.h> 48 #include <linux/cache.h> 49 #include <linux/log2.h> 50 #include <linux/aer.h> 51 #include <linux/bitmap.h> 52 #include <linux/cpu_rmap.h> 53 #include <linux/cpumask.h> 54 #include <net/pkt_cls.h> 55 #include <linux/hwmon.h> 56 #include <linux/hwmon-sysfs.h> 57 #include <net/page_pool.h> 58 59 #include "bnxt_hsi.h" 60 #include "bnxt.h" 61 #include "bnxt_ulp.h" 62 #include "bnxt_sriov.h" 63 #include "bnxt_ethtool.h" 64 #include "bnxt_dcb.h" 65 #include "bnxt_xdp.h" 66 #include "bnxt_vfr.h" 67 #include "bnxt_tc.h" 68 #include "bnxt_devlink.h" 69 #include "bnxt_debugfs.h" 70 71 #define BNXT_TX_TIMEOUT (5 * HZ) 72 73 MODULE_LICENSE("GPL"); 74 MODULE_DESCRIPTION("Broadcom BCM573xx network driver"); 75 76 #define BNXT_RX_OFFSET (NET_SKB_PAD + NET_IP_ALIGN) 77 #define BNXT_RX_DMA_OFFSET NET_SKB_PAD 78 #define BNXT_RX_COPY_THRESH 256 79 80 #define BNXT_TX_PUSH_THRESH 164 81 82 enum board_idx { 83 BCM57301, 84 BCM57302, 85 BCM57304, 86 BCM57417_NPAR, 87 BCM58700, 88 BCM57311, 89 BCM57312, 90 BCM57402, 91 BCM57404, 92 BCM57406, 93 BCM57402_NPAR, 94 BCM57407, 95 BCM57412, 96 BCM57414, 97 BCM57416, 98 BCM57417, 99 BCM57412_NPAR, 100 BCM57314, 101 BCM57417_SFP, 102 BCM57416_SFP, 103 BCM57404_NPAR, 104 BCM57406_NPAR, 105 BCM57407_SFP, 106 BCM57407_NPAR, 107 BCM57414_NPAR, 108 BCM57416_NPAR, 109 BCM57452, 110 BCM57454, 111 BCM5745x_NPAR, 112 BCM57508, 113 BCM57504, 114 BCM57502, 115 BCM57508_NPAR, 116 BCM57504_NPAR, 117 BCM57502_NPAR, 118 BCM58802, 119 BCM58804, 120 BCM58808, 121 NETXTREME_E_VF, 122 NETXTREME_C_VF, 123 NETXTREME_S_VF, 124 NETXTREME_E_P5_VF, 125 }; 126 127 /* indexed by enum above */ 128 static const struct { 129 char *name; 130 } board_info[] = { 131 [BCM57301] = { "Broadcom BCM57301 NetXtreme-C 10Gb Ethernet" }, 132 [BCM57302] = { "Broadcom BCM57302 NetXtreme-C 10Gb/25Gb Ethernet" }, 133 [BCM57304] = { "Broadcom BCM57304 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" }, 134 [BCM57417_NPAR] = { "Broadcom BCM57417 NetXtreme-E Ethernet Partition" }, 135 [BCM58700] = { "Broadcom BCM58700 Nitro 1Gb/2.5Gb/10Gb Ethernet" }, 136 [BCM57311] = { "Broadcom BCM57311 NetXtreme-C 10Gb Ethernet" }, 137 [BCM57312] = { "Broadcom BCM57312 NetXtreme-C 10Gb/25Gb Ethernet" }, 138 [BCM57402] = { "Broadcom BCM57402 NetXtreme-E 10Gb Ethernet" }, 139 [BCM57404] = { "Broadcom BCM57404 NetXtreme-E 10Gb/25Gb Ethernet" }, 140 [BCM57406] = { "Broadcom BCM57406 NetXtreme-E 10GBase-T Ethernet" }, 141 [BCM57402_NPAR] = { "Broadcom BCM57402 NetXtreme-E Ethernet Partition" }, 142 [BCM57407] = { "Broadcom BCM57407 NetXtreme-E 10GBase-T Ethernet" }, 143 [BCM57412] = { "Broadcom BCM57412 NetXtreme-E 10Gb Ethernet" }, 144 [BCM57414] = { "Broadcom BCM57414 NetXtreme-E 10Gb/25Gb Ethernet" }, 145 [BCM57416] = { "Broadcom BCM57416 NetXtreme-E 10GBase-T Ethernet" }, 146 [BCM57417] = { "Broadcom BCM57417 NetXtreme-E 10GBase-T Ethernet" }, 147 [BCM57412_NPAR] = { "Broadcom BCM57412 NetXtreme-E Ethernet Partition" }, 148 [BCM57314] = { "Broadcom BCM57314 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" }, 149 [BCM57417_SFP] = { "Broadcom BCM57417 NetXtreme-E 10Gb/25Gb Ethernet" }, 150 [BCM57416_SFP] = { "Broadcom BCM57416 NetXtreme-E 10Gb Ethernet" }, 151 [BCM57404_NPAR] = { "Broadcom BCM57404 NetXtreme-E Ethernet Partition" }, 152 [BCM57406_NPAR] = { "Broadcom BCM57406 NetXtreme-E Ethernet Partition" }, 153 [BCM57407_SFP] = { "Broadcom BCM57407 NetXtreme-E 25Gb Ethernet" }, 154 [BCM57407_NPAR] = { "Broadcom BCM57407 NetXtreme-E Ethernet Partition" }, 155 [BCM57414_NPAR] = { "Broadcom BCM57414 NetXtreme-E Ethernet Partition" }, 156 [BCM57416_NPAR] = { "Broadcom BCM57416 NetXtreme-E Ethernet Partition" }, 157 [BCM57452] = { "Broadcom BCM57452 NetXtreme-E 10Gb/25Gb/40Gb/50Gb Ethernet" }, 158 [BCM57454] = { "Broadcom BCM57454 NetXtreme-E 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" }, 159 [BCM5745x_NPAR] = { "Broadcom BCM5745x NetXtreme-E Ethernet Partition" }, 160 [BCM57508] = { "Broadcom BCM57508 NetXtreme-E 10Gb/25Gb/50Gb/100Gb/200Gb Ethernet" }, 161 [BCM57504] = { "Broadcom BCM57504 NetXtreme-E 10Gb/25Gb/50Gb/100Gb/200Gb Ethernet" }, 162 [BCM57502] = { "Broadcom BCM57502 NetXtreme-E 10Gb/25Gb/50Gb Ethernet" }, 163 [BCM57508_NPAR] = { "Broadcom BCM57508 NetXtreme-E Ethernet Partition" }, 164 [BCM57504_NPAR] = { "Broadcom BCM57504 NetXtreme-E Ethernet Partition" }, 165 [BCM57502_NPAR] = { "Broadcom BCM57502 NetXtreme-E Ethernet Partition" }, 166 [BCM58802] = { "Broadcom BCM58802 NetXtreme-S 10Gb/25Gb/40Gb/50Gb Ethernet" }, 167 [BCM58804] = { "Broadcom BCM58804 NetXtreme-S 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" }, 168 [BCM58808] = { "Broadcom BCM58808 NetXtreme-S 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" }, 169 [NETXTREME_E_VF] = { "Broadcom NetXtreme-E Ethernet Virtual Function" }, 170 [NETXTREME_C_VF] = { "Broadcom NetXtreme-C Ethernet Virtual Function" }, 171 [NETXTREME_S_VF] = { "Broadcom NetXtreme-S Ethernet Virtual Function" }, 172 [NETXTREME_E_P5_VF] = { "Broadcom BCM5750X NetXtreme-E Ethernet Virtual Function" }, 173 }; 174 175 static const struct pci_device_id bnxt_pci_tbl[] = { 176 { PCI_VDEVICE(BROADCOM, 0x1604), .driver_data = BCM5745x_NPAR }, 177 { PCI_VDEVICE(BROADCOM, 0x1605), .driver_data = BCM5745x_NPAR }, 178 { PCI_VDEVICE(BROADCOM, 0x1614), .driver_data = BCM57454 }, 179 { PCI_VDEVICE(BROADCOM, 0x16c0), .driver_data = BCM57417_NPAR }, 180 { PCI_VDEVICE(BROADCOM, 0x16c8), .driver_data = BCM57301 }, 181 { PCI_VDEVICE(BROADCOM, 0x16c9), .driver_data = BCM57302 }, 182 { PCI_VDEVICE(BROADCOM, 0x16ca), .driver_data = BCM57304 }, 183 { PCI_VDEVICE(BROADCOM, 0x16cc), .driver_data = BCM57417_NPAR }, 184 { PCI_VDEVICE(BROADCOM, 0x16cd), .driver_data = BCM58700 }, 185 { PCI_VDEVICE(BROADCOM, 0x16ce), .driver_data = BCM57311 }, 186 { PCI_VDEVICE(BROADCOM, 0x16cf), .driver_data = BCM57312 }, 187 { PCI_VDEVICE(BROADCOM, 0x16d0), .driver_data = BCM57402 }, 188 { PCI_VDEVICE(BROADCOM, 0x16d1), .driver_data = BCM57404 }, 189 { PCI_VDEVICE(BROADCOM, 0x16d2), .driver_data = BCM57406 }, 190 { PCI_VDEVICE(BROADCOM, 0x16d4), .driver_data = BCM57402_NPAR }, 191 { PCI_VDEVICE(BROADCOM, 0x16d5), .driver_data = BCM57407 }, 192 { PCI_VDEVICE(BROADCOM, 0x16d6), .driver_data = BCM57412 }, 193 { PCI_VDEVICE(BROADCOM, 0x16d7), .driver_data = BCM57414 }, 194 { PCI_VDEVICE(BROADCOM, 0x16d8), .driver_data = BCM57416 }, 195 { PCI_VDEVICE(BROADCOM, 0x16d9), .driver_data = BCM57417 }, 196 { PCI_VDEVICE(BROADCOM, 0x16de), .driver_data = BCM57412_NPAR }, 197 { PCI_VDEVICE(BROADCOM, 0x16df), .driver_data = BCM57314 }, 198 { PCI_VDEVICE(BROADCOM, 0x16e2), .driver_data = BCM57417_SFP }, 199 { PCI_VDEVICE(BROADCOM, 0x16e3), .driver_data = BCM57416_SFP }, 200 { PCI_VDEVICE(BROADCOM, 0x16e7), .driver_data = BCM57404_NPAR }, 201 { PCI_VDEVICE(BROADCOM, 0x16e8), .driver_data = BCM57406_NPAR }, 202 { PCI_VDEVICE(BROADCOM, 0x16e9), .driver_data = BCM57407_SFP }, 203 { PCI_VDEVICE(BROADCOM, 0x16ea), .driver_data = BCM57407_NPAR }, 204 { PCI_VDEVICE(BROADCOM, 0x16eb), .driver_data = BCM57412_NPAR }, 205 { PCI_VDEVICE(BROADCOM, 0x16ec), .driver_data = BCM57414_NPAR }, 206 { PCI_VDEVICE(BROADCOM, 0x16ed), .driver_data = BCM57414_NPAR }, 207 { PCI_VDEVICE(BROADCOM, 0x16ee), .driver_data = BCM57416_NPAR }, 208 { PCI_VDEVICE(BROADCOM, 0x16ef), .driver_data = BCM57416_NPAR }, 209 { PCI_VDEVICE(BROADCOM, 0x16f0), .driver_data = BCM58808 }, 210 { PCI_VDEVICE(BROADCOM, 0x16f1), .driver_data = BCM57452 }, 211 { PCI_VDEVICE(BROADCOM, 0x1750), .driver_data = BCM57508 }, 212 { PCI_VDEVICE(BROADCOM, 0x1751), .driver_data = BCM57504 }, 213 { PCI_VDEVICE(BROADCOM, 0x1752), .driver_data = BCM57502 }, 214 { PCI_VDEVICE(BROADCOM, 0x1800), .driver_data = BCM57508_NPAR }, 215 { PCI_VDEVICE(BROADCOM, 0x1801), .driver_data = BCM57504_NPAR }, 216 { PCI_VDEVICE(BROADCOM, 0x1802), .driver_data = BCM57502_NPAR }, 217 { PCI_VDEVICE(BROADCOM, 0x1803), .driver_data = BCM57508_NPAR }, 218 { PCI_VDEVICE(BROADCOM, 0x1804), .driver_data = BCM57504_NPAR }, 219 { PCI_VDEVICE(BROADCOM, 0x1805), .driver_data = BCM57502_NPAR }, 220 { PCI_VDEVICE(BROADCOM, 0xd802), .driver_data = BCM58802 }, 221 { PCI_VDEVICE(BROADCOM, 0xd804), .driver_data = BCM58804 }, 222 #ifdef CONFIG_BNXT_SRIOV 223 { PCI_VDEVICE(BROADCOM, 0x1606), .driver_data = NETXTREME_E_VF }, 224 { PCI_VDEVICE(BROADCOM, 0x1609), .driver_data = NETXTREME_E_VF }, 225 { PCI_VDEVICE(BROADCOM, 0x16c1), .driver_data = NETXTREME_E_VF }, 226 { PCI_VDEVICE(BROADCOM, 0x16cb), .driver_data = NETXTREME_C_VF }, 227 { PCI_VDEVICE(BROADCOM, 0x16d3), .driver_data = NETXTREME_E_VF }, 228 { PCI_VDEVICE(BROADCOM, 0x16dc), .driver_data = NETXTREME_E_VF }, 229 { PCI_VDEVICE(BROADCOM, 0x16e1), .driver_data = NETXTREME_C_VF }, 230 { PCI_VDEVICE(BROADCOM, 0x16e5), .driver_data = NETXTREME_C_VF }, 231 { PCI_VDEVICE(BROADCOM, 0x1806), .driver_data = NETXTREME_E_P5_VF }, 232 { PCI_VDEVICE(BROADCOM, 0x1807), .driver_data = NETXTREME_E_P5_VF }, 233 { PCI_VDEVICE(BROADCOM, 0xd800), .driver_data = NETXTREME_S_VF }, 234 #endif 235 { 0 } 236 }; 237 238 MODULE_DEVICE_TABLE(pci, bnxt_pci_tbl); 239 240 static const u16 bnxt_vf_req_snif[] = { 241 HWRM_FUNC_CFG, 242 HWRM_FUNC_VF_CFG, 243 HWRM_PORT_PHY_QCFG, 244 HWRM_CFA_L2_FILTER_ALLOC, 245 }; 246 247 static const u16 bnxt_async_events_arr[] = { 248 ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE, 249 ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE, 250 ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD, 251 ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED, 252 ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE, 253 ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE, 254 ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE, 255 ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY, 256 ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY, 257 }; 258 259 static struct workqueue_struct *bnxt_pf_wq; 260 261 static bool bnxt_vf_pciid(enum board_idx idx) 262 { 263 return (idx == NETXTREME_C_VF || idx == NETXTREME_E_VF || 264 idx == NETXTREME_S_VF || idx == NETXTREME_E_P5_VF); 265 } 266 267 #define DB_CP_REARM_FLAGS (DB_KEY_CP | DB_IDX_VALID) 268 #define DB_CP_FLAGS (DB_KEY_CP | DB_IDX_VALID | DB_IRQ_DIS) 269 #define DB_CP_IRQ_DIS_FLAGS (DB_KEY_CP | DB_IRQ_DIS) 270 271 #define BNXT_CP_DB_IRQ_DIS(db) \ 272 writel(DB_CP_IRQ_DIS_FLAGS, db) 273 274 #define BNXT_DB_CQ(db, idx) \ 275 writel(DB_CP_FLAGS | RING_CMP(idx), (db)->doorbell) 276 277 #define BNXT_DB_NQ_P5(db, idx) \ 278 writeq((db)->db_key64 | DBR_TYPE_NQ | RING_CMP(idx), (db)->doorbell) 279 280 #define BNXT_DB_CQ_ARM(db, idx) \ 281 writel(DB_CP_REARM_FLAGS | RING_CMP(idx), (db)->doorbell) 282 283 #define BNXT_DB_NQ_ARM_P5(db, idx) \ 284 writeq((db)->db_key64 | DBR_TYPE_NQ_ARM | RING_CMP(idx), (db)->doorbell) 285 286 static void bnxt_db_nq(struct bnxt *bp, struct bnxt_db_info *db, u32 idx) 287 { 288 if (bp->flags & BNXT_FLAG_CHIP_P5) 289 BNXT_DB_NQ_P5(db, idx); 290 else 291 BNXT_DB_CQ(db, idx); 292 } 293 294 static void bnxt_db_nq_arm(struct bnxt *bp, struct bnxt_db_info *db, u32 idx) 295 { 296 if (bp->flags & BNXT_FLAG_CHIP_P5) 297 BNXT_DB_NQ_ARM_P5(db, idx); 298 else 299 BNXT_DB_CQ_ARM(db, idx); 300 } 301 302 static void bnxt_db_cq(struct bnxt *bp, struct bnxt_db_info *db, u32 idx) 303 { 304 if (bp->flags & BNXT_FLAG_CHIP_P5) 305 writeq(db->db_key64 | DBR_TYPE_CQ_ARMALL | RING_CMP(idx), 306 db->doorbell); 307 else 308 BNXT_DB_CQ(db, idx); 309 } 310 311 const u16 bnxt_lhint_arr[] = { 312 TX_BD_FLAGS_LHINT_512_AND_SMALLER, 313 TX_BD_FLAGS_LHINT_512_TO_1023, 314 TX_BD_FLAGS_LHINT_1024_TO_2047, 315 TX_BD_FLAGS_LHINT_1024_TO_2047, 316 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 317 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 318 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 319 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 320 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 321 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 322 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 323 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 324 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 325 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 326 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 327 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 328 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 329 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 330 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 331 }; 332 333 static u16 bnxt_xmit_get_cfa_action(struct sk_buff *skb) 334 { 335 struct metadata_dst *md_dst = skb_metadata_dst(skb); 336 337 if (!md_dst || md_dst->type != METADATA_HW_PORT_MUX) 338 return 0; 339 340 return md_dst->u.port_info.port_id; 341 } 342 343 static netdev_tx_t bnxt_start_xmit(struct sk_buff *skb, struct net_device *dev) 344 { 345 struct bnxt *bp = netdev_priv(dev); 346 struct tx_bd *txbd; 347 struct tx_bd_ext *txbd1; 348 struct netdev_queue *txq; 349 int i; 350 dma_addr_t mapping; 351 unsigned int length, pad = 0; 352 u32 len, free_size, vlan_tag_flags, cfa_action, flags; 353 u16 prod, last_frag; 354 struct pci_dev *pdev = bp->pdev; 355 struct bnxt_tx_ring_info *txr; 356 struct bnxt_sw_tx_bd *tx_buf; 357 358 i = skb_get_queue_mapping(skb); 359 if (unlikely(i >= bp->tx_nr_rings)) { 360 dev_kfree_skb_any(skb); 361 return NETDEV_TX_OK; 362 } 363 364 txq = netdev_get_tx_queue(dev, i); 365 txr = &bp->tx_ring[bp->tx_ring_map[i]]; 366 prod = txr->tx_prod; 367 368 free_size = bnxt_tx_avail(bp, txr); 369 if (unlikely(free_size < skb_shinfo(skb)->nr_frags + 2)) { 370 netif_tx_stop_queue(txq); 371 return NETDEV_TX_BUSY; 372 } 373 374 length = skb->len; 375 len = skb_headlen(skb); 376 last_frag = skb_shinfo(skb)->nr_frags; 377 378 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)]; 379 380 txbd->tx_bd_opaque = prod; 381 382 tx_buf = &txr->tx_buf_ring[prod]; 383 tx_buf->skb = skb; 384 tx_buf->nr_frags = last_frag; 385 386 vlan_tag_flags = 0; 387 cfa_action = bnxt_xmit_get_cfa_action(skb); 388 if (skb_vlan_tag_present(skb)) { 389 vlan_tag_flags = TX_BD_CFA_META_KEY_VLAN | 390 skb_vlan_tag_get(skb); 391 /* Currently supports 8021Q, 8021AD vlan offloads 392 * QINQ1, QINQ2, QINQ3 vlan headers are deprecated 393 */ 394 if (skb->vlan_proto == htons(ETH_P_8021Q)) 395 vlan_tag_flags |= 1 << TX_BD_CFA_META_TPID_SHIFT; 396 } 397 398 if (free_size == bp->tx_ring_size && length <= bp->tx_push_thresh) { 399 struct tx_push_buffer *tx_push_buf = txr->tx_push; 400 struct tx_push_bd *tx_push = &tx_push_buf->push_bd; 401 struct tx_bd_ext *tx_push1 = &tx_push->txbd2; 402 void __iomem *db = txr->tx_db.doorbell; 403 void *pdata = tx_push_buf->data; 404 u64 *end; 405 int j, push_len; 406 407 /* Set COAL_NOW to be ready quickly for the next push */ 408 tx_push->tx_bd_len_flags_type = 409 cpu_to_le32((length << TX_BD_LEN_SHIFT) | 410 TX_BD_TYPE_LONG_TX_BD | 411 TX_BD_FLAGS_LHINT_512_AND_SMALLER | 412 TX_BD_FLAGS_COAL_NOW | 413 TX_BD_FLAGS_PACKET_END | 414 (2 << TX_BD_FLAGS_BD_CNT_SHIFT)); 415 416 if (skb->ip_summed == CHECKSUM_PARTIAL) 417 tx_push1->tx_bd_hsize_lflags = 418 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM); 419 else 420 tx_push1->tx_bd_hsize_lflags = 0; 421 422 tx_push1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags); 423 tx_push1->tx_bd_cfa_action = 424 cpu_to_le32(cfa_action << TX_BD_CFA_ACTION_SHIFT); 425 426 end = pdata + length; 427 end = PTR_ALIGN(end, 8) - 1; 428 *end = 0; 429 430 skb_copy_from_linear_data(skb, pdata, len); 431 pdata += len; 432 for (j = 0; j < last_frag; j++) { 433 skb_frag_t *frag = &skb_shinfo(skb)->frags[j]; 434 void *fptr; 435 436 fptr = skb_frag_address_safe(frag); 437 if (!fptr) 438 goto normal_tx; 439 440 memcpy(pdata, fptr, skb_frag_size(frag)); 441 pdata += skb_frag_size(frag); 442 } 443 444 txbd->tx_bd_len_flags_type = tx_push->tx_bd_len_flags_type; 445 txbd->tx_bd_haddr = txr->data_mapping; 446 prod = NEXT_TX(prod); 447 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)]; 448 memcpy(txbd, tx_push1, sizeof(*txbd)); 449 prod = NEXT_TX(prod); 450 tx_push->doorbell = 451 cpu_to_le32(DB_KEY_TX_PUSH | DB_LONG_TX_PUSH | prod); 452 txr->tx_prod = prod; 453 454 tx_buf->is_push = 1; 455 netdev_tx_sent_queue(txq, skb->len); 456 wmb(); /* Sync is_push and byte queue before pushing data */ 457 458 push_len = (length + sizeof(*tx_push) + 7) / 8; 459 if (push_len > 16) { 460 __iowrite64_copy(db, tx_push_buf, 16); 461 __iowrite32_copy(db + 4, tx_push_buf + 1, 462 (push_len - 16) << 1); 463 } else { 464 __iowrite64_copy(db, tx_push_buf, push_len); 465 } 466 467 goto tx_done; 468 } 469 470 normal_tx: 471 if (length < BNXT_MIN_PKT_SIZE) { 472 pad = BNXT_MIN_PKT_SIZE - length; 473 if (skb_pad(skb, pad)) { 474 /* SKB already freed. */ 475 tx_buf->skb = NULL; 476 return NETDEV_TX_OK; 477 } 478 length = BNXT_MIN_PKT_SIZE; 479 } 480 481 mapping = dma_map_single(&pdev->dev, skb->data, len, DMA_TO_DEVICE); 482 483 if (unlikely(dma_mapping_error(&pdev->dev, mapping))) { 484 dev_kfree_skb_any(skb); 485 tx_buf->skb = NULL; 486 return NETDEV_TX_OK; 487 } 488 489 dma_unmap_addr_set(tx_buf, mapping, mapping); 490 flags = (len << TX_BD_LEN_SHIFT) | TX_BD_TYPE_LONG_TX_BD | 491 ((last_frag + 2) << TX_BD_FLAGS_BD_CNT_SHIFT); 492 493 txbd->tx_bd_haddr = cpu_to_le64(mapping); 494 495 prod = NEXT_TX(prod); 496 txbd1 = (struct tx_bd_ext *) 497 &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)]; 498 499 txbd1->tx_bd_hsize_lflags = 0; 500 if (skb_is_gso(skb)) { 501 u32 hdr_len; 502 503 if (skb->encapsulation) 504 hdr_len = skb_inner_network_offset(skb) + 505 skb_inner_network_header_len(skb) + 506 inner_tcp_hdrlen(skb); 507 else 508 hdr_len = skb_transport_offset(skb) + 509 tcp_hdrlen(skb); 510 511 txbd1->tx_bd_hsize_lflags = cpu_to_le32(TX_BD_FLAGS_LSO | 512 TX_BD_FLAGS_T_IPID | 513 (hdr_len << (TX_BD_HSIZE_SHIFT - 1))); 514 length = skb_shinfo(skb)->gso_size; 515 txbd1->tx_bd_mss = cpu_to_le32(length); 516 length += hdr_len; 517 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 518 txbd1->tx_bd_hsize_lflags = 519 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM); 520 txbd1->tx_bd_mss = 0; 521 } 522 523 length >>= 9; 524 if (unlikely(length >= ARRAY_SIZE(bnxt_lhint_arr))) { 525 dev_warn_ratelimited(&pdev->dev, "Dropped oversize %d bytes TX packet.\n", 526 skb->len); 527 i = 0; 528 goto tx_dma_error; 529 } 530 flags |= bnxt_lhint_arr[length]; 531 txbd->tx_bd_len_flags_type = cpu_to_le32(flags); 532 533 txbd1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags); 534 txbd1->tx_bd_cfa_action = 535 cpu_to_le32(cfa_action << TX_BD_CFA_ACTION_SHIFT); 536 for (i = 0; i < last_frag; i++) { 537 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 538 539 prod = NEXT_TX(prod); 540 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)]; 541 542 len = skb_frag_size(frag); 543 mapping = skb_frag_dma_map(&pdev->dev, frag, 0, len, 544 DMA_TO_DEVICE); 545 546 if (unlikely(dma_mapping_error(&pdev->dev, mapping))) 547 goto tx_dma_error; 548 549 tx_buf = &txr->tx_buf_ring[prod]; 550 dma_unmap_addr_set(tx_buf, mapping, mapping); 551 552 txbd->tx_bd_haddr = cpu_to_le64(mapping); 553 554 flags = len << TX_BD_LEN_SHIFT; 555 txbd->tx_bd_len_flags_type = cpu_to_le32(flags); 556 } 557 558 flags &= ~TX_BD_LEN; 559 txbd->tx_bd_len_flags_type = 560 cpu_to_le32(((len + pad) << TX_BD_LEN_SHIFT) | flags | 561 TX_BD_FLAGS_PACKET_END); 562 563 netdev_tx_sent_queue(txq, skb->len); 564 565 /* Sync BD data before updating doorbell */ 566 wmb(); 567 568 prod = NEXT_TX(prod); 569 txr->tx_prod = prod; 570 571 if (!netdev_xmit_more() || netif_xmit_stopped(txq)) 572 bnxt_db_write(bp, &txr->tx_db, prod); 573 574 tx_done: 575 576 if (unlikely(bnxt_tx_avail(bp, txr) <= MAX_SKB_FRAGS + 1)) { 577 if (netdev_xmit_more() && !tx_buf->is_push) 578 bnxt_db_write(bp, &txr->tx_db, prod); 579 580 netif_tx_stop_queue(txq); 581 582 /* netif_tx_stop_queue() must be done before checking 583 * tx index in bnxt_tx_avail() below, because in 584 * bnxt_tx_int(), we update tx index before checking for 585 * netif_tx_queue_stopped(). 586 */ 587 smp_mb(); 588 if (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh) 589 netif_tx_wake_queue(txq); 590 } 591 return NETDEV_TX_OK; 592 593 tx_dma_error: 594 last_frag = i; 595 596 /* start back at beginning and unmap skb */ 597 prod = txr->tx_prod; 598 tx_buf = &txr->tx_buf_ring[prod]; 599 tx_buf->skb = NULL; 600 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping), 601 skb_headlen(skb), PCI_DMA_TODEVICE); 602 prod = NEXT_TX(prod); 603 604 /* unmap remaining mapped pages */ 605 for (i = 0; i < last_frag; i++) { 606 prod = NEXT_TX(prod); 607 tx_buf = &txr->tx_buf_ring[prod]; 608 dma_unmap_page(&pdev->dev, dma_unmap_addr(tx_buf, mapping), 609 skb_frag_size(&skb_shinfo(skb)->frags[i]), 610 PCI_DMA_TODEVICE); 611 } 612 613 dev_kfree_skb_any(skb); 614 return NETDEV_TX_OK; 615 } 616 617 static void bnxt_tx_int(struct bnxt *bp, struct bnxt_napi *bnapi, int nr_pkts) 618 { 619 struct bnxt_tx_ring_info *txr = bnapi->tx_ring; 620 struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, txr->txq_index); 621 u16 cons = txr->tx_cons; 622 struct pci_dev *pdev = bp->pdev; 623 int i; 624 unsigned int tx_bytes = 0; 625 626 for (i = 0; i < nr_pkts; i++) { 627 struct bnxt_sw_tx_bd *tx_buf; 628 struct sk_buff *skb; 629 int j, last; 630 631 tx_buf = &txr->tx_buf_ring[cons]; 632 cons = NEXT_TX(cons); 633 skb = tx_buf->skb; 634 tx_buf->skb = NULL; 635 636 if (tx_buf->is_push) { 637 tx_buf->is_push = 0; 638 goto next_tx_int; 639 } 640 641 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping), 642 skb_headlen(skb), PCI_DMA_TODEVICE); 643 last = tx_buf->nr_frags; 644 645 for (j = 0; j < last; j++) { 646 cons = NEXT_TX(cons); 647 tx_buf = &txr->tx_buf_ring[cons]; 648 dma_unmap_page( 649 &pdev->dev, 650 dma_unmap_addr(tx_buf, mapping), 651 skb_frag_size(&skb_shinfo(skb)->frags[j]), 652 PCI_DMA_TODEVICE); 653 } 654 655 next_tx_int: 656 cons = NEXT_TX(cons); 657 658 tx_bytes += skb->len; 659 dev_kfree_skb_any(skb); 660 } 661 662 netdev_tx_completed_queue(txq, nr_pkts, tx_bytes); 663 txr->tx_cons = cons; 664 665 /* Need to make the tx_cons update visible to bnxt_start_xmit() 666 * before checking for netif_tx_queue_stopped(). Without the 667 * memory barrier, there is a small possibility that bnxt_start_xmit() 668 * will miss it and cause the queue to be stopped forever. 669 */ 670 smp_mb(); 671 672 if (unlikely(netif_tx_queue_stopped(txq)) && 673 (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)) { 674 __netif_tx_lock(txq, smp_processor_id()); 675 if (netif_tx_queue_stopped(txq) && 676 bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh && 677 txr->dev_state != BNXT_DEV_STATE_CLOSING) 678 netif_tx_wake_queue(txq); 679 __netif_tx_unlock(txq); 680 } 681 } 682 683 static struct page *__bnxt_alloc_rx_page(struct bnxt *bp, dma_addr_t *mapping, 684 struct bnxt_rx_ring_info *rxr, 685 gfp_t gfp) 686 { 687 struct device *dev = &bp->pdev->dev; 688 struct page *page; 689 690 page = page_pool_dev_alloc_pages(rxr->page_pool); 691 if (!page) 692 return NULL; 693 694 *mapping = dma_map_page_attrs(dev, page, 0, PAGE_SIZE, bp->rx_dir, 695 DMA_ATTR_WEAK_ORDERING); 696 if (dma_mapping_error(dev, *mapping)) { 697 page_pool_recycle_direct(rxr->page_pool, page); 698 return NULL; 699 } 700 *mapping += bp->rx_dma_offset; 701 return page; 702 } 703 704 static inline u8 *__bnxt_alloc_rx_data(struct bnxt *bp, dma_addr_t *mapping, 705 gfp_t gfp) 706 { 707 u8 *data; 708 struct pci_dev *pdev = bp->pdev; 709 710 data = kmalloc(bp->rx_buf_size, gfp); 711 if (!data) 712 return NULL; 713 714 *mapping = dma_map_single_attrs(&pdev->dev, data + bp->rx_dma_offset, 715 bp->rx_buf_use_size, bp->rx_dir, 716 DMA_ATTR_WEAK_ORDERING); 717 718 if (dma_mapping_error(&pdev->dev, *mapping)) { 719 kfree(data); 720 data = NULL; 721 } 722 return data; 723 } 724 725 int bnxt_alloc_rx_data(struct bnxt *bp, struct bnxt_rx_ring_info *rxr, 726 u16 prod, gfp_t gfp) 727 { 728 struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)]; 729 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[prod]; 730 dma_addr_t mapping; 731 732 if (BNXT_RX_PAGE_MODE(bp)) { 733 struct page *page = 734 __bnxt_alloc_rx_page(bp, &mapping, rxr, gfp); 735 736 if (!page) 737 return -ENOMEM; 738 739 rx_buf->data = page; 740 rx_buf->data_ptr = page_address(page) + bp->rx_offset; 741 } else { 742 u8 *data = __bnxt_alloc_rx_data(bp, &mapping, gfp); 743 744 if (!data) 745 return -ENOMEM; 746 747 rx_buf->data = data; 748 rx_buf->data_ptr = data + bp->rx_offset; 749 } 750 rx_buf->mapping = mapping; 751 752 rxbd->rx_bd_haddr = cpu_to_le64(mapping); 753 return 0; 754 } 755 756 void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons, void *data) 757 { 758 u16 prod = rxr->rx_prod; 759 struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf; 760 struct rx_bd *cons_bd, *prod_bd; 761 762 prod_rx_buf = &rxr->rx_buf_ring[prod]; 763 cons_rx_buf = &rxr->rx_buf_ring[cons]; 764 765 prod_rx_buf->data = data; 766 prod_rx_buf->data_ptr = cons_rx_buf->data_ptr; 767 768 prod_rx_buf->mapping = cons_rx_buf->mapping; 769 770 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)]; 771 cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)]; 772 773 prod_bd->rx_bd_haddr = cons_bd->rx_bd_haddr; 774 } 775 776 static inline u16 bnxt_find_next_agg_idx(struct bnxt_rx_ring_info *rxr, u16 idx) 777 { 778 u16 next, max = rxr->rx_agg_bmap_size; 779 780 next = find_next_zero_bit(rxr->rx_agg_bmap, max, idx); 781 if (next >= max) 782 next = find_first_zero_bit(rxr->rx_agg_bmap, max); 783 return next; 784 } 785 786 static inline int bnxt_alloc_rx_page(struct bnxt *bp, 787 struct bnxt_rx_ring_info *rxr, 788 u16 prod, gfp_t gfp) 789 { 790 struct rx_bd *rxbd = 791 &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)]; 792 struct bnxt_sw_rx_agg_bd *rx_agg_buf; 793 struct pci_dev *pdev = bp->pdev; 794 struct page *page; 795 dma_addr_t mapping; 796 u16 sw_prod = rxr->rx_sw_agg_prod; 797 unsigned int offset = 0; 798 799 if (PAGE_SIZE > BNXT_RX_PAGE_SIZE) { 800 page = rxr->rx_page; 801 if (!page) { 802 page = alloc_page(gfp); 803 if (!page) 804 return -ENOMEM; 805 rxr->rx_page = page; 806 rxr->rx_page_offset = 0; 807 } 808 offset = rxr->rx_page_offset; 809 rxr->rx_page_offset += BNXT_RX_PAGE_SIZE; 810 if (rxr->rx_page_offset == PAGE_SIZE) 811 rxr->rx_page = NULL; 812 else 813 get_page(page); 814 } else { 815 page = alloc_page(gfp); 816 if (!page) 817 return -ENOMEM; 818 } 819 820 mapping = dma_map_page_attrs(&pdev->dev, page, offset, 821 BNXT_RX_PAGE_SIZE, PCI_DMA_FROMDEVICE, 822 DMA_ATTR_WEAK_ORDERING); 823 if (dma_mapping_error(&pdev->dev, mapping)) { 824 __free_page(page); 825 return -EIO; 826 } 827 828 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap))) 829 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod); 830 831 __set_bit(sw_prod, rxr->rx_agg_bmap); 832 rx_agg_buf = &rxr->rx_agg_ring[sw_prod]; 833 rxr->rx_sw_agg_prod = NEXT_RX_AGG(sw_prod); 834 835 rx_agg_buf->page = page; 836 rx_agg_buf->offset = offset; 837 rx_agg_buf->mapping = mapping; 838 rxbd->rx_bd_haddr = cpu_to_le64(mapping); 839 rxbd->rx_bd_opaque = sw_prod; 840 return 0; 841 } 842 843 static struct rx_agg_cmp *bnxt_get_agg(struct bnxt *bp, 844 struct bnxt_cp_ring_info *cpr, 845 u16 cp_cons, u16 curr) 846 { 847 struct rx_agg_cmp *agg; 848 849 cp_cons = RING_CMP(ADV_RAW_CMP(cp_cons, curr)); 850 agg = (struct rx_agg_cmp *) 851 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 852 return agg; 853 } 854 855 static struct rx_agg_cmp *bnxt_get_tpa_agg_p5(struct bnxt *bp, 856 struct bnxt_rx_ring_info *rxr, 857 u16 agg_id, u16 curr) 858 { 859 struct bnxt_tpa_info *tpa_info = &rxr->rx_tpa[agg_id]; 860 861 return &tpa_info->agg_arr[curr]; 862 } 863 864 static void bnxt_reuse_rx_agg_bufs(struct bnxt_cp_ring_info *cpr, u16 idx, 865 u16 start, u32 agg_bufs, bool tpa) 866 { 867 struct bnxt_napi *bnapi = cpr->bnapi; 868 struct bnxt *bp = bnapi->bp; 869 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 870 u16 prod = rxr->rx_agg_prod; 871 u16 sw_prod = rxr->rx_sw_agg_prod; 872 bool p5_tpa = false; 873 u32 i; 874 875 if ((bp->flags & BNXT_FLAG_CHIP_P5) && tpa) 876 p5_tpa = true; 877 878 for (i = 0; i < agg_bufs; i++) { 879 u16 cons; 880 struct rx_agg_cmp *agg; 881 struct bnxt_sw_rx_agg_bd *cons_rx_buf, *prod_rx_buf; 882 struct rx_bd *prod_bd; 883 struct page *page; 884 885 if (p5_tpa) 886 agg = bnxt_get_tpa_agg_p5(bp, rxr, idx, start + i); 887 else 888 agg = bnxt_get_agg(bp, cpr, idx, start + i); 889 cons = agg->rx_agg_cmp_opaque; 890 __clear_bit(cons, rxr->rx_agg_bmap); 891 892 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap))) 893 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod); 894 895 __set_bit(sw_prod, rxr->rx_agg_bmap); 896 prod_rx_buf = &rxr->rx_agg_ring[sw_prod]; 897 cons_rx_buf = &rxr->rx_agg_ring[cons]; 898 899 /* It is possible for sw_prod to be equal to cons, so 900 * set cons_rx_buf->page to NULL first. 901 */ 902 page = cons_rx_buf->page; 903 cons_rx_buf->page = NULL; 904 prod_rx_buf->page = page; 905 prod_rx_buf->offset = cons_rx_buf->offset; 906 907 prod_rx_buf->mapping = cons_rx_buf->mapping; 908 909 prod_bd = &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)]; 910 911 prod_bd->rx_bd_haddr = cpu_to_le64(cons_rx_buf->mapping); 912 prod_bd->rx_bd_opaque = sw_prod; 913 914 prod = NEXT_RX_AGG(prod); 915 sw_prod = NEXT_RX_AGG(sw_prod); 916 } 917 rxr->rx_agg_prod = prod; 918 rxr->rx_sw_agg_prod = sw_prod; 919 } 920 921 static struct sk_buff *bnxt_rx_page_skb(struct bnxt *bp, 922 struct bnxt_rx_ring_info *rxr, 923 u16 cons, void *data, u8 *data_ptr, 924 dma_addr_t dma_addr, 925 unsigned int offset_and_len) 926 { 927 unsigned int payload = offset_and_len >> 16; 928 unsigned int len = offset_and_len & 0xffff; 929 skb_frag_t *frag; 930 struct page *page = data; 931 u16 prod = rxr->rx_prod; 932 struct sk_buff *skb; 933 int off, err; 934 935 err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC); 936 if (unlikely(err)) { 937 bnxt_reuse_rx_data(rxr, cons, data); 938 return NULL; 939 } 940 dma_addr -= bp->rx_dma_offset; 941 dma_unmap_page_attrs(&bp->pdev->dev, dma_addr, PAGE_SIZE, bp->rx_dir, 942 DMA_ATTR_WEAK_ORDERING); 943 page_pool_release_page(rxr->page_pool, page); 944 945 if (unlikely(!payload)) 946 payload = eth_get_headlen(bp->dev, data_ptr, len); 947 948 skb = napi_alloc_skb(&rxr->bnapi->napi, payload); 949 if (!skb) { 950 __free_page(page); 951 return NULL; 952 } 953 954 off = (void *)data_ptr - page_address(page); 955 skb_add_rx_frag(skb, 0, page, off, len, PAGE_SIZE); 956 memcpy(skb->data - NET_IP_ALIGN, data_ptr - NET_IP_ALIGN, 957 payload + NET_IP_ALIGN); 958 959 frag = &skb_shinfo(skb)->frags[0]; 960 skb_frag_size_sub(frag, payload); 961 skb_frag_off_add(frag, payload); 962 skb->data_len -= payload; 963 skb->tail += payload; 964 965 return skb; 966 } 967 968 static struct sk_buff *bnxt_rx_skb(struct bnxt *bp, 969 struct bnxt_rx_ring_info *rxr, u16 cons, 970 void *data, u8 *data_ptr, 971 dma_addr_t dma_addr, 972 unsigned int offset_and_len) 973 { 974 u16 prod = rxr->rx_prod; 975 struct sk_buff *skb; 976 int err; 977 978 err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC); 979 if (unlikely(err)) { 980 bnxt_reuse_rx_data(rxr, cons, data); 981 return NULL; 982 } 983 984 skb = build_skb(data, 0); 985 dma_unmap_single_attrs(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size, 986 bp->rx_dir, DMA_ATTR_WEAK_ORDERING); 987 if (!skb) { 988 kfree(data); 989 return NULL; 990 } 991 992 skb_reserve(skb, bp->rx_offset); 993 skb_put(skb, offset_and_len & 0xffff); 994 return skb; 995 } 996 997 static struct sk_buff *bnxt_rx_pages(struct bnxt *bp, 998 struct bnxt_cp_ring_info *cpr, 999 struct sk_buff *skb, u16 idx, 1000 u32 agg_bufs, bool tpa) 1001 { 1002 struct bnxt_napi *bnapi = cpr->bnapi; 1003 struct pci_dev *pdev = bp->pdev; 1004 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 1005 u16 prod = rxr->rx_agg_prod; 1006 bool p5_tpa = false; 1007 u32 i; 1008 1009 if ((bp->flags & BNXT_FLAG_CHIP_P5) && tpa) 1010 p5_tpa = true; 1011 1012 for (i = 0; i < agg_bufs; i++) { 1013 u16 cons, frag_len; 1014 struct rx_agg_cmp *agg; 1015 struct bnxt_sw_rx_agg_bd *cons_rx_buf; 1016 struct page *page; 1017 dma_addr_t mapping; 1018 1019 if (p5_tpa) 1020 agg = bnxt_get_tpa_agg_p5(bp, rxr, idx, i); 1021 else 1022 agg = bnxt_get_agg(bp, cpr, idx, i); 1023 cons = agg->rx_agg_cmp_opaque; 1024 frag_len = (le32_to_cpu(agg->rx_agg_cmp_len_flags_type) & 1025 RX_AGG_CMP_LEN) >> RX_AGG_CMP_LEN_SHIFT; 1026 1027 cons_rx_buf = &rxr->rx_agg_ring[cons]; 1028 skb_fill_page_desc(skb, i, cons_rx_buf->page, 1029 cons_rx_buf->offset, frag_len); 1030 __clear_bit(cons, rxr->rx_agg_bmap); 1031 1032 /* It is possible for bnxt_alloc_rx_page() to allocate 1033 * a sw_prod index that equals the cons index, so we 1034 * need to clear the cons entry now. 1035 */ 1036 mapping = cons_rx_buf->mapping; 1037 page = cons_rx_buf->page; 1038 cons_rx_buf->page = NULL; 1039 1040 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_ATOMIC) != 0) { 1041 struct skb_shared_info *shinfo; 1042 unsigned int nr_frags; 1043 1044 shinfo = skb_shinfo(skb); 1045 nr_frags = --shinfo->nr_frags; 1046 __skb_frag_set_page(&shinfo->frags[nr_frags], NULL); 1047 1048 dev_kfree_skb(skb); 1049 1050 cons_rx_buf->page = page; 1051 1052 /* Update prod since possibly some pages have been 1053 * allocated already. 1054 */ 1055 rxr->rx_agg_prod = prod; 1056 bnxt_reuse_rx_agg_bufs(cpr, idx, i, agg_bufs - i, tpa); 1057 return NULL; 1058 } 1059 1060 dma_unmap_page_attrs(&pdev->dev, mapping, BNXT_RX_PAGE_SIZE, 1061 PCI_DMA_FROMDEVICE, 1062 DMA_ATTR_WEAK_ORDERING); 1063 1064 skb->data_len += frag_len; 1065 skb->len += frag_len; 1066 skb->truesize += PAGE_SIZE; 1067 1068 prod = NEXT_RX_AGG(prod); 1069 } 1070 rxr->rx_agg_prod = prod; 1071 return skb; 1072 } 1073 1074 static int bnxt_agg_bufs_valid(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, 1075 u8 agg_bufs, u32 *raw_cons) 1076 { 1077 u16 last; 1078 struct rx_agg_cmp *agg; 1079 1080 *raw_cons = ADV_RAW_CMP(*raw_cons, agg_bufs); 1081 last = RING_CMP(*raw_cons); 1082 agg = (struct rx_agg_cmp *) 1083 &cpr->cp_desc_ring[CP_RING(last)][CP_IDX(last)]; 1084 return RX_AGG_CMP_VALID(agg, *raw_cons); 1085 } 1086 1087 static inline struct sk_buff *bnxt_copy_skb(struct bnxt_napi *bnapi, u8 *data, 1088 unsigned int len, 1089 dma_addr_t mapping) 1090 { 1091 struct bnxt *bp = bnapi->bp; 1092 struct pci_dev *pdev = bp->pdev; 1093 struct sk_buff *skb; 1094 1095 skb = napi_alloc_skb(&bnapi->napi, len); 1096 if (!skb) 1097 return NULL; 1098 1099 dma_sync_single_for_cpu(&pdev->dev, mapping, bp->rx_copy_thresh, 1100 bp->rx_dir); 1101 1102 memcpy(skb->data - NET_IP_ALIGN, data - NET_IP_ALIGN, 1103 len + NET_IP_ALIGN); 1104 1105 dma_sync_single_for_device(&pdev->dev, mapping, bp->rx_copy_thresh, 1106 bp->rx_dir); 1107 1108 skb_put(skb, len); 1109 return skb; 1110 } 1111 1112 static int bnxt_discard_rx(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, 1113 u32 *raw_cons, void *cmp) 1114 { 1115 struct rx_cmp *rxcmp = cmp; 1116 u32 tmp_raw_cons = *raw_cons; 1117 u8 cmp_type, agg_bufs = 0; 1118 1119 cmp_type = RX_CMP_TYPE(rxcmp); 1120 1121 if (cmp_type == CMP_TYPE_RX_L2_CMP) { 1122 agg_bufs = (le32_to_cpu(rxcmp->rx_cmp_misc_v1) & 1123 RX_CMP_AGG_BUFS) >> 1124 RX_CMP_AGG_BUFS_SHIFT; 1125 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) { 1126 struct rx_tpa_end_cmp *tpa_end = cmp; 1127 1128 if (bp->flags & BNXT_FLAG_CHIP_P5) 1129 return 0; 1130 1131 agg_bufs = TPA_END_AGG_BUFS(tpa_end); 1132 } 1133 1134 if (agg_bufs) { 1135 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons)) 1136 return -EBUSY; 1137 } 1138 *raw_cons = tmp_raw_cons; 1139 return 0; 1140 } 1141 1142 static void bnxt_queue_fw_reset_work(struct bnxt *bp, unsigned long delay) 1143 { 1144 if (BNXT_PF(bp)) 1145 queue_delayed_work(bnxt_pf_wq, &bp->fw_reset_task, delay); 1146 else 1147 schedule_delayed_work(&bp->fw_reset_task, delay); 1148 } 1149 1150 static void bnxt_queue_sp_work(struct bnxt *bp) 1151 { 1152 if (BNXT_PF(bp)) 1153 queue_work(bnxt_pf_wq, &bp->sp_task); 1154 else 1155 schedule_work(&bp->sp_task); 1156 } 1157 1158 static void bnxt_cancel_sp_work(struct bnxt *bp) 1159 { 1160 if (BNXT_PF(bp)) 1161 flush_workqueue(bnxt_pf_wq); 1162 else 1163 cancel_work_sync(&bp->sp_task); 1164 } 1165 1166 static void bnxt_sched_reset(struct bnxt *bp, struct bnxt_rx_ring_info *rxr) 1167 { 1168 if (!rxr->bnapi->in_reset) { 1169 rxr->bnapi->in_reset = true; 1170 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event); 1171 bnxt_queue_sp_work(bp); 1172 } 1173 rxr->rx_next_cons = 0xffff; 1174 } 1175 1176 static u16 bnxt_alloc_agg_idx(struct bnxt_rx_ring_info *rxr, u16 agg_id) 1177 { 1178 struct bnxt_tpa_idx_map *map = rxr->rx_tpa_idx_map; 1179 u16 idx = agg_id & MAX_TPA_P5_MASK; 1180 1181 if (test_bit(idx, map->agg_idx_bmap)) 1182 idx = find_first_zero_bit(map->agg_idx_bmap, 1183 BNXT_AGG_IDX_BMAP_SIZE); 1184 __set_bit(idx, map->agg_idx_bmap); 1185 map->agg_id_tbl[agg_id] = idx; 1186 return idx; 1187 } 1188 1189 static void bnxt_free_agg_idx(struct bnxt_rx_ring_info *rxr, u16 idx) 1190 { 1191 struct bnxt_tpa_idx_map *map = rxr->rx_tpa_idx_map; 1192 1193 __clear_bit(idx, map->agg_idx_bmap); 1194 } 1195 1196 static u16 bnxt_lookup_agg_idx(struct bnxt_rx_ring_info *rxr, u16 agg_id) 1197 { 1198 struct bnxt_tpa_idx_map *map = rxr->rx_tpa_idx_map; 1199 1200 return map->agg_id_tbl[agg_id]; 1201 } 1202 1203 static void bnxt_tpa_start(struct bnxt *bp, struct bnxt_rx_ring_info *rxr, 1204 struct rx_tpa_start_cmp *tpa_start, 1205 struct rx_tpa_start_cmp_ext *tpa_start1) 1206 { 1207 struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf; 1208 struct bnxt_tpa_info *tpa_info; 1209 u16 cons, prod, agg_id; 1210 struct rx_bd *prod_bd; 1211 dma_addr_t mapping; 1212 1213 if (bp->flags & BNXT_FLAG_CHIP_P5) { 1214 agg_id = TPA_START_AGG_ID_P5(tpa_start); 1215 agg_id = bnxt_alloc_agg_idx(rxr, agg_id); 1216 } else { 1217 agg_id = TPA_START_AGG_ID(tpa_start); 1218 } 1219 cons = tpa_start->rx_tpa_start_cmp_opaque; 1220 prod = rxr->rx_prod; 1221 cons_rx_buf = &rxr->rx_buf_ring[cons]; 1222 prod_rx_buf = &rxr->rx_buf_ring[prod]; 1223 tpa_info = &rxr->rx_tpa[agg_id]; 1224 1225 if (unlikely(cons != rxr->rx_next_cons || 1226 TPA_START_ERROR(tpa_start))) { 1227 netdev_warn(bp->dev, "TPA cons %x, expected cons %x, error code %x\n", 1228 cons, rxr->rx_next_cons, 1229 TPA_START_ERROR_CODE(tpa_start1)); 1230 bnxt_sched_reset(bp, rxr); 1231 return; 1232 } 1233 /* Store cfa_code in tpa_info to use in tpa_end 1234 * completion processing. 1235 */ 1236 tpa_info->cfa_code = TPA_START_CFA_CODE(tpa_start1); 1237 prod_rx_buf->data = tpa_info->data; 1238 prod_rx_buf->data_ptr = tpa_info->data_ptr; 1239 1240 mapping = tpa_info->mapping; 1241 prod_rx_buf->mapping = mapping; 1242 1243 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)]; 1244 1245 prod_bd->rx_bd_haddr = cpu_to_le64(mapping); 1246 1247 tpa_info->data = cons_rx_buf->data; 1248 tpa_info->data_ptr = cons_rx_buf->data_ptr; 1249 cons_rx_buf->data = NULL; 1250 tpa_info->mapping = cons_rx_buf->mapping; 1251 1252 tpa_info->len = 1253 le32_to_cpu(tpa_start->rx_tpa_start_cmp_len_flags_type) >> 1254 RX_TPA_START_CMP_LEN_SHIFT; 1255 if (likely(TPA_START_HASH_VALID(tpa_start))) { 1256 u32 hash_type = TPA_START_HASH_TYPE(tpa_start); 1257 1258 tpa_info->hash_type = PKT_HASH_TYPE_L4; 1259 tpa_info->gso_type = SKB_GSO_TCPV4; 1260 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */ 1261 if (hash_type == 3 || TPA_START_IS_IPV6(tpa_start1)) 1262 tpa_info->gso_type = SKB_GSO_TCPV6; 1263 tpa_info->rss_hash = 1264 le32_to_cpu(tpa_start->rx_tpa_start_cmp_rss_hash); 1265 } else { 1266 tpa_info->hash_type = PKT_HASH_TYPE_NONE; 1267 tpa_info->gso_type = 0; 1268 if (netif_msg_rx_err(bp)) 1269 netdev_warn(bp->dev, "TPA packet without valid hash\n"); 1270 } 1271 tpa_info->flags2 = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_flags2); 1272 tpa_info->metadata = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_metadata); 1273 tpa_info->hdr_info = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_hdr_info); 1274 tpa_info->agg_count = 0; 1275 1276 rxr->rx_prod = NEXT_RX(prod); 1277 cons = NEXT_RX(cons); 1278 rxr->rx_next_cons = NEXT_RX(cons); 1279 cons_rx_buf = &rxr->rx_buf_ring[cons]; 1280 1281 bnxt_reuse_rx_data(rxr, cons, cons_rx_buf->data); 1282 rxr->rx_prod = NEXT_RX(rxr->rx_prod); 1283 cons_rx_buf->data = NULL; 1284 } 1285 1286 static void bnxt_abort_tpa(struct bnxt_cp_ring_info *cpr, u16 idx, u32 agg_bufs) 1287 { 1288 if (agg_bufs) 1289 bnxt_reuse_rx_agg_bufs(cpr, idx, 0, agg_bufs, true); 1290 } 1291 1292 #ifdef CONFIG_INET 1293 static void bnxt_gro_tunnel(struct sk_buff *skb, __be16 ip_proto) 1294 { 1295 struct udphdr *uh = NULL; 1296 1297 if (ip_proto == htons(ETH_P_IP)) { 1298 struct iphdr *iph = (struct iphdr *)skb->data; 1299 1300 if (iph->protocol == IPPROTO_UDP) 1301 uh = (struct udphdr *)(iph + 1); 1302 } else { 1303 struct ipv6hdr *iph = (struct ipv6hdr *)skb->data; 1304 1305 if (iph->nexthdr == IPPROTO_UDP) 1306 uh = (struct udphdr *)(iph + 1); 1307 } 1308 if (uh) { 1309 if (uh->check) 1310 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL_CSUM; 1311 else 1312 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL; 1313 } 1314 } 1315 #endif 1316 1317 static struct sk_buff *bnxt_gro_func_5731x(struct bnxt_tpa_info *tpa_info, 1318 int payload_off, int tcp_ts, 1319 struct sk_buff *skb) 1320 { 1321 #ifdef CONFIG_INET 1322 struct tcphdr *th; 1323 int len, nw_off; 1324 u16 outer_ip_off, inner_ip_off, inner_mac_off; 1325 u32 hdr_info = tpa_info->hdr_info; 1326 bool loopback = false; 1327 1328 inner_ip_off = BNXT_TPA_INNER_L3_OFF(hdr_info); 1329 inner_mac_off = BNXT_TPA_INNER_L2_OFF(hdr_info); 1330 outer_ip_off = BNXT_TPA_OUTER_L3_OFF(hdr_info); 1331 1332 /* If the packet is an internal loopback packet, the offsets will 1333 * have an extra 4 bytes. 1334 */ 1335 if (inner_mac_off == 4) { 1336 loopback = true; 1337 } else if (inner_mac_off > 4) { 1338 __be16 proto = *((__be16 *)(skb->data + inner_ip_off - 1339 ETH_HLEN - 2)); 1340 1341 /* We only support inner iPv4/ipv6. If we don't see the 1342 * correct protocol ID, it must be a loopback packet where 1343 * the offsets are off by 4. 1344 */ 1345 if (proto != htons(ETH_P_IP) && proto != htons(ETH_P_IPV6)) 1346 loopback = true; 1347 } 1348 if (loopback) { 1349 /* internal loopback packet, subtract all offsets by 4 */ 1350 inner_ip_off -= 4; 1351 inner_mac_off -= 4; 1352 outer_ip_off -= 4; 1353 } 1354 1355 nw_off = inner_ip_off - ETH_HLEN; 1356 skb_set_network_header(skb, nw_off); 1357 if (tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_IP_TYPE) { 1358 struct ipv6hdr *iph = ipv6_hdr(skb); 1359 1360 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr)); 1361 len = skb->len - skb_transport_offset(skb); 1362 th = tcp_hdr(skb); 1363 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0); 1364 } else { 1365 struct iphdr *iph = ip_hdr(skb); 1366 1367 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr)); 1368 len = skb->len - skb_transport_offset(skb); 1369 th = tcp_hdr(skb); 1370 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0); 1371 } 1372 1373 if (inner_mac_off) { /* tunnel */ 1374 __be16 proto = *((__be16 *)(skb->data + outer_ip_off - 1375 ETH_HLEN - 2)); 1376 1377 bnxt_gro_tunnel(skb, proto); 1378 } 1379 #endif 1380 return skb; 1381 } 1382 1383 static struct sk_buff *bnxt_gro_func_5750x(struct bnxt_tpa_info *tpa_info, 1384 int payload_off, int tcp_ts, 1385 struct sk_buff *skb) 1386 { 1387 #ifdef CONFIG_INET 1388 u16 outer_ip_off, inner_ip_off, inner_mac_off; 1389 u32 hdr_info = tpa_info->hdr_info; 1390 int iphdr_len, nw_off; 1391 1392 inner_ip_off = BNXT_TPA_INNER_L3_OFF(hdr_info); 1393 inner_mac_off = BNXT_TPA_INNER_L2_OFF(hdr_info); 1394 outer_ip_off = BNXT_TPA_OUTER_L3_OFF(hdr_info); 1395 1396 nw_off = inner_ip_off - ETH_HLEN; 1397 skb_set_network_header(skb, nw_off); 1398 iphdr_len = (tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_IP_TYPE) ? 1399 sizeof(struct ipv6hdr) : sizeof(struct iphdr); 1400 skb_set_transport_header(skb, nw_off + iphdr_len); 1401 1402 if (inner_mac_off) { /* tunnel */ 1403 __be16 proto = *((__be16 *)(skb->data + outer_ip_off - 1404 ETH_HLEN - 2)); 1405 1406 bnxt_gro_tunnel(skb, proto); 1407 } 1408 #endif 1409 return skb; 1410 } 1411 1412 #define BNXT_IPV4_HDR_SIZE (sizeof(struct iphdr) + sizeof(struct tcphdr)) 1413 #define BNXT_IPV6_HDR_SIZE (sizeof(struct ipv6hdr) + sizeof(struct tcphdr)) 1414 1415 static struct sk_buff *bnxt_gro_func_5730x(struct bnxt_tpa_info *tpa_info, 1416 int payload_off, int tcp_ts, 1417 struct sk_buff *skb) 1418 { 1419 #ifdef CONFIG_INET 1420 struct tcphdr *th; 1421 int len, nw_off, tcp_opt_len = 0; 1422 1423 if (tcp_ts) 1424 tcp_opt_len = 12; 1425 1426 if (tpa_info->gso_type == SKB_GSO_TCPV4) { 1427 struct iphdr *iph; 1428 1429 nw_off = payload_off - BNXT_IPV4_HDR_SIZE - tcp_opt_len - 1430 ETH_HLEN; 1431 skb_set_network_header(skb, nw_off); 1432 iph = ip_hdr(skb); 1433 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr)); 1434 len = skb->len - skb_transport_offset(skb); 1435 th = tcp_hdr(skb); 1436 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0); 1437 } else if (tpa_info->gso_type == SKB_GSO_TCPV6) { 1438 struct ipv6hdr *iph; 1439 1440 nw_off = payload_off - BNXT_IPV6_HDR_SIZE - tcp_opt_len - 1441 ETH_HLEN; 1442 skb_set_network_header(skb, nw_off); 1443 iph = ipv6_hdr(skb); 1444 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr)); 1445 len = skb->len - skb_transport_offset(skb); 1446 th = tcp_hdr(skb); 1447 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0); 1448 } else { 1449 dev_kfree_skb_any(skb); 1450 return NULL; 1451 } 1452 1453 if (nw_off) /* tunnel */ 1454 bnxt_gro_tunnel(skb, skb->protocol); 1455 #endif 1456 return skb; 1457 } 1458 1459 static inline struct sk_buff *bnxt_gro_skb(struct bnxt *bp, 1460 struct bnxt_tpa_info *tpa_info, 1461 struct rx_tpa_end_cmp *tpa_end, 1462 struct rx_tpa_end_cmp_ext *tpa_end1, 1463 struct sk_buff *skb) 1464 { 1465 #ifdef CONFIG_INET 1466 int payload_off; 1467 u16 segs; 1468 1469 segs = TPA_END_TPA_SEGS(tpa_end); 1470 if (segs == 1) 1471 return skb; 1472 1473 NAPI_GRO_CB(skb)->count = segs; 1474 skb_shinfo(skb)->gso_size = 1475 le32_to_cpu(tpa_end1->rx_tpa_end_cmp_seg_len); 1476 skb_shinfo(skb)->gso_type = tpa_info->gso_type; 1477 if (bp->flags & BNXT_FLAG_CHIP_P5) 1478 payload_off = TPA_END_PAYLOAD_OFF_P5(tpa_end1); 1479 else 1480 payload_off = TPA_END_PAYLOAD_OFF(tpa_end); 1481 skb = bp->gro_func(tpa_info, payload_off, TPA_END_GRO_TS(tpa_end), skb); 1482 if (likely(skb)) 1483 tcp_gro_complete(skb); 1484 #endif 1485 return skb; 1486 } 1487 1488 /* Given the cfa_code of a received packet determine which 1489 * netdev (vf-rep or PF) the packet is destined to. 1490 */ 1491 static struct net_device *bnxt_get_pkt_dev(struct bnxt *bp, u16 cfa_code) 1492 { 1493 struct net_device *dev = bnxt_get_vf_rep(bp, cfa_code); 1494 1495 /* if vf-rep dev is NULL, the must belongs to the PF */ 1496 return dev ? dev : bp->dev; 1497 } 1498 1499 static inline struct sk_buff *bnxt_tpa_end(struct bnxt *bp, 1500 struct bnxt_cp_ring_info *cpr, 1501 u32 *raw_cons, 1502 struct rx_tpa_end_cmp *tpa_end, 1503 struct rx_tpa_end_cmp_ext *tpa_end1, 1504 u8 *event) 1505 { 1506 struct bnxt_napi *bnapi = cpr->bnapi; 1507 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 1508 u8 *data_ptr, agg_bufs; 1509 unsigned int len; 1510 struct bnxt_tpa_info *tpa_info; 1511 dma_addr_t mapping; 1512 struct sk_buff *skb; 1513 u16 idx = 0, agg_id; 1514 void *data; 1515 bool gro; 1516 1517 if (unlikely(bnapi->in_reset)) { 1518 int rc = bnxt_discard_rx(bp, cpr, raw_cons, tpa_end); 1519 1520 if (rc < 0) 1521 return ERR_PTR(-EBUSY); 1522 return NULL; 1523 } 1524 1525 if (bp->flags & BNXT_FLAG_CHIP_P5) { 1526 agg_id = TPA_END_AGG_ID_P5(tpa_end); 1527 agg_id = bnxt_lookup_agg_idx(rxr, agg_id); 1528 agg_bufs = TPA_END_AGG_BUFS_P5(tpa_end1); 1529 tpa_info = &rxr->rx_tpa[agg_id]; 1530 if (unlikely(agg_bufs != tpa_info->agg_count)) { 1531 netdev_warn(bp->dev, "TPA end agg_buf %d != expected agg_bufs %d\n", 1532 agg_bufs, tpa_info->agg_count); 1533 agg_bufs = tpa_info->agg_count; 1534 } 1535 tpa_info->agg_count = 0; 1536 *event |= BNXT_AGG_EVENT; 1537 bnxt_free_agg_idx(rxr, agg_id); 1538 idx = agg_id; 1539 gro = !!(bp->flags & BNXT_FLAG_GRO); 1540 } else { 1541 agg_id = TPA_END_AGG_ID(tpa_end); 1542 agg_bufs = TPA_END_AGG_BUFS(tpa_end); 1543 tpa_info = &rxr->rx_tpa[agg_id]; 1544 idx = RING_CMP(*raw_cons); 1545 if (agg_bufs) { 1546 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, raw_cons)) 1547 return ERR_PTR(-EBUSY); 1548 1549 *event |= BNXT_AGG_EVENT; 1550 idx = NEXT_CMP(idx); 1551 } 1552 gro = !!TPA_END_GRO(tpa_end); 1553 } 1554 data = tpa_info->data; 1555 data_ptr = tpa_info->data_ptr; 1556 prefetch(data_ptr); 1557 len = tpa_info->len; 1558 mapping = tpa_info->mapping; 1559 1560 if (unlikely(agg_bufs > MAX_SKB_FRAGS || TPA_END_ERRORS(tpa_end1))) { 1561 bnxt_abort_tpa(cpr, idx, agg_bufs); 1562 if (agg_bufs > MAX_SKB_FRAGS) 1563 netdev_warn(bp->dev, "TPA frags %d exceeded MAX_SKB_FRAGS %d\n", 1564 agg_bufs, (int)MAX_SKB_FRAGS); 1565 return NULL; 1566 } 1567 1568 if (len <= bp->rx_copy_thresh) { 1569 skb = bnxt_copy_skb(bnapi, data_ptr, len, mapping); 1570 if (!skb) { 1571 bnxt_abort_tpa(cpr, idx, agg_bufs); 1572 return NULL; 1573 } 1574 } else { 1575 u8 *new_data; 1576 dma_addr_t new_mapping; 1577 1578 new_data = __bnxt_alloc_rx_data(bp, &new_mapping, GFP_ATOMIC); 1579 if (!new_data) { 1580 bnxt_abort_tpa(cpr, idx, agg_bufs); 1581 return NULL; 1582 } 1583 1584 tpa_info->data = new_data; 1585 tpa_info->data_ptr = new_data + bp->rx_offset; 1586 tpa_info->mapping = new_mapping; 1587 1588 skb = build_skb(data, 0); 1589 dma_unmap_single_attrs(&bp->pdev->dev, mapping, 1590 bp->rx_buf_use_size, bp->rx_dir, 1591 DMA_ATTR_WEAK_ORDERING); 1592 1593 if (!skb) { 1594 kfree(data); 1595 bnxt_abort_tpa(cpr, idx, agg_bufs); 1596 return NULL; 1597 } 1598 skb_reserve(skb, bp->rx_offset); 1599 skb_put(skb, len); 1600 } 1601 1602 if (agg_bufs) { 1603 skb = bnxt_rx_pages(bp, cpr, skb, idx, agg_bufs, true); 1604 if (!skb) { 1605 /* Page reuse already handled by bnxt_rx_pages(). */ 1606 return NULL; 1607 } 1608 } 1609 1610 skb->protocol = 1611 eth_type_trans(skb, bnxt_get_pkt_dev(bp, tpa_info->cfa_code)); 1612 1613 if (tpa_info->hash_type != PKT_HASH_TYPE_NONE) 1614 skb_set_hash(skb, tpa_info->rss_hash, tpa_info->hash_type); 1615 1616 if ((tpa_info->flags2 & RX_CMP_FLAGS2_META_FORMAT_VLAN) && 1617 (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) { 1618 u16 vlan_proto = tpa_info->metadata >> 1619 RX_CMP_FLAGS2_METADATA_TPID_SFT; 1620 u16 vtag = tpa_info->metadata & RX_CMP_FLAGS2_METADATA_TCI_MASK; 1621 1622 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag); 1623 } 1624 1625 skb_checksum_none_assert(skb); 1626 if (likely(tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_L4_CS_CALC)) { 1627 skb->ip_summed = CHECKSUM_UNNECESSARY; 1628 skb->csum_level = 1629 (tpa_info->flags2 & RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3; 1630 } 1631 1632 if (gro) 1633 skb = bnxt_gro_skb(bp, tpa_info, tpa_end, tpa_end1, skb); 1634 1635 return skb; 1636 } 1637 1638 static void bnxt_tpa_agg(struct bnxt *bp, struct bnxt_rx_ring_info *rxr, 1639 struct rx_agg_cmp *rx_agg) 1640 { 1641 u16 agg_id = TPA_AGG_AGG_ID(rx_agg); 1642 struct bnxt_tpa_info *tpa_info; 1643 1644 agg_id = bnxt_lookup_agg_idx(rxr, agg_id); 1645 tpa_info = &rxr->rx_tpa[agg_id]; 1646 BUG_ON(tpa_info->agg_count >= MAX_SKB_FRAGS); 1647 tpa_info->agg_arr[tpa_info->agg_count++] = *rx_agg; 1648 } 1649 1650 static void bnxt_deliver_skb(struct bnxt *bp, struct bnxt_napi *bnapi, 1651 struct sk_buff *skb) 1652 { 1653 if (skb->dev != bp->dev) { 1654 /* this packet belongs to a vf-rep */ 1655 bnxt_vf_rep_rx(bp, skb); 1656 return; 1657 } 1658 skb_record_rx_queue(skb, bnapi->index); 1659 napi_gro_receive(&bnapi->napi, skb); 1660 } 1661 1662 /* returns the following: 1663 * 1 - 1 packet successfully received 1664 * 0 - successful TPA_START, packet not completed yet 1665 * -EBUSY - completion ring does not have all the agg buffers yet 1666 * -ENOMEM - packet aborted due to out of memory 1667 * -EIO - packet aborted due to hw error indicated in BD 1668 */ 1669 static int bnxt_rx_pkt(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, 1670 u32 *raw_cons, u8 *event) 1671 { 1672 struct bnxt_napi *bnapi = cpr->bnapi; 1673 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 1674 struct net_device *dev = bp->dev; 1675 struct rx_cmp *rxcmp; 1676 struct rx_cmp_ext *rxcmp1; 1677 u32 tmp_raw_cons = *raw_cons; 1678 u16 cfa_code, cons, prod, cp_cons = RING_CMP(tmp_raw_cons); 1679 struct bnxt_sw_rx_bd *rx_buf; 1680 unsigned int len; 1681 u8 *data_ptr, agg_bufs, cmp_type; 1682 dma_addr_t dma_addr; 1683 struct sk_buff *skb; 1684 void *data; 1685 int rc = 0; 1686 u32 misc; 1687 1688 rxcmp = (struct rx_cmp *) 1689 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 1690 1691 cmp_type = RX_CMP_TYPE(rxcmp); 1692 1693 if (cmp_type == CMP_TYPE_RX_TPA_AGG_CMP) { 1694 bnxt_tpa_agg(bp, rxr, (struct rx_agg_cmp *)rxcmp); 1695 goto next_rx_no_prod_no_len; 1696 } 1697 1698 tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons); 1699 cp_cons = RING_CMP(tmp_raw_cons); 1700 rxcmp1 = (struct rx_cmp_ext *) 1701 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 1702 1703 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons)) 1704 return -EBUSY; 1705 1706 prod = rxr->rx_prod; 1707 1708 if (cmp_type == CMP_TYPE_RX_L2_TPA_START_CMP) { 1709 bnxt_tpa_start(bp, rxr, (struct rx_tpa_start_cmp *)rxcmp, 1710 (struct rx_tpa_start_cmp_ext *)rxcmp1); 1711 1712 *event |= BNXT_RX_EVENT; 1713 goto next_rx_no_prod_no_len; 1714 1715 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) { 1716 skb = bnxt_tpa_end(bp, cpr, &tmp_raw_cons, 1717 (struct rx_tpa_end_cmp *)rxcmp, 1718 (struct rx_tpa_end_cmp_ext *)rxcmp1, event); 1719 1720 if (IS_ERR(skb)) 1721 return -EBUSY; 1722 1723 rc = -ENOMEM; 1724 if (likely(skb)) { 1725 bnxt_deliver_skb(bp, bnapi, skb); 1726 rc = 1; 1727 } 1728 *event |= BNXT_RX_EVENT; 1729 goto next_rx_no_prod_no_len; 1730 } 1731 1732 cons = rxcmp->rx_cmp_opaque; 1733 if (unlikely(cons != rxr->rx_next_cons)) { 1734 int rc1 = bnxt_discard_rx(bp, cpr, raw_cons, rxcmp); 1735 1736 netdev_warn(bp->dev, "RX cons %x != expected cons %x\n", 1737 cons, rxr->rx_next_cons); 1738 bnxt_sched_reset(bp, rxr); 1739 return rc1; 1740 } 1741 rx_buf = &rxr->rx_buf_ring[cons]; 1742 data = rx_buf->data; 1743 data_ptr = rx_buf->data_ptr; 1744 prefetch(data_ptr); 1745 1746 misc = le32_to_cpu(rxcmp->rx_cmp_misc_v1); 1747 agg_bufs = (misc & RX_CMP_AGG_BUFS) >> RX_CMP_AGG_BUFS_SHIFT; 1748 1749 if (agg_bufs) { 1750 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons)) 1751 return -EBUSY; 1752 1753 cp_cons = NEXT_CMP(cp_cons); 1754 *event |= BNXT_AGG_EVENT; 1755 } 1756 *event |= BNXT_RX_EVENT; 1757 1758 rx_buf->data = NULL; 1759 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L2_ERRORS) { 1760 u32 rx_err = le32_to_cpu(rxcmp1->rx_cmp_cfa_code_errors_v2); 1761 1762 bnxt_reuse_rx_data(rxr, cons, data); 1763 if (agg_bufs) 1764 bnxt_reuse_rx_agg_bufs(cpr, cp_cons, 0, agg_bufs, 1765 false); 1766 1767 rc = -EIO; 1768 if (rx_err & RX_CMPL_ERRORS_BUFFER_ERROR_MASK) { 1769 bnapi->cp_ring.rx_buf_errors++; 1770 if (!(bp->flags & BNXT_FLAG_CHIP_P5)) { 1771 netdev_warn(bp->dev, "RX buffer error %x\n", 1772 rx_err); 1773 bnxt_sched_reset(bp, rxr); 1774 } 1775 } 1776 goto next_rx_no_len; 1777 } 1778 1779 len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT; 1780 dma_addr = rx_buf->mapping; 1781 1782 if (bnxt_rx_xdp(bp, rxr, cons, data, &data_ptr, &len, event)) { 1783 rc = 1; 1784 goto next_rx; 1785 } 1786 1787 if (len <= bp->rx_copy_thresh) { 1788 skb = bnxt_copy_skb(bnapi, data_ptr, len, dma_addr); 1789 bnxt_reuse_rx_data(rxr, cons, data); 1790 if (!skb) { 1791 if (agg_bufs) 1792 bnxt_reuse_rx_agg_bufs(cpr, cp_cons, 0, 1793 agg_bufs, false); 1794 rc = -ENOMEM; 1795 goto next_rx; 1796 } 1797 } else { 1798 u32 payload; 1799 1800 if (rx_buf->data_ptr == data_ptr) 1801 payload = misc & RX_CMP_PAYLOAD_OFFSET; 1802 else 1803 payload = 0; 1804 skb = bp->rx_skb_func(bp, rxr, cons, data, data_ptr, dma_addr, 1805 payload | len); 1806 if (!skb) { 1807 rc = -ENOMEM; 1808 goto next_rx; 1809 } 1810 } 1811 1812 if (agg_bufs) { 1813 skb = bnxt_rx_pages(bp, cpr, skb, cp_cons, agg_bufs, false); 1814 if (!skb) { 1815 rc = -ENOMEM; 1816 goto next_rx; 1817 } 1818 } 1819 1820 if (RX_CMP_HASH_VALID(rxcmp)) { 1821 u32 hash_type = RX_CMP_HASH_TYPE(rxcmp); 1822 enum pkt_hash_types type = PKT_HASH_TYPE_L4; 1823 1824 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */ 1825 if (hash_type != 1 && hash_type != 3) 1826 type = PKT_HASH_TYPE_L3; 1827 skb_set_hash(skb, le32_to_cpu(rxcmp->rx_cmp_rss_hash), type); 1828 } 1829 1830 cfa_code = RX_CMP_CFA_CODE(rxcmp1); 1831 skb->protocol = eth_type_trans(skb, bnxt_get_pkt_dev(bp, cfa_code)); 1832 1833 if ((rxcmp1->rx_cmp_flags2 & 1834 cpu_to_le32(RX_CMP_FLAGS2_META_FORMAT_VLAN)) && 1835 (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) { 1836 u32 meta_data = le32_to_cpu(rxcmp1->rx_cmp_meta_data); 1837 u16 vtag = meta_data & RX_CMP_FLAGS2_METADATA_TCI_MASK; 1838 u16 vlan_proto = meta_data >> RX_CMP_FLAGS2_METADATA_TPID_SFT; 1839 1840 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag); 1841 } 1842 1843 skb_checksum_none_assert(skb); 1844 if (RX_CMP_L4_CS_OK(rxcmp1)) { 1845 if (dev->features & NETIF_F_RXCSUM) { 1846 skb->ip_summed = CHECKSUM_UNNECESSARY; 1847 skb->csum_level = RX_CMP_ENCAP(rxcmp1); 1848 } 1849 } else { 1850 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS) { 1851 if (dev->features & NETIF_F_RXCSUM) 1852 bnapi->cp_ring.rx_l4_csum_errors++; 1853 } 1854 } 1855 1856 bnxt_deliver_skb(bp, bnapi, skb); 1857 rc = 1; 1858 1859 next_rx: 1860 cpr->rx_packets += 1; 1861 cpr->rx_bytes += len; 1862 1863 next_rx_no_len: 1864 rxr->rx_prod = NEXT_RX(prod); 1865 rxr->rx_next_cons = NEXT_RX(cons); 1866 1867 next_rx_no_prod_no_len: 1868 *raw_cons = tmp_raw_cons; 1869 1870 return rc; 1871 } 1872 1873 /* In netpoll mode, if we are using a combined completion ring, we need to 1874 * discard the rx packets and recycle the buffers. 1875 */ 1876 static int bnxt_force_rx_discard(struct bnxt *bp, 1877 struct bnxt_cp_ring_info *cpr, 1878 u32 *raw_cons, u8 *event) 1879 { 1880 u32 tmp_raw_cons = *raw_cons; 1881 struct rx_cmp_ext *rxcmp1; 1882 struct rx_cmp *rxcmp; 1883 u16 cp_cons; 1884 u8 cmp_type; 1885 1886 cp_cons = RING_CMP(tmp_raw_cons); 1887 rxcmp = (struct rx_cmp *) 1888 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 1889 1890 tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons); 1891 cp_cons = RING_CMP(tmp_raw_cons); 1892 rxcmp1 = (struct rx_cmp_ext *) 1893 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 1894 1895 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons)) 1896 return -EBUSY; 1897 1898 cmp_type = RX_CMP_TYPE(rxcmp); 1899 if (cmp_type == CMP_TYPE_RX_L2_CMP) { 1900 rxcmp1->rx_cmp_cfa_code_errors_v2 |= 1901 cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR); 1902 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) { 1903 struct rx_tpa_end_cmp_ext *tpa_end1; 1904 1905 tpa_end1 = (struct rx_tpa_end_cmp_ext *)rxcmp1; 1906 tpa_end1->rx_tpa_end_cmp_errors_v2 |= 1907 cpu_to_le32(RX_TPA_END_CMP_ERRORS); 1908 } 1909 return bnxt_rx_pkt(bp, cpr, raw_cons, event); 1910 } 1911 1912 u32 bnxt_fw_health_readl(struct bnxt *bp, int reg_idx) 1913 { 1914 struct bnxt_fw_health *fw_health = bp->fw_health; 1915 u32 reg = fw_health->regs[reg_idx]; 1916 u32 reg_type, reg_off, val = 0; 1917 1918 reg_type = BNXT_FW_HEALTH_REG_TYPE(reg); 1919 reg_off = BNXT_FW_HEALTH_REG_OFF(reg); 1920 switch (reg_type) { 1921 case BNXT_FW_HEALTH_REG_TYPE_CFG: 1922 pci_read_config_dword(bp->pdev, reg_off, &val); 1923 break; 1924 case BNXT_FW_HEALTH_REG_TYPE_GRC: 1925 reg_off = fw_health->mapped_regs[reg_idx]; 1926 /* fall through */ 1927 case BNXT_FW_HEALTH_REG_TYPE_BAR0: 1928 val = readl(bp->bar0 + reg_off); 1929 break; 1930 case BNXT_FW_HEALTH_REG_TYPE_BAR1: 1931 val = readl(bp->bar1 + reg_off); 1932 break; 1933 } 1934 if (reg_idx == BNXT_FW_RESET_INPROG_REG) 1935 val &= fw_health->fw_reset_inprog_reg_mask; 1936 return val; 1937 } 1938 1939 #define BNXT_GET_EVENT_PORT(data) \ 1940 ((data) & \ 1941 ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK) 1942 1943 static int bnxt_async_event_process(struct bnxt *bp, 1944 struct hwrm_async_event_cmpl *cmpl) 1945 { 1946 u16 event_id = le16_to_cpu(cmpl->event_id); 1947 1948 /* TODO CHIMP_FW: Define event id's for link change, error etc */ 1949 switch (event_id) { 1950 case ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE: { 1951 u32 data1 = le32_to_cpu(cmpl->event_data1); 1952 struct bnxt_link_info *link_info = &bp->link_info; 1953 1954 if (BNXT_VF(bp)) 1955 goto async_event_process_exit; 1956 1957 /* print unsupported speed warning in forced speed mode only */ 1958 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED) && 1959 (data1 & 0x20000)) { 1960 u16 fw_speed = link_info->force_link_speed; 1961 u32 speed = bnxt_fw_to_ethtool_speed(fw_speed); 1962 1963 if (speed != SPEED_UNKNOWN) 1964 netdev_warn(bp->dev, "Link speed %d no longer supported\n", 1965 speed); 1966 } 1967 set_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT, &bp->sp_event); 1968 } 1969 /* fall through */ 1970 case ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE: 1971 case ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE: 1972 set_bit(BNXT_LINK_CFG_CHANGE_SP_EVENT, &bp->sp_event); 1973 /* fall through */ 1974 case ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE: 1975 set_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event); 1976 break; 1977 case ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD: 1978 set_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event); 1979 break; 1980 case ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED: { 1981 u32 data1 = le32_to_cpu(cmpl->event_data1); 1982 u16 port_id = BNXT_GET_EVENT_PORT(data1); 1983 1984 if (BNXT_VF(bp)) 1985 break; 1986 1987 if (bp->pf.port_id != port_id) 1988 break; 1989 1990 set_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event); 1991 break; 1992 } 1993 case ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE: 1994 if (BNXT_PF(bp)) 1995 goto async_event_process_exit; 1996 set_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event); 1997 break; 1998 case ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY: { 1999 u32 data1 = le32_to_cpu(cmpl->event_data1); 2000 2001 if (!bp->fw_health) 2002 goto async_event_process_exit; 2003 2004 bp->fw_reset_timestamp = jiffies; 2005 bp->fw_reset_min_dsecs = cmpl->timestamp_lo; 2006 if (!bp->fw_reset_min_dsecs) 2007 bp->fw_reset_min_dsecs = BNXT_DFLT_FW_RST_MIN_DSECS; 2008 bp->fw_reset_max_dsecs = le16_to_cpu(cmpl->timestamp_hi); 2009 if (!bp->fw_reset_max_dsecs) 2010 bp->fw_reset_max_dsecs = BNXT_DFLT_FW_RST_MAX_DSECS; 2011 if (EVENT_DATA1_RESET_NOTIFY_FATAL(data1)) { 2012 netdev_warn(bp->dev, "Firmware fatal reset event received\n"); 2013 set_bit(BNXT_STATE_FW_FATAL_COND, &bp->state); 2014 } else { 2015 netdev_warn(bp->dev, "Firmware non-fatal reset event received, max wait time %d msec\n", 2016 bp->fw_reset_max_dsecs * 100); 2017 } 2018 set_bit(BNXT_FW_RESET_NOTIFY_SP_EVENT, &bp->sp_event); 2019 break; 2020 } 2021 case ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY: { 2022 struct bnxt_fw_health *fw_health = bp->fw_health; 2023 u32 data1 = le32_to_cpu(cmpl->event_data1); 2024 2025 if (!fw_health) 2026 goto async_event_process_exit; 2027 2028 fw_health->enabled = EVENT_DATA1_RECOVERY_ENABLED(data1); 2029 fw_health->master = EVENT_DATA1_RECOVERY_MASTER_FUNC(data1); 2030 if (!fw_health->enabled) 2031 break; 2032 2033 if (netif_msg_drv(bp)) 2034 netdev_info(bp->dev, "Error recovery info: error recovery[%d], master[%d], reset count[0x%x], health status: 0x%x\n", 2035 fw_health->enabled, fw_health->master, 2036 bnxt_fw_health_readl(bp, 2037 BNXT_FW_RESET_CNT_REG), 2038 bnxt_fw_health_readl(bp, 2039 BNXT_FW_HEALTH_REG)); 2040 fw_health->tmr_multiplier = 2041 DIV_ROUND_UP(fw_health->polling_dsecs * HZ, 2042 bp->current_interval * 10); 2043 fw_health->tmr_counter = fw_health->tmr_multiplier; 2044 fw_health->last_fw_heartbeat = 2045 bnxt_fw_health_readl(bp, BNXT_FW_HEARTBEAT_REG); 2046 fw_health->last_fw_reset_cnt = 2047 bnxt_fw_health_readl(bp, BNXT_FW_RESET_CNT_REG); 2048 goto async_event_process_exit; 2049 } 2050 default: 2051 goto async_event_process_exit; 2052 } 2053 bnxt_queue_sp_work(bp); 2054 async_event_process_exit: 2055 bnxt_ulp_async_events(bp, cmpl); 2056 return 0; 2057 } 2058 2059 static int bnxt_hwrm_handler(struct bnxt *bp, struct tx_cmp *txcmp) 2060 { 2061 u16 cmpl_type = TX_CMP_TYPE(txcmp), vf_id, seq_id; 2062 struct hwrm_cmpl *h_cmpl = (struct hwrm_cmpl *)txcmp; 2063 struct hwrm_fwd_req_cmpl *fwd_req_cmpl = 2064 (struct hwrm_fwd_req_cmpl *)txcmp; 2065 2066 switch (cmpl_type) { 2067 case CMPL_BASE_TYPE_HWRM_DONE: 2068 seq_id = le16_to_cpu(h_cmpl->sequence_id); 2069 if (seq_id == bp->hwrm_intr_seq_id) 2070 bp->hwrm_intr_seq_id = (u16)~bp->hwrm_intr_seq_id; 2071 else 2072 netdev_err(bp->dev, "Invalid hwrm seq id %d\n", seq_id); 2073 break; 2074 2075 case CMPL_BASE_TYPE_HWRM_FWD_REQ: 2076 vf_id = le16_to_cpu(fwd_req_cmpl->source_id); 2077 2078 if ((vf_id < bp->pf.first_vf_id) || 2079 (vf_id >= bp->pf.first_vf_id + bp->pf.active_vfs)) { 2080 netdev_err(bp->dev, "Msg contains invalid VF id %x\n", 2081 vf_id); 2082 return -EINVAL; 2083 } 2084 2085 set_bit(vf_id - bp->pf.first_vf_id, bp->pf.vf_event_bmap); 2086 set_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event); 2087 bnxt_queue_sp_work(bp); 2088 break; 2089 2090 case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT: 2091 bnxt_async_event_process(bp, 2092 (struct hwrm_async_event_cmpl *)txcmp); 2093 2094 default: 2095 break; 2096 } 2097 2098 return 0; 2099 } 2100 2101 static irqreturn_t bnxt_msix(int irq, void *dev_instance) 2102 { 2103 struct bnxt_napi *bnapi = dev_instance; 2104 struct bnxt *bp = bnapi->bp; 2105 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 2106 u32 cons = RING_CMP(cpr->cp_raw_cons); 2107 2108 cpr->event_ctr++; 2109 prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]); 2110 napi_schedule(&bnapi->napi); 2111 return IRQ_HANDLED; 2112 } 2113 2114 static inline int bnxt_has_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr) 2115 { 2116 u32 raw_cons = cpr->cp_raw_cons; 2117 u16 cons = RING_CMP(raw_cons); 2118 struct tx_cmp *txcmp; 2119 2120 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]; 2121 2122 return TX_CMP_VALID(txcmp, raw_cons); 2123 } 2124 2125 static irqreturn_t bnxt_inta(int irq, void *dev_instance) 2126 { 2127 struct bnxt_napi *bnapi = dev_instance; 2128 struct bnxt *bp = bnapi->bp; 2129 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 2130 u32 cons = RING_CMP(cpr->cp_raw_cons); 2131 u32 int_status; 2132 2133 prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]); 2134 2135 if (!bnxt_has_work(bp, cpr)) { 2136 int_status = readl(bp->bar0 + BNXT_CAG_REG_LEGACY_INT_STATUS); 2137 /* return if erroneous interrupt */ 2138 if (!(int_status & (0x10000 << cpr->cp_ring_struct.fw_ring_id))) 2139 return IRQ_NONE; 2140 } 2141 2142 /* disable ring IRQ */ 2143 BNXT_CP_DB_IRQ_DIS(cpr->cp_db.doorbell); 2144 2145 /* Return here if interrupt is shared and is disabled. */ 2146 if (unlikely(atomic_read(&bp->intr_sem) != 0)) 2147 return IRQ_HANDLED; 2148 2149 napi_schedule(&bnapi->napi); 2150 return IRQ_HANDLED; 2151 } 2152 2153 static int __bnxt_poll_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, 2154 int budget) 2155 { 2156 struct bnxt_napi *bnapi = cpr->bnapi; 2157 u32 raw_cons = cpr->cp_raw_cons; 2158 u32 cons; 2159 int tx_pkts = 0; 2160 int rx_pkts = 0; 2161 u8 event = 0; 2162 struct tx_cmp *txcmp; 2163 2164 cpr->has_more_work = 0; 2165 cpr->had_work_done = 1; 2166 while (1) { 2167 int rc; 2168 2169 cons = RING_CMP(raw_cons); 2170 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]; 2171 2172 if (!TX_CMP_VALID(txcmp, raw_cons)) 2173 break; 2174 2175 /* The valid test of the entry must be done first before 2176 * reading any further. 2177 */ 2178 dma_rmb(); 2179 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_TX_L2_CMP) { 2180 tx_pkts++; 2181 /* return full budget so NAPI will complete. */ 2182 if (unlikely(tx_pkts > bp->tx_wake_thresh)) { 2183 rx_pkts = budget; 2184 raw_cons = NEXT_RAW_CMP(raw_cons); 2185 if (budget) 2186 cpr->has_more_work = 1; 2187 break; 2188 } 2189 } else if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) { 2190 if (likely(budget)) 2191 rc = bnxt_rx_pkt(bp, cpr, &raw_cons, &event); 2192 else 2193 rc = bnxt_force_rx_discard(bp, cpr, &raw_cons, 2194 &event); 2195 if (likely(rc >= 0)) 2196 rx_pkts += rc; 2197 /* Increment rx_pkts when rc is -ENOMEM to count towards 2198 * the NAPI budget. Otherwise, we may potentially loop 2199 * here forever if we consistently cannot allocate 2200 * buffers. 2201 */ 2202 else if (rc == -ENOMEM && budget) 2203 rx_pkts++; 2204 else if (rc == -EBUSY) /* partial completion */ 2205 break; 2206 } else if (unlikely((TX_CMP_TYPE(txcmp) == 2207 CMPL_BASE_TYPE_HWRM_DONE) || 2208 (TX_CMP_TYPE(txcmp) == 2209 CMPL_BASE_TYPE_HWRM_FWD_REQ) || 2210 (TX_CMP_TYPE(txcmp) == 2211 CMPL_BASE_TYPE_HWRM_ASYNC_EVENT))) { 2212 bnxt_hwrm_handler(bp, txcmp); 2213 } 2214 raw_cons = NEXT_RAW_CMP(raw_cons); 2215 2216 if (rx_pkts && rx_pkts == budget) { 2217 cpr->has_more_work = 1; 2218 break; 2219 } 2220 } 2221 2222 if (event & BNXT_REDIRECT_EVENT) 2223 xdp_do_flush_map(); 2224 2225 if (event & BNXT_TX_EVENT) { 2226 struct bnxt_tx_ring_info *txr = bnapi->tx_ring; 2227 u16 prod = txr->tx_prod; 2228 2229 /* Sync BD data before updating doorbell */ 2230 wmb(); 2231 2232 bnxt_db_write_relaxed(bp, &txr->tx_db, prod); 2233 } 2234 2235 cpr->cp_raw_cons = raw_cons; 2236 bnapi->tx_pkts += tx_pkts; 2237 bnapi->events |= event; 2238 return rx_pkts; 2239 } 2240 2241 static void __bnxt_poll_work_done(struct bnxt *bp, struct bnxt_napi *bnapi) 2242 { 2243 if (bnapi->tx_pkts) { 2244 bnapi->tx_int(bp, bnapi, bnapi->tx_pkts); 2245 bnapi->tx_pkts = 0; 2246 } 2247 2248 if (bnapi->events & BNXT_RX_EVENT) { 2249 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 2250 2251 if (bnapi->events & BNXT_AGG_EVENT) 2252 bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod); 2253 bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod); 2254 } 2255 bnapi->events = 0; 2256 } 2257 2258 static int bnxt_poll_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, 2259 int budget) 2260 { 2261 struct bnxt_napi *bnapi = cpr->bnapi; 2262 int rx_pkts; 2263 2264 rx_pkts = __bnxt_poll_work(bp, cpr, budget); 2265 2266 /* ACK completion ring before freeing tx ring and producing new 2267 * buffers in rx/agg rings to prevent overflowing the completion 2268 * ring. 2269 */ 2270 bnxt_db_cq(bp, &cpr->cp_db, cpr->cp_raw_cons); 2271 2272 __bnxt_poll_work_done(bp, bnapi); 2273 return rx_pkts; 2274 } 2275 2276 static int bnxt_poll_nitroa0(struct napi_struct *napi, int budget) 2277 { 2278 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi); 2279 struct bnxt *bp = bnapi->bp; 2280 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 2281 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 2282 struct tx_cmp *txcmp; 2283 struct rx_cmp_ext *rxcmp1; 2284 u32 cp_cons, tmp_raw_cons; 2285 u32 raw_cons = cpr->cp_raw_cons; 2286 u32 rx_pkts = 0; 2287 u8 event = 0; 2288 2289 while (1) { 2290 int rc; 2291 2292 cp_cons = RING_CMP(raw_cons); 2293 txcmp = &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 2294 2295 if (!TX_CMP_VALID(txcmp, raw_cons)) 2296 break; 2297 2298 if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) { 2299 tmp_raw_cons = NEXT_RAW_CMP(raw_cons); 2300 cp_cons = RING_CMP(tmp_raw_cons); 2301 rxcmp1 = (struct rx_cmp_ext *) 2302 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 2303 2304 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons)) 2305 break; 2306 2307 /* force an error to recycle the buffer */ 2308 rxcmp1->rx_cmp_cfa_code_errors_v2 |= 2309 cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR); 2310 2311 rc = bnxt_rx_pkt(bp, cpr, &raw_cons, &event); 2312 if (likely(rc == -EIO) && budget) 2313 rx_pkts++; 2314 else if (rc == -EBUSY) /* partial completion */ 2315 break; 2316 } else if (unlikely(TX_CMP_TYPE(txcmp) == 2317 CMPL_BASE_TYPE_HWRM_DONE)) { 2318 bnxt_hwrm_handler(bp, txcmp); 2319 } else { 2320 netdev_err(bp->dev, 2321 "Invalid completion received on special ring\n"); 2322 } 2323 raw_cons = NEXT_RAW_CMP(raw_cons); 2324 2325 if (rx_pkts == budget) 2326 break; 2327 } 2328 2329 cpr->cp_raw_cons = raw_cons; 2330 BNXT_DB_CQ(&cpr->cp_db, cpr->cp_raw_cons); 2331 bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod); 2332 2333 if (event & BNXT_AGG_EVENT) 2334 bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod); 2335 2336 if (!bnxt_has_work(bp, cpr) && rx_pkts < budget) { 2337 napi_complete_done(napi, rx_pkts); 2338 BNXT_DB_CQ_ARM(&cpr->cp_db, cpr->cp_raw_cons); 2339 } 2340 return rx_pkts; 2341 } 2342 2343 static int bnxt_poll(struct napi_struct *napi, int budget) 2344 { 2345 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi); 2346 struct bnxt *bp = bnapi->bp; 2347 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 2348 int work_done = 0; 2349 2350 while (1) { 2351 work_done += bnxt_poll_work(bp, cpr, budget - work_done); 2352 2353 if (work_done >= budget) { 2354 if (!budget) 2355 BNXT_DB_CQ_ARM(&cpr->cp_db, cpr->cp_raw_cons); 2356 break; 2357 } 2358 2359 if (!bnxt_has_work(bp, cpr)) { 2360 if (napi_complete_done(napi, work_done)) 2361 BNXT_DB_CQ_ARM(&cpr->cp_db, cpr->cp_raw_cons); 2362 break; 2363 } 2364 } 2365 if (bp->flags & BNXT_FLAG_DIM) { 2366 struct dim_sample dim_sample = {}; 2367 2368 dim_update_sample(cpr->event_ctr, 2369 cpr->rx_packets, 2370 cpr->rx_bytes, 2371 &dim_sample); 2372 net_dim(&cpr->dim, dim_sample); 2373 } 2374 return work_done; 2375 } 2376 2377 static int __bnxt_poll_cqs(struct bnxt *bp, struct bnxt_napi *bnapi, int budget) 2378 { 2379 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 2380 int i, work_done = 0; 2381 2382 for (i = 0; i < 2; i++) { 2383 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[i]; 2384 2385 if (cpr2) { 2386 work_done += __bnxt_poll_work(bp, cpr2, 2387 budget - work_done); 2388 cpr->has_more_work |= cpr2->has_more_work; 2389 } 2390 } 2391 return work_done; 2392 } 2393 2394 static void __bnxt_poll_cqs_done(struct bnxt *bp, struct bnxt_napi *bnapi, 2395 u64 dbr_type) 2396 { 2397 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 2398 int i; 2399 2400 for (i = 0; i < 2; i++) { 2401 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[i]; 2402 struct bnxt_db_info *db; 2403 2404 if (cpr2 && cpr2->had_work_done) { 2405 db = &cpr2->cp_db; 2406 writeq(db->db_key64 | dbr_type | 2407 RING_CMP(cpr2->cp_raw_cons), db->doorbell); 2408 cpr2->had_work_done = 0; 2409 } 2410 } 2411 __bnxt_poll_work_done(bp, bnapi); 2412 } 2413 2414 static int bnxt_poll_p5(struct napi_struct *napi, int budget) 2415 { 2416 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi); 2417 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 2418 u32 raw_cons = cpr->cp_raw_cons; 2419 struct bnxt *bp = bnapi->bp; 2420 struct nqe_cn *nqcmp; 2421 int work_done = 0; 2422 u32 cons; 2423 2424 if (cpr->has_more_work) { 2425 cpr->has_more_work = 0; 2426 work_done = __bnxt_poll_cqs(bp, bnapi, budget); 2427 } 2428 while (1) { 2429 cons = RING_CMP(raw_cons); 2430 nqcmp = &cpr->nq_desc_ring[CP_RING(cons)][CP_IDX(cons)]; 2431 2432 if (!NQ_CMP_VALID(nqcmp, raw_cons)) { 2433 if (cpr->has_more_work) 2434 break; 2435 2436 __bnxt_poll_cqs_done(bp, bnapi, DBR_TYPE_CQ_ARMALL); 2437 cpr->cp_raw_cons = raw_cons; 2438 if (napi_complete_done(napi, work_done)) 2439 BNXT_DB_NQ_ARM_P5(&cpr->cp_db, 2440 cpr->cp_raw_cons); 2441 return work_done; 2442 } 2443 2444 /* The valid test of the entry must be done first before 2445 * reading any further. 2446 */ 2447 dma_rmb(); 2448 2449 if (nqcmp->type == cpu_to_le16(NQ_CN_TYPE_CQ_NOTIFICATION)) { 2450 u32 idx = le32_to_cpu(nqcmp->cq_handle_low); 2451 struct bnxt_cp_ring_info *cpr2; 2452 2453 cpr2 = cpr->cp_ring_arr[idx]; 2454 work_done += __bnxt_poll_work(bp, cpr2, 2455 budget - work_done); 2456 cpr->has_more_work |= cpr2->has_more_work; 2457 } else { 2458 bnxt_hwrm_handler(bp, (struct tx_cmp *)nqcmp); 2459 } 2460 raw_cons = NEXT_RAW_CMP(raw_cons); 2461 } 2462 __bnxt_poll_cqs_done(bp, bnapi, DBR_TYPE_CQ); 2463 if (raw_cons != cpr->cp_raw_cons) { 2464 cpr->cp_raw_cons = raw_cons; 2465 BNXT_DB_NQ_P5(&cpr->cp_db, raw_cons); 2466 } 2467 return work_done; 2468 } 2469 2470 static void bnxt_free_tx_skbs(struct bnxt *bp) 2471 { 2472 int i, max_idx; 2473 struct pci_dev *pdev = bp->pdev; 2474 2475 if (!bp->tx_ring) 2476 return; 2477 2478 max_idx = bp->tx_nr_pages * TX_DESC_CNT; 2479 for (i = 0; i < bp->tx_nr_rings; i++) { 2480 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; 2481 int j; 2482 2483 for (j = 0; j < max_idx;) { 2484 struct bnxt_sw_tx_bd *tx_buf = &txr->tx_buf_ring[j]; 2485 struct sk_buff *skb; 2486 int k, last; 2487 2488 if (i < bp->tx_nr_rings_xdp && 2489 tx_buf->action == XDP_REDIRECT) { 2490 dma_unmap_single(&pdev->dev, 2491 dma_unmap_addr(tx_buf, mapping), 2492 dma_unmap_len(tx_buf, len), 2493 PCI_DMA_TODEVICE); 2494 xdp_return_frame(tx_buf->xdpf); 2495 tx_buf->action = 0; 2496 tx_buf->xdpf = NULL; 2497 j++; 2498 continue; 2499 } 2500 2501 skb = tx_buf->skb; 2502 if (!skb) { 2503 j++; 2504 continue; 2505 } 2506 2507 tx_buf->skb = NULL; 2508 2509 if (tx_buf->is_push) { 2510 dev_kfree_skb(skb); 2511 j += 2; 2512 continue; 2513 } 2514 2515 dma_unmap_single(&pdev->dev, 2516 dma_unmap_addr(tx_buf, mapping), 2517 skb_headlen(skb), 2518 PCI_DMA_TODEVICE); 2519 2520 last = tx_buf->nr_frags; 2521 j += 2; 2522 for (k = 0; k < last; k++, j++) { 2523 int ring_idx = j & bp->tx_ring_mask; 2524 skb_frag_t *frag = &skb_shinfo(skb)->frags[k]; 2525 2526 tx_buf = &txr->tx_buf_ring[ring_idx]; 2527 dma_unmap_page( 2528 &pdev->dev, 2529 dma_unmap_addr(tx_buf, mapping), 2530 skb_frag_size(frag), PCI_DMA_TODEVICE); 2531 } 2532 dev_kfree_skb(skb); 2533 } 2534 netdev_tx_reset_queue(netdev_get_tx_queue(bp->dev, i)); 2535 } 2536 } 2537 2538 static void bnxt_free_rx_skbs(struct bnxt *bp) 2539 { 2540 int i, max_idx, max_agg_idx; 2541 struct pci_dev *pdev = bp->pdev; 2542 2543 if (!bp->rx_ring) 2544 return; 2545 2546 max_idx = bp->rx_nr_pages * RX_DESC_CNT; 2547 max_agg_idx = bp->rx_agg_nr_pages * RX_DESC_CNT; 2548 for (i = 0; i < bp->rx_nr_rings; i++) { 2549 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 2550 struct bnxt_tpa_idx_map *map; 2551 int j; 2552 2553 if (rxr->rx_tpa) { 2554 for (j = 0; j < bp->max_tpa; j++) { 2555 struct bnxt_tpa_info *tpa_info = 2556 &rxr->rx_tpa[j]; 2557 u8 *data = tpa_info->data; 2558 2559 if (!data) 2560 continue; 2561 2562 dma_unmap_single_attrs(&pdev->dev, 2563 tpa_info->mapping, 2564 bp->rx_buf_use_size, 2565 bp->rx_dir, 2566 DMA_ATTR_WEAK_ORDERING); 2567 2568 tpa_info->data = NULL; 2569 2570 kfree(data); 2571 } 2572 } 2573 2574 for (j = 0; j < max_idx; j++) { 2575 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[j]; 2576 dma_addr_t mapping = rx_buf->mapping; 2577 void *data = rx_buf->data; 2578 2579 if (!data) 2580 continue; 2581 2582 rx_buf->data = NULL; 2583 2584 if (BNXT_RX_PAGE_MODE(bp)) { 2585 mapping -= bp->rx_dma_offset; 2586 dma_unmap_page_attrs(&pdev->dev, mapping, 2587 PAGE_SIZE, bp->rx_dir, 2588 DMA_ATTR_WEAK_ORDERING); 2589 page_pool_recycle_direct(rxr->page_pool, data); 2590 } else { 2591 dma_unmap_single_attrs(&pdev->dev, mapping, 2592 bp->rx_buf_use_size, 2593 bp->rx_dir, 2594 DMA_ATTR_WEAK_ORDERING); 2595 kfree(data); 2596 } 2597 } 2598 2599 for (j = 0; j < max_agg_idx; j++) { 2600 struct bnxt_sw_rx_agg_bd *rx_agg_buf = 2601 &rxr->rx_agg_ring[j]; 2602 struct page *page = rx_agg_buf->page; 2603 2604 if (!page) 2605 continue; 2606 2607 dma_unmap_page_attrs(&pdev->dev, rx_agg_buf->mapping, 2608 BNXT_RX_PAGE_SIZE, 2609 PCI_DMA_FROMDEVICE, 2610 DMA_ATTR_WEAK_ORDERING); 2611 2612 rx_agg_buf->page = NULL; 2613 __clear_bit(j, rxr->rx_agg_bmap); 2614 2615 __free_page(page); 2616 } 2617 if (rxr->rx_page) { 2618 __free_page(rxr->rx_page); 2619 rxr->rx_page = NULL; 2620 } 2621 map = rxr->rx_tpa_idx_map; 2622 if (map) 2623 memset(map->agg_idx_bmap, 0, sizeof(map->agg_idx_bmap)); 2624 } 2625 } 2626 2627 static void bnxt_free_skbs(struct bnxt *bp) 2628 { 2629 bnxt_free_tx_skbs(bp); 2630 bnxt_free_rx_skbs(bp); 2631 } 2632 2633 static void bnxt_free_ring(struct bnxt *bp, struct bnxt_ring_mem_info *rmem) 2634 { 2635 struct pci_dev *pdev = bp->pdev; 2636 int i; 2637 2638 for (i = 0; i < rmem->nr_pages; i++) { 2639 if (!rmem->pg_arr[i]) 2640 continue; 2641 2642 dma_free_coherent(&pdev->dev, rmem->page_size, 2643 rmem->pg_arr[i], rmem->dma_arr[i]); 2644 2645 rmem->pg_arr[i] = NULL; 2646 } 2647 if (rmem->pg_tbl) { 2648 size_t pg_tbl_size = rmem->nr_pages * 8; 2649 2650 if (rmem->flags & BNXT_RMEM_USE_FULL_PAGE_FLAG) 2651 pg_tbl_size = rmem->page_size; 2652 dma_free_coherent(&pdev->dev, pg_tbl_size, 2653 rmem->pg_tbl, rmem->pg_tbl_map); 2654 rmem->pg_tbl = NULL; 2655 } 2656 if (rmem->vmem_size && *rmem->vmem) { 2657 vfree(*rmem->vmem); 2658 *rmem->vmem = NULL; 2659 } 2660 } 2661 2662 static int bnxt_alloc_ring(struct bnxt *bp, struct bnxt_ring_mem_info *rmem) 2663 { 2664 struct pci_dev *pdev = bp->pdev; 2665 u64 valid_bit = 0; 2666 int i; 2667 2668 if (rmem->flags & (BNXT_RMEM_VALID_PTE_FLAG | BNXT_RMEM_RING_PTE_FLAG)) 2669 valid_bit = PTU_PTE_VALID; 2670 if ((rmem->nr_pages > 1 || rmem->depth > 0) && !rmem->pg_tbl) { 2671 size_t pg_tbl_size = rmem->nr_pages * 8; 2672 2673 if (rmem->flags & BNXT_RMEM_USE_FULL_PAGE_FLAG) 2674 pg_tbl_size = rmem->page_size; 2675 rmem->pg_tbl = dma_alloc_coherent(&pdev->dev, pg_tbl_size, 2676 &rmem->pg_tbl_map, 2677 GFP_KERNEL); 2678 if (!rmem->pg_tbl) 2679 return -ENOMEM; 2680 } 2681 2682 for (i = 0; i < rmem->nr_pages; i++) { 2683 u64 extra_bits = valid_bit; 2684 2685 rmem->pg_arr[i] = dma_alloc_coherent(&pdev->dev, 2686 rmem->page_size, 2687 &rmem->dma_arr[i], 2688 GFP_KERNEL); 2689 if (!rmem->pg_arr[i]) 2690 return -ENOMEM; 2691 2692 if (rmem->init_val) 2693 memset(rmem->pg_arr[i], rmem->init_val, 2694 rmem->page_size); 2695 if (rmem->nr_pages > 1 || rmem->depth > 0) { 2696 if (i == rmem->nr_pages - 2 && 2697 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG)) 2698 extra_bits |= PTU_PTE_NEXT_TO_LAST; 2699 else if (i == rmem->nr_pages - 1 && 2700 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG)) 2701 extra_bits |= PTU_PTE_LAST; 2702 rmem->pg_tbl[i] = 2703 cpu_to_le64(rmem->dma_arr[i] | extra_bits); 2704 } 2705 } 2706 2707 if (rmem->vmem_size) { 2708 *rmem->vmem = vzalloc(rmem->vmem_size); 2709 if (!(*rmem->vmem)) 2710 return -ENOMEM; 2711 } 2712 return 0; 2713 } 2714 2715 static void bnxt_free_tpa_info(struct bnxt *bp) 2716 { 2717 int i; 2718 2719 for (i = 0; i < bp->rx_nr_rings; i++) { 2720 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 2721 2722 kfree(rxr->rx_tpa_idx_map); 2723 rxr->rx_tpa_idx_map = NULL; 2724 if (rxr->rx_tpa) { 2725 kfree(rxr->rx_tpa[0].agg_arr); 2726 rxr->rx_tpa[0].agg_arr = NULL; 2727 } 2728 kfree(rxr->rx_tpa); 2729 rxr->rx_tpa = NULL; 2730 } 2731 } 2732 2733 static int bnxt_alloc_tpa_info(struct bnxt *bp) 2734 { 2735 int i, j, total_aggs = 0; 2736 2737 bp->max_tpa = MAX_TPA; 2738 if (bp->flags & BNXT_FLAG_CHIP_P5) { 2739 if (!bp->max_tpa_v2) 2740 return 0; 2741 bp->max_tpa = max_t(u16, bp->max_tpa_v2, MAX_TPA_P5); 2742 total_aggs = bp->max_tpa * MAX_SKB_FRAGS; 2743 } 2744 2745 for (i = 0; i < bp->rx_nr_rings; i++) { 2746 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 2747 struct rx_agg_cmp *agg; 2748 2749 rxr->rx_tpa = kcalloc(bp->max_tpa, sizeof(struct bnxt_tpa_info), 2750 GFP_KERNEL); 2751 if (!rxr->rx_tpa) 2752 return -ENOMEM; 2753 2754 if (!(bp->flags & BNXT_FLAG_CHIP_P5)) 2755 continue; 2756 agg = kcalloc(total_aggs, sizeof(*agg), GFP_KERNEL); 2757 rxr->rx_tpa[0].agg_arr = agg; 2758 if (!agg) 2759 return -ENOMEM; 2760 for (j = 1; j < bp->max_tpa; j++) 2761 rxr->rx_tpa[j].agg_arr = agg + j * MAX_SKB_FRAGS; 2762 rxr->rx_tpa_idx_map = kzalloc(sizeof(*rxr->rx_tpa_idx_map), 2763 GFP_KERNEL); 2764 if (!rxr->rx_tpa_idx_map) 2765 return -ENOMEM; 2766 } 2767 return 0; 2768 } 2769 2770 static void bnxt_free_rx_rings(struct bnxt *bp) 2771 { 2772 int i; 2773 2774 if (!bp->rx_ring) 2775 return; 2776 2777 bnxt_free_tpa_info(bp); 2778 for (i = 0; i < bp->rx_nr_rings; i++) { 2779 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 2780 struct bnxt_ring_struct *ring; 2781 2782 if (rxr->xdp_prog) 2783 bpf_prog_put(rxr->xdp_prog); 2784 2785 if (xdp_rxq_info_is_reg(&rxr->xdp_rxq)) 2786 xdp_rxq_info_unreg(&rxr->xdp_rxq); 2787 2788 page_pool_destroy(rxr->page_pool); 2789 rxr->page_pool = NULL; 2790 2791 kfree(rxr->rx_agg_bmap); 2792 rxr->rx_agg_bmap = NULL; 2793 2794 ring = &rxr->rx_ring_struct; 2795 bnxt_free_ring(bp, &ring->ring_mem); 2796 2797 ring = &rxr->rx_agg_ring_struct; 2798 bnxt_free_ring(bp, &ring->ring_mem); 2799 } 2800 } 2801 2802 static int bnxt_alloc_rx_page_pool(struct bnxt *bp, 2803 struct bnxt_rx_ring_info *rxr) 2804 { 2805 struct page_pool_params pp = { 0 }; 2806 2807 pp.pool_size = bp->rx_ring_size; 2808 pp.nid = dev_to_node(&bp->pdev->dev); 2809 pp.dev = &bp->pdev->dev; 2810 pp.dma_dir = DMA_BIDIRECTIONAL; 2811 2812 rxr->page_pool = page_pool_create(&pp); 2813 if (IS_ERR(rxr->page_pool)) { 2814 int err = PTR_ERR(rxr->page_pool); 2815 2816 rxr->page_pool = NULL; 2817 return err; 2818 } 2819 return 0; 2820 } 2821 2822 static int bnxt_alloc_rx_rings(struct bnxt *bp) 2823 { 2824 int i, rc = 0, agg_rings = 0; 2825 2826 if (!bp->rx_ring) 2827 return -ENOMEM; 2828 2829 if (bp->flags & BNXT_FLAG_AGG_RINGS) 2830 agg_rings = 1; 2831 2832 for (i = 0; i < bp->rx_nr_rings; i++) { 2833 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 2834 struct bnxt_ring_struct *ring; 2835 2836 ring = &rxr->rx_ring_struct; 2837 2838 rc = bnxt_alloc_rx_page_pool(bp, rxr); 2839 if (rc) 2840 return rc; 2841 2842 rc = xdp_rxq_info_reg(&rxr->xdp_rxq, bp->dev, i); 2843 if (rc < 0) 2844 return rc; 2845 2846 rc = xdp_rxq_info_reg_mem_model(&rxr->xdp_rxq, 2847 MEM_TYPE_PAGE_POOL, 2848 rxr->page_pool); 2849 if (rc) { 2850 xdp_rxq_info_unreg(&rxr->xdp_rxq); 2851 return rc; 2852 } 2853 2854 rc = bnxt_alloc_ring(bp, &ring->ring_mem); 2855 if (rc) 2856 return rc; 2857 2858 ring->grp_idx = i; 2859 if (agg_rings) { 2860 u16 mem_size; 2861 2862 ring = &rxr->rx_agg_ring_struct; 2863 rc = bnxt_alloc_ring(bp, &ring->ring_mem); 2864 if (rc) 2865 return rc; 2866 2867 ring->grp_idx = i; 2868 rxr->rx_agg_bmap_size = bp->rx_agg_ring_mask + 1; 2869 mem_size = rxr->rx_agg_bmap_size / 8; 2870 rxr->rx_agg_bmap = kzalloc(mem_size, GFP_KERNEL); 2871 if (!rxr->rx_agg_bmap) 2872 return -ENOMEM; 2873 } 2874 } 2875 if (bp->flags & BNXT_FLAG_TPA) 2876 rc = bnxt_alloc_tpa_info(bp); 2877 return rc; 2878 } 2879 2880 static void bnxt_free_tx_rings(struct bnxt *bp) 2881 { 2882 int i; 2883 struct pci_dev *pdev = bp->pdev; 2884 2885 if (!bp->tx_ring) 2886 return; 2887 2888 for (i = 0; i < bp->tx_nr_rings; i++) { 2889 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; 2890 struct bnxt_ring_struct *ring; 2891 2892 if (txr->tx_push) { 2893 dma_free_coherent(&pdev->dev, bp->tx_push_size, 2894 txr->tx_push, txr->tx_push_mapping); 2895 txr->tx_push = NULL; 2896 } 2897 2898 ring = &txr->tx_ring_struct; 2899 2900 bnxt_free_ring(bp, &ring->ring_mem); 2901 } 2902 } 2903 2904 static int bnxt_alloc_tx_rings(struct bnxt *bp) 2905 { 2906 int i, j, rc; 2907 struct pci_dev *pdev = bp->pdev; 2908 2909 bp->tx_push_size = 0; 2910 if (bp->tx_push_thresh) { 2911 int push_size; 2912 2913 push_size = L1_CACHE_ALIGN(sizeof(struct tx_push_bd) + 2914 bp->tx_push_thresh); 2915 2916 if (push_size > 256) { 2917 push_size = 0; 2918 bp->tx_push_thresh = 0; 2919 } 2920 2921 bp->tx_push_size = push_size; 2922 } 2923 2924 for (i = 0, j = 0; i < bp->tx_nr_rings; i++) { 2925 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; 2926 struct bnxt_ring_struct *ring; 2927 u8 qidx; 2928 2929 ring = &txr->tx_ring_struct; 2930 2931 rc = bnxt_alloc_ring(bp, &ring->ring_mem); 2932 if (rc) 2933 return rc; 2934 2935 ring->grp_idx = txr->bnapi->index; 2936 if (bp->tx_push_size) { 2937 dma_addr_t mapping; 2938 2939 /* One pre-allocated DMA buffer to backup 2940 * TX push operation 2941 */ 2942 txr->tx_push = dma_alloc_coherent(&pdev->dev, 2943 bp->tx_push_size, 2944 &txr->tx_push_mapping, 2945 GFP_KERNEL); 2946 2947 if (!txr->tx_push) 2948 return -ENOMEM; 2949 2950 mapping = txr->tx_push_mapping + 2951 sizeof(struct tx_push_bd); 2952 txr->data_mapping = cpu_to_le64(mapping); 2953 } 2954 qidx = bp->tc_to_qidx[j]; 2955 ring->queue_id = bp->q_info[qidx].queue_id; 2956 if (i < bp->tx_nr_rings_xdp) 2957 continue; 2958 if (i % bp->tx_nr_rings_per_tc == (bp->tx_nr_rings_per_tc - 1)) 2959 j++; 2960 } 2961 return 0; 2962 } 2963 2964 static void bnxt_free_cp_rings(struct bnxt *bp) 2965 { 2966 int i; 2967 2968 if (!bp->bnapi) 2969 return; 2970 2971 for (i = 0; i < bp->cp_nr_rings; i++) { 2972 struct bnxt_napi *bnapi = bp->bnapi[i]; 2973 struct bnxt_cp_ring_info *cpr; 2974 struct bnxt_ring_struct *ring; 2975 int j; 2976 2977 if (!bnapi) 2978 continue; 2979 2980 cpr = &bnapi->cp_ring; 2981 ring = &cpr->cp_ring_struct; 2982 2983 bnxt_free_ring(bp, &ring->ring_mem); 2984 2985 for (j = 0; j < 2; j++) { 2986 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j]; 2987 2988 if (cpr2) { 2989 ring = &cpr2->cp_ring_struct; 2990 bnxt_free_ring(bp, &ring->ring_mem); 2991 kfree(cpr2); 2992 cpr->cp_ring_arr[j] = NULL; 2993 } 2994 } 2995 } 2996 } 2997 2998 static struct bnxt_cp_ring_info *bnxt_alloc_cp_sub_ring(struct bnxt *bp) 2999 { 3000 struct bnxt_ring_mem_info *rmem; 3001 struct bnxt_ring_struct *ring; 3002 struct bnxt_cp_ring_info *cpr; 3003 int rc; 3004 3005 cpr = kzalloc(sizeof(*cpr), GFP_KERNEL); 3006 if (!cpr) 3007 return NULL; 3008 3009 ring = &cpr->cp_ring_struct; 3010 rmem = &ring->ring_mem; 3011 rmem->nr_pages = bp->cp_nr_pages; 3012 rmem->page_size = HW_CMPD_RING_SIZE; 3013 rmem->pg_arr = (void **)cpr->cp_desc_ring; 3014 rmem->dma_arr = cpr->cp_desc_mapping; 3015 rmem->flags = BNXT_RMEM_RING_PTE_FLAG; 3016 rc = bnxt_alloc_ring(bp, rmem); 3017 if (rc) { 3018 bnxt_free_ring(bp, rmem); 3019 kfree(cpr); 3020 cpr = NULL; 3021 } 3022 return cpr; 3023 } 3024 3025 static int bnxt_alloc_cp_rings(struct bnxt *bp) 3026 { 3027 bool sh = !!(bp->flags & BNXT_FLAG_SHARED_RINGS); 3028 int i, rc, ulp_base_vec, ulp_msix; 3029 3030 ulp_msix = bnxt_get_ulp_msix_num(bp); 3031 ulp_base_vec = bnxt_get_ulp_msix_base(bp); 3032 for (i = 0; i < bp->cp_nr_rings; i++) { 3033 struct bnxt_napi *bnapi = bp->bnapi[i]; 3034 struct bnxt_cp_ring_info *cpr; 3035 struct bnxt_ring_struct *ring; 3036 3037 if (!bnapi) 3038 continue; 3039 3040 cpr = &bnapi->cp_ring; 3041 cpr->bnapi = bnapi; 3042 ring = &cpr->cp_ring_struct; 3043 3044 rc = bnxt_alloc_ring(bp, &ring->ring_mem); 3045 if (rc) 3046 return rc; 3047 3048 if (ulp_msix && i >= ulp_base_vec) 3049 ring->map_idx = i + ulp_msix; 3050 else 3051 ring->map_idx = i; 3052 3053 if (!(bp->flags & BNXT_FLAG_CHIP_P5)) 3054 continue; 3055 3056 if (i < bp->rx_nr_rings) { 3057 struct bnxt_cp_ring_info *cpr2 = 3058 bnxt_alloc_cp_sub_ring(bp); 3059 3060 cpr->cp_ring_arr[BNXT_RX_HDL] = cpr2; 3061 if (!cpr2) 3062 return -ENOMEM; 3063 cpr2->bnapi = bnapi; 3064 } 3065 if ((sh && i < bp->tx_nr_rings) || 3066 (!sh && i >= bp->rx_nr_rings)) { 3067 struct bnxt_cp_ring_info *cpr2 = 3068 bnxt_alloc_cp_sub_ring(bp); 3069 3070 cpr->cp_ring_arr[BNXT_TX_HDL] = cpr2; 3071 if (!cpr2) 3072 return -ENOMEM; 3073 cpr2->bnapi = bnapi; 3074 } 3075 } 3076 return 0; 3077 } 3078 3079 static void bnxt_init_ring_struct(struct bnxt *bp) 3080 { 3081 int i; 3082 3083 for (i = 0; i < bp->cp_nr_rings; i++) { 3084 struct bnxt_napi *bnapi = bp->bnapi[i]; 3085 struct bnxt_ring_mem_info *rmem; 3086 struct bnxt_cp_ring_info *cpr; 3087 struct bnxt_rx_ring_info *rxr; 3088 struct bnxt_tx_ring_info *txr; 3089 struct bnxt_ring_struct *ring; 3090 3091 if (!bnapi) 3092 continue; 3093 3094 cpr = &bnapi->cp_ring; 3095 ring = &cpr->cp_ring_struct; 3096 rmem = &ring->ring_mem; 3097 rmem->nr_pages = bp->cp_nr_pages; 3098 rmem->page_size = HW_CMPD_RING_SIZE; 3099 rmem->pg_arr = (void **)cpr->cp_desc_ring; 3100 rmem->dma_arr = cpr->cp_desc_mapping; 3101 rmem->vmem_size = 0; 3102 3103 rxr = bnapi->rx_ring; 3104 if (!rxr) 3105 goto skip_rx; 3106 3107 ring = &rxr->rx_ring_struct; 3108 rmem = &ring->ring_mem; 3109 rmem->nr_pages = bp->rx_nr_pages; 3110 rmem->page_size = HW_RXBD_RING_SIZE; 3111 rmem->pg_arr = (void **)rxr->rx_desc_ring; 3112 rmem->dma_arr = rxr->rx_desc_mapping; 3113 rmem->vmem_size = SW_RXBD_RING_SIZE * bp->rx_nr_pages; 3114 rmem->vmem = (void **)&rxr->rx_buf_ring; 3115 3116 ring = &rxr->rx_agg_ring_struct; 3117 rmem = &ring->ring_mem; 3118 rmem->nr_pages = bp->rx_agg_nr_pages; 3119 rmem->page_size = HW_RXBD_RING_SIZE; 3120 rmem->pg_arr = (void **)rxr->rx_agg_desc_ring; 3121 rmem->dma_arr = rxr->rx_agg_desc_mapping; 3122 rmem->vmem_size = SW_RXBD_AGG_RING_SIZE * bp->rx_agg_nr_pages; 3123 rmem->vmem = (void **)&rxr->rx_agg_ring; 3124 3125 skip_rx: 3126 txr = bnapi->tx_ring; 3127 if (!txr) 3128 continue; 3129 3130 ring = &txr->tx_ring_struct; 3131 rmem = &ring->ring_mem; 3132 rmem->nr_pages = bp->tx_nr_pages; 3133 rmem->page_size = HW_RXBD_RING_SIZE; 3134 rmem->pg_arr = (void **)txr->tx_desc_ring; 3135 rmem->dma_arr = txr->tx_desc_mapping; 3136 rmem->vmem_size = SW_TXBD_RING_SIZE * bp->tx_nr_pages; 3137 rmem->vmem = (void **)&txr->tx_buf_ring; 3138 } 3139 } 3140 3141 static void bnxt_init_rxbd_pages(struct bnxt_ring_struct *ring, u32 type) 3142 { 3143 int i; 3144 u32 prod; 3145 struct rx_bd **rx_buf_ring; 3146 3147 rx_buf_ring = (struct rx_bd **)ring->ring_mem.pg_arr; 3148 for (i = 0, prod = 0; i < ring->ring_mem.nr_pages; i++) { 3149 int j; 3150 struct rx_bd *rxbd; 3151 3152 rxbd = rx_buf_ring[i]; 3153 if (!rxbd) 3154 continue; 3155 3156 for (j = 0; j < RX_DESC_CNT; j++, rxbd++, prod++) { 3157 rxbd->rx_bd_len_flags_type = cpu_to_le32(type); 3158 rxbd->rx_bd_opaque = prod; 3159 } 3160 } 3161 } 3162 3163 static int bnxt_init_one_rx_ring(struct bnxt *bp, int ring_nr) 3164 { 3165 struct net_device *dev = bp->dev; 3166 struct bnxt_rx_ring_info *rxr; 3167 struct bnxt_ring_struct *ring; 3168 u32 prod, type; 3169 int i; 3170 3171 type = (bp->rx_buf_use_size << RX_BD_LEN_SHIFT) | 3172 RX_BD_TYPE_RX_PACKET_BD | RX_BD_FLAGS_EOP; 3173 3174 if (NET_IP_ALIGN == 2) 3175 type |= RX_BD_FLAGS_SOP; 3176 3177 rxr = &bp->rx_ring[ring_nr]; 3178 ring = &rxr->rx_ring_struct; 3179 bnxt_init_rxbd_pages(ring, type); 3180 3181 if (BNXT_RX_PAGE_MODE(bp) && bp->xdp_prog) { 3182 bpf_prog_add(bp->xdp_prog, 1); 3183 rxr->xdp_prog = bp->xdp_prog; 3184 } 3185 prod = rxr->rx_prod; 3186 for (i = 0; i < bp->rx_ring_size; i++) { 3187 if (bnxt_alloc_rx_data(bp, rxr, prod, GFP_KERNEL) != 0) { 3188 netdev_warn(dev, "init'ed rx ring %d with %d/%d skbs only\n", 3189 ring_nr, i, bp->rx_ring_size); 3190 break; 3191 } 3192 prod = NEXT_RX(prod); 3193 } 3194 rxr->rx_prod = prod; 3195 ring->fw_ring_id = INVALID_HW_RING_ID; 3196 3197 ring = &rxr->rx_agg_ring_struct; 3198 ring->fw_ring_id = INVALID_HW_RING_ID; 3199 3200 if (!(bp->flags & BNXT_FLAG_AGG_RINGS)) 3201 return 0; 3202 3203 type = ((u32)BNXT_RX_PAGE_SIZE << RX_BD_LEN_SHIFT) | 3204 RX_BD_TYPE_RX_AGG_BD | RX_BD_FLAGS_SOP; 3205 3206 bnxt_init_rxbd_pages(ring, type); 3207 3208 prod = rxr->rx_agg_prod; 3209 for (i = 0; i < bp->rx_agg_ring_size; i++) { 3210 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_KERNEL) != 0) { 3211 netdev_warn(dev, "init'ed rx ring %d with %d/%d pages only\n", 3212 ring_nr, i, bp->rx_ring_size); 3213 break; 3214 } 3215 prod = NEXT_RX_AGG(prod); 3216 } 3217 rxr->rx_agg_prod = prod; 3218 3219 if (bp->flags & BNXT_FLAG_TPA) { 3220 if (rxr->rx_tpa) { 3221 u8 *data; 3222 dma_addr_t mapping; 3223 3224 for (i = 0; i < bp->max_tpa; i++) { 3225 data = __bnxt_alloc_rx_data(bp, &mapping, 3226 GFP_KERNEL); 3227 if (!data) 3228 return -ENOMEM; 3229 3230 rxr->rx_tpa[i].data = data; 3231 rxr->rx_tpa[i].data_ptr = data + bp->rx_offset; 3232 rxr->rx_tpa[i].mapping = mapping; 3233 } 3234 } else { 3235 netdev_err(bp->dev, "No resource allocated for LRO/GRO\n"); 3236 return -ENOMEM; 3237 } 3238 } 3239 3240 return 0; 3241 } 3242 3243 static void bnxt_init_cp_rings(struct bnxt *bp) 3244 { 3245 int i, j; 3246 3247 for (i = 0; i < bp->cp_nr_rings; i++) { 3248 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring; 3249 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct; 3250 3251 ring->fw_ring_id = INVALID_HW_RING_ID; 3252 cpr->rx_ring_coal.coal_ticks = bp->rx_coal.coal_ticks; 3253 cpr->rx_ring_coal.coal_bufs = bp->rx_coal.coal_bufs; 3254 for (j = 0; j < 2; j++) { 3255 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j]; 3256 3257 if (!cpr2) 3258 continue; 3259 3260 ring = &cpr2->cp_ring_struct; 3261 ring->fw_ring_id = INVALID_HW_RING_ID; 3262 cpr2->rx_ring_coal.coal_ticks = bp->rx_coal.coal_ticks; 3263 cpr2->rx_ring_coal.coal_bufs = bp->rx_coal.coal_bufs; 3264 } 3265 } 3266 } 3267 3268 static int bnxt_init_rx_rings(struct bnxt *bp) 3269 { 3270 int i, rc = 0; 3271 3272 if (BNXT_RX_PAGE_MODE(bp)) { 3273 bp->rx_offset = NET_IP_ALIGN + XDP_PACKET_HEADROOM; 3274 bp->rx_dma_offset = XDP_PACKET_HEADROOM; 3275 } else { 3276 bp->rx_offset = BNXT_RX_OFFSET; 3277 bp->rx_dma_offset = BNXT_RX_DMA_OFFSET; 3278 } 3279 3280 for (i = 0; i < bp->rx_nr_rings; i++) { 3281 rc = bnxt_init_one_rx_ring(bp, i); 3282 if (rc) 3283 break; 3284 } 3285 3286 return rc; 3287 } 3288 3289 static int bnxt_init_tx_rings(struct bnxt *bp) 3290 { 3291 u16 i; 3292 3293 bp->tx_wake_thresh = max_t(int, bp->tx_ring_size / 2, 3294 MAX_SKB_FRAGS + 1); 3295 3296 for (i = 0; i < bp->tx_nr_rings; i++) { 3297 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; 3298 struct bnxt_ring_struct *ring = &txr->tx_ring_struct; 3299 3300 ring->fw_ring_id = INVALID_HW_RING_ID; 3301 } 3302 3303 return 0; 3304 } 3305 3306 static void bnxt_free_ring_grps(struct bnxt *bp) 3307 { 3308 kfree(bp->grp_info); 3309 bp->grp_info = NULL; 3310 } 3311 3312 static int bnxt_init_ring_grps(struct bnxt *bp, bool irq_re_init) 3313 { 3314 int i; 3315 3316 if (irq_re_init) { 3317 bp->grp_info = kcalloc(bp->cp_nr_rings, 3318 sizeof(struct bnxt_ring_grp_info), 3319 GFP_KERNEL); 3320 if (!bp->grp_info) 3321 return -ENOMEM; 3322 } 3323 for (i = 0; i < bp->cp_nr_rings; i++) { 3324 if (irq_re_init) 3325 bp->grp_info[i].fw_stats_ctx = INVALID_HW_RING_ID; 3326 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID; 3327 bp->grp_info[i].rx_fw_ring_id = INVALID_HW_RING_ID; 3328 bp->grp_info[i].agg_fw_ring_id = INVALID_HW_RING_ID; 3329 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID; 3330 } 3331 return 0; 3332 } 3333 3334 static void bnxt_free_vnics(struct bnxt *bp) 3335 { 3336 kfree(bp->vnic_info); 3337 bp->vnic_info = NULL; 3338 bp->nr_vnics = 0; 3339 } 3340 3341 static int bnxt_alloc_vnics(struct bnxt *bp) 3342 { 3343 int num_vnics = 1; 3344 3345 #ifdef CONFIG_RFS_ACCEL 3346 if ((bp->flags & (BNXT_FLAG_RFS | BNXT_FLAG_CHIP_P5)) == BNXT_FLAG_RFS) 3347 num_vnics += bp->rx_nr_rings; 3348 #endif 3349 3350 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 3351 num_vnics++; 3352 3353 bp->vnic_info = kcalloc(num_vnics, sizeof(struct bnxt_vnic_info), 3354 GFP_KERNEL); 3355 if (!bp->vnic_info) 3356 return -ENOMEM; 3357 3358 bp->nr_vnics = num_vnics; 3359 return 0; 3360 } 3361 3362 static void bnxt_init_vnics(struct bnxt *bp) 3363 { 3364 int i; 3365 3366 for (i = 0; i < bp->nr_vnics; i++) { 3367 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 3368 int j; 3369 3370 vnic->fw_vnic_id = INVALID_HW_RING_ID; 3371 for (j = 0; j < BNXT_MAX_CTX_PER_VNIC; j++) 3372 vnic->fw_rss_cos_lb_ctx[j] = INVALID_HW_RING_ID; 3373 3374 vnic->fw_l2_ctx_id = INVALID_HW_RING_ID; 3375 3376 if (bp->vnic_info[i].rss_hash_key) { 3377 if (i == 0) 3378 prandom_bytes(vnic->rss_hash_key, 3379 HW_HASH_KEY_SIZE); 3380 else 3381 memcpy(vnic->rss_hash_key, 3382 bp->vnic_info[0].rss_hash_key, 3383 HW_HASH_KEY_SIZE); 3384 } 3385 } 3386 } 3387 3388 static int bnxt_calc_nr_ring_pages(u32 ring_size, int desc_per_pg) 3389 { 3390 int pages; 3391 3392 pages = ring_size / desc_per_pg; 3393 3394 if (!pages) 3395 return 1; 3396 3397 pages++; 3398 3399 while (pages & (pages - 1)) 3400 pages++; 3401 3402 return pages; 3403 } 3404 3405 void bnxt_set_tpa_flags(struct bnxt *bp) 3406 { 3407 bp->flags &= ~BNXT_FLAG_TPA; 3408 if (bp->flags & BNXT_FLAG_NO_AGG_RINGS) 3409 return; 3410 if (bp->dev->features & NETIF_F_LRO) 3411 bp->flags |= BNXT_FLAG_LRO; 3412 else if (bp->dev->features & NETIF_F_GRO_HW) 3413 bp->flags |= BNXT_FLAG_GRO; 3414 } 3415 3416 /* bp->rx_ring_size, bp->tx_ring_size, dev->mtu, BNXT_FLAG_{G|L}RO flags must 3417 * be set on entry. 3418 */ 3419 void bnxt_set_ring_params(struct bnxt *bp) 3420 { 3421 u32 ring_size, rx_size, rx_space; 3422 u32 agg_factor = 0, agg_ring_size = 0; 3423 3424 /* 8 for CRC and VLAN */ 3425 rx_size = SKB_DATA_ALIGN(bp->dev->mtu + ETH_HLEN + NET_IP_ALIGN + 8); 3426 3427 rx_space = rx_size + NET_SKB_PAD + 3428 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 3429 3430 bp->rx_copy_thresh = BNXT_RX_COPY_THRESH; 3431 ring_size = bp->rx_ring_size; 3432 bp->rx_agg_ring_size = 0; 3433 bp->rx_agg_nr_pages = 0; 3434 3435 if (bp->flags & BNXT_FLAG_TPA) 3436 agg_factor = min_t(u32, 4, 65536 / BNXT_RX_PAGE_SIZE); 3437 3438 bp->flags &= ~BNXT_FLAG_JUMBO; 3439 if (rx_space > PAGE_SIZE && !(bp->flags & BNXT_FLAG_NO_AGG_RINGS)) { 3440 u32 jumbo_factor; 3441 3442 bp->flags |= BNXT_FLAG_JUMBO; 3443 jumbo_factor = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT; 3444 if (jumbo_factor > agg_factor) 3445 agg_factor = jumbo_factor; 3446 } 3447 agg_ring_size = ring_size * agg_factor; 3448 3449 if (agg_ring_size) { 3450 bp->rx_agg_nr_pages = bnxt_calc_nr_ring_pages(agg_ring_size, 3451 RX_DESC_CNT); 3452 if (bp->rx_agg_nr_pages > MAX_RX_AGG_PAGES) { 3453 u32 tmp = agg_ring_size; 3454 3455 bp->rx_agg_nr_pages = MAX_RX_AGG_PAGES; 3456 agg_ring_size = MAX_RX_AGG_PAGES * RX_DESC_CNT - 1; 3457 netdev_warn(bp->dev, "rx agg ring size %d reduced to %d.\n", 3458 tmp, agg_ring_size); 3459 } 3460 bp->rx_agg_ring_size = agg_ring_size; 3461 bp->rx_agg_ring_mask = (bp->rx_agg_nr_pages * RX_DESC_CNT) - 1; 3462 rx_size = SKB_DATA_ALIGN(BNXT_RX_COPY_THRESH + NET_IP_ALIGN); 3463 rx_space = rx_size + NET_SKB_PAD + 3464 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 3465 } 3466 3467 bp->rx_buf_use_size = rx_size; 3468 bp->rx_buf_size = rx_space; 3469 3470 bp->rx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, RX_DESC_CNT); 3471 bp->rx_ring_mask = (bp->rx_nr_pages * RX_DESC_CNT) - 1; 3472 3473 ring_size = bp->tx_ring_size; 3474 bp->tx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, TX_DESC_CNT); 3475 bp->tx_ring_mask = (bp->tx_nr_pages * TX_DESC_CNT) - 1; 3476 3477 ring_size = bp->rx_ring_size * (2 + agg_factor) + bp->tx_ring_size; 3478 bp->cp_ring_size = ring_size; 3479 3480 bp->cp_nr_pages = bnxt_calc_nr_ring_pages(ring_size, CP_DESC_CNT); 3481 if (bp->cp_nr_pages > MAX_CP_PAGES) { 3482 bp->cp_nr_pages = MAX_CP_PAGES; 3483 bp->cp_ring_size = MAX_CP_PAGES * CP_DESC_CNT - 1; 3484 netdev_warn(bp->dev, "completion ring size %d reduced to %d.\n", 3485 ring_size, bp->cp_ring_size); 3486 } 3487 bp->cp_bit = bp->cp_nr_pages * CP_DESC_CNT; 3488 bp->cp_ring_mask = bp->cp_bit - 1; 3489 } 3490 3491 /* Changing allocation mode of RX rings. 3492 * TODO: Update when extending xdp_rxq_info to support allocation modes. 3493 */ 3494 int bnxt_set_rx_skb_mode(struct bnxt *bp, bool page_mode) 3495 { 3496 if (page_mode) { 3497 if (bp->dev->mtu > BNXT_MAX_PAGE_MODE_MTU) 3498 return -EOPNOTSUPP; 3499 bp->dev->max_mtu = 3500 min_t(u16, bp->max_mtu, BNXT_MAX_PAGE_MODE_MTU); 3501 bp->flags &= ~BNXT_FLAG_AGG_RINGS; 3502 bp->flags |= BNXT_FLAG_NO_AGG_RINGS | BNXT_FLAG_RX_PAGE_MODE; 3503 bp->rx_dir = DMA_BIDIRECTIONAL; 3504 bp->rx_skb_func = bnxt_rx_page_skb; 3505 /* Disable LRO or GRO_HW */ 3506 netdev_update_features(bp->dev); 3507 } else { 3508 bp->dev->max_mtu = bp->max_mtu; 3509 bp->flags &= ~BNXT_FLAG_RX_PAGE_MODE; 3510 bp->rx_dir = DMA_FROM_DEVICE; 3511 bp->rx_skb_func = bnxt_rx_skb; 3512 } 3513 return 0; 3514 } 3515 3516 static void bnxt_free_vnic_attributes(struct bnxt *bp) 3517 { 3518 int i; 3519 struct bnxt_vnic_info *vnic; 3520 struct pci_dev *pdev = bp->pdev; 3521 3522 if (!bp->vnic_info) 3523 return; 3524 3525 for (i = 0; i < bp->nr_vnics; i++) { 3526 vnic = &bp->vnic_info[i]; 3527 3528 kfree(vnic->fw_grp_ids); 3529 vnic->fw_grp_ids = NULL; 3530 3531 kfree(vnic->uc_list); 3532 vnic->uc_list = NULL; 3533 3534 if (vnic->mc_list) { 3535 dma_free_coherent(&pdev->dev, vnic->mc_list_size, 3536 vnic->mc_list, vnic->mc_list_mapping); 3537 vnic->mc_list = NULL; 3538 } 3539 3540 if (vnic->rss_table) { 3541 dma_free_coherent(&pdev->dev, PAGE_SIZE, 3542 vnic->rss_table, 3543 vnic->rss_table_dma_addr); 3544 vnic->rss_table = NULL; 3545 } 3546 3547 vnic->rss_hash_key = NULL; 3548 vnic->flags = 0; 3549 } 3550 } 3551 3552 static int bnxt_alloc_vnic_attributes(struct bnxt *bp) 3553 { 3554 int i, rc = 0, size; 3555 struct bnxt_vnic_info *vnic; 3556 struct pci_dev *pdev = bp->pdev; 3557 int max_rings; 3558 3559 for (i = 0; i < bp->nr_vnics; i++) { 3560 vnic = &bp->vnic_info[i]; 3561 3562 if (vnic->flags & BNXT_VNIC_UCAST_FLAG) { 3563 int mem_size = (BNXT_MAX_UC_ADDRS - 1) * ETH_ALEN; 3564 3565 if (mem_size > 0) { 3566 vnic->uc_list = kmalloc(mem_size, GFP_KERNEL); 3567 if (!vnic->uc_list) { 3568 rc = -ENOMEM; 3569 goto out; 3570 } 3571 } 3572 } 3573 3574 if (vnic->flags & BNXT_VNIC_MCAST_FLAG) { 3575 vnic->mc_list_size = BNXT_MAX_MC_ADDRS * ETH_ALEN; 3576 vnic->mc_list = 3577 dma_alloc_coherent(&pdev->dev, 3578 vnic->mc_list_size, 3579 &vnic->mc_list_mapping, 3580 GFP_KERNEL); 3581 if (!vnic->mc_list) { 3582 rc = -ENOMEM; 3583 goto out; 3584 } 3585 } 3586 3587 if (bp->flags & BNXT_FLAG_CHIP_P5) 3588 goto vnic_skip_grps; 3589 3590 if (vnic->flags & BNXT_VNIC_RSS_FLAG) 3591 max_rings = bp->rx_nr_rings; 3592 else 3593 max_rings = 1; 3594 3595 vnic->fw_grp_ids = kcalloc(max_rings, sizeof(u16), GFP_KERNEL); 3596 if (!vnic->fw_grp_ids) { 3597 rc = -ENOMEM; 3598 goto out; 3599 } 3600 vnic_skip_grps: 3601 if ((bp->flags & BNXT_FLAG_NEW_RSS_CAP) && 3602 !(vnic->flags & BNXT_VNIC_RSS_FLAG)) 3603 continue; 3604 3605 /* Allocate rss table and hash key */ 3606 vnic->rss_table = dma_alloc_coherent(&pdev->dev, PAGE_SIZE, 3607 &vnic->rss_table_dma_addr, 3608 GFP_KERNEL); 3609 if (!vnic->rss_table) { 3610 rc = -ENOMEM; 3611 goto out; 3612 } 3613 3614 size = L1_CACHE_ALIGN(HW_HASH_INDEX_SIZE * sizeof(u16)); 3615 3616 vnic->rss_hash_key = ((void *)vnic->rss_table) + size; 3617 vnic->rss_hash_key_dma_addr = vnic->rss_table_dma_addr + size; 3618 } 3619 return 0; 3620 3621 out: 3622 return rc; 3623 } 3624 3625 static void bnxt_free_hwrm_resources(struct bnxt *bp) 3626 { 3627 struct pci_dev *pdev = bp->pdev; 3628 3629 if (bp->hwrm_cmd_resp_addr) { 3630 dma_free_coherent(&pdev->dev, PAGE_SIZE, bp->hwrm_cmd_resp_addr, 3631 bp->hwrm_cmd_resp_dma_addr); 3632 bp->hwrm_cmd_resp_addr = NULL; 3633 } 3634 3635 if (bp->hwrm_cmd_kong_resp_addr) { 3636 dma_free_coherent(&pdev->dev, PAGE_SIZE, 3637 bp->hwrm_cmd_kong_resp_addr, 3638 bp->hwrm_cmd_kong_resp_dma_addr); 3639 bp->hwrm_cmd_kong_resp_addr = NULL; 3640 } 3641 } 3642 3643 static int bnxt_alloc_kong_hwrm_resources(struct bnxt *bp) 3644 { 3645 struct pci_dev *pdev = bp->pdev; 3646 3647 if (bp->hwrm_cmd_kong_resp_addr) 3648 return 0; 3649 3650 bp->hwrm_cmd_kong_resp_addr = 3651 dma_alloc_coherent(&pdev->dev, PAGE_SIZE, 3652 &bp->hwrm_cmd_kong_resp_dma_addr, 3653 GFP_KERNEL); 3654 if (!bp->hwrm_cmd_kong_resp_addr) 3655 return -ENOMEM; 3656 3657 return 0; 3658 } 3659 3660 static int bnxt_alloc_hwrm_resources(struct bnxt *bp) 3661 { 3662 struct pci_dev *pdev = bp->pdev; 3663 3664 bp->hwrm_cmd_resp_addr = dma_alloc_coherent(&pdev->dev, PAGE_SIZE, 3665 &bp->hwrm_cmd_resp_dma_addr, 3666 GFP_KERNEL); 3667 if (!bp->hwrm_cmd_resp_addr) 3668 return -ENOMEM; 3669 3670 return 0; 3671 } 3672 3673 static void bnxt_free_hwrm_short_cmd_req(struct bnxt *bp) 3674 { 3675 if (bp->hwrm_short_cmd_req_addr) { 3676 struct pci_dev *pdev = bp->pdev; 3677 3678 dma_free_coherent(&pdev->dev, bp->hwrm_max_ext_req_len, 3679 bp->hwrm_short_cmd_req_addr, 3680 bp->hwrm_short_cmd_req_dma_addr); 3681 bp->hwrm_short_cmd_req_addr = NULL; 3682 } 3683 } 3684 3685 static int bnxt_alloc_hwrm_short_cmd_req(struct bnxt *bp) 3686 { 3687 struct pci_dev *pdev = bp->pdev; 3688 3689 if (bp->hwrm_short_cmd_req_addr) 3690 return 0; 3691 3692 bp->hwrm_short_cmd_req_addr = 3693 dma_alloc_coherent(&pdev->dev, bp->hwrm_max_ext_req_len, 3694 &bp->hwrm_short_cmd_req_dma_addr, 3695 GFP_KERNEL); 3696 if (!bp->hwrm_short_cmd_req_addr) 3697 return -ENOMEM; 3698 3699 return 0; 3700 } 3701 3702 static void bnxt_free_port_stats(struct bnxt *bp) 3703 { 3704 struct pci_dev *pdev = bp->pdev; 3705 3706 bp->flags &= ~BNXT_FLAG_PORT_STATS; 3707 bp->flags &= ~BNXT_FLAG_PORT_STATS_EXT; 3708 3709 if (bp->hw_rx_port_stats) { 3710 dma_free_coherent(&pdev->dev, bp->hw_port_stats_size, 3711 bp->hw_rx_port_stats, 3712 bp->hw_rx_port_stats_map); 3713 bp->hw_rx_port_stats = NULL; 3714 } 3715 3716 if (bp->hw_tx_port_stats_ext) { 3717 dma_free_coherent(&pdev->dev, sizeof(struct tx_port_stats_ext), 3718 bp->hw_tx_port_stats_ext, 3719 bp->hw_tx_port_stats_ext_map); 3720 bp->hw_tx_port_stats_ext = NULL; 3721 } 3722 3723 if (bp->hw_rx_port_stats_ext) { 3724 dma_free_coherent(&pdev->dev, sizeof(struct rx_port_stats_ext), 3725 bp->hw_rx_port_stats_ext, 3726 bp->hw_rx_port_stats_ext_map); 3727 bp->hw_rx_port_stats_ext = NULL; 3728 } 3729 3730 if (bp->hw_pcie_stats) { 3731 dma_free_coherent(&pdev->dev, sizeof(struct pcie_ctx_hw_stats), 3732 bp->hw_pcie_stats, bp->hw_pcie_stats_map); 3733 bp->hw_pcie_stats = NULL; 3734 } 3735 } 3736 3737 static void bnxt_free_ring_stats(struct bnxt *bp) 3738 { 3739 struct pci_dev *pdev = bp->pdev; 3740 int size, i; 3741 3742 if (!bp->bnapi) 3743 return; 3744 3745 size = bp->hw_ring_stats_size; 3746 3747 for (i = 0; i < bp->cp_nr_rings; i++) { 3748 struct bnxt_napi *bnapi = bp->bnapi[i]; 3749 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 3750 3751 if (cpr->hw_stats) { 3752 dma_free_coherent(&pdev->dev, size, cpr->hw_stats, 3753 cpr->hw_stats_map); 3754 cpr->hw_stats = NULL; 3755 } 3756 } 3757 } 3758 3759 static int bnxt_alloc_stats(struct bnxt *bp) 3760 { 3761 u32 size, i; 3762 struct pci_dev *pdev = bp->pdev; 3763 3764 size = bp->hw_ring_stats_size; 3765 3766 for (i = 0; i < bp->cp_nr_rings; i++) { 3767 struct bnxt_napi *bnapi = bp->bnapi[i]; 3768 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 3769 3770 cpr->hw_stats = dma_alloc_coherent(&pdev->dev, size, 3771 &cpr->hw_stats_map, 3772 GFP_KERNEL); 3773 if (!cpr->hw_stats) 3774 return -ENOMEM; 3775 3776 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID; 3777 } 3778 3779 if (BNXT_VF(bp) || bp->chip_num == CHIP_NUM_58700) 3780 return 0; 3781 3782 if (bp->hw_rx_port_stats) 3783 goto alloc_ext_stats; 3784 3785 bp->hw_port_stats_size = sizeof(struct rx_port_stats) + 3786 sizeof(struct tx_port_stats) + 1024; 3787 3788 bp->hw_rx_port_stats = 3789 dma_alloc_coherent(&pdev->dev, bp->hw_port_stats_size, 3790 &bp->hw_rx_port_stats_map, 3791 GFP_KERNEL); 3792 if (!bp->hw_rx_port_stats) 3793 return -ENOMEM; 3794 3795 bp->hw_tx_port_stats = (void *)(bp->hw_rx_port_stats + 1) + 512; 3796 bp->hw_tx_port_stats_map = bp->hw_rx_port_stats_map + 3797 sizeof(struct rx_port_stats) + 512; 3798 bp->flags |= BNXT_FLAG_PORT_STATS; 3799 3800 alloc_ext_stats: 3801 /* Display extended statistics only if FW supports it */ 3802 if (bp->hwrm_spec_code < 0x10804 || bp->hwrm_spec_code == 0x10900) 3803 if (!(bp->fw_cap & BNXT_FW_CAP_EXT_STATS_SUPPORTED)) 3804 return 0; 3805 3806 if (bp->hw_rx_port_stats_ext) 3807 goto alloc_tx_ext_stats; 3808 3809 bp->hw_rx_port_stats_ext = 3810 dma_alloc_coherent(&pdev->dev, sizeof(struct rx_port_stats_ext), 3811 &bp->hw_rx_port_stats_ext_map, GFP_KERNEL); 3812 if (!bp->hw_rx_port_stats_ext) 3813 return 0; 3814 3815 alloc_tx_ext_stats: 3816 if (bp->hw_tx_port_stats_ext) 3817 goto alloc_pcie_stats; 3818 3819 if (bp->hwrm_spec_code >= 0x10902 || 3820 (bp->fw_cap & BNXT_FW_CAP_EXT_STATS_SUPPORTED)) { 3821 bp->hw_tx_port_stats_ext = 3822 dma_alloc_coherent(&pdev->dev, 3823 sizeof(struct tx_port_stats_ext), 3824 &bp->hw_tx_port_stats_ext_map, 3825 GFP_KERNEL); 3826 } 3827 bp->flags |= BNXT_FLAG_PORT_STATS_EXT; 3828 3829 alloc_pcie_stats: 3830 if (bp->hw_pcie_stats || 3831 !(bp->fw_cap & BNXT_FW_CAP_PCIE_STATS_SUPPORTED)) 3832 return 0; 3833 3834 bp->hw_pcie_stats = 3835 dma_alloc_coherent(&pdev->dev, sizeof(struct pcie_ctx_hw_stats), 3836 &bp->hw_pcie_stats_map, GFP_KERNEL); 3837 if (!bp->hw_pcie_stats) 3838 return 0; 3839 3840 bp->flags |= BNXT_FLAG_PCIE_STATS; 3841 return 0; 3842 } 3843 3844 static void bnxt_clear_ring_indices(struct bnxt *bp) 3845 { 3846 int i; 3847 3848 if (!bp->bnapi) 3849 return; 3850 3851 for (i = 0; i < bp->cp_nr_rings; i++) { 3852 struct bnxt_napi *bnapi = bp->bnapi[i]; 3853 struct bnxt_cp_ring_info *cpr; 3854 struct bnxt_rx_ring_info *rxr; 3855 struct bnxt_tx_ring_info *txr; 3856 3857 if (!bnapi) 3858 continue; 3859 3860 cpr = &bnapi->cp_ring; 3861 cpr->cp_raw_cons = 0; 3862 3863 txr = bnapi->tx_ring; 3864 if (txr) { 3865 txr->tx_prod = 0; 3866 txr->tx_cons = 0; 3867 } 3868 3869 rxr = bnapi->rx_ring; 3870 if (rxr) { 3871 rxr->rx_prod = 0; 3872 rxr->rx_agg_prod = 0; 3873 rxr->rx_sw_agg_prod = 0; 3874 rxr->rx_next_cons = 0; 3875 } 3876 } 3877 } 3878 3879 static void bnxt_free_ntp_fltrs(struct bnxt *bp, bool irq_reinit) 3880 { 3881 #ifdef CONFIG_RFS_ACCEL 3882 int i; 3883 3884 /* Under rtnl_lock and all our NAPIs have been disabled. It's 3885 * safe to delete the hash table. 3886 */ 3887 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) { 3888 struct hlist_head *head; 3889 struct hlist_node *tmp; 3890 struct bnxt_ntuple_filter *fltr; 3891 3892 head = &bp->ntp_fltr_hash_tbl[i]; 3893 hlist_for_each_entry_safe(fltr, tmp, head, hash) { 3894 hlist_del(&fltr->hash); 3895 kfree(fltr); 3896 } 3897 } 3898 if (irq_reinit) { 3899 kfree(bp->ntp_fltr_bmap); 3900 bp->ntp_fltr_bmap = NULL; 3901 } 3902 bp->ntp_fltr_count = 0; 3903 #endif 3904 } 3905 3906 static int bnxt_alloc_ntp_fltrs(struct bnxt *bp) 3907 { 3908 #ifdef CONFIG_RFS_ACCEL 3909 int i, rc = 0; 3910 3911 if (!(bp->flags & BNXT_FLAG_RFS)) 3912 return 0; 3913 3914 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) 3915 INIT_HLIST_HEAD(&bp->ntp_fltr_hash_tbl[i]); 3916 3917 bp->ntp_fltr_count = 0; 3918 bp->ntp_fltr_bmap = kcalloc(BITS_TO_LONGS(BNXT_NTP_FLTR_MAX_FLTR), 3919 sizeof(long), 3920 GFP_KERNEL); 3921 3922 if (!bp->ntp_fltr_bmap) 3923 rc = -ENOMEM; 3924 3925 return rc; 3926 #else 3927 return 0; 3928 #endif 3929 } 3930 3931 static void bnxt_free_mem(struct bnxt *bp, bool irq_re_init) 3932 { 3933 bnxt_free_vnic_attributes(bp); 3934 bnxt_free_tx_rings(bp); 3935 bnxt_free_rx_rings(bp); 3936 bnxt_free_cp_rings(bp); 3937 bnxt_free_ntp_fltrs(bp, irq_re_init); 3938 if (irq_re_init) { 3939 bnxt_free_ring_stats(bp); 3940 bnxt_free_ring_grps(bp); 3941 bnxt_free_vnics(bp); 3942 kfree(bp->tx_ring_map); 3943 bp->tx_ring_map = NULL; 3944 kfree(bp->tx_ring); 3945 bp->tx_ring = NULL; 3946 kfree(bp->rx_ring); 3947 bp->rx_ring = NULL; 3948 kfree(bp->bnapi); 3949 bp->bnapi = NULL; 3950 } else { 3951 bnxt_clear_ring_indices(bp); 3952 } 3953 } 3954 3955 static int bnxt_alloc_mem(struct bnxt *bp, bool irq_re_init) 3956 { 3957 int i, j, rc, size, arr_size; 3958 void *bnapi; 3959 3960 if (irq_re_init) { 3961 /* Allocate bnapi mem pointer array and mem block for 3962 * all queues 3963 */ 3964 arr_size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi *) * 3965 bp->cp_nr_rings); 3966 size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi)); 3967 bnapi = kzalloc(arr_size + size * bp->cp_nr_rings, GFP_KERNEL); 3968 if (!bnapi) 3969 return -ENOMEM; 3970 3971 bp->bnapi = bnapi; 3972 bnapi += arr_size; 3973 for (i = 0; i < bp->cp_nr_rings; i++, bnapi += size) { 3974 bp->bnapi[i] = bnapi; 3975 bp->bnapi[i]->index = i; 3976 bp->bnapi[i]->bp = bp; 3977 if (bp->flags & BNXT_FLAG_CHIP_P5) { 3978 struct bnxt_cp_ring_info *cpr = 3979 &bp->bnapi[i]->cp_ring; 3980 3981 cpr->cp_ring_struct.ring_mem.flags = 3982 BNXT_RMEM_RING_PTE_FLAG; 3983 } 3984 } 3985 3986 bp->rx_ring = kcalloc(bp->rx_nr_rings, 3987 sizeof(struct bnxt_rx_ring_info), 3988 GFP_KERNEL); 3989 if (!bp->rx_ring) 3990 return -ENOMEM; 3991 3992 for (i = 0; i < bp->rx_nr_rings; i++) { 3993 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 3994 3995 if (bp->flags & BNXT_FLAG_CHIP_P5) { 3996 rxr->rx_ring_struct.ring_mem.flags = 3997 BNXT_RMEM_RING_PTE_FLAG; 3998 rxr->rx_agg_ring_struct.ring_mem.flags = 3999 BNXT_RMEM_RING_PTE_FLAG; 4000 } 4001 rxr->bnapi = bp->bnapi[i]; 4002 bp->bnapi[i]->rx_ring = &bp->rx_ring[i]; 4003 } 4004 4005 bp->tx_ring = kcalloc(bp->tx_nr_rings, 4006 sizeof(struct bnxt_tx_ring_info), 4007 GFP_KERNEL); 4008 if (!bp->tx_ring) 4009 return -ENOMEM; 4010 4011 bp->tx_ring_map = kcalloc(bp->tx_nr_rings, sizeof(u16), 4012 GFP_KERNEL); 4013 4014 if (!bp->tx_ring_map) 4015 return -ENOMEM; 4016 4017 if (bp->flags & BNXT_FLAG_SHARED_RINGS) 4018 j = 0; 4019 else 4020 j = bp->rx_nr_rings; 4021 4022 for (i = 0; i < bp->tx_nr_rings; i++, j++) { 4023 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; 4024 4025 if (bp->flags & BNXT_FLAG_CHIP_P5) 4026 txr->tx_ring_struct.ring_mem.flags = 4027 BNXT_RMEM_RING_PTE_FLAG; 4028 txr->bnapi = bp->bnapi[j]; 4029 bp->bnapi[j]->tx_ring = txr; 4030 bp->tx_ring_map[i] = bp->tx_nr_rings_xdp + i; 4031 if (i >= bp->tx_nr_rings_xdp) { 4032 txr->txq_index = i - bp->tx_nr_rings_xdp; 4033 bp->bnapi[j]->tx_int = bnxt_tx_int; 4034 } else { 4035 bp->bnapi[j]->flags |= BNXT_NAPI_FLAG_XDP; 4036 bp->bnapi[j]->tx_int = bnxt_tx_int_xdp; 4037 } 4038 } 4039 4040 rc = bnxt_alloc_stats(bp); 4041 if (rc) 4042 goto alloc_mem_err; 4043 4044 rc = bnxt_alloc_ntp_fltrs(bp); 4045 if (rc) 4046 goto alloc_mem_err; 4047 4048 rc = bnxt_alloc_vnics(bp); 4049 if (rc) 4050 goto alloc_mem_err; 4051 } 4052 4053 bnxt_init_ring_struct(bp); 4054 4055 rc = bnxt_alloc_rx_rings(bp); 4056 if (rc) 4057 goto alloc_mem_err; 4058 4059 rc = bnxt_alloc_tx_rings(bp); 4060 if (rc) 4061 goto alloc_mem_err; 4062 4063 rc = bnxt_alloc_cp_rings(bp); 4064 if (rc) 4065 goto alloc_mem_err; 4066 4067 bp->vnic_info[0].flags |= BNXT_VNIC_RSS_FLAG | BNXT_VNIC_MCAST_FLAG | 4068 BNXT_VNIC_UCAST_FLAG; 4069 rc = bnxt_alloc_vnic_attributes(bp); 4070 if (rc) 4071 goto alloc_mem_err; 4072 return 0; 4073 4074 alloc_mem_err: 4075 bnxt_free_mem(bp, true); 4076 return rc; 4077 } 4078 4079 static void bnxt_disable_int(struct bnxt *bp) 4080 { 4081 int i; 4082 4083 if (!bp->bnapi) 4084 return; 4085 4086 for (i = 0; i < bp->cp_nr_rings; i++) { 4087 struct bnxt_napi *bnapi = bp->bnapi[i]; 4088 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 4089 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct; 4090 4091 if (ring->fw_ring_id != INVALID_HW_RING_ID) 4092 bnxt_db_nq(bp, &cpr->cp_db, cpr->cp_raw_cons); 4093 } 4094 } 4095 4096 static int bnxt_cp_num_to_irq_num(struct bnxt *bp, int n) 4097 { 4098 struct bnxt_napi *bnapi = bp->bnapi[n]; 4099 struct bnxt_cp_ring_info *cpr; 4100 4101 cpr = &bnapi->cp_ring; 4102 return cpr->cp_ring_struct.map_idx; 4103 } 4104 4105 static void bnxt_disable_int_sync(struct bnxt *bp) 4106 { 4107 int i; 4108 4109 atomic_inc(&bp->intr_sem); 4110 4111 bnxt_disable_int(bp); 4112 for (i = 0; i < bp->cp_nr_rings; i++) { 4113 int map_idx = bnxt_cp_num_to_irq_num(bp, i); 4114 4115 synchronize_irq(bp->irq_tbl[map_idx].vector); 4116 } 4117 } 4118 4119 static void bnxt_enable_int(struct bnxt *bp) 4120 { 4121 int i; 4122 4123 atomic_set(&bp->intr_sem, 0); 4124 for (i = 0; i < bp->cp_nr_rings; i++) { 4125 struct bnxt_napi *bnapi = bp->bnapi[i]; 4126 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 4127 4128 bnxt_db_nq_arm(bp, &cpr->cp_db, cpr->cp_raw_cons); 4129 } 4130 } 4131 4132 void bnxt_hwrm_cmd_hdr_init(struct bnxt *bp, void *request, u16 req_type, 4133 u16 cmpl_ring, u16 target_id) 4134 { 4135 struct input *req = request; 4136 4137 req->req_type = cpu_to_le16(req_type); 4138 req->cmpl_ring = cpu_to_le16(cmpl_ring); 4139 req->target_id = cpu_to_le16(target_id); 4140 if (bnxt_kong_hwrm_message(bp, req)) 4141 req->resp_addr = cpu_to_le64(bp->hwrm_cmd_kong_resp_dma_addr); 4142 else 4143 req->resp_addr = cpu_to_le64(bp->hwrm_cmd_resp_dma_addr); 4144 } 4145 4146 static int bnxt_hwrm_to_stderr(u32 hwrm_err) 4147 { 4148 switch (hwrm_err) { 4149 case HWRM_ERR_CODE_SUCCESS: 4150 return 0; 4151 case HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED: 4152 return -EACCES; 4153 case HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR: 4154 return -ENOSPC; 4155 case HWRM_ERR_CODE_INVALID_PARAMS: 4156 case HWRM_ERR_CODE_INVALID_FLAGS: 4157 case HWRM_ERR_CODE_INVALID_ENABLES: 4158 case HWRM_ERR_CODE_UNSUPPORTED_TLV: 4159 case HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR: 4160 return -EINVAL; 4161 case HWRM_ERR_CODE_NO_BUFFER: 4162 return -ENOMEM; 4163 case HWRM_ERR_CODE_HOT_RESET_PROGRESS: 4164 case HWRM_ERR_CODE_BUSY: 4165 return -EAGAIN; 4166 case HWRM_ERR_CODE_CMD_NOT_SUPPORTED: 4167 return -EOPNOTSUPP; 4168 default: 4169 return -EIO; 4170 } 4171 } 4172 4173 static int bnxt_hwrm_do_send_msg(struct bnxt *bp, void *msg, u32 msg_len, 4174 int timeout, bool silent) 4175 { 4176 int i, intr_process, rc, tmo_count; 4177 struct input *req = msg; 4178 u32 *data = msg; 4179 u8 *valid; 4180 u16 cp_ring_id, len = 0; 4181 struct hwrm_err_output *resp = bp->hwrm_cmd_resp_addr; 4182 u16 max_req_len = BNXT_HWRM_MAX_REQ_LEN; 4183 struct hwrm_short_input short_input = {0}; 4184 u32 doorbell_offset = BNXT_GRCPF_REG_CHIMP_COMM_TRIGGER; 4185 u32 bar_offset = BNXT_GRCPF_REG_CHIMP_COMM; 4186 u16 dst = BNXT_HWRM_CHNL_CHIMP; 4187 4188 if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state)) 4189 return -EBUSY; 4190 4191 if (msg_len > BNXT_HWRM_MAX_REQ_LEN) { 4192 if (msg_len > bp->hwrm_max_ext_req_len || 4193 !bp->hwrm_short_cmd_req_addr) 4194 return -EINVAL; 4195 } 4196 4197 if (bnxt_hwrm_kong_chnl(bp, req)) { 4198 dst = BNXT_HWRM_CHNL_KONG; 4199 bar_offset = BNXT_GRCPF_REG_KONG_COMM; 4200 doorbell_offset = BNXT_GRCPF_REG_KONG_COMM_TRIGGER; 4201 resp = bp->hwrm_cmd_kong_resp_addr; 4202 } 4203 4204 memset(resp, 0, PAGE_SIZE); 4205 cp_ring_id = le16_to_cpu(req->cmpl_ring); 4206 intr_process = (cp_ring_id == INVALID_HW_RING_ID) ? 0 : 1; 4207 4208 req->seq_id = cpu_to_le16(bnxt_get_hwrm_seq_id(bp, dst)); 4209 /* currently supports only one outstanding message */ 4210 if (intr_process) 4211 bp->hwrm_intr_seq_id = le16_to_cpu(req->seq_id); 4212 4213 if ((bp->fw_cap & BNXT_FW_CAP_SHORT_CMD) || 4214 msg_len > BNXT_HWRM_MAX_REQ_LEN) { 4215 void *short_cmd_req = bp->hwrm_short_cmd_req_addr; 4216 u16 max_msg_len; 4217 4218 /* Set boundary for maximum extended request length for short 4219 * cmd format. If passed up from device use the max supported 4220 * internal req length. 4221 */ 4222 max_msg_len = bp->hwrm_max_ext_req_len; 4223 4224 memcpy(short_cmd_req, req, msg_len); 4225 if (msg_len < max_msg_len) 4226 memset(short_cmd_req + msg_len, 0, 4227 max_msg_len - msg_len); 4228 4229 short_input.req_type = req->req_type; 4230 short_input.signature = 4231 cpu_to_le16(SHORT_REQ_SIGNATURE_SHORT_CMD); 4232 short_input.size = cpu_to_le16(msg_len); 4233 short_input.req_addr = 4234 cpu_to_le64(bp->hwrm_short_cmd_req_dma_addr); 4235 4236 data = (u32 *)&short_input; 4237 msg_len = sizeof(short_input); 4238 4239 /* Sync memory write before updating doorbell */ 4240 wmb(); 4241 4242 max_req_len = BNXT_HWRM_SHORT_REQ_LEN; 4243 } 4244 4245 /* Write request msg to hwrm channel */ 4246 __iowrite32_copy(bp->bar0 + bar_offset, data, msg_len / 4); 4247 4248 for (i = msg_len; i < max_req_len; i += 4) 4249 writel(0, bp->bar0 + bar_offset + i); 4250 4251 /* Ring channel doorbell */ 4252 writel(1, bp->bar0 + doorbell_offset); 4253 4254 if (!pci_is_enabled(bp->pdev)) 4255 return 0; 4256 4257 if (!timeout) 4258 timeout = DFLT_HWRM_CMD_TIMEOUT; 4259 /* convert timeout to usec */ 4260 timeout *= 1000; 4261 4262 i = 0; 4263 /* Short timeout for the first few iterations: 4264 * number of loops = number of loops for short timeout + 4265 * number of loops for standard timeout. 4266 */ 4267 tmo_count = HWRM_SHORT_TIMEOUT_COUNTER; 4268 timeout = timeout - HWRM_SHORT_MIN_TIMEOUT * HWRM_SHORT_TIMEOUT_COUNTER; 4269 tmo_count += DIV_ROUND_UP(timeout, HWRM_MIN_TIMEOUT); 4270 4271 if (intr_process) { 4272 u16 seq_id = bp->hwrm_intr_seq_id; 4273 4274 /* Wait until hwrm response cmpl interrupt is processed */ 4275 while (bp->hwrm_intr_seq_id != (u16)~seq_id && 4276 i++ < tmo_count) { 4277 /* Abort the wait for completion if the FW health 4278 * check has failed. 4279 */ 4280 if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state)) 4281 return -EBUSY; 4282 /* on first few passes, just barely sleep */ 4283 if (i < HWRM_SHORT_TIMEOUT_COUNTER) 4284 usleep_range(HWRM_SHORT_MIN_TIMEOUT, 4285 HWRM_SHORT_MAX_TIMEOUT); 4286 else 4287 usleep_range(HWRM_MIN_TIMEOUT, 4288 HWRM_MAX_TIMEOUT); 4289 } 4290 4291 if (bp->hwrm_intr_seq_id != (u16)~seq_id) { 4292 if (!silent) 4293 netdev_err(bp->dev, "Resp cmpl intr err msg: 0x%x\n", 4294 le16_to_cpu(req->req_type)); 4295 return -EBUSY; 4296 } 4297 len = le16_to_cpu(resp->resp_len); 4298 valid = ((u8 *)resp) + len - 1; 4299 } else { 4300 int j; 4301 4302 /* Check if response len is updated */ 4303 for (i = 0; i < tmo_count; i++) { 4304 /* Abort the wait for completion if the FW health 4305 * check has failed. 4306 */ 4307 if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state)) 4308 return -EBUSY; 4309 len = le16_to_cpu(resp->resp_len); 4310 if (len) 4311 break; 4312 /* on first few passes, just barely sleep */ 4313 if (i < HWRM_SHORT_TIMEOUT_COUNTER) 4314 usleep_range(HWRM_SHORT_MIN_TIMEOUT, 4315 HWRM_SHORT_MAX_TIMEOUT); 4316 else 4317 usleep_range(HWRM_MIN_TIMEOUT, 4318 HWRM_MAX_TIMEOUT); 4319 } 4320 4321 if (i >= tmo_count) { 4322 if (!silent) 4323 netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d\n", 4324 HWRM_TOTAL_TIMEOUT(i), 4325 le16_to_cpu(req->req_type), 4326 le16_to_cpu(req->seq_id), len); 4327 return -EBUSY; 4328 } 4329 4330 /* Last byte of resp contains valid bit */ 4331 valid = ((u8 *)resp) + len - 1; 4332 for (j = 0; j < HWRM_VALID_BIT_DELAY_USEC; j++) { 4333 /* make sure we read from updated DMA memory */ 4334 dma_rmb(); 4335 if (*valid) 4336 break; 4337 usleep_range(1, 5); 4338 } 4339 4340 if (j >= HWRM_VALID_BIT_DELAY_USEC) { 4341 if (!silent) 4342 netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d v:%d\n", 4343 HWRM_TOTAL_TIMEOUT(i), 4344 le16_to_cpu(req->req_type), 4345 le16_to_cpu(req->seq_id), len, 4346 *valid); 4347 return -EBUSY; 4348 } 4349 } 4350 4351 /* Zero valid bit for compatibility. Valid bit in an older spec 4352 * may become a new field in a newer spec. We must make sure that 4353 * a new field not implemented by old spec will read zero. 4354 */ 4355 *valid = 0; 4356 rc = le16_to_cpu(resp->error_code); 4357 if (rc && !silent) 4358 netdev_err(bp->dev, "hwrm req_type 0x%x seq id 0x%x error 0x%x\n", 4359 le16_to_cpu(resp->req_type), 4360 le16_to_cpu(resp->seq_id), rc); 4361 return bnxt_hwrm_to_stderr(rc); 4362 } 4363 4364 int _hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout) 4365 { 4366 return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, false); 4367 } 4368 4369 int _hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len, 4370 int timeout) 4371 { 4372 return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true); 4373 } 4374 4375 int hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout) 4376 { 4377 int rc; 4378 4379 mutex_lock(&bp->hwrm_cmd_lock); 4380 rc = _hwrm_send_message(bp, msg, msg_len, timeout); 4381 mutex_unlock(&bp->hwrm_cmd_lock); 4382 return rc; 4383 } 4384 4385 int hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len, 4386 int timeout) 4387 { 4388 int rc; 4389 4390 mutex_lock(&bp->hwrm_cmd_lock); 4391 rc = bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true); 4392 mutex_unlock(&bp->hwrm_cmd_lock); 4393 return rc; 4394 } 4395 4396 int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp, unsigned long *bmap, int bmap_size, 4397 bool async_only) 4398 { 4399 struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr; 4400 struct hwrm_func_drv_rgtr_input req = {0}; 4401 DECLARE_BITMAP(async_events_bmap, 256); 4402 u32 *events = (u32 *)async_events_bmap; 4403 u32 flags; 4404 int rc, i; 4405 4406 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1); 4407 4408 req.enables = 4409 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE | 4410 FUNC_DRV_RGTR_REQ_ENABLES_VER | 4411 FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD); 4412 4413 req.os_type = cpu_to_le16(FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX); 4414 flags = FUNC_DRV_RGTR_REQ_FLAGS_16BIT_VER_MODE; 4415 if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET) 4416 flags |= FUNC_DRV_RGTR_REQ_FLAGS_HOT_RESET_SUPPORT; 4417 if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY) 4418 flags |= FUNC_DRV_RGTR_REQ_FLAGS_ERROR_RECOVERY_SUPPORT | 4419 FUNC_DRV_RGTR_REQ_FLAGS_MASTER_SUPPORT; 4420 req.flags = cpu_to_le32(flags); 4421 req.ver_maj_8b = DRV_VER_MAJ; 4422 req.ver_min_8b = DRV_VER_MIN; 4423 req.ver_upd_8b = DRV_VER_UPD; 4424 req.ver_maj = cpu_to_le16(DRV_VER_MAJ); 4425 req.ver_min = cpu_to_le16(DRV_VER_MIN); 4426 req.ver_upd = cpu_to_le16(DRV_VER_UPD); 4427 4428 if (BNXT_PF(bp)) { 4429 u32 data[8]; 4430 int i; 4431 4432 memset(data, 0, sizeof(data)); 4433 for (i = 0; i < ARRAY_SIZE(bnxt_vf_req_snif); i++) { 4434 u16 cmd = bnxt_vf_req_snif[i]; 4435 unsigned int bit, idx; 4436 4437 idx = cmd / 32; 4438 bit = cmd % 32; 4439 data[idx] |= 1 << bit; 4440 } 4441 4442 for (i = 0; i < 8; i++) 4443 req.vf_req_fwd[i] = cpu_to_le32(data[i]); 4444 4445 req.enables |= 4446 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD); 4447 } 4448 4449 if (bp->fw_cap & BNXT_FW_CAP_OVS_64BIT_HANDLE) 4450 req.flags |= cpu_to_le32( 4451 FUNC_DRV_RGTR_REQ_FLAGS_FLOW_HANDLE_64BIT_MODE); 4452 4453 memset(async_events_bmap, 0, sizeof(async_events_bmap)); 4454 for (i = 0; i < ARRAY_SIZE(bnxt_async_events_arr); i++) { 4455 u16 event_id = bnxt_async_events_arr[i]; 4456 4457 if (event_id == ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY && 4458 !(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)) 4459 continue; 4460 __set_bit(bnxt_async_events_arr[i], async_events_bmap); 4461 } 4462 if (bmap && bmap_size) { 4463 for (i = 0; i < bmap_size; i++) { 4464 if (test_bit(i, bmap)) 4465 __set_bit(i, async_events_bmap); 4466 } 4467 } 4468 for (i = 0; i < 8; i++) 4469 req.async_event_fwd[i] |= cpu_to_le32(events[i]); 4470 4471 if (async_only) 4472 req.enables = 4473 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD); 4474 4475 mutex_lock(&bp->hwrm_cmd_lock); 4476 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4477 if (!rc) { 4478 set_bit(BNXT_STATE_DRV_REGISTERED, &bp->state); 4479 if (resp->flags & 4480 cpu_to_le32(FUNC_DRV_RGTR_RESP_FLAGS_IF_CHANGE_SUPPORTED)) 4481 bp->fw_cap |= BNXT_FW_CAP_IF_CHANGE; 4482 } 4483 mutex_unlock(&bp->hwrm_cmd_lock); 4484 return rc; 4485 } 4486 4487 static int bnxt_hwrm_func_drv_unrgtr(struct bnxt *bp) 4488 { 4489 struct hwrm_func_drv_unrgtr_input req = {0}; 4490 4491 if (!test_and_clear_bit(BNXT_STATE_DRV_REGISTERED, &bp->state)) 4492 return 0; 4493 4494 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_UNRGTR, -1, -1); 4495 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4496 } 4497 4498 static int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, u8 tunnel_type) 4499 { 4500 u32 rc = 0; 4501 struct hwrm_tunnel_dst_port_free_input req = {0}; 4502 4503 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_FREE, -1, -1); 4504 req.tunnel_type = tunnel_type; 4505 4506 switch (tunnel_type) { 4507 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN: 4508 req.tunnel_dst_port_id = bp->vxlan_fw_dst_port_id; 4509 break; 4510 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE: 4511 req.tunnel_dst_port_id = bp->nge_fw_dst_port_id; 4512 break; 4513 default: 4514 break; 4515 } 4516 4517 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4518 if (rc) 4519 netdev_err(bp->dev, "hwrm_tunnel_dst_port_free failed. rc:%d\n", 4520 rc); 4521 return rc; 4522 } 4523 4524 static int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, __be16 port, 4525 u8 tunnel_type) 4526 { 4527 u32 rc = 0; 4528 struct hwrm_tunnel_dst_port_alloc_input req = {0}; 4529 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr; 4530 4531 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_ALLOC, -1, -1); 4532 4533 req.tunnel_type = tunnel_type; 4534 req.tunnel_dst_port_val = port; 4535 4536 mutex_lock(&bp->hwrm_cmd_lock); 4537 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4538 if (rc) { 4539 netdev_err(bp->dev, "hwrm_tunnel_dst_port_alloc failed. rc:%d\n", 4540 rc); 4541 goto err_out; 4542 } 4543 4544 switch (tunnel_type) { 4545 case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN: 4546 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id; 4547 break; 4548 case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE: 4549 bp->nge_fw_dst_port_id = resp->tunnel_dst_port_id; 4550 break; 4551 default: 4552 break; 4553 } 4554 4555 err_out: 4556 mutex_unlock(&bp->hwrm_cmd_lock); 4557 return rc; 4558 } 4559 4560 static int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp, u16 vnic_id) 4561 { 4562 struct hwrm_cfa_l2_set_rx_mask_input req = {0}; 4563 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 4564 4565 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_SET_RX_MASK, -1, -1); 4566 req.vnic_id = cpu_to_le32(vnic->fw_vnic_id); 4567 4568 req.num_mc_entries = cpu_to_le32(vnic->mc_list_count); 4569 req.mc_tbl_addr = cpu_to_le64(vnic->mc_list_mapping); 4570 req.mask = cpu_to_le32(vnic->rx_mask); 4571 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4572 } 4573 4574 #ifdef CONFIG_RFS_ACCEL 4575 static int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt *bp, 4576 struct bnxt_ntuple_filter *fltr) 4577 { 4578 struct hwrm_cfa_ntuple_filter_free_input req = {0}; 4579 4580 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_FREE, -1, -1); 4581 req.ntuple_filter_id = fltr->filter_id; 4582 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4583 } 4584 4585 #define BNXT_NTP_FLTR_FLAGS \ 4586 (CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID | \ 4587 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE | \ 4588 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR | \ 4589 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE | \ 4590 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR | \ 4591 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK | \ 4592 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR | \ 4593 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK | \ 4594 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL | \ 4595 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT | \ 4596 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK | \ 4597 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT | \ 4598 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK | \ 4599 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID) 4600 4601 #define BNXT_NTP_TUNNEL_FLTR_FLAG \ 4602 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 4603 4604 static int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt *bp, 4605 struct bnxt_ntuple_filter *fltr) 4606 { 4607 struct hwrm_cfa_ntuple_filter_alloc_input req = {0}; 4608 struct hwrm_cfa_ntuple_filter_alloc_output *resp; 4609 struct flow_keys *keys = &fltr->fkeys; 4610 struct bnxt_vnic_info *vnic; 4611 u32 flags = 0; 4612 int rc = 0; 4613 4614 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_ALLOC, -1, -1); 4615 req.l2_filter_id = bp->vnic_info[0].fw_l2_filter_id[fltr->l2_fltr_idx]; 4616 4617 if (bp->fw_cap & BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V2) { 4618 flags = CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DEST_RFS_RING_IDX; 4619 req.dst_id = cpu_to_le16(fltr->rxq); 4620 } else { 4621 vnic = &bp->vnic_info[fltr->rxq + 1]; 4622 req.dst_id = cpu_to_le16(vnic->fw_vnic_id); 4623 } 4624 req.flags = cpu_to_le32(flags); 4625 req.enables = cpu_to_le32(BNXT_NTP_FLTR_FLAGS); 4626 4627 req.ethertype = htons(ETH_P_IP); 4628 memcpy(req.src_macaddr, fltr->src_mac_addr, ETH_ALEN); 4629 req.ip_addr_type = CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4; 4630 req.ip_protocol = keys->basic.ip_proto; 4631 4632 if (keys->basic.n_proto == htons(ETH_P_IPV6)) { 4633 int i; 4634 4635 req.ethertype = htons(ETH_P_IPV6); 4636 req.ip_addr_type = 4637 CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6; 4638 *(struct in6_addr *)&req.src_ipaddr[0] = 4639 keys->addrs.v6addrs.src; 4640 *(struct in6_addr *)&req.dst_ipaddr[0] = 4641 keys->addrs.v6addrs.dst; 4642 for (i = 0; i < 4; i++) { 4643 req.src_ipaddr_mask[i] = cpu_to_be32(0xffffffff); 4644 req.dst_ipaddr_mask[i] = cpu_to_be32(0xffffffff); 4645 } 4646 } else { 4647 req.src_ipaddr[0] = keys->addrs.v4addrs.src; 4648 req.src_ipaddr_mask[0] = cpu_to_be32(0xffffffff); 4649 req.dst_ipaddr[0] = keys->addrs.v4addrs.dst; 4650 req.dst_ipaddr_mask[0] = cpu_to_be32(0xffffffff); 4651 } 4652 if (keys->control.flags & FLOW_DIS_ENCAPSULATION) { 4653 req.enables |= cpu_to_le32(BNXT_NTP_TUNNEL_FLTR_FLAG); 4654 req.tunnel_type = 4655 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL; 4656 } 4657 4658 req.src_port = keys->ports.src; 4659 req.src_port_mask = cpu_to_be16(0xffff); 4660 req.dst_port = keys->ports.dst; 4661 req.dst_port_mask = cpu_to_be16(0xffff); 4662 4663 mutex_lock(&bp->hwrm_cmd_lock); 4664 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4665 if (!rc) { 4666 resp = bnxt_get_hwrm_resp_addr(bp, &req); 4667 fltr->filter_id = resp->ntuple_filter_id; 4668 } 4669 mutex_unlock(&bp->hwrm_cmd_lock); 4670 return rc; 4671 } 4672 #endif 4673 4674 static int bnxt_hwrm_set_vnic_filter(struct bnxt *bp, u16 vnic_id, u16 idx, 4675 u8 *mac_addr) 4676 { 4677 u32 rc = 0; 4678 struct hwrm_cfa_l2_filter_alloc_input req = {0}; 4679 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr; 4680 4681 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_ALLOC, -1, -1); 4682 req.flags = cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX); 4683 if (!BNXT_CHIP_TYPE_NITRO_A0(bp)) 4684 req.flags |= 4685 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST); 4686 req.dst_id = cpu_to_le16(bp->vnic_info[vnic_id].fw_vnic_id); 4687 req.enables = 4688 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR | 4689 CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID | 4690 CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK); 4691 memcpy(req.l2_addr, mac_addr, ETH_ALEN); 4692 req.l2_addr_mask[0] = 0xff; 4693 req.l2_addr_mask[1] = 0xff; 4694 req.l2_addr_mask[2] = 0xff; 4695 req.l2_addr_mask[3] = 0xff; 4696 req.l2_addr_mask[4] = 0xff; 4697 req.l2_addr_mask[5] = 0xff; 4698 4699 mutex_lock(&bp->hwrm_cmd_lock); 4700 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4701 if (!rc) 4702 bp->vnic_info[vnic_id].fw_l2_filter_id[idx] = 4703 resp->l2_filter_id; 4704 mutex_unlock(&bp->hwrm_cmd_lock); 4705 return rc; 4706 } 4707 4708 static int bnxt_hwrm_clear_vnic_filter(struct bnxt *bp) 4709 { 4710 u16 i, j, num_of_vnics = 1; /* only vnic 0 supported */ 4711 int rc = 0; 4712 4713 /* Any associated ntuple filters will also be cleared by firmware. */ 4714 mutex_lock(&bp->hwrm_cmd_lock); 4715 for (i = 0; i < num_of_vnics; i++) { 4716 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 4717 4718 for (j = 0; j < vnic->uc_filter_count; j++) { 4719 struct hwrm_cfa_l2_filter_free_input req = {0}; 4720 4721 bnxt_hwrm_cmd_hdr_init(bp, &req, 4722 HWRM_CFA_L2_FILTER_FREE, -1, -1); 4723 4724 req.l2_filter_id = vnic->fw_l2_filter_id[j]; 4725 4726 rc = _hwrm_send_message(bp, &req, sizeof(req), 4727 HWRM_CMD_TIMEOUT); 4728 } 4729 vnic->uc_filter_count = 0; 4730 } 4731 mutex_unlock(&bp->hwrm_cmd_lock); 4732 4733 return rc; 4734 } 4735 4736 static int bnxt_hwrm_vnic_set_tpa(struct bnxt *bp, u16 vnic_id, u32 tpa_flags) 4737 { 4738 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 4739 u16 max_aggs = VNIC_TPA_CFG_REQ_MAX_AGGS_MAX; 4740 struct hwrm_vnic_tpa_cfg_input req = {0}; 4741 4742 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) 4743 return 0; 4744 4745 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_TPA_CFG, -1, -1); 4746 4747 if (tpa_flags) { 4748 u16 mss = bp->dev->mtu - 40; 4749 u32 nsegs, n, segs = 0, flags; 4750 4751 flags = VNIC_TPA_CFG_REQ_FLAGS_TPA | 4752 VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA | 4753 VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE | 4754 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN | 4755 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ; 4756 if (tpa_flags & BNXT_FLAG_GRO) 4757 flags |= VNIC_TPA_CFG_REQ_FLAGS_GRO; 4758 4759 req.flags = cpu_to_le32(flags); 4760 4761 req.enables = 4762 cpu_to_le32(VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS | 4763 VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS | 4764 VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN); 4765 4766 /* Number of segs are log2 units, and first packet is not 4767 * included as part of this units. 4768 */ 4769 if (mss <= BNXT_RX_PAGE_SIZE) { 4770 n = BNXT_RX_PAGE_SIZE / mss; 4771 nsegs = (MAX_SKB_FRAGS - 1) * n; 4772 } else { 4773 n = mss / BNXT_RX_PAGE_SIZE; 4774 if (mss & (BNXT_RX_PAGE_SIZE - 1)) 4775 n++; 4776 nsegs = (MAX_SKB_FRAGS - n) / n; 4777 } 4778 4779 if (bp->flags & BNXT_FLAG_CHIP_P5) { 4780 segs = MAX_TPA_SEGS_P5; 4781 max_aggs = bp->max_tpa; 4782 } else { 4783 segs = ilog2(nsegs); 4784 } 4785 req.max_agg_segs = cpu_to_le16(segs); 4786 req.max_aggs = cpu_to_le16(max_aggs); 4787 4788 req.min_agg_len = cpu_to_le32(512); 4789 } 4790 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id); 4791 4792 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4793 } 4794 4795 static u16 bnxt_cp_ring_from_grp(struct bnxt *bp, struct bnxt_ring_struct *ring) 4796 { 4797 struct bnxt_ring_grp_info *grp_info; 4798 4799 grp_info = &bp->grp_info[ring->grp_idx]; 4800 return grp_info->cp_fw_ring_id; 4801 } 4802 4803 static u16 bnxt_cp_ring_for_rx(struct bnxt *bp, struct bnxt_rx_ring_info *rxr) 4804 { 4805 if (bp->flags & BNXT_FLAG_CHIP_P5) { 4806 struct bnxt_napi *bnapi = rxr->bnapi; 4807 struct bnxt_cp_ring_info *cpr; 4808 4809 cpr = bnapi->cp_ring.cp_ring_arr[BNXT_RX_HDL]; 4810 return cpr->cp_ring_struct.fw_ring_id; 4811 } else { 4812 return bnxt_cp_ring_from_grp(bp, &rxr->rx_ring_struct); 4813 } 4814 } 4815 4816 static u16 bnxt_cp_ring_for_tx(struct bnxt *bp, struct bnxt_tx_ring_info *txr) 4817 { 4818 if (bp->flags & BNXT_FLAG_CHIP_P5) { 4819 struct bnxt_napi *bnapi = txr->bnapi; 4820 struct bnxt_cp_ring_info *cpr; 4821 4822 cpr = bnapi->cp_ring.cp_ring_arr[BNXT_TX_HDL]; 4823 return cpr->cp_ring_struct.fw_ring_id; 4824 } else { 4825 return bnxt_cp_ring_from_grp(bp, &txr->tx_ring_struct); 4826 } 4827 } 4828 4829 static int bnxt_hwrm_vnic_set_rss(struct bnxt *bp, u16 vnic_id, bool set_rss) 4830 { 4831 u32 i, j, max_rings; 4832 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 4833 struct hwrm_vnic_rss_cfg_input req = {0}; 4834 4835 if ((bp->flags & BNXT_FLAG_CHIP_P5) || 4836 vnic->fw_rss_cos_lb_ctx[0] == INVALID_HW_RING_ID) 4837 return 0; 4838 4839 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1); 4840 if (set_rss) { 4841 req.hash_type = cpu_to_le32(bp->rss_hash_cfg); 4842 req.hash_mode_flags = VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT; 4843 if (vnic->flags & BNXT_VNIC_RSS_FLAG) { 4844 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 4845 max_rings = bp->rx_nr_rings - 1; 4846 else 4847 max_rings = bp->rx_nr_rings; 4848 } else { 4849 max_rings = 1; 4850 } 4851 4852 /* Fill the RSS indirection table with ring group ids */ 4853 for (i = 0, j = 0; i < HW_HASH_INDEX_SIZE; i++, j++) { 4854 if (j == max_rings) 4855 j = 0; 4856 vnic->rss_table[i] = cpu_to_le16(vnic->fw_grp_ids[j]); 4857 } 4858 4859 req.ring_grp_tbl_addr = cpu_to_le64(vnic->rss_table_dma_addr); 4860 req.hash_key_tbl_addr = 4861 cpu_to_le64(vnic->rss_hash_key_dma_addr); 4862 } 4863 req.rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]); 4864 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4865 } 4866 4867 static int bnxt_hwrm_vnic_set_rss_p5(struct bnxt *bp, u16 vnic_id, bool set_rss) 4868 { 4869 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 4870 u32 i, j, k, nr_ctxs, max_rings = bp->rx_nr_rings; 4871 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[0]; 4872 struct hwrm_vnic_rss_cfg_input req = {0}; 4873 4874 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1); 4875 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id); 4876 if (!set_rss) { 4877 hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4878 return 0; 4879 } 4880 req.hash_type = cpu_to_le32(bp->rss_hash_cfg); 4881 req.hash_mode_flags = VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT; 4882 req.ring_grp_tbl_addr = cpu_to_le64(vnic->rss_table_dma_addr); 4883 req.hash_key_tbl_addr = cpu_to_le64(vnic->rss_hash_key_dma_addr); 4884 nr_ctxs = DIV_ROUND_UP(bp->rx_nr_rings, 64); 4885 for (i = 0, k = 0; i < nr_ctxs; i++) { 4886 __le16 *ring_tbl = vnic->rss_table; 4887 int rc; 4888 4889 req.ring_table_pair_index = i; 4890 req.rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[i]); 4891 for (j = 0; j < 64; j++) { 4892 u16 ring_id; 4893 4894 ring_id = rxr->rx_ring_struct.fw_ring_id; 4895 *ring_tbl++ = cpu_to_le16(ring_id); 4896 ring_id = bnxt_cp_ring_for_rx(bp, rxr); 4897 *ring_tbl++ = cpu_to_le16(ring_id); 4898 rxr++; 4899 k++; 4900 if (k == max_rings) { 4901 k = 0; 4902 rxr = &bp->rx_ring[0]; 4903 } 4904 } 4905 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4906 if (rc) 4907 return rc; 4908 } 4909 return 0; 4910 } 4911 4912 static int bnxt_hwrm_vnic_set_hds(struct bnxt *bp, u16 vnic_id) 4913 { 4914 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 4915 struct hwrm_vnic_plcmodes_cfg_input req = {0}; 4916 4917 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_PLCMODES_CFG, -1, -1); 4918 req.flags = cpu_to_le32(VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT | 4919 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 | 4920 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6); 4921 req.enables = 4922 cpu_to_le32(VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID | 4923 VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID); 4924 /* thresholds not implemented in firmware yet */ 4925 req.jumbo_thresh = cpu_to_le16(bp->rx_copy_thresh); 4926 req.hds_threshold = cpu_to_le16(bp->rx_copy_thresh); 4927 req.vnic_id = cpu_to_le32(vnic->fw_vnic_id); 4928 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4929 } 4930 4931 static void bnxt_hwrm_vnic_ctx_free_one(struct bnxt *bp, u16 vnic_id, 4932 u16 ctx_idx) 4933 { 4934 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {0}; 4935 4936 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, -1, -1); 4937 req.rss_cos_lb_ctx_id = 4938 cpu_to_le16(bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx]); 4939 4940 hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4941 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] = INVALID_HW_RING_ID; 4942 } 4943 4944 static void bnxt_hwrm_vnic_ctx_free(struct bnxt *bp) 4945 { 4946 int i, j; 4947 4948 for (i = 0; i < bp->nr_vnics; i++) { 4949 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 4950 4951 for (j = 0; j < BNXT_MAX_CTX_PER_VNIC; j++) { 4952 if (vnic->fw_rss_cos_lb_ctx[j] != INVALID_HW_RING_ID) 4953 bnxt_hwrm_vnic_ctx_free_one(bp, i, j); 4954 } 4955 } 4956 bp->rsscos_nr_ctxs = 0; 4957 } 4958 4959 static int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, u16 vnic_id, u16 ctx_idx) 4960 { 4961 int rc; 4962 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {0}; 4963 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp = 4964 bp->hwrm_cmd_resp_addr; 4965 4966 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, -1, 4967 -1); 4968 4969 mutex_lock(&bp->hwrm_cmd_lock); 4970 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4971 if (!rc) 4972 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] = 4973 le16_to_cpu(resp->rss_cos_lb_ctx_id); 4974 mutex_unlock(&bp->hwrm_cmd_lock); 4975 4976 return rc; 4977 } 4978 4979 static u32 bnxt_get_roce_vnic_mode(struct bnxt *bp) 4980 { 4981 if (bp->flags & BNXT_FLAG_ROCE_MIRROR_CAP) 4982 return VNIC_CFG_REQ_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE; 4983 return VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE; 4984 } 4985 4986 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id) 4987 { 4988 unsigned int ring = 0, grp_idx; 4989 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 4990 struct hwrm_vnic_cfg_input req = {0}; 4991 u16 def_vlan = 0; 4992 4993 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_CFG, -1, -1); 4994 4995 if (bp->flags & BNXT_FLAG_CHIP_P5) { 4996 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[0]; 4997 4998 req.default_rx_ring_id = 4999 cpu_to_le16(rxr->rx_ring_struct.fw_ring_id); 5000 req.default_cmpl_ring_id = 5001 cpu_to_le16(bnxt_cp_ring_for_rx(bp, rxr)); 5002 req.enables = 5003 cpu_to_le32(VNIC_CFG_REQ_ENABLES_DEFAULT_RX_RING_ID | 5004 VNIC_CFG_REQ_ENABLES_DEFAULT_CMPL_RING_ID); 5005 goto vnic_mru; 5006 } 5007 req.enables = cpu_to_le32(VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP); 5008 /* Only RSS support for now TBD: COS & LB */ 5009 if (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID) { 5010 req.rss_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]); 5011 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE | 5012 VNIC_CFG_REQ_ENABLES_MRU); 5013 } else if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG) { 5014 req.rss_rule = 5015 cpu_to_le16(bp->vnic_info[0].fw_rss_cos_lb_ctx[0]); 5016 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE | 5017 VNIC_CFG_REQ_ENABLES_MRU); 5018 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE); 5019 } else { 5020 req.rss_rule = cpu_to_le16(0xffff); 5021 } 5022 5023 if (BNXT_CHIP_TYPE_NITRO_A0(bp) && 5024 (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID)) { 5025 req.cos_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[1]); 5026 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_COS_RULE); 5027 } else { 5028 req.cos_rule = cpu_to_le16(0xffff); 5029 } 5030 5031 if (vnic->flags & BNXT_VNIC_RSS_FLAG) 5032 ring = 0; 5033 else if (vnic->flags & BNXT_VNIC_RFS_FLAG) 5034 ring = vnic_id - 1; 5035 else if ((vnic_id == 1) && BNXT_CHIP_TYPE_NITRO_A0(bp)) 5036 ring = bp->rx_nr_rings - 1; 5037 5038 grp_idx = bp->rx_ring[ring].bnapi->index; 5039 req.dflt_ring_grp = cpu_to_le16(bp->grp_info[grp_idx].fw_grp_id); 5040 req.lb_rule = cpu_to_le16(0xffff); 5041 vnic_mru: 5042 req.mru = cpu_to_le16(bp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + 5043 VLAN_HLEN); 5044 5045 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id); 5046 #ifdef CONFIG_BNXT_SRIOV 5047 if (BNXT_VF(bp)) 5048 def_vlan = bp->vf.vlan; 5049 #endif 5050 if ((bp->flags & BNXT_FLAG_STRIP_VLAN) || def_vlan) 5051 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE); 5052 if (!vnic_id && bnxt_ulp_registered(bp->edev, BNXT_ROCE_ULP)) 5053 req.flags |= cpu_to_le32(bnxt_get_roce_vnic_mode(bp)); 5054 5055 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5056 } 5057 5058 static void bnxt_hwrm_vnic_free_one(struct bnxt *bp, u16 vnic_id) 5059 { 5060 if (bp->vnic_info[vnic_id].fw_vnic_id != INVALID_HW_RING_ID) { 5061 struct hwrm_vnic_free_input req = {0}; 5062 5063 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_FREE, -1, -1); 5064 req.vnic_id = 5065 cpu_to_le32(bp->vnic_info[vnic_id].fw_vnic_id); 5066 5067 hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5068 bp->vnic_info[vnic_id].fw_vnic_id = INVALID_HW_RING_ID; 5069 } 5070 } 5071 5072 static void bnxt_hwrm_vnic_free(struct bnxt *bp) 5073 { 5074 u16 i; 5075 5076 for (i = 0; i < bp->nr_vnics; i++) 5077 bnxt_hwrm_vnic_free_one(bp, i); 5078 } 5079 5080 static int bnxt_hwrm_vnic_alloc(struct bnxt *bp, u16 vnic_id, 5081 unsigned int start_rx_ring_idx, 5082 unsigned int nr_rings) 5083 { 5084 int rc = 0; 5085 unsigned int i, j, grp_idx, end_idx = start_rx_ring_idx + nr_rings; 5086 struct hwrm_vnic_alloc_input req = {0}; 5087 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr; 5088 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 5089 5090 if (bp->flags & BNXT_FLAG_CHIP_P5) 5091 goto vnic_no_ring_grps; 5092 5093 /* map ring groups to this vnic */ 5094 for (i = start_rx_ring_idx, j = 0; i < end_idx; i++, j++) { 5095 grp_idx = bp->rx_ring[i].bnapi->index; 5096 if (bp->grp_info[grp_idx].fw_grp_id == INVALID_HW_RING_ID) { 5097 netdev_err(bp->dev, "Not enough ring groups avail:%x req:%x\n", 5098 j, nr_rings); 5099 break; 5100 } 5101 vnic->fw_grp_ids[j] = bp->grp_info[grp_idx].fw_grp_id; 5102 } 5103 5104 vnic_no_ring_grps: 5105 for (i = 0; i < BNXT_MAX_CTX_PER_VNIC; i++) 5106 vnic->fw_rss_cos_lb_ctx[i] = INVALID_HW_RING_ID; 5107 if (vnic_id == 0) 5108 req.flags = cpu_to_le32(VNIC_ALLOC_REQ_FLAGS_DEFAULT); 5109 5110 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_ALLOC, -1, -1); 5111 5112 mutex_lock(&bp->hwrm_cmd_lock); 5113 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5114 if (!rc) 5115 vnic->fw_vnic_id = le32_to_cpu(resp->vnic_id); 5116 mutex_unlock(&bp->hwrm_cmd_lock); 5117 return rc; 5118 } 5119 5120 static int bnxt_hwrm_vnic_qcaps(struct bnxt *bp) 5121 { 5122 struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr; 5123 struct hwrm_vnic_qcaps_input req = {0}; 5124 int rc; 5125 5126 bp->hw_ring_stats_size = sizeof(struct ctx_hw_stats); 5127 bp->flags &= ~(BNXT_FLAG_NEW_RSS_CAP | BNXT_FLAG_ROCE_MIRROR_CAP); 5128 if (bp->hwrm_spec_code < 0x10600) 5129 return 0; 5130 5131 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_QCAPS, -1, -1); 5132 mutex_lock(&bp->hwrm_cmd_lock); 5133 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5134 if (!rc) { 5135 u32 flags = le32_to_cpu(resp->flags); 5136 5137 if (!(bp->flags & BNXT_FLAG_CHIP_P5) && 5138 (flags & VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP)) 5139 bp->flags |= BNXT_FLAG_NEW_RSS_CAP; 5140 if (flags & 5141 VNIC_QCAPS_RESP_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP) 5142 bp->flags |= BNXT_FLAG_ROCE_MIRROR_CAP; 5143 bp->max_tpa_v2 = le16_to_cpu(resp->max_aggs_supported); 5144 if (bp->max_tpa_v2) 5145 bp->hw_ring_stats_size = 5146 sizeof(struct ctx_hw_stats_ext); 5147 } 5148 mutex_unlock(&bp->hwrm_cmd_lock); 5149 return rc; 5150 } 5151 5152 static int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp) 5153 { 5154 u16 i; 5155 u32 rc = 0; 5156 5157 if (bp->flags & BNXT_FLAG_CHIP_P5) 5158 return 0; 5159 5160 mutex_lock(&bp->hwrm_cmd_lock); 5161 for (i = 0; i < bp->rx_nr_rings; i++) { 5162 struct hwrm_ring_grp_alloc_input req = {0}; 5163 struct hwrm_ring_grp_alloc_output *resp = 5164 bp->hwrm_cmd_resp_addr; 5165 unsigned int grp_idx = bp->rx_ring[i].bnapi->index; 5166 5167 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_ALLOC, -1, -1); 5168 5169 req.cr = cpu_to_le16(bp->grp_info[grp_idx].cp_fw_ring_id); 5170 req.rr = cpu_to_le16(bp->grp_info[grp_idx].rx_fw_ring_id); 5171 req.ar = cpu_to_le16(bp->grp_info[grp_idx].agg_fw_ring_id); 5172 req.sc = cpu_to_le16(bp->grp_info[grp_idx].fw_stats_ctx); 5173 5174 rc = _hwrm_send_message(bp, &req, sizeof(req), 5175 HWRM_CMD_TIMEOUT); 5176 if (rc) 5177 break; 5178 5179 bp->grp_info[grp_idx].fw_grp_id = 5180 le32_to_cpu(resp->ring_group_id); 5181 } 5182 mutex_unlock(&bp->hwrm_cmd_lock); 5183 return rc; 5184 } 5185 5186 static void bnxt_hwrm_ring_grp_free(struct bnxt *bp) 5187 { 5188 u16 i; 5189 struct hwrm_ring_grp_free_input req = {0}; 5190 5191 if (!bp->grp_info || (bp->flags & BNXT_FLAG_CHIP_P5)) 5192 return; 5193 5194 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_FREE, -1, -1); 5195 5196 mutex_lock(&bp->hwrm_cmd_lock); 5197 for (i = 0; i < bp->cp_nr_rings; i++) { 5198 if (bp->grp_info[i].fw_grp_id == INVALID_HW_RING_ID) 5199 continue; 5200 req.ring_group_id = 5201 cpu_to_le32(bp->grp_info[i].fw_grp_id); 5202 5203 _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5204 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID; 5205 } 5206 mutex_unlock(&bp->hwrm_cmd_lock); 5207 } 5208 5209 static int hwrm_ring_alloc_send_msg(struct bnxt *bp, 5210 struct bnxt_ring_struct *ring, 5211 u32 ring_type, u32 map_index) 5212 { 5213 int rc = 0, err = 0; 5214 struct hwrm_ring_alloc_input req = {0}; 5215 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr; 5216 struct bnxt_ring_mem_info *rmem = &ring->ring_mem; 5217 struct bnxt_ring_grp_info *grp_info; 5218 u16 ring_id; 5219 5220 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_ALLOC, -1, -1); 5221 5222 req.enables = 0; 5223 if (rmem->nr_pages > 1) { 5224 req.page_tbl_addr = cpu_to_le64(rmem->pg_tbl_map); 5225 /* Page size is in log2 units */ 5226 req.page_size = BNXT_PAGE_SHIFT; 5227 req.page_tbl_depth = 1; 5228 } else { 5229 req.page_tbl_addr = cpu_to_le64(rmem->dma_arr[0]); 5230 } 5231 req.fbo = 0; 5232 /* Association of ring index with doorbell index and MSIX number */ 5233 req.logical_id = cpu_to_le16(map_index); 5234 5235 switch (ring_type) { 5236 case HWRM_RING_ALLOC_TX: { 5237 struct bnxt_tx_ring_info *txr; 5238 5239 txr = container_of(ring, struct bnxt_tx_ring_info, 5240 tx_ring_struct); 5241 req.ring_type = RING_ALLOC_REQ_RING_TYPE_TX; 5242 /* Association of transmit ring with completion ring */ 5243 grp_info = &bp->grp_info[ring->grp_idx]; 5244 req.cmpl_ring_id = cpu_to_le16(bnxt_cp_ring_for_tx(bp, txr)); 5245 req.length = cpu_to_le32(bp->tx_ring_mask + 1); 5246 req.stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx); 5247 req.queue_id = cpu_to_le16(ring->queue_id); 5248 break; 5249 } 5250 case HWRM_RING_ALLOC_RX: 5251 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX; 5252 req.length = cpu_to_le32(bp->rx_ring_mask + 1); 5253 if (bp->flags & BNXT_FLAG_CHIP_P5) { 5254 u16 flags = 0; 5255 5256 /* Association of rx ring with stats context */ 5257 grp_info = &bp->grp_info[ring->grp_idx]; 5258 req.rx_buf_size = cpu_to_le16(bp->rx_buf_use_size); 5259 req.stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx); 5260 req.enables |= cpu_to_le32( 5261 RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID); 5262 if (NET_IP_ALIGN == 2) 5263 flags = RING_ALLOC_REQ_FLAGS_RX_SOP_PAD; 5264 req.flags = cpu_to_le16(flags); 5265 } 5266 break; 5267 case HWRM_RING_ALLOC_AGG: 5268 if (bp->flags & BNXT_FLAG_CHIP_P5) { 5269 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX_AGG; 5270 /* Association of agg ring with rx ring */ 5271 grp_info = &bp->grp_info[ring->grp_idx]; 5272 req.rx_ring_id = cpu_to_le16(grp_info->rx_fw_ring_id); 5273 req.rx_buf_size = cpu_to_le16(BNXT_RX_PAGE_SIZE); 5274 req.stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx); 5275 req.enables |= cpu_to_le32( 5276 RING_ALLOC_REQ_ENABLES_RX_RING_ID_VALID | 5277 RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID); 5278 } else { 5279 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX; 5280 } 5281 req.length = cpu_to_le32(bp->rx_agg_ring_mask + 1); 5282 break; 5283 case HWRM_RING_ALLOC_CMPL: 5284 req.ring_type = RING_ALLOC_REQ_RING_TYPE_L2_CMPL; 5285 req.length = cpu_to_le32(bp->cp_ring_mask + 1); 5286 if (bp->flags & BNXT_FLAG_CHIP_P5) { 5287 /* Association of cp ring with nq */ 5288 grp_info = &bp->grp_info[map_index]; 5289 req.nq_ring_id = cpu_to_le16(grp_info->cp_fw_ring_id); 5290 req.cq_handle = cpu_to_le64(ring->handle); 5291 req.enables |= cpu_to_le32( 5292 RING_ALLOC_REQ_ENABLES_NQ_RING_ID_VALID); 5293 } else if (bp->flags & BNXT_FLAG_USING_MSIX) { 5294 req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX; 5295 } 5296 break; 5297 case HWRM_RING_ALLOC_NQ: 5298 req.ring_type = RING_ALLOC_REQ_RING_TYPE_NQ; 5299 req.length = cpu_to_le32(bp->cp_ring_mask + 1); 5300 if (bp->flags & BNXT_FLAG_USING_MSIX) 5301 req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX; 5302 break; 5303 default: 5304 netdev_err(bp->dev, "hwrm alloc invalid ring type %d\n", 5305 ring_type); 5306 return -1; 5307 } 5308 5309 mutex_lock(&bp->hwrm_cmd_lock); 5310 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5311 err = le16_to_cpu(resp->error_code); 5312 ring_id = le16_to_cpu(resp->ring_id); 5313 mutex_unlock(&bp->hwrm_cmd_lock); 5314 5315 if (rc || err) { 5316 netdev_err(bp->dev, "hwrm_ring_alloc type %d failed. rc:%x err:%x\n", 5317 ring_type, rc, err); 5318 return -EIO; 5319 } 5320 ring->fw_ring_id = ring_id; 5321 return rc; 5322 } 5323 5324 static int bnxt_hwrm_set_async_event_cr(struct bnxt *bp, int idx) 5325 { 5326 int rc; 5327 5328 if (BNXT_PF(bp)) { 5329 struct hwrm_func_cfg_input req = {0}; 5330 5331 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1); 5332 req.fid = cpu_to_le16(0xffff); 5333 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR); 5334 req.async_event_cr = cpu_to_le16(idx); 5335 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5336 } else { 5337 struct hwrm_func_vf_cfg_input req = {0}; 5338 5339 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_VF_CFG, -1, -1); 5340 req.enables = 5341 cpu_to_le32(FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR); 5342 req.async_event_cr = cpu_to_le16(idx); 5343 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5344 } 5345 return rc; 5346 } 5347 5348 static void bnxt_set_db(struct bnxt *bp, struct bnxt_db_info *db, u32 ring_type, 5349 u32 map_idx, u32 xid) 5350 { 5351 if (bp->flags & BNXT_FLAG_CHIP_P5) { 5352 if (BNXT_PF(bp)) 5353 db->doorbell = bp->bar1 + 0x10000; 5354 else 5355 db->doorbell = bp->bar1 + 0x4000; 5356 switch (ring_type) { 5357 case HWRM_RING_ALLOC_TX: 5358 db->db_key64 = DBR_PATH_L2 | DBR_TYPE_SQ; 5359 break; 5360 case HWRM_RING_ALLOC_RX: 5361 case HWRM_RING_ALLOC_AGG: 5362 db->db_key64 = DBR_PATH_L2 | DBR_TYPE_SRQ; 5363 break; 5364 case HWRM_RING_ALLOC_CMPL: 5365 db->db_key64 = DBR_PATH_L2; 5366 break; 5367 case HWRM_RING_ALLOC_NQ: 5368 db->db_key64 = DBR_PATH_L2; 5369 break; 5370 } 5371 db->db_key64 |= (u64)xid << DBR_XID_SFT; 5372 } else { 5373 db->doorbell = bp->bar1 + map_idx * 0x80; 5374 switch (ring_type) { 5375 case HWRM_RING_ALLOC_TX: 5376 db->db_key32 = DB_KEY_TX; 5377 break; 5378 case HWRM_RING_ALLOC_RX: 5379 case HWRM_RING_ALLOC_AGG: 5380 db->db_key32 = DB_KEY_RX; 5381 break; 5382 case HWRM_RING_ALLOC_CMPL: 5383 db->db_key32 = DB_KEY_CP; 5384 break; 5385 } 5386 } 5387 } 5388 5389 static int bnxt_hwrm_ring_alloc(struct bnxt *bp) 5390 { 5391 bool agg_rings = !!(bp->flags & BNXT_FLAG_AGG_RINGS); 5392 int i, rc = 0; 5393 u32 type; 5394 5395 if (bp->flags & BNXT_FLAG_CHIP_P5) 5396 type = HWRM_RING_ALLOC_NQ; 5397 else 5398 type = HWRM_RING_ALLOC_CMPL; 5399 for (i = 0; i < bp->cp_nr_rings; i++) { 5400 struct bnxt_napi *bnapi = bp->bnapi[i]; 5401 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 5402 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct; 5403 u32 map_idx = ring->map_idx; 5404 unsigned int vector; 5405 5406 vector = bp->irq_tbl[map_idx].vector; 5407 disable_irq_nosync(vector); 5408 rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx); 5409 if (rc) { 5410 enable_irq(vector); 5411 goto err_out; 5412 } 5413 bnxt_set_db(bp, &cpr->cp_db, type, map_idx, ring->fw_ring_id); 5414 bnxt_db_nq(bp, &cpr->cp_db, cpr->cp_raw_cons); 5415 enable_irq(vector); 5416 bp->grp_info[i].cp_fw_ring_id = ring->fw_ring_id; 5417 5418 if (!i) { 5419 rc = bnxt_hwrm_set_async_event_cr(bp, ring->fw_ring_id); 5420 if (rc) 5421 netdev_warn(bp->dev, "Failed to set async event completion ring.\n"); 5422 } 5423 } 5424 5425 type = HWRM_RING_ALLOC_TX; 5426 for (i = 0; i < bp->tx_nr_rings; i++) { 5427 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; 5428 struct bnxt_ring_struct *ring; 5429 u32 map_idx; 5430 5431 if (bp->flags & BNXT_FLAG_CHIP_P5) { 5432 struct bnxt_napi *bnapi = txr->bnapi; 5433 struct bnxt_cp_ring_info *cpr, *cpr2; 5434 u32 type2 = HWRM_RING_ALLOC_CMPL; 5435 5436 cpr = &bnapi->cp_ring; 5437 cpr2 = cpr->cp_ring_arr[BNXT_TX_HDL]; 5438 ring = &cpr2->cp_ring_struct; 5439 ring->handle = BNXT_TX_HDL; 5440 map_idx = bnapi->index; 5441 rc = hwrm_ring_alloc_send_msg(bp, ring, type2, map_idx); 5442 if (rc) 5443 goto err_out; 5444 bnxt_set_db(bp, &cpr2->cp_db, type2, map_idx, 5445 ring->fw_ring_id); 5446 bnxt_db_cq(bp, &cpr2->cp_db, cpr2->cp_raw_cons); 5447 } 5448 ring = &txr->tx_ring_struct; 5449 map_idx = i; 5450 rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx); 5451 if (rc) 5452 goto err_out; 5453 bnxt_set_db(bp, &txr->tx_db, type, map_idx, ring->fw_ring_id); 5454 } 5455 5456 type = HWRM_RING_ALLOC_RX; 5457 for (i = 0; i < bp->rx_nr_rings; i++) { 5458 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 5459 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct; 5460 struct bnxt_napi *bnapi = rxr->bnapi; 5461 u32 map_idx = bnapi->index; 5462 5463 rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx); 5464 if (rc) 5465 goto err_out; 5466 bnxt_set_db(bp, &rxr->rx_db, type, map_idx, ring->fw_ring_id); 5467 /* If we have agg rings, post agg buffers first. */ 5468 if (!agg_rings) 5469 bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod); 5470 bp->grp_info[map_idx].rx_fw_ring_id = ring->fw_ring_id; 5471 if (bp->flags & BNXT_FLAG_CHIP_P5) { 5472 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 5473 u32 type2 = HWRM_RING_ALLOC_CMPL; 5474 struct bnxt_cp_ring_info *cpr2; 5475 5476 cpr2 = cpr->cp_ring_arr[BNXT_RX_HDL]; 5477 ring = &cpr2->cp_ring_struct; 5478 ring->handle = BNXT_RX_HDL; 5479 rc = hwrm_ring_alloc_send_msg(bp, ring, type2, map_idx); 5480 if (rc) 5481 goto err_out; 5482 bnxt_set_db(bp, &cpr2->cp_db, type2, map_idx, 5483 ring->fw_ring_id); 5484 bnxt_db_cq(bp, &cpr2->cp_db, cpr2->cp_raw_cons); 5485 } 5486 } 5487 5488 if (agg_rings) { 5489 type = HWRM_RING_ALLOC_AGG; 5490 for (i = 0; i < bp->rx_nr_rings; i++) { 5491 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 5492 struct bnxt_ring_struct *ring = 5493 &rxr->rx_agg_ring_struct; 5494 u32 grp_idx = ring->grp_idx; 5495 u32 map_idx = grp_idx + bp->rx_nr_rings; 5496 5497 rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx); 5498 if (rc) 5499 goto err_out; 5500 5501 bnxt_set_db(bp, &rxr->rx_agg_db, type, map_idx, 5502 ring->fw_ring_id); 5503 bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod); 5504 bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod); 5505 bp->grp_info[grp_idx].agg_fw_ring_id = ring->fw_ring_id; 5506 } 5507 } 5508 err_out: 5509 return rc; 5510 } 5511 5512 static int hwrm_ring_free_send_msg(struct bnxt *bp, 5513 struct bnxt_ring_struct *ring, 5514 u32 ring_type, int cmpl_ring_id) 5515 { 5516 int rc; 5517 struct hwrm_ring_free_input req = {0}; 5518 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr; 5519 u16 error_code; 5520 5521 if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state)) 5522 return 0; 5523 5524 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_FREE, cmpl_ring_id, -1); 5525 req.ring_type = ring_type; 5526 req.ring_id = cpu_to_le16(ring->fw_ring_id); 5527 5528 mutex_lock(&bp->hwrm_cmd_lock); 5529 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5530 error_code = le16_to_cpu(resp->error_code); 5531 mutex_unlock(&bp->hwrm_cmd_lock); 5532 5533 if (rc || error_code) { 5534 netdev_err(bp->dev, "hwrm_ring_free type %d failed. rc:%x err:%x\n", 5535 ring_type, rc, error_code); 5536 return -EIO; 5537 } 5538 return 0; 5539 } 5540 5541 static void bnxt_hwrm_ring_free(struct bnxt *bp, bool close_path) 5542 { 5543 u32 type; 5544 int i; 5545 5546 if (!bp->bnapi) 5547 return; 5548 5549 for (i = 0; i < bp->tx_nr_rings; i++) { 5550 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; 5551 struct bnxt_ring_struct *ring = &txr->tx_ring_struct; 5552 5553 if (ring->fw_ring_id != INVALID_HW_RING_ID) { 5554 u32 cmpl_ring_id = bnxt_cp_ring_for_tx(bp, txr); 5555 5556 hwrm_ring_free_send_msg(bp, ring, 5557 RING_FREE_REQ_RING_TYPE_TX, 5558 close_path ? cmpl_ring_id : 5559 INVALID_HW_RING_ID); 5560 ring->fw_ring_id = INVALID_HW_RING_ID; 5561 } 5562 } 5563 5564 for (i = 0; i < bp->rx_nr_rings; i++) { 5565 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 5566 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct; 5567 u32 grp_idx = rxr->bnapi->index; 5568 5569 if (ring->fw_ring_id != INVALID_HW_RING_ID) { 5570 u32 cmpl_ring_id = bnxt_cp_ring_for_rx(bp, rxr); 5571 5572 hwrm_ring_free_send_msg(bp, ring, 5573 RING_FREE_REQ_RING_TYPE_RX, 5574 close_path ? cmpl_ring_id : 5575 INVALID_HW_RING_ID); 5576 ring->fw_ring_id = INVALID_HW_RING_ID; 5577 bp->grp_info[grp_idx].rx_fw_ring_id = 5578 INVALID_HW_RING_ID; 5579 } 5580 } 5581 5582 if (bp->flags & BNXT_FLAG_CHIP_P5) 5583 type = RING_FREE_REQ_RING_TYPE_RX_AGG; 5584 else 5585 type = RING_FREE_REQ_RING_TYPE_RX; 5586 for (i = 0; i < bp->rx_nr_rings; i++) { 5587 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 5588 struct bnxt_ring_struct *ring = &rxr->rx_agg_ring_struct; 5589 u32 grp_idx = rxr->bnapi->index; 5590 5591 if (ring->fw_ring_id != INVALID_HW_RING_ID) { 5592 u32 cmpl_ring_id = bnxt_cp_ring_for_rx(bp, rxr); 5593 5594 hwrm_ring_free_send_msg(bp, ring, type, 5595 close_path ? cmpl_ring_id : 5596 INVALID_HW_RING_ID); 5597 ring->fw_ring_id = INVALID_HW_RING_ID; 5598 bp->grp_info[grp_idx].agg_fw_ring_id = 5599 INVALID_HW_RING_ID; 5600 } 5601 } 5602 5603 /* The completion rings are about to be freed. After that the 5604 * IRQ doorbell will not work anymore. So we need to disable 5605 * IRQ here. 5606 */ 5607 bnxt_disable_int_sync(bp); 5608 5609 if (bp->flags & BNXT_FLAG_CHIP_P5) 5610 type = RING_FREE_REQ_RING_TYPE_NQ; 5611 else 5612 type = RING_FREE_REQ_RING_TYPE_L2_CMPL; 5613 for (i = 0; i < bp->cp_nr_rings; i++) { 5614 struct bnxt_napi *bnapi = bp->bnapi[i]; 5615 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 5616 struct bnxt_ring_struct *ring; 5617 int j; 5618 5619 for (j = 0; j < 2; j++) { 5620 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j]; 5621 5622 if (cpr2) { 5623 ring = &cpr2->cp_ring_struct; 5624 if (ring->fw_ring_id == INVALID_HW_RING_ID) 5625 continue; 5626 hwrm_ring_free_send_msg(bp, ring, 5627 RING_FREE_REQ_RING_TYPE_L2_CMPL, 5628 INVALID_HW_RING_ID); 5629 ring->fw_ring_id = INVALID_HW_RING_ID; 5630 } 5631 } 5632 ring = &cpr->cp_ring_struct; 5633 if (ring->fw_ring_id != INVALID_HW_RING_ID) { 5634 hwrm_ring_free_send_msg(bp, ring, type, 5635 INVALID_HW_RING_ID); 5636 ring->fw_ring_id = INVALID_HW_RING_ID; 5637 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID; 5638 } 5639 } 5640 } 5641 5642 static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max, 5643 bool shared); 5644 5645 static int bnxt_hwrm_get_rings(struct bnxt *bp) 5646 { 5647 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr; 5648 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 5649 struct hwrm_func_qcfg_input req = {0}; 5650 int rc; 5651 5652 if (bp->hwrm_spec_code < 0x10601) 5653 return 0; 5654 5655 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1); 5656 req.fid = cpu_to_le16(0xffff); 5657 mutex_lock(&bp->hwrm_cmd_lock); 5658 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5659 if (rc) { 5660 mutex_unlock(&bp->hwrm_cmd_lock); 5661 return rc; 5662 } 5663 5664 hw_resc->resv_tx_rings = le16_to_cpu(resp->alloc_tx_rings); 5665 if (BNXT_NEW_RM(bp)) { 5666 u16 cp, stats; 5667 5668 hw_resc->resv_rx_rings = le16_to_cpu(resp->alloc_rx_rings); 5669 hw_resc->resv_hw_ring_grps = 5670 le32_to_cpu(resp->alloc_hw_ring_grps); 5671 hw_resc->resv_vnics = le16_to_cpu(resp->alloc_vnics); 5672 cp = le16_to_cpu(resp->alloc_cmpl_rings); 5673 stats = le16_to_cpu(resp->alloc_stat_ctx); 5674 hw_resc->resv_irqs = cp; 5675 if (bp->flags & BNXT_FLAG_CHIP_P5) { 5676 int rx = hw_resc->resv_rx_rings; 5677 int tx = hw_resc->resv_tx_rings; 5678 5679 if (bp->flags & BNXT_FLAG_AGG_RINGS) 5680 rx >>= 1; 5681 if (cp < (rx + tx)) { 5682 bnxt_trim_rings(bp, &rx, &tx, cp, false); 5683 if (bp->flags & BNXT_FLAG_AGG_RINGS) 5684 rx <<= 1; 5685 hw_resc->resv_rx_rings = rx; 5686 hw_resc->resv_tx_rings = tx; 5687 } 5688 hw_resc->resv_irqs = le16_to_cpu(resp->alloc_msix); 5689 hw_resc->resv_hw_ring_grps = rx; 5690 } 5691 hw_resc->resv_cp_rings = cp; 5692 hw_resc->resv_stat_ctxs = stats; 5693 } 5694 mutex_unlock(&bp->hwrm_cmd_lock); 5695 return 0; 5696 } 5697 5698 /* Caller must hold bp->hwrm_cmd_lock */ 5699 int __bnxt_hwrm_get_tx_rings(struct bnxt *bp, u16 fid, int *tx_rings) 5700 { 5701 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr; 5702 struct hwrm_func_qcfg_input req = {0}; 5703 int rc; 5704 5705 if (bp->hwrm_spec_code < 0x10601) 5706 return 0; 5707 5708 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1); 5709 req.fid = cpu_to_le16(fid); 5710 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5711 if (!rc) 5712 *tx_rings = le16_to_cpu(resp->alloc_tx_rings); 5713 5714 return rc; 5715 } 5716 5717 static bool bnxt_rfs_supported(struct bnxt *bp); 5718 5719 static void 5720 __bnxt_hwrm_reserve_pf_rings(struct bnxt *bp, struct hwrm_func_cfg_input *req, 5721 int tx_rings, int rx_rings, int ring_grps, 5722 int cp_rings, int stats, int vnics) 5723 { 5724 u32 enables = 0; 5725 5726 bnxt_hwrm_cmd_hdr_init(bp, req, HWRM_FUNC_CFG, -1, -1); 5727 req->fid = cpu_to_le16(0xffff); 5728 enables |= tx_rings ? FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS : 0; 5729 req->num_tx_rings = cpu_to_le16(tx_rings); 5730 if (BNXT_NEW_RM(bp)) { 5731 enables |= rx_rings ? FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS : 0; 5732 enables |= stats ? FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0; 5733 if (bp->flags & BNXT_FLAG_CHIP_P5) { 5734 enables |= cp_rings ? FUNC_CFG_REQ_ENABLES_NUM_MSIX : 0; 5735 enables |= tx_rings + ring_grps ? 5736 FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0; 5737 enables |= rx_rings ? 5738 FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0; 5739 } else { 5740 enables |= cp_rings ? 5741 FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0; 5742 enables |= ring_grps ? 5743 FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS | 5744 FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0; 5745 } 5746 enables |= vnics ? FUNC_CFG_REQ_ENABLES_NUM_VNICS : 0; 5747 5748 req->num_rx_rings = cpu_to_le16(rx_rings); 5749 if (bp->flags & BNXT_FLAG_CHIP_P5) { 5750 req->num_cmpl_rings = cpu_to_le16(tx_rings + ring_grps); 5751 req->num_msix = cpu_to_le16(cp_rings); 5752 req->num_rsscos_ctxs = 5753 cpu_to_le16(DIV_ROUND_UP(ring_grps, 64)); 5754 } else { 5755 req->num_cmpl_rings = cpu_to_le16(cp_rings); 5756 req->num_hw_ring_grps = cpu_to_le16(ring_grps); 5757 req->num_rsscos_ctxs = cpu_to_le16(1); 5758 if (!(bp->flags & BNXT_FLAG_NEW_RSS_CAP) && 5759 bnxt_rfs_supported(bp)) 5760 req->num_rsscos_ctxs = 5761 cpu_to_le16(ring_grps + 1); 5762 } 5763 req->num_stat_ctxs = cpu_to_le16(stats); 5764 req->num_vnics = cpu_to_le16(vnics); 5765 } 5766 req->enables = cpu_to_le32(enables); 5767 } 5768 5769 static void 5770 __bnxt_hwrm_reserve_vf_rings(struct bnxt *bp, 5771 struct hwrm_func_vf_cfg_input *req, int tx_rings, 5772 int rx_rings, int ring_grps, int cp_rings, 5773 int stats, int vnics) 5774 { 5775 u32 enables = 0; 5776 5777 bnxt_hwrm_cmd_hdr_init(bp, req, HWRM_FUNC_VF_CFG, -1, -1); 5778 enables |= tx_rings ? FUNC_VF_CFG_REQ_ENABLES_NUM_TX_RINGS : 0; 5779 enables |= rx_rings ? FUNC_VF_CFG_REQ_ENABLES_NUM_RX_RINGS | 5780 FUNC_VF_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0; 5781 enables |= stats ? FUNC_VF_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0; 5782 if (bp->flags & BNXT_FLAG_CHIP_P5) { 5783 enables |= tx_rings + ring_grps ? 5784 FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0; 5785 } else { 5786 enables |= cp_rings ? 5787 FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0; 5788 enables |= ring_grps ? 5789 FUNC_VF_CFG_REQ_ENABLES_NUM_HW_RING_GRPS : 0; 5790 } 5791 enables |= vnics ? FUNC_VF_CFG_REQ_ENABLES_NUM_VNICS : 0; 5792 enables |= FUNC_VF_CFG_REQ_ENABLES_NUM_L2_CTXS; 5793 5794 req->num_l2_ctxs = cpu_to_le16(BNXT_VF_MAX_L2_CTX); 5795 req->num_tx_rings = cpu_to_le16(tx_rings); 5796 req->num_rx_rings = cpu_to_le16(rx_rings); 5797 if (bp->flags & BNXT_FLAG_CHIP_P5) { 5798 req->num_cmpl_rings = cpu_to_le16(tx_rings + ring_grps); 5799 req->num_rsscos_ctxs = cpu_to_le16(DIV_ROUND_UP(ring_grps, 64)); 5800 } else { 5801 req->num_cmpl_rings = cpu_to_le16(cp_rings); 5802 req->num_hw_ring_grps = cpu_to_le16(ring_grps); 5803 req->num_rsscos_ctxs = cpu_to_le16(BNXT_VF_MAX_RSS_CTX); 5804 } 5805 req->num_stat_ctxs = cpu_to_le16(stats); 5806 req->num_vnics = cpu_to_le16(vnics); 5807 5808 req->enables = cpu_to_le32(enables); 5809 } 5810 5811 static int 5812 bnxt_hwrm_reserve_pf_rings(struct bnxt *bp, int tx_rings, int rx_rings, 5813 int ring_grps, int cp_rings, int stats, int vnics) 5814 { 5815 struct hwrm_func_cfg_input req = {0}; 5816 int rc; 5817 5818 __bnxt_hwrm_reserve_pf_rings(bp, &req, tx_rings, rx_rings, ring_grps, 5819 cp_rings, stats, vnics); 5820 if (!req.enables) 5821 return 0; 5822 5823 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5824 if (rc) 5825 return rc; 5826 5827 if (bp->hwrm_spec_code < 0x10601) 5828 bp->hw_resc.resv_tx_rings = tx_rings; 5829 5830 return bnxt_hwrm_get_rings(bp); 5831 } 5832 5833 static int 5834 bnxt_hwrm_reserve_vf_rings(struct bnxt *bp, int tx_rings, int rx_rings, 5835 int ring_grps, int cp_rings, int stats, int vnics) 5836 { 5837 struct hwrm_func_vf_cfg_input req = {0}; 5838 int rc; 5839 5840 if (!BNXT_NEW_RM(bp)) { 5841 bp->hw_resc.resv_tx_rings = tx_rings; 5842 return 0; 5843 } 5844 5845 __bnxt_hwrm_reserve_vf_rings(bp, &req, tx_rings, rx_rings, ring_grps, 5846 cp_rings, stats, vnics); 5847 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5848 if (rc) 5849 return rc; 5850 5851 return bnxt_hwrm_get_rings(bp); 5852 } 5853 5854 static int bnxt_hwrm_reserve_rings(struct bnxt *bp, int tx, int rx, int grp, 5855 int cp, int stat, int vnic) 5856 { 5857 if (BNXT_PF(bp)) 5858 return bnxt_hwrm_reserve_pf_rings(bp, tx, rx, grp, cp, stat, 5859 vnic); 5860 else 5861 return bnxt_hwrm_reserve_vf_rings(bp, tx, rx, grp, cp, stat, 5862 vnic); 5863 } 5864 5865 int bnxt_nq_rings_in_use(struct bnxt *bp) 5866 { 5867 int cp = bp->cp_nr_rings; 5868 int ulp_msix, ulp_base; 5869 5870 ulp_msix = bnxt_get_ulp_msix_num(bp); 5871 if (ulp_msix) { 5872 ulp_base = bnxt_get_ulp_msix_base(bp); 5873 cp += ulp_msix; 5874 if ((ulp_base + ulp_msix) > cp) 5875 cp = ulp_base + ulp_msix; 5876 } 5877 return cp; 5878 } 5879 5880 static int bnxt_cp_rings_in_use(struct bnxt *bp) 5881 { 5882 int cp; 5883 5884 if (!(bp->flags & BNXT_FLAG_CHIP_P5)) 5885 return bnxt_nq_rings_in_use(bp); 5886 5887 cp = bp->tx_nr_rings + bp->rx_nr_rings; 5888 return cp; 5889 } 5890 5891 static int bnxt_get_func_stat_ctxs(struct bnxt *bp) 5892 { 5893 int ulp_stat = bnxt_get_ulp_stat_ctxs(bp); 5894 int cp = bp->cp_nr_rings; 5895 5896 if (!ulp_stat) 5897 return cp; 5898 5899 if (bnxt_nq_rings_in_use(bp) > cp + bnxt_get_ulp_msix_num(bp)) 5900 return bnxt_get_ulp_msix_base(bp) + ulp_stat; 5901 5902 return cp + ulp_stat; 5903 } 5904 5905 static bool bnxt_need_reserve_rings(struct bnxt *bp) 5906 { 5907 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 5908 int cp = bnxt_cp_rings_in_use(bp); 5909 int nq = bnxt_nq_rings_in_use(bp); 5910 int rx = bp->rx_nr_rings, stat; 5911 int vnic = 1, grp = rx; 5912 5913 if (bp->hwrm_spec_code < 0x10601) 5914 return false; 5915 5916 if (hw_resc->resv_tx_rings != bp->tx_nr_rings) 5917 return true; 5918 5919 if ((bp->flags & BNXT_FLAG_RFS) && !(bp->flags & BNXT_FLAG_CHIP_P5)) 5920 vnic = rx + 1; 5921 if (bp->flags & BNXT_FLAG_AGG_RINGS) 5922 rx <<= 1; 5923 stat = bnxt_get_func_stat_ctxs(bp); 5924 if (BNXT_NEW_RM(bp) && 5925 (hw_resc->resv_rx_rings != rx || hw_resc->resv_cp_rings != cp || 5926 hw_resc->resv_vnics != vnic || hw_resc->resv_stat_ctxs != stat || 5927 (hw_resc->resv_hw_ring_grps != grp && 5928 !(bp->flags & BNXT_FLAG_CHIP_P5)))) 5929 return true; 5930 if ((bp->flags & BNXT_FLAG_CHIP_P5) && BNXT_PF(bp) && 5931 hw_resc->resv_irqs != nq) 5932 return true; 5933 return false; 5934 } 5935 5936 static int __bnxt_reserve_rings(struct bnxt *bp) 5937 { 5938 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 5939 int cp = bnxt_nq_rings_in_use(bp); 5940 int tx = bp->tx_nr_rings; 5941 int rx = bp->rx_nr_rings; 5942 int grp, rx_rings, rc; 5943 int vnic = 1, stat; 5944 bool sh = false; 5945 5946 if (!bnxt_need_reserve_rings(bp)) 5947 return 0; 5948 5949 if (bp->flags & BNXT_FLAG_SHARED_RINGS) 5950 sh = true; 5951 if ((bp->flags & BNXT_FLAG_RFS) && !(bp->flags & BNXT_FLAG_CHIP_P5)) 5952 vnic = rx + 1; 5953 if (bp->flags & BNXT_FLAG_AGG_RINGS) 5954 rx <<= 1; 5955 grp = bp->rx_nr_rings; 5956 stat = bnxt_get_func_stat_ctxs(bp); 5957 5958 rc = bnxt_hwrm_reserve_rings(bp, tx, rx, grp, cp, stat, vnic); 5959 if (rc) 5960 return rc; 5961 5962 tx = hw_resc->resv_tx_rings; 5963 if (BNXT_NEW_RM(bp)) { 5964 rx = hw_resc->resv_rx_rings; 5965 cp = hw_resc->resv_irqs; 5966 grp = hw_resc->resv_hw_ring_grps; 5967 vnic = hw_resc->resv_vnics; 5968 stat = hw_resc->resv_stat_ctxs; 5969 } 5970 5971 rx_rings = rx; 5972 if (bp->flags & BNXT_FLAG_AGG_RINGS) { 5973 if (rx >= 2) { 5974 rx_rings = rx >> 1; 5975 } else { 5976 if (netif_running(bp->dev)) 5977 return -ENOMEM; 5978 5979 bp->flags &= ~BNXT_FLAG_AGG_RINGS; 5980 bp->flags |= BNXT_FLAG_NO_AGG_RINGS; 5981 bp->dev->hw_features &= ~NETIF_F_LRO; 5982 bp->dev->features &= ~NETIF_F_LRO; 5983 bnxt_set_ring_params(bp); 5984 } 5985 } 5986 rx_rings = min_t(int, rx_rings, grp); 5987 cp = min_t(int, cp, bp->cp_nr_rings); 5988 if (stat > bnxt_get_ulp_stat_ctxs(bp)) 5989 stat -= bnxt_get_ulp_stat_ctxs(bp); 5990 cp = min_t(int, cp, stat); 5991 rc = bnxt_trim_rings(bp, &rx_rings, &tx, cp, sh); 5992 if (bp->flags & BNXT_FLAG_AGG_RINGS) 5993 rx = rx_rings << 1; 5994 cp = sh ? max_t(int, tx, rx_rings) : tx + rx_rings; 5995 bp->tx_nr_rings = tx; 5996 bp->rx_nr_rings = rx_rings; 5997 bp->cp_nr_rings = cp; 5998 5999 if (!tx || !rx || !cp || !grp || !vnic || !stat) 6000 return -ENOMEM; 6001 6002 return rc; 6003 } 6004 6005 static int bnxt_hwrm_check_vf_rings(struct bnxt *bp, int tx_rings, int rx_rings, 6006 int ring_grps, int cp_rings, int stats, 6007 int vnics) 6008 { 6009 struct hwrm_func_vf_cfg_input req = {0}; 6010 u32 flags; 6011 6012 if (!BNXT_NEW_RM(bp)) 6013 return 0; 6014 6015 __bnxt_hwrm_reserve_vf_rings(bp, &req, tx_rings, rx_rings, ring_grps, 6016 cp_rings, stats, vnics); 6017 flags = FUNC_VF_CFG_REQ_FLAGS_TX_ASSETS_TEST | 6018 FUNC_VF_CFG_REQ_FLAGS_RX_ASSETS_TEST | 6019 FUNC_VF_CFG_REQ_FLAGS_CMPL_ASSETS_TEST | 6020 FUNC_VF_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST | 6021 FUNC_VF_CFG_REQ_FLAGS_VNIC_ASSETS_TEST | 6022 FUNC_VF_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST; 6023 if (!(bp->flags & BNXT_FLAG_CHIP_P5)) 6024 flags |= FUNC_VF_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST; 6025 6026 req.flags = cpu_to_le32(flags); 6027 return hwrm_send_message_silent(bp, &req, sizeof(req), 6028 HWRM_CMD_TIMEOUT); 6029 } 6030 6031 static int bnxt_hwrm_check_pf_rings(struct bnxt *bp, int tx_rings, int rx_rings, 6032 int ring_grps, int cp_rings, int stats, 6033 int vnics) 6034 { 6035 struct hwrm_func_cfg_input req = {0}; 6036 u32 flags; 6037 6038 __bnxt_hwrm_reserve_pf_rings(bp, &req, tx_rings, rx_rings, ring_grps, 6039 cp_rings, stats, vnics); 6040 flags = FUNC_CFG_REQ_FLAGS_TX_ASSETS_TEST; 6041 if (BNXT_NEW_RM(bp)) { 6042 flags |= FUNC_CFG_REQ_FLAGS_RX_ASSETS_TEST | 6043 FUNC_CFG_REQ_FLAGS_CMPL_ASSETS_TEST | 6044 FUNC_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST | 6045 FUNC_CFG_REQ_FLAGS_VNIC_ASSETS_TEST; 6046 if (bp->flags & BNXT_FLAG_CHIP_P5) 6047 flags |= FUNC_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST | 6048 FUNC_CFG_REQ_FLAGS_NQ_ASSETS_TEST; 6049 else 6050 flags |= FUNC_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST; 6051 } 6052 6053 req.flags = cpu_to_le32(flags); 6054 return hwrm_send_message_silent(bp, &req, sizeof(req), 6055 HWRM_CMD_TIMEOUT); 6056 } 6057 6058 static int bnxt_hwrm_check_rings(struct bnxt *bp, int tx_rings, int rx_rings, 6059 int ring_grps, int cp_rings, int stats, 6060 int vnics) 6061 { 6062 if (bp->hwrm_spec_code < 0x10801) 6063 return 0; 6064 6065 if (BNXT_PF(bp)) 6066 return bnxt_hwrm_check_pf_rings(bp, tx_rings, rx_rings, 6067 ring_grps, cp_rings, stats, 6068 vnics); 6069 6070 return bnxt_hwrm_check_vf_rings(bp, tx_rings, rx_rings, ring_grps, 6071 cp_rings, stats, vnics); 6072 } 6073 6074 static void bnxt_hwrm_coal_params_qcaps(struct bnxt *bp) 6075 { 6076 struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr; 6077 struct bnxt_coal_cap *coal_cap = &bp->coal_cap; 6078 struct hwrm_ring_aggint_qcaps_input req = {0}; 6079 int rc; 6080 6081 coal_cap->cmpl_params = BNXT_LEGACY_COAL_CMPL_PARAMS; 6082 coal_cap->num_cmpl_dma_aggr_max = 63; 6083 coal_cap->num_cmpl_dma_aggr_during_int_max = 63; 6084 coal_cap->cmpl_aggr_dma_tmr_max = 65535; 6085 coal_cap->cmpl_aggr_dma_tmr_during_int_max = 65535; 6086 coal_cap->int_lat_tmr_min_max = 65535; 6087 coal_cap->int_lat_tmr_max_max = 65535; 6088 coal_cap->num_cmpl_aggr_int_max = 65535; 6089 coal_cap->timer_units = 80; 6090 6091 if (bp->hwrm_spec_code < 0x10902) 6092 return; 6093 6094 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_AGGINT_QCAPS, -1, -1); 6095 mutex_lock(&bp->hwrm_cmd_lock); 6096 rc = _hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 6097 if (!rc) { 6098 coal_cap->cmpl_params = le32_to_cpu(resp->cmpl_params); 6099 coal_cap->nq_params = le32_to_cpu(resp->nq_params); 6100 coal_cap->num_cmpl_dma_aggr_max = 6101 le16_to_cpu(resp->num_cmpl_dma_aggr_max); 6102 coal_cap->num_cmpl_dma_aggr_during_int_max = 6103 le16_to_cpu(resp->num_cmpl_dma_aggr_during_int_max); 6104 coal_cap->cmpl_aggr_dma_tmr_max = 6105 le16_to_cpu(resp->cmpl_aggr_dma_tmr_max); 6106 coal_cap->cmpl_aggr_dma_tmr_during_int_max = 6107 le16_to_cpu(resp->cmpl_aggr_dma_tmr_during_int_max); 6108 coal_cap->int_lat_tmr_min_max = 6109 le16_to_cpu(resp->int_lat_tmr_min_max); 6110 coal_cap->int_lat_tmr_max_max = 6111 le16_to_cpu(resp->int_lat_tmr_max_max); 6112 coal_cap->num_cmpl_aggr_int_max = 6113 le16_to_cpu(resp->num_cmpl_aggr_int_max); 6114 coal_cap->timer_units = le16_to_cpu(resp->timer_units); 6115 } 6116 mutex_unlock(&bp->hwrm_cmd_lock); 6117 } 6118 6119 static u16 bnxt_usec_to_coal_tmr(struct bnxt *bp, u16 usec) 6120 { 6121 struct bnxt_coal_cap *coal_cap = &bp->coal_cap; 6122 6123 return usec * 1000 / coal_cap->timer_units; 6124 } 6125 6126 static void bnxt_hwrm_set_coal_params(struct bnxt *bp, 6127 struct bnxt_coal *hw_coal, 6128 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req) 6129 { 6130 struct bnxt_coal_cap *coal_cap = &bp->coal_cap; 6131 u32 cmpl_params = coal_cap->cmpl_params; 6132 u16 val, tmr, max, flags = 0; 6133 6134 max = hw_coal->bufs_per_record * 128; 6135 if (hw_coal->budget) 6136 max = hw_coal->bufs_per_record * hw_coal->budget; 6137 max = min_t(u16, max, coal_cap->num_cmpl_aggr_int_max); 6138 6139 val = clamp_t(u16, hw_coal->coal_bufs, 1, max); 6140 req->num_cmpl_aggr_int = cpu_to_le16(val); 6141 6142 val = min_t(u16, val, coal_cap->num_cmpl_dma_aggr_max); 6143 req->num_cmpl_dma_aggr = cpu_to_le16(val); 6144 6145 val = clamp_t(u16, hw_coal->coal_bufs_irq, 1, 6146 coal_cap->num_cmpl_dma_aggr_during_int_max); 6147 req->num_cmpl_dma_aggr_during_int = cpu_to_le16(val); 6148 6149 tmr = bnxt_usec_to_coal_tmr(bp, hw_coal->coal_ticks); 6150 tmr = clamp_t(u16, tmr, 1, coal_cap->int_lat_tmr_max_max); 6151 req->int_lat_tmr_max = cpu_to_le16(tmr); 6152 6153 /* min timer set to 1/2 of interrupt timer */ 6154 if (cmpl_params & RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN) { 6155 val = tmr / 2; 6156 val = clamp_t(u16, val, 1, coal_cap->int_lat_tmr_min_max); 6157 req->int_lat_tmr_min = cpu_to_le16(val); 6158 req->enables |= cpu_to_le16(BNXT_COAL_CMPL_MIN_TMR_ENABLE); 6159 } 6160 6161 /* buf timer set to 1/4 of interrupt timer */ 6162 val = clamp_t(u16, tmr / 4, 1, coal_cap->cmpl_aggr_dma_tmr_max); 6163 req->cmpl_aggr_dma_tmr = cpu_to_le16(val); 6164 6165 if (cmpl_params & 6166 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT) { 6167 tmr = bnxt_usec_to_coal_tmr(bp, hw_coal->coal_ticks_irq); 6168 val = clamp_t(u16, tmr, 1, 6169 coal_cap->cmpl_aggr_dma_tmr_during_int_max); 6170 req->cmpl_aggr_dma_tmr_during_int = cpu_to_le16(val); 6171 req->enables |= 6172 cpu_to_le16(BNXT_COAL_CMPL_AGGR_TMR_DURING_INT_ENABLE); 6173 } 6174 6175 if (cmpl_params & RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET) 6176 flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET; 6177 if ((cmpl_params & RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE) && 6178 hw_coal->idle_thresh && hw_coal->coal_ticks < hw_coal->idle_thresh) 6179 flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE; 6180 req->flags = cpu_to_le16(flags); 6181 req->enables |= cpu_to_le16(BNXT_COAL_CMPL_ENABLES); 6182 } 6183 6184 /* Caller holds bp->hwrm_cmd_lock */ 6185 static int __bnxt_hwrm_set_coal_nq(struct bnxt *bp, struct bnxt_napi *bnapi, 6186 struct bnxt_coal *hw_coal) 6187 { 6188 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0}; 6189 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 6190 struct bnxt_coal_cap *coal_cap = &bp->coal_cap; 6191 u32 nq_params = coal_cap->nq_params; 6192 u16 tmr; 6193 6194 if (!(nq_params & RING_AGGINT_QCAPS_RESP_NQ_PARAMS_INT_LAT_TMR_MIN)) 6195 return 0; 6196 6197 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, 6198 -1, -1); 6199 req.ring_id = cpu_to_le16(cpr->cp_ring_struct.fw_ring_id); 6200 req.flags = 6201 cpu_to_le16(RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_IS_NQ); 6202 6203 tmr = bnxt_usec_to_coal_tmr(bp, hw_coal->coal_ticks) / 2; 6204 tmr = clamp_t(u16, tmr, 1, coal_cap->int_lat_tmr_min_max); 6205 req.int_lat_tmr_min = cpu_to_le16(tmr); 6206 req.enables |= cpu_to_le16(BNXT_COAL_CMPL_MIN_TMR_ENABLE); 6207 return _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 6208 } 6209 6210 int bnxt_hwrm_set_ring_coal(struct bnxt *bp, struct bnxt_napi *bnapi) 6211 { 6212 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx = {0}; 6213 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 6214 struct bnxt_coal coal; 6215 6216 /* Tick values in micro seconds. 6217 * 1 coal_buf x bufs_per_record = 1 completion record. 6218 */ 6219 memcpy(&coal, &bp->rx_coal, sizeof(struct bnxt_coal)); 6220 6221 coal.coal_ticks = cpr->rx_ring_coal.coal_ticks; 6222 coal.coal_bufs = cpr->rx_ring_coal.coal_bufs; 6223 6224 if (!bnapi->rx_ring) 6225 return -ENODEV; 6226 6227 bnxt_hwrm_cmd_hdr_init(bp, &req_rx, 6228 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1); 6229 6230 bnxt_hwrm_set_coal_params(bp, &coal, &req_rx); 6231 6232 req_rx.ring_id = cpu_to_le16(bnxt_cp_ring_for_rx(bp, bnapi->rx_ring)); 6233 6234 return hwrm_send_message(bp, &req_rx, sizeof(req_rx), 6235 HWRM_CMD_TIMEOUT); 6236 } 6237 6238 int bnxt_hwrm_set_coal(struct bnxt *bp) 6239 { 6240 int i, rc = 0; 6241 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx = {0}, 6242 req_tx = {0}, *req; 6243 6244 bnxt_hwrm_cmd_hdr_init(bp, &req_rx, 6245 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1); 6246 bnxt_hwrm_cmd_hdr_init(bp, &req_tx, 6247 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1); 6248 6249 bnxt_hwrm_set_coal_params(bp, &bp->rx_coal, &req_rx); 6250 bnxt_hwrm_set_coal_params(bp, &bp->tx_coal, &req_tx); 6251 6252 mutex_lock(&bp->hwrm_cmd_lock); 6253 for (i = 0; i < bp->cp_nr_rings; i++) { 6254 struct bnxt_napi *bnapi = bp->bnapi[i]; 6255 struct bnxt_coal *hw_coal; 6256 u16 ring_id; 6257 6258 req = &req_rx; 6259 if (!bnapi->rx_ring) { 6260 ring_id = bnxt_cp_ring_for_tx(bp, bnapi->tx_ring); 6261 req = &req_tx; 6262 } else { 6263 ring_id = bnxt_cp_ring_for_rx(bp, bnapi->rx_ring); 6264 } 6265 req->ring_id = cpu_to_le16(ring_id); 6266 6267 rc = _hwrm_send_message(bp, req, sizeof(*req), 6268 HWRM_CMD_TIMEOUT); 6269 if (rc) 6270 break; 6271 6272 if (!(bp->flags & BNXT_FLAG_CHIP_P5)) 6273 continue; 6274 6275 if (bnapi->rx_ring && bnapi->tx_ring) { 6276 req = &req_tx; 6277 ring_id = bnxt_cp_ring_for_tx(bp, bnapi->tx_ring); 6278 req->ring_id = cpu_to_le16(ring_id); 6279 rc = _hwrm_send_message(bp, req, sizeof(*req), 6280 HWRM_CMD_TIMEOUT); 6281 if (rc) 6282 break; 6283 } 6284 if (bnapi->rx_ring) 6285 hw_coal = &bp->rx_coal; 6286 else 6287 hw_coal = &bp->tx_coal; 6288 __bnxt_hwrm_set_coal_nq(bp, bnapi, hw_coal); 6289 } 6290 mutex_unlock(&bp->hwrm_cmd_lock); 6291 return rc; 6292 } 6293 6294 static void bnxt_hwrm_stat_ctx_free(struct bnxt *bp) 6295 { 6296 struct hwrm_stat_ctx_free_input req = {0}; 6297 int i; 6298 6299 if (!bp->bnapi) 6300 return; 6301 6302 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 6303 return; 6304 6305 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_FREE, -1, -1); 6306 6307 mutex_lock(&bp->hwrm_cmd_lock); 6308 for (i = 0; i < bp->cp_nr_rings; i++) { 6309 struct bnxt_napi *bnapi = bp->bnapi[i]; 6310 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 6311 6312 if (cpr->hw_stats_ctx_id != INVALID_STATS_CTX_ID) { 6313 req.stat_ctx_id = cpu_to_le32(cpr->hw_stats_ctx_id); 6314 6315 _hwrm_send_message(bp, &req, sizeof(req), 6316 HWRM_CMD_TIMEOUT); 6317 6318 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID; 6319 } 6320 } 6321 mutex_unlock(&bp->hwrm_cmd_lock); 6322 } 6323 6324 static int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp) 6325 { 6326 int rc = 0, i; 6327 struct hwrm_stat_ctx_alloc_input req = {0}; 6328 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr; 6329 6330 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 6331 return 0; 6332 6333 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_ALLOC, -1, -1); 6334 6335 req.stats_dma_length = cpu_to_le16(bp->hw_ring_stats_size); 6336 req.update_period_ms = cpu_to_le32(bp->stats_coal_ticks / 1000); 6337 6338 mutex_lock(&bp->hwrm_cmd_lock); 6339 for (i = 0; i < bp->cp_nr_rings; i++) { 6340 struct bnxt_napi *bnapi = bp->bnapi[i]; 6341 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 6342 6343 req.stats_dma_addr = cpu_to_le64(cpr->hw_stats_map); 6344 6345 rc = _hwrm_send_message(bp, &req, sizeof(req), 6346 HWRM_CMD_TIMEOUT); 6347 if (rc) 6348 break; 6349 6350 cpr->hw_stats_ctx_id = le32_to_cpu(resp->stat_ctx_id); 6351 6352 bp->grp_info[i].fw_stats_ctx = cpr->hw_stats_ctx_id; 6353 } 6354 mutex_unlock(&bp->hwrm_cmd_lock); 6355 return rc; 6356 } 6357 6358 static int bnxt_hwrm_func_qcfg(struct bnxt *bp) 6359 { 6360 struct hwrm_func_qcfg_input req = {0}; 6361 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr; 6362 u16 flags; 6363 int rc; 6364 6365 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1); 6366 req.fid = cpu_to_le16(0xffff); 6367 mutex_lock(&bp->hwrm_cmd_lock); 6368 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 6369 if (rc) 6370 goto func_qcfg_exit; 6371 6372 #ifdef CONFIG_BNXT_SRIOV 6373 if (BNXT_VF(bp)) { 6374 struct bnxt_vf_info *vf = &bp->vf; 6375 6376 vf->vlan = le16_to_cpu(resp->vlan) & VLAN_VID_MASK; 6377 } else { 6378 bp->pf.registered_vfs = le16_to_cpu(resp->registered_vfs); 6379 } 6380 #endif 6381 flags = le16_to_cpu(resp->flags); 6382 if (flags & (FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED | 6383 FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED)) { 6384 bp->fw_cap |= BNXT_FW_CAP_LLDP_AGENT; 6385 if (flags & FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED) 6386 bp->fw_cap |= BNXT_FW_CAP_DCBX_AGENT; 6387 } 6388 if (BNXT_PF(bp) && (flags & FUNC_QCFG_RESP_FLAGS_MULTI_HOST)) 6389 bp->flags |= BNXT_FLAG_MULTI_HOST; 6390 6391 switch (resp->port_partition_type) { 6392 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0: 6393 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5: 6394 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0: 6395 bp->port_partition_type = resp->port_partition_type; 6396 break; 6397 } 6398 if (bp->hwrm_spec_code < 0x10707 || 6399 resp->evb_mode == FUNC_QCFG_RESP_EVB_MODE_VEB) 6400 bp->br_mode = BRIDGE_MODE_VEB; 6401 else if (resp->evb_mode == FUNC_QCFG_RESP_EVB_MODE_VEPA) 6402 bp->br_mode = BRIDGE_MODE_VEPA; 6403 else 6404 bp->br_mode = BRIDGE_MODE_UNDEF; 6405 6406 bp->max_mtu = le16_to_cpu(resp->max_mtu_configured); 6407 if (!bp->max_mtu) 6408 bp->max_mtu = BNXT_MAX_MTU; 6409 6410 func_qcfg_exit: 6411 mutex_unlock(&bp->hwrm_cmd_lock); 6412 return rc; 6413 } 6414 6415 static int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp) 6416 { 6417 struct hwrm_func_backing_store_qcaps_input req = {0}; 6418 struct hwrm_func_backing_store_qcaps_output *resp = 6419 bp->hwrm_cmd_resp_addr; 6420 int rc; 6421 6422 if (bp->hwrm_spec_code < 0x10902 || BNXT_VF(bp) || bp->ctx) 6423 return 0; 6424 6425 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_BACKING_STORE_QCAPS, -1, -1); 6426 mutex_lock(&bp->hwrm_cmd_lock); 6427 rc = _hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 6428 if (!rc) { 6429 struct bnxt_ctx_pg_info *ctx_pg; 6430 struct bnxt_ctx_mem_info *ctx; 6431 int i; 6432 6433 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); 6434 if (!ctx) { 6435 rc = -ENOMEM; 6436 goto ctx_err; 6437 } 6438 ctx_pg = kzalloc(sizeof(*ctx_pg) * (bp->max_q + 1), GFP_KERNEL); 6439 if (!ctx_pg) { 6440 kfree(ctx); 6441 rc = -ENOMEM; 6442 goto ctx_err; 6443 } 6444 for (i = 0; i < bp->max_q + 1; i++, ctx_pg++) 6445 ctx->tqm_mem[i] = ctx_pg; 6446 6447 bp->ctx = ctx; 6448 ctx->qp_max_entries = le32_to_cpu(resp->qp_max_entries); 6449 ctx->qp_min_qp1_entries = le16_to_cpu(resp->qp_min_qp1_entries); 6450 ctx->qp_max_l2_entries = le16_to_cpu(resp->qp_max_l2_entries); 6451 ctx->qp_entry_size = le16_to_cpu(resp->qp_entry_size); 6452 ctx->srq_max_l2_entries = le16_to_cpu(resp->srq_max_l2_entries); 6453 ctx->srq_max_entries = le32_to_cpu(resp->srq_max_entries); 6454 ctx->srq_entry_size = le16_to_cpu(resp->srq_entry_size); 6455 ctx->cq_max_l2_entries = le16_to_cpu(resp->cq_max_l2_entries); 6456 ctx->cq_max_entries = le32_to_cpu(resp->cq_max_entries); 6457 ctx->cq_entry_size = le16_to_cpu(resp->cq_entry_size); 6458 ctx->vnic_max_vnic_entries = 6459 le16_to_cpu(resp->vnic_max_vnic_entries); 6460 ctx->vnic_max_ring_table_entries = 6461 le16_to_cpu(resp->vnic_max_ring_table_entries); 6462 ctx->vnic_entry_size = le16_to_cpu(resp->vnic_entry_size); 6463 ctx->stat_max_entries = le32_to_cpu(resp->stat_max_entries); 6464 ctx->stat_entry_size = le16_to_cpu(resp->stat_entry_size); 6465 ctx->tqm_entry_size = le16_to_cpu(resp->tqm_entry_size); 6466 ctx->tqm_min_entries_per_ring = 6467 le32_to_cpu(resp->tqm_min_entries_per_ring); 6468 ctx->tqm_max_entries_per_ring = 6469 le32_to_cpu(resp->tqm_max_entries_per_ring); 6470 ctx->tqm_entries_multiple = resp->tqm_entries_multiple; 6471 if (!ctx->tqm_entries_multiple) 6472 ctx->tqm_entries_multiple = 1; 6473 ctx->mrav_max_entries = le32_to_cpu(resp->mrav_max_entries); 6474 ctx->mrav_entry_size = le16_to_cpu(resp->mrav_entry_size); 6475 ctx->mrav_num_entries_units = 6476 le16_to_cpu(resp->mrav_num_entries_units); 6477 ctx->tim_entry_size = le16_to_cpu(resp->tim_entry_size); 6478 ctx->tim_max_entries = le32_to_cpu(resp->tim_max_entries); 6479 ctx->ctx_kind_initializer = resp->ctx_kind_initializer; 6480 } else { 6481 rc = 0; 6482 } 6483 ctx_err: 6484 mutex_unlock(&bp->hwrm_cmd_lock); 6485 return rc; 6486 } 6487 6488 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem, u8 *pg_attr, 6489 __le64 *pg_dir) 6490 { 6491 u8 pg_size = 0; 6492 6493 if (BNXT_PAGE_SHIFT == 13) 6494 pg_size = 1 << 4; 6495 else if (BNXT_PAGE_SIZE == 16) 6496 pg_size = 2 << 4; 6497 6498 *pg_attr = pg_size; 6499 if (rmem->depth >= 1) { 6500 if (rmem->depth == 2) 6501 *pg_attr |= 2; 6502 else 6503 *pg_attr |= 1; 6504 *pg_dir = cpu_to_le64(rmem->pg_tbl_map); 6505 } else { 6506 *pg_dir = cpu_to_le64(rmem->dma_arr[0]); 6507 } 6508 } 6509 6510 #define FUNC_BACKING_STORE_CFG_REQ_DFLT_ENABLES \ 6511 (FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP | \ 6512 FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ | \ 6513 FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ | \ 6514 FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC | \ 6515 FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT) 6516 6517 static int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, u32 enables) 6518 { 6519 struct hwrm_func_backing_store_cfg_input req = {0}; 6520 struct bnxt_ctx_mem_info *ctx = bp->ctx; 6521 struct bnxt_ctx_pg_info *ctx_pg; 6522 __le32 *num_entries; 6523 __le64 *pg_dir; 6524 u32 flags = 0; 6525 u8 *pg_attr; 6526 u32 ena; 6527 int i; 6528 6529 if (!ctx) 6530 return 0; 6531 6532 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_BACKING_STORE_CFG, -1, -1); 6533 req.enables = cpu_to_le32(enables); 6534 6535 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP) { 6536 ctx_pg = &ctx->qp_mem; 6537 req.qp_num_entries = cpu_to_le32(ctx_pg->entries); 6538 req.qp_num_qp1_entries = cpu_to_le16(ctx->qp_min_qp1_entries); 6539 req.qp_num_l2_entries = cpu_to_le16(ctx->qp_max_l2_entries); 6540 req.qp_entry_size = cpu_to_le16(ctx->qp_entry_size); 6541 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, 6542 &req.qpc_pg_size_qpc_lvl, 6543 &req.qpc_page_dir); 6544 } 6545 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ) { 6546 ctx_pg = &ctx->srq_mem; 6547 req.srq_num_entries = cpu_to_le32(ctx_pg->entries); 6548 req.srq_num_l2_entries = cpu_to_le16(ctx->srq_max_l2_entries); 6549 req.srq_entry_size = cpu_to_le16(ctx->srq_entry_size); 6550 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, 6551 &req.srq_pg_size_srq_lvl, 6552 &req.srq_page_dir); 6553 } 6554 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ) { 6555 ctx_pg = &ctx->cq_mem; 6556 req.cq_num_entries = cpu_to_le32(ctx_pg->entries); 6557 req.cq_num_l2_entries = cpu_to_le16(ctx->cq_max_l2_entries); 6558 req.cq_entry_size = cpu_to_le16(ctx->cq_entry_size); 6559 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, &req.cq_pg_size_cq_lvl, 6560 &req.cq_page_dir); 6561 } 6562 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC) { 6563 ctx_pg = &ctx->vnic_mem; 6564 req.vnic_num_vnic_entries = 6565 cpu_to_le16(ctx->vnic_max_vnic_entries); 6566 req.vnic_num_ring_table_entries = 6567 cpu_to_le16(ctx->vnic_max_ring_table_entries); 6568 req.vnic_entry_size = cpu_to_le16(ctx->vnic_entry_size); 6569 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, 6570 &req.vnic_pg_size_vnic_lvl, 6571 &req.vnic_page_dir); 6572 } 6573 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT) { 6574 ctx_pg = &ctx->stat_mem; 6575 req.stat_num_entries = cpu_to_le32(ctx->stat_max_entries); 6576 req.stat_entry_size = cpu_to_le16(ctx->stat_entry_size); 6577 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, 6578 &req.stat_pg_size_stat_lvl, 6579 &req.stat_page_dir); 6580 } 6581 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV) { 6582 ctx_pg = &ctx->mrav_mem; 6583 req.mrav_num_entries = cpu_to_le32(ctx_pg->entries); 6584 if (ctx->mrav_num_entries_units) 6585 flags |= 6586 FUNC_BACKING_STORE_CFG_REQ_FLAGS_MRAV_RESERVATION_SPLIT; 6587 req.mrav_entry_size = cpu_to_le16(ctx->mrav_entry_size); 6588 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, 6589 &req.mrav_pg_size_mrav_lvl, 6590 &req.mrav_page_dir); 6591 } 6592 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM) { 6593 ctx_pg = &ctx->tim_mem; 6594 req.tim_num_entries = cpu_to_le32(ctx_pg->entries); 6595 req.tim_entry_size = cpu_to_le16(ctx->tim_entry_size); 6596 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, 6597 &req.tim_pg_size_tim_lvl, 6598 &req.tim_page_dir); 6599 } 6600 for (i = 0, num_entries = &req.tqm_sp_num_entries, 6601 pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl, 6602 pg_dir = &req.tqm_sp_page_dir, 6603 ena = FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP; 6604 i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) { 6605 if (!(enables & ena)) 6606 continue; 6607 6608 req.tqm_entry_size = cpu_to_le16(ctx->tqm_entry_size); 6609 ctx_pg = ctx->tqm_mem[i]; 6610 *num_entries = cpu_to_le32(ctx_pg->entries); 6611 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir); 6612 } 6613 req.flags = cpu_to_le32(flags); 6614 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 6615 } 6616 6617 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp, 6618 struct bnxt_ctx_pg_info *ctx_pg) 6619 { 6620 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem; 6621 6622 rmem->page_size = BNXT_PAGE_SIZE; 6623 rmem->pg_arr = ctx_pg->ctx_pg_arr; 6624 rmem->dma_arr = ctx_pg->ctx_dma_arr; 6625 rmem->flags = BNXT_RMEM_VALID_PTE_FLAG; 6626 if (rmem->depth >= 1) 6627 rmem->flags |= BNXT_RMEM_USE_FULL_PAGE_FLAG; 6628 return bnxt_alloc_ring(bp, rmem); 6629 } 6630 6631 static int bnxt_alloc_ctx_pg_tbls(struct bnxt *bp, 6632 struct bnxt_ctx_pg_info *ctx_pg, u32 mem_size, 6633 u8 depth, bool use_init_val) 6634 { 6635 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem; 6636 int rc; 6637 6638 if (!mem_size) 6639 return -EINVAL; 6640 6641 ctx_pg->nr_pages = DIV_ROUND_UP(mem_size, BNXT_PAGE_SIZE); 6642 if (ctx_pg->nr_pages > MAX_CTX_TOTAL_PAGES) { 6643 ctx_pg->nr_pages = 0; 6644 return -EINVAL; 6645 } 6646 if (ctx_pg->nr_pages > MAX_CTX_PAGES || depth > 1) { 6647 int nr_tbls, i; 6648 6649 rmem->depth = 2; 6650 ctx_pg->ctx_pg_tbl = kcalloc(MAX_CTX_PAGES, sizeof(ctx_pg), 6651 GFP_KERNEL); 6652 if (!ctx_pg->ctx_pg_tbl) 6653 return -ENOMEM; 6654 nr_tbls = DIV_ROUND_UP(ctx_pg->nr_pages, MAX_CTX_PAGES); 6655 rmem->nr_pages = nr_tbls; 6656 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg); 6657 if (rc) 6658 return rc; 6659 for (i = 0; i < nr_tbls; i++) { 6660 struct bnxt_ctx_pg_info *pg_tbl; 6661 6662 pg_tbl = kzalloc(sizeof(*pg_tbl), GFP_KERNEL); 6663 if (!pg_tbl) 6664 return -ENOMEM; 6665 ctx_pg->ctx_pg_tbl[i] = pg_tbl; 6666 rmem = &pg_tbl->ring_mem; 6667 rmem->pg_tbl = ctx_pg->ctx_pg_arr[i]; 6668 rmem->pg_tbl_map = ctx_pg->ctx_dma_arr[i]; 6669 rmem->depth = 1; 6670 rmem->nr_pages = MAX_CTX_PAGES; 6671 if (use_init_val) 6672 rmem->init_val = bp->ctx->ctx_kind_initializer; 6673 if (i == (nr_tbls - 1)) { 6674 int rem = ctx_pg->nr_pages % MAX_CTX_PAGES; 6675 6676 if (rem) 6677 rmem->nr_pages = rem; 6678 } 6679 rc = bnxt_alloc_ctx_mem_blk(bp, pg_tbl); 6680 if (rc) 6681 break; 6682 } 6683 } else { 6684 rmem->nr_pages = DIV_ROUND_UP(mem_size, BNXT_PAGE_SIZE); 6685 if (rmem->nr_pages > 1 || depth) 6686 rmem->depth = 1; 6687 if (use_init_val) 6688 rmem->init_val = bp->ctx->ctx_kind_initializer; 6689 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg); 6690 } 6691 return rc; 6692 } 6693 6694 static void bnxt_free_ctx_pg_tbls(struct bnxt *bp, 6695 struct bnxt_ctx_pg_info *ctx_pg) 6696 { 6697 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem; 6698 6699 if (rmem->depth > 1 || ctx_pg->nr_pages > MAX_CTX_PAGES || 6700 ctx_pg->ctx_pg_tbl) { 6701 int i, nr_tbls = rmem->nr_pages; 6702 6703 for (i = 0; i < nr_tbls; i++) { 6704 struct bnxt_ctx_pg_info *pg_tbl; 6705 struct bnxt_ring_mem_info *rmem2; 6706 6707 pg_tbl = ctx_pg->ctx_pg_tbl[i]; 6708 if (!pg_tbl) 6709 continue; 6710 rmem2 = &pg_tbl->ring_mem; 6711 bnxt_free_ring(bp, rmem2); 6712 ctx_pg->ctx_pg_arr[i] = NULL; 6713 kfree(pg_tbl); 6714 ctx_pg->ctx_pg_tbl[i] = NULL; 6715 } 6716 kfree(ctx_pg->ctx_pg_tbl); 6717 ctx_pg->ctx_pg_tbl = NULL; 6718 } 6719 bnxt_free_ring(bp, rmem); 6720 ctx_pg->nr_pages = 0; 6721 } 6722 6723 static void bnxt_free_ctx_mem(struct bnxt *bp) 6724 { 6725 struct bnxt_ctx_mem_info *ctx = bp->ctx; 6726 int i; 6727 6728 if (!ctx) 6729 return; 6730 6731 if (ctx->tqm_mem[0]) { 6732 for (i = 0; i < bp->max_q + 1; i++) 6733 bnxt_free_ctx_pg_tbls(bp, ctx->tqm_mem[i]); 6734 kfree(ctx->tqm_mem[0]); 6735 ctx->tqm_mem[0] = NULL; 6736 } 6737 6738 bnxt_free_ctx_pg_tbls(bp, &ctx->tim_mem); 6739 bnxt_free_ctx_pg_tbls(bp, &ctx->mrav_mem); 6740 bnxt_free_ctx_pg_tbls(bp, &ctx->stat_mem); 6741 bnxt_free_ctx_pg_tbls(bp, &ctx->vnic_mem); 6742 bnxt_free_ctx_pg_tbls(bp, &ctx->cq_mem); 6743 bnxt_free_ctx_pg_tbls(bp, &ctx->srq_mem); 6744 bnxt_free_ctx_pg_tbls(bp, &ctx->qp_mem); 6745 ctx->flags &= ~BNXT_CTX_FLAG_INITED; 6746 } 6747 6748 static int bnxt_alloc_ctx_mem(struct bnxt *bp) 6749 { 6750 struct bnxt_ctx_pg_info *ctx_pg; 6751 struct bnxt_ctx_mem_info *ctx; 6752 u32 mem_size, ena, entries; 6753 u32 num_mr, num_ah; 6754 u32 extra_srqs = 0; 6755 u32 extra_qps = 0; 6756 u8 pg_lvl = 1; 6757 int i, rc; 6758 6759 rc = bnxt_hwrm_func_backing_store_qcaps(bp); 6760 if (rc) { 6761 netdev_err(bp->dev, "Failed querying context mem capability, rc = %d.\n", 6762 rc); 6763 return rc; 6764 } 6765 ctx = bp->ctx; 6766 if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED)) 6767 return 0; 6768 6769 if ((bp->flags & BNXT_FLAG_ROCE_CAP) && !is_kdump_kernel()) { 6770 pg_lvl = 2; 6771 extra_qps = 65536; 6772 extra_srqs = 8192; 6773 } 6774 6775 ctx_pg = &ctx->qp_mem; 6776 ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries + 6777 extra_qps; 6778 mem_size = ctx->qp_entry_size * ctx_pg->entries; 6779 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, pg_lvl, true); 6780 if (rc) 6781 return rc; 6782 6783 ctx_pg = &ctx->srq_mem; 6784 ctx_pg->entries = ctx->srq_max_l2_entries + extra_srqs; 6785 mem_size = ctx->srq_entry_size * ctx_pg->entries; 6786 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, pg_lvl, true); 6787 if (rc) 6788 return rc; 6789 6790 ctx_pg = &ctx->cq_mem; 6791 ctx_pg->entries = ctx->cq_max_l2_entries + extra_qps * 2; 6792 mem_size = ctx->cq_entry_size * ctx_pg->entries; 6793 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, pg_lvl, true); 6794 if (rc) 6795 return rc; 6796 6797 ctx_pg = &ctx->vnic_mem; 6798 ctx_pg->entries = ctx->vnic_max_vnic_entries + 6799 ctx->vnic_max_ring_table_entries; 6800 mem_size = ctx->vnic_entry_size * ctx_pg->entries; 6801 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1, true); 6802 if (rc) 6803 return rc; 6804 6805 ctx_pg = &ctx->stat_mem; 6806 ctx_pg->entries = ctx->stat_max_entries; 6807 mem_size = ctx->stat_entry_size * ctx_pg->entries; 6808 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1, true); 6809 if (rc) 6810 return rc; 6811 6812 ena = 0; 6813 if (!(bp->flags & BNXT_FLAG_ROCE_CAP)) 6814 goto skip_rdma; 6815 6816 ctx_pg = &ctx->mrav_mem; 6817 /* 128K extra is needed to accommodate static AH context 6818 * allocation by f/w. 6819 */ 6820 num_mr = 1024 * 256; 6821 num_ah = 1024 * 128; 6822 ctx_pg->entries = num_mr + num_ah; 6823 mem_size = ctx->mrav_entry_size * ctx_pg->entries; 6824 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 2, true); 6825 if (rc) 6826 return rc; 6827 ena = FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV; 6828 if (ctx->mrav_num_entries_units) 6829 ctx_pg->entries = 6830 ((num_mr / ctx->mrav_num_entries_units) << 16) | 6831 (num_ah / ctx->mrav_num_entries_units); 6832 6833 ctx_pg = &ctx->tim_mem; 6834 ctx_pg->entries = ctx->qp_mem.entries; 6835 mem_size = ctx->tim_entry_size * ctx_pg->entries; 6836 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1, false); 6837 if (rc) 6838 return rc; 6839 ena |= FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM; 6840 6841 skip_rdma: 6842 entries = ctx->qp_max_l2_entries + extra_qps; 6843 entries = roundup(entries, ctx->tqm_entries_multiple); 6844 entries = clamp_t(u32, entries, ctx->tqm_min_entries_per_ring, 6845 ctx->tqm_max_entries_per_ring); 6846 for (i = 0; i < bp->max_q + 1; i++) { 6847 ctx_pg = ctx->tqm_mem[i]; 6848 ctx_pg->entries = entries; 6849 mem_size = ctx->tqm_entry_size * entries; 6850 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1, false); 6851 if (rc) 6852 return rc; 6853 ena |= FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP << i; 6854 } 6855 ena |= FUNC_BACKING_STORE_CFG_REQ_DFLT_ENABLES; 6856 rc = bnxt_hwrm_func_backing_store_cfg(bp, ena); 6857 if (rc) { 6858 netdev_err(bp->dev, "Failed configuring context mem, rc = %d.\n", 6859 rc); 6860 return rc; 6861 } 6862 ctx->flags |= BNXT_CTX_FLAG_INITED; 6863 return 0; 6864 } 6865 6866 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp, bool all) 6867 { 6868 struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr; 6869 struct hwrm_func_resource_qcaps_input req = {0}; 6870 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 6871 int rc; 6872 6873 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESOURCE_QCAPS, -1, -1); 6874 req.fid = cpu_to_le16(0xffff); 6875 6876 mutex_lock(&bp->hwrm_cmd_lock); 6877 rc = _hwrm_send_message_silent(bp, &req, sizeof(req), 6878 HWRM_CMD_TIMEOUT); 6879 if (rc) 6880 goto hwrm_func_resc_qcaps_exit; 6881 6882 hw_resc->max_tx_sch_inputs = le16_to_cpu(resp->max_tx_scheduler_inputs); 6883 if (!all) 6884 goto hwrm_func_resc_qcaps_exit; 6885 6886 hw_resc->min_rsscos_ctxs = le16_to_cpu(resp->min_rsscos_ctx); 6887 hw_resc->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx); 6888 hw_resc->min_cp_rings = le16_to_cpu(resp->min_cmpl_rings); 6889 hw_resc->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings); 6890 hw_resc->min_tx_rings = le16_to_cpu(resp->min_tx_rings); 6891 hw_resc->max_tx_rings = le16_to_cpu(resp->max_tx_rings); 6892 hw_resc->min_rx_rings = le16_to_cpu(resp->min_rx_rings); 6893 hw_resc->max_rx_rings = le16_to_cpu(resp->max_rx_rings); 6894 hw_resc->min_hw_ring_grps = le16_to_cpu(resp->min_hw_ring_grps); 6895 hw_resc->max_hw_ring_grps = le16_to_cpu(resp->max_hw_ring_grps); 6896 hw_resc->min_l2_ctxs = le16_to_cpu(resp->min_l2_ctxs); 6897 hw_resc->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs); 6898 hw_resc->min_vnics = le16_to_cpu(resp->min_vnics); 6899 hw_resc->max_vnics = le16_to_cpu(resp->max_vnics); 6900 hw_resc->min_stat_ctxs = le16_to_cpu(resp->min_stat_ctx); 6901 hw_resc->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx); 6902 6903 if (bp->flags & BNXT_FLAG_CHIP_P5) { 6904 u16 max_msix = le16_to_cpu(resp->max_msix); 6905 6906 hw_resc->max_nqs = max_msix; 6907 hw_resc->max_hw_ring_grps = hw_resc->max_rx_rings; 6908 } 6909 6910 if (BNXT_PF(bp)) { 6911 struct bnxt_pf_info *pf = &bp->pf; 6912 6913 pf->vf_resv_strategy = 6914 le16_to_cpu(resp->vf_reservation_strategy); 6915 if (pf->vf_resv_strategy > BNXT_VF_RESV_STRATEGY_MINIMAL_STATIC) 6916 pf->vf_resv_strategy = BNXT_VF_RESV_STRATEGY_MAXIMAL; 6917 } 6918 hwrm_func_resc_qcaps_exit: 6919 mutex_unlock(&bp->hwrm_cmd_lock); 6920 return rc; 6921 } 6922 6923 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp) 6924 { 6925 int rc = 0; 6926 struct hwrm_func_qcaps_input req = {0}; 6927 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr; 6928 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 6929 u32 flags; 6930 6931 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCAPS, -1, -1); 6932 req.fid = cpu_to_le16(0xffff); 6933 6934 mutex_lock(&bp->hwrm_cmd_lock); 6935 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 6936 if (rc) 6937 goto hwrm_func_qcaps_exit; 6938 6939 flags = le32_to_cpu(resp->flags); 6940 if (flags & FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED) 6941 bp->flags |= BNXT_FLAG_ROCEV1_CAP; 6942 if (flags & FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED) 6943 bp->flags |= BNXT_FLAG_ROCEV2_CAP; 6944 if (flags & FUNC_QCAPS_RESP_FLAGS_PCIE_STATS_SUPPORTED) 6945 bp->fw_cap |= BNXT_FW_CAP_PCIE_STATS_SUPPORTED; 6946 if (flags & FUNC_QCAPS_RESP_FLAGS_HOT_RESET_CAPABLE) 6947 bp->fw_cap |= BNXT_FW_CAP_HOT_RESET; 6948 if (flags & FUNC_QCAPS_RESP_FLAGS_EXT_STATS_SUPPORTED) 6949 bp->fw_cap |= BNXT_FW_CAP_EXT_STATS_SUPPORTED; 6950 if (flags & FUNC_QCAPS_RESP_FLAGS_ERROR_RECOVERY_CAPABLE) 6951 bp->fw_cap |= BNXT_FW_CAP_ERROR_RECOVERY; 6952 if (flags & FUNC_QCAPS_RESP_FLAGS_ERR_RECOVER_RELOAD) 6953 bp->fw_cap |= BNXT_FW_CAP_ERR_RECOVER_RELOAD; 6954 6955 bp->tx_push_thresh = 0; 6956 if (flags & FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED) 6957 bp->tx_push_thresh = BNXT_TX_PUSH_THRESH; 6958 6959 hw_resc->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx); 6960 hw_resc->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings); 6961 hw_resc->max_tx_rings = le16_to_cpu(resp->max_tx_rings); 6962 hw_resc->max_rx_rings = le16_to_cpu(resp->max_rx_rings); 6963 hw_resc->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps); 6964 if (!hw_resc->max_hw_ring_grps) 6965 hw_resc->max_hw_ring_grps = hw_resc->max_tx_rings; 6966 hw_resc->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs); 6967 hw_resc->max_vnics = le16_to_cpu(resp->max_vnics); 6968 hw_resc->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx); 6969 6970 if (BNXT_PF(bp)) { 6971 struct bnxt_pf_info *pf = &bp->pf; 6972 6973 pf->fw_fid = le16_to_cpu(resp->fid); 6974 pf->port_id = le16_to_cpu(resp->port_id); 6975 memcpy(pf->mac_addr, resp->mac_address, ETH_ALEN); 6976 pf->first_vf_id = le16_to_cpu(resp->first_vf_id); 6977 pf->max_vfs = le16_to_cpu(resp->max_vfs); 6978 pf->max_encap_records = le32_to_cpu(resp->max_encap_records); 6979 pf->max_decap_records = le32_to_cpu(resp->max_decap_records); 6980 pf->max_tx_em_flows = le32_to_cpu(resp->max_tx_em_flows); 6981 pf->max_tx_wm_flows = le32_to_cpu(resp->max_tx_wm_flows); 6982 pf->max_rx_em_flows = le32_to_cpu(resp->max_rx_em_flows); 6983 pf->max_rx_wm_flows = le32_to_cpu(resp->max_rx_wm_flows); 6984 bp->flags &= ~BNXT_FLAG_WOL_CAP; 6985 if (flags & FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED) 6986 bp->flags |= BNXT_FLAG_WOL_CAP; 6987 } else { 6988 #ifdef CONFIG_BNXT_SRIOV 6989 struct bnxt_vf_info *vf = &bp->vf; 6990 6991 vf->fw_fid = le16_to_cpu(resp->fid); 6992 memcpy(vf->mac_addr, resp->mac_address, ETH_ALEN); 6993 #endif 6994 } 6995 6996 hwrm_func_qcaps_exit: 6997 mutex_unlock(&bp->hwrm_cmd_lock); 6998 return rc; 6999 } 7000 7001 static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp); 7002 7003 static int bnxt_hwrm_func_qcaps(struct bnxt *bp) 7004 { 7005 int rc; 7006 7007 rc = __bnxt_hwrm_func_qcaps(bp); 7008 if (rc) 7009 return rc; 7010 rc = bnxt_hwrm_queue_qportcfg(bp); 7011 if (rc) { 7012 netdev_err(bp->dev, "hwrm query qportcfg failure rc: %d\n", rc); 7013 return rc; 7014 } 7015 if (bp->hwrm_spec_code >= 0x10803) { 7016 rc = bnxt_alloc_ctx_mem(bp); 7017 if (rc) 7018 return rc; 7019 rc = bnxt_hwrm_func_resc_qcaps(bp, true); 7020 if (!rc) 7021 bp->fw_cap |= BNXT_FW_CAP_NEW_RM; 7022 } 7023 return 0; 7024 } 7025 7026 static int bnxt_hwrm_cfa_adv_flow_mgnt_qcaps(struct bnxt *bp) 7027 { 7028 struct hwrm_cfa_adv_flow_mgnt_qcaps_input req = {0}; 7029 struct hwrm_cfa_adv_flow_mgnt_qcaps_output *resp; 7030 int rc = 0; 7031 u32 flags; 7032 7033 if (!(bp->fw_cap & BNXT_FW_CAP_CFA_ADV_FLOW)) 7034 return 0; 7035 7036 resp = bp->hwrm_cmd_resp_addr; 7037 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_ADV_FLOW_MGNT_QCAPS, -1, -1); 7038 7039 mutex_lock(&bp->hwrm_cmd_lock); 7040 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 7041 if (rc) 7042 goto hwrm_cfa_adv_qcaps_exit; 7043 7044 flags = le32_to_cpu(resp->flags); 7045 if (flags & 7046 CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RFS_RING_TBL_IDX_V2_SUPPORTED) 7047 bp->fw_cap |= BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V2; 7048 7049 hwrm_cfa_adv_qcaps_exit: 7050 mutex_unlock(&bp->hwrm_cmd_lock); 7051 return rc; 7052 } 7053 7054 static int bnxt_map_fw_health_regs(struct bnxt *bp) 7055 { 7056 struct bnxt_fw_health *fw_health = bp->fw_health; 7057 u32 reg_base = 0xffffffff; 7058 int i; 7059 7060 /* Only pre-map the monitoring GRC registers using window 3 */ 7061 for (i = 0; i < 4; i++) { 7062 u32 reg = fw_health->regs[i]; 7063 7064 if (BNXT_FW_HEALTH_REG_TYPE(reg) != BNXT_FW_HEALTH_REG_TYPE_GRC) 7065 continue; 7066 if (reg_base == 0xffffffff) 7067 reg_base = reg & BNXT_GRC_BASE_MASK; 7068 if ((reg & BNXT_GRC_BASE_MASK) != reg_base) 7069 return -ERANGE; 7070 fw_health->mapped_regs[i] = BNXT_FW_HEALTH_WIN_BASE + 7071 (reg & BNXT_GRC_OFFSET_MASK); 7072 } 7073 if (reg_base == 0xffffffff) 7074 return 0; 7075 7076 writel(reg_base, bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 7077 BNXT_FW_HEALTH_WIN_MAP_OFF); 7078 return 0; 7079 } 7080 7081 static int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp) 7082 { 7083 struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr; 7084 struct bnxt_fw_health *fw_health = bp->fw_health; 7085 struct hwrm_error_recovery_qcfg_input req = {0}; 7086 int rc, i; 7087 7088 if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)) 7089 return 0; 7090 7091 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_ERROR_RECOVERY_QCFG, -1, -1); 7092 mutex_lock(&bp->hwrm_cmd_lock); 7093 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 7094 if (rc) 7095 goto err_recovery_out; 7096 fw_health->flags = le32_to_cpu(resp->flags); 7097 if ((fw_health->flags & ERROR_RECOVERY_QCFG_RESP_FLAGS_CO_CPU) && 7098 !(bp->fw_cap & BNXT_FW_CAP_KONG_MB_CHNL)) { 7099 rc = -EINVAL; 7100 goto err_recovery_out; 7101 } 7102 fw_health->polling_dsecs = le32_to_cpu(resp->driver_polling_freq); 7103 fw_health->master_func_wait_dsecs = 7104 le32_to_cpu(resp->master_func_wait_period); 7105 fw_health->normal_func_wait_dsecs = 7106 le32_to_cpu(resp->normal_func_wait_period); 7107 fw_health->post_reset_wait_dsecs = 7108 le32_to_cpu(resp->master_func_wait_period_after_reset); 7109 fw_health->post_reset_max_wait_dsecs = 7110 le32_to_cpu(resp->max_bailout_time_after_reset); 7111 fw_health->regs[BNXT_FW_HEALTH_REG] = 7112 le32_to_cpu(resp->fw_health_status_reg); 7113 fw_health->regs[BNXT_FW_HEARTBEAT_REG] = 7114 le32_to_cpu(resp->fw_heartbeat_reg); 7115 fw_health->regs[BNXT_FW_RESET_CNT_REG] = 7116 le32_to_cpu(resp->fw_reset_cnt_reg); 7117 fw_health->regs[BNXT_FW_RESET_INPROG_REG] = 7118 le32_to_cpu(resp->reset_inprogress_reg); 7119 fw_health->fw_reset_inprog_reg_mask = 7120 le32_to_cpu(resp->reset_inprogress_reg_mask); 7121 fw_health->fw_reset_seq_cnt = resp->reg_array_cnt; 7122 if (fw_health->fw_reset_seq_cnt >= 16) { 7123 rc = -EINVAL; 7124 goto err_recovery_out; 7125 } 7126 for (i = 0; i < fw_health->fw_reset_seq_cnt; i++) { 7127 fw_health->fw_reset_seq_regs[i] = 7128 le32_to_cpu(resp->reset_reg[i]); 7129 fw_health->fw_reset_seq_vals[i] = 7130 le32_to_cpu(resp->reset_reg_val[i]); 7131 fw_health->fw_reset_seq_delay_msec[i] = 7132 resp->delay_after_reset[i]; 7133 } 7134 err_recovery_out: 7135 mutex_unlock(&bp->hwrm_cmd_lock); 7136 if (!rc) 7137 rc = bnxt_map_fw_health_regs(bp); 7138 if (rc) 7139 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY; 7140 return rc; 7141 } 7142 7143 static int bnxt_hwrm_func_reset(struct bnxt *bp) 7144 { 7145 struct hwrm_func_reset_input req = {0}; 7146 7147 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESET, -1, -1); 7148 req.enables = 0; 7149 7150 return hwrm_send_message(bp, &req, sizeof(req), HWRM_RESET_TIMEOUT); 7151 } 7152 7153 static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp) 7154 { 7155 int rc = 0; 7156 struct hwrm_queue_qportcfg_input req = {0}; 7157 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr; 7158 u8 i, j, *qptr; 7159 bool no_rdma; 7160 7161 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_QUEUE_QPORTCFG, -1, -1); 7162 7163 mutex_lock(&bp->hwrm_cmd_lock); 7164 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 7165 if (rc) 7166 goto qportcfg_exit; 7167 7168 if (!resp->max_configurable_queues) { 7169 rc = -EINVAL; 7170 goto qportcfg_exit; 7171 } 7172 bp->max_tc = resp->max_configurable_queues; 7173 bp->max_lltc = resp->max_configurable_lossless_queues; 7174 if (bp->max_tc > BNXT_MAX_QUEUE) 7175 bp->max_tc = BNXT_MAX_QUEUE; 7176 7177 no_rdma = !(bp->flags & BNXT_FLAG_ROCE_CAP); 7178 qptr = &resp->queue_id0; 7179 for (i = 0, j = 0; i < bp->max_tc; i++) { 7180 bp->q_info[j].queue_id = *qptr; 7181 bp->q_ids[i] = *qptr++; 7182 bp->q_info[j].queue_profile = *qptr++; 7183 bp->tc_to_qidx[j] = j; 7184 if (!BNXT_CNPQ(bp->q_info[j].queue_profile) || 7185 (no_rdma && BNXT_PF(bp))) 7186 j++; 7187 } 7188 bp->max_q = bp->max_tc; 7189 bp->max_tc = max_t(u8, j, 1); 7190 7191 if (resp->queue_cfg_info & QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG) 7192 bp->max_tc = 1; 7193 7194 if (bp->max_lltc > bp->max_tc) 7195 bp->max_lltc = bp->max_tc; 7196 7197 qportcfg_exit: 7198 mutex_unlock(&bp->hwrm_cmd_lock); 7199 return rc; 7200 } 7201 7202 static int __bnxt_hwrm_ver_get(struct bnxt *bp, bool silent) 7203 { 7204 struct hwrm_ver_get_input req = {0}; 7205 int rc; 7206 7207 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VER_GET, -1, -1); 7208 req.hwrm_intf_maj = HWRM_VERSION_MAJOR; 7209 req.hwrm_intf_min = HWRM_VERSION_MINOR; 7210 req.hwrm_intf_upd = HWRM_VERSION_UPDATE; 7211 7212 rc = bnxt_hwrm_do_send_msg(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT, 7213 silent); 7214 return rc; 7215 } 7216 7217 static int bnxt_hwrm_ver_get(struct bnxt *bp) 7218 { 7219 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr; 7220 u32 dev_caps_cfg, hwrm_ver; 7221 int rc; 7222 7223 bp->hwrm_max_req_len = HWRM_MAX_REQ_LEN; 7224 mutex_lock(&bp->hwrm_cmd_lock); 7225 rc = __bnxt_hwrm_ver_get(bp, false); 7226 if (rc) 7227 goto hwrm_ver_get_exit; 7228 7229 memcpy(&bp->ver_resp, resp, sizeof(struct hwrm_ver_get_output)); 7230 7231 bp->hwrm_spec_code = resp->hwrm_intf_maj_8b << 16 | 7232 resp->hwrm_intf_min_8b << 8 | 7233 resp->hwrm_intf_upd_8b; 7234 if (resp->hwrm_intf_maj_8b < 1) { 7235 netdev_warn(bp->dev, "HWRM interface %d.%d.%d is older than 1.0.0.\n", 7236 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b, 7237 resp->hwrm_intf_upd_8b); 7238 netdev_warn(bp->dev, "Please update firmware with HWRM interface 1.0.0 or newer.\n"); 7239 } 7240 7241 hwrm_ver = HWRM_VERSION_MAJOR << 16 | HWRM_VERSION_MINOR << 8 | 7242 HWRM_VERSION_UPDATE; 7243 7244 if (bp->hwrm_spec_code > hwrm_ver) 7245 snprintf(bp->hwrm_ver_supp, FW_VER_STR_LEN, "%d.%d.%d", 7246 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, 7247 HWRM_VERSION_UPDATE); 7248 else 7249 snprintf(bp->hwrm_ver_supp, FW_VER_STR_LEN, "%d.%d.%d", 7250 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b, 7251 resp->hwrm_intf_upd_8b); 7252 7253 snprintf(bp->fw_ver_str, BC_HWRM_STR_LEN, "%d.%d.%d.%d", 7254 resp->hwrm_fw_maj_8b, resp->hwrm_fw_min_8b, 7255 resp->hwrm_fw_bld_8b, resp->hwrm_fw_rsvd_8b); 7256 7257 if (strlen(resp->active_pkg_name)) { 7258 int fw_ver_len = strlen(bp->fw_ver_str); 7259 7260 snprintf(bp->fw_ver_str + fw_ver_len, 7261 FW_VER_STR_LEN - fw_ver_len - 1, "/pkg %s", 7262 resp->active_pkg_name); 7263 bp->fw_cap |= BNXT_FW_CAP_PKG_VER; 7264 } 7265 7266 bp->hwrm_cmd_timeout = le16_to_cpu(resp->def_req_timeout); 7267 if (!bp->hwrm_cmd_timeout) 7268 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT; 7269 7270 if (resp->hwrm_intf_maj_8b >= 1) { 7271 bp->hwrm_max_req_len = le16_to_cpu(resp->max_req_win_len); 7272 bp->hwrm_max_ext_req_len = le16_to_cpu(resp->max_ext_req_len); 7273 } 7274 if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN) 7275 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN; 7276 7277 bp->chip_num = le16_to_cpu(resp->chip_num); 7278 bp->chip_rev = resp->chip_rev; 7279 if (bp->chip_num == CHIP_NUM_58700 && !resp->chip_rev && 7280 !resp->chip_metal) 7281 bp->flags |= BNXT_FLAG_CHIP_NITRO_A0; 7282 7283 dev_caps_cfg = le32_to_cpu(resp->dev_caps_cfg); 7284 if ((dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) && 7285 (dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) 7286 bp->fw_cap |= BNXT_FW_CAP_SHORT_CMD; 7287 7288 if (dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) 7289 bp->fw_cap |= BNXT_FW_CAP_KONG_MB_CHNL; 7290 7291 if (dev_caps_cfg & 7292 VER_GET_RESP_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED) 7293 bp->fw_cap |= BNXT_FW_CAP_OVS_64BIT_HANDLE; 7294 7295 if (dev_caps_cfg & 7296 VER_GET_RESP_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED) 7297 bp->fw_cap |= BNXT_FW_CAP_TRUSTED_VF; 7298 7299 if (dev_caps_cfg & 7300 VER_GET_RESP_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED) 7301 bp->fw_cap |= BNXT_FW_CAP_CFA_ADV_FLOW; 7302 7303 hwrm_ver_get_exit: 7304 mutex_unlock(&bp->hwrm_cmd_lock); 7305 return rc; 7306 } 7307 7308 int bnxt_hwrm_fw_set_time(struct bnxt *bp) 7309 { 7310 struct hwrm_fw_set_time_input req = {0}; 7311 struct tm tm; 7312 time64_t now = ktime_get_real_seconds(); 7313 7314 if ((BNXT_VF(bp) && bp->hwrm_spec_code < 0x10901) || 7315 bp->hwrm_spec_code < 0x10400) 7316 return -EOPNOTSUPP; 7317 7318 time64_to_tm(now, 0, &tm); 7319 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FW_SET_TIME, -1, -1); 7320 req.year = cpu_to_le16(1900 + tm.tm_year); 7321 req.month = 1 + tm.tm_mon; 7322 req.day = tm.tm_mday; 7323 req.hour = tm.tm_hour; 7324 req.minute = tm.tm_min; 7325 req.second = tm.tm_sec; 7326 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 7327 } 7328 7329 static int bnxt_hwrm_port_qstats(struct bnxt *bp) 7330 { 7331 struct bnxt_pf_info *pf = &bp->pf; 7332 struct hwrm_port_qstats_input req = {0}; 7333 7334 if (!(bp->flags & BNXT_FLAG_PORT_STATS)) 7335 return 0; 7336 7337 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_QSTATS, -1, -1); 7338 req.port_id = cpu_to_le16(pf->port_id); 7339 req.tx_stat_host_addr = cpu_to_le64(bp->hw_tx_port_stats_map); 7340 req.rx_stat_host_addr = cpu_to_le64(bp->hw_rx_port_stats_map); 7341 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 7342 } 7343 7344 static int bnxt_hwrm_port_qstats_ext(struct bnxt *bp) 7345 { 7346 struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr; 7347 struct hwrm_queue_pri2cos_qcfg_input req2 = {0}; 7348 struct hwrm_port_qstats_ext_input req = {0}; 7349 struct bnxt_pf_info *pf = &bp->pf; 7350 u32 tx_stat_size; 7351 int rc; 7352 7353 if (!(bp->flags & BNXT_FLAG_PORT_STATS_EXT)) 7354 return 0; 7355 7356 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_QSTATS_EXT, -1, -1); 7357 req.port_id = cpu_to_le16(pf->port_id); 7358 req.rx_stat_size = cpu_to_le16(sizeof(struct rx_port_stats_ext)); 7359 req.rx_stat_host_addr = cpu_to_le64(bp->hw_rx_port_stats_ext_map); 7360 tx_stat_size = bp->hw_tx_port_stats_ext ? 7361 sizeof(*bp->hw_tx_port_stats_ext) : 0; 7362 req.tx_stat_size = cpu_to_le16(tx_stat_size); 7363 req.tx_stat_host_addr = cpu_to_le64(bp->hw_tx_port_stats_ext_map); 7364 mutex_lock(&bp->hwrm_cmd_lock); 7365 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 7366 if (!rc) { 7367 bp->fw_rx_stats_ext_size = le16_to_cpu(resp->rx_stat_size) / 8; 7368 bp->fw_tx_stats_ext_size = tx_stat_size ? 7369 le16_to_cpu(resp->tx_stat_size) / 8 : 0; 7370 } else { 7371 bp->fw_rx_stats_ext_size = 0; 7372 bp->fw_tx_stats_ext_size = 0; 7373 } 7374 if (bp->fw_tx_stats_ext_size <= 7375 offsetof(struct tx_port_stats_ext, pfc_pri0_tx_duration_us) / 8) { 7376 mutex_unlock(&bp->hwrm_cmd_lock); 7377 bp->pri2cos_valid = 0; 7378 return rc; 7379 } 7380 7381 bnxt_hwrm_cmd_hdr_init(bp, &req2, HWRM_QUEUE_PRI2COS_QCFG, -1, -1); 7382 req2.flags = cpu_to_le32(QUEUE_PRI2COS_QCFG_REQ_FLAGS_IVLAN); 7383 7384 rc = _hwrm_send_message(bp, &req2, sizeof(req2), HWRM_CMD_TIMEOUT); 7385 if (!rc) { 7386 struct hwrm_queue_pri2cos_qcfg_output *resp2; 7387 u8 *pri2cos; 7388 int i, j; 7389 7390 resp2 = bp->hwrm_cmd_resp_addr; 7391 pri2cos = &resp2->pri0_cos_queue_id; 7392 for (i = 0; i < 8; i++) { 7393 u8 queue_id = pri2cos[i]; 7394 u8 queue_idx; 7395 7396 /* Per port queue IDs start from 0, 10, 20, etc */ 7397 queue_idx = queue_id % 10; 7398 if (queue_idx > BNXT_MAX_QUEUE) { 7399 bp->pri2cos_valid = false; 7400 goto qstats_done; 7401 } 7402 for (j = 0; j < bp->max_q; j++) { 7403 if (bp->q_ids[j] == queue_id) 7404 bp->pri2cos_idx[i] = queue_idx; 7405 } 7406 } 7407 bp->pri2cos_valid = 1; 7408 } 7409 qstats_done: 7410 mutex_unlock(&bp->hwrm_cmd_lock); 7411 return rc; 7412 } 7413 7414 static int bnxt_hwrm_pcie_qstats(struct bnxt *bp) 7415 { 7416 struct hwrm_pcie_qstats_input req = {0}; 7417 7418 if (!(bp->flags & BNXT_FLAG_PCIE_STATS)) 7419 return 0; 7420 7421 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PCIE_QSTATS, -1, -1); 7422 req.pcie_stat_size = cpu_to_le16(sizeof(struct pcie_ctx_hw_stats)); 7423 req.pcie_stat_host_addr = cpu_to_le64(bp->hw_pcie_stats_map); 7424 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 7425 } 7426 7427 static void bnxt_hwrm_free_tunnel_ports(struct bnxt *bp) 7428 { 7429 if (bp->vxlan_port_cnt) { 7430 bnxt_hwrm_tunnel_dst_port_free( 7431 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN); 7432 } 7433 bp->vxlan_port_cnt = 0; 7434 if (bp->nge_port_cnt) { 7435 bnxt_hwrm_tunnel_dst_port_free( 7436 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE); 7437 } 7438 bp->nge_port_cnt = 0; 7439 } 7440 7441 static int bnxt_set_tpa(struct bnxt *bp, bool set_tpa) 7442 { 7443 int rc, i; 7444 u32 tpa_flags = 0; 7445 7446 if (set_tpa) 7447 tpa_flags = bp->flags & BNXT_FLAG_TPA; 7448 else if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state)) 7449 return 0; 7450 for (i = 0; i < bp->nr_vnics; i++) { 7451 rc = bnxt_hwrm_vnic_set_tpa(bp, i, tpa_flags); 7452 if (rc) { 7453 netdev_err(bp->dev, "hwrm vnic set tpa failure rc for vnic %d: %x\n", 7454 i, rc); 7455 return rc; 7456 } 7457 } 7458 return 0; 7459 } 7460 7461 static void bnxt_hwrm_clear_vnic_rss(struct bnxt *bp) 7462 { 7463 int i; 7464 7465 for (i = 0; i < bp->nr_vnics; i++) 7466 bnxt_hwrm_vnic_set_rss(bp, i, false); 7467 } 7468 7469 static void bnxt_clear_vnic(struct bnxt *bp) 7470 { 7471 if (!bp->vnic_info) 7472 return; 7473 7474 bnxt_hwrm_clear_vnic_filter(bp); 7475 if (!(bp->flags & BNXT_FLAG_CHIP_P5)) { 7476 /* clear all RSS setting before free vnic ctx */ 7477 bnxt_hwrm_clear_vnic_rss(bp); 7478 bnxt_hwrm_vnic_ctx_free(bp); 7479 } 7480 /* before free the vnic, undo the vnic tpa settings */ 7481 if (bp->flags & BNXT_FLAG_TPA) 7482 bnxt_set_tpa(bp, false); 7483 bnxt_hwrm_vnic_free(bp); 7484 if (bp->flags & BNXT_FLAG_CHIP_P5) 7485 bnxt_hwrm_vnic_ctx_free(bp); 7486 } 7487 7488 static void bnxt_hwrm_resource_free(struct bnxt *bp, bool close_path, 7489 bool irq_re_init) 7490 { 7491 bnxt_clear_vnic(bp); 7492 bnxt_hwrm_ring_free(bp, close_path); 7493 bnxt_hwrm_ring_grp_free(bp); 7494 if (irq_re_init) { 7495 bnxt_hwrm_stat_ctx_free(bp); 7496 bnxt_hwrm_free_tunnel_ports(bp); 7497 } 7498 } 7499 7500 static int bnxt_hwrm_set_br_mode(struct bnxt *bp, u16 br_mode) 7501 { 7502 struct hwrm_func_cfg_input req = {0}; 7503 7504 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1); 7505 req.fid = cpu_to_le16(0xffff); 7506 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_EVB_MODE); 7507 if (br_mode == BRIDGE_MODE_VEB) 7508 req.evb_mode = FUNC_CFG_REQ_EVB_MODE_VEB; 7509 else if (br_mode == BRIDGE_MODE_VEPA) 7510 req.evb_mode = FUNC_CFG_REQ_EVB_MODE_VEPA; 7511 else 7512 return -EINVAL; 7513 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 7514 } 7515 7516 static int bnxt_hwrm_set_cache_line_size(struct bnxt *bp, int size) 7517 { 7518 struct hwrm_func_cfg_input req = {0}; 7519 7520 if (BNXT_VF(bp) || bp->hwrm_spec_code < 0x10803) 7521 return 0; 7522 7523 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1); 7524 req.fid = cpu_to_le16(0xffff); 7525 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_CACHE_LINESIZE); 7526 req.options = FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_64; 7527 if (size == 128) 7528 req.options = FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128; 7529 7530 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 7531 } 7532 7533 static int __bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id) 7534 { 7535 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 7536 int rc; 7537 7538 if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG) 7539 goto skip_rss_ctx; 7540 7541 /* allocate context for vnic */ 7542 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 0); 7543 if (rc) { 7544 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n", 7545 vnic_id, rc); 7546 goto vnic_setup_err; 7547 } 7548 bp->rsscos_nr_ctxs++; 7549 7550 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) { 7551 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 1); 7552 if (rc) { 7553 netdev_err(bp->dev, "hwrm vnic %d cos ctx alloc failure rc: %x\n", 7554 vnic_id, rc); 7555 goto vnic_setup_err; 7556 } 7557 bp->rsscos_nr_ctxs++; 7558 } 7559 7560 skip_rss_ctx: 7561 /* configure default vnic, ring grp */ 7562 rc = bnxt_hwrm_vnic_cfg(bp, vnic_id); 7563 if (rc) { 7564 netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n", 7565 vnic_id, rc); 7566 goto vnic_setup_err; 7567 } 7568 7569 /* Enable RSS hashing on vnic */ 7570 rc = bnxt_hwrm_vnic_set_rss(bp, vnic_id, true); 7571 if (rc) { 7572 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %x\n", 7573 vnic_id, rc); 7574 goto vnic_setup_err; 7575 } 7576 7577 if (bp->flags & BNXT_FLAG_AGG_RINGS) { 7578 rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id); 7579 if (rc) { 7580 netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n", 7581 vnic_id, rc); 7582 } 7583 } 7584 7585 vnic_setup_err: 7586 return rc; 7587 } 7588 7589 static int __bnxt_setup_vnic_p5(struct bnxt *bp, u16 vnic_id) 7590 { 7591 int rc, i, nr_ctxs; 7592 7593 nr_ctxs = DIV_ROUND_UP(bp->rx_nr_rings, 64); 7594 for (i = 0; i < nr_ctxs; i++) { 7595 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, i); 7596 if (rc) { 7597 netdev_err(bp->dev, "hwrm vnic %d ctx %d alloc failure rc: %x\n", 7598 vnic_id, i, rc); 7599 break; 7600 } 7601 bp->rsscos_nr_ctxs++; 7602 } 7603 if (i < nr_ctxs) 7604 return -ENOMEM; 7605 7606 rc = bnxt_hwrm_vnic_set_rss_p5(bp, vnic_id, true); 7607 if (rc) { 7608 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %d\n", 7609 vnic_id, rc); 7610 return rc; 7611 } 7612 rc = bnxt_hwrm_vnic_cfg(bp, vnic_id); 7613 if (rc) { 7614 netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n", 7615 vnic_id, rc); 7616 return rc; 7617 } 7618 if (bp->flags & BNXT_FLAG_AGG_RINGS) { 7619 rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id); 7620 if (rc) { 7621 netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n", 7622 vnic_id, rc); 7623 } 7624 } 7625 return rc; 7626 } 7627 7628 static int bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id) 7629 { 7630 if (bp->flags & BNXT_FLAG_CHIP_P5) 7631 return __bnxt_setup_vnic_p5(bp, vnic_id); 7632 else 7633 return __bnxt_setup_vnic(bp, vnic_id); 7634 } 7635 7636 static int bnxt_alloc_rfs_vnics(struct bnxt *bp) 7637 { 7638 #ifdef CONFIG_RFS_ACCEL 7639 int i, rc = 0; 7640 7641 if (bp->flags & BNXT_FLAG_CHIP_P5) 7642 return 0; 7643 7644 for (i = 0; i < bp->rx_nr_rings; i++) { 7645 struct bnxt_vnic_info *vnic; 7646 u16 vnic_id = i + 1; 7647 u16 ring_id = i; 7648 7649 if (vnic_id >= bp->nr_vnics) 7650 break; 7651 7652 vnic = &bp->vnic_info[vnic_id]; 7653 vnic->flags |= BNXT_VNIC_RFS_FLAG; 7654 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP) 7655 vnic->flags |= BNXT_VNIC_RFS_NEW_RSS_FLAG; 7656 rc = bnxt_hwrm_vnic_alloc(bp, vnic_id, ring_id, 1); 7657 if (rc) { 7658 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n", 7659 vnic_id, rc); 7660 break; 7661 } 7662 rc = bnxt_setup_vnic(bp, vnic_id); 7663 if (rc) 7664 break; 7665 } 7666 return rc; 7667 #else 7668 return 0; 7669 #endif 7670 } 7671 7672 /* Allow PF and VF with default VLAN to be in promiscuous mode */ 7673 static bool bnxt_promisc_ok(struct bnxt *bp) 7674 { 7675 #ifdef CONFIG_BNXT_SRIOV 7676 if (BNXT_VF(bp) && !bp->vf.vlan) 7677 return false; 7678 #endif 7679 return true; 7680 } 7681 7682 static int bnxt_setup_nitroa0_vnic(struct bnxt *bp) 7683 { 7684 unsigned int rc = 0; 7685 7686 rc = bnxt_hwrm_vnic_alloc(bp, 1, bp->rx_nr_rings - 1, 1); 7687 if (rc) { 7688 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n", 7689 rc); 7690 return rc; 7691 } 7692 7693 rc = bnxt_hwrm_vnic_cfg(bp, 1); 7694 if (rc) { 7695 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n", 7696 rc); 7697 return rc; 7698 } 7699 return rc; 7700 } 7701 7702 static int bnxt_cfg_rx_mode(struct bnxt *); 7703 static bool bnxt_mc_list_updated(struct bnxt *, u32 *); 7704 7705 static int bnxt_init_chip(struct bnxt *bp, bool irq_re_init) 7706 { 7707 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 7708 int rc = 0; 7709 unsigned int rx_nr_rings = bp->rx_nr_rings; 7710 7711 if (irq_re_init) { 7712 rc = bnxt_hwrm_stat_ctx_alloc(bp); 7713 if (rc) { 7714 netdev_err(bp->dev, "hwrm stat ctx alloc failure rc: %x\n", 7715 rc); 7716 goto err_out; 7717 } 7718 } 7719 7720 rc = bnxt_hwrm_ring_alloc(bp); 7721 if (rc) { 7722 netdev_err(bp->dev, "hwrm ring alloc failure rc: %x\n", rc); 7723 goto err_out; 7724 } 7725 7726 rc = bnxt_hwrm_ring_grp_alloc(bp); 7727 if (rc) { 7728 netdev_err(bp->dev, "hwrm_ring_grp alloc failure: %x\n", rc); 7729 goto err_out; 7730 } 7731 7732 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 7733 rx_nr_rings--; 7734 7735 /* default vnic 0 */ 7736 rc = bnxt_hwrm_vnic_alloc(bp, 0, 0, rx_nr_rings); 7737 if (rc) { 7738 netdev_err(bp->dev, "hwrm vnic alloc failure rc: %x\n", rc); 7739 goto err_out; 7740 } 7741 7742 rc = bnxt_setup_vnic(bp, 0); 7743 if (rc) 7744 goto err_out; 7745 7746 if (bp->flags & BNXT_FLAG_RFS) { 7747 rc = bnxt_alloc_rfs_vnics(bp); 7748 if (rc) 7749 goto err_out; 7750 } 7751 7752 if (bp->flags & BNXT_FLAG_TPA) { 7753 rc = bnxt_set_tpa(bp, true); 7754 if (rc) 7755 goto err_out; 7756 } 7757 7758 if (BNXT_VF(bp)) 7759 bnxt_update_vf_mac(bp); 7760 7761 /* Filter for default vnic 0 */ 7762 rc = bnxt_hwrm_set_vnic_filter(bp, 0, 0, bp->dev->dev_addr); 7763 if (rc) { 7764 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n", rc); 7765 goto err_out; 7766 } 7767 vnic->uc_filter_count = 1; 7768 7769 vnic->rx_mask = 0; 7770 if (bp->dev->flags & IFF_BROADCAST) 7771 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_BCAST; 7772 7773 if ((bp->dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp)) 7774 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS; 7775 7776 if (bp->dev->flags & IFF_ALLMULTI) { 7777 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST; 7778 vnic->mc_list_count = 0; 7779 } else { 7780 u32 mask = 0; 7781 7782 bnxt_mc_list_updated(bp, &mask); 7783 vnic->rx_mask |= mask; 7784 } 7785 7786 rc = bnxt_cfg_rx_mode(bp); 7787 if (rc) 7788 goto err_out; 7789 7790 rc = bnxt_hwrm_set_coal(bp); 7791 if (rc) 7792 netdev_warn(bp->dev, "HWRM set coalescing failure rc: %x\n", 7793 rc); 7794 7795 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) { 7796 rc = bnxt_setup_nitroa0_vnic(bp); 7797 if (rc) 7798 netdev_err(bp->dev, "Special vnic setup failure for NS2 A0 rc: %x\n", 7799 rc); 7800 } 7801 7802 if (BNXT_VF(bp)) { 7803 bnxt_hwrm_func_qcfg(bp); 7804 netdev_update_features(bp->dev); 7805 } 7806 7807 return 0; 7808 7809 err_out: 7810 bnxt_hwrm_resource_free(bp, 0, true); 7811 7812 return rc; 7813 } 7814 7815 static int bnxt_shutdown_nic(struct bnxt *bp, bool irq_re_init) 7816 { 7817 bnxt_hwrm_resource_free(bp, 1, irq_re_init); 7818 return 0; 7819 } 7820 7821 static int bnxt_init_nic(struct bnxt *bp, bool irq_re_init) 7822 { 7823 bnxt_init_cp_rings(bp); 7824 bnxt_init_rx_rings(bp); 7825 bnxt_init_tx_rings(bp); 7826 bnxt_init_ring_grps(bp, irq_re_init); 7827 bnxt_init_vnics(bp); 7828 7829 return bnxt_init_chip(bp, irq_re_init); 7830 } 7831 7832 static int bnxt_set_real_num_queues(struct bnxt *bp) 7833 { 7834 int rc; 7835 struct net_device *dev = bp->dev; 7836 7837 rc = netif_set_real_num_tx_queues(dev, bp->tx_nr_rings - 7838 bp->tx_nr_rings_xdp); 7839 if (rc) 7840 return rc; 7841 7842 rc = netif_set_real_num_rx_queues(dev, bp->rx_nr_rings); 7843 if (rc) 7844 return rc; 7845 7846 #ifdef CONFIG_RFS_ACCEL 7847 if (bp->flags & BNXT_FLAG_RFS) 7848 dev->rx_cpu_rmap = alloc_irq_cpu_rmap(bp->rx_nr_rings); 7849 #endif 7850 7851 return rc; 7852 } 7853 7854 static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max, 7855 bool shared) 7856 { 7857 int _rx = *rx, _tx = *tx; 7858 7859 if (shared) { 7860 *rx = min_t(int, _rx, max); 7861 *tx = min_t(int, _tx, max); 7862 } else { 7863 if (max < 2) 7864 return -ENOMEM; 7865 7866 while (_rx + _tx > max) { 7867 if (_rx > _tx && _rx > 1) 7868 _rx--; 7869 else if (_tx > 1) 7870 _tx--; 7871 } 7872 *rx = _rx; 7873 *tx = _tx; 7874 } 7875 return 0; 7876 } 7877 7878 static void bnxt_setup_msix(struct bnxt *bp) 7879 { 7880 const int len = sizeof(bp->irq_tbl[0].name); 7881 struct net_device *dev = bp->dev; 7882 int tcs, i; 7883 7884 tcs = netdev_get_num_tc(dev); 7885 if (tcs) { 7886 int i, off, count; 7887 7888 for (i = 0; i < tcs; i++) { 7889 count = bp->tx_nr_rings_per_tc; 7890 off = i * count; 7891 netdev_set_tc_queue(dev, i, count, off); 7892 } 7893 } 7894 7895 for (i = 0; i < bp->cp_nr_rings; i++) { 7896 int map_idx = bnxt_cp_num_to_irq_num(bp, i); 7897 char *attr; 7898 7899 if (bp->flags & BNXT_FLAG_SHARED_RINGS) 7900 attr = "TxRx"; 7901 else if (i < bp->rx_nr_rings) 7902 attr = "rx"; 7903 else 7904 attr = "tx"; 7905 7906 snprintf(bp->irq_tbl[map_idx].name, len, "%s-%s-%d", dev->name, 7907 attr, i); 7908 bp->irq_tbl[map_idx].handler = bnxt_msix; 7909 } 7910 } 7911 7912 static void bnxt_setup_inta(struct bnxt *bp) 7913 { 7914 const int len = sizeof(bp->irq_tbl[0].name); 7915 7916 if (netdev_get_num_tc(bp->dev)) 7917 netdev_reset_tc(bp->dev); 7918 7919 snprintf(bp->irq_tbl[0].name, len, "%s-%s-%d", bp->dev->name, "TxRx", 7920 0); 7921 bp->irq_tbl[0].handler = bnxt_inta; 7922 } 7923 7924 static int bnxt_setup_int_mode(struct bnxt *bp) 7925 { 7926 int rc; 7927 7928 if (bp->flags & BNXT_FLAG_USING_MSIX) 7929 bnxt_setup_msix(bp); 7930 else 7931 bnxt_setup_inta(bp); 7932 7933 rc = bnxt_set_real_num_queues(bp); 7934 return rc; 7935 } 7936 7937 #ifdef CONFIG_RFS_ACCEL 7938 static unsigned int bnxt_get_max_func_rss_ctxs(struct bnxt *bp) 7939 { 7940 return bp->hw_resc.max_rsscos_ctxs; 7941 } 7942 7943 static unsigned int bnxt_get_max_func_vnics(struct bnxt *bp) 7944 { 7945 return bp->hw_resc.max_vnics; 7946 } 7947 #endif 7948 7949 unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt *bp) 7950 { 7951 return bp->hw_resc.max_stat_ctxs; 7952 } 7953 7954 unsigned int bnxt_get_max_func_cp_rings(struct bnxt *bp) 7955 { 7956 return bp->hw_resc.max_cp_rings; 7957 } 7958 7959 static unsigned int bnxt_get_max_func_cp_rings_for_en(struct bnxt *bp) 7960 { 7961 unsigned int cp = bp->hw_resc.max_cp_rings; 7962 7963 if (!(bp->flags & BNXT_FLAG_CHIP_P5)) 7964 cp -= bnxt_get_ulp_msix_num(bp); 7965 7966 return cp; 7967 } 7968 7969 static unsigned int bnxt_get_max_func_irqs(struct bnxt *bp) 7970 { 7971 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 7972 7973 if (bp->flags & BNXT_FLAG_CHIP_P5) 7974 return min_t(unsigned int, hw_resc->max_irqs, hw_resc->max_nqs); 7975 7976 return min_t(unsigned int, hw_resc->max_irqs, hw_resc->max_cp_rings); 7977 } 7978 7979 static void bnxt_set_max_func_irqs(struct bnxt *bp, unsigned int max_irqs) 7980 { 7981 bp->hw_resc.max_irqs = max_irqs; 7982 } 7983 7984 unsigned int bnxt_get_avail_cp_rings_for_en(struct bnxt *bp) 7985 { 7986 unsigned int cp; 7987 7988 cp = bnxt_get_max_func_cp_rings_for_en(bp); 7989 if (bp->flags & BNXT_FLAG_CHIP_P5) 7990 return cp - bp->rx_nr_rings - bp->tx_nr_rings; 7991 else 7992 return cp - bp->cp_nr_rings; 7993 } 7994 7995 unsigned int bnxt_get_avail_stat_ctxs_for_en(struct bnxt *bp) 7996 { 7997 return bnxt_get_max_func_stat_ctxs(bp) - bnxt_get_func_stat_ctxs(bp); 7998 } 7999 8000 int bnxt_get_avail_msix(struct bnxt *bp, int num) 8001 { 8002 int max_cp = bnxt_get_max_func_cp_rings(bp); 8003 int max_irq = bnxt_get_max_func_irqs(bp); 8004 int total_req = bp->cp_nr_rings + num; 8005 int max_idx, avail_msix; 8006 8007 max_idx = bp->total_irqs; 8008 if (!(bp->flags & BNXT_FLAG_CHIP_P5)) 8009 max_idx = min_t(int, bp->total_irqs, max_cp); 8010 avail_msix = max_idx - bp->cp_nr_rings; 8011 if (!BNXT_NEW_RM(bp) || avail_msix >= num) 8012 return avail_msix; 8013 8014 if (max_irq < total_req) { 8015 num = max_irq - bp->cp_nr_rings; 8016 if (num <= 0) 8017 return 0; 8018 } 8019 return num; 8020 } 8021 8022 static int bnxt_get_num_msix(struct bnxt *bp) 8023 { 8024 if (!BNXT_NEW_RM(bp)) 8025 return bnxt_get_max_func_irqs(bp); 8026 8027 return bnxt_nq_rings_in_use(bp); 8028 } 8029 8030 static int bnxt_init_msix(struct bnxt *bp) 8031 { 8032 int i, total_vecs, max, rc = 0, min = 1, ulp_msix; 8033 struct msix_entry *msix_ent; 8034 8035 total_vecs = bnxt_get_num_msix(bp); 8036 max = bnxt_get_max_func_irqs(bp); 8037 if (total_vecs > max) 8038 total_vecs = max; 8039 8040 if (!total_vecs) 8041 return 0; 8042 8043 msix_ent = kcalloc(total_vecs, sizeof(struct msix_entry), GFP_KERNEL); 8044 if (!msix_ent) 8045 return -ENOMEM; 8046 8047 for (i = 0; i < total_vecs; i++) { 8048 msix_ent[i].entry = i; 8049 msix_ent[i].vector = 0; 8050 } 8051 8052 if (!(bp->flags & BNXT_FLAG_SHARED_RINGS)) 8053 min = 2; 8054 8055 total_vecs = pci_enable_msix_range(bp->pdev, msix_ent, min, total_vecs); 8056 ulp_msix = bnxt_get_ulp_msix_num(bp); 8057 if (total_vecs < 0 || total_vecs < ulp_msix) { 8058 rc = -ENODEV; 8059 goto msix_setup_exit; 8060 } 8061 8062 bp->irq_tbl = kcalloc(total_vecs, sizeof(struct bnxt_irq), GFP_KERNEL); 8063 if (bp->irq_tbl) { 8064 for (i = 0; i < total_vecs; i++) 8065 bp->irq_tbl[i].vector = msix_ent[i].vector; 8066 8067 bp->total_irqs = total_vecs; 8068 /* Trim rings based upon num of vectors allocated */ 8069 rc = bnxt_trim_rings(bp, &bp->rx_nr_rings, &bp->tx_nr_rings, 8070 total_vecs - ulp_msix, min == 1); 8071 if (rc) 8072 goto msix_setup_exit; 8073 8074 bp->cp_nr_rings = (min == 1) ? 8075 max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) : 8076 bp->tx_nr_rings + bp->rx_nr_rings; 8077 8078 } else { 8079 rc = -ENOMEM; 8080 goto msix_setup_exit; 8081 } 8082 bp->flags |= BNXT_FLAG_USING_MSIX; 8083 kfree(msix_ent); 8084 return 0; 8085 8086 msix_setup_exit: 8087 netdev_err(bp->dev, "bnxt_init_msix err: %x\n", rc); 8088 kfree(bp->irq_tbl); 8089 bp->irq_tbl = NULL; 8090 pci_disable_msix(bp->pdev); 8091 kfree(msix_ent); 8092 return rc; 8093 } 8094 8095 static int bnxt_init_inta(struct bnxt *bp) 8096 { 8097 bp->irq_tbl = kcalloc(1, sizeof(struct bnxt_irq), GFP_KERNEL); 8098 if (!bp->irq_tbl) 8099 return -ENOMEM; 8100 8101 bp->total_irqs = 1; 8102 bp->rx_nr_rings = 1; 8103 bp->tx_nr_rings = 1; 8104 bp->cp_nr_rings = 1; 8105 bp->flags |= BNXT_FLAG_SHARED_RINGS; 8106 bp->irq_tbl[0].vector = bp->pdev->irq; 8107 return 0; 8108 } 8109 8110 static int bnxt_init_int_mode(struct bnxt *bp) 8111 { 8112 int rc = 0; 8113 8114 if (bp->flags & BNXT_FLAG_MSIX_CAP) 8115 rc = bnxt_init_msix(bp); 8116 8117 if (!(bp->flags & BNXT_FLAG_USING_MSIX) && BNXT_PF(bp)) { 8118 /* fallback to INTA */ 8119 rc = bnxt_init_inta(bp); 8120 } 8121 return rc; 8122 } 8123 8124 static void bnxt_clear_int_mode(struct bnxt *bp) 8125 { 8126 if (bp->flags & BNXT_FLAG_USING_MSIX) 8127 pci_disable_msix(bp->pdev); 8128 8129 kfree(bp->irq_tbl); 8130 bp->irq_tbl = NULL; 8131 bp->flags &= ~BNXT_FLAG_USING_MSIX; 8132 } 8133 8134 int bnxt_reserve_rings(struct bnxt *bp, bool irq_re_init) 8135 { 8136 int tcs = netdev_get_num_tc(bp->dev); 8137 bool irq_cleared = false; 8138 int rc; 8139 8140 if (!bnxt_need_reserve_rings(bp)) 8141 return 0; 8142 8143 if (irq_re_init && BNXT_NEW_RM(bp) && 8144 bnxt_get_num_msix(bp) != bp->total_irqs) { 8145 bnxt_ulp_irq_stop(bp); 8146 bnxt_clear_int_mode(bp); 8147 irq_cleared = true; 8148 } 8149 rc = __bnxt_reserve_rings(bp); 8150 if (irq_cleared) { 8151 if (!rc) 8152 rc = bnxt_init_int_mode(bp); 8153 bnxt_ulp_irq_restart(bp, rc); 8154 } 8155 if (rc) { 8156 netdev_err(bp->dev, "ring reservation/IRQ init failure rc: %d\n", rc); 8157 return rc; 8158 } 8159 if (tcs && (bp->tx_nr_rings_per_tc * tcs != bp->tx_nr_rings)) { 8160 netdev_err(bp->dev, "tx ring reservation failure\n"); 8161 netdev_reset_tc(bp->dev); 8162 bp->tx_nr_rings_per_tc = bp->tx_nr_rings; 8163 return -ENOMEM; 8164 } 8165 return 0; 8166 } 8167 8168 static void bnxt_free_irq(struct bnxt *bp) 8169 { 8170 struct bnxt_irq *irq; 8171 int i; 8172 8173 #ifdef CONFIG_RFS_ACCEL 8174 free_irq_cpu_rmap(bp->dev->rx_cpu_rmap); 8175 bp->dev->rx_cpu_rmap = NULL; 8176 #endif 8177 if (!bp->irq_tbl || !bp->bnapi) 8178 return; 8179 8180 for (i = 0; i < bp->cp_nr_rings; i++) { 8181 int map_idx = bnxt_cp_num_to_irq_num(bp, i); 8182 8183 irq = &bp->irq_tbl[map_idx]; 8184 if (irq->requested) { 8185 if (irq->have_cpumask) { 8186 irq_set_affinity_hint(irq->vector, NULL); 8187 free_cpumask_var(irq->cpu_mask); 8188 irq->have_cpumask = 0; 8189 } 8190 free_irq(irq->vector, bp->bnapi[i]); 8191 } 8192 8193 irq->requested = 0; 8194 } 8195 } 8196 8197 static int bnxt_request_irq(struct bnxt *bp) 8198 { 8199 int i, j, rc = 0; 8200 unsigned long flags = 0; 8201 #ifdef CONFIG_RFS_ACCEL 8202 struct cpu_rmap *rmap; 8203 #endif 8204 8205 rc = bnxt_setup_int_mode(bp); 8206 if (rc) { 8207 netdev_err(bp->dev, "bnxt_setup_int_mode err: %x\n", 8208 rc); 8209 return rc; 8210 } 8211 #ifdef CONFIG_RFS_ACCEL 8212 rmap = bp->dev->rx_cpu_rmap; 8213 #endif 8214 if (!(bp->flags & BNXT_FLAG_USING_MSIX)) 8215 flags = IRQF_SHARED; 8216 8217 for (i = 0, j = 0; i < bp->cp_nr_rings; i++) { 8218 int map_idx = bnxt_cp_num_to_irq_num(bp, i); 8219 struct bnxt_irq *irq = &bp->irq_tbl[map_idx]; 8220 8221 #ifdef CONFIG_RFS_ACCEL 8222 if (rmap && bp->bnapi[i]->rx_ring) { 8223 rc = irq_cpu_rmap_add(rmap, irq->vector); 8224 if (rc) 8225 netdev_warn(bp->dev, "failed adding irq rmap for ring %d\n", 8226 j); 8227 j++; 8228 } 8229 #endif 8230 rc = request_irq(irq->vector, irq->handler, flags, irq->name, 8231 bp->bnapi[i]); 8232 if (rc) 8233 break; 8234 8235 irq->requested = 1; 8236 8237 if (zalloc_cpumask_var(&irq->cpu_mask, GFP_KERNEL)) { 8238 int numa_node = dev_to_node(&bp->pdev->dev); 8239 8240 irq->have_cpumask = 1; 8241 cpumask_set_cpu(cpumask_local_spread(i, numa_node), 8242 irq->cpu_mask); 8243 rc = irq_set_affinity_hint(irq->vector, irq->cpu_mask); 8244 if (rc) { 8245 netdev_warn(bp->dev, 8246 "Set affinity failed, IRQ = %d\n", 8247 irq->vector); 8248 break; 8249 } 8250 } 8251 } 8252 return rc; 8253 } 8254 8255 static void bnxt_del_napi(struct bnxt *bp) 8256 { 8257 int i; 8258 8259 if (!bp->bnapi) 8260 return; 8261 8262 for (i = 0; i < bp->cp_nr_rings; i++) { 8263 struct bnxt_napi *bnapi = bp->bnapi[i]; 8264 8265 napi_hash_del(&bnapi->napi); 8266 netif_napi_del(&bnapi->napi); 8267 } 8268 /* We called napi_hash_del() before netif_napi_del(), we need 8269 * to respect an RCU grace period before freeing napi structures. 8270 */ 8271 synchronize_net(); 8272 } 8273 8274 static void bnxt_init_napi(struct bnxt *bp) 8275 { 8276 int i; 8277 unsigned int cp_nr_rings = bp->cp_nr_rings; 8278 struct bnxt_napi *bnapi; 8279 8280 if (bp->flags & BNXT_FLAG_USING_MSIX) { 8281 int (*poll_fn)(struct napi_struct *, int) = bnxt_poll; 8282 8283 if (bp->flags & BNXT_FLAG_CHIP_P5) 8284 poll_fn = bnxt_poll_p5; 8285 else if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 8286 cp_nr_rings--; 8287 for (i = 0; i < cp_nr_rings; i++) { 8288 bnapi = bp->bnapi[i]; 8289 netif_napi_add(bp->dev, &bnapi->napi, poll_fn, 64); 8290 } 8291 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) { 8292 bnapi = bp->bnapi[cp_nr_rings]; 8293 netif_napi_add(bp->dev, &bnapi->napi, 8294 bnxt_poll_nitroa0, 64); 8295 } 8296 } else { 8297 bnapi = bp->bnapi[0]; 8298 netif_napi_add(bp->dev, &bnapi->napi, bnxt_poll, 64); 8299 } 8300 } 8301 8302 static void bnxt_disable_napi(struct bnxt *bp) 8303 { 8304 int i; 8305 8306 if (!bp->bnapi) 8307 return; 8308 8309 for (i = 0; i < bp->cp_nr_rings; i++) { 8310 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring; 8311 8312 if (bp->bnapi[i]->rx_ring) 8313 cancel_work_sync(&cpr->dim.work); 8314 8315 napi_disable(&bp->bnapi[i]->napi); 8316 } 8317 } 8318 8319 static void bnxt_enable_napi(struct bnxt *bp) 8320 { 8321 int i; 8322 8323 for (i = 0; i < bp->cp_nr_rings; i++) { 8324 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring; 8325 bp->bnapi[i]->in_reset = false; 8326 8327 if (bp->bnapi[i]->rx_ring) { 8328 INIT_WORK(&cpr->dim.work, bnxt_dim_work); 8329 cpr->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE; 8330 } 8331 napi_enable(&bp->bnapi[i]->napi); 8332 } 8333 } 8334 8335 void bnxt_tx_disable(struct bnxt *bp) 8336 { 8337 int i; 8338 struct bnxt_tx_ring_info *txr; 8339 8340 if (bp->tx_ring) { 8341 for (i = 0; i < bp->tx_nr_rings; i++) { 8342 txr = &bp->tx_ring[i]; 8343 txr->dev_state = BNXT_DEV_STATE_CLOSING; 8344 } 8345 } 8346 /* Stop all TX queues */ 8347 netif_tx_disable(bp->dev); 8348 netif_carrier_off(bp->dev); 8349 } 8350 8351 void bnxt_tx_enable(struct bnxt *bp) 8352 { 8353 int i; 8354 struct bnxt_tx_ring_info *txr; 8355 8356 for (i = 0; i < bp->tx_nr_rings; i++) { 8357 txr = &bp->tx_ring[i]; 8358 txr->dev_state = 0; 8359 } 8360 netif_tx_wake_all_queues(bp->dev); 8361 if (bp->link_info.link_up) 8362 netif_carrier_on(bp->dev); 8363 } 8364 8365 static void bnxt_report_link(struct bnxt *bp) 8366 { 8367 if (bp->link_info.link_up) { 8368 const char *duplex; 8369 const char *flow_ctrl; 8370 u32 speed; 8371 u16 fec; 8372 8373 netif_carrier_on(bp->dev); 8374 if (bp->link_info.duplex == BNXT_LINK_DUPLEX_FULL) 8375 duplex = "full"; 8376 else 8377 duplex = "half"; 8378 if (bp->link_info.pause == BNXT_LINK_PAUSE_BOTH) 8379 flow_ctrl = "ON - receive & transmit"; 8380 else if (bp->link_info.pause == BNXT_LINK_PAUSE_TX) 8381 flow_ctrl = "ON - transmit"; 8382 else if (bp->link_info.pause == BNXT_LINK_PAUSE_RX) 8383 flow_ctrl = "ON - receive"; 8384 else 8385 flow_ctrl = "none"; 8386 speed = bnxt_fw_to_ethtool_speed(bp->link_info.link_speed); 8387 netdev_info(bp->dev, "NIC Link is Up, %u Mbps %s duplex, Flow control: %s\n", 8388 speed, duplex, flow_ctrl); 8389 if (bp->flags & BNXT_FLAG_EEE_CAP) 8390 netdev_info(bp->dev, "EEE is %s\n", 8391 bp->eee.eee_active ? "active" : 8392 "not active"); 8393 fec = bp->link_info.fec_cfg; 8394 if (!(fec & PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED)) 8395 netdev_info(bp->dev, "FEC autoneg %s encodings: %s\n", 8396 (fec & BNXT_FEC_AUTONEG) ? "on" : "off", 8397 (fec & BNXT_FEC_ENC_BASE_R) ? "BaseR" : 8398 (fec & BNXT_FEC_ENC_RS) ? "RS" : "None"); 8399 } else { 8400 netif_carrier_off(bp->dev); 8401 netdev_err(bp->dev, "NIC Link is Down\n"); 8402 } 8403 } 8404 8405 static int bnxt_hwrm_phy_qcaps(struct bnxt *bp) 8406 { 8407 int rc = 0; 8408 struct hwrm_port_phy_qcaps_input req = {0}; 8409 struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr; 8410 struct bnxt_link_info *link_info = &bp->link_info; 8411 8412 bp->flags &= ~BNXT_FLAG_EEE_CAP; 8413 if (bp->test_info) 8414 bp->test_info->flags &= ~(BNXT_TEST_FL_EXT_LPBK | 8415 BNXT_TEST_FL_AN_PHY_LPBK); 8416 if (bp->hwrm_spec_code < 0x10201) 8417 return 0; 8418 8419 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCAPS, -1, -1); 8420 8421 mutex_lock(&bp->hwrm_cmd_lock); 8422 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 8423 if (rc) 8424 goto hwrm_phy_qcaps_exit; 8425 8426 if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED) { 8427 struct ethtool_eee *eee = &bp->eee; 8428 u16 fw_speeds = le16_to_cpu(resp->supported_speeds_eee_mode); 8429 8430 bp->flags |= BNXT_FLAG_EEE_CAP; 8431 eee->supported = _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0); 8432 bp->lpi_tmr_lo = le32_to_cpu(resp->tx_lpi_timer_low) & 8433 PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK; 8434 bp->lpi_tmr_hi = le32_to_cpu(resp->valid_tx_lpi_timer_high) & 8435 PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK; 8436 } 8437 if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_EXTERNAL_LPBK_SUPPORTED) { 8438 if (bp->test_info) 8439 bp->test_info->flags |= BNXT_TEST_FL_EXT_LPBK; 8440 } 8441 if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_AUTONEG_LPBK_SUPPORTED) { 8442 if (bp->test_info) 8443 bp->test_info->flags |= BNXT_TEST_FL_AN_PHY_LPBK; 8444 } 8445 if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_SHARED_PHY_CFG_SUPPORTED) { 8446 if (BNXT_PF(bp)) 8447 bp->fw_cap |= BNXT_FW_CAP_SHARED_PORT_CFG; 8448 } 8449 if (resp->supported_speeds_auto_mode) 8450 link_info->support_auto_speeds = 8451 le16_to_cpu(resp->supported_speeds_auto_mode); 8452 8453 bp->port_count = resp->port_cnt; 8454 8455 hwrm_phy_qcaps_exit: 8456 mutex_unlock(&bp->hwrm_cmd_lock); 8457 return rc; 8458 } 8459 8460 static int bnxt_update_link(struct bnxt *bp, bool chng_link_state) 8461 { 8462 int rc = 0; 8463 struct bnxt_link_info *link_info = &bp->link_info; 8464 struct hwrm_port_phy_qcfg_input req = {0}; 8465 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr; 8466 u8 link_up = link_info->link_up; 8467 u16 diff; 8468 8469 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCFG, -1, -1); 8470 8471 mutex_lock(&bp->hwrm_cmd_lock); 8472 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 8473 if (rc) { 8474 mutex_unlock(&bp->hwrm_cmd_lock); 8475 return rc; 8476 } 8477 8478 memcpy(&link_info->phy_qcfg_resp, resp, sizeof(*resp)); 8479 link_info->phy_link_status = resp->link; 8480 link_info->duplex = resp->duplex_cfg; 8481 if (bp->hwrm_spec_code >= 0x10800) 8482 link_info->duplex = resp->duplex_state; 8483 link_info->pause = resp->pause; 8484 link_info->auto_mode = resp->auto_mode; 8485 link_info->auto_pause_setting = resp->auto_pause; 8486 link_info->lp_pause = resp->link_partner_adv_pause; 8487 link_info->force_pause_setting = resp->force_pause; 8488 link_info->duplex_setting = resp->duplex_cfg; 8489 if (link_info->phy_link_status == BNXT_LINK_LINK) 8490 link_info->link_speed = le16_to_cpu(resp->link_speed); 8491 else 8492 link_info->link_speed = 0; 8493 link_info->force_link_speed = le16_to_cpu(resp->force_link_speed); 8494 link_info->support_speeds = le16_to_cpu(resp->support_speeds); 8495 link_info->auto_link_speeds = le16_to_cpu(resp->auto_link_speed_mask); 8496 link_info->lp_auto_link_speeds = 8497 le16_to_cpu(resp->link_partner_adv_speeds); 8498 link_info->preemphasis = le32_to_cpu(resp->preemphasis); 8499 link_info->phy_ver[0] = resp->phy_maj; 8500 link_info->phy_ver[1] = resp->phy_min; 8501 link_info->phy_ver[2] = resp->phy_bld; 8502 link_info->media_type = resp->media_type; 8503 link_info->phy_type = resp->phy_type; 8504 link_info->transceiver = resp->xcvr_pkg_type; 8505 link_info->phy_addr = resp->eee_config_phy_addr & 8506 PORT_PHY_QCFG_RESP_PHY_ADDR_MASK; 8507 link_info->module_status = resp->module_status; 8508 8509 if (bp->flags & BNXT_FLAG_EEE_CAP) { 8510 struct ethtool_eee *eee = &bp->eee; 8511 u16 fw_speeds; 8512 8513 eee->eee_active = 0; 8514 if (resp->eee_config_phy_addr & 8515 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE) { 8516 eee->eee_active = 1; 8517 fw_speeds = le16_to_cpu( 8518 resp->link_partner_adv_eee_link_speed_mask); 8519 eee->lp_advertised = 8520 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0); 8521 } 8522 8523 /* Pull initial EEE config */ 8524 if (!chng_link_state) { 8525 if (resp->eee_config_phy_addr & 8526 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED) 8527 eee->eee_enabled = 1; 8528 8529 fw_speeds = le16_to_cpu(resp->adv_eee_link_speed_mask); 8530 eee->advertised = 8531 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0); 8532 8533 if (resp->eee_config_phy_addr & 8534 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI) { 8535 __le32 tmr; 8536 8537 eee->tx_lpi_enabled = 1; 8538 tmr = resp->xcvr_identifier_type_tx_lpi_timer; 8539 eee->tx_lpi_timer = le32_to_cpu(tmr) & 8540 PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK; 8541 } 8542 } 8543 } 8544 8545 link_info->fec_cfg = PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED; 8546 if (bp->hwrm_spec_code >= 0x10504) 8547 link_info->fec_cfg = le16_to_cpu(resp->fec_cfg); 8548 8549 /* TODO: need to add more logic to report VF link */ 8550 if (chng_link_state) { 8551 if (link_info->phy_link_status == BNXT_LINK_LINK) 8552 link_info->link_up = 1; 8553 else 8554 link_info->link_up = 0; 8555 if (link_up != link_info->link_up) 8556 bnxt_report_link(bp); 8557 } else { 8558 /* alwasy link down if not require to update link state */ 8559 link_info->link_up = 0; 8560 } 8561 mutex_unlock(&bp->hwrm_cmd_lock); 8562 8563 if (!BNXT_PHY_CFG_ABLE(bp)) 8564 return 0; 8565 8566 diff = link_info->support_auto_speeds ^ link_info->advertising; 8567 if ((link_info->support_auto_speeds | diff) != 8568 link_info->support_auto_speeds) { 8569 /* An advertised speed is no longer supported, so we need to 8570 * update the advertisement settings. Caller holds RTNL 8571 * so we can modify link settings. 8572 */ 8573 link_info->advertising = link_info->support_auto_speeds; 8574 if (link_info->autoneg & BNXT_AUTONEG_SPEED) 8575 bnxt_hwrm_set_link_setting(bp, true, false); 8576 } 8577 return 0; 8578 } 8579 8580 static void bnxt_get_port_module_status(struct bnxt *bp) 8581 { 8582 struct bnxt_link_info *link_info = &bp->link_info; 8583 struct hwrm_port_phy_qcfg_output *resp = &link_info->phy_qcfg_resp; 8584 u8 module_status; 8585 8586 if (bnxt_update_link(bp, true)) 8587 return; 8588 8589 module_status = link_info->module_status; 8590 switch (module_status) { 8591 case PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX: 8592 case PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN: 8593 case PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG: 8594 netdev_warn(bp->dev, "Unqualified SFP+ module detected on port %d\n", 8595 bp->pf.port_id); 8596 if (bp->hwrm_spec_code >= 0x10201) { 8597 netdev_warn(bp->dev, "Module part number %s\n", 8598 resp->phy_vendor_partnumber); 8599 } 8600 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX) 8601 netdev_warn(bp->dev, "TX is disabled\n"); 8602 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN) 8603 netdev_warn(bp->dev, "SFP+ module is shutdown\n"); 8604 } 8605 } 8606 8607 static void 8608 bnxt_hwrm_set_pause_common(struct bnxt *bp, struct hwrm_port_phy_cfg_input *req) 8609 { 8610 if (bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) { 8611 if (bp->hwrm_spec_code >= 0x10201) 8612 req->auto_pause = 8613 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE; 8614 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX) 8615 req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX; 8616 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX) 8617 req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_TX; 8618 req->enables |= 8619 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE); 8620 } else { 8621 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX) 8622 req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_RX; 8623 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX) 8624 req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_TX; 8625 req->enables |= 8626 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE); 8627 if (bp->hwrm_spec_code >= 0x10201) { 8628 req->auto_pause = req->force_pause; 8629 req->enables |= cpu_to_le32( 8630 PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE); 8631 } 8632 } 8633 } 8634 8635 static void bnxt_hwrm_set_link_common(struct bnxt *bp, 8636 struct hwrm_port_phy_cfg_input *req) 8637 { 8638 u8 autoneg = bp->link_info.autoneg; 8639 u16 fw_link_speed = bp->link_info.req_link_speed; 8640 u16 advertising = bp->link_info.advertising; 8641 8642 if (autoneg & BNXT_AUTONEG_SPEED) { 8643 req->auto_mode |= 8644 PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK; 8645 8646 req->enables |= cpu_to_le32( 8647 PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK); 8648 req->auto_link_speed_mask = cpu_to_le16(advertising); 8649 8650 req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE); 8651 req->flags |= 8652 cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG); 8653 } else { 8654 req->force_link_speed = cpu_to_le16(fw_link_speed); 8655 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE); 8656 } 8657 8658 /* tell chimp that the setting takes effect immediately */ 8659 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESET_PHY); 8660 } 8661 8662 int bnxt_hwrm_set_pause(struct bnxt *bp) 8663 { 8664 struct hwrm_port_phy_cfg_input req = {0}; 8665 int rc; 8666 8667 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1); 8668 bnxt_hwrm_set_pause_common(bp, &req); 8669 8670 if ((bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) || 8671 bp->link_info.force_link_chng) 8672 bnxt_hwrm_set_link_common(bp, &req); 8673 8674 mutex_lock(&bp->hwrm_cmd_lock); 8675 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 8676 if (!rc && !(bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL)) { 8677 /* since changing of pause setting doesn't trigger any link 8678 * change event, the driver needs to update the current pause 8679 * result upon successfully return of the phy_cfg command 8680 */ 8681 bp->link_info.pause = 8682 bp->link_info.force_pause_setting = bp->link_info.req_flow_ctrl; 8683 bp->link_info.auto_pause_setting = 0; 8684 if (!bp->link_info.force_link_chng) 8685 bnxt_report_link(bp); 8686 } 8687 bp->link_info.force_link_chng = false; 8688 mutex_unlock(&bp->hwrm_cmd_lock); 8689 return rc; 8690 } 8691 8692 static void bnxt_hwrm_set_eee(struct bnxt *bp, 8693 struct hwrm_port_phy_cfg_input *req) 8694 { 8695 struct ethtool_eee *eee = &bp->eee; 8696 8697 if (eee->eee_enabled) { 8698 u16 eee_speeds; 8699 u32 flags = PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE; 8700 8701 if (eee->tx_lpi_enabled) 8702 flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE; 8703 else 8704 flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE; 8705 8706 req->flags |= cpu_to_le32(flags); 8707 eee_speeds = bnxt_get_fw_auto_link_speeds(eee->advertised); 8708 req->eee_link_speed_mask = cpu_to_le16(eee_speeds); 8709 req->tx_lpi_timer = cpu_to_le32(eee->tx_lpi_timer); 8710 } else { 8711 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE); 8712 } 8713 } 8714 8715 int bnxt_hwrm_set_link_setting(struct bnxt *bp, bool set_pause, bool set_eee) 8716 { 8717 struct hwrm_port_phy_cfg_input req = {0}; 8718 8719 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1); 8720 if (set_pause) 8721 bnxt_hwrm_set_pause_common(bp, &req); 8722 8723 bnxt_hwrm_set_link_common(bp, &req); 8724 8725 if (set_eee) 8726 bnxt_hwrm_set_eee(bp, &req); 8727 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 8728 } 8729 8730 static int bnxt_hwrm_shutdown_link(struct bnxt *bp) 8731 { 8732 struct hwrm_port_phy_cfg_input req = {0}; 8733 8734 if (!BNXT_SINGLE_PF(bp)) 8735 return 0; 8736 8737 if (pci_num_vf(bp->pdev)) 8738 return 0; 8739 8740 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1); 8741 req.flags = cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN); 8742 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 8743 } 8744 8745 static int bnxt_fw_init_one(struct bnxt *bp); 8746 8747 static int bnxt_hwrm_if_change(struct bnxt *bp, bool up) 8748 { 8749 struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr; 8750 struct hwrm_func_drv_if_change_input req = {0}; 8751 bool resc_reinit = false, fw_reset = false; 8752 u32 flags = 0; 8753 int rc; 8754 8755 if (!(bp->fw_cap & BNXT_FW_CAP_IF_CHANGE)) 8756 return 0; 8757 8758 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_IF_CHANGE, -1, -1); 8759 if (up) 8760 req.flags = cpu_to_le32(FUNC_DRV_IF_CHANGE_REQ_FLAGS_UP); 8761 mutex_lock(&bp->hwrm_cmd_lock); 8762 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 8763 if (!rc) 8764 flags = le32_to_cpu(resp->flags); 8765 mutex_unlock(&bp->hwrm_cmd_lock); 8766 if (rc) 8767 return rc; 8768 8769 if (!up) 8770 return 0; 8771 8772 if (flags & FUNC_DRV_IF_CHANGE_RESP_FLAGS_RESC_CHANGE) 8773 resc_reinit = true; 8774 if (flags & FUNC_DRV_IF_CHANGE_RESP_FLAGS_HOT_FW_RESET_DONE) 8775 fw_reset = true; 8776 8777 if (test_bit(BNXT_STATE_IN_FW_RESET, &bp->state) && !fw_reset) { 8778 netdev_err(bp->dev, "RESET_DONE not set during FW reset.\n"); 8779 return -ENODEV; 8780 } 8781 if (resc_reinit || fw_reset) { 8782 if (fw_reset) { 8783 if (!test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) 8784 bnxt_ulp_stop(bp); 8785 bnxt_free_ctx_mem(bp); 8786 kfree(bp->ctx); 8787 bp->ctx = NULL; 8788 bnxt_dcb_free(bp); 8789 rc = bnxt_fw_init_one(bp); 8790 if (rc) { 8791 set_bit(BNXT_STATE_ABORT_ERR, &bp->state); 8792 return rc; 8793 } 8794 bnxt_clear_int_mode(bp); 8795 rc = bnxt_init_int_mode(bp); 8796 if (rc) { 8797 netdev_err(bp->dev, "init int mode failed\n"); 8798 return rc; 8799 } 8800 set_bit(BNXT_STATE_FW_RESET_DET, &bp->state); 8801 } 8802 if (BNXT_NEW_RM(bp)) { 8803 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 8804 8805 rc = bnxt_hwrm_func_resc_qcaps(bp, true); 8806 hw_resc->resv_cp_rings = 0; 8807 hw_resc->resv_stat_ctxs = 0; 8808 hw_resc->resv_irqs = 0; 8809 hw_resc->resv_tx_rings = 0; 8810 hw_resc->resv_rx_rings = 0; 8811 hw_resc->resv_hw_ring_grps = 0; 8812 hw_resc->resv_vnics = 0; 8813 if (!fw_reset) { 8814 bp->tx_nr_rings = 0; 8815 bp->rx_nr_rings = 0; 8816 } 8817 } 8818 } 8819 return 0; 8820 } 8821 8822 static int bnxt_hwrm_port_led_qcaps(struct bnxt *bp) 8823 { 8824 struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr; 8825 struct hwrm_port_led_qcaps_input req = {0}; 8826 struct bnxt_pf_info *pf = &bp->pf; 8827 int rc; 8828 8829 bp->num_leds = 0; 8830 if (BNXT_VF(bp) || bp->hwrm_spec_code < 0x10601) 8831 return 0; 8832 8833 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_LED_QCAPS, -1, -1); 8834 req.port_id = cpu_to_le16(pf->port_id); 8835 mutex_lock(&bp->hwrm_cmd_lock); 8836 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 8837 if (rc) { 8838 mutex_unlock(&bp->hwrm_cmd_lock); 8839 return rc; 8840 } 8841 if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) { 8842 int i; 8843 8844 bp->num_leds = resp->num_leds; 8845 memcpy(bp->leds, &resp->led0_id, sizeof(bp->leds[0]) * 8846 bp->num_leds); 8847 for (i = 0; i < bp->num_leds; i++) { 8848 struct bnxt_led_info *led = &bp->leds[i]; 8849 __le16 caps = led->led_state_caps; 8850 8851 if (!led->led_group_id || 8852 !BNXT_LED_ALT_BLINK_CAP(caps)) { 8853 bp->num_leds = 0; 8854 break; 8855 } 8856 } 8857 } 8858 mutex_unlock(&bp->hwrm_cmd_lock); 8859 return 0; 8860 } 8861 8862 int bnxt_hwrm_alloc_wol_fltr(struct bnxt *bp) 8863 { 8864 struct hwrm_wol_filter_alloc_input req = {0}; 8865 struct hwrm_wol_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr; 8866 int rc; 8867 8868 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_ALLOC, -1, -1); 8869 req.port_id = cpu_to_le16(bp->pf.port_id); 8870 req.wol_type = WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT; 8871 req.enables = cpu_to_le32(WOL_FILTER_ALLOC_REQ_ENABLES_MAC_ADDRESS); 8872 memcpy(req.mac_address, bp->dev->dev_addr, ETH_ALEN); 8873 mutex_lock(&bp->hwrm_cmd_lock); 8874 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 8875 if (!rc) 8876 bp->wol_filter_id = resp->wol_filter_id; 8877 mutex_unlock(&bp->hwrm_cmd_lock); 8878 return rc; 8879 } 8880 8881 int bnxt_hwrm_free_wol_fltr(struct bnxt *bp) 8882 { 8883 struct hwrm_wol_filter_free_input req = {0}; 8884 8885 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_FREE, -1, -1); 8886 req.port_id = cpu_to_le16(bp->pf.port_id); 8887 req.enables = cpu_to_le32(WOL_FILTER_FREE_REQ_ENABLES_WOL_FILTER_ID); 8888 req.wol_filter_id = bp->wol_filter_id; 8889 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 8890 } 8891 8892 static u16 bnxt_hwrm_get_wol_fltrs(struct bnxt *bp, u16 handle) 8893 { 8894 struct hwrm_wol_filter_qcfg_input req = {0}; 8895 struct hwrm_wol_filter_qcfg_output *resp = bp->hwrm_cmd_resp_addr; 8896 u16 next_handle = 0; 8897 int rc; 8898 8899 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_QCFG, -1, -1); 8900 req.port_id = cpu_to_le16(bp->pf.port_id); 8901 req.handle = cpu_to_le16(handle); 8902 mutex_lock(&bp->hwrm_cmd_lock); 8903 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 8904 if (!rc) { 8905 next_handle = le16_to_cpu(resp->next_handle); 8906 if (next_handle != 0) { 8907 if (resp->wol_type == 8908 WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT) { 8909 bp->wol = 1; 8910 bp->wol_filter_id = resp->wol_filter_id; 8911 } 8912 } 8913 } 8914 mutex_unlock(&bp->hwrm_cmd_lock); 8915 return next_handle; 8916 } 8917 8918 static void bnxt_get_wol_settings(struct bnxt *bp) 8919 { 8920 u16 handle = 0; 8921 8922 bp->wol = 0; 8923 if (!BNXT_PF(bp) || !(bp->flags & BNXT_FLAG_WOL_CAP)) 8924 return; 8925 8926 do { 8927 handle = bnxt_hwrm_get_wol_fltrs(bp, handle); 8928 } while (handle && handle != 0xffff); 8929 } 8930 8931 #ifdef CONFIG_BNXT_HWMON 8932 static ssize_t bnxt_show_temp(struct device *dev, 8933 struct device_attribute *devattr, char *buf) 8934 { 8935 struct hwrm_temp_monitor_query_input req = {0}; 8936 struct hwrm_temp_monitor_query_output *resp; 8937 struct bnxt *bp = dev_get_drvdata(dev); 8938 u32 temp = 0; 8939 8940 resp = bp->hwrm_cmd_resp_addr; 8941 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TEMP_MONITOR_QUERY, -1, -1); 8942 mutex_lock(&bp->hwrm_cmd_lock); 8943 if (!_hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT)) 8944 temp = resp->temp * 1000; /* display millidegree */ 8945 mutex_unlock(&bp->hwrm_cmd_lock); 8946 8947 return sprintf(buf, "%u\n", temp); 8948 } 8949 static SENSOR_DEVICE_ATTR(temp1_input, 0444, bnxt_show_temp, NULL, 0); 8950 8951 static struct attribute *bnxt_attrs[] = { 8952 &sensor_dev_attr_temp1_input.dev_attr.attr, 8953 NULL 8954 }; 8955 ATTRIBUTE_GROUPS(bnxt); 8956 8957 static void bnxt_hwmon_close(struct bnxt *bp) 8958 { 8959 if (bp->hwmon_dev) { 8960 hwmon_device_unregister(bp->hwmon_dev); 8961 bp->hwmon_dev = NULL; 8962 } 8963 } 8964 8965 static void bnxt_hwmon_open(struct bnxt *bp) 8966 { 8967 struct pci_dev *pdev = bp->pdev; 8968 8969 if (bp->hwmon_dev) 8970 return; 8971 8972 bp->hwmon_dev = hwmon_device_register_with_groups(&pdev->dev, 8973 DRV_MODULE_NAME, bp, 8974 bnxt_groups); 8975 if (IS_ERR(bp->hwmon_dev)) { 8976 bp->hwmon_dev = NULL; 8977 dev_warn(&pdev->dev, "Cannot register hwmon device\n"); 8978 } 8979 } 8980 #else 8981 static void bnxt_hwmon_close(struct bnxt *bp) 8982 { 8983 } 8984 8985 static void bnxt_hwmon_open(struct bnxt *bp) 8986 { 8987 } 8988 #endif 8989 8990 static bool bnxt_eee_config_ok(struct bnxt *bp) 8991 { 8992 struct ethtool_eee *eee = &bp->eee; 8993 struct bnxt_link_info *link_info = &bp->link_info; 8994 8995 if (!(bp->flags & BNXT_FLAG_EEE_CAP)) 8996 return true; 8997 8998 if (eee->eee_enabled) { 8999 u32 advertising = 9000 _bnxt_fw_to_ethtool_adv_spds(link_info->advertising, 0); 9001 9002 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) { 9003 eee->eee_enabled = 0; 9004 return false; 9005 } 9006 if (eee->advertised & ~advertising) { 9007 eee->advertised = advertising & eee->supported; 9008 return false; 9009 } 9010 } 9011 return true; 9012 } 9013 9014 static int bnxt_update_phy_setting(struct bnxt *bp) 9015 { 9016 int rc; 9017 bool update_link = false; 9018 bool update_pause = false; 9019 bool update_eee = false; 9020 struct bnxt_link_info *link_info = &bp->link_info; 9021 9022 rc = bnxt_update_link(bp, true); 9023 if (rc) { 9024 netdev_err(bp->dev, "failed to update link (rc: %x)\n", 9025 rc); 9026 return rc; 9027 } 9028 if (!BNXT_SINGLE_PF(bp)) 9029 return 0; 9030 9031 if ((link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) && 9032 (link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH) != 9033 link_info->req_flow_ctrl) 9034 update_pause = true; 9035 if (!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) && 9036 link_info->force_pause_setting != link_info->req_flow_ctrl) 9037 update_pause = true; 9038 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) { 9039 if (BNXT_AUTO_MODE(link_info->auto_mode)) 9040 update_link = true; 9041 if (link_info->req_link_speed != link_info->force_link_speed) 9042 update_link = true; 9043 if (link_info->req_duplex != link_info->duplex_setting) 9044 update_link = true; 9045 } else { 9046 if (link_info->auto_mode == BNXT_LINK_AUTO_NONE) 9047 update_link = true; 9048 if (link_info->advertising != link_info->auto_link_speeds) 9049 update_link = true; 9050 } 9051 9052 /* The last close may have shutdown the link, so need to call 9053 * PHY_CFG to bring it back up. 9054 */ 9055 if (!bp->link_info.link_up) 9056 update_link = true; 9057 9058 if (!bnxt_eee_config_ok(bp)) 9059 update_eee = true; 9060 9061 if (update_link) 9062 rc = bnxt_hwrm_set_link_setting(bp, update_pause, update_eee); 9063 else if (update_pause) 9064 rc = bnxt_hwrm_set_pause(bp); 9065 if (rc) { 9066 netdev_err(bp->dev, "failed to update phy setting (rc: %x)\n", 9067 rc); 9068 return rc; 9069 } 9070 9071 return rc; 9072 } 9073 9074 /* Common routine to pre-map certain register block to different GRC window. 9075 * A PF has 16 4K windows and a VF has 4 4K windows. However, only 15 windows 9076 * in PF and 3 windows in VF that can be customized to map in different 9077 * register blocks. 9078 */ 9079 static void bnxt_preset_reg_win(struct bnxt *bp) 9080 { 9081 if (BNXT_PF(bp)) { 9082 /* CAG registers map to GRC window #4 */ 9083 writel(BNXT_CAG_REG_BASE, 9084 bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 12); 9085 } 9086 } 9087 9088 static int bnxt_init_dflt_ring_mode(struct bnxt *bp); 9089 9090 static int __bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init) 9091 { 9092 int rc = 0; 9093 9094 bnxt_preset_reg_win(bp); 9095 netif_carrier_off(bp->dev); 9096 if (irq_re_init) { 9097 /* Reserve rings now if none were reserved at driver probe. */ 9098 rc = bnxt_init_dflt_ring_mode(bp); 9099 if (rc) { 9100 netdev_err(bp->dev, "Failed to reserve default rings at open\n"); 9101 return rc; 9102 } 9103 } 9104 rc = bnxt_reserve_rings(bp, irq_re_init); 9105 if (rc) 9106 return rc; 9107 if ((bp->flags & BNXT_FLAG_RFS) && 9108 !(bp->flags & BNXT_FLAG_USING_MSIX)) { 9109 /* disable RFS if falling back to INTA */ 9110 bp->dev->hw_features &= ~NETIF_F_NTUPLE; 9111 bp->flags &= ~BNXT_FLAG_RFS; 9112 } 9113 9114 rc = bnxt_alloc_mem(bp, irq_re_init); 9115 if (rc) { 9116 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc); 9117 goto open_err_free_mem; 9118 } 9119 9120 if (irq_re_init) { 9121 bnxt_init_napi(bp); 9122 rc = bnxt_request_irq(bp); 9123 if (rc) { 9124 netdev_err(bp->dev, "bnxt_request_irq err: %x\n", rc); 9125 goto open_err_irq; 9126 } 9127 } 9128 9129 bnxt_enable_napi(bp); 9130 bnxt_debug_dev_init(bp); 9131 9132 rc = bnxt_init_nic(bp, irq_re_init); 9133 if (rc) { 9134 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc); 9135 goto open_err; 9136 } 9137 9138 if (link_re_init) { 9139 mutex_lock(&bp->link_lock); 9140 rc = bnxt_update_phy_setting(bp); 9141 mutex_unlock(&bp->link_lock); 9142 if (rc) { 9143 netdev_warn(bp->dev, "failed to update phy settings\n"); 9144 if (BNXT_SINGLE_PF(bp)) { 9145 bp->link_info.phy_retry = true; 9146 bp->link_info.phy_retry_expires = 9147 jiffies + 5 * HZ; 9148 } 9149 } 9150 } 9151 9152 if (irq_re_init) 9153 udp_tunnel_get_rx_info(bp->dev); 9154 9155 set_bit(BNXT_STATE_OPEN, &bp->state); 9156 bnxt_enable_int(bp); 9157 /* Enable TX queues */ 9158 bnxt_tx_enable(bp); 9159 mod_timer(&bp->timer, jiffies + bp->current_interval); 9160 /* Poll link status and check for SFP+ module status */ 9161 bnxt_get_port_module_status(bp); 9162 9163 /* VF-reps may need to be re-opened after the PF is re-opened */ 9164 if (BNXT_PF(bp)) 9165 bnxt_vf_reps_open(bp); 9166 return 0; 9167 9168 open_err: 9169 bnxt_debug_dev_exit(bp); 9170 bnxt_disable_napi(bp); 9171 9172 open_err_irq: 9173 bnxt_del_napi(bp); 9174 9175 open_err_free_mem: 9176 bnxt_free_skbs(bp); 9177 bnxt_free_irq(bp); 9178 bnxt_free_mem(bp, true); 9179 return rc; 9180 } 9181 9182 /* rtnl_lock held */ 9183 int bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init) 9184 { 9185 int rc = 0; 9186 9187 rc = __bnxt_open_nic(bp, irq_re_init, link_re_init); 9188 if (rc) { 9189 netdev_err(bp->dev, "nic open fail (rc: %x)\n", rc); 9190 dev_close(bp->dev); 9191 } 9192 return rc; 9193 } 9194 9195 /* rtnl_lock held, open the NIC half way by allocating all resources, but 9196 * NAPI, IRQ, and TX are not enabled. This is mainly used for offline 9197 * self tests. 9198 */ 9199 int bnxt_half_open_nic(struct bnxt *bp) 9200 { 9201 int rc = 0; 9202 9203 rc = bnxt_alloc_mem(bp, false); 9204 if (rc) { 9205 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc); 9206 goto half_open_err; 9207 } 9208 rc = bnxt_init_nic(bp, false); 9209 if (rc) { 9210 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc); 9211 goto half_open_err; 9212 } 9213 return 0; 9214 9215 half_open_err: 9216 bnxt_free_skbs(bp); 9217 bnxt_free_mem(bp, false); 9218 dev_close(bp->dev); 9219 return rc; 9220 } 9221 9222 /* rtnl_lock held, this call can only be made after a previous successful 9223 * call to bnxt_half_open_nic(). 9224 */ 9225 void bnxt_half_close_nic(struct bnxt *bp) 9226 { 9227 bnxt_hwrm_resource_free(bp, false, false); 9228 bnxt_free_skbs(bp); 9229 bnxt_free_mem(bp, false); 9230 } 9231 9232 static void bnxt_reenable_sriov(struct bnxt *bp) 9233 { 9234 if (BNXT_PF(bp)) { 9235 struct bnxt_pf_info *pf = &bp->pf; 9236 int n = pf->active_vfs; 9237 9238 if (n) 9239 bnxt_cfg_hw_sriov(bp, &n, true); 9240 } 9241 } 9242 9243 static int bnxt_open(struct net_device *dev) 9244 { 9245 struct bnxt *bp = netdev_priv(dev); 9246 int rc; 9247 9248 if (test_bit(BNXT_STATE_ABORT_ERR, &bp->state)) { 9249 netdev_err(bp->dev, "A previous firmware reset did not complete, aborting\n"); 9250 return -ENODEV; 9251 } 9252 9253 rc = bnxt_hwrm_if_change(bp, true); 9254 if (rc) 9255 return rc; 9256 rc = __bnxt_open_nic(bp, true, true); 9257 if (rc) { 9258 bnxt_hwrm_if_change(bp, false); 9259 } else { 9260 if (test_and_clear_bit(BNXT_STATE_FW_RESET_DET, &bp->state)) { 9261 if (!test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) { 9262 bnxt_ulp_start(bp, 0); 9263 bnxt_reenable_sriov(bp); 9264 } 9265 } 9266 bnxt_hwmon_open(bp); 9267 } 9268 9269 return rc; 9270 } 9271 9272 static bool bnxt_drv_busy(struct bnxt *bp) 9273 { 9274 return (test_bit(BNXT_STATE_IN_SP_TASK, &bp->state) || 9275 test_bit(BNXT_STATE_READ_STATS, &bp->state)); 9276 } 9277 9278 static void bnxt_get_ring_stats(struct bnxt *bp, 9279 struct rtnl_link_stats64 *stats); 9280 9281 static void __bnxt_close_nic(struct bnxt *bp, bool irq_re_init, 9282 bool link_re_init) 9283 { 9284 /* Close the VF-reps before closing PF */ 9285 if (BNXT_PF(bp)) 9286 bnxt_vf_reps_close(bp); 9287 9288 /* Change device state to avoid TX queue wake up's */ 9289 bnxt_tx_disable(bp); 9290 9291 clear_bit(BNXT_STATE_OPEN, &bp->state); 9292 smp_mb__after_atomic(); 9293 while (bnxt_drv_busy(bp)) 9294 msleep(20); 9295 9296 /* Flush rings and and disable interrupts */ 9297 bnxt_shutdown_nic(bp, irq_re_init); 9298 9299 /* TODO CHIMP_FW: Link/PHY related cleanup if (link_re_init) */ 9300 9301 bnxt_debug_dev_exit(bp); 9302 bnxt_disable_napi(bp); 9303 del_timer_sync(&bp->timer); 9304 bnxt_free_skbs(bp); 9305 9306 /* Save ring stats before shutdown */ 9307 if (bp->bnapi && irq_re_init) 9308 bnxt_get_ring_stats(bp, &bp->net_stats_prev); 9309 if (irq_re_init) { 9310 bnxt_free_irq(bp); 9311 bnxt_del_napi(bp); 9312 } 9313 bnxt_free_mem(bp, irq_re_init); 9314 } 9315 9316 int bnxt_close_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init) 9317 { 9318 int rc = 0; 9319 9320 if (test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) { 9321 /* If we get here, it means firmware reset is in progress 9322 * while we are trying to close. We can safely proceed with 9323 * the close because we are holding rtnl_lock(). Some firmware 9324 * messages may fail as we proceed to close. We set the 9325 * ABORT_ERR flag here so that the FW reset thread will later 9326 * abort when it gets the rtnl_lock() and sees the flag. 9327 */ 9328 netdev_warn(bp->dev, "FW reset in progress during close, FW reset will be aborted\n"); 9329 set_bit(BNXT_STATE_ABORT_ERR, &bp->state); 9330 } 9331 9332 #ifdef CONFIG_BNXT_SRIOV 9333 if (bp->sriov_cfg) { 9334 rc = wait_event_interruptible_timeout(bp->sriov_cfg_wait, 9335 !bp->sriov_cfg, 9336 BNXT_SRIOV_CFG_WAIT_TMO); 9337 if (rc) 9338 netdev_warn(bp->dev, "timeout waiting for SRIOV config operation to complete!\n"); 9339 } 9340 #endif 9341 __bnxt_close_nic(bp, irq_re_init, link_re_init); 9342 return rc; 9343 } 9344 9345 static int bnxt_close(struct net_device *dev) 9346 { 9347 struct bnxt *bp = netdev_priv(dev); 9348 9349 bnxt_hwmon_close(bp); 9350 bnxt_close_nic(bp, true, true); 9351 bnxt_hwrm_shutdown_link(bp); 9352 bnxt_hwrm_if_change(bp, false); 9353 return 0; 9354 } 9355 9356 static int bnxt_hwrm_port_phy_read(struct bnxt *bp, u16 phy_addr, u16 reg, 9357 u16 *val) 9358 { 9359 struct hwrm_port_phy_mdio_read_output *resp = bp->hwrm_cmd_resp_addr; 9360 struct hwrm_port_phy_mdio_read_input req = {0}; 9361 int rc; 9362 9363 if (bp->hwrm_spec_code < 0x10a00) 9364 return -EOPNOTSUPP; 9365 9366 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_MDIO_READ, -1, -1); 9367 req.port_id = cpu_to_le16(bp->pf.port_id); 9368 req.phy_addr = phy_addr; 9369 req.reg_addr = cpu_to_le16(reg & 0x1f); 9370 if (mdio_phy_id_is_c45(phy_addr)) { 9371 req.cl45_mdio = 1; 9372 req.phy_addr = mdio_phy_id_prtad(phy_addr); 9373 req.dev_addr = mdio_phy_id_devad(phy_addr); 9374 req.reg_addr = cpu_to_le16(reg); 9375 } 9376 9377 mutex_lock(&bp->hwrm_cmd_lock); 9378 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 9379 if (!rc) 9380 *val = le16_to_cpu(resp->reg_data); 9381 mutex_unlock(&bp->hwrm_cmd_lock); 9382 return rc; 9383 } 9384 9385 static int bnxt_hwrm_port_phy_write(struct bnxt *bp, u16 phy_addr, u16 reg, 9386 u16 val) 9387 { 9388 struct hwrm_port_phy_mdio_write_input req = {0}; 9389 9390 if (bp->hwrm_spec_code < 0x10a00) 9391 return -EOPNOTSUPP; 9392 9393 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_MDIO_WRITE, -1, -1); 9394 req.port_id = cpu_to_le16(bp->pf.port_id); 9395 req.phy_addr = phy_addr; 9396 req.reg_addr = cpu_to_le16(reg & 0x1f); 9397 if (mdio_phy_id_is_c45(phy_addr)) { 9398 req.cl45_mdio = 1; 9399 req.phy_addr = mdio_phy_id_prtad(phy_addr); 9400 req.dev_addr = mdio_phy_id_devad(phy_addr); 9401 req.reg_addr = cpu_to_le16(reg); 9402 } 9403 req.reg_data = cpu_to_le16(val); 9404 9405 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 9406 } 9407 9408 /* rtnl_lock held */ 9409 static int bnxt_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 9410 { 9411 struct mii_ioctl_data *mdio = if_mii(ifr); 9412 struct bnxt *bp = netdev_priv(dev); 9413 int rc; 9414 9415 switch (cmd) { 9416 case SIOCGMIIPHY: 9417 mdio->phy_id = bp->link_info.phy_addr; 9418 9419 /* fallthru */ 9420 case SIOCGMIIREG: { 9421 u16 mii_regval = 0; 9422 9423 if (!netif_running(dev)) 9424 return -EAGAIN; 9425 9426 rc = bnxt_hwrm_port_phy_read(bp, mdio->phy_id, mdio->reg_num, 9427 &mii_regval); 9428 mdio->val_out = mii_regval; 9429 return rc; 9430 } 9431 9432 case SIOCSMIIREG: 9433 if (!netif_running(dev)) 9434 return -EAGAIN; 9435 9436 return bnxt_hwrm_port_phy_write(bp, mdio->phy_id, mdio->reg_num, 9437 mdio->val_in); 9438 9439 default: 9440 /* do nothing */ 9441 break; 9442 } 9443 return -EOPNOTSUPP; 9444 } 9445 9446 static void bnxt_get_ring_stats(struct bnxt *bp, 9447 struct rtnl_link_stats64 *stats) 9448 { 9449 int i; 9450 9451 9452 for (i = 0; i < bp->cp_nr_rings; i++) { 9453 struct bnxt_napi *bnapi = bp->bnapi[i]; 9454 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 9455 struct ctx_hw_stats *hw_stats = cpr->hw_stats; 9456 9457 stats->rx_packets += le64_to_cpu(hw_stats->rx_ucast_pkts); 9458 stats->rx_packets += le64_to_cpu(hw_stats->rx_mcast_pkts); 9459 stats->rx_packets += le64_to_cpu(hw_stats->rx_bcast_pkts); 9460 9461 stats->tx_packets += le64_to_cpu(hw_stats->tx_ucast_pkts); 9462 stats->tx_packets += le64_to_cpu(hw_stats->tx_mcast_pkts); 9463 stats->tx_packets += le64_to_cpu(hw_stats->tx_bcast_pkts); 9464 9465 stats->rx_bytes += le64_to_cpu(hw_stats->rx_ucast_bytes); 9466 stats->rx_bytes += le64_to_cpu(hw_stats->rx_mcast_bytes); 9467 stats->rx_bytes += le64_to_cpu(hw_stats->rx_bcast_bytes); 9468 9469 stats->tx_bytes += le64_to_cpu(hw_stats->tx_ucast_bytes); 9470 stats->tx_bytes += le64_to_cpu(hw_stats->tx_mcast_bytes); 9471 stats->tx_bytes += le64_to_cpu(hw_stats->tx_bcast_bytes); 9472 9473 stats->rx_missed_errors += 9474 le64_to_cpu(hw_stats->rx_discard_pkts); 9475 9476 stats->multicast += le64_to_cpu(hw_stats->rx_mcast_pkts); 9477 9478 stats->tx_dropped += le64_to_cpu(hw_stats->tx_drop_pkts); 9479 } 9480 } 9481 9482 static void bnxt_add_prev_stats(struct bnxt *bp, 9483 struct rtnl_link_stats64 *stats) 9484 { 9485 struct rtnl_link_stats64 *prev_stats = &bp->net_stats_prev; 9486 9487 stats->rx_packets += prev_stats->rx_packets; 9488 stats->tx_packets += prev_stats->tx_packets; 9489 stats->rx_bytes += prev_stats->rx_bytes; 9490 stats->tx_bytes += prev_stats->tx_bytes; 9491 stats->rx_missed_errors += prev_stats->rx_missed_errors; 9492 stats->multicast += prev_stats->multicast; 9493 stats->tx_dropped += prev_stats->tx_dropped; 9494 } 9495 9496 static void 9497 bnxt_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) 9498 { 9499 struct bnxt *bp = netdev_priv(dev); 9500 9501 set_bit(BNXT_STATE_READ_STATS, &bp->state); 9502 /* Make sure bnxt_close_nic() sees that we are reading stats before 9503 * we check the BNXT_STATE_OPEN flag. 9504 */ 9505 smp_mb__after_atomic(); 9506 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) { 9507 clear_bit(BNXT_STATE_READ_STATS, &bp->state); 9508 *stats = bp->net_stats_prev; 9509 return; 9510 } 9511 9512 bnxt_get_ring_stats(bp, stats); 9513 bnxt_add_prev_stats(bp, stats); 9514 9515 if (bp->flags & BNXT_FLAG_PORT_STATS) { 9516 struct rx_port_stats *rx = bp->hw_rx_port_stats; 9517 struct tx_port_stats *tx = bp->hw_tx_port_stats; 9518 9519 stats->rx_crc_errors = le64_to_cpu(rx->rx_fcs_err_frames); 9520 stats->rx_frame_errors = le64_to_cpu(rx->rx_align_err_frames); 9521 stats->rx_length_errors = le64_to_cpu(rx->rx_undrsz_frames) + 9522 le64_to_cpu(rx->rx_ovrsz_frames) + 9523 le64_to_cpu(rx->rx_runt_frames); 9524 stats->rx_errors = le64_to_cpu(rx->rx_false_carrier_frames) + 9525 le64_to_cpu(rx->rx_jbr_frames); 9526 stats->collisions = le64_to_cpu(tx->tx_total_collisions); 9527 stats->tx_fifo_errors = le64_to_cpu(tx->tx_fifo_underruns); 9528 stats->tx_errors = le64_to_cpu(tx->tx_err); 9529 } 9530 clear_bit(BNXT_STATE_READ_STATS, &bp->state); 9531 } 9532 9533 static bool bnxt_mc_list_updated(struct bnxt *bp, u32 *rx_mask) 9534 { 9535 struct net_device *dev = bp->dev; 9536 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 9537 struct netdev_hw_addr *ha; 9538 u8 *haddr; 9539 int mc_count = 0; 9540 bool update = false; 9541 int off = 0; 9542 9543 netdev_for_each_mc_addr(ha, dev) { 9544 if (mc_count >= BNXT_MAX_MC_ADDRS) { 9545 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST; 9546 vnic->mc_list_count = 0; 9547 return false; 9548 } 9549 haddr = ha->addr; 9550 if (!ether_addr_equal(haddr, vnic->mc_list + off)) { 9551 memcpy(vnic->mc_list + off, haddr, ETH_ALEN); 9552 update = true; 9553 } 9554 off += ETH_ALEN; 9555 mc_count++; 9556 } 9557 if (mc_count) 9558 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_MCAST; 9559 9560 if (mc_count != vnic->mc_list_count) { 9561 vnic->mc_list_count = mc_count; 9562 update = true; 9563 } 9564 return update; 9565 } 9566 9567 static bool bnxt_uc_list_updated(struct bnxt *bp) 9568 { 9569 struct net_device *dev = bp->dev; 9570 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 9571 struct netdev_hw_addr *ha; 9572 int off = 0; 9573 9574 if (netdev_uc_count(dev) != (vnic->uc_filter_count - 1)) 9575 return true; 9576 9577 netdev_for_each_uc_addr(ha, dev) { 9578 if (!ether_addr_equal(ha->addr, vnic->uc_list + off)) 9579 return true; 9580 9581 off += ETH_ALEN; 9582 } 9583 return false; 9584 } 9585 9586 static void bnxt_set_rx_mode(struct net_device *dev) 9587 { 9588 struct bnxt *bp = netdev_priv(dev); 9589 struct bnxt_vnic_info *vnic; 9590 bool mc_update = false; 9591 bool uc_update; 9592 u32 mask; 9593 9594 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) 9595 return; 9596 9597 vnic = &bp->vnic_info[0]; 9598 mask = vnic->rx_mask; 9599 mask &= ~(CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS | 9600 CFA_L2_SET_RX_MASK_REQ_MASK_MCAST | 9601 CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST | 9602 CFA_L2_SET_RX_MASK_REQ_MASK_BCAST); 9603 9604 if ((dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp)) 9605 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS; 9606 9607 uc_update = bnxt_uc_list_updated(bp); 9608 9609 if (dev->flags & IFF_BROADCAST) 9610 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_BCAST; 9611 if (dev->flags & IFF_ALLMULTI) { 9612 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST; 9613 vnic->mc_list_count = 0; 9614 } else { 9615 mc_update = bnxt_mc_list_updated(bp, &mask); 9616 } 9617 9618 if (mask != vnic->rx_mask || uc_update || mc_update) { 9619 vnic->rx_mask = mask; 9620 9621 set_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event); 9622 bnxt_queue_sp_work(bp); 9623 } 9624 } 9625 9626 static int bnxt_cfg_rx_mode(struct bnxt *bp) 9627 { 9628 struct net_device *dev = bp->dev; 9629 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 9630 struct netdev_hw_addr *ha; 9631 int i, off = 0, rc; 9632 bool uc_update; 9633 9634 netif_addr_lock_bh(dev); 9635 uc_update = bnxt_uc_list_updated(bp); 9636 netif_addr_unlock_bh(dev); 9637 9638 if (!uc_update) 9639 goto skip_uc; 9640 9641 mutex_lock(&bp->hwrm_cmd_lock); 9642 for (i = 1; i < vnic->uc_filter_count; i++) { 9643 struct hwrm_cfa_l2_filter_free_input req = {0}; 9644 9645 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_FREE, -1, 9646 -1); 9647 9648 req.l2_filter_id = vnic->fw_l2_filter_id[i]; 9649 9650 rc = _hwrm_send_message(bp, &req, sizeof(req), 9651 HWRM_CMD_TIMEOUT); 9652 } 9653 mutex_unlock(&bp->hwrm_cmd_lock); 9654 9655 vnic->uc_filter_count = 1; 9656 9657 netif_addr_lock_bh(dev); 9658 if (netdev_uc_count(dev) > (BNXT_MAX_UC_ADDRS - 1)) { 9659 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS; 9660 } else { 9661 netdev_for_each_uc_addr(ha, dev) { 9662 memcpy(vnic->uc_list + off, ha->addr, ETH_ALEN); 9663 off += ETH_ALEN; 9664 vnic->uc_filter_count++; 9665 } 9666 } 9667 netif_addr_unlock_bh(dev); 9668 9669 for (i = 1, off = 0; i < vnic->uc_filter_count; i++, off += ETH_ALEN) { 9670 rc = bnxt_hwrm_set_vnic_filter(bp, 0, i, vnic->uc_list + off); 9671 if (rc) { 9672 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n", 9673 rc); 9674 vnic->uc_filter_count = i; 9675 return rc; 9676 } 9677 } 9678 9679 skip_uc: 9680 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0); 9681 if (rc && vnic->mc_list_count) { 9682 netdev_info(bp->dev, "Failed setting MC filters rc: %d, turning on ALL_MCAST mode\n", 9683 rc); 9684 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST; 9685 vnic->mc_list_count = 0; 9686 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0); 9687 } 9688 if (rc) 9689 netdev_err(bp->dev, "HWRM cfa l2 rx mask failure rc: %d\n", 9690 rc); 9691 9692 return rc; 9693 } 9694 9695 static bool bnxt_can_reserve_rings(struct bnxt *bp) 9696 { 9697 #ifdef CONFIG_BNXT_SRIOV 9698 if (BNXT_NEW_RM(bp) && BNXT_VF(bp)) { 9699 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 9700 9701 /* No minimum rings were provisioned by the PF. Don't 9702 * reserve rings by default when device is down. 9703 */ 9704 if (hw_resc->min_tx_rings || hw_resc->resv_tx_rings) 9705 return true; 9706 9707 if (!netif_running(bp->dev)) 9708 return false; 9709 } 9710 #endif 9711 return true; 9712 } 9713 9714 /* If the chip and firmware supports RFS */ 9715 static bool bnxt_rfs_supported(struct bnxt *bp) 9716 { 9717 if (bp->flags & BNXT_FLAG_CHIP_P5) { 9718 if (bp->fw_cap & BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V2) 9719 return true; 9720 return false; 9721 } 9722 if (BNXT_PF(bp) && !BNXT_CHIP_TYPE_NITRO_A0(bp)) 9723 return true; 9724 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP) 9725 return true; 9726 return false; 9727 } 9728 9729 /* If runtime conditions support RFS */ 9730 static bool bnxt_rfs_capable(struct bnxt *bp) 9731 { 9732 #ifdef CONFIG_RFS_ACCEL 9733 int vnics, max_vnics, max_rss_ctxs; 9734 9735 if (bp->flags & BNXT_FLAG_CHIP_P5) 9736 return bnxt_rfs_supported(bp); 9737 if (!(bp->flags & BNXT_FLAG_MSIX_CAP) || !bnxt_can_reserve_rings(bp)) 9738 return false; 9739 9740 vnics = 1 + bp->rx_nr_rings; 9741 max_vnics = bnxt_get_max_func_vnics(bp); 9742 max_rss_ctxs = bnxt_get_max_func_rss_ctxs(bp); 9743 9744 /* RSS contexts not a limiting factor */ 9745 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP) 9746 max_rss_ctxs = max_vnics; 9747 if (vnics > max_vnics || vnics > max_rss_ctxs) { 9748 if (bp->rx_nr_rings > 1) 9749 netdev_warn(bp->dev, 9750 "Not enough resources to support NTUPLE filters, enough resources for up to %d rx rings\n", 9751 min(max_rss_ctxs - 1, max_vnics - 1)); 9752 return false; 9753 } 9754 9755 if (!BNXT_NEW_RM(bp)) 9756 return true; 9757 9758 if (vnics == bp->hw_resc.resv_vnics) 9759 return true; 9760 9761 bnxt_hwrm_reserve_rings(bp, 0, 0, 0, 0, 0, vnics); 9762 if (vnics <= bp->hw_resc.resv_vnics) 9763 return true; 9764 9765 netdev_warn(bp->dev, "Unable to reserve resources to support NTUPLE filters.\n"); 9766 bnxt_hwrm_reserve_rings(bp, 0, 0, 0, 0, 0, 1); 9767 return false; 9768 #else 9769 return false; 9770 #endif 9771 } 9772 9773 static netdev_features_t bnxt_fix_features(struct net_device *dev, 9774 netdev_features_t features) 9775 { 9776 struct bnxt *bp = netdev_priv(dev); 9777 netdev_features_t vlan_features; 9778 9779 if ((features & NETIF_F_NTUPLE) && !bnxt_rfs_capable(bp)) 9780 features &= ~NETIF_F_NTUPLE; 9781 9782 if (bp->flags & BNXT_FLAG_NO_AGG_RINGS) 9783 features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW); 9784 9785 if (!(features & NETIF_F_GRO)) 9786 features &= ~NETIF_F_GRO_HW; 9787 9788 if (features & NETIF_F_GRO_HW) 9789 features &= ~NETIF_F_LRO; 9790 9791 /* Both CTAG and STAG VLAN accelaration on the RX side have to be 9792 * turned on or off together. 9793 */ 9794 vlan_features = features & (NETIF_F_HW_VLAN_CTAG_RX | 9795 NETIF_F_HW_VLAN_STAG_RX); 9796 if (vlan_features != (NETIF_F_HW_VLAN_CTAG_RX | 9797 NETIF_F_HW_VLAN_STAG_RX)) { 9798 if (dev->features & NETIF_F_HW_VLAN_CTAG_RX) 9799 features &= ~(NETIF_F_HW_VLAN_CTAG_RX | 9800 NETIF_F_HW_VLAN_STAG_RX); 9801 else if (vlan_features) 9802 features |= NETIF_F_HW_VLAN_CTAG_RX | 9803 NETIF_F_HW_VLAN_STAG_RX; 9804 } 9805 #ifdef CONFIG_BNXT_SRIOV 9806 if (BNXT_VF(bp)) { 9807 if (bp->vf.vlan) { 9808 features &= ~(NETIF_F_HW_VLAN_CTAG_RX | 9809 NETIF_F_HW_VLAN_STAG_RX); 9810 } 9811 } 9812 #endif 9813 return features; 9814 } 9815 9816 static int bnxt_set_features(struct net_device *dev, netdev_features_t features) 9817 { 9818 struct bnxt *bp = netdev_priv(dev); 9819 u32 flags = bp->flags; 9820 u32 changes; 9821 int rc = 0; 9822 bool re_init = false; 9823 bool update_tpa = false; 9824 9825 flags &= ~BNXT_FLAG_ALL_CONFIG_FEATS; 9826 if (features & NETIF_F_GRO_HW) 9827 flags |= BNXT_FLAG_GRO; 9828 else if (features & NETIF_F_LRO) 9829 flags |= BNXT_FLAG_LRO; 9830 9831 if (bp->flags & BNXT_FLAG_NO_AGG_RINGS) 9832 flags &= ~BNXT_FLAG_TPA; 9833 9834 if (features & NETIF_F_HW_VLAN_CTAG_RX) 9835 flags |= BNXT_FLAG_STRIP_VLAN; 9836 9837 if (features & NETIF_F_NTUPLE) 9838 flags |= BNXT_FLAG_RFS; 9839 9840 changes = flags ^ bp->flags; 9841 if (changes & BNXT_FLAG_TPA) { 9842 update_tpa = true; 9843 if ((bp->flags & BNXT_FLAG_TPA) == 0 || 9844 (flags & BNXT_FLAG_TPA) == 0 || 9845 (bp->flags & BNXT_FLAG_CHIP_P5)) 9846 re_init = true; 9847 } 9848 9849 if (changes & ~BNXT_FLAG_TPA) 9850 re_init = true; 9851 9852 if (flags != bp->flags) { 9853 u32 old_flags = bp->flags; 9854 9855 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) { 9856 bp->flags = flags; 9857 if (update_tpa) 9858 bnxt_set_ring_params(bp); 9859 return rc; 9860 } 9861 9862 if (re_init) { 9863 bnxt_close_nic(bp, false, false); 9864 bp->flags = flags; 9865 if (update_tpa) 9866 bnxt_set_ring_params(bp); 9867 9868 return bnxt_open_nic(bp, false, false); 9869 } 9870 if (update_tpa) { 9871 bp->flags = flags; 9872 rc = bnxt_set_tpa(bp, 9873 (flags & BNXT_FLAG_TPA) ? 9874 true : false); 9875 if (rc) 9876 bp->flags = old_flags; 9877 } 9878 } 9879 return rc; 9880 } 9881 9882 static int bnxt_dbg_hwrm_ring_info_get(struct bnxt *bp, u8 ring_type, 9883 u32 ring_id, u32 *prod, u32 *cons) 9884 { 9885 struct hwrm_dbg_ring_info_get_output *resp = bp->hwrm_cmd_resp_addr; 9886 struct hwrm_dbg_ring_info_get_input req = {0}; 9887 int rc; 9888 9889 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_DBG_RING_INFO_GET, -1, -1); 9890 req.ring_type = ring_type; 9891 req.fw_ring_id = cpu_to_le32(ring_id); 9892 mutex_lock(&bp->hwrm_cmd_lock); 9893 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 9894 if (!rc) { 9895 *prod = le32_to_cpu(resp->producer_index); 9896 *cons = le32_to_cpu(resp->consumer_index); 9897 } 9898 mutex_unlock(&bp->hwrm_cmd_lock); 9899 return rc; 9900 } 9901 9902 static void bnxt_dump_tx_sw_state(struct bnxt_napi *bnapi) 9903 { 9904 struct bnxt_tx_ring_info *txr = bnapi->tx_ring; 9905 int i = bnapi->index; 9906 9907 if (!txr) 9908 return; 9909 9910 netdev_info(bnapi->bp->dev, "[%d]: tx{fw_ring: %d prod: %x cons: %x}\n", 9911 i, txr->tx_ring_struct.fw_ring_id, txr->tx_prod, 9912 txr->tx_cons); 9913 } 9914 9915 static void bnxt_dump_rx_sw_state(struct bnxt_napi *bnapi) 9916 { 9917 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 9918 int i = bnapi->index; 9919 9920 if (!rxr) 9921 return; 9922 9923 netdev_info(bnapi->bp->dev, "[%d]: rx{fw_ring: %d prod: %x} rx_agg{fw_ring: %d agg_prod: %x sw_agg_prod: %x}\n", 9924 i, rxr->rx_ring_struct.fw_ring_id, rxr->rx_prod, 9925 rxr->rx_agg_ring_struct.fw_ring_id, rxr->rx_agg_prod, 9926 rxr->rx_sw_agg_prod); 9927 } 9928 9929 static void bnxt_dump_cp_sw_state(struct bnxt_napi *bnapi) 9930 { 9931 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 9932 int i = bnapi->index; 9933 9934 netdev_info(bnapi->bp->dev, "[%d]: cp{fw_ring: %d raw_cons: %x}\n", 9935 i, cpr->cp_ring_struct.fw_ring_id, cpr->cp_raw_cons); 9936 } 9937 9938 static void bnxt_dbg_dump_states(struct bnxt *bp) 9939 { 9940 int i; 9941 struct bnxt_napi *bnapi; 9942 9943 for (i = 0; i < bp->cp_nr_rings; i++) { 9944 bnapi = bp->bnapi[i]; 9945 if (netif_msg_drv(bp)) { 9946 bnxt_dump_tx_sw_state(bnapi); 9947 bnxt_dump_rx_sw_state(bnapi); 9948 bnxt_dump_cp_sw_state(bnapi); 9949 } 9950 } 9951 } 9952 9953 static void bnxt_reset_task(struct bnxt *bp, bool silent) 9954 { 9955 if (!silent) 9956 bnxt_dbg_dump_states(bp); 9957 if (netif_running(bp->dev)) { 9958 int rc; 9959 9960 if (silent) { 9961 bnxt_close_nic(bp, false, false); 9962 bnxt_open_nic(bp, false, false); 9963 } else { 9964 bnxt_ulp_stop(bp); 9965 bnxt_close_nic(bp, true, false); 9966 rc = bnxt_open_nic(bp, true, false); 9967 bnxt_ulp_start(bp, rc); 9968 } 9969 } 9970 } 9971 9972 static void bnxt_tx_timeout(struct net_device *dev, unsigned int txqueue) 9973 { 9974 struct bnxt *bp = netdev_priv(dev); 9975 9976 netdev_err(bp->dev, "TX timeout detected, starting reset task!\n"); 9977 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event); 9978 bnxt_queue_sp_work(bp); 9979 } 9980 9981 static void bnxt_fw_health_check(struct bnxt *bp) 9982 { 9983 struct bnxt_fw_health *fw_health = bp->fw_health; 9984 u32 val; 9985 9986 if (!fw_health->enabled || test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) 9987 return; 9988 9989 if (fw_health->tmr_counter) { 9990 fw_health->tmr_counter--; 9991 return; 9992 } 9993 9994 val = bnxt_fw_health_readl(bp, BNXT_FW_HEARTBEAT_REG); 9995 if (val == fw_health->last_fw_heartbeat) 9996 goto fw_reset; 9997 9998 fw_health->last_fw_heartbeat = val; 9999 10000 val = bnxt_fw_health_readl(bp, BNXT_FW_RESET_CNT_REG); 10001 if (val != fw_health->last_fw_reset_cnt) 10002 goto fw_reset; 10003 10004 fw_health->tmr_counter = fw_health->tmr_multiplier; 10005 return; 10006 10007 fw_reset: 10008 set_bit(BNXT_FW_EXCEPTION_SP_EVENT, &bp->sp_event); 10009 bnxt_queue_sp_work(bp); 10010 } 10011 10012 static void bnxt_timer(struct timer_list *t) 10013 { 10014 struct bnxt *bp = from_timer(bp, t, timer); 10015 struct net_device *dev = bp->dev; 10016 10017 if (!netif_running(dev)) 10018 return; 10019 10020 if (atomic_read(&bp->intr_sem) != 0) 10021 goto bnxt_restart_timer; 10022 10023 if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY) 10024 bnxt_fw_health_check(bp); 10025 10026 if (bp->link_info.link_up && (bp->flags & BNXT_FLAG_PORT_STATS) && 10027 bp->stats_coal_ticks) { 10028 set_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event); 10029 bnxt_queue_sp_work(bp); 10030 } 10031 10032 if (bnxt_tc_flower_enabled(bp)) { 10033 set_bit(BNXT_FLOW_STATS_SP_EVENT, &bp->sp_event); 10034 bnxt_queue_sp_work(bp); 10035 } 10036 10037 #ifdef CONFIG_RFS_ACCEL 10038 if ((bp->flags & BNXT_FLAG_RFS) && bp->ntp_fltr_count) { 10039 set_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event); 10040 bnxt_queue_sp_work(bp); 10041 } 10042 #endif /*CONFIG_RFS_ACCEL*/ 10043 10044 if (bp->link_info.phy_retry) { 10045 if (time_after(jiffies, bp->link_info.phy_retry_expires)) { 10046 bp->link_info.phy_retry = false; 10047 netdev_warn(bp->dev, "failed to update phy settings after maximum retries.\n"); 10048 } else { 10049 set_bit(BNXT_UPDATE_PHY_SP_EVENT, &bp->sp_event); 10050 bnxt_queue_sp_work(bp); 10051 } 10052 } 10053 10054 if ((bp->flags & BNXT_FLAG_CHIP_P5) && !bp->chip_rev && 10055 netif_carrier_ok(dev)) { 10056 set_bit(BNXT_RING_COAL_NOW_SP_EVENT, &bp->sp_event); 10057 bnxt_queue_sp_work(bp); 10058 } 10059 bnxt_restart_timer: 10060 mod_timer(&bp->timer, jiffies + bp->current_interval); 10061 } 10062 10063 static void bnxt_rtnl_lock_sp(struct bnxt *bp) 10064 { 10065 /* We are called from bnxt_sp_task which has BNXT_STATE_IN_SP_TASK 10066 * set. If the device is being closed, bnxt_close() may be holding 10067 * rtnl() and waiting for BNXT_STATE_IN_SP_TASK to clear. So we 10068 * must clear BNXT_STATE_IN_SP_TASK before holding rtnl(). 10069 */ 10070 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state); 10071 rtnl_lock(); 10072 } 10073 10074 static void bnxt_rtnl_unlock_sp(struct bnxt *bp) 10075 { 10076 set_bit(BNXT_STATE_IN_SP_TASK, &bp->state); 10077 rtnl_unlock(); 10078 } 10079 10080 /* Only called from bnxt_sp_task() */ 10081 static void bnxt_reset(struct bnxt *bp, bool silent) 10082 { 10083 bnxt_rtnl_lock_sp(bp); 10084 if (test_bit(BNXT_STATE_OPEN, &bp->state)) 10085 bnxt_reset_task(bp, silent); 10086 bnxt_rtnl_unlock_sp(bp); 10087 } 10088 10089 static void bnxt_fw_reset_close(struct bnxt *bp) 10090 { 10091 bnxt_ulp_stop(bp); 10092 /* When firmware is fatal state, disable PCI device to prevent 10093 * any potential bad DMAs before freeing kernel memory. 10094 */ 10095 if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state)) 10096 pci_disable_device(bp->pdev); 10097 __bnxt_close_nic(bp, true, false); 10098 bnxt_clear_int_mode(bp); 10099 bnxt_hwrm_func_drv_unrgtr(bp); 10100 if (pci_is_enabled(bp->pdev)) 10101 pci_disable_device(bp->pdev); 10102 bnxt_free_ctx_mem(bp); 10103 kfree(bp->ctx); 10104 bp->ctx = NULL; 10105 } 10106 10107 static bool is_bnxt_fw_ok(struct bnxt *bp) 10108 { 10109 struct bnxt_fw_health *fw_health = bp->fw_health; 10110 bool no_heartbeat = false, has_reset = false; 10111 u32 val; 10112 10113 val = bnxt_fw_health_readl(bp, BNXT_FW_HEARTBEAT_REG); 10114 if (val == fw_health->last_fw_heartbeat) 10115 no_heartbeat = true; 10116 10117 val = bnxt_fw_health_readl(bp, BNXT_FW_RESET_CNT_REG); 10118 if (val != fw_health->last_fw_reset_cnt) 10119 has_reset = true; 10120 10121 if (!no_heartbeat && has_reset) 10122 return true; 10123 10124 return false; 10125 } 10126 10127 /* rtnl_lock is acquired before calling this function */ 10128 static void bnxt_force_fw_reset(struct bnxt *bp) 10129 { 10130 struct bnxt_fw_health *fw_health = bp->fw_health; 10131 u32 wait_dsecs; 10132 10133 if (!test_bit(BNXT_STATE_OPEN, &bp->state) || 10134 test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) 10135 return; 10136 10137 set_bit(BNXT_STATE_IN_FW_RESET, &bp->state); 10138 bnxt_fw_reset_close(bp); 10139 wait_dsecs = fw_health->master_func_wait_dsecs; 10140 if (fw_health->master) { 10141 if (fw_health->flags & ERROR_RECOVERY_QCFG_RESP_FLAGS_CO_CPU) 10142 wait_dsecs = 0; 10143 bp->fw_reset_state = BNXT_FW_RESET_STATE_RESET_FW; 10144 } else { 10145 bp->fw_reset_timestamp = jiffies + wait_dsecs * HZ / 10; 10146 wait_dsecs = fw_health->normal_func_wait_dsecs; 10147 bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV; 10148 } 10149 10150 bp->fw_reset_min_dsecs = fw_health->post_reset_wait_dsecs; 10151 bp->fw_reset_max_dsecs = fw_health->post_reset_max_wait_dsecs; 10152 bnxt_queue_fw_reset_work(bp, wait_dsecs * HZ / 10); 10153 } 10154 10155 void bnxt_fw_exception(struct bnxt *bp) 10156 { 10157 netdev_warn(bp->dev, "Detected firmware fatal condition, initiating reset\n"); 10158 set_bit(BNXT_STATE_FW_FATAL_COND, &bp->state); 10159 bnxt_rtnl_lock_sp(bp); 10160 bnxt_force_fw_reset(bp); 10161 bnxt_rtnl_unlock_sp(bp); 10162 } 10163 10164 /* Returns the number of registered VFs, or 1 if VF configuration is pending, or 10165 * < 0 on error. 10166 */ 10167 static int bnxt_get_registered_vfs(struct bnxt *bp) 10168 { 10169 #ifdef CONFIG_BNXT_SRIOV 10170 int rc; 10171 10172 if (!BNXT_PF(bp)) 10173 return 0; 10174 10175 rc = bnxt_hwrm_func_qcfg(bp); 10176 if (rc) { 10177 netdev_err(bp->dev, "func_qcfg cmd failed, rc = %d\n", rc); 10178 return rc; 10179 } 10180 if (bp->pf.registered_vfs) 10181 return bp->pf.registered_vfs; 10182 if (bp->sriov_cfg) 10183 return 1; 10184 #endif 10185 return 0; 10186 } 10187 10188 void bnxt_fw_reset(struct bnxt *bp) 10189 { 10190 bnxt_rtnl_lock_sp(bp); 10191 if (test_bit(BNXT_STATE_OPEN, &bp->state) && 10192 !test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) { 10193 int n = 0, tmo; 10194 10195 set_bit(BNXT_STATE_IN_FW_RESET, &bp->state); 10196 if (bp->pf.active_vfs && 10197 !test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state)) 10198 n = bnxt_get_registered_vfs(bp); 10199 if (n < 0) { 10200 netdev_err(bp->dev, "Firmware reset aborted, rc = %d\n", 10201 n); 10202 clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state); 10203 dev_close(bp->dev); 10204 goto fw_reset_exit; 10205 } else if (n > 0) { 10206 u16 vf_tmo_dsecs = n * 10; 10207 10208 if (bp->fw_reset_max_dsecs < vf_tmo_dsecs) 10209 bp->fw_reset_max_dsecs = vf_tmo_dsecs; 10210 bp->fw_reset_state = 10211 BNXT_FW_RESET_STATE_POLL_VF; 10212 bnxt_queue_fw_reset_work(bp, HZ / 10); 10213 goto fw_reset_exit; 10214 } 10215 bnxt_fw_reset_close(bp); 10216 if (bp->fw_cap & BNXT_FW_CAP_ERR_RECOVER_RELOAD) { 10217 bp->fw_reset_state = BNXT_FW_RESET_STATE_POLL_FW_DOWN; 10218 tmo = HZ / 10; 10219 } else { 10220 bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV; 10221 tmo = bp->fw_reset_min_dsecs * HZ / 10; 10222 } 10223 bnxt_queue_fw_reset_work(bp, tmo); 10224 } 10225 fw_reset_exit: 10226 bnxt_rtnl_unlock_sp(bp); 10227 } 10228 10229 static void bnxt_chk_missed_irq(struct bnxt *bp) 10230 { 10231 int i; 10232 10233 if (!(bp->flags & BNXT_FLAG_CHIP_P5)) 10234 return; 10235 10236 for (i = 0; i < bp->cp_nr_rings; i++) { 10237 struct bnxt_napi *bnapi = bp->bnapi[i]; 10238 struct bnxt_cp_ring_info *cpr; 10239 u32 fw_ring_id; 10240 int j; 10241 10242 if (!bnapi) 10243 continue; 10244 10245 cpr = &bnapi->cp_ring; 10246 for (j = 0; j < 2; j++) { 10247 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j]; 10248 u32 val[2]; 10249 10250 if (!cpr2 || cpr2->has_more_work || 10251 !bnxt_has_work(bp, cpr2)) 10252 continue; 10253 10254 if (cpr2->cp_raw_cons != cpr2->last_cp_raw_cons) { 10255 cpr2->last_cp_raw_cons = cpr2->cp_raw_cons; 10256 continue; 10257 } 10258 fw_ring_id = cpr2->cp_ring_struct.fw_ring_id; 10259 bnxt_dbg_hwrm_ring_info_get(bp, 10260 DBG_RING_INFO_GET_REQ_RING_TYPE_L2_CMPL, 10261 fw_ring_id, &val[0], &val[1]); 10262 cpr->missed_irqs++; 10263 } 10264 } 10265 } 10266 10267 static void bnxt_cfg_ntp_filters(struct bnxt *); 10268 10269 static void bnxt_init_ethtool_link_settings(struct bnxt *bp) 10270 { 10271 struct bnxt_link_info *link_info = &bp->link_info; 10272 10273 if (BNXT_AUTO_MODE(link_info->auto_mode)) { 10274 link_info->autoneg = BNXT_AUTONEG_SPEED; 10275 if (bp->hwrm_spec_code >= 0x10201) { 10276 if (link_info->auto_pause_setting & 10277 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE) 10278 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL; 10279 } else { 10280 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL; 10281 } 10282 link_info->advertising = link_info->auto_link_speeds; 10283 } else { 10284 link_info->req_link_speed = link_info->force_link_speed; 10285 link_info->req_duplex = link_info->duplex_setting; 10286 } 10287 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) 10288 link_info->req_flow_ctrl = 10289 link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH; 10290 else 10291 link_info->req_flow_ctrl = link_info->force_pause_setting; 10292 } 10293 10294 static void bnxt_sp_task(struct work_struct *work) 10295 { 10296 struct bnxt *bp = container_of(work, struct bnxt, sp_task); 10297 10298 set_bit(BNXT_STATE_IN_SP_TASK, &bp->state); 10299 smp_mb__after_atomic(); 10300 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) { 10301 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state); 10302 return; 10303 } 10304 10305 if (test_and_clear_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event)) 10306 bnxt_cfg_rx_mode(bp); 10307 10308 if (test_and_clear_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event)) 10309 bnxt_cfg_ntp_filters(bp); 10310 if (test_and_clear_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event)) 10311 bnxt_hwrm_exec_fwd_req(bp); 10312 if (test_and_clear_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event)) { 10313 bnxt_hwrm_tunnel_dst_port_alloc( 10314 bp, bp->vxlan_port, 10315 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN); 10316 } 10317 if (test_and_clear_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event)) { 10318 bnxt_hwrm_tunnel_dst_port_free( 10319 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN); 10320 } 10321 if (test_and_clear_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event)) { 10322 bnxt_hwrm_tunnel_dst_port_alloc( 10323 bp, bp->nge_port, 10324 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE); 10325 } 10326 if (test_and_clear_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event)) { 10327 bnxt_hwrm_tunnel_dst_port_free( 10328 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE); 10329 } 10330 if (test_and_clear_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event)) { 10331 bnxt_hwrm_port_qstats(bp); 10332 bnxt_hwrm_port_qstats_ext(bp); 10333 bnxt_hwrm_pcie_qstats(bp); 10334 } 10335 10336 if (test_and_clear_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event)) { 10337 int rc; 10338 10339 mutex_lock(&bp->link_lock); 10340 if (test_and_clear_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT, 10341 &bp->sp_event)) 10342 bnxt_hwrm_phy_qcaps(bp); 10343 10344 if (test_and_clear_bit(BNXT_LINK_CFG_CHANGE_SP_EVENT, 10345 &bp->sp_event)) 10346 bnxt_init_ethtool_link_settings(bp); 10347 10348 rc = bnxt_update_link(bp, true); 10349 mutex_unlock(&bp->link_lock); 10350 if (rc) 10351 netdev_err(bp->dev, "SP task can't update link (rc: %x)\n", 10352 rc); 10353 } 10354 if (test_and_clear_bit(BNXT_UPDATE_PHY_SP_EVENT, &bp->sp_event)) { 10355 int rc; 10356 10357 mutex_lock(&bp->link_lock); 10358 rc = bnxt_update_phy_setting(bp); 10359 mutex_unlock(&bp->link_lock); 10360 if (rc) { 10361 netdev_warn(bp->dev, "update phy settings retry failed\n"); 10362 } else { 10363 bp->link_info.phy_retry = false; 10364 netdev_info(bp->dev, "update phy settings retry succeeded\n"); 10365 } 10366 } 10367 if (test_and_clear_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event)) { 10368 mutex_lock(&bp->link_lock); 10369 bnxt_get_port_module_status(bp); 10370 mutex_unlock(&bp->link_lock); 10371 } 10372 10373 if (test_and_clear_bit(BNXT_FLOW_STATS_SP_EVENT, &bp->sp_event)) 10374 bnxt_tc_flow_stats_work(bp); 10375 10376 if (test_and_clear_bit(BNXT_RING_COAL_NOW_SP_EVENT, &bp->sp_event)) 10377 bnxt_chk_missed_irq(bp); 10378 10379 /* These functions below will clear BNXT_STATE_IN_SP_TASK. They 10380 * must be the last functions to be called before exiting. 10381 */ 10382 if (test_and_clear_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event)) 10383 bnxt_reset(bp, false); 10384 10385 if (test_and_clear_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event)) 10386 bnxt_reset(bp, true); 10387 10388 if (test_and_clear_bit(BNXT_FW_RESET_NOTIFY_SP_EVENT, &bp->sp_event)) 10389 bnxt_devlink_health_report(bp, BNXT_FW_RESET_NOTIFY_SP_EVENT); 10390 10391 if (test_and_clear_bit(BNXT_FW_EXCEPTION_SP_EVENT, &bp->sp_event)) { 10392 if (!is_bnxt_fw_ok(bp)) 10393 bnxt_devlink_health_report(bp, 10394 BNXT_FW_EXCEPTION_SP_EVENT); 10395 } 10396 10397 smp_mb__before_atomic(); 10398 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state); 10399 } 10400 10401 /* Under rtnl_lock */ 10402 int bnxt_check_rings(struct bnxt *bp, int tx, int rx, bool sh, int tcs, 10403 int tx_xdp) 10404 { 10405 int max_rx, max_tx, tx_sets = 1; 10406 int tx_rings_needed, stats; 10407 int rx_rings = rx; 10408 int cp, vnics, rc; 10409 10410 if (tcs) 10411 tx_sets = tcs; 10412 10413 rc = bnxt_get_max_rings(bp, &max_rx, &max_tx, sh); 10414 if (rc) 10415 return rc; 10416 10417 if (max_rx < rx) 10418 return -ENOMEM; 10419 10420 tx_rings_needed = tx * tx_sets + tx_xdp; 10421 if (max_tx < tx_rings_needed) 10422 return -ENOMEM; 10423 10424 vnics = 1; 10425 if ((bp->flags & (BNXT_FLAG_RFS | BNXT_FLAG_CHIP_P5)) == BNXT_FLAG_RFS) 10426 vnics += rx_rings; 10427 10428 if (bp->flags & BNXT_FLAG_AGG_RINGS) 10429 rx_rings <<= 1; 10430 cp = sh ? max_t(int, tx_rings_needed, rx) : tx_rings_needed + rx; 10431 stats = cp; 10432 if (BNXT_NEW_RM(bp)) { 10433 cp += bnxt_get_ulp_msix_num(bp); 10434 stats += bnxt_get_ulp_stat_ctxs(bp); 10435 } 10436 return bnxt_hwrm_check_rings(bp, tx_rings_needed, rx_rings, rx, cp, 10437 stats, vnics); 10438 } 10439 10440 static void bnxt_unmap_bars(struct bnxt *bp, struct pci_dev *pdev) 10441 { 10442 if (bp->bar2) { 10443 pci_iounmap(pdev, bp->bar2); 10444 bp->bar2 = NULL; 10445 } 10446 10447 if (bp->bar1) { 10448 pci_iounmap(pdev, bp->bar1); 10449 bp->bar1 = NULL; 10450 } 10451 10452 if (bp->bar0) { 10453 pci_iounmap(pdev, bp->bar0); 10454 bp->bar0 = NULL; 10455 } 10456 } 10457 10458 static void bnxt_cleanup_pci(struct bnxt *bp) 10459 { 10460 bnxt_unmap_bars(bp, bp->pdev); 10461 pci_release_regions(bp->pdev); 10462 if (pci_is_enabled(bp->pdev)) 10463 pci_disable_device(bp->pdev); 10464 } 10465 10466 static void bnxt_init_dflt_coal(struct bnxt *bp) 10467 { 10468 struct bnxt_coal *coal; 10469 10470 /* Tick values in micro seconds. 10471 * 1 coal_buf x bufs_per_record = 1 completion record. 10472 */ 10473 coal = &bp->rx_coal; 10474 coal->coal_ticks = 10; 10475 coal->coal_bufs = 30; 10476 coal->coal_ticks_irq = 1; 10477 coal->coal_bufs_irq = 2; 10478 coal->idle_thresh = 50; 10479 coal->bufs_per_record = 2; 10480 coal->budget = 64; /* NAPI budget */ 10481 10482 coal = &bp->tx_coal; 10483 coal->coal_ticks = 28; 10484 coal->coal_bufs = 30; 10485 coal->coal_ticks_irq = 2; 10486 coal->coal_bufs_irq = 2; 10487 coal->bufs_per_record = 1; 10488 10489 bp->stats_coal_ticks = BNXT_DEF_STATS_COAL_TICKS; 10490 } 10491 10492 static void bnxt_alloc_fw_health(struct bnxt *bp) 10493 { 10494 if (bp->fw_health) 10495 return; 10496 10497 if (!(bp->fw_cap & BNXT_FW_CAP_HOT_RESET) && 10498 !(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)) 10499 return; 10500 10501 bp->fw_health = kzalloc(sizeof(*bp->fw_health), GFP_KERNEL); 10502 if (!bp->fw_health) { 10503 netdev_warn(bp->dev, "Failed to allocate fw_health\n"); 10504 bp->fw_cap &= ~BNXT_FW_CAP_HOT_RESET; 10505 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY; 10506 } 10507 } 10508 10509 static int bnxt_fw_init_one_p1(struct bnxt *bp) 10510 { 10511 int rc; 10512 10513 bp->fw_cap = 0; 10514 rc = bnxt_hwrm_ver_get(bp); 10515 if (rc) 10516 return rc; 10517 10518 if (bp->fw_cap & BNXT_FW_CAP_KONG_MB_CHNL) { 10519 rc = bnxt_alloc_kong_hwrm_resources(bp); 10520 if (rc) 10521 bp->fw_cap &= ~BNXT_FW_CAP_KONG_MB_CHNL; 10522 } 10523 10524 if ((bp->fw_cap & BNXT_FW_CAP_SHORT_CMD) || 10525 bp->hwrm_max_ext_req_len > BNXT_HWRM_MAX_REQ_LEN) { 10526 rc = bnxt_alloc_hwrm_short_cmd_req(bp); 10527 if (rc) 10528 return rc; 10529 } 10530 rc = bnxt_hwrm_func_reset(bp); 10531 if (rc) 10532 return -ENODEV; 10533 10534 bnxt_hwrm_fw_set_time(bp); 10535 return 0; 10536 } 10537 10538 static int bnxt_fw_init_one_p2(struct bnxt *bp) 10539 { 10540 int rc; 10541 10542 /* Get the MAX capabilities for this function */ 10543 rc = bnxt_hwrm_func_qcaps(bp); 10544 if (rc) { 10545 netdev_err(bp->dev, "hwrm query capability failure rc: %x\n", 10546 rc); 10547 return -ENODEV; 10548 } 10549 10550 rc = bnxt_hwrm_cfa_adv_flow_mgnt_qcaps(bp); 10551 if (rc) 10552 netdev_warn(bp->dev, "hwrm query adv flow mgnt failure rc: %d\n", 10553 rc); 10554 10555 bnxt_alloc_fw_health(bp); 10556 rc = bnxt_hwrm_error_recovery_qcfg(bp); 10557 if (rc) 10558 netdev_warn(bp->dev, "hwrm query error recovery failure rc: %d\n", 10559 rc); 10560 10561 rc = bnxt_hwrm_func_drv_rgtr(bp, NULL, 0, false); 10562 if (rc) 10563 return -ENODEV; 10564 10565 bnxt_hwrm_func_qcfg(bp); 10566 bnxt_hwrm_vnic_qcaps(bp); 10567 bnxt_hwrm_port_led_qcaps(bp); 10568 bnxt_ethtool_init(bp); 10569 bnxt_dcb_init(bp); 10570 return 0; 10571 } 10572 10573 static void bnxt_set_dflt_rss_hash_type(struct bnxt *bp) 10574 { 10575 bp->flags &= ~BNXT_FLAG_UDP_RSS_CAP; 10576 bp->rss_hash_cfg = VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 | 10577 VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 | 10578 VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 | 10579 VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6; 10580 if (BNXT_CHIP_P4_PLUS(bp) && bp->hwrm_spec_code >= 0x10501) { 10581 bp->flags |= BNXT_FLAG_UDP_RSS_CAP; 10582 bp->rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 | 10583 VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6; 10584 } 10585 } 10586 10587 static void bnxt_set_dflt_rfs(struct bnxt *bp) 10588 { 10589 struct net_device *dev = bp->dev; 10590 10591 dev->hw_features &= ~NETIF_F_NTUPLE; 10592 dev->features &= ~NETIF_F_NTUPLE; 10593 bp->flags &= ~BNXT_FLAG_RFS; 10594 if (bnxt_rfs_supported(bp)) { 10595 dev->hw_features |= NETIF_F_NTUPLE; 10596 if (bnxt_rfs_capable(bp)) { 10597 bp->flags |= BNXT_FLAG_RFS; 10598 dev->features |= NETIF_F_NTUPLE; 10599 } 10600 } 10601 } 10602 10603 static void bnxt_fw_init_one_p3(struct bnxt *bp) 10604 { 10605 struct pci_dev *pdev = bp->pdev; 10606 10607 bnxt_set_dflt_rss_hash_type(bp); 10608 bnxt_set_dflt_rfs(bp); 10609 10610 bnxt_get_wol_settings(bp); 10611 if (bp->flags & BNXT_FLAG_WOL_CAP) 10612 device_set_wakeup_enable(&pdev->dev, bp->wol); 10613 else 10614 device_set_wakeup_capable(&pdev->dev, false); 10615 10616 bnxt_hwrm_set_cache_line_size(bp, cache_line_size()); 10617 bnxt_hwrm_coal_params_qcaps(bp); 10618 } 10619 10620 static int bnxt_fw_init_one(struct bnxt *bp) 10621 { 10622 int rc; 10623 10624 rc = bnxt_fw_init_one_p1(bp); 10625 if (rc) { 10626 netdev_err(bp->dev, "Firmware init phase 1 failed\n"); 10627 return rc; 10628 } 10629 rc = bnxt_fw_init_one_p2(bp); 10630 if (rc) { 10631 netdev_err(bp->dev, "Firmware init phase 2 failed\n"); 10632 return rc; 10633 } 10634 rc = bnxt_approve_mac(bp, bp->dev->dev_addr, false); 10635 if (rc) 10636 return rc; 10637 10638 /* In case fw capabilities have changed, destroy the unneeded 10639 * reporters and create newly capable ones. 10640 */ 10641 bnxt_dl_fw_reporters_destroy(bp, false); 10642 bnxt_dl_fw_reporters_create(bp); 10643 bnxt_fw_init_one_p3(bp); 10644 return 0; 10645 } 10646 10647 static void bnxt_fw_reset_writel(struct bnxt *bp, int reg_idx) 10648 { 10649 struct bnxt_fw_health *fw_health = bp->fw_health; 10650 u32 reg = fw_health->fw_reset_seq_regs[reg_idx]; 10651 u32 val = fw_health->fw_reset_seq_vals[reg_idx]; 10652 u32 reg_type, reg_off, delay_msecs; 10653 10654 delay_msecs = fw_health->fw_reset_seq_delay_msec[reg_idx]; 10655 reg_type = BNXT_FW_HEALTH_REG_TYPE(reg); 10656 reg_off = BNXT_FW_HEALTH_REG_OFF(reg); 10657 switch (reg_type) { 10658 case BNXT_FW_HEALTH_REG_TYPE_CFG: 10659 pci_write_config_dword(bp->pdev, reg_off, val); 10660 break; 10661 case BNXT_FW_HEALTH_REG_TYPE_GRC: 10662 writel(reg_off & BNXT_GRC_BASE_MASK, 10663 bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4); 10664 reg_off = (reg_off & BNXT_GRC_OFFSET_MASK) + 0x2000; 10665 /* fall through */ 10666 case BNXT_FW_HEALTH_REG_TYPE_BAR0: 10667 writel(val, bp->bar0 + reg_off); 10668 break; 10669 case BNXT_FW_HEALTH_REG_TYPE_BAR1: 10670 writel(val, bp->bar1 + reg_off); 10671 break; 10672 } 10673 if (delay_msecs) { 10674 pci_read_config_dword(bp->pdev, 0, &val); 10675 msleep(delay_msecs); 10676 } 10677 } 10678 10679 static void bnxt_reset_all(struct bnxt *bp) 10680 { 10681 struct bnxt_fw_health *fw_health = bp->fw_health; 10682 int i, rc; 10683 10684 if (bp->fw_cap & BNXT_FW_CAP_ERR_RECOVER_RELOAD) { 10685 #ifdef CONFIG_TEE_BNXT_FW 10686 rc = tee_bnxt_fw_load(); 10687 if (rc) 10688 netdev_err(bp->dev, "Unable to reset FW rc=%d\n", rc); 10689 bp->fw_reset_timestamp = jiffies; 10690 #endif 10691 return; 10692 } 10693 10694 if (fw_health->flags & ERROR_RECOVERY_QCFG_RESP_FLAGS_HOST) { 10695 for (i = 0; i < fw_health->fw_reset_seq_cnt; i++) 10696 bnxt_fw_reset_writel(bp, i); 10697 } else if (fw_health->flags & ERROR_RECOVERY_QCFG_RESP_FLAGS_CO_CPU) { 10698 struct hwrm_fw_reset_input req = {0}; 10699 10700 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FW_RESET, -1, -1); 10701 req.resp_addr = cpu_to_le64(bp->hwrm_cmd_kong_resp_dma_addr); 10702 req.embedded_proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP; 10703 req.selfrst_status = FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP; 10704 req.flags = FW_RESET_REQ_FLAGS_RESET_GRACEFUL; 10705 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 10706 if (rc) 10707 netdev_warn(bp->dev, "Unable to reset FW rc=%d\n", rc); 10708 } 10709 bp->fw_reset_timestamp = jiffies; 10710 } 10711 10712 static void bnxt_fw_reset_task(struct work_struct *work) 10713 { 10714 struct bnxt *bp = container_of(work, struct bnxt, fw_reset_task.work); 10715 int rc; 10716 10717 if (!test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) { 10718 netdev_err(bp->dev, "bnxt_fw_reset_task() called when not in fw reset mode!\n"); 10719 return; 10720 } 10721 10722 switch (bp->fw_reset_state) { 10723 case BNXT_FW_RESET_STATE_POLL_VF: { 10724 int n = bnxt_get_registered_vfs(bp); 10725 int tmo; 10726 10727 if (n < 0) { 10728 netdev_err(bp->dev, "Firmware reset aborted, subsequent func_qcfg cmd failed, rc = %d, %d msecs since reset timestamp\n", 10729 n, jiffies_to_msecs(jiffies - 10730 bp->fw_reset_timestamp)); 10731 goto fw_reset_abort; 10732 } else if (n > 0) { 10733 if (time_after(jiffies, bp->fw_reset_timestamp + 10734 (bp->fw_reset_max_dsecs * HZ / 10))) { 10735 clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state); 10736 bp->fw_reset_state = 0; 10737 netdev_err(bp->dev, "Firmware reset aborted, bnxt_get_registered_vfs() returns %d\n", 10738 n); 10739 return; 10740 } 10741 bnxt_queue_fw_reset_work(bp, HZ / 10); 10742 return; 10743 } 10744 bp->fw_reset_timestamp = jiffies; 10745 rtnl_lock(); 10746 bnxt_fw_reset_close(bp); 10747 if (bp->fw_cap & BNXT_FW_CAP_ERR_RECOVER_RELOAD) { 10748 bp->fw_reset_state = BNXT_FW_RESET_STATE_POLL_FW_DOWN; 10749 tmo = HZ / 10; 10750 } else { 10751 bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV; 10752 tmo = bp->fw_reset_min_dsecs * HZ / 10; 10753 } 10754 rtnl_unlock(); 10755 bnxt_queue_fw_reset_work(bp, tmo); 10756 return; 10757 } 10758 case BNXT_FW_RESET_STATE_POLL_FW_DOWN: { 10759 u32 val; 10760 10761 val = bnxt_fw_health_readl(bp, BNXT_FW_HEALTH_REG); 10762 if (!(val & BNXT_FW_STATUS_SHUTDOWN) && 10763 !time_after(jiffies, bp->fw_reset_timestamp + 10764 (bp->fw_reset_max_dsecs * HZ / 10))) { 10765 bnxt_queue_fw_reset_work(bp, HZ / 5); 10766 return; 10767 } 10768 10769 if (!bp->fw_health->master) { 10770 u32 wait_dsecs = bp->fw_health->normal_func_wait_dsecs; 10771 10772 bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV; 10773 bnxt_queue_fw_reset_work(bp, wait_dsecs * HZ / 10); 10774 return; 10775 } 10776 bp->fw_reset_state = BNXT_FW_RESET_STATE_RESET_FW; 10777 } 10778 /* fall through */ 10779 case BNXT_FW_RESET_STATE_RESET_FW: 10780 bnxt_reset_all(bp); 10781 bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV; 10782 bnxt_queue_fw_reset_work(bp, bp->fw_reset_min_dsecs * HZ / 10); 10783 return; 10784 case BNXT_FW_RESET_STATE_ENABLE_DEV: 10785 if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state)) { 10786 u32 val; 10787 10788 val = bnxt_fw_health_readl(bp, 10789 BNXT_FW_RESET_INPROG_REG); 10790 if (val) 10791 netdev_warn(bp->dev, "FW reset inprog %x after min wait time.\n", 10792 val); 10793 } 10794 clear_bit(BNXT_STATE_FW_FATAL_COND, &bp->state); 10795 if (pci_enable_device(bp->pdev)) { 10796 netdev_err(bp->dev, "Cannot re-enable PCI device\n"); 10797 goto fw_reset_abort; 10798 } 10799 pci_set_master(bp->pdev); 10800 bp->fw_reset_state = BNXT_FW_RESET_STATE_POLL_FW; 10801 /* fall through */ 10802 case BNXT_FW_RESET_STATE_POLL_FW: 10803 bp->hwrm_cmd_timeout = SHORT_HWRM_CMD_TIMEOUT; 10804 rc = __bnxt_hwrm_ver_get(bp, true); 10805 if (rc) { 10806 if (time_after(jiffies, bp->fw_reset_timestamp + 10807 (bp->fw_reset_max_dsecs * HZ / 10))) { 10808 netdev_err(bp->dev, "Firmware reset aborted\n"); 10809 goto fw_reset_abort; 10810 } 10811 bnxt_queue_fw_reset_work(bp, HZ / 5); 10812 return; 10813 } 10814 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT; 10815 bp->fw_reset_state = BNXT_FW_RESET_STATE_OPENING; 10816 /* fall through */ 10817 case BNXT_FW_RESET_STATE_OPENING: 10818 while (!rtnl_trylock()) { 10819 bnxt_queue_fw_reset_work(bp, HZ / 10); 10820 return; 10821 } 10822 rc = bnxt_open(bp->dev); 10823 if (rc) { 10824 netdev_err(bp->dev, "bnxt_open_nic() failed\n"); 10825 clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state); 10826 dev_close(bp->dev); 10827 } 10828 10829 bp->fw_reset_state = 0; 10830 /* Make sure fw_reset_state is 0 before clearing the flag */ 10831 smp_mb__before_atomic(); 10832 clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state); 10833 bnxt_ulp_start(bp, rc); 10834 if (!rc) 10835 bnxt_reenable_sriov(bp); 10836 bnxt_dl_health_recovery_done(bp); 10837 bnxt_dl_health_status_update(bp, true); 10838 rtnl_unlock(); 10839 break; 10840 } 10841 return; 10842 10843 fw_reset_abort: 10844 clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state); 10845 if (bp->fw_reset_state != BNXT_FW_RESET_STATE_POLL_VF) 10846 bnxt_dl_health_status_update(bp, false); 10847 bp->fw_reset_state = 0; 10848 rtnl_lock(); 10849 dev_close(bp->dev); 10850 rtnl_unlock(); 10851 } 10852 10853 static int bnxt_init_board(struct pci_dev *pdev, struct net_device *dev) 10854 { 10855 int rc; 10856 struct bnxt *bp = netdev_priv(dev); 10857 10858 SET_NETDEV_DEV(dev, &pdev->dev); 10859 10860 /* enable device (incl. PCI PM wakeup), and bus-mastering */ 10861 rc = pci_enable_device(pdev); 10862 if (rc) { 10863 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n"); 10864 goto init_err; 10865 } 10866 10867 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 10868 dev_err(&pdev->dev, 10869 "Cannot find PCI device base address, aborting\n"); 10870 rc = -ENODEV; 10871 goto init_err_disable; 10872 } 10873 10874 rc = pci_request_regions(pdev, DRV_MODULE_NAME); 10875 if (rc) { 10876 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n"); 10877 goto init_err_disable; 10878 } 10879 10880 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) != 0 && 10881 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)) != 0) { 10882 dev_err(&pdev->dev, "System does not support DMA, aborting\n"); 10883 goto init_err_disable; 10884 } 10885 10886 pci_set_master(pdev); 10887 10888 bp->dev = dev; 10889 bp->pdev = pdev; 10890 10891 bp->bar0 = pci_ioremap_bar(pdev, 0); 10892 if (!bp->bar0) { 10893 dev_err(&pdev->dev, "Cannot map device registers, aborting\n"); 10894 rc = -ENOMEM; 10895 goto init_err_release; 10896 } 10897 10898 bp->bar1 = pci_ioremap_bar(pdev, 2); 10899 if (!bp->bar1) { 10900 dev_err(&pdev->dev, "Cannot map doorbell registers, aborting\n"); 10901 rc = -ENOMEM; 10902 goto init_err_release; 10903 } 10904 10905 bp->bar2 = pci_ioremap_bar(pdev, 4); 10906 if (!bp->bar2) { 10907 dev_err(&pdev->dev, "Cannot map bar4 registers, aborting\n"); 10908 rc = -ENOMEM; 10909 goto init_err_release; 10910 } 10911 10912 pci_enable_pcie_error_reporting(pdev); 10913 10914 INIT_WORK(&bp->sp_task, bnxt_sp_task); 10915 INIT_DELAYED_WORK(&bp->fw_reset_task, bnxt_fw_reset_task); 10916 10917 spin_lock_init(&bp->ntp_fltr_lock); 10918 #if BITS_PER_LONG == 32 10919 spin_lock_init(&bp->db_lock); 10920 #endif 10921 10922 bp->rx_ring_size = BNXT_DEFAULT_RX_RING_SIZE; 10923 bp->tx_ring_size = BNXT_DEFAULT_TX_RING_SIZE; 10924 10925 bnxt_init_dflt_coal(bp); 10926 10927 timer_setup(&bp->timer, bnxt_timer, 0); 10928 bp->current_interval = BNXT_TIMER_INTERVAL; 10929 10930 clear_bit(BNXT_STATE_OPEN, &bp->state); 10931 return 0; 10932 10933 init_err_release: 10934 bnxt_unmap_bars(bp, pdev); 10935 pci_release_regions(pdev); 10936 10937 init_err_disable: 10938 pci_disable_device(pdev); 10939 10940 init_err: 10941 return rc; 10942 } 10943 10944 /* rtnl_lock held */ 10945 static int bnxt_change_mac_addr(struct net_device *dev, void *p) 10946 { 10947 struct sockaddr *addr = p; 10948 struct bnxt *bp = netdev_priv(dev); 10949 int rc = 0; 10950 10951 if (!is_valid_ether_addr(addr->sa_data)) 10952 return -EADDRNOTAVAIL; 10953 10954 if (ether_addr_equal(addr->sa_data, dev->dev_addr)) 10955 return 0; 10956 10957 rc = bnxt_approve_mac(bp, addr->sa_data, true); 10958 if (rc) 10959 return rc; 10960 10961 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); 10962 if (netif_running(dev)) { 10963 bnxt_close_nic(bp, false, false); 10964 rc = bnxt_open_nic(bp, false, false); 10965 } 10966 10967 return rc; 10968 } 10969 10970 /* rtnl_lock held */ 10971 static int bnxt_change_mtu(struct net_device *dev, int new_mtu) 10972 { 10973 struct bnxt *bp = netdev_priv(dev); 10974 10975 if (netif_running(dev)) 10976 bnxt_close_nic(bp, true, false); 10977 10978 dev->mtu = new_mtu; 10979 bnxt_set_ring_params(bp); 10980 10981 if (netif_running(dev)) 10982 return bnxt_open_nic(bp, true, false); 10983 10984 return 0; 10985 } 10986 10987 int bnxt_setup_mq_tc(struct net_device *dev, u8 tc) 10988 { 10989 struct bnxt *bp = netdev_priv(dev); 10990 bool sh = false; 10991 int rc; 10992 10993 if (tc > bp->max_tc) { 10994 netdev_err(dev, "Too many traffic classes requested: %d. Max supported is %d.\n", 10995 tc, bp->max_tc); 10996 return -EINVAL; 10997 } 10998 10999 if (netdev_get_num_tc(dev) == tc) 11000 return 0; 11001 11002 if (bp->flags & BNXT_FLAG_SHARED_RINGS) 11003 sh = true; 11004 11005 rc = bnxt_check_rings(bp, bp->tx_nr_rings_per_tc, bp->rx_nr_rings, 11006 sh, tc, bp->tx_nr_rings_xdp); 11007 if (rc) 11008 return rc; 11009 11010 /* Needs to close the device and do hw resource re-allocations */ 11011 if (netif_running(bp->dev)) 11012 bnxt_close_nic(bp, true, false); 11013 11014 if (tc) { 11015 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tc; 11016 netdev_set_num_tc(dev, tc); 11017 } else { 11018 bp->tx_nr_rings = bp->tx_nr_rings_per_tc; 11019 netdev_reset_tc(dev); 11020 } 11021 bp->tx_nr_rings += bp->tx_nr_rings_xdp; 11022 bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) : 11023 bp->tx_nr_rings + bp->rx_nr_rings; 11024 11025 if (netif_running(bp->dev)) 11026 return bnxt_open_nic(bp, true, false); 11027 11028 return 0; 11029 } 11030 11031 static int bnxt_setup_tc_block_cb(enum tc_setup_type type, void *type_data, 11032 void *cb_priv) 11033 { 11034 struct bnxt *bp = cb_priv; 11035 11036 if (!bnxt_tc_flower_enabled(bp) || 11037 !tc_cls_can_offload_and_chain0(bp->dev, type_data)) 11038 return -EOPNOTSUPP; 11039 11040 switch (type) { 11041 case TC_SETUP_CLSFLOWER: 11042 return bnxt_tc_setup_flower(bp, bp->pf.fw_fid, type_data); 11043 default: 11044 return -EOPNOTSUPP; 11045 } 11046 } 11047 11048 LIST_HEAD(bnxt_block_cb_list); 11049 11050 static int bnxt_setup_tc(struct net_device *dev, enum tc_setup_type type, 11051 void *type_data) 11052 { 11053 struct bnxt *bp = netdev_priv(dev); 11054 11055 switch (type) { 11056 case TC_SETUP_BLOCK: 11057 return flow_block_cb_setup_simple(type_data, 11058 &bnxt_block_cb_list, 11059 bnxt_setup_tc_block_cb, 11060 bp, bp, true); 11061 case TC_SETUP_QDISC_MQPRIO: { 11062 struct tc_mqprio_qopt *mqprio = type_data; 11063 11064 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS; 11065 11066 return bnxt_setup_mq_tc(dev, mqprio->num_tc); 11067 } 11068 default: 11069 return -EOPNOTSUPP; 11070 } 11071 } 11072 11073 #ifdef CONFIG_RFS_ACCEL 11074 static bool bnxt_fltr_match(struct bnxt_ntuple_filter *f1, 11075 struct bnxt_ntuple_filter *f2) 11076 { 11077 struct flow_keys *keys1 = &f1->fkeys; 11078 struct flow_keys *keys2 = &f2->fkeys; 11079 11080 if (keys1->basic.n_proto != keys2->basic.n_proto || 11081 keys1->basic.ip_proto != keys2->basic.ip_proto) 11082 return false; 11083 11084 if (keys1->basic.n_proto == htons(ETH_P_IP)) { 11085 if (keys1->addrs.v4addrs.src != keys2->addrs.v4addrs.src || 11086 keys1->addrs.v4addrs.dst != keys2->addrs.v4addrs.dst) 11087 return false; 11088 } else { 11089 if (memcmp(&keys1->addrs.v6addrs.src, &keys2->addrs.v6addrs.src, 11090 sizeof(keys1->addrs.v6addrs.src)) || 11091 memcmp(&keys1->addrs.v6addrs.dst, &keys2->addrs.v6addrs.dst, 11092 sizeof(keys1->addrs.v6addrs.dst))) 11093 return false; 11094 } 11095 11096 if (keys1->ports.ports == keys2->ports.ports && 11097 keys1->control.flags == keys2->control.flags && 11098 ether_addr_equal(f1->src_mac_addr, f2->src_mac_addr) && 11099 ether_addr_equal(f1->dst_mac_addr, f2->dst_mac_addr)) 11100 return true; 11101 11102 return false; 11103 } 11104 11105 static int bnxt_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb, 11106 u16 rxq_index, u32 flow_id) 11107 { 11108 struct bnxt *bp = netdev_priv(dev); 11109 struct bnxt_ntuple_filter *fltr, *new_fltr; 11110 struct flow_keys *fkeys; 11111 struct ethhdr *eth = (struct ethhdr *)skb_mac_header(skb); 11112 int rc = 0, idx, bit_id, l2_idx = 0; 11113 struct hlist_head *head; 11114 u32 flags; 11115 11116 if (!ether_addr_equal(dev->dev_addr, eth->h_dest)) { 11117 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 11118 int off = 0, j; 11119 11120 netif_addr_lock_bh(dev); 11121 for (j = 0; j < vnic->uc_filter_count; j++, off += ETH_ALEN) { 11122 if (ether_addr_equal(eth->h_dest, 11123 vnic->uc_list + off)) { 11124 l2_idx = j + 1; 11125 break; 11126 } 11127 } 11128 netif_addr_unlock_bh(dev); 11129 if (!l2_idx) 11130 return -EINVAL; 11131 } 11132 new_fltr = kzalloc(sizeof(*new_fltr), GFP_ATOMIC); 11133 if (!new_fltr) 11134 return -ENOMEM; 11135 11136 fkeys = &new_fltr->fkeys; 11137 if (!skb_flow_dissect_flow_keys(skb, fkeys, 0)) { 11138 rc = -EPROTONOSUPPORT; 11139 goto err_free; 11140 } 11141 11142 if ((fkeys->basic.n_proto != htons(ETH_P_IP) && 11143 fkeys->basic.n_proto != htons(ETH_P_IPV6)) || 11144 ((fkeys->basic.ip_proto != IPPROTO_TCP) && 11145 (fkeys->basic.ip_proto != IPPROTO_UDP))) { 11146 rc = -EPROTONOSUPPORT; 11147 goto err_free; 11148 } 11149 if (fkeys->basic.n_proto == htons(ETH_P_IPV6) && 11150 bp->hwrm_spec_code < 0x10601) { 11151 rc = -EPROTONOSUPPORT; 11152 goto err_free; 11153 } 11154 flags = fkeys->control.flags; 11155 if (((flags & FLOW_DIS_ENCAPSULATION) && 11156 bp->hwrm_spec_code < 0x10601) || (flags & FLOW_DIS_IS_FRAGMENT)) { 11157 rc = -EPROTONOSUPPORT; 11158 goto err_free; 11159 } 11160 11161 memcpy(new_fltr->dst_mac_addr, eth->h_dest, ETH_ALEN); 11162 memcpy(new_fltr->src_mac_addr, eth->h_source, ETH_ALEN); 11163 11164 idx = skb_get_hash_raw(skb) & BNXT_NTP_FLTR_HASH_MASK; 11165 head = &bp->ntp_fltr_hash_tbl[idx]; 11166 rcu_read_lock(); 11167 hlist_for_each_entry_rcu(fltr, head, hash) { 11168 if (bnxt_fltr_match(fltr, new_fltr)) { 11169 rcu_read_unlock(); 11170 rc = 0; 11171 goto err_free; 11172 } 11173 } 11174 rcu_read_unlock(); 11175 11176 spin_lock_bh(&bp->ntp_fltr_lock); 11177 bit_id = bitmap_find_free_region(bp->ntp_fltr_bmap, 11178 BNXT_NTP_FLTR_MAX_FLTR, 0); 11179 if (bit_id < 0) { 11180 spin_unlock_bh(&bp->ntp_fltr_lock); 11181 rc = -ENOMEM; 11182 goto err_free; 11183 } 11184 11185 new_fltr->sw_id = (u16)bit_id; 11186 new_fltr->flow_id = flow_id; 11187 new_fltr->l2_fltr_idx = l2_idx; 11188 new_fltr->rxq = rxq_index; 11189 hlist_add_head_rcu(&new_fltr->hash, head); 11190 bp->ntp_fltr_count++; 11191 spin_unlock_bh(&bp->ntp_fltr_lock); 11192 11193 set_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event); 11194 bnxt_queue_sp_work(bp); 11195 11196 return new_fltr->sw_id; 11197 11198 err_free: 11199 kfree(new_fltr); 11200 return rc; 11201 } 11202 11203 static void bnxt_cfg_ntp_filters(struct bnxt *bp) 11204 { 11205 int i; 11206 11207 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) { 11208 struct hlist_head *head; 11209 struct hlist_node *tmp; 11210 struct bnxt_ntuple_filter *fltr; 11211 int rc; 11212 11213 head = &bp->ntp_fltr_hash_tbl[i]; 11214 hlist_for_each_entry_safe(fltr, tmp, head, hash) { 11215 bool del = false; 11216 11217 if (test_bit(BNXT_FLTR_VALID, &fltr->state)) { 11218 if (rps_may_expire_flow(bp->dev, fltr->rxq, 11219 fltr->flow_id, 11220 fltr->sw_id)) { 11221 bnxt_hwrm_cfa_ntuple_filter_free(bp, 11222 fltr); 11223 del = true; 11224 } 11225 } else { 11226 rc = bnxt_hwrm_cfa_ntuple_filter_alloc(bp, 11227 fltr); 11228 if (rc) 11229 del = true; 11230 else 11231 set_bit(BNXT_FLTR_VALID, &fltr->state); 11232 } 11233 11234 if (del) { 11235 spin_lock_bh(&bp->ntp_fltr_lock); 11236 hlist_del_rcu(&fltr->hash); 11237 bp->ntp_fltr_count--; 11238 spin_unlock_bh(&bp->ntp_fltr_lock); 11239 synchronize_rcu(); 11240 clear_bit(fltr->sw_id, bp->ntp_fltr_bmap); 11241 kfree(fltr); 11242 } 11243 } 11244 } 11245 if (test_and_clear_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event)) 11246 netdev_info(bp->dev, "Receive PF driver unload event!\n"); 11247 } 11248 11249 #else 11250 11251 static void bnxt_cfg_ntp_filters(struct bnxt *bp) 11252 { 11253 } 11254 11255 #endif /* CONFIG_RFS_ACCEL */ 11256 11257 static void bnxt_udp_tunnel_add(struct net_device *dev, 11258 struct udp_tunnel_info *ti) 11259 { 11260 struct bnxt *bp = netdev_priv(dev); 11261 11262 if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET) 11263 return; 11264 11265 if (!netif_running(dev)) 11266 return; 11267 11268 switch (ti->type) { 11269 case UDP_TUNNEL_TYPE_VXLAN: 11270 if (bp->vxlan_port_cnt && bp->vxlan_port != ti->port) 11271 return; 11272 11273 bp->vxlan_port_cnt++; 11274 if (bp->vxlan_port_cnt == 1) { 11275 bp->vxlan_port = ti->port; 11276 set_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event); 11277 bnxt_queue_sp_work(bp); 11278 } 11279 break; 11280 case UDP_TUNNEL_TYPE_GENEVE: 11281 if (bp->nge_port_cnt && bp->nge_port != ti->port) 11282 return; 11283 11284 bp->nge_port_cnt++; 11285 if (bp->nge_port_cnt == 1) { 11286 bp->nge_port = ti->port; 11287 set_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event); 11288 } 11289 break; 11290 default: 11291 return; 11292 } 11293 11294 bnxt_queue_sp_work(bp); 11295 } 11296 11297 static void bnxt_udp_tunnel_del(struct net_device *dev, 11298 struct udp_tunnel_info *ti) 11299 { 11300 struct bnxt *bp = netdev_priv(dev); 11301 11302 if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET) 11303 return; 11304 11305 if (!netif_running(dev)) 11306 return; 11307 11308 switch (ti->type) { 11309 case UDP_TUNNEL_TYPE_VXLAN: 11310 if (!bp->vxlan_port_cnt || bp->vxlan_port != ti->port) 11311 return; 11312 bp->vxlan_port_cnt--; 11313 11314 if (bp->vxlan_port_cnt != 0) 11315 return; 11316 11317 set_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event); 11318 break; 11319 case UDP_TUNNEL_TYPE_GENEVE: 11320 if (!bp->nge_port_cnt || bp->nge_port != ti->port) 11321 return; 11322 bp->nge_port_cnt--; 11323 11324 if (bp->nge_port_cnt != 0) 11325 return; 11326 11327 set_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event); 11328 break; 11329 default: 11330 return; 11331 } 11332 11333 bnxt_queue_sp_work(bp); 11334 } 11335 11336 static int bnxt_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq, 11337 struct net_device *dev, u32 filter_mask, 11338 int nlflags) 11339 { 11340 struct bnxt *bp = netdev_priv(dev); 11341 11342 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, bp->br_mode, 0, 0, 11343 nlflags, filter_mask, NULL); 11344 } 11345 11346 static int bnxt_bridge_setlink(struct net_device *dev, struct nlmsghdr *nlh, 11347 u16 flags, struct netlink_ext_ack *extack) 11348 { 11349 struct bnxt *bp = netdev_priv(dev); 11350 struct nlattr *attr, *br_spec; 11351 int rem, rc = 0; 11352 11353 if (bp->hwrm_spec_code < 0x10708 || !BNXT_SINGLE_PF(bp)) 11354 return -EOPNOTSUPP; 11355 11356 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC); 11357 if (!br_spec) 11358 return -EINVAL; 11359 11360 nla_for_each_nested(attr, br_spec, rem) { 11361 u16 mode; 11362 11363 if (nla_type(attr) != IFLA_BRIDGE_MODE) 11364 continue; 11365 11366 if (nla_len(attr) < sizeof(mode)) 11367 return -EINVAL; 11368 11369 mode = nla_get_u16(attr); 11370 if (mode == bp->br_mode) 11371 break; 11372 11373 rc = bnxt_hwrm_set_br_mode(bp, mode); 11374 if (!rc) 11375 bp->br_mode = mode; 11376 break; 11377 } 11378 return rc; 11379 } 11380 11381 int bnxt_get_port_parent_id(struct net_device *dev, 11382 struct netdev_phys_item_id *ppid) 11383 { 11384 struct bnxt *bp = netdev_priv(dev); 11385 11386 if (bp->eswitch_mode != DEVLINK_ESWITCH_MODE_SWITCHDEV) 11387 return -EOPNOTSUPP; 11388 11389 /* The PF and it's VF-reps only support the switchdev framework */ 11390 if (!BNXT_PF(bp) || !(bp->flags & BNXT_FLAG_DSN_VALID)) 11391 return -EOPNOTSUPP; 11392 11393 ppid->id_len = sizeof(bp->dsn); 11394 memcpy(ppid->id, bp->dsn, ppid->id_len); 11395 11396 return 0; 11397 } 11398 11399 static struct devlink_port *bnxt_get_devlink_port(struct net_device *dev) 11400 { 11401 struct bnxt *bp = netdev_priv(dev); 11402 11403 return &bp->dl_port; 11404 } 11405 11406 static const struct net_device_ops bnxt_netdev_ops = { 11407 .ndo_open = bnxt_open, 11408 .ndo_start_xmit = bnxt_start_xmit, 11409 .ndo_stop = bnxt_close, 11410 .ndo_get_stats64 = bnxt_get_stats64, 11411 .ndo_set_rx_mode = bnxt_set_rx_mode, 11412 .ndo_do_ioctl = bnxt_ioctl, 11413 .ndo_validate_addr = eth_validate_addr, 11414 .ndo_set_mac_address = bnxt_change_mac_addr, 11415 .ndo_change_mtu = bnxt_change_mtu, 11416 .ndo_fix_features = bnxt_fix_features, 11417 .ndo_set_features = bnxt_set_features, 11418 .ndo_tx_timeout = bnxt_tx_timeout, 11419 #ifdef CONFIG_BNXT_SRIOV 11420 .ndo_get_vf_config = bnxt_get_vf_config, 11421 .ndo_set_vf_mac = bnxt_set_vf_mac, 11422 .ndo_set_vf_vlan = bnxt_set_vf_vlan, 11423 .ndo_set_vf_rate = bnxt_set_vf_bw, 11424 .ndo_set_vf_link_state = bnxt_set_vf_link_state, 11425 .ndo_set_vf_spoofchk = bnxt_set_vf_spoofchk, 11426 .ndo_set_vf_trust = bnxt_set_vf_trust, 11427 #endif 11428 .ndo_setup_tc = bnxt_setup_tc, 11429 #ifdef CONFIG_RFS_ACCEL 11430 .ndo_rx_flow_steer = bnxt_rx_flow_steer, 11431 #endif 11432 .ndo_udp_tunnel_add = bnxt_udp_tunnel_add, 11433 .ndo_udp_tunnel_del = bnxt_udp_tunnel_del, 11434 .ndo_bpf = bnxt_xdp, 11435 .ndo_xdp_xmit = bnxt_xdp_xmit, 11436 .ndo_bridge_getlink = bnxt_bridge_getlink, 11437 .ndo_bridge_setlink = bnxt_bridge_setlink, 11438 .ndo_get_devlink_port = bnxt_get_devlink_port, 11439 }; 11440 11441 static void bnxt_remove_one(struct pci_dev *pdev) 11442 { 11443 struct net_device *dev = pci_get_drvdata(pdev); 11444 struct bnxt *bp = netdev_priv(dev); 11445 11446 if (BNXT_PF(bp)) 11447 bnxt_sriov_disable(bp); 11448 11449 bnxt_dl_fw_reporters_destroy(bp, true); 11450 if (BNXT_PF(bp)) 11451 devlink_port_type_clear(&bp->dl_port); 11452 pci_disable_pcie_error_reporting(pdev); 11453 unregister_netdev(dev); 11454 bnxt_dl_unregister(bp); 11455 bnxt_shutdown_tc(bp); 11456 bnxt_cancel_sp_work(bp); 11457 bp->sp_event = 0; 11458 11459 bnxt_clear_int_mode(bp); 11460 bnxt_hwrm_func_drv_unrgtr(bp); 11461 bnxt_free_hwrm_resources(bp); 11462 bnxt_free_hwrm_short_cmd_req(bp); 11463 bnxt_ethtool_free(bp); 11464 bnxt_dcb_free(bp); 11465 kfree(bp->edev); 11466 bp->edev = NULL; 11467 kfree(bp->fw_health); 11468 bp->fw_health = NULL; 11469 bnxt_cleanup_pci(bp); 11470 bnxt_free_ctx_mem(bp); 11471 kfree(bp->ctx); 11472 bp->ctx = NULL; 11473 bnxt_free_port_stats(bp); 11474 free_netdev(dev); 11475 } 11476 11477 static int bnxt_probe_phy(struct bnxt *bp, bool fw_dflt) 11478 { 11479 int rc = 0; 11480 struct bnxt_link_info *link_info = &bp->link_info; 11481 11482 rc = bnxt_hwrm_phy_qcaps(bp); 11483 if (rc) { 11484 netdev_err(bp->dev, "Probe phy can't get phy capabilities (rc: %x)\n", 11485 rc); 11486 return rc; 11487 } 11488 if (!fw_dflt) 11489 return 0; 11490 11491 rc = bnxt_update_link(bp, false); 11492 if (rc) { 11493 netdev_err(bp->dev, "Probe phy can't update link (rc: %x)\n", 11494 rc); 11495 return rc; 11496 } 11497 11498 /* Older firmware does not have supported_auto_speeds, so assume 11499 * that all supported speeds can be autonegotiated. 11500 */ 11501 if (link_info->auto_link_speeds && !link_info->support_auto_speeds) 11502 link_info->support_auto_speeds = link_info->support_speeds; 11503 11504 bnxt_init_ethtool_link_settings(bp); 11505 return 0; 11506 } 11507 11508 static int bnxt_get_max_irq(struct pci_dev *pdev) 11509 { 11510 u16 ctrl; 11511 11512 if (!pdev->msix_cap) 11513 return 1; 11514 11515 pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &ctrl); 11516 return (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1; 11517 } 11518 11519 static void _bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx, 11520 int *max_cp) 11521 { 11522 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 11523 int max_ring_grps = 0, max_irq; 11524 11525 *max_tx = hw_resc->max_tx_rings; 11526 *max_rx = hw_resc->max_rx_rings; 11527 *max_cp = bnxt_get_max_func_cp_rings_for_en(bp); 11528 max_irq = min_t(int, bnxt_get_max_func_irqs(bp) - 11529 bnxt_get_ulp_msix_num(bp), 11530 hw_resc->max_stat_ctxs - bnxt_get_ulp_stat_ctxs(bp)); 11531 if (!(bp->flags & BNXT_FLAG_CHIP_P5)) 11532 *max_cp = min_t(int, *max_cp, max_irq); 11533 max_ring_grps = hw_resc->max_hw_ring_grps; 11534 if (BNXT_CHIP_TYPE_NITRO_A0(bp) && BNXT_PF(bp)) { 11535 *max_cp -= 1; 11536 *max_rx -= 2; 11537 } 11538 if (bp->flags & BNXT_FLAG_AGG_RINGS) 11539 *max_rx >>= 1; 11540 if (bp->flags & BNXT_FLAG_CHIP_P5) { 11541 bnxt_trim_rings(bp, max_rx, max_tx, *max_cp, false); 11542 /* On P5 chips, max_cp output param should be available NQs */ 11543 *max_cp = max_irq; 11544 } 11545 *max_rx = min_t(int, *max_rx, max_ring_grps); 11546 } 11547 11548 int bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx, bool shared) 11549 { 11550 int rx, tx, cp; 11551 11552 _bnxt_get_max_rings(bp, &rx, &tx, &cp); 11553 *max_rx = rx; 11554 *max_tx = tx; 11555 if (!rx || !tx || !cp) 11556 return -ENOMEM; 11557 11558 return bnxt_trim_rings(bp, max_rx, max_tx, cp, shared); 11559 } 11560 11561 static int bnxt_get_dflt_rings(struct bnxt *bp, int *max_rx, int *max_tx, 11562 bool shared) 11563 { 11564 int rc; 11565 11566 rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared); 11567 if (rc && (bp->flags & BNXT_FLAG_AGG_RINGS)) { 11568 /* Not enough rings, try disabling agg rings. */ 11569 bp->flags &= ~BNXT_FLAG_AGG_RINGS; 11570 rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared); 11571 if (rc) { 11572 /* set BNXT_FLAG_AGG_RINGS back for consistency */ 11573 bp->flags |= BNXT_FLAG_AGG_RINGS; 11574 return rc; 11575 } 11576 bp->flags |= BNXT_FLAG_NO_AGG_RINGS; 11577 bp->dev->hw_features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW); 11578 bp->dev->features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW); 11579 bnxt_set_ring_params(bp); 11580 } 11581 11582 if (bp->flags & BNXT_FLAG_ROCE_CAP) { 11583 int max_cp, max_stat, max_irq; 11584 11585 /* Reserve minimum resources for RoCE */ 11586 max_cp = bnxt_get_max_func_cp_rings(bp); 11587 max_stat = bnxt_get_max_func_stat_ctxs(bp); 11588 max_irq = bnxt_get_max_func_irqs(bp); 11589 if (max_cp <= BNXT_MIN_ROCE_CP_RINGS || 11590 max_irq <= BNXT_MIN_ROCE_CP_RINGS || 11591 max_stat <= BNXT_MIN_ROCE_STAT_CTXS) 11592 return 0; 11593 11594 max_cp -= BNXT_MIN_ROCE_CP_RINGS; 11595 max_irq -= BNXT_MIN_ROCE_CP_RINGS; 11596 max_stat -= BNXT_MIN_ROCE_STAT_CTXS; 11597 max_cp = min_t(int, max_cp, max_irq); 11598 max_cp = min_t(int, max_cp, max_stat); 11599 rc = bnxt_trim_rings(bp, max_rx, max_tx, max_cp, shared); 11600 if (rc) 11601 rc = 0; 11602 } 11603 return rc; 11604 } 11605 11606 /* In initial default shared ring setting, each shared ring must have a 11607 * RX/TX ring pair. 11608 */ 11609 static void bnxt_trim_dflt_sh_rings(struct bnxt *bp) 11610 { 11611 bp->cp_nr_rings = min_t(int, bp->tx_nr_rings_per_tc, bp->rx_nr_rings); 11612 bp->rx_nr_rings = bp->cp_nr_rings; 11613 bp->tx_nr_rings_per_tc = bp->cp_nr_rings; 11614 bp->tx_nr_rings = bp->tx_nr_rings_per_tc; 11615 } 11616 11617 static int bnxt_set_dflt_rings(struct bnxt *bp, bool sh) 11618 { 11619 int dflt_rings, max_rx_rings, max_tx_rings, rc; 11620 11621 if (!bnxt_can_reserve_rings(bp)) 11622 return 0; 11623 11624 if (sh) 11625 bp->flags |= BNXT_FLAG_SHARED_RINGS; 11626 dflt_rings = is_kdump_kernel() ? 1 : netif_get_num_default_rss_queues(); 11627 /* Reduce default rings on multi-port cards so that total default 11628 * rings do not exceed CPU count. 11629 */ 11630 if (bp->port_count > 1) { 11631 int max_rings = 11632 max_t(int, num_online_cpus() / bp->port_count, 1); 11633 11634 dflt_rings = min_t(int, dflt_rings, max_rings); 11635 } 11636 rc = bnxt_get_dflt_rings(bp, &max_rx_rings, &max_tx_rings, sh); 11637 if (rc) 11638 return rc; 11639 bp->rx_nr_rings = min_t(int, dflt_rings, max_rx_rings); 11640 bp->tx_nr_rings_per_tc = min_t(int, dflt_rings, max_tx_rings); 11641 if (sh) 11642 bnxt_trim_dflt_sh_rings(bp); 11643 else 11644 bp->cp_nr_rings = bp->tx_nr_rings_per_tc + bp->rx_nr_rings; 11645 bp->tx_nr_rings = bp->tx_nr_rings_per_tc; 11646 11647 rc = __bnxt_reserve_rings(bp); 11648 if (rc) 11649 netdev_warn(bp->dev, "Unable to reserve tx rings\n"); 11650 bp->tx_nr_rings_per_tc = bp->tx_nr_rings; 11651 if (sh) 11652 bnxt_trim_dflt_sh_rings(bp); 11653 11654 /* Rings may have been trimmed, re-reserve the trimmed rings. */ 11655 if (bnxt_need_reserve_rings(bp)) { 11656 rc = __bnxt_reserve_rings(bp); 11657 if (rc) 11658 netdev_warn(bp->dev, "2nd rings reservation failed.\n"); 11659 bp->tx_nr_rings_per_tc = bp->tx_nr_rings; 11660 } 11661 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) { 11662 bp->rx_nr_rings++; 11663 bp->cp_nr_rings++; 11664 } 11665 if (rc) { 11666 bp->tx_nr_rings = 0; 11667 bp->rx_nr_rings = 0; 11668 } 11669 return rc; 11670 } 11671 11672 static int bnxt_init_dflt_ring_mode(struct bnxt *bp) 11673 { 11674 int rc; 11675 11676 if (bp->tx_nr_rings) 11677 return 0; 11678 11679 bnxt_ulp_irq_stop(bp); 11680 bnxt_clear_int_mode(bp); 11681 rc = bnxt_set_dflt_rings(bp, true); 11682 if (rc) { 11683 netdev_err(bp->dev, "Not enough rings available.\n"); 11684 goto init_dflt_ring_err; 11685 } 11686 rc = bnxt_init_int_mode(bp); 11687 if (rc) 11688 goto init_dflt_ring_err; 11689 11690 bp->tx_nr_rings_per_tc = bp->tx_nr_rings; 11691 if (bnxt_rfs_supported(bp) && bnxt_rfs_capable(bp)) { 11692 bp->flags |= BNXT_FLAG_RFS; 11693 bp->dev->features |= NETIF_F_NTUPLE; 11694 } 11695 init_dflt_ring_err: 11696 bnxt_ulp_irq_restart(bp, rc); 11697 return rc; 11698 } 11699 11700 int bnxt_restore_pf_fw_resources(struct bnxt *bp) 11701 { 11702 int rc; 11703 11704 ASSERT_RTNL(); 11705 bnxt_hwrm_func_qcaps(bp); 11706 11707 if (netif_running(bp->dev)) 11708 __bnxt_close_nic(bp, true, false); 11709 11710 bnxt_ulp_irq_stop(bp); 11711 bnxt_clear_int_mode(bp); 11712 rc = bnxt_init_int_mode(bp); 11713 bnxt_ulp_irq_restart(bp, rc); 11714 11715 if (netif_running(bp->dev)) { 11716 if (rc) 11717 dev_close(bp->dev); 11718 else 11719 rc = bnxt_open_nic(bp, true, false); 11720 } 11721 11722 return rc; 11723 } 11724 11725 static int bnxt_init_mac_addr(struct bnxt *bp) 11726 { 11727 int rc = 0; 11728 11729 if (BNXT_PF(bp)) { 11730 memcpy(bp->dev->dev_addr, bp->pf.mac_addr, ETH_ALEN); 11731 } else { 11732 #ifdef CONFIG_BNXT_SRIOV 11733 struct bnxt_vf_info *vf = &bp->vf; 11734 bool strict_approval = true; 11735 11736 if (is_valid_ether_addr(vf->mac_addr)) { 11737 /* overwrite netdev dev_addr with admin VF MAC */ 11738 memcpy(bp->dev->dev_addr, vf->mac_addr, ETH_ALEN); 11739 /* Older PF driver or firmware may not approve this 11740 * correctly. 11741 */ 11742 strict_approval = false; 11743 } else { 11744 eth_hw_addr_random(bp->dev); 11745 } 11746 rc = bnxt_approve_mac(bp, bp->dev->dev_addr, strict_approval); 11747 #endif 11748 } 11749 return rc; 11750 } 11751 11752 #define BNXT_VPD_LEN 512 11753 static void bnxt_vpd_read_info(struct bnxt *bp) 11754 { 11755 struct pci_dev *pdev = bp->pdev; 11756 int i, len, pos, ro_size; 11757 ssize_t vpd_size; 11758 u8 *vpd_data; 11759 11760 vpd_data = kmalloc(BNXT_VPD_LEN, GFP_KERNEL); 11761 if (!vpd_data) 11762 return; 11763 11764 vpd_size = pci_read_vpd(pdev, 0, BNXT_VPD_LEN, vpd_data); 11765 if (vpd_size <= 0) { 11766 netdev_err(bp->dev, "Unable to read VPD\n"); 11767 goto exit; 11768 } 11769 11770 i = pci_vpd_find_tag(vpd_data, 0, vpd_size, PCI_VPD_LRDT_RO_DATA); 11771 if (i < 0) { 11772 netdev_err(bp->dev, "VPD READ-Only not found\n"); 11773 goto exit; 11774 } 11775 11776 ro_size = pci_vpd_lrdt_size(&vpd_data[i]); 11777 i += PCI_VPD_LRDT_TAG_SIZE; 11778 if (i + ro_size > vpd_size) 11779 goto exit; 11780 11781 pos = pci_vpd_find_info_keyword(vpd_data, i, ro_size, 11782 PCI_VPD_RO_KEYWORD_PARTNO); 11783 if (pos < 0) 11784 goto read_sn; 11785 11786 len = pci_vpd_info_field_size(&vpd_data[pos]); 11787 pos += PCI_VPD_INFO_FLD_HDR_SIZE; 11788 if (len + pos > vpd_size) 11789 goto read_sn; 11790 11791 strlcpy(bp->board_partno, &vpd_data[pos], min(len, BNXT_VPD_FLD_LEN)); 11792 11793 read_sn: 11794 pos = pci_vpd_find_info_keyword(vpd_data, i, ro_size, 11795 PCI_VPD_RO_KEYWORD_SERIALNO); 11796 if (pos < 0) 11797 goto exit; 11798 11799 len = pci_vpd_info_field_size(&vpd_data[pos]); 11800 pos += PCI_VPD_INFO_FLD_HDR_SIZE; 11801 if (len + pos > vpd_size) 11802 goto exit; 11803 11804 strlcpy(bp->board_serialno, &vpd_data[pos], min(len, BNXT_VPD_FLD_LEN)); 11805 exit: 11806 kfree(vpd_data); 11807 } 11808 11809 static int bnxt_pcie_dsn_get(struct bnxt *bp, u8 dsn[]) 11810 { 11811 struct pci_dev *pdev = bp->pdev; 11812 u64 qword; 11813 11814 qword = pci_get_dsn(pdev); 11815 if (!qword) { 11816 netdev_info(bp->dev, "Unable to read adapter's DSN\n"); 11817 return -EOPNOTSUPP; 11818 } 11819 11820 put_unaligned_le64(qword, dsn); 11821 11822 bp->flags |= BNXT_FLAG_DSN_VALID; 11823 return 0; 11824 } 11825 11826 static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 11827 { 11828 struct net_device *dev; 11829 struct bnxt *bp; 11830 int rc, max_irqs; 11831 11832 if (pci_is_bridge(pdev)) 11833 return -ENODEV; 11834 11835 /* Clear any pending DMA transactions from crash kernel 11836 * while loading driver in capture kernel. 11837 */ 11838 if (is_kdump_kernel()) { 11839 pci_clear_master(pdev); 11840 pcie_flr(pdev); 11841 } 11842 11843 max_irqs = bnxt_get_max_irq(pdev); 11844 dev = alloc_etherdev_mq(sizeof(*bp), max_irqs); 11845 if (!dev) 11846 return -ENOMEM; 11847 11848 bp = netdev_priv(dev); 11849 bnxt_set_max_func_irqs(bp, max_irqs); 11850 11851 if (bnxt_vf_pciid(ent->driver_data)) 11852 bp->flags |= BNXT_FLAG_VF; 11853 11854 if (pdev->msix_cap) 11855 bp->flags |= BNXT_FLAG_MSIX_CAP; 11856 11857 rc = bnxt_init_board(pdev, dev); 11858 if (rc < 0) 11859 goto init_err_free; 11860 11861 dev->netdev_ops = &bnxt_netdev_ops; 11862 dev->watchdog_timeo = BNXT_TX_TIMEOUT; 11863 dev->ethtool_ops = &bnxt_ethtool_ops; 11864 pci_set_drvdata(pdev, dev); 11865 11866 bnxt_vpd_read_info(bp); 11867 11868 rc = bnxt_alloc_hwrm_resources(bp); 11869 if (rc) 11870 goto init_err_pci_clean; 11871 11872 mutex_init(&bp->hwrm_cmd_lock); 11873 mutex_init(&bp->link_lock); 11874 11875 rc = bnxt_fw_init_one_p1(bp); 11876 if (rc) 11877 goto init_err_pci_clean; 11878 11879 if (BNXT_CHIP_P5(bp)) 11880 bp->flags |= BNXT_FLAG_CHIP_P5; 11881 11882 rc = bnxt_fw_init_one_p2(bp); 11883 if (rc) 11884 goto init_err_pci_clean; 11885 11886 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG | 11887 NETIF_F_TSO | NETIF_F_TSO6 | 11888 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE | 11889 NETIF_F_GSO_IPXIP4 | 11890 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM | 11891 NETIF_F_GSO_PARTIAL | NETIF_F_RXHASH | 11892 NETIF_F_RXCSUM | NETIF_F_GRO; 11893 11894 if (BNXT_SUPPORTS_TPA(bp)) 11895 dev->hw_features |= NETIF_F_LRO; 11896 11897 dev->hw_enc_features = 11898 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG | 11899 NETIF_F_TSO | NETIF_F_TSO6 | 11900 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE | 11901 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM | 11902 NETIF_F_GSO_IPXIP4 | NETIF_F_GSO_PARTIAL; 11903 dev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM | 11904 NETIF_F_GSO_GRE_CSUM; 11905 dev->vlan_features = dev->hw_features | NETIF_F_HIGHDMA; 11906 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX | 11907 NETIF_F_HW_VLAN_STAG_RX | NETIF_F_HW_VLAN_STAG_TX; 11908 if (BNXT_SUPPORTS_TPA(bp)) 11909 dev->hw_features |= NETIF_F_GRO_HW; 11910 dev->features |= dev->hw_features | NETIF_F_HIGHDMA; 11911 if (dev->features & NETIF_F_GRO_HW) 11912 dev->features &= ~NETIF_F_LRO; 11913 dev->priv_flags |= IFF_UNICAST_FLT; 11914 11915 #ifdef CONFIG_BNXT_SRIOV 11916 init_waitqueue_head(&bp->sriov_cfg_wait); 11917 mutex_init(&bp->sriov_lock); 11918 #endif 11919 if (BNXT_SUPPORTS_TPA(bp)) { 11920 bp->gro_func = bnxt_gro_func_5730x; 11921 if (BNXT_CHIP_P4(bp)) 11922 bp->gro_func = bnxt_gro_func_5731x; 11923 else if (BNXT_CHIP_P5(bp)) 11924 bp->gro_func = bnxt_gro_func_5750x; 11925 } 11926 if (!BNXT_CHIP_P4_PLUS(bp)) 11927 bp->flags |= BNXT_FLAG_DOUBLE_DB; 11928 11929 bp->ulp_probe = bnxt_ulp_probe; 11930 11931 rc = bnxt_init_mac_addr(bp); 11932 if (rc) { 11933 dev_err(&pdev->dev, "Unable to initialize mac address.\n"); 11934 rc = -EADDRNOTAVAIL; 11935 goto init_err_pci_clean; 11936 } 11937 11938 if (BNXT_PF(bp)) { 11939 /* Read the adapter's DSN to use as the eswitch switch_id */ 11940 rc = bnxt_pcie_dsn_get(bp, bp->dsn); 11941 } 11942 11943 /* MTU range: 60 - FW defined max */ 11944 dev->min_mtu = ETH_ZLEN; 11945 dev->max_mtu = bp->max_mtu; 11946 11947 rc = bnxt_probe_phy(bp, true); 11948 if (rc) 11949 goto init_err_pci_clean; 11950 11951 bnxt_set_rx_skb_mode(bp, false); 11952 bnxt_set_tpa_flags(bp); 11953 bnxt_set_ring_params(bp); 11954 rc = bnxt_set_dflt_rings(bp, true); 11955 if (rc) { 11956 netdev_err(bp->dev, "Not enough rings available.\n"); 11957 rc = -ENOMEM; 11958 goto init_err_pci_clean; 11959 } 11960 11961 bnxt_fw_init_one_p3(bp); 11962 11963 if (dev->hw_features & NETIF_F_HW_VLAN_CTAG_RX) 11964 bp->flags |= BNXT_FLAG_STRIP_VLAN; 11965 11966 rc = bnxt_init_int_mode(bp); 11967 if (rc) 11968 goto init_err_pci_clean; 11969 11970 /* No TC has been set yet and rings may have been trimmed due to 11971 * limited MSIX, so we re-initialize the TX rings per TC. 11972 */ 11973 bp->tx_nr_rings_per_tc = bp->tx_nr_rings; 11974 11975 if (BNXT_PF(bp)) { 11976 if (!bnxt_pf_wq) { 11977 bnxt_pf_wq = 11978 create_singlethread_workqueue("bnxt_pf_wq"); 11979 if (!bnxt_pf_wq) { 11980 dev_err(&pdev->dev, "Unable to create workqueue.\n"); 11981 goto init_err_pci_clean; 11982 } 11983 } 11984 bnxt_init_tc(bp); 11985 } 11986 11987 bnxt_dl_register(bp); 11988 11989 rc = register_netdev(dev); 11990 if (rc) 11991 goto init_err_cleanup; 11992 11993 if (BNXT_PF(bp)) 11994 devlink_port_type_eth_set(&bp->dl_port, bp->dev); 11995 bnxt_dl_fw_reporters_create(bp); 11996 11997 netdev_info(dev, "%s found at mem %lx, node addr %pM\n", 11998 board_info[ent->driver_data].name, 11999 (long)pci_resource_start(pdev, 0), dev->dev_addr); 12000 pcie_print_link_status(pdev); 12001 12002 return 0; 12003 12004 init_err_cleanup: 12005 bnxt_dl_unregister(bp); 12006 bnxt_shutdown_tc(bp); 12007 bnxt_clear_int_mode(bp); 12008 12009 init_err_pci_clean: 12010 bnxt_hwrm_func_drv_unrgtr(bp); 12011 bnxt_free_hwrm_short_cmd_req(bp); 12012 bnxt_free_hwrm_resources(bp); 12013 kfree(bp->fw_health); 12014 bp->fw_health = NULL; 12015 bnxt_cleanup_pci(bp); 12016 bnxt_free_ctx_mem(bp); 12017 kfree(bp->ctx); 12018 bp->ctx = NULL; 12019 12020 init_err_free: 12021 free_netdev(dev); 12022 return rc; 12023 } 12024 12025 static void bnxt_shutdown(struct pci_dev *pdev) 12026 { 12027 struct net_device *dev = pci_get_drvdata(pdev); 12028 struct bnxt *bp; 12029 12030 if (!dev) 12031 return; 12032 12033 rtnl_lock(); 12034 bp = netdev_priv(dev); 12035 if (!bp) 12036 goto shutdown_exit; 12037 12038 if (netif_running(dev)) 12039 dev_close(dev); 12040 12041 bnxt_ulp_shutdown(bp); 12042 bnxt_clear_int_mode(bp); 12043 pci_disable_device(pdev); 12044 12045 if (system_state == SYSTEM_POWER_OFF) { 12046 pci_wake_from_d3(pdev, bp->wol); 12047 pci_set_power_state(pdev, PCI_D3hot); 12048 } 12049 12050 shutdown_exit: 12051 rtnl_unlock(); 12052 } 12053 12054 #ifdef CONFIG_PM_SLEEP 12055 static int bnxt_suspend(struct device *device) 12056 { 12057 struct net_device *dev = dev_get_drvdata(device); 12058 struct bnxt *bp = netdev_priv(dev); 12059 int rc = 0; 12060 12061 rtnl_lock(); 12062 bnxt_ulp_stop(bp); 12063 if (netif_running(dev)) { 12064 netif_device_detach(dev); 12065 rc = bnxt_close(dev); 12066 } 12067 bnxt_hwrm_func_drv_unrgtr(bp); 12068 pci_disable_device(bp->pdev); 12069 bnxt_free_ctx_mem(bp); 12070 kfree(bp->ctx); 12071 bp->ctx = NULL; 12072 rtnl_unlock(); 12073 return rc; 12074 } 12075 12076 static int bnxt_resume(struct device *device) 12077 { 12078 struct net_device *dev = dev_get_drvdata(device); 12079 struct bnxt *bp = netdev_priv(dev); 12080 int rc = 0; 12081 12082 rtnl_lock(); 12083 rc = pci_enable_device(bp->pdev); 12084 if (rc) { 12085 netdev_err(dev, "Cannot re-enable PCI device during resume, err = %d\n", 12086 rc); 12087 goto resume_exit; 12088 } 12089 pci_set_master(bp->pdev); 12090 if (bnxt_hwrm_ver_get(bp)) { 12091 rc = -ENODEV; 12092 goto resume_exit; 12093 } 12094 rc = bnxt_hwrm_func_reset(bp); 12095 if (rc) { 12096 rc = -EBUSY; 12097 goto resume_exit; 12098 } 12099 12100 if (bnxt_hwrm_queue_qportcfg(bp)) { 12101 rc = -ENODEV; 12102 goto resume_exit; 12103 } 12104 12105 if (bp->hwrm_spec_code >= 0x10803) { 12106 if (bnxt_alloc_ctx_mem(bp)) { 12107 rc = -ENODEV; 12108 goto resume_exit; 12109 } 12110 } 12111 if (BNXT_NEW_RM(bp)) 12112 bnxt_hwrm_func_resc_qcaps(bp, false); 12113 12114 if (bnxt_hwrm_func_drv_rgtr(bp, NULL, 0, false)) { 12115 rc = -ENODEV; 12116 goto resume_exit; 12117 } 12118 12119 bnxt_get_wol_settings(bp); 12120 if (netif_running(dev)) { 12121 rc = bnxt_open(dev); 12122 if (!rc) 12123 netif_device_attach(dev); 12124 } 12125 12126 resume_exit: 12127 bnxt_ulp_start(bp, rc); 12128 rtnl_unlock(); 12129 return rc; 12130 } 12131 12132 static SIMPLE_DEV_PM_OPS(bnxt_pm_ops, bnxt_suspend, bnxt_resume); 12133 #define BNXT_PM_OPS (&bnxt_pm_ops) 12134 12135 #else 12136 12137 #define BNXT_PM_OPS NULL 12138 12139 #endif /* CONFIG_PM_SLEEP */ 12140 12141 /** 12142 * bnxt_io_error_detected - called when PCI error is detected 12143 * @pdev: Pointer to PCI device 12144 * @state: The current pci connection state 12145 * 12146 * This function is called after a PCI bus error affecting 12147 * this device has been detected. 12148 */ 12149 static pci_ers_result_t bnxt_io_error_detected(struct pci_dev *pdev, 12150 pci_channel_state_t state) 12151 { 12152 struct net_device *netdev = pci_get_drvdata(pdev); 12153 struct bnxt *bp = netdev_priv(netdev); 12154 12155 netdev_info(netdev, "PCI I/O error detected\n"); 12156 12157 rtnl_lock(); 12158 netif_device_detach(netdev); 12159 12160 bnxt_ulp_stop(bp); 12161 12162 if (state == pci_channel_io_perm_failure) { 12163 rtnl_unlock(); 12164 return PCI_ERS_RESULT_DISCONNECT; 12165 } 12166 12167 if (netif_running(netdev)) 12168 bnxt_close(netdev); 12169 12170 pci_disable_device(pdev); 12171 rtnl_unlock(); 12172 12173 /* Request a slot slot reset. */ 12174 return PCI_ERS_RESULT_NEED_RESET; 12175 } 12176 12177 /** 12178 * bnxt_io_slot_reset - called after the pci bus has been reset. 12179 * @pdev: Pointer to PCI device 12180 * 12181 * Restart the card from scratch, as if from a cold-boot. 12182 * At this point, the card has exprienced a hard reset, 12183 * followed by fixups by BIOS, and has its config space 12184 * set up identically to what it was at cold boot. 12185 */ 12186 static pci_ers_result_t bnxt_io_slot_reset(struct pci_dev *pdev) 12187 { 12188 struct net_device *netdev = pci_get_drvdata(pdev); 12189 struct bnxt *bp = netdev_priv(netdev); 12190 int err = 0; 12191 pci_ers_result_t result = PCI_ERS_RESULT_DISCONNECT; 12192 12193 netdev_info(bp->dev, "PCI Slot Reset\n"); 12194 12195 rtnl_lock(); 12196 12197 if (pci_enable_device(pdev)) { 12198 dev_err(&pdev->dev, 12199 "Cannot re-enable PCI device after reset.\n"); 12200 } else { 12201 pci_set_master(pdev); 12202 12203 err = bnxt_hwrm_func_reset(bp); 12204 if (!err && netif_running(netdev)) 12205 err = bnxt_open(netdev); 12206 12207 if (!err) 12208 result = PCI_ERS_RESULT_RECOVERED; 12209 bnxt_ulp_start(bp, err); 12210 } 12211 12212 if (result != PCI_ERS_RESULT_RECOVERED) { 12213 if (netif_running(netdev)) 12214 dev_close(netdev); 12215 pci_disable_device(pdev); 12216 } 12217 12218 rtnl_unlock(); 12219 12220 return result; 12221 } 12222 12223 /** 12224 * bnxt_io_resume - called when traffic can start flowing again. 12225 * @pdev: Pointer to PCI device 12226 * 12227 * This callback is called when the error recovery driver tells 12228 * us that its OK to resume normal operation. 12229 */ 12230 static void bnxt_io_resume(struct pci_dev *pdev) 12231 { 12232 struct net_device *netdev = pci_get_drvdata(pdev); 12233 12234 rtnl_lock(); 12235 12236 netif_device_attach(netdev); 12237 12238 rtnl_unlock(); 12239 } 12240 12241 static const struct pci_error_handlers bnxt_err_handler = { 12242 .error_detected = bnxt_io_error_detected, 12243 .slot_reset = bnxt_io_slot_reset, 12244 .resume = bnxt_io_resume 12245 }; 12246 12247 static struct pci_driver bnxt_pci_driver = { 12248 .name = DRV_MODULE_NAME, 12249 .id_table = bnxt_pci_tbl, 12250 .probe = bnxt_init_one, 12251 .remove = bnxt_remove_one, 12252 .shutdown = bnxt_shutdown, 12253 .driver.pm = BNXT_PM_OPS, 12254 .err_handler = &bnxt_err_handler, 12255 #if defined(CONFIG_BNXT_SRIOV) 12256 .sriov_configure = bnxt_sriov_configure, 12257 #endif 12258 }; 12259 12260 static int __init bnxt_init(void) 12261 { 12262 bnxt_debug_init(); 12263 return pci_register_driver(&bnxt_pci_driver); 12264 } 12265 12266 static void __exit bnxt_exit(void) 12267 { 12268 pci_unregister_driver(&bnxt_pci_driver); 12269 if (bnxt_pf_wq) 12270 destroy_workqueue(bnxt_pf_wq); 12271 bnxt_debug_exit(); 12272 } 12273 12274 module_init(bnxt_init); 12275 module_exit(bnxt_exit); 12276