1 /* Broadcom NetXtreme-C/E network driver. 2 * 3 * Copyright (c) 2014-2016 Broadcom Corporation 4 * Copyright (c) 2016-2019 Broadcom Limited 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation. 9 */ 10 11 #include <linux/module.h> 12 13 #include <linux/stringify.h> 14 #include <linux/kernel.h> 15 #include <linux/timer.h> 16 #include <linux/errno.h> 17 #include <linux/ioport.h> 18 #include <linux/slab.h> 19 #include <linux/vmalloc.h> 20 #include <linux/interrupt.h> 21 #include <linux/pci.h> 22 #include <linux/netdevice.h> 23 #include <linux/etherdevice.h> 24 #include <linux/skbuff.h> 25 #include <linux/dma-mapping.h> 26 #include <linux/bitops.h> 27 #include <linux/io.h> 28 #include <linux/irq.h> 29 #include <linux/delay.h> 30 #include <asm/byteorder.h> 31 #include <asm/page.h> 32 #include <linux/time.h> 33 #include <linux/mii.h> 34 #include <linux/mdio.h> 35 #include <linux/if.h> 36 #include <linux/if_vlan.h> 37 #include <linux/if_bridge.h> 38 #include <linux/rtc.h> 39 #include <linux/bpf.h> 40 #include <net/ip.h> 41 #include <net/tcp.h> 42 #include <net/udp.h> 43 #include <net/checksum.h> 44 #include <net/ip6_checksum.h> 45 #include <net/udp_tunnel.h> 46 #include <linux/workqueue.h> 47 #include <linux/prefetch.h> 48 #include <linux/cache.h> 49 #include <linux/log2.h> 50 #include <linux/aer.h> 51 #include <linux/bitmap.h> 52 #include <linux/cpu_rmap.h> 53 #include <linux/cpumask.h> 54 #include <net/pkt_cls.h> 55 #include <linux/hwmon.h> 56 #include <linux/hwmon-sysfs.h> 57 #include <net/page_pool.h> 58 59 #include "bnxt_hsi.h" 60 #include "bnxt.h" 61 #include "bnxt_ulp.h" 62 #include "bnxt_sriov.h" 63 #include "bnxt_ethtool.h" 64 #include "bnxt_dcb.h" 65 #include "bnxt_xdp.h" 66 #include "bnxt_vfr.h" 67 #include "bnxt_tc.h" 68 #include "bnxt_devlink.h" 69 #include "bnxt_debugfs.h" 70 71 #define BNXT_TX_TIMEOUT (5 * HZ) 72 73 MODULE_LICENSE("GPL"); 74 MODULE_DESCRIPTION("Broadcom BCM573xx network driver"); 75 76 #define BNXT_RX_OFFSET (NET_SKB_PAD + NET_IP_ALIGN) 77 #define BNXT_RX_DMA_OFFSET NET_SKB_PAD 78 #define BNXT_RX_COPY_THRESH 256 79 80 #define BNXT_TX_PUSH_THRESH 164 81 82 enum board_idx { 83 BCM57301, 84 BCM57302, 85 BCM57304, 86 BCM57417_NPAR, 87 BCM58700, 88 BCM57311, 89 BCM57312, 90 BCM57402, 91 BCM57404, 92 BCM57406, 93 BCM57402_NPAR, 94 BCM57407, 95 BCM57412, 96 BCM57414, 97 BCM57416, 98 BCM57417, 99 BCM57412_NPAR, 100 BCM57314, 101 BCM57417_SFP, 102 BCM57416_SFP, 103 BCM57404_NPAR, 104 BCM57406_NPAR, 105 BCM57407_SFP, 106 BCM57407_NPAR, 107 BCM57414_NPAR, 108 BCM57416_NPAR, 109 BCM57452, 110 BCM57454, 111 BCM5745x_NPAR, 112 BCM57508, 113 BCM57504, 114 BCM57502, 115 BCM57508_NPAR, 116 BCM57504_NPAR, 117 BCM57502_NPAR, 118 BCM58802, 119 BCM58804, 120 BCM58808, 121 NETXTREME_E_VF, 122 NETXTREME_C_VF, 123 NETXTREME_S_VF, 124 NETXTREME_E_P5_VF, 125 }; 126 127 /* indexed by enum above */ 128 static const struct { 129 char *name; 130 } board_info[] = { 131 [BCM57301] = { "Broadcom BCM57301 NetXtreme-C 10Gb Ethernet" }, 132 [BCM57302] = { "Broadcom BCM57302 NetXtreme-C 10Gb/25Gb Ethernet" }, 133 [BCM57304] = { "Broadcom BCM57304 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" }, 134 [BCM57417_NPAR] = { "Broadcom BCM57417 NetXtreme-E Ethernet Partition" }, 135 [BCM58700] = { "Broadcom BCM58700 Nitro 1Gb/2.5Gb/10Gb Ethernet" }, 136 [BCM57311] = { "Broadcom BCM57311 NetXtreme-C 10Gb Ethernet" }, 137 [BCM57312] = { "Broadcom BCM57312 NetXtreme-C 10Gb/25Gb Ethernet" }, 138 [BCM57402] = { "Broadcom BCM57402 NetXtreme-E 10Gb Ethernet" }, 139 [BCM57404] = { "Broadcom BCM57404 NetXtreme-E 10Gb/25Gb Ethernet" }, 140 [BCM57406] = { "Broadcom BCM57406 NetXtreme-E 10GBase-T Ethernet" }, 141 [BCM57402_NPAR] = { "Broadcom BCM57402 NetXtreme-E Ethernet Partition" }, 142 [BCM57407] = { "Broadcom BCM57407 NetXtreme-E 10GBase-T Ethernet" }, 143 [BCM57412] = { "Broadcom BCM57412 NetXtreme-E 10Gb Ethernet" }, 144 [BCM57414] = { "Broadcom BCM57414 NetXtreme-E 10Gb/25Gb Ethernet" }, 145 [BCM57416] = { "Broadcom BCM57416 NetXtreme-E 10GBase-T Ethernet" }, 146 [BCM57417] = { "Broadcom BCM57417 NetXtreme-E 10GBase-T Ethernet" }, 147 [BCM57412_NPAR] = { "Broadcom BCM57412 NetXtreme-E Ethernet Partition" }, 148 [BCM57314] = { "Broadcom BCM57314 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" }, 149 [BCM57417_SFP] = { "Broadcom BCM57417 NetXtreme-E 10Gb/25Gb Ethernet" }, 150 [BCM57416_SFP] = { "Broadcom BCM57416 NetXtreme-E 10Gb Ethernet" }, 151 [BCM57404_NPAR] = { "Broadcom BCM57404 NetXtreme-E Ethernet Partition" }, 152 [BCM57406_NPAR] = { "Broadcom BCM57406 NetXtreme-E Ethernet Partition" }, 153 [BCM57407_SFP] = { "Broadcom BCM57407 NetXtreme-E 25Gb Ethernet" }, 154 [BCM57407_NPAR] = { "Broadcom BCM57407 NetXtreme-E Ethernet Partition" }, 155 [BCM57414_NPAR] = { "Broadcom BCM57414 NetXtreme-E Ethernet Partition" }, 156 [BCM57416_NPAR] = { "Broadcom BCM57416 NetXtreme-E Ethernet Partition" }, 157 [BCM57452] = { "Broadcom BCM57452 NetXtreme-E 10Gb/25Gb/40Gb/50Gb Ethernet" }, 158 [BCM57454] = { "Broadcom BCM57454 NetXtreme-E 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" }, 159 [BCM5745x_NPAR] = { "Broadcom BCM5745x NetXtreme-E Ethernet Partition" }, 160 [BCM57508] = { "Broadcom BCM57508 NetXtreme-E 10Gb/25Gb/50Gb/100Gb/200Gb Ethernet" }, 161 [BCM57504] = { "Broadcom BCM57504 NetXtreme-E 10Gb/25Gb/50Gb/100Gb/200Gb Ethernet" }, 162 [BCM57502] = { "Broadcom BCM57502 NetXtreme-E 10Gb/25Gb/50Gb Ethernet" }, 163 [BCM57508_NPAR] = { "Broadcom BCM57508 NetXtreme-E Ethernet Partition" }, 164 [BCM57504_NPAR] = { "Broadcom BCM57504 NetXtreme-E Ethernet Partition" }, 165 [BCM57502_NPAR] = { "Broadcom BCM57502 NetXtreme-E Ethernet Partition" }, 166 [BCM58802] = { "Broadcom BCM58802 NetXtreme-S 10Gb/25Gb/40Gb/50Gb Ethernet" }, 167 [BCM58804] = { "Broadcom BCM58804 NetXtreme-S 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" }, 168 [BCM58808] = { "Broadcom BCM58808 NetXtreme-S 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" }, 169 [NETXTREME_E_VF] = { "Broadcom NetXtreme-E Ethernet Virtual Function" }, 170 [NETXTREME_C_VF] = { "Broadcom NetXtreme-C Ethernet Virtual Function" }, 171 [NETXTREME_S_VF] = { "Broadcom NetXtreme-S Ethernet Virtual Function" }, 172 [NETXTREME_E_P5_VF] = { "Broadcom BCM5750X NetXtreme-E Ethernet Virtual Function" }, 173 }; 174 175 static const struct pci_device_id bnxt_pci_tbl[] = { 176 { PCI_VDEVICE(BROADCOM, 0x1604), .driver_data = BCM5745x_NPAR }, 177 { PCI_VDEVICE(BROADCOM, 0x1605), .driver_data = BCM5745x_NPAR }, 178 { PCI_VDEVICE(BROADCOM, 0x1614), .driver_data = BCM57454 }, 179 { PCI_VDEVICE(BROADCOM, 0x16c0), .driver_data = BCM57417_NPAR }, 180 { PCI_VDEVICE(BROADCOM, 0x16c8), .driver_data = BCM57301 }, 181 { PCI_VDEVICE(BROADCOM, 0x16c9), .driver_data = BCM57302 }, 182 { PCI_VDEVICE(BROADCOM, 0x16ca), .driver_data = BCM57304 }, 183 { PCI_VDEVICE(BROADCOM, 0x16cc), .driver_data = BCM57417_NPAR }, 184 { PCI_VDEVICE(BROADCOM, 0x16cd), .driver_data = BCM58700 }, 185 { PCI_VDEVICE(BROADCOM, 0x16ce), .driver_data = BCM57311 }, 186 { PCI_VDEVICE(BROADCOM, 0x16cf), .driver_data = BCM57312 }, 187 { PCI_VDEVICE(BROADCOM, 0x16d0), .driver_data = BCM57402 }, 188 { PCI_VDEVICE(BROADCOM, 0x16d1), .driver_data = BCM57404 }, 189 { PCI_VDEVICE(BROADCOM, 0x16d2), .driver_data = BCM57406 }, 190 { PCI_VDEVICE(BROADCOM, 0x16d4), .driver_data = BCM57402_NPAR }, 191 { PCI_VDEVICE(BROADCOM, 0x16d5), .driver_data = BCM57407 }, 192 { PCI_VDEVICE(BROADCOM, 0x16d6), .driver_data = BCM57412 }, 193 { PCI_VDEVICE(BROADCOM, 0x16d7), .driver_data = BCM57414 }, 194 { PCI_VDEVICE(BROADCOM, 0x16d8), .driver_data = BCM57416 }, 195 { PCI_VDEVICE(BROADCOM, 0x16d9), .driver_data = BCM57417 }, 196 { PCI_VDEVICE(BROADCOM, 0x16de), .driver_data = BCM57412_NPAR }, 197 { PCI_VDEVICE(BROADCOM, 0x16df), .driver_data = BCM57314 }, 198 { PCI_VDEVICE(BROADCOM, 0x16e2), .driver_data = BCM57417_SFP }, 199 { PCI_VDEVICE(BROADCOM, 0x16e3), .driver_data = BCM57416_SFP }, 200 { PCI_VDEVICE(BROADCOM, 0x16e7), .driver_data = BCM57404_NPAR }, 201 { PCI_VDEVICE(BROADCOM, 0x16e8), .driver_data = BCM57406_NPAR }, 202 { PCI_VDEVICE(BROADCOM, 0x16e9), .driver_data = BCM57407_SFP }, 203 { PCI_VDEVICE(BROADCOM, 0x16ea), .driver_data = BCM57407_NPAR }, 204 { PCI_VDEVICE(BROADCOM, 0x16eb), .driver_data = BCM57412_NPAR }, 205 { PCI_VDEVICE(BROADCOM, 0x16ec), .driver_data = BCM57414_NPAR }, 206 { PCI_VDEVICE(BROADCOM, 0x16ed), .driver_data = BCM57414_NPAR }, 207 { PCI_VDEVICE(BROADCOM, 0x16ee), .driver_data = BCM57416_NPAR }, 208 { PCI_VDEVICE(BROADCOM, 0x16ef), .driver_data = BCM57416_NPAR }, 209 { PCI_VDEVICE(BROADCOM, 0x16f0), .driver_data = BCM58808 }, 210 { PCI_VDEVICE(BROADCOM, 0x16f1), .driver_data = BCM57452 }, 211 { PCI_VDEVICE(BROADCOM, 0x1750), .driver_data = BCM57508 }, 212 { PCI_VDEVICE(BROADCOM, 0x1751), .driver_data = BCM57504 }, 213 { PCI_VDEVICE(BROADCOM, 0x1752), .driver_data = BCM57502 }, 214 { PCI_VDEVICE(BROADCOM, 0x1800), .driver_data = BCM57508_NPAR }, 215 { PCI_VDEVICE(BROADCOM, 0x1801), .driver_data = BCM57504_NPAR }, 216 { PCI_VDEVICE(BROADCOM, 0x1802), .driver_data = BCM57502_NPAR }, 217 { PCI_VDEVICE(BROADCOM, 0x1803), .driver_data = BCM57508_NPAR }, 218 { PCI_VDEVICE(BROADCOM, 0x1804), .driver_data = BCM57504_NPAR }, 219 { PCI_VDEVICE(BROADCOM, 0x1805), .driver_data = BCM57502_NPAR }, 220 { PCI_VDEVICE(BROADCOM, 0xd802), .driver_data = BCM58802 }, 221 { PCI_VDEVICE(BROADCOM, 0xd804), .driver_data = BCM58804 }, 222 #ifdef CONFIG_BNXT_SRIOV 223 { PCI_VDEVICE(BROADCOM, 0x1606), .driver_data = NETXTREME_E_VF }, 224 { PCI_VDEVICE(BROADCOM, 0x1609), .driver_data = NETXTREME_E_VF }, 225 { PCI_VDEVICE(BROADCOM, 0x16c1), .driver_data = NETXTREME_E_VF }, 226 { PCI_VDEVICE(BROADCOM, 0x16cb), .driver_data = NETXTREME_C_VF }, 227 { PCI_VDEVICE(BROADCOM, 0x16d3), .driver_data = NETXTREME_E_VF }, 228 { PCI_VDEVICE(BROADCOM, 0x16dc), .driver_data = NETXTREME_E_VF }, 229 { PCI_VDEVICE(BROADCOM, 0x16e1), .driver_data = NETXTREME_C_VF }, 230 { PCI_VDEVICE(BROADCOM, 0x16e5), .driver_data = NETXTREME_C_VF }, 231 { PCI_VDEVICE(BROADCOM, 0x1806), .driver_data = NETXTREME_E_P5_VF }, 232 { PCI_VDEVICE(BROADCOM, 0x1807), .driver_data = NETXTREME_E_P5_VF }, 233 { PCI_VDEVICE(BROADCOM, 0xd800), .driver_data = NETXTREME_S_VF }, 234 #endif 235 { 0 } 236 }; 237 238 MODULE_DEVICE_TABLE(pci, bnxt_pci_tbl); 239 240 static const u16 bnxt_vf_req_snif[] = { 241 HWRM_FUNC_CFG, 242 HWRM_FUNC_VF_CFG, 243 HWRM_PORT_PHY_QCFG, 244 HWRM_CFA_L2_FILTER_ALLOC, 245 }; 246 247 static const u16 bnxt_async_events_arr[] = { 248 ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE, 249 ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE, 250 ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD, 251 ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED, 252 ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE, 253 ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE, 254 ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE, 255 ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY, 256 ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY, 257 }; 258 259 static struct workqueue_struct *bnxt_pf_wq; 260 261 static bool bnxt_vf_pciid(enum board_idx idx) 262 { 263 return (idx == NETXTREME_C_VF || idx == NETXTREME_E_VF || 264 idx == NETXTREME_S_VF || idx == NETXTREME_E_P5_VF); 265 } 266 267 #define DB_CP_REARM_FLAGS (DB_KEY_CP | DB_IDX_VALID) 268 #define DB_CP_FLAGS (DB_KEY_CP | DB_IDX_VALID | DB_IRQ_DIS) 269 #define DB_CP_IRQ_DIS_FLAGS (DB_KEY_CP | DB_IRQ_DIS) 270 271 #define BNXT_CP_DB_IRQ_DIS(db) \ 272 writel(DB_CP_IRQ_DIS_FLAGS, db) 273 274 #define BNXT_DB_CQ(db, idx) \ 275 writel(DB_CP_FLAGS | RING_CMP(idx), (db)->doorbell) 276 277 #define BNXT_DB_NQ_P5(db, idx) \ 278 writeq((db)->db_key64 | DBR_TYPE_NQ | RING_CMP(idx), (db)->doorbell) 279 280 #define BNXT_DB_CQ_ARM(db, idx) \ 281 writel(DB_CP_REARM_FLAGS | RING_CMP(idx), (db)->doorbell) 282 283 #define BNXT_DB_NQ_ARM_P5(db, idx) \ 284 writeq((db)->db_key64 | DBR_TYPE_NQ_ARM | RING_CMP(idx), (db)->doorbell) 285 286 static void bnxt_db_nq(struct bnxt *bp, struct bnxt_db_info *db, u32 idx) 287 { 288 if (bp->flags & BNXT_FLAG_CHIP_P5) 289 BNXT_DB_NQ_P5(db, idx); 290 else 291 BNXT_DB_CQ(db, idx); 292 } 293 294 static void bnxt_db_nq_arm(struct bnxt *bp, struct bnxt_db_info *db, u32 idx) 295 { 296 if (bp->flags & BNXT_FLAG_CHIP_P5) 297 BNXT_DB_NQ_ARM_P5(db, idx); 298 else 299 BNXT_DB_CQ_ARM(db, idx); 300 } 301 302 static void bnxt_db_cq(struct bnxt *bp, struct bnxt_db_info *db, u32 idx) 303 { 304 if (bp->flags & BNXT_FLAG_CHIP_P5) 305 writeq(db->db_key64 | DBR_TYPE_CQ_ARMALL | RING_CMP(idx), 306 db->doorbell); 307 else 308 BNXT_DB_CQ(db, idx); 309 } 310 311 const u16 bnxt_lhint_arr[] = { 312 TX_BD_FLAGS_LHINT_512_AND_SMALLER, 313 TX_BD_FLAGS_LHINT_512_TO_1023, 314 TX_BD_FLAGS_LHINT_1024_TO_2047, 315 TX_BD_FLAGS_LHINT_1024_TO_2047, 316 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 317 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 318 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 319 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 320 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 321 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 322 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 323 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 324 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 325 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 326 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 327 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 328 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 329 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 330 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 331 }; 332 333 static u16 bnxt_xmit_get_cfa_action(struct sk_buff *skb) 334 { 335 struct metadata_dst *md_dst = skb_metadata_dst(skb); 336 337 if (!md_dst || md_dst->type != METADATA_HW_PORT_MUX) 338 return 0; 339 340 return md_dst->u.port_info.port_id; 341 } 342 343 static netdev_tx_t bnxt_start_xmit(struct sk_buff *skb, struct net_device *dev) 344 { 345 struct bnxt *bp = netdev_priv(dev); 346 struct tx_bd *txbd; 347 struct tx_bd_ext *txbd1; 348 struct netdev_queue *txq; 349 int i; 350 dma_addr_t mapping; 351 unsigned int length, pad = 0; 352 u32 len, free_size, vlan_tag_flags, cfa_action, flags; 353 u16 prod, last_frag; 354 struct pci_dev *pdev = bp->pdev; 355 struct bnxt_tx_ring_info *txr; 356 struct bnxt_sw_tx_bd *tx_buf; 357 358 i = skb_get_queue_mapping(skb); 359 if (unlikely(i >= bp->tx_nr_rings)) { 360 dev_kfree_skb_any(skb); 361 return NETDEV_TX_OK; 362 } 363 364 txq = netdev_get_tx_queue(dev, i); 365 txr = &bp->tx_ring[bp->tx_ring_map[i]]; 366 prod = txr->tx_prod; 367 368 free_size = bnxt_tx_avail(bp, txr); 369 if (unlikely(free_size < skb_shinfo(skb)->nr_frags + 2)) { 370 netif_tx_stop_queue(txq); 371 return NETDEV_TX_BUSY; 372 } 373 374 length = skb->len; 375 len = skb_headlen(skb); 376 last_frag = skb_shinfo(skb)->nr_frags; 377 378 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)]; 379 380 txbd->tx_bd_opaque = prod; 381 382 tx_buf = &txr->tx_buf_ring[prod]; 383 tx_buf->skb = skb; 384 tx_buf->nr_frags = last_frag; 385 386 vlan_tag_flags = 0; 387 cfa_action = bnxt_xmit_get_cfa_action(skb); 388 if (skb_vlan_tag_present(skb)) { 389 vlan_tag_flags = TX_BD_CFA_META_KEY_VLAN | 390 skb_vlan_tag_get(skb); 391 /* Currently supports 8021Q, 8021AD vlan offloads 392 * QINQ1, QINQ2, QINQ3 vlan headers are deprecated 393 */ 394 if (skb->vlan_proto == htons(ETH_P_8021Q)) 395 vlan_tag_flags |= 1 << TX_BD_CFA_META_TPID_SHIFT; 396 } 397 398 if (free_size == bp->tx_ring_size && length <= bp->tx_push_thresh) { 399 struct tx_push_buffer *tx_push_buf = txr->tx_push; 400 struct tx_push_bd *tx_push = &tx_push_buf->push_bd; 401 struct tx_bd_ext *tx_push1 = &tx_push->txbd2; 402 void __iomem *db = txr->tx_db.doorbell; 403 void *pdata = tx_push_buf->data; 404 u64 *end; 405 int j, push_len; 406 407 /* Set COAL_NOW to be ready quickly for the next push */ 408 tx_push->tx_bd_len_flags_type = 409 cpu_to_le32((length << TX_BD_LEN_SHIFT) | 410 TX_BD_TYPE_LONG_TX_BD | 411 TX_BD_FLAGS_LHINT_512_AND_SMALLER | 412 TX_BD_FLAGS_COAL_NOW | 413 TX_BD_FLAGS_PACKET_END | 414 (2 << TX_BD_FLAGS_BD_CNT_SHIFT)); 415 416 if (skb->ip_summed == CHECKSUM_PARTIAL) 417 tx_push1->tx_bd_hsize_lflags = 418 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM); 419 else 420 tx_push1->tx_bd_hsize_lflags = 0; 421 422 tx_push1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags); 423 tx_push1->tx_bd_cfa_action = 424 cpu_to_le32(cfa_action << TX_BD_CFA_ACTION_SHIFT); 425 426 end = pdata + length; 427 end = PTR_ALIGN(end, 8) - 1; 428 *end = 0; 429 430 skb_copy_from_linear_data(skb, pdata, len); 431 pdata += len; 432 for (j = 0; j < last_frag; j++) { 433 skb_frag_t *frag = &skb_shinfo(skb)->frags[j]; 434 void *fptr; 435 436 fptr = skb_frag_address_safe(frag); 437 if (!fptr) 438 goto normal_tx; 439 440 memcpy(pdata, fptr, skb_frag_size(frag)); 441 pdata += skb_frag_size(frag); 442 } 443 444 txbd->tx_bd_len_flags_type = tx_push->tx_bd_len_flags_type; 445 txbd->tx_bd_haddr = txr->data_mapping; 446 prod = NEXT_TX(prod); 447 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)]; 448 memcpy(txbd, tx_push1, sizeof(*txbd)); 449 prod = NEXT_TX(prod); 450 tx_push->doorbell = 451 cpu_to_le32(DB_KEY_TX_PUSH | DB_LONG_TX_PUSH | prod); 452 txr->tx_prod = prod; 453 454 tx_buf->is_push = 1; 455 netdev_tx_sent_queue(txq, skb->len); 456 wmb(); /* Sync is_push and byte queue before pushing data */ 457 458 push_len = (length + sizeof(*tx_push) + 7) / 8; 459 if (push_len > 16) { 460 __iowrite64_copy(db, tx_push_buf, 16); 461 __iowrite32_copy(db + 4, tx_push_buf + 1, 462 (push_len - 16) << 1); 463 } else { 464 __iowrite64_copy(db, tx_push_buf, push_len); 465 } 466 467 goto tx_done; 468 } 469 470 normal_tx: 471 if (length < BNXT_MIN_PKT_SIZE) { 472 pad = BNXT_MIN_PKT_SIZE - length; 473 if (skb_pad(skb, pad)) { 474 /* SKB already freed. */ 475 tx_buf->skb = NULL; 476 return NETDEV_TX_OK; 477 } 478 length = BNXT_MIN_PKT_SIZE; 479 } 480 481 mapping = dma_map_single(&pdev->dev, skb->data, len, DMA_TO_DEVICE); 482 483 if (unlikely(dma_mapping_error(&pdev->dev, mapping))) { 484 dev_kfree_skb_any(skb); 485 tx_buf->skb = NULL; 486 return NETDEV_TX_OK; 487 } 488 489 dma_unmap_addr_set(tx_buf, mapping, mapping); 490 flags = (len << TX_BD_LEN_SHIFT) | TX_BD_TYPE_LONG_TX_BD | 491 ((last_frag + 2) << TX_BD_FLAGS_BD_CNT_SHIFT); 492 493 txbd->tx_bd_haddr = cpu_to_le64(mapping); 494 495 prod = NEXT_TX(prod); 496 txbd1 = (struct tx_bd_ext *) 497 &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)]; 498 499 txbd1->tx_bd_hsize_lflags = 0; 500 if (skb_is_gso(skb)) { 501 u32 hdr_len; 502 503 if (skb->encapsulation) 504 hdr_len = skb_inner_network_offset(skb) + 505 skb_inner_network_header_len(skb) + 506 inner_tcp_hdrlen(skb); 507 else 508 hdr_len = skb_transport_offset(skb) + 509 tcp_hdrlen(skb); 510 511 txbd1->tx_bd_hsize_lflags = cpu_to_le32(TX_BD_FLAGS_LSO | 512 TX_BD_FLAGS_T_IPID | 513 (hdr_len << (TX_BD_HSIZE_SHIFT - 1))); 514 length = skb_shinfo(skb)->gso_size; 515 txbd1->tx_bd_mss = cpu_to_le32(length); 516 length += hdr_len; 517 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 518 txbd1->tx_bd_hsize_lflags = 519 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM); 520 txbd1->tx_bd_mss = 0; 521 } 522 523 length >>= 9; 524 if (unlikely(length >= ARRAY_SIZE(bnxt_lhint_arr))) { 525 dev_warn_ratelimited(&pdev->dev, "Dropped oversize %d bytes TX packet.\n", 526 skb->len); 527 i = 0; 528 goto tx_dma_error; 529 } 530 flags |= bnxt_lhint_arr[length]; 531 txbd->tx_bd_len_flags_type = cpu_to_le32(flags); 532 533 txbd1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags); 534 txbd1->tx_bd_cfa_action = 535 cpu_to_le32(cfa_action << TX_BD_CFA_ACTION_SHIFT); 536 for (i = 0; i < last_frag; i++) { 537 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 538 539 prod = NEXT_TX(prod); 540 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)]; 541 542 len = skb_frag_size(frag); 543 mapping = skb_frag_dma_map(&pdev->dev, frag, 0, len, 544 DMA_TO_DEVICE); 545 546 if (unlikely(dma_mapping_error(&pdev->dev, mapping))) 547 goto tx_dma_error; 548 549 tx_buf = &txr->tx_buf_ring[prod]; 550 dma_unmap_addr_set(tx_buf, mapping, mapping); 551 552 txbd->tx_bd_haddr = cpu_to_le64(mapping); 553 554 flags = len << TX_BD_LEN_SHIFT; 555 txbd->tx_bd_len_flags_type = cpu_to_le32(flags); 556 } 557 558 flags &= ~TX_BD_LEN; 559 txbd->tx_bd_len_flags_type = 560 cpu_to_le32(((len + pad) << TX_BD_LEN_SHIFT) | flags | 561 TX_BD_FLAGS_PACKET_END); 562 563 netdev_tx_sent_queue(txq, skb->len); 564 565 /* Sync BD data before updating doorbell */ 566 wmb(); 567 568 prod = NEXT_TX(prod); 569 txr->tx_prod = prod; 570 571 if (!netdev_xmit_more() || netif_xmit_stopped(txq)) 572 bnxt_db_write(bp, &txr->tx_db, prod); 573 574 tx_done: 575 576 if (unlikely(bnxt_tx_avail(bp, txr) <= MAX_SKB_FRAGS + 1)) { 577 if (netdev_xmit_more() && !tx_buf->is_push) 578 bnxt_db_write(bp, &txr->tx_db, prod); 579 580 netif_tx_stop_queue(txq); 581 582 /* netif_tx_stop_queue() must be done before checking 583 * tx index in bnxt_tx_avail() below, because in 584 * bnxt_tx_int(), we update tx index before checking for 585 * netif_tx_queue_stopped(). 586 */ 587 smp_mb(); 588 if (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh) 589 netif_tx_wake_queue(txq); 590 } 591 return NETDEV_TX_OK; 592 593 tx_dma_error: 594 last_frag = i; 595 596 /* start back at beginning and unmap skb */ 597 prod = txr->tx_prod; 598 tx_buf = &txr->tx_buf_ring[prod]; 599 tx_buf->skb = NULL; 600 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping), 601 skb_headlen(skb), PCI_DMA_TODEVICE); 602 prod = NEXT_TX(prod); 603 604 /* unmap remaining mapped pages */ 605 for (i = 0; i < last_frag; i++) { 606 prod = NEXT_TX(prod); 607 tx_buf = &txr->tx_buf_ring[prod]; 608 dma_unmap_page(&pdev->dev, dma_unmap_addr(tx_buf, mapping), 609 skb_frag_size(&skb_shinfo(skb)->frags[i]), 610 PCI_DMA_TODEVICE); 611 } 612 613 dev_kfree_skb_any(skb); 614 return NETDEV_TX_OK; 615 } 616 617 static void bnxt_tx_int(struct bnxt *bp, struct bnxt_napi *bnapi, int nr_pkts) 618 { 619 struct bnxt_tx_ring_info *txr = bnapi->tx_ring; 620 struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, txr->txq_index); 621 u16 cons = txr->tx_cons; 622 struct pci_dev *pdev = bp->pdev; 623 int i; 624 unsigned int tx_bytes = 0; 625 626 for (i = 0; i < nr_pkts; i++) { 627 struct bnxt_sw_tx_bd *tx_buf; 628 struct sk_buff *skb; 629 int j, last; 630 631 tx_buf = &txr->tx_buf_ring[cons]; 632 cons = NEXT_TX(cons); 633 skb = tx_buf->skb; 634 tx_buf->skb = NULL; 635 636 if (tx_buf->is_push) { 637 tx_buf->is_push = 0; 638 goto next_tx_int; 639 } 640 641 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping), 642 skb_headlen(skb), PCI_DMA_TODEVICE); 643 last = tx_buf->nr_frags; 644 645 for (j = 0; j < last; j++) { 646 cons = NEXT_TX(cons); 647 tx_buf = &txr->tx_buf_ring[cons]; 648 dma_unmap_page( 649 &pdev->dev, 650 dma_unmap_addr(tx_buf, mapping), 651 skb_frag_size(&skb_shinfo(skb)->frags[j]), 652 PCI_DMA_TODEVICE); 653 } 654 655 next_tx_int: 656 cons = NEXT_TX(cons); 657 658 tx_bytes += skb->len; 659 dev_kfree_skb_any(skb); 660 } 661 662 netdev_tx_completed_queue(txq, nr_pkts, tx_bytes); 663 txr->tx_cons = cons; 664 665 /* Need to make the tx_cons update visible to bnxt_start_xmit() 666 * before checking for netif_tx_queue_stopped(). Without the 667 * memory barrier, there is a small possibility that bnxt_start_xmit() 668 * will miss it and cause the queue to be stopped forever. 669 */ 670 smp_mb(); 671 672 if (unlikely(netif_tx_queue_stopped(txq)) && 673 (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)) { 674 __netif_tx_lock(txq, smp_processor_id()); 675 if (netif_tx_queue_stopped(txq) && 676 bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh && 677 txr->dev_state != BNXT_DEV_STATE_CLOSING) 678 netif_tx_wake_queue(txq); 679 __netif_tx_unlock(txq); 680 } 681 } 682 683 static struct page *__bnxt_alloc_rx_page(struct bnxt *bp, dma_addr_t *mapping, 684 struct bnxt_rx_ring_info *rxr, 685 gfp_t gfp) 686 { 687 struct device *dev = &bp->pdev->dev; 688 struct page *page; 689 690 page = page_pool_dev_alloc_pages(rxr->page_pool); 691 if (!page) 692 return NULL; 693 694 *mapping = dma_map_page_attrs(dev, page, 0, PAGE_SIZE, bp->rx_dir, 695 DMA_ATTR_WEAK_ORDERING); 696 if (dma_mapping_error(dev, *mapping)) { 697 page_pool_recycle_direct(rxr->page_pool, page); 698 return NULL; 699 } 700 *mapping += bp->rx_dma_offset; 701 return page; 702 } 703 704 static inline u8 *__bnxt_alloc_rx_data(struct bnxt *bp, dma_addr_t *mapping, 705 gfp_t gfp) 706 { 707 u8 *data; 708 struct pci_dev *pdev = bp->pdev; 709 710 data = kmalloc(bp->rx_buf_size, gfp); 711 if (!data) 712 return NULL; 713 714 *mapping = dma_map_single_attrs(&pdev->dev, data + bp->rx_dma_offset, 715 bp->rx_buf_use_size, bp->rx_dir, 716 DMA_ATTR_WEAK_ORDERING); 717 718 if (dma_mapping_error(&pdev->dev, *mapping)) { 719 kfree(data); 720 data = NULL; 721 } 722 return data; 723 } 724 725 int bnxt_alloc_rx_data(struct bnxt *bp, struct bnxt_rx_ring_info *rxr, 726 u16 prod, gfp_t gfp) 727 { 728 struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)]; 729 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[prod]; 730 dma_addr_t mapping; 731 732 if (BNXT_RX_PAGE_MODE(bp)) { 733 struct page *page = 734 __bnxt_alloc_rx_page(bp, &mapping, rxr, gfp); 735 736 if (!page) 737 return -ENOMEM; 738 739 rx_buf->data = page; 740 rx_buf->data_ptr = page_address(page) + bp->rx_offset; 741 } else { 742 u8 *data = __bnxt_alloc_rx_data(bp, &mapping, gfp); 743 744 if (!data) 745 return -ENOMEM; 746 747 rx_buf->data = data; 748 rx_buf->data_ptr = data + bp->rx_offset; 749 } 750 rx_buf->mapping = mapping; 751 752 rxbd->rx_bd_haddr = cpu_to_le64(mapping); 753 return 0; 754 } 755 756 void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons, void *data) 757 { 758 u16 prod = rxr->rx_prod; 759 struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf; 760 struct rx_bd *cons_bd, *prod_bd; 761 762 prod_rx_buf = &rxr->rx_buf_ring[prod]; 763 cons_rx_buf = &rxr->rx_buf_ring[cons]; 764 765 prod_rx_buf->data = data; 766 prod_rx_buf->data_ptr = cons_rx_buf->data_ptr; 767 768 prod_rx_buf->mapping = cons_rx_buf->mapping; 769 770 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)]; 771 cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)]; 772 773 prod_bd->rx_bd_haddr = cons_bd->rx_bd_haddr; 774 } 775 776 static inline u16 bnxt_find_next_agg_idx(struct bnxt_rx_ring_info *rxr, u16 idx) 777 { 778 u16 next, max = rxr->rx_agg_bmap_size; 779 780 next = find_next_zero_bit(rxr->rx_agg_bmap, max, idx); 781 if (next >= max) 782 next = find_first_zero_bit(rxr->rx_agg_bmap, max); 783 return next; 784 } 785 786 static inline int bnxt_alloc_rx_page(struct bnxt *bp, 787 struct bnxt_rx_ring_info *rxr, 788 u16 prod, gfp_t gfp) 789 { 790 struct rx_bd *rxbd = 791 &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)]; 792 struct bnxt_sw_rx_agg_bd *rx_agg_buf; 793 struct pci_dev *pdev = bp->pdev; 794 struct page *page; 795 dma_addr_t mapping; 796 u16 sw_prod = rxr->rx_sw_agg_prod; 797 unsigned int offset = 0; 798 799 if (PAGE_SIZE > BNXT_RX_PAGE_SIZE) { 800 page = rxr->rx_page; 801 if (!page) { 802 page = alloc_page(gfp); 803 if (!page) 804 return -ENOMEM; 805 rxr->rx_page = page; 806 rxr->rx_page_offset = 0; 807 } 808 offset = rxr->rx_page_offset; 809 rxr->rx_page_offset += BNXT_RX_PAGE_SIZE; 810 if (rxr->rx_page_offset == PAGE_SIZE) 811 rxr->rx_page = NULL; 812 else 813 get_page(page); 814 } else { 815 page = alloc_page(gfp); 816 if (!page) 817 return -ENOMEM; 818 } 819 820 mapping = dma_map_page_attrs(&pdev->dev, page, offset, 821 BNXT_RX_PAGE_SIZE, PCI_DMA_FROMDEVICE, 822 DMA_ATTR_WEAK_ORDERING); 823 if (dma_mapping_error(&pdev->dev, mapping)) { 824 __free_page(page); 825 return -EIO; 826 } 827 828 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap))) 829 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod); 830 831 __set_bit(sw_prod, rxr->rx_agg_bmap); 832 rx_agg_buf = &rxr->rx_agg_ring[sw_prod]; 833 rxr->rx_sw_agg_prod = NEXT_RX_AGG(sw_prod); 834 835 rx_agg_buf->page = page; 836 rx_agg_buf->offset = offset; 837 rx_agg_buf->mapping = mapping; 838 rxbd->rx_bd_haddr = cpu_to_le64(mapping); 839 rxbd->rx_bd_opaque = sw_prod; 840 return 0; 841 } 842 843 static struct rx_agg_cmp *bnxt_get_agg(struct bnxt *bp, 844 struct bnxt_cp_ring_info *cpr, 845 u16 cp_cons, u16 curr) 846 { 847 struct rx_agg_cmp *agg; 848 849 cp_cons = RING_CMP(ADV_RAW_CMP(cp_cons, curr)); 850 agg = (struct rx_agg_cmp *) 851 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 852 return agg; 853 } 854 855 static struct rx_agg_cmp *bnxt_get_tpa_agg_p5(struct bnxt *bp, 856 struct bnxt_rx_ring_info *rxr, 857 u16 agg_id, u16 curr) 858 { 859 struct bnxt_tpa_info *tpa_info = &rxr->rx_tpa[agg_id]; 860 861 return &tpa_info->agg_arr[curr]; 862 } 863 864 static void bnxt_reuse_rx_agg_bufs(struct bnxt_cp_ring_info *cpr, u16 idx, 865 u16 start, u32 agg_bufs, bool tpa) 866 { 867 struct bnxt_napi *bnapi = cpr->bnapi; 868 struct bnxt *bp = bnapi->bp; 869 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 870 u16 prod = rxr->rx_agg_prod; 871 u16 sw_prod = rxr->rx_sw_agg_prod; 872 bool p5_tpa = false; 873 u32 i; 874 875 if ((bp->flags & BNXT_FLAG_CHIP_P5) && tpa) 876 p5_tpa = true; 877 878 for (i = 0; i < agg_bufs; i++) { 879 u16 cons; 880 struct rx_agg_cmp *agg; 881 struct bnxt_sw_rx_agg_bd *cons_rx_buf, *prod_rx_buf; 882 struct rx_bd *prod_bd; 883 struct page *page; 884 885 if (p5_tpa) 886 agg = bnxt_get_tpa_agg_p5(bp, rxr, idx, start + i); 887 else 888 agg = bnxt_get_agg(bp, cpr, idx, start + i); 889 cons = agg->rx_agg_cmp_opaque; 890 __clear_bit(cons, rxr->rx_agg_bmap); 891 892 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap))) 893 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod); 894 895 __set_bit(sw_prod, rxr->rx_agg_bmap); 896 prod_rx_buf = &rxr->rx_agg_ring[sw_prod]; 897 cons_rx_buf = &rxr->rx_agg_ring[cons]; 898 899 /* It is possible for sw_prod to be equal to cons, so 900 * set cons_rx_buf->page to NULL first. 901 */ 902 page = cons_rx_buf->page; 903 cons_rx_buf->page = NULL; 904 prod_rx_buf->page = page; 905 prod_rx_buf->offset = cons_rx_buf->offset; 906 907 prod_rx_buf->mapping = cons_rx_buf->mapping; 908 909 prod_bd = &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)]; 910 911 prod_bd->rx_bd_haddr = cpu_to_le64(cons_rx_buf->mapping); 912 prod_bd->rx_bd_opaque = sw_prod; 913 914 prod = NEXT_RX_AGG(prod); 915 sw_prod = NEXT_RX_AGG(sw_prod); 916 } 917 rxr->rx_agg_prod = prod; 918 rxr->rx_sw_agg_prod = sw_prod; 919 } 920 921 static struct sk_buff *bnxt_rx_page_skb(struct bnxt *bp, 922 struct bnxt_rx_ring_info *rxr, 923 u16 cons, void *data, u8 *data_ptr, 924 dma_addr_t dma_addr, 925 unsigned int offset_and_len) 926 { 927 unsigned int payload = offset_and_len >> 16; 928 unsigned int len = offset_and_len & 0xffff; 929 skb_frag_t *frag; 930 struct page *page = data; 931 u16 prod = rxr->rx_prod; 932 struct sk_buff *skb; 933 int off, err; 934 935 err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC); 936 if (unlikely(err)) { 937 bnxt_reuse_rx_data(rxr, cons, data); 938 return NULL; 939 } 940 dma_addr -= bp->rx_dma_offset; 941 dma_unmap_page_attrs(&bp->pdev->dev, dma_addr, PAGE_SIZE, bp->rx_dir, 942 DMA_ATTR_WEAK_ORDERING); 943 page_pool_release_page(rxr->page_pool, page); 944 945 if (unlikely(!payload)) 946 payload = eth_get_headlen(bp->dev, data_ptr, len); 947 948 skb = napi_alloc_skb(&rxr->bnapi->napi, payload); 949 if (!skb) { 950 __free_page(page); 951 return NULL; 952 } 953 954 off = (void *)data_ptr - page_address(page); 955 skb_add_rx_frag(skb, 0, page, off, len, PAGE_SIZE); 956 memcpy(skb->data - NET_IP_ALIGN, data_ptr - NET_IP_ALIGN, 957 payload + NET_IP_ALIGN); 958 959 frag = &skb_shinfo(skb)->frags[0]; 960 skb_frag_size_sub(frag, payload); 961 skb_frag_off_add(frag, payload); 962 skb->data_len -= payload; 963 skb->tail += payload; 964 965 return skb; 966 } 967 968 static struct sk_buff *bnxt_rx_skb(struct bnxt *bp, 969 struct bnxt_rx_ring_info *rxr, u16 cons, 970 void *data, u8 *data_ptr, 971 dma_addr_t dma_addr, 972 unsigned int offset_and_len) 973 { 974 u16 prod = rxr->rx_prod; 975 struct sk_buff *skb; 976 int err; 977 978 err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC); 979 if (unlikely(err)) { 980 bnxt_reuse_rx_data(rxr, cons, data); 981 return NULL; 982 } 983 984 skb = build_skb(data, 0); 985 dma_unmap_single_attrs(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size, 986 bp->rx_dir, DMA_ATTR_WEAK_ORDERING); 987 if (!skb) { 988 kfree(data); 989 return NULL; 990 } 991 992 skb_reserve(skb, bp->rx_offset); 993 skb_put(skb, offset_and_len & 0xffff); 994 return skb; 995 } 996 997 static struct sk_buff *bnxt_rx_pages(struct bnxt *bp, 998 struct bnxt_cp_ring_info *cpr, 999 struct sk_buff *skb, u16 idx, 1000 u32 agg_bufs, bool tpa) 1001 { 1002 struct bnxt_napi *bnapi = cpr->bnapi; 1003 struct pci_dev *pdev = bp->pdev; 1004 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 1005 u16 prod = rxr->rx_agg_prod; 1006 bool p5_tpa = false; 1007 u32 i; 1008 1009 if ((bp->flags & BNXT_FLAG_CHIP_P5) && tpa) 1010 p5_tpa = true; 1011 1012 for (i = 0; i < agg_bufs; i++) { 1013 u16 cons, frag_len; 1014 struct rx_agg_cmp *agg; 1015 struct bnxt_sw_rx_agg_bd *cons_rx_buf; 1016 struct page *page; 1017 dma_addr_t mapping; 1018 1019 if (p5_tpa) 1020 agg = bnxt_get_tpa_agg_p5(bp, rxr, idx, i); 1021 else 1022 agg = bnxt_get_agg(bp, cpr, idx, i); 1023 cons = agg->rx_agg_cmp_opaque; 1024 frag_len = (le32_to_cpu(agg->rx_agg_cmp_len_flags_type) & 1025 RX_AGG_CMP_LEN) >> RX_AGG_CMP_LEN_SHIFT; 1026 1027 cons_rx_buf = &rxr->rx_agg_ring[cons]; 1028 skb_fill_page_desc(skb, i, cons_rx_buf->page, 1029 cons_rx_buf->offset, frag_len); 1030 __clear_bit(cons, rxr->rx_agg_bmap); 1031 1032 /* It is possible for bnxt_alloc_rx_page() to allocate 1033 * a sw_prod index that equals the cons index, so we 1034 * need to clear the cons entry now. 1035 */ 1036 mapping = cons_rx_buf->mapping; 1037 page = cons_rx_buf->page; 1038 cons_rx_buf->page = NULL; 1039 1040 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_ATOMIC) != 0) { 1041 struct skb_shared_info *shinfo; 1042 unsigned int nr_frags; 1043 1044 shinfo = skb_shinfo(skb); 1045 nr_frags = --shinfo->nr_frags; 1046 __skb_frag_set_page(&shinfo->frags[nr_frags], NULL); 1047 1048 dev_kfree_skb(skb); 1049 1050 cons_rx_buf->page = page; 1051 1052 /* Update prod since possibly some pages have been 1053 * allocated already. 1054 */ 1055 rxr->rx_agg_prod = prod; 1056 bnxt_reuse_rx_agg_bufs(cpr, idx, i, agg_bufs - i, tpa); 1057 return NULL; 1058 } 1059 1060 dma_unmap_page_attrs(&pdev->dev, mapping, BNXT_RX_PAGE_SIZE, 1061 PCI_DMA_FROMDEVICE, 1062 DMA_ATTR_WEAK_ORDERING); 1063 1064 skb->data_len += frag_len; 1065 skb->len += frag_len; 1066 skb->truesize += PAGE_SIZE; 1067 1068 prod = NEXT_RX_AGG(prod); 1069 } 1070 rxr->rx_agg_prod = prod; 1071 return skb; 1072 } 1073 1074 static int bnxt_agg_bufs_valid(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, 1075 u8 agg_bufs, u32 *raw_cons) 1076 { 1077 u16 last; 1078 struct rx_agg_cmp *agg; 1079 1080 *raw_cons = ADV_RAW_CMP(*raw_cons, agg_bufs); 1081 last = RING_CMP(*raw_cons); 1082 agg = (struct rx_agg_cmp *) 1083 &cpr->cp_desc_ring[CP_RING(last)][CP_IDX(last)]; 1084 return RX_AGG_CMP_VALID(agg, *raw_cons); 1085 } 1086 1087 static inline struct sk_buff *bnxt_copy_skb(struct bnxt_napi *bnapi, u8 *data, 1088 unsigned int len, 1089 dma_addr_t mapping) 1090 { 1091 struct bnxt *bp = bnapi->bp; 1092 struct pci_dev *pdev = bp->pdev; 1093 struct sk_buff *skb; 1094 1095 skb = napi_alloc_skb(&bnapi->napi, len); 1096 if (!skb) 1097 return NULL; 1098 1099 dma_sync_single_for_cpu(&pdev->dev, mapping, bp->rx_copy_thresh, 1100 bp->rx_dir); 1101 1102 memcpy(skb->data - NET_IP_ALIGN, data - NET_IP_ALIGN, 1103 len + NET_IP_ALIGN); 1104 1105 dma_sync_single_for_device(&pdev->dev, mapping, bp->rx_copy_thresh, 1106 bp->rx_dir); 1107 1108 skb_put(skb, len); 1109 return skb; 1110 } 1111 1112 static int bnxt_discard_rx(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, 1113 u32 *raw_cons, void *cmp) 1114 { 1115 struct rx_cmp *rxcmp = cmp; 1116 u32 tmp_raw_cons = *raw_cons; 1117 u8 cmp_type, agg_bufs = 0; 1118 1119 cmp_type = RX_CMP_TYPE(rxcmp); 1120 1121 if (cmp_type == CMP_TYPE_RX_L2_CMP) { 1122 agg_bufs = (le32_to_cpu(rxcmp->rx_cmp_misc_v1) & 1123 RX_CMP_AGG_BUFS) >> 1124 RX_CMP_AGG_BUFS_SHIFT; 1125 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) { 1126 struct rx_tpa_end_cmp *tpa_end = cmp; 1127 1128 if (bp->flags & BNXT_FLAG_CHIP_P5) 1129 return 0; 1130 1131 agg_bufs = TPA_END_AGG_BUFS(tpa_end); 1132 } 1133 1134 if (agg_bufs) { 1135 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons)) 1136 return -EBUSY; 1137 } 1138 *raw_cons = tmp_raw_cons; 1139 return 0; 1140 } 1141 1142 static void bnxt_queue_fw_reset_work(struct bnxt *bp, unsigned long delay) 1143 { 1144 if (BNXT_PF(bp)) 1145 queue_delayed_work(bnxt_pf_wq, &bp->fw_reset_task, delay); 1146 else 1147 schedule_delayed_work(&bp->fw_reset_task, delay); 1148 } 1149 1150 static void bnxt_queue_sp_work(struct bnxt *bp) 1151 { 1152 if (BNXT_PF(bp)) 1153 queue_work(bnxt_pf_wq, &bp->sp_task); 1154 else 1155 schedule_work(&bp->sp_task); 1156 } 1157 1158 static void bnxt_cancel_sp_work(struct bnxt *bp) 1159 { 1160 if (BNXT_PF(bp)) 1161 flush_workqueue(bnxt_pf_wq); 1162 else 1163 cancel_work_sync(&bp->sp_task); 1164 } 1165 1166 static void bnxt_sched_reset(struct bnxt *bp, struct bnxt_rx_ring_info *rxr) 1167 { 1168 if (!rxr->bnapi->in_reset) { 1169 rxr->bnapi->in_reset = true; 1170 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event); 1171 bnxt_queue_sp_work(bp); 1172 } 1173 rxr->rx_next_cons = 0xffff; 1174 } 1175 1176 static u16 bnxt_alloc_agg_idx(struct bnxt_rx_ring_info *rxr, u16 agg_id) 1177 { 1178 struct bnxt_tpa_idx_map *map = rxr->rx_tpa_idx_map; 1179 u16 idx = agg_id & MAX_TPA_P5_MASK; 1180 1181 if (test_bit(idx, map->agg_idx_bmap)) 1182 idx = find_first_zero_bit(map->agg_idx_bmap, 1183 BNXT_AGG_IDX_BMAP_SIZE); 1184 __set_bit(idx, map->agg_idx_bmap); 1185 map->agg_id_tbl[agg_id] = idx; 1186 return idx; 1187 } 1188 1189 static void bnxt_free_agg_idx(struct bnxt_rx_ring_info *rxr, u16 idx) 1190 { 1191 struct bnxt_tpa_idx_map *map = rxr->rx_tpa_idx_map; 1192 1193 __clear_bit(idx, map->agg_idx_bmap); 1194 } 1195 1196 static u16 bnxt_lookup_agg_idx(struct bnxt_rx_ring_info *rxr, u16 agg_id) 1197 { 1198 struct bnxt_tpa_idx_map *map = rxr->rx_tpa_idx_map; 1199 1200 return map->agg_id_tbl[agg_id]; 1201 } 1202 1203 static void bnxt_tpa_start(struct bnxt *bp, struct bnxt_rx_ring_info *rxr, 1204 struct rx_tpa_start_cmp *tpa_start, 1205 struct rx_tpa_start_cmp_ext *tpa_start1) 1206 { 1207 struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf; 1208 struct bnxt_tpa_info *tpa_info; 1209 u16 cons, prod, agg_id; 1210 struct rx_bd *prod_bd; 1211 dma_addr_t mapping; 1212 1213 if (bp->flags & BNXT_FLAG_CHIP_P5) { 1214 agg_id = TPA_START_AGG_ID_P5(tpa_start); 1215 agg_id = bnxt_alloc_agg_idx(rxr, agg_id); 1216 } else { 1217 agg_id = TPA_START_AGG_ID(tpa_start); 1218 } 1219 cons = tpa_start->rx_tpa_start_cmp_opaque; 1220 prod = rxr->rx_prod; 1221 cons_rx_buf = &rxr->rx_buf_ring[cons]; 1222 prod_rx_buf = &rxr->rx_buf_ring[prod]; 1223 tpa_info = &rxr->rx_tpa[agg_id]; 1224 1225 if (unlikely(cons != rxr->rx_next_cons || 1226 TPA_START_ERROR(tpa_start))) { 1227 netdev_warn(bp->dev, "TPA cons %x, expected cons %x, error code %x\n", 1228 cons, rxr->rx_next_cons, 1229 TPA_START_ERROR_CODE(tpa_start1)); 1230 bnxt_sched_reset(bp, rxr); 1231 return; 1232 } 1233 /* Store cfa_code in tpa_info to use in tpa_end 1234 * completion processing. 1235 */ 1236 tpa_info->cfa_code = TPA_START_CFA_CODE(tpa_start1); 1237 prod_rx_buf->data = tpa_info->data; 1238 prod_rx_buf->data_ptr = tpa_info->data_ptr; 1239 1240 mapping = tpa_info->mapping; 1241 prod_rx_buf->mapping = mapping; 1242 1243 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)]; 1244 1245 prod_bd->rx_bd_haddr = cpu_to_le64(mapping); 1246 1247 tpa_info->data = cons_rx_buf->data; 1248 tpa_info->data_ptr = cons_rx_buf->data_ptr; 1249 cons_rx_buf->data = NULL; 1250 tpa_info->mapping = cons_rx_buf->mapping; 1251 1252 tpa_info->len = 1253 le32_to_cpu(tpa_start->rx_tpa_start_cmp_len_flags_type) >> 1254 RX_TPA_START_CMP_LEN_SHIFT; 1255 if (likely(TPA_START_HASH_VALID(tpa_start))) { 1256 u32 hash_type = TPA_START_HASH_TYPE(tpa_start); 1257 1258 tpa_info->hash_type = PKT_HASH_TYPE_L4; 1259 tpa_info->gso_type = SKB_GSO_TCPV4; 1260 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */ 1261 if (hash_type == 3 || TPA_START_IS_IPV6(tpa_start1)) 1262 tpa_info->gso_type = SKB_GSO_TCPV6; 1263 tpa_info->rss_hash = 1264 le32_to_cpu(tpa_start->rx_tpa_start_cmp_rss_hash); 1265 } else { 1266 tpa_info->hash_type = PKT_HASH_TYPE_NONE; 1267 tpa_info->gso_type = 0; 1268 if (netif_msg_rx_err(bp)) 1269 netdev_warn(bp->dev, "TPA packet without valid hash\n"); 1270 } 1271 tpa_info->flags2 = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_flags2); 1272 tpa_info->metadata = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_metadata); 1273 tpa_info->hdr_info = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_hdr_info); 1274 tpa_info->agg_count = 0; 1275 1276 rxr->rx_prod = NEXT_RX(prod); 1277 cons = NEXT_RX(cons); 1278 rxr->rx_next_cons = NEXT_RX(cons); 1279 cons_rx_buf = &rxr->rx_buf_ring[cons]; 1280 1281 bnxt_reuse_rx_data(rxr, cons, cons_rx_buf->data); 1282 rxr->rx_prod = NEXT_RX(rxr->rx_prod); 1283 cons_rx_buf->data = NULL; 1284 } 1285 1286 static void bnxt_abort_tpa(struct bnxt_cp_ring_info *cpr, u16 idx, u32 agg_bufs) 1287 { 1288 if (agg_bufs) 1289 bnxt_reuse_rx_agg_bufs(cpr, idx, 0, agg_bufs, true); 1290 } 1291 1292 #ifdef CONFIG_INET 1293 static void bnxt_gro_tunnel(struct sk_buff *skb, __be16 ip_proto) 1294 { 1295 struct udphdr *uh = NULL; 1296 1297 if (ip_proto == htons(ETH_P_IP)) { 1298 struct iphdr *iph = (struct iphdr *)skb->data; 1299 1300 if (iph->protocol == IPPROTO_UDP) 1301 uh = (struct udphdr *)(iph + 1); 1302 } else { 1303 struct ipv6hdr *iph = (struct ipv6hdr *)skb->data; 1304 1305 if (iph->nexthdr == IPPROTO_UDP) 1306 uh = (struct udphdr *)(iph + 1); 1307 } 1308 if (uh) { 1309 if (uh->check) 1310 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL_CSUM; 1311 else 1312 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL; 1313 } 1314 } 1315 #endif 1316 1317 static struct sk_buff *bnxt_gro_func_5731x(struct bnxt_tpa_info *tpa_info, 1318 int payload_off, int tcp_ts, 1319 struct sk_buff *skb) 1320 { 1321 #ifdef CONFIG_INET 1322 struct tcphdr *th; 1323 int len, nw_off; 1324 u16 outer_ip_off, inner_ip_off, inner_mac_off; 1325 u32 hdr_info = tpa_info->hdr_info; 1326 bool loopback = false; 1327 1328 inner_ip_off = BNXT_TPA_INNER_L3_OFF(hdr_info); 1329 inner_mac_off = BNXT_TPA_INNER_L2_OFF(hdr_info); 1330 outer_ip_off = BNXT_TPA_OUTER_L3_OFF(hdr_info); 1331 1332 /* If the packet is an internal loopback packet, the offsets will 1333 * have an extra 4 bytes. 1334 */ 1335 if (inner_mac_off == 4) { 1336 loopback = true; 1337 } else if (inner_mac_off > 4) { 1338 __be16 proto = *((__be16 *)(skb->data + inner_ip_off - 1339 ETH_HLEN - 2)); 1340 1341 /* We only support inner iPv4/ipv6. If we don't see the 1342 * correct protocol ID, it must be a loopback packet where 1343 * the offsets are off by 4. 1344 */ 1345 if (proto != htons(ETH_P_IP) && proto != htons(ETH_P_IPV6)) 1346 loopback = true; 1347 } 1348 if (loopback) { 1349 /* internal loopback packet, subtract all offsets by 4 */ 1350 inner_ip_off -= 4; 1351 inner_mac_off -= 4; 1352 outer_ip_off -= 4; 1353 } 1354 1355 nw_off = inner_ip_off - ETH_HLEN; 1356 skb_set_network_header(skb, nw_off); 1357 if (tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_IP_TYPE) { 1358 struct ipv6hdr *iph = ipv6_hdr(skb); 1359 1360 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr)); 1361 len = skb->len - skb_transport_offset(skb); 1362 th = tcp_hdr(skb); 1363 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0); 1364 } else { 1365 struct iphdr *iph = ip_hdr(skb); 1366 1367 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr)); 1368 len = skb->len - skb_transport_offset(skb); 1369 th = tcp_hdr(skb); 1370 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0); 1371 } 1372 1373 if (inner_mac_off) { /* tunnel */ 1374 __be16 proto = *((__be16 *)(skb->data + outer_ip_off - 1375 ETH_HLEN - 2)); 1376 1377 bnxt_gro_tunnel(skb, proto); 1378 } 1379 #endif 1380 return skb; 1381 } 1382 1383 static struct sk_buff *bnxt_gro_func_5750x(struct bnxt_tpa_info *tpa_info, 1384 int payload_off, int tcp_ts, 1385 struct sk_buff *skb) 1386 { 1387 #ifdef CONFIG_INET 1388 u16 outer_ip_off, inner_ip_off, inner_mac_off; 1389 u32 hdr_info = tpa_info->hdr_info; 1390 int iphdr_len, nw_off; 1391 1392 inner_ip_off = BNXT_TPA_INNER_L3_OFF(hdr_info); 1393 inner_mac_off = BNXT_TPA_INNER_L2_OFF(hdr_info); 1394 outer_ip_off = BNXT_TPA_OUTER_L3_OFF(hdr_info); 1395 1396 nw_off = inner_ip_off - ETH_HLEN; 1397 skb_set_network_header(skb, nw_off); 1398 iphdr_len = (tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_IP_TYPE) ? 1399 sizeof(struct ipv6hdr) : sizeof(struct iphdr); 1400 skb_set_transport_header(skb, nw_off + iphdr_len); 1401 1402 if (inner_mac_off) { /* tunnel */ 1403 __be16 proto = *((__be16 *)(skb->data + outer_ip_off - 1404 ETH_HLEN - 2)); 1405 1406 bnxt_gro_tunnel(skb, proto); 1407 } 1408 #endif 1409 return skb; 1410 } 1411 1412 #define BNXT_IPV4_HDR_SIZE (sizeof(struct iphdr) + sizeof(struct tcphdr)) 1413 #define BNXT_IPV6_HDR_SIZE (sizeof(struct ipv6hdr) + sizeof(struct tcphdr)) 1414 1415 static struct sk_buff *bnxt_gro_func_5730x(struct bnxt_tpa_info *tpa_info, 1416 int payload_off, int tcp_ts, 1417 struct sk_buff *skb) 1418 { 1419 #ifdef CONFIG_INET 1420 struct tcphdr *th; 1421 int len, nw_off, tcp_opt_len = 0; 1422 1423 if (tcp_ts) 1424 tcp_opt_len = 12; 1425 1426 if (tpa_info->gso_type == SKB_GSO_TCPV4) { 1427 struct iphdr *iph; 1428 1429 nw_off = payload_off - BNXT_IPV4_HDR_SIZE - tcp_opt_len - 1430 ETH_HLEN; 1431 skb_set_network_header(skb, nw_off); 1432 iph = ip_hdr(skb); 1433 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr)); 1434 len = skb->len - skb_transport_offset(skb); 1435 th = tcp_hdr(skb); 1436 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0); 1437 } else if (tpa_info->gso_type == SKB_GSO_TCPV6) { 1438 struct ipv6hdr *iph; 1439 1440 nw_off = payload_off - BNXT_IPV6_HDR_SIZE - tcp_opt_len - 1441 ETH_HLEN; 1442 skb_set_network_header(skb, nw_off); 1443 iph = ipv6_hdr(skb); 1444 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr)); 1445 len = skb->len - skb_transport_offset(skb); 1446 th = tcp_hdr(skb); 1447 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0); 1448 } else { 1449 dev_kfree_skb_any(skb); 1450 return NULL; 1451 } 1452 1453 if (nw_off) /* tunnel */ 1454 bnxt_gro_tunnel(skb, skb->protocol); 1455 #endif 1456 return skb; 1457 } 1458 1459 static inline struct sk_buff *bnxt_gro_skb(struct bnxt *bp, 1460 struct bnxt_tpa_info *tpa_info, 1461 struct rx_tpa_end_cmp *tpa_end, 1462 struct rx_tpa_end_cmp_ext *tpa_end1, 1463 struct sk_buff *skb) 1464 { 1465 #ifdef CONFIG_INET 1466 int payload_off; 1467 u16 segs; 1468 1469 segs = TPA_END_TPA_SEGS(tpa_end); 1470 if (segs == 1) 1471 return skb; 1472 1473 NAPI_GRO_CB(skb)->count = segs; 1474 skb_shinfo(skb)->gso_size = 1475 le32_to_cpu(tpa_end1->rx_tpa_end_cmp_seg_len); 1476 skb_shinfo(skb)->gso_type = tpa_info->gso_type; 1477 if (bp->flags & BNXT_FLAG_CHIP_P5) 1478 payload_off = TPA_END_PAYLOAD_OFF_P5(tpa_end1); 1479 else 1480 payload_off = TPA_END_PAYLOAD_OFF(tpa_end); 1481 skb = bp->gro_func(tpa_info, payload_off, TPA_END_GRO_TS(tpa_end), skb); 1482 if (likely(skb)) 1483 tcp_gro_complete(skb); 1484 #endif 1485 return skb; 1486 } 1487 1488 /* Given the cfa_code of a received packet determine which 1489 * netdev (vf-rep or PF) the packet is destined to. 1490 */ 1491 static struct net_device *bnxt_get_pkt_dev(struct bnxt *bp, u16 cfa_code) 1492 { 1493 struct net_device *dev = bnxt_get_vf_rep(bp, cfa_code); 1494 1495 /* if vf-rep dev is NULL, the must belongs to the PF */ 1496 return dev ? dev : bp->dev; 1497 } 1498 1499 static inline struct sk_buff *bnxt_tpa_end(struct bnxt *bp, 1500 struct bnxt_cp_ring_info *cpr, 1501 u32 *raw_cons, 1502 struct rx_tpa_end_cmp *tpa_end, 1503 struct rx_tpa_end_cmp_ext *tpa_end1, 1504 u8 *event) 1505 { 1506 struct bnxt_napi *bnapi = cpr->bnapi; 1507 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 1508 u8 *data_ptr, agg_bufs; 1509 unsigned int len; 1510 struct bnxt_tpa_info *tpa_info; 1511 dma_addr_t mapping; 1512 struct sk_buff *skb; 1513 u16 idx = 0, agg_id; 1514 void *data; 1515 bool gro; 1516 1517 if (unlikely(bnapi->in_reset)) { 1518 int rc = bnxt_discard_rx(bp, cpr, raw_cons, tpa_end); 1519 1520 if (rc < 0) 1521 return ERR_PTR(-EBUSY); 1522 return NULL; 1523 } 1524 1525 if (bp->flags & BNXT_FLAG_CHIP_P5) { 1526 agg_id = TPA_END_AGG_ID_P5(tpa_end); 1527 agg_id = bnxt_lookup_agg_idx(rxr, agg_id); 1528 agg_bufs = TPA_END_AGG_BUFS_P5(tpa_end1); 1529 tpa_info = &rxr->rx_tpa[agg_id]; 1530 if (unlikely(agg_bufs != tpa_info->agg_count)) { 1531 netdev_warn(bp->dev, "TPA end agg_buf %d != expected agg_bufs %d\n", 1532 agg_bufs, tpa_info->agg_count); 1533 agg_bufs = tpa_info->agg_count; 1534 } 1535 tpa_info->agg_count = 0; 1536 *event |= BNXT_AGG_EVENT; 1537 bnxt_free_agg_idx(rxr, agg_id); 1538 idx = agg_id; 1539 gro = !!(bp->flags & BNXT_FLAG_GRO); 1540 } else { 1541 agg_id = TPA_END_AGG_ID(tpa_end); 1542 agg_bufs = TPA_END_AGG_BUFS(tpa_end); 1543 tpa_info = &rxr->rx_tpa[agg_id]; 1544 idx = RING_CMP(*raw_cons); 1545 if (agg_bufs) { 1546 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, raw_cons)) 1547 return ERR_PTR(-EBUSY); 1548 1549 *event |= BNXT_AGG_EVENT; 1550 idx = NEXT_CMP(idx); 1551 } 1552 gro = !!TPA_END_GRO(tpa_end); 1553 } 1554 data = tpa_info->data; 1555 data_ptr = tpa_info->data_ptr; 1556 prefetch(data_ptr); 1557 len = tpa_info->len; 1558 mapping = tpa_info->mapping; 1559 1560 if (unlikely(agg_bufs > MAX_SKB_FRAGS || TPA_END_ERRORS(tpa_end1))) { 1561 bnxt_abort_tpa(cpr, idx, agg_bufs); 1562 if (agg_bufs > MAX_SKB_FRAGS) 1563 netdev_warn(bp->dev, "TPA frags %d exceeded MAX_SKB_FRAGS %d\n", 1564 agg_bufs, (int)MAX_SKB_FRAGS); 1565 return NULL; 1566 } 1567 1568 if (len <= bp->rx_copy_thresh) { 1569 skb = bnxt_copy_skb(bnapi, data_ptr, len, mapping); 1570 if (!skb) { 1571 bnxt_abort_tpa(cpr, idx, agg_bufs); 1572 return NULL; 1573 } 1574 } else { 1575 u8 *new_data; 1576 dma_addr_t new_mapping; 1577 1578 new_data = __bnxt_alloc_rx_data(bp, &new_mapping, GFP_ATOMIC); 1579 if (!new_data) { 1580 bnxt_abort_tpa(cpr, idx, agg_bufs); 1581 return NULL; 1582 } 1583 1584 tpa_info->data = new_data; 1585 tpa_info->data_ptr = new_data + bp->rx_offset; 1586 tpa_info->mapping = new_mapping; 1587 1588 skb = build_skb(data, 0); 1589 dma_unmap_single_attrs(&bp->pdev->dev, mapping, 1590 bp->rx_buf_use_size, bp->rx_dir, 1591 DMA_ATTR_WEAK_ORDERING); 1592 1593 if (!skb) { 1594 kfree(data); 1595 bnxt_abort_tpa(cpr, idx, agg_bufs); 1596 return NULL; 1597 } 1598 skb_reserve(skb, bp->rx_offset); 1599 skb_put(skb, len); 1600 } 1601 1602 if (agg_bufs) { 1603 skb = bnxt_rx_pages(bp, cpr, skb, idx, agg_bufs, true); 1604 if (!skb) { 1605 /* Page reuse already handled by bnxt_rx_pages(). */ 1606 return NULL; 1607 } 1608 } 1609 1610 skb->protocol = 1611 eth_type_trans(skb, bnxt_get_pkt_dev(bp, tpa_info->cfa_code)); 1612 1613 if (tpa_info->hash_type != PKT_HASH_TYPE_NONE) 1614 skb_set_hash(skb, tpa_info->rss_hash, tpa_info->hash_type); 1615 1616 if ((tpa_info->flags2 & RX_CMP_FLAGS2_META_FORMAT_VLAN) && 1617 (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) { 1618 u16 vlan_proto = tpa_info->metadata >> 1619 RX_CMP_FLAGS2_METADATA_TPID_SFT; 1620 u16 vtag = tpa_info->metadata & RX_CMP_FLAGS2_METADATA_TCI_MASK; 1621 1622 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag); 1623 } 1624 1625 skb_checksum_none_assert(skb); 1626 if (likely(tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_L4_CS_CALC)) { 1627 skb->ip_summed = CHECKSUM_UNNECESSARY; 1628 skb->csum_level = 1629 (tpa_info->flags2 & RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3; 1630 } 1631 1632 if (gro) 1633 skb = bnxt_gro_skb(bp, tpa_info, tpa_end, tpa_end1, skb); 1634 1635 return skb; 1636 } 1637 1638 static void bnxt_tpa_agg(struct bnxt *bp, struct bnxt_rx_ring_info *rxr, 1639 struct rx_agg_cmp *rx_agg) 1640 { 1641 u16 agg_id = TPA_AGG_AGG_ID(rx_agg); 1642 struct bnxt_tpa_info *tpa_info; 1643 1644 agg_id = bnxt_lookup_agg_idx(rxr, agg_id); 1645 tpa_info = &rxr->rx_tpa[agg_id]; 1646 BUG_ON(tpa_info->agg_count >= MAX_SKB_FRAGS); 1647 tpa_info->agg_arr[tpa_info->agg_count++] = *rx_agg; 1648 } 1649 1650 static void bnxt_deliver_skb(struct bnxt *bp, struct bnxt_napi *bnapi, 1651 struct sk_buff *skb) 1652 { 1653 if (skb->dev != bp->dev) { 1654 /* this packet belongs to a vf-rep */ 1655 bnxt_vf_rep_rx(bp, skb); 1656 return; 1657 } 1658 skb_record_rx_queue(skb, bnapi->index); 1659 napi_gro_receive(&bnapi->napi, skb); 1660 } 1661 1662 /* returns the following: 1663 * 1 - 1 packet successfully received 1664 * 0 - successful TPA_START, packet not completed yet 1665 * -EBUSY - completion ring does not have all the agg buffers yet 1666 * -ENOMEM - packet aborted due to out of memory 1667 * -EIO - packet aborted due to hw error indicated in BD 1668 */ 1669 static int bnxt_rx_pkt(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, 1670 u32 *raw_cons, u8 *event) 1671 { 1672 struct bnxt_napi *bnapi = cpr->bnapi; 1673 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 1674 struct net_device *dev = bp->dev; 1675 struct rx_cmp *rxcmp; 1676 struct rx_cmp_ext *rxcmp1; 1677 u32 tmp_raw_cons = *raw_cons; 1678 u16 cfa_code, cons, prod, cp_cons = RING_CMP(tmp_raw_cons); 1679 struct bnxt_sw_rx_bd *rx_buf; 1680 unsigned int len; 1681 u8 *data_ptr, agg_bufs, cmp_type; 1682 dma_addr_t dma_addr; 1683 struct sk_buff *skb; 1684 void *data; 1685 int rc = 0; 1686 u32 misc; 1687 1688 rxcmp = (struct rx_cmp *) 1689 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 1690 1691 cmp_type = RX_CMP_TYPE(rxcmp); 1692 1693 if (cmp_type == CMP_TYPE_RX_TPA_AGG_CMP) { 1694 bnxt_tpa_agg(bp, rxr, (struct rx_agg_cmp *)rxcmp); 1695 goto next_rx_no_prod_no_len; 1696 } 1697 1698 tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons); 1699 cp_cons = RING_CMP(tmp_raw_cons); 1700 rxcmp1 = (struct rx_cmp_ext *) 1701 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 1702 1703 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons)) 1704 return -EBUSY; 1705 1706 prod = rxr->rx_prod; 1707 1708 if (cmp_type == CMP_TYPE_RX_L2_TPA_START_CMP) { 1709 bnxt_tpa_start(bp, rxr, (struct rx_tpa_start_cmp *)rxcmp, 1710 (struct rx_tpa_start_cmp_ext *)rxcmp1); 1711 1712 *event |= BNXT_RX_EVENT; 1713 goto next_rx_no_prod_no_len; 1714 1715 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) { 1716 skb = bnxt_tpa_end(bp, cpr, &tmp_raw_cons, 1717 (struct rx_tpa_end_cmp *)rxcmp, 1718 (struct rx_tpa_end_cmp_ext *)rxcmp1, event); 1719 1720 if (IS_ERR(skb)) 1721 return -EBUSY; 1722 1723 rc = -ENOMEM; 1724 if (likely(skb)) { 1725 bnxt_deliver_skb(bp, bnapi, skb); 1726 rc = 1; 1727 } 1728 *event |= BNXT_RX_EVENT; 1729 goto next_rx_no_prod_no_len; 1730 } 1731 1732 cons = rxcmp->rx_cmp_opaque; 1733 if (unlikely(cons != rxr->rx_next_cons)) { 1734 int rc1 = bnxt_discard_rx(bp, cpr, raw_cons, rxcmp); 1735 1736 netdev_warn(bp->dev, "RX cons %x != expected cons %x\n", 1737 cons, rxr->rx_next_cons); 1738 bnxt_sched_reset(bp, rxr); 1739 return rc1; 1740 } 1741 rx_buf = &rxr->rx_buf_ring[cons]; 1742 data = rx_buf->data; 1743 data_ptr = rx_buf->data_ptr; 1744 prefetch(data_ptr); 1745 1746 misc = le32_to_cpu(rxcmp->rx_cmp_misc_v1); 1747 agg_bufs = (misc & RX_CMP_AGG_BUFS) >> RX_CMP_AGG_BUFS_SHIFT; 1748 1749 if (agg_bufs) { 1750 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons)) 1751 return -EBUSY; 1752 1753 cp_cons = NEXT_CMP(cp_cons); 1754 *event |= BNXT_AGG_EVENT; 1755 } 1756 *event |= BNXT_RX_EVENT; 1757 1758 rx_buf->data = NULL; 1759 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L2_ERRORS) { 1760 u32 rx_err = le32_to_cpu(rxcmp1->rx_cmp_cfa_code_errors_v2); 1761 1762 bnxt_reuse_rx_data(rxr, cons, data); 1763 if (agg_bufs) 1764 bnxt_reuse_rx_agg_bufs(cpr, cp_cons, 0, agg_bufs, 1765 false); 1766 1767 rc = -EIO; 1768 if (rx_err & RX_CMPL_ERRORS_BUFFER_ERROR_MASK) { 1769 bnapi->cp_ring.sw_stats.rx.rx_buf_errors++; 1770 if (!(bp->flags & BNXT_FLAG_CHIP_P5)) { 1771 netdev_warn(bp->dev, "RX buffer error %x\n", 1772 rx_err); 1773 bnxt_sched_reset(bp, rxr); 1774 } 1775 } 1776 goto next_rx_no_len; 1777 } 1778 1779 len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT; 1780 dma_addr = rx_buf->mapping; 1781 1782 if (bnxt_rx_xdp(bp, rxr, cons, data, &data_ptr, &len, event)) { 1783 rc = 1; 1784 goto next_rx; 1785 } 1786 1787 if (len <= bp->rx_copy_thresh) { 1788 skb = bnxt_copy_skb(bnapi, data_ptr, len, dma_addr); 1789 bnxt_reuse_rx_data(rxr, cons, data); 1790 if (!skb) { 1791 if (agg_bufs) 1792 bnxt_reuse_rx_agg_bufs(cpr, cp_cons, 0, 1793 agg_bufs, false); 1794 rc = -ENOMEM; 1795 goto next_rx; 1796 } 1797 } else { 1798 u32 payload; 1799 1800 if (rx_buf->data_ptr == data_ptr) 1801 payload = misc & RX_CMP_PAYLOAD_OFFSET; 1802 else 1803 payload = 0; 1804 skb = bp->rx_skb_func(bp, rxr, cons, data, data_ptr, dma_addr, 1805 payload | len); 1806 if (!skb) { 1807 rc = -ENOMEM; 1808 goto next_rx; 1809 } 1810 } 1811 1812 if (agg_bufs) { 1813 skb = bnxt_rx_pages(bp, cpr, skb, cp_cons, agg_bufs, false); 1814 if (!skb) { 1815 rc = -ENOMEM; 1816 goto next_rx; 1817 } 1818 } 1819 1820 if (RX_CMP_HASH_VALID(rxcmp)) { 1821 u32 hash_type = RX_CMP_HASH_TYPE(rxcmp); 1822 enum pkt_hash_types type = PKT_HASH_TYPE_L4; 1823 1824 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */ 1825 if (hash_type != 1 && hash_type != 3) 1826 type = PKT_HASH_TYPE_L3; 1827 skb_set_hash(skb, le32_to_cpu(rxcmp->rx_cmp_rss_hash), type); 1828 } 1829 1830 cfa_code = RX_CMP_CFA_CODE(rxcmp1); 1831 skb->protocol = eth_type_trans(skb, bnxt_get_pkt_dev(bp, cfa_code)); 1832 1833 if ((rxcmp1->rx_cmp_flags2 & 1834 cpu_to_le32(RX_CMP_FLAGS2_META_FORMAT_VLAN)) && 1835 (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) { 1836 u32 meta_data = le32_to_cpu(rxcmp1->rx_cmp_meta_data); 1837 u16 vtag = meta_data & RX_CMP_FLAGS2_METADATA_TCI_MASK; 1838 u16 vlan_proto = meta_data >> RX_CMP_FLAGS2_METADATA_TPID_SFT; 1839 1840 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag); 1841 } 1842 1843 skb_checksum_none_assert(skb); 1844 if (RX_CMP_L4_CS_OK(rxcmp1)) { 1845 if (dev->features & NETIF_F_RXCSUM) { 1846 skb->ip_summed = CHECKSUM_UNNECESSARY; 1847 skb->csum_level = RX_CMP_ENCAP(rxcmp1); 1848 } 1849 } else { 1850 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS) { 1851 if (dev->features & NETIF_F_RXCSUM) 1852 bnapi->cp_ring.sw_stats.rx.rx_l4_csum_errors++; 1853 } 1854 } 1855 1856 bnxt_deliver_skb(bp, bnapi, skb); 1857 rc = 1; 1858 1859 next_rx: 1860 cpr->rx_packets += 1; 1861 cpr->rx_bytes += len; 1862 1863 next_rx_no_len: 1864 rxr->rx_prod = NEXT_RX(prod); 1865 rxr->rx_next_cons = NEXT_RX(cons); 1866 1867 next_rx_no_prod_no_len: 1868 *raw_cons = tmp_raw_cons; 1869 1870 return rc; 1871 } 1872 1873 /* In netpoll mode, if we are using a combined completion ring, we need to 1874 * discard the rx packets and recycle the buffers. 1875 */ 1876 static int bnxt_force_rx_discard(struct bnxt *bp, 1877 struct bnxt_cp_ring_info *cpr, 1878 u32 *raw_cons, u8 *event) 1879 { 1880 u32 tmp_raw_cons = *raw_cons; 1881 struct rx_cmp_ext *rxcmp1; 1882 struct rx_cmp *rxcmp; 1883 u16 cp_cons; 1884 u8 cmp_type; 1885 1886 cp_cons = RING_CMP(tmp_raw_cons); 1887 rxcmp = (struct rx_cmp *) 1888 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 1889 1890 tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons); 1891 cp_cons = RING_CMP(tmp_raw_cons); 1892 rxcmp1 = (struct rx_cmp_ext *) 1893 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 1894 1895 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons)) 1896 return -EBUSY; 1897 1898 cmp_type = RX_CMP_TYPE(rxcmp); 1899 if (cmp_type == CMP_TYPE_RX_L2_CMP) { 1900 rxcmp1->rx_cmp_cfa_code_errors_v2 |= 1901 cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR); 1902 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) { 1903 struct rx_tpa_end_cmp_ext *tpa_end1; 1904 1905 tpa_end1 = (struct rx_tpa_end_cmp_ext *)rxcmp1; 1906 tpa_end1->rx_tpa_end_cmp_errors_v2 |= 1907 cpu_to_le32(RX_TPA_END_CMP_ERRORS); 1908 } 1909 return bnxt_rx_pkt(bp, cpr, raw_cons, event); 1910 } 1911 1912 u32 bnxt_fw_health_readl(struct bnxt *bp, int reg_idx) 1913 { 1914 struct bnxt_fw_health *fw_health = bp->fw_health; 1915 u32 reg = fw_health->regs[reg_idx]; 1916 u32 reg_type, reg_off, val = 0; 1917 1918 reg_type = BNXT_FW_HEALTH_REG_TYPE(reg); 1919 reg_off = BNXT_FW_HEALTH_REG_OFF(reg); 1920 switch (reg_type) { 1921 case BNXT_FW_HEALTH_REG_TYPE_CFG: 1922 pci_read_config_dword(bp->pdev, reg_off, &val); 1923 break; 1924 case BNXT_FW_HEALTH_REG_TYPE_GRC: 1925 reg_off = fw_health->mapped_regs[reg_idx]; 1926 /* fall through */ 1927 case BNXT_FW_HEALTH_REG_TYPE_BAR0: 1928 val = readl(bp->bar0 + reg_off); 1929 break; 1930 case BNXT_FW_HEALTH_REG_TYPE_BAR1: 1931 val = readl(bp->bar1 + reg_off); 1932 break; 1933 } 1934 if (reg_idx == BNXT_FW_RESET_INPROG_REG) 1935 val &= fw_health->fw_reset_inprog_reg_mask; 1936 return val; 1937 } 1938 1939 #define BNXT_GET_EVENT_PORT(data) \ 1940 ((data) & \ 1941 ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK) 1942 1943 static int bnxt_async_event_process(struct bnxt *bp, 1944 struct hwrm_async_event_cmpl *cmpl) 1945 { 1946 u16 event_id = le16_to_cpu(cmpl->event_id); 1947 1948 /* TODO CHIMP_FW: Define event id's for link change, error etc */ 1949 switch (event_id) { 1950 case ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE: { 1951 u32 data1 = le32_to_cpu(cmpl->event_data1); 1952 struct bnxt_link_info *link_info = &bp->link_info; 1953 1954 if (BNXT_VF(bp)) 1955 goto async_event_process_exit; 1956 1957 /* print unsupported speed warning in forced speed mode only */ 1958 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED) && 1959 (data1 & 0x20000)) { 1960 u16 fw_speed = link_info->force_link_speed; 1961 u32 speed = bnxt_fw_to_ethtool_speed(fw_speed); 1962 1963 if (speed != SPEED_UNKNOWN) 1964 netdev_warn(bp->dev, "Link speed %d no longer supported\n", 1965 speed); 1966 } 1967 set_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT, &bp->sp_event); 1968 } 1969 /* fall through */ 1970 case ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE: 1971 case ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE: 1972 set_bit(BNXT_LINK_CFG_CHANGE_SP_EVENT, &bp->sp_event); 1973 /* fall through */ 1974 case ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE: 1975 set_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event); 1976 break; 1977 case ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD: 1978 set_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event); 1979 break; 1980 case ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED: { 1981 u32 data1 = le32_to_cpu(cmpl->event_data1); 1982 u16 port_id = BNXT_GET_EVENT_PORT(data1); 1983 1984 if (BNXT_VF(bp)) 1985 break; 1986 1987 if (bp->pf.port_id != port_id) 1988 break; 1989 1990 set_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event); 1991 break; 1992 } 1993 case ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE: 1994 if (BNXT_PF(bp)) 1995 goto async_event_process_exit; 1996 set_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event); 1997 break; 1998 case ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY: { 1999 u32 data1 = le32_to_cpu(cmpl->event_data1); 2000 2001 if (!bp->fw_health) 2002 goto async_event_process_exit; 2003 2004 bp->fw_reset_timestamp = jiffies; 2005 bp->fw_reset_min_dsecs = cmpl->timestamp_lo; 2006 if (!bp->fw_reset_min_dsecs) 2007 bp->fw_reset_min_dsecs = BNXT_DFLT_FW_RST_MIN_DSECS; 2008 bp->fw_reset_max_dsecs = le16_to_cpu(cmpl->timestamp_hi); 2009 if (!bp->fw_reset_max_dsecs) 2010 bp->fw_reset_max_dsecs = BNXT_DFLT_FW_RST_MAX_DSECS; 2011 if (EVENT_DATA1_RESET_NOTIFY_FATAL(data1)) { 2012 netdev_warn(bp->dev, "Firmware fatal reset event received\n"); 2013 set_bit(BNXT_STATE_FW_FATAL_COND, &bp->state); 2014 } else { 2015 netdev_warn(bp->dev, "Firmware non-fatal reset event received, max wait time %d msec\n", 2016 bp->fw_reset_max_dsecs * 100); 2017 } 2018 set_bit(BNXT_FW_RESET_NOTIFY_SP_EVENT, &bp->sp_event); 2019 break; 2020 } 2021 case ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY: { 2022 struct bnxt_fw_health *fw_health = bp->fw_health; 2023 u32 data1 = le32_to_cpu(cmpl->event_data1); 2024 2025 if (!fw_health) 2026 goto async_event_process_exit; 2027 2028 fw_health->enabled = EVENT_DATA1_RECOVERY_ENABLED(data1); 2029 fw_health->master = EVENT_DATA1_RECOVERY_MASTER_FUNC(data1); 2030 if (!fw_health->enabled) 2031 break; 2032 2033 if (netif_msg_drv(bp)) 2034 netdev_info(bp->dev, "Error recovery info: error recovery[%d], master[%d], reset count[0x%x], health status: 0x%x\n", 2035 fw_health->enabled, fw_health->master, 2036 bnxt_fw_health_readl(bp, 2037 BNXT_FW_RESET_CNT_REG), 2038 bnxt_fw_health_readl(bp, 2039 BNXT_FW_HEALTH_REG)); 2040 fw_health->tmr_multiplier = 2041 DIV_ROUND_UP(fw_health->polling_dsecs * HZ, 2042 bp->current_interval * 10); 2043 fw_health->tmr_counter = fw_health->tmr_multiplier; 2044 fw_health->last_fw_heartbeat = 2045 bnxt_fw_health_readl(bp, BNXT_FW_HEARTBEAT_REG); 2046 fw_health->last_fw_reset_cnt = 2047 bnxt_fw_health_readl(bp, BNXT_FW_RESET_CNT_REG); 2048 goto async_event_process_exit; 2049 } 2050 default: 2051 goto async_event_process_exit; 2052 } 2053 bnxt_queue_sp_work(bp); 2054 async_event_process_exit: 2055 bnxt_ulp_async_events(bp, cmpl); 2056 return 0; 2057 } 2058 2059 static int bnxt_hwrm_handler(struct bnxt *bp, struct tx_cmp *txcmp) 2060 { 2061 u16 cmpl_type = TX_CMP_TYPE(txcmp), vf_id, seq_id; 2062 struct hwrm_cmpl *h_cmpl = (struct hwrm_cmpl *)txcmp; 2063 struct hwrm_fwd_req_cmpl *fwd_req_cmpl = 2064 (struct hwrm_fwd_req_cmpl *)txcmp; 2065 2066 switch (cmpl_type) { 2067 case CMPL_BASE_TYPE_HWRM_DONE: 2068 seq_id = le16_to_cpu(h_cmpl->sequence_id); 2069 if (seq_id == bp->hwrm_intr_seq_id) 2070 bp->hwrm_intr_seq_id = (u16)~bp->hwrm_intr_seq_id; 2071 else 2072 netdev_err(bp->dev, "Invalid hwrm seq id %d\n", seq_id); 2073 break; 2074 2075 case CMPL_BASE_TYPE_HWRM_FWD_REQ: 2076 vf_id = le16_to_cpu(fwd_req_cmpl->source_id); 2077 2078 if ((vf_id < bp->pf.first_vf_id) || 2079 (vf_id >= bp->pf.first_vf_id + bp->pf.active_vfs)) { 2080 netdev_err(bp->dev, "Msg contains invalid VF id %x\n", 2081 vf_id); 2082 return -EINVAL; 2083 } 2084 2085 set_bit(vf_id - bp->pf.first_vf_id, bp->pf.vf_event_bmap); 2086 set_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event); 2087 bnxt_queue_sp_work(bp); 2088 break; 2089 2090 case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT: 2091 bnxt_async_event_process(bp, 2092 (struct hwrm_async_event_cmpl *)txcmp); 2093 2094 default: 2095 break; 2096 } 2097 2098 return 0; 2099 } 2100 2101 static irqreturn_t bnxt_msix(int irq, void *dev_instance) 2102 { 2103 struct bnxt_napi *bnapi = dev_instance; 2104 struct bnxt *bp = bnapi->bp; 2105 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 2106 u32 cons = RING_CMP(cpr->cp_raw_cons); 2107 2108 cpr->event_ctr++; 2109 prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]); 2110 napi_schedule(&bnapi->napi); 2111 return IRQ_HANDLED; 2112 } 2113 2114 static inline int bnxt_has_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr) 2115 { 2116 u32 raw_cons = cpr->cp_raw_cons; 2117 u16 cons = RING_CMP(raw_cons); 2118 struct tx_cmp *txcmp; 2119 2120 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]; 2121 2122 return TX_CMP_VALID(txcmp, raw_cons); 2123 } 2124 2125 static irqreturn_t bnxt_inta(int irq, void *dev_instance) 2126 { 2127 struct bnxt_napi *bnapi = dev_instance; 2128 struct bnxt *bp = bnapi->bp; 2129 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 2130 u32 cons = RING_CMP(cpr->cp_raw_cons); 2131 u32 int_status; 2132 2133 prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]); 2134 2135 if (!bnxt_has_work(bp, cpr)) { 2136 int_status = readl(bp->bar0 + BNXT_CAG_REG_LEGACY_INT_STATUS); 2137 /* return if erroneous interrupt */ 2138 if (!(int_status & (0x10000 << cpr->cp_ring_struct.fw_ring_id))) 2139 return IRQ_NONE; 2140 } 2141 2142 /* disable ring IRQ */ 2143 BNXT_CP_DB_IRQ_DIS(cpr->cp_db.doorbell); 2144 2145 /* Return here if interrupt is shared and is disabled. */ 2146 if (unlikely(atomic_read(&bp->intr_sem) != 0)) 2147 return IRQ_HANDLED; 2148 2149 napi_schedule(&bnapi->napi); 2150 return IRQ_HANDLED; 2151 } 2152 2153 static int __bnxt_poll_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, 2154 int budget) 2155 { 2156 struct bnxt_napi *bnapi = cpr->bnapi; 2157 u32 raw_cons = cpr->cp_raw_cons; 2158 u32 cons; 2159 int tx_pkts = 0; 2160 int rx_pkts = 0; 2161 u8 event = 0; 2162 struct tx_cmp *txcmp; 2163 2164 cpr->has_more_work = 0; 2165 cpr->had_work_done = 1; 2166 while (1) { 2167 int rc; 2168 2169 cons = RING_CMP(raw_cons); 2170 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]; 2171 2172 if (!TX_CMP_VALID(txcmp, raw_cons)) 2173 break; 2174 2175 /* The valid test of the entry must be done first before 2176 * reading any further. 2177 */ 2178 dma_rmb(); 2179 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_TX_L2_CMP) { 2180 tx_pkts++; 2181 /* return full budget so NAPI will complete. */ 2182 if (unlikely(tx_pkts > bp->tx_wake_thresh)) { 2183 rx_pkts = budget; 2184 raw_cons = NEXT_RAW_CMP(raw_cons); 2185 if (budget) 2186 cpr->has_more_work = 1; 2187 break; 2188 } 2189 } else if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) { 2190 if (likely(budget)) 2191 rc = bnxt_rx_pkt(bp, cpr, &raw_cons, &event); 2192 else 2193 rc = bnxt_force_rx_discard(bp, cpr, &raw_cons, 2194 &event); 2195 if (likely(rc >= 0)) 2196 rx_pkts += rc; 2197 /* Increment rx_pkts when rc is -ENOMEM to count towards 2198 * the NAPI budget. Otherwise, we may potentially loop 2199 * here forever if we consistently cannot allocate 2200 * buffers. 2201 */ 2202 else if (rc == -ENOMEM && budget) 2203 rx_pkts++; 2204 else if (rc == -EBUSY) /* partial completion */ 2205 break; 2206 } else if (unlikely((TX_CMP_TYPE(txcmp) == 2207 CMPL_BASE_TYPE_HWRM_DONE) || 2208 (TX_CMP_TYPE(txcmp) == 2209 CMPL_BASE_TYPE_HWRM_FWD_REQ) || 2210 (TX_CMP_TYPE(txcmp) == 2211 CMPL_BASE_TYPE_HWRM_ASYNC_EVENT))) { 2212 bnxt_hwrm_handler(bp, txcmp); 2213 } 2214 raw_cons = NEXT_RAW_CMP(raw_cons); 2215 2216 if (rx_pkts && rx_pkts == budget) { 2217 cpr->has_more_work = 1; 2218 break; 2219 } 2220 } 2221 2222 if (event & BNXT_REDIRECT_EVENT) 2223 xdp_do_flush_map(); 2224 2225 if (event & BNXT_TX_EVENT) { 2226 struct bnxt_tx_ring_info *txr = bnapi->tx_ring; 2227 u16 prod = txr->tx_prod; 2228 2229 /* Sync BD data before updating doorbell */ 2230 wmb(); 2231 2232 bnxt_db_write_relaxed(bp, &txr->tx_db, prod); 2233 } 2234 2235 cpr->cp_raw_cons = raw_cons; 2236 bnapi->tx_pkts += tx_pkts; 2237 bnapi->events |= event; 2238 return rx_pkts; 2239 } 2240 2241 static void __bnxt_poll_work_done(struct bnxt *bp, struct bnxt_napi *bnapi) 2242 { 2243 if (bnapi->tx_pkts) { 2244 bnapi->tx_int(bp, bnapi, bnapi->tx_pkts); 2245 bnapi->tx_pkts = 0; 2246 } 2247 2248 if (bnapi->events & BNXT_RX_EVENT) { 2249 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 2250 2251 if (bnapi->events & BNXT_AGG_EVENT) 2252 bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod); 2253 bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod); 2254 } 2255 bnapi->events = 0; 2256 } 2257 2258 static int bnxt_poll_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, 2259 int budget) 2260 { 2261 struct bnxt_napi *bnapi = cpr->bnapi; 2262 int rx_pkts; 2263 2264 rx_pkts = __bnxt_poll_work(bp, cpr, budget); 2265 2266 /* ACK completion ring before freeing tx ring and producing new 2267 * buffers in rx/agg rings to prevent overflowing the completion 2268 * ring. 2269 */ 2270 bnxt_db_cq(bp, &cpr->cp_db, cpr->cp_raw_cons); 2271 2272 __bnxt_poll_work_done(bp, bnapi); 2273 return rx_pkts; 2274 } 2275 2276 static int bnxt_poll_nitroa0(struct napi_struct *napi, int budget) 2277 { 2278 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi); 2279 struct bnxt *bp = bnapi->bp; 2280 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 2281 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 2282 struct tx_cmp *txcmp; 2283 struct rx_cmp_ext *rxcmp1; 2284 u32 cp_cons, tmp_raw_cons; 2285 u32 raw_cons = cpr->cp_raw_cons; 2286 u32 rx_pkts = 0; 2287 u8 event = 0; 2288 2289 while (1) { 2290 int rc; 2291 2292 cp_cons = RING_CMP(raw_cons); 2293 txcmp = &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 2294 2295 if (!TX_CMP_VALID(txcmp, raw_cons)) 2296 break; 2297 2298 if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) { 2299 tmp_raw_cons = NEXT_RAW_CMP(raw_cons); 2300 cp_cons = RING_CMP(tmp_raw_cons); 2301 rxcmp1 = (struct rx_cmp_ext *) 2302 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 2303 2304 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons)) 2305 break; 2306 2307 /* force an error to recycle the buffer */ 2308 rxcmp1->rx_cmp_cfa_code_errors_v2 |= 2309 cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR); 2310 2311 rc = bnxt_rx_pkt(bp, cpr, &raw_cons, &event); 2312 if (likely(rc == -EIO) && budget) 2313 rx_pkts++; 2314 else if (rc == -EBUSY) /* partial completion */ 2315 break; 2316 } else if (unlikely(TX_CMP_TYPE(txcmp) == 2317 CMPL_BASE_TYPE_HWRM_DONE)) { 2318 bnxt_hwrm_handler(bp, txcmp); 2319 } else { 2320 netdev_err(bp->dev, 2321 "Invalid completion received on special ring\n"); 2322 } 2323 raw_cons = NEXT_RAW_CMP(raw_cons); 2324 2325 if (rx_pkts == budget) 2326 break; 2327 } 2328 2329 cpr->cp_raw_cons = raw_cons; 2330 BNXT_DB_CQ(&cpr->cp_db, cpr->cp_raw_cons); 2331 bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod); 2332 2333 if (event & BNXT_AGG_EVENT) 2334 bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod); 2335 2336 if (!bnxt_has_work(bp, cpr) && rx_pkts < budget) { 2337 napi_complete_done(napi, rx_pkts); 2338 BNXT_DB_CQ_ARM(&cpr->cp_db, cpr->cp_raw_cons); 2339 } 2340 return rx_pkts; 2341 } 2342 2343 static int bnxt_poll(struct napi_struct *napi, int budget) 2344 { 2345 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi); 2346 struct bnxt *bp = bnapi->bp; 2347 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 2348 int work_done = 0; 2349 2350 while (1) { 2351 work_done += bnxt_poll_work(bp, cpr, budget - work_done); 2352 2353 if (work_done >= budget) { 2354 if (!budget) 2355 BNXT_DB_CQ_ARM(&cpr->cp_db, cpr->cp_raw_cons); 2356 break; 2357 } 2358 2359 if (!bnxt_has_work(bp, cpr)) { 2360 if (napi_complete_done(napi, work_done)) 2361 BNXT_DB_CQ_ARM(&cpr->cp_db, cpr->cp_raw_cons); 2362 break; 2363 } 2364 } 2365 if (bp->flags & BNXT_FLAG_DIM) { 2366 struct dim_sample dim_sample = {}; 2367 2368 dim_update_sample(cpr->event_ctr, 2369 cpr->rx_packets, 2370 cpr->rx_bytes, 2371 &dim_sample); 2372 net_dim(&cpr->dim, dim_sample); 2373 } 2374 return work_done; 2375 } 2376 2377 static int __bnxt_poll_cqs(struct bnxt *bp, struct bnxt_napi *bnapi, int budget) 2378 { 2379 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 2380 int i, work_done = 0; 2381 2382 for (i = 0; i < 2; i++) { 2383 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[i]; 2384 2385 if (cpr2) { 2386 work_done += __bnxt_poll_work(bp, cpr2, 2387 budget - work_done); 2388 cpr->has_more_work |= cpr2->has_more_work; 2389 } 2390 } 2391 return work_done; 2392 } 2393 2394 static void __bnxt_poll_cqs_done(struct bnxt *bp, struct bnxt_napi *bnapi, 2395 u64 dbr_type) 2396 { 2397 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 2398 int i; 2399 2400 for (i = 0; i < 2; i++) { 2401 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[i]; 2402 struct bnxt_db_info *db; 2403 2404 if (cpr2 && cpr2->had_work_done) { 2405 db = &cpr2->cp_db; 2406 writeq(db->db_key64 | dbr_type | 2407 RING_CMP(cpr2->cp_raw_cons), db->doorbell); 2408 cpr2->had_work_done = 0; 2409 } 2410 } 2411 __bnxt_poll_work_done(bp, bnapi); 2412 } 2413 2414 static int bnxt_poll_p5(struct napi_struct *napi, int budget) 2415 { 2416 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi); 2417 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 2418 u32 raw_cons = cpr->cp_raw_cons; 2419 struct bnxt *bp = bnapi->bp; 2420 struct nqe_cn *nqcmp; 2421 int work_done = 0; 2422 u32 cons; 2423 2424 if (cpr->has_more_work) { 2425 cpr->has_more_work = 0; 2426 work_done = __bnxt_poll_cqs(bp, bnapi, budget); 2427 } 2428 while (1) { 2429 cons = RING_CMP(raw_cons); 2430 nqcmp = &cpr->nq_desc_ring[CP_RING(cons)][CP_IDX(cons)]; 2431 2432 if (!NQ_CMP_VALID(nqcmp, raw_cons)) { 2433 if (cpr->has_more_work) 2434 break; 2435 2436 __bnxt_poll_cqs_done(bp, bnapi, DBR_TYPE_CQ_ARMALL); 2437 cpr->cp_raw_cons = raw_cons; 2438 if (napi_complete_done(napi, work_done)) 2439 BNXT_DB_NQ_ARM_P5(&cpr->cp_db, 2440 cpr->cp_raw_cons); 2441 return work_done; 2442 } 2443 2444 /* The valid test of the entry must be done first before 2445 * reading any further. 2446 */ 2447 dma_rmb(); 2448 2449 if (nqcmp->type == cpu_to_le16(NQ_CN_TYPE_CQ_NOTIFICATION)) { 2450 u32 idx = le32_to_cpu(nqcmp->cq_handle_low); 2451 struct bnxt_cp_ring_info *cpr2; 2452 2453 cpr2 = cpr->cp_ring_arr[idx]; 2454 work_done += __bnxt_poll_work(bp, cpr2, 2455 budget - work_done); 2456 cpr->has_more_work |= cpr2->has_more_work; 2457 } else { 2458 bnxt_hwrm_handler(bp, (struct tx_cmp *)nqcmp); 2459 } 2460 raw_cons = NEXT_RAW_CMP(raw_cons); 2461 } 2462 __bnxt_poll_cqs_done(bp, bnapi, DBR_TYPE_CQ); 2463 if (raw_cons != cpr->cp_raw_cons) { 2464 cpr->cp_raw_cons = raw_cons; 2465 BNXT_DB_NQ_P5(&cpr->cp_db, raw_cons); 2466 } 2467 return work_done; 2468 } 2469 2470 static void bnxt_free_tx_skbs(struct bnxt *bp) 2471 { 2472 int i, max_idx; 2473 struct pci_dev *pdev = bp->pdev; 2474 2475 if (!bp->tx_ring) 2476 return; 2477 2478 max_idx = bp->tx_nr_pages * TX_DESC_CNT; 2479 for (i = 0; i < bp->tx_nr_rings; i++) { 2480 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; 2481 int j; 2482 2483 for (j = 0; j < max_idx;) { 2484 struct bnxt_sw_tx_bd *tx_buf = &txr->tx_buf_ring[j]; 2485 struct sk_buff *skb; 2486 int k, last; 2487 2488 if (i < bp->tx_nr_rings_xdp && 2489 tx_buf->action == XDP_REDIRECT) { 2490 dma_unmap_single(&pdev->dev, 2491 dma_unmap_addr(tx_buf, mapping), 2492 dma_unmap_len(tx_buf, len), 2493 PCI_DMA_TODEVICE); 2494 xdp_return_frame(tx_buf->xdpf); 2495 tx_buf->action = 0; 2496 tx_buf->xdpf = NULL; 2497 j++; 2498 continue; 2499 } 2500 2501 skb = tx_buf->skb; 2502 if (!skb) { 2503 j++; 2504 continue; 2505 } 2506 2507 tx_buf->skb = NULL; 2508 2509 if (tx_buf->is_push) { 2510 dev_kfree_skb(skb); 2511 j += 2; 2512 continue; 2513 } 2514 2515 dma_unmap_single(&pdev->dev, 2516 dma_unmap_addr(tx_buf, mapping), 2517 skb_headlen(skb), 2518 PCI_DMA_TODEVICE); 2519 2520 last = tx_buf->nr_frags; 2521 j += 2; 2522 for (k = 0; k < last; k++, j++) { 2523 int ring_idx = j & bp->tx_ring_mask; 2524 skb_frag_t *frag = &skb_shinfo(skb)->frags[k]; 2525 2526 tx_buf = &txr->tx_buf_ring[ring_idx]; 2527 dma_unmap_page( 2528 &pdev->dev, 2529 dma_unmap_addr(tx_buf, mapping), 2530 skb_frag_size(frag), PCI_DMA_TODEVICE); 2531 } 2532 dev_kfree_skb(skb); 2533 } 2534 netdev_tx_reset_queue(netdev_get_tx_queue(bp->dev, i)); 2535 } 2536 } 2537 2538 static void bnxt_free_rx_skbs(struct bnxt *bp) 2539 { 2540 int i, max_idx, max_agg_idx; 2541 struct pci_dev *pdev = bp->pdev; 2542 2543 if (!bp->rx_ring) 2544 return; 2545 2546 max_idx = bp->rx_nr_pages * RX_DESC_CNT; 2547 max_agg_idx = bp->rx_agg_nr_pages * RX_DESC_CNT; 2548 for (i = 0; i < bp->rx_nr_rings; i++) { 2549 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 2550 struct bnxt_tpa_idx_map *map; 2551 int j; 2552 2553 if (rxr->rx_tpa) { 2554 for (j = 0; j < bp->max_tpa; j++) { 2555 struct bnxt_tpa_info *tpa_info = 2556 &rxr->rx_tpa[j]; 2557 u8 *data = tpa_info->data; 2558 2559 if (!data) 2560 continue; 2561 2562 dma_unmap_single_attrs(&pdev->dev, 2563 tpa_info->mapping, 2564 bp->rx_buf_use_size, 2565 bp->rx_dir, 2566 DMA_ATTR_WEAK_ORDERING); 2567 2568 tpa_info->data = NULL; 2569 2570 kfree(data); 2571 } 2572 } 2573 2574 for (j = 0; j < max_idx; j++) { 2575 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[j]; 2576 dma_addr_t mapping = rx_buf->mapping; 2577 void *data = rx_buf->data; 2578 2579 if (!data) 2580 continue; 2581 2582 rx_buf->data = NULL; 2583 2584 if (BNXT_RX_PAGE_MODE(bp)) { 2585 mapping -= bp->rx_dma_offset; 2586 dma_unmap_page_attrs(&pdev->dev, mapping, 2587 PAGE_SIZE, bp->rx_dir, 2588 DMA_ATTR_WEAK_ORDERING); 2589 page_pool_recycle_direct(rxr->page_pool, data); 2590 } else { 2591 dma_unmap_single_attrs(&pdev->dev, mapping, 2592 bp->rx_buf_use_size, 2593 bp->rx_dir, 2594 DMA_ATTR_WEAK_ORDERING); 2595 kfree(data); 2596 } 2597 } 2598 2599 for (j = 0; j < max_agg_idx; j++) { 2600 struct bnxt_sw_rx_agg_bd *rx_agg_buf = 2601 &rxr->rx_agg_ring[j]; 2602 struct page *page = rx_agg_buf->page; 2603 2604 if (!page) 2605 continue; 2606 2607 dma_unmap_page_attrs(&pdev->dev, rx_agg_buf->mapping, 2608 BNXT_RX_PAGE_SIZE, 2609 PCI_DMA_FROMDEVICE, 2610 DMA_ATTR_WEAK_ORDERING); 2611 2612 rx_agg_buf->page = NULL; 2613 __clear_bit(j, rxr->rx_agg_bmap); 2614 2615 __free_page(page); 2616 } 2617 if (rxr->rx_page) { 2618 __free_page(rxr->rx_page); 2619 rxr->rx_page = NULL; 2620 } 2621 map = rxr->rx_tpa_idx_map; 2622 if (map) 2623 memset(map->agg_idx_bmap, 0, sizeof(map->agg_idx_bmap)); 2624 } 2625 } 2626 2627 static void bnxt_free_skbs(struct bnxt *bp) 2628 { 2629 bnxt_free_tx_skbs(bp); 2630 bnxt_free_rx_skbs(bp); 2631 } 2632 2633 static void bnxt_free_ring(struct bnxt *bp, struct bnxt_ring_mem_info *rmem) 2634 { 2635 struct pci_dev *pdev = bp->pdev; 2636 int i; 2637 2638 for (i = 0; i < rmem->nr_pages; i++) { 2639 if (!rmem->pg_arr[i]) 2640 continue; 2641 2642 dma_free_coherent(&pdev->dev, rmem->page_size, 2643 rmem->pg_arr[i], rmem->dma_arr[i]); 2644 2645 rmem->pg_arr[i] = NULL; 2646 } 2647 if (rmem->pg_tbl) { 2648 size_t pg_tbl_size = rmem->nr_pages * 8; 2649 2650 if (rmem->flags & BNXT_RMEM_USE_FULL_PAGE_FLAG) 2651 pg_tbl_size = rmem->page_size; 2652 dma_free_coherent(&pdev->dev, pg_tbl_size, 2653 rmem->pg_tbl, rmem->pg_tbl_map); 2654 rmem->pg_tbl = NULL; 2655 } 2656 if (rmem->vmem_size && *rmem->vmem) { 2657 vfree(*rmem->vmem); 2658 *rmem->vmem = NULL; 2659 } 2660 } 2661 2662 static int bnxt_alloc_ring(struct bnxt *bp, struct bnxt_ring_mem_info *rmem) 2663 { 2664 struct pci_dev *pdev = bp->pdev; 2665 u64 valid_bit = 0; 2666 int i; 2667 2668 if (rmem->flags & (BNXT_RMEM_VALID_PTE_FLAG | BNXT_RMEM_RING_PTE_FLAG)) 2669 valid_bit = PTU_PTE_VALID; 2670 if ((rmem->nr_pages > 1 || rmem->depth > 0) && !rmem->pg_tbl) { 2671 size_t pg_tbl_size = rmem->nr_pages * 8; 2672 2673 if (rmem->flags & BNXT_RMEM_USE_FULL_PAGE_FLAG) 2674 pg_tbl_size = rmem->page_size; 2675 rmem->pg_tbl = dma_alloc_coherent(&pdev->dev, pg_tbl_size, 2676 &rmem->pg_tbl_map, 2677 GFP_KERNEL); 2678 if (!rmem->pg_tbl) 2679 return -ENOMEM; 2680 } 2681 2682 for (i = 0; i < rmem->nr_pages; i++) { 2683 u64 extra_bits = valid_bit; 2684 2685 rmem->pg_arr[i] = dma_alloc_coherent(&pdev->dev, 2686 rmem->page_size, 2687 &rmem->dma_arr[i], 2688 GFP_KERNEL); 2689 if (!rmem->pg_arr[i]) 2690 return -ENOMEM; 2691 2692 if (rmem->init_val) 2693 memset(rmem->pg_arr[i], rmem->init_val, 2694 rmem->page_size); 2695 if (rmem->nr_pages > 1 || rmem->depth > 0) { 2696 if (i == rmem->nr_pages - 2 && 2697 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG)) 2698 extra_bits |= PTU_PTE_NEXT_TO_LAST; 2699 else if (i == rmem->nr_pages - 1 && 2700 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG)) 2701 extra_bits |= PTU_PTE_LAST; 2702 rmem->pg_tbl[i] = 2703 cpu_to_le64(rmem->dma_arr[i] | extra_bits); 2704 } 2705 } 2706 2707 if (rmem->vmem_size) { 2708 *rmem->vmem = vzalloc(rmem->vmem_size); 2709 if (!(*rmem->vmem)) 2710 return -ENOMEM; 2711 } 2712 return 0; 2713 } 2714 2715 static void bnxt_free_tpa_info(struct bnxt *bp) 2716 { 2717 int i; 2718 2719 for (i = 0; i < bp->rx_nr_rings; i++) { 2720 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 2721 2722 kfree(rxr->rx_tpa_idx_map); 2723 rxr->rx_tpa_idx_map = NULL; 2724 if (rxr->rx_tpa) { 2725 kfree(rxr->rx_tpa[0].agg_arr); 2726 rxr->rx_tpa[0].agg_arr = NULL; 2727 } 2728 kfree(rxr->rx_tpa); 2729 rxr->rx_tpa = NULL; 2730 } 2731 } 2732 2733 static int bnxt_alloc_tpa_info(struct bnxt *bp) 2734 { 2735 int i, j, total_aggs = 0; 2736 2737 bp->max_tpa = MAX_TPA; 2738 if (bp->flags & BNXT_FLAG_CHIP_P5) { 2739 if (!bp->max_tpa_v2) 2740 return 0; 2741 bp->max_tpa = max_t(u16, bp->max_tpa_v2, MAX_TPA_P5); 2742 total_aggs = bp->max_tpa * MAX_SKB_FRAGS; 2743 } 2744 2745 for (i = 0; i < bp->rx_nr_rings; i++) { 2746 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 2747 struct rx_agg_cmp *agg; 2748 2749 rxr->rx_tpa = kcalloc(bp->max_tpa, sizeof(struct bnxt_tpa_info), 2750 GFP_KERNEL); 2751 if (!rxr->rx_tpa) 2752 return -ENOMEM; 2753 2754 if (!(bp->flags & BNXT_FLAG_CHIP_P5)) 2755 continue; 2756 agg = kcalloc(total_aggs, sizeof(*agg), GFP_KERNEL); 2757 rxr->rx_tpa[0].agg_arr = agg; 2758 if (!agg) 2759 return -ENOMEM; 2760 for (j = 1; j < bp->max_tpa; j++) 2761 rxr->rx_tpa[j].agg_arr = agg + j * MAX_SKB_FRAGS; 2762 rxr->rx_tpa_idx_map = kzalloc(sizeof(*rxr->rx_tpa_idx_map), 2763 GFP_KERNEL); 2764 if (!rxr->rx_tpa_idx_map) 2765 return -ENOMEM; 2766 } 2767 return 0; 2768 } 2769 2770 static void bnxt_free_rx_rings(struct bnxt *bp) 2771 { 2772 int i; 2773 2774 if (!bp->rx_ring) 2775 return; 2776 2777 bnxt_free_tpa_info(bp); 2778 for (i = 0; i < bp->rx_nr_rings; i++) { 2779 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 2780 struct bnxt_ring_struct *ring; 2781 2782 if (rxr->xdp_prog) 2783 bpf_prog_put(rxr->xdp_prog); 2784 2785 if (xdp_rxq_info_is_reg(&rxr->xdp_rxq)) 2786 xdp_rxq_info_unreg(&rxr->xdp_rxq); 2787 2788 page_pool_destroy(rxr->page_pool); 2789 rxr->page_pool = NULL; 2790 2791 kfree(rxr->rx_agg_bmap); 2792 rxr->rx_agg_bmap = NULL; 2793 2794 ring = &rxr->rx_ring_struct; 2795 bnxt_free_ring(bp, &ring->ring_mem); 2796 2797 ring = &rxr->rx_agg_ring_struct; 2798 bnxt_free_ring(bp, &ring->ring_mem); 2799 } 2800 } 2801 2802 static int bnxt_alloc_rx_page_pool(struct bnxt *bp, 2803 struct bnxt_rx_ring_info *rxr) 2804 { 2805 struct page_pool_params pp = { 0 }; 2806 2807 pp.pool_size = bp->rx_ring_size; 2808 pp.nid = dev_to_node(&bp->pdev->dev); 2809 pp.dev = &bp->pdev->dev; 2810 pp.dma_dir = DMA_BIDIRECTIONAL; 2811 2812 rxr->page_pool = page_pool_create(&pp); 2813 if (IS_ERR(rxr->page_pool)) { 2814 int err = PTR_ERR(rxr->page_pool); 2815 2816 rxr->page_pool = NULL; 2817 return err; 2818 } 2819 return 0; 2820 } 2821 2822 static int bnxt_alloc_rx_rings(struct bnxt *bp) 2823 { 2824 int i, rc = 0, agg_rings = 0; 2825 2826 if (!bp->rx_ring) 2827 return -ENOMEM; 2828 2829 if (bp->flags & BNXT_FLAG_AGG_RINGS) 2830 agg_rings = 1; 2831 2832 for (i = 0; i < bp->rx_nr_rings; i++) { 2833 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 2834 struct bnxt_ring_struct *ring; 2835 2836 ring = &rxr->rx_ring_struct; 2837 2838 rc = bnxt_alloc_rx_page_pool(bp, rxr); 2839 if (rc) 2840 return rc; 2841 2842 rc = xdp_rxq_info_reg(&rxr->xdp_rxq, bp->dev, i); 2843 if (rc < 0) 2844 return rc; 2845 2846 rc = xdp_rxq_info_reg_mem_model(&rxr->xdp_rxq, 2847 MEM_TYPE_PAGE_POOL, 2848 rxr->page_pool); 2849 if (rc) { 2850 xdp_rxq_info_unreg(&rxr->xdp_rxq); 2851 return rc; 2852 } 2853 2854 rc = bnxt_alloc_ring(bp, &ring->ring_mem); 2855 if (rc) 2856 return rc; 2857 2858 ring->grp_idx = i; 2859 if (agg_rings) { 2860 u16 mem_size; 2861 2862 ring = &rxr->rx_agg_ring_struct; 2863 rc = bnxt_alloc_ring(bp, &ring->ring_mem); 2864 if (rc) 2865 return rc; 2866 2867 ring->grp_idx = i; 2868 rxr->rx_agg_bmap_size = bp->rx_agg_ring_mask + 1; 2869 mem_size = rxr->rx_agg_bmap_size / 8; 2870 rxr->rx_agg_bmap = kzalloc(mem_size, GFP_KERNEL); 2871 if (!rxr->rx_agg_bmap) 2872 return -ENOMEM; 2873 } 2874 } 2875 if (bp->flags & BNXT_FLAG_TPA) 2876 rc = bnxt_alloc_tpa_info(bp); 2877 return rc; 2878 } 2879 2880 static void bnxt_free_tx_rings(struct bnxt *bp) 2881 { 2882 int i; 2883 struct pci_dev *pdev = bp->pdev; 2884 2885 if (!bp->tx_ring) 2886 return; 2887 2888 for (i = 0; i < bp->tx_nr_rings; i++) { 2889 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; 2890 struct bnxt_ring_struct *ring; 2891 2892 if (txr->tx_push) { 2893 dma_free_coherent(&pdev->dev, bp->tx_push_size, 2894 txr->tx_push, txr->tx_push_mapping); 2895 txr->tx_push = NULL; 2896 } 2897 2898 ring = &txr->tx_ring_struct; 2899 2900 bnxt_free_ring(bp, &ring->ring_mem); 2901 } 2902 } 2903 2904 static int bnxt_alloc_tx_rings(struct bnxt *bp) 2905 { 2906 int i, j, rc; 2907 struct pci_dev *pdev = bp->pdev; 2908 2909 bp->tx_push_size = 0; 2910 if (bp->tx_push_thresh) { 2911 int push_size; 2912 2913 push_size = L1_CACHE_ALIGN(sizeof(struct tx_push_bd) + 2914 bp->tx_push_thresh); 2915 2916 if (push_size > 256) { 2917 push_size = 0; 2918 bp->tx_push_thresh = 0; 2919 } 2920 2921 bp->tx_push_size = push_size; 2922 } 2923 2924 for (i = 0, j = 0; i < bp->tx_nr_rings; i++) { 2925 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; 2926 struct bnxt_ring_struct *ring; 2927 u8 qidx; 2928 2929 ring = &txr->tx_ring_struct; 2930 2931 rc = bnxt_alloc_ring(bp, &ring->ring_mem); 2932 if (rc) 2933 return rc; 2934 2935 ring->grp_idx = txr->bnapi->index; 2936 if (bp->tx_push_size) { 2937 dma_addr_t mapping; 2938 2939 /* One pre-allocated DMA buffer to backup 2940 * TX push operation 2941 */ 2942 txr->tx_push = dma_alloc_coherent(&pdev->dev, 2943 bp->tx_push_size, 2944 &txr->tx_push_mapping, 2945 GFP_KERNEL); 2946 2947 if (!txr->tx_push) 2948 return -ENOMEM; 2949 2950 mapping = txr->tx_push_mapping + 2951 sizeof(struct tx_push_bd); 2952 txr->data_mapping = cpu_to_le64(mapping); 2953 } 2954 qidx = bp->tc_to_qidx[j]; 2955 ring->queue_id = bp->q_info[qidx].queue_id; 2956 if (i < bp->tx_nr_rings_xdp) 2957 continue; 2958 if (i % bp->tx_nr_rings_per_tc == (bp->tx_nr_rings_per_tc - 1)) 2959 j++; 2960 } 2961 return 0; 2962 } 2963 2964 static void bnxt_free_cp_rings(struct bnxt *bp) 2965 { 2966 int i; 2967 2968 if (!bp->bnapi) 2969 return; 2970 2971 for (i = 0; i < bp->cp_nr_rings; i++) { 2972 struct bnxt_napi *bnapi = bp->bnapi[i]; 2973 struct bnxt_cp_ring_info *cpr; 2974 struct bnxt_ring_struct *ring; 2975 int j; 2976 2977 if (!bnapi) 2978 continue; 2979 2980 cpr = &bnapi->cp_ring; 2981 ring = &cpr->cp_ring_struct; 2982 2983 bnxt_free_ring(bp, &ring->ring_mem); 2984 2985 for (j = 0; j < 2; j++) { 2986 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j]; 2987 2988 if (cpr2) { 2989 ring = &cpr2->cp_ring_struct; 2990 bnxt_free_ring(bp, &ring->ring_mem); 2991 kfree(cpr2); 2992 cpr->cp_ring_arr[j] = NULL; 2993 } 2994 } 2995 } 2996 } 2997 2998 static struct bnxt_cp_ring_info *bnxt_alloc_cp_sub_ring(struct bnxt *bp) 2999 { 3000 struct bnxt_ring_mem_info *rmem; 3001 struct bnxt_ring_struct *ring; 3002 struct bnxt_cp_ring_info *cpr; 3003 int rc; 3004 3005 cpr = kzalloc(sizeof(*cpr), GFP_KERNEL); 3006 if (!cpr) 3007 return NULL; 3008 3009 ring = &cpr->cp_ring_struct; 3010 rmem = &ring->ring_mem; 3011 rmem->nr_pages = bp->cp_nr_pages; 3012 rmem->page_size = HW_CMPD_RING_SIZE; 3013 rmem->pg_arr = (void **)cpr->cp_desc_ring; 3014 rmem->dma_arr = cpr->cp_desc_mapping; 3015 rmem->flags = BNXT_RMEM_RING_PTE_FLAG; 3016 rc = bnxt_alloc_ring(bp, rmem); 3017 if (rc) { 3018 bnxt_free_ring(bp, rmem); 3019 kfree(cpr); 3020 cpr = NULL; 3021 } 3022 return cpr; 3023 } 3024 3025 static int bnxt_alloc_cp_rings(struct bnxt *bp) 3026 { 3027 bool sh = !!(bp->flags & BNXT_FLAG_SHARED_RINGS); 3028 int i, rc, ulp_base_vec, ulp_msix; 3029 3030 ulp_msix = bnxt_get_ulp_msix_num(bp); 3031 ulp_base_vec = bnxt_get_ulp_msix_base(bp); 3032 for (i = 0; i < bp->cp_nr_rings; i++) { 3033 struct bnxt_napi *bnapi = bp->bnapi[i]; 3034 struct bnxt_cp_ring_info *cpr; 3035 struct bnxt_ring_struct *ring; 3036 3037 if (!bnapi) 3038 continue; 3039 3040 cpr = &bnapi->cp_ring; 3041 cpr->bnapi = bnapi; 3042 ring = &cpr->cp_ring_struct; 3043 3044 rc = bnxt_alloc_ring(bp, &ring->ring_mem); 3045 if (rc) 3046 return rc; 3047 3048 if (ulp_msix && i >= ulp_base_vec) 3049 ring->map_idx = i + ulp_msix; 3050 else 3051 ring->map_idx = i; 3052 3053 if (!(bp->flags & BNXT_FLAG_CHIP_P5)) 3054 continue; 3055 3056 if (i < bp->rx_nr_rings) { 3057 struct bnxt_cp_ring_info *cpr2 = 3058 bnxt_alloc_cp_sub_ring(bp); 3059 3060 cpr->cp_ring_arr[BNXT_RX_HDL] = cpr2; 3061 if (!cpr2) 3062 return -ENOMEM; 3063 cpr2->bnapi = bnapi; 3064 } 3065 if ((sh && i < bp->tx_nr_rings) || 3066 (!sh && i >= bp->rx_nr_rings)) { 3067 struct bnxt_cp_ring_info *cpr2 = 3068 bnxt_alloc_cp_sub_ring(bp); 3069 3070 cpr->cp_ring_arr[BNXT_TX_HDL] = cpr2; 3071 if (!cpr2) 3072 return -ENOMEM; 3073 cpr2->bnapi = bnapi; 3074 } 3075 } 3076 return 0; 3077 } 3078 3079 static void bnxt_init_ring_struct(struct bnxt *bp) 3080 { 3081 int i; 3082 3083 for (i = 0; i < bp->cp_nr_rings; i++) { 3084 struct bnxt_napi *bnapi = bp->bnapi[i]; 3085 struct bnxt_ring_mem_info *rmem; 3086 struct bnxt_cp_ring_info *cpr; 3087 struct bnxt_rx_ring_info *rxr; 3088 struct bnxt_tx_ring_info *txr; 3089 struct bnxt_ring_struct *ring; 3090 3091 if (!bnapi) 3092 continue; 3093 3094 cpr = &bnapi->cp_ring; 3095 ring = &cpr->cp_ring_struct; 3096 rmem = &ring->ring_mem; 3097 rmem->nr_pages = bp->cp_nr_pages; 3098 rmem->page_size = HW_CMPD_RING_SIZE; 3099 rmem->pg_arr = (void **)cpr->cp_desc_ring; 3100 rmem->dma_arr = cpr->cp_desc_mapping; 3101 rmem->vmem_size = 0; 3102 3103 rxr = bnapi->rx_ring; 3104 if (!rxr) 3105 goto skip_rx; 3106 3107 ring = &rxr->rx_ring_struct; 3108 rmem = &ring->ring_mem; 3109 rmem->nr_pages = bp->rx_nr_pages; 3110 rmem->page_size = HW_RXBD_RING_SIZE; 3111 rmem->pg_arr = (void **)rxr->rx_desc_ring; 3112 rmem->dma_arr = rxr->rx_desc_mapping; 3113 rmem->vmem_size = SW_RXBD_RING_SIZE * bp->rx_nr_pages; 3114 rmem->vmem = (void **)&rxr->rx_buf_ring; 3115 3116 ring = &rxr->rx_agg_ring_struct; 3117 rmem = &ring->ring_mem; 3118 rmem->nr_pages = bp->rx_agg_nr_pages; 3119 rmem->page_size = HW_RXBD_RING_SIZE; 3120 rmem->pg_arr = (void **)rxr->rx_agg_desc_ring; 3121 rmem->dma_arr = rxr->rx_agg_desc_mapping; 3122 rmem->vmem_size = SW_RXBD_AGG_RING_SIZE * bp->rx_agg_nr_pages; 3123 rmem->vmem = (void **)&rxr->rx_agg_ring; 3124 3125 skip_rx: 3126 txr = bnapi->tx_ring; 3127 if (!txr) 3128 continue; 3129 3130 ring = &txr->tx_ring_struct; 3131 rmem = &ring->ring_mem; 3132 rmem->nr_pages = bp->tx_nr_pages; 3133 rmem->page_size = HW_RXBD_RING_SIZE; 3134 rmem->pg_arr = (void **)txr->tx_desc_ring; 3135 rmem->dma_arr = txr->tx_desc_mapping; 3136 rmem->vmem_size = SW_TXBD_RING_SIZE * bp->tx_nr_pages; 3137 rmem->vmem = (void **)&txr->tx_buf_ring; 3138 } 3139 } 3140 3141 static void bnxt_init_rxbd_pages(struct bnxt_ring_struct *ring, u32 type) 3142 { 3143 int i; 3144 u32 prod; 3145 struct rx_bd **rx_buf_ring; 3146 3147 rx_buf_ring = (struct rx_bd **)ring->ring_mem.pg_arr; 3148 for (i = 0, prod = 0; i < ring->ring_mem.nr_pages; i++) { 3149 int j; 3150 struct rx_bd *rxbd; 3151 3152 rxbd = rx_buf_ring[i]; 3153 if (!rxbd) 3154 continue; 3155 3156 for (j = 0; j < RX_DESC_CNT; j++, rxbd++, prod++) { 3157 rxbd->rx_bd_len_flags_type = cpu_to_le32(type); 3158 rxbd->rx_bd_opaque = prod; 3159 } 3160 } 3161 } 3162 3163 static int bnxt_init_one_rx_ring(struct bnxt *bp, int ring_nr) 3164 { 3165 struct net_device *dev = bp->dev; 3166 struct bnxt_rx_ring_info *rxr; 3167 struct bnxt_ring_struct *ring; 3168 u32 prod, type; 3169 int i; 3170 3171 type = (bp->rx_buf_use_size << RX_BD_LEN_SHIFT) | 3172 RX_BD_TYPE_RX_PACKET_BD | RX_BD_FLAGS_EOP; 3173 3174 if (NET_IP_ALIGN == 2) 3175 type |= RX_BD_FLAGS_SOP; 3176 3177 rxr = &bp->rx_ring[ring_nr]; 3178 ring = &rxr->rx_ring_struct; 3179 bnxt_init_rxbd_pages(ring, type); 3180 3181 if (BNXT_RX_PAGE_MODE(bp) && bp->xdp_prog) { 3182 bpf_prog_add(bp->xdp_prog, 1); 3183 rxr->xdp_prog = bp->xdp_prog; 3184 } 3185 prod = rxr->rx_prod; 3186 for (i = 0; i < bp->rx_ring_size; i++) { 3187 if (bnxt_alloc_rx_data(bp, rxr, prod, GFP_KERNEL) != 0) { 3188 netdev_warn(dev, "init'ed rx ring %d with %d/%d skbs only\n", 3189 ring_nr, i, bp->rx_ring_size); 3190 break; 3191 } 3192 prod = NEXT_RX(prod); 3193 } 3194 rxr->rx_prod = prod; 3195 ring->fw_ring_id = INVALID_HW_RING_ID; 3196 3197 ring = &rxr->rx_agg_ring_struct; 3198 ring->fw_ring_id = INVALID_HW_RING_ID; 3199 3200 if (!(bp->flags & BNXT_FLAG_AGG_RINGS)) 3201 return 0; 3202 3203 type = ((u32)BNXT_RX_PAGE_SIZE << RX_BD_LEN_SHIFT) | 3204 RX_BD_TYPE_RX_AGG_BD | RX_BD_FLAGS_SOP; 3205 3206 bnxt_init_rxbd_pages(ring, type); 3207 3208 prod = rxr->rx_agg_prod; 3209 for (i = 0; i < bp->rx_agg_ring_size; i++) { 3210 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_KERNEL) != 0) { 3211 netdev_warn(dev, "init'ed rx ring %d with %d/%d pages only\n", 3212 ring_nr, i, bp->rx_ring_size); 3213 break; 3214 } 3215 prod = NEXT_RX_AGG(prod); 3216 } 3217 rxr->rx_agg_prod = prod; 3218 3219 if (bp->flags & BNXT_FLAG_TPA) { 3220 if (rxr->rx_tpa) { 3221 u8 *data; 3222 dma_addr_t mapping; 3223 3224 for (i = 0; i < bp->max_tpa; i++) { 3225 data = __bnxt_alloc_rx_data(bp, &mapping, 3226 GFP_KERNEL); 3227 if (!data) 3228 return -ENOMEM; 3229 3230 rxr->rx_tpa[i].data = data; 3231 rxr->rx_tpa[i].data_ptr = data + bp->rx_offset; 3232 rxr->rx_tpa[i].mapping = mapping; 3233 } 3234 } else { 3235 netdev_err(bp->dev, "No resource allocated for LRO/GRO\n"); 3236 return -ENOMEM; 3237 } 3238 } 3239 3240 return 0; 3241 } 3242 3243 static void bnxt_init_cp_rings(struct bnxt *bp) 3244 { 3245 int i, j; 3246 3247 for (i = 0; i < bp->cp_nr_rings; i++) { 3248 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring; 3249 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct; 3250 3251 ring->fw_ring_id = INVALID_HW_RING_ID; 3252 cpr->rx_ring_coal.coal_ticks = bp->rx_coal.coal_ticks; 3253 cpr->rx_ring_coal.coal_bufs = bp->rx_coal.coal_bufs; 3254 for (j = 0; j < 2; j++) { 3255 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j]; 3256 3257 if (!cpr2) 3258 continue; 3259 3260 ring = &cpr2->cp_ring_struct; 3261 ring->fw_ring_id = INVALID_HW_RING_ID; 3262 cpr2->rx_ring_coal.coal_ticks = bp->rx_coal.coal_ticks; 3263 cpr2->rx_ring_coal.coal_bufs = bp->rx_coal.coal_bufs; 3264 } 3265 } 3266 } 3267 3268 static int bnxt_init_rx_rings(struct bnxt *bp) 3269 { 3270 int i, rc = 0; 3271 3272 if (BNXT_RX_PAGE_MODE(bp)) { 3273 bp->rx_offset = NET_IP_ALIGN + XDP_PACKET_HEADROOM; 3274 bp->rx_dma_offset = XDP_PACKET_HEADROOM; 3275 } else { 3276 bp->rx_offset = BNXT_RX_OFFSET; 3277 bp->rx_dma_offset = BNXT_RX_DMA_OFFSET; 3278 } 3279 3280 for (i = 0; i < bp->rx_nr_rings; i++) { 3281 rc = bnxt_init_one_rx_ring(bp, i); 3282 if (rc) 3283 break; 3284 } 3285 3286 return rc; 3287 } 3288 3289 static int bnxt_init_tx_rings(struct bnxt *bp) 3290 { 3291 u16 i; 3292 3293 bp->tx_wake_thresh = max_t(int, bp->tx_ring_size / 2, 3294 MAX_SKB_FRAGS + 1); 3295 3296 for (i = 0; i < bp->tx_nr_rings; i++) { 3297 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; 3298 struct bnxt_ring_struct *ring = &txr->tx_ring_struct; 3299 3300 ring->fw_ring_id = INVALID_HW_RING_ID; 3301 } 3302 3303 return 0; 3304 } 3305 3306 static void bnxt_free_ring_grps(struct bnxt *bp) 3307 { 3308 kfree(bp->grp_info); 3309 bp->grp_info = NULL; 3310 } 3311 3312 static int bnxt_init_ring_grps(struct bnxt *bp, bool irq_re_init) 3313 { 3314 int i; 3315 3316 if (irq_re_init) { 3317 bp->grp_info = kcalloc(bp->cp_nr_rings, 3318 sizeof(struct bnxt_ring_grp_info), 3319 GFP_KERNEL); 3320 if (!bp->grp_info) 3321 return -ENOMEM; 3322 } 3323 for (i = 0; i < bp->cp_nr_rings; i++) { 3324 if (irq_re_init) 3325 bp->grp_info[i].fw_stats_ctx = INVALID_HW_RING_ID; 3326 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID; 3327 bp->grp_info[i].rx_fw_ring_id = INVALID_HW_RING_ID; 3328 bp->grp_info[i].agg_fw_ring_id = INVALID_HW_RING_ID; 3329 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID; 3330 } 3331 return 0; 3332 } 3333 3334 static void bnxt_free_vnics(struct bnxt *bp) 3335 { 3336 kfree(bp->vnic_info); 3337 bp->vnic_info = NULL; 3338 bp->nr_vnics = 0; 3339 } 3340 3341 static int bnxt_alloc_vnics(struct bnxt *bp) 3342 { 3343 int num_vnics = 1; 3344 3345 #ifdef CONFIG_RFS_ACCEL 3346 if ((bp->flags & (BNXT_FLAG_RFS | BNXT_FLAG_CHIP_P5)) == BNXT_FLAG_RFS) 3347 num_vnics += bp->rx_nr_rings; 3348 #endif 3349 3350 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 3351 num_vnics++; 3352 3353 bp->vnic_info = kcalloc(num_vnics, sizeof(struct bnxt_vnic_info), 3354 GFP_KERNEL); 3355 if (!bp->vnic_info) 3356 return -ENOMEM; 3357 3358 bp->nr_vnics = num_vnics; 3359 return 0; 3360 } 3361 3362 static void bnxt_init_vnics(struct bnxt *bp) 3363 { 3364 int i; 3365 3366 for (i = 0; i < bp->nr_vnics; i++) { 3367 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 3368 int j; 3369 3370 vnic->fw_vnic_id = INVALID_HW_RING_ID; 3371 for (j = 0; j < BNXT_MAX_CTX_PER_VNIC; j++) 3372 vnic->fw_rss_cos_lb_ctx[j] = INVALID_HW_RING_ID; 3373 3374 vnic->fw_l2_ctx_id = INVALID_HW_RING_ID; 3375 3376 if (bp->vnic_info[i].rss_hash_key) { 3377 if (i == 0) 3378 prandom_bytes(vnic->rss_hash_key, 3379 HW_HASH_KEY_SIZE); 3380 else 3381 memcpy(vnic->rss_hash_key, 3382 bp->vnic_info[0].rss_hash_key, 3383 HW_HASH_KEY_SIZE); 3384 } 3385 } 3386 } 3387 3388 static int bnxt_calc_nr_ring_pages(u32 ring_size, int desc_per_pg) 3389 { 3390 int pages; 3391 3392 pages = ring_size / desc_per_pg; 3393 3394 if (!pages) 3395 return 1; 3396 3397 pages++; 3398 3399 while (pages & (pages - 1)) 3400 pages++; 3401 3402 return pages; 3403 } 3404 3405 void bnxt_set_tpa_flags(struct bnxt *bp) 3406 { 3407 bp->flags &= ~BNXT_FLAG_TPA; 3408 if (bp->flags & BNXT_FLAG_NO_AGG_RINGS) 3409 return; 3410 if (bp->dev->features & NETIF_F_LRO) 3411 bp->flags |= BNXT_FLAG_LRO; 3412 else if (bp->dev->features & NETIF_F_GRO_HW) 3413 bp->flags |= BNXT_FLAG_GRO; 3414 } 3415 3416 /* bp->rx_ring_size, bp->tx_ring_size, dev->mtu, BNXT_FLAG_{G|L}RO flags must 3417 * be set on entry. 3418 */ 3419 void bnxt_set_ring_params(struct bnxt *bp) 3420 { 3421 u32 ring_size, rx_size, rx_space, max_rx_cmpl; 3422 u32 agg_factor = 0, agg_ring_size = 0; 3423 3424 /* 8 for CRC and VLAN */ 3425 rx_size = SKB_DATA_ALIGN(bp->dev->mtu + ETH_HLEN + NET_IP_ALIGN + 8); 3426 3427 rx_space = rx_size + NET_SKB_PAD + 3428 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 3429 3430 bp->rx_copy_thresh = BNXT_RX_COPY_THRESH; 3431 ring_size = bp->rx_ring_size; 3432 bp->rx_agg_ring_size = 0; 3433 bp->rx_agg_nr_pages = 0; 3434 3435 if (bp->flags & BNXT_FLAG_TPA) 3436 agg_factor = min_t(u32, 4, 65536 / BNXT_RX_PAGE_SIZE); 3437 3438 bp->flags &= ~BNXT_FLAG_JUMBO; 3439 if (rx_space > PAGE_SIZE && !(bp->flags & BNXT_FLAG_NO_AGG_RINGS)) { 3440 u32 jumbo_factor; 3441 3442 bp->flags |= BNXT_FLAG_JUMBO; 3443 jumbo_factor = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT; 3444 if (jumbo_factor > agg_factor) 3445 agg_factor = jumbo_factor; 3446 } 3447 agg_ring_size = ring_size * agg_factor; 3448 3449 if (agg_ring_size) { 3450 bp->rx_agg_nr_pages = bnxt_calc_nr_ring_pages(agg_ring_size, 3451 RX_DESC_CNT); 3452 if (bp->rx_agg_nr_pages > MAX_RX_AGG_PAGES) { 3453 u32 tmp = agg_ring_size; 3454 3455 bp->rx_agg_nr_pages = MAX_RX_AGG_PAGES; 3456 agg_ring_size = MAX_RX_AGG_PAGES * RX_DESC_CNT - 1; 3457 netdev_warn(bp->dev, "rx agg ring size %d reduced to %d.\n", 3458 tmp, agg_ring_size); 3459 } 3460 bp->rx_agg_ring_size = agg_ring_size; 3461 bp->rx_agg_ring_mask = (bp->rx_agg_nr_pages * RX_DESC_CNT) - 1; 3462 rx_size = SKB_DATA_ALIGN(BNXT_RX_COPY_THRESH + NET_IP_ALIGN); 3463 rx_space = rx_size + NET_SKB_PAD + 3464 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 3465 } 3466 3467 bp->rx_buf_use_size = rx_size; 3468 bp->rx_buf_size = rx_space; 3469 3470 bp->rx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, RX_DESC_CNT); 3471 bp->rx_ring_mask = (bp->rx_nr_pages * RX_DESC_CNT) - 1; 3472 3473 ring_size = bp->tx_ring_size; 3474 bp->tx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, TX_DESC_CNT); 3475 bp->tx_ring_mask = (bp->tx_nr_pages * TX_DESC_CNT) - 1; 3476 3477 max_rx_cmpl = bp->rx_ring_size; 3478 /* MAX TPA needs to be added because TPA_START completions are 3479 * immediately recycled, so the TPA completions are not bound by 3480 * the RX ring size. 3481 */ 3482 if (bp->flags & BNXT_FLAG_TPA) 3483 max_rx_cmpl += bp->max_tpa; 3484 /* RX and TPA completions are 32-byte, all others are 16-byte */ 3485 ring_size = max_rx_cmpl * 2 + agg_ring_size + bp->tx_ring_size; 3486 bp->cp_ring_size = ring_size; 3487 3488 bp->cp_nr_pages = bnxt_calc_nr_ring_pages(ring_size, CP_DESC_CNT); 3489 if (bp->cp_nr_pages > MAX_CP_PAGES) { 3490 bp->cp_nr_pages = MAX_CP_PAGES; 3491 bp->cp_ring_size = MAX_CP_PAGES * CP_DESC_CNT - 1; 3492 netdev_warn(bp->dev, "completion ring size %d reduced to %d.\n", 3493 ring_size, bp->cp_ring_size); 3494 } 3495 bp->cp_bit = bp->cp_nr_pages * CP_DESC_CNT; 3496 bp->cp_ring_mask = bp->cp_bit - 1; 3497 } 3498 3499 /* Changing allocation mode of RX rings. 3500 * TODO: Update when extending xdp_rxq_info to support allocation modes. 3501 */ 3502 int bnxt_set_rx_skb_mode(struct bnxt *bp, bool page_mode) 3503 { 3504 if (page_mode) { 3505 if (bp->dev->mtu > BNXT_MAX_PAGE_MODE_MTU) 3506 return -EOPNOTSUPP; 3507 bp->dev->max_mtu = 3508 min_t(u16, bp->max_mtu, BNXT_MAX_PAGE_MODE_MTU); 3509 bp->flags &= ~BNXT_FLAG_AGG_RINGS; 3510 bp->flags |= BNXT_FLAG_NO_AGG_RINGS | BNXT_FLAG_RX_PAGE_MODE; 3511 bp->rx_dir = DMA_BIDIRECTIONAL; 3512 bp->rx_skb_func = bnxt_rx_page_skb; 3513 /* Disable LRO or GRO_HW */ 3514 netdev_update_features(bp->dev); 3515 } else { 3516 bp->dev->max_mtu = bp->max_mtu; 3517 bp->flags &= ~BNXT_FLAG_RX_PAGE_MODE; 3518 bp->rx_dir = DMA_FROM_DEVICE; 3519 bp->rx_skb_func = bnxt_rx_skb; 3520 } 3521 return 0; 3522 } 3523 3524 static void bnxt_free_vnic_attributes(struct bnxt *bp) 3525 { 3526 int i; 3527 struct bnxt_vnic_info *vnic; 3528 struct pci_dev *pdev = bp->pdev; 3529 3530 if (!bp->vnic_info) 3531 return; 3532 3533 for (i = 0; i < bp->nr_vnics; i++) { 3534 vnic = &bp->vnic_info[i]; 3535 3536 kfree(vnic->fw_grp_ids); 3537 vnic->fw_grp_ids = NULL; 3538 3539 kfree(vnic->uc_list); 3540 vnic->uc_list = NULL; 3541 3542 if (vnic->mc_list) { 3543 dma_free_coherent(&pdev->dev, vnic->mc_list_size, 3544 vnic->mc_list, vnic->mc_list_mapping); 3545 vnic->mc_list = NULL; 3546 } 3547 3548 if (vnic->rss_table) { 3549 dma_free_coherent(&pdev->dev, PAGE_SIZE, 3550 vnic->rss_table, 3551 vnic->rss_table_dma_addr); 3552 vnic->rss_table = NULL; 3553 } 3554 3555 vnic->rss_hash_key = NULL; 3556 vnic->flags = 0; 3557 } 3558 } 3559 3560 static int bnxt_alloc_vnic_attributes(struct bnxt *bp) 3561 { 3562 int i, rc = 0, size; 3563 struct bnxt_vnic_info *vnic; 3564 struct pci_dev *pdev = bp->pdev; 3565 int max_rings; 3566 3567 for (i = 0; i < bp->nr_vnics; i++) { 3568 vnic = &bp->vnic_info[i]; 3569 3570 if (vnic->flags & BNXT_VNIC_UCAST_FLAG) { 3571 int mem_size = (BNXT_MAX_UC_ADDRS - 1) * ETH_ALEN; 3572 3573 if (mem_size > 0) { 3574 vnic->uc_list = kmalloc(mem_size, GFP_KERNEL); 3575 if (!vnic->uc_list) { 3576 rc = -ENOMEM; 3577 goto out; 3578 } 3579 } 3580 } 3581 3582 if (vnic->flags & BNXT_VNIC_MCAST_FLAG) { 3583 vnic->mc_list_size = BNXT_MAX_MC_ADDRS * ETH_ALEN; 3584 vnic->mc_list = 3585 dma_alloc_coherent(&pdev->dev, 3586 vnic->mc_list_size, 3587 &vnic->mc_list_mapping, 3588 GFP_KERNEL); 3589 if (!vnic->mc_list) { 3590 rc = -ENOMEM; 3591 goto out; 3592 } 3593 } 3594 3595 if (bp->flags & BNXT_FLAG_CHIP_P5) 3596 goto vnic_skip_grps; 3597 3598 if (vnic->flags & BNXT_VNIC_RSS_FLAG) 3599 max_rings = bp->rx_nr_rings; 3600 else 3601 max_rings = 1; 3602 3603 vnic->fw_grp_ids = kcalloc(max_rings, sizeof(u16), GFP_KERNEL); 3604 if (!vnic->fw_grp_ids) { 3605 rc = -ENOMEM; 3606 goto out; 3607 } 3608 vnic_skip_grps: 3609 if ((bp->flags & BNXT_FLAG_NEW_RSS_CAP) && 3610 !(vnic->flags & BNXT_VNIC_RSS_FLAG)) 3611 continue; 3612 3613 /* Allocate rss table and hash key */ 3614 vnic->rss_table = dma_alloc_coherent(&pdev->dev, PAGE_SIZE, 3615 &vnic->rss_table_dma_addr, 3616 GFP_KERNEL); 3617 if (!vnic->rss_table) { 3618 rc = -ENOMEM; 3619 goto out; 3620 } 3621 3622 size = L1_CACHE_ALIGN(HW_HASH_INDEX_SIZE * sizeof(u16)); 3623 3624 vnic->rss_hash_key = ((void *)vnic->rss_table) + size; 3625 vnic->rss_hash_key_dma_addr = vnic->rss_table_dma_addr + size; 3626 } 3627 return 0; 3628 3629 out: 3630 return rc; 3631 } 3632 3633 static void bnxt_free_hwrm_resources(struct bnxt *bp) 3634 { 3635 struct pci_dev *pdev = bp->pdev; 3636 3637 if (bp->hwrm_cmd_resp_addr) { 3638 dma_free_coherent(&pdev->dev, PAGE_SIZE, bp->hwrm_cmd_resp_addr, 3639 bp->hwrm_cmd_resp_dma_addr); 3640 bp->hwrm_cmd_resp_addr = NULL; 3641 } 3642 3643 if (bp->hwrm_cmd_kong_resp_addr) { 3644 dma_free_coherent(&pdev->dev, PAGE_SIZE, 3645 bp->hwrm_cmd_kong_resp_addr, 3646 bp->hwrm_cmd_kong_resp_dma_addr); 3647 bp->hwrm_cmd_kong_resp_addr = NULL; 3648 } 3649 } 3650 3651 static int bnxt_alloc_kong_hwrm_resources(struct bnxt *bp) 3652 { 3653 struct pci_dev *pdev = bp->pdev; 3654 3655 if (bp->hwrm_cmd_kong_resp_addr) 3656 return 0; 3657 3658 bp->hwrm_cmd_kong_resp_addr = 3659 dma_alloc_coherent(&pdev->dev, PAGE_SIZE, 3660 &bp->hwrm_cmd_kong_resp_dma_addr, 3661 GFP_KERNEL); 3662 if (!bp->hwrm_cmd_kong_resp_addr) 3663 return -ENOMEM; 3664 3665 return 0; 3666 } 3667 3668 static int bnxt_alloc_hwrm_resources(struct bnxt *bp) 3669 { 3670 struct pci_dev *pdev = bp->pdev; 3671 3672 bp->hwrm_cmd_resp_addr = dma_alloc_coherent(&pdev->dev, PAGE_SIZE, 3673 &bp->hwrm_cmd_resp_dma_addr, 3674 GFP_KERNEL); 3675 if (!bp->hwrm_cmd_resp_addr) 3676 return -ENOMEM; 3677 3678 return 0; 3679 } 3680 3681 static void bnxt_free_hwrm_short_cmd_req(struct bnxt *bp) 3682 { 3683 if (bp->hwrm_short_cmd_req_addr) { 3684 struct pci_dev *pdev = bp->pdev; 3685 3686 dma_free_coherent(&pdev->dev, bp->hwrm_max_ext_req_len, 3687 bp->hwrm_short_cmd_req_addr, 3688 bp->hwrm_short_cmd_req_dma_addr); 3689 bp->hwrm_short_cmd_req_addr = NULL; 3690 } 3691 } 3692 3693 static int bnxt_alloc_hwrm_short_cmd_req(struct bnxt *bp) 3694 { 3695 struct pci_dev *pdev = bp->pdev; 3696 3697 if (bp->hwrm_short_cmd_req_addr) 3698 return 0; 3699 3700 bp->hwrm_short_cmd_req_addr = 3701 dma_alloc_coherent(&pdev->dev, bp->hwrm_max_ext_req_len, 3702 &bp->hwrm_short_cmd_req_dma_addr, 3703 GFP_KERNEL); 3704 if (!bp->hwrm_short_cmd_req_addr) 3705 return -ENOMEM; 3706 3707 return 0; 3708 } 3709 3710 static void bnxt_free_port_stats(struct bnxt *bp) 3711 { 3712 struct pci_dev *pdev = bp->pdev; 3713 3714 bp->flags &= ~BNXT_FLAG_PORT_STATS; 3715 bp->flags &= ~BNXT_FLAG_PORT_STATS_EXT; 3716 3717 if (bp->hw_rx_port_stats) { 3718 dma_free_coherent(&pdev->dev, bp->hw_port_stats_size, 3719 bp->hw_rx_port_stats, 3720 bp->hw_rx_port_stats_map); 3721 bp->hw_rx_port_stats = NULL; 3722 } 3723 3724 if (bp->hw_tx_port_stats_ext) { 3725 dma_free_coherent(&pdev->dev, sizeof(struct tx_port_stats_ext), 3726 bp->hw_tx_port_stats_ext, 3727 bp->hw_tx_port_stats_ext_map); 3728 bp->hw_tx_port_stats_ext = NULL; 3729 } 3730 3731 if (bp->hw_rx_port_stats_ext) { 3732 dma_free_coherent(&pdev->dev, sizeof(struct rx_port_stats_ext), 3733 bp->hw_rx_port_stats_ext, 3734 bp->hw_rx_port_stats_ext_map); 3735 bp->hw_rx_port_stats_ext = NULL; 3736 } 3737 3738 if (bp->hw_pcie_stats) { 3739 dma_free_coherent(&pdev->dev, sizeof(struct pcie_ctx_hw_stats), 3740 bp->hw_pcie_stats, bp->hw_pcie_stats_map); 3741 bp->hw_pcie_stats = NULL; 3742 } 3743 } 3744 3745 static void bnxt_free_ring_stats(struct bnxt *bp) 3746 { 3747 struct pci_dev *pdev = bp->pdev; 3748 int size, i; 3749 3750 if (!bp->bnapi) 3751 return; 3752 3753 size = bp->hw_ring_stats_size; 3754 3755 for (i = 0; i < bp->cp_nr_rings; i++) { 3756 struct bnxt_napi *bnapi = bp->bnapi[i]; 3757 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 3758 3759 if (cpr->hw_stats) { 3760 dma_free_coherent(&pdev->dev, size, cpr->hw_stats, 3761 cpr->hw_stats_map); 3762 cpr->hw_stats = NULL; 3763 } 3764 } 3765 } 3766 3767 static int bnxt_alloc_stats(struct bnxt *bp) 3768 { 3769 u32 size, i; 3770 struct pci_dev *pdev = bp->pdev; 3771 3772 size = bp->hw_ring_stats_size; 3773 3774 for (i = 0; i < bp->cp_nr_rings; i++) { 3775 struct bnxt_napi *bnapi = bp->bnapi[i]; 3776 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 3777 3778 cpr->hw_stats = dma_alloc_coherent(&pdev->dev, size, 3779 &cpr->hw_stats_map, 3780 GFP_KERNEL); 3781 if (!cpr->hw_stats) 3782 return -ENOMEM; 3783 3784 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID; 3785 } 3786 3787 if (BNXT_VF(bp) || bp->chip_num == CHIP_NUM_58700) 3788 return 0; 3789 3790 if (bp->hw_rx_port_stats) 3791 goto alloc_ext_stats; 3792 3793 bp->hw_port_stats_size = sizeof(struct rx_port_stats) + 3794 sizeof(struct tx_port_stats) + 1024; 3795 3796 bp->hw_rx_port_stats = 3797 dma_alloc_coherent(&pdev->dev, bp->hw_port_stats_size, 3798 &bp->hw_rx_port_stats_map, 3799 GFP_KERNEL); 3800 if (!bp->hw_rx_port_stats) 3801 return -ENOMEM; 3802 3803 bp->hw_tx_port_stats = (void *)(bp->hw_rx_port_stats + 1) + 512; 3804 bp->hw_tx_port_stats_map = bp->hw_rx_port_stats_map + 3805 sizeof(struct rx_port_stats) + 512; 3806 bp->flags |= BNXT_FLAG_PORT_STATS; 3807 3808 alloc_ext_stats: 3809 /* Display extended statistics only if FW supports it */ 3810 if (bp->hwrm_spec_code < 0x10804 || bp->hwrm_spec_code == 0x10900) 3811 if (!(bp->fw_cap & BNXT_FW_CAP_EXT_STATS_SUPPORTED)) 3812 return 0; 3813 3814 if (bp->hw_rx_port_stats_ext) 3815 goto alloc_tx_ext_stats; 3816 3817 bp->hw_rx_port_stats_ext = 3818 dma_alloc_coherent(&pdev->dev, sizeof(struct rx_port_stats_ext), 3819 &bp->hw_rx_port_stats_ext_map, GFP_KERNEL); 3820 if (!bp->hw_rx_port_stats_ext) 3821 return 0; 3822 3823 alloc_tx_ext_stats: 3824 if (bp->hw_tx_port_stats_ext) 3825 goto alloc_pcie_stats; 3826 3827 if (bp->hwrm_spec_code >= 0x10902 || 3828 (bp->fw_cap & BNXT_FW_CAP_EXT_STATS_SUPPORTED)) { 3829 bp->hw_tx_port_stats_ext = 3830 dma_alloc_coherent(&pdev->dev, 3831 sizeof(struct tx_port_stats_ext), 3832 &bp->hw_tx_port_stats_ext_map, 3833 GFP_KERNEL); 3834 } 3835 bp->flags |= BNXT_FLAG_PORT_STATS_EXT; 3836 3837 alloc_pcie_stats: 3838 if (bp->hw_pcie_stats || 3839 !(bp->fw_cap & BNXT_FW_CAP_PCIE_STATS_SUPPORTED)) 3840 return 0; 3841 3842 bp->hw_pcie_stats = 3843 dma_alloc_coherent(&pdev->dev, sizeof(struct pcie_ctx_hw_stats), 3844 &bp->hw_pcie_stats_map, GFP_KERNEL); 3845 if (!bp->hw_pcie_stats) 3846 return 0; 3847 3848 bp->flags |= BNXT_FLAG_PCIE_STATS; 3849 return 0; 3850 } 3851 3852 static void bnxt_clear_ring_indices(struct bnxt *bp) 3853 { 3854 int i; 3855 3856 if (!bp->bnapi) 3857 return; 3858 3859 for (i = 0; i < bp->cp_nr_rings; i++) { 3860 struct bnxt_napi *bnapi = bp->bnapi[i]; 3861 struct bnxt_cp_ring_info *cpr; 3862 struct bnxt_rx_ring_info *rxr; 3863 struct bnxt_tx_ring_info *txr; 3864 3865 if (!bnapi) 3866 continue; 3867 3868 cpr = &bnapi->cp_ring; 3869 cpr->cp_raw_cons = 0; 3870 3871 txr = bnapi->tx_ring; 3872 if (txr) { 3873 txr->tx_prod = 0; 3874 txr->tx_cons = 0; 3875 } 3876 3877 rxr = bnapi->rx_ring; 3878 if (rxr) { 3879 rxr->rx_prod = 0; 3880 rxr->rx_agg_prod = 0; 3881 rxr->rx_sw_agg_prod = 0; 3882 rxr->rx_next_cons = 0; 3883 } 3884 } 3885 } 3886 3887 static void bnxt_free_ntp_fltrs(struct bnxt *bp, bool irq_reinit) 3888 { 3889 #ifdef CONFIG_RFS_ACCEL 3890 int i; 3891 3892 /* Under rtnl_lock and all our NAPIs have been disabled. It's 3893 * safe to delete the hash table. 3894 */ 3895 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) { 3896 struct hlist_head *head; 3897 struct hlist_node *tmp; 3898 struct bnxt_ntuple_filter *fltr; 3899 3900 head = &bp->ntp_fltr_hash_tbl[i]; 3901 hlist_for_each_entry_safe(fltr, tmp, head, hash) { 3902 hlist_del(&fltr->hash); 3903 kfree(fltr); 3904 } 3905 } 3906 if (irq_reinit) { 3907 kfree(bp->ntp_fltr_bmap); 3908 bp->ntp_fltr_bmap = NULL; 3909 } 3910 bp->ntp_fltr_count = 0; 3911 #endif 3912 } 3913 3914 static int bnxt_alloc_ntp_fltrs(struct bnxt *bp) 3915 { 3916 #ifdef CONFIG_RFS_ACCEL 3917 int i, rc = 0; 3918 3919 if (!(bp->flags & BNXT_FLAG_RFS)) 3920 return 0; 3921 3922 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) 3923 INIT_HLIST_HEAD(&bp->ntp_fltr_hash_tbl[i]); 3924 3925 bp->ntp_fltr_count = 0; 3926 bp->ntp_fltr_bmap = kcalloc(BITS_TO_LONGS(BNXT_NTP_FLTR_MAX_FLTR), 3927 sizeof(long), 3928 GFP_KERNEL); 3929 3930 if (!bp->ntp_fltr_bmap) 3931 rc = -ENOMEM; 3932 3933 return rc; 3934 #else 3935 return 0; 3936 #endif 3937 } 3938 3939 static void bnxt_free_mem(struct bnxt *bp, bool irq_re_init) 3940 { 3941 bnxt_free_vnic_attributes(bp); 3942 bnxt_free_tx_rings(bp); 3943 bnxt_free_rx_rings(bp); 3944 bnxt_free_cp_rings(bp); 3945 bnxt_free_ntp_fltrs(bp, irq_re_init); 3946 if (irq_re_init) { 3947 bnxt_free_ring_stats(bp); 3948 bnxt_free_ring_grps(bp); 3949 bnxt_free_vnics(bp); 3950 kfree(bp->tx_ring_map); 3951 bp->tx_ring_map = NULL; 3952 kfree(bp->tx_ring); 3953 bp->tx_ring = NULL; 3954 kfree(bp->rx_ring); 3955 bp->rx_ring = NULL; 3956 kfree(bp->bnapi); 3957 bp->bnapi = NULL; 3958 } else { 3959 bnxt_clear_ring_indices(bp); 3960 } 3961 } 3962 3963 static int bnxt_alloc_mem(struct bnxt *bp, bool irq_re_init) 3964 { 3965 int i, j, rc, size, arr_size; 3966 void *bnapi; 3967 3968 if (irq_re_init) { 3969 /* Allocate bnapi mem pointer array and mem block for 3970 * all queues 3971 */ 3972 arr_size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi *) * 3973 bp->cp_nr_rings); 3974 size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi)); 3975 bnapi = kzalloc(arr_size + size * bp->cp_nr_rings, GFP_KERNEL); 3976 if (!bnapi) 3977 return -ENOMEM; 3978 3979 bp->bnapi = bnapi; 3980 bnapi += arr_size; 3981 for (i = 0; i < bp->cp_nr_rings; i++, bnapi += size) { 3982 bp->bnapi[i] = bnapi; 3983 bp->bnapi[i]->index = i; 3984 bp->bnapi[i]->bp = bp; 3985 if (bp->flags & BNXT_FLAG_CHIP_P5) { 3986 struct bnxt_cp_ring_info *cpr = 3987 &bp->bnapi[i]->cp_ring; 3988 3989 cpr->cp_ring_struct.ring_mem.flags = 3990 BNXT_RMEM_RING_PTE_FLAG; 3991 } 3992 } 3993 3994 bp->rx_ring = kcalloc(bp->rx_nr_rings, 3995 sizeof(struct bnxt_rx_ring_info), 3996 GFP_KERNEL); 3997 if (!bp->rx_ring) 3998 return -ENOMEM; 3999 4000 for (i = 0; i < bp->rx_nr_rings; i++) { 4001 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 4002 4003 if (bp->flags & BNXT_FLAG_CHIP_P5) { 4004 rxr->rx_ring_struct.ring_mem.flags = 4005 BNXT_RMEM_RING_PTE_FLAG; 4006 rxr->rx_agg_ring_struct.ring_mem.flags = 4007 BNXT_RMEM_RING_PTE_FLAG; 4008 } 4009 rxr->bnapi = bp->bnapi[i]; 4010 bp->bnapi[i]->rx_ring = &bp->rx_ring[i]; 4011 } 4012 4013 bp->tx_ring = kcalloc(bp->tx_nr_rings, 4014 sizeof(struct bnxt_tx_ring_info), 4015 GFP_KERNEL); 4016 if (!bp->tx_ring) 4017 return -ENOMEM; 4018 4019 bp->tx_ring_map = kcalloc(bp->tx_nr_rings, sizeof(u16), 4020 GFP_KERNEL); 4021 4022 if (!bp->tx_ring_map) 4023 return -ENOMEM; 4024 4025 if (bp->flags & BNXT_FLAG_SHARED_RINGS) 4026 j = 0; 4027 else 4028 j = bp->rx_nr_rings; 4029 4030 for (i = 0; i < bp->tx_nr_rings; i++, j++) { 4031 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; 4032 4033 if (bp->flags & BNXT_FLAG_CHIP_P5) 4034 txr->tx_ring_struct.ring_mem.flags = 4035 BNXT_RMEM_RING_PTE_FLAG; 4036 txr->bnapi = bp->bnapi[j]; 4037 bp->bnapi[j]->tx_ring = txr; 4038 bp->tx_ring_map[i] = bp->tx_nr_rings_xdp + i; 4039 if (i >= bp->tx_nr_rings_xdp) { 4040 txr->txq_index = i - bp->tx_nr_rings_xdp; 4041 bp->bnapi[j]->tx_int = bnxt_tx_int; 4042 } else { 4043 bp->bnapi[j]->flags |= BNXT_NAPI_FLAG_XDP; 4044 bp->bnapi[j]->tx_int = bnxt_tx_int_xdp; 4045 } 4046 } 4047 4048 rc = bnxt_alloc_stats(bp); 4049 if (rc) 4050 goto alloc_mem_err; 4051 4052 rc = bnxt_alloc_ntp_fltrs(bp); 4053 if (rc) 4054 goto alloc_mem_err; 4055 4056 rc = bnxt_alloc_vnics(bp); 4057 if (rc) 4058 goto alloc_mem_err; 4059 } 4060 4061 bnxt_init_ring_struct(bp); 4062 4063 rc = bnxt_alloc_rx_rings(bp); 4064 if (rc) 4065 goto alloc_mem_err; 4066 4067 rc = bnxt_alloc_tx_rings(bp); 4068 if (rc) 4069 goto alloc_mem_err; 4070 4071 rc = bnxt_alloc_cp_rings(bp); 4072 if (rc) 4073 goto alloc_mem_err; 4074 4075 bp->vnic_info[0].flags |= BNXT_VNIC_RSS_FLAG | BNXT_VNIC_MCAST_FLAG | 4076 BNXT_VNIC_UCAST_FLAG; 4077 rc = bnxt_alloc_vnic_attributes(bp); 4078 if (rc) 4079 goto alloc_mem_err; 4080 return 0; 4081 4082 alloc_mem_err: 4083 bnxt_free_mem(bp, true); 4084 return rc; 4085 } 4086 4087 static void bnxt_disable_int(struct bnxt *bp) 4088 { 4089 int i; 4090 4091 if (!bp->bnapi) 4092 return; 4093 4094 for (i = 0; i < bp->cp_nr_rings; i++) { 4095 struct bnxt_napi *bnapi = bp->bnapi[i]; 4096 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 4097 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct; 4098 4099 if (ring->fw_ring_id != INVALID_HW_RING_ID) 4100 bnxt_db_nq(bp, &cpr->cp_db, cpr->cp_raw_cons); 4101 } 4102 } 4103 4104 static int bnxt_cp_num_to_irq_num(struct bnxt *bp, int n) 4105 { 4106 struct bnxt_napi *bnapi = bp->bnapi[n]; 4107 struct bnxt_cp_ring_info *cpr; 4108 4109 cpr = &bnapi->cp_ring; 4110 return cpr->cp_ring_struct.map_idx; 4111 } 4112 4113 static void bnxt_disable_int_sync(struct bnxt *bp) 4114 { 4115 int i; 4116 4117 atomic_inc(&bp->intr_sem); 4118 4119 bnxt_disable_int(bp); 4120 for (i = 0; i < bp->cp_nr_rings; i++) { 4121 int map_idx = bnxt_cp_num_to_irq_num(bp, i); 4122 4123 synchronize_irq(bp->irq_tbl[map_idx].vector); 4124 } 4125 } 4126 4127 static void bnxt_enable_int(struct bnxt *bp) 4128 { 4129 int i; 4130 4131 atomic_set(&bp->intr_sem, 0); 4132 for (i = 0; i < bp->cp_nr_rings; i++) { 4133 struct bnxt_napi *bnapi = bp->bnapi[i]; 4134 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 4135 4136 bnxt_db_nq_arm(bp, &cpr->cp_db, cpr->cp_raw_cons); 4137 } 4138 } 4139 4140 void bnxt_hwrm_cmd_hdr_init(struct bnxt *bp, void *request, u16 req_type, 4141 u16 cmpl_ring, u16 target_id) 4142 { 4143 struct input *req = request; 4144 4145 req->req_type = cpu_to_le16(req_type); 4146 req->cmpl_ring = cpu_to_le16(cmpl_ring); 4147 req->target_id = cpu_to_le16(target_id); 4148 if (bnxt_kong_hwrm_message(bp, req)) 4149 req->resp_addr = cpu_to_le64(bp->hwrm_cmd_kong_resp_dma_addr); 4150 else 4151 req->resp_addr = cpu_to_le64(bp->hwrm_cmd_resp_dma_addr); 4152 } 4153 4154 static int bnxt_hwrm_to_stderr(u32 hwrm_err) 4155 { 4156 switch (hwrm_err) { 4157 case HWRM_ERR_CODE_SUCCESS: 4158 return 0; 4159 case HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED: 4160 return -EACCES; 4161 case HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR: 4162 return -ENOSPC; 4163 case HWRM_ERR_CODE_INVALID_PARAMS: 4164 case HWRM_ERR_CODE_INVALID_FLAGS: 4165 case HWRM_ERR_CODE_INVALID_ENABLES: 4166 case HWRM_ERR_CODE_UNSUPPORTED_TLV: 4167 case HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR: 4168 return -EINVAL; 4169 case HWRM_ERR_CODE_NO_BUFFER: 4170 return -ENOMEM; 4171 case HWRM_ERR_CODE_HOT_RESET_PROGRESS: 4172 case HWRM_ERR_CODE_BUSY: 4173 return -EAGAIN; 4174 case HWRM_ERR_CODE_CMD_NOT_SUPPORTED: 4175 return -EOPNOTSUPP; 4176 default: 4177 return -EIO; 4178 } 4179 } 4180 4181 static int bnxt_hwrm_do_send_msg(struct bnxt *bp, void *msg, u32 msg_len, 4182 int timeout, bool silent) 4183 { 4184 int i, intr_process, rc, tmo_count; 4185 struct input *req = msg; 4186 u32 *data = msg; 4187 u8 *valid; 4188 u16 cp_ring_id, len = 0; 4189 struct hwrm_err_output *resp = bp->hwrm_cmd_resp_addr; 4190 u16 max_req_len = BNXT_HWRM_MAX_REQ_LEN; 4191 struct hwrm_short_input short_input = {0}; 4192 u32 doorbell_offset = BNXT_GRCPF_REG_CHIMP_COMM_TRIGGER; 4193 u32 bar_offset = BNXT_GRCPF_REG_CHIMP_COMM; 4194 u16 dst = BNXT_HWRM_CHNL_CHIMP; 4195 4196 if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state)) 4197 return -EBUSY; 4198 4199 if (msg_len > BNXT_HWRM_MAX_REQ_LEN) { 4200 if (msg_len > bp->hwrm_max_ext_req_len || 4201 !bp->hwrm_short_cmd_req_addr) 4202 return -EINVAL; 4203 } 4204 4205 if (bnxt_hwrm_kong_chnl(bp, req)) { 4206 dst = BNXT_HWRM_CHNL_KONG; 4207 bar_offset = BNXT_GRCPF_REG_KONG_COMM; 4208 doorbell_offset = BNXT_GRCPF_REG_KONG_COMM_TRIGGER; 4209 resp = bp->hwrm_cmd_kong_resp_addr; 4210 } 4211 4212 memset(resp, 0, PAGE_SIZE); 4213 cp_ring_id = le16_to_cpu(req->cmpl_ring); 4214 intr_process = (cp_ring_id == INVALID_HW_RING_ID) ? 0 : 1; 4215 4216 req->seq_id = cpu_to_le16(bnxt_get_hwrm_seq_id(bp, dst)); 4217 /* currently supports only one outstanding message */ 4218 if (intr_process) 4219 bp->hwrm_intr_seq_id = le16_to_cpu(req->seq_id); 4220 4221 if ((bp->fw_cap & BNXT_FW_CAP_SHORT_CMD) || 4222 msg_len > BNXT_HWRM_MAX_REQ_LEN) { 4223 void *short_cmd_req = bp->hwrm_short_cmd_req_addr; 4224 u16 max_msg_len; 4225 4226 /* Set boundary for maximum extended request length for short 4227 * cmd format. If passed up from device use the max supported 4228 * internal req length. 4229 */ 4230 max_msg_len = bp->hwrm_max_ext_req_len; 4231 4232 memcpy(short_cmd_req, req, msg_len); 4233 if (msg_len < max_msg_len) 4234 memset(short_cmd_req + msg_len, 0, 4235 max_msg_len - msg_len); 4236 4237 short_input.req_type = req->req_type; 4238 short_input.signature = 4239 cpu_to_le16(SHORT_REQ_SIGNATURE_SHORT_CMD); 4240 short_input.size = cpu_to_le16(msg_len); 4241 short_input.req_addr = 4242 cpu_to_le64(bp->hwrm_short_cmd_req_dma_addr); 4243 4244 data = (u32 *)&short_input; 4245 msg_len = sizeof(short_input); 4246 4247 /* Sync memory write before updating doorbell */ 4248 wmb(); 4249 4250 max_req_len = BNXT_HWRM_SHORT_REQ_LEN; 4251 } 4252 4253 /* Write request msg to hwrm channel */ 4254 __iowrite32_copy(bp->bar0 + bar_offset, data, msg_len / 4); 4255 4256 for (i = msg_len; i < max_req_len; i += 4) 4257 writel(0, bp->bar0 + bar_offset + i); 4258 4259 /* Ring channel doorbell */ 4260 writel(1, bp->bar0 + doorbell_offset); 4261 4262 if (!pci_is_enabled(bp->pdev)) 4263 return 0; 4264 4265 if (!timeout) 4266 timeout = DFLT_HWRM_CMD_TIMEOUT; 4267 /* convert timeout to usec */ 4268 timeout *= 1000; 4269 4270 i = 0; 4271 /* Short timeout for the first few iterations: 4272 * number of loops = number of loops for short timeout + 4273 * number of loops for standard timeout. 4274 */ 4275 tmo_count = HWRM_SHORT_TIMEOUT_COUNTER; 4276 timeout = timeout - HWRM_SHORT_MIN_TIMEOUT * HWRM_SHORT_TIMEOUT_COUNTER; 4277 tmo_count += DIV_ROUND_UP(timeout, HWRM_MIN_TIMEOUT); 4278 4279 if (intr_process) { 4280 u16 seq_id = bp->hwrm_intr_seq_id; 4281 4282 /* Wait until hwrm response cmpl interrupt is processed */ 4283 while (bp->hwrm_intr_seq_id != (u16)~seq_id && 4284 i++ < tmo_count) { 4285 /* Abort the wait for completion if the FW health 4286 * check has failed. 4287 */ 4288 if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state)) 4289 return -EBUSY; 4290 /* on first few passes, just barely sleep */ 4291 if (i < HWRM_SHORT_TIMEOUT_COUNTER) 4292 usleep_range(HWRM_SHORT_MIN_TIMEOUT, 4293 HWRM_SHORT_MAX_TIMEOUT); 4294 else 4295 usleep_range(HWRM_MIN_TIMEOUT, 4296 HWRM_MAX_TIMEOUT); 4297 } 4298 4299 if (bp->hwrm_intr_seq_id != (u16)~seq_id) { 4300 if (!silent) 4301 netdev_err(bp->dev, "Resp cmpl intr err msg: 0x%x\n", 4302 le16_to_cpu(req->req_type)); 4303 return -EBUSY; 4304 } 4305 len = le16_to_cpu(resp->resp_len); 4306 valid = ((u8 *)resp) + len - 1; 4307 } else { 4308 int j; 4309 4310 /* Check if response len is updated */ 4311 for (i = 0; i < tmo_count; i++) { 4312 /* Abort the wait for completion if the FW health 4313 * check has failed. 4314 */ 4315 if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state)) 4316 return -EBUSY; 4317 len = le16_to_cpu(resp->resp_len); 4318 if (len) 4319 break; 4320 /* on first few passes, just barely sleep */ 4321 if (i < HWRM_SHORT_TIMEOUT_COUNTER) 4322 usleep_range(HWRM_SHORT_MIN_TIMEOUT, 4323 HWRM_SHORT_MAX_TIMEOUT); 4324 else 4325 usleep_range(HWRM_MIN_TIMEOUT, 4326 HWRM_MAX_TIMEOUT); 4327 } 4328 4329 if (i >= tmo_count) { 4330 if (!silent) 4331 netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d\n", 4332 HWRM_TOTAL_TIMEOUT(i), 4333 le16_to_cpu(req->req_type), 4334 le16_to_cpu(req->seq_id), len); 4335 return -EBUSY; 4336 } 4337 4338 /* Last byte of resp contains valid bit */ 4339 valid = ((u8 *)resp) + len - 1; 4340 for (j = 0; j < HWRM_VALID_BIT_DELAY_USEC; j++) { 4341 /* make sure we read from updated DMA memory */ 4342 dma_rmb(); 4343 if (*valid) 4344 break; 4345 usleep_range(1, 5); 4346 } 4347 4348 if (j >= HWRM_VALID_BIT_DELAY_USEC) { 4349 if (!silent) 4350 netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d v:%d\n", 4351 HWRM_TOTAL_TIMEOUT(i), 4352 le16_to_cpu(req->req_type), 4353 le16_to_cpu(req->seq_id), len, 4354 *valid); 4355 return -EBUSY; 4356 } 4357 } 4358 4359 /* Zero valid bit for compatibility. Valid bit in an older spec 4360 * may become a new field in a newer spec. We must make sure that 4361 * a new field not implemented by old spec will read zero. 4362 */ 4363 *valid = 0; 4364 rc = le16_to_cpu(resp->error_code); 4365 if (rc && !silent) 4366 netdev_err(bp->dev, "hwrm req_type 0x%x seq id 0x%x error 0x%x\n", 4367 le16_to_cpu(resp->req_type), 4368 le16_to_cpu(resp->seq_id), rc); 4369 return bnxt_hwrm_to_stderr(rc); 4370 } 4371 4372 int _hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout) 4373 { 4374 return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, false); 4375 } 4376 4377 int _hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len, 4378 int timeout) 4379 { 4380 return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true); 4381 } 4382 4383 int hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout) 4384 { 4385 int rc; 4386 4387 mutex_lock(&bp->hwrm_cmd_lock); 4388 rc = _hwrm_send_message(bp, msg, msg_len, timeout); 4389 mutex_unlock(&bp->hwrm_cmd_lock); 4390 return rc; 4391 } 4392 4393 int hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len, 4394 int timeout) 4395 { 4396 int rc; 4397 4398 mutex_lock(&bp->hwrm_cmd_lock); 4399 rc = bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true); 4400 mutex_unlock(&bp->hwrm_cmd_lock); 4401 return rc; 4402 } 4403 4404 int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp, unsigned long *bmap, int bmap_size, 4405 bool async_only) 4406 { 4407 struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr; 4408 struct hwrm_func_drv_rgtr_input req = {0}; 4409 DECLARE_BITMAP(async_events_bmap, 256); 4410 u32 *events = (u32 *)async_events_bmap; 4411 u32 flags; 4412 int rc, i; 4413 4414 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1); 4415 4416 req.enables = 4417 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE | 4418 FUNC_DRV_RGTR_REQ_ENABLES_VER | 4419 FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD); 4420 4421 req.os_type = cpu_to_le16(FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX); 4422 flags = FUNC_DRV_RGTR_REQ_FLAGS_16BIT_VER_MODE; 4423 if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET) 4424 flags |= FUNC_DRV_RGTR_REQ_FLAGS_HOT_RESET_SUPPORT; 4425 if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY) 4426 flags |= FUNC_DRV_RGTR_REQ_FLAGS_ERROR_RECOVERY_SUPPORT | 4427 FUNC_DRV_RGTR_REQ_FLAGS_MASTER_SUPPORT; 4428 req.flags = cpu_to_le32(flags); 4429 req.ver_maj_8b = DRV_VER_MAJ; 4430 req.ver_min_8b = DRV_VER_MIN; 4431 req.ver_upd_8b = DRV_VER_UPD; 4432 req.ver_maj = cpu_to_le16(DRV_VER_MAJ); 4433 req.ver_min = cpu_to_le16(DRV_VER_MIN); 4434 req.ver_upd = cpu_to_le16(DRV_VER_UPD); 4435 4436 if (BNXT_PF(bp)) { 4437 u32 data[8]; 4438 int i; 4439 4440 memset(data, 0, sizeof(data)); 4441 for (i = 0; i < ARRAY_SIZE(bnxt_vf_req_snif); i++) { 4442 u16 cmd = bnxt_vf_req_snif[i]; 4443 unsigned int bit, idx; 4444 4445 idx = cmd / 32; 4446 bit = cmd % 32; 4447 data[idx] |= 1 << bit; 4448 } 4449 4450 for (i = 0; i < 8; i++) 4451 req.vf_req_fwd[i] = cpu_to_le32(data[i]); 4452 4453 req.enables |= 4454 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD); 4455 } 4456 4457 if (bp->fw_cap & BNXT_FW_CAP_OVS_64BIT_HANDLE) 4458 req.flags |= cpu_to_le32( 4459 FUNC_DRV_RGTR_REQ_FLAGS_FLOW_HANDLE_64BIT_MODE); 4460 4461 memset(async_events_bmap, 0, sizeof(async_events_bmap)); 4462 for (i = 0; i < ARRAY_SIZE(bnxt_async_events_arr); i++) { 4463 u16 event_id = bnxt_async_events_arr[i]; 4464 4465 if (event_id == ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY && 4466 !(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)) 4467 continue; 4468 __set_bit(bnxt_async_events_arr[i], async_events_bmap); 4469 } 4470 if (bmap && bmap_size) { 4471 for (i = 0; i < bmap_size; i++) { 4472 if (test_bit(i, bmap)) 4473 __set_bit(i, async_events_bmap); 4474 } 4475 } 4476 for (i = 0; i < 8; i++) 4477 req.async_event_fwd[i] |= cpu_to_le32(events[i]); 4478 4479 if (async_only) 4480 req.enables = 4481 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD); 4482 4483 mutex_lock(&bp->hwrm_cmd_lock); 4484 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4485 if (!rc) { 4486 set_bit(BNXT_STATE_DRV_REGISTERED, &bp->state); 4487 if (resp->flags & 4488 cpu_to_le32(FUNC_DRV_RGTR_RESP_FLAGS_IF_CHANGE_SUPPORTED)) 4489 bp->fw_cap |= BNXT_FW_CAP_IF_CHANGE; 4490 } 4491 mutex_unlock(&bp->hwrm_cmd_lock); 4492 return rc; 4493 } 4494 4495 static int bnxt_hwrm_func_drv_unrgtr(struct bnxt *bp) 4496 { 4497 struct hwrm_func_drv_unrgtr_input req = {0}; 4498 4499 if (!test_and_clear_bit(BNXT_STATE_DRV_REGISTERED, &bp->state)) 4500 return 0; 4501 4502 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_UNRGTR, -1, -1); 4503 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4504 } 4505 4506 static int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, u8 tunnel_type) 4507 { 4508 u32 rc = 0; 4509 struct hwrm_tunnel_dst_port_free_input req = {0}; 4510 4511 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_FREE, -1, -1); 4512 req.tunnel_type = tunnel_type; 4513 4514 switch (tunnel_type) { 4515 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN: 4516 req.tunnel_dst_port_id = bp->vxlan_fw_dst_port_id; 4517 break; 4518 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE: 4519 req.tunnel_dst_port_id = bp->nge_fw_dst_port_id; 4520 break; 4521 default: 4522 break; 4523 } 4524 4525 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4526 if (rc) 4527 netdev_err(bp->dev, "hwrm_tunnel_dst_port_free failed. rc:%d\n", 4528 rc); 4529 return rc; 4530 } 4531 4532 static int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, __be16 port, 4533 u8 tunnel_type) 4534 { 4535 u32 rc = 0; 4536 struct hwrm_tunnel_dst_port_alloc_input req = {0}; 4537 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr; 4538 4539 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_ALLOC, -1, -1); 4540 4541 req.tunnel_type = tunnel_type; 4542 req.tunnel_dst_port_val = port; 4543 4544 mutex_lock(&bp->hwrm_cmd_lock); 4545 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4546 if (rc) { 4547 netdev_err(bp->dev, "hwrm_tunnel_dst_port_alloc failed. rc:%d\n", 4548 rc); 4549 goto err_out; 4550 } 4551 4552 switch (tunnel_type) { 4553 case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN: 4554 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id; 4555 break; 4556 case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE: 4557 bp->nge_fw_dst_port_id = resp->tunnel_dst_port_id; 4558 break; 4559 default: 4560 break; 4561 } 4562 4563 err_out: 4564 mutex_unlock(&bp->hwrm_cmd_lock); 4565 return rc; 4566 } 4567 4568 static int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp, u16 vnic_id) 4569 { 4570 struct hwrm_cfa_l2_set_rx_mask_input req = {0}; 4571 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 4572 4573 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_SET_RX_MASK, -1, -1); 4574 req.vnic_id = cpu_to_le32(vnic->fw_vnic_id); 4575 4576 req.num_mc_entries = cpu_to_le32(vnic->mc_list_count); 4577 req.mc_tbl_addr = cpu_to_le64(vnic->mc_list_mapping); 4578 req.mask = cpu_to_le32(vnic->rx_mask); 4579 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4580 } 4581 4582 #ifdef CONFIG_RFS_ACCEL 4583 static int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt *bp, 4584 struct bnxt_ntuple_filter *fltr) 4585 { 4586 struct hwrm_cfa_ntuple_filter_free_input req = {0}; 4587 4588 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_FREE, -1, -1); 4589 req.ntuple_filter_id = fltr->filter_id; 4590 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4591 } 4592 4593 #define BNXT_NTP_FLTR_FLAGS \ 4594 (CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID | \ 4595 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE | \ 4596 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR | \ 4597 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE | \ 4598 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR | \ 4599 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK | \ 4600 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR | \ 4601 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK | \ 4602 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL | \ 4603 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT | \ 4604 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK | \ 4605 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT | \ 4606 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK | \ 4607 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID) 4608 4609 #define BNXT_NTP_TUNNEL_FLTR_FLAG \ 4610 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 4611 4612 static int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt *bp, 4613 struct bnxt_ntuple_filter *fltr) 4614 { 4615 struct hwrm_cfa_ntuple_filter_alloc_input req = {0}; 4616 struct hwrm_cfa_ntuple_filter_alloc_output *resp; 4617 struct flow_keys *keys = &fltr->fkeys; 4618 struct bnxt_vnic_info *vnic; 4619 u32 flags = 0; 4620 int rc = 0; 4621 4622 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_ALLOC, -1, -1); 4623 req.l2_filter_id = bp->vnic_info[0].fw_l2_filter_id[fltr->l2_fltr_idx]; 4624 4625 if (bp->fw_cap & BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V2) { 4626 flags = CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DEST_RFS_RING_IDX; 4627 req.dst_id = cpu_to_le16(fltr->rxq); 4628 } else { 4629 vnic = &bp->vnic_info[fltr->rxq + 1]; 4630 req.dst_id = cpu_to_le16(vnic->fw_vnic_id); 4631 } 4632 req.flags = cpu_to_le32(flags); 4633 req.enables = cpu_to_le32(BNXT_NTP_FLTR_FLAGS); 4634 4635 req.ethertype = htons(ETH_P_IP); 4636 memcpy(req.src_macaddr, fltr->src_mac_addr, ETH_ALEN); 4637 req.ip_addr_type = CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4; 4638 req.ip_protocol = keys->basic.ip_proto; 4639 4640 if (keys->basic.n_proto == htons(ETH_P_IPV6)) { 4641 int i; 4642 4643 req.ethertype = htons(ETH_P_IPV6); 4644 req.ip_addr_type = 4645 CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6; 4646 *(struct in6_addr *)&req.src_ipaddr[0] = 4647 keys->addrs.v6addrs.src; 4648 *(struct in6_addr *)&req.dst_ipaddr[0] = 4649 keys->addrs.v6addrs.dst; 4650 for (i = 0; i < 4; i++) { 4651 req.src_ipaddr_mask[i] = cpu_to_be32(0xffffffff); 4652 req.dst_ipaddr_mask[i] = cpu_to_be32(0xffffffff); 4653 } 4654 } else { 4655 req.src_ipaddr[0] = keys->addrs.v4addrs.src; 4656 req.src_ipaddr_mask[0] = cpu_to_be32(0xffffffff); 4657 req.dst_ipaddr[0] = keys->addrs.v4addrs.dst; 4658 req.dst_ipaddr_mask[0] = cpu_to_be32(0xffffffff); 4659 } 4660 if (keys->control.flags & FLOW_DIS_ENCAPSULATION) { 4661 req.enables |= cpu_to_le32(BNXT_NTP_TUNNEL_FLTR_FLAG); 4662 req.tunnel_type = 4663 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL; 4664 } 4665 4666 req.src_port = keys->ports.src; 4667 req.src_port_mask = cpu_to_be16(0xffff); 4668 req.dst_port = keys->ports.dst; 4669 req.dst_port_mask = cpu_to_be16(0xffff); 4670 4671 mutex_lock(&bp->hwrm_cmd_lock); 4672 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4673 if (!rc) { 4674 resp = bnxt_get_hwrm_resp_addr(bp, &req); 4675 fltr->filter_id = resp->ntuple_filter_id; 4676 } 4677 mutex_unlock(&bp->hwrm_cmd_lock); 4678 return rc; 4679 } 4680 #endif 4681 4682 static int bnxt_hwrm_set_vnic_filter(struct bnxt *bp, u16 vnic_id, u16 idx, 4683 u8 *mac_addr) 4684 { 4685 u32 rc = 0; 4686 struct hwrm_cfa_l2_filter_alloc_input req = {0}; 4687 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr; 4688 4689 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_ALLOC, -1, -1); 4690 req.flags = cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX); 4691 if (!BNXT_CHIP_TYPE_NITRO_A0(bp)) 4692 req.flags |= 4693 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST); 4694 req.dst_id = cpu_to_le16(bp->vnic_info[vnic_id].fw_vnic_id); 4695 req.enables = 4696 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR | 4697 CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID | 4698 CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK); 4699 memcpy(req.l2_addr, mac_addr, ETH_ALEN); 4700 req.l2_addr_mask[0] = 0xff; 4701 req.l2_addr_mask[1] = 0xff; 4702 req.l2_addr_mask[2] = 0xff; 4703 req.l2_addr_mask[3] = 0xff; 4704 req.l2_addr_mask[4] = 0xff; 4705 req.l2_addr_mask[5] = 0xff; 4706 4707 mutex_lock(&bp->hwrm_cmd_lock); 4708 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4709 if (!rc) 4710 bp->vnic_info[vnic_id].fw_l2_filter_id[idx] = 4711 resp->l2_filter_id; 4712 mutex_unlock(&bp->hwrm_cmd_lock); 4713 return rc; 4714 } 4715 4716 static int bnxt_hwrm_clear_vnic_filter(struct bnxt *bp) 4717 { 4718 u16 i, j, num_of_vnics = 1; /* only vnic 0 supported */ 4719 int rc = 0; 4720 4721 /* Any associated ntuple filters will also be cleared by firmware. */ 4722 mutex_lock(&bp->hwrm_cmd_lock); 4723 for (i = 0; i < num_of_vnics; i++) { 4724 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 4725 4726 for (j = 0; j < vnic->uc_filter_count; j++) { 4727 struct hwrm_cfa_l2_filter_free_input req = {0}; 4728 4729 bnxt_hwrm_cmd_hdr_init(bp, &req, 4730 HWRM_CFA_L2_FILTER_FREE, -1, -1); 4731 4732 req.l2_filter_id = vnic->fw_l2_filter_id[j]; 4733 4734 rc = _hwrm_send_message(bp, &req, sizeof(req), 4735 HWRM_CMD_TIMEOUT); 4736 } 4737 vnic->uc_filter_count = 0; 4738 } 4739 mutex_unlock(&bp->hwrm_cmd_lock); 4740 4741 return rc; 4742 } 4743 4744 static int bnxt_hwrm_vnic_set_tpa(struct bnxt *bp, u16 vnic_id, u32 tpa_flags) 4745 { 4746 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 4747 u16 max_aggs = VNIC_TPA_CFG_REQ_MAX_AGGS_MAX; 4748 struct hwrm_vnic_tpa_cfg_input req = {0}; 4749 4750 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) 4751 return 0; 4752 4753 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_TPA_CFG, -1, -1); 4754 4755 if (tpa_flags) { 4756 u16 mss = bp->dev->mtu - 40; 4757 u32 nsegs, n, segs = 0, flags; 4758 4759 flags = VNIC_TPA_CFG_REQ_FLAGS_TPA | 4760 VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA | 4761 VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE | 4762 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN | 4763 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ; 4764 if (tpa_flags & BNXT_FLAG_GRO) 4765 flags |= VNIC_TPA_CFG_REQ_FLAGS_GRO; 4766 4767 req.flags = cpu_to_le32(flags); 4768 4769 req.enables = 4770 cpu_to_le32(VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS | 4771 VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS | 4772 VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN); 4773 4774 /* Number of segs are log2 units, and first packet is not 4775 * included as part of this units. 4776 */ 4777 if (mss <= BNXT_RX_PAGE_SIZE) { 4778 n = BNXT_RX_PAGE_SIZE / mss; 4779 nsegs = (MAX_SKB_FRAGS - 1) * n; 4780 } else { 4781 n = mss / BNXT_RX_PAGE_SIZE; 4782 if (mss & (BNXT_RX_PAGE_SIZE - 1)) 4783 n++; 4784 nsegs = (MAX_SKB_FRAGS - n) / n; 4785 } 4786 4787 if (bp->flags & BNXT_FLAG_CHIP_P5) { 4788 segs = MAX_TPA_SEGS_P5; 4789 max_aggs = bp->max_tpa; 4790 } else { 4791 segs = ilog2(nsegs); 4792 } 4793 req.max_agg_segs = cpu_to_le16(segs); 4794 req.max_aggs = cpu_to_le16(max_aggs); 4795 4796 req.min_agg_len = cpu_to_le32(512); 4797 } 4798 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id); 4799 4800 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4801 } 4802 4803 static u16 bnxt_cp_ring_from_grp(struct bnxt *bp, struct bnxt_ring_struct *ring) 4804 { 4805 struct bnxt_ring_grp_info *grp_info; 4806 4807 grp_info = &bp->grp_info[ring->grp_idx]; 4808 return grp_info->cp_fw_ring_id; 4809 } 4810 4811 static u16 bnxt_cp_ring_for_rx(struct bnxt *bp, struct bnxt_rx_ring_info *rxr) 4812 { 4813 if (bp->flags & BNXT_FLAG_CHIP_P5) { 4814 struct bnxt_napi *bnapi = rxr->bnapi; 4815 struct bnxt_cp_ring_info *cpr; 4816 4817 cpr = bnapi->cp_ring.cp_ring_arr[BNXT_RX_HDL]; 4818 return cpr->cp_ring_struct.fw_ring_id; 4819 } else { 4820 return bnxt_cp_ring_from_grp(bp, &rxr->rx_ring_struct); 4821 } 4822 } 4823 4824 static u16 bnxt_cp_ring_for_tx(struct bnxt *bp, struct bnxt_tx_ring_info *txr) 4825 { 4826 if (bp->flags & BNXT_FLAG_CHIP_P5) { 4827 struct bnxt_napi *bnapi = txr->bnapi; 4828 struct bnxt_cp_ring_info *cpr; 4829 4830 cpr = bnapi->cp_ring.cp_ring_arr[BNXT_TX_HDL]; 4831 return cpr->cp_ring_struct.fw_ring_id; 4832 } else { 4833 return bnxt_cp_ring_from_grp(bp, &txr->tx_ring_struct); 4834 } 4835 } 4836 4837 static int bnxt_hwrm_vnic_set_rss(struct bnxt *bp, u16 vnic_id, bool set_rss) 4838 { 4839 u32 i, j, max_rings; 4840 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 4841 struct hwrm_vnic_rss_cfg_input req = {0}; 4842 4843 if ((bp->flags & BNXT_FLAG_CHIP_P5) || 4844 vnic->fw_rss_cos_lb_ctx[0] == INVALID_HW_RING_ID) 4845 return 0; 4846 4847 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1); 4848 if (set_rss) { 4849 req.hash_type = cpu_to_le32(bp->rss_hash_cfg); 4850 req.hash_mode_flags = VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT; 4851 if (vnic->flags & BNXT_VNIC_RSS_FLAG) { 4852 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 4853 max_rings = bp->rx_nr_rings - 1; 4854 else 4855 max_rings = bp->rx_nr_rings; 4856 } else { 4857 max_rings = 1; 4858 } 4859 4860 /* Fill the RSS indirection table with ring group ids */ 4861 for (i = 0, j = 0; i < HW_HASH_INDEX_SIZE; i++, j++) { 4862 if (j == max_rings) 4863 j = 0; 4864 vnic->rss_table[i] = cpu_to_le16(vnic->fw_grp_ids[j]); 4865 } 4866 4867 req.ring_grp_tbl_addr = cpu_to_le64(vnic->rss_table_dma_addr); 4868 req.hash_key_tbl_addr = 4869 cpu_to_le64(vnic->rss_hash_key_dma_addr); 4870 } 4871 req.rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]); 4872 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4873 } 4874 4875 static int bnxt_hwrm_vnic_set_rss_p5(struct bnxt *bp, u16 vnic_id, bool set_rss) 4876 { 4877 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 4878 u32 i, j, k, nr_ctxs, max_rings = bp->rx_nr_rings; 4879 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[0]; 4880 struct hwrm_vnic_rss_cfg_input req = {0}; 4881 4882 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1); 4883 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id); 4884 if (!set_rss) { 4885 hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4886 return 0; 4887 } 4888 req.hash_type = cpu_to_le32(bp->rss_hash_cfg); 4889 req.hash_mode_flags = VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT; 4890 req.ring_grp_tbl_addr = cpu_to_le64(vnic->rss_table_dma_addr); 4891 req.hash_key_tbl_addr = cpu_to_le64(vnic->rss_hash_key_dma_addr); 4892 nr_ctxs = DIV_ROUND_UP(bp->rx_nr_rings, 64); 4893 for (i = 0, k = 0; i < nr_ctxs; i++) { 4894 __le16 *ring_tbl = vnic->rss_table; 4895 int rc; 4896 4897 req.ring_table_pair_index = i; 4898 req.rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[i]); 4899 for (j = 0; j < 64; j++) { 4900 u16 ring_id; 4901 4902 ring_id = rxr->rx_ring_struct.fw_ring_id; 4903 *ring_tbl++ = cpu_to_le16(ring_id); 4904 ring_id = bnxt_cp_ring_for_rx(bp, rxr); 4905 *ring_tbl++ = cpu_to_le16(ring_id); 4906 rxr++; 4907 k++; 4908 if (k == max_rings) { 4909 k = 0; 4910 rxr = &bp->rx_ring[0]; 4911 } 4912 } 4913 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4914 if (rc) 4915 return rc; 4916 } 4917 return 0; 4918 } 4919 4920 static int bnxt_hwrm_vnic_set_hds(struct bnxt *bp, u16 vnic_id) 4921 { 4922 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 4923 struct hwrm_vnic_plcmodes_cfg_input req = {0}; 4924 4925 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_PLCMODES_CFG, -1, -1); 4926 req.flags = cpu_to_le32(VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT | 4927 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 | 4928 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6); 4929 req.enables = 4930 cpu_to_le32(VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID | 4931 VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID); 4932 /* thresholds not implemented in firmware yet */ 4933 req.jumbo_thresh = cpu_to_le16(bp->rx_copy_thresh); 4934 req.hds_threshold = cpu_to_le16(bp->rx_copy_thresh); 4935 req.vnic_id = cpu_to_le32(vnic->fw_vnic_id); 4936 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4937 } 4938 4939 static void bnxt_hwrm_vnic_ctx_free_one(struct bnxt *bp, u16 vnic_id, 4940 u16 ctx_idx) 4941 { 4942 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {0}; 4943 4944 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, -1, -1); 4945 req.rss_cos_lb_ctx_id = 4946 cpu_to_le16(bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx]); 4947 4948 hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4949 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] = INVALID_HW_RING_ID; 4950 } 4951 4952 static void bnxt_hwrm_vnic_ctx_free(struct bnxt *bp) 4953 { 4954 int i, j; 4955 4956 for (i = 0; i < bp->nr_vnics; i++) { 4957 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 4958 4959 for (j = 0; j < BNXT_MAX_CTX_PER_VNIC; j++) { 4960 if (vnic->fw_rss_cos_lb_ctx[j] != INVALID_HW_RING_ID) 4961 bnxt_hwrm_vnic_ctx_free_one(bp, i, j); 4962 } 4963 } 4964 bp->rsscos_nr_ctxs = 0; 4965 } 4966 4967 static int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, u16 vnic_id, u16 ctx_idx) 4968 { 4969 int rc; 4970 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {0}; 4971 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp = 4972 bp->hwrm_cmd_resp_addr; 4973 4974 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, -1, 4975 -1); 4976 4977 mutex_lock(&bp->hwrm_cmd_lock); 4978 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4979 if (!rc) 4980 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] = 4981 le16_to_cpu(resp->rss_cos_lb_ctx_id); 4982 mutex_unlock(&bp->hwrm_cmd_lock); 4983 4984 return rc; 4985 } 4986 4987 static u32 bnxt_get_roce_vnic_mode(struct bnxt *bp) 4988 { 4989 if (bp->flags & BNXT_FLAG_ROCE_MIRROR_CAP) 4990 return VNIC_CFG_REQ_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE; 4991 return VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE; 4992 } 4993 4994 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id) 4995 { 4996 unsigned int ring = 0, grp_idx; 4997 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 4998 struct hwrm_vnic_cfg_input req = {0}; 4999 u16 def_vlan = 0; 5000 5001 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_CFG, -1, -1); 5002 5003 if (bp->flags & BNXT_FLAG_CHIP_P5) { 5004 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[0]; 5005 5006 req.default_rx_ring_id = 5007 cpu_to_le16(rxr->rx_ring_struct.fw_ring_id); 5008 req.default_cmpl_ring_id = 5009 cpu_to_le16(bnxt_cp_ring_for_rx(bp, rxr)); 5010 req.enables = 5011 cpu_to_le32(VNIC_CFG_REQ_ENABLES_DEFAULT_RX_RING_ID | 5012 VNIC_CFG_REQ_ENABLES_DEFAULT_CMPL_RING_ID); 5013 goto vnic_mru; 5014 } 5015 req.enables = cpu_to_le32(VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP); 5016 /* Only RSS support for now TBD: COS & LB */ 5017 if (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID) { 5018 req.rss_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]); 5019 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE | 5020 VNIC_CFG_REQ_ENABLES_MRU); 5021 } else if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG) { 5022 req.rss_rule = 5023 cpu_to_le16(bp->vnic_info[0].fw_rss_cos_lb_ctx[0]); 5024 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE | 5025 VNIC_CFG_REQ_ENABLES_MRU); 5026 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE); 5027 } else { 5028 req.rss_rule = cpu_to_le16(0xffff); 5029 } 5030 5031 if (BNXT_CHIP_TYPE_NITRO_A0(bp) && 5032 (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID)) { 5033 req.cos_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[1]); 5034 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_COS_RULE); 5035 } else { 5036 req.cos_rule = cpu_to_le16(0xffff); 5037 } 5038 5039 if (vnic->flags & BNXT_VNIC_RSS_FLAG) 5040 ring = 0; 5041 else if (vnic->flags & BNXT_VNIC_RFS_FLAG) 5042 ring = vnic_id - 1; 5043 else if ((vnic_id == 1) && BNXT_CHIP_TYPE_NITRO_A0(bp)) 5044 ring = bp->rx_nr_rings - 1; 5045 5046 grp_idx = bp->rx_ring[ring].bnapi->index; 5047 req.dflt_ring_grp = cpu_to_le16(bp->grp_info[grp_idx].fw_grp_id); 5048 req.lb_rule = cpu_to_le16(0xffff); 5049 vnic_mru: 5050 req.mru = cpu_to_le16(bp->dev->mtu + ETH_HLEN + VLAN_HLEN); 5051 5052 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id); 5053 #ifdef CONFIG_BNXT_SRIOV 5054 if (BNXT_VF(bp)) 5055 def_vlan = bp->vf.vlan; 5056 #endif 5057 if ((bp->flags & BNXT_FLAG_STRIP_VLAN) || def_vlan) 5058 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE); 5059 if (!vnic_id && bnxt_ulp_registered(bp->edev, BNXT_ROCE_ULP)) 5060 req.flags |= cpu_to_le32(bnxt_get_roce_vnic_mode(bp)); 5061 5062 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5063 } 5064 5065 static void bnxt_hwrm_vnic_free_one(struct bnxt *bp, u16 vnic_id) 5066 { 5067 if (bp->vnic_info[vnic_id].fw_vnic_id != INVALID_HW_RING_ID) { 5068 struct hwrm_vnic_free_input req = {0}; 5069 5070 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_FREE, -1, -1); 5071 req.vnic_id = 5072 cpu_to_le32(bp->vnic_info[vnic_id].fw_vnic_id); 5073 5074 hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5075 bp->vnic_info[vnic_id].fw_vnic_id = INVALID_HW_RING_ID; 5076 } 5077 } 5078 5079 static void bnxt_hwrm_vnic_free(struct bnxt *bp) 5080 { 5081 u16 i; 5082 5083 for (i = 0; i < bp->nr_vnics; i++) 5084 bnxt_hwrm_vnic_free_one(bp, i); 5085 } 5086 5087 static int bnxt_hwrm_vnic_alloc(struct bnxt *bp, u16 vnic_id, 5088 unsigned int start_rx_ring_idx, 5089 unsigned int nr_rings) 5090 { 5091 int rc = 0; 5092 unsigned int i, j, grp_idx, end_idx = start_rx_ring_idx + nr_rings; 5093 struct hwrm_vnic_alloc_input req = {0}; 5094 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr; 5095 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 5096 5097 if (bp->flags & BNXT_FLAG_CHIP_P5) 5098 goto vnic_no_ring_grps; 5099 5100 /* map ring groups to this vnic */ 5101 for (i = start_rx_ring_idx, j = 0; i < end_idx; i++, j++) { 5102 grp_idx = bp->rx_ring[i].bnapi->index; 5103 if (bp->grp_info[grp_idx].fw_grp_id == INVALID_HW_RING_ID) { 5104 netdev_err(bp->dev, "Not enough ring groups avail:%x req:%x\n", 5105 j, nr_rings); 5106 break; 5107 } 5108 vnic->fw_grp_ids[j] = bp->grp_info[grp_idx].fw_grp_id; 5109 } 5110 5111 vnic_no_ring_grps: 5112 for (i = 0; i < BNXT_MAX_CTX_PER_VNIC; i++) 5113 vnic->fw_rss_cos_lb_ctx[i] = INVALID_HW_RING_ID; 5114 if (vnic_id == 0) 5115 req.flags = cpu_to_le32(VNIC_ALLOC_REQ_FLAGS_DEFAULT); 5116 5117 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_ALLOC, -1, -1); 5118 5119 mutex_lock(&bp->hwrm_cmd_lock); 5120 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5121 if (!rc) 5122 vnic->fw_vnic_id = le32_to_cpu(resp->vnic_id); 5123 mutex_unlock(&bp->hwrm_cmd_lock); 5124 return rc; 5125 } 5126 5127 static int bnxt_hwrm_vnic_qcaps(struct bnxt *bp) 5128 { 5129 struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr; 5130 struct hwrm_vnic_qcaps_input req = {0}; 5131 int rc; 5132 5133 bp->hw_ring_stats_size = sizeof(struct ctx_hw_stats); 5134 bp->flags &= ~(BNXT_FLAG_NEW_RSS_CAP | BNXT_FLAG_ROCE_MIRROR_CAP); 5135 if (bp->hwrm_spec_code < 0x10600) 5136 return 0; 5137 5138 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_QCAPS, -1, -1); 5139 mutex_lock(&bp->hwrm_cmd_lock); 5140 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5141 if (!rc) { 5142 u32 flags = le32_to_cpu(resp->flags); 5143 5144 if (!(bp->flags & BNXT_FLAG_CHIP_P5) && 5145 (flags & VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP)) 5146 bp->flags |= BNXT_FLAG_NEW_RSS_CAP; 5147 if (flags & 5148 VNIC_QCAPS_RESP_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP) 5149 bp->flags |= BNXT_FLAG_ROCE_MIRROR_CAP; 5150 bp->max_tpa_v2 = le16_to_cpu(resp->max_aggs_supported); 5151 if (bp->max_tpa_v2) 5152 bp->hw_ring_stats_size = 5153 sizeof(struct ctx_hw_stats_ext); 5154 } 5155 mutex_unlock(&bp->hwrm_cmd_lock); 5156 return rc; 5157 } 5158 5159 static int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp) 5160 { 5161 u16 i; 5162 u32 rc = 0; 5163 5164 if (bp->flags & BNXT_FLAG_CHIP_P5) 5165 return 0; 5166 5167 mutex_lock(&bp->hwrm_cmd_lock); 5168 for (i = 0; i < bp->rx_nr_rings; i++) { 5169 struct hwrm_ring_grp_alloc_input req = {0}; 5170 struct hwrm_ring_grp_alloc_output *resp = 5171 bp->hwrm_cmd_resp_addr; 5172 unsigned int grp_idx = bp->rx_ring[i].bnapi->index; 5173 5174 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_ALLOC, -1, -1); 5175 5176 req.cr = cpu_to_le16(bp->grp_info[grp_idx].cp_fw_ring_id); 5177 req.rr = cpu_to_le16(bp->grp_info[grp_idx].rx_fw_ring_id); 5178 req.ar = cpu_to_le16(bp->grp_info[grp_idx].agg_fw_ring_id); 5179 req.sc = cpu_to_le16(bp->grp_info[grp_idx].fw_stats_ctx); 5180 5181 rc = _hwrm_send_message(bp, &req, sizeof(req), 5182 HWRM_CMD_TIMEOUT); 5183 if (rc) 5184 break; 5185 5186 bp->grp_info[grp_idx].fw_grp_id = 5187 le32_to_cpu(resp->ring_group_id); 5188 } 5189 mutex_unlock(&bp->hwrm_cmd_lock); 5190 return rc; 5191 } 5192 5193 static void bnxt_hwrm_ring_grp_free(struct bnxt *bp) 5194 { 5195 u16 i; 5196 struct hwrm_ring_grp_free_input req = {0}; 5197 5198 if (!bp->grp_info || (bp->flags & BNXT_FLAG_CHIP_P5)) 5199 return; 5200 5201 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_FREE, -1, -1); 5202 5203 mutex_lock(&bp->hwrm_cmd_lock); 5204 for (i = 0; i < bp->cp_nr_rings; i++) { 5205 if (bp->grp_info[i].fw_grp_id == INVALID_HW_RING_ID) 5206 continue; 5207 req.ring_group_id = 5208 cpu_to_le32(bp->grp_info[i].fw_grp_id); 5209 5210 _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5211 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID; 5212 } 5213 mutex_unlock(&bp->hwrm_cmd_lock); 5214 } 5215 5216 static int hwrm_ring_alloc_send_msg(struct bnxt *bp, 5217 struct bnxt_ring_struct *ring, 5218 u32 ring_type, u32 map_index) 5219 { 5220 int rc = 0, err = 0; 5221 struct hwrm_ring_alloc_input req = {0}; 5222 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr; 5223 struct bnxt_ring_mem_info *rmem = &ring->ring_mem; 5224 struct bnxt_ring_grp_info *grp_info; 5225 u16 ring_id; 5226 5227 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_ALLOC, -1, -1); 5228 5229 req.enables = 0; 5230 if (rmem->nr_pages > 1) { 5231 req.page_tbl_addr = cpu_to_le64(rmem->pg_tbl_map); 5232 /* Page size is in log2 units */ 5233 req.page_size = BNXT_PAGE_SHIFT; 5234 req.page_tbl_depth = 1; 5235 } else { 5236 req.page_tbl_addr = cpu_to_le64(rmem->dma_arr[0]); 5237 } 5238 req.fbo = 0; 5239 /* Association of ring index with doorbell index and MSIX number */ 5240 req.logical_id = cpu_to_le16(map_index); 5241 5242 switch (ring_type) { 5243 case HWRM_RING_ALLOC_TX: { 5244 struct bnxt_tx_ring_info *txr; 5245 5246 txr = container_of(ring, struct bnxt_tx_ring_info, 5247 tx_ring_struct); 5248 req.ring_type = RING_ALLOC_REQ_RING_TYPE_TX; 5249 /* Association of transmit ring with completion ring */ 5250 grp_info = &bp->grp_info[ring->grp_idx]; 5251 req.cmpl_ring_id = cpu_to_le16(bnxt_cp_ring_for_tx(bp, txr)); 5252 req.length = cpu_to_le32(bp->tx_ring_mask + 1); 5253 req.stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx); 5254 req.queue_id = cpu_to_le16(ring->queue_id); 5255 break; 5256 } 5257 case HWRM_RING_ALLOC_RX: 5258 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX; 5259 req.length = cpu_to_le32(bp->rx_ring_mask + 1); 5260 if (bp->flags & BNXT_FLAG_CHIP_P5) { 5261 u16 flags = 0; 5262 5263 /* Association of rx ring with stats context */ 5264 grp_info = &bp->grp_info[ring->grp_idx]; 5265 req.rx_buf_size = cpu_to_le16(bp->rx_buf_use_size); 5266 req.stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx); 5267 req.enables |= cpu_to_le32( 5268 RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID); 5269 if (NET_IP_ALIGN == 2) 5270 flags = RING_ALLOC_REQ_FLAGS_RX_SOP_PAD; 5271 req.flags = cpu_to_le16(flags); 5272 } 5273 break; 5274 case HWRM_RING_ALLOC_AGG: 5275 if (bp->flags & BNXT_FLAG_CHIP_P5) { 5276 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX_AGG; 5277 /* Association of agg ring with rx ring */ 5278 grp_info = &bp->grp_info[ring->grp_idx]; 5279 req.rx_ring_id = cpu_to_le16(grp_info->rx_fw_ring_id); 5280 req.rx_buf_size = cpu_to_le16(BNXT_RX_PAGE_SIZE); 5281 req.stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx); 5282 req.enables |= cpu_to_le32( 5283 RING_ALLOC_REQ_ENABLES_RX_RING_ID_VALID | 5284 RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID); 5285 } else { 5286 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX; 5287 } 5288 req.length = cpu_to_le32(bp->rx_agg_ring_mask + 1); 5289 break; 5290 case HWRM_RING_ALLOC_CMPL: 5291 req.ring_type = RING_ALLOC_REQ_RING_TYPE_L2_CMPL; 5292 req.length = cpu_to_le32(bp->cp_ring_mask + 1); 5293 if (bp->flags & BNXT_FLAG_CHIP_P5) { 5294 /* Association of cp ring with nq */ 5295 grp_info = &bp->grp_info[map_index]; 5296 req.nq_ring_id = cpu_to_le16(grp_info->cp_fw_ring_id); 5297 req.cq_handle = cpu_to_le64(ring->handle); 5298 req.enables |= cpu_to_le32( 5299 RING_ALLOC_REQ_ENABLES_NQ_RING_ID_VALID); 5300 } else if (bp->flags & BNXT_FLAG_USING_MSIX) { 5301 req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX; 5302 } 5303 break; 5304 case HWRM_RING_ALLOC_NQ: 5305 req.ring_type = RING_ALLOC_REQ_RING_TYPE_NQ; 5306 req.length = cpu_to_le32(bp->cp_ring_mask + 1); 5307 if (bp->flags & BNXT_FLAG_USING_MSIX) 5308 req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX; 5309 break; 5310 default: 5311 netdev_err(bp->dev, "hwrm alloc invalid ring type %d\n", 5312 ring_type); 5313 return -1; 5314 } 5315 5316 mutex_lock(&bp->hwrm_cmd_lock); 5317 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5318 err = le16_to_cpu(resp->error_code); 5319 ring_id = le16_to_cpu(resp->ring_id); 5320 mutex_unlock(&bp->hwrm_cmd_lock); 5321 5322 if (rc || err) { 5323 netdev_err(bp->dev, "hwrm_ring_alloc type %d failed. rc:%x err:%x\n", 5324 ring_type, rc, err); 5325 return -EIO; 5326 } 5327 ring->fw_ring_id = ring_id; 5328 return rc; 5329 } 5330 5331 static int bnxt_hwrm_set_async_event_cr(struct bnxt *bp, int idx) 5332 { 5333 int rc; 5334 5335 if (BNXT_PF(bp)) { 5336 struct hwrm_func_cfg_input req = {0}; 5337 5338 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1); 5339 req.fid = cpu_to_le16(0xffff); 5340 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR); 5341 req.async_event_cr = cpu_to_le16(idx); 5342 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5343 } else { 5344 struct hwrm_func_vf_cfg_input req = {0}; 5345 5346 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_VF_CFG, -1, -1); 5347 req.enables = 5348 cpu_to_le32(FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR); 5349 req.async_event_cr = cpu_to_le16(idx); 5350 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5351 } 5352 return rc; 5353 } 5354 5355 static void bnxt_set_db(struct bnxt *bp, struct bnxt_db_info *db, u32 ring_type, 5356 u32 map_idx, u32 xid) 5357 { 5358 if (bp->flags & BNXT_FLAG_CHIP_P5) { 5359 if (BNXT_PF(bp)) 5360 db->doorbell = bp->bar1 + DB_PF_OFFSET_P5; 5361 else 5362 db->doorbell = bp->bar1 + DB_VF_OFFSET_P5; 5363 switch (ring_type) { 5364 case HWRM_RING_ALLOC_TX: 5365 db->db_key64 = DBR_PATH_L2 | DBR_TYPE_SQ; 5366 break; 5367 case HWRM_RING_ALLOC_RX: 5368 case HWRM_RING_ALLOC_AGG: 5369 db->db_key64 = DBR_PATH_L2 | DBR_TYPE_SRQ; 5370 break; 5371 case HWRM_RING_ALLOC_CMPL: 5372 db->db_key64 = DBR_PATH_L2; 5373 break; 5374 case HWRM_RING_ALLOC_NQ: 5375 db->db_key64 = DBR_PATH_L2; 5376 break; 5377 } 5378 db->db_key64 |= (u64)xid << DBR_XID_SFT; 5379 } else { 5380 db->doorbell = bp->bar1 + map_idx * 0x80; 5381 switch (ring_type) { 5382 case HWRM_RING_ALLOC_TX: 5383 db->db_key32 = DB_KEY_TX; 5384 break; 5385 case HWRM_RING_ALLOC_RX: 5386 case HWRM_RING_ALLOC_AGG: 5387 db->db_key32 = DB_KEY_RX; 5388 break; 5389 case HWRM_RING_ALLOC_CMPL: 5390 db->db_key32 = DB_KEY_CP; 5391 break; 5392 } 5393 } 5394 } 5395 5396 static int bnxt_hwrm_ring_alloc(struct bnxt *bp) 5397 { 5398 bool agg_rings = !!(bp->flags & BNXT_FLAG_AGG_RINGS); 5399 int i, rc = 0; 5400 u32 type; 5401 5402 if (bp->flags & BNXT_FLAG_CHIP_P5) 5403 type = HWRM_RING_ALLOC_NQ; 5404 else 5405 type = HWRM_RING_ALLOC_CMPL; 5406 for (i = 0; i < bp->cp_nr_rings; i++) { 5407 struct bnxt_napi *bnapi = bp->bnapi[i]; 5408 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 5409 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct; 5410 u32 map_idx = ring->map_idx; 5411 unsigned int vector; 5412 5413 vector = bp->irq_tbl[map_idx].vector; 5414 disable_irq_nosync(vector); 5415 rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx); 5416 if (rc) { 5417 enable_irq(vector); 5418 goto err_out; 5419 } 5420 bnxt_set_db(bp, &cpr->cp_db, type, map_idx, ring->fw_ring_id); 5421 bnxt_db_nq(bp, &cpr->cp_db, cpr->cp_raw_cons); 5422 enable_irq(vector); 5423 bp->grp_info[i].cp_fw_ring_id = ring->fw_ring_id; 5424 5425 if (!i) { 5426 rc = bnxt_hwrm_set_async_event_cr(bp, ring->fw_ring_id); 5427 if (rc) 5428 netdev_warn(bp->dev, "Failed to set async event completion ring.\n"); 5429 } 5430 } 5431 5432 type = HWRM_RING_ALLOC_TX; 5433 for (i = 0; i < bp->tx_nr_rings; i++) { 5434 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; 5435 struct bnxt_ring_struct *ring; 5436 u32 map_idx; 5437 5438 if (bp->flags & BNXT_FLAG_CHIP_P5) { 5439 struct bnxt_napi *bnapi = txr->bnapi; 5440 struct bnxt_cp_ring_info *cpr, *cpr2; 5441 u32 type2 = HWRM_RING_ALLOC_CMPL; 5442 5443 cpr = &bnapi->cp_ring; 5444 cpr2 = cpr->cp_ring_arr[BNXT_TX_HDL]; 5445 ring = &cpr2->cp_ring_struct; 5446 ring->handle = BNXT_TX_HDL; 5447 map_idx = bnapi->index; 5448 rc = hwrm_ring_alloc_send_msg(bp, ring, type2, map_idx); 5449 if (rc) 5450 goto err_out; 5451 bnxt_set_db(bp, &cpr2->cp_db, type2, map_idx, 5452 ring->fw_ring_id); 5453 bnxt_db_cq(bp, &cpr2->cp_db, cpr2->cp_raw_cons); 5454 } 5455 ring = &txr->tx_ring_struct; 5456 map_idx = i; 5457 rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx); 5458 if (rc) 5459 goto err_out; 5460 bnxt_set_db(bp, &txr->tx_db, type, map_idx, ring->fw_ring_id); 5461 } 5462 5463 type = HWRM_RING_ALLOC_RX; 5464 for (i = 0; i < bp->rx_nr_rings; i++) { 5465 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 5466 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct; 5467 struct bnxt_napi *bnapi = rxr->bnapi; 5468 u32 map_idx = bnapi->index; 5469 5470 rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx); 5471 if (rc) 5472 goto err_out; 5473 bnxt_set_db(bp, &rxr->rx_db, type, map_idx, ring->fw_ring_id); 5474 /* If we have agg rings, post agg buffers first. */ 5475 if (!agg_rings) 5476 bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod); 5477 bp->grp_info[map_idx].rx_fw_ring_id = ring->fw_ring_id; 5478 if (bp->flags & BNXT_FLAG_CHIP_P5) { 5479 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 5480 u32 type2 = HWRM_RING_ALLOC_CMPL; 5481 struct bnxt_cp_ring_info *cpr2; 5482 5483 cpr2 = cpr->cp_ring_arr[BNXT_RX_HDL]; 5484 ring = &cpr2->cp_ring_struct; 5485 ring->handle = BNXT_RX_HDL; 5486 rc = hwrm_ring_alloc_send_msg(bp, ring, type2, map_idx); 5487 if (rc) 5488 goto err_out; 5489 bnxt_set_db(bp, &cpr2->cp_db, type2, map_idx, 5490 ring->fw_ring_id); 5491 bnxt_db_cq(bp, &cpr2->cp_db, cpr2->cp_raw_cons); 5492 } 5493 } 5494 5495 if (agg_rings) { 5496 type = HWRM_RING_ALLOC_AGG; 5497 for (i = 0; i < bp->rx_nr_rings; i++) { 5498 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 5499 struct bnxt_ring_struct *ring = 5500 &rxr->rx_agg_ring_struct; 5501 u32 grp_idx = ring->grp_idx; 5502 u32 map_idx = grp_idx + bp->rx_nr_rings; 5503 5504 rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx); 5505 if (rc) 5506 goto err_out; 5507 5508 bnxt_set_db(bp, &rxr->rx_agg_db, type, map_idx, 5509 ring->fw_ring_id); 5510 bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod); 5511 bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod); 5512 bp->grp_info[grp_idx].agg_fw_ring_id = ring->fw_ring_id; 5513 } 5514 } 5515 err_out: 5516 return rc; 5517 } 5518 5519 static int hwrm_ring_free_send_msg(struct bnxt *bp, 5520 struct bnxt_ring_struct *ring, 5521 u32 ring_type, int cmpl_ring_id) 5522 { 5523 int rc; 5524 struct hwrm_ring_free_input req = {0}; 5525 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr; 5526 u16 error_code; 5527 5528 if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state)) 5529 return 0; 5530 5531 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_FREE, cmpl_ring_id, -1); 5532 req.ring_type = ring_type; 5533 req.ring_id = cpu_to_le16(ring->fw_ring_id); 5534 5535 mutex_lock(&bp->hwrm_cmd_lock); 5536 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5537 error_code = le16_to_cpu(resp->error_code); 5538 mutex_unlock(&bp->hwrm_cmd_lock); 5539 5540 if (rc || error_code) { 5541 netdev_err(bp->dev, "hwrm_ring_free type %d failed. rc:%x err:%x\n", 5542 ring_type, rc, error_code); 5543 return -EIO; 5544 } 5545 return 0; 5546 } 5547 5548 static void bnxt_hwrm_ring_free(struct bnxt *bp, bool close_path) 5549 { 5550 u32 type; 5551 int i; 5552 5553 if (!bp->bnapi) 5554 return; 5555 5556 for (i = 0; i < bp->tx_nr_rings; i++) { 5557 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; 5558 struct bnxt_ring_struct *ring = &txr->tx_ring_struct; 5559 5560 if (ring->fw_ring_id != INVALID_HW_RING_ID) { 5561 u32 cmpl_ring_id = bnxt_cp_ring_for_tx(bp, txr); 5562 5563 hwrm_ring_free_send_msg(bp, ring, 5564 RING_FREE_REQ_RING_TYPE_TX, 5565 close_path ? cmpl_ring_id : 5566 INVALID_HW_RING_ID); 5567 ring->fw_ring_id = INVALID_HW_RING_ID; 5568 } 5569 } 5570 5571 for (i = 0; i < bp->rx_nr_rings; i++) { 5572 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 5573 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct; 5574 u32 grp_idx = rxr->bnapi->index; 5575 5576 if (ring->fw_ring_id != INVALID_HW_RING_ID) { 5577 u32 cmpl_ring_id = bnxt_cp_ring_for_rx(bp, rxr); 5578 5579 hwrm_ring_free_send_msg(bp, ring, 5580 RING_FREE_REQ_RING_TYPE_RX, 5581 close_path ? cmpl_ring_id : 5582 INVALID_HW_RING_ID); 5583 ring->fw_ring_id = INVALID_HW_RING_ID; 5584 bp->grp_info[grp_idx].rx_fw_ring_id = 5585 INVALID_HW_RING_ID; 5586 } 5587 } 5588 5589 if (bp->flags & BNXT_FLAG_CHIP_P5) 5590 type = RING_FREE_REQ_RING_TYPE_RX_AGG; 5591 else 5592 type = RING_FREE_REQ_RING_TYPE_RX; 5593 for (i = 0; i < bp->rx_nr_rings; i++) { 5594 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 5595 struct bnxt_ring_struct *ring = &rxr->rx_agg_ring_struct; 5596 u32 grp_idx = rxr->bnapi->index; 5597 5598 if (ring->fw_ring_id != INVALID_HW_RING_ID) { 5599 u32 cmpl_ring_id = bnxt_cp_ring_for_rx(bp, rxr); 5600 5601 hwrm_ring_free_send_msg(bp, ring, type, 5602 close_path ? cmpl_ring_id : 5603 INVALID_HW_RING_ID); 5604 ring->fw_ring_id = INVALID_HW_RING_ID; 5605 bp->grp_info[grp_idx].agg_fw_ring_id = 5606 INVALID_HW_RING_ID; 5607 } 5608 } 5609 5610 /* The completion rings are about to be freed. After that the 5611 * IRQ doorbell will not work anymore. So we need to disable 5612 * IRQ here. 5613 */ 5614 bnxt_disable_int_sync(bp); 5615 5616 if (bp->flags & BNXT_FLAG_CHIP_P5) 5617 type = RING_FREE_REQ_RING_TYPE_NQ; 5618 else 5619 type = RING_FREE_REQ_RING_TYPE_L2_CMPL; 5620 for (i = 0; i < bp->cp_nr_rings; i++) { 5621 struct bnxt_napi *bnapi = bp->bnapi[i]; 5622 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 5623 struct bnxt_ring_struct *ring; 5624 int j; 5625 5626 for (j = 0; j < 2; j++) { 5627 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j]; 5628 5629 if (cpr2) { 5630 ring = &cpr2->cp_ring_struct; 5631 if (ring->fw_ring_id == INVALID_HW_RING_ID) 5632 continue; 5633 hwrm_ring_free_send_msg(bp, ring, 5634 RING_FREE_REQ_RING_TYPE_L2_CMPL, 5635 INVALID_HW_RING_ID); 5636 ring->fw_ring_id = INVALID_HW_RING_ID; 5637 } 5638 } 5639 ring = &cpr->cp_ring_struct; 5640 if (ring->fw_ring_id != INVALID_HW_RING_ID) { 5641 hwrm_ring_free_send_msg(bp, ring, type, 5642 INVALID_HW_RING_ID); 5643 ring->fw_ring_id = INVALID_HW_RING_ID; 5644 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID; 5645 } 5646 } 5647 } 5648 5649 static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max, 5650 bool shared); 5651 5652 static int bnxt_hwrm_get_rings(struct bnxt *bp) 5653 { 5654 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr; 5655 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 5656 struct hwrm_func_qcfg_input req = {0}; 5657 int rc; 5658 5659 if (bp->hwrm_spec_code < 0x10601) 5660 return 0; 5661 5662 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1); 5663 req.fid = cpu_to_le16(0xffff); 5664 mutex_lock(&bp->hwrm_cmd_lock); 5665 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5666 if (rc) { 5667 mutex_unlock(&bp->hwrm_cmd_lock); 5668 return rc; 5669 } 5670 5671 hw_resc->resv_tx_rings = le16_to_cpu(resp->alloc_tx_rings); 5672 if (BNXT_NEW_RM(bp)) { 5673 u16 cp, stats; 5674 5675 hw_resc->resv_rx_rings = le16_to_cpu(resp->alloc_rx_rings); 5676 hw_resc->resv_hw_ring_grps = 5677 le32_to_cpu(resp->alloc_hw_ring_grps); 5678 hw_resc->resv_vnics = le16_to_cpu(resp->alloc_vnics); 5679 cp = le16_to_cpu(resp->alloc_cmpl_rings); 5680 stats = le16_to_cpu(resp->alloc_stat_ctx); 5681 hw_resc->resv_irqs = cp; 5682 if (bp->flags & BNXT_FLAG_CHIP_P5) { 5683 int rx = hw_resc->resv_rx_rings; 5684 int tx = hw_resc->resv_tx_rings; 5685 5686 if (bp->flags & BNXT_FLAG_AGG_RINGS) 5687 rx >>= 1; 5688 if (cp < (rx + tx)) { 5689 bnxt_trim_rings(bp, &rx, &tx, cp, false); 5690 if (bp->flags & BNXT_FLAG_AGG_RINGS) 5691 rx <<= 1; 5692 hw_resc->resv_rx_rings = rx; 5693 hw_resc->resv_tx_rings = tx; 5694 } 5695 hw_resc->resv_irqs = le16_to_cpu(resp->alloc_msix); 5696 hw_resc->resv_hw_ring_grps = rx; 5697 } 5698 hw_resc->resv_cp_rings = cp; 5699 hw_resc->resv_stat_ctxs = stats; 5700 } 5701 mutex_unlock(&bp->hwrm_cmd_lock); 5702 return 0; 5703 } 5704 5705 /* Caller must hold bp->hwrm_cmd_lock */ 5706 int __bnxt_hwrm_get_tx_rings(struct bnxt *bp, u16 fid, int *tx_rings) 5707 { 5708 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr; 5709 struct hwrm_func_qcfg_input req = {0}; 5710 int rc; 5711 5712 if (bp->hwrm_spec_code < 0x10601) 5713 return 0; 5714 5715 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1); 5716 req.fid = cpu_to_le16(fid); 5717 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5718 if (!rc) 5719 *tx_rings = le16_to_cpu(resp->alloc_tx_rings); 5720 5721 return rc; 5722 } 5723 5724 static bool bnxt_rfs_supported(struct bnxt *bp); 5725 5726 static void 5727 __bnxt_hwrm_reserve_pf_rings(struct bnxt *bp, struct hwrm_func_cfg_input *req, 5728 int tx_rings, int rx_rings, int ring_grps, 5729 int cp_rings, int stats, int vnics) 5730 { 5731 u32 enables = 0; 5732 5733 bnxt_hwrm_cmd_hdr_init(bp, req, HWRM_FUNC_CFG, -1, -1); 5734 req->fid = cpu_to_le16(0xffff); 5735 enables |= tx_rings ? FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS : 0; 5736 req->num_tx_rings = cpu_to_le16(tx_rings); 5737 if (BNXT_NEW_RM(bp)) { 5738 enables |= rx_rings ? FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS : 0; 5739 enables |= stats ? FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0; 5740 if (bp->flags & BNXT_FLAG_CHIP_P5) { 5741 enables |= cp_rings ? FUNC_CFG_REQ_ENABLES_NUM_MSIX : 0; 5742 enables |= tx_rings + ring_grps ? 5743 FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0; 5744 enables |= rx_rings ? 5745 FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0; 5746 } else { 5747 enables |= cp_rings ? 5748 FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0; 5749 enables |= ring_grps ? 5750 FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS | 5751 FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0; 5752 } 5753 enables |= vnics ? FUNC_CFG_REQ_ENABLES_NUM_VNICS : 0; 5754 5755 req->num_rx_rings = cpu_to_le16(rx_rings); 5756 if (bp->flags & BNXT_FLAG_CHIP_P5) { 5757 req->num_cmpl_rings = cpu_to_le16(tx_rings + ring_grps); 5758 req->num_msix = cpu_to_le16(cp_rings); 5759 req->num_rsscos_ctxs = 5760 cpu_to_le16(DIV_ROUND_UP(ring_grps, 64)); 5761 } else { 5762 req->num_cmpl_rings = cpu_to_le16(cp_rings); 5763 req->num_hw_ring_grps = cpu_to_le16(ring_grps); 5764 req->num_rsscos_ctxs = cpu_to_le16(1); 5765 if (!(bp->flags & BNXT_FLAG_NEW_RSS_CAP) && 5766 bnxt_rfs_supported(bp)) 5767 req->num_rsscos_ctxs = 5768 cpu_to_le16(ring_grps + 1); 5769 } 5770 req->num_stat_ctxs = cpu_to_le16(stats); 5771 req->num_vnics = cpu_to_le16(vnics); 5772 } 5773 req->enables = cpu_to_le32(enables); 5774 } 5775 5776 static void 5777 __bnxt_hwrm_reserve_vf_rings(struct bnxt *bp, 5778 struct hwrm_func_vf_cfg_input *req, int tx_rings, 5779 int rx_rings, int ring_grps, int cp_rings, 5780 int stats, int vnics) 5781 { 5782 u32 enables = 0; 5783 5784 bnxt_hwrm_cmd_hdr_init(bp, req, HWRM_FUNC_VF_CFG, -1, -1); 5785 enables |= tx_rings ? FUNC_VF_CFG_REQ_ENABLES_NUM_TX_RINGS : 0; 5786 enables |= rx_rings ? FUNC_VF_CFG_REQ_ENABLES_NUM_RX_RINGS | 5787 FUNC_VF_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0; 5788 enables |= stats ? FUNC_VF_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0; 5789 if (bp->flags & BNXT_FLAG_CHIP_P5) { 5790 enables |= tx_rings + ring_grps ? 5791 FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0; 5792 } else { 5793 enables |= cp_rings ? 5794 FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0; 5795 enables |= ring_grps ? 5796 FUNC_VF_CFG_REQ_ENABLES_NUM_HW_RING_GRPS : 0; 5797 } 5798 enables |= vnics ? FUNC_VF_CFG_REQ_ENABLES_NUM_VNICS : 0; 5799 enables |= FUNC_VF_CFG_REQ_ENABLES_NUM_L2_CTXS; 5800 5801 req->num_l2_ctxs = cpu_to_le16(BNXT_VF_MAX_L2_CTX); 5802 req->num_tx_rings = cpu_to_le16(tx_rings); 5803 req->num_rx_rings = cpu_to_le16(rx_rings); 5804 if (bp->flags & BNXT_FLAG_CHIP_P5) { 5805 req->num_cmpl_rings = cpu_to_le16(tx_rings + ring_grps); 5806 req->num_rsscos_ctxs = cpu_to_le16(DIV_ROUND_UP(ring_grps, 64)); 5807 } else { 5808 req->num_cmpl_rings = cpu_to_le16(cp_rings); 5809 req->num_hw_ring_grps = cpu_to_le16(ring_grps); 5810 req->num_rsscos_ctxs = cpu_to_le16(BNXT_VF_MAX_RSS_CTX); 5811 } 5812 req->num_stat_ctxs = cpu_to_le16(stats); 5813 req->num_vnics = cpu_to_le16(vnics); 5814 5815 req->enables = cpu_to_le32(enables); 5816 } 5817 5818 static int 5819 bnxt_hwrm_reserve_pf_rings(struct bnxt *bp, int tx_rings, int rx_rings, 5820 int ring_grps, int cp_rings, int stats, int vnics) 5821 { 5822 struct hwrm_func_cfg_input req = {0}; 5823 int rc; 5824 5825 __bnxt_hwrm_reserve_pf_rings(bp, &req, tx_rings, rx_rings, ring_grps, 5826 cp_rings, stats, vnics); 5827 if (!req.enables) 5828 return 0; 5829 5830 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5831 if (rc) 5832 return rc; 5833 5834 if (bp->hwrm_spec_code < 0x10601) 5835 bp->hw_resc.resv_tx_rings = tx_rings; 5836 5837 return bnxt_hwrm_get_rings(bp); 5838 } 5839 5840 static int 5841 bnxt_hwrm_reserve_vf_rings(struct bnxt *bp, int tx_rings, int rx_rings, 5842 int ring_grps, int cp_rings, int stats, int vnics) 5843 { 5844 struct hwrm_func_vf_cfg_input req = {0}; 5845 int rc; 5846 5847 if (!BNXT_NEW_RM(bp)) { 5848 bp->hw_resc.resv_tx_rings = tx_rings; 5849 return 0; 5850 } 5851 5852 __bnxt_hwrm_reserve_vf_rings(bp, &req, tx_rings, rx_rings, ring_grps, 5853 cp_rings, stats, vnics); 5854 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5855 if (rc) 5856 return rc; 5857 5858 return bnxt_hwrm_get_rings(bp); 5859 } 5860 5861 static int bnxt_hwrm_reserve_rings(struct bnxt *bp, int tx, int rx, int grp, 5862 int cp, int stat, int vnic) 5863 { 5864 if (BNXT_PF(bp)) 5865 return bnxt_hwrm_reserve_pf_rings(bp, tx, rx, grp, cp, stat, 5866 vnic); 5867 else 5868 return bnxt_hwrm_reserve_vf_rings(bp, tx, rx, grp, cp, stat, 5869 vnic); 5870 } 5871 5872 int bnxt_nq_rings_in_use(struct bnxt *bp) 5873 { 5874 int cp = bp->cp_nr_rings; 5875 int ulp_msix, ulp_base; 5876 5877 ulp_msix = bnxt_get_ulp_msix_num(bp); 5878 if (ulp_msix) { 5879 ulp_base = bnxt_get_ulp_msix_base(bp); 5880 cp += ulp_msix; 5881 if ((ulp_base + ulp_msix) > cp) 5882 cp = ulp_base + ulp_msix; 5883 } 5884 return cp; 5885 } 5886 5887 static int bnxt_cp_rings_in_use(struct bnxt *bp) 5888 { 5889 int cp; 5890 5891 if (!(bp->flags & BNXT_FLAG_CHIP_P5)) 5892 return bnxt_nq_rings_in_use(bp); 5893 5894 cp = bp->tx_nr_rings + bp->rx_nr_rings; 5895 return cp; 5896 } 5897 5898 static int bnxt_get_func_stat_ctxs(struct bnxt *bp) 5899 { 5900 int ulp_stat = bnxt_get_ulp_stat_ctxs(bp); 5901 int cp = bp->cp_nr_rings; 5902 5903 if (!ulp_stat) 5904 return cp; 5905 5906 if (bnxt_nq_rings_in_use(bp) > cp + bnxt_get_ulp_msix_num(bp)) 5907 return bnxt_get_ulp_msix_base(bp) + ulp_stat; 5908 5909 return cp + ulp_stat; 5910 } 5911 5912 static bool bnxt_need_reserve_rings(struct bnxt *bp) 5913 { 5914 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 5915 int cp = bnxt_cp_rings_in_use(bp); 5916 int nq = bnxt_nq_rings_in_use(bp); 5917 int rx = bp->rx_nr_rings, stat; 5918 int vnic = 1, grp = rx; 5919 5920 if (bp->hwrm_spec_code < 0x10601) 5921 return false; 5922 5923 if (hw_resc->resv_tx_rings != bp->tx_nr_rings) 5924 return true; 5925 5926 if ((bp->flags & BNXT_FLAG_RFS) && !(bp->flags & BNXT_FLAG_CHIP_P5)) 5927 vnic = rx + 1; 5928 if (bp->flags & BNXT_FLAG_AGG_RINGS) 5929 rx <<= 1; 5930 stat = bnxt_get_func_stat_ctxs(bp); 5931 if (BNXT_NEW_RM(bp) && 5932 (hw_resc->resv_rx_rings != rx || hw_resc->resv_cp_rings != cp || 5933 hw_resc->resv_vnics != vnic || hw_resc->resv_stat_ctxs != stat || 5934 (hw_resc->resv_hw_ring_grps != grp && 5935 !(bp->flags & BNXT_FLAG_CHIP_P5)))) 5936 return true; 5937 if ((bp->flags & BNXT_FLAG_CHIP_P5) && BNXT_PF(bp) && 5938 hw_resc->resv_irqs != nq) 5939 return true; 5940 return false; 5941 } 5942 5943 static int __bnxt_reserve_rings(struct bnxt *bp) 5944 { 5945 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 5946 int cp = bnxt_nq_rings_in_use(bp); 5947 int tx = bp->tx_nr_rings; 5948 int rx = bp->rx_nr_rings; 5949 int grp, rx_rings, rc; 5950 int vnic = 1, stat; 5951 bool sh = false; 5952 5953 if (!bnxt_need_reserve_rings(bp)) 5954 return 0; 5955 5956 if (bp->flags & BNXT_FLAG_SHARED_RINGS) 5957 sh = true; 5958 if ((bp->flags & BNXT_FLAG_RFS) && !(bp->flags & BNXT_FLAG_CHIP_P5)) 5959 vnic = rx + 1; 5960 if (bp->flags & BNXT_FLAG_AGG_RINGS) 5961 rx <<= 1; 5962 grp = bp->rx_nr_rings; 5963 stat = bnxt_get_func_stat_ctxs(bp); 5964 5965 rc = bnxt_hwrm_reserve_rings(bp, tx, rx, grp, cp, stat, vnic); 5966 if (rc) 5967 return rc; 5968 5969 tx = hw_resc->resv_tx_rings; 5970 if (BNXT_NEW_RM(bp)) { 5971 rx = hw_resc->resv_rx_rings; 5972 cp = hw_resc->resv_irqs; 5973 grp = hw_resc->resv_hw_ring_grps; 5974 vnic = hw_resc->resv_vnics; 5975 stat = hw_resc->resv_stat_ctxs; 5976 } 5977 5978 rx_rings = rx; 5979 if (bp->flags & BNXT_FLAG_AGG_RINGS) { 5980 if (rx >= 2) { 5981 rx_rings = rx >> 1; 5982 } else { 5983 if (netif_running(bp->dev)) 5984 return -ENOMEM; 5985 5986 bp->flags &= ~BNXT_FLAG_AGG_RINGS; 5987 bp->flags |= BNXT_FLAG_NO_AGG_RINGS; 5988 bp->dev->hw_features &= ~NETIF_F_LRO; 5989 bp->dev->features &= ~NETIF_F_LRO; 5990 bnxt_set_ring_params(bp); 5991 } 5992 } 5993 rx_rings = min_t(int, rx_rings, grp); 5994 cp = min_t(int, cp, bp->cp_nr_rings); 5995 if (stat > bnxt_get_ulp_stat_ctxs(bp)) 5996 stat -= bnxt_get_ulp_stat_ctxs(bp); 5997 cp = min_t(int, cp, stat); 5998 rc = bnxt_trim_rings(bp, &rx_rings, &tx, cp, sh); 5999 if (bp->flags & BNXT_FLAG_AGG_RINGS) 6000 rx = rx_rings << 1; 6001 cp = sh ? max_t(int, tx, rx_rings) : tx + rx_rings; 6002 bp->tx_nr_rings = tx; 6003 bp->rx_nr_rings = rx_rings; 6004 bp->cp_nr_rings = cp; 6005 6006 if (!tx || !rx || !cp || !grp || !vnic || !stat) 6007 return -ENOMEM; 6008 6009 return rc; 6010 } 6011 6012 static int bnxt_hwrm_check_vf_rings(struct bnxt *bp, int tx_rings, int rx_rings, 6013 int ring_grps, int cp_rings, int stats, 6014 int vnics) 6015 { 6016 struct hwrm_func_vf_cfg_input req = {0}; 6017 u32 flags; 6018 6019 if (!BNXT_NEW_RM(bp)) 6020 return 0; 6021 6022 __bnxt_hwrm_reserve_vf_rings(bp, &req, tx_rings, rx_rings, ring_grps, 6023 cp_rings, stats, vnics); 6024 flags = FUNC_VF_CFG_REQ_FLAGS_TX_ASSETS_TEST | 6025 FUNC_VF_CFG_REQ_FLAGS_RX_ASSETS_TEST | 6026 FUNC_VF_CFG_REQ_FLAGS_CMPL_ASSETS_TEST | 6027 FUNC_VF_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST | 6028 FUNC_VF_CFG_REQ_FLAGS_VNIC_ASSETS_TEST | 6029 FUNC_VF_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST; 6030 if (!(bp->flags & BNXT_FLAG_CHIP_P5)) 6031 flags |= FUNC_VF_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST; 6032 6033 req.flags = cpu_to_le32(flags); 6034 return hwrm_send_message_silent(bp, &req, sizeof(req), 6035 HWRM_CMD_TIMEOUT); 6036 } 6037 6038 static int bnxt_hwrm_check_pf_rings(struct bnxt *bp, int tx_rings, int rx_rings, 6039 int ring_grps, int cp_rings, int stats, 6040 int vnics) 6041 { 6042 struct hwrm_func_cfg_input req = {0}; 6043 u32 flags; 6044 6045 __bnxt_hwrm_reserve_pf_rings(bp, &req, tx_rings, rx_rings, ring_grps, 6046 cp_rings, stats, vnics); 6047 flags = FUNC_CFG_REQ_FLAGS_TX_ASSETS_TEST; 6048 if (BNXT_NEW_RM(bp)) { 6049 flags |= FUNC_CFG_REQ_FLAGS_RX_ASSETS_TEST | 6050 FUNC_CFG_REQ_FLAGS_CMPL_ASSETS_TEST | 6051 FUNC_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST | 6052 FUNC_CFG_REQ_FLAGS_VNIC_ASSETS_TEST; 6053 if (bp->flags & BNXT_FLAG_CHIP_P5) 6054 flags |= FUNC_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST | 6055 FUNC_CFG_REQ_FLAGS_NQ_ASSETS_TEST; 6056 else 6057 flags |= FUNC_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST; 6058 } 6059 6060 req.flags = cpu_to_le32(flags); 6061 return hwrm_send_message_silent(bp, &req, sizeof(req), 6062 HWRM_CMD_TIMEOUT); 6063 } 6064 6065 static int bnxt_hwrm_check_rings(struct bnxt *bp, int tx_rings, int rx_rings, 6066 int ring_grps, int cp_rings, int stats, 6067 int vnics) 6068 { 6069 if (bp->hwrm_spec_code < 0x10801) 6070 return 0; 6071 6072 if (BNXT_PF(bp)) 6073 return bnxt_hwrm_check_pf_rings(bp, tx_rings, rx_rings, 6074 ring_grps, cp_rings, stats, 6075 vnics); 6076 6077 return bnxt_hwrm_check_vf_rings(bp, tx_rings, rx_rings, ring_grps, 6078 cp_rings, stats, vnics); 6079 } 6080 6081 static void bnxt_hwrm_coal_params_qcaps(struct bnxt *bp) 6082 { 6083 struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr; 6084 struct bnxt_coal_cap *coal_cap = &bp->coal_cap; 6085 struct hwrm_ring_aggint_qcaps_input req = {0}; 6086 int rc; 6087 6088 coal_cap->cmpl_params = BNXT_LEGACY_COAL_CMPL_PARAMS; 6089 coal_cap->num_cmpl_dma_aggr_max = 63; 6090 coal_cap->num_cmpl_dma_aggr_during_int_max = 63; 6091 coal_cap->cmpl_aggr_dma_tmr_max = 65535; 6092 coal_cap->cmpl_aggr_dma_tmr_during_int_max = 65535; 6093 coal_cap->int_lat_tmr_min_max = 65535; 6094 coal_cap->int_lat_tmr_max_max = 65535; 6095 coal_cap->num_cmpl_aggr_int_max = 65535; 6096 coal_cap->timer_units = 80; 6097 6098 if (bp->hwrm_spec_code < 0x10902) 6099 return; 6100 6101 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_AGGINT_QCAPS, -1, -1); 6102 mutex_lock(&bp->hwrm_cmd_lock); 6103 rc = _hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 6104 if (!rc) { 6105 coal_cap->cmpl_params = le32_to_cpu(resp->cmpl_params); 6106 coal_cap->nq_params = le32_to_cpu(resp->nq_params); 6107 coal_cap->num_cmpl_dma_aggr_max = 6108 le16_to_cpu(resp->num_cmpl_dma_aggr_max); 6109 coal_cap->num_cmpl_dma_aggr_during_int_max = 6110 le16_to_cpu(resp->num_cmpl_dma_aggr_during_int_max); 6111 coal_cap->cmpl_aggr_dma_tmr_max = 6112 le16_to_cpu(resp->cmpl_aggr_dma_tmr_max); 6113 coal_cap->cmpl_aggr_dma_tmr_during_int_max = 6114 le16_to_cpu(resp->cmpl_aggr_dma_tmr_during_int_max); 6115 coal_cap->int_lat_tmr_min_max = 6116 le16_to_cpu(resp->int_lat_tmr_min_max); 6117 coal_cap->int_lat_tmr_max_max = 6118 le16_to_cpu(resp->int_lat_tmr_max_max); 6119 coal_cap->num_cmpl_aggr_int_max = 6120 le16_to_cpu(resp->num_cmpl_aggr_int_max); 6121 coal_cap->timer_units = le16_to_cpu(resp->timer_units); 6122 } 6123 mutex_unlock(&bp->hwrm_cmd_lock); 6124 } 6125 6126 static u16 bnxt_usec_to_coal_tmr(struct bnxt *bp, u16 usec) 6127 { 6128 struct bnxt_coal_cap *coal_cap = &bp->coal_cap; 6129 6130 return usec * 1000 / coal_cap->timer_units; 6131 } 6132 6133 static void bnxt_hwrm_set_coal_params(struct bnxt *bp, 6134 struct bnxt_coal *hw_coal, 6135 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req) 6136 { 6137 struct bnxt_coal_cap *coal_cap = &bp->coal_cap; 6138 u32 cmpl_params = coal_cap->cmpl_params; 6139 u16 val, tmr, max, flags = 0; 6140 6141 max = hw_coal->bufs_per_record * 128; 6142 if (hw_coal->budget) 6143 max = hw_coal->bufs_per_record * hw_coal->budget; 6144 max = min_t(u16, max, coal_cap->num_cmpl_aggr_int_max); 6145 6146 val = clamp_t(u16, hw_coal->coal_bufs, 1, max); 6147 req->num_cmpl_aggr_int = cpu_to_le16(val); 6148 6149 val = min_t(u16, val, coal_cap->num_cmpl_dma_aggr_max); 6150 req->num_cmpl_dma_aggr = cpu_to_le16(val); 6151 6152 val = clamp_t(u16, hw_coal->coal_bufs_irq, 1, 6153 coal_cap->num_cmpl_dma_aggr_during_int_max); 6154 req->num_cmpl_dma_aggr_during_int = cpu_to_le16(val); 6155 6156 tmr = bnxt_usec_to_coal_tmr(bp, hw_coal->coal_ticks); 6157 tmr = clamp_t(u16, tmr, 1, coal_cap->int_lat_tmr_max_max); 6158 req->int_lat_tmr_max = cpu_to_le16(tmr); 6159 6160 /* min timer set to 1/2 of interrupt timer */ 6161 if (cmpl_params & RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN) { 6162 val = tmr / 2; 6163 val = clamp_t(u16, val, 1, coal_cap->int_lat_tmr_min_max); 6164 req->int_lat_tmr_min = cpu_to_le16(val); 6165 req->enables |= cpu_to_le16(BNXT_COAL_CMPL_MIN_TMR_ENABLE); 6166 } 6167 6168 /* buf timer set to 1/4 of interrupt timer */ 6169 val = clamp_t(u16, tmr / 4, 1, coal_cap->cmpl_aggr_dma_tmr_max); 6170 req->cmpl_aggr_dma_tmr = cpu_to_le16(val); 6171 6172 if (cmpl_params & 6173 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT) { 6174 tmr = bnxt_usec_to_coal_tmr(bp, hw_coal->coal_ticks_irq); 6175 val = clamp_t(u16, tmr, 1, 6176 coal_cap->cmpl_aggr_dma_tmr_during_int_max); 6177 req->cmpl_aggr_dma_tmr_during_int = cpu_to_le16(val); 6178 req->enables |= 6179 cpu_to_le16(BNXT_COAL_CMPL_AGGR_TMR_DURING_INT_ENABLE); 6180 } 6181 6182 if (cmpl_params & RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET) 6183 flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET; 6184 if ((cmpl_params & RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE) && 6185 hw_coal->idle_thresh && hw_coal->coal_ticks < hw_coal->idle_thresh) 6186 flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE; 6187 req->flags = cpu_to_le16(flags); 6188 req->enables |= cpu_to_le16(BNXT_COAL_CMPL_ENABLES); 6189 } 6190 6191 /* Caller holds bp->hwrm_cmd_lock */ 6192 static int __bnxt_hwrm_set_coal_nq(struct bnxt *bp, struct bnxt_napi *bnapi, 6193 struct bnxt_coal *hw_coal) 6194 { 6195 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0}; 6196 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 6197 struct bnxt_coal_cap *coal_cap = &bp->coal_cap; 6198 u32 nq_params = coal_cap->nq_params; 6199 u16 tmr; 6200 6201 if (!(nq_params & RING_AGGINT_QCAPS_RESP_NQ_PARAMS_INT_LAT_TMR_MIN)) 6202 return 0; 6203 6204 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, 6205 -1, -1); 6206 req.ring_id = cpu_to_le16(cpr->cp_ring_struct.fw_ring_id); 6207 req.flags = 6208 cpu_to_le16(RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_IS_NQ); 6209 6210 tmr = bnxt_usec_to_coal_tmr(bp, hw_coal->coal_ticks) / 2; 6211 tmr = clamp_t(u16, tmr, 1, coal_cap->int_lat_tmr_min_max); 6212 req.int_lat_tmr_min = cpu_to_le16(tmr); 6213 req.enables |= cpu_to_le16(BNXT_COAL_CMPL_MIN_TMR_ENABLE); 6214 return _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 6215 } 6216 6217 int bnxt_hwrm_set_ring_coal(struct bnxt *bp, struct bnxt_napi *bnapi) 6218 { 6219 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx = {0}; 6220 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 6221 struct bnxt_coal coal; 6222 6223 /* Tick values in micro seconds. 6224 * 1 coal_buf x bufs_per_record = 1 completion record. 6225 */ 6226 memcpy(&coal, &bp->rx_coal, sizeof(struct bnxt_coal)); 6227 6228 coal.coal_ticks = cpr->rx_ring_coal.coal_ticks; 6229 coal.coal_bufs = cpr->rx_ring_coal.coal_bufs; 6230 6231 if (!bnapi->rx_ring) 6232 return -ENODEV; 6233 6234 bnxt_hwrm_cmd_hdr_init(bp, &req_rx, 6235 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1); 6236 6237 bnxt_hwrm_set_coal_params(bp, &coal, &req_rx); 6238 6239 req_rx.ring_id = cpu_to_le16(bnxt_cp_ring_for_rx(bp, bnapi->rx_ring)); 6240 6241 return hwrm_send_message(bp, &req_rx, sizeof(req_rx), 6242 HWRM_CMD_TIMEOUT); 6243 } 6244 6245 int bnxt_hwrm_set_coal(struct bnxt *bp) 6246 { 6247 int i, rc = 0; 6248 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx = {0}, 6249 req_tx = {0}, *req; 6250 6251 bnxt_hwrm_cmd_hdr_init(bp, &req_rx, 6252 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1); 6253 bnxt_hwrm_cmd_hdr_init(bp, &req_tx, 6254 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1); 6255 6256 bnxt_hwrm_set_coal_params(bp, &bp->rx_coal, &req_rx); 6257 bnxt_hwrm_set_coal_params(bp, &bp->tx_coal, &req_tx); 6258 6259 mutex_lock(&bp->hwrm_cmd_lock); 6260 for (i = 0; i < bp->cp_nr_rings; i++) { 6261 struct bnxt_napi *bnapi = bp->bnapi[i]; 6262 struct bnxt_coal *hw_coal; 6263 u16 ring_id; 6264 6265 req = &req_rx; 6266 if (!bnapi->rx_ring) { 6267 ring_id = bnxt_cp_ring_for_tx(bp, bnapi->tx_ring); 6268 req = &req_tx; 6269 } else { 6270 ring_id = bnxt_cp_ring_for_rx(bp, bnapi->rx_ring); 6271 } 6272 req->ring_id = cpu_to_le16(ring_id); 6273 6274 rc = _hwrm_send_message(bp, req, sizeof(*req), 6275 HWRM_CMD_TIMEOUT); 6276 if (rc) 6277 break; 6278 6279 if (!(bp->flags & BNXT_FLAG_CHIP_P5)) 6280 continue; 6281 6282 if (bnapi->rx_ring && bnapi->tx_ring) { 6283 req = &req_tx; 6284 ring_id = bnxt_cp_ring_for_tx(bp, bnapi->tx_ring); 6285 req->ring_id = cpu_to_le16(ring_id); 6286 rc = _hwrm_send_message(bp, req, sizeof(*req), 6287 HWRM_CMD_TIMEOUT); 6288 if (rc) 6289 break; 6290 } 6291 if (bnapi->rx_ring) 6292 hw_coal = &bp->rx_coal; 6293 else 6294 hw_coal = &bp->tx_coal; 6295 __bnxt_hwrm_set_coal_nq(bp, bnapi, hw_coal); 6296 } 6297 mutex_unlock(&bp->hwrm_cmd_lock); 6298 return rc; 6299 } 6300 6301 static void bnxt_hwrm_stat_ctx_free(struct bnxt *bp) 6302 { 6303 struct hwrm_stat_ctx_clr_stats_input req0 = {0}; 6304 struct hwrm_stat_ctx_free_input req = {0}; 6305 int i; 6306 6307 if (!bp->bnapi) 6308 return; 6309 6310 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 6311 return; 6312 6313 bnxt_hwrm_cmd_hdr_init(bp, &req0, HWRM_STAT_CTX_CLR_STATS, -1, -1); 6314 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_FREE, -1, -1); 6315 6316 mutex_lock(&bp->hwrm_cmd_lock); 6317 for (i = 0; i < bp->cp_nr_rings; i++) { 6318 struct bnxt_napi *bnapi = bp->bnapi[i]; 6319 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 6320 6321 if (cpr->hw_stats_ctx_id != INVALID_STATS_CTX_ID) { 6322 req.stat_ctx_id = cpu_to_le32(cpr->hw_stats_ctx_id); 6323 if (BNXT_FW_MAJ(bp) <= 20) { 6324 req0.stat_ctx_id = req.stat_ctx_id; 6325 _hwrm_send_message(bp, &req0, sizeof(req0), 6326 HWRM_CMD_TIMEOUT); 6327 } 6328 _hwrm_send_message(bp, &req, sizeof(req), 6329 HWRM_CMD_TIMEOUT); 6330 6331 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID; 6332 } 6333 } 6334 mutex_unlock(&bp->hwrm_cmd_lock); 6335 } 6336 6337 static int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp) 6338 { 6339 int rc = 0, i; 6340 struct hwrm_stat_ctx_alloc_input req = {0}; 6341 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr; 6342 6343 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 6344 return 0; 6345 6346 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_ALLOC, -1, -1); 6347 6348 req.stats_dma_length = cpu_to_le16(bp->hw_ring_stats_size); 6349 req.update_period_ms = cpu_to_le32(bp->stats_coal_ticks / 1000); 6350 6351 mutex_lock(&bp->hwrm_cmd_lock); 6352 for (i = 0; i < bp->cp_nr_rings; i++) { 6353 struct bnxt_napi *bnapi = bp->bnapi[i]; 6354 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 6355 6356 req.stats_dma_addr = cpu_to_le64(cpr->hw_stats_map); 6357 6358 rc = _hwrm_send_message(bp, &req, sizeof(req), 6359 HWRM_CMD_TIMEOUT); 6360 if (rc) 6361 break; 6362 6363 cpr->hw_stats_ctx_id = le32_to_cpu(resp->stat_ctx_id); 6364 6365 bp->grp_info[i].fw_stats_ctx = cpr->hw_stats_ctx_id; 6366 } 6367 mutex_unlock(&bp->hwrm_cmd_lock); 6368 return rc; 6369 } 6370 6371 static int bnxt_hwrm_func_qcfg(struct bnxt *bp) 6372 { 6373 struct hwrm_func_qcfg_input req = {0}; 6374 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr; 6375 u32 min_db_offset = 0; 6376 u16 flags; 6377 int rc; 6378 6379 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1); 6380 req.fid = cpu_to_le16(0xffff); 6381 mutex_lock(&bp->hwrm_cmd_lock); 6382 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 6383 if (rc) 6384 goto func_qcfg_exit; 6385 6386 #ifdef CONFIG_BNXT_SRIOV 6387 if (BNXT_VF(bp)) { 6388 struct bnxt_vf_info *vf = &bp->vf; 6389 6390 vf->vlan = le16_to_cpu(resp->vlan) & VLAN_VID_MASK; 6391 } else { 6392 bp->pf.registered_vfs = le16_to_cpu(resp->registered_vfs); 6393 } 6394 #endif 6395 flags = le16_to_cpu(resp->flags); 6396 if (flags & (FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED | 6397 FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED)) { 6398 bp->fw_cap |= BNXT_FW_CAP_LLDP_AGENT; 6399 if (flags & FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED) 6400 bp->fw_cap |= BNXT_FW_CAP_DCBX_AGENT; 6401 } 6402 if (BNXT_PF(bp) && (flags & FUNC_QCFG_RESP_FLAGS_MULTI_HOST)) 6403 bp->flags |= BNXT_FLAG_MULTI_HOST; 6404 6405 switch (resp->port_partition_type) { 6406 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0: 6407 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5: 6408 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0: 6409 bp->port_partition_type = resp->port_partition_type; 6410 break; 6411 } 6412 if (bp->hwrm_spec_code < 0x10707 || 6413 resp->evb_mode == FUNC_QCFG_RESP_EVB_MODE_VEB) 6414 bp->br_mode = BRIDGE_MODE_VEB; 6415 else if (resp->evb_mode == FUNC_QCFG_RESP_EVB_MODE_VEPA) 6416 bp->br_mode = BRIDGE_MODE_VEPA; 6417 else 6418 bp->br_mode = BRIDGE_MODE_UNDEF; 6419 6420 bp->max_mtu = le16_to_cpu(resp->max_mtu_configured); 6421 if (!bp->max_mtu) 6422 bp->max_mtu = BNXT_MAX_MTU; 6423 6424 if (bp->db_size) 6425 goto func_qcfg_exit; 6426 6427 if (bp->flags & BNXT_FLAG_CHIP_P5) { 6428 if (BNXT_PF(bp)) 6429 min_db_offset = DB_PF_OFFSET_P5; 6430 else 6431 min_db_offset = DB_VF_OFFSET_P5; 6432 } 6433 bp->db_size = PAGE_ALIGN(le16_to_cpu(resp->l2_doorbell_bar_size_kb) * 6434 1024); 6435 if (!bp->db_size || bp->db_size > pci_resource_len(bp->pdev, 2) || 6436 bp->db_size <= min_db_offset) 6437 bp->db_size = pci_resource_len(bp->pdev, 2); 6438 6439 func_qcfg_exit: 6440 mutex_unlock(&bp->hwrm_cmd_lock); 6441 return rc; 6442 } 6443 6444 static int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp) 6445 { 6446 struct hwrm_func_backing_store_qcaps_input req = {0}; 6447 struct hwrm_func_backing_store_qcaps_output *resp = 6448 bp->hwrm_cmd_resp_addr; 6449 int rc; 6450 6451 if (bp->hwrm_spec_code < 0x10902 || BNXT_VF(bp) || bp->ctx) 6452 return 0; 6453 6454 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_BACKING_STORE_QCAPS, -1, -1); 6455 mutex_lock(&bp->hwrm_cmd_lock); 6456 rc = _hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 6457 if (!rc) { 6458 struct bnxt_ctx_pg_info *ctx_pg; 6459 struct bnxt_ctx_mem_info *ctx; 6460 int i, tqm_rings; 6461 6462 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); 6463 if (!ctx) { 6464 rc = -ENOMEM; 6465 goto ctx_err; 6466 } 6467 ctx->qp_max_entries = le32_to_cpu(resp->qp_max_entries); 6468 ctx->qp_min_qp1_entries = le16_to_cpu(resp->qp_min_qp1_entries); 6469 ctx->qp_max_l2_entries = le16_to_cpu(resp->qp_max_l2_entries); 6470 ctx->qp_entry_size = le16_to_cpu(resp->qp_entry_size); 6471 ctx->srq_max_l2_entries = le16_to_cpu(resp->srq_max_l2_entries); 6472 ctx->srq_max_entries = le32_to_cpu(resp->srq_max_entries); 6473 ctx->srq_entry_size = le16_to_cpu(resp->srq_entry_size); 6474 ctx->cq_max_l2_entries = le16_to_cpu(resp->cq_max_l2_entries); 6475 ctx->cq_max_entries = le32_to_cpu(resp->cq_max_entries); 6476 ctx->cq_entry_size = le16_to_cpu(resp->cq_entry_size); 6477 ctx->vnic_max_vnic_entries = 6478 le16_to_cpu(resp->vnic_max_vnic_entries); 6479 ctx->vnic_max_ring_table_entries = 6480 le16_to_cpu(resp->vnic_max_ring_table_entries); 6481 ctx->vnic_entry_size = le16_to_cpu(resp->vnic_entry_size); 6482 ctx->stat_max_entries = le32_to_cpu(resp->stat_max_entries); 6483 ctx->stat_entry_size = le16_to_cpu(resp->stat_entry_size); 6484 ctx->tqm_entry_size = le16_to_cpu(resp->tqm_entry_size); 6485 ctx->tqm_min_entries_per_ring = 6486 le32_to_cpu(resp->tqm_min_entries_per_ring); 6487 ctx->tqm_max_entries_per_ring = 6488 le32_to_cpu(resp->tqm_max_entries_per_ring); 6489 ctx->tqm_entries_multiple = resp->tqm_entries_multiple; 6490 if (!ctx->tqm_entries_multiple) 6491 ctx->tqm_entries_multiple = 1; 6492 ctx->mrav_max_entries = le32_to_cpu(resp->mrav_max_entries); 6493 ctx->mrav_entry_size = le16_to_cpu(resp->mrav_entry_size); 6494 ctx->mrav_num_entries_units = 6495 le16_to_cpu(resp->mrav_num_entries_units); 6496 ctx->tim_entry_size = le16_to_cpu(resp->tim_entry_size); 6497 ctx->tim_max_entries = le32_to_cpu(resp->tim_max_entries); 6498 ctx->ctx_kind_initializer = resp->ctx_kind_initializer; 6499 ctx->tqm_fp_rings_count = resp->tqm_fp_rings_count; 6500 if (!ctx->tqm_fp_rings_count) 6501 ctx->tqm_fp_rings_count = bp->max_q; 6502 6503 tqm_rings = ctx->tqm_fp_rings_count + 1; 6504 ctx_pg = kcalloc(tqm_rings, sizeof(*ctx_pg), GFP_KERNEL); 6505 if (!ctx_pg) { 6506 kfree(ctx); 6507 rc = -ENOMEM; 6508 goto ctx_err; 6509 } 6510 for (i = 0; i < tqm_rings; i++, ctx_pg++) 6511 ctx->tqm_mem[i] = ctx_pg; 6512 bp->ctx = ctx; 6513 } else { 6514 rc = 0; 6515 } 6516 ctx_err: 6517 mutex_unlock(&bp->hwrm_cmd_lock); 6518 return rc; 6519 } 6520 6521 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem, u8 *pg_attr, 6522 __le64 *pg_dir) 6523 { 6524 u8 pg_size = 0; 6525 6526 if (BNXT_PAGE_SHIFT == 13) 6527 pg_size = 1 << 4; 6528 else if (BNXT_PAGE_SIZE == 16) 6529 pg_size = 2 << 4; 6530 6531 *pg_attr = pg_size; 6532 if (rmem->depth >= 1) { 6533 if (rmem->depth == 2) 6534 *pg_attr |= 2; 6535 else 6536 *pg_attr |= 1; 6537 *pg_dir = cpu_to_le64(rmem->pg_tbl_map); 6538 } else { 6539 *pg_dir = cpu_to_le64(rmem->dma_arr[0]); 6540 } 6541 } 6542 6543 #define FUNC_BACKING_STORE_CFG_REQ_DFLT_ENABLES \ 6544 (FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP | \ 6545 FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ | \ 6546 FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ | \ 6547 FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC | \ 6548 FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT) 6549 6550 static int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, u32 enables) 6551 { 6552 struct hwrm_func_backing_store_cfg_input req = {0}; 6553 struct bnxt_ctx_mem_info *ctx = bp->ctx; 6554 struct bnxt_ctx_pg_info *ctx_pg; 6555 __le32 *num_entries; 6556 __le64 *pg_dir; 6557 u32 flags = 0; 6558 u8 *pg_attr; 6559 u32 ena; 6560 int i; 6561 6562 if (!ctx) 6563 return 0; 6564 6565 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_BACKING_STORE_CFG, -1, -1); 6566 req.enables = cpu_to_le32(enables); 6567 6568 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP) { 6569 ctx_pg = &ctx->qp_mem; 6570 req.qp_num_entries = cpu_to_le32(ctx_pg->entries); 6571 req.qp_num_qp1_entries = cpu_to_le16(ctx->qp_min_qp1_entries); 6572 req.qp_num_l2_entries = cpu_to_le16(ctx->qp_max_l2_entries); 6573 req.qp_entry_size = cpu_to_le16(ctx->qp_entry_size); 6574 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, 6575 &req.qpc_pg_size_qpc_lvl, 6576 &req.qpc_page_dir); 6577 } 6578 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ) { 6579 ctx_pg = &ctx->srq_mem; 6580 req.srq_num_entries = cpu_to_le32(ctx_pg->entries); 6581 req.srq_num_l2_entries = cpu_to_le16(ctx->srq_max_l2_entries); 6582 req.srq_entry_size = cpu_to_le16(ctx->srq_entry_size); 6583 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, 6584 &req.srq_pg_size_srq_lvl, 6585 &req.srq_page_dir); 6586 } 6587 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ) { 6588 ctx_pg = &ctx->cq_mem; 6589 req.cq_num_entries = cpu_to_le32(ctx_pg->entries); 6590 req.cq_num_l2_entries = cpu_to_le16(ctx->cq_max_l2_entries); 6591 req.cq_entry_size = cpu_to_le16(ctx->cq_entry_size); 6592 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, &req.cq_pg_size_cq_lvl, 6593 &req.cq_page_dir); 6594 } 6595 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC) { 6596 ctx_pg = &ctx->vnic_mem; 6597 req.vnic_num_vnic_entries = 6598 cpu_to_le16(ctx->vnic_max_vnic_entries); 6599 req.vnic_num_ring_table_entries = 6600 cpu_to_le16(ctx->vnic_max_ring_table_entries); 6601 req.vnic_entry_size = cpu_to_le16(ctx->vnic_entry_size); 6602 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, 6603 &req.vnic_pg_size_vnic_lvl, 6604 &req.vnic_page_dir); 6605 } 6606 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT) { 6607 ctx_pg = &ctx->stat_mem; 6608 req.stat_num_entries = cpu_to_le32(ctx->stat_max_entries); 6609 req.stat_entry_size = cpu_to_le16(ctx->stat_entry_size); 6610 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, 6611 &req.stat_pg_size_stat_lvl, 6612 &req.stat_page_dir); 6613 } 6614 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV) { 6615 ctx_pg = &ctx->mrav_mem; 6616 req.mrav_num_entries = cpu_to_le32(ctx_pg->entries); 6617 if (ctx->mrav_num_entries_units) 6618 flags |= 6619 FUNC_BACKING_STORE_CFG_REQ_FLAGS_MRAV_RESERVATION_SPLIT; 6620 req.mrav_entry_size = cpu_to_le16(ctx->mrav_entry_size); 6621 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, 6622 &req.mrav_pg_size_mrav_lvl, 6623 &req.mrav_page_dir); 6624 } 6625 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM) { 6626 ctx_pg = &ctx->tim_mem; 6627 req.tim_num_entries = cpu_to_le32(ctx_pg->entries); 6628 req.tim_entry_size = cpu_to_le16(ctx->tim_entry_size); 6629 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, 6630 &req.tim_pg_size_tim_lvl, 6631 &req.tim_page_dir); 6632 } 6633 for (i = 0, num_entries = &req.tqm_sp_num_entries, 6634 pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl, 6635 pg_dir = &req.tqm_sp_page_dir, 6636 ena = FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP; 6637 i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) { 6638 if (!(enables & ena)) 6639 continue; 6640 6641 req.tqm_entry_size = cpu_to_le16(ctx->tqm_entry_size); 6642 ctx_pg = ctx->tqm_mem[i]; 6643 *num_entries = cpu_to_le32(ctx_pg->entries); 6644 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir); 6645 } 6646 req.flags = cpu_to_le32(flags); 6647 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 6648 } 6649 6650 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp, 6651 struct bnxt_ctx_pg_info *ctx_pg) 6652 { 6653 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem; 6654 6655 rmem->page_size = BNXT_PAGE_SIZE; 6656 rmem->pg_arr = ctx_pg->ctx_pg_arr; 6657 rmem->dma_arr = ctx_pg->ctx_dma_arr; 6658 rmem->flags = BNXT_RMEM_VALID_PTE_FLAG; 6659 if (rmem->depth >= 1) 6660 rmem->flags |= BNXT_RMEM_USE_FULL_PAGE_FLAG; 6661 return bnxt_alloc_ring(bp, rmem); 6662 } 6663 6664 static int bnxt_alloc_ctx_pg_tbls(struct bnxt *bp, 6665 struct bnxt_ctx_pg_info *ctx_pg, u32 mem_size, 6666 u8 depth, bool use_init_val) 6667 { 6668 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem; 6669 int rc; 6670 6671 if (!mem_size) 6672 return -EINVAL; 6673 6674 ctx_pg->nr_pages = DIV_ROUND_UP(mem_size, BNXT_PAGE_SIZE); 6675 if (ctx_pg->nr_pages > MAX_CTX_TOTAL_PAGES) { 6676 ctx_pg->nr_pages = 0; 6677 return -EINVAL; 6678 } 6679 if (ctx_pg->nr_pages > MAX_CTX_PAGES || depth > 1) { 6680 int nr_tbls, i; 6681 6682 rmem->depth = 2; 6683 ctx_pg->ctx_pg_tbl = kcalloc(MAX_CTX_PAGES, sizeof(ctx_pg), 6684 GFP_KERNEL); 6685 if (!ctx_pg->ctx_pg_tbl) 6686 return -ENOMEM; 6687 nr_tbls = DIV_ROUND_UP(ctx_pg->nr_pages, MAX_CTX_PAGES); 6688 rmem->nr_pages = nr_tbls; 6689 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg); 6690 if (rc) 6691 return rc; 6692 for (i = 0; i < nr_tbls; i++) { 6693 struct bnxt_ctx_pg_info *pg_tbl; 6694 6695 pg_tbl = kzalloc(sizeof(*pg_tbl), GFP_KERNEL); 6696 if (!pg_tbl) 6697 return -ENOMEM; 6698 ctx_pg->ctx_pg_tbl[i] = pg_tbl; 6699 rmem = &pg_tbl->ring_mem; 6700 rmem->pg_tbl = ctx_pg->ctx_pg_arr[i]; 6701 rmem->pg_tbl_map = ctx_pg->ctx_dma_arr[i]; 6702 rmem->depth = 1; 6703 rmem->nr_pages = MAX_CTX_PAGES; 6704 if (use_init_val) 6705 rmem->init_val = bp->ctx->ctx_kind_initializer; 6706 if (i == (nr_tbls - 1)) { 6707 int rem = ctx_pg->nr_pages % MAX_CTX_PAGES; 6708 6709 if (rem) 6710 rmem->nr_pages = rem; 6711 } 6712 rc = bnxt_alloc_ctx_mem_blk(bp, pg_tbl); 6713 if (rc) 6714 break; 6715 } 6716 } else { 6717 rmem->nr_pages = DIV_ROUND_UP(mem_size, BNXT_PAGE_SIZE); 6718 if (rmem->nr_pages > 1 || depth) 6719 rmem->depth = 1; 6720 if (use_init_val) 6721 rmem->init_val = bp->ctx->ctx_kind_initializer; 6722 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg); 6723 } 6724 return rc; 6725 } 6726 6727 static void bnxt_free_ctx_pg_tbls(struct bnxt *bp, 6728 struct bnxt_ctx_pg_info *ctx_pg) 6729 { 6730 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem; 6731 6732 if (rmem->depth > 1 || ctx_pg->nr_pages > MAX_CTX_PAGES || 6733 ctx_pg->ctx_pg_tbl) { 6734 int i, nr_tbls = rmem->nr_pages; 6735 6736 for (i = 0; i < nr_tbls; i++) { 6737 struct bnxt_ctx_pg_info *pg_tbl; 6738 struct bnxt_ring_mem_info *rmem2; 6739 6740 pg_tbl = ctx_pg->ctx_pg_tbl[i]; 6741 if (!pg_tbl) 6742 continue; 6743 rmem2 = &pg_tbl->ring_mem; 6744 bnxt_free_ring(bp, rmem2); 6745 ctx_pg->ctx_pg_arr[i] = NULL; 6746 kfree(pg_tbl); 6747 ctx_pg->ctx_pg_tbl[i] = NULL; 6748 } 6749 kfree(ctx_pg->ctx_pg_tbl); 6750 ctx_pg->ctx_pg_tbl = NULL; 6751 } 6752 bnxt_free_ring(bp, rmem); 6753 ctx_pg->nr_pages = 0; 6754 } 6755 6756 static void bnxt_free_ctx_mem(struct bnxt *bp) 6757 { 6758 struct bnxt_ctx_mem_info *ctx = bp->ctx; 6759 int i; 6760 6761 if (!ctx) 6762 return; 6763 6764 if (ctx->tqm_mem[0]) { 6765 for (i = 0; i < ctx->tqm_fp_rings_count + 1; i++) 6766 bnxt_free_ctx_pg_tbls(bp, ctx->tqm_mem[i]); 6767 kfree(ctx->tqm_mem[0]); 6768 ctx->tqm_mem[0] = NULL; 6769 } 6770 6771 bnxt_free_ctx_pg_tbls(bp, &ctx->tim_mem); 6772 bnxt_free_ctx_pg_tbls(bp, &ctx->mrav_mem); 6773 bnxt_free_ctx_pg_tbls(bp, &ctx->stat_mem); 6774 bnxt_free_ctx_pg_tbls(bp, &ctx->vnic_mem); 6775 bnxt_free_ctx_pg_tbls(bp, &ctx->cq_mem); 6776 bnxt_free_ctx_pg_tbls(bp, &ctx->srq_mem); 6777 bnxt_free_ctx_pg_tbls(bp, &ctx->qp_mem); 6778 ctx->flags &= ~BNXT_CTX_FLAG_INITED; 6779 } 6780 6781 static int bnxt_alloc_ctx_mem(struct bnxt *bp) 6782 { 6783 struct bnxt_ctx_pg_info *ctx_pg; 6784 struct bnxt_ctx_mem_info *ctx; 6785 u32 mem_size, ena, entries; 6786 u32 entries_sp, min; 6787 u32 num_mr, num_ah; 6788 u32 extra_srqs = 0; 6789 u32 extra_qps = 0; 6790 u8 pg_lvl = 1; 6791 int i, rc; 6792 6793 rc = bnxt_hwrm_func_backing_store_qcaps(bp); 6794 if (rc) { 6795 netdev_err(bp->dev, "Failed querying context mem capability, rc = %d.\n", 6796 rc); 6797 return rc; 6798 } 6799 ctx = bp->ctx; 6800 if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED)) 6801 return 0; 6802 6803 if ((bp->flags & BNXT_FLAG_ROCE_CAP) && !is_kdump_kernel()) { 6804 pg_lvl = 2; 6805 extra_qps = 65536; 6806 extra_srqs = 8192; 6807 } 6808 6809 ctx_pg = &ctx->qp_mem; 6810 ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries + 6811 extra_qps; 6812 mem_size = ctx->qp_entry_size * ctx_pg->entries; 6813 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, pg_lvl, true); 6814 if (rc) 6815 return rc; 6816 6817 ctx_pg = &ctx->srq_mem; 6818 ctx_pg->entries = ctx->srq_max_l2_entries + extra_srqs; 6819 mem_size = ctx->srq_entry_size * ctx_pg->entries; 6820 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, pg_lvl, true); 6821 if (rc) 6822 return rc; 6823 6824 ctx_pg = &ctx->cq_mem; 6825 ctx_pg->entries = ctx->cq_max_l2_entries + extra_qps * 2; 6826 mem_size = ctx->cq_entry_size * ctx_pg->entries; 6827 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, pg_lvl, true); 6828 if (rc) 6829 return rc; 6830 6831 ctx_pg = &ctx->vnic_mem; 6832 ctx_pg->entries = ctx->vnic_max_vnic_entries + 6833 ctx->vnic_max_ring_table_entries; 6834 mem_size = ctx->vnic_entry_size * ctx_pg->entries; 6835 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1, true); 6836 if (rc) 6837 return rc; 6838 6839 ctx_pg = &ctx->stat_mem; 6840 ctx_pg->entries = ctx->stat_max_entries; 6841 mem_size = ctx->stat_entry_size * ctx_pg->entries; 6842 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1, true); 6843 if (rc) 6844 return rc; 6845 6846 ena = 0; 6847 if (!(bp->flags & BNXT_FLAG_ROCE_CAP)) 6848 goto skip_rdma; 6849 6850 ctx_pg = &ctx->mrav_mem; 6851 /* 128K extra is needed to accommodate static AH context 6852 * allocation by f/w. 6853 */ 6854 num_mr = 1024 * 256; 6855 num_ah = 1024 * 128; 6856 ctx_pg->entries = num_mr + num_ah; 6857 mem_size = ctx->mrav_entry_size * ctx_pg->entries; 6858 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 2, true); 6859 if (rc) 6860 return rc; 6861 ena = FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV; 6862 if (ctx->mrav_num_entries_units) 6863 ctx_pg->entries = 6864 ((num_mr / ctx->mrav_num_entries_units) << 16) | 6865 (num_ah / ctx->mrav_num_entries_units); 6866 6867 ctx_pg = &ctx->tim_mem; 6868 ctx_pg->entries = ctx->qp_mem.entries; 6869 mem_size = ctx->tim_entry_size * ctx_pg->entries; 6870 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1, false); 6871 if (rc) 6872 return rc; 6873 ena |= FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM; 6874 6875 skip_rdma: 6876 min = ctx->tqm_min_entries_per_ring; 6877 entries_sp = ctx->vnic_max_vnic_entries + ctx->qp_max_l2_entries + 6878 2 * (extra_qps + ctx->qp_min_qp1_entries) + min; 6879 entries_sp = roundup(entries_sp, ctx->tqm_entries_multiple); 6880 entries = ctx->qp_max_l2_entries + extra_qps + ctx->qp_min_qp1_entries; 6881 entries = roundup(entries, ctx->tqm_entries_multiple); 6882 entries = clamp_t(u32, entries, min, ctx->tqm_max_entries_per_ring); 6883 for (i = 0; i < ctx->tqm_fp_rings_count + 1; i++) { 6884 ctx_pg = ctx->tqm_mem[i]; 6885 ctx_pg->entries = i ? entries : entries_sp; 6886 mem_size = ctx->tqm_entry_size * ctx_pg->entries; 6887 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1, false); 6888 if (rc) 6889 return rc; 6890 ena |= FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP << i; 6891 } 6892 ena |= FUNC_BACKING_STORE_CFG_REQ_DFLT_ENABLES; 6893 rc = bnxt_hwrm_func_backing_store_cfg(bp, ena); 6894 if (rc) { 6895 netdev_err(bp->dev, "Failed configuring context mem, rc = %d.\n", 6896 rc); 6897 return rc; 6898 } 6899 ctx->flags |= BNXT_CTX_FLAG_INITED; 6900 return 0; 6901 } 6902 6903 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp, bool all) 6904 { 6905 struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr; 6906 struct hwrm_func_resource_qcaps_input req = {0}; 6907 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 6908 int rc; 6909 6910 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESOURCE_QCAPS, -1, -1); 6911 req.fid = cpu_to_le16(0xffff); 6912 6913 mutex_lock(&bp->hwrm_cmd_lock); 6914 rc = _hwrm_send_message_silent(bp, &req, sizeof(req), 6915 HWRM_CMD_TIMEOUT); 6916 if (rc) 6917 goto hwrm_func_resc_qcaps_exit; 6918 6919 hw_resc->max_tx_sch_inputs = le16_to_cpu(resp->max_tx_scheduler_inputs); 6920 if (!all) 6921 goto hwrm_func_resc_qcaps_exit; 6922 6923 hw_resc->min_rsscos_ctxs = le16_to_cpu(resp->min_rsscos_ctx); 6924 hw_resc->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx); 6925 hw_resc->min_cp_rings = le16_to_cpu(resp->min_cmpl_rings); 6926 hw_resc->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings); 6927 hw_resc->min_tx_rings = le16_to_cpu(resp->min_tx_rings); 6928 hw_resc->max_tx_rings = le16_to_cpu(resp->max_tx_rings); 6929 hw_resc->min_rx_rings = le16_to_cpu(resp->min_rx_rings); 6930 hw_resc->max_rx_rings = le16_to_cpu(resp->max_rx_rings); 6931 hw_resc->min_hw_ring_grps = le16_to_cpu(resp->min_hw_ring_grps); 6932 hw_resc->max_hw_ring_grps = le16_to_cpu(resp->max_hw_ring_grps); 6933 hw_resc->min_l2_ctxs = le16_to_cpu(resp->min_l2_ctxs); 6934 hw_resc->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs); 6935 hw_resc->min_vnics = le16_to_cpu(resp->min_vnics); 6936 hw_resc->max_vnics = le16_to_cpu(resp->max_vnics); 6937 hw_resc->min_stat_ctxs = le16_to_cpu(resp->min_stat_ctx); 6938 hw_resc->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx); 6939 6940 if (bp->flags & BNXT_FLAG_CHIP_P5) { 6941 u16 max_msix = le16_to_cpu(resp->max_msix); 6942 6943 hw_resc->max_nqs = max_msix; 6944 hw_resc->max_hw_ring_grps = hw_resc->max_rx_rings; 6945 } 6946 6947 if (BNXT_PF(bp)) { 6948 struct bnxt_pf_info *pf = &bp->pf; 6949 6950 pf->vf_resv_strategy = 6951 le16_to_cpu(resp->vf_reservation_strategy); 6952 if (pf->vf_resv_strategy > BNXT_VF_RESV_STRATEGY_MINIMAL_STATIC) 6953 pf->vf_resv_strategy = BNXT_VF_RESV_STRATEGY_MAXIMAL; 6954 } 6955 hwrm_func_resc_qcaps_exit: 6956 mutex_unlock(&bp->hwrm_cmd_lock); 6957 return rc; 6958 } 6959 6960 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp) 6961 { 6962 int rc = 0; 6963 struct hwrm_func_qcaps_input req = {0}; 6964 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr; 6965 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 6966 u32 flags; 6967 6968 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCAPS, -1, -1); 6969 req.fid = cpu_to_le16(0xffff); 6970 6971 mutex_lock(&bp->hwrm_cmd_lock); 6972 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 6973 if (rc) 6974 goto hwrm_func_qcaps_exit; 6975 6976 flags = le32_to_cpu(resp->flags); 6977 if (flags & FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED) 6978 bp->flags |= BNXT_FLAG_ROCEV1_CAP; 6979 if (flags & FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED) 6980 bp->flags |= BNXT_FLAG_ROCEV2_CAP; 6981 if (flags & FUNC_QCAPS_RESP_FLAGS_PCIE_STATS_SUPPORTED) 6982 bp->fw_cap |= BNXT_FW_CAP_PCIE_STATS_SUPPORTED; 6983 if (flags & FUNC_QCAPS_RESP_FLAGS_HOT_RESET_CAPABLE) 6984 bp->fw_cap |= BNXT_FW_CAP_HOT_RESET; 6985 if (flags & FUNC_QCAPS_RESP_FLAGS_EXT_STATS_SUPPORTED) 6986 bp->fw_cap |= BNXT_FW_CAP_EXT_STATS_SUPPORTED; 6987 if (flags & FUNC_QCAPS_RESP_FLAGS_ERROR_RECOVERY_CAPABLE) 6988 bp->fw_cap |= BNXT_FW_CAP_ERROR_RECOVERY; 6989 if (flags & FUNC_QCAPS_RESP_FLAGS_ERR_RECOVER_RELOAD) 6990 bp->fw_cap |= BNXT_FW_CAP_ERR_RECOVER_RELOAD; 6991 6992 bp->tx_push_thresh = 0; 6993 if ((flags & FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED) && 6994 BNXT_FW_MAJ(bp) > 217) 6995 bp->tx_push_thresh = BNXT_TX_PUSH_THRESH; 6996 6997 hw_resc->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx); 6998 hw_resc->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings); 6999 hw_resc->max_tx_rings = le16_to_cpu(resp->max_tx_rings); 7000 hw_resc->max_rx_rings = le16_to_cpu(resp->max_rx_rings); 7001 hw_resc->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps); 7002 if (!hw_resc->max_hw_ring_grps) 7003 hw_resc->max_hw_ring_grps = hw_resc->max_tx_rings; 7004 hw_resc->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs); 7005 hw_resc->max_vnics = le16_to_cpu(resp->max_vnics); 7006 hw_resc->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx); 7007 7008 if (BNXT_PF(bp)) { 7009 struct bnxt_pf_info *pf = &bp->pf; 7010 7011 pf->fw_fid = le16_to_cpu(resp->fid); 7012 pf->port_id = le16_to_cpu(resp->port_id); 7013 memcpy(pf->mac_addr, resp->mac_address, ETH_ALEN); 7014 pf->first_vf_id = le16_to_cpu(resp->first_vf_id); 7015 pf->max_vfs = le16_to_cpu(resp->max_vfs); 7016 pf->max_encap_records = le32_to_cpu(resp->max_encap_records); 7017 pf->max_decap_records = le32_to_cpu(resp->max_decap_records); 7018 pf->max_tx_em_flows = le32_to_cpu(resp->max_tx_em_flows); 7019 pf->max_tx_wm_flows = le32_to_cpu(resp->max_tx_wm_flows); 7020 pf->max_rx_em_flows = le32_to_cpu(resp->max_rx_em_flows); 7021 pf->max_rx_wm_flows = le32_to_cpu(resp->max_rx_wm_flows); 7022 bp->flags &= ~BNXT_FLAG_WOL_CAP; 7023 if (flags & FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED) 7024 bp->flags |= BNXT_FLAG_WOL_CAP; 7025 } else { 7026 #ifdef CONFIG_BNXT_SRIOV 7027 struct bnxt_vf_info *vf = &bp->vf; 7028 7029 vf->fw_fid = le16_to_cpu(resp->fid); 7030 memcpy(vf->mac_addr, resp->mac_address, ETH_ALEN); 7031 #endif 7032 } 7033 7034 hwrm_func_qcaps_exit: 7035 mutex_unlock(&bp->hwrm_cmd_lock); 7036 return rc; 7037 } 7038 7039 static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp); 7040 7041 static int bnxt_hwrm_func_qcaps(struct bnxt *bp) 7042 { 7043 int rc; 7044 7045 rc = __bnxt_hwrm_func_qcaps(bp); 7046 if (rc) 7047 return rc; 7048 rc = bnxt_hwrm_queue_qportcfg(bp); 7049 if (rc) { 7050 netdev_err(bp->dev, "hwrm query qportcfg failure rc: %d\n", rc); 7051 return rc; 7052 } 7053 if (bp->hwrm_spec_code >= 0x10803) { 7054 rc = bnxt_alloc_ctx_mem(bp); 7055 if (rc) 7056 return rc; 7057 rc = bnxt_hwrm_func_resc_qcaps(bp, true); 7058 if (!rc) 7059 bp->fw_cap |= BNXT_FW_CAP_NEW_RM; 7060 } 7061 return 0; 7062 } 7063 7064 static int bnxt_hwrm_cfa_adv_flow_mgnt_qcaps(struct bnxt *bp) 7065 { 7066 struct hwrm_cfa_adv_flow_mgnt_qcaps_input req = {0}; 7067 struct hwrm_cfa_adv_flow_mgnt_qcaps_output *resp; 7068 int rc = 0; 7069 u32 flags; 7070 7071 if (!(bp->fw_cap & BNXT_FW_CAP_CFA_ADV_FLOW)) 7072 return 0; 7073 7074 resp = bp->hwrm_cmd_resp_addr; 7075 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_ADV_FLOW_MGNT_QCAPS, -1, -1); 7076 7077 mutex_lock(&bp->hwrm_cmd_lock); 7078 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 7079 if (rc) 7080 goto hwrm_cfa_adv_qcaps_exit; 7081 7082 flags = le32_to_cpu(resp->flags); 7083 if (flags & 7084 CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RFS_RING_TBL_IDX_V2_SUPPORTED) 7085 bp->fw_cap |= BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V2; 7086 7087 hwrm_cfa_adv_qcaps_exit: 7088 mutex_unlock(&bp->hwrm_cmd_lock); 7089 return rc; 7090 } 7091 7092 static int bnxt_map_fw_health_regs(struct bnxt *bp) 7093 { 7094 struct bnxt_fw_health *fw_health = bp->fw_health; 7095 u32 reg_base = 0xffffffff; 7096 int i; 7097 7098 /* Only pre-map the monitoring GRC registers using window 3 */ 7099 for (i = 0; i < 4; i++) { 7100 u32 reg = fw_health->regs[i]; 7101 7102 if (BNXT_FW_HEALTH_REG_TYPE(reg) != BNXT_FW_HEALTH_REG_TYPE_GRC) 7103 continue; 7104 if (reg_base == 0xffffffff) 7105 reg_base = reg & BNXT_GRC_BASE_MASK; 7106 if ((reg & BNXT_GRC_BASE_MASK) != reg_base) 7107 return -ERANGE; 7108 fw_health->mapped_regs[i] = BNXT_FW_HEALTH_WIN_BASE + 7109 (reg & BNXT_GRC_OFFSET_MASK); 7110 } 7111 if (reg_base == 0xffffffff) 7112 return 0; 7113 7114 writel(reg_base, bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 7115 BNXT_FW_HEALTH_WIN_MAP_OFF); 7116 return 0; 7117 } 7118 7119 static int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp) 7120 { 7121 struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr; 7122 struct bnxt_fw_health *fw_health = bp->fw_health; 7123 struct hwrm_error_recovery_qcfg_input req = {0}; 7124 int rc, i; 7125 7126 if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)) 7127 return 0; 7128 7129 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_ERROR_RECOVERY_QCFG, -1, -1); 7130 mutex_lock(&bp->hwrm_cmd_lock); 7131 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 7132 if (rc) 7133 goto err_recovery_out; 7134 fw_health->flags = le32_to_cpu(resp->flags); 7135 if ((fw_health->flags & ERROR_RECOVERY_QCFG_RESP_FLAGS_CO_CPU) && 7136 !(bp->fw_cap & BNXT_FW_CAP_KONG_MB_CHNL)) { 7137 rc = -EINVAL; 7138 goto err_recovery_out; 7139 } 7140 fw_health->polling_dsecs = le32_to_cpu(resp->driver_polling_freq); 7141 fw_health->master_func_wait_dsecs = 7142 le32_to_cpu(resp->master_func_wait_period); 7143 fw_health->normal_func_wait_dsecs = 7144 le32_to_cpu(resp->normal_func_wait_period); 7145 fw_health->post_reset_wait_dsecs = 7146 le32_to_cpu(resp->master_func_wait_period_after_reset); 7147 fw_health->post_reset_max_wait_dsecs = 7148 le32_to_cpu(resp->max_bailout_time_after_reset); 7149 fw_health->regs[BNXT_FW_HEALTH_REG] = 7150 le32_to_cpu(resp->fw_health_status_reg); 7151 fw_health->regs[BNXT_FW_HEARTBEAT_REG] = 7152 le32_to_cpu(resp->fw_heartbeat_reg); 7153 fw_health->regs[BNXT_FW_RESET_CNT_REG] = 7154 le32_to_cpu(resp->fw_reset_cnt_reg); 7155 fw_health->regs[BNXT_FW_RESET_INPROG_REG] = 7156 le32_to_cpu(resp->reset_inprogress_reg); 7157 fw_health->fw_reset_inprog_reg_mask = 7158 le32_to_cpu(resp->reset_inprogress_reg_mask); 7159 fw_health->fw_reset_seq_cnt = resp->reg_array_cnt; 7160 if (fw_health->fw_reset_seq_cnt >= 16) { 7161 rc = -EINVAL; 7162 goto err_recovery_out; 7163 } 7164 for (i = 0; i < fw_health->fw_reset_seq_cnt; i++) { 7165 fw_health->fw_reset_seq_regs[i] = 7166 le32_to_cpu(resp->reset_reg[i]); 7167 fw_health->fw_reset_seq_vals[i] = 7168 le32_to_cpu(resp->reset_reg_val[i]); 7169 fw_health->fw_reset_seq_delay_msec[i] = 7170 resp->delay_after_reset[i]; 7171 } 7172 err_recovery_out: 7173 mutex_unlock(&bp->hwrm_cmd_lock); 7174 if (!rc) 7175 rc = bnxt_map_fw_health_regs(bp); 7176 if (rc) 7177 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY; 7178 return rc; 7179 } 7180 7181 static int bnxt_hwrm_func_reset(struct bnxt *bp) 7182 { 7183 struct hwrm_func_reset_input req = {0}; 7184 7185 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESET, -1, -1); 7186 req.enables = 0; 7187 7188 return hwrm_send_message(bp, &req, sizeof(req), HWRM_RESET_TIMEOUT); 7189 } 7190 7191 static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp) 7192 { 7193 int rc = 0; 7194 struct hwrm_queue_qportcfg_input req = {0}; 7195 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr; 7196 u8 i, j, *qptr; 7197 bool no_rdma; 7198 7199 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_QUEUE_QPORTCFG, -1, -1); 7200 7201 mutex_lock(&bp->hwrm_cmd_lock); 7202 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 7203 if (rc) 7204 goto qportcfg_exit; 7205 7206 if (!resp->max_configurable_queues) { 7207 rc = -EINVAL; 7208 goto qportcfg_exit; 7209 } 7210 bp->max_tc = resp->max_configurable_queues; 7211 bp->max_lltc = resp->max_configurable_lossless_queues; 7212 if (bp->max_tc > BNXT_MAX_QUEUE) 7213 bp->max_tc = BNXT_MAX_QUEUE; 7214 7215 no_rdma = !(bp->flags & BNXT_FLAG_ROCE_CAP); 7216 qptr = &resp->queue_id0; 7217 for (i = 0, j = 0; i < bp->max_tc; i++) { 7218 bp->q_info[j].queue_id = *qptr; 7219 bp->q_ids[i] = *qptr++; 7220 bp->q_info[j].queue_profile = *qptr++; 7221 bp->tc_to_qidx[j] = j; 7222 if (!BNXT_CNPQ(bp->q_info[j].queue_profile) || 7223 (no_rdma && BNXT_PF(bp))) 7224 j++; 7225 } 7226 bp->max_q = bp->max_tc; 7227 bp->max_tc = max_t(u8, j, 1); 7228 7229 if (resp->queue_cfg_info & QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG) 7230 bp->max_tc = 1; 7231 7232 if (bp->max_lltc > bp->max_tc) 7233 bp->max_lltc = bp->max_tc; 7234 7235 qportcfg_exit: 7236 mutex_unlock(&bp->hwrm_cmd_lock); 7237 return rc; 7238 } 7239 7240 static int __bnxt_hwrm_ver_get(struct bnxt *bp, bool silent) 7241 { 7242 struct hwrm_ver_get_input req = {0}; 7243 int rc; 7244 7245 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VER_GET, -1, -1); 7246 req.hwrm_intf_maj = HWRM_VERSION_MAJOR; 7247 req.hwrm_intf_min = HWRM_VERSION_MINOR; 7248 req.hwrm_intf_upd = HWRM_VERSION_UPDATE; 7249 7250 rc = bnxt_hwrm_do_send_msg(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT, 7251 silent); 7252 return rc; 7253 } 7254 7255 static int bnxt_hwrm_ver_get(struct bnxt *bp) 7256 { 7257 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr; 7258 u16 fw_maj, fw_min, fw_bld, fw_rsv; 7259 u32 dev_caps_cfg, hwrm_ver; 7260 int rc, len; 7261 7262 bp->hwrm_max_req_len = HWRM_MAX_REQ_LEN; 7263 mutex_lock(&bp->hwrm_cmd_lock); 7264 rc = __bnxt_hwrm_ver_get(bp, false); 7265 if (rc) 7266 goto hwrm_ver_get_exit; 7267 7268 memcpy(&bp->ver_resp, resp, sizeof(struct hwrm_ver_get_output)); 7269 7270 bp->hwrm_spec_code = resp->hwrm_intf_maj_8b << 16 | 7271 resp->hwrm_intf_min_8b << 8 | 7272 resp->hwrm_intf_upd_8b; 7273 if (resp->hwrm_intf_maj_8b < 1) { 7274 netdev_warn(bp->dev, "HWRM interface %d.%d.%d is older than 1.0.0.\n", 7275 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b, 7276 resp->hwrm_intf_upd_8b); 7277 netdev_warn(bp->dev, "Please update firmware with HWRM interface 1.0.0 or newer.\n"); 7278 } 7279 7280 hwrm_ver = HWRM_VERSION_MAJOR << 16 | HWRM_VERSION_MINOR << 8 | 7281 HWRM_VERSION_UPDATE; 7282 7283 if (bp->hwrm_spec_code > hwrm_ver) 7284 snprintf(bp->hwrm_ver_supp, FW_VER_STR_LEN, "%d.%d.%d", 7285 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, 7286 HWRM_VERSION_UPDATE); 7287 else 7288 snprintf(bp->hwrm_ver_supp, FW_VER_STR_LEN, "%d.%d.%d", 7289 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b, 7290 resp->hwrm_intf_upd_8b); 7291 7292 fw_maj = le16_to_cpu(resp->hwrm_fw_major); 7293 if (bp->hwrm_spec_code > 0x10803 && fw_maj) { 7294 fw_min = le16_to_cpu(resp->hwrm_fw_minor); 7295 fw_bld = le16_to_cpu(resp->hwrm_fw_build); 7296 fw_rsv = le16_to_cpu(resp->hwrm_fw_patch); 7297 len = FW_VER_STR_LEN; 7298 } else { 7299 fw_maj = resp->hwrm_fw_maj_8b; 7300 fw_min = resp->hwrm_fw_min_8b; 7301 fw_bld = resp->hwrm_fw_bld_8b; 7302 fw_rsv = resp->hwrm_fw_rsvd_8b; 7303 len = BC_HWRM_STR_LEN; 7304 } 7305 bp->fw_ver_code = BNXT_FW_VER_CODE(fw_maj, fw_min, fw_bld, fw_rsv); 7306 snprintf(bp->fw_ver_str, len, "%d.%d.%d.%d", fw_maj, fw_min, fw_bld, 7307 fw_rsv); 7308 7309 if (strlen(resp->active_pkg_name)) { 7310 int fw_ver_len = strlen(bp->fw_ver_str); 7311 7312 snprintf(bp->fw_ver_str + fw_ver_len, 7313 FW_VER_STR_LEN - fw_ver_len - 1, "/pkg %s", 7314 resp->active_pkg_name); 7315 bp->fw_cap |= BNXT_FW_CAP_PKG_VER; 7316 } 7317 7318 bp->hwrm_cmd_timeout = le16_to_cpu(resp->def_req_timeout); 7319 if (!bp->hwrm_cmd_timeout) 7320 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT; 7321 7322 if (resp->hwrm_intf_maj_8b >= 1) { 7323 bp->hwrm_max_req_len = le16_to_cpu(resp->max_req_win_len); 7324 bp->hwrm_max_ext_req_len = le16_to_cpu(resp->max_ext_req_len); 7325 } 7326 if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN) 7327 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN; 7328 7329 bp->chip_num = le16_to_cpu(resp->chip_num); 7330 bp->chip_rev = resp->chip_rev; 7331 if (bp->chip_num == CHIP_NUM_58700 && !resp->chip_rev && 7332 !resp->chip_metal) 7333 bp->flags |= BNXT_FLAG_CHIP_NITRO_A0; 7334 7335 dev_caps_cfg = le32_to_cpu(resp->dev_caps_cfg); 7336 if ((dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) && 7337 (dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) 7338 bp->fw_cap |= BNXT_FW_CAP_SHORT_CMD; 7339 7340 if (dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) 7341 bp->fw_cap |= BNXT_FW_CAP_KONG_MB_CHNL; 7342 7343 if (dev_caps_cfg & 7344 VER_GET_RESP_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED) 7345 bp->fw_cap |= BNXT_FW_CAP_OVS_64BIT_HANDLE; 7346 7347 if (dev_caps_cfg & 7348 VER_GET_RESP_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED) 7349 bp->fw_cap |= BNXT_FW_CAP_TRUSTED_VF; 7350 7351 if (dev_caps_cfg & 7352 VER_GET_RESP_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED) 7353 bp->fw_cap |= BNXT_FW_CAP_CFA_ADV_FLOW; 7354 7355 hwrm_ver_get_exit: 7356 mutex_unlock(&bp->hwrm_cmd_lock); 7357 return rc; 7358 } 7359 7360 int bnxt_hwrm_fw_set_time(struct bnxt *bp) 7361 { 7362 struct hwrm_fw_set_time_input req = {0}; 7363 struct tm tm; 7364 time64_t now = ktime_get_real_seconds(); 7365 7366 if ((BNXT_VF(bp) && bp->hwrm_spec_code < 0x10901) || 7367 bp->hwrm_spec_code < 0x10400) 7368 return -EOPNOTSUPP; 7369 7370 time64_to_tm(now, 0, &tm); 7371 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FW_SET_TIME, -1, -1); 7372 req.year = cpu_to_le16(1900 + tm.tm_year); 7373 req.month = 1 + tm.tm_mon; 7374 req.day = tm.tm_mday; 7375 req.hour = tm.tm_hour; 7376 req.minute = tm.tm_min; 7377 req.second = tm.tm_sec; 7378 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 7379 } 7380 7381 static int bnxt_hwrm_port_qstats(struct bnxt *bp) 7382 { 7383 struct bnxt_pf_info *pf = &bp->pf; 7384 struct hwrm_port_qstats_input req = {0}; 7385 7386 if (!(bp->flags & BNXT_FLAG_PORT_STATS)) 7387 return 0; 7388 7389 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_QSTATS, -1, -1); 7390 req.port_id = cpu_to_le16(pf->port_id); 7391 req.tx_stat_host_addr = cpu_to_le64(bp->hw_tx_port_stats_map); 7392 req.rx_stat_host_addr = cpu_to_le64(bp->hw_rx_port_stats_map); 7393 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 7394 } 7395 7396 static int bnxt_hwrm_port_qstats_ext(struct bnxt *bp) 7397 { 7398 struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr; 7399 struct hwrm_queue_pri2cos_qcfg_input req2 = {0}; 7400 struct hwrm_port_qstats_ext_input req = {0}; 7401 struct bnxt_pf_info *pf = &bp->pf; 7402 u32 tx_stat_size; 7403 int rc; 7404 7405 if (!(bp->flags & BNXT_FLAG_PORT_STATS_EXT)) 7406 return 0; 7407 7408 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_QSTATS_EXT, -1, -1); 7409 req.port_id = cpu_to_le16(pf->port_id); 7410 req.rx_stat_size = cpu_to_le16(sizeof(struct rx_port_stats_ext)); 7411 req.rx_stat_host_addr = cpu_to_le64(bp->hw_rx_port_stats_ext_map); 7412 tx_stat_size = bp->hw_tx_port_stats_ext ? 7413 sizeof(*bp->hw_tx_port_stats_ext) : 0; 7414 req.tx_stat_size = cpu_to_le16(tx_stat_size); 7415 req.tx_stat_host_addr = cpu_to_le64(bp->hw_tx_port_stats_ext_map); 7416 mutex_lock(&bp->hwrm_cmd_lock); 7417 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 7418 if (!rc) { 7419 bp->fw_rx_stats_ext_size = le16_to_cpu(resp->rx_stat_size) / 8; 7420 bp->fw_tx_stats_ext_size = tx_stat_size ? 7421 le16_to_cpu(resp->tx_stat_size) / 8 : 0; 7422 } else { 7423 bp->fw_rx_stats_ext_size = 0; 7424 bp->fw_tx_stats_ext_size = 0; 7425 } 7426 if (bp->fw_tx_stats_ext_size <= 7427 offsetof(struct tx_port_stats_ext, pfc_pri0_tx_duration_us) / 8) { 7428 mutex_unlock(&bp->hwrm_cmd_lock); 7429 bp->pri2cos_valid = 0; 7430 return rc; 7431 } 7432 7433 bnxt_hwrm_cmd_hdr_init(bp, &req2, HWRM_QUEUE_PRI2COS_QCFG, -1, -1); 7434 req2.flags = cpu_to_le32(QUEUE_PRI2COS_QCFG_REQ_FLAGS_IVLAN); 7435 7436 rc = _hwrm_send_message(bp, &req2, sizeof(req2), HWRM_CMD_TIMEOUT); 7437 if (!rc) { 7438 struct hwrm_queue_pri2cos_qcfg_output *resp2; 7439 u8 *pri2cos; 7440 int i, j; 7441 7442 resp2 = bp->hwrm_cmd_resp_addr; 7443 pri2cos = &resp2->pri0_cos_queue_id; 7444 for (i = 0; i < 8; i++) { 7445 u8 queue_id = pri2cos[i]; 7446 u8 queue_idx; 7447 7448 /* Per port queue IDs start from 0, 10, 20, etc */ 7449 queue_idx = queue_id % 10; 7450 if (queue_idx > BNXT_MAX_QUEUE) { 7451 bp->pri2cos_valid = false; 7452 goto qstats_done; 7453 } 7454 for (j = 0; j < bp->max_q; j++) { 7455 if (bp->q_ids[j] == queue_id) 7456 bp->pri2cos_idx[i] = queue_idx; 7457 } 7458 } 7459 bp->pri2cos_valid = 1; 7460 } 7461 qstats_done: 7462 mutex_unlock(&bp->hwrm_cmd_lock); 7463 return rc; 7464 } 7465 7466 static int bnxt_hwrm_pcie_qstats(struct bnxt *bp) 7467 { 7468 struct hwrm_pcie_qstats_input req = {0}; 7469 7470 if (!(bp->flags & BNXT_FLAG_PCIE_STATS)) 7471 return 0; 7472 7473 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PCIE_QSTATS, -1, -1); 7474 req.pcie_stat_size = cpu_to_le16(sizeof(struct pcie_ctx_hw_stats)); 7475 req.pcie_stat_host_addr = cpu_to_le64(bp->hw_pcie_stats_map); 7476 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 7477 } 7478 7479 static void bnxt_hwrm_free_tunnel_ports(struct bnxt *bp) 7480 { 7481 if (bp->vxlan_port_cnt) { 7482 bnxt_hwrm_tunnel_dst_port_free( 7483 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN); 7484 } 7485 bp->vxlan_port_cnt = 0; 7486 if (bp->nge_port_cnt) { 7487 bnxt_hwrm_tunnel_dst_port_free( 7488 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE); 7489 } 7490 bp->nge_port_cnt = 0; 7491 } 7492 7493 static int bnxt_set_tpa(struct bnxt *bp, bool set_tpa) 7494 { 7495 int rc, i; 7496 u32 tpa_flags = 0; 7497 7498 if (set_tpa) 7499 tpa_flags = bp->flags & BNXT_FLAG_TPA; 7500 else if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state)) 7501 return 0; 7502 for (i = 0; i < bp->nr_vnics; i++) { 7503 rc = bnxt_hwrm_vnic_set_tpa(bp, i, tpa_flags); 7504 if (rc) { 7505 netdev_err(bp->dev, "hwrm vnic set tpa failure rc for vnic %d: %x\n", 7506 i, rc); 7507 return rc; 7508 } 7509 } 7510 return 0; 7511 } 7512 7513 static void bnxt_hwrm_clear_vnic_rss(struct bnxt *bp) 7514 { 7515 int i; 7516 7517 for (i = 0; i < bp->nr_vnics; i++) 7518 bnxt_hwrm_vnic_set_rss(bp, i, false); 7519 } 7520 7521 static void bnxt_clear_vnic(struct bnxt *bp) 7522 { 7523 if (!bp->vnic_info) 7524 return; 7525 7526 bnxt_hwrm_clear_vnic_filter(bp); 7527 if (!(bp->flags & BNXT_FLAG_CHIP_P5)) { 7528 /* clear all RSS setting before free vnic ctx */ 7529 bnxt_hwrm_clear_vnic_rss(bp); 7530 bnxt_hwrm_vnic_ctx_free(bp); 7531 } 7532 /* before free the vnic, undo the vnic tpa settings */ 7533 if (bp->flags & BNXT_FLAG_TPA) 7534 bnxt_set_tpa(bp, false); 7535 bnxt_hwrm_vnic_free(bp); 7536 if (bp->flags & BNXT_FLAG_CHIP_P5) 7537 bnxt_hwrm_vnic_ctx_free(bp); 7538 } 7539 7540 static void bnxt_hwrm_resource_free(struct bnxt *bp, bool close_path, 7541 bool irq_re_init) 7542 { 7543 bnxt_clear_vnic(bp); 7544 bnxt_hwrm_ring_free(bp, close_path); 7545 bnxt_hwrm_ring_grp_free(bp); 7546 if (irq_re_init) { 7547 bnxt_hwrm_stat_ctx_free(bp); 7548 bnxt_hwrm_free_tunnel_ports(bp); 7549 } 7550 } 7551 7552 static int bnxt_hwrm_set_br_mode(struct bnxt *bp, u16 br_mode) 7553 { 7554 struct hwrm_func_cfg_input req = {0}; 7555 7556 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1); 7557 req.fid = cpu_to_le16(0xffff); 7558 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_EVB_MODE); 7559 if (br_mode == BRIDGE_MODE_VEB) 7560 req.evb_mode = FUNC_CFG_REQ_EVB_MODE_VEB; 7561 else if (br_mode == BRIDGE_MODE_VEPA) 7562 req.evb_mode = FUNC_CFG_REQ_EVB_MODE_VEPA; 7563 else 7564 return -EINVAL; 7565 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 7566 } 7567 7568 static int bnxt_hwrm_set_cache_line_size(struct bnxt *bp, int size) 7569 { 7570 struct hwrm_func_cfg_input req = {0}; 7571 7572 if (BNXT_VF(bp) || bp->hwrm_spec_code < 0x10803) 7573 return 0; 7574 7575 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1); 7576 req.fid = cpu_to_le16(0xffff); 7577 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_CACHE_LINESIZE); 7578 req.options = FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_64; 7579 if (size == 128) 7580 req.options = FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128; 7581 7582 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 7583 } 7584 7585 static int __bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id) 7586 { 7587 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 7588 int rc; 7589 7590 if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG) 7591 goto skip_rss_ctx; 7592 7593 /* allocate context for vnic */ 7594 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 0); 7595 if (rc) { 7596 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n", 7597 vnic_id, rc); 7598 goto vnic_setup_err; 7599 } 7600 bp->rsscos_nr_ctxs++; 7601 7602 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) { 7603 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 1); 7604 if (rc) { 7605 netdev_err(bp->dev, "hwrm vnic %d cos ctx alloc failure rc: %x\n", 7606 vnic_id, rc); 7607 goto vnic_setup_err; 7608 } 7609 bp->rsscos_nr_ctxs++; 7610 } 7611 7612 skip_rss_ctx: 7613 /* configure default vnic, ring grp */ 7614 rc = bnxt_hwrm_vnic_cfg(bp, vnic_id); 7615 if (rc) { 7616 netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n", 7617 vnic_id, rc); 7618 goto vnic_setup_err; 7619 } 7620 7621 /* Enable RSS hashing on vnic */ 7622 rc = bnxt_hwrm_vnic_set_rss(bp, vnic_id, true); 7623 if (rc) { 7624 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %x\n", 7625 vnic_id, rc); 7626 goto vnic_setup_err; 7627 } 7628 7629 if (bp->flags & BNXT_FLAG_AGG_RINGS) { 7630 rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id); 7631 if (rc) { 7632 netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n", 7633 vnic_id, rc); 7634 } 7635 } 7636 7637 vnic_setup_err: 7638 return rc; 7639 } 7640 7641 static int __bnxt_setup_vnic_p5(struct bnxt *bp, u16 vnic_id) 7642 { 7643 int rc, i, nr_ctxs; 7644 7645 nr_ctxs = DIV_ROUND_UP(bp->rx_nr_rings, 64); 7646 for (i = 0; i < nr_ctxs; i++) { 7647 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, i); 7648 if (rc) { 7649 netdev_err(bp->dev, "hwrm vnic %d ctx %d alloc failure rc: %x\n", 7650 vnic_id, i, rc); 7651 break; 7652 } 7653 bp->rsscos_nr_ctxs++; 7654 } 7655 if (i < nr_ctxs) 7656 return -ENOMEM; 7657 7658 rc = bnxt_hwrm_vnic_set_rss_p5(bp, vnic_id, true); 7659 if (rc) { 7660 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %d\n", 7661 vnic_id, rc); 7662 return rc; 7663 } 7664 rc = bnxt_hwrm_vnic_cfg(bp, vnic_id); 7665 if (rc) { 7666 netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n", 7667 vnic_id, rc); 7668 return rc; 7669 } 7670 if (bp->flags & BNXT_FLAG_AGG_RINGS) { 7671 rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id); 7672 if (rc) { 7673 netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n", 7674 vnic_id, rc); 7675 } 7676 } 7677 return rc; 7678 } 7679 7680 static int bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id) 7681 { 7682 if (bp->flags & BNXT_FLAG_CHIP_P5) 7683 return __bnxt_setup_vnic_p5(bp, vnic_id); 7684 else 7685 return __bnxt_setup_vnic(bp, vnic_id); 7686 } 7687 7688 static int bnxt_alloc_rfs_vnics(struct bnxt *bp) 7689 { 7690 #ifdef CONFIG_RFS_ACCEL 7691 int i, rc = 0; 7692 7693 if (bp->flags & BNXT_FLAG_CHIP_P5) 7694 return 0; 7695 7696 for (i = 0; i < bp->rx_nr_rings; i++) { 7697 struct bnxt_vnic_info *vnic; 7698 u16 vnic_id = i + 1; 7699 u16 ring_id = i; 7700 7701 if (vnic_id >= bp->nr_vnics) 7702 break; 7703 7704 vnic = &bp->vnic_info[vnic_id]; 7705 vnic->flags |= BNXT_VNIC_RFS_FLAG; 7706 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP) 7707 vnic->flags |= BNXT_VNIC_RFS_NEW_RSS_FLAG; 7708 rc = bnxt_hwrm_vnic_alloc(bp, vnic_id, ring_id, 1); 7709 if (rc) { 7710 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n", 7711 vnic_id, rc); 7712 break; 7713 } 7714 rc = bnxt_setup_vnic(bp, vnic_id); 7715 if (rc) 7716 break; 7717 } 7718 return rc; 7719 #else 7720 return 0; 7721 #endif 7722 } 7723 7724 /* Allow PF and VF with default VLAN to be in promiscuous mode */ 7725 static bool bnxt_promisc_ok(struct bnxt *bp) 7726 { 7727 #ifdef CONFIG_BNXT_SRIOV 7728 if (BNXT_VF(bp) && !bp->vf.vlan) 7729 return false; 7730 #endif 7731 return true; 7732 } 7733 7734 static int bnxt_setup_nitroa0_vnic(struct bnxt *bp) 7735 { 7736 unsigned int rc = 0; 7737 7738 rc = bnxt_hwrm_vnic_alloc(bp, 1, bp->rx_nr_rings - 1, 1); 7739 if (rc) { 7740 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n", 7741 rc); 7742 return rc; 7743 } 7744 7745 rc = bnxt_hwrm_vnic_cfg(bp, 1); 7746 if (rc) { 7747 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n", 7748 rc); 7749 return rc; 7750 } 7751 return rc; 7752 } 7753 7754 static int bnxt_cfg_rx_mode(struct bnxt *); 7755 static bool bnxt_mc_list_updated(struct bnxt *, u32 *); 7756 7757 static int bnxt_init_chip(struct bnxt *bp, bool irq_re_init) 7758 { 7759 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 7760 int rc = 0; 7761 unsigned int rx_nr_rings = bp->rx_nr_rings; 7762 7763 if (irq_re_init) { 7764 rc = bnxt_hwrm_stat_ctx_alloc(bp); 7765 if (rc) { 7766 netdev_err(bp->dev, "hwrm stat ctx alloc failure rc: %x\n", 7767 rc); 7768 goto err_out; 7769 } 7770 } 7771 7772 rc = bnxt_hwrm_ring_alloc(bp); 7773 if (rc) { 7774 netdev_err(bp->dev, "hwrm ring alloc failure rc: %x\n", rc); 7775 goto err_out; 7776 } 7777 7778 rc = bnxt_hwrm_ring_grp_alloc(bp); 7779 if (rc) { 7780 netdev_err(bp->dev, "hwrm_ring_grp alloc failure: %x\n", rc); 7781 goto err_out; 7782 } 7783 7784 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 7785 rx_nr_rings--; 7786 7787 /* default vnic 0 */ 7788 rc = bnxt_hwrm_vnic_alloc(bp, 0, 0, rx_nr_rings); 7789 if (rc) { 7790 netdev_err(bp->dev, "hwrm vnic alloc failure rc: %x\n", rc); 7791 goto err_out; 7792 } 7793 7794 rc = bnxt_setup_vnic(bp, 0); 7795 if (rc) 7796 goto err_out; 7797 7798 if (bp->flags & BNXT_FLAG_RFS) { 7799 rc = bnxt_alloc_rfs_vnics(bp); 7800 if (rc) 7801 goto err_out; 7802 } 7803 7804 if (bp->flags & BNXT_FLAG_TPA) { 7805 rc = bnxt_set_tpa(bp, true); 7806 if (rc) 7807 goto err_out; 7808 } 7809 7810 if (BNXT_VF(bp)) 7811 bnxt_update_vf_mac(bp); 7812 7813 /* Filter for default vnic 0 */ 7814 rc = bnxt_hwrm_set_vnic_filter(bp, 0, 0, bp->dev->dev_addr); 7815 if (rc) { 7816 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n", rc); 7817 goto err_out; 7818 } 7819 vnic->uc_filter_count = 1; 7820 7821 vnic->rx_mask = 0; 7822 if (bp->dev->flags & IFF_BROADCAST) 7823 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_BCAST; 7824 7825 if ((bp->dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp)) 7826 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS; 7827 7828 if (bp->dev->flags & IFF_ALLMULTI) { 7829 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST; 7830 vnic->mc_list_count = 0; 7831 } else { 7832 u32 mask = 0; 7833 7834 bnxt_mc_list_updated(bp, &mask); 7835 vnic->rx_mask |= mask; 7836 } 7837 7838 rc = bnxt_cfg_rx_mode(bp); 7839 if (rc) 7840 goto err_out; 7841 7842 rc = bnxt_hwrm_set_coal(bp); 7843 if (rc) 7844 netdev_warn(bp->dev, "HWRM set coalescing failure rc: %x\n", 7845 rc); 7846 7847 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) { 7848 rc = bnxt_setup_nitroa0_vnic(bp); 7849 if (rc) 7850 netdev_err(bp->dev, "Special vnic setup failure for NS2 A0 rc: %x\n", 7851 rc); 7852 } 7853 7854 if (BNXT_VF(bp)) { 7855 bnxt_hwrm_func_qcfg(bp); 7856 netdev_update_features(bp->dev); 7857 } 7858 7859 return 0; 7860 7861 err_out: 7862 bnxt_hwrm_resource_free(bp, 0, true); 7863 7864 return rc; 7865 } 7866 7867 static int bnxt_shutdown_nic(struct bnxt *bp, bool irq_re_init) 7868 { 7869 bnxt_hwrm_resource_free(bp, 1, irq_re_init); 7870 return 0; 7871 } 7872 7873 static int bnxt_init_nic(struct bnxt *bp, bool irq_re_init) 7874 { 7875 bnxt_init_cp_rings(bp); 7876 bnxt_init_rx_rings(bp); 7877 bnxt_init_tx_rings(bp); 7878 bnxt_init_ring_grps(bp, irq_re_init); 7879 bnxt_init_vnics(bp); 7880 7881 return bnxt_init_chip(bp, irq_re_init); 7882 } 7883 7884 static int bnxt_set_real_num_queues(struct bnxt *bp) 7885 { 7886 int rc; 7887 struct net_device *dev = bp->dev; 7888 7889 rc = netif_set_real_num_tx_queues(dev, bp->tx_nr_rings - 7890 bp->tx_nr_rings_xdp); 7891 if (rc) 7892 return rc; 7893 7894 rc = netif_set_real_num_rx_queues(dev, bp->rx_nr_rings); 7895 if (rc) 7896 return rc; 7897 7898 #ifdef CONFIG_RFS_ACCEL 7899 if (bp->flags & BNXT_FLAG_RFS) 7900 dev->rx_cpu_rmap = alloc_irq_cpu_rmap(bp->rx_nr_rings); 7901 #endif 7902 7903 return rc; 7904 } 7905 7906 static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max, 7907 bool shared) 7908 { 7909 int _rx = *rx, _tx = *tx; 7910 7911 if (shared) { 7912 *rx = min_t(int, _rx, max); 7913 *tx = min_t(int, _tx, max); 7914 } else { 7915 if (max < 2) 7916 return -ENOMEM; 7917 7918 while (_rx + _tx > max) { 7919 if (_rx > _tx && _rx > 1) 7920 _rx--; 7921 else if (_tx > 1) 7922 _tx--; 7923 } 7924 *rx = _rx; 7925 *tx = _tx; 7926 } 7927 return 0; 7928 } 7929 7930 static void bnxt_setup_msix(struct bnxt *bp) 7931 { 7932 const int len = sizeof(bp->irq_tbl[0].name); 7933 struct net_device *dev = bp->dev; 7934 int tcs, i; 7935 7936 tcs = netdev_get_num_tc(dev); 7937 if (tcs) { 7938 int i, off, count; 7939 7940 for (i = 0; i < tcs; i++) { 7941 count = bp->tx_nr_rings_per_tc; 7942 off = i * count; 7943 netdev_set_tc_queue(dev, i, count, off); 7944 } 7945 } 7946 7947 for (i = 0; i < bp->cp_nr_rings; i++) { 7948 int map_idx = bnxt_cp_num_to_irq_num(bp, i); 7949 char *attr; 7950 7951 if (bp->flags & BNXT_FLAG_SHARED_RINGS) 7952 attr = "TxRx"; 7953 else if (i < bp->rx_nr_rings) 7954 attr = "rx"; 7955 else 7956 attr = "tx"; 7957 7958 snprintf(bp->irq_tbl[map_idx].name, len, "%s-%s-%d", dev->name, 7959 attr, i); 7960 bp->irq_tbl[map_idx].handler = bnxt_msix; 7961 } 7962 } 7963 7964 static void bnxt_setup_inta(struct bnxt *bp) 7965 { 7966 const int len = sizeof(bp->irq_tbl[0].name); 7967 7968 if (netdev_get_num_tc(bp->dev)) 7969 netdev_reset_tc(bp->dev); 7970 7971 snprintf(bp->irq_tbl[0].name, len, "%s-%s-%d", bp->dev->name, "TxRx", 7972 0); 7973 bp->irq_tbl[0].handler = bnxt_inta; 7974 } 7975 7976 static int bnxt_setup_int_mode(struct bnxt *bp) 7977 { 7978 int rc; 7979 7980 if (bp->flags & BNXT_FLAG_USING_MSIX) 7981 bnxt_setup_msix(bp); 7982 else 7983 bnxt_setup_inta(bp); 7984 7985 rc = bnxt_set_real_num_queues(bp); 7986 return rc; 7987 } 7988 7989 #ifdef CONFIG_RFS_ACCEL 7990 static unsigned int bnxt_get_max_func_rss_ctxs(struct bnxt *bp) 7991 { 7992 return bp->hw_resc.max_rsscos_ctxs; 7993 } 7994 7995 static unsigned int bnxt_get_max_func_vnics(struct bnxt *bp) 7996 { 7997 return bp->hw_resc.max_vnics; 7998 } 7999 #endif 8000 8001 unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt *bp) 8002 { 8003 return bp->hw_resc.max_stat_ctxs; 8004 } 8005 8006 unsigned int bnxt_get_max_func_cp_rings(struct bnxt *bp) 8007 { 8008 return bp->hw_resc.max_cp_rings; 8009 } 8010 8011 static unsigned int bnxt_get_max_func_cp_rings_for_en(struct bnxt *bp) 8012 { 8013 unsigned int cp = bp->hw_resc.max_cp_rings; 8014 8015 if (!(bp->flags & BNXT_FLAG_CHIP_P5)) 8016 cp -= bnxt_get_ulp_msix_num(bp); 8017 8018 return cp; 8019 } 8020 8021 static unsigned int bnxt_get_max_func_irqs(struct bnxt *bp) 8022 { 8023 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 8024 8025 if (bp->flags & BNXT_FLAG_CHIP_P5) 8026 return min_t(unsigned int, hw_resc->max_irqs, hw_resc->max_nqs); 8027 8028 return min_t(unsigned int, hw_resc->max_irqs, hw_resc->max_cp_rings); 8029 } 8030 8031 static void bnxt_set_max_func_irqs(struct bnxt *bp, unsigned int max_irqs) 8032 { 8033 bp->hw_resc.max_irqs = max_irqs; 8034 } 8035 8036 unsigned int bnxt_get_avail_cp_rings_for_en(struct bnxt *bp) 8037 { 8038 unsigned int cp; 8039 8040 cp = bnxt_get_max_func_cp_rings_for_en(bp); 8041 if (bp->flags & BNXT_FLAG_CHIP_P5) 8042 return cp - bp->rx_nr_rings - bp->tx_nr_rings; 8043 else 8044 return cp - bp->cp_nr_rings; 8045 } 8046 8047 unsigned int bnxt_get_avail_stat_ctxs_for_en(struct bnxt *bp) 8048 { 8049 return bnxt_get_max_func_stat_ctxs(bp) - bnxt_get_func_stat_ctxs(bp); 8050 } 8051 8052 int bnxt_get_avail_msix(struct bnxt *bp, int num) 8053 { 8054 int max_cp = bnxt_get_max_func_cp_rings(bp); 8055 int max_irq = bnxt_get_max_func_irqs(bp); 8056 int total_req = bp->cp_nr_rings + num; 8057 int max_idx, avail_msix; 8058 8059 max_idx = bp->total_irqs; 8060 if (!(bp->flags & BNXT_FLAG_CHIP_P5)) 8061 max_idx = min_t(int, bp->total_irqs, max_cp); 8062 avail_msix = max_idx - bp->cp_nr_rings; 8063 if (!BNXT_NEW_RM(bp) || avail_msix >= num) 8064 return avail_msix; 8065 8066 if (max_irq < total_req) { 8067 num = max_irq - bp->cp_nr_rings; 8068 if (num <= 0) 8069 return 0; 8070 } 8071 return num; 8072 } 8073 8074 static int bnxt_get_num_msix(struct bnxt *bp) 8075 { 8076 if (!BNXT_NEW_RM(bp)) 8077 return bnxt_get_max_func_irqs(bp); 8078 8079 return bnxt_nq_rings_in_use(bp); 8080 } 8081 8082 static int bnxt_init_msix(struct bnxt *bp) 8083 { 8084 int i, total_vecs, max, rc = 0, min = 1, ulp_msix; 8085 struct msix_entry *msix_ent; 8086 8087 total_vecs = bnxt_get_num_msix(bp); 8088 max = bnxt_get_max_func_irqs(bp); 8089 if (total_vecs > max) 8090 total_vecs = max; 8091 8092 if (!total_vecs) 8093 return 0; 8094 8095 msix_ent = kcalloc(total_vecs, sizeof(struct msix_entry), GFP_KERNEL); 8096 if (!msix_ent) 8097 return -ENOMEM; 8098 8099 for (i = 0; i < total_vecs; i++) { 8100 msix_ent[i].entry = i; 8101 msix_ent[i].vector = 0; 8102 } 8103 8104 if (!(bp->flags & BNXT_FLAG_SHARED_RINGS)) 8105 min = 2; 8106 8107 total_vecs = pci_enable_msix_range(bp->pdev, msix_ent, min, total_vecs); 8108 ulp_msix = bnxt_get_ulp_msix_num(bp); 8109 if (total_vecs < 0 || total_vecs < ulp_msix) { 8110 rc = -ENODEV; 8111 goto msix_setup_exit; 8112 } 8113 8114 bp->irq_tbl = kcalloc(total_vecs, sizeof(struct bnxt_irq), GFP_KERNEL); 8115 if (bp->irq_tbl) { 8116 for (i = 0; i < total_vecs; i++) 8117 bp->irq_tbl[i].vector = msix_ent[i].vector; 8118 8119 bp->total_irqs = total_vecs; 8120 /* Trim rings based upon num of vectors allocated */ 8121 rc = bnxt_trim_rings(bp, &bp->rx_nr_rings, &bp->tx_nr_rings, 8122 total_vecs - ulp_msix, min == 1); 8123 if (rc) 8124 goto msix_setup_exit; 8125 8126 bp->cp_nr_rings = (min == 1) ? 8127 max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) : 8128 bp->tx_nr_rings + bp->rx_nr_rings; 8129 8130 } else { 8131 rc = -ENOMEM; 8132 goto msix_setup_exit; 8133 } 8134 bp->flags |= BNXT_FLAG_USING_MSIX; 8135 kfree(msix_ent); 8136 return 0; 8137 8138 msix_setup_exit: 8139 netdev_err(bp->dev, "bnxt_init_msix err: %x\n", rc); 8140 kfree(bp->irq_tbl); 8141 bp->irq_tbl = NULL; 8142 pci_disable_msix(bp->pdev); 8143 kfree(msix_ent); 8144 return rc; 8145 } 8146 8147 static int bnxt_init_inta(struct bnxt *bp) 8148 { 8149 bp->irq_tbl = kcalloc(1, sizeof(struct bnxt_irq), GFP_KERNEL); 8150 if (!bp->irq_tbl) 8151 return -ENOMEM; 8152 8153 bp->total_irqs = 1; 8154 bp->rx_nr_rings = 1; 8155 bp->tx_nr_rings = 1; 8156 bp->cp_nr_rings = 1; 8157 bp->flags |= BNXT_FLAG_SHARED_RINGS; 8158 bp->irq_tbl[0].vector = bp->pdev->irq; 8159 return 0; 8160 } 8161 8162 static int bnxt_init_int_mode(struct bnxt *bp) 8163 { 8164 int rc = 0; 8165 8166 if (bp->flags & BNXT_FLAG_MSIX_CAP) 8167 rc = bnxt_init_msix(bp); 8168 8169 if (!(bp->flags & BNXT_FLAG_USING_MSIX) && BNXT_PF(bp)) { 8170 /* fallback to INTA */ 8171 rc = bnxt_init_inta(bp); 8172 } 8173 return rc; 8174 } 8175 8176 static void bnxt_clear_int_mode(struct bnxt *bp) 8177 { 8178 if (bp->flags & BNXT_FLAG_USING_MSIX) 8179 pci_disable_msix(bp->pdev); 8180 8181 kfree(bp->irq_tbl); 8182 bp->irq_tbl = NULL; 8183 bp->flags &= ~BNXT_FLAG_USING_MSIX; 8184 } 8185 8186 int bnxt_reserve_rings(struct bnxt *bp, bool irq_re_init) 8187 { 8188 int tcs = netdev_get_num_tc(bp->dev); 8189 bool irq_cleared = false; 8190 int rc; 8191 8192 if (!bnxt_need_reserve_rings(bp)) 8193 return 0; 8194 8195 if (irq_re_init && BNXT_NEW_RM(bp) && 8196 bnxt_get_num_msix(bp) != bp->total_irqs) { 8197 bnxt_ulp_irq_stop(bp); 8198 bnxt_clear_int_mode(bp); 8199 irq_cleared = true; 8200 } 8201 rc = __bnxt_reserve_rings(bp); 8202 if (irq_cleared) { 8203 if (!rc) 8204 rc = bnxt_init_int_mode(bp); 8205 bnxt_ulp_irq_restart(bp, rc); 8206 } 8207 if (rc) { 8208 netdev_err(bp->dev, "ring reservation/IRQ init failure rc: %d\n", rc); 8209 return rc; 8210 } 8211 if (tcs && (bp->tx_nr_rings_per_tc * tcs != bp->tx_nr_rings)) { 8212 netdev_err(bp->dev, "tx ring reservation failure\n"); 8213 netdev_reset_tc(bp->dev); 8214 bp->tx_nr_rings_per_tc = bp->tx_nr_rings; 8215 return -ENOMEM; 8216 } 8217 return 0; 8218 } 8219 8220 static void bnxt_free_irq(struct bnxt *bp) 8221 { 8222 struct bnxt_irq *irq; 8223 int i; 8224 8225 #ifdef CONFIG_RFS_ACCEL 8226 free_irq_cpu_rmap(bp->dev->rx_cpu_rmap); 8227 bp->dev->rx_cpu_rmap = NULL; 8228 #endif 8229 if (!bp->irq_tbl || !bp->bnapi) 8230 return; 8231 8232 for (i = 0; i < bp->cp_nr_rings; i++) { 8233 int map_idx = bnxt_cp_num_to_irq_num(bp, i); 8234 8235 irq = &bp->irq_tbl[map_idx]; 8236 if (irq->requested) { 8237 if (irq->have_cpumask) { 8238 irq_set_affinity_hint(irq->vector, NULL); 8239 free_cpumask_var(irq->cpu_mask); 8240 irq->have_cpumask = 0; 8241 } 8242 free_irq(irq->vector, bp->bnapi[i]); 8243 } 8244 8245 irq->requested = 0; 8246 } 8247 } 8248 8249 static int bnxt_request_irq(struct bnxt *bp) 8250 { 8251 int i, j, rc = 0; 8252 unsigned long flags = 0; 8253 #ifdef CONFIG_RFS_ACCEL 8254 struct cpu_rmap *rmap; 8255 #endif 8256 8257 rc = bnxt_setup_int_mode(bp); 8258 if (rc) { 8259 netdev_err(bp->dev, "bnxt_setup_int_mode err: %x\n", 8260 rc); 8261 return rc; 8262 } 8263 #ifdef CONFIG_RFS_ACCEL 8264 rmap = bp->dev->rx_cpu_rmap; 8265 #endif 8266 if (!(bp->flags & BNXT_FLAG_USING_MSIX)) 8267 flags = IRQF_SHARED; 8268 8269 for (i = 0, j = 0; i < bp->cp_nr_rings; i++) { 8270 int map_idx = bnxt_cp_num_to_irq_num(bp, i); 8271 struct bnxt_irq *irq = &bp->irq_tbl[map_idx]; 8272 8273 #ifdef CONFIG_RFS_ACCEL 8274 if (rmap && bp->bnapi[i]->rx_ring) { 8275 rc = irq_cpu_rmap_add(rmap, irq->vector); 8276 if (rc) 8277 netdev_warn(bp->dev, "failed adding irq rmap for ring %d\n", 8278 j); 8279 j++; 8280 } 8281 #endif 8282 rc = request_irq(irq->vector, irq->handler, flags, irq->name, 8283 bp->bnapi[i]); 8284 if (rc) 8285 break; 8286 8287 irq->requested = 1; 8288 8289 if (zalloc_cpumask_var(&irq->cpu_mask, GFP_KERNEL)) { 8290 int numa_node = dev_to_node(&bp->pdev->dev); 8291 8292 irq->have_cpumask = 1; 8293 cpumask_set_cpu(cpumask_local_spread(i, numa_node), 8294 irq->cpu_mask); 8295 rc = irq_set_affinity_hint(irq->vector, irq->cpu_mask); 8296 if (rc) { 8297 netdev_warn(bp->dev, 8298 "Set affinity failed, IRQ = %d\n", 8299 irq->vector); 8300 break; 8301 } 8302 } 8303 } 8304 return rc; 8305 } 8306 8307 static void bnxt_del_napi(struct bnxt *bp) 8308 { 8309 int i; 8310 8311 if (!bp->bnapi) 8312 return; 8313 8314 for (i = 0; i < bp->cp_nr_rings; i++) { 8315 struct bnxt_napi *bnapi = bp->bnapi[i]; 8316 8317 napi_hash_del(&bnapi->napi); 8318 netif_napi_del(&bnapi->napi); 8319 } 8320 /* We called napi_hash_del() before netif_napi_del(), we need 8321 * to respect an RCU grace period before freeing napi structures. 8322 */ 8323 synchronize_net(); 8324 } 8325 8326 static void bnxt_init_napi(struct bnxt *bp) 8327 { 8328 int i; 8329 unsigned int cp_nr_rings = bp->cp_nr_rings; 8330 struct bnxt_napi *bnapi; 8331 8332 if (bp->flags & BNXT_FLAG_USING_MSIX) { 8333 int (*poll_fn)(struct napi_struct *, int) = bnxt_poll; 8334 8335 if (bp->flags & BNXT_FLAG_CHIP_P5) 8336 poll_fn = bnxt_poll_p5; 8337 else if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 8338 cp_nr_rings--; 8339 for (i = 0; i < cp_nr_rings; i++) { 8340 bnapi = bp->bnapi[i]; 8341 netif_napi_add(bp->dev, &bnapi->napi, poll_fn, 64); 8342 } 8343 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) { 8344 bnapi = bp->bnapi[cp_nr_rings]; 8345 netif_napi_add(bp->dev, &bnapi->napi, 8346 bnxt_poll_nitroa0, 64); 8347 } 8348 } else { 8349 bnapi = bp->bnapi[0]; 8350 netif_napi_add(bp->dev, &bnapi->napi, bnxt_poll, 64); 8351 } 8352 } 8353 8354 static void bnxt_disable_napi(struct bnxt *bp) 8355 { 8356 int i; 8357 8358 if (!bp->bnapi) 8359 return; 8360 8361 for (i = 0; i < bp->cp_nr_rings; i++) { 8362 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring; 8363 8364 if (bp->bnapi[i]->rx_ring) 8365 cancel_work_sync(&cpr->dim.work); 8366 8367 napi_disable(&bp->bnapi[i]->napi); 8368 } 8369 } 8370 8371 static void bnxt_enable_napi(struct bnxt *bp) 8372 { 8373 int i; 8374 8375 for (i = 0; i < bp->cp_nr_rings; i++) { 8376 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring; 8377 bp->bnapi[i]->in_reset = false; 8378 8379 if (bp->bnapi[i]->rx_ring) { 8380 INIT_WORK(&cpr->dim.work, bnxt_dim_work); 8381 cpr->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE; 8382 } 8383 napi_enable(&bp->bnapi[i]->napi); 8384 } 8385 } 8386 8387 void bnxt_tx_disable(struct bnxt *bp) 8388 { 8389 int i; 8390 struct bnxt_tx_ring_info *txr; 8391 8392 if (bp->tx_ring) { 8393 for (i = 0; i < bp->tx_nr_rings; i++) { 8394 txr = &bp->tx_ring[i]; 8395 txr->dev_state = BNXT_DEV_STATE_CLOSING; 8396 } 8397 } 8398 /* Stop all TX queues */ 8399 netif_tx_disable(bp->dev); 8400 netif_carrier_off(bp->dev); 8401 } 8402 8403 void bnxt_tx_enable(struct bnxt *bp) 8404 { 8405 int i; 8406 struct bnxt_tx_ring_info *txr; 8407 8408 for (i = 0; i < bp->tx_nr_rings; i++) { 8409 txr = &bp->tx_ring[i]; 8410 txr->dev_state = 0; 8411 } 8412 netif_tx_wake_all_queues(bp->dev); 8413 if (bp->link_info.link_up) 8414 netif_carrier_on(bp->dev); 8415 } 8416 8417 static void bnxt_report_link(struct bnxt *bp) 8418 { 8419 if (bp->link_info.link_up) { 8420 const char *duplex; 8421 const char *flow_ctrl; 8422 u32 speed; 8423 u16 fec; 8424 8425 netif_carrier_on(bp->dev); 8426 if (bp->link_info.duplex == BNXT_LINK_DUPLEX_FULL) 8427 duplex = "full"; 8428 else 8429 duplex = "half"; 8430 if (bp->link_info.pause == BNXT_LINK_PAUSE_BOTH) 8431 flow_ctrl = "ON - receive & transmit"; 8432 else if (bp->link_info.pause == BNXT_LINK_PAUSE_TX) 8433 flow_ctrl = "ON - transmit"; 8434 else if (bp->link_info.pause == BNXT_LINK_PAUSE_RX) 8435 flow_ctrl = "ON - receive"; 8436 else 8437 flow_ctrl = "none"; 8438 speed = bnxt_fw_to_ethtool_speed(bp->link_info.link_speed); 8439 netdev_info(bp->dev, "NIC Link is Up, %u Mbps %s duplex, Flow control: %s\n", 8440 speed, duplex, flow_ctrl); 8441 if (bp->flags & BNXT_FLAG_EEE_CAP) 8442 netdev_info(bp->dev, "EEE is %s\n", 8443 bp->eee.eee_active ? "active" : 8444 "not active"); 8445 fec = bp->link_info.fec_cfg; 8446 if (!(fec & PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED)) 8447 netdev_info(bp->dev, "FEC autoneg %s encodings: %s\n", 8448 (fec & BNXT_FEC_AUTONEG) ? "on" : "off", 8449 (fec & BNXT_FEC_ENC_BASE_R) ? "BaseR" : 8450 (fec & BNXT_FEC_ENC_RS) ? "RS" : "None"); 8451 } else { 8452 netif_carrier_off(bp->dev); 8453 netdev_err(bp->dev, "NIC Link is Down\n"); 8454 } 8455 } 8456 8457 static int bnxt_hwrm_phy_qcaps(struct bnxt *bp) 8458 { 8459 int rc = 0; 8460 struct hwrm_port_phy_qcaps_input req = {0}; 8461 struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr; 8462 struct bnxt_link_info *link_info = &bp->link_info; 8463 8464 bp->flags &= ~BNXT_FLAG_EEE_CAP; 8465 if (bp->test_info) 8466 bp->test_info->flags &= ~(BNXT_TEST_FL_EXT_LPBK | 8467 BNXT_TEST_FL_AN_PHY_LPBK); 8468 if (bp->hwrm_spec_code < 0x10201) 8469 return 0; 8470 8471 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCAPS, -1, -1); 8472 8473 mutex_lock(&bp->hwrm_cmd_lock); 8474 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 8475 if (rc) 8476 goto hwrm_phy_qcaps_exit; 8477 8478 if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED) { 8479 struct ethtool_eee *eee = &bp->eee; 8480 u16 fw_speeds = le16_to_cpu(resp->supported_speeds_eee_mode); 8481 8482 bp->flags |= BNXT_FLAG_EEE_CAP; 8483 eee->supported = _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0); 8484 bp->lpi_tmr_lo = le32_to_cpu(resp->tx_lpi_timer_low) & 8485 PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK; 8486 bp->lpi_tmr_hi = le32_to_cpu(resp->valid_tx_lpi_timer_high) & 8487 PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK; 8488 } 8489 if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_EXTERNAL_LPBK_SUPPORTED) { 8490 if (bp->test_info) 8491 bp->test_info->flags |= BNXT_TEST_FL_EXT_LPBK; 8492 } 8493 if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_AUTONEG_LPBK_SUPPORTED) { 8494 if (bp->test_info) 8495 bp->test_info->flags |= BNXT_TEST_FL_AN_PHY_LPBK; 8496 } 8497 if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_SHARED_PHY_CFG_SUPPORTED) { 8498 if (BNXT_PF(bp)) 8499 bp->fw_cap |= BNXT_FW_CAP_SHARED_PORT_CFG; 8500 } 8501 if (resp->supported_speeds_auto_mode) 8502 link_info->support_auto_speeds = 8503 le16_to_cpu(resp->supported_speeds_auto_mode); 8504 8505 bp->port_count = resp->port_cnt; 8506 8507 hwrm_phy_qcaps_exit: 8508 mutex_unlock(&bp->hwrm_cmd_lock); 8509 return rc; 8510 } 8511 8512 static int bnxt_update_link(struct bnxt *bp, bool chng_link_state) 8513 { 8514 int rc = 0; 8515 struct bnxt_link_info *link_info = &bp->link_info; 8516 struct hwrm_port_phy_qcfg_input req = {0}; 8517 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr; 8518 u8 link_up = link_info->link_up; 8519 u16 diff; 8520 8521 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCFG, -1, -1); 8522 8523 mutex_lock(&bp->hwrm_cmd_lock); 8524 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 8525 if (rc) { 8526 mutex_unlock(&bp->hwrm_cmd_lock); 8527 return rc; 8528 } 8529 8530 memcpy(&link_info->phy_qcfg_resp, resp, sizeof(*resp)); 8531 link_info->phy_link_status = resp->link; 8532 link_info->duplex = resp->duplex_cfg; 8533 if (bp->hwrm_spec_code >= 0x10800) 8534 link_info->duplex = resp->duplex_state; 8535 link_info->pause = resp->pause; 8536 link_info->auto_mode = resp->auto_mode; 8537 link_info->auto_pause_setting = resp->auto_pause; 8538 link_info->lp_pause = resp->link_partner_adv_pause; 8539 link_info->force_pause_setting = resp->force_pause; 8540 link_info->duplex_setting = resp->duplex_cfg; 8541 if (link_info->phy_link_status == BNXT_LINK_LINK) 8542 link_info->link_speed = le16_to_cpu(resp->link_speed); 8543 else 8544 link_info->link_speed = 0; 8545 link_info->force_link_speed = le16_to_cpu(resp->force_link_speed); 8546 link_info->support_speeds = le16_to_cpu(resp->support_speeds); 8547 link_info->auto_link_speeds = le16_to_cpu(resp->auto_link_speed_mask); 8548 link_info->lp_auto_link_speeds = 8549 le16_to_cpu(resp->link_partner_adv_speeds); 8550 link_info->preemphasis = le32_to_cpu(resp->preemphasis); 8551 link_info->phy_ver[0] = resp->phy_maj; 8552 link_info->phy_ver[1] = resp->phy_min; 8553 link_info->phy_ver[2] = resp->phy_bld; 8554 link_info->media_type = resp->media_type; 8555 link_info->phy_type = resp->phy_type; 8556 link_info->transceiver = resp->xcvr_pkg_type; 8557 link_info->phy_addr = resp->eee_config_phy_addr & 8558 PORT_PHY_QCFG_RESP_PHY_ADDR_MASK; 8559 link_info->module_status = resp->module_status; 8560 8561 if (bp->flags & BNXT_FLAG_EEE_CAP) { 8562 struct ethtool_eee *eee = &bp->eee; 8563 u16 fw_speeds; 8564 8565 eee->eee_active = 0; 8566 if (resp->eee_config_phy_addr & 8567 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE) { 8568 eee->eee_active = 1; 8569 fw_speeds = le16_to_cpu( 8570 resp->link_partner_adv_eee_link_speed_mask); 8571 eee->lp_advertised = 8572 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0); 8573 } 8574 8575 /* Pull initial EEE config */ 8576 if (!chng_link_state) { 8577 if (resp->eee_config_phy_addr & 8578 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED) 8579 eee->eee_enabled = 1; 8580 8581 fw_speeds = le16_to_cpu(resp->adv_eee_link_speed_mask); 8582 eee->advertised = 8583 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0); 8584 8585 if (resp->eee_config_phy_addr & 8586 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI) { 8587 __le32 tmr; 8588 8589 eee->tx_lpi_enabled = 1; 8590 tmr = resp->xcvr_identifier_type_tx_lpi_timer; 8591 eee->tx_lpi_timer = le32_to_cpu(tmr) & 8592 PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK; 8593 } 8594 } 8595 } 8596 8597 link_info->fec_cfg = PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED; 8598 if (bp->hwrm_spec_code >= 0x10504) 8599 link_info->fec_cfg = le16_to_cpu(resp->fec_cfg); 8600 8601 /* TODO: need to add more logic to report VF link */ 8602 if (chng_link_state) { 8603 if (link_info->phy_link_status == BNXT_LINK_LINK) 8604 link_info->link_up = 1; 8605 else 8606 link_info->link_up = 0; 8607 if (link_up != link_info->link_up) 8608 bnxt_report_link(bp); 8609 } else { 8610 /* alwasy link down if not require to update link state */ 8611 link_info->link_up = 0; 8612 } 8613 mutex_unlock(&bp->hwrm_cmd_lock); 8614 8615 if (!BNXT_PHY_CFG_ABLE(bp)) 8616 return 0; 8617 8618 diff = link_info->support_auto_speeds ^ link_info->advertising; 8619 if ((link_info->support_auto_speeds | diff) != 8620 link_info->support_auto_speeds) { 8621 /* An advertised speed is no longer supported, so we need to 8622 * update the advertisement settings. Caller holds RTNL 8623 * so we can modify link settings. 8624 */ 8625 link_info->advertising = link_info->support_auto_speeds; 8626 if (link_info->autoneg & BNXT_AUTONEG_SPEED) 8627 bnxt_hwrm_set_link_setting(bp, true, false); 8628 } 8629 return 0; 8630 } 8631 8632 static void bnxt_get_port_module_status(struct bnxt *bp) 8633 { 8634 struct bnxt_link_info *link_info = &bp->link_info; 8635 struct hwrm_port_phy_qcfg_output *resp = &link_info->phy_qcfg_resp; 8636 u8 module_status; 8637 8638 if (bnxt_update_link(bp, true)) 8639 return; 8640 8641 module_status = link_info->module_status; 8642 switch (module_status) { 8643 case PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX: 8644 case PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN: 8645 case PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG: 8646 netdev_warn(bp->dev, "Unqualified SFP+ module detected on port %d\n", 8647 bp->pf.port_id); 8648 if (bp->hwrm_spec_code >= 0x10201) { 8649 netdev_warn(bp->dev, "Module part number %s\n", 8650 resp->phy_vendor_partnumber); 8651 } 8652 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX) 8653 netdev_warn(bp->dev, "TX is disabled\n"); 8654 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN) 8655 netdev_warn(bp->dev, "SFP+ module is shutdown\n"); 8656 } 8657 } 8658 8659 static void 8660 bnxt_hwrm_set_pause_common(struct bnxt *bp, struct hwrm_port_phy_cfg_input *req) 8661 { 8662 if (bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) { 8663 if (bp->hwrm_spec_code >= 0x10201) 8664 req->auto_pause = 8665 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE; 8666 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX) 8667 req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX; 8668 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX) 8669 req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_TX; 8670 req->enables |= 8671 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE); 8672 } else { 8673 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX) 8674 req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_RX; 8675 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX) 8676 req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_TX; 8677 req->enables |= 8678 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE); 8679 if (bp->hwrm_spec_code >= 0x10201) { 8680 req->auto_pause = req->force_pause; 8681 req->enables |= cpu_to_le32( 8682 PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE); 8683 } 8684 } 8685 } 8686 8687 static void bnxt_hwrm_set_link_common(struct bnxt *bp, 8688 struct hwrm_port_phy_cfg_input *req) 8689 { 8690 u8 autoneg = bp->link_info.autoneg; 8691 u16 fw_link_speed = bp->link_info.req_link_speed; 8692 u16 advertising = bp->link_info.advertising; 8693 8694 if (autoneg & BNXT_AUTONEG_SPEED) { 8695 req->auto_mode |= 8696 PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK; 8697 8698 req->enables |= cpu_to_le32( 8699 PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK); 8700 req->auto_link_speed_mask = cpu_to_le16(advertising); 8701 8702 req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE); 8703 req->flags |= 8704 cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG); 8705 } else { 8706 req->force_link_speed = cpu_to_le16(fw_link_speed); 8707 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE); 8708 } 8709 8710 /* tell chimp that the setting takes effect immediately */ 8711 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESET_PHY); 8712 } 8713 8714 int bnxt_hwrm_set_pause(struct bnxt *bp) 8715 { 8716 struct hwrm_port_phy_cfg_input req = {0}; 8717 int rc; 8718 8719 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1); 8720 bnxt_hwrm_set_pause_common(bp, &req); 8721 8722 if ((bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) || 8723 bp->link_info.force_link_chng) 8724 bnxt_hwrm_set_link_common(bp, &req); 8725 8726 mutex_lock(&bp->hwrm_cmd_lock); 8727 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 8728 if (!rc && !(bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL)) { 8729 /* since changing of pause setting doesn't trigger any link 8730 * change event, the driver needs to update the current pause 8731 * result upon successfully return of the phy_cfg command 8732 */ 8733 bp->link_info.pause = 8734 bp->link_info.force_pause_setting = bp->link_info.req_flow_ctrl; 8735 bp->link_info.auto_pause_setting = 0; 8736 if (!bp->link_info.force_link_chng) 8737 bnxt_report_link(bp); 8738 } 8739 bp->link_info.force_link_chng = false; 8740 mutex_unlock(&bp->hwrm_cmd_lock); 8741 return rc; 8742 } 8743 8744 static void bnxt_hwrm_set_eee(struct bnxt *bp, 8745 struct hwrm_port_phy_cfg_input *req) 8746 { 8747 struct ethtool_eee *eee = &bp->eee; 8748 8749 if (eee->eee_enabled) { 8750 u16 eee_speeds; 8751 u32 flags = PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE; 8752 8753 if (eee->tx_lpi_enabled) 8754 flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE; 8755 else 8756 flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE; 8757 8758 req->flags |= cpu_to_le32(flags); 8759 eee_speeds = bnxt_get_fw_auto_link_speeds(eee->advertised); 8760 req->eee_link_speed_mask = cpu_to_le16(eee_speeds); 8761 req->tx_lpi_timer = cpu_to_le32(eee->tx_lpi_timer); 8762 } else { 8763 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE); 8764 } 8765 } 8766 8767 int bnxt_hwrm_set_link_setting(struct bnxt *bp, bool set_pause, bool set_eee) 8768 { 8769 struct hwrm_port_phy_cfg_input req = {0}; 8770 8771 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1); 8772 if (set_pause) 8773 bnxt_hwrm_set_pause_common(bp, &req); 8774 8775 bnxt_hwrm_set_link_common(bp, &req); 8776 8777 if (set_eee) 8778 bnxt_hwrm_set_eee(bp, &req); 8779 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 8780 } 8781 8782 static int bnxt_hwrm_shutdown_link(struct bnxt *bp) 8783 { 8784 struct hwrm_port_phy_cfg_input req = {0}; 8785 8786 if (!BNXT_SINGLE_PF(bp)) 8787 return 0; 8788 8789 if (pci_num_vf(bp->pdev)) 8790 return 0; 8791 8792 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1); 8793 req.flags = cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN); 8794 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 8795 } 8796 8797 static int bnxt_fw_init_one(struct bnxt *bp); 8798 8799 static int bnxt_hwrm_if_change(struct bnxt *bp, bool up) 8800 { 8801 struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr; 8802 struct hwrm_func_drv_if_change_input req = {0}; 8803 bool resc_reinit = false, fw_reset = false; 8804 u32 flags = 0; 8805 int rc; 8806 8807 if (!(bp->fw_cap & BNXT_FW_CAP_IF_CHANGE)) 8808 return 0; 8809 8810 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_IF_CHANGE, -1, -1); 8811 if (up) 8812 req.flags = cpu_to_le32(FUNC_DRV_IF_CHANGE_REQ_FLAGS_UP); 8813 mutex_lock(&bp->hwrm_cmd_lock); 8814 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 8815 if (!rc) 8816 flags = le32_to_cpu(resp->flags); 8817 mutex_unlock(&bp->hwrm_cmd_lock); 8818 if (rc) 8819 return rc; 8820 8821 if (!up) 8822 return 0; 8823 8824 if (flags & FUNC_DRV_IF_CHANGE_RESP_FLAGS_RESC_CHANGE) 8825 resc_reinit = true; 8826 if (flags & FUNC_DRV_IF_CHANGE_RESP_FLAGS_HOT_FW_RESET_DONE) 8827 fw_reset = true; 8828 8829 if (test_bit(BNXT_STATE_IN_FW_RESET, &bp->state) && !fw_reset) { 8830 netdev_err(bp->dev, "RESET_DONE not set during FW reset.\n"); 8831 return -ENODEV; 8832 } 8833 if (resc_reinit || fw_reset) { 8834 if (fw_reset) { 8835 if (!test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) 8836 bnxt_ulp_stop(bp); 8837 bnxt_free_ctx_mem(bp); 8838 kfree(bp->ctx); 8839 bp->ctx = NULL; 8840 bnxt_dcb_free(bp); 8841 rc = bnxt_fw_init_one(bp); 8842 if (rc) { 8843 set_bit(BNXT_STATE_ABORT_ERR, &bp->state); 8844 return rc; 8845 } 8846 bnxt_clear_int_mode(bp); 8847 rc = bnxt_init_int_mode(bp); 8848 if (rc) { 8849 netdev_err(bp->dev, "init int mode failed\n"); 8850 return rc; 8851 } 8852 set_bit(BNXT_STATE_FW_RESET_DET, &bp->state); 8853 } 8854 if (BNXT_NEW_RM(bp)) { 8855 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 8856 8857 rc = bnxt_hwrm_func_resc_qcaps(bp, true); 8858 hw_resc->resv_cp_rings = 0; 8859 hw_resc->resv_stat_ctxs = 0; 8860 hw_resc->resv_irqs = 0; 8861 hw_resc->resv_tx_rings = 0; 8862 hw_resc->resv_rx_rings = 0; 8863 hw_resc->resv_hw_ring_grps = 0; 8864 hw_resc->resv_vnics = 0; 8865 if (!fw_reset) { 8866 bp->tx_nr_rings = 0; 8867 bp->rx_nr_rings = 0; 8868 } 8869 } 8870 } 8871 return 0; 8872 } 8873 8874 static int bnxt_hwrm_port_led_qcaps(struct bnxt *bp) 8875 { 8876 struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr; 8877 struct hwrm_port_led_qcaps_input req = {0}; 8878 struct bnxt_pf_info *pf = &bp->pf; 8879 int rc; 8880 8881 bp->num_leds = 0; 8882 if (BNXT_VF(bp) || bp->hwrm_spec_code < 0x10601) 8883 return 0; 8884 8885 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_LED_QCAPS, -1, -1); 8886 req.port_id = cpu_to_le16(pf->port_id); 8887 mutex_lock(&bp->hwrm_cmd_lock); 8888 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 8889 if (rc) { 8890 mutex_unlock(&bp->hwrm_cmd_lock); 8891 return rc; 8892 } 8893 if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) { 8894 int i; 8895 8896 bp->num_leds = resp->num_leds; 8897 memcpy(bp->leds, &resp->led0_id, sizeof(bp->leds[0]) * 8898 bp->num_leds); 8899 for (i = 0; i < bp->num_leds; i++) { 8900 struct bnxt_led_info *led = &bp->leds[i]; 8901 __le16 caps = led->led_state_caps; 8902 8903 if (!led->led_group_id || 8904 !BNXT_LED_ALT_BLINK_CAP(caps)) { 8905 bp->num_leds = 0; 8906 break; 8907 } 8908 } 8909 } 8910 mutex_unlock(&bp->hwrm_cmd_lock); 8911 return 0; 8912 } 8913 8914 int bnxt_hwrm_alloc_wol_fltr(struct bnxt *bp) 8915 { 8916 struct hwrm_wol_filter_alloc_input req = {0}; 8917 struct hwrm_wol_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr; 8918 int rc; 8919 8920 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_ALLOC, -1, -1); 8921 req.port_id = cpu_to_le16(bp->pf.port_id); 8922 req.wol_type = WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT; 8923 req.enables = cpu_to_le32(WOL_FILTER_ALLOC_REQ_ENABLES_MAC_ADDRESS); 8924 memcpy(req.mac_address, bp->dev->dev_addr, ETH_ALEN); 8925 mutex_lock(&bp->hwrm_cmd_lock); 8926 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 8927 if (!rc) 8928 bp->wol_filter_id = resp->wol_filter_id; 8929 mutex_unlock(&bp->hwrm_cmd_lock); 8930 return rc; 8931 } 8932 8933 int bnxt_hwrm_free_wol_fltr(struct bnxt *bp) 8934 { 8935 struct hwrm_wol_filter_free_input req = {0}; 8936 8937 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_FREE, -1, -1); 8938 req.port_id = cpu_to_le16(bp->pf.port_id); 8939 req.enables = cpu_to_le32(WOL_FILTER_FREE_REQ_ENABLES_WOL_FILTER_ID); 8940 req.wol_filter_id = bp->wol_filter_id; 8941 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 8942 } 8943 8944 static u16 bnxt_hwrm_get_wol_fltrs(struct bnxt *bp, u16 handle) 8945 { 8946 struct hwrm_wol_filter_qcfg_input req = {0}; 8947 struct hwrm_wol_filter_qcfg_output *resp = bp->hwrm_cmd_resp_addr; 8948 u16 next_handle = 0; 8949 int rc; 8950 8951 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_QCFG, -1, -1); 8952 req.port_id = cpu_to_le16(bp->pf.port_id); 8953 req.handle = cpu_to_le16(handle); 8954 mutex_lock(&bp->hwrm_cmd_lock); 8955 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 8956 if (!rc) { 8957 next_handle = le16_to_cpu(resp->next_handle); 8958 if (next_handle != 0) { 8959 if (resp->wol_type == 8960 WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT) { 8961 bp->wol = 1; 8962 bp->wol_filter_id = resp->wol_filter_id; 8963 } 8964 } 8965 } 8966 mutex_unlock(&bp->hwrm_cmd_lock); 8967 return next_handle; 8968 } 8969 8970 static void bnxt_get_wol_settings(struct bnxt *bp) 8971 { 8972 u16 handle = 0; 8973 8974 bp->wol = 0; 8975 if (!BNXT_PF(bp) || !(bp->flags & BNXT_FLAG_WOL_CAP)) 8976 return; 8977 8978 do { 8979 handle = bnxt_hwrm_get_wol_fltrs(bp, handle); 8980 } while (handle && handle != 0xffff); 8981 } 8982 8983 #ifdef CONFIG_BNXT_HWMON 8984 static ssize_t bnxt_show_temp(struct device *dev, 8985 struct device_attribute *devattr, char *buf) 8986 { 8987 struct hwrm_temp_monitor_query_input req = {0}; 8988 struct hwrm_temp_monitor_query_output *resp; 8989 struct bnxt *bp = dev_get_drvdata(dev); 8990 u32 temp = 0; 8991 8992 resp = bp->hwrm_cmd_resp_addr; 8993 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TEMP_MONITOR_QUERY, -1, -1); 8994 mutex_lock(&bp->hwrm_cmd_lock); 8995 if (!_hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT)) 8996 temp = resp->temp * 1000; /* display millidegree */ 8997 mutex_unlock(&bp->hwrm_cmd_lock); 8998 8999 return sprintf(buf, "%u\n", temp); 9000 } 9001 static SENSOR_DEVICE_ATTR(temp1_input, 0444, bnxt_show_temp, NULL, 0); 9002 9003 static struct attribute *bnxt_attrs[] = { 9004 &sensor_dev_attr_temp1_input.dev_attr.attr, 9005 NULL 9006 }; 9007 ATTRIBUTE_GROUPS(bnxt); 9008 9009 static void bnxt_hwmon_close(struct bnxt *bp) 9010 { 9011 if (bp->hwmon_dev) { 9012 hwmon_device_unregister(bp->hwmon_dev); 9013 bp->hwmon_dev = NULL; 9014 } 9015 } 9016 9017 static void bnxt_hwmon_open(struct bnxt *bp) 9018 { 9019 struct pci_dev *pdev = bp->pdev; 9020 9021 if (bp->hwmon_dev) 9022 return; 9023 9024 bp->hwmon_dev = hwmon_device_register_with_groups(&pdev->dev, 9025 DRV_MODULE_NAME, bp, 9026 bnxt_groups); 9027 if (IS_ERR(bp->hwmon_dev)) { 9028 bp->hwmon_dev = NULL; 9029 dev_warn(&pdev->dev, "Cannot register hwmon device\n"); 9030 } 9031 } 9032 #else 9033 static void bnxt_hwmon_close(struct bnxt *bp) 9034 { 9035 } 9036 9037 static void bnxt_hwmon_open(struct bnxt *bp) 9038 { 9039 } 9040 #endif 9041 9042 static bool bnxt_eee_config_ok(struct bnxt *bp) 9043 { 9044 struct ethtool_eee *eee = &bp->eee; 9045 struct bnxt_link_info *link_info = &bp->link_info; 9046 9047 if (!(bp->flags & BNXT_FLAG_EEE_CAP)) 9048 return true; 9049 9050 if (eee->eee_enabled) { 9051 u32 advertising = 9052 _bnxt_fw_to_ethtool_adv_spds(link_info->advertising, 0); 9053 9054 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) { 9055 eee->eee_enabled = 0; 9056 return false; 9057 } 9058 if (eee->advertised & ~advertising) { 9059 eee->advertised = advertising & eee->supported; 9060 return false; 9061 } 9062 } 9063 return true; 9064 } 9065 9066 static int bnxt_update_phy_setting(struct bnxt *bp) 9067 { 9068 int rc; 9069 bool update_link = false; 9070 bool update_pause = false; 9071 bool update_eee = false; 9072 struct bnxt_link_info *link_info = &bp->link_info; 9073 9074 rc = bnxt_update_link(bp, true); 9075 if (rc) { 9076 netdev_err(bp->dev, "failed to update link (rc: %x)\n", 9077 rc); 9078 return rc; 9079 } 9080 if (!BNXT_SINGLE_PF(bp)) 9081 return 0; 9082 9083 if ((link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) && 9084 (link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH) != 9085 link_info->req_flow_ctrl) 9086 update_pause = true; 9087 if (!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) && 9088 link_info->force_pause_setting != link_info->req_flow_ctrl) 9089 update_pause = true; 9090 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) { 9091 if (BNXT_AUTO_MODE(link_info->auto_mode)) 9092 update_link = true; 9093 if (link_info->req_link_speed != link_info->force_link_speed) 9094 update_link = true; 9095 if (link_info->req_duplex != link_info->duplex_setting) 9096 update_link = true; 9097 } else { 9098 if (link_info->auto_mode == BNXT_LINK_AUTO_NONE) 9099 update_link = true; 9100 if (link_info->advertising != link_info->auto_link_speeds) 9101 update_link = true; 9102 } 9103 9104 /* The last close may have shutdown the link, so need to call 9105 * PHY_CFG to bring it back up. 9106 */ 9107 if (!bp->link_info.link_up) 9108 update_link = true; 9109 9110 if (!bnxt_eee_config_ok(bp)) 9111 update_eee = true; 9112 9113 if (update_link) 9114 rc = bnxt_hwrm_set_link_setting(bp, update_pause, update_eee); 9115 else if (update_pause) 9116 rc = bnxt_hwrm_set_pause(bp); 9117 if (rc) { 9118 netdev_err(bp->dev, "failed to update phy setting (rc: %x)\n", 9119 rc); 9120 return rc; 9121 } 9122 9123 return rc; 9124 } 9125 9126 /* Common routine to pre-map certain register block to different GRC window. 9127 * A PF has 16 4K windows and a VF has 4 4K windows. However, only 15 windows 9128 * in PF and 3 windows in VF that can be customized to map in different 9129 * register blocks. 9130 */ 9131 static void bnxt_preset_reg_win(struct bnxt *bp) 9132 { 9133 if (BNXT_PF(bp)) { 9134 /* CAG registers map to GRC window #4 */ 9135 writel(BNXT_CAG_REG_BASE, 9136 bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 12); 9137 } 9138 } 9139 9140 static int bnxt_init_dflt_ring_mode(struct bnxt *bp); 9141 9142 static int __bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init) 9143 { 9144 int rc = 0; 9145 9146 bnxt_preset_reg_win(bp); 9147 netif_carrier_off(bp->dev); 9148 if (irq_re_init) { 9149 /* Reserve rings now if none were reserved at driver probe. */ 9150 rc = bnxt_init_dflt_ring_mode(bp); 9151 if (rc) { 9152 netdev_err(bp->dev, "Failed to reserve default rings at open\n"); 9153 return rc; 9154 } 9155 } 9156 rc = bnxt_reserve_rings(bp, irq_re_init); 9157 if (rc) 9158 return rc; 9159 if ((bp->flags & BNXT_FLAG_RFS) && 9160 !(bp->flags & BNXT_FLAG_USING_MSIX)) { 9161 /* disable RFS if falling back to INTA */ 9162 bp->dev->hw_features &= ~NETIF_F_NTUPLE; 9163 bp->flags &= ~BNXT_FLAG_RFS; 9164 } 9165 9166 rc = bnxt_alloc_mem(bp, irq_re_init); 9167 if (rc) { 9168 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc); 9169 goto open_err_free_mem; 9170 } 9171 9172 if (irq_re_init) { 9173 bnxt_init_napi(bp); 9174 rc = bnxt_request_irq(bp); 9175 if (rc) { 9176 netdev_err(bp->dev, "bnxt_request_irq err: %x\n", rc); 9177 goto open_err_irq; 9178 } 9179 } 9180 9181 bnxt_enable_napi(bp); 9182 bnxt_debug_dev_init(bp); 9183 9184 rc = bnxt_init_nic(bp, irq_re_init); 9185 if (rc) { 9186 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc); 9187 goto open_err; 9188 } 9189 9190 if (link_re_init) { 9191 mutex_lock(&bp->link_lock); 9192 rc = bnxt_update_phy_setting(bp); 9193 mutex_unlock(&bp->link_lock); 9194 if (rc) { 9195 netdev_warn(bp->dev, "failed to update phy settings\n"); 9196 if (BNXT_SINGLE_PF(bp)) { 9197 bp->link_info.phy_retry = true; 9198 bp->link_info.phy_retry_expires = 9199 jiffies + 5 * HZ; 9200 } 9201 } 9202 } 9203 9204 if (irq_re_init) 9205 udp_tunnel_get_rx_info(bp->dev); 9206 9207 set_bit(BNXT_STATE_OPEN, &bp->state); 9208 bnxt_enable_int(bp); 9209 /* Enable TX queues */ 9210 bnxt_tx_enable(bp); 9211 mod_timer(&bp->timer, jiffies + bp->current_interval); 9212 /* Poll link status and check for SFP+ module status */ 9213 bnxt_get_port_module_status(bp); 9214 9215 /* VF-reps may need to be re-opened after the PF is re-opened */ 9216 if (BNXT_PF(bp)) 9217 bnxt_vf_reps_open(bp); 9218 return 0; 9219 9220 open_err: 9221 bnxt_debug_dev_exit(bp); 9222 bnxt_disable_napi(bp); 9223 9224 open_err_irq: 9225 bnxt_del_napi(bp); 9226 9227 open_err_free_mem: 9228 bnxt_free_skbs(bp); 9229 bnxt_free_irq(bp); 9230 bnxt_free_mem(bp, true); 9231 return rc; 9232 } 9233 9234 /* rtnl_lock held */ 9235 int bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init) 9236 { 9237 int rc = 0; 9238 9239 rc = __bnxt_open_nic(bp, irq_re_init, link_re_init); 9240 if (rc) { 9241 netdev_err(bp->dev, "nic open fail (rc: %x)\n", rc); 9242 dev_close(bp->dev); 9243 } 9244 return rc; 9245 } 9246 9247 /* rtnl_lock held, open the NIC half way by allocating all resources, but 9248 * NAPI, IRQ, and TX are not enabled. This is mainly used for offline 9249 * self tests. 9250 */ 9251 int bnxt_half_open_nic(struct bnxt *bp) 9252 { 9253 int rc = 0; 9254 9255 rc = bnxt_alloc_mem(bp, false); 9256 if (rc) { 9257 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc); 9258 goto half_open_err; 9259 } 9260 rc = bnxt_init_nic(bp, false); 9261 if (rc) { 9262 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc); 9263 goto half_open_err; 9264 } 9265 return 0; 9266 9267 half_open_err: 9268 bnxt_free_skbs(bp); 9269 bnxt_free_mem(bp, false); 9270 dev_close(bp->dev); 9271 return rc; 9272 } 9273 9274 /* rtnl_lock held, this call can only be made after a previous successful 9275 * call to bnxt_half_open_nic(). 9276 */ 9277 void bnxt_half_close_nic(struct bnxt *bp) 9278 { 9279 bnxt_hwrm_resource_free(bp, false, false); 9280 bnxt_free_skbs(bp); 9281 bnxt_free_mem(bp, false); 9282 } 9283 9284 static void bnxt_reenable_sriov(struct bnxt *bp) 9285 { 9286 if (BNXT_PF(bp)) { 9287 struct bnxt_pf_info *pf = &bp->pf; 9288 int n = pf->active_vfs; 9289 9290 if (n) 9291 bnxt_cfg_hw_sriov(bp, &n, true); 9292 } 9293 } 9294 9295 static int bnxt_open(struct net_device *dev) 9296 { 9297 struct bnxt *bp = netdev_priv(dev); 9298 int rc; 9299 9300 if (test_bit(BNXT_STATE_ABORT_ERR, &bp->state)) { 9301 netdev_err(bp->dev, "A previous firmware reset did not complete, aborting\n"); 9302 return -ENODEV; 9303 } 9304 9305 rc = bnxt_hwrm_if_change(bp, true); 9306 if (rc) 9307 return rc; 9308 rc = __bnxt_open_nic(bp, true, true); 9309 if (rc) { 9310 bnxt_hwrm_if_change(bp, false); 9311 } else { 9312 if (test_and_clear_bit(BNXT_STATE_FW_RESET_DET, &bp->state)) { 9313 if (!test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) { 9314 bnxt_ulp_start(bp, 0); 9315 bnxt_reenable_sriov(bp); 9316 } 9317 } 9318 bnxt_hwmon_open(bp); 9319 } 9320 9321 return rc; 9322 } 9323 9324 static bool bnxt_drv_busy(struct bnxt *bp) 9325 { 9326 return (test_bit(BNXT_STATE_IN_SP_TASK, &bp->state) || 9327 test_bit(BNXT_STATE_READ_STATS, &bp->state)); 9328 } 9329 9330 static void bnxt_get_ring_stats(struct bnxt *bp, 9331 struct rtnl_link_stats64 *stats); 9332 9333 static void __bnxt_close_nic(struct bnxt *bp, bool irq_re_init, 9334 bool link_re_init) 9335 { 9336 /* Close the VF-reps before closing PF */ 9337 if (BNXT_PF(bp)) 9338 bnxt_vf_reps_close(bp); 9339 9340 /* Change device state to avoid TX queue wake up's */ 9341 bnxt_tx_disable(bp); 9342 9343 clear_bit(BNXT_STATE_OPEN, &bp->state); 9344 smp_mb__after_atomic(); 9345 while (bnxt_drv_busy(bp)) 9346 msleep(20); 9347 9348 /* Flush rings and and disable interrupts */ 9349 bnxt_shutdown_nic(bp, irq_re_init); 9350 9351 /* TODO CHIMP_FW: Link/PHY related cleanup if (link_re_init) */ 9352 9353 bnxt_debug_dev_exit(bp); 9354 bnxt_disable_napi(bp); 9355 del_timer_sync(&bp->timer); 9356 bnxt_free_skbs(bp); 9357 9358 /* Save ring stats before shutdown */ 9359 if (bp->bnapi && irq_re_init) 9360 bnxt_get_ring_stats(bp, &bp->net_stats_prev); 9361 if (irq_re_init) { 9362 bnxt_free_irq(bp); 9363 bnxt_del_napi(bp); 9364 } 9365 bnxt_free_mem(bp, irq_re_init); 9366 } 9367 9368 int bnxt_close_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init) 9369 { 9370 int rc = 0; 9371 9372 if (test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) { 9373 /* If we get here, it means firmware reset is in progress 9374 * while we are trying to close. We can safely proceed with 9375 * the close because we are holding rtnl_lock(). Some firmware 9376 * messages may fail as we proceed to close. We set the 9377 * ABORT_ERR flag here so that the FW reset thread will later 9378 * abort when it gets the rtnl_lock() and sees the flag. 9379 */ 9380 netdev_warn(bp->dev, "FW reset in progress during close, FW reset will be aborted\n"); 9381 set_bit(BNXT_STATE_ABORT_ERR, &bp->state); 9382 } 9383 9384 #ifdef CONFIG_BNXT_SRIOV 9385 if (bp->sriov_cfg) { 9386 rc = wait_event_interruptible_timeout(bp->sriov_cfg_wait, 9387 !bp->sriov_cfg, 9388 BNXT_SRIOV_CFG_WAIT_TMO); 9389 if (rc) 9390 netdev_warn(bp->dev, "timeout waiting for SRIOV config operation to complete!\n"); 9391 } 9392 #endif 9393 __bnxt_close_nic(bp, irq_re_init, link_re_init); 9394 return rc; 9395 } 9396 9397 static int bnxt_close(struct net_device *dev) 9398 { 9399 struct bnxt *bp = netdev_priv(dev); 9400 9401 bnxt_hwmon_close(bp); 9402 bnxt_close_nic(bp, true, true); 9403 bnxt_hwrm_shutdown_link(bp); 9404 bnxt_hwrm_if_change(bp, false); 9405 return 0; 9406 } 9407 9408 static int bnxt_hwrm_port_phy_read(struct bnxt *bp, u16 phy_addr, u16 reg, 9409 u16 *val) 9410 { 9411 struct hwrm_port_phy_mdio_read_output *resp = bp->hwrm_cmd_resp_addr; 9412 struct hwrm_port_phy_mdio_read_input req = {0}; 9413 int rc; 9414 9415 if (bp->hwrm_spec_code < 0x10a00) 9416 return -EOPNOTSUPP; 9417 9418 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_MDIO_READ, -1, -1); 9419 req.port_id = cpu_to_le16(bp->pf.port_id); 9420 req.phy_addr = phy_addr; 9421 req.reg_addr = cpu_to_le16(reg & 0x1f); 9422 if (mdio_phy_id_is_c45(phy_addr)) { 9423 req.cl45_mdio = 1; 9424 req.phy_addr = mdio_phy_id_prtad(phy_addr); 9425 req.dev_addr = mdio_phy_id_devad(phy_addr); 9426 req.reg_addr = cpu_to_le16(reg); 9427 } 9428 9429 mutex_lock(&bp->hwrm_cmd_lock); 9430 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 9431 if (!rc) 9432 *val = le16_to_cpu(resp->reg_data); 9433 mutex_unlock(&bp->hwrm_cmd_lock); 9434 return rc; 9435 } 9436 9437 static int bnxt_hwrm_port_phy_write(struct bnxt *bp, u16 phy_addr, u16 reg, 9438 u16 val) 9439 { 9440 struct hwrm_port_phy_mdio_write_input req = {0}; 9441 9442 if (bp->hwrm_spec_code < 0x10a00) 9443 return -EOPNOTSUPP; 9444 9445 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_MDIO_WRITE, -1, -1); 9446 req.port_id = cpu_to_le16(bp->pf.port_id); 9447 req.phy_addr = phy_addr; 9448 req.reg_addr = cpu_to_le16(reg & 0x1f); 9449 if (mdio_phy_id_is_c45(phy_addr)) { 9450 req.cl45_mdio = 1; 9451 req.phy_addr = mdio_phy_id_prtad(phy_addr); 9452 req.dev_addr = mdio_phy_id_devad(phy_addr); 9453 req.reg_addr = cpu_to_le16(reg); 9454 } 9455 req.reg_data = cpu_to_le16(val); 9456 9457 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 9458 } 9459 9460 /* rtnl_lock held */ 9461 static int bnxt_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 9462 { 9463 struct mii_ioctl_data *mdio = if_mii(ifr); 9464 struct bnxt *bp = netdev_priv(dev); 9465 int rc; 9466 9467 switch (cmd) { 9468 case SIOCGMIIPHY: 9469 mdio->phy_id = bp->link_info.phy_addr; 9470 9471 /* fallthru */ 9472 case SIOCGMIIREG: { 9473 u16 mii_regval = 0; 9474 9475 if (!netif_running(dev)) 9476 return -EAGAIN; 9477 9478 rc = bnxt_hwrm_port_phy_read(bp, mdio->phy_id, mdio->reg_num, 9479 &mii_regval); 9480 mdio->val_out = mii_regval; 9481 return rc; 9482 } 9483 9484 case SIOCSMIIREG: 9485 if (!netif_running(dev)) 9486 return -EAGAIN; 9487 9488 return bnxt_hwrm_port_phy_write(bp, mdio->phy_id, mdio->reg_num, 9489 mdio->val_in); 9490 9491 default: 9492 /* do nothing */ 9493 break; 9494 } 9495 return -EOPNOTSUPP; 9496 } 9497 9498 static void bnxt_get_ring_stats(struct bnxt *bp, 9499 struct rtnl_link_stats64 *stats) 9500 { 9501 int i; 9502 9503 9504 for (i = 0; i < bp->cp_nr_rings; i++) { 9505 struct bnxt_napi *bnapi = bp->bnapi[i]; 9506 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 9507 struct ctx_hw_stats *hw_stats = cpr->hw_stats; 9508 9509 stats->rx_packets += le64_to_cpu(hw_stats->rx_ucast_pkts); 9510 stats->rx_packets += le64_to_cpu(hw_stats->rx_mcast_pkts); 9511 stats->rx_packets += le64_to_cpu(hw_stats->rx_bcast_pkts); 9512 9513 stats->tx_packets += le64_to_cpu(hw_stats->tx_ucast_pkts); 9514 stats->tx_packets += le64_to_cpu(hw_stats->tx_mcast_pkts); 9515 stats->tx_packets += le64_to_cpu(hw_stats->tx_bcast_pkts); 9516 9517 stats->rx_bytes += le64_to_cpu(hw_stats->rx_ucast_bytes); 9518 stats->rx_bytes += le64_to_cpu(hw_stats->rx_mcast_bytes); 9519 stats->rx_bytes += le64_to_cpu(hw_stats->rx_bcast_bytes); 9520 9521 stats->tx_bytes += le64_to_cpu(hw_stats->tx_ucast_bytes); 9522 stats->tx_bytes += le64_to_cpu(hw_stats->tx_mcast_bytes); 9523 stats->tx_bytes += le64_to_cpu(hw_stats->tx_bcast_bytes); 9524 9525 stats->rx_missed_errors += 9526 le64_to_cpu(hw_stats->rx_discard_pkts); 9527 9528 stats->multicast += le64_to_cpu(hw_stats->rx_mcast_pkts); 9529 9530 stats->tx_dropped += le64_to_cpu(hw_stats->tx_drop_pkts); 9531 } 9532 } 9533 9534 static void bnxt_add_prev_stats(struct bnxt *bp, 9535 struct rtnl_link_stats64 *stats) 9536 { 9537 struct rtnl_link_stats64 *prev_stats = &bp->net_stats_prev; 9538 9539 stats->rx_packets += prev_stats->rx_packets; 9540 stats->tx_packets += prev_stats->tx_packets; 9541 stats->rx_bytes += prev_stats->rx_bytes; 9542 stats->tx_bytes += prev_stats->tx_bytes; 9543 stats->rx_missed_errors += prev_stats->rx_missed_errors; 9544 stats->multicast += prev_stats->multicast; 9545 stats->tx_dropped += prev_stats->tx_dropped; 9546 } 9547 9548 static void 9549 bnxt_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) 9550 { 9551 struct bnxt *bp = netdev_priv(dev); 9552 9553 set_bit(BNXT_STATE_READ_STATS, &bp->state); 9554 /* Make sure bnxt_close_nic() sees that we are reading stats before 9555 * we check the BNXT_STATE_OPEN flag. 9556 */ 9557 smp_mb__after_atomic(); 9558 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) { 9559 clear_bit(BNXT_STATE_READ_STATS, &bp->state); 9560 *stats = bp->net_stats_prev; 9561 return; 9562 } 9563 9564 bnxt_get_ring_stats(bp, stats); 9565 bnxt_add_prev_stats(bp, stats); 9566 9567 if (bp->flags & BNXT_FLAG_PORT_STATS) { 9568 struct rx_port_stats *rx = bp->hw_rx_port_stats; 9569 struct tx_port_stats *tx = bp->hw_tx_port_stats; 9570 9571 stats->rx_crc_errors = le64_to_cpu(rx->rx_fcs_err_frames); 9572 stats->rx_frame_errors = le64_to_cpu(rx->rx_align_err_frames); 9573 stats->rx_length_errors = le64_to_cpu(rx->rx_undrsz_frames) + 9574 le64_to_cpu(rx->rx_ovrsz_frames) + 9575 le64_to_cpu(rx->rx_runt_frames); 9576 stats->rx_errors = le64_to_cpu(rx->rx_false_carrier_frames) + 9577 le64_to_cpu(rx->rx_jbr_frames); 9578 stats->collisions = le64_to_cpu(tx->tx_total_collisions); 9579 stats->tx_fifo_errors = le64_to_cpu(tx->tx_fifo_underruns); 9580 stats->tx_errors = le64_to_cpu(tx->tx_err); 9581 } 9582 clear_bit(BNXT_STATE_READ_STATS, &bp->state); 9583 } 9584 9585 static bool bnxt_mc_list_updated(struct bnxt *bp, u32 *rx_mask) 9586 { 9587 struct net_device *dev = bp->dev; 9588 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 9589 struct netdev_hw_addr *ha; 9590 u8 *haddr; 9591 int mc_count = 0; 9592 bool update = false; 9593 int off = 0; 9594 9595 netdev_for_each_mc_addr(ha, dev) { 9596 if (mc_count >= BNXT_MAX_MC_ADDRS) { 9597 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST; 9598 vnic->mc_list_count = 0; 9599 return false; 9600 } 9601 haddr = ha->addr; 9602 if (!ether_addr_equal(haddr, vnic->mc_list + off)) { 9603 memcpy(vnic->mc_list + off, haddr, ETH_ALEN); 9604 update = true; 9605 } 9606 off += ETH_ALEN; 9607 mc_count++; 9608 } 9609 if (mc_count) 9610 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_MCAST; 9611 9612 if (mc_count != vnic->mc_list_count) { 9613 vnic->mc_list_count = mc_count; 9614 update = true; 9615 } 9616 return update; 9617 } 9618 9619 static bool bnxt_uc_list_updated(struct bnxt *bp) 9620 { 9621 struct net_device *dev = bp->dev; 9622 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 9623 struct netdev_hw_addr *ha; 9624 int off = 0; 9625 9626 if (netdev_uc_count(dev) != (vnic->uc_filter_count - 1)) 9627 return true; 9628 9629 netdev_for_each_uc_addr(ha, dev) { 9630 if (!ether_addr_equal(ha->addr, vnic->uc_list + off)) 9631 return true; 9632 9633 off += ETH_ALEN; 9634 } 9635 return false; 9636 } 9637 9638 static void bnxt_set_rx_mode(struct net_device *dev) 9639 { 9640 struct bnxt *bp = netdev_priv(dev); 9641 struct bnxt_vnic_info *vnic; 9642 bool mc_update = false; 9643 bool uc_update; 9644 u32 mask; 9645 9646 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) 9647 return; 9648 9649 vnic = &bp->vnic_info[0]; 9650 mask = vnic->rx_mask; 9651 mask &= ~(CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS | 9652 CFA_L2_SET_RX_MASK_REQ_MASK_MCAST | 9653 CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST | 9654 CFA_L2_SET_RX_MASK_REQ_MASK_BCAST); 9655 9656 if ((dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp)) 9657 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS; 9658 9659 uc_update = bnxt_uc_list_updated(bp); 9660 9661 if (dev->flags & IFF_BROADCAST) 9662 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_BCAST; 9663 if (dev->flags & IFF_ALLMULTI) { 9664 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST; 9665 vnic->mc_list_count = 0; 9666 } else { 9667 mc_update = bnxt_mc_list_updated(bp, &mask); 9668 } 9669 9670 if (mask != vnic->rx_mask || uc_update || mc_update) { 9671 vnic->rx_mask = mask; 9672 9673 set_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event); 9674 bnxt_queue_sp_work(bp); 9675 } 9676 } 9677 9678 static int bnxt_cfg_rx_mode(struct bnxt *bp) 9679 { 9680 struct net_device *dev = bp->dev; 9681 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 9682 struct netdev_hw_addr *ha; 9683 int i, off = 0, rc; 9684 bool uc_update; 9685 9686 netif_addr_lock_bh(dev); 9687 uc_update = bnxt_uc_list_updated(bp); 9688 netif_addr_unlock_bh(dev); 9689 9690 if (!uc_update) 9691 goto skip_uc; 9692 9693 mutex_lock(&bp->hwrm_cmd_lock); 9694 for (i = 1; i < vnic->uc_filter_count; i++) { 9695 struct hwrm_cfa_l2_filter_free_input req = {0}; 9696 9697 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_FREE, -1, 9698 -1); 9699 9700 req.l2_filter_id = vnic->fw_l2_filter_id[i]; 9701 9702 rc = _hwrm_send_message(bp, &req, sizeof(req), 9703 HWRM_CMD_TIMEOUT); 9704 } 9705 mutex_unlock(&bp->hwrm_cmd_lock); 9706 9707 vnic->uc_filter_count = 1; 9708 9709 netif_addr_lock_bh(dev); 9710 if (netdev_uc_count(dev) > (BNXT_MAX_UC_ADDRS - 1)) { 9711 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS; 9712 } else { 9713 netdev_for_each_uc_addr(ha, dev) { 9714 memcpy(vnic->uc_list + off, ha->addr, ETH_ALEN); 9715 off += ETH_ALEN; 9716 vnic->uc_filter_count++; 9717 } 9718 } 9719 netif_addr_unlock_bh(dev); 9720 9721 for (i = 1, off = 0; i < vnic->uc_filter_count; i++, off += ETH_ALEN) { 9722 rc = bnxt_hwrm_set_vnic_filter(bp, 0, i, vnic->uc_list + off); 9723 if (rc) { 9724 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n", 9725 rc); 9726 vnic->uc_filter_count = i; 9727 return rc; 9728 } 9729 } 9730 9731 skip_uc: 9732 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0); 9733 if (rc && vnic->mc_list_count) { 9734 netdev_info(bp->dev, "Failed setting MC filters rc: %d, turning on ALL_MCAST mode\n", 9735 rc); 9736 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST; 9737 vnic->mc_list_count = 0; 9738 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0); 9739 } 9740 if (rc) 9741 netdev_err(bp->dev, "HWRM cfa l2 rx mask failure rc: %d\n", 9742 rc); 9743 9744 return rc; 9745 } 9746 9747 static bool bnxt_can_reserve_rings(struct bnxt *bp) 9748 { 9749 #ifdef CONFIG_BNXT_SRIOV 9750 if (BNXT_NEW_RM(bp) && BNXT_VF(bp)) { 9751 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 9752 9753 /* No minimum rings were provisioned by the PF. Don't 9754 * reserve rings by default when device is down. 9755 */ 9756 if (hw_resc->min_tx_rings || hw_resc->resv_tx_rings) 9757 return true; 9758 9759 if (!netif_running(bp->dev)) 9760 return false; 9761 } 9762 #endif 9763 return true; 9764 } 9765 9766 /* If the chip and firmware supports RFS */ 9767 static bool bnxt_rfs_supported(struct bnxt *bp) 9768 { 9769 if (bp->flags & BNXT_FLAG_CHIP_P5) { 9770 if (bp->fw_cap & BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V2) 9771 return true; 9772 return false; 9773 } 9774 if (BNXT_PF(bp) && !BNXT_CHIP_TYPE_NITRO_A0(bp)) 9775 return true; 9776 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP) 9777 return true; 9778 return false; 9779 } 9780 9781 /* If runtime conditions support RFS */ 9782 static bool bnxt_rfs_capable(struct bnxt *bp) 9783 { 9784 #ifdef CONFIG_RFS_ACCEL 9785 int vnics, max_vnics, max_rss_ctxs; 9786 9787 if (bp->flags & BNXT_FLAG_CHIP_P5) 9788 return bnxt_rfs_supported(bp); 9789 if (!(bp->flags & BNXT_FLAG_MSIX_CAP) || !bnxt_can_reserve_rings(bp)) 9790 return false; 9791 9792 vnics = 1 + bp->rx_nr_rings; 9793 max_vnics = bnxt_get_max_func_vnics(bp); 9794 max_rss_ctxs = bnxt_get_max_func_rss_ctxs(bp); 9795 9796 /* RSS contexts not a limiting factor */ 9797 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP) 9798 max_rss_ctxs = max_vnics; 9799 if (vnics > max_vnics || vnics > max_rss_ctxs) { 9800 if (bp->rx_nr_rings > 1) 9801 netdev_warn(bp->dev, 9802 "Not enough resources to support NTUPLE filters, enough resources for up to %d rx rings\n", 9803 min(max_rss_ctxs - 1, max_vnics - 1)); 9804 return false; 9805 } 9806 9807 if (!BNXT_NEW_RM(bp)) 9808 return true; 9809 9810 if (vnics == bp->hw_resc.resv_vnics) 9811 return true; 9812 9813 bnxt_hwrm_reserve_rings(bp, 0, 0, 0, 0, 0, vnics); 9814 if (vnics <= bp->hw_resc.resv_vnics) 9815 return true; 9816 9817 netdev_warn(bp->dev, "Unable to reserve resources to support NTUPLE filters.\n"); 9818 bnxt_hwrm_reserve_rings(bp, 0, 0, 0, 0, 0, 1); 9819 return false; 9820 #else 9821 return false; 9822 #endif 9823 } 9824 9825 static netdev_features_t bnxt_fix_features(struct net_device *dev, 9826 netdev_features_t features) 9827 { 9828 struct bnxt *bp = netdev_priv(dev); 9829 netdev_features_t vlan_features; 9830 9831 if ((features & NETIF_F_NTUPLE) && !bnxt_rfs_capable(bp)) 9832 features &= ~NETIF_F_NTUPLE; 9833 9834 if (bp->flags & BNXT_FLAG_NO_AGG_RINGS) 9835 features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW); 9836 9837 if (!(features & NETIF_F_GRO)) 9838 features &= ~NETIF_F_GRO_HW; 9839 9840 if (features & NETIF_F_GRO_HW) 9841 features &= ~NETIF_F_LRO; 9842 9843 /* Both CTAG and STAG VLAN accelaration on the RX side have to be 9844 * turned on or off together. 9845 */ 9846 vlan_features = features & (NETIF_F_HW_VLAN_CTAG_RX | 9847 NETIF_F_HW_VLAN_STAG_RX); 9848 if (vlan_features != (NETIF_F_HW_VLAN_CTAG_RX | 9849 NETIF_F_HW_VLAN_STAG_RX)) { 9850 if (dev->features & NETIF_F_HW_VLAN_CTAG_RX) 9851 features &= ~(NETIF_F_HW_VLAN_CTAG_RX | 9852 NETIF_F_HW_VLAN_STAG_RX); 9853 else if (vlan_features) 9854 features |= NETIF_F_HW_VLAN_CTAG_RX | 9855 NETIF_F_HW_VLAN_STAG_RX; 9856 } 9857 #ifdef CONFIG_BNXT_SRIOV 9858 if (BNXT_VF(bp)) { 9859 if (bp->vf.vlan) { 9860 features &= ~(NETIF_F_HW_VLAN_CTAG_RX | 9861 NETIF_F_HW_VLAN_STAG_RX); 9862 } 9863 } 9864 #endif 9865 return features; 9866 } 9867 9868 static int bnxt_set_features(struct net_device *dev, netdev_features_t features) 9869 { 9870 struct bnxt *bp = netdev_priv(dev); 9871 u32 flags = bp->flags; 9872 u32 changes; 9873 int rc = 0; 9874 bool re_init = false; 9875 bool update_tpa = false; 9876 9877 flags &= ~BNXT_FLAG_ALL_CONFIG_FEATS; 9878 if (features & NETIF_F_GRO_HW) 9879 flags |= BNXT_FLAG_GRO; 9880 else if (features & NETIF_F_LRO) 9881 flags |= BNXT_FLAG_LRO; 9882 9883 if (bp->flags & BNXT_FLAG_NO_AGG_RINGS) 9884 flags &= ~BNXT_FLAG_TPA; 9885 9886 if (features & NETIF_F_HW_VLAN_CTAG_RX) 9887 flags |= BNXT_FLAG_STRIP_VLAN; 9888 9889 if (features & NETIF_F_NTUPLE) 9890 flags |= BNXT_FLAG_RFS; 9891 9892 changes = flags ^ bp->flags; 9893 if (changes & BNXT_FLAG_TPA) { 9894 update_tpa = true; 9895 if ((bp->flags & BNXT_FLAG_TPA) == 0 || 9896 (flags & BNXT_FLAG_TPA) == 0 || 9897 (bp->flags & BNXT_FLAG_CHIP_P5)) 9898 re_init = true; 9899 } 9900 9901 if (changes & ~BNXT_FLAG_TPA) 9902 re_init = true; 9903 9904 if (flags != bp->flags) { 9905 u32 old_flags = bp->flags; 9906 9907 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) { 9908 bp->flags = flags; 9909 if (update_tpa) 9910 bnxt_set_ring_params(bp); 9911 return rc; 9912 } 9913 9914 if (re_init) { 9915 bnxt_close_nic(bp, false, false); 9916 bp->flags = flags; 9917 if (update_tpa) 9918 bnxt_set_ring_params(bp); 9919 9920 return bnxt_open_nic(bp, false, false); 9921 } 9922 if (update_tpa) { 9923 bp->flags = flags; 9924 rc = bnxt_set_tpa(bp, 9925 (flags & BNXT_FLAG_TPA) ? 9926 true : false); 9927 if (rc) 9928 bp->flags = old_flags; 9929 } 9930 } 9931 return rc; 9932 } 9933 9934 static int bnxt_dbg_hwrm_ring_info_get(struct bnxt *bp, u8 ring_type, 9935 u32 ring_id, u32 *prod, u32 *cons) 9936 { 9937 struct hwrm_dbg_ring_info_get_output *resp = bp->hwrm_cmd_resp_addr; 9938 struct hwrm_dbg_ring_info_get_input req = {0}; 9939 int rc; 9940 9941 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_DBG_RING_INFO_GET, -1, -1); 9942 req.ring_type = ring_type; 9943 req.fw_ring_id = cpu_to_le32(ring_id); 9944 mutex_lock(&bp->hwrm_cmd_lock); 9945 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 9946 if (!rc) { 9947 *prod = le32_to_cpu(resp->producer_index); 9948 *cons = le32_to_cpu(resp->consumer_index); 9949 } 9950 mutex_unlock(&bp->hwrm_cmd_lock); 9951 return rc; 9952 } 9953 9954 static void bnxt_dump_tx_sw_state(struct bnxt_napi *bnapi) 9955 { 9956 struct bnxt_tx_ring_info *txr = bnapi->tx_ring; 9957 int i = bnapi->index; 9958 9959 if (!txr) 9960 return; 9961 9962 netdev_info(bnapi->bp->dev, "[%d]: tx{fw_ring: %d prod: %x cons: %x}\n", 9963 i, txr->tx_ring_struct.fw_ring_id, txr->tx_prod, 9964 txr->tx_cons); 9965 } 9966 9967 static void bnxt_dump_rx_sw_state(struct bnxt_napi *bnapi) 9968 { 9969 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 9970 int i = bnapi->index; 9971 9972 if (!rxr) 9973 return; 9974 9975 netdev_info(bnapi->bp->dev, "[%d]: rx{fw_ring: %d prod: %x} rx_agg{fw_ring: %d agg_prod: %x sw_agg_prod: %x}\n", 9976 i, rxr->rx_ring_struct.fw_ring_id, rxr->rx_prod, 9977 rxr->rx_agg_ring_struct.fw_ring_id, rxr->rx_agg_prod, 9978 rxr->rx_sw_agg_prod); 9979 } 9980 9981 static void bnxt_dump_cp_sw_state(struct bnxt_napi *bnapi) 9982 { 9983 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 9984 int i = bnapi->index; 9985 9986 netdev_info(bnapi->bp->dev, "[%d]: cp{fw_ring: %d raw_cons: %x}\n", 9987 i, cpr->cp_ring_struct.fw_ring_id, cpr->cp_raw_cons); 9988 } 9989 9990 static void bnxt_dbg_dump_states(struct bnxt *bp) 9991 { 9992 int i; 9993 struct bnxt_napi *bnapi; 9994 9995 for (i = 0; i < bp->cp_nr_rings; i++) { 9996 bnapi = bp->bnapi[i]; 9997 if (netif_msg_drv(bp)) { 9998 bnxt_dump_tx_sw_state(bnapi); 9999 bnxt_dump_rx_sw_state(bnapi); 10000 bnxt_dump_cp_sw_state(bnapi); 10001 } 10002 } 10003 } 10004 10005 static void bnxt_reset_task(struct bnxt *bp, bool silent) 10006 { 10007 if (!silent) 10008 bnxt_dbg_dump_states(bp); 10009 if (netif_running(bp->dev)) { 10010 int rc; 10011 10012 if (silent) { 10013 bnxt_close_nic(bp, false, false); 10014 bnxt_open_nic(bp, false, false); 10015 } else { 10016 bnxt_ulp_stop(bp); 10017 bnxt_close_nic(bp, true, false); 10018 rc = bnxt_open_nic(bp, true, false); 10019 bnxt_ulp_start(bp, rc); 10020 } 10021 } 10022 } 10023 10024 static void bnxt_tx_timeout(struct net_device *dev, unsigned int txqueue) 10025 { 10026 struct bnxt *bp = netdev_priv(dev); 10027 10028 netdev_err(bp->dev, "TX timeout detected, starting reset task!\n"); 10029 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event); 10030 bnxt_queue_sp_work(bp); 10031 } 10032 10033 static void bnxt_fw_health_check(struct bnxt *bp) 10034 { 10035 struct bnxt_fw_health *fw_health = bp->fw_health; 10036 u32 val; 10037 10038 if (!fw_health->enabled || test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) 10039 return; 10040 10041 if (fw_health->tmr_counter) { 10042 fw_health->tmr_counter--; 10043 return; 10044 } 10045 10046 val = bnxt_fw_health_readl(bp, BNXT_FW_HEARTBEAT_REG); 10047 if (val == fw_health->last_fw_heartbeat) 10048 goto fw_reset; 10049 10050 fw_health->last_fw_heartbeat = val; 10051 10052 val = bnxt_fw_health_readl(bp, BNXT_FW_RESET_CNT_REG); 10053 if (val != fw_health->last_fw_reset_cnt) 10054 goto fw_reset; 10055 10056 fw_health->tmr_counter = fw_health->tmr_multiplier; 10057 return; 10058 10059 fw_reset: 10060 set_bit(BNXT_FW_EXCEPTION_SP_EVENT, &bp->sp_event); 10061 bnxt_queue_sp_work(bp); 10062 } 10063 10064 static void bnxt_timer(struct timer_list *t) 10065 { 10066 struct bnxt *bp = from_timer(bp, t, timer); 10067 struct net_device *dev = bp->dev; 10068 10069 if (!netif_running(dev) || !test_bit(BNXT_STATE_OPEN, &bp->state)) 10070 return; 10071 10072 if (atomic_read(&bp->intr_sem) != 0) 10073 goto bnxt_restart_timer; 10074 10075 if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY) 10076 bnxt_fw_health_check(bp); 10077 10078 if (bp->link_info.link_up && (bp->flags & BNXT_FLAG_PORT_STATS) && 10079 bp->stats_coal_ticks) { 10080 set_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event); 10081 bnxt_queue_sp_work(bp); 10082 } 10083 10084 if (bnxt_tc_flower_enabled(bp)) { 10085 set_bit(BNXT_FLOW_STATS_SP_EVENT, &bp->sp_event); 10086 bnxt_queue_sp_work(bp); 10087 } 10088 10089 #ifdef CONFIG_RFS_ACCEL 10090 if ((bp->flags & BNXT_FLAG_RFS) && bp->ntp_fltr_count) { 10091 set_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event); 10092 bnxt_queue_sp_work(bp); 10093 } 10094 #endif /*CONFIG_RFS_ACCEL*/ 10095 10096 if (bp->link_info.phy_retry) { 10097 if (time_after(jiffies, bp->link_info.phy_retry_expires)) { 10098 bp->link_info.phy_retry = false; 10099 netdev_warn(bp->dev, "failed to update phy settings after maximum retries.\n"); 10100 } else { 10101 set_bit(BNXT_UPDATE_PHY_SP_EVENT, &bp->sp_event); 10102 bnxt_queue_sp_work(bp); 10103 } 10104 } 10105 10106 if ((bp->flags & BNXT_FLAG_CHIP_P5) && !bp->chip_rev && 10107 netif_carrier_ok(dev)) { 10108 set_bit(BNXT_RING_COAL_NOW_SP_EVENT, &bp->sp_event); 10109 bnxt_queue_sp_work(bp); 10110 } 10111 bnxt_restart_timer: 10112 mod_timer(&bp->timer, jiffies + bp->current_interval); 10113 } 10114 10115 static void bnxt_rtnl_lock_sp(struct bnxt *bp) 10116 { 10117 /* We are called from bnxt_sp_task which has BNXT_STATE_IN_SP_TASK 10118 * set. If the device is being closed, bnxt_close() may be holding 10119 * rtnl() and waiting for BNXT_STATE_IN_SP_TASK to clear. So we 10120 * must clear BNXT_STATE_IN_SP_TASK before holding rtnl(). 10121 */ 10122 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state); 10123 rtnl_lock(); 10124 } 10125 10126 static void bnxt_rtnl_unlock_sp(struct bnxt *bp) 10127 { 10128 set_bit(BNXT_STATE_IN_SP_TASK, &bp->state); 10129 rtnl_unlock(); 10130 } 10131 10132 /* Only called from bnxt_sp_task() */ 10133 static void bnxt_reset(struct bnxt *bp, bool silent) 10134 { 10135 bnxt_rtnl_lock_sp(bp); 10136 if (test_bit(BNXT_STATE_OPEN, &bp->state)) 10137 bnxt_reset_task(bp, silent); 10138 bnxt_rtnl_unlock_sp(bp); 10139 } 10140 10141 static void bnxt_fw_reset_close(struct bnxt *bp) 10142 { 10143 bnxt_ulp_stop(bp); 10144 /* When firmware is fatal state, disable PCI device to prevent 10145 * any potential bad DMAs before freeing kernel memory. 10146 */ 10147 if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state)) 10148 pci_disable_device(bp->pdev); 10149 __bnxt_close_nic(bp, true, false); 10150 bnxt_clear_int_mode(bp); 10151 bnxt_hwrm_func_drv_unrgtr(bp); 10152 if (pci_is_enabled(bp->pdev)) 10153 pci_disable_device(bp->pdev); 10154 bnxt_free_ctx_mem(bp); 10155 kfree(bp->ctx); 10156 bp->ctx = NULL; 10157 } 10158 10159 static bool is_bnxt_fw_ok(struct bnxt *bp) 10160 { 10161 struct bnxt_fw_health *fw_health = bp->fw_health; 10162 bool no_heartbeat = false, has_reset = false; 10163 u32 val; 10164 10165 val = bnxt_fw_health_readl(bp, BNXT_FW_HEARTBEAT_REG); 10166 if (val == fw_health->last_fw_heartbeat) 10167 no_heartbeat = true; 10168 10169 val = bnxt_fw_health_readl(bp, BNXT_FW_RESET_CNT_REG); 10170 if (val != fw_health->last_fw_reset_cnt) 10171 has_reset = true; 10172 10173 if (!no_heartbeat && has_reset) 10174 return true; 10175 10176 return false; 10177 } 10178 10179 /* rtnl_lock is acquired before calling this function */ 10180 static void bnxt_force_fw_reset(struct bnxt *bp) 10181 { 10182 struct bnxt_fw_health *fw_health = bp->fw_health; 10183 u32 wait_dsecs; 10184 10185 if (!test_bit(BNXT_STATE_OPEN, &bp->state) || 10186 test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) 10187 return; 10188 10189 set_bit(BNXT_STATE_IN_FW_RESET, &bp->state); 10190 bnxt_fw_reset_close(bp); 10191 wait_dsecs = fw_health->master_func_wait_dsecs; 10192 if (fw_health->master) { 10193 if (fw_health->flags & ERROR_RECOVERY_QCFG_RESP_FLAGS_CO_CPU) 10194 wait_dsecs = 0; 10195 bp->fw_reset_state = BNXT_FW_RESET_STATE_RESET_FW; 10196 } else { 10197 bp->fw_reset_timestamp = jiffies + wait_dsecs * HZ / 10; 10198 wait_dsecs = fw_health->normal_func_wait_dsecs; 10199 bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV; 10200 } 10201 10202 bp->fw_reset_min_dsecs = fw_health->post_reset_wait_dsecs; 10203 bp->fw_reset_max_dsecs = fw_health->post_reset_max_wait_dsecs; 10204 bnxt_queue_fw_reset_work(bp, wait_dsecs * HZ / 10); 10205 } 10206 10207 void bnxt_fw_exception(struct bnxt *bp) 10208 { 10209 netdev_warn(bp->dev, "Detected firmware fatal condition, initiating reset\n"); 10210 set_bit(BNXT_STATE_FW_FATAL_COND, &bp->state); 10211 bnxt_rtnl_lock_sp(bp); 10212 bnxt_force_fw_reset(bp); 10213 bnxt_rtnl_unlock_sp(bp); 10214 } 10215 10216 /* Returns the number of registered VFs, or 1 if VF configuration is pending, or 10217 * < 0 on error. 10218 */ 10219 static int bnxt_get_registered_vfs(struct bnxt *bp) 10220 { 10221 #ifdef CONFIG_BNXT_SRIOV 10222 int rc; 10223 10224 if (!BNXT_PF(bp)) 10225 return 0; 10226 10227 rc = bnxt_hwrm_func_qcfg(bp); 10228 if (rc) { 10229 netdev_err(bp->dev, "func_qcfg cmd failed, rc = %d\n", rc); 10230 return rc; 10231 } 10232 if (bp->pf.registered_vfs) 10233 return bp->pf.registered_vfs; 10234 if (bp->sriov_cfg) 10235 return 1; 10236 #endif 10237 return 0; 10238 } 10239 10240 void bnxt_fw_reset(struct bnxt *bp) 10241 { 10242 bnxt_rtnl_lock_sp(bp); 10243 if (test_bit(BNXT_STATE_OPEN, &bp->state) && 10244 !test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) { 10245 int n = 0, tmo; 10246 10247 set_bit(BNXT_STATE_IN_FW_RESET, &bp->state); 10248 if (bp->pf.active_vfs && 10249 !test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state)) 10250 n = bnxt_get_registered_vfs(bp); 10251 if (n < 0) { 10252 netdev_err(bp->dev, "Firmware reset aborted, rc = %d\n", 10253 n); 10254 clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state); 10255 dev_close(bp->dev); 10256 goto fw_reset_exit; 10257 } else if (n > 0) { 10258 u16 vf_tmo_dsecs = n * 10; 10259 10260 if (bp->fw_reset_max_dsecs < vf_tmo_dsecs) 10261 bp->fw_reset_max_dsecs = vf_tmo_dsecs; 10262 bp->fw_reset_state = 10263 BNXT_FW_RESET_STATE_POLL_VF; 10264 bnxt_queue_fw_reset_work(bp, HZ / 10); 10265 goto fw_reset_exit; 10266 } 10267 bnxt_fw_reset_close(bp); 10268 if (bp->fw_cap & BNXT_FW_CAP_ERR_RECOVER_RELOAD) { 10269 bp->fw_reset_state = BNXT_FW_RESET_STATE_POLL_FW_DOWN; 10270 tmo = HZ / 10; 10271 } else { 10272 bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV; 10273 tmo = bp->fw_reset_min_dsecs * HZ / 10; 10274 } 10275 bnxt_queue_fw_reset_work(bp, tmo); 10276 } 10277 fw_reset_exit: 10278 bnxt_rtnl_unlock_sp(bp); 10279 } 10280 10281 static void bnxt_chk_missed_irq(struct bnxt *bp) 10282 { 10283 int i; 10284 10285 if (!(bp->flags & BNXT_FLAG_CHIP_P5)) 10286 return; 10287 10288 for (i = 0; i < bp->cp_nr_rings; i++) { 10289 struct bnxt_napi *bnapi = bp->bnapi[i]; 10290 struct bnxt_cp_ring_info *cpr; 10291 u32 fw_ring_id; 10292 int j; 10293 10294 if (!bnapi) 10295 continue; 10296 10297 cpr = &bnapi->cp_ring; 10298 for (j = 0; j < 2; j++) { 10299 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j]; 10300 u32 val[2]; 10301 10302 if (!cpr2 || cpr2->has_more_work || 10303 !bnxt_has_work(bp, cpr2)) 10304 continue; 10305 10306 if (cpr2->cp_raw_cons != cpr2->last_cp_raw_cons) { 10307 cpr2->last_cp_raw_cons = cpr2->cp_raw_cons; 10308 continue; 10309 } 10310 fw_ring_id = cpr2->cp_ring_struct.fw_ring_id; 10311 bnxt_dbg_hwrm_ring_info_get(bp, 10312 DBG_RING_INFO_GET_REQ_RING_TYPE_L2_CMPL, 10313 fw_ring_id, &val[0], &val[1]); 10314 cpr->sw_stats.cmn.missed_irqs++; 10315 } 10316 } 10317 } 10318 10319 static void bnxt_cfg_ntp_filters(struct bnxt *); 10320 10321 static void bnxt_init_ethtool_link_settings(struct bnxt *bp) 10322 { 10323 struct bnxt_link_info *link_info = &bp->link_info; 10324 10325 if (BNXT_AUTO_MODE(link_info->auto_mode)) { 10326 link_info->autoneg = BNXT_AUTONEG_SPEED; 10327 if (bp->hwrm_spec_code >= 0x10201) { 10328 if (link_info->auto_pause_setting & 10329 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE) 10330 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL; 10331 } else { 10332 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL; 10333 } 10334 link_info->advertising = link_info->auto_link_speeds; 10335 } else { 10336 link_info->req_link_speed = link_info->force_link_speed; 10337 link_info->req_duplex = link_info->duplex_setting; 10338 } 10339 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) 10340 link_info->req_flow_ctrl = 10341 link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH; 10342 else 10343 link_info->req_flow_ctrl = link_info->force_pause_setting; 10344 } 10345 10346 static void bnxt_sp_task(struct work_struct *work) 10347 { 10348 struct bnxt *bp = container_of(work, struct bnxt, sp_task); 10349 10350 set_bit(BNXT_STATE_IN_SP_TASK, &bp->state); 10351 smp_mb__after_atomic(); 10352 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) { 10353 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state); 10354 return; 10355 } 10356 10357 if (test_and_clear_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event)) 10358 bnxt_cfg_rx_mode(bp); 10359 10360 if (test_and_clear_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event)) 10361 bnxt_cfg_ntp_filters(bp); 10362 if (test_and_clear_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event)) 10363 bnxt_hwrm_exec_fwd_req(bp); 10364 if (test_and_clear_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event)) { 10365 bnxt_hwrm_tunnel_dst_port_alloc( 10366 bp, bp->vxlan_port, 10367 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN); 10368 } 10369 if (test_and_clear_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event)) { 10370 bnxt_hwrm_tunnel_dst_port_free( 10371 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN); 10372 } 10373 if (test_and_clear_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event)) { 10374 bnxt_hwrm_tunnel_dst_port_alloc( 10375 bp, bp->nge_port, 10376 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE); 10377 } 10378 if (test_and_clear_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event)) { 10379 bnxt_hwrm_tunnel_dst_port_free( 10380 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE); 10381 } 10382 if (test_and_clear_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event)) { 10383 bnxt_hwrm_port_qstats(bp); 10384 bnxt_hwrm_port_qstats_ext(bp); 10385 bnxt_hwrm_pcie_qstats(bp); 10386 } 10387 10388 if (test_and_clear_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event)) { 10389 int rc; 10390 10391 mutex_lock(&bp->link_lock); 10392 if (test_and_clear_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT, 10393 &bp->sp_event)) 10394 bnxt_hwrm_phy_qcaps(bp); 10395 10396 rc = bnxt_update_link(bp, true); 10397 if (rc) 10398 netdev_err(bp->dev, "SP task can't update link (rc: %x)\n", 10399 rc); 10400 10401 if (test_and_clear_bit(BNXT_LINK_CFG_CHANGE_SP_EVENT, 10402 &bp->sp_event)) 10403 bnxt_init_ethtool_link_settings(bp); 10404 mutex_unlock(&bp->link_lock); 10405 } 10406 if (test_and_clear_bit(BNXT_UPDATE_PHY_SP_EVENT, &bp->sp_event)) { 10407 int rc; 10408 10409 mutex_lock(&bp->link_lock); 10410 rc = bnxt_update_phy_setting(bp); 10411 mutex_unlock(&bp->link_lock); 10412 if (rc) { 10413 netdev_warn(bp->dev, "update phy settings retry failed\n"); 10414 } else { 10415 bp->link_info.phy_retry = false; 10416 netdev_info(bp->dev, "update phy settings retry succeeded\n"); 10417 } 10418 } 10419 if (test_and_clear_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event)) { 10420 mutex_lock(&bp->link_lock); 10421 bnxt_get_port_module_status(bp); 10422 mutex_unlock(&bp->link_lock); 10423 } 10424 10425 if (test_and_clear_bit(BNXT_FLOW_STATS_SP_EVENT, &bp->sp_event)) 10426 bnxt_tc_flow_stats_work(bp); 10427 10428 if (test_and_clear_bit(BNXT_RING_COAL_NOW_SP_EVENT, &bp->sp_event)) 10429 bnxt_chk_missed_irq(bp); 10430 10431 /* These functions below will clear BNXT_STATE_IN_SP_TASK. They 10432 * must be the last functions to be called before exiting. 10433 */ 10434 if (test_and_clear_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event)) 10435 bnxt_reset(bp, false); 10436 10437 if (test_and_clear_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event)) 10438 bnxt_reset(bp, true); 10439 10440 if (test_and_clear_bit(BNXT_FW_RESET_NOTIFY_SP_EVENT, &bp->sp_event)) 10441 bnxt_devlink_health_report(bp, BNXT_FW_RESET_NOTIFY_SP_EVENT); 10442 10443 if (test_and_clear_bit(BNXT_FW_EXCEPTION_SP_EVENT, &bp->sp_event)) { 10444 if (!is_bnxt_fw_ok(bp)) 10445 bnxt_devlink_health_report(bp, 10446 BNXT_FW_EXCEPTION_SP_EVENT); 10447 } 10448 10449 smp_mb__before_atomic(); 10450 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state); 10451 } 10452 10453 /* Under rtnl_lock */ 10454 int bnxt_check_rings(struct bnxt *bp, int tx, int rx, bool sh, int tcs, 10455 int tx_xdp) 10456 { 10457 int max_rx, max_tx, tx_sets = 1; 10458 int tx_rings_needed, stats; 10459 int rx_rings = rx; 10460 int cp, vnics, rc; 10461 10462 if (tcs) 10463 tx_sets = tcs; 10464 10465 rc = bnxt_get_max_rings(bp, &max_rx, &max_tx, sh); 10466 if (rc) 10467 return rc; 10468 10469 if (max_rx < rx) 10470 return -ENOMEM; 10471 10472 tx_rings_needed = tx * tx_sets + tx_xdp; 10473 if (max_tx < tx_rings_needed) 10474 return -ENOMEM; 10475 10476 vnics = 1; 10477 if ((bp->flags & (BNXT_FLAG_RFS | BNXT_FLAG_CHIP_P5)) == BNXT_FLAG_RFS) 10478 vnics += rx_rings; 10479 10480 if (bp->flags & BNXT_FLAG_AGG_RINGS) 10481 rx_rings <<= 1; 10482 cp = sh ? max_t(int, tx_rings_needed, rx) : tx_rings_needed + rx; 10483 stats = cp; 10484 if (BNXT_NEW_RM(bp)) { 10485 cp += bnxt_get_ulp_msix_num(bp); 10486 stats += bnxt_get_ulp_stat_ctxs(bp); 10487 } 10488 return bnxt_hwrm_check_rings(bp, tx_rings_needed, rx_rings, rx, cp, 10489 stats, vnics); 10490 } 10491 10492 static void bnxt_unmap_bars(struct bnxt *bp, struct pci_dev *pdev) 10493 { 10494 if (bp->bar2) { 10495 pci_iounmap(pdev, bp->bar2); 10496 bp->bar2 = NULL; 10497 } 10498 10499 if (bp->bar1) { 10500 pci_iounmap(pdev, bp->bar1); 10501 bp->bar1 = NULL; 10502 } 10503 10504 if (bp->bar0) { 10505 pci_iounmap(pdev, bp->bar0); 10506 bp->bar0 = NULL; 10507 } 10508 } 10509 10510 static void bnxt_cleanup_pci(struct bnxt *bp) 10511 { 10512 bnxt_unmap_bars(bp, bp->pdev); 10513 pci_release_regions(bp->pdev); 10514 if (pci_is_enabled(bp->pdev)) 10515 pci_disable_device(bp->pdev); 10516 } 10517 10518 static void bnxt_init_dflt_coal(struct bnxt *bp) 10519 { 10520 struct bnxt_coal *coal; 10521 10522 /* Tick values in micro seconds. 10523 * 1 coal_buf x bufs_per_record = 1 completion record. 10524 */ 10525 coal = &bp->rx_coal; 10526 coal->coal_ticks = 10; 10527 coal->coal_bufs = 30; 10528 coal->coal_ticks_irq = 1; 10529 coal->coal_bufs_irq = 2; 10530 coal->idle_thresh = 50; 10531 coal->bufs_per_record = 2; 10532 coal->budget = 64; /* NAPI budget */ 10533 10534 coal = &bp->tx_coal; 10535 coal->coal_ticks = 28; 10536 coal->coal_bufs = 30; 10537 coal->coal_ticks_irq = 2; 10538 coal->coal_bufs_irq = 2; 10539 coal->bufs_per_record = 1; 10540 10541 bp->stats_coal_ticks = BNXT_DEF_STATS_COAL_TICKS; 10542 } 10543 10544 static void bnxt_alloc_fw_health(struct bnxt *bp) 10545 { 10546 if (bp->fw_health) 10547 return; 10548 10549 if (!(bp->fw_cap & BNXT_FW_CAP_HOT_RESET) && 10550 !(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)) 10551 return; 10552 10553 bp->fw_health = kzalloc(sizeof(*bp->fw_health), GFP_KERNEL); 10554 if (!bp->fw_health) { 10555 netdev_warn(bp->dev, "Failed to allocate fw_health\n"); 10556 bp->fw_cap &= ~BNXT_FW_CAP_HOT_RESET; 10557 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY; 10558 } 10559 } 10560 10561 static int bnxt_fw_init_one_p1(struct bnxt *bp) 10562 { 10563 int rc; 10564 10565 bp->fw_cap = 0; 10566 rc = bnxt_hwrm_ver_get(bp); 10567 if (rc) 10568 return rc; 10569 10570 if (bp->fw_cap & BNXT_FW_CAP_KONG_MB_CHNL) { 10571 rc = bnxt_alloc_kong_hwrm_resources(bp); 10572 if (rc) 10573 bp->fw_cap &= ~BNXT_FW_CAP_KONG_MB_CHNL; 10574 } 10575 10576 if ((bp->fw_cap & BNXT_FW_CAP_SHORT_CMD) || 10577 bp->hwrm_max_ext_req_len > BNXT_HWRM_MAX_REQ_LEN) { 10578 rc = bnxt_alloc_hwrm_short_cmd_req(bp); 10579 if (rc) 10580 return rc; 10581 } 10582 rc = bnxt_hwrm_func_reset(bp); 10583 if (rc) 10584 return -ENODEV; 10585 10586 bnxt_hwrm_fw_set_time(bp); 10587 return 0; 10588 } 10589 10590 static int bnxt_fw_init_one_p2(struct bnxt *bp) 10591 { 10592 int rc; 10593 10594 /* Get the MAX capabilities for this function */ 10595 rc = bnxt_hwrm_func_qcaps(bp); 10596 if (rc) { 10597 netdev_err(bp->dev, "hwrm query capability failure rc: %x\n", 10598 rc); 10599 return -ENODEV; 10600 } 10601 10602 rc = bnxt_hwrm_cfa_adv_flow_mgnt_qcaps(bp); 10603 if (rc) 10604 netdev_warn(bp->dev, "hwrm query adv flow mgnt failure rc: %d\n", 10605 rc); 10606 10607 bnxt_alloc_fw_health(bp); 10608 rc = bnxt_hwrm_error_recovery_qcfg(bp); 10609 if (rc) 10610 netdev_warn(bp->dev, "hwrm query error recovery failure rc: %d\n", 10611 rc); 10612 10613 rc = bnxt_hwrm_func_drv_rgtr(bp, NULL, 0, false); 10614 if (rc) 10615 return -ENODEV; 10616 10617 bnxt_hwrm_func_qcfg(bp); 10618 bnxt_hwrm_vnic_qcaps(bp); 10619 bnxt_hwrm_port_led_qcaps(bp); 10620 bnxt_ethtool_init(bp); 10621 bnxt_dcb_init(bp); 10622 return 0; 10623 } 10624 10625 static void bnxt_set_dflt_rss_hash_type(struct bnxt *bp) 10626 { 10627 bp->flags &= ~BNXT_FLAG_UDP_RSS_CAP; 10628 bp->rss_hash_cfg = VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 | 10629 VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 | 10630 VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 | 10631 VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6; 10632 if (BNXT_CHIP_P4_PLUS(bp) && bp->hwrm_spec_code >= 0x10501) { 10633 bp->flags |= BNXT_FLAG_UDP_RSS_CAP; 10634 bp->rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 | 10635 VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6; 10636 } 10637 } 10638 10639 static void bnxt_set_dflt_rfs(struct bnxt *bp) 10640 { 10641 struct net_device *dev = bp->dev; 10642 10643 dev->hw_features &= ~NETIF_F_NTUPLE; 10644 dev->features &= ~NETIF_F_NTUPLE; 10645 bp->flags &= ~BNXT_FLAG_RFS; 10646 if (bnxt_rfs_supported(bp)) { 10647 dev->hw_features |= NETIF_F_NTUPLE; 10648 if (bnxt_rfs_capable(bp)) { 10649 bp->flags |= BNXT_FLAG_RFS; 10650 dev->features |= NETIF_F_NTUPLE; 10651 } 10652 } 10653 } 10654 10655 static void bnxt_fw_init_one_p3(struct bnxt *bp) 10656 { 10657 struct pci_dev *pdev = bp->pdev; 10658 10659 bnxt_set_dflt_rss_hash_type(bp); 10660 bnxt_set_dflt_rfs(bp); 10661 10662 bnxt_get_wol_settings(bp); 10663 if (bp->flags & BNXT_FLAG_WOL_CAP) 10664 device_set_wakeup_enable(&pdev->dev, bp->wol); 10665 else 10666 device_set_wakeup_capable(&pdev->dev, false); 10667 10668 bnxt_hwrm_set_cache_line_size(bp, cache_line_size()); 10669 bnxt_hwrm_coal_params_qcaps(bp); 10670 } 10671 10672 static int bnxt_fw_init_one(struct bnxt *bp) 10673 { 10674 int rc; 10675 10676 rc = bnxt_fw_init_one_p1(bp); 10677 if (rc) { 10678 netdev_err(bp->dev, "Firmware init phase 1 failed\n"); 10679 return rc; 10680 } 10681 rc = bnxt_fw_init_one_p2(bp); 10682 if (rc) { 10683 netdev_err(bp->dev, "Firmware init phase 2 failed\n"); 10684 return rc; 10685 } 10686 rc = bnxt_approve_mac(bp, bp->dev->dev_addr, false); 10687 if (rc) 10688 return rc; 10689 10690 /* In case fw capabilities have changed, destroy the unneeded 10691 * reporters and create newly capable ones. 10692 */ 10693 bnxt_dl_fw_reporters_destroy(bp, false); 10694 bnxt_dl_fw_reporters_create(bp); 10695 bnxt_fw_init_one_p3(bp); 10696 return 0; 10697 } 10698 10699 static void bnxt_fw_reset_writel(struct bnxt *bp, int reg_idx) 10700 { 10701 struct bnxt_fw_health *fw_health = bp->fw_health; 10702 u32 reg = fw_health->fw_reset_seq_regs[reg_idx]; 10703 u32 val = fw_health->fw_reset_seq_vals[reg_idx]; 10704 u32 reg_type, reg_off, delay_msecs; 10705 10706 delay_msecs = fw_health->fw_reset_seq_delay_msec[reg_idx]; 10707 reg_type = BNXT_FW_HEALTH_REG_TYPE(reg); 10708 reg_off = BNXT_FW_HEALTH_REG_OFF(reg); 10709 switch (reg_type) { 10710 case BNXT_FW_HEALTH_REG_TYPE_CFG: 10711 pci_write_config_dword(bp->pdev, reg_off, val); 10712 break; 10713 case BNXT_FW_HEALTH_REG_TYPE_GRC: 10714 writel(reg_off & BNXT_GRC_BASE_MASK, 10715 bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4); 10716 reg_off = (reg_off & BNXT_GRC_OFFSET_MASK) + 0x2000; 10717 /* fall through */ 10718 case BNXT_FW_HEALTH_REG_TYPE_BAR0: 10719 writel(val, bp->bar0 + reg_off); 10720 break; 10721 case BNXT_FW_HEALTH_REG_TYPE_BAR1: 10722 writel(val, bp->bar1 + reg_off); 10723 break; 10724 } 10725 if (delay_msecs) { 10726 pci_read_config_dword(bp->pdev, 0, &val); 10727 msleep(delay_msecs); 10728 } 10729 } 10730 10731 static void bnxt_reset_all(struct bnxt *bp) 10732 { 10733 struct bnxt_fw_health *fw_health = bp->fw_health; 10734 int i, rc; 10735 10736 if (bp->fw_cap & BNXT_FW_CAP_ERR_RECOVER_RELOAD) { 10737 #ifdef CONFIG_TEE_BNXT_FW 10738 rc = tee_bnxt_fw_load(); 10739 if (rc) 10740 netdev_err(bp->dev, "Unable to reset FW rc=%d\n", rc); 10741 bp->fw_reset_timestamp = jiffies; 10742 #endif 10743 return; 10744 } 10745 10746 if (fw_health->flags & ERROR_RECOVERY_QCFG_RESP_FLAGS_HOST) { 10747 for (i = 0; i < fw_health->fw_reset_seq_cnt; i++) 10748 bnxt_fw_reset_writel(bp, i); 10749 } else if (fw_health->flags & ERROR_RECOVERY_QCFG_RESP_FLAGS_CO_CPU) { 10750 struct hwrm_fw_reset_input req = {0}; 10751 10752 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FW_RESET, -1, -1); 10753 req.resp_addr = cpu_to_le64(bp->hwrm_cmd_kong_resp_dma_addr); 10754 req.embedded_proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP; 10755 req.selfrst_status = FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP; 10756 req.flags = FW_RESET_REQ_FLAGS_RESET_GRACEFUL; 10757 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 10758 if (rc) 10759 netdev_warn(bp->dev, "Unable to reset FW rc=%d\n", rc); 10760 } 10761 bp->fw_reset_timestamp = jiffies; 10762 } 10763 10764 static void bnxt_fw_reset_task(struct work_struct *work) 10765 { 10766 struct bnxt *bp = container_of(work, struct bnxt, fw_reset_task.work); 10767 int rc; 10768 10769 if (!test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) { 10770 netdev_err(bp->dev, "bnxt_fw_reset_task() called when not in fw reset mode!\n"); 10771 return; 10772 } 10773 10774 switch (bp->fw_reset_state) { 10775 case BNXT_FW_RESET_STATE_POLL_VF: { 10776 int n = bnxt_get_registered_vfs(bp); 10777 int tmo; 10778 10779 if (n < 0) { 10780 netdev_err(bp->dev, "Firmware reset aborted, subsequent func_qcfg cmd failed, rc = %d, %d msecs since reset timestamp\n", 10781 n, jiffies_to_msecs(jiffies - 10782 bp->fw_reset_timestamp)); 10783 goto fw_reset_abort; 10784 } else if (n > 0) { 10785 if (time_after(jiffies, bp->fw_reset_timestamp + 10786 (bp->fw_reset_max_dsecs * HZ / 10))) { 10787 clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state); 10788 bp->fw_reset_state = 0; 10789 netdev_err(bp->dev, "Firmware reset aborted, bnxt_get_registered_vfs() returns %d\n", 10790 n); 10791 return; 10792 } 10793 bnxt_queue_fw_reset_work(bp, HZ / 10); 10794 return; 10795 } 10796 bp->fw_reset_timestamp = jiffies; 10797 rtnl_lock(); 10798 bnxt_fw_reset_close(bp); 10799 if (bp->fw_cap & BNXT_FW_CAP_ERR_RECOVER_RELOAD) { 10800 bp->fw_reset_state = BNXT_FW_RESET_STATE_POLL_FW_DOWN; 10801 tmo = HZ / 10; 10802 } else { 10803 bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV; 10804 tmo = bp->fw_reset_min_dsecs * HZ / 10; 10805 } 10806 rtnl_unlock(); 10807 bnxt_queue_fw_reset_work(bp, tmo); 10808 return; 10809 } 10810 case BNXT_FW_RESET_STATE_POLL_FW_DOWN: { 10811 u32 val; 10812 10813 val = bnxt_fw_health_readl(bp, BNXT_FW_HEALTH_REG); 10814 if (!(val & BNXT_FW_STATUS_SHUTDOWN) && 10815 !time_after(jiffies, bp->fw_reset_timestamp + 10816 (bp->fw_reset_max_dsecs * HZ / 10))) { 10817 bnxt_queue_fw_reset_work(bp, HZ / 5); 10818 return; 10819 } 10820 10821 if (!bp->fw_health->master) { 10822 u32 wait_dsecs = bp->fw_health->normal_func_wait_dsecs; 10823 10824 bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV; 10825 bnxt_queue_fw_reset_work(bp, wait_dsecs * HZ / 10); 10826 return; 10827 } 10828 bp->fw_reset_state = BNXT_FW_RESET_STATE_RESET_FW; 10829 } 10830 /* fall through */ 10831 case BNXT_FW_RESET_STATE_RESET_FW: 10832 bnxt_reset_all(bp); 10833 bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV; 10834 bnxt_queue_fw_reset_work(bp, bp->fw_reset_min_dsecs * HZ / 10); 10835 return; 10836 case BNXT_FW_RESET_STATE_ENABLE_DEV: 10837 if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state)) { 10838 u32 val; 10839 10840 val = bnxt_fw_health_readl(bp, 10841 BNXT_FW_RESET_INPROG_REG); 10842 if (val) 10843 netdev_warn(bp->dev, "FW reset inprog %x after min wait time.\n", 10844 val); 10845 } 10846 clear_bit(BNXT_STATE_FW_FATAL_COND, &bp->state); 10847 if (pci_enable_device(bp->pdev)) { 10848 netdev_err(bp->dev, "Cannot re-enable PCI device\n"); 10849 goto fw_reset_abort; 10850 } 10851 pci_set_master(bp->pdev); 10852 bp->fw_reset_state = BNXT_FW_RESET_STATE_POLL_FW; 10853 /* fall through */ 10854 case BNXT_FW_RESET_STATE_POLL_FW: 10855 bp->hwrm_cmd_timeout = SHORT_HWRM_CMD_TIMEOUT; 10856 rc = __bnxt_hwrm_ver_get(bp, true); 10857 if (rc) { 10858 if (time_after(jiffies, bp->fw_reset_timestamp + 10859 (bp->fw_reset_max_dsecs * HZ / 10))) { 10860 netdev_err(bp->dev, "Firmware reset aborted\n"); 10861 goto fw_reset_abort; 10862 } 10863 bnxt_queue_fw_reset_work(bp, HZ / 5); 10864 return; 10865 } 10866 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT; 10867 bp->fw_reset_state = BNXT_FW_RESET_STATE_OPENING; 10868 /* fall through */ 10869 case BNXT_FW_RESET_STATE_OPENING: 10870 while (!rtnl_trylock()) { 10871 bnxt_queue_fw_reset_work(bp, HZ / 10); 10872 return; 10873 } 10874 rc = bnxt_open(bp->dev); 10875 if (rc) { 10876 netdev_err(bp->dev, "bnxt_open_nic() failed\n"); 10877 clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state); 10878 dev_close(bp->dev); 10879 } 10880 10881 bp->fw_reset_state = 0; 10882 /* Make sure fw_reset_state is 0 before clearing the flag */ 10883 smp_mb__before_atomic(); 10884 clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state); 10885 bnxt_ulp_start(bp, rc); 10886 if (!rc) 10887 bnxt_reenable_sriov(bp); 10888 bnxt_dl_health_recovery_done(bp); 10889 bnxt_dl_health_status_update(bp, true); 10890 rtnl_unlock(); 10891 break; 10892 } 10893 return; 10894 10895 fw_reset_abort: 10896 clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state); 10897 if (bp->fw_reset_state != BNXT_FW_RESET_STATE_POLL_VF) 10898 bnxt_dl_health_status_update(bp, false); 10899 bp->fw_reset_state = 0; 10900 rtnl_lock(); 10901 dev_close(bp->dev); 10902 rtnl_unlock(); 10903 } 10904 10905 static int bnxt_init_board(struct pci_dev *pdev, struct net_device *dev) 10906 { 10907 int rc; 10908 struct bnxt *bp = netdev_priv(dev); 10909 10910 SET_NETDEV_DEV(dev, &pdev->dev); 10911 10912 /* enable device (incl. PCI PM wakeup), and bus-mastering */ 10913 rc = pci_enable_device(pdev); 10914 if (rc) { 10915 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n"); 10916 goto init_err; 10917 } 10918 10919 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 10920 dev_err(&pdev->dev, 10921 "Cannot find PCI device base address, aborting\n"); 10922 rc = -ENODEV; 10923 goto init_err_disable; 10924 } 10925 10926 rc = pci_request_regions(pdev, DRV_MODULE_NAME); 10927 if (rc) { 10928 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n"); 10929 goto init_err_disable; 10930 } 10931 10932 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) != 0 && 10933 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)) != 0) { 10934 dev_err(&pdev->dev, "System does not support DMA, aborting\n"); 10935 goto init_err_disable; 10936 } 10937 10938 pci_set_master(pdev); 10939 10940 bp->dev = dev; 10941 bp->pdev = pdev; 10942 10943 /* Doorbell BAR bp->bar1 is mapped after bnxt_fw_init_one_p2() 10944 * determines the BAR size. 10945 */ 10946 bp->bar0 = pci_ioremap_bar(pdev, 0); 10947 if (!bp->bar0) { 10948 dev_err(&pdev->dev, "Cannot map device registers, aborting\n"); 10949 rc = -ENOMEM; 10950 goto init_err_release; 10951 } 10952 10953 bp->bar2 = pci_ioremap_bar(pdev, 4); 10954 if (!bp->bar2) { 10955 dev_err(&pdev->dev, "Cannot map bar4 registers, aborting\n"); 10956 rc = -ENOMEM; 10957 goto init_err_release; 10958 } 10959 10960 pci_enable_pcie_error_reporting(pdev); 10961 10962 INIT_WORK(&bp->sp_task, bnxt_sp_task); 10963 INIT_DELAYED_WORK(&bp->fw_reset_task, bnxt_fw_reset_task); 10964 10965 spin_lock_init(&bp->ntp_fltr_lock); 10966 #if BITS_PER_LONG == 32 10967 spin_lock_init(&bp->db_lock); 10968 #endif 10969 10970 bp->rx_ring_size = BNXT_DEFAULT_RX_RING_SIZE; 10971 bp->tx_ring_size = BNXT_DEFAULT_TX_RING_SIZE; 10972 10973 bnxt_init_dflt_coal(bp); 10974 10975 timer_setup(&bp->timer, bnxt_timer, 0); 10976 bp->current_interval = BNXT_TIMER_INTERVAL; 10977 10978 clear_bit(BNXT_STATE_OPEN, &bp->state); 10979 return 0; 10980 10981 init_err_release: 10982 bnxt_unmap_bars(bp, pdev); 10983 pci_release_regions(pdev); 10984 10985 init_err_disable: 10986 pci_disable_device(pdev); 10987 10988 init_err: 10989 return rc; 10990 } 10991 10992 /* rtnl_lock held */ 10993 static int bnxt_change_mac_addr(struct net_device *dev, void *p) 10994 { 10995 struct sockaddr *addr = p; 10996 struct bnxt *bp = netdev_priv(dev); 10997 int rc = 0; 10998 10999 if (!is_valid_ether_addr(addr->sa_data)) 11000 return -EADDRNOTAVAIL; 11001 11002 if (ether_addr_equal(addr->sa_data, dev->dev_addr)) 11003 return 0; 11004 11005 rc = bnxt_approve_mac(bp, addr->sa_data, true); 11006 if (rc) 11007 return rc; 11008 11009 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); 11010 if (netif_running(dev)) { 11011 bnxt_close_nic(bp, false, false); 11012 rc = bnxt_open_nic(bp, false, false); 11013 } 11014 11015 return rc; 11016 } 11017 11018 /* rtnl_lock held */ 11019 static int bnxt_change_mtu(struct net_device *dev, int new_mtu) 11020 { 11021 struct bnxt *bp = netdev_priv(dev); 11022 11023 if (netif_running(dev)) 11024 bnxt_close_nic(bp, true, false); 11025 11026 dev->mtu = new_mtu; 11027 bnxt_set_ring_params(bp); 11028 11029 if (netif_running(dev)) 11030 return bnxt_open_nic(bp, true, false); 11031 11032 return 0; 11033 } 11034 11035 int bnxt_setup_mq_tc(struct net_device *dev, u8 tc) 11036 { 11037 struct bnxt *bp = netdev_priv(dev); 11038 bool sh = false; 11039 int rc; 11040 11041 if (tc > bp->max_tc) { 11042 netdev_err(dev, "Too many traffic classes requested: %d. Max supported is %d.\n", 11043 tc, bp->max_tc); 11044 return -EINVAL; 11045 } 11046 11047 if (netdev_get_num_tc(dev) == tc) 11048 return 0; 11049 11050 if (bp->flags & BNXT_FLAG_SHARED_RINGS) 11051 sh = true; 11052 11053 rc = bnxt_check_rings(bp, bp->tx_nr_rings_per_tc, bp->rx_nr_rings, 11054 sh, tc, bp->tx_nr_rings_xdp); 11055 if (rc) 11056 return rc; 11057 11058 /* Needs to close the device and do hw resource re-allocations */ 11059 if (netif_running(bp->dev)) 11060 bnxt_close_nic(bp, true, false); 11061 11062 if (tc) { 11063 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tc; 11064 netdev_set_num_tc(dev, tc); 11065 } else { 11066 bp->tx_nr_rings = bp->tx_nr_rings_per_tc; 11067 netdev_reset_tc(dev); 11068 } 11069 bp->tx_nr_rings += bp->tx_nr_rings_xdp; 11070 bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) : 11071 bp->tx_nr_rings + bp->rx_nr_rings; 11072 11073 if (netif_running(bp->dev)) 11074 return bnxt_open_nic(bp, true, false); 11075 11076 return 0; 11077 } 11078 11079 static int bnxt_setup_tc_block_cb(enum tc_setup_type type, void *type_data, 11080 void *cb_priv) 11081 { 11082 struct bnxt *bp = cb_priv; 11083 11084 if (!bnxt_tc_flower_enabled(bp) || 11085 !tc_cls_can_offload_and_chain0(bp->dev, type_data)) 11086 return -EOPNOTSUPP; 11087 11088 switch (type) { 11089 case TC_SETUP_CLSFLOWER: 11090 return bnxt_tc_setup_flower(bp, bp->pf.fw_fid, type_data); 11091 default: 11092 return -EOPNOTSUPP; 11093 } 11094 } 11095 11096 LIST_HEAD(bnxt_block_cb_list); 11097 11098 static int bnxt_setup_tc(struct net_device *dev, enum tc_setup_type type, 11099 void *type_data) 11100 { 11101 struct bnxt *bp = netdev_priv(dev); 11102 11103 switch (type) { 11104 case TC_SETUP_BLOCK: 11105 return flow_block_cb_setup_simple(type_data, 11106 &bnxt_block_cb_list, 11107 bnxt_setup_tc_block_cb, 11108 bp, bp, true); 11109 case TC_SETUP_QDISC_MQPRIO: { 11110 struct tc_mqprio_qopt *mqprio = type_data; 11111 11112 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS; 11113 11114 return bnxt_setup_mq_tc(dev, mqprio->num_tc); 11115 } 11116 default: 11117 return -EOPNOTSUPP; 11118 } 11119 } 11120 11121 #ifdef CONFIG_RFS_ACCEL 11122 static bool bnxt_fltr_match(struct bnxt_ntuple_filter *f1, 11123 struct bnxt_ntuple_filter *f2) 11124 { 11125 struct flow_keys *keys1 = &f1->fkeys; 11126 struct flow_keys *keys2 = &f2->fkeys; 11127 11128 if (keys1->basic.n_proto != keys2->basic.n_proto || 11129 keys1->basic.ip_proto != keys2->basic.ip_proto) 11130 return false; 11131 11132 if (keys1->basic.n_proto == htons(ETH_P_IP)) { 11133 if (keys1->addrs.v4addrs.src != keys2->addrs.v4addrs.src || 11134 keys1->addrs.v4addrs.dst != keys2->addrs.v4addrs.dst) 11135 return false; 11136 } else { 11137 if (memcmp(&keys1->addrs.v6addrs.src, &keys2->addrs.v6addrs.src, 11138 sizeof(keys1->addrs.v6addrs.src)) || 11139 memcmp(&keys1->addrs.v6addrs.dst, &keys2->addrs.v6addrs.dst, 11140 sizeof(keys1->addrs.v6addrs.dst))) 11141 return false; 11142 } 11143 11144 if (keys1->ports.ports == keys2->ports.ports && 11145 keys1->control.flags == keys2->control.flags && 11146 ether_addr_equal(f1->src_mac_addr, f2->src_mac_addr) && 11147 ether_addr_equal(f1->dst_mac_addr, f2->dst_mac_addr)) 11148 return true; 11149 11150 return false; 11151 } 11152 11153 static int bnxt_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb, 11154 u16 rxq_index, u32 flow_id) 11155 { 11156 struct bnxt *bp = netdev_priv(dev); 11157 struct bnxt_ntuple_filter *fltr, *new_fltr; 11158 struct flow_keys *fkeys; 11159 struct ethhdr *eth = (struct ethhdr *)skb_mac_header(skb); 11160 int rc = 0, idx, bit_id, l2_idx = 0; 11161 struct hlist_head *head; 11162 u32 flags; 11163 11164 if (!ether_addr_equal(dev->dev_addr, eth->h_dest)) { 11165 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 11166 int off = 0, j; 11167 11168 netif_addr_lock_bh(dev); 11169 for (j = 0; j < vnic->uc_filter_count; j++, off += ETH_ALEN) { 11170 if (ether_addr_equal(eth->h_dest, 11171 vnic->uc_list + off)) { 11172 l2_idx = j + 1; 11173 break; 11174 } 11175 } 11176 netif_addr_unlock_bh(dev); 11177 if (!l2_idx) 11178 return -EINVAL; 11179 } 11180 new_fltr = kzalloc(sizeof(*new_fltr), GFP_ATOMIC); 11181 if (!new_fltr) 11182 return -ENOMEM; 11183 11184 fkeys = &new_fltr->fkeys; 11185 if (!skb_flow_dissect_flow_keys(skb, fkeys, 0)) { 11186 rc = -EPROTONOSUPPORT; 11187 goto err_free; 11188 } 11189 11190 if ((fkeys->basic.n_proto != htons(ETH_P_IP) && 11191 fkeys->basic.n_proto != htons(ETH_P_IPV6)) || 11192 ((fkeys->basic.ip_proto != IPPROTO_TCP) && 11193 (fkeys->basic.ip_proto != IPPROTO_UDP))) { 11194 rc = -EPROTONOSUPPORT; 11195 goto err_free; 11196 } 11197 if (fkeys->basic.n_proto == htons(ETH_P_IPV6) && 11198 bp->hwrm_spec_code < 0x10601) { 11199 rc = -EPROTONOSUPPORT; 11200 goto err_free; 11201 } 11202 flags = fkeys->control.flags; 11203 if (((flags & FLOW_DIS_ENCAPSULATION) && 11204 bp->hwrm_spec_code < 0x10601) || (flags & FLOW_DIS_IS_FRAGMENT)) { 11205 rc = -EPROTONOSUPPORT; 11206 goto err_free; 11207 } 11208 11209 memcpy(new_fltr->dst_mac_addr, eth->h_dest, ETH_ALEN); 11210 memcpy(new_fltr->src_mac_addr, eth->h_source, ETH_ALEN); 11211 11212 idx = skb_get_hash_raw(skb) & BNXT_NTP_FLTR_HASH_MASK; 11213 head = &bp->ntp_fltr_hash_tbl[idx]; 11214 rcu_read_lock(); 11215 hlist_for_each_entry_rcu(fltr, head, hash) { 11216 if (bnxt_fltr_match(fltr, new_fltr)) { 11217 rcu_read_unlock(); 11218 rc = 0; 11219 goto err_free; 11220 } 11221 } 11222 rcu_read_unlock(); 11223 11224 spin_lock_bh(&bp->ntp_fltr_lock); 11225 bit_id = bitmap_find_free_region(bp->ntp_fltr_bmap, 11226 BNXT_NTP_FLTR_MAX_FLTR, 0); 11227 if (bit_id < 0) { 11228 spin_unlock_bh(&bp->ntp_fltr_lock); 11229 rc = -ENOMEM; 11230 goto err_free; 11231 } 11232 11233 new_fltr->sw_id = (u16)bit_id; 11234 new_fltr->flow_id = flow_id; 11235 new_fltr->l2_fltr_idx = l2_idx; 11236 new_fltr->rxq = rxq_index; 11237 hlist_add_head_rcu(&new_fltr->hash, head); 11238 bp->ntp_fltr_count++; 11239 spin_unlock_bh(&bp->ntp_fltr_lock); 11240 11241 set_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event); 11242 bnxt_queue_sp_work(bp); 11243 11244 return new_fltr->sw_id; 11245 11246 err_free: 11247 kfree(new_fltr); 11248 return rc; 11249 } 11250 11251 static void bnxt_cfg_ntp_filters(struct bnxt *bp) 11252 { 11253 int i; 11254 11255 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) { 11256 struct hlist_head *head; 11257 struct hlist_node *tmp; 11258 struct bnxt_ntuple_filter *fltr; 11259 int rc; 11260 11261 head = &bp->ntp_fltr_hash_tbl[i]; 11262 hlist_for_each_entry_safe(fltr, tmp, head, hash) { 11263 bool del = false; 11264 11265 if (test_bit(BNXT_FLTR_VALID, &fltr->state)) { 11266 if (rps_may_expire_flow(bp->dev, fltr->rxq, 11267 fltr->flow_id, 11268 fltr->sw_id)) { 11269 bnxt_hwrm_cfa_ntuple_filter_free(bp, 11270 fltr); 11271 del = true; 11272 } 11273 } else { 11274 rc = bnxt_hwrm_cfa_ntuple_filter_alloc(bp, 11275 fltr); 11276 if (rc) 11277 del = true; 11278 else 11279 set_bit(BNXT_FLTR_VALID, &fltr->state); 11280 } 11281 11282 if (del) { 11283 spin_lock_bh(&bp->ntp_fltr_lock); 11284 hlist_del_rcu(&fltr->hash); 11285 bp->ntp_fltr_count--; 11286 spin_unlock_bh(&bp->ntp_fltr_lock); 11287 synchronize_rcu(); 11288 clear_bit(fltr->sw_id, bp->ntp_fltr_bmap); 11289 kfree(fltr); 11290 } 11291 } 11292 } 11293 if (test_and_clear_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event)) 11294 netdev_info(bp->dev, "Receive PF driver unload event!\n"); 11295 } 11296 11297 #else 11298 11299 static void bnxt_cfg_ntp_filters(struct bnxt *bp) 11300 { 11301 } 11302 11303 #endif /* CONFIG_RFS_ACCEL */ 11304 11305 static void bnxt_udp_tunnel_add(struct net_device *dev, 11306 struct udp_tunnel_info *ti) 11307 { 11308 struct bnxt *bp = netdev_priv(dev); 11309 11310 if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET) 11311 return; 11312 11313 if (!netif_running(dev)) 11314 return; 11315 11316 switch (ti->type) { 11317 case UDP_TUNNEL_TYPE_VXLAN: 11318 if (bp->vxlan_port_cnt && bp->vxlan_port != ti->port) 11319 return; 11320 11321 bp->vxlan_port_cnt++; 11322 if (bp->vxlan_port_cnt == 1) { 11323 bp->vxlan_port = ti->port; 11324 set_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event); 11325 bnxt_queue_sp_work(bp); 11326 } 11327 break; 11328 case UDP_TUNNEL_TYPE_GENEVE: 11329 if (bp->nge_port_cnt && bp->nge_port != ti->port) 11330 return; 11331 11332 bp->nge_port_cnt++; 11333 if (bp->nge_port_cnt == 1) { 11334 bp->nge_port = ti->port; 11335 set_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event); 11336 } 11337 break; 11338 default: 11339 return; 11340 } 11341 11342 bnxt_queue_sp_work(bp); 11343 } 11344 11345 static void bnxt_udp_tunnel_del(struct net_device *dev, 11346 struct udp_tunnel_info *ti) 11347 { 11348 struct bnxt *bp = netdev_priv(dev); 11349 11350 if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET) 11351 return; 11352 11353 if (!netif_running(dev)) 11354 return; 11355 11356 switch (ti->type) { 11357 case UDP_TUNNEL_TYPE_VXLAN: 11358 if (!bp->vxlan_port_cnt || bp->vxlan_port != ti->port) 11359 return; 11360 bp->vxlan_port_cnt--; 11361 11362 if (bp->vxlan_port_cnt != 0) 11363 return; 11364 11365 set_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event); 11366 break; 11367 case UDP_TUNNEL_TYPE_GENEVE: 11368 if (!bp->nge_port_cnt || bp->nge_port != ti->port) 11369 return; 11370 bp->nge_port_cnt--; 11371 11372 if (bp->nge_port_cnt != 0) 11373 return; 11374 11375 set_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event); 11376 break; 11377 default: 11378 return; 11379 } 11380 11381 bnxt_queue_sp_work(bp); 11382 } 11383 11384 static int bnxt_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq, 11385 struct net_device *dev, u32 filter_mask, 11386 int nlflags) 11387 { 11388 struct bnxt *bp = netdev_priv(dev); 11389 11390 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, bp->br_mode, 0, 0, 11391 nlflags, filter_mask, NULL); 11392 } 11393 11394 static int bnxt_bridge_setlink(struct net_device *dev, struct nlmsghdr *nlh, 11395 u16 flags, struct netlink_ext_ack *extack) 11396 { 11397 struct bnxt *bp = netdev_priv(dev); 11398 struct nlattr *attr, *br_spec; 11399 int rem, rc = 0; 11400 11401 if (bp->hwrm_spec_code < 0x10708 || !BNXT_SINGLE_PF(bp)) 11402 return -EOPNOTSUPP; 11403 11404 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC); 11405 if (!br_spec) 11406 return -EINVAL; 11407 11408 nla_for_each_nested(attr, br_spec, rem) { 11409 u16 mode; 11410 11411 if (nla_type(attr) != IFLA_BRIDGE_MODE) 11412 continue; 11413 11414 if (nla_len(attr) < sizeof(mode)) 11415 return -EINVAL; 11416 11417 mode = nla_get_u16(attr); 11418 if (mode == bp->br_mode) 11419 break; 11420 11421 rc = bnxt_hwrm_set_br_mode(bp, mode); 11422 if (!rc) 11423 bp->br_mode = mode; 11424 break; 11425 } 11426 return rc; 11427 } 11428 11429 int bnxt_get_port_parent_id(struct net_device *dev, 11430 struct netdev_phys_item_id *ppid) 11431 { 11432 struct bnxt *bp = netdev_priv(dev); 11433 11434 if (bp->eswitch_mode != DEVLINK_ESWITCH_MODE_SWITCHDEV) 11435 return -EOPNOTSUPP; 11436 11437 /* The PF and it's VF-reps only support the switchdev framework */ 11438 if (!BNXT_PF(bp) || !(bp->flags & BNXT_FLAG_DSN_VALID)) 11439 return -EOPNOTSUPP; 11440 11441 ppid->id_len = sizeof(bp->dsn); 11442 memcpy(ppid->id, bp->dsn, ppid->id_len); 11443 11444 return 0; 11445 } 11446 11447 static struct devlink_port *bnxt_get_devlink_port(struct net_device *dev) 11448 { 11449 struct bnxt *bp = netdev_priv(dev); 11450 11451 return &bp->dl_port; 11452 } 11453 11454 static const struct net_device_ops bnxt_netdev_ops = { 11455 .ndo_open = bnxt_open, 11456 .ndo_start_xmit = bnxt_start_xmit, 11457 .ndo_stop = bnxt_close, 11458 .ndo_get_stats64 = bnxt_get_stats64, 11459 .ndo_set_rx_mode = bnxt_set_rx_mode, 11460 .ndo_do_ioctl = bnxt_ioctl, 11461 .ndo_validate_addr = eth_validate_addr, 11462 .ndo_set_mac_address = bnxt_change_mac_addr, 11463 .ndo_change_mtu = bnxt_change_mtu, 11464 .ndo_fix_features = bnxt_fix_features, 11465 .ndo_set_features = bnxt_set_features, 11466 .ndo_tx_timeout = bnxt_tx_timeout, 11467 #ifdef CONFIG_BNXT_SRIOV 11468 .ndo_get_vf_config = bnxt_get_vf_config, 11469 .ndo_set_vf_mac = bnxt_set_vf_mac, 11470 .ndo_set_vf_vlan = bnxt_set_vf_vlan, 11471 .ndo_set_vf_rate = bnxt_set_vf_bw, 11472 .ndo_set_vf_link_state = bnxt_set_vf_link_state, 11473 .ndo_set_vf_spoofchk = bnxt_set_vf_spoofchk, 11474 .ndo_set_vf_trust = bnxt_set_vf_trust, 11475 #endif 11476 .ndo_setup_tc = bnxt_setup_tc, 11477 #ifdef CONFIG_RFS_ACCEL 11478 .ndo_rx_flow_steer = bnxt_rx_flow_steer, 11479 #endif 11480 .ndo_udp_tunnel_add = bnxt_udp_tunnel_add, 11481 .ndo_udp_tunnel_del = bnxt_udp_tunnel_del, 11482 .ndo_bpf = bnxt_xdp, 11483 .ndo_xdp_xmit = bnxt_xdp_xmit, 11484 .ndo_bridge_getlink = bnxt_bridge_getlink, 11485 .ndo_bridge_setlink = bnxt_bridge_setlink, 11486 .ndo_get_devlink_port = bnxt_get_devlink_port, 11487 }; 11488 11489 static void bnxt_remove_one(struct pci_dev *pdev) 11490 { 11491 struct net_device *dev = pci_get_drvdata(pdev); 11492 struct bnxt *bp = netdev_priv(dev); 11493 11494 if (BNXT_PF(bp)) 11495 bnxt_sriov_disable(bp); 11496 11497 bnxt_dl_fw_reporters_destroy(bp, true); 11498 if (BNXT_PF(bp)) 11499 devlink_port_type_clear(&bp->dl_port); 11500 pci_disable_pcie_error_reporting(pdev); 11501 unregister_netdev(dev); 11502 bnxt_dl_unregister(bp); 11503 bnxt_shutdown_tc(bp); 11504 bnxt_cancel_sp_work(bp); 11505 bp->sp_event = 0; 11506 11507 bnxt_clear_int_mode(bp); 11508 bnxt_hwrm_func_drv_unrgtr(bp); 11509 bnxt_free_hwrm_resources(bp); 11510 bnxt_free_hwrm_short_cmd_req(bp); 11511 bnxt_ethtool_free(bp); 11512 bnxt_dcb_free(bp); 11513 kfree(bp->edev); 11514 bp->edev = NULL; 11515 kfree(bp->fw_health); 11516 bp->fw_health = NULL; 11517 bnxt_cleanup_pci(bp); 11518 bnxt_free_ctx_mem(bp); 11519 kfree(bp->ctx); 11520 bp->ctx = NULL; 11521 bnxt_free_port_stats(bp); 11522 free_netdev(dev); 11523 } 11524 11525 static int bnxt_probe_phy(struct bnxt *bp, bool fw_dflt) 11526 { 11527 int rc = 0; 11528 struct bnxt_link_info *link_info = &bp->link_info; 11529 11530 rc = bnxt_hwrm_phy_qcaps(bp); 11531 if (rc) { 11532 netdev_err(bp->dev, "Probe phy can't get phy capabilities (rc: %x)\n", 11533 rc); 11534 return rc; 11535 } 11536 if (!fw_dflt) 11537 return 0; 11538 11539 rc = bnxt_update_link(bp, false); 11540 if (rc) { 11541 netdev_err(bp->dev, "Probe phy can't update link (rc: %x)\n", 11542 rc); 11543 return rc; 11544 } 11545 11546 /* Older firmware does not have supported_auto_speeds, so assume 11547 * that all supported speeds can be autonegotiated. 11548 */ 11549 if (link_info->auto_link_speeds && !link_info->support_auto_speeds) 11550 link_info->support_auto_speeds = link_info->support_speeds; 11551 11552 bnxt_init_ethtool_link_settings(bp); 11553 return 0; 11554 } 11555 11556 static int bnxt_get_max_irq(struct pci_dev *pdev) 11557 { 11558 u16 ctrl; 11559 11560 if (!pdev->msix_cap) 11561 return 1; 11562 11563 pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &ctrl); 11564 return (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1; 11565 } 11566 11567 static void _bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx, 11568 int *max_cp) 11569 { 11570 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 11571 int max_ring_grps = 0, max_irq; 11572 11573 *max_tx = hw_resc->max_tx_rings; 11574 *max_rx = hw_resc->max_rx_rings; 11575 *max_cp = bnxt_get_max_func_cp_rings_for_en(bp); 11576 max_irq = min_t(int, bnxt_get_max_func_irqs(bp) - 11577 bnxt_get_ulp_msix_num(bp), 11578 hw_resc->max_stat_ctxs - bnxt_get_ulp_stat_ctxs(bp)); 11579 if (!(bp->flags & BNXT_FLAG_CHIP_P5)) 11580 *max_cp = min_t(int, *max_cp, max_irq); 11581 max_ring_grps = hw_resc->max_hw_ring_grps; 11582 if (BNXT_CHIP_TYPE_NITRO_A0(bp) && BNXT_PF(bp)) { 11583 *max_cp -= 1; 11584 *max_rx -= 2; 11585 } 11586 if (bp->flags & BNXT_FLAG_AGG_RINGS) 11587 *max_rx >>= 1; 11588 if (bp->flags & BNXT_FLAG_CHIP_P5) { 11589 bnxt_trim_rings(bp, max_rx, max_tx, *max_cp, false); 11590 /* On P5 chips, max_cp output param should be available NQs */ 11591 *max_cp = max_irq; 11592 } 11593 *max_rx = min_t(int, *max_rx, max_ring_grps); 11594 } 11595 11596 int bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx, bool shared) 11597 { 11598 int rx, tx, cp; 11599 11600 _bnxt_get_max_rings(bp, &rx, &tx, &cp); 11601 *max_rx = rx; 11602 *max_tx = tx; 11603 if (!rx || !tx || !cp) 11604 return -ENOMEM; 11605 11606 return bnxt_trim_rings(bp, max_rx, max_tx, cp, shared); 11607 } 11608 11609 static int bnxt_get_dflt_rings(struct bnxt *bp, int *max_rx, int *max_tx, 11610 bool shared) 11611 { 11612 int rc; 11613 11614 rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared); 11615 if (rc && (bp->flags & BNXT_FLAG_AGG_RINGS)) { 11616 /* Not enough rings, try disabling agg rings. */ 11617 bp->flags &= ~BNXT_FLAG_AGG_RINGS; 11618 rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared); 11619 if (rc) { 11620 /* set BNXT_FLAG_AGG_RINGS back for consistency */ 11621 bp->flags |= BNXT_FLAG_AGG_RINGS; 11622 return rc; 11623 } 11624 bp->flags |= BNXT_FLAG_NO_AGG_RINGS; 11625 bp->dev->hw_features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW); 11626 bp->dev->features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW); 11627 bnxt_set_ring_params(bp); 11628 } 11629 11630 if (bp->flags & BNXT_FLAG_ROCE_CAP) { 11631 int max_cp, max_stat, max_irq; 11632 11633 /* Reserve minimum resources for RoCE */ 11634 max_cp = bnxt_get_max_func_cp_rings(bp); 11635 max_stat = bnxt_get_max_func_stat_ctxs(bp); 11636 max_irq = bnxt_get_max_func_irqs(bp); 11637 if (max_cp <= BNXT_MIN_ROCE_CP_RINGS || 11638 max_irq <= BNXT_MIN_ROCE_CP_RINGS || 11639 max_stat <= BNXT_MIN_ROCE_STAT_CTXS) 11640 return 0; 11641 11642 max_cp -= BNXT_MIN_ROCE_CP_RINGS; 11643 max_irq -= BNXT_MIN_ROCE_CP_RINGS; 11644 max_stat -= BNXT_MIN_ROCE_STAT_CTXS; 11645 max_cp = min_t(int, max_cp, max_irq); 11646 max_cp = min_t(int, max_cp, max_stat); 11647 rc = bnxt_trim_rings(bp, max_rx, max_tx, max_cp, shared); 11648 if (rc) 11649 rc = 0; 11650 } 11651 return rc; 11652 } 11653 11654 /* In initial default shared ring setting, each shared ring must have a 11655 * RX/TX ring pair. 11656 */ 11657 static void bnxt_trim_dflt_sh_rings(struct bnxt *bp) 11658 { 11659 bp->cp_nr_rings = min_t(int, bp->tx_nr_rings_per_tc, bp->rx_nr_rings); 11660 bp->rx_nr_rings = bp->cp_nr_rings; 11661 bp->tx_nr_rings_per_tc = bp->cp_nr_rings; 11662 bp->tx_nr_rings = bp->tx_nr_rings_per_tc; 11663 } 11664 11665 static int bnxt_set_dflt_rings(struct bnxt *bp, bool sh) 11666 { 11667 int dflt_rings, max_rx_rings, max_tx_rings, rc; 11668 11669 if (!bnxt_can_reserve_rings(bp)) 11670 return 0; 11671 11672 if (sh) 11673 bp->flags |= BNXT_FLAG_SHARED_RINGS; 11674 dflt_rings = is_kdump_kernel() ? 1 : netif_get_num_default_rss_queues(); 11675 /* Reduce default rings on multi-port cards so that total default 11676 * rings do not exceed CPU count. 11677 */ 11678 if (bp->port_count > 1) { 11679 int max_rings = 11680 max_t(int, num_online_cpus() / bp->port_count, 1); 11681 11682 dflt_rings = min_t(int, dflt_rings, max_rings); 11683 } 11684 rc = bnxt_get_dflt_rings(bp, &max_rx_rings, &max_tx_rings, sh); 11685 if (rc) 11686 return rc; 11687 bp->rx_nr_rings = min_t(int, dflt_rings, max_rx_rings); 11688 bp->tx_nr_rings_per_tc = min_t(int, dflt_rings, max_tx_rings); 11689 if (sh) 11690 bnxt_trim_dflt_sh_rings(bp); 11691 else 11692 bp->cp_nr_rings = bp->tx_nr_rings_per_tc + bp->rx_nr_rings; 11693 bp->tx_nr_rings = bp->tx_nr_rings_per_tc; 11694 11695 rc = __bnxt_reserve_rings(bp); 11696 if (rc) 11697 netdev_warn(bp->dev, "Unable to reserve tx rings\n"); 11698 bp->tx_nr_rings_per_tc = bp->tx_nr_rings; 11699 if (sh) 11700 bnxt_trim_dflt_sh_rings(bp); 11701 11702 /* Rings may have been trimmed, re-reserve the trimmed rings. */ 11703 if (bnxt_need_reserve_rings(bp)) { 11704 rc = __bnxt_reserve_rings(bp); 11705 if (rc) 11706 netdev_warn(bp->dev, "2nd rings reservation failed.\n"); 11707 bp->tx_nr_rings_per_tc = bp->tx_nr_rings; 11708 } 11709 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) { 11710 bp->rx_nr_rings++; 11711 bp->cp_nr_rings++; 11712 } 11713 if (rc) { 11714 bp->tx_nr_rings = 0; 11715 bp->rx_nr_rings = 0; 11716 } 11717 return rc; 11718 } 11719 11720 static int bnxt_init_dflt_ring_mode(struct bnxt *bp) 11721 { 11722 int rc; 11723 11724 if (bp->tx_nr_rings) 11725 return 0; 11726 11727 bnxt_ulp_irq_stop(bp); 11728 bnxt_clear_int_mode(bp); 11729 rc = bnxt_set_dflt_rings(bp, true); 11730 if (rc) { 11731 netdev_err(bp->dev, "Not enough rings available.\n"); 11732 goto init_dflt_ring_err; 11733 } 11734 rc = bnxt_init_int_mode(bp); 11735 if (rc) 11736 goto init_dflt_ring_err; 11737 11738 bp->tx_nr_rings_per_tc = bp->tx_nr_rings; 11739 if (bnxt_rfs_supported(bp) && bnxt_rfs_capable(bp)) { 11740 bp->flags |= BNXT_FLAG_RFS; 11741 bp->dev->features |= NETIF_F_NTUPLE; 11742 } 11743 init_dflt_ring_err: 11744 bnxt_ulp_irq_restart(bp, rc); 11745 return rc; 11746 } 11747 11748 int bnxt_restore_pf_fw_resources(struct bnxt *bp) 11749 { 11750 int rc; 11751 11752 ASSERT_RTNL(); 11753 bnxt_hwrm_func_qcaps(bp); 11754 11755 if (netif_running(bp->dev)) 11756 __bnxt_close_nic(bp, true, false); 11757 11758 bnxt_ulp_irq_stop(bp); 11759 bnxt_clear_int_mode(bp); 11760 rc = bnxt_init_int_mode(bp); 11761 bnxt_ulp_irq_restart(bp, rc); 11762 11763 if (netif_running(bp->dev)) { 11764 if (rc) 11765 dev_close(bp->dev); 11766 else 11767 rc = bnxt_open_nic(bp, true, false); 11768 } 11769 11770 return rc; 11771 } 11772 11773 static int bnxt_init_mac_addr(struct bnxt *bp) 11774 { 11775 int rc = 0; 11776 11777 if (BNXT_PF(bp)) { 11778 memcpy(bp->dev->dev_addr, bp->pf.mac_addr, ETH_ALEN); 11779 } else { 11780 #ifdef CONFIG_BNXT_SRIOV 11781 struct bnxt_vf_info *vf = &bp->vf; 11782 bool strict_approval = true; 11783 11784 if (is_valid_ether_addr(vf->mac_addr)) { 11785 /* overwrite netdev dev_addr with admin VF MAC */ 11786 memcpy(bp->dev->dev_addr, vf->mac_addr, ETH_ALEN); 11787 /* Older PF driver or firmware may not approve this 11788 * correctly. 11789 */ 11790 strict_approval = false; 11791 } else { 11792 eth_hw_addr_random(bp->dev); 11793 } 11794 rc = bnxt_approve_mac(bp, bp->dev->dev_addr, strict_approval); 11795 #endif 11796 } 11797 return rc; 11798 } 11799 11800 #define BNXT_VPD_LEN 512 11801 static void bnxt_vpd_read_info(struct bnxt *bp) 11802 { 11803 struct pci_dev *pdev = bp->pdev; 11804 int i, len, pos, ro_size; 11805 ssize_t vpd_size; 11806 u8 *vpd_data; 11807 11808 vpd_data = kmalloc(BNXT_VPD_LEN, GFP_KERNEL); 11809 if (!vpd_data) 11810 return; 11811 11812 vpd_size = pci_read_vpd(pdev, 0, BNXT_VPD_LEN, vpd_data); 11813 if (vpd_size <= 0) { 11814 netdev_err(bp->dev, "Unable to read VPD\n"); 11815 goto exit; 11816 } 11817 11818 i = pci_vpd_find_tag(vpd_data, 0, vpd_size, PCI_VPD_LRDT_RO_DATA); 11819 if (i < 0) { 11820 netdev_err(bp->dev, "VPD READ-Only not found\n"); 11821 goto exit; 11822 } 11823 11824 ro_size = pci_vpd_lrdt_size(&vpd_data[i]); 11825 i += PCI_VPD_LRDT_TAG_SIZE; 11826 if (i + ro_size > vpd_size) 11827 goto exit; 11828 11829 pos = pci_vpd_find_info_keyword(vpd_data, i, ro_size, 11830 PCI_VPD_RO_KEYWORD_PARTNO); 11831 if (pos < 0) 11832 goto read_sn; 11833 11834 len = pci_vpd_info_field_size(&vpd_data[pos]); 11835 pos += PCI_VPD_INFO_FLD_HDR_SIZE; 11836 if (len + pos > vpd_size) 11837 goto read_sn; 11838 11839 strlcpy(bp->board_partno, &vpd_data[pos], min(len, BNXT_VPD_FLD_LEN)); 11840 11841 read_sn: 11842 pos = pci_vpd_find_info_keyword(vpd_data, i, ro_size, 11843 PCI_VPD_RO_KEYWORD_SERIALNO); 11844 if (pos < 0) 11845 goto exit; 11846 11847 len = pci_vpd_info_field_size(&vpd_data[pos]); 11848 pos += PCI_VPD_INFO_FLD_HDR_SIZE; 11849 if (len + pos > vpd_size) 11850 goto exit; 11851 11852 strlcpy(bp->board_serialno, &vpd_data[pos], min(len, BNXT_VPD_FLD_LEN)); 11853 exit: 11854 kfree(vpd_data); 11855 } 11856 11857 static int bnxt_pcie_dsn_get(struct bnxt *bp, u8 dsn[]) 11858 { 11859 struct pci_dev *pdev = bp->pdev; 11860 u64 qword; 11861 11862 qword = pci_get_dsn(pdev); 11863 if (!qword) { 11864 netdev_info(bp->dev, "Unable to read adapter's DSN\n"); 11865 return -EOPNOTSUPP; 11866 } 11867 11868 put_unaligned_le64(qword, dsn); 11869 11870 bp->flags |= BNXT_FLAG_DSN_VALID; 11871 return 0; 11872 } 11873 11874 static int bnxt_map_db_bar(struct bnxt *bp) 11875 { 11876 if (!bp->db_size) 11877 return -ENODEV; 11878 bp->bar1 = pci_iomap(bp->pdev, 2, bp->db_size); 11879 if (!bp->bar1) 11880 return -ENOMEM; 11881 return 0; 11882 } 11883 11884 static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 11885 { 11886 struct net_device *dev; 11887 struct bnxt *bp; 11888 int rc, max_irqs; 11889 11890 if (pci_is_bridge(pdev)) 11891 return -ENODEV; 11892 11893 /* Clear any pending DMA transactions from crash kernel 11894 * while loading driver in capture kernel. 11895 */ 11896 if (is_kdump_kernel()) { 11897 pci_clear_master(pdev); 11898 pcie_flr(pdev); 11899 } 11900 11901 max_irqs = bnxt_get_max_irq(pdev); 11902 dev = alloc_etherdev_mq(sizeof(*bp), max_irqs); 11903 if (!dev) 11904 return -ENOMEM; 11905 11906 bp = netdev_priv(dev); 11907 bnxt_set_max_func_irqs(bp, max_irqs); 11908 11909 if (bnxt_vf_pciid(ent->driver_data)) 11910 bp->flags |= BNXT_FLAG_VF; 11911 11912 if (pdev->msix_cap) 11913 bp->flags |= BNXT_FLAG_MSIX_CAP; 11914 11915 rc = bnxt_init_board(pdev, dev); 11916 if (rc < 0) 11917 goto init_err_free; 11918 11919 dev->netdev_ops = &bnxt_netdev_ops; 11920 dev->watchdog_timeo = BNXT_TX_TIMEOUT; 11921 dev->ethtool_ops = &bnxt_ethtool_ops; 11922 pci_set_drvdata(pdev, dev); 11923 11924 if (BNXT_PF(bp)) 11925 bnxt_vpd_read_info(bp); 11926 11927 rc = bnxt_alloc_hwrm_resources(bp); 11928 if (rc) 11929 goto init_err_pci_clean; 11930 11931 mutex_init(&bp->hwrm_cmd_lock); 11932 mutex_init(&bp->link_lock); 11933 11934 rc = bnxt_fw_init_one_p1(bp); 11935 if (rc) 11936 goto init_err_pci_clean; 11937 11938 if (BNXT_CHIP_P5(bp)) 11939 bp->flags |= BNXT_FLAG_CHIP_P5; 11940 11941 rc = bnxt_fw_init_one_p2(bp); 11942 if (rc) 11943 goto init_err_pci_clean; 11944 11945 rc = bnxt_map_db_bar(bp); 11946 if (rc) { 11947 dev_err(&pdev->dev, "Cannot map doorbell BAR rc = %d, aborting\n", 11948 rc); 11949 goto init_err_pci_clean; 11950 } 11951 11952 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG | 11953 NETIF_F_TSO | NETIF_F_TSO6 | 11954 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE | 11955 NETIF_F_GSO_IPXIP4 | 11956 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM | 11957 NETIF_F_GSO_PARTIAL | NETIF_F_RXHASH | 11958 NETIF_F_RXCSUM | NETIF_F_GRO; 11959 11960 if (BNXT_SUPPORTS_TPA(bp)) 11961 dev->hw_features |= NETIF_F_LRO; 11962 11963 dev->hw_enc_features = 11964 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG | 11965 NETIF_F_TSO | NETIF_F_TSO6 | 11966 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE | 11967 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM | 11968 NETIF_F_GSO_IPXIP4 | NETIF_F_GSO_PARTIAL; 11969 dev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM | 11970 NETIF_F_GSO_GRE_CSUM; 11971 dev->vlan_features = dev->hw_features | NETIF_F_HIGHDMA; 11972 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX | 11973 NETIF_F_HW_VLAN_STAG_RX | NETIF_F_HW_VLAN_STAG_TX; 11974 if (BNXT_SUPPORTS_TPA(bp)) 11975 dev->hw_features |= NETIF_F_GRO_HW; 11976 dev->features |= dev->hw_features | NETIF_F_HIGHDMA; 11977 if (dev->features & NETIF_F_GRO_HW) 11978 dev->features &= ~NETIF_F_LRO; 11979 dev->priv_flags |= IFF_UNICAST_FLT; 11980 11981 #ifdef CONFIG_BNXT_SRIOV 11982 init_waitqueue_head(&bp->sriov_cfg_wait); 11983 mutex_init(&bp->sriov_lock); 11984 #endif 11985 if (BNXT_SUPPORTS_TPA(bp)) { 11986 bp->gro_func = bnxt_gro_func_5730x; 11987 if (BNXT_CHIP_P4(bp)) 11988 bp->gro_func = bnxt_gro_func_5731x; 11989 else if (BNXT_CHIP_P5(bp)) 11990 bp->gro_func = bnxt_gro_func_5750x; 11991 } 11992 if (!BNXT_CHIP_P4_PLUS(bp)) 11993 bp->flags |= BNXT_FLAG_DOUBLE_DB; 11994 11995 bp->ulp_probe = bnxt_ulp_probe; 11996 11997 rc = bnxt_init_mac_addr(bp); 11998 if (rc) { 11999 dev_err(&pdev->dev, "Unable to initialize mac address.\n"); 12000 rc = -EADDRNOTAVAIL; 12001 goto init_err_pci_clean; 12002 } 12003 12004 if (BNXT_PF(bp)) { 12005 /* Read the adapter's DSN to use as the eswitch switch_id */ 12006 rc = bnxt_pcie_dsn_get(bp, bp->dsn); 12007 } 12008 12009 /* MTU range: 60 - FW defined max */ 12010 dev->min_mtu = ETH_ZLEN; 12011 dev->max_mtu = bp->max_mtu; 12012 12013 rc = bnxt_probe_phy(bp, true); 12014 if (rc) 12015 goto init_err_pci_clean; 12016 12017 bnxt_set_rx_skb_mode(bp, false); 12018 bnxt_set_tpa_flags(bp); 12019 bnxt_set_ring_params(bp); 12020 rc = bnxt_set_dflt_rings(bp, true); 12021 if (rc) { 12022 netdev_err(bp->dev, "Not enough rings available.\n"); 12023 rc = -ENOMEM; 12024 goto init_err_pci_clean; 12025 } 12026 12027 bnxt_fw_init_one_p3(bp); 12028 12029 if (dev->hw_features & NETIF_F_HW_VLAN_CTAG_RX) 12030 bp->flags |= BNXT_FLAG_STRIP_VLAN; 12031 12032 rc = bnxt_init_int_mode(bp); 12033 if (rc) 12034 goto init_err_pci_clean; 12035 12036 /* No TC has been set yet and rings may have been trimmed due to 12037 * limited MSIX, so we re-initialize the TX rings per TC. 12038 */ 12039 bp->tx_nr_rings_per_tc = bp->tx_nr_rings; 12040 12041 if (BNXT_PF(bp)) { 12042 if (!bnxt_pf_wq) { 12043 bnxt_pf_wq = 12044 create_singlethread_workqueue("bnxt_pf_wq"); 12045 if (!bnxt_pf_wq) { 12046 dev_err(&pdev->dev, "Unable to create workqueue.\n"); 12047 goto init_err_pci_clean; 12048 } 12049 } 12050 bnxt_init_tc(bp); 12051 } 12052 12053 bnxt_dl_register(bp); 12054 12055 rc = register_netdev(dev); 12056 if (rc) 12057 goto init_err_cleanup; 12058 12059 if (BNXT_PF(bp)) 12060 devlink_port_type_eth_set(&bp->dl_port, bp->dev); 12061 bnxt_dl_fw_reporters_create(bp); 12062 12063 netdev_info(dev, "%s found at mem %lx, node addr %pM\n", 12064 board_info[ent->driver_data].name, 12065 (long)pci_resource_start(pdev, 0), dev->dev_addr); 12066 pcie_print_link_status(pdev); 12067 12068 return 0; 12069 12070 init_err_cleanup: 12071 bnxt_dl_unregister(bp); 12072 bnxt_shutdown_tc(bp); 12073 bnxt_clear_int_mode(bp); 12074 12075 init_err_pci_clean: 12076 bnxt_hwrm_func_drv_unrgtr(bp); 12077 bnxt_free_hwrm_short_cmd_req(bp); 12078 bnxt_free_hwrm_resources(bp); 12079 kfree(bp->fw_health); 12080 bp->fw_health = NULL; 12081 bnxt_cleanup_pci(bp); 12082 bnxt_free_ctx_mem(bp); 12083 kfree(bp->ctx); 12084 bp->ctx = NULL; 12085 12086 init_err_free: 12087 free_netdev(dev); 12088 return rc; 12089 } 12090 12091 static void bnxt_shutdown(struct pci_dev *pdev) 12092 { 12093 struct net_device *dev = pci_get_drvdata(pdev); 12094 struct bnxt *bp; 12095 12096 if (!dev) 12097 return; 12098 12099 rtnl_lock(); 12100 bp = netdev_priv(dev); 12101 if (!bp) 12102 goto shutdown_exit; 12103 12104 if (netif_running(dev)) 12105 dev_close(dev); 12106 12107 bnxt_ulp_shutdown(bp); 12108 bnxt_clear_int_mode(bp); 12109 pci_disable_device(pdev); 12110 12111 if (system_state == SYSTEM_POWER_OFF) { 12112 pci_wake_from_d3(pdev, bp->wol); 12113 pci_set_power_state(pdev, PCI_D3hot); 12114 } 12115 12116 shutdown_exit: 12117 rtnl_unlock(); 12118 } 12119 12120 #ifdef CONFIG_PM_SLEEP 12121 static int bnxt_suspend(struct device *device) 12122 { 12123 struct net_device *dev = dev_get_drvdata(device); 12124 struct bnxt *bp = netdev_priv(dev); 12125 int rc = 0; 12126 12127 rtnl_lock(); 12128 bnxt_ulp_stop(bp); 12129 if (netif_running(dev)) { 12130 netif_device_detach(dev); 12131 rc = bnxt_close(dev); 12132 } 12133 bnxt_hwrm_func_drv_unrgtr(bp); 12134 pci_disable_device(bp->pdev); 12135 bnxt_free_ctx_mem(bp); 12136 kfree(bp->ctx); 12137 bp->ctx = NULL; 12138 rtnl_unlock(); 12139 return rc; 12140 } 12141 12142 static int bnxt_resume(struct device *device) 12143 { 12144 struct net_device *dev = dev_get_drvdata(device); 12145 struct bnxt *bp = netdev_priv(dev); 12146 int rc = 0; 12147 12148 rtnl_lock(); 12149 rc = pci_enable_device(bp->pdev); 12150 if (rc) { 12151 netdev_err(dev, "Cannot re-enable PCI device during resume, err = %d\n", 12152 rc); 12153 goto resume_exit; 12154 } 12155 pci_set_master(bp->pdev); 12156 if (bnxt_hwrm_ver_get(bp)) { 12157 rc = -ENODEV; 12158 goto resume_exit; 12159 } 12160 rc = bnxt_hwrm_func_reset(bp); 12161 if (rc) { 12162 rc = -EBUSY; 12163 goto resume_exit; 12164 } 12165 12166 rc = bnxt_hwrm_func_qcaps(bp); 12167 if (rc) 12168 goto resume_exit; 12169 12170 if (bnxt_hwrm_func_drv_rgtr(bp, NULL, 0, false)) { 12171 rc = -ENODEV; 12172 goto resume_exit; 12173 } 12174 12175 bnxt_get_wol_settings(bp); 12176 if (netif_running(dev)) { 12177 rc = bnxt_open(dev); 12178 if (!rc) 12179 netif_device_attach(dev); 12180 } 12181 12182 resume_exit: 12183 bnxt_ulp_start(bp, rc); 12184 if (!rc) 12185 bnxt_reenable_sriov(bp); 12186 rtnl_unlock(); 12187 return rc; 12188 } 12189 12190 static SIMPLE_DEV_PM_OPS(bnxt_pm_ops, bnxt_suspend, bnxt_resume); 12191 #define BNXT_PM_OPS (&bnxt_pm_ops) 12192 12193 #else 12194 12195 #define BNXT_PM_OPS NULL 12196 12197 #endif /* CONFIG_PM_SLEEP */ 12198 12199 /** 12200 * bnxt_io_error_detected - called when PCI error is detected 12201 * @pdev: Pointer to PCI device 12202 * @state: The current pci connection state 12203 * 12204 * This function is called after a PCI bus error affecting 12205 * this device has been detected. 12206 */ 12207 static pci_ers_result_t bnxt_io_error_detected(struct pci_dev *pdev, 12208 pci_channel_state_t state) 12209 { 12210 struct net_device *netdev = pci_get_drvdata(pdev); 12211 struct bnxt *bp = netdev_priv(netdev); 12212 12213 netdev_info(netdev, "PCI I/O error detected\n"); 12214 12215 rtnl_lock(); 12216 netif_device_detach(netdev); 12217 12218 bnxt_ulp_stop(bp); 12219 12220 if (state == pci_channel_io_perm_failure) { 12221 rtnl_unlock(); 12222 return PCI_ERS_RESULT_DISCONNECT; 12223 } 12224 12225 if (netif_running(netdev)) 12226 bnxt_close(netdev); 12227 12228 pci_disable_device(pdev); 12229 bnxt_free_ctx_mem(bp); 12230 kfree(bp->ctx); 12231 bp->ctx = NULL; 12232 rtnl_unlock(); 12233 12234 /* Request a slot slot reset. */ 12235 return PCI_ERS_RESULT_NEED_RESET; 12236 } 12237 12238 /** 12239 * bnxt_io_slot_reset - called after the pci bus has been reset. 12240 * @pdev: Pointer to PCI device 12241 * 12242 * Restart the card from scratch, as if from a cold-boot. 12243 * At this point, the card has exprienced a hard reset, 12244 * followed by fixups by BIOS, and has its config space 12245 * set up identically to what it was at cold boot. 12246 */ 12247 static pci_ers_result_t bnxt_io_slot_reset(struct pci_dev *pdev) 12248 { 12249 struct net_device *netdev = pci_get_drvdata(pdev); 12250 struct bnxt *bp = netdev_priv(netdev); 12251 int err = 0; 12252 pci_ers_result_t result = PCI_ERS_RESULT_DISCONNECT; 12253 12254 netdev_info(bp->dev, "PCI Slot Reset\n"); 12255 12256 rtnl_lock(); 12257 12258 if (pci_enable_device(pdev)) { 12259 dev_err(&pdev->dev, 12260 "Cannot re-enable PCI device after reset.\n"); 12261 } else { 12262 pci_set_master(pdev); 12263 12264 err = bnxt_hwrm_func_reset(bp); 12265 if (!err) { 12266 err = bnxt_hwrm_func_qcaps(bp); 12267 if (!err && netif_running(netdev)) 12268 err = bnxt_open(netdev); 12269 } 12270 bnxt_ulp_start(bp, err); 12271 if (!err) { 12272 bnxt_reenable_sriov(bp); 12273 result = PCI_ERS_RESULT_RECOVERED; 12274 } 12275 } 12276 12277 if (result != PCI_ERS_RESULT_RECOVERED) { 12278 if (netif_running(netdev)) 12279 dev_close(netdev); 12280 pci_disable_device(pdev); 12281 } 12282 12283 rtnl_unlock(); 12284 12285 return result; 12286 } 12287 12288 /** 12289 * bnxt_io_resume - called when traffic can start flowing again. 12290 * @pdev: Pointer to PCI device 12291 * 12292 * This callback is called when the error recovery driver tells 12293 * us that its OK to resume normal operation. 12294 */ 12295 static void bnxt_io_resume(struct pci_dev *pdev) 12296 { 12297 struct net_device *netdev = pci_get_drvdata(pdev); 12298 12299 rtnl_lock(); 12300 12301 netif_device_attach(netdev); 12302 12303 rtnl_unlock(); 12304 } 12305 12306 static const struct pci_error_handlers bnxt_err_handler = { 12307 .error_detected = bnxt_io_error_detected, 12308 .slot_reset = bnxt_io_slot_reset, 12309 .resume = bnxt_io_resume 12310 }; 12311 12312 static struct pci_driver bnxt_pci_driver = { 12313 .name = DRV_MODULE_NAME, 12314 .id_table = bnxt_pci_tbl, 12315 .probe = bnxt_init_one, 12316 .remove = bnxt_remove_one, 12317 .shutdown = bnxt_shutdown, 12318 .driver.pm = BNXT_PM_OPS, 12319 .err_handler = &bnxt_err_handler, 12320 #if defined(CONFIG_BNXT_SRIOV) 12321 .sriov_configure = bnxt_sriov_configure, 12322 #endif 12323 }; 12324 12325 static int __init bnxt_init(void) 12326 { 12327 bnxt_debug_init(); 12328 return pci_register_driver(&bnxt_pci_driver); 12329 } 12330 12331 static void __exit bnxt_exit(void) 12332 { 12333 pci_unregister_driver(&bnxt_pci_driver); 12334 if (bnxt_pf_wq) 12335 destroy_workqueue(bnxt_pf_wq); 12336 bnxt_debug_exit(); 12337 } 12338 12339 module_init(bnxt_init); 12340 module_exit(bnxt_exit); 12341