1 /* Broadcom NetXtreme-C/E network driver. 2 * 3 * Copyright (c) 2014-2016 Broadcom Corporation 4 * Copyright (c) 2016-2019 Broadcom Limited 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation. 9 */ 10 11 #include <linux/module.h> 12 13 #include <linux/stringify.h> 14 #include <linux/kernel.h> 15 #include <linux/timer.h> 16 #include <linux/errno.h> 17 #include <linux/ioport.h> 18 #include <linux/slab.h> 19 #include <linux/vmalloc.h> 20 #include <linux/interrupt.h> 21 #include <linux/pci.h> 22 #include <linux/netdevice.h> 23 #include <linux/etherdevice.h> 24 #include <linux/skbuff.h> 25 #include <linux/dma-mapping.h> 26 #include <linux/bitops.h> 27 #include <linux/io.h> 28 #include <linux/irq.h> 29 #include <linux/delay.h> 30 #include <asm/byteorder.h> 31 #include <asm/page.h> 32 #include <linux/time.h> 33 #include <linux/mii.h> 34 #include <linux/mdio.h> 35 #include <linux/if.h> 36 #include <linux/if_vlan.h> 37 #include <linux/if_bridge.h> 38 #include <linux/rtc.h> 39 #include <linux/bpf.h> 40 #include <net/ip.h> 41 #include <net/tcp.h> 42 #include <net/udp.h> 43 #include <net/checksum.h> 44 #include <net/ip6_checksum.h> 45 #include <net/udp_tunnel.h> 46 #include <linux/workqueue.h> 47 #include <linux/prefetch.h> 48 #include <linux/cache.h> 49 #include <linux/log2.h> 50 #include <linux/aer.h> 51 #include <linux/bitmap.h> 52 #include <linux/cpu_rmap.h> 53 #include <linux/cpumask.h> 54 #include <net/pkt_cls.h> 55 #include <linux/hwmon.h> 56 #include <linux/hwmon-sysfs.h> 57 58 #include "bnxt_hsi.h" 59 #include "bnxt.h" 60 #include "bnxt_ulp.h" 61 #include "bnxt_sriov.h" 62 #include "bnxt_ethtool.h" 63 #include "bnxt_dcb.h" 64 #include "bnxt_xdp.h" 65 #include "bnxt_vfr.h" 66 #include "bnxt_tc.h" 67 #include "bnxt_devlink.h" 68 #include "bnxt_debugfs.h" 69 70 #define BNXT_TX_TIMEOUT (5 * HZ) 71 72 static const char version[] = 73 "Broadcom NetXtreme-C/E driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION "\n"; 74 75 MODULE_LICENSE("GPL"); 76 MODULE_DESCRIPTION("Broadcom BCM573xx network driver"); 77 MODULE_VERSION(DRV_MODULE_VERSION); 78 79 #define BNXT_RX_OFFSET (NET_SKB_PAD + NET_IP_ALIGN) 80 #define BNXT_RX_DMA_OFFSET NET_SKB_PAD 81 #define BNXT_RX_COPY_THRESH 256 82 83 #define BNXT_TX_PUSH_THRESH 164 84 85 enum board_idx { 86 BCM57301, 87 BCM57302, 88 BCM57304, 89 BCM57417_NPAR, 90 BCM58700, 91 BCM57311, 92 BCM57312, 93 BCM57402, 94 BCM57404, 95 BCM57406, 96 BCM57402_NPAR, 97 BCM57407, 98 BCM57412, 99 BCM57414, 100 BCM57416, 101 BCM57417, 102 BCM57412_NPAR, 103 BCM57314, 104 BCM57417_SFP, 105 BCM57416_SFP, 106 BCM57404_NPAR, 107 BCM57406_NPAR, 108 BCM57407_SFP, 109 BCM57407_NPAR, 110 BCM57414_NPAR, 111 BCM57416_NPAR, 112 BCM57452, 113 BCM57454, 114 BCM5745x_NPAR, 115 BCM57508, 116 BCM57504, 117 BCM57502, 118 BCM58802, 119 BCM58804, 120 BCM58808, 121 NETXTREME_E_VF, 122 NETXTREME_C_VF, 123 NETXTREME_S_VF, 124 NETXTREME_E_P5_VF, 125 }; 126 127 /* indexed by enum above */ 128 static const struct { 129 char *name; 130 } board_info[] = { 131 [BCM57301] = { "Broadcom BCM57301 NetXtreme-C 10Gb Ethernet" }, 132 [BCM57302] = { "Broadcom BCM57302 NetXtreme-C 10Gb/25Gb Ethernet" }, 133 [BCM57304] = { "Broadcom BCM57304 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" }, 134 [BCM57417_NPAR] = { "Broadcom BCM57417 NetXtreme-E Ethernet Partition" }, 135 [BCM58700] = { "Broadcom BCM58700 Nitro 1Gb/2.5Gb/10Gb Ethernet" }, 136 [BCM57311] = { "Broadcom BCM57311 NetXtreme-C 10Gb Ethernet" }, 137 [BCM57312] = { "Broadcom BCM57312 NetXtreme-C 10Gb/25Gb Ethernet" }, 138 [BCM57402] = { "Broadcom BCM57402 NetXtreme-E 10Gb Ethernet" }, 139 [BCM57404] = { "Broadcom BCM57404 NetXtreme-E 10Gb/25Gb Ethernet" }, 140 [BCM57406] = { "Broadcom BCM57406 NetXtreme-E 10GBase-T Ethernet" }, 141 [BCM57402_NPAR] = { "Broadcom BCM57402 NetXtreme-E Ethernet Partition" }, 142 [BCM57407] = { "Broadcom BCM57407 NetXtreme-E 10GBase-T Ethernet" }, 143 [BCM57412] = { "Broadcom BCM57412 NetXtreme-E 10Gb Ethernet" }, 144 [BCM57414] = { "Broadcom BCM57414 NetXtreme-E 10Gb/25Gb Ethernet" }, 145 [BCM57416] = { "Broadcom BCM57416 NetXtreme-E 10GBase-T Ethernet" }, 146 [BCM57417] = { "Broadcom BCM57417 NetXtreme-E 10GBase-T Ethernet" }, 147 [BCM57412_NPAR] = { "Broadcom BCM57412 NetXtreme-E Ethernet Partition" }, 148 [BCM57314] = { "Broadcom BCM57314 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" }, 149 [BCM57417_SFP] = { "Broadcom BCM57417 NetXtreme-E 10Gb/25Gb Ethernet" }, 150 [BCM57416_SFP] = { "Broadcom BCM57416 NetXtreme-E 10Gb Ethernet" }, 151 [BCM57404_NPAR] = { "Broadcom BCM57404 NetXtreme-E Ethernet Partition" }, 152 [BCM57406_NPAR] = { "Broadcom BCM57406 NetXtreme-E Ethernet Partition" }, 153 [BCM57407_SFP] = { "Broadcom BCM57407 NetXtreme-E 25Gb Ethernet" }, 154 [BCM57407_NPAR] = { "Broadcom BCM57407 NetXtreme-E Ethernet Partition" }, 155 [BCM57414_NPAR] = { "Broadcom BCM57414 NetXtreme-E Ethernet Partition" }, 156 [BCM57416_NPAR] = { "Broadcom BCM57416 NetXtreme-E Ethernet Partition" }, 157 [BCM57452] = { "Broadcom BCM57452 NetXtreme-E 10Gb/25Gb/40Gb/50Gb Ethernet" }, 158 [BCM57454] = { "Broadcom BCM57454 NetXtreme-E 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" }, 159 [BCM5745x_NPAR] = { "Broadcom BCM5745x NetXtreme-E Ethernet Partition" }, 160 [BCM57508] = { "Broadcom BCM57508 NetXtreme-E 10Gb/25Gb/50Gb/100Gb/200Gb Ethernet" }, 161 [BCM57504] = { "Broadcom BCM57504 NetXtreme-E 10Gb/25Gb/50Gb/100Gb/200Gb Ethernet" }, 162 [BCM57502] = { "Broadcom BCM57502 NetXtreme-E 10Gb/25Gb/50Gb Ethernet" }, 163 [BCM58802] = { "Broadcom BCM58802 NetXtreme-S 10Gb/25Gb/40Gb/50Gb Ethernet" }, 164 [BCM58804] = { "Broadcom BCM58804 NetXtreme-S 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" }, 165 [BCM58808] = { "Broadcom BCM58808 NetXtreme-S 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" }, 166 [NETXTREME_E_VF] = { "Broadcom NetXtreme-E Ethernet Virtual Function" }, 167 [NETXTREME_C_VF] = { "Broadcom NetXtreme-C Ethernet Virtual Function" }, 168 [NETXTREME_S_VF] = { "Broadcom NetXtreme-S Ethernet Virtual Function" }, 169 [NETXTREME_E_P5_VF] = { "Broadcom BCM5750X NetXtreme-E Ethernet Virtual Function" }, 170 }; 171 172 static const struct pci_device_id bnxt_pci_tbl[] = { 173 { PCI_VDEVICE(BROADCOM, 0x1604), .driver_data = BCM5745x_NPAR }, 174 { PCI_VDEVICE(BROADCOM, 0x1605), .driver_data = BCM5745x_NPAR }, 175 { PCI_VDEVICE(BROADCOM, 0x1614), .driver_data = BCM57454 }, 176 { PCI_VDEVICE(BROADCOM, 0x16c0), .driver_data = BCM57417_NPAR }, 177 { PCI_VDEVICE(BROADCOM, 0x16c8), .driver_data = BCM57301 }, 178 { PCI_VDEVICE(BROADCOM, 0x16c9), .driver_data = BCM57302 }, 179 { PCI_VDEVICE(BROADCOM, 0x16ca), .driver_data = BCM57304 }, 180 { PCI_VDEVICE(BROADCOM, 0x16cc), .driver_data = BCM57417_NPAR }, 181 { PCI_VDEVICE(BROADCOM, 0x16cd), .driver_data = BCM58700 }, 182 { PCI_VDEVICE(BROADCOM, 0x16ce), .driver_data = BCM57311 }, 183 { PCI_VDEVICE(BROADCOM, 0x16cf), .driver_data = BCM57312 }, 184 { PCI_VDEVICE(BROADCOM, 0x16d0), .driver_data = BCM57402 }, 185 { PCI_VDEVICE(BROADCOM, 0x16d1), .driver_data = BCM57404 }, 186 { PCI_VDEVICE(BROADCOM, 0x16d2), .driver_data = BCM57406 }, 187 { PCI_VDEVICE(BROADCOM, 0x16d4), .driver_data = BCM57402_NPAR }, 188 { PCI_VDEVICE(BROADCOM, 0x16d5), .driver_data = BCM57407 }, 189 { PCI_VDEVICE(BROADCOM, 0x16d6), .driver_data = BCM57412 }, 190 { PCI_VDEVICE(BROADCOM, 0x16d7), .driver_data = BCM57414 }, 191 { PCI_VDEVICE(BROADCOM, 0x16d8), .driver_data = BCM57416 }, 192 { PCI_VDEVICE(BROADCOM, 0x16d9), .driver_data = BCM57417 }, 193 { PCI_VDEVICE(BROADCOM, 0x16de), .driver_data = BCM57412_NPAR }, 194 { PCI_VDEVICE(BROADCOM, 0x16df), .driver_data = BCM57314 }, 195 { PCI_VDEVICE(BROADCOM, 0x16e2), .driver_data = BCM57417_SFP }, 196 { PCI_VDEVICE(BROADCOM, 0x16e3), .driver_data = BCM57416_SFP }, 197 { PCI_VDEVICE(BROADCOM, 0x16e7), .driver_data = BCM57404_NPAR }, 198 { PCI_VDEVICE(BROADCOM, 0x16e8), .driver_data = BCM57406_NPAR }, 199 { PCI_VDEVICE(BROADCOM, 0x16e9), .driver_data = BCM57407_SFP }, 200 { PCI_VDEVICE(BROADCOM, 0x16ea), .driver_data = BCM57407_NPAR }, 201 { PCI_VDEVICE(BROADCOM, 0x16eb), .driver_data = BCM57412_NPAR }, 202 { PCI_VDEVICE(BROADCOM, 0x16ec), .driver_data = BCM57414_NPAR }, 203 { PCI_VDEVICE(BROADCOM, 0x16ed), .driver_data = BCM57414_NPAR }, 204 { PCI_VDEVICE(BROADCOM, 0x16ee), .driver_data = BCM57416_NPAR }, 205 { PCI_VDEVICE(BROADCOM, 0x16ef), .driver_data = BCM57416_NPAR }, 206 { PCI_VDEVICE(BROADCOM, 0x16f0), .driver_data = BCM58808 }, 207 { PCI_VDEVICE(BROADCOM, 0x16f1), .driver_data = BCM57452 }, 208 { PCI_VDEVICE(BROADCOM, 0x1750), .driver_data = BCM57508 }, 209 { PCI_VDEVICE(BROADCOM, 0x1751), .driver_data = BCM57504 }, 210 { PCI_VDEVICE(BROADCOM, 0x1752), .driver_data = BCM57502 }, 211 { PCI_VDEVICE(BROADCOM, 0xd802), .driver_data = BCM58802 }, 212 { PCI_VDEVICE(BROADCOM, 0xd804), .driver_data = BCM58804 }, 213 #ifdef CONFIG_BNXT_SRIOV 214 { PCI_VDEVICE(BROADCOM, 0x1606), .driver_data = NETXTREME_E_VF }, 215 { PCI_VDEVICE(BROADCOM, 0x1609), .driver_data = NETXTREME_E_VF }, 216 { PCI_VDEVICE(BROADCOM, 0x16c1), .driver_data = NETXTREME_E_VF }, 217 { PCI_VDEVICE(BROADCOM, 0x16cb), .driver_data = NETXTREME_C_VF }, 218 { PCI_VDEVICE(BROADCOM, 0x16d3), .driver_data = NETXTREME_E_VF }, 219 { PCI_VDEVICE(BROADCOM, 0x16dc), .driver_data = NETXTREME_E_VF }, 220 { PCI_VDEVICE(BROADCOM, 0x16e1), .driver_data = NETXTREME_C_VF }, 221 { PCI_VDEVICE(BROADCOM, 0x16e5), .driver_data = NETXTREME_C_VF }, 222 { PCI_VDEVICE(BROADCOM, 0x1806), .driver_data = NETXTREME_E_P5_VF }, 223 { PCI_VDEVICE(BROADCOM, 0x1807), .driver_data = NETXTREME_E_P5_VF }, 224 { PCI_VDEVICE(BROADCOM, 0xd800), .driver_data = NETXTREME_S_VF }, 225 #endif 226 { 0 } 227 }; 228 229 MODULE_DEVICE_TABLE(pci, bnxt_pci_tbl); 230 231 static const u16 bnxt_vf_req_snif[] = { 232 HWRM_FUNC_CFG, 233 HWRM_FUNC_VF_CFG, 234 HWRM_PORT_PHY_QCFG, 235 HWRM_CFA_L2_FILTER_ALLOC, 236 }; 237 238 static const u16 bnxt_async_events_arr[] = { 239 ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE, 240 ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD, 241 ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED, 242 ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE, 243 ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE, 244 }; 245 246 static struct workqueue_struct *bnxt_pf_wq; 247 248 static bool bnxt_vf_pciid(enum board_idx idx) 249 { 250 return (idx == NETXTREME_C_VF || idx == NETXTREME_E_VF || 251 idx == NETXTREME_S_VF || idx == NETXTREME_E_P5_VF); 252 } 253 254 #define DB_CP_REARM_FLAGS (DB_KEY_CP | DB_IDX_VALID) 255 #define DB_CP_FLAGS (DB_KEY_CP | DB_IDX_VALID | DB_IRQ_DIS) 256 #define DB_CP_IRQ_DIS_FLAGS (DB_KEY_CP | DB_IRQ_DIS) 257 258 #define BNXT_CP_DB_IRQ_DIS(db) \ 259 writel(DB_CP_IRQ_DIS_FLAGS, db) 260 261 #define BNXT_DB_CQ(db, idx) \ 262 writel(DB_CP_FLAGS | RING_CMP(idx), (db)->doorbell) 263 264 #define BNXT_DB_NQ_P5(db, idx) \ 265 writeq((db)->db_key64 | DBR_TYPE_NQ | RING_CMP(idx), (db)->doorbell) 266 267 #define BNXT_DB_CQ_ARM(db, idx) \ 268 writel(DB_CP_REARM_FLAGS | RING_CMP(idx), (db)->doorbell) 269 270 #define BNXT_DB_NQ_ARM_P5(db, idx) \ 271 writeq((db)->db_key64 | DBR_TYPE_NQ_ARM | RING_CMP(idx), (db)->doorbell) 272 273 static void bnxt_db_nq(struct bnxt *bp, struct bnxt_db_info *db, u32 idx) 274 { 275 if (bp->flags & BNXT_FLAG_CHIP_P5) 276 BNXT_DB_NQ_P5(db, idx); 277 else 278 BNXT_DB_CQ(db, idx); 279 } 280 281 static void bnxt_db_nq_arm(struct bnxt *bp, struct bnxt_db_info *db, u32 idx) 282 { 283 if (bp->flags & BNXT_FLAG_CHIP_P5) 284 BNXT_DB_NQ_ARM_P5(db, idx); 285 else 286 BNXT_DB_CQ_ARM(db, idx); 287 } 288 289 static void bnxt_db_cq(struct bnxt *bp, struct bnxt_db_info *db, u32 idx) 290 { 291 if (bp->flags & BNXT_FLAG_CHIP_P5) 292 writeq(db->db_key64 | DBR_TYPE_CQ_ARMALL | RING_CMP(idx), 293 db->doorbell); 294 else 295 BNXT_DB_CQ(db, idx); 296 } 297 298 const u16 bnxt_lhint_arr[] = { 299 TX_BD_FLAGS_LHINT_512_AND_SMALLER, 300 TX_BD_FLAGS_LHINT_512_TO_1023, 301 TX_BD_FLAGS_LHINT_1024_TO_2047, 302 TX_BD_FLAGS_LHINT_1024_TO_2047, 303 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 304 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 305 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 306 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 307 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 308 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 309 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 310 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 311 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 312 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 313 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 314 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 315 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 316 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 317 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 318 }; 319 320 static u16 bnxt_xmit_get_cfa_action(struct sk_buff *skb) 321 { 322 struct metadata_dst *md_dst = skb_metadata_dst(skb); 323 324 if (!md_dst || md_dst->type != METADATA_HW_PORT_MUX) 325 return 0; 326 327 return md_dst->u.port_info.port_id; 328 } 329 330 static netdev_tx_t bnxt_start_xmit(struct sk_buff *skb, struct net_device *dev) 331 { 332 struct bnxt *bp = netdev_priv(dev); 333 struct tx_bd *txbd; 334 struct tx_bd_ext *txbd1; 335 struct netdev_queue *txq; 336 int i; 337 dma_addr_t mapping; 338 unsigned int length, pad = 0; 339 u32 len, free_size, vlan_tag_flags, cfa_action, flags; 340 u16 prod, last_frag; 341 struct pci_dev *pdev = bp->pdev; 342 struct bnxt_tx_ring_info *txr; 343 struct bnxt_sw_tx_bd *tx_buf; 344 345 i = skb_get_queue_mapping(skb); 346 if (unlikely(i >= bp->tx_nr_rings)) { 347 dev_kfree_skb_any(skb); 348 return NETDEV_TX_OK; 349 } 350 351 txq = netdev_get_tx_queue(dev, i); 352 txr = &bp->tx_ring[bp->tx_ring_map[i]]; 353 prod = txr->tx_prod; 354 355 free_size = bnxt_tx_avail(bp, txr); 356 if (unlikely(free_size < skb_shinfo(skb)->nr_frags + 2)) { 357 netif_tx_stop_queue(txq); 358 return NETDEV_TX_BUSY; 359 } 360 361 length = skb->len; 362 len = skb_headlen(skb); 363 last_frag = skb_shinfo(skb)->nr_frags; 364 365 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)]; 366 367 txbd->tx_bd_opaque = prod; 368 369 tx_buf = &txr->tx_buf_ring[prod]; 370 tx_buf->skb = skb; 371 tx_buf->nr_frags = last_frag; 372 373 vlan_tag_flags = 0; 374 cfa_action = bnxt_xmit_get_cfa_action(skb); 375 if (skb_vlan_tag_present(skb)) { 376 vlan_tag_flags = TX_BD_CFA_META_KEY_VLAN | 377 skb_vlan_tag_get(skb); 378 /* Currently supports 8021Q, 8021AD vlan offloads 379 * QINQ1, QINQ2, QINQ3 vlan headers are deprecated 380 */ 381 if (skb->vlan_proto == htons(ETH_P_8021Q)) 382 vlan_tag_flags |= 1 << TX_BD_CFA_META_TPID_SHIFT; 383 } 384 385 if (free_size == bp->tx_ring_size && length <= bp->tx_push_thresh) { 386 struct tx_push_buffer *tx_push_buf = txr->tx_push; 387 struct tx_push_bd *tx_push = &tx_push_buf->push_bd; 388 struct tx_bd_ext *tx_push1 = &tx_push->txbd2; 389 void __iomem *db = txr->tx_db.doorbell; 390 void *pdata = tx_push_buf->data; 391 u64 *end; 392 int j, push_len; 393 394 /* Set COAL_NOW to be ready quickly for the next push */ 395 tx_push->tx_bd_len_flags_type = 396 cpu_to_le32((length << TX_BD_LEN_SHIFT) | 397 TX_BD_TYPE_LONG_TX_BD | 398 TX_BD_FLAGS_LHINT_512_AND_SMALLER | 399 TX_BD_FLAGS_COAL_NOW | 400 TX_BD_FLAGS_PACKET_END | 401 (2 << TX_BD_FLAGS_BD_CNT_SHIFT)); 402 403 if (skb->ip_summed == CHECKSUM_PARTIAL) 404 tx_push1->tx_bd_hsize_lflags = 405 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM); 406 else 407 tx_push1->tx_bd_hsize_lflags = 0; 408 409 tx_push1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags); 410 tx_push1->tx_bd_cfa_action = 411 cpu_to_le32(cfa_action << TX_BD_CFA_ACTION_SHIFT); 412 413 end = pdata + length; 414 end = PTR_ALIGN(end, 8) - 1; 415 *end = 0; 416 417 skb_copy_from_linear_data(skb, pdata, len); 418 pdata += len; 419 for (j = 0; j < last_frag; j++) { 420 skb_frag_t *frag = &skb_shinfo(skb)->frags[j]; 421 void *fptr; 422 423 fptr = skb_frag_address_safe(frag); 424 if (!fptr) 425 goto normal_tx; 426 427 memcpy(pdata, fptr, skb_frag_size(frag)); 428 pdata += skb_frag_size(frag); 429 } 430 431 txbd->tx_bd_len_flags_type = tx_push->tx_bd_len_flags_type; 432 txbd->tx_bd_haddr = txr->data_mapping; 433 prod = NEXT_TX(prod); 434 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)]; 435 memcpy(txbd, tx_push1, sizeof(*txbd)); 436 prod = NEXT_TX(prod); 437 tx_push->doorbell = 438 cpu_to_le32(DB_KEY_TX_PUSH | DB_LONG_TX_PUSH | prod); 439 txr->tx_prod = prod; 440 441 tx_buf->is_push = 1; 442 netdev_tx_sent_queue(txq, skb->len); 443 wmb(); /* Sync is_push and byte queue before pushing data */ 444 445 push_len = (length + sizeof(*tx_push) + 7) / 8; 446 if (push_len > 16) { 447 __iowrite64_copy(db, tx_push_buf, 16); 448 __iowrite32_copy(db + 4, tx_push_buf + 1, 449 (push_len - 16) << 1); 450 } else { 451 __iowrite64_copy(db, tx_push_buf, push_len); 452 } 453 454 goto tx_done; 455 } 456 457 normal_tx: 458 if (length < BNXT_MIN_PKT_SIZE) { 459 pad = BNXT_MIN_PKT_SIZE - length; 460 if (skb_pad(skb, pad)) { 461 /* SKB already freed. */ 462 tx_buf->skb = NULL; 463 return NETDEV_TX_OK; 464 } 465 length = BNXT_MIN_PKT_SIZE; 466 } 467 468 mapping = dma_map_single(&pdev->dev, skb->data, len, DMA_TO_DEVICE); 469 470 if (unlikely(dma_mapping_error(&pdev->dev, mapping))) { 471 dev_kfree_skb_any(skb); 472 tx_buf->skb = NULL; 473 return NETDEV_TX_OK; 474 } 475 476 dma_unmap_addr_set(tx_buf, mapping, mapping); 477 flags = (len << TX_BD_LEN_SHIFT) | TX_BD_TYPE_LONG_TX_BD | 478 ((last_frag + 2) << TX_BD_FLAGS_BD_CNT_SHIFT); 479 480 txbd->tx_bd_haddr = cpu_to_le64(mapping); 481 482 prod = NEXT_TX(prod); 483 txbd1 = (struct tx_bd_ext *) 484 &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)]; 485 486 txbd1->tx_bd_hsize_lflags = 0; 487 if (skb_is_gso(skb)) { 488 u32 hdr_len; 489 490 if (skb->encapsulation) 491 hdr_len = skb_inner_network_offset(skb) + 492 skb_inner_network_header_len(skb) + 493 inner_tcp_hdrlen(skb); 494 else 495 hdr_len = skb_transport_offset(skb) + 496 tcp_hdrlen(skb); 497 498 txbd1->tx_bd_hsize_lflags = cpu_to_le32(TX_BD_FLAGS_LSO | 499 TX_BD_FLAGS_T_IPID | 500 (hdr_len << (TX_BD_HSIZE_SHIFT - 1))); 501 length = skb_shinfo(skb)->gso_size; 502 txbd1->tx_bd_mss = cpu_to_le32(length); 503 length += hdr_len; 504 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 505 txbd1->tx_bd_hsize_lflags = 506 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM); 507 txbd1->tx_bd_mss = 0; 508 } 509 510 length >>= 9; 511 if (unlikely(length >= ARRAY_SIZE(bnxt_lhint_arr))) { 512 dev_warn_ratelimited(&pdev->dev, "Dropped oversize %d bytes TX packet.\n", 513 skb->len); 514 i = 0; 515 goto tx_dma_error; 516 } 517 flags |= bnxt_lhint_arr[length]; 518 txbd->tx_bd_len_flags_type = cpu_to_le32(flags); 519 520 txbd1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags); 521 txbd1->tx_bd_cfa_action = 522 cpu_to_le32(cfa_action << TX_BD_CFA_ACTION_SHIFT); 523 for (i = 0; i < last_frag; i++) { 524 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 525 526 prod = NEXT_TX(prod); 527 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)]; 528 529 len = skb_frag_size(frag); 530 mapping = skb_frag_dma_map(&pdev->dev, frag, 0, len, 531 DMA_TO_DEVICE); 532 533 if (unlikely(dma_mapping_error(&pdev->dev, mapping))) 534 goto tx_dma_error; 535 536 tx_buf = &txr->tx_buf_ring[prod]; 537 dma_unmap_addr_set(tx_buf, mapping, mapping); 538 539 txbd->tx_bd_haddr = cpu_to_le64(mapping); 540 541 flags = len << TX_BD_LEN_SHIFT; 542 txbd->tx_bd_len_flags_type = cpu_to_le32(flags); 543 } 544 545 flags &= ~TX_BD_LEN; 546 txbd->tx_bd_len_flags_type = 547 cpu_to_le32(((len + pad) << TX_BD_LEN_SHIFT) | flags | 548 TX_BD_FLAGS_PACKET_END); 549 550 netdev_tx_sent_queue(txq, skb->len); 551 552 /* Sync BD data before updating doorbell */ 553 wmb(); 554 555 prod = NEXT_TX(prod); 556 txr->tx_prod = prod; 557 558 if (!netdev_xmit_more() || netif_xmit_stopped(txq)) 559 bnxt_db_write(bp, &txr->tx_db, prod); 560 561 tx_done: 562 563 if (unlikely(bnxt_tx_avail(bp, txr) <= MAX_SKB_FRAGS + 1)) { 564 if (netdev_xmit_more() && !tx_buf->is_push) 565 bnxt_db_write(bp, &txr->tx_db, prod); 566 567 netif_tx_stop_queue(txq); 568 569 /* netif_tx_stop_queue() must be done before checking 570 * tx index in bnxt_tx_avail() below, because in 571 * bnxt_tx_int(), we update tx index before checking for 572 * netif_tx_queue_stopped(). 573 */ 574 smp_mb(); 575 if (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh) 576 netif_tx_wake_queue(txq); 577 } 578 return NETDEV_TX_OK; 579 580 tx_dma_error: 581 last_frag = i; 582 583 /* start back at beginning and unmap skb */ 584 prod = txr->tx_prod; 585 tx_buf = &txr->tx_buf_ring[prod]; 586 tx_buf->skb = NULL; 587 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping), 588 skb_headlen(skb), PCI_DMA_TODEVICE); 589 prod = NEXT_TX(prod); 590 591 /* unmap remaining mapped pages */ 592 for (i = 0; i < last_frag; i++) { 593 prod = NEXT_TX(prod); 594 tx_buf = &txr->tx_buf_ring[prod]; 595 dma_unmap_page(&pdev->dev, dma_unmap_addr(tx_buf, mapping), 596 skb_frag_size(&skb_shinfo(skb)->frags[i]), 597 PCI_DMA_TODEVICE); 598 } 599 600 dev_kfree_skb_any(skb); 601 return NETDEV_TX_OK; 602 } 603 604 static void bnxt_tx_int(struct bnxt *bp, struct bnxt_napi *bnapi, int nr_pkts) 605 { 606 struct bnxt_tx_ring_info *txr = bnapi->tx_ring; 607 struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, txr->txq_index); 608 u16 cons = txr->tx_cons; 609 struct pci_dev *pdev = bp->pdev; 610 int i; 611 unsigned int tx_bytes = 0; 612 613 for (i = 0; i < nr_pkts; i++) { 614 struct bnxt_sw_tx_bd *tx_buf; 615 struct sk_buff *skb; 616 int j, last; 617 618 tx_buf = &txr->tx_buf_ring[cons]; 619 cons = NEXT_TX(cons); 620 skb = tx_buf->skb; 621 tx_buf->skb = NULL; 622 623 if (tx_buf->is_push) { 624 tx_buf->is_push = 0; 625 goto next_tx_int; 626 } 627 628 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping), 629 skb_headlen(skb), PCI_DMA_TODEVICE); 630 last = tx_buf->nr_frags; 631 632 for (j = 0; j < last; j++) { 633 cons = NEXT_TX(cons); 634 tx_buf = &txr->tx_buf_ring[cons]; 635 dma_unmap_page( 636 &pdev->dev, 637 dma_unmap_addr(tx_buf, mapping), 638 skb_frag_size(&skb_shinfo(skb)->frags[j]), 639 PCI_DMA_TODEVICE); 640 } 641 642 next_tx_int: 643 cons = NEXT_TX(cons); 644 645 tx_bytes += skb->len; 646 dev_kfree_skb_any(skb); 647 } 648 649 netdev_tx_completed_queue(txq, nr_pkts, tx_bytes); 650 txr->tx_cons = cons; 651 652 /* Need to make the tx_cons update visible to bnxt_start_xmit() 653 * before checking for netif_tx_queue_stopped(). Without the 654 * memory barrier, there is a small possibility that bnxt_start_xmit() 655 * will miss it and cause the queue to be stopped forever. 656 */ 657 smp_mb(); 658 659 if (unlikely(netif_tx_queue_stopped(txq)) && 660 (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)) { 661 __netif_tx_lock(txq, smp_processor_id()); 662 if (netif_tx_queue_stopped(txq) && 663 bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh && 664 txr->dev_state != BNXT_DEV_STATE_CLOSING) 665 netif_tx_wake_queue(txq); 666 __netif_tx_unlock(txq); 667 } 668 } 669 670 static struct page *__bnxt_alloc_rx_page(struct bnxt *bp, dma_addr_t *mapping, 671 gfp_t gfp) 672 { 673 struct device *dev = &bp->pdev->dev; 674 struct page *page; 675 676 page = alloc_page(gfp); 677 if (!page) 678 return NULL; 679 680 *mapping = dma_map_page_attrs(dev, page, 0, PAGE_SIZE, bp->rx_dir, 681 DMA_ATTR_WEAK_ORDERING); 682 if (dma_mapping_error(dev, *mapping)) { 683 __free_page(page); 684 return NULL; 685 } 686 *mapping += bp->rx_dma_offset; 687 return page; 688 } 689 690 static inline u8 *__bnxt_alloc_rx_data(struct bnxt *bp, dma_addr_t *mapping, 691 gfp_t gfp) 692 { 693 u8 *data; 694 struct pci_dev *pdev = bp->pdev; 695 696 data = kmalloc(bp->rx_buf_size, gfp); 697 if (!data) 698 return NULL; 699 700 *mapping = dma_map_single_attrs(&pdev->dev, data + bp->rx_dma_offset, 701 bp->rx_buf_use_size, bp->rx_dir, 702 DMA_ATTR_WEAK_ORDERING); 703 704 if (dma_mapping_error(&pdev->dev, *mapping)) { 705 kfree(data); 706 data = NULL; 707 } 708 return data; 709 } 710 711 int bnxt_alloc_rx_data(struct bnxt *bp, struct bnxt_rx_ring_info *rxr, 712 u16 prod, gfp_t gfp) 713 { 714 struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)]; 715 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[prod]; 716 dma_addr_t mapping; 717 718 if (BNXT_RX_PAGE_MODE(bp)) { 719 struct page *page = __bnxt_alloc_rx_page(bp, &mapping, gfp); 720 721 if (!page) 722 return -ENOMEM; 723 724 rx_buf->data = page; 725 rx_buf->data_ptr = page_address(page) + bp->rx_offset; 726 } else { 727 u8 *data = __bnxt_alloc_rx_data(bp, &mapping, gfp); 728 729 if (!data) 730 return -ENOMEM; 731 732 rx_buf->data = data; 733 rx_buf->data_ptr = data + bp->rx_offset; 734 } 735 rx_buf->mapping = mapping; 736 737 rxbd->rx_bd_haddr = cpu_to_le64(mapping); 738 return 0; 739 } 740 741 void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons, void *data) 742 { 743 u16 prod = rxr->rx_prod; 744 struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf; 745 struct rx_bd *cons_bd, *prod_bd; 746 747 prod_rx_buf = &rxr->rx_buf_ring[prod]; 748 cons_rx_buf = &rxr->rx_buf_ring[cons]; 749 750 prod_rx_buf->data = data; 751 prod_rx_buf->data_ptr = cons_rx_buf->data_ptr; 752 753 prod_rx_buf->mapping = cons_rx_buf->mapping; 754 755 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)]; 756 cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)]; 757 758 prod_bd->rx_bd_haddr = cons_bd->rx_bd_haddr; 759 } 760 761 static inline u16 bnxt_find_next_agg_idx(struct bnxt_rx_ring_info *rxr, u16 idx) 762 { 763 u16 next, max = rxr->rx_agg_bmap_size; 764 765 next = find_next_zero_bit(rxr->rx_agg_bmap, max, idx); 766 if (next >= max) 767 next = find_first_zero_bit(rxr->rx_agg_bmap, max); 768 return next; 769 } 770 771 static inline int bnxt_alloc_rx_page(struct bnxt *bp, 772 struct bnxt_rx_ring_info *rxr, 773 u16 prod, gfp_t gfp) 774 { 775 struct rx_bd *rxbd = 776 &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)]; 777 struct bnxt_sw_rx_agg_bd *rx_agg_buf; 778 struct pci_dev *pdev = bp->pdev; 779 struct page *page; 780 dma_addr_t mapping; 781 u16 sw_prod = rxr->rx_sw_agg_prod; 782 unsigned int offset = 0; 783 784 if (PAGE_SIZE > BNXT_RX_PAGE_SIZE) { 785 page = rxr->rx_page; 786 if (!page) { 787 page = alloc_page(gfp); 788 if (!page) 789 return -ENOMEM; 790 rxr->rx_page = page; 791 rxr->rx_page_offset = 0; 792 } 793 offset = rxr->rx_page_offset; 794 rxr->rx_page_offset += BNXT_RX_PAGE_SIZE; 795 if (rxr->rx_page_offset == PAGE_SIZE) 796 rxr->rx_page = NULL; 797 else 798 get_page(page); 799 } else { 800 page = alloc_page(gfp); 801 if (!page) 802 return -ENOMEM; 803 } 804 805 mapping = dma_map_page_attrs(&pdev->dev, page, offset, 806 BNXT_RX_PAGE_SIZE, PCI_DMA_FROMDEVICE, 807 DMA_ATTR_WEAK_ORDERING); 808 if (dma_mapping_error(&pdev->dev, mapping)) { 809 __free_page(page); 810 return -EIO; 811 } 812 813 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap))) 814 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod); 815 816 __set_bit(sw_prod, rxr->rx_agg_bmap); 817 rx_agg_buf = &rxr->rx_agg_ring[sw_prod]; 818 rxr->rx_sw_agg_prod = NEXT_RX_AGG(sw_prod); 819 820 rx_agg_buf->page = page; 821 rx_agg_buf->offset = offset; 822 rx_agg_buf->mapping = mapping; 823 rxbd->rx_bd_haddr = cpu_to_le64(mapping); 824 rxbd->rx_bd_opaque = sw_prod; 825 return 0; 826 } 827 828 static void bnxt_reuse_rx_agg_bufs(struct bnxt_cp_ring_info *cpr, u16 cp_cons, 829 u32 agg_bufs) 830 { 831 struct bnxt_napi *bnapi = cpr->bnapi; 832 struct bnxt *bp = bnapi->bp; 833 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 834 u16 prod = rxr->rx_agg_prod; 835 u16 sw_prod = rxr->rx_sw_agg_prod; 836 u32 i; 837 838 for (i = 0; i < agg_bufs; i++) { 839 u16 cons; 840 struct rx_agg_cmp *agg; 841 struct bnxt_sw_rx_agg_bd *cons_rx_buf, *prod_rx_buf; 842 struct rx_bd *prod_bd; 843 struct page *page; 844 845 agg = (struct rx_agg_cmp *) 846 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 847 cons = agg->rx_agg_cmp_opaque; 848 __clear_bit(cons, rxr->rx_agg_bmap); 849 850 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap))) 851 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod); 852 853 __set_bit(sw_prod, rxr->rx_agg_bmap); 854 prod_rx_buf = &rxr->rx_agg_ring[sw_prod]; 855 cons_rx_buf = &rxr->rx_agg_ring[cons]; 856 857 /* It is possible for sw_prod to be equal to cons, so 858 * set cons_rx_buf->page to NULL first. 859 */ 860 page = cons_rx_buf->page; 861 cons_rx_buf->page = NULL; 862 prod_rx_buf->page = page; 863 prod_rx_buf->offset = cons_rx_buf->offset; 864 865 prod_rx_buf->mapping = cons_rx_buf->mapping; 866 867 prod_bd = &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)]; 868 869 prod_bd->rx_bd_haddr = cpu_to_le64(cons_rx_buf->mapping); 870 prod_bd->rx_bd_opaque = sw_prod; 871 872 prod = NEXT_RX_AGG(prod); 873 sw_prod = NEXT_RX_AGG(sw_prod); 874 cp_cons = NEXT_CMP(cp_cons); 875 } 876 rxr->rx_agg_prod = prod; 877 rxr->rx_sw_agg_prod = sw_prod; 878 } 879 880 static struct sk_buff *bnxt_rx_page_skb(struct bnxt *bp, 881 struct bnxt_rx_ring_info *rxr, 882 u16 cons, void *data, u8 *data_ptr, 883 dma_addr_t dma_addr, 884 unsigned int offset_and_len) 885 { 886 unsigned int payload = offset_and_len >> 16; 887 unsigned int len = offset_and_len & 0xffff; 888 struct skb_frag_struct *frag; 889 struct page *page = data; 890 u16 prod = rxr->rx_prod; 891 struct sk_buff *skb; 892 int off, err; 893 894 err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC); 895 if (unlikely(err)) { 896 bnxt_reuse_rx_data(rxr, cons, data); 897 return NULL; 898 } 899 dma_addr -= bp->rx_dma_offset; 900 dma_unmap_page_attrs(&bp->pdev->dev, dma_addr, PAGE_SIZE, bp->rx_dir, 901 DMA_ATTR_WEAK_ORDERING); 902 903 if (unlikely(!payload)) 904 payload = eth_get_headlen(bp->dev, data_ptr, len); 905 906 skb = napi_alloc_skb(&rxr->bnapi->napi, payload); 907 if (!skb) { 908 __free_page(page); 909 return NULL; 910 } 911 912 off = (void *)data_ptr - page_address(page); 913 skb_add_rx_frag(skb, 0, page, off, len, PAGE_SIZE); 914 memcpy(skb->data - NET_IP_ALIGN, data_ptr - NET_IP_ALIGN, 915 payload + NET_IP_ALIGN); 916 917 frag = &skb_shinfo(skb)->frags[0]; 918 skb_frag_size_sub(frag, payload); 919 frag->page_offset += payload; 920 skb->data_len -= payload; 921 skb->tail += payload; 922 923 return skb; 924 } 925 926 static struct sk_buff *bnxt_rx_skb(struct bnxt *bp, 927 struct bnxt_rx_ring_info *rxr, u16 cons, 928 void *data, u8 *data_ptr, 929 dma_addr_t dma_addr, 930 unsigned int offset_and_len) 931 { 932 u16 prod = rxr->rx_prod; 933 struct sk_buff *skb; 934 int err; 935 936 err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC); 937 if (unlikely(err)) { 938 bnxt_reuse_rx_data(rxr, cons, data); 939 return NULL; 940 } 941 942 skb = build_skb(data, 0); 943 dma_unmap_single_attrs(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size, 944 bp->rx_dir, DMA_ATTR_WEAK_ORDERING); 945 if (!skb) { 946 kfree(data); 947 return NULL; 948 } 949 950 skb_reserve(skb, bp->rx_offset); 951 skb_put(skb, offset_and_len & 0xffff); 952 return skb; 953 } 954 955 static struct sk_buff *bnxt_rx_pages(struct bnxt *bp, 956 struct bnxt_cp_ring_info *cpr, 957 struct sk_buff *skb, u16 cp_cons, 958 u32 agg_bufs) 959 { 960 struct bnxt_napi *bnapi = cpr->bnapi; 961 struct pci_dev *pdev = bp->pdev; 962 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 963 u16 prod = rxr->rx_agg_prod; 964 u32 i; 965 966 for (i = 0; i < agg_bufs; i++) { 967 u16 cons, frag_len; 968 struct rx_agg_cmp *agg; 969 struct bnxt_sw_rx_agg_bd *cons_rx_buf; 970 struct page *page; 971 dma_addr_t mapping; 972 973 agg = (struct rx_agg_cmp *) 974 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 975 cons = agg->rx_agg_cmp_opaque; 976 frag_len = (le32_to_cpu(agg->rx_agg_cmp_len_flags_type) & 977 RX_AGG_CMP_LEN) >> RX_AGG_CMP_LEN_SHIFT; 978 979 cons_rx_buf = &rxr->rx_agg_ring[cons]; 980 skb_fill_page_desc(skb, i, cons_rx_buf->page, 981 cons_rx_buf->offset, frag_len); 982 __clear_bit(cons, rxr->rx_agg_bmap); 983 984 /* It is possible for bnxt_alloc_rx_page() to allocate 985 * a sw_prod index that equals the cons index, so we 986 * need to clear the cons entry now. 987 */ 988 mapping = cons_rx_buf->mapping; 989 page = cons_rx_buf->page; 990 cons_rx_buf->page = NULL; 991 992 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_ATOMIC) != 0) { 993 struct skb_shared_info *shinfo; 994 unsigned int nr_frags; 995 996 shinfo = skb_shinfo(skb); 997 nr_frags = --shinfo->nr_frags; 998 __skb_frag_set_page(&shinfo->frags[nr_frags], NULL); 999 1000 dev_kfree_skb(skb); 1001 1002 cons_rx_buf->page = page; 1003 1004 /* Update prod since possibly some pages have been 1005 * allocated already. 1006 */ 1007 rxr->rx_agg_prod = prod; 1008 bnxt_reuse_rx_agg_bufs(cpr, cp_cons, agg_bufs - i); 1009 return NULL; 1010 } 1011 1012 dma_unmap_page_attrs(&pdev->dev, mapping, BNXT_RX_PAGE_SIZE, 1013 PCI_DMA_FROMDEVICE, 1014 DMA_ATTR_WEAK_ORDERING); 1015 1016 skb->data_len += frag_len; 1017 skb->len += frag_len; 1018 skb->truesize += PAGE_SIZE; 1019 1020 prod = NEXT_RX_AGG(prod); 1021 cp_cons = NEXT_CMP(cp_cons); 1022 } 1023 rxr->rx_agg_prod = prod; 1024 return skb; 1025 } 1026 1027 static int bnxt_agg_bufs_valid(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, 1028 u8 agg_bufs, u32 *raw_cons) 1029 { 1030 u16 last; 1031 struct rx_agg_cmp *agg; 1032 1033 *raw_cons = ADV_RAW_CMP(*raw_cons, agg_bufs); 1034 last = RING_CMP(*raw_cons); 1035 agg = (struct rx_agg_cmp *) 1036 &cpr->cp_desc_ring[CP_RING(last)][CP_IDX(last)]; 1037 return RX_AGG_CMP_VALID(agg, *raw_cons); 1038 } 1039 1040 static inline struct sk_buff *bnxt_copy_skb(struct bnxt_napi *bnapi, u8 *data, 1041 unsigned int len, 1042 dma_addr_t mapping) 1043 { 1044 struct bnxt *bp = bnapi->bp; 1045 struct pci_dev *pdev = bp->pdev; 1046 struct sk_buff *skb; 1047 1048 skb = napi_alloc_skb(&bnapi->napi, len); 1049 if (!skb) 1050 return NULL; 1051 1052 dma_sync_single_for_cpu(&pdev->dev, mapping, bp->rx_copy_thresh, 1053 bp->rx_dir); 1054 1055 memcpy(skb->data - NET_IP_ALIGN, data - NET_IP_ALIGN, 1056 len + NET_IP_ALIGN); 1057 1058 dma_sync_single_for_device(&pdev->dev, mapping, bp->rx_copy_thresh, 1059 bp->rx_dir); 1060 1061 skb_put(skb, len); 1062 return skb; 1063 } 1064 1065 static int bnxt_discard_rx(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, 1066 u32 *raw_cons, void *cmp) 1067 { 1068 struct rx_cmp *rxcmp = cmp; 1069 u32 tmp_raw_cons = *raw_cons; 1070 u8 cmp_type, agg_bufs = 0; 1071 1072 cmp_type = RX_CMP_TYPE(rxcmp); 1073 1074 if (cmp_type == CMP_TYPE_RX_L2_CMP) { 1075 agg_bufs = (le32_to_cpu(rxcmp->rx_cmp_misc_v1) & 1076 RX_CMP_AGG_BUFS) >> 1077 RX_CMP_AGG_BUFS_SHIFT; 1078 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) { 1079 struct rx_tpa_end_cmp *tpa_end = cmp; 1080 1081 agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) & 1082 RX_TPA_END_CMP_AGG_BUFS) >> 1083 RX_TPA_END_CMP_AGG_BUFS_SHIFT; 1084 } 1085 1086 if (agg_bufs) { 1087 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons)) 1088 return -EBUSY; 1089 } 1090 *raw_cons = tmp_raw_cons; 1091 return 0; 1092 } 1093 1094 static void bnxt_queue_sp_work(struct bnxt *bp) 1095 { 1096 if (BNXT_PF(bp)) 1097 queue_work(bnxt_pf_wq, &bp->sp_task); 1098 else 1099 schedule_work(&bp->sp_task); 1100 } 1101 1102 static void bnxt_cancel_sp_work(struct bnxt *bp) 1103 { 1104 if (BNXT_PF(bp)) 1105 flush_workqueue(bnxt_pf_wq); 1106 else 1107 cancel_work_sync(&bp->sp_task); 1108 } 1109 1110 static void bnxt_sched_reset(struct bnxt *bp, struct bnxt_rx_ring_info *rxr) 1111 { 1112 if (!rxr->bnapi->in_reset) { 1113 rxr->bnapi->in_reset = true; 1114 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event); 1115 bnxt_queue_sp_work(bp); 1116 } 1117 rxr->rx_next_cons = 0xffff; 1118 } 1119 1120 static void bnxt_tpa_start(struct bnxt *bp, struct bnxt_rx_ring_info *rxr, 1121 struct rx_tpa_start_cmp *tpa_start, 1122 struct rx_tpa_start_cmp_ext *tpa_start1) 1123 { 1124 u8 agg_id = TPA_START_AGG_ID(tpa_start); 1125 u16 cons, prod; 1126 struct bnxt_tpa_info *tpa_info; 1127 struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf; 1128 struct rx_bd *prod_bd; 1129 dma_addr_t mapping; 1130 1131 cons = tpa_start->rx_tpa_start_cmp_opaque; 1132 prod = rxr->rx_prod; 1133 cons_rx_buf = &rxr->rx_buf_ring[cons]; 1134 prod_rx_buf = &rxr->rx_buf_ring[prod]; 1135 tpa_info = &rxr->rx_tpa[agg_id]; 1136 1137 if (unlikely(cons != rxr->rx_next_cons)) { 1138 netdev_warn(bp->dev, "TPA cons %x != expected cons %x\n", 1139 cons, rxr->rx_next_cons); 1140 bnxt_sched_reset(bp, rxr); 1141 return; 1142 } 1143 /* Store cfa_code in tpa_info to use in tpa_end 1144 * completion processing. 1145 */ 1146 tpa_info->cfa_code = TPA_START_CFA_CODE(tpa_start1); 1147 prod_rx_buf->data = tpa_info->data; 1148 prod_rx_buf->data_ptr = tpa_info->data_ptr; 1149 1150 mapping = tpa_info->mapping; 1151 prod_rx_buf->mapping = mapping; 1152 1153 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)]; 1154 1155 prod_bd->rx_bd_haddr = cpu_to_le64(mapping); 1156 1157 tpa_info->data = cons_rx_buf->data; 1158 tpa_info->data_ptr = cons_rx_buf->data_ptr; 1159 cons_rx_buf->data = NULL; 1160 tpa_info->mapping = cons_rx_buf->mapping; 1161 1162 tpa_info->len = 1163 le32_to_cpu(tpa_start->rx_tpa_start_cmp_len_flags_type) >> 1164 RX_TPA_START_CMP_LEN_SHIFT; 1165 if (likely(TPA_START_HASH_VALID(tpa_start))) { 1166 u32 hash_type = TPA_START_HASH_TYPE(tpa_start); 1167 1168 tpa_info->hash_type = PKT_HASH_TYPE_L4; 1169 tpa_info->gso_type = SKB_GSO_TCPV4; 1170 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */ 1171 if (hash_type == 3 || TPA_START_IS_IPV6(tpa_start1)) 1172 tpa_info->gso_type = SKB_GSO_TCPV6; 1173 tpa_info->rss_hash = 1174 le32_to_cpu(tpa_start->rx_tpa_start_cmp_rss_hash); 1175 } else { 1176 tpa_info->hash_type = PKT_HASH_TYPE_NONE; 1177 tpa_info->gso_type = 0; 1178 if (netif_msg_rx_err(bp)) 1179 netdev_warn(bp->dev, "TPA packet without valid hash\n"); 1180 } 1181 tpa_info->flags2 = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_flags2); 1182 tpa_info->metadata = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_metadata); 1183 tpa_info->hdr_info = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_hdr_info); 1184 1185 rxr->rx_prod = NEXT_RX(prod); 1186 cons = NEXT_RX(cons); 1187 rxr->rx_next_cons = NEXT_RX(cons); 1188 cons_rx_buf = &rxr->rx_buf_ring[cons]; 1189 1190 bnxt_reuse_rx_data(rxr, cons, cons_rx_buf->data); 1191 rxr->rx_prod = NEXT_RX(rxr->rx_prod); 1192 cons_rx_buf->data = NULL; 1193 } 1194 1195 static void bnxt_abort_tpa(struct bnxt_cp_ring_info *cpr, u16 cp_cons, 1196 u32 agg_bufs) 1197 { 1198 if (agg_bufs) 1199 bnxt_reuse_rx_agg_bufs(cpr, cp_cons, agg_bufs); 1200 } 1201 1202 static struct sk_buff *bnxt_gro_func_5731x(struct bnxt_tpa_info *tpa_info, 1203 int payload_off, int tcp_ts, 1204 struct sk_buff *skb) 1205 { 1206 #ifdef CONFIG_INET 1207 struct tcphdr *th; 1208 int len, nw_off; 1209 u16 outer_ip_off, inner_ip_off, inner_mac_off; 1210 u32 hdr_info = tpa_info->hdr_info; 1211 bool loopback = false; 1212 1213 inner_ip_off = BNXT_TPA_INNER_L3_OFF(hdr_info); 1214 inner_mac_off = BNXT_TPA_INNER_L2_OFF(hdr_info); 1215 outer_ip_off = BNXT_TPA_OUTER_L3_OFF(hdr_info); 1216 1217 /* If the packet is an internal loopback packet, the offsets will 1218 * have an extra 4 bytes. 1219 */ 1220 if (inner_mac_off == 4) { 1221 loopback = true; 1222 } else if (inner_mac_off > 4) { 1223 __be16 proto = *((__be16 *)(skb->data + inner_ip_off - 1224 ETH_HLEN - 2)); 1225 1226 /* We only support inner iPv4/ipv6. If we don't see the 1227 * correct protocol ID, it must be a loopback packet where 1228 * the offsets are off by 4. 1229 */ 1230 if (proto != htons(ETH_P_IP) && proto != htons(ETH_P_IPV6)) 1231 loopback = true; 1232 } 1233 if (loopback) { 1234 /* internal loopback packet, subtract all offsets by 4 */ 1235 inner_ip_off -= 4; 1236 inner_mac_off -= 4; 1237 outer_ip_off -= 4; 1238 } 1239 1240 nw_off = inner_ip_off - ETH_HLEN; 1241 skb_set_network_header(skb, nw_off); 1242 if (tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_IP_TYPE) { 1243 struct ipv6hdr *iph = ipv6_hdr(skb); 1244 1245 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr)); 1246 len = skb->len - skb_transport_offset(skb); 1247 th = tcp_hdr(skb); 1248 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0); 1249 } else { 1250 struct iphdr *iph = ip_hdr(skb); 1251 1252 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr)); 1253 len = skb->len - skb_transport_offset(skb); 1254 th = tcp_hdr(skb); 1255 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0); 1256 } 1257 1258 if (inner_mac_off) { /* tunnel */ 1259 struct udphdr *uh = NULL; 1260 __be16 proto = *((__be16 *)(skb->data + outer_ip_off - 1261 ETH_HLEN - 2)); 1262 1263 if (proto == htons(ETH_P_IP)) { 1264 struct iphdr *iph = (struct iphdr *)skb->data; 1265 1266 if (iph->protocol == IPPROTO_UDP) 1267 uh = (struct udphdr *)(iph + 1); 1268 } else { 1269 struct ipv6hdr *iph = (struct ipv6hdr *)skb->data; 1270 1271 if (iph->nexthdr == IPPROTO_UDP) 1272 uh = (struct udphdr *)(iph + 1); 1273 } 1274 if (uh) { 1275 if (uh->check) 1276 skb_shinfo(skb)->gso_type |= 1277 SKB_GSO_UDP_TUNNEL_CSUM; 1278 else 1279 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL; 1280 } 1281 } 1282 #endif 1283 return skb; 1284 } 1285 1286 #define BNXT_IPV4_HDR_SIZE (sizeof(struct iphdr) + sizeof(struct tcphdr)) 1287 #define BNXT_IPV6_HDR_SIZE (sizeof(struct ipv6hdr) + sizeof(struct tcphdr)) 1288 1289 static struct sk_buff *bnxt_gro_func_5730x(struct bnxt_tpa_info *tpa_info, 1290 int payload_off, int tcp_ts, 1291 struct sk_buff *skb) 1292 { 1293 #ifdef CONFIG_INET 1294 struct tcphdr *th; 1295 int len, nw_off, tcp_opt_len = 0; 1296 1297 if (tcp_ts) 1298 tcp_opt_len = 12; 1299 1300 if (tpa_info->gso_type == SKB_GSO_TCPV4) { 1301 struct iphdr *iph; 1302 1303 nw_off = payload_off - BNXT_IPV4_HDR_SIZE - tcp_opt_len - 1304 ETH_HLEN; 1305 skb_set_network_header(skb, nw_off); 1306 iph = ip_hdr(skb); 1307 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr)); 1308 len = skb->len - skb_transport_offset(skb); 1309 th = tcp_hdr(skb); 1310 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0); 1311 } else if (tpa_info->gso_type == SKB_GSO_TCPV6) { 1312 struct ipv6hdr *iph; 1313 1314 nw_off = payload_off - BNXT_IPV6_HDR_SIZE - tcp_opt_len - 1315 ETH_HLEN; 1316 skb_set_network_header(skb, nw_off); 1317 iph = ipv6_hdr(skb); 1318 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr)); 1319 len = skb->len - skb_transport_offset(skb); 1320 th = tcp_hdr(skb); 1321 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0); 1322 } else { 1323 dev_kfree_skb_any(skb); 1324 return NULL; 1325 } 1326 1327 if (nw_off) { /* tunnel */ 1328 struct udphdr *uh = NULL; 1329 1330 if (skb->protocol == htons(ETH_P_IP)) { 1331 struct iphdr *iph = (struct iphdr *)skb->data; 1332 1333 if (iph->protocol == IPPROTO_UDP) 1334 uh = (struct udphdr *)(iph + 1); 1335 } else { 1336 struct ipv6hdr *iph = (struct ipv6hdr *)skb->data; 1337 1338 if (iph->nexthdr == IPPROTO_UDP) 1339 uh = (struct udphdr *)(iph + 1); 1340 } 1341 if (uh) { 1342 if (uh->check) 1343 skb_shinfo(skb)->gso_type |= 1344 SKB_GSO_UDP_TUNNEL_CSUM; 1345 else 1346 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL; 1347 } 1348 } 1349 #endif 1350 return skb; 1351 } 1352 1353 static inline struct sk_buff *bnxt_gro_skb(struct bnxt *bp, 1354 struct bnxt_tpa_info *tpa_info, 1355 struct rx_tpa_end_cmp *tpa_end, 1356 struct rx_tpa_end_cmp_ext *tpa_end1, 1357 struct sk_buff *skb) 1358 { 1359 #ifdef CONFIG_INET 1360 int payload_off; 1361 u16 segs; 1362 1363 segs = TPA_END_TPA_SEGS(tpa_end); 1364 if (segs == 1) 1365 return skb; 1366 1367 NAPI_GRO_CB(skb)->count = segs; 1368 skb_shinfo(skb)->gso_size = 1369 le32_to_cpu(tpa_end1->rx_tpa_end_cmp_seg_len); 1370 skb_shinfo(skb)->gso_type = tpa_info->gso_type; 1371 payload_off = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) & 1372 RX_TPA_END_CMP_PAYLOAD_OFFSET) >> 1373 RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT; 1374 skb = bp->gro_func(tpa_info, payload_off, TPA_END_GRO_TS(tpa_end), skb); 1375 if (likely(skb)) 1376 tcp_gro_complete(skb); 1377 #endif 1378 return skb; 1379 } 1380 1381 /* Given the cfa_code of a received packet determine which 1382 * netdev (vf-rep or PF) the packet is destined to. 1383 */ 1384 static struct net_device *bnxt_get_pkt_dev(struct bnxt *bp, u16 cfa_code) 1385 { 1386 struct net_device *dev = bnxt_get_vf_rep(bp, cfa_code); 1387 1388 /* if vf-rep dev is NULL, the must belongs to the PF */ 1389 return dev ? dev : bp->dev; 1390 } 1391 1392 static inline struct sk_buff *bnxt_tpa_end(struct bnxt *bp, 1393 struct bnxt_cp_ring_info *cpr, 1394 u32 *raw_cons, 1395 struct rx_tpa_end_cmp *tpa_end, 1396 struct rx_tpa_end_cmp_ext *tpa_end1, 1397 u8 *event) 1398 { 1399 struct bnxt_napi *bnapi = cpr->bnapi; 1400 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 1401 u8 agg_id = TPA_END_AGG_ID(tpa_end); 1402 u8 *data_ptr, agg_bufs; 1403 u16 cp_cons = RING_CMP(*raw_cons); 1404 unsigned int len; 1405 struct bnxt_tpa_info *tpa_info; 1406 dma_addr_t mapping; 1407 struct sk_buff *skb; 1408 void *data; 1409 1410 if (unlikely(bnapi->in_reset)) { 1411 int rc = bnxt_discard_rx(bp, cpr, raw_cons, tpa_end); 1412 1413 if (rc < 0) 1414 return ERR_PTR(-EBUSY); 1415 return NULL; 1416 } 1417 1418 tpa_info = &rxr->rx_tpa[agg_id]; 1419 data = tpa_info->data; 1420 data_ptr = tpa_info->data_ptr; 1421 prefetch(data_ptr); 1422 len = tpa_info->len; 1423 mapping = tpa_info->mapping; 1424 1425 agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) & 1426 RX_TPA_END_CMP_AGG_BUFS) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT; 1427 1428 if (agg_bufs) { 1429 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, raw_cons)) 1430 return ERR_PTR(-EBUSY); 1431 1432 *event |= BNXT_AGG_EVENT; 1433 cp_cons = NEXT_CMP(cp_cons); 1434 } 1435 1436 if (unlikely(agg_bufs > MAX_SKB_FRAGS || TPA_END_ERRORS(tpa_end1))) { 1437 bnxt_abort_tpa(cpr, cp_cons, agg_bufs); 1438 if (agg_bufs > MAX_SKB_FRAGS) 1439 netdev_warn(bp->dev, "TPA frags %d exceeded MAX_SKB_FRAGS %d\n", 1440 agg_bufs, (int)MAX_SKB_FRAGS); 1441 return NULL; 1442 } 1443 1444 if (len <= bp->rx_copy_thresh) { 1445 skb = bnxt_copy_skb(bnapi, data_ptr, len, mapping); 1446 if (!skb) { 1447 bnxt_abort_tpa(cpr, cp_cons, agg_bufs); 1448 return NULL; 1449 } 1450 } else { 1451 u8 *new_data; 1452 dma_addr_t new_mapping; 1453 1454 new_data = __bnxt_alloc_rx_data(bp, &new_mapping, GFP_ATOMIC); 1455 if (!new_data) { 1456 bnxt_abort_tpa(cpr, cp_cons, agg_bufs); 1457 return NULL; 1458 } 1459 1460 tpa_info->data = new_data; 1461 tpa_info->data_ptr = new_data + bp->rx_offset; 1462 tpa_info->mapping = new_mapping; 1463 1464 skb = build_skb(data, 0); 1465 dma_unmap_single_attrs(&bp->pdev->dev, mapping, 1466 bp->rx_buf_use_size, bp->rx_dir, 1467 DMA_ATTR_WEAK_ORDERING); 1468 1469 if (!skb) { 1470 kfree(data); 1471 bnxt_abort_tpa(cpr, cp_cons, agg_bufs); 1472 return NULL; 1473 } 1474 skb_reserve(skb, bp->rx_offset); 1475 skb_put(skb, len); 1476 } 1477 1478 if (agg_bufs) { 1479 skb = bnxt_rx_pages(bp, cpr, skb, cp_cons, agg_bufs); 1480 if (!skb) { 1481 /* Page reuse already handled by bnxt_rx_pages(). */ 1482 return NULL; 1483 } 1484 } 1485 1486 skb->protocol = 1487 eth_type_trans(skb, bnxt_get_pkt_dev(bp, tpa_info->cfa_code)); 1488 1489 if (tpa_info->hash_type != PKT_HASH_TYPE_NONE) 1490 skb_set_hash(skb, tpa_info->rss_hash, tpa_info->hash_type); 1491 1492 if ((tpa_info->flags2 & RX_CMP_FLAGS2_META_FORMAT_VLAN) && 1493 (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) { 1494 u16 vlan_proto = tpa_info->metadata >> 1495 RX_CMP_FLAGS2_METADATA_TPID_SFT; 1496 u16 vtag = tpa_info->metadata & RX_CMP_FLAGS2_METADATA_TCI_MASK; 1497 1498 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag); 1499 } 1500 1501 skb_checksum_none_assert(skb); 1502 if (likely(tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_L4_CS_CALC)) { 1503 skb->ip_summed = CHECKSUM_UNNECESSARY; 1504 skb->csum_level = 1505 (tpa_info->flags2 & RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3; 1506 } 1507 1508 if (TPA_END_GRO(tpa_end)) 1509 skb = bnxt_gro_skb(bp, tpa_info, tpa_end, tpa_end1, skb); 1510 1511 return skb; 1512 } 1513 1514 static void bnxt_deliver_skb(struct bnxt *bp, struct bnxt_napi *bnapi, 1515 struct sk_buff *skb) 1516 { 1517 if (skb->dev != bp->dev) { 1518 /* this packet belongs to a vf-rep */ 1519 bnxt_vf_rep_rx(bp, skb); 1520 return; 1521 } 1522 skb_record_rx_queue(skb, bnapi->index); 1523 napi_gro_receive(&bnapi->napi, skb); 1524 } 1525 1526 /* returns the following: 1527 * 1 - 1 packet successfully received 1528 * 0 - successful TPA_START, packet not completed yet 1529 * -EBUSY - completion ring does not have all the agg buffers yet 1530 * -ENOMEM - packet aborted due to out of memory 1531 * -EIO - packet aborted due to hw error indicated in BD 1532 */ 1533 static int bnxt_rx_pkt(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, 1534 u32 *raw_cons, u8 *event) 1535 { 1536 struct bnxt_napi *bnapi = cpr->bnapi; 1537 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 1538 struct net_device *dev = bp->dev; 1539 struct rx_cmp *rxcmp; 1540 struct rx_cmp_ext *rxcmp1; 1541 u32 tmp_raw_cons = *raw_cons; 1542 u16 cfa_code, cons, prod, cp_cons = RING_CMP(tmp_raw_cons); 1543 struct bnxt_sw_rx_bd *rx_buf; 1544 unsigned int len; 1545 u8 *data_ptr, agg_bufs, cmp_type; 1546 dma_addr_t dma_addr; 1547 struct sk_buff *skb; 1548 void *data; 1549 int rc = 0; 1550 u32 misc; 1551 1552 rxcmp = (struct rx_cmp *) 1553 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 1554 1555 tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons); 1556 cp_cons = RING_CMP(tmp_raw_cons); 1557 rxcmp1 = (struct rx_cmp_ext *) 1558 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 1559 1560 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons)) 1561 return -EBUSY; 1562 1563 cmp_type = RX_CMP_TYPE(rxcmp); 1564 1565 prod = rxr->rx_prod; 1566 1567 if (cmp_type == CMP_TYPE_RX_L2_TPA_START_CMP) { 1568 bnxt_tpa_start(bp, rxr, (struct rx_tpa_start_cmp *)rxcmp, 1569 (struct rx_tpa_start_cmp_ext *)rxcmp1); 1570 1571 *event |= BNXT_RX_EVENT; 1572 goto next_rx_no_prod_no_len; 1573 1574 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) { 1575 skb = bnxt_tpa_end(bp, cpr, &tmp_raw_cons, 1576 (struct rx_tpa_end_cmp *)rxcmp, 1577 (struct rx_tpa_end_cmp_ext *)rxcmp1, event); 1578 1579 if (IS_ERR(skb)) 1580 return -EBUSY; 1581 1582 rc = -ENOMEM; 1583 if (likely(skb)) { 1584 bnxt_deliver_skb(bp, bnapi, skb); 1585 rc = 1; 1586 } 1587 *event |= BNXT_RX_EVENT; 1588 goto next_rx_no_prod_no_len; 1589 } 1590 1591 cons = rxcmp->rx_cmp_opaque; 1592 if (unlikely(cons != rxr->rx_next_cons)) { 1593 int rc1 = bnxt_discard_rx(bp, cpr, raw_cons, rxcmp); 1594 1595 netdev_warn(bp->dev, "RX cons %x != expected cons %x\n", 1596 cons, rxr->rx_next_cons); 1597 bnxt_sched_reset(bp, rxr); 1598 return rc1; 1599 } 1600 rx_buf = &rxr->rx_buf_ring[cons]; 1601 data = rx_buf->data; 1602 data_ptr = rx_buf->data_ptr; 1603 prefetch(data_ptr); 1604 1605 misc = le32_to_cpu(rxcmp->rx_cmp_misc_v1); 1606 agg_bufs = (misc & RX_CMP_AGG_BUFS) >> RX_CMP_AGG_BUFS_SHIFT; 1607 1608 if (agg_bufs) { 1609 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons)) 1610 return -EBUSY; 1611 1612 cp_cons = NEXT_CMP(cp_cons); 1613 *event |= BNXT_AGG_EVENT; 1614 } 1615 *event |= BNXT_RX_EVENT; 1616 1617 rx_buf->data = NULL; 1618 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L2_ERRORS) { 1619 u32 rx_err = le32_to_cpu(rxcmp1->rx_cmp_cfa_code_errors_v2); 1620 1621 bnxt_reuse_rx_data(rxr, cons, data); 1622 if (agg_bufs) 1623 bnxt_reuse_rx_agg_bufs(cpr, cp_cons, agg_bufs); 1624 1625 rc = -EIO; 1626 if (rx_err & RX_CMPL_ERRORS_BUFFER_ERROR_MASK) { 1627 netdev_warn(bp->dev, "RX buffer error %x\n", rx_err); 1628 bnxt_sched_reset(bp, rxr); 1629 } 1630 goto next_rx_no_len; 1631 } 1632 1633 len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT; 1634 dma_addr = rx_buf->mapping; 1635 1636 if (bnxt_rx_xdp(bp, rxr, cons, data, &data_ptr, &len, event)) { 1637 rc = 1; 1638 goto next_rx; 1639 } 1640 1641 if (len <= bp->rx_copy_thresh) { 1642 skb = bnxt_copy_skb(bnapi, data_ptr, len, dma_addr); 1643 bnxt_reuse_rx_data(rxr, cons, data); 1644 if (!skb) { 1645 rc = -ENOMEM; 1646 goto next_rx; 1647 } 1648 } else { 1649 u32 payload; 1650 1651 if (rx_buf->data_ptr == data_ptr) 1652 payload = misc & RX_CMP_PAYLOAD_OFFSET; 1653 else 1654 payload = 0; 1655 skb = bp->rx_skb_func(bp, rxr, cons, data, data_ptr, dma_addr, 1656 payload | len); 1657 if (!skb) { 1658 rc = -ENOMEM; 1659 goto next_rx; 1660 } 1661 } 1662 1663 if (agg_bufs) { 1664 skb = bnxt_rx_pages(bp, cpr, skb, cp_cons, agg_bufs); 1665 if (!skb) { 1666 rc = -ENOMEM; 1667 goto next_rx; 1668 } 1669 } 1670 1671 if (RX_CMP_HASH_VALID(rxcmp)) { 1672 u32 hash_type = RX_CMP_HASH_TYPE(rxcmp); 1673 enum pkt_hash_types type = PKT_HASH_TYPE_L4; 1674 1675 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */ 1676 if (hash_type != 1 && hash_type != 3) 1677 type = PKT_HASH_TYPE_L3; 1678 skb_set_hash(skb, le32_to_cpu(rxcmp->rx_cmp_rss_hash), type); 1679 } 1680 1681 cfa_code = RX_CMP_CFA_CODE(rxcmp1); 1682 skb->protocol = eth_type_trans(skb, bnxt_get_pkt_dev(bp, cfa_code)); 1683 1684 if ((rxcmp1->rx_cmp_flags2 & 1685 cpu_to_le32(RX_CMP_FLAGS2_META_FORMAT_VLAN)) && 1686 (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) { 1687 u32 meta_data = le32_to_cpu(rxcmp1->rx_cmp_meta_data); 1688 u16 vtag = meta_data & RX_CMP_FLAGS2_METADATA_TCI_MASK; 1689 u16 vlan_proto = meta_data >> RX_CMP_FLAGS2_METADATA_TPID_SFT; 1690 1691 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag); 1692 } 1693 1694 skb_checksum_none_assert(skb); 1695 if (RX_CMP_L4_CS_OK(rxcmp1)) { 1696 if (dev->features & NETIF_F_RXCSUM) { 1697 skb->ip_summed = CHECKSUM_UNNECESSARY; 1698 skb->csum_level = RX_CMP_ENCAP(rxcmp1); 1699 } 1700 } else { 1701 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS) { 1702 if (dev->features & NETIF_F_RXCSUM) 1703 bnapi->cp_ring.rx_l4_csum_errors++; 1704 } 1705 } 1706 1707 bnxt_deliver_skb(bp, bnapi, skb); 1708 rc = 1; 1709 1710 next_rx: 1711 cpr->rx_packets += 1; 1712 cpr->rx_bytes += len; 1713 1714 next_rx_no_len: 1715 rxr->rx_prod = NEXT_RX(prod); 1716 rxr->rx_next_cons = NEXT_RX(cons); 1717 1718 next_rx_no_prod_no_len: 1719 *raw_cons = tmp_raw_cons; 1720 1721 return rc; 1722 } 1723 1724 /* In netpoll mode, if we are using a combined completion ring, we need to 1725 * discard the rx packets and recycle the buffers. 1726 */ 1727 static int bnxt_force_rx_discard(struct bnxt *bp, 1728 struct bnxt_cp_ring_info *cpr, 1729 u32 *raw_cons, u8 *event) 1730 { 1731 u32 tmp_raw_cons = *raw_cons; 1732 struct rx_cmp_ext *rxcmp1; 1733 struct rx_cmp *rxcmp; 1734 u16 cp_cons; 1735 u8 cmp_type; 1736 1737 cp_cons = RING_CMP(tmp_raw_cons); 1738 rxcmp = (struct rx_cmp *) 1739 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 1740 1741 tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons); 1742 cp_cons = RING_CMP(tmp_raw_cons); 1743 rxcmp1 = (struct rx_cmp_ext *) 1744 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 1745 1746 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons)) 1747 return -EBUSY; 1748 1749 cmp_type = RX_CMP_TYPE(rxcmp); 1750 if (cmp_type == CMP_TYPE_RX_L2_CMP) { 1751 rxcmp1->rx_cmp_cfa_code_errors_v2 |= 1752 cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR); 1753 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) { 1754 struct rx_tpa_end_cmp_ext *tpa_end1; 1755 1756 tpa_end1 = (struct rx_tpa_end_cmp_ext *)rxcmp1; 1757 tpa_end1->rx_tpa_end_cmp_errors_v2 |= 1758 cpu_to_le32(RX_TPA_END_CMP_ERRORS); 1759 } 1760 return bnxt_rx_pkt(bp, cpr, raw_cons, event); 1761 } 1762 1763 #define BNXT_GET_EVENT_PORT(data) \ 1764 ((data) & \ 1765 ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK) 1766 1767 static int bnxt_async_event_process(struct bnxt *bp, 1768 struct hwrm_async_event_cmpl *cmpl) 1769 { 1770 u16 event_id = le16_to_cpu(cmpl->event_id); 1771 1772 /* TODO CHIMP_FW: Define event id's for link change, error etc */ 1773 switch (event_id) { 1774 case ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE: { 1775 u32 data1 = le32_to_cpu(cmpl->event_data1); 1776 struct bnxt_link_info *link_info = &bp->link_info; 1777 1778 if (BNXT_VF(bp)) 1779 goto async_event_process_exit; 1780 1781 /* print unsupported speed warning in forced speed mode only */ 1782 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED) && 1783 (data1 & 0x20000)) { 1784 u16 fw_speed = link_info->force_link_speed; 1785 u32 speed = bnxt_fw_to_ethtool_speed(fw_speed); 1786 1787 if (speed != SPEED_UNKNOWN) 1788 netdev_warn(bp->dev, "Link speed %d no longer supported\n", 1789 speed); 1790 } 1791 set_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT, &bp->sp_event); 1792 } 1793 /* fall through */ 1794 case ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE: 1795 set_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event); 1796 break; 1797 case ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD: 1798 set_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event); 1799 break; 1800 case ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED: { 1801 u32 data1 = le32_to_cpu(cmpl->event_data1); 1802 u16 port_id = BNXT_GET_EVENT_PORT(data1); 1803 1804 if (BNXT_VF(bp)) 1805 break; 1806 1807 if (bp->pf.port_id != port_id) 1808 break; 1809 1810 set_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event); 1811 break; 1812 } 1813 case ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE: 1814 if (BNXT_PF(bp)) 1815 goto async_event_process_exit; 1816 set_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event); 1817 break; 1818 default: 1819 goto async_event_process_exit; 1820 } 1821 bnxt_queue_sp_work(bp); 1822 async_event_process_exit: 1823 bnxt_ulp_async_events(bp, cmpl); 1824 return 0; 1825 } 1826 1827 static int bnxt_hwrm_handler(struct bnxt *bp, struct tx_cmp *txcmp) 1828 { 1829 u16 cmpl_type = TX_CMP_TYPE(txcmp), vf_id, seq_id; 1830 struct hwrm_cmpl *h_cmpl = (struct hwrm_cmpl *)txcmp; 1831 struct hwrm_fwd_req_cmpl *fwd_req_cmpl = 1832 (struct hwrm_fwd_req_cmpl *)txcmp; 1833 1834 switch (cmpl_type) { 1835 case CMPL_BASE_TYPE_HWRM_DONE: 1836 seq_id = le16_to_cpu(h_cmpl->sequence_id); 1837 if (seq_id == bp->hwrm_intr_seq_id) 1838 bp->hwrm_intr_seq_id = (u16)~bp->hwrm_intr_seq_id; 1839 else 1840 netdev_err(bp->dev, "Invalid hwrm seq id %d\n", seq_id); 1841 break; 1842 1843 case CMPL_BASE_TYPE_HWRM_FWD_REQ: 1844 vf_id = le16_to_cpu(fwd_req_cmpl->source_id); 1845 1846 if ((vf_id < bp->pf.first_vf_id) || 1847 (vf_id >= bp->pf.first_vf_id + bp->pf.active_vfs)) { 1848 netdev_err(bp->dev, "Msg contains invalid VF id %x\n", 1849 vf_id); 1850 return -EINVAL; 1851 } 1852 1853 set_bit(vf_id - bp->pf.first_vf_id, bp->pf.vf_event_bmap); 1854 set_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event); 1855 bnxt_queue_sp_work(bp); 1856 break; 1857 1858 case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT: 1859 bnxt_async_event_process(bp, 1860 (struct hwrm_async_event_cmpl *)txcmp); 1861 1862 default: 1863 break; 1864 } 1865 1866 return 0; 1867 } 1868 1869 static irqreturn_t bnxt_msix(int irq, void *dev_instance) 1870 { 1871 struct bnxt_napi *bnapi = dev_instance; 1872 struct bnxt *bp = bnapi->bp; 1873 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 1874 u32 cons = RING_CMP(cpr->cp_raw_cons); 1875 1876 cpr->event_ctr++; 1877 prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]); 1878 napi_schedule(&bnapi->napi); 1879 return IRQ_HANDLED; 1880 } 1881 1882 static inline int bnxt_has_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr) 1883 { 1884 u32 raw_cons = cpr->cp_raw_cons; 1885 u16 cons = RING_CMP(raw_cons); 1886 struct tx_cmp *txcmp; 1887 1888 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]; 1889 1890 return TX_CMP_VALID(txcmp, raw_cons); 1891 } 1892 1893 static irqreturn_t bnxt_inta(int irq, void *dev_instance) 1894 { 1895 struct bnxt_napi *bnapi = dev_instance; 1896 struct bnxt *bp = bnapi->bp; 1897 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 1898 u32 cons = RING_CMP(cpr->cp_raw_cons); 1899 u32 int_status; 1900 1901 prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]); 1902 1903 if (!bnxt_has_work(bp, cpr)) { 1904 int_status = readl(bp->bar0 + BNXT_CAG_REG_LEGACY_INT_STATUS); 1905 /* return if erroneous interrupt */ 1906 if (!(int_status & (0x10000 << cpr->cp_ring_struct.fw_ring_id))) 1907 return IRQ_NONE; 1908 } 1909 1910 /* disable ring IRQ */ 1911 BNXT_CP_DB_IRQ_DIS(cpr->cp_db.doorbell); 1912 1913 /* Return here if interrupt is shared and is disabled. */ 1914 if (unlikely(atomic_read(&bp->intr_sem) != 0)) 1915 return IRQ_HANDLED; 1916 1917 napi_schedule(&bnapi->napi); 1918 return IRQ_HANDLED; 1919 } 1920 1921 static int __bnxt_poll_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, 1922 int budget) 1923 { 1924 struct bnxt_napi *bnapi = cpr->bnapi; 1925 u32 raw_cons = cpr->cp_raw_cons; 1926 u32 cons; 1927 int tx_pkts = 0; 1928 int rx_pkts = 0; 1929 u8 event = 0; 1930 struct tx_cmp *txcmp; 1931 1932 cpr->has_more_work = 0; 1933 while (1) { 1934 int rc; 1935 1936 cons = RING_CMP(raw_cons); 1937 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]; 1938 1939 if (!TX_CMP_VALID(txcmp, raw_cons)) 1940 break; 1941 1942 /* The valid test of the entry must be done first before 1943 * reading any further. 1944 */ 1945 dma_rmb(); 1946 cpr->had_work_done = 1; 1947 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_TX_L2_CMP) { 1948 tx_pkts++; 1949 /* return full budget so NAPI will complete. */ 1950 if (unlikely(tx_pkts > bp->tx_wake_thresh)) { 1951 rx_pkts = budget; 1952 raw_cons = NEXT_RAW_CMP(raw_cons); 1953 if (budget) 1954 cpr->has_more_work = 1; 1955 break; 1956 } 1957 } else if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) { 1958 if (likely(budget)) 1959 rc = bnxt_rx_pkt(bp, cpr, &raw_cons, &event); 1960 else 1961 rc = bnxt_force_rx_discard(bp, cpr, &raw_cons, 1962 &event); 1963 if (likely(rc >= 0)) 1964 rx_pkts += rc; 1965 /* Increment rx_pkts when rc is -ENOMEM to count towards 1966 * the NAPI budget. Otherwise, we may potentially loop 1967 * here forever if we consistently cannot allocate 1968 * buffers. 1969 */ 1970 else if (rc == -ENOMEM && budget) 1971 rx_pkts++; 1972 else if (rc == -EBUSY) /* partial completion */ 1973 break; 1974 } else if (unlikely((TX_CMP_TYPE(txcmp) == 1975 CMPL_BASE_TYPE_HWRM_DONE) || 1976 (TX_CMP_TYPE(txcmp) == 1977 CMPL_BASE_TYPE_HWRM_FWD_REQ) || 1978 (TX_CMP_TYPE(txcmp) == 1979 CMPL_BASE_TYPE_HWRM_ASYNC_EVENT))) { 1980 bnxt_hwrm_handler(bp, txcmp); 1981 } 1982 raw_cons = NEXT_RAW_CMP(raw_cons); 1983 1984 if (rx_pkts && rx_pkts == budget) { 1985 cpr->has_more_work = 1; 1986 break; 1987 } 1988 } 1989 1990 if (event & BNXT_TX_EVENT) { 1991 struct bnxt_tx_ring_info *txr = bnapi->tx_ring; 1992 u16 prod = txr->tx_prod; 1993 1994 /* Sync BD data before updating doorbell */ 1995 wmb(); 1996 1997 bnxt_db_write_relaxed(bp, &txr->tx_db, prod); 1998 } 1999 2000 cpr->cp_raw_cons = raw_cons; 2001 bnapi->tx_pkts += tx_pkts; 2002 bnapi->events |= event; 2003 return rx_pkts; 2004 } 2005 2006 static void __bnxt_poll_work_done(struct bnxt *bp, struct bnxt_napi *bnapi) 2007 { 2008 if (bnapi->tx_pkts) { 2009 bnapi->tx_int(bp, bnapi, bnapi->tx_pkts); 2010 bnapi->tx_pkts = 0; 2011 } 2012 2013 if (bnapi->events & BNXT_RX_EVENT) { 2014 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 2015 2016 bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod); 2017 if (bnapi->events & BNXT_AGG_EVENT) 2018 bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod); 2019 } 2020 bnapi->events = 0; 2021 } 2022 2023 static int bnxt_poll_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, 2024 int budget) 2025 { 2026 struct bnxt_napi *bnapi = cpr->bnapi; 2027 int rx_pkts; 2028 2029 rx_pkts = __bnxt_poll_work(bp, cpr, budget); 2030 2031 /* ACK completion ring before freeing tx ring and producing new 2032 * buffers in rx/agg rings to prevent overflowing the completion 2033 * ring. 2034 */ 2035 bnxt_db_cq(bp, &cpr->cp_db, cpr->cp_raw_cons); 2036 2037 __bnxt_poll_work_done(bp, bnapi); 2038 return rx_pkts; 2039 } 2040 2041 static int bnxt_poll_nitroa0(struct napi_struct *napi, int budget) 2042 { 2043 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi); 2044 struct bnxt *bp = bnapi->bp; 2045 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 2046 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 2047 struct tx_cmp *txcmp; 2048 struct rx_cmp_ext *rxcmp1; 2049 u32 cp_cons, tmp_raw_cons; 2050 u32 raw_cons = cpr->cp_raw_cons; 2051 u32 rx_pkts = 0; 2052 u8 event = 0; 2053 2054 while (1) { 2055 int rc; 2056 2057 cp_cons = RING_CMP(raw_cons); 2058 txcmp = &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 2059 2060 if (!TX_CMP_VALID(txcmp, raw_cons)) 2061 break; 2062 2063 if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) { 2064 tmp_raw_cons = NEXT_RAW_CMP(raw_cons); 2065 cp_cons = RING_CMP(tmp_raw_cons); 2066 rxcmp1 = (struct rx_cmp_ext *) 2067 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 2068 2069 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons)) 2070 break; 2071 2072 /* force an error to recycle the buffer */ 2073 rxcmp1->rx_cmp_cfa_code_errors_v2 |= 2074 cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR); 2075 2076 rc = bnxt_rx_pkt(bp, cpr, &raw_cons, &event); 2077 if (likely(rc == -EIO) && budget) 2078 rx_pkts++; 2079 else if (rc == -EBUSY) /* partial completion */ 2080 break; 2081 } else if (unlikely(TX_CMP_TYPE(txcmp) == 2082 CMPL_BASE_TYPE_HWRM_DONE)) { 2083 bnxt_hwrm_handler(bp, txcmp); 2084 } else { 2085 netdev_err(bp->dev, 2086 "Invalid completion received on special ring\n"); 2087 } 2088 raw_cons = NEXT_RAW_CMP(raw_cons); 2089 2090 if (rx_pkts == budget) 2091 break; 2092 } 2093 2094 cpr->cp_raw_cons = raw_cons; 2095 BNXT_DB_CQ(&cpr->cp_db, cpr->cp_raw_cons); 2096 bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod); 2097 2098 if (event & BNXT_AGG_EVENT) 2099 bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod); 2100 2101 if (!bnxt_has_work(bp, cpr) && rx_pkts < budget) { 2102 napi_complete_done(napi, rx_pkts); 2103 BNXT_DB_CQ_ARM(&cpr->cp_db, cpr->cp_raw_cons); 2104 } 2105 return rx_pkts; 2106 } 2107 2108 static int bnxt_poll(struct napi_struct *napi, int budget) 2109 { 2110 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi); 2111 struct bnxt *bp = bnapi->bp; 2112 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 2113 int work_done = 0; 2114 2115 while (1) { 2116 work_done += bnxt_poll_work(bp, cpr, budget - work_done); 2117 2118 if (work_done >= budget) { 2119 if (!budget) 2120 BNXT_DB_CQ_ARM(&cpr->cp_db, cpr->cp_raw_cons); 2121 break; 2122 } 2123 2124 if (!bnxt_has_work(bp, cpr)) { 2125 if (napi_complete_done(napi, work_done)) 2126 BNXT_DB_CQ_ARM(&cpr->cp_db, cpr->cp_raw_cons); 2127 break; 2128 } 2129 } 2130 if (bp->flags & BNXT_FLAG_DIM) { 2131 struct net_dim_sample dim_sample; 2132 2133 net_dim_sample(cpr->event_ctr, 2134 cpr->rx_packets, 2135 cpr->rx_bytes, 2136 &dim_sample); 2137 net_dim(&cpr->dim, dim_sample); 2138 } 2139 return work_done; 2140 } 2141 2142 static int __bnxt_poll_cqs(struct bnxt *bp, struct bnxt_napi *bnapi, int budget) 2143 { 2144 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 2145 int i, work_done = 0; 2146 2147 for (i = 0; i < 2; i++) { 2148 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[i]; 2149 2150 if (cpr2) { 2151 work_done += __bnxt_poll_work(bp, cpr2, 2152 budget - work_done); 2153 cpr->has_more_work |= cpr2->has_more_work; 2154 } 2155 } 2156 return work_done; 2157 } 2158 2159 static void __bnxt_poll_cqs_done(struct bnxt *bp, struct bnxt_napi *bnapi, 2160 u64 dbr_type, bool all) 2161 { 2162 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 2163 int i; 2164 2165 for (i = 0; i < 2; i++) { 2166 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[i]; 2167 struct bnxt_db_info *db; 2168 2169 if (cpr2 && (all || cpr2->had_work_done)) { 2170 db = &cpr2->cp_db; 2171 writeq(db->db_key64 | dbr_type | 2172 RING_CMP(cpr2->cp_raw_cons), db->doorbell); 2173 cpr2->had_work_done = 0; 2174 } 2175 } 2176 __bnxt_poll_work_done(bp, bnapi); 2177 } 2178 2179 static int bnxt_poll_p5(struct napi_struct *napi, int budget) 2180 { 2181 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi); 2182 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 2183 u32 raw_cons = cpr->cp_raw_cons; 2184 struct bnxt *bp = bnapi->bp; 2185 struct nqe_cn *nqcmp; 2186 int work_done = 0; 2187 u32 cons; 2188 2189 if (cpr->has_more_work) { 2190 cpr->has_more_work = 0; 2191 work_done = __bnxt_poll_cqs(bp, bnapi, budget); 2192 if (cpr->has_more_work) { 2193 __bnxt_poll_cqs_done(bp, bnapi, DBR_TYPE_CQ, false); 2194 return work_done; 2195 } 2196 __bnxt_poll_cqs_done(bp, bnapi, DBR_TYPE_CQ_ARMALL, true); 2197 if (napi_complete_done(napi, work_done)) 2198 BNXT_DB_NQ_ARM_P5(&cpr->cp_db, cpr->cp_raw_cons); 2199 return work_done; 2200 } 2201 while (1) { 2202 cons = RING_CMP(raw_cons); 2203 nqcmp = &cpr->nq_desc_ring[CP_RING(cons)][CP_IDX(cons)]; 2204 2205 if (!NQ_CMP_VALID(nqcmp, raw_cons)) { 2206 __bnxt_poll_cqs_done(bp, bnapi, DBR_TYPE_CQ_ARMALL, 2207 false); 2208 cpr->cp_raw_cons = raw_cons; 2209 if (napi_complete_done(napi, work_done)) 2210 BNXT_DB_NQ_ARM_P5(&cpr->cp_db, 2211 cpr->cp_raw_cons); 2212 return work_done; 2213 } 2214 2215 /* The valid test of the entry must be done first before 2216 * reading any further. 2217 */ 2218 dma_rmb(); 2219 2220 if (nqcmp->type == cpu_to_le16(NQ_CN_TYPE_CQ_NOTIFICATION)) { 2221 u32 idx = le32_to_cpu(nqcmp->cq_handle_low); 2222 struct bnxt_cp_ring_info *cpr2; 2223 2224 cpr2 = cpr->cp_ring_arr[idx]; 2225 work_done += __bnxt_poll_work(bp, cpr2, 2226 budget - work_done); 2227 cpr->has_more_work = cpr2->has_more_work; 2228 } else { 2229 bnxt_hwrm_handler(bp, (struct tx_cmp *)nqcmp); 2230 } 2231 raw_cons = NEXT_RAW_CMP(raw_cons); 2232 if (cpr->has_more_work) 2233 break; 2234 } 2235 __bnxt_poll_cqs_done(bp, bnapi, DBR_TYPE_CQ, true); 2236 cpr->cp_raw_cons = raw_cons; 2237 return work_done; 2238 } 2239 2240 static void bnxt_free_tx_skbs(struct bnxt *bp) 2241 { 2242 int i, max_idx; 2243 struct pci_dev *pdev = bp->pdev; 2244 2245 if (!bp->tx_ring) 2246 return; 2247 2248 max_idx = bp->tx_nr_pages * TX_DESC_CNT; 2249 for (i = 0; i < bp->tx_nr_rings; i++) { 2250 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; 2251 int j; 2252 2253 for (j = 0; j < max_idx;) { 2254 struct bnxt_sw_tx_bd *tx_buf = &txr->tx_buf_ring[j]; 2255 struct sk_buff *skb = tx_buf->skb; 2256 int k, last; 2257 2258 if (!skb) { 2259 j++; 2260 continue; 2261 } 2262 2263 tx_buf->skb = NULL; 2264 2265 if (tx_buf->is_push) { 2266 dev_kfree_skb(skb); 2267 j += 2; 2268 continue; 2269 } 2270 2271 dma_unmap_single(&pdev->dev, 2272 dma_unmap_addr(tx_buf, mapping), 2273 skb_headlen(skb), 2274 PCI_DMA_TODEVICE); 2275 2276 last = tx_buf->nr_frags; 2277 j += 2; 2278 for (k = 0; k < last; k++, j++) { 2279 int ring_idx = j & bp->tx_ring_mask; 2280 skb_frag_t *frag = &skb_shinfo(skb)->frags[k]; 2281 2282 tx_buf = &txr->tx_buf_ring[ring_idx]; 2283 dma_unmap_page( 2284 &pdev->dev, 2285 dma_unmap_addr(tx_buf, mapping), 2286 skb_frag_size(frag), PCI_DMA_TODEVICE); 2287 } 2288 dev_kfree_skb(skb); 2289 } 2290 netdev_tx_reset_queue(netdev_get_tx_queue(bp->dev, i)); 2291 } 2292 } 2293 2294 static void bnxt_free_rx_skbs(struct bnxt *bp) 2295 { 2296 int i, max_idx, max_agg_idx; 2297 struct pci_dev *pdev = bp->pdev; 2298 2299 if (!bp->rx_ring) 2300 return; 2301 2302 max_idx = bp->rx_nr_pages * RX_DESC_CNT; 2303 max_agg_idx = bp->rx_agg_nr_pages * RX_DESC_CNT; 2304 for (i = 0; i < bp->rx_nr_rings; i++) { 2305 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 2306 int j; 2307 2308 if (rxr->rx_tpa) { 2309 for (j = 0; j < MAX_TPA; j++) { 2310 struct bnxt_tpa_info *tpa_info = 2311 &rxr->rx_tpa[j]; 2312 u8 *data = tpa_info->data; 2313 2314 if (!data) 2315 continue; 2316 2317 dma_unmap_single_attrs(&pdev->dev, 2318 tpa_info->mapping, 2319 bp->rx_buf_use_size, 2320 bp->rx_dir, 2321 DMA_ATTR_WEAK_ORDERING); 2322 2323 tpa_info->data = NULL; 2324 2325 kfree(data); 2326 } 2327 } 2328 2329 for (j = 0; j < max_idx; j++) { 2330 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[j]; 2331 dma_addr_t mapping = rx_buf->mapping; 2332 void *data = rx_buf->data; 2333 2334 if (!data) 2335 continue; 2336 2337 rx_buf->data = NULL; 2338 2339 if (BNXT_RX_PAGE_MODE(bp)) { 2340 mapping -= bp->rx_dma_offset; 2341 dma_unmap_page_attrs(&pdev->dev, mapping, 2342 PAGE_SIZE, bp->rx_dir, 2343 DMA_ATTR_WEAK_ORDERING); 2344 __free_page(data); 2345 } else { 2346 dma_unmap_single_attrs(&pdev->dev, mapping, 2347 bp->rx_buf_use_size, 2348 bp->rx_dir, 2349 DMA_ATTR_WEAK_ORDERING); 2350 kfree(data); 2351 } 2352 } 2353 2354 for (j = 0; j < max_agg_idx; j++) { 2355 struct bnxt_sw_rx_agg_bd *rx_agg_buf = 2356 &rxr->rx_agg_ring[j]; 2357 struct page *page = rx_agg_buf->page; 2358 2359 if (!page) 2360 continue; 2361 2362 dma_unmap_page_attrs(&pdev->dev, rx_agg_buf->mapping, 2363 BNXT_RX_PAGE_SIZE, 2364 PCI_DMA_FROMDEVICE, 2365 DMA_ATTR_WEAK_ORDERING); 2366 2367 rx_agg_buf->page = NULL; 2368 __clear_bit(j, rxr->rx_agg_bmap); 2369 2370 __free_page(page); 2371 } 2372 if (rxr->rx_page) { 2373 __free_page(rxr->rx_page); 2374 rxr->rx_page = NULL; 2375 } 2376 } 2377 } 2378 2379 static void bnxt_free_skbs(struct bnxt *bp) 2380 { 2381 bnxt_free_tx_skbs(bp); 2382 bnxt_free_rx_skbs(bp); 2383 } 2384 2385 static void bnxt_free_ring(struct bnxt *bp, struct bnxt_ring_mem_info *rmem) 2386 { 2387 struct pci_dev *pdev = bp->pdev; 2388 int i; 2389 2390 for (i = 0; i < rmem->nr_pages; i++) { 2391 if (!rmem->pg_arr[i]) 2392 continue; 2393 2394 dma_free_coherent(&pdev->dev, rmem->page_size, 2395 rmem->pg_arr[i], rmem->dma_arr[i]); 2396 2397 rmem->pg_arr[i] = NULL; 2398 } 2399 if (rmem->pg_tbl) { 2400 size_t pg_tbl_size = rmem->nr_pages * 8; 2401 2402 if (rmem->flags & BNXT_RMEM_USE_FULL_PAGE_FLAG) 2403 pg_tbl_size = rmem->page_size; 2404 dma_free_coherent(&pdev->dev, pg_tbl_size, 2405 rmem->pg_tbl, rmem->pg_tbl_map); 2406 rmem->pg_tbl = NULL; 2407 } 2408 if (rmem->vmem_size && *rmem->vmem) { 2409 vfree(*rmem->vmem); 2410 *rmem->vmem = NULL; 2411 } 2412 } 2413 2414 static int bnxt_alloc_ring(struct bnxt *bp, struct bnxt_ring_mem_info *rmem) 2415 { 2416 struct pci_dev *pdev = bp->pdev; 2417 u64 valid_bit = 0; 2418 int i; 2419 2420 if (rmem->flags & (BNXT_RMEM_VALID_PTE_FLAG | BNXT_RMEM_RING_PTE_FLAG)) 2421 valid_bit = PTU_PTE_VALID; 2422 if ((rmem->nr_pages > 1 || rmem->depth > 0) && !rmem->pg_tbl) { 2423 size_t pg_tbl_size = rmem->nr_pages * 8; 2424 2425 if (rmem->flags & BNXT_RMEM_USE_FULL_PAGE_FLAG) 2426 pg_tbl_size = rmem->page_size; 2427 rmem->pg_tbl = dma_alloc_coherent(&pdev->dev, pg_tbl_size, 2428 &rmem->pg_tbl_map, 2429 GFP_KERNEL); 2430 if (!rmem->pg_tbl) 2431 return -ENOMEM; 2432 } 2433 2434 for (i = 0; i < rmem->nr_pages; i++) { 2435 u64 extra_bits = valid_bit; 2436 2437 rmem->pg_arr[i] = dma_alloc_coherent(&pdev->dev, 2438 rmem->page_size, 2439 &rmem->dma_arr[i], 2440 GFP_KERNEL); 2441 if (!rmem->pg_arr[i]) 2442 return -ENOMEM; 2443 2444 if (rmem->nr_pages > 1 || rmem->depth > 0) { 2445 if (i == rmem->nr_pages - 2 && 2446 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG)) 2447 extra_bits |= PTU_PTE_NEXT_TO_LAST; 2448 else if (i == rmem->nr_pages - 1 && 2449 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG)) 2450 extra_bits |= PTU_PTE_LAST; 2451 rmem->pg_tbl[i] = 2452 cpu_to_le64(rmem->dma_arr[i] | extra_bits); 2453 } 2454 } 2455 2456 if (rmem->vmem_size) { 2457 *rmem->vmem = vzalloc(rmem->vmem_size); 2458 if (!(*rmem->vmem)) 2459 return -ENOMEM; 2460 } 2461 return 0; 2462 } 2463 2464 static void bnxt_free_rx_rings(struct bnxt *bp) 2465 { 2466 int i; 2467 2468 if (!bp->rx_ring) 2469 return; 2470 2471 for (i = 0; i < bp->rx_nr_rings; i++) { 2472 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 2473 struct bnxt_ring_struct *ring; 2474 2475 if (rxr->xdp_prog) 2476 bpf_prog_put(rxr->xdp_prog); 2477 2478 if (xdp_rxq_info_is_reg(&rxr->xdp_rxq)) 2479 xdp_rxq_info_unreg(&rxr->xdp_rxq); 2480 2481 kfree(rxr->rx_tpa); 2482 rxr->rx_tpa = NULL; 2483 2484 kfree(rxr->rx_agg_bmap); 2485 rxr->rx_agg_bmap = NULL; 2486 2487 ring = &rxr->rx_ring_struct; 2488 bnxt_free_ring(bp, &ring->ring_mem); 2489 2490 ring = &rxr->rx_agg_ring_struct; 2491 bnxt_free_ring(bp, &ring->ring_mem); 2492 } 2493 } 2494 2495 static int bnxt_alloc_rx_rings(struct bnxt *bp) 2496 { 2497 int i, rc, agg_rings = 0, tpa_rings = 0; 2498 2499 if (!bp->rx_ring) 2500 return -ENOMEM; 2501 2502 if (bp->flags & BNXT_FLAG_AGG_RINGS) 2503 agg_rings = 1; 2504 2505 if (bp->flags & BNXT_FLAG_TPA) 2506 tpa_rings = 1; 2507 2508 for (i = 0; i < bp->rx_nr_rings; i++) { 2509 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 2510 struct bnxt_ring_struct *ring; 2511 2512 ring = &rxr->rx_ring_struct; 2513 2514 rc = xdp_rxq_info_reg(&rxr->xdp_rxq, bp->dev, i); 2515 if (rc < 0) 2516 return rc; 2517 2518 rc = bnxt_alloc_ring(bp, &ring->ring_mem); 2519 if (rc) 2520 return rc; 2521 2522 ring->grp_idx = i; 2523 if (agg_rings) { 2524 u16 mem_size; 2525 2526 ring = &rxr->rx_agg_ring_struct; 2527 rc = bnxt_alloc_ring(bp, &ring->ring_mem); 2528 if (rc) 2529 return rc; 2530 2531 ring->grp_idx = i; 2532 rxr->rx_agg_bmap_size = bp->rx_agg_ring_mask + 1; 2533 mem_size = rxr->rx_agg_bmap_size / 8; 2534 rxr->rx_agg_bmap = kzalloc(mem_size, GFP_KERNEL); 2535 if (!rxr->rx_agg_bmap) 2536 return -ENOMEM; 2537 2538 if (tpa_rings) { 2539 rxr->rx_tpa = kcalloc(MAX_TPA, 2540 sizeof(struct bnxt_tpa_info), 2541 GFP_KERNEL); 2542 if (!rxr->rx_tpa) 2543 return -ENOMEM; 2544 } 2545 } 2546 } 2547 return 0; 2548 } 2549 2550 static void bnxt_free_tx_rings(struct bnxt *bp) 2551 { 2552 int i; 2553 struct pci_dev *pdev = bp->pdev; 2554 2555 if (!bp->tx_ring) 2556 return; 2557 2558 for (i = 0; i < bp->tx_nr_rings; i++) { 2559 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; 2560 struct bnxt_ring_struct *ring; 2561 2562 if (txr->tx_push) { 2563 dma_free_coherent(&pdev->dev, bp->tx_push_size, 2564 txr->tx_push, txr->tx_push_mapping); 2565 txr->tx_push = NULL; 2566 } 2567 2568 ring = &txr->tx_ring_struct; 2569 2570 bnxt_free_ring(bp, &ring->ring_mem); 2571 } 2572 } 2573 2574 static int bnxt_alloc_tx_rings(struct bnxt *bp) 2575 { 2576 int i, j, rc; 2577 struct pci_dev *pdev = bp->pdev; 2578 2579 bp->tx_push_size = 0; 2580 if (bp->tx_push_thresh) { 2581 int push_size; 2582 2583 push_size = L1_CACHE_ALIGN(sizeof(struct tx_push_bd) + 2584 bp->tx_push_thresh); 2585 2586 if (push_size > 256) { 2587 push_size = 0; 2588 bp->tx_push_thresh = 0; 2589 } 2590 2591 bp->tx_push_size = push_size; 2592 } 2593 2594 for (i = 0, j = 0; i < bp->tx_nr_rings; i++) { 2595 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; 2596 struct bnxt_ring_struct *ring; 2597 u8 qidx; 2598 2599 ring = &txr->tx_ring_struct; 2600 2601 rc = bnxt_alloc_ring(bp, &ring->ring_mem); 2602 if (rc) 2603 return rc; 2604 2605 ring->grp_idx = txr->bnapi->index; 2606 if (bp->tx_push_size) { 2607 dma_addr_t mapping; 2608 2609 /* One pre-allocated DMA buffer to backup 2610 * TX push operation 2611 */ 2612 txr->tx_push = dma_alloc_coherent(&pdev->dev, 2613 bp->tx_push_size, 2614 &txr->tx_push_mapping, 2615 GFP_KERNEL); 2616 2617 if (!txr->tx_push) 2618 return -ENOMEM; 2619 2620 mapping = txr->tx_push_mapping + 2621 sizeof(struct tx_push_bd); 2622 txr->data_mapping = cpu_to_le64(mapping); 2623 2624 memset(txr->tx_push, 0, sizeof(struct tx_push_bd)); 2625 } 2626 qidx = bp->tc_to_qidx[j]; 2627 ring->queue_id = bp->q_info[qidx].queue_id; 2628 if (i < bp->tx_nr_rings_xdp) 2629 continue; 2630 if (i % bp->tx_nr_rings_per_tc == (bp->tx_nr_rings_per_tc - 1)) 2631 j++; 2632 } 2633 return 0; 2634 } 2635 2636 static void bnxt_free_cp_rings(struct bnxt *bp) 2637 { 2638 int i; 2639 2640 if (!bp->bnapi) 2641 return; 2642 2643 for (i = 0; i < bp->cp_nr_rings; i++) { 2644 struct bnxt_napi *bnapi = bp->bnapi[i]; 2645 struct bnxt_cp_ring_info *cpr; 2646 struct bnxt_ring_struct *ring; 2647 int j; 2648 2649 if (!bnapi) 2650 continue; 2651 2652 cpr = &bnapi->cp_ring; 2653 ring = &cpr->cp_ring_struct; 2654 2655 bnxt_free_ring(bp, &ring->ring_mem); 2656 2657 for (j = 0; j < 2; j++) { 2658 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j]; 2659 2660 if (cpr2) { 2661 ring = &cpr2->cp_ring_struct; 2662 bnxt_free_ring(bp, &ring->ring_mem); 2663 kfree(cpr2); 2664 cpr->cp_ring_arr[j] = NULL; 2665 } 2666 } 2667 } 2668 } 2669 2670 static struct bnxt_cp_ring_info *bnxt_alloc_cp_sub_ring(struct bnxt *bp) 2671 { 2672 struct bnxt_ring_mem_info *rmem; 2673 struct bnxt_ring_struct *ring; 2674 struct bnxt_cp_ring_info *cpr; 2675 int rc; 2676 2677 cpr = kzalloc(sizeof(*cpr), GFP_KERNEL); 2678 if (!cpr) 2679 return NULL; 2680 2681 ring = &cpr->cp_ring_struct; 2682 rmem = &ring->ring_mem; 2683 rmem->nr_pages = bp->cp_nr_pages; 2684 rmem->page_size = HW_CMPD_RING_SIZE; 2685 rmem->pg_arr = (void **)cpr->cp_desc_ring; 2686 rmem->dma_arr = cpr->cp_desc_mapping; 2687 rmem->flags = BNXT_RMEM_RING_PTE_FLAG; 2688 rc = bnxt_alloc_ring(bp, rmem); 2689 if (rc) { 2690 bnxt_free_ring(bp, rmem); 2691 kfree(cpr); 2692 cpr = NULL; 2693 } 2694 return cpr; 2695 } 2696 2697 static int bnxt_alloc_cp_rings(struct bnxt *bp) 2698 { 2699 bool sh = !!(bp->flags & BNXT_FLAG_SHARED_RINGS); 2700 int i, rc, ulp_base_vec, ulp_msix; 2701 2702 ulp_msix = bnxt_get_ulp_msix_num(bp); 2703 ulp_base_vec = bnxt_get_ulp_msix_base(bp); 2704 for (i = 0; i < bp->cp_nr_rings; i++) { 2705 struct bnxt_napi *bnapi = bp->bnapi[i]; 2706 struct bnxt_cp_ring_info *cpr; 2707 struct bnxt_ring_struct *ring; 2708 2709 if (!bnapi) 2710 continue; 2711 2712 cpr = &bnapi->cp_ring; 2713 cpr->bnapi = bnapi; 2714 ring = &cpr->cp_ring_struct; 2715 2716 rc = bnxt_alloc_ring(bp, &ring->ring_mem); 2717 if (rc) 2718 return rc; 2719 2720 if (ulp_msix && i >= ulp_base_vec) 2721 ring->map_idx = i + ulp_msix; 2722 else 2723 ring->map_idx = i; 2724 2725 if (!(bp->flags & BNXT_FLAG_CHIP_P5)) 2726 continue; 2727 2728 if (i < bp->rx_nr_rings) { 2729 struct bnxt_cp_ring_info *cpr2 = 2730 bnxt_alloc_cp_sub_ring(bp); 2731 2732 cpr->cp_ring_arr[BNXT_RX_HDL] = cpr2; 2733 if (!cpr2) 2734 return -ENOMEM; 2735 cpr2->bnapi = bnapi; 2736 } 2737 if ((sh && i < bp->tx_nr_rings) || 2738 (!sh && i >= bp->rx_nr_rings)) { 2739 struct bnxt_cp_ring_info *cpr2 = 2740 bnxt_alloc_cp_sub_ring(bp); 2741 2742 cpr->cp_ring_arr[BNXT_TX_HDL] = cpr2; 2743 if (!cpr2) 2744 return -ENOMEM; 2745 cpr2->bnapi = bnapi; 2746 } 2747 } 2748 return 0; 2749 } 2750 2751 static void bnxt_init_ring_struct(struct bnxt *bp) 2752 { 2753 int i; 2754 2755 for (i = 0; i < bp->cp_nr_rings; i++) { 2756 struct bnxt_napi *bnapi = bp->bnapi[i]; 2757 struct bnxt_ring_mem_info *rmem; 2758 struct bnxt_cp_ring_info *cpr; 2759 struct bnxt_rx_ring_info *rxr; 2760 struct bnxt_tx_ring_info *txr; 2761 struct bnxt_ring_struct *ring; 2762 2763 if (!bnapi) 2764 continue; 2765 2766 cpr = &bnapi->cp_ring; 2767 ring = &cpr->cp_ring_struct; 2768 rmem = &ring->ring_mem; 2769 rmem->nr_pages = bp->cp_nr_pages; 2770 rmem->page_size = HW_CMPD_RING_SIZE; 2771 rmem->pg_arr = (void **)cpr->cp_desc_ring; 2772 rmem->dma_arr = cpr->cp_desc_mapping; 2773 rmem->vmem_size = 0; 2774 2775 rxr = bnapi->rx_ring; 2776 if (!rxr) 2777 goto skip_rx; 2778 2779 ring = &rxr->rx_ring_struct; 2780 rmem = &ring->ring_mem; 2781 rmem->nr_pages = bp->rx_nr_pages; 2782 rmem->page_size = HW_RXBD_RING_SIZE; 2783 rmem->pg_arr = (void **)rxr->rx_desc_ring; 2784 rmem->dma_arr = rxr->rx_desc_mapping; 2785 rmem->vmem_size = SW_RXBD_RING_SIZE * bp->rx_nr_pages; 2786 rmem->vmem = (void **)&rxr->rx_buf_ring; 2787 2788 ring = &rxr->rx_agg_ring_struct; 2789 rmem = &ring->ring_mem; 2790 rmem->nr_pages = bp->rx_agg_nr_pages; 2791 rmem->page_size = HW_RXBD_RING_SIZE; 2792 rmem->pg_arr = (void **)rxr->rx_agg_desc_ring; 2793 rmem->dma_arr = rxr->rx_agg_desc_mapping; 2794 rmem->vmem_size = SW_RXBD_AGG_RING_SIZE * bp->rx_agg_nr_pages; 2795 rmem->vmem = (void **)&rxr->rx_agg_ring; 2796 2797 skip_rx: 2798 txr = bnapi->tx_ring; 2799 if (!txr) 2800 continue; 2801 2802 ring = &txr->tx_ring_struct; 2803 rmem = &ring->ring_mem; 2804 rmem->nr_pages = bp->tx_nr_pages; 2805 rmem->page_size = HW_RXBD_RING_SIZE; 2806 rmem->pg_arr = (void **)txr->tx_desc_ring; 2807 rmem->dma_arr = txr->tx_desc_mapping; 2808 rmem->vmem_size = SW_TXBD_RING_SIZE * bp->tx_nr_pages; 2809 rmem->vmem = (void **)&txr->tx_buf_ring; 2810 } 2811 } 2812 2813 static void bnxt_init_rxbd_pages(struct bnxt_ring_struct *ring, u32 type) 2814 { 2815 int i; 2816 u32 prod; 2817 struct rx_bd **rx_buf_ring; 2818 2819 rx_buf_ring = (struct rx_bd **)ring->ring_mem.pg_arr; 2820 for (i = 0, prod = 0; i < ring->ring_mem.nr_pages; i++) { 2821 int j; 2822 struct rx_bd *rxbd; 2823 2824 rxbd = rx_buf_ring[i]; 2825 if (!rxbd) 2826 continue; 2827 2828 for (j = 0; j < RX_DESC_CNT; j++, rxbd++, prod++) { 2829 rxbd->rx_bd_len_flags_type = cpu_to_le32(type); 2830 rxbd->rx_bd_opaque = prod; 2831 } 2832 } 2833 } 2834 2835 static int bnxt_init_one_rx_ring(struct bnxt *bp, int ring_nr) 2836 { 2837 struct net_device *dev = bp->dev; 2838 struct bnxt_rx_ring_info *rxr; 2839 struct bnxt_ring_struct *ring; 2840 u32 prod, type; 2841 int i; 2842 2843 type = (bp->rx_buf_use_size << RX_BD_LEN_SHIFT) | 2844 RX_BD_TYPE_RX_PACKET_BD | RX_BD_FLAGS_EOP; 2845 2846 if (NET_IP_ALIGN == 2) 2847 type |= RX_BD_FLAGS_SOP; 2848 2849 rxr = &bp->rx_ring[ring_nr]; 2850 ring = &rxr->rx_ring_struct; 2851 bnxt_init_rxbd_pages(ring, type); 2852 2853 if (BNXT_RX_PAGE_MODE(bp) && bp->xdp_prog) { 2854 rxr->xdp_prog = bpf_prog_add(bp->xdp_prog, 1); 2855 if (IS_ERR(rxr->xdp_prog)) { 2856 int rc = PTR_ERR(rxr->xdp_prog); 2857 2858 rxr->xdp_prog = NULL; 2859 return rc; 2860 } 2861 } 2862 prod = rxr->rx_prod; 2863 for (i = 0; i < bp->rx_ring_size; i++) { 2864 if (bnxt_alloc_rx_data(bp, rxr, prod, GFP_KERNEL) != 0) { 2865 netdev_warn(dev, "init'ed rx ring %d with %d/%d skbs only\n", 2866 ring_nr, i, bp->rx_ring_size); 2867 break; 2868 } 2869 prod = NEXT_RX(prod); 2870 } 2871 rxr->rx_prod = prod; 2872 ring->fw_ring_id = INVALID_HW_RING_ID; 2873 2874 ring = &rxr->rx_agg_ring_struct; 2875 ring->fw_ring_id = INVALID_HW_RING_ID; 2876 2877 if (!(bp->flags & BNXT_FLAG_AGG_RINGS)) 2878 return 0; 2879 2880 type = ((u32)BNXT_RX_PAGE_SIZE << RX_BD_LEN_SHIFT) | 2881 RX_BD_TYPE_RX_AGG_BD | RX_BD_FLAGS_SOP; 2882 2883 bnxt_init_rxbd_pages(ring, type); 2884 2885 prod = rxr->rx_agg_prod; 2886 for (i = 0; i < bp->rx_agg_ring_size; i++) { 2887 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_KERNEL) != 0) { 2888 netdev_warn(dev, "init'ed rx ring %d with %d/%d pages only\n", 2889 ring_nr, i, bp->rx_ring_size); 2890 break; 2891 } 2892 prod = NEXT_RX_AGG(prod); 2893 } 2894 rxr->rx_agg_prod = prod; 2895 2896 if (bp->flags & BNXT_FLAG_TPA) { 2897 if (rxr->rx_tpa) { 2898 u8 *data; 2899 dma_addr_t mapping; 2900 2901 for (i = 0; i < MAX_TPA; i++) { 2902 data = __bnxt_alloc_rx_data(bp, &mapping, 2903 GFP_KERNEL); 2904 if (!data) 2905 return -ENOMEM; 2906 2907 rxr->rx_tpa[i].data = data; 2908 rxr->rx_tpa[i].data_ptr = data + bp->rx_offset; 2909 rxr->rx_tpa[i].mapping = mapping; 2910 } 2911 } else { 2912 netdev_err(bp->dev, "No resource allocated for LRO/GRO\n"); 2913 return -ENOMEM; 2914 } 2915 } 2916 2917 return 0; 2918 } 2919 2920 static void bnxt_init_cp_rings(struct bnxt *bp) 2921 { 2922 int i, j; 2923 2924 for (i = 0; i < bp->cp_nr_rings; i++) { 2925 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring; 2926 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct; 2927 2928 ring->fw_ring_id = INVALID_HW_RING_ID; 2929 cpr->rx_ring_coal.coal_ticks = bp->rx_coal.coal_ticks; 2930 cpr->rx_ring_coal.coal_bufs = bp->rx_coal.coal_bufs; 2931 for (j = 0; j < 2; j++) { 2932 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j]; 2933 2934 if (!cpr2) 2935 continue; 2936 2937 ring = &cpr2->cp_ring_struct; 2938 ring->fw_ring_id = INVALID_HW_RING_ID; 2939 cpr2->rx_ring_coal.coal_ticks = bp->rx_coal.coal_ticks; 2940 cpr2->rx_ring_coal.coal_bufs = bp->rx_coal.coal_bufs; 2941 } 2942 } 2943 } 2944 2945 static int bnxt_init_rx_rings(struct bnxt *bp) 2946 { 2947 int i, rc = 0; 2948 2949 if (BNXT_RX_PAGE_MODE(bp)) { 2950 bp->rx_offset = NET_IP_ALIGN + XDP_PACKET_HEADROOM; 2951 bp->rx_dma_offset = XDP_PACKET_HEADROOM; 2952 } else { 2953 bp->rx_offset = BNXT_RX_OFFSET; 2954 bp->rx_dma_offset = BNXT_RX_DMA_OFFSET; 2955 } 2956 2957 for (i = 0; i < bp->rx_nr_rings; i++) { 2958 rc = bnxt_init_one_rx_ring(bp, i); 2959 if (rc) 2960 break; 2961 } 2962 2963 return rc; 2964 } 2965 2966 static int bnxt_init_tx_rings(struct bnxt *bp) 2967 { 2968 u16 i; 2969 2970 bp->tx_wake_thresh = max_t(int, bp->tx_ring_size / 2, 2971 MAX_SKB_FRAGS + 1); 2972 2973 for (i = 0; i < bp->tx_nr_rings; i++) { 2974 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; 2975 struct bnxt_ring_struct *ring = &txr->tx_ring_struct; 2976 2977 ring->fw_ring_id = INVALID_HW_RING_ID; 2978 } 2979 2980 return 0; 2981 } 2982 2983 static void bnxt_free_ring_grps(struct bnxt *bp) 2984 { 2985 kfree(bp->grp_info); 2986 bp->grp_info = NULL; 2987 } 2988 2989 static int bnxt_init_ring_grps(struct bnxt *bp, bool irq_re_init) 2990 { 2991 int i; 2992 2993 if (irq_re_init) { 2994 bp->grp_info = kcalloc(bp->cp_nr_rings, 2995 sizeof(struct bnxt_ring_grp_info), 2996 GFP_KERNEL); 2997 if (!bp->grp_info) 2998 return -ENOMEM; 2999 } 3000 for (i = 0; i < bp->cp_nr_rings; i++) { 3001 if (irq_re_init) 3002 bp->grp_info[i].fw_stats_ctx = INVALID_HW_RING_ID; 3003 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID; 3004 bp->grp_info[i].rx_fw_ring_id = INVALID_HW_RING_ID; 3005 bp->grp_info[i].agg_fw_ring_id = INVALID_HW_RING_ID; 3006 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID; 3007 } 3008 return 0; 3009 } 3010 3011 static void bnxt_free_vnics(struct bnxt *bp) 3012 { 3013 kfree(bp->vnic_info); 3014 bp->vnic_info = NULL; 3015 bp->nr_vnics = 0; 3016 } 3017 3018 static int bnxt_alloc_vnics(struct bnxt *bp) 3019 { 3020 int num_vnics = 1; 3021 3022 #ifdef CONFIG_RFS_ACCEL 3023 if (bp->flags & BNXT_FLAG_RFS) 3024 num_vnics += bp->rx_nr_rings; 3025 #endif 3026 3027 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 3028 num_vnics++; 3029 3030 bp->vnic_info = kcalloc(num_vnics, sizeof(struct bnxt_vnic_info), 3031 GFP_KERNEL); 3032 if (!bp->vnic_info) 3033 return -ENOMEM; 3034 3035 bp->nr_vnics = num_vnics; 3036 return 0; 3037 } 3038 3039 static void bnxt_init_vnics(struct bnxt *bp) 3040 { 3041 int i; 3042 3043 for (i = 0; i < bp->nr_vnics; i++) { 3044 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 3045 int j; 3046 3047 vnic->fw_vnic_id = INVALID_HW_RING_ID; 3048 for (j = 0; j < BNXT_MAX_CTX_PER_VNIC; j++) 3049 vnic->fw_rss_cos_lb_ctx[j] = INVALID_HW_RING_ID; 3050 3051 vnic->fw_l2_ctx_id = INVALID_HW_RING_ID; 3052 3053 if (bp->vnic_info[i].rss_hash_key) { 3054 if (i == 0) 3055 prandom_bytes(vnic->rss_hash_key, 3056 HW_HASH_KEY_SIZE); 3057 else 3058 memcpy(vnic->rss_hash_key, 3059 bp->vnic_info[0].rss_hash_key, 3060 HW_HASH_KEY_SIZE); 3061 } 3062 } 3063 } 3064 3065 static int bnxt_calc_nr_ring_pages(u32 ring_size, int desc_per_pg) 3066 { 3067 int pages; 3068 3069 pages = ring_size / desc_per_pg; 3070 3071 if (!pages) 3072 return 1; 3073 3074 pages++; 3075 3076 while (pages & (pages - 1)) 3077 pages++; 3078 3079 return pages; 3080 } 3081 3082 void bnxt_set_tpa_flags(struct bnxt *bp) 3083 { 3084 bp->flags &= ~BNXT_FLAG_TPA; 3085 if (bp->flags & BNXT_FLAG_NO_AGG_RINGS) 3086 return; 3087 if (bp->dev->features & NETIF_F_LRO) 3088 bp->flags |= BNXT_FLAG_LRO; 3089 else if (bp->dev->features & NETIF_F_GRO_HW) 3090 bp->flags |= BNXT_FLAG_GRO; 3091 } 3092 3093 /* bp->rx_ring_size, bp->tx_ring_size, dev->mtu, BNXT_FLAG_{G|L}RO flags must 3094 * be set on entry. 3095 */ 3096 void bnxt_set_ring_params(struct bnxt *bp) 3097 { 3098 u32 ring_size, rx_size, rx_space; 3099 u32 agg_factor = 0, agg_ring_size = 0; 3100 3101 /* 8 for CRC and VLAN */ 3102 rx_size = SKB_DATA_ALIGN(bp->dev->mtu + ETH_HLEN + NET_IP_ALIGN + 8); 3103 3104 rx_space = rx_size + NET_SKB_PAD + 3105 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 3106 3107 bp->rx_copy_thresh = BNXT_RX_COPY_THRESH; 3108 ring_size = bp->rx_ring_size; 3109 bp->rx_agg_ring_size = 0; 3110 bp->rx_agg_nr_pages = 0; 3111 3112 if (bp->flags & BNXT_FLAG_TPA) 3113 agg_factor = min_t(u32, 4, 65536 / BNXT_RX_PAGE_SIZE); 3114 3115 bp->flags &= ~BNXT_FLAG_JUMBO; 3116 if (rx_space > PAGE_SIZE && !(bp->flags & BNXT_FLAG_NO_AGG_RINGS)) { 3117 u32 jumbo_factor; 3118 3119 bp->flags |= BNXT_FLAG_JUMBO; 3120 jumbo_factor = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT; 3121 if (jumbo_factor > agg_factor) 3122 agg_factor = jumbo_factor; 3123 } 3124 agg_ring_size = ring_size * agg_factor; 3125 3126 if (agg_ring_size) { 3127 bp->rx_agg_nr_pages = bnxt_calc_nr_ring_pages(agg_ring_size, 3128 RX_DESC_CNT); 3129 if (bp->rx_agg_nr_pages > MAX_RX_AGG_PAGES) { 3130 u32 tmp = agg_ring_size; 3131 3132 bp->rx_agg_nr_pages = MAX_RX_AGG_PAGES; 3133 agg_ring_size = MAX_RX_AGG_PAGES * RX_DESC_CNT - 1; 3134 netdev_warn(bp->dev, "rx agg ring size %d reduced to %d.\n", 3135 tmp, agg_ring_size); 3136 } 3137 bp->rx_agg_ring_size = agg_ring_size; 3138 bp->rx_agg_ring_mask = (bp->rx_agg_nr_pages * RX_DESC_CNT) - 1; 3139 rx_size = SKB_DATA_ALIGN(BNXT_RX_COPY_THRESH + NET_IP_ALIGN); 3140 rx_space = rx_size + NET_SKB_PAD + 3141 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 3142 } 3143 3144 bp->rx_buf_use_size = rx_size; 3145 bp->rx_buf_size = rx_space; 3146 3147 bp->rx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, RX_DESC_CNT); 3148 bp->rx_ring_mask = (bp->rx_nr_pages * RX_DESC_CNT) - 1; 3149 3150 ring_size = bp->tx_ring_size; 3151 bp->tx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, TX_DESC_CNT); 3152 bp->tx_ring_mask = (bp->tx_nr_pages * TX_DESC_CNT) - 1; 3153 3154 ring_size = bp->rx_ring_size * (2 + agg_factor) + bp->tx_ring_size; 3155 bp->cp_ring_size = ring_size; 3156 3157 bp->cp_nr_pages = bnxt_calc_nr_ring_pages(ring_size, CP_DESC_CNT); 3158 if (bp->cp_nr_pages > MAX_CP_PAGES) { 3159 bp->cp_nr_pages = MAX_CP_PAGES; 3160 bp->cp_ring_size = MAX_CP_PAGES * CP_DESC_CNT - 1; 3161 netdev_warn(bp->dev, "completion ring size %d reduced to %d.\n", 3162 ring_size, bp->cp_ring_size); 3163 } 3164 bp->cp_bit = bp->cp_nr_pages * CP_DESC_CNT; 3165 bp->cp_ring_mask = bp->cp_bit - 1; 3166 } 3167 3168 /* Changing allocation mode of RX rings. 3169 * TODO: Update when extending xdp_rxq_info to support allocation modes. 3170 */ 3171 int bnxt_set_rx_skb_mode(struct bnxt *bp, bool page_mode) 3172 { 3173 if (page_mode) { 3174 if (bp->dev->mtu > BNXT_MAX_PAGE_MODE_MTU) 3175 return -EOPNOTSUPP; 3176 bp->dev->max_mtu = 3177 min_t(u16, bp->max_mtu, BNXT_MAX_PAGE_MODE_MTU); 3178 bp->flags &= ~BNXT_FLAG_AGG_RINGS; 3179 bp->flags |= BNXT_FLAG_NO_AGG_RINGS | BNXT_FLAG_RX_PAGE_MODE; 3180 bp->rx_dir = DMA_BIDIRECTIONAL; 3181 bp->rx_skb_func = bnxt_rx_page_skb; 3182 /* Disable LRO or GRO_HW */ 3183 netdev_update_features(bp->dev); 3184 } else { 3185 bp->dev->max_mtu = bp->max_mtu; 3186 bp->flags &= ~BNXT_FLAG_RX_PAGE_MODE; 3187 bp->rx_dir = DMA_FROM_DEVICE; 3188 bp->rx_skb_func = bnxt_rx_skb; 3189 } 3190 return 0; 3191 } 3192 3193 static void bnxt_free_vnic_attributes(struct bnxt *bp) 3194 { 3195 int i; 3196 struct bnxt_vnic_info *vnic; 3197 struct pci_dev *pdev = bp->pdev; 3198 3199 if (!bp->vnic_info) 3200 return; 3201 3202 for (i = 0; i < bp->nr_vnics; i++) { 3203 vnic = &bp->vnic_info[i]; 3204 3205 kfree(vnic->fw_grp_ids); 3206 vnic->fw_grp_ids = NULL; 3207 3208 kfree(vnic->uc_list); 3209 vnic->uc_list = NULL; 3210 3211 if (vnic->mc_list) { 3212 dma_free_coherent(&pdev->dev, vnic->mc_list_size, 3213 vnic->mc_list, vnic->mc_list_mapping); 3214 vnic->mc_list = NULL; 3215 } 3216 3217 if (vnic->rss_table) { 3218 dma_free_coherent(&pdev->dev, PAGE_SIZE, 3219 vnic->rss_table, 3220 vnic->rss_table_dma_addr); 3221 vnic->rss_table = NULL; 3222 } 3223 3224 vnic->rss_hash_key = NULL; 3225 vnic->flags = 0; 3226 } 3227 } 3228 3229 static int bnxt_alloc_vnic_attributes(struct bnxt *bp) 3230 { 3231 int i, rc = 0, size; 3232 struct bnxt_vnic_info *vnic; 3233 struct pci_dev *pdev = bp->pdev; 3234 int max_rings; 3235 3236 for (i = 0; i < bp->nr_vnics; i++) { 3237 vnic = &bp->vnic_info[i]; 3238 3239 if (vnic->flags & BNXT_VNIC_UCAST_FLAG) { 3240 int mem_size = (BNXT_MAX_UC_ADDRS - 1) * ETH_ALEN; 3241 3242 if (mem_size > 0) { 3243 vnic->uc_list = kmalloc(mem_size, GFP_KERNEL); 3244 if (!vnic->uc_list) { 3245 rc = -ENOMEM; 3246 goto out; 3247 } 3248 } 3249 } 3250 3251 if (vnic->flags & BNXT_VNIC_MCAST_FLAG) { 3252 vnic->mc_list_size = BNXT_MAX_MC_ADDRS * ETH_ALEN; 3253 vnic->mc_list = 3254 dma_alloc_coherent(&pdev->dev, 3255 vnic->mc_list_size, 3256 &vnic->mc_list_mapping, 3257 GFP_KERNEL); 3258 if (!vnic->mc_list) { 3259 rc = -ENOMEM; 3260 goto out; 3261 } 3262 } 3263 3264 if (bp->flags & BNXT_FLAG_CHIP_P5) 3265 goto vnic_skip_grps; 3266 3267 if (vnic->flags & BNXT_VNIC_RSS_FLAG) 3268 max_rings = bp->rx_nr_rings; 3269 else 3270 max_rings = 1; 3271 3272 vnic->fw_grp_ids = kcalloc(max_rings, sizeof(u16), GFP_KERNEL); 3273 if (!vnic->fw_grp_ids) { 3274 rc = -ENOMEM; 3275 goto out; 3276 } 3277 vnic_skip_grps: 3278 if ((bp->flags & BNXT_FLAG_NEW_RSS_CAP) && 3279 !(vnic->flags & BNXT_VNIC_RSS_FLAG)) 3280 continue; 3281 3282 /* Allocate rss table and hash key */ 3283 vnic->rss_table = dma_alloc_coherent(&pdev->dev, PAGE_SIZE, 3284 &vnic->rss_table_dma_addr, 3285 GFP_KERNEL); 3286 if (!vnic->rss_table) { 3287 rc = -ENOMEM; 3288 goto out; 3289 } 3290 3291 size = L1_CACHE_ALIGN(HW_HASH_INDEX_SIZE * sizeof(u16)); 3292 3293 vnic->rss_hash_key = ((void *)vnic->rss_table) + size; 3294 vnic->rss_hash_key_dma_addr = vnic->rss_table_dma_addr + size; 3295 } 3296 return 0; 3297 3298 out: 3299 return rc; 3300 } 3301 3302 static void bnxt_free_hwrm_resources(struct bnxt *bp) 3303 { 3304 struct pci_dev *pdev = bp->pdev; 3305 3306 if (bp->hwrm_cmd_resp_addr) { 3307 dma_free_coherent(&pdev->dev, PAGE_SIZE, bp->hwrm_cmd_resp_addr, 3308 bp->hwrm_cmd_resp_dma_addr); 3309 bp->hwrm_cmd_resp_addr = NULL; 3310 } 3311 3312 if (bp->hwrm_cmd_kong_resp_addr) { 3313 dma_free_coherent(&pdev->dev, PAGE_SIZE, 3314 bp->hwrm_cmd_kong_resp_addr, 3315 bp->hwrm_cmd_kong_resp_dma_addr); 3316 bp->hwrm_cmd_kong_resp_addr = NULL; 3317 } 3318 } 3319 3320 static int bnxt_alloc_kong_hwrm_resources(struct bnxt *bp) 3321 { 3322 struct pci_dev *pdev = bp->pdev; 3323 3324 bp->hwrm_cmd_kong_resp_addr = 3325 dma_alloc_coherent(&pdev->dev, PAGE_SIZE, 3326 &bp->hwrm_cmd_kong_resp_dma_addr, 3327 GFP_KERNEL); 3328 if (!bp->hwrm_cmd_kong_resp_addr) 3329 return -ENOMEM; 3330 3331 return 0; 3332 } 3333 3334 static int bnxt_alloc_hwrm_resources(struct bnxt *bp) 3335 { 3336 struct pci_dev *pdev = bp->pdev; 3337 3338 bp->hwrm_cmd_resp_addr = dma_alloc_coherent(&pdev->dev, PAGE_SIZE, 3339 &bp->hwrm_cmd_resp_dma_addr, 3340 GFP_KERNEL); 3341 if (!bp->hwrm_cmd_resp_addr) 3342 return -ENOMEM; 3343 3344 return 0; 3345 } 3346 3347 static void bnxt_free_hwrm_short_cmd_req(struct bnxt *bp) 3348 { 3349 if (bp->hwrm_short_cmd_req_addr) { 3350 struct pci_dev *pdev = bp->pdev; 3351 3352 dma_free_coherent(&pdev->dev, bp->hwrm_max_ext_req_len, 3353 bp->hwrm_short_cmd_req_addr, 3354 bp->hwrm_short_cmd_req_dma_addr); 3355 bp->hwrm_short_cmd_req_addr = NULL; 3356 } 3357 } 3358 3359 static int bnxt_alloc_hwrm_short_cmd_req(struct bnxt *bp) 3360 { 3361 struct pci_dev *pdev = bp->pdev; 3362 3363 bp->hwrm_short_cmd_req_addr = 3364 dma_alloc_coherent(&pdev->dev, bp->hwrm_max_ext_req_len, 3365 &bp->hwrm_short_cmd_req_dma_addr, 3366 GFP_KERNEL); 3367 if (!bp->hwrm_short_cmd_req_addr) 3368 return -ENOMEM; 3369 3370 return 0; 3371 } 3372 3373 static void bnxt_free_port_stats(struct bnxt *bp) 3374 { 3375 struct pci_dev *pdev = bp->pdev; 3376 3377 bp->flags &= ~BNXT_FLAG_PORT_STATS; 3378 bp->flags &= ~BNXT_FLAG_PORT_STATS_EXT; 3379 3380 if (bp->hw_rx_port_stats) { 3381 dma_free_coherent(&pdev->dev, bp->hw_port_stats_size, 3382 bp->hw_rx_port_stats, 3383 bp->hw_rx_port_stats_map); 3384 bp->hw_rx_port_stats = NULL; 3385 } 3386 3387 if (bp->hw_tx_port_stats_ext) { 3388 dma_free_coherent(&pdev->dev, sizeof(struct tx_port_stats_ext), 3389 bp->hw_tx_port_stats_ext, 3390 bp->hw_tx_port_stats_ext_map); 3391 bp->hw_tx_port_stats_ext = NULL; 3392 } 3393 3394 if (bp->hw_rx_port_stats_ext) { 3395 dma_free_coherent(&pdev->dev, sizeof(struct rx_port_stats_ext), 3396 bp->hw_rx_port_stats_ext, 3397 bp->hw_rx_port_stats_ext_map); 3398 bp->hw_rx_port_stats_ext = NULL; 3399 } 3400 3401 if (bp->hw_pcie_stats) { 3402 dma_free_coherent(&pdev->dev, sizeof(struct pcie_ctx_hw_stats), 3403 bp->hw_pcie_stats, bp->hw_pcie_stats_map); 3404 bp->hw_pcie_stats = NULL; 3405 } 3406 } 3407 3408 static void bnxt_free_ring_stats(struct bnxt *bp) 3409 { 3410 struct pci_dev *pdev = bp->pdev; 3411 int size, i; 3412 3413 if (!bp->bnapi) 3414 return; 3415 3416 size = sizeof(struct ctx_hw_stats); 3417 3418 for (i = 0; i < bp->cp_nr_rings; i++) { 3419 struct bnxt_napi *bnapi = bp->bnapi[i]; 3420 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 3421 3422 if (cpr->hw_stats) { 3423 dma_free_coherent(&pdev->dev, size, cpr->hw_stats, 3424 cpr->hw_stats_map); 3425 cpr->hw_stats = NULL; 3426 } 3427 } 3428 } 3429 3430 static int bnxt_alloc_stats(struct bnxt *bp) 3431 { 3432 u32 size, i; 3433 struct pci_dev *pdev = bp->pdev; 3434 3435 size = sizeof(struct ctx_hw_stats); 3436 3437 for (i = 0; i < bp->cp_nr_rings; i++) { 3438 struct bnxt_napi *bnapi = bp->bnapi[i]; 3439 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 3440 3441 cpr->hw_stats = dma_alloc_coherent(&pdev->dev, size, 3442 &cpr->hw_stats_map, 3443 GFP_KERNEL); 3444 if (!cpr->hw_stats) 3445 return -ENOMEM; 3446 3447 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID; 3448 } 3449 3450 if (BNXT_VF(bp) || bp->chip_num == CHIP_NUM_58700) 3451 return 0; 3452 3453 if (bp->hw_rx_port_stats) 3454 goto alloc_ext_stats; 3455 3456 bp->hw_port_stats_size = sizeof(struct rx_port_stats) + 3457 sizeof(struct tx_port_stats) + 1024; 3458 3459 bp->hw_rx_port_stats = 3460 dma_alloc_coherent(&pdev->dev, bp->hw_port_stats_size, 3461 &bp->hw_rx_port_stats_map, 3462 GFP_KERNEL); 3463 if (!bp->hw_rx_port_stats) 3464 return -ENOMEM; 3465 3466 bp->hw_tx_port_stats = (void *)(bp->hw_rx_port_stats + 1) + 512; 3467 bp->hw_tx_port_stats_map = bp->hw_rx_port_stats_map + 3468 sizeof(struct rx_port_stats) + 512; 3469 bp->flags |= BNXT_FLAG_PORT_STATS; 3470 3471 alloc_ext_stats: 3472 /* Display extended statistics only if FW supports it */ 3473 if (bp->hwrm_spec_code < 0x10804 || bp->hwrm_spec_code == 0x10900) 3474 if (!(bp->fw_cap & BNXT_FW_CAP_EXT_STATS_SUPPORTED)) 3475 return 0; 3476 3477 if (bp->hw_rx_port_stats_ext) 3478 goto alloc_tx_ext_stats; 3479 3480 bp->hw_rx_port_stats_ext = 3481 dma_alloc_coherent(&pdev->dev, sizeof(struct rx_port_stats_ext), 3482 &bp->hw_rx_port_stats_ext_map, GFP_KERNEL); 3483 if (!bp->hw_rx_port_stats_ext) 3484 return 0; 3485 3486 alloc_tx_ext_stats: 3487 if (bp->hw_tx_port_stats_ext) 3488 goto alloc_pcie_stats; 3489 3490 if (bp->hwrm_spec_code >= 0x10902 || 3491 (bp->fw_cap & BNXT_FW_CAP_EXT_STATS_SUPPORTED)) { 3492 bp->hw_tx_port_stats_ext = 3493 dma_alloc_coherent(&pdev->dev, 3494 sizeof(struct tx_port_stats_ext), 3495 &bp->hw_tx_port_stats_ext_map, 3496 GFP_KERNEL); 3497 } 3498 bp->flags |= BNXT_FLAG_PORT_STATS_EXT; 3499 3500 alloc_pcie_stats: 3501 if (bp->hw_pcie_stats || 3502 !(bp->fw_cap & BNXT_FW_CAP_PCIE_STATS_SUPPORTED)) 3503 return 0; 3504 3505 bp->hw_pcie_stats = 3506 dma_alloc_coherent(&pdev->dev, sizeof(struct pcie_ctx_hw_stats), 3507 &bp->hw_pcie_stats_map, GFP_KERNEL); 3508 if (!bp->hw_pcie_stats) 3509 return 0; 3510 3511 bp->flags |= BNXT_FLAG_PCIE_STATS; 3512 return 0; 3513 } 3514 3515 static void bnxt_clear_ring_indices(struct bnxt *bp) 3516 { 3517 int i; 3518 3519 if (!bp->bnapi) 3520 return; 3521 3522 for (i = 0; i < bp->cp_nr_rings; i++) { 3523 struct bnxt_napi *bnapi = bp->bnapi[i]; 3524 struct bnxt_cp_ring_info *cpr; 3525 struct bnxt_rx_ring_info *rxr; 3526 struct bnxt_tx_ring_info *txr; 3527 3528 if (!bnapi) 3529 continue; 3530 3531 cpr = &bnapi->cp_ring; 3532 cpr->cp_raw_cons = 0; 3533 3534 txr = bnapi->tx_ring; 3535 if (txr) { 3536 txr->tx_prod = 0; 3537 txr->tx_cons = 0; 3538 } 3539 3540 rxr = bnapi->rx_ring; 3541 if (rxr) { 3542 rxr->rx_prod = 0; 3543 rxr->rx_agg_prod = 0; 3544 rxr->rx_sw_agg_prod = 0; 3545 rxr->rx_next_cons = 0; 3546 } 3547 } 3548 } 3549 3550 static void bnxt_free_ntp_fltrs(struct bnxt *bp, bool irq_reinit) 3551 { 3552 #ifdef CONFIG_RFS_ACCEL 3553 int i; 3554 3555 /* Under rtnl_lock and all our NAPIs have been disabled. It's 3556 * safe to delete the hash table. 3557 */ 3558 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) { 3559 struct hlist_head *head; 3560 struct hlist_node *tmp; 3561 struct bnxt_ntuple_filter *fltr; 3562 3563 head = &bp->ntp_fltr_hash_tbl[i]; 3564 hlist_for_each_entry_safe(fltr, tmp, head, hash) { 3565 hlist_del(&fltr->hash); 3566 kfree(fltr); 3567 } 3568 } 3569 if (irq_reinit) { 3570 kfree(bp->ntp_fltr_bmap); 3571 bp->ntp_fltr_bmap = NULL; 3572 } 3573 bp->ntp_fltr_count = 0; 3574 #endif 3575 } 3576 3577 static int bnxt_alloc_ntp_fltrs(struct bnxt *bp) 3578 { 3579 #ifdef CONFIG_RFS_ACCEL 3580 int i, rc = 0; 3581 3582 if (!(bp->flags & BNXT_FLAG_RFS)) 3583 return 0; 3584 3585 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) 3586 INIT_HLIST_HEAD(&bp->ntp_fltr_hash_tbl[i]); 3587 3588 bp->ntp_fltr_count = 0; 3589 bp->ntp_fltr_bmap = kcalloc(BITS_TO_LONGS(BNXT_NTP_FLTR_MAX_FLTR), 3590 sizeof(long), 3591 GFP_KERNEL); 3592 3593 if (!bp->ntp_fltr_bmap) 3594 rc = -ENOMEM; 3595 3596 return rc; 3597 #else 3598 return 0; 3599 #endif 3600 } 3601 3602 static void bnxt_free_mem(struct bnxt *bp, bool irq_re_init) 3603 { 3604 bnxt_free_vnic_attributes(bp); 3605 bnxt_free_tx_rings(bp); 3606 bnxt_free_rx_rings(bp); 3607 bnxt_free_cp_rings(bp); 3608 bnxt_free_ntp_fltrs(bp, irq_re_init); 3609 if (irq_re_init) { 3610 bnxt_free_ring_stats(bp); 3611 bnxt_free_ring_grps(bp); 3612 bnxt_free_vnics(bp); 3613 kfree(bp->tx_ring_map); 3614 bp->tx_ring_map = NULL; 3615 kfree(bp->tx_ring); 3616 bp->tx_ring = NULL; 3617 kfree(bp->rx_ring); 3618 bp->rx_ring = NULL; 3619 kfree(bp->bnapi); 3620 bp->bnapi = NULL; 3621 } else { 3622 bnxt_clear_ring_indices(bp); 3623 } 3624 } 3625 3626 static int bnxt_alloc_mem(struct bnxt *bp, bool irq_re_init) 3627 { 3628 int i, j, rc, size, arr_size; 3629 void *bnapi; 3630 3631 if (irq_re_init) { 3632 /* Allocate bnapi mem pointer array and mem block for 3633 * all queues 3634 */ 3635 arr_size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi *) * 3636 bp->cp_nr_rings); 3637 size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi)); 3638 bnapi = kzalloc(arr_size + size * bp->cp_nr_rings, GFP_KERNEL); 3639 if (!bnapi) 3640 return -ENOMEM; 3641 3642 bp->bnapi = bnapi; 3643 bnapi += arr_size; 3644 for (i = 0; i < bp->cp_nr_rings; i++, bnapi += size) { 3645 bp->bnapi[i] = bnapi; 3646 bp->bnapi[i]->index = i; 3647 bp->bnapi[i]->bp = bp; 3648 if (bp->flags & BNXT_FLAG_CHIP_P5) { 3649 struct bnxt_cp_ring_info *cpr = 3650 &bp->bnapi[i]->cp_ring; 3651 3652 cpr->cp_ring_struct.ring_mem.flags = 3653 BNXT_RMEM_RING_PTE_FLAG; 3654 } 3655 } 3656 3657 bp->rx_ring = kcalloc(bp->rx_nr_rings, 3658 sizeof(struct bnxt_rx_ring_info), 3659 GFP_KERNEL); 3660 if (!bp->rx_ring) 3661 return -ENOMEM; 3662 3663 for (i = 0; i < bp->rx_nr_rings; i++) { 3664 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 3665 3666 if (bp->flags & BNXT_FLAG_CHIP_P5) { 3667 rxr->rx_ring_struct.ring_mem.flags = 3668 BNXT_RMEM_RING_PTE_FLAG; 3669 rxr->rx_agg_ring_struct.ring_mem.flags = 3670 BNXT_RMEM_RING_PTE_FLAG; 3671 } 3672 rxr->bnapi = bp->bnapi[i]; 3673 bp->bnapi[i]->rx_ring = &bp->rx_ring[i]; 3674 } 3675 3676 bp->tx_ring = kcalloc(bp->tx_nr_rings, 3677 sizeof(struct bnxt_tx_ring_info), 3678 GFP_KERNEL); 3679 if (!bp->tx_ring) 3680 return -ENOMEM; 3681 3682 bp->tx_ring_map = kcalloc(bp->tx_nr_rings, sizeof(u16), 3683 GFP_KERNEL); 3684 3685 if (!bp->tx_ring_map) 3686 return -ENOMEM; 3687 3688 if (bp->flags & BNXT_FLAG_SHARED_RINGS) 3689 j = 0; 3690 else 3691 j = bp->rx_nr_rings; 3692 3693 for (i = 0; i < bp->tx_nr_rings; i++, j++) { 3694 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; 3695 3696 if (bp->flags & BNXT_FLAG_CHIP_P5) 3697 txr->tx_ring_struct.ring_mem.flags = 3698 BNXT_RMEM_RING_PTE_FLAG; 3699 txr->bnapi = bp->bnapi[j]; 3700 bp->bnapi[j]->tx_ring = txr; 3701 bp->tx_ring_map[i] = bp->tx_nr_rings_xdp + i; 3702 if (i >= bp->tx_nr_rings_xdp) { 3703 txr->txq_index = i - bp->tx_nr_rings_xdp; 3704 bp->bnapi[j]->tx_int = bnxt_tx_int; 3705 } else { 3706 bp->bnapi[j]->flags |= BNXT_NAPI_FLAG_XDP; 3707 bp->bnapi[j]->tx_int = bnxt_tx_int_xdp; 3708 } 3709 } 3710 3711 rc = bnxt_alloc_stats(bp); 3712 if (rc) 3713 goto alloc_mem_err; 3714 3715 rc = bnxt_alloc_ntp_fltrs(bp); 3716 if (rc) 3717 goto alloc_mem_err; 3718 3719 rc = bnxt_alloc_vnics(bp); 3720 if (rc) 3721 goto alloc_mem_err; 3722 } 3723 3724 bnxt_init_ring_struct(bp); 3725 3726 rc = bnxt_alloc_rx_rings(bp); 3727 if (rc) 3728 goto alloc_mem_err; 3729 3730 rc = bnxt_alloc_tx_rings(bp); 3731 if (rc) 3732 goto alloc_mem_err; 3733 3734 rc = bnxt_alloc_cp_rings(bp); 3735 if (rc) 3736 goto alloc_mem_err; 3737 3738 bp->vnic_info[0].flags |= BNXT_VNIC_RSS_FLAG | BNXT_VNIC_MCAST_FLAG | 3739 BNXT_VNIC_UCAST_FLAG; 3740 rc = bnxt_alloc_vnic_attributes(bp); 3741 if (rc) 3742 goto alloc_mem_err; 3743 return 0; 3744 3745 alloc_mem_err: 3746 bnxt_free_mem(bp, true); 3747 return rc; 3748 } 3749 3750 static void bnxt_disable_int(struct bnxt *bp) 3751 { 3752 int i; 3753 3754 if (!bp->bnapi) 3755 return; 3756 3757 for (i = 0; i < bp->cp_nr_rings; i++) { 3758 struct bnxt_napi *bnapi = bp->bnapi[i]; 3759 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 3760 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct; 3761 3762 if (ring->fw_ring_id != INVALID_HW_RING_ID) 3763 bnxt_db_nq(bp, &cpr->cp_db, cpr->cp_raw_cons); 3764 } 3765 } 3766 3767 static int bnxt_cp_num_to_irq_num(struct bnxt *bp, int n) 3768 { 3769 struct bnxt_napi *bnapi = bp->bnapi[n]; 3770 struct bnxt_cp_ring_info *cpr; 3771 3772 cpr = &bnapi->cp_ring; 3773 return cpr->cp_ring_struct.map_idx; 3774 } 3775 3776 static void bnxt_disable_int_sync(struct bnxt *bp) 3777 { 3778 int i; 3779 3780 atomic_inc(&bp->intr_sem); 3781 3782 bnxt_disable_int(bp); 3783 for (i = 0; i < bp->cp_nr_rings; i++) { 3784 int map_idx = bnxt_cp_num_to_irq_num(bp, i); 3785 3786 synchronize_irq(bp->irq_tbl[map_idx].vector); 3787 } 3788 } 3789 3790 static void bnxt_enable_int(struct bnxt *bp) 3791 { 3792 int i; 3793 3794 atomic_set(&bp->intr_sem, 0); 3795 for (i = 0; i < bp->cp_nr_rings; i++) { 3796 struct bnxt_napi *bnapi = bp->bnapi[i]; 3797 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 3798 3799 bnxt_db_nq_arm(bp, &cpr->cp_db, cpr->cp_raw_cons); 3800 } 3801 } 3802 3803 void bnxt_hwrm_cmd_hdr_init(struct bnxt *bp, void *request, u16 req_type, 3804 u16 cmpl_ring, u16 target_id) 3805 { 3806 struct input *req = request; 3807 3808 req->req_type = cpu_to_le16(req_type); 3809 req->cmpl_ring = cpu_to_le16(cmpl_ring); 3810 req->target_id = cpu_to_le16(target_id); 3811 if (bnxt_kong_hwrm_message(bp, req)) 3812 req->resp_addr = cpu_to_le64(bp->hwrm_cmd_kong_resp_dma_addr); 3813 else 3814 req->resp_addr = cpu_to_le64(bp->hwrm_cmd_resp_dma_addr); 3815 } 3816 3817 static int bnxt_hwrm_do_send_msg(struct bnxt *bp, void *msg, u32 msg_len, 3818 int timeout, bool silent) 3819 { 3820 int i, intr_process, rc, tmo_count; 3821 struct input *req = msg; 3822 u32 *data = msg; 3823 __le32 *resp_len; 3824 u8 *valid; 3825 u16 cp_ring_id, len = 0; 3826 struct hwrm_err_output *resp = bp->hwrm_cmd_resp_addr; 3827 u16 max_req_len = BNXT_HWRM_MAX_REQ_LEN; 3828 struct hwrm_short_input short_input = {0}; 3829 u32 doorbell_offset = BNXT_GRCPF_REG_CHIMP_COMM_TRIGGER; 3830 u8 *resp_addr = (u8 *)bp->hwrm_cmd_resp_addr; 3831 u32 bar_offset = BNXT_GRCPF_REG_CHIMP_COMM; 3832 u16 dst = BNXT_HWRM_CHNL_CHIMP; 3833 3834 if (msg_len > BNXT_HWRM_MAX_REQ_LEN) { 3835 if (msg_len > bp->hwrm_max_ext_req_len || 3836 !bp->hwrm_short_cmd_req_addr) 3837 return -EINVAL; 3838 } 3839 3840 if (bnxt_hwrm_kong_chnl(bp, req)) { 3841 dst = BNXT_HWRM_CHNL_KONG; 3842 bar_offset = BNXT_GRCPF_REG_KONG_COMM; 3843 doorbell_offset = BNXT_GRCPF_REG_KONG_COMM_TRIGGER; 3844 resp = bp->hwrm_cmd_kong_resp_addr; 3845 resp_addr = (u8 *)bp->hwrm_cmd_kong_resp_addr; 3846 } 3847 3848 memset(resp, 0, PAGE_SIZE); 3849 cp_ring_id = le16_to_cpu(req->cmpl_ring); 3850 intr_process = (cp_ring_id == INVALID_HW_RING_ID) ? 0 : 1; 3851 3852 req->seq_id = cpu_to_le16(bnxt_get_hwrm_seq_id(bp, dst)); 3853 /* currently supports only one outstanding message */ 3854 if (intr_process) 3855 bp->hwrm_intr_seq_id = le16_to_cpu(req->seq_id); 3856 3857 if ((bp->fw_cap & BNXT_FW_CAP_SHORT_CMD) || 3858 msg_len > BNXT_HWRM_MAX_REQ_LEN) { 3859 void *short_cmd_req = bp->hwrm_short_cmd_req_addr; 3860 u16 max_msg_len; 3861 3862 /* Set boundary for maximum extended request length for short 3863 * cmd format. If passed up from device use the max supported 3864 * internal req length. 3865 */ 3866 max_msg_len = bp->hwrm_max_ext_req_len; 3867 3868 memcpy(short_cmd_req, req, msg_len); 3869 if (msg_len < max_msg_len) 3870 memset(short_cmd_req + msg_len, 0, 3871 max_msg_len - msg_len); 3872 3873 short_input.req_type = req->req_type; 3874 short_input.signature = 3875 cpu_to_le16(SHORT_REQ_SIGNATURE_SHORT_CMD); 3876 short_input.size = cpu_to_le16(msg_len); 3877 short_input.req_addr = 3878 cpu_to_le64(bp->hwrm_short_cmd_req_dma_addr); 3879 3880 data = (u32 *)&short_input; 3881 msg_len = sizeof(short_input); 3882 3883 /* Sync memory write before updating doorbell */ 3884 wmb(); 3885 3886 max_req_len = BNXT_HWRM_SHORT_REQ_LEN; 3887 } 3888 3889 /* Write request msg to hwrm channel */ 3890 __iowrite32_copy(bp->bar0 + bar_offset, data, msg_len / 4); 3891 3892 for (i = msg_len; i < max_req_len; i += 4) 3893 writel(0, bp->bar0 + bar_offset + i); 3894 3895 /* Ring channel doorbell */ 3896 writel(1, bp->bar0 + doorbell_offset); 3897 3898 if (!timeout) 3899 timeout = DFLT_HWRM_CMD_TIMEOUT; 3900 /* convert timeout to usec */ 3901 timeout *= 1000; 3902 3903 i = 0; 3904 /* Short timeout for the first few iterations: 3905 * number of loops = number of loops for short timeout + 3906 * number of loops for standard timeout. 3907 */ 3908 tmo_count = HWRM_SHORT_TIMEOUT_COUNTER; 3909 timeout = timeout - HWRM_SHORT_MIN_TIMEOUT * HWRM_SHORT_TIMEOUT_COUNTER; 3910 tmo_count += DIV_ROUND_UP(timeout, HWRM_MIN_TIMEOUT); 3911 resp_len = (__le32 *)(resp_addr + HWRM_RESP_LEN_OFFSET); 3912 3913 if (intr_process) { 3914 u16 seq_id = bp->hwrm_intr_seq_id; 3915 3916 /* Wait until hwrm response cmpl interrupt is processed */ 3917 while (bp->hwrm_intr_seq_id != (u16)~seq_id && 3918 i++ < tmo_count) { 3919 /* on first few passes, just barely sleep */ 3920 if (i < HWRM_SHORT_TIMEOUT_COUNTER) 3921 usleep_range(HWRM_SHORT_MIN_TIMEOUT, 3922 HWRM_SHORT_MAX_TIMEOUT); 3923 else 3924 usleep_range(HWRM_MIN_TIMEOUT, 3925 HWRM_MAX_TIMEOUT); 3926 } 3927 3928 if (bp->hwrm_intr_seq_id != (u16)~seq_id) { 3929 netdev_err(bp->dev, "Resp cmpl intr err msg: 0x%x\n", 3930 le16_to_cpu(req->req_type)); 3931 return -1; 3932 } 3933 len = (le32_to_cpu(*resp_len) & HWRM_RESP_LEN_MASK) >> 3934 HWRM_RESP_LEN_SFT; 3935 valid = resp_addr + len - 1; 3936 } else { 3937 int j; 3938 3939 /* Check if response len is updated */ 3940 for (i = 0; i < tmo_count; i++) { 3941 len = (le32_to_cpu(*resp_len) & HWRM_RESP_LEN_MASK) >> 3942 HWRM_RESP_LEN_SFT; 3943 if (len) 3944 break; 3945 /* on first few passes, just barely sleep */ 3946 if (i < HWRM_SHORT_TIMEOUT_COUNTER) 3947 usleep_range(HWRM_SHORT_MIN_TIMEOUT, 3948 HWRM_SHORT_MAX_TIMEOUT); 3949 else 3950 usleep_range(HWRM_MIN_TIMEOUT, 3951 HWRM_MAX_TIMEOUT); 3952 } 3953 3954 if (i >= tmo_count) { 3955 netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d\n", 3956 HWRM_TOTAL_TIMEOUT(i), 3957 le16_to_cpu(req->req_type), 3958 le16_to_cpu(req->seq_id), len); 3959 return -1; 3960 } 3961 3962 /* Last byte of resp contains valid bit */ 3963 valid = resp_addr + len - 1; 3964 for (j = 0; j < HWRM_VALID_BIT_DELAY_USEC; j++) { 3965 /* make sure we read from updated DMA memory */ 3966 dma_rmb(); 3967 if (*valid) 3968 break; 3969 usleep_range(1, 5); 3970 } 3971 3972 if (j >= HWRM_VALID_BIT_DELAY_USEC) { 3973 netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d v:%d\n", 3974 HWRM_TOTAL_TIMEOUT(i), 3975 le16_to_cpu(req->req_type), 3976 le16_to_cpu(req->seq_id), len, *valid); 3977 return -1; 3978 } 3979 } 3980 3981 /* Zero valid bit for compatibility. Valid bit in an older spec 3982 * may become a new field in a newer spec. We must make sure that 3983 * a new field not implemented by old spec will read zero. 3984 */ 3985 *valid = 0; 3986 rc = le16_to_cpu(resp->error_code); 3987 if (rc && !silent) 3988 netdev_err(bp->dev, "hwrm req_type 0x%x seq id 0x%x error 0x%x\n", 3989 le16_to_cpu(resp->req_type), 3990 le16_to_cpu(resp->seq_id), rc); 3991 return rc; 3992 } 3993 3994 int _hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout) 3995 { 3996 return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, false); 3997 } 3998 3999 int _hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len, 4000 int timeout) 4001 { 4002 return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true); 4003 } 4004 4005 int hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout) 4006 { 4007 int rc; 4008 4009 mutex_lock(&bp->hwrm_cmd_lock); 4010 rc = _hwrm_send_message(bp, msg, msg_len, timeout); 4011 mutex_unlock(&bp->hwrm_cmd_lock); 4012 return rc; 4013 } 4014 4015 int hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len, 4016 int timeout) 4017 { 4018 int rc; 4019 4020 mutex_lock(&bp->hwrm_cmd_lock); 4021 rc = bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true); 4022 mutex_unlock(&bp->hwrm_cmd_lock); 4023 return rc; 4024 } 4025 4026 int bnxt_hwrm_func_rgtr_async_events(struct bnxt *bp, unsigned long *bmap, 4027 int bmap_size) 4028 { 4029 struct hwrm_func_drv_rgtr_input req = {0}; 4030 DECLARE_BITMAP(async_events_bmap, 256); 4031 u32 *events = (u32 *)async_events_bmap; 4032 int i; 4033 4034 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1); 4035 4036 req.enables = 4037 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD); 4038 4039 memset(async_events_bmap, 0, sizeof(async_events_bmap)); 4040 for (i = 0; i < ARRAY_SIZE(bnxt_async_events_arr); i++) 4041 __set_bit(bnxt_async_events_arr[i], async_events_bmap); 4042 4043 if (bmap && bmap_size) { 4044 for (i = 0; i < bmap_size; i++) { 4045 if (test_bit(i, bmap)) 4046 __set_bit(i, async_events_bmap); 4047 } 4048 } 4049 4050 for (i = 0; i < 8; i++) 4051 req.async_event_fwd[i] |= cpu_to_le32(events[i]); 4052 4053 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4054 } 4055 4056 static int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp) 4057 { 4058 struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr; 4059 struct hwrm_func_drv_rgtr_input req = {0}; 4060 int rc; 4061 4062 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1); 4063 4064 req.enables = 4065 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE | 4066 FUNC_DRV_RGTR_REQ_ENABLES_VER); 4067 4068 req.os_type = cpu_to_le16(FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX); 4069 req.flags = cpu_to_le32(FUNC_DRV_RGTR_REQ_FLAGS_16BIT_VER_MODE); 4070 req.ver_maj_8b = DRV_VER_MAJ; 4071 req.ver_min_8b = DRV_VER_MIN; 4072 req.ver_upd_8b = DRV_VER_UPD; 4073 req.ver_maj = cpu_to_le16(DRV_VER_MAJ); 4074 req.ver_min = cpu_to_le16(DRV_VER_MIN); 4075 req.ver_upd = cpu_to_le16(DRV_VER_UPD); 4076 4077 if (BNXT_PF(bp)) { 4078 u32 data[8]; 4079 int i; 4080 4081 memset(data, 0, sizeof(data)); 4082 for (i = 0; i < ARRAY_SIZE(bnxt_vf_req_snif); i++) { 4083 u16 cmd = bnxt_vf_req_snif[i]; 4084 unsigned int bit, idx; 4085 4086 idx = cmd / 32; 4087 bit = cmd % 32; 4088 data[idx] |= 1 << bit; 4089 } 4090 4091 for (i = 0; i < 8; i++) 4092 req.vf_req_fwd[i] = cpu_to_le32(data[i]); 4093 4094 req.enables |= 4095 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD); 4096 } 4097 4098 if (bp->fw_cap & BNXT_FW_CAP_OVS_64BIT_HANDLE) 4099 req.flags |= cpu_to_le32( 4100 FUNC_DRV_RGTR_REQ_FLAGS_FLOW_HANDLE_64BIT_MODE); 4101 4102 mutex_lock(&bp->hwrm_cmd_lock); 4103 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4104 if (rc) 4105 rc = -EIO; 4106 else if (resp->flags & 4107 cpu_to_le32(FUNC_DRV_RGTR_RESP_FLAGS_IF_CHANGE_SUPPORTED)) 4108 bp->fw_cap |= BNXT_FW_CAP_IF_CHANGE; 4109 mutex_unlock(&bp->hwrm_cmd_lock); 4110 return rc; 4111 } 4112 4113 static int bnxt_hwrm_func_drv_unrgtr(struct bnxt *bp) 4114 { 4115 struct hwrm_func_drv_unrgtr_input req = {0}; 4116 4117 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_UNRGTR, -1, -1); 4118 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4119 } 4120 4121 static int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, u8 tunnel_type) 4122 { 4123 u32 rc = 0; 4124 struct hwrm_tunnel_dst_port_free_input req = {0}; 4125 4126 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_FREE, -1, -1); 4127 req.tunnel_type = tunnel_type; 4128 4129 switch (tunnel_type) { 4130 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN: 4131 req.tunnel_dst_port_id = bp->vxlan_fw_dst_port_id; 4132 break; 4133 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE: 4134 req.tunnel_dst_port_id = bp->nge_fw_dst_port_id; 4135 break; 4136 default: 4137 break; 4138 } 4139 4140 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4141 if (rc) 4142 netdev_err(bp->dev, "hwrm_tunnel_dst_port_free failed. rc:%d\n", 4143 rc); 4144 return rc; 4145 } 4146 4147 static int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, __be16 port, 4148 u8 tunnel_type) 4149 { 4150 u32 rc = 0; 4151 struct hwrm_tunnel_dst_port_alloc_input req = {0}; 4152 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr; 4153 4154 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_ALLOC, -1, -1); 4155 4156 req.tunnel_type = tunnel_type; 4157 req.tunnel_dst_port_val = port; 4158 4159 mutex_lock(&bp->hwrm_cmd_lock); 4160 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4161 if (rc) { 4162 netdev_err(bp->dev, "hwrm_tunnel_dst_port_alloc failed. rc:%d\n", 4163 rc); 4164 goto err_out; 4165 } 4166 4167 switch (tunnel_type) { 4168 case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN: 4169 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id; 4170 break; 4171 case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE: 4172 bp->nge_fw_dst_port_id = resp->tunnel_dst_port_id; 4173 break; 4174 default: 4175 break; 4176 } 4177 4178 err_out: 4179 mutex_unlock(&bp->hwrm_cmd_lock); 4180 return rc; 4181 } 4182 4183 static int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp, u16 vnic_id) 4184 { 4185 struct hwrm_cfa_l2_set_rx_mask_input req = {0}; 4186 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 4187 4188 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_SET_RX_MASK, -1, -1); 4189 req.vnic_id = cpu_to_le32(vnic->fw_vnic_id); 4190 4191 req.num_mc_entries = cpu_to_le32(vnic->mc_list_count); 4192 req.mc_tbl_addr = cpu_to_le64(vnic->mc_list_mapping); 4193 req.mask = cpu_to_le32(vnic->rx_mask); 4194 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4195 } 4196 4197 #ifdef CONFIG_RFS_ACCEL 4198 static int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt *bp, 4199 struct bnxt_ntuple_filter *fltr) 4200 { 4201 struct hwrm_cfa_ntuple_filter_free_input req = {0}; 4202 4203 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_FREE, -1, -1); 4204 req.ntuple_filter_id = fltr->filter_id; 4205 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4206 } 4207 4208 #define BNXT_NTP_FLTR_FLAGS \ 4209 (CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID | \ 4210 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE | \ 4211 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR | \ 4212 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE | \ 4213 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR | \ 4214 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK | \ 4215 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR | \ 4216 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK | \ 4217 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL | \ 4218 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT | \ 4219 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK | \ 4220 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT | \ 4221 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK | \ 4222 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID) 4223 4224 #define BNXT_NTP_TUNNEL_FLTR_FLAG \ 4225 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 4226 4227 static int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt *bp, 4228 struct bnxt_ntuple_filter *fltr) 4229 { 4230 struct hwrm_cfa_ntuple_filter_alloc_input req = {0}; 4231 struct hwrm_cfa_ntuple_filter_alloc_output *resp; 4232 struct flow_keys *keys = &fltr->fkeys; 4233 struct bnxt_vnic_info *vnic; 4234 u32 dst_ena = 0; 4235 int rc = 0; 4236 4237 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_ALLOC, -1, -1); 4238 req.l2_filter_id = bp->vnic_info[0].fw_l2_filter_id[fltr->l2_fltr_idx]; 4239 4240 if (bp->fw_cap & BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX) { 4241 dst_ena = CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_RFS_RING_TBL_IDX; 4242 req.rfs_ring_tbl_idx = cpu_to_le16(fltr->rxq); 4243 vnic = &bp->vnic_info[0]; 4244 } else { 4245 vnic = &bp->vnic_info[fltr->rxq + 1]; 4246 } 4247 req.dst_id = cpu_to_le16(vnic->fw_vnic_id); 4248 req.enables = cpu_to_le32(BNXT_NTP_FLTR_FLAGS | dst_ena); 4249 4250 req.ethertype = htons(ETH_P_IP); 4251 memcpy(req.src_macaddr, fltr->src_mac_addr, ETH_ALEN); 4252 req.ip_addr_type = CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4; 4253 req.ip_protocol = keys->basic.ip_proto; 4254 4255 if (keys->basic.n_proto == htons(ETH_P_IPV6)) { 4256 int i; 4257 4258 req.ethertype = htons(ETH_P_IPV6); 4259 req.ip_addr_type = 4260 CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6; 4261 *(struct in6_addr *)&req.src_ipaddr[0] = 4262 keys->addrs.v6addrs.src; 4263 *(struct in6_addr *)&req.dst_ipaddr[0] = 4264 keys->addrs.v6addrs.dst; 4265 for (i = 0; i < 4; i++) { 4266 req.src_ipaddr_mask[i] = cpu_to_be32(0xffffffff); 4267 req.dst_ipaddr_mask[i] = cpu_to_be32(0xffffffff); 4268 } 4269 } else { 4270 req.src_ipaddr[0] = keys->addrs.v4addrs.src; 4271 req.src_ipaddr_mask[0] = cpu_to_be32(0xffffffff); 4272 req.dst_ipaddr[0] = keys->addrs.v4addrs.dst; 4273 req.dst_ipaddr_mask[0] = cpu_to_be32(0xffffffff); 4274 } 4275 if (keys->control.flags & FLOW_DIS_ENCAPSULATION) { 4276 req.enables |= cpu_to_le32(BNXT_NTP_TUNNEL_FLTR_FLAG); 4277 req.tunnel_type = 4278 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL; 4279 } 4280 4281 req.src_port = keys->ports.src; 4282 req.src_port_mask = cpu_to_be16(0xffff); 4283 req.dst_port = keys->ports.dst; 4284 req.dst_port_mask = cpu_to_be16(0xffff); 4285 4286 mutex_lock(&bp->hwrm_cmd_lock); 4287 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4288 if (!rc) { 4289 resp = bnxt_get_hwrm_resp_addr(bp, &req); 4290 fltr->filter_id = resp->ntuple_filter_id; 4291 } 4292 mutex_unlock(&bp->hwrm_cmd_lock); 4293 return rc; 4294 } 4295 #endif 4296 4297 static int bnxt_hwrm_set_vnic_filter(struct bnxt *bp, u16 vnic_id, u16 idx, 4298 u8 *mac_addr) 4299 { 4300 u32 rc = 0; 4301 struct hwrm_cfa_l2_filter_alloc_input req = {0}; 4302 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr; 4303 4304 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_ALLOC, -1, -1); 4305 req.flags = cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX); 4306 if (!BNXT_CHIP_TYPE_NITRO_A0(bp)) 4307 req.flags |= 4308 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST); 4309 req.dst_id = cpu_to_le16(bp->vnic_info[vnic_id].fw_vnic_id); 4310 req.enables = 4311 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR | 4312 CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID | 4313 CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK); 4314 memcpy(req.l2_addr, mac_addr, ETH_ALEN); 4315 req.l2_addr_mask[0] = 0xff; 4316 req.l2_addr_mask[1] = 0xff; 4317 req.l2_addr_mask[2] = 0xff; 4318 req.l2_addr_mask[3] = 0xff; 4319 req.l2_addr_mask[4] = 0xff; 4320 req.l2_addr_mask[5] = 0xff; 4321 4322 mutex_lock(&bp->hwrm_cmd_lock); 4323 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4324 if (!rc) 4325 bp->vnic_info[vnic_id].fw_l2_filter_id[idx] = 4326 resp->l2_filter_id; 4327 mutex_unlock(&bp->hwrm_cmd_lock); 4328 return rc; 4329 } 4330 4331 static int bnxt_hwrm_clear_vnic_filter(struct bnxt *bp) 4332 { 4333 u16 i, j, num_of_vnics = 1; /* only vnic 0 supported */ 4334 int rc = 0; 4335 4336 /* Any associated ntuple filters will also be cleared by firmware. */ 4337 mutex_lock(&bp->hwrm_cmd_lock); 4338 for (i = 0; i < num_of_vnics; i++) { 4339 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 4340 4341 for (j = 0; j < vnic->uc_filter_count; j++) { 4342 struct hwrm_cfa_l2_filter_free_input req = {0}; 4343 4344 bnxt_hwrm_cmd_hdr_init(bp, &req, 4345 HWRM_CFA_L2_FILTER_FREE, -1, -1); 4346 4347 req.l2_filter_id = vnic->fw_l2_filter_id[j]; 4348 4349 rc = _hwrm_send_message(bp, &req, sizeof(req), 4350 HWRM_CMD_TIMEOUT); 4351 } 4352 vnic->uc_filter_count = 0; 4353 } 4354 mutex_unlock(&bp->hwrm_cmd_lock); 4355 4356 return rc; 4357 } 4358 4359 static int bnxt_hwrm_vnic_set_tpa(struct bnxt *bp, u16 vnic_id, u32 tpa_flags) 4360 { 4361 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 4362 struct hwrm_vnic_tpa_cfg_input req = {0}; 4363 4364 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) 4365 return 0; 4366 4367 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_TPA_CFG, -1, -1); 4368 4369 if (tpa_flags) { 4370 u16 mss = bp->dev->mtu - 40; 4371 u32 nsegs, n, segs = 0, flags; 4372 4373 flags = VNIC_TPA_CFG_REQ_FLAGS_TPA | 4374 VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA | 4375 VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE | 4376 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN | 4377 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ; 4378 if (tpa_flags & BNXT_FLAG_GRO) 4379 flags |= VNIC_TPA_CFG_REQ_FLAGS_GRO; 4380 4381 req.flags = cpu_to_le32(flags); 4382 4383 req.enables = 4384 cpu_to_le32(VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS | 4385 VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS | 4386 VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN); 4387 4388 /* Number of segs are log2 units, and first packet is not 4389 * included as part of this units. 4390 */ 4391 if (mss <= BNXT_RX_PAGE_SIZE) { 4392 n = BNXT_RX_PAGE_SIZE / mss; 4393 nsegs = (MAX_SKB_FRAGS - 1) * n; 4394 } else { 4395 n = mss / BNXT_RX_PAGE_SIZE; 4396 if (mss & (BNXT_RX_PAGE_SIZE - 1)) 4397 n++; 4398 nsegs = (MAX_SKB_FRAGS - n) / n; 4399 } 4400 4401 segs = ilog2(nsegs); 4402 req.max_agg_segs = cpu_to_le16(segs); 4403 req.max_aggs = cpu_to_le16(VNIC_TPA_CFG_REQ_MAX_AGGS_MAX); 4404 4405 req.min_agg_len = cpu_to_le32(512); 4406 } 4407 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id); 4408 4409 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4410 } 4411 4412 static u16 bnxt_cp_ring_from_grp(struct bnxt *bp, struct bnxt_ring_struct *ring) 4413 { 4414 struct bnxt_ring_grp_info *grp_info; 4415 4416 grp_info = &bp->grp_info[ring->grp_idx]; 4417 return grp_info->cp_fw_ring_id; 4418 } 4419 4420 static u16 bnxt_cp_ring_for_rx(struct bnxt *bp, struct bnxt_rx_ring_info *rxr) 4421 { 4422 if (bp->flags & BNXT_FLAG_CHIP_P5) { 4423 struct bnxt_napi *bnapi = rxr->bnapi; 4424 struct bnxt_cp_ring_info *cpr; 4425 4426 cpr = bnapi->cp_ring.cp_ring_arr[BNXT_RX_HDL]; 4427 return cpr->cp_ring_struct.fw_ring_id; 4428 } else { 4429 return bnxt_cp_ring_from_grp(bp, &rxr->rx_ring_struct); 4430 } 4431 } 4432 4433 static u16 bnxt_cp_ring_for_tx(struct bnxt *bp, struct bnxt_tx_ring_info *txr) 4434 { 4435 if (bp->flags & BNXT_FLAG_CHIP_P5) { 4436 struct bnxt_napi *bnapi = txr->bnapi; 4437 struct bnxt_cp_ring_info *cpr; 4438 4439 cpr = bnapi->cp_ring.cp_ring_arr[BNXT_TX_HDL]; 4440 return cpr->cp_ring_struct.fw_ring_id; 4441 } else { 4442 return bnxt_cp_ring_from_grp(bp, &txr->tx_ring_struct); 4443 } 4444 } 4445 4446 static int bnxt_hwrm_vnic_set_rss(struct bnxt *bp, u16 vnic_id, bool set_rss) 4447 { 4448 u32 i, j, max_rings; 4449 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 4450 struct hwrm_vnic_rss_cfg_input req = {0}; 4451 4452 if ((bp->flags & BNXT_FLAG_CHIP_P5) || 4453 vnic->fw_rss_cos_lb_ctx[0] == INVALID_HW_RING_ID) 4454 return 0; 4455 4456 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1); 4457 if (set_rss) { 4458 req.hash_type = cpu_to_le32(bp->rss_hash_cfg); 4459 req.hash_mode_flags = VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT; 4460 if (vnic->flags & BNXT_VNIC_RSS_FLAG) { 4461 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 4462 max_rings = bp->rx_nr_rings - 1; 4463 else 4464 max_rings = bp->rx_nr_rings; 4465 } else { 4466 max_rings = 1; 4467 } 4468 4469 /* Fill the RSS indirection table with ring group ids */ 4470 for (i = 0, j = 0; i < HW_HASH_INDEX_SIZE; i++, j++) { 4471 if (j == max_rings) 4472 j = 0; 4473 vnic->rss_table[i] = cpu_to_le16(vnic->fw_grp_ids[j]); 4474 } 4475 4476 req.ring_grp_tbl_addr = cpu_to_le64(vnic->rss_table_dma_addr); 4477 req.hash_key_tbl_addr = 4478 cpu_to_le64(vnic->rss_hash_key_dma_addr); 4479 } 4480 req.rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]); 4481 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4482 } 4483 4484 static int bnxt_hwrm_vnic_set_rss_p5(struct bnxt *bp, u16 vnic_id, bool set_rss) 4485 { 4486 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 4487 u32 i, j, k, nr_ctxs, max_rings = bp->rx_nr_rings; 4488 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[0]; 4489 struct hwrm_vnic_rss_cfg_input req = {0}; 4490 4491 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1); 4492 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id); 4493 if (!set_rss) { 4494 hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4495 return 0; 4496 } 4497 req.hash_type = cpu_to_le32(bp->rss_hash_cfg); 4498 req.hash_mode_flags = VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT; 4499 req.ring_grp_tbl_addr = cpu_to_le64(vnic->rss_table_dma_addr); 4500 req.hash_key_tbl_addr = cpu_to_le64(vnic->rss_hash_key_dma_addr); 4501 nr_ctxs = DIV_ROUND_UP(bp->rx_nr_rings, 64); 4502 for (i = 0, k = 0; i < nr_ctxs; i++) { 4503 __le16 *ring_tbl = vnic->rss_table; 4504 int rc; 4505 4506 req.ring_table_pair_index = i; 4507 req.rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[i]); 4508 for (j = 0; j < 64; j++) { 4509 u16 ring_id; 4510 4511 ring_id = rxr->rx_ring_struct.fw_ring_id; 4512 *ring_tbl++ = cpu_to_le16(ring_id); 4513 ring_id = bnxt_cp_ring_for_rx(bp, rxr); 4514 *ring_tbl++ = cpu_to_le16(ring_id); 4515 rxr++; 4516 k++; 4517 if (k == max_rings) { 4518 k = 0; 4519 rxr = &bp->rx_ring[0]; 4520 } 4521 } 4522 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4523 if (rc) 4524 return -EIO; 4525 } 4526 return 0; 4527 } 4528 4529 static int bnxt_hwrm_vnic_set_hds(struct bnxt *bp, u16 vnic_id) 4530 { 4531 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 4532 struct hwrm_vnic_plcmodes_cfg_input req = {0}; 4533 4534 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_PLCMODES_CFG, -1, -1); 4535 req.flags = cpu_to_le32(VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT | 4536 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 | 4537 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6); 4538 req.enables = 4539 cpu_to_le32(VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID | 4540 VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID); 4541 /* thresholds not implemented in firmware yet */ 4542 req.jumbo_thresh = cpu_to_le16(bp->rx_copy_thresh); 4543 req.hds_threshold = cpu_to_le16(bp->rx_copy_thresh); 4544 req.vnic_id = cpu_to_le32(vnic->fw_vnic_id); 4545 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4546 } 4547 4548 static void bnxt_hwrm_vnic_ctx_free_one(struct bnxt *bp, u16 vnic_id, 4549 u16 ctx_idx) 4550 { 4551 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {0}; 4552 4553 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, -1, -1); 4554 req.rss_cos_lb_ctx_id = 4555 cpu_to_le16(bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx]); 4556 4557 hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4558 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] = INVALID_HW_RING_ID; 4559 } 4560 4561 static void bnxt_hwrm_vnic_ctx_free(struct bnxt *bp) 4562 { 4563 int i, j; 4564 4565 for (i = 0; i < bp->nr_vnics; i++) { 4566 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 4567 4568 for (j = 0; j < BNXT_MAX_CTX_PER_VNIC; j++) { 4569 if (vnic->fw_rss_cos_lb_ctx[j] != INVALID_HW_RING_ID) 4570 bnxt_hwrm_vnic_ctx_free_one(bp, i, j); 4571 } 4572 } 4573 bp->rsscos_nr_ctxs = 0; 4574 } 4575 4576 static int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, u16 vnic_id, u16 ctx_idx) 4577 { 4578 int rc; 4579 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {0}; 4580 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp = 4581 bp->hwrm_cmd_resp_addr; 4582 4583 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, -1, 4584 -1); 4585 4586 mutex_lock(&bp->hwrm_cmd_lock); 4587 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4588 if (!rc) 4589 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] = 4590 le16_to_cpu(resp->rss_cos_lb_ctx_id); 4591 mutex_unlock(&bp->hwrm_cmd_lock); 4592 4593 return rc; 4594 } 4595 4596 static u32 bnxt_get_roce_vnic_mode(struct bnxt *bp) 4597 { 4598 if (bp->flags & BNXT_FLAG_ROCE_MIRROR_CAP) 4599 return VNIC_CFG_REQ_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE; 4600 return VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE; 4601 } 4602 4603 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id) 4604 { 4605 unsigned int ring = 0, grp_idx; 4606 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 4607 struct hwrm_vnic_cfg_input req = {0}; 4608 u16 def_vlan = 0; 4609 4610 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_CFG, -1, -1); 4611 4612 if (bp->flags & BNXT_FLAG_CHIP_P5) { 4613 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[0]; 4614 4615 req.default_rx_ring_id = 4616 cpu_to_le16(rxr->rx_ring_struct.fw_ring_id); 4617 req.default_cmpl_ring_id = 4618 cpu_to_le16(bnxt_cp_ring_for_rx(bp, rxr)); 4619 req.enables = 4620 cpu_to_le32(VNIC_CFG_REQ_ENABLES_DEFAULT_RX_RING_ID | 4621 VNIC_CFG_REQ_ENABLES_DEFAULT_CMPL_RING_ID); 4622 goto vnic_mru; 4623 } 4624 req.enables = cpu_to_le32(VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP); 4625 /* Only RSS support for now TBD: COS & LB */ 4626 if (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID) { 4627 req.rss_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]); 4628 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE | 4629 VNIC_CFG_REQ_ENABLES_MRU); 4630 } else if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG) { 4631 req.rss_rule = 4632 cpu_to_le16(bp->vnic_info[0].fw_rss_cos_lb_ctx[0]); 4633 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE | 4634 VNIC_CFG_REQ_ENABLES_MRU); 4635 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE); 4636 } else { 4637 req.rss_rule = cpu_to_le16(0xffff); 4638 } 4639 4640 if (BNXT_CHIP_TYPE_NITRO_A0(bp) && 4641 (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID)) { 4642 req.cos_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[1]); 4643 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_COS_RULE); 4644 } else { 4645 req.cos_rule = cpu_to_le16(0xffff); 4646 } 4647 4648 if (vnic->flags & BNXT_VNIC_RSS_FLAG) 4649 ring = 0; 4650 else if (vnic->flags & BNXT_VNIC_RFS_FLAG) 4651 ring = vnic_id - 1; 4652 else if ((vnic_id == 1) && BNXT_CHIP_TYPE_NITRO_A0(bp)) 4653 ring = bp->rx_nr_rings - 1; 4654 4655 grp_idx = bp->rx_ring[ring].bnapi->index; 4656 req.dflt_ring_grp = cpu_to_le16(bp->grp_info[grp_idx].fw_grp_id); 4657 req.lb_rule = cpu_to_le16(0xffff); 4658 vnic_mru: 4659 req.mru = cpu_to_le16(bp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + 4660 VLAN_HLEN); 4661 4662 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id); 4663 #ifdef CONFIG_BNXT_SRIOV 4664 if (BNXT_VF(bp)) 4665 def_vlan = bp->vf.vlan; 4666 #endif 4667 if ((bp->flags & BNXT_FLAG_STRIP_VLAN) || def_vlan) 4668 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE); 4669 if (!vnic_id && bnxt_ulp_registered(bp->edev, BNXT_ROCE_ULP)) 4670 req.flags |= cpu_to_le32(bnxt_get_roce_vnic_mode(bp)); 4671 4672 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4673 } 4674 4675 static int bnxt_hwrm_vnic_free_one(struct bnxt *bp, u16 vnic_id) 4676 { 4677 u32 rc = 0; 4678 4679 if (bp->vnic_info[vnic_id].fw_vnic_id != INVALID_HW_RING_ID) { 4680 struct hwrm_vnic_free_input req = {0}; 4681 4682 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_FREE, -1, -1); 4683 req.vnic_id = 4684 cpu_to_le32(bp->vnic_info[vnic_id].fw_vnic_id); 4685 4686 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4687 if (rc) 4688 return rc; 4689 bp->vnic_info[vnic_id].fw_vnic_id = INVALID_HW_RING_ID; 4690 } 4691 return rc; 4692 } 4693 4694 static void bnxt_hwrm_vnic_free(struct bnxt *bp) 4695 { 4696 u16 i; 4697 4698 for (i = 0; i < bp->nr_vnics; i++) 4699 bnxt_hwrm_vnic_free_one(bp, i); 4700 } 4701 4702 static int bnxt_hwrm_vnic_alloc(struct bnxt *bp, u16 vnic_id, 4703 unsigned int start_rx_ring_idx, 4704 unsigned int nr_rings) 4705 { 4706 int rc = 0; 4707 unsigned int i, j, grp_idx, end_idx = start_rx_ring_idx + nr_rings; 4708 struct hwrm_vnic_alloc_input req = {0}; 4709 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr; 4710 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 4711 4712 if (bp->flags & BNXT_FLAG_CHIP_P5) 4713 goto vnic_no_ring_grps; 4714 4715 /* map ring groups to this vnic */ 4716 for (i = start_rx_ring_idx, j = 0; i < end_idx; i++, j++) { 4717 grp_idx = bp->rx_ring[i].bnapi->index; 4718 if (bp->grp_info[grp_idx].fw_grp_id == INVALID_HW_RING_ID) { 4719 netdev_err(bp->dev, "Not enough ring groups avail:%x req:%x\n", 4720 j, nr_rings); 4721 break; 4722 } 4723 vnic->fw_grp_ids[j] = bp->grp_info[grp_idx].fw_grp_id; 4724 } 4725 4726 vnic_no_ring_grps: 4727 for (i = 0; i < BNXT_MAX_CTX_PER_VNIC; i++) 4728 vnic->fw_rss_cos_lb_ctx[i] = INVALID_HW_RING_ID; 4729 if (vnic_id == 0) 4730 req.flags = cpu_to_le32(VNIC_ALLOC_REQ_FLAGS_DEFAULT); 4731 4732 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_ALLOC, -1, -1); 4733 4734 mutex_lock(&bp->hwrm_cmd_lock); 4735 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4736 if (!rc) 4737 vnic->fw_vnic_id = le32_to_cpu(resp->vnic_id); 4738 mutex_unlock(&bp->hwrm_cmd_lock); 4739 return rc; 4740 } 4741 4742 static int bnxt_hwrm_vnic_qcaps(struct bnxt *bp) 4743 { 4744 struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr; 4745 struct hwrm_vnic_qcaps_input req = {0}; 4746 int rc; 4747 4748 if (bp->hwrm_spec_code < 0x10600) 4749 return 0; 4750 4751 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_QCAPS, -1, -1); 4752 mutex_lock(&bp->hwrm_cmd_lock); 4753 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4754 if (!rc) { 4755 u32 flags = le32_to_cpu(resp->flags); 4756 4757 if (!(bp->flags & BNXT_FLAG_CHIP_P5) && 4758 (flags & VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP)) 4759 bp->flags |= BNXT_FLAG_NEW_RSS_CAP; 4760 if (flags & 4761 VNIC_QCAPS_RESP_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP) 4762 bp->flags |= BNXT_FLAG_ROCE_MIRROR_CAP; 4763 } 4764 mutex_unlock(&bp->hwrm_cmd_lock); 4765 return rc; 4766 } 4767 4768 static int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp) 4769 { 4770 u16 i; 4771 u32 rc = 0; 4772 4773 if (bp->flags & BNXT_FLAG_CHIP_P5) 4774 return 0; 4775 4776 mutex_lock(&bp->hwrm_cmd_lock); 4777 for (i = 0; i < bp->rx_nr_rings; i++) { 4778 struct hwrm_ring_grp_alloc_input req = {0}; 4779 struct hwrm_ring_grp_alloc_output *resp = 4780 bp->hwrm_cmd_resp_addr; 4781 unsigned int grp_idx = bp->rx_ring[i].bnapi->index; 4782 4783 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_ALLOC, -1, -1); 4784 4785 req.cr = cpu_to_le16(bp->grp_info[grp_idx].cp_fw_ring_id); 4786 req.rr = cpu_to_le16(bp->grp_info[grp_idx].rx_fw_ring_id); 4787 req.ar = cpu_to_le16(bp->grp_info[grp_idx].agg_fw_ring_id); 4788 req.sc = cpu_to_le16(bp->grp_info[grp_idx].fw_stats_ctx); 4789 4790 rc = _hwrm_send_message(bp, &req, sizeof(req), 4791 HWRM_CMD_TIMEOUT); 4792 if (rc) 4793 break; 4794 4795 bp->grp_info[grp_idx].fw_grp_id = 4796 le32_to_cpu(resp->ring_group_id); 4797 } 4798 mutex_unlock(&bp->hwrm_cmd_lock); 4799 return rc; 4800 } 4801 4802 static int bnxt_hwrm_ring_grp_free(struct bnxt *bp) 4803 { 4804 u16 i; 4805 u32 rc = 0; 4806 struct hwrm_ring_grp_free_input req = {0}; 4807 4808 if (!bp->grp_info || (bp->flags & BNXT_FLAG_CHIP_P5)) 4809 return 0; 4810 4811 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_FREE, -1, -1); 4812 4813 mutex_lock(&bp->hwrm_cmd_lock); 4814 for (i = 0; i < bp->cp_nr_rings; i++) { 4815 if (bp->grp_info[i].fw_grp_id == INVALID_HW_RING_ID) 4816 continue; 4817 req.ring_group_id = 4818 cpu_to_le32(bp->grp_info[i].fw_grp_id); 4819 4820 rc = _hwrm_send_message(bp, &req, sizeof(req), 4821 HWRM_CMD_TIMEOUT); 4822 if (rc) 4823 break; 4824 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID; 4825 } 4826 mutex_unlock(&bp->hwrm_cmd_lock); 4827 return rc; 4828 } 4829 4830 static int hwrm_ring_alloc_send_msg(struct bnxt *bp, 4831 struct bnxt_ring_struct *ring, 4832 u32 ring_type, u32 map_index) 4833 { 4834 int rc = 0, err = 0; 4835 struct hwrm_ring_alloc_input req = {0}; 4836 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr; 4837 struct bnxt_ring_mem_info *rmem = &ring->ring_mem; 4838 struct bnxt_ring_grp_info *grp_info; 4839 u16 ring_id; 4840 4841 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_ALLOC, -1, -1); 4842 4843 req.enables = 0; 4844 if (rmem->nr_pages > 1) { 4845 req.page_tbl_addr = cpu_to_le64(rmem->pg_tbl_map); 4846 /* Page size is in log2 units */ 4847 req.page_size = BNXT_PAGE_SHIFT; 4848 req.page_tbl_depth = 1; 4849 } else { 4850 req.page_tbl_addr = cpu_to_le64(rmem->dma_arr[0]); 4851 } 4852 req.fbo = 0; 4853 /* Association of ring index with doorbell index and MSIX number */ 4854 req.logical_id = cpu_to_le16(map_index); 4855 4856 switch (ring_type) { 4857 case HWRM_RING_ALLOC_TX: { 4858 struct bnxt_tx_ring_info *txr; 4859 4860 txr = container_of(ring, struct bnxt_tx_ring_info, 4861 tx_ring_struct); 4862 req.ring_type = RING_ALLOC_REQ_RING_TYPE_TX; 4863 /* Association of transmit ring with completion ring */ 4864 grp_info = &bp->grp_info[ring->grp_idx]; 4865 req.cmpl_ring_id = cpu_to_le16(bnxt_cp_ring_for_tx(bp, txr)); 4866 req.length = cpu_to_le32(bp->tx_ring_mask + 1); 4867 req.stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx); 4868 req.queue_id = cpu_to_le16(ring->queue_id); 4869 break; 4870 } 4871 case HWRM_RING_ALLOC_RX: 4872 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX; 4873 req.length = cpu_to_le32(bp->rx_ring_mask + 1); 4874 if (bp->flags & BNXT_FLAG_CHIP_P5) { 4875 u16 flags = 0; 4876 4877 /* Association of rx ring with stats context */ 4878 grp_info = &bp->grp_info[ring->grp_idx]; 4879 req.rx_buf_size = cpu_to_le16(bp->rx_buf_use_size); 4880 req.stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx); 4881 req.enables |= cpu_to_le32( 4882 RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID); 4883 if (NET_IP_ALIGN == 2) 4884 flags = RING_ALLOC_REQ_FLAGS_RX_SOP_PAD; 4885 req.flags = cpu_to_le16(flags); 4886 } 4887 break; 4888 case HWRM_RING_ALLOC_AGG: 4889 if (bp->flags & BNXT_FLAG_CHIP_P5) { 4890 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX_AGG; 4891 /* Association of agg ring with rx ring */ 4892 grp_info = &bp->grp_info[ring->grp_idx]; 4893 req.rx_ring_id = cpu_to_le16(grp_info->rx_fw_ring_id); 4894 req.rx_buf_size = cpu_to_le16(BNXT_RX_PAGE_SIZE); 4895 req.stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx); 4896 req.enables |= cpu_to_le32( 4897 RING_ALLOC_REQ_ENABLES_RX_RING_ID_VALID | 4898 RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID); 4899 } else { 4900 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX; 4901 } 4902 req.length = cpu_to_le32(bp->rx_agg_ring_mask + 1); 4903 break; 4904 case HWRM_RING_ALLOC_CMPL: 4905 req.ring_type = RING_ALLOC_REQ_RING_TYPE_L2_CMPL; 4906 req.length = cpu_to_le32(bp->cp_ring_mask + 1); 4907 if (bp->flags & BNXT_FLAG_CHIP_P5) { 4908 /* Association of cp ring with nq */ 4909 grp_info = &bp->grp_info[map_index]; 4910 req.nq_ring_id = cpu_to_le16(grp_info->cp_fw_ring_id); 4911 req.cq_handle = cpu_to_le64(ring->handle); 4912 req.enables |= cpu_to_le32( 4913 RING_ALLOC_REQ_ENABLES_NQ_RING_ID_VALID); 4914 } else if (bp->flags & BNXT_FLAG_USING_MSIX) { 4915 req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX; 4916 } 4917 break; 4918 case HWRM_RING_ALLOC_NQ: 4919 req.ring_type = RING_ALLOC_REQ_RING_TYPE_NQ; 4920 req.length = cpu_to_le32(bp->cp_ring_mask + 1); 4921 if (bp->flags & BNXT_FLAG_USING_MSIX) 4922 req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX; 4923 break; 4924 default: 4925 netdev_err(bp->dev, "hwrm alloc invalid ring type %d\n", 4926 ring_type); 4927 return -1; 4928 } 4929 4930 mutex_lock(&bp->hwrm_cmd_lock); 4931 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4932 err = le16_to_cpu(resp->error_code); 4933 ring_id = le16_to_cpu(resp->ring_id); 4934 mutex_unlock(&bp->hwrm_cmd_lock); 4935 4936 if (rc || err) { 4937 netdev_err(bp->dev, "hwrm_ring_alloc type %d failed. rc:%x err:%x\n", 4938 ring_type, rc, err); 4939 return -EIO; 4940 } 4941 ring->fw_ring_id = ring_id; 4942 return rc; 4943 } 4944 4945 static int bnxt_hwrm_set_async_event_cr(struct bnxt *bp, int idx) 4946 { 4947 int rc; 4948 4949 if (BNXT_PF(bp)) { 4950 struct hwrm_func_cfg_input req = {0}; 4951 4952 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1); 4953 req.fid = cpu_to_le16(0xffff); 4954 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR); 4955 req.async_event_cr = cpu_to_le16(idx); 4956 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4957 } else { 4958 struct hwrm_func_vf_cfg_input req = {0}; 4959 4960 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_VF_CFG, -1, -1); 4961 req.enables = 4962 cpu_to_le32(FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR); 4963 req.async_event_cr = cpu_to_le16(idx); 4964 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4965 } 4966 return rc; 4967 } 4968 4969 static void bnxt_set_db(struct bnxt *bp, struct bnxt_db_info *db, u32 ring_type, 4970 u32 map_idx, u32 xid) 4971 { 4972 if (bp->flags & BNXT_FLAG_CHIP_P5) { 4973 if (BNXT_PF(bp)) 4974 db->doorbell = bp->bar1 + 0x10000; 4975 else 4976 db->doorbell = bp->bar1 + 0x4000; 4977 switch (ring_type) { 4978 case HWRM_RING_ALLOC_TX: 4979 db->db_key64 = DBR_PATH_L2 | DBR_TYPE_SQ; 4980 break; 4981 case HWRM_RING_ALLOC_RX: 4982 case HWRM_RING_ALLOC_AGG: 4983 db->db_key64 = DBR_PATH_L2 | DBR_TYPE_SRQ; 4984 break; 4985 case HWRM_RING_ALLOC_CMPL: 4986 db->db_key64 = DBR_PATH_L2; 4987 break; 4988 case HWRM_RING_ALLOC_NQ: 4989 db->db_key64 = DBR_PATH_L2; 4990 break; 4991 } 4992 db->db_key64 |= (u64)xid << DBR_XID_SFT; 4993 } else { 4994 db->doorbell = bp->bar1 + map_idx * 0x80; 4995 switch (ring_type) { 4996 case HWRM_RING_ALLOC_TX: 4997 db->db_key32 = DB_KEY_TX; 4998 break; 4999 case HWRM_RING_ALLOC_RX: 5000 case HWRM_RING_ALLOC_AGG: 5001 db->db_key32 = DB_KEY_RX; 5002 break; 5003 case HWRM_RING_ALLOC_CMPL: 5004 db->db_key32 = DB_KEY_CP; 5005 break; 5006 } 5007 } 5008 } 5009 5010 static int bnxt_hwrm_ring_alloc(struct bnxt *bp) 5011 { 5012 int i, rc = 0; 5013 u32 type; 5014 5015 if (bp->flags & BNXT_FLAG_CHIP_P5) 5016 type = HWRM_RING_ALLOC_NQ; 5017 else 5018 type = HWRM_RING_ALLOC_CMPL; 5019 for (i = 0; i < bp->cp_nr_rings; i++) { 5020 struct bnxt_napi *bnapi = bp->bnapi[i]; 5021 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 5022 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct; 5023 u32 map_idx = ring->map_idx; 5024 unsigned int vector; 5025 5026 vector = bp->irq_tbl[map_idx].vector; 5027 disable_irq_nosync(vector); 5028 rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx); 5029 if (rc) { 5030 enable_irq(vector); 5031 goto err_out; 5032 } 5033 bnxt_set_db(bp, &cpr->cp_db, type, map_idx, ring->fw_ring_id); 5034 bnxt_db_nq(bp, &cpr->cp_db, cpr->cp_raw_cons); 5035 enable_irq(vector); 5036 bp->grp_info[i].cp_fw_ring_id = ring->fw_ring_id; 5037 5038 if (!i) { 5039 rc = bnxt_hwrm_set_async_event_cr(bp, ring->fw_ring_id); 5040 if (rc) 5041 netdev_warn(bp->dev, "Failed to set async event completion ring.\n"); 5042 } 5043 } 5044 5045 type = HWRM_RING_ALLOC_TX; 5046 for (i = 0; i < bp->tx_nr_rings; i++) { 5047 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; 5048 struct bnxt_ring_struct *ring; 5049 u32 map_idx; 5050 5051 if (bp->flags & BNXT_FLAG_CHIP_P5) { 5052 struct bnxt_napi *bnapi = txr->bnapi; 5053 struct bnxt_cp_ring_info *cpr, *cpr2; 5054 u32 type2 = HWRM_RING_ALLOC_CMPL; 5055 5056 cpr = &bnapi->cp_ring; 5057 cpr2 = cpr->cp_ring_arr[BNXT_TX_HDL]; 5058 ring = &cpr2->cp_ring_struct; 5059 ring->handle = BNXT_TX_HDL; 5060 map_idx = bnapi->index; 5061 rc = hwrm_ring_alloc_send_msg(bp, ring, type2, map_idx); 5062 if (rc) 5063 goto err_out; 5064 bnxt_set_db(bp, &cpr2->cp_db, type2, map_idx, 5065 ring->fw_ring_id); 5066 bnxt_db_cq(bp, &cpr2->cp_db, cpr2->cp_raw_cons); 5067 } 5068 ring = &txr->tx_ring_struct; 5069 map_idx = i; 5070 rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx); 5071 if (rc) 5072 goto err_out; 5073 bnxt_set_db(bp, &txr->tx_db, type, map_idx, ring->fw_ring_id); 5074 } 5075 5076 type = HWRM_RING_ALLOC_RX; 5077 for (i = 0; i < bp->rx_nr_rings; i++) { 5078 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 5079 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct; 5080 struct bnxt_napi *bnapi = rxr->bnapi; 5081 u32 map_idx = bnapi->index; 5082 5083 rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx); 5084 if (rc) 5085 goto err_out; 5086 bnxt_set_db(bp, &rxr->rx_db, type, map_idx, ring->fw_ring_id); 5087 bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod); 5088 bp->grp_info[map_idx].rx_fw_ring_id = ring->fw_ring_id; 5089 if (bp->flags & BNXT_FLAG_CHIP_P5) { 5090 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 5091 u32 type2 = HWRM_RING_ALLOC_CMPL; 5092 struct bnxt_cp_ring_info *cpr2; 5093 5094 cpr2 = cpr->cp_ring_arr[BNXT_RX_HDL]; 5095 ring = &cpr2->cp_ring_struct; 5096 ring->handle = BNXT_RX_HDL; 5097 rc = hwrm_ring_alloc_send_msg(bp, ring, type2, map_idx); 5098 if (rc) 5099 goto err_out; 5100 bnxt_set_db(bp, &cpr2->cp_db, type2, map_idx, 5101 ring->fw_ring_id); 5102 bnxt_db_cq(bp, &cpr2->cp_db, cpr2->cp_raw_cons); 5103 } 5104 } 5105 5106 if (bp->flags & BNXT_FLAG_AGG_RINGS) { 5107 type = HWRM_RING_ALLOC_AGG; 5108 for (i = 0; i < bp->rx_nr_rings; i++) { 5109 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 5110 struct bnxt_ring_struct *ring = 5111 &rxr->rx_agg_ring_struct; 5112 u32 grp_idx = ring->grp_idx; 5113 u32 map_idx = grp_idx + bp->rx_nr_rings; 5114 5115 rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx); 5116 if (rc) 5117 goto err_out; 5118 5119 bnxt_set_db(bp, &rxr->rx_agg_db, type, map_idx, 5120 ring->fw_ring_id); 5121 bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod); 5122 bp->grp_info[grp_idx].agg_fw_ring_id = ring->fw_ring_id; 5123 } 5124 } 5125 err_out: 5126 return rc; 5127 } 5128 5129 static int hwrm_ring_free_send_msg(struct bnxt *bp, 5130 struct bnxt_ring_struct *ring, 5131 u32 ring_type, int cmpl_ring_id) 5132 { 5133 int rc; 5134 struct hwrm_ring_free_input req = {0}; 5135 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr; 5136 u16 error_code; 5137 5138 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_FREE, cmpl_ring_id, -1); 5139 req.ring_type = ring_type; 5140 req.ring_id = cpu_to_le16(ring->fw_ring_id); 5141 5142 mutex_lock(&bp->hwrm_cmd_lock); 5143 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5144 error_code = le16_to_cpu(resp->error_code); 5145 mutex_unlock(&bp->hwrm_cmd_lock); 5146 5147 if (rc || error_code) { 5148 netdev_err(bp->dev, "hwrm_ring_free type %d failed. rc:%x err:%x\n", 5149 ring_type, rc, error_code); 5150 return -EIO; 5151 } 5152 return 0; 5153 } 5154 5155 static void bnxt_hwrm_ring_free(struct bnxt *bp, bool close_path) 5156 { 5157 u32 type; 5158 int i; 5159 5160 if (!bp->bnapi) 5161 return; 5162 5163 for (i = 0; i < bp->tx_nr_rings; i++) { 5164 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; 5165 struct bnxt_ring_struct *ring = &txr->tx_ring_struct; 5166 5167 if (ring->fw_ring_id != INVALID_HW_RING_ID) { 5168 u32 cmpl_ring_id = bnxt_cp_ring_for_tx(bp, txr); 5169 5170 hwrm_ring_free_send_msg(bp, ring, 5171 RING_FREE_REQ_RING_TYPE_TX, 5172 close_path ? cmpl_ring_id : 5173 INVALID_HW_RING_ID); 5174 ring->fw_ring_id = INVALID_HW_RING_ID; 5175 } 5176 } 5177 5178 for (i = 0; i < bp->rx_nr_rings; i++) { 5179 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 5180 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct; 5181 u32 grp_idx = rxr->bnapi->index; 5182 5183 if (ring->fw_ring_id != INVALID_HW_RING_ID) { 5184 u32 cmpl_ring_id = bnxt_cp_ring_for_rx(bp, rxr); 5185 5186 hwrm_ring_free_send_msg(bp, ring, 5187 RING_FREE_REQ_RING_TYPE_RX, 5188 close_path ? cmpl_ring_id : 5189 INVALID_HW_RING_ID); 5190 ring->fw_ring_id = INVALID_HW_RING_ID; 5191 bp->grp_info[grp_idx].rx_fw_ring_id = 5192 INVALID_HW_RING_ID; 5193 } 5194 } 5195 5196 if (bp->flags & BNXT_FLAG_CHIP_P5) 5197 type = RING_FREE_REQ_RING_TYPE_RX_AGG; 5198 else 5199 type = RING_FREE_REQ_RING_TYPE_RX; 5200 for (i = 0; i < bp->rx_nr_rings; i++) { 5201 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 5202 struct bnxt_ring_struct *ring = &rxr->rx_agg_ring_struct; 5203 u32 grp_idx = rxr->bnapi->index; 5204 5205 if (ring->fw_ring_id != INVALID_HW_RING_ID) { 5206 u32 cmpl_ring_id = bnxt_cp_ring_for_rx(bp, rxr); 5207 5208 hwrm_ring_free_send_msg(bp, ring, type, 5209 close_path ? cmpl_ring_id : 5210 INVALID_HW_RING_ID); 5211 ring->fw_ring_id = INVALID_HW_RING_ID; 5212 bp->grp_info[grp_idx].agg_fw_ring_id = 5213 INVALID_HW_RING_ID; 5214 } 5215 } 5216 5217 /* The completion rings are about to be freed. After that the 5218 * IRQ doorbell will not work anymore. So we need to disable 5219 * IRQ here. 5220 */ 5221 bnxt_disable_int_sync(bp); 5222 5223 if (bp->flags & BNXT_FLAG_CHIP_P5) 5224 type = RING_FREE_REQ_RING_TYPE_NQ; 5225 else 5226 type = RING_FREE_REQ_RING_TYPE_L2_CMPL; 5227 for (i = 0; i < bp->cp_nr_rings; i++) { 5228 struct bnxt_napi *bnapi = bp->bnapi[i]; 5229 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 5230 struct bnxt_ring_struct *ring; 5231 int j; 5232 5233 for (j = 0; j < 2; j++) { 5234 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j]; 5235 5236 if (cpr2) { 5237 ring = &cpr2->cp_ring_struct; 5238 if (ring->fw_ring_id == INVALID_HW_RING_ID) 5239 continue; 5240 hwrm_ring_free_send_msg(bp, ring, 5241 RING_FREE_REQ_RING_TYPE_L2_CMPL, 5242 INVALID_HW_RING_ID); 5243 ring->fw_ring_id = INVALID_HW_RING_ID; 5244 } 5245 } 5246 ring = &cpr->cp_ring_struct; 5247 if (ring->fw_ring_id != INVALID_HW_RING_ID) { 5248 hwrm_ring_free_send_msg(bp, ring, type, 5249 INVALID_HW_RING_ID); 5250 ring->fw_ring_id = INVALID_HW_RING_ID; 5251 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID; 5252 } 5253 } 5254 } 5255 5256 static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max, 5257 bool shared); 5258 5259 static int bnxt_hwrm_get_rings(struct bnxt *bp) 5260 { 5261 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr; 5262 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 5263 struct hwrm_func_qcfg_input req = {0}; 5264 int rc; 5265 5266 if (bp->hwrm_spec_code < 0x10601) 5267 return 0; 5268 5269 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1); 5270 req.fid = cpu_to_le16(0xffff); 5271 mutex_lock(&bp->hwrm_cmd_lock); 5272 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5273 if (rc) { 5274 mutex_unlock(&bp->hwrm_cmd_lock); 5275 return -EIO; 5276 } 5277 5278 hw_resc->resv_tx_rings = le16_to_cpu(resp->alloc_tx_rings); 5279 if (BNXT_NEW_RM(bp)) { 5280 u16 cp, stats; 5281 5282 hw_resc->resv_rx_rings = le16_to_cpu(resp->alloc_rx_rings); 5283 hw_resc->resv_hw_ring_grps = 5284 le32_to_cpu(resp->alloc_hw_ring_grps); 5285 hw_resc->resv_vnics = le16_to_cpu(resp->alloc_vnics); 5286 cp = le16_to_cpu(resp->alloc_cmpl_rings); 5287 stats = le16_to_cpu(resp->alloc_stat_ctx); 5288 hw_resc->resv_irqs = cp; 5289 if (bp->flags & BNXT_FLAG_CHIP_P5) { 5290 int rx = hw_resc->resv_rx_rings; 5291 int tx = hw_resc->resv_tx_rings; 5292 5293 if (bp->flags & BNXT_FLAG_AGG_RINGS) 5294 rx >>= 1; 5295 if (cp < (rx + tx)) { 5296 bnxt_trim_rings(bp, &rx, &tx, cp, false); 5297 if (bp->flags & BNXT_FLAG_AGG_RINGS) 5298 rx <<= 1; 5299 hw_resc->resv_rx_rings = rx; 5300 hw_resc->resv_tx_rings = tx; 5301 } 5302 hw_resc->resv_irqs = le16_to_cpu(resp->alloc_msix); 5303 hw_resc->resv_hw_ring_grps = rx; 5304 } 5305 hw_resc->resv_cp_rings = cp; 5306 hw_resc->resv_stat_ctxs = stats; 5307 } 5308 mutex_unlock(&bp->hwrm_cmd_lock); 5309 return 0; 5310 } 5311 5312 /* Caller must hold bp->hwrm_cmd_lock */ 5313 int __bnxt_hwrm_get_tx_rings(struct bnxt *bp, u16 fid, int *tx_rings) 5314 { 5315 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr; 5316 struct hwrm_func_qcfg_input req = {0}; 5317 int rc; 5318 5319 if (bp->hwrm_spec_code < 0x10601) 5320 return 0; 5321 5322 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1); 5323 req.fid = cpu_to_le16(fid); 5324 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5325 if (!rc) 5326 *tx_rings = le16_to_cpu(resp->alloc_tx_rings); 5327 5328 return rc; 5329 } 5330 5331 static bool bnxt_rfs_supported(struct bnxt *bp); 5332 5333 static void 5334 __bnxt_hwrm_reserve_pf_rings(struct bnxt *bp, struct hwrm_func_cfg_input *req, 5335 int tx_rings, int rx_rings, int ring_grps, 5336 int cp_rings, int stats, int vnics) 5337 { 5338 u32 enables = 0; 5339 5340 bnxt_hwrm_cmd_hdr_init(bp, req, HWRM_FUNC_CFG, -1, -1); 5341 req->fid = cpu_to_le16(0xffff); 5342 enables |= tx_rings ? FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS : 0; 5343 req->num_tx_rings = cpu_to_le16(tx_rings); 5344 if (BNXT_NEW_RM(bp)) { 5345 enables |= rx_rings ? FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS : 0; 5346 enables |= stats ? FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0; 5347 if (bp->flags & BNXT_FLAG_CHIP_P5) { 5348 enables |= cp_rings ? FUNC_CFG_REQ_ENABLES_NUM_MSIX : 0; 5349 enables |= tx_rings + ring_grps ? 5350 FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0; 5351 enables |= rx_rings ? 5352 FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0; 5353 } else { 5354 enables |= cp_rings ? 5355 FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0; 5356 enables |= ring_grps ? 5357 FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS | 5358 FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0; 5359 } 5360 enables |= vnics ? FUNC_CFG_REQ_ENABLES_NUM_VNICS : 0; 5361 5362 req->num_rx_rings = cpu_to_le16(rx_rings); 5363 if (bp->flags & BNXT_FLAG_CHIP_P5) { 5364 req->num_cmpl_rings = cpu_to_le16(tx_rings + ring_grps); 5365 req->num_msix = cpu_to_le16(cp_rings); 5366 req->num_rsscos_ctxs = 5367 cpu_to_le16(DIV_ROUND_UP(ring_grps, 64)); 5368 } else { 5369 req->num_cmpl_rings = cpu_to_le16(cp_rings); 5370 req->num_hw_ring_grps = cpu_to_le16(ring_grps); 5371 req->num_rsscos_ctxs = cpu_to_le16(1); 5372 if (!(bp->flags & BNXT_FLAG_NEW_RSS_CAP) && 5373 bnxt_rfs_supported(bp)) 5374 req->num_rsscos_ctxs = 5375 cpu_to_le16(ring_grps + 1); 5376 } 5377 req->num_stat_ctxs = cpu_to_le16(stats); 5378 req->num_vnics = cpu_to_le16(vnics); 5379 } 5380 req->enables = cpu_to_le32(enables); 5381 } 5382 5383 static void 5384 __bnxt_hwrm_reserve_vf_rings(struct bnxt *bp, 5385 struct hwrm_func_vf_cfg_input *req, int tx_rings, 5386 int rx_rings, int ring_grps, int cp_rings, 5387 int stats, int vnics) 5388 { 5389 u32 enables = 0; 5390 5391 bnxt_hwrm_cmd_hdr_init(bp, req, HWRM_FUNC_VF_CFG, -1, -1); 5392 enables |= tx_rings ? FUNC_VF_CFG_REQ_ENABLES_NUM_TX_RINGS : 0; 5393 enables |= rx_rings ? FUNC_VF_CFG_REQ_ENABLES_NUM_RX_RINGS | 5394 FUNC_VF_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0; 5395 enables |= stats ? FUNC_VF_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0; 5396 if (bp->flags & BNXT_FLAG_CHIP_P5) { 5397 enables |= tx_rings + ring_grps ? 5398 FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0; 5399 } else { 5400 enables |= cp_rings ? 5401 FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0; 5402 enables |= ring_grps ? 5403 FUNC_VF_CFG_REQ_ENABLES_NUM_HW_RING_GRPS : 0; 5404 } 5405 enables |= vnics ? FUNC_VF_CFG_REQ_ENABLES_NUM_VNICS : 0; 5406 enables |= FUNC_VF_CFG_REQ_ENABLES_NUM_L2_CTXS; 5407 5408 req->num_l2_ctxs = cpu_to_le16(BNXT_VF_MAX_L2_CTX); 5409 req->num_tx_rings = cpu_to_le16(tx_rings); 5410 req->num_rx_rings = cpu_to_le16(rx_rings); 5411 if (bp->flags & BNXT_FLAG_CHIP_P5) { 5412 req->num_cmpl_rings = cpu_to_le16(tx_rings + ring_grps); 5413 req->num_rsscos_ctxs = cpu_to_le16(DIV_ROUND_UP(ring_grps, 64)); 5414 } else { 5415 req->num_cmpl_rings = cpu_to_le16(cp_rings); 5416 req->num_hw_ring_grps = cpu_to_le16(ring_grps); 5417 req->num_rsscos_ctxs = cpu_to_le16(BNXT_VF_MAX_RSS_CTX); 5418 } 5419 req->num_stat_ctxs = cpu_to_le16(stats); 5420 req->num_vnics = cpu_to_le16(vnics); 5421 5422 req->enables = cpu_to_le32(enables); 5423 } 5424 5425 static int 5426 bnxt_hwrm_reserve_pf_rings(struct bnxt *bp, int tx_rings, int rx_rings, 5427 int ring_grps, int cp_rings, int stats, int vnics) 5428 { 5429 struct hwrm_func_cfg_input req = {0}; 5430 int rc; 5431 5432 __bnxt_hwrm_reserve_pf_rings(bp, &req, tx_rings, rx_rings, ring_grps, 5433 cp_rings, stats, vnics); 5434 if (!req.enables) 5435 return 0; 5436 5437 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5438 if (rc) 5439 return -ENOMEM; 5440 5441 if (bp->hwrm_spec_code < 0x10601) 5442 bp->hw_resc.resv_tx_rings = tx_rings; 5443 5444 rc = bnxt_hwrm_get_rings(bp); 5445 return rc; 5446 } 5447 5448 static int 5449 bnxt_hwrm_reserve_vf_rings(struct bnxt *bp, int tx_rings, int rx_rings, 5450 int ring_grps, int cp_rings, int stats, int vnics) 5451 { 5452 struct hwrm_func_vf_cfg_input req = {0}; 5453 int rc; 5454 5455 if (!BNXT_NEW_RM(bp)) { 5456 bp->hw_resc.resv_tx_rings = tx_rings; 5457 return 0; 5458 } 5459 5460 __bnxt_hwrm_reserve_vf_rings(bp, &req, tx_rings, rx_rings, ring_grps, 5461 cp_rings, stats, vnics); 5462 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5463 if (rc) 5464 return -ENOMEM; 5465 5466 rc = bnxt_hwrm_get_rings(bp); 5467 return rc; 5468 } 5469 5470 static int bnxt_hwrm_reserve_rings(struct bnxt *bp, int tx, int rx, int grp, 5471 int cp, int stat, int vnic) 5472 { 5473 if (BNXT_PF(bp)) 5474 return bnxt_hwrm_reserve_pf_rings(bp, tx, rx, grp, cp, stat, 5475 vnic); 5476 else 5477 return bnxt_hwrm_reserve_vf_rings(bp, tx, rx, grp, cp, stat, 5478 vnic); 5479 } 5480 5481 int bnxt_nq_rings_in_use(struct bnxt *bp) 5482 { 5483 int cp = bp->cp_nr_rings; 5484 int ulp_msix, ulp_base; 5485 5486 ulp_msix = bnxt_get_ulp_msix_num(bp); 5487 if (ulp_msix) { 5488 ulp_base = bnxt_get_ulp_msix_base(bp); 5489 cp += ulp_msix; 5490 if ((ulp_base + ulp_msix) > cp) 5491 cp = ulp_base + ulp_msix; 5492 } 5493 return cp; 5494 } 5495 5496 static int bnxt_cp_rings_in_use(struct bnxt *bp) 5497 { 5498 int cp; 5499 5500 if (!(bp->flags & BNXT_FLAG_CHIP_P5)) 5501 return bnxt_nq_rings_in_use(bp); 5502 5503 cp = bp->tx_nr_rings + bp->rx_nr_rings; 5504 return cp; 5505 } 5506 5507 static int bnxt_get_func_stat_ctxs(struct bnxt *bp) 5508 { 5509 return bp->cp_nr_rings + bnxt_get_ulp_stat_ctxs(bp); 5510 } 5511 5512 static bool bnxt_need_reserve_rings(struct bnxt *bp) 5513 { 5514 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 5515 int cp = bnxt_cp_rings_in_use(bp); 5516 int nq = bnxt_nq_rings_in_use(bp); 5517 int rx = bp->rx_nr_rings, stat; 5518 int vnic = 1, grp = rx; 5519 5520 if (bp->hwrm_spec_code < 0x10601) 5521 return false; 5522 5523 if (hw_resc->resv_tx_rings != bp->tx_nr_rings) 5524 return true; 5525 5526 if ((bp->flags & BNXT_FLAG_RFS) && !(bp->flags & BNXT_FLAG_CHIP_P5)) 5527 vnic = rx + 1; 5528 if (bp->flags & BNXT_FLAG_AGG_RINGS) 5529 rx <<= 1; 5530 stat = bnxt_get_func_stat_ctxs(bp); 5531 if (BNXT_NEW_RM(bp) && 5532 (hw_resc->resv_rx_rings != rx || hw_resc->resv_cp_rings != cp || 5533 hw_resc->resv_vnics != vnic || hw_resc->resv_stat_ctxs != stat || 5534 (hw_resc->resv_hw_ring_grps != grp && 5535 !(bp->flags & BNXT_FLAG_CHIP_P5)))) 5536 return true; 5537 if ((bp->flags & BNXT_FLAG_CHIP_P5) && BNXT_PF(bp) && 5538 hw_resc->resv_irqs != nq) 5539 return true; 5540 return false; 5541 } 5542 5543 static int __bnxt_reserve_rings(struct bnxt *bp) 5544 { 5545 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 5546 int cp = bnxt_nq_rings_in_use(bp); 5547 int tx = bp->tx_nr_rings; 5548 int rx = bp->rx_nr_rings; 5549 int grp, rx_rings, rc; 5550 int vnic = 1, stat; 5551 bool sh = false; 5552 5553 if (!bnxt_need_reserve_rings(bp)) 5554 return 0; 5555 5556 if (bp->flags & BNXT_FLAG_SHARED_RINGS) 5557 sh = true; 5558 if ((bp->flags & BNXT_FLAG_RFS) && !(bp->flags & BNXT_FLAG_CHIP_P5)) 5559 vnic = rx + 1; 5560 if (bp->flags & BNXT_FLAG_AGG_RINGS) 5561 rx <<= 1; 5562 grp = bp->rx_nr_rings; 5563 stat = bnxt_get_func_stat_ctxs(bp); 5564 5565 rc = bnxt_hwrm_reserve_rings(bp, tx, rx, grp, cp, stat, vnic); 5566 if (rc) 5567 return rc; 5568 5569 tx = hw_resc->resv_tx_rings; 5570 if (BNXT_NEW_RM(bp)) { 5571 rx = hw_resc->resv_rx_rings; 5572 cp = hw_resc->resv_irqs; 5573 grp = hw_resc->resv_hw_ring_grps; 5574 vnic = hw_resc->resv_vnics; 5575 stat = hw_resc->resv_stat_ctxs; 5576 } 5577 5578 rx_rings = rx; 5579 if (bp->flags & BNXT_FLAG_AGG_RINGS) { 5580 if (rx >= 2) { 5581 rx_rings = rx >> 1; 5582 } else { 5583 if (netif_running(bp->dev)) 5584 return -ENOMEM; 5585 5586 bp->flags &= ~BNXT_FLAG_AGG_RINGS; 5587 bp->flags |= BNXT_FLAG_NO_AGG_RINGS; 5588 bp->dev->hw_features &= ~NETIF_F_LRO; 5589 bp->dev->features &= ~NETIF_F_LRO; 5590 bnxt_set_ring_params(bp); 5591 } 5592 } 5593 rx_rings = min_t(int, rx_rings, grp); 5594 cp = min_t(int, cp, bp->cp_nr_rings); 5595 if (stat > bnxt_get_ulp_stat_ctxs(bp)) 5596 stat -= bnxt_get_ulp_stat_ctxs(bp); 5597 cp = min_t(int, cp, stat); 5598 rc = bnxt_trim_rings(bp, &rx_rings, &tx, cp, sh); 5599 if (bp->flags & BNXT_FLAG_AGG_RINGS) 5600 rx = rx_rings << 1; 5601 cp = sh ? max_t(int, tx, rx_rings) : tx + rx_rings; 5602 bp->tx_nr_rings = tx; 5603 bp->rx_nr_rings = rx_rings; 5604 bp->cp_nr_rings = cp; 5605 5606 if (!tx || !rx || !cp || !grp || !vnic || !stat) 5607 return -ENOMEM; 5608 5609 return rc; 5610 } 5611 5612 static int bnxt_hwrm_check_vf_rings(struct bnxt *bp, int tx_rings, int rx_rings, 5613 int ring_grps, int cp_rings, int stats, 5614 int vnics) 5615 { 5616 struct hwrm_func_vf_cfg_input req = {0}; 5617 u32 flags; 5618 int rc; 5619 5620 if (!BNXT_NEW_RM(bp)) 5621 return 0; 5622 5623 __bnxt_hwrm_reserve_vf_rings(bp, &req, tx_rings, rx_rings, ring_grps, 5624 cp_rings, stats, vnics); 5625 flags = FUNC_VF_CFG_REQ_FLAGS_TX_ASSETS_TEST | 5626 FUNC_VF_CFG_REQ_FLAGS_RX_ASSETS_TEST | 5627 FUNC_VF_CFG_REQ_FLAGS_CMPL_ASSETS_TEST | 5628 FUNC_VF_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST | 5629 FUNC_VF_CFG_REQ_FLAGS_VNIC_ASSETS_TEST | 5630 FUNC_VF_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST; 5631 if (!(bp->flags & BNXT_FLAG_CHIP_P5)) 5632 flags |= FUNC_VF_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST; 5633 5634 req.flags = cpu_to_le32(flags); 5635 rc = hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5636 if (rc) 5637 return -ENOMEM; 5638 return 0; 5639 } 5640 5641 static int bnxt_hwrm_check_pf_rings(struct bnxt *bp, int tx_rings, int rx_rings, 5642 int ring_grps, int cp_rings, int stats, 5643 int vnics) 5644 { 5645 struct hwrm_func_cfg_input req = {0}; 5646 u32 flags; 5647 int rc; 5648 5649 __bnxt_hwrm_reserve_pf_rings(bp, &req, tx_rings, rx_rings, ring_grps, 5650 cp_rings, stats, vnics); 5651 flags = FUNC_CFG_REQ_FLAGS_TX_ASSETS_TEST; 5652 if (BNXT_NEW_RM(bp)) { 5653 flags |= FUNC_CFG_REQ_FLAGS_RX_ASSETS_TEST | 5654 FUNC_CFG_REQ_FLAGS_CMPL_ASSETS_TEST | 5655 FUNC_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST | 5656 FUNC_CFG_REQ_FLAGS_VNIC_ASSETS_TEST; 5657 if (bp->flags & BNXT_FLAG_CHIP_P5) 5658 flags |= FUNC_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST | 5659 FUNC_CFG_REQ_FLAGS_NQ_ASSETS_TEST; 5660 else 5661 flags |= FUNC_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST; 5662 } 5663 5664 req.flags = cpu_to_le32(flags); 5665 rc = hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5666 if (rc) 5667 return -ENOMEM; 5668 return 0; 5669 } 5670 5671 static int bnxt_hwrm_check_rings(struct bnxt *bp, int tx_rings, int rx_rings, 5672 int ring_grps, int cp_rings, int stats, 5673 int vnics) 5674 { 5675 if (bp->hwrm_spec_code < 0x10801) 5676 return 0; 5677 5678 if (BNXT_PF(bp)) 5679 return bnxt_hwrm_check_pf_rings(bp, tx_rings, rx_rings, 5680 ring_grps, cp_rings, stats, 5681 vnics); 5682 5683 return bnxt_hwrm_check_vf_rings(bp, tx_rings, rx_rings, ring_grps, 5684 cp_rings, stats, vnics); 5685 } 5686 5687 static void bnxt_hwrm_coal_params_qcaps(struct bnxt *bp) 5688 { 5689 struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr; 5690 struct bnxt_coal_cap *coal_cap = &bp->coal_cap; 5691 struct hwrm_ring_aggint_qcaps_input req = {0}; 5692 int rc; 5693 5694 coal_cap->cmpl_params = BNXT_LEGACY_COAL_CMPL_PARAMS; 5695 coal_cap->num_cmpl_dma_aggr_max = 63; 5696 coal_cap->num_cmpl_dma_aggr_during_int_max = 63; 5697 coal_cap->cmpl_aggr_dma_tmr_max = 65535; 5698 coal_cap->cmpl_aggr_dma_tmr_during_int_max = 65535; 5699 coal_cap->int_lat_tmr_min_max = 65535; 5700 coal_cap->int_lat_tmr_max_max = 65535; 5701 coal_cap->num_cmpl_aggr_int_max = 65535; 5702 coal_cap->timer_units = 80; 5703 5704 if (bp->hwrm_spec_code < 0x10902) 5705 return; 5706 5707 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_AGGINT_QCAPS, -1, -1); 5708 mutex_lock(&bp->hwrm_cmd_lock); 5709 rc = _hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5710 if (!rc) { 5711 coal_cap->cmpl_params = le32_to_cpu(resp->cmpl_params); 5712 coal_cap->nq_params = le32_to_cpu(resp->nq_params); 5713 coal_cap->num_cmpl_dma_aggr_max = 5714 le16_to_cpu(resp->num_cmpl_dma_aggr_max); 5715 coal_cap->num_cmpl_dma_aggr_during_int_max = 5716 le16_to_cpu(resp->num_cmpl_dma_aggr_during_int_max); 5717 coal_cap->cmpl_aggr_dma_tmr_max = 5718 le16_to_cpu(resp->cmpl_aggr_dma_tmr_max); 5719 coal_cap->cmpl_aggr_dma_tmr_during_int_max = 5720 le16_to_cpu(resp->cmpl_aggr_dma_tmr_during_int_max); 5721 coal_cap->int_lat_tmr_min_max = 5722 le16_to_cpu(resp->int_lat_tmr_min_max); 5723 coal_cap->int_lat_tmr_max_max = 5724 le16_to_cpu(resp->int_lat_tmr_max_max); 5725 coal_cap->num_cmpl_aggr_int_max = 5726 le16_to_cpu(resp->num_cmpl_aggr_int_max); 5727 coal_cap->timer_units = le16_to_cpu(resp->timer_units); 5728 } 5729 mutex_unlock(&bp->hwrm_cmd_lock); 5730 } 5731 5732 static u16 bnxt_usec_to_coal_tmr(struct bnxt *bp, u16 usec) 5733 { 5734 struct bnxt_coal_cap *coal_cap = &bp->coal_cap; 5735 5736 return usec * 1000 / coal_cap->timer_units; 5737 } 5738 5739 static void bnxt_hwrm_set_coal_params(struct bnxt *bp, 5740 struct bnxt_coal *hw_coal, 5741 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req) 5742 { 5743 struct bnxt_coal_cap *coal_cap = &bp->coal_cap; 5744 u32 cmpl_params = coal_cap->cmpl_params; 5745 u16 val, tmr, max, flags = 0; 5746 5747 max = hw_coal->bufs_per_record * 128; 5748 if (hw_coal->budget) 5749 max = hw_coal->bufs_per_record * hw_coal->budget; 5750 max = min_t(u16, max, coal_cap->num_cmpl_aggr_int_max); 5751 5752 val = clamp_t(u16, hw_coal->coal_bufs, 1, max); 5753 req->num_cmpl_aggr_int = cpu_to_le16(val); 5754 5755 val = min_t(u16, val, coal_cap->num_cmpl_dma_aggr_max); 5756 req->num_cmpl_dma_aggr = cpu_to_le16(val); 5757 5758 val = clamp_t(u16, hw_coal->coal_bufs_irq, 1, 5759 coal_cap->num_cmpl_dma_aggr_during_int_max); 5760 req->num_cmpl_dma_aggr_during_int = cpu_to_le16(val); 5761 5762 tmr = bnxt_usec_to_coal_tmr(bp, hw_coal->coal_ticks); 5763 tmr = clamp_t(u16, tmr, 1, coal_cap->int_lat_tmr_max_max); 5764 req->int_lat_tmr_max = cpu_to_le16(tmr); 5765 5766 /* min timer set to 1/2 of interrupt timer */ 5767 if (cmpl_params & RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN) { 5768 val = tmr / 2; 5769 val = clamp_t(u16, val, 1, coal_cap->int_lat_tmr_min_max); 5770 req->int_lat_tmr_min = cpu_to_le16(val); 5771 req->enables |= cpu_to_le16(BNXT_COAL_CMPL_MIN_TMR_ENABLE); 5772 } 5773 5774 /* buf timer set to 1/4 of interrupt timer */ 5775 val = clamp_t(u16, tmr / 4, 1, coal_cap->cmpl_aggr_dma_tmr_max); 5776 req->cmpl_aggr_dma_tmr = cpu_to_le16(val); 5777 5778 if (cmpl_params & 5779 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT) { 5780 tmr = bnxt_usec_to_coal_tmr(bp, hw_coal->coal_ticks_irq); 5781 val = clamp_t(u16, tmr, 1, 5782 coal_cap->cmpl_aggr_dma_tmr_during_int_max); 5783 req->cmpl_aggr_dma_tmr_during_int = cpu_to_le16(tmr); 5784 req->enables |= 5785 cpu_to_le16(BNXT_COAL_CMPL_AGGR_TMR_DURING_INT_ENABLE); 5786 } 5787 5788 if (cmpl_params & RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET) 5789 flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET; 5790 if ((cmpl_params & RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE) && 5791 hw_coal->idle_thresh && hw_coal->coal_ticks < hw_coal->idle_thresh) 5792 flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE; 5793 req->flags = cpu_to_le16(flags); 5794 req->enables |= cpu_to_le16(BNXT_COAL_CMPL_ENABLES); 5795 } 5796 5797 /* Caller holds bp->hwrm_cmd_lock */ 5798 static int __bnxt_hwrm_set_coal_nq(struct bnxt *bp, struct bnxt_napi *bnapi, 5799 struct bnxt_coal *hw_coal) 5800 { 5801 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0}; 5802 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 5803 struct bnxt_coal_cap *coal_cap = &bp->coal_cap; 5804 u32 nq_params = coal_cap->nq_params; 5805 u16 tmr; 5806 5807 if (!(nq_params & RING_AGGINT_QCAPS_RESP_NQ_PARAMS_INT_LAT_TMR_MIN)) 5808 return 0; 5809 5810 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, 5811 -1, -1); 5812 req.ring_id = cpu_to_le16(cpr->cp_ring_struct.fw_ring_id); 5813 req.flags = 5814 cpu_to_le16(RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_IS_NQ); 5815 5816 tmr = bnxt_usec_to_coal_tmr(bp, hw_coal->coal_ticks) / 2; 5817 tmr = clamp_t(u16, tmr, 1, coal_cap->int_lat_tmr_min_max); 5818 req.int_lat_tmr_min = cpu_to_le16(tmr); 5819 req.enables |= cpu_to_le16(BNXT_COAL_CMPL_MIN_TMR_ENABLE); 5820 return _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5821 } 5822 5823 int bnxt_hwrm_set_ring_coal(struct bnxt *bp, struct bnxt_napi *bnapi) 5824 { 5825 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx = {0}; 5826 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 5827 struct bnxt_coal coal; 5828 5829 /* Tick values in micro seconds. 5830 * 1 coal_buf x bufs_per_record = 1 completion record. 5831 */ 5832 memcpy(&coal, &bp->rx_coal, sizeof(struct bnxt_coal)); 5833 5834 coal.coal_ticks = cpr->rx_ring_coal.coal_ticks; 5835 coal.coal_bufs = cpr->rx_ring_coal.coal_bufs; 5836 5837 if (!bnapi->rx_ring) 5838 return -ENODEV; 5839 5840 bnxt_hwrm_cmd_hdr_init(bp, &req_rx, 5841 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1); 5842 5843 bnxt_hwrm_set_coal_params(bp, &coal, &req_rx); 5844 5845 req_rx.ring_id = cpu_to_le16(bnxt_cp_ring_for_rx(bp, bnapi->rx_ring)); 5846 5847 return hwrm_send_message(bp, &req_rx, sizeof(req_rx), 5848 HWRM_CMD_TIMEOUT); 5849 } 5850 5851 int bnxt_hwrm_set_coal(struct bnxt *bp) 5852 { 5853 int i, rc = 0; 5854 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx = {0}, 5855 req_tx = {0}, *req; 5856 5857 bnxt_hwrm_cmd_hdr_init(bp, &req_rx, 5858 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1); 5859 bnxt_hwrm_cmd_hdr_init(bp, &req_tx, 5860 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1); 5861 5862 bnxt_hwrm_set_coal_params(bp, &bp->rx_coal, &req_rx); 5863 bnxt_hwrm_set_coal_params(bp, &bp->tx_coal, &req_tx); 5864 5865 mutex_lock(&bp->hwrm_cmd_lock); 5866 for (i = 0; i < bp->cp_nr_rings; i++) { 5867 struct bnxt_napi *bnapi = bp->bnapi[i]; 5868 struct bnxt_coal *hw_coal; 5869 u16 ring_id; 5870 5871 req = &req_rx; 5872 if (!bnapi->rx_ring) { 5873 ring_id = bnxt_cp_ring_for_tx(bp, bnapi->tx_ring); 5874 req = &req_tx; 5875 } else { 5876 ring_id = bnxt_cp_ring_for_rx(bp, bnapi->rx_ring); 5877 } 5878 req->ring_id = cpu_to_le16(ring_id); 5879 5880 rc = _hwrm_send_message(bp, req, sizeof(*req), 5881 HWRM_CMD_TIMEOUT); 5882 if (rc) 5883 break; 5884 5885 if (!(bp->flags & BNXT_FLAG_CHIP_P5)) 5886 continue; 5887 5888 if (bnapi->rx_ring && bnapi->tx_ring) { 5889 req = &req_tx; 5890 ring_id = bnxt_cp_ring_for_tx(bp, bnapi->tx_ring); 5891 req->ring_id = cpu_to_le16(ring_id); 5892 rc = _hwrm_send_message(bp, req, sizeof(*req), 5893 HWRM_CMD_TIMEOUT); 5894 if (rc) 5895 break; 5896 } 5897 if (bnapi->rx_ring) 5898 hw_coal = &bp->rx_coal; 5899 else 5900 hw_coal = &bp->tx_coal; 5901 __bnxt_hwrm_set_coal_nq(bp, bnapi, hw_coal); 5902 } 5903 mutex_unlock(&bp->hwrm_cmd_lock); 5904 return rc; 5905 } 5906 5907 static int bnxt_hwrm_stat_ctx_free(struct bnxt *bp) 5908 { 5909 int rc = 0, i; 5910 struct hwrm_stat_ctx_free_input req = {0}; 5911 5912 if (!bp->bnapi) 5913 return 0; 5914 5915 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 5916 return 0; 5917 5918 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_FREE, -1, -1); 5919 5920 mutex_lock(&bp->hwrm_cmd_lock); 5921 for (i = 0; i < bp->cp_nr_rings; i++) { 5922 struct bnxt_napi *bnapi = bp->bnapi[i]; 5923 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 5924 5925 if (cpr->hw_stats_ctx_id != INVALID_STATS_CTX_ID) { 5926 req.stat_ctx_id = cpu_to_le32(cpr->hw_stats_ctx_id); 5927 5928 rc = _hwrm_send_message(bp, &req, sizeof(req), 5929 HWRM_CMD_TIMEOUT); 5930 if (rc) 5931 break; 5932 5933 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID; 5934 } 5935 } 5936 mutex_unlock(&bp->hwrm_cmd_lock); 5937 return rc; 5938 } 5939 5940 static int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp) 5941 { 5942 int rc = 0, i; 5943 struct hwrm_stat_ctx_alloc_input req = {0}; 5944 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr; 5945 5946 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 5947 return 0; 5948 5949 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_ALLOC, -1, -1); 5950 5951 req.update_period_ms = cpu_to_le32(bp->stats_coal_ticks / 1000); 5952 5953 mutex_lock(&bp->hwrm_cmd_lock); 5954 for (i = 0; i < bp->cp_nr_rings; i++) { 5955 struct bnxt_napi *bnapi = bp->bnapi[i]; 5956 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 5957 5958 req.stats_dma_addr = cpu_to_le64(cpr->hw_stats_map); 5959 5960 rc = _hwrm_send_message(bp, &req, sizeof(req), 5961 HWRM_CMD_TIMEOUT); 5962 if (rc) 5963 break; 5964 5965 cpr->hw_stats_ctx_id = le32_to_cpu(resp->stat_ctx_id); 5966 5967 bp->grp_info[i].fw_stats_ctx = cpr->hw_stats_ctx_id; 5968 } 5969 mutex_unlock(&bp->hwrm_cmd_lock); 5970 return rc; 5971 } 5972 5973 static int bnxt_hwrm_func_qcfg(struct bnxt *bp) 5974 { 5975 struct hwrm_func_qcfg_input req = {0}; 5976 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr; 5977 u16 flags; 5978 int rc; 5979 5980 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1); 5981 req.fid = cpu_to_le16(0xffff); 5982 mutex_lock(&bp->hwrm_cmd_lock); 5983 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5984 if (rc) 5985 goto func_qcfg_exit; 5986 5987 #ifdef CONFIG_BNXT_SRIOV 5988 if (BNXT_VF(bp)) { 5989 struct bnxt_vf_info *vf = &bp->vf; 5990 5991 vf->vlan = le16_to_cpu(resp->vlan) & VLAN_VID_MASK; 5992 } 5993 #endif 5994 flags = le16_to_cpu(resp->flags); 5995 if (flags & (FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED | 5996 FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED)) { 5997 bp->fw_cap |= BNXT_FW_CAP_LLDP_AGENT; 5998 if (flags & FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED) 5999 bp->fw_cap |= BNXT_FW_CAP_DCBX_AGENT; 6000 } 6001 if (BNXT_PF(bp) && (flags & FUNC_QCFG_RESP_FLAGS_MULTI_HOST)) 6002 bp->flags |= BNXT_FLAG_MULTI_HOST; 6003 6004 switch (resp->port_partition_type) { 6005 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0: 6006 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5: 6007 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0: 6008 bp->port_partition_type = resp->port_partition_type; 6009 break; 6010 } 6011 if (bp->hwrm_spec_code < 0x10707 || 6012 resp->evb_mode == FUNC_QCFG_RESP_EVB_MODE_VEB) 6013 bp->br_mode = BRIDGE_MODE_VEB; 6014 else if (resp->evb_mode == FUNC_QCFG_RESP_EVB_MODE_VEPA) 6015 bp->br_mode = BRIDGE_MODE_VEPA; 6016 else 6017 bp->br_mode = BRIDGE_MODE_UNDEF; 6018 6019 bp->max_mtu = le16_to_cpu(resp->max_mtu_configured); 6020 if (!bp->max_mtu) 6021 bp->max_mtu = BNXT_MAX_MTU; 6022 6023 func_qcfg_exit: 6024 mutex_unlock(&bp->hwrm_cmd_lock); 6025 return rc; 6026 } 6027 6028 static int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp) 6029 { 6030 struct hwrm_func_backing_store_qcaps_input req = {0}; 6031 struct hwrm_func_backing_store_qcaps_output *resp = 6032 bp->hwrm_cmd_resp_addr; 6033 int rc; 6034 6035 if (bp->hwrm_spec_code < 0x10902 || BNXT_VF(bp) || bp->ctx) 6036 return 0; 6037 6038 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_BACKING_STORE_QCAPS, -1, -1); 6039 mutex_lock(&bp->hwrm_cmd_lock); 6040 rc = _hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 6041 if (!rc) { 6042 struct bnxt_ctx_pg_info *ctx_pg; 6043 struct bnxt_ctx_mem_info *ctx; 6044 int i; 6045 6046 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); 6047 if (!ctx) { 6048 rc = -ENOMEM; 6049 goto ctx_err; 6050 } 6051 ctx_pg = kzalloc(sizeof(*ctx_pg) * (bp->max_q + 1), GFP_KERNEL); 6052 if (!ctx_pg) { 6053 kfree(ctx); 6054 rc = -ENOMEM; 6055 goto ctx_err; 6056 } 6057 for (i = 0; i < bp->max_q + 1; i++, ctx_pg++) 6058 ctx->tqm_mem[i] = ctx_pg; 6059 6060 bp->ctx = ctx; 6061 ctx->qp_max_entries = le32_to_cpu(resp->qp_max_entries); 6062 ctx->qp_min_qp1_entries = le16_to_cpu(resp->qp_min_qp1_entries); 6063 ctx->qp_max_l2_entries = le16_to_cpu(resp->qp_max_l2_entries); 6064 ctx->qp_entry_size = le16_to_cpu(resp->qp_entry_size); 6065 ctx->srq_max_l2_entries = le16_to_cpu(resp->srq_max_l2_entries); 6066 ctx->srq_max_entries = le32_to_cpu(resp->srq_max_entries); 6067 ctx->srq_entry_size = le16_to_cpu(resp->srq_entry_size); 6068 ctx->cq_max_l2_entries = le16_to_cpu(resp->cq_max_l2_entries); 6069 ctx->cq_max_entries = le32_to_cpu(resp->cq_max_entries); 6070 ctx->cq_entry_size = le16_to_cpu(resp->cq_entry_size); 6071 ctx->vnic_max_vnic_entries = 6072 le16_to_cpu(resp->vnic_max_vnic_entries); 6073 ctx->vnic_max_ring_table_entries = 6074 le16_to_cpu(resp->vnic_max_ring_table_entries); 6075 ctx->vnic_entry_size = le16_to_cpu(resp->vnic_entry_size); 6076 ctx->stat_max_entries = le32_to_cpu(resp->stat_max_entries); 6077 ctx->stat_entry_size = le16_to_cpu(resp->stat_entry_size); 6078 ctx->tqm_entry_size = le16_to_cpu(resp->tqm_entry_size); 6079 ctx->tqm_min_entries_per_ring = 6080 le32_to_cpu(resp->tqm_min_entries_per_ring); 6081 ctx->tqm_max_entries_per_ring = 6082 le32_to_cpu(resp->tqm_max_entries_per_ring); 6083 ctx->tqm_entries_multiple = resp->tqm_entries_multiple; 6084 if (!ctx->tqm_entries_multiple) 6085 ctx->tqm_entries_multiple = 1; 6086 ctx->mrav_max_entries = le32_to_cpu(resp->mrav_max_entries); 6087 ctx->mrav_entry_size = le16_to_cpu(resp->mrav_entry_size); 6088 ctx->mrav_num_entries_units = 6089 le16_to_cpu(resp->mrav_num_entries_units); 6090 ctx->tim_entry_size = le16_to_cpu(resp->tim_entry_size); 6091 ctx->tim_max_entries = le32_to_cpu(resp->tim_max_entries); 6092 } else { 6093 rc = 0; 6094 } 6095 ctx_err: 6096 mutex_unlock(&bp->hwrm_cmd_lock); 6097 return rc; 6098 } 6099 6100 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem, u8 *pg_attr, 6101 __le64 *pg_dir) 6102 { 6103 u8 pg_size = 0; 6104 6105 if (BNXT_PAGE_SHIFT == 13) 6106 pg_size = 1 << 4; 6107 else if (BNXT_PAGE_SIZE == 16) 6108 pg_size = 2 << 4; 6109 6110 *pg_attr = pg_size; 6111 if (rmem->depth >= 1) { 6112 if (rmem->depth == 2) 6113 *pg_attr |= 2; 6114 else 6115 *pg_attr |= 1; 6116 *pg_dir = cpu_to_le64(rmem->pg_tbl_map); 6117 } else { 6118 *pg_dir = cpu_to_le64(rmem->dma_arr[0]); 6119 } 6120 } 6121 6122 #define FUNC_BACKING_STORE_CFG_REQ_DFLT_ENABLES \ 6123 (FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP | \ 6124 FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ | \ 6125 FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ | \ 6126 FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC | \ 6127 FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT) 6128 6129 static int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, u32 enables) 6130 { 6131 struct hwrm_func_backing_store_cfg_input req = {0}; 6132 struct bnxt_ctx_mem_info *ctx = bp->ctx; 6133 struct bnxt_ctx_pg_info *ctx_pg; 6134 __le32 *num_entries; 6135 __le64 *pg_dir; 6136 u32 flags = 0; 6137 u8 *pg_attr; 6138 int i, rc; 6139 u32 ena; 6140 6141 if (!ctx) 6142 return 0; 6143 6144 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_BACKING_STORE_CFG, -1, -1); 6145 req.enables = cpu_to_le32(enables); 6146 6147 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP) { 6148 ctx_pg = &ctx->qp_mem; 6149 req.qp_num_entries = cpu_to_le32(ctx_pg->entries); 6150 req.qp_num_qp1_entries = cpu_to_le16(ctx->qp_min_qp1_entries); 6151 req.qp_num_l2_entries = cpu_to_le16(ctx->qp_max_l2_entries); 6152 req.qp_entry_size = cpu_to_le16(ctx->qp_entry_size); 6153 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, 6154 &req.qpc_pg_size_qpc_lvl, 6155 &req.qpc_page_dir); 6156 } 6157 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ) { 6158 ctx_pg = &ctx->srq_mem; 6159 req.srq_num_entries = cpu_to_le32(ctx_pg->entries); 6160 req.srq_num_l2_entries = cpu_to_le16(ctx->srq_max_l2_entries); 6161 req.srq_entry_size = cpu_to_le16(ctx->srq_entry_size); 6162 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, 6163 &req.srq_pg_size_srq_lvl, 6164 &req.srq_page_dir); 6165 } 6166 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ) { 6167 ctx_pg = &ctx->cq_mem; 6168 req.cq_num_entries = cpu_to_le32(ctx_pg->entries); 6169 req.cq_num_l2_entries = cpu_to_le16(ctx->cq_max_l2_entries); 6170 req.cq_entry_size = cpu_to_le16(ctx->cq_entry_size); 6171 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, &req.cq_pg_size_cq_lvl, 6172 &req.cq_page_dir); 6173 } 6174 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC) { 6175 ctx_pg = &ctx->vnic_mem; 6176 req.vnic_num_vnic_entries = 6177 cpu_to_le16(ctx->vnic_max_vnic_entries); 6178 req.vnic_num_ring_table_entries = 6179 cpu_to_le16(ctx->vnic_max_ring_table_entries); 6180 req.vnic_entry_size = cpu_to_le16(ctx->vnic_entry_size); 6181 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, 6182 &req.vnic_pg_size_vnic_lvl, 6183 &req.vnic_page_dir); 6184 } 6185 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT) { 6186 ctx_pg = &ctx->stat_mem; 6187 req.stat_num_entries = cpu_to_le32(ctx->stat_max_entries); 6188 req.stat_entry_size = cpu_to_le16(ctx->stat_entry_size); 6189 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, 6190 &req.stat_pg_size_stat_lvl, 6191 &req.stat_page_dir); 6192 } 6193 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV) { 6194 ctx_pg = &ctx->mrav_mem; 6195 req.mrav_num_entries = cpu_to_le32(ctx_pg->entries); 6196 if (ctx->mrav_num_entries_units) 6197 flags |= 6198 FUNC_BACKING_STORE_CFG_REQ_FLAGS_MRAV_RESERVATION_SPLIT; 6199 req.mrav_entry_size = cpu_to_le16(ctx->mrav_entry_size); 6200 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, 6201 &req.mrav_pg_size_mrav_lvl, 6202 &req.mrav_page_dir); 6203 } 6204 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM) { 6205 ctx_pg = &ctx->tim_mem; 6206 req.tim_num_entries = cpu_to_le32(ctx_pg->entries); 6207 req.tim_entry_size = cpu_to_le16(ctx->tim_entry_size); 6208 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, 6209 &req.tim_pg_size_tim_lvl, 6210 &req.tim_page_dir); 6211 } 6212 for (i = 0, num_entries = &req.tqm_sp_num_entries, 6213 pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl, 6214 pg_dir = &req.tqm_sp_page_dir, 6215 ena = FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP; 6216 i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) { 6217 if (!(enables & ena)) 6218 continue; 6219 6220 req.tqm_entry_size = cpu_to_le16(ctx->tqm_entry_size); 6221 ctx_pg = ctx->tqm_mem[i]; 6222 *num_entries = cpu_to_le32(ctx_pg->entries); 6223 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir); 6224 } 6225 req.flags = cpu_to_le32(flags); 6226 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 6227 if (rc) 6228 rc = -EIO; 6229 return rc; 6230 } 6231 6232 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp, 6233 struct bnxt_ctx_pg_info *ctx_pg) 6234 { 6235 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem; 6236 6237 rmem->page_size = BNXT_PAGE_SIZE; 6238 rmem->pg_arr = ctx_pg->ctx_pg_arr; 6239 rmem->dma_arr = ctx_pg->ctx_dma_arr; 6240 rmem->flags = BNXT_RMEM_VALID_PTE_FLAG; 6241 if (rmem->depth >= 1) 6242 rmem->flags |= BNXT_RMEM_USE_FULL_PAGE_FLAG; 6243 return bnxt_alloc_ring(bp, rmem); 6244 } 6245 6246 static int bnxt_alloc_ctx_pg_tbls(struct bnxt *bp, 6247 struct bnxt_ctx_pg_info *ctx_pg, u32 mem_size, 6248 u8 depth) 6249 { 6250 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem; 6251 int rc; 6252 6253 if (!mem_size) 6254 return 0; 6255 6256 ctx_pg->nr_pages = DIV_ROUND_UP(mem_size, BNXT_PAGE_SIZE); 6257 if (ctx_pg->nr_pages > MAX_CTX_TOTAL_PAGES) { 6258 ctx_pg->nr_pages = 0; 6259 return -EINVAL; 6260 } 6261 if (ctx_pg->nr_pages > MAX_CTX_PAGES || depth > 1) { 6262 int nr_tbls, i; 6263 6264 rmem->depth = 2; 6265 ctx_pg->ctx_pg_tbl = kcalloc(MAX_CTX_PAGES, sizeof(ctx_pg), 6266 GFP_KERNEL); 6267 if (!ctx_pg->ctx_pg_tbl) 6268 return -ENOMEM; 6269 nr_tbls = DIV_ROUND_UP(ctx_pg->nr_pages, MAX_CTX_PAGES); 6270 rmem->nr_pages = nr_tbls; 6271 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg); 6272 if (rc) 6273 return rc; 6274 for (i = 0; i < nr_tbls; i++) { 6275 struct bnxt_ctx_pg_info *pg_tbl; 6276 6277 pg_tbl = kzalloc(sizeof(*pg_tbl), GFP_KERNEL); 6278 if (!pg_tbl) 6279 return -ENOMEM; 6280 ctx_pg->ctx_pg_tbl[i] = pg_tbl; 6281 rmem = &pg_tbl->ring_mem; 6282 rmem->pg_tbl = ctx_pg->ctx_pg_arr[i]; 6283 rmem->pg_tbl_map = ctx_pg->ctx_dma_arr[i]; 6284 rmem->depth = 1; 6285 rmem->nr_pages = MAX_CTX_PAGES; 6286 if (i == (nr_tbls - 1)) { 6287 int rem = ctx_pg->nr_pages % MAX_CTX_PAGES; 6288 6289 if (rem) 6290 rmem->nr_pages = rem; 6291 } 6292 rc = bnxt_alloc_ctx_mem_blk(bp, pg_tbl); 6293 if (rc) 6294 break; 6295 } 6296 } else { 6297 rmem->nr_pages = DIV_ROUND_UP(mem_size, BNXT_PAGE_SIZE); 6298 if (rmem->nr_pages > 1 || depth) 6299 rmem->depth = 1; 6300 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg); 6301 } 6302 return rc; 6303 } 6304 6305 static void bnxt_free_ctx_pg_tbls(struct bnxt *bp, 6306 struct bnxt_ctx_pg_info *ctx_pg) 6307 { 6308 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem; 6309 6310 if (rmem->depth > 1 || ctx_pg->nr_pages > MAX_CTX_PAGES || 6311 ctx_pg->ctx_pg_tbl) { 6312 int i, nr_tbls = rmem->nr_pages; 6313 6314 for (i = 0; i < nr_tbls; i++) { 6315 struct bnxt_ctx_pg_info *pg_tbl; 6316 struct bnxt_ring_mem_info *rmem2; 6317 6318 pg_tbl = ctx_pg->ctx_pg_tbl[i]; 6319 if (!pg_tbl) 6320 continue; 6321 rmem2 = &pg_tbl->ring_mem; 6322 bnxt_free_ring(bp, rmem2); 6323 ctx_pg->ctx_pg_arr[i] = NULL; 6324 kfree(pg_tbl); 6325 ctx_pg->ctx_pg_tbl[i] = NULL; 6326 } 6327 kfree(ctx_pg->ctx_pg_tbl); 6328 ctx_pg->ctx_pg_tbl = NULL; 6329 } 6330 bnxt_free_ring(bp, rmem); 6331 ctx_pg->nr_pages = 0; 6332 } 6333 6334 static void bnxt_free_ctx_mem(struct bnxt *bp) 6335 { 6336 struct bnxt_ctx_mem_info *ctx = bp->ctx; 6337 int i; 6338 6339 if (!ctx) 6340 return; 6341 6342 if (ctx->tqm_mem[0]) { 6343 for (i = 0; i < bp->max_q + 1; i++) 6344 bnxt_free_ctx_pg_tbls(bp, ctx->tqm_mem[i]); 6345 kfree(ctx->tqm_mem[0]); 6346 ctx->tqm_mem[0] = NULL; 6347 } 6348 6349 bnxt_free_ctx_pg_tbls(bp, &ctx->tim_mem); 6350 bnxt_free_ctx_pg_tbls(bp, &ctx->mrav_mem); 6351 bnxt_free_ctx_pg_tbls(bp, &ctx->stat_mem); 6352 bnxt_free_ctx_pg_tbls(bp, &ctx->vnic_mem); 6353 bnxt_free_ctx_pg_tbls(bp, &ctx->cq_mem); 6354 bnxt_free_ctx_pg_tbls(bp, &ctx->srq_mem); 6355 bnxt_free_ctx_pg_tbls(bp, &ctx->qp_mem); 6356 ctx->flags &= ~BNXT_CTX_FLAG_INITED; 6357 } 6358 6359 static int bnxt_alloc_ctx_mem(struct bnxt *bp) 6360 { 6361 struct bnxt_ctx_pg_info *ctx_pg; 6362 struct bnxt_ctx_mem_info *ctx; 6363 u32 mem_size, ena, entries; 6364 u32 num_mr, num_ah; 6365 u32 extra_srqs = 0; 6366 u32 extra_qps = 0; 6367 u8 pg_lvl = 1; 6368 int i, rc; 6369 6370 rc = bnxt_hwrm_func_backing_store_qcaps(bp); 6371 if (rc) { 6372 netdev_err(bp->dev, "Failed querying context mem capability, rc = %d.\n", 6373 rc); 6374 return rc; 6375 } 6376 ctx = bp->ctx; 6377 if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED)) 6378 return 0; 6379 6380 if (bp->flags & BNXT_FLAG_ROCE_CAP) { 6381 pg_lvl = 2; 6382 extra_qps = 65536; 6383 extra_srqs = 8192; 6384 } 6385 6386 ctx_pg = &ctx->qp_mem; 6387 ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries + 6388 extra_qps; 6389 mem_size = ctx->qp_entry_size * ctx_pg->entries; 6390 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, pg_lvl); 6391 if (rc) 6392 return rc; 6393 6394 ctx_pg = &ctx->srq_mem; 6395 ctx_pg->entries = ctx->srq_max_l2_entries + extra_srqs; 6396 mem_size = ctx->srq_entry_size * ctx_pg->entries; 6397 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, pg_lvl); 6398 if (rc) 6399 return rc; 6400 6401 ctx_pg = &ctx->cq_mem; 6402 ctx_pg->entries = ctx->cq_max_l2_entries + extra_qps * 2; 6403 mem_size = ctx->cq_entry_size * ctx_pg->entries; 6404 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, pg_lvl); 6405 if (rc) 6406 return rc; 6407 6408 ctx_pg = &ctx->vnic_mem; 6409 ctx_pg->entries = ctx->vnic_max_vnic_entries + 6410 ctx->vnic_max_ring_table_entries; 6411 mem_size = ctx->vnic_entry_size * ctx_pg->entries; 6412 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1); 6413 if (rc) 6414 return rc; 6415 6416 ctx_pg = &ctx->stat_mem; 6417 ctx_pg->entries = ctx->stat_max_entries; 6418 mem_size = ctx->stat_entry_size * ctx_pg->entries; 6419 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1); 6420 if (rc) 6421 return rc; 6422 6423 ena = 0; 6424 if (!(bp->flags & BNXT_FLAG_ROCE_CAP)) 6425 goto skip_rdma; 6426 6427 ctx_pg = &ctx->mrav_mem; 6428 /* 128K extra is needed to accommodate static AH context 6429 * allocation by f/w. 6430 */ 6431 num_mr = 1024 * 256; 6432 num_ah = 1024 * 128; 6433 ctx_pg->entries = num_mr + num_ah; 6434 mem_size = ctx->mrav_entry_size * ctx_pg->entries; 6435 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 2); 6436 if (rc) 6437 return rc; 6438 ena = FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV; 6439 if (ctx->mrav_num_entries_units) 6440 ctx_pg->entries = 6441 ((num_mr / ctx->mrav_num_entries_units) << 16) | 6442 (num_ah / ctx->mrav_num_entries_units); 6443 6444 ctx_pg = &ctx->tim_mem; 6445 ctx_pg->entries = ctx->qp_mem.entries; 6446 mem_size = ctx->tim_entry_size * ctx_pg->entries; 6447 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1); 6448 if (rc) 6449 return rc; 6450 ena |= FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM; 6451 6452 skip_rdma: 6453 entries = ctx->qp_max_l2_entries + extra_qps; 6454 entries = roundup(entries, ctx->tqm_entries_multiple); 6455 entries = clamp_t(u32, entries, ctx->tqm_min_entries_per_ring, 6456 ctx->tqm_max_entries_per_ring); 6457 for (i = 0; i < bp->max_q + 1; i++) { 6458 ctx_pg = ctx->tqm_mem[i]; 6459 ctx_pg->entries = entries; 6460 mem_size = ctx->tqm_entry_size * entries; 6461 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1); 6462 if (rc) 6463 return rc; 6464 ena |= FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP << i; 6465 } 6466 ena |= FUNC_BACKING_STORE_CFG_REQ_DFLT_ENABLES; 6467 rc = bnxt_hwrm_func_backing_store_cfg(bp, ena); 6468 if (rc) 6469 netdev_err(bp->dev, "Failed configuring context mem, rc = %d.\n", 6470 rc); 6471 else 6472 ctx->flags |= BNXT_CTX_FLAG_INITED; 6473 6474 return 0; 6475 } 6476 6477 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp, bool all) 6478 { 6479 struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr; 6480 struct hwrm_func_resource_qcaps_input req = {0}; 6481 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 6482 int rc; 6483 6484 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESOURCE_QCAPS, -1, -1); 6485 req.fid = cpu_to_le16(0xffff); 6486 6487 mutex_lock(&bp->hwrm_cmd_lock); 6488 rc = _hwrm_send_message_silent(bp, &req, sizeof(req), 6489 HWRM_CMD_TIMEOUT); 6490 if (rc) { 6491 rc = -EIO; 6492 goto hwrm_func_resc_qcaps_exit; 6493 } 6494 6495 hw_resc->max_tx_sch_inputs = le16_to_cpu(resp->max_tx_scheduler_inputs); 6496 if (!all) 6497 goto hwrm_func_resc_qcaps_exit; 6498 6499 hw_resc->min_rsscos_ctxs = le16_to_cpu(resp->min_rsscos_ctx); 6500 hw_resc->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx); 6501 hw_resc->min_cp_rings = le16_to_cpu(resp->min_cmpl_rings); 6502 hw_resc->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings); 6503 hw_resc->min_tx_rings = le16_to_cpu(resp->min_tx_rings); 6504 hw_resc->max_tx_rings = le16_to_cpu(resp->max_tx_rings); 6505 hw_resc->min_rx_rings = le16_to_cpu(resp->min_rx_rings); 6506 hw_resc->max_rx_rings = le16_to_cpu(resp->max_rx_rings); 6507 hw_resc->min_hw_ring_grps = le16_to_cpu(resp->min_hw_ring_grps); 6508 hw_resc->max_hw_ring_grps = le16_to_cpu(resp->max_hw_ring_grps); 6509 hw_resc->min_l2_ctxs = le16_to_cpu(resp->min_l2_ctxs); 6510 hw_resc->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs); 6511 hw_resc->min_vnics = le16_to_cpu(resp->min_vnics); 6512 hw_resc->max_vnics = le16_to_cpu(resp->max_vnics); 6513 hw_resc->min_stat_ctxs = le16_to_cpu(resp->min_stat_ctx); 6514 hw_resc->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx); 6515 6516 if (bp->flags & BNXT_FLAG_CHIP_P5) { 6517 u16 max_msix = le16_to_cpu(resp->max_msix); 6518 6519 hw_resc->max_nqs = max_msix; 6520 hw_resc->max_hw_ring_grps = hw_resc->max_rx_rings; 6521 } 6522 6523 if (BNXT_PF(bp)) { 6524 struct bnxt_pf_info *pf = &bp->pf; 6525 6526 pf->vf_resv_strategy = 6527 le16_to_cpu(resp->vf_reservation_strategy); 6528 if (pf->vf_resv_strategy > BNXT_VF_RESV_STRATEGY_MINIMAL_STATIC) 6529 pf->vf_resv_strategy = BNXT_VF_RESV_STRATEGY_MAXIMAL; 6530 } 6531 hwrm_func_resc_qcaps_exit: 6532 mutex_unlock(&bp->hwrm_cmd_lock); 6533 return rc; 6534 } 6535 6536 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp) 6537 { 6538 int rc = 0; 6539 struct hwrm_func_qcaps_input req = {0}; 6540 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr; 6541 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 6542 u32 flags; 6543 6544 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCAPS, -1, -1); 6545 req.fid = cpu_to_le16(0xffff); 6546 6547 mutex_lock(&bp->hwrm_cmd_lock); 6548 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 6549 if (rc) 6550 goto hwrm_func_qcaps_exit; 6551 6552 flags = le32_to_cpu(resp->flags); 6553 if (flags & FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED) 6554 bp->flags |= BNXT_FLAG_ROCEV1_CAP; 6555 if (flags & FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED) 6556 bp->flags |= BNXT_FLAG_ROCEV2_CAP; 6557 if (flags & FUNC_QCAPS_RESP_FLAGS_PCIE_STATS_SUPPORTED) 6558 bp->fw_cap |= BNXT_FW_CAP_PCIE_STATS_SUPPORTED; 6559 if (flags & FUNC_QCAPS_RESP_FLAGS_EXT_STATS_SUPPORTED) 6560 bp->fw_cap |= BNXT_FW_CAP_EXT_STATS_SUPPORTED; 6561 6562 bp->tx_push_thresh = 0; 6563 if (flags & FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED) 6564 bp->tx_push_thresh = BNXT_TX_PUSH_THRESH; 6565 6566 hw_resc->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx); 6567 hw_resc->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings); 6568 hw_resc->max_tx_rings = le16_to_cpu(resp->max_tx_rings); 6569 hw_resc->max_rx_rings = le16_to_cpu(resp->max_rx_rings); 6570 hw_resc->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps); 6571 if (!hw_resc->max_hw_ring_grps) 6572 hw_resc->max_hw_ring_grps = hw_resc->max_tx_rings; 6573 hw_resc->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs); 6574 hw_resc->max_vnics = le16_to_cpu(resp->max_vnics); 6575 hw_resc->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx); 6576 6577 if (BNXT_PF(bp)) { 6578 struct bnxt_pf_info *pf = &bp->pf; 6579 6580 pf->fw_fid = le16_to_cpu(resp->fid); 6581 pf->port_id = le16_to_cpu(resp->port_id); 6582 bp->dev->dev_port = pf->port_id; 6583 memcpy(pf->mac_addr, resp->mac_address, ETH_ALEN); 6584 pf->first_vf_id = le16_to_cpu(resp->first_vf_id); 6585 pf->max_vfs = le16_to_cpu(resp->max_vfs); 6586 pf->max_encap_records = le32_to_cpu(resp->max_encap_records); 6587 pf->max_decap_records = le32_to_cpu(resp->max_decap_records); 6588 pf->max_tx_em_flows = le32_to_cpu(resp->max_tx_em_flows); 6589 pf->max_tx_wm_flows = le32_to_cpu(resp->max_tx_wm_flows); 6590 pf->max_rx_em_flows = le32_to_cpu(resp->max_rx_em_flows); 6591 pf->max_rx_wm_flows = le32_to_cpu(resp->max_rx_wm_flows); 6592 if (flags & FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED) 6593 bp->flags |= BNXT_FLAG_WOL_CAP; 6594 } else { 6595 #ifdef CONFIG_BNXT_SRIOV 6596 struct bnxt_vf_info *vf = &bp->vf; 6597 6598 vf->fw_fid = le16_to_cpu(resp->fid); 6599 memcpy(vf->mac_addr, resp->mac_address, ETH_ALEN); 6600 #endif 6601 } 6602 6603 hwrm_func_qcaps_exit: 6604 mutex_unlock(&bp->hwrm_cmd_lock); 6605 return rc; 6606 } 6607 6608 static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp); 6609 6610 static int bnxt_hwrm_func_qcaps(struct bnxt *bp) 6611 { 6612 int rc; 6613 6614 rc = __bnxt_hwrm_func_qcaps(bp); 6615 if (rc) 6616 return rc; 6617 rc = bnxt_hwrm_queue_qportcfg(bp); 6618 if (rc) { 6619 netdev_err(bp->dev, "hwrm query qportcfg failure rc: %d\n", rc); 6620 return rc; 6621 } 6622 if (bp->hwrm_spec_code >= 0x10803) { 6623 rc = bnxt_alloc_ctx_mem(bp); 6624 if (rc) 6625 return rc; 6626 rc = bnxt_hwrm_func_resc_qcaps(bp, true); 6627 if (!rc) 6628 bp->fw_cap |= BNXT_FW_CAP_NEW_RM; 6629 } 6630 return 0; 6631 } 6632 6633 static int bnxt_hwrm_cfa_adv_flow_mgnt_qcaps(struct bnxt *bp) 6634 { 6635 struct hwrm_cfa_adv_flow_mgnt_qcaps_input req = {0}; 6636 struct hwrm_cfa_adv_flow_mgnt_qcaps_output *resp; 6637 int rc = 0; 6638 u32 flags; 6639 6640 if (!(bp->fw_cap & BNXT_FW_CAP_CFA_ADV_FLOW)) 6641 return 0; 6642 6643 resp = bp->hwrm_cmd_resp_addr; 6644 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_ADV_FLOW_MGNT_QCAPS, -1, -1); 6645 6646 mutex_lock(&bp->hwrm_cmd_lock); 6647 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 6648 if (rc) 6649 goto hwrm_cfa_adv_qcaps_exit; 6650 6651 flags = le32_to_cpu(resp->flags); 6652 if (flags & 6653 CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RFS_RING_TBL_IDX_SUPPORTED) 6654 bp->fw_cap |= BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX; 6655 6656 hwrm_cfa_adv_qcaps_exit: 6657 mutex_unlock(&bp->hwrm_cmd_lock); 6658 return rc; 6659 } 6660 6661 static int bnxt_hwrm_func_reset(struct bnxt *bp) 6662 { 6663 struct hwrm_func_reset_input req = {0}; 6664 6665 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESET, -1, -1); 6666 req.enables = 0; 6667 6668 return hwrm_send_message(bp, &req, sizeof(req), HWRM_RESET_TIMEOUT); 6669 } 6670 6671 static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp) 6672 { 6673 int rc = 0; 6674 struct hwrm_queue_qportcfg_input req = {0}; 6675 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr; 6676 u8 i, j, *qptr; 6677 bool no_rdma; 6678 6679 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_QUEUE_QPORTCFG, -1, -1); 6680 6681 mutex_lock(&bp->hwrm_cmd_lock); 6682 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 6683 if (rc) 6684 goto qportcfg_exit; 6685 6686 if (!resp->max_configurable_queues) { 6687 rc = -EINVAL; 6688 goto qportcfg_exit; 6689 } 6690 bp->max_tc = resp->max_configurable_queues; 6691 bp->max_lltc = resp->max_configurable_lossless_queues; 6692 if (bp->max_tc > BNXT_MAX_QUEUE) 6693 bp->max_tc = BNXT_MAX_QUEUE; 6694 6695 no_rdma = !(bp->flags & BNXT_FLAG_ROCE_CAP); 6696 qptr = &resp->queue_id0; 6697 for (i = 0, j = 0; i < bp->max_tc; i++) { 6698 bp->q_info[j].queue_id = *qptr; 6699 bp->q_ids[i] = *qptr++; 6700 bp->q_info[j].queue_profile = *qptr++; 6701 bp->tc_to_qidx[j] = j; 6702 if (!BNXT_CNPQ(bp->q_info[j].queue_profile) || 6703 (no_rdma && BNXT_PF(bp))) 6704 j++; 6705 } 6706 bp->max_q = bp->max_tc; 6707 bp->max_tc = max_t(u8, j, 1); 6708 6709 if (resp->queue_cfg_info & QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG) 6710 bp->max_tc = 1; 6711 6712 if (bp->max_lltc > bp->max_tc) 6713 bp->max_lltc = bp->max_tc; 6714 6715 qportcfg_exit: 6716 mutex_unlock(&bp->hwrm_cmd_lock); 6717 return rc; 6718 } 6719 6720 static int bnxt_hwrm_ver_get(struct bnxt *bp) 6721 { 6722 int rc; 6723 struct hwrm_ver_get_input req = {0}; 6724 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr; 6725 u32 dev_caps_cfg; 6726 6727 bp->hwrm_max_req_len = HWRM_MAX_REQ_LEN; 6728 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VER_GET, -1, -1); 6729 req.hwrm_intf_maj = HWRM_VERSION_MAJOR; 6730 req.hwrm_intf_min = HWRM_VERSION_MINOR; 6731 req.hwrm_intf_upd = HWRM_VERSION_UPDATE; 6732 mutex_lock(&bp->hwrm_cmd_lock); 6733 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 6734 if (rc) 6735 goto hwrm_ver_get_exit; 6736 6737 memcpy(&bp->ver_resp, resp, sizeof(struct hwrm_ver_get_output)); 6738 6739 bp->hwrm_spec_code = resp->hwrm_intf_maj_8b << 16 | 6740 resp->hwrm_intf_min_8b << 8 | 6741 resp->hwrm_intf_upd_8b; 6742 if (resp->hwrm_intf_maj_8b < 1) { 6743 netdev_warn(bp->dev, "HWRM interface %d.%d.%d is older than 1.0.0.\n", 6744 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b, 6745 resp->hwrm_intf_upd_8b); 6746 netdev_warn(bp->dev, "Please update firmware with HWRM interface 1.0.0 or newer.\n"); 6747 } 6748 snprintf(bp->fw_ver_str, BC_HWRM_STR_LEN, "%d.%d.%d.%d", 6749 resp->hwrm_fw_maj_8b, resp->hwrm_fw_min_8b, 6750 resp->hwrm_fw_bld_8b, resp->hwrm_fw_rsvd_8b); 6751 6752 if (strlen(resp->active_pkg_name)) { 6753 int fw_ver_len = strlen(bp->fw_ver_str); 6754 6755 snprintf(bp->fw_ver_str + fw_ver_len, 6756 FW_VER_STR_LEN - fw_ver_len - 1, "/pkg %s", 6757 resp->active_pkg_name); 6758 bp->fw_cap |= BNXT_FW_CAP_PKG_VER; 6759 } 6760 6761 bp->hwrm_cmd_timeout = le16_to_cpu(resp->def_req_timeout); 6762 if (!bp->hwrm_cmd_timeout) 6763 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT; 6764 6765 if (resp->hwrm_intf_maj_8b >= 1) { 6766 bp->hwrm_max_req_len = le16_to_cpu(resp->max_req_win_len); 6767 bp->hwrm_max_ext_req_len = le16_to_cpu(resp->max_ext_req_len); 6768 } 6769 if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN) 6770 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN; 6771 6772 bp->chip_num = le16_to_cpu(resp->chip_num); 6773 if (bp->chip_num == CHIP_NUM_58700 && !resp->chip_rev && 6774 !resp->chip_metal) 6775 bp->flags |= BNXT_FLAG_CHIP_NITRO_A0; 6776 6777 dev_caps_cfg = le32_to_cpu(resp->dev_caps_cfg); 6778 if ((dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) && 6779 (dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) 6780 bp->fw_cap |= BNXT_FW_CAP_SHORT_CMD; 6781 6782 if (dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) 6783 bp->fw_cap |= BNXT_FW_CAP_KONG_MB_CHNL; 6784 6785 if (dev_caps_cfg & 6786 VER_GET_RESP_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED) 6787 bp->fw_cap |= BNXT_FW_CAP_OVS_64BIT_HANDLE; 6788 6789 if (dev_caps_cfg & 6790 VER_GET_RESP_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED) 6791 bp->fw_cap |= BNXT_FW_CAP_TRUSTED_VF; 6792 6793 if (dev_caps_cfg & 6794 VER_GET_RESP_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED) 6795 bp->fw_cap |= BNXT_FW_CAP_CFA_ADV_FLOW; 6796 6797 hwrm_ver_get_exit: 6798 mutex_unlock(&bp->hwrm_cmd_lock); 6799 return rc; 6800 } 6801 6802 int bnxt_hwrm_fw_set_time(struct bnxt *bp) 6803 { 6804 struct hwrm_fw_set_time_input req = {0}; 6805 struct tm tm; 6806 time64_t now = ktime_get_real_seconds(); 6807 6808 if ((BNXT_VF(bp) && bp->hwrm_spec_code < 0x10901) || 6809 bp->hwrm_spec_code < 0x10400) 6810 return -EOPNOTSUPP; 6811 6812 time64_to_tm(now, 0, &tm); 6813 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FW_SET_TIME, -1, -1); 6814 req.year = cpu_to_le16(1900 + tm.tm_year); 6815 req.month = 1 + tm.tm_mon; 6816 req.day = tm.tm_mday; 6817 req.hour = tm.tm_hour; 6818 req.minute = tm.tm_min; 6819 req.second = tm.tm_sec; 6820 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 6821 } 6822 6823 static int bnxt_hwrm_port_qstats(struct bnxt *bp) 6824 { 6825 int rc; 6826 struct bnxt_pf_info *pf = &bp->pf; 6827 struct hwrm_port_qstats_input req = {0}; 6828 6829 if (!(bp->flags & BNXT_FLAG_PORT_STATS)) 6830 return 0; 6831 6832 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_QSTATS, -1, -1); 6833 req.port_id = cpu_to_le16(pf->port_id); 6834 req.tx_stat_host_addr = cpu_to_le64(bp->hw_tx_port_stats_map); 6835 req.rx_stat_host_addr = cpu_to_le64(bp->hw_rx_port_stats_map); 6836 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 6837 return rc; 6838 } 6839 6840 static int bnxt_hwrm_port_qstats_ext(struct bnxt *bp) 6841 { 6842 struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr; 6843 struct hwrm_queue_pri2cos_qcfg_input req2 = {0}; 6844 struct hwrm_port_qstats_ext_input req = {0}; 6845 struct bnxt_pf_info *pf = &bp->pf; 6846 u32 tx_stat_size; 6847 int rc; 6848 6849 if (!(bp->flags & BNXT_FLAG_PORT_STATS_EXT)) 6850 return 0; 6851 6852 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_QSTATS_EXT, -1, -1); 6853 req.port_id = cpu_to_le16(pf->port_id); 6854 req.rx_stat_size = cpu_to_le16(sizeof(struct rx_port_stats_ext)); 6855 req.rx_stat_host_addr = cpu_to_le64(bp->hw_rx_port_stats_ext_map); 6856 tx_stat_size = bp->hw_tx_port_stats_ext ? 6857 sizeof(*bp->hw_tx_port_stats_ext) : 0; 6858 req.tx_stat_size = cpu_to_le16(tx_stat_size); 6859 req.tx_stat_host_addr = cpu_to_le64(bp->hw_tx_port_stats_ext_map); 6860 mutex_lock(&bp->hwrm_cmd_lock); 6861 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 6862 if (!rc) { 6863 bp->fw_rx_stats_ext_size = le16_to_cpu(resp->rx_stat_size) / 8; 6864 bp->fw_tx_stats_ext_size = tx_stat_size ? 6865 le16_to_cpu(resp->tx_stat_size) / 8 : 0; 6866 } else { 6867 bp->fw_rx_stats_ext_size = 0; 6868 bp->fw_tx_stats_ext_size = 0; 6869 } 6870 if (bp->fw_tx_stats_ext_size <= 6871 offsetof(struct tx_port_stats_ext, pfc_pri0_tx_duration_us) / 8) { 6872 mutex_unlock(&bp->hwrm_cmd_lock); 6873 bp->pri2cos_valid = 0; 6874 return rc; 6875 } 6876 6877 bnxt_hwrm_cmd_hdr_init(bp, &req2, HWRM_QUEUE_PRI2COS_QCFG, -1, -1); 6878 req2.flags = cpu_to_le32(QUEUE_PRI2COS_QCFG_REQ_FLAGS_IVLAN); 6879 6880 rc = _hwrm_send_message(bp, &req2, sizeof(req2), HWRM_CMD_TIMEOUT); 6881 if (!rc) { 6882 struct hwrm_queue_pri2cos_qcfg_output *resp2; 6883 u8 *pri2cos; 6884 int i, j; 6885 6886 resp2 = bp->hwrm_cmd_resp_addr; 6887 pri2cos = &resp2->pri0_cos_queue_id; 6888 for (i = 0; i < 8; i++) { 6889 u8 queue_id = pri2cos[i]; 6890 6891 for (j = 0; j < bp->max_q; j++) { 6892 if (bp->q_ids[j] == queue_id) 6893 bp->pri2cos[i] = j; 6894 } 6895 } 6896 bp->pri2cos_valid = 1; 6897 } 6898 mutex_unlock(&bp->hwrm_cmd_lock); 6899 return rc; 6900 } 6901 6902 static int bnxt_hwrm_pcie_qstats(struct bnxt *bp) 6903 { 6904 struct hwrm_pcie_qstats_input req = {0}; 6905 6906 if (!(bp->flags & BNXT_FLAG_PCIE_STATS)) 6907 return 0; 6908 6909 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PCIE_QSTATS, -1, -1); 6910 req.pcie_stat_size = cpu_to_le16(sizeof(struct pcie_ctx_hw_stats)); 6911 req.pcie_stat_host_addr = cpu_to_le64(bp->hw_pcie_stats_map); 6912 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 6913 } 6914 6915 static void bnxt_hwrm_free_tunnel_ports(struct bnxt *bp) 6916 { 6917 if (bp->vxlan_port_cnt) { 6918 bnxt_hwrm_tunnel_dst_port_free( 6919 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN); 6920 } 6921 bp->vxlan_port_cnt = 0; 6922 if (bp->nge_port_cnt) { 6923 bnxt_hwrm_tunnel_dst_port_free( 6924 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE); 6925 } 6926 bp->nge_port_cnt = 0; 6927 } 6928 6929 static int bnxt_set_tpa(struct bnxt *bp, bool set_tpa) 6930 { 6931 int rc, i; 6932 u32 tpa_flags = 0; 6933 6934 if (set_tpa) 6935 tpa_flags = bp->flags & BNXT_FLAG_TPA; 6936 for (i = 0; i < bp->nr_vnics; i++) { 6937 rc = bnxt_hwrm_vnic_set_tpa(bp, i, tpa_flags); 6938 if (rc) { 6939 netdev_err(bp->dev, "hwrm vnic set tpa failure rc for vnic %d: %x\n", 6940 i, rc); 6941 return rc; 6942 } 6943 } 6944 return 0; 6945 } 6946 6947 static void bnxt_hwrm_clear_vnic_rss(struct bnxt *bp) 6948 { 6949 int i; 6950 6951 for (i = 0; i < bp->nr_vnics; i++) 6952 bnxt_hwrm_vnic_set_rss(bp, i, false); 6953 } 6954 6955 static void bnxt_hwrm_resource_free(struct bnxt *bp, bool close_path, 6956 bool irq_re_init) 6957 { 6958 if (bp->vnic_info) { 6959 bnxt_hwrm_clear_vnic_filter(bp); 6960 /* clear all RSS setting before free vnic ctx */ 6961 bnxt_hwrm_clear_vnic_rss(bp); 6962 bnxt_hwrm_vnic_ctx_free(bp); 6963 /* before free the vnic, undo the vnic tpa settings */ 6964 if (bp->flags & BNXT_FLAG_TPA) 6965 bnxt_set_tpa(bp, false); 6966 bnxt_hwrm_vnic_free(bp); 6967 } 6968 bnxt_hwrm_ring_free(bp, close_path); 6969 bnxt_hwrm_ring_grp_free(bp); 6970 if (irq_re_init) { 6971 bnxt_hwrm_stat_ctx_free(bp); 6972 bnxt_hwrm_free_tunnel_ports(bp); 6973 } 6974 } 6975 6976 static int bnxt_hwrm_set_br_mode(struct bnxt *bp, u16 br_mode) 6977 { 6978 struct hwrm_func_cfg_input req = {0}; 6979 int rc; 6980 6981 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1); 6982 req.fid = cpu_to_le16(0xffff); 6983 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_EVB_MODE); 6984 if (br_mode == BRIDGE_MODE_VEB) 6985 req.evb_mode = FUNC_CFG_REQ_EVB_MODE_VEB; 6986 else if (br_mode == BRIDGE_MODE_VEPA) 6987 req.evb_mode = FUNC_CFG_REQ_EVB_MODE_VEPA; 6988 else 6989 return -EINVAL; 6990 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 6991 if (rc) 6992 rc = -EIO; 6993 return rc; 6994 } 6995 6996 static int bnxt_hwrm_set_cache_line_size(struct bnxt *bp, int size) 6997 { 6998 struct hwrm_func_cfg_input req = {0}; 6999 int rc; 7000 7001 if (BNXT_VF(bp) || bp->hwrm_spec_code < 0x10803) 7002 return 0; 7003 7004 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1); 7005 req.fid = cpu_to_le16(0xffff); 7006 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_CACHE_LINESIZE); 7007 req.options = FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_64; 7008 if (size == 128) 7009 req.options = FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128; 7010 7011 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 7012 if (rc) 7013 rc = -EIO; 7014 return rc; 7015 } 7016 7017 static int __bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id) 7018 { 7019 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 7020 int rc; 7021 7022 if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG) 7023 goto skip_rss_ctx; 7024 7025 /* allocate context for vnic */ 7026 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 0); 7027 if (rc) { 7028 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n", 7029 vnic_id, rc); 7030 goto vnic_setup_err; 7031 } 7032 bp->rsscos_nr_ctxs++; 7033 7034 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) { 7035 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 1); 7036 if (rc) { 7037 netdev_err(bp->dev, "hwrm vnic %d cos ctx alloc failure rc: %x\n", 7038 vnic_id, rc); 7039 goto vnic_setup_err; 7040 } 7041 bp->rsscos_nr_ctxs++; 7042 } 7043 7044 skip_rss_ctx: 7045 /* configure default vnic, ring grp */ 7046 rc = bnxt_hwrm_vnic_cfg(bp, vnic_id); 7047 if (rc) { 7048 netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n", 7049 vnic_id, rc); 7050 goto vnic_setup_err; 7051 } 7052 7053 /* Enable RSS hashing on vnic */ 7054 rc = bnxt_hwrm_vnic_set_rss(bp, vnic_id, true); 7055 if (rc) { 7056 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %x\n", 7057 vnic_id, rc); 7058 goto vnic_setup_err; 7059 } 7060 7061 if (bp->flags & BNXT_FLAG_AGG_RINGS) { 7062 rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id); 7063 if (rc) { 7064 netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n", 7065 vnic_id, rc); 7066 } 7067 } 7068 7069 vnic_setup_err: 7070 return rc; 7071 } 7072 7073 static int __bnxt_setup_vnic_p5(struct bnxt *bp, u16 vnic_id) 7074 { 7075 int rc, i, nr_ctxs; 7076 7077 nr_ctxs = DIV_ROUND_UP(bp->rx_nr_rings, 64); 7078 for (i = 0; i < nr_ctxs; i++) { 7079 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, i); 7080 if (rc) { 7081 netdev_err(bp->dev, "hwrm vnic %d ctx %d alloc failure rc: %x\n", 7082 vnic_id, i, rc); 7083 break; 7084 } 7085 bp->rsscos_nr_ctxs++; 7086 } 7087 if (i < nr_ctxs) 7088 return -ENOMEM; 7089 7090 rc = bnxt_hwrm_vnic_set_rss_p5(bp, vnic_id, true); 7091 if (rc) { 7092 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %d\n", 7093 vnic_id, rc); 7094 return rc; 7095 } 7096 rc = bnxt_hwrm_vnic_cfg(bp, vnic_id); 7097 if (rc) { 7098 netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n", 7099 vnic_id, rc); 7100 return rc; 7101 } 7102 if (bp->flags & BNXT_FLAG_AGG_RINGS) { 7103 rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id); 7104 if (rc) { 7105 netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n", 7106 vnic_id, rc); 7107 } 7108 } 7109 return rc; 7110 } 7111 7112 static int bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id) 7113 { 7114 if (bp->flags & BNXT_FLAG_CHIP_P5) 7115 return __bnxt_setup_vnic_p5(bp, vnic_id); 7116 else 7117 return __bnxt_setup_vnic(bp, vnic_id); 7118 } 7119 7120 static int bnxt_alloc_rfs_vnics(struct bnxt *bp) 7121 { 7122 #ifdef CONFIG_RFS_ACCEL 7123 int i, rc = 0; 7124 7125 for (i = 0; i < bp->rx_nr_rings; i++) { 7126 struct bnxt_vnic_info *vnic; 7127 u16 vnic_id = i + 1; 7128 u16 ring_id = i; 7129 7130 if (vnic_id >= bp->nr_vnics) 7131 break; 7132 7133 vnic = &bp->vnic_info[vnic_id]; 7134 vnic->flags |= BNXT_VNIC_RFS_FLAG; 7135 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP) 7136 vnic->flags |= BNXT_VNIC_RFS_NEW_RSS_FLAG; 7137 rc = bnxt_hwrm_vnic_alloc(bp, vnic_id, ring_id, 1); 7138 if (rc) { 7139 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n", 7140 vnic_id, rc); 7141 break; 7142 } 7143 rc = bnxt_setup_vnic(bp, vnic_id); 7144 if (rc) 7145 break; 7146 } 7147 return rc; 7148 #else 7149 return 0; 7150 #endif 7151 } 7152 7153 /* Allow PF and VF with default VLAN to be in promiscuous mode */ 7154 static bool bnxt_promisc_ok(struct bnxt *bp) 7155 { 7156 #ifdef CONFIG_BNXT_SRIOV 7157 if (BNXT_VF(bp) && !bp->vf.vlan) 7158 return false; 7159 #endif 7160 return true; 7161 } 7162 7163 static int bnxt_setup_nitroa0_vnic(struct bnxt *bp) 7164 { 7165 unsigned int rc = 0; 7166 7167 rc = bnxt_hwrm_vnic_alloc(bp, 1, bp->rx_nr_rings - 1, 1); 7168 if (rc) { 7169 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n", 7170 rc); 7171 return rc; 7172 } 7173 7174 rc = bnxt_hwrm_vnic_cfg(bp, 1); 7175 if (rc) { 7176 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n", 7177 rc); 7178 return rc; 7179 } 7180 return rc; 7181 } 7182 7183 static int bnxt_cfg_rx_mode(struct bnxt *); 7184 static bool bnxt_mc_list_updated(struct bnxt *, u32 *); 7185 7186 static int bnxt_init_chip(struct bnxt *bp, bool irq_re_init) 7187 { 7188 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 7189 int rc = 0; 7190 unsigned int rx_nr_rings = bp->rx_nr_rings; 7191 7192 if (irq_re_init) { 7193 rc = bnxt_hwrm_stat_ctx_alloc(bp); 7194 if (rc) { 7195 netdev_err(bp->dev, "hwrm stat ctx alloc failure rc: %x\n", 7196 rc); 7197 goto err_out; 7198 } 7199 } 7200 7201 rc = bnxt_hwrm_ring_alloc(bp); 7202 if (rc) { 7203 netdev_err(bp->dev, "hwrm ring alloc failure rc: %x\n", rc); 7204 goto err_out; 7205 } 7206 7207 rc = bnxt_hwrm_ring_grp_alloc(bp); 7208 if (rc) { 7209 netdev_err(bp->dev, "hwrm_ring_grp alloc failure: %x\n", rc); 7210 goto err_out; 7211 } 7212 7213 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 7214 rx_nr_rings--; 7215 7216 /* default vnic 0 */ 7217 rc = bnxt_hwrm_vnic_alloc(bp, 0, 0, rx_nr_rings); 7218 if (rc) { 7219 netdev_err(bp->dev, "hwrm vnic alloc failure rc: %x\n", rc); 7220 goto err_out; 7221 } 7222 7223 rc = bnxt_setup_vnic(bp, 0); 7224 if (rc) 7225 goto err_out; 7226 7227 if (bp->flags & BNXT_FLAG_RFS) { 7228 rc = bnxt_alloc_rfs_vnics(bp); 7229 if (rc) 7230 goto err_out; 7231 } 7232 7233 if (bp->flags & BNXT_FLAG_TPA) { 7234 rc = bnxt_set_tpa(bp, true); 7235 if (rc) 7236 goto err_out; 7237 } 7238 7239 if (BNXT_VF(bp)) 7240 bnxt_update_vf_mac(bp); 7241 7242 /* Filter for default vnic 0 */ 7243 rc = bnxt_hwrm_set_vnic_filter(bp, 0, 0, bp->dev->dev_addr); 7244 if (rc) { 7245 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n", rc); 7246 goto err_out; 7247 } 7248 vnic->uc_filter_count = 1; 7249 7250 vnic->rx_mask = 0; 7251 if (bp->dev->flags & IFF_BROADCAST) 7252 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_BCAST; 7253 7254 if ((bp->dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp)) 7255 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS; 7256 7257 if (bp->dev->flags & IFF_ALLMULTI) { 7258 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST; 7259 vnic->mc_list_count = 0; 7260 } else { 7261 u32 mask = 0; 7262 7263 bnxt_mc_list_updated(bp, &mask); 7264 vnic->rx_mask |= mask; 7265 } 7266 7267 rc = bnxt_cfg_rx_mode(bp); 7268 if (rc) 7269 goto err_out; 7270 7271 rc = bnxt_hwrm_set_coal(bp); 7272 if (rc) 7273 netdev_warn(bp->dev, "HWRM set coalescing failure rc: %x\n", 7274 rc); 7275 7276 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) { 7277 rc = bnxt_setup_nitroa0_vnic(bp); 7278 if (rc) 7279 netdev_err(bp->dev, "Special vnic setup failure for NS2 A0 rc: %x\n", 7280 rc); 7281 } 7282 7283 if (BNXT_VF(bp)) { 7284 bnxt_hwrm_func_qcfg(bp); 7285 netdev_update_features(bp->dev); 7286 } 7287 7288 return 0; 7289 7290 err_out: 7291 bnxt_hwrm_resource_free(bp, 0, true); 7292 7293 return rc; 7294 } 7295 7296 static int bnxt_shutdown_nic(struct bnxt *bp, bool irq_re_init) 7297 { 7298 bnxt_hwrm_resource_free(bp, 1, irq_re_init); 7299 return 0; 7300 } 7301 7302 static int bnxt_init_nic(struct bnxt *bp, bool irq_re_init) 7303 { 7304 bnxt_init_cp_rings(bp); 7305 bnxt_init_rx_rings(bp); 7306 bnxt_init_tx_rings(bp); 7307 bnxt_init_ring_grps(bp, irq_re_init); 7308 bnxt_init_vnics(bp); 7309 7310 return bnxt_init_chip(bp, irq_re_init); 7311 } 7312 7313 static int bnxt_set_real_num_queues(struct bnxt *bp) 7314 { 7315 int rc; 7316 struct net_device *dev = bp->dev; 7317 7318 rc = netif_set_real_num_tx_queues(dev, bp->tx_nr_rings - 7319 bp->tx_nr_rings_xdp); 7320 if (rc) 7321 return rc; 7322 7323 rc = netif_set_real_num_rx_queues(dev, bp->rx_nr_rings); 7324 if (rc) 7325 return rc; 7326 7327 #ifdef CONFIG_RFS_ACCEL 7328 if (bp->flags & BNXT_FLAG_RFS) 7329 dev->rx_cpu_rmap = alloc_irq_cpu_rmap(bp->rx_nr_rings); 7330 #endif 7331 7332 return rc; 7333 } 7334 7335 static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max, 7336 bool shared) 7337 { 7338 int _rx = *rx, _tx = *tx; 7339 7340 if (shared) { 7341 *rx = min_t(int, _rx, max); 7342 *tx = min_t(int, _tx, max); 7343 } else { 7344 if (max < 2) 7345 return -ENOMEM; 7346 7347 while (_rx + _tx > max) { 7348 if (_rx > _tx && _rx > 1) 7349 _rx--; 7350 else if (_tx > 1) 7351 _tx--; 7352 } 7353 *rx = _rx; 7354 *tx = _tx; 7355 } 7356 return 0; 7357 } 7358 7359 static void bnxt_setup_msix(struct bnxt *bp) 7360 { 7361 const int len = sizeof(bp->irq_tbl[0].name); 7362 struct net_device *dev = bp->dev; 7363 int tcs, i; 7364 7365 tcs = netdev_get_num_tc(dev); 7366 if (tcs > 1) { 7367 int i, off, count; 7368 7369 for (i = 0; i < tcs; i++) { 7370 count = bp->tx_nr_rings_per_tc; 7371 off = i * count; 7372 netdev_set_tc_queue(dev, i, count, off); 7373 } 7374 } 7375 7376 for (i = 0; i < bp->cp_nr_rings; i++) { 7377 int map_idx = bnxt_cp_num_to_irq_num(bp, i); 7378 char *attr; 7379 7380 if (bp->flags & BNXT_FLAG_SHARED_RINGS) 7381 attr = "TxRx"; 7382 else if (i < bp->rx_nr_rings) 7383 attr = "rx"; 7384 else 7385 attr = "tx"; 7386 7387 snprintf(bp->irq_tbl[map_idx].name, len, "%s-%s-%d", dev->name, 7388 attr, i); 7389 bp->irq_tbl[map_idx].handler = bnxt_msix; 7390 } 7391 } 7392 7393 static void bnxt_setup_inta(struct bnxt *bp) 7394 { 7395 const int len = sizeof(bp->irq_tbl[0].name); 7396 7397 if (netdev_get_num_tc(bp->dev)) 7398 netdev_reset_tc(bp->dev); 7399 7400 snprintf(bp->irq_tbl[0].name, len, "%s-%s-%d", bp->dev->name, "TxRx", 7401 0); 7402 bp->irq_tbl[0].handler = bnxt_inta; 7403 } 7404 7405 static int bnxt_setup_int_mode(struct bnxt *bp) 7406 { 7407 int rc; 7408 7409 if (bp->flags & BNXT_FLAG_USING_MSIX) 7410 bnxt_setup_msix(bp); 7411 else 7412 bnxt_setup_inta(bp); 7413 7414 rc = bnxt_set_real_num_queues(bp); 7415 return rc; 7416 } 7417 7418 #ifdef CONFIG_RFS_ACCEL 7419 static unsigned int bnxt_get_max_func_rss_ctxs(struct bnxt *bp) 7420 { 7421 return bp->hw_resc.max_rsscos_ctxs; 7422 } 7423 7424 static unsigned int bnxt_get_max_func_vnics(struct bnxt *bp) 7425 { 7426 return bp->hw_resc.max_vnics; 7427 } 7428 #endif 7429 7430 unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt *bp) 7431 { 7432 return bp->hw_resc.max_stat_ctxs; 7433 } 7434 7435 unsigned int bnxt_get_max_func_cp_rings(struct bnxt *bp) 7436 { 7437 return bp->hw_resc.max_cp_rings; 7438 } 7439 7440 static unsigned int bnxt_get_max_func_cp_rings_for_en(struct bnxt *bp) 7441 { 7442 unsigned int cp = bp->hw_resc.max_cp_rings; 7443 7444 if (!(bp->flags & BNXT_FLAG_CHIP_P5)) 7445 cp -= bnxt_get_ulp_msix_num(bp); 7446 7447 return cp; 7448 } 7449 7450 static unsigned int bnxt_get_max_func_irqs(struct bnxt *bp) 7451 { 7452 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 7453 7454 if (bp->flags & BNXT_FLAG_CHIP_P5) 7455 return min_t(unsigned int, hw_resc->max_irqs, hw_resc->max_nqs); 7456 7457 return min_t(unsigned int, hw_resc->max_irqs, hw_resc->max_cp_rings); 7458 } 7459 7460 static void bnxt_set_max_func_irqs(struct bnxt *bp, unsigned int max_irqs) 7461 { 7462 bp->hw_resc.max_irqs = max_irqs; 7463 } 7464 7465 unsigned int bnxt_get_avail_cp_rings_for_en(struct bnxt *bp) 7466 { 7467 unsigned int cp; 7468 7469 cp = bnxt_get_max_func_cp_rings_for_en(bp); 7470 if (bp->flags & BNXT_FLAG_CHIP_P5) 7471 return cp - bp->rx_nr_rings - bp->tx_nr_rings; 7472 else 7473 return cp - bp->cp_nr_rings; 7474 } 7475 7476 unsigned int bnxt_get_avail_stat_ctxs_for_en(struct bnxt *bp) 7477 { 7478 unsigned int stat; 7479 7480 stat = bnxt_get_max_func_stat_ctxs(bp) - bnxt_get_ulp_stat_ctxs(bp); 7481 stat -= bp->cp_nr_rings; 7482 return stat; 7483 } 7484 7485 int bnxt_get_avail_msix(struct bnxt *bp, int num) 7486 { 7487 int max_cp = bnxt_get_max_func_cp_rings(bp); 7488 int max_irq = bnxt_get_max_func_irqs(bp); 7489 int total_req = bp->cp_nr_rings + num; 7490 int max_idx, avail_msix; 7491 7492 max_idx = bp->total_irqs; 7493 if (!(bp->flags & BNXT_FLAG_CHIP_P5)) 7494 max_idx = min_t(int, bp->total_irqs, max_cp); 7495 avail_msix = max_idx - bp->cp_nr_rings; 7496 if (!BNXT_NEW_RM(bp) || avail_msix >= num) 7497 return avail_msix; 7498 7499 if (max_irq < total_req) { 7500 num = max_irq - bp->cp_nr_rings; 7501 if (num <= 0) 7502 return 0; 7503 } 7504 return num; 7505 } 7506 7507 static int bnxt_get_num_msix(struct bnxt *bp) 7508 { 7509 if (!BNXT_NEW_RM(bp)) 7510 return bnxt_get_max_func_irqs(bp); 7511 7512 return bnxt_nq_rings_in_use(bp); 7513 } 7514 7515 static int bnxt_init_msix(struct bnxt *bp) 7516 { 7517 int i, total_vecs, max, rc = 0, min = 1, ulp_msix; 7518 struct msix_entry *msix_ent; 7519 7520 total_vecs = bnxt_get_num_msix(bp); 7521 max = bnxt_get_max_func_irqs(bp); 7522 if (total_vecs > max) 7523 total_vecs = max; 7524 7525 if (!total_vecs) 7526 return 0; 7527 7528 msix_ent = kcalloc(total_vecs, sizeof(struct msix_entry), GFP_KERNEL); 7529 if (!msix_ent) 7530 return -ENOMEM; 7531 7532 for (i = 0; i < total_vecs; i++) { 7533 msix_ent[i].entry = i; 7534 msix_ent[i].vector = 0; 7535 } 7536 7537 if (!(bp->flags & BNXT_FLAG_SHARED_RINGS)) 7538 min = 2; 7539 7540 total_vecs = pci_enable_msix_range(bp->pdev, msix_ent, min, total_vecs); 7541 ulp_msix = bnxt_get_ulp_msix_num(bp); 7542 if (total_vecs < 0 || total_vecs < ulp_msix) { 7543 rc = -ENODEV; 7544 goto msix_setup_exit; 7545 } 7546 7547 bp->irq_tbl = kcalloc(total_vecs, sizeof(struct bnxt_irq), GFP_KERNEL); 7548 if (bp->irq_tbl) { 7549 for (i = 0; i < total_vecs; i++) 7550 bp->irq_tbl[i].vector = msix_ent[i].vector; 7551 7552 bp->total_irqs = total_vecs; 7553 /* Trim rings based upon num of vectors allocated */ 7554 rc = bnxt_trim_rings(bp, &bp->rx_nr_rings, &bp->tx_nr_rings, 7555 total_vecs - ulp_msix, min == 1); 7556 if (rc) 7557 goto msix_setup_exit; 7558 7559 bp->cp_nr_rings = (min == 1) ? 7560 max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) : 7561 bp->tx_nr_rings + bp->rx_nr_rings; 7562 7563 } else { 7564 rc = -ENOMEM; 7565 goto msix_setup_exit; 7566 } 7567 bp->flags |= BNXT_FLAG_USING_MSIX; 7568 kfree(msix_ent); 7569 return 0; 7570 7571 msix_setup_exit: 7572 netdev_err(bp->dev, "bnxt_init_msix err: %x\n", rc); 7573 kfree(bp->irq_tbl); 7574 bp->irq_tbl = NULL; 7575 pci_disable_msix(bp->pdev); 7576 kfree(msix_ent); 7577 return rc; 7578 } 7579 7580 static int bnxt_init_inta(struct bnxt *bp) 7581 { 7582 bp->irq_tbl = kcalloc(1, sizeof(struct bnxt_irq), GFP_KERNEL); 7583 if (!bp->irq_tbl) 7584 return -ENOMEM; 7585 7586 bp->total_irqs = 1; 7587 bp->rx_nr_rings = 1; 7588 bp->tx_nr_rings = 1; 7589 bp->cp_nr_rings = 1; 7590 bp->flags |= BNXT_FLAG_SHARED_RINGS; 7591 bp->irq_tbl[0].vector = bp->pdev->irq; 7592 return 0; 7593 } 7594 7595 static int bnxt_init_int_mode(struct bnxt *bp) 7596 { 7597 int rc = 0; 7598 7599 if (bp->flags & BNXT_FLAG_MSIX_CAP) 7600 rc = bnxt_init_msix(bp); 7601 7602 if (!(bp->flags & BNXT_FLAG_USING_MSIX) && BNXT_PF(bp)) { 7603 /* fallback to INTA */ 7604 rc = bnxt_init_inta(bp); 7605 } 7606 return rc; 7607 } 7608 7609 static void bnxt_clear_int_mode(struct bnxt *bp) 7610 { 7611 if (bp->flags & BNXT_FLAG_USING_MSIX) 7612 pci_disable_msix(bp->pdev); 7613 7614 kfree(bp->irq_tbl); 7615 bp->irq_tbl = NULL; 7616 bp->flags &= ~BNXT_FLAG_USING_MSIX; 7617 } 7618 7619 int bnxt_reserve_rings(struct bnxt *bp) 7620 { 7621 int tcs = netdev_get_num_tc(bp->dev); 7622 bool reinit_irq = false; 7623 int rc; 7624 7625 if (!bnxt_need_reserve_rings(bp)) 7626 return 0; 7627 7628 if (BNXT_NEW_RM(bp) && (bnxt_get_num_msix(bp) != bp->total_irqs)) { 7629 bnxt_ulp_irq_stop(bp); 7630 bnxt_clear_int_mode(bp); 7631 reinit_irq = true; 7632 } 7633 rc = __bnxt_reserve_rings(bp); 7634 if (reinit_irq) { 7635 if (!rc) 7636 rc = bnxt_init_int_mode(bp); 7637 bnxt_ulp_irq_restart(bp, rc); 7638 } 7639 if (rc) { 7640 netdev_err(bp->dev, "ring reservation/IRQ init failure rc: %d\n", rc); 7641 return rc; 7642 } 7643 if (tcs && (bp->tx_nr_rings_per_tc * tcs != bp->tx_nr_rings)) { 7644 netdev_err(bp->dev, "tx ring reservation failure\n"); 7645 netdev_reset_tc(bp->dev); 7646 bp->tx_nr_rings_per_tc = bp->tx_nr_rings; 7647 return -ENOMEM; 7648 } 7649 return 0; 7650 } 7651 7652 static void bnxt_free_irq(struct bnxt *bp) 7653 { 7654 struct bnxt_irq *irq; 7655 int i; 7656 7657 #ifdef CONFIG_RFS_ACCEL 7658 free_irq_cpu_rmap(bp->dev->rx_cpu_rmap); 7659 bp->dev->rx_cpu_rmap = NULL; 7660 #endif 7661 if (!bp->irq_tbl || !bp->bnapi) 7662 return; 7663 7664 for (i = 0; i < bp->cp_nr_rings; i++) { 7665 int map_idx = bnxt_cp_num_to_irq_num(bp, i); 7666 7667 irq = &bp->irq_tbl[map_idx]; 7668 if (irq->requested) { 7669 if (irq->have_cpumask) { 7670 irq_set_affinity_hint(irq->vector, NULL); 7671 free_cpumask_var(irq->cpu_mask); 7672 irq->have_cpumask = 0; 7673 } 7674 free_irq(irq->vector, bp->bnapi[i]); 7675 } 7676 7677 irq->requested = 0; 7678 } 7679 } 7680 7681 static int bnxt_request_irq(struct bnxt *bp) 7682 { 7683 int i, j, rc = 0; 7684 unsigned long flags = 0; 7685 #ifdef CONFIG_RFS_ACCEL 7686 struct cpu_rmap *rmap; 7687 #endif 7688 7689 rc = bnxt_setup_int_mode(bp); 7690 if (rc) { 7691 netdev_err(bp->dev, "bnxt_setup_int_mode err: %x\n", 7692 rc); 7693 return rc; 7694 } 7695 #ifdef CONFIG_RFS_ACCEL 7696 rmap = bp->dev->rx_cpu_rmap; 7697 #endif 7698 if (!(bp->flags & BNXT_FLAG_USING_MSIX)) 7699 flags = IRQF_SHARED; 7700 7701 for (i = 0, j = 0; i < bp->cp_nr_rings; i++) { 7702 int map_idx = bnxt_cp_num_to_irq_num(bp, i); 7703 struct bnxt_irq *irq = &bp->irq_tbl[map_idx]; 7704 7705 #ifdef CONFIG_RFS_ACCEL 7706 if (rmap && bp->bnapi[i]->rx_ring) { 7707 rc = irq_cpu_rmap_add(rmap, irq->vector); 7708 if (rc) 7709 netdev_warn(bp->dev, "failed adding irq rmap for ring %d\n", 7710 j); 7711 j++; 7712 } 7713 #endif 7714 rc = request_irq(irq->vector, irq->handler, flags, irq->name, 7715 bp->bnapi[i]); 7716 if (rc) 7717 break; 7718 7719 irq->requested = 1; 7720 7721 if (zalloc_cpumask_var(&irq->cpu_mask, GFP_KERNEL)) { 7722 int numa_node = dev_to_node(&bp->pdev->dev); 7723 7724 irq->have_cpumask = 1; 7725 cpumask_set_cpu(cpumask_local_spread(i, numa_node), 7726 irq->cpu_mask); 7727 rc = irq_set_affinity_hint(irq->vector, irq->cpu_mask); 7728 if (rc) { 7729 netdev_warn(bp->dev, 7730 "Set affinity failed, IRQ = %d\n", 7731 irq->vector); 7732 break; 7733 } 7734 } 7735 } 7736 return rc; 7737 } 7738 7739 static void bnxt_del_napi(struct bnxt *bp) 7740 { 7741 int i; 7742 7743 if (!bp->bnapi) 7744 return; 7745 7746 for (i = 0; i < bp->cp_nr_rings; i++) { 7747 struct bnxt_napi *bnapi = bp->bnapi[i]; 7748 7749 napi_hash_del(&bnapi->napi); 7750 netif_napi_del(&bnapi->napi); 7751 } 7752 /* We called napi_hash_del() before netif_napi_del(), we need 7753 * to respect an RCU grace period before freeing napi structures. 7754 */ 7755 synchronize_net(); 7756 } 7757 7758 static void bnxt_init_napi(struct bnxt *bp) 7759 { 7760 int i; 7761 unsigned int cp_nr_rings = bp->cp_nr_rings; 7762 struct bnxt_napi *bnapi; 7763 7764 if (bp->flags & BNXT_FLAG_USING_MSIX) { 7765 int (*poll_fn)(struct napi_struct *, int) = bnxt_poll; 7766 7767 if (bp->flags & BNXT_FLAG_CHIP_P5) 7768 poll_fn = bnxt_poll_p5; 7769 else if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 7770 cp_nr_rings--; 7771 for (i = 0; i < cp_nr_rings; i++) { 7772 bnapi = bp->bnapi[i]; 7773 netif_napi_add(bp->dev, &bnapi->napi, poll_fn, 64); 7774 } 7775 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) { 7776 bnapi = bp->bnapi[cp_nr_rings]; 7777 netif_napi_add(bp->dev, &bnapi->napi, 7778 bnxt_poll_nitroa0, 64); 7779 } 7780 } else { 7781 bnapi = bp->bnapi[0]; 7782 netif_napi_add(bp->dev, &bnapi->napi, bnxt_poll, 64); 7783 } 7784 } 7785 7786 static void bnxt_disable_napi(struct bnxt *bp) 7787 { 7788 int i; 7789 7790 if (!bp->bnapi) 7791 return; 7792 7793 for (i = 0; i < bp->cp_nr_rings; i++) { 7794 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring; 7795 7796 if (bp->bnapi[i]->rx_ring) 7797 cancel_work_sync(&cpr->dim.work); 7798 7799 napi_disable(&bp->bnapi[i]->napi); 7800 } 7801 } 7802 7803 static void bnxt_enable_napi(struct bnxt *bp) 7804 { 7805 int i; 7806 7807 for (i = 0; i < bp->cp_nr_rings; i++) { 7808 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring; 7809 bp->bnapi[i]->in_reset = false; 7810 7811 if (bp->bnapi[i]->rx_ring) { 7812 INIT_WORK(&cpr->dim.work, bnxt_dim_work); 7813 cpr->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE; 7814 } 7815 napi_enable(&bp->bnapi[i]->napi); 7816 } 7817 } 7818 7819 void bnxt_tx_disable(struct bnxt *bp) 7820 { 7821 int i; 7822 struct bnxt_tx_ring_info *txr; 7823 7824 if (bp->tx_ring) { 7825 for (i = 0; i < bp->tx_nr_rings; i++) { 7826 txr = &bp->tx_ring[i]; 7827 txr->dev_state = BNXT_DEV_STATE_CLOSING; 7828 } 7829 } 7830 /* Stop all TX queues */ 7831 netif_tx_disable(bp->dev); 7832 netif_carrier_off(bp->dev); 7833 } 7834 7835 void bnxt_tx_enable(struct bnxt *bp) 7836 { 7837 int i; 7838 struct bnxt_tx_ring_info *txr; 7839 7840 for (i = 0; i < bp->tx_nr_rings; i++) { 7841 txr = &bp->tx_ring[i]; 7842 txr->dev_state = 0; 7843 } 7844 netif_tx_wake_all_queues(bp->dev); 7845 if (bp->link_info.link_up) 7846 netif_carrier_on(bp->dev); 7847 } 7848 7849 static void bnxt_report_link(struct bnxt *bp) 7850 { 7851 if (bp->link_info.link_up) { 7852 const char *duplex; 7853 const char *flow_ctrl; 7854 u32 speed; 7855 u16 fec; 7856 7857 netif_carrier_on(bp->dev); 7858 if (bp->link_info.duplex == BNXT_LINK_DUPLEX_FULL) 7859 duplex = "full"; 7860 else 7861 duplex = "half"; 7862 if (bp->link_info.pause == BNXT_LINK_PAUSE_BOTH) 7863 flow_ctrl = "ON - receive & transmit"; 7864 else if (bp->link_info.pause == BNXT_LINK_PAUSE_TX) 7865 flow_ctrl = "ON - transmit"; 7866 else if (bp->link_info.pause == BNXT_LINK_PAUSE_RX) 7867 flow_ctrl = "ON - receive"; 7868 else 7869 flow_ctrl = "none"; 7870 speed = bnxt_fw_to_ethtool_speed(bp->link_info.link_speed); 7871 netdev_info(bp->dev, "NIC Link is Up, %u Mbps %s duplex, Flow control: %s\n", 7872 speed, duplex, flow_ctrl); 7873 if (bp->flags & BNXT_FLAG_EEE_CAP) 7874 netdev_info(bp->dev, "EEE is %s\n", 7875 bp->eee.eee_active ? "active" : 7876 "not active"); 7877 fec = bp->link_info.fec_cfg; 7878 if (!(fec & PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED)) 7879 netdev_info(bp->dev, "FEC autoneg %s encodings: %s\n", 7880 (fec & BNXT_FEC_AUTONEG) ? "on" : "off", 7881 (fec & BNXT_FEC_ENC_BASE_R) ? "BaseR" : 7882 (fec & BNXT_FEC_ENC_RS) ? "RS" : "None"); 7883 } else { 7884 netif_carrier_off(bp->dev); 7885 netdev_err(bp->dev, "NIC Link is Down\n"); 7886 } 7887 } 7888 7889 static int bnxt_hwrm_phy_qcaps(struct bnxt *bp) 7890 { 7891 int rc = 0; 7892 struct hwrm_port_phy_qcaps_input req = {0}; 7893 struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr; 7894 struct bnxt_link_info *link_info = &bp->link_info; 7895 7896 if (bp->hwrm_spec_code < 0x10201) 7897 return 0; 7898 7899 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCAPS, -1, -1); 7900 7901 mutex_lock(&bp->hwrm_cmd_lock); 7902 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 7903 if (rc) 7904 goto hwrm_phy_qcaps_exit; 7905 7906 if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED) { 7907 struct ethtool_eee *eee = &bp->eee; 7908 u16 fw_speeds = le16_to_cpu(resp->supported_speeds_eee_mode); 7909 7910 bp->flags |= BNXT_FLAG_EEE_CAP; 7911 eee->supported = _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0); 7912 bp->lpi_tmr_lo = le32_to_cpu(resp->tx_lpi_timer_low) & 7913 PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK; 7914 bp->lpi_tmr_hi = le32_to_cpu(resp->valid_tx_lpi_timer_high) & 7915 PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK; 7916 } 7917 if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_EXTERNAL_LPBK_SUPPORTED) { 7918 if (bp->test_info) 7919 bp->test_info->flags |= BNXT_TEST_FL_EXT_LPBK; 7920 } 7921 if (resp->supported_speeds_auto_mode) 7922 link_info->support_auto_speeds = 7923 le16_to_cpu(resp->supported_speeds_auto_mode); 7924 7925 bp->port_count = resp->port_cnt; 7926 7927 hwrm_phy_qcaps_exit: 7928 mutex_unlock(&bp->hwrm_cmd_lock); 7929 return rc; 7930 } 7931 7932 static int bnxt_update_link(struct bnxt *bp, bool chng_link_state) 7933 { 7934 int rc = 0; 7935 struct bnxt_link_info *link_info = &bp->link_info; 7936 struct hwrm_port_phy_qcfg_input req = {0}; 7937 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr; 7938 u8 link_up = link_info->link_up; 7939 u16 diff; 7940 7941 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCFG, -1, -1); 7942 7943 mutex_lock(&bp->hwrm_cmd_lock); 7944 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 7945 if (rc) { 7946 mutex_unlock(&bp->hwrm_cmd_lock); 7947 return rc; 7948 } 7949 7950 memcpy(&link_info->phy_qcfg_resp, resp, sizeof(*resp)); 7951 link_info->phy_link_status = resp->link; 7952 link_info->duplex = resp->duplex_cfg; 7953 if (bp->hwrm_spec_code >= 0x10800) 7954 link_info->duplex = resp->duplex_state; 7955 link_info->pause = resp->pause; 7956 link_info->auto_mode = resp->auto_mode; 7957 link_info->auto_pause_setting = resp->auto_pause; 7958 link_info->lp_pause = resp->link_partner_adv_pause; 7959 link_info->force_pause_setting = resp->force_pause; 7960 link_info->duplex_setting = resp->duplex_cfg; 7961 if (link_info->phy_link_status == BNXT_LINK_LINK) 7962 link_info->link_speed = le16_to_cpu(resp->link_speed); 7963 else 7964 link_info->link_speed = 0; 7965 link_info->force_link_speed = le16_to_cpu(resp->force_link_speed); 7966 link_info->support_speeds = le16_to_cpu(resp->support_speeds); 7967 link_info->auto_link_speeds = le16_to_cpu(resp->auto_link_speed_mask); 7968 link_info->lp_auto_link_speeds = 7969 le16_to_cpu(resp->link_partner_adv_speeds); 7970 link_info->preemphasis = le32_to_cpu(resp->preemphasis); 7971 link_info->phy_ver[0] = resp->phy_maj; 7972 link_info->phy_ver[1] = resp->phy_min; 7973 link_info->phy_ver[2] = resp->phy_bld; 7974 link_info->media_type = resp->media_type; 7975 link_info->phy_type = resp->phy_type; 7976 link_info->transceiver = resp->xcvr_pkg_type; 7977 link_info->phy_addr = resp->eee_config_phy_addr & 7978 PORT_PHY_QCFG_RESP_PHY_ADDR_MASK; 7979 link_info->module_status = resp->module_status; 7980 7981 if (bp->flags & BNXT_FLAG_EEE_CAP) { 7982 struct ethtool_eee *eee = &bp->eee; 7983 u16 fw_speeds; 7984 7985 eee->eee_active = 0; 7986 if (resp->eee_config_phy_addr & 7987 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE) { 7988 eee->eee_active = 1; 7989 fw_speeds = le16_to_cpu( 7990 resp->link_partner_adv_eee_link_speed_mask); 7991 eee->lp_advertised = 7992 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0); 7993 } 7994 7995 /* Pull initial EEE config */ 7996 if (!chng_link_state) { 7997 if (resp->eee_config_phy_addr & 7998 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED) 7999 eee->eee_enabled = 1; 8000 8001 fw_speeds = le16_to_cpu(resp->adv_eee_link_speed_mask); 8002 eee->advertised = 8003 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0); 8004 8005 if (resp->eee_config_phy_addr & 8006 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI) { 8007 __le32 tmr; 8008 8009 eee->tx_lpi_enabled = 1; 8010 tmr = resp->xcvr_identifier_type_tx_lpi_timer; 8011 eee->tx_lpi_timer = le32_to_cpu(tmr) & 8012 PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK; 8013 } 8014 } 8015 } 8016 8017 link_info->fec_cfg = PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED; 8018 if (bp->hwrm_spec_code >= 0x10504) 8019 link_info->fec_cfg = le16_to_cpu(resp->fec_cfg); 8020 8021 /* TODO: need to add more logic to report VF link */ 8022 if (chng_link_state) { 8023 if (link_info->phy_link_status == BNXT_LINK_LINK) 8024 link_info->link_up = 1; 8025 else 8026 link_info->link_up = 0; 8027 if (link_up != link_info->link_up) 8028 bnxt_report_link(bp); 8029 } else { 8030 /* alwasy link down if not require to update link state */ 8031 link_info->link_up = 0; 8032 } 8033 mutex_unlock(&bp->hwrm_cmd_lock); 8034 8035 if (!BNXT_SINGLE_PF(bp)) 8036 return 0; 8037 8038 diff = link_info->support_auto_speeds ^ link_info->advertising; 8039 if ((link_info->support_auto_speeds | diff) != 8040 link_info->support_auto_speeds) { 8041 /* An advertised speed is no longer supported, so we need to 8042 * update the advertisement settings. Caller holds RTNL 8043 * so we can modify link settings. 8044 */ 8045 link_info->advertising = link_info->support_auto_speeds; 8046 if (link_info->autoneg & BNXT_AUTONEG_SPEED) 8047 bnxt_hwrm_set_link_setting(bp, true, false); 8048 } 8049 return 0; 8050 } 8051 8052 static void bnxt_get_port_module_status(struct bnxt *bp) 8053 { 8054 struct bnxt_link_info *link_info = &bp->link_info; 8055 struct hwrm_port_phy_qcfg_output *resp = &link_info->phy_qcfg_resp; 8056 u8 module_status; 8057 8058 if (bnxt_update_link(bp, true)) 8059 return; 8060 8061 module_status = link_info->module_status; 8062 switch (module_status) { 8063 case PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX: 8064 case PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN: 8065 case PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG: 8066 netdev_warn(bp->dev, "Unqualified SFP+ module detected on port %d\n", 8067 bp->pf.port_id); 8068 if (bp->hwrm_spec_code >= 0x10201) { 8069 netdev_warn(bp->dev, "Module part number %s\n", 8070 resp->phy_vendor_partnumber); 8071 } 8072 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX) 8073 netdev_warn(bp->dev, "TX is disabled\n"); 8074 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN) 8075 netdev_warn(bp->dev, "SFP+ module is shutdown\n"); 8076 } 8077 } 8078 8079 static void 8080 bnxt_hwrm_set_pause_common(struct bnxt *bp, struct hwrm_port_phy_cfg_input *req) 8081 { 8082 if (bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) { 8083 if (bp->hwrm_spec_code >= 0x10201) 8084 req->auto_pause = 8085 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE; 8086 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX) 8087 req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX; 8088 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX) 8089 req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_TX; 8090 req->enables |= 8091 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE); 8092 } else { 8093 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX) 8094 req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_RX; 8095 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX) 8096 req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_TX; 8097 req->enables |= 8098 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE); 8099 if (bp->hwrm_spec_code >= 0x10201) { 8100 req->auto_pause = req->force_pause; 8101 req->enables |= cpu_to_le32( 8102 PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE); 8103 } 8104 } 8105 } 8106 8107 static void bnxt_hwrm_set_link_common(struct bnxt *bp, 8108 struct hwrm_port_phy_cfg_input *req) 8109 { 8110 u8 autoneg = bp->link_info.autoneg; 8111 u16 fw_link_speed = bp->link_info.req_link_speed; 8112 u16 advertising = bp->link_info.advertising; 8113 8114 if (autoneg & BNXT_AUTONEG_SPEED) { 8115 req->auto_mode |= 8116 PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK; 8117 8118 req->enables |= cpu_to_le32( 8119 PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK); 8120 req->auto_link_speed_mask = cpu_to_le16(advertising); 8121 8122 req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE); 8123 req->flags |= 8124 cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG); 8125 } else { 8126 req->force_link_speed = cpu_to_le16(fw_link_speed); 8127 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE); 8128 } 8129 8130 /* tell chimp that the setting takes effect immediately */ 8131 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESET_PHY); 8132 } 8133 8134 int bnxt_hwrm_set_pause(struct bnxt *bp) 8135 { 8136 struct hwrm_port_phy_cfg_input req = {0}; 8137 int rc; 8138 8139 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1); 8140 bnxt_hwrm_set_pause_common(bp, &req); 8141 8142 if ((bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) || 8143 bp->link_info.force_link_chng) 8144 bnxt_hwrm_set_link_common(bp, &req); 8145 8146 mutex_lock(&bp->hwrm_cmd_lock); 8147 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 8148 if (!rc && !(bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL)) { 8149 /* since changing of pause setting doesn't trigger any link 8150 * change event, the driver needs to update the current pause 8151 * result upon successfully return of the phy_cfg command 8152 */ 8153 bp->link_info.pause = 8154 bp->link_info.force_pause_setting = bp->link_info.req_flow_ctrl; 8155 bp->link_info.auto_pause_setting = 0; 8156 if (!bp->link_info.force_link_chng) 8157 bnxt_report_link(bp); 8158 } 8159 bp->link_info.force_link_chng = false; 8160 mutex_unlock(&bp->hwrm_cmd_lock); 8161 return rc; 8162 } 8163 8164 static void bnxt_hwrm_set_eee(struct bnxt *bp, 8165 struct hwrm_port_phy_cfg_input *req) 8166 { 8167 struct ethtool_eee *eee = &bp->eee; 8168 8169 if (eee->eee_enabled) { 8170 u16 eee_speeds; 8171 u32 flags = PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE; 8172 8173 if (eee->tx_lpi_enabled) 8174 flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE; 8175 else 8176 flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE; 8177 8178 req->flags |= cpu_to_le32(flags); 8179 eee_speeds = bnxt_get_fw_auto_link_speeds(eee->advertised); 8180 req->eee_link_speed_mask = cpu_to_le16(eee_speeds); 8181 req->tx_lpi_timer = cpu_to_le32(eee->tx_lpi_timer); 8182 } else { 8183 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE); 8184 } 8185 } 8186 8187 int bnxt_hwrm_set_link_setting(struct bnxt *bp, bool set_pause, bool set_eee) 8188 { 8189 struct hwrm_port_phy_cfg_input req = {0}; 8190 8191 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1); 8192 if (set_pause) 8193 bnxt_hwrm_set_pause_common(bp, &req); 8194 8195 bnxt_hwrm_set_link_common(bp, &req); 8196 8197 if (set_eee) 8198 bnxt_hwrm_set_eee(bp, &req); 8199 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 8200 } 8201 8202 static int bnxt_hwrm_shutdown_link(struct bnxt *bp) 8203 { 8204 struct hwrm_port_phy_cfg_input req = {0}; 8205 8206 if (!BNXT_SINGLE_PF(bp)) 8207 return 0; 8208 8209 if (pci_num_vf(bp->pdev)) 8210 return 0; 8211 8212 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1); 8213 req.flags = cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN); 8214 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 8215 } 8216 8217 static int bnxt_hwrm_if_change(struct bnxt *bp, bool up) 8218 { 8219 struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr; 8220 struct hwrm_func_drv_if_change_input req = {0}; 8221 bool resc_reinit = false; 8222 int rc; 8223 8224 if (!(bp->fw_cap & BNXT_FW_CAP_IF_CHANGE)) 8225 return 0; 8226 8227 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_IF_CHANGE, -1, -1); 8228 if (up) 8229 req.flags = cpu_to_le32(FUNC_DRV_IF_CHANGE_REQ_FLAGS_UP); 8230 mutex_lock(&bp->hwrm_cmd_lock); 8231 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 8232 if (!rc && (resp->flags & 8233 cpu_to_le32(FUNC_DRV_IF_CHANGE_RESP_FLAGS_RESC_CHANGE))) 8234 resc_reinit = true; 8235 mutex_unlock(&bp->hwrm_cmd_lock); 8236 8237 if (up && resc_reinit && BNXT_NEW_RM(bp)) { 8238 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 8239 8240 rc = bnxt_hwrm_func_resc_qcaps(bp, true); 8241 hw_resc->resv_cp_rings = 0; 8242 hw_resc->resv_stat_ctxs = 0; 8243 hw_resc->resv_irqs = 0; 8244 hw_resc->resv_tx_rings = 0; 8245 hw_resc->resv_rx_rings = 0; 8246 hw_resc->resv_hw_ring_grps = 0; 8247 hw_resc->resv_vnics = 0; 8248 bp->tx_nr_rings = 0; 8249 bp->rx_nr_rings = 0; 8250 } 8251 return rc; 8252 } 8253 8254 static int bnxt_hwrm_port_led_qcaps(struct bnxt *bp) 8255 { 8256 struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr; 8257 struct hwrm_port_led_qcaps_input req = {0}; 8258 struct bnxt_pf_info *pf = &bp->pf; 8259 int rc; 8260 8261 if (BNXT_VF(bp) || bp->hwrm_spec_code < 0x10601) 8262 return 0; 8263 8264 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_LED_QCAPS, -1, -1); 8265 req.port_id = cpu_to_le16(pf->port_id); 8266 mutex_lock(&bp->hwrm_cmd_lock); 8267 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 8268 if (rc) { 8269 mutex_unlock(&bp->hwrm_cmd_lock); 8270 return rc; 8271 } 8272 if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) { 8273 int i; 8274 8275 bp->num_leds = resp->num_leds; 8276 memcpy(bp->leds, &resp->led0_id, sizeof(bp->leds[0]) * 8277 bp->num_leds); 8278 for (i = 0; i < bp->num_leds; i++) { 8279 struct bnxt_led_info *led = &bp->leds[i]; 8280 __le16 caps = led->led_state_caps; 8281 8282 if (!led->led_group_id || 8283 !BNXT_LED_ALT_BLINK_CAP(caps)) { 8284 bp->num_leds = 0; 8285 break; 8286 } 8287 } 8288 } 8289 mutex_unlock(&bp->hwrm_cmd_lock); 8290 return 0; 8291 } 8292 8293 int bnxt_hwrm_alloc_wol_fltr(struct bnxt *bp) 8294 { 8295 struct hwrm_wol_filter_alloc_input req = {0}; 8296 struct hwrm_wol_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr; 8297 int rc; 8298 8299 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_ALLOC, -1, -1); 8300 req.port_id = cpu_to_le16(bp->pf.port_id); 8301 req.wol_type = WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT; 8302 req.enables = cpu_to_le32(WOL_FILTER_ALLOC_REQ_ENABLES_MAC_ADDRESS); 8303 memcpy(req.mac_address, bp->dev->dev_addr, ETH_ALEN); 8304 mutex_lock(&bp->hwrm_cmd_lock); 8305 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 8306 if (!rc) 8307 bp->wol_filter_id = resp->wol_filter_id; 8308 mutex_unlock(&bp->hwrm_cmd_lock); 8309 return rc; 8310 } 8311 8312 int bnxt_hwrm_free_wol_fltr(struct bnxt *bp) 8313 { 8314 struct hwrm_wol_filter_free_input req = {0}; 8315 int rc; 8316 8317 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_FREE, -1, -1); 8318 req.port_id = cpu_to_le16(bp->pf.port_id); 8319 req.enables = cpu_to_le32(WOL_FILTER_FREE_REQ_ENABLES_WOL_FILTER_ID); 8320 req.wol_filter_id = bp->wol_filter_id; 8321 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 8322 return rc; 8323 } 8324 8325 static u16 bnxt_hwrm_get_wol_fltrs(struct bnxt *bp, u16 handle) 8326 { 8327 struct hwrm_wol_filter_qcfg_input req = {0}; 8328 struct hwrm_wol_filter_qcfg_output *resp = bp->hwrm_cmd_resp_addr; 8329 u16 next_handle = 0; 8330 int rc; 8331 8332 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_QCFG, -1, -1); 8333 req.port_id = cpu_to_le16(bp->pf.port_id); 8334 req.handle = cpu_to_le16(handle); 8335 mutex_lock(&bp->hwrm_cmd_lock); 8336 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 8337 if (!rc) { 8338 next_handle = le16_to_cpu(resp->next_handle); 8339 if (next_handle != 0) { 8340 if (resp->wol_type == 8341 WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT) { 8342 bp->wol = 1; 8343 bp->wol_filter_id = resp->wol_filter_id; 8344 } 8345 } 8346 } 8347 mutex_unlock(&bp->hwrm_cmd_lock); 8348 return next_handle; 8349 } 8350 8351 static void bnxt_get_wol_settings(struct bnxt *bp) 8352 { 8353 u16 handle = 0; 8354 8355 if (!BNXT_PF(bp) || !(bp->flags & BNXT_FLAG_WOL_CAP)) 8356 return; 8357 8358 do { 8359 handle = bnxt_hwrm_get_wol_fltrs(bp, handle); 8360 } while (handle && handle != 0xffff); 8361 } 8362 8363 #ifdef CONFIG_BNXT_HWMON 8364 static ssize_t bnxt_show_temp(struct device *dev, 8365 struct device_attribute *devattr, char *buf) 8366 { 8367 struct hwrm_temp_monitor_query_input req = {0}; 8368 struct hwrm_temp_monitor_query_output *resp; 8369 struct bnxt *bp = dev_get_drvdata(dev); 8370 u32 temp = 0; 8371 8372 resp = bp->hwrm_cmd_resp_addr; 8373 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TEMP_MONITOR_QUERY, -1, -1); 8374 mutex_lock(&bp->hwrm_cmd_lock); 8375 if (!_hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT)) 8376 temp = resp->temp * 1000; /* display millidegree */ 8377 mutex_unlock(&bp->hwrm_cmd_lock); 8378 8379 return sprintf(buf, "%u\n", temp); 8380 } 8381 static SENSOR_DEVICE_ATTR(temp1_input, 0444, bnxt_show_temp, NULL, 0); 8382 8383 static struct attribute *bnxt_attrs[] = { 8384 &sensor_dev_attr_temp1_input.dev_attr.attr, 8385 NULL 8386 }; 8387 ATTRIBUTE_GROUPS(bnxt); 8388 8389 static void bnxt_hwmon_close(struct bnxt *bp) 8390 { 8391 if (bp->hwmon_dev) { 8392 hwmon_device_unregister(bp->hwmon_dev); 8393 bp->hwmon_dev = NULL; 8394 } 8395 } 8396 8397 static void bnxt_hwmon_open(struct bnxt *bp) 8398 { 8399 struct pci_dev *pdev = bp->pdev; 8400 8401 bp->hwmon_dev = hwmon_device_register_with_groups(&pdev->dev, 8402 DRV_MODULE_NAME, bp, 8403 bnxt_groups); 8404 if (IS_ERR(bp->hwmon_dev)) { 8405 bp->hwmon_dev = NULL; 8406 dev_warn(&pdev->dev, "Cannot register hwmon device\n"); 8407 } 8408 } 8409 #else 8410 static void bnxt_hwmon_close(struct bnxt *bp) 8411 { 8412 } 8413 8414 static void bnxt_hwmon_open(struct bnxt *bp) 8415 { 8416 } 8417 #endif 8418 8419 static bool bnxt_eee_config_ok(struct bnxt *bp) 8420 { 8421 struct ethtool_eee *eee = &bp->eee; 8422 struct bnxt_link_info *link_info = &bp->link_info; 8423 8424 if (!(bp->flags & BNXT_FLAG_EEE_CAP)) 8425 return true; 8426 8427 if (eee->eee_enabled) { 8428 u32 advertising = 8429 _bnxt_fw_to_ethtool_adv_spds(link_info->advertising, 0); 8430 8431 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) { 8432 eee->eee_enabled = 0; 8433 return false; 8434 } 8435 if (eee->advertised & ~advertising) { 8436 eee->advertised = advertising & eee->supported; 8437 return false; 8438 } 8439 } 8440 return true; 8441 } 8442 8443 static int bnxt_update_phy_setting(struct bnxt *bp) 8444 { 8445 int rc; 8446 bool update_link = false; 8447 bool update_pause = false; 8448 bool update_eee = false; 8449 struct bnxt_link_info *link_info = &bp->link_info; 8450 8451 rc = bnxt_update_link(bp, true); 8452 if (rc) { 8453 netdev_err(bp->dev, "failed to update link (rc: %x)\n", 8454 rc); 8455 return rc; 8456 } 8457 if (!BNXT_SINGLE_PF(bp)) 8458 return 0; 8459 8460 if ((link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) && 8461 (link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH) != 8462 link_info->req_flow_ctrl) 8463 update_pause = true; 8464 if (!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) && 8465 link_info->force_pause_setting != link_info->req_flow_ctrl) 8466 update_pause = true; 8467 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) { 8468 if (BNXT_AUTO_MODE(link_info->auto_mode)) 8469 update_link = true; 8470 if (link_info->req_link_speed != link_info->force_link_speed) 8471 update_link = true; 8472 if (link_info->req_duplex != link_info->duplex_setting) 8473 update_link = true; 8474 } else { 8475 if (link_info->auto_mode == BNXT_LINK_AUTO_NONE) 8476 update_link = true; 8477 if (link_info->advertising != link_info->auto_link_speeds) 8478 update_link = true; 8479 } 8480 8481 /* The last close may have shutdown the link, so need to call 8482 * PHY_CFG to bring it back up. 8483 */ 8484 if (!netif_carrier_ok(bp->dev)) 8485 update_link = true; 8486 8487 if (!bnxt_eee_config_ok(bp)) 8488 update_eee = true; 8489 8490 if (update_link) 8491 rc = bnxt_hwrm_set_link_setting(bp, update_pause, update_eee); 8492 else if (update_pause) 8493 rc = bnxt_hwrm_set_pause(bp); 8494 if (rc) { 8495 netdev_err(bp->dev, "failed to update phy setting (rc: %x)\n", 8496 rc); 8497 return rc; 8498 } 8499 8500 return rc; 8501 } 8502 8503 /* Common routine to pre-map certain register block to different GRC window. 8504 * A PF has 16 4K windows and a VF has 4 4K windows. However, only 15 windows 8505 * in PF and 3 windows in VF that can be customized to map in different 8506 * register blocks. 8507 */ 8508 static void bnxt_preset_reg_win(struct bnxt *bp) 8509 { 8510 if (BNXT_PF(bp)) { 8511 /* CAG registers map to GRC window #4 */ 8512 writel(BNXT_CAG_REG_BASE, 8513 bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 12); 8514 } 8515 } 8516 8517 static int bnxt_init_dflt_ring_mode(struct bnxt *bp); 8518 8519 static int __bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init) 8520 { 8521 int rc = 0; 8522 8523 bnxt_preset_reg_win(bp); 8524 netif_carrier_off(bp->dev); 8525 if (irq_re_init) { 8526 /* Reserve rings now if none were reserved at driver probe. */ 8527 rc = bnxt_init_dflt_ring_mode(bp); 8528 if (rc) { 8529 netdev_err(bp->dev, "Failed to reserve default rings at open\n"); 8530 return rc; 8531 } 8532 } 8533 rc = bnxt_reserve_rings(bp); 8534 if (rc) 8535 return rc; 8536 if ((bp->flags & BNXT_FLAG_RFS) && 8537 !(bp->flags & BNXT_FLAG_USING_MSIX)) { 8538 /* disable RFS if falling back to INTA */ 8539 bp->dev->hw_features &= ~NETIF_F_NTUPLE; 8540 bp->flags &= ~BNXT_FLAG_RFS; 8541 } 8542 8543 rc = bnxt_alloc_mem(bp, irq_re_init); 8544 if (rc) { 8545 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc); 8546 goto open_err_free_mem; 8547 } 8548 8549 if (irq_re_init) { 8550 bnxt_init_napi(bp); 8551 rc = bnxt_request_irq(bp); 8552 if (rc) { 8553 netdev_err(bp->dev, "bnxt_request_irq err: %x\n", rc); 8554 goto open_err_irq; 8555 } 8556 } 8557 8558 bnxt_enable_napi(bp); 8559 bnxt_debug_dev_init(bp); 8560 8561 rc = bnxt_init_nic(bp, irq_re_init); 8562 if (rc) { 8563 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc); 8564 goto open_err; 8565 } 8566 8567 if (link_re_init) { 8568 mutex_lock(&bp->link_lock); 8569 rc = bnxt_update_phy_setting(bp); 8570 mutex_unlock(&bp->link_lock); 8571 if (rc) { 8572 netdev_warn(bp->dev, "failed to update phy settings\n"); 8573 if (BNXT_SINGLE_PF(bp)) { 8574 bp->link_info.phy_retry = true; 8575 bp->link_info.phy_retry_expires = 8576 jiffies + 5 * HZ; 8577 } 8578 } 8579 } 8580 8581 if (irq_re_init) 8582 udp_tunnel_get_rx_info(bp->dev); 8583 8584 set_bit(BNXT_STATE_OPEN, &bp->state); 8585 bnxt_enable_int(bp); 8586 /* Enable TX queues */ 8587 bnxt_tx_enable(bp); 8588 mod_timer(&bp->timer, jiffies + bp->current_interval); 8589 /* Poll link status and check for SFP+ module status */ 8590 bnxt_get_port_module_status(bp); 8591 8592 /* VF-reps may need to be re-opened after the PF is re-opened */ 8593 if (BNXT_PF(bp)) 8594 bnxt_vf_reps_open(bp); 8595 return 0; 8596 8597 open_err: 8598 bnxt_debug_dev_exit(bp); 8599 bnxt_disable_napi(bp); 8600 8601 open_err_irq: 8602 bnxt_del_napi(bp); 8603 8604 open_err_free_mem: 8605 bnxt_free_skbs(bp); 8606 bnxt_free_irq(bp); 8607 bnxt_free_mem(bp, true); 8608 return rc; 8609 } 8610 8611 /* rtnl_lock held */ 8612 int bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init) 8613 { 8614 int rc = 0; 8615 8616 rc = __bnxt_open_nic(bp, irq_re_init, link_re_init); 8617 if (rc) { 8618 netdev_err(bp->dev, "nic open fail (rc: %x)\n", rc); 8619 dev_close(bp->dev); 8620 } 8621 return rc; 8622 } 8623 8624 /* rtnl_lock held, open the NIC half way by allocating all resources, but 8625 * NAPI, IRQ, and TX are not enabled. This is mainly used for offline 8626 * self tests. 8627 */ 8628 int bnxt_half_open_nic(struct bnxt *bp) 8629 { 8630 int rc = 0; 8631 8632 rc = bnxt_alloc_mem(bp, false); 8633 if (rc) { 8634 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc); 8635 goto half_open_err; 8636 } 8637 rc = bnxt_init_nic(bp, false); 8638 if (rc) { 8639 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc); 8640 goto half_open_err; 8641 } 8642 return 0; 8643 8644 half_open_err: 8645 bnxt_free_skbs(bp); 8646 bnxt_free_mem(bp, false); 8647 dev_close(bp->dev); 8648 return rc; 8649 } 8650 8651 /* rtnl_lock held, this call can only be made after a previous successful 8652 * call to bnxt_half_open_nic(). 8653 */ 8654 void bnxt_half_close_nic(struct bnxt *bp) 8655 { 8656 bnxt_hwrm_resource_free(bp, false, false); 8657 bnxt_free_skbs(bp); 8658 bnxt_free_mem(bp, false); 8659 } 8660 8661 static int bnxt_open(struct net_device *dev) 8662 { 8663 struct bnxt *bp = netdev_priv(dev); 8664 int rc; 8665 8666 bnxt_hwrm_if_change(bp, true); 8667 rc = __bnxt_open_nic(bp, true, true); 8668 if (rc) 8669 bnxt_hwrm_if_change(bp, false); 8670 8671 bnxt_hwmon_open(bp); 8672 8673 return rc; 8674 } 8675 8676 static bool bnxt_drv_busy(struct bnxt *bp) 8677 { 8678 return (test_bit(BNXT_STATE_IN_SP_TASK, &bp->state) || 8679 test_bit(BNXT_STATE_READ_STATS, &bp->state)); 8680 } 8681 8682 static void bnxt_get_ring_stats(struct bnxt *bp, 8683 struct rtnl_link_stats64 *stats); 8684 8685 static void __bnxt_close_nic(struct bnxt *bp, bool irq_re_init, 8686 bool link_re_init) 8687 { 8688 /* Close the VF-reps before closing PF */ 8689 if (BNXT_PF(bp)) 8690 bnxt_vf_reps_close(bp); 8691 8692 /* Change device state to avoid TX queue wake up's */ 8693 bnxt_tx_disable(bp); 8694 8695 clear_bit(BNXT_STATE_OPEN, &bp->state); 8696 smp_mb__after_atomic(); 8697 while (bnxt_drv_busy(bp)) 8698 msleep(20); 8699 8700 /* Flush rings and and disable interrupts */ 8701 bnxt_shutdown_nic(bp, irq_re_init); 8702 8703 /* TODO CHIMP_FW: Link/PHY related cleanup if (link_re_init) */ 8704 8705 bnxt_debug_dev_exit(bp); 8706 bnxt_disable_napi(bp); 8707 del_timer_sync(&bp->timer); 8708 bnxt_free_skbs(bp); 8709 8710 /* Save ring stats before shutdown */ 8711 if (bp->bnapi) 8712 bnxt_get_ring_stats(bp, &bp->net_stats_prev); 8713 if (irq_re_init) { 8714 bnxt_free_irq(bp); 8715 bnxt_del_napi(bp); 8716 } 8717 bnxt_free_mem(bp, irq_re_init); 8718 } 8719 8720 int bnxt_close_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init) 8721 { 8722 int rc = 0; 8723 8724 #ifdef CONFIG_BNXT_SRIOV 8725 if (bp->sriov_cfg) { 8726 rc = wait_event_interruptible_timeout(bp->sriov_cfg_wait, 8727 !bp->sriov_cfg, 8728 BNXT_SRIOV_CFG_WAIT_TMO); 8729 if (rc) 8730 netdev_warn(bp->dev, "timeout waiting for SRIOV config operation to complete!\n"); 8731 } 8732 #endif 8733 __bnxt_close_nic(bp, irq_re_init, link_re_init); 8734 return rc; 8735 } 8736 8737 static int bnxt_close(struct net_device *dev) 8738 { 8739 struct bnxt *bp = netdev_priv(dev); 8740 8741 bnxt_hwmon_close(bp); 8742 bnxt_close_nic(bp, true, true); 8743 bnxt_hwrm_shutdown_link(bp); 8744 bnxt_hwrm_if_change(bp, false); 8745 return 0; 8746 } 8747 8748 static int bnxt_hwrm_port_phy_read(struct bnxt *bp, u16 phy_addr, u16 reg, 8749 u16 *val) 8750 { 8751 struct hwrm_port_phy_mdio_read_output *resp = bp->hwrm_cmd_resp_addr; 8752 struct hwrm_port_phy_mdio_read_input req = {0}; 8753 int rc; 8754 8755 if (bp->hwrm_spec_code < 0x10a00) 8756 return -EOPNOTSUPP; 8757 8758 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_MDIO_READ, -1, -1); 8759 req.port_id = cpu_to_le16(bp->pf.port_id); 8760 req.phy_addr = phy_addr; 8761 req.reg_addr = cpu_to_le16(reg & 0x1f); 8762 if (mdio_phy_id_is_c45(phy_addr)) { 8763 req.cl45_mdio = 1; 8764 req.phy_addr = mdio_phy_id_prtad(phy_addr); 8765 req.dev_addr = mdio_phy_id_devad(phy_addr); 8766 req.reg_addr = cpu_to_le16(reg); 8767 } 8768 8769 mutex_lock(&bp->hwrm_cmd_lock); 8770 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 8771 if (!rc) 8772 *val = le16_to_cpu(resp->reg_data); 8773 mutex_unlock(&bp->hwrm_cmd_lock); 8774 return rc; 8775 } 8776 8777 static int bnxt_hwrm_port_phy_write(struct bnxt *bp, u16 phy_addr, u16 reg, 8778 u16 val) 8779 { 8780 struct hwrm_port_phy_mdio_write_input req = {0}; 8781 8782 if (bp->hwrm_spec_code < 0x10a00) 8783 return -EOPNOTSUPP; 8784 8785 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_MDIO_WRITE, -1, -1); 8786 req.port_id = cpu_to_le16(bp->pf.port_id); 8787 req.phy_addr = phy_addr; 8788 req.reg_addr = cpu_to_le16(reg & 0x1f); 8789 if (mdio_phy_id_is_c45(phy_addr)) { 8790 req.cl45_mdio = 1; 8791 req.phy_addr = mdio_phy_id_prtad(phy_addr); 8792 req.dev_addr = mdio_phy_id_devad(phy_addr); 8793 req.reg_addr = cpu_to_le16(reg); 8794 } 8795 req.reg_data = cpu_to_le16(val); 8796 8797 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 8798 } 8799 8800 /* rtnl_lock held */ 8801 static int bnxt_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 8802 { 8803 struct mii_ioctl_data *mdio = if_mii(ifr); 8804 struct bnxt *bp = netdev_priv(dev); 8805 int rc; 8806 8807 switch (cmd) { 8808 case SIOCGMIIPHY: 8809 mdio->phy_id = bp->link_info.phy_addr; 8810 8811 /* fallthru */ 8812 case SIOCGMIIREG: { 8813 u16 mii_regval = 0; 8814 8815 if (!netif_running(dev)) 8816 return -EAGAIN; 8817 8818 rc = bnxt_hwrm_port_phy_read(bp, mdio->phy_id, mdio->reg_num, 8819 &mii_regval); 8820 mdio->val_out = mii_regval; 8821 return rc; 8822 } 8823 8824 case SIOCSMIIREG: 8825 if (!netif_running(dev)) 8826 return -EAGAIN; 8827 8828 return bnxt_hwrm_port_phy_write(bp, mdio->phy_id, mdio->reg_num, 8829 mdio->val_in); 8830 8831 default: 8832 /* do nothing */ 8833 break; 8834 } 8835 return -EOPNOTSUPP; 8836 } 8837 8838 static void bnxt_get_ring_stats(struct bnxt *bp, 8839 struct rtnl_link_stats64 *stats) 8840 { 8841 int i; 8842 8843 8844 for (i = 0; i < bp->cp_nr_rings; i++) { 8845 struct bnxt_napi *bnapi = bp->bnapi[i]; 8846 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 8847 struct ctx_hw_stats *hw_stats = cpr->hw_stats; 8848 8849 stats->rx_packets += le64_to_cpu(hw_stats->rx_ucast_pkts); 8850 stats->rx_packets += le64_to_cpu(hw_stats->rx_mcast_pkts); 8851 stats->rx_packets += le64_to_cpu(hw_stats->rx_bcast_pkts); 8852 8853 stats->tx_packets += le64_to_cpu(hw_stats->tx_ucast_pkts); 8854 stats->tx_packets += le64_to_cpu(hw_stats->tx_mcast_pkts); 8855 stats->tx_packets += le64_to_cpu(hw_stats->tx_bcast_pkts); 8856 8857 stats->rx_bytes += le64_to_cpu(hw_stats->rx_ucast_bytes); 8858 stats->rx_bytes += le64_to_cpu(hw_stats->rx_mcast_bytes); 8859 stats->rx_bytes += le64_to_cpu(hw_stats->rx_bcast_bytes); 8860 8861 stats->tx_bytes += le64_to_cpu(hw_stats->tx_ucast_bytes); 8862 stats->tx_bytes += le64_to_cpu(hw_stats->tx_mcast_bytes); 8863 stats->tx_bytes += le64_to_cpu(hw_stats->tx_bcast_bytes); 8864 8865 stats->rx_missed_errors += 8866 le64_to_cpu(hw_stats->rx_discard_pkts); 8867 8868 stats->multicast += le64_to_cpu(hw_stats->rx_mcast_pkts); 8869 8870 stats->tx_dropped += le64_to_cpu(hw_stats->tx_drop_pkts); 8871 } 8872 } 8873 8874 static void bnxt_add_prev_stats(struct bnxt *bp, 8875 struct rtnl_link_stats64 *stats) 8876 { 8877 struct rtnl_link_stats64 *prev_stats = &bp->net_stats_prev; 8878 8879 stats->rx_packets += prev_stats->rx_packets; 8880 stats->tx_packets += prev_stats->tx_packets; 8881 stats->rx_bytes += prev_stats->rx_bytes; 8882 stats->tx_bytes += prev_stats->tx_bytes; 8883 stats->rx_missed_errors += prev_stats->rx_missed_errors; 8884 stats->multicast += prev_stats->multicast; 8885 stats->tx_dropped += prev_stats->tx_dropped; 8886 } 8887 8888 static void 8889 bnxt_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) 8890 { 8891 struct bnxt *bp = netdev_priv(dev); 8892 8893 set_bit(BNXT_STATE_READ_STATS, &bp->state); 8894 /* Make sure bnxt_close_nic() sees that we are reading stats before 8895 * we check the BNXT_STATE_OPEN flag. 8896 */ 8897 smp_mb__after_atomic(); 8898 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) { 8899 clear_bit(BNXT_STATE_READ_STATS, &bp->state); 8900 *stats = bp->net_stats_prev; 8901 return; 8902 } 8903 8904 bnxt_get_ring_stats(bp, stats); 8905 bnxt_add_prev_stats(bp, stats); 8906 8907 if (bp->flags & BNXT_FLAG_PORT_STATS) { 8908 struct rx_port_stats *rx = bp->hw_rx_port_stats; 8909 struct tx_port_stats *tx = bp->hw_tx_port_stats; 8910 8911 stats->rx_crc_errors = le64_to_cpu(rx->rx_fcs_err_frames); 8912 stats->rx_frame_errors = le64_to_cpu(rx->rx_align_err_frames); 8913 stats->rx_length_errors = le64_to_cpu(rx->rx_undrsz_frames) + 8914 le64_to_cpu(rx->rx_ovrsz_frames) + 8915 le64_to_cpu(rx->rx_runt_frames); 8916 stats->rx_errors = le64_to_cpu(rx->rx_false_carrier_frames) + 8917 le64_to_cpu(rx->rx_jbr_frames); 8918 stats->collisions = le64_to_cpu(tx->tx_total_collisions); 8919 stats->tx_fifo_errors = le64_to_cpu(tx->tx_fifo_underruns); 8920 stats->tx_errors = le64_to_cpu(tx->tx_err); 8921 } 8922 clear_bit(BNXT_STATE_READ_STATS, &bp->state); 8923 } 8924 8925 static bool bnxt_mc_list_updated(struct bnxt *bp, u32 *rx_mask) 8926 { 8927 struct net_device *dev = bp->dev; 8928 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 8929 struct netdev_hw_addr *ha; 8930 u8 *haddr; 8931 int mc_count = 0; 8932 bool update = false; 8933 int off = 0; 8934 8935 netdev_for_each_mc_addr(ha, dev) { 8936 if (mc_count >= BNXT_MAX_MC_ADDRS) { 8937 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST; 8938 vnic->mc_list_count = 0; 8939 return false; 8940 } 8941 haddr = ha->addr; 8942 if (!ether_addr_equal(haddr, vnic->mc_list + off)) { 8943 memcpy(vnic->mc_list + off, haddr, ETH_ALEN); 8944 update = true; 8945 } 8946 off += ETH_ALEN; 8947 mc_count++; 8948 } 8949 if (mc_count) 8950 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_MCAST; 8951 8952 if (mc_count != vnic->mc_list_count) { 8953 vnic->mc_list_count = mc_count; 8954 update = true; 8955 } 8956 return update; 8957 } 8958 8959 static bool bnxt_uc_list_updated(struct bnxt *bp) 8960 { 8961 struct net_device *dev = bp->dev; 8962 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 8963 struct netdev_hw_addr *ha; 8964 int off = 0; 8965 8966 if (netdev_uc_count(dev) != (vnic->uc_filter_count - 1)) 8967 return true; 8968 8969 netdev_for_each_uc_addr(ha, dev) { 8970 if (!ether_addr_equal(ha->addr, vnic->uc_list + off)) 8971 return true; 8972 8973 off += ETH_ALEN; 8974 } 8975 return false; 8976 } 8977 8978 static void bnxt_set_rx_mode(struct net_device *dev) 8979 { 8980 struct bnxt *bp = netdev_priv(dev); 8981 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 8982 u32 mask = vnic->rx_mask; 8983 bool mc_update = false; 8984 bool uc_update; 8985 8986 if (!netif_running(dev)) 8987 return; 8988 8989 mask &= ~(CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS | 8990 CFA_L2_SET_RX_MASK_REQ_MASK_MCAST | 8991 CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST | 8992 CFA_L2_SET_RX_MASK_REQ_MASK_BCAST); 8993 8994 if ((dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp)) 8995 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS; 8996 8997 uc_update = bnxt_uc_list_updated(bp); 8998 8999 if (dev->flags & IFF_BROADCAST) 9000 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_BCAST; 9001 if (dev->flags & IFF_ALLMULTI) { 9002 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST; 9003 vnic->mc_list_count = 0; 9004 } else { 9005 mc_update = bnxt_mc_list_updated(bp, &mask); 9006 } 9007 9008 if (mask != vnic->rx_mask || uc_update || mc_update) { 9009 vnic->rx_mask = mask; 9010 9011 set_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event); 9012 bnxt_queue_sp_work(bp); 9013 } 9014 } 9015 9016 static int bnxt_cfg_rx_mode(struct bnxt *bp) 9017 { 9018 struct net_device *dev = bp->dev; 9019 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 9020 struct netdev_hw_addr *ha; 9021 int i, off = 0, rc; 9022 bool uc_update; 9023 9024 netif_addr_lock_bh(dev); 9025 uc_update = bnxt_uc_list_updated(bp); 9026 netif_addr_unlock_bh(dev); 9027 9028 if (!uc_update) 9029 goto skip_uc; 9030 9031 mutex_lock(&bp->hwrm_cmd_lock); 9032 for (i = 1; i < vnic->uc_filter_count; i++) { 9033 struct hwrm_cfa_l2_filter_free_input req = {0}; 9034 9035 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_FREE, -1, 9036 -1); 9037 9038 req.l2_filter_id = vnic->fw_l2_filter_id[i]; 9039 9040 rc = _hwrm_send_message(bp, &req, sizeof(req), 9041 HWRM_CMD_TIMEOUT); 9042 } 9043 mutex_unlock(&bp->hwrm_cmd_lock); 9044 9045 vnic->uc_filter_count = 1; 9046 9047 netif_addr_lock_bh(dev); 9048 if (netdev_uc_count(dev) > (BNXT_MAX_UC_ADDRS - 1)) { 9049 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS; 9050 } else { 9051 netdev_for_each_uc_addr(ha, dev) { 9052 memcpy(vnic->uc_list + off, ha->addr, ETH_ALEN); 9053 off += ETH_ALEN; 9054 vnic->uc_filter_count++; 9055 } 9056 } 9057 netif_addr_unlock_bh(dev); 9058 9059 for (i = 1, off = 0; i < vnic->uc_filter_count; i++, off += ETH_ALEN) { 9060 rc = bnxt_hwrm_set_vnic_filter(bp, 0, i, vnic->uc_list + off); 9061 if (rc) { 9062 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n", 9063 rc); 9064 vnic->uc_filter_count = i; 9065 return rc; 9066 } 9067 } 9068 9069 skip_uc: 9070 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0); 9071 if (rc && vnic->mc_list_count) { 9072 netdev_info(bp->dev, "Failed setting MC filters rc: %d, turning on ALL_MCAST mode\n", 9073 rc); 9074 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST; 9075 vnic->mc_list_count = 0; 9076 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0); 9077 } 9078 if (rc) 9079 netdev_err(bp->dev, "HWRM cfa l2 rx mask failure rc: %d\n", 9080 rc); 9081 9082 return rc; 9083 } 9084 9085 static bool bnxt_can_reserve_rings(struct bnxt *bp) 9086 { 9087 #ifdef CONFIG_BNXT_SRIOV 9088 if (BNXT_NEW_RM(bp) && BNXT_VF(bp)) { 9089 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 9090 9091 /* No minimum rings were provisioned by the PF. Don't 9092 * reserve rings by default when device is down. 9093 */ 9094 if (hw_resc->min_tx_rings || hw_resc->resv_tx_rings) 9095 return true; 9096 9097 if (!netif_running(bp->dev)) 9098 return false; 9099 } 9100 #endif 9101 return true; 9102 } 9103 9104 /* If the chip and firmware supports RFS */ 9105 static bool bnxt_rfs_supported(struct bnxt *bp) 9106 { 9107 if (bp->flags & BNXT_FLAG_CHIP_P5) { 9108 if (bp->fw_cap & BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX) 9109 return true; 9110 return false; 9111 } 9112 if (BNXT_PF(bp) && !BNXT_CHIP_TYPE_NITRO_A0(bp)) 9113 return true; 9114 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP) 9115 return true; 9116 return false; 9117 } 9118 9119 /* If runtime conditions support RFS */ 9120 static bool bnxt_rfs_capable(struct bnxt *bp) 9121 { 9122 #ifdef CONFIG_RFS_ACCEL 9123 int vnics, max_vnics, max_rss_ctxs; 9124 9125 if (bp->flags & BNXT_FLAG_CHIP_P5) 9126 return bnxt_rfs_supported(bp); 9127 if (!(bp->flags & BNXT_FLAG_MSIX_CAP) || !bnxt_can_reserve_rings(bp)) 9128 return false; 9129 9130 vnics = 1 + bp->rx_nr_rings; 9131 max_vnics = bnxt_get_max_func_vnics(bp); 9132 max_rss_ctxs = bnxt_get_max_func_rss_ctxs(bp); 9133 9134 /* RSS contexts not a limiting factor */ 9135 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP) 9136 max_rss_ctxs = max_vnics; 9137 if (vnics > max_vnics || vnics > max_rss_ctxs) { 9138 if (bp->rx_nr_rings > 1) 9139 netdev_warn(bp->dev, 9140 "Not enough resources to support NTUPLE filters, enough resources for up to %d rx rings\n", 9141 min(max_rss_ctxs - 1, max_vnics - 1)); 9142 return false; 9143 } 9144 9145 if (!BNXT_NEW_RM(bp)) 9146 return true; 9147 9148 if (vnics == bp->hw_resc.resv_vnics) 9149 return true; 9150 9151 bnxt_hwrm_reserve_rings(bp, 0, 0, 0, 0, 0, vnics); 9152 if (vnics <= bp->hw_resc.resv_vnics) 9153 return true; 9154 9155 netdev_warn(bp->dev, "Unable to reserve resources to support NTUPLE filters.\n"); 9156 bnxt_hwrm_reserve_rings(bp, 0, 0, 0, 0, 0, 1); 9157 return false; 9158 #else 9159 return false; 9160 #endif 9161 } 9162 9163 static netdev_features_t bnxt_fix_features(struct net_device *dev, 9164 netdev_features_t features) 9165 { 9166 struct bnxt *bp = netdev_priv(dev); 9167 9168 if ((features & NETIF_F_NTUPLE) && !bnxt_rfs_capable(bp)) 9169 features &= ~NETIF_F_NTUPLE; 9170 9171 if (bp->flags & BNXT_FLAG_NO_AGG_RINGS) 9172 features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW); 9173 9174 if (!(features & NETIF_F_GRO)) 9175 features &= ~NETIF_F_GRO_HW; 9176 9177 if (features & NETIF_F_GRO_HW) 9178 features &= ~NETIF_F_LRO; 9179 9180 /* Both CTAG and STAG VLAN accelaration on the RX side have to be 9181 * turned on or off together. 9182 */ 9183 if ((features & (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) != 9184 (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) { 9185 if (dev->features & NETIF_F_HW_VLAN_CTAG_RX) 9186 features &= ~(NETIF_F_HW_VLAN_CTAG_RX | 9187 NETIF_F_HW_VLAN_STAG_RX); 9188 else 9189 features |= NETIF_F_HW_VLAN_CTAG_RX | 9190 NETIF_F_HW_VLAN_STAG_RX; 9191 } 9192 #ifdef CONFIG_BNXT_SRIOV 9193 if (BNXT_VF(bp)) { 9194 if (bp->vf.vlan) { 9195 features &= ~(NETIF_F_HW_VLAN_CTAG_RX | 9196 NETIF_F_HW_VLAN_STAG_RX); 9197 } 9198 } 9199 #endif 9200 return features; 9201 } 9202 9203 static int bnxt_set_features(struct net_device *dev, netdev_features_t features) 9204 { 9205 struct bnxt *bp = netdev_priv(dev); 9206 u32 flags = bp->flags; 9207 u32 changes; 9208 int rc = 0; 9209 bool re_init = false; 9210 bool update_tpa = false; 9211 9212 flags &= ~BNXT_FLAG_ALL_CONFIG_FEATS; 9213 if (features & NETIF_F_GRO_HW) 9214 flags |= BNXT_FLAG_GRO; 9215 else if (features & NETIF_F_LRO) 9216 flags |= BNXT_FLAG_LRO; 9217 9218 if (bp->flags & BNXT_FLAG_NO_AGG_RINGS) 9219 flags &= ~BNXT_FLAG_TPA; 9220 9221 if (features & NETIF_F_HW_VLAN_CTAG_RX) 9222 flags |= BNXT_FLAG_STRIP_VLAN; 9223 9224 if (features & NETIF_F_NTUPLE) 9225 flags |= BNXT_FLAG_RFS; 9226 9227 changes = flags ^ bp->flags; 9228 if (changes & BNXT_FLAG_TPA) { 9229 update_tpa = true; 9230 if ((bp->flags & BNXT_FLAG_TPA) == 0 || 9231 (flags & BNXT_FLAG_TPA) == 0) 9232 re_init = true; 9233 } 9234 9235 if (changes & ~BNXT_FLAG_TPA) 9236 re_init = true; 9237 9238 if (flags != bp->flags) { 9239 u32 old_flags = bp->flags; 9240 9241 bp->flags = flags; 9242 9243 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) { 9244 if (update_tpa) 9245 bnxt_set_ring_params(bp); 9246 return rc; 9247 } 9248 9249 if (re_init) { 9250 bnxt_close_nic(bp, false, false); 9251 if (update_tpa) 9252 bnxt_set_ring_params(bp); 9253 9254 return bnxt_open_nic(bp, false, false); 9255 } 9256 if (update_tpa) { 9257 rc = bnxt_set_tpa(bp, 9258 (flags & BNXT_FLAG_TPA) ? 9259 true : false); 9260 if (rc) 9261 bp->flags = old_flags; 9262 } 9263 } 9264 return rc; 9265 } 9266 9267 static int bnxt_dbg_hwrm_ring_info_get(struct bnxt *bp, u8 ring_type, 9268 u32 ring_id, u32 *prod, u32 *cons) 9269 { 9270 struct hwrm_dbg_ring_info_get_output *resp = bp->hwrm_cmd_resp_addr; 9271 struct hwrm_dbg_ring_info_get_input req = {0}; 9272 int rc; 9273 9274 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_DBG_RING_INFO_GET, -1, -1); 9275 req.ring_type = ring_type; 9276 req.fw_ring_id = cpu_to_le32(ring_id); 9277 mutex_lock(&bp->hwrm_cmd_lock); 9278 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 9279 if (!rc) { 9280 *prod = le32_to_cpu(resp->producer_index); 9281 *cons = le32_to_cpu(resp->consumer_index); 9282 } 9283 mutex_unlock(&bp->hwrm_cmd_lock); 9284 return rc; 9285 } 9286 9287 static void bnxt_dump_tx_sw_state(struct bnxt_napi *bnapi) 9288 { 9289 struct bnxt_tx_ring_info *txr = bnapi->tx_ring; 9290 int i = bnapi->index; 9291 9292 if (!txr) 9293 return; 9294 9295 netdev_info(bnapi->bp->dev, "[%d]: tx{fw_ring: %d prod: %x cons: %x}\n", 9296 i, txr->tx_ring_struct.fw_ring_id, txr->tx_prod, 9297 txr->tx_cons); 9298 } 9299 9300 static void bnxt_dump_rx_sw_state(struct bnxt_napi *bnapi) 9301 { 9302 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 9303 int i = bnapi->index; 9304 9305 if (!rxr) 9306 return; 9307 9308 netdev_info(bnapi->bp->dev, "[%d]: rx{fw_ring: %d prod: %x} rx_agg{fw_ring: %d agg_prod: %x sw_agg_prod: %x}\n", 9309 i, rxr->rx_ring_struct.fw_ring_id, rxr->rx_prod, 9310 rxr->rx_agg_ring_struct.fw_ring_id, rxr->rx_agg_prod, 9311 rxr->rx_sw_agg_prod); 9312 } 9313 9314 static void bnxt_dump_cp_sw_state(struct bnxt_napi *bnapi) 9315 { 9316 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 9317 int i = bnapi->index; 9318 9319 netdev_info(bnapi->bp->dev, "[%d]: cp{fw_ring: %d raw_cons: %x}\n", 9320 i, cpr->cp_ring_struct.fw_ring_id, cpr->cp_raw_cons); 9321 } 9322 9323 static void bnxt_dbg_dump_states(struct bnxt *bp) 9324 { 9325 int i; 9326 struct bnxt_napi *bnapi; 9327 9328 for (i = 0; i < bp->cp_nr_rings; i++) { 9329 bnapi = bp->bnapi[i]; 9330 if (netif_msg_drv(bp)) { 9331 bnxt_dump_tx_sw_state(bnapi); 9332 bnxt_dump_rx_sw_state(bnapi); 9333 bnxt_dump_cp_sw_state(bnapi); 9334 } 9335 } 9336 } 9337 9338 static void bnxt_reset_task(struct bnxt *bp, bool silent) 9339 { 9340 if (!silent) 9341 bnxt_dbg_dump_states(bp); 9342 if (netif_running(bp->dev)) { 9343 int rc; 9344 9345 if (!silent) 9346 bnxt_ulp_stop(bp); 9347 bnxt_close_nic(bp, false, false); 9348 rc = bnxt_open_nic(bp, false, false); 9349 if (!silent && !rc) 9350 bnxt_ulp_start(bp); 9351 } 9352 } 9353 9354 static void bnxt_tx_timeout(struct net_device *dev) 9355 { 9356 struct bnxt *bp = netdev_priv(dev); 9357 9358 netdev_err(bp->dev, "TX timeout detected, starting reset task!\n"); 9359 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event); 9360 bnxt_queue_sp_work(bp); 9361 } 9362 9363 static void bnxt_timer(struct timer_list *t) 9364 { 9365 struct bnxt *bp = from_timer(bp, t, timer); 9366 struct net_device *dev = bp->dev; 9367 9368 if (!netif_running(dev)) 9369 return; 9370 9371 if (atomic_read(&bp->intr_sem) != 0) 9372 goto bnxt_restart_timer; 9373 9374 if (bp->link_info.link_up && (bp->flags & BNXT_FLAG_PORT_STATS) && 9375 bp->stats_coal_ticks) { 9376 set_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event); 9377 bnxt_queue_sp_work(bp); 9378 } 9379 9380 if (bnxt_tc_flower_enabled(bp)) { 9381 set_bit(BNXT_FLOW_STATS_SP_EVENT, &bp->sp_event); 9382 bnxt_queue_sp_work(bp); 9383 } 9384 9385 if (bp->link_info.phy_retry) { 9386 if (time_after(jiffies, bp->link_info.phy_retry_expires)) { 9387 bp->link_info.phy_retry = 0; 9388 netdev_warn(bp->dev, "failed to update phy settings after maximum retries.\n"); 9389 } else { 9390 set_bit(BNXT_UPDATE_PHY_SP_EVENT, &bp->sp_event); 9391 bnxt_queue_sp_work(bp); 9392 } 9393 } 9394 9395 if ((bp->flags & BNXT_FLAG_CHIP_P5) && netif_carrier_ok(dev)) { 9396 set_bit(BNXT_RING_COAL_NOW_SP_EVENT, &bp->sp_event); 9397 bnxt_queue_sp_work(bp); 9398 } 9399 bnxt_restart_timer: 9400 mod_timer(&bp->timer, jiffies + bp->current_interval); 9401 } 9402 9403 static void bnxt_rtnl_lock_sp(struct bnxt *bp) 9404 { 9405 /* We are called from bnxt_sp_task which has BNXT_STATE_IN_SP_TASK 9406 * set. If the device is being closed, bnxt_close() may be holding 9407 * rtnl() and waiting for BNXT_STATE_IN_SP_TASK to clear. So we 9408 * must clear BNXT_STATE_IN_SP_TASK before holding rtnl(). 9409 */ 9410 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state); 9411 rtnl_lock(); 9412 } 9413 9414 static void bnxt_rtnl_unlock_sp(struct bnxt *bp) 9415 { 9416 set_bit(BNXT_STATE_IN_SP_TASK, &bp->state); 9417 rtnl_unlock(); 9418 } 9419 9420 /* Only called from bnxt_sp_task() */ 9421 static void bnxt_reset(struct bnxt *bp, bool silent) 9422 { 9423 bnxt_rtnl_lock_sp(bp); 9424 if (test_bit(BNXT_STATE_OPEN, &bp->state)) 9425 bnxt_reset_task(bp, silent); 9426 bnxt_rtnl_unlock_sp(bp); 9427 } 9428 9429 static void bnxt_chk_missed_irq(struct bnxt *bp) 9430 { 9431 int i; 9432 9433 if (!(bp->flags & BNXT_FLAG_CHIP_P5)) 9434 return; 9435 9436 for (i = 0; i < bp->cp_nr_rings; i++) { 9437 struct bnxt_napi *bnapi = bp->bnapi[i]; 9438 struct bnxt_cp_ring_info *cpr; 9439 u32 fw_ring_id; 9440 int j; 9441 9442 if (!bnapi) 9443 continue; 9444 9445 cpr = &bnapi->cp_ring; 9446 for (j = 0; j < 2; j++) { 9447 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j]; 9448 u32 val[2]; 9449 9450 if (!cpr2 || cpr2->has_more_work || 9451 !bnxt_has_work(bp, cpr2)) 9452 continue; 9453 9454 if (cpr2->cp_raw_cons != cpr2->last_cp_raw_cons) { 9455 cpr2->last_cp_raw_cons = cpr2->cp_raw_cons; 9456 continue; 9457 } 9458 fw_ring_id = cpr2->cp_ring_struct.fw_ring_id; 9459 bnxt_dbg_hwrm_ring_info_get(bp, 9460 DBG_RING_INFO_GET_REQ_RING_TYPE_L2_CMPL, 9461 fw_ring_id, &val[0], &val[1]); 9462 cpr->missed_irqs++; 9463 } 9464 } 9465 } 9466 9467 static void bnxt_cfg_ntp_filters(struct bnxt *); 9468 9469 static void bnxt_sp_task(struct work_struct *work) 9470 { 9471 struct bnxt *bp = container_of(work, struct bnxt, sp_task); 9472 9473 set_bit(BNXT_STATE_IN_SP_TASK, &bp->state); 9474 smp_mb__after_atomic(); 9475 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) { 9476 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state); 9477 return; 9478 } 9479 9480 if (test_and_clear_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event)) 9481 bnxt_cfg_rx_mode(bp); 9482 9483 if (test_and_clear_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event)) 9484 bnxt_cfg_ntp_filters(bp); 9485 if (test_and_clear_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event)) 9486 bnxt_hwrm_exec_fwd_req(bp); 9487 if (test_and_clear_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event)) { 9488 bnxt_hwrm_tunnel_dst_port_alloc( 9489 bp, bp->vxlan_port, 9490 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN); 9491 } 9492 if (test_and_clear_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event)) { 9493 bnxt_hwrm_tunnel_dst_port_free( 9494 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN); 9495 } 9496 if (test_and_clear_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event)) { 9497 bnxt_hwrm_tunnel_dst_port_alloc( 9498 bp, bp->nge_port, 9499 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE); 9500 } 9501 if (test_and_clear_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event)) { 9502 bnxt_hwrm_tunnel_dst_port_free( 9503 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE); 9504 } 9505 if (test_and_clear_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event)) { 9506 bnxt_hwrm_port_qstats(bp); 9507 bnxt_hwrm_port_qstats_ext(bp); 9508 bnxt_hwrm_pcie_qstats(bp); 9509 } 9510 9511 if (test_and_clear_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event)) { 9512 int rc; 9513 9514 mutex_lock(&bp->link_lock); 9515 if (test_and_clear_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT, 9516 &bp->sp_event)) 9517 bnxt_hwrm_phy_qcaps(bp); 9518 9519 rc = bnxt_update_link(bp, true); 9520 mutex_unlock(&bp->link_lock); 9521 if (rc) 9522 netdev_err(bp->dev, "SP task can't update link (rc: %x)\n", 9523 rc); 9524 } 9525 if (test_and_clear_bit(BNXT_UPDATE_PHY_SP_EVENT, &bp->sp_event)) { 9526 int rc; 9527 9528 mutex_lock(&bp->link_lock); 9529 rc = bnxt_update_phy_setting(bp); 9530 mutex_unlock(&bp->link_lock); 9531 if (rc) { 9532 netdev_warn(bp->dev, "update phy settings retry failed\n"); 9533 } else { 9534 bp->link_info.phy_retry = false; 9535 netdev_info(bp->dev, "update phy settings retry succeeded\n"); 9536 } 9537 } 9538 if (test_and_clear_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event)) { 9539 mutex_lock(&bp->link_lock); 9540 bnxt_get_port_module_status(bp); 9541 mutex_unlock(&bp->link_lock); 9542 } 9543 9544 if (test_and_clear_bit(BNXT_FLOW_STATS_SP_EVENT, &bp->sp_event)) 9545 bnxt_tc_flow_stats_work(bp); 9546 9547 if (test_and_clear_bit(BNXT_RING_COAL_NOW_SP_EVENT, &bp->sp_event)) 9548 bnxt_chk_missed_irq(bp); 9549 9550 /* These functions below will clear BNXT_STATE_IN_SP_TASK. They 9551 * must be the last functions to be called before exiting. 9552 */ 9553 if (test_and_clear_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event)) 9554 bnxt_reset(bp, false); 9555 9556 if (test_and_clear_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event)) 9557 bnxt_reset(bp, true); 9558 9559 smp_mb__before_atomic(); 9560 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state); 9561 } 9562 9563 /* Under rtnl_lock */ 9564 int bnxt_check_rings(struct bnxt *bp, int tx, int rx, bool sh, int tcs, 9565 int tx_xdp) 9566 { 9567 int max_rx, max_tx, tx_sets = 1; 9568 int tx_rings_needed, stats; 9569 int rx_rings = rx; 9570 int cp, vnics, rc; 9571 9572 if (tcs) 9573 tx_sets = tcs; 9574 9575 rc = bnxt_get_max_rings(bp, &max_rx, &max_tx, sh); 9576 if (rc) 9577 return rc; 9578 9579 if (max_rx < rx) 9580 return -ENOMEM; 9581 9582 tx_rings_needed = tx * tx_sets + tx_xdp; 9583 if (max_tx < tx_rings_needed) 9584 return -ENOMEM; 9585 9586 vnics = 1; 9587 if (bp->flags & BNXT_FLAG_RFS) 9588 vnics += rx_rings; 9589 9590 if (bp->flags & BNXT_FLAG_AGG_RINGS) 9591 rx_rings <<= 1; 9592 cp = sh ? max_t(int, tx_rings_needed, rx) : tx_rings_needed + rx; 9593 stats = cp; 9594 if (BNXT_NEW_RM(bp)) { 9595 cp += bnxt_get_ulp_msix_num(bp); 9596 stats += bnxt_get_ulp_stat_ctxs(bp); 9597 } 9598 return bnxt_hwrm_check_rings(bp, tx_rings_needed, rx_rings, rx, cp, 9599 stats, vnics); 9600 } 9601 9602 static void bnxt_unmap_bars(struct bnxt *bp, struct pci_dev *pdev) 9603 { 9604 if (bp->bar2) { 9605 pci_iounmap(pdev, bp->bar2); 9606 bp->bar2 = NULL; 9607 } 9608 9609 if (bp->bar1) { 9610 pci_iounmap(pdev, bp->bar1); 9611 bp->bar1 = NULL; 9612 } 9613 9614 if (bp->bar0) { 9615 pci_iounmap(pdev, bp->bar0); 9616 bp->bar0 = NULL; 9617 } 9618 } 9619 9620 static void bnxt_cleanup_pci(struct bnxt *bp) 9621 { 9622 bnxt_unmap_bars(bp, bp->pdev); 9623 pci_release_regions(bp->pdev); 9624 pci_disable_device(bp->pdev); 9625 } 9626 9627 static void bnxt_init_dflt_coal(struct bnxt *bp) 9628 { 9629 struct bnxt_coal *coal; 9630 9631 /* Tick values in micro seconds. 9632 * 1 coal_buf x bufs_per_record = 1 completion record. 9633 */ 9634 coal = &bp->rx_coal; 9635 coal->coal_ticks = 10; 9636 coal->coal_bufs = 30; 9637 coal->coal_ticks_irq = 1; 9638 coal->coal_bufs_irq = 2; 9639 coal->idle_thresh = 50; 9640 coal->bufs_per_record = 2; 9641 coal->budget = 64; /* NAPI budget */ 9642 9643 coal = &bp->tx_coal; 9644 coal->coal_ticks = 28; 9645 coal->coal_bufs = 30; 9646 coal->coal_ticks_irq = 2; 9647 coal->coal_bufs_irq = 2; 9648 coal->bufs_per_record = 1; 9649 9650 bp->stats_coal_ticks = BNXT_DEF_STATS_COAL_TICKS; 9651 } 9652 9653 static int bnxt_init_board(struct pci_dev *pdev, struct net_device *dev) 9654 { 9655 int rc; 9656 struct bnxt *bp = netdev_priv(dev); 9657 9658 SET_NETDEV_DEV(dev, &pdev->dev); 9659 9660 /* enable device (incl. PCI PM wakeup), and bus-mastering */ 9661 rc = pci_enable_device(pdev); 9662 if (rc) { 9663 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n"); 9664 goto init_err; 9665 } 9666 9667 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 9668 dev_err(&pdev->dev, 9669 "Cannot find PCI device base address, aborting\n"); 9670 rc = -ENODEV; 9671 goto init_err_disable; 9672 } 9673 9674 rc = pci_request_regions(pdev, DRV_MODULE_NAME); 9675 if (rc) { 9676 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n"); 9677 goto init_err_disable; 9678 } 9679 9680 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) != 0 && 9681 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)) != 0) { 9682 dev_err(&pdev->dev, "System does not support DMA, aborting\n"); 9683 goto init_err_disable; 9684 } 9685 9686 pci_set_master(pdev); 9687 9688 bp->dev = dev; 9689 bp->pdev = pdev; 9690 9691 bp->bar0 = pci_ioremap_bar(pdev, 0); 9692 if (!bp->bar0) { 9693 dev_err(&pdev->dev, "Cannot map device registers, aborting\n"); 9694 rc = -ENOMEM; 9695 goto init_err_release; 9696 } 9697 9698 bp->bar1 = pci_ioremap_bar(pdev, 2); 9699 if (!bp->bar1) { 9700 dev_err(&pdev->dev, "Cannot map doorbell registers, aborting\n"); 9701 rc = -ENOMEM; 9702 goto init_err_release; 9703 } 9704 9705 bp->bar2 = pci_ioremap_bar(pdev, 4); 9706 if (!bp->bar2) { 9707 dev_err(&pdev->dev, "Cannot map bar4 registers, aborting\n"); 9708 rc = -ENOMEM; 9709 goto init_err_release; 9710 } 9711 9712 pci_enable_pcie_error_reporting(pdev); 9713 9714 INIT_WORK(&bp->sp_task, bnxt_sp_task); 9715 9716 spin_lock_init(&bp->ntp_fltr_lock); 9717 #if BITS_PER_LONG == 32 9718 spin_lock_init(&bp->db_lock); 9719 #endif 9720 9721 bp->rx_ring_size = BNXT_DEFAULT_RX_RING_SIZE; 9722 bp->tx_ring_size = BNXT_DEFAULT_TX_RING_SIZE; 9723 9724 bnxt_init_dflt_coal(bp); 9725 9726 timer_setup(&bp->timer, bnxt_timer, 0); 9727 bp->current_interval = BNXT_TIMER_INTERVAL; 9728 9729 clear_bit(BNXT_STATE_OPEN, &bp->state); 9730 return 0; 9731 9732 init_err_release: 9733 bnxt_unmap_bars(bp, pdev); 9734 pci_release_regions(pdev); 9735 9736 init_err_disable: 9737 pci_disable_device(pdev); 9738 9739 init_err: 9740 return rc; 9741 } 9742 9743 /* rtnl_lock held */ 9744 static int bnxt_change_mac_addr(struct net_device *dev, void *p) 9745 { 9746 struct sockaddr *addr = p; 9747 struct bnxt *bp = netdev_priv(dev); 9748 int rc = 0; 9749 9750 if (!is_valid_ether_addr(addr->sa_data)) 9751 return -EADDRNOTAVAIL; 9752 9753 if (ether_addr_equal(addr->sa_data, dev->dev_addr)) 9754 return 0; 9755 9756 rc = bnxt_approve_mac(bp, addr->sa_data, true); 9757 if (rc) 9758 return rc; 9759 9760 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); 9761 if (netif_running(dev)) { 9762 bnxt_close_nic(bp, false, false); 9763 rc = bnxt_open_nic(bp, false, false); 9764 } 9765 9766 return rc; 9767 } 9768 9769 /* rtnl_lock held */ 9770 static int bnxt_change_mtu(struct net_device *dev, int new_mtu) 9771 { 9772 struct bnxt *bp = netdev_priv(dev); 9773 9774 if (netif_running(dev)) 9775 bnxt_close_nic(bp, false, false); 9776 9777 dev->mtu = new_mtu; 9778 bnxt_set_ring_params(bp); 9779 9780 if (netif_running(dev)) 9781 return bnxt_open_nic(bp, false, false); 9782 9783 return 0; 9784 } 9785 9786 int bnxt_setup_mq_tc(struct net_device *dev, u8 tc) 9787 { 9788 struct bnxt *bp = netdev_priv(dev); 9789 bool sh = false; 9790 int rc; 9791 9792 if (tc > bp->max_tc) { 9793 netdev_err(dev, "Too many traffic classes requested: %d. Max supported is %d.\n", 9794 tc, bp->max_tc); 9795 return -EINVAL; 9796 } 9797 9798 if (netdev_get_num_tc(dev) == tc) 9799 return 0; 9800 9801 if (bp->flags & BNXT_FLAG_SHARED_RINGS) 9802 sh = true; 9803 9804 rc = bnxt_check_rings(bp, bp->tx_nr_rings_per_tc, bp->rx_nr_rings, 9805 sh, tc, bp->tx_nr_rings_xdp); 9806 if (rc) 9807 return rc; 9808 9809 /* Needs to close the device and do hw resource re-allocations */ 9810 if (netif_running(bp->dev)) 9811 bnxt_close_nic(bp, true, false); 9812 9813 if (tc) { 9814 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tc; 9815 netdev_set_num_tc(dev, tc); 9816 } else { 9817 bp->tx_nr_rings = bp->tx_nr_rings_per_tc; 9818 netdev_reset_tc(dev); 9819 } 9820 bp->tx_nr_rings += bp->tx_nr_rings_xdp; 9821 bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) : 9822 bp->tx_nr_rings + bp->rx_nr_rings; 9823 9824 if (netif_running(bp->dev)) 9825 return bnxt_open_nic(bp, true, false); 9826 9827 return 0; 9828 } 9829 9830 static int bnxt_setup_tc_block_cb(enum tc_setup_type type, void *type_data, 9831 void *cb_priv) 9832 { 9833 struct bnxt *bp = cb_priv; 9834 9835 if (!bnxt_tc_flower_enabled(bp) || 9836 !tc_cls_can_offload_and_chain0(bp->dev, type_data)) 9837 return -EOPNOTSUPP; 9838 9839 switch (type) { 9840 case TC_SETUP_CLSFLOWER: 9841 return bnxt_tc_setup_flower(bp, bp->pf.fw_fid, type_data); 9842 default: 9843 return -EOPNOTSUPP; 9844 } 9845 } 9846 9847 static int bnxt_setup_tc_block(struct net_device *dev, 9848 struct tc_block_offload *f) 9849 { 9850 struct bnxt *bp = netdev_priv(dev); 9851 9852 if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS) 9853 return -EOPNOTSUPP; 9854 9855 switch (f->command) { 9856 case TC_BLOCK_BIND: 9857 return tcf_block_cb_register(f->block, bnxt_setup_tc_block_cb, 9858 bp, bp, f->extack); 9859 case TC_BLOCK_UNBIND: 9860 tcf_block_cb_unregister(f->block, bnxt_setup_tc_block_cb, bp); 9861 return 0; 9862 default: 9863 return -EOPNOTSUPP; 9864 } 9865 } 9866 9867 static int bnxt_setup_tc(struct net_device *dev, enum tc_setup_type type, 9868 void *type_data) 9869 { 9870 switch (type) { 9871 case TC_SETUP_BLOCK: 9872 return bnxt_setup_tc_block(dev, type_data); 9873 case TC_SETUP_QDISC_MQPRIO: { 9874 struct tc_mqprio_qopt *mqprio = type_data; 9875 9876 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS; 9877 9878 return bnxt_setup_mq_tc(dev, mqprio->num_tc); 9879 } 9880 default: 9881 return -EOPNOTSUPP; 9882 } 9883 } 9884 9885 #ifdef CONFIG_RFS_ACCEL 9886 static bool bnxt_fltr_match(struct bnxt_ntuple_filter *f1, 9887 struct bnxt_ntuple_filter *f2) 9888 { 9889 struct flow_keys *keys1 = &f1->fkeys; 9890 struct flow_keys *keys2 = &f2->fkeys; 9891 9892 if (keys1->addrs.v4addrs.src == keys2->addrs.v4addrs.src && 9893 keys1->addrs.v4addrs.dst == keys2->addrs.v4addrs.dst && 9894 keys1->ports.ports == keys2->ports.ports && 9895 keys1->basic.ip_proto == keys2->basic.ip_proto && 9896 keys1->basic.n_proto == keys2->basic.n_proto && 9897 keys1->control.flags == keys2->control.flags && 9898 ether_addr_equal(f1->src_mac_addr, f2->src_mac_addr) && 9899 ether_addr_equal(f1->dst_mac_addr, f2->dst_mac_addr)) 9900 return true; 9901 9902 return false; 9903 } 9904 9905 static int bnxt_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb, 9906 u16 rxq_index, u32 flow_id) 9907 { 9908 struct bnxt *bp = netdev_priv(dev); 9909 struct bnxt_ntuple_filter *fltr, *new_fltr; 9910 struct flow_keys *fkeys; 9911 struct ethhdr *eth = (struct ethhdr *)skb_mac_header(skb); 9912 int rc = 0, idx, bit_id, l2_idx = 0; 9913 struct hlist_head *head; 9914 9915 if (!ether_addr_equal(dev->dev_addr, eth->h_dest)) { 9916 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 9917 int off = 0, j; 9918 9919 netif_addr_lock_bh(dev); 9920 for (j = 0; j < vnic->uc_filter_count; j++, off += ETH_ALEN) { 9921 if (ether_addr_equal(eth->h_dest, 9922 vnic->uc_list + off)) { 9923 l2_idx = j + 1; 9924 break; 9925 } 9926 } 9927 netif_addr_unlock_bh(dev); 9928 if (!l2_idx) 9929 return -EINVAL; 9930 } 9931 new_fltr = kzalloc(sizeof(*new_fltr), GFP_ATOMIC); 9932 if (!new_fltr) 9933 return -ENOMEM; 9934 9935 fkeys = &new_fltr->fkeys; 9936 if (!skb_flow_dissect_flow_keys(skb, fkeys, 0)) { 9937 rc = -EPROTONOSUPPORT; 9938 goto err_free; 9939 } 9940 9941 if ((fkeys->basic.n_proto != htons(ETH_P_IP) && 9942 fkeys->basic.n_proto != htons(ETH_P_IPV6)) || 9943 ((fkeys->basic.ip_proto != IPPROTO_TCP) && 9944 (fkeys->basic.ip_proto != IPPROTO_UDP))) { 9945 rc = -EPROTONOSUPPORT; 9946 goto err_free; 9947 } 9948 if (fkeys->basic.n_proto == htons(ETH_P_IPV6) && 9949 bp->hwrm_spec_code < 0x10601) { 9950 rc = -EPROTONOSUPPORT; 9951 goto err_free; 9952 } 9953 if ((fkeys->control.flags & FLOW_DIS_ENCAPSULATION) && 9954 bp->hwrm_spec_code < 0x10601) { 9955 rc = -EPROTONOSUPPORT; 9956 goto err_free; 9957 } 9958 9959 memcpy(new_fltr->dst_mac_addr, eth->h_dest, ETH_ALEN); 9960 memcpy(new_fltr->src_mac_addr, eth->h_source, ETH_ALEN); 9961 9962 idx = skb_get_hash_raw(skb) & BNXT_NTP_FLTR_HASH_MASK; 9963 head = &bp->ntp_fltr_hash_tbl[idx]; 9964 rcu_read_lock(); 9965 hlist_for_each_entry_rcu(fltr, head, hash) { 9966 if (bnxt_fltr_match(fltr, new_fltr)) { 9967 rcu_read_unlock(); 9968 rc = 0; 9969 goto err_free; 9970 } 9971 } 9972 rcu_read_unlock(); 9973 9974 spin_lock_bh(&bp->ntp_fltr_lock); 9975 bit_id = bitmap_find_free_region(bp->ntp_fltr_bmap, 9976 BNXT_NTP_FLTR_MAX_FLTR, 0); 9977 if (bit_id < 0) { 9978 spin_unlock_bh(&bp->ntp_fltr_lock); 9979 rc = -ENOMEM; 9980 goto err_free; 9981 } 9982 9983 new_fltr->sw_id = (u16)bit_id; 9984 new_fltr->flow_id = flow_id; 9985 new_fltr->l2_fltr_idx = l2_idx; 9986 new_fltr->rxq = rxq_index; 9987 hlist_add_head_rcu(&new_fltr->hash, head); 9988 bp->ntp_fltr_count++; 9989 spin_unlock_bh(&bp->ntp_fltr_lock); 9990 9991 set_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event); 9992 bnxt_queue_sp_work(bp); 9993 9994 return new_fltr->sw_id; 9995 9996 err_free: 9997 kfree(new_fltr); 9998 return rc; 9999 } 10000 10001 static void bnxt_cfg_ntp_filters(struct bnxt *bp) 10002 { 10003 int i; 10004 10005 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) { 10006 struct hlist_head *head; 10007 struct hlist_node *tmp; 10008 struct bnxt_ntuple_filter *fltr; 10009 int rc; 10010 10011 head = &bp->ntp_fltr_hash_tbl[i]; 10012 hlist_for_each_entry_safe(fltr, tmp, head, hash) { 10013 bool del = false; 10014 10015 if (test_bit(BNXT_FLTR_VALID, &fltr->state)) { 10016 if (rps_may_expire_flow(bp->dev, fltr->rxq, 10017 fltr->flow_id, 10018 fltr->sw_id)) { 10019 bnxt_hwrm_cfa_ntuple_filter_free(bp, 10020 fltr); 10021 del = true; 10022 } 10023 } else { 10024 rc = bnxt_hwrm_cfa_ntuple_filter_alloc(bp, 10025 fltr); 10026 if (rc) 10027 del = true; 10028 else 10029 set_bit(BNXT_FLTR_VALID, &fltr->state); 10030 } 10031 10032 if (del) { 10033 spin_lock_bh(&bp->ntp_fltr_lock); 10034 hlist_del_rcu(&fltr->hash); 10035 bp->ntp_fltr_count--; 10036 spin_unlock_bh(&bp->ntp_fltr_lock); 10037 synchronize_rcu(); 10038 clear_bit(fltr->sw_id, bp->ntp_fltr_bmap); 10039 kfree(fltr); 10040 } 10041 } 10042 } 10043 if (test_and_clear_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event)) 10044 netdev_info(bp->dev, "Receive PF driver unload event!"); 10045 } 10046 10047 #else 10048 10049 static void bnxt_cfg_ntp_filters(struct bnxt *bp) 10050 { 10051 } 10052 10053 #endif /* CONFIG_RFS_ACCEL */ 10054 10055 static void bnxt_udp_tunnel_add(struct net_device *dev, 10056 struct udp_tunnel_info *ti) 10057 { 10058 struct bnxt *bp = netdev_priv(dev); 10059 10060 if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET) 10061 return; 10062 10063 if (!netif_running(dev)) 10064 return; 10065 10066 switch (ti->type) { 10067 case UDP_TUNNEL_TYPE_VXLAN: 10068 if (bp->vxlan_port_cnt && bp->vxlan_port != ti->port) 10069 return; 10070 10071 bp->vxlan_port_cnt++; 10072 if (bp->vxlan_port_cnt == 1) { 10073 bp->vxlan_port = ti->port; 10074 set_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event); 10075 bnxt_queue_sp_work(bp); 10076 } 10077 break; 10078 case UDP_TUNNEL_TYPE_GENEVE: 10079 if (bp->nge_port_cnt && bp->nge_port != ti->port) 10080 return; 10081 10082 bp->nge_port_cnt++; 10083 if (bp->nge_port_cnt == 1) { 10084 bp->nge_port = ti->port; 10085 set_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event); 10086 } 10087 break; 10088 default: 10089 return; 10090 } 10091 10092 bnxt_queue_sp_work(bp); 10093 } 10094 10095 static void bnxt_udp_tunnel_del(struct net_device *dev, 10096 struct udp_tunnel_info *ti) 10097 { 10098 struct bnxt *bp = netdev_priv(dev); 10099 10100 if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET) 10101 return; 10102 10103 if (!netif_running(dev)) 10104 return; 10105 10106 switch (ti->type) { 10107 case UDP_TUNNEL_TYPE_VXLAN: 10108 if (!bp->vxlan_port_cnt || bp->vxlan_port != ti->port) 10109 return; 10110 bp->vxlan_port_cnt--; 10111 10112 if (bp->vxlan_port_cnt != 0) 10113 return; 10114 10115 set_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event); 10116 break; 10117 case UDP_TUNNEL_TYPE_GENEVE: 10118 if (!bp->nge_port_cnt || bp->nge_port != ti->port) 10119 return; 10120 bp->nge_port_cnt--; 10121 10122 if (bp->nge_port_cnt != 0) 10123 return; 10124 10125 set_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event); 10126 break; 10127 default: 10128 return; 10129 } 10130 10131 bnxt_queue_sp_work(bp); 10132 } 10133 10134 static int bnxt_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq, 10135 struct net_device *dev, u32 filter_mask, 10136 int nlflags) 10137 { 10138 struct bnxt *bp = netdev_priv(dev); 10139 10140 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, bp->br_mode, 0, 0, 10141 nlflags, filter_mask, NULL); 10142 } 10143 10144 static int bnxt_bridge_setlink(struct net_device *dev, struct nlmsghdr *nlh, 10145 u16 flags, struct netlink_ext_ack *extack) 10146 { 10147 struct bnxt *bp = netdev_priv(dev); 10148 struct nlattr *attr, *br_spec; 10149 int rem, rc = 0; 10150 10151 if (bp->hwrm_spec_code < 0x10708 || !BNXT_SINGLE_PF(bp)) 10152 return -EOPNOTSUPP; 10153 10154 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC); 10155 if (!br_spec) 10156 return -EINVAL; 10157 10158 nla_for_each_nested(attr, br_spec, rem) { 10159 u16 mode; 10160 10161 if (nla_type(attr) != IFLA_BRIDGE_MODE) 10162 continue; 10163 10164 if (nla_len(attr) < sizeof(mode)) 10165 return -EINVAL; 10166 10167 mode = nla_get_u16(attr); 10168 if (mode == bp->br_mode) 10169 break; 10170 10171 rc = bnxt_hwrm_set_br_mode(bp, mode); 10172 if (!rc) 10173 bp->br_mode = mode; 10174 break; 10175 } 10176 return rc; 10177 } 10178 10179 int bnxt_get_port_parent_id(struct net_device *dev, 10180 struct netdev_phys_item_id *ppid) 10181 { 10182 struct bnxt *bp = netdev_priv(dev); 10183 10184 if (bp->eswitch_mode != DEVLINK_ESWITCH_MODE_SWITCHDEV) 10185 return -EOPNOTSUPP; 10186 10187 /* The PF and it's VF-reps only support the switchdev framework */ 10188 if (!BNXT_PF(bp)) 10189 return -EOPNOTSUPP; 10190 10191 ppid->id_len = sizeof(bp->switch_id); 10192 memcpy(ppid->id, bp->switch_id, ppid->id_len); 10193 10194 return 0; 10195 } 10196 10197 static struct devlink_port *bnxt_get_devlink_port(struct net_device *dev) 10198 { 10199 struct bnxt *bp = netdev_priv(dev); 10200 10201 return &bp->dl_port; 10202 } 10203 10204 static const struct net_device_ops bnxt_netdev_ops = { 10205 .ndo_open = bnxt_open, 10206 .ndo_start_xmit = bnxt_start_xmit, 10207 .ndo_stop = bnxt_close, 10208 .ndo_get_stats64 = bnxt_get_stats64, 10209 .ndo_set_rx_mode = bnxt_set_rx_mode, 10210 .ndo_do_ioctl = bnxt_ioctl, 10211 .ndo_validate_addr = eth_validate_addr, 10212 .ndo_set_mac_address = bnxt_change_mac_addr, 10213 .ndo_change_mtu = bnxt_change_mtu, 10214 .ndo_fix_features = bnxt_fix_features, 10215 .ndo_set_features = bnxt_set_features, 10216 .ndo_tx_timeout = bnxt_tx_timeout, 10217 #ifdef CONFIG_BNXT_SRIOV 10218 .ndo_get_vf_config = bnxt_get_vf_config, 10219 .ndo_set_vf_mac = bnxt_set_vf_mac, 10220 .ndo_set_vf_vlan = bnxt_set_vf_vlan, 10221 .ndo_set_vf_rate = bnxt_set_vf_bw, 10222 .ndo_set_vf_link_state = bnxt_set_vf_link_state, 10223 .ndo_set_vf_spoofchk = bnxt_set_vf_spoofchk, 10224 .ndo_set_vf_trust = bnxt_set_vf_trust, 10225 #endif 10226 .ndo_setup_tc = bnxt_setup_tc, 10227 #ifdef CONFIG_RFS_ACCEL 10228 .ndo_rx_flow_steer = bnxt_rx_flow_steer, 10229 #endif 10230 .ndo_udp_tunnel_add = bnxt_udp_tunnel_add, 10231 .ndo_udp_tunnel_del = bnxt_udp_tunnel_del, 10232 .ndo_bpf = bnxt_xdp, 10233 .ndo_bridge_getlink = bnxt_bridge_getlink, 10234 .ndo_bridge_setlink = bnxt_bridge_setlink, 10235 .ndo_get_devlink_port = bnxt_get_devlink_port, 10236 }; 10237 10238 static void bnxt_remove_one(struct pci_dev *pdev) 10239 { 10240 struct net_device *dev = pci_get_drvdata(pdev); 10241 struct bnxt *bp = netdev_priv(dev); 10242 10243 if (BNXT_PF(bp)) { 10244 bnxt_sriov_disable(bp); 10245 bnxt_dl_unregister(bp); 10246 } 10247 10248 pci_disable_pcie_error_reporting(pdev); 10249 unregister_netdev(dev); 10250 bnxt_shutdown_tc(bp); 10251 bnxt_cancel_sp_work(bp); 10252 bp->sp_event = 0; 10253 10254 bnxt_clear_int_mode(bp); 10255 bnxt_hwrm_func_drv_unrgtr(bp); 10256 bnxt_free_hwrm_resources(bp); 10257 bnxt_free_hwrm_short_cmd_req(bp); 10258 bnxt_ethtool_free(bp); 10259 bnxt_dcb_free(bp); 10260 kfree(bp->edev); 10261 bp->edev = NULL; 10262 bnxt_free_ctx_mem(bp); 10263 kfree(bp->ctx); 10264 bp->ctx = NULL; 10265 bnxt_cleanup_pci(bp); 10266 bnxt_free_port_stats(bp); 10267 free_netdev(dev); 10268 } 10269 10270 static int bnxt_probe_phy(struct bnxt *bp) 10271 { 10272 int rc = 0; 10273 struct bnxt_link_info *link_info = &bp->link_info; 10274 10275 rc = bnxt_hwrm_phy_qcaps(bp); 10276 if (rc) { 10277 netdev_err(bp->dev, "Probe phy can't get phy capabilities (rc: %x)\n", 10278 rc); 10279 return rc; 10280 } 10281 mutex_init(&bp->link_lock); 10282 10283 rc = bnxt_update_link(bp, false); 10284 if (rc) { 10285 netdev_err(bp->dev, "Probe phy can't update link (rc: %x)\n", 10286 rc); 10287 return rc; 10288 } 10289 10290 /* Older firmware does not have supported_auto_speeds, so assume 10291 * that all supported speeds can be autonegotiated. 10292 */ 10293 if (link_info->auto_link_speeds && !link_info->support_auto_speeds) 10294 link_info->support_auto_speeds = link_info->support_speeds; 10295 10296 /*initialize the ethool setting copy with NVM settings */ 10297 if (BNXT_AUTO_MODE(link_info->auto_mode)) { 10298 link_info->autoneg = BNXT_AUTONEG_SPEED; 10299 if (bp->hwrm_spec_code >= 0x10201) { 10300 if (link_info->auto_pause_setting & 10301 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE) 10302 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL; 10303 } else { 10304 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL; 10305 } 10306 link_info->advertising = link_info->auto_link_speeds; 10307 } else { 10308 link_info->req_link_speed = link_info->force_link_speed; 10309 link_info->req_duplex = link_info->duplex_setting; 10310 } 10311 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) 10312 link_info->req_flow_ctrl = 10313 link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH; 10314 else 10315 link_info->req_flow_ctrl = link_info->force_pause_setting; 10316 return rc; 10317 } 10318 10319 static int bnxt_get_max_irq(struct pci_dev *pdev) 10320 { 10321 u16 ctrl; 10322 10323 if (!pdev->msix_cap) 10324 return 1; 10325 10326 pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &ctrl); 10327 return (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1; 10328 } 10329 10330 static void _bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx, 10331 int *max_cp) 10332 { 10333 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 10334 int max_ring_grps = 0, max_irq; 10335 10336 *max_tx = hw_resc->max_tx_rings; 10337 *max_rx = hw_resc->max_rx_rings; 10338 *max_cp = bnxt_get_max_func_cp_rings_for_en(bp); 10339 max_irq = min_t(int, bnxt_get_max_func_irqs(bp) - 10340 bnxt_get_ulp_msix_num(bp), 10341 hw_resc->max_stat_ctxs - bnxt_get_ulp_stat_ctxs(bp)); 10342 if (!(bp->flags & BNXT_FLAG_CHIP_P5)) 10343 *max_cp = min_t(int, *max_cp, max_irq); 10344 max_ring_grps = hw_resc->max_hw_ring_grps; 10345 if (BNXT_CHIP_TYPE_NITRO_A0(bp) && BNXT_PF(bp)) { 10346 *max_cp -= 1; 10347 *max_rx -= 2; 10348 } 10349 if (bp->flags & BNXT_FLAG_AGG_RINGS) 10350 *max_rx >>= 1; 10351 if (bp->flags & BNXT_FLAG_CHIP_P5) { 10352 bnxt_trim_rings(bp, max_rx, max_tx, *max_cp, false); 10353 /* On P5 chips, max_cp output param should be available NQs */ 10354 *max_cp = max_irq; 10355 } 10356 *max_rx = min_t(int, *max_rx, max_ring_grps); 10357 } 10358 10359 int bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx, bool shared) 10360 { 10361 int rx, tx, cp; 10362 10363 _bnxt_get_max_rings(bp, &rx, &tx, &cp); 10364 *max_rx = rx; 10365 *max_tx = tx; 10366 if (!rx || !tx || !cp) 10367 return -ENOMEM; 10368 10369 return bnxt_trim_rings(bp, max_rx, max_tx, cp, shared); 10370 } 10371 10372 static int bnxt_get_dflt_rings(struct bnxt *bp, int *max_rx, int *max_tx, 10373 bool shared) 10374 { 10375 int rc; 10376 10377 rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared); 10378 if (rc && (bp->flags & BNXT_FLAG_AGG_RINGS)) { 10379 /* Not enough rings, try disabling agg rings. */ 10380 bp->flags &= ~BNXT_FLAG_AGG_RINGS; 10381 rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared); 10382 if (rc) { 10383 /* set BNXT_FLAG_AGG_RINGS back for consistency */ 10384 bp->flags |= BNXT_FLAG_AGG_RINGS; 10385 return rc; 10386 } 10387 bp->flags |= BNXT_FLAG_NO_AGG_RINGS; 10388 bp->dev->hw_features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW); 10389 bp->dev->features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW); 10390 bnxt_set_ring_params(bp); 10391 } 10392 10393 if (bp->flags & BNXT_FLAG_ROCE_CAP) { 10394 int max_cp, max_stat, max_irq; 10395 10396 /* Reserve minimum resources for RoCE */ 10397 max_cp = bnxt_get_max_func_cp_rings(bp); 10398 max_stat = bnxt_get_max_func_stat_ctxs(bp); 10399 max_irq = bnxt_get_max_func_irqs(bp); 10400 if (max_cp <= BNXT_MIN_ROCE_CP_RINGS || 10401 max_irq <= BNXT_MIN_ROCE_CP_RINGS || 10402 max_stat <= BNXT_MIN_ROCE_STAT_CTXS) 10403 return 0; 10404 10405 max_cp -= BNXT_MIN_ROCE_CP_RINGS; 10406 max_irq -= BNXT_MIN_ROCE_CP_RINGS; 10407 max_stat -= BNXT_MIN_ROCE_STAT_CTXS; 10408 max_cp = min_t(int, max_cp, max_irq); 10409 max_cp = min_t(int, max_cp, max_stat); 10410 rc = bnxt_trim_rings(bp, max_rx, max_tx, max_cp, shared); 10411 if (rc) 10412 rc = 0; 10413 } 10414 return rc; 10415 } 10416 10417 /* In initial default shared ring setting, each shared ring must have a 10418 * RX/TX ring pair. 10419 */ 10420 static void bnxt_trim_dflt_sh_rings(struct bnxt *bp) 10421 { 10422 bp->cp_nr_rings = min_t(int, bp->tx_nr_rings_per_tc, bp->rx_nr_rings); 10423 bp->rx_nr_rings = bp->cp_nr_rings; 10424 bp->tx_nr_rings_per_tc = bp->cp_nr_rings; 10425 bp->tx_nr_rings = bp->tx_nr_rings_per_tc; 10426 } 10427 10428 static int bnxt_set_dflt_rings(struct bnxt *bp, bool sh) 10429 { 10430 int dflt_rings, max_rx_rings, max_tx_rings, rc; 10431 10432 if (!bnxt_can_reserve_rings(bp)) 10433 return 0; 10434 10435 if (sh) 10436 bp->flags |= BNXT_FLAG_SHARED_RINGS; 10437 dflt_rings = netif_get_num_default_rss_queues(); 10438 /* Reduce default rings on multi-port cards so that total default 10439 * rings do not exceed CPU count. 10440 */ 10441 if (bp->port_count > 1) { 10442 int max_rings = 10443 max_t(int, num_online_cpus() / bp->port_count, 1); 10444 10445 dflt_rings = min_t(int, dflt_rings, max_rings); 10446 } 10447 rc = bnxt_get_dflt_rings(bp, &max_rx_rings, &max_tx_rings, sh); 10448 if (rc) 10449 return rc; 10450 bp->rx_nr_rings = min_t(int, dflt_rings, max_rx_rings); 10451 bp->tx_nr_rings_per_tc = min_t(int, dflt_rings, max_tx_rings); 10452 if (sh) 10453 bnxt_trim_dflt_sh_rings(bp); 10454 else 10455 bp->cp_nr_rings = bp->tx_nr_rings_per_tc + bp->rx_nr_rings; 10456 bp->tx_nr_rings = bp->tx_nr_rings_per_tc; 10457 10458 rc = __bnxt_reserve_rings(bp); 10459 if (rc) 10460 netdev_warn(bp->dev, "Unable to reserve tx rings\n"); 10461 bp->tx_nr_rings_per_tc = bp->tx_nr_rings; 10462 if (sh) 10463 bnxt_trim_dflt_sh_rings(bp); 10464 10465 /* Rings may have been trimmed, re-reserve the trimmed rings. */ 10466 if (bnxt_need_reserve_rings(bp)) { 10467 rc = __bnxt_reserve_rings(bp); 10468 if (rc) 10469 netdev_warn(bp->dev, "2nd rings reservation failed.\n"); 10470 bp->tx_nr_rings_per_tc = bp->tx_nr_rings; 10471 } 10472 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) { 10473 bp->rx_nr_rings++; 10474 bp->cp_nr_rings++; 10475 } 10476 return rc; 10477 } 10478 10479 static int bnxt_init_dflt_ring_mode(struct bnxt *bp) 10480 { 10481 int rc; 10482 10483 if (bp->tx_nr_rings) 10484 return 0; 10485 10486 bnxt_ulp_irq_stop(bp); 10487 bnxt_clear_int_mode(bp); 10488 rc = bnxt_set_dflt_rings(bp, true); 10489 if (rc) { 10490 netdev_err(bp->dev, "Not enough rings available.\n"); 10491 goto init_dflt_ring_err; 10492 } 10493 rc = bnxt_init_int_mode(bp); 10494 if (rc) 10495 goto init_dflt_ring_err; 10496 10497 bp->tx_nr_rings_per_tc = bp->tx_nr_rings; 10498 if (bnxt_rfs_supported(bp) && bnxt_rfs_capable(bp)) { 10499 bp->flags |= BNXT_FLAG_RFS; 10500 bp->dev->features |= NETIF_F_NTUPLE; 10501 } 10502 init_dflt_ring_err: 10503 bnxt_ulp_irq_restart(bp, rc); 10504 return rc; 10505 } 10506 10507 int bnxt_restore_pf_fw_resources(struct bnxt *bp) 10508 { 10509 int rc; 10510 10511 ASSERT_RTNL(); 10512 bnxt_hwrm_func_qcaps(bp); 10513 10514 if (netif_running(bp->dev)) 10515 __bnxt_close_nic(bp, true, false); 10516 10517 bnxt_ulp_irq_stop(bp); 10518 bnxt_clear_int_mode(bp); 10519 rc = bnxt_init_int_mode(bp); 10520 bnxt_ulp_irq_restart(bp, rc); 10521 10522 if (netif_running(bp->dev)) { 10523 if (rc) 10524 dev_close(bp->dev); 10525 else 10526 rc = bnxt_open_nic(bp, true, false); 10527 } 10528 10529 return rc; 10530 } 10531 10532 static int bnxt_init_mac_addr(struct bnxt *bp) 10533 { 10534 int rc = 0; 10535 10536 if (BNXT_PF(bp)) { 10537 memcpy(bp->dev->dev_addr, bp->pf.mac_addr, ETH_ALEN); 10538 } else { 10539 #ifdef CONFIG_BNXT_SRIOV 10540 struct bnxt_vf_info *vf = &bp->vf; 10541 bool strict_approval = true; 10542 10543 if (is_valid_ether_addr(vf->mac_addr)) { 10544 /* overwrite netdev dev_addr with admin VF MAC */ 10545 memcpy(bp->dev->dev_addr, vf->mac_addr, ETH_ALEN); 10546 /* Older PF driver or firmware may not approve this 10547 * correctly. 10548 */ 10549 strict_approval = false; 10550 } else { 10551 eth_hw_addr_random(bp->dev); 10552 } 10553 rc = bnxt_approve_mac(bp, bp->dev->dev_addr, strict_approval); 10554 #endif 10555 } 10556 return rc; 10557 } 10558 10559 static int bnxt_pcie_dsn_get(struct bnxt *bp, u8 dsn[]) 10560 { 10561 struct pci_dev *pdev = bp->pdev; 10562 int pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_DSN); 10563 u32 dw; 10564 10565 if (!pos) { 10566 netdev_info(bp->dev, "Unable do read adapter's DSN"); 10567 return -EOPNOTSUPP; 10568 } 10569 10570 /* DSN (two dw) is at an offset of 4 from the cap pos */ 10571 pos += 4; 10572 pci_read_config_dword(pdev, pos, &dw); 10573 put_unaligned_le32(dw, &dsn[0]); 10574 pci_read_config_dword(pdev, pos + 4, &dw); 10575 put_unaligned_le32(dw, &dsn[4]); 10576 return 0; 10577 } 10578 10579 static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 10580 { 10581 static int version_printed; 10582 struct net_device *dev; 10583 struct bnxt *bp; 10584 int rc, max_irqs; 10585 10586 if (pci_is_bridge(pdev)) 10587 return -ENODEV; 10588 10589 if (version_printed++ == 0) 10590 pr_info("%s", version); 10591 10592 max_irqs = bnxt_get_max_irq(pdev); 10593 dev = alloc_etherdev_mq(sizeof(*bp), max_irqs); 10594 if (!dev) 10595 return -ENOMEM; 10596 10597 bp = netdev_priv(dev); 10598 bnxt_set_max_func_irqs(bp, max_irqs); 10599 10600 if (bnxt_vf_pciid(ent->driver_data)) 10601 bp->flags |= BNXT_FLAG_VF; 10602 10603 if (pdev->msix_cap) 10604 bp->flags |= BNXT_FLAG_MSIX_CAP; 10605 10606 rc = bnxt_init_board(pdev, dev); 10607 if (rc < 0) 10608 goto init_err_free; 10609 10610 dev->netdev_ops = &bnxt_netdev_ops; 10611 dev->watchdog_timeo = BNXT_TX_TIMEOUT; 10612 dev->ethtool_ops = &bnxt_ethtool_ops; 10613 pci_set_drvdata(pdev, dev); 10614 10615 rc = bnxt_alloc_hwrm_resources(bp); 10616 if (rc) 10617 goto init_err_pci_clean; 10618 10619 mutex_init(&bp->hwrm_cmd_lock); 10620 rc = bnxt_hwrm_ver_get(bp); 10621 if (rc) 10622 goto init_err_pci_clean; 10623 10624 if (bp->fw_cap & BNXT_FW_CAP_KONG_MB_CHNL) { 10625 rc = bnxt_alloc_kong_hwrm_resources(bp); 10626 if (rc) 10627 bp->fw_cap &= ~BNXT_FW_CAP_KONG_MB_CHNL; 10628 } 10629 10630 if ((bp->fw_cap & BNXT_FW_CAP_SHORT_CMD) || 10631 bp->hwrm_max_ext_req_len > BNXT_HWRM_MAX_REQ_LEN) { 10632 rc = bnxt_alloc_hwrm_short_cmd_req(bp); 10633 if (rc) 10634 goto init_err_pci_clean; 10635 } 10636 10637 if (BNXT_CHIP_P5(bp)) 10638 bp->flags |= BNXT_FLAG_CHIP_P5; 10639 10640 rc = bnxt_hwrm_func_reset(bp); 10641 if (rc) 10642 goto init_err_pci_clean; 10643 10644 bnxt_hwrm_fw_set_time(bp); 10645 10646 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG | 10647 NETIF_F_TSO | NETIF_F_TSO6 | 10648 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE | 10649 NETIF_F_GSO_IPXIP4 | 10650 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM | 10651 NETIF_F_GSO_PARTIAL | NETIF_F_RXHASH | 10652 NETIF_F_RXCSUM | NETIF_F_GRO; 10653 10654 if (BNXT_SUPPORTS_TPA(bp)) 10655 dev->hw_features |= NETIF_F_LRO; 10656 10657 dev->hw_enc_features = 10658 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG | 10659 NETIF_F_TSO | NETIF_F_TSO6 | 10660 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE | 10661 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM | 10662 NETIF_F_GSO_IPXIP4 | NETIF_F_GSO_PARTIAL; 10663 dev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM | 10664 NETIF_F_GSO_GRE_CSUM; 10665 dev->vlan_features = dev->hw_features | NETIF_F_HIGHDMA; 10666 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX | 10667 NETIF_F_HW_VLAN_STAG_RX | NETIF_F_HW_VLAN_STAG_TX; 10668 if (BNXT_SUPPORTS_TPA(bp)) 10669 dev->hw_features |= NETIF_F_GRO_HW; 10670 dev->features |= dev->hw_features | NETIF_F_HIGHDMA; 10671 if (dev->features & NETIF_F_GRO_HW) 10672 dev->features &= ~NETIF_F_LRO; 10673 dev->priv_flags |= IFF_UNICAST_FLT; 10674 10675 #ifdef CONFIG_BNXT_SRIOV 10676 init_waitqueue_head(&bp->sriov_cfg_wait); 10677 mutex_init(&bp->sriov_lock); 10678 #endif 10679 if (BNXT_SUPPORTS_TPA(bp)) { 10680 bp->gro_func = bnxt_gro_func_5730x; 10681 if (BNXT_CHIP_P4(bp)) 10682 bp->gro_func = bnxt_gro_func_5731x; 10683 } 10684 if (!BNXT_CHIP_P4_PLUS(bp)) 10685 bp->flags |= BNXT_FLAG_DOUBLE_DB; 10686 10687 rc = bnxt_hwrm_func_drv_rgtr(bp); 10688 if (rc) 10689 goto init_err_pci_clean; 10690 10691 rc = bnxt_hwrm_func_rgtr_async_events(bp, NULL, 0); 10692 if (rc) 10693 goto init_err_pci_clean; 10694 10695 bp->ulp_probe = bnxt_ulp_probe; 10696 10697 rc = bnxt_hwrm_queue_qportcfg(bp); 10698 if (rc) { 10699 netdev_err(bp->dev, "hwrm query qportcfg failure rc: %x\n", 10700 rc); 10701 rc = -1; 10702 goto init_err_pci_clean; 10703 } 10704 /* Get the MAX capabilities for this function */ 10705 rc = bnxt_hwrm_func_qcaps(bp); 10706 if (rc) { 10707 netdev_err(bp->dev, "hwrm query capability failure rc: %x\n", 10708 rc); 10709 rc = -1; 10710 goto init_err_pci_clean; 10711 } 10712 10713 rc = bnxt_hwrm_cfa_adv_flow_mgnt_qcaps(bp); 10714 if (rc) 10715 netdev_warn(bp->dev, "hwrm query adv flow mgnt failure rc: %d\n", 10716 rc); 10717 10718 rc = bnxt_init_mac_addr(bp); 10719 if (rc) { 10720 dev_err(&pdev->dev, "Unable to initialize mac address.\n"); 10721 rc = -EADDRNOTAVAIL; 10722 goto init_err_pci_clean; 10723 } 10724 10725 /* Read the adapter's DSN to use as the eswitch switch_id */ 10726 rc = bnxt_pcie_dsn_get(bp, bp->switch_id); 10727 if (rc) 10728 goto init_err_pci_clean; 10729 10730 bnxt_hwrm_func_qcfg(bp); 10731 bnxt_hwrm_vnic_qcaps(bp); 10732 bnxt_hwrm_port_led_qcaps(bp); 10733 bnxt_ethtool_init(bp); 10734 bnxt_dcb_init(bp); 10735 10736 /* MTU range: 60 - FW defined max */ 10737 dev->min_mtu = ETH_ZLEN; 10738 dev->max_mtu = bp->max_mtu; 10739 10740 rc = bnxt_probe_phy(bp); 10741 if (rc) 10742 goto init_err_pci_clean; 10743 10744 bnxt_set_rx_skb_mode(bp, false); 10745 bnxt_set_tpa_flags(bp); 10746 bnxt_set_ring_params(bp); 10747 rc = bnxt_set_dflt_rings(bp, true); 10748 if (rc) { 10749 netdev_err(bp->dev, "Not enough rings available.\n"); 10750 rc = -ENOMEM; 10751 goto init_err_pci_clean; 10752 } 10753 10754 /* Default RSS hash cfg. */ 10755 bp->rss_hash_cfg = VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 | 10756 VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 | 10757 VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 | 10758 VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6; 10759 if (BNXT_CHIP_P4(bp) && bp->hwrm_spec_code >= 0x10501) { 10760 bp->flags |= BNXT_FLAG_UDP_RSS_CAP; 10761 bp->rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 | 10762 VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6; 10763 } 10764 10765 if (bnxt_rfs_supported(bp)) { 10766 dev->hw_features |= NETIF_F_NTUPLE; 10767 if (bnxt_rfs_capable(bp)) { 10768 bp->flags |= BNXT_FLAG_RFS; 10769 dev->features |= NETIF_F_NTUPLE; 10770 } 10771 } 10772 10773 if (dev->hw_features & NETIF_F_HW_VLAN_CTAG_RX) 10774 bp->flags |= BNXT_FLAG_STRIP_VLAN; 10775 10776 rc = bnxt_init_int_mode(bp); 10777 if (rc) 10778 goto init_err_pci_clean; 10779 10780 /* No TC has been set yet and rings may have been trimmed due to 10781 * limited MSIX, so we re-initialize the TX rings per TC. 10782 */ 10783 bp->tx_nr_rings_per_tc = bp->tx_nr_rings; 10784 10785 bnxt_get_wol_settings(bp); 10786 if (bp->flags & BNXT_FLAG_WOL_CAP) 10787 device_set_wakeup_enable(&pdev->dev, bp->wol); 10788 else 10789 device_set_wakeup_capable(&pdev->dev, false); 10790 10791 bnxt_hwrm_set_cache_line_size(bp, cache_line_size()); 10792 10793 bnxt_hwrm_coal_params_qcaps(bp); 10794 10795 if (BNXT_PF(bp)) { 10796 if (!bnxt_pf_wq) { 10797 bnxt_pf_wq = 10798 create_singlethread_workqueue("bnxt_pf_wq"); 10799 if (!bnxt_pf_wq) { 10800 dev_err(&pdev->dev, "Unable to create workqueue.\n"); 10801 goto init_err_pci_clean; 10802 } 10803 } 10804 bnxt_init_tc(bp); 10805 } 10806 10807 rc = register_netdev(dev); 10808 if (rc) 10809 goto init_err_cleanup_tc; 10810 10811 if (BNXT_PF(bp)) 10812 bnxt_dl_register(bp); 10813 10814 netdev_info(dev, "%s found at mem %lx, node addr %pM\n", 10815 board_info[ent->driver_data].name, 10816 (long)pci_resource_start(pdev, 0), dev->dev_addr); 10817 pcie_print_link_status(pdev); 10818 10819 return 0; 10820 10821 init_err_cleanup_tc: 10822 bnxt_shutdown_tc(bp); 10823 bnxt_clear_int_mode(bp); 10824 10825 init_err_pci_clean: 10826 bnxt_free_hwrm_short_cmd_req(bp); 10827 bnxt_free_hwrm_resources(bp); 10828 bnxt_free_ctx_mem(bp); 10829 kfree(bp->ctx); 10830 bp->ctx = NULL; 10831 bnxt_cleanup_pci(bp); 10832 10833 init_err_free: 10834 free_netdev(dev); 10835 return rc; 10836 } 10837 10838 static void bnxt_shutdown(struct pci_dev *pdev) 10839 { 10840 struct net_device *dev = pci_get_drvdata(pdev); 10841 struct bnxt *bp; 10842 10843 if (!dev) 10844 return; 10845 10846 rtnl_lock(); 10847 bp = netdev_priv(dev); 10848 if (!bp) 10849 goto shutdown_exit; 10850 10851 if (netif_running(dev)) 10852 dev_close(dev); 10853 10854 bnxt_ulp_shutdown(bp); 10855 10856 if (system_state == SYSTEM_POWER_OFF) { 10857 bnxt_clear_int_mode(bp); 10858 pci_wake_from_d3(pdev, bp->wol); 10859 pci_set_power_state(pdev, PCI_D3hot); 10860 } 10861 10862 shutdown_exit: 10863 rtnl_unlock(); 10864 } 10865 10866 #ifdef CONFIG_PM_SLEEP 10867 static int bnxt_suspend(struct device *device) 10868 { 10869 struct pci_dev *pdev = to_pci_dev(device); 10870 struct net_device *dev = pci_get_drvdata(pdev); 10871 struct bnxt *bp = netdev_priv(dev); 10872 int rc = 0; 10873 10874 rtnl_lock(); 10875 if (netif_running(dev)) { 10876 netif_device_detach(dev); 10877 rc = bnxt_close(dev); 10878 } 10879 bnxt_hwrm_func_drv_unrgtr(bp); 10880 rtnl_unlock(); 10881 return rc; 10882 } 10883 10884 static int bnxt_resume(struct device *device) 10885 { 10886 struct pci_dev *pdev = to_pci_dev(device); 10887 struct net_device *dev = pci_get_drvdata(pdev); 10888 struct bnxt *bp = netdev_priv(dev); 10889 int rc = 0; 10890 10891 rtnl_lock(); 10892 if (bnxt_hwrm_ver_get(bp) || bnxt_hwrm_func_drv_rgtr(bp)) { 10893 rc = -ENODEV; 10894 goto resume_exit; 10895 } 10896 rc = bnxt_hwrm_func_reset(bp); 10897 if (rc) { 10898 rc = -EBUSY; 10899 goto resume_exit; 10900 } 10901 bnxt_get_wol_settings(bp); 10902 if (netif_running(dev)) { 10903 rc = bnxt_open(dev); 10904 if (!rc) 10905 netif_device_attach(dev); 10906 } 10907 10908 resume_exit: 10909 rtnl_unlock(); 10910 return rc; 10911 } 10912 10913 static SIMPLE_DEV_PM_OPS(bnxt_pm_ops, bnxt_suspend, bnxt_resume); 10914 #define BNXT_PM_OPS (&bnxt_pm_ops) 10915 10916 #else 10917 10918 #define BNXT_PM_OPS NULL 10919 10920 #endif /* CONFIG_PM_SLEEP */ 10921 10922 /** 10923 * bnxt_io_error_detected - called when PCI error is detected 10924 * @pdev: Pointer to PCI device 10925 * @state: The current pci connection state 10926 * 10927 * This function is called after a PCI bus error affecting 10928 * this device has been detected. 10929 */ 10930 static pci_ers_result_t bnxt_io_error_detected(struct pci_dev *pdev, 10931 pci_channel_state_t state) 10932 { 10933 struct net_device *netdev = pci_get_drvdata(pdev); 10934 struct bnxt *bp = netdev_priv(netdev); 10935 10936 netdev_info(netdev, "PCI I/O error detected\n"); 10937 10938 rtnl_lock(); 10939 netif_device_detach(netdev); 10940 10941 bnxt_ulp_stop(bp); 10942 10943 if (state == pci_channel_io_perm_failure) { 10944 rtnl_unlock(); 10945 return PCI_ERS_RESULT_DISCONNECT; 10946 } 10947 10948 if (netif_running(netdev)) 10949 bnxt_close(netdev); 10950 10951 pci_disable_device(pdev); 10952 rtnl_unlock(); 10953 10954 /* Request a slot slot reset. */ 10955 return PCI_ERS_RESULT_NEED_RESET; 10956 } 10957 10958 /** 10959 * bnxt_io_slot_reset - called after the pci bus has been reset. 10960 * @pdev: Pointer to PCI device 10961 * 10962 * Restart the card from scratch, as if from a cold-boot. 10963 * At this point, the card has exprienced a hard reset, 10964 * followed by fixups by BIOS, and has its config space 10965 * set up identically to what it was at cold boot. 10966 */ 10967 static pci_ers_result_t bnxt_io_slot_reset(struct pci_dev *pdev) 10968 { 10969 struct net_device *netdev = pci_get_drvdata(pdev); 10970 struct bnxt *bp = netdev_priv(netdev); 10971 int err = 0; 10972 pci_ers_result_t result = PCI_ERS_RESULT_DISCONNECT; 10973 10974 netdev_info(bp->dev, "PCI Slot Reset\n"); 10975 10976 rtnl_lock(); 10977 10978 if (pci_enable_device(pdev)) { 10979 dev_err(&pdev->dev, 10980 "Cannot re-enable PCI device after reset.\n"); 10981 } else { 10982 pci_set_master(pdev); 10983 10984 err = bnxt_hwrm_func_reset(bp); 10985 if (!err && netif_running(netdev)) 10986 err = bnxt_open(netdev); 10987 10988 if (!err) { 10989 result = PCI_ERS_RESULT_RECOVERED; 10990 bnxt_ulp_start(bp); 10991 } 10992 } 10993 10994 if (result != PCI_ERS_RESULT_RECOVERED && netif_running(netdev)) 10995 dev_close(netdev); 10996 10997 rtnl_unlock(); 10998 10999 return PCI_ERS_RESULT_RECOVERED; 11000 } 11001 11002 /** 11003 * bnxt_io_resume - called when traffic can start flowing again. 11004 * @pdev: Pointer to PCI device 11005 * 11006 * This callback is called when the error recovery driver tells 11007 * us that its OK to resume normal operation. 11008 */ 11009 static void bnxt_io_resume(struct pci_dev *pdev) 11010 { 11011 struct net_device *netdev = pci_get_drvdata(pdev); 11012 11013 rtnl_lock(); 11014 11015 netif_device_attach(netdev); 11016 11017 rtnl_unlock(); 11018 } 11019 11020 static const struct pci_error_handlers bnxt_err_handler = { 11021 .error_detected = bnxt_io_error_detected, 11022 .slot_reset = bnxt_io_slot_reset, 11023 .resume = bnxt_io_resume 11024 }; 11025 11026 static struct pci_driver bnxt_pci_driver = { 11027 .name = DRV_MODULE_NAME, 11028 .id_table = bnxt_pci_tbl, 11029 .probe = bnxt_init_one, 11030 .remove = bnxt_remove_one, 11031 .shutdown = bnxt_shutdown, 11032 .driver.pm = BNXT_PM_OPS, 11033 .err_handler = &bnxt_err_handler, 11034 #if defined(CONFIG_BNXT_SRIOV) 11035 .sriov_configure = bnxt_sriov_configure, 11036 #endif 11037 }; 11038 11039 static int __init bnxt_init(void) 11040 { 11041 bnxt_debug_init(); 11042 return pci_register_driver(&bnxt_pci_driver); 11043 } 11044 11045 static void __exit bnxt_exit(void) 11046 { 11047 pci_unregister_driver(&bnxt_pci_driver); 11048 if (bnxt_pf_wq) 11049 destroy_workqueue(bnxt_pf_wq); 11050 bnxt_debug_exit(); 11051 } 11052 11053 module_init(bnxt_init); 11054 module_exit(bnxt_exit); 11055