1 /* Broadcom NetXtreme-C/E network driver. 2 * 3 * Copyright (c) 2014-2016 Broadcom Corporation 4 * Copyright (c) 2016-2018 Broadcom Limited 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation. 9 */ 10 11 #include <linux/module.h> 12 13 #include <linux/stringify.h> 14 #include <linux/kernel.h> 15 #include <linux/timer.h> 16 #include <linux/errno.h> 17 #include <linux/ioport.h> 18 #include <linux/slab.h> 19 #include <linux/vmalloc.h> 20 #include <linux/interrupt.h> 21 #include <linux/pci.h> 22 #include <linux/netdevice.h> 23 #include <linux/etherdevice.h> 24 #include <linux/skbuff.h> 25 #include <linux/dma-mapping.h> 26 #include <linux/bitops.h> 27 #include <linux/io.h> 28 #include <linux/irq.h> 29 #include <linux/delay.h> 30 #include <asm/byteorder.h> 31 #include <asm/page.h> 32 #include <linux/time.h> 33 #include <linux/mii.h> 34 #include <linux/if.h> 35 #include <linux/if_vlan.h> 36 #include <linux/if_bridge.h> 37 #include <linux/rtc.h> 38 #include <linux/bpf.h> 39 #include <net/ip.h> 40 #include <net/tcp.h> 41 #include <net/udp.h> 42 #include <net/checksum.h> 43 #include <net/ip6_checksum.h> 44 #include <net/udp_tunnel.h> 45 #include <linux/workqueue.h> 46 #include <linux/prefetch.h> 47 #include <linux/cache.h> 48 #include <linux/log2.h> 49 #include <linux/aer.h> 50 #include <linux/bitmap.h> 51 #include <linux/cpu_rmap.h> 52 #include <linux/cpumask.h> 53 #include <net/pkt_cls.h> 54 55 #include "bnxt_hsi.h" 56 #include "bnxt.h" 57 #include "bnxt_ulp.h" 58 #include "bnxt_sriov.h" 59 #include "bnxt_ethtool.h" 60 #include "bnxt_dcb.h" 61 #include "bnxt_xdp.h" 62 #include "bnxt_vfr.h" 63 #include "bnxt_tc.h" 64 #include "bnxt_devlink.h" 65 66 #define BNXT_TX_TIMEOUT (5 * HZ) 67 68 static const char version[] = 69 "Broadcom NetXtreme-C/E driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION "\n"; 70 71 MODULE_LICENSE("GPL"); 72 MODULE_DESCRIPTION("Broadcom BCM573xx network driver"); 73 MODULE_VERSION(DRV_MODULE_VERSION); 74 75 #define BNXT_RX_OFFSET (NET_SKB_PAD + NET_IP_ALIGN) 76 #define BNXT_RX_DMA_OFFSET NET_SKB_PAD 77 #define BNXT_RX_COPY_THRESH 256 78 79 #define BNXT_TX_PUSH_THRESH 164 80 81 enum board_idx { 82 BCM57301, 83 BCM57302, 84 BCM57304, 85 BCM57417_NPAR, 86 BCM58700, 87 BCM57311, 88 BCM57312, 89 BCM57402, 90 BCM57404, 91 BCM57406, 92 BCM57402_NPAR, 93 BCM57407, 94 BCM57412, 95 BCM57414, 96 BCM57416, 97 BCM57417, 98 BCM57412_NPAR, 99 BCM57314, 100 BCM57417_SFP, 101 BCM57416_SFP, 102 BCM57404_NPAR, 103 BCM57406_NPAR, 104 BCM57407_SFP, 105 BCM57407_NPAR, 106 BCM57414_NPAR, 107 BCM57416_NPAR, 108 BCM57452, 109 BCM57454, 110 BCM5745x_NPAR, 111 BCM58802, 112 BCM58804, 113 BCM58808, 114 NETXTREME_E_VF, 115 NETXTREME_C_VF, 116 NETXTREME_S_VF, 117 }; 118 119 /* indexed by enum above */ 120 static const struct { 121 char *name; 122 } board_info[] = { 123 [BCM57301] = { "Broadcom BCM57301 NetXtreme-C 10Gb Ethernet" }, 124 [BCM57302] = { "Broadcom BCM57302 NetXtreme-C 10Gb/25Gb Ethernet" }, 125 [BCM57304] = { "Broadcom BCM57304 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" }, 126 [BCM57417_NPAR] = { "Broadcom BCM57417 NetXtreme-E Ethernet Partition" }, 127 [BCM58700] = { "Broadcom BCM58700 Nitro 1Gb/2.5Gb/10Gb Ethernet" }, 128 [BCM57311] = { "Broadcom BCM57311 NetXtreme-C 10Gb Ethernet" }, 129 [BCM57312] = { "Broadcom BCM57312 NetXtreme-C 10Gb/25Gb Ethernet" }, 130 [BCM57402] = { "Broadcom BCM57402 NetXtreme-E 10Gb Ethernet" }, 131 [BCM57404] = { "Broadcom BCM57404 NetXtreme-E 10Gb/25Gb Ethernet" }, 132 [BCM57406] = { "Broadcom BCM57406 NetXtreme-E 10GBase-T Ethernet" }, 133 [BCM57402_NPAR] = { "Broadcom BCM57402 NetXtreme-E Ethernet Partition" }, 134 [BCM57407] = { "Broadcom BCM57407 NetXtreme-E 10GBase-T Ethernet" }, 135 [BCM57412] = { "Broadcom BCM57412 NetXtreme-E 10Gb Ethernet" }, 136 [BCM57414] = { "Broadcom BCM57414 NetXtreme-E 10Gb/25Gb Ethernet" }, 137 [BCM57416] = { "Broadcom BCM57416 NetXtreme-E 10GBase-T Ethernet" }, 138 [BCM57417] = { "Broadcom BCM57417 NetXtreme-E 10GBase-T Ethernet" }, 139 [BCM57412_NPAR] = { "Broadcom BCM57412 NetXtreme-E Ethernet Partition" }, 140 [BCM57314] = { "Broadcom BCM57314 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" }, 141 [BCM57417_SFP] = { "Broadcom BCM57417 NetXtreme-E 10Gb/25Gb Ethernet" }, 142 [BCM57416_SFP] = { "Broadcom BCM57416 NetXtreme-E 10Gb Ethernet" }, 143 [BCM57404_NPAR] = { "Broadcom BCM57404 NetXtreme-E Ethernet Partition" }, 144 [BCM57406_NPAR] = { "Broadcom BCM57406 NetXtreme-E Ethernet Partition" }, 145 [BCM57407_SFP] = { "Broadcom BCM57407 NetXtreme-E 25Gb Ethernet" }, 146 [BCM57407_NPAR] = { "Broadcom BCM57407 NetXtreme-E Ethernet Partition" }, 147 [BCM57414_NPAR] = { "Broadcom BCM57414 NetXtreme-E Ethernet Partition" }, 148 [BCM57416_NPAR] = { "Broadcom BCM57416 NetXtreme-E Ethernet Partition" }, 149 [BCM57452] = { "Broadcom BCM57452 NetXtreme-E 10Gb/25Gb/40Gb/50Gb Ethernet" }, 150 [BCM57454] = { "Broadcom BCM57454 NetXtreme-E 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" }, 151 [BCM5745x_NPAR] = { "Broadcom BCM5745x NetXtreme-E Ethernet Partition" }, 152 [BCM58802] = { "Broadcom BCM58802 NetXtreme-S 10Gb/25Gb/40Gb/50Gb Ethernet" }, 153 [BCM58804] = { "Broadcom BCM58804 NetXtreme-S 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" }, 154 [BCM58808] = { "Broadcom BCM58808 NetXtreme-S 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" }, 155 [NETXTREME_E_VF] = { "Broadcom NetXtreme-E Ethernet Virtual Function" }, 156 [NETXTREME_C_VF] = { "Broadcom NetXtreme-C Ethernet Virtual Function" }, 157 [NETXTREME_S_VF] = { "Broadcom NetXtreme-S Ethernet Virtual Function" }, 158 }; 159 160 static const struct pci_device_id bnxt_pci_tbl[] = { 161 { PCI_VDEVICE(BROADCOM, 0x1604), .driver_data = BCM5745x_NPAR }, 162 { PCI_VDEVICE(BROADCOM, 0x1605), .driver_data = BCM5745x_NPAR }, 163 { PCI_VDEVICE(BROADCOM, 0x1614), .driver_data = BCM57454 }, 164 { PCI_VDEVICE(BROADCOM, 0x16c0), .driver_data = BCM57417_NPAR }, 165 { PCI_VDEVICE(BROADCOM, 0x16c8), .driver_data = BCM57301 }, 166 { PCI_VDEVICE(BROADCOM, 0x16c9), .driver_data = BCM57302 }, 167 { PCI_VDEVICE(BROADCOM, 0x16ca), .driver_data = BCM57304 }, 168 { PCI_VDEVICE(BROADCOM, 0x16cc), .driver_data = BCM57417_NPAR }, 169 { PCI_VDEVICE(BROADCOM, 0x16cd), .driver_data = BCM58700 }, 170 { PCI_VDEVICE(BROADCOM, 0x16ce), .driver_data = BCM57311 }, 171 { PCI_VDEVICE(BROADCOM, 0x16cf), .driver_data = BCM57312 }, 172 { PCI_VDEVICE(BROADCOM, 0x16d0), .driver_data = BCM57402 }, 173 { PCI_VDEVICE(BROADCOM, 0x16d1), .driver_data = BCM57404 }, 174 { PCI_VDEVICE(BROADCOM, 0x16d2), .driver_data = BCM57406 }, 175 { PCI_VDEVICE(BROADCOM, 0x16d4), .driver_data = BCM57402_NPAR }, 176 { PCI_VDEVICE(BROADCOM, 0x16d5), .driver_data = BCM57407 }, 177 { PCI_VDEVICE(BROADCOM, 0x16d6), .driver_data = BCM57412 }, 178 { PCI_VDEVICE(BROADCOM, 0x16d7), .driver_data = BCM57414 }, 179 { PCI_VDEVICE(BROADCOM, 0x16d8), .driver_data = BCM57416 }, 180 { PCI_VDEVICE(BROADCOM, 0x16d9), .driver_data = BCM57417 }, 181 { PCI_VDEVICE(BROADCOM, 0x16de), .driver_data = BCM57412_NPAR }, 182 { PCI_VDEVICE(BROADCOM, 0x16df), .driver_data = BCM57314 }, 183 { PCI_VDEVICE(BROADCOM, 0x16e2), .driver_data = BCM57417_SFP }, 184 { PCI_VDEVICE(BROADCOM, 0x16e3), .driver_data = BCM57416_SFP }, 185 { PCI_VDEVICE(BROADCOM, 0x16e7), .driver_data = BCM57404_NPAR }, 186 { PCI_VDEVICE(BROADCOM, 0x16e8), .driver_data = BCM57406_NPAR }, 187 { PCI_VDEVICE(BROADCOM, 0x16e9), .driver_data = BCM57407_SFP }, 188 { PCI_VDEVICE(BROADCOM, 0x16ea), .driver_data = BCM57407_NPAR }, 189 { PCI_VDEVICE(BROADCOM, 0x16eb), .driver_data = BCM57412_NPAR }, 190 { PCI_VDEVICE(BROADCOM, 0x16ec), .driver_data = BCM57414_NPAR }, 191 { PCI_VDEVICE(BROADCOM, 0x16ed), .driver_data = BCM57414_NPAR }, 192 { PCI_VDEVICE(BROADCOM, 0x16ee), .driver_data = BCM57416_NPAR }, 193 { PCI_VDEVICE(BROADCOM, 0x16ef), .driver_data = BCM57416_NPAR }, 194 { PCI_VDEVICE(BROADCOM, 0x16f0), .driver_data = BCM58808 }, 195 { PCI_VDEVICE(BROADCOM, 0x16f1), .driver_data = BCM57452 }, 196 { PCI_VDEVICE(BROADCOM, 0xd802), .driver_data = BCM58802 }, 197 { PCI_VDEVICE(BROADCOM, 0xd804), .driver_data = BCM58804 }, 198 #ifdef CONFIG_BNXT_SRIOV 199 { PCI_VDEVICE(BROADCOM, 0x1606), .driver_data = NETXTREME_E_VF }, 200 { PCI_VDEVICE(BROADCOM, 0x1609), .driver_data = NETXTREME_E_VF }, 201 { PCI_VDEVICE(BROADCOM, 0x16c1), .driver_data = NETXTREME_E_VF }, 202 { PCI_VDEVICE(BROADCOM, 0x16cb), .driver_data = NETXTREME_C_VF }, 203 { PCI_VDEVICE(BROADCOM, 0x16d3), .driver_data = NETXTREME_E_VF }, 204 { PCI_VDEVICE(BROADCOM, 0x16dc), .driver_data = NETXTREME_E_VF }, 205 { PCI_VDEVICE(BROADCOM, 0x16e1), .driver_data = NETXTREME_C_VF }, 206 { PCI_VDEVICE(BROADCOM, 0x16e5), .driver_data = NETXTREME_C_VF }, 207 { PCI_VDEVICE(BROADCOM, 0xd800), .driver_data = NETXTREME_S_VF }, 208 #endif 209 { 0 } 210 }; 211 212 MODULE_DEVICE_TABLE(pci, bnxt_pci_tbl); 213 214 static const u16 bnxt_vf_req_snif[] = { 215 HWRM_FUNC_CFG, 216 HWRM_FUNC_VF_CFG, 217 HWRM_PORT_PHY_QCFG, 218 HWRM_CFA_L2_FILTER_ALLOC, 219 }; 220 221 static const u16 bnxt_async_events_arr[] = { 222 ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE, 223 ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD, 224 ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED, 225 ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE, 226 ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE, 227 }; 228 229 static struct workqueue_struct *bnxt_pf_wq; 230 231 static bool bnxt_vf_pciid(enum board_idx idx) 232 { 233 return (idx == NETXTREME_C_VF || idx == NETXTREME_E_VF || 234 idx == NETXTREME_S_VF); 235 } 236 237 #define DB_CP_REARM_FLAGS (DB_KEY_CP | DB_IDX_VALID) 238 #define DB_CP_FLAGS (DB_KEY_CP | DB_IDX_VALID | DB_IRQ_DIS) 239 #define DB_CP_IRQ_DIS_FLAGS (DB_KEY_CP | DB_IRQ_DIS) 240 241 #define BNXT_CP_DB_REARM(db, raw_cons) \ 242 writel(DB_CP_REARM_FLAGS | RING_CMP(raw_cons), db) 243 244 #define BNXT_CP_DB(db, raw_cons) \ 245 writel(DB_CP_FLAGS | RING_CMP(raw_cons), db) 246 247 #define BNXT_CP_DB_IRQ_DIS(db) \ 248 writel(DB_CP_IRQ_DIS_FLAGS, db) 249 250 const u16 bnxt_lhint_arr[] = { 251 TX_BD_FLAGS_LHINT_512_AND_SMALLER, 252 TX_BD_FLAGS_LHINT_512_TO_1023, 253 TX_BD_FLAGS_LHINT_1024_TO_2047, 254 TX_BD_FLAGS_LHINT_1024_TO_2047, 255 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 256 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 257 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 258 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 259 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 260 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 261 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 262 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 263 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 264 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 265 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 266 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 267 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 268 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 269 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 270 }; 271 272 static u16 bnxt_xmit_get_cfa_action(struct sk_buff *skb) 273 { 274 struct metadata_dst *md_dst = skb_metadata_dst(skb); 275 276 if (!md_dst || md_dst->type != METADATA_HW_PORT_MUX) 277 return 0; 278 279 return md_dst->u.port_info.port_id; 280 } 281 282 static netdev_tx_t bnxt_start_xmit(struct sk_buff *skb, struct net_device *dev) 283 { 284 struct bnxt *bp = netdev_priv(dev); 285 struct tx_bd *txbd; 286 struct tx_bd_ext *txbd1; 287 struct netdev_queue *txq; 288 int i; 289 dma_addr_t mapping; 290 unsigned int length, pad = 0; 291 u32 len, free_size, vlan_tag_flags, cfa_action, flags; 292 u16 prod, last_frag; 293 struct pci_dev *pdev = bp->pdev; 294 struct bnxt_tx_ring_info *txr; 295 struct bnxt_sw_tx_bd *tx_buf; 296 297 i = skb_get_queue_mapping(skb); 298 if (unlikely(i >= bp->tx_nr_rings)) { 299 dev_kfree_skb_any(skb); 300 return NETDEV_TX_OK; 301 } 302 303 txq = netdev_get_tx_queue(dev, i); 304 txr = &bp->tx_ring[bp->tx_ring_map[i]]; 305 prod = txr->tx_prod; 306 307 free_size = bnxt_tx_avail(bp, txr); 308 if (unlikely(free_size < skb_shinfo(skb)->nr_frags + 2)) { 309 netif_tx_stop_queue(txq); 310 return NETDEV_TX_BUSY; 311 } 312 313 length = skb->len; 314 len = skb_headlen(skb); 315 last_frag = skb_shinfo(skb)->nr_frags; 316 317 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)]; 318 319 txbd->tx_bd_opaque = prod; 320 321 tx_buf = &txr->tx_buf_ring[prod]; 322 tx_buf->skb = skb; 323 tx_buf->nr_frags = last_frag; 324 325 vlan_tag_flags = 0; 326 cfa_action = bnxt_xmit_get_cfa_action(skb); 327 if (skb_vlan_tag_present(skb)) { 328 vlan_tag_flags = TX_BD_CFA_META_KEY_VLAN | 329 skb_vlan_tag_get(skb); 330 /* Currently supports 8021Q, 8021AD vlan offloads 331 * QINQ1, QINQ2, QINQ3 vlan headers are deprecated 332 */ 333 if (skb->vlan_proto == htons(ETH_P_8021Q)) 334 vlan_tag_flags |= 1 << TX_BD_CFA_META_TPID_SHIFT; 335 } 336 337 if (free_size == bp->tx_ring_size && length <= bp->tx_push_thresh) { 338 struct tx_push_buffer *tx_push_buf = txr->tx_push; 339 struct tx_push_bd *tx_push = &tx_push_buf->push_bd; 340 struct tx_bd_ext *tx_push1 = &tx_push->txbd2; 341 void *pdata = tx_push_buf->data; 342 u64 *end; 343 int j, push_len; 344 345 /* Set COAL_NOW to be ready quickly for the next push */ 346 tx_push->tx_bd_len_flags_type = 347 cpu_to_le32((length << TX_BD_LEN_SHIFT) | 348 TX_BD_TYPE_LONG_TX_BD | 349 TX_BD_FLAGS_LHINT_512_AND_SMALLER | 350 TX_BD_FLAGS_COAL_NOW | 351 TX_BD_FLAGS_PACKET_END | 352 (2 << TX_BD_FLAGS_BD_CNT_SHIFT)); 353 354 if (skb->ip_summed == CHECKSUM_PARTIAL) 355 tx_push1->tx_bd_hsize_lflags = 356 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM); 357 else 358 tx_push1->tx_bd_hsize_lflags = 0; 359 360 tx_push1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags); 361 tx_push1->tx_bd_cfa_action = 362 cpu_to_le32(cfa_action << TX_BD_CFA_ACTION_SHIFT); 363 364 end = pdata + length; 365 end = PTR_ALIGN(end, 8) - 1; 366 *end = 0; 367 368 skb_copy_from_linear_data(skb, pdata, len); 369 pdata += len; 370 for (j = 0; j < last_frag; j++) { 371 skb_frag_t *frag = &skb_shinfo(skb)->frags[j]; 372 void *fptr; 373 374 fptr = skb_frag_address_safe(frag); 375 if (!fptr) 376 goto normal_tx; 377 378 memcpy(pdata, fptr, skb_frag_size(frag)); 379 pdata += skb_frag_size(frag); 380 } 381 382 txbd->tx_bd_len_flags_type = tx_push->tx_bd_len_flags_type; 383 txbd->tx_bd_haddr = txr->data_mapping; 384 prod = NEXT_TX(prod); 385 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)]; 386 memcpy(txbd, tx_push1, sizeof(*txbd)); 387 prod = NEXT_TX(prod); 388 tx_push->doorbell = 389 cpu_to_le32(DB_KEY_TX_PUSH | DB_LONG_TX_PUSH | prod); 390 txr->tx_prod = prod; 391 392 tx_buf->is_push = 1; 393 netdev_tx_sent_queue(txq, skb->len); 394 wmb(); /* Sync is_push and byte queue before pushing data */ 395 396 push_len = (length + sizeof(*tx_push) + 7) / 8; 397 if (push_len > 16) { 398 __iowrite64_copy(txr->tx_doorbell, tx_push_buf, 16); 399 __iowrite32_copy(txr->tx_doorbell + 4, tx_push_buf + 1, 400 (push_len - 16) << 1); 401 } else { 402 __iowrite64_copy(txr->tx_doorbell, tx_push_buf, 403 push_len); 404 } 405 406 goto tx_done; 407 } 408 409 normal_tx: 410 if (length < BNXT_MIN_PKT_SIZE) { 411 pad = BNXT_MIN_PKT_SIZE - length; 412 if (skb_pad(skb, pad)) { 413 /* SKB already freed. */ 414 tx_buf->skb = NULL; 415 return NETDEV_TX_OK; 416 } 417 length = BNXT_MIN_PKT_SIZE; 418 } 419 420 mapping = dma_map_single(&pdev->dev, skb->data, len, DMA_TO_DEVICE); 421 422 if (unlikely(dma_mapping_error(&pdev->dev, mapping))) { 423 dev_kfree_skb_any(skb); 424 tx_buf->skb = NULL; 425 return NETDEV_TX_OK; 426 } 427 428 dma_unmap_addr_set(tx_buf, mapping, mapping); 429 flags = (len << TX_BD_LEN_SHIFT) | TX_BD_TYPE_LONG_TX_BD | 430 ((last_frag + 2) << TX_BD_FLAGS_BD_CNT_SHIFT); 431 432 txbd->tx_bd_haddr = cpu_to_le64(mapping); 433 434 prod = NEXT_TX(prod); 435 txbd1 = (struct tx_bd_ext *) 436 &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)]; 437 438 txbd1->tx_bd_hsize_lflags = 0; 439 if (skb_is_gso(skb)) { 440 u32 hdr_len; 441 442 if (skb->encapsulation) 443 hdr_len = skb_inner_network_offset(skb) + 444 skb_inner_network_header_len(skb) + 445 inner_tcp_hdrlen(skb); 446 else 447 hdr_len = skb_transport_offset(skb) + 448 tcp_hdrlen(skb); 449 450 txbd1->tx_bd_hsize_lflags = cpu_to_le32(TX_BD_FLAGS_LSO | 451 TX_BD_FLAGS_T_IPID | 452 (hdr_len << (TX_BD_HSIZE_SHIFT - 1))); 453 length = skb_shinfo(skb)->gso_size; 454 txbd1->tx_bd_mss = cpu_to_le32(length); 455 length += hdr_len; 456 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 457 txbd1->tx_bd_hsize_lflags = 458 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM); 459 txbd1->tx_bd_mss = 0; 460 } 461 462 length >>= 9; 463 flags |= bnxt_lhint_arr[length]; 464 txbd->tx_bd_len_flags_type = cpu_to_le32(flags); 465 466 txbd1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags); 467 txbd1->tx_bd_cfa_action = 468 cpu_to_le32(cfa_action << TX_BD_CFA_ACTION_SHIFT); 469 for (i = 0; i < last_frag; i++) { 470 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 471 472 prod = NEXT_TX(prod); 473 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)]; 474 475 len = skb_frag_size(frag); 476 mapping = skb_frag_dma_map(&pdev->dev, frag, 0, len, 477 DMA_TO_DEVICE); 478 479 if (unlikely(dma_mapping_error(&pdev->dev, mapping))) 480 goto tx_dma_error; 481 482 tx_buf = &txr->tx_buf_ring[prod]; 483 dma_unmap_addr_set(tx_buf, mapping, mapping); 484 485 txbd->tx_bd_haddr = cpu_to_le64(mapping); 486 487 flags = len << TX_BD_LEN_SHIFT; 488 txbd->tx_bd_len_flags_type = cpu_to_le32(flags); 489 } 490 491 flags &= ~TX_BD_LEN; 492 txbd->tx_bd_len_flags_type = 493 cpu_to_le32(((len + pad) << TX_BD_LEN_SHIFT) | flags | 494 TX_BD_FLAGS_PACKET_END); 495 496 netdev_tx_sent_queue(txq, skb->len); 497 498 /* Sync BD data before updating doorbell */ 499 wmb(); 500 501 prod = NEXT_TX(prod); 502 txr->tx_prod = prod; 503 504 if (!skb->xmit_more || netif_xmit_stopped(txq)) 505 bnxt_db_write(bp, txr->tx_doorbell, DB_KEY_TX | prod); 506 507 tx_done: 508 509 mmiowb(); 510 511 if (unlikely(bnxt_tx_avail(bp, txr) <= MAX_SKB_FRAGS + 1)) { 512 if (skb->xmit_more && !tx_buf->is_push) 513 bnxt_db_write(bp, txr->tx_doorbell, DB_KEY_TX | prod); 514 515 netif_tx_stop_queue(txq); 516 517 /* netif_tx_stop_queue() must be done before checking 518 * tx index in bnxt_tx_avail() below, because in 519 * bnxt_tx_int(), we update tx index before checking for 520 * netif_tx_queue_stopped(). 521 */ 522 smp_mb(); 523 if (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh) 524 netif_tx_wake_queue(txq); 525 } 526 return NETDEV_TX_OK; 527 528 tx_dma_error: 529 last_frag = i; 530 531 /* start back at beginning and unmap skb */ 532 prod = txr->tx_prod; 533 tx_buf = &txr->tx_buf_ring[prod]; 534 tx_buf->skb = NULL; 535 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping), 536 skb_headlen(skb), PCI_DMA_TODEVICE); 537 prod = NEXT_TX(prod); 538 539 /* unmap remaining mapped pages */ 540 for (i = 0; i < last_frag; i++) { 541 prod = NEXT_TX(prod); 542 tx_buf = &txr->tx_buf_ring[prod]; 543 dma_unmap_page(&pdev->dev, dma_unmap_addr(tx_buf, mapping), 544 skb_frag_size(&skb_shinfo(skb)->frags[i]), 545 PCI_DMA_TODEVICE); 546 } 547 548 dev_kfree_skb_any(skb); 549 return NETDEV_TX_OK; 550 } 551 552 static void bnxt_tx_int(struct bnxt *bp, struct bnxt_napi *bnapi, int nr_pkts) 553 { 554 struct bnxt_tx_ring_info *txr = bnapi->tx_ring; 555 struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, txr->txq_index); 556 u16 cons = txr->tx_cons; 557 struct pci_dev *pdev = bp->pdev; 558 int i; 559 unsigned int tx_bytes = 0; 560 561 for (i = 0; i < nr_pkts; i++) { 562 struct bnxt_sw_tx_bd *tx_buf; 563 struct sk_buff *skb; 564 int j, last; 565 566 tx_buf = &txr->tx_buf_ring[cons]; 567 cons = NEXT_TX(cons); 568 skb = tx_buf->skb; 569 tx_buf->skb = NULL; 570 571 if (tx_buf->is_push) { 572 tx_buf->is_push = 0; 573 goto next_tx_int; 574 } 575 576 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping), 577 skb_headlen(skb), PCI_DMA_TODEVICE); 578 last = tx_buf->nr_frags; 579 580 for (j = 0; j < last; j++) { 581 cons = NEXT_TX(cons); 582 tx_buf = &txr->tx_buf_ring[cons]; 583 dma_unmap_page( 584 &pdev->dev, 585 dma_unmap_addr(tx_buf, mapping), 586 skb_frag_size(&skb_shinfo(skb)->frags[j]), 587 PCI_DMA_TODEVICE); 588 } 589 590 next_tx_int: 591 cons = NEXT_TX(cons); 592 593 tx_bytes += skb->len; 594 dev_kfree_skb_any(skb); 595 } 596 597 netdev_tx_completed_queue(txq, nr_pkts, tx_bytes); 598 txr->tx_cons = cons; 599 600 /* Need to make the tx_cons update visible to bnxt_start_xmit() 601 * before checking for netif_tx_queue_stopped(). Without the 602 * memory barrier, there is a small possibility that bnxt_start_xmit() 603 * will miss it and cause the queue to be stopped forever. 604 */ 605 smp_mb(); 606 607 if (unlikely(netif_tx_queue_stopped(txq)) && 608 (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)) { 609 __netif_tx_lock(txq, smp_processor_id()); 610 if (netif_tx_queue_stopped(txq) && 611 bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh && 612 txr->dev_state != BNXT_DEV_STATE_CLOSING) 613 netif_tx_wake_queue(txq); 614 __netif_tx_unlock(txq); 615 } 616 } 617 618 static struct page *__bnxt_alloc_rx_page(struct bnxt *bp, dma_addr_t *mapping, 619 gfp_t gfp) 620 { 621 struct device *dev = &bp->pdev->dev; 622 struct page *page; 623 624 page = alloc_page(gfp); 625 if (!page) 626 return NULL; 627 628 *mapping = dma_map_page_attrs(dev, page, 0, PAGE_SIZE, bp->rx_dir, 629 DMA_ATTR_WEAK_ORDERING); 630 if (dma_mapping_error(dev, *mapping)) { 631 __free_page(page); 632 return NULL; 633 } 634 *mapping += bp->rx_dma_offset; 635 return page; 636 } 637 638 static inline u8 *__bnxt_alloc_rx_data(struct bnxt *bp, dma_addr_t *mapping, 639 gfp_t gfp) 640 { 641 u8 *data; 642 struct pci_dev *pdev = bp->pdev; 643 644 data = kmalloc(bp->rx_buf_size, gfp); 645 if (!data) 646 return NULL; 647 648 *mapping = dma_map_single_attrs(&pdev->dev, data + bp->rx_dma_offset, 649 bp->rx_buf_use_size, bp->rx_dir, 650 DMA_ATTR_WEAK_ORDERING); 651 652 if (dma_mapping_error(&pdev->dev, *mapping)) { 653 kfree(data); 654 data = NULL; 655 } 656 return data; 657 } 658 659 int bnxt_alloc_rx_data(struct bnxt *bp, struct bnxt_rx_ring_info *rxr, 660 u16 prod, gfp_t gfp) 661 { 662 struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)]; 663 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[prod]; 664 dma_addr_t mapping; 665 666 if (BNXT_RX_PAGE_MODE(bp)) { 667 struct page *page = __bnxt_alloc_rx_page(bp, &mapping, gfp); 668 669 if (!page) 670 return -ENOMEM; 671 672 rx_buf->data = page; 673 rx_buf->data_ptr = page_address(page) + bp->rx_offset; 674 } else { 675 u8 *data = __bnxt_alloc_rx_data(bp, &mapping, gfp); 676 677 if (!data) 678 return -ENOMEM; 679 680 rx_buf->data = data; 681 rx_buf->data_ptr = data + bp->rx_offset; 682 } 683 rx_buf->mapping = mapping; 684 685 rxbd->rx_bd_haddr = cpu_to_le64(mapping); 686 return 0; 687 } 688 689 void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons, void *data) 690 { 691 u16 prod = rxr->rx_prod; 692 struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf; 693 struct rx_bd *cons_bd, *prod_bd; 694 695 prod_rx_buf = &rxr->rx_buf_ring[prod]; 696 cons_rx_buf = &rxr->rx_buf_ring[cons]; 697 698 prod_rx_buf->data = data; 699 prod_rx_buf->data_ptr = cons_rx_buf->data_ptr; 700 701 prod_rx_buf->mapping = cons_rx_buf->mapping; 702 703 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)]; 704 cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)]; 705 706 prod_bd->rx_bd_haddr = cons_bd->rx_bd_haddr; 707 } 708 709 static inline u16 bnxt_find_next_agg_idx(struct bnxt_rx_ring_info *rxr, u16 idx) 710 { 711 u16 next, max = rxr->rx_agg_bmap_size; 712 713 next = find_next_zero_bit(rxr->rx_agg_bmap, max, idx); 714 if (next >= max) 715 next = find_first_zero_bit(rxr->rx_agg_bmap, max); 716 return next; 717 } 718 719 static inline int bnxt_alloc_rx_page(struct bnxt *bp, 720 struct bnxt_rx_ring_info *rxr, 721 u16 prod, gfp_t gfp) 722 { 723 struct rx_bd *rxbd = 724 &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)]; 725 struct bnxt_sw_rx_agg_bd *rx_agg_buf; 726 struct pci_dev *pdev = bp->pdev; 727 struct page *page; 728 dma_addr_t mapping; 729 u16 sw_prod = rxr->rx_sw_agg_prod; 730 unsigned int offset = 0; 731 732 if (PAGE_SIZE > BNXT_RX_PAGE_SIZE) { 733 page = rxr->rx_page; 734 if (!page) { 735 page = alloc_page(gfp); 736 if (!page) 737 return -ENOMEM; 738 rxr->rx_page = page; 739 rxr->rx_page_offset = 0; 740 } 741 offset = rxr->rx_page_offset; 742 rxr->rx_page_offset += BNXT_RX_PAGE_SIZE; 743 if (rxr->rx_page_offset == PAGE_SIZE) 744 rxr->rx_page = NULL; 745 else 746 get_page(page); 747 } else { 748 page = alloc_page(gfp); 749 if (!page) 750 return -ENOMEM; 751 } 752 753 mapping = dma_map_page_attrs(&pdev->dev, page, offset, 754 BNXT_RX_PAGE_SIZE, PCI_DMA_FROMDEVICE, 755 DMA_ATTR_WEAK_ORDERING); 756 if (dma_mapping_error(&pdev->dev, mapping)) { 757 __free_page(page); 758 return -EIO; 759 } 760 761 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap))) 762 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod); 763 764 __set_bit(sw_prod, rxr->rx_agg_bmap); 765 rx_agg_buf = &rxr->rx_agg_ring[sw_prod]; 766 rxr->rx_sw_agg_prod = NEXT_RX_AGG(sw_prod); 767 768 rx_agg_buf->page = page; 769 rx_agg_buf->offset = offset; 770 rx_agg_buf->mapping = mapping; 771 rxbd->rx_bd_haddr = cpu_to_le64(mapping); 772 rxbd->rx_bd_opaque = sw_prod; 773 return 0; 774 } 775 776 static void bnxt_reuse_rx_agg_bufs(struct bnxt_napi *bnapi, u16 cp_cons, 777 u32 agg_bufs) 778 { 779 struct bnxt *bp = bnapi->bp; 780 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 781 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 782 u16 prod = rxr->rx_agg_prod; 783 u16 sw_prod = rxr->rx_sw_agg_prod; 784 u32 i; 785 786 for (i = 0; i < agg_bufs; i++) { 787 u16 cons; 788 struct rx_agg_cmp *agg; 789 struct bnxt_sw_rx_agg_bd *cons_rx_buf, *prod_rx_buf; 790 struct rx_bd *prod_bd; 791 struct page *page; 792 793 agg = (struct rx_agg_cmp *) 794 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 795 cons = agg->rx_agg_cmp_opaque; 796 __clear_bit(cons, rxr->rx_agg_bmap); 797 798 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap))) 799 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod); 800 801 __set_bit(sw_prod, rxr->rx_agg_bmap); 802 prod_rx_buf = &rxr->rx_agg_ring[sw_prod]; 803 cons_rx_buf = &rxr->rx_agg_ring[cons]; 804 805 /* It is possible for sw_prod to be equal to cons, so 806 * set cons_rx_buf->page to NULL first. 807 */ 808 page = cons_rx_buf->page; 809 cons_rx_buf->page = NULL; 810 prod_rx_buf->page = page; 811 prod_rx_buf->offset = cons_rx_buf->offset; 812 813 prod_rx_buf->mapping = cons_rx_buf->mapping; 814 815 prod_bd = &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)]; 816 817 prod_bd->rx_bd_haddr = cpu_to_le64(cons_rx_buf->mapping); 818 prod_bd->rx_bd_opaque = sw_prod; 819 820 prod = NEXT_RX_AGG(prod); 821 sw_prod = NEXT_RX_AGG(sw_prod); 822 cp_cons = NEXT_CMP(cp_cons); 823 } 824 rxr->rx_agg_prod = prod; 825 rxr->rx_sw_agg_prod = sw_prod; 826 } 827 828 static struct sk_buff *bnxt_rx_page_skb(struct bnxt *bp, 829 struct bnxt_rx_ring_info *rxr, 830 u16 cons, void *data, u8 *data_ptr, 831 dma_addr_t dma_addr, 832 unsigned int offset_and_len) 833 { 834 unsigned int payload = offset_and_len >> 16; 835 unsigned int len = offset_and_len & 0xffff; 836 struct skb_frag_struct *frag; 837 struct page *page = data; 838 u16 prod = rxr->rx_prod; 839 struct sk_buff *skb; 840 int off, err; 841 842 err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC); 843 if (unlikely(err)) { 844 bnxt_reuse_rx_data(rxr, cons, data); 845 return NULL; 846 } 847 dma_addr -= bp->rx_dma_offset; 848 dma_unmap_page_attrs(&bp->pdev->dev, dma_addr, PAGE_SIZE, bp->rx_dir, 849 DMA_ATTR_WEAK_ORDERING); 850 851 if (unlikely(!payload)) 852 payload = eth_get_headlen(data_ptr, len); 853 854 skb = napi_alloc_skb(&rxr->bnapi->napi, payload); 855 if (!skb) { 856 __free_page(page); 857 return NULL; 858 } 859 860 off = (void *)data_ptr - page_address(page); 861 skb_add_rx_frag(skb, 0, page, off, len, PAGE_SIZE); 862 memcpy(skb->data - NET_IP_ALIGN, data_ptr - NET_IP_ALIGN, 863 payload + NET_IP_ALIGN); 864 865 frag = &skb_shinfo(skb)->frags[0]; 866 skb_frag_size_sub(frag, payload); 867 frag->page_offset += payload; 868 skb->data_len -= payload; 869 skb->tail += payload; 870 871 return skb; 872 } 873 874 static struct sk_buff *bnxt_rx_skb(struct bnxt *bp, 875 struct bnxt_rx_ring_info *rxr, u16 cons, 876 void *data, u8 *data_ptr, 877 dma_addr_t dma_addr, 878 unsigned int offset_and_len) 879 { 880 u16 prod = rxr->rx_prod; 881 struct sk_buff *skb; 882 int err; 883 884 err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC); 885 if (unlikely(err)) { 886 bnxt_reuse_rx_data(rxr, cons, data); 887 return NULL; 888 } 889 890 skb = build_skb(data, 0); 891 dma_unmap_single_attrs(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size, 892 bp->rx_dir, DMA_ATTR_WEAK_ORDERING); 893 if (!skb) { 894 kfree(data); 895 return NULL; 896 } 897 898 skb_reserve(skb, bp->rx_offset); 899 skb_put(skb, offset_and_len & 0xffff); 900 return skb; 901 } 902 903 static struct sk_buff *bnxt_rx_pages(struct bnxt *bp, struct bnxt_napi *bnapi, 904 struct sk_buff *skb, u16 cp_cons, 905 u32 agg_bufs) 906 { 907 struct pci_dev *pdev = bp->pdev; 908 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 909 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 910 u16 prod = rxr->rx_agg_prod; 911 u32 i; 912 913 for (i = 0; i < agg_bufs; i++) { 914 u16 cons, frag_len; 915 struct rx_agg_cmp *agg; 916 struct bnxt_sw_rx_agg_bd *cons_rx_buf; 917 struct page *page; 918 dma_addr_t mapping; 919 920 agg = (struct rx_agg_cmp *) 921 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 922 cons = agg->rx_agg_cmp_opaque; 923 frag_len = (le32_to_cpu(agg->rx_agg_cmp_len_flags_type) & 924 RX_AGG_CMP_LEN) >> RX_AGG_CMP_LEN_SHIFT; 925 926 cons_rx_buf = &rxr->rx_agg_ring[cons]; 927 skb_fill_page_desc(skb, i, cons_rx_buf->page, 928 cons_rx_buf->offset, frag_len); 929 __clear_bit(cons, rxr->rx_agg_bmap); 930 931 /* It is possible for bnxt_alloc_rx_page() to allocate 932 * a sw_prod index that equals the cons index, so we 933 * need to clear the cons entry now. 934 */ 935 mapping = cons_rx_buf->mapping; 936 page = cons_rx_buf->page; 937 cons_rx_buf->page = NULL; 938 939 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_ATOMIC) != 0) { 940 struct skb_shared_info *shinfo; 941 unsigned int nr_frags; 942 943 shinfo = skb_shinfo(skb); 944 nr_frags = --shinfo->nr_frags; 945 __skb_frag_set_page(&shinfo->frags[nr_frags], NULL); 946 947 dev_kfree_skb(skb); 948 949 cons_rx_buf->page = page; 950 951 /* Update prod since possibly some pages have been 952 * allocated already. 953 */ 954 rxr->rx_agg_prod = prod; 955 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs - i); 956 return NULL; 957 } 958 959 dma_unmap_page_attrs(&pdev->dev, mapping, BNXT_RX_PAGE_SIZE, 960 PCI_DMA_FROMDEVICE, 961 DMA_ATTR_WEAK_ORDERING); 962 963 skb->data_len += frag_len; 964 skb->len += frag_len; 965 skb->truesize += PAGE_SIZE; 966 967 prod = NEXT_RX_AGG(prod); 968 cp_cons = NEXT_CMP(cp_cons); 969 } 970 rxr->rx_agg_prod = prod; 971 return skb; 972 } 973 974 static int bnxt_agg_bufs_valid(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, 975 u8 agg_bufs, u32 *raw_cons) 976 { 977 u16 last; 978 struct rx_agg_cmp *agg; 979 980 *raw_cons = ADV_RAW_CMP(*raw_cons, agg_bufs); 981 last = RING_CMP(*raw_cons); 982 agg = (struct rx_agg_cmp *) 983 &cpr->cp_desc_ring[CP_RING(last)][CP_IDX(last)]; 984 return RX_AGG_CMP_VALID(agg, *raw_cons); 985 } 986 987 static inline struct sk_buff *bnxt_copy_skb(struct bnxt_napi *bnapi, u8 *data, 988 unsigned int len, 989 dma_addr_t mapping) 990 { 991 struct bnxt *bp = bnapi->bp; 992 struct pci_dev *pdev = bp->pdev; 993 struct sk_buff *skb; 994 995 skb = napi_alloc_skb(&bnapi->napi, len); 996 if (!skb) 997 return NULL; 998 999 dma_sync_single_for_cpu(&pdev->dev, mapping, bp->rx_copy_thresh, 1000 bp->rx_dir); 1001 1002 memcpy(skb->data - NET_IP_ALIGN, data - NET_IP_ALIGN, 1003 len + NET_IP_ALIGN); 1004 1005 dma_sync_single_for_device(&pdev->dev, mapping, bp->rx_copy_thresh, 1006 bp->rx_dir); 1007 1008 skb_put(skb, len); 1009 return skb; 1010 } 1011 1012 static int bnxt_discard_rx(struct bnxt *bp, struct bnxt_napi *bnapi, 1013 u32 *raw_cons, void *cmp) 1014 { 1015 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 1016 struct rx_cmp *rxcmp = cmp; 1017 u32 tmp_raw_cons = *raw_cons; 1018 u8 cmp_type, agg_bufs = 0; 1019 1020 cmp_type = RX_CMP_TYPE(rxcmp); 1021 1022 if (cmp_type == CMP_TYPE_RX_L2_CMP) { 1023 agg_bufs = (le32_to_cpu(rxcmp->rx_cmp_misc_v1) & 1024 RX_CMP_AGG_BUFS) >> 1025 RX_CMP_AGG_BUFS_SHIFT; 1026 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) { 1027 struct rx_tpa_end_cmp *tpa_end = cmp; 1028 1029 agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) & 1030 RX_TPA_END_CMP_AGG_BUFS) >> 1031 RX_TPA_END_CMP_AGG_BUFS_SHIFT; 1032 } 1033 1034 if (agg_bufs) { 1035 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons)) 1036 return -EBUSY; 1037 } 1038 *raw_cons = tmp_raw_cons; 1039 return 0; 1040 } 1041 1042 static void bnxt_queue_sp_work(struct bnxt *bp) 1043 { 1044 if (BNXT_PF(bp)) 1045 queue_work(bnxt_pf_wq, &bp->sp_task); 1046 else 1047 schedule_work(&bp->sp_task); 1048 } 1049 1050 static void bnxt_cancel_sp_work(struct bnxt *bp) 1051 { 1052 if (BNXT_PF(bp)) 1053 flush_workqueue(bnxt_pf_wq); 1054 else 1055 cancel_work_sync(&bp->sp_task); 1056 } 1057 1058 static void bnxt_sched_reset(struct bnxt *bp, struct bnxt_rx_ring_info *rxr) 1059 { 1060 if (!rxr->bnapi->in_reset) { 1061 rxr->bnapi->in_reset = true; 1062 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event); 1063 bnxt_queue_sp_work(bp); 1064 } 1065 rxr->rx_next_cons = 0xffff; 1066 } 1067 1068 static void bnxt_tpa_start(struct bnxt *bp, struct bnxt_rx_ring_info *rxr, 1069 struct rx_tpa_start_cmp *tpa_start, 1070 struct rx_tpa_start_cmp_ext *tpa_start1) 1071 { 1072 u8 agg_id = TPA_START_AGG_ID(tpa_start); 1073 u16 cons, prod; 1074 struct bnxt_tpa_info *tpa_info; 1075 struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf; 1076 struct rx_bd *prod_bd; 1077 dma_addr_t mapping; 1078 1079 cons = tpa_start->rx_tpa_start_cmp_opaque; 1080 prod = rxr->rx_prod; 1081 cons_rx_buf = &rxr->rx_buf_ring[cons]; 1082 prod_rx_buf = &rxr->rx_buf_ring[prod]; 1083 tpa_info = &rxr->rx_tpa[agg_id]; 1084 1085 if (unlikely(cons != rxr->rx_next_cons)) { 1086 bnxt_sched_reset(bp, rxr); 1087 return; 1088 } 1089 /* Store cfa_code in tpa_info to use in tpa_end 1090 * completion processing. 1091 */ 1092 tpa_info->cfa_code = TPA_START_CFA_CODE(tpa_start1); 1093 prod_rx_buf->data = tpa_info->data; 1094 prod_rx_buf->data_ptr = tpa_info->data_ptr; 1095 1096 mapping = tpa_info->mapping; 1097 prod_rx_buf->mapping = mapping; 1098 1099 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)]; 1100 1101 prod_bd->rx_bd_haddr = cpu_to_le64(mapping); 1102 1103 tpa_info->data = cons_rx_buf->data; 1104 tpa_info->data_ptr = cons_rx_buf->data_ptr; 1105 cons_rx_buf->data = NULL; 1106 tpa_info->mapping = cons_rx_buf->mapping; 1107 1108 tpa_info->len = 1109 le32_to_cpu(tpa_start->rx_tpa_start_cmp_len_flags_type) >> 1110 RX_TPA_START_CMP_LEN_SHIFT; 1111 if (likely(TPA_START_HASH_VALID(tpa_start))) { 1112 u32 hash_type = TPA_START_HASH_TYPE(tpa_start); 1113 1114 tpa_info->hash_type = PKT_HASH_TYPE_L4; 1115 tpa_info->gso_type = SKB_GSO_TCPV4; 1116 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */ 1117 if (hash_type == 3) 1118 tpa_info->gso_type = SKB_GSO_TCPV6; 1119 tpa_info->rss_hash = 1120 le32_to_cpu(tpa_start->rx_tpa_start_cmp_rss_hash); 1121 } else { 1122 tpa_info->hash_type = PKT_HASH_TYPE_NONE; 1123 tpa_info->gso_type = 0; 1124 if (netif_msg_rx_err(bp)) 1125 netdev_warn(bp->dev, "TPA packet without valid hash\n"); 1126 } 1127 tpa_info->flags2 = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_flags2); 1128 tpa_info->metadata = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_metadata); 1129 tpa_info->hdr_info = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_hdr_info); 1130 1131 rxr->rx_prod = NEXT_RX(prod); 1132 cons = NEXT_RX(cons); 1133 rxr->rx_next_cons = NEXT_RX(cons); 1134 cons_rx_buf = &rxr->rx_buf_ring[cons]; 1135 1136 bnxt_reuse_rx_data(rxr, cons, cons_rx_buf->data); 1137 rxr->rx_prod = NEXT_RX(rxr->rx_prod); 1138 cons_rx_buf->data = NULL; 1139 } 1140 1141 static void bnxt_abort_tpa(struct bnxt *bp, struct bnxt_napi *bnapi, 1142 u16 cp_cons, u32 agg_bufs) 1143 { 1144 if (agg_bufs) 1145 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs); 1146 } 1147 1148 static struct sk_buff *bnxt_gro_func_5731x(struct bnxt_tpa_info *tpa_info, 1149 int payload_off, int tcp_ts, 1150 struct sk_buff *skb) 1151 { 1152 #ifdef CONFIG_INET 1153 struct tcphdr *th; 1154 int len, nw_off; 1155 u16 outer_ip_off, inner_ip_off, inner_mac_off; 1156 u32 hdr_info = tpa_info->hdr_info; 1157 bool loopback = false; 1158 1159 inner_ip_off = BNXT_TPA_INNER_L3_OFF(hdr_info); 1160 inner_mac_off = BNXT_TPA_INNER_L2_OFF(hdr_info); 1161 outer_ip_off = BNXT_TPA_OUTER_L3_OFF(hdr_info); 1162 1163 /* If the packet is an internal loopback packet, the offsets will 1164 * have an extra 4 bytes. 1165 */ 1166 if (inner_mac_off == 4) { 1167 loopback = true; 1168 } else if (inner_mac_off > 4) { 1169 __be16 proto = *((__be16 *)(skb->data + inner_ip_off - 1170 ETH_HLEN - 2)); 1171 1172 /* We only support inner iPv4/ipv6. If we don't see the 1173 * correct protocol ID, it must be a loopback packet where 1174 * the offsets are off by 4. 1175 */ 1176 if (proto != htons(ETH_P_IP) && proto != htons(ETH_P_IPV6)) 1177 loopback = true; 1178 } 1179 if (loopback) { 1180 /* internal loopback packet, subtract all offsets by 4 */ 1181 inner_ip_off -= 4; 1182 inner_mac_off -= 4; 1183 outer_ip_off -= 4; 1184 } 1185 1186 nw_off = inner_ip_off - ETH_HLEN; 1187 skb_set_network_header(skb, nw_off); 1188 if (tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_IP_TYPE) { 1189 struct ipv6hdr *iph = ipv6_hdr(skb); 1190 1191 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr)); 1192 len = skb->len - skb_transport_offset(skb); 1193 th = tcp_hdr(skb); 1194 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0); 1195 } else { 1196 struct iphdr *iph = ip_hdr(skb); 1197 1198 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr)); 1199 len = skb->len - skb_transport_offset(skb); 1200 th = tcp_hdr(skb); 1201 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0); 1202 } 1203 1204 if (inner_mac_off) { /* tunnel */ 1205 struct udphdr *uh = NULL; 1206 __be16 proto = *((__be16 *)(skb->data + outer_ip_off - 1207 ETH_HLEN - 2)); 1208 1209 if (proto == htons(ETH_P_IP)) { 1210 struct iphdr *iph = (struct iphdr *)skb->data; 1211 1212 if (iph->protocol == IPPROTO_UDP) 1213 uh = (struct udphdr *)(iph + 1); 1214 } else { 1215 struct ipv6hdr *iph = (struct ipv6hdr *)skb->data; 1216 1217 if (iph->nexthdr == IPPROTO_UDP) 1218 uh = (struct udphdr *)(iph + 1); 1219 } 1220 if (uh) { 1221 if (uh->check) 1222 skb_shinfo(skb)->gso_type |= 1223 SKB_GSO_UDP_TUNNEL_CSUM; 1224 else 1225 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL; 1226 } 1227 } 1228 #endif 1229 return skb; 1230 } 1231 1232 #define BNXT_IPV4_HDR_SIZE (sizeof(struct iphdr) + sizeof(struct tcphdr)) 1233 #define BNXT_IPV6_HDR_SIZE (sizeof(struct ipv6hdr) + sizeof(struct tcphdr)) 1234 1235 static struct sk_buff *bnxt_gro_func_5730x(struct bnxt_tpa_info *tpa_info, 1236 int payload_off, int tcp_ts, 1237 struct sk_buff *skb) 1238 { 1239 #ifdef CONFIG_INET 1240 struct tcphdr *th; 1241 int len, nw_off, tcp_opt_len = 0; 1242 1243 if (tcp_ts) 1244 tcp_opt_len = 12; 1245 1246 if (tpa_info->gso_type == SKB_GSO_TCPV4) { 1247 struct iphdr *iph; 1248 1249 nw_off = payload_off - BNXT_IPV4_HDR_SIZE - tcp_opt_len - 1250 ETH_HLEN; 1251 skb_set_network_header(skb, nw_off); 1252 iph = ip_hdr(skb); 1253 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr)); 1254 len = skb->len - skb_transport_offset(skb); 1255 th = tcp_hdr(skb); 1256 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0); 1257 } else if (tpa_info->gso_type == SKB_GSO_TCPV6) { 1258 struct ipv6hdr *iph; 1259 1260 nw_off = payload_off - BNXT_IPV6_HDR_SIZE - tcp_opt_len - 1261 ETH_HLEN; 1262 skb_set_network_header(skb, nw_off); 1263 iph = ipv6_hdr(skb); 1264 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr)); 1265 len = skb->len - skb_transport_offset(skb); 1266 th = tcp_hdr(skb); 1267 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0); 1268 } else { 1269 dev_kfree_skb_any(skb); 1270 return NULL; 1271 } 1272 1273 if (nw_off) { /* tunnel */ 1274 struct udphdr *uh = NULL; 1275 1276 if (skb->protocol == htons(ETH_P_IP)) { 1277 struct iphdr *iph = (struct iphdr *)skb->data; 1278 1279 if (iph->protocol == IPPROTO_UDP) 1280 uh = (struct udphdr *)(iph + 1); 1281 } else { 1282 struct ipv6hdr *iph = (struct ipv6hdr *)skb->data; 1283 1284 if (iph->nexthdr == IPPROTO_UDP) 1285 uh = (struct udphdr *)(iph + 1); 1286 } 1287 if (uh) { 1288 if (uh->check) 1289 skb_shinfo(skb)->gso_type |= 1290 SKB_GSO_UDP_TUNNEL_CSUM; 1291 else 1292 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL; 1293 } 1294 } 1295 #endif 1296 return skb; 1297 } 1298 1299 static inline struct sk_buff *bnxt_gro_skb(struct bnxt *bp, 1300 struct bnxt_tpa_info *tpa_info, 1301 struct rx_tpa_end_cmp *tpa_end, 1302 struct rx_tpa_end_cmp_ext *tpa_end1, 1303 struct sk_buff *skb) 1304 { 1305 #ifdef CONFIG_INET 1306 int payload_off; 1307 u16 segs; 1308 1309 segs = TPA_END_TPA_SEGS(tpa_end); 1310 if (segs == 1) 1311 return skb; 1312 1313 NAPI_GRO_CB(skb)->count = segs; 1314 skb_shinfo(skb)->gso_size = 1315 le32_to_cpu(tpa_end1->rx_tpa_end_cmp_seg_len); 1316 skb_shinfo(skb)->gso_type = tpa_info->gso_type; 1317 payload_off = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) & 1318 RX_TPA_END_CMP_PAYLOAD_OFFSET) >> 1319 RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT; 1320 skb = bp->gro_func(tpa_info, payload_off, TPA_END_GRO_TS(tpa_end), skb); 1321 if (likely(skb)) 1322 tcp_gro_complete(skb); 1323 #endif 1324 return skb; 1325 } 1326 1327 /* Given the cfa_code of a received packet determine which 1328 * netdev (vf-rep or PF) the packet is destined to. 1329 */ 1330 static struct net_device *bnxt_get_pkt_dev(struct bnxt *bp, u16 cfa_code) 1331 { 1332 struct net_device *dev = bnxt_get_vf_rep(bp, cfa_code); 1333 1334 /* if vf-rep dev is NULL, the must belongs to the PF */ 1335 return dev ? dev : bp->dev; 1336 } 1337 1338 static inline struct sk_buff *bnxt_tpa_end(struct bnxt *bp, 1339 struct bnxt_napi *bnapi, 1340 u32 *raw_cons, 1341 struct rx_tpa_end_cmp *tpa_end, 1342 struct rx_tpa_end_cmp_ext *tpa_end1, 1343 u8 *event) 1344 { 1345 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 1346 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 1347 u8 agg_id = TPA_END_AGG_ID(tpa_end); 1348 u8 *data_ptr, agg_bufs; 1349 u16 cp_cons = RING_CMP(*raw_cons); 1350 unsigned int len; 1351 struct bnxt_tpa_info *tpa_info; 1352 dma_addr_t mapping; 1353 struct sk_buff *skb; 1354 void *data; 1355 1356 if (unlikely(bnapi->in_reset)) { 1357 int rc = bnxt_discard_rx(bp, bnapi, raw_cons, tpa_end); 1358 1359 if (rc < 0) 1360 return ERR_PTR(-EBUSY); 1361 return NULL; 1362 } 1363 1364 tpa_info = &rxr->rx_tpa[agg_id]; 1365 data = tpa_info->data; 1366 data_ptr = tpa_info->data_ptr; 1367 prefetch(data_ptr); 1368 len = tpa_info->len; 1369 mapping = tpa_info->mapping; 1370 1371 agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) & 1372 RX_TPA_END_CMP_AGG_BUFS) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT; 1373 1374 if (agg_bufs) { 1375 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, raw_cons)) 1376 return ERR_PTR(-EBUSY); 1377 1378 *event |= BNXT_AGG_EVENT; 1379 cp_cons = NEXT_CMP(cp_cons); 1380 } 1381 1382 if (unlikely(agg_bufs > MAX_SKB_FRAGS || TPA_END_ERRORS(tpa_end1))) { 1383 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs); 1384 if (agg_bufs > MAX_SKB_FRAGS) 1385 netdev_warn(bp->dev, "TPA frags %d exceeded MAX_SKB_FRAGS %d\n", 1386 agg_bufs, (int)MAX_SKB_FRAGS); 1387 return NULL; 1388 } 1389 1390 if (len <= bp->rx_copy_thresh) { 1391 skb = bnxt_copy_skb(bnapi, data_ptr, len, mapping); 1392 if (!skb) { 1393 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs); 1394 return NULL; 1395 } 1396 } else { 1397 u8 *new_data; 1398 dma_addr_t new_mapping; 1399 1400 new_data = __bnxt_alloc_rx_data(bp, &new_mapping, GFP_ATOMIC); 1401 if (!new_data) { 1402 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs); 1403 return NULL; 1404 } 1405 1406 tpa_info->data = new_data; 1407 tpa_info->data_ptr = new_data + bp->rx_offset; 1408 tpa_info->mapping = new_mapping; 1409 1410 skb = build_skb(data, 0); 1411 dma_unmap_single_attrs(&bp->pdev->dev, mapping, 1412 bp->rx_buf_use_size, bp->rx_dir, 1413 DMA_ATTR_WEAK_ORDERING); 1414 1415 if (!skb) { 1416 kfree(data); 1417 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs); 1418 return NULL; 1419 } 1420 skb_reserve(skb, bp->rx_offset); 1421 skb_put(skb, len); 1422 } 1423 1424 if (agg_bufs) { 1425 skb = bnxt_rx_pages(bp, bnapi, skb, cp_cons, agg_bufs); 1426 if (!skb) { 1427 /* Page reuse already handled by bnxt_rx_pages(). */ 1428 return NULL; 1429 } 1430 } 1431 1432 skb->protocol = 1433 eth_type_trans(skb, bnxt_get_pkt_dev(bp, tpa_info->cfa_code)); 1434 1435 if (tpa_info->hash_type != PKT_HASH_TYPE_NONE) 1436 skb_set_hash(skb, tpa_info->rss_hash, tpa_info->hash_type); 1437 1438 if ((tpa_info->flags2 & RX_CMP_FLAGS2_META_FORMAT_VLAN) && 1439 (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) { 1440 u16 vlan_proto = tpa_info->metadata >> 1441 RX_CMP_FLAGS2_METADATA_TPID_SFT; 1442 u16 vtag = tpa_info->metadata & RX_CMP_FLAGS2_METADATA_VID_MASK; 1443 1444 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag); 1445 } 1446 1447 skb_checksum_none_assert(skb); 1448 if (likely(tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_L4_CS_CALC)) { 1449 skb->ip_summed = CHECKSUM_UNNECESSARY; 1450 skb->csum_level = 1451 (tpa_info->flags2 & RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3; 1452 } 1453 1454 if (TPA_END_GRO(tpa_end)) 1455 skb = bnxt_gro_skb(bp, tpa_info, tpa_end, tpa_end1, skb); 1456 1457 return skb; 1458 } 1459 1460 static void bnxt_deliver_skb(struct bnxt *bp, struct bnxt_napi *bnapi, 1461 struct sk_buff *skb) 1462 { 1463 if (skb->dev != bp->dev) { 1464 /* this packet belongs to a vf-rep */ 1465 bnxt_vf_rep_rx(bp, skb); 1466 return; 1467 } 1468 skb_record_rx_queue(skb, bnapi->index); 1469 napi_gro_receive(&bnapi->napi, skb); 1470 } 1471 1472 /* returns the following: 1473 * 1 - 1 packet successfully received 1474 * 0 - successful TPA_START, packet not completed yet 1475 * -EBUSY - completion ring does not have all the agg buffers yet 1476 * -ENOMEM - packet aborted due to out of memory 1477 * -EIO - packet aborted due to hw error indicated in BD 1478 */ 1479 static int bnxt_rx_pkt(struct bnxt *bp, struct bnxt_napi *bnapi, u32 *raw_cons, 1480 u8 *event) 1481 { 1482 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 1483 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 1484 struct net_device *dev = bp->dev; 1485 struct rx_cmp *rxcmp; 1486 struct rx_cmp_ext *rxcmp1; 1487 u32 tmp_raw_cons = *raw_cons; 1488 u16 cfa_code, cons, prod, cp_cons = RING_CMP(tmp_raw_cons); 1489 struct bnxt_sw_rx_bd *rx_buf; 1490 unsigned int len; 1491 u8 *data_ptr, agg_bufs, cmp_type; 1492 dma_addr_t dma_addr; 1493 struct sk_buff *skb; 1494 void *data; 1495 int rc = 0; 1496 u32 misc; 1497 1498 rxcmp = (struct rx_cmp *) 1499 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 1500 1501 tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons); 1502 cp_cons = RING_CMP(tmp_raw_cons); 1503 rxcmp1 = (struct rx_cmp_ext *) 1504 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 1505 1506 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons)) 1507 return -EBUSY; 1508 1509 cmp_type = RX_CMP_TYPE(rxcmp); 1510 1511 prod = rxr->rx_prod; 1512 1513 if (cmp_type == CMP_TYPE_RX_L2_TPA_START_CMP) { 1514 bnxt_tpa_start(bp, rxr, (struct rx_tpa_start_cmp *)rxcmp, 1515 (struct rx_tpa_start_cmp_ext *)rxcmp1); 1516 1517 *event |= BNXT_RX_EVENT; 1518 goto next_rx_no_prod_no_len; 1519 1520 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) { 1521 skb = bnxt_tpa_end(bp, bnapi, &tmp_raw_cons, 1522 (struct rx_tpa_end_cmp *)rxcmp, 1523 (struct rx_tpa_end_cmp_ext *)rxcmp1, event); 1524 1525 if (IS_ERR(skb)) 1526 return -EBUSY; 1527 1528 rc = -ENOMEM; 1529 if (likely(skb)) { 1530 bnxt_deliver_skb(bp, bnapi, skb); 1531 rc = 1; 1532 } 1533 *event |= BNXT_RX_EVENT; 1534 goto next_rx_no_prod_no_len; 1535 } 1536 1537 cons = rxcmp->rx_cmp_opaque; 1538 rx_buf = &rxr->rx_buf_ring[cons]; 1539 data = rx_buf->data; 1540 data_ptr = rx_buf->data_ptr; 1541 if (unlikely(cons != rxr->rx_next_cons)) { 1542 int rc1 = bnxt_discard_rx(bp, bnapi, raw_cons, rxcmp); 1543 1544 bnxt_sched_reset(bp, rxr); 1545 return rc1; 1546 } 1547 prefetch(data_ptr); 1548 1549 misc = le32_to_cpu(rxcmp->rx_cmp_misc_v1); 1550 agg_bufs = (misc & RX_CMP_AGG_BUFS) >> RX_CMP_AGG_BUFS_SHIFT; 1551 1552 if (agg_bufs) { 1553 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons)) 1554 return -EBUSY; 1555 1556 cp_cons = NEXT_CMP(cp_cons); 1557 *event |= BNXT_AGG_EVENT; 1558 } 1559 *event |= BNXT_RX_EVENT; 1560 1561 rx_buf->data = NULL; 1562 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L2_ERRORS) { 1563 bnxt_reuse_rx_data(rxr, cons, data); 1564 if (agg_bufs) 1565 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs); 1566 1567 rc = -EIO; 1568 goto next_rx; 1569 } 1570 1571 len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT; 1572 dma_addr = rx_buf->mapping; 1573 1574 if (bnxt_rx_xdp(bp, rxr, cons, data, &data_ptr, &len, event)) { 1575 rc = 1; 1576 goto next_rx; 1577 } 1578 1579 if (len <= bp->rx_copy_thresh) { 1580 skb = bnxt_copy_skb(bnapi, data_ptr, len, dma_addr); 1581 bnxt_reuse_rx_data(rxr, cons, data); 1582 if (!skb) { 1583 rc = -ENOMEM; 1584 goto next_rx; 1585 } 1586 } else { 1587 u32 payload; 1588 1589 if (rx_buf->data_ptr == data_ptr) 1590 payload = misc & RX_CMP_PAYLOAD_OFFSET; 1591 else 1592 payload = 0; 1593 skb = bp->rx_skb_func(bp, rxr, cons, data, data_ptr, dma_addr, 1594 payload | len); 1595 if (!skb) { 1596 rc = -ENOMEM; 1597 goto next_rx; 1598 } 1599 } 1600 1601 if (agg_bufs) { 1602 skb = bnxt_rx_pages(bp, bnapi, skb, cp_cons, agg_bufs); 1603 if (!skb) { 1604 rc = -ENOMEM; 1605 goto next_rx; 1606 } 1607 } 1608 1609 if (RX_CMP_HASH_VALID(rxcmp)) { 1610 u32 hash_type = RX_CMP_HASH_TYPE(rxcmp); 1611 enum pkt_hash_types type = PKT_HASH_TYPE_L4; 1612 1613 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */ 1614 if (hash_type != 1 && hash_type != 3) 1615 type = PKT_HASH_TYPE_L3; 1616 skb_set_hash(skb, le32_to_cpu(rxcmp->rx_cmp_rss_hash), type); 1617 } 1618 1619 cfa_code = RX_CMP_CFA_CODE(rxcmp1); 1620 skb->protocol = eth_type_trans(skb, bnxt_get_pkt_dev(bp, cfa_code)); 1621 1622 if ((rxcmp1->rx_cmp_flags2 & 1623 cpu_to_le32(RX_CMP_FLAGS2_META_FORMAT_VLAN)) && 1624 (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) { 1625 u32 meta_data = le32_to_cpu(rxcmp1->rx_cmp_meta_data); 1626 u16 vtag = meta_data & RX_CMP_FLAGS2_METADATA_VID_MASK; 1627 u16 vlan_proto = meta_data >> RX_CMP_FLAGS2_METADATA_TPID_SFT; 1628 1629 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag); 1630 } 1631 1632 skb_checksum_none_assert(skb); 1633 if (RX_CMP_L4_CS_OK(rxcmp1)) { 1634 if (dev->features & NETIF_F_RXCSUM) { 1635 skb->ip_summed = CHECKSUM_UNNECESSARY; 1636 skb->csum_level = RX_CMP_ENCAP(rxcmp1); 1637 } 1638 } else { 1639 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS) { 1640 if (dev->features & NETIF_F_RXCSUM) 1641 cpr->rx_l4_csum_errors++; 1642 } 1643 } 1644 1645 bnxt_deliver_skb(bp, bnapi, skb); 1646 rc = 1; 1647 1648 next_rx: 1649 rxr->rx_prod = NEXT_RX(prod); 1650 rxr->rx_next_cons = NEXT_RX(cons); 1651 1652 cpr->rx_packets += 1; 1653 cpr->rx_bytes += len; 1654 1655 next_rx_no_prod_no_len: 1656 *raw_cons = tmp_raw_cons; 1657 1658 return rc; 1659 } 1660 1661 /* In netpoll mode, if we are using a combined completion ring, we need to 1662 * discard the rx packets and recycle the buffers. 1663 */ 1664 static int bnxt_force_rx_discard(struct bnxt *bp, struct bnxt_napi *bnapi, 1665 u32 *raw_cons, u8 *event) 1666 { 1667 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 1668 u32 tmp_raw_cons = *raw_cons; 1669 struct rx_cmp_ext *rxcmp1; 1670 struct rx_cmp *rxcmp; 1671 u16 cp_cons; 1672 u8 cmp_type; 1673 1674 cp_cons = RING_CMP(tmp_raw_cons); 1675 rxcmp = (struct rx_cmp *) 1676 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 1677 1678 tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons); 1679 cp_cons = RING_CMP(tmp_raw_cons); 1680 rxcmp1 = (struct rx_cmp_ext *) 1681 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 1682 1683 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons)) 1684 return -EBUSY; 1685 1686 cmp_type = RX_CMP_TYPE(rxcmp); 1687 if (cmp_type == CMP_TYPE_RX_L2_CMP) { 1688 rxcmp1->rx_cmp_cfa_code_errors_v2 |= 1689 cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR); 1690 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) { 1691 struct rx_tpa_end_cmp_ext *tpa_end1; 1692 1693 tpa_end1 = (struct rx_tpa_end_cmp_ext *)rxcmp1; 1694 tpa_end1->rx_tpa_end_cmp_errors_v2 |= 1695 cpu_to_le32(RX_TPA_END_CMP_ERRORS); 1696 } 1697 return bnxt_rx_pkt(bp, bnapi, raw_cons, event); 1698 } 1699 1700 #define BNXT_GET_EVENT_PORT(data) \ 1701 ((data) & \ 1702 ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK) 1703 1704 static int bnxt_async_event_process(struct bnxt *bp, 1705 struct hwrm_async_event_cmpl *cmpl) 1706 { 1707 u16 event_id = le16_to_cpu(cmpl->event_id); 1708 1709 /* TODO CHIMP_FW: Define event id's for link change, error etc */ 1710 switch (event_id) { 1711 case ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE: { 1712 u32 data1 = le32_to_cpu(cmpl->event_data1); 1713 struct bnxt_link_info *link_info = &bp->link_info; 1714 1715 if (BNXT_VF(bp)) 1716 goto async_event_process_exit; 1717 1718 /* print unsupported speed warning in forced speed mode only */ 1719 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED) && 1720 (data1 & 0x20000)) { 1721 u16 fw_speed = link_info->force_link_speed; 1722 u32 speed = bnxt_fw_to_ethtool_speed(fw_speed); 1723 1724 if (speed != SPEED_UNKNOWN) 1725 netdev_warn(bp->dev, "Link speed %d no longer supported\n", 1726 speed); 1727 } 1728 set_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT, &bp->sp_event); 1729 /* fall thru */ 1730 } 1731 case ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE: 1732 set_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event); 1733 break; 1734 case ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD: 1735 set_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event); 1736 break; 1737 case ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED: { 1738 u32 data1 = le32_to_cpu(cmpl->event_data1); 1739 u16 port_id = BNXT_GET_EVENT_PORT(data1); 1740 1741 if (BNXT_VF(bp)) 1742 break; 1743 1744 if (bp->pf.port_id != port_id) 1745 break; 1746 1747 set_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event); 1748 break; 1749 } 1750 case ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE: 1751 if (BNXT_PF(bp)) 1752 goto async_event_process_exit; 1753 set_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event); 1754 break; 1755 default: 1756 goto async_event_process_exit; 1757 } 1758 bnxt_queue_sp_work(bp); 1759 async_event_process_exit: 1760 bnxt_ulp_async_events(bp, cmpl); 1761 return 0; 1762 } 1763 1764 static int bnxt_hwrm_handler(struct bnxt *bp, struct tx_cmp *txcmp) 1765 { 1766 u16 cmpl_type = TX_CMP_TYPE(txcmp), vf_id, seq_id; 1767 struct hwrm_cmpl *h_cmpl = (struct hwrm_cmpl *)txcmp; 1768 struct hwrm_fwd_req_cmpl *fwd_req_cmpl = 1769 (struct hwrm_fwd_req_cmpl *)txcmp; 1770 1771 switch (cmpl_type) { 1772 case CMPL_BASE_TYPE_HWRM_DONE: 1773 seq_id = le16_to_cpu(h_cmpl->sequence_id); 1774 if (seq_id == bp->hwrm_intr_seq_id) 1775 bp->hwrm_intr_seq_id = HWRM_SEQ_ID_INVALID; 1776 else 1777 netdev_err(bp->dev, "Invalid hwrm seq id %d\n", seq_id); 1778 break; 1779 1780 case CMPL_BASE_TYPE_HWRM_FWD_REQ: 1781 vf_id = le16_to_cpu(fwd_req_cmpl->source_id); 1782 1783 if ((vf_id < bp->pf.first_vf_id) || 1784 (vf_id >= bp->pf.first_vf_id + bp->pf.active_vfs)) { 1785 netdev_err(bp->dev, "Msg contains invalid VF id %x\n", 1786 vf_id); 1787 return -EINVAL; 1788 } 1789 1790 set_bit(vf_id - bp->pf.first_vf_id, bp->pf.vf_event_bmap); 1791 set_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event); 1792 bnxt_queue_sp_work(bp); 1793 break; 1794 1795 case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT: 1796 bnxt_async_event_process(bp, 1797 (struct hwrm_async_event_cmpl *)txcmp); 1798 1799 default: 1800 break; 1801 } 1802 1803 return 0; 1804 } 1805 1806 static irqreturn_t bnxt_msix(int irq, void *dev_instance) 1807 { 1808 struct bnxt_napi *bnapi = dev_instance; 1809 struct bnxt *bp = bnapi->bp; 1810 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 1811 u32 cons = RING_CMP(cpr->cp_raw_cons); 1812 1813 cpr->event_ctr++; 1814 prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]); 1815 napi_schedule(&bnapi->napi); 1816 return IRQ_HANDLED; 1817 } 1818 1819 static inline int bnxt_has_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr) 1820 { 1821 u32 raw_cons = cpr->cp_raw_cons; 1822 u16 cons = RING_CMP(raw_cons); 1823 struct tx_cmp *txcmp; 1824 1825 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]; 1826 1827 return TX_CMP_VALID(txcmp, raw_cons); 1828 } 1829 1830 static irqreturn_t bnxt_inta(int irq, void *dev_instance) 1831 { 1832 struct bnxt_napi *bnapi = dev_instance; 1833 struct bnxt *bp = bnapi->bp; 1834 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 1835 u32 cons = RING_CMP(cpr->cp_raw_cons); 1836 u32 int_status; 1837 1838 prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]); 1839 1840 if (!bnxt_has_work(bp, cpr)) { 1841 int_status = readl(bp->bar0 + BNXT_CAG_REG_LEGACY_INT_STATUS); 1842 /* return if erroneous interrupt */ 1843 if (!(int_status & (0x10000 << cpr->cp_ring_struct.fw_ring_id))) 1844 return IRQ_NONE; 1845 } 1846 1847 /* disable ring IRQ */ 1848 BNXT_CP_DB_IRQ_DIS(cpr->cp_doorbell); 1849 1850 /* Return here if interrupt is shared and is disabled. */ 1851 if (unlikely(atomic_read(&bp->intr_sem) != 0)) 1852 return IRQ_HANDLED; 1853 1854 napi_schedule(&bnapi->napi); 1855 return IRQ_HANDLED; 1856 } 1857 1858 static int bnxt_poll_work(struct bnxt *bp, struct bnxt_napi *bnapi, int budget) 1859 { 1860 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 1861 u32 raw_cons = cpr->cp_raw_cons; 1862 u32 cons; 1863 int tx_pkts = 0; 1864 int rx_pkts = 0; 1865 u8 event = 0; 1866 struct tx_cmp *txcmp; 1867 1868 while (1) { 1869 int rc; 1870 1871 cons = RING_CMP(raw_cons); 1872 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]; 1873 1874 if (!TX_CMP_VALID(txcmp, raw_cons)) 1875 break; 1876 1877 /* The valid test of the entry must be done first before 1878 * reading any further. 1879 */ 1880 dma_rmb(); 1881 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_TX_L2_CMP) { 1882 tx_pkts++; 1883 /* return full budget so NAPI will complete. */ 1884 if (unlikely(tx_pkts > bp->tx_wake_thresh)) 1885 rx_pkts = budget; 1886 } else if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) { 1887 if (likely(budget)) 1888 rc = bnxt_rx_pkt(bp, bnapi, &raw_cons, &event); 1889 else 1890 rc = bnxt_force_rx_discard(bp, bnapi, &raw_cons, 1891 &event); 1892 if (likely(rc >= 0)) 1893 rx_pkts += rc; 1894 /* Increment rx_pkts when rc is -ENOMEM to count towards 1895 * the NAPI budget. Otherwise, we may potentially loop 1896 * here forever if we consistently cannot allocate 1897 * buffers. 1898 */ 1899 else if (rc == -ENOMEM && budget) 1900 rx_pkts++; 1901 else if (rc == -EBUSY) /* partial completion */ 1902 break; 1903 } else if (unlikely((TX_CMP_TYPE(txcmp) == 1904 CMPL_BASE_TYPE_HWRM_DONE) || 1905 (TX_CMP_TYPE(txcmp) == 1906 CMPL_BASE_TYPE_HWRM_FWD_REQ) || 1907 (TX_CMP_TYPE(txcmp) == 1908 CMPL_BASE_TYPE_HWRM_ASYNC_EVENT))) { 1909 bnxt_hwrm_handler(bp, txcmp); 1910 } 1911 raw_cons = NEXT_RAW_CMP(raw_cons); 1912 1913 if (rx_pkts == budget) 1914 break; 1915 } 1916 1917 if (event & BNXT_TX_EVENT) { 1918 struct bnxt_tx_ring_info *txr = bnapi->tx_ring; 1919 void __iomem *db = txr->tx_doorbell; 1920 u16 prod = txr->tx_prod; 1921 1922 /* Sync BD data before updating doorbell */ 1923 wmb(); 1924 1925 bnxt_db_write(bp, db, DB_KEY_TX | prod); 1926 } 1927 1928 cpr->cp_raw_cons = raw_cons; 1929 /* ACK completion ring before freeing tx ring and producing new 1930 * buffers in rx/agg rings to prevent overflowing the completion 1931 * ring. 1932 */ 1933 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons); 1934 1935 if (tx_pkts) 1936 bnapi->tx_int(bp, bnapi, tx_pkts); 1937 1938 if (event & BNXT_RX_EVENT) { 1939 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 1940 1941 bnxt_db_write(bp, rxr->rx_doorbell, DB_KEY_RX | rxr->rx_prod); 1942 if (event & BNXT_AGG_EVENT) 1943 bnxt_db_write(bp, rxr->rx_agg_doorbell, 1944 DB_KEY_RX | rxr->rx_agg_prod); 1945 } 1946 return rx_pkts; 1947 } 1948 1949 static int bnxt_poll_nitroa0(struct napi_struct *napi, int budget) 1950 { 1951 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi); 1952 struct bnxt *bp = bnapi->bp; 1953 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 1954 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 1955 struct tx_cmp *txcmp; 1956 struct rx_cmp_ext *rxcmp1; 1957 u32 cp_cons, tmp_raw_cons; 1958 u32 raw_cons = cpr->cp_raw_cons; 1959 u32 rx_pkts = 0; 1960 u8 event = 0; 1961 1962 while (1) { 1963 int rc; 1964 1965 cp_cons = RING_CMP(raw_cons); 1966 txcmp = &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 1967 1968 if (!TX_CMP_VALID(txcmp, raw_cons)) 1969 break; 1970 1971 if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) { 1972 tmp_raw_cons = NEXT_RAW_CMP(raw_cons); 1973 cp_cons = RING_CMP(tmp_raw_cons); 1974 rxcmp1 = (struct rx_cmp_ext *) 1975 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 1976 1977 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons)) 1978 break; 1979 1980 /* force an error to recycle the buffer */ 1981 rxcmp1->rx_cmp_cfa_code_errors_v2 |= 1982 cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR); 1983 1984 rc = bnxt_rx_pkt(bp, bnapi, &raw_cons, &event); 1985 if (likely(rc == -EIO) && budget) 1986 rx_pkts++; 1987 else if (rc == -EBUSY) /* partial completion */ 1988 break; 1989 } else if (unlikely(TX_CMP_TYPE(txcmp) == 1990 CMPL_BASE_TYPE_HWRM_DONE)) { 1991 bnxt_hwrm_handler(bp, txcmp); 1992 } else { 1993 netdev_err(bp->dev, 1994 "Invalid completion received on special ring\n"); 1995 } 1996 raw_cons = NEXT_RAW_CMP(raw_cons); 1997 1998 if (rx_pkts == budget) 1999 break; 2000 } 2001 2002 cpr->cp_raw_cons = raw_cons; 2003 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons); 2004 bnxt_db_write(bp, rxr->rx_doorbell, DB_KEY_RX | rxr->rx_prod); 2005 2006 if (event & BNXT_AGG_EVENT) 2007 bnxt_db_write(bp, rxr->rx_agg_doorbell, 2008 DB_KEY_RX | rxr->rx_agg_prod); 2009 2010 if (!bnxt_has_work(bp, cpr) && rx_pkts < budget) { 2011 napi_complete_done(napi, rx_pkts); 2012 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons); 2013 } 2014 return rx_pkts; 2015 } 2016 2017 static int bnxt_poll(struct napi_struct *napi, int budget) 2018 { 2019 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi); 2020 struct bnxt *bp = bnapi->bp; 2021 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 2022 int work_done = 0; 2023 2024 while (1) { 2025 work_done += bnxt_poll_work(bp, bnapi, budget - work_done); 2026 2027 if (work_done >= budget) 2028 break; 2029 2030 if (!bnxt_has_work(bp, cpr)) { 2031 if (napi_complete_done(napi, work_done)) 2032 BNXT_CP_DB_REARM(cpr->cp_doorbell, 2033 cpr->cp_raw_cons); 2034 break; 2035 } 2036 } 2037 if (bp->flags & BNXT_FLAG_DIM) { 2038 struct net_dim_sample dim_sample; 2039 2040 net_dim_sample(cpr->event_ctr, 2041 cpr->rx_packets, 2042 cpr->rx_bytes, 2043 &dim_sample); 2044 net_dim(&cpr->dim, dim_sample); 2045 } 2046 mmiowb(); 2047 return work_done; 2048 } 2049 2050 static void bnxt_free_tx_skbs(struct bnxt *bp) 2051 { 2052 int i, max_idx; 2053 struct pci_dev *pdev = bp->pdev; 2054 2055 if (!bp->tx_ring) 2056 return; 2057 2058 max_idx = bp->tx_nr_pages * TX_DESC_CNT; 2059 for (i = 0; i < bp->tx_nr_rings; i++) { 2060 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; 2061 int j; 2062 2063 for (j = 0; j < max_idx;) { 2064 struct bnxt_sw_tx_bd *tx_buf = &txr->tx_buf_ring[j]; 2065 struct sk_buff *skb = tx_buf->skb; 2066 int k, last; 2067 2068 if (!skb) { 2069 j++; 2070 continue; 2071 } 2072 2073 tx_buf->skb = NULL; 2074 2075 if (tx_buf->is_push) { 2076 dev_kfree_skb(skb); 2077 j += 2; 2078 continue; 2079 } 2080 2081 dma_unmap_single(&pdev->dev, 2082 dma_unmap_addr(tx_buf, mapping), 2083 skb_headlen(skb), 2084 PCI_DMA_TODEVICE); 2085 2086 last = tx_buf->nr_frags; 2087 j += 2; 2088 for (k = 0; k < last; k++, j++) { 2089 int ring_idx = j & bp->tx_ring_mask; 2090 skb_frag_t *frag = &skb_shinfo(skb)->frags[k]; 2091 2092 tx_buf = &txr->tx_buf_ring[ring_idx]; 2093 dma_unmap_page( 2094 &pdev->dev, 2095 dma_unmap_addr(tx_buf, mapping), 2096 skb_frag_size(frag), PCI_DMA_TODEVICE); 2097 } 2098 dev_kfree_skb(skb); 2099 } 2100 netdev_tx_reset_queue(netdev_get_tx_queue(bp->dev, i)); 2101 } 2102 } 2103 2104 static void bnxt_free_rx_skbs(struct bnxt *bp) 2105 { 2106 int i, max_idx, max_agg_idx; 2107 struct pci_dev *pdev = bp->pdev; 2108 2109 if (!bp->rx_ring) 2110 return; 2111 2112 max_idx = bp->rx_nr_pages * RX_DESC_CNT; 2113 max_agg_idx = bp->rx_agg_nr_pages * RX_DESC_CNT; 2114 for (i = 0; i < bp->rx_nr_rings; i++) { 2115 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 2116 int j; 2117 2118 if (rxr->rx_tpa) { 2119 for (j = 0; j < MAX_TPA; j++) { 2120 struct bnxt_tpa_info *tpa_info = 2121 &rxr->rx_tpa[j]; 2122 u8 *data = tpa_info->data; 2123 2124 if (!data) 2125 continue; 2126 2127 dma_unmap_single_attrs(&pdev->dev, 2128 tpa_info->mapping, 2129 bp->rx_buf_use_size, 2130 bp->rx_dir, 2131 DMA_ATTR_WEAK_ORDERING); 2132 2133 tpa_info->data = NULL; 2134 2135 kfree(data); 2136 } 2137 } 2138 2139 for (j = 0; j < max_idx; j++) { 2140 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[j]; 2141 dma_addr_t mapping = rx_buf->mapping; 2142 void *data = rx_buf->data; 2143 2144 if (!data) 2145 continue; 2146 2147 rx_buf->data = NULL; 2148 2149 if (BNXT_RX_PAGE_MODE(bp)) { 2150 mapping -= bp->rx_dma_offset; 2151 dma_unmap_page_attrs(&pdev->dev, mapping, 2152 PAGE_SIZE, bp->rx_dir, 2153 DMA_ATTR_WEAK_ORDERING); 2154 __free_page(data); 2155 } else { 2156 dma_unmap_single_attrs(&pdev->dev, mapping, 2157 bp->rx_buf_use_size, 2158 bp->rx_dir, 2159 DMA_ATTR_WEAK_ORDERING); 2160 kfree(data); 2161 } 2162 } 2163 2164 for (j = 0; j < max_agg_idx; j++) { 2165 struct bnxt_sw_rx_agg_bd *rx_agg_buf = 2166 &rxr->rx_agg_ring[j]; 2167 struct page *page = rx_agg_buf->page; 2168 2169 if (!page) 2170 continue; 2171 2172 dma_unmap_page_attrs(&pdev->dev, rx_agg_buf->mapping, 2173 BNXT_RX_PAGE_SIZE, 2174 PCI_DMA_FROMDEVICE, 2175 DMA_ATTR_WEAK_ORDERING); 2176 2177 rx_agg_buf->page = NULL; 2178 __clear_bit(j, rxr->rx_agg_bmap); 2179 2180 __free_page(page); 2181 } 2182 if (rxr->rx_page) { 2183 __free_page(rxr->rx_page); 2184 rxr->rx_page = NULL; 2185 } 2186 } 2187 } 2188 2189 static void bnxt_free_skbs(struct bnxt *bp) 2190 { 2191 bnxt_free_tx_skbs(bp); 2192 bnxt_free_rx_skbs(bp); 2193 } 2194 2195 static void bnxt_free_ring(struct bnxt *bp, struct bnxt_ring_struct *ring) 2196 { 2197 struct pci_dev *pdev = bp->pdev; 2198 int i; 2199 2200 for (i = 0; i < ring->nr_pages; i++) { 2201 if (!ring->pg_arr[i]) 2202 continue; 2203 2204 dma_free_coherent(&pdev->dev, ring->page_size, 2205 ring->pg_arr[i], ring->dma_arr[i]); 2206 2207 ring->pg_arr[i] = NULL; 2208 } 2209 if (ring->pg_tbl) { 2210 dma_free_coherent(&pdev->dev, ring->nr_pages * 8, 2211 ring->pg_tbl, ring->pg_tbl_map); 2212 ring->pg_tbl = NULL; 2213 } 2214 if (ring->vmem_size && *ring->vmem) { 2215 vfree(*ring->vmem); 2216 *ring->vmem = NULL; 2217 } 2218 } 2219 2220 static int bnxt_alloc_ring(struct bnxt *bp, struct bnxt_ring_struct *ring) 2221 { 2222 int i; 2223 struct pci_dev *pdev = bp->pdev; 2224 2225 if (ring->nr_pages > 1) { 2226 ring->pg_tbl = dma_alloc_coherent(&pdev->dev, 2227 ring->nr_pages * 8, 2228 &ring->pg_tbl_map, 2229 GFP_KERNEL); 2230 if (!ring->pg_tbl) 2231 return -ENOMEM; 2232 } 2233 2234 for (i = 0; i < ring->nr_pages; i++) { 2235 ring->pg_arr[i] = dma_alloc_coherent(&pdev->dev, 2236 ring->page_size, 2237 &ring->dma_arr[i], 2238 GFP_KERNEL); 2239 if (!ring->pg_arr[i]) 2240 return -ENOMEM; 2241 2242 if (ring->nr_pages > 1) 2243 ring->pg_tbl[i] = cpu_to_le64(ring->dma_arr[i]); 2244 } 2245 2246 if (ring->vmem_size) { 2247 *ring->vmem = vzalloc(ring->vmem_size); 2248 if (!(*ring->vmem)) 2249 return -ENOMEM; 2250 } 2251 return 0; 2252 } 2253 2254 static void bnxt_free_rx_rings(struct bnxt *bp) 2255 { 2256 int i; 2257 2258 if (!bp->rx_ring) 2259 return; 2260 2261 for (i = 0; i < bp->rx_nr_rings; i++) { 2262 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 2263 struct bnxt_ring_struct *ring; 2264 2265 if (rxr->xdp_prog) 2266 bpf_prog_put(rxr->xdp_prog); 2267 2268 if (xdp_rxq_info_is_reg(&rxr->xdp_rxq)) 2269 xdp_rxq_info_unreg(&rxr->xdp_rxq); 2270 2271 kfree(rxr->rx_tpa); 2272 rxr->rx_tpa = NULL; 2273 2274 kfree(rxr->rx_agg_bmap); 2275 rxr->rx_agg_bmap = NULL; 2276 2277 ring = &rxr->rx_ring_struct; 2278 bnxt_free_ring(bp, ring); 2279 2280 ring = &rxr->rx_agg_ring_struct; 2281 bnxt_free_ring(bp, ring); 2282 } 2283 } 2284 2285 static int bnxt_alloc_rx_rings(struct bnxt *bp) 2286 { 2287 int i, rc, agg_rings = 0, tpa_rings = 0; 2288 2289 if (!bp->rx_ring) 2290 return -ENOMEM; 2291 2292 if (bp->flags & BNXT_FLAG_AGG_RINGS) 2293 agg_rings = 1; 2294 2295 if (bp->flags & BNXT_FLAG_TPA) 2296 tpa_rings = 1; 2297 2298 for (i = 0; i < bp->rx_nr_rings; i++) { 2299 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 2300 struct bnxt_ring_struct *ring; 2301 2302 ring = &rxr->rx_ring_struct; 2303 2304 rc = xdp_rxq_info_reg(&rxr->xdp_rxq, bp->dev, i); 2305 if (rc < 0) 2306 return rc; 2307 2308 rc = bnxt_alloc_ring(bp, ring); 2309 if (rc) 2310 return rc; 2311 2312 if (agg_rings) { 2313 u16 mem_size; 2314 2315 ring = &rxr->rx_agg_ring_struct; 2316 rc = bnxt_alloc_ring(bp, ring); 2317 if (rc) 2318 return rc; 2319 2320 rxr->rx_agg_bmap_size = bp->rx_agg_ring_mask + 1; 2321 mem_size = rxr->rx_agg_bmap_size / 8; 2322 rxr->rx_agg_bmap = kzalloc(mem_size, GFP_KERNEL); 2323 if (!rxr->rx_agg_bmap) 2324 return -ENOMEM; 2325 2326 if (tpa_rings) { 2327 rxr->rx_tpa = kcalloc(MAX_TPA, 2328 sizeof(struct bnxt_tpa_info), 2329 GFP_KERNEL); 2330 if (!rxr->rx_tpa) 2331 return -ENOMEM; 2332 } 2333 } 2334 } 2335 return 0; 2336 } 2337 2338 static void bnxt_free_tx_rings(struct bnxt *bp) 2339 { 2340 int i; 2341 struct pci_dev *pdev = bp->pdev; 2342 2343 if (!bp->tx_ring) 2344 return; 2345 2346 for (i = 0; i < bp->tx_nr_rings; i++) { 2347 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; 2348 struct bnxt_ring_struct *ring; 2349 2350 if (txr->tx_push) { 2351 dma_free_coherent(&pdev->dev, bp->tx_push_size, 2352 txr->tx_push, txr->tx_push_mapping); 2353 txr->tx_push = NULL; 2354 } 2355 2356 ring = &txr->tx_ring_struct; 2357 2358 bnxt_free_ring(bp, ring); 2359 } 2360 } 2361 2362 static int bnxt_alloc_tx_rings(struct bnxt *bp) 2363 { 2364 int i, j, rc; 2365 struct pci_dev *pdev = bp->pdev; 2366 2367 bp->tx_push_size = 0; 2368 if (bp->tx_push_thresh) { 2369 int push_size; 2370 2371 push_size = L1_CACHE_ALIGN(sizeof(struct tx_push_bd) + 2372 bp->tx_push_thresh); 2373 2374 if (push_size > 256) { 2375 push_size = 0; 2376 bp->tx_push_thresh = 0; 2377 } 2378 2379 bp->tx_push_size = push_size; 2380 } 2381 2382 for (i = 0, j = 0; i < bp->tx_nr_rings; i++) { 2383 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; 2384 struct bnxt_ring_struct *ring; 2385 2386 ring = &txr->tx_ring_struct; 2387 2388 rc = bnxt_alloc_ring(bp, ring); 2389 if (rc) 2390 return rc; 2391 2392 if (bp->tx_push_size) { 2393 dma_addr_t mapping; 2394 2395 /* One pre-allocated DMA buffer to backup 2396 * TX push operation 2397 */ 2398 txr->tx_push = dma_alloc_coherent(&pdev->dev, 2399 bp->tx_push_size, 2400 &txr->tx_push_mapping, 2401 GFP_KERNEL); 2402 2403 if (!txr->tx_push) 2404 return -ENOMEM; 2405 2406 mapping = txr->tx_push_mapping + 2407 sizeof(struct tx_push_bd); 2408 txr->data_mapping = cpu_to_le64(mapping); 2409 2410 memset(txr->tx_push, 0, sizeof(struct tx_push_bd)); 2411 } 2412 ring->queue_id = bp->q_info[j].queue_id; 2413 if (i < bp->tx_nr_rings_xdp) 2414 continue; 2415 if (i % bp->tx_nr_rings_per_tc == (bp->tx_nr_rings_per_tc - 1)) 2416 j++; 2417 } 2418 return 0; 2419 } 2420 2421 static void bnxt_free_cp_rings(struct bnxt *bp) 2422 { 2423 int i; 2424 2425 if (!bp->bnapi) 2426 return; 2427 2428 for (i = 0; i < bp->cp_nr_rings; i++) { 2429 struct bnxt_napi *bnapi = bp->bnapi[i]; 2430 struct bnxt_cp_ring_info *cpr; 2431 struct bnxt_ring_struct *ring; 2432 2433 if (!bnapi) 2434 continue; 2435 2436 cpr = &bnapi->cp_ring; 2437 ring = &cpr->cp_ring_struct; 2438 2439 bnxt_free_ring(bp, ring); 2440 } 2441 } 2442 2443 static int bnxt_alloc_cp_rings(struct bnxt *bp) 2444 { 2445 int i, rc; 2446 2447 for (i = 0; i < bp->cp_nr_rings; i++) { 2448 struct bnxt_napi *bnapi = bp->bnapi[i]; 2449 struct bnxt_cp_ring_info *cpr; 2450 struct bnxt_ring_struct *ring; 2451 2452 if (!bnapi) 2453 continue; 2454 2455 cpr = &bnapi->cp_ring; 2456 ring = &cpr->cp_ring_struct; 2457 2458 rc = bnxt_alloc_ring(bp, ring); 2459 if (rc) 2460 return rc; 2461 } 2462 return 0; 2463 } 2464 2465 static void bnxt_init_ring_struct(struct bnxt *bp) 2466 { 2467 int i; 2468 2469 for (i = 0; i < bp->cp_nr_rings; i++) { 2470 struct bnxt_napi *bnapi = bp->bnapi[i]; 2471 struct bnxt_cp_ring_info *cpr; 2472 struct bnxt_rx_ring_info *rxr; 2473 struct bnxt_tx_ring_info *txr; 2474 struct bnxt_ring_struct *ring; 2475 2476 if (!bnapi) 2477 continue; 2478 2479 cpr = &bnapi->cp_ring; 2480 ring = &cpr->cp_ring_struct; 2481 ring->nr_pages = bp->cp_nr_pages; 2482 ring->page_size = HW_CMPD_RING_SIZE; 2483 ring->pg_arr = (void **)cpr->cp_desc_ring; 2484 ring->dma_arr = cpr->cp_desc_mapping; 2485 ring->vmem_size = 0; 2486 2487 rxr = bnapi->rx_ring; 2488 if (!rxr) 2489 goto skip_rx; 2490 2491 ring = &rxr->rx_ring_struct; 2492 ring->nr_pages = bp->rx_nr_pages; 2493 ring->page_size = HW_RXBD_RING_SIZE; 2494 ring->pg_arr = (void **)rxr->rx_desc_ring; 2495 ring->dma_arr = rxr->rx_desc_mapping; 2496 ring->vmem_size = SW_RXBD_RING_SIZE * bp->rx_nr_pages; 2497 ring->vmem = (void **)&rxr->rx_buf_ring; 2498 2499 ring = &rxr->rx_agg_ring_struct; 2500 ring->nr_pages = bp->rx_agg_nr_pages; 2501 ring->page_size = HW_RXBD_RING_SIZE; 2502 ring->pg_arr = (void **)rxr->rx_agg_desc_ring; 2503 ring->dma_arr = rxr->rx_agg_desc_mapping; 2504 ring->vmem_size = SW_RXBD_AGG_RING_SIZE * bp->rx_agg_nr_pages; 2505 ring->vmem = (void **)&rxr->rx_agg_ring; 2506 2507 skip_rx: 2508 txr = bnapi->tx_ring; 2509 if (!txr) 2510 continue; 2511 2512 ring = &txr->tx_ring_struct; 2513 ring->nr_pages = bp->tx_nr_pages; 2514 ring->page_size = HW_RXBD_RING_SIZE; 2515 ring->pg_arr = (void **)txr->tx_desc_ring; 2516 ring->dma_arr = txr->tx_desc_mapping; 2517 ring->vmem_size = SW_TXBD_RING_SIZE * bp->tx_nr_pages; 2518 ring->vmem = (void **)&txr->tx_buf_ring; 2519 } 2520 } 2521 2522 static void bnxt_init_rxbd_pages(struct bnxt_ring_struct *ring, u32 type) 2523 { 2524 int i; 2525 u32 prod; 2526 struct rx_bd **rx_buf_ring; 2527 2528 rx_buf_ring = (struct rx_bd **)ring->pg_arr; 2529 for (i = 0, prod = 0; i < ring->nr_pages; i++) { 2530 int j; 2531 struct rx_bd *rxbd; 2532 2533 rxbd = rx_buf_ring[i]; 2534 if (!rxbd) 2535 continue; 2536 2537 for (j = 0; j < RX_DESC_CNT; j++, rxbd++, prod++) { 2538 rxbd->rx_bd_len_flags_type = cpu_to_le32(type); 2539 rxbd->rx_bd_opaque = prod; 2540 } 2541 } 2542 } 2543 2544 static int bnxt_init_one_rx_ring(struct bnxt *bp, int ring_nr) 2545 { 2546 struct net_device *dev = bp->dev; 2547 struct bnxt_rx_ring_info *rxr; 2548 struct bnxt_ring_struct *ring; 2549 u32 prod, type; 2550 int i; 2551 2552 type = (bp->rx_buf_use_size << RX_BD_LEN_SHIFT) | 2553 RX_BD_TYPE_RX_PACKET_BD | RX_BD_FLAGS_EOP; 2554 2555 if (NET_IP_ALIGN == 2) 2556 type |= RX_BD_FLAGS_SOP; 2557 2558 rxr = &bp->rx_ring[ring_nr]; 2559 ring = &rxr->rx_ring_struct; 2560 bnxt_init_rxbd_pages(ring, type); 2561 2562 if (BNXT_RX_PAGE_MODE(bp) && bp->xdp_prog) { 2563 rxr->xdp_prog = bpf_prog_add(bp->xdp_prog, 1); 2564 if (IS_ERR(rxr->xdp_prog)) { 2565 int rc = PTR_ERR(rxr->xdp_prog); 2566 2567 rxr->xdp_prog = NULL; 2568 return rc; 2569 } 2570 } 2571 prod = rxr->rx_prod; 2572 for (i = 0; i < bp->rx_ring_size; i++) { 2573 if (bnxt_alloc_rx_data(bp, rxr, prod, GFP_KERNEL) != 0) { 2574 netdev_warn(dev, "init'ed rx ring %d with %d/%d skbs only\n", 2575 ring_nr, i, bp->rx_ring_size); 2576 break; 2577 } 2578 prod = NEXT_RX(prod); 2579 } 2580 rxr->rx_prod = prod; 2581 ring->fw_ring_id = INVALID_HW_RING_ID; 2582 2583 ring = &rxr->rx_agg_ring_struct; 2584 ring->fw_ring_id = INVALID_HW_RING_ID; 2585 2586 if (!(bp->flags & BNXT_FLAG_AGG_RINGS)) 2587 return 0; 2588 2589 type = ((u32)BNXT_RX_PAGE_SIZE << RX_BD_LEN_SHIFT) | 2590 RX_BD_TYPE_RX_AGG_BD | RX_BD_FLAGS_SOP; 2591 2592 bnxt_init_rxbd_pages(ring, type); 2593 2594 prod = rxr->rx_agg_prod; 2595 for (i = 0; i < bp->rx_agg_ring_size; i++) { 2596 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_KERNEL) != 0) { 2597 netdev_warn(dev, "init'ed rx ring %d with %d/%d pages only\n", 2598 ring_nr, i, bp->rx_ring_size); 2599 break; 2600 } 2601 prod = NEXT_RX_AGG(prod); 2602 } 2603 rxr->rx_agg_prod = prod; 2604 2605 if (bp->flags & BNXT_FLAG_TPA) { 2606 if (rxr->rx_tpa) { 2607 u8 *data; 2608 dma_addr_t mapping; 2609 2610 for (i = 0; i < MAX_TPA; i++) { 2611 data = __bnxt_alloc_rx_data(bp, &mapping, 2612 GFP_KERNEL); 2613 if (!data) 2614 return -ENOMEM; 2615 2616 rxr->rx_tpa[i].data = data; 2617 rxr->rx_tpa[i].data_ptr = data + bp->rx_offset; 2618 rxr->rx_tpa[i].mapping = mapping; 2619 } 2620 } else { 2621 netdev_err(bp->dev, "No resource allocated for LRO/GRO\n"); 2622 return -ENOMEM; 2623 } 2624 } 2625 2626 return 0; 2627 } 2628 2629 static void bnxt_init_cp_rings(struct bnxt *bp) 2630 { 2631 int i; 2632 2633 for (i = 0; i < bp->cp_nr_rings; i++) { 2634 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring; 2635 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct; 2636 2637 ring->fw_ring_id = INVALID_HW_RING_ID; 2638 cpr->rx_ring_coal.coal_ticks = bp->rx_coal.coal_ticks; 2639 cpr->rx_ring_coal.coal_bufs = bp->rx_coal.coal_bufs; 2640 } 2641 } 2642 2643 static int bnxt_init_rx_rings(struct bnxt *bp) 2644 { 2645 int i, rc = 0; 2646 2647 if (BNXT_RX_PAGE_MODE(bp)) { 2648 bp->rx_offset = NET_IP_ALIGN + XDP_PACKET_HEADROOM; 2649 bp->rx_dma_offset = XDP_PACKET_HEADROOM; 2650 } else { 2651 bp->rx_offset = BNXT_RX_OFFSET; 2652 bp->rx_dma_offset = BNXT_RX_DMA_OFFSET; 2653 } 2654 2655 for (i = 0; i < bp->rx_nr_rings; i++) { 2656 rc = bnxt_init_one_rx_ring(bp, i); 2657 if (rc) 2658 break; 2659 } 2660 2661 return rc; 2662 } 2663 2664 static int bnxt_init_tx_rings(struct bnxt *bp) 2665 { 2666 u16 i; 2667 2668 bp->tx_wake_thresh = max_t(int, bp->tx_ring_size / 2, 2669 MAX_SKB_FRAGS + 1); 2670 2671 for (i = 0; i < bp->tx_nr_rings; i++) { 2672 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; 2673 struct bnxt_ring_struct *ring = &txr->tx_ring_struct; 2674 2675 ring->fw_ring_id = INVALID_HW_RING_ID; 2676 } 2677 2678 return 0; 2679 } 2680 2681 static void bnxt_free_ring_grps(struct bnxt *bp) 2682 { 2683 kfree(bp->grp_info); 2684 bp->grp_info = NULL; 2685 } 2686 2687 static int bnxt_init_ring_grps(struct bnxt *bp, bool irq_re_init) 2688 { 2689 int i; 2690 2691 if (irq_re_init) { 2692 bp->grp_info = kcalloc(bp->cp_nr_rings, 2693 sizeof(struct bnxt_ring_grp_info), 2694 GFP_KERNEL); 2695 if (!bp->grp_info) 2696 return -ENOMEM; 2697 } 2698 for (i = 0; i < bp->cp_nr_rings; i++) { 2699 if (irq_re_init) 2700 bp->grp_info[i].fw_stats_ctx = INVALID_HW_RING_ID; 2701 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID; 2702 bp->grp_info[i].rx_fw_ring_id = INVALID_HW_RING_ID; 2703 bp->grp_info[i].agg_fw_ring_id = INVALID_HW_RING_ID; 2704 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID; 2705 } 2706 return 0; 2707 } 2708 2709 static void bnxt_free_vnics(struct bnxt *bp) 2710 { 2711 kfree(bp->vnic_info); 2712 bp->vnic_info = NULL; 2713 bp->nr_vnics = 0; 2714 } 2715 2716 static int bnxt_alloc_vnics(struct bnxt *bp) 2717 { 2718 int num_vnics = 1; 2719 2720 #ifdef CONFIG_RFS_ACCEL 2721 if (bp->flags & BNXT_FLAG_RFS) 2722 num_vnics += bp->rx_nr_rings; 2723 #endif 2724 2725 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 2726 num_vnics++; 2727 2728 bp->vnic_info = kcalloc(num_vnics, sizeof(struct bnxt_vnic_info), 2729 GFP_KERNEL); 2730 if (!bp->vnic_info) 2731 return -ENOMEM; 2732 2733 bp->nr_vnics = num_vnics; 2734 return 0; 2735 } 2736 2737 static void bnxt_init_vnics(struct bnxt *bp) 2738 { 2739 int i; 2740 2741 for (i = 0; i < bp->nr_vnics; i++) { 2742 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 2743 2744 vnic->fw_vnic_id = INVALID_HW_RING_ID; 2745 vnic->fw_rss_cos_lb_ctx[0] = INVALID_HW_RING_ID; 2746 vnic->fw_rss_cos_lb_ctx[1] = INVALID_HW_RING_ID; 2747 vnic->fw_l2_ctx_id = INVALID_HW_RING_ID; 2748 2749 if (bp->vnic_info[i].rss_hash_key) { 2750 if (i == 0) 2751 prandom_bytes(vnic->rss_hash_key, 2752 HW_HASH_KEY_SIZE); 2753 else 2754 memcpy(vnic->rss_hash_key, 2755 bp->vnic_info[0].rss_hash_key, 2756 HW_HASH_KEY_SIZE); 2757 } 2758 } 2759 } 2760 2761 static int bnxt_calc_nr_ring_pages(u32 ring_size, int desc_per_pg) 2762 { 2763 int pages; 2764 2765 pages = ring_size / desc_per_pg; 2766 2767 if (!pages) 2768 return 1; 2769 2770 pages++; 2771 2772 while (pages & (pages - 1)) 2773 pages++; 2774 2775 return pages; 2776 } 2777 2778 void bnxt_set_tpa_flags(struct bnxt *bp) 2779 { 2780 bp->flags &= ~BNXT_FLAG_TPA; 2781 if (bp->flags & BNXT_FLAG_NO_AGG_RINGS) 2782 return; 2783 if (bp->dev->features & NETIF_F_LRO) 2784 bp->flags |= BNXT_FLAG_LRO; 2785 else if (bp->dev->features & NETIF_F_GRO_HW) 2786 bp->flags |= BNXT_FLAG_GRO; 2787 } 2788 2789 /* bp->rx_ring_size, bp->tx_ring_size, dev->mtu, BNXT_FLAG_{G|L}RO flags must 2790 * be set on entry. 2791 */ 2792 void bnxt_set_ring_params(struct bnxt *bp) 2793 { 2794 u32 ring_size, rx_size, rx_space; 2795 u32 agg_factor = 0, agg_ring_size = 0; 2796 2797 /* 8 for CRC and VLAN */ 2798 rx_size = SKB_DATA_ALIGN(bp->dev->mtu + ETH_HLEN + NET_IP_ALIGN + 8); 2799 2800 rx_space = rx_size + NET_SKB_PAD + 2801 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 2802 2803 bp->rx_copy_thresh = BNXT_RX_COPY_THRESH; 2804 ring_size = bp->rx_ring_size; 2805 bp->rx_agg_ring_size = 0; 2806 bp->rx_agg_nr_pages = 0; 2807 2808 if (bp->flags & BNXT_FLAG_TPA) 2809 agg_factor = min_t(u32, 4, 65536 / BNXT_RX_PAGE_SIZE); 2810 2811 bp->flags &= ~BNXT_FLAG_JUMBO; 2812 if (rx_space > PAGE_SIZE && !(bp->flags & BNXT_FLAG_NO_AGG_RINGS)) { 2813 u32 jumbo_factor; 2814 2815 bp->flags |= BNXT_FLAG_JUMBO; 2816 jumbo_factor = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT; 2817 if (jumbo_factor > agg_factor) 2818 agg_factor = jumbo_factor; 2819 } 2820 agg_ring_size = ring_size * agg_factor; 2821 2822 if (agg_ring_size) { 2823 bp->rx_agg_nr_pages = bnxt_calc_nr_ring_pages(agg_ring_size, 2824 RX_DESC_CNT); 2825 if (bp->rx_agg_nr_pages > MAX_RX_AGG_PAGES) { 2826 u32 tmp = agg_ring_size; 2827 2828 bp->rx_agg_nr_pages = MAX_RX_AGG_PAGES; 2829 agg_ring_size = MAX_RX_AGG_PAGES * RX_DESC_CNT - 1; 2830 netdev_warn(bp->dev, "rx agg ring size %d reduced to %d.\n", 2831 tmp, agg_ring_size); 2832 } 2833 bp->rx_agg_ring_size = agg_ring_size; 2834 bp->rx_agg_ring_mask = (bp->rx_agg_nr_pages * RX_DESC_CNT) - 1; 2835 rx_size = SKB_DATA_ALIGN(BNXT_RX_COPY_THRESH + NET_IP_ALIGN); 2836 rx_space = rx_size + NET_SKB_PAD + 2837 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 2838 } 2839 2840 bp->rx_buf_use_size = rx_size; 2841 bp->rx_buf_size = rx_space; 2842 2843 bp->rx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, RX_DESC_CNT); 2844 bp->rx_ring_mask = (bp->rx_nr_pages * RX_DESC_CNT) - 1; 2845 2846 ring_size = bp->tx_ring_size; 2847 bp->tx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, TX_DESC_CNT); 2848 bp->tx_ring_mask = (bp->tx_nr_pages * TX_DESC_CNT) - 1; 2849 2850 ring_size = bp->rx_ring_size * (2 + agg_factor) + bp->tx_ring_size; 2851 bp->cp_ring_size = ring_size; 2852 2853 bp->cp_nr_pages = bnxt_calc_nr_ring_pages(ring_size, CP_DESC_CNT); 2854 if (bp->cp_nr_pages > MAX_CP_PAGES) { 2855 bp->cp_nr_pages = MAX_CP_PAGES; 2856 bp->cp_ring_size = MAX_CP_PAGES * CP_DESC_CNT - 1; 2857 netdev_warn(bp->dev, "completion ring size %d reduced to %d.\n", 2858 ring_size, bp->cp_ring_size); 2859 } 2860 bp->cp_bit = bp->cp_nr_pages * CP_DESC_CNT; 2861 bp->cp_ring_mask = bp->cp_bit - 1; 2862 } 2863 2864 /* Changing allocation mode of RX rings. 2865 * TODO: Update when extending xdp_rxq_info to support allocation modes. 2866 */ 2867 int bnxt_set_rx_skb_mode(struct bnxt *bp, bool page_mode) 2868 { 2869 if (page_mode) { 2870 if (bp->dev->mtu > BNXT_MAX_PAGE_MODE_MTU) 2871 return -EOPNOTSUPP; 2872 bp->dev->max_mtu = 2873 min_t(u16, bp->max_mtu, BNXT_MAX_PAGE_MODE_MTU); 2874 bp->flags &= ~BNXT_FLAG_AGG_RINGS; 2875 bp->flags |= BNXT_FLAG_NO_AGG_RINGS | BNXT_FLAG_RX_PAGE_MODE; 2876 bp->rx_dir = DMA_BIDIRECTIONAL; 2877 bp->rx_skb_func = bnxt_rx_page_skb; 2878 /* Disable LRO or GRO_HW */ 2879 netdev_update_features(bp->dev); 2880 } else { 2881 bp->dev->max_mtu = bp->max_mtu; 2882 bp->flags &= ~BNXT_FLAG_RX_PAGE_MODE; 2883 bp->rx_dir = DMA_FROM_DEVICE; 2884 bp->rx_skb_func = bnxt_rx_skb; 2885 } 2886 return 0; 2887 } 2888 2889 static void bnxt_free_vnic_attributes(struct bnxt *bp) 2890 { 2891 int i; 2892 struct bnxt_vnic_info *vnic; 2893 struct pci_dev *pdev = bp->pdev; 2894 2895 if (!bp->vnic_info) 2896 return; 2897 2898 for (i = 0; i < bp->nr_vnics; i++) { 2899 vnic = &bp->vnic_info[i]; 2900 2901 kfree(vnic->fw_grp_ids); 2902 vnic->fw_grp_ids = NULL; 2903 2904 kfree(vnic->uc_list); 2905 vnic->uc_list = NULL; 2906 2907 if (vnic->mc_list) { 2908 dma_free_coherent(&pdev->dev, vnic->mc_list_size, 2909 vnic->mc_list, vnic->mc_list_mapping); 2910 vnic->mc_list = NULL; 2911 } 2912 2913 if (vnic->rss_table) { 2914 dma_free_coherent(&pdev->dev, PAGE_SIZE, 2915 vnic->rss_table, 2916 vnic->rss_table_dma_addr); 2917 vnic->rss_table = NULL; 2918 } 2919 2920 vnic->rss_hash_key = NULL; 2921 vnic->flags = 0; 2922 } 2923 } 2924 2925 static int bnxt_alloc_vnic_attributes(struct bnxt *bp) 2926 { 2927 int i, rc = 0, size; 2928 struct bnxt_vnic_info *vnic; 2929 struct pci_dev *pdev = bp->pdev; 2930 int max_rings; 2931 2932 for (i = 0; i < bp->nr_vnics; i++) { 2933 vnic = &bp->vnic_info[i]; 2934 2935 if (vnic->flags & BNXT_VNIC_UCAST_FLAG) { 2936 int mem_size = (BNXT_MAX_UC_ADDRS - 1) * ETH_ALEN; 2937 2938 if (mem_size > 0) { 2939 vnic->uc_list = kmalloc(mem_size, GFP_KERNEL); 2940 if (!vnic->uc_list) { 2941 rc = -ENOMEM; 2942 goto out; 2943 } 2944 } 2945 } 2946 2947 if (vnic->flags & BNXT_VNIC_MCAST_FLAG) { 2948 vnic->mc_list_size = BNXT_MAX_MC_ADDRS * ETH_ALEN; 2949 vnic->mc_list = 2950 dma_alloc_coherent(&pdev->dev, 2951 vnic->mc_list_size, 2952 &vnic->mc_list_mapping, 2953 GFP_KERNEL); 2954 if (!vnic->mc_list) { 2955 rc = -ENOMEM; 2956 goto out; 2957 } 2958 } 2959 2960 if (vnic->flags & BNXT_VNIC_RSS_FLAG) 2961 max_rings = bp->rx_nr_rings; 2962 else 2963 max_rings = 1; 2964 2965 vnic->fw_grp_ids = kcalloc(max_rings, sizeof(u16), GFP_KERNEL); 2966 if (!vnic->fw_grp_ids) { 2967 rc = -ENOMEM; 2968 goto out; 2969 } 2970 2971 if ((bp->flags & BNXT_FLAG_NEW_RSS_CAP) && 2972 !(vnic->flags & BNXT_VNIC_RSS_FLAG)) 2973 continue; 2974 2975 /* Allocate rss table and hash key */ 2976 vnic->rss_table = dma_alloc_coherent(&pdev->dev, PAGE_SIZE, 2977 &vnic->rss_table_dma_addr, 2978 GFP_KERNEL); 2979 if (!vnic->rss_table) { 2980 rc = -ENOMEM; 2981 goto out; 2982 } 2983 2984 size = L1_CACHE_ALIGN(HW_HASH_INDEX_SIZE * sizeof(u16)); 2985 2986 vnic->rss_hash_key = ((void *)vnic->rss_table) + size; 2987 vnic->rss_hash_key_dma_addr = vnic->rss_table_dma_addr + size; 2988 } 2989 return 0; 2990 2991 out: 2992 return rc; 2993 } 2994 2995 static void bnxt_free_hwrm_resources(struct bnxt *bp) 2996 { 2997 struct pci_dev *pdev = bp->pdev; 2998 2999 dma_free_coherent(&pdev->dev, PAGE_SIZE, bp->hwrm_cmd_resp_addr, 3000 bp->hwrm_cmd_resp_dma_addr); 3001 3002 bp->hwrm_cmd_resp_addr = NULL; 3003 if (bp->hwrm_dbg_resp_addr) { 3004 dma_free_coherent(&pdev->dev, HWRM_DBG_REG_BUF_SIZE, 3005 bp->hwrm_dbg_resp_addr, 3006 bp->hwrm_dbg_resp_dma_addr); 3007 3008 bp->hwrm_dbg_resp_addr = NULL; 3009 } 3010 } 3011 3012 static int bnxt_alloc_hwrm_resources(struct bnxt *bp) 3013 { 3014 struct pci_dev *pdev = bp->pdev; 3015 3016 bp->hwrm_cmd_resp_addr = dma_alloc_coherent(&pdev->dev, PAGE_SIZE, 3017 &bp->hwrm_cmd_resp_dma_addr, 3018 GFP_KERNEL); 3019 if (!bp->hwrm_cmd_resp_addr) 3020 return -ENOMEM; 3021 bp->hwrm_dbg_resp_addr = dma_alloc_coherent(&pdev->dev, 3022 HWRM_DBG_REG_BUF_SIZE, 3023 &bp->hwrm_dbg_resp_dma_addr, 3024 GFP_KERNEL); 3025 if (!bp->hwrm_dbg_resp_addr) 3026 netdev_warn(bp->dev, "fail to alloc debug register dma mem\n"); 3027 3028 return 0; 3029 } 3030 3031 static void bnxt_free_hwrm_short_cmd_req(struct bnxt *bp) 3032 { 3033 if (bp->hwrm_short_cmd_req_addr) { 3034 struct pci_dev *pdev = bp->pdev; 3035 3036 dma_free_coherent(&pdev->dev, BNXT_HWRM_MAX_REQ_LEN, 3037 bp->hwrm_short_cmd_req_addr, 3038 bp->hwrm_short_cmd_req_dma_addr); 3039 bp->hwrm_short_cmd_req_addr = NULL; 3040 } 3041 } 3042 3043 static int bnxt_alloc_hwrm_short_cmd_req(struct bnxt *bp) 3044 { 3045 struct pci_dev *pdev = bp->pdev; 3046 3047 bp->hwrm_short_cmd_req_addr = 3048 dma_alloc_coherent(&pdev->dev, BNXT_HWRM_MAX_REQ_LEN, 3049 &bp->hwrm_short_cmd_req_dma_addr, 3050 GFP_KERNEL); 3051 if (!bp->hwrm_short_cmd_req_addr) 3052 return -ENOMEM; 3053 3054 return 0; 3055 } 3056 3057 static void bnxt_free_stats(struct bnxt *bp) 3058 { 3059 u32 size, i; 3060 struct pci_dev *pdev = bp->pdev; 3061 3062 if (bp->hw_rx_port_stats) { 3063 dma_free_coherent(&pdev->dev, bp->hw_port_stats_size, 3064 bp->hw_rx_port_stats, 3065 bp->hw_rx_port_stats_map); 3066 bp->hw_rx_port_stats = NULL; 3067 bp->flags &= ~BNXT_FLAG_PORT_STATS; 3068 } 3069 3070 if (!bp->bnapi) 3071 return; 3072 3073 size = sizeof(struct ctx_hw_stats); 3074 3075 for (i = 0; i < bp->cp_nr_rings; i++) { 3076 struct bnxt_napi *bnapi = bp->bnapi[i]; 3077 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 3078 3079 if (cpr->hw_stats) { 3080 dma_free_coherent(&pdev->dev, size, cpr->hw_stats, 3081 cpr->hw_stats_map); 3082 cpr->hw_stats = NULL; 3083 } 3084 } 3085 } 3086 3087 static int bnxt_alloc_stats(struct bnxt *bp) 3088 { 3089 u32 size, i; 3090 struct pci_dev *pdev = bp->pdev; 3091 3092 size = sizeof(struct ctx_hw_stats); 3093 3094 for (i = 0; i < bp->cp_nr_rings; i++) { 3095 struct bnxt_napi *bnapi = bp->bnapi[i]; 3096 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 3097 3098 cpr->hw_stats = dma_alloc_coherent(&pdev->dev, size, 3099 &cpr->hw_stats_map, 3100 GFP_KERNEL); 3101 if (!cpr->hw_stats) 3102 return -ENOMEM; 3103 3104 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID; 3105 } 3106 3107 if (BNXT_PF(bp) && bp->chip_num != CHIP_NUM_58700) { 3108 bp->hw_port_stats_size = sizeof(struct rx_port_stats) + 3109 sizeof(struct tx_port_stats) + 1024; 3110 3111 bp->hw_rx_port_stats = 3112 dma_alloc_coherent(&pdev->dev, bp->hw_port_stats_size, 3113 &bp->hw_rx_port_stats_map, 3114 GFP_KERNEL); 3115 if (!bp->hw_rx_port_stats) 3116 return -ENOMEM; 3117 3118 bp->hw_tx_port_stats = (void *)(bp->hw_rx_port_stats + 1) + 3119 512; 3120 bp->hw_tx_port_stats_map = bp->hw_rx_port_stats_map + 3121 sizeof(struct rx_port_stats) + 512; 3122 bp->flags |= BNXT_FLAG_PORT_STATS; 3123 } 3124 return 0; 3125 } 3126 3127 static void bnxt_clear_ring_indices(struct bnxt *bp) 3128 { 3129 int i; 3130 3131 if (!bp->bnapi) 3132 return; 3133 3134 for (i = 0; i < bp->cp_nr_rings; i++) { 3135 struct bnxt_napi *bnapi = bp->bnapi[i]; 3136 struct bnxt_cp_ring_info *cpr; 3137 struct bnxt_rx_ring_info *rxr; 3138 struct bnxt_tx_ring_info *txr; 3139 3140 if (!bnapi) 3141 continue; 3142 3143 cpr = &bnapi->cp_ring; 3144 cpr->cp_raw_cons = 0; 3145 3146 txr = bnapi->tx_ring; 3147 if (txr) { 3148 txr->tx_prod = 0; 3149 txr->tx_cons = 0; 3150 } 3151 3152 rxr = bnapi->rx_ring; 3153 if (rxr) { 3154 rxr->rx_prod = 0; 3155 rxr->rx_agg_prod = 0; 3156 rxr->rx_sw_agg_prod = 0; 3157 rxr->rx_next_cons = 0; 3158 } 3159 } 3160 } 3161 3162 static void bnxt_free_ntp_fltrs(struct bnxt *bp, bool irq_reinit) 3163 { 3164 #ifdef CONFIG_RFS_ACCEL 3165 int i; 3166 3167 /* Under rtnl_lock and all our NAPIs have been disabled. It's 3168 * safe to delete the hash table. 3169 */ 3170 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) { 3171 struct hlist_head *head; 3172 struct hlist_node *tmp; 3173 struct bnxt_ntuple_filter *fltr; 3174 3175 head = &bp->ntp_fltr_hash_tbl[i]; 3176 hlist_for_each_entry_safe(fltr, tmp, head, hash) { 3177 hlist_del(&fltr->hash); 3178 kfree(fltr); 3179 } 3180 } 3181 if (irq_reinit) { 3182 kfree(bp->ntp_fltr_bmap); 3183 bp->ntp_fltr_bmap = NULL; 3184 } 3185 bp->ntp_fltr_count = 0; 3186 #endif 3187 } 3188 3189 static int bnxt_alloc_ntp_fltrs(struct bnxt *bp) 3190 { 3191 #ifdef CONFIG_RFS_ACCEL 3192 int i, rc = 0; 3193 3194 if (!(bp->flags & BNXT_FLAG_RFS)) 3195 return 0; 3196 3197 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) 3198 INIT_HLIST_HEAD(&bp->ntp_fltr_hash_tbl[i]); 3199 3200 bp->ntp_fltr_count = 0; 3201 bp->ntp_fltr_bmap = kcalloc(BITS_TO_LONGS(BNXT_NTP_FLTR_MAX_FLTR), 3202 sizeof(long), 3203 GFP_KERNEL); 3204 3205 if (!bp->ntp_fltr_bmap) 3206 rc = -ENOMEM; 3207 3208 return rc; 3209 #else 3210 return 0; 3211 #endif 3212 } 3213 3214 static void bnxt_free_mem(struct bnxt *bp, bool irq_re_init) 3215 { 3216 bnxt_free_vnic_attributes(bp); 3217 bnxt_free_tx_rings(bp); 3218 bnxt_free_rx_rings(bp); 3219 bnxt_free_cp_rings(bp); 3220 bnxt_free_ntp_fltrs(bp, irq_re_init); 3221 if (irq_re_init) { 3222 bnxt_free_stats(bp); 3223 bnxt_free_ring_grps(bp); 3224 bnxt_free_vnics(bp); 3225 kfree(bp->tx_ring_map); 3226 bp->tx_ring_map = NULL; 3227 kfree(bp->tx_ring); 3228 bp->tx_ring = NULL; 3229 kfree(bp->rx_ring); 3230 bp->rx_ring = NULL; 3231 kfree(bp->bnapi); 3232 bp->bnapi = NULL; 3233 } else { 3234 bnxt_clear_ring_indices(bp); 3235 } 3236 } 3237 3238 static int bnxt_alloc_mem(struct bnxt *bp, bool irq_re_init) 3239 { 3240 int i, j, rc, size, arr_size; 3241 void *bnapi; 3242 3243 if (irq_re_init) { 3244 /* Allocate bnapi mem pointer array and mem block for 3245 * all queues 3246 */ 3247 arr_size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi *) * 3248 bp->cp_nr_rings); 3249 size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi)); 3250 bnapi = kzalloc(arr_size + size * bp->cp_nr_rings, GFP_KERNEL); 3251 if (!bnapi) 3252 return -ENOMEM; 3253 3254 bp->bnapi = bnapi; 3255 bnapi += arr_size; 3256 for (i = 0; i < bp->cp_nr_rings; i++, bnapi += size) { 3257 bp->bnapi[i] = bnapi; 3258 bp->bnapi[i]->index = i; 3259 bp->bnapi[i]->bp = bp; 3260 } 3261 3262 bp->rx_ring = kcalloc(bp->rx_nr_rings, 3263 sizeof(struct bnxt_rx_ring_info), 3264 GFP_KERNEL); 3265 if (!bp->rx_ring) 3266 return -ENOMEM; 3267 3268 for (i = 0; i < bp->rx_nr_rings; i++) { 3269 bp->rx_ring[i].bnapi = bp->bnapi[i]; 3270 bp->bnapi[i]->rx_ring = &bp->rx_ring[i]; 3271 } 3272 3273 bp->tx_ring = kcalloc(bp->tx_nr_rings, 3274 sizeof(struct bnxt_tx_ring_info), 3275 GFP_KERNEL); 3276 if (!bp->tx_ring) 3277 return -ENOMEM; 3278 3279 bp->tx_ring_map = kcalloc(bp->tx_nr_rings, sizeof(u16), 3280 GFP_KERNEL); 3281 3282 if (!bp->tx_ring_map) 3283 return -ENOMEM; 3284 3285 if (bp->flags & BNXT_FLAG_SHARED_RINGS) 3286 j = 0; 3287 else 3288 j = bp->rx_nr_rings; 3289 3290 for (i = 0; i < bp->tx_nr_rings; i++, j++) { 3291 bp->tx_ring[i].bnapi = bp->bnapi[j]; 3292 bp->bnapi[j]->tx_ring = &bp->tx_ring[i]; 3293 bp->tx_ring_map[i] = bp->tx_nr_rings_xdp + i; 3294 if (i >= bp->tx_nr_rings_xdp) { 3295 bp->tx_ring[i].txq_index = i - 3296 bp->tx_nr_rings_xdp; 3297 bp->bnapi[j]->tx_int = bnxt_tx_int; 3298 } else { 3299 bp->bnapi[j]->flags |= BNXT_NAPI_FLAG_XDP; 3300 bp->bnapi[j]->tx_int = bnxt_tx_int_xdp; 3301 } 3302 } 3303 3304 rc = bnxt_alloc_stats(bp); 3305 if (rc) 3306 goto alloc_mem_err; 3307 3308 rc = bnxt_alloc_ntp_fltrs(bp); 3309 if (rc) 3310 goto alloc_mem_err; 3311 3312 rc = bnxt_alloc_vnics(bp); 3313 if (rc) 3314 goto alloc_mem_err; 3315 } 3316 3317 bnxt_init_ring_struct(bp); 3318 3319 rc = bnxt_alloc_rx_rings(bp); 3320 if (rc) 3321 goto alloc_mem_err; 3322 3323 rc = bnxt_alloc_tx_rings(bp); 3324 if (rc) 3325 goto alloc_mem_err; 3326 3327 rc = bnxt_alloc_cp_rings(bp); 3328 if (rc) 3329 goto alloc_mem_err; 3330 3331 bp->vnic_info[0].flags |= BNXT_VNIC_RSS_FLAG | BNXT_VNIC_MCAST_FLAG | 3332 BNXT_VNIC_UCAST_FLAG; 3333 rc = bnxt_alloc_vnic_attributes(bp); 3334 if (rc) 3335 goto alloc_mem_err; 3336 return 0; 3337 3338 alloc_mem_err: 3339 bnxt_free_mem(bp, true); 3340 return rc; 3341 } 3342 3343 static void bnxt_disable_int(struct bnxt *bp) 3344 { 3345 int i; 3346 3347 if (!bp->bnapi) 3348 return; 3349 3350 for (i = 0; i < bp->cp_nr_rings; i++) { 3351 struct bnxt_napi *bnapi = bp->bnapi[i]; 3352 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 3353 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct; 3354 3355 if (ring->fw_ring_id != INVALID_HW_RING_ID) 3356 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons); 3357 } 3358 } 3359 3360 static void bnxt_disable_int_sync(struct bnxt *bp) 3361 { 3362 int i; 3363 3364 atomic_inc(&bp->intr_sem); 3365 3366 bnxt_disable_int(bp); 3367 for (i = 0; i < bp->cp_nr_rings; i++) 3368 synchronize_irq(bp->irq_tbl[i].vector); 3369 } 3370 3371 static void bnxt_enable_int(struct bnxt *bp) 3372 { 3373 int i; 3374 3375 atomic_set(&bp->intr_sem, 0); 3376 for (i = 0; i < bp->cp_nr_rings; i++) { 3377 struct bnxt_napi *bnapi = bp->bnapi[i]; 3378 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 3379 3380 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons); 3381 } 3382 } 3383 3384 void bnxt_hwrm_cmd_hdr_init(struct bnxt *bp, void *request, u16 req_type, 3385 u16 cmpl_ring, u16 target_id) 3386 { 3387 struct input *req = request; 3388 3389 req->req_type = cpu_to_le16(req_type); 3390 req->cmpl_ring = cpu_to_le16(cmpl_ring); 3391 req->target_id = cpu_to_le16(target_id); 3392 req->resp_addr = cpu_to_le64(bp->hwrm_cmd_resp_dma_addr); 3393 } 3394 3395 static int bnxt_hwrm_do_send_msg(struct bnxt *bp, void *msg, u32 msg_len, 3396 int timeout, bool silent) 3397 { 3398 int i, intr_process, rc, tmo_count; 3399 struct input *req = msg; 3400 u32 *data = msg; 3401 __le32 *resp_len, *valid; 3402 u16 cp_ring_id, len = 0; 3403 struct hwrm_err_output *resp = bp->hwrm_cmd_resp_addr; 3404 u16 max_req_len = BNXT_HWRM_MAX_REQ_LEN; 3405 struct hwrm_short_input short_input = {0}; 3406 3407 req->seq_id = cpu_to_le16(bp->hwrm_cmd_seq++); 3408 memset(resp, 0, PAGE_SIZE); 3409 cp_ring_id = le16_to_cpu(req->cmpl_ring); 3410 intr_process = (cp_ring_id == INVALID_HW_RING_ID) ? 0 : 1; 3411 3412 if (bp->flags & BNXT_FLAG_SHORT_CMD) { 3413 void *short_cmd_req = bp->hwrm_short_cmd_req_addr; 3414 3415 memcpy(short_cmd_req, req, msg_len); 3416 memset(short_cmd_req + msg_len, 0, BNXT_HWRM_MAX_REQ_LEN - 3417 msg_len); 3418 3419 short_input.req_type = req->req_type; 3420 short_input.signature = 3421 cpu_to_le16(SHORT_REQ_SIGNATURE_SHORT_CMD); 3422 short_input.size = cpu_to_le16(msg_len); 3423 short_input.req_addr = 3424 cpu_to_le64(bp->hwrm_short_cmd_req_dma_addr); 3425 3426 data = (u32 *)&short_input; 3427 msg_len = sizeof(short_input); 3428 3429 /* Sync memory write before updating doorbell */ 3430 wmb(); 3431 3432 max_req_len = BNXT_HWRM_SHORT_REQ_LEN; 3433 } 3434 3435 /* Write request msg to hwrm channel */ 3436 __iowrite32_copy(bp->bar0, data, msg_len / 4); 3437 3438 for (i = msg_len; i < max_req_len; i += 4) 3439 writel(0, bp->bar0 + i); 3440 3441 /* currently supports only one outstanding message */ 3442 if (intr_process) 3443 bp->hwrm_intr_seq_id = le16_to_cpu(req->seq_id); 3444 3445 /* Ring channel doorbell */ 3446 writel(1, bp->bar0 + 0x100); 3447 3448 if (!timeout) 3449 timeout = DFLT_HWRM_CMD_TIMEOUT; 3450 3451 i = 0; 3452 tmo_count = timeout * 40; 3453 if (intr_process) { 3454 /* Wait until hwrm response cmpl interrupt is processed */ 3455 while (bp->hwrm_intr_seq_id != HWRM_SEQ_ID_INVALID && 3456 i++ < tmo_count) { 3457 usleep_range(25, 40); 3458 } 3459 3460 if (bp->hwrm_intr_seq_id != HWRM_SEQ_ID_INVALID) { 3461 netdev_err(bp->dev, "Resp cmpl intr err msg: 0x%x\n", 3462 le16_to_cpu(req->req_type)); 3463 return -1; 3464 } 3465 } else { 3466 /* Check if response len is updated */ 3467 resp_len = bp->hwrm_cmd_resp_addr + HWRM_RESP_LEN_OFFSET; 3468 for (i = 0; i < tmo_count; i++) { 3469 len = (le32_to_cpu(*resp_len) & HWRM_RESP_LEN_MASK) >> 3470 HWRM_RESP_LEN_SFT; 3471 if (len) 3472 break; 3473 usleep_range(25, 40); 3474 } 3475 3476 if (i >= tmo_count) { 3477 netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d\n", 3478 timeout, le16_to_cpu(req->req_type), 3479 le16_to_cpu(req->seq_id), len); 3480 return -1; 3481 } 3482 3483 /* Last word of resp contains valid bit */ 3484 valid = bp->hwrm_cmd_resp_addr + len - 4; 3485 for (i = 0; i < 5; i++) { 3486 if (le32_to_cpu(*valid) & HWRM_RESP_VALID_MASK) 3487 break; 3488 udelay(1); 3489 } 3490 3491 if (i >= 5) { 3492 netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d v:%d\n", 3493 timeout, le16_to_cpu(req->req_type), 3494 le16_to_cpu(req->seq_id), len, *valid); 3495 return -1; 3496 } 3497 } 3498 3499 rc = le16_to_cpu(resp->error_code); 3500 if (rc && !silent) 3501 netdev_err(bp->dev, "hwrm req_type 0x%x seq id 0x%x error 0x%x\n", 3502 le16_to_cpu(resp->req_type), 3503 le16_to_cpu(resp->seq_id), rc); 3504 return rc; 3505 } 3506 3507 int _hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout) 3508 { 3509 return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, false); 3510 } 3511 3512 int _hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len, 3513 int timeout) 3514 { 3515 return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true); 3516 } 3517 3518 int hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout) 3519 { 3520 int rc; 3521 3522 mutex_lock(&bp->hwrm_cmd_lock); 3523 rc = _hwrm_send_message(bp, msg, msg_len, timeout); 3524 mutex_unlock(&bp->hwrm_cmd_lock); 3525 return rc; 3526 } 3527 3528 int hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len, 3529 int timeout) 3530 { 3531 int rc; 3532 3533 mutex_lock(&bp->hwrm_cmd_lock); 3534 rc = bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true); 3535 mutex_unlock(&bp->hwrm_cmd_lock); 3536 return rc; 3537 } 3538 3539 int bnxt_hwrm_func_rgtr_async_events(struct bnxt *bp, unsigned long *bmap, 3540 int bmap_size) 3541 { 3542 struct hwrm_func_drv_rgtr_input req = {0}; 3543 DECLARE_BITMAP(async_events_bmap, 256); 3544 u32 *events = (u32 *)async_events_bmap; 3545 int i; 3546 3547 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1); 3548 3549 req.enables = 3550 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD); 3551 3552 memset(async_events_bmap, 0, sizeof(async_events_bmap)); 3553 for (i = 0; i < ARRAY_SIZE(bnxt_async_events_arr); i++) 3554 __set_bit(bnxt_async_events_arr[i], async_events_bmap); 3555 3556 if (bmap && bmap_size) { 3557 for (i = 0; i < bmap_size; i++) { 3558 if (test_bit(i, bmap)) 3559 __set_bit(i, async_events_bmap); 3560 } 3561 } 3562 3563 for (i = 0; i < 8; i++) 3564 req.async_event_fwd[i] |= cpu_to_le32(events[i]); 3565 3566 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 3567 } 3568 3569 static int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp) 3570 { 3571 struct hwrm_func_drv_rgtr_input req = {0}; 3572 3573 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1); 3574 3575 req.enables = 3576 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE | 3577 FUNC_DRV_RGTR_REQ_ENABLES_VER); 3578 3579 req.os_type = cpu_to_le16(FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX); 3580 req.ver_maj = DRV_VER_MAJ; 3581 req.ver_min = DRV_VER_MIN; 3582 req.ver_upd = DRV_VER_UPD; 3583 3584 if (BNXT_PF(bp)) { 3585 u32 data[8]; 3586 int i; 3587 3588 memset(data, 0, sizeof(data)); 3589 for (i = 0; i < ARRAY_SIZE(bnxt_vf_req_snif); i++) { 3590 u16 cmd = bnxt_vf_req_snif[i]; 3591 unsigned int bit, idx; 3592 3593 idx = cmd / 32; 3594 bit = cmd % 32; 3595 data[idx] |= 1 << bit; 3596 } 3597 3598 for (i = 0; i < 8; i++) 3599 req.vf_req_fwd[i] = cpu_to_le32(data[i]); 3600 3601 req.enables |= 3602 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD); 3603 } 3604 3605 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 3606 } 3607 3608 static int bnxt_hwrm_func_drv_unrgtr(struct bnxt *bp) 3609 { 3610 struct hwrm_func_drv_unrgtr_input req = {0}; 3611 3612 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_UNRGTR, -1, -1); 3613 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 3614 } 3615 3616 static int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, u8 tunnel_type) 3617 { 3618 u32 rc = 0; 3619 struct hwrm_tunnel_dst_port_free_input req = {0}; 3620 3621 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_FREE, -1, -1); 3622 req.tunnel_type = tunnel_type; 3623 3624 switch (tunnel_type) { 3625 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN: 3626 req.tunnel_dst_port_id = bp->vxlan_fw_dst_port_id; 3627 break; 3628 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE: 3629 req.tunnel_dst_port_id = bp->nge_fw_dst_port_id; 3630 break; 3631 default: 3632 break; 3633 } 3634 3635 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 3636 if (rc) 3637 netdev_err(bp->dev, "hwrm_tunnel_dst_port_free failed. rc:%d\n", 3638 rc); 3639 return rc; 3640 } 3641 3642 static int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, __be16 port, 3643 u8 tunnel_type) 3644 { 3645 u32 rc = 0; 3646 struct hwrm_tunnel_dst_port_alloc_input req = {0}; 3647 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr; 3648 3649 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_ALLOC, -1, -1); 3650 3651 req.tunnel_type = tunnel_type; 3652 req.tunnel_dst_port_val = port; 3653 3654 mutex_lock(&bp->hwrm_cmd_lock); 3655 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 3656 if (rc) { 3657 netdev_err(bp->dev, "hwrm_tunnel_dst_port_alloc failed. rc:%d\n", 3658 rc); 3659 goto err_out; 3660 } 3661 3662 switch (tunnel_type) { 3663 case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN: 3664 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id; 3665 break; 3666 case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE: 3667 bp->nge_fw_dst_port_id = resp->tunnel_dst_port_id; 3668 break; 3669 default: 3670 break; 3671 } 3672 3673 err_out: 3674 mutex_unlock(&bp->hwrm_cmd_lock); 3675 return rc; 3676 } 3677 3678 static int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp, u16 vnic_id) 3679 { 3680 struct hwrm_cfa_l2_set_rx_mask_input req = {0}; 3681 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 3682 3683 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_SET_RX_MASK, -1, -1); 3684 req.vnic_id = cpu_to_le32(vnic->fw_vnic_id); 3685 3686 req.num_mc_entries = cpu_to_le32(vnic->mc_list_count); 3687 req.mc_tbl_addr = cpu_to_le64(vnic->mc_list_mapping); 3688 req.mask = cpu_to_le32(vnic->rx_mask); 3689 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 3690 } 3691 3692 #ifdef CONFIG_RFS_ACCEL 3693 static int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt *bp, 3694 struct bnxt_ntuple_filter *fltr) 3695 { 3696 struct hwrm_cfa_ntuple_filter_free_input req = {0}; 3697 3698 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_FREE, -1, -1); 3699 req.ntuple_filter_id = fltr->filter_id; 3700 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 3701 } 3702 3703 #define BNXT_NTP_FLTR_FLAGS \ 3704 (CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID | \ 3705 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE | \ 3706 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR | \ 3707 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE | \ 3708 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR | \ 3709 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK | \ 3710 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR | \ 3711 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK | \ 3712 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL | \ 3713 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT | \ 3714 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK | \ 3715 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT | \ 3716 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK | \ 3717 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID) 3718 3719 #define BNXT_NTP_TUNNEL_FLTR_FLAG \ 3720 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 3721 3722 static int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt *bp, 3723 struct bnxt_ntuple_filter *fltr) 3724 { 3725 int rc = 0; 3726 struct hwrm_cfa_ntuple_filter_alloc_input req = {0}; 3727 struct hwrm_cfa_ntuple_filter_alloc_output *resp = 3728 bp->hwrm_cmd_resp_addr; 3729 struct flow_keys *keys = &fltr->fkeys; 3730 struct bnxt_vnic_info *vnic = &bp->vnic_info[fltr->rxq + 1]; 3731 3732 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_ALLOC, -1, -1); 3733 req.l2_filter_id = bp->vnic_info[0].fw_l2_filter_id[fltr->l2_fltr_idx]; 3734 3735 req.enables = cpu_to_le32(BNXT_NTP_FLTR_FLAGS); 3736 3737 req.ethertype = htons(ETH_P_IP); 3738 memcpy(req.src_macaddr, fltr->src_mac_addr, ETH_ALEN); 3739 req.ip_addr_type = CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4; 3740 req.ip_protocol = keys->basic.ip_proto; 3741 3742 if (keys->basic.n_proto == htons(ETH_P_IPV6)) { 3743 int i; 3744 3745 req.ethertype = htons(ETH_P_IPV6); 3746 req.ip_addr_type = 3747 CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6; 3748 *(struct in6_addr *)&req.src_ipaddr[0] = 3749 keys->addrs.v6addrs.src; 3750 *(struct in6_addr *)&req.dst_ipaddr[0] = 3751 keys->addrs.v6addrs.dst; 3752 for (i = 0; i < 4; i++) { 3753 req.src_ipaddr_mask[i] = cpu_to_be32(0xffffffff); 3754 req.dst_ipaddr_mask[i] = cpu_to_be32(0xffffffff); 3755 } 3756 } else { 3757 req.src_ipaddr[0] = keys->addrs.v4addrs.src; 3758 req.src_ipaddr_mask[0] = cpu_to_be32(0xffffffff); 3759 req.dst_ipaddr[0] = keys->addrs.v4addrs.dst; 3760 req.dst_ipaddr_mask[0] = cpu_to_be32(0xffffffff); 3761 } 3762 if (keys->control.flags & FLOW_DIS_ENCAPSULATION) { 3763 req.enables |= cpu_to_le32(BNXT_NTP_TUNNEL_FLTR_FLAG); 3764 req.tunnel_type = 3765 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL; 3766 } 3767 3768 req.src_port = keys->ports.src; 3769 req.src_port_mask = cpu_to_be16(0xffff); 3770 req.dst_port = keys->ports.dst; 3771 req.dst_port_mask = cpu_to_be16(0xffff); 3772 3773 req.dst_id = cpu_to_le16(vnic->fw_vnic_id); 3774 mutex_lock(&bp->hwrm_cmd_lock); 3775 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 3776 if (!rc) 3777 fltr->filter_id = resp->ntuple_filter_id; 3778 mutex_unlock(&bp->hwrm_cmd_lock); 3779 return rc; 3780 } 3781 #endif 3782 3783 static int bnxt_hwrm_set_vnic_filter(struct bnxt *bp, u16 vnic_id, u16 idx, 3784 u8 *mac_addr) 3785 { 3786 u32 rc = 0; 3787 struct hwrm_cfa_l2_filter_alloc_input req = {0}; 3788 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr; 3789 3790 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_ALLOC, -1, -1); 3791 req.flags = cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX); 3792 if (!BNXT_CHIP_TYPE_NITRO_A0(bp)) 3793 req.flags |= 3794 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST); 3795 req.dst_id = cpu_to_le16(bp->vnic_info[vnic_id].fw_vnic_id); 3796 req.enables = 3797 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR | 3798 CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID | 3799 CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK); 3800 memcpy(req.l2_addr, mac_addr, ETH_ALEN); 3801 req.l2_addr_mask[0] = 0xff; 3802 req.l2_addr_mask[1] = 0xff; 3803 req.l2_addr_mask[2] = 0xff; 3804 req.l2_addr_mask[3] = 0xff; 3805 req.l2_addr_mask[4] = 0xff; 3806 req.l2_addr_mask[5] = 0xff; 3807 3808 mutex_lock(&bp->hwrm_cmd_lock); 3809 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 3810 if (!rc) 3811 bp->vnic_info[vnic_id].fw_l2_filter_id[idx] = 3812 resp->l2_filter_id; 3813 mutex_unlock(&bp->hwrm_cmd_lock); 3814 return rc; 3815 } 3816 3817 static int bnxt_hwrm_clear_vnic_filter(struct bnxt *bp) 3818 { 3819 u16 i, j, num_of_vnics = 1; /* only vnic 0 supported */ 3820 int rc = 0; 3821 3822 /* Any associated ntuple filters will also be cleared by firmware. */ 3823 mutex_lock(&bp->hwrm_cmd_lock); 3824 for (i = 0; i < num_of_vnics; i++) { 3825 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 3826 3827 for (j = 0; j < vnic->uc_filter_count; j++) { 3828 struct hwrm_cfa_l2_filter_free_input req = {0}; 3829 3830 bnxt_hwrm_cmd_hdr_init(bp, &req, 3831 HWRM_CFA_L2_FILTER_FREE, -1, -1); 3832 3833 req.l2_filter_id = vnic->fw_l2_filter_id[j]; 3834 3835 rc = _hwrm_send_message(bp, &req, sizeof(req), 3836 HWRM_CMD_TIMEOUT); 3837 } 3838 vnic->uc_filter_count = 0; 3839 } 3840 mutex_unlock(&bp->hwrm_cmd_lock); 3841 3842 return rc; 3843 } 3844 3845 static int bnxt_hwrm_vnic_set_tpa(struct bnxt *bp, u16 vnic_id, u32 tpa_flags) 3846 { 3847 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 3848 struct hwrm_vnic_tpa_cfg_input req = {0}; 3849 3850 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_TPA_CFG, -1, -1); 3851 3852 if (tpa_flags) { 3853 u16 mss = bp->dev->mtu - 40; 3854 u32 nsegs, n, segs = 0, flags; 3855 3856 flags = VNIC_TPA_CFG_REQ_FLAGS_TPA | 3857 VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA | 3858 VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE | 3859 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN | 3860 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ; 3861 if (tpa_flags & BNXT_FLAG_GRO) 3862 flags |= VNIC_TPA_CFG_REQ_FLAGS_GRO; 3863 3864 req.flags = cpu_to_le32(flags); 3865 3866 req.enables = 3867 cpu_to_le32(VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS | 3868 VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS | 3869 VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN); 3870 3871 /* Number of segs are log2 units, and first packet is not 3872 * included as part of this units. 3873 */ 3874 if (mss <= BNXT_RX_PAGE_SIZE) { 3875 n = BNXT_RX_PAGE_SIZE / mss; 3876 nsegs = (MAX_SKB_FRAGS - 1) * n; 3877 } else { 3878 n = mss / BNXT_RX_PAGE_SIZE; 3879 if (mss & (BNXT_RX_PAGE_SIZE - 1)) 3880 n++; 3881 nsegs = (MAX_SKB_FRAGS - n) / n; 3882 } 3883 3884 segs = ilog2(nsegs); 3885 req.max_agg_segs = cpu_to_le16(segs); 3886 req.max_aggs = cpu_to_le16(VNIC_TPA_CFG_REQ_MAX_AGGS_MAX); 3887 3888 req.min_agg_len = cpu_to_le32(512); 3889 } 3890 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id); 3891 3892 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 3893 } 3894 3895 static int bnxt_hwrm_vnic_set_rss(struct bnxt *bp, u16 vnic_id, bool set_rss) 3896 { 3897 u32 i, j, max_rings; 3898 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 3899 struct hwrm_vnic_rss_cfg_input req = {0}; 3900 3901 if (vnic->fw_rss_cos_lb_ctx[0] == INVALID_HW_RING_ID) 3902 return 0; 3903 3904 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1); 3905 if (set_rss) { 3906 req.hash_type = cpu_to_le32(bp->rss_hash_cfg); 3907 if (vnic->flags & BNXT_VNIC_RSS_FLAG) { 3908 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 3909 max_rings = bp->rx_nr_rings - 1; 3910 else 3911 max_rings = bp->rx_nr_rings; 3912 } else { 3913 max_rings = 1; 3914 } 3915 3916 /* Fill the RSS indirection table with ring group ids */ 3917 for (i = 0, j = 0; i < HW_HASH_INDEX_SIZE; i++, j++) { 3918 if (j == max_rings) 3919 j = 0; 3920 vnic->rss_table[i] = cpu_to_le16(vnic->fw_grp_ids[j]); 3921 } 3922 3923 req.ring_grp_tbl_addr = cpu_to_le64(vnic->rss_table_dma_addr); 3924 req.hash_key_tbl_addr = 3925 cpu_to_le64(vnic->rss_hash_key_dma_addr); 3926 } 3927 req.rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]); 3928 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 3929 } 3930 3931 static int bnxt_hwrm_vnic_set_hds(struct bnxt *bp, u16 vnic_id) 3932 { 3933 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 3934 struct hwrm_vnic_plcmodes_cfg_input req = {0}; 3935 3936 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_PLCMODES_CFG, -1, -1); 3937 req.flags = cpu_to_le32(VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT | 3938 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 | 3939 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6); 3940 req.enables = 3941 cpu_to_le32(VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID | 3942 VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID); 3943 /* thresholds not implemented in firmware yet */ 3944 req.jumbo_thresh = cpu_to_le16(bp->rx_copy_thresh); 3945 req.hds_threshold = cpu_to_le16(bp->rx_copy_thresh); 3946 req.vnic_id = cpu_to_le32(vnic->fw_vnic_id); 3947 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 3948 } 3949 3950 static void bnxt_hwrm_vnic_ctx_free_one(struct bnxt *bp, u16 vnic_id, 3951 u16 ctx_idx) 3952 { 3953 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {0}; 3954 3955 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, -1, -1); 3956 req.rss_cos_lb_ctx_id = 3957 cpu_to_le16(bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx]); 3958 3959 hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 3960 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] = INVALID_HW_RING_ID; 3961 } 3962 3963 static void bnxt_hwrm_vnic_ctx_free(struct bnxt *bp) 3964 { 3965 int i, j; 3966 3967 for (i = 0; i < bp->nr_vnics; i++) { 3968 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 3969 3970 for (j = 0; j < BNXT_MAX_CTX_PER_VNIC; j++) { 3971 if (vnic->fw_rss_cos_lb_ctx[j] != INVALID_HW_RING_ID) 3972 bnxt_hwrm_vnic_ctx_free_one(bp, i, j); 3973 } 3974 } 3975 bp->rsscos_nr_ctxs = 0; 3976 } 3977 3978 static int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, u16 vnic_id, u16 ctx_idx) 3979 { 3980 int rc; 3981 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {0}; 3982 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp = 3983 bp->hwrm_cmd_resp_addr; 3984 3985 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, -1, 3986 -1); 3987 3988 mutex_lock(&bp->hwrm_cmd_lock); 3989 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 3990 if (!rc) 3991 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] = 3992 le16_to_cpu(resp->rss_cos_lb_ctx_id); 3993 mutex_unlock(&bp->hwrm_cmd_lock); 3994 3995 return rc; 3996 } 3997 3998 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id) 3999 { 4000 unsigned int ring = 0, grp_idx; 4001 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 4002 struct hwrm_vnic_cfg_input req = {0}; 4003 u16 def_vlan = 0; 4004 4005 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_CFG, -1, -1); 4006 4007 req.enables = cpu_to_le32(VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP); 4008 /* Only RSS support for now TBD: COS & LB */ 4009 if (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID) { 4010 req.rss_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]); 4011 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE | 4012 VNIC_CFG_REQ_ENABLES_MRU); 4013 } else if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG) { 4014 req.rss_rule = 4015 cpu_to_le16(bp->vnic_info[0].fw_rss_cos_lb_ctx[0]); 4016 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE | 4017 VNIC_CFG_REQ_ENABLES_MRU); 4018 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE); 4019 } else { 4020 req.rss_rule = cpu_to_le16(0xffff); 4021 } 4022 4023 if (BNXT_CHIP_TYPE_NITRO_A0(bp) && 4024 (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID)) { 4025 req.cos_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[1]); 4026 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_COS_RULE); 4027 } else { 4028 req.cos_rule = cpu_to_le16(0xffff); 4029 } 4030 4031 if (vnic->flags & BNXT_VNIC_RSS_FLAG) 4032 ring = 0; 4033 else if (vnic->flags & BNXT_VNIC_RFS_FLAG) 4034 ring = vnic_id - 1; 4035 else if ((vnic_id == 1) && BNXT_CHIP_TYPE_NITRO_A0(bp)) 4036 ring = bp->rx_nr_rings - 1; 4037 4038 grp_idx = bp->rx_ring[ring].bnapi->index; 4039 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id); 4040 req.dflt_ring_grp = cpu_to_le16(bp->grp_info[grp_idx].fw_grp_id); 4041 4042 req.lb_rule = cpu_to_le16(0xffff); 4043 req.mru = cpu_to_le16(bp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + 4044 VLAN_HLEN); 4045 4046 #ifdef CONFIG_BNXT_SRIOV 4047 if (BNXT_VF(bp)) 4048 def_vlan = bp->vf.vlan; 4049 #endif 4050 if ((bp->flags & BNXT_FLAG_STRIP_VLAN) || def_vlan) 4051 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE); 4052 if (!vnic_id && bnxt_ulp_registered(bp->edev, BNXT_ROCE_ULP)) 4053 req.flags |= 4054 cpu_to_le32(VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE); 4055 4056 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4057 } 4058 4059 static int bnxt_hwrm_vnic_free_one(struct bnxt *bp, u16 vnic_id) 4060 { 4061 u32 rc = 0; 4062 4063 if (bp->vnic_info[vnic_id].fw_vnic_id != INVALID_HW_RING_ID) { 4064 struct hwrm_vnic_free_input req = {0}; 4065 4066 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_FREE, -1, -1); 4067 req.vnic_id = 4068 cpu_to_le32(bp->vnic_info[vnic_id].fw_vnic_id); 4069 4070 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4071 if (rc) 4072 return rc; 4073 bp->vnic_info[vnic_id].fw_vnic_id = INVALID_HW_RING_ID; 4074 } 4075 return rc; 4076 } 4077 4078 static void bnxt_hwrm_vnic_free(struct bnxt *bp) 4079 { 4080 u16 i; 4081 4082 for (i = 0; i < bp->nr_vnics; i++) 4083 bnxt_hwrm_vnic_free_one(bp, i); 4084 } 4085 4086 static int bnxt_hwrm_vnic_alloc(struct bnxt *bp, u16 vnic_id, 4087 unsigned int start_rx_ring_idx, 4088 unsigned int nr_rings) 4089 { 4090 int rc = 0; 4091 unsigned int i, j, grp_idx, end_idx = start_rx_ring_idx + nr_rings; 4092 struct hwrm_vnic_alloc_input req = {0}; 4093 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr; 4094 4095 /* map ring groups to this vnic */ 4096 for (i = start_rx_ring_idx, j = 0; i < end_idx; i++, j++) { 4097 grp_idx = bp->rx_ring[i].bnapi->index; 4098 if (bp->grp_info[grp_idx].fw_grp_id == INVALID_HW_RING_ID) { 4099 netdev_err(bp->dev, "Not enough ring groups avail:%x req:%x\n", 4100 j, nr_rings); 4101 break; 4102 } 4103 bp->vnic_info[vnic_id].fw_grp_ids[j] = 4104 bp->grp_info[grp_idx].fw_grp_id; 4105 } 4106 4107 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[0] = INVALID_HW_RING_ID; 4108 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[1] = INVALID_HW_RING_ID; 4109 if (vnic_id == 0) 4110 req.flags = cpu_to_le32(VNIC_ALLOC_REQ_FLAGS_DEFAULT); 4111 4112 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_ALLOC, -1, -1); 4113 4114 mutex_lock(&bp->hwrm_cmd_lock); 4115 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4116 if (!rc) 4117 bp->vnic_info[vnic_id].fw_vnic_id = le32_to_cpu(resp->vnic_id); 4118 mutex_unlock(&bp->hwrm_cmd_lock); 4119 return rc; 4120 } 4121 4122 static int bnxt_hwrm_vnic_qcaps(struct bnxt *bp) 4123 { 4124 struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr; 4125 struct hwrm_vnic_qcaps_input req = {0}; 4126 int rc; 4127 4128 if (bp->hwrm_spec_code < 0x10600) 4129 return 0; 4130 4131 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_QCAPS, -1, -1); 4132 mutex_lock(&bp->hwrm_cmd_lock); 4133 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4134 if (!rc) { 4135 if (resp->flags & 4136 cpu_to_le32(VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP)) 4137 bp->flags |= BNXT_FLAG_NEW_RSS_CAP; 4138 } 4139 mutex_unlock(&bp->hwrm_cmd_lock); 4140 return rc; 4141 } 4142 4143 static int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp) 4144 { 4145 u16 i; 4146 u32 rc = 0; 4147 4148 mutex_lock(&bp->hwrm_cmd_lock); 4149 for (i = 0; i < bp->rx_nr_rings; i++) { 4150 struct hwrm_ring_grp_alloc_input req = {0}; 4151 struct hwrm_ring_grp_alloc_output *resp = 4152 bp->hwrm_cmd_resp_addr; 4153 unsigned int grp_idx = bp->rx_ring[i].bnapi->index; 4154 4155 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_ALLOC, -1, -1); 4156 4157 req.cr = cpu_to_le16(bp->grp_info[grp_idx].cp_fw_ring_id); 4158 req.rr = cpu_to_le16(bp->grp_info[grp_idx].rx_fw_ring_id); 4159 req.ar = cpu_to_le16(bp->grp_info[grp_idx].agg_fw_ring_id); 4160 req.sc = cpu_to_le16(bp->grp_info[grp_idx].fw_stats_ctx); 4161 4162 rc = _hwrm_send_message(bp, &req, sizeof(req), 4163 HWRM_CMD_TIMEOUT); 4164 if (rc) 4165 break; 4166 4167 bp->grp_info[grp_idx].fw_grp_id = 4168 le32_to_cpu(resp->ring_group_id); 4169 } 4170 mutex_unlock(&bp->hwrm_cmd_lock); 4171 return rc; 4172 } 4173 4174 static int bnxt_hwrm_ring_grp_free(struct bnxt *bp) 4175 { 4176 u16 i; 4177 u32 rc = 0; 4178 struct hwrm_ring_grp_free_input req = {0}; 4179 4180 if (!bp->grp_info) 4181 return 0; 4182 4183 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_FREE, -1, -1); 4184 4185 mutex_lock(&bp->hwrm_cmd_lock); 4186 for (i = 0; i < bp->cp_nr_rings; i++) { 4187 if (bp->grp_info[i].fw_grp_id == INVALID_HW_RING_ID) 4188 continue; 4189 req.ring_group_id = 4190 cpu_to_le32(bp->grp_info[i].fw_grp_id); 4191 4192 rc = _hwrm_send_message(bp, &req, sizeof(req), 4193 HWRM_CMD_TIMEOUT); 4194 if (rc) 4195 break; 4196 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID; 4197 } 4198 mutex_unlock(&bp->hwrm_cmd_lock); 4199 return rc; 4200 } 4201 4202 static int hwrm_ring_alloc_send_msg(struct bnxt *bp, 4203 struct bnxt_ring_struct *ring, 4204 u32 ring_type, u32 map_index, 4205 u32 stats_ctx_id) 4206 { 4207 int rc = 0, err = 0; 4208 struct hwrm_ring_alloc_input req = {0}; 4209 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr; 4210 u16 ring_id; 4211 4212 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_ALLOC, -1, -1); 4213 4214 req.enables = 0; 4215 if (ring->nr_pages > 1) { 4216 req.page_tbl_addr = cpu_to_le64(ring->pg_tbl_map); 4217 /* Page size is in log2 units */ 4218 req.page_size = BNXT_PAGE_SHIFT; 4219 req.page_tbl_depth = 1; 4220 } else { 4221 req.page_tbl_addr = cpu_to_le64(ring->dma_arr[0]); 4222 } 4223 req.fbo = 0; 4224 /* Association of ring index with doorbell index and MSIX number */ 4225 req.logical_id = cpu_to_le16(map_index); 4226 4227 switch (ring_type) { 4228 case HWRM_RING_ALLOC_TX: 4229 req.ring_type = RING_ALLOC_REQ_RING_TYPE_TX; 4230 /* Association of transmit ring with completion ring */ 4231 req.cmpl_ring_id = 4232 cpu_to_le16(bp->grp_info[map_index].cp_fw_ring_id); 4233 req.length = cpu_to_le32(bp->tx_ring_mask + 1); 4234 req.stat_ctx_id = cpu_to_le32(stats_ctx_id); 4235 req.queue_id = cpu_to_le16(ring->queue_id); 4236 break; 4237 case HWRM_RING_ALLOC_RX: 4238 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX; 4239 req.length = cpu_to_le32(bp->rx_ring_mask + 1); 4240 break; 4241 case HWRM_RING_ALLOC_AGG: 4242 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX; 4243 req.length = cpu_to_le32(bp->rx_agg_ring_mask + 1); 4244 break; 4245 case HWRM_RING_ALLOC_CMPL: 4246 req.ring_type = RING_ALLOC_REQ_RING_TYPE_L2_CMPL; 4247 req.length = cpu_to_le32(bp->cp_ring_mask + 1); 4248 if (bp->flags & BNXT_FLAG_USING_MSIX) 4249 req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX; 4250 break; 4251 default: 4252 netdev_err(bp->dev, "hwrm alloc invalid ring type %d\n", 4253 ring_type); 4254 return -1; 4255 } 4256 4257 mutex_lock(&bp->hwrm_cmd_lock); 4258 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4259 err = le16_to_cpu(resp->error_code); 4260 ring_id = le16_to_cpu(resp->ring_id); 4261 mutex_unlock(&bp->hwrm_cmd_lock); 4262 4263 if (rc || err) { 4264 switch (ring_type) { 4265 case RING_FREE_REQ_RING_TYPE_L2_CMPL: 4266 netdev_err(bp->dev, "hwrm_ring_alloc cp failed. rc:%x err:%x\n", 4267 rc, err); 4268 return -1; 4269 4270 case RING_FREE_REQ_RING_TYPE_RX: 4271 netdev_err(bp->dev, "hwrm_ring_alloc rx failed. rc:%x err:%x\n", 4272 rc, err); 4273 return -1; 4274 4275 case RING_FREE_REQ_RING_TYPE_TX: 4276 netdev_err(bp->dev, "hwrm_ring_alloc tx failed. rc:%x err:%x\n", 4277 rc, err); 4278 return -1; 4279 4280 default: 4281 netdev_err(bp->dev, "Invalid ring\n"); 4282 return -1; 4283 } 4284 } 4285 ring->fw_ring_id = ring_id; 4286 return rc; 4287 } 4288 4289 static int bnxt_hwrm_set_async_event_cr(struct bnxt *bp, int idx) 4290 { 4291 int rc; 4292 4293 if (BNXT_PF(bp)) { 4294 struct hwrm_func_cfg_input req = {0}; 4295 4296 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1); 4297 req.fid = cpu_to_le16(0xffff); 4298 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR); 4299 req.async_event_cr = cpu_to_le16(idx); 4300 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4301 } else { 4302 struct hwrm_func_vf_cfg_input req = {0}; 4303 4304 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_VF_CFG, -1, -1); 4305 req.enables = 4306 cpu_to_le32(FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR); 4307 req.async_event_cr = cpu_to_le16(idx); 4308 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4309 } 4310 return rc; 4311 } 4312 4313 static int bnxt_hwrm_ring_alloc(struct bnxt *bp) 4314 { 4315 int i, rc = 0; 4316 4317 for (i = 0; i < bp->cp_nr_rings; i++) { 4318 struct bnxt_napi *bnapi = bp->bnapi[i]; 4319 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 4320 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct; 4321 4322 cpr->cp_doorbell = bp->bar1 + i * 0x80; 4323 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_CMPL, i, 4324 INVALID_STATS_CTX_ID); 4325 if (rc) 4326 goto err_out; 4327 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons); 4328 bp->grp_info[i].cp_fw_ring_id = ring->fw_ring_id; 4329 4330 if (!i) { 4331 rc = bnxt_hwrm_set_async_event_cr(bp, ring->fw_ring_id); 4332 if (rc) 4333 netdev_warn(bp->dev, "Failed to set async event completion ring.\n"); 4334 } 4335 } 4336 4337 for (i = 0; i < bp->tx_nr_rings; i++) { 4338 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; 4339 struct bnxt_ring_struct *ring = &txr->tx_ring_struct; 4340 u32 map_idx = txr->bnapi->index; 4341 u16 fw_stats_ctx = bp->grp_info[map_idx].fw_stats_ctx; 4342 4343 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_TX, 4344 map_idx, fw_stats_ctx); 4345 if (rc) 4346 goto err_out; 4347 txr->tx_doorbell = bp->bar1 + map_idx * 0x80; 4348 } 4349 4350 for (i = 0; i < bp->rx_nr_rings; i++) { 4351 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 4352 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct; 4353 u32 map_idx = rxr->bnapi->index; 4354 4355 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_RX, 4356 map_idx, INVALID_STATS_CTX_ID); 4357 if (rc) 4358 goto err_out; 4359 rxr->rx_doorbell = bp->bar1 + map_idx * 0x80; 4360 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell); 4361 bp->grp_info[map_idx].rx_fw_ring_id = ring->fw_ring_id; 4362 } 4363 4364 if (bp->flags & BNXT_FLAG_AGG_RINGS) { 4365 for (i = 0; i < bp->rx_nr_rings; i++) { 4366 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 4367 struct bnxt_ring_struct *ring = 4368 &rxr->rx_agg_ring_struct; 4369 u32 grp_idx = rxr->bnapi->index; 4370 u32 map_idx = grp_idx + bp->rx_nr_rings; 4371 4372 rc = hwrm_ring_alloc_send_msg(bp, ring, 4373 HWRM_RING_ALLOC_AGG, 4374 map_idx, 4375 INVALID_STATS_CTX_ID); 4376 if (rc) 4377 goto err_out; 4378 4379 rxr->rx_agg_doorbell = bp->bar1 + map_idx * 0x80; 4380 writel(DB_KEY_RX | rxr->rx_agg_prod, 4381 rxr->rx_agg_doorbell); 4382 bp->grp_info[grp_idx].agg_fw_ring_id = ring->fw_ring_id; 4383 } 4384 } 4385 err_out: 4386 return rc; 4387 } 4388 4389 static int hwrm_ring_free_send_msg(struct bnxt *bp, 4390 struct bnxt_ring_struct *ring, 4391 u32 ring_type, int cmpl_ring_id) 4392 { 4393 int rc; 4394 struct hwrm_ring_free_input req = {0}; 4395 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr; 4396 u16 error_code; 4397 4398 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_FREE, cmpl_ring_id, -1); 4399 req.ring_type = ring_type; 4400 req.ring_id = cpu_to_le16(ring->fw_ring_id); 4401 4402 mutex_lock(&bp->hwrm_cmd_lock); 4403 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4404 error_code = le16_to_cpu(resp->error_code); 4405 mutex_unlock(&bp->hwrm_cmd_lock); 4406 4407 if (rc || error_code) { 4408 switch (ring_type) { 4409 case RING_FREE_REQ_RING_TYPE_L2_CMPL: 4410 netdev_err(bp->dev, "hwrm_ring_free cp failed. rc:%d\n", 4411 rc); 4412 return rc; 4413 case RING_FREE_REQ_RING_TYPE_RX: 4414 netdev_err(bp->dev, "hwrm_ring_free rx failed. rc:%d\n", 4415 rc); 4416 return rc; 4417 case RING_FREE_REQ_RING_TYPE_TX: 4418 netdev_err(bp->dev, "hwrm_ring_free tx failed. rc:%d\n", 4419 rc); 4420 return rc; 4421 default: 4422 netdev_err(bp->dev, "Invalid ring\n"); 4423 return -1; 4424 } 4425 } 4426 return 0; 4427 } 4428 4429 static void bnxt_hwrm_ring_free(struct bnxt *bp, bool close_path) 4430 { 4431 int i; 4432 4433 if (!bp->bnapi) 4434 return; 4435 4436 for (i = 0; i < bp->tx_nr_rings; i++) { 4437 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; 4438 struct bnxt_ring_struct *ring = &txr->tx_ring_struct; 4439 u32 grp_idx = txr->bnapi->index; 4440 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id; 4441 4442 if (ring->fw_ring_id != INVALID_HW_RING_ID) { 4443 hwrm_ring_free_send_msg(bp, ring, 4444 RING_FREE_REQ_RING_TYPE_TX, 4445 close_path ? cmpl_ring_id : 4446 INVALID_HW_RING_ID); 4447 ring->fw_ring_id = INVALID_HW_RING_ID; 4448 } 4449 } 4450 4451 for (i = 0; i < bp->rx_nr_rings; i++) { 4452 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 4453 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct; 4454 u32 grp_idx = rxr->bnapi->index; 4455 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id; 4456 4457 if (ring->fw_ring_id != INVALID_HW_RING_ID) { 4458 hwrm_ring_free_send_msg(bp, ring, 4459 RING_FREE_REQ_RING_TYPE_RX, 4460 close_path ? cmpl_ring_id : 4461 INVALID_HW_RING_ID); 4462 ring->fw_ring_id = INVALID_HW_RING_ID; 4463 bp->grp_info[grp_idx].rx_fw_ring_id = 4464 INVALID_HW_RING_ID; 4465 } 4466 } 4467 4468 for (i = 0; i < bp->rx_nr_rings; i++) { 4469 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 4470 struct bnxt_ring_struct *ring = &rxr->rx_agg_ring_struct; 4471 u32 grp_idx = rxr->bnapi->index; 4472 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id; 4473 4474 if (ring->fw_ring_id != INVALID_HW_RING_ID) { 4475 hwrm_ring_free_send_msg(bp, ring, 4476 RING_FREE_REQ_RING_TYPE_RX, 4477 close_path ? cmpl_ring_id : 4478 INVALID_HW_RING_ID); 4479 ring->fw_ring_id = INVALID_HW_RING_ID; 4480 bp->grp_info[grp_idx].agg_fw_ring_id = 4481 INVALID_HW_RING_ID; 4482 } 4483 } 4484 4485 /* The completion rings are about to be freed. After that the 4486 * IRQ doorbell will not work anymore. So we need to disable 4487 * IRQ here. 4488 */ 4489 bnxt_disable_int_sync(bp); 4490 4491 for (i = 0; i < bp->cp_nr_rings; i++) { 4492 struct bnxt_napi *bnapi = bp->bnapi[i]; 4493 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 4494 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct; 4495 4496 if (ring->fw_ring_id != INVALID_HW_RING_ID) { 4497 hwrm_ring_free_send_msg(bp, ring, 4498 RING_FREE_REQ_RING_TYPE_L2_CMPL, 4499 INVALID_HW_RING_ID); 4500 ring->fw_ring_id = INVALID_HW_RING_ID; 4501 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID; 4502 } 4503 } 4504 } 4505 4506 static int bnxt_hwrm_get_rings(struct bnxt *bp) 4507 { 4508 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr; 4509 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 4510 struct hwrm_func_qcfg_input req = {0}; 4511 int rc; 4512 4513 if (bp->hwrm_spec_code < 0x10601) 4514 return 0; 4515 4516 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1); 4517 req.fid = cpu_to_le16(0xffff); 4518 mutex_lock(&bp->hwrm_cmd_lock); 4519 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4520 if (rc) { 4521 mutex_unlock(&bp->hwrm_cmd_lock); 4522 return -EIO; 4523 } 4524 4525 hw_resc->resv_tx_rings = le16_to_cpu(resp->alloc_tx_rings); 4526 if (bp->flags & BNXT_FLAG_NEW_RM) { 4527 u16 cp, stats; 4528 4529 hw_resc->resv_rx_rings = le16_to_cpu(resp->alloc_rx_rings); 4530 hw_resc->resv_hw_ring_grps = 4531 le32_to_cpu(resp->alloc_hw_ring_grps); 4532 hw_resc->resv_vnics = le16_to_cpu(resp->alloc_vnics); 4533 cp = le16_to_cpu(resp->alloc_cmpl_rings); 4534 stats = le16_to_cpu(resp->alloc_stat_ctx); 4535 cp = min_t(u16, cp, stats); 4536 hw_resc->resv_cp_rings = cp; 4537 } 4538 mutex_unlock(&bp->hwrm_cmd_lock); 4539 return 0; 4540 } 4541 4542 /* Caller must hold bp->hwrm_cmd_lock */ 4543 int __bnxt_hwrm_get_tx_rings(struct bnxt *bp, u16 fid, int *tx_rings) 4544 { 4545 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr; 4546 struct hwrm_func_qcfg_input req = {0}; 4547 int rc; 4548 4549 if (bp->hwrm_spec_code < 0x10601) 4550 return 0; 4551 4552 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1); 4553 req.fid = cpu_to_le16(fid); 4554 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4555 if (!rc) 4556 *tx_rings = le16_to_cpu(resp->alloc_tx_rings); 4557 4558 return rc; 4559 } 4560 4561 static int 4562 bnxt_hwrm_reserve_pf_rings(struct bnxt *bp, int tx_rings, int rx_rings, 4563 int ring_grps, int cp_rings, int vnics) 4564 { 4565 struct hwrm_func_cfg_input req = {0}; 4566 u32 enables = 0; 4567 int rc; 4568 4569 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1); 4570 req.fid = cpu_to_le16(0xffff); 4571 enables |= tx_rings ? FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS : 0; 4572 req.num_tx_rings = cpu_to_le16(tx_rings); 4573 if (bp->flags & BNXT_FLAG_NEW_RM) { 4574 enables |= rx_rings ? FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS : 0; 4575 enables |= cp_rings ? FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS | 4576 FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0; 4577 enables |= ring_grps ? 4578 FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS : 0; 4579 enables |= vnics ? FUNC_VF_CFG_REQ_ENABLES_NUM_VNICS : 0; 4580 4581 req.num_rx_rings = cpu_to_le16(rx_rings); 4582 req.num_hw_ring_grps = cpu_to_le16(ring_grps); 4583 req.num_cmpl_rings = cpu_to_le16(cp_rings); 4584 req.num_stat_ctxs = req.num_cmpl_rings; 4585 req.num_vnics = cpu_to_le16(vnics); 4586 } 4587 if (!enables) 4588 return 0; 4589 4590 req.enables = cpu_to_le32(enables); 4591 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4592 if (rc) 4593 return -ENOMEM; 4594 4595 if (bp->hwrm_spec_code < 0x10601) 4596 bp->hw_resc.resv_tx_rings = tx_rings; 4597 4598 rc = bnxt_hwrm_get_rings(bp); 4599 return rc; 4600 } 4601 4602 static int 4603 bnxt_hwrm_reserve_vf_rings(struct bnxt *bp, int tx_rings, int rx_rings, 4604 int ring_grps, int cp_rings, int vnics) 4605 { 4606 struct hwrm_func_vf_cfg_input req = {0}; 4607 u32 enables = 0; 4608 int rc; 4609 4610 if (!(bp->flags & BNXT_FLAG_NEW_RM)) { 4611 bp->hw_resc.resv_tx_rings = tx_rings; 4612 return 0; 4613 } 4614 4615 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_VF_CFG, -1, -1); 4616 enables |= tx_rings ? FUNC_VF_CFG_REQ_ENABLES_NUM_TX_RINGS : 0; 4617 enables |= rx_rings ? FUNC_VF_CFG_REQ_ENABLES_NUM_RX_RINGS : 0; 4618 enables |= cp_rings ? FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS | 4619 FUNC_VF_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0; 4620 enables |= ring_grps ? FUNC_VF_CFG_REQ_ENABLES_NUM_HW_RING_GRPS : 0; 4621 enables |= vnics ? FUNC_VF_CFG_REQ_ENABLES_NUM_VNICS : 0; 4622 4623 req.num_tx_rings = cpu_to_le16(tx_rings); 4624 req.num_rx_rings = cpu_to_le16(rx_rings); 4625 req.num_hw_ring_grps = cpu_to_le16(ring_grps); 4626 req.num_cmpl_rings = cpu_to_le16(cp_rings); 4627 req.num_stat_ctxs = req.num_cmpl_rings; 4628 req.num_vnics = cpu_to_le16(vnics); 4629 4630 req.enables = cpu_to_le32(enables); 4631 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4632 if (rc) 4633 return -ENOMEM; 4634 4635 rc = bnxt_hwrm_get_rings(bp); 4636 return rc; 4637 } 4638 4639 static int bnxt_hwrm_reserve_rings(struct bnxt *bp, int tx, int rx, int grp, 4640 int cp, int vnic) 4641 { 4642 if (BNXT_PF(bp)) 4643 return bnxt_hwrm_reserve_pf_rings(bp, tx, rx, grp, cp, vnic); 4644 else 4645 return bnxt_hwrm_reserve_vf_rings(bp, tx, rx, grp, cp, vnic); 4646 } 4647 4648 static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max, 4649 bool shared); 4650 4651 static int __bnxt_reserve_rings(struct bnxt *bp) 4652 { 4653 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 4654 int tx = bp->tx_nr_rings; 4655 int rx = bp->rx_nr_rings; 4656 int cp = bp->cp_nr_rings; 4657 int grp, rx_rings, rc; 4658 bool sh = false; 4659 int vnic = 1; 4660 4661 if (bp->hwrm_spec_code < 0x10601) 4662 return 0; 4663 4664 if (bp->flags & BNXT_FLAG_SHARED_RINGS) 4665 sh = true; 4666 if (bp->flags & BNXT_FLAG_RFS) 4667 vnic = rx + 1; 4668 if (bp->flags & BNXT_FLAG_AGG_RINGS) 4669 rx <<= 1; 4670 4671 grp = bp->rx_nr_rings; 4672 if (tx == hw_resc->resv_tx_rings && 4673 (!(bp->flags & BNXT_FLAG_NEW_RM) || 4674 (rx == hw_resc->resv_rx_rings && 4675 grp == hw_resc->resv_hw_ring_grps && 4676 cp == hw_resc->resv_cp_rings && vnic == hw_resc->resv_vnics))) 4677 return 0; 4678 4679 rc = bnxt_hwrm_reserve_rings(bp, tx, rx, grp, cp, vnic); 4680 if (rc) 4681 return rc; 4682 4683 tx = hw_resc->resv_tx_rings; 4684 if (bp->flags & BNXT_FLAG_NEW_RM) { 4685 rx = hw_resc->resv_rx_rings; 4686 cp = hw_resc->resv_cp_rings; 4687 grp = hw_resc->resv_hw_ring_grps; 4688 vnic = hw_resc->resv_vnics; 4689 } 4690 4691 rx_rings = rx; 4692 if (bp->flags & BNXT_FLAG_AGG_RINGS) { 4693 if (rx >= 2) { 4694 rx_rings = rx >> 1; 4695 } else { 4696 if (netif_running(bp->dev)) 4697 return -ENOMEM; 4698 4699 bp->flags &= ~BNXT_FLAG_AGG_RINGS; 4700 bp->flags |= BNXT_FLAG_NO_AGG_RINGS; 4701 bp->dev->hw_features &= ~NETIF_F_LRO; 4702 bp->dev->features &= ~NETIF_F_LRO; 4703 bnxt_set_ring_params(bp); 4704 } 4705 } 4706 rx_rings = min_t(int, rx_rings, grp); 4707 rc = bnxt_trim_rings(bp, &rx_rings, &tx, cp, sh); 4708 if (bp->flags & BNXT_FLAG_AGG_RINGS) 4709 rx = rx_rings << 1; 4710 cp = sh ? max_t(int, tx, rx_rings) : tx + rx_rings; 4711 bp->tx_nr_rings = tx; 4712 bp->rx_nr_rings = rx_rings; 4713 bp->cp_nr_rings = cp; 4714 4715 if (!tx || !rx || !cp || !grp || !vnic) 4716 return -ENOMEM; 4717 4718 return rc; 4719 } 4720 4721 static bool bnxt_need_reserve_rings(struct bnxt *bp) 4722 { 4723 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 4724 int rx = bp->rx_nr_rings; 4725 int vnic = 1; 4726 4727 if (bp->hwrm_spec_code < 0x10601) 4728 return false; 4729 4730 if (hw_resc->resv_tx_rings != bp->tx_nr_rings) 4731 return true; 4732 4733 if (bp->flags & BNXT_FLAG_RFS) 4734 vnic = rx + 1; 4735 if (bp->flags & BNXT_FLAG_AGG_RINGS) 4736 rx <<= 1; 4737 if ((bp->flags & BNXT_FLAG_NEW_RM) && 4738 (hw_resc->resv_rx_rings != rx || 4739 hw_resc->resv_cp_rings != bp->cp_nr_rings || 4740 hw_resc->resv_vnics != vnic)) 4741 return true; 4742 return false; 4743 } 4744 4745 static int bnxt_hwrm_check_vf_rings(struct bnxt *bp, int tx_rings, int rx_rings, 4746 int ring_grps, int cp_rings) 4747 { 4748 struct hwrm_func_vf_cfg_input req = {0}; 4749 u32 flags, enables; 4750 int rc; 4751 4752 if (!(bp->flags & BNXT_FLAG_NEW_RM)) 4753 return 0; 4754 4755 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_VF_CFG, -1, -1); 4756 flags = FUNC_VF_CFG_REQ_FLAGS_TX_ASSETS_TEST | 4757 FUNC_VF_CFG_REQ_FLAGS_RX_ASSETS_TEST | 4758 FUNC_VF_CFG_REQ_FLAGS_CMPL_ASSETS_TEST | 4759 FUNC_VF_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST | 4760 FUNC_VF_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST | 4761 FUNC_VF_CFG_REQ_FLAGS_VNIC_ASSETS_TEST; 4762 enables = FUNC_VF_CFG_REQ_ENABLES_NUM_TX_RINGS | 4763 FUNC_VF_CFG_REQ_ENABLES_NUM_RX_RINGS | 4764 FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS | 4765 FUNC_VF_CFG_REQ_ENABLES_NUM_HW_RING_GRPS | 4766 FUNC_VF_CFG_REQ_ENABLES_NUM_STAT_CTXS | 4767 FUNC_VF_CFG_REQ_ENABLES_NUM_VNICS; 4768 4769 req.flags = cpu_to_le32(flags); 4770 req.enables = cpu_to_le32(enables); 4771 req.num_tx_rings = cpu_to_le16(tx_rings); 4772 req.num_rx_rings = cpu_to_le16(rx_rings); 4773 req.num_cmpl_rings = cpu_to_le16(cp_rings); 4774 req.num_hw_ring_grps = cpu_to_le16(ring_grps); 4775 req.num_stat_ctxs = cpu_to_le16(cp_rings); 4776 req.num_vnics = cpu_to_le16(1); 4777 if (bp->flags & BNXT_FLAG_RFS) 4778 req.num_vnics = cpu_to_le16(rx_rings + 1); 4779 rc = hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4780 if (rc) 4781 return -ENOMEM; 4782 return 0; 4783 } 4784 4785 static int bnxt_hwrm_check_pf_rings(struct bnxt *bp, int tx_rings, int rx_rings, 4786 int ring_grps, int cp_rings) 4787 { 4788 struct hwrm_func_cfg_input req = {0}; 4789 u32 flags, enables; 4790 int rc; 4791 4792 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1); 4793 req.fid = cpu_to_le16(0xffff); 4794 flags = FUNC_CFG_REQ_FLAGS_TX_ASSETS_TEST; 4795 enables = FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS; 4796 req.num_tx_rings = cpu_to_le16(tx_rings); 4797 if (bp->flags & BNXT_FLAG_NEW_RM) { 4798 flags |= FUNC_CFG_REQ_FLAGS_RX_ASSETS_TEST | 4799 FUNC_CFG_REQ_FLAGS_CMPL_ASSETS_TEST | 4800 FUNC_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST | 4801 FUNC_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST | 4802 FUNC_CFG_REQ_FLAGS_VNIC_ASSETS_TEST; 4803 enables |= FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS | 4804 FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS | 4805 FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS | 4806 FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS | 4807 FUNC_CFG_REQ_ENABLES_NUM_VNICS; 4808 req.num_rx_rings = cpu_to_le16(rx_rings); 4809 req.num_cmpl_rings = cpu_to_le16(cp_rings); 4810 req.num_hw_ring_grps = cpu_to_le16(ring_grps); 4811 req.num_stat_ctxs = cpu_to_le16(cp_rings); 4812 req.num_vnics = cpu_to_le16(1); 4813 if (bp->flags & BNXT_FLAG_RFS) 4814 req.num_vnics = cpu_to_le16(rx_rings + 1); 4815 } 4816 req.flags = cpu_to_le32(flags); 4817 req.enables = cpu_to_le32(enables); 4818 rc = hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4819 if (rc) 4820 return -ENOMEM; 4821 return 0; 4822 } 4823 4824 static int bnxt_hwrm_check_rings(struct bnxt *bp, int tx_rings, int rx_rings, 4825 int ring_grps, int cp_rings) 4826 { 4827 if (bp->hwrm_spec_code < 0x10801) 4828 return 0; 4829 4830 if (BNXT_PF(bp)) 4831 return bnxt_hwrm_check_pf_rings(bp, tx_rings, rx_rings, 4832 ring_grps, cp_rings); 4833 4834 return bnxt_hwrm_check_vf_rings(bp, tx_rings, rx_rings, ring_grps, 4835 cp_rings); 4836 } 4837 4838 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal, 4839 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req) 4840 { 4841 u16 val, tmr, max, flags; 4842 4843 max = hw_coal->bufs_per_record * 128; 4844 if (hw_coal->budget) 4845 max = hw_coal->bufs_per_record * hw_coal->budget; 4846 4847 val = clamp_t(u16, hw_coal->coal_bufs, 1, max); 4848 req->num_cmpl_aggr_int = cpu_to_le16(val); 4849 4850 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */ 4851 val = min_t(u16, val, 63); 4852 req->num_cmpl_dma_aggr = cpu_to_le16(val); 4853 4854 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */ 4855 val = clamp_t(u16, hw_coal->coal_bufs_irq, 1, 63); 4856 req->num_cmpl_dma_aggr_during_int = cpu_to_le16(val); 4857 4858 tmr = BNXT_USEC_TO_COAL_TIMER(hw_coal->coal_ticks); 4859 tmr = max_t(u16, tmr, 1); 4860 req->int_lat_tmr_max = cpu_to_le16(tmr); 4861 4862 /* min timer set to 1/2 of interrupt timer */ 4863 val = tmr / 2; 4864 req->int_lat_tmr_min = cpu_to_le16(val); 4865 4866 /* buf timer set to 1/4 of interrupt timer */ 4867 val = max_t(u16, tmr / 4, 1); 4868 req->cmpl_aggr_dma_tmr = cpu_to_le16(val); 4869 4870 tmr = BNXT_USEC_TO_COAL_TIMER(hw_coal->coal_ticks_irq); 4871 tmr = max_t(u16, tmr, 1); 4872 req->cmpl_aggr_dma_tmr_during_int = cpu_to_le16(tmr); 4873 4874 flags = RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET; 4875 if (hw_coal->idle_thresh && hw_coal->coal_ticks < hw_coal->idle_thresh) 4876 flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE; 4877 req->flags = cpu_to_le16(flags); 4878 } 4879 4880 int bnxt_hwrm_set_ring_coal(struct bnxt *bp, struct bnxt_napi *bnapi) 4881 { 4882 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx = {0}; 4883 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 4884 struct bnxt_coal coal; 4885 unsigned int grp_idx; 4886 4887 /* Tick values in micro seconds. 4888 * 1 coal_buf x bufs_per_record = 1 completion record. 4889 */ 4890 memcpy(&coal, &bp->rx_coal, sizeof(struct bnxt_coal)); 4891 4892 coal.coal_ticks = cpr->rx_ring_coal.coal_ticks; 4893 coal.coal_bufs = cpr->rx_ring_coal.coal_bufs; 4894 4895 if (!bnapi->rx_ring) 4896 return -ENODEV; 4897 4898 bnxt_hwrm_cmd_hdr_init(bp, &req_rx, 4899 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1); 4900 4901 bnxt_hwrm_set_coal_params(&coal, &req_rx); 4902 4903 grp_idx = bnapi->index; 4904 req_rx.ring_id = cpu_to_le16(bp->grp_info[grp_idx].cp_fw_ring_id); 4905 4906 return hwrm_send_message(bp, &req_rx, sizeof(req_rx), 4907 HWRM_CMD_TIMEOUT); 4908 } 4909 4910 int bnxt_hwrm_set_coal(struct bnxt *bp) 4911 { 4912 int i, rc = 0; 4913 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx = {0}, 4914 req_tx = {0}, *req; 4915 4916 bnxt_hwrm_cmd_hdr_init(bp, &req_rx, 4917 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1); 4918 bnxt_hwrm_cmd_hdr_init(bp, &req_tx, 4919 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1); 4920 4921 bnxt_hwrm_set_coal_params(&bp->rx_coal, &req_rx); 4922 bnxt_hwrm_set_coal_params(&bp->tx_coal, &req_tx); 4923 4924 mutex_lock(&bp->hwrm_cmd_lock); 4925 for (i = 0; i < bp->cp_nr_rings; i++) { 4926 struct bnxt_napi *bnapi = bp->bnapi[i]; 4927 4928 req = &req_rx; 4929 if (!bnapi->rx_ring) 4930 req = &req_tx; 4931 req->ring_id = cpu_to_le16(bp->grp_info[i].cp_fw_ring_id); 4932 4933 rc = _hwrm_send_message(bp, req, sizeof(*req), 4934 HWRM_CMD_TIMEOUT); 4935 if (rc) 4936 break; 4937 } 4938 mutex_unlock(&bp->hwrm_cmd_lock); 4939 return rc; 4940 } 4941 4942 static int bnxt_hwrm_stat_ctx_free(struct bnxt *bp) 4943 { 4944 int rc = 0, i; 4945 struct hwrm_stat_ctx_free_input req = {0}; 4946 4947 if (!bp->bnapi) 4948 return 0; 4949 4950 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 4951 return 0; 4952 4953 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_FREE, -1, -1); 4954 4955 mutex_lock(&bp->hwrm_cmd_lock); 4956 for (i = 0; i < bp->cp_nr_rings; i++) { 4957 struct bnxt_napi *bnapi = bp->bnapi[i]; 4958 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 4959 4960 if (cpr->hw_stats_ctx_id != INVALID_STATS_CTX_ID) { 4961 req.stat_ctx_id = cpu_to_le32(cpr->hw_stats_ctx_id); 4962 4963 rc = _hwrm_send_message(bp, &req, sizeof(req), 4964 HWRM_CMD_TIMEOUT); 4965 if (rc) 4966 break; 4967 4968 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID; 4969 } 4970 } 4971 mutex_unlock(&bp->hwrm_cmd_lock); 4972 return rc; 4973 } 4974 4975 static int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp) 4976 { 4977 int rc = 0, i; 4978 struct hwrm_stat_ctx_alloc_input req = {0}; 4979 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr; 4980 4981 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 4982 return 0; 4983 4984 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_ALLOC, -1, -1); 4985 4986 req.update_period_ms = cpu_to_le32(bp->stats_coal_ticks / 1000); 4987 4988 mutex_lock(&bp->hwrm_cmd_lock); 4989 for (i = 0; i < bp->cp_nr_rings; i++) { 4990 struct bnxt_napi *bnapi = bp->bnapi[i]; 4991 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 4992 4993 req.stats_dma_addr = cpu_to_le64(cpr->hw_stats_map); 4994 4995 rc = _hwrm_send_message(bp, &req, sizeof(req), 4996 HWRM_CMD_TIMEOUT); 4997 if (rc) 4998 break; 4999 5000 cpr->hw_stats_ctx_id = le32_to_cpu(resp->stat_ctx_id); 5001 5002 bp->grp_info[i].fw_stats_ctx = cpr->hw_stats_ctx_id; 5003 } 5004 mutex_unlock(&bp->hwrm_cmd_lock); 5005 return rc; 5006 } 5007 5008 static int bnxt_hwrm_func_qcfg(struct bnxt *bp) 5009 { 5010 struct hwrm_func_qcfg_input req = {0}; 5011 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr; 5012 u16 flags; 5013 int rc; 5014 5015 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1); 5016 req.fid = cpu_to_le16(0xffff); 5017 mutex_lock(&bp->hwrm_cmd_lock); 5018 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5019 if (rc) 5020 goto func_qcfg_exit; 5021 5022 #ifdef CONFIG_BNXT_SRIOV 5023 if (BNXT_VF(bp)) { 5024 struct bnxt_vf_info *vf = &bp->vf; 5025 5026 vf->vlan = le16_to_cpu(resp->vlan) & VLAN_VID_MASK; 5027 } 5028 #endif 5029 flags = le16_to_cpu(resp->flags); 5030 if (flags & (FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED | 5031 FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED)) { 5032 bp->flags |= BNXT_FLAG_FW_LLDP_AGENT; 5033 if (flags & FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED) 5034 bp->flags |= BNXT_FLAG_FW_DCBX_AGENT; 5035 } 5036 if (BNXT_PF(bp) && (flags & FUNC_QCFG_RESP_FLAGS_MULTI_HOST)) 5037 bp->flags |= BNXT_FLAG_MULTI_HOST; 5038 5039 switch (resp->port_partition_type) { 5040 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0: 5041 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5: 5042 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0: 5043 bp->port_partition_type = resp->port_partition_type; 5044 break; 5045 } 5046 if (bp->hwrm_spec_code < 0x10707 || 5047 resp->evb_mode == FUNC_QCFG_RESP_EVB_MODE_VEB) 5048 bp->br_mode = BRIDGE_MODE_VEB; 5049 else if (resp->evb_mode == FUNC_QCFG_RESP_EVB_MODE_VEPA) 5050 bp->br_mode = BRIDGE_MODE_VEPA; 5051 else 5052 bp->br_mode = BRIDGE_MODE_UNDEF; 5053 5054 bp->max_mtu = le16_to_cpu(resp->max_mtu_configured); 5055 if (!bp->max_mtu) 5056 bp->max_mtu = BNXT_MAX_MTU; 5057 5058 func_qcfg_exit: 5059 mutex_unlock(&bp->hwrm_cmd_lock); 5060 return rc; 5061 } 5062 5063 static int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp) 5064 { 5065 struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr; 5066 struct hwrm_func_resource_qcaps_input req = {0}; 5067 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 5068 int rc; 5069 5070 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESOURCE_QCAPS, -1, -1); 5071 req.fid = cpu_to_le16(0xffff); 5072 5073 mutex_lock(&bp->hwrm_cmd_lock); 5074 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5075 if (rc) { 5076 rc = -EIO; 5077 goto hwrm_func_resc_qcaps_exit; 5078 } 5079 5080 hw_resc->min_rsscos_ctxs = le16_to_cpu(resp->min_rsscos_ctx); 5081 hw_resc->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx); 5082 hw_resc->min_cp_rings = le16_to_cpu(resp->min_cmpl_rings); 5083 hw_resc->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings); 5084 hw_resc->min_tx_rings = le16_to_cpu(resp->min_tx_rings); 5085 hw_resc->max_tx_rings = le16_to_cpu(resp->max_tx_rings); 5086 hw_resc->min_rx_rings = le16_to_cpu(resp->min_rx_rings); 5087 hw_resc->max_rx_rings = le16_to_cpu(resp->max_rx_rings); 5088 hw_resc->min_hw_ring_grps = le16_to_cpu(resp->min_hw_ring_grps); 5089 hw_resc->max_hw_ring_grps = le16_to_cpu(resp->max_hw_ring_grps); 5090 hw_resc->min_l2_ctxs = le16_to_cpu(resp->min_l2_ctxs); 5091 hw_resc->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs); 5092 hw_resc->min_vnics = le16_to_cpu(resp->min_vnics); 5093 hw_resc->max_vnics = le16_to_cpu(resp->max_vnics); 5094 hw_resc->min_stat_ctxs = le16_to_cpu(resp->min_stat_ctx); 5095 hw_resc->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx); 5096 5097 if (BNXT_PF(bp)) { 5098 struct bnxt_pf_info *pf = &bp->pf; 5099 5100 pf->vf_resv_strategy = 5101 le16_to_cpu(resp->vf_reservation_strategy); 5102 if (pf->vf_resv_strategy > BNXT_VF_RESV_STRATEGY_MINIMAL) 5103 pf->vf_resv_strategy = BNXT_VF_RESV_STRATEGY_MAXIMAL; 5104 } 5105 hwrm_func_resc_qcaps_exit: 5106 mutex_unlock(&bp->hwrm_cmd_lock); 5107 return rc; 5108 } 5109 5110 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp) 5111 { 5112 int rc = 0; 5113 struct hwrm_func_qcaps_input req = {0}; 5114 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr; 5115 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 5116 u32 flags; 5117 5118 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCAPS, -1, -1); 5119 req.fid = cpu_to_le16(0xffff); 5120 5121 mutex_lock(&bp->hwrm_cmd_lock); 5122 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5123 if (rc) 5124 goto hwrm_func_qcaps_exit; 5125 5126 flags = le32_to_cpu(resp->flags); 5127 if (flags & FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED) 5128 bp->flags |= BNXT_FLAG_ROCEV1_CAP; 5129 if (flags & FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED) 5130 bp->flags |= BNXT_FLAG_ROCEV2_CAP; 5131 5132 bp->tx_push_thresh = 0; 5133 if (flags & FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED) 5134 bp->tx_push_thresh = BNXT_TX_PUSH_THRESH; 5135 5136 hw_resc->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx); 5137 hw_resc->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings); 5138 hw_resc->max_tx_rings = le16_to_cpu(resp->max_tx_rings); 5139 hw_resc->max_rx_rings = le16_to_cpu(resp->max_rx_rings); 5140 hw_resc->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps); 5141 if (!hw_resc->max_hw_ring_grps) 5142 hw_resc->max_hw_ring_grps = hw_resc->max_tx_rings; 5143 hw_resc->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs); 5144 hw_resc->max_vnics = le16_to_cpu(resp->max_vnics); 5145 hw_resc->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx); 5146 5147 if (BNXT_PF(bp)) { 5148 struct bnxt_pf_info *pf = &bp->pf; 5149 5150 pf->fw_fid = le16_to_cpu(resp->fid); 5151 pf->port_id = le16_to_cpu(resp->port_id); 5152 bp->dev->dev_port = pf->port_id; 5153 memcpy(pf->mac_addr, resp->mac_address, ETH_ALEN); 5154 pf->first_vf_id = le16_to_cpu(resp->first_vf_id); 5155 pf->max_vfs = le16_to_cpu(resp->max_vfs); 5156 pf->max_encap_records = le32_to_cpu(resp->max_encap_records); 5157 pf->max_decap_records = le32_to_cpu(resp->max_decap_records); 5158 pf->max_tx_em_flows = le32_to_cpu(resp->max_tx_em_flows); 5159 pf->max_tx_wm_flows = le32_to_cpu(resp->max_tx_wm_flows); 5160 pf->max_rx_em_flows = le32_to_cpu(resp->max_rx_em_flows); 5161 pf->max_rx_wm_flows = le32_to_cpu(resp->max_rx_wm_flows); 5162 if (flags & FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED) 5163 bp->flags |= BNXT_FLAG_WOL_CAP; 5164 } else { 5165 #ifdef CONFIG_BNXT_SRIOV 5166 struct bnxt_vf_info *vf = &bp->vf; 5167 5168 vf->fw_fid = le16_to_cpu(resp->fid); 5169 memcpy(vf->mac_addr, resp->mac_address, ETH_ALEN); 5170 #endif 5171 } 5172 5173 hwrm_func_qcaps_exit: 5174 mutex_unlock(&bp->hwrm_cmd_lock); 5175 return rc; 5176 } 5177 5178 static int bnxt_hwrm_func_qcaps(struct bnxt *bp) 5179 { 5180 int rc; 5181 5182 rc = __bnxt_hwrm_func_qcaps(bp); 5183 if (rc) 5184 return rc; 5185 if (bp->hwrm_spec_code >= 0x10803) { 5186 rc = bnxt_hwrm_func_resc_qcaps(bp); 5187 if (!rc) 5188 bp->flags |= BNXT_FLAG_NEW_RM; 5189 } 5190 return 0; 5191 } 5192 5193 static int bnxt_hwrm_func_reset(struct bnxt *bp) 5194 { 5195 struct hwrm_func_reset_input req = {0}; 5196 5197 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESET, -1, -1); 5198 req.enables = 0; 5199 5200 return hwrm_send_message(bp, &req, sizeof(req), HWRM_RESET_TIMEOUT); 5201 } 5202 5203 static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp) 5204 { 5205 int rc = 0; 5206 struct hwrm_queue_qportcfg_input req = {0}; 5207 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr; 5208 u8 i, *qptr; 5209 5210 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_QUEUE_QPORTCFG, -1, -1); 5211 5212 mutex_lock(&bp->hwrm_cmd_lock); 5213 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5214 if (rc) 5215 goto qportcfg_exit; 5216 5217 if (!resp->max_configurable_queues) { 5218 rc = -EINVAL; 5219 goto qportcfg_exit; 5220 } 5221 bp->max_tc = resp->max_configurable_queues; 5222 bp->max_lltc = resp->max_configurable_lossless_queues; 5223 if (bp->max_tc > BNXT_MAX_QUEUE) 5224 bp->max_tc = BNXT_MAX_QUEUE; 5225 5226 if (resp->queue_cfg_info & QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG) 5227 bp->max_tc = 1; 5228 5229 if (bp->max_lltc > bp->max_tc) 5230 bp->max_lltc = bp->max_tc; 5231 5232 qptr = &resp->queue_id0; 5233 for (i = 0; i < bp->max_tc; i++) { 5234 bp->q_info[i].queue_id = *qptr++; 5235 bp->q_info[i].queue_profile = *qptr++; 5236 } 5237 5238 qportcfg_exit: 5239 mutex_unlock(&bp->hwrm_cmd_lock); 5240 return rc; 5241 } 5242 5243 static int bnxt_hwrm_ver_get(struct bnxt *bp) 5244 { 5245 int rc; 5246 struct hwrm_ver_get_input req = {0}; 5247 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr; 5248 u32 dev_caps_cfg; 5249 5250 bp->hwrm_max_req_len = HWRM_MAX_REQ_LEN; 5251 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VER_GET, -1, -1); 5252 req.hwrm_intf_maj = HWRM_VERSION_MAJOR; 5253 req.hwrm_intf_min = HWRM_VERSION_MINOR; 5254 req.hwrm_intf_upd = HWRM_VERSION_UPDATE; 5255 mutex_lock(&bp->hwrm_cmd_lock); 5256 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5257 if (rc) 5258 goto hwrm_ver_get_exit; 5259 5260 memcpy(&bp->ver_resp, resp, sizeof(struct hwrm_ver_get_output)); 5261 5262 bp->hwrm_spec_code = resp->hwrm_intf_maj_8b << 16 | 5263 resp->hwrm_intf_min_8b << 8 | 5264 resp->hwrm_intf_upd_8b; 5265 if (resp->hwrm_intf_maj_8b < 1) { 5266 netdev_warn(bp->dev, "HWRM interface %d.%d.%d is older than 1.0.0.\n", 5267 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b, 5268 resp->hwrm_intf_upd_8b); 5269 netdev_warn(bp->dev, "Please update firmware with HWRM interface 1.0.0 or newer.\n"); 5270 } 5271 snprintf(bp->fw_ver_str, BC_HWRM_STR_LEN, "%d.%d.%d.%d", 5272 resp->hwrm_fw_maj_8b, resp->hwrm_fw_min_8b, 5273 resp->hwrm_fw_bld_8b, resp->hwrm_fw_rsvd_8b); 5274 5275 bp->hwrm_cmd_timeout = le16_to_cpu(resp->def_req_timeout); 5276 if (!bp->hwrm_cmd_timeout) 5277 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT; 5278 5279 if (resp->hwrm_intf_maj_8b >= 1) 5280 bp->hwrm_max_req_len = le16_to_cpu(resp->max_req_win_len); 5281 5282 bp->chip_num = le16_to_cpu(resp->chip_num); 5283 if (bp->chip_num == CHIP_NUM_58700 && !resp->chip_rev && 5284 !resp->chip_metal) 5285 bp->flags |= BNXT_FLAG_CHIP_NITRO_A0; 5286 5287 dev_caps_cfg = le32_to_cpu(resp->dev_caps_cfg); 5288 if ((dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) && 5289 (dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) 5290 bp->flags |= BNXT_FLAG_SHORT_CMD; 5291 5292 hwrm_ver_get_exit: 5293 mutex_unlock(&bp->hwrm_cmd_lock); 5294 return rc; 5295 } 5296 5297 int bnxt_hwrm_fw_set_time(struct bnxt *bp) 5298 { 5299 struct hwrm_fw_set_time_input req = {0}; 5300 struct tm tm; 5301 time64_t now = ktime_get_real_seconds(); 5302 5303 if (bp->hwrm_spec_code < 0x10400) 5304 return -EOPNOTSUPP; 5305 5306 time64_to_tm(now, 0, &tm); 5307 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FW_SET_TIME, -1, -1); 5308 req.year = cpu_to_le16(1900 + tm.tm_year); 5309 req.month = 1 + tm.tm_mon; 5310 req.day = tm.tm_mday; 5311 req.hour = tm.tm_hour; 5312 req.minute = tm.tm_min; 5313 req.second = tm.tm_sec; 5314 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5315 } 5316 5317 static int bnxt_hwrm_port_qstats(struct bnxt *bp) 5318 { 5319 int rc; 5320 struct bnxt_pf_info *pf = &bp->pf; 5321 struct hwrm_port_qstats_input req = {0}; 5322 5323 if (!(bp->flags & BNXT_FLAG_PORT_STATS)) 5324 return 0; 5325 5326 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_QSTATS, -1, -1); 5327 req.port_id = cpu_to_le16(pf->port_id); 5328 req.tx_stat_host_addr = cpu_to_le64(bp->hw_tx_port_stats_map); 5329 req.rx_stat_host_addr = cpu_to_le64(bp->hw_rx_port_stats_map); 5330 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5331 return rc; 5332 } 5333 5334 static void bnxt_hwrm_free_tunnel_ports(struct bnxt *bp) 5335 { 5336 if (bp->vxlan_port_cnt) { 5337 bnxt_hwrm_tunnel_dst_port_free( 5338 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN); 5339 } 5340 bp->vxlan_port_cnt = 0; 5341 if (bp->nge_port_cnt) { 5342 bnxt_hwrm_tunnel_dst_port_free( 5343 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE); 5344 } 5345 bp->nge_port_cnt = 0; 5346 } 5347 5348 static int bnxt_set_tpa(struct bnxt *bp, bool set_tpa) 5349 { 5350 int rc, i; 5351 u32 tpa_flags = 0; 5352 5353 if (set_tpa) 5354 tpa_flags = bp->flags & BNXT_FLAG_TPA; 5355 for (i = 0; i < bp->nr_vnics; i++) { 5356 rc = bnxt_hwrm_vnic_set_tpa(bp, i, tpa_flags); 5357 if (rc) { 5358 netdev_err(bp->dev, "hwrm vnic set tpa failure rc for vnic %d: %x\n", 5359 i, rc); 5360 return rc; 5361 } 5362 } 5363 return 0; 5364 } 5365 5366 static void bnxt_hwrm_clear_vnic_rss(struct bnxt *bp) 5367 { 5368 int i; 5369 5370 for (i = 0; i < bp->nr_vnics; i++) 5371 bnxt_hwrm_vnic_set_rss(bp, i, false); 5372 } 5373 5374 static void bnxt_hwrm_resource_free(struct bnxt *bp, bool close_path, 5375 bool irq_re_init) 5376 { 5377 if (bp->vnic_info) { 5378 bnxt_hwrm_clear_vnic_filter(bp); 5379 /* clear all RSS setting before free vnic ctx */ 5380 bnxt_hwrm_clear_vnic_rss(bp); 5381 bnxt_hwrm_vnic_ctx_free(bp); 5382 /* before free the vnic, undo the vnic tpa settings */ 5383 if (bp->flags & BNXT_FLAG_TPA) 5384 bnxt_set_tpa(bp, false); 5385 bnxt_hwrm_vnic_free(bp); 5386 } 5387 bnxt_hwrm_ring_free(bp, close_path); 5388 bnxt_hwrm_ring_grp_free(bp); 5389 if (irq_re_init) { 5390 bnxt_hwrm_stat_ctx_free(bp); 5391 bnxt_hwrm_free_tunnel_ports(bp); 5392 } 5393 } 5394 5395 static int bnxt_hwrm_set_br_mode(struct bnxt *bp, u16 br_mode) 5396 { 5397 struct hwrm_func_cfg_input req = {0}; 5398 int rc; 5399 5400 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1); 5401 req.fid = cpu_to_le16(0xffff); 5402 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_EVB_MODE); 5403 if (br_mode == BRIDGE_MODE_VEB) 5404 req.evb_mode = FUNC_CFG_REQ_EVB_MODE_VEB; 5405 else if (br_mode == BRIDGE_MODE_VEPA) 5406 req.evb_mode = FUNC_CFG_REQ_EVB_MODE_VEPA; 5407 else 5408 return -EINVAL; 5409 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5410 if (rc) 5411 rc = -EIO; 5412 return rc; 5413 } 5414 5415 static int bnxt_hwrm_set_cache_line_size(struct bnxt *bp, int size) 5416 { 5417 struct hwrm_func_cfg_input req = {0}; 5418 int rc; 5419 5420 if (BNXT_VF(bp) || bp->hwrm_spec_code < 0x10803) 5421 return 0; 5422 5423 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1); 5424 req.fid = cpu_to_le16(0xffff); 5425 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_CACHE_LINESIZE); 5426 req.cache_linesize = FUNC_QCFG_RESP_CACHE_LINESIZE_CACHE_LINESIZE_64; 5427 if (size == 128) 5428 req.cache_linesize = 5429 FUNC_QCFG_RESP_CACHE_LINESIZE_CACHE_LINESIZE_128; 5430 5431 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5432 if (rc) 5433 rc = -EIO; 5434 return rc; 5435 } 5436 5437 static int bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id) 5438 { 5439 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 5440 int rc; 5441 5442 if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG) 5443 goto skip_rss_ctx; 5444 5445 /* allocate context for vnic */ 5446 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 0); 5447 if (rc) { 5448 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n", 5449 vnic_id, rc); 5450 goto vnic_setup_err; 5451 } 5452 bp->rsscos_nr_ctxs++; 5453 5454 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) { 5455 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 1); 5456 if (rc) { 5457 netdev_err(bp->dev, "hwrm vnic %d cos ctx alloc failure rc: %x\n", 5458 vnic_id, rc); 5459 goto vnic_setup_err; 5460 } 5461 bp->rsscos_nr_ctxs++; 5462 } 5463 5464 skip_rss_ctx: 5465 /* configure default vnic, ring grp */ 5466 rc = bnxt_hwrm_vnic_cfg(bp, vnic_id); 5467 if (rc) { 5468 netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n", 5469 vnic_id, rc); 5470 goto vnic_setup_err; 5471 } 5472 5473 /* Enable RSS hashing on vnic */ 5474 rc = bnxt_hwrm_vnic_set_rss(bp, vnic_id, true); 5475 if (rc) { 5476 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %x\n", 5477 vnic_id, rc); 5478 goto vnic_setup_err; 5479 } 5480 5481 if (bp->flags & BNXT_FLAG_AGG_RINGS) { 5482 rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id); 5483 if (rc) { 5484 netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n", 5485 vnic_id, rc); 5486 } 5487 } 5488 5489 vnic_setup_err: 5490 return rc; 5491 } 5492 5493 static int bnxt_alloc_rfs_vnics(struct bnxt *bp) 5494 { 5495 #ifdef CONFIG_RFS_ACCEL 5496 int i, rc = 0; 5497 5498 for (i = 0; i < bp->rx_nr_rings; i++) { 5499 struct bnxt_vnic_info *vnic; 5500 u16 vnic_id = i + 1; 5501 u16 ring_id = i; 5502 5503 if (vnic_id >= bp->nr_vnics) 5504 break; 5505 5506 vnic = &bp->vnic_info[vnic_id]; 5507 vnic->flags |= BNXT_VNIC_RFS_FLAG; 5508 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP) 5509 vnic->flags |= BNXT_VNIC_RFS_NEW_RSS_FLAG; 5510 rc = bnxt_hwrm_vnic_alloc(bp, vnic_id, ring_id, 1); 5511 if (rc) { 5512 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n", 5513 vnic_id, rc); 5514 break; 5515 } 5516 rc = bnxt_setup_vnic(bp, vnic_id); 5517 if (rc) 5518 break; 5519 } 5520 return rc; 5521 #else 5522 return 0; 5523 #endif 5524 } 5525 5526 /* Allow PF and VF with default VLAN to be in promiscuous mode */ 5527 static bool bnxt_promisc_ok(struct bnxt *bp) 5528 { 5529 #ifdef CONFIG_BNXT_SRIOV 5530 if (BNXT_VF(bp) && !bp->vf.vlan) 5531 return false; 5532 #endif 5533 return true; 5534 } 5535 5536 static int bnxt_setup_nitroa0_vnic(struct bnxt *bp) 5537 { 5538 unsigned int rc = 0; 5539 5540 rc = bnxt_hwrm_vnic_alloc(bp, 1, bp->rx_nr_rings - 1, 1); 5541 if (rc) { 5542 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n", 5543 rc); 5544 return rc; 5545 } 5546 5547 rc = bnxt_hwrm_vnic_cfg(bp, 1); 5548 if (rc) { 5549 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n", 5550 rc); 5551 return rc; 5552 } 5553 return rc; 5554 } 5555 5556 static int bnxt_cfg_rx_mode(struct bnxt *); 5557 static bool bnxt_mc_list_updated(struct bnxt *, u32 *); 5558 5559 static int bnxt_init_chip(struct bnxt *bp, bool irq_re_init) 5560 { 5561 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 5562 int rc = 0; 5563 unsigned int rx_nr_rings = bp->rx_nr_rings; 5564 5565 if (irq_re_init) { 5566 rc = bnxt_hwrm_stat_ctx_alloc(bp); 5567 if (rc) { 5568 netdev_err(bp->dev, "hwrm stat ctx alloc failure rc: %x\n", 5569 rc); 5570 goto err_out; 5571 } 5572 } 5573 5574 rc = bnxt_hwrm_ring_alloc(bp); 5575 if (rc) { 5576 netdev_err(bp->dev, "hwrm ring alloc failure rc: %x\n", rc); 5577 goto err_out; 5578 } 5579 5580 rc = bnxt_hwrm_ring_grp_alloc(bp); 5581 if (rc) { 5582 netdev_err(bp->dev, "hwrm_ring_grp alloc failure: %x\n", rc); 5583 goto err_out; 5584 } 5585 5586 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 5587 rx_nr_rings--; 5588 5589 /* default vnic 0 */ 5590 rc = bnxt_hwrm_vnic_alloc(bp, 0, 0, rx_nr_rings); 5591 if (rc) { 5592 netdev_err(bp->dev, "hwrm vnic alloc failure rc: %x\n", rc); 5593 goto err_out; 5594 } 5595 5596 rc = bnxt_setup_vnic(bp, 0); 5597 if (rc) 5598 goto err_out; 5599 5600 if (bp->flags & BNXT_FLAG_RFS) { 5601 rc = bnxt_alloc_rfs_vnics(bp); 5602 if (rc) 5603 goto err_out; 5604 } 5605 5606 if (bp->flags & BNXT_FLAG_TPA) { 5607 rc = bnxt_set_tpa(bp, true); 5608 if (rc) 5609 goto err_out; 5610 } 5611 5612 if (BNXT_VF(bp)) 5613 bnxt_update_vf_mac(bp); 5614 5615 /* Filter for default vnic 0 */ 5616 rc = bnxt_hwrm_set_vnic_filter(bp, 0, 0, bp->dev->dev_addr); 5617 if (rc) { 5618 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n", rc); 5619 goto err_out; 5620 } 5621 vnic->uc_filter_count = 1; 5622 5623 vnic->rx_mask = CFA_L2_SET_RX_MASK_REQ_MASK_BCAST; 5624 5625 if ((bp->dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp)) 5626 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS; 5627 5628 if (bp->dev->flags & IFF_ALLMULTI) { 5629 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST; 5630 vnic->mc_list_count = 0; 5631 } else { 5632 u32 mask = 0; 5633 5634 bnxt_mc_list_updated(bp, &mask); 5635 vnic->rx_mask |= mask; 5636 } 5637 5638 rc = bnxt_cfg_rx_mode(bp); 5639 if (rc) 5640 goto err_out; 5641 5642 rc = bnxt_hwrm_set_coal(bp); 5643 if (rc) 5644 netdev_warn(bp->dev, "HWRM set coalescing failure rc: %x\n", 5645 rc); 5646 5647 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) { 5648 rc = bnxt_setup_nitroa0_vnic(bp); 5649 if (rc) 5650 netdev_err(bp->dev, "Special vnic setup failure for NS2 A0 rc: %x\n", 5651 rc); 5652 } 5653 5654 if (BNXT_VF(bp)) { 5655 bnxt_hwrm_func_qcfg(bp); 5656 netdev_update_features(bp->dev); 5657 } 5658 5659 return 0; 5660 5661 err_out: 5662 bnxt_hwrm_resource_free(bp, 0, true); 5663 5664 return rc; 5665 } 5666 5667 static int bnxt_shutdown_nic(struct bnxt *bp, bool irq_re_init) 5668 { 5669 bnxt_hwrm_resource_free(bp, 1, irq_re_init); 5670 return 0; 5671 } 5672 5673 static int bnxt_init_nic(struct bnxt *bp, bool irq_re_init) 5674 { 5675 bnxt_init_cp_rings(bp); 5676 bnxt_init_rx_rings(bp); 5677 bnxt_init_tx_rings(bp); 5678 bnxt_init_ring_grps(bp, irq_re_init); 5679 bnxt_init_vnics(bp); 5680 5681 return bnxt_init_chip(bp, irq_re_init); 5682 } 5683 5684 static int bnxt_set_real_num_queues(struct bnxt *bp) 5685 { 5686 int rc; 5687 struct net_device *dev = bp->dev; 5688 5689 rc = netif_set_real_num_tx_queues(dev, bp->tx_nr_rings - 5690 bp->tx_nr_rings_xdp); 5691 if (rc) 5692 return rc; 5693 5694 rc = netif_set_real_num_rx_queues(dev, bp->rx_nr_rings); 5695 if (rc) 5696 return rc; 5697 5698 #ifdef CONFIG_RFS_ACCEL 5699 if (bp->flags & BNXT_FLAG_RFS) 5700 dev->rx_cpu_rmap = alloc_irq_cpu_rmap(bp->rx_nr_rings); 5701 #endif 5702 5703 return rc; 5704 } 5705 5706 static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max, 5707 bool shared) 5708 { 5709 int _rx = *rx, _tx = *tx; 5710 5711 if (shared) { 5712 *rx = min_t(int, _rx, max); 5713 *tx = min_t(int, _tx, max); 5714 } else { 5715 if (max < 2) 5716 return -ENOMEM; 5717 5718 while (_rx + _tx > max) { 5719 if (_rx > _tx && _rx > 1) 5720 _rx--; 5721 else if (_tx > 1) 5722 _tx--; 5723 } 5724 *rx = _rx; 5725 *tx = _tx; 5726 } 5727 return 0; 5728 } 5729 5730 static void bnxt_setup_msix(struct bnxt *bp) 5731 { 5732 const int len = sizeof(bp->irq_tbl[0].name); 5733 struct net_device *dev = bp->dev; 5734 int tcs, i; 5735 5736 tcs = netdev_get_num_tc(dev); 5737 if (tcs > 1) { 5738 int i, off, count; 5739 5740 for (i = 0; i < tcs; i++) { 5741 count = bp->tx_nr_rings_per_tc; 5742 off = i * count; 5743 netdev_set_tc_queue(dev, i, count, off); 5744 } 5745 } 5746 5747 for (i = 0; i < bp->cp_nr_rings; i++) { 5748 char *attr; 5749 5750 if (bp->flags & BNXT_FLAG_SHARED_RINGS) 5751 attr = "TxRx"; 5752 else if (i < bp->rx_nr_rings) 5753 attr = "rx"; 5754 else 5755 attr = "tx"; 5756 5757 snprintf(bp->irq_tbl[i].name, len, "%s-%s-%d", dev->name, attr, 5758 i); 5759 bp->irq_tbl[i].handler = bnxt_msix; 5760 } 5761 } 5762 5763 static void bnxt_setup_inta(struct bnxt *bp) 5764 { 5765 const int len = sizeof(bp->irq_tbl[0].name); 5766 5767 if (netdev_get_num_tc(bp->dev)) 5768 netdev_reset_tc(bp->dev); 5769 5770 snprintf(bp->irq_tbl[0].name, len, "%s-%s-%d", bp->dev->name, "TxRx", 5771 0); 5772 bp->irq_tbl[0].handler = bnxt_inta; 5773 } 5774 5775 static int bnxt_setup_int_mode(struct bnxt *bp) 5776 { 5777 int rc; 5778 5779 if (bp->flags & BNXT_FLAG_USING_MSIX) 5780 bnxt_setup_msix(bp); 5781 else 5782 bnxt_setup_inta(bp); 5783 5784 rc = bnxt_set_real_num_queues(bp); 5785 return rc; 5786 } 5787 5788 #ifdef CONFIG_RFS_ACCEL 5789 static unsigned int bnxt_get_max_func_rss_ctxs(struct bnxt *bp) 5790 { 5791 return bp->hw_resc.max_rsscos_ctxs; 5792 } 5793 5794 static unsigned int bnxt_get_max_func_vnics(struct bnxt *bp) 5795 { 5796 return bp->hw_resc.max_vnics; 5797 } 5798 #endif 5799 5800 unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt *bp) 5801 { 5802 return bp->hw_resc.max_stat_ctxs; 5803 } 5804 5805 void bnxt_set_max_func_stat_ctxs(struct bnxt *bp, unsigned int max) 5806 { 5807 bp->hw_resc.max_stat_ctxs = max; 5808 } 5809 5810 unsigned int bnxt_get_max_func_cp_rings(struct bnxt *bp) 5811 { 5812 return bp->hw_resc.max_cp_rings; 5813 } 5814 5815 void bnxt_set_max_func_cp_rings(struct bnxt *bp, unsigned int max) 5816 { 5817 bp->hw_resc.max_cp_rings = max; 5818 } 5819 5820 static unsigned int bnxt_get_max_func_irqs(struct bnxt *bp) 5821 { 5822 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 5823 5824 return min_t(unsigned int, hw_resc->max_irqs, hw_resc->max_cp_rings); 5825 } 5826 5827 void bnxt_set_max_func_irqs(struct bnxt *bp, unsigned int max_irqs) 5828 { 5829 bp->hw_resc.max_irqs = max_irqs; 5830 } 5831 5832 static int bnxt_init_msix(struct bnxt *bp) 5833 { 5834 int i, total_vecs, rc = 0, min = 1; 5835 struct msix_entry *msix_ent; 5836 5837 total_vecs = bnxt_get_max_func_irqs(bp); 5838 msix_ent = kcalloc(total_vecs, sizeof(struct msix_entry), GFP_KERNEL); 5839 if (!msix_ent) 5840 return -ENOMEM; 5841 5842 for (i = 0; i < total_vecs; i++) { 5843 msix_ent[i].entry = i; 5844 msix_ent[i].vector = 0; 5845 } 5846 5847 if (!(bp->flags & BNXT_FLAG_SHARED_RINGS)) 5848 min = 2; 5849 5850 total_vecs = pci_enable_msix_range(bp->pdev, msix_ent, min, total_vecs); 5851 if (total_vecs < 0) { 5852 rc = -ENODEV; 5853 goto msix_setup_exit; 5854 } 5855 5856 bp->irq_tbl = kcalloc(total_vecs, sizeof(struct bnxt_irq), GFP_KERNEL); 5857 if (bp->irq_tbl) { 5858 for (i = 0; i < total_vecs; i++) 5859 bp->irq_tbl[i].vector = msix_ent[i].vector; 5860 5861 bp->total_irqs = total_vecs; 5862 /* Trim rings based upon num of vectors allocated */ 5863 rc = bnxt_trim_rings(bp, &bp->rx_nr_rings, &bp->tx_nr_rings, 5864 total_vecs, min == 1); 5865 if (rc) 5866 goto msix_setup_exit; 5867 5868 bp->tx_nr_rings_per_tc = bp->tx_nr_rings; 5869 bp->cp_nr_rings = (min == 1) ? 5870 max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) : 5871 bp->tx_nr_rings + bp->rx_nr_rings; 5872 5873 } else { 5874 rc = -ENOMEM; 5875 goto msix_setup_exit; 5876 } 5877 bp->flags |= BNXT_FLAG_USING_MSIX; 5878 kfree(msix_ent); 5879 return 0; 5880 5881 msix_setup_exit: 5882 netdev_err(bp->dev, "bnxt_init_msix err: %x\n", rc); 5883 kfree(bp->irq_tbl); 5884 bp->irq_tbl = NULL; 5885 pci_disable_msix(bp->pdev); 5886 kfree(msix_ent); 5887 return rc; 5888 } 5889 5890 static int bnxt_init_inta(struct bnxt *bp) 5891 { 5892 bp->irq_tbl = kcalloc(1, sizeof(struct bnxt_irq), GFP_KERNEL); 5893 if (!bp->irq_tbl) 5894 return -ENOMEM; 5895 5896 bp->total_irqs = 1; 5897 bp->rx_nr_rings = 1; 5898 bp->tx_nr_rings = 1; 5899 bp->cp_nr_rings = 1; 5900 bp->tx_nr_rings_per_tc = bp->tx_nr_rings; 5901 bp->flags |= BNXT_FLAG_SHARED_RINGS; 5902 bp->irq_tbl[0].vector = bp->pdev->irq; 5903 return 0; 5904 } 5905 5906 static int bnxt_init_int_mode(struct bnxt *bp) 5907 { 5908 int rc = 0; 5909 5910 if (bp->flags & BNXT_FLAG_MSIX_CAP) 5911 rc = bnxt_init_msix(bp); 5912 5913 if (!(bp->flags & BNXT_FLAG_USING_MSIX) && BNXT_PF(bp)) { 5914 /* fallback to INTA */ 5915 rc = bnxt_init_inta(bp); 5916 } 5917 return rc; 5918 } 5919 5920 static void bnxt_clear_int_mode(struct bnxt *bp) 5921 { 5922 if (bp->flags & BNXT_FLAG_USING_MSIX) 5923 pci_disable_msix(bp->pdev); 5924 5925 kfree(bp->irq_tbl); 5926 bp->irq_tbl = NULL; 5927 bp->flags &= ~BNXT_FLAG_USING_MSIX; 5928 } 5929 5930 static int bnxt_reserve_rings(struct bnxt *bp) 5931 { 5932 int orig_cp = bp->hw_resc.resv_cp_rings; 5933 int tcs = netdev_get_num_tc(bp->dev); 5934 int rc; 5935 5936 if (!bnxt_need_reserve_rings(bp)) 5937 return 0; 5938 5939 rc = __bnxt_reserve_rings(bp); 5940 if (rc) { 5941 netdev_err(bp->dev, "ring reservation failure rc: %d\n", rc); 5942 return rc; 5943 } 5944 if ((bp->flags & BNXT_FLAG_NEW_RM) && bp->cp_nr_rings > orig_cp) { 5945 bnxt_clear_int_mode(bp); 5946 rc = bnxt_init_int_mode(bp); 5947 if (rc) 5948 return rc; 5949 } 5950 if (tcs && (bp->tx_nr_rings_per_tc * tcs != bp->tx_nr_rings)) { 5951 netdev_err(bp->dev, "tx ring reservation failure\n"); 5952 netdev_reset_tc(bp->dev); 5953 bp->tx_nr_rings_per_tc = bp->tx_nr_rings; 5954 return -ENOMEM; 5955 } 5956 bp->num_stat_ctxs = bp->cp_nr_rings; 5957 return 0; 5958 } 5959 5960 static void bnxt_free_irq(struct bnxt *bp) 5961 { 5962 struct bnxt_irq *irq; 5963 int i; 5964 5965 #ifdef CONFIG_RFS_ACCEL 5966 free_irq_cpu_rmap(bp->dev->rx_cpu_rmap); 5967 bp->dev->rx_cpu_rmap = NULL; 5968 #endif 5969 if (!bp->irq_tbl) 5970 return; 5971 5972 for (i = 0; i < bp->cp_nr_rings; i++) { 5973 irq = &bp->irq_tbl[i]; 5974 if (irq->requested) { 5975 if (irq->have_cpumask) { 5976 irq_set_affinity_hint(irq->vector, NULL); 5977 free_cpumask_var(irq->cpu_mask); 5978 irq->have_cpumask = 0; 5979 } 5980 free_irq(irq->vector, bp->bnapi[i]); 5981 } 5982 5983 irq->requested = 0; 5984 } 5985 } 5986 5987 static int bnxt_request_irq(struct bnxt *bp) 5988 { 5989 int i, j, rc = 0; 5990 unsigned long flags = 0; 5991 #ifdef CONFIG_RFS_ACCEL 5992 struct cpu_rmap *rmap = bp->dev->rx_cpu_rmap; 5993 #endif 5994 5995 if (!(bp->flags & BNXT_FLAG_USING_MSIX)) 5996 flags = IRQF_SHARED; 5997 5998 for (i = 0, j = 0; i < bp->cp_nr_rings; i++) { 5999 struct bnxt_irq *irq = &bp->irq_tbl[i]; 6000 #ifdef CONFIG_RFS_ACCEL 6001 if (rmap && bp->bnapi[i]->rx_ring) { 6002 rc = irq_cpu_rmap_add(rmap, irq->vector); 6003 if (rc) 6004 netdev_warn(bp->dev, "failed adding irq rmap for ring %d\n", 6005 j); 6006 j++; 6007 } 6008 #endif 6009 rc = request_irq(irq->vector, irq->handler, flags, irq->name, 6010 bp->bnapi[i]); 6011 if (rc) 6012 break; 6013 6014 irq->requested = 1; 6015 6016 if (zalloc_cpumask_var(&irq->cpu_mask, GFP_KERNEL)) { 6017 int numa_node = dev_to_node(&bp->pdev->dev); 6018 6019 irq->have_cpumask = 1; 6020 cpumask_set_cpu(cpumask_local_spread(i, numa_node), 6021 irq->cpu_mask); 6022 rc = irq_set_affinity_hint(irq->vector, irq->cpu_mask); 6023 if (rc) { 6024 netdev_warn(bp->dev, 6025 "Set affinity failed, IRQ = %d\n", 6026 irq->vector); 6027 break; 6028 } 6029 } 6030 } 6031 return rc; 6032 } 6033 6034 static void bnxt_del_napi(struct bnxt *bp) 6035 { 6036 int i; 6037 6038 if (!bp->bnapi) 6039 return; 6040 6041 for (i = 0; i < bp->cp_nr_rings; i++) { 6042 struct bnxt_napi *bnapi = bp->bnapi[i]; 6043 6044 napi_hash_del(&bnapi->napi); 6045 netif_napi_del(&bnapi->napi); 6046 } 6047 /* We called napi_hash_del() before netif_napi_del(), we need 6048 * to respect an RCU grace period before freeing napi structures. 6049 */ 6050 synchronize_net(); 6051 } 6052 6053 static void bnxt_init_napi(struct bnxt *bp) 6054 { 6055 int i; 6056 unsigned int cp_nr_rings = bp->cp_nr_rings; 6057 struct bnxt_napi *bnapi; 6058 6059 if (bp->flags & BNXT_FLAG_USING_MSIX) { 6060 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 6061 cp_nr_rings--; 6062 for (i = 0; i < cp_nr_rings; i++) { 6063 bnapi = bp->bnapi[i]; 6064 netif_napi_add(bp->dev, &bnapi->napi, 6065 bnxt_poll, 64); 6066 } 6067 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) { 6068 bnapi = bp->bnapi[cp_nr_rings]; 6069 netif_napi_add(bp->dev, &bnapi->napi, 6070 bnxt_poll_nitroa0, 64); 6071 } 6072 } else { 6073 bnapi = bp->bnapi[0]; 6074 netif_napi_add(bp->dev, &bnapi->napi, bnxt_poll, 64); 6075 } 6076 } 6077 6078 static void bnxt_disable_napi(struct bnxt *bp) 6079 { 6080 int i; 6081 6082 if (!bp->bnapi) 6083 return; 6084 6085 for (i = 0; i < bp->cp_nr_rings; i++) { 6086 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring; 6087 6088 if (bp->bnapi[i]->rx_ring) 6089 cancel_work_sync(&cpr->dim.work); 6090 6091 napi_disable(&bp->bnapi[i]->napi); 6092 } 6093 } 6094 6095 static void bnxt_enable_napi(struct bnxt *bp) 6096 { 6097 int i; 6098 6099 for (i = 0; i < bp->cp_nr_rings; i++) { 6100 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring; 6101 bp->bnapi[i]->in_reset = false; 6102 6103 if (bp->bnapi[i]->rx_ring) { 6104 INIT_WORK(&cpr->dim.work, bnxt_dim_work); 6105 cpr->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE; 6106 } 6107 napi_enable(&bp->bnapi[i]->napi); 6108 } 6109 } 6110 6111 void bnxt_tx_disable(struct bnxt *bp) 6112 { 6113 int i; 6114 struct bnxt_tx_ring_info *txr; 6115 6116 if (bp->tx_ring) { 6117 for (i = 0; i < bp->tx_nr_rings; i++) { 6118 txr = &bp->tx_ring[i]; 6119 txr->dev_state = BNXT_DEV_STATE_CLOSING; 6120 } 6121 } 6122 /* Stop all TX queues */ 6123 netif_tx_disable(bp->dev); 6124 netif_carrier_off(bp->dev); 6125 } 6126 6127 void bnxt_tx_enable(struct bnxt *bp) 6128 { 6129 int i; 6130 struct bnxt_tx_ring_info *txr; 6131 6132 for (i = 0; i < bp->tx_nr_rings; i++) { 6133 txr = &bp->tx_ring[i]; 6134 txr->dev_state = 0; 6135 } 6136 netif_tx_wake_all_queues(bp->dev); 6137 if (bp->link_info.link_up) 6138 netif_carrier_on(bp->dev); 6139 } 6140 6141 static void bnxt_report_link(struct bnxt *bp) 6142 { 6143 if (bp->link_info.link_up) { 6144 const char *duplex; 6145 const char *flow_ctrl; 6146 u32 speed; 6147 u16 fec; 6148 6149 netif_carrier_on(bp->dev); 6150 if (bp->link_info.duplex == BNXT_LINK_DUPLEX_FULL) 6151 duplex = "full"; 6152 else 6153 duplex = "half"; 6154 if (bp->link_info.pause == BNXT_LINK_PAUSE_BOTH) 6155 flow_ctrl = "ON - receive & transmit"; 6156 else if (bp->link_info.pause == BNXT_LINK_PAUSE_TX) 6157 flow_ctrl = "ON - transmit"; 6158 else if (bp->link_info.pause == BNXT_LINK_PAUSE_RX) 6159 flow_ctrl = "ON - receive"; 6160 else 6161 flow_ctrl = "none"; 6162 speed = bnxt_fw_to_ethtool_speed(bp->link_info.link_speed); 6163 netdev_info(bp->dev, "NIC Link is Up, %u Mbps %s duplex, Flow control: %s\n", 6164 speed, duplex, flow_ctrl); 6165 if (bp->flags & BNXT_FLAG_EEE_CAP) 6166 netdev_info(bp->dev, "EEE is %s\n", 6167 bp->eee.eee_active ? "active" : 6168 "not active"); 6169 fec = bp->link_info.fec_cfg; 6170 if (!(fec & PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED)) 6171 netdev_info(bp->dev, "FEC autoneg %s encodings: %s\n", 6172 (fec & BNXT_FEC_AUTONEG) ? "on" : "off", 6173 (fec & BNXT_FEC_ENC_BASE_R) ? "BaseR" : 6174 (fec & BNXT_FEC_ENC_RS) ? "RS" : "None"); 6175 } else { 6176 netif_carrier_off(bp->dev); 6177 netdev_err(bp->dev, "NIC Link is Down\n"); 6178 } 6179 } 6180 6181 static int bnxt_hwrm_phy_qcaps(struct bnxt *bp) 6182 { 6183 int rc = 0; 6184 struct hwrm_port_phy_qcaps_input req = {0}; 6185 struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr; 6186 struct bnxt_link_info *link_info = &bp->link_info; 6187 6188 if (bp->hwrm_spec_code < 0x10201) 6189 return 0; 6190 6191 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCAPS, -1, -1); 6192 6193 mutex_lock(&bp->hwrm_cmd_lock); 6194 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 6195 if (rc) 6196 goto hwrm_phy_qcaps_exit; 6197 6198 if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED) { 6199 struct ethtool_eee *eee = &bp->eee; 6200 u16 fw_speeds = le16_to_cpu(resp->supported_speeds_eee_mode); 6201 6202 bp->flags |= BNXT_FLAG_EEE_CAP; 6203 eee->supported = _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0); 6204 bp->lpi_tmr_lo = le32_to_cpu(resp->tx_lpi_timer_low) & 6205 PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK; 6206 bp->lpi_tmr_hi = le32_to_cpu(resp->valid_tx_lpi_timer_high) & 6207 PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK; 6208 } 6209 if (resp->supported_speeds_auto_mode) 6210 link_info->support_auto_speeds = 6211 le16_to_cpu(resp->supported_speeds_auto_mode); 6212 6213 bp->port_count = resp->port_cnt; 6214 6215 hwrm_phy_qcaps_exit: 6216 mutex_unlock(&bp->hwrm_cmd_lock); 6217 return rc; 6218 } 6219 6220 static int bnxt_update_link(struct bnxt *bp, bool chng_link_state) 6221 { 6222 int rc = 0; 6223 struct bnxt_link_info *link_info = &bp->link_info; 6224 struct hwrm_port_phy_qcfg_input req = {0}; 6225 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr; 6226 u8 link_up = link_info->link_up; 6227 u16 diff; 6228 6229 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCFG, -1, -1); 6230 6231 mutex_lock(&bp->hwrm_cmd_lock); 6232 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 6233 if (rc) { 6234 mutex_unlock(&bp->hwrm_cmd_lock); 6235 return rc; 6236 } 6237 6238 memcpy(&link_info->phy_qcfg_resp, resp, sizeof(*resp)); 6239 link_info->phy_link_status = resp->link; 6240 link_info->duplex = resp->duplex_cfg; 6241 if (bp->hwrm_spec_code >= 0x10800) 6242 link_info->duplex = resp->duplex_state; 6243 link_info->pause = resp->pause; 6244 link_info->auto_mode = resp->auto_mode; 6245 link_info->auto_pause_setting = resp->auto_pause; 6246 link_info->lp_pause = resp->link_partner_adv_pause; 6247 link_info->force_pause_setting = resp->force_pause; 6248 link_info->duplex_setting = resp->duplex_cfg; 6249 if (link_info->phy_link_status == BNXT_LINK_LINK) 6250 link_info->link_speed = le16_to_cpu(resp->link_speed); 6251 else 6252 link_info->link_speed = 0; 6253 link_info->force_link_speed = le16_to_cpu(resp->force_link_speed); 6254 link_info->support_speeds = le16_to_cpu(resp->support_speeds); 6255 link_info->auto_link_speeds = le16_to_cpu(resp->auto_link_speed_mask); 6256 link_info->lp_auto_link_speeds = 6257 le16_to_cpu(resp->link_partner_adv_speeds); 6258 link_info->preemphasis = le32_to_cpu(resp->preemphasis); 6259 link_info->phy_ver[0] = resp->phy_maj; 6260 link_info->phy_ver[1] = resp->phy_min; 6261 link_info->phy_ver[2] = resp->phy_bld; 6262 link_info->media_type = resp->media_type; 6263 link_info->phy_type = resp->phy_type; 6264 link_info->transceiver = resp->xcvr_pkg_type; 6265 link_info->phy_addr = resp->eee_config_phy_addr & 6266 PORT_PHY_QCFG_RESP_PHY_ADDR_MASK; 6267 link_info->module_status = resp->module_status; 6268 6269 if (bp->flags & BNXT_FLAG_EEE_CAP) { 6270 struct ethtool_eee *eee = &bp->eee; 6271 u16 fw_speeds; 6272 6273 eee->eee_active = 0; 6274 if (resp->eee_config_phy_addr & 6275 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE) { 6276 eee->eee_active = 1; 6277 fw_speeds = le16_to_cpu( 6278 resp->link_partner_adv_eee_link_speed_mask); 6279 eee->lp_advertised = 6280 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0); 6281 } 6282 6283 /* Pull initial EEE config */ 6284 if (!chng_link_state) { 6285 if (resp->eee_config_phy_addr & 6286 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED) 6287 eee->eee_enabled = 1; 6288 6289 fw_speeds = le16_to_cpu(resp->adv_eee_link_speed_mask); 6290 eee->advertised = 6291 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0); 6292 6293 if (resp->eee_config_phy_addr & 6294 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI) { 6295 __le32 tmr; 6296 6297 eee->tx_lpi_enabled = 1; 6298 tmr = resp->xcvr_identifier_type_tx_lpi_timer; 6299 eee->tx_lpi_timer = le32_to_cpu(tmr) & 6300 PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK; 6301 } 6302 } 6303 } 6304 6305 link_info->fec_cfg = PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED; 6306 if (bp->hwrm_spec_code >= 0x10504) 6307 link_info->fec_cfg = le16_to_cpu(resp->fec_cfg); 6308 6309 /* TODO: need to add more logic to report VF link */ 6310 if (chng_link_state) { 6311 if (link_info->phy_link_status == BNXT_LINK_LINK) 6312 link_info->link_up = 1; 6313 else 6314 link_info->link_up = 0; 6315 if (link_up != link_info->link_up) 6316 bnxt_report_link(bp); 6317 } else { 6318 /* alwasy link down if not require to update link state */ 6319 link_info->link_up = 0; 6320 } 6321 mutex_unlock(&bp->hwrm_cmd_lock); 6322 6323 diff = link_info->support_auto_speeds ^ link_info->advertising; 6324 if ((link_info->support_auto_speeds | diff) != 6325 link_info->support_auto_speeds) { 6326 /* An advertised speed is no longer supported, so we need to 6327 * update the advertisement settings. Caller holds RTNL 6328 * so we can modify link settings. 6329 */ 6330 link_info->advertising = link_info->support_auto_speeds; 6331 if (link_info->autoneg & BNXT_AUTONEG_SPEED) 6332 bnxt_hwrm_set_link_setting(bp, true, false); 6333 } 6334 return 0; 6335 } 6336 6337 static void bnxt_get_port_module_status(struct bnxt *bp) 6338 { 6339 struct bnxt_link_info *link_info = &bp->link_info; 6340 struct hwrm_port_phy_qcfg_output *resp = &link_info->phy_qcfg_resp; 6341 u8 module_status; 6342 6343 if (bnxt_update_link(bp, true)) 6344 return; 6345 6346 module_status = link_info->module_status; 6347 switch (module_status) { 6348 case PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX: 6349 case PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN: 6350 case PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG: 6351 netdev_warn(bp->dev, "Unqualified SFP+ module detected on port %d\n", 6352 bp->pf.port_id); 6353 if (bp->hwrm_spec_code >= 0x10201) { 6354 netdev_warn(bp->dev, "Module part number %s\n", 6355 resp->phy_vendor_partnumber); 6356 } 6357 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX) 6358 netdev_warn(bp->dev, "TX is disabled\n"); 6359 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN) 6360 netdev_warn(bp->dev, "SFP+ module is shutdown\n"); 6361 } 6362 } 6363 6364 static void 6365 bnxt_hwrm_set_pause_common(struct bnxt *bp, struct hwrm_port_phy_cfg_input *req) 6366 { 6367 if (bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) { 6368 if (bp->hwrm_spec_code >= 0x10201) 6369 req->auto_pause = 6370 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE; 6371 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX) 6372 req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX; 6373 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX) 6374 req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_TX; 6375 req->enables |= 6376 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE); 6377 } else { 6378 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX) 6379 req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_RX; 6380 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX) 6381 req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_TX; 6382 req->enables |= 6383 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE); 6384 if (bp->hwrm_spec_code >= 0x10201) { 6385 req->auto_pause = req->force_pause; 6386 req->enables |= cpu_to_le32( 6387 PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE); 6388 } 6389 } 6390 } 6391 6392 static void bnxt_hwrm_set_link_common(struct bnxt *bp, 6393 struct hwrm_port_phy_cfg_input *req) 6394 { 6395 u8 autoneg = bp->link_info.autoneg; 6396 u16 fw_link_speed = bp->link_info.req_link_speed; 6397 u16 advertising = bp->link_info.advertising; 6398 6399 if (autoneg & BNXT_AUTONEG_SPEED) { 6400 req->auto_mode |= 6401 PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK; 6402 6403 req->enables |= cpu_to_le32( 6404 PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK); 6405 req->auto_link_speed_mask = cpu_to_le16(advertising); 6406 6407 req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE); 6408 req->flags |= 6409 cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG); 6410 } else { 6411 req->force_link_speed = cpu_to_le16(fw_link_speed); 6412 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE); 6413 } 6414 6415 /* tell chimp that the setting takes effect immediately */ 6416 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESET_PHY); 6417 } 6418 6419 int bnxt_hwrm_set_pause(struct bnxt *bp) 6420 { 6421 struct hwrm_port_phy_cfg_input req = {0}; 6422 int rc; 6423 6424 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1); 6425 bnxt_hwrm_set_pause_common(bp, &req); 6426 6427 if ((bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) || 6428 bp->link_info.force_link_chng) 6429 bnxt_hwrm_set_link_common(bp, &req); 6430 6431 mutex_lock(&bp->hwrm_cmd_lock); 6432 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 6433 if (!rc && !(bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL)) { 6434 /* since changing of pause setting doesn't trigger any link 6435 * change event, the driver needs to update the current pause 6436 * result upon successfully return of the phy_cfg command 6437 */ 6438 bp->link_info.pause = 6439 bp->link_info.force_pause_setting = bp->link_info.req_flow_ctrl; 6440 bp->link_info.auto_pause_setting = 0; 6441 if (!bp->link_info.force_link_chng) 6442 bnxt_report_link(bp); 6443 } 6444 bp->link_info.force_link_chng = false; 6445 mutex_unlock(&bp->hwrm_cmd_lock); 6446 return rc; 6447 } 6448 6449 static void bnxt_hwrm_set_eee(struct bnxt *bp, 6450 struct hwrm_port_phy_cfg_input *req) 6451 { 6452 struct ethtool_eee *eee = &bp->eee; 6453 6454 if (eee->eee_enabled) { 6455 u16 eee_speeds; 6456 u32 flags = PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE; 6457 6458 if (eee->tx_lpi_enabled) 6459 flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE; 6460 else 6461 flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE; 6462 6463 req->flags |= cpu_to_le32(flags); 6464 eee_speeds = bnxt_get_fw_auto_link_speeds(eee->advertised); 6465 req->eee_link_speed_mask = cpu_to_le16(eee_speeds); 6466 req->tx_lpi_timer = cpu_to_le32(eee->tx_lpi_timer); 6467 } else { 6468 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE); 6469 } 6470 } 6471 6472 int bnxt_hwrm_set_link_setting(struct bnxt *bp, bool set_pause, bool set_eee) 6473 { 6474 struct hwrm_port_phy_cfg_input req = {0}; 6475 6476 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1); 6477 if (set_pause) 6478 bnxt_hwrm_set_pause_common(bp, &req); 6479 6480 bnxt_hwrm_set_link_common(bp, &req); 6481 6482 if (set_eee) 6483 bnxt_hwrm_set_eee(bp, &req); 6484 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 6485 } 6486 6487 static int bnxt_hwrm_shutdown_link(struct bnxt *bp) 6488 { 6489 struct hwrm_port_phy_cfg_input req = {0}; 6490 6491 if (!BNXT_SINGLE_PF(bp)) 6492 return 0; 6493 6494 if (pci_num_vf(bp->pdev)) 6495 return 0; 6496 6497 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1); 6498 req.flags = cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN); 6499 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 6500 } 6501 6502 static int bnxt_hwrm_port_led_qcaps(struct bnxt *bp) 6503 { 6504 struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr; 6505 struct hwrm_port_led_qcaps_input req = {0}; 6506 struct bnxt_pf_info *pf = &bp->pf; 6507 int rc; 6508 6509 if (BNXT_VF(bp) || bp->hwrm_spec_code < 0x10601) 6510 return 0; 6511 6512 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_LED_QCAPS, -1, -1); 6513 req.port_id = cpu_to_le16(pf->port_id); 6514 mutex_lock(&bp->hwrm_cmd_lock); 6515 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 6516 if (rc) { 6517 mutex_unlock(&bp->hwrm_cmd_lock); 6518 return rc; 6519 } 6520 if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) { 6521 int i; 6522 6523 bp->num_leds = resp->num_leds; 6524 memcpy(bp->leds, &resp->led0_id, sizeof(bp->leds[0]) * 6525 bp->num_leds); 6526 for (i = 0; i < bp->num_leds; i++) { 6527 struct bnxt_led_info *led = &bp->leds[i]; 6528 __le16 caps = led->led_state_caps; 6529 6530 if (!led->led_group_id || 6531 !BNXT_LED_ALT_BLINK_CAP(caps)) { 6532 bp->num_leds = 0; 6533 break; 6534 } 6535 } 6536 } 6537 mutex_unlock(&bp->hwrm_cmd_lock); 6538 return 0; 6539 } 6540 6541 int bnxt_hwrm_alloc_wol_fltr(struct bnxt *bp) 6542 { 6543 struct hwrm_wol_filter_alloc_input req = {0}; 6544 struct hwrm_wol_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr; 6545 int rc; 6546 6547 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_ALLOC, -1, -1); 6548 req.port_id = cpu_to_le16(bp->pf.port_id); 6549 req.wol_type = WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT; 6550 req.enables = cpu_to_le32(WOL_FILTER_ALLOC_REQ_ENABLES_MAC_ADDRESS); 6551 memcpy(req.mac_address, bp->dev->dev_addr, ETH_ALEN); 6552 mutex_lock(&bp->hwrm_cmd_lock); 6553 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 6554 if (!rc) 6555 bp->wol_filter_id = resp->wol_filter_id; 6556 mutex_unlock(&bp->hwrm_cmd_lock); 6557 return rc; 6558 } 6559 6560 int bnxt_hwrm_free_wol_fltr(struct bnxt *bp) 6561 { 6562 struct hwrm_wol_filter_free_input req = {0}; 6563 int rc; 6564 6565 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_FREE, -1, -1); 6566 req.port_id = cpu_to_le16(bp->pf.port_id); 6567 req.enables = cpu_to_le32(WOL_FILTER_FREE_REQ_ENABLES_WOL_FILTER_ID); 6568 req.wol_filter_id = bp->wol_filter_id; 6569 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 6570 return rc; 6571 } 6572 6573 static u16 bnxt_hwrm_get_wol_fltrs(struct bnxt *bp, u16 handle) 6574 { 6575 struct hwrm_wol_filter_qcfg_input req = {0}; 6576 struct hwrm_wol_filter_qcfg_output *resp = bp->hwrm_cmd_resp_addr; 6577 u16 next_handle = 0; 6578 int rc; 6579 6580 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_QCFG, -1, -1); 6581 req.port_id = cpu_to_le16(bp->pf.port_id); 6582 req.handle = cpu_to_le16(handle); 6583 mutex_lock(&bp->hwrm_cmd_lock); 6584 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 6585 if (!rc) { 6586 next_handle = le16_to_cpu(resp->next_handle); 6587 if (next_handle != 0) { 6588 if (resp->wol_type == 6589 WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT) { 6590 bp->wol = 1; 6591 bp->wol_filter_id = resp->wol_filter_id; 6592 } 6593 } 6594 } 6595 mutex_unlock(&bp->hwrm_cmd_lock); 6596 return next_handle; 6597 } 6598 6599 static void bnxt_get_wol_settings(struct bnxt *bp) 6600 { 6601 u16 handle = 0; 6602 6603 if (!BNXT_PF(bp) || !(bp->flags & BNXT_FLAG_WOL_CAP)) 6604 return; 6605 6606 do { 6607 handle = bnxt_hwrm_get_wol_fltrs(bp, handle); 6608 } while (handle && handle != 0xffff); 6609 } 6610 6611 static bool bnxt_eee_config_ok(struct bnxt *bp) 6612 { 6613 struct ethtool_eee *eee = &bp->eee; 6614 struct bnxt_link_info *link_info = &bp->link_info; 6615 6616 if (!(bp->flags & BNXT_FLAG_EEE_CAP)) 6617 return true; 6618 6619 if (eee->eee_enabled) { 6620 u32 advertising = 6621 _bnxt_fw_to_ethtool_adv_spds(link_info->advertising, 0); 6622 6623 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) { 6624 eee->eee_enabled = 0; 6625 return false; 6626 } 6627 if (eee->advertised & ~advertising) { 6628 eee->advertised = advertising & eee->supported; 6629 return false; 6630 } 6631 } 6632 return true; 6633 } 6634 6635 static int bnxt_update_phy_setting(struct bnxt *bp) 6636 { 6637 int rc; 6638 bool update_link = false; 6639 bool update_pause = false; 6640 bool update_eee = false; 6641 struct bnxt_link_info *link_info = &bp->link_info; 6642 6643 rc = bnxt_update_link(bp, true); 6644 if (rc) { 6645 netdev_err(bp->dev, "failed to update link (rc: %x)\n", 6646 rc); 6647 return rc; 6648 } 6649 if (!BNXT_SINGLE_PF(bp)) 6650 return 0; 6651 6652 if ((link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) && 6653 (link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH) != 6654 link_info->req_flow_ctrl) 6655 update_pause = true; 6656 if (!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) && 6657 link_info->force_pause_setting != link_info->req_flow_ctrl) 6658 update_pause = true; 6659 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) { 6660 if (BNXT_AUTO_MODE(link_info->auto_mode)) 6661 update_link = true; 6662 if (link_info->req_link_speed != link_info->force_link_speed) 6663 update_link = true; 6664 if (link_info->req_duplex != link_info->duplex_setting) 6665 update_link = true; 6666 } else { 6667 if (link_info->auto_mode == BNXT_LINK_AUTO_NONE) 6668 update_link = true; 6669 if (link_info->advertising != link_info->auto_link_speeds) 6670 update_link = true; 6671 } 6672 6673 /* The last close may have shutdown the link, so need to call 6674 * PHY_CFG to bring it back up. 6675 */ 6676 if (!netif_carrier_ok(bp->dev)) 6677 update_link = true; 6678 6679 if (!bnxt_eee_config_ok(bp)) 6680 update_eee = true; 6681 6682 if (update_link) 6683 rc = bnxt_hwrm_set_link_setting(bp, update_pause, update_eee); 6684 else if (update_pause) 6685 rc = bnxt_hwrm_set_pause(bp); 6686 if (rc) { 6687 netdev_err(bp->dev, "failed to update phy setting (rc: %x)\n", 6688 rc); 6689 return rc; 6690 } 6691 6692 return rc; 6693 } 6694 6695 /* Common routine to pre-map certain register block to different GRC window. 6696 * A PF has 16 4K windows and a VF has 4 4K windows. However, only 15 windows 6697 * in PF and 3 windows in VF that can be customized to map in different 6698 * register blocks. 6699 */ 6700 static void bnxt_preset_reg_win(struct bnxt *bp) 6701 { 6702 if (BNXT_PF(bp)) { 6703 /* CAG registers map to GRC window #4 */ 6704 writel(BNXT_CAG_REG_BASE, 6705 bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 12); 6706 } 6707 } 6708 6709 static int __bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init) 6710 { 6711 int rc = 0; 6712 6713 bnxt_preset_reg_win(bp); 6714 netif_carrier_off(bp->dev); 6715 if (irq_re_init) { 6716 rc = bnxt_reserve_rings(bp); 6717 if (rc) 6718 return rc; 6719 6720 rc = bnxt_setup_int_mode(bp); 6721 if (rc) { 6722 netdev_err(bp->dev, "bnxt_setup_int_mode err: %x\n", 6723 rc); 6724 return rc; 6725 } 6726 } 6727 if ((bp->flags & BNXT_FLAG_RFS) && 6728 !(bp->flags & BNXT_FLAG_USING_MSIX)) { 6729 /* disable RFS if falling back to INTA */ 6730 bp->dev->hw_features &= ~NETIF_F_NTUPLE; 6731 bp->flags &= ~BNXT_FLAG_RFS; 6732 } 6733 6734 rc = bnxt_alloc_mem(bp, irq_re_init); 6735 if (rc) { 6736 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc); 6737 goto open_err_free_mem; 6738 } 6739 6740 if (irq_re_init) { 6741 bnxt_init_napi(bp); 6742 rc = bnxt_request_irq(bp); 6743 if (rc) { 6744 netdev_err(bp->dev, "bnxt_request_irq err: %x\n", rc); 6745 goto open_err; 6746 } 6747 } 6748 6749 bnxt_enable_napi(bp); 6750 6751 rc = bnxt_init_nic(bp, irq_re_init); 6752 if (rc) { 6753 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc); 6754 goto open_err; 6755 } 6756 6757 if (link_re_init) { 6758 mutex_lock(&bp->link_lock); 6759 rc = bnxt_update_phy_setting(bp); 6760 mutex_unlock(&bp->link_lock); 6761 if (rc) 6762 netdev_warn(bp->dev, "failed to update phy settings\n"); 6763 } 6764 6765 if (irq_re_init) 6766 udp_tunnel_get_rx_info(bp->dev); 6767 6768 set_bit(BNXT_STATE_OPEN, &bp->state); 6769 bnxt_enable_int(bp); 6770 /* Enable TX queues */ 6771 bnxt_tx_enable(bp); 6772 mod_timer(&bp->timer, jiffies + bp->current_interval); 6773 /* Poll link status and check for SFP+ module status */ 6774 bnxt_get_port_module_status(bp); 6775 6776 /* VF-reps may need to be re-opened after the PF is re-opened */ 6777 if (BNXT_PF(bp)) 6778 bnxt_vf_reps_open(bp); 6779 return 0; 6780 6781 open_err: 6782 bnxt_disable_napi(bp); 6783 bnxt_del_napi(bp); 6784 6785 open_err_free_mem: 6786 bnxt_free_skbs(bp); 6787 bnxt_free_irq(bp); 6788 bnxt_free_mem(bp, true); 6789 return rc; 6790 } 6791 6792 /* rtnl_lock held */ 6793 int bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init) 6794 { 6795 int rc = 0; 6796 6797 rc = __bnxt_open_nic(bp, irq_re_init, link_re_init); 6798 if (rc) { 6799 netdev_err(bp->dev, "nic open fail (rc: %x)\n", rc); 6800 dev_close(bp->dev); 6801 } 6802 return rc; 6803 } 6804 6805 /* rtnl_lock held, open the NIC half way by allocating all resources, but 6806 * NAPI, IRQ, and TX are not enabled. This is mainly used for offline 6807 * self tests. 6808 */ 6809 int bnxt_half_open_nic(struct bnxt *bp) 6810 { 6811 int rc = 0; 6812 6813 rc = bnxt_alloc_mem(bp, false); 6814 if (rc) { 6815 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc); 6816 goto half_open_err; 6817 } 6818 rc = bnxt_init_nic(bp, false); 6819 if (rc) { 6820 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc); 6821 goto half_open_err; 6822 } 6823 return 0; 6824 6825 half_open_err: 6826 bnxt_free_skbs(bp); 6827 bnxt_free_mem(bp, false); 6828 dev_close(bp->dev); 6829 return rc; 6830 } 6831 6832 /* rtnl_lock held, this call can only be made after a previous successful 6833 * call to bnxt_half_open_nic(). 6834 */ 6835 void bnxt_half_close_nic(struct bnxt *bp) 6836 { 6837 bnxt_hwrm_resource_free(bp, false, false); 6838 bnxt_free_skbs(bp); 6839 bnxt_free_mem(bp, false); 6840 } 6841 6842 static int bnxt_open(struct net_device *dev) 6843 { 6844 struct bnxt *bp = netdev_priv(dev); 6845 6846 return __bnxt_open_nic(bp, true, true); 6847 } 6848 6849 static bool bnxt_drv_busy(struct bnxt *bp) 6850 { 6851 return (test_bit(BNXT_STATE_IN_SP_TASK, &bp->state) || 6852 test_bit(BNXT_STATE_READ_STATS, &bp->state)); 6853 } 6854 6855 static void __bnxt_close_nic(struct bnxt *bp, bool irq_re_init, 6856 bool link_re_init) 6857 { 6858 /* Close the VF-reps before closing PF */ 6859 if (BNXT_PF(bp)) 6860 bnxt_vf_reps_close(bp); 6861 6862 /* Change device state to avoid TX queue wake up's */ 6863 bnxt_tx_disable(bp); 6864 6865 clear_bit(BNXT_STATE_OPEN, &bp->state); 6866 smp_mb__after_atomic(); 6867 while (bnxt_drv_busy(bp)) 6868 msleep(20); 6869 6870 /* Flush rings and and disable interrupts */ 6871 bnxt_shutdown_nic(bp, irq_re_init); 6872 6873 /* TODO CHIMP_FW: Link/PHY related cleanup if (link_re_init) */ 6874 6875 bnxt_disable_napi(bp); 6876 del_timer_sync(&bp->timer); 6877 bnxt_free_skbs(bp); 6878 6879 if (irq_re_init) { 6880 bnxt_free_irq(bp); 6881 bnxt_del_napi(bp); 6882 } 6883 bnxt_free_mem(bp, irq_re_init); 6884 } 6885 6886 int bnxt_close_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init) 6887 { 6888 int rc = 0; 6889 6890 #ifdef CONFIG_BNXT_SRIOV 6891 if (bp->sriov_cfg) { 6892 rc = wait_event_interruptible_timeout(bp->sriov_cfg_wait, 6893 !bp->sriov_cfg, 6894 BNXT_SRIOV_CFG_WAIT_TMO); 6895 if (rc) 6896 netdev_warn(bp->dev, "timeout waiting for SRIOV config operation to complete!\n"); 6897 } 6898 #endif 6899 __bnxt_close_nic(bp, irq_re_init, link_re_init); 6900 return rc; 6901 } 6902 6903 static int bnxt_close(struct net_device *dev) 6904 { 6905 struct bnxt *bp = netdev_priv(dev); 6906 6907 bnxt_close_nic(bp, true, true); 6908 bnxt_hwrm_shutdown_link(bp); 6909 return 0; 6910 } 6911 6912 /* rtnl_lock held */ 6913 static int bnxt_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 6914 { 6915 switch (cmd) { 6916 case SIOCGMIIPHY: 6917 /* fallthru */ 6918 case SIOCGMIIREG: { 6919 if (!netif_running(dev)) 6920 return -EAGAIN; 6921 6922 return 0; 6923 } 6924 6925 case SIOCSMIIREG: 6926 if (!netif_running(dev)) 6927 return -EAGAIN; 6928 6929 return 0; 6930 6931 default: 6932 /* do nothing */ 6933 break; 6934 } 6935 return -EOPNOTSUPP; 6936 } 6937 6938 static void 6939 bnxt_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) 6940 { 6941 u32 i; 6942 struct bnxt *bp = netdev_priv(dev); 6943 6944 set_bit(BNXT_STATE_READ_STATS, &bp->state); 6945 /* Make sure bnxt_close_nic() sees that we are reading stats before 6946 * we check the BNXT_STATE_OPEN flag. 6947 */ 6948 smp_mb__after_atomic(); 6949 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) { 6950 clear_bit(BNXT_STATE_READ_STATS, &bp->state); 6951 return; 6952 } 6953 6954 /* TODO check if we need to synchronize with bnxt_close path */ 6955 for (i = 0; i < bp->cp_nr_rings; i++) { 6956 struct bnxt_napi *bnapi = bp->bnapi[i]; 6957 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 6958 struct ctx_hw_stats *hw_stats = cpr->hw_stats; 6959 6960 stats->rx_packets += le64_to_cpu(hw_stats->rx_ucast_pkts); 6961 stats->rx_packets += le64_to_cpu(hw_stats->rx_mcast_pkts); 6962 stats->rx_packets += le64_to_cpu(hw_stats->rx_bcast_pkts); 6963 6964 stats->tx_packets += le64_to_cpu(hw_stats->tx_ucast_pkts); 6965 stats->tx_packets += le64_to_cpu(hw_stats->tx_mcast_pkts); 6966 stats->tx_packets += le64_to_cpu(hw_stats->tx_bcast_pkts); 6967 6968 stats->rx_bytes += le64_to_cpu(hw_stats->rx_ucast_bytes); 6969 stats->rx_bytes += le64_to_cpu(hw_stats->rx_mcast_bytes); 6970 stats->rx_bytes += le64_to_cpu(hw_stats->rx_bcast_bytes); 6971 6972 stats->tx_bytes += le64_to_cpu(hw_stats->tx_ucast_bytes); 6973 stats->tx_bytes += le64_to_cpu(hw_stats->tx_mcast_bytes); 6974 stats->tx_bytes += le64_to_cpu(hw_stats->tx_bcast_bytes); 6975 6976 stats->rx_missed_errors += 6977 le64_to_cpu(hw_stats->rx_discard_pkts); 6978 6979 stats->multicast += le64_to_cpu(hw_stats->rx_mcast_pkts); 6980 6981 stats->tx_dropped += le64_to_cpu(hw_stats->tx_drop_pkts); 6982 } 6983 6984 if (bp->flags & BNXT_FLAG_PORT_STATS) { 6985 struct rx_port_stats *rx = bp->hw_rx_port_stats; 6986 struct tx_port_stats *tx = bp->hw_tx_port_stats; 6987 6988 stats->rx_crc_errors = le64_to_cpu(rx->rx_fcs_err_frames); 6989 stats->rx_frame_errors = le64_to_cpu(rx->rx_align_err_frames); 6990 stats->rx_length_errors = le64_to_cpu(rx->rx_undrsz_frames) + 6991 le64_to_cpu(rx->rx_ovrsz_frames) + 6992 le64_to_cpu(rx->rx_runt_frames); 6993 stats->rx_errors = le64_to_cpu(rx->rx_false_carrier_frames) + 6994 le64_to_cpu(rx->rx_jbr_frames); 6995 stats->collisions = le64_to_cpu(tx->tx_total_collisions); 6996 stats->tx_fifo_errors = le64_to_cpu(tx->tx_fifo_underruns); 6997 stats->tx_errors = le64_to_cpu(tx->tx_err); 6998 } 6999 clear_bit(BNXT_STATE_READ_STATS, &bp->state); 7000 } 7001 7002 static bool bnxt_mc_list_updated(struct bnxt *bp, u32 *rx_mask) 7003 { 7004 struct net_device *dev = bp->dev; 7005 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 7006 struct netdev_hw_addr *ha; 7007 u8 *haddr; 7008 int mc_count = 0; 7009 bool update = false; 7010 int off = 0; 7011 7012 netdev_for_each_mc_addr(ha, dev) { 7013 if (mc_count >= BNXT_MAX_MC_ADDRS) { 7014 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST; 7015 vnic->mc_list_count = 0; 7016 return false; 7017 } 7018 haddr = ha->addr; 7019 if (!ether_addr_equal(haddr, vnic->mc_list + off)) { 7020 memcpy(vnic->mc_list + off, haddr, ETH_ALEN); 7021 update = true; 7022 } 7023 off += ETH_ALEN; 7024 mc_count++; 7025 } 7026 if (mc_count) 7027 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_MCAST; 7028 7029 if (mc_count != vnic->mc_list_count) { 7030 vnic->mc_list_count = mc_count; 7031 update = true; 7032 } 7033 return update; 7034 } 7035 7036 static bool bnxt_uc_list_updated(struct bnxt *bp) 7037 { 7038 struct net_device *dev = bp->dev; 7039 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 7040 struct netdev_hw_addr *ha; 7041 int off = 0; 7042 7043 if (netdev_uc_count(dev) != (vnic->uc_filter_count - 1)) 7044 return true; 7045 7046 netdev_for_each_uc_addr(ha, dev) { 7047 if (!ether_addr_equal(ha->addr, vnic->uc_list + off)) 7048 return true; 7049 7050 off += ETH_ALEN; 7051 } 7052 return false; 7053 } 7054 7055 static void bnxt_set_rx_mode(struct net_device *dev) 7056 { 7057 struct bnxt *bp = netdev_priv(dev); 7058 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 7059 u32 mask = vnic->rx_mask; 7060 bool mc_update = false; 7061 bool uc_update; 7062 7063 if (!netif_running(dev)) 7064 return; 7065 7066 mask &= ~(CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS | 7067 CFA_L2_SET_RX_MASK_REQ_MASK_MCAST | 7068 CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST); 7069 7070 if ((dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp)) 7071 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS; 7072 7073 uc_update = bnxt_uc_list_updated(bp); 7074 7075 if (dev->flags & IFF_ALLMULTI) { 7076 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST; 7077 vnic->mc_list_count = 0; 7078 } else { 7079 mc_update = bnxt_mc_list_updated(bp, &mask); 7080 } 7081 7082 if (mask != vnic->rx_mask || uc_update || mc_update) { 7083 vnic->rx_mask = mask; 7084 7085 set_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event); 7086 bnxt_queue_sp_work(bp); 7087 } 7088 } 7089 7090 static int bnxt_cfg_rx_mode(struct bnxt *bp) 7091 { 7092 struct net_device *dev = bp->dev; 7093 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 7094 struct netdev_hw_addr *ha; 7095 int i, off = 0, rc; 7096 bool uc_update; 7097 7098 netif_addr_lock_bh(dev); 7099 uc_update = bnxt_uc_list_updated(bp); 7100 netif_addr_unlock_bh(dev); 7101 7102 if (!uc_update) 7103 goto skip_uc; 7104 7105 mutex_lock(&bp->hwrm_cmd_lock); 7106 for (i = 1; i < vnic->uc_filter_count; i++) { 7107 struct hwrm_cfa_l2_filter_free_input req = {0}; 7108 7109 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_FREE, -1, 7110 -1); 7111 7112 req.l2_filter_id = vnic->fw_l2_filter_id[i]; 7113 7114 rc = _hwrm_send_message(bp, &req, sizeof(req), 7115 HWRM_CMD_TIMEOUT); 7116 } 7117 mutex_unlock(&bp->hwrm_cmd_lock); 7118 7119 vnic->uc_filter_count = 1; 7120 7121 netif_addr_lock_bh(dev); 7122 if (netdev_uc_count(dev) > (BNXT_MAX_UC_ADDRS - 1)) { 7123 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS; 7124 } else { 7125 netdev_for_each_uc_addr(ha, dev) { 7126 memcpy(vnic->uc_list + off, ha->addr, ETH_ALEN); 7127 off += ETH_ALEN; 7128 vnic->uc_filter_count++; 7129 } 7130 } 7131 netif_addr_unlock_bh(dev); 7132 7133 for (i = 1, off = 0; i < vnic->uc_filter_count; i++, off += ETH_ALEN) { 7134 rc = bnxt_hwrm_set_vnic_filter(bp, 0, i, vnic->uc_list + off); 7135 if (rc) { 7136 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n", 7137 rc); 7138 vnic->uc_filter_count = i; 7139 return rc; 7140 } 7141 } 7142 7143 skip_uc: 7144 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0); 7145 if (rc) 7146 netdev_err(bp->dev, "HWRM cfa l2 rx mask failure rc: %x\n", 7147 rc); 7148 7149 return rc; 7150 } 7151 7152 /* If the chip and firmware supports RFS */ 7153 static bool bnxt_rfs_supported(struct bnxt *bp) 7154 { 7155 if (BNXT_PF(bp) && !BNXT_CHIP_TYPE_NITRO_A0(bp)) 7156 return true; 7157 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP) 7158 return true; 7159 return false; 7160 } 7161 7162 /* If runtime conditions support RFS */ 7163 static bool bnxt_rfs_capable(struct bnxt *bp) 7164 { 7165 #ifdef CONFIG_RFS_ACCEL 7166 int vnics, max_vnics, max_rss_ctxs; 7167 7168 if (!(bp->flags & BNXT_FLAG_MSIX_CAP)) 7169 return false; 7170 7171 vnics = 1 + bp->rx_nr_rings; 7172 max_vnics = bnxt_get_max_func_vnics(bp); 7173 max_rss_ctxs = bnxt_get_max_func_rss_ctxs(bp); 7174 7175 /* RSS contexts not a limiting factor */ 7176 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP) 7177 max_rss_ctxs = max_vnics; 7178 if (vnics > max_vnics || vnics > max_rss_ctxs) { 7179 if (bp->rx_nr_rings > 1) 7180 netdev_warn(bp->dev, 7181 "Not enough resources to support NTUPLE filters, enough resources for up to %d rx rings\n", 7182 min(max_rss_ctxs - 1, max_vnics - 1)); 7183 return false; 7184 } 7185 7186 if (!(bp->flags & BNXT_FLAG_NEW_RM)) 7187 return true; 7188 7189 if (vnics == bp->hw_resc.resv_vnics) 7190 return true; 7191 7192 bnxt_hwrm_reserve_rings(bp, 0, 0, 0, 0, vnics); 7193 if (vnics <= bp->hw_resc.resv_vnics) 7194 return true; 7195 7196 netdev_warn(bp->dev, "Unable to reserve resources to support NTUPLE filters.\n"); 7197 bnxt_hwrm_reserve_rings(bp, 0, 0, 0, 0, 1); 7198 return false; 7199 #else 7200 return false; 7201 #endif 7202 } 7203 7204 static netdev_features_t bnxt_fix_features(struct net_device *dev, 7205 netdev_features_t features) 7206 { 7207 struct bnxt *bp = netdev_priv(dev); 7208 7209 if ((features & NETIF_F_NTUPLE) && !bnxt_rfs_capable(bp)) 7210 features &= ~NETIF_F_NTUPLE; 7211 7212 if (bp->flags & BNXT_FLAG_NO_AGG_RINGS) 7213 features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW); 7214 7215 if (!(features & NETIF_F_GRO)) 7216 features &= ~NETIF_F_GRO_HW; 7217 7218 if (features & NETIF_F_GRO_HW) 7219 features &= ~NETIF_F_LRO; 7220 7221 /* Both CTAG and STAG VLAN accelaration on the RX side have to be 7222 * turned on or off together. 7223 */ 7224 if ((features & (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) != 7225 (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) { 7226 if (dev->features & NETIF_F_HW_VLAN_CTAG_RX) 7227 features &= ~(NETIF_F_HW_VLAN_CTAG_RX | 7228 NETIF_F_HW_VLAN_STAG_RX); 7229 else 7230 features |= NETIF_F_HW_VLAN_CTAG_RX | 7231 NETIF_F_HW_VLAN_STAG_RX; 7232 } 7233 #ifdef CONFIG_BNXT_SRIOV 7234 if (BNXT_VF(bp)) { 7235 if (bp->vf.vlan) { 7236 features &= ~(NETIF_F_HW_VLAN_CTAG_RX | 7237 NETIF_F_HW_VLAN_STAG_RX); 7238 } 7239 } 7240 #endif 7241 return features; 7242 } 7243 7244 static int bnxt_set_features(struct net_device *dev, netdev_features_t features) 7245 { 7246 struct bnxt *bp = netdev_priv(dev); 7247 u32 flags = bp->flags; 7248 u32 changes; 7249 int rc = 0; 7250 bool re_init = false; 7251 bool update_tpa = false; 7252 7253 flags &= ~BNXT_FLAG_ALL_CONFIG_FEATS; 7254 if (features & NETIF_F_GRO_HW) 7255 flags |= BNXT_FLAG_GRO; 7256 else if (features & NETIF_F_LRO) 7257 flags |= BNXT_FLAG_LRO; 7258 7259 if (bp->flags & BNXT_FLAG_NO_AGG_RINGS) 7260 flags &= ~BNXT_FLAG_TPA; 7261 7262 if (features & NETIF_F_HW_VLAN_CTAG_RX) 7263 flags |= BNXT_FLAG_STRIP_VLAN; 7264 7265 if (features & NETIF_F_NTUPLE) 7266 flags |= BNXT_FLAG_RFS; 7267 7268 changes = flags ^ bp->flags; 7269 if (changes & BNXT_FLAG_TPA) { 7270 update_tpa = true; 7271 if ((bp->flags & BNXT_FLAG_TPA) == 0 || 7272 (flags & BNXT_FLAG_TPA) == 0) 7273 re_init = true; 7274 } 7275 7276 if (changes & ~BNXT_FLAG_TPA) 7277 re_init = true; 7278 7279 if (flags != bp->flags) { 7280 u32 old_flags = bp->flags; 7281 7282 bp->flags = flags; 7283 7284 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) { 7285 if (update_tpa) 7286 bnxt_set_ring_params(bp); 7287 return rc; 7288 } 7289 7290 if (re_init) { 7291 bnxt_close_nic(bp, false, false); 7292 if (update_tpa) 7293 bnxt_set_ring_params(bp); 7294 7295 return bnxt_open_nic(bp, false, false); 7296 } 7297 if (update_tpa) { 7298 rc = bnxt_set_tpa(bp, 7299 (flags & BNXT_FLAG_TPA) ? 7300 true : false); 7301 if (rc) 7302 bp->flags = old_flags; 7303 } 7304 } 7305 return rc; 7306 } 7307 7308 static void bnxt_dump_tx_sw_state(struct bnxt_napi *bnapi) 7309 { 7310 struct bnxt_tx_ring_info *txr = bnapi->tx_ring; 7311 int i = bnapi->index; 7312 7313 if (!txr) 7314 return; 7315 7316 netdev_info(bnapi->bp->dev, "[%d]: tx{fw_ring: %d prod: %x cons: %x}\n", 7317 i, txr->tx_ring_struct.fw_ring_id, txr->tx_prod, 7318 txr->tx_cons); 7319 } 7320 7321 static void bnxt_dump_rx_sw_state(struct bnxt_napi *bnapi) 7322 { 7323 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 7324 int i = bnapi->index; 7325 7326 if (!rxr) 7327 return; 7328 7329 netdev_info(bnapi->bp->dev, "[%d]: rx{fw_ring: %d prod: %x} rx_agg{fw_ring: %d agg_prod: %x sw_agg_prod: %x}\n", 7330 i, rxr->rx_ring_struct.fw_ring_id, rxr->rx_prod, 7331 rxr->rx_agg_ring_struct.fw_ring_id, rxr->rx_agg_prod, 7332 rxr->rx_sw_agg_prod); 7333 } 7334 7335 static void bnxt_dump_cp_sw_state(struct bnxt_napi *bnapi) 7336 { 7337 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 7338 int i = bnapi->index; 7339 7340 netdev_info(bnapi->bp->dev, "[%d]: cp{fw_ring: %d raw_cons: %x}\n", 7341 i, cpr->cp_ring_struct.fw_ring_id, cpr->cp_raw_cons); 7342 } 7343 7344 static void bnxt_dbg_dump_states(struct bnxt *bp) 7345 { 7346 int i; 7347 struct bnxt_napi *bnapi; 7348 7349 for (i = 0; i < bp->cp_nr_rings; i++) { 7350 bnapi = bp->bnapi[i]; 7351 if (netif_msg_drv(bp)) { 7352 bnxt_dump_tx_sw_state(bnapi); 7353 bnxt_dump_rx_sw_state(bnapi); 7354 bnxt_dump_cp_sw_state(bnapi); 7355 } 7356 } 7357 } 7358 7359 static void bnxt_reset_task(struct bnxt *bp, bool silent) 7360 { 7361 if (!silent) 7362 bnxt_dbg_dump_states(bp); 7363 if (netif_running(bp->dev)) { 7364 int rc; 7365 7366 if (!silent) 7367 bnxt_ulp_stop(bp); 7368 bnxt_close_nic(bp, false, false); 7369 rc = bnxt_open_nic(bp, false, false); 7370 if (!silent && !rc) 7371 bnxt_ulp_start(bp); 7372 } 7373 } 7374 7375 static void bnxt_tx_timeout(struct net_device *dev) 7376 { 7377 struct bnxt *bp = netdev_priv(dev); 7378 7379 netdev_err(bp->dev, "TX timeout detected, starting reset task!\n"); 7380 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event); 7381 bnxt_queue_sp_work(bp); 7382 } 7383 7384 #ifdef CONFIG_NET_POLL_CONTROLLER 7385 static void bnxt_poll_controller(struct net_device *dev) 7386 { 7387 struct bnxt *bp = netdev_priv(dev); 7388 int i; 7389 7390 /* Only process tx rings/combined rings in netpoll mode. */ 7391 for (i = 0; i < bp->tx_nr_rings; i++) { 7392 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; 7393 7394 napi_schedule(&txr->bnapi->napi); 7395 } 7396 } 7397 #endif 7398 7399 static void bnxt_timer(struct timer_list *t) 7400 { 7401 struct bnxt *bp = from_timer(bp, t, timer); 7402 struct net_device *dev = bp->dev; 7403 7404 if (!netif_running(dev)) 7405 return; 7406 7407 if (atomic_read(&bp->intr_sem) != 0) 7408 goto bnxt_restart_timer; 7409 7410 if (bp->link_info.link_up && (bp->flags & BNXT_FLAG_PORT_STATS) && 7411 bp->stats_coal_ticks) { 7412 set_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event); 7413 bnxt_queue_sp_work(bp); 7414 } 7415 7416 if (bnxt_tc_flower_enabled(bp)) { 7417 set_bit(BNXT_FLOW_STATS_SP_EVENT, &bp->sp_event); 7418 bnxt_queue_sp_work(bp); 7419 } 7420 bnxt_restart_timer: 7421 mod_timer(&bp->timer, jiffies + bp->current_interval); 7422 } 7423 7424 static void bnxt_rtnl_lock_sp(struct bnxt *bp) 7425 { 7426 /* We are called from bnxt_sp_task which has BNXT_STATE_IN_SP_TASK 7427 * set. If the device is being closed, bnxt_close() may be holding 7428 * rtnl() and waiting for BNXT_STATE_IN_SP_TASK to clear. So we 7429 * must clear BNXT_STATE_IN_SP_TASK before holding rtnl(). 7430 */ 7431 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state); 7432 rtnl_lock(); 7433 } 7434 7435 static void bnxt_rtnl_unlock_sp(struct bnxt *bp) 7436 { 7437 set_bit(BNXT_STATE_IN_SP_TASK, &bp->state); 7438 rtnl_unlock(); 7439 } 7440 7441 /* Only called from bnxt_sp_task() */ 7442 static void bnxt_reset(struct bnxt *bp, bool silent) 7443 { 7444 bnxt_rtnl_lock_sp(bp); 7445 if (test_bit(BNXT_STATE_OPEN, &bp->state)) 7446 bnxt_reset_task(bp, silent); 7447 bnxt_rtnl_unlock_sp(bp); 7448 } 7449 7450 static void bnxt_cfg_ntp_filters(struct bnxt *); 7451 7452 static void bnxt_sp_task(struct work_struct *work) 7453 { 7454 struct bnxt *bp = container_of(work, struct bnxt, sp_task); 7455 7456 set_bit(BNXT_STATE_IN_SP_TASK, &bp->state); 7457 smp_mb__after_atomic(); 7458 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) { 7459 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state); 7460 return; 7461 } 7462 7463 if (test_and_clear_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event)) 7464 bnxt_cfg_rx_mode(bp); 7465 7466 if (test_and_clear_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event)) 7467 bnxt_cfg_ntp_filters(bp); 7468 if (test_and_clear_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event)) 7469 bnxt_hwrm_exec_fwd_req(bp); 7470 if (test_and_clear_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event)) { 7471 bnxt_hwrm_tunnel_dst_port_alloc( 7472 bp, bp->vxlan_port, 7473 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN); 7474 } 7475 if (test_and_clear_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event)) { 7476 bnxt_hwrm_tunnel_dst_port_free( 7477 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN); 7478 } 7479 if (test_and_clear_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event)) { 7480 bnxt_hwrm_tunnel_dst_port_alloc( 7481 bp, bp->nge_port, 7482 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE); 7483 } 7484 if (test_and_clear_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event)) { 7485 bnxt_hwrm_tunnel_dst_port_free( 7486 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE); 7487 } 7488 if (test_and_clear_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event)) 7489 bnxt_hwrm_port_qstats(bp); 7490 7491 if (test_and_clear_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event)) { 7492 int rc; 7493 7494 mutex_lock(&bp->link_lock); 7495 if (test_and_clear_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT, 7496 &bp->sp_event)) 7497 bnxt_hwrm_phy_qcaps(bp); 7498 7499 rc = bnxt_update_link(bp, true); 7500 mutex_unlock(&bp->link_lock); 7501 if (rc) 7502 netdev_err(bp->dev, "SP task can't update link (rc: %x)\n", 7503 rc); 7504 } 7505 if (test_and_clear_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event)) { 7506 mutex_lock(&bp->link_lock); 7507 bnxt_get_port_module_status(bp); 7508 mutex_unlock(&bp->link_lock); 7509 } 7510 7511 if (test_and_clear_bit(BNXT_FLOW_STATS_SP_EVENT, &bp->sp_event)) 7512 bnxt_tc_flow_stats_work(bp); 7513 7514 /* These functions below will clear BNXT_STATE_IN_SP_TASK. They 7515 * must be the last functions to be called before exiting. 7516 */ 7517 if (test_and_clear_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event)) 7518 bnxt_reset(bp, false); 7519 7520 if (test_and_clear_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event)) 7521 bnxt_reset(bp, true); 7522 7523 smp_mb__before_atomic(); 7524 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state); 7525 } 7526 7527 /* Under rtnl_lock */ 7528 int bnxt_check_rings(struct bnxt *bp, int tx, int rx, bool sh, int tcs, 7529 int tx_xdp) 7530 { 7531 int max_rx, max_tx, tx_sets = 1; 7532 int tx_rings_needed; 7533 int rx_rings = rx; 7534 int cp, rc; 7535 7536 if (tcs) 7537 tx_sets = tcs; 7538 7539 rc = bnxt_get_max_rings(bp, &max_rx, &max_tx, sh); 7540 if (rc) 7541 return rc; 7542 7543 if (max_rx < rx) 7544 return -ENOMEM; 7545 7546 tx_rings_needed = tx * tx_sets + tx_xdp; 7547 if (max_tx < tx_rings_needed) 7548 return -ENOMEM; 7549 7550 if (bp->flags & BNXT_FLAG_AGG_RINGS) 7551 rx_rings <<= 1; 7552 cp = sh ? max_t(int, tx_rings_needed, rx) : tx_rings_needed + rx; 7553 return bnxt_hwrm_check_rings(bp, tx_rings_needed, rx_rings, rx, cp); 7554 } 7555 7556 static void bnxt_unmap_bars(struct bnxt *bp, struct pci_dev *pdev) 7557 { 7558 if (bp->bar2) { 7559 pci_iounmap(pdev, bp->bar2); 7560 bp->bar2 = NULL; 7561 } 7562 7563 if (bp->bar1) { 7564 pci_iounmap(pdev, bp->bar1); 7565 bp->bar1 = NULL; 7566 } 7567 7568 if (bp->bar0) { 7569 pci_iounmap(pdev, bp->bar0); 7570 bp->bar0 = NULL; 7571 } 7572 } 7573 7574 static void bnxt_cleanup_pci(struct bnxt *bp) 7575 { 7576 bnxt_unmap_bars(bp, bp->pdev); 7577 pci_release_regions(bp->pdev); 7578 pci_disable_device(bp->pdev); 7579 } 7580 7581 static void bnxt_init_dflt_coal(struct bnxt *bp) 7582 { 7583 struct bnxt_coal *coal; 7584 7585 /* Tick values in micro seconds. 7586 * 1 coal_buf x bufs_per_record = 1 completion record. 7587 */ 7588 coal = &bp->rx_coal; 7589 coal->coal_ticks = 14; 7590 coal->coal_bufs = 30; 7591 coal->coal_ticks_irq = 1; 7592 coal->coal_bufs_irq = 2; 7593 coal->idle_thresh = 25; 7594 coal->bufs_per_record = 2; 7595 coal->budget = 64; /* NAPI budget */ 7596 7597 coal = &bp->tx_coal; 7598 coal->coal_ticks = 28; 7599 coal->coal_bufs = 30; 7600 coal->coal_ticks_irq = 2; 7601 coal->coal_bufs_irq = 2; 7602 coal->bufs_per_record = 1; 7603 7604 bp->stats_coal_ticks = BNXT_DEF_STATS_COAL_TICKS; 7605 } 7606 7607 static int bnxt_init_board(struct pci_dev *pdev, struct net_device *dev) 7608 { 7609 int rc; 7610 struct bnxt *bp = netdev_priv(dev); 7611 7612 SET_NETDEV_DEV(dev, &pdev->dev); 7613 7614 /* enable device (incl. PCI PM wakeup), and bus-mastering */ 7615 rc = pci_enable_device(pdev); 7616 if (rc) { 7617 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n"); 7618 goto init_err; 7619 } 7620 7621 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 7622 dev_err(&pdev->dev, 7623 "Cannot find PCI device base address, aborting\n"); 7624 rc = -ENODEV; 7625 goto init_err_disable; 7626 } 7627 7628 rc = pci_request_regions(pdev, DRV_MODULE_NAME); 7629 if (rc) { 7630 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n"); 7631 goto init_err_disable; 7632 } 7633 7634 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) != 0 && 7635 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)) != 0) { 7636 dev_err(&pdev->dev, "System does not support DMA, aborting\n"); 7637 goto init_err_disable; 7638 } 7639 7640 pci_set_master(pdev); 7641 7642 bp->dev = dev; 7643 bp->pdev = pdev; 7644 7645 bp->bar0 = pci_ioremap_bar(pdev, 0); 7646 if (!bp->bar0) { 7647 dev_err(&pdev->dev, "Cannot map device registers, aborting\n"); 7648 rc = -ENOMEM; 7649 goto init_err_release; 7650 } 7651 7652 bp->bar1 = pci_ioremap_bar(pdev, 2); 7653 if (!bp->bar1) { 7654 dev_err(&pdev->dev, "Cannot map doorbell registers, aborting\n"); 7655 rc = -ENOMEM; 7656 goto init_err_release; 7657 } 7658 7659 bp->bar2 = pci_ioremap_bar(pdev, 4); 7660 if (!bp->bar2) { 7661 dev_err(&pdev->dev, "Cannot map bar4 registers, aborting\n"); 7662 rc = -ENOMEM; 7663 goto init_err_release; 7664 } 7665 7666 pci_enable_pcie_error_reporting(pdev); 7667 7668 INIT_WORK(&bp->sp_task, bnxt_sp_task); 7669 7670 spin_lock_init(&bp->ntp_fltr_lock); 7671 7672 bp->rx_ring_size = BNXT_DEFAULT_RX_RING_SIZE; 7673 bp->tx_ring_size = BNXT_DEFAULT_TX_RING_SIZE; 7674 7675 bnxt_init_dflt_coal(bp); 7676 7677 timer_setup(&bp->timer, bnxt_timer, 0); 7678 bp->current_interval = BNXT_TIMER_INTERVAL; 7679 7680 clear_bit(BNXT_STATE_OPEN, &bp->state); 7681 return 0; 7682 7683 init_err_release: 7684 bnxt_unmap_bars(bp, pdev); 7685 pci_release_regions(pdev); 7686 7687 init_err_disable: 7688 pci_disable_device(pdev); 7689 7690 init_err: 7691 return rc; 7692 } 7693 7694 /* rtnl_lock held */ 7695 static int bnxt_change_mac_addr(struct net_device *dev, void *p) 7696 { 7697 struct sockaddr *addr = p; 7698 struct bnxt *bp = netdev_priv(dev); 7699 int rc = 0; 7700 7701 if (!is_valid_ether_addr(addr->sa_data)) 7702 return -EADDRNOTAVAIL; 7703 7704 if (ether_addr_equal(addr->sa_data, dev->dev_addr)) 7705 return 0; 7706 7707 rc = bnxt_approve_mac(bp, addr->sa_data); 7708 if (rc) 7709 return rc; 7710 7711 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); 7712 if (netif_running(dev)) { 7713 bnxt_close_nic(bp, false, false); 7714 rc = bnxt_open_nic(bp, false, false); 7715 } 7716 7717 return rc; 7718 } 7719 7720 /* rtnl_lock held */ 7721 static int bnxt_change_mtu(struct net_device *dev, int new_mtu) 7722 { 7723 struct bnxt *bp = netdev_priv(dev); 7724 7725 if (netif_running(dev)) 7726 bnxt_close_nic(bp, false, false); 7727 7728 dev->mtu = new_mtu; 7729 bnxt_set_ring_params(bp); 7730 7731 if (netif_running(dev)) 7732 return bnxt_open_nic(bp, false, false); 7733 7734 return 0; 7735 } 7736 7737 int bnxt_setup_mq_tc(struct net_device *dev, u8 tc) 7738 { 7739 struct bnxt *bp = netdev_priv(dev); 7740 bool sh = false; 7741 int rc; 7742 7743 if (tc > bp->max_tc) { 7744 netdev_err(dev, "Too many traffic classes requested: %d. Max supported is %d.\n", 7745 tc, bp->max_tc); 7746 return -EINVAL; 7747 } 7748 7749 if (netdev_get_num_tc(dev) == tc) 7750 return 0; 7751 7752 if (bp->flags & BNXT_FLAG_SHARED_RINGS) 7753 sh = true; 7754 7755 rc = bnxt_check_rings(bp, bp->tx_nr_rings_per_tc, bp->rx_nr_rings, 7756 sh, tc, bp->tx_nr_rings_xdp); 7757 if (rc) 7758 return rc; 7759 7760 /* Needs to close the device and do hw resource re-allocations */ 7761 if (netif_running(bp->dev)) 7762 bnxt_close_nic(bp, true, false); 7763 7764 if (tc) { 7765 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tc; 7766 netdev_set_num_tc(dev, tc); 7767 } else { 7768 bp->tx_nr_rings = bp->tx_nr_rings_per_tc; 7769 netdev_reset_tc(dev); 7770 } 7771 bp->tx_nr_rings += bp->tx_nr_rings_xdp; 7772 bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) : 7773 bp->tx_nr_rings + bp->rx_nr_rings; 7774 bp->num_stat_ctxs = bp->cp_nr_rings; 7775 7776 if (netif_running(bp->dev)) 7777 return bnxt_open_nic(bp, true, false); 7778 7779 return 0; 7780 } 7781 7782 static int bnxt_setup_tc_block_cb(enum tc_setup_type type, void *type_data, 7783 void *cb_priv) 7784 { 7785 struct bnxt *bp = cb_priv; 7786 7787 if (!bnxt_tc_flower_enabled(bp) || 7788 !tc_cls_can_offload_and_chain0(bp->dev, type_data)) 7789 return -EOPNOTSUPP; 7790 7791 switch (type) { 7792 case TC_SETUP_CLSFLOWER: 7793 return bnxt_tc_setup_flower(bp, bp->pf.fw_fid, type_data); 7794 default: 7795 return -EOPNOTSUPP; 7796 } 7797 } 7798 7799 static int bnxt_setup_tc_block(struct net_device *dev, 7800 struct tc_block_offload *f) 7801 { 7802 struct bnxt *bp = netdev_priv(dev); 7803 7804 if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS) 7805 return -EOPNOTSUPP; 7806 7807 switch (f->command) { 7808 case TC_BLOCK_BIND: 7809 return tcf_block_cb_register(f->block, bnxt_setup_tc_block_cb, 7810 bp, bp); 7811 case TC_BLOCK_UNBIND: 7812 tcf_block_cb_unregister(f->block, bnxt_setup_tc_block_cb, bp); 7813 return 0; 7814 default: 7815 return -EOPNOTSUPP; 7816 } 7817 } 7818 7819 static int bnxt_setup_tc(struct net_device *dev, enum tc_setup_type type, 7820 void *type_data) 7821 { 7822 switch (type) { 7823 case TC_SETUP_BLOCK: 7824 return bnxt_setup_tc_block(dev, type_data); 7825 case TC_SETUP_QDISC_MQPRIO: { 7826 struct tc_mqprio_qopt *mqprio = type_data; 7827 7828 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS; 7829 7830 return bnxt_setup_mq_tc(dev, mqprio->num_tc); 7831 } 7832 default: 7833 return -EOPNOTSUPP; 7834 } 7835 } 7836 7837 #ifdef CONFIG_RFS_ACCEL 7838 static bool bnxt_fltr_match(struct bnxt_ntuple_filter *f1, 7839 struct bnxt_ntuple_filter *f2) 7840 { 7841 struct flow_keys *keys1 = &f1->fkeys; 7842 struct flow_keys *keys2 = &f2->fkeys; 7843 7844 if (keys1->addrs.v4addrs.src == keys2->addrs.v4addrs.src && 7845 keys1->addrs.v4addrs.dst == keys2->addrs.v4addrs.dst && 7846 keys1->ports.ports == keys2->ports.ports && 7847 keys1->basic.ip_proto == keys2->basic.ip_proto && 7848 keys1->basic.n_proto == keys2->basic.n_proto && 7849 keys1->control.flags == keys2->control.flags && 7850 ether_addr_equal(f1->src_mac_addr, f2->src_mac_addr) && 7851 ether_addr_equal(f1->dst_mac_addr, f2->dst_mac_addr)) 7852 return true; 7853 7854 return false; 7855 } 7856 7857 static int bnxt_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb, 7858 u16 rxq_index, u32 flow_id) 7859 { 7860 struct bnxt *bp = netdev_priv(dev); 7861 struct bnxt_ntuple_filter *fltr, *new_fltr; 7862 struct flow_keys *fkeys; 7863 struct ethhdr *eth = (struct ethhdr *)skb_mac_header(skb); 7864 int rc = 0, idx, bit_id, l2_idx = 0; 7865 struct hlist_head *head; 7866 7867 if (!ether_addr_equal(dev->dev_addr, eth->h_dest)) { 7868 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 7869 int off = 0, j; 7870 7871 netif_addr_lock_bh(dev); 7872 for (j = 0; j < vnic->uc_filter_count; j++, off += ETH_ALEN) { 7873 if (ether_addr_equal(eth->h_dest, 7874 vnic->uc_list + off)) { 7875 l2_idx = j + 1; 7876 break; 7877 } 7878 } 7879 netif_addr_unlock_bh(dev); 7880 if (!l2_idx) 7881 return -EINVAL; 7882 } 7883 new_fltr = kzalloc(sizeof(*new_fltr), GFP_ATOMIC); 7884 if (!new_fltr) 7885 return -ENOMEM; 7886 7887 fkeys = &new_fltr->fkeys; 7888 if (!skb_flow_dissect_flow_keys(skb, fkeys, 0)) { 7889 rc = -EPROTONOSUPPORT; 7890 goto err_free; 7891 } 7892 7893 if ((fkeys->basic.n_proto != htons(ETH_P_IP) && 7894 fkeys->basic.n_proto != htons(ETH_P_IPV6)) || 7895 ((fkeys->basic.ip_proto != IPPROTO_TCP) && 7896 (fkeys->basic.ip_proto != IPPROTO_UDP))) { 7897 rc = -EPROTONOSUPPORT; 7898 goto err_free; 7899 } 7900 if (fkeys->basic.n_proto == htons(ETH_P_IPV6) && 7901 bp->hwrm_spec_code < 0x10601) { 7902 rc = -EPROTONOSUPPORT; 7903 goto err_free; 7904 } 7905 if ((fkeys->control.flags & FLOW_DIS_ENCAPSULATION) && 7906 bp->hwrm_spec_code < 0x10601) { 7907 rc = -EPROTONOSUPPORT; 7908 goto err_free; 7909 } 7910 7911 memcpy(new_fltr->dst_mac_addr, eth->h_dest, ETH_ALEN); 7912 memcpy(new_fltr->src_mac_addr, eth->h_source, ETH_ALEN); 7913 7914 idx = skb_get_hash_raw(skb) & BNXT_NTP_FLTR_HASH_MASK; 7915 head = &bp->ntp_fltr_hash_tbl[idx]; 7916 rcu_read_lock(); 7917 hlist_for_each_entry_rcu(fltr, head, hash) { 7918 if (bnxt_fltr_match(fltr, new_fltr)) { 7919 rcu_read_unlock(); 7920 rc = 0; 7921 goto err_free; 7922 } 7923 } 7924 rcu_read_unlock(); 7925 7926 spin_lock_bh(&bp->ntp_fltr_lock); 7927 bit_id = bitmap_find_free_region(bp->ntp_fltr_bmap, 7928 BNXT_NTP_FLTR_MAX_FLTR, 0); 7929 if (bit_id < 0) { 7930 spin_unlock_bh(&bp->ntp_fltr_lock); 7931 rc = -ENOMEM; 7932 goto err_free; 7933 } 7934 7935 new_fltr->sw_id = (u16)bit_id; 7936 new_fltr->flow_id = flow_id; 7937 new_fltr->l2_fltr_idx = l2_idx; 7938 new_fltr->rxq = rxq_index; 7939 hlist_add_head_rcu(&new_fltr->hash, head); 7940 bp->ntp_fltr_count++; 7941 spin_unlock_bh(&bp->ntp_fltr_lock); 7942 7943 set_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event); 7944 bnxt_queue_sp_work(bp); 7945 7946 return new_fltr->sw_id; 7947 7948 err_free: 7949 kfree(new_fltr); 7950 return rc; 7951 } 7952 7953 static void bnxt_cfg_ntp_filters(struct bnxt *bp) 7954 { 7955 int i; 7956 7957 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) { 7958 struct hlist_head *head; 7959 struct hlist_node *tmp; 7960 struct bnxt_ntuple_filter *fltr; 7961 int rc; 7962 7963 head = &bp->ntp_fltr_hash_tbl[i]; 7964 hlist_for_each_entry_safe(fltr, tmp, head, hash) { 7965 bool del = false; 7966 7967 if (test_bit(BNXT_FLTR_VALID, &fltr->state)) { 7968 if (rps_may_expire_flow(bp->dev, fltr->rxq, 7969 fltr->flow_id, 7970 fltr->sw_id)) { 7971 bnxt_hwrm_cfa_ntuple_filter_free(bp, 7972 fltr); 7973 del = true; 7974 } 7975 } else { 7976 rc = bnxt_hwrm_cfa_ntuple_filter_alloc(bp, 7977 fltr); 7978 if (rc) 7979 del = true; 7980 else 7981 set_bit(BNXT_FLTR_VALID, &fltr->state); 7982 } 7983 7984 if (del) { 7985 spin_lock_bh(&bp->ntp_fltr_lock); 7986 hlist_del_rcu(&fltr->hash); 7987 bp->ntp_fltr_count--; 7988 spin_unlock_bh(&bp->ntp_fltr_lock); 7989 synchronize_rcu(); 7990 clear_bit(fltr->sw_id, bp->ntp_fltr_bmap); 7991 kfree(fltr); 7992 } 7993 } 7994 } 7995 if (test_and_clear_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event)) 7996 netdev_info(bp->dev, "Receive PF driver unload event!"); 7997 } 7998 7999 #else 8000 8001 static void bnxt_cfg_ntp_filters(struct bnxt *bp) 8002 { 8003 } 8004 8005 #endif /* CONFIG_RFS_ACCEL */ 8006 8007 static void bnxt_udp_tunnel_add(struct net_device *dev, 8008 struct udp_tunnel_info *ti) 8009 { 8010 struct bnxt *bp = netdev_priv(dev); 8011 8012 if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET) 8013 return; 8014 8015 if (!netif_running(dev)) 8016 return; 8017 8018 switch (ti->type) { 8019 case UDP_TUNNEL_TYPE_VXLAN: 8020 if (bp->vxlan_port_cnt && bp->vxlan_port != ti->port) 8021 return; 8022 8023 bp->vxlan_port_cnt++; 8024 if (bp->vxlan_port_cnt == 1) { 8025 bp->vxlan_port = ti->port; 8026 set_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event); 8027 bnxt_queue_sp_work(bp); 8028 } 8029 break; 8030 case UDP_TUNNEL_TYPE_GENEVE: 8031 if (bp->nge_port_cnt && bp->nge_port != ti->port) 8032 return; 8033 8034 bp->nge_port_cnt++; 8035 if (bp->nge_port_cnt == 1) { 8036 bp->nge_port = ti->port; 8037 set_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event); 8038 } 8039 break; 8040 default: 8041 return; 8042 } 8043 8044 bnxt_queue_sp_work(bp); 8045 } 8046 8047 static void bnxt_udp_tunnel_del(struct net_device *dev, 8048 struct udp_tunnel_info *ti) 8049 { 8050 struct bnxt *bp = netdev_priv(dev); 8051 8052 if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET) 8053 return; 8054 8055 if (!netif_running(dev)) 8056 return; 8057 8058 switch (ti->type) { 8059 case UDP_TUNNEL_TYPE_VXLAN: 8060 if (!bp->vxlan_port_cnt || bp->vxlan_port != ti->port) 8061 return; 8062 bp->vxlan_port_cnt--; 8063 8064 if (bp->vxlan_port_cnt != 0) 8065 return; 8066 8067 set_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event); 8068 break; 8069 case UDP_TUNNEL_TYPE_GENEVE: 8070 if (!bp->nge_port_cnt || bp->nge_port != ti->port) 8071 return; 8072 bp->nge_port_cnt--; 8073 8074 if (bp->nge_port_cnt != 0) 8075 return; 8076 8077 set_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event); 8078 break; 8079 default: 8080 return; 8081 } 8082 8083 bnxt_queue_sp_work(bp); 8084 } 8085 8086 static int bnxt_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq, 8087 struct net_device *dev, u32 filter_mask, 8088 int nlflags) 8089 { 8090 struct bnxt *bp = netdev_priv(dev); 8091 8092 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, bp->br_mode, 0, 0, 8093 nlflags, filter_mask, NULL); 8094 } 8095 8096 static int bnxt_bridge_setlink(struct net_device *dev, struct nlmsghdr *nlh, 8097 u16 flags) 8098 { 8099 struct bnxt *bp = netdev_priv(dev); 8100 struct nlattr *attr, *br_spec; 8101 int rem, rc = 0; 8102 8103 if (bp->hwrm_spec_code < 0x10708 || !BNXT_SINGLE_PF(bp)) 8104 return -EOPNOTSUPP; 8105 8106 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC); 8107 if (!br_spec) 8108 return -EINVAL; 8109 8110 nla_for_each_nested(attr, br_spec, rem) { 8111 u16 mode; 8112 8113 if (nla_type(attr) != IFLA_BRIDGE_MODE) 8114 continue; 8115 8116 if (nla_len(attr) < sizeof(mode)) 8117 return -EINVAL; 8118 8119 mode = nla_get_u16(attr); 8120 if (mode == bp->br_mode) 8121 break; 8122 8123 rc = bnxt_hwrm_set_br_mode(bp, mode); 8124 if (!rc) 8125 bp->br_mode = mode; 8126 break; 8127 } 8128 return rc; 8129 } 8130 8131 static int bnxt_get_phys_port_name(struct net_device *dev, char *buf, 8132 size_t len) 8133 { 8134 struct bnxt *bp = netdev_priv(dev); 8135 int rc; 8136 8137 /* The PF and it's VF-reps only support the switchdev framework */ 8138 if (!BNXT_PF(bp)) 8139 return -EOPNOTSUPP; 8140 8141 rc = snprintf(buf, len, "p%d", bp->pf.port_id); 8142 8143 if (rc >= len) 8144 return -EOPNOTSUPP; 8145 return 0; 8146 } 8147 8148 int bnxt_port_attr_get(struct bnxt *bp, struct switchdev_attr *attr) 8149 { 8150 if (bp->eswitch_mode != DEVLINK_ESWITCH_MODE_SWITCHDEV) 8151 return -EOPNOTSUPP; 8152 8153 /* The PF and it's VF-reps only support the switchdev framework */ 8154 if (!BNXT_PF(bp)) 8155 return -EOPNOTSUPP; 8156 8157 switch (attr->id) { 8158 case SWITCHDEV_ATTR_ID_PORT_PARENT_ID: 8159 attr->u.ppid.id_len = sizeof(bp->switch_id); 8160 memcpy(attr->u.ppid.id, bp->switch_id, attr->u.ppid.id_len); 8161 break; 8162 default: 8163 return -EOPNOTSUPP; 8164 } 8165 return 0; 8166 } 8167 8168 static int bnxt_swdev_port_attr_get(struct net_device *dev, 8169 struct switchdev_attr *attr) 8170 { 8171 return bnxt_port_attr_get(netdev_priv(dev), attr); 8172 } 8173 8174 static const struct switchdev_ops bnxt_switchdev_ops = { 8175 .switchdev_port_attr_get = bnxt_swdev_port_attr_get 8176 }; 8177 8178 static const struct net_device_ops bnxt_netdev_ops = { 8179 .ndo_open = bnxt_open, 8180 .ndo_start_xmit = bnxt_start_xmit, 8181 .ndo_stop = bnxt_close, 8182 .ndo_get_stats64 = bnxt_get_stats64, 8183 .ndo_set_rx_mode = bnxt_set_rx_mode, 8184 .ndo_do_ioctl = bnxt_ioctl, 8185 .ndo_validate_addr = eth_validate_addr, 8186 .ndo_set_mac_address = bnxt_change_mac_addr, 8187 .ndo_change_mtu = bnxt_change_mtu, 8188 .ndo_fix_features = bnxt_fix_features, 8189 .ndo_set_features = bnxt_set_features, 8190 .ndo_tx_timeout = bnxt_tx_timeout, 8191 #ifdef CONFIG_BNXT_SRIOV 8192 .ndo_get_vf_config = bnxt_get_vf_config, 8193 .ndo_set_vf_mac = bnxt_set_vf_mac, 8194 .ndo_set_vf_vlan = bnxt_set_vf_vlan, 8195 .ndo_set_vf_rate = bnxt_set_vf_bw, 8196 .ndo_set_vf_link_state = bnxt_set_vf_link_state, 8197 .ndo_set_vf_spoofchk = bnxt_set_vf_spoofchk, 8198 #endif 8199 #ifdef CONFIG_NET_POLL_CONTROLLER 8200 .ndo_poll_controller = bnxt_poll_controller, 8201 #endif 8202 .ndo_setup_tc = bnxt_setup_tc, 8203 #ifdef CONFIG_RFS_ACCEL 8204 .ndo_rx_flow_steer = bnxt_rx_flow_steer, 8205 #endif 8206 .ndo_udp_tunnel_add = bnxt_udp_tunnel_add, 8207 .ndo_udp_tunnel_del = bnxt_udp_tunnel_del, 8208 .ndo_bpf = bnxt_xdp, 8209 .ndo_bridge_getlink = bnxt_bridge_getlink, 8210 .ndo_bridge_setlink = bnxt_bridge_setlink, 8211 .ndo_get_phys_port_name = bnxt_get_phys_port_name 8212 }; 8213 8214 static void bnxt_remove_one(struct pci_dev *pdev) 8215 { 8216 struct net_device *dev = pci_get_drvdata(pdev); 8217 struct bnxt *bp = netdev_priv(dev); 8218 8219 if (BNXT_PF(bp)) { 8220 bnxt_sriov_disable(bp); 8221 bnxt_dl_unregister(bp); 8222 } 8223 8224 pci_disable_pcie_error_reporting(pdev); 8225 unregister_netdev(dev); 8226 bnxt_shutdown_tc(bp); 8227 bnxt_cancel_sp_work(bp); 8228 bp->sp_event = 0; 8229 8230 bnxt_clear_int_mode(bp); 8231 bnxt_hwrm_func_drv_unrgtr(bp); 8232 bnxt_free_hwrm_resources(bp); 8233 bnxt_free_hwrm_short_cmd_req(bp); 8234 bnxt_ethtool_free(bp); 8235 bnxt_dcb_free(bp); 8236 kfree(bp->edev); 8237 bp->edev = NULL; 8238 bnxt_cleanup_pci(bp); 8239 free_netdev(dev); 8240 } 8241 8242 static int bnxt_probe_phy(struct bnxt *bp) 8243 { 8244 int rc = 0; 8245 struct bnxt_link_info *link_info = &bp->link_info; 8246 8247 rc = bnxt_hwrm_phy_qcaps(bp); 8248 if (rc) { 8249 netdev_err(bp->dev, "Probe phy can't get phy capabilities (rc: %x)\n", 8250 rc); 8251 return rc; 8252 } 8253 mutex_init(&bp->link_lock); 8254 8255 rc = bnxt_update_link(bp, false); 8256 if (rc) { 8257 netdev_err(bp->dev, "Probe phy can't update link (rc: %x)\n", 8258 rc); 8259 return rc; 8260 } 8261 8262 /* Older firmware does not have supported_auto_speeds, so assume 8263 * that all supported speeds can be autonegotiated. 8264 */ 8265 if (link_info->auto_link_speeds && !link_info->support_auto_speeds) 8266 link_info->support_auto_speeds = link_info->support_speeds; 8267 8268 /*initialize the ethool setting copy with NVM settings */ 8269 if (BNXT_AUTO_MODE(link_info->auto_mode)) { 8270 link_info->autoneg = BNXT_AUTONEG_SPEED; 8271 if (bp->hwrm_spec_code >= 0x10201) { 8272 if (link_info->auto_pause_setting & 8273 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE) 8274 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL; 8275 } else { 8276 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL; 8277 } 8278 link_info->advertising = link_info->auto_link_speeds; 8279 } else { 8280 link_info->req_link_speed = link_info->force_link_speed; 8281 link_info->req_duplex = link_info->duplex_setting; 8282 } 8283 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) 8284 link_info->req_flow_ctrl = 8285 link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH; 8286 else 8287 link_info->req_flow_ctrl = link_info->force_pause_setting; 8288 return rc; 8289 } 8290 8291 static int bnxt_get_max_irq(struct pci_dev *pdev) 8292 { 8293 u16 ctrl; 8294 8295 if (!pdev->msix_cap) 8296 return 1; 8297 8298 pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &ctrl); 8299 return (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1; 8300 } 8301 8302 static void _bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx, 8303 int *max_cp) 8304 { 8305 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 8306 int max_ring_grps = 0; 8307 8308 *max_tx = hw_resc->max_tx_rings; 8309 *max_rx = hw_resc->max_rx_rings; 8310 *max_cp = min_t(int, hw_resc->max_irqs, hw_resc->max_cp_rings); 8311 *max_cp = min_t(int, *max_cp, hw_resc->max_stat_ctxs); 8312 max_ring_grps = hw_resc->max_hw_ring_grps; 8313 if (BNXT_CHIP_TYPE_NITRO_A0(bp) && BNXT_PF(bp)) { 8314 *max_cp -= 1; 8315 *max_rx -= 2; 8316 } 8317 if (bp->flags & BNXT_FLAG_AGG_RINGS) 8318 *max_rx >>= 1; 8319 *max_rx = min_t(int, *max_rx, max_ring_grps); 8320 } 8321 8322 int bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx, bool shared) 8323 { 8324 int rx, tx, cp; 8325 8326 _bnxt_get_max_rings(bp, &rx, &tx, &cp); 8327 if (!rx || !tx || !cp) 8328 return -ENOMEM; 8329 8330 *max_rx = rx; 8331 *max_tx = tx; 8332 return bnxt_trim_rings(bp, max_rx, max_tx, cp, shared); 8333 } 8334 8335 static int bnxt_get_dflt_rings(struct bnxt *bp, int *max_rx, int *max_tx, 8336 bool shared) 8337 { 8338 int rc; 8339 8340 rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared); 8341 if (rc && (bp->flags & BNXT_FLAG_AGG_RINGS)) { 8342 /* Not enough rings, try disabling agg rings. */ 8343 bp->flags &= ~BNXT_FLAG_AGG_RINGS; 8344 rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared); 8345 if (rc) 8346 return rc; 8347 bp->flags |= BNXT_FLAG_NO_AGG_RINGS; 8348 bp->dev->hw_features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW); 8349 bp->dev->features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW); 8350 bnxt_set_ring_params(bp); 8351 } 8352 8353 if (bp->flags & BNXT_FLAG_ROCE_CAP) { 8354 int max_cp, max_stat, max_irq; 8355 8356 /* Reserve minimum resources for RoCE */ 8357 max_cp = bnxt_get_max_func_cp_rings(bp); 8358 max_stat = bnxt_get_max_func_stat_ctxs(bp); 8359 max_irq = bnxt_get_max_func_irqs(bp); 8360 if (max_cp <= BNXT_MIN_ROCE_CP_RINGS || 8361 max_irq <= BNXT_MIN_ROCE_CP_RINGS || 8362 max_stat <= BNXT_MIN_ROCE_STAT_CTXS) 8363 return 0; 8364 8365 max_cp -= BNXT_MIN_ROCE_CP_RINGS; 8366 max_irq -= BNXT_MIN_ROCE_CP_RINGS; 8367 max_stat -= BNXT_MIN_ROCE_STAT_CTXS; 8368 max_cp = min_t(int, max_cp, max_irq); 8369 max_cp = min_t(int, max_cp, max_stat); 8370 rc = bnxt_trim_rings(bp, max_rx, max_tx, max_cp, shared); 8371 if (rc) 8372 rc = 0; 8373 } 8374 return rc; 8375 } 8376 8377 /* In initial default shared ring setting, each shared ring must have a 8378 * RX/TX ring pair. 8379 */ 8380 static void bnxt_trim_dflt_sh_rings(struct bnxt *bp) 8381 { 8382 bp->cp_nr_rings = min_t(int, bp->tx_nr_rings_per_tc, bp->rx_nr_rings); 8383 bp->rx_nr_rings = bp->cp_nr_rings; 8384 bp->tx_nr_rings_per_tc = bp->cp_nr_rings; 8385 bp->tx_nr_rings = bp->tx_nr_rings_per_tc; 8386 } 8387 8388 static int bnxt_set_dflt_rings(struct bnxt *bp, bool sh) 8389 { 8390 int dflt_rings, max_rx_rings, max_tx_rings, rc; 8391 8392 if (sh) 8393 bp->flags |= BNXT_FLAG_SHARED_RINGS; 8394 dflt_rings = netif_get_num_default_rss_queues(); 8395 /* Reduce default rings to reduce memory usage on multi-port cards */ 8396 if (bp->port_count > 1) 8397 dflt_rings = min_t(int, dflt_rings, 4); 8398 rc = bnxt_get_dflt_rings(bp, &max_rx_rings, &max_tx_rings, sh); 8399 if (rc) 8400 return rc; 8401 bp->rx_nr_rings = min_t(int, dflt_rings, max_rx_rings); 8402 bp->tx_nr_rings_per_tc = min_t(int, dflt_rings, max_tx_rings); 8403 if (sh) 8404 bnxt_trim_dflt_sh_rings(bp); 8405 else 8406 bp->cp_nr_rings = bp->tx_nr_rings_per_tc + bp->rx_nr_rings; 8407 bp->tx_nr_rings = bp->tx_nr_rings_per_tc; 8408 8409 rc = __bnxt_reserve_rings(bp); 8410 if (rc) 8411 netdev_warn(bp->dev, "Unable to reserve tx rings\n"); 8412 bp->tx_nr_rings_per_tc = bp->tx_nr_rings; 8413 if (sh) 8414 bnxt_trim_dflt_sh_rings(bp); 8415 8416 /* Rings may have been trimmed, re-reserve the trimmed rings. */ 8417 if (bnxt_need_reserve_rings(bp)) { 8418 rc = __bnxt_reserve_rings(bp); 8419 if (rc) 8420 netdev_warn(bp->dev, "2nd rings reservation failed.\n"); 8421 bp->tx_nr_rings_per_tc = bp->tx_nr_rings; 8422 } 8423 bp->num_stat_ctxs = bp->cp_nr_rings; 8424 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) { 8425 bp->rx_nr_rings++; 8426 bp->cp_nr_rings++; 8427 } 8428 return rc; 8429 } 8430 8431 int bnxt_restore_pf_fw_resources(struct bnxt *bp) 8432 { 8433 int rc; 8434 8435 ASSERT_RTNL(); 8436 if (bnxt_ulp_registered(bp->edev, BNXT_ROCE_ULP)) 8437 return 0; 8438 8439 bnxt_hwrm_func_qcaps(bp); 8440 __bnxt_close_nic(bp, true, false); 8441 bnxt_clear_int_mode(bp); 8442 rc = bnxt_init_int_mode(bp); 8443 if (rc) 8444 dev_close(bp->dev); 8445 else 8446 rc = bnxt_open_nic(bp, true, false); 8447 return rc; 8448 } 8449 8450 static int bnxt_init_mac_addr(struct bnxt *bp) 8451 { 8452 int rc = 0; 8453 8454 if (BNXT_PF(bp)) { 8455 memcpy(bp->dev->dev_addr, bp->pf.mac_addr, ETH_ALEN); 8456 } else { 8457 #ifdef CONFIG_BNXT_SRIOV 8458 struct bnxt_vf_info *vf = &bp->vf; 8459 8460 if (is_valid_ether_addr(vf->mac_addr)) { 8461 /* overwrite netdev dev_addr with admin VF MAC */ 8462 memcpy(bp->dev->dev_addr, vf->mac_addr, ETH_ALEN); 8463 } else { 8464 eth_hw_addr_random(bp->dev); 8465 rc = bnxt_approve_mac(bp, bp->dev->dev_addr); 8466 } 8467 #endif 8468 } 8469 return rc; 8470 } 8471 8472 static void bnxt_parse_log_pcie_link(struct bnxt *bp) 8473 { 8474 enum pcie_link_width width = PCIE_LNK_WIDTH_UNKNOWN; 8475 enum pci_bus_speed speed = PCI_SPEED_UNKNOWN; 8476 8477 if (pcie_get_minimum_link(pci_physfn(bp->pdev), &speed, &width) || 8478 speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN) 8479 netdev_info(bp->dev, "Failed to determine PCIe Link Info\n"); 8480 else 8481 netdev_info(bp->dev, "PCIe: Speed %s Width x%d\n", 8482 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" : 8483 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" : 8484 speed == PCIE_SPEED_8_0GT ? "8.0GT/s" : 8485 "Unknown", width); 8486 } 8487 8488 static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 8489 { 8490 static int version_printed; 8491 struct net_device *dev; 8492 struct bnxt *bp; 8493 int rc, max_irqs; 8494 8495 if (pci_is_bridge(pdev)) 8496 return -ENODEV; 8497 8498 if (version_printed++ == 0) 8499 pr_info("%s", version); 8500 8501 max_irqs = bnxt_get_max_irq(pdev); 8502 dev = alloc_etherdev_mq(sizeof(*bp), max_irqs); 8503 if (!dev) 8504 return -ENOMEM; 8505 8506 bp = netdev_priv(dev); 8507 8508 if (bnxt_vf_pciid(ent->driver_data)) 8509 bp->flags |= BNXT_FLAG_VF; 8510 8511 if (pdev->msix_cap) 8512 bp->flags |= BNXT_FLAG_MSIX_CAP; 8513 8514 rc = bnxt_init_board(pdev, dev); 8515 if (rc < 0) 8516 goto init_err_free; 8517 8518 dev->netdev_ops = &bnxt_netdev_ops; 8519 dev->watchdog_timeo = BNXT_TX_TIMEOUT; 8520 dev->ethtool_ops = &bnxt_ethtool_ops; 8521 SWITCHDEV_SET_OPS(dev, &bnxt_switchdev_ops); 8522 pci_set_drvdata(pdev, dev); 8523 8524 rc = bnxt_alloc_hwrm_resources(bp); 8525 if (rc) 8526 goto init_err_pci_clean; 8527 8528 mutex_init(&bp->hwrm_cmd_lock); 8529 rc = bnxt_hwrm_ver_get(bp); 8530 if (rc) 8531 goto init_err_pci_clean; 8532 8533 if (bp->flags & BNXT_FLAG_SHORT_CMD) { 8534 rc = bnxt_alloc_hwrm_short_cmd_req(bp); 8535 if (rc) 8536 goto init_err_pci_clean; 8537 } 8538 8539 rc = bnxt_hwrm_func_reset(bp); 8540 if (rc) 8541 goto init_err_pci_clean; 8542 8543 bnxt_hwrm_fw_set_time(bp); 8544 8545 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG | 8546 NETIF_F_TSO | NETIF_F_TSO6 | 8547 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE | 8548 NETIF_F_GSO_IPXIP4 | 8549 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM | 8550 NETIF_F_GSO_PARTIAL | NETIF_F_RXHASH | 8551 NETIF_F_RXCSUM | NETIF_F_GRO; 8552 8553 if (!BNXT_CHIP_TYPE_NITRO_A0(bp)) 8554 dev->hw_features |= NETIF_F_LRO; 8555 8556 dev->hw_enc_features = 8557 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG | 8558 NETIF_F_TSO | NETIF_F_TSO6 | 8559 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE | 8560 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM | 8561 NETIF_F_GSO_IPXIP4 | NETIF_F_GSO_PARTIAL; 8562 dev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM | 8563 NETIF_F_GSO_GRE_CSUM; 8564 dev->vlan_features = dev->hw_features | NETIF_F_HIGHDMA; 8565 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX | 8566 NETIF_F_HW_VLAN_STAG_RX | NETIF_F_HW_VLAN_STAG_TX; 8567 if (!BNXT_CHIP_TYPE_NITRO_A0(bp)) 8568 dev->hw_features |= NETIF_F_GRO_HW; 8569 dev->features |= dev->hw_features | NETIF_F_HIGHDMA; 8570 if (dev->features & NETIF_F_GRO_HW) 8571 dev->features &= ~NETIF_F_LRO; 8572 dev->priv_flags |= IFF_UNICAST_FLT; 8573 8574 #ifdef CONFIG_BNXT_SRIOV 8575 init_waitqueue_head(&bp->sriov_cfg_wait); 8576 mutex_init(&bp->sriov_lock); 8577 #endif 8578 bp->gro_func = bnxt_gro_func_5730x; 8579 if (BNXT_CHIP_P4_PLUS(bp)) 8580 bp->gro_func = bnxt_gro_func_5731x; 8581 else 8582 bp->flags |= BNXT_FLAG_DOUBLE_DB; 8583 8584 rc = bnxt_hwrm_func_drv_rgtr(bp); 8585 if (rc) 8586 goto init_err_pci_clean; 8587 8588 rc = bnxt_hwrm_func_rgtr_async_events(bp, NULL, 0); 8589 if (rc) 8590 goto init_err_pci_clean; 8591 8592 bp->ulp_probe = bnxt_ulp_probe; 8593 8594 /* Get the MAX capabilities for this function */ 8595 rc = bnxt_hwrm_func_qcaps(bp); 8596 if (rc) { 8597 netdev_err(bp->dev, "hwrm query capability failure rc: %x\n", 8598 rc); 8599 rc = -1; 8600 goto init_err_pci_clean; 8601 } 8602 rc = bnxt_init_mac_addr(bp); 8603 if (rc) { 8604 dev_err(&pdev->dev, "Unable to initialize mac address.\n"); 8605 rc = -EADDRNOTAVAIL; 8606 goto init_err_pci_clean; 8607 } 8608 rc = bnxt_hwrm_queue_qportcfg(bp); 8609 if (rc) { 8610 netdev_err(bp->dev, "hwrm query qportcfg failure rc: %x\n", 8611 rc); 8612 rc = -1; 8613 goto init_err_pci_clean; 8614 } 8615 8616 bnxt_hwrm_func_qcfg(bp); 8617 bnxt_hwrm_port_led_qcaps(bp); 8618 bnxt_ethtool_init(bp); 8619 bnxt_dcb_init(bp); 8620 8621 /* MTU range: 60 - FW defined max */ 8622 dev->min_mtu = ETH_ZLEN; 8623 dev->max_mtu = bp->max_mtu; 8624 8625 rc = bnxt_probe_phy(bp); 8626 if (rc) 8627 goto init_err_pci_clean; 8628 8629 bnxt_set_rx_skb_mode(bp, false); 8630 bnxt_set_tpa_flags(bp); 8631 bnxt_set_ring_params(bp); 8632 bnxt_set_max_func_irqs(bp, max_irqs); 8633 rc = bnxt_set_dflt_rings(bp, true); 8634 if (rc) { 8635 netdev_err(bp->dev, "Not enough rings available.\n"); 8636 rc = -ENOMEM; 8637 goto init_err_pci_clean; 8638 } 8639 8640 /* Default RSS hash cfg. */ 8641 bp->rss_hash_cfg = VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 | 8642 VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 | 8643 VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 | 8644 VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6; 8645 if (BNXT_CHIP_P4_PLUS(bp) && bp->hwrm_spec_code >= 0x10501) { 8646 bp->flags |= BNXT_FLAG_UDP_RSS_CAP; 8647 bp->rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 | 8648 VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6; 8649 } 8650 8651 bnxt_hwrm_vnic_qcaps(bp); 8652 if (bnxt_rfs_supported(bp)) { 8653 dev->hw_features |= NETIF_F_NTUPLE; 8654 if (bnxt_rfs_capable(bp)) { 8655 bp->flags |= BNXT_FLAG_RFS; 8656 dev->features |= NETIF_F_NTUPLE; 8657 } 8658 } 8659 8660 if (dev->hw_features & NETIF_F_HW_VLAN_CTAG_RX) 8661 bp->flags |= BNXT_FLAG_STRIP_VLAN; 8662 8663 rc = bnxt_init_int_mode(bp); 8664 if (rc) 8665 goto init_err_pci_clean; 8666 8667 bnxt_get_wol_settings(bp); 8668 if (bp->flags & BNXT_FLAG_WOL_CAP) 8669 device_set_wakeup_enable(&pdev->dev, bp->wol); 8670 else 8671 device_set_wakeup_capable(&pdev->dev, false); 8672 8673 bnxt_hwrm_set_cache_line_size(bp, cache_line_size()); 8674 8675 if (BNXT_PF(bp)) { 8676 if (!bnxt_pf_wq) { 8677 bnxt_pf_wq = 8678 create_singlethread_workqueue("bnxt_pf_wq"); 8679 if (!bnxt_pf_wq) { 8680 dev_err(&pdev->dev, "Unable to create workqueue.\n"); 8681 goto init_err_pci_clean; 8682 } 8683 } 8684 bnxt_init_tc(bp); 8685 } 8686 8687 rc = register_netdev(dev); 8688 if (rc) 8689 goto init_err_cleanup_tc; 8690 8691 if (BNXT_PF(bp)) 8692 bnxt_dl_register(bp); 8693 8694 netdev_info(dev, "%s found at mem %lx, node addr %pM\n", 8695 board_info[ent->driver_data].name, 8696 (long)pci_resource_start(pdev, 0), dev->dev_addr); 8697 8698 bnxt_parse_log_pcie_link(bp); 8699 8700 return 0; 8701 8702 init_err_cleanup_tc: 8703 bnxt_shutdown_tc(bp); 8704 bnxt_clear_int_mode(bp); 8705 8706 init_err_pci_clean: 8707 bnxt_cleanup_pci(bp); 8708 8709 init_err_free: 8710 free_netdev(dev); 8711 return rc; 8712 } 8713 8714 static void bnxt_shutdown(struct pci_dev *pdev) 8715 { 8716 struct net_device *dev = pci_get_drvdata(pdev); 8717 struct bnxt *bp; 8718 8719 if (!dev) 8720 return; 8721 8722 rtnl_lock(); 8723 bp = netdev_priv(dev); 8724 if (!bp) 8725 goto shutdown_exit; 8726 8727 if (netif_running(dev)) 8728 dev_close(dev); 8729 8730 bnxt_ulp_shutdown(bp); 8731 8732 if (system_state == SYSTEM_POWER_OFF) { 8733 bnxt_clear_int_mode(bp); 8734 pci_wake_from_d3(pdev, bp->wol); 8735 pci_set_power_state(pdev, PCI_D3hot); 8736 } 8737 8738 shutdown_exit: 8739 rtnl_unlock(); 8740 } 8741 8742 #ifdef CONFIG_PM_SLEEP 8743 static int bnxt_suspend(struct device *device) 8744 { 8745 struct pci_dev *pdev = to_pci_dev(device); 8746 struct net_device *dev = pci_get_drvdata(pdev); 8747 struct bnxt *bp = netdev_priv(dev); 8748 int rc = 0; 8749 8750 rtnl_lock(); 8751 if (netif_running(dev)) { 8752 netif_device_detach(dev); 8753 rc = bnxt_close(dev); 8754 } 8755 bnxt_hwrm_func_drv_unrgtr(bp); 8756 rtnl_unlock(); 8757 return rc; 8758 } 8759 8760 static int bnxt_resume(struct device *device) 8761 { 8762 struct pci_dev *pdev = to_pci_dev(device); 8763 struct net_device *dev = pci_get_drvdata(pdev); 8764 struct bnxt *bp = netdev_priv(dev); 8765 int rc = 0; 8766 8767 rtnl_lock(); 8768 if (bnxt_hwrm_ver_get(bp) || bnxt_hwrm_func_drv_rgtr(bp)) { 8769 rc = -ENODEV; 8770 goto resume_exit; 8771 } 8772 rc = bnxt_hwrm_func_reset(bp); 8773 if (rc) { 8774 rc = -EBUSY; 8775 goto resume_exit; 8776 } 8777 bnxt_get_wol_settings(bp); 8778 if (netif_running(dev)) { 8779 rc = bnxt_open(dev); 8780 if (!rc) 8781 netif_device_attach(dev); 8782 } 8783 8784 resume_exit: 8785 rtnl_unlock(); 8786 return rc; 8787 } 8788 8789 static SIMPLE_DEV_PM_OPS(bnxt_pm_ops, bnxt_suspend, bnxt_resume); 8790 #define BNXT_PM_OPS (&bnxt_pm_ops) 8791 8792 #else 8793 8794 #define BNXT_PM_OPS NULL 8795 8796 #endif /* CONFIG_PM_SLEEP */ 8797 8798 /** 8799 * bnxt_io_error_detected - called when PCI error is detected 8800 * @pdev: Pointer to PCI device 8801 * @state: The current pci connection state 8802 * 8803 * This function is called after a PCI bus error affecting 8804 * this device has been detected. 8805 */ 8806 static pci_ers_result_t bnxt_io_error_detected(struct pci_dev *pdev, 8807 pci_channel_state_t state) 8808 { 8809 struct net_device *netdev = pci_get_drvdata(pdev); 8810 struct bnxt *bp = netdev_priv(netdev); 8811 8812 netdev_info(netdev, "PCI I/O error detected\n"); 8813 8814 rtnl_lock(); 8815 netif_device_detach(netdev); 8816 8817 bnxt_ulp_stop(bp); 8818 8819 if (state == pci_channel_io_perm_failure) { 8820 rtnl_unlock(); 8821 return PCI_ERS_RESULT_DISCONNECT; 8822 } 8823 8824 if (netif_running(netdev)) 8825 bnxt_close(netdev); 8826 8827 pci_disable_device(pdev); 8828 rtnl_unlock(); 8829 8830 /* Request a slot slot reset. */ 8831 return PCI_ERS_RESULT_NEED_RESET; 8832 } 8833 8834 /** 8835 * bnxt_io_slot_reset - called after the pci bus has been reset. 8836 * @pdev: Pointer to PCI device 8837 * 8838 * Restart the card from scratch, as if from a cold-boot. 8839 * At this point, the card has exprienced a hard reset, 8840 * followed by fixups by BIOS, and has its config space 8841 * set up identically to what it was at cold boot. 8842 */ 8843 static pci_ers_result_t bnxt_io_slot_reset(struct pci_dev *pdev) 8844 { 8845 struct net_device *netdev = pci_get_drvdata(pdev); 8846 struct bnxt *bp = netdev_priv(netdev); 8847 int err = 0; 8848 pci_ers_result_t result = PCI_ERS_RESULT_DISCONNECT; 8849 8850 netdev_info(bp->dev, "PCI Slot Reset\n"); 8851 8852 rtnl_lock(); 8853 8854 if (pci_enable_device(pdev)) { 8855 dev_err(&pdev->dev, 8856 "Cannot re-enable PCI device after reset.\n"); 8857 } else { 8858 pci_set_master(pdev); 8859 8860 err = bnxt_hwrm_func_reset(bp); 8861 if (!err && netif_running(netdev)) 8862 err = bnxt_open(netdev); 8863 8864 if (!err) { 8865 result = PCI_ERS_RESULT_RECOVERED; 8866 bnxt_ulp_start(bp); 8867 } 8868 } 8869 8870 if (result != PCI_ERS_RESULT_RECOVERED && netif_running(netdev)) 8871 dev_close(netdev); 8872 8873 rtnl_unlock(); 8874 8875 err = pci_cleanup_aer_uncorrect_error_status(pdev); 8876 if (err) { 8877 dev_err(&pdev->dev, 8878 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", 8879 err); /* non-fatal, continue */ 8880 } 8881 8882 return PCI_ERS_RESULT_RECOVERED; 8883 } 8884 8885 /** 8886 * bnxt_io_resume - called when traffic can start flowing again. 8887 * @pdev: Pointer to PCI device 8888 * 8889 * This callback is called when the error recovery driver tells 8890 * us that its OK to resume normal operation. 8891 */ 8892 static void bnxt_io_resume(struct pci_dev *pdev) 8893 { 8894 struct net_device *netdev = pci_get_drvdata(pdev); 8895 8896 rtnl_lock(); 8897 8898 netif_device_attach(netdev); 8899 8900 rtnl_unlock(); 8901 } 8902 8903 static const struct pci_error_handlers bnxt_err_handler = { 8904 .error_detected = bnxt_io_error_detected, 8905 .slot_reset = bnxt_io_slot_reset, 8906 .resume = bnxt_io_resume 8907 }; 8908 8909 static struct pci_driver bnxt_pci_driver = { 8910 .name = DRV_MODULE_NAME, 8911 .id_table = bnxt_pci_tbl, 8912 .probe = bnxt_init_one, 8913 .remove = bnxt_remove_one, 8914 .shutdown = bnxt_shutdown, 8915 .driver.pm = BNXT_PM_OPS, 8916 .err_handler = &bnxt_err_handler, 8917 #if defined(CONFIG_BNXT_SRIOV) 8918 .sriov_configure = bnxt_sriov_configure, 8919 #endif 8920 }; 8921 8922 static int __init bnxt_init(void) 8923 { 8924 return pci_register_driver(&bnxt_pci_driver); 8925 } 8926 8927 static void __exit bnxt_exit(void) 8928 { 8929 pci_unregister_driver(&bnxt_pci_driver); 8930 if (bnxt_pf_wq) 8931 destroy_workqueue(bnxt_pf_wq); 8932 } 8933 8934 module_init(bnxt_init); 8935 module_exit(bnxt_exit); 8936