1 /* Broadcom NetXtreme-C/E network driver. 2 * 3 * Copyright (c) 2014-2016 Broadcom Corporation 4 * Copyright (c) 2016-2019 Broadcom Limited 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation. 9 */ 10 11 #include <linux/module.h> 12 13 #include <linux/stringify.h> 14 #include <linux/kernel.h> 15 #include <linux/timer.h> 16 #include <linux/errno.h> 17 #include <linux/ioport.h> 18 #include <linux/slab.h> 19 #include <linux/vmalloc.h> 20 #include <linux/interrupt.h> 21 #include <linux/pci.h> 22 #include <linux/netdevice.h> 23 #include <linux/etherdevice.h> 24 #include <linux/skbuff.h> 25 #include <linux/dma-mapping.h> 26 #include <linux/bitops.h> 27 #include <linux/io.h> 28 #include <linux/irq.h> 29 #include <linux/delay.h> 30 #include <asm/byteorder.h> 31 #include <asm/page.h> 32 #include <linux/time.h> 33 #include <linux/mii.h> 34 #include <linux/mdio.h> 35 #include <linux/if.h> 36 #include <linux/if_vlan.h> 37 #include <linux/if_bridge.h> 38 #include <linux/rtc.h> 39 #include <linux/bpf.h> 40 #include <net/gro.h> 41 #include <net/ip.h> 42 #include <net/tcp.h> 43 #include <net/udp.h> 44 #include <net/checksum.h> 45 #include <net/ip6_checksum.h> 46 #include <net/udp_tunnel.h> 47 #include <linux/workqueue.h> 48 #include <linux/prefetch.h> 49 #include <linux/cache.h> 50 #include <linux/log2.h> 51 #include <linux/bitmap.h> 52 #include <linux/cpu_rmap.h> 53 #include <linux/cpumask.h> 54 #include <net/pkt_cls.h> 55 #include <linux/hwmon.h> 56 #include <linux/hwmon-sysfs.h> 57 #include <net/page_pool.h> 58 #include <linux/align.h> 59 #include <net/netdev_queues.h> 60 61 #include "bnxt_hsi.h" 62 #include "bnxt.h" 63 #include "bnxt_hwrm.h" 64 #include "bnxt_ulp.h" 65 #include "bnxt_sriov.h" 66 #include "bnxt_ethtool.h" 67 #include "bnxt_dcb.h" 68 #include "bnxt_xdp.h" 69 #include "bnxt_ptp.h" 70 #include "bnxt_vfr.h" 71 #include "bnxt_tc.h" 72 #include "bnxt_devlink.h" 73 #include "bnxt_debugfs.h" 74 75 #define BNXT_TX_TIMEOUT (5 * HZ) 76 #define BNXT_DEF_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_HW | \ 77 NETIF_MSG_TX_ERR) 78 79 MODULE_LICENSE("GPL"); 80 MODULE_DESCRIPTION("Broadcom BCM573xx network driver"); 81 82 #define BNXT_RX_OFFSET (NET_SKB_PAD + NET_IP_ALIGN) 83 #define BNXT_RX_DMA_OFFSET NET_SKB_PAD 84 #define BNXT_RX_COPY_THRESH 256 85 86 #define BNXT_TX_PUSH_THRESH 164 87 88 /* indexed by enum board_idx */ 89 static const struct { 90 char *name; 91 } board_info[] = { 92 [BCM57301] = { "Broadcom BCM57301 NetXtreme-C 10Gb Ethernet" }, 93 [BCM57302] = { "Broadcom BCM57302 NetXtreme-C 10Gb/25Gb Ethernet" }, 94 [BCM57304] = { "Broadcom BCM57304 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" }, 95 [BCM57417_NPAR] = { "Broadcom BCM57417 NetXtreme-E Ethernet Partition" }, 96 [BCM58700] = { "Broadcom BCM58700 Nitro 1Gb/2.5Gb/10Gb Ethernet" }, 97 [BCM57311] = { "Broadcom BCM57311 NetXtreme-C 10Gb Ethernet" }, 98 [BCM57312] = { "Broadcom BCM57312 NetXtreme-C 10Gb/25Gb Ethernet" }, 99 [BCM57402] = { "Broadcom BCM57402 NetXtreme-E 10Gb Ethernet" }, 100 [BCM57404] = { "Broadcom BCM57404 NetXtreme-E 10Gb/25Gb Ethernet" }, 101 [BCM57406] = { "Broadcom BCM57406 NetXtreme-E 10GBase-T Ethernet" }, 102 [BCM57402_NPAR] = { "Broadcom BCM57402 NetXtreme-E Ethernet Partition" }, 103 [BCM57407] = { "Broadcom BCM57407 NetXtreme-E 10GBase-T Ethernet" }, 104 [BCM57412] = { "Broadcom BCM57412 NetXtreme-E 10Gb Ethernet" }, 105 [BCM57414] = { "Broadcom BCM57414 NetXtreme-E 10Gb/25Gb Ethernet" }, 106 [BCM57416] = { "Broadcom BCM57416 NetXtreme-E 10GBase-T Ethernet" }, 107 [BCM57417] = { "Broadcom BCM57417 NetXtreme-E 10GBase-T Ethernet" }, 108 [BCM57412_NPAR] = { "Broadcom BCM57412 NetXtreme-E Ethernet Partition" }, 109 [BCM57314] = { "Broadcom BCM57314 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" }, 110 [BCM57417_SFP] = { "Broadcom BCM57417 NetXtreme-E 10Gb/25Gb Ethernet" }, 111 [BCM57416_SFP] = { "Broadcom BCM57416 NetXtreme-E 10Gb Ethernet" }, 112 [BCM57404_NPAR] = { "Broadcom BCM57404 NetXtreme-E Ethernet Partition" }, 113 [BCM57406_NPAR] = { "Broadcom BCM57406 NetXtreme-E Ethernet Partition" }, 114 [BCM57407_SFP] = { "Broadcom BCM57407 NetXtreme-E 25Gb Ethernet" }, 115 [BCM57407_NPAR] = { "Broadcom BCM57407 NetXtreme-E Ethernet Partition" }, 116 [BCM57414_NPAR] = { "Broadcom BCM57414 NetXtreme-E Ethernet Partition" }, 117 [BCM57416_NPAR] = { "Broadcom BCM57416 NetXtreme-E Ethernet Partition" }, 118 [BCM57452] = { "Broadcom BCM57452 NetXtreme-E 10Gb/25Gb/40Gb/50Gb Ethernet" }, 119 [BCM57454] = { "Broadcom BCM57454 NetXtreme-E 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" }, 120 [BCM5745x_NPAR] = { "Broadcom BCM5745x NetXtreme-E Ethernet Partition" }, 121 [BCM57508] = { "Broadcom BCM57508 NetXtreme-E 10Gb/25Gb/50Gb/100Gb/200Gb Ethernet" }, 122 [BCM57504] = { "Broadcom BCM57504 NetXtreme-E 10Gb/25Gb/50Gb/100Gb/200Gb Ethernet" }, 123 [BCM57502] = { "Broadcom BCM57502 NetXtreme-E 10Gb/25Gb/50Gb Ethernet" }, 124 [BCM57508_NPAR] = { "Broadcom BCM57508 NetXtreme-E Ethernet Partition" }, 125 [BCM57504_NPAR] = { "Broadcom BCM57504 NetXtreme-E Ethernet Partition" }, 126 [BCM57502_NPAR] = { "Broadcom BCM57502 NetXtreme-E Ethernet Partition" }, 127 [BCM58802] = { "Broadcom BCM58802 NetXtreme-S 10Gb/25Gb/40Gb/50Gb Ethernet" }, 128 [BCM58804] = { "Broadcom BCM58804 NetXtreme-S 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" }, 129 [BCM58808] = { "Broadcom BCM58808 NetXtreme-S 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" }, 130 [NETXTREME_E_VF] = { "Broadcom NetXtreme-E Ethernet Virtual Function" }, 131 [NETXTREME_C_VF] = { "Broadcom NetXtreme-C Ethernet Virtual Function" }, 132 [NETXTREME_S_VF] = { "Broadcom NetXtreme-S Ethernet Virtual Function" }, 133 [NETXTREME_C_VF_HV] = { "Broadcom NetXtreme-C Virtual Function for Hyper-V" }, 134 [NETXTREME_E_VF_HV] = { "Broadcom NetXtreme-E Virtual Function for Hyper-V" }, 135 [NETXTREME_E_P5_VF] = { "Broadcom BCM5750X NetXtreme-E Ethernet Virtual Function" }, 136 [NETXTREME_E_P5_VF_HV] = { "Broadcom BCM5750X NetXtreme-E Virtual Function for Hyper-V" }, 137 }; 138 139 static const struct pci_device_id bnxt_pci_tbl[] = { 140 { PCI_VDEVICE(BROADCOM, 0x1604), .driver_data = BCM5745x_NPAR }, 141 { PCI_VDEVICE(BROADCOM, 0x1605), .driver_data = BCM5745x_NPAR }, 142 { PCI_VDEVICE(BROADCOM, 0x1614), .driver_data = BCM57454 }, 143 { PCI_VDEVICE(BROADCOM, 0x16c0), .driver_data = BCM57417_NPAR }, 144 { PCI_VDEVICE(BROADCOM, 0x16c8), .driver_data = BCM57301 }, 145 { PCI_VDEVICE(BROADCOM, 0x16c9), .driver_data = BCM57302 }, 146 { PCI_VDEVICE(BROADCOM, 0x16ca), .driver_data = BCM57304 }, 147 { PCI_VDEVICE(BROADCOM, 0x16cc), .driver_data = BCM57417_NPAR }, 148 { PCI_VDEVICE(BROADCOM, 0x16cd), .driver_data = BCM58700 }, 149 { PCI_VDEVICE(BROADCOM, 0x16ce), .driver_data = BCM57311 }, 150 { PCI_VDEVICE(BROADCOM, 0x16cf), .driver_data = BCM57312 }, 151 { PCI_VDEVICE(BROADCOM, 0x16d0), .driver_data = BCM57402 }, 152 { PCI_VDEVICE(BROADCOM, 0x16d1), .driver_data = BCM57404 }, 153 { PCI_VDEVICE(BROADCOM, 0x16d2), .driver_data = BCM57406 }, 154 { PCI_VDEVICE(BROADCOM, 0x16d4), .driver_data = BCM57402_NPAR }, 155 { PCI_VDEVICE(BROADCOM, 0x16d5), .driver_data = BCM57407 }, 156 { PCI_VDEVICE(BROADCOM, 0x16d6), .driver_data = BCM57412 }, 157 { PCI_VDEVICE(BROADCOM, 0x16d7), .driver_data = BCM57414 }, 158 { PCI_VDEVICE(BROADCOM, 0x16d8), .driver_data = BCM57416 }, 159 { PCI_VDEVICE(BROADCOM, 0x16d9), .driver_data = BCM57417 }, 160 { PCI_VDEVICE(BROADCOM, 0x16de), .driver_data = BCM57412_NPAR }, 161 { PCI_VDEVICE(BROADCOM, 0x16df), .driver_data = BCM57314 }, 162 { PCI_VDEVICE(BROADCOM, 0x16e2), .driver_data = BCM57417_SFP }, 163 { PCI_VDEVICE(BROADCOM, 0x16e3), .driver_data = BCM57416_SFP }, 164 { PCI_VDEVICE(BROADCOM, 0x16e7), .driver_data = BCM57404_NPAR }, 165 { PCI_VDEVICE(BROADCOM, 0x16e8), .driver_data = BCM57406_NPAR }, 166 { PCI_VDEVICE(BROADCOM, 0x16e9), .driver_data = BCM57407_SFP }, 167 { PCI_VDEVICE(BROADCOM, 0x16ea), .driver_data = BCM57407_NPAR }, 168 { PCI_VDEVICE(BROADCOM, 0x16eb), .driver_data = BCM57412_NPAR }, 169 { PCI_VDEVICE(BROADCOM, 0x16ec), .driver_data = BCM57414_NPAR }, 170 { PCI_VDEVICE(BROADCOM, 0x16ed), .driver_data = BCM57414_NPAR }, 171 { PCI_VDEVICE(BROADCOM, 0x16ee), .driver_data = BCM57416_NPAR }, 172 { PCI_VDEVICE(BROADCOM, 0x16ef), .driver_data = BCM57416_NPAR }, 173 { PCI_VDEVICE(BROADCOM, 0x16f0), .driver_data = BCM58808 }, 174 { PCI_VDEVICE(BROADCOM, 0x16f1), .driver_data = BCM57452 }, 175 { PCI_VDEVICE(BROADCOM, 0x1750), .driver_data = BCM57508 }, 176 { PCI_VDEVICE(BROADCOM, 0x1751), .driver_data = BCM57504 }, 177 { PCI_VDEVICE(BROADCOM, 0x1752), .driver_data = BCM57502 }, 178 { PCI_VDEVICE(BROADCOM, 0x1800), .driver_data = BCM57502_NPAR }, 179 { PCI_VDEVICE(BROADCOM, 0x1801), .driver_data = BCM57504_NPAR }, 180 { PCI_VDEVICE(BROADCOM, 0x1802), .driver_data = BCM57508_NPAR }, 181 { PCI_VDEVICE(BROADCOM, 0x1803), .driver_data = BCM57502_NPAR }, 182 { PCI_VDEVICE(BROADCOM, 0x1804), .driver_data = BCM57504_NPAR }, 183 { PCI_VDEVICE(BROADCOM, 0x1805), .driver_data = BCM57508_NPAR }, 184 { PCI_VDEVICE(BROADCOM, 0xd802), .driver_data = BCM58802 }, 185 { PCI_VDEVICE(BROADCOM, 0xd804), .driver_data = BCM58804 }, 186 #ifdef CONFIG_BNXT_SRIOV 187 { PCI_VDEVICE(BROADCOM, 0x1606), .driver_data = NETXTREME_E_VF }, 188 { PCI_VDEVICE(BROADCOM, 0x1607), .driver_data = NETXTREME_E_VF_HV }, 189 { PCI_VDEVICE(BROADCOM, 0x1608), .driver_data = NETXTREME_E_VF_HV }, 190 { PCI_VDEVICE(BROADCOM, 0x1609), .driver_data = NETXTREME_E_VF }, 191 { PCI_VDEVICE(BROADCOM, 0x16bd), .driver_data = NETXTREME_E_VF_HV }, 192 { PCI_VDEVICE(BROADCOM, 0x16c1), .driver_data = NETXTREME_E_VF }, 193 { PCI_VDEVICE(BROADCOM, 0x16c2), .driver_data = NETXTREME_C_VF_HV }, 194 { PCI_VDEVICE(BROADCOM, 0x16c3), .driver_data = NETXTREME_C_VF_HV }, 195 { PCI_VDEVICE(BROADCOM, 0x16c4), .driver_data = NETXTREME_E_VF_HV }, 196 { PCI_VDEVICE(BROADCOM, 0x16c5), .driver_data = NETXTREME_E_VF_HV }, 197 { PCI_VDEVICE(BROADCOM, 0x16cb), .driver_data = NETXTREME_C_VF }, 198 { PCI_VDEVICE(BROADCOM, 0x16d3), .driver_data = NETXTREME_E_VF }, 199 { PCI_VDEVICE(BROADCOM, 0x16dc), .driver_data = NETXTREME_E_VF }, 200 { PCI_VDEVICE(BROADCOM, 0x16e1), .driver_data = NETXTREME_C_VF }, 201 { PCI_VDEVICE(BROADCOM, 0x16e5), .driver_data = NETXTREME_C_VF }, 202 { PCI_VDEVICE(BROADCOM, 0x16e6), .driver_data = NETXTREME_C_VF_HV }, 203 { PCI_VDEVICE(BROADCOM, 0x1806), .driver_data = NETXTREME_E_P5_VF }, 204 { PCI_VDEVICE(BROADCOM, 0x1807), .driver_data = NETXTREME_E_P5_VF }, 205 { PCI_VDEVICE(BROADCOM, 0x1808), .driver_data = NETXTREME_E_P5_VF_HV }, 206 { PCI_VDEVICE(BROADCOM, 0x1809), .driver_data = NETXTREME_E_P5_VF_HV }, 207 { PCI_VDEVICE(BROADCOM, 0xd800), .driver_data = NETXTREME_S_VF }, 208 #endif 209 { 0 } 210 }; 211 212 MODULE_DEVICE_TABLE(pci, bnxt_pci_tbl); 213 214 static const u16 bnxt_vf_req_snif[] = { 215 HWRM_FUNC_CFG, 216 HWRM_FUNC_VF_CFG, 217 HWRM_PORT_PHY_QCFG, 218 HWRM_CFA_L2_FILTER_ALLOC, 219 }; 220 221 static const u16 bnxt_async_events_arr[] = { 222 ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE, 223 ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE, 224 ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD, 225 ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED, 226 ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE, 227 ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE, 228 ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE, 229 ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY, 230 ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY, 231 ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION, 232 ASYNC_EVENT_CMPL_EVENT_ID_DEFERRED_RESPONSE, 233 ASYNC_EVENT_CMPL_EVENT_ID_RING_MONITOR_MSG, 234 ASYNC_EVENT_CMPL_EVENT_ID_ECHO_REQUEST, 235 ASYNC_EVENT_CMPL_EVENT_ID_PPS_TIMESTAMP, 236 ASYNC_EVENT_CMPL_EVENT_ID_ERROR_REPORT, 237 ASYNC_EVENT_CMPL_EVENT_ID_PHC_UPDATE, 238 }; 239 240 static struct workqueue_struct *bnxt_pf_wq; 241 242 static bool bnxt_vf_pciid(enum board_idx idx) 243 { 244 return (idx == NETXTREME_C_VF || idx == NETXTREME_E_VF || 245 idx == NETXTREME_S_VF || idx == NETXTREME_C_VF_HV || 246 idx == NETXTREME_E_VF_HV || idx == NETXTREME_E_P5_VF || 247 idx == NETXTREME_E_P5_VF_HV); 248 } 249 250 #define DB_CP_REARM_FLAGS (DB_KEY_CP | DB_IDX_VALID) 251 #define DB_CP_FLAGS (DB_KEY_CP | DB_IDX_VALID | DB_IRQ_DIS) 252 #define DB_CP_IRQ_DIS_FLAGS (DB_KEY_CP | DB_IRQ_DIS) 253 254 #define BNXT_CP_DB_IRQ_DIS(db) \ 255 writel(DB_CP_IRQ_DIS_FLAGS, db) 256 257 #define BNXT_DB_CQ(db, idx) \ 258 writel(DB_CP_FLAGS | RING_CMP(idx), (db)->doorbell) 259 260 #define BNXT_DB_NQ_P5(db, idx) \ 261 bnxt_writeq(bp, (db)->db_key64 | DBR_TYPE_NQ | RING_CMP(idx), \ 262 (db)->doorbell) 263 264 #define BNXT_DB_CQ_ARM(db, idx) \ 265 writel(DB_CP_REARM_FLAGS | RING_CMP(idx), (db)->doorbell) 266 267 #define BNXT_DB_NQ_ARM_P5(db, idx) \ 268 bnxt_writeq(bp, (db)->db_key64 | DBR_TYPE_NQ_ARM | RING_CMP(idx),\ 269 (db)->doorbell) 270 271 static void bnxt_db_nq(struct bnxt *bp, struct bnxt_db_info *db, u32 idx) 272 { 273 if (bp->flags & BNXT_FLAG_CHIP_P5) 274 BNXT_DB_NQ_P5(db, idx); 275 else 276 BNXT_DB_CQ(db, idx); 277 } 278 279 static void bnxt_db_nq_arm(struct bnxt *bp, struct bnxt_db_info *db, u32 idx) 280 { 281 if (bp->flags & BNXT_FLAG_CHIP_P5) 282 BNXT_DB_NQ_ARM_P5(db, idx); 283 else 284 BNXT_DB_CQ_ARM(db, idx); 285 } 286 287 static void bnxt_db_cq(struct bnxt *bp, struct bnxt_db_info *db, u32 idx) 288 { 289 if (bp->flags & BNXT_FLAG_CHIP_P5) 290 bnxt_writeq(bp, db->db_key64 | DBR_TYPE_CQ_ARMALL | 291 RING_CMP(idx), db->doorbell); 292 else 293 BNXT_DB_CQ(db, idx); 294 } 295 296 static void bnxt_queue_fw_reset_work(struct bnxt *bp, unsigned long delay) 297 { 298 if (!(test_bit(BNXT_STATE_IN_FW_RESET, &bp->state))) 299 return; 300 301 if (BNXT_PF(bp)) 302 queue_delayed_work(bnxt_pf_wq, &bp->fw_reset_task, delay); 303 else 304 schedule_delayed_work(&bp->fw_reset_task, delay); 305 } 306 307 static void __bnxt_queue_sp_work(struct bnxt *bp) 308 { 309 if (BNXT_PF(bp)) 310 queue_work(bnxt_pf_wq, &bp->sp_task); 311 else 312 schedule_work(&bp->sp_task); 313 } 314 315 static void bnxt_queue_sp_work(struct bnxt *bp, unsigned int event) 316 { 317 set_bit(event, &bp->sp_event); 318 __bnxt_queue_sp_work(bp); 319 } 320 321 static void bnxt_sched_reset_rxr(struct bnxt *bp, struct bnxt_rx_ring_info *rxr) 322 { 323 if (!rxr->bnapi->in_reset) { 324 rxr->bnapi->in_reset = true; 325 if (bp->flags & BNXT_FLAG_CHIP_P5) 326 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event); 327 else 328 set_bit(BNXT_RST_RING_SP_EVENT, &bp->sp_event); 329 __bnxt_queue_sp_work(bp); 330 } 331 rxr->rx_next_cons = 0xffff; 332 } 333 334 void bnxt_sched_reset_txr(struct bnxt *bp, struct bnxt_tx_ring_info *txr, 335 int idx) 336 { 337 struct bnxt_napi *bnapi = txr->bnapi; 338 339 if (bnapi->tx_fault) 340 return; 341 342 netdev_err(bp->dev, "Invalid Tx completion (ring:%d tx_pkts:%d cons:%u prod:%u i:%d)", 343 txr->txq_index, bnapi->tx_pkts, 344 txr->tx_cons, txr->tx_prod, idx); 345 WARN_ON_ONCE(1); 346 bnapi->tx_fault = 1; 347 bnxt_queue_sp_work(bp, BNXT_RESET_TASK_SP_EVENT); 348 } 349 350 const u16 bnxt_lhint_arr[] = { 351 TX_BD_FLAGS_LHINT_512_AND_SMALLER, 352 TX_BD_FLAGS_LHINT_512_TO_1023, 353 TX_BD_FLAGS_LHINT_1024_TO_2047, 354 TX_BD_FLAGS_LHINT_1024_TO_2047, 355 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 356 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 357 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 358 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 359 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 360 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 361 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 362 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 363 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 364 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 365 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 366 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 367 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 368 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 369 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 370 }; 371 372 static u16 bnxt_xmit_get_cfa_action(struct sk_buff *skb) 373 { 374 struct metadata_dst *md_dst = skb_metadata_dst(skb); 375 376 if (!md_dst || md_dst->type != METADATA_HW_PORT_MUX) 377 return 0; 378 379 return md_dst->u.port_info.port_id; 380 } 381 382 static void bnxt_txr_db_kick(struct bnxt *bp, struct bnxt_tx_ring_info *txr, 383 u16 prod) 384 { 385 bnxt_db_write(bp, &txr->tx_db, prod); 386 txr->kick_pending = 0; 387 } 388 389 static netdev_tx_t bnxt_start_xmit(struct sk_buff *skb, struct net_device *dev) 390 { 391 struct bnxt *bp = netdev_priv(dev); 392 struct tx_bd *txbd; 393 struct tx_bd_ext *txbd1; 394 struct netdev_queue *txq; 395 int i; 396 dma_addr_t mapping; 397 unsigned int length, pad = 0; 398 u32 len, free_size, vlan_tag_flags, cfa_action, flags; 399 u16 prod, last_frag; 400 struct pci_dev *pdev = bp->pdev; 401 struct bnxt_tx_ring_info *txr; 402 struct bnxt_sw_tx_bd *tx_buf; 403 __le32 lflags = 0; 404 405 i = skb_get_queue_mapping(skb); 406 if (unlikely(i >= bp->tx_nr_rings)) { 407 dev_kfree_skb_any(skb); 408 dev_core_stats_tx_dropped_inc(dev); 409 return NETDEV_TX_OK; 410 } 411 412 txq = netdev_get_tx_queue(dev, i); 413 txr = &bp->tx_ring[bp->tx_ring_map[i]]; 414 prod = txr->tx_prod; 415 416 free_size = bnxt_tx_avail(bp, txr); 417 if (unlikely(free_size < skb_shinfo(skb)->nr_frags + 2)) { 418 /* We must have raced with NAPI cleanup */ 419 if (net_ratelimit() && txr->kick_pending) 420 netif_warn(bp, tx_err, dev, 421 "bnxt: ring busy w/ flush pending!\n"); 422 if (!netif_txq_try_stop(txq, bnxt_tx_avail(bp, txr), 423 bp->tx_wake_thresh)) 424 return NETDEV_TX_BUSY; 425 } 426 427 if (unlikely(ipv6_hopopt_jumbo_remove(skb))) 428 goto tx_free; 429 430 length = skb->len; 431 len = skb_headlen(skb); 432 last_frag = skb_shinfo(skb)->nr_frags; 433 434 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)]; 435 436 txbd->tx_bd_opaque = prod; 437 438 tx_buf = &txr->tx_buf_ring[prod]; 439 tx_buf->skb = skb; 440 tx_buf->nr_frags = last_frag; 441 442 vlan_tag_flags = 0; 443 cfa_action = bnxt_xmit_get_cfa_action(skb); 444 if (skb_vlan_tag_present(skb)) { 445 vlan_tag_flags = TX_BD_CFA_META_KEY_VLAN | 446 skb_vlan_tag_get(skb); 447 /* Currently supports 8021Q, 8021AD vlan offloads 448 * QINQ1, QINQ2, QINQ3 vlan headers are deprecated 449 */ 450 if (skb->vlan_proto == htons(ETH_P_8021Q)) 451 vlan_tag_flags |= 1 << TX_BD_CFA_META_TPID_SHIFT; 452 } 453 454 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) { 455 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 456 457 if (ptp && ptp->tx_tstamp_en && !skb_is_gso(skb) && 458 atomic_dec_if_positive(&ptp->tx_avail) >= 0) { 459 if (!bnxt_ptp_parse(skb, &ptp->tx_seqid, 460 &ptp->tx_hdr_off)) { 461 if (vlan_tag_flags) 462 ptp->tx_hdr_off += VLAN_HLEN; 463 lflags |= cpu_to_le32(TX_BD_FLAGS_STAMP); 464 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 465 } else { 466 atomic_inc(&bp->ptp_cfg->tx_avail); 467 } 468 } 469 } 470 471 if (unlikely(skb->no_fcs)) 472 lflags |= cpu_to_le32(TX_BD_FLAGS_NO_CRC); 473 474 if (free_size == bp->tx_ring_size && length <= bp->tx_push_thresh && 475 !lflags) { 476 struct tx_push_buffer *tx_push_buf = txr->tx_push; 477 struct tx_push_bd *tx_push = &tx_push_buf->push_bd; 478 struct tx_bd_ext *tx_push1 = &tx_push->txbd2; 479 void __iomem *db = txr->tx_db.doorbell; 480 void *pdata = tx_push_buf->data; 481 u64 *end; 482 int j, push_len; 483 484 /* Set COAL_NOW to be ready quickly for the next push */ 485 tx_push->tx_bd_len_flags_type = 486 cpu_to_le32((length << TX_BD_LEN_SHIFT) | 487 TX_BD_TYPE_LONG_TX_BD | 488 TX_BD_FLAGS_LHINT_512_AND_SMALLER | 489 TX_BD_FLAGS_COAL_NOW | 490 TX_BD_FLAGS_PACKET_END | 491 (2 << TX_BD_FLAGS_BD_CNT_SHIFT)); 492 493 if (skb->ip_summed == CHECKSUM_PARTIAL) 494 tx_push1->tx_bd_hsize_lflags = 495 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM); 496 else 497 tx_push1->tx_bd_hsize_lflags = 0; 498 499 tx_push1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags); 500 tx_push1->tx_bd_cfa_action = 501 cpu_to_le32(cfa_action << TX_BD_CFA_ACTION_SHIFT); 502 503 end = pdata + length; 504 end = PTR_ALIGN(end, 8) - 1; 505 *end = 0; 506 507 skb_copy_from_linear_data(skb, pdata, len); 508 pdata += len; 509 for (j = 0; j < last_frag; j++) { 510 skb_frag_t *frag = &skb_shinfo(skb)->frags[j]; 511 void *fptr; 512 513 fptr = skb_frag_address_safe(frag); 514 if (!fptr) 515 goto normal_tx; 516 517 memcpy(pdata, fptr, skb_frag_size(frag)); 518 pdata += skb_frag_size(frag); 519 } 520 521 txbd->tx_bd_len_flags_type = tx_push->tx_bd_len_flags_type; 522 txbd->tx_bd_haddr = txr->data_mapping; 523 prod = NEXT_TX(prod); 524 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)]; 525 memcpy(txbd, tx_push1, sizeof(*txbd)); 526 prod = NEXT_TX(prod); 527 tx_push->doorbell = 528 cpu_to_le32(DB_KEY_TX_PUSH | DB_LONG_TX_PUSH | prod); 529 WRITE_ONCE(txr->tx_prod, prod); 530 531 tx_buf->is_push = 1; 532 netdev_tx_sent_queue(txq, skb->len); 533 wmb(); /* Sync is_push and byte queue before pushing data */ 534 535 push_len = (length + sizeof(*tx_push) + 7) / 8; 536 if (push_len > 16) { 537 __iowrite64_copy(db, tx_push_buf, 16); 538 __iowrite32_copy(db + 4, tx_push_buf + 1, 539 (push_len - 16) << 1); 540 } else { 541 __iowrite64_copy(db, tx_push_buf, push_len); 542 } 543 544 goto tx_done; 545 } 546 547 normal_tx: 548 if (length < BNXT_MIN_PKT_SIZE) { 549 pad = BNXT_MIN_PKT_SIZE - length; 550 if (skb_pad(skb, pad)) 551 /* SKB already freed. */ 552 goto tx_kick_pending; 553 length = BNXT_MIN_PKT_SIZE; 554 } 555 556 mapping = dma_map_single(&pdev->dev, skb->data, len, DMA_TO_DEVICE); 557 558 if (unlikely(dma_mapping_error(&pdev->dev, mapping))) 559 goto tx_free; 560 561 dma_unmap_addr_set(tx_buf, mapping, mapping); 562 flags = (len << TX_BD_LEN_SHIFT) | TX_BD_TYPE_LONG_TX_BD | 563 ((last_frag + 2) << TX_BD_FLAGS_BD_CNT_SHIFT); 564 565 txbd->tx_bd_haddr = cpu_to_le64(mapping); 566 567 prod = NEXT_TX(prod); 568 txbd1 = (struct tx_bd_ext *) 569 &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)]; 570 571 txbd1->tx_bd_hsize_lflags = lflags; 572 if (skb_is_gso(skb)) { 573 u32 hdr_len; 574 575 if (skb->encapsulation) 576 hdr_len = skb_inner_tcp_all_headers(skb); 577 else 578 hdr_len = skb_tcp_all_headers(skb); 579 580 txbd1->tx_bd_hsize_lflags |= cpu_to_le32(TX_BD_FLAGS_LSO | 581 TX_BD_FLAGS_T_IPID | 582 (hdr_len << (TX_BD_HSIZE_SHIFT - 1))); 583 length = skb_shinfo(skb)->gso_size; 584 txbd1->tx_bd_mss = cpu_to_le32(length); 585 length += hdr_len; 586 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 587 txbd1->tx_bd_hsize_lflags |= 588 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM); 589 txbd1->tx_bd_mss = 0; 590 } 591 592 length >>= 9; 593 if (unlikely(length >= ARRAY_SIZE(bnxt_lhint_arr))) { 594 dev_warn_ratelimited(&pdev->dev, "Dropped oversize %d bytes TX packet.\n", 595 skb->len); 596 i = 0; 597 goto tx_dma_error; 598 } 599 flags |= bnxt_lhint_arr[length]; 600 txbd->tx_bd_len_flags_type = cpu_to_le32(flags); 601 602 txbd1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags); 603 txbd1->tx_bd_cfa_action = 604 cpu_to_le32(cfa_action << TX_BD_CFA_ACTION_SHIFT); 605 for (i = 0; i < last_frag; i++) { 606 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 607 608 prod = NEXT_TX(prod); 609 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)]; 610 611 len = skb_frag_size(frag); 612 mapping = skb_frag_dma_map(&pdev->dev, frag, 0, len, 613 DMA_TO_DEVICE); 614 615 if (unlikely(dma_mapping_error(&pdev->dev, mapping))) 616 goto tx_dma_error; 617 618 tx_buf = &txr->tx_buf_ring[prod]; 619 dma_unmap_addr_set(tx_buf, mapping, mapping); 620 621 txbd->tx_bd_haddr = cpu_to_le64(mapping); 622 623 flags = len << TX_BD_LEN_SHIFT; 624 txbd->tx_bd_len_flags_type = cpu_to_le32(flags); 625 } 626 627 flags &= ~TX_BD_LEN; 628 txbd->tx_bd_len_flags_type = 629 cpu_to_le32(((len + pad) << TX_BD_LEN_SHIFT) | flags | 630 TX_BD_FLAGS_PACKET_END); 631 632 netdev_tx_sent_queue(txq, skb->len); 633 634 skb_tx_timestamp(skb); 635 636 /* Sync BD data before updating doorbell */ 637 wmb(); 638 639 prod = NEXT_TX(prod); 640 WRITE_ONCE(txr->tx_prod, prod); 641 642 if (!netdev_xmit_more() || netif_xmit_stopped(txq)) 643 bnxt_txr_db_kick(bp, txr, prod); 644 else 645 txr->kick_pending = 1; 646 647 tx_done: 648 649 if (unlikely(bnxt_tx_avail(bp, txr) <= MAX_SKB_FRAGS + 1)) { 650 if (netdev_xmit_more() && !tx_buf->is_push) 651 bnxt_txr_db_kick(bp, txr, prod); 652 653 netif_txq_try_stop(txq, bnxt_tx_avail(bp, txr), 654 bp->tx_wake_thresh); 655 } 656 return NETDEV_TX_OK; 657 658 tx_dma_error: 659 if (BNXT_TX_PTP_IS_SET(lflags)) 660 atomic_inc(&bp->ptp_cfg->tx_avail); 661 662 last_frag = i; 663 664 /* start back at beginning and unmap skb */ 665 prod = txr->tx_prod; 666 tx_buf = &txr->tx_buf_ring[prod]; 667 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping), 668 skb_headlen(skb), DMA_TO_DEVICE); 669 prod = NEXT_TX(prod); 670 671 /* unmap remaining mapped pages */ 672 for (i = 0; i < last_frag; i++) { 673 prod = NEXT_TX(prod); 674 tx_buf = &txr->tx_buf_ring[prod]; 675 dma_unmap_page(&pdev->dev, dma_unmap_addr(tx_buf, mapping), 676 skb_frag_size(&skb_shinfo(skb)->frags[i]), 677 DMA_TO_DEVICE); 678 } 679 680 tx_free: 681 dev_kfree_skb_any(skb); 682 tx_kick_pending: 683 if (txr->kick_pending) 684 bnxt_txr_db_kick(bp, txr, txr->tx_prod); 685 txr->tx_buf_ring[txr->tx_prod].skb = NULL; 686 dev_core_stats_tx_dropped_inc(dev); 687 return NETDEV_TX_OK; 688 } 689 690 static void bnxt_tx_int(struct bnxt *bp, struct bnxt_napi *bnapi, int nr_pkts) 691 { 692 struct bnxt_tx_ring_info *txr = bnapi->tx_ring; 693 struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, txr->txq_index); 694 u16 cons = txr->tx_cons; 695 struct pci_dev *pdev = bp->pdev; 696 int i; 697 unsigned int tx_bytes = 0; 698 699 for (i = 0; i < nr_pkts; i++) { 700 struct bnxt_sw_tx_bd *tx_buf; 701 struct sk_buff *skb; 702 int j, last; 703 704 tx_buf = &txr->tx_buf_ring[cons]; 705 cons = NEXT_TX(cons); 706 skb = tx_buf->skb; 707 tx_buf->skb = NULL; 708 709 if (unlikely(!skb)) { 710 bnxt_sched_reset_txr(bp, txr, i); 711 return; 712 } 713 714 tx_bytes += skb->len; 715 716 if (tx_buf->is_push) { 717 tx_buf->is_push = 0; 718 goto next_tx_int; 719 } 720 721 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping), 722 skb_headlen(skb), DMA_TO_DEVICE); 723 last = tx_buf->nr_frags; 724 725 for (j = 0; j < last; j++) { 726 cons = NEXT_TX(cons); 727 tx_buf = &txr->tx_buf_ring[cons]; 728 dma_unmap_page( 729 &pdev->dev, 730 dma_unmap_addr(tx_buf, mapping), 731 skb_frag_size(&skb_shinfo(skb)->frags[j]), 732 DMA_TO_DEVICE); 733 } 734 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) { 735 if (bp->flags & BNXT_FLAG_CHIP_P5) { 736 /* PTP worker takes ownership of the skb */ 737 if (!bnxt_get_tx_ts_p5(bp, skb)) 738 skb = NULL; 739 else 740 atomic_inc(&bp->ptp_cfg->tx_avail); 741 } 742 } 743 744 next_tx_int: 745 cons = NEXT_TX(cons); 746 747 dev_consume_skb_any(skb); 748 } 749 750 WRITE_ONCE(txr->tx_cons, cons); 751 752 __netif_txq_completed_wake(txq, nr_pkts, tx_bytes, 753 bnxt_tx_avail(bp, txr), bp->tx_wake_thresh, 754 READ_ONCE(txr->dev_state) == BNXT_DEV_STATE_CLOSING); 755 } 756 757 static struct page *__bnxt_alloc_rx_page(struct bnxt *bp, dma_addr_t *mapping, 758 struct bnxt_rx_ring_info *rxr, 759 gfp_t gfp) 760 { 761 struct device *dev = &bp->pdev->dev; 762 struct page *page; 763 764 page = page_pool_dev_alloc_pages(rxr->page_pool); 765 if (!page) 766 return NULL; 767 768 *mapping = dma_map_page_attrs(dev, page, 0, PAGE_SIZE, bp->rx_dir, 769 DMA_ATTR_WEAK_ORDERING); 770 if (dma_mapping_error(dev, *mapping)) { 771 page_pool_recycle_direct(rxr->page_pool, page); 772 return NULL; 773 } 774 return page; 775 } 776 777 static inline u8 *__bnxt_alloc_rx_frag(struct bnxt *bp, dma_addr_t *mapping, 778 gfp_t gfp) 779 { 780 u8 *data; 781 struct pci_dev *pdev = bp->pdev; 782 783 if (gfp == GFP_ATOMIC) 784 data = napi_alloc_frag(bp->rx_buf_size); 785 else 786 data = netdev_alloc_frag(bp->rx_buf_size); 787 if (!data) 788 return NULL; 789 790 *mapping = dma_map_single_attrs(&pdev->dev, data + bp->rx_dma_offset, 791 bp->rx_buf_use_size, bp->rx_dir, 792 DMA_ATTR_WEAK_ORDERING); 793 794 if (dma_mapping_error(&pdev->dev, *mapping)) { 795 skb_free_frag(data); 796 data = NULL; 797 } 798 return data; 799 } 800 801 int bnxt_alloc_rx_data(struct bnxt *bp, struct bnxt_rx_ring_info *rxr, 802 u16 prod, gfp_t gfp) 803 { 804 struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)]; 805 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[prod]; 806 dma_addr_t mapping; 807 808 if (BNXT_RX_PAGE_MODE(bp)) { 809 struct page *page = 810 __bnxt_alloc_rx_page(bp, &mapping, rxr, gfp); 811 812 if (!page) 813 return -ENOMEM; 814 815 mapping += bp->rx_dma_offset; 816 rx_buf->data = page; 817 rx_buf->data_ptr = page_address(page) + bp->rx_offset; 818 } else { 819 u8 *data = __bnxt_alloc_rx_frag(bp, &mapping, gfp); 820 821 if (!data) 822 return -ENOMEM; 823 824 rx_buf->data = data; 825 rx_buf->data_ptr = data + bp->rx_offset; 826 } 827 rx_buf->mapping = mapping; 828 829 rxbd->rx_bd_haddr = cpu_to_le64(mapping); 830 return 0; 831 } 832 833 void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons, void *data) 834 { 835 u16 prod = rxr->rx_prod; 836 struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf; 837 struct rx_bd *cons_bd, *prod_bd; 838 839 prod_rx_buf = &rxr->rx_buf_ring[prod]; 840 cons_rx_buf = &rxr->rx_buf_ring[cons]; 841 842 prod_rx_buf->data = data; 843 prod_rx_buf->data_ptr = cons_rx_buf->data_ptr; 844 845 prod_rx_buf->mapping = cons_rx_buf->mapping; 846 847 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)]; 848 cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)]; 849 850 prod_bd->rx_bd_haddr = cons_bd->rx_bd_haddr; 851 } 852 853 static inline u16 bnxt_find_next_agg_idx(struct bnxt_rx_ring_info *rxr, u16 idx) 854 { 855 u16 next, max = rxr->rx_agg_bmap_size; 856 857 next = find_next_zero_bit(rxr->rx_agg_bmap, max, idx); 858 if (next >= max) 859 next = find_first_zero_bit(rxr->rx_agg_bmap, max); 860 return next; 861 } 862 863 static inline int bnxt_alloc_rx_page(struct bnxt *bp, 864 struct bnxt_rx_ring_info *rxr, 865 u16 prod, gfp_t gfp) 866 { 867 struct rx_bd *rxbd = 868 &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)]; 869 struct bnxt_sw_rx_agg_bd *rx_agg_buf; 870 struct pci_dev *pdev = bp->pdev; 871 struct page *page; 872 dma_addr_t mapping; 873 u16 sw_prod = rxr->rx_sw_agg_prod; 874 unsigned int offset = 0; 875 876 if (BNXT_RX_PAGE_MODE(bp)) { 877 page = __bnxt_alloc_rx_page(bp, &mapping, rxr, gfp); 878 879 if (!page) 880 return -ENOMEM; 881 882 } else { 883 if (PAGE_SIZE > BNXT_RX_PAGE_SIZE) { 884 page = rxr->rx_page; 885 if (!page) { 886 page = alloc_page(gfp); 887 if (!page) 888 return -ENOMEM; 889 rxr->rx_page = page; 890 rxr->rx_page_offset = 0; 891 } 892 offset = rxr->rx_page_offset; 893 rxr->rx_page_offset += BNXT_RX_PAGE_SIZE; 894 if (rxr->rx_page_offset == PAGE_SIZE) 895 rxr->rx_page = NULL; 896 else 897 get_page(page); 898 } else { 899 page = alloc_page(gfp); 900 if (!page) 901 return -ENOMEM; 902 } 903 904 mapping = dma_map_page_attrs(&pdev->dev, page, offset, 905 BNXT_RX_PAGE_SIZE, DMA_FROM_DEVICE, 906 DMA_ATTR_WEAK_ORDERING); 907 if (dma_mapping_error(&pdev->dev, mapping)) { 908 __free_page(page); 909 return -EIO; 910 } 911 } 912 913 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap))) 914 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod); 915 916 __set_bit(sw_prod, rxr->rx_agg_bmap); 917 rx_agg_buf = &rxr->rx_agg_ring[sw_prod]; 918 rxr->rx_sw_agg_prod = NEXT_RX_AGG(sw_prod); 919 920 rx_agg_buf->page = page; 921 rx_agg_buf->offset = offset; 922 rx_agg_buf->mapping = mapping; 923 rxbd->rx_bd_haddr = cpu_to_le64(mapping); 924 rxbd->rx_bd_opaque = sw_prod; 925 return 0; 926 } 927 928 static struct rx_agg_cmp *bnxt_get_agg(struct bnxt *bp, 929 struct bnxt_cp_ring_info *cpr, 930 u16 cp_cons, u16 curr) 931 { 932 struct rx_agg_cmp *agg; 933 934 cp_cons = RING_CMP(ADV_RAW_CMP(cp_cons, curr)); 935 agg = (struct rx_agg_cmp *) 936 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 937 return agg; 938 } 939 940 static struct rx_agg_cmp *bnxt_get_tpa_agg_p5(struct bnxt *bp, 941 struct bnxt_rx_ring_info *rxr, 942 u16 agg_id, u16 curr) 943 { 944 struct bnxt_tpa_info *tpa_info = &rxr->rx_tpa[agg_id]; 945 946 return &tpa_info->agg_arr[curr]; 947 } 948 949 static void bnxt_reuse_rx_agg_bufs(struct bnxt_cp_ring_info *cpr, u16 idx, 950 u16 start, u32 agg_bufs, bool tpa) 951 { 952 struct bnxt_napi *bnapi = cpr->bnapi; 953 struct bnxt *bp = bnapi->bp; 954 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 955 u16 prod = rxr->rx_agg_prod; 956 u16 sw_prod = rxr->rx_sw_agg_prod; 957 bool p5_tpa = false; 958 u32 i; 959 960 if ((bp->flags & BNXT_FLAG_CHIP_P5) && tpa) 961 p5_tpa = true; 962 963 for (i = 0; i < agg_bufs; i++) { 964 u16 cons; 965 struct rx_agg_cmp *agg; 966 struct bnxt_sw_rx_agg_bd *cons_rx_buf, *prod_rx_buf; 967 struct rx_bd *prod_bd; 968 struct page *page; 969 970 if (p5_tpa) 971 agg = bnxt_get_tpa_agg_p5(bp, rxr, idx, start + i); 972 else 973 agg = bnxt_get_agg(bp, cpr, idx, start + i); 974 cons = agg->rx_agg_cmp_opaque; 975 __clear_bit(cons, rxr->rx_agg_bmap); 976 977 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap))) 978 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod); 979 980 __set_bit(sw_prod, rxr->rx_agg_bmap); 981 prod_rx_buf = &rxr->rx_agg_ring[sw_prod]; 982 cons_rx_buf = &rxr->rx_agg_ring[cons]; 983 984 /* It is possible for sw_prod to be equal to cons, so 985 * set cons_rx_buf->page to NULL first. 986 */ 987 page = cons_rx_buf->page; 988 cons_rx_buf->page = NULL; 989 prod_rx_buf->page = page; 990 prod_rx_buf->offset = cons_rx_buf->offset; 991 992 prod_rx_buf->mapping = cons_rx_buf->mapping; 993 994 prod_bd = &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)]; 995 996 prod_bd->rx_bd_haddr = cpu_to_le64(cons_rx_buf->mapping); 997 prod_bd->rx_bd_opaque = sw_prod; 998 999 prod = NEXT_RX_AGG(prod); 1000 sw_prod = NEXT_RX_AGG(sw_prod); 1001 } 1002 rxr->rx_agg_prod = prod; 1003 rxr->rx_sw_agg_prod = sw_prod; 1004 } 1005 1006 static struct sk_buff *bnxt_rx_multi_page_skb(struct bnxt *bp, 1007 struct bnxt_rx_ring_info *rxr, 1008 u16 cons, void *data, u8 *data_ptr, 1009 dma_addr_t dma_addr, 1010 unsigned int offset_and_len) 1011 { 1012 unsigned int len = offset_and_len & 0xffff; 1013 struct page *page = data; 1014 u16 prod = rxr->rx_prod; 1015 struct sk_buff *skb; 1016 int err; 1017 1018 err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC); 1019 if (unlikely(err)) { 1020 bnxt_reuse_rx_data(rxr, cons, data); 1021 return NULL; 1022 } 1023 dma_addr -= bp->rx_dma_offset; 1024 dma_unmap_page_attrs(&bp->pdev->dev, dma_addr, PAGE_SIZE, bp->rx_dir, 1025 DMA_ATTR_WEAK_ORDERING); 1026 skb = build_skb(page_address(page), PAGE_SIZE); 1027 if (!skb) { 1028 page_pool_recycle_direct(rxr->page_pool, page); 1029 return NULL; 1030 } 1031 skb_mark_for_recycle(skb); 1032 skb_reserve(skb, bp->rx_dma_offset); 1033 __skb_put(skb, len); 1034 1035 return skb; 1036 } 1037 1038 static struct sk_buff *bnxt_rx_page_skb(struct bnxt *bp, 1039 struct bnxt_rx_ring_info *rxr, 1040 u16 cons, void *data, u8 *data_ptr, 1041 dma_addr_t dma_addr, 1042 unsigned int offset_and_len) 1043 { 1044 unsigned int payload = offset_and_len >> 16; 1045 unsigned int len = offset_and_len & 0xffff; 1046 skb_frag_t *frag; 1047 struct page *page = data; 1048 u16 prod = rxr->rx_prod; 1049 struct sk_buff *skb; 1050 int off, err; 1051 1052 err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC); 1053 if (unlikely(err)) { 1054 bnxt_reuse_rx_data(rxr, cons, data); 1055 return NULL; 1056 } 1057 dma_addr -= bp->rx_dma_offset; 1058 dma_unmap_page_attrs(&bp->pdev->dev, dma_addr, PAGE_SIZE, bp->rx_dir, 1059 DMA_ATTR_WEAK_ORDERING); 1060 1061 if (unlikely(!payload)) 1062 payload = eth_get_headlen(bp->dev, data_ptr, len); 1063 1064 skb = napi_alloc_skb(&rxr->bnapi->napi, payload); 1065 if (!skb) { 1066 page_pool_recycle_direct(rxr->page_pool, page); 1067 return NULL; 1068 } 1069 1070 skb_mark_for_recycle(skb); 1071 off = (void *)data_ptr - page_address(page); 1072 skb_add_rx_frag(skb, 0, page, off, len, PAGE_SIZE); 1073 memcpy(skb->data - NET_IP_ALIGN, data_ptr - NET_IP_ALIGN, 1074 payload + NET_IP_ALIGN); 1075 1076 frag = &skb_shinfo(skb)->frags[0]; 1077 skb_frag_size_sub(frag, payload); 1078 skb_frag_off_add(frag, payload); 1079 skb->data_len -= payload; 1080 skb->tail += payload; 1081 1082 return skb; 1083 } 1084 1085 static struct sk_buff *bnxt_rx_skb(struct bnxt *bp, 1086 struct bnxt_rx_ring_info *rxr, u16 cons, 1087 void *data, u8 *data_ptr, 1088 dma_addr_t dma_addr, 1089 unsigned int offset_and_len) 1090 { 1091 u16 prod = rxr->rx_prod; 1092 struct sk_buff *skb; 1093 int err; 1094 1095 err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC); 1096 if (unlikely(err)) { 1097 bnxt_reuse_rx_data(rxr, cons, data); 1098 return NULL; 1099 } 1100 1101 skb = build_skb(data, bp->rx_buf_size); 1102 dma_unmap_single_attrs(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size, 1103 bp->rx_dir, DMA_ATTR_WEAK_ORDERING); 1104 if (!skb) { 1105 skb_free_frag(data); 1106 return NULL; 1107 } 1108 1109 skb_reserve(skb, bp->rx_offset); 1110 skb_put(skb, offset_and_len & 0xffff); 1111 return skb; 1112 } 1113 1114 static u32 __bnxt_rx_agg_pages(struct bnxt *bp, 1115 struct bnxt_cp_ring_info *cpr, 1116 struct skb_shared_info *shinfo, 1117 u16 idx, u32 agg_bufs, bool tpa, 1118 struct xdp_buff *xdp) 1119 { 1120 struct bnxt_napi *bnapi = cpr->bnapi; 1121 struct pci_dev *pdev = bp->pdev; 1122 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 1123 u16 prod = rxr->rx_agg_prod; 1124 u32 i, total_frag_len = 0; 1125 bool p5_tpa = false; 1126 1127 if ((bp->flags & BNXT_FLAG_CHIP_P5) && tpa) 1128 p5_tpa = true; 1129 1130 for (i = 0; i < agg_bufs; i++) { 1131 skb_frag_t *frag = &shinfo->frags[i]; 1132 u16 cons, frag_len; 1133 struct rx_agg_cmp *agg; 1134 struct bnxt_sw_rx_agg_bd *cons_rx_buf; 1135 struct page *page; 1136 dma_addr_t mapping; 1137 1138 if (p5_tpa) 1139 agg = bnxt_get_tpa_agg_p5(bp, rxr, idx, i); 1140 else 1141 agg = bnxt_get_agg(bp, cpr, idx, i); 1142 cons = agg->rx_agg_cmp_opaque; 1143 frag_len = (le32_to_cpu(agg->rx_agg_cmp_len_flags_type) & 1144 RX_AGG_CMP_LEN) >> RX_AGG_CMP_LEN_SHIFT; 1145 1146 cons_rx_buf = &rxr->rx_agg_ring[cons]; 1147 skb_frag_fill_page_desc(frag, cons_rx_buf->page, 1148 cons_rx_buf->offset, frag_len); 1149 shinfo->nr_frags = i + 1; 1150 __clear_bit(cons, rxr->rx_agg_bmap); 1151 1152 /* It is possible for bnxt_alloc_rx_page() to allocate 1153 * a sw_prod index that equals the cons index, so we 1154 * need to clear the cons entry now. 1155 */ 1156 mapping = cons_rx_buf->mapping; 1157 page = cons_rx_buf->page; 1158 cons_rx_buf->page = NULL; 1159 1160 if (xdp && page_is_pfmemalloc(page)) 1161 xdp_buff_set_frag_pfmemalloc(xdp); 1162 1163 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_ATOMIC) != 0) { 1164 --shinfo->nr_frags; 1165 cons_rx_buf->page = page; 1166 1167 /* Update prod since possibly some pages have been 1168 * allocated already. 1169 */ 1170 rxr->rx_agg_prod = prod; 1171 bnxt_reuse_rx_agg_bufs(cpr, idx, i, agg_bufs - i, tpa); 1172 return 0; 1173 } 1174 1175 dma_unmap_page_attrs(&pdev->dev, mapping, BNXT_RX_PAGE_SIZE, 1176 bp->rx_dir, 1177 DMA_ATTR_WEAK_ORDERING); 1178 1179 total_frag_len += frag_len; 1180 prod = NEXT_RX_AGG(prod); 1181 } 1182 rxr->rx_agg_prod = prod; 1183 return total_frag_len; 1184 } 1185 1186 static struct sk_buff *bnxt_rx_agg_pages_skb(struct bnxt *bp, 1187 struct bnxt_cp_ring_info *cpr, 1188 struct sk_buff *skb, u16 idx, 1189 u32 agg_bufs, bool tpa) 1190 { 1191 struct skb_shared_info *shinfo = skb_shinfo(skb); 1192 u32 total_frag_len = 0; 1193 1194 total_frag_len = __bnxt_rx_agg_pages(bp, cpr, shinfo, idx, 1195 agg_bufs, tpa, NULL); 1196 if (!total_frag_len) { 1197 dev_kfree_skb(skb); 1198 return NULL; 1199 } 1200 1201 skb->data_len += total_frag_len; 1202 skb->len += total_frag_len; 1203 skb->truesize += PAGE_SIZE * agg_bufs; 1204 return skb; 1205 } 1206 1207 static u32 bnxt_rx_agg_pages_xdp(struct bnxt *bp, 1208 struct bnxt_cp_ring_info *cpr, 1209 struct xdp_buff *xdp, u16 idx, 1210 u32 agg_bufs, bool tpa) 1211 { 1212 struct skb_shared_info *shinfo = xdp_get_shared_info_from_buff(xdp); 1213 u32 total_frag_len = 0; 1214 1215 if (!xdp_buff_has_frags(xdp)) 1216 shinfo->nr_frags = 0; 1217 1218 total_frag_len = __bnxt_rx_agg_pages(bp, cpr, shinfo, 1219 idx, agg_bufs, tpa, xdp); 1220 if (total_frag_len) { 1221 xdp_buff_set_frags_flag(xdp); 1222 shinfo->nr_frags = agg_bufs; 1223 shinfo->xdp_frags_size = total_frag_len; 1224 } 1225 return total_frag_len; 1226 } 1227 1228 static int bnxt_agg_bufs_valid(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, 1229 u8 agg_bufs, u32 *raw_cons) 1230 { 1231 u16 last; 1232 struct rx_agg_cmp *agg; 1233 1234 *raw_cons = ADV_RAW_CMP(*raw_cons, agg_bufs); 1235 last = RING_CMP(*raw_cons); 1236 agg = (struct rx_agg_cmp *) 1237 &cpr->cp_desc_ring[CP_RING(last)][CP_IDX(last)]; 1238 return RX_AGG_CMP_VALID(agg, *raw_cons); 1239 } 1240 1241 static inline struct sk_buff *bnxt_copy_skb(struct bnxt_napi *bnapi, u8 *data, 1242 unsigned int len, 1243 dma_addr_t mapping) 1244 { 1245 struct bnxt *bp = bnapi->bp; 1246 struct pci_dev *pdev = bp->pdev; 1247 struct sk_buff *skb; 1248 1249 skb = napi_alloc_skb(&bnapi->napi, len); 1250 if (!skb) 1251 return NULL; 1252 1253 dma_sync_single_for_cpu(&pdev->dev, mapping, bp->rx_copy_thresh, 1254 bp->rx_dir); 1255 1256 memcpy(skb->data - NET_IP_ALIGN, data - NET_IP_ALIGN, 1257 len + NET_IP_ALIGN); 1258 1259 dma_sync_single_for_device(&pdev->dev, mapping, bp->rx_copy_thresh, 1260 bp->rx_dir); 1261 1262 skb_put(skb, len); 1263 return skb; 1264 } 1265 1266 static int bnxt_discard_rx(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, 1267 u32 *raw_cons, void *cmp) 1268 { 1269 struct rx_cmp *rxcmp = cmp; 1270 u32 tmp_raw_cons = *raw_cons; 1271 u8 cmp_type, agg_bufs = 0; 1272 1273 cmp_type = RX_CMP_TYPE(rxcmp); 1274 1275 if (cmp_type == CMP_TYPE_RX_L2_CMP) { 1276 agg_bufs = (le32_to_cpu(rxcmp->rx_cmp_misc_v1) & 1277 RX_CMP_AGG_BUFS) >> 1278 RX_CMP_AGG_BUFS_SHIFT; 1279 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) { 1280 struct rx_tpa_end_cmp *tpa_end = cmp; 1281 1282 if (bp->flags & BNXT_FLAG_CHIP_P5) 1283 return 0; 1284 1285 agg_bufs = TPA_END_AGG_BUFS(tpa_end); 1286 } 1287 1288 if (agg_bufs) { 1289 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons)) 1290 return -EBUSY; 1291 } 1292 *raw_cons = tmp_raw_cons; 1293 return 0; 1294 } 1295 1296 static u16 bnxt_alloc_agg_idx(struct bnxt_rx_ring_info *rxr, u16 agg_id) 1297 { 1298 struct bnxt_tpa_idx_map *map = rxr->rx_tpa_idx_map; 1299 u16 idx = agg_id & MAX_TPA_P5_MASK; 1300 1301 if (test_bit(idx, map->agg_idx_bmap)) 1302 idx = find_first_zero_bit(map->agg_idx_bmap, 1303 BNXT_AGG_IDX_BMAP_SIZE); 1304 __set_bit(idx, map->agg_idx_bmap); 1305 map->agg_id_tbl[agg_id] = idx; 1306 return idx; 1307 } 1308 1309 static void bnxt_free_agg_idx(struct bnxt_rx_ring_info *rxr, u16 idx) 1310 { 1311 struct bnxt_tpa_idx_map *map = rxr->rx_tpa_idx_map; 1312 1313 __clear_bit(idx, map->agg_idx_bmap); 1314 } 1315 1316 static u16 bnxt_lookup_agg_idx(struct bnxt_rx_ring_info *rxr, u16 agg_id) 1317 { 1318 struct bnxt_tpa_idx_map *map = rxr->rx_tpa_idx_map; 1319 1320 return map->agg_id_tbl[agg_id]; 1321 } 1322 1323 static void bnxt_tpa_start(struct bnxt *bp, struct bnxt_rx_ring_info *rxr, 1324 struct rx_tpa_start_cmp *tpa_start, 1325 struct rx_tpa_start_cmp_ext *tpa_start1) 1326 { 1327 struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf; 1328 struct bnxt_tpa_info *tpa_info; 1329 u16 cons, prod, agg_id; 1330 struct rx_bd *prod_bd; 1331 dma_addr_t mapping; 1332 1333 if (bp->flags & BNXT_FLAG_CHIP_P5) { 1334 agg_id = TPA_START_AGG_ID_P5(tpa_start); 1335 agg_id = bnxt_alloc_agg_idx(rxr, agg_id); 1336 } else { 1337 agg_id = TPA_START_AGG_ID(tpa_start); 1338 } 1339 cons = tpa_start->rx_tpa_start_cmp_opaque; 1340 prod = rxr->rx_prod; 1341 cons_rx_buf = &rxr->rx_buf_ring[cons]; 1342 prod_rx_buf = &rxr->rx_buf_ring[prod]; 1343 tpa_info = &rxr->rx_tpa[agg_id]; 1344 1345 if (unlikely(cons != rxr->rx_next_cons || 1346 TPA_START_ERROR(tpa_start))) { 1347 netdev_warn(bp->dev, "TPA cons %x, expected cons %x, error code %x\n", 1348 cons, rxr->rx_next_cons, 1349 TPA_START_ERROR_CODE(tpa_start1)); 1350 bnxt_sched_reset_rxr(bp, rxr); 1351 return; 1352 } 1353 /* Store cfa_code in tpa_info to use in tpa_end 1354 * completion processing. 1355 */ 1356 tpa_info->cfa_code = TPA_START_CFA_CODE(tpa_start1); 1357 prod_rx_buf->data = tpa_info->data; 1358 prod_rx_buf->data_ptr = tpa_info->data_ptr; 1359 1360 mapping = tpa_info->mapping; 1361 prod_rx_buf->mapping = mapping; 1362 1363 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)]; 1364 1365 prod_bd->rx_bd_haddr = cpu_to_le64(mapping); 1366 1367 tpa_info->data = cons_rx_buf->data; 1368 tpa_info->data_ptr = cons_rx_buf->data_ptr; 1369 cons_rx_buf->data = NULL; 1370 tpa_info->mapping = cons_rx_buf->mapping; 1371 1372 tpa_info->len = 1373 le32_to_cpu(tpa_start->rx_tpa_start_cmp_len_flags_type) >> 1374 RX_TPA_START_CMP_LEN_SHIFT; 1375 if (likely(TPA_START_HASH_VALID(tpa_start))) { 1376 u32 hash_type = TPA_START_HASH_TYPE(tpa_start); 1377 1378 tpa_info->hash_type = PKT_HASH_TYPE_L4; 1379 tpa_info->gso_type = SKB_GSO_TCPV4; 1380 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */ 1381 if (hash_type == 3 || TPA_START_IS_IPV6(tpa_start1)) 1382 tpa_info->gso_type = SKB_GSO_TCPV6; 1383 tpa_info->rss_hash = 1384 le32_to_cpu(tpa_start->rx_tpa_start_cmp_rss_hash); 1385 } else { 1386 tpa_info->hash_type = PKT_HASH_TYPE_NONE; 1387 tpa_info->gso_type = 0; 1388 netif_warn(bp, rx_err, bp->dev, "TPA packet without valid hash\n"); 1389 } 1390 tpa_info->flags2 = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_flags2); 1391 tpa_info->metadata = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_metadata); 1392 tpa_info->hdr_info = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_hdr_info); 1393 tpa_info->agg_count = 0; 1394 1395 rxr->rx_prod = NEXT_RX(prod); 1396 cons = NEXT_RX(cons); 1397 rxr->rx_next_cons = NEXT_RX(cons); 1398 cons_rx_buf = &rxr->rx_buf_ring[cons]; 1399 1400 bnxt_reuse_rx_data(rxr, cons, cons_rx_buf->data); 1401 rxr->rx_prod = NEXT_RX(rxr->rx_prod); 1402 cons_rx_buf->data = NULL; 1403 } 1404 1405 static void bnxt_abort_tpa(struct bnxt_cp_ring_info *cpr, u16 idx, u32 agg_bufs) 1406 { 1407 if (agg_bufs) 1408 bnxt_reuse_rx_agg_bufs(cpr, idx, 0, agg_bufs, true); 1409 } 1410 1411 #ifdef CONFIG_INET 1412 static void bnxt_gro_tunnel(struct sk_buff *skb, __be16 ip_proto) 1413 { 1414 struct udphdr *uh = NULL; 1415 1416 if (ip_proto == htons(ETH_P_IP)) { 1417 struct iphdr *iph = (struct iphdr *)skb->data; 1418 1419 if (iph->protocol == IPPROTO_UDP) 1420 uh = (struct udphdr *)(iph + 1); 1421 } else { 1422 struct ipv6hdr *iph = (struct ipv6hdr *)skb->data; 1423 1424 if (iph->nexthdr == IPPROTO_UDP) 1425 uh = (struct udphdr *)(iph + 1); 1426 } 1427 if (uh) { 1428 if (uh->check) 1429 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL_CSUM; 1430 else 1431 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL; 1432 } 1433 } 1434 #endif 1435 1436 static struct sk_buff *bnxt_gro_func_5731x(struct bnxt_tpa_info *tpa_info, 1437 int payload_off, int tcp_ts, 1438 struct sk_buff *skb) 1439 { 1440 #ifdef CONFIG_INET 1441 struct tcphdr *th; 1442 int len, nw_off; 1443 u16 outer_ip_off, inner_ip_off, inner_mac_off; 1444 u32 hdr_info = tpa_info->hdr_info; 1445 bool loopback = false; 1446 1447 inner_ip_off = BNXT_TPA_INNER_L3_OFF(hdr_info); 1448 inner_mac_off = BNXT_TPA_INNER_L2_OFF(hdr_info); 1449 outer_ip_off = BNXT_TPA_OUTER_L3_OFF(hdr_info); 1450 1451 /* If the packet is an internal loopback packet, the offsets will 1452 * have an extra 4 bytes. 1453 */ 1454 if (inner_mac_off == 4) { 1455 loopback = true; 1456 } else if (inner_mac_off > 4) { 1457 __be16 proto = *((__be16 *)(skb->data + inner_ip_off - 1458 ETH_HLEN - 2)); 1459 1460 /* We only support inner iPv4/ipv6. If we don't see the 1461 * correct protocol ID, it must be a loopback packet where 1462 * the offsets are off by 4. 1463 */ 1464 if (proto != htons(ETH_P_IP) && proto != htons(ETH_P_IPV6)) 1465 loopback = true; 1466 } 1467 if (loopback) { 1468 /* internal loopback packet, subtract all offsets by 4 */ 1469 inner_ip_off -= 4; 1470 inner_mac_off -= 4; 1471 outer_ip_off -= 4; 1472 } 1473 1474 nw_off = inner_ip_off - ETH_HLEN; 1475 skb_set_network_header(skb, nw_off); 1476 if (tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_IP_TYPE) { 1477 struct ipv6hdr *iph = ipv6_hdr(skb); 1478 1479 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr)); 1480 len = skb->len - skb_transport_offset(skb); 1481 th = tcp_hdr(skb); 1482 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0); 1483 } else { 1484 struct iphdr *iph = ip_hdr(skb); 1485 1486 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr)); 1487 len = skb->len - skb_transport_offset(skb); 1488 th = tcp_hdr(skb); 1489 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0); 1490 } 1491 1492 if (inner_mac_off) { /* tunnel */ 1493 __be16 proto = *((__be16 *)(skb->data + outer_ip_off - 1494 ETH_HLEN - 2)); 1495 1496 bnxt_gro_tunnel(skb, proto); 1497 } 1498 #endif 1499 return skb; 1500 } 1501 1502 static struct sk_buff *bnxt_gro_func_5750x(struct bnxt_tpa_info *tpa_info, 1503 int payload_off, int tcp_ts, 1504 struct sk_buff *skb) 1505 { 1506 #ifdef CONFIG_INET 1507 u16 outer_ip_off, inner_ip_off, inner_mac_off; 1508 u32 hdr_info = tpa_info->hdr_info; 1509 int iphdr_len, nw_off; 1510 1511 inner_ip_off = BNXT_TPA_INNER_L3_OFF(hdr_info); 1512 inner_mac_off = BNXT_TPA_INNER_L2_OFF(hdr_info); 1513 outer_ip_off = BNXT_TPA_OUTER_L3_OFF(hdr_info); 1514 1515 nw_off = inner_ip_off - ETH_HLEN; 1516 skb_set_network_header(skb, nw_off); 1517 iphdr_len = (tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_IP_TYPE) ? 1518 sizeof(struct ipv6hdr) : sizeof(struct iphdr); 1519 skb_set_transport_header(skb, nw_off + iphdr_len); 1520 1521 if (inner_mac_off) { /* tunnel */ 1522 __be16 proto = *((__be16 *)(skb->data + outer_ip_off - 1523 ETH_HLEN - 2)); 1524 1525 bnxt_gro_tunnel(skb, proto); 1526 } 1527 #endif 1528 return skb; 1529 } 1530 1531 #define BNXT_IPV4_HDR_SIZE (sizeof(struct iphdr) + sizeof(struct tcphdr)) 1532 #define BNXT_IPV6_HDR_SIZE (sizeof(struct ipv6hdr) + sizeof(struct tcphdr)) 1533 1534 static struct sk_buff *bnxt_gro_func_5730x(struct bnxt_tpa_info *tpa_info, 1535 int payload_off, int tcp_ts, 1536 struct sk_buff *skb) 1537 { 1538 #ifdef CONFIG_INET 1539 struct tcphdr *th; 1540 int len, nw_off, tcp_opt_len = 0; 1541 1542 if (tcp_ts) 1543 tcp_opt_len = 12; 1544 1545 if (tpa_info->gso_type == SKB_GSO_TCPV4) { 1546 struct iphdr *iph; 1547 1548 nw_off = payload_off - BNXT_IPV4_HDR_SIZE - tcp_opt_len - 1549 ETH_HLEN; 1550 skb_set_network_header(skb, nw_off); 1551 iph = ip_hdr(skb); 1552 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr)); 1553 len = skb->len - skb_transport_offset(skb); 1554 th = tcp_hdr(skb); 1555 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0); 1556 } else if (tpa_info->gso_type == SKB_GSO_TCPV6) { 1557 struct ipv6hdr *iph; 1558 1559 nw_off = payload_off - BNXT_IPV6_HDR_SIZE - tcp_opt_len - 1560 ETH_HLEN; 1561 skb_set_network_header(skb, nw_off); 1562 iph = ipv6_hdr(skb); 1563 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr)); 1564 len = skb->len - skb_transport_offset(skb); 1565 th = tcp_hdr(skb); 1566 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0); 1567 } else { 1568 dev_kfree_skb_any(skb); 1569 return NULL; 1570 } 1571 1572 if (nw_off) /* tunnel */ 1573 bnxt_gro_tunnel(skb, skb->protocol); 1574 #endif 1575 return skb; 1576 } 1577 1578 static inline struct sk_buff *bnxt_gro_skb(struct bnxt *bp, 1579 struct bnxt_tpa_info *tpa_info, 1580 struct rx_tpa_end_cmp *tpa_end, 1581 struct rx_tpa_end_cmp_ext *tpa_end1, 1582 struct sk_buff *skb) 1583 { 1584 #ifdef CONFIG_INET 1585 int payload_off; 1586 u16 segs; 1587 1588 segs = TPA_END_TPA_SEGS(tpa_end); 1589 if (segs == 1) 1590 return skb; 1591 1592 NAPI_GRO_CB(skb)->count = segs; 1593 skb_shinfo(skb)->gso_size = 1594 le32_to_cpu(tpa_end1->rx_tpa_end_cmp_seg_len); 1595 skb_shinfo(skb)->gso_type = tpa_info->gso_type; 1596 if (bp->flags & BNXT_FLAG_CHIP_P5) 1597 payload_off = TPA_END_PAYLOAD_OFF_P5(tpa_end1); 1598 else 1599 payload_off = TPA_END_PAYLOAD_OFF(tpa_end); 1600 skb = bp->gro_func(tpa_info, payload_off, TPA_END_GRO_TS(tpa_end), skb); 1601 if (likely(skb)) 1602 tcp_gro_complete(skb); 1603 #endif 1604 return skb; 1605 } 1606 1607 /* Given the cfa_code of a received packet determine which 1608 * netdev (vf-rep or PF) the packet is destined to. 1609 */ 1610 static struct net_device *bnxt_get_pkt_dev(struct bnxt *bp, u16 cfa_code) 1611 { 1612 struct net_device *dev = bnxt_get_vf_rep(bp, cfa_code); 1613 1614 /* if vf-rep dev is NULL, the must belongs to the PF */ 1615 return dev ? dev : bp->dev; 1616 } 1617 1618 static inline struct sk_buff *bnxt_tpa_end(struct bnxt *bp, 1619 struct bnxt_cp_ring_info *cpr, 1620 u32 *raw_cons, 1621 struct rx_tpa_end_cmp *tpa_end, 1622 struct rx_tpa_end_cmp_ext *tpa_end1, 1623 u8 *event) 1624 { 1625 struct bnxt_napi *bnapi = cpr->bnapi; 1626 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 1627 u8 *data_ptr, agg_bufs; 1628 unsigned int len; 1629 struct bnxt_tpa_info *tpa_info; 1630 dma_addr_t mapping; 1631 struct sk_buff *skb; 1632 u16 idx = 0, agg_id; 1633 void *data; 1634 bool gro; 1635 1636 if (unlikely(bnapi->in_reset)) { 1637 int rc = bnxt_discard_rx(bp, cpr, raw_cons, tpa_end); 1638 1639 if (rc < 0) 1640 return ERR_PTR(-EBUSY); 1641 return NULL; 1642 } 1643 1644 if (bp->flags & BNXT_FLAG_CHIP_P5) { 1645 agg_id = TPA_END_AGG_ID_P5(tpa_end); 1646 agg_id = bnxt_lookup_agg_idx(rxr, agg_id); 1647 agg_bufs = TPA_END_AGG_BUFS_P5(tpa_end1); 1648 tpa_info = &rxr->rx_tpa[agg_id]; 1649 if (unlikely(agg_bufs != tpa_info->agg_count)) { 1650 netdev_warn(bp->dev, "TPA end agg_buf %d != expected agg_bufs %d\n", 1651 agg_bufs, tpa_info->agg_count); 1652 agg_bufs = tpa_info->agg_count; 1653 } 1654 tpa_info->agg_count = 0; 1655 *event |= BNXT_AGG_EVENT; 1656 bnxt_free_agg_idx(rxr, agg_id); 1657 idx = agg_id; 1658 gro = !!(bp->flags & BNXT_FLAG_GRO); 1659 } else { 1660 agg_id = TPA_END_AGG_ID(tpa_end); 1661 agg_bufs = TPA_END_AGG_BUFS(tpa_end); 1662 tpa_info = &rxr->rx_tpa[agg_id]; 1663 idx = RING_CMP(*raw_cons); 1664 if (agg_bufs) { 1665 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, raw_cons)) 1666 return ERR_PTR(-EBUSY); 1667 1668 *event |= BNXT_AGG_EVENT; 1669 idx = NEXT_CMP(idx); 1670 } 1671 gro = !!TPA_END_GRO(tpa_end); 1672 } 1673 data = tpa_info->data; 1674 data_ptr = tpa_info->data_ptr; 1675 prefetch(data_ptr); 1676 len = tpa_info->len; 1677 mapping = tpa_info->mapping; 1678 1679 if (unlikely(agg_bufs > MAX_SKB_FRAGS || TPA_END_ERRORS(tpa_end1))) { 1680 bnxt_abort_tpa(cpr, idx, agg_bufs); 1681 if (agg_bufs > MAX_SKB_FRAGS) 1682 netdev_warn(bp->dev, "TPA frags %d exceeded MAX_SKB_FRAGS %d\n", 1683 agg_bufs, (int)MAX_SKB_FRAGS); 1684 return NULL; 1685 } 1686 1687 if (len <= bp->rx_copy_thresh) { 1688 skb = bnxt_copy_skb(bnapi, data_ptr, len, mapping); 1689 if (!skb) { 1690 bnxt_abort_tpa(cpr, idx, agg_bufs); 1691 cpr->sw_stats.rx.rx_oom_discards += 1; 1692 return NULL; 1693 } 1694 } else { 1695 u8 *new_data; 1696 dma_addr_t new_mapping; 1697 1698 new_data = __bnxt_alloc_rx_frag(bp, &new_mapping, GFP_ATOMIC); 1699 if (!new_data) { 1700 bnxt_abort_tpa(cpr, idx, agg_bufs); 1701 cpr->sw_stats.rx.rx_oom_discards += 1; 1702 return NULL; 1703 } 1704 1705 tpa_info->data = new_data; 1706 tpa_info->data_ptr = new_data + bp->rx_offset; 1707 tpa_info->mapping = new_mapping; 1708 1709 skb = build_skb(data, bp->rx_buf_size); 1710 dma_unmap_single_attrs(&bp->pdev->dev, mapping, 1711 bp->rx_buf_use_size, bp->rx_dir, 1712 DMA_ATTR_WEAK_ORDERING); 1713 1714 if (!skb) { 1715 skb_free_frag(data); 1716 bnxt_abort_tpa(cpr, idx, agg_bufs); 1717 cpr->sw_stats.rx.rx_oom_discards += 1; 1718 return NULL; 1719 } 1720 skb_reserve(skb, bp->rx_offset); 1721 skb_put(skb, len); 1722 } 1723 1724 if (agg_bufs) { 1725 skb = bnxt_rx_agg_pages_skb(bp, cpr, skb, idx, agg_bufs, true); 1726 if (!skb) { 1727 /* Page reuse already handled by bnxt_rx_pages(). */ 1728 cpr->sw_stats.rx.rx_oom_discards += 1; 1729 return NULL; 1730 } 1731 } 1732 1733 skb->protocol = 1734 eth_type_trans(skb, bnxt_get_pkt_dev(bp, tpa_info->cfa_code)); 1735 1736 if (tpa_info->hash_type != PKT_HASH_TYPE_NONE) 1737 skb_set_hash(skb, tpa_info->rss_hash, tpa_info->hash_type); 1738 1739 if ((tpa_info->flags2 & RX_CMP_FLAGS2_META_FORMAT_VLAN) && 1740 (skb->dev->features & BNXT_HW_FEATURE_VLAN_ALL_RX)) { 1741 __be16 vlan_proto = htons(tpa_info->metadata >> 1742 RX_CMP_FLAGS2_METADATA_TPID_SFT); 1743 u16 vtag = tpa_info->metadata & RX_CMP_FLAGS2_METADATA_TCI_MASK; 1744 1745 if (eth_type_vlan(vlan_proto)) { 1746 __vlan_hwaccel_put_tag(skb, vlan_proto, vtag); 1747 } else { 1748 dev_kfree_skb(skb); 1749 return NULL; 1750 } 1751 } 1752 1753 skb_checksum_none_assert(skb); 1754 if (likely(tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_L4_CS_CALC)) { 1755 skb->ip_summed = CHECKSUM_UNNECESSARY; 1756 skb->csum_level = 1757 (tpa_info->flags2 & RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3; 1758 } 1759 1760 if (gro) 1761 skb = bnxt_gro_skb(bp, tpa_info, tpa_end, tpa_end1, skb); 1762 1763 return skb; 1764 } 1765 1766 static void bnxt_tpa_agg(struct bnxt *bp, struct bnxt_rx_ring_info *rxr, 1767 struct rx_agg_cmp *rx_agg) 1768 { 1769 u16 agg_id = TPA_AGG_AGG_ID(rx_agg); 1770 struct bnxt_tpa_info *tpa_info; 1771 1772 agg_id = bnxt_lookup_agg_idx(rxr, agg_id); 1773 tpa_info = &rxr->rx_tpa[agg_id]; 1774 BUG_ON(tpa_info->agg_count >= MAX_SKB_FRAGS); 1775 tpa_info->agg_arr[tpa_info->agg_count++] = *rx_agg; 1776 } 1777 1778 static void bnxt_deliver_skb(struct bnxt *bp, struct bnxt_napi *bnapi, 1779 struct sk_buff *skb) 1780 { 1781 if (skb->dev != bp->dev) { 1782 /* this packet belongs to a vf-rep */ 1783 bnxt_vf_rep_rx(bp, skb); 1784 return; 1785 } 1786 skb_record_rx_queue(skb, bnapi->index); 1787 napi_gro_receive(&bnapi->napi, skb); 1788 } 1789 1790 /* returns the following: 1791 * 1 - 1 packet successfully received 1792 * 0 - successful TPA_START, packet not completed yet 1793 * -EBUSY - completion ring does not have all the agg buffers yet 1794 * -ENOMEM - packet aborted due to out of memory 1795 * -EIO - packet aborted due to hw error indicated in BD 1796 */ 1797 static int bnxt_rx_pkt(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, 1798 u32 *raw_cons, u8 *event) 1799 { 1800 struct bnxt_napi *bnapi = cpr->bnapi; 1801 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 1802 struct net_device *dev = bp->dev; 1803 struct rx_cmp *rxcmp; 1804 struct rx_cmp_ext *rxcmp1; 1805 u32 tmp_raw_cons = *raw_cons; 1806 u16 cfa_code, cons, prod, cp_cons = RING_CMP(tmp_raw_cons); 1807 struct bnxt_sw_rx_bd *rx_buf; 1808 unsigned int len; 1809 u8 *data_ptr, agg_bufs, cmp_type; 1810 bool xdp_active = false; 1811 dma_addr_t dma_addr; 1812 struct sk_buff *skb; 1813 struct xdp_buff xdp; 1814 u32 flags, misc; 1815 void *data; 1816 int rc = 0; 1817 1818 rxcmp = (struct rx_cmp *) 1819 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 1820 1821 cmp_type = RX_CMP_TYPE(rxcmp); 1822 1823 if (cmp_type == CMP_TYPE_RX_TPA_AGG_CMP) { 1824 bnxt_tpa_agg(bp, rxr, (struct rx_agg_cmp *)rxcmp); 1825 goto next_rx_no_prod_no_len; 1826 } 1827 1828 tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons); 1829 cp_cons = RING_CMP(tmp_raw_cons); 1830 rxcmp1 = (struct rx_cmp_ext *) 1831 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 1832 1833 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons)) 1834 return -EBUSY; 1835 1836 /* The valid test of the entry must be done first before 1837 * reading any further. 1838 */ 1839 dma_rmb(); 1840 prod = rxr->rx_prod; 1841 1842 if (cmp_type == CMP_TYPE_RX_L2_TPA_START_CMP) { 1843 bnxt_tpa_start(bp, rxr, (struct rx_tpa_start_cmp *)rxcmp, 1844 (struct rx_tpa_start_cmp_ext *)rxcmp1); 1845 1846 *event |= BNXT_RX_EVENT; 1847 goto next_rx_no_prod_no_len; 1848 1849 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) { 1850 skb = bnxt_tpa_end(bp, cpr, &tmp_raw_cons, 1851 (struct rx_tpa_end_cmp *)rxcmp, 1852 (struct rx_tpa_end_cmp_ext *)rxcmp1, event); 1853 1854 if (IS_ERR(skb)) 1855 return -EBUSY; 1856 1857 rc = -ENOMEM; 1858 if (likely(skb)) { 1859 bnxt_deliver_skb(bp, bnapi, skb); 1860 rc = 1; 1861 } 1862 *event |= BNXT_RX_EVENT; 1863 goto next_rx_no_prod_no_len; 1864 } 1865 1866 cons = rxcmp->rx_cmp_opaque; 1867 if (unlikely(cons != rxr->rx_next_cons)) { 1868 int rc1 = bnxt_discard_rx(bp, cpr, &tmp_raw_cons, rxcmp); 1869 1870 /* 0xffff is forced error, don't print it */ 1871 if (rxr->rx_next_cons != 0xffff) 1872 netdev_warn(bp->dev, "RX cons %x != expected cons %x\n", 1873 cons, rxr->rx_next_cons); 1874 bnxt_sched_reset_rxr(bp, rxr); 1875 if (rc1) 1876 return rc1; 1877 goto next_rx_no_prod_no_len; 1878 } 1879 rx_buf = &rxr->rx_buf_ring[cons]; 1880 data = rx_buf->data; 1881 data_ptr = rx_buf->data_ptr; 1882 prefetch(data_ptr); 1883 1884 misc = le32_to_cpu(rxcmp->rx_cmp_misc_v1); 1885 agg_bufs = (misc & RX_CMP_AGG_BUFS) >> RX_CMP_AGG_BUFS_SHIFT; 1886 1887 if (agg_bufs) { 1888 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons)) 1889 return -EBUSY; 1890 1891 cp_cons = NEXT_CMP(cp_cons); 1892 *event |= BNXT_AGG_EVENT; 1893 } 1894 *event |= BNXT_RX_EVENT; 1895 1896 rx_buf->data = NULL; 1897 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L2_ERRORS) { 1898 u32 rx_err = le32_to_cpu(rxcmp1->rx_cmp_cfa_code_errors_v2); 1899 1900 bnxt_reuse_rx_data(rxr, cons, data); 1901 if (agg_bufs) 1902 bnxt_reuse_rx_agg_bufs(cpr, cp_cons, 0, agg_bufs, 1903 false); 1904 1905 rc = -EIO; 1906 if (rx_err & RX_CMPL_ERRORS_BUFFER_ERROR_MASK) { 1907 bnapi->cp_ring.sw_stats.rx.rx_buf_errors++; 1908 if (!(bp->flags & BNXT_FLAG_CHIP_P5) && 1909 !(bp->fw_cap & BNXT_FW_CAP_RING_MONITOR)) { 1910 netdev_warn_once(bp->dev, "RX buffer error %x\n", 1911 rx_err); 1912 bnxt_sched_reset_rxr(bp, rxr); 1913 } 1914 } 1915 goto next_rx_no_len; 1916 } 1917 1918 flags = le32_to_cpu(rxcmp->rx_cmp_len_flags_type); 1919 len = flags >> RX_CMP_LEN_SHIFT; 1920 dma_addr = rx_buf->mapping; 1921 1922 if (bnxt_xdp_attached(bp, rxr)) { 1923 bnxt_xdp_buff_init(bp, rxr, cons, data_ptr, len, &xdp); 1924 if (agg_bufs) { 1925 u32 frag_len = bnxt_rx_agg_pages_xdp(bp, cpr, &xdp, 1926 cp_cons, agg_bufs, 1927 false); 1928 if (!frag_len) { 1929 cpr->sw_stats.rx.rx_oom_discards += 1; 1930 rc = -ENOMEM; 1931 goto next_rx; 1932 } 1933 } 1934 xdp_active = true; 1935 } 1936 1937 if (xdp_active) { 1938 if (bnxt_rx_xdp(bp, rxr, cons, xdp, data, &data_ptr, &len, event)) { 1939 rc = 1; 1940 goto next_rx; 1941 } 1942 } 1943 1944 if (len <= bp->rx_copy_thresh) { 1945 skb = bnxt_copy_skb(bnapi, data_ptr, len, dma_addr); 1946 bnxt_reuse_rx_data(rxr, cons, data); 1947 if (!skb) { 1948 if (agg_bufs) { 1949 if (!xdp_active) 1950 bnxt_reuse_rx_agg_bufs(cpr, cp_cons, 0, 1951 agg_bufs, false); 1952 else 1953 bnxt_xdp_buff_frags_free(rxr, &xdp); 1954 } 1955 cpr->sw_stats.rx.rx_oom_discards += 1; 1956 rc = -ENOMEM; 1957 goto next_rx; 1958 } 1959 } else { 1960 u32 payload; 1961 1962 if (rx_buf->data_ptr == data_ptr) 1963 payload = misc & RX_CMP_PAYLOAD_OFFSET; 1964 else 1965 payload = 0; 1966 skb = bp->rx_skb_func(bp, rxr, cons, data, data_ptr, dma_addr, 1967 payload | len); 1968 if (!skb) { 1969 cpr->sw_stats.rx.rx_oom_discards += 1; 1970 rc = -ENOMEM; 1971 goto next_rx; 1972 } 1973 } 1974 1975 if (agg_bufs) { 1976 if (!xdp_active) { 1977 skb = bnxt_rx_agg_pages_skb(bp, cpr, skb, cp_cons, agg_bufs, false); 1978 if (!skb) { 1979 cpr->sw_stats.rx.rx_oom_discards += 1; 1980 rc = -ENOMEM; 1981 goto next_rx; 1982 } 1983 } else { 1984 skb = bnxt_xdp_build_skb(bp, skb, agg_bufs, rxr->page_pool, &xdp, rxcmp1); 1985 if (!skb) { 1986 /* we should be able to free the old skb here */ 1987 bnxt_xdp_buff_frags_free(rxr, &xdp); 1988 cpr->sw_stats.rx.rx_oom_discards += 1; 1989 rc = -ENOMEM; 1990 goto next_rx; 1991 } 1992 } 1993 } 1994 1995 if (RX_CMP_HASH_VALID(rxcmp)) { 1996 u32 hash_type = RX_CMP_HASH_TYPE(rxcmp); 1997 enum pkt_hash_types type = PKT_HASH_TYPE_L4; 1998 1999 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */ 2000 if (hash_type != 1 && hash_type != 3) 2001 type = PKT_HASH_TYPE_L3; 2002 skb_set_hash(skb, le32_to_cpu(rxcmp->rx_cmp_rss_hash), type); 2003 } 2004 2005 cfa_code = RX_CMP_CFA_CODE(rxcmp1); 2006 skb->protocol = eth_type_trans(skb, bnxt_get_pkt_dev(bp, cfa_code)); 2007 2008 if ((rxcmp1->rx_cmp_flags2 & 2009 cpu_to_le32(RX_CMP_FLAGS2_META_FORMAT_VLAN)) && 2010 (skb->dev->features & BNXT_HW_FEATURE_VLAN_ALL_RX)) { 2011 u32 meta_data = le32_to_cpu(rxcmp1->rx_cmp_meta_data); 2012 u16 vtag = meta_data & RX_CMP_FLAGS2_METADATA_TCI_MASK; 2013 __be16 vlan_proto = htons(meta_data >> 2014 RX_CMP_FLAGS2_METADATA_TPID_SFT); 2015 2016 if (eth_type_vlan(vlan_proto)) { 2017 __vlan_hwaccel_put_tag(skb, vlan_proto, vtag); 2018 } else { 2019 dev_kfree_skb(skb); 2020 goto next_rx; 2021 } 2022 } 2023 2024 skb_checksum_none_assert(skb); 2025 if (RX_CMP_L4_CS_OK(rxcmp1)) { 2026 if (dev->features & NETIF_F_RXCSUM) { 2027 skb->ip_summed = CHECKSUM_UNNECESSARY; 2028 skb->csum_level = RX_CMP_ENCAP(rxcmp1); 2029 } 2030 } else { 2031 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS) { 2032 if (dev->features & NETIF_F_RXCSUM) 2033 bnapi->cp_ring.sw_stats.rx.rx_l4_csum_errors++; 2034 } 2035 } 2036 2037 if (unlikely((flags & RX_CMP_FLAGS_ITYPES_MASK) == 2038 RX_CMP_FLAGS_ITYPE_PTP_W_TS) || bp->ptp_all_rx_tstamp) { 2039 if (bp->flags & BNXT_FLAG_CHIP_P5) { 2040 u32 cmpl_ts = le32_to_cpu(rxcmp1->rx_cmp_timestamp); 2041 u64 ns, ts; 2042 2043 if (!bnxt_get_rx_ts_p5(bp, &ts, cmpl_ts)) { 2044 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 2045 2046 spin_lock_bh(&ptp->ptp_lock); 2047 ns = timecounter_cyc2time(&ptp->tc, ts); 2048 spin_unlock_bh(&ptp->ptp_lock); 2049 memset(skb_hwtstamps(skb), 0, 2050 sizeof(*skb_hwtstamps(skb))); 2051 skb_hwtstamps(skb)->hwtstamp = ns_to_ktime(ns); 2052 } 2053 } 2054 } 2055 bnxt_deliver_skb(bp, bnapi, skb); 2056 rc = 1; 2057 2058 next_rx: 2059 cpr->rx_packets += 1; 2060 cpr->rx_bytes += len; 2061 2062 next_rx_no_len: 2063 rxr->rx_prod = NEXT_RX(prod); 2064 rxr->rx_next_cons = NEXT_RX(cons); 2065 2066 next_rx_no_prod_no_len: 2067 *raw_cons = tmp_raw_cons; 2068 2069 return rc; 2070 } 2071 2072 /* In netpoll mode, if we are using a combined completion ring, we need to 2073 * discard the rx packets and recycle the buffers. 2074 */ 2075 static int bnxt_force_rx_discard(struct bnxt *bp, 2076 struct bnxt_cp_ring_info *cpr, 2077 u32 *raw_cons, u8 *event) 2078 { 2079 u32 tmp_raw_cons = *raw_cons; 2080 struct rx_cmp_ext *rxcmp1; 2081 struct rx_cmp *rxcmp; 2082 u16 cp_cons; 2083 u8 cmp_type; 2084 int rc; 2085 2086 cp_cons = RING_CMP(tmp_raw_cons); 2087 rxcmp = (struct rx_cmp *) 2088 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 2089 2090 tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons); 2091 cp_cons = RING_CMP(tmp_raw_cons); 2092 rxcmp1 = (struct rx_cmp_ext *) 2093 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 2094 2095 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons)) 2096 return -EBUSY; 2097 2098 /* The valid test of the entry must be done first before 2099 * reading any further. 2100 */ 2101 dma_rmb(); 2102 cmp_type = RX_CMP_TYPE(rxcmp); 2103 if (cmp_type == CMP_TYPE_RX_L2_CMP) { 2104 rxcmp1->rx_cmp_cfa_code_errors_v2 |= 2105 cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR); 2106 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) { 2107 struct rx_tpa_end_cmp_ext *tpa_end1; 2108 2109 tpa_end1 = (struct rx_tpa_end_cmp_ext *)rxcmp1; 2110 tpa_end1->rx_tpa_end_cmp_errors_v2 |= 2111 cpu_to_le32(RX_TPA_END_CMP_ERRORS); 2112 } 2113 rc = bnxt_rx_pkt(bp, cpr, raw_cons, event); 2114 if (rc && rc != -EBUSY) 2115 cpr->sw_stats.rx.rx_netpoll_discards += 1; 2116 return rc; 2117 } 2118 2119 u32 bnxt_fw_health_readl(struct bnxt *bp, int reg_idx) 2120 { 2121 struct bnxt_fw_health *fw_health = bp->fw_health; 2122 u32 reg = fw_health->regs[reg_idx]; 2123 u32 reg_type, reg_off, val = 0; 2124 2125 reg_type = BNXT_FW_HEALTH_REG_TYPE(reg); 2126 reg_off = BNXT_FW_HEALTH_REG_OFF(reg); 2127 switch (reg_type) { 2128 case BNXT_FW_HEALTH_REG_TYPE_CFG: 2129 pci_read_config_dword(bp->pdev, reg_off, &val); 2130 break; 2131 case BNXT_FW_HEALTH_REG_TYPE_GRC: 2132 reg_off = fw_health->mapped_regs[reg_idx]; 2133 fallthrough; 2134 case BNXT_FW_HEALTH_REG_TYPE_BAR0: 2135 val = readl(bp->bar0 + reg_off); 2136 break; 2137 case BNXT_FW_HEALTH_REG_TYPE_BAR1: 2138 val = readl(bp->bar1 + reg_off); 2139 break; 2140 } 2141 if (reg_idx == BNXT_FW_RESET_INPROG_REG) 2142 val &= fw_health->fw_reset_inprog_reg_mask; 2143 return val; 2144 } 2145 2146 static u16 bnxt_agg_ring_id_to_grp_idx(struct bnxt *bp, u16 ring_id) 2147 { 2148 int i; 2149 2150 for (i = 0; i < bp->rx_nr_rings; i++) { 2151 u16 grp_idx = bp->rx_ring[i].bnapi->index; 2152 struct bnxt_ring_grp_info *grp_info; 2153 2154 grp_info = &bp->grp_info[grp_idx]; 2155 if (grp_info->agg_fw_ring_id == ring_id) 2156 return grp_idx; 2157 } 2158 return INVALID_HW_RING_ID; 2159 } 2160 2161 static void bnxt_event_error_report(struct bnxt *bp, u32 data1, u32 data2) 2162 { 2163 u32 err_type = BNXT_EVENT_ERROR_REPORT_TYPE(data1); 2164 2165 switch (err_type) { 2166 case ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL: 2167 netdev_err(bp->dev, "1PPS: Received invalid signal on pin%lu from the external source. Please fix the signal and reconfigure the pin\n", 2168 BNXT_EVENT_INVALID_SIGNAL_DATA(data2)); 2169 break; 2170 case ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_PAUSE_STORM: 2171 netdev_warn(bp->dev, "Pause Storm detected!\n"); 2172 break; 2173 case ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD: 2174 netdev_warn(bp->dev, "One or more MMIO doorbells dropped by the device!\n"); 2175 break; 2176 default: 2177 netdev_err(bp->dev, "FW reported unknown error type %u\n", 2178 err_type); 2179 break; 2180 } 2181 } 2182 2183 #define BNXT_GET_EVENT_PORT(data) \ 2184 ((data) & \ 2185 ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK) 2186 2187 #define BNXT_EVENT_RING_TYPE(data2) \ 2188 ((data2) & \ 2189 ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_MASK) 2190 2191 #define BNXT_EVENT_RING_TYPE_RX(data2) \ 2192 (BNXT_EVENT_RING_TYPE(data2) == \ 2193 ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_RX) 2194 2195 #define BNXT_EVENT_PHC_EVENT_TYPE(data1) \ 2196 (((data1) & ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_MASK) >>\ 2197 ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_SFT) 2198 2199 #define BNXT_EVENT_PHC_RTC_UPDATE(data1) \ 2200 (((data1) & ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_PHC_TIME_MSB_MASK) >>\ 2201 ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_PHC_TIME_MSB_SFT) 2202 2203 #define BNXT_PHC_BITS 48 2204 2205 static int bnxt_async_event_process(struct bnxt *bp, 2206 struct hwrm_async_event_cmpl *cmpl) 2207 { 2208 u16 event_id = le16_to_cpu(cmpl->event_id); 2209 u32 data1 = le32_to_cpu(cmpl->event_data1); 2210 u32 data2 = le32_to_cpu(cmpl->event_data2); 2211 2212 netdev_dbg(bp->dev, "hwrm event 0x%x {0x%x, 0x%x}\n", 2213 event_id, data1, data2); 2214 2215 /* TODO CHIMP_FW: Define event id's for link change, error etc */ 2216 switch (event_id) { 2217 case ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE: { 2218 struct bnxt_link_info *link_info = &bp->link_info; 2219 2220 if (BNXT_VF(bp)) 2221 goto async_event_process_exit; 2222 2223 /* print unsupported speed warning in forced speed mode only */ 2224 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED) && 2225 (data1 & 0x20000)) { 2226 u16 fw_speed = link_info->force_link_speed; 2227 u32 speed = bnxt_fw_to_ethtool_speed(fw_speed); 2228 2229 if (speed != SPEED_UNKNOWN) 2230 netdev_warn(bp->dev, "Link speed %d no longer supported\n", 2231 speed); 2232 } 2233 set_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT, &bp->sp_event); 2234 } 2235 fallthrough; 2236 case ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE: 2237 case ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE: 2238 set_bit(BNXT_LINK_CFG_CHANGE_SP_EVENT, &bp->sp_event); 2239 fallthrough; 2240 case ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE: 2241 set_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event); 2242 break; 2243 case ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD: 2244 set_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event); 2245 break; 2246 case ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED: { 2247 u16 port_id = BNXT_GET_EVENT_PORT(data1); 2248 2249 if (BNXT_VF(bp)) 2250 break; 2251 2252 if (bp->pf.port_id != port_id) 2253 break; 2254 2255 set_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event); 2256 break; 2257 } 2258 case ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE: 2259 if (BNXT_PF(bp)) 2260 goto async_event_process_exit; 2261 set_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event); 2262 break; 2263 case ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY: { 2264 char *type_str = "Solicited"; 2265 2266 if (!bp->fw_health) 2267 goto async_event_process_exit; 2268 2269 bp->fw_reset_timestamp = jiffies; 2270 bp->fw_reset_min_dsecs = cmpl->timestamp_lo; 2271 if (!bp->fw_reset_min_dsecs) 2272 bp->fw_reset_min_dsecs = BNXT_DFLT_FW_RST_MIN_DSECS; 2273 bp->fw_reset_max_dsecs = le16_to_cpu(cmpl->timestamp_hi); 2274 if (!bp->fw_reset_max_dsecs) 2275 bp->fw_reset_max_dsecs = BNXT_DFLT_FW_RST_MAX_DSECS; 2276 if (EVENT_DATA1_RESET_NOTIFY_FW_ACTIVATION(data1)) { 2277 set_bit(BNXT_STATE_FW_ACTIVATE_RESET, &bp->state); 2278 } else if (EVENT_DATA1_RESET_NOTIFY_FATAL(data1)) { 2279 type_str = "Fatal"; 2280 bp->fw_health->fatalities++; 2281 set_bit(BNXT_STATE_FW_FATAL_COND, &bp->state); 2282 } else if (data2 && BNXT_FW_STATUS_HEALTHY != 2283 EVENT_DATA2_RESET_NOTIFY_FW_STATUS_CODE(data2)) { 2284 type_str = "Non-fatal"; 2285 bp->fw_health->survivals++; 2286 set_bit(BNXT_STATE_FW_NON_FATAL_COND, &bp->state); 2287 } 2288 netif_warn(bp, hw, bp->dev, 2289 "%s firmware reset event, data1: 0x%x, data2: 0x%x, min wait %u ms, max wait %u ms\n", 2290 type_str, data1, data2, 2291 bp->fw_reset_min_dsecs * 100, 2292 bp->fw_reset_max_dsecs * 100); 2293 set_bit(BNXT_FW_RESET_NOTIFY_SP_EVENT, &bp->sp_event); 2294 break; 2295 } 2296 case ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY: { 2297 struct bnxt_fw_health *fw_health = bp->fw_health; 2298 char *status_desc = "healthy"; 2299 u32 status; 2300 2301 if (!fw_health) 2302 goto async_event_process_exit; 2303 2304 if (!EVENT_DATA1_RECOVERY_ENABLED(data1)) { 2305 fw_health->enabled = false; 2306 netif_info(bp, drv, bp->dev, "Driver recovery watchdog is disabled\n"); 2307 break; 2308 } 2309 fw_health->primary = EVENT_DATA1_RECOVERY_MASTER_FUNC(data1); 2310 fw_health->tmr_multiplier = 2311 DIV_ROUND_UP(fw_health->polling_dsecs * HZ, 2312 bp->current_interval * 10); 2313 fw_health->tmr_counter = fw_health->tmr_multiplier; 2314 if (!fw_health->enabled) 2315 fw_health->last_fw_heartbeat = 2316 bnxt_fw_health_readl(bp, BNXT_FW_HEARTBEAT_REG); 2317 fw_health->last_fw_reset_cnt = 2318 bnxt_fw_health_readl(bp, BNXT_FW_RESET_CNT_REG); 2319 status = bnxt_fw_health_readl(bp, BNXT_FW_HEALTH_REG); 2320 if (status != BNXT_FW_STATUS_HEALTHY) 2321 status_desc = "unhealthy"; 2322 netif_info(bp, drv, bp->dev, 2323 "Driver recovery watchdog, role: %s, firmware status: 0x%x (%s), resets: %u\n", 2324 fw_health->primary ? "primary" : "backup", status, 2325 status_desc, fw_health->last_fw_reset_cnt); 2326 if (!fw_health->enabled) { 2327 /* Make sure tmr_counter is set and visible to 2328 * bnxt_health_check() before setting enabled to true. 2329 */ 2330 smp_wmb(); 2331 fw_health->enabled = true; 2332 } 2333 goto async_event_process_exit; 2334 } 2335 case ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION: 2336 netif_notice(bp, hw, bp->dev, 2337 "Received firmware debug notification, data1: 0x%x, data2: 0x%x\n", 2338 data1, data2); 2339 goto async_event_process_exit; 2340 case ASYNC_EVENT_CMPL_EVENT_ID_RING_MONITOR_MSG: { 2341 struct bnxt_rx_ring_info *rxr; 2342 u16 grp_idx; 2343 2344 if (bp->flags & BNXT_FLAG_CHIP_P5) 2345 goto async_event_process_exit; 2346 2347 netdev_warn(bp->dev, "Ring monitor event, ring type %lu id 0x%x\n", 2348 BNXT_EVENT_RING_TYPE(data2), data1); 2349 if (!BNXT_EVENT_RING_TYPE_RX(data2)) 2350 goto async_event_process_exit; 2351 2352 grp_idx = bnxt_agg_ring_id_to_grp_idx(bp, data1); 2353 if (grp_idx == INVALID_HW_RING_ID) { 2354 netdev_warn(bp->dev, "Unknown RX agg ring id 0x%x\n", 2355 data1); 2356 goto async_event_process_exit; 2357 } 2358 rxr = bp->bnapi[grp_idx]->rx_ring; 2359 bnxt_sched_reset_rxr(bp, rxr); 2360 goto async_event_process_exit; 2361 } 2362 case ASYNC_EVENT_CMPL_EVENT_ID_ECHO_REQUEST: { 2363 struct bnxt_fw_health *fw_health = bp->fw_health; 2364 2365 netif_notice(bp, hw, bp->dev, 2366 "Received firmware echo request, data1: 0x%x, data2: 0x%x\n", 2367 data1, data2); 2368 if (fw_health) { 2369 fw_health->echo_req_data1 = data1; 2370 fw_health->echo_req_data2 = data2; 2371 set_bit(BNXT_FW_ECHO_REQUEST_SP_EVENT, &bp->sp_event); 2372 break; 2373 } 2374 goto async_event_process_exit; 2375 } 2376 case ASYNC_EVENT_CMPL_EVENT_ID_PPS_TIMESTAMP: { 2377 bnxt_ptp_pps_event(bp, data1, data2); 2378 goto async_event_process_exit; 2379 } 2380 case ASYNC_EVENT_CMPL_EVENT_ID_ERROR_REPORT: { 2381 bnxt_event_error_report(bp, data1, data2); 2382 goto async_event_process_exit; 2383 } 2384 case ASYNC_EVENT_CMPL_EVENT_ID_PHC_UPDATE: { 2385 switch (BNXT_EVENT_PHC_EVENT_TYPE(data1)) { 2386 case ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_RTC_UPDATE: 2387 if (BNXT_PTP_USE_RTC(bp)) { 2388 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 2389 u64 ns; 2390 2391 if (!ptp) 2392 goto async_event_process_exit; 2393 2394 spin_lock_bh(&ptp->ptp_lock); 2395 bnxt_ptp_update_current_time(bp); 2396 ns = (((u64)BNXT_EVENT_PHC_RTC_UPDATE(data1) << 2397 BNXT_PHC_BITS) | ptp->current_time); 2398 bnxt_ptp_rtc_timecounter_init(ptp, ns); 2399 spin_unlock_bh(&ptp->ptp_lock); 2400 } 2401 break; 2402 } 2403 goto async_event_process_exit; 2404 } 2405 case ASYNC_EVENT_CMPL_EVENT_ID_DEFERRED_RESPONSE: { 2406 u16 seq_id = le32_to_cpu(cmpl->event_data2) & 0xffff; 2407 2408 hwrm_update_token(bp, seq_id, BNXT_HWRM_DEFERRED); 2409 goto async_event_process_exit; 2410 } 2411 default: 2412 goto async_event_process_exit; 2413 } 2414 __bnxt_queue_sp_work(bp); 2415 async_event_process_exit: 2416 return 0; 2417 } 2418 2419 static int bnxt_hwrm_handler(struct bnxt *bp, struct tx_cmp *txcmp) 2420 { 2421 u16 cmpl_type = TX_CMP_TYPE(txcmp), vf_id, seq_id; 2422 struct hwrm_cmpl *h_cmpl = (struct hwrm_cmpl *)txcmp; 2423 struct hwrm_fwd_req_cmpl *fwd_req_cmpl = 2424 (struct hwrm_fwd_req_cmpl *)txcmp; 2425 2426 switch (cmpl_type) { 2427 case CMPL_BASE_TYPE_HWRM_DONE: 2428 seq_id = le16_to_cpu(h_cmpl->sequence_id); 2429 hwrm_update_token(bp, seq_id, BNXT_HWRM_COMPLETE); 2430 break; 2431 2432 case CMPL_BASE_TYPE_HWRM_FWD_REQ: 2433 vf_id = le16_to_cpu(fwd_req_cmpl->source_id); 2434 2435 if ((vf_id < bp->pf.first_vf_id) || 2436 (vf_id >= bp->pf.first_vf_id + bp->pf.active_vfs)) { 2437 netdev_err(bp->dev, "Msg contains invalid VF id %x\n", 2438 vf_id); 2439 return -EINVAL; 2440 } 2441 2442 set_bit(vf_id - bp->pf.first_vf_id, bp->pf.vf_event_bmap); 2443 bnxt_queue_sp_work(bp, BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT); 2444 break; 2445 2446 case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT: 2447 bnxt_async_event_process(bp, 2448 (struct hwrm_async_event_cmpl *)txcmp); 2449 break; 2450 2451 default: 2452 break; 2453 } 2454 2455 return 0; 2456 } 2457 2458 static irqreturn_t bnxt_msix(int irq, void *dev_instance) 2459 { 2460 struct bnxt_napi *bnapi = dev_instance; 2461 struct bnxt *bp = bnapi->bp; 2462 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 2463 u32 cons = RING_CMP(cpr->cp_raw_cons); 2464 2465 cpr->event_ctr++; 2466 prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]); 2467 napi_schedule(&bnapi->napi); 2468 return IRQ_HANDLED; 2469 } 2470 2471 static inline int bnxt_has_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr) 2472 { 2473 u32 raw_cons = cpr->cp_raw_cons; 2474 u16 cons = RING_CMP(raw_cons); 2475 struct tx_cmp *txcmp; 2476 2477 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]; 2478 2479 return TX_CMP_VALID(txcmp, raw_cons); 2480 } 2481 2482 static irqreturn_t bnxt_inta(int irq, void *dev_instance) 2483 { 2484 struct bnxt_napi *bnapi = dev_instance; 2485 struct bnxt *bp = bnapi->bp; 2486 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 2487 u32 cons = RING_CMP(cpr->cp_raw_cons); 2488 u32 int_status; 2489 2490 prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]); 2491 2492 if (!bnxt_has_work(bp, cpr)) { 2493 int_status = readl(bp->bar0 + BNXT_CAG_REG_LEGACY_INT_STATUS); 2494 /* return if erroneous interrupt */ 2495 if (!(int_status & (0x10000 << cpr->cp_ring_struct.fw_ring_id))) 2496 return IRQ_NONE; 2497 } 2498 2499 /* disable ring IRQ */ 2500 BNXT_CP_DB_IRQ_DIS(cpr->cp_db.doorbell); 2501 2502 /* Return here if interrupt is shared and is disabled. */ 2503 if (unlikely(atomic_read(&bp->intr_sem) != 0)) 2504 return IRQ_HANDLED; 2505 2506 napi_schedule(&bnapi->napi); 2507 return IRQ_HANDLED; 2508 } 2509 2510 static int __bnxt_poll_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, 2511 int budget) 2512 { 2513 struct bnxt_napi *bnapi = cpr->bnapi; 2514 u32 raw_cons = cpr->cp_raw_cons; 2515 u32 cons; 2516 int tx_pkts = 0; 2517 int rx_pkts = 0; 2518 u8 event = 0; 2519 struct tx_cmp *txcmp; 2520 2521 cpr->has_more_work = 0; 2522 cpr->had_work_done = 1; 2523 while (1) { 2524 int rc; 2525 2526 cons = RING_CMP(raw_cons); 2527 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]; 2528 2529 if (!TX_CMP_VALID(txcmp, raw_cons)) 2530 break; 2531 2532 /* The valid test of the entry must be done first before 2533 * reading any further. 2534 */ 2535 dma_rmb(); 2536 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_TX_L2_CMP) { 2537 tx_pkts++; 2538 /* return full budget so NAPI will complete. */ 2539 if (unlikely(tx_pkts >= bp->tx_wake_thresh)) { 2540 rx_pkts = budget; 2541 raw_cons = NEXT_RAW_CMP(raw_cons); 2542 if (budget) 2543 cpr->has_more_work = 1; 2544 break; 2545 } 2546 } else if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) { 2547 if (likely(budget)) 2548 rc = bnxt_rx_pkt(bp, cpr, &raw_cons, &event); 2549 else 2550 rc = bnxt_force_rx_discard(bp, cpr, &raw_cons, 2551 &event); 2552 if (likely(rc >= 0)) 2553 rx_pkts += rc; 2554 /* Increment rx_pkts when rc is -ENOMEM to count towards 2555 * the NAPI budget. Otherwise, we may potentially loop 2556 * here forever if we consistently cannot allocate 2557 * buffers. 2558 */ 2559 else if (rc == -ENOMEM && budget) 2560 rx_pkts++; 2561 else if (rc == -EBUSY) /* partial completion */ 2562 break; 2563 } else if (unlikely((TX_CMP_TYPE(txcmp) == 2564 CMPL_BASE_TYPE_HWRM_DONE) || 2565 (TX_CMP_TYPE(txcmp) == 2566 CMPL_BASE_TYPE_HWRM_FWD_REQ) || 2567 (TX_CMP_TYPE(txcmp) == 2568 CMPL_BASE_TYPE_HWRM_ASYNC_EVENT))) { 2569 bnxt_hwrm_handler(bp, txcmp); 2570 } 2571 raw_cons = NEXT_RAW_CMP(raw_cons); 2572 2573 if (rx_pkts && rx_pkts == budget) { 2574 cpr->has_more_work = 1; 2575 break; 2576 } 2577 } 2578 2579 if (event & BNXT_REDIRECT_EVENT) 2580 xdp_do_flush(); 2581 2582 if (event & BNXT_TX_EVENT) { 2583 struct bnxt_tx_ring_info *txr = bnapi->tx_ring; 2584 u16 prod = txr->tx_prod; 2585 2586 /* Sync BD data before updating doorbell */ 2587 wmb(); 2588 2589 bnxt_db_write_relaxed(bp, &txr->tx_db, prod); 2590 } 2591 2592 cpr->cp_raw_cons = raw_cons; 2593 bnapi->tx_pkts += tx_pkts; 2594 bnapi->events |= event; 2595 return rx_pkts; 2596 } 2597 2598 static void __bnxt_poll_work_done(struct bnxt *bp, struct bnxt_napi *bnapi) 2599 { 2600 if (bnapi->tx_pkts && !bnapi->tx_fault) { 2601 bnapi->tx_int(bp, bnapi, bnapi->tx_pkts); 2602 bnapi->tx_pkts = 0; 2603 } 2604 2605 if ((bnapi->events & BNXT_RX_EVENT) && !(bnapi->in_reset)) { 2606 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 2607 2608 bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod); 2609 } 2610 if (bnapi->events & BNXT_AGG_EVENT) { 2611 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 2612 2613 bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod); 2614 } 2615 bnapi->events = 0; 2616 } 2617 2618 static int bnxt_poll_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, 2619 int budget) 2620 { 2621 struct bnxt_napi *bnapi = cpr->bnapi; 2622 int rx_pkts; 2623 2624 rx_pkts = __bnxt_poll_work(bp, cpr, budget); 2625 2626 /* ACK completion ring before freeing tx ring and producing new 2627 * buffers in rx/agg rings to prevent overflowing the completion 2628 * ring. 2629 */ 2630 bnxt_db_cq(bp, &cpr->cp_db, cpr->cp_raw_cons); 2631 2632 __bnxt_poll_work_done(bp, bnapi); 2633 return rx_pkts; 2634 } 2635 2636 static int bnxt_poll_nitroa0(struct napi_struct *napi, int budget) 2637 { 2638 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi); 2639 struct bnxt *bp = bnapi->bp; 2640 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 2641 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 2642 struct tx_cmp *txcmp; 2643 struct rx_cmp_ext *rxcmp1; 2644 u32 cp_cons, tmp_raw_cons; 2645 u32 raw_cons = cpr->cp_raw_cons; 2646 u32 rx_pkts = 0; 2647 u8 event = 0; 2648 2649 while (1) { 2650 int rc; 2651 2652 cp_cons = RING_CMP(raw_cons); 2653 txcmp = &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 2654 2655 if (!TX_CMP_VALID(txcmp, raw_cons)) 2656 break; 2657 2658 /* The valid test of the entry must be done first before 2659 * reading any further. 2660 */ 2661 dma_rmb(); 2662 if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) { 2663 tmp_raw_cons = NEXT_RAW_CMP(raw_cons); 2664 cp_cons = RING_CMP(tmp_raw_cons); 2665 rxcmp1 = (struct rx_cmp_ext *) 2666 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 2667 2668 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons)) 2669 break; 2670 2671 /* force an error to recycle the buffer */ 2672 rxcmp1->rx_cmp_cfa_code_errors_v2 |= 2673 cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR); 2674 2675 rc = bnxt_rx_pkt(bp, cpr, &raw_cons, &event); 2676 if (likely(rc == -EIO) && budget) 2677 rx_pkts++; 2678 else if (rc == -EBUSY) /* partial completion */ 2679 break; 2680 } else if (unlikely(TX_CMP_TYPE(txcmp) == 2681 CMPL_BASE_TYPE_HWRM_DONE)) { 2682 bnxt_hwrm_handler(bp, txcmp); 2683 } else { 2684 netdev_err(bp->dev, 2685 "Invalid completion received on special ring\n"); 2686 } 2687 raw_cons = NEXT_RAW_CMP(raw_cons); 2688 2689 if (rx_pkts == budget) 2690 break; 2691 } 2692 2693 cpr->cp_raw_cons = raw_cons; 2694 BNXT_DB_CQ(&cpr->cp_db, cpr->cp_raw_cons); 2695 bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod); 2696 2697 if (event & BNXT_AGG_EVENT) 2698 bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod); 2699 2700 if (!bnxt_has_work(bp, cpr) && rx_pkts < budget) { 2701 napi_complete_done(napi, rx_pkts); 2702 BNXT_DB_CQ_ARM(&cpr->cp_db, cpr->cp_raw_cons); 2703 } 2704 return rx_pkts; 2705 } 2706 2707 static int bnxt_poll(struct napi_struct *napi, int budget) 2708 { 2709 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi); 2710 struct bnxt *bp = bnapi->bp; 2711 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 2712 int work_done = 0; 2713 2714 if (unlikely(test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state))) { 2715 napi_complete(napi); 2716 return 0; 2717 } 2718 while (1) { 2719 work_done += bnxt_poll_work(bp, cpr, budget - work_done); 2720 2721 if (work_done >= budget) { 2722 if (!budget) 2723 BNXT_DB_CQ_ARM(&cpr->cp_db, cpr->cp_raw_cons); 2724 break; 2725 } 2726 2727 if (!bnxt_has_work(bp, cpr)) { 2728 if (napi_complete_done(napi, work_done)) 2729 BNXT_DB_CQ_ARM(&cpr->cp_db, cpr->cp_raw_cons); 2730 break; 2731 } 2732 } 2733 if (bp->flags & BNXT_FLAG_DIM) { 2734 struct dim_sample dim_sample = {}; 2735 2736 dim_update_sample(cpr->event_ctr, 2737 cpr->rx_packets, 2738 cpr->rx_bytes, 2739 &dim_sample); 2740 net_dim(&cpr->dim, dim_sample); 2741 } 2742 return work_done; 2743 } 2744 2745 static int __bnxt_poll_cqs(struct bnxt *bp, struct bnxt_napi *bnapi, int budget) 2746 { 2747 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 2748 int i, work_done = 0; 2749 2750 for (i = 0; i < 2; i++) { 2751 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[i]; 2752 2753 if (cpr2) { 2754 work_done += __bnxt_poll_work(bp, cpr2, 2755 budget - work_done); 2756 cpr->has_more_work |= cpr2->has_more_work; 2757 } 2758 } 2759 return work_done; 2760 } 2761 2762 static void __bnxt_poll_cqs_done(struct bnxt *bp, struct bnxt_napi *bnapi, 2763 u64 dbr_type) 2764 { 2765 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 2766 int i; 2767 2768 for (i = 0; i < 2; i++) { 2769 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[i]; 2770 struct bnxt_db_info *db; 2771 2772 if (cpr2 && cpr2->had_work_done) { 2773 db = &cpr2->cp_db; 2774 bnxt_writeq(bp, db->db_key64 | dbr_type | 2775 RING_CMP(cpr2->cp_raw_cons), db->doorbell); 2776 cpr2->had_work_done = 0; 2777 } 2778 } 2779 __bnxt_poll_work_done(bp, bnapi); 2780 } 2781 2782 static int bnxt_poll_p5(struct napi_struct *napi, int budget) 2783 { 2784 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi); 2785 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 2786 struct bnxt_cp_ring_info *cpr_rx; 2787 u32 raw_cons = cpr->cp_raw_cons; 2788 struct bnxt *bp = bnapi->bp; 2789 struct nqe_cn *nqcmp; 2790 int work_done = 0; 2791 u32 cons; 2792 2793 if (unlikely(test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state))) { 2794 napi_complete(napi); 2795 return 0; 2796 } 2797 if (cpr->has_more_work) { 2798 cpr->has_more_work = 0; 2799 work_done = __bnxt_poll_cqs(bp, bnapi, budget); 2800 } 2801 while (1) { 2802 cons = RING_CMP(raw_cons); 2803 nqcmp = &cpr->nq_desc_ring[CP_RING(cons)][CP_IDX(cons)]; 2804 2805 if (!NQ_CMP_VALID(nqcmp, raw_cons)) { 2806 if (cpr->has_more_work) 2807 break; 2808 2809 __bnxt_poll_cqs_done(bp, bnapi, DBR_TYPE_CQ_ARMALL); 2810 cpr->cp_raw_cons = raw_cons; 2811 if (napi_complete_done(napi, work_done)) 2812 BNXT_DB_NQ_ARM_P5(&cpr->cp_db, 2813 cpr->cp_raw_cons); 2814 goto poll_done; 2815 } 2816 2817 /* The valid test of the entry must be done first before 2818 * reading any further. 2819 */ 2820 dma_rmb(); 2821 2822 if (nqcmp->type == cpu_to_le16(NQ_CN_TYPE_CQ_NOTIFICATION)) { 2823 u32 idx = le32_to_cpu(nqcmp->cq_handle_low); 2824 struct bnxt_cp_ring_info *cpr2; 2825 2826 /* No more budget for RX work */ 2827 if (budget && work_done >= budget && idx == BNXT_RX_HDL) 2828 break; 2829 2830 cpr2 = cpr->cp_ring_arr[idx]; 2831 work_done += __bnxt_poll_work(bp, cpr2, 2832 budget - work_done); 2833 cpr->has_more_work |= cpr2->has_more_work; 2834 } else { 2835 bnxt_hwrm_handler(bp, (struct tx_cmp *)nqcmp); 2836 } 2837 raw_cons = NEXT_RAW_CMP(raw_cons); 2838 } 2839 __bnxt_poll_cqs_done(bp, bnapi, DBR_TYPE_CQ); 2840 if (raw_cons != cpr->cp_raw_cons) { 2841 cpr->cp_raw_cons = raw_cons; 2842 BNXT_DB_NQ_P5(&cpr->cp_db, raw_cons); 2843 } 2844 poll_done: 2845 cpr_rx = cpr->cp_ring_arr[BNXT_RX_HDL]; 2846 if (cpr_rx && (bp->flags & BNXT_FLAG_DIM)) { 2847 struct dim_sample dim_sample = {}; 2848 2849 dim_update_sample(cpr->event_ctr, 2850 cpr_rx->rx_packets, 2851 cpr_rx->rx_bytes, 2852 &dim_sample); 2853 net_dim(&cpr->dim, dim_sample); 2854 } 2855 return work_done; 2856 } 2857 2858 static void bnxt_free_tx_skbs(struct bnxt *bp) 2859 { 2860 int i, max_idx; 2861 struct pci_dev *pdev = bp->pdev; 2862 2863 if (!bp->tx_ring) 2864 return; 2865 2866 max_idx = bp->tx_nr_pages * TX_DESC_CNT; 2867 for (i = 0; i < bp->tx_nr_rings; i++) { 2868 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; 2869 int j; 2870 2871 if (!txr->tx_buf_ring) 2872 continue; 2873 2874 for (j = 0; j < max_idx;) { 2875 struct bnxt_sw_tx_bd *tx_buf = &txr->tx_buf_ring[j]; 2876 struct sk_buff *skb; 2877 int k, last; 2878 2879 if (i < bp->tx_nr_rings_xdp && 2880 tx_buf->action == XDP_REDIRECT) { 2881 dma_unmap_single(&pdev->dev, 2882 dma_unmap_addr(tx_buf, mapping), 2883 dma_unmap_len(tx_buf, len), 2884 DMA_TO_DEVICE); 2885 xdp_return_frame(tx_buf->xdpf); 2886 tx_buf->action = 0; 2887 tx_buf->xdpf = NULL; 2888 j++; 2889 continue; 2890 } 2891 2892 skb = tx_buf->skb; 2893 if (!skb) { 2894 j++; 2895 continue; 2896 } 2897 2898 tx_buf->skb = NULL; 2899 2900 if (tx_buf->is_push) { 2901 dev_kfree_skb(skb); 2902 j += 2; 2903 continue; 2904 } 2905 2906 dma_unmap_single(&pdev->dev, 2907 dma_unmap_addr(tx_buf, mapping), 2908 skb_headlen(skb), 2909 DMA_TO_DEVICE); 2910 2911 last = tx_buf->nr_frags; 2912 j += 2; 2913 for (k = 0; k < last; k++, j++) { 2914 int ring_idx = j & bp->tx_ring_mask; 2915 skb_frag_t *frag = &skb_shinfo(skb)->frags[k]; 2916 2917 tx_buf = &txr->tx_buf_ring[ring_idx]; 2918 dma_unmap_page( 2919 &pdev->dev, 2920 dma_unmap_addr(tx_buf, mapping), 2921 skb_frag_size(frag), DMA_TO_DEVICE); 2922 } 2923 dev_kfree_skb(skb); 2924 } 2925 netdev_tx_reset_queue(netdev_get_tx_queue(bp->dev, i)); 2926 } 2927 } 2928 2929 static void bnxt_free_one_rx_ring_skbs(struct bnxt *bp, int ring_nr) 2930 { 2931 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[ring_nr]; 2932 struct pci_dev *pdev = bp->pdev; 2933 struct bnxt_tpa_idx_map *map; 2934 int i, max_idx, max_agg_idx; 2935 2936 max_idx = bp->rx_nr_pages * RX_DESC_CNT; 2937 max_agg_idx = bp->rx_agg_nr_pages * RX_DESC_CNT; 2938 if (!rxr->rx_tpa) 2939 goto skip_rx_tpa_free; 2940 2941 for (i = 0; i < bp->max_tpa; i++) { 2942 struct bnxt_tpa_info *tpa_info = &rxr->rx_tpa[i]; 2943 u8 *data = tpa_info->data; 2944 2945 if (!data) 2946 continue; 2947 2948 dma_unmap_single_attrs(&pdev->dev, tpa_info->mapping, 2949 bp->rx_buf_use_size, bp->rx_dir, 2950 DMA_ATTR_WEAK_ORDERING); 2951 2952 tpa_info->data = NULL; 2953 2954 skb_free_frag(data); 2955 } 2956 2957 skip_rx_tpa_free: 2958 if (!rxr->rx_buf_ring) 2959 goto skip_rx_buf_free; 2960 2961 for (i = 0; i < max_idx; i++) { 2962 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[i]; 2963 dma_addr_t mapping = rx_buf->mapping; 2964 void *data = rx_buf->data; 2965 2966 if (!data) 2967 continue; 2968 2969 rx_buf->data = NULL; 2970 if (BNXT_RX_PAGE_MODE(bp)) { 2971 mapping -= bp->rx_dma_offset; 2972 dma_unmap_page_attrs(&pdev->dev, mapping, PAGE_SIZE, 2973 bp->rx_dir, 2974 DMA_ATTR_WEAK_ORDERING); 2975 page_pool_recycle_direct(rxr->page_pool, data); 2976 } else { 2977 dma_unmap_single_attrs(&pdev->dev, mapping, 2978 bp->rx_buf_use_size, bp->rx_dir, 2979 DMA_ATTR_WEAK_ORDERING); 2980 skb_free_frag(data); 2981 } 2982 } 2983 2984 skip_rx_buf_free: 2985 if (!rxr->rx_agg_ring) 2986 goto skip_rx_agg_free; 2987 2988 for (i = 0; i < max_agg_idx; i++) { 2989 struct bnxt_sw_rx_agg_bd *rx_agg_buf = &rxr->rx_agg_ring[i]; 2990 struct page *page = rx_agg_buf->page; 2991 2992 if (!page) 2993 continue; 2994 2995 if (BNXT_RX_PAGE_MODE(bp)) { 2996 dma_unmap_page_attrs(&pdev->dev, rx_agg_buf->mapping, 2997 BNXT_RX_PAGE_SIZE, bp->rx_dir, 2998 DMA_ATTR_WEAK_ORDERING); 2999 rx_agg_buf->page = NULL; 3000 __clear_bit(i, rxr->rx_agg_bmap); 3001 3002 page_pool_recycle_direct(rxr->page_pool, page); 3003 } else { 3004 dma_unmap_page_attrs(&pdev->dev, rx_agg_buf->mapping, 3005 BNXT_RX_PAGE_SIZE, DMA_FROM_DEVICE, 3006 DMA_ATTR_WEAK_ORDERING); 3007 rx_agg_buf->page = NULL; 3008 __clear_bit(i, rxr->rx_agg_bmap); 3009 3010 __free_page(page); 3011 } 3012 } 3013 3014 skip_rx_agg_free: 3015 if (rxr->rx_page) { 3016 __free_page(rxr->rx_page); 3017 rxr->rx_page = NULL; 3018 } 3019 map = rxr->rx_tpa_idx_map; 3020 if (map) 3021 memset(map->agg_idx_bmap, 0, sizeof(map->agg_idx_bmap)); 3022 } 3023 3024 static void bnxt_free_rx_skbs(struct bnxt *bp) 3025 { 3026 int i; 3027 3028 if (!bp->rx_ring) 3029 return; 3030 3031 for (i = 0; i < bp->rx_nr_rings; i++) 3032 bnxt_free_one_rx_ring_skbs(bp, i); 3033 } 3034 3035 static void bnxt_free_skbs(struct bnxt *bp) 3036 { 3037 bnxt_free_tx_skbs(bp); 3038 bnxt_free_rx_skbs(bp); 3039 } 3040 3041 static void bnxt_init_ctx_mem(struct bnxt_mem_init *mem_init, void *p, int len) 3042 { 3043 u8 init_val = mem_init->init_val; 3044 u16 offset = mem_init->offset; 3045 u8 *p2 = p; 3046 int i; 3047 3048 if (!init_val) 3049 return; 3050 if (offset == BNXT_MEM_INVALID_OFFSET) { 3051 memset(p, init_val, len); 3052 return; 3053 } 3054 for (i = 0; i < len; i += mem_init->size) 3055 *(p2 + i + offset) = init_val; 3056 } 3057 3058 static void bnxt_free_ring(struct bnxt *bp, struct bnxt_ring_mem_info *rmem) 3059 { 3060 struct pci_dev *pdev = bp->pdev; 3061 int i; 3062 3063 if (!rmem->pg_arr) 3064 goto skip_pages; 3065 3066 for (i = 0; i < rmem->nr_pages; i++) { 3067 if (!rmem->pg_arr[i]) 3068 continue; 3069 3070 dma_free_coherent(&pdev->dev, rmem->page_size, 3071 rmem->pg_arr[i], rmem->dma_arr[i]); 3072 3073 rmem->pg_arr[i] = NULL; 3074 } 3075 skip_pages: 3076 if (rmem->pg_tbl) { 3077 size_t pg_tbl_size = rmem->nr_pages * 8; 3078 3079 if (rmem->flags & BNXT_RMEM_USE_FULL_PAGE_FLAG) 3080 pg_tbl_size = rmem->page_size; 3081 dma_free_coherent(&pdev->dev, pg_tbl_size, 3082 rmem->pg_tbl, rmem->pg_tbl_map); 3083 rmem->pg_tbl = NULL; 3084 } 3085 if (rmem->vmem_size && *rmem->vmem) { 3086 vfree(*rmem->vmem); 3087 *rmem->vmem = NULL; 3088 } 3089 } 3090 3091 static int bnxt_alloc_ring(struct bnxt *bp, struct bnxt_ring_mem_info *rmem) 3092 { 3093 struct pci_dev *pdev = bp->pdev; 3094 u64 valid_bit = 0; 3095 int i; 3096 3097 if (rmem->flags & (BNXT_RMEM_VALID_PTE_FLAG | BNXT_RMEM_RING_PTE_FLAG)) 3098 valid_bit = PTU_PTE_VALID; 3099 if ((rmem->nr_pages > 1 || rmem->depth > 0) && !rmem->pg_tbl) { 3100 size_t pg_tbl_size = rmem->nr_pages * 8; 3101 3102 if (rmem->flags & BNXT_RMEM_USE_FULL_PAGE_FLAG) 3103 pg_tbl_size = rmem->page_size; 3104 rmem->pg_tbl = dma_alloc_coherent(&pdev->dev, pg_tbl_size, 3105 &rmem->pg_tbl_map, 3106 GFP_KERNEL); 3107 if (!rmem->pg_tbl) 3108 return -ENOMEM; 3109 } 3110 3111 for (i = 0; i < rmem->nr_pages; i++) { 3112 u64 extra_bits = valid_bit; 3113 3114 rmem->pg_arr[i] = dma_alloc_coherent(&pdev->dev, 3115 rmem->page_size, 3116 &rmem->dma_arr[i], 3117 GFP_KERNEL); 3118 if (!rmem->pg_arr[i]) 3119 return -ENOMEM; 3120 3121 if (rmem->mem_init) 3122 bnxt_init_ctx_mem(rmem->mem_init, rmem->pg_arr[i], 3123 rmem->page_size); 3124 if (rmem->nr_pages > 1 || rmem->depth > 0) { 3125 if (i == rmem->nr_pages - 2 && 3126 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG)) 3127 extra_bits |= PTU_PTE_NEXT_TO_LAST; 3128 else if (i == rmem->nr_pages - 1 && 3129 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG)) 3130 extra_bits |= PTU_PTE_LAST; 3131 rmem->pg_tbl[i] = 3132 cpu_to_le64(rmem->dma_arr[i] | extra_bits); 3133 } 3134 } 3135 3136 if (rmem->vmem_size) { 3137 *rmem->vmem = vzalloc(rmem->vmem_size); 3138 if (!(*rmem->vmem)) 3139 return -ENOMEM; 3140 } 3141 return 0; 3142 } 3143 3144 static void bnxt_free_tpa_info(struct bnxt *bp) 3145 { 3146 int i, j; 3147 3148 for (i = 0; i < bp->rx_nr_rings; i++) { 3149 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 3150 3151 kfree(rxr->rx_tpa_idx_map); 3152 rxr->rx_tpa_idx_map = NULL; 3153 if (rxr->rx_tpa) { 3154 for (j = 0; j < bp->max_tpa; j++) { 3155 kfree(rxr->rx_tpa[j].agg_arr); 3156 rxr->rx_tpa[j].agg_arr = NULL; 3157 } 3158 } 3159 kfree(rxr->rx_tpa); 3160 rxr->rx_tpa = NULL; 3161 } 3162 } 3163 3164 static int bnxt_alloc_tpa_info(struct bnxt *bp) 3165 { 3166 int i, j; 3167 3168 bp->max_tpa = MAX_TPA; 3169 if (bp->flags & BNXT_FLAG_CHIP_P5) { 3170 if (!bp->max_tpa_v2) 3171 return 0; 3172 bp->max_tpa = max_t(u16, bp->max_tpa_v2, MAX_TPA_P5); 3173 } 3174 3175 for (i = 0; i < bp->rx_nr_rings; i++) { 3176 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 3177 struct rx_agg_cmp *agg; 3178 3179 rxr->rx_tpa = kcalloc(bp->max_tpa, sizeof(struct bnxt_tpa_info), 3180 GFP_KERNEL); 3181 if (!rxr->rx_tpa) 3182 return -ENOMEM; 3183 3184 if (!(bp->flags & BNXT_FLAG_CHIP_P5)) 3185 continue; 3186 for (j = 0; j < bp->max_tpa; j++) { 3187 agg = kcalloc(MAX_SKB_FRAGS, sizeof(*agg), GFP_KERNEL); 3188 if (!agg) 3189 return -ENOMEM; 3190 rxr->rx_tpa[j].agg_arr = agg; 3191 } 3192 rxr->rx_tpa_idx_map = kzalloc(sizeof(*rxr->rx_tpa_idx_map), 3193 GFP_KERNEL); 3194 if (!rxr->rx_tpa_idx_map) 3195 return -ENOMEM; 3196 } 3197 return 0; 3198 } 3199 3200 static void bnxt_free_rx_rings(struct bnxt *bp) 3201 { 3202 int i; 3203 3204 if (!bp->rx_ring) 3205 return; 3206 3207 bnxt_free_tpa_info(bp); 3208 for (i = 0; i < bp->rx_nr_rings; i++) { 3209 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 3210 struct bnxt_ring_struct *ring; 3211 3212 if (rxr->xdp_prog) 3213 bpf_prog_put(rxr->xdp_prog); 3214 3215 if (xdp_rxq_info_is_reg(&rxr->xdp_rxq)) 3216 xdp_rxq_info_unreg(&rxr->xdp_rxq); 3217 3218 page_pool_destroy(rxr->page_pool); 3219 rxr->page_pool = NULL; 3220 3221 kfree(rxr->rx_agg_bmap); 3222 rxr->rx_agg_bmap = NULL; 3223 3224 ring = &rxr->rx_ring_struct; 3225 bnxt_free_ring(bp, &ring->ring_mem); 3226 3227 ring = &rxr->rx_agg_ring_struct; 3228 bnxt_free_ring(bp, &ring->ring_mem); 3229 } 3230 } 3231 3232 static int bnxt_alloc_rx_page_pool(struct bnxt *bp, 3233 struct bnxt_rx_ring_info *rxr) 3234 { 3235 struct page_pool_params pp = { 0 }; 3236 3237 pp.pool_size = bp->rx_ring_size; 3238 pp.nid = dev_to_node(&bp->pdev->dev); 3239 pp.napi = &rxr->bnapi->napi; 3240 pp.dev = &bp->pdev->dev; 3241 pp.dma_dir = DMA_BIDIRECTIONAL; 3242 3243 rxr->page_pool = page_pool_create(&pp); 3244 if (IS_ERR(rxr->page_pool)) { 3245 int err = PTR_ERR(rxr->page_pool); 3246 3247 rxr->page_pool = NULL; 3248 return err; 3249 } 3250 return 0; 3251 } 3252 3253 static int bnxt_alloc_rx_rings(struct bnxt *bp) 3254 { 3255 int i, rc = 0, agg_rings = 0; 3256 3257 if (!bp->rx_ring) 3258 return -ENOMEM; 3259 3260 if (bp->flags & BNXT_FLAG_AGG_RINGS) 3261 agg_rings = 1; 3262 3263 for (i = 0; i < bp->rx_nr_rings; i++) { 3264 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 3265 struct bnxt_ring_struct *ring; 3266 3267 ring = &rxr->rx_ring_struct; 3268 3269 rc = bnxt_alloc_rx_page_pool(bp, rxr); 3270 if (rc) 3271 return rc; 3272 3273 rc = xdp_rxq_info_reg(&rxr->xdp_rxq, bp->dev, i, 0); 3274 if (rc < 0) 3275 return rc; 3276 3277 rc = xdp_rxq_info_reg_mem_model(&rxr->xdp_rxq, 3278 MEM_TYPE_PAGE_POOL, 3279 rxr->page_pool); 3280 if (rc) { 3281 xdp_rxq_info_unreg(&rxr->xdp_rxq); 3282 return rc; 3283 } 3284 3285 rc = bnxt_alloc_ring(bp, &ring->ring_mem); 3286 if (rc) 3287 return rc; 3288 3289 ring->grp_idx = i; 3290 if (agg_rings) { 3291 u16 mem_size; 3292 3293 ring = &rxr->rx_agg_ring_struct; 3294 rc = bnxt_alloc_ring(bp, &ring->ring_mem); 3295 if (rc) 3296 return rc; 3297 3298 ring->grp_idx = i; 3299 rxr->rx_agg_bmap_size = bp->rx_agg_ring_mask + 1; 3300 mem_size = rxr->rx_agg_bmap_size / 8; 3301 rxr->rx_agg_bmap = kzalloc(mem_size, GFP_KERNEL); 3302 if (!rxr->rx_agg_bmap) 3303 return -ENOMEM; 3304 } 3305 } 3306 if (bp->flags & BNXT_FLAG_TPA) 3307 rc = bnxt_alloc_tpa_info(bp); 3308 return rc; 3309 } 3310 3311 static void bnxt_free_tx_rings(struct bnxt *bp) 3312 { 3313 int i; 3314 struct pci_dev *pdev = bp->pdev; 3315 3316 if (!bp->tx_ring) 3317 return; 3318 3319 for (i = 0; i < bp->tx_nr_rings; i++) { 3320 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; 3321 struct bnxt_ring_struct *ring; 3322 3323 if (txr->tx_push) { 3324 dma_free_coherent(&pdev->dev, bp->tx_push_size, 3325 txr->tx_push, txr->tx_push_mapping); 3326 txr->tx_push = NULL; 3327 } 3328 3329 ring = &txr->tx_ring_struct; 3330 3331 bnxt_free_ring(bp, &ring->ring_mem); 3332 } 3333 } 3334 3335 static int bnxt_alloc_tx_rings(struct bnxt *bp) 3336 { 3337 int i, j, rc; 3338 struct pci_dev *pdev = bp->pdev; 3339 3340 bp->tx_push_size = 0; 3341 if (bp->tx_push_thresh) { 3342 int push_size; 3343 3344 push_size = L1_CACHE_ALIGN(sizeof(struct tx_push_bd) + 3345 bp->tx_push_thresh); 3346 3347 if (push_size > 256) { 3348 push_size = 0; 3349 bp->tx_push_thresh = 0; 3350 } 3351 3352 bp->tx_push_size = push_size; 3353 } 3354 3355 for (i = 0, j = 0; i < bp->tx_nr_rings; i++) { 3356 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; 3357 struct bnxt_ring_struct *ring; 3358 u8 qidx; 3359 3360 ring = &txr->tx_ring_struct; 3361 3362 rc = bnxt_alloc_ring(bp, &ring->ring_mem); 3363 if (rc) 3364 return rc; 3365 3366 ring->grp_idx = txr->bnapi->index; 3367 if (bp->tx_push_size) { 3368 dma_addr_t mapping; 3369 3370 /* One pre-allocated DMA buffer to backup 3371 * TX push operation 3372 */ 3373 txr->tx_push = dma_alloc_coherent(&pdev->dev, 3374 bp->tx_push_size, 3375 &txr->tx_push_mapping, 3376 GFP_KERNEL); 3377 3378 if (!txr->tx_push) 3379 return -ENOMEM; 3380 3381 mapping = txr->tx_push_mapping + 3382 sizeof(struct tx_push_bd); 3383 txr->data_mapping = cpu_to_le64(mapping); 3384 } 3385 qidx = bp->tc_to_qidx[j]; 3386 ring->queue_id = bp->q_info[qidx].queue_id; 3387 spin_lock_init(&txr->xdp_tx_lock); 3388 if (i < bp->tx_nr_rings_xdp) 3389 continue; 3390 if (i % bp->tx_nr_rings_per_tc == (bp->tx_nr_rings_per_tc - 1)) 3391 j++; 3392 } 3393 return 0; 3394 } 3395 3396 static void bnxt_free_cp_arrays(struct bnxt_cp_ring_info *cpr) 3397 { 3398 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct; 3399 3400 kfree(cpr->cp_desc_ring); 3401 cpr->cp_desc_ring = NULL; 3402 ring->ring_mem.pg_arr = NULL; 3403 kfree(cpr->cp_desc_mapping); 3404 cpr->cp_desc_mapping = NULL; 3405 ring->ring_mem.dma_arr = NULL; 3406 } 3407 3408 static int bnxt_alloc_cp_arrays(struct bnxt_cp_ring_info *cpr, int n) 3409 { 3410 cpr->cp_desc_ring = kcalloc(n, sizeof(*cpr->cp_desc_ring), GFP_KERNEL); 3411 if (!cpr->cp_desc_ring) 3412 return -ENOMEM; 3413 cpr->cp_desc_mapping = kcalloc(n, sizeof(*cpr->cp_desc_mapping), 3414 GFP_KERNEL); 3415 if (!cpr->cp_desc_mapping) 3416 return -ENOMEM; 3417 return 0; 3418 } 3419 3420 static void bnxt_free_all_cp_arrays(struct bnxt *bp) 3421 { 3422 int i; 3423 3424 if (!bp->bnapi) 3425 return; 3426 for (i = 0; i < bp->cp_nr_rings; i++) { 3427 struct bnxt_napi *bnapi = bp->bnapi[i]; 3428 3429 if (!bnapi) 3430 continue; 3431 bnxt_free_cp_arrays(&bnapi->cp_ring); 3432 } 3433 } 3434 3435 static int bnxt_alloc_all_cp_arrays(struct bnxt *bp) 3436 { 3437 int i, n = bp->cp_nr_pages; 3438 3439 for (i = 0; i < bp->cp_nr_rings; i++) { 3440 struct bnxt_napi *bnapi = bp->bnapi[i]; 3441 int rc; 3442 3443 if (!bnapi) 3444 continue; 3445 rc = bnxt_alloc_cp_arrays(&bnapi->cp_ring, n); 3446 if (rc) 3447 return rc; 3448 } 3449 return 0; 3450 } 3451 3452 static void bnxt_free_cp_rings(struct bnxt *bp) 3453 { 3454 int i; 3455 3456 if (!bp->bnapi) 3457 return; 3458 3459 for (i = 0; i < bp->cp_nr_rings; i++) { 3460 struct bnxt_napi *bnapi = bp->bnapi[i]; 3461 struct bnxt_cp_ring_info *cpr; 3462 struct bnxt_ring_struct *ring; 3463 int j; 3464 3465 if (!bnapi) 3466 continue; 3467 3468 cpr = &bnapi->cp_ring; 3469 ring = &cpr->cp_ring_struct; 3470 3471 bnxt_free_ring(bp, &ring->ring_mem); 3472 3473 for (j = 0; j < 2; j++) { 3474 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j]; 3475 3476 if (cpr2) { 3477 ring = &cpr2->cp_ring_struct; 3478 bnxt_free_ring(bp, &ring->ring_mem); 3479 bnxt_free_cp_arrays(cpr2); 3480 kfree(cpr2); 3481 cpr->cp_ring_arr[j] = NULL; 3482 } 3483 } 3484 } 3485 } 3486 3487 static struct bnxt_cp_ring_info *bnxt_alloc_cp_sub_ring(struct bnxt *bp) 3488 { 3489 struct bnxt_ring_mem_info *rmem; 3490 struct bnxt_ring_struct *ring; 3491 struct bnxt_cp_ring_info *cpr; 3492 int rc; 3493 3494 cpr = kzalloc(sizeof(*cpr), GFP_KERNEL); 3495 if (!cpr) 3496 return NULL; 3497 3498 rc = bnxt_alloc_cp_arrays(cpr, bp->cp_nr_pages); 3499 if (rc) { 3500 bnxt_free_cp_arrays(cpr); 3501 kfree(cpr); 3502 return NULL; 3503 } 3504 ring = &cpr->cp_ring_struct; 3505 rmem = &ring->ring_mem; 3506 rmem->nr_pages = bp->cp_nr_pages; 3507 rmem->page_size = HW_CMPD_RING_SIZE; 3508 rmem->pg_arr = (void **)cpr->cp_desc_ring; 3509 rmem->dma_arr = cpr->cp_desc_mapping; 3510 rmem->flags = BNXT_RMEM_RING_PTE_FLAG; 3511 rc = bnxt_alloc_ring(bp, rmem); 3512 if (rc) { 3513 bnxt_free_ring(bp, rmem); 3514 bnxt_free_cp_arrays(cpr); 3515 kfree(cpr); 3516 cpr = NULL; 3517 } 3518 return cpr; 3519 } 3520 3521 static int bnxt_alloc_cp_rings(struct bnxt *bp) 3522 { 3523 bool sh = !!(bp->flags & BNXT_FLAG_SHARED_RINGS); 3524 int i, rc, ulp_base_vec, ulp_msix; 3525 3526 ulp_msix = bnxt_get_ulp_msix_num(bp); 3527 ulp_base_vec = bnxt_get_ulp_msix_base(bp); 3528 for (i = 0; i < bp->cp_nr_rings; i++) { 3529 struct bnxt_napi *bnapi = bp->bnapi[i]; 3530 struct bnxt_cp_ring_info *cpr; 3531 struct bnxt_ring_struct *ring; 3532 3533 if (!bnapi) 3534 continue; 3535 3536 cpr = &bnapi->cp_ring; 3537 cpr->bnapi = bnapi; 3538 ring = &cpr->cp_ring_struct; 3539 3540 rc = bnxt_alloc_ring(bp, &ring->ring_mem); 3541 if (rc) 3542 return rc; 3543 3544 if (ulp_msix && i >= ulp_base_vec) 3545 ring->map_idx = i + ulp_msix; 3546 else 3547 ring->map_idx = i; 3548 3549 if (!(bp->flags & BNXT_FLAG_CHIP_P5)) 3550 continue; 3551 3552 if (i < bp->rx_nr_rings) { 3553 struct bnxt_cp_ring_info *cpr2 = 3554 bnxt_alloc_cp_sub_ring(bp); 3555 3556 cpr->cp_ring_arr[BNXT_RX_HDL] = cpr2; 3557 if (!cpr2) 3558 return -ENOMEM; 3559 cpr2->bnapi = bnapi; 3560 } 3561 if ((sh && i < bp->tx_nr_rings) || 3562 (!sh && i >= bp->rx_nr_rings)) { 3563 struct bnxt_cp_ring_info *cpr2 = 3564 bnxt_alloc_cp_sub_ring(bp); 3565 3566 cpr->cp_ring_arr[BNXT_TX_HDL] = cpr2; 3567 if (!cpr2) 3568 return -ENOMEM; 3569 cpr2->bnapi = bnapi; 3570 } 3571 } 3572 return 0; 3573 } 3574 3575 static void bnxt_init_ring_struct(struct bnxt *bp) 3576 { 3577 int i; 3578 3579 for (i = 0; i < bp->cp_nr_rings; i++) { 3580 struct bnxt_napi *bnapi = bp->bnapi[i]; 3581 struct bnxt_ring_mem_info *rmem; 3582 struct bnxt_cp_ring_info *cpr; 3583 struct bnxt_rx_ring_info *rxr; 3584 struct bnxt_tx_ring_info *txr; 3585 struct bnxt_ring_struct *ring; 3586 3587 if (!bnapi) 3588 continue; 3589 3590 cpr = &bnapi->cp_ring; 3591 ring = &cpr->cp_ring_struct; 3592 rmem = &ring->ring_mem; 3593 rmem->nr_pages = bp->cp_nr_pages; 3594 rmem->page_size = HW_CMPD_RING_SIZE; 3595 rmem->pg_arr = (void **)cpr->cp_desc_ring; 3596 rmem->dma_arr = cpr->cp_desc_mapping; 3597 rmem->vmem_size = 0; 3598 3599 rxr = bnapi->rx_ring; 3600 if (!rxr) 3601 goto skip_rx; 3602 3603 ring = &rxr->rx_ring_struct; 3604 rmem = &ring->ring_mem; 3605 rmem->nr_pages = bp->rx_nr_pages; 3606 rmem->page_size = HW_RXBD_RING_SIZE; 3607 rmem->pg_arr = (void **)rxr->rx_desc_ring; 3608 rmem->dma_arr = rxr->rx_desc_mapping; 3609 rmem->vmem_size = SW_RXBD_RING_SIZE * bp->rx_nr_pages; 3610 rmem->vmem = (void **)&rxr->rx_buf_ring; 3611 3612 ring = &rxr->rx_agg_ring_struct; 3613 rmem = &ring->ring_mem; 3614 rmem->nr_pages = bp->rx_agg_nr_pages; 3615 rmem->page_size = HW_RXBD_RING_SIZE; 3616 rmem->pg_arr = (void **)rxr->rx_agg_desc_ring; 3617 rmem->dma_arr = rxr->rx_agg_desc_mapping; 3618 rmem->vmem_size = SW_RXBD_AGG_RING_SIZE * bp->rx_agg_nr_pages; 3619 rmem->vmem = (void **)&rxr->rx_agg_ring; 3620 3621 skip_rx: 3622 txr = bnapi->tx_ring; 3623 if (!txr) 3624 continue; 3625 3626 ring = &txr->tx_ring_struct; 3627 rmem = &ring->ring_mem; 3628 rmem->nr_pages = bp->tx_nr_pages; 3629 rmem->page_size = HW_RXBD_RING_SIZE; 3630 rmem->pg_arr = (void **)txr->tx_desc_ring; 3631 rmem->dma_arr = txr->tx_desc_mapping; 3632 rmem->vmem_size = SW_TXBD_RING_SIZE * bp->tx_nr_pages; 3633 rmem->vmem = (void **)&txr->tx_buf_ring; 3634 } 3635 } 3636 3637 static void bnxt_init_rxbd_pages(struct bnxt_ring_struct *ring, u32 type) 3638 { 3639 int i; 3640 u32 prod; 3641 struct rx_bd **rx_buf_ring; 3642 3643 rx_buf_ring = (struct rx_bd **)ring->ring_mem.pg_arr; 3644 for (i = 0, prod = 0; i < ring->ring_mem.nr_pages; i++) { 3645 int j; 3646 struct rx_bd *rxbd; 3647 3648 rxbd = rx_buf_ring[i]; 3649 if (!rxbd) 3650 continue; 3651 3652 for (j = 0; j < RX_DESC_CNT; j++, rxbd++, prod++) { 3653 rxbd->rx_bd_len_flags_type = cpu_to_le32(type); 3654 rxbd->rx_bd_opaque = prod; 3655 } 3656 } 3657 } 3658 3659 static int bnxt_alloc_one_rx_ring(struct bnxt *bp, int ring_nr) 3660 { 3661 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[ring_nr]; 3662 struct net_device *dev = bp->dev; 3663 u32 prod; 3664 int i; 3665 3666 prod = rxr->rx_prod; 3667 for (i = 0; i < bp->rx_ring_size; i++) { 3668 if (bnxt_alloc_rx_data(bp, rxr, prod, GFP_KERNEL)) { 3669 netdev_warn(dev, "init'ed rx ring %d with %d/%d skbs only\n", 3670 ring_nr, i, bp->rx_ring_size); 3671 break; 3672 } 3673 prod = NEXT_RX(prod); 3674 } 3675 rxr->rx_prod = prod; 3676 3677 if (!(bp->flags & BNXT_FLAG_AGG_RINGS)) 3678 return 0; 3679 3680 prod = rxr->rx_agg_prod; 3681 for (i = 0; i < bp->rx_agg_ring_size; i++) { 3682 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_KERNEL)) { 3683 netdev_warn(dev, "init'ed rx ring %d with %d/%d pages only\n", 3684 ring_nr, i, bp->rx_ring_size); 3685 break; 3686 } 3687 prod = NEXT_RX_AGG(prod); 3688 } 3689 rxr->rx_agg_prod = prod; 3690 3691 if (rxr->rx_tpa) { 3692 dma_addr_t mapping; 3693 u8 *data; 3694 3695 for (i = 0; i < bp->max_tpa; i++) { 3696 data = __bnxt_alloc_rx_frag(bp, &mapping, GFP_KERNEL); 3697 if (!data) 3698 return -ENOMEM; 3699 3700 rxr->rx_tpa[i].data = data; 3701 rxr->rx_tpa[i].data_ptr = data + bp->rx_offset; 3702 rxr->rx_tpa[i].mapping = mapping; 3703 } 3704 } 3705 return 0; 3706 } 3707 3708 static int bnxt_init_one_rx_ring(struct bnxt *bp, int ring_nr) 3709 { 3710 struct bnxt_rx_ring_info *rxr; 3711 struct bnxt_ring_struct *ring; 3712 u32 type; 3713 3714 type = (bp->rx_buf_use_size << RX_BD_LEN_SHIFT) | 3715 RX_BD_TYPE_RX_PACKET_BD | RX_BD_FLAGS_EOP; 3716 3717 if (NET_IP_ALIGN == 2) 3718 type |= RX_BD_FLAGS_SOP; 3719 3720 rxr = &bp->rx_ring[ring_nr]; 3721 ring = &rxr->rx_ring_struct; 3722 bnxt_init_rxbd_pages(ring, type); 3723 3724 if (BNXT_RX_PAGE_MODE(bp) && bp->xdp_prog) { 3725 bpf_prog_add(bp->xdp_prog, 1); 3726 rxr->xdp_prog = bp->xdp_prog; 3727 } 3728 ring->fw_ring_id = INVALID_HW_RING_ID; 3729 3730 ring = &rxr->rx_agg_ring_struct; 3731 ring->fw_ring_id = INVALID_HW_RING_ID; 3732 3733 if ((bp->flags & BNXT_FLAG_AGG_RINGS)) { 3734 type = ((u32)BNXT_RX_PAGE_SIZE << RX_BD_LEN_SHIFT) | 3735 RX_BD_TYPE_RX_AGG_BD | RX_BD_FLAGS_SOP; 3736 3737 bnxt_init_rxbd_pages(ring, type); 3738 } 3739 3740 return bnxt_alloc_one_rx_ring(bp, ring_nr); 3741 } 3742 3743 static void bnxt_init_cp_rings(struct bnxt *bp) 3744 { 3745 int i, j; 3746 3747 for (i = 0; i < bp->cp_nr_rings; i++) { 3748 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring; 3749 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct; 3750 3751 ring->fw_ring_id = INVALID_HW_RING_ID; 3752 cpr->rx_ring_coal.coal_ticks = bp->rx_coal.coal_ticks; 3753 cpr->rx_ring_coal.coal_bufs = bp->rx_coal.coal_bufs; 3754 for (j = 0; j < 2; j++) { 3755 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j]; 3756 3757 if (!cpr2) 3758 continue; 3759 3760 ring = &cpr2->cp_ring_struct; 3761 ring->fw_ring_id = INVALID_HW_RING_ID; 3762 cpr2->rx_ring_coal.coal_ticks = bp->rx_coal.coal_ticks; 3763 cpr2->rx_ring_coal.coal_bufs = bp->rx_coal.coal_bufs; 3764 } 3765 } 3766 } 3767 3768 static int bnxt_init_rx_rings(struct bnxt *bp) 3769 { 3770 int i, rc = 0; 3771 3772 if (BNXT_RX_PAGE_MODE(bp)) { 3773 bp->rx_offset = NET_IP_ALIGN + XDP_PACKET_HEADROOM; 3774 bp->rx_dma_offset = XDP_PACKET_HEADROOM; 3775 } else { 3776 bp->rx_offset = BNXT_RX_OFFSET; 3777 bp->rx_dma_offset = BNXT_RX_DMA_OFFSET; 3778 } 3779 3780 for (i = 0; i < bp->rx_nr_rings; i++) { 3781 rc = bnxt_init_one_rx_ring(bp, i); 3782 if (rc) 3783 break; 3784 } 3785 3786 return rc; 3787 } 3788 3789 static int bnxt_init_tx_rings(struct bnxt *bp) 3790 { 3791 u16 i; 3792 3793 bp->tx_wake_thresh = max_t(int, bp->tx_ring_size / 2, 3794 BNXT_MIN_TX_DESC_CNT); 3795 3796 for (i = 0; i < bp->tx_nr_rings; i++) { 3797 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; 3798 struct bnxt_ring_struct *ring = &txr->tx_ring_struct; 3799 3800 ring->fw_ring_id = INVALID_HW_RING_ID; 3801 } 3802 3803 return 0; 3804 } 3805 3806 static void bnxt_free_ring_grps(struct bnxt *bp) 3807 { 3808 kfree(bp->grp_info); 3809 bp->grp_info = NULL; 3810 } 3811 3812 static int bnxt_init_ring_grps(struct bnxt *bp, bool irq_re_init) 3813 { 3814 int i; 3815 3816 if (irq_re_init) { 3817 bp->grp_info = kcalloc(bp->cp_nr_rings, 3818 sizeof(struct bnxt_ring_grp_info), 3819 GFP_KERNEL); 3820 if (!bp->grp_info) 3821 return -ENOMEM; 3822 } 3823 for (i = 0; i < bp->cp_nr_rings; i++) { 3824 if (irq_re_init) 3825 bp->grp_info[i].fw_stats_ctx = INVALID_HW_RING_ID; 3826 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID; 3827 bp->grp_info[i].rx_fw_ring_id = INVALID_HW_RING_ID; 3828 bp->grp_info[i].agg_fw_ring_id = INVALID_HW_RING_ID; 3829 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID; 3830 } 3831 return 0; 3832 } 3833 3834 static void bnxt_free_vnics(struct bnxt *bp) 3835 { 3836 kfree(bp->vnic_info); 3837 bp->vnic_info = NULL; 3838 bp->nr_vnics = 0; 3839 } 3840 3841 static int bnxt_alloc_vnics(struct bnxt *bp) 3842 { 3843 int num_vnics = 1; 3844 3845 #ifdef CONFIG_RFS_ACCEL 3846 if ((bp->flags & (BNXT_FLAG_RFS | BNXT_FLAG_CHIP_P5)) == BNXT_FLAG_RFS) 3847 num_vnics += bp->rx_nr_rings; 3848 #endif 3849 3850 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 3851 num_vnics++; 3852 3853 bp->vnic_info = kcalloc(num_vnics, sizeof(struct bnxt_vnic_info), 3854 GFP_KERNEL); 3855 if (!bp->vnic_info) 3856 return -ENOMEM; 3857 3858 bp->nr_vnics = num_vnics; 3859 return 0; 3860 } 3861 3862 static void bnxt_init_vnics(struct bnxt *bp) 3863 { 3864 int i; 3865 3866 for (i = 0; i < bp->nr_vnics; i++) { 3867 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 3868 int j; 3869 3870 vnic->fw_vnic_id = INVALID_HW_RING_ID; 3871 for (j = 0; j < BNXT_MAX_CTX_PER_VNIC; j++) 3872 vnic->fw_rss_cos_lb_ctx[j] = INVALID_HW_RING_ID; 3873 3874 vnic->fw_l2_ctx_id = INVALID_HW_RING_ID; 3875 3876 if (bp->vnic_info[i].rss_hash_key) { 3877 if (i == 0) 3878 get_random_bytes(vnic->rss_hash_key, 3879 HW_HASH_KEY_SIZE); 3880 else 3881 memcpy(vnic->rss_hash_key, 3882 bp->vnic_info[0].rss_hash_key, 3883 HW_HASH_KEY_SIZE); 3884 } 3885 } 3886 } 3887 3888 static int bnxt_calc_nr_ring_pages(u32 ring_size, int desc_per_pg) 3889 { 3890 int pages; 3891 3892 pages = ring_size / desc_per_pg; 3893 3894 if (!pages) 3895 return 1; 3896 3897 pages++; 3898 3899 while (pages & (pages - 1)) 3900 pages++; 3901 3902 return pages; 3903 } 3904 3905 void bnxt_set_tpa_flags(struct bnxt *bp) 3906 { 3907 bp->flags &= ~BNXT_FLAG_TPA; 3908 if (bp->flags & BNXT_FLAG_NO_AGG_RINGS) 3909 return; 3910 if (bp->dev->features & NETIF_F_LRO) 3911 bp->flags |= BNXT_FLAG_LRO; 3912 else if (bp->dev->features & NETIF_F_GRO_HW) 3913 bp->flags |= BNXT_FLAG_GRO; 3914 } 3915 3916 /* bp->rx_ring_size, bp->tx_ring_size, dev->mtu, BNXT_FLAG_{G|L}RO flags must 3917 * be set on entry. 3918 */ 3919 void bnxt_set_ring_params(struct bnxt *bp) 3920 { 3921 u32 ring_size, rx_size, rx_space, max_rx_cmpl; 3922 u32 agg_factor = 0, agg_ring_size = 0; 3923 3924 /* 8 for CRC and VLAN */ 3925 rx_size = SKB_DATA_ALIGN(bp->dev->mtu + ETH_HLEN + NET_IP_ALIGN + 8); 3926 3927 rx_space = rx_size + ALIGN(max(NET_SKB_PAD, XDP_PACKET_HEADROOM), 8) + 3928 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 3929 3930 bp->rx_copy_thresh = BNXT_RX_COPY_THRESH; 3931 ring_size = bp->rx_ring_size; 3932 bp->rx_agg_ring_size = 0; 3933 bp->rx_agg_nr_pages = 0; 3934 3935 if (bp->flags & BNXT_FLAG_TPA) 3936 agg_factor = min_t(u32, 4, 65536 / BNXT_RX_PAGE_SIZE); 3937 3938 bp->flags &= ~BNXT_FLAG_JUMBO; 3939 if (rx_space > PAGE_SIZE && !(bp->flags & BNXT_FLAG_NO_AGG_RINGS)) { 3940 u32 jumbo_factor; 3941 3942 bp->flags |= BNXT_FLAG_JUMBO; 3943 jumbo_factor = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT; 3944 if (jumbo_factor > agg_factor) 3945 agg_factor = jumbo_factor; 3946 } 3947 if (agg_factor) { 3948 if (ring_size > BNXT_MAX_RX_DESC_CNT_JUM_ENA) { 3949 ring_size = BNXT_MAX_RX_DESC_CNT_JUM_ENA; 3950 netdev_warn(bp->dev, "RX ring size reduced from %d to %d because the jumbo ring is now enabled\n", 3951 bp->rx_ring_size, ring_size); 3952 bp->rx_ring_size = ring_size; 3953 } 3954 agg_ring_size = ring_size * agg_factor; 3955 3956 bp->rx_agg_nr_pages = bnxt_calc_nr_ring_pages(agg_ring_size, 3957 RX_DESC_CNT); 3958 if (bp->rx_agg_nr_pages > MAX_RX_AGG_PAGES) { 3959 u32 tmp = agg_ring_size; 3960 3961 bp->rx_agg_nr_pages = MAX_RX_AGG_PAGES; 3962 agg_ring_size = MAX_RX_AGG_PAGES * RX_DESC_CNT - 1; 3963 netdev_warn(bp->dev, "rx agg ring size %d reduced to %d.\n", 3964 tmp, agg_ring_size); 3965 } 3966 bp->rx_agg_ring_size = agg_ring_size; 3967 bp->rx_agg_ring_mask = (bp->rx_agg_nr_pages * RX_DESC_CNT) - 1; 3968 3969 if (BNXT_RX_PAGE_MODE(bp)) { 3970 rx_space = PAGE_SIZE; 3971 rx_size = PAGE_SIZE - 3972 ALIGN(max(NET_SKB_PAD, XDP_PACKET_HEADROOM), 8) - 3973 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 3974 } else { 3975 rx_size = SKB_DATA_ALIGN(BNXT_RX_COPY_THRESH + NET_IP_ALIGN); 3976 rx_space = rx_size + NET_SKB_PAD + 3977 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 3978 } 3979 } 3980 3981 bp->rx_buf_use_size = rx_size; 3982 bp->rx_buf_size = rx_space; 3983 3984 bp->rx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, RX_DESC_CNT); 3985 bp->rx_ring_mask = (bp->rx_nr_pages * RX_DESC_CNT) - 1; 3986 3987 ring_size = bp->tx_ring_size; 3988 bp->tx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, TX_DESC_CNT); 3989 bp->tx_ring_mask = (bp->tx_nr_pages * TX_DESC_CNT) - 1; 3990 3991 max_rx_cmpl = bp->rx_ring_size; 3992 /* MAX TPA needs to be added because TPA_START completions are 3993 * immediately recycled, so the TPA completions are not bound by 3994 * the RX ring size. 3995 */ 3996 if (bp->flags & BNXT_FLAG_TPA) 3997 max_rx_cmpl += bp->max_tpa; 3998 /* RX and TPA completions are 32-byte, all others are 16-byte */ 3999 ring_size = max_rx_cmpl * 2 + agg_ring_size + bp->tx_ring_size; 4000 bp->cp_ring_size = ring_size; 4001 4002 bp->cp_nr_pages = bnxt_calc_nr_ring_pages(ring_size, CP_DESC_CNT); 4003 if (bp->cp_nr_pages > MAX_CP_PAGES) { 4004 bp->cp_nr_pages = MAX_CP_PAGES; 4005 bp->cp_ring_size = MAX_CP_PAGES * CP_DESC_CNT - 1; 4006 netdev_warn(bp->dev, "completion ring size %d reduced to %d.\n", 4007 ring_size, bp->cp_ring_size); 4008 } 4009 bp->cp_bit = bp->cp_nr_pages * CP_DESC_CNT; 4010 bp->cp_ring_mask = bp->cp_bit - 1; 4011 } 4012 4013 /* Changing allocation mode of RX rings. 4014 * TODO: Update when extending xdp_rxq_info to support allocation modes. 4015 */ 4016 int bnxt_set_rx_skb_mode(struct bnxt *bp, bool page_mode) 4017 { 4018 if (page_mode) { 4019 bp->flags &= ~BNXT_FLAG_AGG_RINGS; 4020 bp->flags |= BNXT_FLAG_RX_PAGE_MODE; 4021 4022 if (bp->dev->mtu > BNXT_MAX_PAGE_MODE_MTU) { 4023 bp->flags |= BNXT_FLAG_JUMBO; 4024 bp->rx_skb_func = bnxt_rx_multi_page_skb; 4025 bp->dev->max_mtu = 4026 min_t(u16, bp->max_mtu, BNXT_MAX_MTU); 4027 } else { 4028 bp->flags |= BNXT_FLAG_NO_AGG_RINGS; 4029 bp->rx_skb_func = bnxt_rx_page_skb; 4030 bp->dev->max_mtu = 4031 min_t(u16, bp->max_mtu, BNXT_MAX_PAGE_MODE_MTU); 4032 } 4033 bp->rx_dir = DMA_BIDIRECTIONAL; 4034 /* Disable LRO or GRO_HW */ 4035 netdev_update_features(bp->dev); 4036 } else { 4037 bp->dev->max_mtu = bp->max_mtu; 4038 bp->flags &= ~BNXT_FLAG_RX_PAGE_MODE; 4039 bp->rx_dir = DMA_FROM_DEVICE; 4040 bp->rx_skb_func = bnxt_rx_skb; 4041 } 4042 return 0; 4043 } 4044 4045 static void bnxt_free_vnic_attributes(struct bnxt *bp) 4046 { 4047 int i; 4048 struct bnxt_vnic_info *vnic; 4049 struct pci_dev *pdev = bp->pdev; 4050 4051 if (!bp->vnic_info) 4052 return; 4053 4054 for (i = 0; i < bp->nr_vnics; i++) { 4055 vnic = &bp->vnic_info[i]; 4056 4057 kfree(vnic->fw_grp_ids); 4058 vnic->fw_grp_ids = NULL; 4059 4060 kfree(vnic->uc_list); 4061 vnic->uc_list = NULL; 4062 4063 if (vnic->mc_list) { 4064 dma_free_coherent(&pdev->dev, vnic->mc_list_size, 4065 vnic->mc_list, vnic->mc_list_mapping); 4066 vnic->mc_list = NULL; 4067 } 4068 4069 if (vnic->rss_table) { 4070 dma_free_coherent(&pdev->dev, vnic->rss_table_size, 4071 vnic->rss_table, 4072 vnic->rss_table_dma_addr); 4073 vnic->rss_table = NULL; 4074 } 4075 4076 vnic->rss_hash_key = NULL; 4077 vnic->flags = 0; 4078 } 4079 } 4080 4081 static int bnxt_alloc_vnic_attributes(struct bnxt *bp) 4082 { 4083 int i, rc = 0, size; 4084 struct bnxt_vnic_info *vnic; 4085 struct pci_dev *pdev = bp->pdev; 4086 int max_rings; 4087 4088 for (i = 0; i < bp->nr_vnics; i++) { 4089 vnic = &bp->vnic_info[i]; 4090 4091 if (vnic->flags & BNXT_VNIC_UCAST_FLAG) { 4092 int mem_size = (BNXT_MAX_UC_ADDRS - 1) * ETH_ALEN; 4093 4094 if (mem_size > 0) { 4095 vnic->uc_list = kmalloc(mem_size, GFP_KERNEL); 4096 if (!vnic->uc_list) { 4097 rc = -ENOMEM; 4098 goto out; 4099 } 4100 } 4101 } 4102 4103 if (vnic->flags & BNXT_VNIC_MCAST_FLAG) { 4104 vnic->mc_list_size = BNXT_MAX_MC_ADDRS * ETH_ALEN; 4105 vnic->mc_list = 4106 dma_alloc_coherent(&pdev->dev, 4107 vnic->mc_list_size, 4108 &vnic->mc_list_mapping, 4109 GFP_KERNEL); 4110 if (!vnic->mc_list) { 4111 rc = -ENOMEM; 4112 goto out; 4113 } 4114 } 4115 4116 if (bp->flags & BNXT_FLAG_CHIP_P5) 4117 goto vnic_skip_grps; 4118 4119 if (vnic->flags & BNXT_VNIC_RSS_FLAG) 4120 max_rings = bp->rx_nr_rings; 4121 else 4122 max_rings = 1; 4123 4124 vnic->fw_grp_ids = kcalloc(max_rings, sizeof(u16), GFP_KERNEL); 4125 if (!vnic->fw_grp_ids) { 4126 rc = -ENOMEM; 4127 goto out; 4128 } 4129 vnic_skip_grps: 4130 if ((bp->flags & BNXT_FLAG_NEW_RSS_CAP) && 4131 !(vnic->flags & BNXT_VNIC_RSS_FLAG)) 4132 continue; 4133 4134 /* Allocate rss table and hash key */ 4135 size = L1_CACHE_ALIGN(HW_HASH_INDEX_SIZE * sizeof(u16)); 4136 if (bp->flags & BNXT_FLAG_CHIP_P5) 4137 size = L1_CACHE_ALIGN(BNXT_MAX_RSS_TABLE_SIZE_P5); 4138 4139 vnic->rss_table_size = size + HW_HASH_KEY_SIZE; 4140 vnic->rss_table = dma_alloc_coherent(&pdev->dev, 4141 vnic->rss_table_size, 4142 &vnic->rss_table_dma_addr, 4143 GFP_KERNEL); 4144 if (!vnic->rss_table) { 4145 rc = -ENOMEM; 4146 goto out; 4147 } 4148 4149 vnic->rss_hash_key = ((void *)vnic->rss_table) + size; 4150 vnic->rss_hash_key_dma_addr = vnic->rss_table_dma_addr + size; 4151 } 4152 return 0; 4153 4154 out: 4155 return rc; 4156 } 4157 4158 static void bnxt_free_hwrm_resources(struct bnxt *bp) 4159 { 4160 struct bnxt_hwrm_wait_token *token; 4161 4162 dma_pool_destroy(bp->hwrm_dma_pool); 4163 bp->hwrm_dma_pool = NULL; 4164 4165 rcu_read_lock(); 4166 hlist_for_each_entry_rcu(token, &bp->hwrm_pending_list, node) 4167 WRITE_ONCE(token->state, BNXT_HWRM_CANCELLED); 4168 rcu_read_unlock(); 4169 } 4170 4171 static int bnxt_alloc_hwrm_resources(struct bnxt *bp) 4172 { 4173 bp->hwrm_dma_pool = dma_pool_create("bnxt_hwrm", &bp->pdev->dev, 4174 BNXT_HWRM_DMA_SIZE, 4175 BNXT_HWRM_DMA_ALIGN, 0); 4176 if (!bp->hwrm_dma_pool) 4177 return -ENOMEM; 4178 4179 INIT_HLIST_HEAD(&bp->hwrm_pending_list); 4180 4181 return 0; 4182 } 4183 4184 static void bnxt_free_stats_mem(struct bnxt *bp, struct bnxt_stats_mem *stats) 4185 { 4186 kfree(stats->hw_masks); 4187 stats->hw_masks = NULL; 4188 kfree(stats->sw_stats); 4189 stats->sw_stats = NULL; 4190 if (stats->hw_stats) { 4191 dma_free_coherent(&bp->pdev->dev, stats->len, stats->hw_stats, 4192 stats->hw_stats_map); 4193 stats->hw_stats = NULL; 4194 } 4195 } 4196 4197 static int bnxt_alloc_stats_mem(struct bnxt *bp, struct bnxt_stats_mem *stats, 4198 bool alloc_masks) 4199 { 4200 stats->hw_stats = dma_alloc_coherent(&bp->pdev->dev, stats->len, 4201 &stats->hw_stats_map, GFP_KERNEL); 4202 if (!stats->hw_stats) 4203 return -ENOMEM; 4204 4205 stats->sw_stats = kzalloc(stats->len, GFP_KERNEL); 4206 if (!stats->sw_stats) 4207 goto stats_mem_err; 4208 4209 if (alloc_masks) { 4210 stats->hw_masks = kzalloc(stats->len, GFP_KERNEL); 4211 if (!stats->hw_masks) 4212 goto stats_mem_err; 4213 } 4214 return 0; 4215 4216 stats_mem_err: 4217 bnxt_free_stats_mem(bp, stats); 4218 return -ENOMEM; 4219 } 4220 4221 static void bnxt_fill_masks(u64 *mask_arr, u64 mask, int count) 4222 { 4223 int i; 4224 4225 for (i = 0; i < count; i++) 4226 mask_arr[i] = mask; 4227 } 4228 4229 static void bnxt_copy_hw_masks(u64 *mask_arr, __le64 *hw_mask_arr, int count) 4230 { 4231 int i; 4232 4233 for (i = 0; i < count; i++) 4234 mask_arr[i] = le64_to_cpu(hw_mask_arr[i]); 4235 } 4236 4237 static int bnxt_hwrm_func_qstat_ext(struct bnxt *bp, 4238 struct bnxt_stats_mem *stats) 4239 { 4240 struct hwrm_func_qstats_ext_output *resp; 4241 struct hwrm_func_qstats_ext_input *req; 4242 __le64 *hw_masks; 4243 int rc; 4244 4245 if (!(bp->fw_cap & BNXT_FW_CAP_EXT_HW_STATS_SUPPORTED) || 4246 !(bp->flags & BNXT_FLAG_CHIP_P5)) 4247 return -EOPNOTSUPP; 4248 4249 rc = hwrm_req_init(bp, req, HWRM_FUNC_QSTATS_EXT); 4250 if (rc) 4251 return rc; 4252 4253 req->fid = cpu_to_le16(0xffff); 4254 req->flags = FUNC_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK; 4255 4256 resp = hwrm_req_hold(bp, req); 4257 rc = hwrm_req_send(bp, req); 4258 if (!rc) { 4259 hw_masks = &resp->rx_ucast_pkts; 4260 bnxt_copy_hw_masks(stats->hw_masks, hw_masks, stats->len / 8); 4261 } 4262 hwrm_req_drop(bp, req); 4263 return rc; 4264 } 4265 4266 static int bnxt_hwrm_port_qstats(struct bnxt *bp, u8 flags); 4267 static int bnxt_hwrm_port_qstats_ext(struct bnxt *bp, u8 flags); 4268 4269 static void bnxt_init_stats(struct bnxt *bp) 4270 { 4271 struct bnxt_napi *bnapi = bp->bnapi[0]; 4272 struct bnxt_cp_ring_info *cpr; 4273 struct bnxt_stats_mem *stats; 4274 __le64 *rx_stats, *tx_stats; 4275 int rc, rx_count, tx_count; 4276 u64 *rx_masks, *tx_masks; 4277 u64 mask; 4278 u8 flags; 4279 4280 cpr = &bnapi->cp_ring; 4281 stats = &cpr->stats; 4282 rc = bnxt_hwrm_func_qstat_ext(bp, stats); 4283 if (rc) { 4284 if (bp->flags & BNXT_FLAG_CHIP_P5) 4285 mask = (1ULL << 48) - 1; 4286 else 4287 mask = -1ULL; 4288 bnxt_fill_masks(stats->hw_masks, mask, stats->len / 8); 4289 } 4290 if (bp->flags & BNXT_FLAG_PORT_STATS) { 4291 stats = &bp->port_stats; 4292 rx_stats = stats->hw_stats; 4293 rx_masks = stats->hw_masks; 4294 rx_count = sizeof(struct rx_port_stats) / 8; 4295 tx_stats = rx_stats + BNXT_TX_PORT_STATS_BYTE_OFFSET / 8; 4296 tx_masks = rx_masks + BNXT_TX_PORT_STATS_BYTE_OFFSET / 8; 4297 tx_count = sizeof(struct tx_port_stats) / 8; 4298 4299 flags = PORT_QSTATS_REQ_FLAGS_COUNTER_MASK; 4300 rc = bnxt_hwrm_port_qstats(bp, flags); 4301 if (rc) { 4302 mask = (1ULL << 40) - 1; 4303 4304 bnxt_fill_masks(rx_masks, mask, rx_count); 4305 bnxt_fill_masks(tx_masks, mask, tx_count); 4306 } else { 4307 bnxt_copy_hw_masks(rx_masks, rx_stats, rx_count); 4308 bnxt_copy_hw_masks(tx_masks, tx_stats, tx_count); 4309 bnxt_hwrm_port_qstats(bp, 0); 4310 } 4311 } 4312 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) { 4313 stats = &bp->rx_port_stats_ext; 4314 rx_stats = stats->hw_stats; 4315 rx_masks = stats->hw_masks; 4316 rx_count = sizeof(struct rx_port_stats_ext) / 8; 4317 stats = &bp->tx_port_stats_ext; 4318 tx_stats = stats->hw_stats; 4319 tx_masks = stats->hw_masks; 4320 tx_count = sizeof(struct tx_port_stats_ext) / 8; 4321 4322 flags = PORT_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK; 4323 rc = bnxt_hwrm_port_qstats_ext(bp, flags); 4324 if (rc) { 4325 mask = (1ULL << 40) - 1; 4326 4327 bnxt_fill_masks(rx_masks, mask, rx_count); 4328 if (tx_stats) 4329 bnxt_fill_masks(tx_masks, mask, tx_count); 4330 } else { 4331 bnxt_copy_hw_masks(rx_masks, rx_stats, rx_count); 4332 if (tx_stats) 4333 bnxt_copy_hw_masks(tx_masks, tx_stats, 4334 tx_count); 4335 bnxt_hwrm_port_qstats_ext(bp, 0); 4336 } 4337 } 4338 } 4339 4340 static void bnxt_free_port_stats(struct bnxt *bp) 4341 { 4342 bp->flags &= ~BNXT_FLAG_PORT_STATS; 4343 bp->flags &= ~BNXT_FLAG_PORT_STATS_EXT; 4344 4345 bnxt_free_stats_mem(bp, &bp->port_stats); 4346 bnxt_free_stats_mem(bp, &bp->rx_port_stats_ext); 4347 bnxt_free_stats_mem(bp, &bp->tx_port_stats_ext); 4348 } 4349 4350 static void bnxt_free_ring_stats(struct bnxt *bp) 4351 { 4352 int i; 4353 4354 if (!bp->bnapi) 4355 return; 4356 4357 for (i = 0; i < bp->cp_nr_rings; i++) { 4358 struct bnxt_napi *bnapi = bp->bnapi[i]; 4359 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 4360 4361 bnxt_free_stats_mem(bp, &cpr->stats); 4362 } 4363 } 4364 4365 static int bnxt_alloc_stats(struct bnxt *bp) 4366 { 4367 u32 size, i; 4368 int rc; 4369 4370 size = bp->hw_ring_stats_size; 4371 4372 for (i = 0; i < bp->cp_nr_rings; i++) { 4373 struct bnxt_napi *bnapi = bp->bnapi[i]; 4374 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 4375 4376 cpr->stats.len = size; 4377 rc = bnxt_alloc_stats_mem(bp, &cpr->stats, !i); 4378 if (rc) 4379 return rc; 4380 4381 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID; 4382 } 4383 4384 if (BNXT_VF(bp) || bp->chip_num == CHIP_NUM_58700) 4385 return 0; 4386 4387 if (bp->port_stats.hw_stats) 4388 goto alloc_ext_stats; 4389 4390 bp->port_stats.len = BNXT_PORT_STATS_SIZE; 4391 rc = bnxt_alloc_stats_mem(bp, &bp->port_stats, true); 4392 if (rc) 4393 return rc; 4394 4395 bp->flags |= BNXT_FLAG_PORT_STATS; 4396 4397 alloc_ext_stats: 4398 /* Display extended statistics only if FW supports it */ 4399 if (bp->hwrm_spec_code < 0x10804 || bp->hwrm_spec_code == 0x10900) 4400 if (!(bp->fw_cap & BNXT_FW_CAP_EXT_STATS_SUPPORTED)) 4401 return 0; 4402 4403 if (bp->rx_port_stats_ext.hw_stats) 4404 goto alloc_tx_ext_stats; 4405 4406 bp->rx_port_stats_ext.len = sizeof(struct rx_port_stats_ext); 4407 rc = bnxt_alloc_stats_mem(bp, &bp->rx_port_stats_ext, true); 4408 /* Extended stats are optional */ 4409 if (rc) 4410 return 0; 4411 4412 alloc_tx_ext_stats: 4413 if (bp->tx_port_stats_ext.hw_stats) 4414 return 0; 4415 4416 if (bp->hwrm_spec_code >= 0x10902 || 4417 (bp->fw_cap & BNXT_FW_CAP_EXT_STATS_SUPPORTED)) { 4418 bp->tx_port_stats_ext.len = sizeof(struct tx_port_stats_ext); 4419 rc = bnxt_alloc_stats_mem(bp, &bp->tx_port_stats_ext, true); 4420 /* Extended stats are optional */ 4421 if (rc) 4422 return 0; 4423 } 4424 bp->flags |= BNXT_FLAG_PORT_STATS_EXT; 4425 return 0; 4426 } 4427 4428 static void bnxt_clear_ring_indices(struct bnxt *bp) 4429 { 4430 int i; 4431 4432 if (!bp->bnapi) 4433 return; 4434 4435 for (i = 0; i < bp->cp_nr_rings; i++) { 4436 struct bnxt_napi *bnapi = bp->bnapi[i]; 4437 struct bnxt_cp_ring_info *cpr; 4438 struct bnxt_rx_ring_info *rxr; 4439 struct bnxt_tx_ring_info *txr; 4440 4441 if (!bnapi) 4442 continue; 4443 4444 cpr = &bnapi->cp_ring; 4445 cpr->cp_raw_cons = 0; 4446 4447 txr = bnapi->tx_ring; 4448 if (txr) { 4449 txr->tx_prod = 0; 4450 txr->tx_cons = 0; 4451 } 4452 4453 rxr = bnapi->rx_ring; 4454 if (rxr) { 4455 rxr->rx_prod = 0; 4456 rxr->rx_agg_prod = 0; 4457 rxr->rx_sw_agg_prod = 0; 4458 rxr->rx_next_cons = 0; 4459 } 4460 } 4461 } 4462 4463 static void bnxt_free_ntp_fltrs(struct bnxt *bp, bool irq_reinit) 4464 { 4465 #ifdef CONFIG_RFS_ACCEL 4466 int i; 4467 4468 /* Under rtnl_lock and all our NAPIs have been disabled. It's 4469 * safe to delete the hash table. 4470 */ 4471 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) { 4472 struct hlist_head *head; 4473 struct hlist_node *tmp; 4474 struct bnxt_ntuple_filter *fltr; 4475 4476 head = &bp->ntp_fltr_hash_tbl[i]; 4477 hlist_for_each_entry_safe(fltr, tmp, head, hash) { 4478 hlist_del(&fltr->hash); 4479 kfree(fltr); 4480 } 4481 } 4482 if (irq_reinit) { 4483 bitmap_free(bp->ntp_fltr_bmap); 4484 bp->ntp_fltr_bmap = NULL; 4485 } 4486 bp->ntp_fltr_count = 0; 4487 #endif 4488 } 4489 4490 static int bnxt_alloc_ntp_fltrs(struct bnxt *bp) 4491 { 4492 #ifdef CONFIG_RFS_ACCEL 4493 int i, rc = 0; 4494 4495 if (!(bp->flags & BNXT_FLAG_RFS)) 4496 return 0; 4497 4498 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) 4499 INIT_HLIST_HEAD(&bp->ntp_fltr_hash_tbl[i]); 4500 4501 bp->ntp_fltr_count = 0; 4502 bp->ntp_fltr_bmap = bitmap_zalloc(BNXT_NTP_FLTR_MAX_FLTR, GFP_KERNEL); 4503 4504 if (!bp->ntp_fltr_bmap) 4505 rc = -ENOMEM; 4506 4507 return rc; 4508 #else 4509 return 0; 4510 #endif 4511 } 4512 4513 static void bnxt_free_mem(struct bnxt *bp, bool irq_re_init) 4514 { 4515 bnxt_free_vnic_attributes(bp); 4516 bnxt_free_tx_rings(bp); 4517 bnxt_free_rx_rings(bp); 4518 bnxt_free_cp_rings(bp); 4519 bnxt_free_all_cp_arrays(bp); 4520 bnxt_free_ntp_fltrs(bp, irq_re_init); 4521 if (irq_re_init) { 4522 bnxt_free_ring_stats(bp); 4523 if (!(bp->phy_flags & BNXT_PHY_FL_PORT_STATS_NO_RESET) || 4524 test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) 4525 bnxt_free_port_stats(bp); 4526 bnxt_free_ring_grps(bp); 4527 bnxt_free_vnics(bp); 4528 kfree(bp->tx_ring_map); 4529 bp->tx_ring_map = NULL; 4530 kfree(bp->tx_ring); 4531 bp->tx_ring = NULL; 4532 kfree(bp->rx_ring); 4533 bp->rx_ring = NULL; 4534 kfree(bp->bnapi); 4535 bp->bnapi = NULL; 4536 } else { 4537 bnxt_clear_ring_indices(bp); 4538 } 4539 } 4540 4541 static int bnxt_alloc_mem(struct bnxt *bp, bool irq_re_init) 4542 { 4543 int i, j, rc, size, arr_size; 4544 void *bnapi; 4545 4546 if (irq_re_init) { 4547 /* Allocate bnapi mem pointer array and mem block for 4548 * all queues 4549 */ 4550 arr_size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi *) * 4551 bp->cp_nr_rings); 4552 size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi)); 4553 bnapi = kzalloc(arr_size + size * bp->cp_nr_rings, GFP_KERNEL); 4554 if (!bnapi) 4555 return -ENOMEM; 4556 4557 bp->bnapi = bnapi; 4558 bnapi += arr_size; 4559 for (i = 0; i < bp->cp_nr_rings; i++, bnapi += size) { 4560 bp->bnapi[i] = bnapi; 4561 bp->bnapi[i]->index = i; 4562 bp->bnapi[i]->bp = bp; 4563 if (bp->flags & BNXT_FLAG_CHIP_P5) { 4564 struct bnxt_cp_ring_info *cpr = 4565 &bp->bnapi[i]->cp_ring; 4566 4567 cpr->cp_ring_struct.ring_mem.flags = 4568 BNXT_RMEM_RING_PTE_FLAG; 4569 } 4570 } 4571 4572 bp->rx_ring = kcalloc(bp->rx_nr_rings, 4573 sizeof(struct bnxt_rx_ring_info), 4574 GFP_KERNEL); 4575 if (!bp->rx_ring) 4576 return -ENOMEM; 4577 4578 for (i = 0; i < bp->rx_nr_rings; i++) { 4579 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 4580 4581 if (bp->flags & BNXT_FLAG_CHIP_P5) { 4582 rxr->rx_ring_struct.ring_mem.flags = 4583 BNXT_RMEM_RING_PTE_FLAG; 4584 rxr->rx_agg_ring_struct.ring_mem.flags = 4585 BNXT_RMEM_RING_PTE_FLAG; 4586 } 4587 rxr->bnapi = bp->bnapi[i]; 4588 bp->bnapi[i]->rx_ring = &bp->rx_ring[i]; 4589 } 4590 4591 bp->tx_ring = kcalloc(bp->tx_nr_rings, 4592 sizeof(struct bnxt_tx_ring_info), 4593 GFP_KERNEL); 4594 if (!bp->tx_ring) 4595 return -ENOMEM; 4596 4597 bp->tx_ring_map = kcalloc(bp->tx_nr_rings, sizeof(u16), 4598 GFP_KERNEL); 4599 4600 if (!bp->tx_ring_map) 4601 return -ENOMEM; 4602 4603 if (bp->flags & BNXT_FLAG_SHARED_RINGS) 4604 j = 0; 4605 else 4606 j = bp->rx_nr_rings; 4607 4608 for (i = 0; i < bp->tx_nr_rings; i++, j++) { 4609 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; 4610 4611 if (bp->flags & BNXT_FLAG_CHIP_P5) 4612 txr->tx_ring_struct.ring_mem.flags = 4613 BNXT_RMEM_RING_PTE_FLAG; 4614 txr->bnapi = bp->bnapi[j]; 4615 bp->bnapi[j]->tx_ring = txr; 4616 bp->tx_ring_map[i] = bp->tx_nr_rings_xdp + i; 4617 if (i >= bp->tx_nr_rings_xdp) { 4618 txr->txq_index = i - bp->tx_nr_rings_xdp; 4619 bp->bnapi[j]->tx_int = bnxt_tx_int; 4620 } else { 4621 bp->bnapi[j]->flags |= BNXT_NAPI_FLAG_XDP; 4622 bp->bnapi[j]->tx_int = bnxt_tx_int_xdp; 4623 } 4624 } 4625 4626 rc = bnxt_alloc_stats(bp); 4627 if (rc) 4628 goto alloc_mem_err; 4629 bnxt_init_stats(bp); 4630 4631 rc = bnxt_alloc_ntp_fltrs(bp); 4632 if (rc) 4633 goto alloc_mem_err; 4634 4635 rc = bnxt_alloc_vnics(bp); 4636 if (rc) 4637 goto alloc_mem_err; 4638 } 4639 4640 rc = bnxt_alloc_all_cp_arrays(bp); 4641 if (rc) 4642 goto alloc_mem_err; 4643 4644 bnxt_init_ring_struct(bp); 4645 4646 rc = bnxt_alloc_rx_rings(bp); 4647 if (rc) 4648 goto alloc_mem_err; 4649 4650 rc = bnxt_alloc_tx_rings(bp); 4651 if (rc) 4652 goto alloc_mem_err; 4653 4654 rc = bnxt_alloc_cp_rings(bp); 4655 if (rc) 4656 goto alloc_mem_err; 4657 4658 bp->vnic_info[0].flags |= BNXT_VNIC_RSS_FLAG | BNXT_VNIC_MCAST_FLAG | 4659 BNXT_VNIC_UCAST_FLAG; 4660 rc = bnxt_alloc_vnic_attributes(bp); 4661 if (rc) 4662 goto alloc_mem_err; 4663 return 0; 4664 4665 alloc_mem_err: 4666 bnxt_free_mem(bp, true); 4667 return rc; 4668 } 4669 4670 static void bnxt_disable_int(struct bnxt *bp) 4671 { 4672 int i; 4673 4674 if (!bp->bnapi) 4675 return; 4676 4677 for (i = 0; i < bp->cp_nr_rings; i++) { 4678 struct bnxt_napi *bnapi = bp->bnapi[i]; 4679 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 4680 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct; 4681 4682 if (ring->fw_ring_id != INVALID_HW_RING_ID) 4683 bnxt_db_nq(bp, &cpr->cp_db, cpr->cp_raw_cons); 4684 } 4685 } 4686 4687 static int bnxt_cp_num_to_irq_num(struct bnxt *bp, int n) 4688 { 4689 struct bnxt_napi *bnapi = bp->bnapi[n]; 4690 struct bnxt_cp_ring_info *cpr; 4691 4692 cpr = &bnapi->cp_ring; 4693 return cpr->cp_ring_struct.map_idx; 4694 } 4695 4696 static void bnxt_disable_int_sync(struct bnxt *bp) 4697 { 4698 int i; 4699 4700 if (!bp->irq_tbl) 4701 return; 4702 4703 atomic_inc(&bp->intr_sem); 4704 4705 bnxt_disable_int(bp); 4706 for (i = 0; i < bp->cp_nr_rings; i++) { 4707 int map_idx = bnxt_cp_num_to_irq_num(bp, i); 4708 4709 synchronize_irq(bp->irq_tbl[map_idx].vector); 4710 } 4711 } 4712 4713 static void bnxt_enable_int(struct bnxt *bp) 4714 { 4715 int i; 4716 4717 atomic_set(&bp->intr_sem, 0); 4718 for (i = 0; i < bp->cp_nr_rings; i++) { 4719 struct bnxt_napi *bnapi = bp->bnapi[i]; 4720 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 4721 4722 bnxt_db_nq_arm(bp, &cpr->cp_db, cpr->cp_raw_cons); 4723 } 4724 } 4725 4726 int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp, unsigned long *bmap, int bmap_size, 4727 bool async_only) 4728 { 4729 DECLARE_BITMAP(async_events_bmap, 256); 4730 u32 *events = (u32 *)async_events_bmap; 4731 struct hwrm_func_drv_rgtr_output *resp; 4732 struct hwrm_func_drv_rgtr_input *req; 4733 u32 flags; 4734 int rc, i; 4735 4736 rc = hwrm_req_init(bp, req, HWRM_FUNC_DRV_RGTR); 4737 if (rc) 4738 return rc; 4739 4740 req->enables = cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE | 4741 FUNC_DRV_RGTR_REQ_ENABLES_VER | 4742 FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD); 4743 4744 req->os_type = cpu_to_le16(FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX); 4745 flags = FUNC_DRV_RGTR_REQ_FLAGS_16BIT_VER_MODE; 4746 if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET) 4747 flags |= FUNC_DRV_RGTR_REQ_FLAGS_HOT_RESET_SUPPORT; 4748 if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY) 4749 flags |= FUNC_DRV_RGTR_REQ_FLAGS_ERROR_RECOVERY_SUPPORT | 4750 FUNC_DRV_RGTR_REQ_FLAGS_MASTER_SUPPORT; 4751 req->flags = cpu_to_le32(flags); 4752 req->ver_maj_8b = DRV_VER_MAJ; 4753 req->ver_min_8b = DRV_VER_MIN; 4754 req->ver_upd_8b = DRV_VER_UPD; 4755 req->ver_maj = cpu_to_le16(DRV_VER_MAJ); 4756 req->ver_min = cpu_to_le16(DRV_VER_MIN); 4757 req->ver_upd = cpu_to_le16(DRV_VER_UPD); 4758 4759 if (BNXT_PF(bp)) { 4760 u32 data[8]; 4761 int i; 4762 4763 memset(data, 0, sizeof(data)); 4764 for (i = 0; i < ARRAY_SIZE(bnxt_vf_req_snif); i++) { 4765 u16 cmd = bnxt_vf_req_snif[i]; 4766 unsigned int bit, idx; 4767 4768 idx = cmd / 32; 4769 bit = cmd % 32; 4770 data[idx] |= 1 << bit; 4771 } 4772 4773 for (i = 0; i < 8; i++) 4774 req->vf_req_fwd[i] = cpu_to_le32(data[i]); 4775 4776 req->enables |= 4777 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD); 4778 } 4779 4780 if (bp->fw_cap & BNXT_FW_CAP_OVS_64BIT_HANDLE) 4781 req->flags |= cpu_to_le32( 4782 FUNC_DRV_RGTR_REQ_FLAGS_FLOW_HANDLE_64BIT_MODE); 4783 4784 memset(async_events_bmap, 0, sizeof(async_events_bmap)); 4785 for (i = 0; i < ARRAY_SIZE(bnxt_async_events_arr); i++) { 4786 u16 event_id = bnxt_async_events_arr[i]; 4787 4788 if (event_id == ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY && 4789 !(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)) 4790 continue; 4791 if (event_id == ASYNC_EVENT_CMPL_EVENT_ID_PHC_UPDATE && 4792 !bp->ptp_cfg) 4793 continue; 4794 __set_bit(bnxt_async_events_arr[i], async_events_bmap); 4795 } 4796 if (bmap && bmap_size) { 4797 for (i = 0; i < bmap_size; i++) { 4798 if (test_bit(i, bmap)) 4799 __set_bit(i, async_events_bmap); 4800 } 4801 } 4802 for (i = 0; i < 8; i++) 4803 req->async_event_fwd[i] |= cpu_to_le32(events[i]); 4804 4805 if (async_only) 4806 req->enables = 4807 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD); 4808 4809 resp = hwrm_req_hold(bp, req); 4810 rc = hwrm_req_send(bp, req); 4811 if (!rc) { 4812 set_bit(BNXT_STATE_DRV_REGISTERED, &bp->state); 4813 if (resp->flags & 4814 cpu_to_le32(FUNC_DRV_RGTR_RESP_FLAGS_IF_CHANGE_SUPPORTED)) 4815 bp->fw_cap |= BNXT_FW_CAP_IF_CHANGE; 4816 } 4817 hwrm_req_drop(bp, req); 4818 return rc; 4819 } 4820 4821 int bnxt_hwrm_func_drv_unrgtr(struct bnxt *bp) 4822 { 4823 struct hwrm_func_drv_unrgtr_input *req; 4824 int rc; 4825 4826 if (!test_and_clear_bit(BNXT_STATE_DRV_REGISTERED, &bp->state)) 4827 return 0; 4828 4829 rc = hwrm_req_init(bp, req, HWRM_FUNC_DRV_UNRGTR); 4830 if (rc) 4831 return rc; 4832 return hwrm_req_send(bp, req); 4833 } 4834 4835 static int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, u8 tunnel_type) 4836 { 4837 struct hwrm_tunnel_dst_port_free_input *req; 4838 int rc; 4839 4840 if (tunnel_type == TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN && 4841 bp->vxlan_fw_dst_port_id == INVALID_HW_RING_ID) 4842 return 0; 4843 if (tunnel_type == TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE && 4844 bp->nge_fw_dst_port_id == INVALID_HW_RING_ID) 4845 return 0; 4846 4847 rc = hwrm_req_init(bp, req, HWRM_TUNNEL_DST_PORT_FREE); 4848 if (rc) 4849 return rc; 4850 4851 req->tunnel_type = tunnel_type; 4852 4853 switch (tunnel_type) { 4854 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN: 4855 req->tunnel_dst_port_id = cpu_to_le16(bp->vxlan_fw_dst_port_id); 4856 bp->vxlan_port = 0; 4857 bp->vxlan_fw_dst_port_id = INVALID_HW_RING_ID; 4858 break; 4859 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE: 4860 req->tunnel_dst_port_id = cpu_to_le16(bp->nge_fw_dst_port_id); 4861 bp->nge_port = 0; 4862 bp->nge_fw_dst_port_id = INVALID_HW_RING_ID; 4863 break; 4864 default: 4865 break; 4866 } 4867 4868 rc = hwrm_req_send(bp, req); 4869 if (rc) 4870 netdev_err(bp->dev, "hwrm_tunnel_dst_port_free failed. rc:%d\n", 4871 rc); 4872 return rc; 4873 } 4874 4875 static int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, __be16 port, 4876 u8 tunnel_type) 4877 { 4878 struct hwrm_tunnel_dst_port_alloc_output *resp; 4879 struct hwrm_tunnel_dst_port_alloc_input *req; 4880 int rc; 4881 4882 rc = hwrm_req_init(bp, req, HWRM_TUNNEL_DST_PORT_ALLOC); 4883 if (rc) 4884 return rc; 4885 4886 req->tunnel_type = tunnel_type; 4887 req->tunnel_dst_port_val = port; 4888 4889 resp = hwrm_req_hold(bp, req); 4890 rc = hwrm_req_send(bp, req); 4891 if (rc) { 4892 netdev_err(bp->dev, "hwrm_tunnel_dst_port_alloc failed. rc:%d\n", 4893 rc); 4894 goto err_out; 4895 } 4896 4897 switch (tunnel_type) { 4898 case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN: 4899 bp->vxlan_port = port; 4900 bp->vxlan_fw_dst_port_id = 4901 le16_to_cpu(resp->tunnel_dst_port_id); 4902 break; 4903 case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE: 4904 bp->nge_port = port; 4905 bp->nge_fw_dst_port_id = le16_to_cpu(resp->tunnel_dst_port_id); 4906 break; 4907 default: 4908 break; 4909 } 4910 4911 err_out: 4912 hwrm_req_drop(bp, req); 4913 return rc; 4914 } 4915 4916 static int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp, u16 vnic_id) 4917 { 4918 struct hwrm_cfa_l2_set_rx_mask_input *req; 4919 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 4920 int rc; 4921 4922 rc = hwrm_req_init(bp, req, HWRM_CFA_L2_SET_RX_MASK); 4923 if (rc) 4924 return rc; 4925 4926 req->vnic_id = cpu_to_le32(vnic->fw_vnic_id); 4927 if (vnic->rx_mask & CFA_L2_SET_RX_MASK_REQ_MASK_MCAST) { 4928 req->num_mc_entries = cpu_to_le32(vnic->mc_list_count); 4929 req->mc_tbl_addr = cpu_to_le64(vnic->mc_list_mapping); 4930 } 4931 req->mask = cpu_to_le32(vnic->rx_mask); 4932 return hwrm_req_send_silent(bp, req); 4933 } 4934 4935 #ifdef CONFIG_RFS_ACCEL 4936 static int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt *bp, 4937 struct bnxt_ntuple_filter *fltr) 4938 { 4939 struct hwrm_cfa_ntuple_filter_free_input *req; 4940 int rc; 4941 4942 rc = hwrm_req_init(bp, req, HWRM_CFA_NTUPLE_FILTER_FREE); 4943 if (rc) 4944 return rc; 4945 4946 req->ntuple_filter_id = fltr->filter_id; 4947 return hwrm_req_send(bp, req); 4948 } 4949 4950 #define BNXT_NTP_FLTR_FLAGS \ 4951 (CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID | \ 4952 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE | \ 4953 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR | \ 4954 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE | \ 4955 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR | \ 4956 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK | \ 4957 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR | \ 4958 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK | \ 4959 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL | \ 4960 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT | \ 4961 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK | \ 4962 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT | \ 4963 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK | \ 4964 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID) 4965 4966 #define BNXT_NTP_TUNNEL_FLTR_FLAG \ 4967 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 4968 4969 static int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt *bp, 4970 struct bnxt_ntuple_filter *fltr) 4971 { 4972 struct hwrm_cfa_ntuple_filter_alloc_output *resp; 4973 struct hwrm_cfa_ntuple_filter_alloc_input *req; 4974 struct flow_keys *keys = &fltr->fkeys; 4975 struct bnxt_vnic_info *vnic; 4976 u32 flags = 0; 4977 int rc; 4978 4979 rc = hwrm_req_init(bp, req, HWRM_CFA_NTUPLE_FILTER_ALLOC); 4980 if (rc) 4981 return rc; 4982 4983 req->l2_filter_id = bp->vnic_info[0].fw_l2_filter_id[fltr->l2_fltr_idx]; 4984 4985 if (bp->fw_cap & BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V2) { 4986 flags = CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DEST_RFS_RING_IDX; 4987 req->dst_id = cpu_to_le16(fltr->rxq); 4988 } else { 4989 vnic = &bp->vnic_info[fltr->rxq + 1]; 4990 req->dst_id = cpu_to_le16(vnic->fw_vnic_id); 4991 } 4992 req->flags = cpu_to_le32(flags); 4993 req->enables = cpu_to_le32(BNXT_NTP_FLTR_FLAGS); 4994 4995 req->ethertype = htons(ETH_P_IP); 4996 memcpy(req->src_macaddr, fltr->src_mac_addr, ETH_ALEN); 4997 req->ip_addr_type = CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4; 4998 req->ip_protocol = keys->basic.ip_proto; 4999 5000 if (keys->basic.n_proto == htons(ETH_P_IPV6)) { 5001 int i; 5002 5003 req->ethertype = htons(ETH_P_IPV6); 5004 req->ip_addr_type = 5005 CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6; 5006 *(struct in6_addr *)&req->src_ipaddr[0] = 5007 keys->addrs.v6addrs.src; 5008 *(struct in6_addr *)&req->dst_ipaddr[0] = 5009 keys->addrs.v6addrs.dst; 5010 for (i = 0; i < 4; i++) { 5011 req->src_ipaddr_mask[i] = cpu_to_be32(0xffffffff); 5012 req->dst_ipaddr_mask[i] = cpu_to_be32(0xffffffff); 5013 } 5014 } else { 5015 req->src_ipaddr[0] = keys->addrs.v4addrs.src; 5016 req->src_ipaddr_mask[0] = cpu_to_be32(0xffffffff); 5017 req->dst_ipaddr[0] = keys->addrs.v4addrs.dst; 5018 req->dst_ipaddr_mask[0] = cpu_to_be32(0xffffffff); 5019 } 5020 if (keys->control.flags & FLOW_DIS_ENCAPSULATION) { 5021 req->enables |= cpu_to_le32(BNXT_NTP_TUNNEL_FLTR_FLAG); 5022 req->tunnel_type = 5023 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL; 5024 } 5025 5026 req->src_port = keys->ports.src; 5027 req->src_port_mask = cpu_to_be16(0xffff); 5028 req->dst_port = keys->ports.dst; 5029 req->dst_port_mask = cpu_to_be16(0xffff); 5030 5031 resp = hwrm_req_hold(bp, req); 5032 rc = hwrm_req_send(bp, req); 5033 if (!rc) 5034 fltr->filter_id = resp->ntuple_filter_id; 5035 hwrm_req_drop(bp, req); 5036 return rc; 5037 } 5038 #endif 5039 5040 static int bnxt_hwrm_set_vnic_filter(struct bnxt *bp, u16 vnic_id, u16 idx, 5041 const u8 *mac_addr) 5042 { 5043 struct hwrm_cfa_l2_filter_alloc_output *resp; 5044 struct hwrm_cfa_l2_filter_alloc_input *req; 5045 int rc; 5046 5047 rc = hwrm_req_init(bp, req, HWRM_CFA_L2_FILTER_ALLOC); 5048 if (rc) 5049 return rc; 5050 5051 req->flags = cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX); 5052 if (!BNXT_CHIP_TYPE_NITRO_A0(bp)) 5053 req->flags |= 5054 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST); 5055 req->dst_id = cpu_to_le16(bp->vnic_info[vnic_id].fw_vnic_id); 5056 req->enables = 5057 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR | 5058 CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID | 5059 CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK); 5060 memcpy(req->l2_addr, mac_addr, ETH_ALEN); 5061 req->l2_addr_mask[0] = 0xff; 5062 req->l2_addr_mask[1] = 0xff; 5063 req->l2_addr_mask[2] = 0xff; 5064 req->l2_addr_mask[3] = 0xff; 5065 req->l2_addr_mask[4] = 0xff; 5066 req->l2_addr_mask[5] = 0xff; 5067 5068 resp = hwrm_req_hold(bp, req); 5069 rc = hwrm_req_send(bp, req); 5070 if (!rc) 5071 bp->vnic_info[vnic_id].fw_l2_filter_id[idx] = 5072 resp->l2_filter_id; 5073 hwrm_req_drop(bp, req); 5074 return rc; 5075 } 5076 5077 static int bnxt_hwrm_clear_vnic_filter(struct bnxt *bp) 5078 { 5079 struct hwrm_cfa_l2_filter_free_input *req; 5080 u16 i, j, num_of_vnics = 1; /* only vnic 0 supported */ 5081 int rc; 5082 5083 /* Any associated ntuple filters will also be cleared by firmware. */ 5084 rc = hwrm_req_init(bp, req, HWRM_CFA_L2_FILTER_FREE); 5085 if (rc) 5086 return rc; 5087 hwrm_req_hold(bp, req); 5088 for (i = 0; i < num_of_vnics; i++) { 5089 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 5090 5091 for (j = 0; j < vnic->uc_filter_count; j++) { 5092 req->l2_filter_id = vnic->fw_l2_filter_id[j]; 5093 5094 rc = hwrm_req_send(bp, req); 5095 } 5096 vnic->uc_filter_count = 0; 5097 } 5098 hwrm_req_drop(bp, req); 5099 return rc; 5100 } 5101 5102 static int bnxt_hwrm_vnic_set_tpa(struct bnxt *bp, u16 vnic_id, u32 tpa_flags) 5103 { 5104 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 5105 u16 max_aggs = VNIC_TPA_CFG_REQ_MAX_AGGS_MAX; 5106 struct hwrm_vnic_tpa_cfg_input *req; 5107 int rc; 5108 5109 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) 5110 return 0; 5111 5112 rc = hwrm_req_init(bp, req, HWRM_VNIC_TPA_CFG); 5113 if (rc) 5114 return rc; 5115 5116 if (tpa_flags) { 5117 u16 mss = bp->dev->mtu - 40; 5118 u32 nsegs, n, segs = 0, flags; 5119 5120 flags = VNIC_TPA_CFG_REQ_FLAGS_TPA | 5121 VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA | 5122 VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE | 5123 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN | 5124 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ; 5125 if (tpa_flags & BNXT_FLAG_GRO) 5126 flags |= VNIC_TPA_CFG_REQ_FLAGS_GRO; 5127 5128 req->flags = cpu_to_le32(flags); 5129 5130 req->enables = 5131 cpu_to_le32(VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS | 5132 VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS | 5133 VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN); 5134 5135 /* Number of segs are log2 units, and first packet is not 5136 * included as part of this units. 5137 */ 5138 if (mss <= BNXT_RX_PAGE_SIZE) { 5139 n = BNXT_RX_PAGE_SIZE / mss; 5140 nsegs = (MAX_SKB_FRAGS - 1) * n; 5141 } else { 5142 n = mss / BNXT_RX_PAGE_SIZE; 5143 if (mss & (BNXT_RX_PAGE_SIZE - 1)) 5144 n++; 5145 nsegs = (MAX_SKB_FRAGS - n) / n; 5146 } 5147 5148 if (bp->flags & BNXT_FLAG_CHIP_P5) { 5149 segs = MAX_TPA_SEGS_P5; 5150 max_aggs = bp->max_tpa; 5151 } else { 5152 segs = ilog2(nsegs); 5153 } 5154 req->max_agg_segs = cpu_to_le16(segs); 5155 req->max_aggs = cpu_to_le16(max_aggs); 5156 5157 req->min_agg_len = cpu_to_le32(512); 5158 } 5159 req->vnic_id = cpu_to_le16(vnic->fw_vnic_id); 5160 5161 return hwrm_req_send(bp, req); 5162 } 5163 5164 static u16 bnxt_cp_ring_from_grp(struct bnxt *bp, struct bnxt_ring_struct *ring) 5165 { 5166 struct bnxt_ring_grp_info *grp_info; 5167 5168 grp_info = &bp->grp_info[ring->grp_idx]; 5169 return grp_info->cp_fw_ring_id; 5170 } 5171 5172 static u16 bnxt_cp_ring_for_rx(struct bnxt *bp, struct bnxt_rx_ring_info *rxr) 5173 { 5174 if (bp->flags & BNXT_FLAG_CHIP_P5) { 5175 struct bnxt_napi *bnapi = rxr->bnapi; 5176 struct bnxt_cp_ring_info *cpr; 5177 5178 cpr = bnapi->cp_ring.cp_ring_arr[BNXT_RX_HDL]; 5179 return cpr->cp_ring_struct.fw_ring_id; 5180 } else { 5181 return bnxt_cp_ring_from_grp(bp, &rxr->rx_ring_struct); 5182 } 5183 } 5184 5185 static u16 bnxt_cp_ring_for_tx(struct bnxt *bp, struct bnxt_tx_ring_info *txr) 5186 { 5187 if (bp->flags & BNXT_FLAG_CHIP_P5) { 5188 struct bnxt_napi *bnapi = txr->bnapi; 5189 struct bnxt_cp_ring_info *cpr; 5190 5191 cpr = bnapi->cp_ring.cp_ring_arr[BNXT_TX_HDL]; 5192 return cpr->cp_ring_struct.fw_ring_id; 5193 } else { 5194 return bnxt_cp_ring_from_grp(bp, &txr->tx_ring_struct); 5195 } 5196 } 5197 5198 static int bnxt_alloc_rss_indir_tbl(struct bnxt *bp) 5199 { 5200 int entries; 5201 5202 if (bp->flags & BNXT_FLAG_CHIP_P5) 5203 entries = BNXT_MAX_RSS_TABLE_ENTRIES_P5; 5204 else 5205 entries = HW_HASH_INDEX_SIZE; 5206 5207 bp->rss_indir_tbl_entries = entries; 5208 bp->rss_indir_tbl = kmalloc_array(entries, sizeof(*bp->rss_indir_tbl), 5209 GFP_KERNEL); 5210 if (!bp->rss_indir_tbl) 5211 return -ENOMEM; 5212 return 0; 5213 } 5214 5215 static void bnxt_set_dflt_rss_indir_tbl(struct bnxt *bp) 5216 { 5217 u16 max_rings, max_entries, pad, i; 5218 5219 if (!bp->rx_nr_rings) 5220 return; 5221 5222 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 5223 max_rings = bp->rx_nr_rings - 1; 5224 else 5225 max_rings = bp->rx_nr_rings; 5226 5227 max_entries = bnxt_get_rxfh_indir_size(bp->dev); 5228 5229 for (i = 0; i < max_entries; i++) 5230 bp->rss_indir_tbl[i] = ethtool_rxfh_indir_default(i, max_rings); 5231 5232 pad = bp->rss_indir_tbl_entries - max_entries; 5233 if (pad) 5234 memset(&bp->rss_indir_tbl[i], 0, pad * sizeof(u16)); 5235 } 5236 5237 static u16 bnxt_get_max_rss_ring(struct bnxt *bp) 5238 { 5239 u16 i, tbl_size, max_ring = 0; 5240 5241 if (!bp->rss_indir_tbl) 5242 return 0; 5243 5244 tbl_size = bnxt_get_rxfh_indir_size(bp->dev); 5245 for (i = 0; i < tbl_size; i++) 5246 max_ring = max(max_ring, bp->rss_indir_tbl[i]); 5247 return max_ring; 5248 } 5249 5250 int bnxt_get_nr_rss_ctxs(struct bnxt *bp, int rx_rings) 5251 { 5252 if (bp->flags & BNXT_FLAG_CHIP_P5) 5253 return DIV_ROUND_UP(rx_rings, BNXT_RSS_TABLE_ENTRIES_P5); 5254 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 5255 return 2; 5256 return 1; 5257 } 5258 5259 static void bnxt_fill_hw_rss_tbl(struct bnxt *bp, struct bnxt_vnic_info *vnic) 5260 { 5261 bool no_rss = !(vnic->flags & BNXT_VNIC_RSS_FLAG); 5262 u16 i, j; 5263 5264 /* Fill the RSS indirection table with ring group ids */ 5265 for (i = 0, j = 0; i < HW_HASH_INDEX_SIZE; i++) { 5266 if (!no_rss) 5267 j = bp->rss_indir_tbl[i]; 5268 vnic->rss_table[i] = cpu_to_le16(vnic->fw_grp_ids[j]); 5269 } 5270 } 5271 5272 static void bnxt_fill_hw_rss_tbl_p5(struct bnxt *bp, 5273 struct bnxt_vnic_info *vnic) 5274 { 5275 __le16 *ring_tbl = vnic->rss_table; 5276 struct bnxt_rx_ring_info *rxr; 5277 u16 tbl_size, i; 5278 5279 tbl_size = bnxt_get_rxfh_indir_size(bp->dev); 5280 5281 for (i = 0; i < tbl_size; i++) { 5282 u16 ring_id, j; 5283 5284 j = bp->rss_indir_tbl[i]; 5285 rxr = &bp->rx_ring[j]; 5286 5287 ring_id = rxr->rx_ring_struct.fw_ring_id; 5288 *ring_tbl++ = cpu_to_le16(ring_id); 5289 ring_id = bnxt_cp_ring_for_rx(bp, rxr); 5290 *ring_tbl++ = cpu_to_le16(ring_id); 5291 } 5292 } 5293 5294 static void 5295 __bnxt_hwrm_vnic_set_rss(struct bnxt *bp, struct hwrm_vnic_rss_cfg_input *req, 5296 struct bnxt_vnic_info *vnic) 5297 { 5298 if (bp->flags & BNXT_FLAG_CHIP_P5) 5299 bnxt_fill_hw_rss_tbl_p5(bp, vnic); 5300 else 5301 bnxt_fill_hw_rss_tbl(bp, vnic); 5302 5303 if (bp->rss_hash_delta) { 5304 req->hash_type = cpu_to_le32(bp->rss_hash_delta); 5305 if (bp->rss_hash_cfg & bp->rss_hash_delta) 5306 req->flags |= VNIC_RSS_CFG_REQ_FLAGS_HASH_TYPE_INCLUDE; 5307 else 5308 req->flags |= VNIC_RSS_CFG_REQ_FLAGS_HASH_TYPE_EXCLUDE; 5309 } else { 5310 req->hash_type = cpu_to_le32(bp->rss_hash_cfg); 5311 } 5312 req->hash_mode_flags = VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT; 5313 req->ring_grp_tbl_addr = cpu_to_le64(vnic->rss_table_dma_addr); 5314 req->hash_key_tbl_addr = cpu_to_le64(vnic->rss_hash_key_dma_addr); 5315 } 5316 5317 static int bnxt_hwrm_vnic_set_rss(struct bnxt *bp, u16 vnic_id, bool set_rss) 5318 { 5319 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 5320 struct hwrm_vnic_rss_cfg_input *req; 5321 int rc; 5322 5323 if ((bp->flags & BNXT_FLAG_CHIP_P5) || 5324 vnic->fw_rss_cos_lb_ctx[0] == INVALID_HW_RING_ID) 5325 return 0; 5326 5327 rc = hwrm_req_init(bp, req, HWRM_VNIC_RSS_CFG); 5328 if (rc) 5329 return rc; 5330 5331 if (set_rss) 5332 __bnxt_hwrm_vnic_set_rss(bp, req, vnic); 5333 req->rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]); 5334 return hwrm_req_send(bp, req); 5335 } 5336 5337 static int bnxt_hwrm_vnic_set_rss_p5(struct bnxt *bp, u16 vnic_id, bool set_rss) 5338 { 5339 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 5340 struct hwrm_vnic_rss_cfg_input *req; 5341 dma_addr_t ring_tbl_map; 5342 u32 i, nr_ctxs; 5343 int rc; 5344 5345 rc = hwrm_req_init(bp, req, HWRM_VNIC_RSS_CFG); 5346 if (rc) 5347 return rc; 5348 5349 req->vnic_id = cpu_to_le16(vnic->fw_vnic_id); 5350 if (!set_rss) 5351 return hwrm_req_send(bp, req); 5352 5353 __bnxt_hwrm_vnic_set_rss(bp, req, vnic); 5354 ring_tbl_map = vnic->rss_table_dma_addr; 5355 nr_ctxs = bnxt_get_nr_rss_ctxs(bp, bp->rx_nr_rings); 5356 5357 hwrm_req_hold(bp, req); 5358 for (i = 0; i < nr_ctxs; ring_tbl_map += BNXT_RSS_TABLE_SIZE_P5, i++) { 5359 req->ring_grp_tbl_addr = cpu_to_le64(ring_tbl_map); 5360 req->ring_table_pair_index = i; 5361 req->rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[i]); 5362 rc = hwrm_req_send(bp, req); 5363 if (rc) 5364 goto exit; 5365 } 5366 5367 exit: 5368 hwrm_req_drop(bp, req); 5369 return rc; 5370 } 5371 5372 static void bnxt_hwrm_update_rss_hash_cfg(struct bnxt *bp) 5373 { 5374 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 5375 struct hwrm_vnic_rss_qcfg_output *resp; 5376 struct hwrm_vnic_rss_qcfg_input *req; 5377 5378 if (hwrm_req_init(bp, req, HWRM_VNIC_RSS_QCFG)) 5379 return; 5380 5381 req->vnic_id = cpu_to_le16(vnic->fw_vnic_id); 5382 /* all contexts configured to same hash_type, zero always exists */ 5383 req->rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]); 5384 resp = hwrm_req_hold(bp, req); 5385 if (!hwrm_req_send(bp, req)) { 5386 bp->rss_hash_cfg = le32_to_cpu(resp->hash_type) ?: bp->rss_hash_cfg; 5387 bp->rss_hash_delta = 0; 5388 } 5389 hwrm_req_drop(bp, req); 5390 } 5391 5392 static int bnxt_hwrm_vnic_set_hds(struct bnxt *bp, u16 vnic_id) 5393 { 5394 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 5395 struct hwrm_vnic_plcmodes_cfg_input *req; 5396 int rc; 5397 5398 rc = hwrm_req_init(bp, req, HWRM_VNIC_PLCMODES_CFG); 5399 if (rc) 5400 return rc; 5401 5402 req->flags = cpu_to_le32(VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT); 5403 req->enables = cpu_to_le32(VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID); 5404 5405 if (BNXT_RX_PAGE_MODE(bp)) { 5406 req->jumbo_thresh = cpu_to_le16(bp->rx_buf_use_size); 5407 } else { 5408 req->flags |= cpu_to_le32(VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 | 5409 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6); 5410 req->enables |= 5411 cpu_to_le32(VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID); 5412 req->jumbo_thresh = cpu_to_le16(bp->rx_copy_thresh); 5413 req->hds_threshold = cpu_to_le16(bp->rx_copy_thresh); 5414 } 5415 req->vnic_id = cpu_to_le32(vnic->fw_vnic_id); 5416 return hwrm_req_send(bp, req); 5417 } 5418 5419 static void bnxt_hwrm_vnic_ctx_free_one(struct bnxt *bp, u16 vnic_id, 5420 u16 ctx_idx) 5421 { 5422 struct hwrm_vnic_rss_cos_lb_ctx_free_input *req; 5423 5424 if (hwrm_req_init(bp, req, HWRM_VNIC_RSS_COS_LB_CTX_FREE)) 5425 return; 5426 5427 req->rss_cos_lb_ctx_id = 5428 cpu_to_le16(bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx]); 5429 5430 hwrm_req_send(bp, req); 5431 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] = INVALID_HW_RING_ID; 5432 } 5433 5434 static void bnxt_hwrm_vnic_ctx_free(struct bnxt *bp) 5435 { 5436 int i, j; 5437 5438 for (i = 0; i < bp->nr_vnics; i++) { 5439 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 5440 5441 for (j = 0; j < BNXT_MAX_CTX_PER_VNIC; j++) { 5442 if (vnic->fw_rss_cos_lb_ctx[j] != INVALID_HW_RING_ID) 5443 bnxt_hwrm_vnic_ctx_free_one(bp, i, j); 5444 } 5445 } 5446 bp->rsscos_nr_ctxs = 0; 5447 } 5448 5449 static int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, u16 vnic_id, u16 ctx_idx) 5450 { 5451 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp; 5452 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input *req; 5453 int rc; 5454 5455 rc = hwrm_req_init(bp, req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC); 5456 if (rc) 5457 return rc; 5458 5459 resp = hwrm_req_hold(bp, req); 5460 rc = hwrm_req_send(bp, req); 5461 if (!rc) 5462 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] = 5463 le16_to_cpu(resp->rss_cos_lb_ctx_id); 5464 hwrm_req_drop(bp, req); 5465 5466 return rc; 5467 } 5468 5469 static u32 bnxt_get_roce_vnic_mode(struct bnxt *bp) 5470 { 5471 if (bp->flags & BNXT_FLAG_ROCE_MIRROR_CAP) 5472 return VNIC_CFG_REQ_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE; 5473 return VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE; 5474 } 5475 5476 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id) 5477 { 5478 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 5479 struct hwrm_vnic_cfg_input *req; 5480 unsigned int ring = 0, grp_idx; 5481 u16 def_vlan = 0; 5482 int rc; 5483 5484 rc = hwrm_req_init(bp, req, HWRM_VNIC_CFG); 5485 if (rc) 5486 return rc; 5487 5488 if (bp->flags & BNXT_FLAG_CHIP_P5) { 5489 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[0]; 5490 5491 req->default_rx_ring_id = 5492 cpu_to_le16(rxr->rx_ring_struct.fw_ring_id); 5493 req->default_cmpl_ring_id = 5494 cpu_to_le16(bnxt_cp_ring_for_rx(bp, rxr)); 5495 req->enables = 5496 cpu_to_le32(VNIC_CFG_REQ_ENABLES_DEFAULT_RX_RING_ID | 5497 VNIC_CFG_REQ_ENABLES_DEFAULT_CMPL_RING_ID); 5498 goto vnic_mru; 5499 } 5500 req->enables = cpu_to_le32(VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP); 5501 /* Only RSS support for now TBD: COS & LB */ 5502 if (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID) { 5503 req->rss_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]); 5504 req->enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE | 5505 VNIC_CFG_REQ_ENABLES_MRU); 5506 } else if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG) { 5507 req->rss_rule = 5508 cpu_to_le16(bp->vnic_info[0].fw_rss_cos_lb_ctx[0]); 5509 req->enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE | 5510 VNIC_CFG_REQ_ENABLES_MRU); 5511 req->flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE); 5512 } else { 5513 req->rss_rule = cpu_to_le16(0xffff); 5514 } 5515 5516 if (BNXT_CHIP_TYPE_NITRO_A0(bp) && 5517 (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID)) { 5518 req->cos_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[1]); 5519 req->enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_COS_RULE); 5520 } else { 5521 req->cos_rule = cpu_to_le16(0xffff); 5522 } 5523 5524 if (vnic->flags & BNXT_VNIC_RSS_FLAG) 5525 ring = 0; 5526 else if (vnic->flags & BNXT_VNIC_RFS_FLAG) 5527 ring = vnic_id - 1; 5528 else if ((vnic_id == 1) && BNXT_CHIP_TYPE_NITRO_A0(bp)) 5529 ring = bp->rx_nr_rings - 1; 5530 5531 grp_idx = bp->rx_ring[ring].bnapi->index; 5532 req->dflt_ring_grp = cpu_to_le16(bp->grp_info[grp_idx].fw_grp_id); 5533 req->lb_rule = cpu_to_le16(0xffff); 5534 vnic_mru: 5535 req->mru = cpu_to_le16(bp->dev->mtu + ETH_HLEN + VLAN_HLEN); 5536 5537 req->vnic_id = cpu_to_le16(vnic->fw_vnic_id); 5538 #ifdef CONFIG_BNXT_SRIOV 5539 if (BNXT_VF(bp)) 5540 def_vlan = bp->vf.vlan; 5541 #endif 5542 if ((bp->flags & BNXT_FLAG_STRIP_VLAN) || def_vlan) 5543 req->flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE); 5544 if (!vnic_id && bnxt_ulp_registered(bp->edev)) 5545 req->flags |= cpu_to_le32(bnxt_get_roce_vnic_mode(bp)); 5546 5547 return hwrm_req_send(bp, req); 5548 } 5549 5550 static void bnxt_hwrm_vnic_free_one(struct bnxt *bp, u16 vnic_id) 5551 { 5552 if (bp->vnic_info[vnic_id].fw_vnic_id != INVALID_HW_RING_ID) { 5553 struct hwrm_vnic_free_input *req; 5554 5555 if (hwrm_req_init(bp, req, HWRM_VNIC_FREE)) 5556 return; 5557 5558 req->vnic_id = 5559 cpu_to_le32(bp->vnic_info[vnic_id].fw_vnic_id); 5560 5561 hwrm_req_send(bp, req); 5562 bp->vnic_info[vnic_id].fw_vnic_id = INVALID_HW_RING_ID; 5563 } 5564 } 5565 5566 static void bnxt_hwrm_vnic_free(struct bnxt *bp) 5567 { 5568 u16 i; 5569 5570 for (i = 0; i < bp->nr_vnics; i++) 5571 bnxt_hwrm_vnic_free_one(bp, i); 5572 } 5573 5574 static int bnxt_hwrm_vnic_alloc(struct bnxt *bp, u16 vnic_id, 5575 unsigned int start_rx_ring_idx, 5576 unsigned int nr_rings) 5577 { 5578 unsigned int i, j, grp_idx, end_idx = start_rx_ring_idx + nr_rings; 5579 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 5580 struct hwrm_vnic_alloc_output *resp; 5581 struct hwrm_vnic_alloc_input *req; 5582 int rc; 5583 5584 rc = hwrm_req_init(bp, req, HWRM_VNIC_ALLOC); 5585 if (rc) 5586 return rc; 5587 5588 if (bp->flags & BNXT_FLAG_CHIP_P5) 5589 goto vnic_no_ring_grps; 5590 5591 /* map ring groups to this vnic */ 5592 for (i = start_rx_ring_idx, j = 0; i < end_idx; i++, j++) { 5593 grp_idx = bp->rx_ring[i].bnapi->index; 5594 if (bp->grp_info[grp_idx].fw_grp_id == INVALID_HW_RING_ID) { 5595 netdev_err(bp->dev, "Not enough ring groups avail:%x req:%x\n", 5596 j, nr_rings); 5597 break; 5598 } 5599 vnic->fw_grp_ids[j] = bp->grp_info[grp_idx].fw_grp_id; 5600 } 5601 5602 vnic_no_ring_grps: 5603 for (i = 0; i < BNXT_MAX_CTX_PER_VNIC; i++) 5604 vnic->fw_rss_cos_lb_ctx[i] = INVALID_HW_RING_ID; 5605 if (vnic_id == 0) 5606 req->flags = cpu_to_le32(VNIC_ALLOC_REQ_FLAGS_DEFAULT); 5607 5608 resp = hwrm_req_hold(bp, req); 5609 rc = hwrm_req_send(bp, req); 5610 if (!rc) 5611 vnic->fw_vnic_id = le32_to_cpu(resp->vnic_id); 5612 hwrm_req_drop(bp, req); 5613 return rc; 5614 } 5615 5616 static int bnxt_hwrm_vnic_qcaps(struct bnxt *bp) 5617 { 5618 struct hwrm_vnic_qcaps_output *resp; 5619 struct hwrm_vnic_qcaps_input *req; 5620 int rc; 5621 5622 bp->hw_ring_stats_size = sizeof(struct ctx_hw_stats); 5623 bp->flags &= ~(BNXT_FLAG_NEW_RSS_CAP | BNXT_FLAG_ROCE_MIRROR_CAP); 5624 if (bp->hwrm_spec_code < 0x10600) 5625 return 0; 5626 5627 rc = hwrm_req_init(bp, req, HWRM_VNIC_QCAPS); 5628 if (rc) 5629 return rc; 5630 5631 resp = hwrm_req_hold(bp, req); 5632 rc = hwrm_req_send(bp, req); 5633 if (!rc) { 5634 u32 flags = le32_to_cpu(resp->flags); 5635 5636 if (!(bp->flags & BNXT_FLAG_CHIP_P5) && 5637 (flags & VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP)) 5638 bp->flags |= BNXT_FLAG_NEW_RSS_CAP; 5639 if (flags & 5640 VNIC_QCAPS_RESP_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP) 5641 bp->flags |= BNXT_FLAG_ROCE_MIRROR_CAP; 5642 5643 /* Older P5 fw before EXT_HW_STATS support did not set 5644 * VLAN_STRIP_CAP properly. 5645 */ 5646 if ((flags & VNIC_QCAPS_RESP_FLAGS_VLAN_STRIP_CAP) || 5647 (BNXT_CHIP_P5_THOR(bp) && 5648 !(bp->fw_cap & BNXT_FW_CAP_EXT_HW_STATS_SUPPORTED))) 5649 bp->fw_cap |= BNXT_FW_CAP_VLAN_RX_STRIP; 5650 if (flags & VNIC_QCAPS_RESP_FLAGS_RSS_HASH_TYPE_DELTA_CAP) 5651 bp->fw_cap |= BNXT_FW_CAP_RSS_HASH_TYPE_DELTA; 5652 bp->max_tpa_v2 = le16_to_cpu(resp->max_aggs_supported); 5653 if (bp->max_tpa_v2) { 5654 if (BNXT_CHIP_P5_THOR(bp)) 5655 bp->hw_ring_stats_size = BNXT_RING_STATS_SIZE_P5; 5656 else 5657 bp->hw_ring_stats_size = BNXT_RING_STATS_SIZE_P5_SR2; 5658 } 5659 } 5660 hwrm_req_drop(bp, req); 5661 return rc; 5662 } 5663 5664 static int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp) 5665 { 5666 struct hwrm_ring_grp_alloc_output *resp; 5667 struct hwrm_ring_grp_alloc_input *req; 5668 int rc; 5669 u16 i; 5670 5671 if (bp->flags & BNXT_FLAG_CHIP_P5) 5672 return 0; 5673 5674 rc = hwrm_req_init(bp, req, HWRM_RING_GRP_ALLOC); 5675 if (rc) 5676 return rc; 5677 5678 resp = hwrm_req_hold(bp, req); 5679 for (i = 0; i < bp->rx_nr_rings; i++) { 5680 unsigned int grp_idx = bp->rx_ring[i].bnapi->index; 5681 5682 req->cr = cpu_to_le16(bp->grp_info[grp_idx].cp_fw_ring_id); 5683 req->rr = cpu_to_le16(bp->grp_info[grp_idx].rx_fw_ring_id); 5684 req->ar = cpu_to_le16(bp->grp_info[grp_idx].agg_fw_ring_id); 5685 req->sc = cpu_to_le16(bp->grp_info[grp_idx].fw_stats_ctx); 5686 5687 rc = hwrm_req_send(bp, req); 5688 5689 if (rc) 5690 break; 5691 5692 bp->grp_info[grp_idx].fw_grp_id = 5693 le32_to_cpu(resp->ring_group_id); 5694 } 5695 hwrm_req_drop(bp, req); 5696 return rc; 5697 } 5698 5699 static void bnxt_hwrm_ring_grp_free(struct bnxt *bp) 5700 { 5701 struct hwrm_ring_grp_free_input *req; 5702 u16 i; 5703 5704 if (!bp->grp_info || (bp->flags & BNXT_FLAG_CHIP_P5)) 5705 return; 5706 5707 if (hwrm_req_init(bp, req, HWRM_RING_GRP_FREE)) 5708 return; 5709 5710 hwrm_req_hold(bp, req); 5711 for (i = 0; i < bp->cp_nr_rings; i++) { 5712 if (bp->grp_info[i].fw_grp_id == INVALID_HW_RING_ID) 5713 continue; 5714 req->ring_group_id = 5715 cpu_to_le32(bp->grp_info[i].fw_grp_id); 5716 5717 hwrm_req_send(bp, req); 5718 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID; 5719 } 5720 hwrm_req_drop(bp, req); 5721 } 5722 5723 static int hwrm_ring_alloc_send_msg(struct bnxt *bp, 5724 struct bnxt_ring_struct *ring, 5725 u32 ring_type, u32 map_index) 5726 { 5727 struct hwrm_ring_alloc_output *resp; 5728 struct hwrm_ring_alloc_input *req; 5729 struct bnxt_ring_mem_info *rmem = &ring->ring_mem; 5730 struct bnxt_ring_grp_info *grp_info; 5731 int rc, err = 0; 5732 u16 ring_id; 5733 5734 rc = hwrm_req_init(bp, req, HWRM_RING_ALLOC); 5735 if (rc) 5736 goto exit; 5737 5738 req->enables = 0; 5739 if (rmem->nr_pages > 1) { 5740 req->page_tbl_addr = cpu_to_le64(rmem->pg_tbl_map); 5741 /* Page size is in log2 units */ 5742 req->page_size = BNXT_PAGE_SHIFT; 5743 req->page_tbl_depth = 1; 5744 } else { 5745 req->page_tbl_addr = cpu_to_le64(rmem->dma_arr[0]); 5746 } 5747 req->fbo = 0; 5748 /* Association of ring index with doorbell index and MSIX number */ 5749 req->logical_id = cpu_to_le16(map_index); 5750 5751 switch (ring_type) { 5752 case HWRM_RING_ALLOC_TX: { 5753 struct bnxt_tx_ring_info *txr; 5754 5755 txr = container_of(ring, struct bnxt_tx_ring_info, 5756 tx_ring_struct); 5757 req->ring_type = RING_ALLOC_REQ_RING_TYPE_TX; 5758 /* Association of transmit ring with completion ring */ 5759 grp_info = &bp->grp_info[ring->grp_idx]; 5760 req->cmpl_ring_id = cpu_to_le16(bnxt_cp_ring_for_tx(bp, txr)); 5761 req->length = cpu_to_le32(bp->tx_ring_mask + 1); 5762 req->stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx); 5763 req->queue_id = cpu_to_le16(ring->queue_id); 5764 break; 5765 } 5766 case HWRM_RING_ALLOC_RX: 5767 req->ring_type = RING_ALLOC_REQ_RING_TYPE_RX; 5768 req->length = cpu_to_le32(bp->rx_ring_mask + 1); 5769 if (bp->flags & BNXT_FLAG_CHIP_P5) { 5770 u16 flags = 0; 5771 5772 /* Association of rx ring with stats context */ 5773 grp_info = &bp->grp_info[ring->grp_idx]; 5774 req->rx_buf_size = cpu_to_le16(bp->rx_buf_use_size); 5775 req->stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx); 5776 req->enables |= cpu_to_le32( 5777 RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID); 5778 if (NET_IP_ALIGN == 2) 5779 flags = RING_ALLOC_REQ_FLAGS_RX_SOP_PAD; 5780 req->flags = cpu_to_le16(flags); 5781 } 5782 break; 5783 case HWRM_RING_ALLOC_AGG: 5784 if (bp->flags & BNXT_FLAG_CHIP_P5) { 5785 req->ring_type = RING_ALLOC_REQ_RING_TYPE_RX_AGG; 5786 /* Association of agg ring with rx ring */ 5787 grp_info = &bp->grp_info[ring->grp_idx]; 5788 req->rx_ring_id = cpu_to_le16(grp_info->rx_fw_ring_id); 5789 req->rx_buf_size = cpu_to_le16(BNXT_RX_PAGE_SIZE); 5790 req->stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx); 5791 req->enables |= cpu_to_le32( 5792 RING_ALLOC_REQ_ENABLES_RX_RING_ID_VALID | 5793 RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID); 5794 } else { 5795 req->ring_type = RING_ALLOC_REQ_RING_TYPE_RX; 5796 } 5797 req->length = cpu_to_le32(bp->rx_agg_ring_mask + 1); 5798 break; 5799 case HWRM_RING_ALLOC_CMPL: 5800 req->ring_type = RING_ALLOC_REQ_RING_TYPE_L2_CMPL; 5801 req->length = cpu_to_le32(bp->cp_ring_mask + 1); 5802 if (bp->flags & BNXT_FLAG_CHIP_P5) { 5803 /* Association of cp ring with nq */ 5804 grp_info = &bp->grp_info[map_index]; 5805 req->nq_ring_id = cpu_to_le16(grp_info->cp_fw_ring_id); 5806 req->cq_handle = cpu_to_le64(ring->handle); 5807 req->enables |= cpu_to_le32( 5808 RING_ALLOC_REQ_ENABLES_NQ_RING_ID_VALID); 5809 } else if (bp->flags & BNXT_FLAG_USING_MSIX) { 5810 req->int_mode = RING_ALLOC_REQ_INT_MODE_MSIX; 5811 } 5812 break; 5813 case HWRM_RING_ALLOC_NQ: 5814 req->ring_type = RING_ALLOC_REQ_RING_TYPE_NQ; 5815 req->length = cpu_to_le32(bp->cp_ring_mask + 1); 5816 if (bp->flags & BNXT_FLAG_USING_MSIX) 5817 req->int_mode = RING_ALLOC_REQ_INT_MODE_MSIX; 5818 break; 5819 default: 5820 netdev_err(bp->dev, "hwrm alloc invalid ring type %d\n", 5821 ring_type); 5822 return -1; 5823 } 5824 5825 resp = hwrm_req_hold(bp, req); 5826 rc = hwrm_req_send(bp, req); 5827 err = le16_to_cpu(resp->error_code); 5828 ring_id = le16_to_cpu(resp->ring_id); 5829 hwrm_req_drop(bp, req); 5830 5831 exit: 5832 if (rc || err) { 5833 netdev_err(bp->dev, "hwrm_ring_alloc type %d failed. rc:%x err:%x\n", 5834 ring_type, rc, err); 5835 return -EIO; 5836 } 5837 ring->fw_ring_id = ring_id; 5838 return rc; 5839 } 5840 5841 static int bnxt_hwrm_set_async_event_cr(struct bnxt *bp, int idx) 5842 { 5843 int rc; 5844 5845 if (BNXT_PF(bp)) { 5846 struct hwrm_func_cfg_input *req; 5847 5848 rc = hwrm_req_init(bp, req, HWRM_FUNC_CFG); 5849 if (rc) 5850 return rc; 5851 5852 req->fid = cpu_to_le16(0xffff); 5853 req->enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR); 5854 req->async_event_cr = cpu_to_le16(idx); 5855 return hwrm_req_send(bp, req); 5856 } else { 5857 struct hwrm_func_vf_cfg_input *req; 5858 5859 rc = hwrm_req_init(bp, req, HWRM_FUNC_VF_CFG); 5860 if (rc) 5861 return rc; 5862 5863 req->enables = 5864 cpu_to_le32(FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR); 5865 req->async_event_cr = cpu_to_le16(idx); 5866 return hwrm_req_send(bp, req); 5867 } 5868 } 5869 5870 static void bnxt_set_db(struct bnxt *bp, struct bnxt_db_info *db, u32 ring_type, 5871 u32 map_idx, u32 xid) 5872 { 5873 if (bp->flags & BNXT_FLAG_CHIP_P5) { 5874 if (BNXT_PF(bp)) 5875 db->doorbell = bp->bar1 + DB_PF_OFFSET_P5; 5876 else 5877 db->doorbell = bp->bar1 + DB_VF_OFFSET_P5; 5878 switch (ring_type) { 5879 case HWRM_RING_ALLOC_TX: 5880 db->db_key64 = DBR_PATH_L2 | DBR_TYPE_SQ; 5881 break; 5882 case HWRM_RING_ALLOC_RX: 5883 case HWRM_RING_ALLOC_AGG: 5884 db->db_key64 = DBR_PATH_L2 | DBR_TYPE_SRQ; 5885 break; 5886 case HWRM_RING_ALLOC_CMPL: 5887 db->db_key64 = DBR_PATH_L2; 5888 break; 5889 case HWRM_RING_ALLOC_NQ: 5890 db->db_key64 = DBR_PATH_L2; 5891 break; 5892 } 5893 db->db_key64 |= (u64)xid << DBR_XID_SFT; 5894 } else { 5895 db->doorbell = bp->bar1 + map_idx * 0x80; 5896 switch (ring_type) { 5897 case HWRM_RING_ALLOC_TX: 5898 db->db_key32 = DB_KEY_TX; 5899 break; 5900 case HWRM_RING_ALLOC_RX: 5901 case HWRM_RING_ALLOC_AGG: 5902 db->db_key32 = DB_KEY_RX; 5903 break; 5904 case HWRM_RING_ALLOC_CMPL: 5905 db->db_key32 = DB_KEY_CP; 5906 break; 5907 } 5908 } 5909 } 5910 5911 static int bnxt_hwrm_ring_alloc(struct bnxt *bp) 5912 { 5913 bool agg_rings = !!(bp->flags & BNXT_FLAG_AGG_RINGS); 5914 int i, rc = 0; 5915 u32 type; 5916 5917 if (bp->flags & BNXT_FLAG_CHIP_P5) 5918 type = HWRM_RING_ALLOC_NQ; 5919 else 5920 type = HWRM_RING_ALLOC_CMPL; 5921 for (i = 0; i < bp->cp_nr_rings; i++) { 5922 struct bnxt_napi *bnapi = bp->bnapi[i]; 5923 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 5924 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct; 5925 u32 map_idx = ring->map_idx; 5926 unsigned int vector; 5927 5928 vector = bp->irq_tbl[map_idx].vector; 5929 disable_irq_nosync(vector); 5930 rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx); 5931 if (rc) { 5932 enable_irq(vector); 5933 goto err_out; 5934 } 5935 bnxt_set_db(bp, &cpr->cp_db, type, map_idx, ring->fw_ring_id); 5936 bnxt_db_nq(bp, &cpr->cp_db, cpr->cp_raw_cons); 5937 enable_irq(vector); 5938 bp->grp_info[i].cp_fw_ring_id = ring->fw_ring_id; 5939 5940 if (!i) { 5941 rc = bnxt_hwrm_set_async_event_cr(bp, ring->fw_ring_id); 5942 if (rc) 5943 netdev_warn(bp->dev, "Failed to set async event completion ring.\n"); 5944 } 5945 } 5946 5947 type = HWRM_RING_ALLOC_TX; 5948 for (i = 0; i < bp->tx_nr_rings; i++) { 5949 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; 5950 struct bnxt_ring_struct *ring; 5951 u32 map_idx; 5952 5953 if (bp->flags & BNXT_FLAG_CHIP_P5) { 5954 struct bnxt_napi *bnapi = txr->bnapi; 5955 struct bnxt_cp_ring_info *cpr, *cpr2; 5956 u32 type2 = HWRM_RING_ALLOC_CMPL; 5957 5958 cpr = &bnapi->cp_ring; 5959 cpr2 = cpr->cp_ring_arr[BNXT_TX_HDL]; 5960 ring = &cpr2->cp_ring_struct; 5961 ring->handle = BNXT_TX_HDL; 5962 map_idx = bnapi->index; 5963 rc = hwrm_ring_alloc_send_msg(bp, ring, type2, map_idx); 5964 if (rc) 5965 goto err_out; 5966 bnxt_set_db(bp, &cpr2->cp_db, type2, map_idx, 5967 ring->fw_ring_id); 5968 bnxt_db_cq(bp, &cpr2->cp_db, cpr2->cp_raw_cons); 5969 } 5970 ring = &txr->tx_ring_struct; 5971 map_idx = i; 5972 rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx); 5973 if (rc) 5974 goto err_out; 5975 bnxt_set_db(bp, &txr->tx_db, type, map_idx, ring->fw_ring_id); 5976 } 5977 5978 type = HWRM_RING_ALLOC_RX; 5979 for (i = 0; i < bp->rx_nr_rings; i++) { 5980 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 5981 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct; 5982 struct bnxt_napi *bnapi = rxr->bnapi; 5983 u32 map_idx = bnapi->index; 5984 5985 rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx); 5986 if (rc) 5987 goto err_out; 5988 bnxt_set_db(bp, &rxr->rx_db, type, map_idx, ring->fw_ring_id); 5989 /* If we have agg rings, post agg buffers first. */ 5990 if (!agg_rings) 5991 bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod); 5992 bp->grp_info[map_idx].rx_fw_ring_id = ring->fw_ring_id; 5993 if (bp->flags & BNXT_FLAG_CHIP_P5) { 5994 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 5995 u32 type2 = HWRM_RING_ALLOC_CMPL; 5996 struct bnxt_cp_ring_info *cpr2; 5997 5998 cpr2 = cpr->cp_ring_arr[BNXT_RX_HDL]; 5999 ring = &cpr2->cp_ring_struct; 6000 ring->handle = BNXT_RX_HDL; 6001 rc = hwrm_ring_alloc_send_msg(bp, ring, type2, map_idx); 6002 if (rc) 6003 goto err_out; 6004 bnxt_set_db(bp, &cpr2->cp_db, type2, map_idx, 6005 ring->fw_ring_id); 6006 bnxt_db_cq(bp, &cpr2->cp_db, cpr2->cp_raw_cons); 6007 } 6008 } 6009 6010 if (agg_rings) { 6011 type = HWRM_RING_ALLOC_AGG; 6012 for (i = 0; i < bp->rx_nr_rings; i++) { 6013 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 6014 struct bnxt_ring_struct *ring = 6015 &rxr->rx_agg_ring_struct; 6016 u32 grp_idx = ring->grp_idx; 6017 u32 map_idx = grp_idx + bp->rx_nr_rings; 6018 6019 rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx); 6020 if (rc) 6021 goto err_out; 6022 6023 bnxt_set_db(bp, &rxr->rx_agg_db, type, map_idx, 6024 ring->fw_ring_id); 6025 bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod); 6026 bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod); 6027 bp->grp_info[grp_idx].agg_fw_ring_id = ring->fw_ring_id; 6028 } 6029 } 6030 err_out: 6031 return rc; 6032 } 6033 6034 static int hwrm_ring_free_send_msg(struct bnxt *bp, 6035 struct bnxt_ring_struct *ring, 6036 u32 ring_type, int cmpl_ring_id) 6037 { 6038 struct hwrm_ring_free_output *resp; 6039 struct hwrm_ring_free_input *req; 6040 u16 error_code = 0; 6041 int rc; 6042 6043 if (BNXT_NO_FW_ACCESS(bp)) 6044 return 0; 6045 6046 rc = hwrm_req_init(bp, req, HWRM_RING_FREE); 6047 if (rc) 6048 goto exit; 6049 6050 req->cmpl_ring = cpu_to_le16(cmpl_ring_id); 6051 req->ring_type = ring_type; 6052 req->ring_id = cpu_to_le16(ring->fw_ring_id); 6053 6054 resp = hwrm_req_hold(bp, req); 6055 rc = hwrm_req_send(bp, req); 6056 error_code = le16_to_cpu(resp->error_code); 6057 hwrm_req_drop(bp, req); 6058 exit: 6059 if (rc || error_code) { 6060 netdev_err(bp->dev, "hwrm_ring_free type %d failed. rc:%x err:%x\n", 6061 ring_type, rc, error_code); 6062 return -EIO; 6063 } 6064 return 0; 6065 } 6066 6067 static void bnxt_hwrm_ring_free(struct bnxt *bp, bool close_path) 6068 { 6069 u32 type; 6070 int i; 6071 6072 if (!bp->bnapi) 6073 return; 6074 6075 for (i = 0; i < bp->tx_nr_rings; i++) { 6076 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; 6077 struct bnxt_ring_struct *ring = &txr->tx_ring_struct; 6078 6079 if (ring->fw_ring_id != INVALID_HW_RING_ID) { 6080 u32 cmpl_ring_id = bnxt_cp_ring_for_tx(bp, txr); 6081 6082 hwrm_ring_free_send_msg(bp, ring, 6083 RING_FREE_REQ_RING_TYPE_TX, 6084 close_path ? cmpl_ring_id : 6085 INVALID_HW_RING_ID); 6086 ring->fw_ring_id = INVALID_HW_RING_ID; 6087 } 6088 } 6089 6090 for (i = 0; i < bp->rx_nr_rings; i++) { 6091 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 6092 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct; 6093 u32 grp_idx = rxr->bnapi->index; 6094 6095 if (ring->fw_ring_id != INVALID_HW_RING_ID) { 6096 u32 cmpl_ring_id = bnxt_cp_ring_for_rx(bp, rxr); 6097 6098 hwrm_ring_free_send_msg(bp, ring, 6099 RING_FREE_REQ_RING_TYPE_RX, 6100 close_path ? cmpl_ring_id : 6101 INVALID_HW_RING_ID); 6102 ring->fw_ring_id = INVALID_HW_RING_ID; 6103 bp->grp_info[grp_idx].rx_fw_ring_id = 6104 INVALID_HW_RING_ID; 6105 } 6106 } 6107 6108 if (bp->flags & BNXT_FLAG_CHIP_P5) 6109 type = RING_FREE_REQ_RING_TYPE_RX_AGG; 6110 else 6111 type = RING_FREE_REQ_RING_TYPE_RX; 6112 for (i = 0; i < bp->rx_nr_rings; i++) { 6113 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 6114 struct bnxt_ring_struct *ring = &rxr->rx_agg_ring_struct; 6115 u32 grp_idx = rxr->bnapi->index; 6116 6117 if (ring->fw_ring_id != INVALID_HW_RING_ID) { 6118 u32 cmpl_ring_id = bnxt_cp_ring_for_rx(bp, rxr); 6119 6120 hwrm_ring_free_send_msg(bp, ring, type, 6121 close_path ? cmpl_ring_id : 6122 INVALID_HW_RING_ID); 6123 ring->fw_ring_id = INVALID_HW_RING_ID; 6124 bp->grp_info[grp_idx].agg_fw_ring_id = 6125 INVALID_HW_RING_ID; 6126 } 6127 } 6128 6129 /* The completion rings are about to be freed. After that the 6130 * IRQ doorbell will not work anymore. So we need to disable 6131 * IRQ here. 6132 */ 6133 bnxt_disable_int_sync(bp); 6134 6135 if (bp->flags & BNXT_FLAG_CHIP_P5) 6136 type = RING_FREE_REQ_RING_TYPE_NQ; 6137 else 6138 type = RING_FREE_REQ_RING_TYPE_L2_CMPL; 6139 for (i = 0; i < bp->cp_nr_rings; i++) { 6140 struct bnxt_napi *bnapi = bp->bnapi[i]; 6141 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 6142 struct bnxt_ring_struct *ring; 6143 int j; 6144 6145 for (j = 0; j < 2; j++) { 6146 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j]; 6147 6148 if (cpr2) { 6149 ring = &cpr2->cp_ring_struct; 6150 if (ring->fw_ring_id == INVALID_HW_RING_ID) 6151 continue; 6152 hwrm_ring_free_send_msg(bp, ring, 6153 RING_FREE_REQ_RING_TYPE_L2_CMPL, 6154 INVALID_HW_RING_ID); 6155 ring->fw_ring_id = INVALID_HW_RING_ID; 6156 } 6157 } 6158 ring = &cpr->cp_ring_struct; 6159 if (ring->fw_ring_id != INVALID_HW_RING_ID) { 6160 hwrm_ring_free_send_msg(bp, ring, type, 6161 INVALID_HW_RING_ID); 6162 ring->fw_ring_id = INVALID_HW_RING_ID; 6163 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID; 6164 } 6165 } 6166 } 6167 6168 static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max, 6169 bool shared); 6170 6171 static int bnxt_hwrm_get_rings(struct bnxt *bp) 6172 { 6173 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 6174 struct hwrm_func_qcfg_output *resp; 6175 struct hwrm_func_qcfg_input *req; 6176 int rc; 6177 6178 if (bp->hwrm_spec_code < 0x10601) 6179 return 0; 6180 6181 rc = hwrm_req_init(bp, req, HWRM_FUNC_QCFG); 6182 if (rc) 6183 return rc; 6184 6185 req->fid = cpu_to_le16(0xffff); 6186 resp = hwrm_req_hold(bp, req); 6187 rc = hwrm_req_send(bp, req); 6188 if (rc) { 6189 hwrm_req_drop(bp, req); 6190 return rc; 6191 } 6192 6193 hw_resc->resv_tx_rings = le16_to_cpu(resp->alloc_tx_rings); 6194 if (BNXT_NEW_RM(bp)) { 6195 u16 cp, stats; 6196 6197 hw_resc->resv_rx_rings = le16_to_cpu(resp->alloc_rx_rings); 6198 hw_resc->resv_hw_ring_grps = 6199 le32_to_cpu(resp->alloc_hw_ring_grps); 6200 hw_resc->resv_vnics = le16_to_cpu(resp->alloc_vnics); 6201 cp = le16_to_cpu(resp->alloc_cmpl_rings); 6202 stats = le16_to_cpu(resp->alloc_stat_ctx); 6203 hw_resc->resv_irqs = cp; 6204 if (bp->flags & BNXT_FLAG_CHIP_P5) { 6205 int rx = hw_resc->resv_rx_rings; 6206 int tx = hw_resc->resv_tx_rings; 6207 6208 if (bp->flags & BNXT_FLAG_AGG_RINGS) 6209 rx >>= 1; 6210 if (cp < (rx + tx)) { 6211 bnxt_trim_rings(bp, &rx, &tx, cp, false); 6212 if (bp->flags & BNXT_FLAG_AGG_RINGS) 6213 rx <<= 1; 6214 hw_resc->resv_rx_rings = rx; 6215 hw_resc->resv_tx_rings = tx; 6216 } 6217 hw_resc->resv_irqs = le16_to_cpu(resp->alloc_msix); 6218 hw_resc->resv_hw_ring_grps = rx; 6219 } 6220 hw_resc->resv_cp_rings = cp; 6221 hw_resc->resv_stat_ctxs = stats; 6222 } 6223 hwrm_req_drop(bp, req); 6224 return 0; 6225 } 6226 6227 int __bnxt_hwrm_get_tx_rings(struct bnxt *bp, u16 fid, int *tx_rings) 6228 { 6229 struct hwrm_func_qcfg_output *resp; 6230 struct hwrm_func_qcfg_input *req; 6231 int rc; 6232 6233 if (bp->hwrm_spec_code < 0x10601) 6234 return 0; 6235 6236 rc = hwrm_req_init(bp, req, HWRM_FUNC_QCFG); 6237 if (rc) 6238 return rc; 6239 6240 req->fid = cpu_to_le16(fid); 6241 resp = hwrm_req_hold(bp, req); 6242 rc = hwrm_req_send(bp, req); 6243 if (!rc) 6244 *tx_rings = le16_to_cpu(resp->alloc_tx_rings); 6245 6246 hwrm_req_drop(bp, req); 6247 return rc; 6248 } 6249 6250 static bool bnxt_rfs_supported(struct bnxt *bp); 6251 6252 static struct hwrm_func_cfg_input * 6253 __bnxt_hwrm_reserve_pf_rings(struct bnxt *bp, int tx_rings, int rx_rings, 6254 int ring_grps, int cp_rings, int stats, int vnics) 6255 { 6256 struct hwrm_func_cfg_input *req; 6257 u32 enables = 0; 6258 6259 if (hwrm_req_init(bp, req, HWRM_FUNC_CFG)) 6260 return NULL; 6261 6262 req->fid = cpu_to_le16(0xffff); 6263 enables |= tx_rings ? FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS : 0; 6264 req->num_tx_rings = cpu_to_le16(tx_rings); 6265 if (BNXT_NEW_RM(bp)) { 6266 enables |= rx_rings ? FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS : 0; 6267 enables |= stats ? FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0; 6268 if (bp->flags & BNXT_FLAG_CHIP_P5) { 6269 enables |= cp_rings ? FUNC_CFG_REQ_ENABLES_NUM_MSIX : 0; 6270 enables |= tx_rings + ring_grps ? 6271 FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0; 6272 enables |= rx_rings ? 6273 FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0; 6274 } else { 6275 enables |= cp_rings ? 6276 FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0; 6277 enables |= ring_grps ? 6278 FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS | 6279 FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0; 6280 } 6281 enables |= vnics ? FUNC_CFG_REQ_ENABLES_NUM_VNICS : 0; 6282 6283 req->num_rx_rings = cpu_to_le16(rx_rings); 6284 if (bp->flags & BNXT_FLAG_CHIP_P5) { 6285 req->num_cmpl_rings = cpu_to_le16(tx_rings + ring_grps); 6286 req->num_msix = cpu_to_le16(cp_rings); 6287 req->num_rsscos_ctxs = 6288 cpu_to_le16(DIV_ROUND_UP(ring_grps, 64)); 6289 } else { 6290 req->num_cmpl_rings = cpu_to_le16(cp_rings); 6291 req->num_hw_ring_grps = cpu_to_le16(ring_grps); 6292 req->num_rsscos_ctxs = cpu_to_le16(1); 6293 if (!(bp->flags & BNXT_FLAG_NEW_RSS_CAP) && 6294 bnxt_rfs_supported(bp)) 6295 req->num_rsscos_ctxs = 6296 cpu_to_le16(ring_grps + 1); 6297 } 6298 req->num_stat_ctxs = cpu_to_le16(stats); 6299 req->num_vnics = cpu_to_le16(vnics); 6300 } 6301 req->enables = cpu_to_le32(enables); 6302 return req; 6303 } 6304 6305 static struct hwrm_func_vf_cfg_input * 6306 __bnxt_hwrm_reserve_vf_rings(struct bnxt *bp, int tx_rings, int rx_rings, 6307 int ring_grps, int cp_rings, int stats, int vnics) 6308 { 6309 struct hwrm_func_vf_cfg_input *req; 6310 u32 enables = 0; 6311 6312 if (hwrm_req_init(bp, req, HWRM_FUNC_VF_CFG)) 6313 return NULL; 6314 6315 enables |= tx_rings ? FUNC_VF_CFG_REQ_ENABLES_NUM_TX_RINGS : 0; 6316 enables |= rx_rings ? FUNC_VF_CFG_REQ_ENABLES_NUM_RX_RINGS | 6317 FUNC_VF_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0; 6318 enables |= stats ? FUNC_VF_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0; 6319 if (bp->flags & BNXT_FLAG_CHIP_P5) { 6320 enables |= tx_rings + ring_grps ? 6321 FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0; 6322 } else { 6323 enables |= cp_rings ? 6324 FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0; 6325 enables |= ring_grps ? 6326 FUNC_VF_CFG_REQ_ENABLES_NUM_HW_RING_GRPS : 0; 6327 } 6328 enables |= vnics ? FUNC_VF_CFG_REQ_ENABLES_NUM_VNICS : 0; 6329 enables |= FUNC_VF_CFG_REQ_ENABLES_NUM_L2_CTXS; 6330 6331 req->num_l2_ctxs = cpu_to_le16(BNXT_VF_MAX_L2_CTX); 6332 req->num_tx_rings = cpu_to_le16(tx_rings); 6333 req->num_rx_rings = cpu_to_le16(rx_rings); 6334 if (bp->flags & BNXT_FLAG_CHIP_P5) { 6335 req->num_cmpl_rings = cpu_to_le16(tx_rings + ring_grps); 6336 req->num_rsscos_ctxs = cpu_to_le16(DIV_ROUND_UP(ring_grps, 64)); 6337 } else { 6338 req->num_cmpl_rings = cpu_to_le16(cp_rings); 6339 req->num_hw_ring_grps = cpu_to_le16(ring_grps); 6340 req->num_rsscos_ctxs = cpu_to_le16(BNXT_VF_MAX_RSS_CTX); 6341 } 6342 req->num_stat_ctxs = cpu_to_le16(stats); 6343 req->num_vnics = cpu_to_le16(vnics); 6344 6345 req->enables = cpu_to_le32(enables); 6346 return req; 6347 } 6348 6349 static int 6350 bnxt_hwrm_reserve_pf_rings(struct bnxt *bp, int tx_rings, int rx_rings, 6351 int ring_grps, int cp_rings, int stats, int vnics) 6352 { 6353 struct hwrm_func_cfg_input *req; 6354 int rc; 6355 6356 req = __bnxt_hwrm_reserve_pf_rings(bp, tx_rings, rx_rings, ring_grps, 6357 cp_rings, stats, vnics); 6358 if (!req) 6359 return -ENOMEM; 6360 6361 if (!req->enables) { 6362 hwrm_req_drop(bp, req); 6363 return 0; 6364 } 6365 6366 rc = hwrm_req_send(bp, req); 6367 if (rc) 6368 return rc; 6369 6370 if (bp->hwrm_spec_code < 0x10601) 6371 bp->hw_resc.resv_tx_rings = tx_rings; 6372 6373 return bnxt_hwrm_get_rings(bp); 6374 } 6375 6376 static int 6377 bnxt_hwrm_reserve_vf_rings(struct bnxt *bp, int tx_rings, int rx_rings, 6378 int ring_grps, int cp_rings, int stats, int vnics) 6379 { 6380 struct hwrm_func_vf_cfg_input *req; 6381 int rc; 6382 6383 if (!BNXT_NEW_RM(bp)) { 6384 bp->hw_resc.resv_tx_rings = tx_rings; 6385 return 0; 6386 } 6387 6388 req = __bnxt_hwrm_reserve_vf_rings(bp, tx_rings, rx_rings, ring_grps, 6389 cp_rings, stats, vnics); 6390 if (!req) 6391 return -ENOMEM; 6392 6393 rc = hwrm_req_send(bp, req); 6394 if (rc) 6395 return rc; 6396 6397 return bnxt_hwrm_get_rings(bp); 6398 } 6399 6400 static int bnxt_hwrm_reserve_rings(struct bnxt *bp, int tx, int rx, int grp, 6401 int cp, int stat, int vnic) 6402 { 6403 if (BNXT_PF(bp)) 6404 return bnxt_hwrm_reserve_pf_rings(bp, tx, rx, grp, cp, stat, 6405 vnic); 6406 else 6407 return bnxt_hwrm_reserve_vf_rings(bp, tx, rx, grp, cp, stat, 6408 vnic); 6409 } 6410 6411 int bnxt_nq_rings_in_use(struct bnxt *bp) 6412 { 6413 int cp = bp->cp_nr_rings; 6414 int ulp_msix, ulp_base; 6415 6416 ulp_msix = bnxt_get_ulp_msix_num(bp); 6417 if (ulp_msix) { 6418 ulp_base = bnxt_get_ulp_msix_base(bp); 6419 cp += ulp_msix; 6420 if ((ulp_base + ulp_msix) > cp) 6421 cp = ulp_base + ulp_msix; 6422 } 6423 return cp; 6424 } 6425 6426 static int bnxt_cp_rings_in_use(struct bnxt *bp) 6427 { 6428 int cp; 6429 6430 if (!(bp->flags & BNXT_FLAG_CHIP_P5)) 6431 return bnxt_nq_rings_in_use(bp); 6432 6433 cp = bp->tx_nr_rings + bp->rx_nr_rings; 6434 return cp; 6435 } 6436 6437 static int bnxt_get_func_stat_ctxs(struct bnxt *bp) 6438 { 6439 int ulp_stat = bnxt_get_ulp_stat_ctxs(bp); 6440 int cp = bp->cp_nr_rings; 6441 6442 if (!ulp_stat) 6443 return cp; 6444 6445 if (bnxt_nq_rings_in_use(bp) > cp + bnxt_get_ulp_msix_num(bp)) 6446 return bnxt_get_ulp_msix_base(bp) + ulp_stat; 6447 6448 return cp + ulp_stat; 6449 } 6450 6451 /* Check if a default RSS map needs to be setup. This function is only 6452 * used on older firmware that does not require reserving RX rings. 6453 */ 6454 static void bnxt_check_rss_tbl_no_rmgr(struct bnxt *bp) 6455 { 6456 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 6457 6458 /* The RSS map is valid for RX rings set to resv_rx_rings */ 6459 if (hw_resc->resv_rx_rings != bp->rx_nr_rings) { 6460 hw_resc->resv_rx_rings = bp->rx_nr_rings; 6461 if (!netif_is_rxfh_configured(bp->dev)) 6462 bnxt_set_dflt_rss_indir_tbl(bp); 6463 } 6464 } 6465 6466 static bool bnxt_need_reserve_rings(struct bnxt *bp) 6467 { 6468 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 6469 int cp = bnxt_cp_rings_in_use(bp); 6470 int nq = bnxt_nq_rings_in_use(bp); 6471 int rx = bp->rx_nr_rings, stat; 6472 int vnic = 1, grp = rx; 6473 6474 if (hw_resc->resv_tx_rings != bp->tx_nr_rings && 6475 bp->hwrm_spec_code >= 0x10601) 6476 return true; 6477 6478 /* Old firmware does not need RX ring reservations but we still 6479 * need to setup a default RSS map when needed. With new firmware 6480 * we go through RX ring reservations first and then set up the 6481 * RSS map for the successfully reserved RX rings when needed. 6482 */ 6483 if (!BNXT_NEW_RM(bp)) { 6484 bnxt_check_rss_tbl_no_rmgr(bp); 6485 return false; 6486 } 6487 if ((bp->flags & BNXT_FLAG_RFS) && !(bp->flags & BNXT_FLAG_CHIP_P5)) 6488 vnic = rx + 1; 6489 if (bp->flags & BNXT_FLAG_AGG_RINGS) 6490 rx <<= 1; 6491 stat = bnxt_get_func_stat_ctxs(bp); 6492 if (hw_resc->resv_rx_rings != rx || hw_resc->resv_cp_rings != cp || 6493 hw_resc->resv_vnics != vnic || hw_resc->resv_stat_ctxs != stat || 6494 (hw_resc->resv_hw_ring_grps != grp && 6495 !(bp->flags & BNXT_FLAG_CHIP_P5))) 6496 return true; 6497 if ((bp->flags & BNXT_FLAG_CHIP_P5) && BNXT_PF(bp) && 6498 hw_resc->resv_irqs != nq) 6499 return true; 6500 return false; 6501 } 6502 6503 static int __bnxt_reserve_rings(struct bnxt *bp) 6504 { 6505 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 6506 int cp = bnxt_nq_rings_in_use(bp); 6507 int tx = bp->tx_nr_rings; 6508 int rx = bp->rx_nr_rings; 6509 int grp, rx_rings, rc; 6510 int vnic = 1, stat; 6511 bool sh = false; 6512 6513 if (!bnxt_need_reserve_rings(bp)) 6514 return 0; 6515 6516 if (bp->flags & BNXT_FLAG_SHARED_RINGS) 6517 sh = true; 6518 if ((bp->flags & BNXT_FLAG_RFS) && !(bp->flags & BNXT_FLAG_CHIP_P5)) 6519 vnic = rx + 1; 6520 if (bp->flags & BNXT_FLAG_AGG_RINGS) 6521 rx <<= 1; 6522 grp = bp->rx_nr_rings; 6523 stat = bnxt_get_func_stat_ctxs(bp); 6524 6525 rc = bnxt_hwrm_reserve_rings(bp, tx, rx, grp, cp, stat, vnic); 6526 if (rc) 6527 return rc; 6528 6529 tx = hw_resc->resv_tx_rings; 6530 if (BNXT_NEW_RM(bp)) { 6531 rx = hw_resc->resv_rx_rings; 6532 cp = hw_resc->resv_irqs; 6533 grp = hw_resc->resv_hw_ring_grps; 6534 vnic = hw_resc->resv_vnics; 6535 stat = hw_resc->resv_stat_ctxs; 6536 } 6537 6538 rx_rings = rx; 6539 if (bp->flags & BNXT_FLAG_AGG_RINGS) { 6540 if (rx >= 2) { 6541 rx_rings = rx >> 1; 6542 } else { 6543 if (netif_running(bp->dev)) 6544 return -ENOMEM; 6545 6546 bp->flags &= ~BNXT_FLAG_AGG_RINGS; 6547 bp->flags |= BNXT_FLAG_NO_AGG_RINGS; 6548 bp->dev->hw_features &= ~NETIF_F_LRO; 6549 bp->dev->features &= ~NETIF_F_LRO; 6550 bnxt_set_ring_params(bp); 6551 } 6552 } 6553 rx_rings = min_t(int, rx_rings, grp); 6554 cp = min_t(int, cp, bp->cp_nr_rings); 6555 if (stat > bnxt_get_ulp_stat_ctxs(bp)) 6556 stat -= bnxt_get_ulp_stat_ctxs(bp); 6557 cp = min_t(int, cp, stat); 6558 rc = bnxt_trim_rings(bp, &rx_rings, &tx, cp, sh); 6559 if (bp->flags & BNXT_FLAG_AGG_RINGS) 6560 rx = rx_rings << 1; 6561 cp = sh ? max_t(int, tx, rx_rings) : tx + rx_rings; 6562 bp->tx_nr_rings = tx; 6563 6564 /* If we cannot reserve all the RX rings, reset the RSS map only 6565 * if absolutely necessary 6566 */ 6567 if (rx_rings != bp->rx_nr_rings) { 6568 netdev_warn(bp->dev, "Able to reserve only %d out of %d requested RX rings\n", 6569 rx_rings, bp->rx_nr_rings); 6570 if (netif_is_rxfh_configured(bp->dev) && 6571 (bnxt_get_nr_rss_ctxs(bp, bp->rx_nr_rings) != 6572 bnxt_get_nr_rss_ctxs(bp, rx_rings) || 6573 bnxt_get_max_rss_ring(bp) >= rx_rings)) { 6574 netdev_warn(bp->dev, "RSS table entries reverting to default\n"); 6575 bp->dev->priv_flags &= ~IFF_RXFH_CONFIGURED; 6576 } 6577 } 6578 bp->rx_nr_rings = rx_rings; 6579 bp->cp_nr_rings = cp; 6580 6581 if (!tx || !rx || !cp || !grp || !vnic || !stat) 6582 return -ENOMEM; 6583 6584 if (!netif_is_rxfh_configured(bp->dev)) 6585 bnxt_set_dflt_rss_indir_tbl(bp); 6586 6587 return rc; 6588 } 6589 6590 static int bnxt_hwrm_check_vf_rings(struct bnxt *bp, int tx_rings, int rx_rings, 6591 int ring_grps, int cp_rings, int stats, 6592 int vnics) 6593 { 6594 struct hwrm_func_vf_cfg_input *req; 6595 u32 flags; 6596 6597 if (!BNXT_NEW_RM(bp)) 6598 return 0; 6599 6600 req = __bnxt_hwrm_reserve_vf_rings(bp, tx_rings, rx_rings, ring_grps, 6601 cp_rings, stats, vnics); 6602 flags = FUNC_VF_CFG_REQ_FLAGS_TX_ASSETS_TEST | 6603 FUNC_VF_CFG_REQ_FLAGS_RX_ASSETS_TEST | 6604 FUNC_VF_CFG_REQ_FLAGS_CMPL_ASSETS_TEST | 6605 FUNC_VF_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST | 6606 FUNC_VF_CFG_REQ_FLAGS_VNIC_ASSETS_TEST | 6607 FUNC_VF_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST; 6608 if (!(bp->flags & BNXT_FLAG_CHIP_P5)) 6609 flags |= FUNC_VF_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST; 6610 6611 req->flags = cpu_to_le32(flags); 6612 return hwrm_req_send_silent(bp, req); 6613 } 6614 6615 static int bnxt_hwrm_check_pf_rings(struct bnxt *bp, int tx_rings, int rx_rings, 6616 int ring_grps, int cp_rings, int stats, 6617 int vnics) 6618 { 6619 struct hwrm_func_cfg_input *req; 6620 u32 flags; 6621 6622 req = __bnxt_hwrm_reserve_pf_rings(bp, tx_rings, rx_rings, ring_grps, 6623 cp_rings, stats, vnics); 6624 flags = FUNC_CFG_REQ_FLAGS_TX_ASSETS_TEST; 6625 if (BNXT_NEW_RM(bp)) { 6626 flags |= FUNC_CFG_REQ_FLAGS_RX_ASSETS_TEST | 6627 FUNC_CFG_REQ_FLAGS_CMPL_ASSETS_TEST | 6628 FUNC_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST | 6629 FUNC_CFG_REQ_FLAGS_VNIC_ASSETS_TEST; 6630 if (bp->flags & BNXT_FLAG_CHIP_P5) 6631 flags |= FUNC_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST | 6632 FUNC_CFG_REQ_FLAGS_NQ_ASSETS_TEST; 6633 else 6634 flags |= FUNC_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST; 6635 } 6636 6637 req->flags = cpu_to_le32(flags); 6638 return hwrm_req_send_silent(bp, req); 6639 } 6640 6641 static int bnxt_hwrm_check_rings(struct bnxt *bp, int tx_rings, int rx_rings, 6642 int ring_grps, int cp_rings, int stats, 6643 int vnics) 6644 { 6645 if (bp->hwrm_spec_code < 0x10801) 6646 return 0; 6647 6648 if (BNXT_PF(bp)) 6649 return bnxt_hwrm_check_pf_rings(bp, tx_rings, rx_rings, 6650 ring_grps, cp_rings, stats, 6651 vnics); 6652 6653 return bnxt_hwrm_check_vf_rings(bp, tx_rings, rx_rings, ring_grps, 6654 cp_rings, stats, vnics); 6655 } 6656 6657 static void bnxt_hwrm_coal_params_qcaps(struct bnxt *bp) 6658 { 6659 struct bnxt_coal_cap *coal_cap = &bp->coal_cap; 6660 struct hwrm_ring_aggint_qcaps_output *resp; 6661 struct hwrm_ring_aggint_qcaps_input *req; 6662 int rc; 6663 6664 coal_cap->cmpl_params = BNXT_LEGACY_COAL_CMPL_PARAMS; 6665 coal_cap->num_cmpl_dma_aggr_max = 63; 6666 coal_cap->num_cmpl_dma_aggr_during_int_max = 63; 6667 coal_cap->cmpl_aggr_dma_tmr_max = 65535; 6668 coal_cap->cmpl_aggr_dma_tmr_during_int_max = 65535; 6669 coal_cap->int_lat_tmr_min_max = 65535; 6670 coal_cap->int_lat_tmr_max_max = 65535; 6671 coal_cap->num_cmpl_aggr_int_max = 65535; 6672 coal_cap->timer_units = 80; 6673 6674 if (bp->hwrm_spec_code < 0x10902) 6675 return; 6676 6677 if (hwrm_req_init(bp, req, HWRM_RING_AGGINT_QCAPS)) 6678 return; 6679 6680 resp = hwrm_req_hold(bp, req); 6681 rc = hwrm_req_send_silent(bp, req); 6682 if (!rc) { 6683 coal_cap->cmpl_params = le32_to_cpu(resp->cmpl_params); 6684 coal_cap->nq_params = le32_to_cpu(resp->nq_params); 6685 coal_cap->num_cmpl_dma_aggr_max = 6686 le16_to_cpu(resp->num_cmpl_dma_aggr_max); 6687 coal_cap->num_cmpl_dma_aggr_during_int_max = 6688 le16_to_cpu(resp->num_cmpl_dma_aggr_during_int_max); 6689 coal_cap->cmpl_aggr_dma_tmr_max = 6690 le16_to_cpu(resp->cmpl_aggr_dma_tmr_max); 6691 coal_cap->cmpl_aggr_dma_tmr_during_int_max = 6692 le16_to_cpu(resp->cmpl_aggr_dma_tmr_during_int_max); 6693 coal_cap->int_lat_tmr_min_max = 6694 le16_to_cpu(resp->int_lat_tmr_min_max); 6695 coal_cap->int_lat_tmr_max_max = 6696 le16_to_cpu(resp->int_lat_tmr_max_max); 6697 coal_cap->num_cmpl_aggr_int_max = 6698 le16_to_cpu(resp->num_cmpl_aggr_int_max); 6699 coal_cap->timer_units = le16_to_cpu(resp->timer_units); 6700 } 6701 hwrm_req_drop(bp, req); 6702 } 6703 6704 static u16 bnxt_usec_to_coal_tmr(struct bnxt *bp, u16 usec) 6705 { 6706 struct bnxt_coal_cap *coal_cap = &bp->coal_cap; 6707 6708 return usec * 1000 / coal_cap->timer_units; 6709 } 6710 6711 static void bnxt_hwrm_set_coal_params(struct bnxt *bp, 6712 struct bnxt_coal *hw_coal, 6713 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req) 6714 { 6715 struct bnxt_coal_cap *coal_cap = &bp->coal_cap; 6716 u16 val, tmr, max, flags = hw_coal->flags; 6717 u32 cmpl_params = coal_cap->cmpl_params; 6718 6719 max = hw_coal->bufs_per_record * 128; 6720 if (hw_coal->budget) 6721 max = hw_coal->bufs_per_record * hw_coal->budget; 6722 max = min_t(u16, max, coal_cap->num_cmpl_aggr_int_max); 6723 6724 val = clamp_t(u16, hw_coal->coal_bufs, 1, max); 6725 req->num_cmpl_aggr_int = cpu_to_le16(val); 6726 6727 val = min_t(u16, val, coal_cap->num_cmpl_dma_aggr_max); 6728 req->num_cmpl_dma_aggr = cpu_to_le16(val); 6729 6730 val = clamp_t(u16, hw_coal->coal_bufs_irq, 1, 6731 coal_cap->num_cmpl_dma_aggr_during_int_max); 6732 req->num_cmpl_dma_aggr_during_int = cpu_to_le16(val); 6733 6734 tmr = bnxt_usec_to_coal_tmr(bp, hw_coal->coal_ticks); 6735 tmr = clamp_t(u16, tmr, 1, coal_cap->int_lat_tmr_max_max); 6736 req->int_lat_tmr_max = cpu_to_le16(tmr); 6737 6738 /* min timer set to 1/2 of interrupt timer */ 6739 if (cmpl_params & RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN) { 6740 val = tmr / 2; 6741 val = clamp_t(u16, val, 1, coal_cap->int_lat_tmr_min_max); 6742 req->int_lat_tmr_min = cpu_to_le16(val); 6743 req->enables |= cpu_to_le16(BNXT_COAL_CMPL_MIN_TMR_ENABLE); 6744 } 6745 6746 /* buf timer set to 1/4 of interrupt timer */ 6747 val = clamp_t(u16, tmr / 4, 1, coal_cap->cmpl_aggr_dma_tmr_max); 6748 req->cmpl_aggr_dma_tmr = cpu_to_le16(val); 6749 6750 if (cmpl_params & 6751 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT) { 6752 tmr = bnxt_usec_to_coal_tmr(bp, hw_coal->coal_ticks_irq); 6753 val = clamp_t(u16, tmr, 1, 6754 coal_cap->cmpl_aggr_dma_tmr_during_int_max); 6755 req->cmpl_aggr_dma_tmr_during_int = cpu_to_le16(val); 6756 req->enables |= 6757 cpu_to_le16(BNXT_COAL_CMPL_AGGR_TMR_DURING_INT_ENABLE); 6758 } 6759 6760 if ((cmpl_params & RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE) && 6761 hw_coal->idle_thresh && hw_coal->coal_ticks < hw_coal->idle_thresh) 6762 flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE; 6763 req->flags = cpu_to_le16(flags); 6764 req->enables |= cpu_to_le16(BNXT_COAL_CMPL_ENABLES); 6765 } 6766 6767 static int __bnxt_hwrm_set_coal_nq(struct bnxt *bp, struct bnxt_napi *bnapi, 6768 struct bnxt_coal *hw_coal) 6769 { 6770 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req; 6771 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 6772 struct bnxt_coal_cap *coal_cap = &bp->coal_cap; 6773 u32 nq_params = coal_cap->nq_params; 6774 u16 tmr; 6775 int rc; 6776 6777 if (!(nq_params & RING_AGGINT_QCAPS_RESP_NQ_PARAMS_INT_LAT_TMR_MIN)) 6778 return 0; 6779 6780 rc = hwrm_req_init(bp, req, HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS); 6781 if (rc) 6782 return rc; 6783 6784 req->ring_id = cpu_to_le16(cpr->cp_ring_struct.fw_ring_id); 6785 req->flags = 6786 cpu_to_le16(RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_IS_NQ); 6787 6788 tmr = bnxt_usec_to_coal_tmr(bp, hw_coal->coal_ticks) / 2; 6789 tmr = clamp_t(u16, tmr, 1, coal_cap->int_lat_tmr_min_max); 6790 req->int_lat_tmr_min = cpu_to_le16(tmr); 6791 req->enables |= cpu_to_le16(BNXT_COAL_CMPL_MIN_TMR_ENABLE); 6792 return hwrm_req_send(bp, req); 6793 } 6794 6795 int bnxt_hwrm_set_ring_coal(struct bnxt *bp, struct bnxt_napi *bnapi) 6796 { 6797 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req_rx; 6798 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 6799 struct bnxt_coal coal; 6800 int rc; 6801 6802 /* Tick values in micro seconds. 6803 * 1 coal_buf x bufs_per_record = 1 completion record. 6804 */ 6805 memcpy(&coal, &bp->rx_coal, sizeof(struct bnxt_coal)); 6806 6807 coal.coal_ticks = cpr->rx_ring_coal.coal_ticks; 6808 coal.coal_bufs = cpr->rx_ring_coal.coal_bufs; 6809 6810 if (!bnapi->rx_ring) 6811 return -ENODEV; 6812 6813 rc = hwrm_req_init(bp, req_rx, HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS); 6814 if (rc) 6815 return rc; 6816 6817 bnxt_hwrm_set_coal_params(bp, &coal, req_rx); 6818 6819 req_rx->ring_id = cpu_to_le16(bnxt_cp_ring_for_rx(bp, bnapi->rx_ring)); 6820 6821 return hwrm_req_send(bp, req_rx); 6822 } 6823 6824 int bnxt_hwrm_set_coal(struct bnxt *bp) 6825 { 6826 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req_rx, *req_tx, 6827 *req; 6828 int i, rc; 6829 6830 rc = hwrm_req_init(bp, req_rx, HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS); 6831 if (rc) 6832 return rc; 6833 6834 rc = hwrm_req_init(bp, req_tx, HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS); 6835 if (rc) { 6836 hwrm_req_drop(bp, req_rx); 6837 return rc; 6838 } 6839 6840 bnxt_hwrm_set_coal_params(bp, &bp->rx_coal, req_rx); 6841 bnxt_hwrm_set_coal_params(bp, &bp->tx_coal, req_tx); 6842 6843 hwrm_req_hold(bp, req_rx); 6844 hwrm_req_hold(bp, req_tx); 6845 for (i = 0; i < bp->cp_nr_rings; i++) { 6846 struct bnxt_napi *bnapi = bp->bnapi[i]; 6847 struct bnxt_coal *hw_coal; 6848 u16 ring_id; 6849 6850 req = req_rx; 6851 if (!bnapi->rx_ring) { 6852 ring_id = bnxt_cp_ring_for_tx(bp, bnapi->tx_ring); 6853 req = req_tx; 6854 } else { 6855 ring_id = bnxt_cp_ring_for_rx(bp, bnapi->rx_ring); 6856 } 6857 req->ring_id = cpu_to_le16(ring_id); 6858 6859 rc = hwrm_req_send(bp, req); 6860 if (rc) 6861 break; 6862 6863 if (!(bp->flags & BNXT_FLAG_CHIP_P5)) 6864 continue; 6865 6866 if (bnapi->rx_ring && bnapi->tx_ring) { 6867 req = req_tx; 6868 ring_id = bnxt_cp_ring_for_tx(bp, bnapi->tx_ring); 6869 req->ring_id = cpu_to_le16(ring_id); 6870 rc = hwrm_req_send(bp, req); 6871 if (rc) 6872 break; 6873 } 6874 if (bnapi->rx_ring) 6875 hw_coal = &bp->rx_coal; 6876 else 6877 hw_coal = &bp->tx_coal; 6878 __bnxt_hwrm_set_coal_nq(bp, bnapi, hw_coal); 6879 } 6880 hwrm_req_drop(bp, req_rx); 6881 hwrm_req_drop(bp, req_tx); 6882 return rc; 6883 } 6884 6885 static void bnxt_hwrm_stat_ctx_free(struct bnxt *bp) 6886 { 6887 struct hwrm_stat_ctx_clr_stats_input *req0 = NULL; 6888 struct hwrm_stat_ctx_free_input *req; 6889 int i; 6890 6891 if (!bp->bnapi) 6892 return; 6893 6894 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 6895 return; 6896 6897 if (hwrm_req_init(bp, req, HWRM_STAT_CTX_FREE)) 6898 return; 6899 if (BNXT_FW_MAJ(bp) <= 20) { 6900 if (hwrm_req_init(bp, req0, HWRM_STAT_CTX_CLR_STATS)) { 6901 hwrm_req_drop(bp, req); 6902 return; 6903 } 6904 hwrm_req_hold(bp, req0); 6905 } 6906 hwrm_req_hold(bp, req); 6907 for (i = 0; i < bp->cp_nr_rings; i++) { 6908 struct bnxt_napi *bnapi = bp->bnapi[i]; 6909 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 6910 6911 if (cpr->hw_stats_ctx_id != INVALID_STATS_CTX_ID) { 6912 req->stat_ctx_id = cpu_to_le32(cpr->hw_stats_ctx_id); 6913 if (req0) { 6914 req0->stat_ctx_id = req->stat_ctx_id; 6915 hwrm_req_send(bp, req0); 6916 } 6917 hwrm_req_send(bp, req); 6918 6919 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID; 6920 } 6921 } 6922 hwrm_req_drop(bp, req); 6923 if (req0) 6924 hwrm_req_drop(bp, req0); 6925 } 6926 6927 static int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp) 6928 { 6929 struct hwrm_stat_ctx_alloc_output *resp; 6930 struct hwrm_stat_ctx_alloc_input *req; 6931 int rc, i; 6932 6933 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 6934 return 0; 6935 6936 rc = hwrm_req_init(bp, req, HWRM_STAT_CTX_ALLOC); 6937 if (rc) 6938 return rc; 6939 6940 req->stats_dma_length = cpu_to_le16(bp->hw_ring_stats_size); 6941 req->update_period_ms = cpu_to_le32(bp->stats_coal_ticks / 1000); 6942 6943 resp = hwrm_req_hold(bp, req); 6944 for (i = 0; i < bp->cp_nr_rings; i++) { 6945 struct bnxt_napi *bnapi = bp->bnapi[i]; 6946 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 6947 6948 req->stats_dma_addr = cpu_to_le64(cpr->stats.hw_stats_map); 6949 6950 rc = hwrm_req_send(bp, req); 6951 if (rc) 6952 break; 6953 6954 cpr->hw_stats_ctx_id = le32_to_cpu(resp->stat_ctx_id); 6955 6956 bp->grp_info[i].fw_stats_ctx = cpr->hw_stats_ctx_id; 6957 } 6958 hwrm_req_drop(bp, req); 6959 return rc; 6960 } 6961 6962 static int bnxt_hwrm_func_qcfg(struct bnxt *bp) 6963 { 6964 struct hwrm_func_qcfg_output *resp; 6965 struct hwrm_func_qcfg_input *req; 6966 u32 min_db_offset = 0; 6967 u16 flags; 6968 int rc; 6969 6970 rc = hwrm_req_init(bp, req, HWRM_FUNC_QCFG); 6971 if (rc) 6972 return rc; 6973 6974 req->fid = cpu_to_le16(0xffff); 6975 resp = hwrm_req_hold(bp, req); 6976 rc = hwrm_req_send(bp, req); 6977 if (rc) 6978 goto func_qcfg_exit; 6979 6980 #ifdef CONFIG_BNXT_SRIOV 6981 if (BNXT_VF(bp)) { 6982 struct bnxt_vf_info *vf = &bp->vf; 6983 6984 vf->vlan = le16_to_cpu(resp->vlan) & VLAN_VID_MASK; 6985 } else { 6986 bp->pf.registered_vfs = le16_to_cpu(resp->registered_vfs); 6987 } 6988 #endif 6989 flags = le16_to_cpu(resp->flags); 6990 if (flags & (FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED | 6991 FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED)) { 6992 bp->fw_cap |= BNXT_FW_CAP_LLDP_AGENT; 6993 if (flags & FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED) 6994 bp->fw_cap |= BNXT_FW_CAP_DCBX_AGENT; 6995 } 6996 if (BNXT_PF(bp) && (flags & FUNC_QCFG_RESP_FLAGS_MULTI_HOST)) 6997 bp->flags |= BNXT_FLAG_MULTI_HOST; 6998 6999 if (flags & FUNC_QCFG_RESP_FLAGS_RING_MONITOR_ENABLED) 7000 bp->fw_cap |= BNXT_FW_CAP_RING_MONITOR; 7001 7002 switch (resp->port_partition_type) { 7003 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0: 7004 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5: 7005 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0: 7006 bp->port_partition_type = resp->port_partition_type; 7007 break; 7008 } 7009 if (bp->hwrm_spec_code < 0x10707 || 7010 resp->evb_mode == FUNC_QCFG_RESP_EVB_MODE_VEB) 7011 bp->br_mode = BRIDGE_MODE_VEB; 7012 else if (resp->evb_mode == FUNC_QCFG_RESP_EVB_MODE_VEPA) 7013 bp->br_mode = BRIDGE_MODE_VEPA; 7014 else 7015 bp->br_mode = BRIDGE_MODE_UNDEF; 7016 7017 bp->max_mtu = le16_to_cpu(resp->max_mtu_configured); 7018 if (!bp->max_mtu) 7019 bp->max_mtu = BNXT_MAX_MTU; 7020 7021 if (bp->db_size) 7022 goto func_qcfg_exit; 7023 7024 if (bp->flags & BNXT_FLAG_CHIP_P5) { 7025 if (BNXT_PF(bp)) 7026 min_db_offset = DB_PF_OFFSET_P5; 7027 else 7028 min_db_offset = DB_VF_OFFSET_P5; 7029 } 7030 bp->db_size = PAGE_ALIGN(le16_to_cpu(resp->l2_doorbell_bar_size_kb) * 7031 1024); 7032 if (!bp->db_size || bp->db_size > pci_resource_len(bp->pdev, 2) || 7033 bp->db_size <= min_db_offset) 7034 bp->db_size = pci_resource_len(bp->pdev, 2); 7035 7036 func_qcfg_exit: 7037 hwrm_req_drop(bp, req); 7038 return rc; 7039 } 7040 7041 static void bnxt_init_ctx_initializer(struct bnxt_ctx_mem_info *ctx, 7042 struct hwrm_func_backing_store_qcaps_output *resp) 7043 { 7044 struct bnxt_mem_init *mem_init; 7045 u16 init_mask; 7046 u8 init_val; 7047 u8 *offset; 7048 int i; 7049 7050 init_val = resp->ctx_kind_initializer; 7051 init_mask = le16_to_cpu(resp->ctx_init_mask); 7052 offset = &resp->qp_init_offset; 7053 mem_init = &ctx->mem_init[BNXT_CTX_MEM_INIT_QP]; 7054 for (i = 0; i < BNXT_CTX_MEM_INIT_MAX; i++, mem_init++, offset++) { 7055 mem_init->init_val = init_val; 7056 mem_init->offset = BNXT_MEM_INVALID_OFFSET; 7057 if (!init_mask) 7058 continue; 7059 if (i == BNXT_CTX_MEM_INIT_STAT) 7060 offset = &resp->stat_init_offset; 7061 if (init_mask & (1 << i)) 7062 mem_init->offset = *offset * 4; 7063 else 7064 mem_init->init_val = 0; 7065 } 7066 ctx->mem_init[BNXT_CTX_MEM_INIT_QP].size = ctx->qp_entry_size; 7067 ctx->mem_init[BNXT_CTX_MEM_INIT_SRQ].size = ctx->srq_entry_size; 7068 ctx->mem_init[BNXT_CTX_MEM_INIT_CQ].size = ctx->cq_entry_size; 7069 ctx->mem_init[BNXT_CTX_MEM_INIT_VNIC].size = ctx->vnic_entry_size; 7070 ctx->mem_init[BNXT_CTX_MEM_INIT_STAT].size = ctx->stat_entry_size; 7071 ctx->mem_init[BNXT_CTX_MEM_INIT_MRAV].size = ctx->mrav_entry_size; 7072 } 7073 7074 static int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp) 7075 { 7076 struct hwrm_func_backing_store_qcaps_output *resp; 7077 struct hwrm_func_backing_store_qcaps_input *req; 7078 int rc; 7079 7080 if (bp->hwrm_spec_code < 0x10902 || BNXT_VF(bp) || bp->ctx) 7081 return 0; 7082 7083 rc = hwrm_req_init(bp, req, HWRM_FUNC_BACKING_STORE_QCAPS); 7084 if (rc) 7085 return rc; 7086 7087 resp = hwrm_req_hold(bp, req); 7088 rc = hwrm_req_send_silent(bp, req); 7089 if (!rc) { 7090 struct bnxt_ctx_pg_info *ctx_pg; 7091 struct bnxt_ctx_mem_info *ctx; 7092 int i, tqm_rings; 7093 7094 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); 7095 if (!ctx) { 7096 rc = -ENOMEM; 7097 goto ctx_err; 7098 } 7099 ctx->qp_max_entries = le32_to_cpu(resp->qp_max_entries); 7100 ctx->qp_min_qp1_entries = le16_to_cpu(resp->qp_min_qp1_entries); 7101 ctx->qp_max_l2_entries = le16_to_cpu(resp->qp_max_l2_entries); 7102 ctx->qp_entry_size = le16_to_cpu(resp->qp_entry_size); 7103 ctx->srq_max_l2_entries = le16_to_cpu(resp->srq_max_l2_entries); 7104 ctx->srq_max_entries = le32_to_cpu(resp->srq_max_entries); 7105 ctx->srq_entry_size = le16_to_cpu(resp->srq_entry_size); 7106 ctx->cq_max_l2_entries = le16_to_cpu(resp->cq_max_l2_entries); 7107 ctx->cq_max_entries = le32_to_cpu(resp->cq_max_entries); 7108 ctx->cq_entry_size = le16_to_cpu(resp->cq_entry_size); 7109 ctx->vnic_max_vnic_entries = 7110 le16_to_cpu(resp->vnic_max_vnic_entries); 7111 ctx->vnic_max_ring_table_entries = 7112 le16_to_cpu(resp->vnic_max_ring_table_entries); 7113 ctx->vnic_entry_size = le16_to_cpu(resp->vnic_entry_size); 7114 ctx->stat_max_entries = le32_to_cpu(resp->stat_max_entries); 7115 ctx->stat_entry_size = le16_to_cpu(resp->stat_entry_size); 7116 ctx->tqm_entry_size = le16_to_cpu(resp->tqm_entry_size); 7117 ctx->tqm_min_entries_per_ring = 7118 le32_to_cpu(resp->tqm_min_entries_per_ring); 7119 ctx->tqm_max_entries_per_ring = 7120 le32_to_cpu(resp->tqm_max_entries_per_ring); 7121 ctx->tqm_entries_multiple = resp->tqm_entries_multiple; 7122 if (!ctx->tqm_entries_multiple) 7123 ctx->tqm_entries_multiple = 1; 7124 ctx->mrav_max_entries = le32_to_cpu(resp->mrav_max_entries); 7125 ctx->mrav_entry_size = le16_to_cpu(resp->mrav_entry_size); 7126 ctx->mrav_num_entries_units = 7127 le16_to_cpu(resp->mrav_num_entries_units); 7128 ctx->tim_entry_size = le16_to_cpu(resp->tim_entry_size); 7129 ctx->tim_max_entries = le32_to_cpu(resp->tim_max_entries); 7130 7131 bnxt_init_ctx_initializer(ctx, resp); 7132 7133 ctx->tqm_fp_rings_count = resp->tqm_fp_rings_count; 7134 if (!ctx->tqm_fp_rings_count) 7135 ctx->tqm_fp_rings_count = bp->max_q; 7136 else if (ctx->tqm_fp_rings_count > BNXT_MAX_TQM_FP_RINGS) 7137 ctx->tqm_fp_rings_count = BNXT_MAX_TQM_FP_RINGS; 7138 7139 tqm_rings = ctx->tqm_fp_rings_count + BNXT_MAX_TQM_SP_RINGS; 7140 ctx_pg = kcalloc(tqm_rings, sizeof(*ctx_pg), GFP_KERNEL); 7141 if (!ctx_pg) { 7142 kfree(ctx); 7143 rc = -ENOMEM; 7144 goto ctx_err; 7145 } 7146 for (i = 0; i < tqm_rings; i++, ctx_pg++) 7147 ctx->tqm_mem[i] = ctx_pg; 7148 bp->ctx = ctx; 7149 } else { 7150 rc = 0; 7151 } 7152 ctx_err: 7153 hwrm_req_drop(bp, req); 7154 return rc; 7155 } 7156 7157 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem, u8 *pg_attr, 7158 __le64 *pg_dir) 7159 { 7160 if (!rmem->nr_pages) 7161 return; 7162 7163 BNXT_SET_CTX_PAGE_ATTR(*pg_attr); 7164 if (rmem->depth >= 1) { 7165 if (rmem->depth == 2) 7166 *pg_attr |= 2; 7167 else 7168 *pg_attr |= 1; 7169 *pg_dir = cpu_to_le64(rmem->pg_tbl_map); 7170 } else { 7171 *pg_dir = cpu_to_le64(rmem->dma_arr[0]); 7172 } 7173 } 7174 7175 #define FUNC_BACKING_STORE_CFG_REQ_DFLT_ENABLES \ 7176 (FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP | \ 7177 FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ | \ 7178 FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ | \ 7179 FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC | \ 7180 FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT) 7181 7182 static int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, u32 enables) 7183 { 7184 struct hwrm_func_backing_store_cfg_input *req; 7185 struct bnxt_ctx_mem_info *ctx = bp->ctx; 7186 struct bnxt_ctx_pg_info *ctx_pg; 7187 void **__req = (void **)&req; 7188 u32 req_len = sizeof(*req); 7189 __le32 *num_entries; 7190 __le64 *pg_dir; 7191 u32 flags = 0; 7192 u8 *pg_attr; 7193 u32 ena; 7194 int rc; 7195 int i; 7196 7197 if (!ctx) 7198 return 0; 7199 7200 if (req_len > bp->hwrm_max_ext_req_len) 7201 req_len = BNXT_BACKING_STORE_CFG_LEGACY_LEN; 7202 rc = __hwrm_req_init(bp, __req, HWRM_FUNC_BACKING_STORE_CFG, req_len); 7203 if (rc) 7204 return rc; 7205 7206 req->enables = cpu_to_le32(enables); 7207 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP) { 7208 ctx_pg = &ctx->qp_mem; 7209 req->qp_num_entries = cpu_to_le32(ctx_pg->entries); 7210 req->qp_num_qp1_entries = cpu_to_le16(ctx->qp_min_qp1_entries); 7211 req->qp_num_l2_entries = cpu_to_le16(ctx->qp_max_l2_entries); 7212 req->qp_entry_size = cpu_to_le16(ctx->qp_entry_size); 7213 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, 7214 &req->qpc_pg_size_qpc_lvl, 7215 &req->qpc_page_dir); 7216 } 7217 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ) { 7218 ctx_pg = &ctx->srq_mem; 7219 req->srq_num_entries = cpu_to_le32(ctx_pg->entries); 7220 req->srq_num_l2_entries = cpu_to_le16(ctx->srq_max_l2_entries); 7221 req->srq_entry_size = cpu_to_le16(ctx->srq_entry_size); 7222 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, 7223 &req->srq_pg_size_srq_lvl, 7224 &req->srq_page_dir); 7225 } 7226 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ) { 7227 ctx_pg = &ctx->cq_mem; 7228 req->cq_num_entries = cpu_to_le32(ctx_pg->entries); 7229 req->cq_num_l2_entries = cpu_to_le16(ctx->cq_max_l2_entries); 7230 req->cq_entry_size = cpu_to_le16(ctx->cq_entry_size); 7231 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, 7232 &req->cq_pg_size_cq_lvl, 7233 &req->cq_page_dir); 7234 } 7235 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC) { 7236 ctx_pg = &ctx->vnic_mem; 7237 req->vnic_num_vnic_entries = 7238 cpu_to_le16(ctx->vnic_max_vnic_entries); 7239 req->vnic_num_ring_table_entries = 7240 cpu_to_le16(ctx->vnic_max_ring_table_entries); 7241 req->vnic_entry_size = cpu_to_le16(ctx->vnic_entry_size); 7242 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, 7243 &req->vnic_pg_size_vnic_lvl, 7244 &req->vnic_page_dir); 7245 } 7246 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT) { 7247 ctx_pg = &ctx->stat_mem; 7248 req->stat_num_entries = cpu_to_le32(ctx->stat_max_entries); 7249 req->stat_entry_size = cpu_to_le16(ctx->stat_entry_size); 7250 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, 7251 &req->stat_pg_size_stat_lvl, 7252 &req->stat_page_dir); 7253 } 7254 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV) { 7255 ctx_pg = &ctx->mrav_mem; 7256 req->mrav_num_entries = cpu_to_le32(ctx_pg->entries); 7257 if (ctx->mrav_num_entries_units) 7258 flags |= 7259 FUNC_BACKING_STORE_CFG_REQ_FLAGS_MRAV_RESERVATION_SPLIT; 7260 req->mrav_entry_size = cpu_to_le16(ctx->mrav_entry_size); 7261 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, 7262 &req->mrav_pg_size_mrav_lvl, 7263 &req->mrav_page_dir); 7264 } 7265 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM) { 7266 ctx_pg = &ctx->tim_mem; 7267 req->tim_num_entries = cpu_to_le32(ctx_pg->entries); 7268 req->tim_entry_size = cpu_to_le16(ctx->tim_entry_size); 7269 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, 7270 &req->tim_pg_size_tim_lvl, 7271 &req->tim_page_dir); 7272 } 7273 for (i = 0, num_entries = &req->tqm_sp_num_entries, 7274 pg_attr = &req->tqm_sp_pg_size_tqm_sp_lvl, 7275 pg_dir = &req->tqm_sp_page_dir, 7276 ena = FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP; 7277 i < BNXT_MAX_TQM_RINGS; 7278 i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) { 7279 if (!(enables & ena)) 7280 continue; 7281 7282 req->tqm_entry_size = cpu_to_le16(ctx->tqm_entry_size); 7283 ctx_pg = ctx->tqm_mem[i]; 7284 *num_entries = cpu_to_le32(ctx_pg->entries); 7285 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir); 7286 } 7287 req->flags = cpu_to_le32(flags); 7288 return hwrm_req_send(bp, req); 7289 } 7290 7291 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp, 7292 struct bnxt_ctx_pg_info *ctx_pg) 7293 { 7294 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem; 7295 7296 rmem->page_size = BNXT_PAGE_SIZE; 7297 rmem->pg_arr = ctx_pg->ctx_pg_arr; 7298 rmem->dma_arr = ctx_pg->ctx_dma_arr; 7299 rmem->flags = BNXT_RMEM_VALID_PTE_FLAG; 7300 if (rmem->depth >= 1) 7301 rmem->flags |= BNXT_RMEM_USE_FULL_PAGE_FLAG; 7302 return bnxt_alloc_ring(bp, rmem); 7303 } 7304 7305 static int bnxt_alloc_ctx_pg_tbls(struct bnxt *bp, 7306 struct bnxt_ctx_pg_info *ctx_pg, u32 mem_size, 7307 u8 depth, struct bnxt_mem_init *mem_init) 7308 { 7309 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem; 7310 int rc; 7311 7312 if (!mem_size) 7313 return -EINVAL; 7314 7315 ctx_pg->nr_pages = DIV_ROUND_UP(mem_size, BNXT_PAGE_SIZE); 7316 if (ctx_pg->nr_pages > MAX_CTX_TOTAL_PAGES) { 7317 ctx_pg->nr_pages = 0; 7318 return -EINVAL; 7319 } 7320 if (ctx_pg->nr_pages > MAX_CTX_PAGES || depth > 1) { 7321 int nr_tbls, i; 7322 7323 rmem->depth = 2; 7324 ctx_pg->ctx_pg_tbl = kcalloc(MAX_CTX_PAGES, sizeof(ctx_pg), 7325 GFP_KERNEL); 7326 if (!ctx_pg->ctx_pg_tbl) 7327 return -ENOMEM; 7328 nr_tbls = DIV_ROUND_UP(ctx_pg->nr_pages, MAX_CTX_PAGES); 7329 rmem->nr_pages = nr_tbls; 7330 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg); 7331 if (rc) 7332 return rc; 7333 for (i = 0; i < nr_tbls; i++) { 7334 struct bnxt_ctx_pg_info *pg_tbl; 7335 7336 pg_tbl = kzalloc(sizeof(*pg_tbl), GFP_KERNEL); 7337 if (!pg_tbl) 7338 return -ENOMEM; 7339 ctx_pg->ctx_pg_tbl[i] = pg_tbl; 7340 rmem = &pg_tbl->ring_mem; 7341 rmem->pg_tbl = ctx_pg->ctx_pg_arr[i]; 7342 rmem->pg_tbl_map = ctx_pg->ctx_dma_arr[i]; 7343 rmem->depth = 1; 7344 rmem->nr_pages = MAX_CTX_PAGES; 7345 rmem->mem_init = mem_init; 7346 if (i == (nr_tbls - 1)) { 7347 int rem = ctx_pg->nr_pages % MAX_CTX_PAGES; 7348 7349 if (rem) 7350 rmem->nr_pages = rem; 7351 } 7352 rc = bnxt_alloc_ctx_mem_blk(bp, pg_tbl); 7353 if (rc) 7354 break; 7355 } 7356 } else { 7357 rmem->nr_pages = DIV_ROUND_UP(mem_size, BNXT_PAGE_SIZE); 7358 if (rmem->nr_pages > 1 || depth) 7359 rmem->depth = 1; 7360 rmem->mem_init = mem_init; 7361 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg); 7362 } 7363 return rc; 7364 } 7365 7366 static void bnxt_free_ctx_pg_tbls(struct bnxt *bp, 7367 struct bnxt_ctx_pg_info *ctx_pg) 7368 { 7369 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem; 7370 7371 if (rmem->depth > 1 || ctx_pg->nr_pages > MAX_CTX_PAGES || 7372 ctx_pg->ctx_pg_tbl) { 7373 int i, nr_tbls = rmem->nr_pages; 7374 7375 for (i = 0; i < nr_tbls; i++) { 7376 struct bnxt_ctx_pg_info *pg_tbl; 7377 struct bnxt_ring_mem_info *rmem2; 7378 7379 pg_tbl = ctx_pg->ctx_pg_tbl[i]; 7380 if (!pg_tbl) 7381 continue; 7382 rmem2 = &pg_tbl->ring_mem; 7383 bnxt_free_ring(bp, rmem2); 7384 ctx_pg->ctx_pg_arr[i] = NULL; 7385 kfree(pg_tbl); 7386 ctx_pg->ctx_pg_tbl[i] = NULL; 7387 } 7388 kfree(ctx_pg->ctx_pg_tbl); 7389 ctx_pg->ctx_pg_tbl = NULL; 7390 } 7391 bnxt_free_ring(bp, rmem); 7392 ctx_pg->nr_pages = 0; 7393 } 7394 7395 void bnxt_free_ctx_mem(struct bnxt *bp) 7396 { 7397 struct bnxt_ctx_mem_info *ctx = bp->ctx; 7398 int i; 7399 7400 if (!ctx) 7401 return; 7402 7403 if (ctx->tqm_mem[0]) { 7404 for (i = 0; i < ctx->tqm_fp_rings_count + 1; i++) 7405 bnxt_free_ctx_pg_tbls(bp, ctx->tqm_mem[i]); 7406 kfree(ctx->tqm_mem[0]); 7407 ctx->tqm_mem[0] = NULL; 7408 } 7409 7410 bnxt_free_ctx_pg_tbls(bp, &ctx->tim_mem); 7411 bnxt_free_ctx_pg_tbls(bp, &ctx->mrav_mem); 7412 bnxt_free_ctx_pg_tbls(bp, &ctx->stat_mem); 7413 bnxt_free_ctx_pg_tbls(bp, &ctx->vnic_mem); 7414 bnxt_free_ctx_pg_tbls(bp, &ctx->cq_mem); 7415 bnxt_free_ctx_pg_tbls(bp, &ctx->srq_mem); 7416 bnxt_free_ctx_pg_tbls(bp, &ctx->qp_mem); 7417 ctx->flags &= ~BNXT_CTX_FLAG_INITED; 7418 } 7419 7420 static int bnxt_alloc_ctx_mem(struct bnxt *bp) 7421 { 7422 struct bnxt_ctx_pg_info *ctx_pg; 7423 struct bnxt_ctx_mem_info *ctx; 7424 struct bnxt_mem_init *init; 7425 u32 mem_size, ena, entries; 7426 u32 entries_sp, min; 7427 u32 num_mr, num_ah; 7428 u32 extra_srqs = 0; 7429 u32 extra_qps = 0; 7430 u8 pg_lvl = 1; 7431 int i, rc; 7432 7433 rc = bnxt_hwrm_func_backing_store_qcaps(bp); 7434 if (rc) { 7435 netdev_err(bp->dev, "Failed querying context mem capability, rc = %d.\n", 7436 rc); 7437 return rc; 7438 } 7439 ctx = bp->ctx; 7440 if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED)) 7441 return 0; 7442 7443 if ((bp->flags & BNXT_FLAG_ROCE_CAP) && !is_kdump_kernel()) { 7444 pg_lvl = 2; 7445 extra_qps = 65536; 7446 extra_srqs = 8192; 7447 } 7448 7449 ctx_pg = &ctx->qp_mem; 7450 ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries + 7451 extra_qps; 7452 if (ctx->qp_entry_size) { 7453 mem_size = ctx->qp_entry_size * ctx_pg->entries; 7454 init = &ctx->mem_init[BNXT_CTX_MEM_INIT_QP]; 7455 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, pg_lvl, init); 7456 if (rc) 7457 return rc; 7458 } 7459 7460 ctx_pg = &ctx->srq_mem; 7461 ctx_pg->entries = ctx->srq_max_l2_entries + extra_srqs; 7462 if (ctx->srq_entry_size) { 7463 mem_size = ctx->srq_entry_size * ctx_pg->entries; 7464 init = &ctx->mem_init[BNXT_CTX_MEM_INIT_SRQ]; 7465 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, pg_lvl, init); 7466 if (rc) 7467 return rc; 7468 } 7469 7470 ctx_pg = &ctx->cq_mem; 7471 ctx_pg->entries = ctx->cq_max_l2_entries + extra_qps * 2; 7472 if (ctx->cq_entry_size) { 7473 mem_size = ctx->cq_entry_size * ctx_pg->entries; 7474 init = &ctx->mem_init[BNXT_CTX_MEM_INIT_CQ]; 7475 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, pg_lvl, init); 7476 if (rc) 7477 return rc; 7478 } 7479 7480 ctx_pg = &ctx->vnic_mem; 7481 ctx_pg->entries = ctx->vnic_max_vnic_entries + 7482 ctx->vnic_max_ring_table_entries; 7483 if (ctx->vnic_entry_size) { 7484 mem_size = ctx->vnic_entry_size * ctx_pg->entries; 7485 init = &ctx->mem_init[BNXT_CTX_MEM_INIT_VNIC]; 7486 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1, init); 7487 if (rc) 7488 return rc; 7489 } 7490 7491 ctx_pg = &ctx->stat_mem; 7492 ctx_pg->entries = ctx->stat_max_entries; 7493 if (ctx->stat_entry_size) { 7494 mem_size = ctx->stat_entry_size * ctx_pg->entries; 7495 init = &ctx->mem_init[BNXT_CTX_MEM_INIT_STAT]; 7496 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1, init); 7497 if (rc) 7498 return rc; 7499 } 7500 7501 ena = 0; 7502 if (!(bp->flags & BNXT_FLAG_ROCE_CAP)) 7503 goto skip_rdma; 7504 7505 ctx_pg = &ctx->mrav_mem; 7506 /* 128K extra is needed to accommodate static AH context 7507 * allocation by f/w. 7508 */ 7509 num_mr = 1024 * 256; 7510 num_ah = 1024 * 128; 7511 ctx_pg->entries = num_mr + num_ah; 7512 if (ctx->mrav_entry_size) { 7513 mem_size = ctx->mrav_entry_size * ctx_pg->entries; 7514 init = &ctx->mem_init[BNXT_CTX_MEM_INIT_MRAV]; 7515 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 2, init); 7516 if (rc) 7517 return rc; 7518 } 7519 ena = FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV; 7520 if (ctx->mrav_num_entries_units) 7521 ctx_pg->entries = 7522 ((num_mr / ctx->mrav_num_entries_units) << 16) | 7523 (num_ah / ctx->mrav_num_entries_units); 7524 7525 ctx_pg = &ctx->tim_mem; 7526 ctx_pg->entries = ctx->qp_mem.entries; 7527 if (ctx->tim_entry_size) { 7528 mem_size = ctx->tim_entry_size * ctx_pg->entries; 7529 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1, NULL); 7530 if (rc) 7531 return rc; 7532 } 7533 ena |= FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM; 7534 7535 skip_rdma: 7536 min = ctx->tqm_min_entries_per_ring; 7537 entries_sp = ctx->vnic_max_vnic_entries + ctx->qp_max_l2_entries + 7538 2 * (extra_qps + ctx->qp_min_qp1_entries) + min; 7539 entries_sp = roundup(entries_sp, ctx->tqm_entries_multiple); 7540 entries = ctx->qp_max_l2_entries + 2 * (extra_qps + ctx->qp_min_qp1_entries); 7541 entries = roundup(entries, ctx->tqm_entries_multiple); 7542 entries = clamp_t(u32, entries, min, ctx->tqm_max_entries_per_ring); 7543 for (i = 0; i < ctx->tqm_fp_rings_count + 1; i++) { 7544 ctx_pg = ctx->tqm_mem[i]; 7545 ctx_pg->entries = i ? entries : entries_sp; 7546 if (ctx->tqm_entry_size) { 7547 mem_size = ctx->tqm_entry_size * ctx_pg->entries; 7548 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1, 7549 NULL); 7550 if (rc) 7551 return rc; 7552 } 7553 ena |= FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP << i; 7554 } 7555 ena |= FUNC_BACKING_STORE_CFG_REQ_DFLT_ENABLES; 7556 rc = bnxt_hwrm_func_backing_store_cfg(bp, ena); 7557 if (rc) { 7558 netdev_err(bp->dev, "Failed configuring context mem, rc = %d.\n", 7559 rc); 7560 return rc; 7561 } 7562 ctx->flags |= BNXT_CTX_FLAG_INITED; 7563 return 0; 7564 } 7565 7566 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp, bool all) 7567 { 7568 struct hwrm_func_resource_qcaps_output *resp; 7569 struct hwrm_func_resource_qcaps_input *req; 7570 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 7571 int rc; 7572 7573 rc = hwrm_req_init(bp, req, HWRM_FUNC_RESOURCE_QCAPS); 7574 if (rc) 7575 return rc; 7576 7577 req->fid = cpu_to_le16(0xffff); 7578 resp = hwrm_req_hold(bp, req); 7579 rc = hwrm_req_send_silent(bp, req); 7580 if (rc) 7581 goto hwrm_func_resc_qcaps_exit; 7582 7583 hw_resc->max_tx_sch_inputs = le16_to_cpu(resp->max_tx_scheduler_inputs); 7584 if (!all) 7585 goto hwrm_func_resc_qcaps_exit; 7586 7587 hw_resc->min_rsscos_ctxs = le16_to_cpu(resp->min_rsscos_ctx); 7588 hw_resc->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx); 7589 hw_resc->min_cp_rings = le16_to_cpu(resp->min_cmpl_rings); 7590 hw_resc->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings); 7591 hw_resc->min_tx_rings = le16_to_cpu(resp->min_tx_rings); 7592 hw_resc->max_tx_rings = le16_to_cpu(resp->max_tx_rings); 7593 hw_resc->min_rx_rings = le16_to_cpu(resp->min_rx_rings); 7594 hw_resc->max_rx_rings = le16_to_cpu(resp->max_rx_rings); 7595 hw_resc->min_hw_ring_grps = le16_to_cpu(resp->min_hw_ring_grps); 7596 hw_resc->max_hw_ring_grps = le16_to_cpu(resp->max_hw_ring_grps); 7597 hw_resc->min_l2_ctxs = le16_to_cpu(resp->min_l2_ctxs); 7598 hw_resc->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs); 7599 hw_resc->min_vnics = le16_to_cpu(resp->min_vnics); 7600 hw_resc->max_vnics = le16_to_cpu(resp->max_vnics); 7601 hw_resc->min_stat_ctxs = le16_to_cpu(resp->min_stat_ctx); 7602 hw_resc->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx); 7603 7604 if (bp->flags & BNXT_FLAG_CHIP_P5) { 7605 u16 max_msix = le16_to_cpu(resp->max_msix); 7606 7607 hw_resc->max_nqs = max_msix; 7608 hw_resc->max_hw_ring_grps = hw_resc->max_rx_rings; 7609 } 7610 7611 if (BNXT_PF(bp)) { 7612 struct bnxt_pf_info *pf = &bp->pf; 7613 7614 pf->vf_resv_strategy = 7615 le16_to_cpu(resp->vf_reservation_strategy); 7616 if (pf->vf_resv_strategy > BNXT_VF_RESV_STRATEGY_MINIMAL_STATIC) 7617 pf->vf_resv_strategy = BNXT_VF_RESV_STRATEGY_MAXIMAL; 7618 } 7619 hwrm_func_resc_qcaps_exit: 7620 hwrm_req_drop(bp, req); 7621 return rc; 7622 } 7623 7624 static int __bnxt_hwrm_ptp_qcfg(struct bnxt *bp) 7625 { 7626 struct hwrm_port_mac_ptp_qcfg_output *resp; 7627 struct hwrm_port_mac_ptp_qcfg_input *req; 7628 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 7629 bool phc_cfg; 7630 u8 flags; 7631 int rc; 7632 7633 if (bp->hwrm_spec_code < 0x10801 || !BNXT_CHIP_P5_THOR(bp)) { 7634 rc = -ENODEV; 7635 goto no_ptp; 7636 } 7637 7638 rc = hwrm_req_init(bp, req, HWRM_PORT_MAC_PTP_QCFG); 7639 if (rc) 7640 goto no_ptp; 7641 7642 req->port_id = cpu_to_le16(bp->pf.port_id); 7643 resp = hwrm_req_hold(bp, req); 7644 rc = hwrm_req_send(bp, req); 7645 if (rc) 7646 goto exit; 7647 7648 flags = resp->flags; 7649 if (!(flags & PORT_MAC_PTP_QCFG_RESP_FLAGS_HWRM_ACCESS)) { 7650 rc = -ENODEV; 7651 goto exit; 7652 } 7653 if (!ptp) { 7654 ptp = kzalloc(sizeof(*ptp), GFP_KERNEL); 7655 if (!ptp) { 7656 rc = -ENOMEM; 7657 goto exit; 7658 } 7659 ptp->bp = bp; 7660 bp->ptp_cfg = ptp; 7661 } 7662 if (flags & PORT_MAC_PTP_QCFG_RESP_FLAGS_PARTIAL_DIRECT_ACCESS_REF_CLOCK) { 7663 ptp->refclk_regs[0] = le32_to_cpu(resp->ts_ref_clock_reg_lower); 7664 ptp->refclk_regs[1] = le32_to_cpu(resp->ts_ref_clock_reg_upper); 7665 } else if (bp->flags & BNXT_FLAG_CHIP_P5) { 7666 ptp->refclk_regs[0] = BNXT_TS_REG_TIMESYNC_TS0_LOWER; 7667 ptp->refclk_regs[1] = BNXT_TS_REG_TIMESYNC_TS0_UPPER; 7668 } else { 7669 rc = -ENODEV; 7670 goto exit; 7671 } 7672 phc_cfg = (flags & PORT_MAC_PTP_QCFG_RESP_FLAGS_RTC_CONFIGURED) != 0; 7673 rc = bnxt_ptp_init(bp, phc_cfg); 7674 if (rc) 7675 netdev_warn(bp->dev, "PTP initialization failed.\n"); 7676 exit: 7677 hwrm_req_drop(bp, req); 7678 if (!rc) 7679 return 0; 7680 7681 no_ptp: 7682 bnxt_ptp_clear(bp); 7683 kfree(ptp); 7684 bp->ptp_cfg = NULL; 7685 return rc; 7686 } 7687 7688 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp) 7689 { 7690 struct hwrm_func_qcaps_output *resp; 7691 struct hwrm_func_qcaps_input *req; 7692 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 7693 u32 flags, flags_ext, flags_ext2; 7694 int rc; 7695 7696 rc = hwrm_req_init(bp, req, HWRM_FUNC_QCAPS); 7697 if (rc) 7698 return rc; 7699 7700 req->fid = cpu_to_le16(0xffff); 7701 resp = hwrm_req_hold(bp, req); 7702 rc = hwrm_req_send(bp, req); 7703 if (rc) 7704 goto hwrm_func_qcaps_exit; 7705 7706 flags = le32_to_cpu(resp->flags); 7707 if (flags & FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED) 7708 bp->flags |= BNXT_FLAG_ROCEV1_CAP; 7709 if (flags & FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED) 7710 bp->flags |= BNXT_FLAG_ROCEV2_CAP; 7711 if (flags & FUNC_QCAPS_RESP_FLAGS_PCIE_STATS_SUPPORTED) 7712 bp->fw_cap |= BNXT_FW_CAP_PCIE_STATS_SUPPORTED; 7713 if (flags & FUNC_QCAPS_RESP_FLAGS_HOT_RESET_CAPABLE) 7714 bp->fw_cap |= BNXT_FW_CAP_HOT_RESET; 7715 if (flags & FUNC_QCAPS_RESP_FLAGS_EXT_STATS_SUPPORTED) 7716 bp->fw_cap |= BNXT_FW_CAP_EXT_STATS_SUPPORTED; 7717 if (flags & FUNC_QCAPS_RESP_FLAGS_ERROR_RECOVERY_CAPABLE) 7718 bp->fw_cap |= BNXT_FW_CAP_ERROR_RECOVERY; 7719 if (flags & FUNC_QCAPS_RESP_FLAGS_ERR_RECOVER_RELOAD) 7720 bp->fw_cap |= BNXT_FW_CAP_ERR_RECOVER_RELOAD; 7721 if (!(flags & FUNC_QCAPS_RESP_FLAGS_VLAN_ACCELERATION_TX_DISABLED)) 7722 bp->fw_cap |= BNXT_FW_CAP_VLAN_TX_INSERT; 7723 if (flags & FUNC_QCAPS_RESP_FLAGS_DBG_QCAPS_CMD_SUPPORTED) 7724 bp->fw_cap |= BNXT_FW_CAP_DBG_QCAPS; 7725 7726 flags_ext = le32_to_cpu(resp->flags_ext); 7727 if (flags_ext & FUNC_QCAPS_RESP_FLAGS_EXT_EXT_HW_STATS_SUPPORTED) 7728 bp->fw_cap |= BNXT_FW_CAP_EXT_HW_STATS_SUPPORTED; 7729 if (BNXT_PF(bp) && (flags_ext & FUNC_QCAPS_RESP_FLAGS_EXT_PTP_PPS_SUPPORTED)) 7730 bp->fw_cap |= BNXT_FW_CAP_PTP_PPS; 7731 if (flags_ext & FUNC_QCAPS_RESP_FLAGS_EXT_PTP_64BIT_RTC_SUPPORTED) 7732 bp->fw_cap |= BNXT_FW_CAP_PTP_RTC; 7733 if (BNXT_PF(bp) && (flags_ext & FUNC_QCAPS_RESP_FLAGS_EXT_HOT_RESET_IF_SUPPORT)) 7734 bp->fw_cap |= BNXT_FW_CAP_HOT_RESET_IF; 7735 if (BNXT_PF(bp) && (flags_ext & FUNC_QCAPS_RESP_FLAGS_EXT_FW_LIVEPATCH_SUPPORTED)) 7736 bp->fw_cap |= BNXT_FW_CAP_LIVEPATCH; 7737 7738 flags_ext2 = le32_to_cpu(resp->flags_ext2); 7739 if (flags_ext2 & FUNC_QCAPS_RESP_FLAGS_EXT2_RX_ALL_PKTS_TIMESTAMPS_SUPPORTED) 7740 bp->fw_cap |= BNXT_FW_CAP_RX_ALL_PKT_TS; 7741 7742 bp->tx_push_thresh = 0; 7743 if ((flags & FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED) && 7744 BNXT_FW_MAJ(bp) > 217) 7745 bp->tx_push_thresh = BNXT_TX_PUSH_THRESH; 7746 7747 hw_resc->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx); 7748 hw_resc->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings); 7749 hw_resc->max_tx_rings = le16_to_cpu(resp->max_tx_rings); 7750 hw_resc->max_rx_rings = le16_to_cpu(resp->max_rx_rings); 7751 hw_resc->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps); 7752 if (!hw_resc->max_hw_ring_grps) 7753 hw_resc->max_hw_ring_grps = hw_resc->max_tx_rings; 7754 hw_resc->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs); 7755 hw_resc->max_vnics = le16_to_cpu(resp->max_vnics); 7756 hw_resc->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx); 7757 7758 if (BNXT_PF(bp)) { 7759 struct bnxt_pf_info *pf = &bp->pf; 7760 7761 pf->fw_fid = le16_to_cpu(resp->fid); 7762 pf->port_id = le16_to_cpu(resp->port_id); 7763 memcpy(pf->mac_addr, resp->mac_address, ETH_ALEN); 7764 pf->first_vf_id = le16_to_cpu(resp->first_vf_id); 7765 pf->max_vfs = le16_to_cpu(resp->max_vfs); 7766 pf->max_encap_records = le32_to_cpu(resp->max_encap_records); 7767 pf->max_decap_records = le32_to_cpu(resp->max_decap_records); 7768 pf->max_tx_em_flows = le32_to_cpu(resp->max_tx_em_flows); 7769 pf->max_tx_wm_flows = le32_to_cpu(resp->max_tx_wm_flows); 7770 pf->max_rx_em_flows = le32_to_cpu(resp->max_rx_em_flows); 7771 pf->max_rx_wm_flows = le32_to_cpu(resp->max_rx_wm_flows); 7772 bp->flags &= ~BNXT_FLAG_WOL_CAP; 7773 if (flags & FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED) 7774 bp->flags |= BNXT_FLAG_WOL_CAP; 7775 if (flags & FUNC_QCAPS_RESP_FLAGS_PTP_SUPPORTED) { 7776 bp->fw_cap |= BNXT_FW_CAP_PTP; 7777 } else { 7778 bnxt_ptp_clear(bp); 7779 kfree(bp->ptp_cfg); 7780 bp->ptp_cfg = NULL; 7781 } 7782 } else { 7783 #ifdef CONFIG_BNXT_SRIOV 7784 struct bnxt_vf_info *vf = &bp->vf; 7785 7786 vf->fw_fid = le16_to_cpu(resp->fid); 7787 memcpy(vf->mac_addr, resp->mac_address, ETH_ALEN); 7788 #endif 7789 } 7790 7791 hwrm_func_qcaps_exit: 7792 hwrm_req_drop(bp, req); 7793 return rc; 7794 } 7795 7796 static void bnxt_hwrm_dbg_qcaps(struct bnxt *bp) 7797 { 7798 struct hwrm_dbg_qcaps_output *resp; 7799 struct hwrm_dbg_qcaps_input *req; 7800 int rc; 7801 7802 bp->fw_dbg_cap = 0; 7803 if (!(bp->fw_cap & BNXT_FW_CAP_DBG_QCAPS)) 7804 return; 7805 7806 rc = hwrm_req_init(bp, req, HWRM_DBG_QCAPS); 7807 if (rc) 7808 return; 7809 7810 req->fid = cpu_to_le16(0xffff); 7811 resp = hwrm_req_hold(bp, req); 7812 rc = hwrm_req_send(bp, req); 7813 if (rc) 7814 goto hwrm_dbg_qcaps_exit; 7815 7816 bp->fw_dbg_cap = le32_to_cpu(resp->flags); 7817 7818 hwrm_dbg_qcaps_exit: 7819 hwrm_req_drop(bp, req); 7820 } 7821 7822 static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp); 7823 7824 int bnxt_hwrm_func_qcaps(struct bnxt *bp) 7825 { 7826 int rc; 7827 7828 rc = __bnxt_hwrm_func_qcaps(bp); 7829 if (rc) 7830 return rc; 7831 7832 bnxt_hwrm_dbg_qcaps(bp); 7833 7834 rc = bnxt_hwrm_queue_qportcfg(bp); 7835 if (rc) { 7836 netdev_err(bp->dev, "hwrm query qportcfg failure rc: %d\n", rc); 7837 return rc; 7838 } 7839 if (bp->hwrm_spec_code >= 0x10803) { 7840 rc = bnxt_alloc_ctx_mem(bp); 7841 if (rc) 7842 return rc; 7843 rc = bnxt_hwrm_func_resc_qcaps(bp, true); 7844 if (!rc) 7845 bp->fw_cap |= BNXT_FW_CAP_NEW_RM; 7846 } 7847 return 0; 7848 } 7849 7850 static int bnxt_hwrm_cfa_adv_flow_mgnt_qcaps(struct bnxt *bp) 7851 { 7852 struct hwrm_cfa_adv_flow_mgnt_qcaps_output *resp; 7853 struct hwrm_cfa_adv_flow_mgnt_qcaps_input *req; 7854 u32 flags; 7855 int rc; 7856 7857 if (!(bp->fw_cap & BNXT_FW_CAP_CFA_ADV_FLOW)) 7858 return 0; 7859 7860 rc = hwrm_req_init(bp, req, HWRM_CFA_ADV_FLOW_MGNT_QCAPS); 7861 if (rc) 7862 return rc; 7863 7864 resp = hwrm_req_hold(bp, req); 7865 rc = hwrm_req_send(bp, req); 7866 if (rc) 7867 goto hwrm_cfa_adv_qcaps_exit; 7868 7869 flags = le32_to_cpu(resp->flags); 7870 if (flags & 7871 CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RFS_RING_TBL_IDX_V2_SUPPORTED) 7872 bp->fw_cap |= BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V2; 7873 7874 hwrm_cfa_adv_qcaps_exit: 7875 hwrm_req_drop(bp, req); 7876 return rc; 7877 } 7878 7879 static int __bnxt_alloc_fw_health(struct bnxt *bp) 7880 { 7881 if (bp->fw_health) 7882 return 0; 7883 7884 bp->fw_health = kzalloc(sizeof(*bp->fw_health), GFP_KERNEL); 7885 if (!bp->fw_health) 7886 return -ENOMEM; 7887 7888 mutex_init(&bp->fw_health->lock); 7889 return 0; 7890 } 7891 7892 static int bnxt_alloc_fw_health(struct bnxt *bp) 7893 { 7894 int rc; 7895 7896 if (!(bp->fw_cap & BNXT_FW_CAP_HOT_RESET) && 7897 !(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)) 7898 return 0; 7899 7900 rc = __bnxt_alloc_fw_health(bp); 7901 if (rc) { 7902 bp->fw_cap &= ~BNXT_FW_CAP_HOT_RESET; 7903 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY; 7904 return rc; 7905 } 7906 7907 return 0; 7908 } 7909 7910 static void __bnxt_map_fw_health_reg(struct bnxt *bp, u32 reg) 7911 { 7912 writel(reg & BNXT_GRC_BASE_MASK, bp->bar0 + 7913 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 7914 BNXT_FW_HEALTH_WIN_MAP_OFF); 7915 } 7916 7917 static void bnxt_inv_fw_health_reg(struct bnxt *bp) 7918 { 7919 struct bnxt_fw_health *fw_health = bp->fw_health; 7920 u32 reg_type; 7921 7922 if (!fw_health) 7923 return; 7924 7925 reg_type = BNXT_FW_HEALTH_REG_TYPE(fw_health->regs[BNXT_FW_HEALTH_REG]); 7926 if (reg_type == BNXT_FW_HEALTH_REG_TYPE_GRC) 7927 fw_health->status_reliable = false; 7928 7929 reg_type = BNXT_FW_HEALTH_REG_TYPE(fw_health->regs[BNXT_FW_RESET_CNT_REG]); 7930 if (reg_type == BNXT_FW_HEALTH_REG_TYPE_GRC) 7931 fw_health->resets_reliable = false; 7932 } 7933 7934 static void bnxt_try_map_fw_health_reg(struct bnxt *bp) 7935 { 7936 void __iomem *hs; 7937 u32 status_loc; 7938 u32 reg_type; 7939 u32 sig; 7940 7941 if (bp->fw_health) 7942 bp->fw_health->status_reliable = false; 7943 7944 __bnxt_map_fw_health_reg(bp, HCOMM_STATUS_STRUCT_LOC); 7945 hs = bp->bar0 + BNXT_FW_HEALTH_WIN_OFF(HCOMM_STATUS_STRUCT_LOC); 7946 7947 sig = readl(hs + offsetof(struct hcomm_status, sig_ver)); 7948 if ((sig & HCOMM_STATUS_SIGNATURE_MASK) != HCOMM_STATUS_SIGNATURE_VAL) { 7949 if (!bp->chip_num) { 7950 __bnxt_map_fw_health_reg(bp, BNXT_GRC_REG_BASE); 7951 bp->chip_num = readl(bp->bar0 + 7952 BNXT_FW_HEALTH_WIN_BASE + 7953 BNXT_GRC_REG_CHIP_NUM); 7954 } 7955 if (!BNXT_CHIP_P5(bp)) 7956 return; 7957 7958 status_loc = BNXT_GRC_REG_STATUS_P5 | 7959 BNXT_FW_HEALTH_REG_TYPE_BAR0; 7960 } else { 7961 status_loc = readl(hs + offsetof(struct hcomm_status, 7962 fw_status_loc)); 7963 } 7964 7965 if (__bnxt_alloc_fw_health(bp)) { 7966 netdev_warn(bp->dev, "no memory for firmware status checks\n"); 7967 return; 7968 } 7969 7970 bp->fw_health->regs[BNXT_FW_HEALTH_REG] = status_loc; 7971 reg_type = BNXT_FW_HEALTH_REG_TYPE(status_loc); 7972 if (reg_type == BNXT_FW_HEALTH_REG_TYPE_GRC) { 7973 __bnxt_map_fw_health_reg(bp, status_loc); 7974 bp->fw_health->mapped_regs[BNXT_FW_HEALTH_REG] = 7975 BNXT_FW_HEALTH_WIN_OFF(status_loc); 7976 } 7977 7978 bp->fw_health->status_reliable = true; 7979 } 7980 7981 static int bnxt_map_fw_health_regs(struct bnxt *bp) 7982 { 7983 struct bnxt_fw_health *fw_health = bp->fw_health; 7984 u32 reg_base = 0xffffffff; 7985 int i; 7986 7987 bp->fw_health->status_reliable = false; 7988 bp->fw_health->resets_reliable = false; 7989 /* Only pre-map the monitoring GRC registers using window 3 */ 7990 for (i = 0; i < 4; i++) { 7991 u32 reg = fw_health->regs[i]; 7992 7993 if (BNXT_FW_HEALTH_REG_TYPE(reg) != BNXT_FW_HEALTH_REG_TYPE_GRC) 7994 continue; 7995 if (reg_base == 0xffffffff) 7996 reg_base = reg & BNXT_GRC_BASE_MASK; 7997 if ((reg & BNXT_GRC_BASE_MASK) != reg_base) 7998 return -ERANGE; 7999 fw_health->mapped_regs[i] = BNXT_FW_HEALTH_WIN_OFF(reg); 8000 } 8001 bp->fw_health->status_reliable = true; 8002 bp->fw_health->resets_reliable = true; 8003 if (reg_base == 0xffffffff) 8004 return 0; 8005 8006 __bnxt_map_fw_health_reg(bp, reg_base); 8007 return 0; 8008 } 8009 8010 static void bnxt_remap_fw_health_regs(struct bnxt *bp) 8011 { 8012 if (!bp->fw_health) 8013 return; 8014 8015 if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY) { 8016 bp->fw_health->status_reliable = true; 8017 bp->fw_health->resets_reliable = true; 8018 } else { 8019 bnxt_try_map_fw_health_reg(bp); 8020 } 8021 } 8022 8023 static int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp) 8024 { 8025 struct bnxt_fw_health *fw_health = bp->fw_health; 8026 struct hwrm_error_recovery_qcfg_output *resp; 8027 struct hwrm_error_recovery_qcfg_input *req; 8028 int rc, i; 8029 8030 if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)) 8031 return 0; 8032 8033 rc = hwrm_req_init(bp, req, HWRM_ERROR_RECOVERY_QCFG); 8034 if (rc) 8035 return rc; 8036 8037 resp = hwrm_req_hold(bp, req); 8038 rc = hwrm_req_send(bp, req); 8039 if (rc) 8040 goto err_recovery_out; 8041 fw_health->flags = le32_to_cpu(resp->flags); 8042 if ((fw_health->flags & ERROR_RECOVERY_QCFG_RESP_FLAGS_CO_CPU) && 8043 !(bp->fw_cap & BNXT_FW_CAP_KONG_MB_CHNL)) { 8044 rc = -EINVAL; 8045 goto err_recovery_out; 8046 } 8047 fw_health->polling_dsecs = le32_to_cpu(resp->driver_polling_freq); 8048 fw_health->master_func_wait_dsecs = 8049 le32_to_cpu(resp->master_func_wait_period); 8050 fw_health->normal_func_wait_dsecs = 8051 le32_to_cpu(resp->normal_func_wait_period); 8052 fw_health->post_reset_wait_dsecs = 8053 le32_to_cpu(resp->master_func_wait_period_after_reset); 8054 fw_health->post_reset_max_wait_dsecs = 8055 le32_to_cpu(resp->max_bailout_time_after_reset); 8056 fw_health->regs[BNXT_FW_HEALTH_REG] = 8057 le32_to_cpu(resp->fw_health_status_reg); 8058 fw_health->regs[BNXT_FW_HEARTBEAT_REG] = 8059 le32_to_cpu(resp->fw_heartbeat_reg); 8060 fw_health->regs[BNXT_FW_RESET_CNT_REG] = 8061 le32_to_cpu(resp->fw_reset_cnt_reg); 8062 fw_health->regs[BNXT_FW_RESET_INPROG_REG] = 8063 le32_to_cpu(resp->reset_inprogress_reg); 8064 fw_health->fw_reset_inprog_reg_mask = 8065 le32_to_cpu(resp->reset_inprogress_reg_mask); 8066 fw_health->fw_reset_seq_cnt = resp->reg_array_cnt; 8067 if (fw_health->fw_reset_seq_cnt >= 16) { 8068 rc = -EINVAL; 8069 goto err_recovery_out; 8070 } 8071 for (i = 0; i < fw_health->fw_reset_seq_cnt; i++) { 8072 fw_health->fw_reset_seq_regs[i] = 8073 le32_to_cpu(resp->reset_reg[i]); 8074 fw_health->fw_reset_seq_vals[i] = 8075 le32_to_cpu(resp->reset_reg_val[i]); 8076 fw_health->fw_reset_seq_delay_msec[i] = 8077 resp->delay_after_reset[i]; 8078 } 8079 err_recovery_out: 8080 hwrm_req_drop(bp, req); 8081 if (!rc) 8082 rc = bnxt_map_fw_health_regs(bp); 8083 if (rc) 8084 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY; 8085 return rc; 8086 } 8087 8088 static int bnxt_hwrm_func_reset(struct bnxt *bp) 8089 { 8090 struct hwrm_func_reset_input *req; 8091 int rc; 8092 8093 rc = hwrm_req_init(bp, req, HWRM_FUNC_RESET); 8094 if (rc) 8095 return rc; 8096 8097 req->enables = 0; 8098 hwrm_req_timeout(bp, req, HWRM_RESET_TIMEOUT); 8099 return hwrm_req_send(bp, req); 8100 } 8101 8102 static void bnxt_nvm_cfg_ver_get(struct bnxt *bp) 8103 { 8104 struct hwrm_nvm_get_dev_info_output nvm_info; 8105 8106 if (!bnxt_hwrm_nvm_get_dev_info(bp, &nvm_info)) 8107 snprintf(bp->nvm_cfg_ver, FW_VER_STR_LEN, "%d.%d.%d", 8108 nvm_info.nvm_cfg_ver_maj, nvm_info.nvm_cfg_ver_min, 8109 nvm_info.nvm_cfg_ver_upd); 8110 } 8111 8112 static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp) 8113 { 8114 struct hwrm_queue_qportcfg_output *resp; 8115 struct hwrm_queue_qportcfg_input *req; 8116 u8 i, j, *qptr; 8117 bool no_rdma; 8118 int rc = 0; 8119 8120 rc = hwrm_req_init(bp, req, HWRM_QUEUE_QPORTCFG); 8121 if (rc) 8122 return rc; 8123 8124 resp = hwrm_req_hold(bp, req); 8125 rc = hwrm_req_send(bp, req); 8126 if (rc) 8127 goto qportcfg_exit; 8128 8129 if (!resp->max_configurable_queues) { 8130 rc = -EINVAL; 8131 goto qportcfg_exit; 8132 } 8133 bp->max_tc = resp->max_configurable_queues; 8134 bp->max_lltc = resp->max_configurable_lossless_queues; 8135 if (bp->max_tc > BNXT_MAX_QUEUE) 8136 bp->max_tc = BNXT_MAX_QUEUE; 8137 8138 no_rdma = !(bp->flags & BNXT_FLAG_ROCE_CAP); 8139 qptr = &resp->queue_id0; 8140 for (i = 0, j = 0; i < bp->max_tc; i++) { 8141 bp->q_info[j].queue_id = *qptr; 8142 bp->q_ids[i] = *qptr++; 8143 bp->q_info[j].queue_profile = *qptr++; 8144 bp->tc_to_qidx[j] = j; 8145 if (!BNXT_CNPQ(bp->q_info[j].queue_profile) || 8146 (no_rdma && BNXT_PF(bp))) 8147 j++; 8148 } 8149 bp->max_q = bp->max_tc; 8150 bp->max_tc = max_t(u8, j, 1); 8151 8152 if (resp->queue_cfg_info & QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG) 8153 bp->max_tc = 1; 8154 8155 if (bp->max_lltc > bp->max_tc) 8156 bp->max_lltc = bp->max_tc; 8157 8158 qportcfg_exit: 8159 hwrm_req_drop(bp, req); 8160 return rc; 8161 } 8162 8163 static int bnxt_hwrm_poll(struct bnxt *bp) 8164 { 8165 struct hwrm_ver_get_input *req; 8166 int rc; 8167 8168 rc = hwrm_req_init(bp, req, HWRM_VER_GET); 8169 if (rc) 8170 return rc; 8171 8172 req->hwrm_intf_maj = HWRM_VERSION_MAJOR; 8173 req->hwrm_intf_min = HWRM_VERSION_MINOR; 8174 req->hwrm_intf_upd = HWRM_VERSION_UPDATE; 8175 8176 hwrm_req_flags(bp, req, BNXT_HWRM_CTX_SILENT | BNXT_HWRM_FULL_WAIT); 8177 rc = hwrm_req_send(bp, req); 8178 return rc; 8179 } 8180 8181 static int bnxt_hwrm_ver_get(struct bnxt *bp) 8182 { 8183 struct hwrm_ver_get_output *resp; 8184 struct hwrm_ver_get_input *req; 8185 u16 fw_maj, fw_min, fw_bld, fw_rsv; 8186 u32 dev_caps_cfg, hwrm_ver; 8187 int rc, len; 8188 8189 rc = hwrm_req_init(bp, req, HWRM_VER_GET); 8190 if (rc) 8191 return rc; 8192 8193 hwrm_req_flags(bp, req, BNXT_HWRM_FULL_WAIT); 8194 bp->hwrm_max_req_len = HWRM_MAX_REQ_LEN; 8195 req->hwrm_intf_maj = HWRM_VERSION_MAJOR; 8196 req->hwrm_intf_min = HWRM_VERSION_MINOR; 8197 req->hwrm_intf_upd = HWRM_VERSION_UPDATE; 8198 8199 resp = hwrm_req_hold(bp, req); 8200 rc = hwrm_req_send(bp, req); 8201 if (rc) 8202 goto hwrm_ver_get_exit; 8203 8204 memcpy(&bp->ver_resp, resp, sizeof(struct hwrm_ver_get_output)); 8205 8206 bp->hwrm_spec_code = resp->hwrm_intf_maj_8b << 16 | 8207 resp->hwrm_intf_min_8b << 8 | 8208 resp->hwrm_intf_upd_8b; 8209 if (resp->hwrm_intf_maj_8b < 1) { 8210 netdev_warn(bp->dev, "HWRM interface %d.%d.%d is older than 1.0.0.\n", 8211 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b, 8212 resp->hwrm_intf_upd_8b); 8213 netdev_warn(bp->dev, "Please update firmware with HWRM interface 1.0.0 or newer.\n"); 8214 } 8215 8216 hwrm_ver = HWRM_VERSION_MAJOR << 16 | HWRM_VERSION_MINOR << 8 | 8217 HWRM_VERSION_UPDATE; 8218 8219 if (bp->hwrm_spec_code > hwrm_ver) 8220 snprintf(bp->hwrm_ver_supp, FW_VER_STR_LEN, "%d.%d.%d", 8221 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, 8222 HWRM_VERSION_UPDATE); 8223 else 8224 snprintf(bp->hwrm_ver_supp, FW_VER_STR_LEN, "%d.%d.%d", 8225 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b, 8226 resp->hwrm_intf_upd_8b); 8227 8228 fw_maj = le16_to_cpu(resp->hwrm_fw_major); 8229 if (bp->hwrm_spec_code > 0x10803 && fw_maj) { 8230 fw_min = le16_to_cpu(resp->hwrm_fw_minor); 8231 fw_bld = le16_to_cpu(resp->hwrm_fw_build); 8232 fw_rsv = le16_to_cpu(resp->hwrm_fw_patch); 8233 len = FW_VER_STR_LEN; 8234 } else { 8235 fw_maj = resp->hwrm_fw_maj_8b; 8236 fw_min = resp->hwrm_fw_min_8b; 8237 fw_bld = resp->hwrm_fw_bld_8b; 8238 fw_rsv = resp->hwrm_fw_rsvd_8b; 8239 len = BC_HWRM_STR_LEN; 8240 } 8241 bp->fw_ver_code = BNXT_FW_VER_CODE(fw_maj, fw_min, fw_bld, fw_rsv); 8242 snprintf(bp->fw_ver_str, len, "%d.%d.%d.%d", fw_maj, fw_min, fw_bld, 8243 fw_rsv); 8244 8245 if (strlen(resp->active_pkg_name)) { 8246 int fw_ver_len = strlen(bp->fw_ver_str); 8247 8248 snprintf(bp->fw_ver_str + fw_ver_len, 8249 FW_VER_STR_LEN - fw_ver_len - 1, "/pkg %s", 8250 resp->active_pkg_name); 8251 bp->fw_cap |= BNXT_FW_CAP_PKG_VER; 8252 } 8253 8254 bp->hwrm_cmd_timeout = le16_to_cpu(resp->def_req_timeout); 8255 if (!bp->hwrm_cmd_timeout) 8256 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT; 8257 bp->hwrm_cmd_max_timeout = le16_to_cpu(resp->max_req_timeout) * 1000; 8258 if (!bp->hwrm_cmd_max_timeout) 8259 bp->hwrm_cmd_max_timeout = HWRM_CMD_MAX_TIMEOUT; 8260 else if (bp->hwrm_cmd_max_timeout > HWRM_CMD_MAX_TIMEOUT) 8261 netdev_warn(bp->dev, "Device requests max timeout of %d seconds, may trigger hung task watchdog\n", 8262 bp->hwrm_cmd_max_timeout / 1000); 8263 8264 if (resp->hwrm_intf_maj_8b >= 1) { 8265 bp->hwrm_max_req_len = le16_to_cpu(resp->max_req_win_len); 8266 bp->hwrm_max_ext_req_len = le16_to_cpu(resp->max_ext_req_len); 8267 } 8268 if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN) 8269 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN; 8270 8271 bp->chip_num = le16_to_cpu(resp->chip_num); 8272 bp->chip_rev = resp->chip_rev; 8273 if (bp->chip_num == CHIP_NUM_58700 && !resp->chip_rev && 8274 !resp->chip_metal) 8275 bp->flags |= BNXT_FLAG_CHIP_NITRO_A0; 8276 8277 dev_caps_cfg = le32_to_cpu(resp->dev_caps_cfg); 8278 if ((dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) && 8279 (dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) 8280 bp->fw_cap |= BNXT_FW_CAP_SHORT_CMD; 8281 8282 if (dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) 8283 bp->fw_cap |= BNXT_FW_CAP_KONG_MB_CHNL; 8284 8285 if (dev_caps_cfg & 8286 VER_GET_RESP_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED) 8287 bp->fw_cap |= BNXT_FW_CAP_OVS_64BIT_HANDLE; 8288 8289 if (dev_caps_cfg & 8290 VER_GET_RESP_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED) 8291 bp->fw_cap |= BNXT_FW_CAP_TRUSTED_VF; 8292 8293 if (dev_caps_cfg & 8294 VER_GET_RESP_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED) 8295 bp->fw_cap |= BNXT_FW_CAP_CFA_ADV_FLOW; 8296 8297 hwrm_ver_get_exit: 8298 hwrm_req_drop(bp, req); 8299 return rc; 8300 } 8301 8302 int bnxt_hwrm_fw_set_time(struct bnxt *bp) 8303 { 8304 struct hwrm_fw_set_time_input *req; 8305 struct tm tm; 8306 time64_t now = ktime_get_real_seconds(); 8307 int rc; 8308 8309 if ((BNXT_VF(bp) && bp->hwrm_spec_code < 0x10901) || 8310 bp->hwrm_spec_code < 0x10400) 8311 return -EOPNOTSUPP; 8312 8313 time64_to_tm(now, 0, &tm); 8314 rc = hwrm_req_init(bp, req, HWRM_FW_SET_TIME); 8315 if (rc) 8316 return rc; 8317 8318 req->year = cpu_to_le16(1900 + tm.tm_year); 8319 req->month = 1 + tm.tm_mon; 8320 req->day = tm.tm_mday; 8321 req->hour = tm.tm_hour; 8322 req->minute = tm.tm_min; 8323 req->second = tm.tm_sec; 8324 return hwrm_req_send(bp, req); 8325 } 8326 8327 static void bnxt_add_one_ctr(u64 hw, u64 *sw, u64 mask) 8328 { 8329 u64 sw_tmp; 8330 8331 hw &= mask; 8332 sw_tmp = (*sw & ~mask) | hw; 8333 if (hw < (*sw & mask)) 8334 sw_tmp += mask + 1; 8335 WRITE_ONCE(*sw, sw_tmp); 8336 } 8337 8338 static void __bnxt_accumulate_stats(__le64 *hw_stats, u64 *sw_stats, u64 *masks, 8339 int count, bool ignore_zero) 8340 { 8341 int i; 8342 8343 for (i = 0; i < count; i++) { 8344 u64 hw = le64_to_cpu(READ_ONCE(hw_stats[i])); 8345 8346 if (ignore_zero && !hw) 8347 continue; 8348 8349 if (masks[i] == -1ULL) 8350 sw_stats[i] = hw; 8351 else 8352 bnxt_add_one_ctr(hw, &sw_stats[i], masks[i]); 8353 } 8354 } 8355 8356 static void bnxt_accumulate_stats(struct bnxt_stats_mem *stats) 8357 { 8358 if (!stats->hw_stats) 8359 return; 8360 8361 __bnxt_accumulate_stats(stats->hw_stats, stats->sw_stats, 8362 stats->hw_masks, stats->len / 8, false); 8363 } 8364 8365 static void bnxt_accumulate_all_stats(struct bnxt *bp) 8366 { 8367 struct bnxt_stats_mem *ring0_stats; 8368 bool ignore_zero = false; 8369 int i; 8370 8371 /* Chip bug. Counter intermittently becomes 0. */ 8372 if (bp->flags & BNXT_FLAG_CHIP_P5) 8373 ignore_zero = true; 8374 8375 for (i = 0; i < bp->cp_nr_rings; i++) { 8376 struct bnxt_napi *bnapi = bp->bnapi[i]; 8377 struct bnxt_cp_ring_info *cpr; 8378 struct bnxt_stats_mem *stats; 8379 8380 cpr = &bnapi->cp_ring; 8381 stats = &cpr->stats; 8382 if (!i) 8383 ring0_stats = stats; 8384 __bnxt_accumulate_stats(stats->hw_stats, stats->sw_stats, 8385 ring0_stats->hw_masks, 8386 ring0_stats->len / 8, ignore_zero); 8387 } 8388 if (bp->flags & BNXT_FLAG_PORT_STATS) { 8389 struct bnxt_stats_mem *stats = &bp->port_stats; 8390 __le64 *hw_stats = stats->hw_stats; 8391 u64 *sw_stats = stats->sw_stats; 8392 u64 *masks = stats->hw_masks; 8393 int cnt; 8394 8395 cnt = sizeof(struct rx_port_stats) / 8; 8396 __bnxt_accumulate_stats(hw_stats, sw_stats, masks, cnt, false); 8397 8398 hw_stats += BNXT_TX_PORT_STATS_BYTE_OFFSET / 8; 8399 sw_stats += BNXT_TX_PORT_STATS_BYTE_OFFSET / 8; 8400 masks += BNXT_TX_PORT_STATS_BYTE_OFFSET / 8; 8401 cnt = sizeof(struct tx_port_stats) / 8; 8402 __bnxt_accumulate_stats(hw_stats, sw_stats, masks, cnt, false); 8403 } 8404 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) { 8405 bnxt_accumulate_stats(&bp->rx_port_stats_ext); 8406 bnxt_accumulate_stats(&bp->tx_port_stats_ext); 8407 } 8408 } 8409 8410 static int bnxt_hwrm_port_qstats(struct bnxt *bp, u8 flags) 8411 { 8412 struct hwrm_port_qstats_input *req; 8413 struct bnxt_pf_info *pf = &bp->pf; 8414 int rc; 8415 8416 if (!(bp->flags & BNXT_FLAG_PORT_STATS)) 8417 return 0; 8418 8419 if (flags && !(bp->fw_cap & BNXT_FW_CAP_EXT_HW_STATS_SUPPORTED)) 8420 return -EOPNOTSUPP; 8421 8422 rc = hwrm_req_init(bp, req, HWRM_PORT_QSTATS); 8423 if (rc) 8424 return rc; 8425 8426 req->flags = flags; 8427 req->port_id = cpu_to_le16(pf->port_id); 8428 req->tx_stat_host_addr = cpu_to_le64(bp->port_stats.hw_stats_map + 8429 BNXT_TX_PORT_STATS_BYTE_OFFSET); 8430 req->rx_stat_host_addr = cpu_to_le64(bp->port_stats.hw_stats_map); 8431 return hwrm_req_send(bp, req); 8432 } 8433 8434 static int bnxt_hwrm_port_qstats_ext(struct bnxt *bp, u8 flags) 8435 { 8436 struct hwrm_queue_pri2cos_qcfg_output *resp_qc; 8437 struct hwrm_queue_pri2cos_qcfg_input *req_qc; 8438 struct hwrm_port_qstats_ext_output *resp_qs; 8439 struct hwrm_port_qstats_ext_input *req_qs; 8440 struct bnxt_pf_info *pf = &bp->pf; 8441 u32 tx_stat_size; 8442 int rc; 8443 8444 if (!(bp->flags & BNXT_FLAG_PORT_STATS_EXT)) 8445 return 0; 8446 8447 if (flags && !(bp->fw_cap & BNXT_FW_CAP_EXT_HW_STATS_SUPPORTED)) 8448 return -EOPNOTSUPP; 8449 8450 rc = hwrm_req_init(bp, req_qs, HWRM_PORT_QSTATS_EXT); 8451 if (rc) 8452 return rc; 8453 8454 req_qs->flags = flags; 8455 req_qs->port_id = cpu_to_le16(pf->port_id); 8456 req_qs->rx_stat_size = cpu_to_le16(sizeof(struct rx_port_stats_ext)); 8457 req_qs->rx_stat_host_addr = cpu_to_le64(bp->rx_port_stats_ext.hw_stats_map); 8458 tx_stat_size = bp->tx_port_stats_ext.hw_stats ? 8459 sizeof(struct tx_port_stats_ext) : 0; 8460 req_qs->tx_stat_size = cpu_to_le16(tx_stat_size); 8461 req_qs->tx_stat_host_addr = cpu_to_le64(bp->tx_port_stats_ext.hw_stats_map); 8462 resp_qs = hwrm_req_hold(bp, req_qs); 8463 rc = hwrm_req_send(bp, req_qs); 8464 if (!rc) { 8465 bp->fw_rx_stats_ext_size = 8466 le16_to_cpu(resp_qs->rx_stat_size) / 8; 8467 if (BNXT_FW_MAJ(bp) < 220 && 8468 bp->fw_rx_stats_ext_size > BNXT_RX_STATS_EXT_NUM_LEGACY) 8469 bp->fw_rx_stats_ext_size = BNXT_RX_STATS_EXT_NUM_LEGACY; 8470 8471 bp->fw_tx_stats_ext_size = tx_stat_size ? 8472 le16_to_cpu(resp_qs->tx_stat_size) / 8 : 0; 8473 } else { 8474 bp->fw_rx_stats_ext_size = 0; 8475 bp->fw_tx_stats_ext_size = 0; 8476 } 8477 hwrm_req_drop(bp, req_qs); 8478 8479 if (flags) 8480 return rc; 8481 8482 if (bp->fw_tx_stats_ext_size <= 8483 offsetof(struct tx_port_stats_ext, pfc_pri0_tx_duration_us) / 8) { 8484 bp->pri2cos_valid = 0; 8485 return rc; 8486 } 8487 8488 rc = hwrm_req_init(bp, req_qc, HWRM_QUEUE_PRI2COS_QCFG); 8489 if (rc) 8490 return rc; 8491 8492 req_qc->flags = cpu_to_le32(QUEUE_PRI2COS_QCFG_REQ_FLAGS_IVLAN); 8493 8494 resp_qc = hwrm_req_hold(bp, req_qc); 8495 rc = hwrm_req_send(bp, req_qc); 8496 if (!rc) { 8497 u8 *pri2cos; 8498 int i, j; 8499 8500 pri2cos = &resp_qc->pri0_cos_queue_id; 8501 for (i = 0; i < 8; i++) { 8502 u8 queue_id = pri2cos[i]; 8503 u8 queue_idx; 8504 8505 /* Per port queue IDs start from 0, 10, 20, etc */ 8506 queue_idx = queue_id % 10; 8507 if (queue_idx > BNXT_MAX_QUEUE) { 8508 bp->pri2cos_valid = false; 8509 hwrm_req_drop(bp, req_qc); 8510 return rc; 8511 } 8512 for (j = 0; j < bp->max_q; j++) { 8513 if (bp->q_ids[j] == queue_id) 8514 bp->pri2cos_idx[i] = queue_idx; 8515 } 8516 } 8517 bp->pri2cos_valid = true; 8518 } 8519 hwrm_req_drop(bp, req_qc); 8520 8521 return rc; 8522 } 8523 8524 static void bnxt_hwrm_free_tunnel_ports(struct bnxt *bp) 8525 { 8526 bnxt_hwrm_tunnel_dst_port_free(bp, 8527 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN); 8528 bnxt_hwrm_tunnel_dst_port_free(bp, 8529 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE); 8530 } 8531 8532 static int bnxt_set_tpa(struct bnxt *bp, bool set_tpa) 8533 { 8534 int rc, i; 8535 u32 tpa_flags = 0; 8536 8537 if (set_tpa) 8538 tpa_flags = bp->flags & BNXT_FLAG_TPA; 8539 else if (BNXT_NO_FW_ACCESS(bp)) 8540 return 0; 8541 for (i = 0; i < bp->nr_vnics; i++) { 8542 rc = bnxt_hwrm_vnic_set_tpa(bp, i, tpa_flags); 8543 if (rc) { 8544 netdev_err(bp->dev, "hwrm vnic set tpa failure rc for vnic %d: %x\n", 8545 i, rc); 8546 return rc; 8547 } 8548 } 8549 return 0; 8550 } 8551 8552 static void bnxt_hwrm_clear_vnic_rss(struct bnxt *bp) 8553 { 8554 int i; 8555 8556 for (i = 0; i < bp->nr_vnics; i++) 8557 bnxt_hwrm_vnic_set_rss(bp, i, false); 8558 } 8559 8560 static void bnxt_clear_vnic(struct bnxt *bp) 8561 { 8562 if (!bp->vnic_info) 8563 return; 8564 8565 bnxt_hwrm_clear_vnic_filter(bp); 8566 if (!(bp->flags & BNXT_FLAG_CHIP_P5)) { 8567 /* clear all RSS setting before free vnic ctx */ 8568 bnxt_hwrm_clear_vnic_rss(bp); 8569 bnxt_hwrm_vnic_ctx_free(bp); 8570 } 8571 /* before free the vnic, undo the vnic tpa settings */ 8572 if (bp->flags & BNXT_FLAG_TPA) 8573 bnxt_set_tpa(bp, false); 8574 bnxt_hwrm_vnic_free(bp); 8575 if (bp->flags & BNXT_FLAG_CHIP_P5) 8576 bnxt_hwrm_vnic_ctx_free(bp); 8577 } 8578 8579 static void bnxt_hwrm_resource_free(struct bnxt *bp, bool close_path, 8580 bool irq_re_init) 8581 { 8582 bnxt_clear_vnic(bp); 8583 bnxt_hwrm_ring_free(bp, close_path); 8584 bnxt_hwrm_ring_grp_free(bp); 8585 if (irq_re_init) { 8586 bnxt_hwrm_stat_ctx_free(bp); 8587 bnxt_hwrm_free_tunnel_ports(bp); 8588 } 8589 } 8590 8591 static int bnxt_hwrm_set_br_mode(struct bnxt *bp, u16 br_mode) 8592 { 8593 struct hwrm_func_cfg_input *req; 8594 u8 evb_mode; 8595 int rc; 8596 8597 if (br_mode == BRIDGE_MODE_VEB) 8598 evb_mode = FUNC_CFG_REQ_EVB_MODE_VEB; 8599 else if (br_mode == BRIDGE_MODE_VEPA) 8600 evb_mode = FUNC_CFG_REQ_EVB_MODE_VEPA; 8601 else 8602 return -EINVAL; 8603 8604 rc = hwrm_req_init(bp, req, HWRM_FUNC_CFG); 8605 if (rc) 8606 return rc; 8607 8608 req->fid = cpu_to_le16(0xffff); 8609 req->enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_EVB_MODE); 8610 req->evb_mode = evb_mode; 8611 return hwrm_req_send(bp, req); 8612 } 8613 8614 static int bnxt_hwrm_set_cache_line_size(struct bnxt *bp, int size) 8615 { 8616 struct hwrm_func_cfg_input *req; 8617 int rc; 8618 8619 if (BNXT_VF(bp) || bp->hwrm_spec_code < 0x10803) 8620 return 0; 8621 8622 rc = hwrm_req_init(bp, req, HWRM_FUNC_CFG); 8623 if (rc) 8624 return rc; 8625 8626 req->fid = cpu_to_le16(0xffff); 8627 req->enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_CACHE_LINESIZE); 8628 req->options = FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_64; 8629 if (size == 128) 8630 req->options = FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128; 8631 8632 return hwrm_req_send(bp, req); 8633 } 8634 8635 static int __bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id) 8636 { 8637 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 8638 int rc; 8639 8640 if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG) 8641 goto skip_rss_ctx; 8642 8643 /* allocate context for vnic */ 8644 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 0); 8645 if (rc) { 8646 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n", 8647 vnic_id, rc); 8648 goto vnic_setup_err; 8649 } 8650 bp->rsscos_nr_ctxs++; 8651 8652 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) { 8653 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 1); 8654 if (rc) { 8655 netdev_err(bp->dev, "hwrm vnic %d cos ctx alloc failure rc: %x\n", 8656 vnic_id, rc); 8657 goto vnic_setup_err; 8658 } 8659 bp->rsscos_nr_ctxs++; 8660 } 8661 8662 skip_rss_ctx: 8663 /* configure default vnic, ring grp */ 8664 rc = bnxt_hwrm_vnic_cfg(bp, vnic_id); 8665 if (rc) { 8666 netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n", 8667 vnic_id, rc); 8668 goto vnic_setup_err; 8669 } 8670 8671 /* Enable RSS hashing on vnic */ 8672 rc = bnxt_hwrm_vnic_set_rss(bp, vnic_id, true); 8673 if (rc) { 8674 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %x\n", 8675 vnic_id, rc); 8676 goto vnic_setup_err; 8677 } 8678 8679 if (bp->flags & BNXT_FLAG_AGG_RINGS) { 8680 rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id); 8681 if (rc) { 8682 netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n", 8683 vnic_id, rc); 8684 } 8685 } 8686 8687 vnic_setup_err: 8688 return rc; 8689 } 8690 8691 static int __bnxt_setup_vnic_p5(struct bnxt *bp, u16 vnic_id) 8692 { 8693 int rc, i, nr_ctxs; 8694 8695 nr_ctxs = bnxt_get_nr_rss_ctxs(bp, bp->rx_nr_rings); 8696 for (i = 0; i < nr_ctxs; i++) { 8697 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, i); 8698 if (rc) { 8699 netdev_err(bp->dev, "hwrm vnic %d ctx %d alloc failure rc: %x\n", 8700 vnic_id, i, rc); 8701 break; 8702 } 8703 bp->rsscos_nr_ctxs++; 8704 } 8705 if (i < nr_ctxs) 8706 return -ENOMEM; 8707 8708 rc = bnxt_hwrm_vnic_set_rss_p5(bp, vnic_id, true); 8709 if (rc) { 8710 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %d\n", 8711 vnic_id, rc); 8712 return rc; 8713 } 8714 rc = bnxt_hwrm_vnic_cfg(bp, vnic_id); 8715 if (rc) { 8716 netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n", 8717 vnic_id, rc); 8718 return rc; 8719 } 8720 if (bp->flags & BNXT_FLAG_AGG_RINGS) { 8721 rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id); 8722 if (rc) { 8723 netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n", 8724 vnic_id, rc); 8725 } 8726 } 8727 return rc; 8728 } 8729 8730 static int bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id) 8731 { 8732 if (bp->flags & BNXT_FLAG_CHIP_P5) 8733 return __bnxt_setup_vnic_p5(bp, vnic_id); 8734 else 8735 return __bnxt_setup_vnic(bp, vnic_id); 8736 } 8737 8738 static int bnxt_alloc_rfs_vnics(struct bnxt *bp) 8739 { 8740 #ifdef CONFIG_RFS_ACCEL 8741 int i, rc = 0; 8742 8743 if (bp->flags & BNXT_FLAG_CHIP_P5) 8744 return 0; 8745 8746 for (i = 0; i < bp->rx_nr_rings; i++) { 8747 struct bnxt_vnic_info *vnic; 8748 u16 vnic_id = i + 1; 8749 u16 ring_id = i; 8750 8751 if (vnic_id >= bp->nr_vnics) 8752 break; 8753 8754 vnic = &bp->vnic_info[vnic_id]; 8755 vnic->flags |= BNXT_VNIC_RFS_FLAG; 8756 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP) 8757 vnic->flags |= BNXT_VNIC_RFS_NEW_RSS_FLAG; 8758 rc = bnxt_hwrm_vnic_alloc(bp, vnic_id, ring_id, 1); 8759 if (rc) { 8760 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n", 8761 vnic_id, rc); 8762 break; 8763 } 8764 rc = bnxt_setup_vnic(bp, vnic_id); 8765 if (rc) 8766 break; 8767 } 8768 return rc; 8769 #else 8770 return 0; 8771 #endif 8772 } 8773 8774 /* Allow PF, trusted VFs and VFs with default VLAN to be in promiscuous mode */ 8775 static bool bnxt_promisc_ok(struct bnxt *bp) 8776 { 8777 #ifdef CONFIG_BNXT_SRIOV 8778 if (BNXT_VF(bp) && !bp->vf.vlan && !bnxt_is_trusted_vf(bp, &bp->vf)) 8779 return false; 8780 #endif 8781 return true; 8782 } 8783 8784 static int bnxt_setup_nitroa0_vnic(struct bnxt *bp) 8785 { 8786 unsigned int rc = 0; 8787 8788 rc = bnxt_hwrm_vnic_alloc(bp, 1, bp->rx_nr_rings - 1, 1); 8789 if (rc) { 8790 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n", 8791 rc); 8792 return rc; 8793 } 8794 8795 rc = bnxt_hwrm_vnic_cfg(bp, 1); 8796 if (rc) { 8797 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n", 8798 rc); 8799 return rc; 8800 } 8801 return rc; 8802 } 8803 8804 static int bnxt_cfg_rx_mode(struct bnxt *); 8805 static bool bnxt_mc_list_updated(struct bnxt *, u32 *); 8806 8807 static int bnxt_init_chip(struct bnxt *bp, bool irq_re_init) 8808 { 8809 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 8810 int rc = 0; 8811 unsigned int rx_nr_rings = bp->rx_nr_rings; 8812 8813 if (irq_re_init) { 8814 rc = bnxt_hwrm_stat_ctx_alloc(bp); 8815 if (rc) { 8816 netdev_err(bp->dev, "hwrm stat ctx alloc failure rc: %x\n", 8817 rc); 8818 goto err_out; 8819 } 8820 } 8821 8822 rc = bnxt_hwrm_ring_alloc(bp); 8823 if (rc) { 8824 netdev_err(bp->dev, "hwrm ring alloc failure rc: %x\n", rc); 8825 goto err_out; 8826 } 8827 8828 rc = bnxt_hwrm_ring_grp_alloc(bp); 8829 if (rc) { 8830 netdev_err(bp->dev, "hwrm_ring_grp alloc failure: %x\n", rc); 8831 goto err_out; 8832 } 8833 8834 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 8835 rx_nr_rings--; 8836 8837 /* default vnic 0 */ 8838 rc = bnxt_hwrm_vnic_alloc(bp, 0, 0, rx_nr_rings); 8839 if (rc) { 8840 netdev_err(bp->dev, "hwrm vnic alloc failure rc: %x\n", rc); 8841 goto err_out; 8842 } 8843 8844 if (BNXT_VF(bp)) 8845 bnxt_hwrm_func_qcfg(bp); 8846 8847 rc = bnxt_setup_vnic(bp, 0); 8848 if (rc) 8849 goto err_out; 8850 if (bp->fw_cap & BNXT_FW_CAP_RSS_HASH_TYPE_DELTA) 8851 bnxt_hwrm_update_rss_hash_cfg(bp); 8852 8853 if (bp->flags & BNXT_FLAG_RFS) { 8854 rc = bnxt_alloc_rfs_vnics(bp); 8855 if (rc) 8856 goto err_out; 8857 } 8858 8859 if (bp->flags & BNXT_FLAG_TPA) { 8860 rc = bnxt_set_tpa(bp, true); 8861 if (rc) 8862 goto err_out; 8863 } 8864 8865 if (BNXT_VF(bp)) 8866 bnxt_update_vf_mac(bp); 8867 8868 /* Filter for default vnic 0 */ 8869 rc = bnxt_hwrm_set_vnic_filter(bp, 0, 0, bp->dev->dev_addr); 8870 if (rc) { 8871 if (BNXT_VF(bp) && rc == -ENODEV) 8872 netdev_err(bp->dev, "Cannot configure L2 filter while PF is unavailable\n"); 8873 else 8874 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n", rc); 8875 goto err_out; 8876 } 8877 vnic->uc_filter_count = 1; 8878 8879 vnic->rx_mask = 0; 8880 if (test_bit(BNXT_STATE_HALF_OPEN, &bp->state)) 8881 goto skip_rx_mask; 8882 8883 if (bp->dev->flags & IFF_BROADCAST) 8884 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_BCAST; 8885 8886 if (bp->dev->flags & IFF_PROMISC) 8887 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS; 8888 8889 if (bp->dev->flags & IFF_ALLMULTI) { 8890 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST; 8891 vnic->mc_list_count = 0; 8892 } else if (bp->dev->flags & IFF_MULTICAST) { 8893 u32 mask = 0; 8894 8895 bnxt_mc_list_updated(bp, &mask); 8896 vnic->rx_mask |= mask; 8897 } 8898 8899 rc = bnxt_cfg_rx_mode(bp); 8900 if (rc) 8901 goto err_out; 8902 8903 skip_rx_mask: 8904 rc = bnxt_hwrm_set_coal(bp); 8905 if (rc) 8906 netdev_warn(bp->dev, "HWRM set coalescing failure rc: %x\n", 8907 rc); 8908 8909 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) { 8910 rc = bnxt_setup_nitroa0_vnic(bp); 8911 if (rc) 8912 netdev_err(bp->dev, "Special vnic setup failure for NS2 A0 rc: %x\n", 8913 rc); 8914 } 8915 8916 if (BNXT_VF(bp)) { 8917 bnxt_hwrm_func_qcfg(bp); 8918 netdev_update_features(bp->dev); 8919 } 8920 8921 return 0; 8922 8923 err_out: 8924 bnxt_hwrm_resource_free(bp, 0, true); 8925 8926 return rc; 8927 } 8928 8929 static int bnxt_shutdown_nic(struct bnxt *bp, bool irq_re_init) 8930 { 8931 bnxt_hwrm_resource_free(bp, 1, irq_re_init); 8932 return 0; 8933 } 8934 8935 static int bnxt_init_nic(struct bnxt *bp, bool irq_re_init) 8936 { 8937 bnxt_init_cp_rings(bp); 8938 bnxt_init_rx_rings(bp); 8939 bnxt_init_tx_rings(bp); 8940 bnxt_init_ring_grps(bp, irq_re_init); 8941 bnxt_init_vnics(bp); 8942 8943 return bnxt_init_chip(bp, irq_re_init); 8944 } 8945 8946 static int bnxt_set_real_num_queues(struct bnxt *bp) 8947 { 8948 int rc; 8949 struct net_device *dev = bp->dev; 8950 8951 rc = netif_set_real_num_tx_queues(dev, bp->tx_nr_rings - 8952 bp->tx_nr_rings_xdp); 8953 if (rc) 8954 return rc; 8955 8956 rc = netif_set_real_num_rx_queues(dev, bp->rx_nr_rings); 8957 if (rc) 8958 return rc; 8959 8960 #ifdef CONFIG_RFS_ACCEL 8961 if (bp->flags & BNXT_FLAG_RFS) 8962 dev->rx_cpu_rmap = alloc_irq_cpu_rmap(bp->rx_nr_rings); 8963 #endif 8964 8965 return rc; 8966 } 8967 8968 static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max, 8969 bool shared) 8970 { 8971 int _rx = *rx, _tx = *tx; 8972 8973 if (shared) { 8974 *rx = min_t(int, _rx, max); 8975 *tx = min_t(int, _tx, max); 8976 } else { 8977 if (max < 2) 8978 return -ENOMEM; 8979 8980 while (_rx + _tx > max) { 8981 if (_rx > _tx && _rx > 1) 8982 _rx--; 8983 else if (_tx > 1) 8984 _tx--; 8985 } 8986 *rx = _rx; 8987 *tx = _tx; 8988 } 8989 return 0; 8990 } 8991 8992 static void bnxt_setup_msix(struct bnxt *bp) 8993 { 8994 const int len = sizeof(bp->irq_tbl[0].name); 8995 struct net_device *dev = bp->dev; 8996 int tcs, i; 8997 8998 tcs = netdev_get_num_tc(dev); 8999 if (tcs) { 9000 int i, off, count; 9001 9002 for (i = 0; i < tcs; i++) { 9003 count = bp->tx_nr_rings_per_tc; 9004 off = i * count; 9005 netdev_set_tc_queue(dev, i, count, off); 9006 } 9007 } 9008 9009 for (i = 0; i < bp->cp_nr_rings; i++) { 9010 int map_idx = bnxt_cp_num_to_irq_num(bp, i); 9011 char *attr; 9012 9013 if (bp->flags & BNXT_FLAG_SHARED_RINGS) 9014 attr = "TxRx"; 9015 else if (i < bp->rx_nr_rings) 9016 attr = "rx"; 9017 else 9018 attr = "tx"; 9019 9020 snprintf(bp->irq_tbl[map_idx].name, len, "%s-%s-%d", dev->name, 9021 attr, i); 9022 bp->irq_tbl[map_idx].handler = bnxt_msix; 9023 } 9024 } 9025 9026 static void bnxt_setup_inta(struct bnxt *bp) 9027 { 9028 const int len = sizeof(bp->irq_tbl[0].name); 9029 9030 if (netdev_get_num_tc(bp->dev)) 9031 netdev_reset_tc(bp->dev); 9032 9033 snprintf(bp->irq_tbl[0].name, len, "%s-%s-%d", bp->dev->name, "TxRx", 9034 0); 9035 bp->irq_tbl[0].handler = bnxt_inta; 9036 } 9037 9038 static int bnxt_init_int_mode(struct bnxt *bp); 9039 9040 static int bnxt_setup_int_mode(struct bnxt *bp) 9041 { 9042 int rc; 9043 9044 if (!bp->irq_tbl) { 9045 rc = bnxt_init_int_mode(bp); 9046 if (rc || !bp->irq_tbl) 9047 return rc ?: -ENODEV; 9048 } 9049 9050 if (bp->flags & BNXT_FLAG_USING_MSIX) 9051 bnxt_setup_msix(bp); 9052 else 9053 bnxt_setup_inta(bp); 9054 9055 rc = bnxt_set_real_num_queues(bp); 9056 return rc; 9057 } 9058 9059 #ifdef CONFIG_RFS_ACCEL 9060 static unsigned int bnxt_get_max_func_rss_ctxs(struct bnxt *bp) 9061 { 9062 return bp->hw_resc.max_rsscos_ctxs; 9063 } 9064 9065 static unsigned int bnxt_get_max_func_vnics(struct bnxt *bp) 9066 { 9067 return bp->hw_resc.max_vnics; 9068 } 9069 #endif 9070 9071 unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt *bp) 9072 { 9073 return bp->hw_resc.max_stat_ctxs; 9074 } 9075 9076 unsigned int bnxt_get_max_func_cp_rings(struct bnxt *bp) 9077 { 9078 return bp->hw_resc.max_cp_rings; 9079 } 9080 9081 static unsigned int bnxt_get_max_func_cp_rings_for_en(struct bnxt *bp) 9082 { 9083 unsigned int cp = bp->hw_resc.max_cp_rings; 9084 9085 if (!(bp->flags & BNXT_FLAG_CHIP_P5)) 9086 cp -= bnxt_get_ulp_msix_num(bp); 9087 9088 return cp; 9089 } 9090 9091 static unsigned int bnxt_get_max_func_irqs(struct bnxt *bp) 9092 { 9093 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 9094 9095 if (bp->flags & BNXT_FLAG_CHIP_P5) 9096 return min_t(unsigned int, hw_resc->max_irqs, hw_resc->max_nqs); 9097 9098 return min_t(unsigned int, hw_resc->max_irqs, hw_resc->max_cp_rings); 9099 } 9100 9101 static void bnxt_set_max_func_irqs(struct bnxt *bp, unsigned int max_irqs) 9102 { 9103 bp->hw_resc.max_irqs = max_irqs; 9104 } 9105 9106 unsigned int bnxt_get_avail_cp_rings_for_en(struct bnxt *bp) 9107 { 9108 unsigned int cp; 9109 9110 cp = bnxt_get_max_func_cp_rings_for_en(bp); 9111 if (bp->flags & BNXT_FLAG_CHIP_P5) 9112 return cp - bp->rx_nr_rings - bp->tx_nr_rings; 9113 else 9114 return cp - bp->cp_nr_rings; 9115 } 9116 9117 unsigned int bnxt_get_avail_stat_ctxs_for_en(struct bnxt *bp) 9118 { 9119 return bnxt_get_max_func_stat_ctxs(bp) - bnxt_get_func_stat_ctxs(bp); 9120 } 9121 9122 int bnxt_get_avail_msix(struct bnxt *bp, int num) 9123 { 9124 int max_cp = bnxt_get_max_func_cp_rings(bp); 9125 int max_irq = bnxt_get_max_func_irqs(bp); 9126 int total_req = bp->cp_nr_rings + num; 9127 int max_idx, avail_msix; 9128 9129 max_idx = bp->total_irqs; 9130 if (!(bp->flags & BNXT_FLAG_CHIP_P5)) 9131 max_idx = min_t(int, bp->total_irqs, max_cp); 9132 avail_msix = max_idx - bp->cp_nr_rings; 9133 if (!BNXT_NEW_RM(bp) || avail_msix >= num) 9134 return avail_msix; 9135 9136 if (max_irq < total_req) { 9137 num = max_irq - bp->cp_nr_rings; 9138 if (num <= 0) 9139 return 0; 9140 } 9141 return num; 9142 } 9143 9144 static int bnxt_get_num_msix(struct bnxt *bp) 9145 { 9146 if (!BNXT_NEW_RM(bp)) 9147 return bnxt_get_max_func_irqs(bp); 9148 9149 return bnxt_nq_rings_in_use(bp); 9150 } 9151 9152 static int bnxt_init_msix(struct bnxt *bp) 9153 { 9154 int i, total_vecs, max, rc = 0, min = 1, ulp_msix; 9155 struct msix_entry *msix_ent; 9156 9157 total_vecs = bnxt_get_num_msix(bp); 9158 max = bnxt_get_max_func_irqs(bp); 9159 if (total_vecs > max) 9160 total_vecs = max; 9161 9162 if (!total_vecs) 9163 return 0; 9164 9165 msix_ent = kcalloc(total_vecs, sizeof(struct msix_entry), GFP_KERNEL); 9166 if (!msix_ent) 9167 return -ENOMEM; 9168 9169 for (i = 0; i < total_vecs; i++) { 9170 msix_ent[i].entry = i; 9171 msix_ent[i].vector = 0; 9172 } 9173 9174 if (!(bp->flags & BNXT_FLAG_SHARED_RINGS)) 9175 min = 2; 9176 9177 total_vecs = pci_enable_msix_range(bp->pdev, msix_ent, min, total_vecs); 9178 ulp_msix = bnxt_get_ulp_msix_num(bp); 9179 if (total_vecs < 0 || total_vecs < ulp_msix) { 9180 rc = -ENODEV; 9181 goto msix_setup_exit; 9182 } 9183 9184 bp->irq_tbl = kcalloc(total_vecs, sizeof(struct bnxt_irq), GFP_KERNEL); 9185 if (bp->irq_tbl) { 9186 for (i = 0; i < total_vecs; i++) 9187 bp->irq_tbl[i].vector = msix_ent[i].vector; 9188 9189 bp->total_irqs = total_vecs; 9190 /* Trim rings based upon num of vectors allocated */ 9191 rc = bnxt_trim_rings(bp, &bp->rx_nr_rings, &bp->tx_nr_rings, 9192 total_vecs - ulp_msix, min == 1); 9193 if (rc) 9194 goto msix_setup_exit; 9195 9196 bp->cp_nr_rings = (min == 1) ? 9197 max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) : 9198 bp->tx_nr_rings + bp->rx_nr_rings; 9199 9200 } else { 9201 rc = -ENOMEM; 9202 goto msix_setup_exit; 9203 } 9204 bp->flags |= BNXT_FLAG_USING_MSIX; 9205 kfree(msix_ent); 9206 return 0; 9207 9208 msix_setup_exit: 9209 netdev_err(bp->dev, "bnxt_init_msix err: %x\n", rc); 9210 kfree(bp->irq_tbl); 9211 bp->irq_tbl = NULL; 9212 pci_disable_msix(bp->pdev); 9213 kfree(msix_ent); 9214 return rc; 9215 } 9216 9217 static int bnxt_init_inta(struct bnxt *bp) 9218 { 9219 bp->irq_tbl = kzalloc(sizeof(struct bnxt_irq), GFP_KERNEL); 9220 if (!bp->irq_tbl) 9221 return -ENOMEM; 9222 9223 bp->total_irqs = 1; 9224 bp->rx_nr_rings = 1; 9225 bp->tx_nr_rings = 1; 9226 bp->cp_nr_rings = 1; 9227 bp->flags |= BNXT_FLAG_SHARED_RINGS; 9228 bp->irq_tbl[0].vector = bp->pdev->irq; 9229 return 0; 9230 } 9231 9232 static int bnxt_init_int_mode(struct bnxt *bp) 9233 { 9234 int rc = -ENODEV; 9235 9236 if (bp->flags & BNXT_FLAG_MSIX_CAP) 9237 rc = bnxt_init_msix(bp); 9238 9239 if (!(bp->flags & BNXT_FLAG_USING_MSIX) && BNXT_PF(bp)) { 9240 /* fallback to INTA */ 9241 rc = bnxt_init_inta(bp); 9242 } 9243 return rc; 9244 } 9245 9246 static void bnxt_clear_int_mode(struct bnxt *bp) 9247 { 9248 if (bp->flags & BNXT_FLAG_USING_MSIX) 9249 pci_disable_msix(bp->pdev); 9250 9251 kfree(bp->irq_tbl); 9252 bp->irq_tbl = NULL; 9253 bp->flags &= ~BNXT_FLAG_USING_MSIX; 9254 } 9255 9256 int bnxt_reserve_rings(struct bnxt *bp, bool irq_re_init) 9257 { 9258 int tcs = netdev_get_num_tc(bp->dev); 9259 bool irq_cleared = false; 9260 int rc; 9261 9262 if (!bnxt_need_reserve_rings(bp)) 9263 return 0; 9264 9265 if (irq_re_init && BNXT_NEW_RM(bp) && 9266 bnxt_get_num_msix(bp) != bp->total_irqs) { 9267 bnxt_ulp_irq_stop(bp); 9268 bnxt_clear_int_mode(bp); 9269 irq_cleared = true; 9270 } 9271 rc = __bnxt_reserve_rings(bp); 9272 if (irq_cleared) { 9273 if (!rc) 9274 rc = bnxt_init_int_mode(bp); 9275 bnxt_ulp_irq_restart(bp, rc); 9276 } 9277 if (rc) { 9278 netdev_err(bp->dev, "ring reservation/IRQ init failure rc: %d\n", rc); 9279 return rc; 9280 } 9281 if (tcs && (bp->tx_nr_rings_per_tc * tcs != 9282 bp->tx_nr_rings - bp->tx_nr_rings_xdp)) { 9283 netdev_err(bp->dev, "tx ring reservation failure\n"); 9284 netdev_reset_tc(bp->dev); 9285 if (bp->tx_nr_rings_xdp) 9286 bp->tx_nr_rings_per_tc = bp->tx_nr_rings_xdp; 9287 else 9288 bp->tx_nr_rings_per_tc = bp->tx_nr_rings; 9289 return -ENOMEM; 9290 } 9291 return 0; 9292 } 9293 9294 static void bnxt_free_irq(struct bnxt *bp) 9295 { 9296 struct bnxt_irq *irq; 9297 int i; 9298 9299 #ifdef CONFIG_RFS_ACCEL 9300 free_irq_cpu_rmap(bp->dev->rx_cpu_rmap); 9301 bp->dev->rx_cpu_rmap = NULL; 9302 #endif 9303 if (!bp->irq_tbl || !bp->bnapi) 9304 return; 9305 9306 for (i = 0; i < bp->cp_nr_rings; i++) { 9307 int map_idx = bnxt_cp_num_to_irq_num(bp, i); 9308 9309 irq = &bp->irq_tbl[map_idx]; 9310 if (irq->requested) { 9311 if (irq->have_cpumask) { 9312 irq_set_affinity_hint(irq->vector, NULL); 9313 free_cpumask_var(irq->cpu_mask); 9314 irq->have_cpumask = 0; 9315 } 9316 free_irq(irq->vector, bp->bnapi[i]); 9317 } 9318 9319 irq->requested = 0; 9320 } 9321 } 9322 9323 static int bnxt_request_irq(struct bnxt *bp) 9324 { 9325 int i, j, rc = 0; 9326 unsigned long flags = 0; 9327 #ifdef CONFIG_RFS_ACCEL 9328 struct cpu_rmap *rmap; 9329 #endif 9330 9331 rc = bnxt_setup_int_mode(bp); 9332 if (rc) { 9333 netdev_err(bp->dev, "bnxt_setup_int_mode err: %x\n", 9334 rc); 9335 return rc; 9336 } 9337 #ifdef CONFIG_RFS_ACCEL 9338 rmap = bp->dev->rx_cpu_rmap; 9339 #endif 9340 if (!(bp->flags & BNXT_FLAG_USING_MSIX)) 9341 flags = IRQF_SHARED; 9342 9343 for (i = 0, j = 0; i < bp->cp_nr_rings; i++) { 9344 int map_idx = bnxt_cp_num_to_irq_num(bp, i); 9345 struct bnxt_irq *irq = &bp->irq_tbl[map_idx]; 9346 9347 #ifdef CONFIG_RFS_ACCEL 9348 if (rmap && bp->bnapi[i]->rx_ring) { 9349 rc = irq_cpu_rmap_add(rmap, irq->vector); 9350 if (rc) 9351 netdev_warn(bp->dev, "failed adding irq rmap for ring %d\n", 9352 j); 9353 j++; 9354 } 9355 #endif 9356 rc = request_irq(irq->vector, irq->handler, flags, irq->name, 9357 bp->bnapi[i]); 9358 if (rc) 9359 break; 9360 9361 irq->requested = 1; 9362 9363 if (zalloc_cpumask_var(&irq->cpu_mask, GFP_KERNEL)) { 9364 int numa_node = dev_to_node(&bp->pdev->dev); 9365 9366 irq->have_cpumask = 1; 9367 cpumask_set_cpu(cpumask_local_spread(i, numa_node), 9368 irq->cpu_mask); 9369 rc = irq_set_affinity_hint(irq->vector, irq->cpu_mask); 9370 if (rc) { 9371 netdev_warn(bp->dev, 9372 "Set affinity failed, IRQ = %d\n", 9373 irq->vector); 9374 break; 9375 } 9376 } 9377 } 9378 return rc; 9379 } 9380 9381 static void bnxt_del_napi(struct bnxt *bp) 9382 { 9383 int i; 9384 9385 if (!bp->bnapi) 9386 return; 9387 9388 for (i = 0; i < bp->cp_nr_rings; i++) { 9389 struct bnxt_napi *bnapi = bp->bnapi[i]; 9390 9391 __netif_napi_del(&bnapi->napi); 9392 } 9393 /* We called __netif_napi_del(), we need 9394 * to respect an RCU grace period before freeing napi structures. 9395 */ 9396 synchronize_net(); 9397 } 9398 9399 static void bnxt_init_napi(struct bnxt *bp) 9400 { 9401 int i; 9402 unsigned int cp_nr_rings = bp->cp_nr_rings; 9403 struct bnxt_napi *bnapi; 9404 9405 if (bp->flags & BNXT_FLAG_USING_MSIX) { 9406 int (*poll_fn)(struct napi_struct *, int) = bnxt_poll; 9407 9408 if (bp->flags & BNXT_FLAG_CHIP_P5) 9409 poll_fn = bnxt_poll_p5; 9410 else if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 9411 cp_nr_rings--; 9412 for (i = 0; i < cp_nr_rings; i++) { 9413 bnapi = bp->bnapi[i]; 9414 netif_napi_add(bp->dev, &bnapi->napi, poll_fn); 9415 } 9416 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) { 9417 bnapi = bp->bnapi[cp_nr_rings]; 9418 netif_napi_add(bp->dev, &bnapi->napi, 9419 bnxt_poll_nitroa0); 9420 } 9421 } else { 9422 bnapi = bp->bnapi[0]; 9423 netif_napi_add(bp->dev, &bnapi->napi, bnxt_poll); 9424 } 9425 } 9426 9427 static void bnxt_disable_napi(struct bnxt *bp) 9428 { 9429 int i; 9430 9431 if (!bp->bnapi || 9432 test_and_set_bit(BNXT_STATE_NAPI_DISABLED, &bp->state)) 9433 return; 9434 9435 for (i = 0; i < bp->cp_nr_rings; i++) { 9436 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring; 9437 9438 napi_disable(&bp->bnapi[i]->napi); 9439 if (bp->bnapi[i]->rx_ring) 9440 cancel_work_sync(&cpr->dim.work); 9441 } 9442 } 9443 9444 static void bnxt_enable_napi(struct bnxt *bp) 9445 { 9446 int i; 9447 9448 clear_bit(BNXT_STATE_NAPI_DISABLED, &bp->state); 9449 for (i = 0; i < bp->cp_nr_rings; i++) { 9450 struct bnxt_napi *bnapi = bp->bnapi[i]; 9451 struct bnxt_cp_ring_info *cpr; 9452 9453 bnapi->tx_fault = 0; 9454 9455 cpr = &bnapi->cp_ring; 9456 if (bnapi->in_reset) 9457 cpr->sw_stats.rx.rx_resets++; 9458 bnapi->in_reset = false; 9459 9460 if (bnapi->rx_ring) { 9461 INIT_WORK(&cpr->dim.work, bnxt_dim_work); 9462 cpr->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE; 9463 } 9464 napi_enable(&bnapi->napi); 9465 } 9466 } 9467 9468 void bnxt_tx_disable(struct bnxt *bp) 9469 { 9470 int i; 9471 struct bnxt_tx_ring_info *txr; 9472 9473 if (bp->tx_ring) { 9474 for (i = 0; i < bp->tx_nr_rings; i++) { 9475 txr = &bp->tx_ring[i]; 9476 WRITE_ONCE(txr->dev_state, BNXT_DEV_STATE_CLOSING); 9477 } 9478 } 9479 /* Make sure napi polls see @dev_state change */ 9480 synchronize_net(); 9481 /* Drop carrier first to prevent TX timeout */ 9482 netif_carrier_off(bp->dev); 9483 /* Stop all TX queues */ 9484 netif_tx_disable(bp->dev); 9485 } 9486 9487 void bnxt_tx_enable(struct bnxt *bp) 9488 { 9489 int i; 9490 struct bnxt_tx_ring_info *txr; 9491 9492 for (i = 0; i < bp->tx_nr_rings; i++) { 9493 txr = &bp->tx_ring[i]; 9494 WRITE_ONCE(txr->dev_state, 0); 9495 } 9496 /* Make sure napi polls see @dev_state change */ 9497 synchronize_net(); 9498 netif_tx_wake_all_queues(bp->dev); 9499 if (BNXT_LINK_IS_UP(bp)) 9500 netif_carrier_on(bp->dev); 9501 } 9502 9503 static char *bnxt_report_fec(struct bnxt_link_info *link_info) 9504 { 9505 u8 active_fec = link_info->active_fec_sig_mode & 9506 PORT_PHY_QCFG_RESP_ACTIVE_FEC_MASK; 9507 9508 switch (active_fec) { 9509 default: 9510 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_NONE_ACTIVE: 9511 return "None"; 9512 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE74_ACTIVE: 9513 return "Clause 74 BaseR"; 9514 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE91_ACTIVE: 9515 return "Clause 91 RS(528,514)"; 9516 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_1XN_ACTIVE: 9517 return "Clause 91 RS544_1XN"; 9518 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_IEEE_ACTIVE: 9519 return "Clause 91 RS(544,514)"; 9520 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_1XN_ACTIVE: 9521 return "Clause 91 RS272_1XN"; 9522 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE: 9523 return "Clause 91 RS(272,257)"; 9524 } 9525 } 9526 9527 void bnxt_report_link(struct bnxt *bp) 9528 { 9529 if (BNXT_LINK_IS_UP(bp)) { 9530 const char *signal = ""; 9531 const char *flow_ctrl; 9532 const char *duplex; 9533 u32 speed; 9534 u16 fec; 9535 9536 netif_carrier_on(bp->dev); 9537 speed = bnxt_fw_to_ethtool_speed(bp->link_info.link_speed); 9538 if (speed == SPEED_UNKNOWN) { 9539 netdev_info(bp->dev, "NIC Link is Up, speed unknown\n"); 9540 return; 9541 } 9542 if (bp->link_info.duplex == BNXT_LINK_DUPLEX_FULL) 9543 duplex = "full"; 9544 else 9545 duplex = "half"; 9546 if (bp->link_info.pause == BNXT_LINK_PAUSE_BOTH) 9547 flow_ctrl = "ON - receive & transmit"; 9548 else if (bp->link_info.pause == BNXT_LINK_PAUSE_TX) 9549 flow_ctrl = "ON - transmit"; 9550 else if (bp->link_info.pause == BNXT_LINK_PAUSE_RX) 9551 flow_ctrl = "ON - receive"; 9552 else 9553 flow_ctrl = "none"; 9554 if (bp->link_info.phy_qcfg_resp.option_flags & 9555 PORT_PHY_QCFG_RESP_OPTION_FLAGS_SIGNAL_MODE_KNOWN) { 9556 u8 sig_mode = bp->link_info.active_fec_sig_mode & 9557 PORT_PHY_QCFG_RESP_SIGNAL_MODE_MASK; 9558 switch (sig_mode) { 9559 case PORT_PHY_QCFG_RESP_SIGNAL_MODE_NRZ: 9560 signal = "(NRZ) "; 9561 break; 9562 case PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4: 9563 signal = "(PAM4) "; 9564 break; 9565 default: 9566 break; 9567 } 9568 } 9569 netdev_info(bp->dev, "NIC Link is Up, %u Mbps %s%s duplex, Flow control: %s\n", 9570 speed, signal, duplex, flow_ctrl); 9571 if (bp->phy_flags & BNXT_PHY_FL_EEE_CAP) 9572 netdev_info(bp->dev, "EEE is %s\n", 9573 bp->eee.eee_active ? "active" : 9574 "not active"); 9575 fec = bp->link_info.fec_cfg; 9576 if (!(fec & PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED)) 9577 netdev_info(bp->dev, "FEC autoneg %s encoding: %s\n", 9578 (fec & BNXT_FEC_AUTONEG) ? "on" : "off", 9579 bnxt_report_fec(&bp->link_info)); 9580 } else { 9581 netif_carrier_off(bp->dev); 9582 netdev_err(bp->dev, "NIC Link is Down\n"); 9583 } 9584 } 9585 9586 static bool bnxt_phy_qcaps_no_speed(struct hwrm_port_phy_qcaps_output *resp) 9587 { 9588 if (!resp->supported_speeds_auto_mode && 9589 !resp->supported_speeds_force_mode && 9590 !resp->supported_pam4_speeds_auto_mode && 9591 !resp->supported_pam4_speeds_force_mode) 9592 return true; 9593 return false; 9594 } 9595 9596 static int bnxt_hwrm_phy_qcaps(struct bnxt *bp) 9597 { 9598 struct bnxt_link_info *link_info = &bp->link_info; 9599 struct hwrm_port_phy_qcaps_output *resp; 9600 struct hwrm_port_phy_qcaps_input *req; 9601 int rc = 0; 9602 9603 if (bp->hwrm_spec_code < 0x10201) 9604 return 0; 9605 9606 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_QCAPS); 9607 if (rc) 9608 return rc; 9609 9610 resp = hwrm_req_hold(bp, req); 9611 rc = hwrm_req_send(bp, req); 9612 if (rc) 9613 goto hwrm_phy_qcaps_exit; 9614 9615 bp->phy_flags = resp->flags | (le16_to_cpu(resp->flags2) << 8); 9616 if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED) { 9617 struct ethtool_eee *eee = &bp->eee; 9618 u16 fw_speeds = le16_to_cpu(resp->supported_speeds_eee_mode); 9619 9620 eee->supported = _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0); 9621 bp->lpi_tmr_lo = le32_to_cpu(resp->tx_lpi_timer_low) & 9622 PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK; 9623 bp->lpi_tmr_hi = le32_to_cpu(resp->valid_tx_lpi_timer_high) & 9624 PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK; 9625 } 9626 9627 if (bp->hwrm_spec_code >= 0x10a01) { 9628 if (bnxt_phy_qcaps_no_speed(resp)) { 9629 link_info->phy_state = BNXT_PHY_STATE_DISABLED; 9630 netdev_warn(bp->dev, "Ethernet link disabled\n"); 9631 } else if (link_info->phy_state == BNXT_PHY_STATE_DISABLED) { 9632 link_info->phy_state = BNXT_PHY_STATE_ENABLED; 9633 netdev_info(bp->dev, "Ethernet link enabled\n"); 9634 /* Phy re-enabled, reprobe the speeds */ 9635 link_info->support_auto_speeds = 0; 9636 link_info->support_pam4_auto_speeds = 0; 9637 } 9638 } 9639 if (resp->supported_speeds_auto_mode) 9640 link_info->support_auto_speeds = 9641 le16_to_cpu(resp->supported_speeds_auto_mode); 9642 if (resp->supported_pam4_speeds_auto_mode) 9643 link_info->support_pam4_auto_speeds = 9644 le16_to_cpu(resp->supported_pam4_speeds_auto_mode); 9645 9646 bp->port_count = resp->port_cnt; 9647 9648 hwrm_phy_qcaps_exit: 9649 hwrm_req_drop(bp, req); 9650 return rc; 9651 } 9652 9653 static bool bnxt_support_dropped(u16 advertising, u16 supported) 9654 { 9655 u16 diff = advertising ^ supported; 9656 9657 return ((supported | diff) != supported); 9658 } 9659 9660 int bnxt_update_link(struct bnxt *bp, bool chng_link_state) 9661 { 9662 struct bnxt_link_info *link_info = &bp->link_info; 9663 struct hwrm_port_phy_qcfg_output *resp; 9664 struct hwrm_port_phy_qcfg_input *req; 9665 u8 link_state = link_info->link_state; 9666 bool support_changed = false; 9667 int rc; 9668 9669 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_QCFG); 9670 if (rc) 9671 return rc; 9672 9673 resp = hwrm_req_hold(bp, req); 9674 rc = hwrm_req_send(bp, req); 9675 if (rc) { 9676 hwrm_req_drop(bp, req); 9677 if (BNXT_VF(bp) && rc == -ENODEV) { 9678 netdev_warn(bp->dev, "Cannot obtain link state while PF unavailable.\n"); 9679 rc = 0; 9680 } 9681 return rc; 9682 } 9683 9684 memcpy(&link_info->phy_qcfg_resp, resp, sizeof(*resp)); 9685 link_info->phy_link_status = resp->link; 9686 link_info->duplex = resp->duplex_cfg; 9687 if (bp->hwrm_spec_code >= 0x10800) 9688 link_info->duplex = resp->duplex_state; 9689 link_info->pause = resp->pause; 9690 link_info->auto_mode = resp->auto_mode; 9691 link_info->auto_pause_setting = resp->auto_pause; 9692 link_info->lp_pause = resp->link_partner_adv_pause; 9693 link_info->force_pause_setting = resp->force_pause; 9694 link_info->duplex_setting = resp->duplex_cfg; 9695 if (link_info->phy_link_status == BNXT_LINK_LINK) 9696 link_info->link_speed = le16_to_cpu(resp->link_speed); 9697 else 9698 link_info->link_speed = 0; 9699 link_info->force_link_speed = le16_to_cpu(resp->force_link_speed); 9700 link_info->force_pam4_link_speed = 9701 le16_to_cpu(resp->force_pam4_link_speed); 9702 link_info->support_speeds = le16_to_cpu(resp->support_speeds); 9703 link_info->support_pam4_speeds = le16_to_cpu(resp->support_pam4_speeds); 9704 link_info->auto_link_speeds = le16_to_cpu(resp->auto_link_speed_mask); 9705 link_info->auto_pam4_link_speeds = 9706 le16_to_cpu(resp->auto_pam4_link_speed_mask); 9707 link_info->lp_auto_link_speeds = 9708 le16_to_cpu(resp->link_partner_adv_speeds); 9709 link_info->lp_auto_pam4_link_speeds = 9710 resp->link_partner_pam4_adv_speeds; 9711 link_info->preemphasis = le32_to_cpu(resp->preemphasis); 9712 link_info->phy_ver[0] = resp->phy_maj; 9713 link_info->phy_ver[1] = resp->phy_min; 9714 link_info->phy_ver[2] = resp->phy_bld; 9715 link_info->media_type = resp->media_type; 9716 link_info->phy_type = resp->phy_type; 9717 link_info->transceiver = resp->xcvr_pkg_type; 9718 link_info->phy_addr = resp->eee_config_phy_addr & 9719 PORT_PHY_QCFG_RESP_PHY_ADDR_MASK; 9720 link_info->module_status = resp->module_status; 9721 9722 if (bp->phy_flags & BNXT_PHY_FL_EEE_CAP) { 9723 struct ethtool_eee *eee = &bp->eee; 9724 u16 fw_speeds; 9725 9726 eee->eee_active = 0; 9727 if (resp->eee_config_phy_addr & 9728 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE) { 9729 eee->eee_active = 1; 9730 fw_speeds = le16_to_cpu( 9731 resp->link_partner_adv_eee_link_speed_mask); 9732 eee->lp_advertised = 9733 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0); 9734 } 9735 9736 /* Pull initial EEE config */ 9737 if (!chng_link_state) { 9738 if (resp->eee_config_phy_addr & 9739 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED) 9740 eee->eee_enabled = 1; 9741 9742 fw_speeds = le16_to_cpu(resp->adv_eee_link_speed_mask); 9743 eee->advertised = 9744 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0); 9745 9746 if (resp->eee_config_phy_addr & 9747 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI) { 9748 __le32 tmr; 9749 9750 eee->tx_lpi_enabled = 1; 9751 tmr = resp->xcvr_identifier_type_tx_lpi_timer; 9752 eee->tx_lpi_timer = le32_to_cpu(tmr) & 9753 PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK; 9754 } 9755 } 9756 } 9757 9758 link_info->fec_cfg = PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED; 9759 if (bp->hwrm_spec_code >= 0x10504) { 9760 link_info->fec_cfg = le16_to_cpu(resp->fec_cfg); 9761 link_info->active_fec_sig_mode = resp->active_fec_signal_mode; 9762 } 9763 /* TODO: need to add more logic to report VF link */ 9764 if (chng_link_state) { 9765 if (link_info->phy_link_status == BNXT_LINK_LINK) 9766 link_info->link_state = BNXT_LINK_STATE_UP; 9767 else 9768 link_info->link_state = BNXT_LINK_STATE_DOWN; 9769 if (link_state != link_info->link_state) 9770 bnxt_report_link(bp); 9771 } else { 9772 /* always link down if not require to update link state */ 9773 link_info->link_state = BNXT_LINK_STATE_DOWN; 9774 } 9775 hwrm_req_drop(bp, req); 9776 9777 if (!BNXT_PHY_CFG_ABLE(bp)) 9778 return 0; 9779 9780 /* Check if any advertised speeds are no longer supported. The caller 9781 * holds the link_lock mutex, so we can modify link_info settings. 9782 */ 9783 if (bnxt_support_dropped(link_info->advertising, 9784 link_info->support_auto_speeds)) { 9785 link_info->advertising = link_info->support_auto_speeds; 9786 support_changed = true; 9787 } 9788 if (bnxt_support_dropped(link_info->advertising_pam4, 9789 link_info->support_pam4_auto_speeds)) { 9790 link_info->advertising_pam4 = link_info->support_pam4_auto_speeds; 9791 support_changed = true; 9792 } 9793 if (support_changed && (link_info->autoneg & BNXT_AUTONEG_SPEED)) 9794 bnxt_hwrm_set_link_setting(bp, true, false); 9795 return 0; 9796 } 9797 9798 static void bnxt_get_port_module_status(struct bnxt *bp) 9799 { 9800 struct bnxt_link_info *link_info = &bp->link_info; 9801 struct hwrm_port_phy_qcfg_output *resp = &link_info->phy_qcfg_resp; 9802 u8 module_status; 9803 9804 if (bnxt_update_link(bp, true)) 9805 return; 9806 9807 module_status = link_info->module_status; 9808 switch (module_status) { 9809 case PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX: 9810 case PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN: 9811 case PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG: 9812 netdev_warn(bp->dev, "Unqualified SFP+ module detected on port %d\n", 9813 bp->pf.port_id); 9814 if (bp->hwrm_spec_code >= 0x10201) { 9815 netdev_warn(bp->dev, "Module part number %s\n", 9816 resp->phy_vendor_partnumber); 9817 } 9818 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX) 9819 netdev_warn(bp->dev, "TX is disabled\n"); 9820 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN) 9821 netdev_warn(bp->dev, "SFP+ module is shutdown\n"); 9822 } 9823 } 9824 9825 static void 9826 bnxt_hwrm_set_pause_common(struct bnxt *bp, struct hwrm_port_phy_cfg_input *req) 9827 { 9828 if (bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) { 9829 if (bp->hwrm_spec_code >= 0x10201) 9830 req->auto_pause = 9831 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE; 9832 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX) 9833 req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX; 9834 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX) 9835 req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_TX; 9836 req->enables |= 9837 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE); 9838 } else { 9839 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX) 9840 req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_RX; 9841 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX) 9842 req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_TX; 9843 req->enables |= 9844 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE); 9845 if (bp->hwrm_spec_code >= 0x10201) { 9846 req->auto_pause = req->force_pause; 9847 req->enables |= cpu_to_le32( 9848 PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE); 9849 } 9850 } 9851 } 9852 9853 static void bnxt_hwrm_set_link_common(struct bnxt *bp, struct hwrm_port_phy_cfg_input *req) 9854 { 9855 if (bp->link_info.autoneg & BNXT_AUTONEG_SPEED) { 9856 req->auto_mode |= PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK; 9857 if (bp->link_info.advertising) { 9858 req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK); 9859 req->auto_link_speed_mask = cpu_to_le16(bp->link_info.advertising); 9860 } 9861 if (bp->link_info.advertising_pam4) { 9862 req->enables |= 9863 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAM4_LINK_SPEED_MASK); 9864 req->auto_link_pam4_speed_mask = 9865 cpu_to_le16(bp->link_info.advertising_pam4); 9866 } 9867 req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE); 9868 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG); 9869 } else { 9870 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE); 9871 if (bp->link_info.req_signal_mode == BNXT_SIG_MODE_PAM4) { 9872 req->force_pam4_link_speed = cpu_to_le16(bp->link_info.req_link_speed); 9873 req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAM4_LINK_SPEED); 9874 } else { 9875 req->force_link_speed = cpu_to_le16(bp->link_info.req_link_speed); 9876 } 9877 } 9878 9879 /* tell chimp that the setting takes effect immediately */ 9880 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESET_PHY); 9881 } 9882 9883 int bnxt_hwrm_set_pause(struct bnxt *bp) 9884 { 9885 struct hwrm_port_phy_cfg_input *req; 9886 int rc; 9887 9888 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_CFG); 9889 if (rc) 9890 return rc; 9891 9892 bnxt_hwrm_set_pause_common(bp, req); 9893 9894 if ((bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) || 9895 bp->link_info.force_link_chng) 9896 bnxt_hwrm_set_link_common(bp, req); 9897 9898 rc = hwrm_req_send(bp, req); 9899 if (!rc && !(bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL)) { 9900 /* since changing of pause setting doesn't trigger any link 9901 * change event, the driver needs to update the current pause 9902 * result upon successfully return of the phy_cfg command 9903 */ 9904 bp->link_info.pause = 9905 bp->link_info.force_pause_setting = bp->link_info.req_flow_ctrl; 9906 bp->link_info.auto_pause_setting = 0; 9907 if (!bp->link_info.force_link_chng) 9908 bnxt_report_link(bp); 9909 } 9910 bp->link_info.force_link_chng = false; 9911 return rc; 9912 } 9913 9914 static void bnxt_hwrm_set_eee(struct bnxt *bp, 9915 struct hwrm_port_phy_cfg_input *req) 9916 { 9917 struct ethtool_eee *eee = &bp->eee; 9918 9919 if (eee->eee_enabled) { 9920 u16 eee_speeds; 9921 u32 flags = PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE; 9922 9923 if (eee->tx_lpi_enabled) 9924 flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE; 9925 else 9926 flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE; 9927 9928 req->flags |= cpu_to_le32(flags); 9929 eee_speeds = bnxt_get_fw_auto_link_speeds(eee->advertised); 9930 req->eee_link_speed_mask = cpu_to_le16(eee_speeds); 9931 req->tx_lpi_timer = cpu_to_le32(eee->tx_lpi_timer); 9932 } else { 9933 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE); 9934 } 9935 } 9936 9937 int bnxt_hwrm_set_link_setting(struct bnxt *bp, bool set_pause, bool set_eee) 9938 { 9939 struct hwrm_port_phy_cfg_input *req; 9940 int rc; 9941 9942 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_CFG); 9943 if (rc) 9944 return rc; 9945 9946 if (set_pause) 9947 bnxt_hwrm_set_pause_common(bp, req); 9948 9949 bnxt_hwrm_set_link_common(bp, req); 9950 9951 if (set_eee) 9952 bnxt_hwrm_set_eee(bp, req); 9953 return hwrm_req_send(bp, req); 9954 } 9955 9956 static int bnxt_hwrm_shutdown_link(struct bnxt *bp) 9957 { 9958 struct hwrm_port_phy_cfg_input *req; 9959 int rc; 9960 9961 if (!BNXT_SINGLE_PF(bp)) 9962 return 0; 9963 9964 if (pci_num_vf(bp->pdev) && 9965 !(bp->phy_flags & BNXT_PHY_FL_FW_MANAGED_LKDN)) 9966 return 0; 9967 9968 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_CFG); 9969 if (rc) 9970 return rc; 9971 9972 req->flags = cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN); 9973 rc = hwrm_req_send(bp, req); 9974 if (!rc) { 9975 mutex_lock(&bp->link_lock); 9976 /* Device is not obliged link down in certain scenarios, even 9977 * when forced. Setting the state unknown is consistent with 9978 * driver startup and will force link state to be reported 9979 * during subsequent open based on PORT_PHY_QCFG. 9980 */ 9981 bp->link_info.link_state = BNXT_LINK_STATE_UNKNOWN; 9982 mutex_unlock(&bp->link_lock); 9983 } 9984 return rc; 9985 } 9986 9987 static int bnxt_fw_reset_via_optee(struct bnxt *bp) 9988 { 9989 #ifdef CONFIG_TEE_BNXT_FW 9990 int rc = tee_bnxt_fw_load(); 9991 9992 if (rc) 9993 netdev_err(bp->dev, "Failed FW reset via OP-TEE, rc=%d\n", rc); 9994 9995 return rc; 9996 #else 9997 netdev_err(bp->dev, "OP-TEE not supported\n"); 9998 return -ENODEV; 9999 #endif 10000 } 10001 10002 static int bnxt_try_recover_fw(struct bnxt *bp) 10003 { 10004 if (bp->fw_health && bp->fw_health->status_reliable) { 10005 int retry = 0, rc; 10006 u32 sts; 10007 10008 do { 10009 sts = bnxt_fw_health_readl(bp, BNXT_FW_HEALTH_REG); 10010 rc = bnxt_hwrm_poll(bp); 10011 if (!BNXT_FW_IS_BOOTING(sts) && 10012 !BNXT_FW_IS_RECOVERING(sts)) 10013 break; 10014 retry++; 10015 } while (rc == -EBUSY && retry < BNXT_FW_RETRY); 10016 10017 if (!BNXT_FW_IS_HEALTHY(sts)) { 10018 netdev_err(bp->dev, 10019 "Firmware not responding, status: 0x%x\n", 10020 sts); 10021 rc = -ENODEV; 10022 } 10023 if (sts & FW_STATUS_REG_CRASHED_NO_MASTER) { 10024 netdev_warn(bp->dev, "Firmware recover via OP-TEE requested\n"); 10025 return bnxt_fw_reset_via_optee(bp); 10026 } 10027 return rc; 10028 } 10029 10030 return -ENODEV; 10031 } 10032 10033 static void bnxt_clear_reservations(struct bnxt *bp, bool fw_reset) 10034 { 10035 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 10036 10037 if (!BNXT_NEW_RM(bp)) 10038 return; /* no resource reservations required */ 10039 10040 hw_resc->resv_cp_rings = 0; 10041 hw_resc->resv_stat_ctxs = 0; 10042 hw_resc->resv_irqs = 0; 10043 hw_resc->resv_tx_rings = 0; 10044 hw_resc->resv_rx_rings = 0; 10045 hw_resc->resv_hw_ring_grps = 0; 10046 hw_resc->resv_vnics = 0; 10047 if (!fw_reset) { 10048 bp->tx_nr_rings = 0; 10049 bp->rx_nr_rings = 0; 10050 } 10051 } 10052 10053 int bnxt_cancel_reservations(struct bnxt *bp, bool fw_reset) 10054 { 10055 int rc; 10056 10057 if (!BNXT_NEW_RM(bp)) 10058 return 0; /* no resource reservations required */ 10059 10060 rc = bnxt_hwrm_func_resc_qcaps(bp, true); 10061 if (rc) 10062 netdev_err(bp->dev, "resc_qcaps failed\n"); 10063 10064 bnxt_clear_reservations(bp, fw_reset); 10065 10066 return rc; 10067 } 10068 10069 static int bnxt_hwrm_if_change(struct bnxt *bp, bool up) 10070 { 10071 struct hwrm_func_drv_if_change_output *resp; 10072 struct hwrm_func_drv_if_change_input *req; 10073 bool fw_reset = !bp->irq_tbl; 10074 bool resc_reinit = false; 10075 int rc, retry = 0; 10076 u32 flags = 0; 10077 10078 if (!(bp->fw_cap & BNXT_FW_CAP_IF_CHANGE)) 10079 return 0; 10080 10081 rc = hwrm_req_init(bp, req, HWRM_FUNC_DRV_IF_CHANGE); 10082 if (rc) 10083 return rc; 10084 10085 if (up) 10086 req->flags = cpu_to_le32(FUNC_DRV_IF_CHANGE_REQ_FLAGS_UP); 10087 resp = hwrm_req_hold(bp, req); 10088 10089 hwrm_req_flags(bp, req, BNXT_HWRM_FULL_WAIT); 10090 while (retry < BNXT_FW_IF_RETRY) { 10091 rc = hwrm_req_send(bp, req); 10092 if (rc != -EAGAIN) 10093 break; 10094 10095 msleep(50); 10096 retry++; 10097 } 10098 10099 if (rc == -EAGAIN) { 10100 hwrm_req_drop(bp, req); 10101 return rc; 10102 } else if (!rc) { 10103 flags = le32_to_cpu(resp->flags); 10104 } else if (up) { 10105 rc = bnxt_try_recover_fw(bp); 10106 fw_reset = true; 10107 } 10108 hwrm_req_drop(bp, req); 10109 if (rc) 10110 return rc; 10111 10112 if (!up) { 10113 bnxt_inv_fw_health_reg(bp); 10114 return 0; 10115 } 10116 10117 if (flags & FUNC_DRV_IF_CHANGE_RESP_FLAGS_RESC_CHANGE) 10118 resc_reinit = true; 10119 if (flags & FUNC_DRV_IF_CHANGE_RESP_FLAGS_HOT_FW_RESET_DONE || 10120 test_bit(BNXT_STATE_FW_RESET_DET, &bp->state)) 10121 fw_reset = true; 10122 else 10123 bnxt_remap_fw_health_regs(bp); 10124 10125 if (test_bit(BNXT_STATE_IN_FW_RESET, &bp->state) && !fw_reset) { 10126 netdev_err(bp->dev, "RESET_DONE not set during FW reset.\n"); 10127 set_bit(BNXT_STATE_ABORT_ERR, &bp->state); 10128 return -ENODEV; 10129 } 10130 if (resc_reinit || fw_reset) { 10131 if (fw_reset) { 10132 set_bit(BNXT_STATE_FW_RESET_DET, &bp->state); 10133 if (!test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) 10134 bnxt_ulp_stop(bp); 10135 bnxt_free_ctx_mem(bp); 10136 kfree(bp->ctx); 10137 bp->ctx = NULL; 10138 bnxt_dcb_free(bp); 10139 rc = bnxt_fw_init_one(bp); 10140 if (rc) { 10141 clear_bit(BNXT_STATE_FW_RESET_DET, &bp->state); 10142 set_bit(BNXT_STATE_ABORT_ERR, &bp->state); 10143 return rc; 10144 } 10145 bnxt_clear_int_mode(bp); 10146 rc = bnxt_init_int_mode(bp); 10147 if (rc) { 10148 clear_bit(BNXT_STATE_FW_RESET_DET, &bp->state); 10149 netdev_err(bp->dev, "init int mode failed\n"); 10150 return rc; 10151 } 10152 } 10153 rc = bnxt_cancel_reservations(bp, fw_reset); 10154 } 10155 return rc; 10156 } 10157 10158 static int bnxt_hwrm_port_led_qcaps(struct bnxt *bp) 10159 { 10160 struct hwrm_port_led_qcaps_output *resp; 10161 struct hwrm_port_led_qcaps_input *req; 10162 struct bnxt_pf_info *pf = &bp->pf; 10163 int rc; 10164 10165 bp->num_leds = 0; 10166 if (BNXT_VF(bp) || bp->hwrm_spec_code < 0x10601) 10167 return 0; 10168 10169 rc = hwrm_req_init(bp, req, HWRM_PORT_LED_QCAPS); 10170 if (rc) 10171 return rc; 10172 10173 req->port_id = cpu_to_le16(pf->port_id); 10174 resp = hwrm_req_hold(bp, req); 10175 rc = hwrm_req_send(bp, req); 10176 if (rc) { 10177 hwrm_req_drop(bp, req); 10178 return rc; 10179 } 10180 if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) { 10181 int i; 10182 10183 bp->num_leds = resp->num_leds; 10184 memcpy(bp->leds, &resp->led0_id, sizeof(bp->leds[0]) * 10185 bp->num_leds); 10186 for (i = 0; i < bp->num_leds; i++) { 10187 struct bnxt_led_info *led = &bp->leds[i]; 10188 __le16 caps = led->led_state_caps; 10189 10190 if (!led->led_group_id || 10191 !BNXT_LED_ALT_BLINK_CAP(caps)) { 10192 bp->num_leds = 0; 10193 break; 10194 } 10195 } 10196 } 10197 hwrm_req_drop(bp, req); 10198 return 0; 10199 } 10200 10201 int bnxt_hwrm_alloc_wol_fltr(struct bnxt *bp) 10202 { 10203 struct hwrm_wol_filter_alloc_output *resp; 10204 struct hwrm_wol_filter_alloc_input *req; 10205 int rc; 10206 10207 rc = hwrm_req_init(bp, req, HWRM_WOL_FILTER_ALLOC); 10208 if (rc) 10209 return rc; 10210 10211 req->port_id = cpu_to_le16(bp->pf.port_id); 10212 req->wol_type = WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT; 10213 req->enables = cpu_to_le32(WOL_FILTER_ALLOC_REQ_ENABLES_MAC_ADDRESS); 10214 memcpy(req->mac_address, bp->dev->dev_addr, ETH_ALEN); 10215 10216 resp = hwrm_req_hold(bp, req); 10217 rc = hwrm_req_send(bp, req); 10218 if (!rc) 10219 bp->wol_filter_id = resp->wol_filter_id; 10220 hwrm_req_drop(bp, req); 10221 return rc; 10222 } 10223 10224 int bnxt_hwrm_free_wol_fltr(struct bnxt *bp) 10225 { 10226 struct hwrm_wol_filter_free_input *req; 10227 int rc; 10228 10229 rc = hwrm_req_init(bp, req, HWRM_WOL_FILTER_FREE); 10230 if (rc) 10231 return rc; 10232 10233 req->port_id = cpu_to_le16(bp->pf.port_id); 10234 req->enables = cpu_to_le32(WOL_FILTER_FREE_REQ_ENABLES_WOL_FILTER_ID); 10235 req->wol_filter_id = bp->wol_filter_id; 10236 10237 return hwrm_req_send(bp, req); 10238 } 10239 10240 static u16 bnxt_hwrm_get_wol_fltrs(struct bnxt *bp, u16 handle) 10241 { 10242 struct hwrm_wol_filter_qcfg_output *resp; 10243 struct hwrm_wol_filter_qcfg_input *req; 10244 u16 next_handle = 0; 10245 int rc; 10246 10247 rc = hwrm_req_init(bp, req, HWRM_WOL_FILTER_QCFG); 10248 if (rc) 10249 return rc; 10250 10251 req->port_id = cpu_to_le16(bp->pf.port_id); 10252 req->handle = cpu_to_le16(handle); 10253 resp = hwrm_req_hold(bp, req); 10254 rc = hwrm_req_send(bp, req); 10255 if (!rc) { 10256 next_handle = le16_to_cpu(resp->next_handle); 10257 if (next_handle != 0) { 10258 if (resp->wol_type == 10259 WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT) { 10260 bp->wol = 1; 10261 bp->wol_filter_id = resp->wol_filter_id; 10262 } 10263 } 10264 } 10265 hwrm_req_drop(bp, req); 10266 return next_handle; 10267 } 10268 10269 static void bnxt_get_wol_settings(struct bnxt *bp) 10270 { 10271 u16 handle = 0; 10272 10273 bp->wol = 0; 10274 if (!BNXT_PF(bp) || !(bp->flags & BNXT_FLAG_WOL_CAP)) 10275 return; 10276 10277 do { 10278 handle = bnxt_hwrm_get_wol_fltrs(bp, handle); 10279 } while (handle && handle != 0xffff); 10280 } 10281 10282 #ifdef CONFIG_BNXT_HWMON 10283 static ssize_t bnxt_show_temp(struct device *dev, 10284 struct device_attribute *devattr, char *buf) 10285 { 10286 struct hwrm_temp_monitor_query_output *resp; 10287 struct hwrm_temp_monitor_query_input *req; 10288 struct bnxt *bp = dev_get_drvdata(dev); 10289 u32 len = 0; 10290 int rc; 10291 10292 rc = hwrm_req_init(bp, req, HWRM_TEMP_MONITOR_QUERY); 10293 if (rc) 10294 return rc; 10295 resp = hwrm_req_hold(bp, req); 10296 rc = hwrm_req_send(bp, req); 10297 if (!rc) 10298 len = sprintf(buf, "%u\n", resp->temp * 1000); /* display millidegree */ 10299 hwrm_req_drop(bp, req); 10300 if (rc) 10301 return rc; 10302 return len; 10303 } 10304 static SENSOR_DEVICE_ATTR(temp1_input, 0444, bnxt_show_temp, NULL, 0); 10305 10306 static struct attribute *bnxt_attrs[] = { 10307 &sensor_dev_attr_temp1_input.dev_attr.attr, 10308 NULL 10309 }; 10310 ATTRIBUTE_GROUPS(bnxt); 10311 10312 static void bnxt_hwmon_close(struct bnxt *bp) 10313 { 10314 if (bp->hwmon_dev) { 10315 hwmon_device_unregister(bp->hwmon_dev); 10316 bp->hwmon_dev = NULL; 10317 } 10318 } 10319 10320 static void bnxt_hwmon_open(struct bnxt *bp) 10321 { 10322 struct hwrm_temp_monitor_query_input *req; 10323 struct pci_dev *pdev = bp->pdev; 10324 int rc; 10325 10326 rc = hwrm_req_init(bp, req, HWRM_TEMP_MONITOR_QUERY); 10327 if (!rc) 10328 rc = hwrm_req_send_silent(bp, req); 10329 if (rc == -EACCES || rc == -EOPNOTSUPP) { 10330 bnxt_hwmon_close(bp); 10331 return; 10332 } 10333 10334 if (bp->hwmon_dev) 10335 return; 10336 10337 bp->hwmon_dev = hwmon_device_register_with_groups(&pdev->dev, 10338 DRV_MODULE_NAME, bp, 10339 bnxt_groups); 10340 if (IS_ERR(bp->hwmon_dev)) { 10341 bp->hwmon_dev = NULL; 10342 dev_warn(&pdev->dev, "Cannot register hwmon device\n"); 10343 } 10344 } 10345 #else 10346 static void bnxt_hwmon_close(struct bnxt *bp) 10347 { 10348 } 10349 10350 static void bnxt_hwmon_open(struct bnxt *bp) 10351 { 10352 } 10353 #endif 10354 10355 static bool bnxt_eee_config_ok(struct bnxt *bp) 10356 { 10357 struct ethtool_eee *eee = &bp->eee; 10358 struct bnxt_link_info *link_info = &bp->link_info; 10359 10360 if (!(bp->phy_flags & BNXT_PHY_FL_EEE_CAP)) 10361 return true; 10362 10363 if (eee->eee_enabled) { 10364 u32 advertising = 10365 _bnxt_fw_to_ethtool_adv_spds(link_info->advertising, 0); 10366 10367 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) { 10368 eee->eee_enabled = 0; 10369 return false; 10370 } 10371 if (eee->advertised & ~advertising) { 10372 eee->advertised = advertising & eee->supported; 10373 return false; 10374 } 10375 } 10376 return true; 10377 } 10378 10379 static int bnxt_update_phy_setting(struct bnxt *bp) 10380 { 10381 int rc; 10382 bool update_link = false; 10383 bool update_pause = false; 10384 bool update_eee = false; 10385 struct bnxt_link_info *link_info = &bp->link_info; 10386 10387 rc = bnxt_update_link(bp, true); 10388 if (rc) { 10389 netdev_err(bp->dev, "failed to update link (rc: %x)\n", 10390 rc); 10391 return rc; 10392 } 10393 if (!BNXT_SINGLE_PF(bp)) 10394 return 0; 10395 10396 if ((link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) && 10397 (link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH) != 10398 link_info->req_flow_ctrl) 10399 update_pause = true; 10400 if (!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) && 10401 link_info->force_pause_setting != link_info->req_flow_ctrl) 10402 update_pause = true; 10403 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) { 10404 if (BNXT_AUTO_MODE(link_info->auto_mode)) 10405 update_link = true; 10406 if (link_info->req_signal_mode == BNXT_SIG_MODE_NRZ && 10407 link_info->req_link_speed != link_info->force_link_speed) 10408 update_link = true; 10409 else if (link_info->req_signal_mode == BNXT_SIG_MODE_PAM4 && 10410 link_info->req_link_speed != link_info->force_pam4_link_speed) 10411 update_link = true; 10412 if (link_info->req_duplex != link_info->duplex_setting) 10413 update_link = true; 10414 } else { 10415 if (link_info->auto_mode == BNXT_LINK_AUTO_NONE) 10416 update_link = true; 10417 if (link_info->advertising != link_info->auto_link_speeds || 10418 link_info->advertising_pam4 != link_info->auto_pam4_link_speeds) 10419 update_link = true; 10420 } 10421 10422 /* The last close may have shutdown the link, so need to call 10423 * PHY_CFG to bring it back up. 10424 */ 10425 if (!BNXT_LINK_IS_UP(bp)) 10426 update_link = true; 10427 10428 if (!bnxt_eee_config_ok(bp)) 10429 update_eee = true; 10430 10431 if (update_link) 10432 rc = bnxt_hwrm_set_link_setting(bp, update_pause, update_eee); 10433 else if (update_pause) 10434 rc = bnxt_hwrm_set_pause(bp); 10435 if (rc) { 10436 netdev_err(bp->dev, "failed to update phy setting (rc: %x)\n", 10437 rc); 10438 return rc; 10439 } 10440 10441 return rc; 10442 } 10443 10444 /* Common routine to pre-map certain register block to different GRC window. 10445 * A PF has 16 4K windows and a VF has 4 4K windows. However, only 15 windows 10446 * in PF and 3 windows in VF that can be customized to map in different 10447 * register blocks. 10448 */ 10449 static void bnxt_preset_reg_win(struct bnxt *bp) 10450 { 10451 if (BNXT_PF(bp)) { 10452 /* CAG registers map to GRC window #4 */ 10453 writel(BNXT_CAG_REG_BASE, 10454 bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 12); 10455 } 10456 } 10457 10458 static int bnxt_init_dflt_ring_mode(struct bnxt *bp); 10459 10460 static int bnxt_reinit_after_abort(struct bnxt *bp) 10461 { 10462 int rc; 10463 10464 if (test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) 10465 return -EBUSY; 10466 10467 if (bp->dev->reg_state == NETREG_UNREGISTERED) 10468 return -ENODEV; 10469 10470 rc = bnxt_fw_init_one(bp); 10471 if (!rc) { 10472 bnxt_clear_int_mode(bp); 10473 rc = bnxt_init_int_mode(bp); 10474 if (!rc) { 10475 clear_bit(BNXT_STATE_ABORT_ERR, &bp->state); 10476 set_bit(BNXT_STATE_FW_RESET_DET, &bp->state); 10477 } 10478 } 10479 return rc; 10480 } 10481 10482 static int __bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init) 10483 { 10484 int rc = 0; 10485 10486 bnxt_preset_reg_win(bp); 10487 netif_carrier_off(bp->dev); 10488 if (irq_re_init) { 10489 /* Reserve rings now if none were reserved at driver probe. */ 10490 rc = bnxt_init_dflt_ring_mode(bp); 10491 if (rc) { 10492 netdev_err(bp->dev, "Failed to reserve default rings at open\n"); 10493 return rc; 10494 } 10495 } 10496 rc = bnxt_reserve_rings(bp, irq_re_init); 10497 if (rc) 10498 return rc; 10499 if ((bp->flags & BNXT_FLAG_RFS) && 10500 !(bp->flags & BNXT_FLAG_USING_MSIX)) { 10501 /* disable RFS if falling back to INTA */ 10502 bp->dev->hw_features &= ~NETIF_F_NTUPLE; 10503 bp->flags &= ~BNXT_FLAG_RFS; 10504 } 10505 10506 rc = bnxt_alloc_mem(bp, irq_re_init); 10507 if (rc) { 10508 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc); 10509 goto open_err_free_mem; 10510 } 10511 10512 if (irq_re_init) { 10513 bnxt_init_napi(bp); 10514 rc = bnxt_request_irq(bp); 10515 if (rc) { 10516 netdev_err(bp->dev, "bnxt_request_irq err: %x\n", rc); 10517 goto open_err_irq; 10518 } 10519 } 10520 10521 rc = bnxt_init_nic(bp, irq_re_init); 10522 if (rc) { 10523 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc); 10524 goto open_err_irq; 10525 } 10526 10527 bnxt_enable_napi(bp); 10528 bnxt_debug_dev_init(bp); 10529 10530 if (link_re_init) { 10531 mutex_lock(&bp->link_lock); 10532 rc = bnxt_update_phy_setting(bp); 10533 mutex_unlock(&bp->link_lock); 10534 if (rc) { 10535 netdev_warn(bp->dev, "failed to update phy settings\n"); 10536 if (BNXT_SINGLE_PF(bp)) { 10537 bp->link_info.phy_retry = true; 10538 bp->link_info.phy_retry_expires = 10539 jiffies + 5 * HZ; 10540 } 10541 } 10542 } 10543 10544 if (irq_re_init) 10545 udp_tunnel_nic_reset_ntf(bp->dev); 10546 10547 if (bp->tx_nr_rings_xdp < num_possible_cpus()) { 10548 if (!static_key_enabled(&bnxt_xdp_locking_key)) 10549 static_branch_enable(&bnxt_xdp_locking_key); 10550 } else if (static_key_enabled(&bnxt_xdp_locking_key)) { 10551 static_branch_disable(&bnxt_xdp_locking_key); 10552 } 10553 set_bit(BNXT_STATE_OPEN, &bp->state); 10554 bnxt_enable_int(bp); 10555 /* Enable TX queues */ 10556 bnxt_tx_enable(bp); 10557 mod_timer(&bp->timer, jiffies + bp->current_interval); 10558 /* Poll link status and check for SFP+ module status */ 10559 mutex_lock(&bp->link_lock); 10560 bnxt_get_port_module_status(bp); 10561 mutex_unlock(&bp->link_lock); 10562 10563 /* VF-reps may need to be re-opened after the PF is re-opened */ 10564 if (BNXT_PF(bp)) 10565 bnxt_vf_reps_open(bp); 10566 bnxt_ptp_init_rtc(bp, true); 10567 bnxt_ptp_cfg_tstamp_filters(bp); 10568 return 0; 10569 10570 open_err_irq: 10571 bnxt_del_napi(bp); 10572 10573 open_err_free_mem: 10574 bnxt_free_skbs(bp); 10575 bnxt_free_irq(bp); 10576 bnxt_free_mem(bp, true); 10577 return rc; 10578 } 10579 10580 /* rtnl_lock held */ 10581 int bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init) 10582 { 10583 int rc = 0; 10584 10585 if (test_bit(BNXT_STATE_ABORT_ERR, &bp->state)) 10586 rc = -EIO; 10587 if (!rc) 10588 rc = __bnxt_open_nic(bp, irq_re_init, link_re_init); 10589 if (rc) { 10590 netdev_err(bp->dev, "nic open fail (rc: %x)\n", rc); 10591 dev_close(bp->dev); 10592 } 10593 return rc; 10594 } 10595 10596 /* rtnl_lock held, open the NIC half way by allocating all resources, but 10597 * NAPI, IRQ, and TX are not enabled. This is mainly used for offline 10598 * self tests. 10599 */ 10600 int bnxt_half_open_nic(struct bnxt *bp) 10601 { 10602 int rc = 0; 10603 10604 if (test_bit(BNXT_STATE_ABORT_ERR, &bp->state)) { 10605 netdev_err(bp->dev, "A previous firmware reset has not completed, aborting half open\n"); 10606 rc = -ENODEV; 10607 goto half_open_err; 10608 } 10609 10610 rc = bnxt_alloc_mem(bp, true); 10611 if (rc) { 10612 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc); 10613 goto half_open_err; 10614 } 10615 set_bit(BNXT_STATE_HALF_OPEN, &bp->state); 10616 rc = bnxt_init_nic(bp, true); 10617 if (rc) { 10618 clear_bit(BNXT_STATE_HALF_OPEN, &bp->state); 10619 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc); 10620 goto half_open_err; 10621 } 10622 return 0; 10623 10624 half_open_err: 10625 bnxt_free_skbs(bp); 10626 bnxt_free_mem(bp, true); 10627 dev_close(bp->dev); 10628 return rc; 10629 } 10630 10631 /* rtnl_lock held, this call can only be made after a previous successful 10632 * call to bnxt_half_open_nic(). 10633 */ 10634 void bnxt_half_close_nic(struct bnxt *bp) 10635 { 10636 bnxt_hwrm_resource_free(bp, false, true); 10637 bnxt_free_skbs(bp); 10638 bnxt_free_mem(bp, true); 10639 clear_bit(BNXT_STATE_HALF_OPEN, &bp->state); 10640 } 10641 10642 void bnxt_reenable_sriov(struct bnxt *bp) 10643 { 10644 if (BNXT_PF(bp)) { 10645 struct bnxt_pf_info *pf = &bp->pf; 10646 int n = pf->active_vfs; 10647 10648 if (n) 10649 bnxt_cfg_hw_sriov(bp, &n, true); 10650 } 10651 } 10652 10653 static int bnxt_open(struct net_device *dev) 10654 { 10655 struct bnxt *bp = netdev_priv(dev); 10656 int rc; 10657 10658 if (test_bit(BNXT_STATE_ABORT_ERR, &bp->state)) { 10659 rc = bnxt_reinit_after_abort(bp); 10660 if (rc) { 10661 if (rc == -EBUSY) 10662 netdev_err(bp->dev, "A previous firmware reset has not completed, aborting\n"); 10663 else 10664 netdev_err(bp->dev, "Failed to reinitialize after aborted firmware reset\n"); 10665 return -ENODEV; 10666 } 10667 } 10668 10669 rc = bnxt_hwrm_if_change(bp, true); 10670 if (rc) 10671 return rc; 10672 10673 rc = __bnxt_open_nic(bp, true, true); 10674 if (rc) { 10675 bnxt_hwrm_if_change(bp, false); 10676 } else { 10677 if (test_and_clear_bit(BNXT_STATE_FW_RESET_DET, &bp->state)) { 10678 if (!test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) { 10679 bnxt_ulp_start(bp, 0); 10680 bnxt_reenable_sriov(bp); 10681 } 10682 } 10683 bnxt_hwmon_open(bp); 10684 } 10685 10686 return rc; 10687 } 10688 10689 static bool bnxt_drv_busy(struct bnxt *bp) 10690 { 10691 return (test_bit(BNXT_STATE_IN_SP_TASK, &bp->state) || 10692 test_bit(BNXT_STATE_READ_STATS, &bp->state)); 10693 } 10694 10695 static void bnxt_get_ring_stats(struct bnxt *bp, 10696 struct rtnl_link_stats64 *stats); 10697 10698 static void __bnxt_close_nic(struct bnxt *bp, bool irq_re_init, 10699 bool link_re_init) 10700 { 10701 /* Close the VF-reps before closing PF */ 10702 if (BNXT_PF(bp)) 10703 bnxt_vf_reps_close(bp); 10704 10705 /* Change device state to avoid TX queue wake up's */ 10706 bnxt_tx_disable(bp); 10707 10708 clear_bit(BNXT_STATE_OPEN, &bp->state); 10709 smp_mb__after_atomic(); 10710 while (bnxt_drv_busy(bp)) 10711 msleep(20); 10712 10713 /* Flush rings and disable interrupts */ 10714 bnxt_shutdown_nic(bp, irq_re_init); 10715 10716 /* TODO CHIMP_FW: Link/PHY related cleanup if (link_re_init) */ 10717 10718 bnxt_debug_dev_exit(bp); 10719 bnxt_disable_napi(bp); 10720 del_timer_sync(&bp->timer); 10721 bnxt_free_skbs(bp); 10722 10723 /* Save ring stats before shutdown */ 10724 if (bp->bnapi && irq_re_init) 10725 bnxt_get_ring_stats(bp, &bp->net_stats_prev); 10726 if (irq_re_init) { 10727 bnxt_free_irq(bp); 10728 bnxt_del_napi(bp); 10729 } 10730 bnxt_free_mem(bp, irq_re_init); 10731 } 10732 10733 int bnxt_close_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init) 10734 { 10735 int rc = 0; 10736 10737 if (test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) { 10738 /* If we get here, it means firmware reset is in progress 10739 * while we are trying to close. We can safely proceed with 10740 * the close because we are holding rtnl_lock(). Some firmware 10741 * messages may fail as we proceed to close. We set the 10742 * ABORT_ERR flag here so that the FW reset thread will later 10743 * abort when it gets the rtnl_lock() and sees the flag. 10744 */ 10745 netdev_warn(bp->dev, "FW reset in progress during close, FW reset will be aborted\n"); 10746 set_bit(BNXT_STATE_ABORT_ERR, &bp->state); 10747 } 10748 10749 #ifdef CONFIG_BNXT_SRIOV 10750 if (bp->sriov_cfg) { 10751 rc = wait_event_interruptible_timeout(bp->sriov_cfg_wait, 10752 !bp->sriov_cfg, 10753 BNXT_SRIOV_CFG_WAIT_TMO); 10754 if (rc) 10755 netdev_warn(bp->dev, "timeout waiting for SRIOV config operation to complete!\n"); 10756 } 10757 #endif 10758 __bnxt_close_nic(bp, irq_re_init, link_re_init); 10759 return rc; 10760 } 10761 10762 static int bnxt_close(struct net_device *dev) 10763 { 10764 struct bnxt *bp = netdev_priv(dev); 10765 10766 bnxt_hwmon_close(bp); 10767 bnxt_close_nic(bp, true, true); 10768 bnxt_hwrm_shutdown_link(bp); 10769 bnxt_hwrm_if_change(bp, false); 10770 return 0; 10771 } 10772 10773 static int bnxt_hwrm_port_phy_read(struct bnxt *bp, u16 phy_addr, u16 reg, 10774 u16 *val) 10775 { 10776 struct hwrm_port_phy_mdio_read_output *resp; 10777 struct hwrm_port_phy_mdio_read_input *req; 10778 int rc; 10779 10780 if (bp->hwrm_spec_code < 0x10a00) 10781 return -EOPNOTSUPP; 10782 10783 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_MDIO_READ); 10784 if (rc) 10785 return rc; 10786 10787 req->port_id = cpu_to_le16(bp->pf.port_id); 10788 req->phy_addr = phy_addr; 10789 req->reg_addr = cpu_to_le16(reg & 0x1f); 10790 if (mdio_phy_id_is_c45(phy_addr)) { 10791 req->cl45_mdio = 1; 10792 req->phy_addr = mdio_phy_id_prtad(phy_addr); 10793 req->dev_addr = mdio_phy_id_devad(phy_addr); 10794 req->reg_addr = cpu_to_le16(reg); 10795 } 10796 10797 resp = hwrm_req_hold(bp, req); 10798 rc = hwrm_req_send(bp, req); 10799 if (!rc) 10800 *val = le16_to_cpu(resp->reg_data); 10801 hwrm_req_drop(bp, req); 10802 return rc; 10803 } 10804 10805 static int bnxt_hwrm_port_phy_write(struct bnxt *bp, u16 phy_addr, u16 reg, 10806 u16 val) 10807 { 10808 struct hwrm_port_phy_mdio_write_input *req; 10809 int rc; 10810 10811 if (bp->hwrm_spec_code < 0x10a00) 10812 return -EOPNOTSUPP; 10813 10814 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_MDIO_WRITE); 10815 if (rc) 10816 return rc; 10817 10818 req->port_id = cpu_to_le16(bp->pf.port_id); 10819 req->phy_addr = phy_addr; 10820 req->reg_addr = cpu_to_le16(reg & 0x1f); 10821 if (mdio_phy_id_is_c45(phy_addr)) { 10822 req->cl45_mdio = 1; 10823 req->phy_addr = mdio_phy_id_prtad(phy_addr); 10824 req->dev_addr = mdio_phy_id_devad(phy_addr); 10825 req->reg_addr = cpu_to_le16(reg); 10826 } 10827 req->reg_data = cpu_to_le16(val); 10828 10829 return hwrm_req_send(bp, req); 10830 } 10831 10832 /* rtnl_lock held */ 10833 static int bnxt_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 10834 { 10835 struct mii_ioctl_data *mdio = if_mii(ifr); 10836 struct bnxt *bp = netdev_priv(dev); 10837 int rc; 10838 10839 switch (cmd) { 10840 case SIOCGMIIPHY: 10841 mdio->phy_id = bp->link_info.phy_addr; 10842 10843 fallthrough; 10844 case SIOCGMIIREG: { 10845 u16 mii_regval = 0; 10846 10847 if (!netif_running(dev)) 10848 return -EAGAIN; 10849 10850 rc = bnxt_hwrm_port_phy_read(bp, mdio->phy_id, mdio->reg_num, 10851 &mii_regval); 10852 mdio->val_out = mii_regval; 10853 return rc; 10854 } 10855 10856 case SIOCSMIIREG: 10857 if (!netif_running(dev)) 10858 return -EAGAIN; 10859 10860 return bnxt_hwrm_port_phy_write(bp, mdio->phy_id, mdio->reg_num, 10861 mdio->val_in); 10862 10863 case SIOCSHWTSTAMP: 10864 return bnxt_hwtstamp_set(dev, ifr); 10865 10866 case SIOCGHWTSTAMP: 10867 return bnxt_hwtstamp_get(dev, ifr); 10868 10869 default: 10870 /* do nothing */ 10871 break; 10872 } 10873 return -EOPNOTSUPP; 10874 } 10875 10876 static void bnxt_get_ring_stats(struct bnxt *bp, 10877 struct rtnl_link_stats64 *stats) 10878 { 10879 int i; 10880 10881 for (i = 0; i < bp->cp_nr_rings; i++) { 10882 struct bnxt_napi *bnapi = bp->bnapi[i]; 10883 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 10884 u64 *sw = cpr->stats.sw_stats; 10885 10886 stats->rx_packets += BNXT_GET_RING_STATS64(sw, rx_ucast_pkts); 10887 stats->rx_packets += BNXT_GET_RING_STATS64(sw, rx_mcast_pkts); 10888 stats->rx_packets += BNXT_GET_RING_STATS64(sw, rx_bcast_pkts); 10889 10890 stats->tx_packets += BNXT_GET_RING_STATS64(sw, tx_ucast_pkts); 10891 stats->tx_packets += BNXT_GET_RING_STATS64(sw, tx_mcast_pkts); 10892 stats->tx_packets += BNXT_GET_RING_STATS64(sw, tx_bcast_pkts); 10893 10894 stats->rx_bytes += BNXT_GET_RING_STATS64(sw, rx_ucast_bytes); 10895 stats->rx_bytes += BNXT_GET_RING_STATS64(sw, rx_mcast_bytes); 10896 stats->rx_bytes += BNXT_GET_RING_STATS64(sw, rx_bcast_bytes); 10897 10898 stats->tx_bytes += BNXT_GET_RING_STATS64(sw, tx_ucast_bytes); 10899 stats->tx_bytes += BNXT_GET_RING_STATS64(sw, tx_mcast_bytes); 10900 stats->tx_bytes += BNXT_GET_RING_STATS64(sw, tx_bcast_bytes); 10901 10902 stats->rx_missed_errors += 10903 BNXT_GET_RING_STATS64(sw, rx_discard_pkts); 10904 10905 stats->multicast += BNXT_GET_RING_STATS64(sw, rx_mcast_pkts); 10906 10907 stats->tx_dropped += BNXT_GET_RING_STATS64(sw, tx_error_pkts); 10908 10909 stats->rx_dropped += 10910 cpr->sw_stats.rx.rx_netpoll_discards + 10911 cpr->sw_stats.rx.rx_oom_discards; 10912 } 10913 } 10914 10915 static void bnxt_add_prev_stats(struct bnxt *bp, 10916 struct rtnl_link_stats64 *stats) 10917 { 10918 struct rtnl_link_stats64 *prev_stats = &bp->net_stats_prev; 10919 10920 stats->rx_packets += prev_stats->rx_packets; 10921 stats->tx_packets += prev_stats->tx_packets; 10922 stats->rx_bytes += prev_stats->rx_bytes; 10923 stats->tx_bytes += prev_stats->tx_bytes; 10924 stats->rx_missed_errors += prev_stats->rx_missed_errors; 10925 stats->multicast += prev_stats->multicast; 10926 stats->rx_dropped += prev_stats->rx_dropped; 10927 stats->tx_dropped += prev_stats->tx_dropped; 10928 } 10929 10930 static void 10931 bnxt_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) 10932 { 10933 struct bnxt *bp = netdev_priv(dev); 10934 10935 set_bit(BNXT_STATE_READ_STATS, &bp->state); 10936 /* Make sure bnxt_close_nic() sees that we are reading stats before 10937 * we check the BNXT_STATE_OPEN flag. 10938 */ 10939 smp_mb__after_atomic(); 10940 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) { 10941 clear_bit(BNXT_STATE_READ_STATS, &bp->state); 10942 *stats = bp->net_stats_prev; 10943 return; 10944 } 10945 10946 bnxt_get_ring_stats(bp, stats); 10947 bnxt_add_prev_stats(bp, stats); 10948 10949 if (bp->flags & BNXT_FLAG_PORT_STATS) { 10950 u64 *rx = bp->port_stats.sw_stats; 10951 u64 *tx = bp->port_stats.sw_stats + 10952 BNXT_TX_PORT_STATS_BYTE_OFFSET / 8; 10953 10954 stats->rx_crc_errors = 10955 BNXT_GET_RX_PORT_STATS64(rx, rx_fcs_err_frames); 10956 stats->rx_frame_errors = 10957 BNXT_GET_RX_PORT_STATS64(rx, rx_align_err_frames); 10958 stats->rx_length_errors = 10959 BNXT_GET_RX_PORT_STATS64(rx, rx_undrsz_frames) + 10960 BNXT_GET_RX_PORT_STATS64(rx, rx_ovrsz_frames) + 10961 BNXT_GET_RX_PORT_STATS64(rx, rx_runt_frames); 10962 stats->rx_errors = 10963 BNXT_GET_RX_PORT_STATS64(rx, rx_false_carrier_frames) + 10964 BNXT_GET_RX_PORT_STATS64(rx, rx_jbr_frames); 10965 stats->collisions = 10966 BNXT_GET_TX_PORT_STATS64(tx, tx_total_collisions); 10967 stats->tx_fifo_errors = 10968 BNXT_GET_TX_PORT_STATS64(tx, tx_fifo_underruns); 10969 stats->tx_errors = BNXT_GET_TX_PORT_STATS64(tx, tx_err); 10970 } 10971 clear_bit(BNXT_STATE_READ_STATS, &bp->state); 10972 } 10973 10974 static bool bnxt_mc_list_updated(struct bnxt *bp, u32 *rx_mask) 10975 { 10976 struct net_device *dev = bp->dev; 10977 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 10978 struct netdev_hw_addr *ha; 10979 u8 *haddr; 10980 int mc_count = 0; 10981 bool update = false; 10982 int off = 0; 10983 10984 netdev_for_each_mc_addr(ha, dev) { 10985 if (mc_count >= BNXT_MAX_MC_ADDRS) { 10986 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST; 10987 vnic->mc_list_count = 0; 10988 return false; 10989 } 10990 haddr = ha->addr; 10991 if (!ether_addr_equal(haddr, vnic->mc_list + off)) { 10992 memcpy(vnic->mc_list + off, haddr, ETH_ALEN); 10993 update = true; 10994 } 10995 off += ETH_ALEN; 10996 mc_count++; 10997 } 10998 if (mc_count) 10999 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_MCAST; 11000 11001 if (mc_count != vnic->mc_list_count) { 11002 vnic->mc_list_count = mc_count; 11003 update = true; 11004 } 11005 return update; 11006 } 11007 11008 static bool bnxt_uc_list_updated(struct bnxt *bp) 11009 { 11010 struct net_device *dev = bp->dev; 11011 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 11012 struct netdev_hw_addr *ha; 11013 int off = 0; 11014 11015 if (netdev_uc_count(dev) != (vnic->uc_filter_count - 1)) 11016 return true; 11017 11018 netdev_for_each_uc_addr(ha, dev) { 11019 if (!ether_addr_equal(ha->addr, vnic->uc_list + off)) 11020 return true; 11021 11022 off += ETH_ALEN; 11023 } 11024 return false; 11025 } 11026 11027 static void bnxt_set_rx_mode(struct net_device *dev) 11028 { 11029 struct bnxt *bp = netdev_priv(dev); 11030 struct bnxt_vnic_info *vnic; 11031 bool mc_update = false; 11032 bool uc_update; 11033 u32 mask; 11034 11035 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) 11036 return; 11037 11038 vnic = &bp->vnic_info[0]; 11039 mask = vnic->rx_mask; 11040 mask &= ~(CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS | 11041 CFA_L2_SET_RX_MASK_REQ_MASK_MCAST | 11042 CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST | 11043 CFA_L2_SET_RX_MASK_REQ_MASK_BCAST); 11044 11045 if (dev->flags & IFF_PROMISC) 11046 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS; 11047 11048 uc_update = bnxt_uc_list_updated(bp); 11049 11050 if (dev->flags & IFF_BROADCAST) 11051 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_BCAST; 11052 if (dev->flags & IFF_ALLMULTI) { 11053 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST; 11054 vnic->mc_list_count = 0; 11055 } else if (dev->flags & IFF_MULTICAST) { 11056 mc_update = bnxt_mc_list_updated(bp, &mask); 11057 } 11058 11059 if (mask != vnic->rx_mask || uc_update || mc_update) { 11060 vnic->rx_mask = mask; 11061 11062 bnxt_queue_sp_work(bp, BNXT_RX_MASK_SP_EVENT); 11063 } 11064 } 11065 11066 static int bnxt_cfg_rx_mode(struct bnxt *bp) 11067 { 11068 struct net_device *dev = bp->dev; 11069 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 11070 struct hwrm_cfa_l2_filter_free_input *req; 11071 struct netdev_hw_addr *ha; 11072 int i, off = 0, rc; 11073 bool uc_update; 11074 11075 netif_addr_lock_bh(dev); 11076 uc_update = bnxt_uc_list_updated(bp); 11077 netif_addr_unlock_bh(dev); 11078 11079 if (!uc_update) 11080 goto skip_uc; 11081 11082 rc = hwrm_req_init(bp, req, HWRM_CFA_L2_FILTER_FREE); 11083 if (rc) 11084 return rc; 11085 hwrm_req_hold(bp, req); 11086 for (i = 1; i < vnic->uc_filter_count; i++) { 11087 req->l2_filter_id = vnic->fw_l2_filter_id[i]; 11088 11089 rc = hwrm_req_send(bp, req); 11090 } 11091 hwrm_req_drop(bp, req); 11092 11093 vnic->uc_filter_count = 1; 11094 11095 netif_addr_lock_bh(dev); 11096 if (netdev_uc_count(dev) > (BNXT_MAX_UC_ADDRS - 1)) { 11097 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS; 11098 } else { 11099 netdev_for_each_uc_addr(ha, dev) { 11100 memcpy(vnic->uc_list + off, ha->addr, ETH_ALEN); 11101 off += ETH_ALEN; 11102 vnic->uc_filter_count++; 11103 } 11104 } 11105 netif_addr_unlock_bh(dev); 11106 11107 for (i = 1, off = 0; i < vnic->uc_filter_count; i++, off += ETH_ALEN) { 11108 rc = bnxt_hwrm_set_vnic_filter(bp, 0, i, vnic->uc_list + off); 11109 if (rc) { 11110 if (BNXT_VF(bp) && rc == -ENODEV) { 11111 if (!test_and_set_bit(BNXT_STATE_L2_FILTER_RETRY, &bp->state)) 11112 netdev_warn(bp->dev, "Cannot configure L2 filters while PF is unavailable, will retry\n"); 11113 else 11114 netdev_dbg(bp->dev, "PF still unavailable while configuring L2 filters.\n"); 11115 rc = 0; 11116 } else { 11117 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n", rc); 11118 } 11119 vnic->uc_filter_count = i; 11120 return rc; 11121 } 11122 } 11123 if (test_and_clear_bit(BNXT_STATE_L2_FILTER_RETRY, &bp->state)) 11124 netdev_notice(bp->dev, "Retry of L2 filter configuration successful.\n"); 11125 11126 skip_uc: 11127 if ((vnic->rx_mask & CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS) && 11128 !bnxt_promisc_ok(bp)) 11129 vnic->rx_mask &= ~CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS; 11130 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0); 11131 if (rc && (vnic->rx_mask & CFA_L2_SET_RX_MASK_REQ_MASK_MCAST)) { 11132 netdev_info(bp->dev, "Failed setting MC filters rc: %d, turning on ALL_MCAST mode\n", 11133 rc); 11134 vnic->rx_mask &= ~CFA_L2_SET_RX_MASK_REQ_MASK_MCAST; 11135 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST; 11136 vnic->mc_list_count = 0; 11137 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0); 11138 } 11139 if (rc) 11140 netdev_err(bp->dev, "HWRM cfa l2 rx mask failure rc: %d\n", 11141 rc); 11142 11143 return rc; 11144 } 11145 11146 static bool bnxt_can_reserve_rings(struct bnxt *bp) 11147 { 11148 #ifdef CONFIG_BNXT_SRIOV 11149 if (BNXT_NEW_RM(bp) && BNXT_VF(bp)) { 11150 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 11151 11152 /* No minimum rings were provisioned by the PF. Don't 11153 * reserve rings by default when device is down. 11154 */ 11155 if (hw_resc->min_tx_rings || hw_resc->resv_tx_rings) 11156 return true; 11157 11158 if (!netif_running(bp->dev)) 11159 return false; 11160 } 11161 #endif 11162 return true; 11163 } 11164 11165 /* If the chip and firmware supports RFS */ 11166 static bool bnxt_rfs_supported(struct bnxt *bp) 11167 { 11168 if (bp->flags & BNXT_FLAG_CHIP_P5) { 11169 if (bp->fw_cap & BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V2) 11170 return true; 11171 return false; 11172 } 11173 /* 212 firmware is broken for aRFS */ 11174 if (BNXT_FW_MAJ(bp) == 212) 11175 return false; 11176 if (BNXT_PF(bp) && !BNXT_CHIP_TYPE_NITRO_A0(bp)) 11177 return true; 11178 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP) 11179 return true; 11180 return false; 11181 } 11182 11183 /* If runtime conditions support RFS */ 11184 static bool bnxt_rfs_capable(struct bnxt *bp) 11185 { 11186 #ifdef CONFIG_RFS_ACCEL 11187 int vnics, max_vnics, max_rss_ctxs; 11188 11189 if (bp->flags & BNXT_FLAG_CHIP_P5) 11190 return bnxt_rfs_supported(bp); 11191 if (!(bp->flags & BNXT_FLAG_MSIX_CAP) || !bnxt_can_reserve_rings(bp) || !bp->rx_nr_rings) 11192 return false; 11193 11194 vnics = 1 + bp->rx_nr_rings; 11195 max_vnics = bnxt_get_max_func_vnics(bp); 11196 max_rss_ctxs = bnxt_get_max_func_rss_ctxs(bp); 11197 11198 /* RSS contexts not a limiting factor */ 11199 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP) 11200 max_rss_ctxs = max_vnics; 11201 if (vnics > max_vnics || vnics > max_rss_ctxs) { 11202 if (bp->rx_nr_rings > 1) 11203 netdev_warn(bp->dev, 11204 "Not enough resources to support NTUPLE filters, enough resources for up to %d rx rings\n", 11205 min(max_rss_ctxs - 1, max_vnics - 1)); 11206 return false; 11207 } 11208 11209 if (!BNXT_NEW_RM(bp)) 11210 return true; 11211 11212 if (vnics == bp->hw_resc.resv_vnics) 11213 return true; 11214 11215 bnxt_hwrm_reserve_rings(bp, 0, 0, 0, 0, 0, vnics); 11216 if (vnics <= bp->hw_resc.resv_vnics) 11217 return true; 11218 11219 netdev_warn(bp->dev, "Unable to reserve resources to support NTUPLE filters.\n"); 11220 bnxt_hwrm_reserve_rings(bp, 0, 0, 0, 0, 0, 1); 11221 return false; 11222 #else 11223 return false; 11224 #endif 11225 } 11226 11227 static netdev_features_t bnxt_fix_features(struct net_device *dev, 11228 netdev_features_t features) 11229 { 11230 struct bnxt *bp = netdev_priv(dev); 11231 netdev_features_t vlan_features; 11232 11233 if ((features & NETIF_F_NTUPLE) && !bnxt_rfs_capable(bp)) 11234 features &= ~NETIF_F_NTUPLE; 11235 11236 if ((bp->flags & BNXT_FLAG_NO_AGG_RINGS) || bp->xdp_prog) 11237 features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW); 11238 11239 if (!(features & NETIF_F_GRO)) 11240 features &= ~NETIF_F_GRO_HW; 11241 11242 if (features & NETIF_F_GRO_HW) 11243 features &= ~NETIF_F_LRO; 11244 11245 /* Both CTAG and STAG VLAN accelaration on the RX side have to be 11246 * turned on or off together. 11247 */ 11248 vlan_features = features & BNXT_HW_FEATURE_VLAN_ALL_RX; 11249 if (vlan_features != BNXT_HW_FEATURE_VLAN_ALL_RX) { 11250 if (dev->features & BNXT_HW_FEATURE_VLAN_ALL_RX) 11251 features &= ~BNXT_HW_FEATURE_VLAN_ALL_RX; 11252 else if (vlan_features) 11253 features |= BNXT_HW_FEATURE_VLAN_ALL_RX; 11254 } 11255 #ifdef CONFIG_BNXT_SRIOV 11256 if (BNXT_VF(bp) && bp->vf.vlan) 11257 features &= ~BNXT_HW_FEATURE_VLAN_ALL_RX; 11258 #endif 11259 return features; 11260 } 11261 11262 static int bnxt_set_features(struct net_device *dev, netdev_features_t features) 11263 { 11264 struct bnxt *bp = netdev_priv(dev); 11265 u32 flags = bp->flags; 11266 u32 changes; 11267 int rc = 0; 11268 bool re_init = false; 11269 bool update_tpa = false; 11270 11271 flags &= ~BNXT_FLAG_ALL_CONFIG_FEATS; 11272 if (features & NETIF_F_GRO_HW) 11273 flags |= BNXT_FLAG_GRO; 11274 else if (features & NETIF_F_LRO) 11275 flags |= BNXT_FLAG_LRO; 11276 11277 if (bp->flags & BNXT_FLAG_NO_AGG_RINGS) 11278 flags &= ~BNXT_FLAG_TPA; 11279 11280 if (features & BNXT_HW_FEATURE_VLAN_ALL_RX) 11281 flags |= BNXT_FLAG_STRIP_VLAN; 11282 11283 if (features & NETIF_F_NTUPLE) 11284 flags |= BNXT_FLAG_RFS; 11285 11286 changes = flags ^ bp->flags; 11287 if (changes & BNXT_FLAG_TPA) { 11288 update_tpa = true; 11289 if ((bp->flags & BNXT_FLAG_TPA) == 0 || 11290 (flags & BNXT_FLAG_TPA) == 0 || 11291 (bp->flags & BNXT_FLAG_CHIP_P5)) 11292 re_init = true; 11293 } 11294 11295 if (changes & ~BNXT_FLAG_TPA) 11296 re_init = true; 11297 11298 if (flags != bp->flags) { 11299 u32 old_flags = bp->flags; 11300 11301 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) { 11302 bp->flags = flags; 11303 if (update_tpa) 11304 bnxt_set_ring_params(bp); 11305 return rc; 11306 } 11307 11308 if (re_init) { 11309 bnxt_close_nic(bp, false, false); 11310 bp->flags = flags; 11311 if (update_tpa) 11312 bnxt_set_ring_params(bp); 11313 11314 return bnxt_open_nic(bp, false, false); 11315 } 11316 if (update_tpa) { 11317 bp->flags = flags; 11318 rc = bnxt_set_tpa(bp, 11319 (flags & BNXT_FLAG_TPA) ? 11320 true : false); 11321 if (rc) 11322 bp->flags = old_flags; 11323 } 11324 } 11325 return rc; 11326 } 11327 11328 static bool bnxt_exthdr_check(struct bnxt *bp, struct sk_buff *skb, int nw_off, 11329 u8 **nextp) 11330 { 11331 struct ipv6hdr *ip6h = (struct ipv6hdr *)(skb->data + nw_off); 11332 struct hop_jumbo_hdr *jhdr; 11333 int hdr_count = 0; 11334 u8 *nexthdr; 11335 int start; 11336 11337 /* Check that there are at most 2 IPv6 extension headers, no 11338 * fragment header, and each is <= 64 bytes. 11339 */ 11340 start = nw_off + sizeof(*ip6h); 11341 nexthdr = &ip6h->nexthdr; 11342 while (ipv6_ext_hdr(*nexthdr)) { 11343 struct ipv6_opt_hdr *hp; 11344 int hdrlen; 11345 11346 if (hdr_count >= 3 || *nexthdr == NEXTHDR_NONE || 11347 *nexthdr == NEXTHDR_FRAGMENT) 11348 return false; 11349 hp = __skb_header_pointer(NULL, start, sizeof(*hp), skb->data, 11350 skb_headlen(skb), NULL); 11351 if (!hp) 11352 return false; 11353 if (*nexthdr == NEXTHDR_AUTH) 11354 hdrlen = ipv6_authlen(hp); 11355 else 11356 hdrlen = ipv6_optlen(hp); 11357 11358 if (hdrlen > 64) 11359 return false; 11360 11361 /* The ext header may be a hop-by-hop header inserted for 11362 * big TCP purposes. This will be removed before sending 11363 * from NIC, so do not count it. 11364 */ 11365 if (*nexthdr == NEXTHDR_HOP) { 11366 if (likely(skb->len <= GRO_LEGACY_MAX_SIZE)) 11367 goto increment_hdr; 11368 11369 jhdr = (struct hop_jumbo_hdr *)hp; 11370 if (jhdr->tlv_type != IPV6_TLV_JUMBO || jhdr->hdrlen != 0 || 11371 jhdr->nexthdr != IPPROTO_TCP) 11372 goto increment_hdr; 11373 11374 goto next_hdr; 11375 } 11376 increment_hdr: 11377 hdr_count++; 11378 next_hdr: 11379 nexthdr = &hp->nexthdr; 11380 start += hdrlen; 11381 } 11382 if (nextp) { 11383 /* Caller will check inner protocol */ 11384 if (skb->encapsulation) { 11385 *nextp = nexthdr; 11386 return true; 11387 } 11388 *nextp = NULL; 11389 } 11390 /* Only support TCP/UDP for non-tunneled ipv6 and inner ipv6 */ 11391 return *nexthdr == IPPROTO_TCP || *nexthdr == IPPROTO_UDP; 11392 } 11393 11394 /* For UDP, we can only handle 1 Vxlan port and 1 Geneve port. */ 11395 static bool bnxt_udp_tunl_check(struct bnxt *bp, struct sk_buff *skb) 11396 { 11397 struct udphdr *uh = udp_hdr(skb); 11398 __be16 udp_port = uh->dest; 11399 11400 if (udp_port != bp->vxlan_port && udp_port != bp->nge_port) 11401 return false; 11402 if (skb->inner_protocol_type == ENCAP_TYPE_ETHER) { 11403 struct ethhdr *eh = inner_eth_hdr(skb); 11404 11405 switch (eh->h_proto) { 11406 case htons(ETH_P_IP): 11407 return true; 11408 case htons(ETH_P_IPV6): 11409 return bnxt_exthdr_check(bp, skb, 11410 skb_inner_network_offset(skb), 11411 NULL); 11412 } 11413 } 11414 return false; 11415 } 11416 11417 static bool bnxt_tunl_check(struct bnxt *bp, struct sk_buff *skb, u8 l4_proto) 11418 { 11419 switch (l4_proto) { 11420 case IPPROTO_UDP: 11421 return bnxt_udp_tunl_check(bp, skb); 11422 case IPPROTO_IPIP: 11423 return true; 11424 case IPPROTO_GRE: { 11425 switch (skb->inner_protocol) { 11426 default: 11427 return false; 11428 case htons(ETH_P_IP): 11429 return true; 11430 case htons(ETH_P_IPV6): 11431 fallthrough; 11432 } 11433 } 11434 case IPPROTO_IPV6: 11435 /* Check ext headers of inner ipv6 */ 11436 return bnxt_exthdr_check(bp, skb, skb_inner_network_offset(skb), 11437 NULL); 11438 } 11439 return false; 11440 } 11441 11442 static netdev_features_t bnxt_features_check(struct sk_buff *skb, 11443 struct net_device *dev, 11444 netdev_features_t features) 11445 { 11446 struct bnxt *bp = netdev_priv(dev); 11447 u8 *l4_proto; 11448 11449 features = vlan_features_check(skb, features); 11450 switch (vlan_get_protocol(skb)) { 11451 case htons(ETH_P_IP): 11452 if (!skb->encapsulation) 11453 return features; 11454 l4_proto = &ip_hdr(skb)->protocol; 11455 if (bnxt_tunl_check(bp, skb, *l4_proto)) 11456 return features; 11457 break; 11458 case htons(ETH_P_IPV6): 11459 if (!bnxt_exthdr_check(bp, skb, skb_network_offset(skb), 11460 &l4_proto)) 11461 break; 11462 if (!l4_proto || bnxt_tunl_check(bp, skb, *l4_proto)) 11463 return features; 11464 break; 11465 } 11466 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK); 11467 } 11468 11469 int bnxt_dbg_hwrm_rd_reg(struct bnxt *bp, u32 reg_off, u16 num_words, 11470 u32 *reg_buf) 11471 { 11472 struct hwrm_dbg_read_direct_output *resp; 11473 struct hwrm_dbg_read_direct_input *req; 11474 __le32 *dbg_reg_buf; 11475 dma_addr_t mapping; 11476 int rc, i; 11477 11478 rc = hwrm_req_init(bp, req, HWRM_DBG_READ_DIRECT); 11479 if (rc) 11480 return rc; 11481 11482 dbg_reg_buf = hwrm_req_dma_slice(bp, req, num_words * 4, 11483 &mapping); 11484 if (!dbg_reg_buf) { 11485 rc = -ENOMEM; 11486 goto dbg_rd_reg_exit; 11487 } 11488 11489 req->host_dest_addr = cpu_to_le64(mapping); 11490 11491 resp = hwrm_req_hold(bp, req); 11492 req->read_addr = cpu_to_le32(reg_off + CHIMP_REG_VIEW_ADDR); 11493 req->read_len32 = cpu_to_le32(num_words); 11494 11495 rc = hwrm_req_send(bp, req); 11496 if (rc || resp->error_code) { 11497 rc = -EIO; 11498 goto dbg_rd_reg_exit; 11499 } 11500 for (i = 0; i < num_words; i++) 11501 reg_buf[i] = le32_to_cpu(dbg_reg_buf[i]); 11502 11503 dbg_rd_reg_exit: 11504 hwrm_req_drop(bp, req); 11505 return rc; 11506 } 11507 11508 static int bnxt_dbg_hwrm_ring_info_get(struct bnxt *bp, u8 ring_type, 11509 u32 ring_id, u32 *prod, u32 *cons) 11510 { 11511 struct hwrm_dbg_ring_info_get_output *resp; 11512 struct hwrm_dbg_ring_info_get_input *req; 11513 int rc; 11514 11515 rc = hwrm_req_init(bp, req, HWRM_DBG_RING_INFO_GET); 11516 if (rc) 11517 return rc; 11518 11519 req->ring_type = ring_type; 11520 req->fw_ring_id = cpu_to_le32(ring_id); 11521 resp = hwrm_req_hold(bp, req); 11522 rc = hwrm_req_send(bp, req); 11523 if (!rc) { 11524 *prod = le32_to_cpu(resp->producer_index); 11525 *cons = le32_to_cpu(resp->consumer_index); 11526 } 11527 hwrm_req_drop(bp, req); 11528 return rc; 11529 } 11530 11531 static void bnxt_dump_tx_sw_state(struct bnxt_napi *bnapi) 11532 { 11533 struct bnxt_tx_ring_info *txr = bnapi->tx_ring; 11534 int i = bnapi->index; 11535 11536 if (!txr) 11537 return; 11538 11539 netdev_info(bnapi->bp->dev, "[%d]: tx{fw_ring: %d prod: %x cons: %x}\n", 11540 i, txr->tx_ring_struct.fw_ring_id, txr->tx_prod, 11541 txr->tx_cons); 11542 } 11543 11544 static void bnxt_dump_rx_sw_state(struct bnxt_napi *bnapi) 11545 { 11546 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 11547 int i = bnapi->index; 11548 11549 if (!rxr) 11550 return; 11551 11552 netdev_info(bnapi->bp->dev, "[%d]: rx{fw_ring: %d prod: %x} rx_agg{fw_ring: %d agg_prod: %x sw_agg_prod: %x}\n", 11553 i, rxr->rx_ring_struct.fw_ring_id, rxr->rx_prod, 11554 rxr->rx_agg_ring_struct.fw_ring_id, rxr->rx_agg_prod, 11555 rxr->rx_sw_agg_prod); 11556 } 11557 11558 static void bnxt_dump_cp_sw_state(struct bnxt_napi *bnapi) 11559 { 11560 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 11561 int i = bnapi->index; 11562 11563 netdev_info(bnapi->bp->dev, "[%d]: cp{fw_ring: %d raw_cons: %x}\n", 11564 i, cpr->cp_ring_struct.fw_ring_id, cpr->cp_raw_cons); 11565 } 11566 11567 static void bnxt_dbg_dump_states(struct bnxt *bp) 11568 { 11569 int i; 11570 struct bnxt_napi *bnapi; 11571 11572 for (i = 0; i < bp->cp_nr_rings; i++) { 11573 bnapi = bp->bnapi[i]; 11574 if (netif_msg_drv(bp)) { 11575 bnxt_dump_tx_sw_state(bnapi); 11576 bnxt_dump_rx_sw_state(bnapi); 11577 bnxt_dump_cp_sw_state(bnapi); 11578 } 11579 } 11580 } 11581 11582 static int bnxt_hwrm_rx_ring_reset(struct bnxt *bp, int ring_nr) 11583 { 11584 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[ring_nr]; 11585 struct hwrm_ring_reset_input *req; 11586 struct bnxt_napi *bnapi = rxr->bnapi; 11587 struct bnxt_cp_ring_info *cpr; 11588 u16 cp_ring_id; 11589 int rc; 11590 11591 rc = hwrm_req_init(bp, req, HWRM_RING_RESET); 11592 if (rc) 11593 return rc; 11594 11595 cpr = &bnapi->cp_ring; 11596 cp_ring_id = cpr->cp_ring_struct.fw_ring_id; 11597 req->cmpl_ring = cpu_to_le16(cp_ring_id); 11598 req->ring_type = RING_RESET_REQ_RING_TYPE_RX_RING_GRP; 11599 req->ring_id = cpu_to_le16(bp->grp_info[bnapi->index].fw_grp_id); 11600 return hwrm_req_send_silent(bp, req); 11601 } 11602 11603 static void bnxt_reset_task(struct bnxt *bp, bool silent) 11604 { 11605 if (!silent) 11606 bnxt_dbg_dump_states(bp); 11607 if (netif_running(bp->dev)) { 11608 int rc; 11609 11610 if (silent) { 11611 bnxt_close_nic(bp, false, false); 11612 bnxt_open_nic(bp, false, false); 11613 } else { 11614 bnxt_ulp_stop(bp); 11615 bnxt_close_nic(bp, true, false); 11616 rc = bnxt_open_nic(bp, true, false); 11617 bnxt_ulp_start(bp, rc); 11618 } 11619 } 11620 } 11621 11622 static void bnxt_tx_timeout(struct net_device *dev, unsigned int txqueue) 11623 { 11624 struct bnxt *bp = netdev_priv(dev); 11625 11626 netdev_err(bp->dev, "TX timeout detected, starting reset task!\n"); 11627 bnxt_queue_sp_work(bp, BNXT_RESET_TASK_SP_EVENT); 11628 } 11629 11630 static void bnxt_fw_health_check(struct bnxt *bp) 11631 { 11632 struct bnxt_fw_health *fw_health = bp->fw_health; 11633 struct pci_dev *pdev = bp->pdev; 11634 u32 val; 11635 11636 if (!fw_health->enabled || test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) 11637 return; 11638 11639 /* Make sure it is enabled before checking the tmr_counter. */ 11640 smp_rmb(); 11641 if (fw_health->tmr_counter) { 11642 fw_health->tmr_counter--; 11643 return; 11644 } 11645 11646 val = bnxt_fw_health_readl(bp, BNXT_FW_HEARTBEAT_REG); 11647 if (val == fw_health->last_fw_heartbeat && pci_device_is_present(pdev)) { 11648 fw_health->arrests++; 11649 goto fw_reset; 11650 } 11651 11652 fw_health->last_fw_heartbeat = val; 11653 11654 val = bnxt_fw_health_readl(bp, BNXT_FW_RESET_CNT_REG); 11655 if (val != fw_health->last_fw_reset_cnt && pci_device_is_present(pdev)) { 11656 fw_health->discoveries++; 11657 goto fw_reset; 11658 } 11659 11660 fw_health->tmr_counter = fw_health->tmr_multiplier; 11661 return; 11662 11663 fw_reset: 11664 bnxt_queue_sp_work(bp, BNXT_FW_EXCEPTION_SP_EVENT); 11665 } 11666 11667 static void bnxt_timer(struct timer_list *t) 11668 { 11669 struct bnxt *bp = from_timer(bp, t, timer); 11670 struct net_device *dev = bp->dev; 11671 11672 if (!netif_running(dev) || !test_bit(BNXT_STATE_OPEN, &bp->state)) 11673 return; 11674 11675 if (atomic_read(&bp->intr_sem) != 0) 11676 goto bnxt_restart_timer; 11677 11678 if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY) 11679 bnxt_fw_health_check(bp); 11680 11681 if (BNXT_LINK_IS_UP(bp) && bp->stats_coal_ticks) 11682 bnxt_queue_sp_work(bp, BNXT_PERIODIC_STATS_SP_EVENT); 11683 11684 if (bnxt_tc_flower_enabled(bp)) 11685 bnxt_queue_sp_work(bp, BNXT_FLOW_STATS_SP_EVENT); 11686 11687 #ifdef CONFIG_RFS_ACCEL 11688 if ((bp->flags & BNXT_FLAG_RFS) && bp->ntp_fltr_count) 11689 bnxt_queue_sp_work(bp, BNXT_RX_NTP_FLTR_SP_EVENT); 11690 #endif /*CONFIG_RFS_ACCEL*/ 11691 11692 if (bp->link_info.phy_retry) { 11693 if (time_after(jiffies, bp->link_info.phy_retry_expires)) { 11694 bp->link_info.phy_retry = false; 11695 netdev_warn(bp->dev, "failed to update phy settings after maximum retries.\n"); 11696 } else { 11697 bnxt_queue_sp_work(bp, BNXT_UPDATE_PHY_SP_EVENT); 11698 } 11699 } 11700 11701 if (test_bit(BNXT_STATE_L2_FILTER_RETRY, &bp->state)) 11702 bnxt_queue_sp_work(bp, BNXT_RX_MASK_SP_EVENT); 11703 11704 if ((bp->flags & BNXT_FLAG_CHIP_P5) && !bp->chip_rev && 11705 netif_carrier_ok(dev)) 11706 bnxt_queue_sp_work(bp, BNXT_RING_COAL_NOW_SP_EVENT); 11707 11708 bnxt_restart_timer: 11709 mod_timer(&bp->timer, jiffies + bp->current_interval); 11710 } 11711 11712 static void bnxt_rtnl_lock_sp(struct bnxt *bp) 11713 { 11714 /* We are called from bnxt_sp_task which has BNXT_STATE_IN_SP_TASK 11715 * set. If the device is being closed, bnxt_close() may be holding 11716 * rtnl() and waiting for BNXT_STATE_IN_SP_TASK to clear. So we 11717 * must clear BNXT_STATE_IN_SP_TASK before holding rtnl(). 11718 */ 11719 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state); 11720 rtnl_lock(); 11721 } 11722 11723 static void bnxt_rtnl_unlock_sp(struct bnxt *bp) 11724 { 11725 set_bit(BNXT_STATE_IN_SP_TASK, &bp->state); 11726 rtnl_unlock(); 11727 } 11728 11729 /* Only called from bnxt_sp_task() */ 11730 static void bnxt_reset(struct bnxt *bp, bool silent) 11731 { 11732 bnxt_rtnl_lock_sp(bp); 11733 if (test_bit(BNXT_STATE_OPEN, &bp->state)) 11734 bnxt_reset_task(bp, silent); 11735 bnxt_rtnl_unlock_sp(bp); 11736 } 11737 11738 /* Only called from bnxt_sp_task() */ 11739 static void bnxt_rx_ring_reset(struct bnxt *bp) 11740 { 11741 int i; 11742 11743 bnxt_rtnl_lock_sp(bp); 11744 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) { 11745 bnxt_rtnl_unlock_sp(bp); 11746 return; 11747 } 11748 /* Disable and flush TPA before resetting the RX ring */ 11749 if (bp->flags & BNXT_FLAG_TPA) 11750 bnxt_set_tpa(bp, false); 11751 for (i = 0; i < bp->rx_nr_rings; i++) { 11752 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 11753 struct bnxt_cp_ring_info *cpr; 11754 int rc; 11755 11756 if (!rxr->bnapi->in_reset) 11757 continue; 11758 11759 rc = bnxt_hwrm_rx_ring_reset(bp, i); 11760 if (rc) { 11761 if (rc == -EINVAL || rc == -EOPNOTSUPP) 11762 netdev_info_once(bp->dev, "RX ring reset not supported by firmware, falling back to global reset\n"); 11763 else 11764 netdev_warn(bp->dev, "RX ring reset failed, rc = %d, falling back to global reset\n", 11765 rc); 11766 bnxt_reset_task(bp, true); 11767 break; 11768 } 11769 bnxt_free_one_rx_ring_skbs(bp, i); 11770 rxr->rx_prod = 0; 11771 rxr->rx_agg_prod = 0; 11772 rxr->rx_sw_agg_prod = 0; 11773 rxr->rx_next_cons = 0; 11774 rxr->bnapi->in_reset = false; 11775 bnxt_alloc_one_rx_ring(bp, i); 11776 cpr = &rxr->bnapi->cp_ring; 11777 cpr->sw_stats.rx.rx_resets++; 11778 if (bp->flags & BNXT_FLAG_AGG_RINGS) 11779 bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod); 11780 bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod); 11781 } 11782 if (bp->flags & BNXT_FLAG_TPA) 11783 bnxt_set_tpa(bp, true); 11784 bnxt_rtnl_unlock_sp(bp); 11785 } 11786 11787 static void bnxt_fw_reset_close(struct bnxt *bp) 11788 { 11789 bnxt_ulp_stop(bp); 11790 /* When firmware is in fatal state, quiesce device and disable 11791 * bus master to prevent any potential bad DMAs before freeing 11792 * kernel memory. 11793 */ 11794 if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state)) { 11795 u16 val = 0; 11796 11797 pci_read_config_word(bp->pdev, PCI_SUBSYSTEM_ID, &val); 11798 if (val == 0xffff) 11799 bp->fw_reset_min_dsecs = 0; 11800 bnxt_tx_disable(bp); 11801 bnxt_disable_napi(bp); 11802 bnxt_disable_int_sync(bp); 11803 bnxt_free_irq(bp); 11804 bnxt_clear_int_mode(bp); 11805 pci_disable_device(bp->pdev); 11806 } 11807 __bnxt_close_nic(bp, true, false); 11808 bnxt_vf_reps_free(bp); 11809 bnxt_clear_int_mode(bp); 11810 bnxt_hwrm_func_drv_unrgtr(bp); 11811 if (pci_is_enabled(bp->pdev)) 11812 pci_disable_device(bp->pdev); 11813 bnxt_free_ctx_mem(bp); 11814 kfree(bp->ctx); 11815 bp->ctx = NULL; 11816 } 11817 11818 static bool is_bnxt_fw_ok(struct bnxt *bp) 11819 { 11820 struct bnxt_fw_health *fw_health = bp->fw_health; 11821 bool no_heartbeat = false, has_reset = false; 11822 u32 val; 11823 11824 val = bnxt_fw_health_readl(bp, BNXT_FW_HEARTBEAT_REG); 11825 if (val == fw_health->last_fw_heartbeat) 11826 no_heartbeat = true; 11827 11828 val = bnxt_fw_health_readl(bp, BNXT_FW_RESET_CNT_REG); 11829 if (val != fw_health->last_fw_reset_cnt) 11830 has_reset = true; 11831 11832 if (!no_heartbeat && has_reset) 11833 return true; 11834 11835 return false; 11836 } 11837 11838 /* rtnl_lock is acquired before calling this function */ 11839 static void bnxt_force_fw_reset(struct bnxt *bp) 11840 { 11841 struct bnxt_fw_health *fw_health = bp->fw_health; 11842 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 11843 u32 wait_dsecs; 11844 11845 if (!test_bit(BNXT_STATE_OPEN, &bp->state) || 11846 test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) 11847 return; 11848 11849 if (ptp) { 11850 spin_lock_bh(&ptp->ptp_lock); 11851 set_bit(BNXT_STATE_IN_FW_RESET, &bp->state); 11852 spin_unlock_bh(&ptp->ptp_lock); 11853 } else { 11854 set_bit(BNXT_STATE_IN_FW_RESET, &bp->state); 11855 } 11856 bnxt_fw_reset_close(bp); 11857 wait_dsecs = fw_health->master_func_wait_dsecs; 11858 if (fw_health->primary) { 11859 if (fw_health->flags & ERROR_RECOVERY_QCFG_RESP_FLAGS_CO_CPU) 11860 wait_dsecs = 0; 11861 bp->fw_reset_state = BNXT_FW_RESET_STATE_RESET_FW; 11862 } else { 11863 bp->fw_reset_timestamp = jiffies + wait_dsecs * HZ / 10; 11864 wait_dsecs = fw_health->normal_func_wait_dsecs; 11865 bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV; 11866 } 11867 11868 bp->fw_reset_min_dsecs = fw_health->post_reset_wait_dsecs; 11869 bp->fw_reset_max_dsecs = fw_health->post_reset_max_wait_dsecs; 11870 bnxt_queue_fw_reset_work(bp, wait_dsecs * HZ / 10); 11871 } 11872 11873 void bnxt_fw_exception(struct bnxt *bp) 11874 { 11875 netdev_warn(bp->dev, "Detected firmware fatal condition, initiating reset\n"); 11876 set_bit(BNXT_STATE_FW_FATAL_COND, &bp->state); 11877 bnxt_rtnl_lock_sp(bp); 11878 bnxt_force_fw_reset(bp); 11879 bnxt_rtnl_unlock_sp(bp); 11880 } 11881 11882 /* Returns the number of registered VFs, or 1 if VF configuration is pending, or 11883 * < 0 on error. 11884 */ 11885 static int bnxt_get_registered_vfs(struct bnxt *bp) 11886 { 11887 #ifdef CONFIG_BNXT_SRIOV 11888 int rc; 11889 11890 if (!BNXT_PF(bp)) 11891 return 0; 11892 11893 rc = bnxt_hwrm_func_qcfg(bp); 11894 if (rc) { 11895 netdev_err(bp->dev, "func_qcfg cmd failed, rc = %d\n", rc); 11896 return rc; 11897 } 11898 if (bp->pf.registered_vfs) 11899 return bp->pf.registered_vfs; 11900 if (bp->sriov_cfg) 11901 return 1; 11902 #endif 11903 return 0; 11904 } 11905 11906 void bnxt_fw_reset(struct bnxt *bp) 11907 { 11908 bnxt_rtnl_lock_sp(bp); 11909 if (test_bit(BNXT_STATE_OPEN, &bp->state) && 11910 !test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) { 11911 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 11912 int n = 0, tmo; 11913 11914 if (ptp) { 11915 spin_lock_bh(&ptp->ptp_lock); 11916 set_bit(BNXT_STATE_IN_FW_RESET, &bp->state); 11917 spin_unlock_bh(&ptp->ptp_lock); 11918 } else { 11919 set_bit(BNXT_STATE_IN_FW_RESET, &bp->state); 11920 } 11921 if (bp->pf.active_vfs && 11922 !test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state)) 11923 n = bnxt_get_registered_vfs(bp); 11924 if (n < 0) { 11925 netdev_err(bp->dev, "Firmware reset aborted, rc = %d\n", 11926 n); 11927 clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state); 11928 dev_close(bp->dev); 11929 goto fw_reset_exit; 11930 } else if (n > 0) { 11931 u16 vf_tmo_dsecs = n * 10; 11932 11933 if (bp->fw_reset_max_dsecs < vf_tmo_dsecs) 11934 bp->fw_reset_max_dsecs = vf_tmo_dsecs; 11935 bp->fw_reset_state = 11936 BNXT_FW_RESET_STATE_POLL_VF; 11937 bnxt_queue_fw_reset_work(bp, HZ / 10); 11938 goto fw_reset_exit; 11939 } 11940 bnxt_fw_reset_close(bp); 11941 if (bp->fw_cap & BNXT_FW_CAP_ERR_RECOVER_RELOAD) { 11942 bp->fw_reset_state = BNXT_FW_RESET_STATE_POLL_FW_DOWN; 11943 tmo = HZ / 10; 11944 } else { 11945 bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV; 11946 tmo = bp->fw_reset_min_dsecs * HZ / 10; 11947 } 11948 bnxt_queue_fw_reset_work(bp, tmo); 11949 } 11950 fw_reset_exit: 11951 bnxt_rtnl_unlock_sp(bp); 11952 } 11953 11954 static void bnxt_chk_missed_irq(struct bnxt *bp) 11955 { 11956 int i; 11957 11958 if (!(bp->flags & BNXT_FLAG_CHIP_P5)) 11959 return; 11960 11961 for (i = 0; i < bp->cp_nr_rings; i++) { 11962 struct bnxt_napi *bnapi = bp->bnapi[i]; 11963 struct bnxt_cp_ring_info *cpr; 11964 u32 fw_ring_id; 11965 int j; 11966 11967 if (!bnapi) 11968 continue; 11969 11970 cpr = &bnapi->cp_ring; 11971 for (j = 0; j < 2; j++) { 11972 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j]; 11973 u32 val[2]; 11974 11975 if (!cpr2 || cpr2->has_more_work || 11976 !bnxt_has_work(bp, cpr2)) 11977 continue; 11978 11979 if (cpr2->cp_raw_cons != cpr2->last_cp_raw_cons) { 11980 cpr2->last_cp_raw_cons = cpr2->cp_raw_cons; 11981 continue; 11982 } 11983 fw_ring_id = cpr2->cp_ring_struct.fw_ring_id; 11984 bnxt_dbg_hwrm_ring_info_get(bp, 11985 DBG_RING_INFO_GET_REQ_RING_TYPE_L2_CMPL, 11986 fw_ring_id, &val[0], &val[1]); 11987 cpr->sw_stats.cmn.missed_irqs++; 11988 } 11989 } 11990 } 11991 11992 static void bnxt_cfg_ntp_filters(struct bnxt *); 11993 11994 static void bnxt_init_ethtool_link_settings(struct bnxt *bp) 11995 { 11996 struct bnxt_link_info *link_info = &bp->link_info; 11997 11998 if (BNXT_AUTO_MODE(link_info->auto_mode)) { 11999 link_info->autoneg = BNXT_AUTONEG_SPEED; 12000 if (bp->hwrm_spec_code >= 0x10201) { 12001 if (link_info->auto_pause_setting & 12002 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE) 12003 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL; 12004 } else { 12005 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL; 12006 } 12007 link_info->advertising = link_info->auto_link_speeds; 12008 link_info->advertising_pam4 = link_info->auto_pam4_link_speeds; 12009 } else { 12010 link_info->req_link_speed = link_info->force_link_speed; 12011 link_info->req_signal_mode = BNXT_SIG_MODE_NRZ; 12012 if (link_info->force_pam4_link_speed) { 12013 link_info->req_link_speed = 12014 link_info->force_pam4_link_speed; 12015 link_info->req_signal_mode = BNXT_SIG_MODE_PAM4; 12016 } 12017 link_info->req_duplex = link_info->duplex_setting; 12018 } 12019 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) 12020 link_info->req_flow_ctrl = 12021 link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH; 12022 else 12023 link_info->req_flow_ctrl = link_info->force_pause_setting; 12024 } 12025 12026 static void bnxt_fw_echo_reply(struct bnxt *bp) 12027 { 12028 struct bnxt_fw_health *fw_health = bp->fw_health; 12029 struct hwrm_func_echo_response_input *req; 12030 int rc; 12031 12032 rc = hwrm_req_init(bp, req, HWRM_FUNC_ECHO_RESPONSE); 12033 if (rc) 12034 return; 12035 req->event_data1 = cpu_to_le32(fw_health->echo_req_data1); 12036 req->event_data2 = cpu_to_le32(fw_health->echo_req_data2); 12037 hwrm_req_send(bp, req); 12038 } 12039 12040 static void bnxt_sp_task(struct work_struct *work) 12041 { 12042 struct bnxt *bp = container_of(work, struct bnxt, sp_task); 12043 12044 set_bit(BNXT_STATE_IN_SP_TASK, &bp->state); 12045 smp_mb__after_atomic(); 12046 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) { 12047 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state); 12048 return; 12049 } 12050 12051 if (test_and_clear_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event)) 12052 bnxt_cfg_rx_mode(bp); 12053 12054 if (test_and_clear_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event)) 12055 bnxt_cfg_ntp_filters(bp); 12056 if (test_and_clear_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event)) 12057 bnxt_hwrm_exec_fwd_req(bp); 12058 if (test_and_clear_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event)) { 12059 bnxt_hwrm_port_qstats(bp, 0); 12060 bnxt_hwrm_port_qstats_ext(bp, 0); 12061 bnxt_accumulate_all_stats(bp); 12062 } 12063 12064 if (test_and_clear_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event)) { 12065 int rc; 12066 12067 mutex_lock(&bp->link_lock); 12068 if (test_and_clear_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT, 12069 &bp->sp_event)) 12070 bnxt_hwrm_phy_qcaps(bp); 12071 12072 rc = bnxt_update_link(bp, true); 12073 if (rc) 12074 netdev_err(bp->dev, "SP task can't update link (rc: %x)\n", 12075 rc); 12076 12077 if (test_and_clear_bit(BNXT_LINK_CFG_CHANGE_SP_EVENT, 12078 &bp->sp_event)) 12079 bnxt_init_ethtool_link_settings(bp); 12080 mutex_unlock(&bp->link_lock); 12081 } 12082 if (test_and_clear_bit(BNXT_UPDATE_PHY_SP_EVENT, &bp->sp_event)) { 12083 int rc; 12084 12085 mutex_lock(&bp->link_lock); 12086 rc = bnxt_update_phy_setting(bp); 12087 mutex_unlock(&bp->link_lock); 12088 if (rc) { 12089 netdev_warn(bp->dev, "update phy settings retry failed\n"); 12090 } else { 12091 bp->link_info.phy_retry = false; 12092 netdev_info(bp->dev, "update phy settings retry succeeded\n"); 12093 } 12094 } 12095 if (test_and_clear_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event)) { 12096 mutex_lock(&bp->link_lock); 12097 bnxt_get_port_module_status(bp); 12098 mutex_unlock(&bp->link_lock); 12099 } 12100 12101 if (test_and_clear_bit(BNXT_FLOW_STATS_SP_EVENT, &bp->sp_event)) 12102 bnxt_tc_flow_stats_work(bp); 12103 12104 if (test_and_clear_bit(BNXT_RING_COAL_NOW_SP_EVENT, &bp->sp_event)) 12105 bnxt_chk_missed_irq(bp); 12106 12107 if (test_and_clear_bit(BNXT_FW_ECHO_REQUEST_SP_EVENT, &bp->sp_event)) 12108 bnxt_fw_echo_reply(bp); 12109 12110 /* These functions below will clear BNXT_STATE_IN_SP_TASK. They 12111 * must be the last functions to be called before exiting. 12112 */ 12113 if (test_and_clear_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event)) 12114 bnxt_reset(bp, false); 12115 12116 if (test_and_clear_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event)) 12117 bnxt_reset(bp, true); 12118 12119 if (test_and_clear_bit(BNXT_RST_RING_SP_EVENT, &bp->sp_event)) 12120 bnxt_rx_ring_reset(bp); 12121 12122 if (test_and_clear_bit(BNXT_FW_RESET_NOTIFY_SP_EVENT, &bp->sp_event)) { 12123 if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state) || 12124 test_bit(BNXT_STATE_FW_NON_FATAL_COND, &bp->state)) 12125 bnxt_devlink_health_fw_report(bp); 12126 else 12127 bnxt_fw_reset(bp); 12128 } 12129 12130 if (test_and_clear_bit(BNXT_FW_EXCEPTION_SP_EVENT, &bp->sp_event)) { 12131 if (!is_bnxt_fw_ok(bp)) 12132 bnxt_devlink_health_fw_report(bp); 12133 } 12134 12135 smp_mb__before_atomic(); 12136 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state); 12137 } 12138 12139 /* Under rtnl_lock */ 12140 int bnxt_check_rings(struct bnxt *bp, int tx, int rx, bool sh, int tcs, 12141 int tx_xdp) 12142 { 12143 int max_rx, max_tx, tx_sets = 1; 12144 int tx_rings_needed, stats; 12145 int rx_rings = rx; 12146 int cp, vnics, rc; 12147 12148 if (tcs) 12149 tx_sets = tcs; 12150 12151 rc = bnxt_get_max_rings(bp, &max_rx, &max_tx, sh); 12152 if (rc) 12153 return rc; 12154 12155 if (max_rx < rx) 12156 return -ENOMEM; 12157 12158 tx_rings_needed = tx * tx_sets + tx_xdp; 12159 if (max_tx < tx_rings_needed) 12160 return -ENOMEM; 12161 12162 vnics = 1; 12163 if ((bp->flags & (BNXT_FLAG_RFS | BNXT_FLAG_CHIP_P5)) == BNXT_FLAG_RFS) 12164 vnics += rx_rings; 12165 12166 if (bp->flags & BNXT_FLAG_AGG_RINGS) 12167 rx_rings <<= 1; 12168 cp = sh ? max_t(int, tx_rings_needed, rx) : tx_rings_needed + rx; 12169 stats = cp; 12170 if (BNXT_NEW_RM(bp)) { 12171 cp += bnxt_get_ulp_msix_num(bp); 12172 stats += bnxt_get_ulp_stat_ctxs(bp); 12173 } 12174 return bnxt_hwrm_check_rings(bp, tx_rings_needed, rx_rings, rx, cp, 12175 stats, vnics); 12176 } 12177 12178 static void bnxt_unmap_bars(struct bnxt *bp, struct pci_dev *pdev) 12179 { 12180 if (bp->bar2) { 12181 pci_iounmap(pdev, bp->bar2); 12182 bp->bar2 = NULL; 12183 } 12184 12185 if (bp->bar1) { 12186 pci_iounmap(pdev, bp->bar1); 12187 bp->bar1 = NULL; 12188 } 12189 12190 if (bp->bar0) { 12191 pci_iounmap(pdev, bp->bar0); 12192 bp->bar0 = NULL; 12193 } 12194 } 12195 12196 static void bnxt_cleanup_pci(struct bnxt *bp) 12197 { 12198 bnxt_unmap_bars(bp, bp->pdev); 12199 pci_release_regions(bp->pdev); 12200 if (pci_is_enabled(bp->pdev)) 12201 pci_disable_device(bp->pdev); 12202 } 12203 12204 static void bnxt_init_dflt_coal(struct bnxt *bp) 12205 { 12206 struct bnxt_coal_cap *coal_cap = &bp->coal_cap; 12207 struct bnxt_coal *coal; 12208 u16 flags = 0; 12209 12210 if (coal_cap->cmpl_params & 12211 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET) 12212 flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET; 12213 12214 /* Tick values in micro seconds. 12215 * 1 coal_buf x bufs_per_record = 1 completion record. 12216 */ 12217 coal = &bp->rx_coal; 12218 coal->coal_ticks = 10; 12219 coal->coal_bufs = 30; 12220 coal->coal_ticks_irq = 1; 12221 coal->coal_bufs_irq = 2; 12222 coal->idle_thresh = 50; 12223 coal->bufs_per_record = 2; 12224 coal->budget = 64; /* NAPI budget */ 12225 coal->flags = flags; 12226 12227 coal = &bp->tx_coal; 12228 coal->coal_ticks = 28; 12229 coal->coal_bufs = 30; 12230 coal->coal_ticks_irq = 2; 12231 coal->coal_bufs_irq = 2; 12232 coal->bufs_per_record = 1; 12233 coal->flags = flags; 12234 12235 bp->stats_coal_ticks = BNXT_DEF_STATS_COAL_TICKS; 12236 } 12237 12238 static int bnxt_fw_init_one_p1(struct bnxt *bp) 12239 { 12240 int rc; 12241 12242 bp->fw_cap = 0; 12243 rc = bnxt_hwrm_ver_get(bp); 12244 bnxt_try_map_fw_health_reg(bp); 12245 if (rc) { 12246 rc = bnxt_try_recover_fw(bp); 12247 if (rc) 12248 return rc; 12249 rc = bnxt_hwrm_ver_get(bp); 12250 if (rc) 12251 return rc; 12252 } 12253 12254 bnxt_nvm_cfg_ver_get(bp); 12255 12256 rc = bnxt_hwrm_func_reset(bp); 12257 if (rc) 12258 return -ENODEV; 12259 12260 bnxt_hwrm_fw_set_time(bp); 12261 return 0; 12262 } 12263 12264 static int bnxt_fw_init_one_p2(struct bnxt *bp) 12265 { 12266 int rc; 12267 12268 /* Get the MAX capabilities for this function */ 12269 rc = bnxt_hwrm_func_qcaps(bp); 12270 if (rc) { 12271 netdev_err(bp->dev, "hwrm query capability failure rc: %x\n", 12272 rc); 12273 return -ENODEV; 12274 } 12275 12276 rc = bnxt_hwrm_cfa_adv_flow_mgnt_qcaps(bp); 12277 if (rc) 12278 netdev_warn(bp->dev, "hwrm query adv flow mgnt failure rc: %d\n", 12279 rc); 12280 12281 if (bnxt_alloc_fw_health(bp)) { 12282 netdev_warn(bp->dev, "no memory for firmware error recovery\n"); 12283 } else { 12284 rc = bnxt_hwrm_error_recovery_qcfg(bp); 12285 if (rc) 12286 netdev_warn(bp->dev, "hwrm query error recovery failure rc: %d\n", 12287 rc); 12288 } 12289 12290 rc = bnxt_hwrm_func_drv_rgtr(bp, NULL, 0, false); 12291 if (rc) 12292 return -ENODEV; 12293 12294 bnxt_hwrm_func_qcfg(bp); 12295 bnxt_hwrm_vnic_qcaps(bp); 12296 bnxt_hwrm_port_led_qcaps(bp); 12297 bnxt_ethtool_init(bp); 12298 if (bp->fw_cap & BNXT_FW_CAP_PTP) 12299 __bnxt_hwrm_ptp_qcfg(bp); 12300 bnxt_dcb_init(bp); 12301 return 0; 12302 } 12303 12304 static void bnxt_set_dflt_rss_hash_type(struct bnxt *bp) 12305 { 12306 bp->flags &= ~BNXT_FLAG_UDP_RSS_CAP; 12307 bp->rss_hash_cfg = VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 | 12308 VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 | 12309 VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 | 12310 VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6; 12311 if (bp->fw_cap & BNXT_FW_CAP_RSS_HASH_TYPE_DELTA) 12312 bp->rss_hash_delta = bp->rss_hash_cfg; 12313 if (BNXT_CHIP_P4_PLUS(bp) && bp->hwrm_spec_code >= 0x10501) { 12314 bp->flags |= BNXT_FLAG_UDP_RSS_CAP; 12315 bp->rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 | 12316 VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6; 12317 } 12318 } 12319 12320 static void bnxt_set_dflt_rfs(struct bnxt *bp) 12321 { 12322 struct net_device *dev = bp->dev; 12323 12324 dev->hw_features &= ~NETIF_F_NTUPLE; 12325 dev->features &= ~NETIF_F_NTUPLE; 12326 bp->flags &= ~BNXT_FLAG_RFS; 12327 if (bnxt_rfs_supported(bp)) { 12328 dev->hw_features |= NETIF_F_NTUPLE; 12329 if (bnxt_rfs_capable(bp)) { 12330 bp->flags |= BNXT_FLAG_RFS; 12331 dev->features |= NETIF_F_NTUPLE; 12332 } 12333 } 12334 } 12335 12336 static void bnxt_fw_init_one_p3(struct bnxt *bp) 12337 { 12338 struct pci_dev *pdev = bp->pdev; 12339 12340 bnxt_set_dflt_rss_hash_type(bp); 12341 bnxt_set_dflt_rfs(bp); 12342 12343 bnxt_get_wol_settings(bp); 12344 if (bp->flags & BNXT_FLAG_WOL_CAP) 12345 device_set_wakeup_enable(&pdev->dev, bp->wol); 12346 else 12347 device_set_wakeup_capable(&pdev->dev, false); 12348 12349 bnxt_hwrm_set_cache_line_size(bp, cache_line_size()); 12350 bnxt_hwrm_coal_params_qcaps(bp); 12351 } 12352 12353 static int bnxt_probe_phy(struct bnxt *bp, bool fw_dflt); 12354 12355 int bnxt_fw_init_one(struct bnxt *bp) 12356 { 12357 int rc; 12358 12359 rc = bnxt_fw_init_one_p1(bp); 12360 if (rc) { 12361 netdev_err(bp->dev, "Firmware init phase 1 failed\n"); 12362 return rc; 12363 } 12364 rc = bnxt_fw_init_one_p2(bp); 12365 if (rc) { 12366 netdev_err(bp->dev, "Firmware init phase 2 failed\n"); 12367 return rc; 12368 } 12369 rc = bnxt_probe_phy(bp, false); 12370 if (rc) 12371 return rc; 12372 rc = bnxt_approve_mac(bp, bp->dev->dev_addr, false); 12373 if (rc) 12374 return rc; 12375 12376 bnxt_fw_init_one_p3(bp); 12377 return 0; 12378 } 12379 12380 static void bnxt_fw_reset_writel(struct bnxt *bp, int reg_idx) 12381 { 12382 struct bnxt_fw_health *fw_health = bp->fw_health; 12383 u32 reg = fw_health->fw_reset_seq_regs[reg_idx]; 12384 u32 val = fw_health->fw_reset_seq_vals[reg_idx]; 12385 u32 reg_type, reg_off, delay_msecs; 12386 12387 delay_msecs = fw_health->fw_reset_seq_delay_msec[reg_idx]; 12388 reg_type = BNXT_FW_HEALTH_REG_TYPE(reg); 12389 reg_off = BNXT_FW_HEALTH_REG_OFF(reg); 12390 switch (reg_type) { 12391 case BNXT_FW_HEALTH_REG_TYPE_CFG: 12392 pci_write_config_dword(bp->pdev, reg_off, val); 12393 break; 12394 case BNXT_FW_HEALTH_REG_TYPE_GRC: 12395 writel(reg_off & BNXT_GRC_BASE_MASK, 12396 bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4); 12397 reg_off = (reg_off & BNXT_GRC_OFFSET_MASK) + 0x2000; 12398 fallthrough; 12399 case BNXT_FW_HEALTH_REG_TYPE_BAR0: 12400 writel(val, bp->bar0 + reg_off); 12401 break; 12402 case BNXT_FW_HEALTH_REG_TYPE_BAR1: 12403 writel(val, bp->bar1 + reg_off); 12404 break; 12405 } 12406 if (delay_msecs) { 12407 pci_read_config_dword(bp->pdev, 0, &val); 12408 msleep(delay_msecs); 12409 } 12410 } 12411 12412 bool bnxt_hwrm_reset_permitted(struct bnxt *bp) 12413 { 12414 struct hwrm_func_qcfg_output *resp; 12415 struct hwrm_func_qcfg_input *req; 12416 bool result = true; /* firmware will enforce if unknown */ 12417 12418 if (~bp->fw_cap & BNXT_FW_CAP_HOT_RESET_IF) 12419 return result; 12420 12421 if (hwrm_req_init(bp, req, HWRM_FUNC_QCFG)) 12422 return result; 12423 12424 req->fid = cpu_to_le16(0xffff); 12425 resp = hwrm_req_hold(bp, req); 12426 if (!hwrm_req_send(bp, req)) 12427 result = !!(le16_to_cpu(resp->flags) & 12428 FUNC_QCFG_RESP_FLAGS_HOT_RESET_ALLOWED); 12429 hwrm_req_drop(bp, req); 12430 return result; 12431 } 12432 12433 static void bnxt_reset_all(struct bnxt *bp) 12434 { 12435 struct bnxt_fw_health *fw_health = bp->fw_health; 12436 int i, rc; 12437 12438 if (bp->fw_cap & BNXT_FW_CAP_ERR_RECOVER_RELOAD) { 12439 bnxt_fw_reset_via_optee(bp); 12440 bp->fw_reset_timestamp = jiffies; 12441 return; 12442 } 12443 12444 if (fw_health->flags & ERROR_RECOVERY_QCFG_RESP_FLAGS_HOST) { 12445 for (i = 0; i < fw_health->fw_reset_seq_cnt; i++) 12446 bnxt_fw_reset_writel(bp, i); 12447 } else if (fw_health->flags & ERROR_RECOVERY_QCFG_RESP_FLAGS_CO_CPU) { 12448 struct hwrm_fw_reset_input *req; 12449 12450 rc = hwrm_req_init(bp, req, HWRM_FW_RESET); 12451 if (!rc) { 12452 req->target_id = cpu_to_le16(HWRM_TARGET_ID_KONG); 12453 req->embedded_proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP; 12454 req->selfrst_status = FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP; 12455 req->flags = FW_RESET_REQ_FLAGS_RESET_GRACEFUL; 12456 rc = hwrm_req_send(bp, req); 12457 } 12458 if (rc != -ENODEV) 12459 netdev_warn(bp->dev, "Unable to reset FW rc=%d\n", rc); 12460 } 12461 bp->fw_reset_timestamp = jiffies; 12462 } 12463 12464 static bool bnxt_fw_reset_timeout(struct bnxt *bp) 12465 { 12466 return time_after(jiffies, bp->fw_reset_timestamp + 12467 (bp->fw_reset_max_dsecs * HZ / 10)); 12468 } 12469 12470 static void bnxt_fw_reset_abort(struct bnxt *bp, int rc) 12471 { 12472 clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state); 12473 if (bp->fw_reset_state != BNXT_FW_RESET_STATE_POLL_VF) { 12474 bnxt_ulp_start(bp, rc); 12475 bnxt_dl_health_fw_status_update(bp, false); 12476 } 12477 bp->fw_reset_state = 0; 12478 dev_close(bp->dev); 12479 } 12480 12481 static void bnxt_fw_reset_task(struct work_struct *work) 12482 { 12483 struct bnxt *bp = container_of(work, struct bnxt, fw_reset_task.work); 12484 int rc = 0; 12485 12486 if (!test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) { 12487 netdev_err(bp->dev, "bnxt_fw_reset_task() called when not in fw reset mode!\n"); 12488 return; 12489 } 12490 12491 switch (bp->fw_reset_state) { 12492 case BNXT_FW_RESET_STATE_POLL_VF: { 12493 int n = bnxt_get_registered_vfs(bp); 12494 int tmo; 12495 12496 if (n < 0) { 12497 netdev_err(bp->dev, "Firmware reset aborted, subsequent func_qcfg cmd failed, rc = %d, %d msecs since reset timestamp\n", 12498 n, jiffies_to_msecs(jiffies - 12499 bp->fw_reset_timestamp)); 12500 goto fw_reset_abort; 12501 } else if (n > 0) { 12502 if (bnxt_fw_reset_timeout(bp)) { 12503 clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state); 12504 bp->fw_reset_state = 0; 12505 netdev_err(bp->dev, "Firmware reset aborted, bnxt_get_registered_vfs() returns %d\n", 12506 n); 12507 return; 12508 } 12509 bnxt_queue_fw_reset_work(bp, HZ / 10); 12510 return; 12511 } 12512 bp->fw_reset_timestamp = jiffies; 12513 rtnl_lock(); 12514 if (test_bit(BNXT_STATE_ABORT_ERR, &bp->state)) { 12515 bnxt_fw_reset_abort(bp, rc); 12516 rtnl_unlock(); 12517 return; 12518 } 12519 bnxt_fw_reset_close(bp); 12520 if (bp->fw_cap & BNXT_FW_CAP_ERR_RECOVER_RELOAD) { 12521 bp->fw_reset_state = BNXT_FW_RESET_STATE_POLL_FW_DOWN; 12522 tmo = HZ / 10; 12523 } else { 12524 bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV; 12525 tmo = bp->fw_reset_min_dsecs * HZ / 10; 12526 } 12527 rtnl_unlock(); 12528 bnxt_queue_fw_reset_work(bp, tmo); 12529 return; 12530 } 12531 case BNXT_FW_RESET_STATE_POLL_FW_DOWN: { 12532 u32 val; 12533 12534 val = bnxt_fw_health_readl(bp, BNXT_FW_HEALTH_REG); 12535 if (!(val & BNXT_FW_STATUS_SHUTDOWN) && 12536 !bnxt_fw_reset_timeout(bp)) { 12537 bnxt_queue_fw_reset_work(bp, HZ / 5); 12538 return; 12539 } 12540 12541 if (!bp->fw_health->primary) { 12542 u32 wait_dsecs = bp->fw_health->normal_func_wait_dsecs; 12543 12544 bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV; 12545 bnxt_queue_fw_reset_work(bp, wait_dsecs * HZ / 10); 12546 return; 12547 } 12548 bp->fw_reset_state = BNXT_FW_RESET_STATE_RESET_FW; 12549 } 12550 fallthrough; 12551 case BNXT_FW_RESET_STATE_RESET_FW: 12552 bnxt_reset_all(bp); 12553 bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV; 12554 bnxt_queue_fw_reset_work(bp, bp->fw_reset_min_dsecs * HZ / 10); 12555 return; 12556 case BNXT_FW_RESET_STATE_ENABLE_DEV: 12557 bnxt_inv_fw_health_reg(bp); 12558 if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state) && 12559 !bp->fw_reset_min_dsecs) { 12560 u16 val; 12561 12562 pci_read_config_word(bp->pdev, PCI_SUBSYSTEM_ID, &val); 12563 if (val == 0xffff) { 12564 if (bnxt_fw_reset_timeout(bp)) { 12565 netdev_err(bp->dev, "Firmware reset aborted, PCI config space invalid\n"); 12566 rc = -ETIMEDOUT; 12567 goto fw_reset_abort; 12568 } 12569 bnxt_queue_fw_reset_work(bp, HZ / 1000); 12570 return; 12571 } 12572 } 12573 clear_bit(BNXT_STATE_FW_FATAL_COND, &bp->state); 12574 clear_bit(BNXT_STATE_FW_NON_FATAL_COND, &bp->state); 12575 if (test_and_clear_bit(BNXT_STATE_FW_ACTIVATE_RESET, &bp->state) && 12576 !test_bit(BNXT_STATE_FW_ACTIVATE, &bp->state)) 12577 bnxt_dl_remote_reload(bp); 12578 if (pci_enable_device(bp->pdev)) { 12579 netdev_err(bp->dev, "Cannot re-enable PCI device\n"); 12580 rc = -ENODEV; 12581 goto fw_reset_abort; 12582 } 12583 pci_set_master(bp->pdev); 12584 bp->fw_reset_state = BNXT_FW_RESET_STATE_POLL_FW; 12585 fallthrough; 12586 case BNXT_FW_RESET_STATE_POLL_FW: 12587 bp->hwrm_cmd_timeout = SHORT_HWRM_CMD_TIMEOUT; 12588 rc = bnxt_hwrm_poll(bp); 12589 if (rc) { 12590 if (bnxt_fw_reset_timeout(bp)) { 12591 netdev_err(bp->dev, "Firmware reset aborted\n"); 12592 goto fw_reset_abort_status; 12593 } 12594 bnxt_queue_fw_reset_work(bp, HZ / 5); 12595 return; 12596 } 12597 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT; 12598 bp->fw_reset_state = BNXT_FW_RESET_STATE_OPENING; 12599 fallthrough; 12600 case BNXT_FW_RESET_STATE_OPENING: 12601 while (!rtnl_trylock()) { 12602 bnxt_queue_fw_reset_work(bp, HZ / 10); 12603 return; 12604 } 12605 rc = bnxt_open(bp->dev); 12606 if (rc) { 12607 netdev_err(bp->dev, "bnxt_open() failed during FW reset\n"); 12608 bnxt_fw_reset_abort(bp, rc); 12609 rtnl_unlock(); 12610 return; 12611 } 12612 12613 if ((bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY) && 12614 bp->fw_health->enabled) { 12615 bp->fw_health->last_fw_reset_cnt = 12616 bnxt_fw_health_readl(bp, BNXT_FW_RESET_CNT_REG); 12617 } 12618 bp->fw_reset_state = 0; 12619 /* Make sure fw_reset_state is 0 before clearing the flag */ 12620 smp_mb__before_atomic(); 12621 clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state); 12622 bnxt_ulp_start(bp, 0); 12623 bnxt_reenable_sriov(bp); 12624 bnxt_vf_reps_alloc(bp); 12625 bnxt_vf_reps_open(bp); 12626 bnxt_ptp_reapply_pps(bp); 12627 clear_bit(BNXT_STATE_FW_ACTIVATE, &bp->state); 12628 if (test_and_clear_bit(BNXT_STATE_RECOVER, &bp->state)) { 12629 bnxt_dl_health_fw_recovery_done(bp); 12630 bnxt_dl_health_fw_status_update(bp, true); 12631 } 12632 rtnl_unlock(); 12633 break; 12634 } 12635 return; 12636 12637 fw_reset_abort_status: 12638 if (bp->fw_health->status_reliable || 12639 (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)) { 12640 u32 sts = bnxt_fw_health_readl(bp, BNXT_FW_HEALTH_REG); 12641 12642 netdev_err(bp->dev, "fw_health_status 0x%x\n", sts); 12643 } 12644 fw_reset_abort: 12645 rtnl_lock(); 12646 bnxt_fw_reset_abort(bp, rc); 12647 rtnl_unlock(); 12648 } 12649 12650 static int bnxt_init_board(struct pci_dev *pdev, struct net_device *dev) 12651 { 12652 int rc; 12653 struct bnxt *bp = netdev_priv(dev); 12654 12655 SET_NETDEV_DEV(dev, &pdev->dev); 12656 12657 /* enable device (incl. PCI PM wakeup), and bus-mastering */ 12658 rc = pci_enable_device(pdev); 12659 if (rc) { 12660 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n"); 12661 goto init_err; 12662 } 12663 12664 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 12665 dev_err(&pdev->dev, 12666 "Cannot find PCI device base address, aborting\n"); 12667 rc = -ENODEV; 12668 goto init_err_disable; 12669 } 12670 12671 rc = pci_request_regions(pdev, DRV_MODULE_NAME); 12672 if (rc) { 12673 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n"); 12674 goto init_err_disable; 12675 } 12676 12677 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) != 0 && 12678 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)) != 0) { 12679 dev_err(&pdev->dev, "System does not support DMA, aborting\n"); 12680 rc = -EIO; 12681 goto init_err_release; 12682 } 12683 12684 pci_set_master(pdev); 12685 12686 bp->dev = dev; 12687 bp->pdev = pdev; 12688 12689 /* Doorbell BAR bp->bar1 is mapped after bnxt_fw_init_one_p2() 12690 * determines the BAR size. 12691 */ 12692 bp->bar0 = pci_ioremap_bar(pdev, 0); 12693 if (!bp->bar0) { 12694 dev_err(&pdev->dev, "Cannot map device registers, aborting\n"); 12695 rc = -ENOMEM; 12696 goto init_err_release; 12697 } 12698 12699 bp->bar2 = pci_ioremap_bar(pdev, 4); 12700 if (!bp->bar2) { 12701 dev_err(&pdev->dev, "Cannot map bar4 registers, aborting\n"); 12702 rc = -ENOMEM; 12703 goto init_err_release; 12704 } 12705 12706 INIT_WORK(&bp->sp_task, bnxt_sp_task); 12707 INIT_DELAYED_WORK(&bp->fw_reset_task, bnxt_fw_reset_task); 12708 12709 spin_lock_init(&bp->ntp_fltr_lock); 12710 #if BITS_PER_LONG == 32 12711 spin_lock_init(&bp->db_lock); 12712 #endif 12713 12714 bp->rx_ring_size = BNXT_DEFAULT_RX_RING_SIZE; 12715 bp->tx_ring_size = BNXT_DEFAULT_TX_RING_SIZE; 12716 12717 timer_setup(&bp->timer, bnxt_timer, 0); 12718 bp->current_interval = BNXT_TIMER_INTERVAL; 12719 12720 bp->vxlan_fw_dst_port_id = INVALID_HW_RING_ID; 12721 bp->nge_fw_dst_port_id = INVALID_HW_RING_ID; 12722 12723 clear_bit(BNXT_STATE_OPEN, &bp->state); 12724 return 0; 12725 12726 init_err_release: 12727 bnxt_unmap_bars(bp, pdev); 12728 pci_release_regions(pdev); 12729 12730 init_err_disable: 12731 pci_disable_device(pdev); 12732 12733 init_err: 12734 return rc; 12735 } 12736 12737 /* rtnl_lock held */ 12738 static int bnxt_change_mac_addr(struct net_device *dev, void *p) 12739 { 12740 struct sockaddr *addr = p; 12741 struct bnxt *bp = netdev_priv(dev); 12742 int rc = 0; 12743 12744 if (!is_valid_ether_addr(addr->sa_data)) 12745 return -EADDRNOTAVAIL; 12746 12747 if (ether_addr_equal(addr->sa_data, dev->dev_addr)) 12748 return 0; 12749 12750 rc = bnxt_approve_mac(bp, addr->sa_data, true); 12751 if (rc) 12752 return rc; 12753 12754 eth_hw_addr_set(dev, addr->sa_data); 12755 if (netif_running(dev)) { 12756 bnxt_close_nic(bp, false, false); 12757 rc = bnxt_open_nic(bp, false, false); 12758 } 12759 12760 return rc; 12761 } 12762 12763 /* rtnl_lock held */ 12764 static int bnxt_change_mtu(struct net_device *dev, int new_mtu) 12765 { 12766 struct bnxt *bp = netdev_priv(dev); 12767 12768 if (netif_running(dev)) 12769 bnxt_close_nic(bp, true, false); 12770 12771 dev->mtu = new_mtu; 12772 bnxt_set_ring_params(bp); 12773 12774 if (netif_running(dev)) 12775 return bnxt_open_nic(bp, true, false); 12776 12777 return 0; 12778 } 12779 12780 int bnxt_setup_mq_tc(struct net_device *dev, u8 tc) 12781 { 12782 struct bnxt *bp = netdev_priv(dev); 12783 bool sh = false; 12784 int rc; 12785 12786 if (tc > bp->max_tc) { 12787 netdev_err(dev, "Too many traffic classes requested: %d. Max supported is %d.\n", 12788 tc, bp->max_tc); 12789 return -EINVAL; 12790 } 12791 12792 if (netdev_get_num_tc(dev) == tc) 12793 return 0; 12794 12795 if (bp->flags & BNXT_FLAG_SHARED_RINGS) 12796 sh = true; 12797 12798 rc = bnxt_check_rings(bp, bp->tx_nr_rings_per_tc, bp->rx_nr_rings, 12799 sh, tc, bp->tx_nr_rings_xdp); 12800 if (rc) 12801 return rc; 12802 12803 /* Needs to close the device and do hw resource re-allocations */ 12804 if (netif_running(bp->dev)) 12805 bnxt_close_nic(bp, true, false); 12806 12807 if (tc) { 12808 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tc; 12809 netdev_set_num_tc(dev, tc); 12810 } else { 12811 bp->tx_nr_rings = bp->tx_nr_rings_per_tc; 12812 netdev_reset_tc(dev); 12813 } 12814 bp->tx_nr_rings += bp->tx_nr_rings_xdp; 12815 bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) : 12816 bp->tx_nr_rings + bp->rx_nr_rings; 12817 12818 if (netif_running(bp->dev)) 12819 return bnxt_open_nic(bp, true, false); 12820 12821 return 0; 12822 } 12823 12824 static int bnxt_setup_tc_block_cb(enum tc_setup_type type, void *type_data, 12825 void *cb_priv) 12826 { 12827 struct bnxt *bp = cb_priv; 12828 12829 if (!bnxt_tc_flower_enabled(bp) || 12830 !tc_cls_can_offload_and_chain0(bp->dev, type_data)) 12831 return -EOPNOTSUPP; 12832 12833 switch (type) { 12834 case TC_SETUP_CLSFLOWER: 12835 return bnxt_tc_setup_flower(bp, bp->pf.fw_fid, type_data); 12836 default: 12837 return -EOPNOTSUPP; 12838 } 12839 } 12840 12841 LIST_HEAD(bnxt_block_cb_list); 12842 12843 static int bnxt_setup_tc(struct net_device *dev, enum tc_setup_type type, 12844 void *type_data) 12845 { 12846 struct bnxt *bp = netdev_priv(dev); 12847 12848 switch (type) { 12849 case TC_SETUP_BLOCK: 12850 return flow_block_cb_setup_simple(type_data, 12851 &bnxt_block_cb_list, 12852 bnxt_setup_tc_block_cb, 12853 bp, bp, true); 12854 case TC_SETUP_QDISC_MQPRIO: { 12855 struct tc_mqprio_qopt *mqprio = type_data; 12856 12857 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS; 12858 12859 return bnxt_setup_mq_tc(dev, mqprio->num_tc); 12860 } 12861 default: 12862 return -EOPNOTSUPP; 12863 } 12864 } 12865 12866 #ifdef CONFIG_RFS_ACCEL 12867 static bool bnxt_fltr_match(struct bnxt_ntuple_filter *f1, 12868 struct bnxt_ntuple_filter *f2) 12869 { 12870 struct flow_keys *keys1 = &f1->fkeys; 12871 struct flow_keys *keys2 = &f2->fkeys; 12872 12873 if (keys1->basic.n_proto != keys2->basic.n_proto || 12874 keys1->basic.ip_proto != keys2->basic.ip_proto) 12875 return false; 12876 12877 if (keys1->basic.n_proto == htons(ETH_P_IP)) { 12878 if (keys1->addrs.v4addrs.src != keys2->addrs.v4addrs.src || 12879 keys1->addrs.v4addrs.dst != keys2->addrs.v4addrs.dst) 12880 return false; 12881 } else { 12882 if (memcmp(&keys1->addrs.v6addrs.src, &keys2->addrs.v6addrs.src, 12883 sizeof(keys1->addrs.v6addrs.src)) || 12884 memcmp(&keys1->addrs.v6addrs.dst, &keys2->addrs.v6addrs.dst, 12885 sizeof(keys1->addrs.v6addrs.dst))) 12886 return false; 12887 } 12888 12889 if (keys1->ports.ports == keys2->ports.ports && 12890 keys1->control.flags == keys2->control.flags && 12891 ether_addr_equal(f1->src_mac_addr, f2->src_mac_addr) && 12892 ether_addr_equal(f1->dst_mac_addr, f2->dst_mac_addr)) 12893 return true; 12894 12895 return false; 12896 } 12897 12898 static int bnxt_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb, 12899 u16 rxq_index, u32 flow_id) 12900 { 12901 struct bnxt *bp = netdev_priv(dev); 12902 struct bnxt_ntuple_filter *fltr, *new_fltr; 12903 struct flow_keys *fkeys; 12904 struct ethhdr *eth = (struct ethhdr *)skb_mac_header(skb); 12905 int rc = 0, idx, bit_id, l2_idx = 0; 12906 struct hlist_head *head; 12907 u32 flags; 12908 12909 if (!ether_addr_equal(dev->dev_addr, eth->h_dest)) { 12910 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 12911 int off = 0, j; 12912 12913 netif_addr_lock_bh(dev); 12914 for (j = 0; j < vnic->uc_filter_count; j++, off += ETH_ALEN) { 12915 if (ether_addr_equal(eth->h_dest, 12916 vnic->uc_list + off)) { 12917 l2_idx = j + 1; 12918 break; 12919 } 12920 } 12921 netif_addr_unlock_bh(dev); 12922 if (!l2_idx) 12923 return -EINVAL; 12924 } 12925 new_fltr = kzalloc(sizeof(*new_fltr), GFP_ATOMIC); 12926 if (!new_fltr) 12927 return -ENOMEM; 12928 12929 fkeys = &new_fltr->fkeys; 12930 if (!skb_flow_dissect_flow_keys(skb, fkeys, 0)) { 12931 rc = -EPROTONOSUPPORT; 12932 goto err_free; 12933 } 12934 12935 if ((fkeys->basic.n_proto != htons(ETH_P_IP) && 12936 fkeys->basic.n_proto != htons(ETH_P_IPV6)) || 12937 ((fkeys->basic.ip_proto != IPPROTO_TCP) && 12938 (fkeys->basic.ip_proto != IPPROTO_UDP))) { 12939 rc = -EPROTONOSUPPORT; 12940 goto err_free; 12941 } 12942 if (fkeys->basic.n_proto == htons(ETH_P_IPV6) && 12943 bp->hwrm_spec_code < 0x10601) { 12944 rc = -EPROTONOSUPPORT; 12945 goto err_free; 12946 } 12947 flags = fkeys->control.flags; 12948 if (((flags & FLOW_DIS_ENCAPSULATION) && 12949 bp->hwrm_spec_code < 0x10601) || (flags & FLOW_DIS_IS_FRAGMENT)) { 12950 rc = -EPROTONOSUPPORT; 12951 goto err_free; 12952 } 12953 12954 memcpy(new_fltr->dst_mac_addr, eth->h_dest, ETH_ALEN); 12955 memcpy(new_fltr->src_mac_addr, eth->h_source, ETH_ALEN); 12956 12957 idx = skb_get_hash_raw(skb) & BNXT_NTP_FLTR_HASH_MASK; 12958 head = &bp->ntp_fltr_hash_tbl[idx]; 12959 rcu_read_lock(); 12960 hlist_for_each_entry_rcu(fltr, head, hash) { 12961 if (bnxt_fltr_match(fltr, new_fltr)) { 12962 rc = fltr->sw_id; 12963 rcu_read_unlock(); 12964 goto err_free; 12965 } 12966 } 12967 rcu_read_unlock(); 12968 12969 spin_lock_bh(&bp->ntp_fltr_lock); 12970 bit_id = bitmap_find_free_region(bp->ntp_fltr_bmap, 12971 BNXT_NTP_FLTR_MAX_FLTR, 0); 12972 if (bit_id < 0) { 12973 spin_unlock_bh(&bp->ntp_fltr_lock); 12974 rc = -ENOMEM; 12975 goto err_free; 12976 } 12977 12978 new_fltr->sw_id = (u16)bit_id; 12979 new_fltr->flow_id = flow_id; 12980 new_fltr->l2_fltr_idx = l2_idx; 12981 new_fltr->rxq = rxq_index; 12982 hlist_add_head_rcu(&new_fltr->hash, head); 12983 bp->ntp_fltr_count++; 12984 spin_unlock_bh(&bp->ntp_fltr_lock); 12985 12986 bnxt_queue_sp_work(bp, BNXT_RX_NTP_FLTR_SP_EVENT); 12987 12988 return new_fltr->sw_id; 12989 12990 err_free: 12991 kfree(new_fltr); 12992 return rc; 12993 } 12994 12995 static void bnxt_cfg_ntp_filters(struct bnxt *bp) 12996 { 12997 int i; 12998 12999 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) { 13000 struct hlist_head *head; 13001 struct hlist_node *tmp; 13002 struct bnxt_ntuple_filter *fltr; 13003 int rc; 13004 13005 head = &bp->ntp_fltr_hash_tbl[i]; 13006 hlist_for_each_entry_safe(fltr, tmp, head, hash) { 13007 bool del = false; 13008 13009 if (test_bit(BNXT_FLTR_VALID, &fltr->state)) { 13010 if (rps_may_expire_flow(bp->dev, fltr->rxq, 13011 fltr->flow_id, 13012 fltr->sw_id)) { 13013 bnxt_hwrm_cfa_ntuple_filter_free(bp, 13014 fltr); 13015 del = true; 13016 } 13017 } else { 13018 rc = bnxt_hwrm_cfa_ntuple_filter_alloc(bp, 13019 fltr); 13020 if (rc) 13021 del = true; 13022 else 13023 set_bit(BNXT_FLTR_VALID, &fltr->state); 13024 } 13025 13026 if (del) { 13027 spin_lock_bh(&bp->ntp_fltr_lock); 13028 hlist_del_rcu(&fltr->hash); 13029 bp->ntp_fltr_count--; 13030 spin_unlock_bh(&bp->ntp_fltr_lock); 13031 synchronize_rcu(); 13032 clear_bit(fltr->sw_id, bp->ntp_fltr_bmap); 13033 kfree(fltr); 13034 } 13035 } 13036 } 13037 if (test_and_clear_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event)) 13038 netdev_info(bp->dev, "Receive PF driver unload event!\n"); 13039 } 13040 13041 #else 13042 13043 static void bnxt_cfg_ntp_filters(struct bnxt *bp) 13044 { 13045 } 13046 13047 #endif /* CONFIG_RFS_ACCEL */ 13048 13049 static int bnxt_udp_tunnel_set_port(struct net_device *netdev, unsigned int table, 13050 unsigned int entry, struct udp_tunnel_info *ti) 13051 { 13052 struct bnxt *bp = netdev_priv(netdev); 13053 unsigned int cmd; 13054 13055 if (ti->type == UDP_TUNNEL_TYPE_VXLAN) 13056 cmd = TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN; 13057 else 13058 cmd = TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE; 13059 13060 return bnxt_hwrm_tunnel_dst_port_alloc(bp, ti->port, cmd); 13061 } 13062 13063 static int bnxt_udp_tunnel_unset_port(struct net_device *netdev, unsigned int table, 13064 unsigned int entry, struct udp_tunnel_info *ti) 13065 { 13066 struct bnxt *bp = netdev_priv(netdev); 13067 unsigned int cmd; 13068 13069 if (ti->type == UDP_TUNNEL_TYPE_VXLAN) 13070 cmd = TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN; 13071 else 13072 cmd = TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE; 13073 13074 return bnxt_hwrm_tunnel_dst_port_free(bp, cmd); 13075 } 13076 13077 static const struct udp_tunnel_nic_info bnxt_udp_tunnels = { 13078 .set_port = bnxt_udp_tunnel_set_port, 13079 .unset_port = bnxt_udp_tunnel_unset_port, 13080 .flags = UDP_TUNNEL_NIC_INFO_MAY_SLEEP | 13081 UDP_TUNNEL_NIC_INFO_OPEN_ONLY, 13082 .tables = { 13083 { .n_entries = 1, .tunnel_types = UDP_TUNNEL_TYPE_VXLAN, }, 13084 { .n_entries = 1, .tunnel_types = UDP_TUNNEL_TYPE_GENEVE, }, 13085 }, 13086 }; 13087 13088 static int bnxt_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq, 13089 struct net_device *dev, u32 filter_mask, 13090 int nlflags) 13091 { 13092 struct bnxt *bp = netdev_priv(dev); 13093 13094 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, bp->br_mode, 0, 0, 13095 nlflags, filter_mask, NULL); 13096 } 13097 13098 static int bnxt_bridge_setlink(struct net_device *dev, struct nlmsghdr *nlh, 13099 u16 flags, struct netlink_ext_ack *extack) 13100 { 13101 struct bnxt *bp = netdev_priv(dev); 13102 struct nlattr *attr, *br_spec; 13103 int rem, rc = 0; 13104 13105 if (bp->hwrm_spec_code < 0x10708 || !BNXT_SINGLE_PF(bp)) 13106 return -EOPNOTSUPP; 13107 13108 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC); 13109 if (!br_spec) 13110 return -EINVAL; 13111 13112 nla_for_each_nested(attr, br_spec, rem) { 13113 u16 mode; 13114 13115 if (nla_type(attr) != IFLA_BRIDGE_MODE) 13116 continue; 13117 13118 if (nla_len(attr) < sizeof(mode)) 13119 return -EINVAL; 13120 13121 mode = nla_get_u16(attr); 13122 if (mode == bp->br_mode) 13123 break; 13124 13125 rc = bnxt_hwrm_set_br_mode(bp, mode); 13126 if (!rc) 13127 bp->br_mode = mode; 13128 break; 13129 } 13130 return rc; 13131 } 13132 13133 int bnxt_get_port_parent_id(struct net_device *dev, 13134 struct netdev_phys_item_id *ppid) 13135 { 13136 struct bnxt *bp = netdev_priv(dev); 13137 13138 if (bp->eswitch_mode != DEVLINK_ESWITCH_MODE_SWITCHDEV) 13139 return -EOPNOTSUPP; 13140 13141 /* The PF and it's VF-reps only support the switchdev framework */ 13142 if (!BNXT_PF(bp) || !(bp->flags & BNXT_FLAG_DSN_VALID)) 13143 return -EOPNOTSUPP; 13144 13145 ppid->id_len = sizeof(bp->dsn); 13146 memcpy(ppid->id, bp->dsn, ppid->id_len); 13147 13148 return 0; 13149 } 13150 13151 static const struct net_device_ops bnxt_netdev_ops = { 13152 .ndo_open = bnxt_open, 13153 .ndo_start_xmit = bnxt_start_xmit, 13154 .ndo_stop = bnxt_close, 13155 .ndo_get_stats64 = bnxt_get_stats64, 13156 .ndo_set_rx_mode = bnxt_set_rx_mode, 13157 .ndo_eth_ioctl = bnxt_ioctl, 13158 .ndo_validate_addr = eth_validate_addr, 13159 .ndo_set_mac_address = bnxt_change_mac_addr, 13160 .ndo_change_mtu = bnxt_change_mtu, 13161 .ndo_fix_features = bnxt_fix_features, 13162 .ndo_set_features = bnxt_set_features, 13163 .ndo_features_check = bnxt_features_check, 13164 .ndo_tx_timeout = bnxt_tx_timeout, 13165 #ifdef CONFIG_BNXT_SRIOV 13166 .ndo_get_vf_config = bnxt_get_vf_config, 13167 .ndo_set_vf_mac = bnxt_set_vf_mac, 13168 .ndo_set_vf_vlan = bnxt_set_vf_vlan, 13169 .ndo_set_vf_rate = bnxt_set_vf_bw, 13170 .ndo_set_vf_link_state = bnxt_set_vf_link_state, 13171 .ndo_set_vf_spoofchk = bnxt_set_vf_spoofchk, 13172 .ndo_set_vf_trust = bnxt_set_vf_trust, 13173 #endif 13174 .ndo_setup_tc = bnxt_setup_tc, 13175 #ifdef CONFIG_RFS_ACCEL 13176 .ndo_rx_flow_steer = bnxt_rx_flow_steer, 13177 #endif 13178 .ndo_bpf = bnxt_xdp, 13179 .ndo_xdp_xmit = bnxt_xdp_xmit, 13180 .ndo_bridge_getlink = bnxt_bridge_getlink, 13181 .ndo_bridge_setlink = bnxt_bridge_setlink, 13182 }; 13183 13184 static void bnxt_remove_one(struct pci_dev *pdev) 13185 { 13186 struct net_device *dev = pci_get_drvdata(pdev); 13187 struct bnxt *bp = netdev_priv(dev); 13188 13189 if (BNXT_PF(bp)) 13190 bnxt_sriov_disable(bp); 13191 13192 bnxt_rdma_aux_device_uninit(bp); 13193 13194 bnxt_ptp_clear(bp); 13195 unregister_netdev(dev); 13196 clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state); 13197 /* Flush any pending tasks */ 13198 cancel_work_sync(&bp->sp_task); 13199 cancel_delayed_work_sync(&bp->fw_reset_task); 13200 bp->sp_event = 0; 13201 13202 bnxt_dl_fw_reporters_destroy(bp); 13203 bnxt_dl_unregister(bp); 13204 bnxt_shutdown_tc(bp); 13205 13206 bnxt_clear_int_mode(bp); 13207 bnxt_hwrm_func_drv_unrgtr(bp); 13208 bnxt_free_hwrm_resources(bp); 13209 bnxt_ethtool_free(bp); 13210 bnxt_dcb_free(bp); 13211 kfree(bp->ptp_cfg); 13212 bp->ptp_cfg = NULL; 13213 kfree(bp->fw_health); 13214 bp->fw_health = NULL; 13215 bnxt_cleanup_pci(bp); 13216 bnxt_free_ctx_mem(bp); 13217 kfree(bp->ctx); 13218 bp->ctx = NULL; 13219 kfree(bp->rss_indir_tbl); 13220 bp->rss_indir_tbl = NULL; 13221 bnxt_free_port_stats(bp); 13222 free_netdev(dev); 13223 } 13224 13225 static int bnxt_probe_phy(struct bnxt *bp, bool fw_dflt) 13226 { 13227 int rc = 0; 13228 struct bnxt_link_info *link_info = &bp->link_info; 13229 13230 bp->phy_flags = 0; 13231 rc = bnxt_hwrm_phy_qcaps(bp); 13232 if (rc) { 13233 netdev_err(bp->dev, "Probe phy can't get phy capabilities (rc: %x)\n", 13234 rc); 13235 return rc; 13236 } 13237 if (bp->phy_flags & BNXT_PHY_FL_NO_FCS) 13238 bp->dev->priv_flags |= IFF_SUPP_NOFCS; 13239 else 13240 bp->dev->priv_flags &= ~IFF_SUPP_NOFCS; 13241 if (!fw_dflt) 13242 return 0; 13243 13244 mutex_lock(&bp->link_lock); 13245 rc = bnxt_update_link(bp, false); 13246 if (rc) { 13247 mutex_unlock(&bp->link_lock); 13248 netdev_err(bp->dev, "Probe phy can't update link (rc: %x)\n", 13249 rc); 13250 return rc; 13251 } 13252 13253 /* Older firmware does not have supported_auto_speeds, so assume 13254 * that all supported speeds can be autonegotiated. 13255 */ 13256 if (link_info->auto_link_speeds && !link_info->support_auto_speeds) 13257 link_info->support_auto_speeds = link_info->support_speeds; 13258 13259 bnxt_init_ethtool_link_settings(bp); 13260 mutex_unlock(&bp->link_lock); 13261 return 0; 13262 } 13263 13264 static int bnxt_get_max_irq(struct pci_dev *pdev) 13265 { 13266 u16 ctrl; 13267 13268 if (!pdev->msix_cap) 13269 return 1; 13270 13271 pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &ctrl); 13272 return (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1; 13273 } 13274 13275 static void _bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx, 13276 int *max_cp) 13277 { 13278 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 13279 int max_ring_grps = 0, max_irq; 13280 13281 *max_tx = hw_resc->max_tx_rings; 13282 *max_rx = hw_resc->max_rx_rings; 13283 *max_cp = bnxt_get_max_func_cp_rings_for_en(bp); 13284 max_irq = min_t(int, bnxt_get_max_func_irqs(bp) - 13285 bnxt_get_ulp_msix_num(bp), 13286 hw_resc->max_stat_ctxs - bnxt_get_ulp_stat_ctxs(bp)); 13287 if (!(bp->flags & BNXT_FLAG_CHIP_P5)) 13288 *max_cp = min_t(int, *max_cp, max_irq); 13289 max_ring_grps = hw_resc->max_hw_ring_grps; 13290 if (BNXT_CHIP_TYPE_NITRO_A0(bp) && BNXT_PF(bp)) { 13291 *max_cp -= 1; 13292 *max_rx -= 2; 13293 } 13294 if (bp->flags & BNXT_FLAG_AGG_RINGS) 13295 *max_rx >>= 1; 13296 if (bp->flags & BNXT_FLAG_CHIP_P5) { 13297 bnxt_trim_rings(bp, max_rx, max_tx, *max_cp, false); 13298 /* On P5 chips, max_cp output param should be available NQs */ 13299 *max_cp = max_irq; 13300 } 13301 *max_rx = min_t(int, *max_rx, max_ring_grps); 13302 } 13303 13304 int bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx, bool shared) 13305 { 13306 int rx, tx, cp; 13307 13308 _bnxt_get_max_rings(bp, &rx, &tx, &cp); 13309 *max_rx = rx; 13310 *max_tx = tx; 13311 if (!rx || !tx || !cp) 13312 return -ENOMEM; 13313 13314 return bnxt_trim_rings(bp, max_rx, max_tx, cp, shared); 13315 } 13316 13317 static int bnxt_get_dflt_rings(struct bnxt *bp, int *max_rx, int *max_tx, 13318 bool shared) 13319 { 13320 int rc; 13321 13322 rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared); 13323 if (rc && (bp->flags & BNXT_FLAG_AGG_RINGS)) { 13324 /* Not enough rings, try disabling agg rings. */ 13325 bp->flags &= ~BNXT_FLAG_AGG_RINGS; 13326 rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared); 13327 if (rc) { 13328 /* set BNXT_FLAG_AGG_RINGS back for consistency */ 13329 bp->flags |= BNXT_FLAG_AGG_RINGS; 13330 return rc; 13331 } 13332 bp->flags |= BNXT_FLAG_NO_AGG_RINGS; 13333 bp->dev->hw_features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW); 13334 bp->dev->features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW); 13335 bnxt_set_ring_params(bp); 13336 } 13337 13338 if (bp->flags & BNXT_FLAG_ROCE_CAP) { 13339 int max_cp, max_stat, max_irq; 13340 13341 /* Reserve minimum resources for RoCE */ 13342 max_cp = bnxt_get_max_func_cp_rings(bp); 13343 max_stat = bnxt_get_max_func_stat_ctxs(bp); 13344 max_irq = bnxt_get_max_func_irqs(bp); 13345 if (max_cp <= BNXT_MIN_ROCE_CP_RINGS || 13346 max_irq <= BNXT_MIN_ROCE_CP_RINGS || 13347 max_stat <= BNXT_MIN_ROCE_STAT_CTXS) 13348 return 0; 13349 13350 max_cp -= BNXT_MIN_ROCE_CP_RINGS; 13351 max_irq -= BNXT_MIN_ROCE_CP_RINGS; 13352 max_stat -= BNXT_MIN_ROCE_STAT_CTXS; 13353 max_cp = min_t(int, max_cp, max_irq); 13354 max_cp = min_t(int, max_cp, max_stat); 13355 rc = bnxt_trim_rings(bp, max_rx, max_tx, max_cp, shared); 13356 if (rc) 13357 rc = 0; 13358 } 13359 return rc; 13360 } 13361 13362 /* In initial default shared ring setting, each shared ring must have a 13363 * RX/TX ring pair. 13364 */ 13365 static void bnxt_trim_dflt_sh_rings(struct bnxt *bp) 13366 { 13367 bp->cp_nr_rings = min_t(int, bp->tx_nr_rings_per_tc, bp->rx_nr_rings); 13368 bp->rx_nr_rings = bp->cp_nr_rings; 13369 bp->tx_nr_rings_per_tc = bp->cp_nr_rings; 13370 bp->tx_nr_rings = bp->tx_nr_rings_per_tc; 13371 } 13372 13373 static int bnxt_set_dflt_rings(struct bnxt *bp, bool sh) 13374 { 13375 int dflt_rings, max_rx_rings, max_tx_rings, rc; 13376 13377 if (!bnxt_can_reserve_rings(bp)) 13378 return 0; 13379 13380 if (sh) 13381 bp->flags |= BNXT_FLAG_SHARED_RINGS; 13382 dflt_rings = is_kdump_kernel() ? 1 : netif_get_num_default_rss_queues(); 13383 /* Reduce default rings on multi-port cards so that total default 13384 * rings do not exceed CPU count. 13385 */ 13386 if (bp->port_count > 1) { 13387 int max_rings = 13388 max_t(int, num_online_cpus() / bp->port_count, 1); 13389 13390 dflt_rings = min_t(int, dflt_rings, max_rings); 13391 } 13392 rc = bnxt_get_dflt_rings(bp, &max_rx_rings, &max_tx_rings, sh); 13393 if (rc) 13394 return rc; 13395 bp->rx_nr_rings = min_t(int, dflt_rings, max_rx_rings); 13396 bp->tx_nr_rings_per_tc = min_t(int, dflt_rings, max_tx_rings); 13397 if (sh) 13398 bnxt_trim_dflt_sh_rings(bp); 13399 else 13400 bp->cp_nr_rings = bp->tx_nr_rings_per_tc + bp->rx_nr_rings; 13401 bp->tx_nr_rings = bp->tx_nr_rings_per_tc; 13402 13403 rc = __bnxt_reserve_rings(bp); 13404 if (rc && rc != -ENODEV) 13405 netdev_warn(bp->dev, "Unable to reserve tx rings\n"); 13406 bp->tx_nr_rings_per_tc = bp->tx_nr_rings; 13407 if (sh) 13408 bnxt_trim_dflt_sh_rings(bp); 13409 13410 /* Rings may have been trimmed, re-reserve the trimmed rings. */ 13411 if (bnxt_need_reserve_rings(bp)) { 13412 rc = __bnxt_reserve_rings(bp); 13413 if (rc && rc != -ENODEV) 13414 netdev_warn(bp->dev, "2nd rings reservation failed.\n"); 13415 bp->tx_nr_rings_per_tc = bp->tx_nr_rings; 13416 } 13417 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) { 13418 bp->rx_nr_rings++; 13419 bp->cp_nr_rings++; 13420 } 13421 if (rc) { 13422 bp->tx_nr_rings = 0; 13423 bp->rx_nr_rings = 0; 13424 } 13425 return rc; 13426 } 13427 13428 static int bnxt_init_dflt_ring_mode(struct bnxt *bp) 13429 { 13430 int rc; 13431 13432 if (bp->tx_nr_rings) 13433 return 0; 13434 13435 bnxt_ulp_irq_stop(bp); 13436 bnxt_clear_int_mode(bp); 13437 rc = bnxt_set_dflt_rings(bp, true); 13438 if (rc) { 13439 if (BNXT_VF(bp) && rc == -ENODEV) 13440 netdev_err(bp->dev, "Cannot configure VF rings while PF is unavailable.\n"); 13441 else 13442 netdev_err(bp->dev, "Not enough rings available.\n"); 13443 goto init_dflt_ring_err; 13444 } 13445 rc = bnxt_init_int_mode(bp); 13446 if (rc) 13447 goto init_dflt_ring_err; 13448 13449 bp->tx_nr_rings_per_tc = bp->tx_nr_rings; 13450 13451 bnxt_set_dflt_rfs(bp); 13452 13453 init_dflt_ring_err: 13454 bnxt_ulp_irq_restart(bp, rc); 13455 return rc; 13456 } 13457 13458 int bnxt_restore_pf_fw_resources(struct bnxt *bp) 13459 { 13460 int rc; 13461 13462 ASSERT_RTNL(); 13463 bnxt_hwrm_func_qcaps(bp); 13464 13465 if (netif_running(bp->dev)) 13466 __bnxt_close_nic(bp, true, false); 13467 13468 bnxt_ulp_irq_stop(bp); 13469 bnxt_clear_int_mode(bp); 13470 rc = bnxt_init_int_mode(bp); 13471 bnxt_ulp_irq_restart(bp, rc); 13472 13473 if (netif_running(bp->dev)) { 13474 if (rc) 13475 dev_close(bp->dev); 13476 else 13477 rc = bnxt_open_nic(bp, true, false); 13478 } 13479 13480 return rc; 13481 } 13482 13483 static int bnxt_init_mac_addr(struct bnxt *bp) 13484 { 13485 int rc = 0; 13486 13487 if (BNXT_PF(bp)) { 13488 eth_hw_addr_set(bp->dev, bp->pf.mac_addr); 13489 } else { 13490 #ifdef CONFIG_BNXT_SRIOV 13491 struct bnxt_vf_info *vf = &bp->vf; 13492 bool strict_approval = true; 13493 13494 if (is_valid_ether_addr(vf->mac_addr)) { 13495 /* overwrite netdev dev_addr with admin VF MAC */ 13496 eth_hw_addr_set(bp->dev, vf->mac_addr); 13497 /* Older PF driver or firmware may not approve this 13498 * correctly. 13499 */ 13500 strict_approval = false; 13501 } else { 13502 eth_hw_addr_random(bp->dev); 13503 } 13504 rc = bnxt_approve_mac(bp, bp->dev->dev_addr, strict_approval); 13505 #endif 13506 } 13507 return rc; 13508 } 13509 13510 static void bnxt_vpd_read_info(struct bnxt *bp) 13511 { 13512 struct pci_dev *pdev = bp->pdev; 13513 unsigned int vpd_size, kw_len; 13514 int pos, size; 13515 u8 *vpd_data; 13516 13517 vpd_data = pci_vpd_alloc(pdev, &vpd_size); 13518 if (IS_ERR(vpd_data)) { 13519 pci_warn(pdev, "Unable to read VPD\n"); 13520 return; 13521 } 13522 13523 pos = pci_vpd_find_ro_info_keyword(vpd_data, vpd_size, 13524 PCI_VPD_RO_KEYWORD_PARTNO, &kw_len); 13525 if (pos < 0) 13526 goto read_sn; 13527 13528 size = min_t(int, kw_len, BNXT_VPD_FLD_LEN - 1); 13529 memcpy(bp->board_partno, &vpd_data[pos], size); 13530 13531 read_sn: 13532 pos = pci_vpd_find_ro_info_keyword(vpd_data, vpd_size, 13533 PCI_VPD_RO_KEYWORD_SERIALNO, 13534 &kw_len); 13535 if (pos < 0) 13536 goto exit; 13537 13538 size = min_t(int, kw_len, BNXT_VPD_FLD_LEN - 1); 13539 memcpy(bp->board_serialno, &vpd_data[pos], size); 13540 exit: 13541 kfree(vpd_data); 13542 } 13543 13544 static int bnxt_pcie_dsn_get(struct bnxt *bp, u8 dsn[]) 13545 { 13546 struct pci_dev *pdev = bp->pdev; 13547 u64 qword; 13548 13549 qword = pci_get_dsn(pdev); 13550 if (!qword) { 13551 netdev_info(bp->dev, "Unable to read adapter's DSN\n"); 13552 return -EOPNOTSUPP; 13553 } 13554 13555 put_unaligned_le64(qword, dsn); 13556 13557 bp->flags |= BNXT_FLAG_DSN_VALID; 13558 return 0; 13559 } 13560 13561 static int bnxt_map_db_bar(struct bnxt *bp) 13562 { 13563 if (!bp->db_size) 13564 return -ENODEV; 13565 bp->bar1 = pci_iomap(bp->pdev, 2, bp->db_size); 13566 if (!bp->bar1) 13567 return -ENOMEM; 13568 return 0; 13569 } 13570 13571 void bnxt_print_device_info(struct bnxt *bp) 13572 { 13573 netdev_info(bp->dev, "%s found at mem %lx, node addr %pM\n", 13574 board_info[bp->board_idx].name, 13575 (long)pci_resource_start(bp->pdev, 0), bp->dev->dev_addr); 13576 13577 pcie_print_link_status(bp->pdev); 13578 } 13579 13580 static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 13581 { 13582 struct net_device *dev; 13583 struct bnxt *bp; 13584 int rc, max_irqs; 13585 13586 if (pci_is_bridge(pdev)) 13587 return -ENODEV; 13588 13589 /* Clear any pending DMA transactions from crash kernel 13590 * while loading driver in capture kernel. 13591 */ 13592 if (is_kdump_kernel()) { 13593 pci_clear_master(pdev); 13594 pcie_flr(pdev); 13595 } 13596 13597 max_irqs = bnxt_get_max_irq(pdev); 13598 dev = alloc_etherdev_mq(sizeof(*bp), max_irqs); 13599 if (!dev) 13600 return -ENOMEM; 13601 13602 bp = netdev_priv(dev); 13603 bp->board_idx = ent->driver_data; 13604 bp->msg_enable = BNXT_DEF_MSG_ENABLE; 13605 bnxt_set_max_func_irqs(bp, max_irqs); 13606 13607 if (bnxt_vf_pciid(bp->board_idx)) 13608 bp->flags |= BNXT_FLAG_VF; 13609 13610 /* No devlink port registration in case of a VF */ 13611 if (BNXT_PF(bp)) 13612 SET_NETDEV_DEVLINK_PORT(dev, &bp->dl_port); 13613 13614 if (pdev->msix_cap) 13615 bp->flags |= BNXT_FLAG_MSIX_CAP; 13616 13617 rc = bnxt_init_board(pdev, dev); 13618 if (rc < 0) 13619 goto init_err_free; 13620 13621 dev->netdev_ops = &bnxt_netdev_ops; 13622 dev->watchdog_timeo = BNXT_TX_TIMEOUT; 13623 dev->ethtool_ops = &bnxt_ethtool_ops; 13624 pci_set_drvdata(pdev, dev); 13625 13626 rc = bnxt_alloc_hwrm_resources(bp); 13627 if (rc) 13628 goto init_err_pci_clean; 13629 13630 mutex_init(&bp->hwrm_cmd_lock); 13631 mutex_init(&bp->link_lock); 13632 13633 rc = bnxt_fw_init_one_p1(bp); 13634 if (rc) 13635 goto init_err_pci_clean; 13636 13637 if (BNXT_PF(bp)) 13638 bnxt_vpd_read_info(bp); 13639 13640 if (BNXT_CHIP_P5(bp)) { 13641 bp->flags |= BNXT_FLAG_CHIP_P5; 13642 if (BNXT_CHIP_SR2(bp)) 13643 bp->flags |= BNXT_FLAG_CHIP_SR2; 13644 } 13645 13646 rc = bnxt_alloc_rss_indir_tbl(bp); 13647 if (rc) 13648 goto init_err_pci_clean; 13649 13650 rc = bnxt_fw_init_one_p2(bp); 13651 if (rc) 13652 goto init_err_pci_clean; 13653 13654 rc = bnxt_map_db_bar(bp); 13655 if (rc) { 13656 dev_err(&pdev->dev, "Cannot map doorbell BAR rc = %d, aborting\n", 13657 rc); 13658 goto init_err_pci_clean; 13659 } 13660 13661 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG | 13662 NETIF_F_TSO | NETIF_F_TSO6 | 13663 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE | 13664 NETIF_F_GSO_IPXIP4 | 13665 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM | 13666 NETIF_F_GSO_PARTIAL | NETIF_F_RXHASH | 13667 NETIF_F_RXCSUM | NETIF_F_GRO; 13668 13669 if (BNXT_SUPPORTS_TPA(bp)) 13670 dev->hw_features |= NETIF_F_LRO; 13671 13672 dev->hw_enc_features = 13673 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG | 13674 NETIF_F_TSO | NETIF_F_TSO6 | 13675 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE | 13676 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM | 13677 NETIF_F_GSO_IPXIP4 | NETIF_F_GSO_PARTIAL; 13678 dev->udp_tunnel_nic_info = &bnxt_udp_tunnels; 13679 13680 dev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM | 13681 NETIF_F_GSO_GRE_CSUM; 13682 dev->vlan_features = dev->hw_features | NETIF_F_HIGHDMA; 13683 if (bp->fw_cap & BNXT_FW_CAP_VLAN_RX_STRIP) 13684 dev->hw_features |= BNXT_HW_FEATURE_VLAN_ALL_RX; 13685 if (bp->fw_cap & BNXT_FW_CAP_VLAN_TX_INSERT) 13686 dev->hw_features |= BNXT_HW_FEATURE_VLAN_ALL_TX; 13687 if (BNXT_SUPPORTS_TPA(bp)) 13688 dev->hw_features |= NETIF_F_GRO_HW; 13689 dev->features |= dev->hw_features | NETIF_F_HIGHDMA; 13690 if (dev->features & NETIF_F_GRO_HW) 13691 dev->features &= ~NETIF_F_LRO; 13692 dev->priv_flags |= IFF_UNICAST_FLT; 13693 13694 netif_set_tso_max_size(dev, GSO_MAX_SIZE); 13695 13696 dev->xdp_features = NETDEV_XDP_ACT_BASIC | NETDEV_XDP_ACT_REDIRECT | 13697 NETDEV_XDP_ACT_RX_SG; 13698 13699 #ifdef CONFIG_BNXT_SRIOV 13700 init_waitqueue_head(&bp->sriov_cfg_wait); 13701 #endif 13702 if (BNXT_SUPPORTS_TPA(bp)) { 13703 bp->gro_func = bnxt_gro_func_5730x; 13704 if (BNXT_CHIP_P4(bp)) 13705 bp->gro_func = bnxt_gro_func_5731x; 13706 else if (BNXT_CHIP_P5(bp)) 13707 bp->gro_func = bnxt_gro_func_5750x; 13708 } 13709 if (!BNXT_CHIP_P4_PLUS(bp)) 13710 bp->flags |= BNXT_FLAG_DOUBLE_DB; 13711 13712 rc = bnxt_init_mac_addr(bp); 13713 if (rc) { 13714 dev_err(&pdev->dev, "Unable to initialize mac address.\n"); 13715 rc = -EADDRNOTAVAIL; 13716 goto init_err_pci_clean; 13717 } 13718 13719 if (BNXT_PF(bp)) { 13720 /* Read the adapter's DSN to use as the eswitch switch_id */ 13721 rc = bnxt_pcie_dsn_get(bp, bp->dsn); 13722 } 13723 13724 /* MTU range: 60 - FW defined max */ 13725 dev->min_mtu = ETH_ZLEN; 13726 dev->max_mtu = bp->max_mtu; 13727 13728 rc = bnxt_probe_phy(bp, true); 13729 if (rc) 13730 goto init_err_pci_clean; 13731 13732 bnxt_set_rx_skb_mode(bp, false); 13733 bnxt_set_tpa_flags(bp); 13734 bnxt_set_ring_params(bp); 13735 rc = bnxt_set_dflt_rings(bp, true); 13736 if (rc) { 13737 if (BNXT_VF(bp) && rc == -ENODEV) { 13738 netdev_err(bp->dev, "Cannot configure VF rings while PF is unavailable.\n"); 13739 } else { 13740 netdev_err(bp->dev, "Not enough rings available.\n"); 13741 rc = -ENOMEM; 13742 } 13743 goto init_err_pci_clean; 13744 } 13745 13746 bnxt_fw_init_one_p3(bp); 13747 13748 bnxt_init_dflt_coal(bp); 13749 13750 if (dev->hw_features & BNXT_HW_FEATURE_VLAN_ALL_RX) 13751 bp->flags |= BNXT_FLAG_STRIP_VLAN; 13752 13753 rc = bnxt_init_int_mode(bp); 13754 if (rc) 13755 goto init_err_pci_clean; 13756 13757 /* No TC has been set yet and rings may have been trimmed due to 13758 * limited MSIX, so we re-initialize the TX rings per TC. 13759 */ 13760 bp->tx_nr_rings_per_tc = bp->tx_nr_rings; 13761 13762 if (BNXT_PF(bp)) { 13763 if (!bnxt_pf_wq) { 13764 bnxt_pf_wq = 13765 create_singlethread_workqueue("bnxt_pf_wq"); 13766 if (!bnxt_pf_wq) { 13767 dev_err(&pdev->dev, "Unable to create workqueue.\n"); 13768 rc = -ENOMEM; 13769 goto init_err_pci_clean; 13770 } 13771 } 13772 rc = bnxt_init_tc(bp); 13773 if (rc) 13774 netdev_err(dev, "Failed to initialize TC flower offload, err = %d.\n", 13775 rc); 13776 } 13777 13778 bnxt_inv_fw_health_reg(bp); 13779 rc = bnxt_dl_register(bp); 13780 if (rc) 13781 goto init_err_dl; 13782 13783 rc = register_netdev(dev); 13784 if (rc) 13785 goto init_err_cleanup; 13786 13787 bnxt_dl_fw_reporters_create(bp); 13788 13789 bnxt_rdma_aux_device_init(bp); 13790 13791 bnxt_print_device_info(bp); 13792 13793 pci_save_state(pdev); 13794 13795 return 0; 13796 init_err_cleanup: 13797 bnxt_dl_unregister(bp); 13798 init_err_dl: 13799 bnxt_shutdown_tc(bp); 13800 bnxt_clear_int_mode(bp); 13801 13802 init_err_pci_clean: 13803 bnxt_hwrm_func_drv_unrgtr(bp); 13804 bnxt_free_hwrm_resources(bp); 13805 bnxt_ethtool_free(bp); 13806 bnxt_ptp_clear(bp); 13807 kfree(bp->ptp_cfg); 13808 bp->ptp_cfg = NULL; 13809 kfree(bp->fw_health); 13810 bp->fw_health = NULL; 13811 bnxt_cleanup_pci(bp); 13812 bnxt_free_ctx_mem(bp); 13813 kfree(bp->ctx); 13814 bp->ctx = NULL; 13815 kfree(bp->rss_indir_tbl); 13816 bp->rss_indir_tbl = NULL; 13817 13818 init_err_free: 13819 free_netdev(dev); 13820 return rc; 13821 } 13822 13823 static void bnxt_shutdown(struct pci_dev *pdev) 13824 { 13825 struct net_device *dev = pci_get_drvdata(pdev); 13826 struct bnxt *bp; 13827 13828 if (!dev) 13829 return; 13830 13831 rtnl_lock(); 13832 bp = netdev_priv(dev); 13833 if (!bp) 13834 goto shutdown_exit; 13835 13836 if (netif_running(dev)) 13837 dev_close(dev); 13838 13839 bnxt_clear_int_mode(bp); 13840 pci_disable_device(pdev); 13841 13842 if (system_state == SYSTEM_POWER_OFF) { 13843 pci_wake_from_d3(pdev, bp->wol); 13844 pci_set_power_state(pdev, PCI_D3hot); 13845 } 13846 13847 shutdown_exit: 13848 rtnl_unlock(); 13849 } 13850 13851 #ifdef CONFIG_PM_SLEEP 13852 static int bnxt_suspend(struct device *device) 13853 { 13854 struct net_device *dev = dev_get_drvdata(device); 13855 struct bnxt *bp = netdev_priv(dev); 13856 int rc = 0; 13857 13858 rtnl_lock(); 13859 bnxt_ulp_stop(bp); 13860 if (netif_running(dev)) { 13861 netif_device_detach(dev); 13862 rc = bnxt_close(dev); 13863 } 13864 bnxt_hwrm_func_drv_unrgtr(bp); 13865 pci_disable_device(bp->pdev); 13866 bnxt_free_ctx_mem(bp); 13867 kfree(bp->ctx); 13868 bp->ctx = NULL; 13869 rtnl_unlock(); 13870 return rc; 13871 } 13872 13873 static int bnxt_resume(struct device *device) 13874 { 13875 struct net_device *dev = dev_get_drvdata(device); 13876 struct bnxt *bp = netdev_priv(dev); 13877 int rc = 0; 13878 13879 rtnl_lock(); 13880 rc = pci_enable_device(bp->pdev); 13881 if (rc) { 13882 netdev_err(dev, "Cannot re-enable PCI device during resume, err = %d\n", 13883 rc); 13884 goto resume_exit; 13885 } 13886 pci_set_master(bp->pdev); 13887 if (bnxt_hwrm_ver_get(bp)) { 13888 rc = -ENODEV; 13889 goto resume_exit; 13890 } 13891 rc = bnxt_hwrm_func_reset(bp); 13892 if (rc) { 13893 rc = -EBUSY; 13894 goto resume_exit; 13895 } 13896 13897 rc = bnxt_hwrm_func_qcaps(bp); 13898 if (rc) 13899 goto resume_exit; 13900 13901 if (bnxt_hwrm_func_drv_rgtr(bp, NULL, 0, false)) { 13902 rc = -ENODEV; 13903 goto resume_exit; 13904 } 13905 13906 bnxt_get_wol_settings(bp); 13907 if (netif_running(dev)) { 13908 rc = bnxt_open(dev); 13909 if (!rc) 13910 netif_device_attach(dev); 13911 } 13912 13913 resume_exit: 13914 bnxt_ulp_start(bp, rc); 13915 if (!rc) 13916 bnxt_reenable_sriov(bp); 13917 rtnl_unlock(); 13918 return rc; 13919 } 13920 13921 static SIMPLE_DEV_PM_OPS(bnxt_pm_ops, bnxt_suspend, bnxt_resume); 13922 #define BNXT_PM_OPS (&bnxt_pm_ops) 13923 13924 #else 13925 13926 #define BNXT_PM_OPS NULL 13927 13928 #endif /* CONFIG_PM_SLEEP */ 13929 13930 /** 13931 * bnxt_io_error_detected - called when PCI error is detected 13932 * @pdev: Pointer to PCI device 13933 * @state: The current pci connection state 13934 * 13935 * This function is called after a PCI bus error affecting 13936 * this device has been detected. 13937 */ 13938 static pci_ers_result_t bnxt_io_error_detected(struct pci_dev *pdev, 13939 pci_channel_state_t state) 13940 { 13941 struct net_device *netdev = pci_get_drvdata(pdev); 13942 struct bnxt *bp = netdev_priv(netdev); 13943 13944 netdev_info(netdev, "PCI I/O error detected\n"); 13945 13946 rtnl_lock(); 13947 netif_device_detach(netdev); 13948 13949 bnxt_ulp_stop(bp); 13950 13951 if (state == pci_channel_io_perm_failure) { 13952 rtnl_unlock(); 13953 return PCI_ERS_RESULT_DISCONNECT; 13954 } 13955 13956 if (state == pci_channel_io_frozen) 13957 set_bit(BNXT_STATE_PCI_CHANNEL_IO_FROZEN, &bp->state); 13958 13959 if (netif_running(netdev)) 13960 bnxt_close(netdev); 13961 13962 if (pci_is_enabled(pdev)) 13963 pci_disable_device(pdev); 13964 bnxt_free_ctx_mem(bp); 13965 kfree(bp->ctx); 13966 bp->ctx = NULL; 13967 rtnl_unlock(); 13968 13969 /* Request a slot slot reset. */ 13970 return PCI_ERS_RESULT_NEED_RESET; 13971 } 13972 13973 /** 13974 * bnxt_io_slot_reset - called after the pci bus has been reset. 13975 * @pdev: Pointer to PCI device 13976 * 13977 * Restart the card from scratch, as if from a cold-boot. 13978 * At this point, the card has exprienced a hard reset, 13979 * followed by fixups by BIOS, and has its config space 13980 * set up identically to what it was at cold boot. 13981 */ 13982 static pci_ers_result_t bnxt_io_slot_reset(struct pci_dev *pdev) 13983 { 13984 pci_ers_result_t result = PCI_ERS_RESULT_DISCONNECT; 13985 struct net_device *netdev = pci_get_drvdata(pdev); 13986 struct bnxt *bp = netdev_priv(netdev); 13987 int retry = 0; 13988 int err = 0; 13989 int off; 13990 13991 netdev_info(bp->dev, "PCI Slot Reset\n"); 13992 13993 rtnl_lock(); 13994 13995 if (pci_enable_device(pdev)) { 13996 dev_err(&pdev->dev, 13997 "Cannot re-enable PCI device after reset.\n"); 13998 } else { 13999 pci_set_master(pdev); 14000 /* Upon fatal error, our device internal logic that latches to 14001 * BAR value is getting reset and will restore only upon 14002 * rewritting the BARs. 14003 * 14004 * As pci_restore_state() does not re-write the BARs if the 14005 * value is same as saved value earlier, driver needs to 14006 * write the BARs to 0 to force restore, in case of fatal error. 14007 */ 14008 if (test_and_clear_bit(BNXT_STATE_PCI_CHANNEL_IO_FROZEN, 14009 &bp->state)) { 14010 for (off = PCI_BASE_ADDRESS_0; 14011 off <= PCI_BASE_ADDRESS_5; off += 4) 14012 pci_write_config_dword(bp->pdev, off, 0); 14013 } 14014 pci_restore_state(pdev); 14015 pci_save_state(pdev); 14016 14017 bnxt_inv_fw_health_reg(bp); 14018 bnxt_try_map_fw_health_reg(bp); 14019 14020 /* In some PCIe AER scenarios, firmware may take up to 14021 * 10 seconds to become ready in the worst case. 14022 */ 14023 do { 14024 err = bnxt_try_recover_fw(bp); 14025 if (!err) 14026 break; 14027 retry++; 14028 } while (retry < BNXT_FW_SLOT_RESET_RETRY); 14029 14030 if (err) { 14031 dev_err(&pdev->dev, "Firmware not ready\n"); 14032 goto reset_exit; 14033 } 14034 14035 err = bnxt_hwrm_func_reset(bp); 14036 if (!err) 14037 result = PCI_ERS_RESULT_RECOVERED; 14038 14039 bnxt_ulp_irq_stop(bp); 14040 bnxt_clear_int_mode(bp); 14041 err = bnxt_init_int_mode(bp); 14042 bnxt_ulp_irq_restart(bp, err); 14043 } 14044 14045 reset_exit: 14046 bnxt_clear_reservations(bp, true); 14047 rtnl_unlock(); 14048 14049 return result; 14050 } 14051 14052 /** 14053 * bnxt_io_resume - called when traffic can start flowing again. 14054 * @pdev: Pointer to PCI device 14055 * 14056 * This callback is called when the error recovery driver tells 14057 * us that its OK to resume normal operation. 14058 */ 14059 static void bnxt_io_resume(struct pci_dev *pdev) 14060 { 14061 struct net_device *netdev = pci_get_drvdata(pdev); 14062 struct bnxt *bp = netdev_priv(netdev); 14063 int err; 14064 14065 netdev_info(bp->dev, "PCI Slot Resume\n"); 14066 rtnl_lock(); 14067 14068 err = bnxt_hwrm_func_qcaps(bp); 14069 if (!err && netif_running(netdev)) 14070 err = bnxt_open(netdev); 14071 14072 bnxt_ulp_start(bp, err); 14073 if (!err) { 14074 bnxt_reenable_sriov(bp); 14075 netif_device_attach(netdev); 14076 } 14077 14078 rtnl_unlock(); 14079 } 14080 14081 static const struct pci_error_handlers bnxt_err_handler = { 14082 .error_detected = bnxt_io_error_detected, 14083 .slot_reset = bnxt_io_slot_reset, 14084 .resume = bnxt_io_resume 14085 }; 14086 14087 static struct pci_driver bnxt_pci_driver = { 14088 .name = DRV_MODULE_NAME, 14089 .id_table = bnxt_pci_tbl, 14090 .probe = bnxt_init_one, 14091 .remove = bnxt_remove_one, 14092 .shutdown = bnxt_shutdown, 14093 .driver.pm = BNXT_PM_OPS, 14094 .err_handler = &bnxt_err_handler, 14095 #if defined(CONFIG_BNXT_SRIOV) 14096 .sriov_configure = bnxt_sriov_configure, 14097 #endif 14098 }; 14099 14100 static int __init bnxt_init(void) 14101 { 14102 int err; 14103 14104 bnxt_debug_init(); 14105 err = pci_register_driver(&bnxt_pci_driver); 14106 if (err) { 14107 bnxt_debug_exit(); 14108 return err; 14109 } 14110 14111 return 0; 14112 } 14113 14114 static void __exit bnxt_exit(void) 14115 { 14116 pci_unregister_driver(&bnxt_pci_driver); 14117 if (bnxt_pf_wq) 14118 destroy_workqueue(bnxt_pf_wq); 14119 bnxt_debug_exit(); 14120 } 14121 14122 module_init(bnxt_init); 14123 module_exit(bnxt_exit); 14124