1 /* bnx2x_sp.h: Broadcom Everest network driver. 2 * 3 * Copyright (c) 2011-2013 Broadcom Corporation 4 * 5 * Unless you and Broadcom execute a separate written software license 6 * agreement governing use of this software, this software is licensed to you 7 * under the terms of the GNU General Public License version 2, available 8 * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL"). 9 * 10 * Notwithstanding the above, under no circumstances may you combine this 11 * software in any way with any other Broadcom software provided under a 12 * license other than the GPL, without Broadcom's express prior written 13 * consent. 14 * 15 * Maintained by: Ariel Elior <ariel.elior@qlogic.com> 16 * Written by: Vladislav Zolotarov 17 * 18 */ 19 #ifndef BNX2X_SP_VERBS 20 #define BNX2X_SP_VERBS 21 22 struct bnx2x; 23 struct eth_context; 24 25 /* Bits representing general command's configuration */ 26 enum { 27 RAMROD_TX, 28 RAMROD_RX, 29 /* Wait until all pending commands complete */ 30 RAMROD_COMP_WAIT, 31 /* Don't send a ramrod, only update a registry */ 32 RAMROD_DRV_CLR_ONLY, 33 /* Configure HW according to the current object state */ 34 RAMROD_RESTORE, 35 /* Execute the next command now */ 36 RAMROD_EXEC, 37 /* Don't add a new command and continue execution of postponed 38 * commands. If not set a new command will be added to the 39 * pending commands list. 40 */ 41 RAMROD_CONT, 42 /* If there is another pending ramrod, wait until it finishes and 43 * re-try to submit this one. This flag can be set only in sleepable 44 * context, and should not be set from the context that completes the 45 * ramrods as deadlock will occur. 46 */ 47 RAMROD_RETRY, 48 }; 49 50 typedef enum { 51 BNX2X_OBJ_TYPE_RX, 52 BNX2X_OBJ_TYPE_TX, 53 BNX2X_OBJ_TYPE_RX_TX, 54 } bnx2x_obj_type; 55 56 /* Public slow path states */ 57 enum { 58 BNX2X_FILTER_MAC_PENDING, 59 BNX2X_FILTER_VLAN_PENDING, 60 BNX2X_FILTER_VLAN_MAC_PENDING, 61 BNX2X_FILTER_RX_MODE_PENDING, 62 BNX2X_FILTER_RX_MODE_SCHED, 63 BNX2X_FILTER_ISCSI_ETH_START_SCHED, 64 BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, 65 BNX2X_FILTER_FCOE_ETH_START_SCHED, 66 BNX2X_FILTER_FCOE_ETH_STOP_SCHED, 67 BNX2X_FILTER_MCAST_PENDING, 68 BNX2X_FILTER_MCAST_SCHED, 69 BNX2X_FILTER_RSS_CONF_PENDING, 70 BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, 71 BNX2X_AFEX_PENDING_VIFSET_MCP_ACK 72 }; 73 74 struct bnx2x_raw_obj { 75 u8 func_id; 76 77 /* Queue params */ 78 u8 cl_id; 79 u32 cid; 80 81 /* Ramrod data buffer params */ 82 void *rdata; 83 dma_addr_t rdata_mapping; 84 85 /* Ramrod state params */ 86 int state; /* "ramrod is pending" state bit */ 87 unsigned long *pstate; /* pointer to state buffer */ 88 89 bnx2x_obj_type obj_type; 90 91 int (*wait_comp)(struct bnx2x *bp, 92 struct bnx2x_raw_obj *o); 93 94 bool (*check_pending)(struct bnx2x_raw_obj *o); 95 void (*clear_pending)(struct bnx2x_raw_obj *o); 96 void (*set_pending)(struct bnx2x_raw_obj *o); 97 }; 98 99 /************************* VLAN-MAC commands related parameters ***************/ 100 struct bnx2x_mac_ramrod_data { 101 u8 mac[ETH_ALEN]; 102 u8 is_inner_mac; 103 }; 104 105 struct bnx2x_vlan_ramrod_data { 106 u16 vlan; 107 }; 108 109 struct bnx2x_vlan_mac_ramrod_data { 110 u8 mac[ETH_ALEN]; 111 u8 is_inner_mac; 112 u16 vlan; 113 }; 114 115 union bnx2x_classification_ramrod_data { 116 struct bnx2x_mac_ramrod_data mac; 117 struct bnx2x_vlan_ramrod_data vlan; 118 struct bnx2x_vlan_mac_ramrod_data vlan_mac; 119 }; 120 121 /* VLAN_MAC commands */ 122 enum bnx2x_vlan_mac_cmd { 123 BNX2X_VLAN_MAC_ADD, 124 BNX2X_VLAN_MAC_DEL, 125 BNX2X_VLAN_MAC_MOVE, 126 }; 127 128 struct bnx2x_vlan_mac_data { 129 /* Requested command: BNX2X_VLAN_MAC_XX */ 130 enum bnx2x_vlan_mac_cmd cmd; 131 /* used to contain the data related vlan_mac_flags bits from 132 * ramrod parameters. 133 */ 134 unsigned long vlan_mac_flags; 135 136 /* Needed for MOVE command */ 137 struct bnx2x_vlan_mac_obj *target_obj; 138 139 union bnx2x_classification_ramrod_data u; 140 }; 141 142 /*************************** Exe Queue obj ************************************/ 143 union bnx2x_exe_queue_cmd_data { 144 struct bnx2x_vlan_mac_data vlan_mac; 145 146 struct { 147 /* TODO */ 148 } mcast; 149 }; 150 151 struct bnx2x_exeq_elem { 152 struct list_head link; 153 154 /* Length of this element in the exe_chunk. */ 155 int cmd_len; 156 157 union bnx2x_exe_queue_cmd_data cmd_data; 158 }; 159 160 union bnx2x_qable_obj; 161 162 union bnx2x_exeq_comp_elem { 163 union event_ring_elem *elem; 164 }; 165 166 struct bnx2x_exe_queue_obj; 167 168 typedef int (*exe_q_validate)(struct bnx2x *bp, 169 union bnx2x_qable_obj *o, 170 struct bnx2x_exeq_elem *elem); 171 172 typedef int (*exe_q_remove)(struct bnx2x *bp, 173 union bnx2x_qable_obj *o, 174 struct bnx2x_exeq_elem *elem); 175 176 /* Return positive if entry was optimized, 0 - if not, negative 177 * in case of an error. 178 */ 179 typedef int (*exe_q_optimize)(struct bnx2x *bp, 180 union bnx2x_qable_obj *o, 181 struct bnx2x_exeq_elem *elem); 182 typedef int (*exe_q_execute)(struct bnx2x *bp, 183 union bnx2x_qable_obj *o, 184 struct list_head *exe_chunk, 185 unsigned long *ramrod_flags); 186 typedef struct bnx2x_exeq_elem * 187 (*exe_q_get)(struct bnx2x_exe_queue_obj *o, 188 struct bnx2x_exeq_elem *elem); 189 190 struct bnx2x_exe_queue_obj { 191 /* Commands pending for an execution. */ 192 struct list_head exe_queue; 193 194 /* Commands pending for an completion. */ 195 struct list_head pending_comp; 196 197 spinlock_t lock; 198 199 /* Maximum length of commands' list for one execution */ 200 int exe_chunk_len; 201 202 union bnx2x_qable_obj *owner; 203 204 /****** Virtual functions ******/ 205 /** 206 * Called before commands execution for commands that are really 207 * going to be executed (after 'optimize'). 208 * 209 * Must run under exe_queue->lock 210 */ 211 exe_q_validate validate; 212 213 /** 214 * Called before removing pending commands, cleaning allocated 215 * resources (e.g., credits from validate) 216 */ 217 exe_q_remove remove; 218 219 /** 220 * This will try to cancel the current pending commands list 221 * considering the new command. 222 * 223 * Returns the number of optimized commands or a negative error code 224 * 225 * Must run under exe_queue->lock 226 */ 227 exe_q_optimize optimize; 228 229 /** 230 * Run the next commands chunk (owner specific). 231 */ 232 exe_q_execute execute; 233 234 /** 235 * Return the exe_queue element containing the specific command 236 * if any. Otherwise return NULL. 237 */ 238 exe_q_get get; 239 }; 240 /***************** Classification verbs: Set/Del MAC/VLAN/VLAN-MAC ************/ 241 /* 242 * Element in the VLAN_MAC registry list having all currently configured 243 * rules. 244 */ 245 struct bnx2x_vlan_mac_registry_elem { 246 struct list_head link; 247 248 /* Used to store the cam offset used for the mac/vlan/vlan-mac. 249 * Relevant for 57710 and 57711 only. VLANs and MACs share the 250 * same CAM for these chips. 251 */ 252 int cam_offset; 253 254 /* Needed for DEL and RESTORE flows */ 255 unsigned long vlan_mac_flags; 256 257 union bnx2x_classification_ramrod_data u; 258 }; 259 260 /* Bits representing VLAN_MAC commands specific flags */ 261 enum { 262 BNX2X_UC_LIST_MAC, 263 BNX2X_ETH_MAC, 264 BNX2X_ISCSI_ETH_MAC, 265 BNX2X_NETQ_ETH_MAC, 266 BNX2X_DONT_CONSUME_CAM_CREDIT, 267 BNX2X_DONT_CONSUME_CAM_CREDIT_DEST, 268 }; 269 /* When looking for matching filters, some flags are not interesting */ 270 #define BNX2X_VLAN_MAC_CMP_MASK (1 << BNX2X_UC_LIST_MAC | \ 271 1 << BNX2X_ETH_MAC | \ 272 1 << BNX2X_ISCSI_ETH_MAC | \ 273 1 << BNX2X_NETQ_ETH_MAC) 274 #define BNX2X_VLAN_MAC_CMP_FLAGS(flags) \ 275 ((flags) & BNX2X_VLAN_MAC_CMP_MASK) 276 277 struct bnx2x_vlan_mac_ramrod_params { 278 /* Object to run the command from */ 279 struct bnx2x_vlan_mac_obj *vlan_mac_obj; 280 281 /* General command flags: COMP_WAIT, etc. */ 282 unsigned long ramrod_flags; 283 284 /* Command specific configuration request */ 285 struct bnx2x_vlan_mac_data user_req; 286 }; 287 288 struct bnx2x_vlan_mac_obj { 289 struct bnx2x_raw_obj raw; 290 291 /* Bookkeeping list: will prevent the addition of already existing 292 * entries. 293 */ 294 struct list_head head; 295 /* Implement a simple reader/writer lock on the head list. 296 * all these fields should only be accessed under the exe_queue lock 297 */ 298 u8 head_reader; /* Num. of readers accessing head list */ 299 bool head_exe_request; /* Pending execution request. */ 300 unsigned long saved_ramrod_flags; /* Ramrods of pending execution */ 301 302 /* TODO: Add it's initialization in the init functions */ 303 struct bnx2x_exe_queue_obj exe_queue; 304 305 /* MACs credit pool */ 306 struct bnx2x_credit_pool_obj *macs_pool; 307 308 /* VLANs credit pool */ 309 struct bnx2x_credit_pool_obj *vlans_pool; 310 311 /* RAMROD command to be used */ 312 int ramrod_cmd; 313 314 /* copy first n elements onto preallocated buffer 315 * 316 * @param n number of elements to get 317 * @param buf buffer preallocated by caller into which elements 318 * will be copied. Note elements are 4-byte aligned 319 * so buffer size must be able to accommodate the 320 * aligned elements. 321 * 322 * @return number of copied bytes 323 */ 324 int (*get_n_elements)(struct bnx2x *bp, 325 struct bnx2x_vlan_mac_obj *o, int n, u8 *base, 326 u8 stride, u8 size); 327 328 /** 329 * Checks if ADD-ramrod with the given params may be performed. 330 * 331 * @return zero if the element may be added 332 */ 333 334 int (*check_add)(struct bnx2x *bp, 335 struct bnx2x_vlan_mac_obj *o, 336 union bnx2x_classification_ramrod_data *data); 337 338 /** 339 * Checks if DEL-ramrod with the given params may be performed. 340 * 341 * @return true if the element may be deleted 342 */ 343 struct bnx2x_vlan_mac_registry_elem * 344 (*check_del)(struct bnx2x *bp, 345 struct bnx2x_vlan_mac_obj *o, 346 union bnx2x_classification_ramrod_data *data); 347 348 /** 349 * Checks if DEL-ramrod with the given params may be performed. 350 * 351 * @return true if the element may be deleted 352 */ 353 bool (*check_move)(struct bnx2x *bp, 354 struct bnx2x_vlan_mac_obj *src_o, 355 struct bnx2x_vlan_mac_obj *dst_o, 356 union bnx2x_classification_ramrod_data *data); 357 358 /** 359 * Update the relevant credit object(s) (consume/return 360 * correspondingly). 361 */ 362 bool (*get_credit)(struct bnx2x_vlan_mac_obj *o); 363 bool (*put_credit)(struct bnx2x_vlan_mac_obj *o); 364 bool (*get_cam_offset)(struct bnx2x_vlan_mac_obj *o, int *offset); 365 bool (*put_cam_offset)(struct bnx2x_vlan_mac_obj *o, int offset); 366 367 /** 368 * Configures one rule in the ramrod data buffer. 369 */ 370 void (*set_one_rule)(struct bnx2x *bp, 371 struct bnx2x_vlan_mac_obj *o, 372 struct bnx2x_exeq_elem *elem, int rule_idx, 373 int cam_offset); 374 375 /** 376 * Delete all configured elements having the given 377 * vlan_mac_flags specification. Assumes no pending for 378 * execution commands. Will schedule all all currently 379 * configured MACs/VLANs/VLAN-MACs matching the vlan_mac_flags 380 * specification for deletion and will use the given 381 * ramrod_flags for the last DEL operation. 382 * 383 * @param bp 384 * @param o 385 * @param ramrod_flags RAMROD_XX flags 386 * 387 * @return 0 if the last operation has completed successfully 388 * and there are no more elements left, positive value 389 * if there are pending for completion commands, 390 * negative value in case of failure. 391 */ 392 int (*delete_all)(struct bnx2x *bp, 393 struct bnx2x_vlan_mac_obj *o, 394 unsigned long *vlan_mac_flags, 395 unsigned long *ramrod_flags); 396 397 /** 398 * Reconfigures the next MAC/VLAN/VLAN-MAC element from the previously 399 * configured elements list. 400 * 401 * @param bp 402 * @param p Command parameters (RAMROD_COMP_WAIT bit in 403 * ramrod_flags is only taken into an account) 404 * @param ppos a pointer to the cookie that should be given back in the 405 * next call to make function handle the next element. If 406 * *ppos is set to NULL it will restart the iterator. 407 * If returned *ppos == NULL this means that the last 408 * element has been handled. 409 * 410 * @return int 411 */ 412 int (*restore)(struct bnx2x *bp, 413 struct bnx2x_vlan_mac_ramrod_params *p, 414 struct bnx2x_vlan_mac_registry_elem **ppos); 415 416 /** 417 * Should be called on a completion arrival. 418 * 419 * @param bp 420 * @param o 421 * @param cqe Completion element we are handling 422 * @param ramrod_flags if RAMROD_CONT is set the next bulk of 423 * pending commands will be executed. 424 * RAMROD_DRV_CLR_ONLY and RAMROD_RESTORE 425 * may also be set if needed. 426 * 427 * @return 0 if there are neither pending nor waiting for 428 * completion commands. Positive value if there are 429 * pending for execution or for completion commands. 430 * Negative value in case of an error (including an 431 * error in the cqe). 432 */ 433 int (*complete)(struct bnx2x *bp, struct bnx2x_vlan_mac_obj *o, 434 union event_ring_elem *cqe, 435 unsigned long *ramrod_flags); 436 437 /** 438 * Wait for completion of all commands. Don't schedule new ones, 439 * just wait. It assumes that the completion code will schedule 440 * for new commands. 441 */ 442 int (*wait)(struct bnx2x *bp, struct bnx2x_vlan_mac_obj *o); 443 }; 444 445 enum { 446 BNX2X_LLH_CAM_ISCSI_ETH_LINE = 0, 447 BNX2X_LLH_CAM_ETH_LINE, 448 BNX2X_LLH_CAM_MAX_PF_LINE = NIG_REG_LLH1_FUNC_MEM_SIZE / 2 449 }; 450 451 /** RX_MODE verbs:DROP_ALL/ACCEPT_ALL/ACCEPT_ALL_MULTI/ACCEPT_ALL_VLAN/NORMAL */ 452 453 /* RX_MODE ramrod special flags: set in rx_mode_flags field in 454 * a bnx2x_rx_mode_ramrod_params. 455 */ 456 enum { 457 BNX2X_RX_MODE_FCOE_ETH, 458 BNX2X_RX_MODE_ISCSI_ETH, 459 }; 460 461 enum { 462 BNX2X_ACCEPT_UNICAST, 463 BNX2X_ACCEPT_MULTICAST, 464 BNX2X_ACCEPT_ALL_UNICAST, 465 BNX2X_ACCEPT_ALL_MULTICAST, 466 BNX2X_ACCEPT_BROADCAST, 467 BNX2X_ACCEPT_UNMATCHED, 468 BNX2X_ACCEPT_ANY_VLAN 469 }; 470 471 struct bnx2x_rx_mode_ramrod_params { 472 struct bnx2x_rx_mode_obj *rx_mode_obj; 473 unsigned long *pstate; 474 int state; 475 u8 cl_id; 476 u32 cid; 477 u8 func_id; 478 unsigned long ramrod_flags; 479 unsigned long rx_mode_flags; 480 481 /* rdata is either a pointer to eth_filter_rules_ramrod_data(e2) or to 482 * a tstorm_eth_mac_filter_config (e1x). 483 */ 484 void *rdata; 485 dma_addr_t rdata_mapping; 486 487 /* Rx mode settings */ 488 unsigned long rx_accept_flags; 489 490 /* internal switching settings */ 491 unsigned long tx_accept_flags; 492 }; 493 494 struct bnx2x_rx_mode_obj { 495 int (*config_rx_mode)(struct bnx2x *bp, 496 struct bnx2x_rx_mode_ramrod_params *p); 497 498 int (*wait_comp)(struct bnx2x *bp, 499 struct bnx2x_rx_mode_ramrod_params *p); 500 }; 501 502 /********************** Set multicast group ***********************************/ 503 504 struct bnx2x_mcast_list_elem { 505 struct list_head link; 506 u8 *mac; 507 }; 508 509 union bnx2x_mcast_config_data { 510 u8 *mac; 511 u8 bin; /* used in a RESTORE flow */ 512 }; 513 514 struct bnx2x_mcast_ramrod_params { 515 struct bnx2x_mcast_obj *mcast_obj; 516 517 /* Relevant options are RAMROD_COMP_WAIT and RAMROD_DRV_CLR_ONLY */ 518 unsigned long ramrod_flags; 519 520 struct list_head mcast_list; /* list of struct bnx2x_mcast_list_elem */ 521 /** TODO: 522 * - rename it to macs_num. 523 * - Add a new command type for handling pending commands 524 * (remove "zero semantics"). 525 * 526 * Length of mcast_list. If zero and ADD_CONT command - post 527 * pending commands. 528 */ 529 int mcast_list_len; 530 }; 531 532 enum bnx2x_mcast_cmd { 533 BNX2X_MCAST_CMD_ADD, 534 BNX2X_MCAST_CMD_CONT, 535 BNX2X_MCAST_CMD_DEL, 536 BNX2X_MCAST_CMD_RESTORE, 537 }; 538 539 struct bnx2x_mcast_obj { 540 struct bnx2x_raw_obj raw; 541 542 union { 543 struct { 544 #define BNX2X_MCAST_BINS_NUM 256 545 #define BNX2X_MCAST_VEC_SZ (BNX2X_MCAST_BINS_NUM / 64) 546 u64 vec[BNX2X_MCAST_VEC_SZ]; 547 548 /** Number of BINs to clear. Should be updated 549 * immediately when a command arrives in order to 550 * properly create DEL commands. 551 */ 552 int num_bins_set; 553 } aprox_match; 554 555 struct { 556 struct list_head macs; 557 int num_macs_set; 558 } exact_match; 559 } registry; 560 561 /* Pending commands */ 562 struct list_head pending_cmds_head; 563 564 /* A state that is set in raw.pstate, when there are pending commands */ 565 int sched_state; 566 567 /* Maximal number of mcast MACs configured in one command */ 568 int max_cmd_len; 569 570 /* Total number of currently pending MACs to configure: both 571 * in the pending commands list and in the current command. 572 */ 573 int total_pending_num; 574 575 u8 engine_id; 576 577 /** 578 * @param cmd command to execute (BNX2X_MCAST_CMD_X, see above) 579 */ 580 int (*config_mcast)(struct bnx2x *bp, 581 struct bnx2x_mcast_ramrod_params *p, 582 enum bnx2x_mcast_cmd cmd); 583 584 /** 585 * Fills the ramrod data during the RESTORE flow. 586 * 587 * @param bp 588 * @param o 589 * @param start_idx Registry index to start from 590 * @param rdata_idx Index in the ramrod data to start from 591 * 592 * @return -1 if we handled the whole registry or index of the last 593 * handled registry element. 594 */ 595 int (*hdl_restore)(struct bnx2x *bp, struct bnx2x_mcast_obj *o, 596 int start_bin, int *rdata_idx); 597 598 int (*enqueue_cmd)(struct bnx2x *bp, struct bnx2x_mcast_obj *o, 599 struct bnx2x_mcast_ramrod_params *p, 600 enum bnx2x_mcast_cmd cmd); 601 602 void (*set_one_rule)(struct bnx2x *bp, 603 struct bnx2x_mcast_obj *o, int idx, 604 union bnx2x_mcast_config_data *cfg_data, 605 enum bnx2x_mcast_cmd cmd); 606 607 /** Checks if there are more mcast MACs to be set or a previous 608 * command is still pending. 609 */ 610 bool (*check_pending)(struct bnx2x_mcast_obj *o); 611 612 /** 613 * Set/Clear/Check SCHEDULED state of the object 614 */ 615 void (*set_sched)(struct bnx2x_mcast_obj *o); 616 void (*clear_sched)(struct bnx2x_mcast_obj *o); 617 bool (*check_sched)(struct bnx2x_mcast_obj *o); 618 619 /* Wait until all pending commands complete */ 620 int (*wait_comp)(struct bnx2x *bp, struct bnx2x_mcast_obj *o); 621 622 /** 623 * Handle the internal object counters needed for proper 624 * commands handling. Checks that the provided parameters are 625 * feasible. 626 */ 627 int (*validate)(struct bnx2x *bp, 628 struct bnx2x_mcast_ramrod_params *p, 629 enum bnx2x_mcast_cmd cmd); 630 631 /** 632 * Restore the values of internal counters in case of a failure. 633 */ 634 void (*revert)(struct bnx2x *bp, 635 struct bnx2x_mcast_ramrod_params *p, 636 int old_num_bins); 637 638 int (*get_registry_size)(struct bnx2x_mcast_obj *o); 639 void (*set_registry_size)(struct bnx2x_mcast_obj *o, int n); 640 }; 641 642 /*************************** Credit handling **********************************/ 643 struct bnx2x_credit_pool_obj { 644 645 /* Current amount of credit in the pool */ 646 atomic_t credit; 647 648 /* Maximum allowed credit. put() will check against it. */ 649 int pool_sz; 650 651 /* Allocate a pool table statically. 652 * 653 * Currently the maximum allowed size is MAX_MAC_CREDIT_E2(272) 654 * 655 * The set bit in the table will mean that the entry is available. 656 */ 657 #define BNX2X_POOL_VEC_SIZE (MAX_MAC_CREDIT_E2 / 64) 658 u64 pool_mirror[BNX2X_POOL_VEC_SIZE]; 659 660 /* Base pool offset (initialized differently */ 661 int base_pool_offset; 662 663 /** 664 * Get the next free pool entry. 665 * 666 * @return true if there was a free entry in the pool 667 */ 668 bool (*get_entry)(struct bnx2x_credit_pool_obj *o, int *entry); 669 670 /** 671 * Return the entry back to the pool. 672 * 673 * @return true if entry is legal and has been successfully 674 * returned to the pool. 675 */ 676 bool (*put_entry)(struct bnx2x_credit_pool_obj *o, int entry); 677 678 /** 679 * Get the requested amount of credit from the pool. 680 * 681 * @param cnt Amount of requested credit 682 * @return true if the operation is successful 683 */ 684 bool (*get)(struct bnx2x_credit_pool_obj *o, int cnt); 685 686 /** 687 * Returns the credit to the pool. 688 * 689 * @param cnt Amount of credit to return 690 * @return true if the operation is successful 691 */ 692 bool (*put)(struct bnx2x_credit_pool_obj *o, int cnt); 693 694 /** 695 * Reads the current amount of credit. 696 */ 697 int (*check)(struct bnx2x_credit_pool_obj *o); 698 }; 699 700 /*************************** RSS configuration ********************************/ 701 enum { 702 /* RSS_MODE bits are mutually exclusive */ 703 BNX2X_RSS_MODE_DISABLED, 704 BNX2X_RSS_MODE_REGULAR, 705 706 BNX2X_RSS_SET_SRCH, /* Setup searcher, E1x specific flag */ 707 708 BNX2X_RSS_IPV4, 709 BNX2X_RSS_IPV4_TCP, 710 BNX2X_RSS_IPV4_UDP, 711 BNX2X_RSS_IPV6, 712 BNX2X_RSS_IPV6_TCP, 713 BNX2X_RSS_IPV6_UDP, 714 BNX2X_RSS_GRE_INNER_HDRS, 715 }; 716 717 struct bnx2x_config_rss_params { 718 struct bnx2x_rss_config_obj *rss_obj; 719 720 /* may have RAMROD_COMP_WAIT set only */ 721 unsigned long ramrod_flags; 722 723 /* BNX2X_RSS_X bits */ 724 unsigned long rss_flags; 725 726 /* Number hash bits to take into an account */ 727 u8 rss_result_mask; 728 729 /* Indirection table */ 730 u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE]; 731 732 /* RSS hash values */ 733 u32 rss_key[10]; 734 735 /* valid only iff BNX2X_RSS_UPDATE_TOE is set */ 736 u16 toe_rss_bitmap; 737 }; 738 739 struct bnx2x_rss_config_obj { 740 struct bnx2x_raw_obj raw; 741 742 /* RSS engine to use */ 743 u8 engine_id; 744 745 /* Last configured indirection table */ 746 u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE]; 747 748 /* flags for enabling 4-tupple hash on UDP */ 749 u8 udp_rss_v4; 750 u8 udp_rss_v6; 751 752 int (*config_rss)(struct bnx2x *bp, 753 struct bnx2x_config_rss_params *p); 754 }; 755 756 /*********************** Queue state update ***********************************/ 757 758 /* UPDATE command options */ 759 enum { 760 BNX2X_Q_UPDATE_IN_VLAN_REM, 761 BNX2X_Q_UPDATE_IN_VLAN_REM_CHNG, 762 BNX2X_Q_UPDATE_OUT_VLAN_REM, 763 BNX2X_Q_UPDATE_OUT_VLAN_REM_CHNG, 764 BNX2X_Q_UPDATE_ANTI_SPOOF, 765 BNX2X_Q_UPDATE_ANTI_SPOOF_CHNG, 766 BNX2X_Q_UPDATE_ACTIVATE, 767 BNX2X_Q_UPDATE_ACTIVATE_CHNG, 768 BNX2X_Q_UPDATE_DEF_VLAN_EN, 769 BNX2X_Q_UPDATE_DEF_VLAN_EN_CHNG, 770 BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG, 771 BNX2X_Q_UPDATE_SILENT_VLAN_REM, 772 BNX2X_Q_UPDATE_TX_SWITCHING_CHNG, 773 BNX2X_Q_UPDATE_TX_SWITCHING, 774 BNX2X_Q_UPDATE_PTP_PKTS_CHNG, 775 BNX2X_Q_UPDATE_PTP_PKTS, 776 }; 777 778 /* Allowed Queue states */ 779 enum bnx2x_q_state { 780 BNX2X_Q_STATE_RESET, 781 BNX2X_Q_STATE_INITIALIZED, 782 BNX2X_Q_STATE_ACTIVE, 783 BNX2X_Q_STATE_MULTI_COS, 784 BNX2X_Q_STATE_MCOS_TERMINATED, 785 BNX2X_Q_STATE_INACTIVE, 786 BNX2X_Q_STATE_STOPPED, 787 BNX2X_Q_STATE_TERMINATED, 788 BNX2X_Q_STATE_FLRED, 789 BNX2X_Q_STATE_MAX, 790 }; 791 792 /* Allowed Queue states */ 793 enum bnx2x_q_logical_state { 794 BNX2X_Q_LOGICAL_STATE_ACTIVE, 795 BNX2X_Q_LOGICAL_STATE_STOPPED, 796 }; 797 798 /* Allowed commands */ 799 enum bnx2x_queue_cmd { 800 BNX2X_Q_CMD_INIT, 801 BNX2X_Q_CMD_SETUP, 802 BNX2X_Q_CMD_SETUP_TX_ONLY, 803 BNX2X_Q_CMD_DEACTIVATE, 804 BNX2X_Q_CMD_ACTIVATE, 805 BNX2X_Q_CMD_UPDATE, 806 BNX2X_Q_CMD_UPDATE_TPA, 807 BNX2X_Q_CMD_HALT, 808 BNX2X_Q_CMD_CFC_DEL, 809 BNX2X_Q_CMD_TERMINATE, 810 BNX2X_Q_CMD_EMPTY, 811 BNX2X_Q_CMD_MAX, 812 }; 813 814 /* queue SETUP + INIT flags */ 815 enum { 816 BNX2X_Q_FLG_TPA, 817 BNX2X_Q_FLG_TPA_IPV6, 818 BNX2X_Q_FLG_TPA_GRO, 819 BNX2X_Q_FLG_STATS, 820 BNX2X_Q_FLG_ZERO_STATS, 821 BNX2X_Q_FLG_ACTIVE, 822 BNX2X_Q_FLG_OV, 823 BNX2X_Q_FLG_VLAN, 824 BNX2X_Q_FLG_COS, 825 BNX2X_Q_FLG_HC, 826 BNX2X_Q_FLG_HC_EN, 827 BNX2X_Q_FLG_DHC, 828 BNX2X_Q_FLG_FCOE, 829 BNX2X_Q_FLG_LEADING_RSS, 830 BNX2X_Q_FLG_MCAST, 831 BNX2X_Q_FLG_DEF_VLAN, 832 BNX2X_Q_FLG_TX_SWITCH, 833 BNX2X_Q_FLG_TX_SEC, 834 BNX2X_Q_FLG_ANTI_SPOOF, 835 BNX2X_Q_FLG_SILENT_VLAN_REM, 836 BNX2X_Q_FLG_FORCE_DEFAULT_PRI, 837 BNX2X_Q_FLG_REFUSE_OUTBAND_VLAN, 838 BNX2X_Q_FLG_PCSUM_ON_PKT, 839 BNX2X_Q_FLG_TUN_INC_INNER_IP_ID 840 }; 841 842 /* Queue type options: queue type may be a combination of below. */ 843 enum bnx2x_q_type { 844 /** TODO: Consider moving both these flags into the init() 845 * ramrod params. 846 */ 847 BNX2X_Q_TYPE_HAS_RX, 848 BNX2X_Q_TYPE_HAS_TX, 849 }; 850 851 #define BNX2X_PRIMARY_CID_INDEX 0 852 #define BNX2X_MULTI_TX_COS_E1X 3 /* QM only */ 853 #define BNX2X_MULTI_TX_COS_E2_E3A0 2 854 #define BNX2X_MULTI_TX_COS_E3B0 3 855 #define BNX2X_MULTI_TX_COS 3 /* Maximum possible */ 856 857 #define MAC_PAD (ALIGN(ETH_ALEN, sizeof(u32)) - ETH_ALEN) 858 /* DMAE channel to be used by FW for timesync workaroun. A driver that sends 859 * timesync-related ramrods must not use this DMAE command ID. 860 */ 861 #define FW_DMAE_CMD_ID 6 862 863 struct bnx2x_queue_init_params { 864 struct { 865 unsigned long flags; 866 u16 hc_rate; 867 u8 fw_sb_id; 868 u8 sb_cq_index; 869 } tx; 870 871 struct { 872 unsigned long flags; 873 u16 hc_rate; 874 u8 fw_sb_id; 875 u8 sb_cq_index; 876 } rx; 877 878 /* CID context in the host memory */ 879 struct eth_context *cxts[BNX2X_MULTI_TX_COS]; 880 881 /* maximum number of cos supported by hardware */ 882 u8 max_cos; 883 }; 884 885 struct bnx2x_queue_terminate_params { 886 /* index within the tx_only cids of this queue object */ 887 u8 cid_index; 888 }; 889 890 struct bnx2x_queue_cfc_del_params { 891 /* index within the tx_only cids of this queue object */ 892 u8 cid_index; 893 }; 894 895 struct bnx2x_queue_update_params { 896 unsigned long update_flags; /* BNX2X_Q_UPDATE_XX bits */ 897 u16 def_vlan; 898 u16 silent_removal_value; 899 u16 silent_removal_mask; 900 /* index within the tx_only cids of this queue object */ 901 u8 cid_index; 902 }; 903 904 struct bnx2x_queue_update_tpa_params { 905 dma_addr_t sge_map; 906 u8 update_ipv4; 907 u8 update_ipv6; 908 u8 max_tpa_queues; 909 u8 max_sges_pkt; 910 u8 complete_on_both_clients; 911 u8 dont_verify_thr; 912 u8 tpa_mode; 913 u8 _pad; 914 915 u16 sge_buff_sz; 916 u16 max_agg_sz; 917 918 u16 sge_pause_thr_low; 919 u16 sge_pause_thr_high; 920 }; 921 922 struct rxq_pause_params { 923 u16 bd_th_lo; 924 u16 bd_th_hi; 925 u16 rcq_th_lo; 926 u16 rcq_th_hi; 927 u16 sge_th_lo; /* valid iff BNX2X_Q_FLG_TPA */ 928 u16 sge_th_hi; /* valid iff BNX2X_Q_FLG_TPA */ 929 u16 pri_map; 930 }; 931 932 /* general */ 933 struct bnx2x_general_setup_params { 934 /* valid iff BNX2X_Q_FLG_STATS */ 935 u8 stat_id; 936 937 u8 spcl_id; 938 u16 mtu; 939 u8 cos; 940 }; 941 942 struct bnx2x_rxq_setup_params { 943 /* dma */ 944 dma_addr_t dscr_map; 945 dma_addr_t sge_map; 946 dma_addr_t rcq_map; 947 dma_addr_t rcq_np_map; 948 949 u16 drop_flags; 950 u16 buf_sz; 951 u8 fw_sb_id; 952 u8 cl_qzone_id; 953 954 /* valid iff BNX2X_Q_FLG_TPA */ 955 u16 tpa_agg_sz; 956 u16 sge_buf_sz; 957 u8 max_sges_pkt; 958 u8 max_tpa_queues; 959 u8 rss_engine_id; 960 961 /* valid iff BNX2X_Q_FLG_MCAST */ 962 u8 mcast_engine_id; 963 964 u8 cache_line_log; 965 966 u8 sb_cq_index; 967 968 /* valid iff BXN2X_Q_FLG_SILENT_VLAN_REM */ 969 u16 silent_removal_value; 970 u16 silent_removal_mask; 971 }; 972 973 struct bnx2x_txq_setup_params { 974 /* dma */ 975 dma_addr_t dscr_map; 976 977 u8 fw_sb_id; 978 u8 sb_cq_index; 979 u8 cos; /* valid iff BNX2X_Q_FLG_COS */ 980 u16 traffic_type; 981 /* equals to the leading rss client id, used for TX classification*/ 982 u8 tss_leading_cl_id; 983 984 /* valid iff BNX2X_Q_FLG_DEF_VLAN */ 985 u16 default_vlan; 986 }; 987 988 struct bnx2x_queue_setup_params { 989 struct bnx2x_general_setup_params gen_params; 990 struct bnx2x_txq_setup_params txq_params; 991 struct bnx2x_rxq_setup_params rxq_params; 992 struct rxq_pause_params pause_params; 993 unsigned long flags; 994 }; 995 996 struct bnx2x_queue_setup_tx_only_params { 997 struct bnx2x_general_setup_params gen_params; 998 struct bnx2x_txq_setup_params txq_params; 999 unsigned long flags; 1000 /* index within the tx_only cids of this queue object */ 1001 u8 cid_index; 1002 }; 1003 1004 struct bnx2x_queue_state_params { 1005 struct bnx2x_queue_sp_obj *q_obj; 1006 1007 /* Current command */ 1008 enum bnx2x_queue_cmd cmd; 1009 1010 /* may have RAMROD_COMP_WAIT set only */ 1011 unsigned long ramrod_flags; 1012 1013 /* Params according to the current command */ 1014 union { 1015 struct bnx2x_queue_update_params update; 1016 struct bnx2x_queue_update_tpa_params update_tpa; 1017 struct bnx2x_queue_setup_params setup; 1018 struct bnx2x_queue_init_params init; 1019 struct bnx2x_queue_setup_tx_only_params tx_only; 1020 struct bnx2x_queue_terminate_params terminate; 1021 struct bnx2x_queue_cfc_del_params cfc_del; 1022 } params; 1023 }; 1024 1025 struct bnx2x_viflist_params { 1026 u8 echo_res; 1027 u8 func_bit_map_res; 1028 }; 1029 1030 struct bnx2x_queue_sp_obj { 1031 u32 cids[BNX2X_MULTI_TX_COS]; 1032 u8 cl_id; 1033 u8 func_id; 1034 1035 /* number of traffic classes supported by queue. 1036 * The primary connection of the queue supports the first traffic 1037 * class. Any further traffic class is supported by a tx-only 1038 * connection. 1039 * 1040 * Therefore max_cos is also a number of valid entries in the cids 1041 * array. 1042 */ 1043 u8 max_cos; 1044 u8 num_tx_only, next_tx_only; 1045 1046 enum bnx2x_q_state state, next_state; 1047 1048 /* bits from enum bnx2x_q_type */ 1049 unsigned long type; 1050 1051 /* BNX2X_Q_CMD_XX bits. This object implements "one 1052 * pending" paradigm but for debug and tracing purposes it's 1053 * more convenient to have different bits for different 1054 * commands. 1055 */ 1056 unsigned long pending; 1057 1058 /* Buffer to use as a ramrod data and its mapping */ 1059 void *rdata; 1060 dma_addr_t rdata_mapping; 1061 1062 /** 1063 * Performs one state change according to the given parameters. 1064 * 1065 * @return 0 in case of success and negative value otherwise. 1066 */ 1067 int (*send_cmd)(struct bnx2x *bp, 1068 struct bnx2x_queue_state_params *params); 1069 1070 /** 1071 * Sets the pending bit according to the requested transition. 1072 */ 1073 int (*set_pending)(struct bnx2x_queue_sp_obj *o, 1074 struct bnx2x_queue_state_params *params); 1075 1076 /** 1077 * Checks that the requested state transition is legal. 1078 */ 1079 int (*check_transition)(struct bnx2x *bp, 1080 struct bnx2x_queue_sp_obj *o, 1081 struct bnx2x_queue_state_params *params); 1082 1083 /** 1084 * Completes the pending command. 1085 */ 1086 int (*complete_cmd)(struct bnx2x *bp, 1087 struct bnx2x_queue_sp_obj *o, 1088 enum bnx2x_queue_cmd); 1089 1090 int (*wait_comp)(struct bnx2x *bp, 1091 struct bnx2x_queue_sp_obj *o, 1092 enum bnx2x_queue_cmd cmd); 1093 }; 1094 1095 /********************** Function state update *********************************/ 1096 1097 /* UPDATE command options */ 1098 enum { 1099 BNX2X_F_UPDATE_TX_SWITCH_SUSPEND_CHNG, 1100 BNX2X_F_UPDATE_TX_SWITCH_SUSPEND, 1101 BNX2X_F_UPDATE_TUNNEL_CFG_CHNG, 1102 BNX2X_F_UPDATE_TUNNEL_CLSS_EN, 1103 BNX2X_F_UPDATE_TUNNEL_INNER_GRE_RSS_EN, 1104 }; 1105 1106 /* Allowed Function states */ 1107 enum bnx2x_func_state { 1108 BNX2X_F_STATE_RESET, 1109 BNX2X_F_STATE_INITIALIZED, 1110 BNX2X_F_STATE_STARTED, 1111 BNX2X_F_STATE_TX_STOPPED, 1112 BNX2X_F_STATE_MAX, 1113 }; 1114 1115 /* Allowed Function commands */ 1116 enum bnx2x_func_cmd { 1117 BNX2X_F_CMD_HW_INIT, 1118 BNX2X_F_CMD_START, 1119 BNX2X_F_CMD_STOP, 1120 BNX2X_F_CMD_HW_RESET, 1121 BNX2X_F_CMD_AFEX_UPDATE, 1122 BNX2X_F_CMD_AFEX_VIFLISTS, 1123 BNX2X_F_CMD_TX_STOP, 1124 BNX2X_F_CMD_TX_START, 1125 BNX2X_F_CMD_SWITCH_UPDATE, 1126 BNX2X_F_CMD_SET_TIMESYNC, 1127 BNX2X_F_CMD_MAX, 1128 }; 1129 1130 struct bnx2x_func_hw_init_params { 1131 /* A load phase returned by MCP. 1132 * 1133 * May be: 1134 * FW_MSG_CODE_DRV_LOAD_COMMON_CHIP 1135 * FW_MSG_CODE_DRV_LOAD_COMMON 1136 * FW_MSG_CODE_DRV_LOAD_PORT 1137 * FW_MSG_CODE_DRV_LOAD_FUNCTION 1138 */ 1139 u32 load_phase; 1140 }; 1141 1142 struct bnx2x_func_hw_reset_params { 1143 /* A load phase returned by MCP. 1144 * 1145 * May be: 1146 * FW_MSG_CODE_DRV_LOAD_COMMON_CHIP 1147 * FW_MSG_CODE_DRV_LOAD_COMMON 1148 * FW_MSG_CODE_DRV_LOAD_PORT 1149 * FW_MSG_CODE_DRV_LOAD_FUNCTION 1150 */ 1151 u32 reset_phase; 1152 }; 1153 1154 struct bnx2x_func_start_params { 1155 /* Multi Function mode: 1156 * - Single Function 1157 * - Switch Dependent 1158 * - Switch Independent 1159 */ 1160 u16 mf_mode; 1161 1162 /* Switch Dependent mode outer VLAN tag */ 1163 u16 sd_vlan_tag; 1164 1165 /* Function cos mode */ 1166 u8 network_cos_mode; 1167 1168 /* TUNN_MODE_NONE/TUNN_MODE_VXLAN/TUNN_MODE_GRE */ 1169 u8 tunnel_mode; 1170 1171 /* tunneling classification enablement */ 1172 u8 tunn_clss_en; 1173 1174 /* NVGRE_TUNNEL/L2GRE_TUNNEL/IPGRE_TUNNEL */ 1175 u8 gre_tunnel_type; 1176 1177 /* Enables Inner GRE RSS on the function, depends on the client RSS 1178 * capailities 1179 */ 1180 u8 inner_gre_rss_en; 1181 }; 1182 1183 struct bnx2x_func_switch_update_params { 1184 unsigned long changes; /* BNX2X_F_UPDATE_XX bits */ 1185 u8 tunnel_mode; 1186 u8 gre_tunnel_type; 1187 }; 1188 1189 struct bnx2x_func_afex_update_params { 1190 u16 vif_id; 1191 u16 afex_default_vlan; 1192 u8 allowed_priorities; 1193 }; 1194 1195 struct bnx2x_func_afex_viflists_params { 1196 u16 vif_list_index; 1197 u8 func_bit_map; 1198 u8 afex_vif_list_command; 1199 u8 func_to_clear; 1200 }; 1201 1202 struct bnx2x_func_tx_start_params { 1203 struct priority_cos traffic_type_to_priority_cos[MAX_TRAFFIC_TYPES]; 1204 u8 dcb_enabled; 1205 u8 dcb_version; 1206 u8 dont_add_pri_0_en; 1207 }; 1208 1209 struct bnx2x_func_set_timesync_params { 1210 /* Reset, set or keep the current drift value */ 1211 u8 drift_adjust_cmd; 1212 1213 /* Dec, inc or keep the current offset */ 1214 u8 offset_cmd; 1215 1216 /* Drift value direction */ 1217 u8 add_sub_drift_adjust_value; 1218 1219 /* Drift, period and offset values to be used according to the commands 1220 * above. 1221 */ 1222 u8 drift_adjust_value; 1223 u32 drift_adjust_period; 1224 u64 offset_delta; 1225 }; 1226 1227 struct bnx2x_func_state_params { 1228 struct bnx2x_func_sp_obj *f_obj; 1229 1230 /* Current command */ 1231 enum bnx2x_func_cmd cmd; 1232 1233 /* may have RAMROD_COMP_WAIT set only */ 1234 unsigned long ramrod_flags; 1235 1236 /* Params according to the current command */ 1237 union { 1238 struct bnx2x_func_hw_init_params hw_init; 1239 struct bnx2x_func_hw_reset_params hw_reset; 1240 struct bnx2x_func_start_params start; 1241 struct bnx2x_func_switch_update_params switch_update; 1242 struct bnx2x_func_afex_update_params afex_update; 1243 struct bnx2x_func_afex_viflists_params afex_viflists; 1244 struct bnx2x_func_tx_start_params tx_start; 1245 struct bnx2x_func_set_timesync_params set_timesync; 1246 } params; 1247 }; 1248 1249 struct bnx2x_func_sp_drv_ops { 1250 /* Init tool + runtime initialization: 1251 * - Common Chip 1252 * - Common (per Path) 1253 * - Port 1254 * - Function phases 1255 */ 1256 int (*init_hw_cmn_chip)(struct bnx2x *bp); 1257 int (*init_hw_cmn)(struct bnx2x *bp); 1258 int (*init_hw_port)(struct bnx2x *bp); 1259 int (*init_hw_func)(struct bnx2x *bp); 1260 1261 /* Reset Function HW: Common, Port, Function phases. */ 1262 void (*reset_hw_cmn)(struct bnx2x *bp); 1263 void (*reset_hw_port)(struct bnx2x *bp); 1264 void (*reset_hw_func)(struct bnx2x *bp); 1265 1266 /* Init/Free GUNZIP resources */ 1267 int (*gunzip_init)(struct bnx2x *bp); 1268 void (*gunzip_end)(struct bnx2x *bp); 1269 1270 /* Prepare/Release FW resources */ 1271 int (*init_fw)(struct bnx2x *bp); 1272 void (*release_fw)(struct bnx2x *bp); 1273 }; 1274 1275 struct bnx2x_func_sp_obj { 1276 enum bnx2x_func_state state, next_state; 1277 1278 /* BNX2X_FUNC_CMD_XX bits. This object implements "one 1279 * pending" paradigm but for debug and tracing purposes it's 1280 * more convenient to have different bits for different 1281 * commands. 1282 */ 1283 unsigned long pending; 1284 1285 /* Buffer to use as a ramrod data and its mapping */ 1286 void *rdata; 1287 dma_addr_t rdata_mapping; 1288 1289 /* Buffer to use as a afex ramrod data and its mapping. 1290 * This can't be same rdata as above because afex ramrod requests 1291 * can arrive to the object in parallel to other ramrod requests. 1292 */ 1293 void *afex_rdata; 1294 dma_addr_t afex_rdata_mapping; 1295 1296 /* this mutex validates that when pending flag is taken, the next 1297 * ramrod to be sent will be the one set the pending bit 1298 */ 1299 struct mutex one_pending_mutex; 1300 1301 /* Driver interface */ 1302 struct bnx2x_func_sp_drv_ops *drv; 1303 1304 /** 1305 * Performs one state change according to the given parameters. 1306 * 1307 * @return 0 in case of success and negative value otherwise. 1308 */ 1309 int (*send_cmd)(struct bnx2x *bp, 1310 struct bnx2x_func_state_params *params); 1311 1312 /** 1313 * Checks that the requested state transition is legal. 1314 */ 1315 int (*check_transition)(struct bnx2x *bp, 1316 struct bnx2x_func_sp_obj *o, 1317 struct bnx2x_func_state_params *params); 1318 1319 /** 1320 * Completes the pending command. 1321 */ 1322 int (*complete_cmd)(struct bnx2x *bp, 1323 struct bnx2x_func_sp_obj *o, 1324 enum bnx2x_func_cmd cmd); 1325 1326 int (*wait_comp)(struct bnx2x *bp, struct bnx2x_func_sp_obj *o, 1327 enum bnx2x_func_cmd cmd); 1328 }; 1329 1330 /********************** Interfaces ********************************************/ 1331 /* Queueable objects set */ 1332 union bnx2x_qable_obj { 1333 struct bnx2x_vlan_mac_obj vlan_mac; 1334 }; 1335 /************** Function state update *********/ 1336 void bnx2x_init_func_obj(struct bnx2x *bp, 1337 struct bnx2x_func_sp_obj *obj, 1338 void *rdata, dma_addr_t rdata_mapping, 1339 void *afex_rdata, dma_addr_t afex_rdata_mapping, 1340 struct bnx2x_func_sp_drv_ops *drv_iface); 1341 1342 int bnx2x_func_state_change(struct bnx2x *bp, 1343 struct bnx2x_func_state_params *params); 1344 1345 enum bnx2x_func_state bnx2x_func_get_state(struct bnx2x *bp, 1346 struct bnx2x_func_sp_obj *o); 1347 /******************* Queue State **************/ 1348 void bnx2x_init_queue_obj(struct bnx2x *bp, 1349 struct bnx2x_queue_sp_obj *obj, u8 cl_id, u32 *cids, 1350 u8 cid_cnt, u8 func_id, void *rdata, 1351 dma_addr_t rdata_mapping, unsigned long type); 1352 1353 int bnx2x_queue_state_change(struct bnx2x *bp, 1354 struct bnx2x_queue_state_params *params); 1355 1356 int bnx2x_get_q_logical_state(struct bnx2x *bp, 1357 struct bnx2x_queue_sp_obj *obj); 1358 1359 /********************* VLAN-MAC ****************/ 1360 void bnx2x_init_mac_obj(struct bnx2x *bp, 1361 struct bnx2x_vlan_mac_obj *mac_obj, 1362 u8 cl_id, u32 cid, u8 func_id, void *rdata, 1363 dma_addr_t rdata_mapping, int state, 1364 unsigned long *pstate, bnx2x_obj_type type, 1365 struct bnx2x_credit_pool_obj *macs_pool); 1366 1367 void bnx2x_init_vlan_obj(struct bnx2x *bp, 1368 struct bnx2x_vlan_mac_obj *vlan_obj, 1369 u8 cl_id, u32 cid, u8 func_id, void *rdata, 1370 dma_addr_t rdata_mapping, int state, 1371 unsigned long *pstate, bnx2x_obj_type type, 1372 struct bnx2x_credit_pool_obj *vlans_pool); 1373 1374 int bnx2x_vlan_mac_h_read_lock(struct bnx2x *bp, 1375 struct bnx2x_vlan_mac_obj *o); 1376 void bnx2x_vlan_mac_h_read_unlock(struct bnx2x *bp, 1377 struct bnx2x_vlan_mac_obj *o); 1378 int bnx2x_vlan_mac_h_write_lock(struct bnx2x *bp, 1379 struct bnx2x_vlan_mac_obj *o); 1380 int bnx2x_config_vlan_mac(struct bnx2x *bp, 1381 struct bnx2x_vlan_mac_ramrod_params *p); 1382 1383 int bnx2x_vlan_mac_move(struct bnx2x *bp, 1384 struct bnx2x_vlan_mac_ramrod_params *p, 1385 struct bnx2x_vlan_mac_obj *dest_o); 1386 1387 /********************* RX MODE ****************/ 1388 1389 void bnx2x_init_rx_mode_obj(struct bnx2x *bp, 1390 struct bnx2x_rx_mode_obj *o); 1391 1392 /** 1393 * bnx2x_config_rx_mode - Send and RX_MODE ramrod according to the provided parameters. 1394 * 1395 * @p: Command parameters 1396 * 1397 * Return: 0 - if operation was successful and there is no pending completions, 1398 * positive number - if there are pending completions, 1399 * negative - if there were errors 1400 */ 1401 int bnx2x_config_rx_mode(struct bnx2x *bp, 1402 struct bnx2x_rx_mode_ramrod_params *p); 1403 1404 /****************** MULTICASTS ****************/ 1405 1406 void bnx2x_init_mcast_obj(struct bnx2x *bp, 1407 struct bnx2x_mcast_obj *mcast_obj, 1408 u8 mcast_cl_id, u32 mcast_cid, u8 func_id, 1409 u8 engine_id, void *rdata, dma_addr_t rdata_mapping, 1410 int state, unsigned long *pstate, 1411 bnx2x_obj_type type); 1412 1413 /** 1414 * bnx2x_config_mcast - Configure multicast MACs list. 1415 * 1416 * @cmd: command to execute: BNX2X_MCAST_CMD_X 1417 * 1418 * May configure a new list 1419 * provided in p->mcast_list (BNX2X_MCAST_CMD_ADD), clean up 1420 * (BNX2X_MCAST_CMD_DEL) or restore (BNX2X_MCAST_CMD_RESTORE) a current 1421 * configuration, continue to execute the pending commands 1422 * (BNX2X_MCAST_CMD_CONT). 1423 * 1424 * If previous command is still pending or if number of MACs to 1425 * configure is more that maximum number of MACs in one command, 1426 * the current command will be enqueued to the tail of the 1427 * pending commands list. 1428 * 1429 * Return: 0 is operation was successful and there are no pending completions, 1430 * negative if there were errors, positive if there are pending 1431 * completions. 1432 */ 1433 int bnx2x_config_mcast(struct bnx2x *bp, 1434 struct bnx2x_mcast_ramrod_params *p, 1435 enum bnx2x_mcast_cmd cmd); 1436 1437 /****************** CREDIT POOL ****************/ 1438 void bnx2x_init_mac_credit_pool(struct bnx2x *bp, 1439 struct bnx2x_credit_pool_obj *p, u8 func_id, 1440 u8 func_num); 1441 void bnx2x_init_vlan_credit_pool(struct bnx2x *bp, 1442 struct bnx2x_credit_pool_obj *p, u8 func_id, 1443 u8 func_num); 1444 1445 /****************** RSS CONFIGURATION ****************/ 1446 void bnx2x_init_rss_config_obj(struct bnx2x *bp, 1447 struct bnx2x_rss_config_obj *rss_obj, 1448 u8 cl_id, u32 cid, u8 func_id, u8 engine_id, 1449 void *rdata, dma_addr_t rdata_mapping, 1450 int state, unsigned long *pstate, 1451 bnx2x_obj_type type); 1452 1453 /** 1454 * bnx2x_config_rss - Updates RSS configuration according to provided parameters 1455 * 1456 * Return: 0 in case of success 1457 */ 1458 int bnx2x_config_rss(struct bnx2x *bp, 1459 struct bnx2x_config_rss_params *p); 1460 1461 /** 1462 * bnx2x_get_rss_ind_table - Return the current ind_table configuration. 1463 * 1464 * @ind_table: buffer to fill with the current indirection 1465 * table content. Should be at least 1466 * T_ETH_INDIRECTION_TABLE_SIZE bytes long. 1467 */ 1468 void bnx2x_get_rss_ind_table(struct bnx2x_rss_config_obj *rss_obj, 1469 u8 *ind_table); 1470 1471 #endif /* BNX2X_SP_VERBS */ 1472