1 /* bnx2x_sp.h: Broadcom Everest network driver. 2 * 3 * Copyright (c) 2011-2013 Broadcom Corporation 4 * 5 * Unless you and Broadcom execute a separate written software license 6 * agreement governing use of this software, this software is licensed to you 7 * under the terms of the GNU General Public License version 2, available 8 * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL"). 9 * 10 * Notwithstanding the above, under no circumstances may you combine this 11 * software in any way with any other Broadcom software provided under a 12 * license other than the GPL, without Broadcom's express prior written 13 * consent. 14 * 15 * Maintained by: Eilon Greenstein <eilong@broadcom.com> 16 * Written by: Vladislav Zolotarov 17 * 18 */ 19 #ifndef BNX2X_SP_VERBS 20 #define BNX2X_SP_VERBS 21 22 struct bnx2x; 23 struct eth_context; 24 25 /* Bits representing general command's configuration */ 26 enum { 27 RAMROD_TX, 28 RAMROD_RX, 29 /* Wait until all pending commands complete */ 30 RAMROD_COMP_WAIT, 31 /* Don't send a ramrod, only update a registry */ 32 RAMROD_DRV_CLR_ONLY, 33 /* Configure HW according to the current object state */ 34 RAMROD_RESTORE, 35 /* Execute the next command now */ 36 RAMROD_EXEC, 37 /* Don't add a new command and continue execution of postponed 38 * commands. If not set a new command will be added to the 39 * pending commands list. 40 */ 41 RAMROD_CONT, 42 /* If there is another pending ramrod, wait until it finishes and 43 * re-try to submit this one. This flag can be set only in sleepable 44 * context, and should not be set from the context that completes the 45 * ramrods as deadlock will occur. 46 */ 47 RAMROD_RETRY, 48 }; 49 50 typedef enum { 51 BNX2X_OBJ_TYPE_RX, 52 BNX2X_OBJ_TYPE_TX, 53 BNX2X_OBJ_TYPE_RX_TX, 54 } bnx2x_obj_type; 55 56 /* Public slow path states */ 57 enum { 58 BNX2X_FILTER_MAC_PENDING, 59 BNX2X_FILTER_VLAN_PENDING, 60 BNX2X_FILTER_VLAN_MAC_PENDING, 61 BNX2X_FILTER_RX_MODE_PENDING, 62 BNX2X_FILTER_RX_MODE_SCHED, 63 BNX2X_FILTER_ISCSI_ETH_START_SCHED, 64 BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, 65 BNX2X_FILTER_FCOE_ETH_START_SCHED, 66 BNX2X_FILTER_FCOE_ETH_STOP_SCHED, 67 BNX2X_FILTER_MCAST_PENDING, 68 BNX2X_FILTER_MCAST_SCHED, 69 BNX2X_FILTER_RSS_CONF_PENDING, 70 BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, 71 BNX2X_AFEX_PENDING_VIFSET_MCP_ACK 72 }; 73 74 struct bnx2x_raw_obj { 75 u8 func_id; 76 77 /* Queue params */ 78 u8 cl_id; 79 u32 cid; 80 81 /* Ramrod data buffer params */ 82 void *rdata; 83 dma_addr_t rdata_mapping; 84 85 /* Ramrod state params */ 86 int state; /* "ramrod is pending" state bit */ 87 unsigned long *pstate; /* pointer to state buffer */ 88 89 bnx2x_obj_type obj_type; 90 91 int (*wait_comp)(struct bnx2x *bp, 92 struct bnx2x_raw_obj *o); 93 94 bool (*check_pending)(struct bnx2x_raw_obj *o); 95 void (*clear_pending)(struct bnx2x_raw_obj *o); 96 void (*set_pending)(struct bnx2x_raw_obj *o); 97 }; 98 99 /************************* VLAN-MAC commands related parameters ***************/ 100 struct bnx2x_mac_ramrod_data { 101 u8 mac[ETH_ALEN]; 102 u8 is_inner_mac; 103 }; 104 105 struct bnx2x_vlan_ramrod_data { 106 u16 vlan; 107 }; 108 109 struct bnx2x_vlan_mac_ramrod_data { 110 u8 mac[ETH_ALEN]; 111 u8 is_inner_mac; 112 u16 vlan; 113 }; 114 115 union bnx2x_classification_ramrod_data { 116 struct bnx2x_mac_ramrod_data mac; 117 struct bnx2x_vlan_ramrod_data vlan; 118 struct bnx2x_vlan_mac_ramrod_data vlan_mac; 119 }; 120 121 /* VLAN_MAC commands */ 122 enum bnx2x_vlan_mac_cmd { 123 BNX2X_VLAN_MAC_ADD, 124 BNX2X_VLAN_MAC_DEL, 125 BNX2X_VLAN_MAC_MOVE, 126 }; 127 128 struct bnx2x_vlan_mac_data { 129 /* Requested command: BNX2X_VLAN_MAC_XX */ 130 enum bnx2x_vlan_mac_cmd cmd; 131 /* used to contain the data related vlan_mac_flags bits from 132 * ramrod parameters. 133 */ 134 unsigned long vlan_mac_flags; 135 136 /* Needed for MOVE command */ 137 struct bnx2x_vlan_mac_obj *target_obj; 138 139 union bnx2x_classification_ramrod_data u; 140 }; 141 142 /*************************** Exe Queue obj ************************************/ 143 union bnx2x_exe_queue_cmd_data { 144 struct bnx2x_vlan_mac_data vlan_mac; 145 146 struct { 147 /* TODO */ 148 } mcast; 149 }; 150 151 struct bnx2x_exeq_elem { 152 struct list_head link; 153 154 /* Length of this element in the exe_chunk. */ 155 int cmd_len; 156 157 union bnx2x_exe_queue_cmd_data cmd_data; 158 }; 159 160 union bnx2x_qable_obj; 161 162 union bnx2x_exeq_comp_elem { 163 union event_ring_elem *elem; 164 }; 165 166 struct bnx2x_exe_queue_obj; 167 168 typedef int (*exe_q_validate)(struct bnx2x *bp, 169 union bnx2x_qable_obj *o, 170 struct bnx2x_exeq_elem *elem); 171 172 typedef int (*exe_q_remove)(struct bnx2x *bp, 173 union bnx2x_qable_obj *o, 174 struct bnx2x_exeq_elem *elem); 175 176 /* Return positive if entry was optimized, 0 - if not, negative 177 * in case of an error. 178 */ 179 typedef int (*exe_q_optimize)(struct bnx2x *bp, 180 union bnx2x_qable_obj *o, 181 struct bnx2x_exeq_elem *elem); 182 typedef int (*exe_q_execute)(struct bnx2x *bp, 183 union bnx2x_qable_obj *o, 184 struct list_head *exe_chunk, 185 unsigned long *ramrod_flags); 186 typedef struct bnx2x_exeq_elem * 187 (*exe_q_get)(struct bnx2x_exe_queue_obj *o, 188 struct bnx2x_exeq_elem *elem); 189 190 struct bnx2x_exe_queue_obj { 191 /* Commands pending for an execution. */ 192 struct list_head exe_queue; 193 194 /* Commands pending for an completion. */ 195 struct list_head pending_comp; 196 197 spinlock_t lock; 198 199 /* Maximum length of commands' list for one execution */ 200 int exe_chunk_len; 201 202 union bnx2x_qable_obj *owner; 203 204 /****** Virtual functions ******/ 205 /** 206 * Called before commands execution for commands that are really 207 * going to be executed (after 'optimize'). 208 * 209 * Must run under exe_queue->lock 210 */ 211 exe_q_validate validate; 212 213 /** 214 * Called before removing pending commands, cleaning allocated 215 * resources (e.g., credits from validate) 216 */ 217 exe_q_remove remove; 218 219 /** 220 * This will try to cancel the current pending commands list 221 * considering the new command. 222 * 223 * Returns the number of optimized commands or a negative error code 224 * 225 * Must run under exe_queue->lock 226 */ 227 exe_q_optimize optimize; 228 229 /** 230 * Run the next commands chunk (owner specific). 231 */ 232 exe_q_execute execute; 233 234 /** 235 * Return the exe_queue element containing the specific command 236 * if any. Otherwise return NULL. 237 */ 238 exe_q_get get; 239 }; 240 /***************** Classification verbs: Set/Del MAC/VLAN/VLAN-MAC ************/ 241 /* 242 * Element in the VLAN_MAC registry list having all currently configured 243 * rules. 244 */ 245 struct bnx2x_vlan_mac_registry_elem { 246 struct list_head link; 247 248 /* Used to store the cam offset used for the mac/vlan/vlan-mac. 249 * Relevant for 57710 and 57711 only. VLANs and MACs share the 250 * same CAM for these chips. 251 */ 252 int cam_offset; 253 254 /* Needed for DEL and RESTORE flows */ 255 unsigned long vlan_mac_flags; 256 257 union bnx2x_classification_ramrod_data u; 258 }; 259 260 /* Bits representing VLAN_MAC commands specific flags */ 261 enum { 262 BNX2X_UC_LIST_MAC, 263 BNX2X_ETH_MAC, 264 BNX2X_ISCSI_ETH_MAC, 265 BNX2X_NETQ_ETH_MAC, 266 BNX2X_DONT_CONSUME_CAM_CREDIT, 267 BNX2X_DONT_CONSUME_CAM_CREDIT_DEST, 268 }; 269 270 struct bnx2x_vlan_mac_ramrod_params { 271 /* Object to run the command from */ 272 struct bnx2x_vlan_mac_obj *vlan_mac_obj; 273 274 /* General command flags: COMP_WAIT, etc. */ 275 unsigned long ramrod_flags; 276 277 /* Command specific configuration request */ 278 struct bnx2x_vlan_mac_data user_req; 279 }; 280 281 struct bnx2x_vlan_mac_obj { 282 struct bnx2x_raw_obj raw; 283 284 /* Bookkeeping list: will prevent the addition of already existing 285 * entries. 286 */ 287 struct list_head head; 288 /* Implement a simple reader/writer lock on the head list. 289 * all these fields should only be accessed under the exe_queue lock 290 */ 291 u8 head_reader; /* Num. of readers accessing head list */ 292 bool head_exe_request; /* Pending execution request. */ 293 unsigned long saved_ramrod_flags; /* Ramrods of pending execution */ 294 295 /* TODO: Add it's initialization in the init functions */ 296 struct bnx2x_exe_queue_obj exe_queue; 297 298 /* MACs credit pool */ 299 struct bnx2x_credit_pool_obj *macs_pool; 300 301 /* VLANs credit pool */ 302 struct bnx2x_credit_pool_obj *vlans_pool; 303 304 /* RAMROD command to be used */ 305 int ramrod_cmd; 306 307 /* copy first n elements onto preallocated buffer 308 * 309 * @param n number of elements to get 310 * @param buf buffer preallocated by caller into which elements 311 * will be copied. Note elements are 4-byte aligned 312 * so buffer size must be able to accommodate the 313 * aligned elements. 314 * 315 * @return number of copied bytes 316 */ 317 int (*get_n_elements)(struct bnx2x *bp, 318 struct bnx2x_vlan_mac_obj *o, int n, u8 *base, 319 u8 stride, u8 size); 320 321 /** 322 * Checks if ADD-ramrod with the given params may be performed. 323 * 324 * @return zero if the element may be added 325 */ 326 327 int (*check_add)(struct bnx2x *bp, 328 struct bnx2x_vlan_mac_obj *o, 329 union bnx2x_classification_ramrod_data *data); 330 331 /** 332 * Checks if DEL-ramrod with the given params may be performed. 333 * 334 * @return true if the element may be deleted 335 */ 336 struct bnx2x_vlan_mac_registry_elem * 337 (*check_del)(struct bnx2x *bp, 338 struct bnx2x_vlan_mac_obj *o, 339 union bnx2x_classification_ramrod_data *data); 340 341 /** 342 * Checks if DEL-ramrod with the given params may be performed. 343 * 344 * @return true if the element may be deleted 345 */ 346 bool (*check_move)(struct bnx2x *bp, 347 struct bnx2x_vlan_mac_obj *src_o, 348 struct bnx2x_vlan_mac_obj *dst_o, 349 union bnx2x_classification_ramrod_data *data); 350 351 /** 352 * Update the relevant credit object(s) (consume/return 353 * correspondingly). 354 */ 355 bool (*get_credit)(struct bnx2x_vlan_mac_obj *o); 356 bool (*put_credit)(struct bnx2x_vlan_mac_obj *o); 357 bool (*get_cam_offset)(struct bnx2x_vlan_mac_obj *o, int *offset); 358 bool (*put_cam_offset)(struct bnx2x_vlan_mac_obj *o, int offset); 359 360 /** 361 * Configures one rule in the ramrod data buffer. 362 */ 363 void (*set_one_rule)(struct bnx2x *bp, 364 struct bnx2x_vlan_mac_obj *o, 365 struct bnx2x_exeq_elem *elem, int rule_idx, 366 int cam_offset); 367 368 /** 369 * Delete all configured elements having the given 370 * vlan_mac_flags specification. Assumes no pending for 371 * execution commands. Will schedule all all currently 372 * configured MACs/VLANs/VLAN-MACs matching the vlan_mac_flags 373 * specification for deletion and will use the given 374 * ramrod_flags for the last DEL operation. 375 * 376 * @param bp 377 * @param o 378 * @param ramrod_flags RAMROD_XX flags 379 * 380 * @return 0 if the last operation has completed successfully 381 * and there are no more elements left, positive value 382 * if there are pending for completion commands, 383 * negative value in case of failure. 384 */ 385 int (*delete_all)(struct bnx2x *bp, 386 struct bnx2x_vlan_mac_obj *o, 387 unsigned long *vlan_mac_flags, 388 unsigned long *ramrod_flags); 389 390 /** 391 * Reconfigures the next MAC/VLAN/VLAN-MAC element from the previously 392 * configured elements list. 393 * 394 * @param bp 395 * @param p Command parameters (RAMROD_COMP_WAIT bit in 396 * ramrod_flags is only taken into an account) 397 * @param ppos a pointer to the cookie that should be given back in the 398 * next call to make function handle the next element. If 399 * *ppos is set to NULL it will restart the iterator. 400 * If returned *ppos == NULL this means that the last 401 * element has been handled. 402 * 403 * @return int 404 */ 405 int (*restore)(struct bnx2x *bp, 406 struct bnx2x_vlan_mac_ramrod_params *p, 407 struct bnx2x_vlan_mac_registry_elem **ppos); 408 409 /** 410 * Should be called on a completion arrival. 411 * 412 * @param bp 413 * @param o 414 * @param cqe Completion element we are handling 415 * @param ramrod_flags if RAMROD_CONT is set the next bulk of 416 * pending commands will be executed. 417 * RAMROD_DRV_CLR_ONLY and RAMROD_RESTORE 418 * may also be set if needed. 419 * 420 * @return 0 if there are neither pending nor waiting for 421 * completion commands. Positive value if there are 422 * pending for execution or for completion commands. 423 * Negative value in case of an error (including an 424 * error in the cqe). 425 */ 426 int (*complete)(struct bnx2x *bp, struct bnx2x_vlan_mac_obj *o, 427 union event_ring_elem *cqe, 428 unsigned long *ramrod_flags); 429 430 /** 431 * Wait for completion of all commands. Don't schedule new ones, 432 * just wait. It assumes that the completion code will schedule 433 * for new commands. 434 */ 435 int (*wait)(struct bnx2x *bp, struct bnx2x_vlan_mac_obj *o); 436 }; 437 438 enum { 439 BNX2X_LLH_CAM_ISCSI_ETH_LINE = 0, 440 BNX2X_LLH_CAM_ETH_LINE, 441 BNX2X_LLH_CAM_MAX_PF_LINE = NIG_REG_LLH1_FUNC_MEM_SIZE / 2 442 }; 443 444 void bnx2x_set_mac_in_nig(struct bnx2x *bp, 445 bool add, unsigned char *dev_addr, int index); 446 447 /** RX_MODE verbs:DROP_ALL/ACCEPT_ALL/ACCEPT_ALL_MULTI/ACCEPT_ALL_VLAN/NORMAL */ 448 449 /* RX_MODE ramrod special flags: set in rx_mode_flags field in 450 * a bnx2x_rx_mode_ramrod_params. 451 */ 452 enum { 453 BNX2X_RX_MODE_FCOE_ETH, 454 BNX2X_RX_MODE_ISCSI_ETH, 455 }; 456 457 enum { 458 BNX2X_ACCEPT_UNICAST, 459 BNX2X_ACCEPT_MULTICAST, 460 BNX2X_ACCEPT_ALL_UNICAST, 461 BNX2X_ACCEPT_ALL_MULTICAST, 462 BNX2X_ACCEPT_BROADCAST, 463 BNX2X_ACCEPT_UNMATCHED, 464 BNX2X_ACCEPT_ANY_VLAN 465 }; 466 467 struct bnx2x_rx_mode_ramrod_params { 468 struct bnx2x_rx_mode_obj *rx_mode_obj; 469 unsigned long *pstate; 470 int state; 471 u8 cl_id; 472 u32 cid; 473 u8 func_id; 474 unsigned long ramrod_flags; 475 unsigned long rx_mode_flags; 476 477 /* rdata is either a pointer to eth_filter_rules_ramrod_data(e2) or to 478 * a tstorm_eth_mac_filter_config (e1x). 479 */ 480 void *rdata; 481 dma_addr_t rdata_mapping; 482 483 /* Rx mode settings */ 484 unsigned long rx_accept_flags; 485 486 /* internal switching settings */ 487 unsigned long tx_accept_flags; 488 }; 489 490 struct bnx2x_rx_mode_obj { 491 int (*config_rx_mode)(struct bnx2x *bp, 492 struct bnx2x_rx_mode_ramrod_params *p); 493 494 int (*wait_comp)(struct bnx2x *bp, 495 struct bnx2x_rx_mode_ramrod_params *p); 496 }; 497 498 /********************** Set multicast group ***********************************/ 499 500 struct bnx2x_mcast_list_elem { 501 struct list_head link; 502 u8 *mac; 503 }; 504 505 union bnx2x_mcast_config_data { 506 u8 *mac; 507 u8 bin; /* used in a RESTORE flow */ 508 }; 509 510 struct bnx2x_mcast_ramrod_params { 511 struct bnx2x_mcast_obj *mcast_obj; 512 513 /* Relevant options are RAMROD_COMP_WAIT and RAMROD_DRV_CLR_ONLY */ 514 unsigned long ramrod_flags; 515 516 struct list_head mcast_list; /* list of struct bnx2x_mcast_list_elem */ 517 /** TODO: 518 * - rename it to macs_num. 519 * - Add a new command type for handling pending commands 520 * (remove "zero semantics"). 521 * 522 * Length of mcast_list. If zero and ADD_CONT command - post 523 * pending commands. 524 */ 525 int mcast_list_len; 526 }; 527 528 enum bnx2x_mcast_cmd { 529 BNX2X_MCAST_CMD_ADD, 530 BNX2X_MCAST_CMD_CONT, 531 BNX2X_MCAST_CMD_DEL, 532 BNX2X_MCAST_CMD_RESTORE, 533 }; 534 535 struct bnx2x_mcast_obj { 536 struct bnx2x_raw_obj raw; 537 538 union { 539 struct { 540 #define BNX2X_MCAST_BINS_NUM 256 541 #define BNX2X_MCAST_VEC_SZ (BNX2X_MCAST_BINS_NUM / 64) 542 u64 vec[BNX2X_MCAST_VEC_SZ]; 543 544 /** Number of BINs to clear. Should be updated 545 * immediately when a command arrives in order to 546 * properly create DEL commands. 547 */ 548 int num_bins_set; 549 } aprox_match; 550 551 struct { 552 struct list_head macs; 553 int num_macs_set; 554 } exact_match; 555 } registry; 556 557 /* Pending commands */ 558 struct list_head pending_cmds_head; 559 560 /* A state that is set in raw.pstate, when there are pending commands */ 561 int sched_state; 562 563 /* Maximal number of mcast MACs configured in one command */ 564 int max_cmd_len; 565 566 /* Total number of currently pending MACs to configure: both 567 * in the pending commands list and in the current command. 568 */ 569 int total_pending_num; 570 571 u8 engine_id; 572 573 /** 574 * @param cmd command to execute (BNX2X_MCAST_CMD_X, see above) 575 */ 576 int (*config_mcast)(struct bnx2x *bp, 577 struct bnx2x_mcast_ramrod_params *p, 578 enum bnx2x_mcast_cmd cmd); 579 580 /** 581 * Fills the ramrod data during the RESTORE flow. 582 * 583 * @param bp 584 * @param o 585 * @param start_idx Registry index to start from 586 * @param rdata_idx Index in the ramrod data to start from 587 * 588 * @return -1 if we handled the whole registry or index of the last 589 * handled registry element. 590 */ 591 int (*hdl_restore)(struct bnx2x *bp, struct bnx2x_mcast_obj *o, 592 int start_bin, int *rdata_idx); 593 594 int (*enqueue_cmd)(struct bnx2x *bp, struct bnx2x_mcast_obj *o, 595 struct bnx2x_mcast_ramrod_params *p, 596 enum bnx2x_mcast_cmd cmd); 597 598 void (*set_one_rule)(struct bnx2x *bp, 599 struct bnx2x_mcast_obj *o, int idx, 600 union bnx2x_mcast_config_data *cfg_data, 601 enum bnx2x_mcast_cmd cmd); 602 603 /** Checks if there are more mcast MACs to be set or a previous 604 * command is still pending. 605 */ 606 bool (*check_pending)(struct bnx2x_mcast_obj *o); 607 608 /** 609 * Set/Clear/Check SCHEDULED state of the object 610 */ 611 void (*set_sched)(struct bnx2x_mcast_obj *o); 612 void (*clear_sched)(struct bnx2x_mcast_obj *o); 613 bool (*check_sched)(struct bnx2x_mcast_obj *o); 614 615 /* Wait until all pending commands complete */ 616 int (*wait_comp)(struct bnx2x *bp, struct bnx2x_mcast_obj *o); 617 618 /** 619 * Handle the internal object counters needed for proper 620 * commands handling. Checks that the provided parameters are 621 * feasible. 622 */ 623 int (*validate)(struct bnx2x *bp, 624 struct bnx2x_mcast_ramrod_params *p, 625 enum bnx2x_mcast_cmd cmd); 626 627 /** 628 * Restore the values of internal counters in case of a failure. 629 */ 630 void (*revert)(struct bnx2x *bp, 631 struct bnx2x_mcast_ramrod_params *p, 632 int old_num_bins); 633 634 int (*get_registry_size)(struct bnx2x_mcast_obj *o); 635 void (*set_registry_size)(struct bnx2x_mcast_obj *o, int n); 636 }; 637 638 /*************************** Credit handling **********************************/ 639 struct bnx2x_credit_pool_obj { 640 641 /* Current amount of credit in the pool */ 642 atomic_t credit; 643 644 /* Maximum allowed credit. put() will check against it. */ 645 int pool_sz; 646 647 /* Allocate a pool table statically. 648 * 649 * Currently the maximum allowed size is MAX_MAC_CREDIT_E2(272) 650 * 651 * The set bit in the table will mean that the entry is available. 652 */ 653 #define BNX2X_POOL_VEC_SIZE (MAX_MAC_CREDIT_E2 / 64) 654 u64 pool_mirror[BNX2X_POOL_VEC_SIZE]; 655 656 /* Base pool offset (initialized differently */ 657 int base_pool_offset; 658 659 /** 660 * Get the next free pool entry. 661 * 662 * @return true if there was a free entry in the pool 663 */ 664 bool (*get_entry)(struct bnx2x_credit_pool_obj *o, int *entry); 665 666 /** 667 * Return the entry back to the pool. 668 * 669 * @return true if entry is legal and has been successfully 670 * returned to the pool. 671 */ 672 bool (*put_entry)(struct bnx2x_credit_pool_obj *o, int entry); 673 674 /** 675 * Get the requested amount of credit from the pool. 676 * 677 * @param cnt Amount of requested credit 678 * @return true if the operation is successful 679 */ 680 bool (*get)(struct bnx2x_credit_pool_obj *o, int cnt); 681 682 /** 683 * Returns the credit to the pool. 684 * 685 * @param cnt Amount of credit to return 686 * @return true if the operation is successful 687 */ 688 bool (*put)(struct bnx2x_credit_pool_obj *o, int cnt); 689 690 /** 691 * Reads the current amount of credit. 692 */ 693 int (*check)(struct bnx2x_credit_pool_obj *o); 694 }; 695 696 /*************************** RSS configuration ********************************/ 697 enum { 698 /* RSS_MODE bits are mutually exclusive */ 699 BNX2X_RSS_MODE_DISABLED, 700 BNX2X_RSS_MODE_REGULAR, 701 702 BNX2X_RSS_SET_SRCH, /* Setup searcher, E1x specific flag */ 703 704 BNX2X_RSS_IPV4, 705 BNX2X_RSS_IPV4_TCP, 706 BNX2X_RSS_IPV4_UDP, 707 BNX2X_RSS_IPV6, 708 BNX2X_RSS_IPV6_TCP, 709 BNX2X_RSS_IPV6_UDP, 710 }; 711 712 struct bnx2x_config_rss_params { 713 struct bnx2x_rss_config_obj *rss_obj; 714 715 /* may have RAMROD_COMP_WAIT set only */ 716 unsigned long ramrod_flags; 717 718 /* BNX2X_RSS_X bits */ 719 unsigned long rss_flags; 720 721 /* Number hash bits to take into an account */ 722 u8 rss_result_mask; 723 724 /* Indirection table */ 725 u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE]; 726 727 /* RSS hash values */ 728 u32 rss_key[10]; 729 730 /* valid only iff BNX2X_RSS_UPDATE_TOE is set */ 731 u16 toe_rss_bitmap; 732 }; 733 734 struct bnx2x_rss_config_obj { 735 struct bnx2x_raw_obj raw; 736 737 /* RSS engine to use */ 738 u8 engine_id; 739 740 /* Last configured indirection table */ 741 u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE]; 742 743 /* flags for enabling 4-tupple hash on UDP */ 744 u8 udp_rss_v4; 745 u8 udp_rss_v6; 746 747 int (*config_rss)(struct bnx2x *bp, 748 struct bnx2x_config_rss_params *p); 749 }; 750 751 /*********************** Queue state update ***********************************/ 752 753 /* UPDATE command options */ 754 enum { 755 BNX2X_Q_UPDATE_IN_VLAN_REM, 756 BNX2X_Q_UPDATE_IN_VLAN_REM_CHNG, 757 BNX2X_Q_UPDATE_OUT_VLAN_REM, 758 BNX2X_Q_UPDATE_OUT_VLAN_REM_CHNG, 759 BNX2X_Q_UPDATE_ANTI_SPOOF, 760 BNX2X_Q_UPDATE_ANTI_SPOOF_CHNG, 761 BNX2X_Q_UPDATE_ACTIVATE, 762 BNX2X_Q_UPDATE_ACTIVATE_CHNG, 763 BNX2X_Q_UPDATE_DEF_VLAN_EN, 764 BNX2X_Q_UPDATE_DEF_VLAN_EN_CHNG, 765 BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG, 766 BNX2X_Q_UPDATE_SILENT_VLAN_REM 767 }; 768 769 /* Allowed Queue states */ 770 enum bnx2x_q_state { 771 BNX2X_Q_STATE_RESET, 772 BNX2X_Q_STATE_INITIALIZED, 773 BNX2X_Q_STATE_ACTIVE, 774 BNX2X_Q_STATE_MULTI_COS, 775 BNX2X_Q_STATE_MCOS_TERMINATED, 776 BNX2X_Q_STATE_INACTIVE, 777 BNX2X_Q_STATE_STOPPED, 778 BNX2X_Q_STATE_TERMINATED, 779 BNX2X_Q_STATE_FLRED, 780 BNX2X_Q_STATE_MAX, 781 }; 782 783 /* Allowed Queue states */ 784 enum bnx2x_q_logical_state { 785 BNX2X_Q_LOGICAL_STATE_ACTIVE, 786 BNX2X_Q_LOGICAL_STATE_STOPPED, 787 }; 788 789 /* Allowed commands */ 790 enum bnx2x_queue_cmd { 791 BNX2X_Q_CMD_INIT, 792 BNX2X_Q_CMD_SETUP, 793 BNX2X_Q_CMD_SETUP_TX_ONLY, 794 BNX2X_Q_CMD_DEACTIVATE, 795 BNX2X_Q_CMD_ACTIVATE, 796 BNX2X_Q_CMD_UPDATE, 797 BNX2X_Q_CMD_UPDATE_TPA, 798 BNX2X_Q_CMD_HALT, 799 BNX2X_Q_CMD_CFC_DEL, 800 BNX2X_Q_CMD_TERMINATE, 801 BNX2X_Q_CMD_EMPTY, 802 BNX2X_Q_CMD_MAX, 803 }; 804 805 /* queue SETUP + INIT flags */ 806 enum { 807 BNX2X_Q_FLG_TPA, 808 BNX2X_Q_FLG_TPA_IPV6, 809 BNX2X_Q_FLG_TPA_GRO, 810 BNX2X_Q_FLG_STATS, 811 BNX2X_Q_FLG_ZERO_STATS, 812 BNX2X_Q_FLG_ACTIVE, 813 BNX2X_Q_FLG_OV, 814 BNX2X_Q_FLG_VLAN, 815 BNX2X_Q_FLG_COS, 816 BNX2X_Q_FLG_HC, 817 BNX2X_Q_FLG_HC_EN, 818 BNX2X_Q_FLG_DHC, 819 BNX2X_Q_FLG_FCOE, 820 BNX2X_Q_FLG_LEADING_RSS, 821 BNX2X_Q_FLG_MCAST, 822 BNX2X_Q_FLG_DEF_VLAN, 823 BNX2X_Q_FLG_TX_SWITCH, 824 BNX2X_Q_FLG_TX_SEC, 825 BNX2X_Q_FLG_ANTI_SPOOF, 826 BNX2X_Q_FLG_SILENT_VLAN_REM, 827 BNX2X_Q_FLG_FORCE_DEFAULT_PRI, 828 BNX2X_Q_FLG_PCSUM_ON_PKT, 829 BNX2X_Q_FLG_TUN_INC_INNER_IP_ID 830 }; 831 832 /* Queue type options: queue type may be a combination of below. */ 833 enum bnx2x_q_type { 834 /** TODO: Consider moving both these flags into the init() 835 * ramrod params. 836 */ 837 BNX2X_Q_TYPE_HAS_RX, 838 BNX2X_Q_TYPE_HAS_TX, 839 }; 840 841 #define BNX2X_PRIMARY_CID_INDEX 0 842 #define BNX2X_MULTI_TX_COS_E1X 3 /* QM only */ 843 #define BNX2X_MULTI_TX_COS_E2_E3A0 2 844 #define BNX2X_MULTI_TX_COS_E3B0 3 845 #define BNX2X_MULTI_TX_COS 3 /* Maximum possible */ 846 847 #define MAC_PAD (ALIGN(ETH_ALEN, sizeof(u32)) - ETH_ALEN) 848 849 struct bnx2x_queue_init_params { 850 struct { 851 unsigned long flags; 852 u16 hc_rate; 853 u8 fw_sb_id; 854 u8 sb_cq_index; 855 } tx; 856 857 struct { 858 unsigned long flags; 859 u16 hc_rate; 860 u8 fw_sb_id; 861 u8 sb_cq_index; 862 } rx; 863 864 /* CID context in the host memory */ 865 struct eth_context *cxts[BNX2X_MULTI_TX_COS]; 866 867 /* maximum number of cos supported by hardware */ 868 u8 max_cos; 869 }; 870 871 struct bnx2x_queue_terminate_params { 872 /* index within the tx_only cids of this queue object */ 873 u8 cid_index; 874 }; 875 876 struct bnx2x_queue_cfc_del_params { 877 /* index within the tx_only cids of this queue object */ 878 u8 cid_index; 879 }; 880 881 struct bnx2x_queue_update_params { 882 unsigned long update_flags; /* BNX2X_Q_UPDATE_XX bits */ 883 u16 def_vlan; 884 u16 silent_removal_value; 885 u16 silent_removal_mask; 886 /* index within the tx_only cids of this queue object */ 887 u8 cid_index; 888 }; 889 890 struct rxq_pause_params { 891 u16 bd_th_lo; 892 u16 bd_th_hi; 893 u16 rcq_th_lo; 894 u16 rcq_th_hi; 895 u16 sge_th_lo; /* valid iff BNX2X_Q_FLG_TPA */ 896 u16 sge_th_hi; /* valid iff BNX2X_Q_FLG_TPA */ 897 u16 pri_map; 898 }; 899 900 /* general */ 901 struct bnx2x_general_setup_params { 902 /* valid iff BNX2X_Q_FLG_STATS */ 903 u8 stat_id; 904 905 u8 spcl_id; 906 u16 mtu; 907 u8 cos; 908 }; 909 910 struct bnx2x_rxq_setup_params { 911 /* dma */ 912 dma_addr_t dscr_map; 913 dma_addr_t sge_map; 914 dma_addr_t rcq_map; 915 dma_addr_t rcq_np_map; 916 917 u16 drop_flags; 918 u16 buf_sz; 919 u8 fw_sb_id; 920 u8 cl_qzone_id; 921 922 /* valid iff BNX2X_Q_FLG_TPA */ 923 u16 tpa_agg_sz; 924 u16 sge_buf_sz; 925 u8 max_sges_pkt; 926 u8 max_tpa_queues; 927 u8 rss_engine_id; 928 929 /* valid iff BNX2X_Q_FLG_MCAST */ 930 u8 mcast_engine_id; 931 932 u8 cache_line_log; 933 934 u8 sb_cq_index; 935 936 /* valid iff BXN2X_Q_FLG_SILENT_VLAN_REM */ 937 u16 silent_removal_value; 938 u16 silent_removal_mask; 939 }; 940 941 struct bnx2x_txq_setup_params { 942 /* dma */ 943 dma_addr_t dscr_map; 944 945 u8 fw_sb_id; 946 u8 sb_cq_index; 947 u8 cos; /* valid iff BNX2X_Q_FLG_COS */ 948 u16 traffic_type; 949 /* equals to the leading rss client id, used for TX classification*/ 950 u8 tss_leading_cl_id; 951 952 /* valid iff BNX2X_Q_FLG_DEF_VLAN */ 953 u16 default_vlan; 954 }; 955 956 struct bnx2x_queue_setup_params { 957 struct bnx2x_general_setup_params gen_params; 958 struct bnx2x_txq_setup_params txq_params; 959 struct bnx2x_rxq_setup_params rxq_params; 960 struct rxq_pause_params pause_params; 961 unsigned long flags; 962 }; 963 964 struct bnx2x_queue_setup_tx_only_params { 965 struct bnx2x_general_setup_params gen_params; 966 struct bnx2x_txq_setup_params txq_params; 967 unsigned long flags; 968 /* index within the tx_only cids of this queue object */ 969 u8 cid_index; 970 }; 971 972 struct bnx2x_queue_state_params { 973 struct bnx2x_queue_sp_obj *q_obj; 974 975 /* Current command */ 976 enum bnx2x_queue_cmd cmd; 977 978 /* may have RAMROD_COMP_WAIT set only */ 979 unsigned long ramrod_flags; 980 981 /* Params according to the current command */ 982 union { 983 struct bnx2x_queue_update_params update; 984 struct bnx2x_queue_setup_params setup; 985 struct bnx2x_queue_init_params init; 986 struct bnx2x_queue_setup_tx_only_params tx_only; 987 struct bnx2x_queue_terminate_params terminate; 988 struct bnx2x_queue_cfc_del_params cfc_del; 989 } params; 990 }; 991 992 struct bnx2x_viflist_params { 993 u8 echo_res; 994 u8 func_bit_map_res; 995 }; 996 997 struct bnx2x_queue_sp_obj { 998 u32 cids[BNX2X_MULTI_TX_COS]; 999 u8 cl_id; 1000 u8 func_id; 1001 1002 /* number of traffic classes supported by queue. 1003 * The primary connection of the queue supports the first traffic 1004 * class. Any further traffic class is supported by a tx-only 1005 * connection. 1006 * 1007 * Therefore max_cos is also a number of valid entries in the cids 1008 * array. 1009 */ 1010 u8 max_cos; 1011 u8 num_tx_only, next_tx_only; 1012 1013 enum bnx2x_q_state state, next_state; 1014 1015 /* bits from enum bnx2x_q_type */ 1016 unsigned long type; 1017 1018 /* BNX2X_Q_CMD_XX bits. This object implements "one 1019 * pending" paradigm but for debug and tracing purposes it's 1020 * more convenient to have different bits for different 1021 * commands. 1022 */ 1023 unsigned long pending; 1024 1025 /* Buffer to use as a ramrod data and its mapping */ 1026 void *rdata; 1027 dma_addr_t rdata_mapping; 1028 1029 /** 1030 * Performs one state change according to the given parameters. 1031 * 1032 * @return 0 in case of success and negative value otherwise. 1033 */ 1034 int (*send_cmd)(struct bnx2x *bp, 1035 struct bnx2x_queue_state_params *params); 1036 1037 /** 1038 * Sets the pending bit according to the requested transition. 1039 */ 1040 int (*set_pending)(struct bnx2x_queue_sp_obj *o, 1041 struct bnx2x_queue_state_params *params); 1042 1043 /** 1044 * Checks that the requested state transition is legal. 1045 */ 1046 int (*check_transition)(struct bnx2x *bp, 1047 struct bnx2x_queue_sp_obj *o, 1048 struct bnx2x_queue_state_params *params); 1049 1050 /** 1051 * Completes the pending command. 1052 */ 1053 int (*complete_cmd)(struct bnx2x *bp, 1054 struct bnx2x_queue_sp_obj *o, 1055 enum bnx2x_queue_cmd); 1056 1057 int (*wait_comp)(struct bnx2x *bp, 1058 struct bnx2x_queue_sp_obj *o, 1059 enum bnx2x_queue_cmd cmd); 1060 }; 1061 1062 /********************** Function state update *********************************/ 1063 /* Allowed Function states */ 1064 enum bnx2x_func_state { 1065 BNX2X_F_STATE_RESET, 1066 BNX2X_F_STATE_INITIALIZED, 1067 BNX2X_F_STATE_STARTED, 1068 BNX2X_F_STATE_TX_STOPPED, 1069 BNX2X_F_STATE_MAX, 1070 }; 1071 1072 /* Allowed Function commands */ 1073 enum bnx2x_func_cmd { 1074 BNX2X_F_CMD_HW_INIT, 1075 BNX2X_F_CMD_START, 1076 BNX2X_F_CMD_STOP, 1077 BNX2X_F_CMD_HW_RESET, 1078 BNX2X_F_CMD_AFEX_UPDATE, 1079 BNX2X_F_CMD_AFEX_VIFLISTS, 1080 BNX2X_F_CMD_TX_STOP, 1081 BNX2X_F_CMD_TX_START, 1082 BNX2X_F_CMD_SWITCH_UPDATE, 1083 BNX2X_F_CMD_MAX, 1084 }; 1085 1086 struct bnx2x_func_hw_init_params { 1087 /* A load phase returned by MCP. 1088 * 1089 * May be: 1090 * FW_MSG_CODE_DRV_LOAD_COMMON_CHIP 1091 * FW_MSG_CODE_DRV_LOAD_COMMON 1092 * FW_MSG_CODE_DRV_LOAD_PORT 1093 * FW_MSG_CODE_DRV_LOAD_FUNCTION 1094 */ 1095 u32 load_phase; 1096 }; 1097 1098 struct bnx2x_func_hw_reset_params { 1099 /* A load phase returned by MCP. 1100 * 1101 * May be: 1102 * FW_MSG_CODE_DRV_LOAD_COMMON_CHIP 1103 * FW_MSG_CODE_DRV_LOAD_COMMON 1104 * FW_MSG_CODE_DRV_LOAD_PORT 1105 * FW_MSG_CODE_DRV_LOAD_FUNCTION 1106 */ 1107 u32 reset_phase; 1108 }; 1109 1110 struct bnx2x_func_start_params { 1111 /* Multi Function mode: 1112 * - Single Function 1113 * - Switch Dependent 1114 * - Switch Independent 1115 */ 1116 u16 mf_mode; 1117 1118 /* Switch Dependent mode outer VLAN tag */ 1119 u16 sd_vlan_tag; 1120 1121 /* Function cos mode */ 1122 u8 network_cos_mode; 1123 1124 /* NVGRE classification enablement */ 1125 u8 nvgre_clss_en; 1126 1127 /* NO_GRE_TUNNEL/NVGRE_TUNNEL/L2GRE_TUNNEL/IPGRE_TUNNEL */ 1128 u8 gre_tunnel_mode; 1129 1130 /* GRE_OUTER_HEADERS_RSS/GRE_INNER_HEADERS_RSS/NVGRE_KEY_ENTROPY_RSS */ 1131 u8 gre_tunnel_rss; 1132 }; 1133 1134 struct bnx2x_func_switch_update_params { 1135 u8 suspend; 1136 }; 1137 1138 struct bnx2x_func_afex_update_params { 1139 u16 vif_id; 1140 u16 afex_default_vlan; 1141 u8 allowed_priorities; 1142 }; 1143 1144 struct bnx2x_func_afex_viflists_params { 1145 u16 vif_list_index; 1146 u8 func_bit_map; 1147 u8 afex_vif_list_command; 1148 u8 func_to_clear; 1149 }; 1150 struct bnx2x_func_tx_start_params { 1151 struct priority_cos traffic_type_to_priority_cos[MAX_TRAFFIC_TYPES]; 1152 u8 dcb_enabled; 1153 u8 dcb_version; 1154 u8 dont_add_pri_0_en; 1155 }; 1156 1157 struct bnx2x_func_state_params { 1158 struct bnx2x_func_sp_obj *f_obj; 1159 1160 /* Current command */ 1161 enum bnx2x_func_cmd cmd; 1162 1163 /* may have RAMROD_COMP_WAIT set only */ 1164 unsigned long ramrod_flags; 1165 1166 /* Params according to the current command */ 1167 union { 1168 struct bnx2x_func_hw_init_params hw_init; 1169 struct bnx2x_func_hw_reset_params hw_reset; 1170 struct bnx2x_func_start_params start; 1171 struct bnx2x_func_switch_update_params switch_update; 1172 struct bnx2x_func_afex_update_params afex_update; 1173 struct bnx2x_func_afex_viflists_params afex_viflists; 1174 struct bnx2x_func_tx_start_params tx_start; 1175 } params; 1176 }; 1177 1178 struct bnx2x_func_sp_drv_ops { 1179 /* Init tool + runtime initialization: 1180 * - Common Chip 1181 * - Common (per Path) 1182 * - Port 1183 * - Function phases 1184 */ 1185 int (*init_hw_cmn_chip)(struct bnx2x *bp); 1186 int (*init_hw_cmn)(struct bnx2x *bp); 1187 int (*init_hw_port)(struct bnx2x *bp); 1188 int (*init_hw_func)(struct bnx2x *bp); 1189 1190 /* Reset Function HW: Common, Port, Function phases. */ 1191 void (*reset_hw_cmn)(struct bnx2x *bp); 1192 void (*reset_hw_port)(struct bnx2x *bp); 1193 void (*reset_hw_func)(struct bnx2x *bp); 1194 1195 /* Init/Free GUNZIP resources */ 1196 int (*gunzip_init)(struct bnx2x *bp); 1197 void (*gunzip_end)(struct bnx2x *bp); 1198 1199 /* Prepare/Release FW resources */ 1200 int (*init_fw)(struct bnx2x *bp); 1201 void (*release_fw)(struct bnx2x *bp); 1202 }; 1203 1204 struct bnx2x_func_sp_obj { 1205 enum bnx2x_func_state state, next_state; 1206 1207 /* BNX2X_FUNC_CMD_XX bits. This object implements "one 1208 * pending" paradigm but for debug and tracing purposes it's 1209 * more convenient to have different bits for different 1210 * commands. 1211 */ 1212 unsigned long pending; 1213 1214 /* Buffer to use as a ramrod data and its mapping */ 1215 void *rdata; 1216 dma_addr_t rdata_mapping; 1217 1218 /* Buffer to use as a afex ramrod data and its mapping. 1219 * This can't be same rdata as above because afex ramrod requests 1220 * can arrive to the object in parallel to other ramrod requests. 1221 */ 1222 void *afex_rdata; 1223 dma_addr_t afex_rdata_mapping; 1224 1225 /* this mutex validates that when pending flag is taken, the next 1226 * ramrod to be sent will be the one set the pending bit 1227 */ 1228 struct mutex one_pending_mutex; 1229 1230 /* Driver interface */ 1231 struct bnx2x_func_sp_drv_ops *drv; 1232 1233 /** 1234 * Performs one state change according to the given parameters. 1235 * 1236 * @return 0 in case of success and negative value otherwise. 1237 */ 1238 int (*send_cmd)(struct bnx2x *bp, 1239 struct bnx2x_func_state_params *params); 1240 1241 /** 1242 * Checks that the requested state transition is legal. 1243 */ 1244 int (*check_transition)(struct bnx2x *bp, 1245 struct bnx2x_func_sp_obj *o, 1246 struct bnx2x_func_state_params *params); 1247 1248 /** 1249 * Completes the pending command. 1250 */ 1251 int (*complete_cmd)(struct bnx2x *bp, 1252 struct bnx2x_func_sp_obj *o, 1253 enum bnx2x_func_cmd cmd); 1254 1255 int (*wait_comp)(struct bnx2x *bp, struct bnx2x_func_sp_obj *o, 1256 enum bnx2x_func_cmd cmd); 1257 }; 1258 1259 /********************** Interfaces ********************************************/ 1260 /* Queueable objects set */ 1261 union bnx2x_qable_obj { 1262 struct bnx2x_vlan_mac_obj vlan_mac; 1263 }; 1264 /************** Function state update *********/ 1265 void bnx2x_init_func_obj(struct bnx2x *bp, 1266 struct bnx2x_func_sp_obj *obj, 1267 void *rdata, dma_addr_t rdata_mapping, 1268 void *afex_rdata, dma_addr_t afex_rdata_mapping, 1269 struct bnx2x_func_sp_drv_ops *drv_iface); 1270 1271 int bnx2x_func_state_change(struct bnx2x *bp, 1272 struct bnx2x_func_state_params *params); 1273 1274 enum bnx2x_func_state bnx2x_func_get_state(struct bnx2x *bp, 1275 struct bnx2x_func_sp_obj *o); 1276 /******************* Queue State **************/ 1277 void bnx2x_init_queue_obj(struct bnx2x *bp, 1278 struct bnx2x_queue_sp_obj *obj, u8 cl_id, u32 *cids, 1279 u8 cid_cnt, u8 func_id, void *rdata, 1280 dma_addr_t rdata_mapping, unsigned long type); 1281 1282 int bnx2x_queue_state_change(struct bnx2x *bp, 1283 struct bnx2x_queue_state_params *params); 1284 1285 int bnx2x_get_q_logical_state(struct bnx2x *bp, 1286 struct bnx2x_queue_sp_obj *obj); 1287 1288 /********************* VLAN-MAC ****************/ 1289 void bnx2x_init_mac_obj(struct bnx2x *bp, 1290 struct bnx2x_vlan_mac_obj *mac_obj, 1291 u8 cl_id, u32 cid, u8 func_id, void *rdata, 1292 dma_addr_t rdata_mapping, int state, 1293 unsigned long *pstate, bnx2x_obj_type type, 1294 struct bnx2x_credit_pool_obj *macs_pool); 1295 1296 void bnx2x_init_vlan_obj(struct bnx2x *bp, 1297 struct bnx2x_vlan_mac_obj *vlan_obj, 1298 u8 cl_id, u32 cid, u8 func_id, void *rdata, 1299 dma_addr_t rdata_mapping, int state, 1300 unsigned long *pstate, bnx2x_obj_type type, 1301 struct bnx2x_credit_pool_obj *vlans_pool); 1302 1303 void bnx2x_init_vlan_mac_obj(struct bnx2x *bp, 1304 struct bnx2x_vlan_mac_obj *vlan_mac_obj, 1305 u8 cl_id, u32 cid, u8 func_id, void *rdata, 1306 dma_addr_t rdata_mapping, int state, 1307 unsigned long *pstate, bnx2x_obj_type type, 1308 struct bnx2x_credit_pool_obj *macs_pool, 1309 struct bnx2x_credit_pool_obj *vlans_pool); 1310 1311 int bnx2x_vlan_mac_h_read_lock(struct bnx2x *bp, 1312 struct bnx2x_vlan_mac_obj *o); 1313 void bnx2x_vlan_mac_h_read_unlock(struct bnx2x *bp, 1314 struct bnx2x_vlan_mac_obj *o); 1315 int bnx2x_vlan_mac_h_write_lock(struct bnx2x *bp, 1316 struct bnx2x_vlan_mac_obj *o); 1317 void bnx2x_vlan_mac_h_write_unlock(struct bnx2x *bp, 1318 struct bnx2x_vlan_mac_obj *o); 1319 int bnx2x_config_vlan_mac(struct bnx2x *bp, 1320 struct bnx2x_vlan_mac_ramrod_params *p); 1321 1322 int bnx2x_vlan_mac_move(struct bnx2x *bp, 1323 struct bnx2x_vlan_mac_ramrod_params *p, 1324 struct bnx2x_vlan_mac_obj *dest_o); 1325 1326 /********************* RX MODE ****************/ 1327 1328 void bnx2x_init_rx_mode_obj(struct bnx2x *bp, 1329 struct bnx2x_rx_mode_obj *o); 1330 1331 /** 1332 * bnx2x_config_rx_mode - Send and RX_MODE ramrod according to the provided parameters. 1333 * 1334 * @p: Command parameters 1335 * 1336 * Return: 0 - if operation was successful and there is no pending completions, 1337 * positive number - if there are pending completions, 1338 * negative - if there were errors 1339 */ 1340 int bnx2x_config_rx_mode(struct bnx2x *bp, 1341 struct bnx2x_rx_mode_ramrod_params *p); 1342 1343 /****************** MULTICASTS ****************/ 1344 1345 void bnx2x_init_mcast_obj(struct bnx2x *bp, 1346 struct bnx2x_mcast_obj *mcast_obj, 1347 u8 mcast_cl_id, u32 mcast_cid, u8 func_id, 1348 u8 engine_id, void *rdata, dma_addr_t rdata_mapping, 1349 int state, unsigned long *pstate, 1350 bnx2x_obj_type type); 1351 1352 /** 1353 * bnx2x_config_mcast - Configure multicast MACs list. 1354 * 1355 * @cmd: command to execute: BNX2X_MCAST_CMD_X 1356 * 1357 * May configure a new list 1358 * provided in p->mcast_list (BNX2X_MCAST_CMD_ADD), clean up 1359 * (BNX2X_MCAST_CMD_DEL) or restore (BNX2X_MCAST_CMD_RESTORE) a current 1360 * configuration, continue to execute the pending commands 1361 * (BNX2X_MCAST_CMD_CONT). 1362 * 1363 * If previous command is still pending or if number of MACs to 1364 * configure is more that maximum number of MACs in one command, 1365 * the current command will be enqueued to the tail of the 1366 * pending commands list. 1367 * 1368 * Return: 0 is operation was successful and there are no pending completions, 1369 * negative if there were errors, positive if there are pending 1370 * completions. 1371 */ 1372 int bnx2x_config_mcast(struct bnx2x *bp, 1373 struct bnx2x_mcast_ramrod_params *p, 1374 enum bnx2x_mcast_cmd cmd); 1375 1376 /****************** CREDIT POOL ****************/ 1377 void bnx2x_init_mac_credit_pool(struct bnx2x *bp, 1378 struct bnx2x_credit_pool_obj *p, u8 func_id, 1379 u8 func_num); 1380 void bnx2x_init_vlan_credit_pool(struct bnx2x *bp, 1381 struct bnx2x_credit_pool_obj *p, u8 func_id, 1382 u8 func_num); 1383 1384 /****************** RSS CONFIGURATION ****************/ 1385 void bnx2x_init_rss_config_obj(struct bnx2x *bp, 1386 struct bnx2x_rss_config_obj *rss_obj, 1387 u8 cl_id, u32 cid, u8 func_id, u8 engine_id, 1388 void *rdata, dma_addr_t rdata_mapping, 1389 int state, unsigned long *pstate, 1390 bnx2x_obj_type type); 1391 1392 /** 1393 * bnx2x_config_rss - Updates RSS configuration according to provided parameters 1394 * 1395 * Return: 0 in case of success 1396 */ 1397 int bnx2x_config_rss(struct bnx2x *bp, 1398 struct bnx2x_config_rss_params *p); 1399 1400 /** 1401 * bnx2x_get_rss_ind_table - Return the current ind_table configuration. 1402 * 1403 * @ind_table: buffer to fill with the current indirection 1404 * table content. Should be at least 1405 * T_ETH_INDIRECTION_TABLE_SIZE bytes long. 1406 */ 1407 void bnx2x_get_rss_ind_table(struct bnx2x_rss_config_obj *rss_obj, 1408 u8 *ind_table); 1409 1410 int validate_vlan_mac(struct bnx2x *bp, 1411 struct bnx2x_vlan_mac_obj *vlan_mac); 1412 #endif /* BNX2X_SP_VERBS */ 1413