1 /* bnx2x_sp.h: Broadcom Everest network driver. 2 * 3 * Copyright (c) 2011-2013 Broadcom Corporation 4 * 5 * Unless you and Broadcom execute a separate written software license 6 * agreement governing use of this software, this software is licensed to you 7 * under the terms of the GNU General Public License version 2, available 8 * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL"). 9 * 10 * Notwithstanding the above, under no circumstances may you combine this 11 * software in any way with any other Broadcom software provided under a 12 * license other than the GPL, without Broadcom's express prior written 13 * consent. 14 * 15 * Maintained by: Eilon Greenstein <eilong@broadcom.com> 16 * Written by: Vladislav Zolotarov 17 * 18 */ 19 #ifndef BNX2X_SP_VERBS 20 #define BNX2X_SP_VERBS 21 22 struct bnx2x; 23 struct eth_context; 24 25 /* Bits representing general command's configuration */ 26 enum { 27 RAMROD_TX, 28 RAMROD_RX, 29 /* Wait until all pending commands complete */ 30 RAMROD_COMP_WAIT, 31 /* Don't send a ramrod, only update a registry */ 32 RAMROD_DRV_CLR_ONLY, 33 /* Configure HW according to the current object state */ 34 RAMROD_RESTORE, 35 /* Execute the next command now */ 36 RAMROD_EXEC, 37 /* Don't add a new command and continue execution of postponed 38 * commands. If not set a new command will be added to the 39 * pending commands list. 40 */ 41 RAMROD_CONT, 42 /* If there is another pending ramrod, wait until it finishes and 43 * re-try to submit this one. This flag can be set only in sleepable 44 * context, and should not be set from the context that completes the 45 * ramrods as deadlock will occur. 46 */ 47 RAMROD_RETRY, 48 }; 49 50 typedef enum { 51 BNX2X_OBJ_TYPE_RX, 52 BNX2X_OBJ_TYPE_TX, 53 BNX2X_OBJ_TYPE_RX_TX, 54 } bnx2x_obj_type; 55 56 /* Public slow path states */ 57 enum { 58 BNX2X_FILTER_MAC_PENDING, 59 BNX2X_FILTER_VLAN_PENDING, 60 BNX2X_FILTER_VLAN_MAC_PENDING, 61 BNX2X_FILTER_RX_MODE_PENDING, 62 BNX2X_FILTER_RX_MODE_SCHED, 63 BNX2X_FILTER_ISCSI_ETH_START_SCHED, 64 BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, 65 BNX2X_FILTER_FCOE_ETH_START_SCHED, 66 BNX2X_FILTER_FCOE_ETH_STOP_SCHED, 67 BNX2X_FILTER_MCAST_PENDING, 68 BNX2X_FILTER_MCAST_SCHED, 69 BNX2X_FILTER_RSS_CONF_PENDING, 70 BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, 71 BNX2X_AFEX_PENDING_VIFSET_MCP_ACK 72 }; 73 74 struct bnx2x_raw_obj { 75 u8 func_id; 76 77 /* Queue params */ 78 u8 cl_id; 79 u32 cid; 80 81 /* Ramrod data buffer params */ 82 void *rdata; 83 dma_addr_t rdata_mapping; 84 85 /* Ramrod state params */ 86 int state; /* "ramrod is pending" state bit */ 87 unsigned long *pstate; /* pointer to state buffer */ 88 89 bnx2x_obj_type obj_type; 90 91 int (*wait_comp)(struct bnx2x *bp, 92 struct bnx2x_raw_obj *o); 93 94 bool (*check_pending)(struct bnx2x_raw_obj *o); 95 void (*clear_pending)(struct bnx2x_raw_obj *o); 96 void (*set_pending)(struct bnx2x_raw_obj *o); 97 }; 98 99 /************************* VLAN-MAC commands related parameters ***************/ 100 struct bnx2x_mac_ramrod_data { 101 u8 mac[ETH_ALEN]; 102 u8 is_inner_mac; 103 }; 104 105 struct bnx2x_vlan_ramrod_data { 106 u16 vlan; 107 }; 108 109 struct bnx2x_vlan_mac_ramrod_data { 110 u8 mac[ETH_ALEN]; 111 u8 is_inner_mac; 112 u16 vlan; 113 }; 114 115 union bnx2x_classification_ramrod_data { 116 struct bnx2x_mac_ramrod_data mac; 117 struct bnx2x_vlan_ramrod_data vlan; 118 struct bnx2x_vlan_mac_ramrod_data vlan_mac; 119 }; 120 121 /* VLAN_MAC commands */ 122 enum bnx2x_vlan_mac_cmd { 123 BNX2X_VLAN_MAC_ADD, 124 BNX2X_VLAN_MAC_DEL, 125 BNX2X_VLAN_MAC_MOVE, 126 }; 127 128 struct bnx2x_vlan_mac_data { 129 /* Requested command: BNX2X_VLAN_MAC_XX */ 130 enum bnx2x_vlan_mac_cmd cmd; 131 /* used to contain the data related vlan_mac_flags bits from 132 * ramrod parameters. 133 */ 134 unsigned long vlan_mac_flags; 135 136 /* Needed for MOVE command */ 137 struct bnx2x_vlan_mac_obj *target_obj; 138 139 union bnx2x_classification_ramrod_data u; 140 }; 141 142 /*************************** Exe Queue obj ************************************/ 143 union bnx2x_exe_queue_cmd_data { 144 struct bnx2x_vlan_mac_data vlan_mac; 145 146 struct { 147 /* TODO */ 148 } mcast; 149 }; 150 151 struct bnx2x_exeq_elem { 152 struct list_head link; 153 154 /* Length of this element in the exe_chunk. */ 155 int cmd_len; 156 157 union bnx2x_exe_queue_cmd_data cmd_data; 158 }; 159 160 union bnx2x_qable_obj; 161 162 union bnx2x_exeq_comp_elem { 163 union event_ring_elem *elem; 164 }; 165 166 struct bnx2x_exe_queue_obj; 167 168 typedef int (*exe_q_validate)(struct bnx2x *bp, 169 union bnx2x_qable_obj *o, 170 struct bnx2x_exeq_elem *elem); 171 172 typedef int (*exe_q_remove)(struct bnx2x *bp, 173 union bnx2x_qable_obj *o, 174 struct bnx2x_exeq_elem *elem); 175 176 /* Return positive if entry was optimized, 0 - if not, negative 177 * in case of an error. 178 */ 179 typedef int (*exe_q_optimize)(struct bnx2x *bp, 180 union bnx2x_qable_obj *o, 181 struct bnx2x_exeq_elem *elem); 182 typedef int (*exe_q_execute)(struct bnx2x *bp, 183 union bnx2x_qable_obj *o, 184 struct list_head *exe_chunk, 185 unsigned long *ramrod_flags); 186 typedef struct bnx2x_exeq_elem * 187 (*exe_q_get)(struct bnx2x_exe_queue_obj *o, 188 struct bnx2x_exeq_elem *elem); 189 190 struct bnx2x_exe_queue_obj { 191 /* Commands pending for an execution. */ 192 struct list_head exe_queue; 193 194 /* Commands pending for an completion. */ 195 struct list_head pending_comp; 196 197 spinlock_t lock; 198 199 /* Maximum length of commands' list for one execution */ 200 int exe_chunk_len; 201 202 union bnx2x_qable_obj *owner; 203 204 /****** Virtual functions ******/ 205 /** 206 * Called before commands execution for commands that are really 207 * going to be executed (after 'optimize'). 208 * 209 * Must run under exe_queue->lock 210 */ 211 exe_q_validate validate; 212 213 /** 214 * Called before removing pending commands, cleaning allocated 215 * resources (e.g., credits from validate) 216 */ 217 exe_q_remove remove; 218 219 /** 220 * This will try to cancel the current pending commands list 221 * considering the new command. 222 * 223 * Returns the number of optimized commands or a negative error code 224 * 225 * Must run under exe_queue->lock 226 */ 227 exe_q_optimize optimize; 228 229 /** 230 * Run the next commands chunk (owner specific). 231 */ 232 exe_q_execute execute; 233 234 /** 235 * Return the exe_queue element containing the specific command 236 * if any. Otherwise return NULL. 237 */ 238 exe_q_get get; 239 }; 240 /***************** Classification verbs: Set/Del MAC/VLAN/VLAN-MAC ************/ 241 /* 242 * Element in the VLAN_MAC registry list having all currently configured 243 * rules. 244 */ 245 struct bnx2x_vlan_mac_registry_elem { 246 struct list_head link; 247 248 /* Used to store the cam offset used for the mac/vlan/vlan-mac. 249 * Relevant for 57710 and 57711 only. VLANs and MACs share the 250 * same CAM for these chips. 251 */ 252 int cam_offset; 253 254 /* Needed for DEL and RESTORE flows */ 255 unsigned long vlan_mac_flags; 256 257 union bnx2x_classification_ramrod_data u; 258 }; 259 260 /* Bits representing VLAN_MAC commands specific flags */ 261 enum { 262 BNX2X_UC_LIST_MAC, 263 BNX2X_ETH_MAC, 264 BNX2X_ISCSI_ETH_MAC, 265 BNX2X_NETQ_ETH_MAC, 266 BNX2X_DONT_CONSUME_CAM_CREDIT, 267 BNX2X_DONT_CONSUME_CAM_CREDIT_DEST, 268 }; 269 270 struct bnx2x_vlan_mac_ramrod_params { 271 /* Object to run the command from */ 272 struct bnx2x_vlan_mac_obj *vlan_mac_obj; 273 274 /* General command flags: COMP_WAIT, etc. */ 275 unsigned long ramrod_flags; 276 277 /* Command specific configuration request */ 278 struct bnx2x_vlan_mac_data user_req; 279 }; 280 281 struct bnx2x_vlan_mac_obj { 282 struct bnx2x_raw_obj raw; 283 284 /* Bookkeeping list: will prevent the addition of already existing 285 * entries. 286 */ 287 struct list_head head; 288 289 /* TODO: Add it's initialization in the init functions */ 290 struct bnx2x_exe_queue_obj exe_queue; 291 292 /* MACs credit pool */ 293 struct bnx2x_credit_pool_obj *macs_pool; 294 295 /* VLANs credit pool */ 296 struct bnx2x_credit_pool_obj *vlans_pool; 297 298 /* RAMROD command to be used */ 299 int ramrod_cmd; 300 301 /* copy first n elements onto preallocated buffer 302 * 303 * @param n number of elements to get 304 * @param buf buffer preallocated by caller into which elements 305 * will be copied. Note elements are 4-byte aligned 306 * so buffer size must be able to accommodate the 307 * aligned elements. 308 * 309 * @return number of copied bytes 310 */ 311 int (*get_n_elements)(struct bnx2x *bp, 312 struct bnx2x_vlan_mac_obj *o, int n, u8 *base, 313 u8 stride, u8 size); 314 315 /** 316 * Checks if ADD-ramrod with the given params may be performed. 317 * 318 * @return zero if the element may be added 319 */ 320 321 int (*check_add)(struct bnx2x *bp, 322 struct bnx2x_vlan_mac_obj *o, 323 union bnx2x_classification_ramrod_data *data); 324 325 /** 326 * Checks if DEL-ramrod with the given params may be performed. 327 * 328 * @return true if the element may be deleted 329 */ 330 struct bnx2x_vlan_mac_registry_elem * 331 (*check_del)(struct bnx2x *bp, 332 struct bnx2x_vlan_mac_obj *o, 333 union bnx2x_classification_ramrod_data *data); 334 335 /** 336 * Checks if DEL-ramrod with the given params may be performed. 337 * 338 * @return true if the element may be deleted 339 */ 340 bool (*check_move)(struct bnx2x *bp, 341 struct bnx2x_vlan_mac_obj *src_o, 342 struct bnx2x_vlan_mac_obj *dst_o, 343 union bnx2x_classification_ramrod_data *data); 344 345 /** 346 * Update the relevant credit object(s) (consume/return 347 * correspondingly). 348 */ 349 bool (*get_credit)(struct bnx2x_vlan_mac_obj *o); 350 bool (*put_credit)(struct bnx2x_vlan_mac_obj *o); 351 bool (*get_cam_offset)(struct bnx2x_vlan_mac_obj *o, int *offset); 352 bool (*put_cam_offset)(struct bnx2x_vlan_mac_obj *o, int offset); 353 354 /** 355 * Configures one rule in the ramrod data buffer. 356 */ 357 void (*set_one_rule)(struct bnx2x *bp, 358 struct bnx2x_vlan_mac_obj *o, 359 struct bnx2x_exeq_elem *elem, int rule_idx, 360 int cam_offset); 361 362 /** 363 * Delete all configured elements having the given 364 * vlan_mac_flags specification. Assumes no pending for 365 * execution commands. Will schedule all all currently 366 * configured MACs/VLANs/VLAN-MACs matching the vlan_mac_flags 367 * specification for deletion and will use the given 368 * ramrod_flags for the last DEL operation. 369 * 370 * @param bp 371 * @param o 372 * @param ramrod_flags RAMROD_XX flags 373 * 374 * @return 0 if the last operation has completed successfully 375 * and there are no more elements left, positive value 376 * if there are pending for completion commands, 377 * negative value in case of failure. 378 */ 379 int (*delete_all)(struct bnx2x *bp, 380 struct bnx2x_vlan_mac_obj *o, 381 unsigned long *vlan_mac_flags, 382 unsigned long *ramrod_flags); 383 384 /** 385 * Reconfigures the next MAC/VLAN/VLAN-MAC element from the previously 386 * configured elements list. 387 * 388 * @param bp 389 * @param p Command parameters (RAMROD_COMP_WAIT bit in 390 * ramrod_flags is only taken into an account) 391 * @param ppos a pointer to the cookie that should be given back in the 392 * next call to make function handle the next element. If 393 * *ppos is set to NULL it will restart the iterator. 394 * If returned *ppos == NULL this means that the last 395 * element has been handled. 396 * 397 * @return int 398 */ 399 int (*restore)(struct bnx2x *bp, 400 struct bnx2x_vlan_mac_ramrod_params *p, 401 struct bnx2x_vlan_mac_registry_elem **ppos); 402 403 /** 404 * Should be called on a completion arrival. 405 * 406 * @param bp 407 * @param o 408 * @param cqe Completion element we are handling 409 * @param ramrod_flags if RAMROD_CONT is set the next bulk of 410 * pending commands will be executed. 411 * RAMROD_DRV_CLR_ONLY and RAMROD_RESTORE 412 * may also be set if needed. 413 * 414 * @return 0 if there are neither pending nor waiting for 415 * completion commands. Positive value if there are 416 * pending for execution or for completion commands. 417 * Negative value in case of an error (including an 418 * error in the cqe). 419 */ 420 int (*complete)(struct bnx2x *bp, struct bnx2x_vlan_mac_obj *o, 421 union event_ring_elem *cqe, 422 unsigned long *ramrod_flags); 423 424 /** 425 * Wait for completion of all commands. Don't schedule new ones, 426 * just wait. It assumes that the completion code will schedule 427 * for new commands. 428 */ 429 int (*wait)(struct bnx2x *bp, struct bnx2x_vlan_mac_obj *o); 430 }; 431 432 enum { 433 BNX2X_LLH_CAM_ISCSI_ETH_LINE = 0, 434 BNX2X_LLH_CAM_ETH_LINE, 435 BNX2X_LLH_CAM_MAX_PF_LINE = NIG_REG_LLH1_FUNC_MEM_SIZE / 2 436 }; 437 438 void bnx2x_set_mac_in_nig(struct bnx2x *bp, 439 bool add, unsigned char *dev_addr, int index); 440 441 /** RX_MODE verbs:DROP_ALL/ACCEPT_ALL/ACCEPT_ALL_MULTI/ACCEPT_ALL_VLAN/NORMAL */ 442 443 /* RX_MODE ramrod special flags: set in rx_mode_flags field in 444 * a bnx2x_rx_mode_ramrod_params. 445 */ 446 enum { 447 BNX2X_RX_MODE_FCOE_ETH, 448 BNX2X_RX_MODE_ISCSI_ETH, 449 }; 450 451 enum { 452 BNX2X_ACCEPT_UNICAST, 453 BNX2X_ACCEPT_MULTICAST, 454 BNX2X_ACCEPT_ALL_UNICAST, 455 BNX2X_ACCEPT_ALL_MULTICAST, 456 BNX2X_ACCEPT_BROADCAST, 457 BNX2X_ACCEPT_UNMATCHED, 458 BNX2X_ACCEPT_ANY_VLAN 459 }; 460 461 struct bnx2x_rx_mode_ramrod_params { 462 struct bnx2x_rx_mode_obj *rx_mode_obj; 463 unsigned long *pstate; 464 int state; 465 u8 cl_id; 466 u32 cid; 467 u8 func_id; 468 unsigned long ramrod_flags; 469 unsigned long rx_mode_flags; 470 471 /* rdata is either a pointer to eth_filter_rules_ramrod_data(e2) or to 472 * a tstorm_eth_mac_filter_config (e1x). 473 */ 474 void *rdata; 475 dma_addr_t rdata_mapping; 476 477 /* Rx mode settings */ 478 unsigned long rx_accept_flags; 479 480 /* internal switching settings */ 481 unsigned long tx_accept_flags; 482 }; 483 484 struct bnx2x_rx_mode_obj { 485 int (*config_rx_mode)(struct bnx2x *bp, 486 struct bnx2x_rx_mode_ramrod_params *p); 487 488 int (*wait_comp)(struct bnx2x *bp, 489 struct bnx2x_rx_mode_ramrod_params *p); 490 }; 491 492 /********************** Set multicast group ***********************************/ 493 494 struct bnx2x_mcast_list_elem { 495 struct list_head link; 496 u8 *mac; 497 }; 498 499 union bnx2x_mcast_config_data { 500 u8 *mac; 501 u8 bin; /* used in a RESTORE flow */ 502 }; 503 504 struct bnx2x_mcast_ramrod_params { 505 struct bnx2x_mcast_obj *mcast_obj; 506 507 /* Relevant options are RAMROD_COMP_WAIT and RAMROD_DRV_CLR_ONLY */ 508 unsigned long ramrod_flags; 509 510 struct list_head mcast_list; /* list of struct bnx2x_mcast_list_elem */ 511 /** TODO: 512 * - rename it to macs_num. 513 * - Add a new command type for handling pending commands 514 * (remove "zero semantics"). 515 * 516 * Length of mcast_list. If zero and ADD_CONT command - post 517 * pending commands. 518 */ 519 int mcast_list_len; 520 }; 521 522 enum bnx2x_mcast_cmd { 523 BNX2X_MCAST_CMD_ADD, 524 BNX2X_MCAST_CMD_CONT, 525 BNX2X_MCAST_CMD_DEL, 526 BNX2X_MCAST_CMD_RESTORE, 527 }; 528 529 struct bnx2x_mcast_obj { 530 struct bnx2x_raw_obj raw; 531 532 union { 533 struct { 534 #define BNX2X_MCAST_BINS_NUM 256 535 #define BNX2X_MCAST_VEC_SZ (BNX2X_MCAST_BINS_NUM / 64) 536 u64 vec[BNX2X_MCAST_VEC_SZ]; 537 538 /** Number of BINs to clear. Should be updated 539 * immediately when a command arrives in order to 540 * properly create DEL commands. 541 */ 542 int num_bins_set; 543 } aprox_match; 544 545 struct { 546 struct list_head macs; 547 int num_macs_set; 548 } exact_match; 549 } registry; 550 551 /* Pending commands */ 552 struct list_head pending_cmds_head; 553 554 /* A state that is set in raw.pstate, when there are pending commands */ 555 int sched_state; 556 557 /* Maximal number of mcast MACs configured in one command */ 558 int max_cmd_len; 559 560 /* Total number of currently pending MACs to configure: both 561 * in the pending commands list and in the current command. 562 */ 563 int total_pending_num; 564 565 u8 engine_id; 566 567 /** 568 * @param cmd command to execute (BNX2X_MCAST_CMD_X, see above) 569 */ 570 int (*config_mcast)(struct bnx2x *bp, 571 struct bnx2x_mcast_ramrod_params *p, 572 enum bnx2x_mcast_cmd cmd); 573 574 /** 575 * Fills the ramrod data during the RESTORE flow. 576 * 577 * @param bp 578 * @param o 579 * @param start_idx Registry index to start from 580 * @param rdata_idx Index in the ramrod data to start from 581 * 582 * @return -1 if we handled the whole registry or index of the last 583 * handled registry element. 584 */ 585 int (*hdl_restore)(struct bnx2x *bp, struct bnx2x_mcast_obj *o, 586 int start_bin, int *rdata_idx); 587 588 int (*enqueue_cmd)(struct bnx2x *bp, struct bnx2x_mcast_obj *o, 589 struct bnx2x_mcast_ramrod_params *p, 590 enum bnx2x_mcast_cmd cmd); 591 592 void (*set_one_rule)(struct bnx2x *bp, 593 struct bnx2x_mcast_obj *o, int idx, 594 union bnx2x_mcast_config_data *cfg_data, 595 enum bnx2x_mcast_cmd cmd); 596 597 /** Checks if there are more mcast MACs to be set or a previous 598 * command is still pending. 599 */ 600 bool (*check_pending)(struct bnx2x_mcast_obj *o); 601 602 /** 603 * Set/Clear/Check SCHEDULED state of the object 604 */ 605 void (*set_sched)(struct bnx2x_mcast_obj *o); 606 void (*clear_sched)(struct bnx2x_mcast_obj *o); 607 bool (*check_sched)(struct bnx2x_mcast_obj *o); 608 609 /* Wait until all pending commands complete */ 610 int (*wait_comp)(struct bnx2x *bp, struct bnx2x_mcast_obj *o); 611 612 /** 613 * Handle the internal object counters needed for proper 614 * commands handling. Checks that the provided parameters are 615 * feasible. 616 */ 617 int (*validate)(struct bnx2x *bp, 618 struct bnx2x_mcast_ramrod_params *p, 619 enum bnx2x_mcast_cmd cmd); 620 621 /** 622 * Restore the values of internal counters in case of a failure. 623 */ 624 void (*revert)(struct bnx2x *bp, 625 struct bnx2x_mcast_ramrod_params *p, 626 int old_num_bins); 627 628 int (*get_registry_size)(struct bnx2x_mcast_obj *o); 629 void (*set_registry_size)(struct bnx2x_mcast_obj *o, int n); 630 }; 631 632 /*************************** Credit handling **********************************/ 633 struct bnx2x_credit_pool_obj { 634 635 /* Current amount of credit in the pool */ 636 atomic_t credit; 637 638 /* Maximum allowed credit. put() will check against it. */ 639 int pool_sz; 640 641 /* Allocate a pool table statically. 642 * 643 * Currently the maximum allowed size is MAX_MAC_CREDIT_E2(272) 644 * 645 * The set bit in the table will mean that the entry is available. 646 */ 647 #define BNX2X_POOL_VEC_SIZE (MAX_MAC_CREDIT_E2 / 64) 648 u64 pool_mirror[BNX2X_POOL_VEC_SIZE]; 649 650 /* Base pool offset (initialized differently */ 651 int base_pool_offset; 652 653 /** 654 * Get the next free pool entry. 655 * 656 * @return true if there was a free entry in the pool 657 */ 658 bool (*get_entry)(struct bnx2x_credit_pool_obj *o, int *entry); 659 660 /** 661 * Return the entry back to the pool. 662 * 663 * @return true if entry is legal and has been successfully 664 * returned to the pool. 665 */ 666 bool (*put_entry)(struct bnx2x_credit_pool_obj *o, int entry); 667 668 /** 669 * Get the requested amount of credit from the pool. 670 * 671 * @param cnt Amount of requested credit 672 * @return true if the operation is successful 673 */ 674 bool (*get)(struct bnx2x_credit_pool_obj *o, int cnt); 675 676 /** 677 * Returns the credit to the pool. 678 * 679 * @param cnt Amount of credit to return 680 * @return true if the operation is successful 681 */ 682 bool (*put)(struct bnx2x_credit_pool_obj *o, int cnt); 683 684 /** 685 * Reads the current amount of credit. 686 */ 687 int (*check)(struct bnx2x_credit_pool_obj *o); 688 }; 689 690 /*************************** RSS configuration ********************************/ 691 enum { 692 /* RSS_MODE bits are mutually exclusive */ 693 BNX2X_RSS_MODE_DISABLED, 694 BNX2X_RSS_MODE_REGULAR, 695 696 BNX2X_RSS_SET_SRCH, /* Setup searcher, E1x specific flag */ 697 698 BNX2X_RSS_IPV4, 699 BNX2X_RSS_IPV4_TCP, 700 BNX2X_RSS_IPV4_UDP, 701 BNX2X_RSS_IPV6, 702 BNX2X_RSS_IPV6_TCP, 703 BNX2X_RSS_IPV6_UDP, 704 }; 705 706 struct bnx2x_config_rss_params { 707 struct bnx2x_rss_config_obj *rss_obj; 708 709 /* may have RAMROD_COMP_WAIT set only */ 710 unsigned long ramrod_flags; 711 712 /* BNX2X_RSS_X bits */ 713 unsigned long rss_flags; 714 715 /* Number hash bits to take into an account */ 716 u8 rss_result_mask; 717 718 /* Indirection table */ 719 u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE]; 720 721 /* RSS hash values */ 722 u32 rss_key[10]; 723 724 /* valid only iff BNX2X_RSS_UPDATE_TOE is set */ 725 u16 toe_rss_bitmap; 726 }; 727 728 struct bnx2x_rss_config_obj { 729 struct bnx2x_raw_obj raw; 730 731 /* RSS engine to use */ 732 u8 engine_id; 733 734 /* Last configured indirection table */ 735 u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE]; 736 737 /* flags for enabling 4-tupple hash on UDP */ 738 u8 udp_rss_v4; 739 u8 udp_rss_v6; 740 741 int (*config_rss)(struct bnx2x *bp, 742 struct bnx2x_config_rss_params *p); 743 }; 744 745 /*********************** Queue state update ***********************************/ 746 747 /* UPDATE command options */ 748 enum { 749 BNX2X_Q_UPDATE_IN_VLAN_REM, 750 BNX2X_Q_UPDATE_IN_VLAN_REM_CHNG, 751 BNX2X_Q_UPDATE_OUT_VLAN_REM, 752 BNX2X_Q_UPDATE_OUT_VLAN_REM_CHNG, 753 BNX2X_Q_UPDATE_ANTI_SPOOF, 754 BNX2X_Q_UPDATE_ANTI_SPOOF_CHNG, 755 BNX2X_Q_UPDATE_ACTIVATE, 756 BNX2X_Q_UPDATE_ACTIVATE_CHNG, 757 BNX2X_Q_UPDATE_DEF_VLAN_EN, 758 BNX2X_Q_UPDATE_DEF_VLAN_EN_CHNG, 759 BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG, 760 BNX2X_Q_UPDATE_SILENT_VLAN_REM 761 }; 762 763 /* Allowed Queue states */ 764 enum bnx2x_q_state { 765 BNX2X_Q_STATE_RESET, 766 BNX2X_Q_STATE_INITIALIZED, 767 BNX2X_Q_STATE_ACTIVE, 768 BNX2X_Q_STATE_MULTI_COS, 769 BNX2X_Q_STATE_MCOS_TERMINATED, 770 BNX2X_Q_STATE_INACTIVE, 771 BNX2X_Q_STATE_STOPPED, 772 BNX2X_Q_STATE_TERMINATED, 773 BNX2X_Q_STATE_FLRED, 774 BNX2X_Q_STATE_MAX, 775 }; 776 777 /* Allowed Queue states */ 778 enum bnx2x_q_logical_state { 779 BNX2X_Q_LOGICAL_STATE_ACTIVE, 780 BNX2X_Q_LOGICAL_STATE_STOPPED, 781 }; 782 783 /* Allowed commands */ 784 enum bnx2x_queue_cmd { 785 BNX2X_Q_CMD_INIT, 786 BNX2X_Q_CMD_SETUP, 787 BNX2X_Q_CMD_SETUP_TX_ONLY, 788 BNX2X_Q_CMD_DEACTIVATE, 789 BNX2X_Q_CMD_ACTIVATE, 790 BNX2X_Q_CMD_UPDATE, 791 BNX2X_Q_CMD_UPDATE_TPA, 792 BNX2X_Q_CMD_HALT, 793 BNX2X_Q_CMD_CFC_DEL, 794 BNX2X_Q_CMD_TERMINATE, 795 BNX2X_Q_CMD_EMPTY, 796 BNX2X_Q_CMD_MAX, 797 }; 798 799 /* queue SETUP + INIT flags */ 800 enum { 801 BNX2X_Q_FLG_TPA, 802 BNX2X_Q_FLG_TPA_IPV6, 803 BNX2X_Q_FLG_TPA_GRO, 804 BNX2X_Q_FLG_STATS, 805 BNX2X_Q_FLG_ZERO_STATS, 806 BNX2X_Q_FLG_ACTIVE, 807 BNX2X_Q_FLG_OV, 808 BNX2X_Q_FLG_VLAN, 809 BNX2X_Q_FLG_COS, 810 BNX2X_Q_FLG_HC, 811 BNX2X_Q_FLG_HC_EN, 812 BNX2X_Q_FLG_DHC, 813 BNX2X_Q_FLG_FCOE, 814 BNX2X_Q_FLG_LEADING_RSS, 815 BNX2X_Q_FLG_MCAST, 816 BNX2X_Q_FLG_DEF_VLAN, 817 BNX2X_Q_FLG_TX_SWITCH, 818 BNX2X_Q_FLG_TX_SEC, 819 BNX2X_Q_FLG_ANTI_SPOOF, 820 BNX2X_Q_FLG_SILENT_VLAN_REM, 821 BNX2X_Q_FLG_FORCE_DEFAULT_PRI, 822 BNX2X_Q_FLG_PCSUM_ON_PKT, 823 BNX2X_Q_FLG_TUN_INC_INNER_IP_ID 824 }; 825 826 /* Queue type options: queue type may be a combination of below. */ 827 enum bnx2x_q_type { 828 /** TODO: Consider moving both these flags into the init() 829 * ramrod params. 830 */ 831 BNX2X_Q_TYPE_HAS_RX, 832 BNX2X_Q_TYPE_HAS_TX, 833 }; 834 835 #define BNX2X_PRIMARY_CID_INDEX 0 836 #define BNX2X_MULTI_TX_COS_E1X 3 /* QM only */ 837 #define BNX2X_MULTI_TX_COS_E2_E3A0 2 838 #define BNX2X_MULTI_TX_COS_E3B0 3 839 #define BNX2X_MULTI_TX_COS 3 /* Maximum possible */ 840 841 #define MAC_PAD (ALIGN(ETH_ALEN, sizeof(u32)) - ETH_ALEN) 842 843 struct bnx2x_queue_init_params { 844 struct { 845 unsigned long flags; 846 u16 hc_rate; 847 u8 fw_sb_id; 848 u8 sb_cq_index; 849 } tx; 850 851 struct { 852 unsigned long flags; 853 u16 hc_rate; 854 u8 fw_sb_id; 855 u8 sb_cq_index; 856 } rx; 857 858 /* CID context in the host memory */ 859 struct eth_context *cxts[BNX2X_MULTI_TX_COS]; 860 861 /* maximum number of cos supported by hardware */ 862 u8 max_cos; 863 }; 864 865 struct bnx2x_queue_terminate_params { 866 /* index within the tx_only cids of this queue object */ 867 u8 cid_index; 868 }; 869 870 struct bnx2x_queue_cfc_del_params { 871 /* index within the tx_only cids of this queue object */ 872 u8 cid_index; 873 }; 874 875 struct bnx2x_queue_update_params { 876 unsigned long update_flags; /* BNX2X_Q_UPDATE_XX bits */ 877 u16 def_vlan; 878 u16 silent_removal_value; 879 u16 silent_removal_mask; 880 /* index within the tx_only cids of this queue object */ 881 u8 cid_index; 882 }; 883 884 struct rxq_pause_params { 885 u16 bd_th_lo; 886 u16 bd_th_hi; 887 u16 rcq_th_lo; 888 u16 rcq_th_hi; 889 u16 sge_th_lo; /* valid iff BNX2X_Q_FLG_TPA */ 890 u16 sge_th_hi; /* valid iff BNX2X_Q_FLG_TPA */ 891 u16 pri_map; 892 }; 893 894 /* general */ 895 struct bnx2x_general_setup_params { 896 /* valid iff BNX2X_Q_FLG_STATS */ 897 u8 stat_id; 898 899 u8 spcl_id; 900 u16 mtu; 901 u8 cos; 902 }; 903 904 struct bnx2x_rxq_setup_params { 905 /* dma */ 906 dma_addr_t dscr_map; 907 dma_addr_t sge_map; 908 dma_addr_t rcq_map; 909 dma_addr_t rcq_np_map; 910 911 u16 drop_flags; 912 u16 buf_sz; 913 u8 fw_sb_id; 914 u8 cl_qzone_id; 915 916 /* valid iff BNX2X_Q_FLG_TPA */ 917 u16 tpa_agg_sz; 918 u16 sge_buf_sz; 919 u8 max_sges_pkt; 920 u8 max_tpa_queues; 921 u8 rss_engine_id; 922 923 /* valid iff BNX2X_Q_FLG_MCAST */ 924 u8 mcast_engine_id; 925 926 u8 cache_line_log; 927 928 u8 sb_cq_index; 929 930 /* valid iff BXN2X_Q_FLG_SILENT_VLAN_REM */ 931 u16 silent_removal_value; 932 u16 silent_removal_mask; 933 }; 934 935 struct bnx2x_txq_setup_params { 936 /* dma */ 937 dma_addr_t dscr_map; 938 939 u8 fw_sb_id; 940 u8 sb_cq_index; 941 u8 cos; /* valid iff BNX2X_Q_FLG_COS */ 942 u16 traffic_type; 943 /* equals to the leading rss client id, used for TX classification*/ 944 u8 tss_leading_cl_id; 945 946 /* valid iff BNX2X_Q_FLG_DEF_VLAN */ 947 u16 default_vlan; 948 }; 949 950 struct bnx2x_queue_setup_params { 951 struct bnx2x_general_setup_params gen_params; 952 struct bnx2x_txq_setup_params txq_params; 953 struct bnx2x_rxq_setup_params rxq_params; 954 struct rxq_pause_params pause_params; 955 unsigned long flags; 956 }; 957 958 struct bnx2x_queue_setup_tx_only_params { 959 struct bnx2x_general_setup_params gen_params; 960 struct bnx2x_txq_setup_params txq_params; 961 unsigned long flags; 962 /* index within the tx_only cids of this queue object */ 963 u8 cid_index; 964 }; 965 966 struct bnx2x_queue_state_params { 967 struct bnx2x_queue_sp_obj *q_obj; 968 969 /* Current command */ 970 enum bnx2x_queue_cmd cmd; 971 972 /* may have RAMROD_COMP_WAIT set only */ 973 unsigned long ramrod_flags; 974 975 /* Params according to the current command */ 976 union { 977 struct bnx2x_queue_update_params update; 978 struct bnx2x_queue_setup_params setup; 979 struct bnx2x_queue_init_params init; 980 struct bnx2x_queue_setup_tx_only_params tx_only; 981 struct bnx2x_queue_terminate_params terminate; 982 struct bnx2x_queue_cfc_del_params cfc_del; 983 } params; 984 }; 985 986 struct bnx2x_viflist_params { 987 u8 echo_res; 988 u8 func_bit_map_res; 989 }; 990 991 struct bnx2x_queue_sp_obj { 992 u32 cids[BNX2X_MULTI_TX_COS]; 993 u8 cl_id; 994 u8 func_id; 995 996 /* number of traffic classes supported by queue. 997 * The primary connection of the queue supports the first traffic 998 * class. Any further traffic class is supported by a tx-only 999 * connection. 1000 * 1001 * Therefore max_cos is also a number of valid entries in the cids 1002 * array. 1003 */ 1004 u8 max_cos; 1005 u8 num_tx_only, next_tx_only; 1006 1007 enum bnx2x_q_state state, next_state; 1008 1009 /* bits from enum bnx2x_q_type */ 1010 unsigned long type; 1011 1012 /* BNX2X_Q_CMD_XX bits. This object implements "one 1013 * pending" paradigm but for debug and tracing purposes it's 1014 * more convenient to have different bits for different 1015 * commands. 1016 */ 1017 unsigned long pending; 1018 1019 /* Buffer to use as a ramrod data and its mapping */ 1020 void *rdata; 1021 dma_addr_t rdata_mapping; 1022 1023 /** 1024 * Performs one state change according to the given parameters. 1025 * 1026 * @return 0 in case of success and negative value otherwise. 1027 */ 1028 int (*send_cmd)(struct bnx2x *bp, 1029 struct bnx2x_queue_state_params *params); 1030 1031 /** 1032 * Sets the pending bit according to the requested transition. 1033 */ 1034 int (*set_pending)(struct bnx2x_queue_sp_obj *o, 1035 struct bnx2x_queue_state_params *params); 1036 1037 /** 1038 * Checks that the requested state transition is legal. 1039 */ 1040 int (*check_transition)(struct bnx2x *bp, 1041 struct bnx2x_queue_sp_obj *o, 1042 struct bnx2x_queue_state_params *params); 1043 1044 /** 1045 * Completes the pending command. 1046 */ 1047 int (*complete_cmd)(struct bnx2x *bp, 1048 struct bnx2x_queue_sp_obj *o, 1049 enum bnx2x_queue_cmd); 1050 1051 int (*wait_comp)(struct bnx2x *bp, 1052 struct bnx2x_queue_sp_obj *o, 1053 enum bnx2x_queue_cmd cmd); 1054 }; 1055 1056 /********************** Function state update *********************************/ 1057 /* Allowed Function states */ 1058 enum bnx2x_func_state { 1059 BNX2X_F_STATE_RESET, 1060 BNX2X_F_STATE_INITIALIZED, 1061 BNX2X_F_STATE_STARTED, 1062 BNX2X_F_STATE_TX_STOPPED, 1063 BNX2X_F_STATE_MAX, 1064 }; 1065 1066 /* Allowed Function commands */ 1067 enum bnx2x_func_cmd { 1068 BNX2X_F_CMD_HW_INIT, 1069 BNX2X_F_CMD_START, 1070 BNX2X_F_CMD_STOP, 1071 BNX2X_F_CMD_HW_RESET, 1072 BNX2X_F_CMD_AFEX_UPDATE, 1073 BNX2X_F_CMD_AFEX_VIFLISTS, 1074 BNX2X_F_CMD_TX_STOP, 1075 BNX2X_F_CMD_TX_START, 1076 BNX2X_F_CMD_SWITCH_UPDATE, 1077 BNX2X_F_CMD_MAX, 1078 }; 1079 1080 struct bnx2x_func_hw_init_params { 1081 /* A load phase returned by MCP. 1082 * 1083 * May be: 1084 * FW_MSG_CODE_DRV_LOAD_COMMON_CHIP 1085 * FW_MSG_CODE_DRV_LOAD_COMMON 1086 * FW_MSG_CODE_DRV_LOAD_PORT 1087 * FW_MSG_CODE_DRV_LOAD_FUNCTION 1088 */ 1089 u32 load_phase; 1090 }; 1091 1092 struct bnx2x_func_hw_reset_params { 1093 /* A load phase returned by MCP. 1094 * 1095 * May be: 1096 * FW_MSG_CODE_DRV_LOAD_COMMON_CHIP 1097 * FW_MSG_CODE_DRV_LOAD_COMMON 1098 * FW_MSG_CODE_DRV_LOAD_PORT 1099 * FW_MSG_CODE_DRV_LOAD_FUNCTION 1100 */ 1101 u32 reset_phase; 1102 }; 1103 1104 struct bnx2x_func_start_params { 1105 /* Multi Function mode: 1106 * - Single Function 1107 * - Switch Dependent 1108 * - Switch Independent 1109 */ 1110 u16 mf_mode; 1111 1112 /* Switch Dependent mode outer VLAN tag */ 1113 u16 sd_vlan_tag; 1114 1115 /* Function cos mode */ 1116 u8 network_cos_mode; 1117 1118 /* NVGRE classification enablement */ 1119 u8 nvgre_clss_en; 1120 1121 /* NO_GRE_TUNNEL/NVGRE_TUNNEL/L2GRE_TUNNEL/IPGRE_TUNNEL */ 1122 u8 gre_tunnel_mode; 1123 1124 /* GRE_OUTER_HEADERS_RSS/GRE_INNER_HEADERS_RSS/NVGRE_KEY_ENTROPY_RSS */ 1125 u8 gre_tunnel_rss; 1126 }; 1127 1128 struct bnx2x_func_switch_update_params { 1129 u8 suspend; 1130 }; 1131 1132 struct bnx2x_func_afex_update_params { 1133 u16 vif_id; 1134 u16 afex_default_vlan; 1135 u8 allowed_priorities; 1136 }; 1137 1138 struct bnx2x_func_afex_viflists_params { 1139 u16 vif_list_index; 1140 u8 func_bit_map; 1141 u8 afex_vif_list_command; 1142 u8 func_to_clear; 1143 }; 1144 struct bnx2x_func_tx_start_params { 1145 struct priority_cos traffic_type_to_priority_cos[MAX_TRAFFIC_TYPES]; 1146 u8 dcb_enabled; 1147 u8 dcb_version; 1148 u8 dont_add_pri_0_en; 1149 }; 1150 1151 struct bnx2x_func_state_params { 1152 struct bnx2x_func_sp_obj *f_obj; 1153 1154 /* Current command */ 1155 enum bnx2x_func_cmd cmd; 1156 1157 /* may have RAMROD_COMP_WAIT set only */ 1158 unsigned long ramrod_flags; 1159 1160 /* Params according to the current command */ 1161 union { 1162 struct bnx2x_func_hw_init_params hw_init; 1163 struct bnx2x_func_hw_reset_params hw_reset; 1164 struct bnx2x_func_start_params start; 1165 struct bnx2x_func_switch_update_params switch_update; 1166 struct bnx2x_func_afex_update_params afex_update; 1167 struct bnx2x_func_afex_viflists_params afex_viflists; 1168 struct bnx2x_func_tx_start_params tx_start; 1169 } params; 1170 }; 1171 1172 struct bnx2x_func_sp_drv_ops { 1173 /* Init tool + runtime initialization: 1174 * - Common Chip 1175 * - Common (per Path) 1176 * - Port 1177 * - Function phases 1178 */ 1179 int (*init_hw_cmn_chip)(struct bnx2x *bp); 1180 int (*init_hw_cmn)(struct bnx2x *bp); 1181 int (*init_hw_port)(struct bnx2x *bp); 1182 int (*init_hw_func)(struct bnx2x *bp); 1183 1184 /* Reset Function HW: Common, Port, Function phases. */ 1185 void (*reset_hw_cmn)(struct bnx2x *bp); 1186 void (*reset_hw_port)(struct bnx2x *bp); 1187 void (*reset_hw_func)(struct bnx2x *bp); 1188 1189 /* Init/Free GUNZIP resources */ 1190 int (*gunzip_init)(struct bnx2x *bp); 1191 void (*gunzip_end)(struct bnx2x *bp); 1192 1193 /* Prepare/Release FW resources */ 1194 int (*init_fw)(struct bnx2x *bp); 1195 void (*release_fw)(struct bnx2x *bp); 1196 }; 1197 1198 struct bnx2x_func_sp_obj { 1199 enum bnx2x_func_state state, next_state; 1200 1201 /* BNX2X_FUNC_CMD_XX bits. This object implements "one 1202 * pending" paradigm but for debug and tracing purposes it's 1203 * more convenient to have different bits for different 1204 * commands. 1205 */ 1206 unsigned long pending; 1207 1208 /* Buffer to use as a ramrod data and its mapping */ 1209 void *rdata; 1210 dma_addr_t rdata_mapping; 1211 1212 /* Buffer to use as a afex ramrod data and its mapping. 1213 * This can't be same rdata as above because afex ramrod requests 1214 * can arrive to the object in parallel to other ramrod requests. 1215 */ 1216 void *afex_rdata; 1217 dma_addr_t afex_rdata_mapping; 1218 1219 /* this mutex validates that when pending flag is taken, the next 1220 * ramrod to be sent will be the one set the pending bit 1221 */ 1222 struct mutex one_pending_mutex; 1223 1224 /* Driver interface */ 1225 struct bnx2x_func_sp_drv_ops *drv; 1226 1227 /** 1228 * Performs one state change according to the given parameters. 1229 * 1230 * @return 0 in case of success and negative value otherwise. 1231 */ 1232 int (*send_cmd)(struct bnx2x *bp, 1233 struct bnx2x_func_state_params *params); 1234 1235 /** 1236 * Checks that the requested state transition is legal. 1237 */ 1238 int (*check_transition)(struct bnx2x *bp, 1239 struct bnx2x_func_sp_obj *o, 1240 struct bnx2x_func_state_params *params); 1241 1242 /** 1243 * Completes the pending command. 1244 */ 1245 int (*complete_cmd)(struct bnx2x *bp, 1246 struct bnx2x_func_sp_obj *o, 1247 enum bnx2x_func_cmd cmd); 1248 1249 int (*wait_comp)(struct bnx2x *bp, struct bnx2x_func_sp_obj *o, 1250 enum bnx2x_func_cmd cmd); 1251 }; 1252 1253 /********************** Interfaces ********************************************/ 1254 /* Queueable objects set */ 1255 union bnx2x_qable_obj { 1256 struct bnx2x_vlan_mac_obj vlan_mac; 1257 }; 1258 /************** Function state update *********/ 1259 void bnx2x_init_func_obj(struct bnx2x *bp, 1260 struct bnx2x_func_sp_obj *obj, 1261 void *rdata, dma_addr_t rdata_mapping, 1262 void *afex_rdata, dma_addr_t afex_rdata_mapping, 1263 struct bnx2x_func_sp_drv_ops *drv_iface); 1264 1265 int bnx2x_func_state_change(struct bnx2x *bp, 1266 struct bnx2x_func_state_params *params); 1267 1268 enum bnx2x_func_state bnx2x_func_get_state(struct bnx2x *bp, 1269 struct bnx2x_func_sp_obj *o); 1270 /******************* Queue State **************/ 1271 void bnx2x_init_queue_obj(struct bnx2x *bp, 1272 struct bnx2x_queue_sp_obj *obj, u8 cl_id, u32 *cids, 1273 u8 cid_cnt, u8 func_id, void *rdata, 1274 dma_addr_t rdata_mapping, unsigned long type); 1275 1276 int bnx2x_queue_state_change(struct bnx2x *bp, 1277 struct bnx2x_queue_state_params *params); 1278 1279 int bnx2x_get_q_logical_state(struct bnx2x *bp, 1280 struct bnx2x_queue_sp_obj *obj); 1281 1282 /********************* VLAN-MAC ****************/ 1283 void bnx2x_init_mac_obj(struct bnx2x *bp, 1284 struct bnx2x_vlan_mac_obj *mac_obj, 1285 u8 cl_id, u32 cid, u8 func_id, void *rdata, 1286 dma_addr_t rdata_mapping, int state, 1287 unsigned long *pstate, bnx2x_obj_type type, 1288 struct bnx2x_credit_pool_obj *macs_pool); 1289 1290 void bnx2x_init_vlan_obj(struct bnx2x *bp, 1291 struct bnx2x_vlan_mac_obj *vlan_obj, 1292 u8 cl_id, u32 cid, u8 func_id, void *rdata, 1293 dma_addr_t rdata_mapping, int state, 1294 unsigned long *pstate, bnx2x_obj_type type, 1295 struct bnx2x_credit_pool_obj *vlans_pool); 1296 1297 void bnx2x_init_vlan_mac_obj(struct bnx2x *bp, 1298 struct bnx2x_vlan_mac_obj *vlan_mac_obj, 1299 u8 cl_id, u32 cid, u8 func_id, void *rdata, 1300 dma_addr_t rdata_mapping, int state, 1301 unsigned long *pstate, bnx2x_obj_type type, 1302 struct bnx2x_credit_pool_obj *macs_pool, 1303 struct bnx2x_credit_pool_obj *vlans_pool); 1304 1305 int bnx2x_config_vlan_mac(struct bnx2x *bp, 1306 struct bnx2x_vlan_mac_ramrod_params *p); 1307 1308 int bnx2x_vlan_mac_move(struct bnx2x *bp, 1309 struct bnx2x_vlan_mac_ramrod_params *p, 1310 struct bnx2x_vlan_mac_obj *dest_o); 1311 1312 /********************* RX MODE ****************/ 1313 1314 void bnx2x_init_rx_mode_obj(struct bnx2x *bp, 1315 struct bnx2x_rx_mode_obj *o); 1316 1317 /** 1318 * bnx2x_config_rx_mode - Send and RX_MODE ramrod according to the provided parameters. 1319 * 1320 * @p: Command parameters 1321 * 1322 * Return: 0 - if operation was successful and there is no pending completions, 1323 * positive number - if there are pending completions, 1324 * negative - if there were errors 1325 */ 1326 int bnx2x_config_rx_mode(struct bnx2x *bp, 1327 struct bnx2x_rx_mode_ramrod_params *p); 1328 1329 /****************** MULTICASTS ****************/ 1330 1331 void bnx2x_init_mcast_obj(struct bnx2x *bp, 1332 struct bnx2x_mcast_obj *mcast_obj, 1333 u8 mcast_cl_id, u32 mcast_cid, u8 func_id, 1334 u8 engine_id, void *rdata, dma_addr_t rdata_mapping, 1335 int state, unsigned long *pstate, 1336 bnx2x_obj_type type); 1337 1338 /** 1339 * bnx2x_config_mcast - Configure multicast MACs list. 1340 * 1341 * @cmd: command to execute: BNX2X_MCAST_CMD_X 1342 * 1343 * May configure a new list 1344 * provided in p->mcast_list (BNX2X_MCAST_CMD_ADD), clean up 1345 * (BNX2X_MCAST_CMD_DEL) or restore (BNX2X_MCAST_CMD_RESTORE) a current 1346 * configuration, continue to execute the pending commands 1347 * (BNX2X_MCAST_CMD_CONT). 1348 * 1349 * If previous command is still pending or if number of MACs to 1350 * configure is more that maximum number of MACs in one command, 1351 * the current command will be enqueued to the tail of the 1352 * pending commands list. 1353 * 1354 * Return: 0 is operation was successful and there are no pending completions, 1355 * negative if there were errors, positive if there are pending 1356 * completions. 1357 */ 1358 int bnx2x_config_mcast(struct bnx2x *bp, 1359 struct bnx2x_mcast_ramrod_params *p, 1360 enum bnx2x_mcast_cmd cmd); 1361 1362 /****************** CREDIT POOL ****************/ 1363 void bnx2x_init_mac_credit_pool(struct bnx2x *bp, 1364 struct bnx2x_credit_pool_obj *p, u8 func_id, 1365 u8 func_num); 1366 void bnx2x_init_vlan_credit_pool(struct bnx2x *bp, 1367 struct bnx2x_credit_pool_obj *p, u8 func_id, 1368 u8 func_num); 1369 1370 /****************** RSS CONFIGURATION ****************/ 1371 void bnx2x_init_rss_config_obj(struct bnx2x *bp, 1372 struct bnx2x_rss_config_obj *rss_obj, 1373 u8 cl_id, u32 cid, u8 func_id, u8 engine_id, 1374 void *rdata, dma_addr_t rdata_mapping, 1375 int state, unsigned long *pstate, 1376 bnx2x_obj_type type); 1377 1378 /** 1379 * bnx2x_config_rss - Updates RSS configuration according to provided parameters 1380 * 1381 * Return: 0 in case of success 1382 */ 1383 int bnx2x_config_rss(struct bnx2x *bp, 1384 struct bnx2x_config_rss_params *p); 1385 1386 /** 1387 * bnx2x_get_rss_ind_table - Return the current ind_table configuration. 1388 * 1389 * @ind_table: buffer to fill with the current indirection 1390 * table content. Should be at least 1391 * T_ETH_INDIRECTION_TABLE_SIZE bytes long. 1392 */ 1393 void bnx2x_get_rss_ind_table(struct bnx2x_rss_config_obj *rss_obj, 1394 u8 *ind_table); 1395 1396 #endif /* BNX2X_SP_VERBS */ 1397