1 /* bnx2x_sp.h: Broadcom Everest network driver. 2 * 3 * Copyright (c) 2011-2013 Broadcom Corporation 4 * 5 * Unless you and Broadcom execute a separate written software license 6 * agreement governing use of this software, this software is licensed to you 7 * under the terms of the GNU General Public License version 2, available 8 * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL"). 9 * 10 * Notwithstanding the above, under no circumstances may you combine this 11 * software in any way with any other Broadcom software provided under a 12 * license other than the GPL, without Broadcom's express prior written 13 * consent. 14 * 15 * Maintained by: Eilon Greenstein <eilong@broadcom.com> 16 * Written by: Vladislav Zolotarov 17 * 18 */ 19 #ifndef BNX2X_SP_VERBS 20 #define BNX2X_SP_VERBS 21 22 struct bnx2x; 23 struct eth_context; 24 25 /* Bits representing general command's configuration */ 26 enum { 27 RAMROD_TX, 28 RAMROD_RX, 29 /* Wait until all pending commands complete */ 30 RAMROD_COMP_WAIT, 31 /* Don't send a ramrod, only update a registry */ 32 RAMROD_DRV_CLR_ONLY, 33 /* Configure HW according to the current object state */ 34 RAMROD_RESTORE, 35 /* Execute the next command now */ 36 RAMROD_EXEC, 37 /* 38 * Don't add a new command and continue execution of posponed 39 * commands. If not set a new command will be added to the 40 * pending commands list. 41 */ 42 RAMROD_CONT, 43 /* If there is another pending ramrod, wait until it finishes and 44 * re-try to submit this one. This flag can be set only in sleepable 45 * context, and should not be set from the context that completes the 46 * ramrods as deadlock will occur. 47 */ 48 RAMROD_RETRY, 49 }; 50 51 typedef enum { 52 BNX2X_OBJ_TYPE_RX, 53 BNX2X_OBJ_TYPE_TX, 54 BNX2X_OBJ_TYPE_RX_TX, 55 } bnx2x_obj_type; 56 57 /* Public slow path states */ 58 enum { 59 BNX2X_FILTER_MAC_PENDING, 60 BNX2X_FILTER_VLAN_PENDING, 61 BNX2X_FILTER_VLAN_MAC_PENDING, 62 BNX2X_FILTER_RX_MODE_PENDING, 63 BNX2X_FILTER_RX_MODE_SCHED, 64 BNX2X_FILTER_ISCSI_ETH_START_SCHED, 65 BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, 66 BNX2X_FILTER_FCOE_ETH_START_SCHED, 67 BNX2X_FILTER_FCOE_ETH_STOP_SCHED, 68 BNX2X_FILTER_MCAST_PENDING, 69 BNX2X_FILTER_MCAST_SCHED, 70 BNX2X_FILTER_RSS_CONF_PENDING, 71 BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, 72 BNX2X_AFEX_PENDING_VIFSET_MCP_ACK 73 }; 74 75 struct bnx2x_raw_obj { 76 u8 func_id; 77 78 /* Queue params */ 79 u8 cl_id; 80 u32 cid; 81 82 /* Ramrod data buffer params */ 83 void *rdata; 84 dma_addr_t rdata_mapping; 85 86 /* Ramrod state params */ 87 int state; /* "ramrod is pending" state bit */ 88 unsigned long *pstate; /* pointer to state buffer */ 89 90 bnx2x_obj_type obj_type; 91 92 int (*wait_comp)(struct bnx2x *bp, 93 struct bnx2x_raw_obj *o); 94 95 bool (*check_pending)(struct bnx2x_raw_obj *o); 96 void (*clear_pending)(struct bnx2x_raw_obj *o); 97 void (*set_pending)(struct bnx2x_raw_obj *o); 98 }; 99 100 /************************* VLAN-MAC commands related parameters ***************/ 101 struct bnx2x_mac_ramrod_data { 102 u8 mac[ETH_ALEN]; 103 }; 104 105 struct bnx2x_vlan_ramrod_data { 106 u16 vlan; 107 }; 108 109 struct bnx2x_vlan_mac_ramrod_data { 110 u8 mac[ETH_ALEN]; 111 u16 vlan; 112 }; 113 114 union bnx2x_classification_ramrod_data { 115 struct bnx2x_mac_ramrod_data mac; 116 struct bnx2x_vlan_ramrod_data vlan; 117 struct bnx2x_vlan_mac_ramrod_data vlan_mac; 118 }; 119 120 /* VLAN_MAC commands */ 121 enum bnx2x_vlan_mac_cmd { 122 BNX2X_VLAN_MAC_ADD, 123 BNX2X_VLAN_MAC_DEL, 124 BNX2X_VLAN_MAC_MOVE, 125 }; 126 127 struct bnx2x_vlan_mac_data { 128 /* Requested command: BNX2X_VLAN_MAC_XX */ 129 enum bnx2x_vlan_mac_cmd cmd; 130 /* 131 * used to contain the data related vlan_mac_flags bits from 132 * ramrod parameters. 133 */ 134 unsigned long vlan_mac_flags; 135 136 /* Needed for MOVE command */ 137 struct bnx2x_vlan_mac_obj *target_obj; 138 139 union bnx2x_classification_ramrod_data u; 140 }; 141 142 /*************************** Exe Queue obj ************************************/ 143 union bnx2x_exe_queue_cmd_data { 144 struct bnx2x_vlan_mac_data vlan_mac; 145 146 struct { 147 /* TODO */ 148 } mcast; 149 }; 150 151 struct bnx2x_exeq_elem { 152 struct list_head link; 153 154 /* Length of this element in the exe_chunk. */ 155 int cmd_len; 156 157 union bnx2x_exe_queue_cmd_data cmd_data; 158 }; 159 160 union bnx2x_qable_obj; 161 162 union bnx2x_exeq_comp_elem { 163 union event_ring_elem *elem; 164 }; 165 166 struct bnx2x_exe_queue_obj; 167 168 typedef int (*exe_q_validate)(struct bnx2x *bp, 169 union bnx2x_qable_obj *o, 170 struct bnx2x_exeq_elem *elem); 171 172 typedef int (*exe_q_remove)(struct bnx2x *bp, 173 union bnx2x_qable_obj *o, 174 struct bnx2x_exeq_elem *elem); 175 176 /* Return positive if entry was optimized, 0 - if not, negative 177 * in case of an error. 178 */ 179 typedef int (*exe_q_optimize)(struct bnx2x *bp, 180 union bnx2x_qable_obj *o, 181 struct bnx2x_exeq_elem *elem); 182 typedef int (*exe_q_execute)(struct bnx2x *bp, 183 union bnx2x_qable_obj *o, 184 struct list_head *exe_chunk, 185 unsigned long *ramrod_flags); 186 typedef struct bnx2x_exeq_elem * 187 (*exe_q_get)(struct bnx2x_exe_queue_obj *o, 188 struct bnx2x_exeq_elem *elem); 189 190 struct bnx2x_exe_queue_obj { 191 /* 192 * Commands pending for an execution. 193 */ 194 struct list_head exe_queue; 195 196 /* 197 * Commands pending for an completion. 198 */ 199 struct list_head pending_comp; 200 201 spinlock_t lock; 202 203 /* Maximum length of commands' list for one execution */ 204 int exe_chunk_len; 205 206 union bnx2x_qable_obj *owner; 207 208 /****** Virtual functions ******/ 209 /** 210 * Called before commands execution for commands that are really 211 * going to be executed (after 'optimize'). 212 * 213 * Must run under exe_queue->lock 214 */ 215 exe_q_validate validate; 216 217 /** 218 * Called before removing pending commands, cleaning allocated 219 * resources (e.g., credits from validate) 220 */ 221 exe_q_remove remove; 222 223 /** 224 * This will try to cancel the current pending commands list 225 * considering the new command. 226 * 227 * Returns the number of optimized commands or a negative error code 228 * 229 * Must run under exe_queue->lock 230 */ 231 exe_q_optimize optimize; 232 233 /** 234 * Run the next commands chunk (owner specific). 235 */ 236 exe_q_execute execute; 237 238 /** 239 * Return the exe_queue element containing the specific command 240 * if any. Otherwise return NULL. 241 */ 242 exe_q_get get; 243 }; 244 /***************** Classification verbs: Set/Del MAC/VLAN/VLAN-MAC ************/ 245 /* 246 * Element in the VLAN_MAC registry list having all currenty configured 247 * rules. 248 */ 249 struct bnx2x_vlan_mac_registry_elem { 250 struct list_head link; 251 252 /* 253 * Used to store the cam offset used for the mac/vlan/vlan-mac. 254 * Relevant for 57710 and 57711 only. VLANs and MACs share the 255 * same CAM for these chips. 256 */ 257 int cam_offset; 258 259 /* Needed for DEL and RESTORE flows */ 260 unsigned long vlan_mac_flags; 261 262 union bnx2x_classification_ramrod_data u; 263 }; 264 265 /* Bits representing VLAN_MAC commands specific flags */ 266 enum { 267 BNX2X_UC_LIST_MAC, 268 BNX2X_ETH_MAC, 269 BNX2X_ISCSI_ETH_MAC, 270 BNX2X_NETQ_ETH_MAC, 271 BNX2X_DONT_CONSUME_CAM_CREDIT, 272 BNX2X_DONT_CONSUME_CAM_CREDIT_DEST, 273 }; 274 275 struct bnx2x_vlan_mac_ramrod_params { 276 /* Object to run the command from */ 277 struct bnx2x_vlan_mac_obj *vlan_mac_obj; 278 279 /* General command flags: COMP_WAIT, etc. */ 280 unsigned long ramrod_flags; 281 282 /* Command specific configuration request */ 283 struct bnx2x_vlan_mac_data user_req; 284 }; 285 286 struct bnx2x_vlan_mac_obj { 287 struct bnx2x_raw_obj raw; 288 289 /* Bookkeeping list: will prevent the addition of already existing 290 * entries. 291 */ 292 struct list_head head; 293 294 /* TODO: Add it's initialization in the init functions */ 295 struct bnx2x_exe_queue_obj exe_queue; 296 297 /* MACs credit pool */ 298 struct bnx2x_credit_pool_obj *macs_pool; 299 300 /* VLANs credit pool */ 301 struct bnx2x_credit_pool_obj *vlans_pool; 302 303 /* RAMROD command to be used */ 304 int ramrod_cmd; 305 306 /* copy first n elements onto preallocated buffer 307 * 308 * @param n number of elements to get 309 * @param buf buffer preallocated by caller into which elements 310 * will be copied. Note elements are 4-byte aligned 311 * so buffer size must be able to accomodate the 312 * aligned elements. 313 * 314 * @return number of copied bytes 315 */ 316 int (*get_n_elements)(struct bnx2x *bp, struct bnx2x_vlan_mac_obj *o, 317 int n, u8 *buf); 318 319 /** 320 * Checks if ADD-ramrod with the given params may be performed. 321 * 322 * @return zero if the element may be added 323 */ 324 325 int (*check_add)(struct bnx2x *bp, 326 struct bnx2x_vlan_mac_obj *o, 327 union bnx2x_classification_ramrod_data *data); 328 329 /** 330 * Checks if DEL-ramrod with the given params may be performed. 331 * 332 * @return true if the element may be deleted 333 */ 334 struct bnx2x_vlan_mac_registry_elem * 335 (*check_del)(struct bnx2x *bp, 336 struct bnx2x_vlan_mac_obj *o, 337 union bnx2x_classification_ramrod_data *data); 338 339 /** 340 * Checks if DEL-ramrod with the given params may be performed. 341 * 342 * @return true if the element may be deleted 343 */ 344 bool (*check_move)(struct bnx2x *bp, 345 struct bnx2x_vlan_mac_obj *src_o, 346 struct bnx2x_vlan_mac_obj *dst_o, 347 union bnx2x_classification_ramrod_data *data); 348 349 /** 350 * Update the relevant credit object(s) (consume/return 351 * correspondingly). 352 */ 353 bool (*get_credit)(struct bnx2x_vlan_mac_obj *o); 354 bool (*put_credit)(struct bnx2x_vlan_mac_obj *o); 355 bool (*get_cam_offset)(struct bnx2x_vlan_mac_obj *o, int *offset); 356 bool (*put_cam_offset)(struct bnx2x_vlan_mac_obj *o, int offset); 357 358 /** 359 * Configures one rule in the ramrod data buffer. 360 */ 361 void (*set_one_rule)(struct bnx2x *bp, 362 struct bnx2x_vlan_mac_obj *o, 363 struct bnx2x_exeq_elem *elem, int rule_idx, 364 int cam_offset); 365 366 /** 367 * Delete all configured elements having the given 368 * vlan_mac_flags specification. Assumes no pending for 369 * execution commands. Will schedule all all currently 370 * configured MACs/VLANs/VLAN-MACs matching the vlan_mac_flags 371 * specification for deletion and will use the given 372 * ramrod_flags for the last DEL operation. 373 * 374 * @param bp 375 * @param o 376 * @param ramrod_flags RAMROD_XX flags 377 * 378 * @return 0 if the last operation has completed successfully 379 * and there are no more elements left, positive value 380 * if there are pending for completion commands, 381 * negative value in case of failure. 382 */ 383 int (*delete_all)(struct bnx2x *bp, 384 struct bnx2x_vlan_mac_obj *o, 385 unsigned long *vlan_mac_flags, 386 unsigned long *ramrod_flags); 387 388 /** 389 * Reconfigures the next MAC/VLAN/VLAN-MAC element from the previously 390 * configured elements list. 391 * 392 * @param bp 393 * @param p Command parameters (RAMROD_COMP_WAIT bit in 394 * ramrod_flags is only taken into an account) 395 * @param ppos a pointer to the cooky that should be given back in the 396 * next call to make function handle the next element. If 397 * *ppos is set to NULL it will restart the iterator. 398 * If returned *ppos == NULL this means that the last 399 * element has been handled. 400 * 401 * @return int 402 */ 403 int (*restore)(struct bnx2x *bp, 404 struct bnx2x_vlan_mac_ramrod_params *p, 405 struct bnx2x_vlan_mac_registry_elem **ppos); 406 407 /** 408 * Should be called on a completion arival. 409 * 410 * @param bp 411 * @param o 412 * @param cqe Completion element we are handling 413 * @param ramrod_flags if RAMROD_CONT is set the next bulk of 414 * pending commands will be executed. 415 * RAMROD_DRV_CLR_ONLY and RAMROD_RESTORE 416 * may also be set if needed. 417 * 418 * @return 0 if there are neither pending nor waiting for 419 * completion commands. Positive value if there are 420 * pending for execution or for completion commands. 421 * Negative value in case of an error (including an 422 * error in the cqe). 423 */ 424 int (*complete)(struct bnx2x *bp, struct bnx2x_vlan_mac_obj *o, 425 union event_ring_elem *cqe, 426 unsigned long *ramrod_flags); 427 428 /** 429 * Wait for completion of all commands. Don't schedule new ones, 430 * just wait. It assumes that the completion code will schedule 431 * for new commands. 432 */ 433 int (*wait)(struct bnx2x *bp, struct bnx2x_vlan_mac_obj *o); 434 }; 435 436 enum { 437 BNX2X_LLH_CAM_ISCSI_ETH_LINE = 0, 438 BNX2X_LLH_CAM_ETH_LINE, 439 BNX2X_LLH_CAM_MAX_PF_LINE = NIG_REG_LLH1_FUNC_MEM_SIZE / 2 440 }; 441 442 void bnx2x_set_mac_in_nig(struct bnx2x *bp, 443 bool add, unsigned char *dev_addr, int index); 444 445 /** RX_MODE verbs:DROP_ALL/ACCEPT_ALL/ACCEPT_ALL_MULTI/ACCEPT_ALL_VLAN/NORMAL */ 446 447 /* RX_MODE ramrod spesial flags: set in rx_mode_flags field in 448 * a bnx2x_rx_mode_ramrod_params. 449 */ 450 enum { 451 BNX2X_RX_MODE_FCOE_ETH, 452 BNX2X_RX_MODE_ISCSI_ETH, 453 }; 454 455 enum { 456 BNX2X_ACCEPT_UNICAST, 457 BNX2X_ACCEPT_MULTICAST, 458 BNX2X_ACCEPT_ALL_UNICAST, 459 BNX2X_ACCEPT_ALL_MULTICAST, 460 BNX2X_ACCEPT_BROADCAST, 461 BNX2X_ACCEPT_UNMATCHED, 462 BNX2X_ACCEPT_ANY_VLAN 463 }; 464 465 struct bnx2x_rx_mode_ramrod_params { 466 struct bnx2x_rx_mode_obj *rx_mode_obj; 467 unsigned long *pstate; 468 int state; 469 u8 cl_id; 470 u32 cid; 471 u8 func_id; 472 unsigned long ramrod_flags; 473 unsigned long rx_mode_flags; 474 475 /* 476 * rdata is either a pointer to eth_filter_rules_ramrod_data(e2) or to 477 * a tstorm_eth_mac_filter_config (e1x). 478 */ 479 void *rdata; 480 dma_addr_t rdata_mapping; 481 482 /* Rx mode settings */ 483 unsigned long rx_accept_flags; 484 485 /* internal switching settings */ 486 unsigned long tx_accept_flags; 487 }; 488 489 struct bnx2x_rx_mode_obj { 490 int (*config_rx_mode)(struct bnx2x *bp, 491 struct bnx2x_rx_mode_ramrod_params *p); 492 493 int (*wait_comp)(struct bnx2x *bp, 494 struct bnx2x_rx_mode_ramrod_params *p); 495 }; 496 497 /********************** Set multicast group ***********************************/ 498 499 struct bnx2x_mcast_list_elem { 500 struct list_head link; 501 u8 *mac; 502 }; 503 504 union bnx2x_mcast_config_data { 505 u8 *mac; 506 u8 bin; /* used in a RESTORE flow */ 507 }; 508 509 struct bnx2x_mcast_ramrod_params { 510 struct bnx2x_mcast_obj *mcast_obj; 511 512 /* Relevant options are RAMROD_COMP_WAIT and RAMROD_DRV_CLR_ONLY */ 513 unsigned long ramrod_flags; 514 515 struct list_head mcast_list; /* list of struct bnx2x_mcast_list_elem */ 516 /** TODO: 517 * - rename it to macs_num. 518 * - Add a new command type for handling pending commands 519 * (remove "zero semantics"). 520 * 521 * Length of mcast_list. If zero and ADD_CONT command - post 522 * pending commands. 523 */ 524 int mcast_list_len; 525 }; 526 527 enum bnx2x_mcast_cmd { 528 BNX2X_MCAST_CMD_ADD, 529 BNX2X_MCAST_CMD_CONT, 530 BNX2X_MCAST_CMD_DEL, 531 BNX2X_MCAST_CMD_RESTORE, 532 }; 533 534 struct bnx2x_mcast_obj { 535 struct bnx2x_raw_obj raw; 536 537 union { 538 struct { 539 #define BNX2X_MCAST_BINS_NUM 256 540 #define BNX2X_MCAST_VEC_SZ (BNX2X_MCAST_BINS_NUM / 64) 541 u64 vec[BNX2X_MCAST_VEC_SZ]; 542 543 /** Number of BINs to clear. Should be updated 544 * immediately when a command arrives in order to 545 * properly create DEL commands. 546 */ 547 int num_bins_set; 548 } aprox_match; 549 550 struct { 551 struct list_head macs; 552 int num_macs_set; 553 } exact_match; 554 } registry; 555 556 /* Pending commands */ 557 struct list_head pending_cmds_head; 558 559 /* A state that is set in raw.pstate, when there are pending commands */ 560 int sched_state; 561 562 /* Maximal number of mcast MACs configured in one command */ 563 int max_cmd_len; 564 565 /* Total number of currently pending MACs to configure: both 566 * in the pending commands list and in the current command. 567 */ 568 int total_pending_num; 569 570 u8 engine_id; 571 572 /** 573 * @param cmd command to execute (BNX2X_MCAST_CMD_X, see above) 574 */ 575 int (*config_mcast)(struct bnx2x *bp, 576 struct bnx2x_mcast_ramrod_params *p, 577 enum bnx2x_mcast_cmd cmd); 578 579 /** 580 * Fills the ramrod data during the RESTORE flow. 581 * 582 * @param bp 583 * @param o 584 * @param start_idx Registry index to start from 585 * @param rdata_idx Index in the ramrod data to start from 586 * 587 * @return -1 if we handled the whole registry or index of the last 588 * handled registry element. 589 */ 590 int (*hdl_restore)(struct bnx2x *bp, struct bnx2x_mcast_obj *o, 591 int start_bin, int *rdata_idx); 592 593 int (*enqueue_cmd)(struct bnx2x *bp, struct bnx2x_mcast_obj *o, 594 struct bnx2x_mcast_ramrod_params *p, 595 enum bnx2x_mcast_cmd cmd); 596 597 void (*set_one_rule)(struct bnx2x *bp, 598 struct bnx2x_mcast_obj *o, int idx, 599 union bnx2x_mcast_config_data *cfg_data, 600 enum bnx2x_mcast_cmd cmd); 601 602 /** Checks if there are more mcast MACs to be set or a previous 603 * command is still pending. 604 */ 605 bool (*check_pending)(struct bnx2x_mcast_obj *o); 606 607 /** 608 * Set/Clear/Check SCHEDULED state of the object 609 */ 610 void (*set_sched)(struct bnx2x_mcast_obj *o); 611 void (*clear_sched)(struct bnx2x_mcast_obj *o); 612 bool (*check_sched)(struct bnx2x_mcast_obj *o); 613 614 /* Wait until all pending commands complete */ 615 int (*wait_comp)(struct bnx2x *bp, struct bnx2x_mcast_obj *o); 616 617 /** 618 * Handle the internal object counters needed for proper 619 * commands handling. Checks that the provided parameters are 620 * feasible. 621 */ 622 int (*validate)(struct bnx2x *bp, 623 struct bnx2x_mcast_ramrod_params *p, 624 enum bnx2x_mcast_cmd cmd); 625 626 /** 627 * Restore the values of internal counters in case of a failure. 628 */ 629 void (*revert)(struct bnx2x *bp, 630 struct bnx2x_mcast_ramrod_params *p, 631 int old_num_bins); 632 633 int (*get_registry_size)(struct bnx2x_mcast_obj *o); 634 void (*set_registry_size)(struct bnx2x_mcast_obj *o, int n); 635 }; 636 637 /*************************** Credit handling **********************************/ 638 struct bnx2x_credit_pool_obj { 639 640 /* Current amount of credit in the pool */ 641 atomic_t credit; 642 643 /* Maximum allowed credit. put() will check against it. */ 644 int pool_sz; 645 646 /* 647 * Allocate a pool table statically. 648 * 649 * Currently the mamimum allowed size is MAX_MAC_CREDIT_E2(272) 650 * 651 * The set bit in the table will mean that the entry is available. 652 */ 653 #define BNX2X_POOL_VEC_SIZE (MAX_MAC_CREDIT_E2 / 64) 654 u64 pool_mirror[BNX2X_POOL_VEC_SIZE]; 655 656 /* Base pool offset (initialized differently */ 657 int base_pool_offset; 658 659 /** 660 * Get the next free pool entry. 661 * 662 * @return true if there was a free entry in the pool 663 */ 664 bool (*get_entry)(struct bnx2x_credit_pool_obj *o, int *entry); 665 666 /** 667 * Return the entry back to the pool. 668 * 669 * @return true if entry is legal and has been successfully 670 * returned to the pool. 671 */ 672 bool (*put_entry)(struct bnx2x_credit_pool_obj *o, int entry); 673 674 /** 675 * Get the requested amount of credit from the pool. 676 * 677 * @param cnt Amount of requested credit 678 * @return true if the operation is successful 679 */ 680 bool (*get)(struct bnx2x_credit_pool_obj *o, int cnt); 681 682 /** 683 * Returns the credit to the pool. 684 * 685 * @param cnt Amount of credit to return 686 * @return true if the operation is successful 687 */ 688 bool (*put)(struct bnx2x_credit_pool_obj *o, int cnt); 689 690 /** 691 * Reads the current amount of credit. 692 */ 693 int (*check)(struct bnx2x_credit_pool_obj *o); 694 }; 695 696 /*************************** RSS configuration ********************************/ 697 enum { 698 /* RSS_MODE bits are mutually exclusive */ 699 BNX2X_RSS_MODE_DISABLED, 700 BNX2X_RSS_MODE_REGULAR, 701 702 BNX2X_RSS_SET_SRCH, /* Setup searcher, E1x specific flag */ 703 704 BNX2X_RSS_IPV4, 705 BNX2X_RSS_IPV4_TCP, 706 BNX2X_RSS_IPV4_UDP, 707 BNX2X_RSS_IPV6, 708 BNX2X_RSS_IPV6_TCP, 709 BNX2X_RSS_IPV6_UDP, 710 }; 711 712 struct bnx2x_config_rss_params { 713 struct bnx2x_rss_config_obj *rss_obj; 714 715 /* may have RAMROD_COMP_WAIT set only */ 716 unsigned long ramrod_flags; 717 718 /* BNX2X_RSS_X bits */ 719 unsigned long rss_flags; 720 721 /* Number hash bits to take into an account */ 722 u8 rss_result_mask; 723 724 /* Indirection table */ 725 u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE]; 726 727 /* RSS hash values */ 728 u32 rss_key[10]; 729 730 /* valid only iff BNX2X_RSS_UPDATE_TOE is set */ 731 u16 toe_rss_bitmap; 732 }; 733 734 struct bnx2x_rss_config_obj { 735 struct bnx2x_raw_obj raw; 736 737 /* RSS engine to use */ 738 u8 engine_id; 739 740 /* Last configured indirection table */ 741 u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE]; 742 743 /* flags for enabling 4-tupple hash on UDP */ 744 u8 udp_rss_v4; 745 u8 udp_rss_v6; 746 747 int (*config_rss)(struct bnx2x *bp, 748 struct bnx2x_config_rss_params *p); 749 }; 750 751 /*********************** Queue state update ***********************************/ 752 753 /* UPDATE command options */ 754 enum { 755 BNX2X_Q_UPDATE_IN_VLAN_REM, 756 BNX2X_Q_UPDATE_IN_VLAN_REM_CHNG, 757 BNX2X_Q_UPDATE_OUT_VLAN_REM, 758 BNX2X_Q_UPDATE_OUT_VLAN_REM_CHNG, 759 BNX2X_Q_UPDATE_ANTI_SPOOF, 760 BNX2X_Q_UPDATE_ANTI_SPOOF_CHNG, 761 BNX2X_Q_UPDATE_ACTIVATE, 762 BNX2X_Q_UPDATE_ACTIVATE_CHNG, 763 BNX2X_Q_UPDATE_DEF_VLAN_EN, 764 BNX2X_Q_UPDATE_DEF_VLAN_EN_CHNG, 765 BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG, 766 BNX2X_Q_UPDATE_SILENT_VLAN_REM 767 }; 768 769 /* Allowed Queue states */ 770 enum bnx2x_q_state { 771 BNX2X_Q_STATE_RESET, 772 BNX2X_Q_STATE_INITIALIZED, 773 BNX2X_Q_STATE_ACTIVE, 774 BNX2X_Q_STATE_MULTI_COS, 775 BNX2X_Q_STATE_MCOS_TERMINATED, 776 BNX2X_Q_STATE_INACTIVE, 777 BNX2X_Q_STATE_STOPPED, 778 BNX2X_Q_STATE_TERMINATED, 779 BNX2X_Q_STATE_FLRED, 780 BNX2X_Q_STATE_MAX, 781 }; 782 783 /* Allowed Queue states */ 784 enum bnx2x_q_logical_state { 785 BNX2X_Q_LOGICAL_STATE_ACTIVE, 786 BNX2X_Q_LOGICAL_STATE_STOPPED, 787 }; 788 789 /* Allowed commands */ 790 enum bnx2x_queue_cmd { 791 BNX2X_Q_CMD_INIT, 792 BNX2X_Q_CMD_SETUP, 793 BNX2X_Q_CMD_SETUP_TX_ONLY, 794 BNX2X_Q_CMD_DEACTIVATE, 795 BNX2X_Q_CMD_ACTIVATE, 796 BNX2X_Q_CMD_UPDATE, 797 BNX2X_Q_CMD_UPDATE_TPA, 798 BNX2X_Q_CMD_HALT, 799 BNX2X_Q_CMD_CFC_DEL, 800 BNX2X_Q_CMD_TERMINATE, 801 BNX2X_Q_CMD_EMPTY, 802 BNX2X_Q_CMD_MAX, 803 }; 804 805 /* queue SETUP + INIT flags */ 806 enum { 807 BNX2X_Q_FLG_TPA, 808 BNX2X_Q_FLG_TPA_IPV6, 809 BNX2X_Q_FLG_TPA_GRO, 810 BNX2X_Q_FLG_STATS, 811 BNX2X_Q_FLG_ZERO_STATS, 812 BNX2X_Q_FLG_ACTIVE, 813 BNX2X_Q_FLG_OV, 814 BNX2X_Q_FLG_VLAN, 815 BNX2X_Q_FLG_COS, 816 BNX2X_Q_FLG_HC, 817 BNX2X_Q_FLG_HC_EN, 818 BNX2X_Q_FLG_DHC, 819 BNX2X_Q_FLG_FCOE, 820 BNX2X_Q_FLG_LEADING_RSS, 821 BNX2X_Q_FLG_MCAST, 822 BNX2X_Q_FLG_DEF_VLAN, 823 BNX2X_Q_FLG_TX_SWITCH, 824 BNX2X_Q_FLG_TX_SEC, 825 BNX2X_Q_FLG_ANTI_SPOOF, 826 BNX2X_Q_FLG_SILENT_VLAN_REM, 827 BNX2X_Q_FLG_FORCE_DEFAULT_PRI 828 }; 829 830 /* Queue type options: queue type may be a compination of below. */ 831 enum bnx2x_q_type { 832 /** TODO: Consider moving both these flags into the init() 833 * ramrod params. 834 */ 835 BNX2X_Q_TYPE_HAS_RX, 836 BNX2X_Q_TYPE_HAS_TX, 837 }; 838 839 #define BNX2X_PRIMARY_CID_INDEX 0 840 #define BNX2X_MULTI_TX_COS_E1X 3 /* QM only */ 841 #define BNX2X_MULTI_TX_COS_E2_E3A0 2 842 #define BNX2X_MULTI_TX_COS_E3B0 3 843 #define BNX2X_MULTI_TX_COS 3 /* Maximum possible */ 844 845 846 struct bnx2x_queue_init_params { 847 struct { 848 unsigned long flags; 849 u16 hc_rate; 850 u8 fw_sb_id; 851 u8 sb_cq_index; 852 } tx; 853 854 struct { 855 unsigned long flags; 856 u16 hc_rate; 857 u8 fw_sb_id; 858 u8 sb_cq_index; 859 } rx; 860 861 /* CID context in the host memory */ 862 struct eth_context *cxts[BNX2X_MULTI_TX_COS]; 863 864 /* maximum number of cos supported by hardware */ 865 u8 max_cos; 866 }; 867 868 struct bnx2x_queue_terminate_params { 869 /* index within the tx_only cids of this queue object */ 870 u8 cid_index; 871 }; 872 873 struct bnx2x_queue_cfc_del_params { 874 /* index within the tx_only cids of this queue object */ 875 u8 cid_index; 876 }; 877 878 struct bnx2x_queue_update_params { 879 unsigned long update_flags; /* BNX2X_Q_UPDATE_XX bits */ 880 u16 def_vlan; 881 u16 silent_removal_value; 882 u16 silent_removal_mask; 883 /* index within the tx_only cids of this queue object */ 884 u8 cid_index; 885 }; 886 887 struct rxq_pause_params { 888 u16 bd_th_lo; 889 u16 bd_th_hi; 890 u16 rcq_th_lo; 891 u16 rcq_th_hi; 892 u16 sge_th_lo; /* valid iff BNX2X_Q_FLG_TPA */ 893 u16 sge_th_hi; /* valid iff BNX2X_Q_FLG_TPA */ 894 u16 pri_map; 895 }; 896 897 /* general */ 898 struct bnx2x_general_setup_params { 899 /* valid iff BNX2X_Q_FLG_STATS */ 900 u8 stat_id; 901 902 u8 spcl_id; 903 u16 mtu; 904 u8 cos; 905 }; 906 907 struct bnx2x_rxq_setup_params { 908 /* dma */ 909 dma_addr_t dscr_map; 910 dma_addr_t sge_map; 911 dma_addr_t rcq_map; 912 dma_addr_t rcq_np_map; 913 914 u16 drop_flags; 915 u16 buf_sz; 916 u8 fw_sb_id; 917 u8 cl_qzone_id; 918 919 /* valid iff BNX2X_Q_FLG_TPA */ 920 u16 tpa_agg_sz; 921 u16 sge_buf_sz; 922 u8 max_sges_pkt; 923 u8 max_tpa_queues; 924 u8 rss_engine_id; 925 926 /* valid iff BNX2X_Q_FLG_MCAST */ 927 u8 mcast_engine_id; 928 929 u8 cache_line_log; 930 931 u8 sb_cq_index; 932 933 /* valid iff BXN2X_Q_FLG_SILENT_VLAN_REM */ 934 u16 silent_removal_value; 935 u16 silent_removal_mask; 936 }; 937 938 struct bnx2x_txq_setup_params { 939 /* dma */ 940 dma_addr_t dscr_map; 941 942 u8 fw_sb_id; 943 u8 sb_cq_index; 944 u8 cos; /* valid iff BNX2X_Q_FLG_COS */ 945 u16 traffic_type; 946 /* equals to the leading rss client id, used for TX classification*/ 947 u8 tss_leading_cl_id; 948 949 /* valid iff BNX2X_Q_FLG_DEF_VLAN */ 950 u16 default_vlan; 951 }; 952 953 struct bnx2x_queue_setup_params { 954 struct bnx2x_general_setup_params gen_params; 955 struct bnx2x_txq_setup_params txq_params; 956 struct bnx2x_rxq_setup_params rxq_params; 957 struct rxq_pause_params pause_params; 958 unsigned long flags; 959 }; 960 961 struct bnx2x_queue_setup_tx_only_params { 962 struct bnx2x_general_setup_params gen_params; 963 struct bnx2x_txq_setup_params txq_params; 964 unsigned long flags; 965 /* index within the tx_only cids of this queue object */ 966 u8 cid_index; 967 }; 968 969 struct bnx2x_queue_state_params { 970 struct bnx2x_queue_sp_obj *q_obj; 971 972 /* Current command */ 973 enum bnx2x_queue_cmd cmd; 974 975 /* may have RAMROD_COMP_WAIT set only */ 976 unsigned long ramrod_flags; 977 978 /* Params according to the current command */ 979 union { 980 struct bnx2x_queue_update_params update; 981 struct bnx2x_queue_setup_params setup; 982 struct bnx2x_queue_init_params init; 983 struct bnx2x_queue_setup_tx_only_params tx_only; 984 struct bnx2x_queue_terminate_params terminate; 985 struct bnx2x_queue_cfc_del_params cfc_del; 986 } params; 987 }; 988 989 struct bnx2x_viflist_params { 990 u8 echo_res; 991 u8 func_bit_map_res; 992 }; 993 994 struct bnx2x_queue_sp_obj { 995 u32 cids[BNX2X_MULTI_TX_COS]; 996 u8 cl_id; 997 u8 func_id; 998 999 /* 1000 * number of traffic classes supported by queue. 1001 * The primary connection of the queue suppotrs the first traffic 1002 * class. Any further traffic class is suppoted by a tx-only 1003 * connection. 1004 * 1005 * Therefore max_cos is also a number of valid entries in the cids 1006 * array. 1007 */ 1008 u8 max_cos; 1009 u8 num_tx_only, next_tx_only; 1010 1011 enum bnx2x_q_state state, next_state; 1012 1013 /* bits from enum bnx2x_q_type */ 1014 unsigned long type; 1015 1016 /* BNX2X_Q_CMD_XX bits. This object implements "one 1017 * pending" paradigm but for debug and tracing purposes it's 1018 * more convinient to have different bits for different 1019 * commands. 1020 */ 1021 unsigned long pending; 1022 1023 /* Buffer to use as a ramrod data and its mapping */ 1024 void *rdata; 1025 dma_addr_t rdata_mapping; 1026 1027 /** 1028 * Performs one state change according to the given parameters. 1029 * 1030 * @return 0 in case of success and negative value otherwise. 1031 */ 1032 int (*send_cmd)(struct bnx2x *bp, 1033 struct bnx2x_queue_state_params *params); 1034 1035 /** 1036 * Sets the pending bit according to the requested transition. 1037 */ 1038 int (*set_pending)(struct bnx2x_queue_sp_obj *o, 1039 struct bnx2x_queue_state_params *params); 1040 1041 /** 1042 * Checks that the requested state transition is legal. 1043 */ 1044 int (*check_transition)(struct bnx2x *bp, 1045 struct bnx2x_queue_sp_obj *o, 1046 struct bnx2x_queue_state_params *params); 1047 1048 /** 1049 * Completes the pending command. 1050 */ 1051 int (*complete_cmd)(struct bnx2x *bp, 1052 struct bnx2x_queue_sp_obj *o, 1053 enum bnx2x_queue_cmd); 1054 1055 int (*wait_comp)(struct bnx2x *bp, 1056 struct bnx2x_queue_sp_obj *o, 1057 enum bnx2x_queue_cmd cmd); 1058 }; 1059 1060 /********************** Function state update *********************************/ 1061 /* Allowed Function states */ 1062 enum bnx2x_func_state { 1063 BNX2X_F_STATE_RESET, 1064 BNX2X_F_STATE_INITIALIZED, 1065 BNX2X_F_STATE_STARTED, 1066 BNX2X_F_STATE_TX_STOPPED, 1067 BNX2X_F_STATE_MAX, 1068 }; 1069 1070 /* Allowed Function commands */ 1071 enum bnx2x_func_cmd { 1072 BNX2X_F_CMD_HW_INIT, 1073 BNX2X_F_CMD_START, 1074 BNX2X_F_CMD_STOP, 1075 BNX2X_F_CMD_HW_RESET, 1076 BNX2X_F_CMD_AFEX_UPDATE, 1077 BNX2X_F_CMD_AFEX_VIFLISTS, 1078 BNX2X_F_CMD_TX_STOP, 1079 BNX2X_F_CMD_TX_START, 1080 BNX2X_F_CMD_SWITCH_UPDATE, 1081 BNX2X_F_CMD_MAX, 1082 }; 1083 1084 struct bnx2x_func_hw_init_params { 1085 /* A load phase returned by MCP. 1086 * 1087 * May be: 1088 * FW_MSG_CODE_DRV_LOAD_COMMON_CHIP 1089 * FW_MSG_CODE_DRV_LOAD_COMMON 1090 * FW_MSG_CODE_DRV_LOAD_PORT 1091 * FW_MSG_CODE_DRV_LOAD_FUNCTION 1092 */ 1093 u32 load_phase; 1094 }; 1095 1096 struct bnx2x_func_hw_reset_params { 1097 /* A load phase returned by MCP. 1098 * 1099 * May be: 1100 * FW_MSG_CODE_DRV_LOAD_COMMON_CHIP 1101 * FW_MSG_CODE_DRV_LOAD_COMMON 1102 * FW_MSG_CODE_DRV_LOAD_PORT 1103 * FW_MSG_CODE_DRV_LOAD_FUNCTION 1104 */ 1105 u32 reset_phase; 1106 }; 1107 1108 struct bnx2x_func_start_params { 1109 /* Multi Function mode: 1110 * - Single Function 1111 * - Switch Dependent 1112 * - Switch Independent 1113 */ 1114 u16 mf_mode; 1115 1116 /* Switch Dependent mode outer VLAN tag */ 1117 u16 sd_vlan_tag; 1118 1119 /* Function cos mode */ 1120 u8 network_cos_mode; 1121 }; 1122 1123 struct bnx2x_func_switch_update_params { 1124 u8 suspend; 1125 }; 1126 1127 struct bnx2x_func_afex_update_params { 1128 u16 vif_id; 1129 u16 afex_default_vlan; 1130 u8 allowed_priorities; 1131 }; 1132 1133 struct bnx2x_func_afex_viflists_params { 1134 u16 vif_list_index; 1135 u8 func_bit_map; 1136 u8 afex_vif_list_command; 1137 u8 func_to_clear; 1138 }; 1139 struct bnx2x_func_tx_start_params { 1140 struct priority_cos traffic_type_to_priority_cos[MAX_TRAFFIC_TYPES]; 1141 u8 dcb_enabled; 1142 u8 dcb_version; 1143 u8 dont_add_pri_0_en; 1144 }; 1145 1146 struct bnx2x_func_state_params { 1147 struct bnx2x_func_sp_obj *f_obj; 1148 1149 /* Current command */ 1150 enum bnx2x_func_cmd cmd; 1151 1152 /* may have RAMROD_COMP_WAIT set only */ 1153 unsigned long ramrod_flags; 1154 1155 /* Params according to the current command */ 1156 union { 1157 struct bnx2x_func_hw_init_params hw_init; 1158 struct bnx2x_func_hw_reset_params hw_reset; 1159 struct bnx2x_func_start_params start; 1160 struct bnx2x_func_switch_update_params switch_update; 1161 struct bnx2x_func_afex_update_params afex_update; 1162 struct bnx2x_func_afex_viflists_params afex_viflists; 1163 struct bnx2x_func_tx_start_params tx_start; 1164 } params; 1165 }; 1166 1167 struct bnx2x_func_sp_drv_ops { 1168 /* Init tool + runtime initialization: 1169 * - Common Chip 1170 * - Common (per Path) 1171 * - Port 1172 * - Function phases 1173 */ 1174 int (*init_hw_cmn_chip)(struct bnx2x *bp); 1175 int (*init_hw_cmn)(struct bnx2x *bp); 1176 int (*init_hw_port)(struct bnx2x *bp); 1177 int (*init_hw_func)(struct bnx2x *bp); 1178 1179 /* Reset Function HW: Common, Port, Function phases. */ 1180 void (*reset_hw_cmn)(struct bnx2x *bp); 1181 void (*reset_hw_port)(struct bnx2x *bp); 1182 void (*reset_hw_func)(struct bnx2x *bp); 1183 1184 /* Init/Free GUNZIP resources */ 1185 int (*gunzip_init)(struct bnx2x *bp); 1186 void (*gunzip_end)(struct bnx2x *bp); 1187 1188 /* Prepare/Release FW resources */ 1189 int (*init_fw)(struct bnx2x *bp); 1190 void (*release_fw)(struct bnx2x *bp); 1191 }; 1192 1193 struct bnx2x_func_sp_obj { 1194 enum bnx2x_func_state state, next_state; 1195 1196 /* BNX2X_FUNC_CMD_XX bits. This object implements "one 1197 * pending" paradigm but for debug and tracing purposes it's 1198 * more convinient to have different bits for different 1199 * commands. 1200 */ 1201 unsigned long pending; 1202 1203 /* Buffer to use as a ramrod data and its mapping */ 1204 void *rdata; 1205 dma_addr_t rdata_mapping; 1206 1207 /* Buffer to use as a afex ramrod data and its mapping. 1208 * This can't be same rdata as above because afex ramrod requests 1209 * can arrive to the object in parallel to other ramrod requests. 1210 */ 1211 void *afex_rdata; 1212 dma_addr_t afex_rdata_mapping; 1213 1214 /* this mutex validates that when pending flag is taken, the next 1215 * ramrod to be sent will be the one set the pending bit 1216 */ 1217 struct mutex one_pending_mutex; 1218 1219 /* Driver interface */ 1220 struct bnx2x_func_sp_drv_ops *drv; 1221 1222 /** 1223 * Performs one state change according to the given parameters. 1224 * 1225 * @return 0 in case of success and negative value otherwise. 1226 */ 1227 int (*send_cmd)(struct bnx2x *bp, 1228 struct bnx2x_func_state_params *params); 1229 1230 /** 1231 * Checks that the requested state transition is legal. 1232 */ 1233 int (*check_transition)(struct bnx2x *bp, 1234 struct bnx2x_func_sp_obj *o, 1235 struct bnx2x_func_state_params *params); 1236 1237 /** 1238 * Completes the pending command. 1239 */ 1240 int (*complete_cmd)(struct bnx2x *bp, 1241 struct bnx2x_func_sp_obj *o, 1242 enum bnx2x_func_cmd cmd); 1243 1244 int (*wait_comp)(struct bnx2x *bp, struct bnx2x_func_sp_obj *o, 1245 enum bnx2x_func_cmd cmd); 1246 }; 1247 1248 /********************** Interfaces ********************************************/ 1249 /* Queueable objects set */ 1250 union bnx2x_qable_obj { 1251 struct bnx2x_vlan_mac_obj vlan_mac; 1252 }; 1253 /************** Function state update *********/ 1254 void bnx2x_init_func_obj(struct bnx2x *bp, 1255 struct bnx2x_func_sp_obj *obj, 1256 void *rdata, dma_addr_t rdata_mapping, 1257 void *afex_rdata, dma_addr_t afex_rdata_mapping, 1258 struct bnx2x_func_sp_drv_ops *drv_iface); 1259 1260 int bnx2x_func_state_change(struct bnx2x *bp, 1261 struct bnx2x_func_state_params *params); 1262 1263 enum bnx2x_func_state bnx2x_func_get_state(struct bnx2x *bp, 1264 struct bnx2x_func_sp_obj *o); 1265 /******************* Queue State **************/ 1266 void bnx2x_init_queue_obj(struct bnx2x *bp, 1267 struct bnx2x_queue_sp_obj *obj, u8 cl_id, u32 *cids, 1268 u8 cid_cnt, u8 func_id, void *rdata, 1269 dma_addr_t rdata_mapping, unsigned long type); 1270 1271 int bnx2x_queue_state_change(struct bnx2x *bp, 1272 struct bnx2x_queue_state_params *params); 1273 1274 int bnx2x_get_q_logical_state(struct bnx2x *bp, 1275 struct bnx2x_queue_sp_obj *obj); 1276 1277 /********************* VLAN-MAC ****************/ 1278 void bnx2x_init_mac_obj(struct bnx2x *bp, 1279 struct bnx2x_vlan_mac_obj *mac_obj, 1280 u8 cl_id, u32 cid, u8 func_id, void *rdata, 1281 dma_addr_t rdata_mapping, int state, 1282 unsigned long *pstate, bnx2x_obj_type type, 1283 struct bnx2x_credit_pool_obj *macs_pool); 1284 1285 void bnx2x_init_vlan_obj(struct bnx2x *bp, 1286 struct bnx2x_vlan_mac_obj *vlan_obj, 1287 u8 cl_id, u32 cid, u8 func_id, void *rdata, 1288 dma_addr_t rdata_mapping, int state, 1289 unsigned long *pstate, bnx2x_obj_type type, 1290 struct bnx2x_credit_pool_obj *vlans_pool); 1291 1292 void bnx2x_init_vlan_mac_obj(struct bnx2x *bp, 1293 struct bnx2x_vlan_mac_obj *vlan_mac_obj, 1294 u8 cl_id, u32 cid, u8 func_id, void *rdata, 1295 dma_addr_t rdata_mapping, int state, 1296 unsigned long *pstate, bnx2x_obj_type type, 1297 struct bnx2x_credit_pool_obj *macs_pool, 1298 struct bnx2x_credit_pool_obj *vlans_pool); 1299 1300 int bnx2x_config_vlan_mac(struct bnx2x *bp, 1301 struct bnx2x_vlan_mac_ramrod_params *p); 1302 1303 int bnx2x_vlan_mac_move(struct bnx2x *bp, 1304 struct bnx2x_vlan_mac_ramrod_params *p, 1305 struct bnx2x_vlan_mac_obj *dest_o); 1306 1307 /********************* RX MODE ****************/ 1308 1309 void bnx2x_init_rx_mode_obj(struct bnx2x *bp, 1310 struct bnx2x_rx_mode_obj *o); 1311 1312 /** 1313 * bnx2x_config_rx_mode - Send and RX_MODE ramrod according to the provided parameters. 1314 * 1315 * @p: Command parameters 1316 * 1317 * Return: 0 - if operation was successfull and there is no pending completions, 1318 * positive number - if there are pending completions, 1319 * negative - if there were errors 1320 */ 1321 int bnx2x_config_rx_mode(struct bnx2x *bp, 1322 struct bnx2x_rx_mode_ramrod_params *p); 1323 1324 /****************** MULTICASTS ****************/ 1325 1326 void bnx2x_init_mcast_obj(struct bnx2x *bp, 1327 struct bnx2x_mcast_obj *mcast_obj, 1328 u8 mcast_cl_id, u32 mcast_cid, u8 func_id, 1329 u8 engine_id, void *rdata, dma_addr_t rdata_mapping, 1330 int state, unsigned long *pstate, 1331 bnx2x_obj_type type); 1332 1333 /** 1334 * bnx2x_config_mcast - Configure multicast MACs list. 1335 * 1336 * @cmd: command to execute: BNX2X_MCAST_CMD_X 1337 * 1338 * May configure a new list 1339 * provided in p->mcast_list (BNX2X_MCAST_CMD_ADD), clean up 1340 * (BNX2X_MCAST_CMD_DEL) or restore (BNX2X_MCAST_CMD_RESTORE) a current 1341 * configuration, continue to execute the pending commands 1342 * (BNX2X_MCAST_CMD_CONT). 1343 * 1344 * If previous command is still pending or if number of MACs to 1345 * configure is more that maximum number of MACs in one command, 1346 * the current command will be enqueued to the tail of the 1347 * pending commands list. 1348 * 1349 * Return: 0 is operation was successfull and there are no pending completions, 1350 * negative if there were errors, positive if there are pending 1351 * completions. 1352 */ 1353 int bnx2x_config_mcast(struct bnx2x *bp, 1354 struct bnx2x_mcast_ramrod_params *p, 1355 enum bnx2x_mcast_cmd cmd); 1356 1357 /****************** CREDIT POOL ****************/ 1358 void bnx2x_init_mac_credit_pool(struct bnx2x *bp, 1359 struct bnx2x_credit_pool_obj *p, u8 func_id, 1360 u8 func_num); 1361 void bnx2x_init_vlan_credit_pool(struct bnx2x *bp, 1362 struct bnx2x_credit_pool_obj *p, u8 func_id, 1363 u8 func_num); 1364 1365 1366 /****************** RSS CONFIGURATION ****************/ 1367 void bnx2x_init_rss_config_obj(struct bnx2x *bp, 1368 struct bnx2x_rss_config_obj *rss_obj, 1369 u8 cl_id, u32 cid, u8 func_id, u8 engine_id, 1370 void *rdata, dma_addr_t rdata_mapping, 1371 int state, unsigned long *pstate, 1372 bnx2x_obj_type type); 1373 1374 /** 1375 * bnx2x_config_rss - Updates RSS configuration according to provided parameters 1376 * 1377 * Return: 0 in case of success 1378 */ 1379 int bnx2x_config_rss(struct bnx2x *bp, 1380 struct bnx2x_config_rss_params *p); 1381 1382 /** 1383 * bnx2x_get_rss_ind_table - Return the current ind_table configuration. 1384 * 1385 * @ind_table: buffer to fill with the current indirection 1386 * table content. Should be at least 1387 * T_ETH_INDIRECTION_TABLE_SIZE bytes long. 1388 */ 1389 void bnx2x_get_rss_ind_table(struct bnx2x_rss_config_obj *rss_obj, 1390 u8 *ind_table); 1391 1392 #endif /* BNX2X_SP_VERBS */ 1393