1 /* bnx2x_sp.h: Broadcom Everest network driver. 2 * 3 * Copyright (c) 2011-2013 Broadcom Corporation 4 * 5 * Unless you and Broadcom execute a separate written software license 6 * agreement governing use of this software, this software is licensed to you 7 * under the terms of the GNU General Public License version 2, available 8 * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL"). 9 * 10 * Notwithstanding the above, under no circumstances may you combine this 11 * software in any way with any other Broadcom software provided under a 12 * license other than the GPL, without Broadcom's express prior written 13 * consent. 14 * 15 * Maintained by: Eilon Greenstein <eilong@broadcom.com> 16 * Written by: Vladislav Zolotarov 17 * 18 */ 19 #ifndef BNX2X_SP_VERBS 20 #define BNX2X_SP_VERBS 21 22 struct bnx2x; 23 struct eth_context; 24 25 /* Bits representing general command's configuration */ 26 enum { 27 RAMROD_TX, 28 RAMROD_RX, 29 /* Wait until all pending commands complete */ 30 RAMROD_COMP_WAIT, 31 /* Don't send a ramrod, only update a registry */ 32 RAMROD_DRV_CLR_ONLY, 33 /* Configure HW according to the current object state */ 34 RAMROD_RESTORE, 35 /* Execute the next command now */ 36 RAMROD_EXEC, 37 /* 38 * Don't add a new command and continue execution of posponed 39 * commands. If not set a new command will be added to the 40 * pending commands list. 41 */ 42 RAMROD_CONT, 43 /* If there is another pending ramrod, wait until it finishes and 44 * re-try to submit this one. This flag can be set only in sleepable 45 * context, and should not be set from the context that completes the 46 * ramrods as deadlock will occur. 47 */ 48 RAMROD_RETRY, 49 }; 50 51 typedef enum { 52 BNX2X_OBJ_TYPE_RX, 53 BNX2X_OBJ_TYPE_TX, 54 BNX2X_OBJ_TYPE_RX_TX, 55 } bnx2x_obj_type; 56 57 /* Public slow path states */ 58 enum { 59 BNX2X_FILTER_MAC_PENDING, 60 BNX2X_FILTER_VLAN_PENDING, 61 BNX2X_FILTER_VLAN_MAC_PENDING, 62 BNX2X_FILTER_RX_MODE_PENDING, 63 BNX2X_FILTER_RX_MODE_SCHED, 64 BNX2X_FILTER_ISCSI_ETH_START_SCHED, 65 BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, 66 BNX2X_FILTER_FCOE_ETH_START_SCHED, 67 BNX2X_FILTER_FCOE_ETH_STOP_SCHED, 68 BNX2X_FILTER_MCAST_PENDING, 69 BNX2X_FILTER_MCAST_SCHED, 70 BNX2X_FILTER_RSS_CONF_PENDING, 71 BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, 72 BNX2X_AFEX_PENDING_VIFSET_MCP_ACK 73 }; 74 75 struct bnx2x_raw_obj { 76 u8 func_id; 77 78 /* Queue params */ 79 u8 cl_id; 80 u32 cid; 81 82 /* Ramrod data buffer params */ 83 void *rdata; 84 dma_addr_t rdata_mapping; 85 86 /* Ramrod state params */ 87 int state; /* "ramrod is pending" state bit */ 88 unsigned long *pstate; /* pointer to state buffer */ 89 90 bnx2x_obj_type obj_type; 91 92 int (*wait_comp)(struct bnx2x *bp, 93 struct bnx2x_raw_obj *o); 94 95 bool (*check_pending)(struct bnx2x_raw_obj *o); 96 void (*clear_pending)(struct bnx2x_raw_obj *o); 97 void (*set_pending)(struct bnx2x_raw_obj *o); 98 }; 99 100 /************************* VLAN-MAC commands related parameters ***************/ 101 struct bnx2x_mac_ramrod_data { 102 u8 mac[ETH_ALEN]; 103 }; 104 105 struct bnx2x_vlan_ramrod_data { 106 u16 vlan; 107 }; 108 109 struct bnx2x_vlan_mac_ramrod_data { 110 u8 mac[ETH_ALEN]; 111 u16 vlan; 112 }; 113 114 union bnx2x_classification_ramrod_data { 115 struct bnx2x_mac_ramrod_data mac; 116 struct bnx2x_vlan_ramrod_data vlan; 117 struct bnx2x_vlan_mac_ramrod_data vlan_mac; 118 }; 119 120 /* VLAN_MAC commands */ 121 enum bnx2x_vlan_mac_cmd { 122 BNX2X_VLAN_MAC_ADD, 123 BNX2X_VLAN_MAC_DEL, 124 BNX2X_VLAN_MAC_MOVE, 125 }; 126 127 struct bnx2x_vlan_mac_data { 128 /* Requested command: BNX2X_VLAN_MAC_XX */ 129 enum bnx2x_vlan_mac_cmd cmd; 130 /* 131 * used to contain the data related vlan_mac_flags bits from 132 * ramrod parameters. 133 */ 134 unsigned long vlan_mac_flags; 135 136 /* Needed for MOVE command */ 137 struct bnx2x_vlan_mac_obj *target_obj; 138 139 union bnx2x_classification_ramrod_data u; 140 }; 141 142 /*************************** Exe Queue obj ************************************/ 143 union bnx2x_exe_queue_cmd_data { 144 struct bnx2x_vlan_mac_data vlan_mac; 145 146 struct { 147 /* TODO */ 148 } mcast; 149 }; 150 151 struct bnx2x_exeq_elem { 152 struct list_head link; 153 154 /* Length of this element in the exe_chunk. */ 155 int cmd_len; 156 157 union bnx2x_exe_queue_cmd_data cmd_data; 158 }; 159 160 union bnx2x_qable_obj; 161 162 union bnx2x_exeq_comp_elem { 163 union event_ring_elem *elem; 164 }; 165 166 struct bnx2x_exe_queue_obj; 167 168 typedef int (*exe_q_validate)(struct bnx2x *bp, 169 union bnx2x_qable_obj *o, 170 struct bnx2x_exeq_elem *elem); 171 172 typedef int (*exe_q_remove)(struct bnx2x *bp, 173 union bnx2x_qable_obj *o, 174 struct bnx2x_exeq_elem *elem); 175 176 /* Return positive if entry was optimized, 0 - if not, negative 177 * in case of an error. 178 */ 179 typedef int (*exe_q_optimize)(struct bnx2x *bp, 180 union bnx2x_qable_obj *o, 181 struct bnx2x_exeq_elem *elem); 182 typedef int (*exe_q_execute)(struct bnx2x *bp, 183 union bnx2x_qable_obj *o, 184 struct list_head *exe_chunk, 185 unsigned long *ramrod_flags); 186 typedef struct bnx2x_exeq_elem * 187 (*exe_q_get)(struct bnx2x_exe_queue_obj *o, 188 struct bnx2x_exeq_elem *elem); 189 190 struct bnx2x_exe_queue_obj { 191 /* 192 * Commands pending for an execution. 193 */ 194 struct list_head exe_queue; 195 196 /* 197 * Commands pending for an completion. 198 */ 199 struct list_head pending_comp; 200 201 spinlock_t lock; 202 203 /* Maximum length of commands' list for one execution */ 204 int exe_chunk_len; 205 206 union bnx2x_qable_obj *owner; 207 208 /****** Virtual functions ******/ 209 /** 210 * Called before commands execution for commands that are really 211 * going to be executed (after 'optimize'). 212 * 213 * Must run under exe_queue->lock 214 */ 215 exe_q_validate validate; 216 217 /** 218 * Called before removing pending commands, cleaning allocated 219 * resources (e.g., credits from validate) 220 */ 221 exe_q_remove remove; 222 223 /** 224 * This will try to cancel the current pending commands list 225 * considering the new command. 226 * 227 * Returns the number of optimized commands or a negative error code 228 * 229 * Must run under exe_queue->lock 230 */ 231 exe_q_optimize optimize; 232 233 /** 234 * Run the next commands chunk (owner specific). 235 */ 236 exe_q_execute execute; 237 238 /** 239 * Return the exe_queue element containing the specific command 240 * if any. Otherwise return NULL. 241 */ 242 exe_q_get get; 243 }; 244 /***************** Classification verbs: Set/Del MAC/VLAN/VLAN-MAC ************/ 245 /* 246 * Element in the VLAN_MAC registry list having all currenty configured 247 * rules. 248 */ 249 struct bnx2x_vlan_mac_registry_elem { 250 struct list_head link; 251 252 /* 253 * Used to store the cam offset used for the mac/vlan/vlan-mac. 254 * Relevant for 57710 and 57711 only. VLANs and MACs share the 255 * same CAM for these chips. 256 */ 257 int cam_offset; 258 259 /* Needed for DEL and RESTORE flows */ 260 unsigned long vlan_mac_flags; 261 262 union bnx2x_classification_ramrod_data u; 263 }; 264 265 /* Bits representing VLAN_MAC commands specific flags */ 266 enum { 267 BNX2X_UC_LIST_MAC, 268 BNX2X_ETH_MAC, 269 BNX2X_ISCSI_ETH_MAC, 270 BNX2X_NETQ_ETH_MAC, 271 BNX2X_DONT_CONSUME_CAM_CREDIT, 272 BNX2X_DONT_CONSUME_CAM_CREDIT_DEST, 273 }; 274 275 struct bnx2x_vlan_mac_ramrod_params { 276 /* Object to run the command from */ 277 struct bnx2x_vlan_mac_obj *vlan_mac_obj; 278 279 /* General command flags: COMP_WAIT, etc. */ 280 unsigned long ramrod_flags; 281 282 /* Command specific configuration request */ 283 struct bnx2x_vlan_mac_data user_req; 284 }; 285 286 struct bnx2x_vlan_mac_obj { 287 struct bnx2x_raw_obj raw; 288 289 /* Bookkeeping list: will prevent the addition of already existing 290 * entries. 291 */ 292 struct list_head head; 293 294 /* TODO: Add it's initialization in the init functions */ 295 struct bnx2x_exe_queue_obj exe_queue; 296 297 /* MACs credit pool */ 298 struct bnx2x_credit_pool_obj *macs_pool; 299 300 /* VLANs credit pool */ 301 struct bnx2x_credit_pool_obj *vlans_pool; 302 303 /* RAMROD command to be used */ 304 int ramrod_cmd; 305 306 /* copy first n elements onto preallocated buffer 307 * 308 * @param n number of elements to get 309 * @param buf buffer preallocated by caller into which elements 310 * will be copied. Note elements are 4-byte aligned 311 * so buffer size must be able to accomodate the 312 * aligned elements. 313 * 314 * @return number of copied bytes 315 */ 316 int (*get_n_elements)(struct bnx2x *bp, 317 struct bnx2x_vlan_mac_obj *o, int n, u8 *base, 318 u8 stride, u8 size); 319 320 /** 321 * Checks if ADD-ramrod with the given params may be performed. 322 * 323 * @return zero if the element may be added 324 */ 325 326 int (*check_add)(struct bnx2x *bp, 327 struct bnx2x_vlan_mac_obj *o, 328 union bnx2x_classification_ramrod_data *data); 329 330 /** 331 * Checks if DEL-ramrod with the given params may be performed. 332 * 333 * @return true if the element may be deleted 334 */ 335 struct bnx2x_vlan_mac_registry_elem * 336 (*check_del)(struct bnx2x *bp, 337 struct bnx2x_vlan_mac_obj *o, 338 union bnx2x_classification_ramrod_data *data); 339 340 /** 341 * Checks if DEL-ramrod with the given params may be performed. 342 * 343 * @return true if the element may be deleted 344 */ 345 bool (*check_move)(struct bnx2x *bp, 346 struct bnx2x_vlan_mac_obj *src_o, 347 struct bnx2x_vlan_mac_obj *dst_o, 348 union bnx2x_classification_ramrod_data *data); 349 350 /** 351 * Update the relevant credit object(s) (consume/return 352 * correspondingly). 353 */ 354 bool (*get_credit)(struct bnx2x_vlan_mac_obj *o); 355 bool (*put_credit)(struct bnx2x_vlan_mac_obj *o); 356 bool (*get_cam_offset)(struct bnx2x_vlan_mac_obj *o, int *offset); 357 bool (*put_cam_offset)(struct bnx2x_vlan_mac_obj *o, int offset); 358 359 /** 360 * Configures one rule in the ramrod data buffer. 361 */ 362 void (*set_one_rule)(struct bnx2x *bp, 363 struct bnx2x_vlan_mac_obj *o, 364 struct bnx2x_exeq_elem *elem, int rule_idx, 365 int cam_offset); 366 367 /** 368 * Delete all configured elements having the given 369 * vlan_mac_flags specification. Assumes no pending for 370 * execution commands. Will schedule all all currently 371 * configured MACs/VLANs/VLAN-MACs matching the vlan_mac_flags 372 * specification for deletion and will use the given 373 * ramrod_flags for the last DEL operation. 374 * 375 * @param bp 376 * @param o 377 * @param ramrod_flags RAMROD_XX flags 378 * 379 * @return 0 if the last operation has completed successfully 380 * and there are no more elements left, positive value 381 * if there are pending for completion commands, 382 * negative value in case of failure. 383 */ 384 int (*delete_all)(struct bnx2x *bp, 385 struct bnx2x_vlan_mac_obj *o, 386 unsigned long *vlan_mac_flags, 387 unsigned long *ramrod_flags); 388 389 /** 390 * Reconfigures the next MAC/VLAN/VLAN-MAC element from the previously 391 * configured elements list. 392 * 393 * @param bp 394 * @param p Command parameters (RAMROD_COMP_WAIT bit in 395 * ramrod_flags is only taken into an account) 396 * @param ppos a pointer to the cooky that should be given back in the 397 * next call to make function handle the next element. If 398 * *ppos is set to NULL it will restart the iterator. 399 * If returned *ppos == NULL this means that the last 400 * element has been handled. 401 * 402 * @return int 403 */ 404 int (*restore)(struct bnx2x *bp, 405 struct bnx2x_vlan_mac_ramrod_params *p, 406 struct bnx2x_vlan_mac_registry_elem **ppos); 407 408 /** 409 * Should be called on a completion arival. 410 * 411 * @param bp 412 * @param o 413 * @param cqe Completion element we are handling 414 * @param ramrod_flags if RAMROD_CONT is set the next bulk of 415 * pending commands will be executed. 416 * RAMROD_DRV_CLR_ONLY and RAMROD_RESTORE 417 * may also be set if needed. 418 * 419 * @return 0 if there are neither pending nor waiting for 420 * completion commands. Positive value if there are 421 * pending for execution or for completion commands. 422 * Negative value in case of an error (including an 423 * error in the cqe). 424 */ 425 int (*complete)(struct bnx2x *bp, struct bnx2x_vlan_mac_obj *o, 426 union event_ring_elem *cqe, 427 unsigned long *ramrod_flags); 428 429 /** 430 * Wait for completion of all commands. Don't schedule new ones, 431 * just wait. It assumes that the completion code will schedule 432 * for new commands. 433 */ 434 int (*wait)(struct bnx2x *bp, struct bnx2x_vlan_mac_obj *o); 435 }; 436 437 enum { 438 BNX2X_LLH_CAM_ISCSI_ETH_LINE = 0, 439 BNX2X_LLH_CAM_ETH_LINE, 440 BNX2X_LLH_CAM_MAX_PF_LINE = NIG_REG_LLH1_FUNC_MEM_SIZE / 2 441 }; 442 443 void bnx2x_set_mac_in_nig(struct bnx2x *bp, 444 bool add, unsigned char *dev_addr, int index); 445 446 /** RX_MODE verbs:DROP_ALL/ACCEPT_ALL/ACCEPT_ALL_MULTI/ACCEPT_ALL_VLAN/NORMAL */ 447 448 /* RX_MODE ramrod spesial flags: set in rx_mode_flags field in 449 * a bnx2x_rx_mode_ramrod_params. 450 */ 451 enum { 452 BNX2X_RX_MODE_FCOE_ETH, 453 BNX2X_RX_MODE_ISCSI_ETH, 454 }; 455 456 enum { 457 BNX2X_ACCEPT_UNICAST, 458 BNX2X_ACCEPT_MULTICAST, 459 BNX2X_ACCEPT_ALL_UNICAST, 460 BNX2X_ACCEPT_ALL_MULTICAST, 461 BNX2X_ACCEPT_BROADCAST, 462 BNX2X_ACCEPT_UNMATCHED, 463 BNX2X_ACCEPT_ANY_VLAN 464 }; 465 466 struct bnx2x_rx_mode_ramrod_params { 467 struct bnx2x_rx_mode_obj *rx_mode_obj; 468 unsigned long *pstate; 469 int state; 470 u8 cl_id; 471 u32 cid; 472 u8 func_id; 473 unsigned long ramrod_flags; 474 unsigned long rx_mode_flags; 475 476 /* 477 * rdata is either a pointer to eth_filter_rules_ramrod_data(e2) or to 478 * a tstorm_eth_mac_filter_config (e1x). 479 */ 480 void *rdata; 481 dma_addr_t rdata_mapping; 482 483 /* Rx mode settings */ 484 unsigned long rx_accept_flags; 485 486 /* internal switching settings */ 487 unsigned long tx_accept_flags; 488 }; 489 490 struct bnx2x_rx_mode_obj { 491 int (*config_rx_mode)(struct bnx2x *bp, 492 struct bnx2x_rx_mode_ramrod_params *p); 493 494 int (*wait_comp)(struct bnx2x *bp, 495 struct bnx2x_rx_mode_ramrod_params *p); 496 }; 497 498 /********************** Set multicast group ***********************************/ 499 500 struct bnx2x_mcast_list_elem { 501 struct list_head link; 502 u8 *mac; 503 }; 504 505 union bnx2x_mcast_config_data { 506 u8 *mac; 507 u8 bin; /* used in a RESTORE flow */ 508 }; 509 510 struct bnx2x_mcast_ramrod_params { 511 struct bnx2x_mcast_obj *mcast_obj; 512 513 /* Relevant options are RAMROD_COMP_WAIT and RAMROD_DRV_CLR_ONLY */ 514 unsigned long ramrod_flags; 515 516 struct list_head mcast_list; /* list of struct bnx2x_mcast_list_elem */ 517 /** TODO: 518 * - rename it to macs_num. 519 * - Add a new command type for handling pending commands 520 * (remove "zero semantics"). 521 * 522 * Length of mcast_list. If zero and ADD_CONT command - post 523 * pending commands. 524 */ 525 int mcast_list_len; 526 }; 527 528 enum bnx2x_mcast_cmd { 529 BNX2X_MCAST_CMD_ADD, 530 BNX2X_MCAST_CMD_CONT, 531 BNX2X_MCAST_CMD_DEL, 532 BNX2X_MCAST_CMD_RESTORE, 533 }; 534 535 struct bnx2x_mcast_obj { 536 struct bnx2x_raw_obj raw; 537 538 union { 539 struct { 540 #define BNX2X_MCAST_BINS_NUM 256 541 #define BNX2X_MCAST_VEC_SZ (BNX2X_MCAST_BINS_NUM / 64) 542 u64 vec[BNX2X_MCAST_VEC_SZ]; 543 544 /** Number of BINs to clear. Should be updated 545 * immediately when a command arrives in order to 546 * properly create DEL commands. 547 */ 548 int num_bins_set; 549 } aprox_match; 550 551 struct { 552 struct list_head macs; 553 int num_macs_set; 554 } exact_match; 555 } registry; 556 557 /* Pending commands */ 558 struct list_head pending_cmds_head; 559 560 /* A state that is set in raw.pstate, when there are pending commands */ 561 int sched_state; 562 563 /* Maximal number of mcast MACs configured in one command */ 564 int max_cmd_len; 565 566 /* Total number of currently pending MACs to configure: both 567 * in the pending commands list and in the current command. 568 */ 569 int total_pending_num; 570 571 u8 engine_id; 572 573 /** 574 * @param cmd command to execute (BNX2X_MCAST_CMD_X, see above) 575 */ 576 int (*config_mcast)(struct bnx2x *bp, 577 struct bnx2x_mcast_ramrod_params *p, 578 enum bnx2x_mcast_cmd cmd); 579 580 /** 581 * Fills the ramrod data during the RESTORE flow. 582 * 583 * @param bp 584 * @param o 585 * @param start_idx Registry index to start from 586 * @param rdata_idx Index in the ramrod data to start from 587 * 588 * @return -1 if we handled the whole registry or index of the last 589 * handled registry element. 590 */ 591 int (*hdl_restore)(struct bnx2x *bp, struct bnx2x_mcast_obj *o, 592 int start_bin, int *rdata_idx); 593 594 int (*enqueue_cmd)(struct bnx2x *bp, struct bnx2x_mcast_obj *o, 595 struct bnx2x_mcast_ramrod_params *p, 596 enum bnx2x_mcast_cmd cmd); 597 598 void (*set_one_rule)(struct bnx2x *bp, 599 struct bnx2x_mcast_obj *o, int idx, 600 union bnx2x_mcast_config_data *cfg_data, 601 enum bnx2x_mcast_cmd cmd); 602 603 /** Checks if there are more mcast MACs to be set or a previous 604 * command is still pending. 605 */ 606 bool (*check_pending)(struct bnx2x_mcast_obj *o); 607 608 /** 609 * Set/Clear/Check SCHEDULED state of the object 610 */ 611 void (*set_sched)(struct bnx2x_mcast_obj *o); 612 void (*clear_sched)(struct bnx2x_mcast_obj *o); 613 bool (*check_sched)(struct bnx2x_mcast_obj *o); 614 615 /* Wait until all pending commands complete */ 616 int (*wait_comp)(struct bnx2x *bp, struct bnx2x_mcast_obj *o); 617 618 /** 619 * Handle the internal object counters needed for proper 620 * commands handling. Checks that the provided parameters are 621 * feasible. 622 */ 623 int (*validate)(struct bnx2x *bp, 624 struct bnx2x_mcast_ramrod_params *p, 625 enum bnx2x_mcast_cmd cmd); 626 627 /** 628 * Restore the values of internal counters in case of a failure. 629 */ 630 void (*revert)(struct bnx2x *bp, 631 struct bnx2x_mcast_ramrod_params *p, 632 int old_num_bins); 633 634 int (*get_registry_size)(struct bnx2x_mcast_obj *o); 635 void (*set_registry_size)(struct bnx2x_mcast_obj *o, int n); 636 }; 637 638 /*************************** Credit handling **********************************/ 639 struct bnx2x_credit_pool_obj { 640 641 /* Current amount of credit in the pool */ 642 atomic_t credit; 643 644 /* Maximum allowed credit. put() will check against it. */ 645 int pool_sz; 646 647 /* 648 * Allocate a pool table statically. 649 * 650 * Currently the mamimum allowed size is MAX_MAC_CREDIT_E2(272) 651 * 652 * The set bit in the table will mean that the entry is available. 653 */ 654 #define BNX2X_POOL_VEC_SIZE (MAX_MAC_CREDIT_E2 / 64) 655 u64 pool_mirror[BNX2X_POOL_VEC_SIZE]; 656 657 /* Base pool offset (initialized differently */ 658 int base_pool_offset; 659 660 /** 661 * Get the next free pool entry. 662 * 663 * @return true if there was a free entry in the pool 664 */ 665 bool (*get_entry)(struct bnx2x_credit_pool_obj *o, int *entry); 666 667 /** 668 * Return the entry back to the pool. 669 * 670 * @return true if entry is legal and has been successfully 671 * returned to the pool. 672 */ 673 bool (*put_entry)(struct bnx2x_credit_pool_obj *o, int entry); 674 675 /** 676 * Get the requested amount of credit from the pool. 677 * 678 * @param cnt Amount of requested credit 679 * @return true if the operation is successful 680 */ 681 bool (*get)(struct bnx2x_credit_pool_obj *o, int cnt); 682 683 /** 684 * Returns the credit to the pool. 685 * 686 * @param cnt Amount of credit to return 687 * @return true if the operation is successful 688 */ 689 bool (*put)(struct bnx2x_credit_pool_obj *o, int cnt); 690 691 /** 692 * Reads the current amount of credit. 693 */ 694 int (*check)(struct bnx2x_credit_pool_obj *o); 695 }; 696 697 /*************************** RSS configuration ********************************/ 698 enum { 699 /* RSS_MODE bits are mutually exclusive */ 700 BNX2X_RSS_MODE_DISABLED, 701 BNX2X_RSS_MODE_REGULAR, 702 703 BNX2X_RSS_SET_SRCH, /* Setup searcher, E1x specific flag */ 704 705 BNX2X_RSS_IPV4, 706 BNX2X_RSS_IPV4_TCP, 707 BNX2X_RSS_IPV4_UDP, 708 BNX2X_RSS_IPV6, 709 BNX2X_RSS_IPV6_TCP, 710 BNX2X_RSS_IPV6_UDP, 711 }; 712 713 struct bnx2x_config_rss_params { 714 struct bnx2x_rss_config_obj *rss_obj; 715 716 /* may have RAMROD_COMP_WAIT set only */ 717 unsigned long ramrod_flags; 718 719 /* BNX2X_RSS_X bits */ 720 unsigned long rss_flags; 721 722 /* Number hash bits to take into an account */ 723 u8 rss_result_mask; 724 725 /* Indirection table */ 726 u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE]; 727 728 /* RSS hash values */ 729 u32 rss_key[10]; 730 731 /* valid only iff BNX2X_RSS_UPDATE_TOE is set */ 732 u16 toe_rss_bitmap; 733 }; 734 735 struct bnx2x_rss_config_obj { 736 struct bnx2x_raw_obj raw; 737 738 /* RSS engine to use */ 739 u8 engine_id; 740 741 /* Last configured indirection table */ 742 u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE]; 743 744 /* flags for enabling 4-tupple hash on UDP */ 745 u8 udp_rss_v4; 746 u8 udp_rss_v6; 747 748 int (*config_rss)(struct bnx2x *bp, 749 struct bnx2x_config_rss_params *p); 750 }; 751 752 /*********************** Queue state update ***********************************/ 753 754 /* UPDATE command options */ 755 enum { 756 BNX2X_Q_UPDATE_IN_VLAN_REM, 757 BNX2X_Q_UPDATE_IN_VLAN_REM_CHNG, 758 BNX2X_Q_UPDATE_OUT_VLAN_REM, 759 BNX2X_Q_UPDATE_OUT_VLAN_REM_CHNG, 760 BNX2X_Q_UPDATE_ANTI_SPOOF, 761 BNX2X_Q_UPDATE_ANTI_SPOOF_CHNG, 762 BNX2X_Q_UPDATE_ACTIVATE, 763 BNX2X_Q_UPDATE_ACTIVATE_CHNG, 764 BNX2X_Q_UPDATE_DEF_VLAN_EN, 765 BNX2X_Q_UPDATE_DEF_VLAN_EN_CHNG, 766 BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG, 767 BNX2X_Q_UPDATE_SILENT_VLAN_REM 768 }; 769 770 /* Allowed Queue states */ 771 enum bnx2x_q_state { 772 BNX2X_Q_STATE_RESET, 773 BNX2X_Q_STATE_INITIALIZED, 774 BNX2X_Q_STATE_ACTIVE, 775 BNX2X_Q_STATE_MULTI_COS, 776 BNX2X_Q_STATE_MCOS_TERMINATED, 777 BNX2X_Q_STATE_INACTIVE, 778 BNX2X_Q_STATE_STOPPED, 779 BNX2X_Q_STATE_TERMINATED, 780 BNX2X_Q_STATE_FLRED, 781 BNX2X_Q_STATE_MAX, 782 }; 783 784 /* Allowed Queue states */ 785 enum bnx2x_q_logical_state { 786 BNX2X_Q_LOGICAL_STATE_ACTIVE, 787 BNX2X_Q_LOGICAL_STATE_STOPPED, 788 }; 789 790 /* Allowed commands */ 791 enum bnx2x_queue_cmd { 792 BNX2X_Q_CMD_INIT, 793 BNX2X_Q_CMD_SETUP, 794 BNX2X_Q_CMD_SETUP_TX_ONLY, 795 BNX2X_Q_CMD_DEACTIVATE, 796 BNX2X_Q_CMD_ACTIVATE, 797 BNX2X_Q_CMD_UPDATE, 798 BNX2X_Q_CMD_UPDATE_TPA, 799 BNX2X_Q_CMD_HALT, 800 BNX2X_Q_CMD_CFC_DEL, 801 BNX2X_Q_CMD_TERMINATE, 802 BNX2X_Q_CMD_EMPTY, 803 BNX2X_Q_CMD_MAX, 804 }; 805 806 /* queue SETUP + INIT flags */ 807 enum { 808 BNX2X_Q_FLG_TPA, 809 BNX2X_Q_FLG_TPA_IPV6, 810 BNX2X_Q_FLG_TPA_GRO, 811 BNX2X_Q_FLG_STATS, 812 BNX2X_Q_FLG_ZERO_STATS, 813 BNX2X_Q_FLG_ACTIVE, 814 BNX2X_Q_FLG_OV, 815 BNX2X_Q_FLG_VLAN, 816 BNX2X_Q_FLG_COS, 817 BNX2X_Q_FLG_HC, 818 BNX2X_Q_FLG_HC_EN, 819 BNX2X_Q_FLG_DHC, 820 BNX2X_Q_FLG_FCOE, 821 BNX2X_Q_FLG_LEADING_RSS, 822 BNX2X_Q_FLG_MCAST, 823 BNX2X_Q_FLG_DEF_VLAN, 824 BNX2X_Q_FLG_TX_SWITCH, 825 BNX2X_Q_FLG_TX_SEC, 826 BNX2X_Q_FLG_ANTI_SPOOF, 827 BNX2X_Q_FLG_SILENT_VLAN_REM, 828 BNX2X_Q_FLG_FORCE_DEFAULT_PRI 829 }; 830 831 /* Queue type options: queue type may be a compination of below. */ 832 enum bnx2x_q_type { 833 /** TODO: Consider moving both these flags into the init() 834 * ramrod params. 835 */ 836 BNX2X_Q_TYPE_HAS_RX, 837 BNX2X_Q_TYPE_HAS_TX, 838 }; 839 840 #define BNX2X_PRIMARY_CID_INDEX 0 841 #define BNX2X_MULTI_TX_COS_E1X 3 /* QM only */ 842 #define BNX2X_MULTI_TX_COS_E2_E3A0 2 843 #define BNX2X_MULTI_TX_COS_E3B0 3 844 #define BNX2X_MULTI_TX_COS 3 /* Maximum possible */ 845 846 #define MAC_PAD (ALIGN(ETH_ALEN, sizeof(u32)) - ETH_ALEN) 847 848 struct bnx2x_queue_init_params { 849 struct { 850 unsigned long flags; 851 u16 hc_rate; 852 u8 fw_sb_id; 853 u8 sb_cq_index; 854 } tx; 855 856 struct { 857 unsigned long flags; 858 u16 hc_rate; 859 u8 fw_sb_id; 860 u8 sb_cq_index; 861 } rx; 862 863 /* CID context in the host memory */ 864 struct eth_context *cxts[BNX2X_MULTI_TX_COS]; 865 866 /* maximum number of cos supported by hardware */ 867 u8 max_cos; 868 }; 869 870 struct bnx2x_queue_terminate_params { 871 /* index within the tx_only cids of this queue object */ 872 u8 cid_index; 873 }; 874 875 struct bnx2x_queue_cfc_del_params { 876 /* index within the tx_only cids of this queue object */ 877 u8 cid_index; 878 }; 879 880 struct bnx2x_queue_update_params { 881 unsigned long update_flags; /* BNX2X_Q_UPDATE_XX bits */ 882 u16 def_vlan; 883 u16 silent_removal_value; 884 u16 silent_removal_mask; 885 /* index within the tx_only cids of this queue object */ 886 u8 cid_index; 887 }; 888 889 struct rxq_pause_params { 890 u16 bd_th_lo; 891 u16 bd_th_hi; 892 u16 rcq_th_lo; 893 u16 rcq_th_hi; 894 u16 sge_th_lo; /* valid iff BNX2X_Q_FLG_TPA */ 895 u16 sge_th_hi; /* valid iff BNX2X_Q_FLG_TPA */ 896 u16 pri_map; 897 }; 898 899 /* general */ 900 struct bnx2x_general_setup_params { 901 /* valid iff BNX2X_Q_FLG_STATS */ 902 u8 stat_id; 903 904 u8 spcl_id; 905 u16 mtu; 906 u8 cos; 907 }; 908 909 struct bnx2x_rxq_setup_params { 910 /* dma */ 911 dma_addr_t dscr_map; 912 dma_addr_t sge_map; 913 dma_addr_t rcq_map; 914 dma_addr_t rcq_np_map; 915 916 u16 drop_flags; 917 u16 buf_sz; 918 u8 fw_sb_id; 919 u8 cl_qzone_id; 920 921 /* valid iff BNX2X_Q_FLG_TPA */ 922 u16 tpa_agg_sz; 923 u16 sge_buf_sz; 924 u8 max_sges_pkt; 925 u8 max_tpa_queues; 926 u8 rss_engine_id; 927 928 /* valid iff BNX2X_Q_FLG_MCAST */ 929 u8 mcast_engine_id; 930 931 u8 cache_line_log; 932 933 u8 sb_cq_index; 934 935 /* valid iff BXN2X_Q_FLG_SILENT_VLAN_REM */ 936 u16 silent_removal_value; 937 u16 silent_removal_mask; 938 }; 939 940 struct bnx2x_txq_setup_params { 941 /* dma */ 942 dma_addr_t dscr_map; 943 944 u8 fw_sb_id; 945 u8 sb_cq_index; 946 u8 cos; /* valid iff BNX2X_Q_FLG_COS */ 947 u16 traffic_type; 948 /* equals to the leading rss client id, used for TX classification*/ 949 u8 tss_leading_cl_id; 950 951 /* valid iff BNX2X_Q_FLG_DEF_VLAN */ 952 u16 default_vlan; 953 }; 954 955 struct bnx2x_queue_setup_params { 956 struct bnx2x_general_setup_params gen_params; 957 struct bnx2x_txq_setup_params txq_params; 958 struct bnx2x_rxq_setup_params rxq_params; 959 struct rxq_pause_params pause_params; 960 unsigned long flags; 961 }; 962 963 struct bnx2x_queue_setup_tx_only_params { 964 struct bnx2x_general_setup_params gen_params; 965 struct bnx2x_txq_setup_params txq_params; 966 unsigned long flags; 967 /* index within the tx_only cids of this queue object */ 968 u8 cid_index; 969 }; 970 971 struct bnx2x_queue_state_params { 972 struct bnx2x_queue_sp_obj *q_obj; 973 974 /* Current command */ 975 enum bnx2x_queue_cmd cmd; 976 977 /* may have RAMROD_COMP_WAIT set only */ 978 unsigned long ramrod_flags; 979 980 /* Params according to the current command */ 981 union { 982 struct bnx2x_queue_update_params update; 983 struct bnx2x_queue_setup_params setup; 984 struct bnx2x_queue_init_params init; 985 struct bnx2x_queue_setup_tx_only_params tx_only; 986 struct bnx2x_queue_terminate_params terminate; 987 struct bnx2x_queue_cfc_del_params cfc_del; 988 } params; 989 }; 990 991 struct bnx2x_viflist_params { 992 u8 echo_res; 993 u8 func_bit_map_res; 994 }; 995 996 struct bnx2x_queue_sp_obj { 997 u32 cids[BNX2X_MULTI_TX_COS]; 998 u8 cl_id; 999 u8 func_id; 1000 1001 /* 1002 * number of traffic classes supported by queue. 1003 * The primary connection of the queue suppotrs the first traffic 1004 * class. Any further traffic class is suppoted by a tx-only 1005 * connection. 1006 * 1007 * Therefore max_cos is also a number of valid entries in the cids 1008 * array. 1009 */ 1010 u8 max_cos; 1011 u8 num_tx_only, next_tx_only; 1012 1013 enum bnx2x_q_state state, next_state; 1014 1015 /* bits from enum bnx2x_q_type */ 1016 unsigned long type; 1017 1018 /* BNX2X_Q_CMD_XX bits. This object implements "one 1019 * pending" paradigm but for debug and tracing purposes it's 1020 * more convinient to have different bits for different 1021 * commands. 1022 */ 1023 unsigned long pending; 1024 1025 /* Buffer to use as a ramrod data and its mapping */ 1026 void *rdata; 1027 dma_addr_t rdata_mapping; 1028 1029 /** 1030 * Performs one state change according to the given parameters. 1031 * 1032 * @return 0 in case of success and negative value otherwise. 1033 */ 1034 int (*send_cmd)(struct bnx2x *bp, 1035 struct bnx2x_queue_state_params *params); 1036 1037 /** 1038 * Sets the pending bit according to the requested transition. 1039 */ 1040 int (*set_pending)(struct bnx2x_queue_sp_obj *o, 1041 struct bnx2x_queue_state_params *params); 1042 1043 /** 1044 * Checks that the requested state transition is legal. 1045 */ 1046 int (*check_transition)(struct bnx2x *bp, 1047 struct bnx2x_queue_sp_obj *o, 1048 struct bnx2x_queue_state_params *params); 1049 1050 /** 1051 * Completes the pending command. 1052 */ 1053 int (*complete_cmd)(struct bnx2x *bp, 1054 struct bnx2x_queue_sp_obj *o, 1055 enum bnx2x_queue_cmd); 1056 1057 int (*wait_comp)(struct bnx2x *bp, 1058 struct bnx2x_queue_sp_obj *o, 1059 enum bnx2x_queue_cmd cmd); 1060 }; 1061 1062 /********************** Function state update *********************************/ 1063 /* Allowed Function states */ 1064 enum bnx2x_func_state { 1065 BNX2X_F_STATE_RESET, 1066 BNX2X_F_STATE_INITIALIZED, 1067 BNX2X_F_STATE_STARTED, 1068 BNX2X_F_STATE_TX_STOPPED, 1069 BNX2X_F_STATE_MAX, 1070 }; 1071 1072 /* Allowed Function commands */ 1073 enum bnx2x_func_cmd { 1074 BNX2X_F_CMD_HW_INIT, 1075 BNX2X_F_CMD_START, 1076 BNX2X_F_CMD_STOP, 1077 BNX2X_F_CMD_HW_RESET, 1078 BNX2X_F_CMD_AFEX_UPDATE, 1079 BNX2X_F_CMD_AFEX_VIFLISTS, 1080 BNX2X_F_CMD_TX_STOP, 1081 BNX2X_F_CMD_TX_START, 1082 BNX2X_F_CMD_SWITCH_UPDATE, 1083 BNX2X_F_CMD_MAX, 1084 }; 1085 1086 struct bnx2x_func_hw_init_params { 1087 /* A load phase returned by MCP. 1088 * 1089 * May be: 1090 * FW_MSG_CODE_DRV_LOAD_COMMON_CHIP 1091 * FW_MSG_CODE_DRV_LOAD_COMMON 1092 * FW_MSG_CODE_DRV_LOAD_PORT 1093 * FW_MSG_CODE_DRV_LOAD_FUNCTION 1094 */ 1095 u32 load_phase; 1096 }; 1097 1098 struct bnx2x_func_hw_reset_params { 1099 /* A load phase returned by MCP. 1100 * 1101 * May be: 1102 * FW_MSG_CODE_DRV_LOAD_COMMON_CHIP 1103 * FW_MSG_CODE_DRV_LOAD_COMMON 1104 * FW_MSG_CODE_DRV_LOAD_PORT 1105 * FW_MSG_CODE_DRV_LOAD_FUNCTION 1106 */ 1107 u32 reset_phase; 1108 }; 1109 1110 struct bnx2x_func_start_params { 1111 /* Multi Function mode: 1112 * - Single Function 1113 * - Switch Dependent 1114 * - Switch Independent 1115 */ 1116 u16 mf_mode; 1117 1118 /* Switch Dependent mode outer VLAN tag */ 1119 u16 sd_vlan_tag; 1120 1121 /* Function cos mode */ 1122 u8 network_cos_mode; 1123 }; 1124 1125 struct bnx2x_func_switch_update_params { 1126 u8 suspend; 1127 }; 1128 1129 struct bnx2x_func_afex_update_params { 1130 u16 vif_id; 1131 u16 afex_default_vlan; 1132 u8 allowed_priorities; 1133 }; 1134 1135 struct bnx2x_func_afex_viflists_params { 1136 u16 vif_list_index; 1137 u8 func_bit_map; 1138 u8 afex_vif_list_command; 1139 u8 func_to_clear; 1140 }; 1141 struct bnx2x_func_tx_start_params { 1142 struct priority_cos traffic_type_to_priority_cos[MAX_TRAFFIC_TYPES]; 1143 u8 dcb_enabled; 1144 u8 dcb_version; 1145 u8 dont_add_pri_0_en; 1146 }; 1147 1148 struct bnx2x_func_state_params { 1149 struct bnx2x_func_sp_obj *f_obj; 1150 1151 /* Current command */ 1152 enum bnx2x_func_cmd cmd; 1153 1154 /* may have RAMROD_COMP_WAIT set only */ 1155 unsigned long ramrod_flags; 1156 1157 /* Params according to the current command */ 1158 union { 1159 struct bnx2x_func_hw_init_params hw_init; 1160 struct bnx2x_func_hw_reset_params hw_reset; 1161 struct bnx2x_func_start_params start; 1162 struct bnx2x_func_switch_update_params switch_update; 1163 struct bnx2x_func_afex_update_params afex_update; 1164 struct bnx2x_func_afex_viflists_params afex_viflists; 1165 struct bnx2x_func_tx_start_params tx_start; 1166 } params; 1167 }; 1168 1169 struct bnx2x_func_sp_drv_ops { 1170 /* Init tool + runtime initialization: 1171 * - Common Chip 1172 * - Common (per Path) 1173 * - Port 1174 * - Function phases 1175 */ 1176 int (*init_hw_cmn_chip)(struct bnx2x *bp); 1177 int (*init_hw_cmn)(struct bnx2x *bp); 1178 int (*init_hw_port)(struct bnx2x *bp); 1179 int (*init_hw_func)(struct bnx2x *bp); 1180 1181 /* Reset Function HW: Common, Port, Function phases. */ 1182 void (*reset_hw_cmn)(struct bnx2x *bp); 1183 void (*reset_hw_port)(struct bnx2x *bp); 1184 void (*reset_hw_func)(struct bnx2x *bp); 1185 1186 /* Init/Free GUNZIP resources */ 1187 int (*gunzip_init)(struct bnx2x *bp); 1188 void (*gunzip_end)(struct bnx2x *bp); 1189 1190 /* Prepare/Release FW resources */ 1191 int (*init_fw)(struct bnx2x *bp); 1192 void (*release_fw)(struct bnx2x *bp); 1193 }; 1194 1195 struct bnx2x_func_sp_obj { 1196 enum bnx2x_func_state state, next_state; 1197 1198 /* BNX2X_FUNC_CMD_XX bits. This object implements "one 1199 * pending" paradigm but for debug and tracing purposes it's 1200 * more convinient to have different bits for different 1201 * commands. 1202 */ 1203 unsigned long pending; 1204 1205 /* Buffer to use as a ramrod data and its mapping */ 1206 void *rdata; 1207 dma_addr_t rdata_mapping; 1208 1209 /* Buffer to use as a afex ramrod data and its mapping. 1210 * This can't be same rdata as above because afex ramrod requests 1211 * can arrive to the object in parallel to other ramrod requests. 1212 */ 1213 void *afex_rdata; 1214 dma_addr_t afex_rdata_mapping; 1215 1216 /* this mutex validates that when pending flag is taken, the next 1217 * ramrod to be sent will be the one set the pending bit 1218 */ 1219 struct mutex one_pending_mutex; 1220 1221 /* Driver interface */ 1222 struct bnx2x_func_sp_drv_ops *drv; 1223 1224 /** 1225 * Performs one state change according to the given parameters. 1226 * 1227 * @return 0 in case of success and negative value otherwise. 1228 */ 1229 int (*send_cmd)(struct bnx2x *bp, 1230 struct bnx2x_func_state_params *params); 1231 1232 /** 1233 * Checks that the requested state transition is legal. 1234 */ 1235 int (*check_transition)(struct bnx2x *bp, 1236 struct bnx2x_func_sp_obj *o, 1237 struct bnx2x_func_state_params *params); 1238 1239 /** 1240 * Completes the pending command. 1241 */ 1242 int (*complete_cmd)(struct bnx2x *bp, 1243 struct bnx2x_func_sp_obj *o, 1244 enum bnx2x_func_cmd cmd); 1245 1246 int (*wait_comp)(struct bnx2x *bp, struct bnx2x_func_sp_obj *o, 1247 enum bnx2x_func_cmd cmd); 1248 }; 1249 1250 /********************** Interfaces ********************************************/ 1251 /* Queueable objects set */ 1252 union bnx2x_qable_obj { 1253 struct bnx2x_vlan_mac_obj vlan_mac; 1254 }; 1255 /************** Function state update *********/ 1256 void bnx2x_init_func_obj(struct bnx2x *bp, 1257 struct bnx2x_func_sp_obj *obj, 1258 void *rdata, dma_addr_t rdata_mapping, 1259 void *afex_rdata, dma_addr_t afex_rdata_mapping, 1260 struct bnx2x_func_sp_drv_ops *drv_iface); 1261 1262 int bnx2x_func_state_change(struct bnx2x *bp, 1263 struct bnx2x_func_state_params *params); 1264 1265 enum bnx2x_func_state bnx2x_func_get_state(struct bnx2x *bp, 1266 struct bnx2x_func_sp_obj *o); 1267 /******************* Queue State **************/ 1268 void bnx2x_init_queue_obj(struct bnx2x *bp, 1269 struct bnx2x_queue_sp_obj *obj, u8 cl_id, u32 *cids, 1270 u8 cid_cnt, u8 func_id, void *rdata, 1271 dma_addr_t rdata_mapping, unsigned long type); 1272 1273 int bnx2x_queue_state_change(struct bnx2x *bp, 1274 struct bnx2x_queue_state_params *params); 1275 1276 int bnx2x_get_q_logical_state(struct bnx2x *bp, 1277 struct bnx2x_queue_sp_obj *obj); 1278 1279 /********************* VLAN-MAC ****************/ 1280 void bnx2x_init_mac_obj(struct bnx2x *bp, 1281 struct bnx2x_vlan_mac_obj *mac_obj, 1282 u8 cl_id, u32 cid, u8 func_id, void *rdata, 1283 dma_addr_t rdata_mapping, int state, 1284 unsigned long *pstate, bnx2x_obj_type type, 1285 struct bnx2x_credit_pool_obj *macs_pool); 1286 1287 void bnx2x_init_vlan_obj(struct bnx2x *bp, 1288 struct bnx2x_vlan_mac_obj *vlan_obj, 1289 u8 cl_id, u32 cid, u8 func_id, void *rdata, 1290 dma_addr_t rdata_mapping, int state, 1291 unsigned long *pstate, bnx2x_obj_type type, 1292 struct bnx2x_credit_pool_obj *vlans_pool); 1293 1294 void bnx2x_init_vlan_mac_obj(struct bnx2x *bp, 1295 struct bnx2x_vlan_mac_obj *vlan_mac_obj, 1296 u8 cl_id, u32 cid, u8 func_id, void *rdata, 1297 dma_addr_t rdata_mapping, int state, 1298 unsigned long *pstate, bnx2x_obj_type type, 1299 struct bnx2x_credit_pool_obj *macs_pool, 1300 struct bnx2x_credit_pool_obj *vlans_pool); 1301 1302 int bnx2x_config_vlan_mac(struct bnx2x *bp, 1303 struct bnx2x_vlan_mac_ramrod_params *p); 1304 1305 int bnx2x_vlan_mac_move(struct bnx2x *bp, 1306 struct bnx2x_vlan_mac_ramrod_params *p, 1307 struct bnx2x_vlan_mac_obj *dest_o); 1308 1309 /********************* RX MODE ****************/ 1310 1311 void bnx2x_init_rx_mode_obj(struct bnx2x *bp, 1312 struct bnx2x_rx_mode_obj *o); 1313 1314 /** 1315 * bnx2x_config_rx_mode - Send and RX_MODE ramrod according to the provided parameters. 1316 * 1317 * @p: Command parameters 1318 * 1319 * Return: 0 - if operation was successfull and there is no pending completions, 1320 * positive number - if there are pending completions, 1321 * negative - if there were errors 1322 */ 1323 int bnx2x_config_rx_mode(struct bnx2x *bp, 1324 struct bnx2x_rx_mode_ramrod_params *p); 1325 1326 /****************** MULTICASTS ****************/ 1327 1328 void bnx2x_init_mcast_obj(struct bnx2x *bp, 1329 struct bnx2x_mcast_obj *mcast_obj, 1330 u8 mcast_cl_id, u32 mcast_cid, u8 func_id, 1331 u8 engine_id, void *rdata, dma_addr_t rdata_mapping, 1332 int state, unsigned long *pstate, 1333 bnx2x_obj_type type); 1334 1335 /** 1336 * bnx2x_config_mcast - Configure multicast MACs list. 1337 * 1338 * @cmd: command to execute: BNX2X_MCAST_CMD_X 1339 * 1340 * May configure a new list 1341 * provided in p->mcast_list (BNX2X_MCAST_CMD_ADD), clean up 1342 * (BNX2X_MCAST_CMD_DEL) or restore (BNX2X_MCAST_CMD_RESTORE) a current 1343 * configuration, continue to execute the pending commands 1344 * (BNX2X_MCAST_CMD_CONT). 1345 * 1346 * If previous command is still pending or if number of MACs to 1347 * configure is more that maximum number of MACs in one command, 1348 * the current command will be enqueued to the tail of the 1349 * pending commands list. 1350 * 1351 * Return: 0 is operation was successfull and there are no pending completions, 1352 * negative if there were errors, positive if there are pending 1353 * completions. 1354 */ 1355 int bnx2x_config_mcast(struct bnx2x *bp, 1356 struct bnx2x_mcast_ramrod_params *p, 1357 enum bnx2x_mcast_cmd cmd); 1358 1359 /****************** CREDIT POOL ****************/ 1360 void bnx2x_init_mac_credit_pool(struct bnx2x *bp, 1361 struct bnx2x_credit_pool_obj *p, u8 func_id, 1362 u8 func_num); 1363 void bnx2x_init_vlan_credit_pool(struct bnx2x *bp, 1364 struct bnx2x_credit_pool_obj *p, u8 func_id, 1365 u8 func_num); 1366 1367 1368 /****************** RSS CONFIGURATION ****************/ 1369 void bnx2x_init_rss_config_obj(struct bnx2x *bp, 1370 struct bnx2x_rss_config_obj *rss_obj, 1371 u8 cl_id, u32 cid, u8 func_id, u8 engine_id, 1372 void *rdata, dma_addr_t rdata_mapping, 1373 int state, unsigned long *pstate, 1374 bnx2x_obj_type type); 1375 1376 /** 1377 * bnx2x_config_rss - Updates RSS configuration according to provided parameters 1378 * 1379 * Return: 0 in case of success 1380 */ 1381 int bnx2x_config_rss(struct bnx2x *bp, 1382 struct bnx2x_config_rss_params *p); 1383 1384 /** 1385 * bnx2x_get_rss_ind_table - Return the current ind_table configuration. 1386 * 1387 * @ind_table: buffer to fill with the current indirection 1388 * table content. Should be at least 1389 * T_ETH_INDIRECTION_TABLE_SIZE bytes long. 1390 */ 1391 void bnx2x_get_rss_ind_table(struct bnx2x_rss_config_obj *rss_obj, 1392 u8 *ind_table); 1393 1394 #endif /* BNX2X_SP_VERBS */ 1395