1adfc5217SJeff Kirsher /* bnx2x_sp.h: Broadcom Everest network driver. 2adfc5217SJeff Kirsher * 3247fa82bSYuval Mintz * Copyright (c) 2011-2013 Broadcom Corporation 4adfc5217SJeff Kirsher * 5adfc5217SJeff Kirsher * Unless you and Broadcom execute a separate written software license 6adfc5217SJeff Kirsher * agreement governing use of this software, this software is licensed to you 7adfc5217SJeff Kirsher * under the terms of the GNU General Public License version 2, available 8adfc5217SJeff Kirsher * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL"). 9adfc5217SJeff Kirsher * 10adfc5217SJeff Kirsher * Notwithstanding the above, under no circumstances may you combine this 11adfc5217SJeff Kirsher * software in any way with any other Broadcom software provided under a 12adfc5217SJeff Kirsher * license other than the GPL, without Broadcom's express prior written 13adfc5217SJeff Kirsher * consent. 14adfc5217SJeff Kirsher * 15adfc5217SJeff Kirsher * Maintained by: Eilon Greenstein <eilong@broadcom.com> 16adfc5217SJeff Kirsher * Written by: Vladislav Zolotarov 17adfc5217SJeff Kirsher * 18adfc5217SJeff Kirsher */ 19adfc5217SJeff Kirsher #ifndef BNX2X_SP_VERBS 20adfc5217SJeff Kirsher #define BNX2X_SP_VERBS 21adfc5217SJeff Kirsher 22adfc5217SJeff Kirsher struct bnx2x; 23adfc5217SJeff Kirsher struct eth_context; 24adfc5217SJeff Kirsher 25adfc5217SJeff Kirsher /* Bits representing general command's configuration */ 26adfc5217SJeff Kirsher enum { 27adfc5217SJeff Kirsher RAMROD_TX, 28adfc5217SJeff Kirsher RAMROD_RX, 29adfc5217SJeff Kirsher /* Wait until all pending commands complete */ 30adfc5217SJeff Kirsher RAMROD_COMP_WAIT, 31adfc5217SJeff Kirsher /* Don't send a ramrod, only update a registry */ 32adfc5217SJeff Kirsher RAMROD_DRV_CLR_ONLY, 33adfc5217SJeff Kirsher /* Configure HW according to the current object state */ 34adfc5217SJeff Kirsher RAMROD_RESTORE, 35adfc5217SJeff Kirsher /* Execute the next command now */ 36adfc5217SJeff Kirsher RAMROD_EXEC, 37adfc5217SJeff Kirsher /* 38adfc5217SJeff Kirsher * Don't add a new command and continue execution of posponed 39adfc5217SJeff Kirsher * commands. If not set a new command will be added to the 40adfc5217SJeff Kirsher * pending commands list. 41adfc5217SJeff Kirsher */ 42adfc5217SJeff Kirsher RAMROD_CONT, 4355c11941SMerav Sicron /* If there is another pending ramrod, wait until it finishes and 4455c11941SMerav Sicron * re-try to submit this one. This flag can be set only in sleepable 4555c11941SMerav Sicron * context, and should not be set from the context that completes the 4655c11941SMerav Sicron * ramrods as deadlock will occur. 4755c11941SMerav Sicron */ 4855c11941SMerav Sicron RAMROD_RETRY, 49adfc5217SJeff Kirsher }; 50adfc5217SJeff Kirsher 51adfc5217SJeff Kirsher typedef enum { 52adfc5217SJeff Kirsher BNX2X_OBJ_TYPE_RX, 53adfc5217SJeff Kirsher BNX2X_OBJ_TYPE_TX, 54adfc5217SJeff Kirsher BNX2X_OBJ_TYPE_RX_TX, 55adfc5217SJeff Kirsher } bnx2x_obj_type; 56adfc5217SJeff Kirsher 572de67439SYuval Mintz /* Public slow path states */ 58adfc5217SJeff Kirsher enum { 59adfc5217SJeff Kirsher BNX2X_FILTER_MAC_PENDING, 60adfc5217SJeff Kirsher BNX2X_FILTER_VLAN_PENDING, 61adfc5217SJeff Kirsher BNX2X_FILTER_VLAN_MAC_PENDING, 62adfc5217SJeff Kirsher BNX2X_FILTER_RX_MODE_PENDING, 63adfc5217SJeff Kirsher BNX2X_FILTER_RX_MODE_SCHED, 64adfc5217SJeff Kirsher BNX2X_FILTER_ISCSI_ETH_START_SCHED, 65adfc5217SJeff Kirsher BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, 66adfc5217SJeff Kirsher BNX2X_FILTER_FCOE_ETH_START_SCHED, 67adfc5217SJeff Kirsher BNX2X_FILTER_FCOE_ETH_STOP_SCHED, 68adfc5217SJeff Kirsher BNX2X_FILTER_MCAST_PENDING, 69adfc5217SJeff Kirsher BNX2X_FILTER_MCAST_SCHED, 70adfc5217SJeff Kirsher BNX2X_FILTER_RSS_CONF_PENDING, 71a3348722SBarak Witkowski BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, 72a3348722SBarak Witkowski BNX2X_AFEX_PENDING_VIFSET_MCP_ACK 73adfc5217SJeff Kirsher }; 74adfc5217SJeff Kirsher 75adfc5217SJeff Kirsher struct bnx2x_raw_obj { 76adfc5217SJeff Kirsher u8 func_id; 77adfc5217SJeff Kirsher 78adfc5217SJeff Kirsher /* Queue params */ 79adfc5217SJeff Kirsher u8 cl_id; 80adfc5217SJeff Kirsher u32 cid; 81adfc5217SJeff Kirsher 82adfc5217SJeff Kirsher /* Ramrod data buffer params */ 83adfc5217SJeff Kirsher void *rdata; 84adfc5217SJeff Kirsher dma_addr_t rdata_mapping; 85adfc5217SJeff Kirsher 86adfc5217SJeff Kirsher /* Ramrod state params */ 87adfc5217SJeff Kirsher int state; /* "ramrod is pending" state bit */ 88adfc5217SJeff Kirsher unsigned long *pstate; /* pointer to state buffer */ 89adfc5217SJeff Kirsher 90adfc5217SJeff Kirsher bnx2x_obj_type obj_type; 91adfc5217SJeff Kirsher 92adfc5217SJeff Kirsher int (*wait_comp)(struct bnx2x *bp, 93adfc5217SJeff Kirsher struct bnx2x_raw_obj *o); 94adfc5217SJeff Kirsher 95adfc5217SJeff Kirsher bool (*check_pending)(struct bnx2x_raw_obj *o); 96adfc5217SJeff Kirsher void (*clear_pending)(struct bnx2x_raw_obj *o); 97adfc5217SJeff Kirsher void (*set_pending)(struct bnx2x_raw_obj *o); 98adfc5217SJeff Kirsher }; 99adfc5217SJeff Kirsher 100adfc5217SJeff Kirsher /************************* VLAN-MAC commands related parameters ***************/ 101adfc5217SJeff Kirsher struct bnx2x_mac_ramrod_data { 102adfc5217SJeff Kirsher u8 mac[ETH_ALEN]; 103adfc5217SJeff Kirsher }; 104adfc5217SJeff Kirsher 105adfc5217SJeff Kirsher struct bnx2x_vlan_ramrod_data { 106adfc5217SJeff Kirsher u16 vlan; 107adfc5217SJeff Kirsher }; 108adfc5217SJeff Kirsher 109adfc5217SJeff Kirsher struct bnx2x_vlan_mac_ramrod_data { 110adfc5217SJeff Kirsher u8 mac[ETH_ALEN]; 111adfc5217SJeff Kirsher u16 vlan; 112adfc5217SJeff Kirsher }; 113adfc5217SJeff Kirsher 114adfc5217SJeff Kirsher union bnx2x_classification_ramrod_data { 115adfc5217SJeff Kirsher struct bnx2x_mac_ramrod_data mac; 116adfc5217SJeff Kirsher struct bnx2x_vlan_ramrod_data vlan; 117adfc5217SJeff Kirsher struct bnx2x_vlan_mac_ramrod_data vlan_mac; 118adfc5217SJeff Kirsher }; 119adfc5217SJeff Kirsher 120adfc5217SJeff Kirsher /* VLAN_MAC commands */ 121adfc5217SJeff Kirsher enum bnx2x_vlan_mac_cmd { 122adfc5217SJeff Kirsher BNX2X_VLAN_MAC_ADD, 123adfc5217SJeff Kirsher BNX2X_VLAN_MAC_DEL, 124adfc5217SJeff Kirsher BNX2X_VLAN_MAC_MOVE, 125adfc5217SJeff Kirsher }; 126adfc5217SJeff Kirsher 127adfc5217SJeff Kirsher struct bnx2x_vlan_mac_data { 128adfc5217SJeff Kirsher /* Requested command: BNX2X_VLAN_MAC_XX */ 129adfc5217SJeff Kirsher enum bnx2x_vlan_mac_cmd cmd; 130adfc5217SJeff Kirsher /* 131adfc5217SJeff Kirsher * used to contain the data related vlan_mac_flags bits from 132adfc5217SJeff Kirsher * ramrod parameters. 133adfc5217SJeff Kirsher */ 134adfc5217SJeff Kirsher unsigned long vlan_mac_flags; 135adfc5217SJeff Kirsher 136adfc5217SJeff Kirsher /* Needed for MOVE command */ 137adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *target_obj; 138adfc5217SJeff Kirsher 139adfc5217SJeff Kirsher union bnx2x_classification_ramrod_data u; 140adfc5217SJeff Kirsher }; 141adfc5217SJeff Kirsher 142adfc5217SJeff Kirsher /*************************** Exe Queue obj ************************************/ 143adfc5217SJeff Kirsher union bnx2x_exe_queue_cmd_data { 144adfc5217SJeff Kirsher struct bnx2x_vlan_mac_data vlan_mac; 145adfc5217SJeff Kirsher 146adfc5217SJeff Kirsher struct { 147adfc5217SJeff Kirsher /* TODO */ 148adfc5217SJeff Kirsher } mcast; 149adfc5217SJeff Kirsher }; 150adfc5217SJeff Kirsher 151adfc5217SJeff Kirsher struct bnx2x_exeq_elem { 152adfc5217SJeff Kirsher struct list_head link; 153adfc5217SJeff Kirsher 154adfc5217SJeff Kirsher /* Length of this element in the exe_chunk. */ 155adfc5217SJeff Kirsher int cmd_len; 156adfc5217SJeff Kirsher 157adfc5217SJeff Kirsher union bnx2x_exe_queue_cmd_data cmd_data; 158adfc5217SJeff Kirsher }; 159adfc5217SJeff Kirsher 160adfc5217SJeff Kirsher union bnx2x_qable_obj; 161adfc5217SJeff Kirsher 162adfc5217SJeff Kirsher union bnx2x_exeq_comp_elem { 163adfc5217SJeff Kirsher union event_ring_elem *elem; 164adfc5217SJeff Kirsher }; 165adfc5217SJeff Kirsher 166adfc5217SJeff Kirsher struct bnx2x_exe_queue_obj; 167adfc5217SJeff Kirsher 168adfc5217SJeff Kirsher typedef int (*exe_q_validate)(struct bnx2x *bp, 169adfc5217SJeff Kirsher union bnx2x_qable_obj *o, 170adfc5217SJeff Kirsher struct bnx2x_exeq_elem *elem); 171adfc5217SJeff Kirsher 172460a25cdSYuval Mintz typedef int (*exe_q_remove)(struct bnx2x *bp, 173460a25cdSYuval Mintz union bnx2x_qable_obj *o, 174460a25cdSYuval Mintz struct bnx2x_exeq_elem *elem); 175460a25cdSYuval Mintz 1761aa8b471SBen Hutchings /* Return positive if entry was optimized, 0 - if not, negative 177adfc5217SJeff Kirsher * in case of an error. 178adfc5217SJeff Kirsher */ 179adfc5217SJeff Kirsher typedef int (*exe_q_optimize)(struct bnx2x *bp, 180adfc5217SJeff Kirsher union bnx2x_qable_obj *o, 181adfc5217SJeff Kirsher struct bnx2x_exeq_elem *elem); 182adfc5217SJeff Kirsher typedef int (*exe_q_execute)(struct bnx2x *bp, 183adfc5217SJeff Kirsher union bnx2x_qable_obj *o, 184adfc5217SJeff Kirsher struct list_head *exe_chunk, 185adfc5217SJeff Kirsher unsigned long *ramrod_flags); 186adfc5217SJeff Kirsher typedef struct bnx2x_exeq_elem * 187adfc5217SJeff Kirsher (*exe_q_get)(struct bnx2x_exe_queue_obj *o, 188adfc5217SJeff Kirsher struct bnx2x_exeq_elem *elem); 189adfc5217SJeff Kirsher 190adfc5217SJeff Kirsher struct bnx2x_exe_queue_obj { 191adfc5217SJeff Kirsher /* 192adfc5217SJeff Kirsher * Commands pending for an execution. 193adfc5217SJeff Kirsher */ 194adfc5217SJeff Kirsher struct list_head exe_queue; 195adfc5217SJeff Kirsher 196adfc5217SJeff Kirsher /* 197adfc5217SJeff Kirsher * Commands pending for an completion. 198adfc5217SJeff Kirsher */ 199adfc5217SJeff Kirsher struct list_head pending_comp; 200adfc5217SJeff Kirsher 201adfc5217SJeff Kirsher spinlock_t lock; 202adfc5217SJeff Kirsher 203adfc5217SJeff Kirsher /* Maximum length of commands' list for one execution */ 204adfc5217SJeff Kirsher int exe_chunk_len; 205adfc5217SJeff Kirsher 206adfc5217SJeff Kirsher union bnx2x_qable_obj *owner; 207adfc5217SJeff Kirsher 208adfc5217SJeff Kirsher /****** Virtual functions ******/ 209adfc5217SJeff Kirsher /** 210adfc5217SJeff Kirsher * Called before commands execution for commands that are really 211adfc5217SJeff Kirsher * going to be executed (after 'optimize'). 212adfc5217SJeff Kirsher * 213adfc5217SJeff Kirsher * Must run under exe_queue->lock 214adfc5217SJeff Kirsher */ 215adfc5217SJeff Kirsher exe_q_validate validate; 216adfc5217SJeff Kirsher 217460a25cdSYuval Mintz /** 218460a25cdSYuval Mintz * Called before removing pending commands, cleaning allocated 219460a25cdSYuval Mintz * resources (e.g., credits from validate) 220460a25cdSYuval Mintz */ 221460a25cdSYuval Mintz exe_q_remove remove; 222adfc5217SJeff Kirsher 223adfc5217SJeff Kirsher /** 224adfc5217SJeff Kirsher * This will try to cancel the current pending commands list 225adfc5217SJeff Kirsher * considering the new command. 226adfc5217SJeff Kirsher * 227460a25cdSYuval Mintz * Returns the number of optimized commands or a negative error code 228460a25cdSYuval Mintz * 229adfc5217SJeff Kirsher * Must run under exe_queue->lock 230adfc5217SJeff Kirsher */ 231adfc5217SJeff Kirsher exe_q_optimize optimize; 232adfc5217SJeff Kirsher 233adfc5217SJeff Kirsher /** 234adfc5217SJeff Kirsher * Run the next commands chunk (owner specific). 235adfc5217SJeff Kirsher */ 236adfc5217SJeff Kirsher exe_q_execute execute; 237adfc5217SJeff Kirsher 238adfc5217SJeff Kirsher /** 239adfc5217SJeff Kirsher * Return the exe_queue element containing the specific command 240adfc5217SJeff Kirsher * if any. Otherwise return NULL. 241adfc5217SJeff Kirsher */ 242adfc5217SJeff Kirsher exe_q_get get; 243adfc5217SJeff Kirsher }; 244adfc5217SJeff Kirsher /***************** Classification verbs: Set/Del MAC/VLAN/VLAN-MAC ************/ 245adfc5217SJeff Kirsher /* 246adfc5217SJeff Kirsher * Element in the VLAN_MAC registry list having all currenty configured 247adfc5217SJeff Kirsher * rules. 248adfc5217SJeff Kirsher */ 249adfc5217SJeff Kirsher struct bnx2x_vlan_mac_registry_elem { 250adfc5217SJeff Kirsher struct list_head link; 251adfc5217SJeff Kirsher 252adfc5217SJeff Kirsher /* 253adfc5217SJeff Kirsher * Used to store the cam offset used for the mac/vlan/vlan-mac. 254adfc5217SJeff Kirsher * Relevant for 57710 and 57711 only. VLANs and MACs share the 255adfc5217SJeff Kirsher * same CAM for these chips. 256adfc5217SJeff Kirsher */ 257adfc5217SJeff Kirsher int cam_offset; 258adfc5217SJeff Kirsher 259adfc5217SJeff Kirsher /* Needed for DEL and RESTORE flows */ 260adfc5217SJeff Kirsher unsigned long vlan_mac_flags; 261adfc5217SJeff Kirsher 262adfc5217SJeff Kirsher union bnx2x_classification_ramrod_data u; 263adfc5217SJeff Kirsher }; 264adfc5217SJeff Kirsher 265adfc5217SJeff Kirsher /* Bits representing VLAN_MAC commands specific flags */ 266adfc5217SJeff Kirsher enum { 267adfc5217SJeff Kirsher BNX2X_UC_LIST_MAC, 268adfc5217SJeff Kirsher BNX2X_ETH_MAC, 269adfc5217SJeff Kirsher BNX2X_ISCSI_ETH_MAC, 270adfc5217SJeff Kirsher BNX2X_NETQ_ETH_MAC, 271adfc5217SJeff Kirsher BNX2X_DONT_CONSUME_CAM_CREDIT, 272adfc5217SJeff Kirsher BNX2X_DONT_CONSUME_CAM_CREDIT_DEST, 273adfc5217SJeff Kirsher }; 274adfc5217SJeff Kirsher 275adfc5217SJeff Kirsher struct bnx2x_vlan_mac_ramrod_params { 276adfc5217SJeff Kirsher /* Object to run the command from */ 277adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *vlan_mac_obj; 278adfc5217SJeff Kirsher 279adfc5217SJeff Kirsher /* General command flags: COMP_WAIT, etc. */ 280adfc5217SJeff Kirsher unsigned long ramrod_flags; 281adfc5217SJeff Kirsher 282adfc5217SJeff Kirsher /* Command specific configuration request */ 283adfc5217SJeff Kirsher struct bnx2x_vlan_mac_data user_req; 284adfc5217SJeff Kirsher }; 285adfc5217SJeff Kirsher 286adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj { 287adfc5217SJeff Kirsher struct bnx2x_raw_obj raw; 288adfc5217SJeff Kirsher 289adfc5217SJeff Kirsher /* Bookkeeping list: will prevent the addition of already existing 290adfc5217SJeff Kirsher * entries. 291adfc5217SJeff Kirsher */ 292adfc5217SJeff Kirsher struct list_head head; 293adfc5217SJeff Kirsher 294adfc5217SJeff Kirsher /* TODO: Add it's initialization in the init functions */ 295adfc5217SJeff Kirsher struct bnx2x_exe_queue_obj exe_queue; 296adfc5217SJeff Kirsher 297adfc5217SJeff Kirsher /* MACs credit pool */ 298adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *macs_pool; 299adfc5217SJeff Kirsher 300adfc5217SJeff Kirsher /* VLANs credit pool */ 301adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *vlans_pool; 302adfc5217SJeff Kirsher 303adfc5217SJeff Kirsher /* RAMROD command to be used */ 304adfc5217SJeff Kirsher int ramrod_cmd; 305adfc5217SJeff Kirsher 306ed5162a0SAriel Elior /* copy first n elements onto preallocated buffer 307ed5162a0SAriel Elior * 308ed5162a0SAriel Elior * @param n number of elements to get 309ed5162a0SAriel Elior * @param buf buffer preallocated by caller into which elements 310ed5162a0SAriel Elior * will be copied. Note elements are 4-byte aligned 311ed5162a0SAriel Elior * so buffer size must be able to accomodate the 312ed5162a0SAriel Elior * aligned elements. 313ed5162a0SAriel Elior * 314ed5162a0SAriel Elior * @return number of copied bytes 315ed5162a0SAriel Elior */ 316ed5162a0SAriel Elior int (*get_n_elements)(struct bnx2x *bp, struct bnx2x_vlan_mac_obj *o, 317ed5162a0SAriel Elior int n, u8 *buf); 318ed5162a0SAriel Elior 319adfc5217SJeff Kirsher /** 320adfc5217SJeff Kirsher * Checks if ADD-ramrod with the given params may be performed. 321adfc5217SJeff Kirsher * 322adfc5217SJeff Kirsher * @return zero if the element may be added 323adfc5217SJeff Kirsher */ 324adfc5217SJeff Kirsher 32551c1a580SMerav Sicron int (*check_add)(struct bnx2x *bp, 32651c1a580SMerav Sicron struct bnx2x_vlan_mac_obj *o, 327adfc5217SJeff Kirsher union bnx2x_classification_ramrod_data *data); 328adfc5217SJeff Kirsher 329adfc5217SJeff Kirsher /** 330adfc5217SJeff Kirsher * Checks if DEL-ramrod with the given params may be performed. 331adfc5217SJeff Kirsher * 332adfc5217SJeff Kirsher * @return true if the element may be deleted 333adfc5217SJeff Kirsher */ 334adfc5217SJeff Kirsher struct bnx2x_vlan_mac_registry_elem * 33551c1a580SMerav Sicron (*check_del)(struct bnx2x *bp, 33651c1a580SMerav Sicron struct bnx2x_vlan_mac_obj *o, 337adfc5217SJeff Kirsher union bnx2x_classification_ramrod_data *data); 338adfc5217SJeff Kirsher 339adfc5217SJeff Kirsher /** 340adfc5217SJeff Kirsher * Checks if DEL-ramrod with the given params may be performed. 341adfc5217SJeff Kirsher * 342adfc5217SJeff Kirsher * @return true if the element may be deleted 343adfc5217SJeff Kirsher */ 34451c1a580SMerav Sicron bool (*check_move)(struct bnx2x *bp, 34551c1a580SMerav Sicron struct bnx2x_vlan_mac_obj *src_o, 346adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *dst_o, 347adfc5217SJeff Kirsher union bnx2x_classification_ramrod_data *data); 348adfc5217SJeff Kirsher 349adfc5217SJeff Kirsher /** 350adfc5217SJeff Kirsher * Update the relevant credit object(s) (consume/return 351adfc5217SJeff Kirsher * correspondingly). 352adfc5217SJeff Kirsher */ 353adfc5217SJeff Kirsher bool (*get_credit)(struct bnx2x_vlan_mac_obj *o); 354adfc5217SJeff Kirsher bool (*put_credit)(struct bnx2x_vlan_mac_obj *o); 355adfc5217SJeff Kirsher bool (*get_cam_offset)(struct bnx2x_vlan_mac_obj *o, int *offset); 356adfc5217SJeff Kirsher bool (*put_cam_offset)(struct bnx2x_vlan_mac_obj *o, int offset); 357adfc5217SJeff Kirsher 358adfc5217SJeff Kirsher /** 359adfc5217SJeff Kirsher * Configures one rule in the ramrod data buffer. 360adfc5217SJeff Kirsher */ 361adfc5217SJeff Kirsher void (*set_one_rule)(struct bnx2x *bp, 362adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *o, 363adfc5217SJeff Kirsher struct bnx2x_exeq_elem *elem, int rule_idx, 364adfc5217SJeff Kirsher int cam_offset); 365adfc5217SJeff Kirsher 366adfc5217SJeff Kirsher /** 367adfc5217SJeff Kirsher * Delete all configured elements having the given 368adfc5217SJeff Kirsher * vlan_mac_flags specification. Assumes no pending for 369adfc5217SJeff Kirsher * execution commands. Will schedule all all currently 370adfc5217SJeff Kirsher * configured MACs/VLANs/VLAN-MACs matching the vlan_mac_flags 371adfc5217SJeff Kirsher * specification for deletion and will use the given 372adfc5217SJeff Kirsher * ramrod_flags for the last DEL operation. 373adfc5217SJeff Kirsher * 374adfc5217SJeff Kirsher * @param bp 375adfc5217SJeff Kirsher * @param o 376adfc5217SJeff Kirsher * @param ramrod_flags RAMROD_XX flags 377adfc5217SJeff Kirsher * 378adfc5217SJeff Kirsher * @return 0 if the last operation has completed successfully 379adfc5217SJeff Kirsher * and there are no more elements left, positive value 380adfc5217SJeff Kirsher * if there are pending for completion commands, 381adfc5217SJeff Kirsher * negative value in case of failure. 382adfc5217SJeff Kirsher */ 383adfc5217SJeff Kirsher int (*delete_all)(struct bnx2x *bp, 384adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *o, 385adfc5217SJeff Kirsher unsigned long *vlan_mac_flags, 386adfc5217SJeff Kirsher unsigned long *ramrod_flags); 387adfc5217SJeff Kirsher 388adfc5217SJeff Kirsher /** 389adfc5217SJeff Kirsher * Reconfigures the next MAC/VLAN/VLAN-MAC element from the previously 390adfc5217SJeff Kirsher * configured elements list. 391adfc5217SJeff Kirsher * 392adfc5217SJeff Kirsher * @param bp 393adfc5217SJeff Kirsher * @param p Command parameters (RAMROD_COMP_WAIT bit in 394adfc5217SJeff Kirsher * ramrod_flags is only taken into an account) 395adfc5217SJeff Kirsher * @param ppos a pointer to the cooky that should be given back in the 396adfc5217SJeff Kirsher * next call to make function handle the next element. If 397adfc5217SJeff Kirsher * *ppos is set to NULL it will restart the iterator. 398adfc5217SJeff Kirsher * If returned *ppos == NULL this means that the last 399adfc5217SJeff Kirsher * element has been handled. 400adfc5217SJeff Kirsher * 401adfc5217SJeff Kirsher * @return int 402adfc5217SJeff Kirsher */ 403adfc5217SJeff Kirsher int (*restore)(struct bnx2x *bp, 404adfc5217SJeff Kirsher struct bnx2x_vlan_mac_ramrod_params *p, 405adfc5217SJeff Kirsher struct bnx2x_vlan_mac_registry_elem **ppos); 406adfc5217SJeff Kirsher 407adfc5217SJeff Kirsher /** 408adfc5217SJeff Kirsher * Should be called on a completion arival. 409adfc5217SJeff Kirsher * 410adfc5217SJeff Kirsher * @param bp 411adfc5217SJeff Kirsher * @param o 412adfc5217SJeff Kirsher * @param cqe Completion element we are handling 413adfc5217SJeff Kirsher * @param ramrod_flags if RAMROD_CONT is set the next bulk of 414adfc5217SJeff Kirsher * pending commands will be executed. 415adfc5217SJeff Kirsher * RAMROD_DRV_CLR_ONLY and RAMROD_RESTORE 416adfc5217SJeff Kirsher * may also be set if needed. 417adfc5217SJeff Kirsher * 418adfc5217SJeff Kirsher * @return 0 if there are neither pending nor waiting for 419adfc5217SJeff Kirsher * completion commands. Positive value if there are 420adfc5217SJeff Kirsher * pending for execution or for completion commands. 421adfc5217SJeff Kirsher * Negative value in case of an error (including an 422adfc5217SJeff Kirsher * error in the cqe). 423adfc5217SJeff Kirsher */ 424adfc5217SJeff Kirsher int (*complete)(struct bnx2x *bp, struct bnx2x_vlan_mac_obj *o, 425adfc5217SJeff Kirsher union event_ring_elem *cqe, 426adfc5217SJeff Kirsher unsigned long *ramrod_flags); 427adfc5217SJeff Kirsher 428adfc5217SJeff Kirsher /** 429adfc5217SJeff Kirsher * Wait for completion of all commands. Don't schedule new ones, 430adfc5217SJeff Kirsher * just wait. It assumes that the completion code will schedule 431adfc5217SJeff Kirsher * for new commands. 432adfc5217SJeff Kirsher */ 433adfc5217SJeff Kirsher int (*wait)(struct bnx2x *bp, struct bnx2x_vlan_mac_obj *o); 434adfc5217SJeff Kirsher }; 435adfc5217SJeff Kirsher 4360a52fd01SYuval Mintz enum { 4370a52fd01SYuval Mintz BNX2X_LLH_CAM_ISCSI_ETH_LINE = 0, 4380a52fd01SYuval Mintz BNX2X_LLH_CAM_ETH_LINE, 4390a52fd01SYuval Mintz BNX2X_LLH_CAM_MAX_PF_LINE = NIG_REG_LLH1_FUNC_MEM_SIZE / 2 4400a52fd01SYuval Mintz }; 4410a52fd01SYuval Mintz 442a3348722SBarak Witkowski void bnx2x_set_mac_in_nig(struct bnx2x *bp, 443a3348722SBarak Witkowski bool add, unsigned char *dev_addr, int index); 4440a52fd01SYuval Mintz 445adfc5217SJeff Kirsher /** RX_MODE verbs:DROP_ALL/ACCEPT_ALL/ACCEPT_ALL_MULTI/ACCEPT_ALL_VLAN/NORMAL */ 446adfc5217SJeff Kirsher 447adfc5217SJeff Kirsher /* RX_MODE ramrod spesial flags: set in rx_mode_flags field in 448adfc5217SJeff Kirsher * a bnx2x_rx_mode_ramrod_params. 449adfc5217SJeff Kirsher */ 450adfc5217SJeff Kirsher enum { 451adfc5217SJeff Kirsher BNX2X_RX_MODE_FCOE_ETH, 452adfc5217SJeff Kirsher BNX2X_RX_MODE_ISCSI_ETH, 453adfc5217SJeff Kirsher }; 454adfc5217SJeff Kirsher 455adfc5217SJeff Kirsher enum { 456adfc5217SJeff Kirsher BNX2X_ACCEPT_UNICAST, 457adfc5217SJeff Kirsher BNX2X_ACCEPT_MULTICAST, 458adfc5217SJeff Kirsher BNX2X_ACCEPT_ALL_UNICAST, 459adfc5217SJeff Kirsher BNX2X_ACCEPT_ALL_MULTICAST, 460adfc5217SJeff Kirsher BNX2X_ACCEPT_BROADCAST, 461adfc5217SJeff Kirsher BNX2X_ACCEPT_UNMATCHED, 462adfc5217SJeff Kirsher BNX2X_ACCEPT_ANY_VLAN 463adfc5217SJeff Kirsher }; 464adfc5217SJeff Kirsher 465adfc5217SJeff Kirsher struct bnx2x_rx_mode_ramrod_params { 466adfc5217SJeff Kirsher struct bnx2x_rx_mode_obj *rx_mode_obj; 467adfc5217SJeff Kirsher unsigned long *pstate; 468adfc5217SJeff Kirsher int state; 469adfc5217SJeff Kirsher u8 cl_id; 470adfc5217SJeff Kirsher u32 cid; 471adfc5217SJeff Kirsher u8 func_id; 472adfc5217SJeff Kirsher unsigned long ramrod_flags; 473adfc5217SJeff Kirsher unsigned long rx_mode_flags; 474adfc5217SJeff Kirsher 475adfc5217SJeff Kirsher /* 476adfc5217SJeff Kirsher * rdata is either a pointer to eth_filter_rules_ramrod_data(e2) or to 477adfc5217SJeff Kirsher * a tstorm_eth_mac_filter_config (e1x). 478adfc5217SJeff Kirsher */ 479adfc5217SJeff Kirsher void *rdata; 480adfc5217SJeff Kirsher dma_addr_t rdata_mapping; 481adfc5217SJeff Kirsher 482adfc5217SJeff Kirsher /* Rx mode settings */ 483adfc5217SJeff Kirsher unsigned long rx_accept_flags; 484adfc5217SJeff Kirsher 485adfc5217SJeff Kirsher /* internal switching settings */ 486adfc5217SJeff Kirsher unsigned long tx_accept_flags; 487adfc5217SJeff Kirsher }; 488adfc5217SJeff Kirsher 489adfc5217SJeff Kirsher struct bnx2x_rx_mode_obj { 490adfc5217SJeff Kirsher int (*config_rx_mode)(struct bnx2x *bp, 491adfc5217SJeff Kirsher struct bnx2x_rx_mode_ramrod_params *p); 492adfc5217SJeff Kirsher 493adfc5217SJeff Kirsher int (*wait_comp)(struct bnx2x *bp, 494adfc5217SJeff Kirsher struct bnx2x_rx_mode_ramrod_params *p); 495adfc5217SJeff Kirsher }; 496adfc5217SJeff Kirsher 497adfc5217SJeff Kirsher /********************** Set multicast group ***********************************/ 498adfc5217SJeff Kirsher 499adfc5217SJeff Kirsher struct bnx2x_mcast_list_elem { 500adfc5217SJeff Kirsher struct list_head link; 501adfc5217SJeff Kirsher u8 *mac; 502adfc5217SJeff Kirsher }; 503adfc5217SJeff Kirsher 504adfc5217SJeff Kirsher union bnx2x_mcast_config_data { 505adfc5217SJeff Kirsher u8 *mac; 506adfc5217SJeff Kirsher u8 bin; /* used in a RESTORE flow */ 507adfc5217SJeff Kirsher }; 508adfc5217SJeff Kirsher 509adfc5217SJeff Kirsher struct bnx2x_mcast_ramrod_params { 510adfc5217SJeff Kirsher struct bnx2x_mcast_obj *mcast_obj; 511adfc5217SJeff Kirsher 512adfc5217SJeff Kirsher /* Relevant options are RAMROD_COMP_WAIT and RAMROD_DRV_CLR_ONLY */ 513adfc5217SJeff Kirsher unsigned long ramrod_flags; 514adfc5217SJeff Kirsher 515adfc5217SJeff Kirsher struct list_head mcast_list; /* list of struct bnx2x_mcast_list_elem */ 516adfc5217SJeff Kirsher /** TODO: 517adfc5217SJeff Kirsher * - rename it to macs_num. 518adfc5217SJeff Kirsher * - Add a new command type for handling pending commands 519adfc5217SJeff Kirsher * (remove "zero semantics"). 520adfc5217SJeff Kirsher * 521adfc5217SJeff Kirsher * Length of mcast_list. If zero and ADD_CONT command - post 522adfc5217SJeff Kirsher * pending commands. 523adfc5217SJeff Kirsher */ 524adfc5217SJeff Kirsher int mcast_list_len; 525adfc5217SJeff Kirsher }; 526adfc5217SJeff Kirsher 52786564c3fSYuval Mintz enum bnx2x_mcast_cmd { 528adfc5217SJeff Kirsher BNX2X_MCAST_CMD_ADD, 529adfc5217SJeff Kirsher BNX2X_MCAST_CMD_CONT, 530adfc5217SJeff Kirsher BNX2X_MCAST_CMD_DEL, 531adfc5217SJeff Kirsher BNX2X_MCAST_CMD_RESTORE, 532adfc5217SJeff Kirsher }; 533adfc5217SJeff Kirsher 534adfc5217SJeff Kirsher struct bnx2x_mcast_obj { 535adfc5217SJeff Kirsher struct bnx2x_raw_obj raw; 536adfc5217SJeff Kirsher 537adfc5217SJeff Kirsher union { 538adfc5217SJeff Kirsher struct { 539adfc5217SJeff Kirsher #define BNX2X_MCAST_BINS_NUM 256 540adfc5217SJeff Kirsher #define BNX2X_MCAST_VEC_SZ (BNX2X_MCAST_BINS_NUM / 64) 541adfc5217SJeff Kirsher u64 vec[BNX2X_MCAST_VEC_SZ]; 542adfc5217SJeff Kirsher 543adfc5217SJeff Kirsher /** Number of BINs to clear. Should be updated 544adfc5217SJeff Kirsher * immediately when a command arrives in order to 545adfc5217SJeff Kirsher * properly create DEL commands. 546adfc5217SJeff Kirsher */ 547adfc5217SJeff Kirsher int num_bins_set; 548adfc5217SJeff Kirsher } aprox_match; 549adfc5217SJeff Kirsher 550adfc5217SJeff Kirsher struct { 551adfc5217SJeff Kirsher struct list_head macs; 552adfc5217SJeff Kirsher int num_macs_set; 553adfc5217SJeff Kirsher } exact_match; 554adfc5217SJeff Kirsher } registry; 555adfc5217SJeff Kirsher 556adfc5217SJeff Kirsher /* Pending commands */ 557adfc5217SJeff Kirsher struct list_head pending_cmds_head; 558adfc5217SJeff Kirsher 559adfc5217SJeff Kirsher /* A state that is set in raw.pstate, when there are pending commands */ 560adfc5217SJeff Kirsher int sched_state; 561adfc5217SJeff Kirsher 562adfc5217SJeff Kirsher /* Maximal number of mcast MACs configured in one command */ 563adfc5217SJeff Kirsher int max_cmd_len; 564adfc5217SJeff Kirsher 565adfc5217SJeff Kirsher /* Total number of currently pending MACs to configure: both 566adfc5217SJeff Kirsher * in the pending commands list and in the current command. 567adfc5217SJeff Kirsher */ 568adfc5217SJeff Kirsher int total_pending_num; 569adfc5217SJeff Kirsher 570adfc5217SJeff Kirsher u8 engine_id; 571adfc5217SJeff Kirsher 572adfc5217SJeff Kirsher /** 573adfc5217SJeff Kirsher * @param cmd command to execute (BNX2X_MCAST_CMD_X, see above) 574adfc5217SJeff Kirsher */ 575adfc5217SJeff Kirsher int (*config_mcast)(struct bnx2x *bp, 57686564c3fSYuval Mintz struct bnx2x_mcast_ramrod_params *p, 57786564c3fSYuval Mintz enum bnx2x_mcast_cmd cmd); 578adfc5217SJeff Kirsher 579adfc5217SJeff Kirsher /** 580adfc5217SJeff Kirsher * Fills the ramrod data during the RESTORE flow. 581adfc5217SJeff Kirsher * 582adfc5217SJeff Kirsher * @param bp 583adfc5217SJeff Kirsher * @param o 584adfc5217SJeff Kirsher * @param start_idx Registry index to start from 585adfc5217SJeff Kirsher * @param rdata_idx Index in the ramrod data to start from 586adfc5217SJeff Kirsher * 587adfc5217SJeff Kirsher * @return -1 if we handled the whole registry or index of the last 588adfc5217SJeff Kirsher * handled registry element. 589adfc5217SJeff Kirsher */ 590adfc5217SJeff Kirsher int (*hdl_restore)(struct bnx2x *bp, struct bnx2x_mcast_obj *o, 591adfc5217SJeff Kirsher int start_bin, int *rdata_idx); 592adfc5217SJeff Kirsher 593adfc5217SJeff Kirsher int (*enqueue_cmd)(struct bnx2x *bp, struct bnx2x_mcast_obj *o, 59486564c3fSYuval Mintz struct bnx2x_mcast_ramrod_params *p, 59586564c3fSYuval Mintz enum bnx2x_mcast_cmd cmd); 596adfc5217SJeff Kirsher 597adfc5217SJeff Kirsher void (*set_one_rule)(struct bnx2x *bp, 598adfc5217SJeff Kirsher struct bnx2x_mcast_obj *o, int idx, 59986564c3fSYuval Mintz union bnx2x_mcast_config_data *cfg_data, 60086564c3fSYuval Mintz enum bnx2x_mcast_cmd cmd); 601adfc5217SJeff Kirsher 602adfc5217SJeff Kirsher /** Checks if there are more mcast MACs to be set or a previous 603adfc5217SJeff Kirsher * command is still pending. 604adfc5217SJeff Kirsher */ 605adfc5217SJeff Kirsher bool (*check_pending)(struct bnx2x_mcast_obj *o); 606adfc5217SJeff Kirsher 607adfc5217SJeff Kirsher /** 608adfc5217SJeff Kirsher * Set/Clear/Check SCHEDULED state of the object 609adfc5217SJeff Kirsher */ 610adfc5217SJeff Kirsher void (*set_sched)(struct bnx2x_mcast_obj *o); 611adfc5217SJeff Kirsher void (*clear_sched)(struct bnx2x_mcast_obj *o); 612adfc5217SJeff Kirsher bool (*check_sched)(struct bnx2x_mcast_obj *o); 613adfc5217SJeff Kirsher 614adfc5217SJeff Kirsher /* Wait until all pending commands complete */ 615adfc5217SJeff Kirsher int (*wait_comp)(struct bnx2x *bp, struct bnx2x_mcast_obj *o); 616adfc5217SJeff Kirsher 617adfc5217SJeff Kirsher /** 618adfc5217SJeff Kirsher * Handle the internal object counters needed for proper 619adfc5217SJeff Kirsher * commands handling. Checks that the provided parameters are 620adfc5217SJeff Kirsher * feasible. 621adfc5217SJeff Kirsher */ 622adfc5217SJeff Kirsher int (*validate)(struct bnx2x *bp, 62386564c3fSYuval Mintz struct bnx2x_mcast_ramrod_params *p, 62486564c3fSYuval Mintz enum bnx2x_mcast_cmd cmd); 625adfc5217SJeff Kirsher 626adfc5217SJeff Kirsher /** 627adfc5217SJeff Kirsher * Restore the values of internal counters in case of a failure. 628adfc5217SJeff Kirsher */ 629adfc5217SJeff Kirsher void (*revert)(struct bnx2x *bp, 630adfc5217SJeff Kirsher struct bnx2x_mcast_ramrod_params *p, 631adfc5217SJeff Kirsher int old_num_bins); 632adfc5217SJeff Kirsher 633adfc5217SJeff Kirsher int (*get_registry_size)(struct bnx2x_mcast_obj *o); 634adfc5217SJeff Kirsher void (*set_registry_size)(struct bnx2x_mcast_obj *o, int n); 635adfc5217SJeff Kirsher }; 636adfc5217SJeff Kirsher 637adfc5217SJeff Kirsher /*************************** Credit handling **********************************/ 638adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj { 639adfc5217SJeff Kirsher 640adfc5217SJeff Kirsher /* Current amount of credit in the pool */ 641adfc5217SJeff Kirsher atomic_t credit; 642adfc5217SJeff Kirsher 643adfc5217SJeff Kirsher /* Maximum allowed credit. put() will check against it. */ 644adfc5217SJeff Kirsher int pool_sz; 645adfc5217SJeff Kirsher 646adfc5217SJeff Kirsher /* 647adfc5217SJeff Kirsher * Allocate a pool table statically. 648adfc5217SJeff Kirsher * 649adfc5217SJeff Kirsher * Currently the mamimum allowed size is MAX_MAC_CREDIT_E2(272) 650adfc5217SJeff Kirsher * 651adfc5217SJeff Kirsher * The set bit in the table will mean that the entry is available. 652adfc5217SJeff Kirsher */ 653adfc5217SJeff Kirsher #define BNX2X_POOL_VEC_SIZE (MAX_MAC_CREDIT_E2 / 64) 654adfc5217SJeff Kirsher u64 pool_mirror[BNX2X_POOL_VEC_SIZE]; 655adfc5217SJeff Kirsher 656adfc5217SJeff Kirsher /* Base pool offset (initialized differently */ 657adfc5217SJeff Kirsher int base_pool_offset; 658adfc5217SJeff Kirsher 659adfc5217SJeff Kirsher /** 660adfc5217SJeff Kirsher * Get the next free pool entry. 661adfc5217SJeff Kirsher * 662adfc5217SJeff Kirsher * @return true if there was a free entry in the pool 663adfc5217SJeff Kirsher */ 664adfc5217SJeff Kirsher bool (*get_entry)(struct bnx2x_credit_pool_obj *o, int *entry); 665adfc5217SJeff Kirsher 666adfc5217SJeff Kirsher /** 667adfc5217SJeff Kirsher * Return the entry back to the pool. 668adfc5217SJeff Kirsher * 669adfc5217SJeff Kirsher * @return true if entry is legal and has been successfully 670adfc5217SJeff Kirsher * returned to the pool. 671adfc5217SJeff Kirsher */ 672adfc5217SJeff Kirsher bool (*put_entry)(struct bnx2x_credit_pool_obj *o, int entry); 673adfc5217SJeff Kirsher 674adfc5217SJeff Kirsher /** 675adfc5217SJeff Kirsher * Get the requested amount of credit from the pool. 676adfc5217SJeff Kirsher * 677adfc5217SJeff Kirsher * @param cnt Amount of requested credit 678adfc5217SJeff Kirsher * @return true if the operation is successful 679adfc5217SJeff Kirsher */ 680adfc5217SJeff Kirsher bool (*get)(struct bnx2x_credit_pool_obj *o, int cnt); 681adfc5217SJeff Kirsher 682adfc5217SJeff Kirsher /** 683adfc5217SJeff Kirsher * Returns the credit to the pool. 684adfc5217SJeff Kirsher * 685adfc5217SJeff Kirsher * @param cnt Amount of credit to return 686adfc5217SJeff Kirsher * @return true if the operation is successful 687adfc5217SJeff Kirsher */ 688adfc5217SJeff Kirsher bool (*put)(struct bnx2x_credit_pool_obj *o, int cnt); 689adfc5217SJeff Kirsher 690adfc5217SJeff Kirsher /** 691adfc5217SJeff Kirsher * Reads the current amount of credit. 692adfc5217SJeff Kirsher */ 693adfc5217SJeff Kirsher int (*check)(struct bnx2x_credit_pool_obj *o); 694adfc5217SJeff Kirsher }; 695adfc5217SJeff Kirsher 696adfc5217SJeff Kirsher /*************************** RSS configuration ********************************/ 697adfc5217SJeff Kirsher enum { 698adfc5217SJeff Kirsher /* RSS_MODE bits are mutually exclusive */ 699adfc5217SJeff Kirsher BNX2X_RSS_MODE_DISABLED, 700adfc5217SJeff Kirsher BNX2X_RSS_MODE_REGULAR, 701adfc5217SJeff Kirsher 702adfc5217SJeff Kirsher BNX2X_RSS_SET_SRCH, /* Setup searcher, E1x specific flag */ 703adfc5217SJeff Kirsher 704adfc5217SJeff Kirsher BNX2X_RSS_IPV4, 705adfc5217SJeff Kirsher BNX2X_RSS_IPV4_TCP, 7065d317c6aSMerav Sicron BNX2X_RSS_IPV4_UDP, 707adfc5217SJeff Kirsher BNX2X_RSS_IPV6, 708adfc5217SJeff Kirsher BNX2X_RSS_IPV6_TCP, 7095d317c6aSMerav Sicron BNX2X_RSS_IPV6_UDP, 710adfc5217SJeff Kirsher }; 711adfc5217SJeff Kirsher 712adfc5217SJeff Kirsher struct bnx2x_config_rss_params { 713adfc5217SJeff Kirsher struct bnx2x_rss_config_obj *rss_obj; 714adfc5217SJeff Kirsher 715adfc5217SJeff Kirsher /* may have RAMROD_COMP_WAIT set only */ 716adfc5217SJeff Kirsher unsigned long ramrod_flags; 717adfc5217SJeff Kirsher 718adfc5217SJeff Kirsher /* BNX2X_RSS_X bits */ 719adfc5217SJeff Kirsher unsigned long rss_flags; 720adfc5217SJeff Kirsher 721adfc5217SJeff Kirsher /* Number hash bits to take into an account */ 722adfc5217SJeff Kirsher u8 rss_result_mask; 723adfc5217SJeff Kirsher 724adfc5217SJeff Kirsher /* Indirection table */ 725adfc5217SJeff Kirsher u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE]; 726adfc5217SJeff Kirsher 727adfc5217SJeff Kirsher /* RSS hash values */ 728adfc5217SJeff Kirsher u32 rss_key[10]; 729adfc5217SJeff Kirsher 730adfc5217SJeff Kirsher /* valid only iff BNX2X_RSS_UPDATE_TOE is set */ 731adfc5217SJeff Kirsher u16 toe_rss_bitmap; 732adfc5217SJeff Kirsher }; 733adfc5217SJeff Kirsher 734adfc5217SJeff Kirsher struct bnx2x_rss_config_obj { 735adfc5217SJeff Kirsher struct bnx2x_raw_obj raw; 736adfc5217SJeff Kirsher 737adfc5217SJeff Kirsher /* RSS engine to use */ 738adfc5217SJeff Kirsher u8 engine_id; 739adfc5217SJeff Kirsher 740adfc5217SJeff Kirsher /* Last configured indirection table */ 741adfc5217SJeff Kirsher u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE]; 742adfc5217SJeff Kirsher 7435d317c6aSMerav Sicron /* flags for enabling 4-tupple hash on UDP */ 7445d317c6aSMerav Sicron u8 udp_rss_v4; 7455d317c6aSMerav Sicron u8 udp_rss_v6; 7465d317c6aSMerav Sicron 747adfc5217SJeff Kirsher int (*config_rss)(struct bnx2x *bp, 748adfc5217SJeff Kirsher struct bnx2x_config_rss_params *p); 749adfc5217SJeff Kirsher }; 750adfc5217SJeff Kirsher 751adfc5217SJeff Kirsher /*********************** Queue state update ***********************************/ 752adfc5217SJeff Kirsher 753adfc5217SJeff Kirsher /* UPDATE command options */ 754adfc5217SJeff Kirsher enum { 755adfc5217SJeff Kirsher BNX2X_Q_UPDATE_IN_VLAN_REM, 756adfc5217SJeff Kirsher BNX2X_Q_UPDATE_IN_VLAN_REM_CHNG, 757adfc5217SJeff Kirsher BNX2X_Q_UPDATE_OUT_VLAN_REM, 758adfc5217SJeff Kirsher BNX2X_Q_UPDATE_OUT_VLAN_REM_CHNG, 759adfc5217SJeff Kirsher BNX2X_Q_UPDATE_ANTI_SPOOF, 760adfc5217SJeff Kirsher BNX2X_Q_UPDATE_ANTI_SPOOF_CHNG, 761adfc5217SJeff Kirsher BNX2X_Q_UPDATE_ACTIVATE, 762adfc5217SJeff Kirsher BNX2X_Q_UPDATE_ACTIVATE_CHNG, 763adfc5217SJeff Kirsher BNX2X_Q_UPDATE_DEF_VLAN_EN, 764adfc5217SJeff Kirsher BNX2X_Q_UPDATE_DEF_VLAN_EN_CHNG, 765adfc5217SJeff Kirsher BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG, 766adfc5217SJeff Kirsher BNX2X_Q_UPDATE_SILENT_VLAN_REM 767adfc5217SJeff Kirsher }; 768adfc5217SJeff Kirsher 769adfc5217SJeff Kirsher /* Allowed Queue states */ 770adfc5217SJeff Kirsher enum bnx2x_q_state { 771adfc5217SJeff Kirsher BNX2X_Q_STATE_RESET, 772adfc5217SJeff Kirsher BNX2X_Q_STATE_INITIALIZED, 773adfc5217SJeff Kirsher BNX2X_Q_STATE_ACTIVE, 774adfc5217SJeff Kirsher BNX2X_Q_STATE_MULTI_COS, 775adfc5217SJeff Kirsher BNX2X_Q_STATE_MCOS_TERMINATED, 776adfc5217SJeff Kirsher BNX2X_Q_STATE_INACTIVE, 777adfc5217SJeff Kirsher BNX2X_Q_STATE_STOPPED, 778adfc5217SJeff Kirsher BNX2X_Q_STATE_TERMINATED, 779adfc5217SJeff Kirsher BNX2X_Q_STATE_FLRED, 780adfc5217SJeff Kirsher BNX2X_Q_STATE_MAX, 781adfc5217SJeff Kirsher }; 782adfc5217SJeff Kirsher 78367c431a5SAriel Elior /* Allowed Queue states */ 78467c431a5SAriel Elior enum bnx2x_q_logical_state { 78567c431a5SAriel Elior BNX2X_Q_LOGICAL_STATE_ACTIVE, 78667c431a5SAriel Elior BNX2X_Q_LOGICAL_STATE_STOPPED, 78767c431a5SAriel Elior }; 78867c431a5SAriel Elior 789adfc5217SJeff Kirsher /* Allowed commands */ 790adfc5217SJeff Kirsher enum bnx2x_queue_cmd { 791adfc5217SJeff Kirsher BNX2X_Q_CMD_INIT, 792adfc5217SJeff Kirsher BNX2X_Q_CMD_SETUP, 793adfc5217SJeff Kirsher BNX2X_Q_CMD_SETUP_TX_ONLY, 794adfc5217SJeff Kirsher BNX2X_Q_CMD_DEACTIVATE, 795adfc5217SJeff Kirsher BNX2X_Q_CMD_ACTIVATE, 796adfc5217SJeff Kirsher BNX2X_Q_CMD_UPDATE, 797adfc5217SJeff Kirsher BNX2X_Q_CMD_UPDATE_TPA, 798adfc5217SJeff Kirsher BNX2X_Q_CMD_HALT, 799adfc5217SJeff Kirsher BNX2X_Q_CMD_CFC_DEL, 800adfc5217SJeff Kirsher BNX2X_Q_CMD_TERMINATE, 801adfc5217SJeff Kirsher BNX2X_Q_CMD_EMPTY, 802adfc5217SJeff Kirsher BNX2X_Q_CMD_MAX, 803adfc5217SJeff Kirsher }; 804adfc5217SJeff Kirsher 805adfc5217SJeff Kirsher /* queue SETUP + INIT flags */ 806adfc5217SJeff Kirsher enum { 807adfc5217SJeff Kirsher BNX2X_Q_FLG_TPA, 808adfc5217SJeff Kirsher BNX2X_Q_FLG_TPA_IPV6, 809621b4d66SDmitry Kravkov BNX2X_Q_FLG_TPA_GRO, 810adfc5217SJeff Kirsher BNX2X_Q_FLG_STATS, 811adfc5217SJeff Kirsher BNX2X_Q_FLG_ZERO_STATS, 812adfc5217SJeff Kirsher BNX2X_Q_FLG_ACTIVE, 813adfc5217SJeff Kirsher BNX2X_Q_FLG_OV, 814adfc5217SJeff Kirsher BNX2X_Q_FLG_VLAN, 815adfc5217SJeff Kirsher BNX2X_Q_FLG_COS, 816adfc5217SJeff Kirsher BNX2X_Q_FLG_HC, 817adfc5217SJeff Kirsher BNX2X_Q_FLG_HC_EN, 818adfc5217SJeff Kirsher BNX2X_Q_FLG_DHC, 819adfc5217SJeff Kirsher BNX2X_Q_FLG_FCOE, 820adfc5217SJeff Kirsher BNX2X_Q_FLG_LEADING_RSS, 821adfc5217SJeff Kirsher BNX2X_Q_FLG_MCAST, 822adfc5217SJeff Kirsher BNX2X_Q_FLG_DEF_VLAN, 823adfc5217SJeff Kirsher BNX2X_Q_FLG_TX_SWITCH, 824adfc5217SJeff Kirsher BNX2X_Q_FLG_TX_SEC, 825adfc5217SJeff Kirsher BNX2X_Q_FLG_ANTI_SPOOF, 826a3348722SBarak Witkowski BNX2X_Q_FLG_SILENT_VLAN_REM, 827a3348722SBarak Witkowski BNX2X_Q_FLG_FORCE_DEFAULT_PRI 828adfc5217SJeff Kirsher }; 829adfc5217SJeff Kirsher 830adfc5217SJeff Kirsher /* Queue type options: queue type may be a compination of below. */ 831adfc5217SJeff Kirsher enum bnx2x_q_type { 832adfc5217SJeff Kirsher /** TODO: Consider moving both these flags into the init() 833adfc5217SJeff Kirsher * ramrod params. 834adfc5217SJeff Kirsher */ 835adfc5217SJeff Kirsher BNX2X_Q_TYPE_HAS_RX, 836adfc5217SJeff Kirsher BNX2X_Q_TYPE_HAS_TX, 837adfc5217SJeff Kirsher }; 838adfc5217SJeff Kirsher 839adfc5217SJeff Kirsher #define BNX2X_PRIMARY_CID_INDEX 0 8408d7b0278SAriel Elior #define BNX2X_MULTI_TX_COS_E1X 3 /* QM only */ 841adfc5217SJeff Kirsher #define BNX2X_MULTI_TX_COS_E2_E3A0 2 842adfc5217SJeff Kirsher #define BNX2X_MULTI_TX_COS_E3B0 3 8438d7b0278SAriel Elior #define BNX2X_MULTI_TX_COS 3 /* Maximum possible */ 844adfc5217SJeff Kirsher 845adfc5217SJeff Kirsher 846adfc5217SJeff Kirsher struct bnx2x_queue_init_params { 847adfc5217SJeff Kirsher struct { 848adfc5217SJeff Kirsher unsigned long flags; 849adfc5217SJeff Kirsher u16 hc_rate; 850adfc5217SJeff Kirsher u8 fw_sb_id; 851adfc5217SJeff Kirsher u8 sb_cq_index; 852adfc5217SJeff Kirsher } tx; 853adfc5217SJeff Kirsher 854adfc5217SJeff Kirsher struct { 855adfc5217SJeff Kirsher unsigned long flags; 856adfc5217SJeff Kirsher u16 hc_rate; 857adfc5217SJeff Kirsher u8 fw_sb_id; 858adfc5217SJeff Kirsher u8 sb_cq_index; 859adfc5217SJeff Kirsher } rx; 860adfc5217SJeff Kirsher 861adfc5217SJeff Kirsher /* CID context in the host memory */ 862adfc5217SJeff Kirsher struct eth_context *cxts[BNX2X_MULTI_TX_COS]; 863adfc5217SJeff Kirsher 864adfc5217SJeff Kirsher /* maximum number of cos supported by hardware */ 865adfc5217SJeff Kirsher u8 max_cos; 866adfc5217SJeff Kirsher }; 867adfc5217SJeff Kirsher 868adfc5217SJeff Kirsher struct bnx2x_queue_terminate_params { 869adfc5217SJeff Kirsher /* index within the tx_only cids of this queue object */ 870adfc5217SJeff Kirsher u8 cid_index; 871adfc5217SJeff Kirsher }; 872adfc5217SJeff Kirsher 873adfc5217SJeff Kirsher struct bnx2x_queue_cfc_del_params { 874adfc5217SJeff Kirsher /* index within the tx_only cids of this queue object */ 875adfc5217SJeff Kirsher u8 cid_index; 876adfc5217SJeff Kirsher }; 877adfc5217SJeff Kirsher 878adfc5217SJeff Kirsher struct bnx2x_queue_update_params { 879adfc5217SJeff Kirsher unsigned long update_flags; /* BNX2X_Q_UPDATE_XX bits */ 880adfc5217SJeff Kirsher u16 def_vlan; 881adfc5217SJeff Kirsher u16 silent_removal_value; 882adfc5217SJeff Kirsher u16 silent_removal_mask; 883adfc5217SJeff Kirsher /* index within the tx_only cids of this queue object */ 884adfc5217SJeff Kirsher u8 cid_index; 885adfc5217SJeff Kirsher }; 886adfc5217SJeff Kirsher 887adfc5217SJeff Kirsher struct rxq_pause_params { 888adfc5217SJeff Kirsher u16 bd_th_lo; 889adfc5217SJeff Kirsher u16 bd_th_hi; 890adfc5217SJeff Kirsher u16 rcq_th_lo; 891adfc5217SJeff Kirsher u16 rcq_th_hi; 892adfc5217SJeff Kirsher u16 sge_th_lo; /* valid iff BNX2X_Q_FLG_TPA */ 893adfc5217SJeff Kirsher u16 sge_th_hi; /* valid iff BNX2X_Q_FLG_TPA */ 894adfc5217SJeff Kirsher u16 pri_map; 895adfc5217SJeff Kirsher }; 896adfc5217SJeff Kirsher 897adfc5217SJeff Kirsher /* general */ 898adfc5217SJeff Kirsher struct bnx2x_general_setup_params { 899adfc5217SJeff Kirsher /* valid iff BNX2X_Q_FLG_STATS */ 900adfc5217SJeff Kirsher u8 stat_id; 901adfc5217SJeff Kirsher 902adfc5217SJeff Kirsher u8 spcl_id; 903adfc5217SJeff Kirsher u16 mtu; 904adfc5217SJeff Kirsher u8 cos; 905adfc5217SJeff Kirsher }; 906adfc5217SJeff Kirsher 907adfc5217SJeff Kirsher struct bnx2x_rxq_setup_params { 908adfc5217SJeff Kirsher /* dma */ 909adfc5217SJeff Kirsher dma_addr_t dscr_map; 910adfc5217SJeff Kirsher dma_addr_t sge_map; 911adfc5217SJeff Kirsher dma_addr_t rcq_map; 912adfc5217SJeff Kirsher dma_addr_t rcq_np_map; 913adfc5217SJeff Kirsher 914adfc5217SJeff Kirsher u16 drop_flags; 915adfc5217SJeff Kirsher u16 buf_sz; 916adfc5217SJeff Kirsher u8 fw_sb_id; 917adfc5217SJeff Kirsher u8 cl_qzone_id; 918adfc5217SJeff Kirsher 919adfc5217SJeff Kirsher /* valid iff BNX2X_Q_FLG_TPA */ 920adfc5217SJeff Kirsher u16 tpa_agg_sz; 921adfc5217SJeff Kirsher u16 sge_buf_sz; 922adfc5217SJeff Kirsher u8 max_sges_pkt; 923adfc5217SJeff Kirsher u8 max_tpa_queues; 924adfc5217SJeff Kirsher u8 rss_engine_id; 925adfc5217SJeff Kirsher 926259afa1fSYuval Mintz /* valid iff BNX2X_Q_FLG_MCAST */ 927259afa1fSYuval Mintz u8 mcast_engine_id; 928259afa1fSYuval Mintz 929adfc5217SJeff Kirsher u8 cache_line_log; 930adfc5217SJeff Kirsher 931adfc5217SJeff Kirsher u8 sb_cq_index; 932adfc5217SJeff Kirsher 933adfc5217SJeff Kirsher /* valid iff BXN2X_Q_FLG_SILENT_VLAN_REM */ 934adfc5217SJeff Kirsher u16 silent_removal_value; 935adfc5217SJeff Kirsher u16 silent_removal_mask; 936adfc5217SJeff Kirsher }; 937adfc5217SJeff Kirsher 938adfc5217SJeff Kirsher struct bnx2x_txq_setup_params { 939adfc5217SJeff Kirsher /* dma */ 940adfc5217SJeff Kirsher dma_addr_t dscr_map; 941adfc5217SJeff Kirsher 942adfc5217SJeff Kirsher u8 fw_sb_id; 943adfc5217SJeff Kirsher u8 sb_cq_index; 944adfc5217SJeff Kirsher u8 cos; /* valid iff BNX2X_Q_FLG_COS */ 945adfc5217SJeff Kirsher u16 traffic_type; 946adfc5217SJeff Kirsher /* equals to the leading rss client id, used for TX classification*/ 947adfc5217SJeff Kirsher u8 tss_leading_cl_id; 948adfc5217SJeff Kirsher 949adfc5217SJeff Kirsher /* valid iff BNX2X_Q_FLG_DEF_VLAN */ 950adfc5217SJeff Kirsher u16 default_vlan; 951adfc5217SJeff Kirsher }; 952adfc5217SJeff Kirsher 953adfc5217SJeff Kirsher struct bnx2x_queue_setup_params { 954adfc5217SJeff Kirsher struct bnx2x_general_setup_params gen_params; 955adfc5217SJeff Kirsher struct bnx2x_txq_setup_params txq_params; 956adfc5217SJeff Kirsher struct bnx2x_rxq_setup_params rxq_params; 957adfc5217SJeff Kirsher struct rxq_pause_params pause_params; 958adfc5217SJeff Kirsher unsigned long flags; 959adfc5217SJeff Kirsher }; 960adfc5217SJeff Kirsher 961adfc5217SJeff Kirsher struct bnx2x_queue_setup_tx_only_params { 962adfc5217SJeff Kirsher struct bnx2x_general_setup_params gen_params; 963adfc5217SJeff Kirsher struct bnx2x_txq_setup_params txq_params; 964adfc5217SJeff Kirsher unsigned long flags; 965adfc5217SJeff Kirsher /* index within the tx_only cids of this queue object */ 966adfc5217SJeff Kirsher u8 cid_index; 967adfc5217SJeff Kirsher }; 968adfc5217SJeff Kirsher 969adfc5217SJeff Kirsher struct bnx2x_queue_state_params { 970adfc5217SJeff Kirsher struct bnx2x_queue_sp_obj *q_obj; 971adfc5217SJeff Kirsher 972adfc5217SJeff Kirsher /* Current command */ 973adfc5217SJeff Kirsher enum bnx2x_queue_cmd cmd; 974adfc5217SJeff Kirsher 975adfc5217SJeff Kirsher /* may have RAMROD_COMP_WAIT set only */ 976adfc5217SJeff Kirsher unsigned long ramrod_flags; 977adfc5217SJeff Kirsher 978adfc5217SJeff Kirsher /* Params according to the current command */ 979adfc5217SJeff Kirsher union { 980adfc5217SJeff Kirsher struct bnx2x_queue_update_params update; 981adfc5217SJeff Kirsher struct bnx2x_queue_setup_params setup; 982adfc5217SJeff Kirsher struct bnx2x_queue_init_params init; 983adfc5217SJeff Kirsher struct bnx2x_queue_setup_tx_only_params tx_only; 984adfc5217SJeff Kirsher struct bnx2x_queue_terminate_params terminate; 985adfc5217SJeff Kirsher struct bnx2x_queue_cfc_del_params cfc_del; 986adfc5217SJeff Kirsher } params; 987adfc5217SJeff Kirsher }; 988adfc5217SJeff Kirsher 989a3348722SBarak Witkowski struct bnx2x_viflist_params { 990a3348722SBarak Witkowski u8 echo_res; 991a3348722SBarak Witkowski u8 func_bit_map_res; 992a3348722SBarak Witkowski }; 993a3348722SBarak Witkowski 994adfc5217SJeff Kirsher struct bnx2x_queue_sp_obj { 995adfc5217SJeff Kirsher u32 cids[BNX2X_MULTI_TX_COS]; 996adfc5217SJeff Kirsher u8 cl_id; 997adfc5217SJeff Kirsher u8 func_id; 998adfc5217SJeff Kirsher 999adfc5217SJeff Kirsher /* 1000adfc5217SJeff Kirsher * number of traffic classes supported by queue. 1001adfc5217SJeff Kirsher * The primary connection of the queue suppotrs the first traffic 1002adfc5217SJeff Kirsher * class. Any further traffic class is suppoted by a tx-only 1003adfc5217SJeff Kirsher * connection. 1004adfc5217SJeff Kirsher * 1005adfc5217SJeff Kirsher * Therefore max_cos is also a number of valid entries in the cids 1006adfc5217SJeff Kirsher * array. 1007adfc5217SJeff Kirsher */ 1008adfc5217SJeff Kirsher u8 max_cos; 1009adfc5217SJeff Kirsher u8 num_tx_only, next_tx_only; 1010adfc5217SJeff Kirsher 1011adfc5217SJeff Kirsher enum bnx2x_q_state state, next_state; 1012adfc5217SJeff Kirsher 1013adfc5217SJeff Kirsher /* bits from enum bnx2x_q_type */ 1014adfc5217SJeff Kirsher unsigned long type; 1015adfc5217SJeff Kirsher 1016adfc5217SJeff Kirsher /* BNX2X_Q_CMD_XX bits. This object implements "one 1017adfc5217SJeff Kirsher * pending" paradigm but for debug and tracing purposes it's 1018adfc5217SJeff Kirsher * more convinient to have different bits for different 1019adfc5217SJeff Kirsher * commands. 1020adfc5217SJeff Kirsher */ 1021adfc5217SJeff Kirsher unsigned long pending; 1022adfc5217SJeff Kirsher 1023adfc5217SJeff Kirsher /* Buffer to use as a ramrod data and its mapping */ 1024adfc5217SJeff Kirsher void *rdata; 1025adfc5217SJeff Kirsher dma_addr_t rdata_mapping; 1026adfc5217SJeff Kirsher 1027adfc5217SJeff Kirsher /** 1028adfc5217SJeff Kirsher * Performs one state change according to the given parameters. 1029adfc5217SJeff Kirsher * 1030adfc5217SJeff Kirsher * @return 0 in case of success and negative value otherwise. 1031adfc5217SJeff Kirsher */ 1032adfc5217SJeff Kirsher int (*send_cmd)(struct bnx2x *bp, 1033adfc5217SJeff Kirsher struct bnx2x_queue_state_params *params); 1034adfc5217SJeff Kirsher 1035adfc5217SJeff Kirsher /** 1036adfc5217SJeff Kirsher * Sets the pending bit according to the requested transition. 1037adfc5217SJeff Kirsher */ 1038adfc5217SJeff Kirsher int (*set_pending)(struct bnx2x_queue_sp_obj *o, 1039adfc5217SJeff Kirsher struct bnx2x_queue_state_params *params); 1040adfc5217SJeff Kirsher 1041adfc5217SJeff Kirsher /** 1042adfc5217SJeff Kirsher * Checks that the requested state transition is legal. 1043adfc5217SJeff Kirsher */ 1044adfc5217SJeff Kirsher int (*check_transition)(struct bnx2x *bp, 1045adfc5217SJeff Kirsher struct bnx2x_queue_sp_obj *o, 1046adfc5217SJeff Kirsher struct bnx2x_queue_state_params *params); 1047adfc5217SJeff Kirsher 1048adfc5217SJeff Kirsher /** 1049adfc5217SJeff Kirsher * Completes the pending command. 1050adfc5217SJeff Kirsher */ 1051adfc5217SJeff Kirsher int (*complete_cmd)(struct bnx2x *bp, 1052adfc5217SJeff Kirsher struct bnx2x_queue_sp_obj *o, 1053adfc5217SJeff Kirsher enum bnx2x_queue_cmd); 1054adfc5217SJeff Kirsher 1055adfc5217SJeff Kirsher int (*wait_comp)(struct bnx2x *bp, 1056adfc5217SJeff Kirsher struct bnx2x_queue_sp_obj *o, 1057adfc5217SJeff Kirsher enum bnx2x_queue_cmd cmd); 1058adfc5217SJeff Kirsher }; 1059adfc5217SJeff Kirsher 1060adfc5217SJeff Kirsher /********************** Function state update *********************************/ 1061adfc5217SJeff Kirsher /* Allowed Function states */ 1062adfc5217SJeff Kirsher enum bnx2x_func_state { 1063adfc5217SJeff Kirsher BNX2X_F_STATE_RESET, 1064adfc5217SJeff Kirsher BNX2X_F_STATE_INITIALIZED, 1065adfc5217SJeff Kirsher BNX2X_F_STATE_STARTED, 1066adfc5217SJeff Kirsher BNX2X_F_STATE_TX_STOPPED, 1067adfc5217SJeff Kirsher BNX2X_F_STATE_MAX, 1068adfc5217SJeff Kirsher }; 1069adfc5217SJeff Kirsher 1070adfc5217SJeff Kirsher /* Allowed Function commands */ 1071adfc5217SJeff Kirsher enum bnx2x_func_cmd { 1072adfc5217SJeff Kirsher BNX2X_F_CMD_HW_INIT, 1073adfc5217SJeff Kirsher BNX2X_F_CMD_START, 1074adfc5217SJeff Kirsher BNX2X_F_CMD_STOP, 1075adfc5217SJeff Kirsher BNX2X_F_CMD_HW_RESET, 1076a3348722SBarak Witkowski BNX2X_F_CMD_AFEX_UPDATE, 1077a3348722SBarak Witkowski BNX2X_F_CMD_AFEX_VIFLISTS, 1078adfc5217SJeff Kirsher BNX2X_F_CMD_TX_STOP, 1079adfc5217SJeff Kirsher BNX2X_F_CMD_TX_START, 108055c11941SMerav Sicron BNX2X_F_CMD_SWITCH_UPDATE, 1081adfc5217SJeff Kirsher BNX2X_F_CMD_MAX, 1082adfc5217SJeff Kirsher }; 1083adfc5217SJeff Kirsher 1084adfc5217SJeff Kirsher struct bnx2x_func_hw_init_params { 1085adfc5217SJeff Kirsher /* A load phase returned by MCP. 1086adfc5217SJeff Kirsher * 1087adfc5217SJeff Kirsher * May be: 1088adfc5217SJeff Kirsher * FW_MSG_CODE_DRV_LOAD_COMMON_CHIP 1089adfc5217SJeff Kirsher * FW_MSG_CODE_DRV_LOAD_COMMON 1090adfc5217SJeff Kirsher * FW_MSG_CODE_DRV_LOAD_PORT 1091adfc5217SJeff Kirsher * FW_MSG_CODE_DRV_LOAD_FUNCTION 1092adfc5217SJeff Kirsher */ 1093adfc5217SJeff Kirsher u32 load_phase; 1094adfc5217SJeff Kirsher }; 1095adfc5217SJeff Kirsher 1096adfc5217SJeff Kirsher struct bnx2x_func_hw_reset_params { 1097adfc5217SJeff Kirsher /* A load phase returned by MCP. 1098adfc5217SJeff Kirsher * 1099adfc5217SJeff Kirsher * May be: 1100adfc5217SJeff Kirsher * FW_MSG_CODE_DRV_LOAD_COMMON_CHIP 1101adfc5217SJeff Kirsher * FW_MSG_CODE_DRV_LOAD_COMMON 1102adfc5217SJeff Kirsher * FW_MSG_CODE_DRV_LOAD_PORT 1103adfc5217SJeff Kirsher * FW_MSG_CODE_DRV_LOAD_FUNCTION 1104adfc5217SJeff Kirsher */ 1105adfc5217SJeff Kirsher u32 reset_phase; 1106adfc5217SJeff Kirsher }; 1107adfc5217SJeff Kirsher 1108adfc5217SJeff Kirsher struct bnx2x_func_start_params { 1109adfc5217SJeff Kirsher /* Multi Function mode: 1110adfc5217SJeff Kirsher * - Single Function 1111adfc5217SJeff Kirsher * - Switch Dependent 1112adfc5217SJeff Kirsher * - Switch Independent 1113adfc5217SJeff Kirsher */ 1114adfc5217SJeff Kirsher u16 mf_mode; 1115adfc5217SJeff Kirsher 1116adfc5217SJeff Kirsher /* Switch Dependent mode outer VLAN tag */ 1117adfc5217SJeff Kirsher u16 sd_vlan_tag; 1118adfc5217SJeff Kirsher 1119adfc5217SJeff Kirsher /* Function cos mode */ 1120adfc5217SJeff Kirsher u8 network_cos_mode; 1121adfc5217SJeff Kirsher }; 1122adfc5217SJeff Kirsher 112355c11941SMerav Sicron struct bnx2x_func_switch_update_params { 112455c11941SMerav Sicron u8 suspend; 112555c11941SMerav Sicron }; 112655c11941SMerav Sicron 1127a3348722SBarak Witkowski struct bnx2x_func_afex_update_params { 1128a3348722SBarak Witkowski u16 vif_id; 1129a3348722SBarak Witkowski u16 afex_default_vlan; 1130a3348722SBarak Witkowski u8 allowed_priorities; 1131a3348722SBarak Witkowski }; 1132a3348722SBarak Witkowski 1133a3348722SBarak Witkowski struct bnx2x_func_afex_viflists_params { 1134a3348722SBarak Witkowski u16 vif_list_index; 1135a3348722SBarak Witkowski u8 func_bit_map; 1136a3348722SBarak Witkowski u8 afex_vif_list_command; 1137a3348722SBarak Witkowski u8 func_to_clear; 1138a3348722SBarak Witkowski }; 1139adfc5217SJeff Kirsher struct bnx2x_func_tx_start_params { 1140adfc5217SJeff Kirsher struct priority_cos traffic_type_to_priority_cos[MAX_TRAFFIC_TYPES]; 1141adfc5217SJeff Kirsher u8 dcb_enabled; 1142adfc5217SJeff Kirsher u8 dcb_version; 1143adfc5217SJeff Kirsher u8 dont_add_pri_0_en; 1144adfc5217SJeff Kirsher }; 1145adfc5217SJeff Kirsher 1146adfc5217SJeff Kirsher struct bnx2x_func_state_params { 1147adfc5217SJeff Kirsher struct bnx2x_func_sp_obj *f_obj; 1148adfc5217SJeff Kirsher 1149adfc5217SJeff Kirsher /* Current command */ 1150adfc5217SJeff Kirsher enum bnx2x_func_cmd cmd; 1151adfc5217SJeff Kirsher 1152adfc5217SJeff Kirsher /* may have RAMROD_COMP_WAIT set only */ 1153adfc5217SJeff Kirsher unsigned long ramrod_flags; 1154adfc5217SJeff Kirsher 1155adfc5217SJeff Kirsher /* Params according to the current command */ 1156adfc5217SJeff Kirsher union { 1157adfc5217SJeff Kirsher struct bnx2x_func_hw_init_params hw_init; 1158adfc5217SJeff Kirsher struct bnx2x_func_hw_reset_params hw_reset; 1159adfc5217SJeff Kirsher struct bnx2x_func_start_params start; 116055c11941SMerav Sicron struct bnx2x_func_switch_update_params switch_update; 1161a3348722SBarak Witkowski struct bnx2x_func_afex_update_params afex_update; 1162a3348722SBarak Witkowski struct bnx2x_func_afex_viflists_params afex_viflists; 1163adfc5217SJeff Kirsher struct bnx2x_func_tx_start_params tx_start; 1164adfc5217SJeff Kirsher } params; 1165adfc5217SJeff Kirsher }; 1166adfc5217SJeff Kirsher 1167adfc5217SJeff Kirsher struct bnx2x_func_sp_drv_ops { 1168adfc5217SJeff Kirsher /* Init tool + runtime initialization: 1169adfc5217SJeff Kirsher * - Common Chip 1170adfc5217SJeff Kirsher * - Common (per Path) 1171adfc5217SJeff Kirsher * - Port 1172adfc5217SJeff Kirsher * - Function phases 1173adfc5217SJeff Kirsher */ 1174adfc5217SJeff Kirsher int (*init_hw_cmn_chip)(struct bnx2x *bp); 1175adfc5217SJeff Kirsher int (*init_hw_cmn)(struct bnx2x *bp); 1176adfc5217SJeff Kirsher int (*init_hw_port)(struct bnx2x *bp); 1177adfc5217SJeff Kirsher int (*init_hw_func)(struct bnx2x *bp); 1178adfc5217SJeff Kirsher 1179adfc5217SJeff Kirsher /* Reset Function HW: Common, Port, Function phases. */ 1180adfc5217SJeff Kirsher void (*reset_hw_cmn)(struct bnx2x *bp); 1181adfc5217SJeff Kirsher void (*reset_hw_port)(struct bnx2x *bp); 1182adfc5217SJeff Kirsher void (*reset_hw_func)(struct bnx2x *bp); 1183adfc5217SJeff Kirsher 1184adfc5217SJeff Kirsher /* Init/Free GUNZIP resources */ 1185adfc5217SJeff Kirsher int (*gunzip_init)(struct bnx2x *bp); 1186adfc5217SJeff Kirsher void (*gunzip_end)(struct bnx2x *bp); 1187adfc5217SJeff Kirsher 1188adfc5217SJeff Kirsher /* Prepare/Release FW resources */ 1189adfc5217SJeff Kirsher int (*init_fw)(struct bnx2x *bp); 1190adfc5217SJeff Kirsher void (*release_fw)(struct bnx2x *bp); 1191adfc5217SJeff Kirsher }; 1192adfc5217SJeff Kirsher 1193adfc5217SJeff Kirsher struct bnx2x_func_sp_obj { 1194adfc5217SJeff Kirsher enum bnx2x_func_state state, next_state; 1195adfc5217SJeff Kirsher 1196adfc5217SJeff Kirsher /* BNX2X_FUNC_CMD_XX bits. This object implements "one 1197adfc5217SJeff Kirsher * pending" paradigm but for debug and tracing purposes it's 1198adfc5217SJeff Kirsher * more convinient to have different bits for different 1199adfc5217SJeff Kirsher * commands. 1200adfc5217SJeff Kirsher */ 1201adfc5217SJeff Kirsher unsigned long pending; 1202adfc5217SJeff Kirsher 1203adfc5217SJeff Kirsher /* Buffer to use as a ramrod data and its mapping */ 1204adfc5217SJeff Kirsher void *rdata; 1205adfc5217SJeff Kirsher dma_addr_t rdata_mapping; 1206adfc5217SJeff Kirsher 1207a3348722SBarak Witkowski /* Buffer to use as a afex ramrod data and its mapping. 1208a3348722SBarak Witkowski * This can't be same rdata as above because afex ramrod requests 1209a3348722SBarak Witkowski * can arrive to the object in parallel to other ramrod requests. 1210a3348722SBarak Witkowski */ 1211a3348722SBarak Witkowski void *afex_rdata; 1212a3348722SBarak Witkowski dma_addr_t afex_rdata_mapping; 1213a3348722SBarak Witkowski 1214adfc5217SJeff Kirsher /* this mutex validates that when pending flag is taken, the next 1215adfc5217SJeff Kirsher * ramrod to be sent will be the one set the pending bit 1216adfc5217SJeff Kirsher */ 1217adfc5217SJeff Kirsher struct mutex one_pending_mutex; 1218adfc5217SJeff Kirsher 1219adfc5217SJeff Kirsher /* Driver interface */ 1220adfc5217SJeff Kirsher struct bnx2x_func_sp_drv_ops *drv; 1221adfc5217SJeff Kirsher 1222adfc5217SJeff Kirsher /** 1223adfc5217SJeff Kirsher * Performs one state change according to the given parameters. 1224adfc5217SJeff Kirsher * 1225adfc5217SJeff Kirsher * @return 0 in case of success and negative value otherwise. 1226adfc5217SJeff Kirsher */ 1227adfc5217SJeff Kirsher int (*send_cmd)(struct bnx2x *bp, 1228adfc5217SJeff Kirsher struct bnx2x_func_state_params *params); 1229adfc5217SJeff Kirsher 1230adfc5217SJeff Kirsher /** 1231adfc5217SJeff Kirsher * Checks that the requested state transition is legal. 1232adfc5217SJeff Kirsher */ 1233adfc5217SJeff Kirsher int (*check_transition)(struct bnx2x *bp, 1234adfc5217SJeff Kirsher struct bnx2x_func_sp_obj *o, 1235adfc5217SJeff Kirsher struct bnx2x_func_state_params *params); 1236adfc5217SJeff Kirsher 1237adfc5217SJeff Kirsher /** 1238adfc5217SJeff Kirsher * Completes the pending command. 1239adfc5217SJeff Kirsher */ 1240adfc5217SJeff Kirsher int (*complete_cmd)(struct bnx2x *bp, 1241adfc5217SJeff Kirsher struct bnx2x_func_sp_obj *o, 1242adfc5217SJeff Kirsher enum bnx2x_func_cmd cmd); 1243adfc5217SJeff Kirsher 1244adfc5217SJeff Kirsher int (*wait_comp)(struct bnx2x *bp, struct bnx2x_func_sp_obj *o, 1245adfc5217SJeff Kirsher enum bnx2x_func_cmd cmd); 1246adfc5217SJeff Kirsher }; 1247adfc5217SJeff Kirsher 1248adfc5217SJeff Kirsher /********************** Interfaces ********************************************/ 1249adfc5217SJeff Kirsher /* Queueable objects set */ 1250adfc5217SJeff Kirsher union bnx2x_qable_obj { 1251adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj vlan_mac; 1252adfc5217SJeff Kirsher }; 1253adfc5217SJeff Kirsher /************** Function state update *********/ 1254adfc5217SJeff Kirsher void bnx2x_init_func_obj(struct bnx2x *bp, 1255adfc5217SJeff Kirsher struct bnx2x_func_sp_obj *obj, 1256adfc5217SJeff Kirsher void *rdata, dma_addr_t rdata_mapping, 1257a3348722SBarak Witkowski void *afex_rdata, dma_addr_t afex_rdata_mapping, 1258adfc5217SJeff Kirsher struct bnx2x_func_sp_drv_ops *drv_iface); 1259adfc5217SJeff Kirsher 1260adfc5217SJeff Kirsher int bnx2x_func_state_change(struct bnx2x *bp, 1261adfc5217SJeff Kirsher struct bnx2x_func_state_params *params); 1262adfc5217SJeff Kirsher 1263adfc5217SJeff Kirsher enum bnx2x_func_state bnx2x_func_get_state(struct bnx2x *bp, 1264adfc5217SJeff Kirsher struct bnx2x_func_sp_obj *o); 1265adfc5217SJeff Kirsher /******************* Queue State **************/ 1266adfc5217SJeff Kirsher void bnx2x_init_queue_obj(struct bnx2x *bp, 1267adfc5217SJeff Kirsher struct bnx2x_queue_sp_obj *obj, u8 cl_id, u32 *cids, 1268adfc5217SJeff Kirsher u8 cid_cnt, u8 func_id, void *rdata, 1269adfc5217SJeff Kirsher dma_addr_t rdata_mapping, unsigned long type); 1270adfc5217SJeff Kirsher 1271adfc5217SJeff Kirsher int bnx2x_queue_state_change(struct bnx2x *bp, 1272adfc5217SJeff Kirsher struct bnx2x_queue_state_params *params); 1273adfc5217SJeff Kirsher 127467c431a5SAriel Elior int bnx2x_get_q_logical_state(struct bnx2x *bp, 127567c431a5SAriel Elior struct bnx2x_queue_sp_obj *obj); 127667c431a5SAriel Elior 1277adfc5217SJeff Kirsher /********************* VLAN-MAC ****************/ 1278adfc5217SJeff Kirsher void bnx2x_init_mac_obj(struct bnx2x *bp, 1279adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *mac_obj, 1280adfc5217SJeff Kirsher u8 cl_id, u32 cid, u8 func_id, void *rdata, 1281adfc5217SJeff Kirsher dma_addr_t rdata_mapping, int state, 1282adfc5217SJeff Kirsher unsigned long *pstate, bnx2x_obj_type type, 1283adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *macs_pool); 1284adfc5217SJeff Kirsher 1285adfc5217SJeff Kirsher void bnx2x_init_vlan_obj(struct bnx2x *bp, 1286adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *vlan_obj, 1287adfc5217SJeff Kirsher u8 cl_id, u32 cid, u8 func_id, void *rdata, 1288adfc5217SJeff Kirsher dma_addr_t rdata_mapping, int state, 1289adfc5217SJeff Kirsher unsigned long *pstate, bnx2x_obj_type type, 1290adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *vlans_pool); 1291adfc5217SJeff Kirsher 1292adfc5217SJeff Kirsher void bnx2x_init_vlan_mac_obj(struct bnx2x *bp, 1293adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *vlan_mac_obj, 1294adfc5217SJeff Kirsher u8 cl_id, u32 cid, u8 func_id, void *rdata, 1295adfc5217SJeff Kirsher dma_addr_t rdata_mapping, int state, 1296adfc5217SJeff Kirsher unsigned long *pstate, bnx2x_obj_type type, 1297adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *macs_pool, 1298adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *vlans_pool); 1299adfc5217SJeff Kirsher 1300adfc5217SJeff Kirsher int bnx2x_config_vlan_mac(struct bnx2x *bp, 1301adfc5217SJeff Kirsher struct bnx2x_vlan_mac_ramrod_params *p); 1302adfc5217SJeff Kirsher 1303adfc5217SJeff Kirsher int bnx2x_vlan_mac_move(struct bnx2x *bp, 1304adfc5217SJeff Kirsher struct bnx2x_vlan_mac_ramrod_params *p, 1305adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *dest_o); 1306adfc5217SJeff Kirsher 1307adfc5217SJeff Kirsher /********************* RX MODE ****************/ 1308adfc5217SJeff Kirsher 1309adfc5217SJeff Kirsher void bnx2x_init_rx_mode_obj(struct bnx2x *bp, 1310adfc5217SJeff Kirsher struct bnx2x_rx_mode_obj *o); 1311adfc5217SJeff Kirsher 1312adfc5217SJeff Kirsher /** 13131aa8b471SBen Hutchings * bnx2x_config_rx_mode - Send and RX_MODE ramrod according to the provided parameters. 1314adfc5217SJeff Kirsher * 13151aa8b471SBen Hutchings * @p: Command parameters 1316adfc5217SJeff Kirsher * 13171aa8b471SBen Hutchings * Return: 0 - if operation was successfull and there is no pending completions, 1318adfc5217SJeff Kirsher * positive number - if there are pending completions, 1319adfc5217SJeff Kirsher * negative - if there were errors 1320adfc5217SJeff Kirsher */ 1321adfc5217SJeff Kirsher int bnx2x_config_rx_mode(struct bnx2x *bp, 1322adfc5217SJeff Kirsher struct bnx2x_rx_mode_ramrod_params *p); 1323adfc5217SJeff Kirsher 1324adfc5217SJeff Kirsher /****************** MULTICASTS ****************/ 1325adfc5217SJeff Kirsher 1326adfc5217SJeff Kirsher void bnx2x_init_mcast_obj(struct bnx2x *bp, 1327adfc5217SJeff Kirsher struct bnx2x_mcast_obj *mcast_obj, 1328adfc5217SJeff Kirsher u8 mcast_cl_id, u32 mcast_cid, u8 func_id, 1329adfc5217SJeff Kirsher u8 engine_id, void *rdata, dma_addr_t rdata_mapping, 1330adfc5217SJeff Kirsher int state, unsigned long *pstate, 1331adfc5217SJeff Kirsher bnx2x_obj_type type); 1332adfc5217SJeff Kirsher 1333adfc5217SJeff Kirsher /** 13341aa8b471SBen Hutchings * bnx2x_config_mcast - Configure multicast MACs list. 13351aa8b471SBen Hutchings * 13361aa8b471SBen Hutchings * @cmd: command to execute: BNX2X_MCAST_CMD_X 13371aa8b471SBen Hutchings * 13381aa8b471SBen Hutchings * May configure a new list 1339adfc5217SJeff Kirsher * provided in p->mcast_list (BNX2X_MCAST_CMD_ADD), clean up 1340adfc5217SJeff Kirsher * (BNX2X_MCAST_CMD_DEL) or restore (BNX2X_MCAST_CMD_RESTORE) a current 1341adfc5217SJeff Kirsher * configuration, continue to execute the pending commands 1342adfc5217SJeff Kirsher * (BNX2X_MCAST_CMD_CONT). 1343adfc5217SJeff Kirsher * 1344adfc5217SJeff Kirsher * If previous command is still pending or if number of MACs to 1345adfc5217SJeff Kirsher * configure is more that maximum number of MACs in one command, 1346adfc5217SJeff Kirsher * the current command will be enqueued to the tail of the 1347adfc5217SJeff Kirsher * pending commands list. 1348adfc5217SJeff Kirsher * 13494907cb7bSAnatol Pomozov * Return: 0 is operation was successfull and there are no pending completions, 1350adfc5217SJeff Kirsher * negative if there were errors, positive if there are pending 1351adfc5217SJeff Kirsher * completions. 1352adfc5217SJeff Kirsher */ 1353adfc5217SJeff Kirsher int bnx2x_config_mcast(struct bnx2x *bp, 135486564c3fSYuval Mintz struct bnx2x_mcast_ramrod_params *p, 135586564c3fSYuval Mintz enum bnx2x_mcast_cmd cmd); 1356adfc5217SJeff Kirsher 1357adfc5217SJeff Kirsher /****************** CREDIT POOL ****************/ 1358adfc5217SJeff Kirsher void bnx2x_init_mac_credit_pool(struct bnx2x *bp, 1359adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *p, u8 func_id, 1360adfc5217SJeff Kirsher u8 func_num); 1361adfc5217SJeff Kirsher void bnx2x_init_vlan_credit_pool(struct bnx2x *bp, 1362adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *p, u8 func_id, 1363adfc5217SJeff Kirsher u8 func_num); 1364adfc5217SJeff Kirsher 1365adfc5217SJeff Kirsher 1366adfc5217SJeff Kirsher /****************** RSS CONFIGURATION ****************/ 1367adfc5217SJeff Kirsher void bnx2x_init_rss_config_obj(struct bnx2x *bp, 1368adfc5217SJeff Kirsher struct bnx2x_rss_config_obj *rss_obj, 1369adfc5217SJeff Kirsher u8 cl_id, u32 cid, u8 func_id, u8 engine_id, 1370adfc5217SJeff Kirsher void *rdata, dma_addr_t rdata_mapping, 1371adfc5217SJeff Kirsher int state, unsigned long *pstate, 1372adfc5217SJeff Kirsher bnx2x_obj_type type); 1373adfc5217SJeff Kirsher 1374adfc5217SJeff Kirsher /** 13751aa8b471SBen Hutchings * bnx2x_config_rss - Updates RSS configuration according to provided parameters 1376adfc5217SJeff Kirsher * 13771aa8b471SBen Hutchings * Return: 0 in case of success 1378adfc5217SJeff Kirsher */ 1379adfc5217SJeff Kirsher int bnx2x_config_rss(struct bnx2x *bp, 1380adfc5217SJeff Kirsher struct bnx2x_config_rss_params *p); 1381adfc5217SJeff Kirsher 1382adfc5217SJeff Kirsher /** 13831aa8b471SBen Hutchings * bnx2x_get_rss_ind_table - Return the current ind_table configuration. 1384adfc5217SJeff Kirsher * 13851aa8b471SBen Hutchings * @ind_table: buffer to fill with the current indirection 1386adfc5217SJeff Kirsher * table content. Should be at least 1387adfc5217SJeff Kirsher * T_ETH_INDIRECTION_TABLE_SIZE bytes long. 1388adfc5217SJeff Kirsher */ 1389adfc5217SJeff Kirsher void bnx2x_get_rss_ind_table(struct bnx2x_rss_config_obj *rss_obj, 1390adfc5217SJeff Kirsher u8 *ind_table); 1391adfc5217SJeff Kirsher 1392adfc5217SJeff Kirsher #endif /* BNX2X_SP_VERBS */ 1393