1adfc5217SJeff Kirsher /* bnx2x_sp.h: Broadcom Everest network driver. 2adfc5217SJeff Kirsher * 385b26ea1SAriel Elior * Copyright (c) 2011-2012 Broadcom Corporation 4adfc5217SJeff Kirsher * 5adfc5217SJeff Kirsher * Unless you and Broadcom execute a separate written software license 6adfc5217SJeff Kirsher * agreement governing use of this software, this software is licensed to you 7adfc5217SJeff Kirsher * under the terms of the GNU General Public License version 2, available 8adfc5217SJeff Kirsher * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL"). 9adfc5217SJeff Kirsher * 10adfc5217SJeff Kirsher * Notwithstanding the above, under no circumstances may you combine this 11adfc5217SJeff Kirsher * software in any way with any other Broadcom software provided under a 12adfc5217SJeff Kirsher * license other than the GPL, without Broadcom's express prior written 13adfc5217SJeff Kirsher * consent. 14adfc5217SJeff Kirsher * 15adfc5217SJeff Kirsher * Maintained by: Eilon Greenstein <eilong@broadcom.com> 16adfc5217SJeff Kirsher * Written by: Vladislav Zolotarov 17adfc5217SJeff Kirsher * 18adfc5217SJeff Kirsher */ 19adfc5217SJeff Kirsher #ifndef BNX2X_SP_VERBS 20adfc5217SJeff Kirsher #define BNX2X_SP_VERBS 21adfc5217SJeff Kirsher 22adfc5217SJeff Kirsher struct bnx2x; 23adfc5217SJeff Kirsher struct eth_context; 24adfc5217SJeff Kirsher 25adfc5217SJeff Kirsher /* Bits representing general command's configuration */ 26adfc5217SJeff Kirsher enum { 27adfc5217SJeff Kirsher RAMROD_TX, 28adfc5217SJeff Kirsher RAMROD_RX, 29adfc5217SJeff Kirsher /* Wait until all pending commands complete */ 30adfc5217SJeff Kirsher RAMROD_COMP_WAIT, 31adfc5217SJeff Kirsher /* Don't send a ramrod, only update a registry */ 32adfc5217SJeff Kirsher RAMROD_DRV_CLR_ONLY, 33adfc5217SJeff Kirsher /* Configure HW according to the current object state */ 34adfc5217SJeff Kirsher RAMROD_RESTORE, 35adfc5217SJeff Kirsher /* Execute the next command now */ 36adfc5217SJeff Kirsher RAMROD_EXEC, 37adfc5217SJeff Kirsher /* 38adfc5217SJeff Kirsher * Don't add a new command and continue execution of posponed 39adfc5217SJeff Kirsher * commands. If not set a new command will be added to the 40adfc5217SJeff Kirsher * pending commands list. 41adfc5217SJeff Kirsher */ 42adfc5217SJeff Kirsher RAMROD_CONT, 43adfc5217SJeff Kirsher }; 44adfc5217SJeff Kirsher 45adfc5217SJeff Kirsher typedef enum { 46adfc5217SJeff Kirsher BNX2X_OBJ_TYPE_RX, 47adfc5217SJeff Kirsher BNX2X_OBJ_TYPE_TX, 48adfc5217SJeff Kirsher BNX2X_OBJ_TYPE_RX_TX, 49adfc5217SJeff Kirsher } bnx2x_obj_type; 50adfc5217SJeff Kirsher 51adfc5217SJeff Kirsher /* Filtering states */ 52adfc5217SJeff Kirsher enum { 53adfc5217SJeff Kirsher BNX2X_FILTER_MAC_PENDING, 54adfc5217SJeff Kirsher BNX2X_FILTER_VLAN_PENDING, 55adfc5217SJeff Kirsher BNX2X_FILTER_VLAN_MAC_PENDING, 56adfc5217SJeff Kirsher BNX2X_FILTER_RX_MODE_PENDING, 57adfc5217SJeff Kirsher BNX2X_FILTER_RX_MODE_SCHED, 58adfc5217SJeff Kirsher BNX2X_FILTER_ISCSI_ETH_START_SCHED, 59adfc5217SJeff Kirsher BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, 60adfc5217SJeff Kirsher BNX2X_FILTER_FCOE_ETH_START_SCHED, 61adfc5217SJeff Kirsher BNX2X_FILTER_FCOE_ETH_STOP_SCHED, 62adfc5217SJeff Kirsher BNX2X_FILTER_MCAST_PENDING, 63adfc5217SJeff Kirsher BNX2X_FILTER_MCAST_SCHED, 64adfc5217SJeff Kirsher BNX2X_FILTER_RSS_CONF_PENDING, 65adfc5217SJeff Kirsher }; 66adfc5217SJeff Kirsher 67adfc5217SJeff Kirsher struct bnx2x_raw_obj { 68adfc5217SJeff Kirsher u8 func_id; 69adfc5217SJeff Kirsher 70adfc5217SJeff Kirsher /* Queue params */ 71adfc5217SJeff Kirsher u8 cl_id; 72adfc5217SJeff Kirsher u32 cid; 73adfc5217SJeff Kirsher 74adfc5217SJeff Kirsher /* Ramrod data buffer params */ 75adfc5217SJeff Kirsher void *rdata; 76adfc5217SJeff Kirsher dma_addr_t rdata_mapping; 77adfc5217SJeff Kirsher 78adfc5217SJeff Kirsher /* Ramrod state params */ 79adfc5217SJeff Kirsher int state; /* "ramrod is pending" state bit */ 80adfc5217SJeff Kirsher unsigned long *pstate; /* pointer to state buffer */ 81adfc5217SJeff Kirsher 82adfc5217SJeff Kirsher bnx2x_obj_type obj_type; 83adfc5217SJeff Kirsher 84adfc5217SJeff Kirsher int (*wait_comp)(struct bnx2x *bp, 85adfc5217SJeff Kirsher struct bnx2x_raw_obj *o); 86adfc5217SJeff Kirsher 87adfc5217SJeff Kirsher bool (*check_pending)(struct bnx2x_raw_obj *o); 88adfc5217SJeff Kirsher void (*clear_pending)(struct bnx2x_raw_obj *o); 89adfc5217SJeff Kirsher void (*set_pending)(struct bnx2x_raw_obj *o); 90adfc5217SJeff Kirsher }; 91adfc5217SJeff Kirsher 92adfc5217SJeff Kirsher /************************* VLAN-MAC commands related parameters ***************/ 93adfc5217SJeff Kirsher struct bnx2x_mac_ramrod_data { 94adfc5217SJeff Kirsher u8 mac[ETH_ALEN]; 95adfc5217SJeff Kirsher }; 96adfc5217SJeff Kirsher 97adfc5217SJeff Kirsher struct bnx2x_vlan_ramrod_data { 98adfc5217SJeff Kirsher u16 vlan; 99adfc5217SJeff Kirsher }; 100adfc5217SJeff Kirsher 101adfc5217SJeff Kirsher struct bnx2x_vlan_mac_ramrod_data { 102adfc5217SJeff Kirsher u8 mac[ETH_ALEN]; 103adfc5217SJeff Kirsher u16 vlan; 104adfc5217SJeff Kirsher }; 105adfc5217SJeff Kirsher 106adfc5217SJeff Kirsher union bnx2x_classification_ramrod_data { 107adfc5217SJeff Kirsher struct bnx2x_mac_ramrod_data mac; 108adfc5217SJeff Kirsher struct bnx2x_vlan_ramrod_data vlan; 109adfc5217SJeff Kirsher struct bnx2x_vlan_mac_ramrod_data vlan_mac; 110adfc5217SJeff Kirsher }; 111adfc5217SJeff Kirsher 112adfc5217SJeff Kirsher /* VLAN_MAC commands */ 113adfc5217SJeff Kirsher enum bnx2x_vlan_mac_cmd { 114adfc5217SJeff Kirsher BNX2X_VLAN_MAC_ADD, 115adfc5217SJeff Kirsher BNX2X_VLAN_MAC_DEL, 116adfc5217SJeff Kirsher BNX2X_VLAN_MAC_MOVE, 117adfc5217SJeff Kirsher }; 118adfc5217SJeff Kirsher 119adfc5217SJeff Kirsher struct bnx2x_vlan_mac_data { 120adfc5217SJeff Kirsher /* Requested command: BNX2X_VLAN_MAC_XX */ 121adfc5217SJeff Kirsher enum bnx2x_vlan_mac_cmd cmd; 122adfc5217SJeff Kirsher /* 123adfc5217SJeff Kirsher * used to contain the data related vlan_mac_flags bits from 124adfc5217SJeff Kirsher * ramrod parameters. 125adfc5217SJeff Kirsher */ 126adfc5217SJeff Kirsher unsigned long vlan_mac_flags; 127adfc5217SJeff Kirsher 128adfc5217SJeff Kirsher /* Needed for MOVE command */ 129adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *target_obj; 130adfc5217SJeff Kirsher 131adfc5217SJeff Kirsher union bnx2x_classification_ramrod_data u; 132adfc5217SJeff Kirsher }; 133adfc5217SJeff Kirsher 134adfc5217SJeff Kirsher /*************************** Exe Queue obj ************************************/ 135adfc5217SJeff Kirsher union bnx2x_exe_queue_cmd_data { 136adfc5217SJeff Kirsher struct bnx2x_vlan_mac_data vlan_mac; 137adfc5217SJeff Kirsher 138adfc5217SJeff Kirsher struct { 139adfc5217SJeff Kirsher /* TODO */ 140adfc5217SJeff Kirsher } mcast; 141adfc5217SJeff Kirsher }; 142adfc5217SJeff Kirsher 143adfc5217SJeff Kirsher struct bnx2x_exeq_elem { 144adfc5217SJeff Kirsher struct list_head link; 145adfc5217SJeff Kirsher 146adfc5217SJeff Kirsher /* Length of this element in the exe_chunk. */ 147adfc5217SJeff Kirsher int cmd_len; 148adfc5217SJeff Kirsher 149adfc5217SJeff Kirsher union bnx2x_exe_queue_cmd_data cmd_data; 150adfc5217SJeff Kirsher }; 151adfc5217SJeff Kirsher 152adfc5217SJeff Kirsher union bnx2x_qable_obj; 153adfc5217SJeff Kirsher 154adfc5217SJeff Kirsher union bnx2x_exeq_comp_elem { 155adfc5217SJeff Kirsher union event_ring_elem *elem; 156adfc5217SJeff Kirsher }; 157adfc5217SJeff Kirsher 158adfc5217SJeff Kirsher struct bnx2x_exe_queue_obj; 159adfc5217SJeff Kirsher 160adfc5217SJeff Kirsher typedef int (*exe_q_validate)(struct bnx2x *bp, 161adfc5217SJeff Kirsher union bnx2x_qable_obj *o, 162adfc5217SJeff Kirsher struct bnx2x_exeq_elem *elem); 163adfc5217SJeff Kirsher 164460a25cdSYuval Mintz typedef int (*exe_q_remove)(struct bnx2x *bp, 165460a25cdSYuval Mintz union bnx2x_qable_obj *o, 166460a25cdSYuval Mintz struct bnx2x_exeq_elem *elem); 167460a25cdSYuval Mintz 168adfc5217SJeff Kirsher /** 169adfc5217SJeff Kirsher * @return positive is entry was optimized, 0 - if not, negative 170adfc5217SJeff Kirsher * in case of an error. 171adfc5217SJeff Kirsher */ 172adfc5217SJeff Kirsher typedef int (*exe_q_optimize)(struct bnx2x *bp, 173adfc5217SJeff Kirsher union bnx2x_qable_obj *o, 174adfc5217SJeff Kirsher struct bnx2x_exeq_elem *elem); 175adfc5217SJeff Kirsher typedef int (*exe_q_execute)(struct bnx2x *bp, 176adfc5217SJeff Kirsher union bnx2x_qable_obj *o, 177adfc5217SJeff Kirsher struct list_head *exe_chunk, 178adfc5217SJeff Kirsher unsigned long *ramrod_flags); 179adfc5217SJeff Kirsher typedef struct bnx2x_exeq_elem * 180adfc5217SJeff Kirsher (*exe_q_get)(struct bnx2x_exe_queue_obj *o, 181adfc5217SJeff Kirsher struct bnx2x_exeq_elem *elem); 182adfc5217SJeff Kirsher 183adfc5217SJeff Kirsher struct bnx2x_exe_queue_obj { 184adfc5217SJeff Kirsher /* 185adfc5217SJeff Kirsher * Commands pending for an execution. 186adfc5217SJeff Kirsher */ 187adfc5217SJeff Kirsher struct list_head exe_queue; 188adfc5217SJeff Kirsher 189adfc5217SJeff Kirsher /* 190adfc5217SJeff Kirsher * Commands pending for an completion. 191adfc5217SJeff Kirsher */ 192adfc5217SJeff Kirsher struct list_head pending_comp; 193adfc5217SJeff Kirsher 194adfc5217SJeff Kirsher spinlock_t lock; 195adfc5217SJeff Kirsher 196adfc5217SJeff Kirsher /* Maximum length of commands' list for one execution */ 197adfc5217SJeff Kirsher int exe_chunk_len; 198adfc5217SJeff Kirsher 199adfc5217SJeff Kirsher union bnx2x_qable_obj *owner; 200adfc5217SJeff Kirsher 201adfc5217SJeff Kirsher /****** Virtual functions ******/ 202adfc5217SJeff Kirsher /** 203adfc5217SJeff Kirsher * Called before commands execution for commands that are really 204adfc5217SJeff Kirsher * going to be executed (after 'optimize'). 205adfc5217SJeff Kirsher * 206adfc5217SJeff Kirsher * Must run under exe_queue->lock 207adfc5217SJeff Kirsher */ 208adfc5217SJeff Kirsher exe_q_validate validate; 209adfc5217SJeff Kirsher 210460a25cdSYuval Mintz /** 211460a25cdSYuval Mintz * Called before removing pending commands, cleaning allocated 212460a25cdSYuval Mintz * resources (e.g., credits from validate) 213460a25cdSYuval Mintz */ 214460a25cdSYuval Mintz exe_q_remove remove; 215adfc5217SJeff Kirsher 216adfc5217SJeff Kirsher /** 217adfc5217SJeff Kirsher * This will try to cancel the current pending commands list 218adfc5217SJeff Kirsher * considering the new command. 219adfc5217SJeff Kirsher * 220460a25cdSYuval Mintz * Returns the number of optimized commands or a negative error code 221460a25cdSYuval Mintz * 222adfc5217SJeff Kirsher * Must run under exe_queue->lock 223adfc5217SJeff Kirsher */ 224adfc5217SJeff Kirsher exe_q_optimize optimize; 225adfc5217SJeff Kirsher 226adfc5217SJeff Kirsher /** 227adfc5217SJeff Kirsher * Run the next commands chunk (owner specific). 228adfc5217SJeff Kirsher */ 229adfc5217SJeff Kirsher exe_q_execute execute; 230adfc5217SJeff Kirsher 231adfc5217SJeff Kirsher /** 232adfc5217SJeff Kirsher * Return the exe_queue element containing the specific command 233adfc5217SJeff Kirsher * if any. Otherwise return NULL. 234adfc5217SJeff Kirsher */ 235adfc5217SJeff Kirsher exe_q_get get; 236adfc5217SJeff Kirsher }; 237adfc5217SJeff Kirsher /***************** Classification verbs: Set/Del MAC/VLAN/VLAN-MAC ************/ 238adfc5217SJeff Kirsher /* 239adfc5217SJeff Kirsher * Element in the VLAN_MAC registry list having all currenty configured 240adfc5217SJeff Kirsher * rules. 241adfc5217SJeff Kirsher */ 242adfc5217SJeff Kirsher struct bnx2x_vlan_mac_registry_elem { 243adfc5217SJeff Kirsher struct list_head link; 244adfc5217SJeff Kirsher 245adfc5217SJeff Kirsher /* 246adfc5217SJeff Kirsher * Used to store the cam offset used for the mac/vlan/vlan-mac. 247adfc5217SJeff Kirsher * Relevant for 57710 and 57711 only. VLANs and MACs share the 248adfc5217SJeff Kirsher * same CAM for these chips. 249adfc5217SJeff Kirsher */ 250adfc5217SJeff Kirsher int cam_offset; 251adfc5217SJeff Kirsher 252adfc5217SJeff Kirsher /* Needed for DEL and RESTORE flows */ 253adfc5217SJeff Kirsher unsigned long vlan_mac_flags; 254adfc5217SJeff Kirsher 255adfc5217SJeff Kirsher union bnx2x_classification_ramrod_data u; 256adfc5217SJeff Kirsher }; 257adfc5217SJeff Kirsher 258adfc5217SJeff Kirsher /* Bits representing VLAN_MAC commands specific flags */ 259adfc5217SJeff Kirsher enum { 260adfc5217SJeff Kirsher BNX2X_UC_LIST_MAC, 261adfc5217SJeff Kirsher BNX2X_ETH_MAC, 262adfc5217SJeff Kirsher BNX2X_ISCSI_ETH_MAC, 263adfc5217SJeff Kirsher BNX2X_NETQ_ETH_MAC, 264adfc5217SJeff Kirsher BNX2X_DONT_CONSUME_CAM_CREDIT, 265adfc5217SJeff Kirsher BNX2X_DONT_CONSUME_CAM_CREDIT_DEST, 266adfc5217SJeff Kirsher }; 267adfc5217SJeff Kirsher 268adfc5217SJeff Kirsher struct bnx2x_vlan_mac_ramrod_params { 269adfc5217SJeff Kirsher /* Object to run the command from */ 270adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *vlan_mac_obj; 271adfc5217SJeff Kirsher 272adfc5217SJeff Kirsher /* General command flags: COMP_WAIT, etc. */ 273adfc5217SJeff Kirsher unsigned long ramrod_flags; 274adfc5217SJeff Kirsher 275adfc5217SJeff Kirsher /* Command specific configuration request */ 276adfc5217SJeff Kirsher struct bnx2x_vlan_mac_data user_req; 277adfc5217SJeff Kirsher }; 278adfc5217SJeff Kirsher 279adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj { 280adfc5217SJeff Kirsher struct bnx2x_raw_obj raw; 281adfc5217SJeff Kirsher 282adfc5217SJeff Kirsher /* Bookkeeping list: will prevent the addition of already existing 283adfc5217SJeff Kirsher * entries. 284adfc5217SJeff Kirsher */ 285adfc5217SJeff Kirsher struct list_head head; 286adfc5217SJeff Kirsher 287adfc5217SJeff Kirsher /* TODO: Add it's initialization in the init functions */ 288adfc5217SJeff Kirsher struct bnx2x_exe_queue_obj exe_queue; 289adfc5217SJeff Kirsher 290adfc5217SJeff Kirsher /* MACs credit pool */ 291adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *macs_pool; 292adfc5217SJeff Kirsher 293adfc5217SJeff Kirsher /* VLANs credit pool */ 294adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *vlans_pool; 295adfc5217SJeff Kirsher 296adfc5217SJeff Kirsher /* RAMROD command to be used */ 297adfc5217SJeff Kirsher int ramrod_cmd; 298adfc5217SJeff Kirsher 299ed5162a0SAriel Elior /* copy first n elements onto preallocated buffer 300ed5162a0SAriel Elior * 301ed5162a0SAriel Elior * @param n number of elements to get 302ed5162a0SAriel Elior * @param buf buffer preallocated by caller into which elements 303ed5162a0SAriel Elior * will be copied. Note elements are 4-byte aligned 304ed5162a0SAriel Elior * so buffer size must be able to accomodate the 305ed5162a0SAriel Elior * aligned elements. 306ed5162a0SAriel Elior * 307ed5162a0SAriel Elior * @return number of copied bytes 308ed5162a0SAriel Elior */ 309ed5162a0SAriel Elior int (*get_n_elements)(struct bnx2x *bp, struct bnx2x_vlan_mac_obj *o, 310ed5162a0SAriel Elior int n, u8 *buf); 311ed5162a0SAriel Elior 312adfc5217SJeff Kirsher /** 313adfc5217SJeff Kirsher * Checks if ADD-ramrod with the given params may be performed. 314adfc5217SJeff Kirsher * 315adfc5217SJeff Kirsher * @return zero if the element may be added 316adfc5217SJeff Kirsher */ 317adfc5217SJeff Kirsher 318adfc5217SJeff Kirsher int (*check_add)(struct bnx2x_vlan_mac_obj *o, 319adfc5217SJeff Kirsher union bnx2x_classification_ramrod_data *data); 320adfc5217SJeff Kirsher 321adfc5217SJeff Kirsher /** 322adfc5217SJeff Kirsher * Checks if DEL-ramrod with the given params may be performed. 323adfc5217SJeff Kirsher * 324adfc5217SJeff Kirsher * @return true if the element may be deleted 325adfc5217SJeff Kirsher */ 326adfc5217SJeff Kirsher struct bnx2x_vlan_mac_registry_elem * 327adfc5217SJeff Kirsher (*check_del)(struct bnx2x_vlan_mac_obj *o, 328adfc5217SJeff Kirsher union bnx2x_classification_ramrod_data *data); 329adfc5217SJeff Kirsher 330adfc5217SJeff Kirsher /** 331adfc5217SJeff Kirsher * Checks if DEL-ramrod with the given params may be performed. 332adfc5217SJeff Kirsher * 333adfc5217SJeff Kirsher * @return true if the element may be deleted 334adfc5217SJeff Kirsher */ 335adfc5217SJeff Kirsher bool (*check_move)(struct bnx2x_vlan_mac_obj *src_o, 336adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *dst_o, 337adfc5217SJeff Kirsher union bnx2x_classification_ramrod_data *data); 338adfc5217SJeff Kirsher 339adfc5217SJeff Kirsher /** 340adfc5217SJeff Kirsher * Update the relevant credit object(s) (consume/return 341adfc5217SJeff Kirsher * correspondingly). 342adfc5217SJeff Kirsher */ 343adfc5217SJeff Kirsher bool (*get_credit)(struct bnx2x_vlan_mac_obj *o); 344adfc5217SJeff Kirsher bool (*put_credit)(struct bnx2x_vlan_mac_obj *o); 345adfc5217SJeff Kirsher bool (*get_cam_offset)(struct bnx2x_vlan_mac_obj *o, int *offset); 346adfc5217SJeff Kirsher bool (*put_cam_offset)(struct bnx2x_vlan_mac_obj *o, int offset); 347adfc5217SJeff Kirsher 348adfc5217SJeff Kirsher /** 349adfc5217SJeff Kirsher * Configures one rule in the ramrod data buffer. 350adfc5217SJeff Kirsher */ 351adfc5217SJeff Kirsher void (*set_one_rule)(struct bnx2x *bp, 352adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *o, 353adfc5217SJeff Kirsher struct bnx2x_exeq_elem *elem, int rule_idx, 354adfc5217SJeff Kirsher int cam_offset); 355adfc5217SJeff Kirsher 356adfc5217SJeff Kirsher /** 357adfc5217SJeff Kirsher * Delete all configured elements having the given 358adfc5217SJeff Kirsher * vlan_mac_flags specification. Assumes no pending for 359adfc5217SJeff Kirsher * execution commands. Will schedule all all currently 360adfc5217SJeff Kirsher * configured MACs/VLANs/VLAN-MACs matching the vlan_mac_flags 361adfc5217SJeff Kirsher * specification for deletion and will use the given 362adfc5217SJeff Kirsher * ramrod_flags for the last DEL operation. 363adfc5217SJeff Kirsher * 364adfc5217SJeff Kirsher * @param bp 365adfc5217SJeff Kirsher * @param o 366adfc5217SJeff Kirsher * @param ramrod_flags RAMROD_XX flags 367adfc5217SJeff Kirsher * 368adfc5217SJeff Kirsher * @return 0 if the last operation has completed successfully 369adfc5217SJeff Kirsher * and there are no more elements left, positive value 370adfc5217SJeff Kirsher * if there are pending for completion commands, 371adfc5217SJeff Kirsher * negative value in case of failure. 372adfc5217SJeff Kirsher */ 373adfc5217SJeff Kirsher int (*delete_all)(struct bnx2x *bp, 374adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *o, 375adfc5217SJeff Kirsher unsigned long *vlan_mac_flags, 376adfc5217SJeff Kirsher unsigned long *ramrod_flags); 377adfc5217SJeff Kirsher 378adfc5217SJeff Kirsher /** 379adfc5217SJeff Kirsher * Reconfigures the next MAC/VLAN/VLAN-MAC element from the previously 380adfc5217SJeff Kirsher * configured elements list. 381adfc5217SJeff Kirsher * 382adfc5217SJeff Kirsher * @param bp 383adfc5217SJeff Kirsher * @param p Command parameters (RAMROD_COMP_WAIT bit in 384adfc5217SJeff Kirsher * ramrod_flags is only taken into an account) 385adfc5217SJeff Kirsher * @param ppos a pointer to the cooky that should be given back in the 386adfc5217SJeff Kirsher * next call to make function handle the next element. If 387adfc5217SJeff Kirsher * *ppos is set to NULL it will restart the iterator. 388adfc5217SJeff Kirsher * If returned *ppos == NULL this means that the last 389adfc5217SJeff Kirsher * element has been handled. 390adfc5217SJeff Kirsher * 391adfc5217SJeff Kirsher * @return int 392adfc5217SJeff Kirsher */ 393adfc5217SJeff Kirsher int (*restore)(struct bnx2x *bp, 394adfc5217SJeff Kirsher struct bnx2x_vlan_mac_ramrod_params *p, 395adfc5217SJeff Kirsher struct bnx2x_vlan_mac_registry_elem **ppos); 396adfc5217SJeff Kirsher 397adfc5217SJeff Kirsher /** 398adfc5217SJeff Kirsher * Should be called on a completion arival. 399adfc5217SJeff Kirsher * 400adfc5217SJeff Kirsher * @param bp 401adfc5217SJeff Kirsher * @param o 402adfc5217SJeff Kirsher * @param cqe Completion element we are handling 403adfc5217SJeff Kirsher * @param ramrod_flags if RAMROD_CONT is set the next bulk of 404adfc5217SJeff Kirsher * pending commands will be executed. 405adfc5217SJeff Kirsher * RAMROD_DRV_CLR_ONLY and RAMROD_RESTORE 406adfc5217SJeff Kirsher * may also be set if needed. 407adfc5217SJeff Kirsher * 408adfc5217SJeff Kirsher * @return 0 if there are neither pending nor waiting for 409adfc5217SJeff Kirsher * completion commands. Positive value if there are 410adfc5217SJeff Kirsher * pending for execution or for completion commands. 411adfc5217SJeff Kirsher * Negative value in case of an error (including an 412adfc5217SJeff Kirsher * error in the cqe). 413adfc5217SJeff Kirsher */ 414adfc5217SJeff Kirsher int (*complete)(struct bnx2x *bp, struct bnx2x_vlan_mac_obj *o, 415adfc5217SJeff Kirsher union event_ring_elem *cqe, 416adfc5217SJeff Kirsher unsigned long *ramrod_flags); 417adfc5217SJeff Kirsher 418adfc5217SJeff Kirsher /** 419adfc5217SJeff Kirsher * Wait for completion of all commands. Don't schedule new ones, 420adfc5217SJeff Kirsher * just wait. It assumes that the completion code will schedule 421adfc5217SJeff Kirsher * for new commands. 422adfc5217SJeff Kirsher */ 423adfc5217SJeff Kirsher int (*wait)(struct bnx2x *bp, struct bnx2x_vlan_mac_obj *o); 424adfc5217SJeff Kirsher }; 425adfc5217SJeff Kirsher 4260a52fd01SYuval Mintz enum { 4270a52fd01SYuval Mintz BNX2X_LLH_CAM_ISCSI_ETH_LINE = 0, 4280a52fd01SYuval Mintz BNX2X_LLH_CAM_ETH_LINE, 4290a52fd01SYuval Mintz BNX2X_LLH_CAM_MAX_PF_LINE = NIG_REG_LLH1_FUNC_MEM_SIZE / 2 4300a52fd01SYuval Mintz }; 4310a52fd01SYuval Mintz 4320a52fd01SYuval Mintz 433adfc5217SJeff Kirsher /** RX_MODE verbs:DROP_ALL/ACCEPT_ALL/ACCEPT_ALL_MULTI/ACCEPT_ALL_VLAN/NORMAL */ 434adfc5217SJeff Kirsher 435adfc5217SJeff Kirsher /* RX_MODE ramrod spesial flags: set in rx_mode_flags field in 436adfc5217SJeff Kirsher * a bnx2x_rx_mode_ramrod_params. 437adfc5217SJeff Kirsher */ 438adfc5217SJeff Kirsher enum { 439adfc5217SJeff Kirsher BNX2X_RX_MODE_FCOE_ETH, 440adfc5217SJeff Kirsher BNX2X_RX_MODE_ISCSI_ETH, 441adfc5217SJeff Kirsher }; 442adfc5217SJeff Kirsher 443adfc5217SJeff Kirsher enum { 444adfc5217SJeff Kirsher BNX2X_ACCEPT_UNICAST, 445adfc5217SJeff Kirsher BNX2X_ACCEPT_MULTICAST, 446adfc5217SJeff Kirsher BNX2X_ACCEPT_ALL_UNICAST, 447adfc5217SJeff Kirsher BNX2X_ACCEPT_ALL_MULTICAST, 448adfc5217SJeff Kirsher BNX2X_ACCEPT_BROADCAST, 449adfc5217SJeff Kirsher BNX2X_ACCEPT_UNMATCHED, 450adfc5217SJeff Kirsher BNX2X_ACCEPT_ANY_VLAN 451adfc5217SJeff Kirsher }; 452adfc5217SJeff Kirsher 453adfc5217SJeff Kirsher struct bnx2x_rx_mode_ramrod_params { 454adfc5217SJeff Kirsher struct bnx2x_rx_mode_obj *rx_mode_obj; 455adfc5217SJeff Kirsher unsigned long *pstate; 456adfc5217SJeff Kirsher int state; 457adfc5217SJeff Kirsher u8 cl_id; 458adfc5217SJeff Kirsher u32 cid; 459adfc5217SJeff Kirsher u8 func_id; 460adfc5217SJeff Kirsher unsigned long ramrod_flags; 461adfc5217SJeff Kirsher unsigned long rx_mode_flags; 462adfc5217SJeff Kirsher 463adfc5217SJeff Kirsher /* 464adfc5217SJeff Kirsher * rdata is either a pointer to eth_filter_rules_ramrod_data(e2) or to 465adfc5217SJeff Kirsher * a tstorm_eth_mac_filter_config (e1x). 466adfc5217SJeff Kirsher */ 467adfc5217SJeff Kirsher void *rdata; 468adfc5217SJeff Kirsher dma_addr_t rdata_mapping; 469adfc5217SJeff Kirsher 470adfc5217SJeff Kirsher /* Rx mode settings */ 471adfc5217SJeff Kirsher unsigned long rx_accept_flags; 472adfc5217SJeff Kirsher 473adfc5217SJeff Kirsher /* internal switching settings */ 474adfc5217SJeff Kirsher unsigned long tx_accept_flags; 475adfc5217SJeff Kirsher }; 476adfc5217SJeff Kirsher 477adfc5217SJeff Kirsher struct bnx2x_rx_mode_obj { 478adfc5217SJeff Kirsher int (*config_rx_mode)(struct bnx2x *bp, 479adfc5217SJeff Kirsher struct bnx2x_rx_mode_ramrod_params *p); 480adfc5217SJeff Kirsher 481adfc5217SJeff Kirsher int (*wait_comp)(struct bnx2x *bp, 482adfc5217SJeff Kirsher struct bnx2x_rx_mode_ramrod_params *p); 483adfc5217SJeff Kirsher }; 484adfc5217SJeff Kirsher 485adfc5217SJeff Kirsher /********************** Set multicast group ***********************************/ 486adfc5217SJeff Kirsher 487adfc5217SJeff Kirsher struct bnx2x_mcast_list_elem { 488adfc5217SJeff Kirsher struct list_head link; 489adfc5217SJeff Kirsher u8 *mac; 490adfc5217SJeff Kirsher }; 491adfc5217SJeff Kirsher 492adfc5217SJeff Kirsher union bnx2x_mcast_config_data { 493adfc5217SJeff Kirsher u8 *mac; 494adfc5217SJeff Kirsher u8 bin; /* used in a RESTORE flow */ 495adfc5217SJeff Kirsher }; 496adfc5217SJeff Kirsher 497adfc5217SJeff Kirsher struct bnx2x_mcast_ramrod_params { 498adfc5217SJeff Kirsher struct bnx2x_mcast_obj *mcast_obj; 499adfc5217SJeff Kirsher 500adfc5217SJeff Kirsher /* Relevant options are RAMROD_COMP_WAIT and RAMROD_DRV_CLR_ONLY */ 501adfc5217SJeff Kirsher unsigned long ramrod_flags; 502adfc5217SJeff Kirsher 503adfc5217SJeff Kirsher struct list_head mcast_list; /* list of struct bnx2x_mcast_list_elem */ 504adfc5217SJeff Kirsher /** TODO: 505adfc5217SJeff Kirsher * - rename it to macs_num. 506adfc5217SJeff Kirsher * - Add a new command type for handling pending commands 507adfc5217SJeff Kirsher * (remove "zero semantics"). 508adfc5217SJeff Kirsher * 509adfc5217SJeff Kirsher * Length of mcast_list. If zero and ADD_CONT command - post 510adfc5217SJeff Kirsher * pending commands. 511adfc5217SJeff Kirsher */ 512adfc5217SJeff Kirsher int mcast_list_len; 513adfc5217SJeff Kirsher }; 514adfc5217SJeff Kirsher 515adfc5217SJeff Kirsher enum { 516adfc5217SJeff Kirsher BNX2X_MCAST_CMD_ADD, 517adfc5217SJeff Kirsher BNX2X_MCAST_CMD_CONT, 518adfc5217SJeff Kirsher BNX2X_MCAST_CMD_DEL, 519adfc5217SJeff Kirsher BNX2X_MCAST_CMD_RESTORE, 520adfc5217SJeff Kirsher }; 521adfc5217SJeff Kirsher 522adfc5217SJeff Kirsher struct bnx2x_mcast_obj { 523adfc5217SJeff Kirsher struct bnx2x_raw_obj raw; 524adfc5217SJeff Kirsher 525adfc5217SJeff Kirsher union { 526adfc5217SJeff Kirsher struct { 527adfc5217SJeff Kirsher #define BNX2X_MCAST_BINS_NUM 256 528adfc5217SJeff Kirsher #define BNX2X_MCAST_VEC_SZ (BNX2X_MCAST_BINS_NUM / 64) 529adfc5217SJeff Kirsher u64 vec[BNX2X_MCAST_VEC_SZ]; 530adfc5217SJeff Kirsher 531adfc5217SJeff Kirsher /** Number of BINs to clear. Should be updated 532adfc5217SJeff Kirsher * immediately when a command arrives in order to 533adfc5217SJeff Kirsher * properly create DEL commands. 534adfc5217SJeff Kirsher */ 535adfc5217SJeff Kirsher int num_bins_set; 536adfc5217SJeff Kirsher } aprox_match; 537adfc5217SJeff Kirsher 538adfc5217SJeff Kirsher struct { 539adfc5217SJeff Kirsher struct list_head macs; 540adfc5217SJeff Kirsher int num_macs_set; 541adfc5217SJeff Kirsher } exact_match; 542adfc5217SJeff Kirsher } registry; 543adfc5217SJeff Kirsher 544adfc5217SJeff Kirsher /* Pending commands */ 545adfc5217SJeff Kirsher struct list_head pending_cmds_head; 546adfc5217SJeff Kirsher 547adfc5217SJeff Kirsher /* A state that is set in raw.pstate, when there are pending commands */ 548adfc5217SJeff Kirsher int sched_state; 549adfc5217SJeff Kirsher 550adfc5217SJeff Kirsher /* Maximal number of mcast MACs configured in one command */ 551adfc5217SJeff Kirsher int max_cmd_len; 552adfc5217SJeff Kirsher 553adfc5217SJeff Kirsher /* Total number of currently pending MACs to configure: both 554adfc5217SJeff Kirsher * in the pending commands list and in the current command. 555adfc5217SJeff Kirsher */ 556adfc5217SJeff Kirsher int total_pending_num; 557adfc5217SJeff Kirsher 558adfc5217SJeff Kirsher u8 engine_id; 559adfc5217SJeff Kirsher 560adfc5217SJeff Kirsher /** 561adfc5217SJeff Kirsher * @param cmd command to execute (BNX2X_MCAST_CMD_X, see above) 562adfc5217SJeff Kirsher */ 563adfc5217SJeff Kirsher int (*config_mcast)(struct bnx2x *bp, 564adfc5217SJeff Kirsher struct bnx2x_mcast_ramrod_params *p, int cmd); 565adfc5217SJeff Kirsher 566adfc5217SJeff Kirsher /** 567adfc5217SJeff Kirsher * Fills the ramrod data during the RESTORE flow. 568adfc5217SJeff Kirsher * 569adfc5217SJeff Kirsher * @param bp 570adfc5217SJeff Kirsher * @param o 571adfc5217SJeff Kirsher * @param start_idx Registry index to start from 572adfc5217SJeff Kirsher * @param rdata_idx Index in the ramrod data to start from 573adfc5217SJeff Kirsher * 574adfc5217SJeff Kirsher * @return -1 if we handled the whole registry or index of the last 575adfc5217SJeff Kirsher * handled registry element. 576adfc5217SJeff Kirsher */ 577adfc5217SJeff Kirsher int (*hdl_restore)(struct bnx2x *bp, struct bnx2x_mcast_obj *o, 578adfc5217SJeff Kirsher int start_bin, int *rdata_idx); 579adfc5217SJeff Kirsher 580adfc5217SJeff Kirsher int (*enqueue_cmd)(struct bnx2x *bp, struct bnx2x_mcast_obj *o, 581adfc5217SJeff Kirsher struct bnx2x_mcast_ramrod_params *p, int cmd); 582adfc5217SJeff Kirsher 583adfc5217SJeff Kirsher void (*set_one_rule)(struct bnx2x *bp, 584adfc5217SJeff Kirsher struct bnx2x_mcast_obj *o, int idx, 585adfc5217SJeff Kirsher union bnx2x_mcast_config_data *cfg_data, int cmd); 586adfc5217SJeff Kirsher 587adfc5217SJeff Kirsher /** Checks if there are more mcast MACs to be set or a previous 588adfc5217SJeff Kirsher * command is still pending. 589adfc5217SJeff Kirsher */ 590adfc5217SJeff Kirsher bool (*check_pending)(struct bnx2x_mcast_obj *o); 591adfc5217SJeff Kirsher 592adfc5217SJeff Kirsher /** 593adfc5217SJeff Kirsher * Set/Clear/Check SCHEDULED state of the object 594adfc5217SJeff Kirsher */ 595adfc5217SJeff Kirsher void (*set_sched)(struct bnx2x_mcast_obj *o); 596adfc5217SJeff Kirsher void (*clear_sched)(struct bnx2x_mcast_obj *o); 597adfc5217SJeff Kirsher bool (*check_sched)(struct bnx2x_mcast_obj *o); 598adfc5217SJeff Kirsher 599adfc5217SJeff Kirsher /* Wait until all pending commands complete */ 600adfc5217SJeff Kirsher int (*wait_comp)(struct bnx2x *bp, struct bnx2x_mcast_obj *o); 601adfc5217SJeff Kirsher 602adfc5217SJeff Kirsher /** 603adfc5217SJeff Kirsher * Handle the internal object counters needed for proper 604adfc5217SJeff Kirsher * commands handling. Checks that the provided parameters are 605adfc5217SJeff Kirsher * feasible. 606adfc5217SJeff Kirsher */ 607adfc5217SJeff Kirsher int (*validate)(struct bnx2x *bp, 608adfc5217SJeff Kirsher struct bnx2x_mcast_ramrod_params *p, int cmd); 609adfc5217SJeff Kirsher 610adfc5217SJeff Kirsher /** 611adfc5217SJeff Kirsher * Restore the values of internal counters in case of a failure. 612adfc5217SJeff Kirsher */ 613adfc5217SJeff Kirsher void (*revert)(struct bnx2x *bp, 614adfc5217SJeff Kirsher struct bnx2x_mcast_ramrod_params *p, 615adfc5217SJeff Kirsher int old_num_bins); 616adfc5217SJeff Kirsher 617adfc5217SJeff Kirsher int (*get_registry_size)(struct bnx2x_mcast_obj *o); 618adfc5217SJeff Kirsher void (*set_registry_size)(struct bnx2x_mcast_obj *o, int n); 619adfc5217SJeff Kirsher }; 620adfc5217SJeff Kirsher 621adfc5217SJeff Kirsher /*************************** Credit handling **********************************/ 622adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj { 623adfc5217SJeff Kirsher 624adfc5217SJeff Kirsher /* Current amount of credit in the pool */ 625adfc5217SJeff Kirsher atomic_t credit; 626adfc5217SJeff Kirsher 627adfc5217SJeff Kirsher /* Maximum allowed credit. put() will check against it. */ 628adfc5217SJeff Kirsher int pool_sz; 629adfc5217SJeff Kirsher 630adfc5217SJeff Kirsher /* 631adfc5217SJeff Kirsher * Allocate a pool table statically. 632adfc5217SJeff Kirsher * 633adfc5217SJeff Kirsher * Currently the mamimum allowed size is MAX_MAC_CREDIT_E2(272) 634adfc5217SJeff Kirsher * 635adfc5217SJeff Kirsher * The set bit in the table will mean that the entry is available. 636adfc5217SJeff Kirsher */ 637adfc5217SJeff Kirsher #define BNX2X_POOL_VEC_SIZE (MAX_MAC_CREDIT_E2 / 64) 638adfc5217SJeff Kirsher u64 pool_mirror[BNX2X_POOL_VEC_SIZE]; 639adfc5217SJeff Kirsher 640adfc5217SJeff Kirsher /* Base pool offset (initialized differently */ 641adfc5217SJeff Kirsher int base_pool_offset; 642adfc5217SJeff Kirsher 643adfc5217SJeff Kirsher /** 644adfc5217SJeff Kirsher * Get the next free pool entry. 645adfc5217SJeff Kirsher * 646adfc5217SJeff Kirsher * @return true if there was a free entry in the pool 647adfc5217SJeff Kirsher */ 648adfc5217SJeff Kirsher bool (*get_entry)(struct bnx2x_credit_pool_obj *o, int *entry); 649adfc5217SJeff Kirsher 650adfc5217SJeff Kirsher /** 651adfc5217SJeff Kirsher * Return the entry back to the pool. 652adfc5217SJeff Kirsher * 653adfc5217SJeff Kirsher * @return true if entry is legal and has been successfully 654adfc5217SJeff Kirsher * returned to the pool. 655adfc5217SJeff Kirsher */ 656adfc5217SJeff Kirsher bool (*put_entry)(struct bnx2x_credit_pool_obj *o, int entry); 657adfc5217SJeff Kirsher 658adfc5217SJeff Kirsher /** 659adfc5217SJeff Kirsher * Get the requested amount of credit from the pool. 660adfc5217SJeff Kirsher * 661adfc5217SJeff Kirsher * @param cnt Amount of requested credit 662adfc5217SJeff Kirsher * @return true if the operation is successful 663adfc5217SJeff Kirsher */ 664adfc5217SJeff Kirsher bool (*get)(struct bnx2x_credit_pool_obj *o, int cnt); 665adfc5217SJeff Kirsher 666adfc5217SJeff Kirsher /** 667adfc5217SJeff Kirsher * Returns the credit to the pool. 668adfc5217SJeff Kirsher * 669adfc5217SJeff Kirsher * @param cnt Amount of credit to return 670adfc5217SJeff Kirsher * @return true if the operation is successful 671adfc5217SJeff Kirsher */ 672adfc5217SJeff Kirsher bool (*put)(struct bnx2x_credit_pool_obj *o, int cnt); 673adfc5217SJeff Kirsher 674adfc5217SJeff Kirsher /** 675adfc5217SJeff Kirsher * Reads the current amount of credit. 676adfc5217SJeff Kirsher */ 677adfc5217SJeff Kirsher int (*check)(struct bnx2x_credit_pool_obj *o); 678adfc5217SJeff Kirsher }; 679adfc5217SJeff Kirsher 680adfc5217SJeff Kirsher /*************************** RSS configuration ********************************/ 681adfc5217SJeff Kirsher enum { 682adfc5217SJeff Kirsher /* RSS_MODE bits are mutually exclusive */ 683adfc5217SJeff Kirsher BNX2X_RSS_MODE_DISABLED, 684adfc5217SJeff Kirsher BNX2X_RSS_MODE_REGULAR, 685adfc5217SJeff Kirsher BNX2X_RSS_MODE_VLAN_PRI, 686adfc5217SJeff Kirsher BNX2X_RSS_MODE_E1HOV_PRI, 687adfc5217SJeff Kirsher BNX2X_RSS_MODE_IP_DSCP, 688adfc5217SJeff Kirsher 689adfc5217SJeff Kirsher BNX2X_RSS_SET_SRCH, /* Setup searcher, E1x specific flag */ 690adfc5217SJeff Kirsher 691adfc5217SJeff Kirsher BNX2X_RSS_IPV4, 692adfc5217SJeff Kirsher BNX2X_RSS_IPV4_TCP, 693adfc5217SJeff Kirsher BNX2X_RSS_IPV6, 694adfc5217SJeff Kirsher BNX2X_RSS_IPV6_TCP, 695adfc5217SJeff Kirsher }; 696adfc5217SJeff Kirsher 697adfc5217SJeff Kirsher struct bnx2x_config_rss_params { 698adfc5217SJeff Kirsher struct bnx2x_rss_config_obj *rss_obj; 699adfc5217SJeff Kirsher 700adfc5217SJeff Kirsher /* may have RAMROD_COMP_WAIT set only */ 701adfc5217SJeff Kirsher unsigned long ramrod_flags; 702adfc5217SJeff Kirsher 703adfc5217SJeff Kirsher /* BNX2X_RSS_X bits */ 704adfc5217SJeff Kirsher unsigned long rss_flags; 705adfc5217SJeff Kirsher 706adfc5217SJeff Kirsher /* Number hash bits to take into an account */ 707adfc5217SJeff Kirsher u8 rss_result_mask; 708adfc5217SJeff Kirsher 709adfc5217SJeff Kirsher /* Indirection table */ 710adfc5217SJeff Kirsher u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE]; 711adfc5217SJeff Kirsher 712adfc5217SJeff Kirsher /* RSS hash values */ 713adfc5217SJeff Kirsher u32 rss_key[10]; 714adfc5217SJeff Kirsher 715adfc5217SJeff Kirsher /* valid only iff BNX2X_RSS_UPDATE_TOE is set */ 716adfc5217SJeff Kirsher u16 toe_rss_bitmap; 717adfc5217SJeff Kirsher }; 718adfc5217SJeff Kirsher 719adfc5217SJeff Kirsher struct bnx2x_rss_config_obj { 720adfc5217SJeff Kirsher struct bnx2x_raw_obj raw; 721adfc5217SJeff Kirsher 722adfc5217SJeff Kirsher /* RSS engine to use */ 723adfc5217SJeff Kirsher u8 engine_id; 724adfc5217SJeff Kirsher 725adfc5217SJeff Kirsher /* Last configured indirection table */ 726adfc5217SJeff Kirsher u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE]; 727adfc5217SJeff Kirsher 728adfc5217SJeff Kirsher int (*config_rss)(struct bnx2x *bp, 729adfc5217SJeff Kirsher struct bnx2x_config_rss_params *p); 730adfc5217SJeff Kirsher }; 731adfc5217SJeff Kirsher 732adfc5217SJeff Kirsher /*********************** Queue state update ***********************************/ 733adfc5217SJeff Kirsher 734adfc5217SJeff Kirsher /* UPDATE command options */ 735adfc5217SJeff Kirsher enum { 736adfc5217SJeff Kirsher BNX2X_Q_UPDATE_IN_VLAN_REM, 737adfc5217SJeff Kirsher BNX2X_Q_UPDATE_IN_VLAN_REM_CHNG, 738adfc5217SJeff Kirsher BNX2X_Q_UPDATE_OUT_VLAN_REM, 739adfc5217SJeff Kirsher BNX2X_Q_UPDATE_OUT_VLAN_REM_CHNG, 740adfc5217SJeff Kirsher BNX2X_Q_UPDATE_ANTI_SPOOF, 741adfc5217SJeff Kirsher BNX2X_Q_UPDATE_ANTI_SPOOF_CHNG, 742adfc5217SJeff Kirsher BNX2X_Q_UPDATE_ACTIVATE, 743adfc5217SJeff Kirsher BNX2X_Q_UPDATE_ACTIVATE_CHNG, 744adfc5217SJeff Kirsher BNX2X_Q_UPDATE_DEF_VLAN_EN, 745adfc5217SJeff Kirsher BNX2X_Q_UPDATE_DEF_VLAN_EN_CHNG, 746adfc5217SJeff Kirsher BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG, 747adfc5217SJeff Kirsher BNX2X_Q_UPDATE_SILENT_VLAN_REM 748adfc5217SJeff Kirsher }; 749adfc5217SJeff Kirsher 750adfc5217SJeff Kirsher /* Allowed Queue states */ 751adfc5217SJeff Kirsher enum bnx2x_q_state { 752adfc5217SJeff Kirsher BNX2X_Q_STATE_RESET, 753adfc5217SJeff Kirsher BNX2X_Q_STATE_INITIALIZED, 754adfc5217SJeff Kirsher BNX2X_Q_STATE_ACTIVE, 755adfc5217SJeff Kirsher BNX2X_Q_STATE_MULTI_COS, 756adfc5217SJeff Kirsher BNX2X_Q_STATE_MCOS_TERMINATED, 757adfc5217SJeff Kirsher BNX2X_Q_STATE_INACTIVE, 758adfc5217SJeff Kirsher BNX2X_Q_STATE_STOPPED, 759adfc5217SJeff Kirsher BNX2X_Q_STATE_TERMINATED, 760adfc5217SJeff Kirsher BNX2X_Q_STATE_FLRED, 761adfc5217SJeff Kirsher BNX2X_Q_STATE_MAX, 762adfc5217SJeff Kirsher }; 763adfc5217SJeff Kirsher 764adfc5217SJeff Kirsher /* Allowed commands */ 765adfc5217SJeff Kirsher enum bnx2x_queue_cmd { 766adfc5217SJeff Kirsher BNX2X_Q_CMD_INIT, 767adfc5217SJeff Kirsher BNX2X_Q_CMD_SETUP, 768adfc5217SJeff Kirsher BNX2X_Q_CMD_SETUP_TX_ONLY, 769adfc5217SJeff Kirsher BNX2X_Q_CMD_DEACTIVATE, 770adfc5217SJeff Kirsher BNX2X_Q_CMD_ACTIVATE, 771adfc5217SJeff Kirsher BNX2X_Q_CMD_UPDATE, 772adfc5217SJeff Kirsher BNX2X_Q_CMD_UPDATE_TPA, 773adfc5217SJeff Kirsher BNX2X_Q_CMD_HALT, 774adfc5217SJeff Kirsher BNX2X_Q_CMD_CFC_DEL, 775adfc5217SJeff Kirsher BNX2X_Q_CMD_TERMINATE, 776adfc5217SJeff Kirsher BNX2X_Q_CMD_EMPTY, 777adfc5217SJeff Kirsher BNX2X_Q_CMD_MAX, 778adfc5217SJeff Kirsher }; 779adfc5217SJeff Kirsher 780adfc5217SJeff Kirsher /* queue SETUP + INIT flags */ 781adfc5217SJeff Kirsher enum { 782adfc5217SJeff Kirsher BNX2X_Q_FLG_TPA, 783adfc5217SJeff Kirsher BNX2X_Q_FLG_TPA_IPV6, 784621b4d66SDmitry Kravkov BNX2X_Q_FLG_TPA_GRO, 785adfc5217SJeff Kirsher BNX2X_Q_FLG_STATS, 786adfc5217SJeff Kirsher BNX2X_Q_FLG_ZERO_STATS, 787adfc5217SJeff Kirsher BNX2X_Q_FLG_ACTIVE, 788adfc5217SJeff Kirsher BNX2X_Q_FLG_OV, 789adfc5217SJeff Kirsher BNX2X_Q_FLG_VLAN, 790adfc5217SJeff Kirsher BNX2X_Q_FLG_COS, 791adfc5217SJeff Kirsher BNX2X_Q_FLG_HC, 792adfc5217SJeff Kirsher BNX2X_Q_FLG_HC_EN, 793adfc5217SJeff Kirsher BNX2X_Q_FLG_DHC, 794adfc5217SJeff Kirsher BNX2X_Q_FLG_FCOE, 795adfc5217SJeff Kirsher BNX2X_Q_FLG_LEADING_RSS, 796adfc5217SJeff Kirsher BNX2X_Q_FLG_MCAST, 797adfc5217SJeff Kirsher BNX2X_Q_FLG_DEF_VLAN, 798adfc5217SJeff Kirsher BNX2X_Q_FLG_TX_SWITCH, 799adfc5217SJeff Kirsher BNX2X_Q_FLG_TX_SEC, 800adfc5217SJeff Kirsher BNX2X_Q_FLG_ANTI_SPOOF, 801adfc5217SJeff Kirsher BNX2X_Q_FLG_SILENT_VLAN_REM 802adfc5217SJeff Kirsher }; 803adfc5217SJeff Kirsher 804adfc5217SJeff Kirsher /* Queue type options: queue type may be a compination of below. */ 805adfc5217SJeff Kirsher enum bnx2x_q_type { 806adfc5217SJeff Kirsher /** TODO: Consider moving both these flags into the init() 807adfc5217SJeff Kirsher * ramrod params. 808adfc5217SJeff Kirsher */ 809adfc5217SJeff Kirsher BNX2X_Q_TYPE_HAS_RX, 810adfc5217SJeff Kirsher BNX2X_Q_TYPE_HAS_TX, 811adfc5217SJeff Kirsher }; 812adfc5217SJeff Kirsher 813adfc5217SJeff Kirsher #define BNX2X_PRIMARY_CID_INDEX 0 8148d7b0278SAriel Elior #define BNX2X_MULTI_TX_COS_E1X 3 /* QM only */ 815adfc5217SJeff Kirsher #define BNX2X_MULTI_TX_COS_E2_E3A0 2 816adfc5217SJeff Kirsher #define BNX2X_MULTI_TX_COS_E3B0 3 8178d7b0278SAriel Elior #define BNX2X_MULTI_TX_COS 3 /* Maximum possible */ 818adfc5217SJeff Kirsher 819adfc5217SJeff Kirsher 820adfc5217SJeff Kirsher struct bnx2x_queue_init_params { 821adfc5217SJeff Kirsher struct { 822adfc5217SJeff Kirsher unsigned long flags; 823adfc5217SJeff Kirsher u16 hc_rate; 824adfc5217SJeff Kirsher u8 fw_sb_id; 825adfc5217SJeff Kirsher u8 sb_cq_index; 826adfc5217SJeff Kirsher } tx; 827adfc5217SJeff Kirsher 828adfc5217SJeff Kirsher struct { 829adfc5217SJeff Kirsher unsigned long flags; 830adfc5217SJeff Kirsher u16 hc_rate; 831adfc5217SJeff Kirsher u8 fw_sb_id; 832adfc5217SJeff Kirsher u8 sb_cq_index; 833adfc5217SJeff Kirsher } rx; 834adfc5217SJeff Kirsher 835adfc5217SJeff Kirsher /* CID context in the host memory */ 836adfc5217SJeff Kirsher struct eth_context *cxts[BNX2X_MULTI_TX_COS]; 837adfc5217SJeff Kirsher 838adfc5217SJeff Kirsher /* maximum number of cos supported by hardware */ 839adfc5217SJeff Kirsher u8 max_cos; 840adfc5217SJeff Kirsher }; 841adfc5217SJeff Kirsher 842adfc5217SJeff Kirsher struct bnx2x_queue_terminate_params { 843adfc5217SJeff Kirsher /* index within the tx_only cids of this queue object */ 844adfc5217SJeff Kirsher u8 cid_index; 845adfc5217SJeff Kirsher }; 846adfc5217SJeff Kirsher 847adfc5217SJeff Kirsher struct bnx2x_queue_cfc_del_params { 848adfc5217SJeff Kirsher /* index within the tx_only cids of this queue object */ 849adfc5217SJeff Kirsher u8 cid_index; 850adfc5217SJeff Kirsher }; 851adfc5217SJeff Kirsher 852adfc5217SJeff Kirsher struct bnx2x_queue_update_params { 853adfc5217SJeff Kirsher unsigned long update_flags; /* BNX2X_Q_UPDATE_XX bits */ 854adfc5217SJeff Kirsher u16 def_vlan; 855adfc5217SJeff Kirsher u16 silent_removal_value; 856adfc5217SJeff Kirsher u16 silent_removal_mask; 857adfc5217SJeff Kirsher /* index within the tx_only cids of this queue object */ 858adfc5217SJeff Kirsher u8 cid_index; 859adfc5217SJeff Kirsher }; 860adfc5217SJeff Kirsher 861adfc5217SJeff Kirsher struct rxq_pause_params { 862adfc5217SJeff Kirsher u16 bd_th_lo; 863adfc5217SJeff Kirsher u16 bd_th_hi; 864adfc5217SJeff Kirsher u16 rcq_th_lo; 865adfc5217SJeff Kirsher u16 rcq_th_hi; 866adfc5217SJeff Kirsher u16 sge_th_lo; /* valid iff BNX2X_Q_FLG_TPA */ 867adfc5217SJeff Kirsher u16 sge_th_hi; /* valid iff BNX2X_Q_FLG_TPA */ 868adfc5217SJeff Kirsher u16 pri_map; 869adfc5217SJeff Kirsher }; 870adfc5217SJeff Kirsher 871adfc5217SJeff Kirsher /* general */ 872adfc5217SJeff Kirsher struct bnx2x_general_setup_params { 873adfc5217SJeff Kirsher /* valid iff BNX2X_Q_FLG_STATS */ 874adfc5217SJeff Kirsher u8 stat_id; 875adfc5217SJeff Kirsher 876adfc5217SJeff Kirsher u8 spcl_id; 877adfc5217SJeff Kirsher u16 mtu; 878adfc5217SJeff Kirsher u8 cos; 879adfc5217SJeff Kirsher }; 880adfc5217SJeff Kirsher 881adfc5217SJeff Kirsher struct bnx2x_rxq_setup_params { 882adfc5217SJeff Kirsher /* dma */ 883adfc5217SJeff Kirsher dma_addr_t dscr_map; 884adfc5217SJeff Kirsher dma_addr_t sge_map; 885adfc5217SJeff Kirsher dma_addr_t rcq_map; 886adfc5217SJeff Kirsher dma_addr_t rcq_np_map; 887adfc5217SJeff Kirsher 888adfc5217SJeff Kirsher u16 drop_flags; 889adfc5217SJeff Kirsher u16 buf_sz; 890adfc5217SJeff Kirsher u8 fw_sb_id; 891adfc5217SJeff Kirsher u8 cl_qzone_id; 892adfc5217SJeff Kirsher 893adfc5217SJeff Kirsher /* valid iff BNX2X_Q_FLG_TPA */ 894adfc5217SJeff Kirsher u16 tpa_agg_sz; 895adfc5217SJeff Kirsher u16 sge_buf_sz; 896adfc5217SJeff Kirsher u8 max_sges_pkt; 897adfc5217SJeff Kirsher u8 max_tpa_queues; 898adfc5217SJeff Kirsher u8 rss_engine_id; 899adfc5217SJeff Kirsher 900259afa1fSYuval Mintz /* valid iff BNX2X_Q_FLG_MCAST */ 901259afa1fSYuval Mintz u8 mcast_engine_id; 902259afa1fSYuval Mintz 903adfc5217SJeff Kirsher u8 cache_line_log; 904adfc5217SJeff Kirsher 905adfc5217SJeff Kirsher u8 sb_cq_index; 906adfc5217SJeff Kirsher 907adfc5217SJeff Kirsher /* valid iff BXN2X_Q_FLG_SILENT_VLAN_REM */ 908adfc5217SJeff Kirsher u16 silent_removal_value; 909adfc5217SJeff Kirsher u16 silent_removal_mask; 910adfc5217SJeff Kirsher }; 911adfc5217SJeff Kirsher 912adfc5217SJeff Kirsher struct bnx2x_txq_setup_params { 913adfc5217SJeff Kirsher /* dma */ 914adfc5217SJeff Kirsher dma_addr_t dscr_map; 915adfc5217SJeff Kirsher 916adfc5217SJeff Kirsher u8 fw_sb_id; 917adfc5217SJeff Kirsher u8 sb_cq_index; 918adfc5217SJeff Kirsher u8 cos; /* valid iff BNX2X_Q_FLG_COS */ 919adfc5217SJeff Kirsher u16 traffic_type; 920adfc5217SJeff Kirsher /* equals to the leading rss client id, used for TX classification*/ 921adfc5217SJeff Kirsher u8 tss_leading_cl_id; 922adfc5217SJeff Kirsher 923adfc5217SJeff Kirsher /* valid iff BNX2X_Q_FLG_DEF_VLAN */ 924adfc5217SJeff Kirsher u16 default_vlan; 925adfc5217SJeff Kirsher }; 926adfc5217SJeff Kirsher 927adfc5217SJeff Kirsher struct bnx2x_queue_setup_params { 928adfc5217SJeff Kirsher struct bnx2x_general_setup_params gen_params; 929adfc5217SJeff Kirsher struct bnx2x_txq_setup_params txq_params; 930adfc5217SJeff Kirsher struct bnx2x_rxq_setup_params rxq_params; 931adfc5217SJeff Kirsher struct rxq_pause_params pause_params; 932adfc5217SJeff Kirsher unsigned long flags; 933adfc5217SJeff Kirsher }; 934adfc5217SJeff Kirsher 935adfc5217SJeff Kirsher struct bnx2x_queue_setup_tx_only_params { 936adfc5217SJeff Kirsher struct bnx2x_general_setup_params gen_params; 937adfc5217SJeff Kirsher struct bnx2x_txq_setup_params txq_params; 938adfc5217SJeff Kirsher unsigned long flags; 939adfc5217SJeff Kirsher /* index within the tx_only cids of this queue object */ 940adfc5217SJeff Kirsher u8 cid_index; 941adfc5217SJeff Kirsher }; 942adfc5217SJeff Kirsher 943adfc5217SJeff Kirsher struct bnx2x_queue_state_params { 944adfc5217SJeff Kirsher struct bnx2x_queue_sp_obj *q_obj; 945adfc5217SJeff Kirsher 946adfc5217SJeff Kirsher /* Current command */ 947adfc5217SJeff Kirsher enum bnx2x_queue_cmd cmd; 948adfc5217SJeff Kirsher 949adfc5217SJeff Kirsher /* may have RAMROD_COMP_WAIT set only */ 950adfc5217SJeff Kirsher unsigned long ramrod_flags; 951adfc5217SJeff Kirsher 952adfc5217SJeff Kirsher /* Params according to the current command */ 953adfc5217SJeff Kirsher union { 954adfc5217SJeff Kirsher struct bnx2x_queue_update_params update; 955adfc5217SJeff Kirsher struct bnx2x_queue_setup_params setup; 956adfc5217SJeff Kirsher struct bnx2x_queue_init_params init; 957adfc5217SJeff Kirsher struct bnx2x_queue_setup_tx_only_params tx_only; 958adfc5217SJeff Kirsher struct bnx2x_queue_terminate_params terminate; 959adfc5217SJeff Kirsher struct bnx2x_queue_cfc_del_params cfc_del; 960adfc5217SJeff Kirsher } params; 961adfc5217SJeff Kirsher }; 962adfc5217SJeff Kirsher 963adfc5217SJeff Kirsher struct bnx2x_queue_sp_obj { 964adfc5217SJeff Kirsher u32 cids[BNX2X_MULTI_TX_COS]; 965adfc5217SJeff Kirsher u8 cl_id; 966adfc5217SJeff Kirsher u8 func_id; 967adfc5217SJeff Kirsher 968adfc5217SJeff Kirsher /* 969adfc5217SJeff Kirsher * number of traffic classes supported by queue. 970adfc5217SJeff Kirsher * The primary connection of the queue suppotrs the first traffic 971adfc5217SJeff Kirsher * class. Any further traffic class is suppoted by a tx-only 972adfc5217SJeff Kirsher * connection. 973adfc5217SJeff Kirsher * 974adfc5217SJeff Kirsher * Therefore max_cos is also a number of valid entries in the cids 975adfc5217SJeff Kirsher * array. 976adfc5217SJeff Kirsher */ 977adfc5217SJeff Kirsher u8 max_cos; 978adfc5217SJeff Kirsher u8 num_tx_only, next_tx_only; 979adfc5217SJeff Kirsher 980adfc5217SJeff Kirsher enum bnx2x_q_state state, next_state; 981adfc5217SJeff Kirsher 982adfc5217SJeff Kirsher /* bits from enum bnx2x_q_type */ 983adfc5217SJeff Kirsher unsigned long type; 984adfc5217SJeff Kirsher 985adfc5217SJeff Kirsher /* BNX2X_Q_CMD_XX bits. This object implements "one 986adfc5217SJeff Kirsher * pending" paradigm but for debug and tracing purposes it's 987adfc5217SJeff Kirsher * more convinient to have different bits for different 988adfc5217SJeff Kirsher * commands. 989adfc5217SJeff Kirsher */ 990adfc5217SJeff Kirsher unsigned long pending; 991adfc5217SJeff Kirsher 992adfc5217SJeff Kirsher /* Buffer to use as a ramrod data and its mapping */ 993adfc5217SJeff Kirsher void *rdata; 994adfc5217SJeff Kirsher dma_addr_t rdata_mapping; 995adfc5217SJeff Kirsher 996adfc5217SJeff Kirsher /** 997adfc5217SJeff Kirsher * Performs one state change according to the given parameters. 998adfc5217SJeff Kirsher * 999adfc5217SJeff Kirsher * @return 0 in case of success and negative value otherwise. 1000adfc5217SJeff Kirsher */ 1001adfc5217SJeff Kirsher int (*send_cmd)(struct bnx2x *bp, 1002adfc5217SJeff Kirsher struct bnx2x_queue_state_params *params); 1003adfc5217SJeff Kirsher 1004adfc5217SJeff Kirsher /** 1005adfc5217SJeff Kirsher * Sets the pending bit according to the requested transition. 1006adfc5217SJeff Kirsher */ 1007adfc5217SJeff Kirsher int (*set_pending)(struct bnx2x_queue_sp_obj *o, 1008adfc5217SJeff Kirsher struct bnx2x_queue_state_params *params); 1009adfc5217SJeff Kirsher 1010adfc5217SJeff Kirsher /** 1011adfc5217SJeff Kirsher * Checks that the requested state transition is legal. 1012adfc5217SJeff Kirsher */ 1013adfc5217SJeff Kirsher int (*check_transition)(struct bnx2x *bp, 1014adfc5217SJeff Kirsher struct bnx2x_queue_sp_obj *o, 1015adfc5217SJeff Kirsher struct bnx2x_queue_state_params *params); 1016adfc5217SJeff Kirsher 1017adfc5217SJeff Kirsher /** 1018adfc5217SJeff Kirsher * Completes the pending command. 1019adfc5217SJeff Kirsher */ 1020adfc5217SJeff Kirsher int (*complete_cmd)(struct bnx2x *bp, 1021adfc5217SJeff Kirsher struct bnx2x_queue_sp_obj *o, 1022adfc5217SJeff Kirsher enum bnx2x_queue_cmd); 1023adfc5217SJeff Kirsher 1024adfc5217SJeff Kirsher int (*wait_comp)(struct bnx2x *bp, 1025adfc5217SJeff Kirsher struct bnx2x_queue_sp_obj *o, 1026adfc5217SJeff Kirsher enum bnx2x_queue_cmd cmd); 1027adfc5217SJeff Kirsher }; 1028adfc5217SJeff Kirsher 1029adfc5217SJeff Kirsher /********************** Function state update *********************************/ 1030adfc5217SJeff Kirsher /* Allowed Function states */ 1031adfc5217SJeff Kirsher enum bnx2x_func_state { 1032adfc5217SJeff Kirsher BNX2X_F_STATE_RESET, 1033adfc5217SJeff Kirsher BNX2X_F_STATE_INITIALIZED, 1034adfc5217SJeff Kirsher BNX2X_F_STATE_STARTED, 1035adfc5217SJeff Kirsher BNX2X_F_STATE_TX_STOPPED, 1036adfc5217SJeff Kirsher BNX2X_F_STATE_MAX, 1037adfc5217SJeff Kirsher }; 1038adfc5217SJeff Kirsher 1039adfc5217SJeff Kirsher /* Allowed Function commands */ 1040adfc5217SJeff Kirsher enum bnx2x_func_cmd { 1041adfc5217SJeff Kirsher BNX2X_F_CMD_HW_INIT, 1042adfc5217SJeff Kirsher BNX2X_F_CMD_START, 1043adfc5217SJeff Kirsher BNX2X_F_CMD_STOP, 1044adfc5217SJeff Kirsher BNX2X_F_CMD_HW_RESET, 1045adfc5217SJeff Kirsher BNX2X_F_CMD_TX_STOP, 1046adfc5217SJeff Kirsher BNX2X_F_CMD_TX_START, 1047adfc5217SJeff Kirsher BNX2X_F_CMD_MAX, 1048adfc5217SJeff Kirsher }; 1049adfc5217SJeff Kirsher 1050adfc5217SJeff Kirsher struct bnx2x_func_hw_init_params { 1051adfc5217SJeff Kirsher /* A load phase returned by MCP. 1052adfc5217SJeff Kirsher * 1053adfc5217SJeff Kirsher * May be: 1054adfc5217SJeff Kirsher * FW_MSG_CODE_DRV_LOAD_COMMON_CHIP 1055adfc5217SJeff Kirsher * FW_MSG_CODE_DRV_LOAD_COMMON 1056adfc5217SJeff Kirsher * FW_MSG_CODE_DRV_LOAD_PORT 1057adfc5217SJeff Kirsher * FW_MSG_CODE_DRV_LOAD_FUNCTION 1058adfc5217SJeff Kirsher */ 1059adfc5217SJeff Kirsher u32 load_phase; 1060adfc5217SJeff Kirsher }; 1061adfc5217SJeff Kirsher 1062adfc5217SJeff Kirsher struct bnx2x_func_hw_reset_params { 1063adfc5217SJeff Kirsher /* A load phase returned by MCP. 1064adfc5217SJeff Kirsher * 1065adfc5217SJeff Kirsher * May be: 1066adfc5217SJeff Kirsher * FW_MSG_CODE_DRV_LOAD_COMMON_CHIP 1067adfc5217SJeff Kirsher * FW_MSG_CODE_DRV_LOAD_COMMON 1068adfc5217SJeff Kirsher * FW_MSG_CODE_DRV_LOAD_PORT 1069adfc5217SJeff Kirsher * FW_MSG_CODE_DRV_LOAD_FUNCTION 1070adfc5217SJeff Kirsher */ 1071adfc5217SJeff Kirsher u32 reset_phase; 1072adfc5217SJeff Kirsher }; 1073adfc5217SJeff Kirsher 1074adfc5217SJeff Kirsher struct bnx2x_func_start_params { 1075adfc5217SJeff Kirsher /* Multi Function mode: 1076adfc5217SJeff Kirsher * - Single Function 1077adfc5217SJeff Kirsher * - Switch Dependent 1078adfc5217SJeff Kirsher * - Switch Independent 1079adfc5217SJeff Kirsher */ 1080adfc5217SJeff Kirsher u16 mf_mode; 1081adfc5217SJeff Kirsher 1082adfc5217SJeff Kirsher /* Switch Dependent mode outer VLAN tag */ 1083adfc5217SJeff Kirsher u16 sd_vlan_tag; 1084adfc5217SJeff Kirsher 1085adfc5217SJeff Kirsher /* Function cos mode */ 1086adfc5217SJeff Kirsher u8 network_cos_mode; 1087adfc5217SJeff Kirsher }; 1088adfc5217SJeff Kirsher 1089adfc5217SJeff Kirsher struct bnx2x_func_tx_start_params { 1090adfc5217SJeff Kirsher struct priority_cos traffic_type_to_priority_cos[MAX_TRAFFIC_TYPES]; 1091adfc5217SJeff Kirsher u8 dcb_enabled; 1092adfc5217SJeff Kirsher u8 dcb_version; 1093adfc5217SJeff Kirsher u8 dont_add_pri_0_en; 1094adfc5217SJeff Kirsher }; 1095adfc5217SJeff Kirsher 1096adfc5217SJeff Kirsher struct bnx2x_func_state_params { 1097adfc5217SJeff Kirsher struct bnx2x_func_sp_obj *f_obj; 1098adfc5217SJeff Kirsher 1099adfc5217SJeff Kirsher /* Current command */ 1100adfc5217SJeff Kirsher enum bnx2x_func_cmd cmd; 1101adfc5217SJeff Kirsher 1102adfc5217SJeff Kirsher /* may have RAMROD_COMP_WAIT set only */ 1103adfc5217SJeff Kirsher unsigned long ramrod_flags; 1104adfc5217SJeff Kirsher 1105adfc5217SJeff Kirsher /* Params according to the current command */ 1106adfc5217SJeff Kirsher union { 1107adfc5217SJeff Kirsher struct bnx2x_func_hw_init_params hw_init; 1108adfc5217SJeff Kirsher struct bnx2x_func_hw_reset_params hw_reset; 1109adfc5217SJeff Kirsher struct bnx2x_func_start_params start; 1110adfc5217SJeff Kirsher struct bnx2x_func_tx_start_params tx_start; 1111adfc5217SJeff Kirsher } params; 1112adfc5217SJeff Kirsher }; 1113adfc5217SJeff Kirsher 1114adfc5217SJeff Kirsher struct bnx2x_func_sp_drv_ops { 1115adfc5217SJeff Kirsher /* Init tool + runtime initialization: 1116adfc5217SJeff Kirsher * - Common Chip 1117adfc5217SJeff Kirsher * - Common (per Path) 1118adfc5217SJeff Kirsher * - Port 1119adfc5217SJeff Kirsher * - Function phases 1120adfc5217SJeff Kirsher */ 1121adfc5217SJeff Kirsher int (*init_hw_cmn_chip)(struct bnx2x *bp); 1122adfc5217SJeff Kirsher int (*init_hw_cmn)(struct bnx2x *bp); 1123adfc5217SJeff Kirsher int (*init_hw_port)(struct bnx2x *bp); 1124adfc5217SJeff Kirsher int (*init_hw_func)(struct bnx2x *bp); 1125adfc5217SJeff Kirsher 1126adfc5217SJeff Kirsher /* Reset Function HW: Common, Port, Function phases. */ 1127adfc5217SJeff Kirsher void (*reset_hw_cmn)(struct bnx2x *bp); 1128adfc5217SJeff Kirsher void (*reset_hw_port)(struct bnx2x *bp); 1129adfc5217SJeff Kirsher void (*reset_hw_func)(struct bnx2x *bp); 1130adfc5217SJeff Kirsher 1131adfc5217SJeff Kirsher /* Init/Free GUNZIP resources */ 1132adfc5217SJeff Kirsher int (*gunzip_init)(struct bnx2x *bp); 1133adfc5217SJeff Kirsher void (*gunzip_end)(struct bnx2x *bp); 1134adfc5217SJeff Kirsher 1135adfc5217SJeff Kirsher /* Prepare/Release FW resources */ 1136adfc5217SJeff Kirsher int (*init_fw)(struct bnx2x *bp); 1137adfc5217SJeff Kirsher void (*release_fw)(struct bnx2x *bp); 1138adfc5217SJeff Kirsher }; 1139adfc5217SJeff Kirsher 1140adfc5217SJeff Kirsher struct bnx2x_func_sp_obj { 1141adfc5217SJeff Kirsher enum bnx2x_func_state state, next_state; 1142adfc5217SJeff Kirsher 1143adfc5217SJeff Kirsher /* BNX2X_FUNC_CMD_XX bits. This object implements "one 1144adfc5217SJeff Kirsher * pending" paradigm but for debug and tracing purposes it's 1145adfc5217SJeff Kirsher * more convinient to have different bits for different 1146adfc5217SJeff Kirsher * commands. 1147adfc5217SJeff Kirsher */ 1148adfc5217SJeff Kirsher unsigned long pending; 1149adfc5217SJeff Kirsher 1150adfc5217SJeff Kirsher /* Buffer to use as a ramrod data and its mapping */ 1151adfc5217SJeff Kirsher void *rdata; 1152adfc5217SJeff Kirsher dma_addr_t rdata_mapping; 1153adfc5217SJeff Kirsher 1154adfc5217SJeff Kirsher /* this mutex validates that when pending flag is taken, the next 1155adfc5217SJeff Kirsher * ramrod to be sent will be the one set the pending bit 1156adfc5217SJeff Kirsher */ 1157adfc5217SJeff Kirsher struct mutex one_pending_mutex; 1158adfc5217SJeff Kirsher 1159adfc5217SJeff Kirsher /* Driver interface */ 1160adfc5217SJeff Kirsher struct bnx2x_func_sp_drv_ops *drv; 1161adfc5217SJeff Kirsher 1162adfc5217SJeff Kirsher /** 1163adfc5217SJeff Kirsher * Performs one state change according to the given parameters. 1164adfc5217SJeff Kirsher * 1165adfc5217SJeff Kirsher * @return 0 in case of success and negative value otherwise. 1166adfc5217SJeff Kirsher */ 1167adfc5217SJeff Kirsher int (*send_cmd)(struct bnx2x *bp, 1168adfc5217SJeff Kirsher struct bnx2x_func_state_params *params); 1169adfc5217SJeff Kirsher 1170adfc5217SJeff Kirsher /** 1171adfc5217SJeff Kirsher * Checks that the requested state transition is legal. 1172adfc5217SJeff Kirsher */ 1173adfc5217SJeff Kirsher int (*check_transition)(struct bnx2x *bp, 1174adfc5217SJeff Kirsher struct bnx2x_func_sp_obj *o, 1175adfc5217SJeff Kirsher struct bnx2x_func_state_params *params); 1176adfc5217SJeff Kirsher 1177adfc5217SJeff Kirsher /** 1178adfc5217SJeff Kirsher * Completes the pending command. 1179adfc5217SJeff Kirsher */ 1180adfc5217SJeff Kirsher int (*complete_cmd)(struct bnx2x *bp, 1181adfc5217SJeff Kirsher struct bnx2x_func_sp_obj *o, 1182adfc5217SJeff Kirsher enum bnx2x_func_cmd cmd); 1183adfc5217SJeff Kirsher 1184adfc5217SJeff Kirsher int (*wait_comp)(struct bnx2x *bp, struct bnx2x_func_sp_obj *o, 1185adfc5217SJeff Kirsher enum bnx2x_func_cmd cmd); 1186adfc5217SJeff Kirsher }; 1187adfc5217SJeff Kirsher 1188adfc5217SJeff Kirsher /********************** Interfaces ********************************************/ 1189adfc5217SJeff Kirsher /* Queueable objects set */ 1190adfc5217SJeff Kirsher union bnx2x_qable_obj { 1191adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj vlan_mac; 1192adfc5217SJeff Kirsher }; 1193adfc5217SJeff Kirsher /************** Function state update *********/ 1194adfc5217SJeff Kirsher void bnx2x_init_func_obj(struct bnx2x *bp, 1195adfc5217SJeff Kirsher struct bnx2x_func_sp_obj *obj, 1196adfc5217SJeff Kirsher void *rdata, dma_addr_t rdata_mapping, 1197adfc5217SJeff Kirsher struct bnx2x_func_sp_drv_ops *drv_iface); 1198adfc5217SJeff Kirsher 1199adfc5217SJeff Kirsher int bnx2x_func_state_change(struct bnx2x *bp, 1200adfc5217SJeff Kirsher struct bnx2x_func_state_params *params); 1201adfc5217SJeff Kirsher 1202adfc5217SJeff Kirsher enum bnx2x_func_state bnx2x_func_get_state(struct bnx2x *bp, 1203adfc5217SJeff Kirsher struct bnx2x_func_sp_obj *o); 1204adfc5217SJeff Kirsher /******************* Queue State **************/ 1205adfc5217SJeff Kirsher void bnx2x_init_queue_obj(struct bnx2x *bp, 1206adfc5217SJeff Kirsher struct bnx2x_queue_sp_obj *obj, u8 cl_id, u32 *cids, 1207adfc5217SJeff Kirsher u8 cid_cnt, u8 func_id, void *rdata, 1208adfc5217SJeff Kirsher dma_addr_t rdata_mapping, unsigned long type); 1209adfc5217SJeff Kirsher 1210adfc5217SJeff Kirsher int bnx2x_queue_state_change(struct bnx2x *bp, 1211adfc5217SJeff Kirsher struct bnx2x_queue_state_params *params); 1212adfc5217SJeff Kirsher 1213adfc5217SJeff Kirsher /********************* VLAN-MAC ****************/ 1214adfc5217SJeff Kirsher void bnx2x_init_mac_obj(struct bnx2x *bp, 1215adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *mac_obj, 1216adfc5217SJeff Kirsher u8 cl_id, u32 cid, u8 func_id, void *rdata, 1217adfc5217SJeff Kirsher dma_addr_t rdata_mapping, int state, 1218adfc5217SJeff Kirsher unsigned long *pstate, bnx2x_obj_type type, 1219adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *macs_pool); 1220adfc5217SJeff Kirsher 1221adfc5217SJeff Kirsher void bnx2x_init_vlan_obj(struct bnx2x *bp, 1222adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *vlan_obj, 1223adfc5217SJeff Kirsher u8 cl_id, u32 cid, u8 func_id, void *rdata, 1224adfc5217SJeff Kirsher dma_addr_t rdata_mapping, int state, 1225adfc5217SJeff Kirsher unsigned long *pstate, bnx2x_obj_type type, 1226adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *vlans_pool); 1227adfc5217SJeff Kirsher 1228adfc5217SJeff Kirsher void bnx2x_init_vlan_mac_obj(struct bnx2x *bp, 1229adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *vlan_mac_obj, 1230adfc5217SJeff Kirsher u8 cl_id, u32 cid, u8 func_id, void *rdata, 1231adfc5217SJeff Kirsher dma_addr_t rdata_mapping, int state, 1232adfc5217SJeff Kirsher unsigned long *pstate, bnx2x_obj_type type, 1233adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *macs_pool, 1234adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *vlans_pool); 1235adfc5217SJeff Kirsher 1236adfc5217SJeff Kirsher int bnx2x_config_vlan_mac(struct bnx2x *bp, 1237adfc5217SJeff Kirsher struct bnx2x_vlan_mac_ramrod_params *p); 1238adfc5217SJeff Kirsher 1239adfc5217SJeff Kirsher int bnx2x_vlan_mac_move(struct bnx2x *bp, 1240adfc5217SJeff Kirsher struct bnx2x_vlan_mac_ramrod_params *p, 1241adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *dest_o); 1242adfc5217SJeff Kirsher 1243adfc5217SJeff Kirsher /********************* RX MODE ****************/ 1244adfc5217SJeff Kirsher 1245adfc5217SJeff Kirsher void bnx2x_init_rx_mode_obj(struct bnx2x *bp, 1246adfc5217SJeff Kirsher struct bnx2x_rx_mode_obj *o); 1247adfc5217SJeff Kirsher 1248adfc5217SJeff Kirsher /** 1249adfc5217SJeff Kirsher * Send and RX_MODE ramrod according to the provided parameters. 1250adfc5217SJeff Kirsher * 1251adfc5217SJeff Kirsher * @param bp 1252adfc5217SJeff Kirsher * @param p Command parameters 1253adfc5217SJeff Kirsher * 1254adfc5217SJeff Kirsher * @return 0 - if operation was successfull and there is no pending completions, 1255adfc5217SJeff Kirsher * positive number - if there are pending completions, 1256adfc5217SJeff Kirsher * negative - if there were errors 1257adfc5217SJeff Kirsher */ 1258adfc5217SJeff Kirsher int bnx2x_config_rx_mode(struct bnx2x *bp, 1259adfc5217SJeff Kirsher struct bnx2x_rx_mode_ramrod_params *p); 1260adfc5217SJeff Kirsher 1261adfc5217SJeff Kirsher /****************** MULTICASTS ****************/ 1262adfc5217SJeff Kirsher 1263adfc5217SJeff Kirsher void bnx2x_init_mcast_obj(struct bnx2x *bp, 1264adfc5217SJeff Kirsher struct bnx2x_mcast_obj *mcast_obj, 1265adfc5217SJeff Kirsher u8 mcast_cl_id, u32 mcast_cid, u8 func_id, 1266adfc5217SJeff Kirsher u8 engine_id, void *rdata, dma_addr_t rdata_mapping, 1267adfc5217SJeff Kirsher int state, unsigned long *pstate, 1268adfc5217SJeff Kirsher bnx2x_obj_type type); 1269adfc5217SJeff Kirsher 1270adfc5217SJeff Kirsher /** 1271adfc5217SJeff Kirsher * Configure multicast MACs list. May configure a new list 1272adfc5217SJeff Kirsher * provided in p->mcast_list (BNX2X_MCAST_CMD_ADD), clean up 1273adfc5217SJeff Kirsher * (BNX2X_MCAST_CMD_DEL) or restore (BNX2X_MCAST_CMD_RESTORE) a current 1274adfc5217SJeff Kirsher * configuration, continue to execute the pending commands 1275adfc5217SJeff Kirsher * (BNX2X_MCAST_CMD_CONT). 1276adfc5217SJeff Kirsher * 1277adfc5217SJeff Kirsher * If previous command is still pending or if number of MACs to 1278adfc5217SJeff Kirsher * configure is more that maximum number of MACs in one command, 1279adfc5217SJeff Kirsher * the current command will be enqueued to the tail of the 1280adfc5217SJeff Kirsher * pending commands list. 1281adfc5217SJeff Kirsher * 1282adfc5217SJeff Kirsher * @param bp 1283adfc5217SJeff Kirsher * @param p 1284adfc5217SJeff Kirsher * @param command to execute: BNX2X_MCAST_CMD_X 1285adfc5217SJeff Kirsher * 1286adfc5217SJeff Kirsher * @return 0 is operation was sucessfull and there are no pending completions, 1287adfc5217SJeff Kirsher * negative if there were errors, positive if there are pending 1288adfc5217SJeff Kirsher * completions. 1289adfc5217SJeff Kirsher */ 1290adfc5217SJeff Kirsher int bnx2x_config_mcast(struct bnx2x *bp, 1291adfc5217SJeff Kirsher struct bnx2x_mcast_ramrod_params *p, int cmd); 1292adfc5217SJeff Kirsher 1293adfc5217SJeff Kirsher /****************** CREDIT POOL ****************/ 1294adfc5217SJeff Kirsher void bnx2x_init_mac_credit_pool(struct bnx2x *bp, 1295adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *p, u8 func_id, 1296adfc5217SJeff Kirsher u8 func_num); 1297adfc5217SJeff Kirsher void bnx2x_init_vlan_credit_pool(struct bnx2x *bp, 1298adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *p, u8 func_id, 1299adfc5217SJeff Kirsher u8 func_num); 1300adfc5217SJeff Kirsher 1301adfc5217SJeff Kirsher 1302adfc5217SJeff Kirsher /****************** RSS CONFIGURATION ****************/ 1303adfc5217SJeff Kirsher void bnx2x_init_rss_config_obj(struct bnx2x *bp, 1304adfc5217SJeff Kirsher struct bnx2x_rss_config_obj *rss_obj, 1305adfc5217SJeff Kirsher u8 cl_id, u32 cid, u8 func_id, u8 engine_id, 1306adfc5217SJeff Kirsher void *rdata, dma_addr_t rdata_mapping, 1307adfc5217SJeff Kirsher int state, unsigned long *pstate, 1308adfc5217SJeff Kirsher bnx2x_obj_type type); 1309adfc5217SJeff Kirsher 1310adfc5217SJeff Kirsher /** 1311adfc5217SJeff Kirsher * Updates RSS configuration according to provided parameters. 1312adfc5217SJeff Kirsher * 1313adfc5217SJeff Kirsher * @param bp 1314adfc5217SJeff Kirsher * @param p 1315adfc5217SJeff Kirsher * 1316adfc5217SJeff Kirsher * @return 0 in case of success 1317adfc5217SJeff Kirsher */ 1318adfc5217SJeff Kirsher int bnx2x_config_rss(struct bnx2x *bp, 1319adfc5217SJeff Kirsher struct bnx2x_config_rss_params *p); 1320adfc5217SJeff Kirsher 1321adfc5217SJeff Kirsher /** 1322adfc5217SJeff Kirsher * Return the current ind_table configuration. 1323adfc5217SJeff Kirsher * 1324adfc5217SJeff Kirsher * @param bp 1325adfc5217SJeff Kirsher * @param ind_table buffer to fill with the current indirection 1326adfc5217SJeff Kirsher * table content. Should be at least 1327adfc5217SJeff Kirsher * T_ETH_INDIRECTION_TABLE_SIZE bytes long. 1328adfc5217SJeff Kirsher */ 1329adfc5217SJeff Kirsher void bnx2x_get_rss_ind_table(struct bnx2x_rss_config_obj *rss_obj, 1330adfc5217SJeff Kirsher u8 *ind_table); 1331adfc5217SJeff Kirsher 1332adfc5217SJeff Kirsher #endif /* BNX2X_SP_VERBS */ 1333