14ad79e13SYuval Mintz /* bnx2x_sp.h: Qlogic Everest network driver. 2adfc5217SJeff Kirsher * 34ad79e13SYuval Mintz * Copyright 2011-2013 Broadcom Corporation 44ad79e13SYuval Mintz * Copyright (c) 2014 QLogic Corporation 54ad79e13SYuval Mintz * All rights reserved 6adfc5217SJeff Kirsher * 74ad79e13SYuval Mintz * Unless you and Qlogic execute a separate written software license 8adfc5217SJeff Kirsher * agreement governing use of this software, this software is licensed to you 9adfc5217SJeff Kirsher * under the terms of the GNU General Public License version 2, available 104ad79e13SYuval Mintz * at http://www.gnu.org/licenses/gpl-2.0.html (the "GPL"). 11adfc5217SJeff Kirsher * 12adfc5217SJeff Kirsher * Notwithstanding the above, under no circumstances may you combine this 134ad79e13SYuval Mintz * software in any way with any other Qlogic software provided under a 144ad79e13SYuval Mintz * license other than the GPL, without Qlogic's express prior written 15adfc5217SJeff Kirsher * consent. 16adfc5217SJeff Kirsher * 1708f6dd89SAriel Elior * Maintained by: Ariel Elior <ariel.elior@qlogic.com> 18adfc5217SJeff Kirsher * Written by: Vladislav Zolotarov 19adfc5217SJeff Kirsher * 20adfc5217SJeff Kirsher */ 21adfc5217SJeff Kirsher #ifndef BNX2X_SP_VERBS 22adfc5217SJeff Kirsher #define BNX2X_SP_VERBS 23adfc5217SJeff Kirsher 24adfc5217SJeff Kirsher struct bnx2x; 25adfc5217SJeff Kirsher struct eth_context; 26adfc5217SJeff Kirsher 27adfc5217SJeff Kirsher /* Bits representing general command's configuration */ 28adfc5217SJeff Kirsher enum { 29adfc5217SJeff Kirsher RAMROD_TX, 30adfc5217SJeff Kirsher RAMROD_RX, 31adfc5217SJeff Kirsher /* Wait until all pending commands complete */ 32adfc5217SJeff Kirsher RAMROD_COMP_WAIT, 33adfc5217SJeff Kirsher /* Don't send a ramrod, only update a registry */ 34adfc5217SJeff Kirsher RAMROD_DRV_CLR_ONLY, 35adfc5217SJeff Kirsher /* Configure HW according to the current object state */ 36adfc5217SJeff Kirsher RAMROD_RESTORE, 37adfc5217SJeff Kirsher /* Execute the next command now */ 38adfc5217SJeff Kirsher RAMROD_EXEC, 3916a5fd92SYuval Mintz /* Don't add a new command and continue execution of postponed 40adfc5217SJeff Kirsher * commands. If not set a new command will be added to the 41adfc5217SJeff Kirsher * pending commands list. 42adfc5217SJeff Kirsher */ 43adfc5217SJeff Kirsher RAMROD_CONT, 4455c11941SMerav Sicron /* If there is another pending ramrod, wait until it finishes and 4555c11941SMerav Sicron * re-try to submit this one. This flag can be set only in sleepable 4655c11941SMerav Sicron * context, and should not be set from the context that completes the 4755c11941SMerav Sicron * ramrods as deadlock will occur. 4855c11941SMerav Sicron */ 4955c11941SMerav Sicron RAMROD_RETRY, 50adfc5217SJeff Kirsher }; 51adfc5217SJeff Kirsher 52adfc5217SJeff Kirsher typedef enum { 53adfc5217SJeff Kirsher BNX2X_OBJ_TYPE_RX, 54adfc5217SJeff Kirsher BNX2X_OBJ_TYPE_TX, 55adfc5217SJeff Kirsher BNX2X_OBJ_TYPE_RX_TX, 56adfc5217SJeff Kirsher } bnx2x_obj_type; 57adfc5217SJeff Kirsher 582de67439SYuval Mintz /* Public slow path states */ 59adfc5217SJeff Kirsher enum { 60adfc5217SJeff Kirsher BNX2X_FILTER_MAC_PENDING, 61adfc5217SJeff Kirsher BNX2X_FILTER_VLAN_PENDING, 62adfc5217SJeff Kirsher BNX2X_FILTER_VLAN_MAC_PENDING, 63adfc5217SJeff Kirsher BNX2X_FILTER_RX_MODE_PENDING, 64adfc5217SJeff Kirsher BNX2X_FILTER_RX_MODE_SCHED, 65adfc5217SJeff Kirsher BNX2X_FILTER_ISCSI_ETH_START_SCHED, 66adfc5217SJeff Kirsher BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, 67adfc5217SJeff Kirsher BNX2X_FILTER_FCOE_ETH_START_SCHED, 68adfc5217SJeff Kirsher BNX2X_FILTER_FCOE_ETH_STOP_SCHED, 69adfc5217SJeff Kirsher BNX2X_FILTER_MCAST_PENDING, 70adfc5217SJeff Kirsher BNX2X_FILTER_MCAST_SCHED, 71adfc5217SJeff Kirsher BNX2X_FILTER_RSS_CONF_PENDING, 72a3348722SBarak Witkowski BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, 73a3348722SBarak Witkowski BNX2X_AFEX_PENDING_VIFSET_MCP_ACK 74adfc5217SJeff Kirsher }; 75adfc5217SJeff Kirsher 76adfc5217SJeff Kirsher struct bnx2x_raw_obj { 77adfc5217SJeff Kirsher u8 func_id; 78adfc5217SJeff Kirsher 79adfc5217SJeff Kirsher /* Queue params */ 80adfc5217SJeff Kirsher u8 cl_id; 81adfc5217SJeff Kirsher u32 cid; 82adfc5217SJeff Kirsher 83adfc5217SJeff Kirsher /* Ramrod data buffer params */ 84adfc5217SJeff Kirsher void *rdata; 85adfc5217SJeff Kirsher dma_addr_t rdata_mapping; 86adfc5217SJeff Kirsher 87adfc5217SJeff Kirsher /* Ramrod state params */ 88adfc5217SJeff Kirsher int state; /* "ramrod is pending" state bit */ 89adfc5217SJeff Kirsher unsigned long *pstate; /* pointer to state buffer */ 90adfc5217SJeff Kirsher 91adfc5217SJeff Kirsher bnx2x_obj_type obj_type; 92adfc5217SJeff Kirsher 93adfc5217SJeff Kirsher int (*wait_comp)(struct bnx2x *bp, 94adfc5217SJeff Kirsher struct bnx2x_raw_obj *o); 95adfc5217SJeff Kirsher 96adfc5217SJeff Kirsher bool (*check_pending)(struct bnx2x_raw_obj *o); 97adfc5217SJeff Kirsher void (*clear_pending)(struct bnx2x_raw_obj *o); 98adfc5217SJeff Kirsher void (*set_pending)(struct bnx2x_raw_obj *o); 99adfc5217SJeff Kirsher }; 100adfc5217SJeff Kirsher 101adfc5217SJeff Kirsher /************************* VLAN-MAC commands related parameters ***************/ 102adfc5217SJeff Kirsher struct bnx2x_mac_ramrod_data { 103adfc5217SJeff Kirsher u8 mac[ETH_ALEN]; 10491226790SDmitry Kravkov u8 is_inner_mac; 105adfc5217SJeff Kirsher }; 106adfc5217SJeff Kirsher 107adfc5217SJeff Kirsher struct bnx2x_vlan_ramrod_data { 108adfc5217SJeff Kirsher u16 vlan; 109adfc5217SJeff Kirsher }; 110adfc5217SJeff Kirsher 111adfc5217SJeff Kirsher struct bnx2x_vlan_mac_ramrod_data { 112adfc5217SJeff Kirsher u8 mac[ETH_ALEN]; 11391226790SDmitry Kravkov u8 is_inner_mac; 114adfc5217SJeff Kirsher u16 vlan; 115adfc5217SJeff Kirsher }; 116adfc5217SJeff Kirsher 117adfc5217SJeff Kirsher union bnx2x_classification_ramrod_data { 118adfc5217SJeff Kirsher struct bnx2x_mac_ramrod_data mac; 119adfc5217SJeff Kirsher struct bnx2x_vlan_ramrod_data vlan; 120adfc5217SJeff Kirsher struct bnx2x_vlan_mac_ramrod_data vlan_mac; 121adfc5217SJeff Kirsher }; 122adfc5217SJeff Kirsher 123adfc5217SJeff Kirsher /* VLAN_MAC commands */ 124adfc5217SJeff Kirsher enum bnx2x_vlan_mac_cmd { 125adfc5217SJeff Kirsher BNX2X_VLAN_MAC_ADD, 126adfc5217SJeff Kirsher BNX2X_VLAN_MAC_DEL, 127adfc5217SJeff Kirsher BNX2X_VLAN_MAC_MOVE, 128adfc5217SJeff Kirsher }; 129adfc5217SJeff Kirsher 130adfc5217SJeff Kirsher struct bnx2x_vlan_mac_data { 131adfc5217SJeff Kirsher /* Requested command: BNX2X_VLAN_MAC_XX */ 132adfc5217SJeff Kirsher enum bnx2x_vlan_mac_cmd cmd; 13316a5fd92SYuval Mintz /* used to contain the data related vlan_mac_flags bits from 134adfc5217SJeff Kirsher * ramrod parameters. 135adfc5217SJeff Kirsher */ 136adfc5217SJeff Kirsher unsigned long vlan_mac_flags; 137adfc5217SJeff Kirsher 138adfc5217SJeff Kirsher /* Needed for MOVE command */ 139adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *target_obj; 140adfc5217SJeff Kirsher 141adfc5217SJeff Kirsher union bnx2x_classification_ramrod_data u; 142adfc5217SJeff Kirsher }; 143adfc5217SJeff Kirsher 144adfc5217SJeff Kirsher /*************************** Exe Queue obj ************************************/ 145adfc5217SJeff Kirsher union bnx2x_exe_queue_cmd_data { 146adfc5217SJeff Kirsher struct bnx2x_vlan_mac_data vlan_mac; 147adfc5217SJeff Kirsher 148adfc5217SJeff Kirsher struct { 149adfc5217SJeff Kirsher /* TODO */ 150adfc5217SJeff Kirsher } mcast; 151adfc5217SJeff Kirsher }; 152adfc5217SJeff Kirsher 153adfc5217SJeff Kirsher struct bnx2x_exeq_elem { 154adfc5217SJeff Kirsher struct list_head link; 155adfc5217SJeff Kirsher 156adfc5217SJeff Kirsher /* Length of this element in the exe_chunk. */ 157adfc5217SJeff Kirsher int cmd_len; 158adfc5217SJeff Kirsher 159adfc5217SJeff Kirsher union bnx2x_exe_queue_cmd_data cmd_data; 160adfc5217SJeff Kirsher }; 161adfc5217SJeff Kirsher 162adfc5217SJeff Kirsher union bnx2x_qable_obj; 163adfc5217SJeff Kirsher 164adfc5217SJeff Kirsher union bnx2x_exeq_comp_elem { 165adfc5217SJeff Kirsher union event_ring_elem *elem; 166adfc5217SJeff Kirsher }; 167adfc5217SJeff Kirsher 168adfc5217SJeff Kirsher struct bnx2x_exe_queue_obj; 169adfc5217SJeff Kirsher 170adfc5217SJeff Kirsher typedef int (*exe_q_validate)(struct bnx2x *bp, 171adfc5217SJeff Kirsher union bnx2x_qable_obj *o, 172adfc5217SJeff Kirsher struct bnx2x_exeq_elem *elem); 173adfc5217SJeff Kirsher 174460a25cdSYuval Mintz typedef int (*exe_q_remove)(struct bnx2x *bp, 175460a25cdSYuval Mintz union bnx2x_qable_obj *o, 176460a25cdSYuval Mintz struct bnx2x_exeq_elem *elem); 177460a25cdSYuval Mintz 1781aa8b471SBen Hutchings /* Return positive if entry was optimized, 0 - if not, negative 179adfc5217SJeff Kirsher * in case of an error. 180adfc5217SJeff Kirsher */ 181adfc5217SJeff Kirsher typedef int (*exe_q_optimize)(struct bnx2x *bp, 182adfc5217SJeff Kirsher union bnx2x_qable_obj *o, 183adfc5217SJeff Kirsher struct bnx2x_exeq_elem *elem); 184adfc5217SJeff Kirsher typedef int (*exe_q_execute)(struct bnx2x *bp, 185adfc5217SJeff Kirsher union bnx2x_qable_obj *o, 186adfc5217SJeff Kirsher struct list_head *exe_chunk, 187adfc5217SJeff Kirsher unsigned long *ramrod_flags); 188adfc5217SJeff Kirsher typedef struct bnx2x_exeq_elem * 189adfc5217SJeff Kirsher (*exe_q_get)(struct bnx2x_exe_queue_obj *o, 190adfc5217SJeff Kirsher struct bnx2x_exeq_elem *elem); 191adfc5217SJeff Kirsher 192adfc5217SJeff Kirsher struct bnx2x_exe_queue_obj { 19316a5fd92SYuval Mintz /* Commands pending for an execution. */ 194adfc5217SJeff Kirsher struct list_head exe_queue; 195adfc5217SJeff Kirsher 19616a5fd92SYuval Mintz /* Commands pending for an completion. */ 197adfc5217SJeff Kirsher struct list_head pending_comp; 198adfc5217SJeff Kirsher 199adfc5217SJeff Kirsher spinlock_t lock; 200adfc5217SJeff Kirsher 201adfc5217SJeff Kirsher /* Maximum length of commands' list for one execution */ 202adfc5217SJeff Kirsher int exe_chunk_len; 203adfc5217SJeff Kirsher 204adfc5217SJeff Kirsher union bnx2x_qable_obj *owner; 205adfc5217SJeff Kirsher 206adfc5217SJeff Kirsher /****** Virtual functions ******/ 207adfc5217SJeff Kirsher /** 208adfc5217SJeff Kirsher * Called before commands execution for commands that are really 209adfc5217SJeff Kirsher * going to be executed (after 'optimize'). 210adfc5217SJeff Kirsher * 211adfc5217SJeff Kirsher * Must run under exe_queue->lock 212adfc5217SJeff Kirsher */ 213adfc5217SJeff Kirsher exe_q_validate validate; 214adfc5217SJeff Kirsher 215460a25cdSYuval Mintz /** 216460a25cdSYuval Mintz * Called before removing pending commands, cleaning allocated 217460a25cdSYuval Mintz * resources (e.g., credits from validate) 218460a25cdSYuval Mintz */ 219460a25cdSYuval Mintz exe_q_remove remove; 220adfc5217SJeff Kirsher 221adfc5217SJeff Kirsher /** 222adfc5217SJeff Kirsher * This will try to cancel the current pending commands list 223adfc5217SJeff Kirsher * considering the new command. 224adfc5217SJeff Kirsher * 225460a25cdSYuval Mintz * Returns the number of optimized commands or a negative error code 226460a25cdSYuval Mintz * 227adfc5217SJeff Kirsher * Must run under exe_queue->lock 228adfc5217SJeff Kirsher */ 229adfc5217SJeff Kirsher exe_q_optimize optimize; 230adfc5217SJeff Kirsher 231adfc5217SJeff Kirsher /** 232adfc5217SJeff Kirsher * Run the next commands chunk (owner specific). 233adfc5217SJeff Kirsher */ 234adfc5217SJeff Kirsher exe_q_execute execute; 235adfc5217SJeff Kirsher 236adfc5217SJeff Kirsher /** 237adfc5217SJeff Kirsher * Return the exe_queue element containing the specific command 238adfc5217SJeff Kirsher * if any. Otherwise return NULL. 239adfc5217SJeff Kirsher */ 240adfc5217SJeff Kirsher exe_q_get get; 241adfc5217SJeff Kirsher }; 242adfc5217SJeff Kirsher /***************** Classification verbs: Set/Del MAC/VLAN/VLAN-MAC ************/ 243adfc5217SJeff Kirsher /* 24416a5fd92SYuval Mintz * Element in the VLAN_MAC registry list having all currently configured 245adfc5217SJeff Kirsher * rules. 246adfc5217SJeff Kirsher */ 247adfc5217SJeff Kirsher struct bnx2x_vlan_mac_registry_elem { 248adfc5217SJeff Kirsher struct list_head link; 249adfc5217SJeff Kirsher 25016a5fd92SYuval Mintz /* Used to store the cam offset used for the mac/vlan/vlan-mac. 251adfc5217SJeff Kirsher * Relevant for 57710 and 57711 only. VLANs and MACs share the 252adfc5217SJeff Kirsher * same CAM for these chips. 253adfc5217SJeff Kirsher */ 254adfc5217SJeff Kirsher int cam_offset; 255adfc5217SJeff Kirsher 256adfc5217SJeff Kirsher /* Needed for DEL and RESTORE flows */ 257adfc5217SJeff Kirsher unsigned long vlan_mac_flags; 258adfc5217SJeff Kirsher 259adfc5217SJeff Kirsher union bnx2x_classification_ramrod_data u; 260adfc5217SJeff Kirsher }; 261adfc5217SJeff Kirsher 262adfc5217SJeff Kirsher /* Bits representing VLAN_MAC commands specific flags */ 263adfc5217SJeff Kirsher enum { 264adfc5217SJeff Kirsher BNX2X_UC_LIST_MAC, 265adfc5217SJeff Kirsher BNX2X_ETH_MAC, 266adfc5217SJeff Kirsher BNX2X_ISCSI_ETH_MAC, 267adfc5217SJeff Kirsher BNX2X_NETQ_ETH_MAC, 268adfc5217SJeff Kirsher BNX2X_DONT_CONSUME_CAM_CREDIT, 269adfc5217SJeff Kirsher BNX2X_DONT_CONSUME_CAM_CREDIT_DEST, 270adfc5217SJeff Kirsher }; 271e8379c79SYuval Mintz /* When looking for matching filters, some flags are not interesting */ 272e8379c79SYuval Mintz #define BNX2X_VLAN_MAC_CMP_MASK (1 << BNX2X_UC_LIST_MAC | \ 273e8379c79SYuval Mintz 1 << BNX2X_ETH_MAC | \ 274e8379c79SYuval Mintz 1 << BNX2X_ISCSI_ETH_MAC | \ 275e8379c79SYuval Mintz 1 << BNX2X_NETQ_ETH_MAC) 276e8379c79SYuval Mintz #define BNX2X_VLAN_MAC_CMP_FLAGS(flags) \ 277e8379c79SYuval Mintz ((flags) & BNX2X_VLAN_MAC_CMP_MASK) 278adfc5217SJeff Kirsher 279adfc5217SJeff Kirsher struct bnx2x_vlan_mac_ramrod_params { 280adfc5217SJeff Kirsher /* Object to run the command from */ 281adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *vlan_mac_obj; 282adfc5217SJeff Kirsher 283adfc5217SJeff Kirsher /* General command flags: COMP_WAIT, etc. */ 284adfc5217SJeff Kirsher unsigned long ramrod_flags; 285adfc5217SJeff Kirsher 286adfc5217SJeff Kirsher /* Command specific configuration request */ 287adfc5217SJeff Kirsher struct bnx2x_vlan_mac_data user_req; 288adfc5217SJeff Kirsher }; 289adfc5217SJeff Kirsher 290adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj { 291adfc5217SJeff Kirsher struct bnx2x_raw_obj raw; 292adfc5217SJeff Kirsher 293adfc5217SJeff Kirsher /* Bookkeeping list: will prevent the addition of already existing 294adfc5217SJeff Kirsher * entries. 295adfc5217SJeff Kirsher */ 296adfc5217SJeff Kirsher struct list_head head; 2978b09be5fSYuval Mintz /* Implement a simple reader/writer lock on the head list. 2988b09be5fSYuval Mintz * all these fields should only be accessed under the exe_queue lock 2998b09be5fSYuval Mintz */ 3008b09be5fSYuval Mintz u8 head_reader; /* Num. of readers accessing head list */ 3018b09be5fSYuval Mintz bool head_exe_request; /* Pending execution request. */ 3028b09be5fSYuval Mintz unsigned long saved_ramrod_flags; /* Ramrods of pending execution */ 303adfc5217SJeff Kirsher 304adfc5217SJeff Kirsher /* TODO: Add it's initialization in the init functions */ 305adfc5217SJeff Kirsher struct bnx2x_exe_queue_obj exe_queue; 306adfc5217SJeff Kirsher 307adfc5217SJeff Kirsher /* MACs credit pool */ 308adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *macs_pool; 309adfc5217SJeff Kirsher 310adfc5217SJeff Kirsher /* VLANs credit pool */ 311adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *vlans_pool; 312adfc5217SJeff Kirsher 313adfc5217SJeff Kirsher /* RAMROD command to be used */ 314adfc5217SJeff Kirsher int ramrod_cmd; 315adfc5217SJeff Kirsher 316ed5162a0SAriel Elior /* copy first n elements onto preallocated buffer 317ed5162a0SAriel Elior * 318ed5162a0SAriel Elior * @param n number of elements to get 319ed5162a0SAriel Elior * @param buf buffer preallocated by caller into which elements 320ed5162a0SAriel Elior * will be copied. Note elements are 4-byte aligned 32116a5fd92SYuval Mintz * so buffer size must be able to accommodate the 322ed5162a0SAriel Elior * aligned elements. 323ed5162a0SAriel Elior * 324ed5162a0SAriel Elior * @return number of copied bytes 325ed5162a0SAriel Elior */ 3263ec9f9caSAriel Elior int (*get_n_elements)(struct bnx2x *bp, 3273ec9f9caSAriel Elior struct bnx2x_vlan_mac_obj *o, int n, u8 *base, 3283ec9f9caSAriel Elior u8 stride, u8 size); 329ed5162a0SAriel Elior 330adfc5217SJeff Kirsher /** 331adfc5217SJeff Kirsher * Checks if ADD-ramrod with the given params may be performed. 332adfc5217SJeff Kirsher * 333adfc5217SJeff Kirsher * @return zero if the element may be added 334adfc5217SJeff Kirsher */ 335adfc5217SJeff Kirsher 33651c1a580SMerav Sicron int (*check_add)(struct bnx2x *bp, 33751c1a580SMerav Sicron struct bnx2x_vlan_mac_obj *o, 338adfc5217SJeff Kirsher union bnx2x_classification_ramrod_data *data); 339adfc5217SJeff Kirsher 340adfc5217SJeff Kirsher /** 341adfc5217SJeff Kirsher * Checks if DEL-ramrod with the given params may be performed. 342adfc5217SJeff Kirsher * 343adfc5217SJeff Kirsher * @return true if the element may be deleted 344adfc5217SJeff Kirsher */ 345adfc5217SJeff Kirsher struct bnx2x_vlan_mac_registry_elem * 34651c1a580SMerav Sicron (*check_del)(struct bnx2x *bp, 34751c1a580SMerav Sicron struct bnx2x_vlan_mac_obj *o, 348adfc5217SJeff Kirsher union bnx2x_classification_ramrod_data *data); 349adfc5217SJeff Kirsher 350adfc5217SJeff Kirsher /** 351adfc5217SJeff Kirsher * Checks if DEL-ramrod with the given params may be performed. 352adfc5217SJeff Kirsher * 353adfc5217SJeff Kirsher * @return true if the element may be deleted 354adfc5217SJeff Kirsher */ 35551c1a580SMerav Sicron bool (*check_move)(struct bnx2x *bp, 35651c1a580SMerav Sicron struct bnx2x_vlan_mac_obj *src_o, 357adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *dst_o, 358adfc5217SJeff Kirsher union bnx2x_classification_ramrod_data *data); 359adfc5217SJeff Kirsher 360adfc5217SJeff Kirsher /** 361adfc5217SJeff Kirsher * Update the relevant credit object(s) (consume/return 362adfc5217SJeff Kirsher * correspondingly). 363adfc5217SJeff Kirsher */ 364adfc5217SJeff Kirsher bool (*get_credit)(struct bnx2x_vlan_mac_obj *o); 365adfc5217SJeff Kirsher bool (*put_credit)(struct bnx2x_vlan_mac_obj *o); 366adfc5217SJeff Kirsher bool (*get_cam_offset)(struct bnx2x_vlan_mac_obj *o, int *offset); 367adfc5217SJeff Kirsher bool (*put_cam_offset)(struct bnx2x_vlan_mac_obj *o, int offset); 368adfc5217SJeff Kirsher 369adfc5217SJeff Kirsher /** 370adfc5217SJeff Kirsher * Configures one rule in the ramrod data buffer. 371adfc5217SJeff Kirsher */ 372adfc5217SJeff Kirsher void (*set_one_rule)(struct bnx2x *bp, 373adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *o, 374adfc5217SJeff Kirsher struct bnx2x_exeq_elem *elem, int rule_idx, 375adfc5217SJeff Kirsher int cam_offset); 376adfc5217SJeff Kirsher 377adfc5217SJeff Kirsher /** 378adfc5217SJeff Kirsher * Delete all configured elements having the given 379adfc5217SJeff Kirsher * vlan_mac_flags specification. Assumes no pending for 380adfc5217SJeff Kirsher * execution commands. Will schedule all all currently 381adfc5217SJeff Kirsher * configured MACs/VLANs/VLAN-MACs matching the vlan_mac_flags 382adfc5217SJeff Kirsher * specification for deletion and will use the given 383adfc5217SJeff Kirsher * ramrod_flags for the last DEL operation. 384adfc5217SJeff Kirsher * 385adfc5217SJeff Kirsher * @param bp 386adfc5217SJeff Kirsher * @param o 387adfc5217SJeff Kirsher * @param ramrod_flags RAMROD_XX flags 388adfc5217SJeff Kirsher * 389adfc5217SJeff Kirsher * @return 0 if the last operation has completed successfully 390adfc5217SJeff Kirsher * and there are no more elements left, positive value 391adfc5217SJeff Kirsher * if there are pending for completion commands, 392adfc5217SJeff Kirsher * negative value in case of failure. 393adfc5217SJeff Kirsher */ 394adfc5217SJeff Kirsher int (*delete_all)(struct bnx2x *bp, 395adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *o, 396adfc5217SJeff Kirsher unsigned long *vlan_mac_flags, 397adfc5217SJeff Kirsher unsigned long *ramrod_flags); 398adfc5217SJeff Kirsher 399adfc5217SJeff Kirsher /** 400adfc5217SJeff Kirsher * Reconfigures the next MAC/VLAN/VLAN-MAC element from the previously 401adfc5217SJeff Kirsher * configured elements list. 402adfc5217SJeff Kirsher * 403adfc5217SJeff Kirsher * @param bp 404adfc5217SJeff Kirsher * @param p Command parameters (RAMROD_COMP_WAIT bit in 405adfc5217SJeff Kirsher * ramrod_flags is only taken into an account) 40616a5fd92SYuval Mintz * @param ppos a pointer to the cookie that should be given back in the 407adfc5217SJeff Kirsher * next call to make function handle the next element. If 408adfc5217SJeff Kirsher * *ppos is set to NULL it will restart the iterator. 409adfc5217SJeff Kirsher * If returned *ppos == NULL this means that the last 410adfc5217SJeff Kirsher * element has been handled. 411adfc5217SJeff Kirsher * 412adfc5217SJeff Kirsher * @return int 413adfc5217SJeff Kirsher */ 414adfc5217SJeff Kirsher int (*restore)(struct bnx2x *bp, 415adfc5217SJeff Kirsher struct bnx2x_vlan_mac_ramrod_params *p, 416adfc5217SJeff Kirsher struct bnx2x_vlan_mac_registry_elem **ppos); 417adfc5217SJeff Kirsher 418adfc5217SJeff Kirsher /** 41916a5fd92SYuval Mintz * Should be called on a completion arrival. 420adfc5217SJeff Kirsher * 421adfc5217SJeff Kirsher * @param bp 422adfc5217SJeff Kirsher * @param o 423adfc5217SJeff Kirsher * @param cqe Completion element we are handling 424adfc5217SJeff Kirsher * @param ramrod_flags if RAMROD_CONT is set the next bulk of 425adfc5217SJeff Kirsher * pending commands will be executed. 426adfc5217SJeff Kirsher * RAMROD_DRV_CLR_ONLY and RAMROD_RESTORE 427adfc5217SJeff Kirsher * may also be set if needed. 428adfc5217SJeff Kirsher * 429adfc5217SJeff Kirsher * @return 0 if there are neither pending nor waiting for 430adfc5217SJeff Kirsher * completion commands. Positive value if there are 431adfc5217SJeff Kirsher * pending for execution or for completion commands. 432adfc5217SJeff Kirsher * Negative value in case of an error (including an 433adfc5217SJeff Kirsher * error in the cqe). 434adfc5217SJeff Kirsher */ 435adfc5217SJeff Kirsher int (*complete)(struct bnx2x *bp, struct bnx2x_vlan_mac_obj *o, 436adfc5217SJeff Kirsher union event_ring_elem *cqe, 437adfc5217SJeff Kirsher unsigned long *ramrod_flags); 438adfc5217SJeff Kirsher 439adfc5217SJeff Kirsher /** 440adfc5217SJeff Kirsher * Wait for completion of all commands. Don't schedule new ones, 441adfc5217SJeff Kirsher * just wait. It assumes that the completion code will schedule 442adfc5217SJeff Kirsher * for new commands. 443adfc5217SJeff Kirsher */ 444adfc5217SJeff Kirsher int (*wait)(struct bnx2x *bp, struct bnx2x_vlan_mac_obj *o); 445adfc5217SJeff Kirsher }; 446adfc5217SJeff Kirsher 4470a52fd01SYuval Mintz enum { 4480a52fd01SYuval Mintz BNX2X_LLH_CAM_ISCSI_ETH_LINE = 0, 4490a52fd01SYuval Mintz BNX2X_LLH_CAM_ETH_LINE, 4500a52fd01SYuval Mintz BNX2X_LLH_CAM_MAX_PF_LINE = NIG_REG_LLH1_FUNC_MEM_SIZE / 2 4510a52fd01SYuval Mintz }; 4520a52fd01SYuval Mintz 453adfc5217SJeff Kirsher /** RX_MODE verbs:DROP_ALL/ACCEPT_ALL/ACCEPT_ALL_MULTI/ACCEPT_ALL_VLAN/NORMAL */ 454adfc5217SJeff Kirsher 45516a5fd92SYuval Mintz /* RX_MODE ramrod special flags: set in rx_mode_flags field in 456adfc5217SJeff Kirsher * a bnx2x_rx_mode_ramrod_params. 457adfc5217SJeff Kirsher */ 458adfc5217SJeff Kirsher enum { 459adfc5217SJeff Kirsher BNX2X_RX_MODE_FCOE_ETH, 460adfc5217SJeff Kirsher BNX2X_RX_MODE_ISCSI_ETH, 461adfc5217SJeff Kirsher }; 462adfc5217SJeff Kirsher 463adfc5217SJeff Kirsher enum { 464adfc5217SJeff Kirsher BNX2X_ACCEPT_UNICAST, 465adfc5217SJeff Kirsher BNX2X_ACCEPT_MULTICAST, 466adfc5217SJeff Kirsher BNX2X_ACCEPT_ALL_UNICAST, 467adfc5217SJeff Kirsher BNX2X_ACCEPT_ALL_MULTICAST, 468adfc5217SJeff Kirsher BNX2X_ACCEPT_BROADCAST, 469adfc5217SJeff Kirsher BNX2X_ACCEPT_UNMATCHED, 470adfc5217SJeff Kirsher BNX2X_ACCEPT_ANY_VLAN 471adfc5217SJeff Kirsher }; 472adfc5217SJeff Kirsher 473adfc5217SJeff Kirsher struct bnx2x_rx_mode_ramrod_params { 474adfc5217SJeff Kirsher struct bnx2x_rx_mode_obj *rx_mode_obj; 475adfc5217SJeff Kirsher unsigned long *pstate; 476adfc5217SJeff Kirsher int state; 477adfc5217SJeff Kirsher u8 cl_id; 478adfc5217SJeff Kirsher u32 cid; 479adfc5217SJeff Kirsher u8 func_id; 480adfc5217SJeff Kirsher unsigned long ramrod_flags; 481adfc5217SJeff Kirsher unsigned long rx_mode_flags; 482adfc5217SJeff Kirsher 48316a5fd92SYuval Mintz /* rdata is either a pointer to eth_filter_rules_ramrod_data(e2) or to 484adfc5217SJeff Kirsher * a tstorm_eth_mac_filter_config (e1x). 485adfc5217SJeff Kirsher */ 486adfc5217SJeff Kirsher void *rdata; 487adfc5217SJeff Kirsher dma_addr_t rdata_mapping; 488adfc5217SJeff Kirsher 489adfc5217SJeff Kirsher /* Rx mode settings */ 490adfc5217SJeff Kirsher unsigned long rx_accept_flags; 491adfc5217SJeff Kirsher 492adfc5217SJeff Kirsher /* internal switching settings */ 493adfc5217SJeff Kirsher unsigned long tx_accept_flags; 494adfc5217SJeff Kirsher }; 495adfc5217SJeff Kirsher 496adfc5217SJeff Kirsher struct bnx2x_rx_mode_obj { 497adfc5217SJeff Kirsher int (*config_rx_mode)(struct bnx2x *bp, 498adfc5217SJeff Kirsher struct bnx2x_rx_mode_ramrod_params *p); 499adfc5217SJeff Kirsher 500adfc5217SJeff Kirsher int (*wait_comp)(struct bnx2x *bp, 501adfc5217SJeff Kirsher struct bnx2x_rx_mode_ramrod_params *p); 502adfc5217SJeff Kirsher }; 503adfc5217SJeff Kirsher 504adfc5217SJeff Kirsher /********************** Set multicast group ***********************************/ 505adfc5217SJeff Kirsher 506adfc5217SJeff Kirsher struct bnx2x_mcast_list_elem { 507adfc5217SJeff Kirsher struct list_head link; 508adfc5217SJeff Kirsher u8 *mac; 509adfc5217SJeff Kirsher }; 510adfc5217SJeff Kirsher 511adfc5217SJeff Kirsher union bnx2x_mcast_config_data { 512adfc5217SJeff Kirsher u8 *mac; 513adfc5217SJeff Kirsher u8 bin; /* used in a RESTORE flow */ 514adfc5217SJeff Kirsher }; 515adfc5217SJeff Kirsher 516adfc5217SJeff Kirsher struct bnx2x_mcast_ramrod_params { 517adfc5217SJeff Kirsher struct bnx2x_mcast_obj *mcast_obj; 518adfc5217SJeff Kirsher 519adfc5217SJeff Kirsher /* Relevant options are RAMROD_COMP_WAIT and RAMROD_DRV_CLR_ONLY */ 520adfc5217SJeff Kirsher unsigned long ramrod_flags; 521adfc5217SJeff Kirsher 522adfc5217SJeff Kirsher struct list_head mcast_list; /* list of struct bnx2x_mcast_list_elem */ 523adfc5217SJeff Kirsher /** TODO: 524adfc5217SJeff Kirsher * - rename it to macs_num. 525adfc5217SJeff Kirsher * - Add a new command type for handling pending commands 526adfc5217SJeff Kirsher * (remove "zero semantics"). 527adfc5217SJeff Kirsher * 528adfc5217SJeff Kirsher * Length of mcast_list. If zero and ADD_CONT command - post 529adfc5217SJeff Kirsher * pending commands. 530adfc5217SJeff Kirsher */ 531adfc5217SJeff Kirsher int mcast_list_len; 532adfc5217SJeff Kirsher }; 533adfc5217SJeff Kirsher 53486564c3fSYuval Mintz enum bnx2x_mcast_cmd { 535adfc5217SJeff Kirsher BNX2X_MCAST_CMD_ADD, 536adfc5217SJeff Kirsher BNX2X_MCAST_CMD_CONT, 537adfc5217SJeff Kirsher BNX2X_MCAST_CMD_DEL, 538adfc5217SJeff Kirsher BNX2X_MCAST_CMD_RESTORE, 539adfc5217SJeff Kirsher }; 540adfc5217SJeff Kirsher 541adfc5217SJeff Kirsher struct bnx2x_mcast_obj { 542adfc5217SJeff Kirsher struct bnx2x_raw_obj raw; 543adfc5217SJeff Kirsher 544adfc5217SJeff Kirsher union { 545adfc5217SJeff Kirsher struct { 546adfc5217SJeff Kirsher #define BNX2X_MCAST_BINS_NUM 256 547adfc5217SJeff Kirsher #define BNX2X_MCAST_VEC_SZ (BNX2X_MCAST_BINS_NUM / 64) 548adfc5217SJeff Kirsher u64 vec[BNX2X_MCAST_VEC_SZ]; 549adfc5217SJeff Kirsher 550adfc5217SJeff Kirsher /** Number of BINs to clear. Should be updated 551adfc5217SJeff Kirsher * immediately when a command arrives in order to 552adfc5217SJeff Kirsher * properly create DEL commands. 553adfc5217SJeff Kirsher */ 554adfc5217SJeff Kirsher int num_bins_set; 555adfc5217SJeff Kirsher } aprox_match; 556adfc5217SJeff Kirsher 557adfc5217SJeff Kirsher struct { 558adfc5217SJeff Kirsher struct list_head macs; 559adfc5217SJeff Kirsher int num_macs_set; 560adfc5217SJeff Kirsher } exact_match; 561adfc5217SJeff Kirsher } registry; 562adfc5217SJeff Kirsher 563adfc5217SJeff Kirsher /* Pending commands */ 564adfc5217SJeff Kirsher struct list_head pending_cmds_head; 565adfc5217SJeff Kirsher 566adfc5217SJeff Kirsher /* A state that is set in raw.pstate, when there are pending commands */ 567adfc5217SJeff Kirsher int sched_state; 568adfc5217SJeff Kirsher 569adfc5217SJeff Kirsher /* Maximal number of mcast MACs configured in one command */ 570adfc5217SJeff Kirsher int max_cmd_len; 571adfc5217SJeff Kirsher 572adfc5217SJeff Kirsher /* Total number of currently pending MACs to configure: both 573adfc5217SJeff Kirsher * in the pending commands list and in the current command. 574adfc5217SJeff Kirsher */ 575adfc5217SJeff Kirsher int total_pending_num; 576adfc5217SJeff Kirsher 577adfc5217SJeff Kirsher u8 engine_id; 578adfc5217SJeff Kirsher 579adfc5217SJeff Kirsher /** 580adfc5217SJeff Kirsher * @param cmd command to execute (BNX2X_MCAST_CMD_X, see above) 581adfc5217SJeff Kirsher */ 582adfc5217SJeff Kirsher int (*config_mcast)(struct bnx2x *bp, 58386564c3fSYuval Mintz struct bnx2x_mcast_ramrod_params *p, 58486564c3fSYuval Mintz enum bnx2x_mcast_cmd cmd); 585adfc5217SJeff Kirsher 586adfc5217SJeff Kirsher /** 587adfc5217SJeff Kirsher * Fills the ramrod data during the RESTORE flow. 588adfc5217SJeff Kirsher * 589adfc5217SJeff Kirsher * @param bp 590adfc5217SJeff Kirsher * @param o 591adfc5217SJeff Kirsher * @param start_idx Registry index to start from 592adfc5217SJeff Kirsher * @param rdata_idx Index in the ramrod data to start from 593adfc5217SJeff Kirsher * 594adfc5217SJeff Kirsher * @return -1 if we handled the whole registry or index of the last 595adfc5217SJeff Kirsher * handled registry element. 596adfc5217SJeff Kirsher */ 597adfc5217SJeff Kirsher int (*hdl_restore)(struct bnx2x *bp, struct bnx2x_mcast_obj *o, 598adfc5217SJeff Kirsher int start_bin, int *rdata_idx); 599adfc5217SJeff Kirsher 600adfc5217SJeff Kirsher int (*enqueue_cmd)(struct bnx2x *bp, struct bnx2x_mcast_obj *o, 60186564c3fSYuval Mintz struct bnx2x_mcast_ramrod_params *p, 60286564c3fSYuval Mintz enum bnx2x_mcast_cmd cmd); 603adfc5217SJeff Kirsher 604adfc5217SJeff Kirsher void (*set_one_rule)(struct bnx2x *bp, 605adfc5217SJeff Kirsher struct bnx2x_mcast_obj *o, int idx, 60686564c3fSYuval Mintz union bnx2x_mcast_config_data *cfg_data, 60786564c3fSYuval Mintz enum bnx2x_mcast_cmd cmd); 608adfc5217SJeff Kirsher 609adfc5217SJeff Kirsher /** Checks if there are more mcast MACs to be set or a previous 610adfc5217SJeff Kirsher * command is still pending. 611adfc5217SJeff Kirsher */ 612adfc5217SJeff Kirsher bool (*check_pending)(struct bnx2x_mcast_obj *o); 613adfc5217SJeff Kirsher 614adfc5217SJeff Kirsher /** 615adfc5217SJeff Kirsher * Set/Clear/Check SCHEDULED state of the object 616adfc5217SJeff Kirsher */ 617adfc5217SJeff Kirsher void (*set_sched)(struct bnx2x_mcast_obj *o); 618adfc5217SJeff Kirsher void (*clear_sched)(struct bnx2x_mcast_obj *o); 619adfc5217SJeff Kirsher bool (*check_sched)(struct bnx2x_mcast_obj *o); 620adfc5217SJeff Kirsher 621adfc5217SJeff Kirsher /* Wait until all pending commands complete */ 622adfc5217SJeff Kirsher int (*wait_comp)(struct bnx2x *bp, struct bnx2x_mcast_obj *o); 623adfc5217SJeff Kirsher 624adfc5217SJeff Kirsher /** 625adfc5217SJeff Kirsher * Handle the internal object counters needed for proper 626adfc5217SJeff Kirsher * commands handling. Checks that the provided parameters are 627adfc5217SJeff Kirsher * feasible. 628adfc5217SJeff Kirsher */ 629adfc5217SJeff Kirsher int (*validate)(struct bnx2x *bp, 63086564c3fSYuval Mintz struct bnx2x_mcast_ramrod_params *p, 63186564c3fSYuval Mintz enum bnx2x_mcast_cmd cmd); 632adfc5217SJeff Kirsher 633adfc5217SJeff Kirsher /** 634adfc5217SJeff Kirsher * Restore the values of internal counters in case of a failure. 635adfc5217SJeff Kirsher */ 636adfc5217SJeff Kirsher void (*revert)(struct bnx2x *bp, 637adfc5217SJeff Kirsher struct bnx2x_mcast_ramrod_params *p, 638adfc5217SJeff Kirsher int old_num_bins); 639adfc5217SJeff Kirsher 640adfc5217SJeff Kirsher int (*get_registry_size)(struct bnx2x_mcast_obj *o); 641adfc5217SJeff Kirsher void (*set_registry_size)(struct bnx2x_mcast_obj *o, int n); 642adfc5217SJeff Kirsher }; 643adfc5217SJeff Kirsher 644adfc5217SJeff Kirsher /*************************** Credit handling **********************************/ 645adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj { 646adfc5217SJeff Kirsher 647adfc5217SJeff Kirsher /* Current amount of credit in the pool */ 648adfc5217SJeff Kirsher atomic_t credit; 649adfc5217SJeff Kirsher 650adfc5217SJeff Kirsher /* Maximum allowed credit. put() will check against it. */ 651adfc5217SJeff Kirsher int pool_sz; 652adfc5217SJeff Kirsher 65316a5fd92SYuval Mintz /* Allocate a pool table statically. 654adfc5217SJeff Kirsher * 65516a5fd92SYuval Mintz * Currently the maximum allowed size is MAX_MAC_CREDIT_E2(272) 656adfc5217SJeff Kirsher * 657adfc5217SJeff Kirsher * The set bit in the table will mean that the entry is available. 658adfc5217SJeff Kirsher */ 659adfc5217SJeff Kirsher #define BNX2X_POOL_VEC_SIZE (MAX_MAC_CREDIT_E2 / 64) 660adfc5217SJeff Kirsher u64 pool_mirror[BNX2X_POOL_VEC_SIZE]; 661adfc5217SJeff Kirsher 662adfc5217SJeff Kirsher /* Base pool offset (initialized differently */ 663adfc5217SJeff Kirsher int base_pool_offset; 664adfc5217SJeff Kirsher 665adfc5217SJeff Kirsher /** 666adfc5217SJeff Kirsher * Get the next free pool entry. 667adfc5217SJeff Kirsher * 668adfc5217SJeff Kirsher * @return true if there was a free entry in the pool 669adfc5217SJeff Kirsher */ 670adfc5217SJeff Kirsher bool (*get_entry)(struct bnx2x_credit_pool_obj *o, int *entry); 671adfc5217SJeff Kirsher 672adfc5217SJeff Kirsher /** 673adfc5217SJeff Kirsher * Return the entry back to the pool. 674adfc5217SJeff Kirsher * 675adfc5217SJeff Kirsher * @return true if entry is legal and has been successfully 676adfc5217SJeff Kirsher * returned to the pool. 677adfc5217SJeff Kirsher */ 678adfc5217SJeff Kirsher bool (*put_entry)(struct bnx2x_credit_pool_obj *o, int entry); 679adfc5217SJeff Kirsher 680adfc5217SJeff Kirsher /** 681adfc5217SJeff Kirsher * Get the requested amount of credit from the pool. 682adfc5217SJeff Kirsher * 683adfc5217SJeff Kirsher * @param cnt Amount of requested credit 684adfc5217SJeff Kirsher * @return true if the operation is successful 685adfc5217SJeff Kirsher */ 686adfc5217SJeff Kirsher bool (*get)(struct bnx2x_credit_pool_obj *o, int cnt); 687adfc5217SJeff Kirsher 688adfc5217SJeff Kirsher /** 689adfc5217SJeff Kirsher * Returns the credit to the pool. 690adfc5217SJeff Kirsher * 691adfc5217SJeff Kirsher * @param cnt Amount of credit to return 692adfc5217SJeff Kirsher * @return true if the operation is successful 693adfc5217SJeff Kirsher */ 694adfc5217SJeff Kirsher bool (*put)(struct bnx2x_credit_pool_obj *o, int cnt); 695adfc5217SJeff Kirsher 696adfc5217SJeff Kirsher /** 697adfc5217SJeff Kirsher * Reads the current amount of credit. 698adfc5217SJeff Kirsher */ 699adfc5217SJeff Kirsher int (*check)(struct bnx2x_credit_pool_obj *o); 700adfc5217SJeff Kirsher }; 701adfc5217SJeff Kirsher 702adfc5217SJeff Kirsher /*************************** RSS configuration ********************************/ 703adfc5217SJeff Kirsher enum { 704adfc5217SJeff Kirsher /* RSS_MODE bits are mutually exclusive */ 705adfc5217SJeff Kirsher BNX2X_RSS_MODE_DISABLED, 706adfc5217SJeff Kirsher BNX2X_RSS_MODE_REGULAR, 707adfc5217SJeff Kirsher 708adfc5217SJeff Kirsher BNX2X_RSS_SET_SRCH, /* Setup searcher, E1x specific flag */ 709adfc5217SJeff Kirsher 710adfc5217SJeff Kirsher BNX2X_RSS_IPV4, 711adfc5217SJeff Kirsher BNX2X_RSS_IPV4_TCP, 7125d317c6aSMerav Sicron BNX2X_RSS_IPV4_UDP, 713adfc5217SJeff Kirsher BNX2X_RSS_IPV6, 714adfc5217SJeff Kirsher BNX2X_RSS_IPV6_TCP, 7155d317c6aSMerav Sicron BNX2X_RSS_IPV6_UDP, 71628311f8eSYuval Mintz 71728311f8eSYuval Mintz BNX2X_RSS_IPV4_VXLAN, 71828311f8eSYuval Mintz BNX2X_RSS_IPV6_VXLAN, 71928311f8eSYuval Mintz BNX2X_RSS_TUNN_INNER_HDRS, 720adfc5217SJeff Kirsher }; 721adfc5217SJeff Kirsher 722adfc5217SJeff Kirsher struct bnx2x_config_rss_params { 723adfc5217SJeff Kirsher struct bnx2x_rss_config_obj *rss_obj; 724adfc5217SJeff Kirsher 725adfc5217SJeff Kirsher /* may have RAMROD_COMP_WAIT set only */ 726adfc5217SJeff Kirsher unsigned long ramrod_flags; 727adfc5217SJeff Kirsher 728adfc5217SJeff Kirsher /* BNX2X_RSS_X bits */ 729adfc5217SJeff Kirsher unsigned long rss_flags; 730adfc5217SJeff Kirsher 731adfc5217SJeff Kirsher /* Number hash bits to take into an account */ 732adfc5217SJeff Kirsher u8 rss_result_mask; 733adfc5217SJeff Kirsher 734adfc5217SJeff Kirsher /* Indirection table */ 735adfc5217SJeff Kirsher u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE]; 736adfc5217SJeff Kirsher 737adfc5217SJeff Kirsher /* RSS hash values */ 738adfc5217SJeff Kirsher u32 rss_key[10]; 739adfc5217SJeff Kirsher 740adfc5217SJeff Kirsher /* valid only iff BNX2X_RSS_UPDATE_TOE is set */ 741adfc5217SJeff Kirsher u16 toe_rss_bitmap; 742adfc5217SJeff Kirsher }; 743adfc5217SJeff Kirsher 744adfc5217SJeff Kirsher struct bnx2x_rss_config_obj { 745adfc5217SJeff Kirsher struct bnx2x_raw_obj raw; 746adfc5217SJeff Kirsher 747adfc5217SJeff Kirsher /* RSS engine to use */ 748adfc5217SJeff Kirsher u8 engine_id; 749adfc5217SJeff Kirsher 750adfc5217SJeff Kirsher /* Last configured indirection table */ 751adfc5217SJeff Kirsher u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE]; 752adfc5217SJeff Kirsher 7535d317c6aSMerav Sicron /* flags for enabling 4-tupple hash on UDP */ 7545d317c6aSMerav Sicron u8 udp_rss_v4; 7555d317c6aSMerav Sicron u8 udp_rss_v6; 7565d317c6aSMerav Sicron 757adfc5217SJeff Kirsher int (*config_rss)(struct bnx2x *bp, 758adfc5217SJeff Kirsher struct bnx2x_config_rss_params *p); 759adfc5217SJeff Kirsher }; 760adfc5217SJeff Kirsher 761adfc5217SJeff Kirsher /*********************** Queue state update ***********************************/ 762adfc5217SJeff Kirsher 763adfc5217SJeff Kirsher /* UPDATE command options */ 764adfc5217SJeff Kirsher enum { 765adfc5217SJeff Kirsher BNX2X_Q_UPDATE_IN_VLAN_REM, 766adfc5217SJeff Kirsher BNX2X_Q_UPDATE_IN_VLAN_REM_CHNG, 767adfc5217SJeff Kirsher BNX2X_Q_UPDATE_OUT_VLAN_REM, 768adfc5217SJeff Kirsher BNX2X_Q_UPDATE_OUT_VLAN_REM_CHNG, 769adfc5217SJeff Kirsher BNX2X_Q_UPDATE_ANTI_SPOOF, 770adfc5217SJeff Kirsher BNX2X_Q_UPDATE_ANTI_SPOOF_CHNG, 771adfc5217SJeff Kirsher BNX2X_Q_UPDATE_ACTIVATE, 772adfc5217SJeff Kirsher BNX2X_Q_UPDATE_ACTIVATE_CHNG, 773adfc5217SJeff Kirsher BNX2X_Q_UPDATE_DEF_VLAN_EN, 774adfc5217SJeff Kirsher BNX2X_Q_UPDATE_DEF_VLAN_EN_CHNG, 775adfc5217SJeff Kirsher BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG, 776c14db202SYuval Mintz BNX2X_Q_UPDATE_SILENT_VLAN_REM, 777c14db202SYuval Mintz BNX2X_Q_UPDATE_TX_SWITCHING_CHNG, 778eeed018cSMichal Kalderon BNX2X_Q_UPDATE_TX_SWITCHING, 779eeed018cSMichal Kalderon BNX2X_Q_UPDATE_PTP_PKTS_CHNG, 780eeed018cSMichal Kalderon BNX2X_Q_UPDATE_PTP_PKTS, 781adfc5217SJeff Kirsher }; 782adfc5217SJeff Kirsher 783adfc5217SJeff Kirsher /* Allowed Queue states */ 784adfc5217SJeff Kirsher enum bnx2x_q_state { 785adfc5217SJeff Kirsher BNX2X_Q_STATE_RESET, 786adfc5217SJeff Kirsher BNX2X_Q_STATE_INITIALIZED, 787adfc5217SJeff Kirsher BNX2X_Q_STATE_ACTIVE, 788adfc5217SJeff Kirsher BNX2X_Q_STATE_MULTI_COS, 789adfc5217SJeff Kirsher BNX2X_Q_STATE_MCOS_TERMINATED, 790adfc5217SJeff Kirsher BNX2X_Q_STATE_INACTIVE, 791adfc5217SJeff Kirsher BNX2X_Q_STATE_STOPPED, 792adfc5217SJeff Kirsher BNX2X_Q_STATE_TERMINATED, 793adfc5217SJeff Kirsher BNX2X_Q_STATE_FLRED, 794adfc5217SJeff Kirsher BNX2X_Q_STATE_MAX, 795adfc5217SJeff Kirsher }; 796adfc5217SJeff Kirsher 79767c431a5SAriel Elior /* Allowed Queue states */ 79867c431a5SAriel Elior enum bnx2x_q_logical_state { 79967c431a5SAriel Elior BNX2X_Q_LOGICAL_STATE_ACTIVE, 80067c431a5SAriel Elior BNX2X_Q_LOGICAL_STATE_STOPPED, 80167c431a5SAriel Elior }; 80267c431a5SAriel Elior 803adfc5217SJeff Kirsher /* Allowed commands */ 804adfc5217SJeff Kirsher enum bnx2x_queue_cmd { 805adfc5217SJeff Kirsher BNX2X_Q_CMD_INIT, 806adfc5217SJeff Kirsher BNX2X_Q_CMD_SETUP, 807adfc5217SJeff Kirsher BNX2X_Q_CMD_SETUP_TX_ONLY, 808adfc5217SJeff Kirsher BNX2X_Q_CMD_DEACTIVATE, 809adfc5217SJeff Kirsher BNX2X_Q_CMD_ACTIVATE, 810adfc5217SJeff Kirsher BNX2X_Q_CMD_UPDATE, 811adfc5217SJeff Kirsher BNX2X_Q_CMD_UPDATE_TPA, 812adfc5217SJeff Kirsher BNX2X_Q_CMD_HALT, 813adfc5217SJeff Kirsher BNX2X_Q_CMD_CFC_DEL, 814adfc5217SJeff Kirsher BNX2X_Q_CMD_TERMINATE, 815adfc5217SJeff Kirsher BNX2X_Q_CMD_EMPTY, 816adfc5217SJeff Kirsher BNX2X_Q_CMD_MAX, 817adfc5217SJeff Kirsher }; 818adfc5217SJeff Kirsher 819adfc5217SJeff Kirsher /* queue SETUP + INIT flags */ 820adfc5217SJeff Kirsher enum { 821adfc5217SJeff Kirsher BNX2X_Q_FLG_TPA, 822adfc5217SJeff Kirsher BNX2X_Q_FLG_TPA_IPV6, 823621b4d66SDmitry Kravkov BNX2X_Q_FLG_TPA_GRO, 824adfc5217SJeff Kirsher BNX2X_Q_FLG_STATS, 825adfc5217SJeff Kirsher BNX2X_Q_FLG_ZERO_STATS, 826adfc5217SJeff Kirsher BNX2X_Q_FLG_ACTIVE, 827adfc5217SJeff Kirsher BNX2X_Q_FLG_OV, 828adfc5217SJeff Kirsher BNX2X_Q_FLG_VLAN, 829adfc5217SJeff Kirsher BNX2X_Q_FLG_COS, 830adfc5217SJeff Kirsher BNX2X_Q_FLG_HC, 831adfc5217SJeff Kirsher BNX2X_Q_FLG_HC_EN, 832adfc5217SJeff Kirsher BNX2X_Q_FLG_DHC, 833adfc5217SJeff Kirsher BNX2X_Q_FLG_FCOE, 834adfc5217SJeff Kirsher BNX2X_Q_FLG_LEADING_RSS, 835adfc5217SJeff Kirsher BNX2X_Q_FLG_MCAST, 836adfc5217SJeff Kirsher BNX2X_Q_FLG_DEF_VLAN, 837adfc5217SJeff Kirsher BNX2X_Q_FLG_TX_SWITCH, 838adfc5217SJeff Kirsher BNX2X_Q_FLG_TX_SEC, 839adfc5217SJeff Kirsher BNX2X_Q_FLG_ANTI_SPOOF, 840a3348722SBarak Witkowski BNX2X_Q_FLG_SILENT_VLAN_REM, 84191226790SDmitry Kravkov BNX2X_Q_FLG_FORCE_DEFAULT_PRI, 842e42780b6SDmitry Kravkov BNX2X_Q_FLG_REFUSE_OUTBAND_VLAN, 843e287a75cSDmitry Kravkov BNX2X_Q_FLG_PCSUM_ON_PKT, 844e287a75cSDmitry Kravkov BNX2X_Q_FLG_TUN_INC_INNER_IP_ID 845adfc5217SJeff Kirsher }; 846adfc5217SJeff Kirsher 84716a5fd92SYuval Mintz /* Queue type options: queue type may be a combination of below. */ 848adfc5217SJeff Kirsher enum bnx2x_q_type { 849adfc5217SJeff Kirsher /** TODO: Consider moving both these flags into the init() 850adfc5217SJeff Kirsher * ramrod params. 851adfc5217SJeff Kirsher */ 852adfc5217SJeff Kirsher BNX2X_Q_TYPE_HAS_RX, 853adfc5217SJeff Kirsher BNX2X_Q_TYPE_HAS_TX, 854adfc5217SJeff Kirsher }; 855adfc5217SJeff Kirsher 856adfc5217SJeff Kirsher #define BNX2X_PRIMARY_CID_INDEX 0 8578d7b0278SAriel Elior #define BNX2X_MULTI_TX_COS_E1X 3 /* QM only */ 858adfc5217SJeff Kirsher #define BNX2X_MULTI_TX_COS_E2_E3A0 2 859adfc5217SJeff Kirsher #define BNX2X_MULTI_TX_COS_E3B0 3 8608d7b0278SAriel Elior #define BNX2X_MULTI_TX_COS 3 /* Maximum possible */ 861adfc5217SJeff Kirsher 8623ec9f9caSAriel Elior #define MAC_PAD (ALIGN(ETH_ALEN, sizeof(u32)) - ETH_ALEN) 863eeed018cSMichal Kalderon /* DMAE channel to be used by FW for timesync workaroun. A driver that sends 864eeed018cSMichal Kalderon * timesync-related ramrods must not use this DMAE command ID. 865eeed018cSMichal Kalderon */ 866eeed018cSMichal Kalderon #define FW_DMAE_CMD_ID 6 867adfc5217SJeff Kirsher 868adfc5217SJeff Kirsher struct bnx2x_queue_init_params { 869adfc5217SJeff Kirsher struct { 870adfc5217SJeff Kirsher unsigned long flags; 871adfc5217SJeff Kirsher u16 hc_rate; 872adfc5217SJeff Kirsher u8 fw_sb_id; 873adfc5217SJeff Kirsher u8 sb_cq_index; 874adfc5217SJeff Kirsher } tx; 875adfc5217SJeff Kirsher 876adfc5217SJeff Kirsher struct { 877adfc5217SJeff Kirsher unsigned long flags; 878adfc5217SJeff Kirsher u16 hc_rate; 879adfc5217SJeff Kirsher u8 fw_sb_id; 880adfc5217SJeff Kirsher u8 sb_cq_index; 881adfc5217SJeff Kirsher } rx; 882adfc5217SJeff Kirsher 883adfc5217SJeff Kirsher /* CID context in the host memory */ 884adfc5217SJeff Kirsher struct eth_context *cxts[BNX2X_MULTI_TX_COS]; 885adfc5217SJeff Kirsher 886adfc5217SJeff Kirsher /* maximum number of cos supported by hardware */ 887adfc5217SJeff Kirsher u8 max_cos; 888adfc5217SJeff Kirsher }; 889adfc5217SJeff Kirsher 890adfc5217SJeff Kirsher struct bnx2x_queue_terminate_params { 891adfc5217SJeff Kirsher /* index within the tx_only cids of this queue object */ 892adfc5217SJeff Kirsher u8 cid_index; 893adfc5217SJeff Kirsher }; 894adfc5217SJeff Kirsher 895adfc5217SJeff Kirsher struct bnx2x_queue_cfc_del_params { 896adfc5217SJeff Kirsher /* index within the tx_only cids of this queue object */ 897adfc5217SJeff Kirsher u8 cid_index; 898adfc5217SJeff Kirsher }; 899adfc5217SJeff Kirsher 900adfc5217SJeff Kirsher struct bnx2x_queue_update_params { 901adfc5217SJeff Kirsher unsigned long update_flags; /* BNX2X_Q_UPDATE_XX bits */ 902adfc5217SJeff Kirsher u16 def_vlan; 903adfc5217SJeff Kirsher u16 silent_removal_value; 904adfc5217SJeff Kirsher u16 silent_removal_mask; 905adfc5217SJeff Kirsher /* index within the tx_only cids of this queue object */ 906adfc5217SJeff Kirsher u8 cid_index; 907adfc5217SJeff Kirsher }; 908adfc5217SJeff Kirsher 90914a94ebdSMichal Kalderon struct bnx2x_queue_update_tpa_params { 91014a94ebdSMichal Kalderon dma_addr_t sge_map; 91114a94ebdSMichal Kalderon u8 update_ipv4; 91214a94ebdSMichal Kalderon u8 update_ipv6; 91314a94ebdSMichal Kalderon u8 max_tpa_queues; 91414a94ebdSMichal Kalderon u8 max_sges_pkt; 91514a94ebdSMichal Kalderon u8 complete_on_both_clients; 91614a94ebdSMichal Kalderon u8 dont_verify_thr; 91714a94ebdSMichal Kalderon u8 tpa_mode; 91814a94ebdSMichal Kalderon u8 _pad; 91914a94ebdSMichal Kalderon 92014a94ebdSMichal Kalderon u16 sge_buff_sz; 92114a94ebdSMichal Kalderon u16 max_agg_sz; 92214a94ebdSMichal Kalderon 92314a94ebdSMichal Kalderon u16 sge_pause_thr_low; 92414a94ebdSMichal Kalderon u16 sge_pause_thr_high; 92514a94ebdSMichal Kalderon }; 92614a94ebdSMichal Kalderon 927adfc5217SJeff Kirsher struct rxq_pause_params { 928adfc5217SJeff Kirsher u16 bd_th_lo; 929adfc5217SJeff Kirsher u16 bd_th_hi; 930adfc5217SJeff Kirsher u16 rcq_th_lo; 931adfc5217SJeff Kirsher u16 rcq_th_hi; 932adfc5217SJeff Kirsher u16 sge_th_lo; /* valid iff BNX2X_Q_FLG_TPA */ 933adfc5217SJeff Kirsher u16 sge_th_hi; /* valid iff BNX2X_Q_FLG_TPA */ 934adfc5217SJeff Kirsher u16 pri_map; 935adfc5217SJeff Kirsher }; 936adfc5217SJeff Kirsher 937adfc5217SJeff Kirsher /* general */ 938adfc5217SJeff Kirsher struct bnx2x_general_setup_params { 939adfc5217SJeff Kirsher /* valid iff BNX2X_Q_FLG_STATS */ 940adfc5217SJeff Kirsher u8 stat_id; 941adfc5217SJeff Kirsher 942adfc5217SJeff Kirsher u8 spcl_id; 943adfc5217SJeff Kirsher u16 mtu; 944adfc5217SJeff Kirsher u8 cos; 94502dc4025SYuval Mintz 94602dc4025SYuval Mintz u8 fp_hsi; 947adfc5217SJeff Kirsher }; 948adfc5217SJeff Kirsher 949adfc5217SJeff Kirsher struct bnx2x_rxq_setup_params { 950adfc5217SJeff Kirsher /* dma */ 951adfc5217SJeff Kirsher dma_addr_t dscr_map; 952adfc5217SJeff Kirsher dma_addr_t sge_map; 953adfc5217SJeff Kirsher dma_addr_t rcq_map; 954adfc5217SJeff Kirsher dma_addr_t rcq_np_map; 955adfc5217SJeff Kirsher 956adfc5217SJeff Kirsher u16 drop_flags; 957adfc5217SJeff Kirsher u16 buf_sz; 958adfc5217SJeff Kirsher u8 fw_sb_id; 959adfc5217SJeff Kirsher u8 cl_qzone_id; 960adfc5217SJeff Kirsher 961adfc5217SJeff Kirsher /* valid iff BNX2X_Q_FLG_TPA */ 962adfc5217SJeff Kirsher u16 tpa_agg_sz; 963adfc5217SJeff Kirsher u16 sge_buf_sz; 964adfc5217SJeff Kirsher u8 max_sges_pkt; 965adfc5217SJeff Kirsher u8 max_tpa_queues; 966adfc5217SJeff Kirsher u8 rss_engine_id; 967adfc5217SJeff Kirsher 968259afa1fSYuval Mintz /* valid iff BNX2X_Q_FLG_MCAST */ 969259afa1fSYuval Mintz u8 mcast_engine_id; 970259afa1fSYuval Mintz 971adfc5217SJeff Kirsher u8 cache_line_log; 972adfc5217SJeff Kirsher 973adfc5217SJeff Kirsher u8 sb_cq_index; 974adfc5217SJeff Kirsher 975adfc5217SJeff Kirsher /* valid iff BXN2X_Q_FLG_SILENT_VLAN_REM */ 976adfc5217SJeff Kirsher u16 silent_removal_value; 977adfc5217SJeff Kirsher u16 silent_removal_mask; 978adfc5217SJeff Kirsher }; 979adfc5217SJeff Kirsher 980adfc5217SJeff Kirsher struct bnx2x_txq_setup_params { 981adfc5217SJeff Kirsher /* dma */ 982adfc5217SJeff Kirsher dma_addr_t dscr_map; 983adfc5217SJeff Kirsher 984adfc5217SJeff Kirsher u8 fw_sb_id; 985adfc5217SJeff Kirsher u8 sb_cq_index; 986adfc5217SJeff Kirsher u8 cos; /* valid iff BNX2X_Q_FLG_COS */ 987adfc5217SJeff Kirsher u16 traffic_type; 988adfc5217SJeff Kirsher /* equals to the leading rss client id, used for TX classification*/ 989adfc5217SJeff Kirsher u8 tss_leading_cl_id; 990adfc5217SJeff Kirsher 991adfc5217SJeff Kirsher /* valid iff BNX2X_Q_FLG_DEF_VLAN */ 992adfc5217SJeff Kirsher u16 default_vlan; 993adfc5217SJeff Kirsher }; 994adfc5217SJeff Kirsher 995adfc5217SJeff Kirsher struct bnx2x_queue_setup_params { 996adfc5217SJeff Kirsher struct bnx2x_general_setup_params gen_params; 997adfc5217SJeff Kirsher struct bnx2x_txq_setup_params txq_params; 998adfc5217SJeff Kirsher struct bnx2x_rxq_setup_params rxq_params; 999adfc5217SJeff Kirsher struct rxq_pause_params pause_params; 1000adfc5217SJeff Kirsher unsigned long flags; 1001adfc5217SJeff Kirsher }; 1002adfc5217SJeff Kirsher 1003adfc5217SJeff Kirsher struct bnx2x_queue_setup_tx_only_params { 1004adfc5217SJeff Kirsher struct bnx2x_general_setup_params gen_params; 1005adfc5217SJeff Kirsher struct bnx2x_txq_setup_params txq_params; 1006adfc5217SJeff Kirsher unsigned long flags; 1007adfc5217SJeff Kirsher /* index within the tx_only cids of this queue object */ 1008adfc5217SJeff Kirsher u8 cid_index; 1009adfc5217SJeff Kirsher }; 1010adfc5217SJeff Kirsher 1011adfc5217SJeff Kirsher struct bnx2x_queue_state_params { 1012adfc5217SJeff Kirsher struct bnx2x_queue_sp_obj *q_obj; 1013adfc5217SJeff Kirsher 1014adfc5217SJeff Kirsher /* Current command */ 1015adfc5217SJeff Kirsher enum bnx2x_queue_cmd cmd; 1016adfc5217SJeff Kirsher 1017adfc5217SJeff Kirsher /* may have RAMROD_COMP_WAIT set only */ 1018adfc5217SJeff Kirsher unsigned long ramrod_flags; 1019adfc5217SJeff Kirsher 1020adfc5217SJeff Kirsher /* Params according to the current command */ 1021adfc5217SJeff Kirsher union { 1022adfc5217SJeff Kirsher struct bnx2x_queue_update_params update; 102314a94ebdSMichal Kalderon struct bnx2x_queue_update_tpa_params update_tpa; 1024adfc5217SJeff Kirsher struct bnx2x_queue_setup_params setup; 1025adfc5217SJeff Kirsher struct bnx2x_queue_init_params init; 1026adfc5217SJeff Kirsher struct bnx2x_queue_setup_tx_only_params tx_only; 1027adfc5217SJeff Kirsher struct bnx2x_queue_terminate_params terminate; 1028adfc5217SJeff Kirsher struct bnx2x_queue_cfc_del_params cfc_del; 1029adfc5217SJeff Kirsher } params; 1030adfc5217SJeff Kirsher }; 1031adfc5217SJeff Kirsher 1032a3348722SBarak Witkowski struct bnx2x_viflist_params { 1033a3348722SBarak Witkowski u8 echo_res; 1034a3348722SBarak Witkowski u8 func_bit_map_res; 1035a3348722SBarak Witkowski }; 1036a3348722SBarak Witkowski 1037adfc5217SJeff Kirsher struct bnx2x_queue_sp_obj { 1038adfc5217SJeff Kirsher u32 cids[BNX2X_MULTI_TX_COS]; 1039adfc5217SJeff Kirsher u8 cl_id; 1040adfc5217SJeff Kirsher u8 func_id; 1041adfc5217SJeff Kirsher 104216a5fd92SYuval Mintz /* number of traffic classes supported by queue. 104316a5fd92SYuval Mintz * The primary connection of the queue supports the first traffic 104416a5fd92SYuval Mintz * class. Any further traffic class is supported by a tx-only 1045adfc5217SJeff Kirsher * connection. 1046adfc5217SJeff Kirsher * 1047adfc5217SJeff Kirsher * Therefore max_cos is also a number of valid entries in the cids 1048adfc5217SJeff Kirsher * array. 1049adfc5217SJeff Kirsher */ 1050adfc5217SJeff Kirsher u8 max_cos; 1051adfc5217SJeff Kirsher u8 num_tx_only, next_tx_only; 1052adfc5217SJeff Kirsher 1053adfc5217SJeff Kirsher enum bnx2x_q_state state, next_state; 1054adfc5217SJeff Kirsher 1055adfc5217SJeff Kirsher /* bits from enum bnx2x_q_type */ 1056adfc5217SJeff Kirsher unsigned long type; 1057adfc5217SJeff Kirsher 1058adfc5217SJeff Kirsher /* BNX2X_Q_CMD_XX bits. This object implements "one 1059adfc5217SJeff Kirsher * pending" paradigm but for debug and tracing purposes it's 106016a5fd92SYuval Mintz * more convenient to have different bits for different 1061adfc5217SJeff Kirsher * commands. 1062adfc5217SJeff Kirsher */ 1063adfc5217SJeff Kirsher unsigned long pending; 1064adfc5217SJeff Kirsher 1065adfc5217SJeff Kirsher /* Buffer to use as a ramrod data and its mapping */ 1066adfc5217SJeff Kirsher void *rdata; 1067adfc5217SJeff Kirsher dma_addr_t rdata_mapping; 1068adfc5217SJeff Kirsher 1069adfc5217SJeff Kirsher /** 1070adfc5217SJeff Kirsher * Performs one state change according to the given parameters. 1071adfc5217SJeff Kirsher * 1072adfc5217SJeff Kirsher * @return 0 in case of success and negative value otherwise. 1073adfc5217SJeff Kirsher */ 1074adfc5217SJeff Kirsher int (*send_cmd)(struct bnx2x *bp, 1075adfc5217SJeff Kirsher struct bnx2x_queue_state_params *params); 1076adfc5217SJeff Kirsher 1077adfc5217SJeff Kirsher /** 1078adfc5217SJeff Kirsher * Sets the pending bit according to the requested transition. 1079adfc5217SJeff Kirsher */ 1080adfc5217SJeff Kirsher int (*set_pending)(struct bnx2x_queue_sp_obj *o, 1081adfc5217SJeff Kirsher struct bnx2x_queue_state_params *params); 1082adfc5217SJeff Kirsher 1083adfc5217SJeff Kirsher /** 1084adfc5217SJeff Kirsher * Checks that the requested state transition is legal. 1085adfc5217SJeff Kirsher */ 1086adfc5217SJeff Kirsher int (*check_transition)(struct bnx2x *bp, 1087adfc5217SJeff Kirsher struct bnx2x_queue_sp_obj *o, 1088adfc5217SJeff Kirsher struct bnx2x_queue_state_params *params); 1089adfc5217SJeff Kirsher 1090adfc5217SJeff Kirsher /** 1091adfc5217SJeff Kirsher * Completes the pending command. 1092adfc5217SJeff Kirsher */ 1093adfc5217SJeff Kirsher int (*complete_cmd)(struct bnx2x *bp, 1094adfc5217SJeff Kirsher struct bnx2x_queue_sp_obj *o, 1095adfc5217SJeff Kirsher enum bnx2x_queue_cmd); 1096adfc5217SJeff Kirsher 1097adfc5217SJeff Kirsher int (*wait_comp)(struct bnx2x *bp, 1098adfc5217SJeff Kirsher struct bnx2x_queue_sp_obj *o, 1099adfc5217SJeff Kirsher enum bnx2x_queue_cmd cmd); 1100adfc5217SJeff Kirsher }; 1101adfc5217SJeff Kirsher 1102adfc5217SJeff Kirsher /********************** Function state update *********************************/ 1103e42780b6SDmitry Kravkov 1104e42780b6SDmitry Kravkov /* UPDATE command options */ 1105e42780b6SDmitry Kravkov enum { 1106e42780b6SDmitry Kravkov BNX2X_F_UPDATE_TX_SWITCH_SUSPEND_CHNG, 1107e42780b6SDmitry Kravkov BNX2X_F_UPDATE_TX_SWITCH_SUSPEND, 11087609647eSYuval Mintz BNX2X_F_UPDATE_SD_VLAN_TAG_CHNG, 11097609647eSYuval Mintz BNX2X_F_UPDATE_SD_VLAN_ETH_TYPE_CHNG, 11107609647eSYuval Mintz BNX2X_F_UPDATE_VLAN_FORCE_PRIO_CHNG, 11117609647eSYuval Mintz BNX2X_F_UPDATE_VLAN_FORCE_PRIO_FLAG, 1112e42780b6SDmitry Kravkov BNX2X_F_UPDATE_TUNNEL_CFG_CHNG, 111328311f8eSYuval Mintz BNX2X_F_UPDATE_TUNNEL_INNER_CLSS_L2GRE, 111428311f8eSYuval Mintz BNX2X_F_UPDATE_TUNNEL_INNER_CLSS_VXLAN, 111528311f8eSYuval Mintz BNX2X_F_UPDATE_TUNNEL_INNER_CLSS_L2GENEVE, 111628311f8eSYuval Mintz BNX2X_F_UPDATE_TUNNEL_INNER_RSS, 1117e42780b6SDmitry Kravkov }; 1118e42780b6SDmitry Kravkov 1119adfc5217SJeff Kirsher /* Allowed Function states */ 1120adfc5217SJeff Kirsher enum bnx2x_func_state { 1121adfc5217SJeff Kirsher BNX2X_F_STATE_RESET, 1122adfc5217SJeff Kirsher BNX2X_F_STATE_INITIALIZED, 1123adfc5217SJeff Kirsher BNX2X_F_STATE_STARTED, 1124adfc5217SJeff Kirsher BNX2X_F_STATE_TX_STOPPED, 1125adfc5217SJeff Kirsher BNX2X_F_STATE_MAX, 1126adfc5217SJeff Kirsher }; 1127adfc5217SJeff Kirsher 1128adfc5217SJeff Kirsher /* Allowed Function commands */ 1129adfc5217SJeff Kirsher enum bnx2x_func_cmd { 1130adfc5217SJeff Kirsher BNX2X_F_CMD_HW_INIT, 1131adfc5217SJeff Kirsher BNX2X_F_CMD_START, 1132adfc5217SJeff Kirsher BNX2X_F_CMD_STOP, 1133adfc5217SJeff Kirsher BNX2X_F_CMD_HW_RESET, 1134a3348722SBarak Witkowski BNX2X_F_CMD_AFEX_UPDATE, 1135a3348722SBarak Witkowski BNX2X_F_CMD_AFEX_VIFLISTS, 1136adfc5217SJeff Kirsher BNX2X_F_CMD_TX_STOP, 1137adfc5217SJeff Kirsher BNX2X_F_CMD_TX_START, 113855c11941SMerav Sicron BNX2X_F_CMD_SWITCH_UPDATE, 1139eeed018cSMichal Kalderon BNX2X_F_CMD_SET_TIMESYNC, 1140adfc5217SJeff Kirsher BNX2X_F_CMD_MAX, 1141adfc5217SJeff Kirsher }; 1142adfc5217SJeff Kirsher 1143adfc5217SJeff Kirsher struct bnx2x_func_hw_init_params { 1144adfc5217SJeff Kirsher /* A load phase returned by MCP. 1145adfc5217SJeff Kirsher * 1146adfc5217SJeff Kirsher * May be: 1147adfc5217SJeff Kirsher * FW_MSG_CODE_DRV_LOAD_COMMON_CHIP 1148adfc5217SJeff Kirsher * FW_MSG_CODE_DRV_LOAD_COMMON 1149adfc5217SJeff Kirsher * FW_MSG_CODE_DRV_LOAD_PORT 1150adfc5217SJeff Kirsher * FW_MSG_CODE_DRV_LOAD_FUNCTION 1151adfc5217SJeff Kirsher */ 1152adfc5217SJeff Kirsher u32 load_phase; 1153adfc5217SJeff Kirsher }; 1154adfc5217SJeff Kirsher 1155adfc5217SJeff Kirsher struct bnx2x_func_hw_reset_params { 1156adfc5217SJeff Kirsher /* A load phase returned by MCP. 1157adfc5217SJeff Kirsher * 1158adfc5217SJeff Kirsher * May be: 1159adfc5217SJeff Kirsher * FW_MSG_CODE_DRV_LOAD_COMMON_CHIP 1160adfc5217SJeff Kirsher * FW_MSG_CODE_DRV_LOAD_COMMON 1161adfc5217SJeff Kirsher * FW_MSG_CODE_DRV_LOAD_PORT 1162adfc5217SJeff Kirsher * FW_MSG_CODE_DRV_LOAD_FUNCTION 1163adfc5217SJeff Kirsher */ 1164adfc5217SJeff Kirsher u32 reset_phase; 1165adfc5217SJeff Kirsher }; 1166adfc5217SJeff Kirsher 1167adfc5217SJeff Kirsher struct bnx2x_func_start_params { 1168adfc5217SJeff Kirsher /* Multi Function mode: 1169adfc5217SJeff Kirsher * - Single Function 1170adfc5217SJeff Kirsher * - Switch Dependent 1171adfc5217SJeff Kirsher * - Switch Independent 1172adfc5217SJeff Kirsher */ 1173adfc5217SJeff Kirsher u16 mf_mode; 1174adfc5217SJeff Kirsher 1175adfc5217SJeff Kirsher /* Switch Dependent mode outer VLAN tag */ 1176adfc5217SJeff Kirsher u16 sd_vlan_tag; 1177adfc5217SJeff Kirsher 1178adfc5217SJeff Kirsher /* Function cos mode */ 1179adfc5217SJeff Kirsher u8 network_cos_mode; 11801bc277f7SDmitry Kravkov 118128311f8eSYuval Mintz /* UDP dest port for VXLAN */ 118228311f8eSYuval Mintz u16 vxlan_dst_port; 11831bc277f7SDmitry Kravkov 118428311f8eSYuval Mintz /* UDP dest port for Geneve */ 118528311f8eSYuval Mintz u16 geneve_dst_port; 11861bc277f7SDmitry Kravkov 118728311f8eSYuval Mintz /* Enable inner Rx classifications for L2GRE packets */ 118828311f8eSYuval Mintz u8 inner_clss_l2gre; 1189e42780b6SDmitry Kravkov 119028311f8eSYuval Mintz /* Enable inner Rx classifications for L2-Geneve packets */ 119128311f8eSYuval Mintz u8 inner_clss_l2geneve; 119228311f8eSYuval Mintz 119328311f8eSYuval Mintz /* Enable inner Rx classification for vxlan packets */ 119428311f8eSYuval Mintz u8 inner_clss_vxlan; 119528311f8eSYuval Mintz 119628311f8eSYuval Mintz /* Enable RSS according to inner header */ 119728311f8eSYuval Mintz u8 inner_rss; 11987609647eSYuval Mintz 11997609647eSYuval Mintz /* Allows accepting of packets failing MF classification, possibly 12007609647eSYuval Mintz * only matching a given ethertype 12017609647eSYuval Mintz */ 12027609647eSYuval Mintz u8 class_fail; 12037609647eSYuval Mintz u16 class_fail_ethtype; 12047609647eSYuval Mintz 12057609647eSYuval Mintz /* Override priority of output packets */ 12067609647eSYuval Mintz u8 sd_vlan_force_pri; 12077609647eSYuval Mintz u8 sd_vlan_force_pri_val; 12087609647eSYuval Mintz 12097609647eSYuval Mintz /* Replace vlan's ethertype */ 12107609647eSYuval Mintz u16 sd_vlan_eth_type; 12117609647eSYuval Mintz 12127609647eSYuval Mintz /* Prevent inner vlans from being added by FW */ 12137609647eSYuval Mintz u8 no_added_tags; 121428311f8eSYuval Mintz 121528311f8eSYuval Mintz /* Inner-to-Outer vlan priority mapping */ 121628311f8eSYuval Mintz u8 c2s_pri[MAX_VLAN_PRIORITIES]; 121728311f8eSYuval Mintz u8 c2s_pri_default; 121828311f8eSYuval Mintz u8 c2s_pri_valid; 1219adfc5217SJeff Kirsher }; 1220adfc5217SJeff Kirsher 122155c11941SMerav Sicron struct bnx2x_func_switch_update_params { 1222e42780b6SDmitry Kravkov unsigned long changes; /* BNX2X_F_UPDATE_XX bits */ 12237609647eSYuval Mintz u16 vlan; 12247609647eSYuval Mintz u16 vlan_eth_type; 12257609647eSYuval Mintz u8 vlan_force_prio; 122628311f8eSYuval Mintz u16 vxlan_dst_port; 122728311f8eSYuval Mintz u16 geneve_dst_port; 122855c11941SMerav Sicron }; 122955c11941SMerav Sicron 1230a3348722SBarak Witkowski struct bnx2x_func_afex_update_params { 1231a3348722SBarak Witkowski u16 vif_id; 1232a3348722SBarak Witkowski u16 afex_default_vlan; 1233a3348722SBarak Witkowski u8 allowed_priorities; 1234a3348722SBarak Witkowski }; 1235a3348722SBarak Witkowski 1236a3348722SBarak Witkowski struct bnx2x_func_afex_viflists_params { 1237a3348722SBarak Witkowski u16 vif_list_index; 1238a3348722SBarak Witkowski u8 func_bit_map; 1239a3348722SBarak Witkowski u8 afex_vif_list_command; 1240a3348722SBarak Witkowski u8 func_to_clear; 1241a3348722SBarak Witkowski }; 1242eeed018cSMichal Kalderon 1243adfc5217SJeff Kirsher struct bnx2x_func_tx_start_params { 1244adfc5217SJeff Kirsher struct priority_cos traffic_type_to_priority_cos[MAX_TRAFFIC_TYPES]; 1245adfc5217SJeff Kirsher u8 dcb_enabled; 1246adfc5217SJeff Kirsher u8 dcb_version; 1247adfc5217SJeff Kirsher u8 dont_add_pri_0_en; 124828311f8eSYuval Mintz u8 dcb_outer_pri[MAX_TRAFFIC_TYPES]; 1249adfc5217SJeff Kirsher }; 1250adfc5217SJeff Kirsher 1251eeed018cSMichal Kalderon struct bnx2x_func_set_timesync_params { 1252eeed018cSMichal Kalderon /* Reset, set or keep the current drift value */ 1253eeed018cSMichal Kalderon u8 drift_adjust_cmd; 1254eeed018cSMichal Kalderon 1255eeed018cSMichal Kalderon /* Dec, inc or keep the current offset */ 1256eeed018cSMichal Kalderon u8 offset_cmd; 1257eeed018cSMichal Kalderon 1258eeed018cSMichal Kalderon /* Drift value direction */ 1259eeed018cSMichal Kalderon u8 add_sub_drift_adjust_value; 1260eeed018cSMichal Kalderon 1261eeed018cSMichal Kalderon /* Drift, period and offset values to be used according to the commands 1262eeed018cSMichal Kalderon * above. 1263eeed018cSMichal Kalderon */ 1264eeed018cSMichal Kalderon u8 drift_adjust_value; 1265eeed018cSMichal Kalderon u32 drift_adjust_period; 1266eeed018cSMichal Kalderon u64 offset_delta; 1267eeed018cSMichal Kalderon }; 1268eeed018cSMichal Kalderon 1269adfc5217SJeff Kirsher struct bnx2x_func_state_params { 1270adfc5217SJeff Kirsher struct bnx2x_func_sp_obj *f_obj; 1271adfc5217SJeff Kirsher 1272adfc5217SJeff Kirsher /* Current command */ 1273adfc5217SJeff Kirsher enum bnx2x_func_cmd cmd; 1274adfc5217SJeff Kirsher 1275adfc5217SJeff Kirsher /* may have RAMROD_COMP_WAIT set only */ 1276adfc5217SJeff Kirsher unsigned long ramrod_flags; 1277adfc5217SJeff Kirsher 1278adfc5217SJeff Kirsher /* Params according to the current command */ 1279adfc5217SJeff Kirsher union { 1280adfc5217SJeff Kirsher struct bnx2x_func_hw_init_params hw_init; 1281adfc5217SJeff Kirsher struct bnx2x_func_hw_reset_params hw_reset; 1282adfc5217SJeff Kirsher struct bnx2x_func_start_params start; 128355c11941SMerav Sicron struct bnx2x_func_switch_update_params switch_update; 1284a3348722SBarak Witkowski struct bnx2x_func_afex_update_params afex_update; 1285a3348722SBarak Witkowski struct bnx2x_func_afex_viflists_params afex_viflists; 1286adfc5217SJeff Kirsher struct bnx2x_func_tx_start_params tx_start; 1287eeed018cSMichal Kalderon struct bnx2x_func_set_timesync_params set_timesync; 1288adfc5217SJeff Kirsher } params; 1289adfc5217SJeff Kirsher }; 1290adfc5217SJeff Kirsher 1291adfc5217SJeff Kirsher struct bnx2x_func_sp_drv_ops { 1292adfc5217SJeff Kirsher /* Init tool + runtime initialization: 1293adfc5217SJeff Kirsher * - Common Chip 1294adfc5217SJeff Kirsher * - Common (per Path) 1295adfc5217SJeff Kirsher * - Port 1296adfc5217SJeff Kirsher * - Function phases 1297adfc5217SJeff Kirsher */ 1298adfc5217SJeff Kirsher int (*init_hw_cmn_chip)(struct bnx2x *bp); 1299adfc5217SJeff Kirsher int (*init_hw_cmn)(struct bnx2x *bp); 1300adfc5217SJeff Kirsher int (*init_hw_port)(struct bnx2x *bp); 1301adfc5217SJeff Kirsher int (*init_hw_func)(struct bnx2x *bp); 1302adfc5217SJeff Kirsher 1303adfc5217SJeff Kirsher /* Reset Function HW: Common, Port, Function phases. */ 1304adfc5217SJeff Kirsher void (*reset_hw_cmn)(struct bnx2x *bp); 1305adfc5217SJeff Kirsher void (*reset_hw_port)(struct bnx2x *bp); 1306adfc5217SJeff Kirsher void (*reset_hw_func)(struct bnx2x *bp); 1307adfc5217SJeff Kirsher 1308adfc5217SJeff Kirsher /* Init/Free GUNZIP resources */ 1309adfc5217SJeff Kirsher int (*gunzip_init)(struct bnx2x *bp); 1310adfc5217SJeff Kirsher void (*gunzip_end)(struct bnx2x *bp); 1311adfc5217SJeff Kirsher 1312adfc5217SJeff Kirsher /* Prepare/Release FW resources */ 1313adfc5217SJeff Kirsher int (*init_fw)(struct bnx2x *bp); 1314adfc5217SJeff Kirsher void (*release_fw)(struct bnx2x *bp); 1315adfc5217SJeff Kirsher }; 1316adfc5217SJeff Kirsher 1317adfc5217SJeff Kirsher struct bnx2x_func_sp_obj { 1318adfc5217SJeff Kirsher enum bnx2x_func_state state, next_state; 1319adfc5217SJeff Kirsher 1320adfc5217SJeff Kirsher /* BNX2X_FUNC_CMD_XX bits. This object implements "one 1321adfc5217SJeff Kirsher * pending" paradigm but for debug and tracing purposes it's 132216a5fd92SYuval Mintz * more convenient to have different bits for different 1323adfc5217SJeff Kirsher * commands. 1324adfc5217SJeff Kirsher */ 1325adfc5217SJeff Kirsher unsigned long pending; 1326adfc5217SJeff Kirsher 1327adfc5217SJeff Kirsher /* Buffer to use as a ramrod data and its mapping */ 1328adfc5217SJeff Kirsher void *rdata; 1329adfc5217SJeff Kirsher dma_addr_t rdata_mapping; 1330adfc5217SJeff Kirsher 1331a3348722SBarak Witkowski /* Buffer to use as a afex ramrod data and its mapping. 1332a3348722SBarak Witkowski * This can't be same rdata as above because afex ramrod requests 1333a3348722SBarak Witkowski * can arrive to the object in parallel to other ramrod requests. 1334a3348722SBarak Witkowski */ 1335a3348722SBarak Witkowski void *afex_rdata; 1336a3348722SBarak Witkowski dma_addr_t afex_rdata_mapping; 1337a3348722SBarak Witkowski 1338adfc5217SJeff Kirsher /* this mutex validates that when pending flag is taken, the next 1339adfc5217SJeff Kirsher * ramrod to be sent will be the one set the pending bit 1340adfc5217SJeff Kirsher */ 1341adfc5217SJeff Kirsher struct mutex one_pending_mutex; 1342adfc5217SJeff Kirsher 1343adfc5217SJeff Kirsher /* Driver interface */ 1344adfc5217SJeff Kirsher struct bnx2x_func_sp_drv_ops *drv; 1345adfc5217SJeff Kirsher 1346adfc5217SJeff Kirsher /** 1347adfc5217SJeff Kirsher * Performs one state change according to the given parameters. 1348adfc5217SJeff Kirsher * 1349adfc5217SJeff Kirsher * @return 0 in case of success and negative value otherwise. 1350adfc5217SJeff Kirsher */ 1351adfc5217SJeff Kirsher int (*send_cmd)(struct bnx2x *bp, 1352adfc5217SJeff Kirsher struct bnx2x_func_state_params *params); 1353adfc5217SJeff Kirsher 1354adfc5217SJeff Kirsher /** 1355adfc5217SJeff Kirsher * Checks that the requested state transition is legal. 1356adfc5217SJeff Kirsher */ 1357adfc5217SJeff Kirsher int (*check_transition)(struct bnx2x *bp, 1358adfc5217SJeff Kirsher struct bnx2x_func_sp_obj *o, 1359adfc5217SJeff Kirsher struct bnx2x_func_state_params *params); 1360adfc5217SJeff Kirsher 1361adfc5217SJeff Kirsher /** 1362adfc5217SJeff Kirsher * Completes the pending command. 1363adfc5217SJeff Kirsher */ 1364adfc5217SJeff Kirsher int (*complete_cmd)(struct bnx2x *bp, 1365adfc5217SJeff Kirsher struct bnx2x_func_sp_obj *o, 1366adfc5217SJeff Kirsher enum bnx2x_func_cmd cmd); 1367adfc5217SJeff Kirsher 1368adfc5217SJeff Kirsher int (*wait_comp)(struct bnx2x *bp, struct bnx2x_func_sp_obj *o, 1369adfc5217SJeff Kirsher enum bnx2x_func_cmd cmd); 1370adfc5217SJeff Kirsher }; 1371adfc5217SJeff Kirsher 1372adfc5217SJeff Kirsher /********************** Interfaces ********************************************/ 1373adfc5217SJeff Kirsher /* Queueable objects set */ 1374adfc5217SJeff Kirsher union bnx2x_qable_obj { 1375adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj vlan_mac; 1376adfc5217SJeff Kirsher }; 1377adfc5217SJeff Kirsher /************** Function state update *********/ 1378adfc5217SJeff Kirsher void bnx2x_init_func_obj(struct bnx2x *bp, 1379adfc5217SJeff Kirsher struct bnx2x_func_sp_obj *obj, 1380adfc5217SJeff Kirsher void *rdata, dma_addr_t rdata_mapping, 1381a3348722SBarak Witkowski void *afex_rdata, dma_addr_t afex_rdata_mapping, 1382adfc5217SJeff Kirsher struct bnx2x_func_sp_drv_ops *drv_iface); 1383adfc5217SJeff Kirsher 1384adfc5217SJeff Kirsher int bnx2x_func_state_change(struct bnx2x *bp, 1385adfc5217SJeff Kirsher struct bnx2x_func_state_params *params); 1386adfc5217SJeff Kirsher 1387adfc5217SJeff Kirsher enum bnx2x_func_state bnx2x_func_get_state(struct bnx2x *bp, 1388adfc5217SJeff Kirsher struct bnx2x_func_sp_obj *o); 1389adfc5217SJeff Kirsher /******************* Queue State **************/ 1390adfc5217SJeff Kirsher void bnx2x_init_queue_obj(struct bnx2x *bp, 1391adfc5217SJeff Kirsher struct bnx2x_queue_sp_obj *obj, u8 cl_id, u32 *cids, 1392adfc5217SJeff Kirsher u8 cid_cnt, u8 func_id, void *rdata, 1393adfc5217SJeff Kirsher dma_addr_t rdata_mapping, unsigned long type); 1394adfc5217SJeff Kirsher 1395adfc5217SJeff Kirsher int bnx2x_queue_state_change(struct bnx2x *bp, 1396adfc5217SJeff Kirsher struct bnx2x_queue_state_params *params); 1397adfc5217SJeff Kirsher 139867c431a5SAriel Elior int bnx2x_get_q_logical_state(struct bnx2x *bp, 139967c431a5SAriel Elior struct bnx2x_queue_sp_obj *obj); 140067c431a5SAriel Elior 1401adfc5217SJeff Kirsher /********************* VLAN-MAC ****************/ 1402adfc5217SJeff Kirsher void bnx2x_init_mac_obj(struct bnx2x *bp, 1403adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *mac_obj, 1404adfc5217SJeff Kirsher u8 cl_id, u32 cid, u8 func_id, void *rdata, 1405adfc5217SJeff Kirsher dma_addr_t rdata_mapping, int state, 1406adfc5217SJeff Kirsher unsigned long *pstate, bnx2x_obj_type type, 1407adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *macs_pool); 1408adfc5217SJeff Kirsher 1409adfc5217SJeff Kirsher void bnx2x_init_vlan_obj(struct bnx2x *bp, 1410adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *vlan_obj, 1411adfc5217SJeff Kirsher u8 cl_id, u32 cid, u8 func_id, void *rdata, 1412adfc5217SJeff Kirsher dma_addr_t rdata_mapping, int state, 1413adfc5217SJeff Kirsher unsigned long *pstate, bnx2x_obj_type type, 1414adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *vlans_pool); 1415adfc5217SJeff Kirsher 141605cc5a39SYuval Mintz void bnx2x_init_vlan_mac_obj(struct bnx2x *bp, 141705cc5a39SYuval Mintz struct bnx2x_vlan_mac_obj *vlan_mac_obj, 141805cc5a39SYuval Mintz u8 cl_id, u32 cid, u8 func_id, void *rdata, 141905cc5a39SYuval Mintz dma_addr_t rdata_mapping, int state, 142005cc5a39SYuval Mintz unsigned long *pstate, bnx2x_obj_type type, 142105cc5a39SYuval Mintz struct bnx2x_credit_pool_obj *macs_pool, 142205cc5a39SYuval Mintz struct bnx2x_credit_pool_obj *vlans_pool); 142305cc5a39SYuval Mintz 14248b09be5fSYuval Mintz int bnx2x_vlan_mac_h_read_lock(struct bnx2x *bp, 14258b09be5fSYuval Mintz struct bnx2x_vlan_mac_obj *o); 14268b09be5fSYuval Mintz void bnx2x_vlan_mac_h_read_unlock(struct bnx2x *bp, 14278b09be5fSYuval Mintz struct bnx2x_vlan_mac_obj *o); 14288b09be5fSYuval Mintz int bnx2x_vlan_mac_h_write_lock(struct bnx2x *bp, 14298b09be5fSYuval Mintz struct bnx2x_vlan_mac_obj *o); 1430adfc5217SJeff Kirsher int bnx2x_config_vlan_mac(struct bnx2x *bp, 1431adfc5217SJeff Kirsher struct bnx2x_vlan_mac_ramrod_params *p); 1432adfc5217SJeff Kirsher 1433adfc5217SJeff Kirsher int bnx2x_vlan_mac_move(struct bnx2x *bp, 1434adfc5217SJeff Kirsher struct bnx2x_vlan_mac_ramrod_params *p, 1435adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *dest_o); 1436adfc5217SJeff Kirsher 1437adfc5217SJeff Kirsher /********************* RX MODE ****************/ 1438adfc5217SJeff Kirsher 1439adfc5217SJeff Kirsher void bnx2x_init_rx_mode_obj(struct bnx2x *bp, 1440adfc5217SJeff Kirsher struct bnx2x_rx_mode_obj *o); 1441adfc5217SJeff Kirsher 1442adfc5217SJeff Kirsher /** 14431aa8b471SBen Hutchings * bnx2x_config_rx_mode - Send and RX_MODE ramrod according to the provided parameters. 1444adfc5217SJeff Kirsher * 14451aa8b471SBen Hutchings * @p: Command parameters 1446adfc5217SJeff Kirsher * 144716a5fd92SYuval Mintz * Return: 0 - if operation was successful and there is no pending completions, 1448adfc5217SJeff Kirsher * positive number - if there are pending completions, 1449adfc5217SJeff Kirsher * negative - if there were errors 1450adfc5217SJeff Kirsher */ 1451adfc5217SJeff Kirsher int bnx2x_config_rx_mode(struct bnx2x *bp, 1452adfc5217SJeff Kirsher struct bnx2x_rx_mode_ramrod_params *p); 1453adfc5217SJeff Kirsher 1454adfc5217SJeff Kirsher /****************** MULTICASTS ****************/ 1455adfc5217SJeff Kirsher 1456adfc5217SJeff Kirsher void bnx2x_init_mcast_obj(struct bnx2x *bp, 1457adfc5217SJeff Kirsher struct bnx2x_mcast_obj *mcast_obj, 1458adfc5217SJeff Kirsher u8 mcast_cl_id, u32 mcast_cid, u8 func_id, 1459adfc5217SJeff Kirsher u8 engine_id, void *rdata, dma_addr_t rdata_mapping, 1460adfc5217SJeff Kirsher int state, unsigned long *pstate, 1461adfc5217SJeff Kirsher bnx2x_obj_type type); 1462adfc5217SJeff Kirsher 1463adfc5217SJeff Kirsher /** 14641aa8b471SBen Hutchings * bnx2x_config_mcast - Configure multicast MACs list. 14651aa8b471SBen Hutchings * 14661aa8b471SBen Hutchings * @cmd: command to execute: BNX2X_MCAST_CMD_X 14671aa8b471SBen Hutchings * 14681aa8b471SBen Hutchings * May configure a new list 1469adfc5217SJeff Kirsher * provided in p->mcast_list (BNX2X_MCAST_CMD_ADD), clean up 1470adfc5217SJeff Kirsher * (BNX2X_MCAST_CMD_DEL) or restore (BNX2X_MCAST_CMD_RESTORE) a current 1471adfc5217SJeff Kirsher * configuration, continue to execute the pending commands 1472adfc5217SJeff Kirsher * (BNX2X_MCAST_CMD_CONT). 1473adfc5217SJeff Kirsher * 1474adfc5217SJeff Kirsher * If previous command is still pending or if number of MACs to 1475adfc5217SJeff Kirsher * configure is more that maximum number of MACs in one command, 1476adfc5217SJeff Kirsher * the current command will be enqueued to the tail of the 1477adfc5217SJeff Kirsher * pending commands list. 1478adfc5217SJeff Kirsher * 147916a5fd92SYuval Mintz * Return: 0 is operation was successful and there are no pending completions, 1480adfc5217SJeff Kirsher * negative if there were errors, positive if there are pending 1481adfc5217SJeff Kirsher * completions. 1482adfc5217SJeff Kirsher */ 1483adfc5217SJeff Kirsher int bnx2x_config_mcast(struct bnx2x *bp, 148486564c3fSYuval Mintz struct bnx2x_mcast_ramrod_params *p, 148586564c3fSYuval Mintz enum bnx2x_mcast_cmd cmd); 1486adfc5217SJeff Kirsher 1487adfc5217SJeff Kirsher /****************** CREDIT POOL ****************/ 1488adfc5217SJeff Kirsher void bnx2x_init_mac_credit_pool(struct bnx2x *bp, 1489adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *p, u8 func_id, 1490adfc5217SJeff Kirsher u8 func_num); 1491adfc5217SJeff Kirsher void bnx2x_init_vlan_credit_pool(struct bnx2x *bp, 1492adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *p, u8 func_id, 1493adfc5217SJeff Kirsher u8 func_num); 149405cc5a39SYuval Mintz void bnx2x_init_credit_pool(struct bnx2x_credit_pool_obj *p, 149505cc5a39SYuval Mintz int base, int credit); 1496adfc5217SJeff Kirsher 1497adfc5217SJeff Kirsher /****************** RSS CONFIGURATION ****************/ 1498adfc5217SJeff Kirsher void bnx2x_init_rss_config_obj(struct bnx2x *bp, 1499adfc5217SJeff Kirsher struct bnx2x_rss_config_obj *rss_obj, 1500adfc5217SJeff Kirsher u8 cl_id, u32 cid, u8 func_id, u8 engine_id, 1501adfc5217SJeff Kirsher void *rdata, dma_addr_t rdata_mapping, 1502adfc5217SJeff Kirsher int state, unsigned long *pstate, 1503adfc5217SJeff Kirsher bnx2x_obj_type type); 1504adfc5217SJeff Kirsher 1505adfc5217SJeff Kirsher /** 15061aa8b471SBen Hutchings * bnx2x_config_rss - Updates RSS configuration according to provided parameters 1507adfc5217SJeff Kirsher * 15081aa8b471SBen Hutchings * Return: 0 in case of success 1509adfc5217SJeff Kirsher */ 1510adfc5217SJeff Kirsher int bnx2x_config_rss(struct bnx2x *bp, 1511adfc5217SJeff Kirsher struct bnx2x_config_rss_params *p); 1512adfc5217SJeff Kirsher 1513adfc5217SJeff Kirsher /** 15141aa8b471SBen Hutchings * bnx2x_get_rss_ind_table - Return the current ind_table configuration. 1515adfc5217SJeff Kirsher * 15161aa8b471SBen Hutchings * @ind_table: buffer to fill with the current indirection 1517adfc5217SJeff Kirsher * table content. Should be at least 1518adfc5217SJeff Kirsher * T_ETH_INDIRECTION_TABLE_SIZE bytes long. 1519adfc5217SJeff Kirsher */ 1520adfc5217SJeff Kirsher void bnx2x_get_rss_ind_table(struct bnx2x_rss_config_obj *rss_obj, 1521adfc5217SJeff Kirsher u8 *ind_table); 1522adfc5217SJeff Kirsher 152305cc5a39SYuval Mintz #define PF_MAC_CREDIT_E2(bp, func_num) \ 152405cc5a39SYuval Mintz ((MAX_MAC_CREDIT_E2 - GET_NUM_VFS_PER_PATH(bp) * VF_MAC_CREDIT_CNT) / \ 152505cc5a39SYuval Mintz func_num + GET_NUM_VFS_PER_PF(bp) * VF_MAC_CREDIT_CNT) 152605cc5a39SYuval Mintz 152705cc5a39SYuval Mintz #define PF_VLAN_CREDIT_E2(bp, func_num) \ 152805cc5a39SYuval Mintz ((MAX_MAC_CREDIT_E2 - GET_NUM_VFS_PER_PATH(bp) * VF_VLAN_CREDIT_CNT) / \ 152905cc5a39SYuval Mintz func_num + GET_NUM_VFS_PER_PF(bp) * VF_VLAN_CREDIT_CNT) 153005cc5a39SYuval Mintz 1531adfc5217SJeff Kirsher #endif /* BNX2X_SP_VERBS */ 1532