1adfc5217SJeff Kirsher /* bnx2x_sp.c: Broadcom Everest network driver. 2adfc5217SJeff Kirsher * 3247fa82bSYuval Mintz * Copyright (c) 2011-2013 Broadcom Corporation 4adfc5217SJeff Kirsher * 5adfc5217SJeff Kirsher * Unless you and Broadcom execute a separate written software license 6adfc5217SJeff Kirsher * agreement governing use of this software, this software is licensed to you 7adfc5217SJeff Kirsher * under the terms of the GNU General Public License version 2, available 8adfc5217SJeff Kirsher * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL"). 9adfc5217SJeff Kirsher * 10adfc5217SJeff Kirsher * Notwithstanding the above, under no circumstances may you combine this 11adfc5217SJeff Kirsher * software in any way with any other Broadcom software provided under a 12adfc5217SJeff Kirsher * license other than the GPL, without Broadcom's express prior written 13adfc5217SJeff Kirsher * consent. 14adfc5217SJeff Kirsher * 15adfc5217SJeff Kirsher * Maintained by: Eilon Greenstein <eilong@broadcom.com> 16adfc5217SJeff Kirsher * Written by: Vladislav Zolotarov 17adfc5217SJeff Kirsher * 18adfc5217SJeff Kirsher */ 19f1deab50SJoe Perches 20f1deab50SJoe Perches #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 21f1deab50SJoe Perches 22adfc5217SJeff Kirsher #include <linux/module.h> 23adfc5217SJeff Kirsher #include <linux/crc32.h> 24adfc5217SJeff Kirsher #include <linux/netdevice.h> 25adfc5217SJeff Kirsher #include <linux/etherdevice.h> 26adfc5217SJeff Kirsher #include <linux/crc32c.h> 27adfc5217SJeff Kirsher #include "bnx2x.h" 28adfc5217SJeff Kirsher #include "bnx2x_cmn.h" 29adfc5217SJeff Kirsher #include "bnx2x_sp.h" 30adfc5217SJeff Kirsher 31adfc5217SJeff Kirsher #define BNX2X_MAX_EMUL_MULTI 16 32adfc5217SJeff Kirsher 33adfc5217SJeff Kirsher /**** Exe Queue interfaces ****/ 34adfc5217SJeff Kirsher 35adfc5217SJeff Kirsher /** 36adfc5217SJeff Kirsher * bnx2x_exe_queue_init - init the Exe Queue object 37adfc5217SJeff Kirsher * 3816a5fd92SYuval Mintz * @o: pointer to the object 39adfc5217SJeff Kirsher * @exe_len: length 4016a5fd92SYuval Mintz * @owner: pointer to the owner 41adfc5217SJeff Kirsher * @validate: validate function pointer 42adfc5217SJeff Kirsher * @optimize: optimize function pointer 43adfc5217SJeff Kirsher * @exec: execute function pointer 44adfc5217SJeff Kirsher * @get: get function pointer 45adfc5217SJeff Kirsher */ 46adfc5217SJeff Kirsher static inline void bnx2x_exe_queue_init(struct bnx2x *bp, 47adfc5217SJeff Kirsher struct bnx2x_exe_queue_obj *o, 48adfc5217SJeff Kirsher int exe_len, 49adfc5217SJeff Kirsher union bnx2x_qable_obj *owner, 50adfc5217SJeff Kirsher exe_q_validate validate, 51460a25cdSYuval Mintz exe_q_remove remove, 52adfc5217SJeff Kirsher exe_q_optimize optimize, 53adfc5217SJeff Kirsher exe_q_execute exec, 54adfc5217SJeff Kirsher exe_q_get get) 55adfc5217SJeff Kirsher { 56adfc5217SJeff Kirsher memset(o, 0, sizeof(*o)); 57adfc5217SJeff Kirsher 58adfc5217SJeff Kirsher INIT_LIST_HEAD(&o->exe_queue); 59adfc5217SJeff Kirsher INIT_LIST_HEAD(&o->pending_comp); 60adfc5217SJeff Kirsher 61adfc5217SJeff Kirsher spin_lock_init(&o->lock); 62adfc5217SJeff Kirsher 63adfc5217SJeff Kirsher o->exe_chunk_len = exe_len; 64adfc5217SJeff Kirsher o->owner = owner; 65adfc5217SJeff Kirsher 66adfc5217SJeff Kirsher /* Owner specific callbacks */ 67adfc5217SJeff Kirsher o->validate = validate; 68460a25cdSYuval Mintz o->remove = remove; 69adfc5217SJeff Kirsher o->optimize = optimize; 70adfc5217SJeff Kirsher o->execute = exec; 71adfc5217SJeff Kirsher o->get = get; 72adfc5217SJeff Kirsher 7351c1a580SMerav Sicron DP(BNX2X_MSG_SP, "Setup the execution queue with the chunk length of %d\n", 7451c1a580SMerav Sicron exe_len); 75adfc5217SJeff Kirsher } 76adfc5217SJeff Kirsher 77adfc5217SJeff Kirsher static inline void bnx2x_exe_queue_free_elem(struct bnx2x *bp, 78adfc5217SJeff Kirsher struct bnx2x_exeq_elem *elem) 79adfc5217SJeff Kirsher { 80adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "Deleting an exe_queue element\n"); 81adfc5217SJeff Kirsher kfree(elem); 82adfc5217SJeff Kirsher } 83adfc5217SJeff Kirsher 84adfc5217SJeff Kirsher static inline int bnx2x_exe_queue_length(struct bnx2x_exe_queue_obj *o) 85adfc5217SJeff Kirsher { 86adfc5217SJeff Kirsher struct bnx2x_exeq_elem *elem; 87adfc5217SJeff Kirsher int cnt = 0; 88adfc5217SJeff Kirsher 89adfc5217SJeff Kirsher spin_lock_bh(&o->lock); 90adfc5217SJeff Kirsher 91adfc5217SJeff Kirsher list_for_each_entry(elem, &o->exe_queue, link) 92adfc5217SJeff Kirsher cnt++; 93adfc5217SJeff Kirsher 94adfc5217SJeff Kirsher spin_unlock_bh(&o->lock); 95adfc5217SJeff Kirsher 96adfc5217SJeff Kirsher return cnt; 97adfc5217SJeff Kirsher } 98adfc5217SJeff Kirsher 99adfc5217SJeff Kirsher /** 100adfc5217SJeff Kirsher * bnx2x_exe_queue_add - add a new element to the execution queue 101adfc5217SJeff Kirsher * 102adfc5217SJeff Kirsher * @bp: driver handle 103adfc5217SJeff Kirsher * @o: queue 104adfc5217SJeff Kirsher * @cmd: new command to add 105adfc5217SJeff Kirsher * @restore: true - do not optimize the command 106adfc5217SJeff Kirsher * 107adfc5217SJeff Kirsher * If the element is optimized or is illegal, frees it. 108adfc5217SJeff Kirsher */ 109adfc5217SJeff Kirsher static inline int bnx2x_exe_queue_add(struct bnx2x *bp, 110adfc5217SJeff Kirsher struct bnx2x_exe_queue_obj *o, 111adfc5217SJeff Kirsher struct bnx2x_exeq_elem *elem, 112adfc5217SJeff Kirsher bool restore) 113adfc5217SJeff Kirsher { 114adfc5217SJeff Kirsher int rc; 115adfc5217SJeff Kirsher 116adfc5217SJeff Kirsher spin_lock_bh(&o->lock); 117adfc5217SJeff Kirsher 118adfc5217SJeff Kirsher if (!restore) { 119adfc5217SJeff Kirsher /* Try to cancel this element queue */ 120adfc5217SJeff Kirsher rc = o->optimize(bp, o->owner, elem); 121adfc5217SJeff Kirsher if (rc) 122adfc5217SJeff Kirsher goto free_and_exit; 123adfc5217SJeff Kirsher 124adfc5217SJeff Kirsher /* Check if this request is ok */ 125adfc5217SJeff Kirsher rc = o->validate(bp, o->owner, elem); 126adfc5217SJeff Kirsher if (rc) { 1272384d6aaSDmitry Kravkov DP(BNX2X_MSG_SP, "Preamble failed: %d\n", rc); 128adfc5217SJeff Kirsher goto free_and_exit; 129adfc5217SJeff Kirsher } 130adfc5217SJeff Kirsher } 131adfc5217SJeff Kirsher 132adfc5217SJeff Kirsher /* If so, add it to the execution queue */ 133adfc5217SJeff Kirsher list_add_tail(&elem->link, &o->exe_queue); 134adfc5217SJeff Kirsher 135adfc5217SJeff Kirsher spin_unlock_bh(&o->lock); 136adfc5217SJeff Kirsher 137adfc5217SJeff Kirsher return 0; 138adfc5217SJeff Kirsher 139adfc5217SJeff Kirsher free_and_exit: 140adfc5217SJeff Kirsher bnx2x_exe_queue_free_elem(bp, elem); 141adfc5217SJeff Kirsher 142adfc5217SJeff Kirsher spin_unlock_bh(&o->lock); 143adfc5217SJeff Kirsher 144adfc5217SJeff Kirsher return rc; 145adfc5217SJeff Kirsher } 146adfc5217SJeff Kirsher 147adfc5217SJeff Kirsher static inline void __bnx2x_exe_queue_reset_pending( 148adfc5217SJeff Kirsher struct bnx2x *bp, 149adfc5217SJeff Kirsher struct bnx2x_exe_queue_obj *o) 150adfc5217SJeff Kirsher { 151adfc5217SJeff Kirsher struct bnx2x_exeq_elem *elem; 152adfc5217SJeff Kirsher 153adfc5217SJeff Kirsher while (!list_empty(&o->pending_comp)) { 154adfc5217SJeff Kirsher elem = list_first_entry(&o->pending_comp, 155adfc5217SJeff Kirsher struct bnx2x_exeq_elem, link); 156adfc5217SJeff Kirsher 157adfc5217SJeff Kirsher list_del(&elem->link); 158adfc5217SJeff Kirsher bnx2x_exe_queue_free_elem(bp, elem); 159adfc5217SJeff Kirsher } 160adfc5217SJeff Kirsher } 161adfc5217SJeff Kirsher 162adfc5217SJeff Kirsher /** 163adfc5217SJeff Kirsher * bnx2x_exe_queue_step - execute one execution chunk atomically 164adfc5217SJeff Kirsher * 165adfc5217SJeff Kirsher * @bp: driver handle 166adfc5217SJeff Kirsher * @o: queue 167adfc5217SJeff Kirsher * @ramrod_flags: flags 168adfc5217SJeff Kirsher * 1698b09be5fSYuval Mintz * (Should be called while holding the exe_queue->lock). 170adfc5217SJeff Kirsher */ 171adfc5217SJeff Kirsher static inline int bnx2x_exe_queue_step(struct bnx2x *bp, 172adfc5217SJeff Kirsher struct bnx2x_exe_queue_obj *o, 173adfc5217SJeff Kirsher unsigned long *ramrod_flags) 174adfc5217SJeff Kirsher { 175adfc5217SJeff Kirsher struct bnx2x_exeq_elem *elem, spacer; 176adfc5217SJeff Kirsher int cur_len = 0, rc; 177adfc5217SJeff Kirsher 178adfc5217SJeff Kirsher memset(&spacer, 0, sizeof(spacer)); 179adfc5217SJeff Kirsher 18016a5fd92SYuval Mintz /* Next step should not be performed until the current is finished, 181adfc5217SJeff Kirsher * unless a DRV_CLEAR_ONLY bit is set. In this case we just want to 182adfc5217SJeff Kirsher * properly clear object internals without sending any command to the FW 183adfc5217SJeff Kirsher * which also implies there won't be any completion to clear the 184adfc5217SJeff Kirsher * 'pending' list. 185adfc5217SJeff Kirsher */ 186adfc5217SJeff Kirsher if (!list_empty(&o->pending_comp)) { 187adfc5217SJeff Kirsher if (test_bit(RAMROD_DRV_CLR_ONLY, ramrod_flags)) { 18851c1a580SMerav Sicron DP(BNX2X_MSG_SP, "RAMROD_DRV_CLR_ONLY requested: resetting a pending_comp list\n"); 189adfc5217SJeff Kirsher __bnx2x_exe_queue_reset_pending(bp, o); 190adfc5217SJeff Kirsher } else { 191adfc5217SJeff Kirsher return 1; 192adfc5217SJeff Kirsher } 193adfc5217SJeff Kirsher } 194adfc5217SJeff Kirsher 19516a5fd92SYuval Mintz /* Run through the pending commands list and create a next 196adfc5217SJeff Kirsher * execution chunk. 197adfc5217SJeff Kirsher */ 198adfc5217SJeff Kirsher while (!list_empty(&o->exe_queue)) { 199adfc5217SJeff Kirsher elem = list_first_entry(&o->exe_queue, struct bnx2x_exeq_elem, 200adfc5217SJeff Kirsher link); 201adfc5217SJeff Kirsher WARN_ON(!elem->cmd_len); 202adfc5217SJeff Kirsher 203adfc5217SJeff Kirsher if (cur_len + elem->cmd_len <= o->exe_chunk_len) { 204adfc5217SJeff Kirsher cur_len += elem->cmd_len; 20516a5fd92SYuval Mintz /* Prevent from both lists being empty when moving an 206adfc5217SJeff Kirsher * element. This will allow the call of 207adfc5217SJeff Kirsher * bnx2x_exe_queue_empty() without locking. 208adfc5217SJeff Kirsher */ 209adfc5217SJeff Kirsher list_add_tail(&spacer.link, &o->pending_comp); 210adfc5217SJeff Kirsher mb(); 2117933aa5cSWei Yongjun list_move_tail(&elem->link, &o->pending_comp); 212adfc5217SJeff Kirsher list_del(&spacer.link); 213adfc5217SJeff Kirsher } else 214adfc5217SJeff Kirsher break; 215adfc5217SJeff Kirsher } 216adfc5217SJeff Kirsher 217adfc5217SJeff Kirsher /* Sanity check */ 2188b09be5fSYuval Mintz if (!cur_len) 219adfc5217SJeff Kirsher return 0; 220adfc5217SJeff Kirsher 221adfc5217SJeff Kirsher rc = o->execute(bp, o->owner, &o->pending_comp, ramrod_flags); 222adfc5217SJeff Kirsher if (rc < 0) 22316a5fd92SYuval Mintz /* In case of an error return the commands back to the queue 224adfc5217SJeff Kirsher * and reset the pending_comp. 225adfc5217SJeff Kirsher */ 226adfc5217SJeff Kirsher list_splice_init(&o->pending_comp, &o->exe_queue); 227adfc5217SJeff Kirsher else if (!rc) 22816a5fd92SYuval Mintz /* If zero is returned, means there are no outstanding pending 229adfc5217SJeff Kirsher * completions and we may dismiss the pending list. 230adfc5217SJeff Kirsher */ 231adfc5217SJeff Kirsher __bnx2x_exe_queue_reset_pending(bp, o); 232adfc5217SJeff Kirsher 233adfc5217SJeff Kirsher return rc; 234adfc5217SJeff Kirsher } 235adfc5217SJeff Kirsher 236adfc5217SJeff Kirsher static inline bool bnx2x_exe_queue_empty(struct bnx2x_exe_queue_obj *o) 237adfc5217SJeff Kirsher { 238adfc5217SJeff Kirsher bool empty = list_empty(&o->exe_queue); 239adfc5217SJeff Kirsher 240adfc5217SJeff Kirsher /* Don't reorder!!! */ 241adfc5217SJeff Kirsher mb(); 242adfc5217SJeff Kirsher 243adfc5217SJeff Kirsher return empty && list_empty(&o->pending_comp); 244adfc5217SJeff Kirsher } 245adfc5217SJeff Kirsher 246adfc5217SJeff Kirsher static inline struct bnx2x_exeq_elem *bnx2x_exe_queue_alloc_elem( 247adfc5217SJeff Kirsher struct bnx2x *bp) 248adfc5217SJeff Kirsher { 249adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "Allocating a new exe_queue element\n"); 250adfc5217SJeff Kirsher return kzalloc(sizeof(struct bnx2x_exeq_elem), GFP_ATOMIC); 251adfc5217SJeff Kirsher } 252adfc5217SJeff Kirsher 253adfc5217SJeff Kirsher /************************ raw_obj functions ***********************************/ 254adfc5217SJeff Kirsher static bool bnx2x_raw_check_pending(struct bnx2x_raw_obj *o) 255adfc5217SJeff Kirsher { 256adfc5217SJeff Kirsher return !!test_bit(o->state, o->pstate); 257adfc5217SJeff Kirsher } 258adfc5217SJeff Kirsher 259adfc5217SJeff Kirsher static void bnx2x_raw_clear_pending(struct bnx2x_raw_obj *o) 260adfc5217SJeff Kirsher { 261adfc5217SJeff Kirsher smp_mb__before_clear_bit(); 262adfc5217SJeff Kirsher clear_bit(o->state, o->pstate); 263adfc5217SJeff Kirsher smp_mb__after_clear_bit(); 264adfc5217SJeff Kirsher } 265adfc5217SJeff Kirsher 266adfc5217SJeff Kirsher static void bnx2x_raw_set_pending(struct bnx2x_raw_obj *o) 267adfc5217SJeff Kirsher { 268adfc5217SJeff Kirsher smp_mb__before_clear_bit(); 269adfc5217SJeff Kirsher set_bit(o->state, o->pstate); 270adfc5217SJeff Kirsher smp_mb__after_clear_bit(); 271adfc5217SJeff Kirsher } 272adfc5217SJeff Kirsher 273adfc5217SJeff Kirsher /** 274adfc5217SJeff Kirsher * bnx2x_state_wait - wait until the given bit(state) is cleared 275adfc5217SJeff Kirsher * 276adfc5217SJeff Kirsher * @bp: device handle 277adfc5217SJeff Kirsher * @state: state which is to be cleared 278adfc5217SJeff Kirsher * @state_p: state buffer 279adfc5217SJeff Kirsher * 280adfc5217SJeff Kirsher */ 281adfc5217SJeff Kirsher static inline int bnx2x_state_wait(struct bnx2x *bp, int state, 282adfc5217SJeff Kirsher unsigned long *pstate) 283adfc5217SJeff Kirsher { 284adfc5217SJeff Kirsher /* can take a while if any port is running */ 285adfc5217SJeff Kirsher int cnt = 5000; 286adfc5217SJeff Kirsher 287adfc5217SJeff Kirsher if (CHIP_REV_IS_EMUL(bp)) 288adfc5217SJeff Kirsher cnt *= 20; 289adfc5217SJeff Kirsher 290adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "waiting for state to become %d\n", state); 291adfc5217SJeff Kirsher 292adfc5217SJeff Kirsher might_sleep(); 293adfc5217SJeff Kirsher while (cnt--) { 294adfc5217SJeff Kirsher if (!test_bit(state, pstate)) { 295adfc5217SJeff Kirsher #ifdef BNX2X_STOP_ON_ERROR 296adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "exit (cnt %d)\n", 5000 - cnt); 297adfc5217SJeff Kirsher #endif 298adfc5217SJeff Kirsher return 0; 299adfc5217SJeff Kirsher } 300adfc5217SJeff Kirsher 3010926d499SYuval Mintz usleep_range(1000, 2000); 302adfc5217SJeff Kirsher 303adfc5217SJeff Kirsher if (bp->panic) 304adfc5217SJeff Kirsher return -EIO; 305adfc5217SJeff Kirsher } 306adfc5217SJeff Kirsher 307adfc5217SJeff Kirsher /* timeout! */ 308adfc5217SJeff Kirsher BNX2X_ERR("timeout waiting for state %d\n", state); 309adfc5217SJeff Kirsher #ifdef BNX2X_STOP_ON_ERROR 310adfc5217SJeff Kirsher bnx2x_panic(); 311adfc5217SJeff Kirsher #endif 312adfc5217SJeff Kirsher 313adfc5217SJeff Kirsher return -EBUSY; 314adfc5217SJeff Kirsher } 315adfc5217SJeff Kirsher 316adfc5217SJeff Kirsher static int bnx2x_raw_wait(struct bnx2x *bp, struct bnx2x_raw_obj *raw) 317adfc5217SJeff Kirsher { 318adfc5217SJeff Kirsher return bnx2x_state_wait(bp, raw->state, raw->pstate); 319adfc5217SJeff Kirsher } 320adfc5217SJeff Kirsher 321adfc5217SJeff Kirsher /***************** Classification verbs: Set/Del MAC/VLAN/VLAN-MAC ************/ 322adfc5217SJeff Kirsher /* credit handling callbacks */ 323adfc5217SJeff Kirsher static bool bnx2x_get_cam_offset_mac(struct bnx2x_vlan_mac_obj *o, int *offset) 324adfc5217SJeff Kirsher { 325adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *mp = o->macs_pool; 326adfc5217SJeff Kirsher 327adfc5217SJeff Kirsher WARN_ON(!mp); 328adfc5217SJeff Kirsher 329adfc5217SJeff Kirsher return mp->get_entry(mp, offset); 330adfc5217SJeff Kirsher } 331adfc5217SJeff Kirsher 332adfc5217SJeff Kirsher static bool bnx2x_get_credit_mac(struct bnx2x_vlan_mac_obj *o) 333adfc5217SJeff Kirsher { 334adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *mp = o->macs_pool; 335adfc5217SJeff Kirsher 336adfc5217SJeff Kirsher WARN_ON(!mp); 337adfc5217SJeff Kirsher 338adfc5217SJeff Kirsher return mp->get(mp, 1); 339adfc5217SJeff Kirsher } 340adfc5217SJeff Kirsher 341adfc5217SJeff Kirsher static bool bnx2x_get_cam_offset_vlan(struct bnx2x_vlan_mac_obj *o, int *offset) 342adfc5217SJeff Kirsher { 343adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *vp = o->vlans_pool; 344adfc5217SJeff Kirsher 345adfc5217SJeff Kirsher WARN_ON(!vp); 346adfc5217SJeff Kirsher 347adfc5217SJeff Kirsher return vp->get_entry(vp, offset); 348adfc5217SJeff Kirsher } 349adfc5217SJeff Kirsher 350adfc5217SJeff Kirsher static bool bnx2x_get_credit_vlan(struct bnx2x_vlan_mac_obj *o) 351adfc5217SJeff Kirsher { 352adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *vp = o->vlans_pool; 353adfc5217SJeff Kirsher 354adfc5217SJeff Kirsher WARN_ON(!vp); 355adfc5217SJeff Kirsher 356adfc5217SJeff Kirsher return vp->get(vp, 1); 357adfc5217SJeff Kirsher } 358adfc5217SJeff Kirsher 359adfc5217SJeff Kirsher static bool bnx2x_get_credit_vlan_mac(struct bnx2x_vlan_mac_obj *o) 360adfc5217SJeff Kirsher { 361adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *mp = o->macs_pool; 362adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *vp = o->vlans_pool; 363adfc5217SJeff Kirsher 364adfc5217SJeff Kirsher if (!mp->get(mp, 1)) 365adfc5217SJeff Kirsher return false; 366adfc5217SJeff Kirsher 367adfc5217SJeff Kirsher if (!vp->get(vp, 1)) { 368adfc5217SJeff Kirsher mp->put(mp, 1); 369adfc5217SJeff Kirsher return false; 370adfc5217SJeff Kirsher } 371adfc5217SJeff Kirsher 372adfc5217SJeff Kirsher return true; 373adfc5217SJeff Kirsher } 374adfc5217SJeff Kirsher 375adfc5217SJeff Kirsher static bool bnx2x_put_cam_offset_mac(struct bnx2x_vlan_mac_obj *o, int offset) 376adfc5217SJeff Kirsher { 377adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *mp = o->macs_pool; 378adfc5217SJeff Kirsher 379adfc5217SJeff Kirsher return mp->put_entry(mp, offset); 380adfc5217SJeff Kirsher } 381adfc5217SJeff Kirsher 382adfc5217SJeff Kirsher static bool bnx2x_put_credit_mac(struct bnx2x_vlan_mac_obj *o) 383adfc5217SJeff Kirsher { 384adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *mp = o->macs_pool; 385adfc5217SJeff Kirsher 386adfc5217SJeff Kirsher return mp->put(mp, 1); 387adfc5217SJeff Kirsher } 388adfc5217SJeff Kirsher 389adfc5217SJeff Kirsher static bool bnx2x_put_cam_offset_vlan(struct bnx2x_vlan_mac_obj *o, int offset) 390adfc5217SJeff Kirsher { 391adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *vp = o->vlans_pool; 392adfc5217SJeff Kirsher 393adfc5217SJeff Kirsher return vp->put_entry(vp, offset); 394adfc5217SJeff Kirsher } 395adfc5217SJeff Kirsher 396adfc5217SJeff Kirsher static bool bnx2x_put_credit_vlan(struct bnx2x_vlan_mac_obj *o) 397adfc5217SJeff Kirsher { 398adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *vp = o->vlans_pool; 399adfc5217SJeff Kirsher 400adfc5217SJeff Kirsher return vp->put(vp, 1); 401adfc5217SJeff Kirsher } 402adfc5217SJeff Kirsher 403adfc5217SJeff Kirsher static bool bnx2x_put_credit_vlan_mac(struct bnx2x_vlan_mac_obj *o) 404adfc5217SJeff Kirsher { 405adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *mp = o->macs_pool; 406adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *vp = o->vlans_pool; 407adfc5217SJeff Kirsher 408adfc5217SJeff Kirsher if (!mp->put(mp, 1)) 409adfc5217SJeff Kirsher return false; 410adfc5217SJeff Kirsher 411adfc5217SJeff Kirsher if (!vp->put(vp, 1)) { 412adfc5217SJeff Kirsher mp->get(mp, 1); 413adfc5217SJeff Kirsher return false; 414adfc5217SJeff Kirsher } 415adfc5217SJeff Kirsher 416adfc5217SJeff Kirsher return true; 417adfc5217SJeff Kirsher } 418adfc5217SJeff Kirsher 4198b09be5fSYuval Mintz /** 4208b09be5fSYuval Mintz * __bnx2x_vlan_mac_h_write_trylock - try getting the vlan mac writer lock 4218b09be5fSYuval Mintz * 4228b09be5fSYuval Mintz * @bp: device handle 4238b09be5fSYuval Mintz * @o: vlan_mac object 4248b09be5fSYuval Mintz * 4258b09be5fSYuval Mintz * @details: Non-blocking implementation; should be called under execution 4268b09be5fSYuval Mintz * queue lock. 4278b09be5fSYuval Mintz */ 4288b09be5fSYuval Mintz static int __bnx2x_vlan_mac_h_write_trylock(struct bnx2x *bp, 4298b09be5fSYuval Mintz struct bnx2x_vlan_mac_obj *o) 4308b09be5fSYuval Mintz { 4318b09be5fSYuval Mintz if (o->head_reader) { 4328b09be5fSYuval Mintz DP(BNX2X_MSG_SP, "vlan_mac_lock writer - There are readers; Busy\n"); 4338b09be5fSYuval Mintz return -EBUSY; 4348b09be5fSYuval Mintz } 4358b09be5fSYuval Mintz 4368b09be5fSYuval Mintz DP(BNX2X_MSG_SP, "vlan_mac_lock writer - Taken\n"); 4378b09be5fSYuval Mintz return 0; 4388b09be5fSYuval Mintz } 4398b09be5fSYuval Mintz 4408b09be5fSYuval Mintz /** 4418b09be5fSYuval Mintz * __bnx2x_vlan_mac_h_exec_pending - execute step instead of a previous step 4428b09be5fSYuval Mintz * 4438b09be5fSYuval Mintz * @bp: device handle 4448b09be5fSYuval Mintz * @o: vlan_mac object 4458b09be5fSYuval Mintz * 4468b09be5fSYuval Mintz * @details Should be called under execution queue lock; notice it might release 4478b09be5fSYuval Mintz * and reclaim it during its run. 4488b09be5fSYuval Mintz */ 4498b09be5fSYuval Mintz static void __bnx2x_vlan_mac_h_exec_pending(struct bnx2x *bp, 4508b09be5fSYuval Mintz struct bnx2x_vlan_mac_obj *o) 4518b09be5fSYuval Mintz { 4528b09be5fSYuval Mintz int rc; 4538b09be5fSYuval Mintz unsigned long ramrod_flags = o->saved_ramrod_flags; 4548b09be5fSYuval Mintz 4558b09be5fSYuval Mintz DP(BNX2X_MSG_SP, "vlan_mac_lock execute pending command with ramrod flags %lu\n", 4568b09be5fSYuval Mintz ramrod_flags); 4578b09be5fSYuval Mintz o->head_exe_request = false; 4588b09be5fSYuval Mintz o->saved_ramrod_flags = 0; 4598b09be5fSYuval Mintz rc = bnx2x_exe_queue_step(bp, &o->exe_queue, &ramrod_flags); 4608b09be5fSYuval Mintz if (rc != 0) { 4618b09be5fSYuval Mintz BNX2X_ERR("execution of pending commands failed with rc %d\n", 4628b09be5fSYuval Mintz rc); 4638b09be5fSYuval Mintz #ifdef BNX2X_STOP_ON_ERROR 4648b09be5fSYuval Mintz bnx2x_panic(); 4658b09be5fSYuval Mintz #endif 4668b09be5fSYuval Mintz } 4678b09be5fSYuval Mintz } 4688b09be5fSYuval Mintz 4698b09be5fSYuval Mintz /** 4708b09be5fSYuval Mintz * __bnx2x_vlan_mac_h_pend - Pend an execution step which couldn't run 4718b09be5fSYuval Mintz * 4728b09be5fSYuval Mintz * @bp: device handle 4738b09be5fSYuval Mintz * @o: vlan_mac object 4748b09be5fSYuval Mintz * @ramrod_flags: ramrod flags of missed execution 4758b09be5fSYuval Mintz * 4768b09be5fSYuval Mintz * @details Should be called under execution queue lock. 4778b09be5fSYuval Mintz */ 4788b09be5fSYuval Mintz static void __bnx2x_vlan_mac_h_pend(struct bnx2x *bp, 4798b09be5fSYuval Mintz struct bnx2x_vlan_mac_obj *o, 4808b09be5fSYuval Mintz unsigned long ramrod_flags) 4818b09be5fSYuval Mintz { 4828b09be5fSYuval Mintz o->head_exe_request = true; 4838b09be5fSYuval Mintz o->saved_ramrod_flags = ramrod_flags; 4848b09be5fSYuval Mintz DP(BNX2X_MSG_SP, "Placing pending execution with ramrod flags %lu\n", 4858b09be5fSYuval Mintz ramrod_flags); 4868b09be5fSYuval Mintz } 4878b09be5fSYuval Mintz 4888b09be5fSYuval Mintz /** 4898b09be5fSYuval Mintz * __bnx2x_vlan_mac_h_write_unlock - unlock the vlan mac head list writer lock 4908b09be5fSYuval Mintz * 4918b09be5fSYuval Mintz * @bp: device handle 4928b09be5fSYuval Mintz * @o: vlan_mac object 4938b09be5fSYuval Mintz * 4948b09be5fSYuval Mintz * @details Should be called under execution queue lock. Notice if a pending 4958b09be5fSYuval Mintz * execution exists, it would perform it - possibly releasing and 4968b09be5fSYuval Mintz * reclaiming the execution queue lock. 4978b09be5fSYuval Mintz */ 4988b09be5fSYuval Mintz static void __bnx2x_vlan_mac_h_write_unlock(struct bnx2x *bp, 4998b09be5fSYuval Mintz struct bnx2x_vlan_mac_obj *o) 5008b09be5fSYuval Mintz { 5018b09be5fSYuval Mintz /* It's possible a new pending execution was added since this writer 5028b09be5fSYuval Mintz * executed. If so, execute again. [Ad infinitum] 5038b09be5fSYuval Mintz */ 5048b09be5fSYuval Mintz while (o->head_exe_request) { 5058b09be5fSYuval Mintz DP(BNX2X_MSG_SP, "vlan_mac_lock - writer release encountered a pending request\n"); 5068b09be5fSYuval Mintz __bnx2x_vlan_mac_h_exec_pending(bp, o); 5078b09be5fSYuval Mintz } 5088b09be5fSYuval Mintz } 5098b09be5fSYuval Mintz 5108b09be5fSYuval Mintz /** 5118b09be5fSYuval Mintz * bnx2x_vlan_mac_h_write_unlock - unlock the vlan mac head list writer lock 5128b09be5fSYuval Mintz * 5138b09be5fSYuval Mintz * @bp: device handle 5148b09be5fSYuval Mintz * @o: vlan_mac object 5158b09be5fSYuval Mintz * 5168b09be5fSYuval Mintz * @details Notice if a pending execution exists, it would perform it - 5178b09be5fSYuval Mintz * possibly releasing and reclaiming the execution queue lock. 5188b09be5fSYuval Mintz */ 5198b09be5fSYuval Mintz void bnx2x_vlan_mac_h_write_unlock(struct bnx2x *bp, 5208b09be5fSYuval Mintz struct bnx2x_vlan_mac_obj *o) 5218b09be5fSYuval Mintz { 5228b09be5fSYuval Mintz spin_lock_bh(&o->exe_queue.lock); 5238b09be5fSYuval Mintz __bnx2x_vlan_mac_h_write_unlock(bp, o); 5248b09be5fSYuval Mintz spin_unlock_bh(&o->exe_queue.lock); 5258b09be5fSYuval Mintz } 5268b09be5fSYuval Mintz 5278b09be5fSYuval Mintz /** 5288b09be5fSYuval Mintz * __bnx2x_vlan_mac_h_read_lock - lock the vlan mac head list reader lock 5298b09be5fSYuval Mintz * 5308b09be5fSYuval Mintz * @bp: device handle 5318b09be5fSYuval Mintz * @o: vlan_mac object 5328b09be5fSYuval Mintz * 5338b09be5fSYuval Mintz * @details Should be called under the execution queue lock. May sleep. May 5348b09be5fSYuval Mintz * release and reclaim execution queue lock during its run. 5358b09be5fSYuval Mintz */ 5368b09be5fSYuval Mintz static int __bnx2x_vlan_mac_h_read_lock(struct bnx2x *bp, 5378b09be5fSYuval Mintz struct bnx2x_vlan_mac_obj *o) 5388b09be5fSYuval Mintz { 5398b09be5fSYuval Mintz /* If we got here, we're holding lock --> no WRITER exists */ 5408b09be5fSYuval Mintz o->head_reader++; 5418b09be5fSYuval Mintz DP(BNX2X_MSG_SP, "vlan_mac_lock - locked reader - number %d\n", 5428b09be5fSYuval Mintz o->head_reader); 5438b09be5fSYuval Mintz 5448b09be5fSYuval Mintz return 0; 5458b09be5fSYuval Mintz } 5468b09be5fSYuval Mintz 5478b09be5fSYuval Mintz /** 5488b09be5fSYuval Mintz * bnx2x_vlan_mac_h_read_lock - lock the vlan mac head list reader lock 5498b09be5fSYuval Mintz * 5508b09be5fSYuval Mintz * @bp: device handle 5518b09be5fSYuval Mintz * @o: vlan_mac object 5528b09be5fSYuval Mintz * 5538b09be5fSYuval Mintz * @details May sleep. Claims and releases execution queue lock during its run. 5548b09be5fSYuval Mintz */ 5558b09be5fSYuval Mintz int bnx2x_vlan_mac_h_read_lock(struct bnx2x *bp, 5568b09be5fSYuval Mintz struct bnx2x_vlan_mac_obj *o) 5578b09be5fSYuval Mintz { 5588b09be5fSYuval Mintz int rc; 5598b09be5fSYuval Mintz 5608b09be5fSYuval Mintz spin_lock_bh(&o->exe_queue.lock); 5618b09be5fSYuval Mintz rc = __bnx2x_vlan_mac_h_read_lock(bp, o); 5628b09be5fSYuval Mintz spin_unlock_bh(&o->exe_queue.lock); 5638b09be5fSYuval Mintz 5648b09be5fSYuval Mintz return rc; 5658b09be5fSYuval Mintz } 5668b09be5fSYuval Mintz 5678b09be5fSYuval Mintz /** 5688b09be5fSYuval Mintz * __bnx2x_vlan_mac_h_read_unlock - unlock the vlan mac head list reader lock 5698b09be5fSYuval Mintz * 5708b09be5fSYuval Mintz * @bp: device handle 5718b09be5fSYuval Mintz * @o: vlan_mac object 5728b09be5fSYuval Mintz * 5738b09be5fSYuval Mintz * @details Should be called under execution queue lock. Notice if a pending 5748b09be5fSYuval Mintz * execution exists, it would be performed if this was the last 5758b09be5fSYuval Mintz * reader. possibly releasing and reclaiming the execution queue lock. 5768b09be5fSYuval Mintz */ 5778b09be5fSYuval Mintz static void __bnx2x_vlan_mac_h_read_unlock(struct bnx2x *bp, 5788b09be5fSYuval Mintz struct bnx2x_vlan_mac_obj *o) 5798b09be5fSYuval Mintz { 5808b09be5fSYuval Mintz if (!o->head_reader) { 5818b09be5fSYuval Mintz BNX2X_ERR("Need to release vlan mac reader lock, but lock isn't taken\n"); 5828b09be5fSYuval Mintz #ifdef BNX2X_STOP_ON_ERROR 5838b09be5fSYuval Mintz bnx2x_panic(); 5848b09be5fSYuval Mintz #endif 5858b09be5fSYuval Mintz } else { 5868b09be5fSYuval Mintz o->head_reader--; 5878b09be5fSYuval Mintz DP(BNX2X_MSG_SP, "vlan_mac_lock - decreased readers to %d\n", 5888b09be5fSYuval Mintz o->head_reader); 5898b09be5fSYuval Mintz } 5908b09be5fSYuval Mintz 5918b09be5fSYuval Mintz /* It's possible a new pending execution was added, and that this reader 5928b09be5fSYuval Mintz * was last - if so we need to execute the command. 5938b09be5fSYuval Mintz */ 5948b09be5fSYuval Mintz if (!o->head_reader && o->head_exe_request) { 5958b09be5fSYuval Mintz DP(BNX2X_MSG_SP, "vlan_mac_lock - reader release encountered a pending request\n"); 5968b09be5fSYuval Mintz 5978b09be5fSYuval Mintz /* Writer release will do the trick */ 5988b09be5fSYuval Mintz __bnx2x_vlan_mac_h_write_unlock(bp, o); 5998b09be5fSYuval Mintz } 6008b09be5fSYuval Mintz } 6018b09be5fSYuval Mintz 6028b09be5fSYuval Mintz /** 6038b09be5fSYuval Mintz * bnx2x_vlan_mac_h_read_unlock - unlock the vlan mac head list reader lock 6048b09be5fSYuval Mintz * 6058b09be5fSYuval Mintz * @bp: device handle 6068b09be5fSYuval Mintz * @o: vlan_mac object 6078b09be5fSYuval Mintz * 6088b09be5fSYuval Mintz * @details Notice if a pending execution exists, it would be performed if this 6098b09be5fSYuval Mintz * was the last reader. Claims and releases the execution queue lock 6108b09be5fSYuval Mintz * during its run. 6118b09be5fSYuval Mintz */ 6128b09be5fSYuval Mintz void bnx2x_vlan_mac_h_read_unlock(struct bnx2x *bp, 6138b09be5fSYuval Mintz struct bnx2x_vlan_mac_obj *o) 6148b09be5fSYuval Mintz { 6158b09be5fSYuval Mintz spin_lock_bh(&o->exe_queue.lock); 6168b09be5fSYuval Mintz __bnx2x_vlan_mac_h_read_unlock(bp, o); 6178b09be5fSYuval Mintz spin_unlock_bh(&o->exe_queue.lock); 6188b09be5fSYuval Mintz } 6198b09be5fSYuval Mintz 620ed5162a0SAriel Elior static int bnx2x_get_n_elements(struct bnx2x *bp, struct bnx2x_vlan_mac_obj *o, 6213ec9f9caSAriel Elior int n, u8 *base, u8 stride, u8 size) 622ed5162a0SAriel Elior { 623ed5162a0SAriel Elior struct bnx2x_vlan_mac_registry_elem *pos; 6243ec9f9caSAriel Elior u8 *next = base; 625ed5162a0SAriel Elior int counter = 0; 6268b09be5fSYuval Mintz int read_lock; 6278b09be5fSYuval Mintz 6288b09be5fSYuval Mintz DP(BNX2X_MSG_SP, "get_n_elements - taking vlan_mac_lock (reader)\n"); 6298b09be5fSYuval Mintz read_lock = bnx2x_vlan_mac_h_read_lock(bp, o); 6308b09be5fSYuval Mintz if (read_lock != 0) 6318b09be5fSYuval Mintz BNX2X_ERR("get_n_elements failed to get vlan mac reader lock; Access without lock\n"); 632ed5162a0SAriel Elior 633ed5162a0SAriel Elior /* traverse list */ 634ed5162a0SAriel Elior list_for_each_entry(pos, &o->head, link) { 635ed5162a0SAriel Elior if (counter < n) { 6363ec9f9caSAriel Elior memcpy(next, &pos->u, size); 637ed5162a0SAriel Elior counter++; 6383ec9f9caSAriel Elior DP(BNX2X_MSG_SP, "copied element number %d to address %p element was:\n", 6393ec9f9caSAriel Elior counter, next); 6403ec9f9caSAriel Elior next += stride + size; 641ed5162a0SAriel Elior } 642ed5162a0SAriel Elior } 6438b09be5fSYuval Mintz 6448b09be5fSYuval Mintz if (read_lock == 0) { 6458b09be5fSYuval Mintz DP(BNX2X_MSG_SP, "get_n_elements - releasing vlan_mac_lock (reader)\n"); 6468b09be5fSYuval Mintz bnx2x_vlan_mac_h_read_unlock(bp, o); 6478b09be5fSYuval Mintz } 6488b09be5fSYuval Mintz 649ed5162a0SAriel Elior return counter * ETH_ALEN; 650ed5162a0SAriel Elior } 651ed5162a0SAriel Elior 652adfc5217SJeff Kirsher /* check_add() callbacks */ 65351c1a580SMerav Sicron static int bnx2x_check_mac_add(struct bnx2x *bp, 65451c1a580SMerav Sicron struct bnx2x_vlan_mac_obj *o, 655adfc5217SJeff Kirsher union bnx2x_classification_ramrod_data *data) 656adfc5217SJeff Kirsher { 657adfc5217SJeff Kirsher struct bnx2x_vlan_mac_registry_elem *pos; 658adfc5217SJeff Kirsher 65951c1a580SMerav Sicron DP(BNX2X_MSG_SP, "Checking MAC %pM for ADD command\n", data->mac.mac); 66051c1a580SMerav Sicron 661adfc5217SJeff Kirsher if (!is_valid_ether_addr(data->mac.mac)) 662adfc5217SJeff Kirsher return -EINVAL; 663adfc5217SJeff Kirsher 664adfc5217SJeff Kirsher /* Check if a requested MAC already exists */ 665adfc5217SJeff Kirsher list_for_each_entry(pos, &o->head, link) 66691226790SDmitry Kravkov if (!memcmp(data->mac.mac, pos->u.mac.mac, ETH_ALEN) && 66791226790SDmitry Kravkov (data->mac.is_inner_mac == pos->u.mac.is_inner_mac)) 668adfc5217SJeff Kirsher return -EEXIST; 669adfc5217SJeff Kirsher 670adfc5217SJeff Kirsher return 0; 671adfc5217SJeff Kirsher } 672adfc5217SJeff Kirsher 67351c1a580SMerav Sicron static int bnx2x_check_vlan_add(struct bnx2x *bp, 67451c1a580SMerav Sicron struct bnx2x_vlan_mac_obj *o, 675adfc5217SJeff Kirsher union bnx2x_classification_ramrod_data *data) 676adfc5217SJeff Kirsher { 677adfc5217SJeff Kirsher struct bnx2x_vlan_mac_registry_elem *pos; 678adfc5217SJeff Kirsher 67951c1a580SMerav Sicron DP(BNX2X_MSG_SP, "Checking VLAN %d for ADD command\n", data->vlan.vlan); 68051c1a580SMerav Sicron 681adfc5217SJeff Kirsher list_for_each_entry(pos, &o->head, link) 682adfc5217SJeff Kirsher if (data->vlan.vlan == pos->u.vlan.vlan) 683adfc5217SJeff Kirsher return -EEXIST; 684adfc5217SJeff Kirsher 685adfc5217SJeff Kirsher return 0; 686adfc5217SJeff Kirsher } 687adfc5217SJeff Kirsher 68851c1a580SMerav Sicron static int bnx2x_check_vlan_mac_add(struct bnx2x *bp, 68951c1a580SMerav Sicron struct bnx2x_vlan_mac_obj *o, 690adfc5217SJeff Kirsher union bnx2x_classification_ramrod_data *data) 691adfc5217SJeff Kirsher { 692adfc5217SJeff Kirsher struct bnx2x_vlan_mac_registry_elem *pos; 693adfc5217SJeff Kirsher 69451c1a580SMerav Sicron DP(BNX2X_MSG_SP, "Checking VLAN_MAC (%pM, %d) for ADD command\n", 69551c1a580SMerav Sicron data->vlan_mac.mac, data->vlan_mac.vlan); 69651c1a580SMerav Sicron 697adfc5217SJeff Kirsher list_for_each_entry(pos, &o->head, link) 698adfc5217SJeff Kirsher if ((data->vlan_mac.vlan == pos->u.vlan_mac.vlan) && 699adfc5217SJeff Kirsher (!memcmp(data->vlan_mac.mac, pos->u.vlan_mac.mac, 70091226790SDmitry Kravkov ETH_ALEN)) && 70191226790SDmitry Kravkov (data->vlan_mac.is_inner_mac == 70291226790SDmitry Kravkov pos->u.vlan_mac.is_inner_mac)) 703adfc5217SJeff Kirsher return -EEXIST; 704adfc5217SJeff Kirsher 705adfc5217SJeff Kirsher return 0; 706adfc5217SJeff Kirsher } 707adfc5217SJeff Kirsher 708adfc5217SJeff Kirsher /* check_del() callbacks */ 709adfc5217SJeff Kirsher static struct bnx2x_vlan_mac_registry_elem * 71051c1a580SMerav Sicron bnx2x_check_mac_del(struct bnx2x *bp, 71151c1a580SMerav Sicron struct bnx2x_vlan_mac_obj *o, 712adfc5217SJeff Kirsher union bnx2x_classification_ramrod_data *data) 713adfc5217SJeff Kirsher { 714adfc5217SJeff Kirsher struct bnx2x_vlan_mac_registry_elem *pos; 715adfc5217SJeff Kirsher 71651c1a580SMerav Sicron DP(BNX2X_MSG_SP, "Checking MAC %pM for DEL command\n", data->mac.mac); 71751c1a580SMerav Sicron 718adfc5217SJeff Kirsher list_for_each_entry(pos, &o->head, link) 71991226790SDmitry Kravkov if ((!memcmp(data->mac.mac, pos->u.mac.mac, ETH_ALEN)) && 72091226790SDmitry Kravkov (data->mac.is_inner_mac == pos->u.mac.is_inner_mac)) 721adfc5217SJeff Kirsher return pos; 722adfc5217SJeff Kirsher 723adfc5217SJeff Kirsher return NULL; 724adfc5217SJeff Kirsher } 725adfc5217SJeff Kirsher 726adfc5217SJeff Kirsher static struct bnx2x_vlan_mac_registry_elem * 72751c1a580SMerav Sicron bnx2x_check_vlan_del(struct bnx2x *bp, 72851c1a580SMerav Sicron struct bnx2x_vlan_mac_obj *o, 729adfc5217SJeff Kirsher union bnx2x_classification_ramrod_data *data) 730adfc5217SJeff Kirsher { 731adfc5217SJeff Kirsher struct bnx2x_vlan_mac_registry_elem *pos; 732adfc5217SJeff Kirsher 73351c1a580SMerav Sicron DP(BNX2X_MSG_SP, "Checking VLAN %d for DEL command\n", data->vlan.vlan); 73451c1a580SMerav Sicron 735adfc5217SJeff Kirsher list_for_each_entry(pos, &o->head, link) 736adfc5217SJeff Kirsher if (data->vlan.vlan == pos->u.vlan.vlan) 737adfc5217SJeff Kirsher return pos; 738adfc5217SJeff Kirsher 739adfc5217SJeff Kirsher return NULL; 740adfc5217SJeff Kirsher } 741adfc5217SJeff Kirsher 742adfc5217SJeff Kirsher static struct bnx2x_vlan_mac_registry_elem * 74351c1a580SMerav Sicron bnx2x_check_vlan_mac_del(struct bnx2x *bp, 74451c1a580SMerav Sicron struct bnx2x_vlan_mac_obj *o, 745adfc5217SJeff Kirsher union bnx2x_classification_ramrod_data *data) 746adfc5217SJeff Kirsher { 747adfc5217SJeff Kirsher struct bnx2x_vlan_mac_registry_elem *pos; 748adfc5217SJeff Kirsher 74951c1a580SMerav Sicron DP(BNX2X_MSG_SP, "Checking VLAN_MAC (%pM, %d) for DEL command\n", 75051c1a580SMerav Sicron data->vlan_mac.mac, data->vlan_mac.vlan); 75151c1a580SMerav Sicron 752adfc5217SJeff Kirsher list_for_each_entry(pos, &o->head, link) 753adfc5217SJeff Kirsher if ((data->vlan_mac.vlan == pos->u.vlan_mac.vlan) && 754adfc5217SJeff Kirsher (!memcmp(data->vlan_mac.mac, pos->u.vlan_mac.mac, 75591226790SDmitry Kravkov ETH_ALEN)) && 75691226790SDmitry Kravkov (data->vlan_mac.is_inner_mac == 75791226790SDmitry Kravkov pos->u.vlan_mac.is_inner_mac)) 758adfc5217SJeff Kirsher return pos; 759adfc5217SJeff Kirsher 760adfc5217SJeff Kirsher return NULL; 761adfc5217SJeff Kirsher } 762adfc5217SJeff Kirsher 763adfc5217SJeff Kirsher /* check_move() callback */ 76451c1a580SMerav Sicron static bool bnx2x_check_move(struct bnx2x *bp, 76551c1a580SMerav Sicron struct bnx2x_vlan_mac_obj *src_o, 766adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *dst_o, 767adfc5217SJeff Kirsher union bnx2x_classification_ramrod_data *data) 768adfc5217SJeff Kirsher { 769adfc5217SJeff Kirsher struct bnx2x_vlan_mac_registry_elem *pos; 770adfc5217SJeff Kirsher int rc; 771adfc5217SJeff Kirsher 772adfc5217SJeff Kirsher /* Check if we can delete the requested configuration from the first 773adfc5217SJeff Kirsher * object. 774adfc5217SJeff Kirsher */ 77551c1a580SMerav Sicron pos = src_o->check_del(bp, src_o, data); 776adfc5217SJeff Kirsher 777adfc5217SJeff Kirsher /* check if configuration can be added */ 77851c1a580SMerav Sicron rc = dst_o->check_add(bp, dst_o, data); 779adfc5217SJeff Kirsher 780adfc5217SJeff Kirsher /* If this classification can not be added (is already set) 781adfc5217SJeff Kirsher * or can't be deleted - return an error. 782adfc5217SJeff Kirsher */ 783adfc5217SJeff Kirsher if (rc || !pos) 784adfc5217SJeff Kirsher return false; 785adfc5217SJeff Kirsher 786adfc5217SJeff Kirsher return true; 787adfc5217SJeff Kirsher } 788adfc5217SJeff Kirsher 789adfc5217SJeff Kirsher static bool bnx2x_check_move_always_err( 79051c1a580SMerav Sicron struct bnx2x *bp, 791adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *src_o, 792adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *dst_o, 793adfc5217SJeff Kirsher union bnx2x_classification_ramrod_data *data) 794adfc5217SJeff Kirsher { 795adfc5217SJeff Kirsher return false; 796adfc5217SJeff Kirsher } 797adfc5217SJeff Kirsher 798adfc5217SJeff Kirsher static inline u8 bnx2x_vlan_mac_get_rx_tx_flag(struct bnx2x_vlan_mac_obj *o) 799adfc5217SJeff Kirsher { 800adfc5217SJeff Kirsher struct bnx2x_raw_obj *raw = &o->raw; 801adfc5217SJeff Kirsher u8 rx_tx_flag = 0; 802adfc5217SJeff Kirsher 803adfc5217SJeff Kirsher if ((raw->obj_type == BNX2X_OBJ_TYPE_TX) || 804adfc5217SJeff Kirsher (raw->obj_type == BNX2X_OBJ_TYPE_RX_TX)) 805adfc5217SJeff Kirsher rx_tx_flag |= ETH_CLASSIFY_CMD_HEADER_TX_CMD; 806adfc5217SJeff Kirsher 807adfc5217SJeff Kirsher if ((raw->obj_type == BNX2X_OBJ_TYPE_RX) || 808adfc5217SJeff Kirsher (raw->obj_type == BNX2X_OBJ_TYPE_RX_TX)) 809adfc5217SJeff Kirsher rx_tx_flag |= ETH_CLASSIFY_CMD_HEADER_RX_CMD; 810adfc5217SJeff Kirsher 811adfc5217SJeff Kirsher return rx_tx_flag; 812adfc5217SJeff Kirsher } 813adfc5217SJeff Kirsher 814a3348722SBarak Witkowski void bnx2x_set_mac_in_nig(struct bnx2x *bp, 815adfc5217SJeff Kirsher bool add, unsigned char *dev_addr, int index) 816adfc5217SJeff Kirsher { 817adfc5217SJeff Kirsher u32 wb_data[2]; 818adfc5217SJeff Kirsher u32 reg_offset = BP_PORT(bp) ? NIG_REG_LLH1_FUNC_MEM : 819adfc5217SJeff Kirsher NIG_REG_LLH0_FUNC_MEM; 820adfc5217SJeff Kirsher 821a3348722SBarak Witkowski if (!IS_MF_SI(bp) && !IS_MF_AFEX(bp)) 822a3348722SBarak Witkowski return; 823a3348722SBarak Witkowski 824a3348722SBarak Witkowski if (index > BNX2X_LLH_CAM_MAX_PF_LINE) 825adfc5217SJeff Kirsher return; 826adfc5217SJeff Kirsher 827adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "Going to %s LLH configuration at entry %d\n", 828adfc5217SJeff Kirsher (add ? "ADD" : "DELETE"), index); 829adfc5217SJeff Kirsher 830adfc5217SJeff Kirsher if (add) { 831adfc5217SJeff Kirsher /* LLH_FUNC_MEM is a u64 WB register */ 832adfc5217SJeff Kirsher reg_offset += 8*index; 833adfc5217SJeff Kirsher 834adfc5217SJeff Kirsher wb_data[0] = ((dev_addr[2] << 24) | (dev_addr[3] << 16) | 835adfc5217SJeff Kirsher (dev_addr[4] << 8) | dev_addr[5]); 836adfc5217SJeff Kirsher wb_data[1] = ((dev_addr[0] << 8) | dev_addr[1]); 837adfc5217SJeff Kirsher 838adfc5217SJeff Kirsher REG_WR_DMAE(bp, reg_offset, wb_data, 2); 839adfc5217SJeff Kirsher } 840adfc5217SJeff Kirsher 841adfc5217SJeff Kirsher REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_FUNC_MEM_ENABLE : 842adfc5217SJeff Kirsher NIG_REG_LLH0_FUNC_MEM_ENABLE) + 4*index, add); 843adfc5217SJeff Kirsher } 844adfc5217SJeff Kirsher 845adfc5217SJeff Kirsher /** 846adfc5217SJeff Kirsher * bnx2x_vlan_mac_set_cmd_hdr_e2 - set a header in a single classify ramrod 847adfc5217SJeff Kirsher * 848adfc5217SJeff Kirsher * @bp: device handle 849adfc5217SJeff Kirsher * @o: queue for which we want to configure this rule 850adfc5217SJeff Kirsher * @add: if true the command is an ADD command, DEL otherwise 851adfc5217SJeff Kirsher * @opcode: CLASSIFY_RULE_OPCODE_XXX 852adfc5217SJeff Kirsher * @hdr: pointer to a header to setup 853adfc5217SJeff Kirsher * 854adfc5217SJeff Kirsher */ 855adfc5217SJeff Kirsher static inline void bnx2x_vlan_mac_set_cmd_hdr_e2(struct bnx2x *bp, 856adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *o, bool add, int opcode, 857adfc5217SJeff Kirsher struct eth_classify_cmd_header *hdr) 858adfc5217SJeff Kirsher { 859adfc5217SJeff Kirsher struct bnx2x_raw_obj *raw = &o->raw; 860adfc5217SJeff Kirsher 861adfc5217SJeff Kirsher hdr->client_id = raw->cl_id; 862adfc5217SJeff Kirsher hdr->func_id = raw->func_id; 863adfc5217SJeff Kirsher 864adfc5217SJeff Kirsher /* Rx or/and Tx (internal switching) configuration ? */ 865adfc5217SJeff Kirsher hdr->cmd_general_data |= 866adfc5217SJeff Kirsher bnx2x_vlan_mac_get_rx_tx_flag(o); 867adfc5217SJeff Kirsher 868adfc5217SJeff Kirsher if (add) 869adfc5217SJeff Kirsher hdr->cmd_general_data |= ETH_CLASSIFY_CMD_HEADER_IS_ADD; 870adfc5217SJeff Kirsher 871adfc5217SJeff Kirsher hdr->cmd_general_data |= 872adfc5217SJeff Kirsher (opcode << ETH_CLASSIFY_CMD_HEADER_OPCODE_SHIFT); 873adfc5217SJeff Kirsher } 874adfc5217SJeff Kirsher 875adfc5217SJeff Kirsher /** 876adfc5217SJeff Kirsher * bnx2x_vlan_mac_set_rdata_hdr_e2 - set the classify ramrod data header 877adfc5217SJeff Kirsher * 878adfc5217SJeff Kirsher * @cid: connection id 879adfc5217SJeff Kirsher * @type: BNX2X_FILTER_XXX_PENDING 88016a5fd92SYuval Mintz * @hdr: pointer to header to setup 881adfc5217SJeff Kirsher * @rule_cnt: 882adfc5217SJeff Kirsher * 883adfc5217SJeff Kirsher * currently we always configure one rule and echo field to contain a CID and an 884adfc5217SJeff Kirsher * opcode type. 885adfc5217SJeff Kirsher */ 886adfc5217SJeff Kirsher static inline void bnx2x_vlan_mac_set_rdata_hdr_e2(u32 cid, int type, 887adfc5217SJeff Kirsher struct eth_classify_header *hdr, int rule_cnt) 888adfc5217SJeff Kirsher { 88986564c3fSYuval Mintz hdr->echo = cpu_to_le32((cid & BNX2X_SWCID_MASK) | 89086564c3fSYuval Mintz (type << BNX2X_SWCID_SHIFT)); 891adfc5217SJeff Kirsher hdr->rule_cnt = (u8)rule_cnt; 892adfc5217SJeff Kirsher } 893adfc5217SJeff Kirsher 894adfc5217SJeff Kirsher /* hw_config() callbacks */ 895adfc5217SJeff Kirsher static void bnx2x_set_one_mac_e2(struct bnx2x *bp, 896adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *o, 897adfc5217SJeff Kirsher struct bnx2x_exeq_elem *elem, int rule_idx, 898adfc5217SJeff Kirsher int cam_offset) 899adfc5217SJeff Kirsher { 900adfc5217SJeff Kirsher struct bnx2x_raw_obj *raw = &o->raw; 901adfc5217SJeff Kirsher struct eth_classify_rules_ramrod_data *data = 902adfc5217SJeff Kirsher (struct eth_classify_rules_ramrod_data *)(raw->rdata); 903adfc5217SJeff Kirsher int rule_cnt = rule_idx + 1, cmd = elem->cmd_data.vlan_mac.cmd; 904adfc5217SJeff Kirsher union eth_classify_rule_cmd *rule_entry = &data->rules[rule_idx]; 905adfc5217SJeff Kirsher bool add = (cmd == BNX2X_VLAN_MAC_ADD) ? true : false; 906adfc5217SJeff Kirsher unsigned long *vlan_mac_flags = &elem->cmd_data.vlan_mac.vlan_mac_flags; 907adfc5217SJeff Kirsher u8 *mac = elem->cmd_data.vlan_mac.u.mac.mac; 908adfc5217SJeff Kirsher 90916a5fd92SYuval Mintz /* Set LLH CAM entry: currently only iSCSI and ETH macs are 910adfc5217SJeff Kirsher * relevant. In addition, current implementation is tuned for a 911adfc5217SJeff Kirsher * single ETH MAC. 912adfc5217SJeff Kirsher * 913adfc5217SJeff Kirsher * When multiple unicast ETH MACs PF configuration in switch 914adfc5217SJeff Kirsher * independent mode is required (NetQ, multiple netdev MACs, 915adfc5217SJeff Kirsher * etc.), consider better utilisation of 8 per function MAC 916adfc5217SJeff Kirsher * entries in the LLH register. There is also 917adfc5217SJeff Kirsher * NIG_REG_P[01]_LLH_FUNC_MEM2 registers that complete the 918adfc5217SJeff Kirsher * total number of CAM entries to 16. 919adfc5217SJeff Kirsher * 920adfc5217SJeff Kirsher * Currently we won't configure NIG for MACs other than a primary ETH 921adfc5217SJeff Kirsher * MAC and iSCSI L2 MAC. 922adfc5217SJeff Kirsher * 923adfc5217SJeff Kirsher * If this MAC is moving from one Queue to another, no need to change 924adfc5217SJeff Kirsher * NIG configuration. 925adfc5217SJeff Kirsher */ 926adfc5217SJeff Kirsher if (cmd != BNX2X_VLAN_MAC_MOVE) { 927adfc5217SJeff Kirsher if (test_bit(BNX2X_ISCSI_ETH_MAC, vlan_mac_flags)) 928adfc5217SJeff Kirsher bnx2x_set_mac_in_nig(bp, add, mac, 9290a52fd01SYuval Mintz BNX2X_LLH_CAM_ISCSI_ETH_LINE); 930adfc5217SJeff Kirsher else if (test_bit(BNX2X_ETH_MAC, vlan_mac_flags)) 9310a52fd01SYuval Mintz bnx2x_set_mac_in_nig(bp, add, mac, 9320a52fd01SYuval Mintz BNX2X_LLH_CAM_ETH_LINE); 933adfc5217SJeff Kirsher } 934adfc5217SJeff Kirsher 935adfc5217SJeff Kirsher /* Reset the ramrod data buffer for the first rule */ 936adfc5217SJeff Kirsher if (rule_idx == 0) 937adfc5217SJeff Kirsher memset(data, 0, sizeof(*data)); 938adfc5217SJeff Kirsher 939adfc5217SJeff Kirsher /* Setup a command header */ 940adfc5217SJeff Kirsher bnx2x_vlan_mac_set_cmd_hdr_e2(bp, o, add, CLASSIFY_RULE_OPCODE_MAC, 941adfc5217SJeff Kirsher &rule_entry->mac.header); 942adfc5217SJeff Kirsher 9430f9dad10SJoe Perches DP(BNX2X_MSG_SP, "About to %s MAC %pM for Queue %d\n", 94451c1a580SMerav Sicron (add ? "add" : "delete"), mac, raw->cl_id); 945adfc5217SJeff Kirsher 946adfc5217SJeff Kirsher /* Set a MAC itself */ 947adfc5217SJeff Kirsher bnx2x_set_fw_mac_addr(&rule_entry->mac.mac_msb, 948adfc5217SJeff Kirsher &rule_entry->mac.mac_mid, 949adfc5217SJeff Kirsher &rule_entry->mac.mac_lsb, mac); 95091226790SDmitry Kravkov rule_entry->mac.inner_mac = 95191226790SDmitry Kravkov cpu_to_le16(elem->cmd_data.vlan_mac.u.mac.is_inner_mac); 952adfc5217SJeff Kirsher 953adfc5217SJeff Kirsher /* MOVE: Add a rule that will add this MAC to the target Queue */ 954adfc5217SJeff Kirsher if (cmd == BNX2X_VLAN_MAC_MOVE) { 955adfc5217SJeff Kirsher rule_entry++; 956adfc5217SJeff Kirsher rule_cnt++; 957adfc5217SJeff Kirsher 958adfc5217SJeff Kirsher /* Setup ramrod data */ 959adfc5217SJeff Kirsher bnx2x_vlan_mac_set_cmd_hdr_e2(bp, 960adfc5217SJeff Kirsher elem->cmd_data.vlan_mac.target_obj, 961adfc5217SJeff Kirsher true, CLASSIFY_RULE_OPCODE_MAC, 962adfc5217SJeff Kirsher &rule_entry->mac.header); 963adfc5217SJeff Kirsher 964adfc5217SJeff Kirsher /* Set a MAC itself */ 965adfc5217SJeff Kirsher bnx2x_set_fw_mac_addr(&rule_entry->mac.mac_msb, 966adfc5217SJeff Kirsher &rule_entry->mac.mac_mid, 967adfc5217SJeff Kirsher &rule_entry->mac.mac_lsb, mac); 96891226790SDmitry Kravkov rule_entry->mac.inner_mac = 96991226790SDmitry Kravkov cpu_to_le16(elem->cmd_data.vlan_mac. 97091226790SDmitry Kravkov u.mac.is_inner_mac); 971adfc5217SJeff Kirsher } 972adfc5217SJeff Kirsher 973adfc5217SJeff Kirsher /* Set the ramrod data header */ 974adfc5217SJeff Kirsher /* TODO: take this to the higher level in order to prevent multiple 975adfc5217SJeff Kirsher writing */ 976adfc5217SJeff Kirsher bnx2x_vlan_mac_set_rdata_hdr_e2(raw->cid, raw->state, &data->header, 977adfc5217SJeff Kirsher rule_cnt); 978adfc5217SJeff Kirsher } 979adfc5217SJeff Kirsher 980adfc5217SJeff Kirsher /** 981adfc5217SJeff Kirsher * bnx2x_vlan_mac_set_rdata_hdr_e1x - set a header in a single classify ramrod 982adfc5217SJeff Kirsher * 983adfc5217SJeff Kirsher * @bp: device handle 984adfc5217SJeff Kirsher * @o: queue 985adfc5217SJeff Kirsher * @type: 986adfc5217SJeff Kirsher * @cam_offset: offset in cam memory 987adfc5217SJeff Kirsher * @hdr: pointer to a header to setup 988adfc5217SJeff Kirsher * 989adfc5217SJeff Kirsher * E1/E1H 990adfc5217SJeff Kirsher */ 991adfc5217SJeff Kirsher static inline void bnx2x_vlan_mac_set_rdata_hdr_e1x(struct bnx2x *bp, 992adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *o, int type, int cam_offset, 993adfc5217SJeff Kirsher struct mac_configuration_hdr *hdr) 994adfc5217SJeff Kirsher { 995adfc5217SJeff Kirsher struct bnx2x_raw_obj *r = &o->raw; 996adfc5217SJeff Kirsher 997adfc5217SJeff Kirsher hdr->length = 1; 998adfc5217SJeff Kirsher hdr->offset = (u8)cam_offset; 99986564c3fSYuval Mintz hdr->client_id = cpu_to_le16(0xff); 100086564c3fSYuval Mintz hdr->echo = cpu_to_le32((r->cid & BNX2X_SWCID_MASK) | 100186564c3fSYuval Mintz (type << BNX2X_SWCID_SHIFT)); 1002adfc5217SJeff Kirsher } 1003adfc5217SJeff Kirsher 1004adfc5217SJeff Kirsher static inline void bnx2x_vlan_mac_set_cfg_entry_e1x(struct bnx2x *bp, 1005adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *o, bool add, int opcode, u8 *mac, 1006adfc5217SJeff Kirsher u16 vlan_id, struct mac_configuration_entry *cfg_entry) 1007adfc5217SJeff Kirsher { 1008adfc5217SJeff Kirsher struct bnx2x_raw_obj *r = &o->raw; 1009adfc5217SJeff Kirsher u32 cl_bit_vec = (1 << r->cl_id); 1010adfc5217SJeff Kirsher 1011adfc5217SJeff Kirsher cfg_entry->clients_bit_vector = cpu_to_le32(cl_bit_vec); 1012adfc5217SJeff Kirsher cfg_entry->pf_id = r->func_id; 1013adfc5217SJeff Kirsher cfg_entry->vlan_id = cpu_to_le16(vlan_id); 1014adfc5217SJeff Kirsher 1015adfc5217SJeff Kirsher if (add) { 1016adfc5217SJeff Kirsher SET_FLAG(cfg_entry->flags, MAC_CONFIGURATION_ENTRY_ACTION_TYPE, 1017adfc5217SJeff Kirsher T_ETH_MAC_COMMAND_SET); 1018adfc5217SJeff Kirsher SET_FLAG(cfg_entry->flags, 1019adfc5217SJeff Kirsher MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE, opcode); 1020adfc5217SJeff Kirsher 1021adfc5217SJeff Kirsher /* Set a MAC in a ramrod data */ 1022adfc5217SJeff Kirsher bnx2x_set_fw_mac_addr(&cfg_entry->msb_mac_addr, 1023adfc5217SJeff Kirsher &cfg_entry->middle_mac_addr, 1024adfc5217SJeff Kirsher &cfg_entry->lsb_mac_addr, mac); 1025adfc5217SJeff Kirsher } else 1026adfc5217SJeff Kirsher SET_FLAG(cfg_entry->flags, MAC_CONFIGURATION_ENTRY_ACTION_TYPE, 1027adfc5217SJeff Kirsher T_ETH_MAC_COMMAND_INVALIDATE); 1028adfc5217SJeff Kirsher } 1029adfc5217SJeff Kirsher 1030adfc5217SJeff Kirsher static inline void bnx2x_vlan_mac_set_rdata_e1x(struct bnx2x *bp, 1031adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *o, int type, int cam_offset, bool add, 1032adfc5217SJeff Kirsher u8 *mac, u16 vlan_id, int opcode, struct mac_configuration_cmd *config) 1033adfc5217SJeff Kirsher { 1034adfc5217SJeff Kirsher struct mac_configuration_entry *cfg_entry = &config->config_table[0]; 1035adfc5217SJeff Kirsher struct bnx2x_raw_obj *raw = &o->raw; 1036adfc5217SJeff Kirsher 1037adfc5217SJeff Kirsher bnx2x_vlan_mac_set_rdata_hdr_e1x(bp, o, type, cam_offset, 1038adfc5217SJeff Kirsher &config->hdr); 1039adfc5217SJeff Kirsher bnx2x_vlan_mac_set_cfg_entry_e1x(bp, o, add, opcode, mac, vlan_id, 1040adfc5217SJeff Kirsher cfg_entry); 1041adfc5217SJeff Kirsher 10420f9dad10SJoe Perches DP(BNX2X_MSG_SP, "%s MAC %pM CLID %d CAM offset %d\n", 104351c1a580SMerav Sicron (add ? "setting" : "clearing"), 10440f9dad10SJoe Perches mac, raw->cl_id, cam_offset); 1045adfc5217SJeff Kirsher } 1046adfc5217SJeff Kirsher 1047adfc5217SJeff Kirsher /** 1048adfc5217SJeff Kirsher * bnx2x_set_one_mac_e1x - fill a single MAC rule ramrod data 1049adfc5217SJeff Kirsher * 1050adfc5217SJeff Kirsher * @bp: device handle 1051adfc5217SJeff Kirsher * @o: bnx2x_vlan_mac_obj 1052adfc5217SJeff Kirsher * @elem: bnx2x_exeq_elem 1053adfc5217SJeff Kirsher * @rule_idx: rule_idx 1054adfc5217SJeff Kirsher * @cam_offset: cam_offset 1055adfc5217SJeff Kirsher */ 1056adfc5217SJeff Kirsher static void bnx2x_set_one_mac_e1x(struct bnx2x *bp, 1057adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *o, 1058adfc5217SJeff Kirsher struct bnx2x_exeq_elem *elem, int rule_idx, 1059adfc5217SJeff Kirsher int cam_offset) 1060adfc5217SJeff Kirsher { 1061adfc5217SJeff Kirsher struct bnx2x_raw_obj *raw = &o->raw; 1062adfc5217SJeff Kirsher struct mac_configuration_cmd *config = 1063adfc5217SJeff Kirsher (struct mac_configuration_cmd *)(raw->rdata); 106416a5fd92SYuval Mintz /* 57710 and 57711 do not support MOVE command, 1065adfc5217SJeff Kirsher * so it's either ADD or DEL 1066adfc5217SJeff Kirsher */ 1067adfc5217SJeff Kirsher bool add = (elem->cmd_data.vlan_mac.cmd == BNX2X_VLAN_MAC_ADD) ? 1068adfc5217SJeff Kirsher true : false; 1069adfc5217SJeff Kirsher 1070adfc5217SJeff Kirsher /* Reset the ramrod data buffer */ 1071adfc5217SJeff Kirsher memset(config, 0, sizeof(*config)); 1072adfc5217SJeff Kirsher 107333ac338cSYuval Mintz bnx2x_vlan_mac_set_rdata_e1x(bp, o, raw->state, 1074adfc5217SJeff Kirsher cam_offset, add, 1075adfc5217SJeff Kirsher elem->cmd_data.vlan_mac.u.mac.mac, 0, 1076adfc5217SJeff Kirsher ETH_VLAN_FILTER_ANY_VLAN, config); 1077adfc5217SJeff Kirsher } 1078adfc5217SJeff Kirsher 1079adfc5217SJeff Kirsher static void bnx2x_set_one_vlan_e2(struct bnx2x *bp, 1080adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *o, 1081adfc5217SJeff Kirsher struct bnx2x_exeq_elem *elem, int rule_idx, 1082adfc5217SJeff Kirsher int cam_offset) 1083adfc5217SJeff Kirsher { 1084adfc5217SJeff Kirsher struct bnx2x_raw_obj *raw = &o->raw; 1085adfc5217SJeff Kirsher struct eth_classify_rules_ramrod_data *data = 1086adfc5217SJeff Kirsher (struct eth_classify_rules_ramrod_data *)(raw->rdata); 1087adfc5217SJeff Kirsher int rule_cnt = rule_idx + 1; 1088adfc5217SJeff Kirsher union eth_classify_rule_cmd *rule_entry = &data->rules[rule_idx]; 108986564c3fSYuval Mintz enum bnx2x_vlan_mac_cmd cmd = elem->cmd_data.vlan_mac.cmd; 1090adfc5217SJeff Kirsher bool add = (cmd == BNX2X_VLAN_MAC_ADD) ? true : false; 1091adfc5217SJeff Kirsher u16 vlan = elem->cmd_data.vlan_mac.u.vlan.vlan; 1092adfc5217SJeff Kirsher 1093adfc5217SJeff Kirsher /* Reset the ramrod data buffer for the first rule */ 1094adfc5217SJeff Kirsher if (rule_idx == 0) 1095adfc5217SJeff Kirsher memset(data, 0, sizeof(*data)); 1096adfc5217SJeff Kirsher 1097adfc5217SJeff Kirsher /* Set a rule header */ 1098adfc5217SJeff Kirsher bnx2x_vlan_mac_set_cmd_hdr_e2(bp, o, add, CLASSIFY_RULE_OPCODE_VLAN, 1099adfc5217SJeff Kirsher &rule_entry->vlan.header); 1100adfc5217SJeff Kirsher 1101adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "About to %s VLAN %d\n", (add ? "add" : "delete"), 1102adfc5217SJeff Kirsher vlan); 1103adfc5217SJeff Kirsher 1104adfc5217SJeff Kirsher /* Set a VLAN itself */ 1105adfc5217SJeff Kirsher rule_entry->vlan.vlan = cpu_to_le16(vlan); 1106adfc5217SJeff Kirsher 1107adfc5217SJeff Kirsher /* MOVE: Add a rule that will add this MAC to the target Queue */ 1108adfc5217SJeff Kirsher if (cmd == BNX2X_VLAN_MAC_MOVE) { 1109adfc5217SJeff Kirsher rule_entry++; 1110adfc5217SJeff Kirsher rule_cnt++; 1111adfc5217SJeff Kirsher 1112adfc5217SJeff Kirsher /* Setup ramrod data */ 1113adfc5217SJeff Kirsher bnx2x_vlan_mac_set_cmd_hdr_e2(bp, 1114adfc5217SJeff Kirsher elem->cmd_data.vlan_mac.target_obj, 1115adfc5217SJeff Kirsher true, CLASSIFY_RULE_OPCODE_VLAN, 1116adfc5217SJeff Kirsher &rule_entry->vlan.header); 1117adfc5217SJeff Kirsher 1118adfc5217SJeff Kirsher /* Set a VLAN itself */ 1119adfc5217SJeff Kirsher rule_entry->vlan.vlan = cpu_to_le16(vlan); 1120adfc5217SJeff Kirsher } 1121adfc5217SJeff Kirsher 1122adfc5217SJeff Kirsher /* Set the ramrod data header */ 1123adfc5217SJeff Kirsher /* TODO: take this to the higher level in order to prevent multiple 1124adfc5217SJeff Kirsher writing */ 1125adfc5217SJeff Kirsher bnx2x_vlan_mac_set_rdata_hdr_e2(raw->cid, raw->state, &data->header, 1126adfc5217SJeff Kirsher rule_cnt); 1127adfc5217SJeff Kirsher } 1128adfc5217SJeff Kirsher 1129adfc5217SJeff Kirsher static void bnx2x_set_one_vlan_mac_e2(struct bnx2x *bp, 1130adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *o, 1131adfc5217SJeff Kirsher struct bnx2x_exeq_elem *elem, 1132adfc5217SJeff Kirsher int rule_idx, int cam_offset) 1133adfc5217SJeff Kirsher { 1134adfc5217SJeff Kirsher struct bnx2x_raw_obj *raw = &o->raw; 1135adfc5217SJeff Kirsher struct eth_classify_rules_ramrod_data *data = 1136adfc5217SJeff Kirsher (struct eth_classify_rules_ramrod_data *)(raw->rdata); 1137adfc5217SJeff Kirsher int rule_cnt = rule_idx + 1; 1138adfc5217SJeff Kirsher union eth_classify_rule_cmd *rule_entry = &data->rules[rule_idx]; 113986564c3fSYuval Mintz enum bnx2x_vlan_mac_cmd cmd = elem->cmd_data.vlan_mac.cmd; 1140adfc5217SJeff Kirsher bool add = (cmd == BNX2X_VLAN_MAC_ADD) ? true : false; 1141adfc5217SJeff Kirsher u16 vlan = elem->cmd_data.vlan_mac.u.vlan_mac.vlan; 1142adfc5217SJeff Kirsher u8 *mac = elem->cmd_data.vlan_mac.u.vlan_mac.mac; 1143adfc5217SJeff Kirsher 1144adfc5217SJeff Kirsher /* Reset the ramrod data buffer for the first rule */ 1145adfc5217SJeff Kirsher if (rule_idx == 0) 1146adfc5217SJeff Kirsher memset(data, 0, sizeof(*data)); 1147adfc5217SJeff Kirsher 1148adfc5217SJeff Kirsher /* Set a rule header */ 1149adfc5217SJeff Kirsher bnx2x_vlan_mac_set_cmd_hdr_e2(bp, o, add, CLASSIFY_RULE_OPCODE_PAIR, 1150adfc5217SJeff Kirsher &rule_entry->pair.header); 1151adfc5217SJeff Kirsher 115216a5fd92SYuval Mintz /* Set VLAN and MAC themselves */ 1153adfc5217SJeff Kirsher rule_entry->pair.vlan = cpu_to_le16(vlan); 1154adfc5217SJeff Kirsher bnx2x_set_fw_mac_addr(&rule_entry->pair.mac_msb, 1155adfc5217SJeff Kirsher &rule_entry->pair.mac_mid, 1156adfc5217SJeff Kirsher &rule_entry->pair.mac_lsb, mac); 115791226790SDmitry Kravkov rule_entry->pair.inner_mac = 115891226790SDmitry Kravkov cpu_to_le16(elem->cmd_data.vlan_mac.u.vlan_mac.is_inner_mac); 1159adfc5217SJeff Kirsher /* MOVE: Add a rule that will add this MAC to the target Queue */ 1160adfc5217SJeff Kirsher if (cmd == BNX2X_VLAN_MAC_MOVE) { 1161adfc5217SJeff Kirsher rule_entry++; 1162adfc5217SJeff Kirsher rule_cnt++; 1163adfc5217SJeff Kirsher 1164adfc5217SJeff Kirsher /* Setup ramrod data */ 1165adfc5217SJeff Kirsher bnx2x_vlan_mac_set_cmd_hdr_e2(bp, 1166adfc5217SJeff Kirsher elem->cmd_data.vlan_mac.target_obj, 1167adfc5217SJeff Kirsher true, CLASSIFY_RULE_OPCODE_PAIR, 1168adfc5217SJeff Kirsher &rule_entry->pair.header); 1169adfc5217SJeff Kirsher 1170adfc5217SJeff Kirsher /* Set a VLAN itself */ 1171adfc5217SJeff Kirsher rule_entry->pair.vlan = cpu_to_le16(vlan); 1172adfc5217SJeff Kirsher bnx2x_set_fw_mac_addr(&rule_entry->pair.mac_msb, 1173adfc5217SJeff Kirsher &rule_entry->pair.mac_mid, 1174adfc5217SJeff Kirsher &rule_entry->pair.mac_lsb, mac); 117591226790SDmitry Kravkov rule_entry->pair.inner_mac = 117691226790SDmitry Kravkov cpu_to_le16(elem->cmd_data.vlan_mac.u. 117791226790SDmitry Kravkov vlan_mac.is_inner_mac); 1178adfc5217SJeff Kirsher } 1179adfc5217SJeff Kirsher 1180adfc5217SJeff Kirsher /* Set the ramrod data header */ 1181adfc5217SJeff Kirsher /* TODO: take this to the higher level in order to prevent multiple 1182adfc5217SJeff Kirsher writing */ 1183adfc5217SJeff Kirsher bnx2x_vlan_mac_set_rdata_hdr_e2(raw->cid, raw->state, &data->header, 1184adfc5217SJeff Kirsher rule_cnt); 1185adfc5217SJeff Kirsher } 1186adfc5217SJeff Kirsher 1187adfc5217SJeff Kirsher /** 1188adfc5217SJeff Kirsher * bnx2x_set_one_vlan_mac_e1h - 1189adfc5217SJeff Kirsher * 1190adfc5217SJeff Kirsher * @bp: device handle 1191adfc5217SJeff Kirsher * @o: bnx2x_vlan_mac_obj 1192adfc5217SJeff Kirsher * @elem: bnx2x_exeq_elem 1193adfc5217SJeff Kirsher * @rule_idx: rule_idx 1194adfc5217SJeff Kirsher * @cam_offset: cam_offset 1195adfc5217SJeff Kirsher */ 1196adfc5217SJeff Kirsher static void bnx2x_set_one_vlan_mac_e1h(struct bnx2x *bp, 1197adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *o, 1198adfc5217SJeff Kirsher struct bnx2x_exeq_elem *elem, 1199adfc5217SJeff Kirsher int rule_idx, int cam_offset) 1200adfc5217SJeff Kirsher { 1201adfc5217SJeff Kirsher struct bnx2x_raw_obj *raw = &o->raw; 1202adfc5217SJeff Kirsher struct mac_configuration_cmd *config = 1203adfc5217SJeff Kirsher (struct mac_configuration_cmd *)(raw->rdata); 120416a5fd92SYuval Mintz /* 57710 and 57711 do not support MOVE command, 1205adfc5217SJeff Kirsher * so it's either ADD or DEL 1206adfc5217SJeff Kirsher */ 1207adfc5217SJeff Kirsher bool add = (elem->cmd_data.vlan_mac.cmd == BNX2X_VLAN_MAC_ADD) ? 1208adfc5217SJeff Kirsher true : false; 1209adfc5217SJeff Kirsher 1210adfc5217SJeff Kirsher /* Reset the ramrod data buffer */ 1211adfc5217SJeff Kirsher memset(config, 0, sizeof(*config)); 1212adfc5217SJeff Kirsher 1213adfc5217SJeff Kirsher bnx2x_vlan_mac_set_rdata_e1x(bp, o, BNX2X_FILTER_VLAN_MAC_PENDING, 1214adfc5217SJeff Kirsher cam_offset, add, 1215adfc5217SJeff Kirsher elem->cmd_data.vlan_mac.u.vlan_mac.mac, 1216adfc5217SJeff Kirsher elem->cmd_data.vlan_mac.u.vlan_mac.vlan, 1217adfc5217SJeff Kirsher ETH_VLAN_FILTER_CLASSIFY, config); 1218adfc5217SJeff Kirsher } 1219adfc5217SJeff Kirsher 1220adfc5217SJeff Kirsher /** 1221adfc5217SJeff Kirsher * bnx2x_vlan_mac_restore - reconfigure next MAC/VLAN/VLAN-MAC element 1222adfc5217SJeff Kirsher * 1223adfc5217SJeff Kirsher * @bp: device handle 1224adfc5217SJeff Kirsher * @p: command parameters 122516a5fd92SYuval Mintz * @ppos: pointer to the cookie 1226adfc5217SJeff Kirsher * 1227adfc5217SJeff Kirsher * reconfigure next MAC/VLAN/VLAN-MAC element from the 1228adfc5217SJeff Kirsher * previously configured elements list. 1229adfc5217SJeff Kirsher * 1230adfc5217SJeff Kirsher * from command parameters only RAMROD_COMP_WAIT bit in ramrod_flags is taken 1231adfc5217SJeff Kirsher * into an account 1232adfc5217SJeff Kirsher * 123316a5fd92SYuval Mintz * pointer to the cookie - that should be given back in the next call to make 1234adfc5217SJeff Kirsher * function handle the next element. If *ppos is set to NULL it will restart the 1235adfc5217SJeff Kirsher * iterator. If returned *ppos == NULL this means that the last element has been 1236adfc5217SJeff Kirsher * handled. 1237adfc5217SJeff Kirsher * 1238adfc5217SJeff Kirsher */ 1239adfc5217SJeff Kirsher static int bnx2x_vlan_mac_restore(struct bnx2x *bp, 1240adfc5217SJeff Kirsher struct bnx2x_vlan_mac_ramrod_params *p, 1241adfc5217SJeff Kirsher struct bnx2x_vlan_mac_registry_elem **ppos) 1242adfc5217SJeff Kirsher { 1243adfc5217SJeff Kirsher struct bnx2x_vlan_mac_registry_elem *pos; 1244adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *o = p->vlan_mac_obj; 1245adfc5217SJeff Kirsher 1246adfc5217SJeff Kirsher /* If list is empty - there is nothing to do here */ 1247adfc5217SJeff Kirsher if (list_empty(&o->head)) { 1248adfc5217SJeff Kirsher *ppos = NULL; 1249adfc5217SJeff Kirsher return 0; 1250adfc5217SJeff Kirsher } 1251adfc5217SJeff Kirsher 1252adfc5217SJeff Kirsher /* make a step... */ 1253adfc5217SJeff Kirsher if (*ppos == NULL) 1254adfc5217SJeff Kirsher *ppos = list_first_entry(&o->head, 1255adfc5217SJeff Kirsher struct bnx2x_vlan_mac_registry_elem, 1256adfc5217SJeff Kirsher link); 1257adfc5217SJeff Kirsher else 1258adfc5217SJeff Kirsher *ppos = list_next_entry(*ppos, link); 1259adfc5217SJeff Kirsher 1260adfc5217SJeff Kirsher pos = *ppos; 1261adfc5217SJeff Kirsher 1262adfc5217SJeff Kirsher /* If it's the last step - return NULL */ 1263adfc5217SJeff Kirsher if (list_is_last(&pos->link, &o->head)) 1264adfc5217SJeff Kirsher *ppos = NULL; 1265adfc5217SJeff Kirsher 1266adfc5217SJeff Kirsher /* Prepare a 'user_req' */ 1267adfc5217SJeff Kirsher memcpy(&p->user_req.u, &pos->u, sizeof(pos->u)); 1268adfc5217SJeff Kirsher 1269adfc5217SJeff Kirsher /* Set the command */ 1270adfc5217SJeff Kirsher p->user_req.cmd = BNX2X_VLAN_MAC_ADD; 1271adfc5217SJeff Kirsher 1272adfc5217SJeff Kirsher /* Set vlan_mac_flags */ 1273adfc5217SJeff Kirsher p->user_req.vlan_mac_flags = pos->vlan_mac_flags; 1274adfc5217SJeff Kirsher 1275adfc5217SJeff Kirsher /* Set a restore bit */ 1276adfc5217SJeff Kirsher __set_bit(RAMROD_RESTORE, &p->ramrod_flags); 1277adfc5217SJeff Kirsher 1278adfc5217SJeff Kirsher return bnx2x_config_vlan_mac(bp, p); 1279adfc5217SJeff Kirsher } 1280adfc5217SJeff Kirsher 128116a5fd92SYuval Mintz /* bnx2x_exeq_get_mac/bnx2x_exeq_get_vlan/bnx2x_exeq_get_vlan_mac return a 1282adfc5217SJeff Kirsher * pointer to an element with a specific criteria and NULL if such an element 1283adfc5217SJeff Kirsher * hasn't been found. 1284adfc5217SJeff Kirsher */ 1285adfc5217SJeff Kirsher static struct bnx2x_exeq_elem *bnx2x_exeq_get_mac( 1286adfc5217SJeff Kirsher struct bnx2x_exe_queue_obj *o, 1287adfc5217SJeff Kirsher struct bnx2x_exeq_elem *elem) 1288adfc5217SJeff Kirsher { 1289adfc5217SJeff Kirsher struct bnx2x_exeq_elem *pos; 1290adfc5217SJeff Kirsher struct bnx2x_mac_ramrod_data *data = &elem->cmd_data.vlan_mac.u.mac; 1291adfc5217SJeff Kirsher 1292adfc5217SJeff Kirsher /* Check pending for execution commands */ 1293adfc5217SJeff Kirsher list_for_each_entry(pos, &o->exe_queue, link) 1294adfc5217SJeff Kirsher if (!memcmp(&pos->cmd_data.vlan_mac.u.mac, data, 1295adfc5217SJeff Kirsher sizeof(*data)) && 1296adfc5217SJeff Kirsher (pos->cmd_data.vlan_mac.cmd == elem->cmd_data.vlan_mac.cmd)) 1297adfc5217SJeff Kirsher return pos; 1298adfc5217SJeff Kirsher 1299adfc5217SJeff Kirsher return NULL; 1300adfc5217SJeff Kirsher } 1301adfc5217SJeff Kirsher 1302adfc5217SJeff Kirsher static struct bnx2x_exeq_elem *bnx2x_exeq_get_vlan( 1303adfc5217SJeff Kirsher struct bnx2x_exe_queue_obj *o, 1304adfc5217SJeff Kirsher struct bnx2x_exeq_elem *elem) 1305adfc5217SJeff Kirsher { 1306adfc5217SJeff Kirsher struct bnx2x_exeq_elem *pos; 1307adfc5217SJeff Kirsher struct bnx2x_vlan_ramrod_data *data = &elem->cmd_data.vlan_mac.u.vlan; 1308adfc5217SJeff Kirsher 1309adfc5217SJeff Kirsher /* Check pending for execution commands */ 1310adfc5217SJeff Kirsher list_for_each_entry(pos, &o->exe_queue, link) 1311adfc5217SJeff Kirsher if (!memcmp(&pos->cmd_data.vlan_mac.u.vlan, data, 1312adfc5217SJeff Kirsher sizeof(*data)) && 1313adfc5217SJeff Kirsher (pos->cmd_data.vlan_mac.cmd == elem->cmd_data.vlan_mac.cmd)) 1314adfc5217SJeff Kirsher return pos; 1315adfc5217SJeff Kirsher 1316adfc5217SJeff Kirsher return NULL; 1317adfc5217SJeff Kirsher } 1318adfc5217SJeff Kirsher 1319adfc5217SJeff Kirsher static struct bnx2x_exeq_elem *bnx2x_exeq_get_vlan_mac( 1320adfc5217SJeff Kirsher struct bnx2x_exe_queue_obj *o, 1321adfc5217SJeff Kirsher struct bnx2x_exeq_elem *elem) 1322adfc5217SJeff Kirsher { 1323adfc5217SJeff Kirsher struct bnx2x_exeq_elem *pos; 1324adfc5217SJeff Kirsher struct bnx2x_vlan_mac_ramrod_data *data = 1325adfc5217SJeff Kirsher &elem->cmd_data.vlan_mac.u.vlan_mac; 1326adfc5217SJeff Kirsher 1327adfc5217SJeff Kirsher /* Check pending for execution commands */ 1328adfc5217SJeff Kirsher list_for_each_entry(pos, &o->exe_queue, link) 1329adfc5217SJeff Kirsher if (!memcmp(&pos->cmd_data.vlan_mac.u.vlan_mac, data, 1330adfc5217SJeff Kirsher sizeof(*data)) && 1331adfc5217SJeff Kirsher (pos->cmd_data.vlan_mac.cmd == elem->cmd_data.vlan_mac.cmd)) 1332adfc5217SJeff Kirsher return pos; 1333adfc5217SJeff Kirsher 1334adfc5217SJeff Kirsher return NULL; 1335adfc5217SJeff Kirsher } 1336adfc5217SJeff Kirsher 1337adfc5217SJeff Kirsher /** 1338adfc5217SJeff Kirsher * bnx2x_validate_vlan_mac_add - check if an ADD command can be executed 1339adfc5217SJeff Kirsher * 1340adfc5217SJeff Kirsher * @bp: device handle 1341adfc5217SJeff Kirsher * @qo: bnx2x_qable_obj 1342adfc5217SJeff Kirsher * @elem: bnx2x_exeq_elem 1343adfc5217SJeff Kirsher * 1344adfc5217SJeff Kirsher * Checks that the requested configuration can be added. If yes and if 1345adfc5217SJeff Kirsher * requested, consume CAM credit. 1346adfc5217SJeff Kirsher * 1347adfc5217SJeff Kirsher * The 'validate' is run after the 'optimize'. 1348adfc5217SJeff Kirsher * 1349adfc5217SJeff Kirsher */ 1350adfc5217SJeff Kirsher static inline int bnx2x_validate_vlan_mac_add(struct bnx2x *bp, 1351adfc5217SJeff Kirsher union bnx2x_qable_obj *qo, 1352adfc5217SJeff Kirsher struct bnx2x_exeq_elem *elem) 1353adfc5217SJeff Kirsher { 1354adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *o = &qo->vlan_mac; 1355adfc5217SJeff Kirsher struct bnx2x_exe_queue_obj *exeq = &o->exe_queue; 1356adfc5217SJeff Kirsher int rc; 1357adfc5217SJeff Kirsher 1358adfc5217SJeff Kirsher /* Check the registry */ 135951c1a580SMerav Sicron rc = o->check_add(bp, o, &elem->cmd_data.vlan_mac.u); 1360adfc5217SJeff Kirsher if (rc) { 136151c1a580SMerav Sicron DP(BNX2X_MSG_SP, "ADD command is not allowed considering current registry state.\n"); 1362adfc5217SJeff Kirsher return rc; 1363adfc5217SJeff Kirsher } 1364adfc5217SJeff Kirsher 136516a5fd92SYuval Mintz /* Check if there is a pending ADD command for this 1366adfc5217SJeff Kirsher * MAC/VLAN/VLAN-MAC. Return an error if there is. 1367adfc5217SJeff Kirsher */ 1368adfc5217SJeff Kirsher if (exeq->get(exeq, elem)) { 1369adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "There is a pending ADD command already\n"); 1370adfc5217SJeff Kirsher return -EEXIST; 1371adfc5217SJeff Kirsher } 1372adfc5217SJeff Kirsher 137316a5fd92SYuval Mintz /* TODO: Check the pending MOVE from other objects where this 1374adfc5217SJeff Kirsher * object is a destination object. 1375adfc5217SJeff Kirsher */ 1376adfc5217SJeff Kirsher 1377adfc5217SJeff Kirsher /* Consume the credit if not requested not to */ 1378adfc5217SJeff Kirsher if (!(test_bit(BNX2X_DONT_CONSUME_CAM_CREDIT, 1379adfc5217SJeff Kirsher &elem->cmd_data.vlan_mac.vlan_mac_flags) || 1380adfc5217SJeff Kirsher o->get_credit(o))) 1381adfc5217SJeff Kirsher return -EINVAL; 1382adfc5217SJeff Kirsher 1383adfc5217SJeff Kirsher return 0; 1384adfc5217SJeff Kirsher } 1385adfc5217SJeff Kirsher 1386adfc5217SJeff Kirsher /** 1387adfc5217SJeff Kirsher * bnx2x_validate_vlan_mac_del - check if the DEL command can be executed 1388adfc5217SJeff Kirsher * 1389adfc5217SJeff Kirsher * @bp: device handle 1390adfc5217SJeff Kirsher * @qo: quable object to check 1391adfc5217SJeff Kirsher * @elem: element that needs to be deleted 1392adfc5217SJeff Kirsher * 1393adfc5217SJeff Kirsher * Checks that the requested configuration can be deleted. If yes and if 1394adfc5217SJeff Kirsher * requested, returns a CAM credit. 1395adfc5217SJeff Kirsher * 1396adfc5217SJeff Kirsher * The 'validate' is run after the 'optimize'. 1397adfc5217SJeff Kirsher */ 1398adfc5217SJeff Kirsher static inline int bnx2x_validate_vlan_mac_del(struct bnx2x *bp, 1399adfc5217SJeff Kirsher union bnx2x_qable_obj *qo, 1400adfc5217SJeff Kirsher struct bnx2x_exeq_elem *elem) 1401adfc5217SJeff Kirsher { 1402adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *o = &qo->vlan_mac; 1403adfc5217SJeff Kirsher struct bnx2x_vlan_mac_registry_elem *pos; 1404adfc5217SJeff Kirsher struct bnx2x_exe_queue_obj *exeq = &o->exe_queue; 1405adfc5217SJeff Kirsher struct bnx2x_exeq_elem query_elem; 1406adfc5217SJeff Kirsher 1407adfc5217SJeff Kirsher /* If this classification can not be deleted (doesn't exist) 1408adfc5217SJeff Kirsher * - return a BNX2X_EXIST. 1409adfc5217SJeff Kirsher */ 141051c1a580SMerav Sicron pos = o->check_del(bp, o, &elem->cmd_data.vlan_mac.u); 1411adfc5217SJeff Kirsher if (!pos) { 141251c1a580SMerav Sicron DP(BNX2X_MSG_SP, "DEL command is not allowed considering current registry state\n"); 1413adfc5217SJeff Kirsher return -EEXIST; 1414adfc5217SJeff Kirsher } 1415adfc5217SJeff Kirsher 141616a5fd92SYuval Mintz /* Check if there are pending DEL or MOVE commands for this 1417adfc5217SJeff Kirsher * MAC/VLAN/VLAN-MAC. Return an error if so. 1418adfc5217SJeff Kirsher */ 1419adfc5217SJeff Kirsher memcpy(&query_elem, elem, sizeof(query_elem)); 1420adfc5217SJeff Kirsher 1421adfc5217SJeff Kirsher /* Check for MOVE commands */ 1422adfc5217SJeff Kirsher query_elem.cmd_data.vlan_mac.cmd = BNX2X_VLAN_MAC_MOVE; 1423adfc5217SJeff Kirsher if (exeq->get(exeq, &query_elem)) { 1424adfc5217SJeff Kirsher BNX2X_ERR("There is a pending MOVE command already\n"); 1425adfc5217SJeff Kirsher return -EINVAL; 1426adfc5217SJeff Kirsher } 1427adfc5217SJeff Kirsher 1428adfc5217SJeff Kirsher /* Check for DEL commands */ 1429adfc5217SJeff Kirsher if (exeq->get(exeq, elem)) { 1430adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "There is a pending DEL command already\n"); 1431adfc5217SJeff Kirsher return -EEXIST; 1432adfc5217SJeff Kirsher } 1433adfc5217SJeff Kirsher 1434adfc5217SJeff Kirsher /* Return the credit to the credit pool if not requested not to */ 1435adfc5217SJeff Kirsher if (!(test_bit(BNX2X_DONT_CONSUME_CAM_CREDIT, 1436adfc5217SJeff Kirsher &elem->cmd_data.vlan_mac.vlan_mac_flags) || 1437adfc5217SJeff Kirsher o->put_credit(o))) { 1438adfc5217SJeff Kirsher BNX2X_ERR("Failed to return a credit\n"); 1439adfc5217SJeff Kirsher return -EINVAL; 1440adfc5217SJeff Kirsher } 1441adfc5217SJeff Kirsher 1442adfc5217SJeff Kirsher return 0; 1443adfc5217SJeff Kirsher } 1444adfc5217SJeff Kirsher 1445adfc5217SJeff Kirsher /** 1446adfc5217SJeff Kirsher * bnx2x_validate_vlan_mac_move - check if the MOVE command can be executed 1447adfc5217SJeff Kirsher * 1448adfc5217SJeff Kirsher * @bp: device handle 1449adfc5217SJeff Kirsher * @qo: quable object to check (source) 1450adfc5217SJeff Kirsher * @elem: element that needs to be moved 1451adfc5217SJeff Kirsher * 1452adfc5217SJeff Kirsher * Checks that the requested configuration can be moved. If yes and if 1453adfc5217SJeff Kirsher * requested, returns a CAM credit. 1454adfc5217SJeff Kirsher * 1455adfc5217SJeff Kirsher * The 'validate' is run after the 'optimize'. 1456adfc5217SJeff Kirsher */ 1457adfc5217SJeff Kirsher static inline int bnx2x_validate_vlan_mac_move(struct bnx2x *bp, 1458adfc5217SJeff Kirsher union bnx2x_qable_obj *qo, 1459adfc5217SJeff Kirsher struct bnx2x_exeq_elem *elem) 1460adfc5217SJeff Kirsher { 1461adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *src_o = &qo->vlan_mac; 1462adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *dest_o = elem->cmd_data.vlan_mac.target_obj; 1463adfc5217SJeff Kirsher struct bnx2x_exeq_elem query_elem; 1464adfc5217SJeff Kirsher struct bnx2x_exe_queue_obj *src_exeq = &src_o->exe_queue; 1465adfc5217SJeff Kirsher struct bnx2x_exe_queue_obj *dest_exeq = &dest_o->exe_queue; 1466adfc5217SJeff Kirsher 146716a5fd92SYuval Mintz /* Check if we can perform this operation based on the current registry 1468adfc5217SJeff Kirsher * state. 1469adfc5217SJeff Kirsher */ 147051c1a580SMerav Sicron if (!src_o->check_move(bp, src_o, dest_o, 147151c1a580SMerav Sicron &elem->cmd_data.vlan_mac.u)) { 147251c1a580SMerav Sicron DP(BNX2X_MSG_SP, "MOVE command is not allowed considering current registry state\n"); 1473adfc5217SJeff Kirsher return -EINVAL; 1474adfc5217SJeff Kirsher } 1475adfc5217SJeff Kirsher 147616a5fd92SYuval Mintz /* Check if there is an already pending DEL or MOVE command for the 1477adfc5217SJeff Kirsher * source object or ADD command for a destination object. Return an 1478adfc5217SJeff Kirsher * error if so. 1479adfc5217SJeff Kirsher */ 1480adfc5217SJeff Kirsher memcpy(&query_elem, elem, sizeof(query_elem)); 1481adfc5217SJeff Kirsher 1482adfc5217SJeff Kirsher /* Check DEL on source */ 1483adfc5217SJeff Kirsher query_elem.cmd_data.vlan_mac.cmd = BNX2X_VLAN_MAC_DEL; 1484adfc5217SJeff Kirsher if (src_exeq->get(src_exeq, &query_elem)) { 148551c1a580SMerav Sicron BNX2X_ERR("There is a pending DEL command on the source queue already\n"); 1486adfc5217SJeff Kirsher return -EINVAL; 1487adfc5217SJeff Kirsher } 1488adfc5217SJeff Kirsher 1489adfc5217SJeff Kirsher /* Check MOVE on source */ 1490adfc5217SJeff Kirsher if (src_exeq->get(src_exeq, elem)) { 1491adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "There is a pending MOVE command already\n"); 1492adfc5217SJeff Kirsher return -EEXIST; 1493adfc5217SJeff Kirsher } 1494adfc5217SJeff Kirsher 1495adfc5217SJeff Kirsher /* Check ADD on destination */ 1496adfc5217SJeff Kirsher query_elem.cmd_data.vlan_mac.cmd = BNX2X_VLAN_MAC_ADD; 1497adfc5217SJeff Kirsher if (dest_exeq->get(dest_exeq, &query_elem)) { 149851c1a580SMerav Sicron BNX2X_ERR("There is a pending ADD command on the destination queue already\n"); 1499adfc5217SJeff Kirsher return -EINVAL; 1500adfc5217SJeff Kirsher } 1501adfc5217SJeff Kirsher 1502adfc5217SJeff Kirsher /* Consume the credit if not requested not to */ 1503adfc5217SJeff Kirsher if (!(test_bit(BNX2X_DONT_CONSUME_CAM_CREDIT_DEST, 1504adfc5217SJeff Kirsher &elem->cmd_data.vlan_mac.vlan_mac_flags) || 1505adfc5217SJeff Kirsher dest_o->get_credit(dest_o))) 1506adfc5217SJeff Kirsher return -EINVAL; 1507adfc5217SJeff Kirsher 1508adfc5217SJeff Kirsher if (!(test_bit(BNX2X_DONT_CONSUME_CAM_CREDIT, 1509adfc5217SJeff Kirsher &elem->cmd_data.vlan_mac.vlan_mac_flags) || 1510adfc5217SJeff Kirsher src_o->put_credit(src_o))) { 1511adfc5217SJeff Kirsher /* return the credit taken from dest... */ 1512adfc5217SJeff Kirsher dest_o->put_credit(dest_o); 1513adfc5217SJeff Kirsher return -EINVAL; 1514adfc5217SJeff Kirsher } 1515adfc5217SJeff Kirsher 1516adfc5217SJeff Kirsher return 0; 1517adfc5217SJeff Kirsher } 1518adfc5217SJeff Kirsher 1519adfc5217SJeff Kirsher static int bnx2x_validate_vlan_mac(struct bnx2x *bp, 1520adfc5217SJeff Kirsher union bnx2x_qable_obj *qo, 1521adfc5217SJeff Kirsher struct bnx2x_exeq_elem *elem) 1522adfc5217SJeff Kirsher { 1523adfc5217SJeff Kirsher switch (elem->cmd_data.vlan_mac.cmd) { 1524adfc5217SJeff Kirsher case BNX2X_VLAN_MAC_ADD: 1525adfc5217SJeff Kirsher return bnx2x_validate_vlan_mac_add(bp, qo, elem); 1526adfc5217SJeff Kirsher case BNX2X_VLAN_MAC_DEL: 1527adfc5217SJeff Kirsher return bnx2x_validate_vlan_mac_del(bp, qo, elem); 1528adfc5217SJeff Kirsher case BNX2X_VLAN_MAC_MOVE: 1529adfc5217SJeff Kirsher return bnx2x_validate_vlan_mac_move(bp, qo, elem); 1530adfc5217SJeff Kirsher default: 1531adfc5217SJeff Kirsher return -EINVAL; 1532adfc5217SJeff Kirsher } 1533adfc5217SJeff Kirsher } 1534adfc5217SJeff Kirsher 1535460a25cdSYuval Mintz static int bnx2x_remove_vlan_mac(struct bnx2x *bp, 1536460a25cdSYuval Mintz union bnx2x_qable_obj *qo, 1537460a25cdSYuval Mintz struct bnx2x_exeq_elem *elem) 1538460a25cdSYuval Mintz { 1539460a25cdSYuval Mintz int rc = 0; 1540460a25cdSYuval Mintz 1541460a25cdSYuval Mintz /* If consumption wasn't required, nothing to do */ 1542460a25cdSYuval Mintz if (test_bit(BNX2X_DONT_CONSUME_CAM_CREDIT, 1543460a25cdSYuval Mintz &elem->cmd_data.vlan_mac.vlan_mac_flags)) 1544460a25cdSYuval Mintz return 0; 1545460a25cdSYuval Mintz 1546460a25cdSYuval Mintz switch (elem->cmd_data.vlan_mac.cmd) { 1547460a25cdSYuval Mintz case BNX2X_VLAN_MAC_ADD: 1548460a25cdSYuval Mintz case BNX2X_VLAN_MAC_MOVE: 1549460a25cdSYuval Mintz rc = qo->vlan_mac.put_credit(&qo->vlan_mac); 1550460a25cdSYuval Mintz break; 1551460a25cdSYuval Mintz case BNX2X_VLAN_MAC_DEL: 1552460a25cdSYuval Mintz rc = qo->vlan_mac.get_credit(&qo->vlan_mac); 1553460a25cdSYuval Mintz break; 1554460a25cdSYuval Mintz default: 1555460a25cdSYuval Mintz return -EINVAL; 1556460a25cdSYuval Mintz } 1557460a25cdSYuval Mintz 1558460a25cdSYuval Mintz if (rc != true) 1559460a25cdSYuval Mintz return -EINVAL; 1560460a25cdSYuval Mintz 1561460a25cdSYuval Mintz return 0; 1562460a25cdSYuval Mintz } 1563460a25cdSYuval Mintz 1564adfc5217SJeff Kirsher /** 156516a5fd92SYuval Mintz * bnx2x_wait_vlan_mac - passively wait for 5 seconds until all work completes. 1566adfc5217SJeff Kirsher * 1567adfc5217SJeff Kirsher * @bp: device handle 1568adfc5217SJeff Kirsher * @o: bnx2x_vlan_mac_obj 1569adfc5217SJeff Kirsher * 1570adfc5217SJeff Kirsher */ 1571adfc5217SJeff Kirsher static int bnx2x_wait_vlan_mac(struct bnx2x *bp, 1572adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *o) 1573adfc5217SJeff Kirsher { 1574adfc5217SJeff Kirsher int cnt = 5000, rc; 1575adfc5217SJeff Kirsher struct bnx2x_exe_queue_obj *exeq = &o->exe_queue; 1576adfc5217SJeff Kirsher struct bnx2x_raw_obj *raw = &o->raw; 1577adfc5217SJeff Kirsher 1578adfc5217SJeff Kirsher while (cnt--) { 1579adfc5217SJeff Kirsher /* Wait for the current command to complete */ 1580adfc5217SJeff Kirsher rc = raw->wait_comp(bp, raw); 1581adfc5217SJeff Kirsher if (rc) 1582adfc5217SJeff Kirsher return rc; 1583adfc5217SJeff Kirsher 1584adfc5217SJeff Kirsher /* Wait until there are no pending commands */ 1585adfc5217SJeff Kirsher if (!bnx2x_exe_queue_empty(exeq)) 15860926d499SYuval Mintz usleep_range(1000, 2000); 1587adfc5217SJeff Kirsher else 1588adfc5217SJeff Kirsher return 0; 1589adfc5217SJeff Kirsher } 1590adfc5217SJeff Kirsher 1591adfc5217SJeff Kirsher return -EBUSY; 1592adfc5217SJeff Kirsher } 1593adfc5217SJeff Kirsher 15948b09be5fSYuval Mintz static int __bnx2x_vlan_mac_execute_step(struct bnx2x *bp, 15958b09be5fSYuval Mintz struct bnx2x_vlan_mac_obj *o, 15968b09be5fSYuval Mintz unsigned long *ramrod_flags) 15978b09be5fSYuval Mintz { 15988b09be5fSYuval Mintz int rc = 0; 15998b09be5fSYuval Mintz 16008b09be5fSYuval Mintz spin_lock_bh(&o->exe_queue.lock); 16018b09be5fSYuval Mintz 16028b09be5fSYuval Mintz DP(BNX2X_MSG_SP, "vlan_mac_execute_step - trying to take writer lock\n"); 16038b09be5fSYuval Mintz rc = __bnx2x_vlan_mac_h_write_trylock(bp, o); 16048b09be5fSYuval Mintz 16058b09be5fSYuval Mintz if (rc != 0) { 16068b09be5fSYuval Mintz __bnx2x_vlan_mac_h_pend(bp, o, *ramrod_flags); 16078b09be5fSYuval Mintz 16088b09be5fSYuval Mintz /* Calling function should not diffrentiate between this case 16098b09be5fSYuval Mintz * and the case in which there is already a pending ramrod 16108b09be5fSYuval Mintz */ 16118b09be5fSYuval Mintz rc = 1; 16128b09be5fSYuval Mintz } else { 16138b09be5fSYuval Mintz rc = bnx2x_exe_queue_step(bp, &o->exe_queue, ramrod_flags); 16148b09be5fSYuval Mintz } 16158b09be5fSYuval Mintz spin_unlock_bh(&o->exe_queue.lock); 16168b09be5fSYuval Mintz 16178b09be5fSYuval Mintz return rc; 16188b09be5fSYuval Mintz } 16198b09be5fSYuval Mintz 1620adfc5217SJeff Kirsher /** 1621adfc5217SJeff Kirsher * bnx2x_complete_vlan_mac - complete one VLAN-MAC ramrod 1622adfc5217SJeff Kirsher * 1623adfc5217SJeff Kirsher * @bp: device handle 1624adfc5217SJeff Kirsher * @o: bnx2x_vlan_mac_obj 1625adfc5217SJeff Kirsher * @cqe: 1626adfc5217SJeff Kirsher * @cont: if true schedule next execution chunk 1627adfc5217SJeff Kirsher * 1628adfc5217SJeff Kirsher */ 1629adfc5217SJeff Kirsher static int bnx2x_complete_vlan_mac(struct bnx2x *bp, 1630adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *o, 1631adfc5217SJeff Kirsher union event_ring_elem *cqe, 1632adfc5217SJeff Kirsher unsigned long *ramrod_flags) 1633adfc5217SJeff Kirsher { 1634adfc5217SJeff Kirsher struct bnx2x_raw_obj *r = &o->raw; 1635adfc5217SJeff Kirsher int rc; 1636adfc5217SJeff Kirsher 16378b09be5fSYuval Mintz /* Clearing the pending list & raw state should be made 16388b09be5fSYuval Mintz * atomically (as execution flow assumes they represent the same). 16398b09be5fSYuval Mintz */ 16408b09be5fSYuval Mintz spin_lock_bh(&o->exe_queue.lock); 16418b09be5fSYuval Mintz 1642adfc5217SJeff Kirsher /* Reset pending list */ 16438b09be5fSYuval Mintz __bnx2x_exe_queue_reset_pending(bp, &o->exe_queue); 1644adfc5217SJeff Kirsher 1645adfc5217SJeff Kirsher /* Clear pending */ 1646adfc5217SJeff Kirsher r->clear_pending(r); 1647adfc5217SJeff Kirsher 16488b09be5fSYuval Mintz spin_unlock_bh(&o->exe_queue.lock); 16498b09be5fSYuval Mintz 1650adfc5217SJeff Kirsher /* If ramrod failed this is most likely a SW bug */ 1651adfc5217SJeff Kirsher if (cqe->message.error) 1652adfc5217SJeff Kirsher return -EINVAL; 1653adfc5217SJeff Kirsher 16542de67439SYuval Mintz /* Run the next bulk of pending commands if requested */ 1655adfc5217SJeff Kirsher if (test_bit(RAMROD_CONT, ramrod_flags)) { 16568b09be5fSYuval Mintz rc = __bnx2x_vlan_mac_execute_step(bp, o, ramrod_flags); 16578b09be5fSYuval Mintz 1658adfc5217SJeff Kirsher if (rc < 0) 1659adfc5217SJeff Kirsher return rc; 1660adfc5217SJeff Kirsher } 1661adfc5217SJeff Kirsher 1662adfc5217SJeff Kirsher /* If there is more work to do return PENDING */ 1663adfc5217SJeff Kirsher if (!bnx2x_exe_queue_empty(&o->exe_queue)) 1664adfc5217SJeff Kirsher return 1; 1665adfc5217SJeff Kirsher 1666adfc5217SJeff Kirsher return 0; 1667adfc5217SJeff Kirsher } 1668adfc5217SJeff Kirsher 1669adfc5217SJeff Kirsher /** 1670adfc5217SJeff Kirsher * bnx2x_optimize_vlan_mac - optimize ADD and DEL commands. 1671adfc5217SJeff Kirsher * 1672adfc5217SJeff Kirsher * @bp: device handle 1673adfc5217SJeff Kirsher * @o: bnx2x_qable_obj 1674adfc5217SJeff Kirsher * @elem: bnx2x_exeq_elem 1675adfc5217SJeff Kirsher */ 1676adfc5217SJeff Kirsher static int bnx2x_optimize_vlan_mac(struct bnx2x *bp, 1677adfc5217SJeff Kirsher union bnx2x_qable_obj *qo, 1678adfc5217SJeff Kirsher struct bnx2x_exeq_elem *elem) 1679adfc5217SJeff Kirsher { 1680adfc5217SJeff Kirsher struct bnx2x_exeq_elem query, *pos; 1681adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *o = &qo->vlan_mac; 1682adfc5217SJeff Kirsher struct bnx2x_exe_queue_obj *exeq = &o->exe_queue; 1683adfc5217SJeff Kirsher 1684adfc5217SJeff Kirsher memcpy(&query, elem, sizeof(query)); 1685adfc5217SJeff Kirsher 1686adfc5217SJeff Kirsher switch (elem->cmd_data.vlan_mac.cmd) { 1687adfc5217SJeff Kirsher case BNX2X_VLAN_MAC_ADD: 1688adfc5217SJeff Kirsher query.cmd_data.vlan_mac.cmd = BNX2X_VLAN_MAC_DEL; 1689adfc5217SJeff Kirsher break; 1690adfc5217SJeff Kirsher case BNX2X_VLAN_MAC_DEL: 1691adfc5217SJeff Kirsher query.cmd_data.vlan_mac.cmd = BNX2X_VLAN_MAC_ADD; 1692adfc5217SJeff Kirsher break; 1693adfc5217SJeff Kirsher default: 1694adfc5217SJeff Kirsher /* Don't handle anything other than ADD or DEL */ 1695adfc5217SJeff Kirsher return 0; 1696adfc5217SJeff Kirsher } 1697adfc5217SJeff Kirsher 1698adfc5217SJeff Kirsher /* If we found the appropriate element - delete it */ 1699adfc5217SJeff Kirsher pos = exeq->get(exeq, &query); 1700adfc5217SJeff Kirsher if (pos) { 1701adfc5217SJeff Kirsher 1702adfc5217SJeff Kirsher /* Return the credit of the optimized command */ 1703adfc5217SJeff Kirsher if (!test_bit(BNX2X_DONT_CONSUME_CAM_CREDIT, 1704adfc5217SJeff Kirsher &pos->cmd_data.vlan_mac.vlan_mac_flags)) { 1705adfc5217SJeff Kirsher if ((query.cmd_data.vlan_mac.cmd == 1706adfc5217SJeff Kirsher BNX2X_VLAN_MAC_ADD) && !o->put_credit(o)) { 170751c1a580SMerav Sicron BNX2X_ERR("Failed to return the credit for the optimized ADD command\n"); 1708adfc5217SJeff Kirsher return -EINVAL; 1709adfc5217SJeff Kirsher } else if (!o->get_credit(o)) { /* VLAN_MAC_DEL */ 171051c1a580SMerav Sicron BNX2X_ERR("Failed to recover the credit from the optimized DEL command\n"); 1711adfc5217SJeff Kirsher return -EINVAL; 1712adfc5217SJeff Kirsher } 1713adfc5217SJeff Kirsher } 1714adfc5217SJeff Kirsher 1715adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "Optimizing %s command\n", 1716adfc5217SJeff Kirsher (elem->cmd_data.vlan_mac.cmd == BNX2X_VLAN_MAC_ADD) ? 1717adfc5217SJeff Kirsher "ADD" : "DEL"); 1718adfc5217SJeff Kirsher 1719adfc5217SJeff Kirsher list_del(&pos->link); 1720adfc5217SJeff Kirsher bnx2x_exe_queue_free_elem(bp, pos); 1721adfc5217SJeff Kirsher return 1; 1722adfc5217SJeff Kirsher } 1723adfc5217SJeff Kirsher 1724adfc5217SJeff Kirsher return 0; 1725adfc5217SJeff Kirsher } 1726adfc5217SJeff Kirsher 1727adfc5217SJeff Kirsher /** 1728adfc5217SJeff Kirsher * bnx2x_vlan_mac_get_registry_elem - prepare a registry element 1729adfc5217SJeff Kirsher * 1730adfc5217SJeff Kirsher * @bp: device handle 1731adfc5217SJeff Kirsher * @o: 1732adfc5217SJeff Kirsher * @elem: 1733adfc5217SJeff Kirsher * @restore: 1734adfc5217SJeff Kirsher * @re: 1735adfc5217SJeff Kirsher * 1736adfc5217SJeff Kirsher * prepare a registry element according to the current command request. 1737adfc5217SJeff Kirsher */ 1738adfc5217SJeff Kirsher static inline int bnx2x_vlan_mac_get_registry_elem( 1739adfc5217SJeff Kirsher struct bnx2x *bp, 1740adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *o, 1741adfc5217SJeff Kirsher struct bnx2x_exeq_elem *elem, 1742adfc5217SJeff Kirsher bool restore, 1743adfc5217SJeff Kirsher struct bnx2x_vlan_mac_registry_elem **re) 1744adfc5217SJeff Kirsher { 174586564c3fSYuval Mintz enum bnx2x_vlan_mac_cmd cmd = elem->cmd_data.vlan_mac.cmd; 1746adfc5217SJeff Kirsher struct bnx2x_vlan_mac_registry_elem *reg_elem; 1747adfc5217SJeff Kirsher 1748adfc5217SJeff Kirsher /* Allocate a new registry element if needed. */ 1749adfc5217SJeff Kirsher if (!restore && 1750adfc5217SJeff Kirsher ((cmd == BNX2X_VLAN_MAC_ADD) || (cmd == BNX2X_VLAN_MAC_MOVE))) { 1751adfc5217SJeff Kirsher reg_elem = kzalloc(sizeof(*reg_elem), GFP_ATOMIC); 1752adfc5217SJeff Kirsher if (!reg_elem) 1753adfc5217SJeff Kirsher return -ENOMEM; 1754adfc5217SJeff Kirsher 1755adfc5217SJeff Kirsher /* Get a new CAM offset */ 1756adfc5217SJeff Kirsher if (!o->get_cam_offset(o, ®_elem->cam_offset)) { 175716a5fd92SYuval Mintz /* This shall never happen, because we have checked the 175816a5fd92SYuval Mintz * CAM availability in the 'validate'. 1759adfc5217SJeff Kirsher */ 1760adfc5217SJeff Kirsher WARN_ON(1); 1761adfc5217SJeff Kirsher kfree(reg_elem); 1762adfc5217SJeff Kirsher return -EINVAL; 1763adfc5217SJeff Kirsher } 1764adfc5217SJeff Kirsher 1765adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "Got cam offset %d\n", reg_elem->cam_offset); 1766adfc5217SJeff Kirsher 1767adfc5217SJeff Kirsher /* Set a VLAN-MAC data */ 1768adfc5217SJeff Kirsher memcpy(®_elem->u, &elem->cmd_data.vlan_mac.u, 1769adfc5217SJeff Kirsher sizeof(reg_elem->u)); 1770adfc5217SJeff Kirsher 1771adfc5217SJeff Kirsher /* Copy the flags (needed for DEL and RESTORE flows) */ 1772adfc5217SJeff Kirsher reg_elem->vlan_mac_flags = 1773adfc5217SJeff Kirsher elem->cmd_data.vlan_mac.vlan_mac_flags; 1774adfc5217SJeff Kirsher } else /* DEL, RESTORE */ 177551c1a580SMerav Sicron reg_elem = o->check_del(bp, o, &elem->cmd_data.vlan_mac.u); 1776adfc5217SJeff Kirsher 1777adfc5217SJeff Kirsher *re = reg_elem; 1778adfc5217SJeff Kirsher return 0; 1779adfc5217SJeff Kirsher } 1780adfc5217SJeff Kirsher 1781adfc5217SJeff Kirsher /** 1782adfc5217SJeff Kirsher * bnx2x_execute_vlan_mac - execute vlan mac command 1783adfc5217SJeff Kirsher * 1784adfc5217SJeff Kirsher * @bp: device handle 1785adfc5217SJeff Kirsher * @qo: 1786adfc5217SJeff Kirsher * @exe_chunk: 1787adfc5217SJeff Kirsher * @ramrod_flags: 1788adfc5217SJeff Kirsher * 1789adfc5217SJeff Kirsher * go and send a ramrod! 1790adfc5217SJeff Kirsher */ 1791adfc5217SJeff Kirsher static int bnx2x_execute_vlan_mac(struct bnx2x *bp, 1792adfc5217SJeff Kirsher union bnx2x_qable_obj *qo, 1793adfc5217SJeff Kirsher struct list_head *exe_chunk, 1794adfc5217SJeff Kirsher unsigned long *ramrod_flags) 1795adfc5217SJeff Kirsher { 1796adfc5217SJeff Kirsher struct bnx2x_exeq_elem *elem; 1797adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *o = &qo->vlan_mac, *cam_obj; 1798adfc5217SJeff Kirsher struct bnx2x_raw_obj *r = &o->raw; 1799adfc5217SJeff Kirsher int rc, idx = 0; 1800adfc5217SJeff Kirsher bool restore = test_bit(RAMROD_RESTORE, ramrod_flags); 1801adfc5217SJeff Kirsher bool drv_only = test_bit(RAMROD_DRV_CLR_ONLY, ramrod_flags); 1802adfc5217SJeff Kirsher struct bnx2x_vlan_mac_registry_elem *reg_elem; 180386564c3fSYuval Mintz enum bnx2x_vlan_mac_cmd cmd; 1804adfc5217SJeff Kirsher 180516a5fd92SYuval Mintz /* If DRIVER_ONLY execution is requested, cleanup a registry 1806adfc5217SJeff Kirsher * and exit. Otherwise send a ramrod to FW. 1807adfc5217SJeff Kirsher */ 1808adfc5217SJeff Kirsher if (!drv_only) { 1809adfc5217SJeff Kirsher WARN_ON(r->check_pending(r)); 1810adfc5217SJeff Kirsher 1811adfc5217SJeff Kirsher /* Set pending */ 1812adfc5217SJeff Kirsher r->set_pending(r); 1813adfc5217SJeff Kirsher 181416a5fd92SYuval Mintz /* Fill the ramrod data */ 1815adfc5217SJeff Kirsher list_for_each_entry(elem, exe_chunk, link) { 1816adfc5217SJeff Kirsher cmd = elem->cmd_data.vlan_mac.cmd; 181716a5fd92SYuval Mintz /* We will add to the target object in MOVE command, so 1818adfc5217SJeff Kirsher * change the object for a CAM search. 1819adfc5217SJeff Kirsher */ 1820adfc5217SJeff Kirsher if (cmd == BNX2X_VLAN_MAC_MOVE) 1821adfc5217SJeff Kirsher cam_obj = elem->cmd_data.vlan_mac.target_obj; 1822adfc5217SJeff Kirsher else 1823adfc5217SJeff Kirsher cam_obj = o; 1824adfc5217SJeff Kirsher 1825adfc5217SJeff Kirsher rc = bnx2x_vlan_mac_get_registry_elem(bp, cam_obj, 1826adfc5217SJeff Kirsher elem, restore, 1827adfc5217SJeff Kirsher ®_elem); 1828adfc5217SJeff Kirsher if (rc) 1829adfc5217SJeff Kirsher goto error_exit; 1830adfc5217SJeff Kirsher 1831adfc5217SJeff Kirsher WARN_ON(!reg_elem); 1832adfc5217SJeff Kirsher 1833adfc5217SJeff Kirsher /* Push a new entry into the registry */ 1834adfc5217SJeff Kirsher if (!restore && 1835adfc5217SJeff Kirsher ((cmd == BNX2X_VLAN_MAC_ADD) || 1836adfc5217SJeff Kirsher (cmd == BNX2X_VLAN_MAC_MOVE))) 1837adfc5217SJeff Kirsher list_add(®_elem->link, &cam_obj->head); 1838adfc5217SJeff Kirsher 1839adfc5217SJeff Kirsher /* Configure a single command in a ramrod data buffer */ 1840adfc5217SJeff Kirsher o->set_one_rule(bp, o, elem, idx, 1841adfc5217SJeff Kirsher reg_elem->cam_offset); 1842adfc5217SJeff Kirsher 1843adfc5217SJeff Kirsher /* MOVE command consumes 2 entries in the ramrod data */ 1844adfc5217SJeff Kirsher if (cmd == BNX2X_VLAN_MAC_MOVE) 1845adfc5217SJeff Kirsher idx += 2; 1846adfc5217SJeff Kirsher else 1847adfc5217SJeff Kirsher idx++; 1848adfc5217SJeff Kirsher } 1849adfc5217SJeff Kirsher 185016a5fd92SYuval Mintz /* No need for an explicit memory barrier here as long we would 1851adfc5217SJeff Kirsher * need to ensure the ordering of writing to the SPQ element 1852adfc5217SJeff Kirsher * and updating of the SPQ producer which involves a memory 1853adfc5217SJeff Kirsher * read and we will have to put a full memory barrier there 1854adfc5217SJeff Kirsher * (inside bnx2x_sp_post()). 1855adfc5217SJeff Kirsher */ 1856adfc5217SJeff Kirsher 1857adfc5217SJeff Kirsher rc = bnx2x_sp_post(bp, o->ramrod_cmd, r->cid, 1858adfc5217SJeff Kirsher U64_HI(r->rdata_mapping), 1859adfc5217SJeff Kirsher U64_LO(r->rdata_mapping), 1860adfc5217SJeff Kirsher ETH_CONNECTION_TYPE); 1861adfc5217SJeff Kirsher if (rc) 1862adfc5217SJeff Kirsher goto error_exit; 1863adfc5217SJeff Kirsher } 1864adfc5217SJeff Kirsher 1865adfc5217SJeff Kirsher /* Now, when we are done with the ramrod - clean up the registry */ 1866adfc5217SJeff Kirsher list_for_each_entry(elem, exe_chunk, link) { 1867adfc5217SJeff Kirsher cmd = elem->cmd_data.vlan_mac.cmd; 1868adfc5217SJeff Kirsher if ((cmd == BNX2X_VLAN_MAC_DEL) || 1869adfc5217SJeff Kirsher (cmd == BNX2X_VLAN_MAC_MOVE)) { 187051c1a580SMerav Sicron reg_elem = o->check_del(bp, o, 187151c1a580SMerav Sicron &elem->cmd_data.vlan_mac.u); 1872adfc5217SJeff Kirsher 1873adfc5217SJeff Kirsher WARN_ON(!reg_elem); 1874adfc5217SJeff Kirsher 1875adfc5217SJeff Kirsher o->put_cam_offset(o, reg_elem->cam_offset); 1876adfc5217SJeff Kirsher list_del(®_elem->link); 1877adfc5217SJeff Kirsher kfree(reg_elem); 1878adfc5217SJeff Kirsher } 1879adfc5217SJeff Kirsher } 1880adfc5217SJeff Kirsher 1881adfc5217SJeff Kirsher if (!drv_only) 1882adfc5217SJeff Kirsher return 1; 1883adfc5217SJeff Kirsher else 1884adfc5217SJeff Kirsher return 0; 1885adfc5217SJeff Kirsher 1886adfc5217SJeff Kirsher error_exit: 1887adfc5217SJeff Kirsher r->clear_pending(r); 1888adfc5217SJeff Kirsher 1889adfc5217SJeff Kirsher /* Cleanup a registry in case of a failure */ 1890adfc5217SJeff Kirsher list_for_each_entry(elem, exe_chunk, link) { 1891adfc5217SJeff Kirsher cmd = elem->cmd_data.vlan_mac.cmd; 1892adfc5217SJeff Kirsher 1893adfc5217SJeff Kirsher if (cmd == BNX2X_VLAN_MAC_MOVE) 1894adfc5217SJeff Kirsher cam_obj = elem->cmd_data.vlan_mac.target_obj; 1895adfc5217SJeff Kirsher else 1896adfc5217SJeff Kirsher cam_obj = o; 1897adfc5217SJeff Kirsher 1898adfc5217SJeff Kirsher /* Delete all newly added above entries */ 1899adfc5217SJeff Kirsher if (!restore && 1900adfc5217SJeff Kirsher ((cmd == BNX2X_VLAN_MAC_ADD) || 1901adfc5217SJeff Kirsher (cmd == BNX2X_VLAN_MAC_MOVE))) { 190251c1a580SMerav Sicron reg_elem = o->check_del(bp, cam_obj, 1903adfc5217SJeff Kirsher &elem->cmd_data.vlan_mac.u); 1904adfc5217SJeff Kirsher if (reg_elem) { 1905adfc5217SJeff Kirsher list_del(®_elem->link); 1906adfc5217SJeff Kirsher kfree(reg_elem); 1907adfc5217SJeff Kirsher } 1908adfc5217SJeff Kirsher } 1909adfc5217SJeff Kirsher } 1910adfc5217SJeff Kirsher 1911adfc5217SJeff Kirsher return rc; 1912adfc5217SJeff Kirsher } 1913adfc5217SJeff Kirsher 1914adfc5217SJeff Kirsher static inline int bnx2x_vlan_mac_push_new_cmd( 1915adfc5217SJeff Kirsher struct bnx2x *bp, 1916adfc5217SJeff Kirsher struct bnx2x_vlan_mac_ramrod_params *p) 1917adfc5217SJeff Kirsher { 1918adfc5217SJeff Kirsher struct bnx2x_exeq_elem *elem; 1919adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *o = p->vlan_mac_obj; 1920adfc5217SJeff Kirsher bool restore = test_bit(RAMROD_RESTORE, &p->ramrod_flags); 1921adfc5217SJeff Kirsher 1922adfc5217SJeff Kirsher /* Allocate the execution queue element */ 1923adfc5217SJeff Kirsher elem = bnx2x_exe_queue_alloc_elem(bp); 1924adfc5217SJeff Kirsher if (!elem) 1925adfc5217SJeff Kirsher return -ENOMEM; 1926adfc5217SJeff Kirsher 1927adfc5217SJeff Kirsher /* Set the command 'length' */ 1928adfc5217SJeff Kirsher switch (p->user_req.cmd) { 1929adfc5217SJeff Kirsher case BNX2X_VLAN_MAC_MOVE: 1930adfc5217SJeff Kirsher elem->cmd_len = 2; 1931adfc5217SJeff Kirsher break; 1932adfc5217SJeff Kirsher default: 1933adfc5217SJeff Kirsher elem->cmd_len = 1; 1934adfc5217SJeff Kirsher } 1935adfc5217SJeff Kirsher 1936adfc5217SJeff Kirsher /* Fill the object specific info */ 1937adfc5217SJeff Kirsher memcpy(&elem->cmd_data.vlan_mac, &p->user_req, sizeof(p->user_req)); 1938adfc5217SJeff Kirsher 1939adfc5217SJeff Kirsher /* Try to add a new command to the pending list */ 1940adfc5217SJeff Kirsher return bnx2x_exe_queue_add(bp, &o->exe_queue, elem, restore); 1941adfc5217SJeff Kirsher } 1942adfc5217SJeff Kirsher 1943adfc5217SJeff Kirsher /** 1944adfc5217SJeff Kirsher * bnx2x_config_vlan_mac - configure VLAN/MAC/VLAN_MAC filtering rules. 1945adfc5217SJeff Kirsher * 1946adfc5217SJeff Kirsher * @bp: device handle 1947adfc5217SJeff Kirsher * @p: 1948adfc5217SJeff Kirsher * 1949adfc5217SJeff Kirsher */ 19508b09be5fSYuval Mintz int bnx2x_config_vlan_mac(struct bnx2x *bp, 1951adfc5217SJeff Kirsher struct bnx2x_vlan_mac_ramrod_params *p) 1952adfc5217SJeff Kirsher { 1953adfc5217SJeff Kirsher int rc = 0; 1954adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *o = p->vlan_mac_obj; 1955adfc5217SJeff Kirsher unsigned long *ramrod_flags = &p->ramrod_flags; 1956adfc5217SJeff Kirsher bool cont = test_bit(RAMROD_CONT, ramrod_flags); 1957adfc5217SJeff Kirsher struct bnx2x_raw_obj *raw = &o->raw; 1958adfc5217SJeff Kirsher 1959adfc5217SJeff Kirsher /* 1960adfc5217SJeff Kirsher * Add new elements to the execution list for commands that require it. 1961adfc5217SJeff Kirsher */ 1962adfc5217SJeff Kirsher if (!cont) { 1963adfc5217SJeff Kirsher rc = bnx2x_vlan_mac_push_new_cmd(bp, p); 1964adfc5217SJeff Kirsher if (rc) 1965adfc5217SJeff Kirsher return rc; 1966adfc5217SJeff Kirsher } 1967adfc5217SJeff Kirsher 196816a5fd92SYuval Mintz /* If nothing will be executed further in this iteration we want to 1969adfc5217SJeff Kirsher * return PENDING if there are pending commands 1970adfc5217SJeff Kirsher */ 1971adfc5217SJeff Kirsher if (!bnx2x_exe_queue_empty(&o->exe_queue)) 1972adfc5217SJeff Kirsher rc = 1; 1973adfc5217SJeff Kirsher 1974adfc5217SJeff Kirsher if (test_bit(RAMROD_DRV_CLR_ONLY, ramrod_flags)) { 197551c1a580SMerav Sicron DP(BNX2X_MSG_SP, "RAMROD_DRV_CLR_ONLY requested: clearing a pending bit.\n"); 1976adfc5217SJeff Kirsher raw->clear_pending(raw); 1977adfc5217SJeff Kirsher } 1978adfc5217SJeff Kirsher 1979adfc5217SJeff Kirsher /* Execute commands if required */ 1980adfc5217SJeff Kirsher if (cont || test_bit(RAMROD_EXEC, ramrod_flags) || 1981adfc5217SJeff Kirsher test_bit(RAMROD_COMP_WAIT, ramrod_flags)) { 19828b09be5fSYuval Mintz rc = __bnx2x_vlan_mac_execute_step(bp, p->vlan_mac_obj, 19838b09be5fSYuval Mintz &p->ramrod_flags); 1984adfc5217SJeff Kirsher if (rc < 0) 1985adfc5217SJeff Kirsher return rc; 1986adfc5217SJeff Kirsher } 1987adfc5217SJeff Kirsher 198816a5fd92SYuval Mintz /* RAMROD_COMP_WAIT is a superset of RAMROD_EXEC. If it was set 1989adfc5217SJeff Kirsher * then user want to wait until the last command is done. 1990adfc5217SJeff Kirsher */ 1991adfc5217SJeff Kirsher if (test_bit(RAMROD_COMP_WAIT, &p->ramrod_flags)) { 199216a5fd92SYuval Mintz /* Wait maximum for the current exe_queue length iterations plus 1993adfc5217SJeff Kirsher * one (for the current pending command). 1994adfc5217SJeff Kirsher */ 1995adfc5217SJeff Kirsher int max_iterations = bnx2x_exe_queue_length(&o->exe_queue) + 1; 1996adfc5217SJeff Kirsher 1997adfc5217SJeff Kirsher while (!bnx2x_exe_queue_empty(&o->exe_queue) && 1998adfc5217SJeff Kirsher max_iterations--) { 1999adfc5217SJeff Kirsher 2000adfc5217SJeff Kirsher /* Wait for the current command to complete */ 2001adfc5217SJeff Kirsher rc = raw->wait_comp(bp, raw); 2002adfc5217SJeff Kirsher if (rc) 2003adfc5217SJeff Kirsher return rc; 2004adfc5217SJeff Kirsher 2005adfc5217SJeff Kirsher /* Make a next step */ 20068b09be5fSYuval Mintz rc = __bnx2x_vlan_mac_execute_step(bp, 20078b09be5fSYuval Mintz p->vlan_mac_obj, 20088b09be5fSYuval Mintz &p->ramrod_flags); 2009adfc5217SJeff Kirsher if (rc < 0) 2010adfc5217SJeff Kirsher return rc; 2011adfc5217SJeff Kirsher } 2012adfc5217SJeff Kirsher 2013adfc5217SJeff Kirsher return 0; 2014adfc5217SJeff Kirsher } 2015adfc5217SJeff Kirsher 2016adfc5217SJeff Kirsher return rc; 2017adfc5217SJeff Kirsher } 2018adfc5217SJeff Kirsher 2019adfc5217SJeff Kirsher /** 2020adfc5217SJeff Kirsher * bnx2x_vlan_mac_del_all - delete elements with given vlan_mac_flags spec 2021adfc5217SJeff Kirsher * 2022adfc5217SJeff Kirsher * @bp: device handle 2023adfc5217SJeff Kirsher * @o: 2024adfc5217SJeff Kirsher * @vlan_mac_flags: 2025adfc5217SJeff Kirsher * @ramrod_flags: execution flags to be used for this deletion 2026adfc5217SJeff Kirsher * 2027adfc5217SJeff Kirsher * if the last operation has completed successfully and there are no 2028adfc5217SJeff Kirsher * more elements left, positive value if the last operation has completed 2029adfc5217SJeff Kirsher * successfully and there are more previously configured elements, negative 2030adfc5217SJeff Kirsher * value is current operation has failed. 2031adfc5217SJeff Kirsher */ 2032adfc5217SJeff Kirsher static int bnx2x_vlan_mac_del_all(struct bnx2x *bp, 2033adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *o, 2034adfc5217SJeff Kirsher unsigned long *vlan_mac_flags, 2035adfc5217SJeff Kirsher unsigned long *ramrod_flags) 2036adfc5217SJeff Kirsher { 2037adfc5217SJeff Kirsher struct bnx2x_vlan_mac_registry_elem *pos = NULL; 2038adfc5217SJeff Kirsher struct bnx2x_vlan_mac_ramrod_params p; 2039adfc5217SJeff Kirsher struct bnx2x_exe_queue_obj *exeq = &o->exe_queue; 2040adfc5217SJeff Kirsher struct bnx2x_exeq_elem *exeq_pos, *exeq_pos_n; 2041e8379c79SYuval Mintz unsigned long flags; 20428b09be5fSYuval Mintz int read_lock; 20438b09be5fSYuval Mintz int rc = 0; 2044adfc5217SJeff Kirsher 2045adfc5217SJeff Kirsher /* Clear pending commands first */ 2046adfc5217SJeff Kirsher 2047adfc5217SJeff Kirsher spin_lock_bh(&exeq->lock); 2048adfc5217SJeff Kirsher 2049adfc5217SJeff Kirsher list_for_each_entry_safe(exeq_pos, exeq_pos_n, &exeq->exe_queue, link) { 2050e8379c79SYuval Mintz flags = exeq_pos->cmd_data.vlan_mac.vlan_mac_flags; 2051e8379c79SYuval Mintz if (BNX2X_VLAN_MAC_CMP_FLAGS(flags) == 2052e8379c79SYuval Mintz BNX2X_VLAN_MAC_CMP_FLAGS(*vlan_mac_flags)) { 2053460a25cdSYuval Mintz rc = exeq->remove(bp, exeq->owner, exeq_pos); 2054460a25cdSYuval Mintz if (rc) { 2055460a25cdSYuval Mintz BNX2X_ERR("Failed to remove command\n"); 2056a44acd55SDan Carpenter spin_unlock_bh(&exeq->lock); 2057460a25cdSYuval Mintz return rc; 2058460a25cdSYuval Mintz } 2059adfc5217SJeff Kirsher list_del(&exeq_pos->link); 206007ef7becSYuval Mintz bnx2x_exe_queue_free_elem(bp, exeq_pos); 2061adfc5217SJeff Kirsher } 2062460a25cdSYuval Mintz } 2063adfc5217SJeff Kirsher 2064adfc5217SJeff Kirsher spin_unlock_bh(&exeq->lock); 2065adfc5217SJeff Kirsher 2066adfc5217SJeff Kirsher /* Prepare a command request */ 2067adfc5217SJeff Kirsher memset(&p, 0, sizeof(p)); 2068adfc5217SJeff Kirsher p.vlan_mac_obj = o; 2069adfc5217SJeff Kirsher p.ramrod_flags = *ramrod_flags; 2070adfc5217SJeff Kirsher p.user_req.cmd = BNX2X_VLAN_MAC_DEL; 2071adfc5217SJeff Kirsher 207216a5fd92SYuval Mintz /* Add all but the last VLAN-MAC to the execution queue without actually 2073adfc5217SJeff Kirsher * execution anything. 2074adfc5217SJeff Kirsher */ 2075adfc5217SJeff Kirsher __clear_bit(RAMROD_COMP_WAIT, &p.ramrod_flags); 2076adfc5217SJeff Kirsher __clear_bit(RAMROD_EXEC, &p.ramrod_flags); 2077adfc5217SJeff Kirsher __clear_bit(RAMROD_CONT, &p.ramrod_flags); 2078adfc5217SJeff Kirsher 20798b09be5fSYuval Mintz DP(BNX2X_MSG_SP, "vlan_mac_del_all -- taking vlan_mac_lock (reader)\n"); 20808b09be5fSYuval Mintz read_lock = bnx2x_vlan_mac_h_read_lock(bp, o); 20818b09be5fSYuval Mintz if (read_lock != 0) 20828b09be5fSYuval Mintz return read_lock; 20838b09be5fSYuval Mintz 2084adfc5217SJeff Kirsher list_for_each_entry(pos, &o->head, link) { 2085e8379c79SYuval Mintz flags = pos->vlan_mac_flags; 2086e8379c79SYuval Mintz if (BNX2X_VLAN_MAC_CMP_FLAGS(flags) == 2087e8379c79SYuval Mintz BNX2X_VLAN_MAC_CMP_FLAGS(*vlan_mac_flags)) { 2088adfc5217SJeff Kirsher p.user_req.vlan_mac_flags = pos->vlan_mac_flags; 2089adfc5217SJeff Kirsher memcpy(&p.user_req.u, &pos->u, sizeof(pos->u)); 2090adfc5217SJeff Kirsher rc = bnx2x_config_vlan_mac(bp, &p); 2091adfc5217SJeff Kirsher if (rc < 0) { 2092adfc5217SJeff Kirsher BNX2X_ERR("Failed to add a new DEL command\n"); 20938b09be5fSYuval Mintz bnx2x_vlan_mac_h_read_unlock(bp, o); 2094adfc5217SJeff Kirsher return rc; 2095adfc5217SJeff Kirsher } 2096adfc5217SJeff Kirsher } 2097adfc5217SJeff Kirsher } 2098adfc5217SJeff Kirsher 20998b09be5fSYuval Mintz DP(BNX2X_MSG_SP, "vlan_mac_del_all -- releasing vlan_mac_lock (reader)\n"); 21008b09be5fSYuval Mintz bnx2x_vlan_mac_h_read_unlock(bp, o); 21018b09be5fSYuval Mintz 2102adfc5217SJeff Kirsher p.ramrod_flags = *ramrod_flags; 2103adfc5217SJeff Kirsher __set_bit(RAMROD_CONT, &p.ramrod_flags); 2104adfc5217SJeff Kirsher 2105adfc5217SJeff Kirsher return bnx2x_config_vlan_mac(bp, &p); 2106adfc5217SJeff Kirsher } 2107adfc5217SJeff Kirsher 2108adfc5217SJeff Kirsher static inline void bnx2x_init_raw_obj(struct bnx2x_raw_obj *raw, u8 cl_id, 2109adfc5217SJeff Kirsher u32 cid, u8 func_id, void *rdata, dma_addr_t rdata_mapping, int state, 2110adfc5217SJeff Kirsher unsigned long *pstate, bnx2x_obj_type type) 2111adfc5217SJeff Kirsher { 2112adfc5217SJeff Kirsher raw->func_id = func_id; 2113adfc5217SJeff Kirsher raw->cid = cid; 2114adfc5217SJeff Kirsher raw->cl_id = cl_id; 2115adfc5217SJeff Kirsher raw->rdata = rdata; 2116adfc5217SJeff Kirsher raw->rdata_mapping = rdata_mapping; 2117adfc5217SJeff Kirsher raw->state = state; 2118adfc5217SJeff Kirsher raw->pstate = pstate; 2119adfc5217SJeff Kirsher raw->obj_type = type; 2120adfc5217SJeff Kirsher raw->check_pending = bnx2x_raw_check_pending; 2121adfc5217SJeff Kirsher raw->clear_pending = bnx2x_raw_clear_pending; 2122adfc5217SJeff Kirsher raw->set_pending = bnx2x_raw_set_pending; 2123adfc5217SJeff Kirsher raw->wait_comp = bnx2x_raw_wait; 2124adfc5217SJeff Kirsher } 2125adfc5217SJeff Kirsher 2126adfc5217SJeff Kirsher static inline void bnx2x_init_vlan_mac_common(struct bnx2x_vlan_mac_obj *o, 2127adfc5217SJeff Kirsher u8 cl_id, u32 cid, u8 func_id, void *rdata, dma_addr_t rdata_mapping, 2128adfc5217SJeff Kirsher int state, unsigned long *pstate, bnx2x_obj_type type, 2129adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *macs_pool, 2130adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *vlans_pool) 2131adfc5217SJeff Kirsher { 2132adfc5217SJeff Kirsher INIT_LIST_HEAD(&o->head); 21338b09be5fSYuval Mintz o->head_reader = 0; 21348b09be5fSYuval Mintz o->head_exe_request = false; 21358b09be5fSYuval Mintz o->saved_ramrod_flags = 0; 2136adfc5217SJeff Kirsher 2137adfc5217SJeff Kirsher o->macs_pool = macs_pool; 2138adfc5217SJeff Kirsher o->vlans_pool = vlans_pool; 2139adfc5217SJeff Kirsher 2140adfc5217SJeff Kirsher o->delete_all = bnx2x_vlan_mac_del_all; 2141adfc5217SJeff Kirsher o->restore = bnx2x_vlan_mac_restore; 2142adfc5217SJeff Kirsher o->complete = bnx2x_complete_vlan_mac; 2143adfc5217SJeff Kirsher o->wait = bnx2x_wait_vlan_mac; 2144adfc5217SJeff Kirsher 2145adfc5217SJeff Kirsher bnx2x_init_raw_obj(&o->raw, cl_id, cid, func_id, rdata, rdata_mapping, 2146adfc5217SJeff Kirsher state, pstate, type); 2147adfc5217SJeff Kirsher } 2148adfc5217SJeff Kirsher 2149adfc5217SJeff Kirsher void bnx2x_init_mac_obj(struct bnx2x *bp, 2150adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *mac_obj, 2151adfc5217SJeff Kirsher u8 cl_id, u32 cid, u8 func_id, void *rdata, 2152adfc5217SJeff Kirsher dma_addr_t rdata_mapping, int state, 2153adfc5217SJeff Kirsher unsigned long *pstate, bnx2x_obj_type type, 2154adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *macs_pool) 2155adfc5217SJeff Kirsher { 2156adfc5217SJeff Kirsher union bnx2x_qable_obj *qable_obj = (union bnx2x_qable_obj *)mac_obj; 2157adfc5217SJeff Kirsher 2158adfc5217SJeff Kirsher bnx2x_init_vlan_mac_common(mac_obj, cl_id, cid, func_id, rdata, 2159adfc5217SJeff Kirsher rdata_mapping, state, pstate, type, 2160adfc5217SJeff Kirsher macs_pool, NULL); 2161adfc5217SJeff Kirsher 2162adfc5217SJeff Kirsher /* CAM credit pool handling */ 2163adfc5217SJeff Kirsher mac_obj->get_credit = bnx2x_get_credit_mac; 2164adfc5217SJeff Kirsher mac_obj->put_credit = bnx2x_put_credit_mac; 2165adfc5217SJeff Kirsher mac_obj->get_cam_offset = bnx2x_get_cam_offset_mac; 2166adfc5217SJeff Kirsher mac_obj->put_cam_offset = bnx2x_put_cam_offset_mac; 2167adfc5217SJeff Kirsher 2168adfc5217SJeff Kirsher if (CHIP_IS_E1x(bp)) { 2169adfc5217SJeff Kirsher mac_obj->set_one_rule = bnx2x_set_one_mac_e1x; 2170adfc5217SJeff Kirsher mac_obj->check_del = bnx2x_check_mac_del; 2171adfc5217SJeff Kirsher mac_obj->check_add = bnx2x_check_mac_add; 2172adfc5217SJeff Kirsher mac_obj->check_move = bnx2x_check_move_always_err; 2173adfc5217SJeff Kirsher mac_obj->ramrod_cmd = RAMROD_CMD_ID_ETH_SET_MAC; 2174adfc5217SJeff Kirsher 2175adfc5217SJeff Kirsher /* Exe Queue */ 2176adfc5217SJeff Kirsher bnx2x_exe_queue_init(bp, 2177adfc5217SJeff Kirsher &mac_obj->exe_queue, 1, qable_obj, 2178adfc5217SJeff Kirsher bnx2x_validate_vlan_mac, 2179460a25cdSYuval Mintz bnx2x_remove_vlan_mac, 2180adfc5217SJeff Kirsher bnx2x_optimize_vlan_mac, 2181adfc5217SJeff Kirsher bnx2x_execute_vlan_mac, 2182adfc5217SJeff Kirsher bnx2x_exeq_get_mac); 2183adfc5217SJeff Kirsher } else { 2184adfc5217SJeff Kirsher mac_obj->set_one_rule = bnx2x_set_one_mac_e2; 2185adfc5217SJeff Kirsher mac_obj->check_del = bnx2x_check_mac_del; 2186adfc5217SJeff Kirsher mac_obj->check_add = bnx2x_check_mac_add; 2187adfc5217SJeff Kirsher mac_obj->check_move = bnx2x_check_move; 2188adfc5217SJeff Kirsher mac_obj->ramrod_cmd = 2189adfc5217SJeff Kirsher RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES; 2190ed5162a0SAriel Elior mac_obj->get_n_elements = bnx2x_get_n_elements; 2191adfc5217SJeff Kirsher 2192adfc5217SJeff Kirsher /* Exe Queue */ 2193adfc5217SJeff Kirsher bnx2x_exe_queue_init(bp, 2194adfc5217SJeff Kirsher &mac_obj->exe_queue, CLASSIFY_RULES_COUNT, 2195adfc5217SJeff Kirsher qable_obj, bnx2x_validate_vlan_mac, 2196460a25cdSYuval Mintz bnx2x_remove_vlan_mac, 2197adfc5217SJeff Kirsher bnx2x_optimize_vlan_mac, 2198adfc5217SJeff Kirsher bnx2x_execute_vlan_mac, 2199adfc5217SJeff Kirsher bnx2x_exeq_get_mac); 2200adfc5217SJeff Kirsher } 2201adfc5217SJeff Kirsher } 2202adfc5217SJeff Kirsher 2203adfc5217SJeff Kirsher void bnx2x_init_vlan_obj(struct bnx2x *bp, 2204adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *vlan_obj, 2205adfc5217SJeff Kirsher u8 cl_id, u32 cid, u8 func_id, void *rdata, 2206adfc5217SJeff Kirsher dma_addr_t rdata_mapping, int state, 2207adfc5217SJeff Kirsher unsigned long *pstate, bnx2x_obj_type type, 2208adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *vlans_pool) 2209adfc5217SJeff Kirsher { 2210adfc5217SJeff Kirsher union bnx2x_qable_obj *qable_obj = (union bnx2x_qable_obj *)vlan_obj; 2211adfc5217SJeff Kirsher 2212adfc5217SJeff Kirsher bnx2x_init_vlan_mac_common(vlan_obj, cl_id, cid, func_id, rdata, 2213adfc5217SJeff Kirsher rdata_mapping, state, pstate, type, NULL, 2214adfc5217SJeff Kirsher vlans_pool); 2215adfc5217SJeff Kirsher 2216adfc5217SJeff Kirsher vlan_obj->get_credit = bnx2x_get_credit_vlan; 2217adfc5217SJeff Kirsher vlan_obj->put_credit = bnx2x_put_credit_vlan; 2218adfc5217SJeff Kirsher vlan_obj->get_cam_offset = bnx2x_get_cam_offset_vlan; 2219adfc5217SJeff Kirsher vlan_obj->put_cam_offset = bnx2x_put_cam_offset_vlan; 2220adfc5217SJeff Kirsher 2221adfc5217SJeff Kirsher if (CHIP_IS_E1x(bp)) { 2222adfc5217SJeff Kirsher BNX2X_ERR("Do not support chips others than E2 and newer\n"); 2223adfc5217SJeff Kirsher BUG(); 2224adfc5217SJeff Kirsher } else { 2225adfc5217SJeff Kirsher vlan_obj->set_one_rule = bnx2x_set_one_vlan_e2; 2226adfc5217SJeff Kirsher vlan_obj->check_del = bnx2x_check_vlan_del; 2227adfc5217SJeff Kirsher vlan_obj->check_add = bnx2x_check_vlan_add; 2228adfc5217SJeff Kirsher vlan_obj->check_move = bnx2x_check_move; 2229adfc5217SJeff Kirsher vlan_obj->ramrod_cmd = 2230adfc5217SJeff Kirsher RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES; 22313ec9f9caSAriel Elior vlan_obj->get_n_elements = bnx2x_get_n_elements; 2232adfc5217SJeff Kirsher 2233adfc5217SJeff Kirsher /* Exe Queue */ 2234adfc5217SJeff Kirsher bnx2x_exe_queue_init(bp, 2235adfc5217SJeff Kirsher &vlan_obj->exe_queue, CLASSIFY_RULES_COUNT, 2236adfc5217SJeff Kirsher qable_obj, bnx2x_validate_vlan_mac, 2237460a25cdSYuval Mintz bnx2x_remove_vlan_mac, 2238adfc5217SJeff Kirsher bnx2x_optimize_vlan_mac, 2239adfc5217SJeff Kirsher bnx2x_execute_vlan_mac, 2240adfc5217SJeff Kirsher bnx2x_exeq_get_vlan); 2241adfc5217SJeff Kirsher } 2242adfc5217SJeff Kirsher } 2243adfc5217SJeff Kirsher 2244adfc5217SJeff Kirsher void bnx2x_init_vlan_mac_obj(struct bnx2x *bp, 2245adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *vlan_mac_obj, 2246adfc5217SJeff Kirsher u8 cl_id, u32 cid, u8 func_id, void *rdata, 2247adfc5217SJeff Kirsher dma_addr_t rdata_mapping, int state, 2248adfc5217SJeff Kirsher unsigned long *pstate, bnx2x_obj_type type, 2249adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *macs_pool, 2250adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *vlans_pool) 2251adfc5217SJeff Kirsher { 2252adfc5217SJeff Kirsher union bnx2x_qable_obj *qable_obj = 2253adfc5217SJeff Kirsher (union bnx2x_qable_obj *)vlan_mac_obj; 2254adfc5217SJeff Kirsher 2255adfc5217SJeff Kirsher bnx2x_init_vlan_mac_common(vlan_mac_obj, cl_id, cid, func_id, rdata, 2256adfc5217SJeff Kirsher rdata_mapping, state, pstate, type, 2257adfc5217SJeff Kirsher macs_pool, vlans_pool); 2258adfc5217SJeff Kirsher 2259adfc5217SJeff Kirsher /* CAM pool handling */ 2260adfc5217SJeff Kirsher vlan_mac_obj->get_credit = bnx2x_get_credit_vlan_mac; 2261adfc5217SJeff Kirsher vlan_mac_obj->put_credit = bnx2x_put_credit_vlan_mac; 226216a5fd92SYuval Mintz /* CAM offset is relevant for 57710 and 57711 chips only which have a 2263adfc5217SJeff Kirsher * single CAM for both MACs and VLAN-MAC pairs. So the offset 2264adfc5217SJeff Kirsher * will be taken from MACs' pool object only. 2265adfc5217SJeff Kirsher */ 2266adfc5217SJeff Kirsher vlan_mac_obj->get_cam_offset = bnx2x_get_cam_offset_mac; 2267adfc5217SJeff Kirsher vlan_mac_obj->put_cam_offset = bnx2x_put_cam_offset_mac; 2268adfc5217SJeff Kirsher 2269adfc5217SJeff Kirsher if (CHIP_IS_E1(bp)) { 2270adfc5217SJeff Kirsher BNX2X_ERR("Do not support chips others than E2\n"); 2271adfc5217SJeff Kirsher BUG(); 2272adfc5217SJeff Kirsher } else if (CHIP_IS_E1H(bp)) { 2273adfc5217SJeff Kirsher vlan_mac_obj->set_one_rule = bnx2x_set_one_vlan_mac_e1h; 2274adfc5217SJeff Kirsher vlan_mac_obj->check_del = bnx2x_check_vlan_mac_del; 2275adfc5217SJeff Kirsher vlan_mac_obj->check_add = bnx2x_check_vlan_mac_add; 2276adfc5217SJeff Kirsher vlan_mac_obj->check_move = bnx2x_check_move_always_err; 2277adfc5217SJeff Kirsher vlan_mac_obj->ramrod_cmd = RAMROD_CMD_ID_ETH_SET_MAC; 2278adfc5217SJeff Kirsher 2279adfc5217SJeff Kirsher /* Exe Queue */ 2280adfc5217SJeff Kirsher bnx2x_exe_queue_init(bp, 2281adfc5217SJeff Kirsher &vlan_mac_obj->exe_queue, 1, qable_obj, 2282adfc5217SJeff Kirsher bnx2x_validate_vlan_mac, 2283460a25cdSYuval Mintz bnx2x_remove_vlan_mac, 2284adfc5217SJeff Kirsher bnx2x_optimize_vlan_mac, 2285adfc5217SJeff Kirsher bnx2x_execute_vlan_mac, 2286adfc5217SJeff Kirsher bnx2x_exeq_get_vlan_mac); 2287adfc5217SJeff Kirsher } else { 2288adfc5217SJeff Kirsher vlan_mac_obj->set_one_rule = bnx2x_set_one_vlan_mac_e2; 2289adfc5217SJeff Kirsher vlan_mac_obj->check_del = bnx2x_check_vlan_mac_del; 2290adfc5217SJeff Kirsher vlan_mac_obj->check_add = bnx2x_check_vlan_mac_add; 2291adfc5217SJeff Kirsher vlan_mac_obj->check_move = bnx2x_check_move; 2292adfc5217SJeff Kirsher vlan_mac_obj->ramrod_cmd = 2293adfc5217SJeff Kirsher RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES; 2294adfc5217SJeff Kirsher 2295adfc5217SJeff Kirsher /* Exe Queue */ 2296adfc5217SJeff Kirsher bnx2x_exe_queue_init(bp, 2297adfc5217SJeff Kirsher &vlan_mac_obj->exe_queue, 2298adfc5217SJeff Kirsher CLASSIFY_RULES_COUNT, 2299adfc5217SJeff Kirsher qable_obj, bnx2x_validate_vlan_mac, 2300460a25cdSYuval Mintz bnx2x_remove_vlan_mac, 2301adfc5217SJeff Kirsher bnx2x_optimize_vlan_mac, 2302adfc5217SJeff Kirsher bnx2x_execute_vlan_mac, 2303adfc5217SJeff Kirsher bnx2x_exeq_get_vlan_mac); 2304adfc5217SJeff Kirsher } 2305adfc5217SJeff Kirsher } 2306adfc5217SJeff Kirsher 2307adfc5217SJeff Kirsher /* RX_MODE verbs: DROP_ALL/ACCEPT_ALL/ACCEPT_ALL_MULTI/ACCEPT_ALL_VLAN/NORMAL */ 2308adfc5217SJeff Kirsher static inline void __storm_memset_mac_filters(struct bnx2x *bp, 2309adfc5217SJeff Kirsher struct tstorm_eth_mac_filter_config *mac_filters, 2310adfc5217SJeff Kirsher u16 pf_id) 2311adfc5217SJeff Kirsher { 2312adfc5217SJeff Kirsher size_t size = sizeof(struct tstorm_eth_mac_filter_config); 2313adfc5217SJeff Kirsher 2314adfc5217SJeff Kirsher u32 addr = BAR_TSTRORM_INTMEM + 2315adfc5217SJeff Kirsher TSTORM_MAC_FILTER_CONFIG_OFFSET(pf_id); 2316adfc5217SJeff Kirsher 2317adfc5217SJeff Kirsher __storm_memset_struct(bp, addr, size, (u32 *)mac_filters); 2318adfc5217SJeff Kirsher } 2319adfc5217SJeff Kirsher 2320adfc5217SJeff Kirsher static int bnx2x_set_rx_mode_e1x(struct bnx2x *bp, 2321adfc5217SJeff Kirsher struct bnx2x_rx_mode_ramrod_params *p) 2322adfc5217SJeff Kirsher { 2323adfc5217SJeff Kirsher /* update the bp MAC filter structure */ 2324adfc5217SJeff Kirsher u32 mask = (1 << p->cl_id); 2325adfc5217SJeff Kirsher 2326adfc5217SJeff Kirsher struct tstorm_eth_mac_filter_config *mac_filters = 2327adfc5217SJeff Kirsher (struct tstorm_eth_mac_filter_config *)p->rdata; 2328adfc5217SJeff Kirsher 232916a5fd92SYuval Mintz /* initial setting is drop-all */ 2330adfc5217SJeff Kirsher u8 drop_all_ucast = 1, drop_all_mcast = 1; 2331adfc5217SJeff Kirsher u8 accp_all_ucast = 0, accp_all_bcast = 0, accp_all_mcast = 0; 2332adfc5217SJeff Kirsher u8 unmatched_unicast = 0; 2333adfc5217SJeff Kirsher 233416a5fd92SYuval Mintz /* In e1x there we only take into account rx accept flag since tx switching 2335adfc5217SJeff Kirsher * isn't enabled. */ 2336adfc5217SJeff Kirsher if (test_bit(BNX2X_ACCEPT_UNICAST, &p->rx_accept_flags)) 2337adfc5217SJeff Kirsher /* accept matched ucast */ 2338adfc5217SJeff Kirsher drop_all_ucast = 0; 2339adfc5217SJeff Kirsher 2340adfc5217SJeff Kirsher if (test_bit(BNX2X_ACCEPT_MULTICAST, &p->rx_accept_flags)) 2341adfc5217SJeff Kirsher /* accept matched mcast */ 2342adfc5217SJeff Kirsher drop_all_mcast = 0; 2343adfc5217SJeff Kirsher 2344adfc5217SJeff Kirsher if (test_bit(BNX2X_ACCEPT_ALL_UNICAST, &p->rx_accept_flags)) { 2345adfc5217SJeff Kirsher /* accept all mcast */ 2346adfc5217SJeff Kirsher drop_all_ucast = 0; 2347adfc5217SJeff Kirsher accp_all_ucast = 1; 2348adfc5217SJeff Kirsher } 2349adfc5217SJeff Kirsher if (test_bit(BNX2X_ACCEPT_ALL_MULTICAST, &p->rx_accept_flags)) { 2350adfc5217SJeff Kirsher /* accept all mcast */ 2351adfc5217SJeff Kirsher drop_all_mcast = 0; 2352adfc5217SJeff Kirsher accp_all_mcast = 1; 2353adfc5217SJeff Kirsher } 2354adfc5217SJeff Kirsher if (test_bit(BNX2X_ACCEPT_BROADCAST, &p->rx_accept_flags)) 2355adfc5217SJeff Kirsher /* accept (all) bcast */ 2356adfc5217SJeff Kirsher accp_all_bcast = 1; 2357adfc5217SJeff Kirsher if (test_bit(BNX2X_ACCEPT_UNMATCHED, &p->rx_accept_flags)) 2358adfc5217SJeff Kirsher /* accept unmatched unicasts */ 2359adfc5217SJeff Kirsher unmatched_unicast = 1; 2360adfc5217SJeff Kirsher 2361adfc5217SJeff Kirsher mac_filters->ucast_drop_all = drop_all_ucast ? 2362adfc5217SJeff Kirsher mac_filters->ucast_drop_all | mask : 2363adfc5217SJeff Kirsher mac_filters->ucast_drop_all & ~mask; 2364adfc5217SJeff Kirsher 2365adfc5217SJeff Kirsher mac_filters->mcast_drop_all = drop_all_mcast ? 2366adfc5217SJeff Kirsher mac_filters->mcast_drop_all | mask : 2367adfc5217SJeff Kirsher mac_filters->mcast_drop_all & ~mask; 2368adfc5217SJeff Kirsher 2369adfc5217SJeff Kirsher mac_filters->ucast_accept_all = accp_all_ucast ? 2370adfc5217SJeff Kirsher mac_filters->ucast_accept_all | mask : 2371adfc5217SJeff Kirsher mac_filters->ucast_accept_all & ~mask; 2372adfc5217SJeff Kirsher 2373adfc5217SJeff Kirsher mac_filters->mcast_accept_all = accp_all_mcast ? 2374adfc5217SJeff Kirsher mac_filters->mcast_accept_all | mask : 2375adfc5217SJeff Kirsher mac_filters->mcast_accept_all & ~mask; 2376adfc5217SJeff Kirsher 2377adfc5217SJeff Kirsher mac_filters->bcast_accept_all = accp_all_bcast ? 2378adfc5217SJeff Kirsher mac_filters->bcast_accept_all | mask : 2379adfc5217SJeff Kirsher mac_filters->bcast_accept_all & ~mask; 2380adfc5217SJeff Kirsher 2381adfc5217SJeff Kirsher mac_filters->unmatched_unicast = unmatched_unicast ? 2382adfc5217SJeff Kirsher mac_filters->unmatched_unicast | mask : 2383adfc5217SJeff Kirsher mac_filters->unmatched_unicast & ~mask; 2384adfc5217SJeff Kirsher 2385adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "drop_ucast 0x%x\ndrop_mcast 0x%x\n accp_ucast 0x%x\n" 2386adfc5217SJeff Kirsher "accp_mcast 0x%x\naccp_bcast 0x%x\n", 238751c1a580SMerav Sicron mac_filters->ucast_drop_all, mac_filters->mcast_drop_all, 238851c1a580SMerav Sicron mac_filters->ucast_accept_all, mac_filters->mcast_accept_all, 2389adfc5217SJeff Kirsher mac_filters->bcast_accept_all); 2390adfc5217SJeff Kirsher 2391adfc5217SJeff Kirsher /* write the MAC filter structure*/ 2392adfc5217SJeff Kirsher __storm_memset_mac_filters(bp, mac_filters, p->func_id); 2393adfc5217SJeff Kirsher 2394adfc5217SJeff Kirsher /* The operation is completed */ 2395adfc5217SJeff Kirsher clear_bit(p->state, p->pstate); 2396adfc5217SJeff Kirsher smp_mb__after_clear_bit(); 2397adfc5217SJeff Kirsher 2398adfc5217SJeff Kirsher return 0; 2399adfc5217SJeff Kirsher } 2400adfc5217SJeff Kirsher 2401adfc5217SJeff Kirsher /* Setup ramrod data */ 2402adfc5217SJeff Kirsher static inline void bnx2x_rx_mode_set_rdata_hdr_e2(u32 cid, 2403adfc5217SJeff Kirsher struct eth_classify_header *hdr, 2404adfc5217SJeff Kirsher u8 rule_cnt) 2405adfc5217SJeff Kirsher { 240686564c3fSYuval Mintz hdr->echo = cpu_to_le32(cid); 2407adfc5217SJeff Kirsher hdr->rule_cnt = rule_cnt; 2408adfc5217SJeff Kirsher } 2409adfc5217SJeff Kirsher 2410adfc5217SJeff Kirsher static inline void bnx2x_rx_mode_set_cmd_state_e2(struct bnx2x *bp, 2411924d75abSYuval Mintz unsigned long *accept_flags, 2412adfc5217SJeff Kirsher struct eth_filter_rules_cmd *cmd, 2413adfc5217SJeff Kirsher bool clear_accept_all) 2414adfc5217SJeff Kirsher { 2415adfc5217SJeff Kirsher u16 state; 2416adfc5217SJeff Kirsher 2417adfc5217SJeff Kirsher /* start with 'drop-all' */ 2418adfc5217SJeff Kirsher state = ETH_FILTER_RULES_CMD_UCAST_DROP_ALL | 2419adfc5217SJeff Kirsher ETH_FILTER_RULES_CMD_MCAST_DROP_ALL; 2420adfc5217SJeff Kirsher 2421924d75abSYuval Mintz if (test_bit(BNX2X_ACCEPT_UNICAST, accept_flags)) 2422adfc5217SJeff Kirsher state &= ~ETH_FILTER_RULES_CMD_UCAST_DROP_ALL; 2423adfc5217SJeff Kirsher 2424924d75abSYuval Mintz if (test_bit(BNX2X_ACCEPT_MULTICAST, accept_flags)) 2425adfc5217SJeff Kirsher state &= ~ETH_FILTER_RULES_CMD_MCAST_DROP_ALL; 2426adfc5217SJeff Kirsher 2427924d75abSYuval Mintz if (test_bit(BNX2X_ACCEPT_ALL_UNICAST, accept_flags)) { 2428adfc5217SJeff Kirsher state &= ~ETH_FILTER_RULES_CMD_UCAST_DROP_ALL; 2429adfc5217SJeff Kirsher state |= ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL; 2430adfc5217SJeff Kirsher } 2431adfc5217SJeff Kirsher 2432924d75abSYuval Mintz if (test_bit(BNX2X_ACCEPT_ALL_MULTICAST, accept_flags)) { 2433adfc5217SJeff Kirsher state |= ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL; 2434adfc5217SJeff Kirsher state &= ~ETH_FILTER_RULES_CMD_MCAST_DROP_ALL; 2435adfc5217SJeff Kirsher } 2436924d75abSYuval Mintz 2437924d75abSYuval Mintz if (test_bit(BNX2X_ACCEPT_BROADCAST, accept_flags)) 2438adfc5217SJeff Kirsher state |= ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL; 2439adfc5217SJeff Kirsher 2440924d75abSYuval Mintz if (test_bit(BNX2X_ACCEPT_UNMATCHED, accept_flags)) { 2441adfc5217SJeff Kirsher state &= ~ETH_FILTER_RULES_CMD_UCAST_DROP_ALL; 2442adfc5217SJeff Kirsher state |= ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED; 2443adfc5217SJeff Kirsher } 2444924d75abSYuval Mintz 2445924d75abSYuval Mintz if (test_bit(BNX2X_ACCEPT_ANY_VLAN, accept_flags)) 2446adfc5217SJeff Kirsher state |= ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN; 2447adfc5217SJeff Kirsher 2448adfc5217SJeff Kirsher /* Clear ACCEPT_ALL_XXX flags for FCoE L2 Queue */ 2449adfc5217SJeff Kirsher if (clear_accept_all) { 2450adfc5217SJeff Kirsher state &= ~ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL; 2451adfc5217SJeff Kirsher state &= ~ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL; 2452adfc5217SJeff Kirsher state &= ~ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL; 2453adfc5217SJeff Kirsher state &= ~ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED; 2454adfc5217SJeff Kirsher } 2455adfc5217SJeff Kirsher 2456adfc5217SJeff Kirsher cmd->state = cpu_to_le16(state); 2457adfc5217SJeff Kirsher } 2458adfc5217SJeff Kirsher 2459adfc5217SJeff Kirsher static int bnx2x_set_rx_mode_e2(struct bnx2x *bp, 2460adfc5217SJeff Kirsher struct bnx2x_rx_mode_ramrod_params *p) 2461adfc5217SJeff Kirsher { 2462adfc5217SJeff Kirsher struct eth_filter_rules_ramrod_data *data = p->rdata; 2463adfc5217SJeff Kirsher int rc; 2464adfc5217SJeff Kirsher u8 rule_idx = 0; 2465adfc5217SJeff Kirsher 2466adfc5217SJeff Kirsher /* Reset the ramrod data buffer */ 2467adfc5217SJeff Kirsher memset(data, 0, sizeof(*data)); 2468adfc5217SJeff Kirsher 2469adfc5217SJeff Kirsher /* Setup ramrod data */ 2470adfc5217SJeff Kirsher 2471adfc5217SJeff Kirsher /* Tx (internal switching) */ 2472adfc5217SJeff Kirsher if (test_bit(RAMROD_TX, &p->ramrod_flags)) { 2473adfc5217SJeff Kirsher data->rules[rule_idx].client_id = p->cl_id; 2474adfc5217SJeff Kirsher data->rules[rule_idx].func_id = p->func_id; 2475adfc5217SJeff Kirsher 2476adfc5217SJeff Kirsher data->rules[rule_idx].cmd_general_data = 2477adfc5217SJeff Kirsher ETH_FILTER_RULES_CMD_TX_CMD; 2478adfc5217SJeff Kirsher 2479924d75abSYuval Mintz bnx2x_rx_mode_set_cmd_state_e2(bp, &p->tx_accept_flags, 2480924d75abSYuval Mintz &(data->rules[rule_idx++]), 2481924d75abSYuval Mintz false); 2482adfc5217SJeff Kirsher } 2483adfc5217SJeff Kirsher 2484adfc5217SJeff Kirsher /* Rx */ 2485adfc5217SJeff Kirsher if (test_bit(RAMROD_RX, &p->ramrod_flags)) { 2486adfc5217SJeff Kirsher data->rules[rule_idx].client_id = p->cl_id; 2487adfc5217SJeff Kirsher data->rules[rule_idx].func_id = p->func_id; 2488adfc5217SJeff Kirsher 2489adfc5217SJeff Kirsher data->rules[rule_idx].cmd_general_data = 2490adfc5217SJeff Kirsher ETH_FILTER_RULES_CMD_RX_CMD; 2491adfc5217SJeff Kirsher 2492924d75abSYuval Mintz bnx2x_rx_mode_set_cmd_state_e2(bp, &p->rx_accept_flags, 2493924d75abSYuval Mintz &(data->rules[rule_idx++]), 2494924d75abSYuval Mintz false); 2495adfc5217SJeff Kirsher } 2496adfc5217SJeff Kirsher 249716a5fd92SYuval Mintz /* If FCoE Queue configuration has been requested configure the Rx and 2498adfc5217SJeff Kirsher * internal switching modes for this queue in separate rules. 2499adfc5217SJeff Kirsher * 2500adfc5217SJeff Kirsher * FCoE queue shell never be set to ACCEPT_ALL packets of any sort: 2501adfc5217SJeff Kirsher * MCAST_ALL, UCAST_ALL, BCAST_ALL and UNMATCHED. 2502adfc5217SJeff Kirsher */ 2503adfc5217SJeff Kirsher if (test_bit(BNX2X_RX_MODE_FCOE_ETH, &p->rx_mode_flags)) { 2504adfc5217SJeff Kirsher /* Tx (internal switching) */ 2505adfc5217SJeff Kirsher if (test_bit(RAMROD_TX, &p->ramrod_flags)) { 2506adfc5217SJeff Kirsher data->rules[rule_idx].client_id = bnx2x_fcoe(bp, cl_id); 2507adfc5217SJeff Kirsher data->rules[rule_idx].func_id = p->func_id; 2508adfc5217SJeff Kirsher 2509adfc5217SJeff Kirsher data->rules[rule_idx].cmd_general_data = 2510adfc5217SJeff Kirsher ETH_FILTER_RULES_CMD_TX_CMD; 2511adfc5217SJeff Kirsher 2512924d75abSYuval Mintz bnx2x_rx_mode_set_cmd_state_e2(bp, &p->tx_accept_flags, 2513924d75abSYuval Mintz &(data->rules[rule_idx]), 2514adfc5217SJeff Kirsher true); 2515924d75abSYuval Mintz rule_idx++; 2516adfc5217SJeff Kirsher } 2517adfc5217SJeff Kirsher 2518adfc5217SJeff Kirsher /* Rx */ 2519adfc5217SJeff Kirsher if (test_bit(RAMROD_RX, &p->ramrod_flags)) { 2520adfc5217SJeff Kirsher data->rules[rule_idx].client_id = bnx2x_fcoe(bp, cl_id); 2521adfc5217SJeff Kirsher data->rules[rule_idx].func_id = p->func_id; 2522adfc5217SJeff Kirsher 2523adfc5217SJeff Kirsher data->rules[rule_idx].cmd_general_data = 2524adfc5217SJeff Kirsher ETH_FILTER_RULES_CMD_RX_CMD; 2525adfc5217SJeff Kirsher 2526924d75abSYuval Mintz bnx2x_rx_mode_set_cmd_state_e2(bp, &p->rx_accept_flags, 2527924d75abSYuval Mintz &(data->rules[rule_idx]), 2528adfc5217SJeff Kirsher true); 2529924d75abSYuval Mintz rule_idx++; 2530adfc5217SJeff Kirsher } 2531adfc5217SJeff Kirsher } 2532adfc5217SJeff Kirsher 253316a5fd92SYuval Mintz /* Set the ramrod header (most importantly - number of rules to 2534adfc5217SJeff Kirsher * configure). 2535adfc5217SJeff Kirsher */ 2536adfc5217SJeff Kirsher bnx2x_rx_mode_set_rdata_hdr_e2(p->cid, &data->header, rule_idx); 2537adfc5217SJeff Kirsher 253851c1a580SMerav Sicron DP(BNX2X_MSG_SP, "About to configure %d rules, rx_accept_flags 0x%lx, tx_accept_flags 0x%lx\n", 2539adfc5217SJeff Kirsher data->header.rule_cnt, p->rx_accept_flags, 2540adfc5217SJeff Kirsher p->tx_accept_flags); 2541adfc5217SJeff Kirsher 254216a5fd92SYuval Mintz /* No need for an explicit memory barrier here as long we would 2543adfc5217SJeff Kirsher * need to ensure the ordering of writing to the SPQ element 2544adfc5217SJeff Kirsher * and updating of the SPQ producer which involves a memory 2545adfc5217SJeff Kirsher * read and we will have to put a full memory barrier there 2546adfc5217SJeff Kirsher * (inside bnx2x_sp_post()). 2547adfc5217SJeff Kirsher */ 2548adfc5217SJeff Kirsher 2549adfc5217SJeff Kirsher /* Send a ramrod */ 2550adfc5217SJeff Kirsher rc = bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_FILTER_RULES, p->cid, 2551adfc5217SJeff Kirsher U64_HI(p->rdata_mapping), 2552adfc5217SJeff Kirsher U64_LO(p->rdata_mapping), 2553adfc5217SJeff Kirsher ETH_CONNECTION_TYPE); 2554adfc5217SJeff Kirsher if (rc) 2555adfc5217SJeff Kirsher return rc; 2556adfc5217SJeff Kirsher 2557adfc5217SJeff Kirsher /* Ramrod completion is pending */ 2558adfc5217SJeff Kirsher return 1; 2559adfc5217SJeff Kirsher } 2560adfc5217SJeff Kirsher 2561adfc5217SJeff Kirsher static int bnx2x_wait_rx_mode_comp_e2(struct bnx2x *bp, 2562adfc5217SJeff Kirsher struct bnx2x_rx_mode_ramrod_params *p) 2563adfc5217SJeff Kirsher { 2564adfc5217SJeff Kirsher return bnx2x_state_wait(bp, p->state, p->pstate); 2565adfc5217SJeff Kirsher } 2566adfc5217SJeff Kirsher 2567adfc5217SJeff Kirsher static int bnx2x_empty_rx_mode_wait(struct bnx2x *bp, 2568adfc5217SJeff Kirsher struct bnx2x_rx_mode_ramrod_params *p) 2569adfc5217SJeff Kirsher { 2570adfc5217SJeff Kirsher /* Do nothing */ 2571adfc5217SJeff Kirsher return 0; 2572adfc5217SJeff Kirsher } 2573adfc5217SJeff Kirsher 2574adfc5217SJeff Kirsher int bnx2x_config_rx_mode(struct bnx2x *bp, 2575adfc5217SJeff Kirsher struct bnx2x_rx_mode_ramrod_params *p) 2576adfc5217SJeff Kirsher { 2577adfc5217SJeff Kirsher int rc; 2578adfc5217SJeff Kirsher 2579adfc5217SJeff Kirsher /* Configure the new classification in the chip */ 2580adfc5217SJeff Kirsher rc = p->rx_mode_obj->config_rx_mode(bp, p); 2581adfc5217SJeff Kirsher if (rc < 0) 2582adfc5217SJeff Kirsher return rc; 2583adfc5217SJeff Kirsher 2584adfc5217SJeff Kirsher /* Wait for a ramrod completion if was requested */ 2585adfc5217SJeff Kirsher if (test_bit(RAMROD_COMP_WAIT, &p->ramrod_flags)) { 2586adfc5217SJeff Kirsher rc = p->rx_mode_obj->wait_comp(bp, p); 2587adfc5217SJeff Kirsher if (rc) 2588adfc5217SJeff Kirsher return rc; 2589adfc5217SJeff Kirsher } 2590adfc5217SJeff Kirsher 2591adfc5217SJeff Kirsher return rc; 2592adfc5217SJeff Kirsher } 2593adfc5217SJeff Kirsher 2594adfc5217SJeff Kirsher void bnx2x_init_rx_mode_obj(struct bnx2x *bp, 2595adfc5217SJeff Kirsher struct bnx2x_rx_mode_obj *o) 2596adfc5217SJeff Kirsher { 2597adfc5217SJeff Kirsher if (CHIP_IS_E1x(bp)) { 2598adfc5217SJeff Kirsher o->wait_comp = bnx2x_empty_rx_mode_wait; 2599adfc5217SJeff Kirsher o->config_rx_mode = bnx2x_set_rx_mode_e1x; 2600adfc5217SJeff Kirsher } else { 2601adfc5217SJeff Kirsher o->wait_comp = bnx2x_wait_rx_mode_comp_e2; 2602adfc5217SJeff Kirsher o->config_rx_mode = bnx2x_set_rx_mode_e2; 2603adfc5217SJeff Kirsher } 2604adfc5217SJeff Kirsher } 2605adfc5217SJeff Kirsher 2606adfc5217SJeff Kirsher /********************* Multicast verbs: SET, CLEAR ****************************/ 2607adfc5217SJeff Kirsher static inline u8 bnx2x_mcast_bin_from_mac(u8 *mac) 2608adfc5217SJeff Kirsher { 2609adfc5217SJeff Kirsher return (crc32c_le(0, mac, ETH_ALEN) >> 24) & 0xff; 2610adfc5217SJeff Kirsher } 2611adfc5217SJeff Kirsher 2612adfc5217SJeff Kirsher struct bnx2x_mcast_mac_elem { 2613adfc5217SJeff Kirsher struct list_head link; 2614adfc5217SJeff Kirsher u8 mac[ETH_ALEN]; 2615adfc5217SJeff Kirsher u8 pad[2]; /* For a natural alignment of the following buffer */ 2616adfc5217SJeff Kirsher }; 2617adfc5217SJeff Kirsher 2618adfc5217SJeff Kirsher struct bnx2x_pending_mcast_cmd { 2619adfc5217SJeff Kirsher struct list_head link; 2620adfc5217SJeff Kirsher int type; /* BNX2X_MCAST_CMD_X */ 2621adfc5217SJeff Kirsher union { 2622adfc5217SJeff Kirsher struct list_head macs_head; 2623adfc5217SJeff Kirsher u32 macs_num; /* Needed for DEL command */ 2624adfc5217SJeff Kirsher int next_bin; /* Needed for RESTORE flow with aprox match */ 2625adfc5217SJeff Kirsher } data; 2626adfc5217SJeff Kirsher 2627adfc5217SJeff Kirsher bool done; /* set to true, when the command has been handled, 2628adfc5217SJeff Kirsher * practically used in 57712 handling only, where one pending 2629adfc5217SJeff Kirsher * command may be handled in a few operations. As long as for 2630adfc5217SJeff Kirsher * other chips every operation handling is completed in a 2631adfc5217SJeff Kirsher * single ramrod, there is no need to utilize this field. 2632adfc5217SJeff Kirsher */ 2633adfc5217SJeff Kirsher }; 2634adfc5217SJeff Kirsher 2635adfc5217SJeff Kirsher static int bnx2x_mcast_wait(struct bnx2x *bp, 2636adfc5217SJeff Kirsher struct bnx2x_mcast_obj *o) 2637adfc5217SJeff Kirsher { 2638adfc5217SJeff Kirsher if (bnx2x_state_wait(bp, o->sched_state, o->raw.pstate) || 2639adfc5217SJeff Kirsher o->raw.wait_comp(bp, &o->raw)) 2640adfc5217SJeff Kirsher return -EBUSY; 2641adfc5217SJeff Kirsher 2642adfc5217SJeff Kirsher return 0; 2643adfc5217SJeff Kirsher } 2644adfc5217SJeff Kirsher 2645adfc5217SJeff Kirsher static int bnx2x_mcast_enqueue_cmd(struct bnx2x *bp, 2646adfc5217SJeff Kirsher struct bnx2x_mcast_obj *o, 2647adfc5217SJeff Kirsher struct bnx2x_mcast_ramrod_params *p, 264886564c3fSYuval Mintz enum bnx2x_mcast_cmd cmd) 2649adfc5217SJeff Kirsher { 2650adfc5217SJeff Kirsher int total_sz; 2651adfc5217SJeff Kirsher struct bnx2x_pending_mcast_cmd *new_cmd; 2652adfc5217SJeff Kirsher struct bnx2x_mcast_mac_elem *cur_mac = NULL; 2653adfc5217SJeff Kirsher struct bnx2x_mcast_list_elem *pos; 2654adfc5217SJeff Kirsher int macs_list_len = ((cmd == BNX2X_MCAST_CMD_ADD) ? 2655adfc5217SJeff Kirsher p->mcast_list_len : 0); 2656adfc5217SJeff Kirsher 2657adfc5217SJeff Kirsher /* If the command is empty ("handle pending commands only"), break */ 2658adfc5217SJeff Kirsher if (!p->mcast_list_len) 2659adfc5217SJeff Kirsher return 0; 2660adfc5217SJeff Kirsher 2661adfc5217SJeff Kirsher total_sz = sizeof(*new_cmd) + 2662adfc5217SJeff Kirsher macs_list_len * sizeof(struct bnx2x_mcast_mac_elem); 2663adfc5217SJeff Kirsher 2664adfc5217SJeff Kirsher /* Add mcast is called under spin_lock, thus calling with GFP_ATOMIC */ 2665adfc5217SJeff Kirsher new_cmd = kzalloc(total_sz, GFP_ATOMIC); 2666adfc5217SJeff Kirsher 2667adfc5217SJeff Kirsher if (!new_cmd) 2668adfc5217SJeff Kirsher return -ENOMEM; 2669adfc5217SJeff Kirsher 267051c1a580SMerav Sicron DP(BNX2X_MSG_SP, "About to enqueue a new %d command. macs_list_len=%d\n", 267151c1a580SMerav Sicron cmd, macs_list_len); 2672adfc5217SJeff Kirsher 2673adfc5217SJeff Kirsher INIT_LIST_HEAD(&new_cmd->data.macs_head); 2674adfc5217SJeff Kirsher 2675adfc5217SJeff Kirsher new_cmd->type = cmd; 2676adfc5217SJeff Kirsher new_cmd->done = false; 2677adfc5217SJeff Kirsher 2678adfc5217SJeff Kirsher switch (cmd) { 2679adfc5217SJeff Kirsher case BNX2X_MCAST_CMD_ADD: 2680adfc5217SJeff Kirsher cur_mac = (struct bnx2x_mcast_mac_elem *) 2681adfc5217SJeff Kirsher ((u8 *)new_cmd + sizeof(*new_cmd)); 2682adfc5217SJeff Kirsher 268316a5fd92SYuval Mintz /* Push the MACs of the current command into the pending command 2684adfc5217SJeff Kirsher * MACs list: FIFO 2685adfc5217SJeff Kirsher */ 2686adfc5217SJeff Kirsher list_for_each_entry(pos, &p->mcast_list, link) { 2687adfc5217SJeff Kirsher memcpy(cur_mac->mac, pos->mac, ETH_ALEN); 2688adfc5217SJeff Kirsher list_add_tail(&cur_mac->link, &new_cmd->data.macs_head); 2689adfc5217SJeff Kirsher cur_mac++; 2690adfc5217SJeff Kirsher } 2691adfc5217SJeff Kirsher 2692adfc5217SJeff Kirsher break; 2693adfc5217SJeff Kirsher 2694adfc5217SJeff Kirsher case BNX2X_MCAST_CMD_DEL: 2695adfc5217SJeff Kirsher new_cmd->data.macs_num = p->mcast_list_len; 2696adfc5217SJeff Kirsher break; 2697adfc5217SJeff Kirsher 2698adfc5217SJeff Kirsher case BNX2X_MCAST_CMD_RESTORE: 2699adfc5217SJeff Kirsher new_cmd->data.next_bin = 0; 2700adfc5217SJeff Kirsher break; 2701adfc5217SJeff Kirsher 2702adfc5217SJeff Kirsher default: 27038b6d5c09SJesper Juhl kfree(new_cmd); 2704adfc5217SJeff Kirsher BNX2X_ERR("Unknown command: %d\n", cmd); 2705adfc5217SJeff Kirsher return -EINVAL; 2706adfc5217SJeff Kirsher } 2707adfc5217SJeff Kirsher 2708adfc5217SJeff Kirsher /* Push the new pending command to the tail of the pending list: FIFO */ 2709adfc5217SJeff Kirsher list_add_tail(&new_cmd->link, &o->pending_cmds_head); 2710adfc5217SJeff Kirsher 2711adfc5217SJeff Kirsher o->set_sched(o); 2712adfc5217SJeff Kirsher 2713adfc5217SJeff Kirsher return 1; 2714adfc5217SJeff Kirsher } 2715adfc5217SJeff Kirsher 2716adfc5217SJeff Kirsher /** 2717adfc5217SJeff Kirsher * bnx2x_mcast_get_next_bin - get the next set bin (index) 2718adfc5217SJeff Kirsher * 2719adfc5217SJeff Kirsher * @o: 2720adfc5217SJeff Kirsher * @last: index to start looking from (including) 2721adfc5217SJeff Kirsher * 2722adfc5217SJeff Kirsher * returns the next found (set) bin or a negative value if none is found. 2723adfc5217SJeff Kirsher */ 2724adfc5217SJeff Kirsher static inline int bnx2x_mcast_get_next_bin(struct bnx2x_mcast_obj *o, int last) 2725adfc5217SJeff Kirsher { 2726adfc5217SJeff Kirsher int i, j, inner_start = last % BIT_VEC64_ELEM_SZ; 2727adfc5217SJeff Kirsher 2728adfc5217SJeff Kirsher for (i = last / BIT_VEC64_ELEM_SZ; i < BNX2X_MCAST_VEC_SZ; i++) { 2729adfc5217SJeff Kirsher if (o->registry.aprox_match.vec[i]) 2730adfc5217SJeff Kirsher for (j = inner_start; j < BIT_VEC64_ELEM_SZ; j++) { 2731adfc5217SJeff Kirsher int cur_bit = j + BIT_VEC64_ELEM_SZ * i; 2732adfc5217SJeff Kirsher if (BIT_VEC64_TEST_BIT(o->registry.aprox_match. 2733adfc5217SJeff Kirsher vec, cur_bit)) { 2734adfc5217SJeff Kirsher return cur_bit; 2735adfc5217SJeff Kirsher } 2736adfc5217SJeff Kirsher } 2737adfc5217SJeff Kirsher inner_start = 0; 2738adfc5217SJeff Kirsher } 2739adfc5217SJeff Kirsher 2740adfc5217SJeff Kirsher /* None found */ 2741adfc5217SJeff Kirsher return -1; 2742adfc5217SJeff Kirsher } 2743adfc5217SJeff Kirsher 2744adfc5217SJeff Kirsher /** 2745adfc5217SJeff Kirsher * bnx2x_mcast_clear_first_bin - find the first set bin and clear it 2746adfc5217SJeff Kirsher * 2747adfc5217SJeff Kirsher * @o: 2748adfc5217SJeff Kirsher * 2749adfc5217SJeff Kirsher * returns the index of the found bin or -1 if none is found 2750adfc5217SJeff Kirsher */ 2751adfc5217SJeff Kirsher static inline int bnx2x_mcast_clear_first_bin(struct bnx2x_mcast_obj *o) 2752adfc5217SJeff Kirsher { 2753adfc5217SJeff Kirsher int cur_bit = bnx2x_mcast_get_next_bin(o, 0); 2754adfc5217SJeff Kirsher 2755adfc5217SJeff Kirsher if (cur_bit >= 0) 2756adfc5217SJeff Kirsher BIT_VEC64_CLEAR_BIT(o->registry.aprox_match.vec, cur_bit); 2757adfc5217SJeff Kirsher 2758adfc5217SJeff Kirsher return cur_bit; 2759adfc5217SJeff Kirsher } 2760adfc5217SJeff Kirsher 2761adfc5217SJeff Kirsher static inline u8 bnx2x_mcast_get_rx_tx_flag(struct bnx2x_mcast_obj *o) 2762adfc5217SJeff Kirsher { 2763adfc5217SJeff Kirsher struct bnx2x_raw_obj *raw = &o->raw; 2764adfc5217SJeff Kirsher u8 rx_tx_flag = 0; 2765adfc5217SJeff Kirsher 2766adfc5217SJeff Kirsher if ((raw->obj_type == BNX2X_OBJ_TYPE_TX) || 2767adfc5217SJeff Kirsher (raw->obj_type == BNX2X_OBJ_TYPE_RX_TX)) 2768adfc5217SJeff Kirsher rx_tx_flag |= ETH_MULTICAST_RULES_CMD_TX_CMD; 2769adfc5217SJeff Kirsher 2770adfc5217SJeff Kirsher if ((raw->obj_type == BNX2X_OBJ_TYPE_RX) || 2771adfc5217SJeff Kirsher (raw->obj_type == BNX2X_OBJ_TYPE_RX_TX)) 2772adfc5217SJeff Kirsher rx_tx_flag |= ETH_MULTICAST_RULES_CMD_RX_CMD; 2773adfc5217SJeff Kirsher 2774adfc5217SJeff Kirsher return rx_tx_flag; 2775adfc5217SJeff Kirsher } 2776adfc5217SJeff Kirsher 2777adfc5217SJeff Kirsher static void bnx2x_mcast_set_one_rule_e2(struct bnx2x *bp, 2778adfc5217SJeff Kirsher struct bnx2x_mcast_obj *o, int idx, 2779adfc5217SJeff Kirsher union bnx2x_mcast_config_data *cfg_data, 278086564c3fSYuval Mintz enum bnx2x_mcast_cmd cmd) 2781adfc5217SJeff Kirsher { 2782adfc5217SJeff Kirsher struct bnx2x_raw_obj *r = &o->raw; 2783adfc5217SJeff Kirsher struct eth_multicast_rules_ramrod_data *data = 2784adfc5217SJeff Kirsher (struct eth_multicast_rules_ramrod_data *)(r->rdata); 2785adfc5217SJeff Kirsher u8 func_id = r->func_id; 2786adfc5217SJeff Kirsher u8 rx_tx_add_flag = bnx2x_mcast_get_rx_tx_flag(o); 2787adfc5217SJeff Kirsher int bin; 2788adfc5217SJeff Kirsher 2789adfc5217SJeff Kirsher if ((cmd == BNX2X_MCAST_CMD_ADD) || (cmd == BNX2X_MCAST_CMD_RESTORE)) 2790adfc5217SJeff Kirsher rx_tx_add_flag |= ETH_MULTICAST_RULES_CMD_IS_ADD; 2791adfc5217SJeff Kirsher 2792adfc5217SJeff Kirsher data->rules[idx].cmd_general_data |= rx_tx_add_flag; 2793adfc5217SJeff Kirsher 2794adfc5217SJeff Kirsher /* Get a bin and update a bins' vector */ 2795adfc5217SJeff Kirsher switch (cmd) { 2796adfc5217SJeff Kirsher case BNX2X_MCAST_CMD_ADD: 2797adfc5217SJeff Kirsher bin = bnx2x_mcast_bin_from_mac(cfg_data->mac); 2798adfc5217SJeff Kirsher BIT_VEC64_SET_BIT(o->registry.aprox_match.vec, bin); 2799adfc5217SJeff Kirsher break; 2800adfc5217SJeff Kirsher 2801adfc5217SJeff Kirsher case BNX2X_MCAST_CMD_DEL: 2802adfc5217SJeff Kirsher /* If there were no more bins to clear 2803adfc5217SJeff Kirsher * (bnx2x_mcast_clear_first_bin() returns -1) then we would 2804adfc5217SJeff Kirsher * clear any (0xff) bin. 2805adfc5217SJeff Kirsher * See bnx2x_mcast_validate_e2() for explanation when it may 2806adfc5217SJeff Kirsher * happen. 2807adfc5217SJeff Kirsher */ 2808adfc5217SJeff Kirsher bin = bnx2x_mcast_clear_first_bin(o); 2809adfc5217SJeff Kirsher break; 2810adfc5217SJeff Kirsher 2811adfc5217SJeff Kirsher case BNX2X_MCAST_CMD_RESTORE: 2812adfc5217SJeff Kirsher bin = cfg_data->bin; 2813adfc5217SJeff Kirsher break; 2814adfc5217SJeff Kirsher 2815adfc5217SJeff Kirsher default: 2816adfc5217SJeff Kirsher BNX2X_ERR("Unknown command: %d\n", cmd); 2817adfc5217SJeff Kirsher return; 2818adfc5217SJeff Kirsher } 2819adfc5217SJeff Kirsher 2820adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "%s bin %d\n", 2821adfc5217SJeff Kirsher ((rx_tx_add_flag & ETH_MULTICAST_RULES_CMD_IS_ADD) ? 2822adfc5217SJeff Kirsher "Setting" : "Clearing"), bin); 2823adfc5217SJeff Kirsher 2824adfc5217SJeff Kirsher data->rules[idx].bin_id = (u8)bin; 2825adfc5217SJeff Kirsher data->rules[idx].func_id = func_id; 2826adfc5217SJeff Kirsher data->rules[idx].engine_id = o->engine_id; 2827adfc5217SJeff Kirsher } 2828adfc5217SJeff Kirsher 2829adfc5217SJeff Kirsher /** 2830adfc5217SJeff Kirsher * bnx2x_mcast_handle_restore_cmd_e2 - restore configuration from the registry 2831adfc5217SJeff Kirsher * 2832adfc5217SJeff Kirsher * @bp: device handle 2833adfc5217SJeff Kirsher * @o: 2834adfc5217SJeff Kirsher * @start_bin: index in the registry to start from (including) 2835adfc5217SJeff Kirsher * @rdata_idx: index in the ramrod data to start from 2836adfc5217SJeff Kirsher * 2837adfc5217SJeff Kirsher * returns last handled bin index or -1 if all bins have been handled 2838adfc5217SJeff Kirsher */ 2839adfc5217SJeff Kirsher static inline int bnx2x_mcast_handle_restore_cmd_e2( 2840adfc5217SJeff Kirsher struct bnx2x *bp, struct bnx2x_mcast_obj *o , int start_bin, 2841adfc5217SJeff Kirsher int *rdata_idx) 2842adfc5217SJeff Kirsher { 2843adfc5217SJeff Kirsher int cur_bin, cnt = *rdata_idx; 284486564c3fSYuval Mintz union bnx2x_mcast_config_data cfg_data = {NULL}; 2845adfc5217SJeff Kirsher 2846adfc5217SJeff Kirsher /* go through the registry and configure the bins from it */ 2847adfc5217SJeff Kirsher for (cur_bin = bnx2x_mcast_get_next_bin(o, start_bin); cur_bin >= 0; 2848adfc5217SJeff Kirsher cur_bin = bnx2x_mcast_get_next_bin(o, cur_bin + 1)) { 2849adfc5217SJeff Kirsher 2850adfc5217SJeff Kirsher cfg_data.bin = (u8)cur_bin; 2851adfc5217SJeff Kirsher o->set_one_rule(bp, o, cnt, &cfg_data, 2852adfc5217SJeff Kirsher BNX2X_MCAST_CMD_RESTORE); 2853adfc5217SJeff Kirsher 2854adfc5217SJeff Kirsher cnt++; 2855adfc5217SJeff Kirsher 2856adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "About to configure a bin %d\n", cur_bin); 2857adfc5217SJeff Kirsher 2858adfc5217SJeff Kirsher /* Break if we reached the maximum number 2859adfc5217SJeff Kirsher * of rules. 2860adfc5217SJeff Kirsher */ 2861adfc5217SJeff Kirsher if (cnt >= o->max_cmd_len) 2862adfc5217SJeff Kirsher break; 2863adfc5217SJeff Kirsher } 2864adfc5217SJeff Kirsher 2865adfc5217SJeff Kirsher *rdata_idx = cnt; 2866adfc5217SJeff Kirsher 2867adfc5217SJeff Kirsher return cur_bin; 2868adfc5217SJeff Kirsher } 2869adfc5217SJeff Kirsher 2870adfc5217SJeff Kirsher static inline void bnx2x_mcast_hdl_pending_add_e2(struct bnx2x *bp, 2871adfc5217SJeff Kirsher struct bnx2x_mcast_obj *o, struct bnx2x_pending_mcast_cmd *cmd_pos, 2872adfc5217SJeff Kirsher int *line_idx) 2873adfc5217SJeff Kirsher { 2874adfc5217SJeff Kirsher struct bnx2x_mcast_mac_elem *pmac_pos, *pmac_pos_n; 2875adfc5217SJeff Kirsher int cnt = *line_idx; 287686564c3fSYuval Mintz union bnx2x_mcast_config_data cfg_data = {NULL}; 2877adfc5217SJeff Kirsher 2878adfc5217SJeff Kirsher list_for_each_entry_safe(pmac_pos, pmac_pos_n, &cmd_pos->data.macs_head, 2879adfc5217SJeff Kirsher link) { 2880adfc5217SJeff Kirsher 2881adfc5217SJeff Kirsher cfg_data.mac = &pmac_pos->mac[0]; 2882adfc5217SJeff Kirsher o->set_one_rule(bp, o, cnt, &cfg_data, cmd_pos->type); 2883adfc5217SJeff Kirsher 2884adfc5217SJeff Kirsher cnt++; 2885adfc5217SJeff Kirsher 28860f9dad10SJoe Perches DP(BNX2X_MSG_SP, "About to configure %pM mcast MAC\n", 28870f9dad10SJoe Perches pmac_pos->mac); 2888adfc5217SJeff Kirsher 2889adfc5217SJeff Kirsher list_del(&pmac_pos->link); 2890adfc5217SJeff Kirsher 2891adfc5217SJeff Kirsher /* Break if we reached the maximum number 2892adfc5217SJeff Kirsher * of rules. 2893adfc5217SJeff Kirsher */ 2894adfc5217SJeff Kirsher if (cnt >= o->max_cmd_len) 2895adfc5217SJeff Kirsher break; 2896adfc5217SJeff Kirsher } 2897adfc5217SJeff Kirsher 2898adfc5217SJeff Kirsher *line_idx = cnt; 2899adfc5217SJeff Kirsher 2900adfc5217SJeff Kirsher /* if no more MACs to configure - we are done */ 2901adfc5217SJeff Kirsher if (list_empty(&cmd_pos->data.macs_head)) 2902adfc5217SJeff Kirsher cmd_pos->done = true; 2903adfc5217SJeff Kirsher } 2904adfc5217SJeff Kirsher 2905adfc5217SJeff Kirsher static inline void bnx2x_mcast_hdl_pending_del_e2(struct bnx2x *bp, 2906adfc5217SJeff Kirsher struct bnx2x_mcast_obj *o, struct bnx2x_pending_mcast_cmd *cmd_pos, 2907adfc5217SJeff Kirsher int *line_idx) 2908adfc5217SJeff Kirsher { 2909adfc5217SJeff Kirsher int cnt = *line_idx; 2910adfc5217SJeff Kirsher 2911adfc5217SJeff Kirsher while (cmd_pos->data.macs_num) { 2912adfc5217SJeff Kirsher o->set_one_rule(bp, o, cnt, NULL, cmd_pos->type); 2913adfc5217SJeff Kirsher 2914adfc5217SJeff Kirsher cnt++; 2915adfc5217SJeff Kirsher 2916adfc5217SJeff Kirsher cmd_pos->data.macs_num--; 2917adfc5217SJeff Kirsher 2918adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "Deleting MAC. %d left,cnt is %d\n", 2919adfc5217SJeff Kirsher cmd_pos->data.macs_num, cnt); 2920adfc5217SJeff Kirsher 2921adfc5217SJeff Kirsher /* Break if we reached the maximum 2922adfc5217SJeff Kirsher * number of rules. 2923adfc5217SJeff Kirsher */ 2924adfc5217SJeff Kirsher if (cnt >= o->max_cmd_len) 2925adfc5217SJeff Kirsher break; 2926adfc5217SJeff Kirsher } 2927adfc5217SJeff Kirsher 2928adfc5217SJeff Kirsher *line_idx = cnt; 2929adfc5217SJeff Kirsher 2930adfc5217SJeff Kirsher /* If we cleared all bins - we are done */ 2931adfc5217SJeff Kirsher if (!cmd_pos->data.macs_num) 2932adfc5217SJeff Kirsher cmd_pos->done = true; 2933adfc5217SJeff Kirsher } 2934adfc5217SJeff Kirsher 2935adfc5217SJeff Kirsher static inline void bnx2x_mcast_hdl_pending_restore_e2(struct bnx2x *bp, 2936adfc5217SJeff Kirsher struct bnx2x_mcast_obj *o, struct bnx2x_pending_mcast_cmd *cmd_pos, 2937adfc5217SJeff Kirsher int *line_idx) 2938adfc5217SJeff Kirsher { 2939adfc5217SJeff Kirsher cmd_pos->data.next_bin = o->hdl_restore(bp, o, cmd_pos->data.next_bin, 2940adfc5217SJeff Kirsher line_idx); 2941adfc5217SJeff Kirsher 2942adfc5217SJeff Kirsher if (cmd_pos->data.next_bin < 0) 2943adfc5217SJeff Kirsher /* If o->set_restore returned -1 we are done */ 2944adfc5217SJeff Kirsher cmd_pos->done = true; 2945adfc5217SJeff Kirsher else 2946adfc5217SJeff Kirsher /* Start from the next bin next time */ 2947adfc5217SJeff Kirsher cmd_pos->data.next_bin++; 2948adfc5217SJeff Kirsher } 2949adfc5217SJeff Kirsher 2950adfc5217SJeff Kirsher static inline int bnx2x_mcast_handle_pending_cmds_e2(struct bnx2x *bp, 2951adfc5217SJeff Kirsher struct bnx2x_mcast_ramrod_params *p) 2952adfc5217SJeff Kirsher { 2953adfc5217SJeff Kirsher struct bnx2x_pending_mcast_cmd *cmd_pos, *cmd_pos_n; 2954adfc5217SJeff Kirsher int cnt = 0; 2955adfc5217SJeff Kirsher struct bnx2x_mcast_obj *o = p->mcast_obj; 2956adfc5217SJeff Kirsher 2957adfc5217SJeff Kirsher list_for_each_entry_safe(cmd_pos, cmd_pos_n, &o->pending_cmds_head, 2958adfc5217SJeff Kirsher link) { 2959adfc5217SJeff Kirsher switch (cmd_pos->type) { 2960adfc5217SJeff Kirsher case BNX2X_MCAST_CMD_ADD: 2961adfc5217SJeff Kirsher bnx2x_mcast_hdl_pending_add_e2(bp, o, cmd_pos, &cnt); 2962adfc5217SJeff Kirsher break; 2963adfc5217SJeff Kirsher 2964adfc5217SJeff Kirsher case BNX2X_MCAST_CMD_DEL: 2965adfc5217SJeff Kirsher bnx2x_mcast_hdl_pending_del_e2(bp, o, cmd_pos, &cnt); 2966adfc5217SJeff Kirsher break; 2967adfc5217SJeff Kirsher 2968adfc5217SJeff Kirsher case BNX2X_MCAST_CMD_RESTORE: 2969adfc5217SJeff Kirsher bnx2x_mcast_hdl_pending_restore_e2(bp, o, cmd_pos, 2970adfc5217SJeff Kirsher &cnt); 2971adfc5217SJeff Kirsher break; 2972adfc5217SJeff Kirsher 2973adfc5217SJeff Kirsher default: 2974adfc5217SJeff Kirsher BNX2X_ERR("Unknown command: %d\n", cmd_pos->type); 2975adfc5217SJeff Kirsher return -EINVAL; 2976adfc5217SJeff Kirsher } 2977adfc5217SJeff Kirsher 2978adfc5217SJeff Kirsher /* If the command has been completed - remove it from the list 2979adfc5217SJeff Kirsher * and free the memory 2980adfc5217SJeff Kirsher */ 2981adfc5217SJeff Kirsher if (cmd_pos->done) { 2982adfc5217SJeff Kirsher list_del(&cmd_pos->link); 2983adfc5217SJeff Kirsher kfree(cmd_pos); 2984adfc5217SJeff Kirsher } 2985adfc5217SJeff Kirsher 2986adfc5217SJeff Kirsher /* Break if we reached the maximum number of rules */ 2987adfc5217SJeff Kirsher if (cnt >= o->max_cmd_len) 2988adfc5217SJeff Kirsher break; 2989adfc5217SJeff Kirsher } 2990adfc5217SJeff Kirsher 2991adfc5217SJeff Kirsher return cnt; 2992adfc5217SJeff Kirsher } 2993adfc5217SJeff Kirsher 2994adfc5217SJeff Kirsher static inline void bnx2x_mcast_hdl_add(struct bnx2x *bp, 2995adfc5217SJeff Kirsher struct bnx2x_mcast_obj *o, struct bnx2x_mcast_ramrod_params *p, 2996adfc5217SJeff Kirsher int *line_idx) 2997adfc5217SJeff Kirsher { 2998adfc5217SJeff Kirsher struct bnx2x_mcast_list_elem *mlist_pos; 299986564c3fSYuval Mintz union bnx2x_mcast_config_data cfg_data = {NULL}; 3000adfc5217SJeff Kirsher int cnt = *line_idx; 3001adfc5217SJeff Kirsher 3002adfc5217SJeff Kirsher list_for_each_entry(mlist_pos, &p->mcast_list, link) { 3003adfc5217SJeff Kirsher cfg_data.mac = mlist_pos->mac; 3004adfc5217SJeff Kirsher o->set_one_rule(bp, o, cnt, &cfg_data, BNX2X_MCAST_CMD_ADD); 3005adfc5217SJeff Kirsher 3006adfc5217SJeff Kirsher cnt++; 3007adfc5217SJeff Kirsher 30080f9dad10SJoe Perches DP(BNX2X_MSG_SP, "About to configure %pM mcast MAC\n", 30090f9dad10SJoe Perches mlist_pos->mac); 3010adfc5217SJeff Kirsher } 3011adfc5217SJeff Kirsher 3012adfc5217SJeff Kirsher *line_idx = cnt; 3013adfc5217SJeff Kirsher } 3014adfc5217SJeff Kirsher 3015adfc5217SJeff Kirsher static inline void bnx2x_mcast_hdl_del(struct bnx2x *bp, 3016adfc5217SJeff Kirsher struct bnx2x_mcast_obj *o, struct bnx2x_mcast_ramrod_params *p, 3017adfc5217SJeff Kirsher int *line_idx) 3018adfc5217SJeff Kirsher { 3019adfc5217SJeff Kirsher int cnt = *line_idx, i; 3020adfc5217SJeff Kirsher 3021adfc5217SJeff Kirsher for (i = 0; i < p->mcast_list_len; i++) { 3022adfc5217SJeff Kirsher o->set_one_rule(bp, o, cnt, NULL, BNX2X_MCAST_CMD_DEL); 3023adfc5217SJeff Kirsher 3024adfc5217SJeff Kirsher cnt++; 3025adfc5217SJeff Kirsher 3026adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "Deleting MAC. %d left\n", 3027adfc5217SJeff Kirsher p->mcast_list_len - i - 1); 3028adfc5217SJeff Kirsher } 3029adfc5217SJeff Kirsher 3030adfc5217SJeff Kirsher *line_idx = cnt; 3031adfc5217SJeff Kirsher } 3032adfc5217SJeff Kirsher 3033adfc5217SJeff Kirsher /** 3034adfc5217SJeff Kirsher * bnx2x_mcast_handle_current_cmd - 3035adfc5217SJeff Kirsher * 3036adfc5217SJeff Kirsher * @bp: device handle 3037adfc5217SJeff Kirsher * @p: 3038adfc5217SJeff Kirsher * @cmd: 3039adfc5217SJeff Kirsher * @start_cnt: first line in the ramrod data that may be used 3040adfc5217SJeff Kirsher * 3041adfc5217SJeff Kirsher * This function is called iff there is enough place for the current command in 3042adfc5217SJeff Kirsher * the ramrod data. 3043adfc5217SJeff Kirsher * Returns number of lines filled in the ramrod data in total. 3044adfc5217SJeff Kirsher */ 3045adfc5217SJeff Kirsher static inline int bnx2x_mcast_handle_current_cmd(struct bnx2x *bp, 304686564c3fSYuval Mintz struct bnx2x_mcast_ramrod_params *p, 304786564c3fSYuval Mintz enum bnx2x_mcast_cmd cmd, 3048adfc5217SJeff Kirsher int start_cnt) 3049adfc5217SJeff Kirsher { 3050adfc5217SJeff Kirsher struct bnx2x_mcast_obj *o = p->mcast_obj; 3051adfc5217SJeff Kirsher int cnt = start_cnt; 3052adfc5217SJeff Kirsher 3053adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "p->mcast_list_len=%d\n", p->mcast_list_len); 3054adfc5217SJeff Kirsher 3055adfc5217SJeff Kirsher switch (cmd) { 3056adfc5217SJeff Kirsher case BNX2X_MCAST_CMD_ADD: 3057adfc5217SJeff Kirsher bnx2x_mcast_hdl_add(bp, o, p, &cnt); 3058adfc5217SJeff Kirsher break; 3059adfc5217SJeff Kirsher 3060adfc5217SJeff Kirsher case BNX2X_MCAST_CMD_DEL: 3061adfc5217SJeff Kirsher bnx2x_mcast_hdl_del(bp, o, p, &cnt); 3062adfc5217SJeff Kirsher break; 3063adfc5217SJeff Kirsher 3064adfc5217SJeff Kirsher case BNX2X_MCAST_CMD_RESTORE: 3065adfc5217SJeff Kirsher o->hdl_restore(bp, o, 0, &cnt); 3066adfc5217SJeff Kirsher break; 3067adfc5217SJeff Kirsher 3068adfc5217SJeff Kirsher default: 3069adfc5217SJeff Kirsher BNX2X_ERR("Unknown command: %d\n", cmd); 3070adfc5217SJeff Kirsher return -EINVAL; 3071adfc5217SJeff Kirsher } 3072adfc5217SJeff Kirsher 3073adfc5217SJeff Kirsher /* The current command has been handled */ 3074adfc5217SJeff Kirsher p->mcast_list_len = 0; 3075adfc5217SJeff Kirsher 3076adfc5217SJeff Kirsher return cnt; 3077adfc5217SJeff Kirsher } 3078adfc5217SJeff Kirsher 3079adfc5217SJeff Kirsher static int bnx2x_mcast_validate_e2(struct bnx2x *bp, 3080adfc5217SJeff Kirsher struct bnx2x_mcast_ramrod_params *p, 308186564c3fSYuval Mintz enum bnx2x_mcast_cmd cmd) 3082adfc5217SJeff Kirsher { 3083adfc5217SJeff Kirsher struct bnx2x_mcast_obj *o = p->mcast_obj; 3084adfc5217SJeff Kirsher int reg_sz = o->get_registry_size(o); 3085adfc5217SJeff Kirsher 3086adfc5217SJeff Kirsher switch (cmd) { 3087adfc5217SJeff Kirsher /* DEL command deletes all currently configured MACs */ 3088adfc5217SJeff Kirsher case BNX2X_MCAST_CMD_DEL: 3089adfc5217SJeff Kirsher o->set_registry_size(o, 0); 3090adfc5217SJeff Kirsher /* Don't break */ 3091adfc5217SJeff Kirsher 3092adfc5217SJeff Kirsher /* RESTORE command will restore the entire multicast configuration */ 3093adfc5217SJeff Kirsher case BNX2X_MCAST_CMD_RESTORE: 3094adfc5217SJeff Kirsher /* Here we set the approximate amount of work to do, which in 3095adfc5217SJeff Kirsher * fact may be only less as some MACs in postponed ADD 3096adfc5217SJeff Kirsher * command(s) scheduled before this command may fall into 3097adfc5217SJeff Kirsher * the same bin and the actual number of bins set in the 3098adfc5217SJeff Kirsher * registry would be less than we estimated here. See 3099adfc5217SJeff Kirsher * bnx2x_mcast_set_one_rule_e2() for further details. 3100adfc5217SJeff Kirsher */ 3101adfc5217SJeff Kirsher p->mcast_list_len = reg_sz; 3102adfc5217SJeff Kirsher break; 3103adfc5217SJeff Kirsher 3104adfc5217SJeff Kirsher case BNX2X_MCAST_CMD_ADD: 3105adfc5217SJeff Kirsher case BNX2X_MCAST_CMD_CONT: 3106adfc5217SJeff Kirsher /* Here we assume that all new MACs will fall into new bins. 3107adfc5217SJeff Kirsher * However we will correct the real registry size after we 3108adfc5217SJeff Kirsher * handle all pending commands. 3109adfc5217SJeff Kirsher */ 3110adfc5217SJeff Kirsher o->set_registry_size(o, reg_sz + p->mcast_list_len); 3111adfc5217SJeff Kirsher break; 3112adfc5217SJeff Kirsher 3113adfc5217SJeff Kirsher default: 3114adfc5217SJeff Kirsher BNX2X_ERR("Unknown command: %d\n", cmd); 3115adfc5217SJeff Kirsher return -EINVAL; 3116adfc5217SJeff Kirsher } 3117adfc5217SJeff Kirsher 3118adfc5217SJeff Kirsher /* Increase the total number of MACs pending to be configured */ 3119adfc5217SJeff Kirsher o->total_pending_num += p->mcast_list_len; 3120adfc5217SJeff Kirsher 3121adfc5217SJeff Kirsher return 0; 3122adfc5217SJeff Kirsher } 3123adfc5217SJeff Kirsher 3124adfc5217SJeff Kirsher static void bnx2x_mcast_revert_e2(struct bnx2x *bp, 3125adfc5217SJeff Kirsher struct bnx2x_mcast_ramrod_params *p, 3126adfc5217SJeff Kirsher int old_num_bins) 3127adfc5217SJeff Kirsher { 3128adfc5217SJeff Kirsher struct bnx2x_mcast_obj *o = p->mcast_obj; 3129adfc5217SJeff Kirsher 3130adfc5217SJeff Kirsher o->set_registry_size(o, old_num_bins); 3131adfc5217SJeff Kirsher o->total_pending_num -= p->mcast_list_len; 3132adfc5217SJeff Kirsher } 3133adfc5217SJeff Kirsher 3134adfc5217SJeff Kirsher /** 3135adfc5217SJeff Kirsher * bnx2x_mcast_set_rdata_hdr_e2 - sets a header values 3136adfc5217SJeff Kirsher * 3137adfc5217SJeff Kirsher * @bp: device handle 3138adfc5217SJeff Kirsher * @p: 3139adfc5217SJeff Kirsher * @len: number of rules to handle 3140adfc5217SJeff Kirsher */ 3141adfc5217SJeff Kirsher static inline void bnx2x_mcast_set_rdata_hdr_e2(struct bnx2x *bp, 3142adfc5217SJeff Kirsher struct bnx2x_mcast_ramrod_params *p, 3143adfc5217SJeff Kirsher u8 len) 3144adfc5217SJeff Kirsher { 3145adfc5217SJeff Kirsher struct bnx2x_raw_obj *r = &p->mcast_obj->raw; 3146adfc5217SJeff Kirsher struct eth_multicast_rules_ramrod_data *data = 3147adfc5217SJeff Kirsher (struct eth_multicast_rules_ramrod_data *)(r->rdata); 3148adfc5217SJeff Kirsher 314986564c3fSYuval Mintz data->header.echo = cpu_to_le32((r->cid & BNX2X_SWCID_MASK) | 315086564c3fSYuval Mintz (BNX2X_FILTER_MCAST_PENDING << 315186564c3fSYuval Mintz BNX2X_SWCID_SHIFT)); 3152adfc5217SJeff Kirsher data->header.rule_cnt = len; 3153adfc5217SJeff Kirsher } 3154adfc5217SJeff Kirsher 3155adfc5217SJeff Kirsher /** 3156adfc5217SJeff Kirsher * bnx2x_mcast_refresh_registry_e2 - recalculate the actual number of set bins 3157adfc5217SJeff Kirsher * 3158adfc5217SJeff Kirsher * @bp: device handle 3159adfc5217SJeff Kirsher * @o: 3160adfc5217SJeff Kirsher * 3161adfc5217SJeff Kirsher * Recalculate the actual number of set bins in the registry using Brian 3162adfc5217SJeff Kirsher * Kernighan's algorithm: it's execution complexity is as a number of set bins. 3163adfc5217SJeff Kirsher * 3164adfc5217SJeff Kirsher * returns 0 for the compliance with bnx2x_mcast_refresh_registry_e1(). 3165adfc5217SJeff Kirsher */ 3166adfc5217SJeff Kirsher static inline int bnx2x_mcast_refresh_registry_e2(struct bnx2x *bp, 3167adfc5217SJeff Kirsher struct bnx2x_mcast_obj *o) 3168adfc5217SJeff Kirsher { 3169adfc5217SJeff Kirsher int i, cnt = 0; 3170adfc5217SJeff Kirsher u64 elem; 3171adfc5217SJeff Kirsher 3172adfc5217SJeff Kirsher for (i = 0; i < BNX2X_MCAST_VEC_SZ; i++) { 3173adfc5217SJeff Kirsher elem = o->registry.aprox_match.vec[i]; 3174adfc5217SJeff Kirsher for (; elem; cnt++) 3175adfc5217SJeff Kirsher elem &= elem - 1; 3176adfc5217SJeff Kirsher } 3177adfc5217SJeff Kirsher 3178adfc5217SJeff Kirsher o->set_registry_size(o, cnt); 3179adfc5217SJeff Kirsher 3180adfc5217SJeff Kirsher return 0; 3181adfc5217SJeff Kirsher } 3182adfc5217SJeff Kirsher 3183adfc5217SJeff Kirsher static int bnx2x_mcast_setup_e2(struct bnx2x *bp, 3184adfc5217SJeff Kirsher struct bnx2x_mcast_ramrod_params *p, 318586564c3fSYuval Mintz enum bnx2x_mcast_cmd cmd) 3186adfc5217SJeff Kirsher { 3187adfc5217SJeff Kirsher struct bnx2x_raw_obj *raw = &p->mcast_obj->raw; 3188adfc5217SJeff Kirsher struct bnx2x_mcast_obj *o = p->mcast_obj; 3189adfc5217SJeff Kirsher struct eth_multicast_rules_ramrod_data *data = 3190adfc5217SJeff Kirsher (struct eth_multicast_rules_ramrod_data *)(raw->rdata); 3191adfc5217SJeff Kirsher int cnt = 0, rc; 3192adfc5217SJeff Kirsher 3193adfc5217SJeff Kirsher /* Reset the ramrod data buffer */ 3194adfc5217SJeff Kirsher memset(data, 0, sizeof(*data)); 3195adfc5217SJeff Kirsher 3196adfc5217SJeff Kirsher cnt = bnx2x_mcast_handle_pending_cmds_e2(bp, p); 3197adfc5217SJeff Kirsher 3198adfc5217SJeff Kirsher /* If there are no more pending commands - clear SCHEDULED state */ 3199adfc5217SJeff Kirsher if (list_empty(&o->pending_cmds_head)) 3200adfc5217SJeff Kirsher o->clear_sched(o); 3201adfc5217SJeff Kirsher 3202adfc5217SJeff Kirsher /* The below may be true iff there was enough room in ramrod 3203adfc5217SJeff Kirsher * data for all pending commands and for the current 3204adfc5217SJeff Kirsher * command. Otherwise the current command would have been added 3205adfc5217SJeff Kirsher * to the pending commands and p->mcast_list_len would have been 3206adfc5217SJeff Kirsher * zeroed. 3207adfc5217SJeff Kirsher */ 3208adfc5217SJeff Kirsher if (p->mcast_list_len > 0) 3209adfc5217SJeff Kirsher cnt = bnx2x_mcast_handle_current_cmd(bp, p, cmd, cnt); 3210adfc5217SJeff Kirsher 3211adfc5217SJeff Kirsher /* We've pulled out some MACs - update the total number of 3212adfc5217SJeff Kirsher * outstanding. 3213adfc5217SJeff Kirsher */ 3214adfc5217SJeff Kirsher o->total_pending_num -= cnt; 3215adfc5217SJeff Kirsher 3216adfc5217SJeff Kirsher /* send a ramrod */ 3217adfc5217SJeff Kirsher WARN_ON(o->total_pending_num < 0); 3218adfc5217SJeff Kirsher WARN_ON(cnt > o->max_cmd_len); 3219adfc5217SJeff Kirsher 3220adfc5217SJeff Kirsher bnx2x_mcast_set_rdata_hdr_e2(bp, p, (u8)cnt); 3221adfc5217SJeff Kirsher 3222adfc5217SJeff Kirsher /* Update a registry size if there are no more pending operations. 3223adfc5217SJeff Kirsher * 3224adfc5217SJeff Kirsher * We don't want to change the value of the registry size if there are 3225adfc5217SJeff Kirsher * pending operations because we want it to always be equal to the 3226adfc5217SJeff Kirsher * exact or the approximate number (see bnx2x_mcast_validate_e2()) of 3227adfc5217SJeff Kirsher * set bins after the last requested operation in order to properly 3228adfc5217SJeff Kirsher * evaluate the size of the next DEL/RESTORE operation. 3229adfc5217SJeff Kirsher * 3230adfc5217SJeff Kirsher * Note that we update the registry itself during command(s) handling 3231adfc5217SJeff Kirsher * - see bnx2x_mcast_set_one_rule_e2(). That's because for 57712 we 3232adfc5217SJeff Kirsher * aggregate multiple commands (ADD/DEL/RESTORE) into one ramrod but 3233adfc5217SJeff Kirsher * with a limited amount of update commands (per MAC/bin) and we don't 3234adfc5217SJeff Kirsher * know in this scope what the actual state of bins configuration is 3235adfc5217SJeff Kirsher * going to be after this ramrod. 3236adfc5217SJeff Kirsher */ 3237adfc5217SJeff Kirsher if (!o->total_pending_num) 3238adfc5217SJeff Kirsher bnx2x_mcast_refresh_registry_e2(bp, o); 3239adfc5217SJeff Kirsher 324016a5fd92SYuval Mintz /* If CLEAR_ONLY was requested - don't send a ramrod and clear 3241adfc5217SJeff Kirsher * RAMROD_PENDING status immediately. 3242adfc5217SJeff Kirsher */ 3243adfc5217SJeff Kirsher if (test_bit(RAMROD_DRV_CLR_ONLY, &p->ramrod_flags)) { 3244adfc5217SJeff Kirsher raw->clear_pending(raw); 3245adfc5217SJeff Kirsher return 0; 3246adfc5217SJeff Kirsher } else { 324716a5fd92SYuval Mintz /* No need for an explicit memory barrier here as long we would 3248adfc5217SJeff Kirsher * need to ensure the ordering of writing to the SPQ element 3249adfc5217SJeff Kirsher * and updating of the SPQ producer which involves a memory 3250adfc5217SJeff Kirsher * read and we will have to put a full memory barrier there 3251adfc5217SJeff Kirsher * (inside bnx2x_sp_post()). 3252adfc5217SJeff Kirsher */ 3253adfc5217SJeff Kirsher 3254adfc5217SJeff Kirsher /* Send a ramrod */ 3255adfc5217SJeff Kirsher rc = bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_MULTICAST_RULES, 3256adfc5217SJeff Kirsher raw->cid, U64_HI(raw->rdata_mapping), 3257adfc5217SJeff Kirsher U64_LO(raw->rdata_mapping), 3258adfc5217SJeff Kirsher ETH_CONNECTION_TYPE); 3259adfc5217SJeff Kirsher if (rc) 3260adfc5217SJeff Kirsher return rc; 3261adfc5217SJeff Kirsher 3262adfc5217SJeff Kirsher /* Ramrod completion is pending */ 3263adfc5217SJeff Kirsher return 1; 3264adfc5217SJeff Kirsher } 3265adfc5217SJeff Kirsher } 3266adfc5217SJeff Kirsher 3267adfc5217SJeff Kirsher static int bnx2x_mcast_validate_e1h(struct bnx2x *bp, 3268adfc5217SJeff Kirsher struct bnx2x_mcast_ramrod_params *p, 326986564c3fSYuval Mintz enum bnx2x_mcast_cmd cmd) 3270adfc5217SJeff Kirsher { 3271adfc5217SJeff Kirsher /* Mark, that there is a work to do */ 3272adfc5217SJeff Kirsher if ((cmd == BNX2X_MCAST_CMD_DEL) || (cmd == BNX2X_MCAST_CMD_RESTORE)) 3273adfc5217SJeff Kirsher p->mcast_list_len = 1; 3274adfc5217SJeff Kirsher 3275adfc5217SJeff Kirsher return 0; 3276adfc5217SJeff Kirsher } 3277adfc5217SJeff Kirsher 3278adfc5217SJeff Kirsher static void bnx2x_mcast_revert_e1h(struct bnx2x *bp, 3279adfc5217SJeff Kirsher struct bnx2x_mcast_ramrod_params *p, 3280adfc5217SJeff Kirsher int old_num_bins) 3281adfc5217SJeff Kirsher { 3282adfc5217SJeff Kirsher /* Do nothing */ 3283adfc5217SJeff Kirsher } 3284adfc5217SJeff Kirsher 3285adfc5217SJeff Kirsher #define BNX2X_57711_SET_MC_FILTER(filter, bit) \ 3286adfc5217SJeff Kirsher do { \ 3287adfc5217SJeff Kirsher (filter)[(bit) >> 5] |= (1 << ((bit) & 0x1f)); \ 3288adfc5217SJeff Kirsher } while (0) 3289adfc5217SJeff Kirsher 3290adfc5217SJeff Kirsher static inline void bnx2x_mcast_hdl_add_e1h(struct bnx2x *bp, 3291adfc5217SJeff Kirsher struct bnx2x_mcast_obj *o, 3292adfc5217SJeff Kirsher struct bnx2x_mcast_ramrod_params *p, 3293adfc5217SJeff Kirsher u32 *mc_filter) 3294adfc5217SJeff Kirsher { 3295adfc5217SJeff Kirsher struct bnx2x_mcast_list_elem *mlist_pos; 3296adfc5217SJeff Kirsher int bit; 3297adfc5217SJeff Kirsher 3298adfc5217SJeff Kirsher list_for_each_entry(mlist_pos, &p->mcast_list, link) { 3299adfc5217SJeff Kirsher bit = bnx2x_mcast_bin_from_mac(mlist_pos->mac); 3300adfc5217SJeff Kirsher BNX2X_57711_SET_MC_FILTER(mc_filter, bit); 3301adfc5217SJeff Kirsher 33020f9dad10SJoe Perches DP(BNX2X_MSG_SP, "About to configure %pM mcast MAC, bin %d\n", 33030f9dad10SJoe Perches mlist_pos->mac, bit); 3304adfc5217SJeff Kirsher 3305adfc5217SJeff Kirsher /* bookkeeping... */ 3306adfc5217SJeff Kirsher BIT_VEC64_SET_BIT(o->registry.aprox_match.vec, 3307adfc5217SJeff Kirsher bit); 3308adfc5217SJeff Kirsher } 3309adfc5217SJeff Kirsher } 3310adfc5217SJeff Kirsher 3311adfc5217SJeff Kirsher static inline void bnx2x_mcast_hdl_restore_e1h(struct bnx2x *bp, 3312adfc5217SJeff Kirsher struct bnx2x_mcast_obj *o, struct bnx2x_mcast_ramrod_params *p, 3313adfc5217SJeff Kirsher u32 *mc_filter) 3314adfc5217SJeff Kirsher { 3315adfc5217SJeff Kirsher int bit; 3316adfc5217SJeff Kirsher 3317adfc5217SJeff Kirsher for (bit = bnx2x_mcast_get_next_bin(o, 0); 3318adfc5217SJeff Kirsher bit >= 0; 3319adfc5217SJeff Kirsher bit = bnx2x_mcast_get_next_bin(o, bit + 1)) { 3320adfc5217SJeff Kirsher BNX2X_57711_SET_MC_FILTER(mc_filter, bit); 3321adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "About to set bin %d\n", bit); 3322adfc5217SJeff Kirsher } 3323adfc5217SJeff Kirsher } 3324adfc5217SJeff Kirsher 332516a5fd92SYuval Mintz /* On 57711 we write the multicast MACs' approximate match 3326adfc5217SJeff Kirsher * table by directly into the TSTORM's internal RAM. So we don't 3327adfc5217SJeff Kirsher * really need to handle any tricks to make it work. 3328adfc5217SJeff Kirsher */ 3329adfc5217SJeff Kirsher static int bnx2x_mcast_setup_e1h(struct bnx2x *bp, 3330adfc5217SJeff Kirsher struct bnx2x_mcast_ramrod_params *p, 333186564c3fSYuval Mintz enum bnx2x_mcast_cmd cmd) 3332adfc5217SJeff Kirsher { 3333adfc5217SJeff Kirsher int i; 3334adfc5217SJeff Kirsher struct bnx2x_mcast_obj *o = p->mcast_obj; 3335adfc5217SJeff Kirsher struct bnx2x_raw_obj *r = &o->raw; 3336adfc5217SJeff Kirsher 3337adfc5217SJeff Kirsher /* If CLEAR_ONLY has been requested - clear the registry 3338adfc5217SJeff Kirsher * and clear a pending bit. 3339adfc5217SJeff Kirsher */ 3340adfc5217SJeff Kirsher if (!test_bit(RAMROD_DRV_CLR_ONLY, &p->ramrod_flags)) { 3341adfc5217SJeff Kirsher u32 mc_filter[MC_HASH_SIZE] = {0}; 3342adfc5217SJeff Kirsher 3343adfc5217SJeff Kirsher /* Set the multicast filter bits before writing it into 3344adfc5217SJeff Kirsher * the internal memory. 3345adfc5217SJeff Kirsher */ 3346adfc5217SJeff Kirsher switch (cmd) { 3347adfc5217SJeff Kirsher case BNX2X_MCAST_CMD_ADD: 3348adfc5217SJeff Kirsher bnx2x_mcast_hdl_add_e1h(bp, o, p, mc_filter); 3349adfc5217SJeff Kirsher break; 3350adfc5217SJeff Kirsher 3351adfc5217SJeff Kirsher case BNX2X_MCAST_CMD_DEL: 335294f05b0fSJoe Perches DP(BNX2X_MSG_SP, 335394f05b0fSJoe Perches "Invalidating multicast MACs configuration\n"); 3354adfc5217SJeff Kirsher 3355adfc5217SJeff Kirsher /* clear the registry */ 3356adfc5217SJeff Kirsher memset(o->registry.aprox_match.vec, 0, 3357adfc5217SJeff Kirsher sizeof(o->registry.aprox_match.vec)); 3358adfc5217SJeff Kirsher break; 3359adfc5217SJeff Kirsher 3360adfc5217SJeff Kirsher case BNX2X_MCAST_CMD_RESTORE: 3361adfc5217SJeff Kirsher bnx2x_mcast_hdl_restore_e1h(bp, o, p, mc_filter); 3362adfc5217SJeff Kirsher break; 3363adfc5217SJeff Kirsher 3364adfc5217SJeff Kirsher default: 3365adfc5217SJeff Kirsher BNX2X_ERR("Unknown command: %d\n", cmd); 3366adfc5217SJeff Kirsher return -EINVAL; 3367adfc5217SJeff Kirsher } 3368adfc5217SJeff Kirsher 3369adfc5217SJeff Kirsher /* Set the mcast filter in the internal memory */ 3370adfc5217SJeff Kirsher for (i = 0; i < MC_HASH_SIZE; i++) 3371adfc5217SJeff Kirsher REG_WR(bp, MC_HASH_OFFSET(bp, i), mc_filter[i]); 3372adfc5217SJeff Kirsher } else 3373adfc5217SJeff Kirsher /* clear the registry */ 3374adfc5217SJeff Kirsher memset(o->registry.aprox_match.vec, 0, 3375adfc5217SJeff Kirsher sizeof(o->registry.aprox_match.vec)); 3376adfc5217SJeff Kirsher 3377adfc5217SJeff Kirsher /* We are done */ 3378adfc5217SJeff Kirsher r->clear_pending(r); 3379adfc5217SJeff Kirsher 3380adfc5217SJeff Kirsher return 0; 3381adfc5217SJeff Kirsher } 3382adfc5217SJeff Kirsher 3383adfc5217SJeff Kirsher static int bnx2x_mcast_validate_e1(struct bnx2x *bp, 3384adfc5217SJeff Kirsher struct bnx2x_mcast_ramrod_params *p, 338586564c3fSYuval Mintz enum bnx2x_mcast_cmd cmd) 3386adfc5217SJeff Kirsher { 3387adfc5217SJeff Kirsher struct bnx2x_mcast_obj *o = p->mcast_obj; 3388adfc5217SJeff Kirsher int reg_sz = o->get_registry_size(o); 3389adfc5217SJeff Kirsher 3390adfc5217SJeff Kirsher switch (cmd) { 3391adfc5217SJeff Kirsher /* DEL command deletes all currently configured MACs */ 3392adfc5217SJeff Kirsher case BNX2X_MCAST_CMD_DEL: 3393adfc5217SJeff Kirsher o->set_registry_size(o, 0); 3394adfc5217SJeff Kirsher /* Don't break */ 3395adfc5217SJeff Kirsher 3396adfc5217SJeff Kirsher /* RESTORE command will restore the entire multicast configuration */ 3397adfc5217SJeff Kirsher case BNX2X_MCAST_CMD_RESTORE: 3398adfc5217SJeff Kirsher p->mcast_list_len = reg_sz; 3399adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "Command %d, p->mcast_list_len=%d\n", 3400adfc5217SJeff Kirsher cmd, p->mcast_list_len); 3401adfc5217SJeff Kirsher break; 3402adfc5217SJeff Kirsher 3403adfc5217SJeff Kirsher case BNX2X_MCAST_CMD_ADD: 3404adfc5217SJeff Kirsher case BNX2X_MCAST_CMD_CONT: 3405adfc5217SJeff Kirsher /* Multicast MACs on 57710 are configured as unicast MACs and 3406adfc5217SJeff Kirsher * there is only a limited number of CAM entries for that 3407adfc5217SJeff Kirsher * matter. 3408adfc5217SJeff Kirsher */ 3409adfc5217SJeff Kirsher if (p->mcast_list_len > o->max_cmd_len) { 341051c1a580SMerav Sicron BNX2X_ERR("Can't configure more than %d multicast MACs on 57710\n", 341151c1a580SMerav Sicron o->max_cmd_len); 3412adfc5217SJeff Kirsher return -EINVAL; 3413adfc5217SJeff Kirsher } 3414adfc5217SJeff Kirsher /* Every configured MAC should be cleared if DEL command is 3415adfc5217SJeff Kirsher * called. Only the last ADD command is relevant as long as 3416adfc5217SJeff Kirsher * every ADD commands overrides the previous configuration. 3417adfc5217SJeff Kirsher */ 3418adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "p->mcast_list_len=%d\n", p->mcast_list_len); 3419adfc5217SJeff Kirsher if (p->mcast_list_len > 0) 3420adfc5217SJeff Kirsher o->set_registry_size(o, p->mcast_list_len); 3421adfc5217SJeff Kirsher 3422adfc5217SJeff Kirsher break; 3423adfc5217SJeff Kirsher 3424adfc5217SJeff Kirsher default: 3425adfc5217SJeff Kirsher BNX2X_ERR("Unknown command: %d\n", cmd); 3426adfc5217SJeff Kirsher return -EINVAL; 3427adfc5217SJeff Kirsher } 3428adfc5217SJeff Kirsher 3429adfc5217SJeff Kirsher /* We want to ensure that commands are executed one by one for 57710. 3430adfc5217SJeff Kirsher * Therefore each none-empty command will consume o->max_cmd_len. 3431adfc5217SJeff Kirsher */ 3432adfc5217SJeff Kirsher if (p->mcast_list_len) 3433adfc5217SJeff Kirsher o->total_pending_num += o->max_cmd_len; 3434adfc5217SJeff Kirsher 3435adfc5217SJeff Kirsher return 0; 3436adfc5217SJeff Kirsher } 3437adfc5217SJeff Kirsher 3438adfc5217SJeff Kirsher static void bnx2x_mcast_revert_e1(struct bnx2x *bp, 3439adfc5217SJeff Kirsher struct bnx2x_mcast_ramrod_params *p, 3440adfc5217SJeff Kirsher int old_num_macs) 3441adfc5217SJeff Kirsher { 3442adfc5217SJeff Kirsher struct bnx2x_mcast_obj *o = p->mcast_obj; 3443adfc5217SJeff Kirsher 3444adfc5217SJeff Kirsher o->set_registry_size(o, old_num_macs); 3445adfc5217SJeff Kirsher 3446adfc5217SJeff Kirsher /* If current command hasn't been handled yet and we are 3447adfc5217SJeff Kirsher * here means that it's meant to be dropped and we have to 344816a5fd92SYuval Mintz * update the number of outstanding MACs accordingly. 3449adfc5217SJeff Kirsher */ 3450adfc5217SJeff Kirsher if (p->mcast_list_len) 3451adfc5217SJeff Kirsher o->total_pending_num -= o->max_cmd_len; 3452adfc5217SJeff Kirsher } 3453adfc5217SJeff Kirsher 3454adfc5217SJeff Kirsher static void bnx2x_mcast_set_one_rule_e1(struct bnx2x *bp, 3455adfc5217SJeff Kirsher struct bnx2x_mcast_obj *o, int idx, 3456adfc5217SJeff Kirsher union bnx2x_mcast_config_data *cfg_data, 345786564c3fSYuval Mintz enum bnx2x_mcast_cmd cmd) 3458adfc5217SJeff Kirsher { 3459adfc5217SJeff Kirsher struct bnx2x_raw_obj *r = &o->raw; 3460adfc5217SJeff Kirsher struct mac_configuration_cmd *data = 3461adfc5217SJeff Kirsher (struct mac_configuration_cmd *)(r->rdata); 3462adfc5217SJeff Kirsher 3463adfc5217SJeff Kirsher /* copy mac */ 3464adfc5217SJeff Kirsher if ((cmd == BNX2X_MCAST_CMD_ADD) || (cmd == BNX2X_MCAST_CMD_RESTORE)) { 3465adfc5217SJeff Kirsher bnx2x_set_fw_mac_addr(&data->config_table[idx].msb_mac_addr, 3466adfc5217SJeff Kirsher &data->config_table[idx].middle_mac_addr, 3467adfc5217SJeff Kirsher &data->config_table[idx].lsb_mac_addr, 3468adfc5217SJeff Kirsher cfg_data->mac); 3469adfc5217SJeff Kirsher 3470adfc5217SJeff Kirsher data->config_table[idx].vlan_id = 0; 3471adfc5217SJeff Kirsher data->config_table[idx].pf_id = r->func_id; 3472adfc5217SJeff Kirsher data->config_table[idx].clients_bit_vector = 3473adfc5217SJeff Kirsher cpu_to_le32(1 << r->cl_id); 3474adfc5217SJeff Kirsher 3475adfc5217SJeff Kirsher SET_FLAG(data->config_table[idx].flags, 3476adfc5217SJeff Kirsher MAC_CONFIGURATION_ENTRY_ACTION_TYPE, 3477adfc5217SJeff Kirsher T_ETH_MAC_COMMAND_SET); 3478adfc5217SJeff Kirsher } 3479adfc5217SJeff Kirsher } 3480adfc5217SJeff Kirsher 3481adfc5217SJeff Kirsher /** 3482adfc5217SJeff Kirsher * bnx2x_mcast_set_rdata_hdr_e1 - set header values in mac_configuration_cmd 3483adfc5217SJeff Kirsher * 3484adfc5217SJeff Kirsher * @bp: device handle 3485adfc5217SJeff Kirsher * @p: 3486adfc5217SJeff Kirsher * @len: number of rules to handle 3487adfc5217SJeff Kirsher */ 3488adfc5217SJeff Kirsher static inline void bnx2x_mcast_set_rdata_hdr_e1(struct bnx2x *bp, 3489adfc5217SJeff Kirsher struct bnx2x_mcast_ramrod_params *p, 3490adfc5217SJeff Kirsher u8 len) 3491adfc5217SJeff Kirsher { 3492adfc5217SJeff Kirsher struct bnx2x_raw_obj *r = &p->mcast_obj->raw; 3493adfc5217SJeff Kirsher struct mac_configuration_cmd *data = 3494adfc5217SJeff Kirsher (struct mac_configuration_cmd *)(r->rdata); 3495adfc5217SJeff Kirsher 3496adfc5217SJeff Kirsher u8 offset = (CHIP_REV_IS_SLOW(bp) ? 3497adfc5217SJeff Kirsher BNX2X_MAX_EMUL_MULTI*(1 + r->func_id) : 3498adfc5217SJeff Kirsher BNX2X_MAX_MULTICAST*(1 + r->func_id)); 3499adfc5217SJeff Kirsher 3500adfc5217SJeff Kirsher data->hdr.offset = offset; 350186564c3fSYuval Mintz data->hdr.client_id = cpu_to_le16(0xff); 350286564c3fSYuval Mintz data->hdr.echo = cpu_to_le32((r->cid & BNX2X_SWCID_MASK) | 350386564c3fSYuval Mintz (BNX2X_FILTER_MCAST_PENDING << 350486564c3fSYuval Mintz BNX2X_SWCID_SHIFT)); 3505adfc5217SJeff Kirsher data->hdr.length = len; 3506adfc5217SJeff Kirsher } 3507adfc5217SJeff Kirsher 3508adfc5217SJeff Kirsher /** 3509adfc5217SJeff Kirsher * bnx2x_mcast_handle_restore_cmd_e1 - restore command for 57710 3510adfc5217SJeff Kirsher * 3511adfc5217SJeff Kirsher * @bp: device handle 3512adfc5217SJeff Kirsher * @o: 3513adfc5217SJeff Kirsher * @start_idx: index in the registry to start from 3514adfc5217SJeff Kirsher * @rdata_idx: index in the ramrod data to start from 3515adfc5217SJeff Kirsher * 3516adfc5217SJeff Kirsher * restore command for 57710 is like all other commands - always a stand alone 3517adfc5217SJeff Kirsher * command - start_idx and rdata_idx will always be 0. This function will always 3518adfc5217SJeff Kirsher * succeed. 3519adfc5217SJeff Kirsher * returns -1 to comply with 57712 variant. 3520adfc5217SJeff Kirsher */ 3521adfc5217SJeff Kirsher static inline int bnx2x_mcast_handle_restore_cmd_e1( 3522adfc5217SJeff Kirsher struct bnx2x *bp, struct bnx2x_mcast_obj *o , int start_idx, 3523adfc5217SJeff Kirsher int *rdata_idx) 3524adfc5217SJeff Kirsher { 3525adfc5217SJeff Kirsher struct bnx2x_mcast_mac_elem *elem; 3526adfc5217SJeff Kirsher int i = 0; 352786564c3fSYuval Mintz union bnx2x_mcast_config_data cfg_data = {NULL}; 3528adfc5217SJeff Kirsher 3529adfc5217SJeff Kirsher /* go through the registry and configure the MACs from it. */ 3530adfc5217SJeff Kirsher list_for_each_entry(elem, &o->registry.exact_match.macs, link) { 3531adfc5217SJeff Kirsher cfg_data.mac = &elem->mac[0]; 3532adfc5217SJeff Kirsher o->set_one_rule(bp, o, i, &cfg_data, BNX2X_MCAST_CMD_RESTORE); 3533adfc5217SJeff Kirsher 3534adfc5217SJeff Kirsher i++; 3535adfc5217SJeff Kirsher 35360f9dad10SJoe Perches DP(BNX2X_MSG_SP, "About to configure %pM mcast MAC\n", 35370f9dad10SJoe Perches cfg_data.mac); 3538adfc5217SJeff Kirsher } 3539adfc5217SJeff Kirsher 3540adfc5217SJeff Kirsher *rdata_idx = i; 3541adfc5217SJeff Kirsher 3542adfc5217SJeff Kirsher return -1; 3543adfc5217SJeff Kirsher } 3544adfc5217SJeff Kirsher 3545adfc5217SJeff Kirsher static inline int bnx2x_mcast_handle_pending_cmds_e1( 3546adfc5217SJeff Kirsher struct bnx2x *bp, struct bnx2x_mcast_ramrod_params *p) 3547adfc5217SJeff Kirsher { 3548adfc5217SJeff Kirsher struct bnx2x_pending_mcast_cmd *cmd_pos; 3549adfc5217SJeff Kirsher struct bnx2x_mcast_mac_elem *pmac_pos; 3550adfc5217SJeff Kirsher struct bnx2x_mcast_obj *o = p->mcast_obj; 355186564c3fSYuval Mintz union bnx2x_mcast_config_data cfg_data = {NULL}; 3552adfc5217SJeff Kirsher int cnt = 0; 3553adfc5217SJeff Kirsher 3554adfc5217SJeff Kirsher /* If nothing to be done - return */ 3555adfc5217SJeff Kirsher if (list_empty(&o->pending_cmds_head)) 3556adfc5217SJeff Kirsher return 0; 3557adfc5217SJeff Kirsher 3558adfc5217SJeff Kirsher /* Handle the first command */ 3559adfc5217SJeff Kirsher cmd_pos = list_first_entry(&o->pending_cmds_head, 3560adfc5217SJeff Kirsher struct bnx2x_pending_mcast_cmd, link); 3561adfc5217SJeff Kirsher 3562adfc5217SJeff Kirsher switch (cmd_pos->type) { 3563adfc5217SJeff Kirsher case BNX2X_MCAST_CMD_ADD: 3564adfc5217SJeff Kirsher list_for_each_entry(pmac_pos, &cmd_pos->data.macs_head, link) { 3565adfc5217SJeff Kirsher cfg_data.mac = &pmac_pos->mac[0]; 3566adfc5217SJeff Kirsher o->set_one_rule(bp, o, cnt, &cfg_data, cmd_pos->type); 3567adfc5217SJeff Kirsher 3568adfc5217SJeff Kirsher cnt++; 3569adfc5217SJeff Kirsher 35700f9dad10SJoe Perches DP(BNX2X_MSG_SP, "About to configure %pM mcast MAC\n", 35710f9dad10SJoe Perches pmac_pos->mac); 3572adfc5217SJeff Kirsher } 3573adfc5217SJeff Kirsher break; 3574adfc5217SJeff Kirsher 3575adfc5217SJeff Kirsher case BNX2X_MCAST_CMD_DEL: 3576adfc5217SJeff Kirsher cnt = cmd_pos->data.macs_num; 3577adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "About to delete %d multicast MACs\n", cnt); 3578adfc5217SJeff Kirsher break; 3579adfc5217SJeff Kirsher 3580adfc5217SJeff Kirsher case BNX2X_MCAST_CMD_RESTORE: 3581adfc5217SJeff Kirsher o->hdl_restore(bp, o, 0, &cnt); 3582adfc5217SJeff Kirsher break; 3583adfc5217SJeff Kirsher 3584adfc5217SJeff Kirsher default: 3585adfc5217SJeff Kirsher BNX2X_ERR("Unknown command: %d\n", cmd_pos->type); 3586adfc5217SJeff Kirsher return -EINVAL; 3587adfc5217SJeff Kirsher } 3588adfc5217SJeff Kirsher 3589adfc5217SJeff Kirsher list_del(&cmd_pos->link); 3590adfc5217SJeff Kirsher kfree(cmd_pos); 3591adfc5217SJeff Kirsher 3592adfc5217SJeff Kirsher return cnt; 3593adfc5217SJeff Kirsher } 3594adfc5217SJeff Kirsher 3595adfc5217SJeff Kirsher /** 3596adfc5217SJeff Kirsher * bnx2x_get_fw_mac_addr - revert the bnx2x_set_fw_mac_addr(). 3597adfc5217SJeff Kirsher * 3598adfc5217SJeff Kirsher * @fw_hi: 3599adfc5217SJeff Kirsher * @fw_mid: 3600adfc5217SJeff Kirsher * @fw_lo: 3601adfc5217SJeff Kirsher * @mac: 3602adfc5217SJeff Kirsher */ 3603adfc5217SJeff Kirsher static inline void bnx2x_get_fw_mac_addr(__le16 *fw_hi, __le16 *fw_mid, 3604adfc5217SJeff Kirsher __le16 *fw_lo, u8 *mac) 3605adfc5217SJeff Kirsher { 3606adfc5217SJeff Kirsher mac[1] = ((u8 *)fw_hi)[0]; 3607adfc5217SJeff Kirsher mac[0] = ((u8 *)fw_hi)[1]; 3608adfc5217SJeff Kirsher mac[3] = ((u8 *)fw_mid)[0]; 3609adfc5217SJeff Kirsher mac[2] = ((u8 *)fw_mid)[1]; 3610adfc5217SJeff Kirsher mac[5] = ((u8 *)fw_lo)[0]; 3611adfc5217SJeff Kirsher mac[4] = ((u8 *)fw_lo)[1]; 3612adfc5217SJeff Kirsher } 3613adfc5217SJeff Kirsher 3614adfc5217SJeff Kirsher /** 3615adfc5217SJeff Kirsher * bnx2x_mcast_refresh_registry_e1 - 3616adfc5217SJeff Kirsher * 3617adfc5217SJeff Kirsher * @bp: device handle 3618adfc5217SJeff Kirsher * @cnt: 3619adfc5217SJeff Kirsher * 3620adfc5217SJeff Kirsher * Check the ramrod data first entry flag to see if it's a DELETE or ADD command 3621adfc5217SJeff Kirsher * and update the registry correspondingly: if ADD - allocate a memory and add 3622adfc5217SJeff Kirsher * the entries to the registry (list), if DELETE - clear the registry and free 3623adfc5217SJeff Kirsher * the memory. 3624adfc5217SJeff Kirsher */ 3625adfc5217SJeff Kirsher static inline int bnx2x_mcast_refresh_registry_e1(struct bnx2x *bp, 3626adfc5217SJeff Kirsher struct bnx2x_mcast_obj *o) 3627adfc5217SJeff Kirsher { 3628adfc5217SJeff Kirsher struct bnx2x_raw_obj *raw = &o->raw; 3629adfc5217SJeff Kirsher struct bnx2x_mcast_mac_elem *elem; 3630adfc5217SJeff Kirsher struct mac_configuration_cmd *data = 3631adfc5217SJeff Kirsher (struct mac_configuration_cmd *)(raw->rdata); 3632adfc5217SJeff Kirsher 3633adfc5217SJeff Kirsher /* If first entry contains a SET bit - the command was ADD, 3634adfc5217SJeff Kirsher * otherwise - DEL_ALL 3635adfc5217SJeff Kirsher */ 3636adfc5217SJeff Kirsher if (GET_FLAG(data->config_table[0].flags, 3637adfc5217SJeff Kirsher MAC_CONFIGURATION_ENTRY_ACTION_TYPE)) { 3638adfc5217SJeff Kirsher int i, len = data->hdr.length; 3639adfc5217SJeff Kirsher 3640adfc5217SJeff Kirsher /* Break if it was a RESTORE command */ 3641adfc5217SJeff Kirsher if (!list_empty(&o->registry.exact_match.macs)) 3642adfc5217SJeff Kirsher return 0; 3643adfc5217SJeff Kirsher 364401e23742SThomas Meyer elem = kcalloc(len, sizeof(*elem), GFP_ATOMIC); 3645adfc5217SJeff Kirsher if (!elem) { 3646adfc5217SJeff Kirsher BNX2X_ERR("Failed to allocate registry memory\n"); 3647adfc5217SJeff Kirsher return -ENOMEM; 3648adfc5217SJeff Kirsher } 3649adfc5217SJeff Kirsher 3650adfc5217SJeff Kirsher for (i = 0; i < len; i++, elem++) { 3651adfc5217SJeff Kirsher bnx2x_get_fw_mac_addr( 3652adfc5217SJeff Kirsher &data->config_table[i].msb_mac_addr, 3653adfc5217SJeff Kirsher &data->config_table[i].middle_mac_addr, 3654adfc5217SJeff Kirsher &data->config_table[i].lsb_mac_addr, 3655adfc5217SJeff Kirsher elem->mac); 36560f9dad10SJoe Perches DP(BNX2X_MSG_SP, "Adding registry entry for [%pM]\n", 36570f9dad10SJoe Perches elem->mac); 3658adfc5217SJeff Kirsher list_add_tail(&elem->link, 3659adfc5217SJeff Kirsher &o->registry.exact_match.macs); 3660adfc5217SJeff Kirsher } 3661adfc5217SJeff Kirsher } else { 3662adfc5217SJeff Kirsher elem = list_first_entry(&o->registry.exact_match.macs, 3663adfc5217SJeff Kirsher struct bnx2x_mcast_mac_elem, link); 3664adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "Deleting a registry\n"); 3665adfc5217SJeff Kirsher kfree(elem); 3666adfc5217SJeff Kirsher INIT_LIST_HEAD(&o->registry.exact_match.macs); 3667adfc5217SJeff Kirsher } 3668adfc5217SJeff Kirsher 3669adfc5217SJeff Kirsher return 0; 3670adfc5217SJeff Kirsher } 3671adfc5217SJeff Kirsher 3672adfc5217SJeff Kirsher static int bnx2x_mcast_setup_e1(struct bnx2x *bp, 3673adfc5217SJeff Kirsher struct bnx2x_mcast_ramrod_params *p, 367486564c3fSYuval Mintz enum bnx2x_mcast_cmd cmd) 3675adfc5217SJeff Kirsher { 3676adfc5217SJeff Kirsher struct bnx2x_mcast_obj *o = p->mcast_obj; 3677adfc5217SJeff Kirsher struct bnx2x_raw_obj *raw = &o->raw; 3678adfc5217SJeff Kirsher struct mac_configuration_cmd *data = 3679adfc5217SJeff Kirsher (struct mac_configuration_cmd *)(raw->rdata); 3680adfc5217SJeff Kirsher int cnt = 0, i, rc; 3681adfc5217SJeff Kirsher 3682adfc5217SJeff Kirsher /* Reset the ramrod data buffer */ 3683adfc5217SJeff Kirsher memset(data, 0, sizeof(*data)); 3684adfc5217SJeff Kirsher 3685adfc5217SJeff Kirsher /* First set all entries as invalid */ 3686adfc5217SJeff Kirsher for (i = 0; i < o->max_cmd_len ; i++) 3687adfc5217SJeff Kirsher SET_FLAG(data->config_table[i].flags, 3688adfc5217SJeff Kirsher MAC_CONFIGURATION_ENTRY_ACTION_TYPE, 3689adfc5217SJeff Kirsher T_ETH_MAC_COMMAND_INVALIDATE); 3690adfc5217SJeff Kirsher 3691adfc5217SJeff Kirsher /* Handle pending commands first */ 3692adfc5217SJeff Kirsher cnt = bnx2x_mcast_handle_pending_cmds_e1(bp, p); 3693adfc5217SJeff Kirsher 3694adfc5217SJeff Kirsher /* If there are no more pending commands - clear SCHEDULED state */ 3695adfc5217SJeff Kirsher if (list_empty(&o->pending_cmds_head)) 3696adfc5217SJeff Kirsher o->clear_sched(o); 3697adfc5217SJeff Kirsher 3698adfc5217SJeff Kirsher /* The below may be true iff there were no pending commands */ 3699adfc5217SJeff Kirsher if (!cnt) 3700adfc5217SJeff Kirsher cnt = bnx2x_mcast_handle_current_cmd(bp, p, cmd, 0); 3701adfc5217SJeff Kirsher 3702adfc5217SJeff Kirsher /* For 57710 every command has o->max_cmd_len length to ensure that 3703adfc5217SJeff Kirsher * commands are done one at a time. 3704adfc5217SJeff Kirsher */ 3705adfc5217SJeff Kirsher o->total_pending_num -= o->max_cmd_len; 3706adfc5217SJeff Kirsher 3707adfc5217SJeff Kirsher /* send a ramrod */ 3708adfc5217SJeff Kirsher 3709adfc5217SJeff Kirsher WARN_ON(cnt > o->max_cmd_len); 3710adfc5217SJeff Kirsher 3711adfc5217SJeff Kirsher /* Set ramrod header (in particular, a number of entries to update) */ 3712adfc5217SJeff Kirsher bnx2x_mcast_set_rdata_hdr_e1(bp, p, (u8)cnt); 3713adfc5217SJeff Kirsher 3714adfc5217SJeff Kirsher /* update a registry: we need the registry contents to be always up 3715adfc5217SJeff Kirsher * to date in order to be able to execute a RESTORE opcode. Here 3716adfc5217SJeff Kirsher * we use the fact that for 57710 we sent one command at a time 3717adfc5217SJeff Kirsher * hence we may take the registry update out of the command handling 3718adfc5217SJeff Kirsher * and do it in a simpler way here. 3719adfc5217SJeff Kirsher */ 3720adfc5217SJeff Kirsher rc = bnx2x_mcast_refresh_registry_e1(bp, o); 3721adfc5217SJeff Kirsher if (rc) 3722adfc5217SJeff Kirsher return rc; 3723adfc5217SJeff Kirsher 372416a5fd92SYuval Mintz /* If CLEAR_ONLY was requested - don't send a ramrod and clear 3725adfc5217SJeff Kirsher * RAMROD_PENDING status immediately. 3726adfc5217SJeff Kirsher */ 3727adfc5217SJeff Kirsher if (test_bit(RAMROD_DRV_CLR_ONLY, &p->ramrod_flags)) { 3728adfc5217SJeff Kirsher raw->clear_pending(raw); 3729adfc5217SJeff Kirsher return 0; 3730adfc5217SJeff Kirsher } else { 373116a5fd92SYuval Mintz /* No need for an explicit memory barrier here as long we would 3732adfc5217SJeff Kirsher * need to ensure the ordering of writing to the SPQ element 3733adfc5217SJeff Kirsher * and updating of the SPQ producer which involves a memory 3734adfc5217SJeff Kirsher * read and we will have to put a full memory barrier there 3735adfc5217SJeff Kirsher * (inside bnx2x_sp_post()). 3736adfc5217SJeff Kirsher */ 3737adfc5217SJeff Kirsher 3738adfc5217SJeff Kirsher /* Send a ramrod */ 3739adfc5217SJeff Kirsher rc = bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_SET_MAC, raw->cid, 3740adfc5217SJeff Kirsher U64_HI(raw->rdata_mapping), 3741adfc5217SJeff Kirsher U64_LO(raw->rdata_mapping), 3742adfc5217SJeff Kirsher ETH_CONNECTION_TYPE); 3743adfc5217SJeff Kirsher if (rc) 3744adfc5217SJeff Kirsher return rc; 3745adfc5217SJeff Kirsher 3746adfc5217SJeff Kirsher /* Ramrod completion is pending */ 3747adfc5217SJeff Kirsher return 1; 3748adfc5217SJeff Kirsher } 3749adfc5217SJeff Kirsher } 3750adfc5217SJeff Kirsher 3751adfc5217SJeff Kirsher static int bnx2x_mcast_get_registry_size_exact(struct bnx2x_mcast_obj *o) 3752adfc5217SJeff Kirsher { 3753adfc5217SJeff Kirsher return o->registry.exact_match.num_macs_set; 3754adfc5217SJeff Kirsher } 3755adfc5217SJeff Kirsher 3756adfc5217SJeff Kirsher static int bnx2x_mcast_get_registry_size_aprox(struct bnx2x_mcast_obj *o) 3757adfc5217SJeff Kirsher { 3758adfc5217SJeff Kirsher return o->registry.aprox_match.num_bins_set; 3759adfc5217SJeff Kirsher } 3760adfc5217SJeff Kirsher 3761adfc5217SJeff Kirsher static void bnx2x_mcast_set_registry_size_exact(struct bnx2x_mcast_obj *o, 3762adfc5217SJeff Kirsher int n) 3763adfc5217SJeff Kirsher { 3764adfc5217SJeff Kirsher o->registry.exact_match.num_macs_set = n; 3765adfc5217SJeff Kirsher } 3766adfc5217SJeff Kirsher 3767adfc5217SJeff Kirsher static void bnx2x_mcast_set_registry_size_aprox(struct bnx2x_mcast_obj *o, 3768adfc5217SJeff Kirsher int n) 3769adfc5217SJeff Kirsher { 3770adfc5217SJeff Kirsher o->registry.aprox_match.num_bins_set = n; 3771adfc5217SJeff Kirsher } 3772adfc5217SJeff Kirsher 3773adfc5217SJeff Kirsher int bnx2x_config_mcast(struct bnx2x *bp, 3774adfc5217SJeff Kirsher struct bnx2x_mcast_ramrod_params *p, 377586564c3fSYuval Mintz enum bnx2x_mcast_cmd cmd) 3776adfc5217SJeff Kirsher { 3777adfc5217SJeff Kirsher struct bnx2x_mcast_obj *o = p->mcast_obj; 3778adfc5217SJeff Kirsher struct bnx2x_raw_obj *r = &o->raw; 3779adfc5217SJeff Kirsher int rc = 0, old_reg_size; 3780adfc5217SJeff Kirsher 3781adfc5217SJeff Kirsher /* This is needed to recover number of currently configured mcast macs 3782adfc5217SJeff Kirsher * in case of failure. 3783adfc5217SJeff Kirsher */ 3784adfc5217SJeff Kirsher old_reg_size = o->get_registry_size(o); 3785adfc5217SJeff Kirsher 3786adfc5217SJeff Kirsher /* Do some calculations and checks */ 3787adfc5217SJeff Kirsher rc = o->validate(bp, p, cmd); 3788adfc5217SJeff Kirsher if (rc) 3789adfc5217SJeff Kirsher return rc; 3790adfc5217SJeff Kirsher 3791adfc5217SJeff Kirsher /* Return if there is no work to do */ 3792adfc5217SJeff Kirsher if ((!p->mcast_list_len) && (!o->check_sched(o))) 3793adfc5217SJeff Kirsher return 0; 3794adfc5217SJeff Kirsher 379551c1a580SMerav Sicron DP(BNX2X_MSG_SP, "o->total_pending_num=%d p->mcast_list_len=%d o->max_cmd_len=%d\n", 379651c1a580SMerav Sicron o->total_pending_num, p->mcast_list_len, o->max_cmd_len); 3797adfc5217SJeff Kirsher 3798adfc5217SJeff Kirsher /* Enqueue the current command to the pending list if we can't complete 3799adfc5217SJeff Kirsher * it in the current iteration 3800adfc5217SJeff Kirsher */ 3801adfc5217SJeff Kirsher if (r->check_pending(r) || 3802adfc5217SJeff Kirsher ((o->max_cmd_len > 0) && (o->total_pending_num > o->max_cmd_len))) { 3803adfc5217SJeff Kirsher rc = o->enqueue_cmd(bp, p->mcast_obj, p, cmd); 3804adfc5217SJeff Kirsher if (rc < 0) 3805adfc5217SJeff Kirsher goto error_exit1; 3806adfc5217SJeff Kirsher 3807adfc5217SJeff Kirsher /* As long as the current command is in a command list we 3808adfc5217SJeff Kirsher * don't need to handle it separately. 3809adfc5217SJeff Kirsher */ 3810adfc5217SJeff Kirsher p->mcast_list_len = 0; 3811adfc5217SJeff Kirsher } 3812adfc5217SJeff Kirsher 3813adfc5217SJeff Kirsher if (!r->check_pending(r)) { 3814adfc5217SJeff Kirsher 3815adfc5217SJeff Kirsher /* Set 'pending' state */ 3816adfc5217SJeff Kirsher r->set_pending(r); 3817adfc5217SJeff Kirsher 3818adfc5217SJeff Kirsher /* Configure the new classification in the chip */ 3819adfc5217SJeff Kirsher rc = o->config_mcast(bp, p, cmd); 3820adfc5217SJeff Kirsher if (rc < 0) 3821adfc5217SJeff Kirsher goto error_exit2; 3822adfc5217SJeff Kirsher 3823adfc5217SJeff Kirsher /* Wait for a ramrod completion if was requested */ 3824adfc5217SJeff Kirsher if (test_bit(RAMROD_COMP_WAIT, &p->ramrod_flags)) 3825adfc5217SJeff Kirsher rc = o->wait_comp(bp, o); 3826adfc5217SJeff Kirsher } 3827adfc5217SJeff Kirsher 3828adfc5217SJeff Kirsher return rc; 3829adfc5217SJeff Kirsher 3830adfc5217SJeff Kirsher error_exit2: 3831adfc5217SJeff Kirsher r->clear_pending(r); 3832adfc5217SJeff Kirsher 3833adfc5217SJeff Kirsher error_exit1: 3834adfc5217SJeff Kirsher o->revert(bp, p, old_reg_size); 3835adfc5217SJeff Kirsher 3836adfc5217SJeff Kirsher return rc; 3837adfc5217SJeff Kirsher } 3838adfc5217SJeff Kirsher 3839adfc5217SJeff Kirsher static void bnx2x_mcast_clear_sched(struct bnx2x_mcast_obj *o) 3840adfc5217SJeff Kirsher { 3841adfc5217SJeff Kirsher smp_mb__before_clear_bit(); 3842adfc5217SJeff Kirsher clear_bit(o->sched_state, o->raw.pstate); 3843adfc5217SJeff Kirsher smp_mb__after_clear_bit(); 3844adfc5217SJeff Kirsher } 3845adfc5217SJeff Kirsher 3846adfc5217SJeff Kirsher static void bnx2x_mcast_set_sched(struct bnx2x_mcast_obj *o) 3847adfc5217SJeff Kirsher { 3848adfc5217SJeff Kirsher smp_mb__before_clear_bit(); 3849adfc5217SJeff Kirsher set_bit(o->sched_state, o->raw.pstate); 3850adfc5217SJeff Kirsher smp_mb__after_clear_bit(); 3851adfc5217SJeff Kirsher } 3852adfc5217SJeff Kirsher 3853adfc5217SJeff Kirsher static bool bnx2x_mcast_check_sched(struct bnx2x_mcast_obj *o) 3854adfc5217SJeff Kirsher { 3855adfc5217SJeff Kirsher return !!test_bit(o->sched_state, o->raw.pstate); 3856adfc5217SJeff Kirsher } 3857adfc5217SJeff Kirsher 3858adfc5217SJeff Kirsher static bool bnx2x_mcast_check_pending(struct bnx2x_mcast_obj *o) 3859adfc5217SJeff Kirsher { 3860adfc5217SJeff Kirsher return o->raw.check_pending(&o->raw) || o->check_sched(o); 3861adfc5217SJeff Kirsher } 3862adfc5217SJeff Kirsher 3863adfc5217SJeff Kirsher void bnx2x_init_mcast_obj(struct bnx2x *bp, 3864adfc5217SJeff Kirsher struct bnx2x_mcast_obj *mcast_obj, 3865adfc5217SJeff Kirsher u8 mcast_cl_id, u32 mcast_cid, u8 func_id, 3866adfc5217SJeff Kirsher u8 engine_id, void *rdata, dma_addr_t rdata_mapping, 3867adfc5217SJeff Kirsher int state, unsigned long *pstate, bnx2x_obj_type type) 3868adfc5217SJeff Kirsher { 3869adfc5217SJeff Kirsher memset(mcast_obj, 0, sizeof(*mcast_obj)); 3870adfc5217SJeff Kirsher 3871adfc5217SJeff Kirsher bnx2x_init_raw_obj(&mcast_obj->raw, mcast_cl_id, mcast_cid, func_id, 3872adfc5217SJeff Kirsher rdata, rdata_mapping, state, pstate, type); 3873adfc5217SJeff Kirsher 3874adfc5217SJeff Kirsher mcast_obj->engine_id = engine_id; 3875adfc5217SJeff Kirsher 3876adfc5217SJeff Kirsher INIT_LIST_HEAD(&mcast_obj->pending_cmds_head); 3877adfc5217SJeff Kirsher 3878adfc5217SJeff Kirsher mcast_obj->sched_state = BNX2X_FILTER_MCAST_SCHED; 3879adfc5217SJeff Kirsher mcast_obj->check_sched = bnx2x_mcast_check_sched; 3880adfc5217SJeff Kirsher mcast_obj->set_sched = bnx2x_mcast_set_sched; 3881adfc5217SJeff Kirsher mcast_obj->clear_sched = bnx2x_mcast_clear_sched; 3882adfc5217SJeff Kirsher 3883adfc5217SJeff Kirsher if (CHIP_IS_E1(bp)) { 3884adfc5217SJeff Kirsher mcast_obj->config_mcast = bnx2x_mcast_setup_e1; 3885adfc5217SJeff Kirsher mcast_obj->enqueue_cmd = bnx2x_mcast_enqueue_cmd; 3886adfc5217SJeff Kirsher mcast_obj->hdl_restore = 3887adfc5217SJeff Kirsher bnx2x_mcast_handle_restore_cmd_e1; 3888adfc5217SJeff Kirsher mcast_obj->check_pending = bnx2x_mcast_check_pending; 3889adfc5217SJeff Kirsher 3890adfc5217SJeff Kirsher if (CHIP_REV_IS_SLOW(bp)) 3891adfc5217SJeff Kirsher mcast_obj->max_cmd_len = BNX2X_MAX_EMUL_MULTI; 3892adfc5217SJeff Kirsher else 3893adfc5217SJeff Kirsher mcast_obj->max_cmd_len = BNX2X_MAX_MULTICAST; 3894adfc5217SJeff Kirsher 3895adfc5217SJeff Kirsher mcast_obj->wait_comp = bnx2x_mcast_wait; 3896adfc5217SJeff Kirsher mcast_obj->set_one_rule = bnx2x_mcast_set_one_rule_e1; 3897adfc5217SJeff Kirsher mcast_obj->validate = bnx2x_mcast_validate_e1; 3898adfc5217SJeff Kirsher mcast_obj->revert = bnx2x_mcast_revert_e1; 3899adfc5217SJeff Kirsher mcast_obj->get_registry_size = 3900adfc5217SJeff Kirsher bnx2x_mcast_get_registry_size_exact; 3901adfc5217SJeff Kirsher mcast_obj->set_registry_size = 3902adfc5217SJeff Kirsher bnx2x_mcast_set_registry_size_exact; 3903adfc5217SJeff Kirsher 3904adfc5217SJeff Kirsher /* 57710 is the only chip that uses the exact match for mcast 3905adfc5217SJeff Kirsher * at the moment. 3906adfc5217SJeff Kirsher */ 3907adfc5217SJeff Kirsher INIT_LIST_HEAD(&mcast_obj->registry.exact_match.macs); 3908adfc5217SJeff Kirsher 3909adfc5217SJeff Kirsher } else if (CHIP_IS_E1H(bp)) { 3910adfc5217SJeff Kirsher mcast_obj->config_mcast = bnx2x_mcast_setup_e1h; 3911adfc5217SJeff Kirsher mcast_obj->enqueue_cmd = NULL; 3912adfc5217SJeff Kirsher mcast_obj->hdl_restore = NULL; 3913adfc5217SJeff Kirsher mcast_obj->check_pending = bnx2x_mcast_check_pending; 3914adfc5217SJeff Kirsher 3915adfc5217SJeff Kirsher /* 57711 doesn't send a ramrod, so it has unlimited credit 3916adfc5217SJeff Kirsher * for one command. 3917adfc5217SJeff Kirsher */ 3918adfc5217SJeff Kirsher mcast_obj->max_cmd_len = -1; 3919adfc5217SJeff Kirsher mcast_obj->wait_comp = bnx2x_mcast_wait; 3920adfc5217SJeff Kirsher mcast_obj->set_one_rule = NULL; 3921adfc5217SJeff Kirsher mcast_obj->validate = bnx2x_mcast_validate_e1h; 3922adfc5217SJeff Kirsher mcast_obj->revert = bnx2x_mcast_revert_e1h; 3923adfc5217SJeff Kirsher mcast_obj->get_registry_size = 3924adfc5217SJeff Kirsher bnx2x_mcast_get_registry_size_aprox; 3925adfc5217SJeff Kirsher mcast_obj->set_registry_size = 3926adfc5217SJeff Kirsher bnx2x_mcast_set_registry_size_aprox; 3927adfc5217SJeff Kirsher } else { 3928adfc5217SJeff Kirsher mcast_obj->config_mcast = bnx2x_mcast_setup_e2; 3929adfc5217SJeff Kirsher mcast_obj->enqueue_cmd = bnx2x_mcast_enqueue_cmd; 3930adfc5217SJeff Kirsher mcast_obj->hdl_restore = 3931adfc5217SJeff Kirsher bnx2x_mcast_handle_restore_cmd_e2; 3932adfc5217SJeff Kirsher mcast_obj->check_pending = bnx2x_mcast_check_pending; 3933adfc5217SJeff Kirsher /* TODO: There should be a proper HSI define for this number!!! 3934adfc5217SJeff Kirsher */ 3935adfc5217SJeff Kirsher mcast_obj->max_cmd_len = 16; 3936adfc5217SJeff Kirsher mcast_obj->wait_comp = bnx2x_mcast_wait; 3937adfc5217SJeff Kirsher mcast_obj->set_one_rule = bnx2x_mcast_set_one_rule_e2; 3938adfc5217SJeff Kirsher mcast_obj->validate = bnx2x_mcast_validate_e2; 3939adfc5217SJeff Kirsher mcast_obj->revert = bnx2x_mcast_revert_e2; 3940adfc5217SJeff Kirsher mcast_obj->get_registry_size = 3941adfc5217SJeff Kirsher bnx2x_mcast_get_registry_size_aprox; 3942adfc5217SJeff Kirsher mcast_obj->set_registry_size = 3943adfc5217SJeff Kirsher bnx2x_mcast_set_registry_size_aprox; 3944adfc5217SJeff Kirsher } 3945adfc5217SJeff Kirsher } 3946adfc5217SJeff Kirsher 3947adfc5217SJeff Kirsher /*************************** Credit handling **********************************/ 3948adfc5217SJeff Kirsher 3949adfc5217SJeff Kirsher /** 3950adfc5217SJeff Kirsher * atomic_add_ifless - add if the result is less than a given value. 3951adfc5217SJeff Kirsher * 3952adfc5217SJeff Kirsher * @v: pointer of type atomic_t 3953adfc5217SJeff Kirsher * @a: the amount to add to v... 3954adfc5217SJeff Kirsher * @u: ...if (v + a) is less than u. 3955adfc5217SJeff Kirsher * 3956adfc5217SJeff Kirsher * returns true if (v + a) was less than u, and false otherwise. 3957adfc5217SJeff Kirsher * 3958adfc5217SJeff Kirsher */ 3959adfc5217SJeff Kirsher static inline bool __atomic_add_ifless(atomic_t *v, int a, int u) 3960adfc5217SJeff Kirsher { 3961adfc5217SJeff Kirsher int c, old; 3962adfc5217SJeff Kirsher 3963adfc5217SJeff Kirsher c = atomic_read(v); 3964adfc5217SJeff Kirsher for (;;) { 3965adfc5217SJeff Kirsher if (unlikely(c + a >= u)) 3966adfc5217SJeff Kirsher return false; 3967adfc5217SJeff Kirsher 3968adfc5217SJeff Kirsher old = atomic_cmpxchg((v), c, c + a); 3969adfc5217SJeff Kirsher if (likely(old == c)) 3970adfc5217SJeff Kirsher break; 3971adfc5217SJeff Kirsher c = old; 3972adfc5217SJeff Kirsher } 3973adfc5217SJeff Kirsher 3974adfc5217SJeff Kirsher return true; 3975adfc5217SJeff Kirsher } 3976adfc5217SJeff Kirsher 3977adfc5217SJeff Kirsher /** 3978adfc5217SJeff Kirsher * atomic_dec_ifmoe - dec if the result is more or equal than a given value. 3979adfc5217SJeff Kirsher * 3980adfc5217SJeff Kirsher * @v: pointer of type atomic_t 3981adfc5217SJeff Kirsher * @a: the amount to dec from v... 3982adfc5217SJeff Kirsher * @u: ...if (v - a) is more or equal than u. 3983adfc5217SJeff Kirsher * 3984adfc5217SJeff Kirsher * returns true if (v - a) was more or equal than u, and false 3985adfc5217SJeff Kirsher * otherwise. 3986adfc5217SJeff Kirsher */ 3987adfc5217SJeff Kirsher static inline bool __atomic_dec_ifmoe(atomic_t *v, int a, int u) 3988adfc5217SJeff Kirsher { 3989adfc5217SJeff Kirsher int c, old; 3990adfc5217SJeff Kirsher 3991adfc5217SJeff Kirsher c = atomic_read(v); 3992adfc5217SJeff Kirsher for (;;) { 3993adfc5217SJeff Kirsher if (unlikely(c - a < u)) 3994adfc5217SJeff Kirsher return false; 3995adfc5217SJeff Kirsher 3996adfc5217SJeff Kirsher old = atomic_cmpxchg((v), c, c - a); 3997adfc5217SJeff Kirsher if (likely(old == c)) 3998adfc5217SJeff Kirsher break; 3999adfc5217SJeff Kirsher c = old; 4000adfc5217SJeff Kirsher } 4001adfc5217SJeff Kirsher 4002adfc5217SJeff Kirsher return true; 4003adfc5217SJeff Kirsher } 4004adfc5217SJeff Kirsher 4005adfc5217SJeff Kirsher static bool bnx2x_credit_pool_get(struct bnx2x_credit_pool_obj *o, int cnt) 4006adfc5217SJeff Kirsher { 4007adfc5217SJeff Kirsher bool rc; 4008adfc5217SJeff Kirsher 4009adfc5217SJeff Kirsher smp_mb(); 4010adfc5217SJeff Kirsher rc = __atomic_dec_ifmoe(&o->credit, cnt, 0); 4011adfc5217SJeff Kirsher smp_mb(); 4012adfc5217SJeff Kirsher 4013adfc5217SJeff Kirsher return rc; 4014adfc5217SJeff Kirsher } 4015adfc5217SJeff Kirsher 4016adfc5217SJeff Kirsher static bool bnx2x_credit_pool_put(struct bnx2x_credit_pool_obj *o, int cnt) 4017adfc5217SJeff Kirsher { 4018adfc5217SJeff Kirsher bool rc; 4019adfc5217SJeff Kirsher 4020adfc5217SJeff Kirsher smp_mb(); 4021adfc5217SJeff Kirsher 4022adfc5217SJeff Kirsher /* Don't let to refill if credit + cnt > pool_sz */ 4023adfc5217SJeff Kirsher rc = __atomic_add_ifless(&o->credit, cnt, o->pool_sz + 1); 4024adfc5217SJeff Kirsher 4025adfc5217SJeff Kirsher smp_mb(); 4026adfc5217SJeff Kirsher 4027adfc5217SJeff Kirsher return rc; 4028adfc5217SJeff Kirsher } 4029adfc5217SJeff Kirsher 4030adfc5217SJeff Kirsher static int bnx2x_credit_pool_check(struct bnx2x_credit_pool_obj *o) 4031adfc5217SJeff Kirsher { 4032adfc5217SJeff Kirsher int cur_credit; 4033adfc5217SJeff Kirsher 4034adfc5217SJeff Kirsher smp_mb(); 4035adfc5217SJeff Kirsher cur_credit = atomic_read(&o->credit); 4036adfc5217SJeff Kirsher 4037adfc5217SJeff Kirsher return cur_credit; 4038adfc5217SJeff Kirsher } 4039adfc5217SJeff Kirsher 4040adfc5217SJeff Kirsher static bool bnx2x_credit_pool_always_true(struct bnx2x_credit_pool_obj *o, 4041adfc5217SJeff Kirsher int cnt) 4042adfc5217SJeff Kirsher { 4043adfc5217SJeff Kirsher return true; 4044adfc5217SJeff Kirsher } 4045adfc5217SJeff Kirsher 4046adfc5217SJeff Kirsher static bool bnx2x_credit_pool_get_entry( 4047adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *o, 4048adfc5217SJeff Kirsher int *offset) 4049adfc5217SJeff Kirsher { 4050adfc5217SJeff Kirsher int idx, vec, i; 4051adfc5217SJeff Kirsher 4052adfc5217SJeff Kirsher *offset = -1; 4053adfc5217SJeff Kirsher 4054adfc5217SJeff Kirsher /* Find "internal cam-offset" then add to base for this object... */ 4055adfc5217SJeff Kirsher for (vec = 0; vec < BNX2X_POOL_VEC_SIZE; vec++) { 4056adfc5217SJeff Kirsher 4057adfc5217SJeff Kirsher /* Skip the current vector if there are no free entries in it */ 4058adfc5217SJeff Kirsher if (!o->pool_mirror[vec]) 4059adfc5217SJeff Kirsher continue; 4060adfc5217SJeff Kirsher 4061adfc5217SJeff Kirsher /* If we've got here we are going to find a free entry */ 4062c54e9bd3SDmitry Kravkov for (idx = vec * BIT_VEC64_ELEM_SZ, i = 0; 4063adfc5217SJeff Kirsher i < BIT_VEC64_ELEM_SZ; idx++, i++) 4064adfc5217SJeff Kirsher 4065adfc5217SJeff Kirsher if (BIT_VEC64_TEST_BIT(o->pool_mirror, idx)) { 4066adfc5217SJeff Kirsher /* Got one!! */ 4067adfc5217SJeff Kirsher BIT_VEC64_CLEAR_BIT(o->pool_mirror, idx); 4068adfc5217SJeff Kirsher *offset = o->base_pool_offset + idx; 4069adfc5217SJeff Kirsher return true; 4070adfc5217SJeff Kirsher } 4071adfc5217SJeff Kirsher } 4072adfc5217SJeff Kirsher 4073adfc5217SJeff Kirsher return false; 4074adfc5217SJeff Kirsher } 4075adfc5217SJeff Kirsher 4076adfc5217SJeff Kirsher static bool bnx2x_credit_pool_put_entry( 4077adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *o, 4078adfc5217SJeff Kirsher int offset) 4079adfc5217SJeff Kirsher { 4080adfc5217SJeff Kirsher if (offset < o->base_pool_offset) 4081adfc5217SJeff Kirsher return false; 4082adfc5217SJeff Kirsher 4083adfc5217SJeff Kirsher offset -= o->base_pool_offset; 4084adfc5217SJeff Kirsher 4085adfc5217SJeff Kirsher if (offset >= o->pool_sz) 4086adfc5217SJeff Kirsher return false; 4087adfc5217SJeff Kirsher 4088adfc5217SJeff Kirsher /* Return the entry to the pool */ 4089adfc5217SJeff Kirsher BIT_VEC64_SET_BIT(o->pool_mirror, offset); 4090adfc5217SJeff Kirsher 4091adfc5217SJeff Kirsher return true; 4092adfc5217SJeff Kirsher } 4093adfc5217SJeff Kirsher 4094adfc5217SJeff Kirsher static bool bnx2x_credit_pool_put_entry_always_true( 4095adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *o, 4096adfc5217SJeff Kirsher int offset) 4097adfc5217SJeff Kirsher { 4098adfc5217SJeff Kirsher return true; 4099adfc5217SJeff Kirsher } 4100adfc5217SJeff Kirsher 4101adfc5217SJeff Kirsher static bool bnx2x_credit_pool_get_entry_always_true( 4102adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *o, 4103adfc5217SJeff Kirsher int *offset) 4104adfc5217SJeff Kirsher { 4105adfc5217SJeff Kirsher *offset = -1; 4106adfc5217SJeff Kirsher return true; 4107adfc5217SJeff Kirsher } 4108adfc5217SJeff Kirsher /** 4109adfc5217SJeff Kirsher * bnx2x_init_credit_pool - initialize credit pool internals. 4110adfc5217SJeff Kirsher * 4111adfc5217SJeff Kirsher * @p: 4112adfc5217SJeff Kirsher * @base: Base entry in the CAM to use. 4113adfc5217SJeff Kirsher * @credit: pool size. 4114adfc5217SJeff Kirsher * 4115adfc5217SJeff Kirsher * If base is negative no CAM entries handling will be performed. 4116adfc5217SJeff Kirsher * If credit is negative pool operations will always succeed (unlimited pool). 4117adfc5217SJeff Kirsher * 4118adfc5217SJeff Kirsher */ 4119adfc5217SJeff Kirsher static inline void bnx2x_init_credit_pool(struct bnx2x_credit_pool_obj *p, 4120adfc5217SJeff Kirsher int base, int credit) 4121adfc5217SJeff Kirsher { 4122adfc5217SJeff Kirsher /* Zero the object first */ 4123adfc5217SJeff Kirsher memset(p, 0, sizeof(*p)); 4124adfc5217SJeff Kirsher 4125adfc5217SJeff Kirsher /* Set the table to all 1s */ 4126adfc5217SJeff Kirsher memset(&p->pool_mirror, 0xff, sizeof(p->pool_mirror)); 4127adfc5217SJeff Kirsher 4128adfc5217SJeff Kirsher /* Init a pool as full */ 4129adfc5217SJeff Kirsher atomic_set(&p->credit, credit); 4130adfc5217SJeff Kirsher 4131adfc5217SJeff Kirsher /* The total poll size */ 4132adfc5217SJeff Kirsher p->pool_sz = credit; 4133adfc5217SJeff Kirsher 4134adfc5217SJeff Kirsher p->base_pool_offset = base; 4135adfc5217SJeff Kirsher 4136adfc5217SJeff Kirsher /* Commit the change */ 4137adfc5217SJeff Kirsher smp_mb(); 4138adfc5217SJeff Kirsher 4139adfc5217SJeff Kirsher p->check = bnx2x_credit_pool_check; 4140adfc5217SJeff Kirsher 4141adfc5217SJeff Kirsher /* if pool credit is negative - disable the checks */ 4142adfc5217SJeff Kirsher if (credit >= 0) { 4143adfc5217SJeff Kirsher p->put = bnx2x_credit_pool_put; 4144adfc5217SJeff Kirsher p->get = bnx2x_credit_pool_get; 4145adfc5217SJeff Kirsher p->put_entry = bnx2x_credit_pool_put_entry; 4146adfc5217SJeff Kirsher p->get_entry = bnx2x_credit_pool_get_entry; 4147adfc5217SJeff Kirsher } else { 4148adfc5217SJeff Kirsher p->put = bnx2x_credit_pool_always_true; 4149adfc5217SJeff Kirsher p->get = bnx2x_credit_pool_always_true; 4150adfc5217SJeff Kirsher p->put_entry = bnx2x_credit_pool_put_entry_always_true; 4151adfc5217SJeff Kirsher p->get_entry = bnx2x_credit_pool_get_entry_always_true; 4152adfc5217SJeff Kirsher } 4153adfc5217SJeff Kirsher 4154adfc5217SJeff Kirsher /* If base is negative - disable entries handling */ 4155adfc5217SJeff Kirsher if (base < 0) { 4156adfc5217SJeff Kirsher p->put_entry = bnx2x_credit_pool_put_entry_always_true; 4157adfc5217SJeff Kirsher p->get_entry = bnx2x_credit_pool_get_entry_always_true; 4158adfc5217SJeff Kirsher } 4159adfc5217SJeff Kirsher } 4160adfc5217SJeff Kirsher 4161adfc5217SJeff Kirsher void bnx2x_init_mac_credit_pool(struct bnx2x *bp, 4162adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *p, u8 func_id, 4163adfc5217SJeff Kirsher u8 func_num) 4164adfc5217SJeff Kirsher { 4165adfc5217SJeff Kirsher /* TODO: this will be defined in consts as well... */ 4166adfc5217SJeff Kirsher #define BNX2X_CAM_SIZE_EMUL 5 4167adfc5217SJeff Kirsher 4168adfc5217SJeff Kirsher int cam_sz; 4169adfc5217SJeff Kirsher 4170adfc5217SJeff Kirsher if (CHIP_IS_E1(bp)) { 4171adfc5217SJeff Kirsher /* In E1, Multicast is saved in cam... */ 4172adfc5217SJeff Kirsher if (!CHIP_REV_IS_SLOW(bp)) 4173adfc5217SJeff Kirsher cam_sz = (MAX_MAC_CREDIT_E1 / 2) - BNX2X_MAX_MULTICAST; 4174adfc5217SJeff Kirsher else 4175adfc5217SJeff Kirsher cam_sz = BNX2X_CAM_SIZE_EMUL - BNX2X_MAX_EMUL_MULTI; 4176adfc5217SJeff Kirsher 4177adfc5217SJeff Kirsher bnx2x_init_credit_pool(p, func_id * cam_sz, cam_sz); 4178adfc5217SJeff Kirsher 4179adfc5217SJeff Kirsher } else if (CHIP_IS_E1H(bp)) { 4180adfc5217SJeff Kirsher /* CAM credit is equaly divided between all active functions 4181adfc5217SJeff Kirsher * on the PORT!. 4182adfc5217SJeff Kirsher */ 4183adfc5217SJeff Kirsher if ((func_num > 0)) { 4184adfc5217SJeff Kirsher if (!CHIP_REV_IS_SLOW(bp)) 4185adfc5217SJeff Kirsher cam_sz = (MAX_MAC_CREDIT_E1H / (2*func_num)); 4186adfc5217SJeff Kirsher else 4187adfc5217SJeff Kirsher cam_sz = BNX2X_CAM_SIZE_EMUL; 4188adfc5217SJeff Kirsher bnx2x_init_credit_pool(p, func_id * cam_sz, cam_sz); 4189adfc5217SJeff Kirsher } else { 4190adfc5217SJeff Kirsher /* this should never happen! Block MAC operations. */ 4191adfc5217SJeff Kirsher bnx2x_init_credit_pool(p, 0, 0); 4192adfc5217SJeff Kirsher } 4193adfc5217SJeff Kirsher 4194adfc5217SJeff Kirsher } else { 4195adfc5217SJeff Kirsher 419616a5fd92SYuval Mintz /* CAM credit is equaly divided between all active functions 4197adfc5217SJeff Kirsher * on the PATH. 4198adfc5217SJeff Kirsher */ 4199adfc5217SJeff Kirsher if ((func_num > 0)) { 4200adfc5217SJeff Kirsher if (!CHIP_REV_IS_SLOW(bp)) 4201adfc5217SJeff Kirsher cam_sz = (MAX_MAC_CREDIT_E2 / func_num); 4202adfc5217SJeff Kirsher else 4203adfc5217SJeff Kirsher cam_sz = BNX2X_CAM_SIZE_EMUL; 4204adfc5217SJeff Kirsher 420516a5fd92SYuval Mintz /* No need for CAM entries handling for 57712 and 4206adfc5217SJeff Kirsher * newer. 4207adfc5217SJeff Kirsher */ 4208adfc5217SJeff Kirsher bnx2x_init_credit_pool(p, -1, cam_sz); 4209adfc5217SJeff Kirsher } else { 4210adfc5217SJeff Kirsher /* this should never happen! Block MAC operations. */ 4211adfc5217SJeff Kirsher bnx2x_init_credit_pool(p, 0, 0); 4212adfc5217SJeff Kirsher } 4213adfc5217SJeff Kirsher } 4214adfc5217SJeff Kirsher } 4215adfc5217SJeff Kirsher 4216adfc5217SJeff Kirsher void bnx2x_init_vlan_credit_pool(struct bnx2x *bp, 4217adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *p, 4218adfc5217SJeff Kirsher u8 func_id, 4219adfc5217SJeff Kirsher u8 func_num) 4220adfc5217SJeff Kirsher { 4221adfc5217SJeff Kirsher if (CHIP_IS_E1x(bp)) { 422216a5fd92SYuval Mintz /* There is no VLAN credit in HW on 57710 and 57711 only 4223adfc5217SJeff Kirsher * MAC / MAC-VLAN can be set 4224adfc5217SJeff Kirsher */ 4225adfc5217SJeff Kirsher bnx2x_init_credit_pool(p, 0, -1); 4226adfc5217SJeff Kirsher } else { 422716a5fd92SYuval Mintz /* CAM credit is equally divided between all active functions 4228adfc5217SJeff Kirsher * on the PATH. 4229adfc5217SJeff Kirsher */ 4230adfc5217SJeff Kirsher if (func_num > 0) { 4231adfc5217SJeff Kirsher int credit = MAX_VLAN_CREDIT_E2 / func_num; 4232adfc5217SJeff Kirsher bnx2x_init_credit_pool(p, func_id * credit, credit); 4233adfc5217SJeff Kirsher } else 4234adfc5217SJeff Kirsher /* this should never happen! Block VLAN operations. */ 4235adfc5217SJeff Kirsher bnx2x_init_credit_pool(p, 0, 0); 4236adfc5217SJeff Kirsher } 4237adfc5217SJeff Kirsher } 4238adfc5217SJeff Kirsher 4239adfc5217SJeff Kirsher /****************** RSS Configuration ******************/ 4240adfc5217SJeff Kirsher /** 4241adfc5217SJeff Kirsher * bnx2x_debug_print_ind_table - prints the indirection table configuration. 4242adfc5217SJeff Kirsher * 424316a5fd92SYuval Mintz * @bp: driver handle 4244adfc5217SJeff Kirsher * @p: pointer to rss configuration 4245adfc5217SJeff Kirsher * 4246adfc5217SJeff Kirsher * Prints it when NETIF_MSG_IFUP debug level is configured. 4247adfc5217SJeff Kirsher */ 4248adfc5217SJeff Kirsher static inline void bnx2x_debug_print_ind_table(struct bnx2x *bp, 4249adfc5217SJeff Kirsher struct bnx2x_config_rss_params *p) 4250adfc5217SJeff Kirsher { 4251adfc5217SJeff Kirsher int i; 4252adfc5217SJeff Kirsher 4253adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "Setting indirection table to:\n"); 4254adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "0x0000: "); 4255adfc5217SJeff Kirsher for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++) { 4256adfc5217SJeff Kirsher DP_CONT(BNX2X_MSG_SP, "0x%02x ", p->ind_table[i]); 4257adfc5217SJeff Kirsher 4258adfc5217SJeff Kirsher /* Print 4 bytes in a line */ 4259adfc5217SJeff Kirsher if ((i + 1 < T_ETH_INDIRECTION_TABLE_SIZE) && 4260adfc5217SJeff Kirsher (((i + 1) & 0x3) == 0)) { 4261adfc5217SJeff Kirsher DP_CONT(BNX2X_MSG_SP, "\n"); 4262adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "0x%04x: ", i + 1); 4263adfc5217SJeff Kirsher } 4264adfc5217SJeff Kirsher } 4265adfc5217SJeff Kirsher 4266adfc5217SJeff Kirsher DP_CONT(BNX2X_MSG_SP, "\n"); 4267adfc5217SJeff Kirsher } 4268adfc5217SJeff Kirsher 4269adfc5217SJeff Kirsher /** 4270adfc5217SJeff Kirsher * bnx2x_setup_rss - configure RSS 4271adfc5217SJeff Kirsher * 4272adfc5217SJeff Kirsher * @bp: device handle 4273adfc5217SJeff Kirsher * @p: rss configuration 4274adfc5217SJeff Kirsher * 4275adfc5217SJeff Kirsher * sends on UPDATE ramrod for that matter. 4276adfc5217SJeff Kirsher */ 4277adfc5217SJeff Kirsher static int bnx2x_setup_rss(struct bnx2x *bp, 4278adfc5217SJeff Kirsher struct bnx2x_config_rss_params *p) 4279adfc5217SJeff Kirsher { 4280adfc5217SJeff Kirsher struct bnx2x_rss_config_obj *o = p->rss_obj; 4281adfc5217SJeff Kirsher struct bnx2x_raw_obj *r = &o->raw; 4282adfc5217SJeff Kirsher struct eth_rss_update_ramrod_data *data = 4283adfc5217SJeff Kirsher (struct eth_rss_update_ramrod_data *)(r->rdata); 4284adfc5217SJeff Kirsher u8 rss_mode = 0; 4285adfc5217SJeff Kirsher int rc; 4286adfc5217SJeff Kirsher 4287adfc5217SJeff Kirsher memset(data, 0, sizeof(*data)); 4288adfc5217SJeff Kirsher 4289adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "Configuring RSS\n"); 4290adfc5217SJeff Kirsher 4291adfc5217SJeff Kirsher /* Set an echo field */ 429286564c3fSYuval Mintz data->echo = cpu_to_le32((r->cid & BNX2X_SWCID_MASK) | 429386564c3fSYuval Mintz (r->state << BNX2X_SWCID_SHIFT)); 4294adfc5217SJeff Kirsher 4295adfc5217SJeff Kirsher /* RSS mode */ 4296adfc5217SJeff Kirsher if (test_bit(BNX2X_RSS_MODE_DISABLED, &p->rss_flags)) 4297adfc5217SJeff Kirsher rss_mode = ETH_RSS_MODE_DISABLED; 4298adfc5217SJeff Kirsher else if (test_bit(BNX2X_RSS_MODE_REGULAR, &p->rss_flags)) 4299adfc5217SJeff Kirsher rss_mode = ETH_RSS_MODE_REGULAR; 4300adfc5217SJeff Kirsher 4301adfc5217SJeff Kirsher data->rss_mode = rss_mode; 4302adfc5217SJeff Kirsher 4303adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "rss_mode=%d\n", rss_mode); 4304adfc5217SJeff Kirsher 4305adfc5217SJeff Kirsher /* RSS capabilities */ 4306adfc5217SJeff Kirsher if (test_bit(BNX2X_RSS_IPV4, &p->rss_flags)) 4307adfc5217SJeff Kirsher data->capabilities |= 4308adfc5217SJeff Kirsher ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY; 4309adfc5217SJeff Kirsher 4310adfc5217SJeff Kirsher if (test_bit(BNX2X_RSS_IPV4_TCP, &p->rss_flags)) 4311adfc5217SJeff Kirsher data->capabilities |= 4312adfc5217SJeff Kirsher ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY; 4313adfc5217SJeff Kirsher 43145d317c6aSMerav Sicron if (test_bit(BNX2X_RSS_IPV4_UDP, &p->rss_flags)) 43155d317c6aSMerav Sicron data->capabilities |= 43165d317c6aSMerav Sicron ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY; 43175d317c6aSMerav Sicron 4318adfc5217SJeff Kirsher if (test_bit(BNX2X_RSS_IPV6, &p->rss_flags)) 4319adfc5217SJeff Kirsher data->capabilities |= 4320adfc5217SJeff Kirsher ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY; 4321adfc5217SJeff Kirsher 4322adfc5217SJeff Kirsher if (test_bit(BNX2X_RSS_IPV6_TCP, &p->rss_flags)) 4323adfc5217SJeff Kirsher data->capabilities |= 4324adfc5217SJeff Kirsher ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY; 4325adfc5217SJeff Kirsher 43265d317c6aSMerav Sicron if (test_bit(BNX2X_RSS_IPV6_UDP, &p->rss_flags)) 43275d317c6aSMerav Sicron data->capabilities |= 43285d317c6aSMerav Sicron ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY; 43295d317c6aSMerav Sicron 4330adfc5217SJeff Kirsher /* Hashing mask */ 4331adfc5217SJeff Kirsher data->rss_result_mask = p->rss_result_mask; 4332adfc5217SJeff Kirsher 4333adfc5217SJeff Kirsher /* RSS engine ID */ 4334adfc5217SJeff Kirsher data->rss_engine_id = o->engine_id; 4335adfc5217SJeff Kirsher 4336adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "rss_engine_id=%d\n", data->rss_engine_id); 4337adfc5217SJeff Kirsher 4338adfc5217SJeff Kirsher /* Indirection table */ 4339adfc5217SJeff Kirsher memcpy(data->indirection_table, p->ind_table, 4340adfc5217SJeff Kirsher T_ETH_INDIRECTION_TABLE_SIZE); 4341adfc5217SJeff Kirsher 4342adfc5217SJeff Kirsher /* Remember the last configuration */ 4343adfc5217SJeff Kirsher memcpy(o->ind_table, p->ind_table, T_ETH_INDIRECTION_TABLE_SIZE); 4344adfc5217SJeff Kirsher 4345adfc5217SJeff Kirsher /* Print the indirection table */ 4346adfc5217SJeff Kirsher if (netif_msg_ifup(bp)) 4347adfc5217SJeff Kirsher bnx2x_debug_print_ind_table(bp, p); 4348adfc5217SJeff Kirsher 4349adfc5217SJeff Kirsher /* RSS keys */ 4350adfc5217SJeff Kirsher if (test_bit(BNX2X_RSS_SET_SRCH, &p->rss_flags)) { 4351adfc5217SJeff Kirsher memcpy(&data->rss_key[0], &p->rss_key[0], 4352adfc5217SJeff Kirsher sizeof(data->rss_key)); 4353adfc5217SJeff Kirsher data->capabilities |= ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY; 4354adfc5217SJeff Kirsher } 4355adfc5217SJeff Kirsher 435616a5fd92SYuval Mintz /* No need for an explicit memory barrier here as long we would 4357adfc5217SJeff Kirsher * need to ensure the ordering of writing to the SPQ element 4358adfc5217SJeff Kirsher * and updating of the SPQ producer which involves a memory 4359adfc5217SJeff Kirsher * read and we will have to put a full memory barrier there 4360adfc5217SJeff Kirsher * (inside bnx2x_sp_post()). 4361adfc5217SJeff Kirsher */ 4362adfc5217SJeff Kirsher 4363adfc5217SJeff Kirsher /* Send a ramrod */ 4364adfc5217SJeff Kirsher rc = bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_RSS_UPDATE, r->cid, 4365adfc5217SJeff Kirsher U64_HI(r->rdata_mapping), 4366adfc5217SJeff Kirsher U64_LO(r->rdata_mapping), 4367adfc5217SJeff Kirsher ETH_CONNECTION_TYPE); 4368adfc5217SJeff Kirsher 4369adfc5217SJeff Kirsher if (rc < 0) 4370adfc5217SJeff Kirsher return rc; 4371adfc5217SJeff Kirsher 4372adfc5217SJeff Kirsher return 1; 4373adfc5217SJeff Kirsher } 4374adfc5217SJeff Kirsher 4375adfc5217SJeff Kirsher void bnx2x_get_rss_ind_table(struct bnx2x_rss_config_obj *rss_obj, 4376adfc5217SJeff Kirsher u8 *ind_table) 4377adfc5217SJeff Kirsher { 4378adfc5217SJeff Kirsher memcpy(ind_table, rss_obj->ind_table, sizeof(rss_obj->ind_table)); 4379adfc5217SJeff Kirsher } 4380adfc5217SJeff Kirsher 4381adfc5217SJeff Kirsher int bnx2x_config_rss(struct bnx2x *bp, 4382adfc5217SJeff Kirsher struct bnx2x_config_rss_params *p) 4383adfc5217SJeff Kirsher { 4384adfc5217SJeff Kirsher int rc; 4385adfc5217SJeff Kirsher struct bnx2x_rss_config_obj *o = p->rss_obj; 4386adfc5217SJeff Kirsher struct bnx2x_raw_obj *r = &o->raw; 4387adfc5217SJeff Kirsher 4388adfc5217SJeff Kirsher /* Do nothing if only driver cleanup was requested */ 43895b622918SMichal Kalderon if (test_bit(RAMROD_DRV_CLR_ONLY, &p->ramrod_flags)) { 43905b622918SMichal Kalderon DP(BNX2X_MSG_SP, "Not configuring RSS ramrod_flags=%lx\n", 43915b622918SMichal Kalderon p->ramrod_flags); 4392adfc5217SJeff Kirsher return 0; 43935b622918SMichal Kalderon } 4394adfc5217SJeff Kirsher 4395adfc5217SJeff Kirsher r->set_pending(r); 4396adfc5217SJeff Kirsher 4397adfc5217SJeff Kirsher rc = o->config_rss(bp, p); 4398adfc5217SJeff Kirsher if (rc < 0) { 4399adfc5217SJeff Kirsher r->clear_pending(r); 4400adfc5217SJeff Kirsher return rc; 4401adfc5217SJeff Kirsher } 4402adfc5217SJeff Kirsher 4403adfc5217SJeff Kirsher if (test_bit(RAMROD_COMP_WAIT, &p->ramrod_flags)) 4404adfc5217SJeff Kirsher rc = r->wait_comp(bp, r); 4405adfc5217SJeff Kirsher 4406adfc5217SJeff Kirsher return rc; 4407adfc5217SJeff Kirsher } 4408adfc5217SJeff Kirsher 4409adfc5217SJeff Kirsher void bnx2x_init_rss_config_obj(struct bnx2x *bp, 4410adfc5217SJeff Kirsher struct bnx2x_rss_config_obj *rss_obj, 4411adfc5217SJeff Kirsher u8 cl_id, u32 cid, u8 func_id, u8 engine_id, 4412adfc5217SJeff Kirsher void *rdata, dma_addr_t rdata_mapping, 4413adfc5217SJeff Kirsher int state, unsigned long *pstate, 4414adfc5217SJeff Kirsher bnx2x_obj_type type) 4415adfc5217SJeff Kirsher { 4416adfc5217SJeff Kirsher bnx2x_init_raw_obj(&rss_obj->raw, cl_id, cid, func_id, rdata, 4417adfc5217SJeff Kirsher rdata_mapping, state, pstate, type); 4418adfc5217SJeff Kirsher 4419adfc5217SJeff Kirsher rss_obj->engine_id = engine_id; 4420adfc5217SJeff Kirsher rss_obj->config_rss = bnx2x_setup_rss; 4421adfc5217SJeff Kirsher } 4422adfc5217SJeff Kirsher 4423b9871bcfSAriel Elior int validate_vlan_mac(struct bnx2x *bp, 4424b9871bcfSAriel Elior struct bnx2x_vlan_mac_obj *vlan_mac) 4425b9871bcfSAriel Elior { 4426b9871bcfSAriel Elior if (!vlan_mac->get_n_elements) { 4427b9871bcfSAriel Elior BNX2X_ERR("vlan mac object was not intialized\n"); 4428b9871bcfSAriel Elior return -EINVAL; 4429b9871bcfSAriel Elior } 4430b9871bcfSAriel Elior return 0; 4431b9871bcfSAriel Elior } 4432b9871bcfSAriel Elior 4433adfc5217SJeff Kirsher /********************** Queue state object ***********************************/ 4434adfc5217SJeff Kirsher 4435adfc5217SJeff Kirsher /** 4436adfc5217SJeff Kirsher * bnx2x_queue_state_change - perform Queue state change transition 4437adfc5217SJeff Kirsher * 4438adfc5217SJeff Kirsher * @bp: device handle 4439adfc5217SJeff Kirsher * @params: parameters to perform the transition 4440adfc5217SJeff Kirsher * 4441adfc5217SJeff Kirsher * returns 0 in case of successfully completed transition, negative error 4442adfc5217SJeff Kirsher * code in case of failure, positive (EBUSY) value if there is a completion 4443adfc5217SJeff Kirsher * to that is still pending (possible only if RAMROD_COMP_WAIT is 4444adfc5217SJeff Kirsher * not set in params->ramrod_flags for asynchronous commands). 4445adfc5217SJeff Kirsher * 4446adfc5217SJeff Kirsher */ 4447adfc5217SJeff Kirsher int bnx2x_queue_state_change(struct bnx2x *bp, 4448adfc5217SJeff Kirsher struct bnx2x_queue_state_params *params) 4449adfc5217SJeff Kirsher { 4450adfc5217SJeff Kirsher struct bnx2x_queue_sp_obj *o = params->q_obj; 4451adfc5217SJeff Kirsher int rc, pending_bit; 4452adfc5217SJeff Kirsher unsigned long *pending = &o->pending; 4453adfc5217SJeff Kirsher 4454adfc5217SJeff Kirsher /* Check that the requested transition is legal */ 445504c46736SYuval Mintz rc = o->check_transition(bp, o, params); 445604c46736SYuval Mintz if (rc) { 445704c46736SYuval Mintz BNX2X_ERR("check transition returned an error. rc %d\n", rc); 4458adfc5217SJeff Kirsher return -EINVAL; 445904c46736SYuval Mintz } 4460adfc5217SJeff Kirsher 4461adfc5217SJeff Kirsher /* Set "pending" bit */ 446204c46736SYuval Mintz DP(BNX2X_MSG_SP, "pending bit was=%lx\n", o->pending); 4463adfc5217SJeff Kirsher pending_bit = o->set_pending(o, params); 446404c46736SYuval Mintz DP(BNX2X_MSG_SP, "pending bit now=%lx\n", o->pending); 4465adfc5217SJeff Kirsher 4466adfc5217SJeff Kirsher /* Don't send a command if only driver cleanup was requested */ 4467adfc5217SJeff Kirsher if (test_bit(RAMROD_DRV_CLR_ONLY, ¶ms->ramrod_flags)) 4468adfc5217SJeff Kirsher o->complete_cmd(bp, o, pending_bit); 4469adfc5217SJeff Kirsher else { 4470adfc5217SJeff Kirsher /* Send a ramrod */ 4471adfc5217SJeff Kirsher rc = o->send_cmd(bp, params); 4472adfc5217SJeff Kirsher if (rc) { 4473adfc5217SJeff Kirsher o->next_state = BNX2X_Q_STATE_MAX; 4474adfc5217SJeff Kirsher clear_bit(pending_bit, pending); 4475adfc5217SJeff Kirsher smp_mb__after_clear_bit(); 4476adfc5217SJeff Kirsher return rc; 4477adfc5217SJeff Kirsher } 4478adfc5217SJeff Kirsher 4479adfc5217SJeff Kirsher if (test_bit(RAMROD_COMP_WAIT, ¶ms->ramrod_flags)) { 4480adfc5217SJeff Kirsher rc = o->wait_comp(bp, o, pending_bit); 4481adfc5217SJeff Kirsher if (rc) 4482adfc5217SJeff Kirsher return rc; 4483adfc5217SJeff Kirsher 4484adfc5217SJeff Kirsher return 0; 4485adfc5217SJeff Kirsher } 4486adfc5217SJeff Kirsher } 4487adfc5217SJeff Kirsher 4488adfc5217SJeff Kirsher return !!test_bit(pending_bit, pending); 4489adfc5217SJeff Kirsher } 4490adfc5217SJeff Kirsher 4491adfc5217SJeff Kirsher static int bnx2x_queue_set_pending(struct bnx2x_queue_sp_obj *obj, 4492adfc5217SJeff Kirsher struct bnx2x_queue_state_params *params) 4493adfc5217SJeff Kirsher { 4494adfc5217SJeff Kirsher enum bnx2x_queue_cmd cmd = params->cmd, bit; 4495adfc5217SJeff Kirsher 4496adfc5217SJeff Kirsher /* ACTIVATE and DEACTIVATE commands are implemented on top of 4497adfc5217SJeff Kirsher * UPDATE command. 4498adfc5217SJeff Kirsher */ 4499adfc5217SJeff Kirsher if ((cmd == BNX2X_Q_CMD_ACTIVATE) || 4500adfc5217SJeff Kirsher (cmd == BNX2X_Q_CMD_DEACTIVATE)) 4501adfc5217SJeff Kirsher bit = BNX2X_Q_CMD_UPDATE; 4502adfc5217SJeff Kirsher else 4503adfc5217SJeff Kirsher bit = cmd; 4504adfc5217SJeff Kirsher 4505adfc5217SJeff Kirsher set_bit(bit, &obj->pending); 4506adfc5217SJeff Kirsher return bit; 4507adfc5217SJeff Kirsher } 4508adfc5217SJeff Kirsher 4509adfc5217SJeff Kirsher static int bnx2x_queue_wait_comp(struct bnx2x *bp, 4510adfc5217SJeff Kirsher struct bnx2x_queue_sp_obj *o, 4511adfc5217SJeff Kirsher enum bnx2x_queue_cmd cmd) 4512adfc5217SJeff Kirsher { 4513adfc5217SJeff Kirsher return bnx2x_state_wait(bp, cmd, &o->pending); 4514adfc5217SJeff Kirsher } 4515adfc5217SJeff Kirsher 4516adfc5217SJeff Kirsher /** 4517adfc5217SJeff Kirsher * bnx2x_queue_comp_cmd - complete the state change command. 4518adfc5217SJeff Kirsher * 4519adfc5217SJeff Kirsher * @bp: device handle 4520adfc5217SJeff Kirsher * @o: 4521adfc5217SJeff Kirsher * @cmd: 4522adfc5217SJeff Kirsher * 4523adfc5217SJeff Kirsher * Checks that the arrived completion is expected. 4524adfc5217SJeff Kirsher */ 4525adfc5217SJeff Kirsher static int bnx2x_queue_comp_cmd(struct bnx2x *bp, 4526adfc5217SJeff Kirsher struct bnx2x_queue_sp_obj *o, 4527adfc5217SJeff Kirsher enum bnx2x_queue_cmd cmd) 4528adfc5217SJeff Kirsher { 4529adfc5217SJeff Kirsher unsigned long cur_pending = o->pending; 4530adfc5217SJeff Kirsher 4531adfc5217SJeff Kirsher if (!test_and_clear_bit(cmd, &cur_pending)) { 453251c1a580SMerav Sicron BNX2X_ERR("Bad MC reply %d for queue %d in state %d pending 0x%lx, next_state %d\n", 453351c1a580SMerav Sicron cmd, o->cids[BNX2X_PRIMARY_CID_INDEX], 4534adfc5217SJeff Kirsher o->state, cur_pending, o->next_state); 4535adfc5217SJeff Kirsher return -EINVAL; 4536adfc5217SJeff Kirsher } 4537adfc5217SJeff Kirsher 4538adfc5217SJeff Kirsher if (o->next_tx_only >= o->max_cos) 453916a5fd92SYuval Mintz /* >= because tx only must always be smaller than cos since the 454002582e9bSMasanari Iida * primary connection supports COS 0 4541adfc5217SJeff Kirsher */ 4542adfc5217SJeff Kirsher BNX2X_ERR("illegal value for next tx_only: %d. max cos was %d", 4543adfc5217SJeff Kirsher o->next_tx_only, o->max_cos); 4544adfc5217SJeff Kirsher 454551c1a580SMerav Sicron DP(BNX2X_MSG_SP, 454651c1a580SMerav Sicron "Completing command %d for queue %d, setting state to %d\n", 454751c1a580SMerav Sicron cmd, o->cids[BNX2X_PRIMARY_CID_INDEX], o->next_state); 4548adfc5217SJeff Kirsher 4549adfc5217SJeff Kirsher if (o->next_tx_only) /* print num tx-only if any exist */ 455094f05b0fSJoe Perches DP(BNX2X_MSG_SP, "primary cid %d: num tx-only cons %d\n", 4551adfc5217SJeff Kirsher o->cids[BNX2X_PRIMARY_CID_INDEX], o->next_tx_only); 4552adfc5217SJeff Kirsher 4553adfc5217SJeff Kirsher o->state = o->next_state; 4554adfc5217SJeff Kirsher o->num_tx_only = o->next_tx_only; 4555adfc5217SJeff Kirsher o->next_state = BNX2X_Q_STATE_MAX; 4556adfc5217SJeff Kirsher 4557adfc5217SJeff Kirsher /* It's important that o->state and o->next_state are 4558adfc5217SJeff Kirsher * updated before o->pending. 4559adfc5217SJeff Kirsher */ 4560adfc5217SJeff Kirsher wmb(); 4561adfc5217SJeff Kirsher 4562adfc5217SJeff Kirsher clear_bit(cmd, &o->pending); 4563adfc5217SJeff Kirsher smp_mb__after_clear_bit(); 4564adfc5217SJeff Kirsher 4565adfc5217SJeff Kirsher return 0; 4566adfc5217SJeff Kirsher } 4567adfc5217SJeff Kirsher 4568adfc5217SJeff Kirsher static void bnx2x_q_fill_setup_data_e2(struct bnx2x *bp, 4569adfc5217SJeff Kirsher struct bnx2x_queue_state_params *cmd_params, 4570adfc5217SJeff Kirsher struct client_init_ramrod_data *data) 4571adfc5217SJeff Kirsher { 4572adfc5217SJeff Kirsher struct bnx2x_queue_setup_params *params = &cmd_params->params.setup; 4573adfc5217SJeff Kirsher 4574adfc5217SJeff Kirsher /* Rx data */ 4575adfc5217SJeff Kirsher 4576adfc5217SJeff Kirsher /* IPv6 TPA supported for E2 and above only */ 4577adfc5217SJeff Kirsher data->rx.tpa_en |= test_bit(BNX2X_Q_FLG_TPA_IPV6, ¶ms->flags) * 4578adfc5217SJeff Kirsher CLIENT_INIT_RX_DATA_TPA_EN_IPV6; 4579adfc5217SJeff Kirsher } 4580adfc5217SJeff Kirsher 4581adfc5217SJeff Kirsher static void bnx2x_q_fill_init_general_data(struct bnx2x *bp, 4582adfc5217SJeff Kirsher struct bnx2x_queue_sp_obj *o, 4583adfc5217SJeff Kirsher struct bnx2x_general_setup_params *params, 4584adfc5217SJeff Kirsher struct client_init_general_data *gen_data, 4585adfc5217SJeff Kirsher unsigned long *flags) 4586adfc5217SJeff Kirsher { 4587adfc5217SJeff Kirsher gen_data->client_id = o->cl_id; 4588adfc5217SJeff Kirsher 4589adfc5217SJeff Kirsher if (test_bit(BNX2X_Q_FLG_STATS, flags)) { 4590adfc5217SJeff Kirsher gen_data->statistics_counter_id = 4591adfc5217SJeff Kirsher params->stat_id; 4592adfc5217SJeff Kirsher gen_data->statistics_en_flg = 1; 4593adfc5217SJeff Kirsher gen_data->statistics_zero_flg = 4594adfc5217SJeff Kirsher test_bit(BNX2X_Q_FLG_ZERO_STATS, flags); 4595adfc5217SJeff Kirsher } else 4596adfc5217SJeff Kirsher gen_data->statistics_counter_id = 4597adfc5217SJeff Kirsher DISABLE_STATISTIC_COUNTER_ID_VALUE; 4598adfc5217SJeff Kirsher 4599adfc5217SJeff Kirsher gen_data->is_fcoe_flg = test_bit(BNX2X_Q_FLG_FCOE, flags); 4600adfc5217SJeff Kirsher gen_data->activate_flg = test_bit(BNX2X_Q_FLG_ACTIVE, flags); 4601adfc5217SJeff Kirsher gen_data->sp_client_id = params->spcl_id; 4602adfc5217SJeff Kirsher gen_data->mtu = cpu_to_le16(params->mtu); 4603adfc5217SJeff Kirsher gen_data->func_id = o->func_id; 4604adfc5217SJeff Kirsher 4605adfc5217SJeff Kirsher gen_data->cos = params->cos; 4606adfc5217SJeff Kirsher 4607adfc5217SJeff Kirsher gen_data->traffic_type = 4608adfc5217SJeff Kirsher test_bit(BNX2X_Q_FLG_FCOE, flags) ? 4609adfc5217SJeff Kirsher LLFC_TRAFFIC_TYPE_FCOE : LLFC_TRAFFIC_TYPE_NW; 4610adfc5217SJeff Kirsher 461194f05b0fSJoe Perches DP(BNX2X_MSG_SP, "flags: active %d, cos %d, stats en %d\n", 4612adfc5217SJeff Kirsher gen_data->activate_flg, gen_data->cos, gen_data->statistics_en_flg); 4613adfc5217SJeff Kirsher } 4614adfc5217SJeff Kirsher 4615adfc5217SJeff Kirsher static void bnx2x_q_fill_init_tx_data(struct bnx2x_queue_sp_obj *o, 4616adfc5217SJeff Kirsher struct bnx2x_txq_setup_params *params, 4617adfc5217SJeff Kirsher struct client_init_tx_data *tx_data, 4618adfc5217SJeff Kirsher unsigned long *flags) 4619adfc5217SJeff Kirsher { 4620adfc5217SJeff Kirsher tx_data->enforce_security_flg = 4621adfc5217SJeff Kirsher test_bit(BNX2X_Q_FLG_TX_SEC, flags); 4622adfc5217SJeff Kirsher tx_data->default_vlan = 4623adfc5217SJeff Kirsher cpu_to_le16(params->default_vlan); 4624adfc5217SJeff Kirsher tx_data->default_vlan_flg = 4625adfc5217SJeff Kirsher test_bit(BNX2X_Q_FLG_DEF_VLAN, flags); 4626adfc5217SJeff Kirsher tx_data->tx_switching_flg = 4627adfc5217SJeff Kirsher test_bit(BNX2X_Q_FLG_TX_SWITCH, flags); 4628adfc5217SJeff Kirsher tx_data->anti_spoofing_flg = 4629adfc5217SJeff Kirsher test_bit(BNX2X_Q_FLG_ANTI_SPOOF, flags); 4630a3348722SBarak Witkowski tx_data->force_default_pri_flg = 4631a3348722SBarak Witkowski test_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI, flags); 4632a3348722SBarak Witkowski 4633e287a75cSDmitry Kravkov tx_data->tunnel_lso_inc_ip_id = 4634e287a75cSDmitry Kravkov test_bit(BNX2X_Q_FLG_TUN_INC_INNER_IP_ID, flags); 463591226790SDmitry Kravkov tx_data->tunnel_non_lso_pcsum_location = 463691226790SDmitry Kravkov test_bit(BNX2X_Q_FLG_PCSUM_ON_PKT, flags) ? PCSUM_ON_PKT : 463791226790SDmitry Kravkov PCSUM_ON_BD; 463891226790SDmitry Kravkov 4639adfc5217SJeff Kirsher tx_data->tx_status_block_id = params->fw_sb_id; 4640adfc5217SJeff Kirsher tx_data->tx_sb_index_number = params->sb_cq_index; 4641adfc5217SJeff Kirsher tx_data->tss_leading_client_id = params->tss_leading_cl_id; 4642adfc5217SJeff Kirsher 4643adfc5217SJeff Kirsher tx_data->tx_bd_page_base.lo = 4644adfc5217SJeff Kirsher cpu_to_le32(U64_LO(params->dscr_map)); 4645adfc5217SJeff Kirsher tx_data->tx_bd_page_base.hi = 4646adfc5217SJeff Kirsher cpu_to_le32(U64_HI(params->dscr_map)); 4647adfc5217SJeff Kirsher 4648adfc5217SJeff Kirsher /* Don't configure any Tx switching mode during queue SETUP */ 4649adfc5217SJeff Kirsher tx_data->state = 0; 4650adfc5217SJeff Kirsher } 4651adfc5217SJeff Kirsher 4652adfc5217SJeff Kirsher static void bnx2x_q_fill_init_pause_data(struct bnx2x_queue_sp_obj *o, 4653adfc5217SJeff Kirsher struct rxq_pause_params *params, 4654adfc5217SJeff Kirsher struct client_init_rx_data *rx_data) 4655adfc5217SJeff Kirsher { 4656adfc5217SJeff Kirsher /* flow control data */ 4657adfc5217SJeff Kirsher rx_data->cqe_pause_thr_low = cpu_to_le16(params->rcq_th_lo); 4658adfc5217SJeff Kirsher rx_data->cqe_pause_thr_high = cpu_to_le16(params->rcq_th_hi); 4659adfc5217SJeff Kirsher rx_data->bd_pause_thr_low = cpu_to_le16(params->bd_th_lo); 4660adfc5217SJeff Kirsher rx_data->bd_pause_thr_high = cpu_to_le16(params->bd_th_hi); 4661adfc5217SJeff Kirsher rx_data->sge_pause_thr_low = cpu_to_le16(params->sge_th_lo); 4662adfc5217SJeff Kirsher rx_data->sge_pause_thr_high = cpu_to_le16(params->sge_th_hi); 4663adfc5217SJeff Kirsher rx_data->rx_cos_mask = cpu_to_le16(params->pri_map); 4664adfc5217SJeff Kirsher } 4665adfc5217SJeff Kirsher 4666adfc5217SJeff Kirsher static void bnx2x_q_fill_init_rx_data(struct bnx2x_queue_sp_obj *o, 4667adfc5217SJeff Kirsher struct bnx2x_rxq_setup_params *params, 4668adfc5217SJeff Kirsher struct client_init_rx_data *rx_data, 4669adfc5217SJeff Kirsher unsigned long *flags) 4670adfc5217SJeff Kirsher { 4671adfc5217SJeff Kirsher rx_data->tpa_en = test_bit(BNX2X_Q_FLG_TPA, flags) * 4672adfc5217SJeff Kirsher CLIENT_INIT_RX_DATA_TPA_EN_IPV4; 4673621b4d66SDmitry Kravkov rx_data->tpa_en |= test_bit(BNX2X_Q_FLG_TPA_GRO, flags) * 4674621b4d66SDmitry Kravkov CLIENT_INIT_RX_DATA_TPA_MODE; 4675adfc5217SJeff Kirsher rx_data->vmqueue_mode_en_flg = 0; 4676adfc5217SJeff Kirsher 4677adfc5217SJeff Kirsher rx_data->cache_line_alignment_log_size = 4678adfc5217SJeff Kirsher params->cache_line_log; 4679adfc5217SJeff Kirsher rx_data->enable_dynamic_hc = 4680adfc5217SJeff Kirsher test_bit(BNX2X_Q_FLG_DHC, flags); 4681adfc5217SJeff Kirsher rx_data->max_sges_for_packet = params->max_sges_pkt; 4682adfc5217SJeff Kirsher rx_data->client_qzone_id = params->cl_qzone_id; 4683adfc5217SJeff Kirsher rx_data->max_agg_size = cpu_to_le16(params->tpa_agg_sz); 4684adfc5217SJeff Kirsher 4685adfc5217SJeff Kirsher /* Always start in DROP_ALL mode */ 4686adfc5217SJeff Kirsher rx_data->state = cpu_to_le16(CLIENT_INIT_RX_DATA_UCAST_DROP_ALL | 4687adfc5217SJeff Kirsher CLIENT_INIT_RX_DATA_MCAST_DROP_ALL); 4688adfc5217SJeff Kirsher 4689adfc5217SJeff Kirsher /* We don't set drop flags */ 4690adfc5217SJeff Kirsher rx_data->drop_ip_cs_err_flg = 0; 4691adfc5217SJeff Kirsher rx_data->drop_tcp_cs_err_flg = 0; 4692adfc5217SJeff Kirsher rx_data->drop_ttl0_flg = 0; 4693adfc5217SJeff Kirsher rx_data->drop_udp_cs_err_flg = 0; 4694adfc5217SJeff Kirsher rx_data->inner_vlan_removal_enable_flg = 4695adfc5217SJeff Kirsher test_bit(BNX2X_Q_FLG_VLAN, flags); 4696adfc5217SJeff Kirsher rx_data->outer_vlan_removal_enable_flg = 4697adfc5217SJeff Kirsher test_bit(BNX2X_Q_FLG_OV, flags); 4698adfc5217SJeff Kirsher rx_data->status_block_id = params->fw_sb_id; 4699adfc5217SJeff Kirsher rx_data->rx_sb_index_number = params->sb_cq_index; 4700adfc5217SJeff Kirsher rx_data->max_tpa_queues = params->max_tpa_queues; 4701adfc5217SJeff Kirsher rx_data->max_bytes_on_bd = cpu_to_le16(params->buf_sz); 4702adfc5217SJeff Kirsher rx_data->sge_buff_size = cpu_to_le16(params->sge_buf_sz); 4703adfc5217SJeff Kirsher rx_data->bd_page_base.lo = 4704adfc5217SJeff Kirsher cpu_to_le32(U64_LO(params->dscr_map)); 4705adfc5217SJeff Kirsher rx_data->bd_page_base.hi = 4706adfc5217SJeff Kirsher cpu_to_le32(U64_HI(params->dscr_map)); 4707adfc5217SJeff Kirsher rx_data->sge_page_base.lo = 4708adfc5217SJeff Kirsher cpu_to_le32(U64_LO(params->sge_map)); 4709adfc5217SJeff Kirsher rx_data->sge_page_base.hi = 4710adfc5217SJeff Kirsher cpu_to_le32(U64_HI(params->sge_map)); 4711adfc5217SJeff Kirsher rx_data->cqe_page_base.lo = 4712adfc5217SJeff Kirsher cpu_to_le32(U64_LO(params->rcq_map)); 4713adfc5217SJeff Kirsher rx_data->cqe_page_base.hi = 4714adfc5217SJeff Kirsher cpu_to_le32(U64_HI(params->rcq_map)); 4715adfc5217SJeff Kirsher rx_data->is_leading_rss = test_bit(BNX2X_Q_FLG_LEADING_RSS, flags); 4716adfc5217SJeff Kirsher 4717adfc5217SJeff Kirsher if (test_bit(BNX2X_Q_FLG_MCAST, flags)) { 4718259afa1fSYuval Mintz rx_data->approx_mcast_engine_id = params->mcast_engine_id; 4719adfc5217SJeff Kirsher rx_data->is_approx_mcast = 1; 4720adfc5217SJeff Kirsher } 4721adfc5217SJeff Kirsher 4722adfc5217SJeff Kirsher rx_data->rss_engine_id = params->rss_engine_id; 4723adfc5217SJeff Kirsher 4724adfc5217SJeff Kirsher /* silent vlan removal */ 4725adfc5217SJeff Kirsher rx_data->silent_vlan_removal_flg = 4726adfc5217SJeff Kirsher test_bit(BNX2X_Q_FLG_SILENT_VLAN_REM, flags); 4727adfc5217SJeff Kirsher rx_data->silent_vlan_value = 4728adfc5217SJeff Kirsher cpu_to_le16(params->silent_removal_value); 4729adfc5217SJeff Kirsher rx_data->silent_vlan_mask = 4730adfc5217SJeff Kirsher cpu_to_le16(params->silent_removal_mask); 4731adfc5217SJeff Kirsher } 4732adfc5217SJeff Kirsher 4733adfc5217SJeff Kirsher /* initialize the general, tx and rx parts of a queue object */ 4734adfc5217SJeff Kirsher static void bnx2x_q_fill_setup_data_cmn(struct bnx2x *bp, 4735adfc5217SJeff Kirsher struct bnx2x_queue_state_params *cmd_params, 4736adfc5217SJeff Kirsher struct client_init_ramrod_data *data) 4737adfc5217SJeff Kirsher { 4738adfc5217SJeff Kirsher bnx2x_q_fill_init_general_data(bp, cmd_params->q_obj, 4739adfc5217SJeff Kirsher &cmd_params->params.setup.gen_params, 4740adfc5217SJeff Kirsher &data->general, 4741adfc5217SJeff Kirsher &cmd_params->params.setup.flags); 4742adfc5217SJeff Kirsher 4743adfc5217SJeff Kirsher bnx2x_q_fill_init_tx_data(cmd_params->q_obj, 4744adfc5217SJeff Kirsher &cmd_params->params.setup.txq_params, 4745adfc5217SJeff Kirsher &data->tx, 4746adfc5217SJeff Kirsher &cmd_params->params.setup.flags); 4747adfc5217SJeff Kirsher 4748adfc5217SJeff Kirsher bnx2x_q_fill_init_rx_data(cmd_params->q_obj, 4749adfc5217SJeff Kirsher &cmd_params->params.setup.rxq_params, 4750adfc5217SJeff Kirsher &data->rx, 4751adfc5217SJeff Kirsher &cmd_params->params.setup.flags); 4752adfc5217SJeff Kirsher 4753adfc5217SJeff Kirsher bnx2x_q_fill_init_pause_data(cmd_params->q_obj, 4754adfc5217SJeff Kirsher &cmd_params->params.setup.pause_params, 4755adfc5217SJeff Kirsher &data->rx); 4756adfc5217SJeff Kirsher } 4757adfc5217SJeff Kirsher 4758adfc5217SJeff Kirsher /* initialize the general and tx parts of a tx-only queue object */ 4759adfc5217SJeff Kirsher static void bnx2x_q_fill_setup_tx_only(struct bnx2x *bp, 4760adfc5217SJeff Kirsher struct bnx2x_queue_state_params *cmd_params, 4761adfc5217SJeff Kirsher struct tx_queue_init_ramrod_data *data) 4762adfc5217SJeff Kirsher { 4763adfc5217SJeff Kirsher bnx2x_q_fill_init_general_data(bp, cmd_params->q_obj, 4764adfc5217SJeff Kirsher &cmd_params->params.tx_only.gen_params, 4765adfc5217SJeff Kirsher &data->general, 4766adfc5217SJeff Kirsher &cmd_params->params.tx_only.flags); 4767adfc5217SJeff Kirsher 4768adfc5217SJeff Kirsher bnx2x_q_fill_init_tx_data(cmd_params->q_obj, 4769adfc5217SJeff Kirsher &cmd_params->params.tx_only.txq_params, 4770adfc5217SJeff Kirsher &data->tx, 4771adfc5217SJeff Kirsher &cmd_params->params.tx_only.flags); 4772adfc5217SJeff Kirsher 477351c1a580SMerav Sicron DP(BNX2X_MSG_SP, "cid %d, tx bd page lo %x hi %x", 477451c1a580SMerav Sicron cmd_params->q_obj->cids[0], 477551c1a580SMerav Sicron data->tx.tx_bd_page_base.lo, 477651c1a580SMerav Sicron data->tx.tx_bd_page_base.hi); 4777adfc5217SJeff Kirsher } 4778adfc5217SJeff Kirsher 4779adfc5217SJeff Kirsher /** 4780adfc5217SJeff Kirsher * bnx2x_q_init - init HW/FW queue 4781adfc5217SJeff Kirsher * 4782adfc5217SJeff Kirsher * @bp: device handle 4783adfc5217SJeff Kirsher * @params: 4784adfc5217SJeff Kirsher * 4785adfc5217SJeff Kirsher * HW/FW initial Queue configuration: 4786adfc5217SJeff Kirsher * - HC: Rx and Tx 4787adfc5217SJeff Kirsher * - CDU context validation 4788adfc5217SJeff Kirsher * 4789adfc5217SJeff Kirsher */ 4790adfc5217SJeff Kirsher static inline int bnx2x_q_init(struct bnx2x *bp, 4791adfc5217SJeff Kirsher struct bnx2x_queue_state_params *params) 4792adfc5217SJeff Kirsher { 4793adfc5217SJeff Kirsher struct bnx2x_queue_sp_obj *o = params->q_obj; 4794adfc5217SJeff Kirsher struct bnx2x_queue_init_params *init = ¶ms->params.init; 4795adfc5217SJeff Kirsher u16 hc_usec; 4796adfc5217SJeff Kirsher u8 cos; 4797adfc5217SJeff Kirsher 4798adfc5217SJeff Kirsher /* Tx HC configuration */ 4799adfc5217SJeff Kirsher if (test_bit(BNX2X_Q_TYPE_HAS_TX, &o->type) && 4800adfc5217SJeff Kirsher test_bit(BNX2X_Q_FLG_HC, &init->tx.flags)) { 4801adfc5217SJeff Kirsher hc_usec = init->tx.hc_rate ? 1000000 / init->tx.hc_rate : 0; 4802adfc5217SJeff Kirsher 4803adfc5217SJeff Kirsher bnx2x_update_coalesce_sb_index(bp, init->tx.fw_sb_id, 4804adfc5217SJeff Kirsher init->tx.sb_cq_index, 4805adfc5217SJeff Kirsher !test_bit(BNX2X_Q_FLG_HC_EN, &init->tx.flags), 4806adfc5217SJeff Kirsher hc_usec); 4807adfc5217SJeff Kirsher } 4808adfc5217SJeff Kirsher 4809adfc5217SJeff Kirsher /* Rx HC configuration */ 4810adfc5217SJeff Kirsher if (test_bit(BNX2X_Q_TYPE_HAS_RX, &o->type) && 4811adfc5217SJeff Kirsher test_bit(BNX2X_Q_FLG_HC, &init->rx.flags)) { 4812adfc5217SJeff Kirsher hc_usec = init->rx.hc_rate ? 1000000 / init->rx.hc_rate : 0; 4813adfc5217SJeff Kirsher 4814adfc5217SJeff Kirsher bnx2x_update_coalesce_sb_index(bp, init->rx.fw_sb_id, 4815adfc5217SJeff Kirsher init->rx.sb_cq_index, 4816adfc5217SJeff Kirsher !test_bit(BNX2X_Q_FLG_HC_EN, &init->rx.flags), 4817adfc5217SJeff Kirsher hc_usec); 4818adfc5217SJeff Kirsher } 4819adfc5217SJeff Kirsher 4820adfc5217SJeff Kirsher /* Set CDU context validation values */ 4821adfc5217SJeff Kirsher for (cos = 0; cos < o->max_cos; cos++) { 482294f05b0fSJoe Perches DP(BNX2X_MSG_SP, "setting context validation. cid %d, cos %d\n", 4823adfc5217SJeff Kirsher o->cids[cos], cos); 482494f05b0fSJoe Perches DP(BNX2X_MSG_SP, "context pointer %p\n", init->cxts[cos]); 4825adfc5217SJeff Kirsher bnx2x_set_ctx_validation(bp, init->cxts[cos], o->cids[cos]); 4826adfc5217SJeff Kirsher } 4827adfc5217SJeff Kirsher 4828adfc5217SJeff Kirsher /* As no ramrod is sent, complete the command immediately */ 4829adfc5217SJeff Kirsher o->complete_cmd(bp, o, BNX2X_Q_CMD_INIT); 4830adfc5217SJeff Kirsher 4831adfc5217SJeff Kirsher mmiowb(); 4832adfc5217SJeff Kirsher smp_mb(); 4833adfc5217SJeff Kirsher 4834adfc5217SJeff Kirsher return 0; 4835adfc5217SJeff Kirsher } 4836adfc5217SJeff Kirsher 4837adfc5217SJeff Kirsher static inline int bnx2x_q_send_setup_e1x(struct bnx2x *bp, 4838adfc5217SJeff Kirsher struct bnx2x_queue_state_params *params) 4839adfc5217SJeff Kirsher { 4840adfc5217SJeff Kirsher struct bnx2x_queue_sp_obj *o = params->q_obj; 4841adfc5217SJeff Kirsher struct client_init_ramrod_data *rdata = 4842adfc5217SJeff Kirsher (struct client_init_ramrod_data *)o->rdata; 4843adfc5217SJeff Kirsher dma_addr_t data_mapping = o->rdata_mapping; 4844adfc5217SJeff Kirsher int ramrod = RAMROD_CMD_ID_ETH_CLIENT_SETUP; 4845adfc5217SJeff Kirsher 4846adfc5217SJeff Kirsher /* Clear the ramrod data */ 4847adfc5217SJeff Kirsher memset(rdata, 0, sizeof(*rdata)); 4848adfc5217SJeff Kirsher 4849adfc5217SJeff Kirsher /* Fill the ramrod data */ 4850adfc5217SJeff Kirsher bnx2x_q_fill_setup_data_cmn(bp, params, rdata); 4851adfc5217SJeff Kirsher 485216a5fd92SYuval Mintz /* No need for an explicit memory barrier here as long we would 4853adfc5217SJeff Kirsher * need to ensure the ordering of writing to the SPQ element 4854adfc5217SJeff Kirsher * and updating of the SPQ producer which involves a memory 4855adfc5217SJeff Kirsher * read and we will have to put a full memory barrier there 4856adfc5217SJeff Kirsher * (inside bnx2x_sp_post()). 4857adfc5217SJeff Kirsher */ 4858adfc5217SJeff Kirsher 4859adfc5217SJeff Kirsher return bnx2x_sp_post(bp, ramrod, o->cids[BNX2X_PRIMARY_CID_INDEX], 4860adfc5217SJeff Kirsher U64_HI(data_mapping), 4861adfc5217SJeff Kirsher U64_LO(data_mapping), ETH_CONNECTION_TYPE); 4862adfc5217SJeff Kirsher } 4863adfc5217SJeff Kirsher 4864adfc5217SJeff Kirsher static inline int bnx2x_q_send_setup_e2(struct bnx2x *bp, 4865adfc5217SJeff Kirsher struct bnx2x_queue_state_params *params) 4866adfc5217SJeff Kirsher { 4867adfc5217SJeff Kirsher struct bnx2x_queue_sp_obj *o = params->q_obj; 4868adfc5217SJeff Kirsher struct client_init_ramrod_data *rdata = 4869adfc5217SJeff Kirsher (struct client_init_ramrod_data *)o->rdata; 4870adfc5217SJeff Kirsher dma_addr_t data_mapping = o->rdata_mapping; 4871adfc5217SJeff Kirsher int ramrod = RAMROD_CMD_ID_ETH_CLIENT_SETUP; 4872adfc5217SJeff Kirsher 4873adfc5217SJeff Kirsher /* Clear the ramrod data */ 4874adfc5217SJeff Kirsher memset(rdata, 0, sizeof(*rdata)); 4875adfc5217SJeff Kirsher 4876adfc5217SJeff Kirsher /* Fill the ramrod data */ 4877adfc5217SJeff Kirsher bnx2x_q_fill_setup_data_cmn(bp, params, rdata); 4878adfc5217SJeff Kirsher bnx2x_q_fill_setup_data_e2(bp, params, rdata); 4879adfc5217SJeff Kirsher 488016a5fd92SYuval Mintz /* No need for an explicit memory barrier here as long we would 4881adfc5217SJeff Kirsher * need to ensure the ordering of writing to the SPQ element 4882adfc5217SJeff Kirsher * and updating of the SPQ producer which involves a memory 4883adfc5217SJeff Kirsher * read and we will have to put a full memory barrier there 4884adfc5217SJeff Kirsher * (inside bnx2x_sp_post()). 4885adfc5217SJeff Kirsher */ 4886adfc5217SJeff Kirsher 4887adfc5217SJeff Kirsher return bnx2x_sp_post(bp, ramrod, o->cids[BNX2X_PRIMARY_CID_INDEX], 4888adfc5217SJeff Kirsher U64_HI(data_mapping), 4889adfc5217SJeff Kirsher U64_LO(data_mapping), ETH_CONNECTION_TYPE); 4890adfc5217SJeff Kirsher } 4891adfc5217SJeff Kirsher 4892adfc5217SJeff Kirsher static inline int bnx2x_q_send_setup_tx_only(struct bnx2x *bp, 4893adfc5217SJeff Kirsher struct bnx2x_queue_state_params *params) 4894adfc5217SJeff Kirsher { 4895adfc5217SJeff Kirsher struct bnx2x_queue_sp_obj *o = params->q_obj; 4896adfc5217SJeff Kirsher struct tx_queue_init_ramrod_data *rdata = 4897adfc5217SJeff Kirsher (struct tx_queue_init_ramrod_data *)o->rdata; 4898adfc5217SJeff Kirsher dma_addr_t data_mapping = o->rdata_mapping; 4899adfc5217SJeff Kirsher int ramrod = RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP; 4900adfc5217SJeff Kirsher struct bnx2x_queue_setup_tx_only_params *tx_only_params = 4901adfc5217SJeff Kirsher ¶ms->params.tx_only; 4902adfc5217SJeff Kirsher u8 cid_index = tx_only_params->cid_index; 4903adfc5217SJeff Kirsher 4904adfc5217SJeff Kirsher if (cid_index >= o->max_cos) { 4905adfc5217SJeff Kirsher BNX2X_ERR("queue[%d]: cid_index (%d) is out of range\n", 4906adfc5217SJeff Kirsher o->cl_id, cid_index); 4907adfc5217SJeff Kirsher return -EINVAL; 4908adfc5217SJeff Kirsher } 4909adfc5217SJeff Kirsher 491094f05b0fSJoe Perches DP(BNX2X_MSG_SP, "parameters received: cos: %d sp-id: %d\n", 4911adfc5217SJeff Kirsher tx_only_params->gen_params.cos, 4912adfc5217SJeff Kirsher tx_only_params->gen_params.spcl_id); 4913adfc5217SJeff Kirsher 4914adfc5217SJeff Kirsher /* Clear the ramrod data */ 4915adfc5217SJeff Kirsher memset(rdata, 0, sizeof(*rdata)); 4916adfc5217SJeff Kirsher 4917adfc5217SJeff Kirsher /* Fill the ramrod data */ 4918adfc5217SJeff Kirsher bnx2x_q_fill_setup_tx_only(bp, params, rdata); 4919adfc5217SJeff Kirsher 492051c1a580SMerav Sicron DP(BNX2X_MSG_SP, "sending tx-only ramrod: cid %d, client-id %d, sp-client id %d, cos %d\n", 492151c1a580SMerav Sicron o->cids[cid_index], rdata->general.client_id, 4922adfc5217SJeff Kirsher rdata->general.sp_client_id, rdata->general.cos); 4923adfc5217SJeff Kirsher 492416a5fd92SYuval Mintz /* No need for an explicit memory barrier here as long we would 4925adfc5217SJeff Kirsher * need to ensure the ordering of writing to the SPQ element 4926adfc5217SJeff Kirsher * and updating of the SPQ producer which involves a memory 4927adfc5217SJeff Kirsher * read and we will have to put a full memory barrier there 4928adfc5217SJeff Kirsher * (inside bnx2x_sp_post()). 4929adfc5217SJeff Kirsher */ 4930adfc5217SJeff Kirsher 4931adfc5217SJeff Kirsher return bnx2x_sp_post(bp, ramrod, o->cids[cid_index], 4932adfc5217SJeff Kirsher U64_HI(data_mapping), 4933adfc5217SJeff Kirsher U64_LO(data_mapping), ETH_CONNECTION_TYPE); 4934adfc5217SJeff Kirsher } 4935adfc5217SJeff Kirsher 4936adfc5217SJeff Kirsher static void bnx2x_q_fill_update_data(struct bnx2x *bp, 4937adfc5217SJeff Kirsher struct bnx2x_queue_sp_obj *obj, 4938adfc5217SJeff Kirsher struct bnx2x_queue_update_params *params, 4939adfc5217SJeff Kirsher struct client_update_ramrod_data *data) 4940adfc5217SJeff Kirsher { 4941adfc5217SJeff Kirsher /* Client ID of the client to update */ 4942adfc5217SJeff Kirsher data->client_id = obj->cl_id; 4943adfc5217SJeff Kirsher 4944adfc5217SJeff Kirsher /* Function ID of the client to update */ 4945adfc5217SJeff Kirsher data->func_id = obj->func_id; 4946adfc5217SJeff Kirsher 4947adfc5217SJeff Kirsher /* Default VLAN value */ 4948adfc5217SJeff Kirsher data->default_vlan = cpu_to_le16(params->def_vlan); 4949adfc5217SJeff Kirsher 4950adfc5217SJeff Kirsher /* Inner VLAN stripping */ 4951adfc5217SJeff Kirsher data->inner_vlan_removal_enable_flg = 4952adfc5217SJeff Kirsher test_bit(BNX2X_Q_UPDATE_IN_VLAN_REM, ¶ms->update_flags); 4953adfc5217SJeff Kirsher data->inner_vlan_removal_change_flg = 4954adfc5217SJeff Kirsher test_bit(BNX2X_Q_UPDATE_IN_VLAN_REM_CHNG, 4955adfc5217SJeff Kirsher ¶ms->update_flags); 4956adfc5217SJeff Kirsher 495716a5fd92SYuval Mintz /* Outer VLAN stripping */ 4958adfc5217SJeff Kirsher data->outer_vlan_removal_enable_flg = 4959adfc5217SJeff Kirsher test_bit(BNX2X_Q_UPDATE_OUT_VLAN_REM, ¶ms->update_flags); 4960adfc5217SJeff Kirsher data->outer_vlan_removal_change_flg = 4961adfc5217SJeff Kirsher test_bit(BNX2X_Q_UPDATE_OUT_VLAN_REM_CHNG, 4962adfc5217SJeff Kirsher ¶ms->update_flags); 4963adfc5217SJeff Kirsher 4964adfc5217SJeff Kirsher /* Drop packets that have source MAC that doesn't belong to this 4965adfc5217SJeff Kirsher * Queue. 4966adfc5217SJeff Kirsher */ 4967adfc5217SJeff Kirsher data->anti_spoofing_enable_flg = 4968adfc5217SJeff Kirsher test_bit(BNX2X_Q_UPDATE_ANTI_SPOOF, ¶ms->update_flags); 4969adfc5217SJeff Kirsher data->anti_spoofing_change_flg = 4970adfc5217SJeff Kirsher test_bit(BNX2X_Q_UPDATE_ANTI_SPOOF_CHNG, ¶ms->update_flags); 4971adfc5217SJeff Kirsher 4972adfc5217SJeff Kirsher /* Activate/Deactivate */ 4973adfc5217SJeff Kirsher data->activate_flg = 4974adfc5217SJeff Kirsher test_bit(BNX2X_Q_UPDATE_ACTIVATE, ¶ms->update_flags); 4975adfc5217SJeff Kirsher data->activate_change_flg = 4976adfc5217SJeff Kirsher test_bit(BNX2X_Q_UPDATE_ACTIVATE_CHNG, ¶ms->update_flags); 4977adfc5217SJeff Kirsher 4978adfc5217SJeff Kirsher /* Enable default VLAN */ 4979adfc5217SJeff Kirsher data->default_vlan_enable_flg = 4980adfc5217SJeff Kirsher test_bit(BNX2X_Q_UPDATE_DEF_VLAN_EN, ¶ms->update_flags); 4981adfc5217SJeff Kirsher data->default_vlan_change_flg = 4982adfc5217SJeff Kirsher test_bit(BNX2X_Q_UPDATE_DEF_VLAN_EN_CHNG, 4983adfc5217SJeff Kirsher ¶ms->update_flags); 4984adfc5217SJeff Kirsher 4985adfc5217SJeff Kirsher /* silent vlan removal */ 4986adfc5217SJeff Kirsher data->silent_vlan_change_flg = 4987adfc5217SJeff Kirsher test_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG, 4988adfc5217SJeff Kirsher ¶ms->update_flags); 4989adfc5217SJeff Kirsher data->silent_vlan_removal_flg = 4990adfc5217SJeff Kirsher test_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM, ¶ms->update_flags); 4991adfc5217SJeff Kirsher data->silent_vlan_value = cpu_to_le16(params->silent_removal_value); 4992adfc5217SJeff Kirsher data->silent_vlan_mask = cpu_to_le16(params->silent_removal_mask); 4993adfc5217SJeff Kirsher } 4994adfc5217SJeff Kirsher 4995adfc5217SJeff Kirsher static inline int bnx2x_q_send_update(struct bnx2x *bp, 4996adfc5217SJeff Kirsher struct bnx2x_queue_state_params *params) 4997adfc5217SJeff Kirsher { 4998adfc5217SJeff Kirsher struct bnx2x_queue_sp_obj *o = params->q_obj; 4999adfc5217SJeff Kirsher struct client_update_ramrod_data *rdata = 5000adfc5217SJeff Kirsher (struct client_update_ramrod_data *)o->rdata; 5001adfc5217SJeff Kirsher dma_addr_t data_mapping = o->rdata_mapping; 5002adfc5217SJeff Kirsher struct bnx2x_queue_update_params *update_params = 5003adfc5217SJeff Kirsher ¶ms->params.update; 5004adfc5217SJeff Kirsher u8 cid_index = update_params->cid_index; 5005adfc5217SJeff Kirsher 5006adfc5217SJeff Kirsher if (cid_index >= o->max_cos) { 5007adfc5217SJeff Kirsher BNX2X_ERR("queue[%d]: cid_index (%d) is out of range\n", 5008adfc5217SJeff Kirsher o->cl_id, cid_index); 5009adfc5217SJeff Kirsher return -EINVAL; 5010adfc5217SJeff Kirsher } 5011adfc5217SJeff Kirsher 5012adfc5217SJeff Kirsher /* Clear the ramrod data */ 5013adfc5217SJeff Kirsher memset(rdata, 0, sizeof(*rdata)); 5014adfc5217SJeff Kirsher 5015adfc5217SJeff Kirsher /* Fill the ramrod data */ 5016adfc5217SJeff Kirsher bnx2x_q_fill_update_data(bp, o, update_params, rdata); 5017adfc5217SJeff Kirsher 501816a5fd92SYuval Mintz /* No need for an explicit memory barrier here as long we would 5019adfc5217SJeff Kirsher * need to ensure the ordering of writing to the SPQ element 5020adfc5217SJeff Kirsher * and updating of the SPQ producer which involves a memory 5021adfc5217SJeff Kirsher * read and we will have to put a full memory barrier there 5022adfc5217SJeff Kirsher * (inside bnx2x_sp_post()). 5023adfc5217SJeff Kirsher */ 5024adfc5217SJeff Kirsher 5025adfc5217SJeff Kirsher return bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_CLIENT_UPDATE, 5026adfc5217SJeff Kirsher o->cids[cid_index], U64_HI(data_mapping), 5027adfc5217SJeff Kirsher U64_LO(data_mapping), ETH_CONNECTION_TYPE); 5028adfc5217SJeff Kirsher } 5029adfc5217SJeff Kirsher 5030adfc5217SJeff Kirsher /** 5031adfc5217SJeff Kirsher * bnx2x_q_send_deactivate - send DEACTIVATE command 5032adfc5217SJeff Kirsher * 5033adfc5217SJeff Kirsher * @bp: device handle 5034adfc5217SJeff Kirsher * @params: 5035adfc5217SJeff Kirsher * 5036adfc5217SJeff Kirsher * implemented using the UPDATE command. 5037adfc5217SJeff Kirsher */ 5038adfc5217SJeff Kirsher static inline int bnx2x_q_send_deactivate(struct bnx2x *bp, 5039adfc5217SJeff Kirsher struct bnx2x_queue_state_params *params) 5040adfc5217SJeff Kirsher { 5041adfc5217SJeff Kirsher struct bnx2x_queue_update_params *update = ¶ms->params.update; 5042adfc5217SJeff Kirsher 5043adfc5217SJeff Kirsher memset(update, 0, sizeof(*update)); 5044adfc5217SJeff Kirsher 5045adfc5217SJeff Kirsher __set_bit(BNX2X_Q_UPDATE_ACTIVATE_CHNG, &update->update_flags); 5046adfc5217SJeff Kirsher 5047adfc5217SJeff Kirsher return bnx2x_q_send_update(bp, params); 5048adfc5217SJeff Kirsher } 5049adfc5217SJeff Kirsher 5050adfc5217SJeff Kirsher /** 5051adfc5217SJeff Kirsher * bnx2x_q_send_activate - send ACTIVATE command 5052adfc5217SJeff Kirsher * 5053adfc5217SJeff Kirsher * @bp: device handle 5054adfc5217SJeff Kirsher * @params: 5055adfc5217SJeff Kirsher * 5056adfc5217SJeff Kirsher * implemented using the UPDATE command. 5057adfc5217SJeff Kirsher */ 5058adfc5217SJeff Kirsher static inline int bnx2x_q_send_activate(struct bnx2x *bp, 5059adfc5217SJeff Kirsher struct bnx2x_queue_state_params *params) 5060adfc5217SJeff Kirsher { 5061adfc5217SJeff Kirsher struct bnx2x_queue_update_params *update = ¶ms->params.update; 5062adfc5217SJeff Kirsher 5063adfc5217SJeff Kirsher memset(update, 0, sizeof(*update)); 5064adfc5217SJeff Kirsher 5065adfc5217SJeff Kirsher __set_bit(BNX2X_Q_UPDATE_ACTIVATE, &update->update_flags); 5066adfc5217SJeff Kirsher __set_bit(BNX2X_Q_UPDATE_ACTIVATE_CHNG, &update->update_flags); 5067adfc5217SJeff Kirsher 5068adfc5217SJeff Kirsher return bnx2x_q_send_update(bp, params); 5069adfc5217SJeff Kirsher } 5070adfc5217SJeff Kirsher 5071adfc5217SJeff Kirsher static inline int bnx2x_q_send_update_tpa(struct bnx2x *bp, 5072adfc5217SJeff Kirsher struct bnx2x_queue_state_params *params) 5073adfc5217SJeff Kirsher { 5074adfc5217SJeff Kirsher /* TODO: Not implemented yet. */ 5075adfc5217SJeff Kirsher return -1; 5076adfc5217SJeff Kirsher } 5077adfc5217SJeff Kirsher 5078adfc5217SJeff Kirsher static inline int bnx2x_q_send_halt(struct bnx2x *bp, 5079adfc5217SJeff Kirsher struct bnx2x_queue_state_params *params) 5080adfc5217SJeff Kirsher { 5081adfc5217SJeff Kirsher struct bnx2x_queue_sp_obj *o = params->q_obj; 5082adfc5217SJeff Kirsher 5083adfc5217SJeff Kirsher return bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_HALT, 5084adfc5217SJeff Kirsher o->cids[BNX2X_PRIMARY_CID_INDEX], 0, o->cl_id, 5085adfc5217SJeff Kirsher ETH_CONNECTION_TYPE); 5086adfc5217SJeff Kirsher } 5087adfc5217SJeff Kirsher 5088adfc5217SJeff Kirsher static inline int bnx2x_q_send_cfc_del(struct bnx2x *bp, 5089adfc5217SJeff Kirsher struct bnx2x_queue_state_params *params) 5090adfc5217SJeff Kirsher { 5091adfc5217SJeff Kirsher struct bnx2x_queue_sp_obj *o = params->q_obj; 5092adfc5217SJeff Kirsher u8 cid_idx = params->params.cfc_del.cid_index; 5093adfc5217SJeff Kirsher 5094adfc5217SJeff Kirsher if (cid_idx >= o->max_cos) { 5095adfc5217SJeff Kirsher BNX2X_ERR("queue[%d]: cid_index (%d) is out of range\n", 5096adfc5217SJeff Kirsher o->cl_id, cid_idx); 5097adfc5217SJeff Kirsher return -EINVAL; 5098adfc5217SJeff Kirsher } 5099adfc5217SJeff Kirsher 5100adfc5217SJeff Kirsher return bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_CFC_DEL, 5101adfc5217SJeff Kirsher o->cids[cid_idx], 0, 0, NONE_CONNECTION_TYPE); 5102adfc5217SJeff Kirsher } 5103adfc5217SJeff Kirsher 5104adfc5217SJeff Kirsher static inline int bnx2x_q_send_terminate(struct bnx2x *bp, 5105adfc5217SJeff Kirsher struct bnx2x_queue_state_params *params) 5106adfc5217SJeff Kirsher { 5107adfc5217SJeff Kirsher struct bnx2x_queue_sp_obj *o = params->q_obj; 5108adfc5217SJeff Kirsher u8 cid_index = params->params.terminate.cid_index; 5109adfc5217SJeff Kirsher 5110adfc5217SJeff Kirsher if (cid_index >= o->max_cos) { 5111adfc5217SJeff Kirsher BNX2X_ERR("queue[%d]: cid_index (%d) is out of range\n", 5112adfc5217SJeff Kirsher o->cl_id, cid_index); 5113adfc5217SJeff Kirsher return -EINVAL; 5114adfc5217SJeff Kirsher } 5115adfc5217SJeff Kirsher 5116adfc5217SJeff Kirsher return bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_TERMINATE, 5117adfc5217SJeff Kirsher o->cids[cid_index], 0, 0, ETH_CONNECTION_TYPE); 5118adfc5217SJeff Kirsher } 5119adfc5217SJeff Kirsher 5120adfc5217SJeff Kirsher static inline int bnx2x_q_send_empty(struct bnx2x *bp, 5121adfc5217SJeff Kirsher struct bnx2x_queue_state_params *params) 5122adfc5217SJeff Kirsher { 5123adfc5217SJeff Kirsher struct bnx2x_queue_sp_obj *o = params->q_obj; 5124adfc5217SJeff Kirsher 5125adfc5217SJeff Kirsher return bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_EMPTY, 5126adfc5217SJeff Kirsher o->cids[BNX2X_PRIMARY_CID_INDEX], 0, 0, 5127adfc5217SJeff Kirsher ETH_CONNECTION_TYPE); 5128adfc5217SJeff Kirsher } 5129adfc5217SJeff Kirsher 5130adfc5217SJeff Kirsher static inline int bnx2x_queue_send_cmd_cmn(struct bnx2x *bp, 5131adfc5217SJeff Kirsher struct bnx2x_queue_state_params *params) 5132adfc5217SJeff Kirsher { 5133adfc5217SJeff Kirsher switch (params->cmd) { 5134adfc5217SJeff Kirsher case BNX2X_Q_CMD_INIT: 5135adfc5217SJeff Kirsher return bnx2x_q_init(bp, params); 5136adfc5217SJeff Kirsher case BNX2X_Q_CMD_SETUP_TX_ONLY: 5137adfc5217SJeff Kirsher return bnx2x_q_send_setup_tx_only(bp, params); 5138adfc5217SJeff Kirsher case BNX2X_Q_CMD_DEACTIVATE: 5139adfc5217SJeff Kirsher return bnx2x_q_send_deactivate(bp, params); 5140adfc5217SJeff Kirsher case BNX2X_Q_CMD_ACTIVATE: 5141adfc5217SJeff Kirsher return bnx2x_q_send_activate(bp, params); 5142adfc5217SJeff Kirsher case BNX2X_Q_CMD_UPDATE: 5143adfc5217SJeff Kirsher return bnx2x_q_send_update(bp, params); 5144adfc5217SJeff Kirsher case BNX2X_Q_CMD_UPDATE_TPA: 5145adfc5217SJeff Kirsher return bnx2x_q_send_update_tpa(bp, params); 5146adfc5217SJeff Kirsher case BNX2X_Q_CMD_HALT: 5147adfc5217SJeff Kirsher return bnx2x_q_send_halt(bp, params); 5148adfc5217SJeff Kirsher case BNX2X_Q_CMD_CFC_DEL: 5149adfc5217SJeff Kirsher return bnx2x_q_send_cfc_del(bp, params); 5150adfc5217SJeff Kirsher case BNX2X_Q_CMD_TERMINATE: 5151adfc5217SJeff Kirsher return bnx2x_q_send_terminate(bp, params); 5152adfc5217SJeff Kirsher case BNX2X_Q_CMD_EMPTY: 5153adfc5217SJeff Kirsher return bnx2x_q_send_empty(bp, params); 5154adfc5217SJeff Kirsher default: 5155adfc5217SJeff Kirsher BNX2X_ERR("Unknown command: %d\n", params->cmd); 5156adfc5217SJeff Kirsher return -EINVAL; 5157adfc5217SJeff Kirsher } 5158adfc5217SJeff Kirsher } 5159adfc5217SJeff Kirsher 5160adfc5217SJeff Kirsher static int bnx2x_queue_send_cmd_e1x(struct bnx2x *bp, 5161adfc5217SJeff Kirsher struct bnx2x_queue_state_params *params) 5162adfc5217SJeff Kirsher { 5163adfc5217SJeff Kirsher switch (params->cmd) { 5164adfc5217SJeff Kirsher case BNX2X_Q_CMD_SETUP: 5165adfc5217SJeff Kirsher return bnx2x_q_send_setup_e1x(bp, params); 5166adfc5217SJeff Kirsher case BNX2X_Q_CMD_INIT: 5167adfc5217SJeff Kirsher case BNX2X_Q_CMD_SETUP_TX_ONLY: 5168adfc5217SJeff Kirsher case BNX2X_Q_CMD_DEACTIVATE: 5169adfc5217SJeff Kirsher case BNX2X_Q_CMD_ACTIVATE: 5170adfc5217SJeff Kirsher case BNX2X_Q_CMD_UPDATE: 5171adfc5217SJeff Kirsher case BNX2X_Q_CMD_UPDATE_TPA: 5172adfc5217SJeff Kirsher case BNX2X_Q_CMD_HALT: 5173adfc5217SJeff Kirsher case BNX2X_Q_CMD_CFC_DEL: 5174adfc5217SJeff Kirsher case BNX2X_Q_CMD_TERMINATE: 5175adfc5217SJeff Kirsher case BNX2X_Q_CMD_EMPTY: 5176adfc5217SJeff Kirsher return bnx2x_queue_send_cmd_cmn(bp, params); 5177adfc5217SJeff Kirsher default: 5178adfc5217SJeff Kirsher BNX2X_ERR("Unknown command: %d\n", params->cmd); 5179adfc5217SJeff Kirsher return -EINVAL; 5180adfc5217SJeff Kirsher } 5181adfc5217SJeff Kirsher } 5182adfc5217SJeff Kirsher 5183adfc5217SJeff Kirsher static int bnx2x_queue_send_cmd_e2(struct bnx2x *bp, 5184adfc5217SJeff Kirsher struct bnx2x_queue_state_params *params) 5185adfc5217SJeff Kirsher { 5186adfc5217SJeff Kirsher switch (params->cmd) { 5187adfc5217SJeff Kirsher case BNX2X_Q_CMD_SETUP: 5188adfc5217SJeff Kirsher return bnx2x_q_send_setup_e2(bp, params); 5189adfc5217SJeff Kirsher case BNX2X_Q_CMD_INIT: 5190adfc5217SJeff Kirsher case BNX2X_Q_CMD_SETUP_TX_ONLY: 5191adfc5217SJeff Kirsher case BNX2X_Q_CMD_DEACTIVATE: 5192adfc5217SJeff Kirsher case BNX2X_Q_CMD_ACTIVATE: 5193adfc5217SJeff Kirsher case BNX2X_Q_CMD_UPDATE: 5194adfc5217SJeff Kirsher case BNX2X_Q_CMD_UPDATE_TPA: 5195adfc5217SJeff Kirsher case BNX2X_Q_CMD_HALT: 5196adfc5217SJeff Kirsher case BNX2X_Q_CMD_CFC_DEL: 5197adfc5217SJeff Kirsher case BNX2X_Q_CMD_TERMINATE: 5198adfc5217SJeff Kirsher case BNX2X_Q_CMD_EMPTY: 5199adfc5217SJeff Kirsher return bnx2x_queue_send_cmd_cmn(bp, params); 5200adfc5217SJeff Kirsher default: 5201adfc5217SJeff Kirsher BNX2X_ERR("Unknown command: %d\n", params->cmd); 5202adfc5217SJeff Kirsher return -EINVAL; 5203adfc5217SJeff Kirsher } 5204adfc5217SJeff Kirsher } 5205adfc5217SJeff Kirsher 5206adfc5217SJeff Kirsher /** 5207adfc5217SJeff Kirsher * bnx2x_queue_chk_transition - check state machine of a regular Queue 5208adfc5217SJeff Kirsher * 5209adfc5217SJeff Kirsher * @bp: device handle 5210adfc5217SJeff Kirsher * @o: 5211adfc5217SJeff Kirsher * @params: 5212adfc5217SJeff Kirsher * 5213adfc5217SJeff Kirsher * (not Forwarding) 5214adfc5217SJeff Kirsher * It both checks if the requested command is legal in a current 5215adfc5217SJeff Kirsher * state and, if it's legal, sets a `next_state' in the object 5216adfc5217SJeff Kirsher * that will be used in the completion flow to set the `state' 5217adfc5217SJeff Kirsher * of the object. 5218adfc5217SJeff Kirsher * 5219adfc5217SJeff Kirsher * returns 0 if a requested command is a legal transition, 5220adfc5217SJeff Kirsher * -EINVAL otherwise. 5221adfc5217SJeff Kirsher */ 5222adfc5217SJeff Kirsher static int bnx2x_queue_chk_transition(struct bnx2x *bp, 5223adfc5217SJeff Kirsher struct bnx2x_queue_sp_obj *o, 5224adfc5217SJeff Kirsher struct bnx2x_queue_state_params *params) 5225adfc5217SJeff Kirsher { 5226adfc5217SJeff Kirsher enum bnx2x_q_state state = o->state, next_state = BNX2X_Q_STATE_MAX; 5227adfc5217SJeff Kirsher enum bnx2x_queue_cmd cmd = params->cmd; 5228adfc5217SJeff Kirsher struct bnx2x_queue_update_params *update_params = 5229adfc5217SJeff Kirsher ¶ms->params.update; 5230adfc5217SJeff Kirsher u8 next_tx_only = o->num_tx_only; 5231adfc5217SJeff Kirsher 523216a5fd92SYuval Mintz /* Forget all pending for completion commands if a driver only state 5233adfc5217SJeff Kirsher * transition has been requested. 5234adfc5217SJeff Kirsher */ 5235adfc5217SJeff Kirsher if (test_bit(RAMROD_DRV_CLR_ONLY, ¶ms->ramrod_flags)) { 5236adfc5217SJeff Kirsher o->pending = 0; 5237adfc5217SJeff Kirsher o->next_state = BNX2X_Q_STATE_MAX; 5238adfc5217SJeff Kirsher } 5239adfc5217SJeff Kirsher 524016a5fd92SYuval Mintz /* Don't allow a next state transition if we are in the middle of 5241adfc5217SJeff Kirsher * the previous one. 5242adfc5217SJeff Kirsher */ 524304c46736SYuval Mintz if (o->pending) { 524404c46736SYuval Mintz BNX2X_ERR("Blocking transition since pending was %lx\n", 524504c46736SYuval Mintz o->pending); 5246adfc5217SJeff Kirsher return -EBUSY; 524704c46736SYuval Mintz } 5248adfc5217SJeff Kirsher 5249adfc5217SJeff Kirsher switch (state) { 5250adfc5217SJeff Kirsher case BNX2X_Q_STATE_RESET: 5251adfc5217SJeff Kirsher if (cmd == BNX2X_Q_CMD_INIT) 5252adfc5217SJeff Kirsher next_state = BNX2X_Q_STATE_INITIALIZED; 5253adfc5217SJeff Kirsher 5254adfc5217SJeff Kirsher break; 5255adfc5217SJeff Kirsher case BNX2X_Q_STATE_INITIALIZED: 5256adfc5217SJeff Kirsher if (cmd == BNX2X_Q_CMD_SETUP) { 5257adfc5217SJeff Kirsher if (test_bit(BNX2X_Q_FLG_ACTIVE, 5258adfc5217SJeff Kirsher ¶ms->params.setup.flags)) 5259adfc5217SJeff Kirsher next_state = BNX2X_Q_STATE_ACTIVE; 5260adfc5217SJeff Kirsher else 5261adfc5217SJeff Kirsher next_state = BNX2X_Q_STATE_INACTIVE; 5262adfc5217SJeff Kirsher } 5263adfc5217SJeff Kirsher 5264adfc5217SJeff Kirsher break; 5265adfc5217SJeff Kirsher case BNX2X_Q_STATE_ACTIVE: 5266adfc5217SJeff Kirsher if (cmd == BNX2X_Q_CMD_DEACTIVATE) 5267adfc5217SJeff Kirsher next_state = BNX2X_Q_STATE_INACTIVE; 5268adfc5217SJeff Kirsher 5269adfc5217SJeff Kirsher else if ((cmd == BNX2X_Q_CMD_EMPTY) || 5270adfc5217SJeff Kirsher (cmd == BNX2X_Q_CMD_UPDATE_TPA)) 5271adfc5217SJeff Kirsher next_state = BNX2X_Q_STATE_ACTIVE; 5272adfc5217SJeff Kirsher 5273adfc5217SJeff Kirsher else if (cmd == BNX2X_Q_CMD_SETUP_TX_ONLY) { 5274adfc5217SJeff Kirsher next_state = BNX2X_Q_STATE_MULTI_COS; 5275adfc5217SJeff Kirsher next_tx_only = 1; 5276adfc5217SJeff Kirsher } 5277adfc5217SJeff Kirsher 5278adfc5217SJeff Kirsher else if (cmd == BNX2X_Q_CMD_HALT) 5279adfc5217SJeff Kirsher next_state = BNX2X_Q_STATE_STOPPED; 5280adfc5217SJeff Kirsher 5281adfc5217SJeff Kirsher else if (cmd == BNX2X_Q_CMD_UPDATE) { 5282adfc5217SJeff Kirsher /* If "active" state change is requested, update the 5283adfc5217SJeff Kirsher * state accordingly. 5284adfc5217SJeff Kirsher */ 5285adfc5217SJeff Kirsher if (test_bit(BNX2X_Q_UPDATE_ACTIVATE_CHNG, 5286adfc5217SJeff Kirsher &update_params->update_flags) && 5287adfc5217SJeff Kirsher !test_bit(BNX2X_Q_UPDATE_ACTIVATE, 5288adfc5217SJeff Kirsher &update_params->update_flags)) 5289adfc5217SJeff Kirsher next_state = BNX2X_Q_STATE_INACTIVE; 5290adfc5217SJeff Kirsher else 5291adfc5217SJeff Kirsher next_state = BNX2X_Q_STATE_ACTIVE; 5292adfc5217SJeff Kirsher } 5293adfc5217SJeff Kirsher 5294adfc5217SJeff Kirsher break; 5295adfc5217SJeff Kirsher case BNX2X_Q_STATE_MULTI_COS: 5296adfc5217SJeff Kirsher if (cmd == BNX2X_Q_CMD_TERMINATE) 5297adfc5217SJeff Kirsher next_state = BNX2X_Q_STATE_MCOS_TERMINATED; 5298adfc5217SJeff Kirsher 5299adfc5217SJeff Kirsher else if (cmd == BNX2X_Q_CMD_SETUP_TX_ONLY) { 5300adfc5217SJeff Kirsher next_state = BNX2X_Q_STATE_MULTI_COS; 5301adfc5217SJeff Kirsher next_tx_only = o->num_tx_only + 1; 5302adfc5217SJeff Kirsher } 5303adfc5217SJeff Kirsher 5304adfc5217SJeff Kirsher else if ((cmd == BNX2X_Q_CMD_EMPTY) || 5305adfc5217SJeff Kirsher (cmd == BNX2X_Q_CMD_UPDATE_TPA)) 5306adfc5217SJeff Kirsher next_state = BNX2X_Q_STATE_MULTI_COS; 5307adfc5217SJeff Kirsher 5308adfc5217SJeff Kirsher else if (cmd == BNX2X_Q_CMD_UPDATE) { 5309adfc5217SJeff Kirsher /* If "active" state change is requested, update the 5310adfc5217SJeff Kirsher * state accordingly. 5311adfc5217SJeff Kirsher */ 5312adfc5217SJeff Kirsher if (test_bit(BNX2X_Q_UPDATE_ACTIVATE_CHNG, 5313adfc5217SJeff Kirsher &update_params->update_flags) && 5314adfc5217SJeff Kirsher !test_bit(BNX2X_Q_UPDATE_ACTIVATE, 5315adfc5217SJeff Kirsher &update_params->update_flags)) 5316adfc5217SJeff Kirsher next_state = BNX2X_Q_STATE_INACTIVE; 5317adfc5217SJeff Kirsher else 5318adfc5217SJeff Kirsher next_state = BNX2X_Q_STATE_MULTI_COS; 5319adfc5217SJeff Kirsher } 5320adfc5217SJeff Kirsher 5321adfc5217SJeff Kirsher break; 5322adfc5217SJeff Kirsher case BNX2X_Q_STATE_MCOS_TERMINATED: 5323adfc5217SJeff Kirsher if (cmd == BNX2X_Q_CMD_CFC_DEL) { 5324adfc5217SJeff Kirsher next_tx_only = o->num_tx_only - 1; 5325adfc5217SJeff Kirsher if (next_tx_only == 0) 5326adfc5217SJeff Kirsher next_state = BNX2X_Q_STATE_ACTIVE; 5327adfc5217SJeff Kirsher else 5328adfc5217SJeff Kirsher next_state = BNX2X_Q_STATE_MULTI_COS; 5329adfc5217SJeff Kirsher } 5330adfc5217SJeff Kirsher 5331adfc5217SJeff Kirsher break; 5332adfc5217SJeff Kirsher case BNX2X_Q_STATE_INACTIVE: 5333adfc5217SJeff Kirsher if (cmd == BNX2X_Q_CMD_ACTIVATE) 5334adfc5217SJeff Kirsher next_state = BNX2X_Q_STATE_ACTIVE; 5335adfc5217SJeff Kirsher 5336adfc5217SJeff Kirsher else if ((cmd == BNX2X_Q_CMD_EMPTY) || 5337adfc5217SJeff Kirsher (cmd == BNX2X_Q_CMD_UPDATE_TPA)) 5338adfc5217SJeff Kirsher next_state = BNX2X_Q_STATE_INACTIVE; 5339adfc5217SJeff Kirsher 5340adfc5217SJeff Kirsher else if (cmd == BNX2X_Q_CMD_HALT) 5341adfc5217SJeff Kirsher next_state = BNX2X_Q_STATE_STOPPED; 5342adfc5217SJeff Kirsher 5343adfc5217SJeff Kirsher else if (cmd == BNX2X_Q_CMD_UPDATE) { 5344adfc5217SJeff Kirsher /* If "active" state change is requested, update the 5345adfc5217SJeff Kirsher * state accordingly. 5346adfc5217SJeff Kirsher */ 5347adfc5217SJeff Kirsher if (test_bit(BNX2X_Q_UPDATE_ACTIVATE_CHNG, 5348adfc5217SJeff Kirsher &update_params->update_flags) && 5349adfc5217SJeff Kirsher test_bit(BNX2X_Q_UPDATE_ACTIVATE, 5350adfc5217SJeff Kirsher &update_params->update_flags)){ 5351adfc5217SJeff Kirsher if (o->num_tx_only == 0) 5352adfc5217SJeff Kirsher next_state = BNX2X_Q_STATE_ACTIVE; 5353adfc5217SJeff Kirsher else /* tx only queues exist for this queue */ 5354adfc5217SJeff Kirsher next_state = BNX2X_Q_STATE_MULTI_COS; 5355adfc5217SJeff Kirsher } else 5356adfc5217SJeff Kirsher next_state = BNX2X_Q_STATE_INACTIVE; 5357adfc5217SJeff Kirsher } 5358adfc5217SJeff Kirsher 5359adfc5217SJeff Kirsher break; 5360adfc5217SJeff Kirsher case BNX2X_Q_STATE_STOPPED: 5361adfc5217SJeff Kirsher if (cmd == BNX2X_Q_CMD_TERMINATE) 5362adfc5217SJeff Kirsher next_state = BNX2X_Q_STATE_TERMINATED; 5363adfc5217SJeff Kirsher 5364adfc5217SJeff Kirsher break; 5365adfc5217SJeff Kirsher case BNX2X_Q_STATE_TERMINATED: 5366adfc5217SJeff Kirsher if (cmd == BNX2X_Q_CMD_CFC_DEL) 5367adfc5217SJeff Kirsher next_state = BNX2X_Q_STATE_RESET; 5368adfc5217SJeff Kirsher 5369adfc5217SJeff Kirsher break; 5370adfc5217SJeff Kirsher default: 5371adfc5217SJeff Kirsher BNX2X_ERR("Illegal state: %d\n", state); 5372adfc5217SJeff Kirsher } 5373adfc5217SJeff Kirsher 5374adfc5217SJeff Kirsher /* Transition is assured */ 5375adfc5217SJeff Kirsher if (next_state != BNX2X_Q_STATE_MAX) { 5376adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "Good state transition: %d(%d)->%d\n", 5377adfc5217SJeff Kirsher state, cmd, next_state); 5378adfc5217SJeff Kirsher o->next_state = next_state; 5379adfc5217SJeff Kirsher o->next_tx_only = next_tx_only; 5380adfc5217SJeff Kirsher return 0; 5381adfc5217SJeff Kirsher } 5382adfc5217SJeff Kirsher 5383adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "Bad state transition request: %d %d\n", state, cmd); 5384adfc5217SJeff Kirsher 5385adfc5217SJeff Kirsher return -EINVAL; 5386adfc5217SJeff Kirsher } 5387adfc5217SJeff Kirsher 5388adfc5217SJeff Kirsher void bnx2x_init_queue_obj(struct bnx2x *bp, 5389adfc5217SJeff Kirsher struct bnx2x_queue_sp_obj *obj, 5390adfc5217SJeff Kirsher u8 cl_id, u32 *cids, u8 cid_cnt, u8 func_id, 5391adfc5217SJeff Kirsher void *rdata, 5392adfc5217SJeff Kirsher dma_addr_t rdata_mapping, unsigned long type) 5393adfc5217SJeff Kirsher { 5394adfc5217SJeff Kirsher memset(obj, 0, sizeof(*obj)); 5395adfc5217SJeff Kirsher 5396adfc5217SJeff Kirsher /* We support only BNX2X_MULTI_TX_COS Tx CoS at the moment */ 5397adfc5217SJeff Kirsher BUG_ON(BNX2X_MULTI_TX_COS < cid_cnt); 5398adfc5217SJeff Kirsher 5399adfc5217SJeff Kirsher memcpy(obj->cids, cids, sizeof(obj->cids[0]) * cid_cnt); 5400adfc5217SJeff Kirsher obj->max_cos = cid_cnt; 5401adfc5217SJeff Kirsher obj->cl_id = cl_id; 5402adfc5217SJeff Kirsher obj->func_id = func_id; 5403adfc5217SJeff Kirsher obj->rdata = rdata; 5404adfc5217SJeff Kirsher obj->rdata_mapping = rdata_mapping; 5405adfc5217SJeff Kirsher obj->type = type; 5406adfc5217SJeff Kirsher obj->next_state = BNX2X_Q_STATE_MAX; 5407adfc5217SJeff Kirsher 5408adfc5217SJeff Kirsher if (CHIP_IS_E1x(bp)) 5409adfc5217SJeff Kirsher obj->send_cmd = bnx2x_queue_send_cmd_e1x; 5410adfc5217SJeff Kirsher else 5411adfc5217SJeff Kirsher obj->send_cmd = bnx2x_queue_send_cmd_e2; 5412adfc5217SJeff Kirsher 5413adfc5217SJeff Kirsher obj->check_transition = bnx2x_queue_chk_transition; 5414adfc5217SJeff Kirsher 5415adfc5217SJeff Kirsher obj->complete_cmd = bnx2x_queue_comp_cmd; 5416adfc5217SJeff Kirsher obj->wait_comp = bnx2x_queue_wait_comp; 5417adfc5217SJeff Kirsher obj->set_pending = bnx2x_queue_set_pending; 5418adfc5217SJeff Kirsher } 5419adfc5217SJeff Kirsher 542067c431a5SAriel Elior /* return a queue object's logical state*/ 542167c431a5SAriel Elior int bnx2x_get_q_logical_state(struct bnx2x *bp, 542267c431a5SAriel Elior struct bnx2x_queue_sp_obj *obj) 542367c431a5SAriel Elior { 542467c431a5SAriel Elior switch (obj->state) { 542567c431a5SAriel Elior case BNX2X_Q_STATE_ACTIVE: 542667c431a5SAriel Elior case BNX2X_Q_STATE_MULTI_COS: 542767c431a5SAriel Elior return BNX2X_Q_LOGICAL_STATE_ACTIVE; 542867c431a5SAriel Elior case BNX2X_Q_STATE_RESET: 542967c431a5SAriel Elior case BNX2X_Q_STATE_INITIALIZED: 543067c431a5SAriel Elior case BNX2X_Q_STATE_MCOS_TERMINATED: 543167c431a5SAriel Elior case BNX2X_Q_STATE_INACTIVE: 543267c431a5SAriel Elior case BNX2X_Q_STATE_STOPPED: 543367c431a5SAriel Elior case BNX2X_Q_STATE_TERMINATED: 543467c431a5SAriel Elior case BNX2X_Q_STATE_FLRED: 543567c431a5SAriel Elior return BNX2X_Q_LOGICAL_STATE_STOPPED; 543667c431a5SAriel Elior default: 543767c431a5SAriel Elior return -EINVAL; 543867c431a5SAriel Elior } 543967c431a5SAriel Elior } 544067c431a5SAriel Elior 5441adfc5217SJeff Kirsher /********************** Function state object *********************************/ 5442adfc5217SJeff Kirsher enum bnx2x_func_state bnx2x_func_get_state(struct bnx2x *bp, 5443adfc5217SJeff Kirsher struct bnx2x_func_sp_obj *o) 5444adfc5217SJeff Kirsher { 5445adfc5217SJeff Kirsher /* in the middle of transaction - return INVALID state */ 5446adfc5217SJeff Kirsher if (o->pending) 5447adfc5217SJeff Kirsher return BNX2X_F_STATE_MAX; 5448adfc5217SJeff Kirsher 544916a5fd92SYuval Mintz /* unsure the order of reading of o->pending and o->state 5450adfc5217SJeff Kirsher * o->pending should be read first 5451adfc5217SJeff Kirsher */ 5452adfc5217SJeff Kirsher rmb(); 5453adfc5217SJeff Kirsher 5454adfc5217SJeff Kirsher return o->state; 5455adfc5217SJeff Kirsher } 5456adfc5217SJeff Kirsher 5457adfc5217SJeff Kirsher static int bnx2x_func_wait_comp(struct bnx2x *bp, 5458adfc5217SJeff Kirsher struct bnx2x_func_sp_obj *o, 5459adfc5217SJeff Kirsher enum bnx2x_func_cmd cmd) 5460adfc5217SJeff Kirsher { 5461adfc5217SJeff Kirsher return bnx2x_state_wait(bp, cmd, &o->pending); 5462adfc5217SJeff Kirsher } 5463adfc5217SJeff Kirsher 5464adfc5217SJeff Kirsher /** 5465adfc5217SJeff Kirsher * bnx2x_func_state_change_comp - complete the state machine transition 5466adfc5217SJeff Kirsher * 5467adfc5217SJeff Kirsher * @bp: device handle 5468adfc5217SJeff Kirsher * @o: 5469adfc5217SJeff Kirsher * @cmd: 5470adfc5217SJeff Kirsher * 5471adfc5217SJeff Kirsher * Called on state change transition. Completes the state 5472adfc5217SJeff Kirsher * machine transition only - no HW interaction. 5473adfc5217SJeff Kirsher */ 5474adfc5217SJeff Kirsher static inline int bnx2x_func_state_change_comp(struct bnx2x *bp, 5475adfc5217SJeff Kirsher struct bnx2x_func_sp_obj *o, 5476adfc5217SJeff Kirsher enum bnx2x_func_cmd cmd) 5477adfc5217SJeff Kirsher { 5478adfc5217SJeff Kirsher unsigned long cur_pending = o->pending; 5479adfc5217SJeff Kirsher 5480adfc5217SJeff Kirsher if (!test_and_clear_bit(cmd, &cur_pending)) { 548151c1a580SMerav Sicron BNX2X_ERR("Bad MC reply %d for func %d in state %d pending 0x%lx, next_state %d\n", 548251c1a580SMerav Sicron cmd, BP_FUNC(bp), o->state, 548351c1a580SMerav Sicron cur_pending, o->next_state); 5484adfc5217SJeff Kirsher return -EINVAL; 5485adfc5217SJeff Kirsher } 5486adfc5217SJeff Kirsher 548794f05b0fSJoe Perches DP(BNX2X_MSG_SP, 548894f05b0fSJoe Perches "Completing command %d for func %d, setting state to %d\n", 548994f05b0fSJoe Perches cmd, BP_FUNC(bp), o->next_state); 5490adfc5217SJeff Kirsher 5491adfc5217SJeff Kirsher o->state = o->next_state; 5492adfc5217SJeff Kirsher o->next_state = BNX2X_F_STATE_MAX; 5493adfc5217SJeff Kirsher 5494adfc5217SJeff Kirsher /* It's important that o->state and o->next_state are 5495adfc5217SJeff Kirsher * updated before o->pending. 5496adfc5217SJeff Kirsher */ 5497adfc5217SJeff Kirsher wmb(); 5498adfc5217SJeff Kirsher 5499adfc5217SJeff Kirsher clear_bit(cmd, &o->pending); 5500adfc5217SJeff Kirsher smp_mb__after_clear_bit(); 5501adfc5217SJeff Kirsher 5502adfc5217SJeff Kirsher return 0; 5503adfc5217SJeff Kirsher } 5504adfc5217SJeff Kirsher 5505adfc5217SJeff Kirsher /** 5506adfc5217SJeff Kirsher * bnx2x_func_comp_cmd - complete the state change command 5507adfc5217SJeff Kirsher * 5508adfc5217SJeff Kirsher * @bp: device handle 5509adfc5217SJeff Kirsher * @o: 5510adfc5217SJeff Kirsher * @cmd: 5511adfc5217SJeff Kirsher * 5512adfc5217SJeff Kirsher * Checks that the arrived completion is expected. 5513adfc5217SJeff Kirsher */ 5514adfc5217SJeff Kirsher static int bnx2x_func_comp_cmd(struct bnx2x *bp, 5515adfc5217SJeff Kirsher struct bnx2x_func_sp_obj *o, 5516adfc5217SJeff Kirsher enum bnx2x_func_cmd cmd) 5517adfc5217SJeff Kirsher { 5518adfc5217SJeff Kirsher /* Complete the state machine part first, check if it's a 5519adfc5217SJeff Kirsher * legal completion. 5520adfc5217SJeff Kirsher */ 5521adfc5217SJeff Kirsher int rc = bnx2x_func_state_change_comp(bp, o, cmd); 5522adfc5217SJeff Kirsher return rc; 5523adfc5217SJeff Kirsher } 5524adfc5217SJeff Kirsher 5525adfc5217SJeff Kirsher /** 5526adfc5217SJeff Kirsher * bnx2x_func_chk_transition - perform function state machine transition 5527adfc5217SJeff Kirsher * 5528adfc5217SJeff Kirsher * @bp: device handle 5529adfc5217SJeff Kirsher * @o: 5530adfc5217SJeff Kirsher * @params: 5531adfc5217SJeff Kirsher * 5532adfc5217SJeff Kirsher * It both checks if the requested command is legal in a current 5533adfc5217SJeff Kirsher * state and, if it's legal, sets a `next_state' in the object 5534adfc5217SJeff Kirsher * that will be used in the completion flow to set the `state' 5535adfc5217SJeff Kirsher * of the object. 5536adfc5217SJeff Kirsher * 5537adfc5217SJeff Kirsher * returns 0 if a requested command is a legal transition, 5538adfc5217SJeff Kirsher * -EINVAL otherwise. 5539adfc5217SJeff Kirsher */ 5540adfc5217SJeff Kirsher static int bnx2x_func_chk_transition(struct bnx2x *bp, 5541adfc5217SJeff Kirsher struct bnx2x_func_sp_obj *o, 5542adfc5217SJeff Kirsher struct bnx2x_func_state_params *params) 5543adfc5217SJeff Kirsher { 5544adfc5217SJeff Kirsher enum bnx2x_func_state state = o->state, next_state = BNX2X_F_STATE_MAX; 5545adfc5217SJeff Kirsher enum bnx2x_func_cmd cmd = params->cmd; 5546adfc5217SJeff Kirsher 554716a5fd92SYuval Mintz /* Forget all pending for completion commands if a driver only state 5548adfc5217SJeff Kirsher * transition has been requested. 5549adfc5217SJeff Kirsher */ 5550adfc5217SJeff Kirsher if (test_bit(RAMROD_DRV_CLR_ONLY, ¶ms->ramrod_flags)) { 5551adfc5217SJeff Kirsher o->pending = 0; 5552adfc5217SJeff Kirsher o->next_state = BNX2X_F_STATE_MAX; 5553adfc5217SJeff Kirsher } 5554adfc5217SJeff Kirsher 555516a5fd92SYuval Mintz /* Don't allow a next state transition if we are in the middle of 5556adfc5217SJeff Kirsher * the previous one. 5557adfc5217SJeff Kirsher */ 5558adfc5217SJeff Kirsher if (o->pending) 5559adfc5217SJeff Kirsher return -EBUSY; 5560adfc5217SJeff Kirsher 5561adfc5217SJeff Kirsher switch (state) { 5562adfc5217SJeff Kirsher case BNX2X_F_STATE_RESET: 5563adfc5217SJeff Kirsher if (cmd == BNX2X_F_CMD_HW_INIT) 5564adfc5217SJeff Kirsher next_state = BNX2X_F_STATE_INITIALIZED; 5565adfc5217SJeff Kirsher 5566adfc5217SJeff Kirsher break; 5567adfc5217SJeff Kirsher case BNX2X_F_STATE_INITIALIZED: 5568adfc5217SJeff Kirsher if (cmd == BNX2X_F_CMD_START) 5569adfc5217SJeff Kirsher next_state = BNX2X_F_STATE_STARTED; 5570adfc5217SJeff Kirsher 5571adfc5217SJeff Kirsher else if (cmd == BNX2X_F_CMD_HW_RESET) 5572adfc5217SJeff Kirsher next_state = BNX2X_F_STATE_RESET; 5573adfc5217SJeff Kirsher 5574adfc5217SJeff Kirsher break; 5575adfc5217SJeff Kirsher case BNX2X_F_STATE_STARTED: 5576adfc5217SJeff Kirsher if (cmd == BNX2X_F_CMD_STOP) 5577adfc5217SJeff Kirsher next_state = BNX2X_F_STATE_INITIALIZED; 5578a3348722SBarak Witkowski /* afex ramrods can be sent only in started mode, and only 5579a3348722SBarak Witkowski * if not pending for function_stop ramrod completion 5580a3348722SBarak Witkowski * for these events - next state remained STARTED. 5581a3348722SBarak Witkowski */ 5582a3348722SBarak Witkowski else if ((cmd == BNX2X_F_CMD_AFEX_UPDATE) && 5583a3348722SBarak Witkowski (!test_bit(BNX2X_F_CMD_STOP, &o->pending))) 5584a3348722SBarak Witkowski next_state = BNX2X_F_STATE_STARTED; 5585a3348722SBarak Witkowski 5586a3348722SBarak Witkowski else if ((cmd == BNX2X_F_CMD_AFEX_VIFLISTS) && 5587a3348722SBarak Witkowski (!test_bit(BNX2X_F_CMD_STOP, &o->pending))) 5588a3348722SBarak Witkowski next_state = BNX2X_F_STATE_STARTED; 558955c11941SMerav Sicron 559055c11941SMerav Sicron /* Switch_update ramrod can be sent in either started or 559155c11941SMerav Sicron * tx_stopped state, and it doesn't change the state. 559255c11941SMerav Sicron */ 559355c11941SMerav Sicron else if ((cmd == BNX2X_F_CMD_SWITCH_UPDATE) && 559455c11941SMerav Sicron (!test_bit(BNX2X_F_CMD_STOP, &o->pending))) 559555c11941SMerav Sicron next_state = BNX2X_F_STATE_STARTED; 559655c11941SMerav Sicron 5597adfc5217SJeff Kirsher else if (cmd == BNX2X_F_CMD_TX_STOP) 5598adfc5217SJeff Kirsher next_state = BNX2X_F_STATE_TX_STOPPED; 5599adfc5217SJeff Kirsher 5600adfc5217SJeff Kirsher break; 5601adfc5217SJeff Kirsher case BNX2X_F_STATE_TX_STOPPED: 560255c11941SMerav Sicron if ((cmd == BNX2X_F_CMD_SWITCH_UPDATE) && 560355c11941SMerav Sicron (!test_bit(BNX2X_F_CMD_STOP, &o->pending))) 560455c11941SMerav Sicron next_state = BNX2X_F_STATE_TX_STOPPED; 560555c11941SMerav Sicron 560655c11941SMerav Sicron else if (cmd == BNX2X_F_CMD_TX_START) 5607adfc5217SJeff Kirsher next_state = BNX2X_F_STATE_STARTED; 5608adfc5217SJeff Kirsher 5609adfc5217SJeff Kirsher break; 5610adfc5217SJeff Kirsher default: 5611adfc5217SJeff Kirsher BNX2X_ERR("Unknown state: %d\n", state); 5612adfc5217SJeff Kirsher } 5613adfc5217SJeff Kirsher 5614adfc5217SJeff Kirsher /* Transition is assured */ 5615adfc5217SJeff Kirsher if (next_state != BNX2X_F_STATE_MAX) { 5616adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "Good function state transition: %d(%d)->%d\n", 5617adfc5217SJeff Kirsher state, cmd, next_state); 5618adfc5217SJeff Kirsher o->next_state = next_state; 5619adfc5217SJeff Kirsher return 0; 5620adfc5217SJeff Kirsher } 5621adfc5217SJeff Kirsher 5622adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "Bad function state transition request: %d %d\n", 5623adfc5217SJeff Kirsher state, cmd); 5624adfc5217SJeff Kirsher 5625adfc5217SJeff Kirsher return -EINVAL; 5626adfc5217SJeff Kirsher } 5627adfc5217SJeff Kirsher 5628adfc5217SJeff Kirsher /** 5629adfc5217SJeff Kirsher * bnx2x_func_init_func - performs HW init at function stage 5630adfc5217SJeff Kirsher * 5631adfc5217SJeff Kirsher * @bp: device handle 5632adfc5217SJeff Kirsher * @drv: 5633adfc5217SJeff Kirsher * 5634adfc5217SJeff Kirsher * Init HW when the current phase is 5635adfc5217SJeff Kirsher * FW_MSG_CODE_DRV_LOAD_FUNCTION: initialize only FUNCTION-only 5636adfc5217SJeff Kirsher * HW blocks. 5637adfc5217SJeff Kirsher */ 5638adfc5217SJeff Kirsher static inline int bnx2x_func_init_func(struct bnx2x *bp, 5639adfc5217SJeff Kirsher const struct bnx2x_func_sp_drv_ops *drv) 5640adfc5217SJeff Kirsher { 5641adfc5217SJeff Kirsher return drv->init_hw_func(bp); 5642adfc5217SJeff Kirsher } 5643adfc5217SJeff Kirsher 5644adfc5217SJeff Kirsher /** 5645adfc5217SJeff Kirsher * bnx2x_func_init_port - performs HW init at port stage 5646adfc5217SJeff Kirsher * 5647adfc5217SJeff Kirsher * @bp: device handle 5648adfc5217SJeff Kirsher * @drv: 5649adfc5217SJeff Kirsher * 5650adfc5217SJeff Kirsher * Init HW when the current phase is 5651adfc5217SJeff Kirsher * FW_MSG_CODE_DRV_LOAD_PORT: initialize PORT-only and 5652adfc5217SJeff Kirsher * FUNCTION-only HW blocks. 5653adfc5217SJeff Kirsher * 5654adfc5217SJeff Kirsher */ 5655adfc5217SJeff Kirsher static inline int bnx2x_func_init_port(struct bnx2x *bp, 5656adfc5217SJeff Kirsher const struct bnx2x_func_sp_drv_ops *drv) 5657adfc5217SJeff Kirsher { 5658adfc5217SJeff Kirsher int rc = drv->init_hw_port(bp); 5659adfc5217SJeff Kirsher if (rc) 5660adfc5217SJeff Kirsher return rc; 5661adfc5217SJeff Kirsher 5662adfc5217SJeff Kirsher return bnx2x_func_init_func(bp, drv); 5663adfc5217SJeff Kirsher } 5664adfc5217SJeff Kirsher 5665adfc5217SJeff Kirsher /** 5666adfc5217SJeff Kirsher * bnx2x_func_init_cmn_chip - performs HW init at chip-common stage 5667adfc5217SJeff Kirsher * 5668adfc5217SJeff Kirsher * @bp: device handle 5669adfc5217SJeff Kirsher * @drv: 5670adfc5217SJeff Kirsher * 5671adfc5217SJeff Kirsher * Init HW when the current phase is 5672adfc5217SJeff Kirsher * FW_MSG_CODE_DRV_LOAD_COMMON_CHIP: initialize COMMON_CHIP, 5673adfc5217SJeff Kirsher * PORT-only and FUNCTION-only HW blocks. 5674adfc5217SJeff Kirsher */ 5675adfc5217SJeff Kirsher static inline int bnx2x_func_init_cmn_chip(struct bnx2x *bp, 5676adfc5217SJeff Kirsher const struct bnx2x_func_sp_drv_ops *drv) 5677adfc5217SJeff Kirsher { 5678adfc5217SJeff Kirsher int rc = drv->init_hw_cmn_chip(bp); 5679adfc5217SJeff Kirsher if (rc) 5680adfc5217SJeff Kirsher return rc; 5681adfc5217SJeff Kirsher 5682adfc5217SJeff Kirsher return bnx2x_func_init_port(bp, drv); 5683adfc5217SJeff Kirsher } 5684adfc5217SJeff Kirsher 5685adfc5217SJeff Kirsher /** 5686adfc5217SJeff Kirsher * bnx2x_func_init_cmn - performs HW init at common stage 5687adfc5217SJeff Kirsher * 5688adfc5217SJeff Kirsher * @bp: device handle 5689adfc5217SJeff Kirsher * @drv: 5690adfc5217SJeff Kirsher * 5691adfc5217SJeff Kirsher * Init HW when the current phase is 5692adfc5217SJeff Kirsher * FW_MSG_CODE_DRV_LOAD_COMMON_CHIP: initialize COMMON, 5693adfc5217SJeff Kirsher * PORT-only and FUNCTION-only HW blocks. 5694adfc5217SJeff Kirsher */ 5695adfc5217SJeff Kirsher static inline int bnx2x_func_init_cmn(struct bnx2x *bp, 5696adfc5217SJeff Kirsher const struct bnx2x_func_sp_drv_ops *drv) 5697adfc5217SJeff Kirsher { 5698adfc5217SJeff Kirsher int rc = drv->init_hw_cmn(bp); 5699adfc5217SJeff Kirsher if (rc) 5700adfc5217SJeff Kirsher return rc; 5701adfc5217SJeff Kirsher 5702adfc5217SJeff Kirsher return bnx2x_func_init_port(bp, drv); 5703adfc5217SJeff Kirsher } 5704adfc5217SJeff Kirsher 5705adfc5217SJeff Kirsher static int bnx2x_func_hw_init(struct bnx2x *bp, 5706adfc5217SJeff Kirsher struct bnx2x_func_state_params *params) 5707adfc5217SJeff Kirsher { 5708adfc5217SJeff Kirsher u32 load_code = params->params.hw_init.load_phase; 5709adfc5217SJeff Kirsher struct bnx2x_func_sp_obj *o = params->f_obj; 5710adfc5217SJeff Kirsher const struct bnx2x_func_sp_drv_ops *drv = o->drv; 5711adfc5217SJeff Kirsher int rc = 0; 5712adfc5217SJeff Kirsher 5713adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "function %d load_code %x\n", 5714adfc5217SJeff Kirsher BP_ABS_FUNC(bp), load_code); 5715adfc5217SJeff Kirsher 5716adfc5217SJeff Kirsher /* Prepare buffers for unzipping the FW */ 5717adfc5217SJeff Kirsher rc = drv->gunzip_init(bp); 5718adfc5217SJeff Kirsher if (rc) 5719adfc5217SJeff Kirsher return rc; 5720adfc5217SJeff Kirsher 5721adfc5217SJeff Kirsher /* Prepare FW */ 5722adfc5217SJeff Kirsher rc = drv->init_fw(bp); 5723adfc5217SJeff Kirsher if (rc) { 5724adfc5217SJeff Kirsher BNX2X_ERR("Error loading firmware\n"); 5725eb2afd4aSDmitry Kravkov goto init_err; 5726adfc5217SJeff Kirsher } 5727adfc5217SJeff Kirsher 572816a5fd92SYuval Mintz /* Handle the beginning of COMMON_XXX pases separately... */ 5729adfc5217SJeff Kirsher switch (load_code) { 5730adfc5217SJeff Kirsher case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP: 5731adfc5217SJeff Kirsher rc = bnx2x_func_init_cmn_chip(bp, drv); 5732adfc5217SJeff Kirsher if (rc) 5733eb2afd4aSDmitry Kravkov goto init_err; 5734adfc5217SJeff Kirsher 5735adfc5217SJeff Kirsher break; 5736adfc5217SJeff Kirsher case FW_MSG_CODE_DRV_LOAD_COMMON: 5737adfc5217SJeff Kirsher rc = bnx2x_func_init_cmn(bp, drv); 5738adfc5217SJeff Kirsher if (rc) 5739eb2afd4aSDmitry Kravkov goto init_err; 5740adfc5217SJeff Kirsher 5741adfc5217SJeff Kirsher break; 5742adfc5217SJeff Kirsher case FW_MSG_CODE_DRV_LOAD_PORT: 5743adfc5217SJeff Kirsher rc = bnx2x_func_init_port(bp, drv); 5744adfc5217SJeff Kirsher if (rc) 5745eb2afd4aSDmitry Kravkov goto init_err; 5746adfc5217SJeff Kirsher 5747adfc5217SJeff Kirsher break; 5748adfc5217SJeff Kirsher case FW_MSG_CODE_DRV_LOAD_FUNCTION: 5749adfc5217SJeff Kirsher rc = bnx2x_func_init_func(bp, drv); 5750adfc5217SJeff Kirsher if (rc) 5751eb2afd4aSDmitry Kravkov goto init_err; 5752adfc5217SJeff Kirsher 5753adfc5217SJeff Kirsher break; 5754adfc5217SJeff Kirsher default: 5755adfc5217SJeff Kirsher BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code); 5756adfc5217SJeff Kirsher rc = -EINVAL; 5757adfc5217SJeff Kirsher } 5758adfc5217SJeff Kirsher 5759eb2afd4aSDmitry Kravkov init_err: 5760adfc5217SJeff Kirsher drv->gunzip_end(bp); 5761adfc5217SJeff Kirsher 576216a5fd92SYuval Mintz /* In case of success, complete the command immediately: no ramrods 5763adfc5217SJeff Kirsher * have been sent. 5764adfc5217SJeff Kirsher */ 5765adfc5217SJeff Kirsher if (!rc) 5766adfc5217SJeff Kirsher o->complete_cmd(bp, o, BNX2X_F_CMD_HW_INIT); 5767adfc5217SJeff Kirsher 5768adfc5217SJeff Kirsher return rc; 5769adfc5217SJeff Kirsher } 5770adfc5217SJeff Kirsher 5771adfc5217SJeff Kirsher /** 5772adfc5217SJeff Kirsher * bnx2x_func_reset_func - reset HW at function stage 5773adfc5217SJeff Kirsher * 5774adfc5217SJeff Kirsher * @bp: device handle 5775adfc5217SJeff Kirsher * @drv: 5776adfc5217SJeff Kirsher * 5777adfc5217SJeff Kirsher * Reset HW at FW_MSG_CODE_DRV_UNLOAD_FUNCTION stage: reset only 5778adfc5217SJeff Kirsher * FUNCTION-only HW blocks. 5779adfc5217SJeff Kirsher */ 5780adfc5217SJeff Kirsher static inline void bnx2x_func_reset_func(struct bnx2x *bp, 5781adfc5217SJeff Kirsher const struct bnx2x_func_sp_drv_ops *drv) 5782adfc5217SJeff Kirsher { 5783adfc5217SJeff Kirsher drv->reset_hw_func(bp); 5784adfc5217SJeff Kirsher } 5785adfc5217SJeff Kirsher 5786adfc5217SJeff Kirsher /** 578716a5fd92SYuval Mintz * bnx2x_func_reset_port - reset HW at port stage 5788adfc5217SJeff Kirsher * 5789adfc5217SJeff Kirsher * @bp: device handle 5790adfc5217SJeff Kirsher * @drv: 5791adfc5217SJeff Kirsher * 5792adfc5217SJeff Kirsher * Reset HW at FW_MSG_CODE_DRV_UNLOAD_PORT stage: reset 5793adfc5217SJeff Kirsher * FUNCTION-only and PORT-only HW blocks. 5794adfc5217SJeff Kirsher * 5795adfc5217SJeff Kirsher * !!!IMPORTANT!!! 5796adfc5217SJeff Kirsher * 5797adfc5217SJeff Kirsher * It's important to call reset_port before reset_func() as the last thing 5798adfc5217SJeff Kirsher * reset_func does is pf_disable() thus disabling PGLUE_B, which 5799adfc5217SJeff Kirsher * makes impossible any DMAE transactions. 5800adfc5217SJeff Kirsher */ 5801adfc5217SJeff Kirsher static inline void bnx2x_func_reset_port(struct bnx2x *bp, 5802adfc5217SJeff Kirsher const struct bnx2x_func_sp_drv_ops *drv) 5803adfc5217SJeff Kirsher { 5804adfc5217SJeff Kirsher drv->reset_hw_port(bp); 5805adfc5217SJeff Kirsher bnx2x_func_reset_func(bp, drv); 5806adfc5217SJeff Kirsher } 5807adfc5217SJeff Kirsher 5808adfc5217SJeff Kirsher /** 580916a5fd92SYuval Mintz * bnx2x_func_reset_cmn - reset HW at common stage 5810adfc5217SJeff Kirsher * 5811adfc5217SJeff Kirsher * @bp: device handle 5812adfc5217SJeff Kirsher * @drv: 5813adfc5217SJeff Kirsher * 5814adfc5217SJeff Kirsher * Reset HW at FW_MSG_CODE_DRV_UNLOAD_COMMON and 5815adfc5217SJeff Kirsher * FW_MSG_CODE_DRV_UNLOAD_COMMON_CHIP stages: reset COMMON, 5816adfc5217SJeff Kirsher * COMMON_CHIP, FUNCTION-only and PORT-only HW blocks. 5817adfc5217SJeff Kirsher */ 5818adfc5217SJeff Kirsher static inline void bnx2x_func_reset_cmn(struct bnx2x *bp, 5819adfc5217SJeff Kirsher const struct bnx2x_func_sp_drv_ops *drv) 5820adfc5217SJeff Kirsher { 5821adfc5217SJeff Kirsher bnx2x_func_reset_port(bp, drv); 5822adfc5217SJeff Kirsher drv->reset_hw_cmn(bp); 5823adfc5217SJeff Kirsher } 5824adfc5217SJeff Kirsher 5825adfc5217SJeff Kirsher static inline int bnx2x_func_hw_reset(struct bnx2x *bp, 5826adfc5217SJeff Kirsher struct bnx2x_func_state_params *params) 5827adfc5217SJeff Kirsher { 5828adfc5217SJeff Kirsher u32 reset_phase = params->params.hw_reset.reset_phase; 5829adfc5217SJeff Kirsher struct bnx2x_func_sp_obj *o = params->f_obj; 5830adfc5217SJeff Kirsher const struct bnx2x_func_sp_drv_ops *drv = o->drv; 5831adfc5217SJeff Kirsher 5832adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "function %d reset_phase %x\n", BP_ABS_FUNC(bp), 5833adfc5217SJeff Kirsher reset_phase); 5834adfc5217SJeff Kirsher 5835adfc5217SJeff Kirsher switch (reset_phase) { 5836adfc5217SJeff Kirsher case FW_MSG_CODE_DRV_UNLOAD_COMMON: 5837adfc5217SJeff Kirsher bnx2x_func_reset_cmn(bp, drv); 5838adfc5217SJeff Kirsher break; 5839adfc5217SJeff Kirsher case FW_MSG_CODE_DRV_UNLOAD_PORT: 5840adfc5217SJeff Kirsher bnx2x_func_reset_port(bp, drv); 5841adfc5217SJeff Kirsher break; 5842adfc5217SJeff Kirsher case FW_MSG_CODE_DRV_UNLOAD_FUNCTION: 5843adfc5217SJeff Kirsher bnx2x_func_reset_func(bp, drv); 5844adfc5217SJeff Kirsher break; 5845adfc5217SJeff Kirsher default: 5846adfc5217SJeff Kirsher BNX2X_ERR("Unknown reset_phase (0x%x) from MCP\n", 5847adfc5217SJeff Kirsher reset_phase); 5848adfc5217SJeff Kirsher break; 5849adfc5217SJeff Kirsher } 5850adfc5217SJeff Kirsher 585116a5fd92SYuval Mintz /* Complete the command immediately: no ramrods have been sent. */ 5852adfc5217SJeff Kirsher o->complete_cmd(bp, o, BNX2X_F_CMD_HW_RESET); 5853adfc5217SJeff Kirsher 5854adfc5217SJeff Kirsher return 0; 5855adfc5217SJeff Kirsher } 5856adfc5217SJeff Kirsher 5857adfc5217SJeff Kirsher static inline int bnx2x_func_send_start(struct bnx2x *bp, 5858adfc5217SJeff Kirsher struct bnx2x_func_state_params *params) 5859adfc5217SJeff Kirsher { 5860adfc5217SJeff Kirsher struct bnx2x_func_sp_obj *o = params->f_obj; 5861adfc5217SJeff Kirsher struct function_start_data *rdata = 5862adfc5217SJeff Kirsher (struct function_start_data *)o->rdata; 5863adfc5217SJeff Kirsher dma_addr_t data_mapping = o->rdata_mapping; 5864adfc5217SJeff Kirsher struct bnx2x_func_start_params *start_params = ¶ms->params.start; 5865adfc5217SJeff Kirsher 5866adfc5217SJeff Kirsher memset(rdata, 0, sizeof(*rdata)); 5867adfc5217SJeff Kirsher 5868adfc5217SJeff Kirsher /* Fill the ramrod data with provided parameters */ 586996bed4b9SYuval Mintz rdata->function_mode = (u8)start_params->mf_mode; 5870ab4a7139SAriel Elior rdata->sd_vlan_tag = cpu_to_le16(start_params->sd_vlan_tag); 5871adfc5217SJeff Kirsher rdata->path_id = BP_PATH(bp); 5872adfc5217SJeff Kirsher rdata->network_cos_mode = start_params->network_cos_mode; 58731bc277f7SDmitry Kravkov rdata->gre_tunnel_mode = start_params->gre_tunnel_mode; 58741bc277f7SDmitry Kravkov rdata->gre_tunnel_rss = start_params->gre_tunnel_rss; 5875adfc5217SJeff Kirsher 58761bc277f7SDmitry Kravkov /* No need for an explicit memory barrier here as long we would 5877adfc5217SJeff Kirsher * need to ensure the ordering of writing to the SPQ element 5878adfc5217SJeff Kirsher * and updating of the SPQ producer which involves a memory 5879adfc5217SJeff Kirsher * read and we will have to put a full memory barrier there 5880adfc5217SJeff Kirsher * (inside bnx2x_sp_post()). 5881adfc5217SJeff Kirsher */ 5882adfc5217SJeff Kirsher 5883adfc5217SJeff Kirsher return bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_FUNCTION_START, 0, 5884adfc5217SJeff Kirsher U64_HI(data_mapping), 5885adfc5217SJeff Kirsher U64_LO(data_mapping), NONE_CONNECTION_TYPE); 5886adfc5217SJeff Kirsher } 5887adfc5217SJeff Kirsher 588855c11941SMerav Sicron static inline int bnx2x_func_send_switch_update(struct bnx2x *bp, 588955c11941SMerav Sicron struct bnx2x_func_state_params *params) 589055c11941SMerav Sicron { 589155c11941SMerav Sicron struct bnx2x_func_sp_obj *o = params->f_obj; 589255c11941SMerav Sicron struct function_update_data *rdata = 589355c11941SMerav Sicron (struct function_update_data *)o->rdata; 589455c11941SMerav Sicron dma_addr_t data_mapping = o->rdata_mapping; 589555c11941SMerav Sicron struct bnx2x_func_switch_update_params *switch_update_params = 589655c11941SMerav Sicron ¶ms->params.switch_update; 589755c11941SMerav Sicron 589855c11941SMerav Sicron memset(rdata, 0, sizeof(*rdata)); 589955c11941SMerav Sicron 590055c11941SMerav Sicron /* Fill the ramrod data with provided parameters */ 590155c11941SMerav Sicron rdata->tx_switch_suspend_change_flg = 1; 590255c11941SMerav Sicron rdata->tx_switch_suspend = switch_update_params->suspend; 590355c11941SMerav Sicron rdata->echo = SWITCH_UPDATE; 590455c11941SMerav Sicron 590555c11941SMerav Sicron return bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_FUNCTION_UPDATE, 0, 590655c11941SMerav Sicron U64_HI(data_mapping), 590755c11941SMerav Sicron U64_LO(data_mapping), NONE_CONNECTION_TYPE); 590855c11941SMerav Sicron } 590955c11941SMerav Sicron 5910a3348722SBarak Witkowski static inline int bnx2x_func_send_afex_update(struct bnx2x *bp, 5911a3348722SBarak Witkowski struct bnx2x_func_state_params *params) 5912a3348722SBarak Witkowski { 5913a3348722SBarak Witkowski struct bnx2x_func_sp_obj *o = params->f_obj; 5914a3348722SBarak Witkowski struct function_update_data *rdata = 5915a3348722SBarak Witkowski (struct function_update_data *)o->afex_rdata; 5916a3348722SBarak Witkowski dma_addr_t data_mapping = o->afex_rdata_mapping; 5917a3348722SBarak Witkowski struct bnx2x_func_afex_update_params *afex_update_params = 5918a3348722SBarak Witkowski ¶ms->params.afex_update; 5919a3348722SBarak Witkowski 5920a3348722SBarak Witkowski memset(rdata, 0, sizeof(*rdata)); 5921a3348722SBarak Witkowski 5922a3348722SBarak Witkowski /* Fill the ramrod data with provided parameters */ 5923a3348722SBarak Witkowski rdata->vif_id_change_flg = 1; 5924a3348722SBarak Witkowski rdata->vif_id = cpu_to_le16(afex_update_params->vif_id); 5925a3348722SBarak Witkowski rdata->afex_default_vlan_change_flg = 1; 5926a3348722SBarak Witkowski rdata->afex_default_vlan = 5927a3348722SBarak Witkowski cpu_to_le16(afex_update_params->afex_default_vlan); 5928a3348722SBarak Witkowski rdata->allowed_priorities_change_flg = 1; 5929a3348722SBarak Witkowski rdata->allowed_priorities = afex_update_params->allowed_priorities; 593055c11941SMerav Sicron rdata->echo = AFEX_UPDATE; 5931a3348722SBarak Witkowski 5932a3348722SBarak Witkowski /* No need for an explicit memory barrier here as long we would 5933a3348722SBarak Witkowski * need to ensure the ordering of writing to the SPQ element 5934a3348722SBarak Witkowski * and updating of the SPQ producer which involves a memory 5935a3348722SBarak Witkowski * read and we will have to put a full memory barrier there 5936a3348722SBarak Witkowski * (inside bnx2x_sp_post()). 5937a3348722SBarak Witkowski */ 5938a3348722SBarak Witkowski DP(BNX2X_MSG_SP, 5939a3348722SBarak Witkowski "afex: sending func_update vif_id 0x%x dvlan 0x%x prio 0x%x\n", 5940a3348722SBarak Witkowski rdata->vif_id, 5941a3348722SBarak Witkowski rdata->afex_default_vlan, rdata->allowed_priorities); 5942a3348722SBarak Witkowski 5943a3348722SBarak Witkowski return bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_FUNCTION_UPDATE, 0, 5944a3348722SBarak Witkowski U64_HI(data_mapping), 5945a3348722SBarak Witkowski U64_LO(data_mapping), NONE_CONNECTION_TYPE); 5946a3348722SBarak Witkowski } 5947a3348722SBarak Witkowski 5948a3348722SBarak Witkowski static 5949a3348722SBarak Witkowski inline int bnx2x_func_send_afex_viflists(struct bnx2x *bp, 5950a3348722SBarak Witkowski struct bnx2x_func_state_params *params) 5951a3348722SBarak Witkowski { 5952a3348722SBarak Witkowski struct bnx2x_func_sp_obj *o = params->f_obj; 5953a3348722SBarak Witkowski struct afex_vif_list_ramrod_data *rdata = 5954a3348722SBarak Witkowski (struct afex_vif_list_ramrod_data *)o->afex_rdata; 595586564c3fSYuval Mintz struct bnx2x_func_afex_viflists_params *afex_vif_params = 5956a3348722SBarak Witkowski ¶ms->params.afex_viflists; 5957a3348722SBarak Witkowski u64 *p_rdata = (u64 *)rdata; 5958a3348722SBarak Witkowski 5959a3348722SBarak Witkowski memset(rdata, 0, sizeof(*rdata)); 5960a3348722SBarak Witkowski 5961a3348722SBarak Witkowski /* Fill the ramrod data with provided parameters */ 596286564c3fSYuval Mintz rdata->vif_list_index = cpu_to_le16(afex_vif_params->vif_list_index); 596386564c3fSYuval Mintz rdata->func_bit_map = afex_vif_params->func_bit_map; 596486564c3fSYuval Mintz rdata->afex_vif_list_command = afex_vif_params->afex_vif_list_command; 596586564c3fSYuval Mintz rdata->func_to_clear = afex_vif_params->func_to_clear; 5966a3348722SBarak Witkowski 5967a3348722SBarak Witkowski /* send in echo type of sub command */ 596886564c3fSYuval Mintz rdata->echo = afex_vif_params->afex_vif_list_command; 5969a3348722SBarak Witkowski 5970a3348722SBarak Witkowski /* No need for an explicit memory barrier here as long we would 5971a3348722SBarak Witkowski * need to ensure the ordering of writing to the SPQ element 5972a3348722SBarak Witkowski * and updating of the SPQ producer which involves a memory 5973a3348722SBarak Witkowski * read and we will have to put a full memory barrier there 5974a3348722SBarak Witkowski * (inside bnx2x_sp_post()). 5975a3348722SBarak Witkowski */ 5976a3348722SBarak Witkowski 5977a3348722SBarak Witkowski DP(BNX2X_MSG_SP, "afex: ramrod lists, cmd 0x%x index 0x%x func_bit_map 0x%x func_to_clr 0x%x\n", 5978a3348722SBarak Witkowski rdata->afex_vif_list_command, rdata->vif_list_index, 5979a3348722SBarak Witkowski rdata->func_bit_map, rdata->func_to_clear); 5980a3348722SBarak Witkowski 5981a3348722SBarak Witkowski /* this ramrod sends data directly and not through DMA mapping */ 5982a3348722SBarak Witkowski return bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_AFEX_VIF_LISTS, 0, 5983a3348722SBarak Witkowski U64_HI(*p_rdata), U64_LO(*p_rdata), 5984a3348722SBarak Witkowski NONE_CONNECTION_TYPE); 5985a3348722SBarak Witkowski } 5986a3348722SBarak Witkowski 5987adfc5217SJeff Kirsher static inline int bnx2x_func_send_stop(struct bnx2x *bp, 5988adfc5217SJeff Kirsher struct bnx2x_func_state_params *params) 5989adfc5217SJeff Kirsher { 5990adfc5217SJeff Kirsher return bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_FUNCTION_STOP, 0, 0, 0, 5991adfc5217SJeff Kirsher NONE_CONNECTION_TYPE); 5992adfc5217SJeff Kirsher } 5993adfc5217SJeff Kirsher 5994adfc5217SJeff Kirsher static inline int bnx2x_func_send_tx_stop(struct bnx2x *bp, 5995adfc5217SJeff Kirsher struct bnx2x_func_state_params *params) 5996adfc5217SJeff Kirsher { 5997adfc5217SJeff Kirsher return bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_STOP_TRAFFIC, 0, 0, 0, 5998adfc5217SJeff Kirsher NONE_CONNECTION_TYPE); 5999adfc5217SJeff Kirsher } 6000adfc5217SJeff Kirsher static inline int bnx2x_func_send_tx_start(struct bnx2x *bp, 6001adfc5217SJeff Kirsher struct bnx2x_func_state_params *params) 6002adfc5217SJeff Kirsher { 6003adfc5217SJeff Kirsher struct bnx2x_func_sp_obj *o = params->f_obj; 6004adfc5217SJeff Kirsher struct flow_control_configuration *rdata = 6005adfc5217SJeff Kirsher (struct flow_control_configuration *)o->rdata; 6006adfc5217SJeff Kirsher dma_addr_t data_mapping = o->rdata_mapping; 6007adfc5217SJeff Kirsher struct bnx2x_func_tx_start_params *tx_start_params = 6008adfc5217SJeff Kirsher ¶ms->params.tx_start; 6009adfc5217SJeff Kirsher int i; 6010adfc5217SJeff Kirsher 6011adfc5217SJeff Kirsher memset(rdata, 0, sizeof(*rdata)); 6012adfc5217SJeff Kirsher 6013adfc5217SJeff Kirsher rdata->dcb_enabled = tx_start_params->dcb_enabled; 6014adfc5217SJeff Kirsher rdata->dcb_version = tx_start_params->dcb_version; 6015adfc5217SJeff Kirsher rdata->dont_add_pri_0_en = tx_start_params->dont_add_pri_0_en; 6016adfc5217SJeff Kirsher 6017adfc5217SJeff Kirsher for (i = 0; i < ARRAY_SIZE(rdata->traffic_type_to_priority_cos); i++) 6018adfc5217SJeff Kirsher rdata->traffic_type_to_priority_cos[i] = 6019adfc5217SJeff Kirsher tx_start_params->traffic_type_to_priority_cos[i]; 6020adfc5217SJeff Kirsher 6021adfc5217SJeff Kirsher return bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_START_TRAFFIC, 0, 6022adfc5217SJeff Kirsher U64_HI(data_mapping), 6023adfc5217SJeff Kirsher U64_LO(data_mapping), NONE_CONNECTION_TYPE); 6024adfc5217SJeff Kirsher } 6025adfc5217SJeff Kirsher 6026adfc5217SJeff Kirsher static int bnx2x_func_send_cmd(struct bnx2x *bp, 6027adfc5217SJeff Kirsher struct bnx2x_func_state_params *params) 6028adfc5217SJeff Kirsher { 6029adfc5217SJeff Kirsher switch (params->cmd) { 6030adfc5217SJeff Kirsher case BNX2X_F_CMD_HW_INIT: 6031adfc5217SJeff Kirsher return bnx2x_func_hw_init(bp, params); 6032adfc5217SJeff Kirsher case BNX2X_F_CMD_START: 6033adfc5217SJeff Kirsher return bnx2x_func_send_start(bp, params); 6034adfc5217SJeff Kirsher case BNX2X_F_CMD_STOP: 6035adfc5217SJeff Kirsher return bnx2x_func_send_stop(bp, params); 6036adfc5217SJeff Kirsher case BNX2X_F_CMD_HW_RESET: 6037adfc5217SJeff Kirsher return bnx2x_func_hw_reset(bp, params); 6038a3348722SBarak Witkowski case BNX2X_F_CMD_AFEX_UPDATE: 6039a3348722SBarak Witkowski return bnx2x_func_send_afex_update(bp, params); 6040a3348722SBarak Witkowski case BNX2X_F_CMD_AFEX_VIFLISTS: 6041a3348722SBarak Witkowski return bnx2x_func_send_afex_viflists(bp, params); 6042adfc5217SJeff Kirsher case BNX2X_F_CMD_TX_STOP: 6043adfc5217SJeff Kirsher return bnx2x_func_send_tx_stop(bp, params); 6044adfc5217SJeff Kirsher case BNX2X_F_CMD_TX_START: 6045adfc5217SJeff Kirsher return bnx2x_func_send_tx_start(bp, params); 604655c11941SMerav Sicron case BNX2X_F_CMD_SWITCH_UPDATE: 604755c11941SMerav Sicron return bnx2x_func_send_switch_update(bp, params); 6048adfc5217SJeff Kirsher default: 6049adfc5217SJeff Kirsher BNX2X_ERR("Unknown command: %d\n", params->cmd); 6050adfc5217SJeff Kirsher return -EINVAL; 6051adfc5217SJeff Kirsher } 6052adfc5217SJeff Kirsher } 6053adfc5217SJeff Kirsher 6054adfc5217SJeff Kirsher void bnx2x_init_func_obj(struct bnx2x *bp, 6055adfc5217SJeff Kirsher struct bnx2x_func_sp_obj *obj, 6056adfc5217SJeff Kirsher void *rdata, dma_addr_t rdata_mapping, 6057a3348722SBarak Witkowski void *afex_rdata, dma_addr_t afex_rdata_mapping, 6058adfc5217SJeff Kirsher struct bnx2x_func_sp_drv_ops *drv_iface) 6059adfc5217SJeff Kirsher { 6060adfc5217SJeff Kirsher memset(obj, 0, sizeof(*obj)); 6061adfc5217SJeff Kirsher 6062adfc5217SJeff Kirsher mutex_init(&obj->one_pending_mutex); 6063adfc5217SJeff Kirsher 6064adfc5217SJeff Kirsher obj->rdata = rdata; 6065adfc5217SJeff Kirsher obj->rdata_mapping = rdata_mapping; 6066a3348722SBarak Witkowski obj->afex_rdata = afex_rdata; 6067a3348722SBarak Witkowski obj->afex_rdata_mapping = afex_rdata_mapping; 6068adfc5217SJeff Kirsher obj->send_cmd = bnx2x_func_send_cmd; 6069adfc5217SJeff Kirsher obj->check_transition = bnx2x_func_chk_transition; 6070adfc5217SJeff Kirsher obj->complete_cmd = bnx2x_func_comp_cmd; 6071adfc5217SJeff Kirsher obj->wait_comp = bnx2x_func_wait_comp; 6072adfc5217SJeff Kirsher 6073adfc5217SJeff Kirsher obj->drv = drv_iface; 6074adfc5217SJeff Kirsher } 6075adfc5217SJeff Kirsher 6076adfc5217SJeff Kirsher /** 6077adfc5217SJeff Kirsher * bnx2x_func_state_change - perform Function state change transition 6078adfc5217SJeff Kirsher * 6079adfc5217SJeff Kirsher * @bp: device handle 6080adfc5217SJeff Kirsher * @params: parameters to perform the transaction 6081adfc5217SJeff Kirsher * 6082adfc5217SJeff Kirsher * returns 0 in case of successfully completed transition, 6083adfc5217SJeff Kirsher * negative error code in case of failure, positive 6084adfc5217SJeff Kirsher * (EBUSY) value if there is a completion to that is 6085adfc5217SJeff Kirsher * still pending (possible only if RAMROD_COMP_WAIT is 6086adfc5217SJeff Kirsher * not set in params->ramrod_flags for asynchronous 6087adfc5217SJeff Kirsher * commands). 6088adfc5217SJeff Kirsher */ 6089adfc5217SJeff Kirsher int bnx2x_func_state_change(struct bnx2x *bp, 6090adfc5217SJeff Kirsher struct bnx2x_func_state_params *params) 6091adfc5217SJeff Kirsher { 6092adfc5217SJeff Kirsher struct bnx2x_func_sp_obj *o = params->f_obj; 609355c11941SMerav Sicron int rc, cnt = 300; 6094adfc5217SJeff Kirsher enum bnx2x_func_cmd cmd = params->cmd; 6095adfc5217SJeff Kirsher unsigned long *pending = &o->pending; 6096adfc5217SJeff Kirsher 6097adfc5217SJeff Kirsher mutex_lock(&o->one_pending_mutex); 6098adfc5217SJeff Kirsher 6099adfc5217SJeff Kirsher /* Check that the requested transition is legal */ 610055c11941SMerav Sicron rc = o->check_transition(bp, o, params); 610155c11941SMerav Sicron if ((rc == -EBUSY) && 610255c11941SMerav Sicron (test_bit(RAMROD_RETRY, ¶ms->ramrod_flags))) { 610355c11941SMerav Sicron while ((rc == -EBUSY) && (--cnt > 0)) { 6104adfc5217SJeff Kirsher mutex_unlock(&o->one_pending_mutex); 610555c11941SMerav Sicron msleep(10); 610655c11941SMerav Sicron mutex_lock(&o->one_pending_mutex); 610755c11941SMerav Sicron rc = o->check_transition(bp, o, params); 610855c11941SMerav Sicron } 610955c11941SMerav Sicron if (rc == -EBUSY) { 611055c11941SMerav Sicron mutex_unlock(&o->one_pending_mutex); 611155c11941SMerav Sicron BNX2X_ERR("timeout waiting for previous ramrod completion\n"); 611255c11941SMerav Sicron return rc; 611355c11941SMerav Sicron } 611455c11941SMerav Sicron } else if (rc) { 611555c11941SMerav Sicron mutex_unlock(&o->one_pending_mutex); 611655c11941SMerav Sicron return rc; 6117adfc5217SJeff Kirsher } 6118adfc5217SJeff Kirsher 6119adfc5217SJeff Kirsher /* Set "pending" bit */ 6120adfc5217SJeff Kirsher set_bit(cmd, pending); 6121adfc5217SJeff Kirsher 6122adfc5217SJeff Kirsher /* Don't send a command if only driver cleanup was requested */ 6123adfc5217SJeff Kirsher if (test_bit(RAMROD_DRV_CLR_ONLY, ¶ms->ramrod_flags)) { 6124adfc5217SJeff Kirsher bnx2x_func_state_change_comp(bp, o, cmd); 6125adfc5217SJeff Kirsher mutex_unlock(&o->one_pending_mutex); 6126adfc5217SJeff Kirsher } else { 6127adfc5217SJeff Kirsher /* Send a ramrod */ 6128adfc5217SJeff Kirsher rc = o->send_cmd(bp, params); 6129adfc5217SJeff Kirsher 6130adfc5217SJeff Kirsher mutex_unlock(&o->one_pending_mutex); 6131adfc5217SJeff Kirsher 6132adfc5217SJeff Kirsher if (rc) { 6133adfc5217SJeff Kirsher o->next_state = BNX2X_F_STATE_MAX; 6134adfc5217SJeff Kirsher clear_bit(cmd, pending); 6135adfc5217SJeff Kirsher smp_mb__after_clear_bit(); 6136adfc5217SJeff Kirsher return rc; 6137adfc5217SJeff Kirsher } 6138adfc5217SJeff Kirsher 6139adfc5217SJeff Kirsher if (test_bit(RAMROD_COMP_WAIT, ¶ms->ramrod_flags)) { 6140adfc5217SJeff Kirsher rc = o->wait_comp(bp, o, cmd); 6141adfc5217SJeff Kirsher if (rc) 6142adfc5217SJeff Kirsher return rc; 6143adfc5217SJeff Kirsher 6144adfc5217SJeff Kirsher return 0; 6145adfc5217SJeff Kirsher } 6146adfc5217SJeff Kirsher } 6147adfc5217SJeff Kirsher 6148adfc5217SJeff Kirsher return !!test_bit(cmd, pending); 6149adfc5217SJeff Kirsher } 6150