1adfc5217SJeff Kirsher /* bnx2x_sp.c: Broadcom Everest network driver. 2adfc5217SJeff Kirsher * 3247fa82bSYuval Mintz * Copyright (c) 2011-2013 Broadcom Corporation 4adfc5217SJeff Kirsher * 5adfc5217SJeff Kirsher * Unless you and Broadcom execute a separate written software license 6adfc5217SJeff Kirsher * agreement governing use of this software, this software is licensed to you 7adfc5217SJeff Kirsher * under the terms of the GNU General Public License version 2, available 8adfc5217SJeff Kirsher * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL"). 9adfc5217SJeff Kirsher * 10adfc5217SJeff Kirsher * Notwithstanding the above, under no circumstances may you combine this 11adfc5217SJeff Kirsher * software in any way with any other Broadcom software provided under a 12adfc5217SJeff Kirsher * license other than the GPL, without Broadcom's express prior written 13adfc5217SJeff Kirsher * consent. 14adfc5217SJeff Kirsher * 15adfc5217SJeff Kirsher * Maintained by: Eilon Greenstein <eilong@broadcom.com> 16adfc5217SJeff Kirsher * Written by: Vladislav Zolotarov 17adfc5217SJeff Kirsher * 18adfc5217SJeff Kirsher */ 19f1deab50SJoe Perches 20f1deab50SJoe Perches #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 21f1deab50SJoe Perches 22adfc5217SJeff Kirsher #include <linux/module.h> 23adfc5217SJeff Kirsher #include <linux/crc32.h> 24adfc5217SJeff Kirsher #include <linux/netdevice.h> 25adfc5217SJeff Kirsher #include <linux/etherdevice.h> 26adfc5217SJeff Kirsher #include <linux/crc32c.h> 27adfc5217SJeff Kirsher #include "bnx2x.h" 28adfc5217SJeff Kirsher #include "bnx2x_cmn.h" 29adfc5217SJeff Kirsher #include "bnx2x_sp.h" 30adfc5217SJeff Kirsher 31adfc5217SJeff Kirsher #define BNX2X_MAX_EMUL_MULTI 16 32adfc5217SJeff Kirsher 33adfc5217SJeff Kirsher /**** Exe Queue interfaces ****/ 34adfc5217SJeff Kirsher 35adfc5217SJeff Kirsher /** 36adfc5217SJeff Kirsher * bnx2x_exe_queue_init - init the Exe Queue object 37adfc5217SJeff Kirsher * 3816a5fd92SYuval Mintz * @o: pointer to the object 39adfc5217SJeff Kirsher * @exe_len: length 4016a5fd92SYuval Mintz * @owner: pointer to the owner 41adfc5217SJeff Kirsher * @validate: validate function pointer 42adfc5217SJeff Kirsher * @optimize: optimize function pointer 43adfc5217SJeff Kirsher * @exec: execute function pointer 44adfc5217SJeff Kirsher * @get: get function pointer 45adfc5217SJeff Kirsher */ 46adfc5217SJeff Kirsher static inline void bnx2x_exe_queue_init(struct bnx2x *bp, 47adfc5217SJeff Kirsher struct bnx2x_exe_queue_obj *o, 48adfc5217SJeff Kirsher int exe_len, 49adfc5217SJeff Kirsher union bnx2x_qable_obj *owner, 50adfc5217SJeff Kirsher exe_q_validate validate, 51460a25cdSYuval Mintz exe_q_remove remove, 52adfc5217SJeff Kirsher exe_q_optimize optimize, 53adfc5217SJeff Kirsher exe_q_execute exec, 54adfc5217SJeff Kirsher exe_q_get get) 55adfc5217SJeff Kirsher { 56adfc5217SJeff Kirsher memset(o, 0, sizeof(*o)); 57adfc5217SJeff Kirsher 58adfc5217SJeff Kirsher INIT_LIST_HEAD(&o->exe_queue); 59adfc5217SJeff Kirsher INIT_LIST_HEAD(&o->pending_comp); 60adfc5217SJeff Kirsher 61adfc5217SJeff Kirsher spin_lock_init(&o->lock); 62adfc5217SJeff Kirsher 63adfc5217SJeff Kirsher o->exe_chunk_len = exe_len; 64adfc5217SJeff Kirsher o->owner = owner; 65adfc5217SJeff Kirsher 66adfc5217SJeff Kirsher /* Owner specific callbacks */ 67adfc5217SJeff Kirsher o->validate = validate; 68460a25cdSYuval Mintz o->remove = remove; 69adfc5217SJeff Kirsher o->optimize = optimize; 70adfc5217SJeff Kirsher o->execute = exec; 71adfc5217SJeff Kirsher o->get = get; 72adfc5217SJeff Kirsher 7351c1a580SMerav Sicron DP(BNX2X_MSG_SP, "Setup the execution queue with the chunk length of %d\n", 7451c1a580SMerav Sicron exe_len); 75adfc5217SJeff Kirsher } 76adfc5217SJeff Kirsher 77adfc5217SJeff Kirsher static inline void bnx2x_exe_queue_free_elem(struct bnx2x *bp, 78adfc5217SJeff Kirsher struct bnx2x_exeq_elem *elem) 79adfc5217SJeff Kirsher { 80adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "Deleting an exe_queue element\n"); 81adfc5217SJeff Kirsher kfree(elem); 82adfc5217SJeff Kirsher } 83adfc5217SJeff Kirsher 84adfc5217SJeff Kirsher static inline int bnx2x_exe_queue_length(struct bnx2x_exe_queue_obj *o) 85adfc5217SJeff Kirsher { 86adfc5217SJeff Kirsher struct bnx2x_exeq_elem *elem; 87adfc5217SJeff Kirsher int cnt = 0; 88adfc5217SJeff Kirsher 89adfc5217SJeff Kirsher spin_lock_bh(&o->lock); 90adfc5217SJeff Kirsher 91adfc5217SJeff Kirsher list_for_each_entry(elem, &o->exe_queue, link) 92adfc5217SJeff Kirsher cnt++; 93adfc5217SJeff Kirsher 94adfc5217SJeff Kirsher spin_unlock_bh(&o->lock); 95adfc5217SJeff Kirsher 96adfc5217SJeff Kirsher return cnt; 97adfc5217SJeff Kirsher } 98adfc5217SJeff Kirsher 99adfc5217SJeff Kirsher /** 100adfc5217SJeff Kirsher * bnx2x_exe_queue_add - add a new element to the execution queue 101adfc5217SJeff Kirsher * 102adfc5217SJeff Kirsher * @bp: driver handle 103adfc5217SJeff Kirsher * @o: queue 104adfc5217SJeff Kirsher * @cmd: new command to add 105adfc5217SJeff Kirsher * @restore: true - do not optimize the command 106adfc5217SJeff Kirsher * 107adfc5217SJeff Kirsher * If the element is optimized or is illegal, frees it. 108adfc5217SJeff Kirsher */ 109adfc5217SJeff Kirsher static inline int bnx2x_exe_queue_add(struct bnx2x *bp, 110adfc5217SJeff Kirsher struct bnx2x_exe_queue_obj *o, 111adfc5217SJeff Kirsher struct bnx2x_exeq_elem *elem, 112adfc5217SJeff Kirsher bool restore) 113adfc5217SJeff Kirsher { 114adfc5217SJeff Kirsher int rc; 115adfc5217SJeff Kirsher 116adfc5217SJeff Kirsher spin_lock_bh(&o->lock); 117adfc5217SJeff Kirsher 118adfc5217SJeff Kirsher if (!restore) { 119adfc5217SJeff Kirsher /* Try to cancel this element queue */ 120adfc5217SJeff Kirsher rc = o->optimize(bp, o->owner, elem); 121adfc5217SJeff Kirsher if (rc) 122adfc5217SJeff Kirsher goto free_and_exit; 123adfc5217SJeff Kirsher 124adfc5217SJeff Kirsher /* Check if this request is ok */ 125adfc5217SJeff Kirsher rc = o->validate(bp, o->owner, elem); 126adfc5217SJeff Kirsher if (rc) { 1272384d6aaSDmitry Kravkov DP(BNX2X_MSG_SP, "Preamble failed: %d\n", rc); 128adfc5217SJeff Kirsher goto free_and_exit; 129adfc5217SJeff Kirsher } 130adfc5217SJeff Kirsher } 131adfc5217SJeff Kirsher 132adfc5217SJeff Kirsher /* If so, add it to the execution queue */ 133adfc5217SJeff Kirsher list_add_tail(&elem->link, &o->exe_queue); 134adfc5217SJeff Kirsher 135adfc5217SJeff Kirsher spin_unlock_bh(&o->lock); 136adfc5217SJeff Kirsher 137adfc5217SJeff Kirsher return 0; 138adfc5217SJeff Kirsher 139adfc5217SJeff Kirsher free_and_exit: 140adfc5217SJeff Kirsher bnx2x_exe_queue_free_elem(bp, elem); 141adfc5217SJeff Kirsher 142adfc5217SJeff Kirsher spin_unlock_bh(&o->lock); 143adfc5217SJeff Kirsher 144adfc5217SJeff Kirsher return rc; 145adfc5217SJeff Kirsher } 146adfc5217SJeff Kirsher 147adfc5217SJeff Kirsher static inline void __bnx2x_exe_queue_reset_pending( 148adfc5217SJeff Kirsher struct bnx2x *bp, 149adfc5217SJeff Kirsher struct bnx2x_exe_queue_obj *o) 150adfc5217SJeff Kirsher { 151adfc5217SJeff Kirsher struct bnx2x_exeq_elem *elem; 152adfc5217SJeff Kirsher 153adfc5217SJeff Kirsher while (!list_empty(&o->pending_comp)) { 154adfc5217SJeff Kirsher elem = list_first_entry(&o->pending_comp, 155adfc5217SJeff Kirsher struct bnx2x_exeq_elem, link); 156adfc5217SJeff Kirsher 157adfc5217SJeff Kirsher list_del(&elem->link); 158adfc5217SJeff Kirsher bnx2x_exe_queue_free_elem(bp, elem); 159adfc5217SJeff Kirsher } 160adfc5217SJeff Kirsher } 161adfc5217SJeff Kirsher 162adfc5217SJeff Kirsher /** 163adfc5217SJeff Kirsher * bnx2x_exe_queue_step - execute one execution chunk atomically 164adfc5217SJeff Kirsher * 165adfc5217SJeff Kirsher * @bp: driver handle 166adfc5217SJeff Kirsher * @o: queue 167adfc5217SJeff Kirsher * @ramrod_flags: flags 168adfc5217SJeff Kirsher * 1698b09be5fSYuval Mintz * (Should be called while holding the exe_queue->lock). 170adfc5217SJeff Kirsher */ 171adfc5217SJeff Kirsher static inline int bnx2x_exe_queue_step(struct bnx2x *bp, 172adfc5217SJeff Kirsher struct bnx2x_exe_queue_obj *o, 173adfc5217SJeff Kirsher unsigned long *ramrod_flags) 174adfc5217SJeff Kirsher { 175adfc5217SJeff Kirsher struct bnx2x_exeq_elem *elem, spacer; 176adfc5217SJeff Kirsher int cur_len = 0, rc; 177adfc5217SJeff Kirsher 178adfc5217SJeff Kirsher memset(&spacer, 0, sizeof(spacer)); 179adfc5217SJeff Kirsher 18016a5fd92SYuval Mintz /* Next step should not be performed until the current is finished, 181adfc5217SJeff Kirsher * unless a DRV_CLEAR_ONLY bit is set. In this case we just want to 182adfc5217SJeff Kirsher * properly clear object internals without sending any command to the FW 183adfc5217SJeff Kirsher * which also implies there won't be any completion to clear the 184adfc5217SJeff Kirsher * 'pending' list. 185adfc5217SJeff Kirsher */ 186adfc5217SJeff Kirsher if (!list_empty(&o->pending_comp)) { 187adfc5217SJeff Kirsher if (test_bit(RAMROD_DRV_CLR_ONLY, ramrod_flags)) { 18851c1a580SMerav Sicron DP(BNX2X_MSG_SP, "RAMROD_DRV_CLR_ONLY requested: resetting a pending_comp list\n"); 189adfc5217SJeff Kirsher __bnx2x_exe_queue_reset_pending(bp, o); 190adfc5217SJeff Kirsher } else { 191adfc5217SJeff Kirsher return 1; 192adfc5217SJeff Kirsher } 193adfc5217SJeff Kirsher } 194adfc5217SJeff Kirsher 19516a5fd92SYuval Mintz /* Run through the pending commands list and create a next 196adfc5217SJeff Kirsher * execution chunk. 197adfc5217SJeff Kirsher */ 198adfc5217SJeff Kirsher while (!list_empty(&o->exe_queue)) { 199adfc5217SJeff Kirsher elem = list_first_entry(&o->exe_queue, struct bnx2x_exeq_elem, 200adfc5217SJeff Kirsher link); 201adfc5217SJeff Kirsher WARN_ON(!elem->cmd_len); 202adfc5217SJeff Kirsher 203adfc5217SJeff Kirsher if (cur_len + elem->cmd_len <= o->exe_chunk_len) { 204adfc5217SJeff Kirsher cur_len += elem->cmd_len; 20516a5fd92SYuval Mintz /* Prevent from both lists being empty when moving an 206adfc5217SJeff Kirsher * element. This will allow the call of 207adfc5217SJeff Kirsher * bnx2x_exe_queue_empty() without locking. 208adfc5217SJeff Kirsher */ 209adfc5217SJeff Kirsher list_add_tail(&spacer.link, &o->pending_comp); 210adfc5217SJeff Kirsher mb(); 2117933aa5cSWei Yongjun list_move_tail(&elem->link, &o->pending_comp); 212adfc5217SJeff Kirsher list_del(&spacer.link); 213adfc5217SJeff Kirsher } else 214adfc5217SJeff Kirsher break; 215adfc5217SJeff Kirsher } 216adfc5217SJeff Kirsher 217adfc5217SJeff Kirsher /* Sanity check */ 2188b09be5fSYuval Mintz if (!cur_len) 219adfc5217SJeff Kirsher return 0; 220adfc5217SJeff Kirsher 221adfc5217SJeff Kirsher rc = o->execute(bp, o->owner, &o->pending_comp, ramrod_flags); 222adfc5217SJeff Kirsher if (rc < 0) 22316a5fd92SYuval Mintz /* In case of an error return the commands back to the queue 224adfc5217SJeff Kirsher * and reset the pending_comp. 225adfc5217SJeff Kirsher */ 226adfc5217SJeff Kirsher list_splice_init(&o->pending_comp, &o->exe_queue); 227adfc5217SJeff Kirsher else if (!rc) 22816a5fd92SYuval Mintz /* If zero is returned, means there are no outstanding pending 229adfc5217SJeff Kirsher * completions and we may dismiss the pending list. 230adfc5217SJeff Kirsher */ 231adfc5217SJeff Kirsher __bnx2x_exe_queue_reset_pending(bp, o); 232adfc5217SJeff Kirsher 233adfc5217SJeff Kirsher return rc; 234adfc5217SJeff Kirsher } 235adfc5217SJeff Kirsher 236adfc5217SJeff Kirsher static inline bool bnx2x_exe_queue_empty(struct bnx2x_exe_queue_obj *o) 237adfc5217SJeff Kirsher { 238adfc5217SJeff Kirsher bool empty = list_empty(&o->exe_queue); 239adfc5217SJeff Kirsher 240adfc5217SJeff Kirsher /* Don't reorder!!! */ 241adfc5217SJeff Kirsher mb(); 242adfc5217SJeff Kirsher 243adfc5217SJeff Kirsher return empty && list_empty(&o->pending_comp); 244adfc5217SJeff Kirsher } 245adfc5217SJeff Kirsher 246adfc5217SJeff Kirsher static inline struct bnx2x_exeq_elem *bnx2x_exe_queue_alloc_elem( 247adfc5217SJeff Kirsher struct bnx2x *bp) 248adfc5217SJeff Kirsher { 249adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "Allocating a new exe_queue element\n"); 250adfc5217SJeff Kirsher return kzalloc(sizeof(struct bnx2x_exeq_elem), GFP_ATOMIC); 251adfc5217SJeff Kirsher } 252adfc5217SJeff Kirsher 253adfc5217SJeff Kirsher /************************ raw_obj functions ***********************************/ 254adfc5217SJeff Kirsher static bool bnx2x_raw_check_pending(struct bnx2x_raw_obj *o) 255adfc5217SJeff Kirsher { 256adfc5217SJeff Kirsher return !!test_bit(o->state, o->pstate); 257adfc5217SJeff Kirsher } 258adfc5217SJeff Kirsher 259adfc5217SJeff Kirsher static void bnx2x_raw_clear_pending(struct bnx2x_raw_obj *o) 260adfc5217SJeff Kirsher { 261adfc5217SJeff Kirsher smp_mb__before_clear_bit(); 262adfc5217SJeff Kirsher clear_bit(o->state, o->pstate); 263adfc5217SJeff Kirsher smp_mb__after_clear_bit(); 264adfc5217SJeff Kirsher } 265adfc5217SJeff Kirsher 266adfc5217SJeff Kirsher static void bnx2x_raw_set_pending(struct bnx2x_raw_obj *o) 267adfc5217SJeff Kirsher { 268adfc5217SJeff Kirsher smp_mb__before_clear_bit(); 269adfc5217SJeff Kirsher set_bit(o->state, o->pstate); 270adfc5217SJeff Kirsher smp_mb__after_clear_bit(); 271adfc5217SJeff Kirsher } 272adfc5217SJeff Kirsher 273adfc5217SJeff Kirsher /** 274adfc5217SJeff Kirsher * bnx2x_state_wait - wait until the given bit(state) is cleared 275adfc5217SJeff Kirsher * 276adfc5217SJeff Kirsher * @bp: device handle 277adfc5217SJeff Kirsher * @state: state which is to be cleared 278adfc5217SJeff Kirsher * @state_p: state buffer 279adfc5217SJeff Kirsher * 280adfc5217SJeff Kirsher */ 281adfc5217SJeff Kirsher static inline int bnx2x_state_wait(struct bnx2x *bp, int state, 282adfc5217SJeff Kirsher unsigned long *pstate) 283adfc5217SJeff Kirsher { 284adfc5217SJeff Kirsher /* can take a while if any port is running */ 285adfc5217SJeff Kirsher int cnt = 5000; 286adfc5217SJeff Kirsher 287adfc5217SJeff Kirsher if (CHIP_REV_IS_EMUL(bp)) 288adfc5217SJeff Kirsher cnt *= 20; 289adfc5217SJeff Kirsher 290adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "waiting for state to become %d\n", state); 291adfc5217SJeff Kirsher 292adfc5217SJeff Kirsher might_sleep(); 293adfc5217SJeff Kirsher while (cnt--) { 294adfc5217SJeff Kirsher if (!test_bit(state, pstate)) { 295adfc5217SJeff Kirsher #ifdef BNX2X_STOP_ON_ERROR 296adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "exit (cnt %d)\n", 5000 - cnt); 297adfc5217SJeff Kirsher #endif 298adfc5217SJeff Kirsher return 0; 299adfc5217SJeff Kirsher } 300adfc5217SJeff Kirsher 3010926d499SYuval Mintz usleep_range(1000, 2000); 302adfc5217SJeff Kirsher 303adfc5217SJeff Kirsher if (bp->panic) 304adfc5217SJeff Kirsher return -EIO; 305adfc5217SJeff Kirsher } 306adfc5217SJeff Kirsher 307adfc5217SJeff Kirsher /* timeout! */ 308adfc5217SJeff Kirsher BNX2X_ERR("timeout waiting for state %d\n", state); 309adfc5217SJeff Kirsher #ifdef BNX2X_STOP_ON_ERROR 310adfc5217SJeff Kirsher bnx2x_panic(); 311adfc5217SJeff Kirsher #endif 312adfc5217SJeff Kirsher 313adfc5217SJeff Kirsher return -EBUSY; 314adfc5217SJeff Kirsher } 315adfc5217SJeff Kirsher 316adfc5217SJeff Kirsher static int bnx2x_raw_wait(struct bnx2x *bp, struct bnx2x_raw_obj *raw) 317adfc5217SJeff Kirsher { 318adfc5217SJeff Kirsher return bnx2x_state_wait(bp, raw->state, raw->pstate); 319adfc5217SJeff Kirsher } 320adfc5217SJeff Kirsher 321adfc5217SJeff Kirsher /***************** Classification verbs: Set/Del MAC/VLAN/VLAN-MAC ************/ 322adfc5217SJeff Kirsher /* credit handling callbacks */ 323adfc5217SJeff Kirsher static bool bnx2x_get_cam_offset_mac(struct bnx2x_vlan_mac_obj *o, int *offset) 324adfc5217SJeff Kirsher { 325adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *mp = o->macs_pool; 326adfc5217SJeff Kirsher 327adfc5217SJeff Kirsher WARN_ON(!mp); 328adfc5217SJeff Kirsher 329adfc5217SJeff Kirsher return mp->get_entry(mp, offset); 330adfc5217SJeff Kirsher } 331adfc5217SJeff Kirsher 332adfc5217SJeff Kirsher static bool bnx2x_get_credit_mac(struct bnx2x_vlan_mac_obj *o) 333adfc5217SJeff Kirsher { 334adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *mp = o->macs_pool; 335adfc5217SJeff Kirsher 336adfc5217SJeff Kirsher WARN_ON(!mp); 337adfc5217SJeff Kirsher 338adfc5217SJeff Kirsher return mp->get(mp, 1); 339adfc5217SJeff Kirsher } 340adfc5217SJeff Kirsher 341adfc5217SJeff Kirsher static bool bnx2x_get_cam_offset_vlan(struct bnx2x_vlan_mac_obj *o, int *offset) 342adfc5217SJeff Kirsher { 343adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *vp = o->vlans_pool; 344adfc5217SJeff Kirsher 345adfc5217SJeff Kirsher WARN_ON(!vp); 346adfc5217SJeff Kirsher 347adfc5217SJeff Kirsher return vp->get_entry(vp, offset); 348adfc5217SJeff Kirsher } 349adfc5217SJeff Kirsher 350adfc5217SJeff Kirsher static bool bnx2x_get_credit_vlan(struct bnx2x_vlan_mac_obj *o) 351adfc5217SJeff Kirsher { 352adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *vp = o->vlans_pool; 353adfc5217SJeff Kirsher 354adfc5217SJeff Kirsher WARN_ON(!vp); 355adfc5217SJeff Kirsher 356adfc5217SJeff Kirsher return vp->get(vp, 1); 357adfc5217SJeff Kirsher } 358adfc5217SJeff Kirsher 359adfc5217SJeff Kirsher static bool bnx2x_get_credit_vlan_mac(struct bnx2x_vlan_mac_obj *o) 360adfc5217SJeff Kirsher { 361adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *mp = o->macs_pool; 362adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *vp = o->vlans_pool; 363adfc5217SJeff Kirsher 364adfc5217SJeff Kirsher if (!mp->get(mp, 1)) 365adfc5217SJeff Kirsher return false; 366adfc5217SJeff Kirsher 367adfc5217SJeff Kirsher if (!vp->get(vp, 1)) { 368adfc5217SJeff Kirsher mp->put(mp, 1); 369adfc5217SJeff Kirsher return false; 370adfc5217SJeff Kirsher } 371adfc5217SJeff Kirsher 372adfc5217SJeff Kirsher return true; 373adfc5217SJeff Kirsher } 374adfc5217SJeff Kirsher 375adfc5217SJeff Kirsher static bool bnx2x_put_cam_offset_mac(struct bnx2x_vlan_mac_obj *o, int offset) 376adfc5217SJeff Kirsher { 377adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *mp = o->macs_pool; 378adfc5217SJeff Kirsher 379adfc5217SJeff Kirsher return mp->put_entry(mp, offset); 380adfc5217SJeff Kirsher } 381adfc5217SJeff Kirsher 382adfc5217SJeff Kirsher static bool bnx2x_put_credit_mac(struct bnx2x_vlan_mac_obj *o) 383adfc5217SJeff Kirsher { 384adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *mp = o->macs_pool; 385adfc5217SJeff Kirsher 386adfc5217SJeff Kirsher return mp->put(mp, 1); 387adfc5217SJeff Kirsher } 388adfc5217SJeff Kirsher 389adfc5217SJeff Kirsher static bool bnx2x_put_cam_offset_vlan(struct bnx2x_vlan_mac_obj *o, int offset) 390adfc5217SJeff Kirsher { 391adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *vp = o->vlans_pool; 392adfc5217SJeff Kirsher 393adfc5217SJeff Kirsher return vp->put_entry(vp, offset); 394adfc5217SJeff Kirsher } 395adfc5217SJeff Kirsher 396adfc5217SJeff Kirsher static bool bnx2x_put_credit_vlan(struct bnx2x_vlan_mac_obj *o) 397adfc5217SJeff Kirsher { 398adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *vp = o->vlans_pool; 399adfc5217SJeff Kirsher 400adfc5217SJeff Kirsher return vp->put(vp, 1); 401adfc5217SJeff Kirsher } 402adfc5217SJeff Kirsher 403adfc5217SJeff Kirsher static bool bnx2x_put_credit_vlan_mac(struct bnx2x_vlan_mac_obj *o) 404adfc5217SJeff Kirsher { 405adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *mp = o->macs_pool; 406adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *vp = o->vlans_pool; 407adfc5217SJeff Kirsher 408adfc5217SJeff Kirsher if (!mp->put(mp, 1)) 409adfc5217SJeff Kirsher return false; 410adfc5217SJeff Kirsher 411adfc5217SJeff Kirsher if (!vp->put(vp, 1)) { 412adfc5217SJeff Kirsher mp->get(mp, 1); 413adfc5217SJeff Kirsher return false; 414adfc5217SJeff Kirsher } 415adfc5217SJeff Kirsher 416adfc5217SJeff Kirsher return true; 417adfc5217SJeff Kirsher } 418adfc5217SJeff Kirsher 4198b09be5fSYuval Mintz /** 4208b09be5fSYuval Mintz * __bnx2x_vlan_mac_h_write_trylock - try getting the vlan mac writer lock 4218b09be5fSYuval Mintz * 4228b09be5fSYuval Mintz * @bp: device handle 4238b09be5fSYuval Mintz * @o: vlan_mac object 4248b09be5fSYuval Mintz * 4258b09be5fSYuval Mintz * @details: Non-blocking implementation; should be called under execution 4268b09be5fSYuval Mintz * queue lock. 4278b09be5fSYuval Mintz */ 4288b09be5fSYuval Mintz static int __bnx2x_vlan_mac_h_write_trylock(struct bnx2x *bp, 4298b09be5fSYuval Mintz struct bnx2x_vlan_mac_obj *o) 4308b09be5fSYuval Mintz { 4318b09be5fSYuval Mintz if (o->head_reader) { 4328b09be5fSYuval Mintz DP(BNX2X_MSG_SP, "vlan_mac_lock writer - There are readers; Busy\n"); 4338b09be5fSYuval Mintz return -EBUSY; 4348b09be5fSYuval Mintz } 4358b09be5fSYuval Mintz 4368b09be5fSYuval Mintz DP(BNX2X_MSG_SP, "vlan_mac_lock writer - Taken\n"); 4378b09be5fSYuval Mintz return 0; 4388b09be5fSYuval Mintz } 4398b09be5fSYuval Mintz 4408b09be5fSYuval Mintz /** 4418b09be5fSYuval Mintz * __bnx2x_vlan_mac_h_exec_pending - execute step instead of a previous step 4428b09be5fSYuval Mintz * 4438b09be5fSYuval Mintz * @bp: device handle 4448b09be5fSYuval Mintz * @o: vlan_mac object 4458b09be5fSYuval Mintz * 4468b09be5fSYuval Mintz * @details Should be called under execution queue lock; notice it might release 4478b09be5fSYuval Mintz * and reclaim it during its run. 4488b09be5fSYuval Mintz */ 4498b09be5fSYuval Mintz static void __bnx2x_vlan_mac_h_exec_pending(struct bnx2x *bp, 4508b09be5fSYuval Mintz struct bnx2x_vlan_mac_obj *o) 4518b09be5fSYuval Mintz { 4528b09be5fSYuval Mintz int rc; 4538b09be5fSYuval Mintz unsigned long ramrod_flags = o->saved_ramrod_flags; 4548b09be5fSYuval Mintz 4558b09be5fSYuval Mintz DP(BNX2X_MSG_SP, "vlan_mac_lock execute pending command with ramrod flags %lu\n", 4568b09be5fSYuval Mintz ramrod_flags); 4578b09be5fSYuval Mintz o->head_exe_request = false; 4588b09be5fSYuval Mintz o->saved_ramrod_flags = 0; 4598b09be5fSYuval Mintz rc = bnx2x_exe_queue_step(bp, &o->exe_queue, &ramrod_flags); 4608b09be5fSYuval Mintz if (rc != 0) { 4618b09be5fSYuval Mintz BNX2X_ERR("execution of pending commands failed with rc %d\n", 4628b09be5fSYuval Mintz rc); 4638b09be5fSYuval Mintz #ifdef BNX2X_STOP_ON_ERROR 4648b09be5fSYuval Mintz bnx2x_panic(); 4658b09be5fSYuval Mintz #endif 4668b09be5fSYuval Mintz } 4678b09be5fSYuval Mintz } 4688b09be5fSYuval Mintz 4698b09be5fSYuval Mintz /** 4708b09be5fSYuval Mintz * __bnx2x_vlan_mac_h_pend - Pend an execution step which couldn't run 4718b09be5fSYuval Mintz * 4728b09be5fSYuval Mintz * @bp: device handle 4738b09be5fSYuval Mintz * @o: vlan_mac object 4748b09be5fSYuval Mintz * @ramrod_flags: ramrod flags of missed execution 4758b09be5fSYuval Mintz * 4768b09be5fSYuval Mintz * @details Should be called under execution queue lock. 4778b09be5fSYuval Mintz */ 4788b09be5fSYuval Mintz static void __bnx2x_vlan_mac_h_pend(struct bnx2x *bp, 4798b09be5fSYuval Mintz struct bnx2x_vlan_mac_obj *o, 4808b09be5fSYuval Mintz unsigned long ramrod_flags) 4818b09be5fSYuval Mintz { 4828b09be5fSYuval Mintz o->head_exe_request = true; 4838b09be5fSYuval Mintz o->saved_ramrod_flags = ramrod_flags; 4848b09be5fSYuval Mintz DP(BNX2X_MSG_SP, "Placing pending execution with ramrod flags %lu\n", 4858b09be5fSYuval Mintz ramrod_flags); 4868b09be5fSYuval Mintz } 4878b09be5fSYuval Mintz 4888b09be5fSYuval Mintz /** 4898b09be5fSYuval Mintz * __bnx2x_vlan_mac_h_write_unlock - unlock the vlan mac head list writer lock 4908b09be5fSYuval Mintz * 4918b09be5fSYuval Mintz * @bp: device handle 4928b09be5fSYuval Mintz * @o: vlan_mac object 4938b09be5fSYuval Mintz * 4948b09be5fSYuval Mintz * @details Should be called under execution queue lock. Notice if a pending 4958b09be5fSYuval Mintz * execution exists, it would perform it - possibly releasing and 4968b09be5fSYuval Mintz * reclaiming the execution queue lock. 4978b09be5fSYuval Mintz */ 4988b09be5fSYuval Mintz static void __bnx2x_vlan_mac_h_write_unlock(struct bnx2x *bp, 4998b09be5fSYuval Mintz struct bnx2x_vlan_mac_obj *o) 5008b09be5fSYuval Mintz { 5018b09be5fSYuval Mintz /* It's possible a new pending execution was added since this writer 5028b09be5fSYuval Mintz * executed. If so, execute again. [Ad infinitum] 5038b09be5fSYuval Mintz */ 5048b09be5fSYuval Mintz while (o->head_exe_request) { 5058b09be5fSYuval Mintz DP(BNX2X_MSG_SP, "vlan_mac_lock - writer release encountered a pending request\n"); 5068b09be5fSYuval Mintz __bnx2x_vlan_mac_h_exec_pending(bp, o); 5078b09be5fSYuval Mintz } 5088b09be5fSYuval Mintz } 5098b09be5fSYuval Mintz 5108b09be5fSYuval Mintz /** 5118b09be5fSYuval Mintz * bnx2x_vlan_mac_h_write_unlock - unlock the vlan mac head list writer lock 5128b09be5fSYuval Mintz * 5138b09be5fSYuval Mintz * @bp: device handle 5148b09be5fSYuval Mintz * @o: vlan_mac object 5158b09be5fSYuval Mintz * 5168b09be5fSYuval Mintz * @details Notice if a pending execution exists, it would perform it - 5178b09be5fSYuval Mintz * possibly releasing and reclaiming the execution queue lock. 5188b09be5fSYuval Mintz */ 5198b09be5fSYuval Mintz void bnx2x_vlan_mac_h_write_unlock(struct bnx2x *bp, 5208b09be5fSYuval Mintz struct bnx2x_vlan_mac_obj *o) 5218b09be5fSYuval Mintz { 5228b09be5fSYuval Mintz spin_lock_bh(&o->exe_queue.lock); 5238b09be5fSYuval Mintz __bnx2x_vlan_mac_h_write_unlock(bp, o); 5248b09be5fSYuval Mintz spin_unlock_bh(&o->exe_queue.lock); 5258b09be5fSYuval Mintz } 5268b09be5fSYuval Mintz 5278b09be5fSYuval Mintz /** 5288b09be5fSYuval Mintz * __bnx2x_vlan_mac_h_read_lock - lock the vlan mac head list reader lock 5298b09be5fSYuval Mintz * 5308b09be5fSYuval Mintz * @bp: device handle 5318b09be5fSYuval Mintz * @o: vlan_mac object 5328b09be5fSYuval Mintz * 5338b09be5fSYuval Mintz * @details Should be called under the execution queue lock. May sleep. May 5348b09be5fSYuval Mintz * release and reclaim execution queue lock during its run. 5358b09be5fSYuval Mintz */ 5368b09be5fSYuval Mintz static int __bnx2x_vlan_mac_h_read_lock(struct bnx2x *bp, 5378b09be5fSYuval Mintz struct bnx2x_vlan_mac_obj *o) 5388b09be5fSYuval Mintz { 5398b09be5fSYuval Mintz /* If we got here, we're holding lock --> no WRITER exists */ 5408b09be5fSYuval Mintz o->head_reader++; 5418b09be5fSYuval Mintz DP(BNX2X_MSG_SP, "vlan_mac_lock - locked reader - number %d\n", 5428b09be5fSYuval Mintz o->head_reader); 5438b09be5fSYuval Mintz 5448b09be5fSYuval Mintz return 0; 5458b09be5fSYuval Mintz } 5468b09be5fSYuval Mintz 5478b09be5fSYuval Mintz /** 5488b09be5fSYuval Mintz * bnx2x_vlan_mac_h_read_lock - lock the vlan mac head list reader lock 5498b09be5fSYuval Mintz * 5508b09be5fSYuval Mintz * @bp: device handle 5518b09be5fSYuval Mintz * @o: vlan_mac object 5528b09be5fSYuval Mintz * 5538b09be5fSYuval Mintz * @details May sleep. Claims and releases execution queue lock during its run. 5548b09be5fSYuval Mintz */ 5558b09be5fSYuval Mintz int bnx2x_vlan_mac_h_read_lock(struct bnx2x *bp, 5568b09be5fSYuval Mintz struct bnx2x_vlan_mac_obj *o) 5578b09be5fSYuval Mintz { 5588b09be5fSYuval Mintz int rc; 5598b09be5fSYuval Mintz 5608b09be5fSYuval Mintz spin_lock_bh(&o->exe_queue.lock); 5618b09be5fSYuval Mintz rc = __bnx2x_vlan_mac_h_read_lock(bp, o); 5628b09be5fSYuval Mintz spin_unlock_bh(&o->exe_queue.lock); 5638b09be5fSYuval Mintz 5648b09be5fSYuval Mintz return rc; 5658b09be5fSYuval Mintz } 5668b09be5fSYuval Mintz 5678b09be5fSYuval Mintz /** 5688b09be5fSYuval Mintz * __bnx2x_vlan_mac_h_read_unlock - unlock the vlan mac head list reader lock 5698b09be5fSYuval Mintz * 5708b09be5fSYuval Mintz * @bp: device handle 5718b09be5fSYuval Mintz * @o: vlan_mac object 5728b09be5fSYuval Mintz * 5738b09be5fSYuval Mintz * @details Should be called under execution queue lock. Notice if a pending 5748b09be5fSYuval Mintz * execution exists, it would be performed if this was the last 5758b09be5fSYuval Mintz * reader. possibly releasing and reclaiming the execution queue lock. 5768b09be5fSYuval Mintz */ 5778b09be5fSYuval Mintz static void __bnx2x_vlan_mac_h_read_unlock(struct bnx2x *bp, 5788b09be5fSYuval Mintz struct bnx2x_vlan_mac_obj *o) 5798b09be5fSYuval Mintz { 5808b09be5fSYuval Mintz if (!o->head_reader) { 5818b09be5fSYuval Mintz BNX2X_ERR("Need to release vlan mac reader lock, but lock isn't taken\n"); 5828b09be5fSYuval Mintz #ifdef BNX2X_STOP_ON_ERROR 5838b09be5fSYuval Mintz bnx2x_panic(); 5848b09be5fSYuval Mintz #endif 5858b09be5fSYuval Mintz } else { 5868b09be5fSYuval Mintz o->head_reader--; 5878b09be5fSYuval Mintz DP(BNX2X_MSG_SP, "vlan_mac_lock - decreased readers to %d\n", 5888b09be5fSYuval Mintz o->head_reader); 5898b09be5fSYuval Mintz } 5908b09be5fSYuval Mintz 5918b09be5fSYuval Mintz /* It's possible a new pending execution was added, and that this reader 5928b09be5fSYuval Mintz * was last - if so we need to execute the command. 5938b09be5fSYuval Mintz */ 5948b09be5fSYuval Mintz if (!o->head_reader && o->head_exe_request) { 5958b09be5fSYuval Mintz DP(BNX2X_MSG_SP, "vlan_mac_lock - reader release encountered a pending request\n"); 5968b09be5fSYuval Mintz 5978b09be5fSYuval Mintz /* Writer release will do the trick */ 5988b09be5fSYuval Mintz __bnx2x_vlan_mac_h_write_unlock(bp, o); 5998b09be5fSYuval Mintz } 6008b09be5fSYuval Mintz } 6018b09be5fSYuval Mintz 6028b09be5fSYuval Mintz /** 6038b09be5fSYuval Mintz * bnx2x_vlan_mac_h_read_unlock - unlock the vlan mac head list reader lock 6048b09be5fSYuval Mintz * 6058b09be5fSYuval Mintz * @bp: device handle 6068b09be5fSYuval Mintz * @o: vlan_mac object 6078b09be5fSYuval Mintz * 6088b09be5fSYuval Mintz * @details Notice if a pending execution exists, it would be performed if this 6098b09be5fSYuval Mintz * was the last reader. Claims and releases the execution queue lock 6108b09be5fSYuval Mintz * during its run. 6118b09be5fSYuval Mintz */ 6128b09be5fSYuval Mintz void bnx2x_vlan_mac_h_read_unlock(struct bnx2x *bp, 6138b09be5fSYuval Mintz struct bnx2x_vlan_mac_obj *o) 6148b09be5fSYuval Mintz { 6158b09be5fSYuval Mintz spin_lock_bh(&o->exe_queue.lock); 6168b09be5fSYuval Mintz __bnx2x_vlan_mac_h_read_unlock(bp, o); 6178b09be5fSYuval Mintz spin_unlock_bh(&o->exe_queue.lock); 6188b09be5fSYuval Mintz } 6198b09be5fSYuval Mintz 620ed5162a0SAriel Elior static int bnx2x_get_n_elements(struct bnx2x *bp, struct bnx2x_vlan_mac_obj *o, 6213ec9f9caSAriel Elior int n, u8 *base, u8 stride, u8 size) 622ed5162a0SAriel Elior { 623ed5162a0SAriel Elior struct bnx2x_vlan_mac_registry_elem *pos; 6243ec9f9caSAriel Elior u8 *next = base; 625ed5162a0SAriel Elior int counter = 0; 6268b09be5fSYuval Mintz int read_lock; 6278b09be5fSYuval Mintz 6288b09be5fSYuval Mintz DP(BNX2X_MSG_SP, "get_n_elements - taking vlan_mac_lock (reader)\n"); 6298b09be5fSYuval Mintz read_lock = bnx2x_vlan_mac_h_read_lock(bp, o); 6308b09be5fSYuval Mintz if (read_lock != 0) 6318b09be5fSYuval Mintz BNX2X_ERR("get_n_elements failed to get vlan mac reader lock; Access without lock\n"); 632ed5162a0SAriel Elior 633ed5162a0SAriel Elior /* traverse list */ 634ed5162a0SAriel Elior list_for_each_entry(pos, &o->head, link) { 635ed5162a0SAriel Elior if (counter < n) { 6363ec9f9caSAriel Elior memcpy(next, &pos->u, size); 637ed5162a0SAriel Elior counter++; 6383ec9f9caSAriel Elior DP(BNX2X_MSG_SP, "copied element number %d to address %p element was:\n", 6393ec9f9caSAriel Elior counter, next); 6403ec9f9caSAriel Elior next += stride + size; 641ed5162a0SAriel Elior } 642ed5162a0SAriel Elior } 6438b09be5fSYuval Mintz 6448b09be5fSYuval Mintz if (read_lock == 0) { 6458b09be5fSYuval Mintz DP(BNX2X_MSG_SP, "get_n_elements - releasing vlan_mac_lock (reader)\n"); 6468b09be5fSYuval Mintz bnx2x_vlan_mac_h_read_unlock(bp, o); 6478b09be5fSYuval Mintz } 6488b09be5fSYuval Mintz 649ed5162a0SAriel Elior return counter * ETH_ALEN; 650ed5162a0SAriel Elior } 651ed5162a0SAriel Elior 652adfc5217SJeff Kirsher /* check_add() callbacks */ 65351c1a580SMerav Sicron static int bnx2x_check_mac_add(struct bnx2x *bp, 65451c1a580SMerav Sicron struct bnx2x_vlan_mac_obj *o, 655adfc5217SJeff Kirsher union bnx2x_classification_ramrod_data *data) 656adfc5217SJeff Kirsher { 657adfc5217SJeff Kirsher struct bnx2x_vlan_mac_registry_elem *pos; 658adfc5217SJeff Kirsher 65951c1a580SMerav Sicron DP(BNX2X_MSG_SP, "Checking MAC %pM for ADD command\n", data->mac.mac); 66051c1a580SMerav Sicron 661adfc5217SJeff Kirsher if (!is_valid_ether_addr(data->mac.mac)) 662adfc5217SJeff Kirsher return -EINVAL; 663adfc5217SJeff Kirsher 664adfc5217SJeff Kirsher /* Check if a requested MAC already exists */ 665adfc5217SJeff Kirsher list_for_each_entry(pos, &o->head, link) 6668fd90de8Sdingtianhong if (ether_addr_equal(data->mac.mac, pos->u.mac.mac) && 66791226790SDmitry Kravkov (data->mac.is_inner_mac == pos->u.mac.is_inner_mac)) 668adfc5217SJeff Kirsher return -EEXIST; 669adfc5217SJeff Kirsher 670adfc5217SJeff Kirsher return 0; 671adfc5217SJeff Kirsher } 672adfc5217SJeff Kirsher 67351c1a580SMerav Sicron static int bnx2x_check_vlan_add(struct bnx2x *bp, 67451c1a580SMerav Sicron struct bnx2x_vlan_mac_obj *o, 675adfc5217SJeff Kirsher union bnx2x_classification_ramrod_data *data) 676adfc5217SJeff Kirsher { 677adfc5217SJeff Kirsher struct bnx2x_vlan_mac_registry_elem *pos; 678adfc5217SJeff Kirsher 67951c1a580SMerav Sicron DP(BNX2X_MSG_SP, "Checking VLAN %d for ADD command\n", data->vlan.vlan); 68051c1a580SMerav Sicron 681adfc5217SJeff Kirsher list_for_each_entry(pos, &o->head, link) 682adfc5217SJeff Kirsher if (data->vlan.vlan == pos->u.vlan.vlan) 683adfc5217SJeff Kirsher return -EEXIST; 684adfc5217SJeff Kirsher 685adfc5217SJeff Kirsher return 0; 686adfc5217SJeff Kirsher } 687adfc5217SJeff Kirsher 68851c1a580SMerav Sicron static int bnx2x_check_vlan_mac_add(struct bnx2x *bp, 68951c1a580SMerav Sicron struct bnx2x_vlan_mac_obj *o, 690adfc5217SJeff Kirsher union bnx2x_classification_ramrod_data *data) 691adfc5217SJeff Kirsher { 692adfc5217SJeff Kirsher struct bnx2x_vlan_mac_registry_elem *pos; 693adfc5217SJeff Kirsher 69451c1a580SMerav Sicron DP(BNX2X_MSG_SP, "Checking VLAN_MAC (%pM, %d) for ADD command\n", 69551c1a580SMerav Sicron data->vlan_mac.mac, data->vlan_mac.vlan); 69651c1a580SMerav Sicron 697adfc5217SJeff Kirsher list_for_each_entry(pos, &o->head, link) 698adfc5217SJeff Kirsher if ((data->vlan_mac.vlan == pos->u.vlan_mac.vlan) && 6998fd90de8Sdingtianhong ether_addr_equal_unaligned(data->vlan_mac.mac, pos->u.vlan_mac.mac) && 70091226790SDmitry Kravkov (data->vlan_mac.is_inner_mac == 70191226790SDmitry Kravkov pos->u.vlan_mac.is_inner_mac)) 702adfc5217SJeff Kirsher return -EEXIST; 703adfc5217SJeff Kirsher 704adfc5217SJeff Kirsher return 0; 705adfc5217SJeff Kirsher } 706adfc5217SJeff Kirsher 707adfc5217SJeff Kirsher /* check_del() callbacks */ 708adfc5217SJeff Kirsher static struct bnx2x_vlan_mac_registry_elem * 70951c1a580SMerav Sicron bnx2x_check_mac_del(struct bnx2x *bp, 71051c1a580SMerav Sicron struct bnx2x_vlan_mac_obj *o, 711adfc5217SJeff Kirsher union bnx2x_classification_ramrod_data *data) 712adfc5217SJeff Kirsher { 713adfc5217SJeff Kirsher struct bnx2x_vlan_mac_registry_elem *pos; 714adfc5217SJeff Kirsher 71551c1a580SMerav Sicron DP(BNX2X_MSG_SP, "Checking MAC %pM for DEL command\n", data->mac.mac); 71651c1a580SMerav Sicron 717adfc5217SJeff Kirsher list_for_each_entry(pos, &o->head, link) 7188fd90de8Sdingtianhong if (ether_addr_equal(data->mac.mac, pos->u.mac.mac) && 71991226790SDmitry Kravkov (data->mac.is_inner_mac == pos->u.mac.is_inner_mac)) 720adfc5217SJeff Kirsher return pos; 721adfc5217SJeff Kirsher 722adfc5217SJeff Kirsher return NULL; 723adfc5217SJeff Kirsher } 724adfc5217SJeff Kirsher 725adfc5217SJeff Kirsher static struct bnx2x_vlan_mac_registry_elem * 72651c1a580SMerav Sicron bnx2x_check_vlan_del(struct bnx2x *bp, 72751c1a580SMerav Sicron struct bnx2x_vlan_mac_obj *o, 728adfc5217SJeff Kirsher union bnx2x_classification_ramrod_data *data) 729adfc5217SJeff Kirsher { 730adfc5217SJeff Kirsher struct bnx2x_vlan_mac_registry_elem *pos; 731adfc5217SJeff Kirsher 73251c1a580SMerav Sicron DP(BNX2X_MSG_SP, "Checking VLAN %d for DEL command\n", data->vlan.vlan); 73351c1a580SMerav Sicron 734adfc5217SJeff Kirsher list_for_each_entry(pos, &o->head, link) 735adfc5217SJeff Kirsher if (data->vlan.vlan == pos->u.vlan.vlan) 736adfc5217SJeff Kirsher return pos; 737adfc5217SJeff Kirsher 738adfc5217SJeff Kirsher return NULL; 739adfc5217SJeff Kirsher } 740adfc5217SJeff Kirsher 741adfc5217SJeff Kirsher static struct bnx2x_vlan_mac_registry_elem * 74251c1a580SMerav Sicron bnx2x_check_vlan_mac_del(struct bnx2x *bp, 74351c1a580SMerav Sicron struct bnx2x_vlan_mac_obj *o, 744adfc5217SJeff Kirsher union bnx2x_classification_ramrod_data *data) 745adfc5217SJeff Kirsher { 746adfc5217SJeff Kirsher struct bnx2x_vlan_mac_registry_elem *pos; 747adfc5217SJeff Kirsher 74851c1a580SMerav Sicron DP(BNX2X_MSG_SP, "Checking VLAN_MAC (%pM, %d) for DEL command\n", 74951c1a580SMerav Sicron data->vlan_mac.mac, data->vlan_mac.vlan); 75051c1a580SMerav Sicron 751adfc5217SJeff Kirsher list_for_each_entry(pos, &o->head, link) 752adfc5217SJeff Kirsher if ((data->vlan_mac.vlan == pos->u.vlan_mac.vlan) && 7538fd90de8Sdingtianhong ether_addr_equal_unaligned(data->vlan_mac.mac, pos->u.vlan_mac.mac) && 75491226790SDmitry Kravkov (data->vlan_mac.is_inner_mac == 75591226790SDmitry Kravkov pos->u.vlan_mac.is_inner_mac)) 756adfc5217SJeff Kirsher return pos; 757adfc5217SJeff Kirsher 758adfc5217SJeff Kirsher return NULL; 759adfc5217SJeff Kirsher } 760adfc5217SJeff Kirsher 761adfc5217SJeff Kirsher /* check_move() callback */ 76251c1a580SMerav Sicron static bool bnx2x_check_move(struct bnx2x *bp, 76351c1a580SMerav Sicron struct bnx2x_vlan_mac_obj *src_o, 764adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *dst_o, 765adfc5217SJeff Kirsher union bnx2x_classification_ramrod_data *data) 766adfc5217SJeff Kirsher { 767adfc5217SJeff Kirsher struct bnx2x_vlan_mac_registry_elem *pos; 768adfc5217SJeff Kirsher int rc; 769adfc5217SJeff Kirsher 770adfc5217SJeff Kirsher /* Check if we can delete the requested configuration from the first 771adfc5217SJeff Kirsher * object. 772adfc5217SJeff Kirsher */ 77351c1a580SMerav Sicron pos = src_o->check_del(bp, src_o, data); 774adfc5217SJeff Kirsher 775adfc5217SJeff Kirsher /* check if configuration can be added */ 77651c1a580SMerav Sicron rc = dst_o->check_add(bp, dst_o, data); 777adfc5217SJeff Kirsher 778adfc5217SJeff Kirsher /* If this classification can not be added (is already set) 779adfc5217SJeff Kirsher * or can't be deleted - return an error. 780adfc5217SJeff Kirsher */ 781adfc5217SJeff Kirsher if (rc || !pos) 782adfc5217SJeff Kirsher return false; 783adfc5217SJeff Kirsher 784adfc5217SJeff Kirsher return true; 785adfc5217SJeff Kirsher } 786adfc5217SJeff Kirsher 787adfc5217SJeff Kirsher static bool bnx2x_check_move_always_err( 78851c1a580SMerav Sicron struct bnx2x *bp, 789adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *src_o, 790adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *dst_o, 791adfc5217SJeff Kirsher union bnx2x_classification_ramrod_data *data) 792adfc5217SJeff Kirsher { 793adfc5217SJeff Kirsher return false; 794adfc5217SJeff Kirsher } 795adfc5217SJeff Kirsher 796adfc5217SJeff Kirsher static inline u8 bnx2x_vlan_mac_get_rx_tx_flag(struct bnx2x_vlan_mac_obj *o) 797adfc5217SJeff Kirsher { 798adfc5217SJeff Kirsher struct bnx2x_raw_obj *raw = &o->raw; 799adfc5217SJeff Kirsher u8 rx_tx_flag = 0; 800adfc5217SJeff Kirsher 801adfc5217SJeff Kirsher if ((raw->obj_type == BNX2X_OBJ_TYPE_TX) || 802adfc5217SJeff Kirsher (raw->obj_type == BNX2X_OBJ_TYPE_RX_TX)) 803adfc5217SJeff Kirsher rx_tx_flag |= ETH_CLASSIFY_CMD_HEADER_TX_CMD; 804adfc5217SJeff Kirsher 805adfc5217SJeff Kirsher if ((raw->obj_type == BNX2X_OBJ_TYPE_RX) || 806adfc5217SJeff Kirsher (raw->obj_type == BNX2X_OBJ_TYPE_RX_TX)) 807adfc5217SJeff Kirsher rx_tx_flag |= ETH_CLASSIFY_CMD_HEADER_RX_CMD; 808adfc5217SJeff Kirsher 809adfc5217SJeff Kirsher return rx_tx_flag; 810adfc5217SJeff Kirsher } 811adfc5217SJeff Kirsher 812a3348722SBarak Witkowski void bnx2x_set_mac_in_nig(struct bnx2x *bp, 813adfc5217SJeff Kirsher bool add, unsigned char *dev_addr, int index) 814adfc5217SJeff Kirsher { 815adfc5217SJeff Kirsher u32 wb_data[2]; 816adfc5217SJeff Kirsher u32 reg_offset = BP_PORT(bp) ? NIG_REG_LLH1_FUNC_MEM : 817adfc5217SJeff Kirsher NIG_REG_LLH0_FUNC_MEM; 818adfc5217SJeff Kirsher 819a3348722SBarak Witkowski if (!IS_MF_SI(bp) && !IS_MF_AFEX(bp)) 820a3348722SBarak Witkowski return; 821a3348722SBarak Witkowski 822a3348722SBarak Witkowski if (index > BNX2X_LLH_CAM_MAX_PF_LINE) 823adfc5217SJeff Kirsher return; 824adfc5217SJeff Kirsher 825adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "Going to %s LLH configuration at entry %d\n", 826adfc5217SJeff Kirsher (add ? "ADD" : "DELETE"), index); 827adfc5217SJeff Kirsher 828adfc5217SJeff Kirsher if (add) { 829adfc5217SJeff Kirsher /* LLH_FUNC_MEM is a u64 WB register */ 830adfc5217SJeff Kirsher reg_offset += 8*index; 831adfc5217SJeff Kirsher 832adfc5217SJeff Kirsher wb_data[0] = ((dev_addr[2] << 24) | (dev_addr[3] << 16) | 833adfc5217SJeff Kirsher (dev_addr[4] << 8) | dev_addr[5]); 834adfc5217SJeff Kirsher wb_data[1] = ((dev_addr[0] << 8) | dev_addr[1]); 835adfc5217SJeff Kirsher 836adfc5217SJeff Kirsher REG_WR_DMAE(bp, reg_offset, wb_data, 2); 837adfc5217SJeff Kirsher } 838adfc5217SJeff Kirsher 839adfc5217SJeff Kirsher REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_FUNC_MEM_ENABLE : 840adfc5217SJeff Kirsher NIG_REG_LLH0_FUNC_MEM_ENABLE) + 4*index, add); 841adfc5217SJeff Kirsher } 842adfc5217SJeff Kirsher 843adfc5217SJeff Kirsher /** 844adfc5217SJeff Kirsher * bnx2x_vlan_mac_set_cmd_hdr_e2 - set a header in a single classify ramrod 845adfc5217SJeff Kirsher * 846adfc5217SJeff Kirsher * @bp: device handle 847adfc5217SJeff Kirsher * @o: queue for which we want to configure this rule 848adfc5217SJeff Kirsher * @add: if true the command is an ADD command, DEL otherwise 849adfc5217SJeff Kirsher * @opcode: CLASSIFY_RULE_OPCODE_XXX 850adfc5217SJeff Kirsher * @hdr: pointer to a header to setup 851adfc5217SJeff Kirsher * 852adfc5217SJeff Kirsher */ 853adfc5217SJeff Kirsher static inline void bnx2x_vlan_mac_set_cmd_hdr_e2(struct bnx2x *bp, 854adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *o, bool add, int opcode, 855adfc5217SJeff Kirsher struct eth_classify_cmd_header *hdr) 856adfc5217SJeff Kirsher { 857adfc5217SJeff Kirsher struct bnx2x_raw_obj *raw = &o->raw; 858adfc5217SJeff Kirsher 859adfc5217SJeff Kirsher hdr->client_id = raw->cl_id; 860adfc5217SJeff Kirsher hdr->func_id = raw->func_id; 861adfc5217SJeff Kirsher 862adfc5217SJeff Kirsher /* Rx or/and Tx (internal switching) configuration ? */ 863adfc5217SJeff Kirsher hdr->cmd_general_data |= 864adfc5217SJeff Kirsher bnx2x_vlan_mac_get_rx_tx_flag(o); 865adfc5217SJeff Kirsher 866adfc5217SJeff Kirsher if (add) 867adfc5217SJeff Kirsher hdr->cmd_general_data |= ETH_CLASSIFY_CMD_HEADER_IS_ADD; 868adfc5217SJeff Kirsher 869adfc5217SJeff Kirsher hdr->cmd_general_data |= 870adfc5217SJeff Kirsher (opcode << ETH_CLASSIFY_CMD_HEADER_OPCODE_SHIFT); 871adfc5217SJeff Kirsher } 872adfc5217SJeff Kirsher 873adfc5217SJeff Kirsher /** 874adfc5217SJeff Kirsher * bnx2x_vlan_mac_set_rdata_hdr_e2 - set the classify ramrod data header 875adfc5217SJeff Kirsher * 876adfc5217SJeff Kirsher * @cid: connection id 877adfc5217SJeff Kirsher * @type: BNX2X_FILTER_XXX_PENDING 87816a5fd92SYuval Mintz * @hdr: pointer to header to setup 879adfc5217SJeff Kirsher * @rule_cnt: 880adfc5217SJeff Kirsher * 881adfc5217SJeff Kirsher * currently we always configure one rule and echo field to contain a CID and an 882adfc5217SJeff Kirsher * opcode type. 883adfc5217SJeff Kirsher */ 884adfc5217SJeff Kirsher static inline void bnx2x_vlan_mac_set_rdata_hdr_e2(u32 cid, int type, 885adfc5217SJeff Kirsher struct eth_classify_header *hdr, int rule_cnt) 886adfc5217SJeff Kirsher { 88786564c3fSYuval Mintz hdr->echo = cpu_to_le32((cid & BNX2X_SWCID_MASK) | 88886564c3fSYuval Mintz (type << BNX2X_SWCID_SHIFT)); 889adfc5217SJeff Kirsher hdr->rule_cnt = (u8)rule_cnt; 890adfc5217SJeff Kirsher } 891adfc5217SJeff Kirsher 892adfc5217SJeff Kirsher /* hw_config() callbacks */ 893adfc5217SJeff Kirsher static void bnx2x_set_one_mac_e2(struct bnx2x *bp, 894adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *o, 895adfc5217SJeff Kirsher struct bnx2x_exeq_elem *elem, int rule_idx, 896adfc5217SJeff Kirsher int cam_offset) 897adfc5217SJeff Kirsher { 898adfc5217SJeff Kirsher struct bnx2x_raw_obj *raw = &o->raw; 899adfc5217SJeff Kirsher struct eth_classify_rules_ramrod_data *data = 900adfc5217SJeff Kirsher (struct eth_classify_rules_ramrod_data *)(raw->rdata); 901adfc5217SJeff Kirsher int rule_cnt = rule_idx + 1, cmd = elem->cmd_data.vlan_mac.cmd; 902adfc5217SJeff Kirsher union eth_classify_rule_cmd *rule_entry = &data->rules[rule_idx]; 903adfc5217SJeff Kirsher bool add = (cmd == BNX2X_VLAN_MAC_ADD) ? true : false; 904adfc5217SJeff Kirsher unsigned long *vlan_mac_flags = &elem->cmd_data.vlan_mac.vlan_mac_flags; 905adfc5217SJeff Kirsher u8 *mac = elem->cmd_data.vlan_mac.u.mac.mac; 906adfc5217SJeff Kirsher 90716a5fd92SYuval Mintz /* Set LLH CAM entry: currently only iSCSI and ETH macs are 908adfc5217SJeff Kirsher * relevant. In addition, current implementation is tuned for a 909adfc5217SJeff Kirsher * single ETH MAC. 910adfc5217SJeff Kirsher * 911adfc5217SJeff Kirsher * When multiple unicast ETH MACs PF configuration in switch 912adfc5217SJeff Kirsher * independent mode is required (NetQ, multiple netdev MACs, 913adfc5217SJeff Kirsher * etc.), consider better utilisation of 8 per function MAC 914adfc5217SJeff Kirsher * entries in the LLH register. There is also 915adfc5217SJeff Kirsher * NIG_REG_P[01]_LLH_FUNC_MEM2 registers that complete the 916adfc5217SJeff Kirsher * total number of CAM entries to 16. 917adfc5217SJeff Kirsher * 918adfc5217SJeff Kirsher * Currently we won't configure NIG for MACs other than a primary ETH 919adfc5217SJeff Kirsher * MAC and iSCSI L2 MAC. 920adfc5217SJeff Kirsher * 921adfc5217SJeff Kirsher * If this MAC is moving from one Queue to another, no need to change 922adfc5217SJeff Kirsher * NIG configuration. 923adfc5217SJeff Kirsher */ 924adfc5217SJeff Kirsher if (cmd != BNX2X_VLAN_MAC_MOVE) { 925adfc5217SJeff Kirsher if (test_bit(BNX2X_ISCSI_ETH_MAC, vlan_mac_flags)) 926adfc5217SJeff Kirsher bnx2x_set_mac_in_nig(bp, add, mac, 9270a52fd01SYuval Mintz BNX2X_LLH_CAM_ISCSI_ETH_LINE); 928adfc5217SJeff Kirsher else if (test_bit(BNX2X_ETH_MAC, vlan_mac_flags)) 9290a52fd01SYuval Mintz bnx2x_set_mac_in_nig(bp, add, mac, 9300a52fd01SYuval Mintz BNX2X_LLH_CAM_ETH_LINE); 931adfc5217SJeff Kirsher } 932adfc5217SJeff Kirsher 933adfc5217SJeff Kirsher /* Reset the ramrod data buffer for the first rule */ 934adfc5217SJeff Kirsher if (rule_idx == 0) 935adfc5217SJeff Kirsher memset(data, 0, sizeof(*data)); 936adfc5217SJeff Kirsher 937adfc5217SJeff Kirsher /* Setup a command header */ 938adfc5217SJeff Kirsher bnx2x_vlan_mac_set_cmd_hdr_e2(bp, o, add, CLASSIFY_RULE_OPCODE_MAC, 939adfc5217SJeff Kirsher &rule_entry->mac.header); 940adfc5217SJeff Kirsher 9410f9dad10SJoe Perches DP(BNX2X_MSG_SP, "About to %s MAC %pM for Queue %d\n", 94251c1a580SMerav Sicron (add ? "add" : "delete"), mac, raw->cl_id); 943adfc5217SJeff Kirsher 944adfc5217SJeff Kirsher /* Set a MAC itself */ 945adfc5217SJeff Kirsher bnx2x_set_fw_mac_addr(&rule_entry->mac.mac_msb, 946adfc5217SJeff Kirsher &rule_entry->mac.mac_mid, 947adfc5217SJeff Kirsher &rule_entry->mac.mac_lsb, mac); 94891226790SDmitry Kravkov rule_entry->mac.inner_mac = 94991226790SDmitry Kravkov cpu_to_le16(elem->cmd_data.vlan_mac.u.mac.is_inner_mac); 950adfc5217SJeff Kirsher 951adfc5217SJeff Kirsher /* MOVE: Add a rule that will add this MAC to the target Queue */ 952adfc5217SJeff Kirsher if (cmd == BNX2X_VLAN_MAC_MOVE) { 953adfc5217SJeff Kirsher rule_entry++; 954adfc5217SJeff Kirsher rule_cnt++; 955adfc5217SJeff Kirsher 956adfc5217SJeff Kirsher /* Setup ramrod data */ 957adfc5217SJeff Kirsher bnx2x_vlan_mac_set_cmd_hdr_e2(bp, 958adfc5217SJeff Kirsher elem->cmd_data.vlan_mac.target_obj, 959adfc5217SJeff Kirsher true, CLASSIFY_RULE_OPCODE_MAC, 960adfc5217SJeff Kirsher &rule_entry->mac.header); 961adfc5217SJeff Kirsher 962adfc5217SJeff Kirsher /* Set a MAC itself */ 963adfc5217SJeff Kirsher bnx2x_set_fw_mac_addr(&rule_entry->mac.mac_msb, 964adfc5217SJeff Kirsher &rule_entry->mac.mac_mid, 965adfc5217SJeff Kirsher &rule_entry->mac.mac_lsb, mac); 96691226790SDmitry Kravkov rule_entry->mac.inner_mac = 96791226790SDmitry Kravkov cpu_to_le16(elem->cmd_data.vlan_mac. 96891226790SDmitry Kravkov u.mac.is_inner_mac); 969adfc5217SJeff Kirsher } 970adfc5217SJeff Kirsher 971adfc5217SJeff Kirsher /* Set the ramrod data header */ 972adfc5217SJeff Kirsher /* TODO: take this to the higher level in order to prevent multiple 973adfc5217SJeff Kirsher writing */ 974adfc5217SJeff Kirsher bnx2x_vlan_mac_set_rdata_hdr_e2(raw->cid, raw->state, &data->header, 975adfc5217SJeff Kirsher rule_cnt); 976adfc5217SJeff Kirsher } 977adfc5217SJeff Kirsher 978adfc5217SJeff Kirsher /** 979adfc5217SJeff Kirsher * bnx2x_vlan_mac_set_rdata_hdr_e1x - set a header in a single classify ramrod 980adfc5217SJeff Kirsher * 981adfc5217SJeff Kirsher * @bp: device handle 982adfc5217SJeff Kirsher * @o: queue 983adfc5217SJeff Kirsher * @type: 984adfc5217SJeff Kirsher * @cam_offset: offset in cam memory 985adfc5217SJeff Kirsher * @hdr: pointer to a header to setup 986adfc5217SJeff Kirsher * 987adfc5217SJeff Kirsher * E1/E1H 988adfc5217SJeff Kirsher */ 989adfc5217SJeff Kirsher static inline void bnx2x_vlan_mac_set_rdata_hdr_e1x(struct bnx2x *bp, 990adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *o, int type, int cam_offset, 991adfc5217SJeff Kirsher struct mac_configuration_hdr *hdr) 992adfc5217SJeff Kirsher { 993adfc5217SJeff Kirsher struct bnx2x_raw_obj *r = &o->raw; 994adfc5217SJeff Kirsher 995adfc5217SJeff Kirsher hdr->length = 1; 996adfc5217SJeff Kirsher hdr->offset = (u8)cam_offset; 99786564c3fSYuval Mintz hdr->client_id = cpu_to_le16(0xff); 99886564c3fSYuval Mintz hdr->echo = cpu_to_le32((r->cid & BNX2X_SWCID_MASK) | 99986564c3fSYuval Mintz (type << BNX2X_SWCID_SHIFT)); 1000adfc5217SJeff Kirsher } 1001adfc5217SJeff Kirsher 1002adfc5217SJeff Kirsher static inline void bnx2x_vlan_mac_set_cfg_entry_e1x(struct bnx2x *bp, 1003adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *o, bool add, int opcode, u8 *mac, 1004adfc5217SJeff Kirsher u16 vlan_id, struct mac_configuration_entry *cfg_entry) 1005adfc5217SJeff Kirsher { 1006adfc5217SJeff Kirsher struct bnx2x_raw_obj *r = &o->raw; 1007adfc5217SJeff Kirsher u32 cl_bit_vec = (1 << r->cl_id); 1008adfc5217SJeff Kirsher 1009adfc5217SJeff Kirsher cfg_entry->clients_bit_vector = cpu_to_le32(cl_bit_vec); 1010adfc5217SJeff Kirsher cfg_entry->pf_id = r->func_id; 1011adfc5217SJeff Kirsher cfg_entry->vlan_id = cpu_to_le16(vlan_id); 1012adfc5217SJeff Kirsher 1013adfc5217SJeff Kirsher if (add) { 1014adfc5217SJeff Kirsher SET_FLAG(cfg_entry->flags, MAC_CONFIGURATION_ENTRY_ACTION_TYPE, 1015adfc5217SJeff Kirsher T_ETH_MAC_COMMAND_SET); 1016adfc5217SJeff Kirsher SET_FLAG(cfg_entry->flags, 1017adfc5217SJeff Kirsher MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE, opcode); 1018adfc5217SJeff Kirsher 1019adfc5217SJeff Kirsher /* Set a MAC in a ramrod data */ 1020adfc5217SJeff Kirsher bnx2x_set_fw_mac_addr(&cfg_entry->msb_mac_addr, 1021adfc5217SJeff Kirsher &cfg_entry->middle_mac_addr, 1022adfc5217SJeff Kirsher &cfg_entry->lsb_mac_addr, mac); 1023adfc5217SJeff Kirsher } else 1024adfc5217SJeff Kirsher SET_FLAG(cfg_entry->flags, MAC_CONFIGURATION_ENTRY_ACTION_TYPE, 1025adfc5217SJeff Kirsher T_ETH_MAC_COMMAND_INVALIDATE); 1026adfc5217SJeff Kirsher } 1027adfc5217SJeff Kirsher 1028adfc5217SJeff Kirsher static inline void bnx2x_vlan_mac_set_rdata_e1x(struct bnx2x *bp, 1029adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *o, int type, int cam_offset, bool add, 1030adfc5217SJeff Kirsher u8 *mac, u16 vlan_id, int opcode, struct mac_configuration_cmd *config) 1031adfc5217SJeff Kirsher { 1032adfc5217SJeff Kirsher struct mac_configuration_entry *cfg_entry = &config->config_table[0]; 1033adfc5217SJeff Kirsher struct bnx2x_raw_obj *raw = &o->raw; 1034adfc5217SJeff Kirsher 1035adfc5217SJeff Kirsher bnx2x_vlan_mac_set_rdata_hdr_e1x(bp, o, type, cam_offset, 1036adfc5217SJeff Kirsher &config->hdr); 1037adfc5217SJeff Kirsher bnx2x_vlan_mac_set_cfg_entry_e1x(bp, o, add, opcode, mac, vlan_id, 1038adfc5217SJeff Kirsher cfg_entry); 1039adfc5217SJeff Kirsher 10400f9dad10SJoe Perches DP(BNX2X_MSG_SP, "%s MAC %pM CLID %d CAM offset %d\n", 104151c1a580SMerav Sicron (add ? "setting" : "clearing"), 10420f9dad10SJoe Perches mac, raw->cl_id, cam_offset); 1043adfc5217SJeff Kirsher } 1044adfc5217SJeff Kirsher 1045adfc5217SJeff Kirsher /** 1046adfc5217SJeff Kirsher * bnx2x_set_one_mac_e1x - fill a single MAC rule ramrod data 1047adfc5217SJeff Kirsher * 1048adfc5217SJeff Kirsher * @bp: device handle 1049adfc5217SJeff Kirsher * @o: bnx2x_vlan_mac_obj 1050adfc5217SJeff Kirsher * @elem: bnx2x_exeq_elem 1051adfc5217SJeff Kirsher * @rule_idx: rule_idx 1052adfc5217SJeff Kirsher * @cam_offset: cam_offset 1053adfc5217SJeff Kirsher */ 1054adfc5217SJeff Kirsher static void bnx2x_set_one_mac_e1x(struct bnx2x *bp, 1055adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *o, 1056adfc5217SJeff Kirsher struct bnx2x_exeq_elem *elem, int rule_idx, 1057adfc5217SJeff Kirsher int cam_offset) 1058adfc5217SJeff Kirsher { 1059adfc5217SJeff Kirsher struct bnx2x_raw_obj *raw = &o->raw; 1060adfc5217SJeff Kirsher struct mac_configuration_cmd *config = 1061adfc5217SJeff Kirsher (struct mac_configuration_cmd *)(raw->rdata); 106216a5fd92SYuval Mintz /* 57710 and 57711 do not support MOVE command, 1063adfc5217SJeff Kirsher * so it's either ADD or DEL 1064adfc5217SJeff Kirsher */ 1065adfc5217SJeff Kirsher bool add = (elem->cmd_data.vlan_mac.cmd == BNX2X_VLAN_MAC_ADD) ? 1066adfc5217SJeff Kirsher true : false; 1067adfc5217SJeff Kirsher 1068adfc5217SJeff Kirsher /* Reset the ramrod data buffer */ 1069adfc5217SJeff Kirsher memset(config, 0, sizeof(*config)); 1070adfc5217SJeff Kirsher 107133ac338cSYuval Mintz bnx2x_vlan_mac_set_rdata_e1x(bp, o, raw->state, 1072adfc5217SJeff Kirsher cam_offset, add, 1073adfc5217SJeff Kirsher elem->cmd_data.vlan_mac.u.mac.mac, 0, 1074adfc5217SJeff Kirsher ETH_VLAN_FILTER_ANY_VLAN, config); 1075adfc5217SJeff Kirsher } 1076adfc5217SJeff Kirsher 1077adfc5217SJeff Kirsher static void bnx2x_set_one_vlan_e2(struct bnx2x *bp, 1078adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *o, 1079adfc5217SJeff Kirsher struct bnx2x_exeq_elem *elem, int rule_idx, 1080adfc5217SJeff Kirsher int cam_offset) 1081adfc5217SJeff Kirsher { 1082adfc5217SJeff Kirsher struct bnx2x_raw_obj *raw = &o->raw; 1083adfc5217SJeff Kirsher struct eth_classify_rules_ramrod_data *data = 1084adfc5217SJeff Kirsher (struct eth_classify_rules_ramrod_data *)(raw->rdata); 1085adfc5217SJeff Kirsher int rule_cnt = rule_idx + 1; 1086adfc5217SJeff Kirsher union eth_classify_rule_cmd *rule_entry = &data->rules[rule_idx]; 108786564c3fSYuval Mintz enum bnx2x_vlan_mac_cmd cmd = elem->cmd_data.vlan_mac.cmd; 1088adfc5217SJeff Kirsher bool add = (cmd == BNX2X_VLAN_MAC_ADD) ? true : false; 1089adfc5217SJeff Kirsher u16 vlan = elem->cmd_data.vlan_mac.u.vlan.vlan; 1090adfc5217SJeff Kirsher 1091adfc5217SJeff Kirsher /* Reset the ramrod data buffer for the first rule */ 1092adfc5217SJeff Kirsher if (rule_idx == 0) 1093adfc5217SJeff Kirsher memset(data, 0, sizeof(*data)); 1094adfc5217SJeff Kirsher 1095adfc5217SJeff Kirsher /* Set a rule header */ 1096adfc5217SJeff Kirsher bnx2x_vlan_mac_set_cmd_hdr_e2(bp, o, add, CLASSIFY_RULE_OPCODE_VLAN, 1097adfc5217SJeff Kirsher &rule_entry->vlan.header); 1098adfc5217SJeff Kirsher 1099adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "About to %s VLAN %d\n", (add ? "add" : "delete"), 1100adfc5217SJeff Kirsher vlan); 1101adfc5217SJeff Kirsher 1102adfc5217SJeff Kirsher /* Set a VLAN itself */ 1103adfc5217SJeff Kirsher rule_entry->vlan.vlan = cpu_to_le16(vlan); 1104adfc5217SJeff Kirsher 1105adfc5217SJeff Kirsher /* MOVE: Add a rule that will add this MAC to the target Queue */ 1106adfc5217SJeff Kirsher if (cmd == BNX2X_VLAN_MAC_MOVE) { 1107adfc5217SJeff Kirsher rule_entry++; 1108adfc5217SJeff Kirsher rule_cnt++; 1109adfc5217SJeff Kirsher 1110adfc5217SJeff Kirsher /* Setup ramrod data */ 1111adfc5217SJeff Kirsher bnx2x_vlan_mac_set_cmd_hdr_e2(bp, 1112adfc5217SJeff Kirsher elem->cmd_data.vlan_mac.target_obj, 1113adfc5217SJeff Kirsher true, CLASSIFY_RULE_OPCODE_VLAN, 1114adfc5217SJeff Kirsher &rule_entry->vlan.header); 1115adfc5217SJeff Kirsher 1116adfc5217SJeff Kirsher /* Set a VLAN itself */ 1117adfc5217SJeff Kirsher rule_entry->vlan.vlan = cpu_to_le16(vlan); 1118adfc5217SJeff Kirsher } 1119adfc5217SJeff Kirsher 1120adfc5217SJeff Kirsher /* Set the ramrod data header */ 1121adfc5217SJeff Kirsher /* TODO: take this to the higher level in order to prevent multiple 1122adfc5217SJeff Kirsher writing */ 1123adfc5217SJeff Kirsher bnx2x_vlan_mac_set_rdata_hdr_e2(raw->cid, raw->state, &data->header, 1124adfc5217SJeff Kirsher rule_cnt); 1125adfc5217SJeff Kirsher } 1126adfc5217SJeff Kirsher 1127adfc5217SJeff Kirsher static void bnx2x_set_one_vlan_mac_e2(struct bnx2x *bp, 1128adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *o, 1129adfc5217SJeff Kirsher struct bnx2x_exeq_elem *elem, 1130adfc5217SJeff Kirsher int rule_idx, int cam_offset) 1131adfc5217SJeff Kirsher { 1132adfc5217SJeff Kirsher struct bnx2x_raw_obj *raw = &o->raw; 1133adfc5217SJeff Kirsher struct eth_classify_rules_ramrod_data *data = 1134adfc5217SJeff Kirsher (struct eth_classify_rules_ramrod_data *)(raw->rdata); 1135adfc5217SJeff Kirsher int rule_cnt = rule_idx + 1; 1136adfc5217SJeff Kirsher union eth_classify_rule_cmd *rule_entry = &data->rules[rule_idx]; 113786564c3fSYuval Mintz enum bnx2x_vlan_mac_cmd cmd = elem->cmd_data.vlan_mac.cmd; 1138adfc5217SJeff Kirsher bool add = (cmd == BNX2X_VLAN_MAC_ADD) ? true : false; 1139adfc5217SJeff Kirsher u16 vlan = elem->cmd_data.vlan_mac.u.vlan_mac.vlan; 1140adfc5217SJeff Kirsher u8 *mac = elem->cmd_data.vlan_mac.u.vlan_mac.mac; 1141adfc5217SJeff Kirsher 1142adfc5217SJeff Kirsher /* Reset the ramrod data buffer for the first rule */ 1143adfc5217SJeff Kirsher if (rule_idx == 0) 1144adfc5217SJeff Kirsher memset(data, 0, sizeof(*data)); 1145adfc5217SJeff Kirsher 1146adfc5217SJeff Kirsher /* Set a rule header */ 1147adfc5217SJeff Kirsher bnx2x_vlan_mac_set_cmd_hdr_e2(bp, o, add, CLASSIFY_RULE_OPCODE_PAIR, 1148adfc5217SJeff Kirsher &rule_entry->pair.header); 1149adfc5217SJeff Kirsher 115016a5fd92SYuval Mintz /* Set VLAN and MAC themselves */ 1151adfc5217SJeff Kirsher rule_entry->pair.vlan = cpu_to_le16(vlan); 1152adfc5217SJeff Kirsher bnx2x_set_fw_mac_addr(&rule_entry->pair.mac_msb, 1153adfc5217SJeff Kirsher &rule_entry->pair.mac_mid, 1154adfc5217SJeff Kirsher &rule_entry->pair.mac_lsb, mac); 115591226790SDmitry Kravkov rule_entry->pair.inner_mac = 115691226790SDmitry Kravkov cpu_to_le16(elem->cmd_data.vlan_mac.u.vlan_mac.is_inner_mac); 1157adfc5217SJeff Kirsher /* MOVE: Add a rule that will add this MAC to the target Queue */ 1158adfc5217SJeff Kirsher if (cmd == BNX2X_VLAN_MAC_MOVE) { 1159adfc5217SJeff Kirsher rule_entry++; 1160adfc5217SJeff Kirsher rule_cnt++; 1161adfc5217SJeff Kirsher 1162adfc5217SJeff Kirsher /* Setup ramrod data */ 1163adfc5217SJeff Kirsher bnx2x_vlan_mac_set_cmd_hdr_e2(bp, 1164adfc5217SJeff Kirsher elem->cmd_data.vlan_mac.target_obj, 1165adfc5217SJeff Kirsher true, CLASSIFY_RULE_OPCODE_PAIR, 1166adfc5217SJeff Kirsher &rule_entry->pair.header); 1167adfc5217SJeff Kirsher 1168adfc5217SJeff Kirsher /* Set a VLAN itself */ 1169adfc5217SJeff Kirsher rule_entry->pair.vlan = cpu_to_le16(vlan); 1170adfc5217SJeff Kirsher bnx2x_set_fw_mac_addr(&rule_entry->pair.mac_msb, 1171adfc5217SJeff Kirsher &rule_entry->pair.mac_mid, 1172adfc5217SJeff Kirsher &rule_entry->pair.mac_lsb, mac); 117391226790SDmitry Kravkov rule_entry->pair.inner_mac = 117491226790SDmitry Kravkov cpu_to_le16(elem->cmd_data.vlan_mac.u. 117591226790SDmitry Kravkov vlan_mac.is_inner_mac); 1176adfc5217SJeff Kirsher } 1177adfc5217SJeff Kirsher 1178adfc5217SJeff Kirsher /* Set the ramrod data header */ 1179adfc5217SJeff Kirsher /* TODO: take this to the higher level in order to prevent multiple 1180adfc5217SJeff Kirsher writing */ 1181adfc5217SJeff Kirsher bnx2x_vlan_mac_set_rdata_hdr_e2(raw->cid, raw->state, &data->header, 1182adfc5217SJeff Kirsher rule_cnt); 1183adfc5217SJeff Kirsher } 1184adfc5217SJeff Kirsher 1185adfc5217SJeff Kirsher /** 1186adfc5217SJeff Kirsher * bnx2x_set_one_vlan_mac_e1h - 1187adfc5217SJeff Kirsher * 1188adfc5217SJeff Kirsher * @bp: device handle 1189adfc5217SJeff Kirsher * @o: bnx2x_vlan_mac_obj 1190adfc5217SJeff Kirsher * @elem: bnx2x_exeq_elem 1191adfc5217SJeff Kirsher * @rule_idx: rule_idx 1192adfc5217SJeff Kirsher * @cam_offset: cam_offset 1193adfc5217SJeff Kirsher */ 1194adfc5217SJeff Kirsher static void bnx2x_set_one_vlan_mac_e1h(struct bnx2x *bp, 1195adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *o, 1196adfc5217SJeff Kirsher struct bnx2x_exeq_elem *elem, 1197adfc5217SJeff Kirsher int rule_idx, int cam_offset) 1198adfc5217SJeff Kirsher { 1199adfc5217SJeff Kirsher struct bnx2x_raw_obj *raw = &o->raw; 1200adfc5217SJeff Kirsher struct mac_configuration_cmd *config = 1201adfc5217SJeff Kirsher (struct mac_configuration_cmd *)(raw->rdata); 120216a5fd92SYuval Mintz /* 57710 and 57711 do not support MOVE command, 1203adfc5217SJeff Kirsher * so it's either ADD or DEL 1204adfc5217SJeff Kirsher */ 1205adfc5217SJeff Kirsher bool add = (elem->cmd_data.vlan_mac.cmd == BNX2X_VLAN_MAC_ADD) ? 1206adfc5217SJeff Kirsher true : false; 1207adfc5217SJeff Kirsher 1208adfc5217SJeff Kirsher /* Reset the ramrod data buffer */ 1209adfc5217SJeff Kirsher memset(config, 0, sizeof(*config)); 1210adfc5217SJeff Kirsher 1211adfc5217SJeff Kirsher bnx2x_vlan_mac_set_rdata_e1x(bp, o, BNX2X_FILTER_VLAN_MAC_PENDING, 1212adfc5217SJeff Kirsher cam_offset, add, 1213adfc5217SJeff Kirsher elem->cmd_data.vlan_mac.u.vlan_mac.mac, 1214adfc5217SJeff Kirsher elem->cmd_data.vlan_mac.u.vlan_mac.vlan, 1215adfc5217SJeff Kirsher ETH_VLAN_FILTER_CLASSIFY, config); 1216adfc5217SJeff Kirsher } 1217adfc5217SJeff Kirsher 1218adfc5217SJeff Kirsher /** 1219adfc5217SJeff Kirsher * bnx2x_vlan_mac_restore - reconfigure next MAC/VLAN/VLAN-MAC element 1220adfc5217SJeff Kirsher * 1221adfc5217SJeff Kirsher * @bp: device handle 1222adfc5217SJeff Kirsher * @p: command parameters 122316a5fd92SYuval Mintz * @ppos: pointer to the cookie 1224adfc5217SJeff Kirsher * 1225adfc5217SJeff Kirsher * reconfigure next MAC/VLAN/VLAN-MAC element from the 1226adfc5217SJeff Kirsher * previously configured elements list. 1227adfc5217SJeff Kirsher * 1228adfc5217SJeff Kirsher * from command parameters only RAMROD_COMP_WAIT bit in ramrod_flags is taken 1229adfc5217SJeff Kirsher * into an account 1230adfc5217SJeff Kirsher * 123116a5fd92SYuval Mintz * pointer to the cookie - that should be given back in the next call to make 1232adfc5217SJeff Kirsher * function handle the next element. If *ppos is set to NULL it will restart the 1233adfc5217SJeff Kirsher * iterator. If returned *ppos == NULL this means that the last element has been 1234adfc5217SJeff Kirsher * handled. 1235adfc5217SJeff Kirsher * 1236adfc5217SJeff Kirsher */ 1237adfc5217SJeff Kirsher static int bnx2x_vlan_mac_restore(struct bnx2x *bp, 1238adfc5217SJeff Kirsher struct bnx2x_vlan_mac_ramrod_params *p, 1239adfc5217SJeff Kirsher struct bnx2x_vlan_mac_registry_elem **ppos) 1240adfc5217SJeff Kirsher { 1241adfc5217SJeff Kirsher struct bnx2x_vlan_mac_registry_elem *pos; 1242adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *o = p->vlan_mac_obj; 1243adfc5217SJeff Kirsher 1244adfc5217SJeff Kirsher /* If list is empty - there is nothing to do here */ 1245adfc5217SJeff Kirsher if (list_empty(&o->head)) { 1246adfc5217SJeff Kirsher *ppos = NULL; 1247adfc5217SJeff Kirsher return 0; 1248adfc5217SJeff Kirsher } 1249adfc5217SJeff Kirsher 1250adfc5217SJeff Kirsher /* make a step... */ 1251adfc5217SJeff Kirsher if (*ppos == NULL) 1252adfc5217SJeff Kirsher *ppos = list_first_entry(&o->head, 1253adfc5217SJeff Kirsher struct bnx2x_vlan_mac_registry_elem, 1254adfc5217SJeff Kirsher link); 1255adfc5217SJeff Kirsher else 1256adfc5217SJeff Kirsher *ppos = list_next_entry(*ppos, link); 1257adfc5217SJeff Kirsher 1258adfc5217SJeff Kirsher pos = *ppos; 1259adfc5217SJeff Kirsher 1260adfc5217SJeff Kirsher /* If it's the last step - return NULL */ 1261adfc5217SJeff Kirsher if (list_is_last(&pos->link, &o->head)) 1262adfc5217SJeff Kirsher *ppos = NULL; 1263adfc5217SJeff Kirsher 1264adfc5217SJeff Kirsher /* Prepare a 'user_req' */ 1265adfc5217SJeff Kirsher memcpy(&p->user_req.u, &pos->u, sizeof(pos->u)); 1266adfc5217SJeff Kirsher 1267adfc5217SJeff Kirsher /* Set the command */ 1268adfc5217SJeff Kirsher p->user_req.cmd = BNX2X_VLAN_MAC_ADD; 1269adfc5217SJeff Kirsher 1270adfc5217SJeff Kirsher /* Set vlan_mac_flags */ 1271adfc5217SJeff Kirsher p->user_req.vlan_mac_flags = pos->vlan_mac_flags; 1272adfc5217SJeff Kirsher 1273adfc5217SJeff Kirsher /* Set a restore bit */ 1274adfc5217SJeff Kirsher __set_bit(RAMROD_RESTORE, &p->ramrod_flags); 1275adfc5217SJeff Kirsher 1276adfc5217SJeff Kirsher return bnx2x_config_vlan_mac(bp, p); 1277adfc5217SJeff Kirsher } 1278adfc5217SJeff Kirsher 127916a5fd92SYuval Mintz /* bnx2x_exeq_get_mac/bnx2x_exeq_get_vlan/bnx2x_exeq_get_vlan_mac return a 1280adfc5217SJeff Kirsher * pointer to an element with a specific criteria and NULL if such an element 1281adfc5217SJeff Kirsher * hasn't been found. 1282adfc5217SJeff Kirsher */ 1283adfc5217SJeff Kirsher static struct bnx2x_exeq_elem *bnx2x_exeq_get_mac( 1284adfc5217SJeff Kirsher struct bnx2x_exe_queue_obj *o, 1285adfc5217SJeff Kirsher struct bnx2x_exeq_elem *elem) 1286adfc5217SJeff Kirsher { 1287adfc5217SJeff Kirsher struct bnx2x_exeq_elem *pos; 1288adfc5217SJeff Kirsher struct bnx2x_mac_ramrod_data *data = &elem->cmd_data.vlan_mac.u.mac; 1289adfc5217SJeff Kirsher 1290adfc5217SJeff Kirsher /* Check pending for execution commands */ 1291adfc5217SJeff Kirsher list_for_each_entry(pos, &o->exe_queue, link) 1292adfc5217SJeff Kirsher if (!memcmp(&pos->cmd_data.vlan_mac.u.mac, data, 1293adfc5217SJeff Kirsher sizeof(*data)) && 1294adfc5217SJeff Kirsher (pos->cmd_data.vlan_mac.cmd == elem->cmd_data.vlan_mac.cmd)) 1295adfc5217SJeff Kirsher return pos; 1296adfc5217SJeff Kirsher 1297adfc5217SJeff Kirsher return NULL; 1298adfc5217SJeff Kirsher } 1299adfc5217SJeff Kirsher 1300adfc5217SJeff Kirsher static struct bnx2x_exeq_elem *bnx2x_exeq_get_vlan( 1301adfc5217SJeff Kirsher struct bnx2x_exe_queue_obj *o, 1302adfc5217SJeff Kirsher struct bnx2x_exeq_elem *elem) 1303adfc5217SJeff Kirsher { 1304adfc5217SJeff Kirsher struct bnx2x_exeq_elem *pos; 1305adfc5217SJeff Kirsher struct bnx2x_vlan_ramrod_data *data = &elem->cmd_data.vlan_mac.u.vlan; 1306adfc5217SJeff Kirsher 1307adfc5217SJeff Kirsher /* Check pending for execution commands */ 1308adfc5217SJeff Kirsher list_for_each_entry(pos, &o->exe_queue, link) 1309adfc5217SJeff Kirsher if (!memcmp(&pos->cmd_data.vlan_mac.u.vlan, data, 1310adfc5217SJeff Kirsher sizeof(*data)) && 1311adfc5217SJeff Kirsher (pos->cmd_data.vlan_mac.cmd == elem->cmd_data.vlan_mac.cmd)) 1312adfc5217SJeff Kirsher return pos; 1313adfc5217SJeff Kirsher 1314adfc5217SJeff Kirsher return NULL; 1315adfc5217SJeff Kirsher } 1316adfc5217SJeff Kirsher 1317adfc5217SJeff Kirsher static struct bnx2x_exeq_elem *bnx2x_exeq_get_vlan_mac( 1318adfc5217SJeff Kirsher struct bnx2x_exe_queue_obj *o, 1319adfc5217SJeff Kirsher struct bnx2x_exeq_elem *elem) 1320adfc5217SJeff Kirsher { 1321adfc5217SJeff Kirsher struct bnx2x_exeq_elem *pos; 1322adfc5217SJeff Kirsher struct bnx2x_vlan_mac_ramrod_data *data = 1323adfc5217SJeff Kirsher &elem->cmd_data.vlan_mac.u.vlan_mac; 1324adfc5217SJeff Kirsher 1325adfc5217SJeff Kirsher /* Check pending for execution commands */ 1326adfc5217SJeff Kirsher list_for_each_entry(pos, &o->exe_queue, link) 1327adfc5217SJeff Kirsher if (!memcmp(&pos->cmd_data.vlan_mac.u.vlan_mac, data, 1328adfc5217SJeff Kirsher sizeof(*data)) && 1329adfc5217SJeff Kirsher (pos->cmd_data.vlan_mac.cmd == elem->cmd_data.vlan_mac.cmd)) 1330adfc5217SJeff Kirsher return pos; 1331adfc5217SJeff Kirsher 1332adfc5217SJeff Kirsher return NULL; 1333adfc5217SJeff Kirsher } 1334adfc5217SJeff Kirsher 1335adfc5217SJeff Kirsher /** 1336adfc5217SJeff Kirsher * bnx2x_validate_vlan_mac_add - check if an ADD command can be executed 1337adfc5217SJeff Kirsher * 1338adfc5217SJeff Kirsher * @bp: device handle 1339adfc5217SJeff Kirsher * @qo: bnx2x_qable_obj 1340adfc5217SJeff Kirsher * @elem: bnx2x_exeq_elem 1341adfc5217SJeff Kirsher * 1342adfc5217SJeff Kirsher * Checks that the requested configuration can be added. If yes and if 1343adfc5217SJeff Kirsher * requested, consume CAM credit. 1344adfc5217SJeff Kirsher * 1345adfc5217SJeff Kirsher * The 'validate' is run after the 'optimize'. 1346adfc5217SJeff Kirsher * 1347adfc5217SJeff Kirsher */ 1348adfc5217SJeff Kirsher static inline int bnx2x_validate_vlan_mac_add(struct bnx2x *bp, 1349adfc5217SJeff Kirsher union bnx2x_qable_obj *qo, 1350adfc5217SJeff Kirsher struct bnx2x_exeq_elem *elem) 1351adfc5217SJeff Kirsher { 1352adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *o = &qo->vlan_mac; 1353adfc5217SJeff Kirsher struct bnx2x_exe_queue_obj *exeq = &o->exe_queue; 1354adfc5217SJeff Kirsher int rc; 1355adfc5217SJeff Kirsher 1356adfc5217SJeff Kirsher /* Check the registry */ 135751c1a580SMerav Sicron rc = o->check_add(bp, o, &elem->cmd_data.vlan_mac.u); 1358adfc5217SJeff Kirsher if (rc) { 135951c1a580SMerav Sicron DP(BNX2X_MSG_SP, "ADD command is not allowed considering current registry state.\n"); 1360adfc5217SJeff Kirsher return rc; 1361adfc5217SJeff Kirsher } 1362adfc5217SJeff Kirsher 136316a5fd92SYuval Mintz /* Check if there is a pending ADD command for this 1364adfc5217SJeff Kirsher * MAC/VLAN/VLAN-MAC. Return an error if there is. 1365adfc5217SJeff Kirsher */ 1366adfc5217SJeff Kirsher if (exeq->get(exeq, elem)) { 1367adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "There is a pending ADD command already\n"); 1368adfc5217SJeff Kirsher return -EEXIST; 1369adfc5217SJeff Kirsher } 1370adfc5217SJeff Kirsher 137116a5fd92SYuval Mintz /* TODO: Check the pending MOVE from other objects where this 1372adfc5217SJeff Kirsher * object is a destination object. 1373adfc5217SJeff Kirsher */ 1374adfc5217SJeff Kirsher 1375adfc5217SJeff Kirsher /* Consume the credit if not requested not to */ 1376adfc5217SJeff Kirsher if (!(test_bit(BNX2X_DONT_CONSUME_CAM_CREDIT, 1377adfc5217SJeff Kirsher &elem->cmd_data.vlan_mac.vlan_mac_flags) || 1378adfc5217SJeff Kirsher o->get_credit(o))) 1379adfc5217SJeff Kirsher return -EINVAL; 1380adfc5217SJeff Kirsher 1381adfc5217SJeff Kirsher return 0; 1382adfc5217SJeff Kirsher } 1383adfc5217SJeff Kirsher 1384adfc5217SJeff Kirsher /** 1385adfc5217SJeff Kirsher * bnx2x_validate_vlan_mac_del - check if the DEL command can be executed 1386adfc5217SJeff Kirsher * 1387adfc5217SJeff Kirsher * @bp: device handle 1388adfc5217SJeff Kirsher * @qo: quable object to check 1389adfc5217SJeff Kirsher * @elem: element that needs to be deleted 1390adfc5217SJeff Kirsher * 1391adfc5217SJeff Kirsher * Checks that the requested configuration can be deleted. If yes and if 1392adfc5217SJeff Kirsher * requested, returns a CAM credit. 1393adfc5217SJeff Kirsher * 1394adfc5217SJeff Kirsher * The 'validate' is run after the 'optimize'. 1395adfc5217SJeff Kirsher */ 1396adfc5217SJeff Kirsher static inline int bnx2x_validate_vlan_mac_del(struct bnx2x *bp, 1397adfc5217SJeff Kirsher union bnx2x_qable_obj *qo, 1398adfc5217SJeff Kirsher struct bnx2x_exeq_elem *elem) 1399adfc5217SJeff Kirsher { 1400adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *o = &qo->vlan_mac; 1401adfc5217SJeff Kirsher struct bnx2x_vlan_mac_registry_elem *pos; 1402adfc5217SJeff Kirsher struct bnx2x_exe_queue_obj *exeq = &o->exe_queue; 1403adfc5217SJeff Kirsher struct bnx2x_exeq_elem query_elem; 1404adfc5217SJeff Kirsher 1405adfc5217SJeff Kirsher /* If this classification can not be deleted (doesn't exist) 1406adfc5217SJeff Kirsher * - return a BNX2X_EXIST. 1407adfc5217SJeff Kirsher */ 140851c1a580SMerav Sicron pos = o->check_del(bp, o, &elem->cmd_data.vlan_mac.u); 1409adfc5217SJeff Kirsher if (!pos) { 141051c1a580SMerav Sicron DP(BNX2X_MSG_SP, "DEL command is not allowed considering current registry state\n"); 1411adfc5217SJeff Kirsher return -EEXIST; 1412adfc5217SJeff Kirsher } 1413adfc5217SJeff Kirsher 141416a5fd92SYuval Mintz /* Check if there are pending DEL or MOVE commands for this 1415adfc5217SJeff Kirsher * MAC/VLAN/VLAN-MAC. Return an error if so. 1416adfc5217SJeff Kirsher */ 1417adfc5217SJeff Kirsher memcpy(&query_elem, elem, sizeof(query_elem)); 1418adfc5217SJeff Kirsher 1419adfc5217SJeff Kirsher /* Check for MOVE commands */ 1420adfc5217SJeff Kirsher query_elem.cmd_data.vlan_mac.cmd = BNX2X_VLAN_MAC_MOVE; 1421adfc5217SJeff Kirsher if (exeq->get(exeq, &query_elem)) { 1422adfc5217SJeff Kirsher BNX2X_ERR("There is a pending MOVE command already\n"); 1423adfc5217SJeff Kirsher return -EINVAL; 1424adfc5217SJeff Kirsher } 1425adfc5217SJeff Kirsher 1426adfc5217SJeff Kirsher /* Check for DEL commands */ 1427adfc5217SJeff Kirsher if (exeq->get(exeq, elem)) { 1428adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "There is a pending DEL command already\n"); 1429adfc5217SJeff Kirsher return -EEXIST; 1430adfc5217SJeff Kirsher } 1431adfc5217SJeff Kirsher 1432adfc5217SJeff Kirsher /* Return the credit to the credit pool if not requested not to */ 1433adfc5217SJeff Kirsher if (!(test_bit(BNX2X_DONT_CONSUME_CAM_CREDIT, 1434adfc5217SJeff Kirsher &elem->cmd_data.vlan_mac.vlan_mac_flags) || 1435adfc5217SJeff Kirsher o->put_credit(o))) { 1436adfc5217SJeff Kirsher BNX2X_ERR("Failed to return a credit\n"); 1437adfc5217SJeff Kirsher return -EINVAL; 1438adfc5217SJeff Kirsher } 1439adfc5217SJeff Kirsher 1440adfc5217SJeff Kirsher return 0; 1441adfc5217SJeff Kirsher } 1442adfc5217SJeff Kirsher 1443adfc5217SJeff Kirsher /** 1444adfc5217SJeff Kirsher * bnx2x_validate_vlan_mac_move - check if the MOVE command can be executed 1445adfc5217SJeff Kirsher * 1446adfc5217SJeff Kirsher * @bp: device handle 1447adfc5217SJeff Kirsher * @qo: quable object to check (source) 1448adfc5217SJeff Kirsher * @elem: element that needs to be moved 1449adfc5217SJeff Kirsher * 1450adfc5217SJeff Kirsher * Checks that the requested configuration can be moved. If yes and if 1451adfc5217SJeff Kirsher * requested, returns a CAM credit. 1452adfc5217SJeff Kirsher * 1453adfc5217SJeff Kirsher * The 'validate' is run after the 'optimize'. 1454adfc5217SJeff Kirsher */ 1455adfc5217SJeff Kirsher static inline int bnx2x_validate_vlan_mac_move(struct bnx2x *bp, 1456adfc5217SJeff Kirsher union bnx2x_qable_obj *qo, 1457adfc5217SJeff Kirsher struct bnx2x_exeq_elem *elem) 1458adfc5217SJeff Kirsher { 1459adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *src_o = &qo->vlan_mac; 1460adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *dest_o = elem->cmd_data.vlan_mac.target_obj; 1461adfc5217SJeff Kirsher struct bnx2x_exeq_elem query_elem; 1462adfc5217SJeff Kirsher struct bnx2x_exe_queue_obj *src_exeq = &src_o->exe_queue; 1463adfc5217SJeff Kirsher struct bnx2x_exe_queue_obj *dest_exeq = &dest_o->exe_queue; 1464adfc5217SJeff Kirsher 146516a5fd92SYuval Mintz /* Check if we can perform this operation based on the current registry 1466adfc5217SJeff Kirsher * state. 1467adfc5217SJeff Kirsher */ 146851c1a580SMerav Sicron if (!src_o->check_move(bp, src_o, dest_o, 146951c1a580SMerav Sicron &elem->cmd_data.vlan_mac.u)) { 147051c1a580SMerav Sicron DP(BNX2X_MSG_SP, "MOVE command is not allowed considering current registry state\n"); 1471adfc5217SJeff Kirsher return -EINVAL; 1472adfc5217SJeff Kirsher } 1473adfc5217SJeff Kirsher 147416a5fd92SYuval Mintz /* Check if there is an already pending DEL or MOVE command for the 1475adfc5217SJeff Kirsher * source object or ADD command for a destination object. Return an 1476adfc5217SJeff Kirsher * error if so. 1477adfc5217SJeff Kirsher */ 1478adfc5217SJeff Kirsher memcpy(&query_elem, elem, sizeof(query_elem)); 1479adfc5217SJeff Kirsher 1480adfc5217SJeff Kirsher /* Check DEL on source */ 1481adfc5217SJeff Kirsher query_elem.cmd_data.vlan_mac.cmd = BNX2X_VLAN_MAC_DEL; 1482adfc5217SJeff Kirsher if (src_exeq->get(src_exeq, &query_elem)) { 148351c1a580SMerav Sicron BNX2X_ERR("There is a pending DEL command on the source queue already\n"); 1484adfc5217SJeff Kirsher return -EINVAL; 1485adfc5217SJeff Kirsher } 1486adfc5217SJeff Kirsher 1487adfc5217SJeff Kirsher /* Check MOVE on source */ 1488adfc5217SJeff Kirsher if (src_exeq->get(src_exeq, elem)) { 1489adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "There is a pending MOVE command already\n"); 1490adfc5217SJeff Kirsher return -EEXIST; 1491adfc5217SJeff Kirsher } 1492adfc5217SJeff Kirsher 1493adfc5217SJeff Kirsher /* Check ADD on destination */ 1494adfc5217SJeff Kirsher query_elem.cmd_data.vlan_mac.cmd = BNX2X_VLAN_MAC_ADD; 1495adfc5217SJeff Kirsher if (dest_exeq->get(dest_exeq, &query_elem)) { 149651c1a580SMerav Sicron BNX2X_ERR("There is a pending ADD command on the destination queue already\n"); 1497adfc5217SJeff Kirsher return -EINVAL; 1498adfc5217SJeff Kirsher } 1499adfc5217SJeff Kirsher 1500adfc5217SJeff Kirsher /* Consume the credit if not requested not to */ 1501adfc5217SJeff Kirsher if (!(test_bit(BNX2X_DONT_CONSUME_CAM_CREDIT_DEST, 1502adfc5217SJeff Kirsher &elem->cmd_data.vlan_mac.vlan_mac_flags) || 1503adfc5217SJeff Kirsher dest_o->get_credit(dest_o))) 1504adfc5217SJeff Kirsher return -EINVAL; 1505adfc5217SJeff Kirsher 1506adfc5217SJeff Kirsher if (!(test_bit(BNX2X_DONT_CONSUME_CAM_CREDIT, 1507adfc5217SJeff Kirsher &elem->cmd_data.vlan_mac.vlan_mac_flags) || 1508adfc5217SJeff Kirsher src_o->put_credit(src_o))) { 1509adfc5217SJeff Kirsher /* return the credit taken from dest... */ 1510adfc5217SJeff Kirsher dest_o->put_credit(dest_o); 1511adfc5217SJeff Kirsher return -EINVAL; 1512adfc5217SJeff Kirsher } 1513adfc5217SJeff Kirsher 1514adfc5217SJeff Kirsher return 0; 1515adfc5217SJeff Kirsher } 1516adfc5217SJeff Kirsher 1517adfc5217SJeff Kirsher static int bnx2x_validate_vlan_mac(struct bnx2x *bp, 1518adfc5217SJeff Kirsher union bnx2x_qable_obj *qo, 1519adfc5217SJeff Kirsher struct bnx2x_exeq_elem *elem) 1520adfc5217SJeff Kirsher { 1521adfc5217SJeff Kirsher switch (elem->cmd_data.vlan_mac.cmd) { 1522adfc5217SJeff Kirsher case BNX2X_VLAN_MAC_ADD: 1523adfc5217SJeff Kirsher return bnx2x_validate_vlan_mac_add(bp, qo, elem); 1524adfc5217SJeff Kirsher case BNX2X_VLAN_MAC_DEL: 1525adfc5217SJeff Kirsher return bnx2x_validate_vlan_mac_del(bp, qo, elem); 1526adfc5217SJeff Kirsher case BNX2X_VLAN_MAC_MOVE: 1527adfc5217SJeff Kirsher return bnx2x_validate_vlan_mac_move(bp, qo, elem); 1528adfc5217SJeff Kirsher default: 1529adfc5217SJeff Kirsher return -EINVAL; 1530adfc5217SJeff Kirsher } 1531adfc5217SJeff Kirsher } 1532adfc5217SJeff Kirsher 1533460a25cdSYuval Mintz static int bnx2x_remove_vlan_mac(struct bnx2x *bp, 1534460a25cdSYuval Mintz union bnx2x_qable_obj *qo, 1535460a25cdSYuval Mintz struct bnx2x_exeq_elem *elem) 1536460a25cdSYuval Mintz { 1537460a25cdSYuval Mintz int rc = 0; 1538460a25cdSYuval Mintz 1539460a25cdSYuval Mintz /* If consumption wasn't required, nothing to do */ 1540460a25cdSYuval Mintz if (test_bit(BNX2X_DONT_CONSUME_CAM_CREDIT, 1541460a25cdSYuval Mintz &elem->cmd_data.vlan_mac.vlan_mac_flags)) 1542460a25cdSYuval Mintz return 0; 1543460a25cdSYuval Mintz 1544460a25cdSYuval Mintz switch (elem->cmd_data.vlan_mac.cmd) { 1545460a25cdSYuval Mintz case BNX2X_VLAN_MAC_ADD: 1546460a25cdSYuval Mintz case BNX2X_VLAN_MAC_MOVE: 1547460a25cdSYuval Mintz rc = qo->vlan_mac.put_credit(&qo->vlan_mac); 1548460a25cdSYuval Mintz break; 1549460a25cdSYuval Mintz case BNX2X_VLAN_MAC_DEL: 1550460a25cdSYuval Mintz rc = qo->vlan_mac.get_credit(&qo->vlan_mac); 1551460a25cdSYuval Mintz break; 1552460a25cdSYuval Mintz default: 1553460a25cdSYuval Mintz return -EINVAL; 1554460a25cdSYuval Mintz } 1555460a25cdSYuval Mintz 1556460a25cdSYuval Mintz if (rc != true) 1557460a25cdSYuval Mintz return -EINVAL; 1558460a25cdSYuval Mintz 1559460a25cdSYuval Mintz return 0; 1560460a25cdSYuval Mintz } 1561460a25cdSYuval Mintz 1562adfc5217SJeff Kirsher /** 156316a5fd92SYuval Mintz * bnx2x_wait_vlan_mac - passively wait for 5 seconds until all work completes. 1564adfc5217SJeff Kirsher * 1565adfc5217SJeff Kirsher * @bp: device handle 1566adfc5217SJeff Kirsher * @o: bnx2x_vlan_mac_obj 1567adfc5217SJeff Kirsher * 1568adfc5217SJeff Kirsher */ 1569adfc5217SJeff Kirsher static int bnx2x_wait_vlan_mac(struct bnx2x *bp, 1570adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *o) 1571adfc5217SJeff Kirsher { 1572adfc5217SJeff Kirsher int cnt = 5000, rc; 1573adfc5217SJeff Kirsher struct bnx2x_exe_queue_obj *exeq = &o->exe_queue; 1574adfc5217SJeff Kirsher struct bnx2x_raw_obj *raw = &o->raw; 1575adfc5217SJeff Kirsher 1576adfc5217SJeff Kirsher while (cnt--) { 1577adfc5217SJeff Kirsher /* Wait for the current command to complete */ 1578adfc5217SJeff Kirsher rc = raw->wait_comp(bp, raw); 1579adfc5217SJeff Kirsher if (rc) 1580adfc5217SJeff Kirsher return rc; 1581adfc5217SJeff Kirsher 1582adfc5217SJeff Kirsher /* Wait until there are no pending commands */ 1583adfc5217SJeff Kirsher if (!bnx2x_exe_queue_empty(exeq)) 15840926d499SYuval Mintz usleep_range(1000, 2000); 1585adfc5217SJeff Kirsher else 1586adfc5217SJeff Kirsher return 0; 1587adfc5217SJeff Kirsher } 1588adfc5217SJeff Kirsher 1589adfc5217SJeff Kirsher return -EBUSY; 1590adfc5217SJeff Kirsher } 1591adfc5217SJeff Kirsher 15928b09be5fSYuval Mintz static int __bnx2x_vlan_mac_execute_step(struct bnx2x *bp, 15938b09be5fSYuval Mintz struct bnx2x_vlan_mac_obj *o, 15948b09be5fSYuval Mintz unsigned long *ramrod_flags) 15958b09be5fSYuval Mintz { 15968b09be5fSYuval Mintz int rc = 0; 15978b09be5fSYuval Mintz 15988b09be5fSYuval Mintz spin_lock_bh(&o->exe_queue.lock); 15998b09be5fSYuval Mintz 16008b09be5fSYuval Mintz DP(BNX2X_MSG_SP, "vlan_mac_execute_step - trying to take writer lock\n"); 16018b09be5fSYuval Mintz rc = __bnx2x_vlan_mac_h_write_trylock(bp, o); 16028b09be5fSYuval Mintz 16038b09be5fSYuval Mintz if (rc != 0) { 16048b09be5fSYuval Mintz __bnx2x_vlan_mac_h_pend(bp, o, *ramrod_flags); 16058b09be5fSYuval Mintz 16068b09be5fSYuval Mintz /* Calling function should not diffrentiate between this case 16078b09be5fSYuval Mintz * and the case in which there is already a pending ramrod 16088b09be5fSYuval Mintz */ 16098b09be5fSYuval Mintz rc = 1; 16108b09be5fSYuval Mintz } else { 16118b09be5fSYuval Mintz rc = bnx2x_exe_queue_step(bp, &o->exe_queue, ramrod_flags); 16128b09be5fSYuval Mintz } 16138b09be5fSYuval Mintz spin_unlock_bh(&o->exe_queue.lock); 16148b09be5fSYuval Mintz 16158b09be5fSYuval Mintz return rc; 16168b09be5fSYuval Mintz } 16178b09be5fSYuval Mintz 1618adfc5217SJeff Kirsher /** 1619adfc5217SJeff Kirsher * bnx2x_complete_vlan_mac - complete one VLAN-MAC ramrod 1620adfc5217SJeff Kirsher * 1621adfc5217SJeff Kirsher * @bp: device handle 1622adfc5217SJeff Kirsher * @o: bnx2x_vlan_mac_obj 1623adfc5217SJeff Kirsher * @cqe: 1624adfc5217SJeff Kirsher * @cont: if true schedule next execution chunk 1625adfc5217SJeff Kirsher * 1626adfc5217SJeff Kirsher */ 1627adfc5217SJeff Kirsher static int bnx2x_complete_vlan_mac(struct bnx2x *bp, 1628adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *o, 1629adfc5217SJeff Kirsher union event_ring_elem *cqe, 1630adfc5217SJeff Kirsher unsigned long *ramrod_flags) 1631adfc5217SJeff Kirsher { 1632adfc5217SJeff Kirsher struct bnx2x_raw_obj *r = &o->raw; 1633adfc5217SJeff Kirsher int rc; 1634adfc5217SJeff Kirsher 16358b09be5fSYuval Mintz /* Clearing the pending list & raw state should be made 16368b09be5fSYuval Mintz * atomically (as execution flow assumes they represent the same). 16378b09be5fSYuval Mintz */ 16388b09be5fSYuval Mintz spin_lock_bh(&o->exe_queue.lock); 16398b09be5fSYuval Mintz 1640adfc5217SJeff Kirsher /* Reset pending list */ 16418b09be5fSYuval Mintz __bnx2x_exe_queue_reset_pending(bp, &o->exe_queue); 1642adfc5217SJeff Kirsher 1643adfc5217SJeff Kirsher /* Clear pending */ 1644adfc5217SJeff Kirsher r->clear_pending(r); 1645adfc5217SJeff Kirsher 16468b09be5fSYuval Mintz spin_unlock_bh(&o->exe_queue.lock); 16478b09be5fSYuval Mintz 1648adfc5217SJeff Kirsher /* If ramrod failed this is most likely a SW bug */ 1649adfc5217SJeff Kirsher if (cqe->message.error) 1650adfc5217SJeff Kirsher return -EINVAL; 1651adfc5217SJeff Kirsher 16522de67439SYuval Mintz /* Run the next bulk of pending commands if requested */ 1653adfc5217SJeff Kirsher if (test_bit(RAMROD_CONT, ramrod_flags)) { 16548b09be5fSYuval Mintz rc = __bnx2x_vlan_mac_execute_step(bp, o, ramrod_flags); 16558b09be5fSYuval Mintz 1656adfc5217SJeff Kirsher if (rc < 0) 1657adfc5217SJeff Kirsher return rc; 1658adfc5217SJeff Kirsher } 1659adfc5217SJeff Kirsher 1660adfc5217SJeff Kirsher /* If there is more work to do return PENDING */ 1661adfc5217SJeff Kirsher if (!bnx2x_exe_queue_empty(&o->exe_queue)) 1662adfc5217SJeff Kirsher return 1; 1663adfc5217SJeff Kirsher 1664adfc5217SJeff Kirsher return 0; 1665adfc5217SJeff Kirsher } 1666adfc5217SJeff Kirsher 1667adfc5217SJeff Kirsher /** 1668adfc5217SJeff Kirsher * bnx2x_optimize_vlan_mac - optimize ADD and DEL commands. 1669adfc5217SJeff Kirsher * 1670adfc5217SJeff Kirsher * @bp: device handle 1671adfc5217SJeff Kirsher * @o: bnx2x_qable_obj 1672adfc5217SJeff Kirsher * @elem: bnx2x_exeq_elem 1673adfc5217SJeff Kirsher */ 1674adfc5217SJeff Kirsher static int bnx2x_optimize_vlan_mac(struct bnx2x *bp, 1675adfc5217SJeff Kirsher union bnx2x_qable_obj *qo, 1676adfc5217SJeff Kirsher struct bnx2x_exeq_elem *elem) 1677adfc5217SJeff Kirsher { 1678adfc5217SJeff Kirsher struct bnx2x_exeq_elem query, *pos; 1679adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *o = &qo->vlan_mac; 1680adfc5217SJeff Kirsher struct bnx2x_exe_queue_obj *exeq = &o->exe_queue; 1681adfc5217SJeff Kirsher 1682adfc5217SJeff Kirsher memcpy(&query, elem, sizeof(query)); 1683adfc5217SJeff Kirsher 1684adfc5217SJeff Kirsher switch (elem->cmd_data.vlan_mac.cmd) { 1685adfc5217SJeff Kirsher case BNX2X_VLAN_MAC_ADD: 1686adfc5217SJeff Kirsher query.cmd_data.vlan_mac.cmd = BNX2X_VLAN_MAC_DEL; 1687adfc5217SJeff Kirsher break; 1688adfc5217SJeff Kirsher case BNX2X_VLAN_MAC_DEL: 1689adfc5217SJeff Kirsher query.cmd_data.vlan_mac.cmd = BNX2X_VLAN_MAC_ADD; 1690adfc5217SJeff Kirsher break; 1691adfc5217SJeff Kirsher default: 1692adfc5217SJeff Kirsher /* Don't handle anything other than ADD or DEL */ 1693adfc5217SJeff Kirsher return 0; 1694adfc5217SJeff Kirsher } 1695adfc5217SJeff Kirsher 1696adfc5217SJeff Kirsher /* If we found the appropriate element - delete it */ 1697adfc5217SJeff Kirsher pos = exeq->get(exeq, &query); 1698adfc5217SJeff Kirsher if (pos) { 1699adfc5217SJeff Kirsher 1700adfc5217SJeff Kirsher /* Return the credit of the optimized command */ 1701adfc5217SJeff Kirsher if (!test_bit(BNX2X_DONT_CONSUME_CAM_CREDIT, 1702adfc5217SJeff Kirsher &pos->cmd_data.vlan_mac.vlan_mac_flags)) { 1703adfc5217SJeff Kirsher if ((query.cmd_data.vlan_mac.cmd == 1704adfc5217SJeff Kirsher BNX2X_VLAN_MAC_ADD) && !o->put_credit(o)) { 170551c1a580SMerav Sicron BNX2X_ERR("Failed to return the credit for the optimized ADD command\n"); 1706adfc5217SJeff Kirsher return -EINVAL; 1707adfc5217SJeff Kirsher } else if (!o->get_credit(o)) { /* VLAN_MAC_DEL */ 170851c1a580SMerav Sicron BNX2X_ERR("Failed to recover the credit from the optimized DEL command\n"); 1709adfc5217SJeff Kirsher return -EINVAL; 1710adfc5217SJeff Kirsher } 1711adfc5217SJeff Kirsher } 1712adfc5217SJeff Kirsher 1713adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "Optimizing %s command\n", 1714adfc5217SJeff Kirsher (elem->cmd_data.vlan_mac.cmd == BNX2X_VLAN_MAC_ADD) ? 1715adfc5217SJeff Kirsher "ADD" : "DEL"); 1716adfc5217SJeff Kirsher 1717adfc5217SJeff Kirsher list_del(&pos->link); 1718adfc5217SJeff Kirsher bnx2x_exe_queue_free_elem(bp, pos); 1719adfc5217SJeff Kirsher return 1; 1720adfc5217SJeff Kirsher } 1721adfc5217SJeff Kirsher 1722adfc5217SJeff Kirsher return 0; 1723adfc5217SJeff Kirsher } 1724adfc5217SJeff Kirsher 1725adfc5217SJeff Kirsher /** 1726adfc5217SJeff Kirsher * bnx2x_vlan_mac_get_registry_elem - prepare a registry element 1727adfc5217SJeff Kirsher * 1728adfc5217SJeff Kirsher * @bp: device handle 1729adfc5217SJeff Kirsher * @o: 1730adfc5217SJeff Kirsher * @elem: 1731adfc5217SJeff Kirsher * @restore: 1732adfc5217SJeff Kirsher * @re: 1733adfc5217SJeff Kirsher * 1734adfc5217SJeff Kirsher * prepare a registry element according to the current command request. 1735adfc5217SJeff Kirsher */ 1736adfc5217SJeff Kirsher static inline int bnx2x_vlan_mac_get_registry_elem( 1737adfc5217SJeff Kirsher struct bnx2x *bp, 1738adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *o, 1739adfc5217SJeff Kirsher struct bnx2x_exeq_elem *elem, 1740adfc5217SJeff Kirsher bool restore, 1741adfc5217SJeff Kirsher struct bnx2x_vlan_mac_registry_elem **re) 1742adfc5217SJeff Kirsher { 174386564c3fSYuval Mintz enum bnx2x_vlan_mac_cmd cmd = elem->cmd_data.vlan_mac.cmd; 1744adfc5217SJeff Kirsher struct bnx2x_vlan_mac_registry_elem *reg_elem; 1745adfc5217SJeff Kirsher 1746adfc5217SJeff Kirsher /* Allocate a new registry element if needed. */ 1747adfc5217SJeff Kirsher if (!restore && 1748adfc5217SJeff Kirsher ((cmd == BNX2X_VLAN_MAC_ADD) || (cmd == BNX2X_VLAN_MAC_MOVE))) { 1749adfc5217SJeff Kirsher reg_elem = kzalloc(sizeof(*reg_elem), GFP_ATOMIC); 1750adfc5217SJeff Kirsher if (!reg_elem) 1751adfc5217SJeff Kirsher return -ENOMEM; 1752adfc5217SJeff Kirsher 1753adfc5217SJeff Kirsher /* Get a new CAM offset */ 1754adfc5217SJeff Kirsher if (!o->get_cam_offset(o, ®_elem->cam_offset)) { 175516a5fd92SYuval Mintz /* This shall never happen, because we have checked the 175616a5fd92SYuval Mintz * CAM availability in the 'validate'. 1757adfc5217SJeff Kirsher */ 1758adfc5217SJeff Kirsher WARN_ON(1); 1759adfc5217SJeff Kirsher kfree(reg_elem); 1760adfc5217SJeff Kirsher return -EINVAL; 1761adfc5217SJeff Kirsher } 1762adfc5217SJeff Kirsher 1763adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "Got cam offset %d\n", reg_elem->cam_offset); 1764adfc5217SJeff Kirsher 1765adfc5217SJeff Kirsher /* Set a VLAN-MAC data */ 1766adfc5217SJeff Kirsher memcpy(®_elem->u, &elem->cmd_data.vlan_mac.u, 1767adfc5217SJeff Kirsher sizeof(reg_elem->u)); 1768adfc5217SJeff Kirsher 1769adfc5217SJeff Kirsher /* Copy the flags (needed for DEL and RESTORE flows) */ 1770adfc5217SJeff Kirsher reg_elem->vlan_mac_flags = 1771adfc5217SJeff Kirsher elem->cmd_data.vlan_mac.vlan_mac_flags; 1772adfc5217SJeff Kirsher } else /* DEL, RESTORE */ 177351c1a580SMerav Sicron reg_elem = o->check_del(bp, o, &elem->cmd_data.vlan_mac.u); 1774adfc5217SJeff Kirsher 1775adfc5217SJeff Kirsher *re = reg_elem; 1776adfc5217SJeff Kirsher return 0; 1777adfc5217SJeff Kirsher } 1778adfc5217SJeff Kirsher 1779adfc5217SJeff Kirsher /** 1780adfc5217SJeff Kirsher * bnx2x_execute_vlan_mac - execute vlan mac command 1781adfc5217SJeff Kirsher * 1782adfc5217SJeff Kirsher * @bp: device handle 1783adfc5217SJeff Kirsher * @qo: 1784adfc5217SJeff Kirsher * @exe_chunk: 1785adfc5217SJeff Kirsher * @ramrod_flags: 1786adfc5217SJeff Kirsher * 1787adfc5217SJeff Kirsher * go and send a ramrod! 1788adfc5217SJeff Kirsher */ 1789adfc5217SJeff Kirsher static int bnx2x_execute_vlan_mac(struct bnx2x *bp, 1790adfc5217SJeff Kirsher union bnx2x_qable_obj *qo, 1791adfc5217SJeff Kirsher struct list_head *exe_chunk, 1792adfc5217SJeff Kirsher unsigned long *ramrod_flags) 1793adfc5217SJeff Kirsher { 1794adfc5217SJeff Kirsher struct bnx2x_exeq_elem *elem; 1795adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *o = &qo->vlan_mac, *cam_obj; 1796adfc5217SJeff Kirsher struct bnx2x_raw_obj *r = &o->raw; 1797adfc5217SJeff Kirsher int rc, idx = 0; 1798adfc5217SJeff Kirsher bool restore = test_bit(RAMROD_RESTORE, ramrod_flags); 1799adfc5217SJeff Kirsher bool drv_only = test_bit(RAMROD_DRV_CLR_ONLY, ramrod_flags); 1800adfc5217SJeff Kirsher struct bnx2x_vlan_mac_registry_elem *reg_elem; 180186564c3fSYuval Mintz enum bnx2x_vlan_mac_cmd cmd; 1802adfc5217SJeff Kirsher 180316a5fd92SYuval Mintz /* If DRIVER_ONLY execution is requested, cleanup a registry 1804adfc5217SJeff Kirsher * and exit. Otherwise send a ramrod to FW. 1805adfc5217SJeff Kirsher */ 1806adfc5217SJeff Kirsher if (!drv_only) { 1807adfc5217SJeff Kirsher WARN_ON(r->check_pending(r)); 1808adfc5217SJeff Kirsher 1809adfc5217SJeff Kirsher /* Set pending */ 1810adfc5217SJeff Kirsher r->set_pending(r); 1811adfc5217SJeff Kirsher 181216a5fd92SYuval Mintz /* Fill the ramrod data */ 1813adfc5217SJeff Kirsher list_for_each_entry(elem, exe_chunk, link) { 1814adfc5217SJeff Kirsher cmd = elem->cmd_data.vlan_mac.cmd; 181516a5fd92SYuval Mintz /* We will add to the target object in MOVE command, so 1816adfc5217SJeff Kirsher * change the object for a CAM search. 1817adfc5217SJeff Kirsher */ 1818adfc5217SJeff Kirsher if (cmd == BNX2X_VLAN_MAC_MOVE) 1819adfc5217SJeff Kirsher cam_obj = elem->cmd_data.vlan_mac.target_obj; 1820adfc5217SJeff Kirsher else 1821adfc5217SJeff Kirsher cam_obj = o; 1822adfc5217SJeff Kirsher 1823adfc5217SJeff Kirsher rc = bnx2x_vlan_mac_get_registry_elem(bp, cam_obj, 1824adfc5217SJeff Kirsher elem, restore, 1825adfc5217SJeff Kirsher ®_elem); 1826adfc5217SJeff Kirsher if (rc) 1827adfc5217SJeff Kirsher goto error_exit; 1828adfc5217SJeff Kirsher 1829adfc5217SJeff Kirsher WARN_ON(!reg_elem); 1830adfc5217SJeff Kirsher 1831adfc5217SJeff Kirsher /* Push a new entry into the registry */ 1832adfc5217SJeff Kirsher if (!restore && 1833adfc5217SJeff Kirsher ((cmd == BNX2X_VLAN_MAC_ADD) || 1834adfc5217SJeff Kirsher (cmd == BNX2X_VLAN_MAC_MOVE))) 1835adfc5217SJeff Kirsher list_add(®_elem->link, &cam_obj->head); 1836adfc5217SJeff Kirsher 1837adfc5217SJeff Kirsher /* Configure a single command in a ramrod data buffer */ 1838adfc5217SJeff Kirsher o->set_one_rule(bp, o, elem, idx, 1839adfc5217SJeff Kirsher reg_elem->cam_offset); 1840adfc5217SJeff Kirsher 1841adfc5217SJeff Kirsher /* MOVE command consumes 2 entries in the ramrod data */ 1842adfc5217SJeff Kirsher if (cmd == BNX2X_VLAN_MAC_MOVE) 1843adfc5217SJeff Kirsher idx += 2; 1844adfc5217SJeff Kirsher else 1845adfc5217SJeff Kirsher idx++; 1846adfc5217SJeff Kirsher } 1847adfc5217SJeff Kirsher 184816a5fd92SYuval Mintz /* No need for an explicit memory barrier here as long we would 1849adfc5217SJeff Kirsher * need to ensure the ordering of writing to the SPQ element 1850adfc5217SJeff Kirsher * and updating of the SPQ producer which involves a memory 1851adfc5217SJeff Kirsher * read and we will have to put a full memory barrier there 1852adfc5217SJeff Kirsher * (inside bnx2x_sp_post()). 1853adfc5217SJeff Kirsher */ 1854adfc5217SJeff Kirsher 1855adfc5217SJeff Kirsher rc = bnx2x_sp_post(bp, o->ramrod_cmd, r->cid, 1856adfc5217SJeff Kirsher U64_HI(r->rdata_mapping), 1857adfc5217SJeff Kirsher U64_LO(r->rdata_mapping), 1858adfc5217SJeff Kirsher ETH_CONNECTION_TYPE); 1859adfc5217SJeff Kirsher if (rc) 1860adfc5217SJeff Kirsher goto error_exit; 1861adfc5217SJeff Kirsher } 1862adfc5217SJeff Kirsher 1863adfc5217SJeff Kirsher /* Now, when we are done with the ramrod - clean up the registry */ 1864adfc5217SJeff Kirsher list_for_each_entry(elem, exe_chunk, link) { 1865adfc5217SJeff Kirsher cmd = elem->cmd_data.vlan_mac.cmd; 1866adfc5217SJeff Kirsher if ((cmd == BNX2X_VLAN_MAC_DEL) || 1867adfc5217SJeff Kirsher (cmd == BNX2X_VLAN_MAC_MOVE)) { 186851c1a580SMerav Sicron reg_elem = o->check_del(bp, o, 186951c1a580SMerav Sicron &elem->cmd_data.vlan_mac.u); 1870adfc5217SJeff Kirsher 1871adfc5217SJeff Kirsher WARN_ON(!reg_elem); 1872adfc5217SJeff Kirsher 1873adfc5217SJeff Kirsher o->put_cam_offset(o, reg_elem->cam_offset); 1874adfc5217SJeff Kirsher list_del(®_elem->link); 1875adfc5217SJeff Kirsher kfree(reg_elem); 1876adfc5217SJeff Kirsher } 1877adfc5217SJeff Kirsher } 1878adfc5217SJeff Kirsher 1879adfc5217SJeff Kirsher if (!drv_only) 1880adfc5217SJeff Kirsher return 1; 1881adfc5217SJeff Kirsher else 1882adfc5217SJeff Kirsher return 0; 1883adfc5217SJeff Kirsher 1884adfc5217SJeff Kirsher error_exit: 1885adfc5217SJeff Kirsher r->clear_pending(r); 1886adfc5217SJeff Kirsher 1887adfc5217SJeff Kirsher /* Cleanup a registry in case of a failure */ 1888adfc5217SJeff Kirsher list_for_each_entry(elem, exe_chunk, link) { 1889adfc5217SJeff Kirsher cmd = elem->cmd_data.vlan_mac.cmd; 1890adfc5217SJeff Kirsher 1891adfc5217SJeff Kirsher if (cmd == BNX2X_VLAN_MAC_MOVE) 1892adfc5217SJeff Kirsher cam_obj = elem->cmd_data.vlan_mac.target_obj; 1893adfc5217SJeff Kirsher else 1894adfc5217SJeff Kirsher cam_obj = o; 1895adfc5217SJeff Kirsher 1896adfc5217SJeff Kirsher /* Delete all newly added above entries */ 1897adfc5217SJeff Kirsher if (!restore && 1898adfc5217SJeff Kirsher ((cmd == BNX2X_VLAN_MAC_ADD) || 1899adfc5217SJeff Kirsher (cmd == BNX2X_VLAN_MAC_MOVE))) { 190051c1a580SMerav Sicron reg_elem = o->check_del(bp, cam_obj, 1901adfc5217SJeff Kirsher &elem->cmd_data.vlan_mac.u); 1902adfc5217SJeff Kirsher if (reg_elem) { 1903adfc5217SJeff Kirsher list_del(®_elem->link); 1904adfc5217SJeff Kirsher kfree(reg_elem); 1905adfc5217SJeff Kirsher } 1906adfc5217SJeff Kirsher } 1907adfc5217SJeff Kirsher } 1908adfc5217SJeff Kirsher 1909adfc5217SJeff Kirsher return rc; 1910adfc5217SJeff Kirsher } 1911adfc5217SJeff Kirsher 1912adfc5217SJeff Kirsher static inline int bnx2x_vlan_mac_push_new_cmd( 1913adfc5217SJeff Kirsher struct bnx2x *bp, 1914adfc5217SJeff Kirsher struct bnx2x_vlan_mac_ramrod_params *p) 1915adfc5217SJeff Kirsher { 1916adfc5217SJeff Kirsher struct bnx2x_exeq_elem *elem; 1917adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *o = p->vlan_mac_obj; 1918adfc5217SJeff Kirsher bool restore = test_bit(RAMROD_RESTORE, &p->ramrod_flags); 1919adfc5217SJeff Kirsher 1920adfc5217SJeff Kirsher /* Allocate the execution queue element */ 1921adfc5217SJeff Kirsher elem = bnx2x_exe_queue_alloc_elem(bp); 1922adfc5217SJeff Kirsher if (!elem) 1923adfc5217SJeff Kirsher return -ENOMEM; 1924adfc5217SJeff Kirsher 1925adfc5217SJeff Kirsher /* Set the command 'length' */ 1926adfc5217SJeff Kirsher switch (p->user_req.cmd) { 1927adfc5217SJeff Kirsher case BNX2X_VLAN_MAC_MOVE: 1928adfc5217SJeff Kirsher elem->cmd_len = 2; 1929adfc5217SJeff Kirsher break; 1930adfc5217SJeff Kirsher default: 1931adfc5217SJeff Kirsher elem->cmd_len = 1; 1932adfc5217SJeff Kirsher } 1933adfc5217SJeff Kirsher 1934adfc5217SJeff Kirsher /* Fill the object specific info */ 1935adfc5217SJeff Kirsher memcpy(&elem->cmd_data.vlan_mac, &p->user_req, sizeof(p->user_req)); 1936adfc5217SJeff Kirsher 1937adfc5217SJeff Kirsher /* Try to add a new command to the pending list */ 1938adfc5217SJeff Kirsher return bnx2x_exe_queue_add(bp, &o->exe_queue, elem, restore); 1939adfc5217SJeff Kirsher } 1940adfc5217SJeff Kirsher 1941adfc5217SJeff Kirsher /** 1942adfc5217SJeff Kirsher * bnx2x_config_vlan_mac - configure VLAN/MAC/VLAN_MAC filtering rules. 1943adfc5217SJeff Kirsher * 1944adfc5217SJeff Kirsher * @bp: device handle 1945adfc5217SJeff Kirsher * @p: 1946adfc5217SJeff Kirsher * 1947adfc5217SJeff Kirsher */ 19488b09be5fSYuval Mintz int bnx2x_config_vlan_mac(struct bnx2x *bp, 1949adfc5217SJeff Kirsher struct bnx2x_vlan_mac_ramrod_params *p) 1950adfc5217SJeff Kirsher { 1951adfc5217SJeff Kirsher int rc = 0; 1952adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *o = p->vlan_mac_obj; 1953adfc5217SJeff Kirsher unsigned long *ramrod_flags = &p->ramrod_flags; 1954adfc5217SJeff Kirsher bool cont = test_bit(RAMROD_CONT, ramrod_flags); 1955adfc5217SJeff Kirsher struct bnx2x_raw_obj *raw = &o->raw; 1956adfc5217SJeff Kirsher 1957adfc5217SJeff Kirsher /* 1958adfc5217SJeff Kirsher * Add new elements to the execution list for commands that require it. 1959adfc5217SJeff Kirsher */ 1960adfc5217SJeff Kirsher if (!cont) { 1961adfc5217SJeff Kirsher rc = bnx2x_vlan_mac_push_new_cmd(bp, p); 1962adfc5217SJeff Kirsher if (rc) 1963adfc5217SJeff Kirsher return rc; 1964adfc5217SJeff Kirsher } 1965adfc5217SJeff Kirsher 196616a5fd92SYuval Mintz /* If nothing will be executed further in this iteration we want to 1967adfc5217SJeff Kirsher * return PENDING if there are pending commands 1968adfc5217SJeff Kirsher */ 1969adfc5217SJeff Kirsher if (!bnx2x_exe_queue_empty(&o->exe_queue)) 1970adfc5217SJeff Kirsher rc = 1; 1971adfc5217SJeff Kirsher 1972adfc5217SJeff Kirsher if (test_bit(RAMROD_DRV_CLR_ONLY, ramrod_flags)) { 197351c1a580SMerav Sicron DP(BNX2X_MSG_SP, "RAMROD_DRV_CLR_ONLY requested: clearing a pending bit.\n"); 1974adfc5217SJeff Kirsher raw->clear_pending(raw); 1975adfc5217SJeff Kirsher } 1976adfc5217SJeff Kirsher 1977adfc5217SJeff Kirsher /* Execute commands if required */ 1978adfc5217SJeff Kirsher if (cont || test_bit(RAMROD_EXEC, ramrod_flags) || 1979adfc5217SJeff Kirsher test_bit(RAMROD_COMP_WAIT, ramrod_flags)) { 19808b09be5fSYuval Mintz rc = __bnx2x_vlan_mac_execute_step(bp, p->vlan_mac_obj, 19818b09be5fSYuval Mintz &p->ramrod_flags); 1982adfc5217SJeff Kirsher if (rc < 0) 1983adfc5217SJeff Kirsher return rc; 1984adfc5217SJeff Kirsher } 1985adfc5217SJeff Kirsher 198616a5fd92SYuval Mintz /* RAMROD_COMP_WAIT is a superset of RAMROD_EXEC. If it was set 1987adfc5217SJeff Kirsher * then user want to wait until the last command is done. 1988adfc5217SJeff Kirsher */ 1989adfc5217SJeff Kirsher if (test_bit(RAMROD_COMP_WAIT, &p->ramrod_flags)) { 199016a5fd92SYuval Mintz /* Wait maximum for the current exe_queue length iterations plus 1991adfc5217SJeff Kirsher * one (for the current pending command). 1992adfc5217SJeff Kirsher */ 1993adfc5217SJeff Kirsher int max_iterations = bnx2x_exe_queue_length(&o->exe_queue) + 1; 1994adfc5217SJeff Kirsher 1995adfc5217SJeff Kirsher while (!bnx2x_exe_queue_empty(&o->exe_queue) && 1996adfc5217SJeff Kirsher max_iterations--) { 1997adfc5217SJeff Kirsher 1998adfc5217SJeff Kirsher /* Wait for the current command to complete */ 1999adfc5217SJeff Kirsher rc = raw->wait_comp(bp, raw); 2000adfc5217SJeff Kirsher if (rc) 2001adfc5217SJeff Kirsher return rc; 2002adfc5217SJeff Kirsher 2003adfc5217SJeff Kirsher /* Make a next step */ 20048b09be5fSYuval Mintz rc = __bnx2x_vlan_mac_execute_step(bp, 20058b09be5fSYuval Mintz p->vlan_mac_obj, 20068b09be5fSYuval Mintz &p->ramrod_flags); 2007adfc5217SJeff Kirsher if (rc < 0) 2008adfc5217SJeff Kirsher return rc; 2009adfc5217SJeff Kirsher } 2010adfc5217SJeff Kirsher 2011adfc5217SJeff Kirsher return 0; 2012adfc5217SJeff Kirsher } 2013adfc5217SJeff Kirsher 2014adfc5217SJeff Kirsher return rc; 2015adfc5217SJeff Kirsher } 2016adfc5217SJeff Kirsher 2017adfc5217SJeff Kirsher /** 2018adfc5217SJeff Kirsher * bnx2x_vlan_mac_del_all - delete elements with given vlan_mac_flags spec 2019adfc5217SJeff Kirsher * 2020adfc5217SJeff Kirsher * @bp: device handle 2021adfc5217SJeff Kirsher * @o: 2022adfc5217SJeff Kirsher * @vlan_mac_flags: 2023adfc5217SJeff Kirsher * @ramrod_flags: execution flags to be used for this deletion 2024adfc5217SJeff Kirsher * 2025adfc5217SJeff Kirsher * if the last operation has completed successfully and there are no 2026adfc5217SJeff Kirsher * more elements left, positive value if the last operation has completed 2027adfc5217SJeff Kirsher * successfully and there are more previously configured elements, negative 2028adfc5217SJeff Kirsher * value is current operation has failed. 2029adfc5217SJeff Kirsher */ 2030adfc5217SJeff Kirsher static int bnx2x_vlan_mac_del_all(struct bnx2x *bp, 2031adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *o, 2032adfc5217SJeff Kirsher unsigned long *vlan_mac_flags, 2033adfc5217SJeff Kirsher unsigned long *ramrod_flags) 2034adfc5217SJeff Kirsher { 2035adfc5217SJeff Kirsher struct bnx2x_vlan_mac_registry_elem *pos = NULL; 2036adfc5217SJeff Kirsher struct bnx2x_vlan_mac_ramrod_params p; 2037adfc5217SJeff Kirsher struct bnx2x_exe_queue_obj *exeq = &o->exe_queue; 2038adfc5217SJeff Kirsher struct bnx2x_exeq_elem *exeq_pos, *exeq_pos_n; 20398b09be5fSYuval Mintz int read_lock; 20408b09be5fSYuval Mintz int rc = 0; 2041adfc5217SJeff Kirsher 2042adfc5217SJeff Kirsher /* Clear pending commands first */ 2043adfc5217SJeff Kirsher 2044adfc5217SJeff Kirsher spin_lock_bh(&exeq->lock); 2045adfc5217SJeff Kirsher 2046adfc5217SJeff Kirsher list_for_each_entry_safe(exeq_pos, exeq_pos_n, &exeq->exe_queue, link) { 2047adfc5217SJeff Kirsher if (exeq_pos->cmd_data.vlan_mac.vlan_mac_flags == 2048460a25cdSYuval Mintz *vlan_mac_flags) { 2049460a25cdSYuval Mintz rc = exeq->remove(bp, exeq->owner, exeq_pos); 2050460a25cdSYuval Mintz if (rc) { 2051460a25cdSYuval Mintz BNX2X_ERR("Failed to remove command\n"); 2052a44acd55SDan Carpenter spin_unlock_bh(&exeq->lock); 2053460a25cdSYuval Mintz return rc; 2054460a25cdSYuval Mintz } 2055adfc5217SJeff Kirsher list_del(&exeq_pos->link); 205607ef7becSYuval Mintz bnx2x_exe_queue_free_elem(bp, exeq_pos); 2057adfc5217SJeff Kirsher } 2058460a25cdSYuval Mintz } 2059adfc5217SJeff Kirsher 2060adfc5217SJeff Kirsher spin_unlock_bh(&exeq->lock); 2061adfc5217SJeff Kirsher 2062adfc5217SJeff Kirsher /* Prepare a command request */ 2063adfc5217SJeff Kirsher memset(&p, 0, sizeof(p)); 2064adfc5217SJeff Kirsher p.vlan_mac_obj = o; 2065adfc5217SJeff Kirsher p.ramrod_flags = *ramrod_flags; 2066adfc5217SJeff Kirsher p.user_req.cmd = BNX2X_VLAN_MAC_DEL; 2067adfc5217SJeff Kirsher 206816a5fd92SYuval Mintz /* Add all but the last VLAN-MAC to the execution queue without actually 2069adfc5217SJeff Kirsher * execution anything. 2070adfc5217SJeff Kirsher */ 2071adfc5217SJeff Kirsher __clear_bit(RAMROD_COMP_WAIT, &p.ramrod_flags); 2072adfc5217SJeff Kirsher __clear_bit(RAMROD_EXEC, &p.ramrod_flags); 2073adfc5217SJeff Kirsher __clear_bit(RAMROD_CONT, &p.ramrod_flags); 2074adfc5217SJeff Kirsher 20758b09be5fSYuval Mintz DP(BNX2X_MSG_SP, "vlan_mac_del_all -- taking vlan_mac_lock (reader)\n"); 20768b09be5fSYuval Mintz read_lock = bnx2x_vlan_mac_h_read_lock(bp, o); 20778b09be5fSYuval Mintz if (read_lock != 0) 20788b09be5fSYuval Mintz return read_lock; 20798b09be5fSYuval Mintz 2080adfc5217SJeff Kirsher list_for_each_entry(pos, &o->head, link) { 2081adfc5217SJeff Kirsher if (pos->vlan_mac_flags == *vlan_mac_flags) { 2082adfc5217SJeff Kirsher p.user_req.vlan_mac_flags = pos->vlan_mac_flags; 2083adfc5217SJeff Kirsher memcpy(&p.user_req.u, &pos->u, sizeof(pos->u)); 2084adfc5217SJeff Kirsher rc = bnx2x_config_vlan_mac(bp, &p); 2085adfc5217SJeff Kirsher if (rc < 0) { 2086adfc5217SJeff Kirsher BNX2X_ERR("Failed to add a new DEL command\n"); 20878b09be5fSYuval Mintz bnx2x_vlan_mac_h_read_unlock(bp, o); 2088adfc5217SJeff Kirsher return rc; 2089adfc5217SJeff Kirsher } 2090adfc5217SJeff Kirsher } 2091adfc5217SJeff Kirsher } 2092adfc5217SJeff Kirsher 20938b09be5fSYuval Mintz DP(BNX2X_MSG_SP, "vlan_mac_del_all -- releasing vlan_mac_lock (reader)\n"); 20948b09be5fSYuval Mintz bnx2x_vlan_mac_h_read_unlock(bp, o); 20958b09be5fSYuval Mintz 2096adfc5217SJeff Kirsher p.ramrod_flags = *ramrod_flags; 2097adfc5217SJeff Kirsher __set_bit(RAMROD_CONT, &p.ramrod_flags); 2098adfc5217SJeff Kirsher 2099adfc5217SJeff Kirsher return bnx2x_config_vlan_mac(bp, &p); 2100adfc5217SJeff Kirsher } 2101adfc5217SJeff Kirsher 2102adfc5217SJeff Kirsher static inline void bnx2x_init_raw_obj(struct bnx2x_raw_obj *raw, u8 cl_id, 2103adfc5217SJeff Kirsher u32 cid, u8 func_id, void *rdata, dma_addr_t rdata_mapping, int state, 2104adfc5217SJeff Kirsher unsigned long *pstate, bnx2x_obj_type type) 2105adfc5217SJeff Kirsher { 2106adfc5217SJeff Kirsher raw->func_id = func_id; 2107adfc5217SJeff Kirsher raw->cid = cid; 2108adfc5217SJeff Kirsher raw->cl_id = cl_id; 2109adfc5217SJeff Kirsher raw->rdata = rdata; 2110adfc5217SJeff Kirsher raw->rdata_mapping = rdata_mapping; 2111adfc5217SJeff Kirsher raw->state = state; 2112adfc5217SJeff Kirsher raw->pstate = pstate; 2113adfc5217SJeff Kirsher raw->obj_type = type; 2114adfc5217SJeff Kirsher raw->check_pending = bnx2x_raw_check_pending; 2115adfc5217SJeff Kirsher raw->clear_pending = bnx2x_raw_clear_pending; 2116adfc5217SJeff Kirsher raw->set_pending = bnx2x_raw_set_pending; 2117adfc5217SJeff Kirsher raw->wait_comp = bnx2x_raw_wait; 2118adfc5217SJeff Kirsher } 2119adfc5217SJeff Kirsher 2120adfc5217SJeff Kirsher static inline void bnx2x_init_vlan_mac_common(struct bnx2x_vlan_mac_obj *o, 2121adfc5217SJeff Kirsher u8 cl_id, u32 cid, u8 func_id, void *rdata, dma_addr_t rdata_mapping, 2122adfc5217SJeff Kirsher int state, unsigned long *pstate, bnx2x_obj_type type, 2123adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *macs_pool, 2124adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *vlans_pool) 2125adfc5217SJeff Kirsher { 2126adfc5217SJeff Kirsher INIT_LIST_HEAD(&o->head); 21278b09be5fSYuval Mintz o->head_reader = 0; 21288b09be5fSYuval Mintz o->head_exe_request = false; 21298b09be5fSYuval Mintz o->saved_ramrod_flags = 0; 2130adfc5217SJeff Kirsher 2131adfc5217SJeff Kirsher o->macs_pool = macs_pool; 2132adfc5217SJeff Kirsher o->vlans_pool = vlans_pool; 2133adfc5217SJeff Kirsher 2134adfc5217SJeff Kirsher o->delete_all = bnx2x_vlan_mac_del_all; 2135adfc5217SJeff Kirsher o->restore = bnx2x_vlan_mac_restore; 2136adfc5217SJeff Kirsher o->complete = bnx2x_complete_vlan_mac; 2137adfc5217SJeff Kirsher o->wait = bnx2x_wait_vlan_mac; 2138adfc5217SJeff Kirsher 2139adfc5217SJeff Kirsher bnx2x_init_raw_obj(&o->raw, cl_id, cid, func_id, rdata, rdata_mapping, 2140adfc5217SJeff Kirsher state, pstate, type); 2141adfc5217SJeff Kirsher } 2142adfc5217SJeff Kirsher 2143adfc5217SJeff Kirsher void bnx2x_init_mac_obj(struct bnx2x *bp, 2144adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *mac_obj, 2145adfc5217SJeff Kirsher u8 cl_id, u32 cid, u8 func_id, void *rdata, 2146adfc5217SJeff Kirsher dma_addr_t rdata_mapping, int state, 2147adfc5217SJeff Kirsher unsigned long *pstate, bnx2x_obj_type type, 2148adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *macs_pool) 2149adfc5217SJeff Kirsher { 2150adfc5217SJeff Kirsher union bnx2x_qable_obj *qable_obj = (union bnx2x_qable_obj *)mac_obj; 2151adfc5217SJeff Kirsher 2152adfc5217SJeff Kirsher bnx2x_init_vlan_mac_common(mac_obj, cl_id, cid, func_id, rdata, 2153adfc5217SJeff Kirsher rdata_mapping, state, pstate, type, 2154adfc5217SJeff Kirsher macs_pool, NULL); 2155adfc5217SJeff Kirsher 2156adfc5217SJeff Kirsher /* CAM credit pool handling */ 2157adfc5217SJeff Kirsher mac_obj->get_credit = bnx2x_get_credit_mac; 2158adfc5217SJeff Kirsher mac_obj->put_credit = bnx2x_put_credit_mac; 2159adfc5217SJeff Kirsher mac_obj->get_cam_offset = bnx2x_get_cam_offset_mac; 2160adfc5217SJeff Kirsher mac_obj->put_cam_offset = bnx2x_put_cam_offset_mac; 2161adfc5217SJeff Kirsher 2162adfc5217SJeff Kirsher if (CHIP_IS_E1x(bp)) { 2163adfc5217SJeff Kirsher mac_obj->set_one_rule = bnx2x_set_one_mac_e1x; 2164adfc5217SJeff Kirsher mac_obj->check_del = bnx2x_check_mac_del; 2165adfc5217SJeff Kirsher mac_obj->check_add = bnx2x_check_mac_add; 2166adfc5217SJeff Kirsher mac_obj->check_move = bnx2x_check_move_always_err; 2167adfc5217SJeff Kirsher mac_obj->ramrod_cmd = RAMROD_CMD_ID_ETH_SET_MAC; 2168adfc5217SJeff Kirsher 2169adfc5217SJeff Kirsher /* Exe Queue */ 2170adfc5217SJeff Kirsher bnx2x_exe_queue_init(bp, 2171adfc5217SJeff Kirsher &mac_obj->exe_queue, 1, qable_obj, 2172adfc5217SJeff Kirsher bnx2x_validate_vlan_mac, 2173460a25cdSYuval Mintz bnx2x_remove_vlan_mac, 2174adfc5217SJeff Kirsher bnx2x_optimize_vlan_mac, 2175adfc5217SJeff Kirsher bnx2x_execute_vlan_mac, 2176adfc5217SJeff Kirsher bnx2x_exeq_get_mac); 2177adfc5217SJeff Kirsher } else { 2178adfc5217SJeff Kirsher mac_obj->set_one_rule = bnx2x_set_one_mac_e2; 2179adfc5217SJeff Kirsher mac_obj->check_del = bnx2x_check_mac_del; 2180adfc5217SJeff Kirsher mac_obj->check_add = bnx2x_check_mac_add; 2181adfc5217SJeff Kirsher mac_obj->check_move = bnx2x_check_move; 2182adfc5217SJeff Kirsher mac_obj->ramrod_cmd = 2183adfc5217SJeff Kirsher RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES; 2184ed5162a0SAriel Elior mac_obj->get_n_elements = bnx2x_get_n_elements; 2185adfc5217SJeff Kirsher 2186adfc5217SJeff Kirsher /* Exe Queue */ 2187adfc5217SJeff Kirsher bnx2x_exe_queue_init(bp, 2188adfc5217SJeff Kirsher &mac_obj->exe_queue, CLASSIFY_RULES_COUNT, 2189adfc5217SJeff Kirsher qable_obj, bnx2x_validate_vlan_mac, 2190460a25cdSYuval Mintz bnx2x_remove_vlan_mac, 2191adfc5217SJeff Kirsher bnx2x_optimize_vlan_mac, 2192adfc5217SJeff Kirsher bnx2x_execute_vlan_mac, 2193adfc5217SJeff Kirsher bnx2x_exeq_get_mac); 2194adfc5217SJeff Kirsher } 2195adfc5217SJeff Kirsher } 2196adfc5217SJeff Kirsher 2197adfc5217SJeff Kirsher void bnx2x_init_vlan_obj(struct bnx2x *bp, 2198adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *vlan_obj, 2199adfc5217SJeff Kirsher u8 cl_id, u32 cid, u8 func_id, void *rdata, 2200adfc5217SJeff Kirsher dma_addr_t rdata_mapping, int state, 2201adfc5217SJeff Kirsher unsigned long *pstate, bnx2x_obj_type type, 2202adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *vlans_pool) 2203adfc5217SJeff Kirsher { 2204adfc5217SJeff Kirsher union bnx2x_qable_obj *qable_obj = (union bnx2x_qable_obj *)vlan_obj; 2205adfc5217SJeff Kirsher 2206adfc5217SJeff Kirsher bnx2x_init_vlan_mac_common(vlan_obj, cl_id, cid, func_id, rdata, 2207adfc5217SJeff Kirsher rdata_mapping, state, pstate, type, NULL, 2208adfc5217SJeff Kirsher vlans_pool); 2209adfc5217SJeff Kirsher 2210adfc5217SJeff Kirsher vlan_obj->get_credit = bnx2x_get_credit_vlan; 2211adfc5217SJeff Kirsher vlan_obj->put_credit = bnx2x_put_credit_vlan; 2212adfc5217SJeff Kirsher vlan_obj->get_cam_offset = bnx2x_get_cam_offset_vlan; 2213adfc5217SJeff Kirsher vlan_obj->put_cam_offset = bnx2x_put_cam_offset_vlan; 2214adfc5217SJeff Kirsher 2215adfc5217SJeff Kirsher if (CHIP_IS_E1x(bp)) { 2216adfc5217SJeff Kirsher BNX2X_ERR("Do not support chips others than E2 and newer\n"); 2217adfc5217SJeff Kirsher BUG(); 2218adfc5217SJeff Kirsher } else { 2219adfc5217SJeff Kirsher vlan_obj->set_one_rule = bnx2x_set_one_vlan_e2; 2220adfc5217SJeff Kirsher vlan_obj->check_del = bnx2x_check_vlan_del; 2221adfc5217SJeff Kirsher vlan_obj->check_add = bnx2x_check_vlan_add; 2222adfc5217SJeff Kirsher vlan_obj->check_move = bnx2x_check_move; 2223adfc5217SJeff Kirsher vlan_obj->ramrod_cmd = 2224adfc5217SJeff Kirsher RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES; 22253ec9f9caSAriel Elior vlan_obj->get_n_elements = bnx2x_get_n_elements; 2226adfc5217SJeff Kirsher 2227adfc5217SJeff Kirsher /* Exe Queue */ 2228adfc5217SJeff Kirsher bnx2x_exe_queue_init(bp, 2229adfc5217SJeff Kirsher &vlan_obj->exe_queue, CLASSIFY_RULES_COUNT, 2230adfc5217SJeff Kirsher qable_obj, bnx2x_validate_vlan_mac, 2231460a25cdSYuval Mintz bnx2x_remove_vlan_mac, 2232adfc5217SJeff Kirsher bnx2x_optimize_vlan_mac, 2233adfc5217SJeff Kirsher bnx2x_execute_vlan_mac, 2234adfc5217SJeff Kirsher bnx2x_exeq_get_vlan); 2235adfc5217SJeff Kirsher } 2236adfc5217SJeff Kirsher } 2237adfc5217SJeff Kirsher 2238adfc5217SJeff Kirsher void bnx2x_init_vlan_mac_obj(struct bnx2x *bp, 2239adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *vlan_mac_obj, 2240adfc5217SJeff Kirsher u8 cl_id, u32 cid, u8 func_id, void *rdata, 2241adfc5217SJeff Kirsher dma_addr_t rdata_mapping, int state, 2242adfc5217SJeff Kirsher unsigned long *pstate, bnx2x_obj_type type, 2243adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *macs_pool, 2244adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *vlans_pool) 2245adfc5217SJeff Kirsher { 2246adfc5217SJeff Kirsher union bnx2x_qable_obj *qable_obj = 2247adfc5217SJeff Kirsher (union bnx2x_qable_obj *)vlan_mac_obj; 2248adfc5217SJeff Kirsher 2249adfc5217SJeff Kirsher bnx2x_init_vlan_mac_common(vlan_mac_obj, cl_id, cid, func_id, rdata, 2250adfc5217SJeff Kirsher rdata_mapping, state, pstate, type, 2251adfc5217SJeff Kirsher macs_pool, vlans_pool); 2252adfc5217SJeff Kirsher 2253adfc5217SJeff Kirsher /* CAM pool handling */ 2254adfc5217SJeff Kirsher vlan_mac_obj->get_credit = bnx2x_get_credit_vlan_mac; 2255adfc5217SJeff Kirsher vlan_mac_obj->put_credit = bnx2x_put_credit_vlan_mac; 225616a5fd92SYuval Mintz /* CAM offset is relevant for 57710 and 57711 chips only which have a 2257adfc5217SJeff Kirsher * single CAM for both MACs and VLAN-MAC pairs. So the offset 2258adfc5217SJeff Kirsher * will be taken from MACs' pool object only. 2259adfc5217SJeff Kirsher */ 2260adfc5217SJeff Kirsher vlan_mac_obj->get_cam_offset = bnx2x_get_cam_offset_mac; 2261adfc5217SJeff Kirsher vlan_mac_obj->put_cam_offset = bnx2x_put_cam_offset_mac; 2262adfc5217SJeff Kirsher 2263adfc5217SJeff Kirsher if (CHIP_IS_E1(bp)) { 2264adfc5217SJeff Kirsher BNX2X_ERR("Do not support chips others than E2\n"); 2265adfc5217SJeff Kirsher BUG(); 2266adfc5217SJeff Kirsher } else if (CHIP_IS_E1H(bp)) { 2267adfc5217SJeff Kirsher vlan_mac_obj->set_one_rule = bnx2x_set_one_vlan_mac_e1h; 2268adfc5217SJeff Kirsher vlan_mac_obj->check_del = bnx2x_check_vlan_mac_del; 2269adfc5217SJeff Kirsher vlan_mac_obj->check_add = bnx2x_check_vlan_mac_add; 2270adfc5217SJeff Kirsher vlan_mac_obj->check_move = bnx2x_check_move_always_err; 2271adfc5217SJeff Kirsher vlan_mac_obj->ramrod_cmd = RAMROD_CMD_ID_ETH_SET_MAC; 2272adfc5217SJeff Kirsher 2273adfc5217SJeff Kirsher /* Exe Queue */ 2274adfc5217SJeff Kirsher bnx2x_exe_queue_init(bp, 2275adfc5217SJeff Kirsher &vlan_mac_obj->exe_queue, 1, qable_obj, 2276adfc5217SJeff Kirsher bnx2x_validate_vlan_mac, 2277460a25cdSYuval Mintz bnx2x_remove_vlan_mac, 2278adfc5217SJeff Kirsher bnx2x_optimize_vlan_mac, 2279adfc5217SJeff Kirsher bnx2x_execute_vlan_mac, 2280adfc5217SJeff Kirsher bnx2x_exeq_get_vlan_mac); 2281adfc5217SJeff Kirsher } else { 2282adfc5217SJeff Kirsher vlan_mac_obj->set_one_rule = bnx2x_set_one_vlan_mac_e2; 2283adfc5217SJeff Kirsher vlan_mac_obj->check_del = bnx2x_check_vlan_mac_del; 2284adfc5217SJeff Kirsher vlan_mac_obj->check_add = bnx2x_check_vlan_mac_add; 2285adfc5217SJeff Kirsher vlan_mac_obj->check_move = bnx2x_check_move; 2286adfc5217SJeff Kirsher vlan_mac_obj->ramrod_cmd = 2287adfc5217SJeff Kirsher RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES; 2288adfc5217SJeff Kirsher 2289adfc5217SJeff Kirsher /* Exe Queue */ 2290adfc5217SJeff Kirsher bnx2x_exe_queue_init(bp, 2291adfc5217SJeff Kirsher &vlan_mac_obj->exe_queue, 2292adfc5217SJeff Kirsher CLASSIFY_RULES_COUNT, 2293adfc5217SJeff Kirsher qable_obj, bnx2x_validate_vlan_mac, 2294460a25cdSYuval Mintz bnx2x_remove_vlan_mac, 2295adfc5217SJeff Kirsher bnx2x_optimize_vlan_mac, 2296adfc5217SJeff Kirsher bnx2x_execute_vlan_mac, 2297adfc5217SJeff Kirsher bnx2x_exeq_get_vlan_mac); 2298adfc5217SJeff Kirsher } 2299adfc5217SJeff Kirsher } 2300adfc5217SJeff Kirsher 2301adfc5217SJeff Kirsher /* RX_MODE verbs: DROP_ALL/ACCEPT_ALL/ACCEPT_ALL_MULTI/ACCEPT_ALL_VLAN/NORMAL */ 2302adfc5217SJeff Kirsher static inline void __storm_memset_mac_filters(struct bnx2x *bp, 2303adfc5217SJeff Kirsher struct tstorm_eth_mac_filter_config *mac_filters, 2304adfc5217SJeff Kirsher u16 pf_id) 2305adfc5217SJeff Kirsher { 2306adfc5217SJeff Kirsher size_t size = sizeof(struct tstorm_eth_mac_filter_config); 2307adfc5217SJeff Kirsher 2308adfc5217SJeff Kirsher u32 addr = BAR_TSTRORM_INTMEM + 2309adfc5217SJeff Kirsher TSTORM_MAC_FILTER_CONFIG_OFFSET(pf_id); 2310adfc5217SJeff Kirsher 2311adfc5217SJeff Kirsher __storm_memset_struct(bp, addr, size, (u32 *)mac_filters); 2312adfc5217SJeff Kirsher } 2313adfc5217SJeff Kirsher 2314adfc5217SJeff Kirsher static int bnx2x_set_rx_mode_e1x(struct bnx2x *bp, 2315adfc5217SJeff Kirsher struct bnx2x_rx_mode_ramrod_params *p) 2316adfc5217SJeff Kirsher { 2317adfc5217SJeff Kirsher /* update the bp MAC filter structure */ 2318adfc5217SJeff Kirsher u32 mask = (1 << p->cl_id); 2319adfc5217SJeff Kirsher 2320adfc5217SJeff Kirsher struct tstorm_eth_mac_filter_config *mac_filters = 2321adfc5217SJeff Kirsher (struct tstorm_eth_mac_filter_config *)p->rdata; 2322adfc5217SJeff Kirsher 232316a5fd92SYuval Mintz /* initial setting is drop-all */ 2324adfc5217SJeff Kirsher u8 drop_all_ucast = 1, drop_all_mcast = 1; 2325adfc5217SJeff Kirsher u8 accp_all_ucast = 0, accp_all_bcast = 0, accp_all_mcast = 0; 2326adfc5217SJeff Kirsher u8 unmatched_unicast = 0; 2327adfc5217SJeff Kirsher 232816a5fd92SYuval Mintz /* In e1x there we only take into account rx accept flag since tx switching 2329adfc5217SJeff Kirsher * isn't enabled. */ 2330adfc5217SJeff Kirsher if (test_bit(BNX2X_ACCEPT_UNICAST, &p->rx_accept_flags)) 2331adfc5217SJeff Kirsher /* accept matched ucast */ 2332adfc5217SJeff Kirsher drop_all_ucast = 0; 2333adfc5217SJeff Kirsher 2334adfc5217SJeff Kirsher if (test_bit(BNX2X_ACCEPT_MULTICAST, &p->rx_accept_flags)) 2335adfc5217SJeff Kirsher /* accept matched mcast */ 2336adfc5217SJeff Kirsher drop_all_mcast = 0; 2337adfc5217SJeff Kirsher 2338adfc5217SJeff Kirsher if (test_bit(BNX2X_ACCEPT_ALL_UNICAST, &p->rx_accept_flags)) { 2339adfc5217SJeff Kirsher /* accept all mcast */ 2340adfc5217SJeff Kirsher drop_all_ucast = 0; 2341adfc5217SJeff Kirsher accp_all_ucast = 1; 2342adfc5217SJeff Kirsher } 2343adfc5217SJeff Kirsher if (test_bit(BNX2X_ACCEPT_ALL_MULTICAST, &p->rx_accept_flags)) { 2344adfc5217SJeff Kirsher /* accept all mcast */ 2345adfc5217SJeff Kirsher drop_all_mcast = 0; 2346adfc5217SJeff Kirsher accp_all_mcast = 1; 2347adfc5217SJeff Kirsher } 2348adfc5217SJeff Kirsher if (test_bit(BNX2X_ACCEPT_BROADCAST, &p->rx_accept_flags)) 2349adfc5217SJeff Kirsher /* accept (all) bcast */ 2350adfc5217SJeff Kirsher accp_all_bcast = 1; 2351adfc5217SJeff Kirsher if (test_bit(BNX2X_ACCEPT_UNMATCHED, &p->rx_accept_flags)) 2352adfc5217SJeff Kirsher /* accept unmatched unicasts */ 2353adfc5217SJeff Kirsher unmatched_unicast = 1; 2354adfc5217SJeff Kirsher 2355adfc5217SJeff Kirsher mac_filters->ucast_drop_all = drop_all_ucast ? 2356adfc5217SJeff Kirsher mac_filters->ucast_drop_all | mask : 2357adfc5217SJeff Kirsher mac_filters->ucast_drop_all & ~mask; 2358adfc5217SJeff Kirsher 2359adfc5217SJeff Kirsher mac_filters->mcast_drop_all = drop_all_mcast ? 2360adfc5217SJeff Kirsher mac_filters->mcast_drop_all | mask : 2361adfc5217SJeff Kirsher mac_filters->mcast_drop_all & ~mask; 2362adfc5217SJeff Kirsher 2363adfc5217SJeff Kirsher mac_filters->ucast_accept_all = accp_all_ucast ? 2364adfc5217SJeff Kirsher mac_filters->ucast_accept_all | mask : 2365adfc5217SJeff Kirsher mac_filters->ucast_accept_all & ~mask; 2366adfc5217SJeff Kirsher 2367adfc5217SJeff Kirsher mac_filters->mcast_accept_all = accp_all_mcast ? 2368adfc5217SJeff Kirsher mac_filters->mcast_accept_all | mask : 2369adfc5217SJeff Kirsher mac_filters->mcast_accept_all & ~mask; 2370adfc5217SJeff Kirsher 2371adfc5217SJeff Kirsher mac_filters->bcast_accept_all = accp_all_bcast ? 2372adfc5217SJeff Kirsher mac_filters->bcast_accept_all | mask : 2373adfc5217SJeff Kirsher mac_filters->bcast_accept_all & ~mask; 2374adfc5217SJeff Kirsher 2375adfc5217SJeff Kirsher mac_filters->unmatched_unicast = unmatched_unicast ? 2376adfc5217SJeff Kirsher mac_filters->unmatched_unicast | mask : 2377adfc5217SJeff Kirsher mac_filters->unmatched_unicast & ~mask; 2378adfc5217SJeff Kirsher 2379adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "drop_ucast 0x%x\ndrop_mcast 0x%x\n accp_ucast 0x%x\n" 2380adfc5217SJeff Kirsher "accp_mcast 0x%x\naccp_bcast 0x%x\n", 238151c1a580SMerav Sicron mac_filters->ucast_drop_all, mac_filters->mcast_drop_all, 238251c1a580SMerav Sicron mac_filters->ucast_accept_all, mac_filters->mcast_accept_all, 2383adfc5217SJeff Kirsher mac_filters->bcast_accept_all); 2384adfc5217SJeff Kirsher 2385adfc5217SJeff Kirsher /* write the MAC filter structure*/ 2386adfc5217SJeff Kirsher __storm_memset_mac_filters(bp, mac_filters, p->func_id); 2387adfc5217SJeff Kirsher 2388adfc5217SJeff Kirsher /* The operation is completed */ 2389adfc5217SJeff Kirsher clear_bit(p->state, p->pstate); 2390adfc5217SJeff Kirsher smp_mb__after_clear_bit(); 2391adfc5217SJeff Kirsher 2392adfc5217SJeff Kirsher return 0; 2393adfc5217SJeff Kirsher } 2394adfc5217SJeff Kirsher 2395adfc5217SJeff Kirsher /* Setup ramrod data */ 2396adfc5217SJeff Kirsher static inline void bnx2x_rx_mode_set_rdata_hdr_e2(u32 cid, 2397adfc5217SJeff Kirsher struct eth_classify_header *hdr, 2398adfc5217SJeff Kirsher u8 rule_cnt) 2399adfc5217SJeff Kirsher { 240086564c3fSYuval Mintz hdr->echo = cpu_to_le32(cid); 2401adfc5217SJeff Kirsher hdr->rule_cnt = rule_cnt; 2402adfc5217SJeff Kirsher } 2403adfc5217SJeff Kirsher 2404adfc5217SJeff Kirsher static inline void bnx2x_rx_mode_set_cmd_state_e2(struct bnx2x *bp, 2405924d75abSYuval Mintz unsigned long *accept_flags, 2406adfc5217SJeff Kirsher struct eth_filter_rules_cmd *cmd, 2407adfc5217SJeff Kirsher bool clear_accept_all) 2408adfc5217SJeff Kirsher { 2409adfc5217SJeff Kirsher u16 state; 2410adfc5217SJeff Kirsher 2411adfc5217SJeff Kirsher /* start with 'drop-all' */ 2412adfc5217SJeff Kirsher state = ETH_FILTER_RULES_CMD_UCAST_DROP_ALL | 2413adfc5217SJeff Kirsher ETH_FILTER_RULES_CMD_MCAST_DROP_ALL; 2414adfc5217SJeff Kirsher 2415924d75abSYuval Mintz if (test_bit(BNX2X_ACCEPT_UNICAST, accept_flags)) 2416adfc5217SJeff Kirsher state &= ~ETH_FILTER_RULES_CMD_UCAST_DROP_ALL; 2417adfc5217SJeff Kirsher 2418924d75abSYuval Mintz if (test_bit(BNX2X_ACCEPT_MULTICAST, accept_flags)) 2419adfc5217SJeff Kirsher state &= ~ETH_FILTER_RULES_CMD_MCAST_DROP_ALL; 2420adfc5217SJeff Kirsher 2421924d75abSYuval Mintz if (test_bit(BNX2X_ACCEPT_ALL_UNICAST, accept_flags)) { 2422adfc5217SJeff Kirsher state &= ~ETH_FILTER_RULES_CMD_UCAST_DROP_ALL; 2423adfc5217SJeff Kirsher state |= ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL; 2424adfc5217SJeff Kirsher } 2425adfc5217SJeff Kirsher 2426924d75abSYuval Mintz if (test_bit(BNX2X_ACCEPT_ALL_MULTICAST, accept_flags)) { 2427adfc5217SJeff Kirsher state |= ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL; 2428adfc5217SJeff Kirsher state &= ~ETH_FILTER_RULES_CMD_MCAST_DROP_ALL; 2429adfc5217SJeff Kirsher } 2430924d75abSYuval Mintz 2431924d75abSYuval Mintz if (test_bit(BNX2X_ACCEPT_BROADCAST, accept_flags)) 2432adfc5217SJeff Kirsher state |= ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL; 2433adfc5217SJeff Kirsher 2434924d75abSYuval Mintz if (test_bit(BNX2X_ACCEPT_UNMATCHED, accept_flags)) { 2435adfc5217SJeff Kirsher state &= ~ETH_FILTER_RULES_CMD_UCAST_DROP_ALL; 2436adfc5217SJeff Kirsher state |= ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED; 2437adfc5217SJeff Kirsher } 2438924d75abSYuval Mintz 2439924d75abSYuval Mintz if (test_bit(BNX2X_ACCEPT_ANY_VLAN, accept_flags)) 2440adfc5217SJeff Kirsher state |= ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN; 2441adfc5217SJeff Kirsher 2442adfc5217SJeff Kirsher /* Clear ACCEPT_ALL_XXX flags for FCoE L2 Queue */ 2443adfc5217SJeff Kirsher if (clear_accept_all) { 2444adfc5217SJeff Kirsher state &= ~ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL; 2445adfc5217SJeff Kirsher state &= ~ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL; 2446adfc5217SJeff Kirsher state &= ~ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL; 2447adfc5217SJeff Kirsher state &= ~ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED; 2448adfc5217SJeff Kirsher } 2449adfc5217SJeff Kirsher 2450adfc5217SJeff Kirsher cmd->state = cpu_to_le16(state); 2451adfc5217SJeff Kirsher } 2452adfc5217SJeff Kirsher 2453adfc5217SJeff Kirsher static int bnx2x_set_rx_mode_e2(struct bnx2x *bp, 2454adfc5217SJeff Kirsher struct bnx2x_rx_mode_ramrod_params *p) 2455adfc5217SJeff Kirsher { 2456adfc5217SJeff Kirsher struct eth_filter_rules_ramrod_data *data = p->rdata; 2457adfc5217SJeff Kirsher int rc; 2458adfc5217SJeff Kirsher u8 rule_idx = 0; 2459adfc5217SJeff Kirsher 2460adfc5217SJeff Kirsher /* Reset the ramrod data buffer */ 2461adfc5217SJeff Kirsher memset(data, 0, sizeof(*data)); 2462adfc5217SJeff Kirsher 2463adfc5217SJeff Kirsher /* Setup ramrod data */ 2464adfc5217SJeff Kirsher 2465adfc5217SJeff Kirsher /* Tx (internal switching) */ 2466adfc5217SJeff Kirsher if (test_bit(RAMROD_TX, &p->ramrod_flags)) { 2467adfc5217SJeff Kirsher data->rules[rule_idx].client_id = p->cl_id; 2468adfc5217SJeff Kirsher data->rules[rule_idx].func_id = p->func_id; 2469adfc5217SJeff Kirsher 2470adfc5217SJeff Kirsher data->rules[rule_idx].cmd_general_data = 2471adfc5217SJeff Kirsher ETH_FILTER_RULES_CMD_TX_CMD; 2472adfc5217SJeff Kirsher 2473924d75abSYuval Mintz bnx2x_rx_mode_set_cmd_state_e2(bp, &p->tx_accept_flags, 2474924d75abSYuval Mintz &(data->rules[rule_idx++]), 2475924d75abSYuval Mintz false); 2476adfc5217SJeff Kirsher } 2477adfc5217SJeff Kirsher 2478adfc5217SJeff Kirsher /* Rx */ 2479adfc5217SJeff Kirsher if (test_bit(RAMROD_RX, &p->ramrod_flags)) { 2480adfc5217SJeff Kirsher data->rules[rule_idx].client_id = p->cl_id; 2481adfc5217SJeff Kirsher data->rules[rule_idx].func_id = p->func_id; 2482adfc5217SJeff Kirsher 2483adfc5217SJeff Kirsher data->rules[rule_idx].cmd_general_data = 2484adfc5217SJeff Kirsher ETH_FILTER_RULES_CMD_RX_CMD; 2485adfc5217SJeff Kirsher 2486924d75abSYuval Mintz bnx2x_rx_mode_set_cmd_state_e2(bp, &p->rx_accept_flags, 2487924d75abSYuval Mintz &(data->rules[rule_idx++]), 2488924d75abSYuval Mintz false); 2489adfc5217SJeff Kirsher } 2490adfc5217SJeff Kirsher 249116a5fd92SYuval Mintz /* If FCoE Queue configuration has been requested configure the Rx and 2492adfc5217SJeff Kirsher * internal switching modes for this queue in separate rules. 2493adfc5217SJeff Kirsher * 2494adfc5217SJeff Kirsher * FCoE queue shell never be set to ACCEPT_ALL packets of any sort: 2495adfc5217SJeff Kirsher * MCAST_ALL, UCAST_ALL, BCAST_ALL and UNMATCHED. 2496adfc5217SJeff Kirsher */ 2497adfc5217SJeff Kirsher if (test_bit(BNX2X_RX_MODE_FCOE_ETH, &p->rx_mode_flags)) { 2498adfc5217SJeff Kirsher /* Tx (internal switching) */ 2499adfc5217SJeff Kirsher if (test_bit(RAMROD_TX, &p->ramrod_flags)) { 2500adfc5217SJeff Kirsher data->rules[rule_idx].client_id = bnx2x_fcoe(bp, cl_id); 2501adfc5217SJeff Kirsher data->rules[rule_idx].func_id = p->func_id; 2502adfc5217SJeff Kirsher 2503adfc5217SJeff Kirsher data->rules[rule_idx].cmd_general_data = 2504adfc5217SJeff Kirsher ETH_FILTER_RULES_CMD_TX_CMD; 2505adfc5217SJeff Kirsher 2506924d75abSYuval Mintz bnx2x_rx_mode_set_cmd_state_e2(bp, &p->tx_accept_flags, 2507924d75abSYuval Mintz &(data->rules[rule_idx]), 2508adfc5217SJeff Kirsher true); 2509924d75abSYuval Mintz rule_idx++; 2510adfc5217SJeff Kirsher } 2511adfc5217SJeff Kirsher 2512adfc5217SJeff Kirsher /* Rx */ 2513adfc5217SJeff Kirsher if (test_bit(RAMROD_RX, &p->ramrod_flags)) { 2514adfc5217SJeff Kirsher data->rules[rule_idx].client_id = bnx2x_fcoe(bp, cl_id); 2515adfc5217SJeff Kirsher data->rules[rule_idx].func_id = p->func_id; 2516adfc5217SJeff Kirsher 2517adfc5217SJeff Kirsher data->rules[rule_idx].cmd_general_data = 2518adfc5217SJeff Kirsher ETH_FILTER_RULES_CMD_RX_CMD; 2519adfc5217SJeff Kirsher 2520924d75abSYuval Mintz bnx2x_rx_mode_set_cmd_state_e2(bp, &p->rx_accept_flags, 2521924d75abSYuval Mintz &(data->rules[rule_idx]), 2522adfc5217SJeff Kirsher true); 2523924d75abSYuval Mintz rule_idx++; 2524adfc5217SJeff Kirsher } 2525adfc5217SJeff Kirsher } 2526adfc5217SJeff Kirsher 252716a5fd92SYuval Mintz /* Set the ramrod header (most importantly - number of rules to 2528adfc5217SJeff Kirsher * configure). 2529adfc5217SJeff Kirsher */ 2530adfc5217SJeff Kirsher bnx2x_rx_mode_set_rdata_hdr_e2(p->cid, &data->header, rule_idx); 2531adfc5217SJeff Kirsher 253251c1a580SMerav Sicron DP(BNX2X_MSG_SP, "About to configure %d rules, rx_accept_flags 0x%lx, tx_accept_flags 0x%lx\n", 2533adfc5217SJeff Kirsher data->header.rule_cnt, p->rx_accept_flags, 2534adfc5217SJeff Kirsher p->tx_accept_flags); 2535adfc5217SJeff Kirsher 253616a5fd92SYuval Mintz /* No need for an explicit memory barrier here as long we would 2537adfc5217SJeff Kirsher * need to ensure the ordering of writing to the SPQ element 2538adfc5217SJeff Kirsher * and updating of the SPQ producer which involves a memory 2539adfc5217SJeff Kirsher * read and we will have to put a full memory barrier there 2540adfc5217SJeff Kirsher * (inside bnx2x_sp_post()). 2541adfc5217SJeff Kirsher */ 2542adfc5217SJeff Kirsher 2543adfc5217SJeff Kirsher /* Send a ramrod */ 2544adfc5217SJeff Kirsher rc = bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_FILTER_RULES, p->cid, 2545adfc5217SJeff Kirsher U64_HI(p->rdata_mapping), 2546adfc5217SJeff Kirsher U64_LO(p->rdata_mapping), 2547adfc5217SJeff Kirsher ETH_CONNECTION_TYPE); 2548adfc5217SJeff Kirsher if (rc) 2549adfc5217SJeff Kirsher return rc; 2550adfc5217SJeff Kirsher 2551adfc5217SJeff Kirsher /* Ramrod completion is pending */ 2552adfc5217SJeff Kirsher return 1; 2553adfc5217SJeff Kirsher } 2554adfc5217SJeff Kirsher 2555adfc5217SJeff Kirsher static int bnx2x_wait_rx_mode_comp_e2(struct bnx2x *bp, 2556adfc5217SJeff Kirsher struct bnx2x_rx_mode_ramrod_params *p) 2557adfc5217SJeff Kirsher { 2558adfc5217SJeff Kirsher return bnx2x_state_wait(bp, p->state, p->pstate); 2559adfc5217SJeff Kirsher } 2560adfc5217SJeff Kirsher 2561adfc5217SJeff Kirsher static int bnx2x_empty_rx_mode_wait(struct bnx2x *bp, 2562adfc5217SJeff Kirsher struct bnx2x_rx_mode_ramrod_params *p) 2563adfc5217SJeff Kirsher { 2564adfc5217SJeff Kirsher /* Do nothing */ 2565adfc5217SJeff Kirsher return 0; 2566adfc5217SJeff Kirsher } 2567adfc5217SJeff Kirsher 2568adfc5217SJeff Kirsher int bnx2x_config_rx_mode(struct bnx2x *bp, 2569adfc5217SJeff Kirsher struct bnx2x_rx_mode_ramrod_params *p) 2570adfc5217SJeff Kirsher { 2571adfc5217SJeff Kirsher int rc; 2572adfc5217SJeff Kirsher 2573adfc5217SJeff Kirsher /* Configure the new classification in the chip */ 2574adfc5217SJeff Kirsher rc = p->rx_mode_obj->config_rx_mode(bp, p); 2575adfc5217SJeff Kirsher if (rc < 0) 2576adfc5217SJeff Kirsher return rc; 2577adfc5217SJeff Kirsher 2578adfc5217SJeff Kirsher /* Wait for a ramrod completion if was requested */ 2579adfc5217SJeff Kirsher if (test_bit(RAMROD_COMP_WAIT, &p->ramrod_flags)) { 2580adfc5217SJeff Kirsher rc = p->rx_mode_obj->wait_comp(bp, p); 2581adfc5217SJeff Kirsher if (rc) 2582adfc5217SJeff Kirsher return rc; 2583adfc5217SJeff Kirsher } 2584adfc5217SJeff Kirsher 2585adfc5217SJeff Kirsher return rc; 2586adfc5217SJeff Kirsher } 2587adfc5217SJeff Kirsher 2588adfc5217SJeff Kirsher void bnx2x_init_rx_mode_obj(struct bnx2x *bp, 2589adfc5217SJeff Kirsher struct bnx2x_rx_mode_obj *o) 2590adfc5217SJeff Kirsher { 2591adfc5217SJeff Kirsher if (CHIP_IS_E1x(bp)) { 2592adfc5217SJeff Kirsher o->wait_comp = bnx2x_empty_rx_mode_wait; 2593adfc5217SJeff Kirsher o->config_rx_mode = bnx2x_set_rx_mode_e1x; 2594adfc5217SJeff Kirsher } else { 2595adfc5217SJeff Kirsher o->wait_comp = bnx2x_wait_rx_mode_comp_e2; 2596adfc5217SJeff Kirsher o->config_rx_mode = bnx2x_set_rx_mode_e2; 2597adfc5217SJeff Kirsher } 2598adfc5217SJeff Kirsher } 2599adfc5217SJeff Kirsher 2600adfc5217SJeff Kirsher /********************* Multicast verbs: SET, CLEAR ****************************/ 2601adfc5217SJeff Kirsher static inline u8 bnx2x_mcast_bin_from_mac(u8 *mac) 2602adfc5217SJeff Kirsher { 2603adfc5217SJeff Kirsher return (crc32c_le(0, mac, ETH_ALEN) >> 24) & 0xff; 2604adfc5217SJeff Kirsher } 2605adfc5217SJeff Kirsher 2606adfc5217SJeff Kirsher struct bnx2x_mcast_mac_elem { 2607adfc5217SJeff Kirsher struct list_head link; 2608adfc5217SJeff Kirsher u8 mac[ETH_ALEN]; 2609adfc5217SJeff Kirsher u8 pad[2]; /* For a natural alignment of the following buffer */ 2610adfc5217SJeff Kirsher }; 2611adfc5217SJeff Kirsher 2612adfc5217SJeff Kirsher struct bnx2x_pending_mcast_cmd { 2613adfc5217SJeff Kirsher struct list_head link; 2614adfc5217SJeff Kirsher int type; /* BNX2X_MCAST_CMD_X */ 2615adfc5217SJeff Kirsher union { 2616adfc5217SJeff Kirsher struct list_head macs_head; 2617adfc5217SJeff Kirsher u32 macs_num; /* Needed for DEL command */ 2618adfc5217SJeff Kirsher int next_bin; /* Needed for RESTORE flow with aprox match */ 2619adfc5217SJeff Kirsher } data; 2620adfc5217SJeff Kirsher 2621adfc5217SJeff Kirsher bool done; /* set to true, when the command has been handled, 2622adfc5217SJeff Kirsher * practically used in 57712 handling only, where one pending 2623adfc5217SJeff Kirsher * command may be handled in a few operations. As long as for 2624adfc5217SJeff Kirsher * other chips every operation handling is completed in a 2625adfc5217SJeff Kirsher * single ramrod, there is no need to utilize this field. 2626adfc5217SJeff Kirsher */ 2627adfc5217SJeff Kirsher }; 2628adfc5217SJeff Kirsher 2629adfc5217SJeff Kirsher static int bnx2x_mcast_wait(struct bnx2x *bp, 2630adfc5217SJeff Kirsher struct bnx2x_mcast_obj *o) 2631adfc5217SJeff Kirsher { 2632adfc5217SJeff Kirsher if (bnx2x_state_wait(bp, o->sched_state, o->raw.pstate) || 2633adfc5217SJeff Kirsher o->raw.wait_comp(bp, &o->raw)) 2634adfc5217SJeff Kirsher return -EBUSY; 2635adfc5217SJeff Kirsher 2636adfc5217SJeff Kirsher return 0; 2637adfc5217SJeff Kirsher } 2638adfc5217SJeff Kirsher 2639adfc5217SJeff Kirsher static int bnx2x_mcast_enqueue_cmd(struct bnx2x *bp, 2640adfc5217SJeff Kirsher struct bnx2x_mcast_obj *o, 2641adfc5217SJeff Kirsher struct bnx2x_mcast_ramrod_params *p, 264286564c3fSYuval Mintz enum bnx2x_mcast_cmd cmd) 2643adfc5217SJeff Kirsher { 2644adfc5217SJeff Kirsher int total_sz; 2645adfc5217SJeff Kirsher struct bnx2x_pending_mcast_cmd *new_cmd; 2646adfc5217SJeff Kirsher struct bnx2x_mcast_mac_elem *cur_mac = NULL; 2647adfc5217SJeff Kirsher struct bnx2x_mcast_list_elem *pos; 2648adfc5217SJeff Kirsher int macs_list_len = ((cmd == BNX2X_MCAST_CMD_ADD) ? 2649adfc5217SJeff Kirsher p->mcast_list_len : 0); 2650adfc5217SJeff Kirsher 2651adfc5217SJeff Kirsher /* If the command is empty ("handle pending commands only"), break */ 2652adfc5217SJeff Kirsher if (!p->mcast_list_len) 2653adfc5217SJeff Kirsher return 0; 2654adfc5217SJeff Kirsher 2655adfc5217SJeff Kirsher total_sz = sizeof(*new_cmd) + 2656adfc5217SJeff Kirsher macs_list_len * sizeof(struct bnx2x_mcast_mac_elem); 2657adfc5217SJeff Kirsher 2658adfc5217SJeff Kirsher /* Add mcast is called under spin_lock, thus calling with GFP_ATOMIC */ 2659adfc5217SJeff Kirsher new_cmd = kzalloc(total_sz, GFP_ATOMIC); 2660adfc5217SJeff Kirsher 2661adfc5217SJeff Kirsher if (!new_cmd) 2662adfc5217SJeff Kirsher return -ENOMEM; 2663adfc5217SJeff Kirsher 266451c1a580SMerav Sicron DP(BNX2X_MSG_SP, "About to enqueue a new %d command. macs_list_len=%d\n", 266551c1a580SMerav Sicron cmd, macs_list_len); 2666adfc5217SJeff Kirsher 2667adfc5217SJeff Kirsher INIT_LIST_HEAD(&new_cmd->data.macs_head); 2668adfc5217SJeff Kirsher 2669adfc5217SJeff Kirsher new_cmd->type = cmd; 2670adfc5217SJeff Kirsher new_cmd->done = false; 2671adfc5217SJeff Kirsher 2672adfc5217SJeff Kirsher switch (cmd) { 2673adfc5217SJeff Kirsher case BNX2X_MCAST_CMD_ADD: 2674adfc5217SJeff Kirsher cur_mac = (struct bnx2x_mcast_mac_elem *) 2675adfc5217SJeff Kirsher ((u8 *)new_cmd + sizeof(*new_cmd)); 2676adfc5217SJeff Kirsher 267716a5fd92SYuval Mintz /* Push the MACs of the current command into the pending command 2678adfc5217SJeff Kirsher * MACs list: FIFO 2679adfc5217SJeff Kirsher */ 2680adfc5217SJeff Kirsher list_for_each_entry(pos, &p->mcast_list, link) { 2681adfc5217SJeff Kirsher memcpy(cur_mac->mac, pos->mac, ETH_ALEN); 2682adfc5217SJeff Kirsher list_add_tail(&cur_mac->link, &new_cmd->data.macs_head); 2683adfc5217SJeff Kirsher cur_mac++; 2684adfc5217SJeff Kirsher } 2685adfc5217SJeff Kirsher 2686adfc5217SJeff Kirsher break; 2687adfc5217SJeff Kirsher 2688adfc5217SJeff Kirsher case BNX2X_MCAST_CMD_DEL: 2689adfc5217SJeff Kirsher new_cmd->data.macs_num = p->mcast_list_len; 2690adfc5217SJeff Kirsher break; 2691adfc5217SJeff Kirsher 2692adfc5217SJeff Kirsher case BNX2X_MCAST_CMD_RESTORE: 2693adfc5217SJeff Kirsher new_cmd->data.next_bin = 0; 2694adfc5217SJeff Kirsher break; 2695adfc5217SJeff Kirsher 2696adfc5217SJeff Kirsher default: 26978b6d5c09SJesper Juhl kfree(new_cmd); 2698adfc5217SJeff Kirsher BNX2X_ERR("Unknown command: %d\n", cmd); 2699adfc5217SJeff Kirsher return -EINVAL; 2700adfc5217SJeff Kirsher } 2701adfc5217SJeff Kirsher 2702adfc5217SJeff Kirsher /* Push the new pending command to the tail of the pending list: FIFO */ 2703adfc5217SJeff Kirsher list_add_tail(&new_cmd->link, &o->pending_cmds_head); 2704adfc5217SJeff Kirsher 2705adfc5217SJeff Kirsher o->set_sched(o); 2706adfc5217SJeff Kirsher 2707adfc5217SJeff Kirsher return 1; 2708adfc5217SJeff Kirsher } 2709adfc5217SJeff Kirsher 2710adfc5217SJeff Kirsher /** 2711adfc5217SJeff Kirsher * bnx2x_mcast_get_next_bin - get the next set bin (index) 2712adfc5217SJeff Kirsher * 2713adfc5217SJeff Kirsher * @o: 2714adfc5217SJeff Kirsher * @last: index to start looking from (including) 2715adfc5217SJeff Kirsher * 2716adfc5217SJeff Kirsher * returns the next found (set) bin or a negative value if none is found. 2717adfc5217SJeff Kirsher */ 2718adfc5217SJeff Kirsher static inline int bnx2x_mcast_get_next_bin(struct bnx2x_mcast_obj *o, int last) 2719adfc5217SJeff Kirsher { 2720adfc5217SJeff Kirsher int i, j, inner_start = last % BIT_VEC64_ELEM_SZ; 2721adfc5217SJeff Kirsher 2722adfc5217SJeff Kirsher for (i = last / BIT_VEC64_ELEM_SZ; i < BNX2X_MCAST_VEC_SZ; i++) { 2723adfc5217SJeff Kirsher if (o->registry.aprox_match.vec[i]) 2724adfc5217SJeff Kirsher for (j = inner_start; j < BIT_VEC64_ELEM_SZ; j++) { 2725adfc5217SJeff Kirsher int cur_bit = j + BIT_VEC64_ELEM_SZ * i; 2726adfc5217SJeff Kirsher if (BIT_VEC64_TEST_BIT(o->registry.aprox_match. 2727adfc5217SJeff Kirsher vec, cur_bit)) { 2728adfc5217SJeff Kirsher return cur_bit; 2729adfc5217SJeff Kirsher } 2730adfc5217SJeff Kirsher } 2731adfc5217SJeff Kirsher inner_start = 0; 2732adfc5217SJeff Kirsher } 2733adfc5217SJeff Kirsher 2734adfc5217SJeff Kirsher /* None found */ 2735adfc5217SJeff Kirsher return -1; 2736adfc5217SJeff Kirsher } 2737adfc5217SJeff Kirsher 2738adfc5217SJeff Kirsher /** 2739adfc5217SJeff Kirsher * bnx2x_mcast_clear_first_bin - find the first set bin and clear it 2740adfc5217SJeff Kirsher * 2741adfc5217SJeff Kirsher * @o: 2742adfc5217SJeff Kirsher * 2743adfc5217SJeff Kirsher * returns the index of the found bin or -1 if none is found 2744adfc5217SJeff Kirsher */ 2745adfc5217SJeff Kirsher static inline int bnx2x_mcast_clear_first_bin(struct bnx2x_mcast_obj *o) 2746adfc5217SJeff Kirsher { 2747adfc5217SJeff Kirsher int cur_bit = bnx2x_mcast_get_next_bin(o, 0); 2748adfc5217SJeff Kirsher 2749adfc5217SJeff Kirsher if (cur_bit >= 0) 2750adfc5217SJeff Kirsher BIT_VEC64_CLEAR_BIT(o->registry.aprox_match.vec, cur_bit); 2751adfc5217SJeff Kirsher 2752adfc5217SJeff Kirsher return cur_bit; 2753adfc5217SJeff Kirsher } 2754adfc5217SJeff Kirsher 2755adfc5217SJeff Kirsher static inline u8 bnx2x_mcast_get_rx_tx_flag(struct bnx2x_mcast_obj *o) 2756adfc5217SJeff Kirsher { 2757adfc5217SJeff Kirsher struct bnx2x_raw_obj *raw = &o->raw; 2758adfc5217SJeff Kirsher u8 rx_tx_flag = 0; 2759adfc5217SJeff Kirsher 2760adfc5217SJeff Kirsher if ((raw->obj_type == BNX2X_OBJ_TYPE_TX) || 2761adfc5217SJeff Kirsher (raw->obj_type == BNX2X_OBJ_TYPE_RX_TX)) 2762adfc5217SJeff Kirsher rx_tx_flag |= ETH_MULTICAST_RULES_CMD_TX_CMD; 2763adfc5217SJeff Kirsher 2764adfc5217SJeff Kirsher if ((raw->obj_type == BNX2X_OBJ_TYPE_RX) || 2765adfc5217SJeff Kirsher (raw->obj_type == BNX2X_OBJ_TYPE_RX_TX)) 2766adfc5217SJeff Kirsher rx_tx_flag |= ETH_MULTICAST_RULES_CMD_RX_CMD; 2767adfc5217SJeff Kirsher 2768adfc5217SJeff Kirsher return rx_tx_flag; 2769adfc5217SJeff Kirsher } 2770adfc5217SJeff Kirsher 2771adfc5217SJeff Kirsher static void bnx2x_mcast_set_one_rule_e2(struct bnx2x *bp, 2772adfc5217SJeff Kirsher struct bnx2x_mcast_obj *o, int idx, 2773adfc5217SJeff Kirsher union bnx2x_mcast_config_data *cfg_data, 277486564c3fSYuval Mintz enum bnx2x_mcast_cmd cmd) 2775adfc5217SJeff Kirsher { 2776adfc5217SJeff Kirsher struct bnx2x_raw_obj *r = &o->raw; 2777adfc5217SJeff Kirsher struct eth_multicast_rules_ramrod_data *data = 2778adfc5217SJeff Kirsher (struct eth_multicast_rules_ramrod_data *)(r->rdata); 2779adfc5217SJeff Kirsher u8 func_id = r->func_id; 2780adfc5217SJeff Kirsher u8 rx_tx_add_flag = bnx2x_mcast_get_rx_tx_flag(o); 2781adfc5217SJeff Kirsher int bin; 2782adfc5217SJeff Kirsher 2783adfc5217SJeff Kirsher if ((cmd == BNX2X_MCAST_CMD_ADD) || (cmd == BNX2X_MCAST_CMD_RESTORE)) 2784adfc5217SJeff Kirsher rx_tx_add_flag |= ETH_MULTICAST_RULES_CMD_IS_ADD; 2785adfc5217SJeff Kirsher 2786adfc5217SJeff Kirsher data->rules[idx].cmd_general_data |= rx_tx_add_flag; 2787adfc5217SJeff Kirsher 2788adfc5217SJeff Kirsher /* Get a bin and update a bins' vector */ 2789adfc5217SJeff Kirsher switch (cmd) { 2790adfc5217SJeff Kirsher case BNX2X_MCAST_CMD_ADD: 2791adfc5217SJeff Kirsher bin = bnx2x_mcast_bin_from_mac(cfg_data->mac); 2792adfc5217SJeff Kirsher BIT_VEC64_SET_BIT(o->registry.aprox_match.vec, bin); 2793adfc5217SJeff Kirsher break; 2794adfc5217SJeff Kirsher 2795adfc5217SJeff Kirsher case BNX2X_MCAST_CMD_DEL: 2796adfc5217SJeff Kirsher /* If there were no more bins to clear 2797adfc5217SJeff Kirsher * (bnx2x_mcast_clear_first_bin() returns -1) then we would 2798adfc5217SJeff Kirsher * clear any (0xff) bin. 2799adfc5217SJeff Kirsher * See bnx2x_mcast_validate_e2() for explanation when it may 2800adfc5217SJeff Kirsher * happen. 2801adfc5217SJeff Kirsher */ 2802adfc5217SJeff Kirsher bin = bnx2x_mcast_clear_first_bin(o); 2803adfc5217SJeff Kirsher break; 2804adfc5217SJeff Kirsher 2805adfc5217SJeff Kirsher case BNX2X_MCAST_CMD_RESTORE: 2806adfc5217SJeff Kirsher bin = cfg_data->bin; 2807adfc5217SJeff Kirsher break; 2808adfc5217SJeff Kirsher 2809adfc5217SJeff Kirsher default: 2810adfc5217SJeff Kirsher BNX2X_ERR("Unknown command: %d\n", cmd); 2811adfc5217SJeff Kirsher return; 2812adfc5217SJeff Kirsher } 2813adfc5217SJeff Kirsher 2814adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "%s bin %d\n", 2815adfc5217SJeff Kirsher ((rx_tx_add_flag & ETH_MULTICAST_RULES_CMD_IS_ADD) ? 2816adfc5217SJeff Kirsher "Setting" : "Clearing"), bin); 2817adfc5217SJeff Kirsher 2818adfc5217SJeff Kirsher data->rules[idx].bin_id = (u8)bin; 2819adfc5217SJeff Kirsher data->rules[idx].func_id = func_id; 2820adfc5217SJeff Kirsher data->rules[idx].engine_id = o->engine_id; 2821adfc5217SJeff Kirsher } 2822adfc5217SJeff Kirsher 2823adfc5217SJeff Kirsher /** 2824adfc5217SJeff Kirsher * bnx2x_mcast_handle_restore_cmd_e2 - restore configuration from the registry 2825adfc5217SJeff Kirsher * 2826adfc5217SJeff Kirsher * @bp: device handle 2827adfc5217SJeff Kirsher * @o: 2828adfc5217SJeff Kirsher * @start_bin: index in the registry to start from (including) 2829adfc5217SJeff Kirsher * @rdata_idx: index in the ramrod data to start from 2830adfc5217SJeff Kirsher * 2831adfc5217SJeff Kirsher * returns last handled bin index or -1 if all bins have been handled 2832adfc5217SJeff Kirsher */ 2833adfc5217SJeff Kirsher static inline int bnx2x_mcast_handle_restore_cmd_e2( 2834adfc5217SJeff Kirsher struct bnx2x *bp, struct bnx2x_mcast_obj *o , int start_bin, 2835adfc5217SJeff Kirsher int *rdata_idx) 2836adfc5217SJeff Kirsher { 2837adfc5217SJeff Kirsher int cur_bin, cnt = *rdata_idx; 283886564c3fSYuval Mintz union bnx2x_mcast_config_data cfg_data = {NULL}; 2839adfc5217SJeff Kirsher 2840adfc5217SJeff Kirsher /* go through the registry and configure the bins from it */ 2841adfc5217SJeff Kirsher for (cur_bin = bnx2x_mcast_get_next_bin(o, start_bin); cur_bin >= 0; 2842adfc5217SJeff Kirsher cur_bin = bnx2x_mcast_get_next_bin(o, cur_bin + 1)) { 2843adfc5217SJeff Kirsher 2844adfc5217SJeff Kirsher cfg_data.bin = (u8)cur_bin; 2845adfc5217SJeff Kirsher o->set_one_rule(bp, o, cnt, &cfg_data, 2846adfc5217SJeff Kirsher BNX2X_MCAST_CMD_RESTORE); 2847adfc5217SJeff Kirsher 2848adfc5217SJeff Kirsher cnt++; 2849adfc5217SJeff Kirsher 2850adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "About to configure a bin %d\n", cur_bin); 2851adfc5217SJeff Kirsher 2852adfc5217SJeff Kirsher /* Break if we reached the maximum number 2853adfc5217SJeff Kirsher * of rules. 2854adfc5217SJeff Kirsher */ 2855adfc5217SJeff Kirsher if (cnt >= o->max_cmd_len) 2856adfc5217SJeff Kirsher break; 2857adfc5217SJeff Kirsher } 2858adfc5217SJeff Kirsher 2859adfc5217SJeff Kirsher *rdata_idx = cnt; 2860adfc5217SJeff Kirsher 2861adfc5217SJeff Kirsher return cur_bin; 2862adfc5217SJeff Kirsher } 2863adfc5217SJeff Kirsher 2864adfc5217SJeff Kirsher static inline void bnx2x_mcast_hdl_pending_add_e2(struct bnx2x *bp, 2865adfc5217SJeff Kirsher struct bnx2x_mcast_obj *o, struct bnx2x_pending_mcast_cmd *cmd_pos, 2866adfc5217SJeff Kirsher int *line_idx) 2867adfc5217SJeff Kirsher { 2868adfc5217SJeff Kirsher struct bnx2x_mcast_mac_elem *pmac_pos, *pmac_pos_n; 2869adfc5217SJeff Kirsher int cnt = *line_idx; 287086564c3fSYuval Mintz union bnx2x_mcast_config_data cfg_data = {NULL}; 2871adfc5217SJeff Kirsher 2872adfc5217SJeff Kirsher list_for_each_entry_safe(pmac_pos, pmac_pos_n, &cmd_pos->data.macs_head, 2873adfc5217SJeff Kirsher link) { 2874adfc5217SJeff Kirsher 2875adfc5217SJeff Kirsher cfg_data.mac = &pmac_pos->mac[0]; 2876adfc5217SJeff Kirsher o->set_one_rule(bp, o, cnt, &cfg_data, cmd_pos->type); 2877adfc5217SJeff Kirsher 2878adfc5217SJeff Kirsher cnt++; 2879adfc5217SJeff Kirsher 28800f9dad10SJoe Perches DP(BNX2X_MSG_SP, "About to configure %pM mcast MAC\n", 28810f9dad10SJoe Perches pmac_pos->mac); 2882adfc5217SJeff Kirsher 2883adfc5217SJeff Kirsher list_del(&pmac_pos->link); 2884adfc5217SJeff Kirsher 2885adfc5217SJeff Kirsher /* Break if we reached the maximum number 2886adfc5217SJeff Kirsher * of rules. 2887adfc5217SJeff Kirsher */ 2888adfc5217SJeff Kirsher if (cnt >= o->max_cmd_len) 2889adfc5217SJeff Kirsher break; 2890adfc5217SJeff Kirsher } 2891adfc5217SJeff Kirsher 2892adfc5217SJeff Kirsher *line_idx = cnt; 2893adfc5217SJeff Kirsher 2894adfc5217SJeff Kirsher /* if no more MACs to configure - we are done */ 2895adfc5217SJeff Kirsher if (list_empty(&cmd_pos->data.macs_head)) 2896adfc5217SJeff Kirsher cmd_pos->done = true; 2897adfc5217SJeff Kirsher } 2898adfc5217SJeff Kirsher 2899adfc5217SJeff Kirsher static inline void bnx2x_mcast_hdl_pending_del_e2(struct bnx2x *bp, 2900adfc5217SJeff Kirsher struct bnx2x_mcast_obj *o, struct bnx2x_pending_mcast_cmd *cmd_pos, 2901adfc5217SJeff Kirsher int *line_idx) 2902adfc5217SJeff Kirsher { 2903adfc5217SJeff Kirsher int cnt = *line_idx; 2904adfc5217SJeff Kirsher 2905adfc5217SJeff Kirsher while (cmd_pos->data.macs_num) { 2906adfc5217SJeff Kirsher o->set_one_rule(bp, o, cnt, NULL, cmd_pos->type); 2907adfc5217SJeff Kirsher 2908adfc5217SJeff Kirsher cnt++; 2909adfc5217SJeff Kirsher 2910adfc5217SJeff Kirsher cmd_pos->data.macs_num--; 2911adfc5217SJeff Kirsher 2912adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "Deleting MAC. %d left,cnt is %d\n", 2913adfc5217SJeff Kirsher cmd_pos->data.macs_num, cnt); 2914adfc5217SJeff Kirsher 2915adfc5217SJeff Kirsher /* Break if we reached the maximum 2916adfc5217SJeff Kirsher * number of rules. 2917adfc5217SJeff Kirsher */ 2918adfc5217SJeff Kirsher if (cnt >= o->max_cmd_len) 2919adfc5217SJeff Kirsher break; 2920adfc5217SJeff Kirsher } 2921adfc5217SJeff Kirsher 2922adfc5217SJeff Kirsher *line_idx = cnt; 2923adfc5217SJeff Kirsher 2924adfc5217SJeff Kirsher /* If we cleared all bins - we are done */ 2925adfc5217SJeff Kirsher if (!cmd_pos->data.macs_num) 2926adfc5217SJeff Kirsher cmd_pos->done = true; 2927adfc5217SJeff Kirsher } 2928adfc5217SJeff Kirsher 2929adfc5217SJeff Kirsher static inline void bnx2x_mcast_hdl_pending_restore_e2(struct bnx2x *bp, 2930adfc5217SJeff Kirsher struct bnx2x_mcast_obj *o, struct bnx2x_pending_mcast_cmd *cmd_pos, 2931adfc5217SJeff Kirsher int *line_idx) 2932adfc5217SJeff Kirsher { 2933adfc5217SJeff Kirsher cmd_pos->data.next_bin = o->hdl_restore(bp, o, cmd_pos->data.next_bin, 2934adfc5217SJeff Kirsher line_idx); 2935adfc5217SJeff Kirsher 2936adfc5217SJeff Kirsher if (cmd_pos->data.next_bin < 0) 2937adfc5217SJeff Kirsher /* If o->set_restore returned -1 we are done */ 2938adfc5217SJeff Kirsher cmd_pos->done = true; 2939adfc5217SJeff Kirsher else 2940adfc5217SJeff Kirsher /* Start from the next bin next time */ 2941adfc5217SJeff Kirsher cmd_pos->data.next_bin++; 2942adfc5217SJeff Kirsher } 2943adfc5217SJeff Kirsher 2944adfc5217SJeff Kirsher static inline int bnx2x_mcast_handle_pending_cmds_e2(struct bnx2x *bp, 2945adfc5217SJeff Kirsher struct bnx2x_mcast_ramrod_params *p) 2946adfc5217SJeff Kirsher { 2947adfc5217SJeff Kirsher struct bnx2x_pending_mcast_cmd *cmd_pos, *cmd_pos_n; 2948adfc5217SJeff Kirsher int cnt = 0; 2949adfc5217SJeff Kirsher struct bnx2x_mcast_obj *o = p->mcast_obj; 2950adfc5217SJeff Kirsher 2951adfc5217SJeff Kirsher list_for_each_entry_safe(cmd_pos, cmd_pos_n, &o->pending_cmds_head, 2952adfc5217SJeff Kirsher link) { 2953adfc5217SJeff Kirsher switch (cmd_pos->type) { 2954adfc5217SJeff Kirsher case BNX2X_MCAST_CMD_ADD: 2955adfc5217SJeff Kirsher bnx2x_mcast_hdl_pending_add_e2(bp, o, cmd_pos, &cnt); 2956adfc5217SJeff Kirsher break; 2957adfc5217SJeff Kirsher 2958adfc5217SJeff Kirsher case BNX2X_MCAST_CMD_DEL: 2959adfc5217SJeff Kirsher bnx2x_mcast_hdl_pending_del_e2(bp, o, cmd_pos, &cnt); 2960adfc5217SJeff Kirsher break; 2961adfc5217SJeff Kirsher 2962adfc5217SJeff Kirsher case BNX2X_MCAST_CMD_RESTORE: 2963adfc5217SJeff Kirsher bnx2x_mcast_hdl_pending_restore_e2(bp, o, cmd_pos, 2964adfc5217SJeff Kirsher &cnt); 2965adfc5217SJeff Kirsher break; 2966adfc5217SJeff Kirsher 2967adfc5217SJeff Kirsher default: 2968adfc5217SJeff Kirsher BNX2X_ERR("Unknown command: %d\n", cmd_pos->type); 2969adfc5217SJeff Kirsher return -EINVAL; 2970adfc5217SJeff Kirsher } 2971adfc5217SJeff Kirsher 2972adfc5217SJeff Kirsher /* If the command has been completed - remove it from the list 2973adfc5217SJeff Kirsher * and free the memory 2974adfc5217SJeff Kirsher */ 2975adfc5217SJeff Kirsher if (cmd_pos->done) { 2976adfc5217SJeff Kirsher list_del(&cmd_pos->link); 2977adfc5217SJeff Kirsher kfree(cmd_pos); 2978adfc5217SJeff Kirsher } 2979adfc5217SJeff Kirsher 2980adfc5217SJeff Kirsher /* Break if we reached the maximum number of rules */ 2981adfc5217SJeff Kirsher if (cnt >= o->max_cmd_len) 2982adfc5217SJeff Kirsher break; 2983adfc5217SJeff Kirsher } 2984adfc5217SJeff Kirsher 2985adfc5217SJeff Kirsher return cnt; 2986adfc5217SJeff Kirsher } 2987adfc5217SJeff Kirsher 2988adfc5217SJeff Kirsher static inline void bnx2x_mcast_hdl_add(struct bnx2x *bp, 2989adfc5217SJeff Kirsher struct bnx2x_mcast_obj *o, struct bnx2x_mcast_ramrod_params *p, 2990adfc5217SJeff Kirsher int *line_idx) 2991adfc5217SJeff Kirsher { 2992adfc5217SJeff Kirsher struct bnx2x_mcast_list_elem *mlist_pos; 299386564c3fSYuval Mintz union bnx2x_mcast_config_data cfg_data = {NULL}; 2994adfc5217SJeff Kirsher int cnt = *line_idx; 2995adfc5217SJeff Kirsher 2996adfc5217SJeff Kirsher list_for_each_entry(mlist_pos, &p->mcast_list, link) { 2997adfc5217SJeff Kirsher cfg_data.mac = mlist_pos->mac; 2998adfc5217SJeff Kirsher o->set_one_rule(bp, o, cnt, &cfg_data, BNX2X_MCAST_CMD_ADD); 2999adfc5217SJeff Kirsher 3000adfc5217SJeff Kirsher cnt++; 3001adfc5217SJeff Kirsher 30020f9dad10SJoe Perches DP(BNX2X_MSG_SP, "About to configure %pM mcast MAC\n", 30030f9dad10SJoe Perches mlist_pos->mac); 3004adfc5217SJeff Kirsher } 3005adfc5217SJeff Kirsher 3006adfc5217SJeff Kirsher *line_idx = cnt; 3007adfc5217SJeff Kirsher } 3008adfc5217SJeff Kirsher 3009adfc5217SJeff Kirsher static inline void bnx2x_mcast_hdl_del(struct bnx2x *bp, 3010adfc5217SJeff Kirsher struct bnx2x_mcast_obj *o, struct bnx2x_mcast_ramrod_params *p, 3011adfc5217SJeff Kirsher int *line_idx) 3012adfc5217SJeff Kirsher { 3013adfc5217SJeff Kirsher int cnt = *line_idx, i; 3014adfc5217SJeff Kirsher 3015adfc5217SJeff Kirsher for (i = 0; i < p->mcast_list_len; i++) { 3016adfc5217SJeff Kirsher o->set_one_rule(bp, o, cnt, NULL, BNX2X_MCAST_CMD_DEL); 3017adfc5217SJeff Kirsher 3018adfc5217SJeff Kirsher cnt++; 3019adfc5217SJeff Kirsher 3020adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "Deleting MAC. %d left\n", 3021adfc5217SJeff Kirsher p->mcast_list_len - i - 1); 3022adfc5217SJeff Kirsher } 3023adfc5217SJeff Kirsher 3024adfc5217SJeff Kirsher *line_idx = cnt; 3025adfc5217SJeff Kirsher } 3026adfc5217SJeff Kirsher 3027adfc5217SJeff Kirsher /** 3028adfc5217SJeff Kirsher * bnx2x_mcast_handle_current_cmd - 3029adfc5217SJeff Kirsher * 3030adfc5217SJeff Kirsher * @bp: device handle 3031adfc5217SJeff Kirsher * @p: 3032adfc5217SJeff Kirsher * @cmd: 3033adfc5217SJeff Kirsher * @start_cnt: first line in the ramrod data that may be used 3034adfc5217SJeff Kirsher * 3035adfc5217SJeff Kirsher * This function is called iff there is enough place for the current command in 3036adfc5217SJeff Kirsher * the ramrod data. 3037adfc5217SJeff Kirsher * Returns number of lines filled in the ramrod data in total. 3038adfc5217SJeff Kirsher */ 3039adfc5217SJeff Kirsher static inline int bnx2x_mcast_handle_current_cmd(struct bnx2x *bp, 304086564c3fSYuval Mintz struct bnx2x_mcast_ramrod_params *p, 304186564c3fSYuval Mintz enum bnx2x_mcast_cmd cmd, 3042adfc5217SJeff Kirsher int start_cnt) 3043adfc5217SJeff Kirsher { 3044adfc5217SJeff Kirsher struct bnx2x_mcast_obj *o = p->mcast_obj; 3045adfc5217SJeff Kirsher int cnt = start_cnt; 3046adfc5217SJeff Kirsher 3047adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "p->mcast_list_len=%d\n", p->mcast_list_len); 3048adfc5217SJeff Kirsher 3049adfc5217SJeff Kirsher switch (cmd) { 3050adfc5217SJeff Kirsher case BNX2X_MCAST_CMD_ADD: 3051adfc5217SJeff Kirsher bnx2x_mcast_hdl_add(bp, o, p, &cnt); 3052adfc5217SJeff Kirsher break; 3053adfc5217SJeff Kirsher 3054adfc5217SJeff Kirsher case BNX2X_MCAST_CMD_DEL: 3055adfc5217SJeff Kirsher bnx2x_mcast_hdl_del(bp, o, p, &cnt); 3056adfc5217SJeff Kirsher break; 3057adfc5217SJeff Kirsher 3058adfc5217SJeff Kirsher case BNX2X_MCAST_CMD_RESTORE: 3059adfc5217SJeff Kirsher o->hdl_restore(bp, o, 0, &cnt); 3060adfc5217SJeff Kirsher break; 3061adfc5217SJeff Kirsher 3062adfc5217SJeff Kirsher default: 3063adfc5217SJeff Kirsher BNX2X_ERR("Unknown command: %d\n", cmd); 3064adfc5217SJeff Kirsher return -EINVAL; 3065adfc5217SJeff Kirsher } 3066adfc5217SJeff Kirsher 3067adfc5217SJeff Kirsher /* The current command has been handled */ 3068adfc5217SJeff Kirsher p->mcast_list_len = 0; 3069adfc5217SJeff Kirsher 3070adfc5217SJeff Kirsher return cnt; 3071adfc5217SJeff Kirsher } 3072adfc5217SJeff Kirsher 3073adfc5217SJeff Kirsher static int bnx2x_mcast_validate_e2(struct bnx2x *bp, 3074adfc5217SJeff Kirsher struct bnx2x_mcast_ramrod_params *p, 307586564c3fSYuval Mintz enum bnx2x_mcast_cmd cmd) 3076adfc5217SJeff Kirsher { 3077adfc5217SJeff Kirsher struct bnx2x_mcast_obj *o = p->mcast_obj; 3078adfc5217SJeff Kirsher int reg_sz = o->get_registry_size(o); 3079adfc5217SJeff Kirsher 3080adfc5217SJeff Kirsher switch (cmd) { 3081adfc5217SJeff Kirsher /* DEL command deletes all currently configured MACs */ 3082adfc5217SJeff Kirsher case BNX2X_MCAST_CMD_DEL: 3083adfc5217SJeff Kirsher o->set_registry_size(o, 0); 3084adfc5217SJeff Kirsher /* Don't break */ 3085adfc5217SJeff Kirsher 3086adfc5217SJeff Kirsher /* RESTORE command will restore the entire multicast configuration */ 3087adfc5217SJeff Kirsher case BNX2X_MCAST_CMD_RESTORE: 3088adfc5217SJeff Kirsher /* Here we set the approximate amount of work to do, which in 3089adfc5217SJeff Kirsher * fact may be only less as some MACs in postponed ADD 3090adfc5217SJeff Kirsher * command(s) scheduled before this command may fall into 3091adfc5217SJeff Kirsher * the same bin and the actual number of bins set in the 3092adfc5217SJeff Kirsher * registry would be less than we estimated here. See 3093adfc5217SJeff Kirsher * bnx2x_mcast_set_one_rule_e2() for further details. 3094adfc5217SJeff Kirsher */ 3095adfc5217SJeff Kirsher p->mcast_list_len = reg_sz; 3096adfc5217SJeff Kirsher break; 3097adfc5217SJeff Kirsher 3098adfc5217SJeff Kirsher case BNX2X_MCAST_CMD_ADD: 3099adfc5217SJeff Kirsher case BNX2X_MCAST_CMD_CONT: 3100adfc5217SJeff Kirsher /* Here we assume that all new MACs will fall into new bins. 3101adfc5217SJeff Kirsher * However we will correct the real registry size after we 3102adfc5217SJeff Kirsher * handle all pending commands. 3103adfc5217SJeff Kirsher */ 3104adfc5217SJeff Kirsher o->set_registry_size(o, reg_sz + p->mcast_list_len); 3105adfc5217SJeff Kirsher break; 3106adfc5217SJeff Kirsher 3107adfc5217SJeff Kirsher default: 3108adfc5217SJeff Kirsher BNX2X_ERR("Unknown command: %d\n", cmd); 3109adfc5217SJeff Kirsher return -EINVAL; 3110adfc5217SJeff Kirsher } 3111adfc5217SJeff Kirsher 3112adfc5217SJeff Kirsher /* Increase the total number of MACs pending to be configured */ 3113adfc5217SJeff Kirsher o->total_pending_num += p->mcast_list_len; 3114adfc5217SJeff Kirsher 3115adfc5217SJeff Kirsher return 0; 3116adfc5217SJeff Kirsher } 3117adfc5217SJeff Kirsher 3118adfc5217SJeff Kirsher static void bnx2x_mcast_revert_e2(struct bnx2x *bp, 3119adfc5217SJeff Kirsher struct bnx2x_mcast_ramrod_params *p, 3120adfc5217SJeff Kirsher int old_num_bins) 3121adfc5217SJeff Kirsher { 3122adfc5217SJeff Kirsher struct bnx2x_mcast_obj *o = p->mcast_obj; 3123adfc5217SJeff Kirsher 3124adfc5217SJeff Kirsher o->set_registry_size(o, old_num_bins); 3125adfc5217SJeff Kirsher o->total_pending_num -= p->mcast_list_len; 3126adfc5217SJeff Kirsher } 3127adfc5217SJeff Kirsher 3128adfc5217SJeff Kirsher /** 3129adfc5217SJeff Kirsher * bnx2x_mcast_set_rdata_hdr_e2 - sets a header values 3130adfc5217SJeff Kirsher * 3131adfc5217SJeff Kirsher * @bp: device handle 3132adfc5217SJeff Kirsher * @p: 3133adfc5217SJeff Kirsher * @len: number of rules to handle 3134adfc5217SJeff Kirsher */ 3135adfc5217SJeff Kirsher static inline void bnx2x_mcast_set_rdata_hdr_e2(struct bnx2x *bp, 3136adfc5217SJeff Kirsher struct bnx2x_mcast_ramrod_params *p, 3137adfc5217SJeff Kirsher u8 len) 3138adfc5217SJeff Kirsher { 3139adfc5217SJeff Kirsher struct bnx2x_raw_obj *r = &p->mcast_obj->raw; 3140adfc5217SJeff Kirsher struct eth_multicast_rules_ramrod_data *data = 3141adfc5217SJeff Kirsher (struct eth_multicast_rules_ramrod_data *)(r->rdata); 3142adfc5217SJeff Kirsher 314386564c3fSYuval Mintz data->header.echo = cpu_to_le32((r->cid & BNX2X_SWCID_MASK) | 314486564c3fSYuval Mintz (BNX2X_FILTER_MCAST_PENDING << 314586564c3fSYuval Mintz BNX2X_SWCID_SHIFT)); 3146adfc5217SJeff Kirsher data->header.rule_cnt = len; 3147adfc5217SJeff Kirsher } 3148adfc5217SJeff Kirsher 3149adfc5217SJeff Kirsher /** 3150adfc5217SJeff Kirsher * bnx2x_mcast_refresh_registry_e2 - recalculate the actual number of set bins 3151adfc5217SJeff Kirsher * 3152adfc5217SJeff Kirsher * @bp: device handle 3153adfc5217SJeff Kirsher * @o: 3154adfc5217SJeff Kirsher * 3155adfc5217SJeff Kirsher * Recalculate the actual number of set bins in the registry using Brian 3156adfc5217SJeff Kirsher * Kernighan's algorithm: it's execution complexity is as a number of set bins. 3157adfc5217SJeff Kirsher * 3158adfc5217SJeff Kirsher * returns 0 for the compliance with bnx2x_mcast_refresh_registry_e1(). 3159adfc5217SJeff Kirsher */ 3160adfc5217SJeff Kirsher static inline int bnx2x_mcast_refresh_registry_e2(struct bnx2x *bp, 3161adfc5217SJeff Kirsher struct bnx2x_mcast_obj *o) 3162adfc5217SJeff Kirsher { 3163adfc5217SJeff Kirsher int i, cnt = 0; 3164adfc5217SJeff Kirsher u64 elem; 3165adfc5217SJeff Kirsher 3166adfc5217SJeff Kirsher for (i = 0; i < BNX2X_MCAST_VEC_SZ; i++) { 3167adfc5217SJeff Kirsher elem = o->registry.aprox_match.vec[i]; 3168adfc5217SJeff Kirsher for (; elem; cnt++) 3169adfc5217SJeff Kirsher elem &= elem - 1; 3170adfc5217SJeff Kirsher } 3171adfc5217SJeff Kirsher 3172adfc5217SJeff Kirsher o->set_registry_size(o, cnt); 3173adfc5217SJeff Kirsher 3174adfc5217SJeff Kirsher return 0; 3175adfc5217SJeff Kirsher } 3176adfc5217SJeff Kirsher 3177adfc5217SJeff Kirsher static int bnx2x_mcast_setup_e2(struct bnx2x *bp, 3178adfc5217SJeff Kirsher struct bnx2x_mcast_ramrod_params *p, 317986564c3fSYuval Mintz enum bnx2x_mcast_cmd cmd) 3180adfc5217SJeff Kirsher { 3181adfc5217SJeff Kirsher struct bnx2x_raw_obj *raw = &p->mcast_obj->raw; 3182adfc5217SJeff Kirsher struct bnx2x_mcast_obj *o = p->mcast_obj; 3183adfc5217SJeff Kirsher struct eth_multicast_rules_ramrod_data *data = 3184adfc5217SJeff Kirsher (struct eth_multicast_rules_ramrod_data *)(raw->rdata); 3185adfc5217SJeff Kirsher int cnt = 0, rc; 3186adfc5217SJeff Kirsher 3187adfc5217SJeff Kirsher /* Reset the ramrod data buffer */ 3188adfc5217SJeff Kirsher memset(data, 0, sizeof(*data)); 3189adfc5217SJeff Kirsher 3190adfc5217SJeff Kirsher cnt = bnx2x_mcast_handle_pending_cmds_e2(bp, p); 3191adfc5217SJeff Kirsher 3192adfc5217SJeff Kirsher /* If there are no more pending commands - clear SCHEDULED state */ 3193adfc5217SJeff Kirsher if (list_empty(&o->pending_cmds_head)) 3194adfc5217SJeff Kirsher o->clear_sched(o); 3195adfc5217SJeff Kirsher 3196adfc5217SJeff Kirsher /* The below may be true iff there was enough room in ramrod 3197adfc5217SJeff Kirsher * data for all pending commands and for the current 3198adfc5217SJeff Kirsher * command. Otherwise the current command would have been added 3199adfc5217SJeff Kirsher * to the pending commands and p->mcast_list_len would have been 3200adfc5217SJeff Kirsher * zeroed. 3201adfc5217SJeff Kirsher */ 3202adfc5217SJeff Kirsher if (p->mcast_list_len > 0) 3203adfc5217SJeff Kirsher cnt = bnx2x_mcast_handle_current_cmd(bp, p, cmd, cnt); 3204adfc5217SJeff Kirsher 3205adfc5217SJeff Kirsher /* We've pulled out some MACs - update the total number of 3206adfc5217SJeff Kirsher * outstanding. 3207adfc5217SJeff Kirsher */ 3208adfc5217SJeff Kirsher o->total_pending_num -= cnt; 3209adfc5217SJeff Kirsher 3210adfc5217SJeff Kirsher /* send a ramrod */ 3211adfc5217SJeff Kirsher WARN_ON(o->total_pending_num < 0); 3212adfc5217SJeff Kirsher WARN_ON(cnt > o->max_cmd_len); 3213adfc5217SJeff Kirsher 3214adfc5217SJeff Kirsher bnx2x_mcast_set_rdata_hdr_e2(bp, p, (u8)cnt); 3215adfc5217SJeff Kirsher 3216adfc5217SJeff Kirsher /* Update a registry size if there are no more pending operations. 3217adfc5217SJeff Kirsher * 3218adfc5217SJeff Kirsher * We don't want to change the value of the registry size if there are 3219adfc5217SJeff Kirsher * pending operations because we want it to always be equal to the 3220adfc5217SJeff Kirsher * exact or the approximate number (see bnx2x_mcast_validate_e2()) of 3221adfc5217SJeff Kirsher * set bins after the last requested operation in order to properly 3222adfc5217SJeff Kirsher * evaluate the size of the next DEL/RESTORE operation. 3223adfc5217SJeff Kirsher * 3224adfc5217SJeff Kirsher * Note that we update the registry itself during command(s) handling 3225adfc5217SJeff Kirsher * - see bnx2x_mcast_set_one_rule_e2(). That's because for 57712 we 3226adfc5217SJeff Kirsher * aggregate multiple commands (ADD/DEL/RESTORE) into one ramrod but 3227adfc5217SJeff Kirsher * with a limited amount of update commands (per MAC/bin) and we don't 3228adfc5217SJeff Kirsher * know in this scope what the actual state of bins configuration is 3229adfc5217SJeff Kirsher * going to be after this ramrod. 3230adfc5217SJeff Kirsher */ 3231adfc5217SJeff Kirsher if (!o->total_pending_num) 3232adfc5217SJeff Kirsher bnx2x_mcast_refresh_registry_e2(bp, o); 3233adfc5217SJeff Kirsher 323416a5fd92SYuval Mintz /* If CLEAR_ONLY was requested - don't send a ramrod and clear 3235adfc5217SJeff Kirsher * RAMROD_PENDING status immediately. 3236adfc5217SJeff Kirsher */ 3237adfc5217SJeff Kirsher if (test_bit(RAMROD_DRV_CLR_ONLY, &p->ramrod_flags)) { 3238adfc5217SJeff Kirsher raw->clear_pending(raw); 3239adfc5217SJeff Kirsher return 0; 3240adfc5217SJeff Kirsher } else { 324116a5fd92SYuval Mintz /* No need for an explicit memory barrier here as long we would 3242adfc5217SJeff Kirsher * need to ensure the ordering of writing to the SPQ element 3243adfc5217SJeff Kirsher * and updating of the SPQ producer which involves a memory 3244adfc5217SJeff Kirsher * read and we will have to put a full memory barrier there 3245adfc5217SJeff Kirsher * (inside bnx2x_sp_post()). 3246adfc5217SJeff Kirsher */ 3247adfc5217SJeff Kirsher 3248adfc5217SJeff Kirsher /* Send a ramrod */ 3249adfc5217SJeff Kirsher rc = bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_MULTICAST_RULES, 3250adfc5217SJeff Kirsher raw->cid, U64_HI(raw->rdata_mapping), 3251adfc5217SJeff Kirsher U64_LO(raw->rdata_mapping), 3252adfc5217SJeff Kirsher ETH_CONNECTION_TYPE); 3253adfc5217SJeff Kirsher if (rc) 3254adfc5217SJeff Kirsher return rc; 3255adfc5217SJeff Kirsher 3256adfc5217SJeff Kirsher /* Ramrod completion is pending */ 3257adfc5217SJeff Kirsher return 1; 3258adfc5217SJeff Kirsher } 3259adfc5217SJeff Kirsher } 3260adfc5217SJeff Kirsher 3261adfc5217SJeff Kirsher static int bnx2x_mcast_validate_e1h(struct bnx2x *bp, 3262adfc5217SJeff Kirsher struct bnx2x_mcast_ramrod_params *p, 326386564c3fSYuval Mintz enum bnx2x_mcast_cmd cmd) 3264adfc5217SJeff Kirsher { 3265adfc5217SJeff Kirsher /* Mark, that there is a work to do */ 3266adfc5217SJeff Kirsher if ((cmd == BNX2X_MCAST_CMD_DEL) || (cmd == BNX2X_MCAST_CMD_RESTORE)) 3267adfc5217SJeff Kirsher p->mcast_list_len = 1; 3268adfc5217SJeff Kirsher 3269adfc5217SJeff Kirsher return 0; 3270adfc5217SJeff Kirsher } 3271adfc5217SJeff Kirsher 3272adfc5217SJeff Kirsher static void bnx2x_mcast_revert_e1h(struct bnx2x *bp, 3273adfc5217SJeff Kirsher struct bnx2x_mcast_ramrod_params *p, 3274adfc5217SJeff Kirsher int old_num_bins) 3275adfc5217SJeff Kirsher { 3276adfc5217SJeff Kirsher /* Do nothing */ 3277adfc5217SJeff Kirsher } 3278adfc5217SJeff Kirsher 3279adfc5217SJeff Kirsher #define BNX2X_57711_SET_MC_FILTER(filter, bit) \ 3280adfc5217SJeff Kirsher do { \ 3281adfc5217SJeff Kirsher (filter)[(bit) >> 5] |= (1 << ((bit) & 0x1f)); \ 3282adfc5217SJeff Kirsher } while (0) 3283adfc5217SJeff Kirsher 3284adfc5217SJeff Kirsher static inline void bnx2x_mcast_hdl_add_e1h(struct bnx2x *bp, 3285adfc5217SJeff Kirsher struct bnx2x_mcast_obj *o, 3286adfc5217SJeff Kirsher struct bnx2x_mcast_ramrod_params *p, 3287adfc5217SJeff Kirsher u32 *mc_filter) 3288adfc5217SJeff Kirsher { 3289adfc5217SJeff Kirsher struct bnx2x_mcast_list_elem *mlist_pos; 3290adfc5217SJeff Kirsher int bit; 3291adfc5217SJeff Kirsher 3292adfc5217SJeff Kirsher list_for_each_entry(mlist_pos, &p->mcast_list, link) { 3293adfc5217SJeff Kirsher bit = bnx2x_mcast_bin_from_mac(mlist_pos->mac); 3294adfc5217SJeff Kirsher BNX2X_57711_SET_MC_FILTER(mc_filter, bit); 3295adfc5217SJeff Kirsher 32960f9dad10SJoe Perches DP(BNX2X_MSG_SP, "About to configure %pM mcast MAC, bin %d\n", 32970f9dad10SJoe Perches mlist_pos->mac, bit); 3298adfc5217SJeff Kirsher 3299adfc5217SJeff Kirsher /* bookkeeping... */ 3300adfc5217SJeff Kirsher BIT_VEC64_SET_BIT(o->registry.aprox_match.vec, 3301adfc5217SJeff Kirsher bit); 3302adfc5217SJeff Kirsher } 3303adfc5217SJeff Kirsher } 3304adfc5217SJeff Kirsher 3305adfc5217SJeff Kirsher static inline void bnx2x_mcast_hdl_restore_e1h(struct bnx2x *bp, 3306adfc5217SJeff Kirsher struct bnx2x_mcast_obj *o, struct bnx2x_mcast_ramrod_params *p, 3307adfc5217SJeff Kirsher u32 *mc_filter) 3308adfc5217SJeff Kirsher { 3309adfc5217SJeff Kirsher int bit; 3310adfc5217SJeff Kirsher 3311adfc5217SJeff Kirsher for (bit = bnx2x_mcast_get_next_bin(o, 0); 3312adfc5217SJeff Kirsher bit >= 0; 3313adfc5217SJeff Kirsher bit = bnx2x_mcast_get_next_bin(o, bit + 1)) { 3314adfc5217SJeff Kirsher BNX2X_57711_SET_MC_FILTER(mc_filter, bit); 3315adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "About to set bin %d\n", bit); 3316adfc5217SJeff Kirsher } 3317adfc5217SJeff Kirsher } 3318adfc5217SJeff Kirsher 331916a5fd92SYuval Mintz /* On 57711 we write the multicast MACs' approximate match 3320adfc5217SJeff Kirsher * table by directly into the TSTORM's internal RAM. So we don't 3321adfc5217SJeff Kirsher * really need to handle any tricks to make it work. 3322adfc5217SJeff Kirsher */ 3323adfc5217SJeff Kirsher static int bnx2x_mcast_setup_e1h(struct bnx2x *bp, 3324adfc5217SJeff Kirsher struct bnx2x_mcast_ramrod_params *p, 332586564c3fSYuval Mintz enum bnx2x_mcast_cmd cmd) 3326adfc5217SJeff Kirsher { 3327adfc5217SJeff Kirsher int i; 3328adfc5217SJeff Kirsher struct bnx2x_mcast_obj *o = p->mcast_obj; 3329adfc5217SJeff Kirsher struct bnx2x_raw_obj *r = &o->raw; 3330adfc5217SJeff Kirsher 3331adfc5217SJeff Kirsher /* If CLEAR_ONLY has been requested - clear the registry 3332adfc5217SJeff Kirsher * and clear a pending bit. 3333adfc5217SJeff Kirsher */ 3334adfc5217SJeff Kirsher if (!test_bit(RAMROD_DRV_CLR_ONLY, &p->ramrod_flags)) { 3335adfc5217SJeff Kirsher u32 mc_filter[MC_HASH_SIZE] = {0}; 3336adfc5217SJeff Kirsher 3337adfc5217SJeff Kirsher /* Set the multicast filter bits before writing it into 3338adfc5217SJeff Kirsher * the internal memory. 3339adfc5217SJeff Kirsher */ 3340adfc5217SJeff Kirsher switch (cmd) { 3341adfc5217SJeff Kirsher case BNX2X_MCAST_CMD_ADD: 3342adfc5217SJeff Kirsher bnx2x_mcast_hdl_add_e1h(bp, o, p, mc_filter); 3343adfc5217SJeff Kirsher break; 3344adfc5217SJeff Kirsher 3345adfc5217SJeff Kirsher case BNX2X_MCAST_CMD_DEL: 334694f05b0fSJoe Perches DP(BNX2X_MSG_SP, 334794f05b0fSJoe Perches "Invalidating multicast MACs configuration\n"); 3348adfc5217SJeff Kirsher 3349adfc5217SJeff Kirsher /* clear the registry */ 3350adfc5217SJeff Kirsher memset(o->registry.aprox_match.vec, 0, 3351adfc5217SJeff Kirsher sizeof(o->registry.aprox_match.vec)); 3352adfc5217SJeff Kirsher break; 3353adfc5217SJeff Kirsher 3354adfc5217SJeff Kirsher case BNX2X_MCAST_CMD_RESTORE: 3355adfc5217SJeff Kirsher bnx2x_mcast_hdl_restore_e1h(bp, o, p, mc_filter); 3356adfc5217SJeff Kirsher break; 3357adfc5217SJeff Kirsher 3358adfc5217SJeff Kirsher default: 3359adfc5217SJeff Kirsher BNX2X_ERR("Unknown command: %d\n", cmd); 3360adfc5217SJeff Kirsher return -EINVAL; 3361adfc5217SJeff Kirsher } 3362adfc5217SJeff Kirsher 3363adfc5217SJeff Kirsher /* Set the mcast filter in the internal memory */ 3364adfc5217SJeff Kirsher for (i = 0; i < MC_HASH_SIZE; i++) 3365adfc5217SJeff Kirsher REG_WR(bp, MC_HASH_OFFSET(bp, i), mc_filter[i]); 3366adfc5217SJeff Kirsher } else 3367adfc5217SJeff Kirsher /* clear the registry */ 3368adfc5217SJeff Kirsher memset(o->registry.aprox_match.vec, 0, 3369adfc5217SJeff Kirsher sizeof(o->registry.aprox_match.vec)); 3370adfc5217SJeff Kirsher 3371adfc5217SJeff Kirsher /* We are done */ 3372adfc5217SJeff Kirsher r->clear_pending(r); 3373adfc5217SJeff Kirsher 3374adfc5217SJeff Kirsher return 0; 3375adfc5217SJeff Kirsher } 3376adfc5217SJeff Kirsher 3377adfc5217SJeff Kirsher static int bnx2x_mcast_validate_e1(struct bnx2x *bp, 3378adfc5217SJeff Kirsher struct bnx2x_mcast_ramrod_params *p, 337986564c3fSYuval Mintz enum bnx2x_mcast_cmd cmd) 3380adfc5217SJeff Kirsher { 3381adfc5217SJeff Kirsher struct bnx2x_mcast_obj *o = p->mcast_obj; 3382adfc5217SJeff Kirsher int reg_sz = o->get_registry_size(o); 3383adfc5217SJeff Kirsher 3384adfc5217SJeff Kirsher switch (cmd) { 3385adfc5217SJeff Kirsher /* DEL command deletes all currently configured MACs */ 3386adfc5217SJeff Kirsher case BNX2X_MCAST_CMD_DEL: 3387adfc5217SJeff Kirsher o->set_registry_size(o, 0); 3388adfc5217SJeff Kirsher /* Don't break */ 3389adfc5217SJeff Kirsher 3390adfc5217SJeff Kirsher /* RESTORE command will restore the entire multicast configuration */ 3391adfc5217SJeff Kirsher case BNX2X_MCAST_CMD_RESTORE: 3392adfc5217SJeff Kirsher p->mcast_list_len = reg_sz; 3393adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "Command %d, p->mcast_list_len=%d\n", 3394adfc5217SJeff Kirsher cmd, p->mcast_list_len); 3395adfc5217SJeff Kirsher break; 3396adfc5217SJeff Kirsher 3397adfc5217SJeff Kirsher case BNX2X_MCAST_CMD_ADD: 3398adfc5217SJeff Kirsher case BNX2X_MCAST_CMD_CONT: 3399adfc5217SJeff Kirsher /* Multicast MACs on 57710 are configured as unicast MACs and 3400adfc5217SJeff Kirsher * there is only a limited number of CAM entries for that 3401adfc5217SJeff Kirsher * matter. 3402adfc5217SJeff Kirsher */ 3403adfc5217SJeff Kirsher if (p->mcast_list_len > o->max_cmd_len) { 340451c1a580SMerav Sicron BNX2X_ERR("Can't configure more than %d multicast MACs on 57710\n", 340551c1a580SMerav Sicron o->max_cmd_len); 3406adfc5217SJeff Kirsher return -EINVAL; 3407adfc5217SJeff Kirsher } 3408adfc5217SJeff Kirsher /* Every configured MAC should be cleared if DEL command is 3409adfc5217SJeff Kirsher * called. Only the last ADD command is relevant as long as 3410adfc5217SJeff Kirsher * every ADD commands overrides the previous configuration. 3411adfc5217SJeff Kirsher */ 3412adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "p->mcast_list_len=%d\n", p->mcast_list_len); 3413adfc5217SJeff Kirsher if (p->mcast_list_len > 0) 3414adfc5217SJeff Kirsher o->set_registry_size(o, p->mcast_list_len); 3415adfc5217SJeff Kirsher 3416adfc5217SJeff Kirsher break; 3417adfc5217SJeff Kirsher 3418adfc5217SJeff Kirsher default: 3419adfc5217SJeff Kirsher BNX2X_ERR("Unknown command: %d\n", cmd); 3420adfc5217SJeff Kirsher return -EINVAL; 3421adfc5217SJeff Kirsher } 3422adfc5217SJeff Kirsher 3423adfc5217SJeff Kirsher /* We want to ensure that commands are executed one by one for 57710. 3424adfc5217SJeff Kirsher * Therefore each none-empty command will consume o->max_cmd_len. 3425adfc5217SJeff Kirsher */ 3426adfc5217SJeff Kirsher if (p->mcast_list_len) 3427adfc5217SJeff Kirsher o->total_pending_num += o->max_cmd_len; 3428adfc5217SJeff Kirsher 3429adfc5217SJeff Kirsher return 0; 3430adfc5217SJeff Kirsher } 3431adfc5217SJeff Kirsher 3432adfc5217SJeff Kirsher static void bnx2x_mcast_revert_e1(struct bnx2x *bp, 3433adfc5217SJeff Kirsher struct bnx2x_mcast_ramrod_params *p, 3434adfc5217SJeff Kirsher int old_num_macs) 3435adfc5217SJeff Kirsher { 3436adfc5217SJeff Kirsher struct bnx2x_mcast_obj *o = p->mcast_obj; 3437adfc5217SJeff Kirsher 3438adfc5217SJeff Kirsher o->set_registry_size(o, old_num_macs); 3439adfc5217SJeff Kirsher 3440adfc5217SJeff Kirsher /* If current command hasn't been handled yet and we are 3441adfc5217SJeff Kirsher * here means that it's meant to be dropped and we have to 344216a5fd92SYuval Mintz * update the number of outstanding MACs accordingly. 3443adfc5217SJeff Kirsher */ 3444adfc5217SJeff Kirsher if (p->mcast_list_len) 3445adfc5217SJeff Kirsher o->total_pending_num -= o->max_cmd_len; 3446adfc5217SJeff Kirsher } 3447adfc5217SJeff Kirsher 3448adfc5217SJeff Kirsher static void bnx2x_mcast_set_one_rule_e1(struct bnx2x *bp, 3449adfc5217SJeff Kirsher struct bnx2x_mcast_obj *o, int idx, 3450adfc5217SJeff Kirsher union bnx2x_mcast_config_data *cfg_data, 345186564c3fSYuval Mintz enum bnx2x_mcast_cmd cmd) 3452adfc5217SJeff Kirsher { 3453adfc5217SJeff Kirsher struct bnx2x_raw_obj *r = &o->raw; 3454adfc5217SJeff Kirsher struct mac_configuration_cmd *data = 3455adfc5217SJeff Kirsher (struct mac_configuration_cmd *)(r->rdata); 3456adfc5217SJeff Kirsher 3457adfc5217SJeff Kirsher /* copy mac */ 3458adfc5217SJeff Kirsher if ((cmd == BNX2X_MCAST_CMD_ADD) || (cmd == BNX2X_MCAST_CMD_RESTORE)) { 3459adfc5217SJeff Kirsher bnx2x_set_fw_mac_addr(&data->config_table[idx].msb_mac_addr, 3460adfc5217SJeff Kirsher &data->config_table[idx].middle_mac_addr, 3461adfc5217SJeff Kirsher &data->config_table[idx].lsb_mac_addr, 3462adfc5217SJeff Kirsher cfg_data->mac); 3463adfc5217SJeff Kirsher 3464adfc5217SJeff Kirsher data->config_table[idx].vlan_id = 0; 3465adfc5217SJeff Kirsher data->config_table[idx].pf_id = r->func_id; 3466adfc5217SJeff Kirsher data->config_table[idx].clients_bit_vector = 3467adfc5217SJeff Kirsher cpu_to_le32(1 << r->cl_id); 3468adfc5217SJeff Kirsher 3469adfc5217SJeff Kirsher SET_FLAG(data->config_table[idx].flags, 3470adfc5217SJeff Kirsher MAC_CONFIGURATION_ENTRY_ACTION_TYPE, 3471adfc5217SJeff Kirsher T_ETH_MAC_COMMAND_SET); 3472adfc5217SJeff Kirsher } 3473adfc5217SJeff Kirsher } 3474adfc5217SJeff Kirsher 3475adfc5217SJeff Kirsher /** 3476adfc5217SJeff Kirsher * bnx2x_mcast_set_rdata_hdr_e1 - set header values in mac_configuration_cmd 3477adfc5217SJeff Kirsher * 3478adfc5217SJeff Kirsher * @bp: device handle 3479adfc5217SJeff Kirsher * @p: 3480adfc5217SJeff Kirsher * @len: number of rules to handle 3481adfc5217SJeff Kirsher */ 3482adfc5217SJeff Kirsher static inline void bnx2x_mcast_set_rdata_hdr_e1(struct bnx2x *bp, 3483adfc5217SJeff Kirsher struct bnx2x_mcast_ramrod_params *p, 3484adfc5217SJeff Kirsher u8 len) 3485adfc5217SJeff Kirsher { 3486adfc5217SJeff Kirsher struct bnx2x_raw_obj *r = &p->mcast_obj->raw; 3487adfc5217SJeff Kirsher struct mac_configuration_cmd *data = 3488adfc5217SJeff Kirsher (struct mac_configuration_cmd *)(r->rdata); 3489adfc5217SJeff Kirsher 3490adfc5217SJeff Kirsher u8 offset = (CHIP_REV_IS_SLOW(bp) ? 3491adfc5217SJeff Kirsher BNX2X_MAX_EMUL_MULTI*(1 + r->func_id) : 3492adfc5217SJeff Kirsher BNX2X_MAX_MULTICAST*(1 + r->func_id)); 3493adfc5217SJeff Kirsher 3494adfc5217SJeff Kirsher data->hdr.offset = offset; 349586564c3fSYuval Mintz data->hdr.client_id = cpu_to_le16(0xff); 349686564c3fSYuval Mintz data->hdr.echo = cpu_to_le32((r->cid & BNX2X_SWCID_MASK) | 349786564c3fSYuval Mintz (BNX2X_FILTER_MCAST_PENDING << 349886564c3fSYuval Mintz BNX2X_SWCID_SHIFT)); 3499adfc5217SJeff Kirsher data->hdr.length = len; 3500adfc5217SJeff Kirsher } 3501adfc5217SJeff Kirsher 3502adfc5217SJeff Kirsher /** 3503adfc5217SJeff Kirsher * bnx2x_mcast_handle_restore_cmd_e1 - restore command for 57710 3504adfc5217SJeff Kirsher * 3505adfc5217SJeff Kirsher * @bp: device handle 3506adfc5217SJeff Kirsher * @o: 3507adfc5217SJeff Kirsher * @start_idx: index in the registry to start from 3508adfc5217SJeff Kirsher * @rdata_idx: index in the ramrod data to start from 3509adfc5217SJeff Kirsher * 3510adfc5217SJeff Kirsher * restore command for 57710 is like all other commands - always a stand alone 3511adfc5217SJeff Kirsher * command - start_idx and rdata_idx will always be 0. This function will always 3512adfc5217SJeff Kirsher * succeed. 3513adfc5217SJeff Kirsher * returns -1 to comply with 57712 variant. 3514adfc5217SJeff Kirsher */ 3515adfc5217SJeff Kirsher static inline int bnx2x_mcast_handle_restore_cmd_e1( 3516adfc5217SJeff Kirsher struct bnx2x *bp, struct bnx2x_mcast_obj *o , int start_idx, 3517adfc5217SJeff Kirsher int *rdata_idx) 3518adfc5217SJeff Kirsher { 3519adfc5217SJeff Kirsher struct bnx2x_mcast_mac_elem *elem; 3520adfc5217SJeff Kirsher int i = 0; 352186564c3fSYuval Mintz union bnx2x_mcast_config_data cfg_data = {NULL}; 3522adfc5217SJeff Kirsher 3523adfc5217SJeff Kirsher /* go through the registry and configure the MACs from it. */ 3524adfc5217SJeff Kirsher list_for_each_entry(elem, &o->registry.exact_match.macs, link) { 3525adfc5217SJeff Kirsher cfg_data.mac = &elem->mac[0]; 3526adfc5217SJeff Kirsher o->set_one_rule(bp, o, i, &cfg_data, BNX2X_MCAST_CMD_RESTORE); 3527adfc5217SJeff Kirsher 3528adfc5217SJeff Kirsher i++; 3529adfc5217SJeff Kirsher 35300f9dad10SJoe Perches DP(BNX2X_MSG_SP, "About to configure %pM mcast MAC\n", 35310f9dad10SJoe Perches cfg_data.mac); 3532adfc5217SJeff Kirsher } 3533adfc5217SJeff Kirsher 3534adfc5217SJeff Kirsher *rdata_idx = i; 3535adfc5217SJeff Kirsher 3536adfc5217SJeff Kirsher return -1; 3537adfc5217SJeff Kirsher } 3538adfc5217SJeff Kirsher 3539adfc5217SJeff Kirsher static inline int bnx2x_mcast_handle_pending_cmds_e1( 3540adfc5217SJeff Kirsher struct bnx2x *bp, struct bnx2x_mcast_ramrod_params *p) 3541adfc5217SJeff Kirsher { 3542adfc5217SJeff Kirsher struct bnx2x_pending_mcast_cmd *cmd_pos; 3543adfc5217SJeff Kirsher struct bnx2x_mcast_mac_elem *pmac_pos; 3544adfc5217SJeff Kirsher struct bnx2x_mcast_obj *o = p->mcast_obj; 354586564c3fSYuval Mintz union bnx2x_mcast_config_data cfg_data = {NULL}; 3546adfc5217SJeff Kirsher int cnt = 0; 3547adfc5217SJeff Kirsher 3548adfc5217SJeff Kirsher /* If nothing to be done - return */ 3549adfc5217SJeff Kirsher if (list_empty(&o->pending_cmds_head)) 3550adfc5217SJeff Kirsher return 0; 3551adfc5217SJeff Kirsher 3552adfc5217SJeff Kirsher /* Handle the first command */ 3553adfc5217SJeff Kirsher cmd_pos = list_first_entry(&o->pending_cmds_head, 3554adfc5217SJeff Kirsher struct bnx2x_pending_mcast_cmd, link); 3555adfc5217SJeff Kirsher 3556adfc5217SJeff Kirsher switch (cmd_pos->type) { 3557adfc5217SJeff Kirsher case BNX2X_MCAST_CMD_ADD: 3558adfc5217SJeff Kirsher list_for_each_entry(pmac_pos, &cmd_pos->data.macs_head, link) { 3559adfc5217SJeff Kirsher cfg_data.mac = &pmac_pos->mac[0]; 3560adfc5217SJeff Kirsher o->set_one_rule(bp, o, cnt, &cfg_data, cmd_pos->type); 3561adfc5217SJeff Kirsher 3562adfc5217SJeff Kirsher cnt++; 3563adfc5217SJeff Kirsher 35640f9dad10SJoe Perches DP(BNX2X_MSG_SP, "About to configure %pM mcast MAC\n", 35650f9dad10SJoe Perches pmac_pos->mac); 3566adfc5217SJeff Kirsher } 3567adfc5217SJeff Kirsher break; 3568adfc5217SJeff Kirsher 3569adfc5217SJeff Kirsher case BNX2X_MCAST_CMD_DEL: 3570adfc5217SJeff Kirsher cnt = cmd_pos->data.macs_num; 3571adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "About to delete %d multicast MACs\n", cnt); 3572adfc5217SJeff Kirsher break; 3573adfc5217SJeff Kirsher 3574adfc5217SJeff Kirsher case BNX2X_MCAST_CMD_RESTORE: 3575adfc5217SJeff Kirsher o->hdl_restore(bp, o, 0, &cnt); 3576adfc5217SJeff Kirsher break; 3577adfc5217SJeff Kirsher 3578adfc5217SJeff Kirsher default: 3579adfc5217SJeff Kirsher BNX2X_ERR("Unknown command: %d\n", cmd_pos->type); 3580adfc5217SJeff Kirsher return -EINVAL; 3581adfc5217SJeff Kirsher } 3582adfc5217SJeff Kirsher 3583adfc5217SJeff Kirsher list_del(&cmd_pos->link); 3584adfc5217SJeff Kirsher kfree(cmd_pos); 3585adfc5217SJeff Kirsher 3586adfc5217SJeff Kirsher return cnt; 3587adfc5217SJeff Kirsher } 3588adfc5217SJeff Kirsher 3589adfc5217SJeff Kirsher /** 3590adfc5217SJeff Kirsher * bnx2x_get_fw_mac_addr - revert the bnx2x_set_fw_mac_addr(). 3591adfc5217SJeff Kirsher * 3592adfc5217SJeff Kirsher * @fw_hi: 3593adfc5217SJeff Kirsher * @fw_mid: 3594adfc5217SJeff Kirsher * @fw_lo: 3595adfc5217SJeff Kirsher * @mac: 3596adfc5217SJeff Kirsher */ 3597adfc5217SJeff Kirsher static inline void bnx2x_get_fw_mac_addr(__le16 *fw_hi, __le16 *fw_mid, 3598adfc5217SJeff Kirsher __le16 *fw_lo, u8 *mac) 3599adfc5217SJeff Kirsher { 3600adfc5217SJeff Kirsher mac[1] = ((u8 *)fw_hi)[0]; 3601adfc5217SJeff Kirsher mac[0] = ((u8 *)fw_hi)[1]; 3602adfc5217SJeff Kirsher mac[3] = ((u8 *)fw_mid)[0]; 3603adfc5217SJeff Kirsher mac[2] = ((u8 *)fw_mid)[1]; 3604adfc5217SJeff Kirsher mac[5] = ((u8 *)fw_lo)[0]; 3605adfc5217SJeff Kirsher mac[4] = ((u8 *)fw_lo)[1]; 3606adfc5217SJeff Kirsher } 3607adfc5217SJeff Kirsher 3608adfc5217SJeff Kirsher /** 3609adfc5217SJeff Kirsher * bnx2x_mcast_refresh_registry_e1 - 3610adfc5217SJeff Kirsher * 3611adfc5217SJeff Kirsher * @bp: device handle 3612adfc5217SJeff Kirsher * @cnt: 3613adfc5217SJeff Kirsher * 3614adfc5217SJeff Kirsher * Check the ramrod data first entry flag to see if it's a DELETE or ADD command 3615adfc5217SJeff Kirsher * and update the registry correspondingly: if ADD - allocate a memory and add 3616adfc5217SJeff Kirsher * the entries to the registry (list), if DELETE - clear the registry and free 3617adfc5217SJeff Kirsher * the memory. 3618adfc5217SJeff Kirsher */ 3619adfc5217SJeff Kirsher static inline int bnx2x_mcast_refresh_registry_e1(struct bnx2x *bp, 3620adfc5217SJeff Kirsher struct bnx2x_mcast_obj *o) 3621adfc5217SJeff Kirsher { 3622adfc5217SJeff Kirsher struct bnx2x_raw_obj *raw = &o->raw; 3623adfc5217SJeff Kirsher struct bnx2x_mcast_mac_elem *elem; 3624adfc5217SJeff Kirsher struct mac_configuration_cmd *data = 3625adfc5217SJeff Kirsher (struct mac_configuration_cmd *)(raw->rdata); 3626adfc5217SJeff Kirsher 3627adfc5217SJeff Kirsher /* If first entry contains a SET bit - the command was ADD, 3628adfc5217SJeff Kirsher * otherwise - DEL_ALL 3629adfc5217SJeff Kirsher */ 3630adfc5217SJeff Kirsher if (GET_FLAG(data->config_table[0].flags, 3631adfc5217SJeff Kirsher MAC_CONFIGURATION_ENTRY_ACTION_TYPE)) { 3632adfc5217SJeff Kirsher int i, len = data->hdr.length; 3633adfc5217SJeff Kirsher 3634adfc5217SJeff Kirsher /* Break if it was a RESTORE command */ 3635adfc5217SJeff Kirsher if (!list_empty(&o->registry.exact_match.macs)) 3636adfc5217SJeff Kirsher return 0; 3637adfc5217SJeff Kirsher 363801e23742SThomas Meyer elem = kcalloc(len, sizeof(*elem), GFP_ATOMIC); 3639adfc5217SJeff Kirsher if (!elem) { 3640adfc5217SJeff Kirsher BNX2X_ERR("Failed to allocate registry memory\n"); 3641adfc5217SJeff Kirsher return -ENOMEM; 3642adfc5217SJeff Kirsher } 3643adfc5217SJeff Kirsher 3644adfc5217SJeff Kirsher for (i = 0; i < len; i++, elem++) { 3645adfc5217SJeff Kirsher bnx2x_get_fw_mac_addr( 3646adfc5217SJeff Kirsher &data->config_table[i].msb_mac_addr, 3647adfc5217SJeff Kirsher &data->config_table[i].middle_mac_addr, 3648adfc5217SJeff Kirsher &data->config_table[i].lsb_mac_addr, 3649adfc5217SJeff Kirsher elem->mac); 36500f9dad10SJoe Perches DP(BNX2X_MSG_SP, "Adding registry entry for [%pM]\n", 36510f9dad10SJoe Perches elem->mac); 3652adfc5217SJeff Kirsher list_add_tail(&elem->link, 3653adfc5217SJeff Kirsher &o->registry.exact_match.macs); 3654adfc5217SJeff Kirsher } 3655adfc5217SJeff Kirsher } else { 3656adfc5217SJeff Kirsher elem = list_first_entry(&o->registry.exact_match.macs, 3657adfc5217SJeff Kirsher struct bnx2x_mcast_mac_elem, link); 3658adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "Deleting a registry\n"); 3659adfc5217SJeff Kirsher kfree(elem); 3660adfc5217SJeff Kirsher INIT_LIST_HEAD(&o->registry.exact_match.macs); 3661adfc5217SJeff Kirsher } 3662adfc5217SJeff Kirsher 3663adfc5217SJeff Kirsher return 0; 3664adfc5217SJeff Kirsher } 3665adfc5217SJeff Kirsher 3666adfc5217SJeff Kirsher static int bnx2x_mcast_setup_e1(struct bnx2x *bp, 3667adfc5217SJeff Kirsher struct bnx2x_mcast_ramrod_params *p, 366886564c3fSYuval Mintz enum bnx2x_mcast_cmd cmd) 3669adfc5217SJeff Kirsher { 3670adfc5217SJeff Kirsher struct bnx2x_mcast_obj *o = p->mcast_obj; 3671adfc5217SJeff Kirsher struct bnx2x_raw_obj *raw = &o->raw; 3672adfc5217SJeff Kirsher struct mac_configuration_cmd *data = 3673adfc5217SJeff Kirsher (struct mac_configuration_cmd *)(raw->rdata); 3674adfc5217SJeff Kirsher int cnt = 0, i, rc; 3675adfc5217SJeff Kirsher 3676adfc5217SJeff Kirsher /* Reset the ramrod data buffer */ 3677adfc5217SJeff Kirsher memset(data, 0, sizeof(*data)); 3678adfc5217SJeff Kirsher 3679adfc5217SJeff Kirsher /* First set all entries as invalid */ 3680adfc5217SJeff Kirsher for (i = 0; i < o->max_cmd_len ; i++) 3681adfc5217SJeff Kirsher SET_FLAG(data->config_table[i].flags, 3682adfc5217SJeff Kirsher MAC_CONFIGURATION_ENTRY_ACTION_TYPE, 3683adfc5217SJeff Kirsher T_ETH_MAC_COMMAND_INVALIDATE); 3684adfc5217SJeff Kirsher 3685adfc5217SJeff Kirsher /* Handle pending commands first */ 3686adfc5217SJeff Kirsher cnt = bnx2x_mcast_handle_pending_cmds_e1(bp, p); 3687adfc5217SJeff Kirsher 3688adfc5217SJeff Kirsher /* If there are no more pending commands - clear SCHEDULED state */ 3689adfc5217SJeff Kirsher if (list_empty(&o->pending_cmds_head)) 3690adfc5217SJeff Kirsher o->clear_sched(o); 3691adfc5217SJeff Kirsher 3692adfc5217SJeff Kirsher /* The below may be true iff there were no pending commands */ 3693adfc5217SJeff Kirsher if (!cnt) 3694adfc5217SJeff Kirsher cnt = bnx2x_mcast_handle_current_cmd(bp, p, cmd, 0); 3695adfc5217SJeff Kirsher 3696adfc5217SJeff Kirsher /* For 57710 every command has o->max_cmd_len length to ensure that 3697adfc5217SJeff Kirsher * commands are done one at a time. 3698adfc5217SJeff Kirsher */ 3699adfc5217SJeff Kirsher o->total_pending_num -= o->max_cmd_len; 3700adfc5217SJeff Kirsher 3701adfc5217SJeff Kirsher /* send a ramrod */ 3702adfc5217SJeff Kirsher 3703adfc5217SJeff Kirsher WARN_ON(cnt > o->max_cmd_len); 3704adfc5217SJeff Kirsher 3705adfc5217SJeff Kirsher /* Set ramrod header (in particular, a number of entries to update) */ 3706adfc5217SJeff Kirsher bnx2x_mcast_set_rdata_hdr_e1(bp, p, (u8)cnt); 3707adfc5217SJeff Kirsher 3708adfc5217SJeff Kirsher /* update a registry: we need the registry contents to be always up 3709adfc5217SJeff Kirsher * to date in order to be able to execute a RESTORE opcode. Here 3710adfc5217SJeff Kirsher * we use the fact that for 57710 we sent one command at a time 3711adfc5217SJeff Kirsher * hence we may take the registry update out of the command handling 3712adfc5217SJeff Kirsher * and do it in a simpler way here. 3713adfc5217SJeff Kirsher */ 3714adfc5217SJeff Kirsher rc = bnx2x_mcast_refresh_registry_e1(bp, o); 3715adfc5217SJeff Kirsher if (rc) 3716adfc5217SJeff Kirsher return rc; 3717adfc5217SJeff Kirsher 371816a5fd92SYuval Mintz /* If CLEAR_ONLY was requested - don't send a ramrod and clear 3719adfc5217SJeff Kirsher * RAMROD_PENDING status immediately. 3720adfc5217SJeff Kirsher */ 3721adfc5217SJeff Kirsher if (test_bit(RAMROD_DRV_CLR_ONLY, &p->ramrod_flags)) { 3722adfc5217SJeff Kirsher raw->clear_pending(raw); 3723adfc5217SJeff Kirsher return 0; 3724adfc5217SJeff Kirsher } else { 372516a5fd92SYuval Mintz /* No need for an explicit memory barrier here as long we would 3726adfc5217SJeff Kirsher * need to ensure the ordering of writing to the SPQ element 3727adfc5217SJeff Kirsher * and updating of the SPQ producer which involves a memory 3728adfc5217SJeff Kirsher * read and we will have to put a full memory barrier there 3729adfc5217SJeff Kirsher * (inside bnx2x_sp_post()). 3730adfc5217SJeff Kirsher */ 3731adfc5217SJeff Kirsher 3732adfc5217SJeff Kirsher /* Send a ramrod */ 3733adfc5217SJeff Kirsher rc = bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_SET_MAC, raw->cid, 3734adfc5217SJeff Kirsher U64_HI(raw->rdata_mapping), 3735adfc5217SJeff Kirsher U64_LO(raw->rdata_mapping), 3736adfc5217SJeff Kirsher ETH_CONNECTION_TYPE); 3737adfc5217SJeff Kirsher if (rc) 3738adfc5217SJeff Kirsher return rc; 3739adfc5217SJeff Kirsher 3740adfc5217SJeff Kirsher /* Ramrod completion is pending */ 3741adfc5217SJeff Kirsher return 1; 3742adfc5217SJeff Kirsher } 3743adfc5217SJeff Kirsher } 3744adfc5217SJeff Kirsher 3745adfc5217SJeff Kirsher static int bnx2x_mcast_get_registry_size_exact(struct bnx2x_mcast_obj *o) 3746adfc5217SJeff Kirsher { 3747adfc5217SJeff Kirsher return o->registry.exact_match.num_macs_set; 3748adfc5217SJeff Kirsher } 3749adfc5217SJeff Kirsher 3750adfc5217SJeff Kirsher static int bnx2x_mcast_get_registry_size_aprox(struct bnx2x_mcast_obj *o) 3751adfc5217SJeff Kirsher { 3752adfc5217SJeff Kirsher return o->registry.aprox_match.num_bins_set; 3753adfc5217SJeff Kirsher } 3754adfc5217SJeff Kirsher 3755adfc5217SJeff Kirsher static void bnx2x_mcast_set_registry_size_exact(struct bnx2x_mcast_obj *o, 3756adfc5217SJeff Kirsher int n) 3757adfc5217SJeff Kirsher { 3758adfc5217SJeff Kirsher o->registry.exact_match.num_macs_set = n; 3759adfc5217SJeff Kirsher } 3760adfc5217SJeff Kirsher 3761adfc5217SJeff Kirsher static void bnx2x_mcast_set_registry_size_aprox(struct bnx2x_mcast_obj *o, 3762adfc5217SJeff Kirsher int n) 3763adfc5217SJeff Kirsher { 3764adfc5217SJeff Kirsher o->registry.aprox_match.num_bins_set = n; 3765adfc5217SJeff Kirsher } 3766adfc5217SJeff Kirsher 3767adfc5217SJeff Kirsher int bnx2x_config_mcast(struct bnx2x *bp, 3768adfc5217SJeff Kirsher struct bnx2x_mcast_ramrod_params *p, 376986564c3fSYuval Mintz enum bnx2x_mcast_cmd cmd) 3770adfc5217SJeff Kirsher { 3771adfc5217SJeff Kirsher struct bnx2x_mcast_obj *o = p->mcast_obj; 3772adfc5217SJeff Kirsher struct bnx2x_raw_obj *r = &o->raw; 3773adfc5217SJeff Kirsher int rc = 0, old_reg_size; 3774adfc5217SJeff Kirsher 3775adfc5217SJeff Kirsher /* This is needed to recover number of currently configured mcast macs 3776adfc5217SJeff Kirsher * in case of failure. 3777adfc5217SJeff Kirsher */ 3778adfc5217SJeff Kirsher old_reg_size = o->get_registry_size(o); 3779adfc5217SJeff Kirsher 3780adfc5217SJeff Kirsher /* Do some calculations and checks */ 3781adfc5217SJeff Kirsher rc = o->validate(bp, p, cmd); 3782adfc5217SJeff Kirsher if (rc) 3783adfc5217SJeff Kirsher return rc; 3784adfc5217SJeff Kirsher 3785adfc5217SJeff Kirsher /* Return if there is no work to do */ 3786adfc5217SJeff Kirsher if ((!p->mcast_list_len) && (!o->check_sched(o))) 3787adfc5217SJeff Kirsher return 0; 3788adfc5217SJeff Kirsher 378951c1a580SMerav Sicron DP(BNX2X_MSG_SP, "o->total_pending_num=%d p->mcast_list_len=%d o->max_cmd_len=%d\n", 379051c1a580SMerav Sicron o->total_pending_num, p->mcast_list_len, o->max_cmd_len); 3791adfc5217SJeff Kirsher 3792adfc5217SJeff Kirsher /* Enqueue the current command to the pending list if we can't complete 3793adfc5217SJeff Kirsher * it in the current iteration 3794adfc5217SJeff Kirsher */ 3795adfc5217SJeff Kirsher if (r->check_pending(r) || 3796adfc5217SJeff Kirsher ((o->max_cmd_len > 0) && (o->total_pending_num > o->max_cmd_len))) { 3797adfc5217SJeff Kirsher rc = o->enqueue_cmd(bp, p->mcast_obj, p, cmd); 3798adfc5217SJeff Kirsher if (rc < 0) 3799adfc5217SJeff Kirsher goto error_exit1; 3800adfc5217SJeff Kirsher 3801adfc5217SJeff Kirsher /* As long as the current command is in a command list we 3802adfc5217SJeff Kirsher * don't need to handle it separately. 3803adfc5217SJeff Kirsher */ 3804adfc5217SJeff Kirsher p->mcast_list_len = 0; 3805adfc5217SJeff Kirsher } 3806adfc5217SJeff Kirsher 3807adfc5217SJeff Kirsher if (!r->check_pending(r)) { 3808adfc5217SJeff Kirsher 3809adfc5217SJeff Kirsher /* Set 'pending' state */ 3810adfc5217SJeff Kirsher r->set_pending(r); 3811adfc5217SJeff Kirsher 3812adfc5217SJeff Kirsher /* Configure the new classification in the chip */ 3813adfc5217SJeff Kirsher rc = o->config_mcast(bp, p, cmd); 3814adfc5217SJeff Kirsher if (rc < 0) 3815adfc5217SJeff Kirsher goto error_exit2; 3816adfc5217SJeff Kirsher 3817adfc5217SJeff Kirsher /* Wait for a ramrod completion if was requested */ 3818adfc5217SJeff Kirsher if (test_bit(RAMROD_COMP_WAIT, &p->ramrod_flags)) 3819adfc5217SJeff Kirsher rc = o->wait_comp(bp, o); 3820adfc5217SJeff Kirsher } 3821adfc5217SJeff Kirsher 3822adfc5217SJeff Kirsher return rc; 3823adfc5217SJeff Kirsher 3824adfc5217SJeff Kirsher error_exit2: 3825adfc5217SJeff Kirsher r->clear_pending(r); 3826adfc5217SJeff Kirsher 3827adfc5217SJeff Kirsher error_exit1: 3828adfc5217SJeff Kirsher o->revert(bp, p, old_reg_size); 3829adfc5217SJeff Kirsher 3830adfc5217SJeff Kirsher return rc; 3831adfc5217SJeff Kirsher } 3832adfc5217SJeff Kirsher 3833adfc5217SJeff Kirsher static void bnx2x_mcast_clear_sched(struct bnx2x_mcast_obj *o) 3834adfc5217SJeff Kirsher { 3835adfc5217SJeff Kirsher smp_mb__before_clear_bit(); 3836adfc5217SJeff Kirsher clear_bit(o->sched_state, o->raw.pstate); 3837adfc5217SJeff Kirsher smp_mb__after_clear_bit(); 3838adfc5217SJeff Kirsher } 3839adfc5217SJeff Kirsher 3840adfc5217SJeff Kirsher static void bnx2x_mcast_set_sched(struct bnx2x_mcast_obj *o) 3841adfc5217SJeff Kirsher { 3842adfc5217SJeff Kirsher smp_mb__before_clear_bit(); 3843adfc5217SJeff Kirsher set_bit(o->sched_state, o->raw.pstate); 3844adfc5217SJeff Kirsher smp_mb__after_clear_bit(); 3845adfc5217SJeff Kirsher } 3846adfc5217SJeff Kirsher 3847adfc5217SJeff Kirsher static bool bnx2x_mcast_check_sched(struct bnx2x_mcast_obj *o) 3848adfc5217SJeff Kirsher { 3849adfc5217SJeff Kirsher return !!test_bit(o->sched_state, o->raw.pstate); 3850adfc5217SJeff Kirsher } 3851adfc5217SJeff Kirsher 3852adfc5217SJeff Kirsher static bool bnx2x_mcast_check_pending(struct bnx2x_mcast_obj *o) 3853adfc5217SJeff Kirsher { 3854adfc5217SJeff Kirsher return o->raw.check_pending(&o->raw) || o->check_sched(o); 3855adfc5217SJeff Kirsher } 3856adfc5217SJeff Kirsher 3857adfc5217SJeff Kirsher void bnx2x_init_mcast_obj(struct bnx2x *bp, 3858adfc5217SJeff Kirsher struct bnx2x_mcast_obj *mcast_obj, 3859adfc5217SJeff Kirsher u8 mcast_cl_id, u32 mcast_cid, u8 func_id, 3860adfc5217SJeff Kirsher u8 engine_id, void *rdata, dma_addr_t rdata_mapping, 3861adfc5217SJeff Kirsher int state, unsigned long *pstate, bnx2x_obj_type type) 3862adfc5217SJeff Kirsher { 3863adfc5217SJeff Kirsher memset(mcast_obj, 0, sizeof(*mcast_obj)); 3864adfc5217SJeff Kirsher 3865adfc5217SJeff Kirsher bnx2x_init_raw_obj(&mcast_obj->raw, mcast_cl_id, mcast_cid, func_id, 3866adfc5217SJeff Kirsher rdata, rdata_mapping, state, pstate, type); 3867adfc5217SJeff Kirsher 3868adfc5217SJeff Kirsher mcast_obj->engine_id = engine_id; 3869adfc5217SJeff Kirsher 3870adfc5217SJeff Kirsher INIT_LIST_HEAD(&mcast_obj->pending_cmds_head); 3871adfc5217SJeff Kirsher 3872adfc5217SJeff Kirsher mcast_obj->sched_state = BNX2X_FILTER_MCAST_SCHED; 3873adfc5217SJeff Kirsher mcast_obj->check_sched = bnx2x_mcast_check_sched; 3874adfc5217SJeff Kirsher mcast_obj->set_sched = bnx2x_mcast_set_sched; 3875adfc5217SJeff Kirsher mcast_obj->clear_sched = bnx2x_mcast_clear_sched; 3876adfc5217SJeff Kirsher 3877adfc5217SJeff Kirsher if (CHIP_IS_E1(bp)) { 3878adfc5217SJeff Kirsher mcast_obj->config_mcast = bnx2x_mcast_setup_e1; 3879adfc5217SJeff Kirsher mcast_obj->enqueue_cmd = bnx2x_mcast_enqueue_cmd; 3880adfc5217SJeff Kirsher mcast_obj->hdl_restore = 3881adfc5217SJeff Kirsher bnx2x_mcast_handle_restore_cmd_e1; 3882adfc5217SJeff Kirsher mcast_obj->check_pending = bnx2x_mcast_check_pending; 3883adfc5217SJeff Kirsher 3884adfc5217SJeff Kirsher if (CHIP_REV_IS_SLOW(bp)) 3885adfc5217SJeff Kirsher mcast_obj->max_cmd_len = BNX2X_MAX_EMUL_MULTI; 3886adfc5217SJeff Kirsher else 3887adfc5217SJeff Kirsher mcast_obj->max_cmd_len = BNX2X_MAX_MULTICAST; 3888adfc5217SJeff Kirsher 3889adfc5217SJeff Kirsher mcast_obj->wait_comp = bnx2x_mcast_wait; 3890adfc5217SJeff Kirsher mcast_obj->set_one_rule = bnx2x_mcast_set_one_rule_e1; 3891adfc5217SJeff Kirsher mcast_obj->validate = bnx2x_mcast_validate_e1; 3892adfc5217SJeff Kirsher mcast_obj->revert = bnx2x_mcast_revert_e1; 3893adfc5217SJeff Kirsher mcast_obj->get_registry_size = 3894adfc5217SJeff Kirsher bnx2x_mcast_get_registry_size_exact; 3895adfc5217SJeff Kirsher mcast_obj->set_registry_size = 3896adfc5217SJeff Kirsher bnx2x_mcast_set_registry_size_exact; 3897adfc5217SJeff Kirsher 3898adfc5217SJeff Kirsher /* 57710 is the only chip that uses the exact match for mcast 3899adfc5217SJeff Kirsher * at the moment. 3900adfc5217SJeff Kirsher */ 3901adfc5217SJeff Kirsher INIT_LIST_HEAD(&mcast_obj->registry.exact_match.macs); 3902adfc5217SJeff Kirsher 3903adfc5217SJeff Kirsher } else if (CHIP_IS_E1H(bp)) { 3904adfc5217SJeff Kirsher mcast_obj->config_mcast = bnx2x_mcast_setup_e1h; 3905adfc5217SJeff Kirsher mcast_obj->enqueue_cmd = NULL; 3906adfc5217SJeff Kirsher mcast_obj->hdl_restore = NULL; 3907adfc5217SJeff Kirsher mcast_obj->check_pending = bnx2x_mcast_check_pending; 3908adfc5217SJeff Kirsher 3909adfc5217SJeff Kirsher /* 57711 doesn't send a ramrod, so it has unlimited credit 3910adfc5217SJeff Kirsher * for one command. 3911adfc5217SJeff Kirsher */ 3912adfc5217SJeff Kirsher mcast_obj->max_cmd_len = -1; 3913adfc5217SJeff Kirsher mcast_obj->wait_comp = bnx2x_mcast_wait; 3914adfc5217SJeff Kirsher mcast_obj->set_one_rule = NULL; 3915adfc5217SJeff Kirsher mcast_obj->validate = bnx2x_mcast_validate_e1h; 3916adfc5217SJeff Kirsher mcast_obj->revert = bnx2x_mcast_revert_e1h; 3917adfc5217SJeff Kirsher mcast_obj->get_registry_size = 3918adfc5217SJeff Kirsher bnx2x_mcast_get_registry_size_aprox; 3919adfc5217SJeff Kirsher mcast_obj->set_registry_size = 3920adfc5217SJeff Kirsher bnx2x_mcast_set_registry_size_aprox; 3921adfc5217SJeff Kirsher } else { 3922adfc5217SJeff Kirsher mcast_obj->config_mcast = bnx2x_mcast_setup_e2; 3923adfc5217SJeff Kirsher mcast_obj->enqueue_cmd = bnx2x_mcast_enqueue_cmd; 3924adfc5217SJeff Kirsher mcast_obj->hdl_restore = 3925adfc5217SJeff Kirsher bnx2x_mcast_handle_restore_cmd_e2; 3926adfc5217SJeff Kirsher mcast_obj->check_pending = bnx2x_mcast_check_pending; 3927adfc5217SJeff Kirsher /* TODO: There should be a proper HSI define for this number!!! 3928adfc5217SJeff Kirsher */ 3929adfc5217SJeff Kirsher mcast_obj->max_cmd_len = 16; 3930adfc5217SJeff Kirsher mcast_obj->wait_comp = bnx2x_mcast_wait; 3931adfc5217SJeff Kirsher mcast_obj->set_one_rule = bnx2x_mcast_set_one_rule_e2; 3932adfc5217SJeff Kirsher mcast_obj->validate = bnx2x_mcast_validate_e2; 3933adfc5217SJeff Kirsher mcast_obj->revert = bnx2x_mcast_revert_e2; 3934adfc5217SJeff Kirsher mcast_obj->get_registry_size = 3935adfc5217SJeff Kirsher bnx2x_mcast_get_registry_size_aprox; 3936adfc5217SJeff Kirsher mcast_obj->set_registry_size = 3937adfc5217SJeff Kirsher bnx2x_mcast_set_registry_size_aprox; 3938adfc5217SJeff Kirsher } 3939adfc5217SJeff Kirsher } 3940adfc5217SJeff Kirsher 3941adfc5217SJeff Kirsher /*************************** Credit handling **********************************/ 3942adfc5217SJeff Kirsher 3943adfc5217SJeff Kirsher /** 3944adfc5217SJeff Kirsher * atomic_add_ifless - add if the result is less than a given value. 3945adfc5217SJeff Kirsher * 3946adfc5217SJeff Kirsher * @v: pointer of type atomic_t 3947adfc5217SJeff Kirsher * @a: the amount to add to v... 3948adfc5217SJeff Kirsher * @u: ...if (v + a) is less than u. 3949adfc5217SJeff Kirsher * 3950adfc5217SJeff Kirsher * returns true if (v + a) was less than u, and false otherwise. 3951adfc5217SJeff Kirsher * 3952adfc5217SJeff Kirsher */ 3953adfc5217SJeff Kirsher static inline bool __atomic_add_ifless(atomic_t *v, int a, int u) 3954adfc5217SJeff Kirsher { 3955adfc5217SJeff Kirsher int c, old; 3956adfc5217SJeff Kirsher 3957adfc5217SJeff Kirsher c = atomic_read(v); 3958adfc5217SJeff Kirsher for (;;) { 3959adfc5217SJeff Kirsher if (unlikely(c + a >= u)) 3960adfc5217SJeff Kirsher return false; 3961adfc5217SJeff Kirsher 3962adfc5217SJeff Kirsher old = atomic_cmpxchg((v), c, c + a); 3963adfc5217SJeff Kirsher if (likely(old == c)) 3964adfc5217SJeff Kirsher break; 3965adfc5217SJeff Kirsher c = old; 3966adfc5217SJeff Kirsher } 3967adfc5217SJeff Kirsher 3968adfc5217SJeff Kirsher return true; 3969adfc5217SJeff Kirsher } 3970adfc5217SJeff Kirsher 3971adfc5217SJeff Kirsher /** 3972adfc5217SJeff Kirsher * atomic_dec_ifmoe - dec if the result is more or equal than a given value. 3973adfc5217SJeff Kirsher * 3974adfc5217SJeff Kirsher * @v: pointer of type atomic_t 3975adfc5217SJeff Kirsher * @a: the amount to dec from v... 3976adfc5217SJeff Kirsher * @u: ...if (v - a) is more or equal than u. 3977adfc5217SJeff Kirsher * 3978adfc5217SJeff Kirsher * returns true if (v - a) was more or equal than u, and false 3979adfc5217SJeff Kirsher * otherwise. 3980adfc5217SJeff Kirsher */ 3981adfc5217SJeff Kirsher static inline bool __atomic_dec_ifmoe(atomic_t *v, int a, int u) 3982adfc5217SJeff Kirsher { 3983adfc5217SJeff Kirsher int c, old; 3984adfc5217SJeff Kirsher 3985adfc5217SJeff Kirsher c = atomic_read(v); 3986adfc5217SJeff Kirsher for (;;) { 3987adfc5217SJeff Kirsher if (unlikely(c - a < u)) 3988adfc5217SJeff Kirsher return false; 3989adfc5217SJeff Kirsher 3990adfc5217SJeff Kirsher old = atomic_cmpxchg((v), c, c - a); 3991adfc5217SJeff Kirsher if (likely(old == c)) 3992adfc5217SJeff Kirsher break; 3993adfc5217SJeff Kirsher c = old; 3994adfc5217SJeff Kirsher } 3995adfc5217SJeff Kirsher 3996adfc5217SJeff Kirsher return true; 3997adfc5217SJeff Kirsher } 3998adfc5217SJeff Kirsher 3999adfc5217SJeff Kirsher static bool bnx2x_credit_pool_get(struct bnx2x_credit_pool_obj *o, int cnt) 4000adfc5217SJeff Kirsher { 4001adfc5217SJeff Kirsher bool rc; 4002adfc5217SJeff Kirsher 4003adfc5217SJeff Kirsher smp_mb(); 4004adfc5217SJeff Kirsher rc = __atomic_dec_ifmoe(&o->credit, cnt, 0); 4005adfc5217SJeff Kirsher smp_mb(); 4006adfc5217SJeff Kirsher 4007adfc5217SJeff Kirsher return rc; 4008adfc5217SJeff Kirsher } 4009adfc5217SJeff Kirsher 4010adfc5217SJeff Kirsher static bool bnx2x_credit_pool_put(struct bnx2x_credit_pool_obj *o, int cnt) 4011adfc5217SJeff Kirsher { 4012adfc5217SJeff Kirsher bool rc; 4013adfc5217SJeff Kirsher 4014adfc5217SJeff Kirsher smp_mb(); 4015adfc5217SJeff Kirsher 4016adfc5217SJeff Kirsher /* Don't let to refill if credit + cnt > pool_sz */ 4017adfc5217SJeff Kirsher rc = __atomic_add_ifless(&o->credit, cnt, o->pool_sz + 1); 4018adfc5217SJeff Kirsher 4019adfc5217SJeff Kirsher smp_mb(); 4020adfc5217SJeff Kirsher 4021adfc5217SJeff Kirsher return rc; 4022adfc5217SJeff Kirsher } 4023adfc5217SJeff Kirsher 4024adfc5217SJeff Kirsher static int bnx2x_credit_pool_check(struct bnx2x_credit_pool_obj *o) 4025adfc5217SJeff Kirsher { 4026adfc5217SJeff Kirsher int cur_credit; 4027adfc5217SJeff Kirsher 4028adfc5217SJeff Kirsher smp_mb(); 4029adfc5217SJeff Kirsher cur_credit = atomic_read(&o->credit); 4030adfc5217SJeff Kirsher 4031adfc5217SJeff Kirsher return cur_credit; 4032adfc5217SJeff Kirsher } 4033adfc5217SJeff Kirsher 4034adfc5217SJeff Kirsher static bool bnx2x_credit_pool_always_true(struct bnx2x_credit_pool_obj *o, 4035adfc5217SJeff Kirsher int cnt) 4036adfc5217SJeff Kirsher { 4037adfc5217SJeff Kirsher return true; 4038adfc5217SJeff Kirsher } 4039adfc5217SJeff Kirsher 4040adfc5217SJeff Kirsher static bool bnx2x_credit_pool_get_entry( 4041adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *o, 4042adfc5217SJeff Kirsher int *offset) 4043adfc5217SJeff Kirsher { 4044adfc5217SJeff Kirsher int idx, vec, i; 4045adfc5217SJeff Kirsher 4046adfc5217SJeff Kirsher *offset = -1; 4047adfc5217SJeff Kirsher 4048adfc5217SJeff Kirsher /* Find "internal cam-offset" then add to base for this object... */ 4049adfc5217SJeff Kirsher for (vec = 0; vec < BNX2X_POOL_VEC_SIZE; vec++) { 4050adfc5217SJeff Kirsher 4051adfc5217SJeff Kirsher /* Skip the current vector if there are no free entries in it */ 4052adfc5217SJeff Kirsher if (!o->pool_mirror[vec]) 4053adfc5217SJeff Kirsher continue; 4054adfc5217SJeff Kirsher 4055adfc5217SJeff Kirsher /* If we've got here we are going to find a free entry */ 4056c54e9bd3SDmitry Kravkov for (idx = vec * BIT_VEC64_ELEM_SZ, i = 0; 4057adfc5217SJeff Kirsher i < BIT_VEC64_ELEM_SZ; idx++, i++) 4058adfc5217SJeff Kirsher 4059adfc5217SJeff Kirsher if (BIT_VEC64_TEST_BIT(o->pool_mirror, idx)) { 4060adfc5217SJeff Kirsher /* Got one!! */ 4061adfc5217SJeff Kirsher BIT_VEC64_CLEAR_BIT(o->pool_mirror, idx); 4062adfc5217SJeff Kirsher *offset = o->base_pool_offset + idx; 4063adfc5217SJeff Kirsher return true; 4064adfc5217SJeff Kirsher } 4065adfc5217SJeff Kirsher } 4066adfc5217SJeff Kirsher 4067adfc5217SJeff Kirsher return false; 4068adfc5217SJeff Kirsher } 4069adfc5217SJeff Kirsher 4070adfc5217SJeff Kirsher static bool bnx2x_credit_pool_put_entry( 4071adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *o, 4072adfc5217SJeff Kirsher int offset) 4073adfc5217SJeff Kirsher { 4074adfc5217SJeff Kirsher if (offset < o->base_pool_offset) 4075adfc5217SJeff Kirsher return false; 4076adfc5217SJeff Kirsher 4077adfc5217SJeff Kirsher offset -= o->base_pool_offset; 4078adfc5217SJeff Kirsher 4079adfc5217SJeff Kirsher if (offset >= o->pool_sz) 4080adfc5217SJeff Kirsher return false; 4081adfc5217SJeff Kirsher 4082adfc5217SJeff Kirsher /* Return the entry to the pool */ 4083adfc5217SJeff Kirsher BIT_VEC64_SET_BIT(o->pool_mirror, offset); 4084adfc5217SJeff Kirsher 4085adfc5217SJeff Kirsher return true; 4086adfc5217SJeff Kirsher } 4087adfc5217SJeff Kirsher 4088adfc5217SJeff Kirsher static bool bnx2x_credit_pool_put_entry_always_true( 4089adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *o, 4090adfc5217SJeff Kirsher int offset) 4091adfc5217SJeff Kirsher { 4092adfc5217SJeff Kirsher return true; 4093adfc5217SJeff Kirsher } 4094adfc5217SJeff Kirsher 4095adfc5217SJeff Kirsher static bool bnx2x_credit_pool_get_entry_always_true( 4096adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *o, 4097adfc5217SJeff Kirsher int *offset) 4098adfc5217SJeff Kirsher { 4099adfc5217SJeff Kirsher *offset = -1; 4100adfc5217SJeff Kirsher return true; 4101adfc5217SJeff Kirsher } 4102adfc5217SJeff Kirsher /** 4103adfc5217SJeff Kirsher * bnx2x_init_credit_pool - initialize credit pool internals. 4104adfc5217SJeff Kirsher * 4105adfc5217SJeff Kirsher * @p: 4106adfc5217SJeff Kirsher * @base: Base entry in the CAM to use. 4107adfc5217SJeff Kirsher * @credit: pool size. 4108adfc5217SJeff Kirsher * 4109adfc5217SJeff Kirsher * If base is negative no CAM entries handling will be performed. 4110adfc5217SJeff Kirsher * If credit is negative pool operations will always succeed (unlimited pool). 4111adfc5217SJeff Kirsher * 4112adfc5217SJeff Kirsher */ 4113adfc5217SJeff Kirsher static inline void bnx2x_init_credit_pool(struct bnx2x_credit_pool_obj *p, 4114adfc5217SJeff Kirsher int base, int credit) 4115adfc5217SJeff Kirsher { 4116adfc5217SJeff Kirsher /* Zero the object first */ 4117adfc5217SJeff Kirsher memset(p, 0, sizeof(*p)); 4118adfc5217SJeff Kirsher 4119adfc5217SJeff Kirsher /* Set the table to all 1s */ 4120adfc5217SJeff Kirsher memset(&p->pool_mirror, 0xff, sizeof(p->pool_mirror)); 4121adfc5217SJeff Kirsher 4122adfc5217SJeff Kirsher /* Init a pool as full */ 4123adfc5217SJeff Kirsher atomic_set(&p->credit, credit); 4124adfc5217SJeff Kirsher 4125adfc5217SJeff Kirsher /* The total poll size */ 4126adfc5217SJeff Kirsher p->pool_sz = credit; 4127adfc5217SJeff Kirsher 4128adfc5217SJeff Kirsher p->base_pool_offset = base; 4129adfc5217SJeff Kirsher 4130adfc5217SJeff Kirsher /* Commit the change */ 4131adfc5217SJeff Kirsher smp_mb(); 4132adfc5217SJeff Kirsher 4133adfc5217SJeff Kirsher p->check = bnx2x_credit_pool_check; 4134adfc5217SJeff Kirsher 4135adfc5217SJeff Kirsher /* if pool credit is negative - disable the checks */ 4136adfc5217SJeff Kirsher if (credit >= 0) { 4137adfc5217SJeff Kirsher p->put = bnx2x_credit_pool_put; 4138adfc5217SJeff Kirsher p->get = bnx2x_credit_pool_get; 4139adfc5217SJeff Kirsher p->put_entry = bnx2x_credit_pool_put_entry; 4140adfc5217SJeff Kirsher p->get_entry = bnx2x_credit_pool_get_entry; 4141adfc5217SJeff Kirsher } else { 4142adfc5217SJeff Kirsher p->put = bnx2x_credit_pool_always_true; 4143adfc5217SJeff Kirsher p->get = bnx2x_credit_pool_always_true; 4144adfc5217SJeff Kirsher p->put_entry = bnx2x_credit_pool_put_entry_always_true; 4145adfc5217SJeff Kirsher p->get_entry = bnx2x_credit_pool_get_entry_always_true; 4146adfc5217SJeff Kirsher } 4147adfc5217SJeff Kirsher 4148adfc5217SJeff Kirsher /* If base is negative - disable entries handling */ 4149adfc5217SJeff Kirsher if (base < 0) { 4150adfc5217SJeff Kirsher p->put_entry = bnx2x_credit_pool_put_entry_always_true; 4151adfc5217SJeff Kirsher p->get_entry = bnx2x_credit_pool_get_entry_always_true; 4152adfc5217SJeff Kirsher } 4153adfc5217SJeff Kirsher } 4154adfc5217SJeff Kirsher 4155adfc5217SJeff Kirsher void bnx2x_init_mac_credit_pool(struct bnx2x *bp, 4156adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *p, u8 func_id, 4157adfc5217SJeff Kirsher u8 func_num) 4158adfc5217SJeff Kirsher { 4159adfc5217SJeff Kirsher /* TODO: this will be defined in consts as well... */ 4160adfc5217SJeff Kirsher #define BNX2X_CAM_SIZE_EMUL 5 4161adfc5217SJeff Kirsher 4162adfc5217SJeff Kirsher int cam_sz; 4163adfc5217SJeff Kirsher 4164adfc5217SJeff Kirsher if (CHIP_IS_E1(bp)) { 4165adfc5217SJeff Kirsher /* In E1, Multicast is saved in cam... */ 4166adfc5217SJeff Kirsher if (!CHIP_REV_IS_SLOW(bp)) 4167adfc5217SJeff Kirsher cam_sz = (MAX_MAC_CREDIT_E1 / 2) - BNX2X_MAX_MULTICAST; 4168adfc5217SJeff Kirsher else 4169adfc5217SJeff Kirsher cam_sz = BNX2X_CAM_SIZE_EMUL - BNX2X_MAX_EMUL_MULTI; 4170adfc5217SJeff Kirsher 4171adfc5217SJeff Kirsher bnx2x_init_credit_pool(p, func_id * cam_sz, cam_sz); 4172adfc5217SJeff Kirsher 4173adfc5217SJeff Kirsher } else if (CHIP_IS_E1H(bp)) { 4174adfc5217SJeff Kirsher /* CAM credit is equaly divided between all active functions 4175adfc5217SJeff Kirsher * on the PORT!. 4176adfc5217SJeff Kirsher */ 4177adfc5217SJeff Kirsher if ((func_num > 0)) { 4178adfc5217SJeff Kirsher if (!CHIP_REV_IS_SLOW(bp)) 4179adfc5217SJeff Kirsher cam_sz = (MAX_MAC_CREDIT_E1H / (2*func_num)); 4180adfc5217SJeff Kirsher else 4181adfc5217SJeff Kirsher cam_sz = BNX2X_CAM_SIZE_EMUL; 4182adfc5217SJeff Kirsher bnx2x_init_credit_pool(p, func_id * cam_sz, cam_sz); 4183adfc5217SJeff Kirsher } else { 4184adfc5217SJeff Kirsher /* this should never happen! Block MAC operations. */ 4185adfc5217SJeff Kirsher bnx2x_init_credit_pool(p, 0, 0); 4186adfc5217SJeff Kirsher } 4187adfc5217SJeff Kirsher 4188adfc5217SJeff Kirsher } else { 4189adfc5217SJeff Kirsher 419016a5fd92SYuval Mintz /* CAM credit is equaly divided between all active functions 4191adfc5217SJeff Kirsher * on the PATH. 4192adfc5217SJeff Kirsher */ 4193adfc5217SJeff Kirsher if ((func_num > 0)) { 4194adfc5217SJeff Kirsher if (!CHIP_REV_IS_SLOW(bp)) 4195adfc5217SJeff Kirsher cam_sz = (MAX_MAC_CREDIT_E2 / func_num); 4196adfc5217SJeff Kirsher else 4197adfc5217SJeff Kirsher cam_sz = BNX2X_CAM_SIZE_EMUL; 4198adfc5217SJeff Kirsher 419916a5fd92SYuval Mintz /* No need for CAM entries handling for 57712 and 4200adfc5217SJeff Kirsher * newer. 4201adfc5217SJeff Kirsher */ 4202adfc5217SJeff Kirsher bnx2x_init_credit_pool(p, -1, cam_sz); 4203adfc5217SJeff Kirsher } else { 4204adfc5217SJeff Kirsher /* this should never happen! Block MAC operations. */ 4205adfc5217SJeff Kirsher bnx2x_init_credit_pool(p, 0, 0); 4206adfc5217SJeff Kirsher } 4207adfc5217SJeff Kirsher } 4208adfc5217SJeff Kirsher } 4209adfc5217SJeff Kirsher 4210adfc5217SJeff Kirsher void bnx2x_init_vlan_credit_pool(struct bnx2x *bp, 4211adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *p, 4212adfc5217SJeff Kirsher u8 func_id, 4213adfc5217SJeff Kirsher u8 func_num) 4214adfc5217SJeff Kirsher { 4215adfc5217SJeff Kirsher if (CHIP_IS_E1x(bp)) { 421616a5fd92SYuval Mintz /* There is no VLAN credit in HW on 57710 and 57711 only 4217adfc5217SJeff Kirsher * MAC / MAC-VLAN can be set 4218adfc5217SJeff Kirsher */ 4219adfc5217SJeff Kirsher bnx2x_init_credit_pool(p, 0, -1); 4220adfc5217SJeff Kirsher } else { 422116a5fd92SYuval Mintz /* CAM credit is equally divided between all active functions 4222adfc5217SJeff Kirsher * on the PATH. 4223adfc5217SJeff Kirsher */ 4224adfc5217SJeff Kirsher if (func_num > 0) { 4225adfc5217SJeff Kirsher int credit = MAX_VLAN_CREDIT_E2 / func_num; 4226adfc5217SJeff Kirsher bnx2x_init_credit_pool(p, func_id * credit, credit); 4227adfc5217SJeff Kirsher } else 4228adfc5217SJeff Kirsher /* this should never happen! Block VLAN operations. */ 4229adfc5217SJeff Kirsher bnx2x_init_credit_pool(p, 0, 0); 4230adfc5217SJeff Kirsher } 4231adfc5217SJeff Kirsher } 4232adfc5217SJeff Kirsher 4233adfc5217SJeff Kirsher /****************** RSS Configuration ******************/ 4234adfc5217SJeff Kirsher /** 4235adfc5217SJeff Kirsher * bnx2x_debug_print_ind_table - prints the indirection table configuration. 4236adfc5217SJeff Kirsher * 423716a5fd92SYuval Mintz * @bp: driver handle 4238adfc5217SJeff Kirsher * @p: pointer to rss configuration 4239adfc5217SJeff Kirsher * 4240adfc5217SJeff Kirsher * Prints it when NETIF_MSG_IFUP debug level is configured. 4241adfc5217SJeff Kirsher */ 4242adfc5217SJeff Kirsher static inline void bnx2x_debug_print_ind_table(struct bnx2x *bp, 4243adfc5217SJeff Kirsher struct bnx2x_config_rss_params *p) 4244adfc5217SJeff Kirsher { 4245adfc5217SJeff Kirsher int i; 4246adfc5217SJeff Kirsher 4247adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "Setting indirection table to:\n"); 4248adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "0x0000: "); 4249adfc5217SJeff Kirsher for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++) { 4250adfc5217SJeff Kirsher DP_CONT(BNX2X_MSG_SP, "0x%02x ", p->ind_table[i]); 4251adfc5217SJeff Kirsher 4252adfc5217SJeff Kirsher /* Print 4 bytes in a line */ 4253adfc5217SJeff Kirsher if ((i + 1 < T_ETH_INDIRECTION_TABLE_SIZE) && 4254adfc5217SJeff Kirsher (((i + 1) & 0x3) == 0)) { 4255adfc5217SJeff Kirsher DP_CONT(BNX2X_MSG_SP, "\n"); 4256adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "0x%04x: ", i + 1); 4257adfc5217SJeff Kirsher } 4258adfc5217SJeff Kirsher } 4259adfc5217SJeff Kirsher 4260adfc5217SJeff Kirsher DP_CONT(BNX2X_MSG_SP, "\n"); 4261adfc5217SJeff Kirsher } 4262adfc5217SJeff Kirsher 4263adfc5217SJeff Kirsher /** 4264adfc5217SJeff Kirsher * bnx2x_setup_rss - configure RSS 4265adfc5217SJeff Kirsher * 4266adfc5217SJeff Kirsher * @bp: device handle 4267adfc5217SJeff Kirsher * @p: rss configuration 4268adfc5217SJeff Kirsher * 4269adfc5217SJeff Kirsher * sends on UPDATE ramrod for that matter. 4270adfc5217SJeff Kirsher */ 4271adfc5217SJeff Kirsher static int bnx2x_setup_rss(struct bnx2x *bp, 4272adfc5217SJeff Kirsher struct bnx2x_config_rss_params *p) 4273adfc5217SJeff Kirsher { 4274adfc5217SJeff Kirsher struct bnx2x_rss_config_obj *o = p->rss_obj; 4275adfc5217SJeff Kirsher struct bnx2x_raw_obj *r = &o->raw; 4276adfc5217SJeff Kirsher struct eth_rss_update_ramrod_data *data = 4277adfc5217SJeff Kirsher (struct eth_rss_update_ramrod_data *)(r->rdata); 4278adfc5217SJeff Kirsher u8 rss_mode = 0; 4279adfc5217SJeff Kirsher int rc; 4280adfc5217SJeff Kirsher 4281adfc5217SJeff Kirsher memset(data, 0, sizeof(*data)); 4282adfc5217SJeff Kirsher 4283adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "Configuring RSS\n"); 4284adfc5217SJeff Kirsher 4285adfc5217SJeff Kirsher /* Set an echo field */ 428686564c3fSYuval Mintz data->echo = cpu_to_le32((r->cid & BNX2X_SWCID_MASK) | 428786564c3fSYuval Mintz (r->state << BNX2X_SWCID_SHIFT)); 4288adfc5217SJeff Kirsher 4289adfc5217SJeff Kirsher /* RSS mode */ 4290adfc5217SJeff Kirsher if (test_bit(BNX2X_RSS_MODE_DISABLED, &p->rss_flags)) 4291adfc5217SJeff Kirsher rss_mode = ETH_RSS_MODE_DISABLED; 4292adfc5217SJeff Kirsher else if (test_bit(BNX2X_RSS_MODE_REGULAR, &p->rss_flags)) 4293adfc5217SJeff Kirsher rss_mode = ETH_RSS_MODE_REGULAR; 4294adfc5217SJeff Kirsher 4295adfc5217SJeff Kirsher data->rss_mode = rss_mode; 4296adfc5217SJeff Kirsher 4297adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "rss_mode=%d\n", rss_mode); 4298adfc5217SJeff Kirsher 4299adfc5217SJeff Kirsher /* RSS capabilities */ 4300adfc5217SJeff Kirsher if (test_bit(BNX2X_RSS_IPV4, &p->rss_flags)) 4301adfc5217SJeff Kirsher data->capabilities |= 4302adfc5217SJeff Kirsher ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY; 4303adfc5217SJeff Kirsher 4304adfc5217SJeff Kirsher if (test_bit(BNX2X_RSS_IPV4_TCP, &p->rss_flags)) 4305adfc5217SJeff Kirsher data->capabilities |= 4306adfc5217SJeff Kirsher ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY; 4307adfc5217SJeff Kirsher 43085d317c6aSMerav Sicron if (test_bit(BNX2X_RSS_IPV4_UDP, &p->rss_flags)) 43095d317c6aSMerav Sicron data->capabilities |= 43105d317c6aSMerav Sicron ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY; 43115d317c6aSMerav Sicron 4312adfc5217SJeff Kirsher if (test_bit(BNX2X_RSS_IPV6, &p->rss_flags)) 4313adfc5217SJeff Kirsher data->capabilities |= 4314adfc5217SJeff Kirsher ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY; 4315adfc5217SJeff Kirsher 4316adfc5217SJeff Kirsher if (test_bit(BNX2X_RSS_IPV6_TCP, &p->rss_flags)) 4317adfc5217SJeff Kirsher data->capabilities |= 4318adfc5217SJeff Kirsher ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY; 4319adfc5217SJeff Kirsher 43205d317c6aSMerav Sicron if (test_bit(BNX2X_RSS_IPV6_UDP, &p->rss_flags)) 43215d317c6aSMerav Sicron data->capabilities |= 43225d317c6aSMerav Sicron ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY; 43235d317c6aSMerav Sicron 4324adfc5217SJeff Kirsher /* Hashing mask */ 4325adfc5217SJeff Kirsher data->rss_result_mask = p->rss_result_mask; 4326adfc5217SJeff Kirsher 4327adfc5217SJeff Kirsher /* RSS engine ID */ 4328adfc5217SJeff Kirsher data->rss_engine_id = o->engine_id; 4329adfc5217SJeff Kirsher 4330adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "rss_engine_id=%d\n", data->rss_engine_id); 4331adfc5217SJeff Kirsher 4332adfc5217SJeff Kirsher /* Indirection table */ 4333adfc5217SJeff Kirsher memcpy(data->indirection_table, p->ind_table, 4334adfc5217SJeff Kirsher T_ETH_INDIRECTION_TABLE_SIZE); 4335adfc5217SJeff Kirsher 4336adfc5217SJeff Kirsher /* Remember the last configuration */ 4337adfc5217SJeff Kirsher memcpy(o->ind_table, p->ind_table, T_ETH_INDIRECTION_TABLE_SIZE); 4338adfc5217SJeff Kirsher 4339adfc5217SJeff Kirsher /* Print the indirection table */ 4340adfc5217SJeff Kirsher if (netif_msg_ifup(bp)) 4341adfc5217SJeff Kirsher bnx2x_debug_print_ind_table(bp, p); 4342adfc5217SJeff Kirsher 4343adfc5217SJeff Kirsher /* RSS keys */ 4344adfc5217SJeff Kirsher if (test_bit(BNX2X_RSS_SET_SRCH, &p->rss_flags)) { 4345adfc5217SJeff Kirsher memcpy(&data->rss_key[0], &p->rss_key[0], 4346adfc5217SJeff Kirsher sizeof(data->rss_key)); 4347adfc5217SJeff Kirsher data->capabilities |= ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY; 4348adfc5217SJeff Kirsher } 4349adfc5217SJeff Kirsher 435016a5fd92SYuval Mintz /* No need for an explicit memory barrier here as long we would 4351adfc5217SJeff Kirsher * need to ensure the ordering of writing to the SPQ element 4352adfc5217SJeff Kirsher * and updating of the SPQ producer which involves a memory 4353adfc5217SJeff Kirsher * read and we will have to put a full memory barrier there 4354adfc5217SJeff Kirsher * (inside bnx2x_sp_post()). 4355adfc5217SJeff Kirsher */ 4356adfc5217SJeff Kirsher 4357adfc5217SJeff Kirsher /* Send a ramrod */ 4358adfc5217SJeff Kirsher rc = bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_RSS_UPDATE, r->cid, 4359adfc5217SJeff Kirsher U64_HI(r->rdata_mapping), 4360adfc5217SJeff Kirsher U64_LO(r->rdata_mapping), 4361adfc5217SJeff Kirsher ETH_CONNECTION_TYPE); 4362adfc5217SJeff Kirsher 4363adfc5217SJeff Kirsher if (rc < 0) 4364adfc5217SJeff Kirsher return rc; 4365adfc5217SJeff Kirsher 4366adfc5217SJeff Kirsher return 1; 4367adfc5217SJeff Kirsher } 4368adfc5217SJeff Kirsher 4369adfc5217SJeff Kirsher void bnx2x_get_rss_ind_table(struct bnx2x_rss_config_obj *rss_obj, 4370adfc5217SJeff Kirsher u8 *ind_table) 4371adfc5217SJeff Kirsher { 4372adfc5217SJeff Kirsher memcpy(ind_table, rss_obj->ind_table, sizeof(rss_obj->ind_table)); 4373adfc5217SJeff Kirsher } 4374adfc5217SJeff Kirsher 4375adfc5217SJeff Kirsher int bnx2x_config_rss(struct bnx2x *bp, 4376adfc5217SJeff Kirsher struct bnx2x_config_rss_params *p) 4377adfc5217SJeff Kirsher { 4378adfc5217SJeff Kirsher int rc; 4379adfc5217SJeff Kirsher struct bnx2x_rss_config_obj *o = p->rss_obj; 4380adfc5217SJeff Kirsher struct bnx2x_raw_obj *r = &o->raw; 4381adfc5217SJeff Kirsher 4382adfc5217SJeff Kirsher /* Do nothing if only driver cleanup was requested */ 4383adfc5217SJeff Kirsher if (test_bit(RAMROD_DRV_CLR_ONLY, &p->ramrod_flags)) 4384adfc5217SJeff Kirsher return 0; 4385adfc5217SJeff Kirsher 4386adfc5217SJeff Kirsher r->set_pending(r); 4387adfc5217SJeff Kirsher 4388adfc5217SJeff Kirsher rc = o->config_rss(bp, p); 4389adfc5217SJeff Kirsher if (rc < 0) { 4390adfc5217SJeff Kirsher r->clear_pending(r); 4391adfc5217SJeff Kirsher return rc; 4392adfc5217SJeff Kirsher } 4393adfc5217SJeff Kirsher 4394adfc5217SJeff Kirsher if (test_bit(RAMROD_COMP_WAIT, &p->ramrod_flags)) 4395adfc5217SJeff Kirsher rc = r->wait_comp(bp, r); 4396adfc5217SJeff Kirsher 4397adfc5217SJeff Kirsher return rc; 4398adfc5217SJeff Kirsher } 4399adfc5217SJeff Kirsher 4400adfc5217SJeff Kirsher void bnx2x_init_rss_config_obj(struct bnx2x *bp, 4401adfc5217SJeff Kirsher struct bnx2x_rss_config_obj *rss_obj, 4402adfc5217SJeff Kirsher u8 cl_id, u32 cid, u8 func_id, u8 engine_id, 4403adfc5217SJeff Kirsher void *rdata, dma_addr_t rdata_mapping, 4404adfc5217SJeff Kirsher int state, unsigned long *pstate, 4405adfc5217SJeff Kirsher bnx2x_obj_type type) 4406adfc5217SJeff Kirsher { 4407adfc5217SJeff Kirsher bnx2x_init_raw_obj(&rss_obj->raw, cl_id, cid, func_id, rdata, 4408adfc5217SJeff Kirsher rdata_mapping, state, pstate, type); 4409adfc5217SJeff Kirsher 4410adfc5217SJeff Kirsher rss_obj->engine_id = engine_id; 4411adfc5217SJeff Kirsher rss_obj->config_rss = bnx2x_setup_rss; 4412adfc5217SJeff Kirsher } 4413adfc5217SJeff Kirsher 4414b9871bcfSAriel Elior int validate_vlan_mac(struct bnx2x *bp, 4415b9871bcfSAriel Elior struct bnx2x_vlan_mac_obj *vlan_mac) 4416b9871bcfSAriel Elior { 4417b9871bcfSAriel Elior if (!vlan_mac->get_n_elements) { 4418b9871bcfSAriel Elior BNX2X_ERR("vlan mac object was not intialized\n"); 4419b9871bcfSAriel Elior return -EINVAL; 4420b9871bcfSAriel Elior } 4421b9871bcfSAriel Elior return 0; 4422b9871bcfSAriel Elior } 4423b9871bcfSAriel Elior 4424adfc5217SJeff Kirsher /********************** Queue state object ***********************************/ 4425adfc5217SJeff Kirsher 4426adfc5217SJeff Kirsher /** 4427adfc5217SJeff Kirsher * bnx2x_queue_state_change - perform Queue state change transition 4428adfc5217SJeff Kirsher * 4429adfc5217SJeff Kirsher * @bp: device handle 4430adfc5217SJeff Kirsher * @params: parameters to perform the transition 4431adfc5217SJeff Kirsher * 4432adfc5217SJeff Kirsher * returns 0 in case of successfully completed transition, negative error 4433adfc5217SJeff Kirsher * code in case of failure, positive (EBUSY) value if there is a completion 4434adfc5217SJeff Kirsher * to that is still pending (possible only if RAMROD_COMP_WAIT is 4435adfc5217SJeff Kirsher * not set in params->ramrod_flags for asynchronous commands). 4436adfc5217SJeff Kirsher * 4437adfc5217SJeff Kirsher */ 4438adfc5217SJeff Kirsher int bnx2x_queue_state_change(struct bnx2x *bp, 4439adfc5217SJeff Kirsher struct bnx2x_queue_state_params *params) 4440adfc5217SJeff Kirsher { 4441adfc5217SJeff Kirsher struct bnx2x_queue_sp_obj *o = params->q_obj; 4442adfc5217SJeff Kirsher int rc, pending_bit; 4443adfc5217SJeff Kirsher unsigned long *pending = &o->pending; 4444adfc5217SJeff Kirsher 4445adfc5217SJeff Kirsher /* Check that the requested transition is legal */ 444604c46736SYuval Mintz rc = o->check_transition(bp, o, params); 444704c46736SYuval Mintz if (rc) { 444804c46736SYuval Mintz BNX2X_ERR("check transition returned an error. rc %d\n", rc); 4449adfc5217SJeff Kirsher return -EINVAL; 445004c46736SYuval Mintz } 4451adfc5217SJeff Kirsher 4452adfc5217SJeff Kirsher /* Set "pending" bit */ 445304c46736SYuval Mintz DP(BNX2X_MSG_SP, "pending bit was=%lx\n", o->pending); 4454adfc5217SJeff Kirsher pending_bit = o->set_pending(o, params); 445504c46736SYuval Mintz DP(BNX2X_MSG_SP, "pending bit now=%lx\n", o->pending); 4456adfc5217SJeff Kirsher 4457adfc5217SJeff Kirsher /* Don't send a command if only driver cleanup was requested */ 4458adfc5217SJeff Kirsher if (test_bit(RAMROD_DRV_CLR_ONLY, ¶ms->ramrod_flags)) 4459adfc5217SJeff Kirsher o->complete_cmd(bp, o, pending_bit); 4460adfc5217SJeff Kirsher else { 4461adfc5217SJeff Kirsher /* Send a ramrod */ 4462adfc5217SJeff Kirsher rc = o->send_cmd(bp, params); 4463adfc5217SJeff Kirsher if (rc) { 4464adfc5217SJeff Kirsher o->next_state = BNX2X_Q_STATE_MAX; 4465adfc5217SJeff Kirsher clear_bit(pending_bit, pending); 4466adfc5217SJeff Kirsher smp_mb__after_clear_bit(); 4467adfc5217SJeff Kirsher return rc; 4468adfc5217SJeff Kirsher } 4469adfc5217SJeff Kirsher 4470adfc5217SJeff Kirsher if (test_bit(RAMROD_COMP_WAIT, ¶ms->ramrod_flags)) { 4471adfc5217SJeff Kirsher rc = o->wait_comp(bp, o, pending_bit); 4472adfc5217SJeff Kirsher if (rc) 4473adfc5217SJeff Kirsher return rc; 4474adfc5217SJeff Kirsher 4475adfc5217SJeff Kirsher return 0; 4476adfc5217SJeff Kirsher } 4477adfc5217SJeff Kirsher } 4478adfc5217SJeff Kirsher 4479adfc5217SJeff Kirsher return !!test_bit(pending_bit, pending); 4480adfc5217SJeff Kirsher } 4481adfc5217SJeff Kirsher 4482adfc5217SJeff Kirsher static int bnx2x_queue_set_pending(struct bnx2x_queue_sp_obj *obj, 4483adfc5217SJeff Kirsher struct bnx2x_queue_state_params *params) 4484adfc5217SJeff Kirsher { 4485adfc5217SJeff Kirsher enum bnx2x_queue_cmd cmd = params->cmd, bit; 4486adfc5217SJeff Kirsher 4487adfc5217SJeff Kirsher /* ACTIVATE and DEACTIVATE commands are implemented on top of 4488adfc5217SJeff Kirsher * UPDATE command. 4489adfc5217SJeff Kirsher */ 4490adfc5217SJeff Kirsher if ((cmd == BNX2X_Q_CMD_ACTIVATE) || 4491adfc5217SJeff Kirsher (cmd == BNX2X_Q_CMD_DEACTIVATE)) 4492adfc5217SJeff Kirsher bit = BNX2X_Q_CMD_UPDATE; 4493adfc5217SJeff Kirsher else 4494adfc5217SJeff Kirsher bit = cmd; 4495adfc5217SJeff Kirsher 4496adfc5217SJeff Kirsher set_bit(bit, &obj->pending); 4497adfc5217SJeff Kirsher return bit; 4498adfc5217SJeff Kirsher } 4499adfc5217SJeff Kirsher 4500adfc5217SJeff Kirsher static int bnx2x_queue_wait_comp(struct bnx2x *bp, 4501adfc5217SJeff Kirsher struct bnx2x_queue_sp_obj *o, 4502adfc5217SJeff Kirsher enum bnx2x_queue_cmd cmd) 4503adfc5217SJeff Kirsher { 4504adfc5217SJeff Kirsher return bnx2x_state_wait(bp, cmd, &o->pending); 4505adfc5217SJeff Kirsher } 4506adfc5217SJeff Kirsher 4507adfc5217SJeff Kirsher /** 4508adfc5217SJeff Kirsher * bnx2x_queue_comp_cmd - complete the state change command. 4509adfc5217SJeff Kirsher * 4510adfc5217SJeff Kirsher * @bp: device handle 4511adfc5217SJeff Kirsher * @o: 4512adfc5217SJeff Kirsher * @cmd: 4513adfc5217SJeff Kirsher * 4514adfc5217SJeff Kirsher * Checks that the arrived completion is expected. 4515adfc5217SJeff Kirsher */ 4516adfc5217SJeff Kirsher static int bnx2x_queue_comp_cmd(struct bnx2x *bp, 4517adfc5217SJeff Kirsher struct bnx2x_queue_sp_obj *o, 4518adfc5217SJeff Kirsher enum bnx2x_queue_cmd cmd) 4519adfc5217SJeff Kirsher { 4520adfc5217SJeff Kirsher unsigned long cur_pending = o->pending; 4521adfc5217SJeff Kirsher 4522adfc5217SJeff Kirsher if (!test_and_clear_bit(cmd, &cur_pending)) { 452351c1a580SMerav Sicron BNX2X_ERR("Bad MC reply %d for queue %d in state %d pending 0x%lx, next_state %d\n", 452451c1a580SMerav Sicron cmd, o->cids[BNX2X_PRIMARY_CID_INDEX], 4525adfc5217SJeff Kirsher o->state, cur_pending, o->next_state); 4526adfc5217SJeff Kirsher return -EINVAL; 4527adfc5217SJeff Kirsher } 4528adfc5217SJeff Kirsher 4529adfc5217SJeff Kirsher if (o->next_tx_only >= o->max_cos) 453016a5fd92SYuval Mintz /* >= because tx only must always be smaller than cos since the 453102582e9bSMasanari Iida * primary connection supports COS 0 4532adfc5217SJeff Kirsher */ 4533adfc5217SJeff Kirsher BNX2X_ERR("illegal value for next tx_only: %d. max cos was %d", 4534adfc5217SJeff Kirsher o->next_tx_only, o->max_cos); 4535adfc5217SJeff Kirsher 453651c1a580SMerav Sicron DP(BNX2X_MSG_SP, 453751c1a580SMerav Sicron "Completing command %d for queue %d, setting state to %d\n", 453851c1a580SMerav Sicron cmd, o->cids[BNX2X_PRIMARY_CID_INDEX], o->next_state); 4539adfc5217SJeff Kirsher 4540adfc5217SJeff Kirsher if (o->next_tx_only) /* print num tx-only if any exist */ 454194f05b0fSJoe Perches DP(BNX2X_MSG_SP, "primary cid %d: num tx-only cons %d\n", 4542adfc5217SJeff Kirsher o->cids[BNX2X_PRIMARY_CID_INDEX], o->next_tx_only); 4543adfc5217SJeff Kirsher 4544adfc5217SJeff Kirsher o->state = o->next_state; 4545adfc5217SJeff Kirsher o->num_tx_only = o->next_tx_only; 4546adfc5217SJeff Kirsher o->next_state = BNX2X_Q_STATE_MAX; 4547adfc5217SJeff Kirsher 4548adfc5217SJeff Kirsher /* It's important that o->state and o->next_state are 4549adfc5217SJeff Kirsher * updated before o->pending. 4550adfc5217SJeff Kirsher */ 4551adfc5217SJeff Kirsher wmb(); 4552adfc5217SJeff Kirsher 4553adfc5217SJeff Kirsher clear_bit(cmd, &o->pending); 4554adfc5217SJeff Kirsher smp_mb__after_clear_bit(); 4555adfc5217SJeff Kirsher 4556adfc5217SJeff Kirsher return 0; 4557adfc5217SJeff Kirsher } 4558adfc5217SJeff Kirsher 4559adfc5217SJeff Kirsher static void bnx2x_q_fill_setup_data_e2(struct bnx2x *bp, 4560adfc5217SJeff Kirsher struct bnx2x_queue_state_params *cmd_params, 4561adfc5217SJeff Kirsher struct client_init_ramrod_data *data) 4562adfc5217SJeff Kirsher { 4563adfc5217SJeff Kirsher struct bnx2x_queue_setup_params *params = &cmd_params->params.setup; 4564adfc5217SJeff Kirsher 4565adfc5217SJeff Kirsher /* Rx data */ 4566adfc5217SJeff Kirsher 4567adfc5217SJeff Kirsher /* IPv6 TPA supported for E2 and above only */ 4568adfc5217SJeff Kirsher data->rx.tpa_en |= test_bit(BNX2X_Q_FLG_TPA_IPV6, ¶ms->flags) * 4569adfc5217SJeff Kirsher CLIENT_INIT_RX_DATA_TPA_EN_IPV6; 4570adfc5217SJeff Kirsher } 4571adfc5217SJeff Kirsher 4572adfc5217SJeff Kirsher static void bnx2x_q_fill_init_general_data(struct bnx2x *bp, 4573adfc5217SJeff Kirsher struct bnx2x_queue_sp_obj *o, 4574adfc5217SJeff Kirsher struct bnx2x_general_setup_params *params, 4575adfc5217SJeff Kirsher struct client_init_general_data *gen_data, 4576adfc5217SJeff Kirsher unsigned long *flags) 4577adfc5217SJeff Kirsher { 4578adfc5217SJeff Kirsher gen_data->client_id = o->cl_id; 4579adfc5217SJeff Kirsher 4580adfc5217SJeff Kirsher if (test_bit(BNX2X_Q_FLG_STATS, flags)) { 4581adfc5217SJeff Kirsher gen_data->statistics_counter_id = 4582adfc5217SJeff Kirsher params->stat_id; 4583adfc5217SJeff Kirsher gen_data->statistics_en_flg = 1; 4584adfc5217SJeff Kirsher gen_data->statistics_zero_flg = 4585adfc5217SJeff Kirsher test_bit(BNX2X_Q_FLG_ZERO_STATS, flags); 4586adfc5217SJeff Kirsher } else 4587adfc5217SJeff Kirsher gen_data->statistics_counter_id = 4588adfc5217SJeff Kirsher DISABLE_STATISTIC_COUNTER_ID_VALUE; 4589adfc5217SJeff Kirsher 4590adfc5217SJeff Kirsher gen_data->is_fcoe_flg = test_bit(BNX2X_Q_FLG_FCOE, flags); 4591adfc5217SJeff Kirsher gen_data->activate_flg = test_bit(BNX2X_Q_FLG_ACTIVE, flags); 4592adfc5217SJeff Kirsher gen_data->sp_client_id = params->spcl_id; 4593adfc5217SJeff Kirsher gen_data->mtu = cpu_to_le16(params->mtu); 4594adfc5217SJeff Kirsher gen_data->func_id = o->func_id; 4595adfc5217SJeff Kirsher 4596adfc5217SJeff Kirsher gen_data->cos = params->cos; 4597adfc5217SJeff Kirsher 4598adfc5217SJeff Kirsher gen_data->traffic_type = 4599adfc5217SJeff Kirsher test_bit(BNX2X_Q_FLG_FCOE, flags) ? 4600adfc5217SJeff Kirsher LLFC_TRAFFIC_TYPE_FCOE : LLFC_TRAFFIC_TYPE_NW; 4601adfc5217SJeff Kirsher 460294f05b0fSJoe Perches DP(BNX2X_MSG_SP, "flags: active %d, cos %d, stats en %d\n", 4603adfc5217SJeff Kirsher gen_data->activate_flg, gen_data->cos, gen_data->statistics_en_flg); 4604adfc5217SJeff Kirsher } 4605adfc5217SJeff Kirsher 4606adfc5217SJeff Kirsher static void bnx2x_q_fill_init_tx_data(struct bnx2x_queue_sp_obj *o, 4607adfc5217SJeff Kirsher struct bnx2x_txq_setup_params *params, 4608adfc5217SJeff Kirsher struct client_init_tx_data *tx_data, 4609adfc5217SJeff Kirsher unsigned long *flags) 4610adfc5217SJeff Kirsher { 4611adfc5217SJeff Kirsher tx_data->enforce_security_flg = 4612adfc5217SJeff Kirsher test_bit(BNX2X_Q_FLG_TX_SEC, flags); 4613adfc5217SJeff Kirsher tx_data->default_vlan = 4614adfc5217SJeff Kirsher cpu_to_le16(params->default_vlan); 4615adfc5217SJeff Kirsher tx_data->default_vlan_flg = 4616adfc5217SJeff Kirsher test_bit(BNX2X_Q_FLG_DEF_VLAN, flags); 4617adfc5217SJeff Kirsher tx_data->tx_switching_flg = 4618adfc5217SJeff Kirsher test_bit(BNX2X_Q_FLG_TX_SWITCH, flags); 4619adfc5217SJeff Kirsher tx_data->anti_spoofing_flg = 4620adfc5217SJeff Kirsher test_bit(BNX2X_Q_FLG_ANTI_SPOOF, flags); 4621a3348722SBarak Witkowski tx_data->force_default_pri_flg = 4622a3348722SBarak Witkowski test_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI, flags); 4623a3348722SBarak Witkowski 4624e287a75cSDmitry Kravkov tx_data->tunnel_lso_inc_ip_id = 4625e287a75cSDmitry Kravkov test_bit(BNX2X_Q_FLG_TUN_INC_INNER_IP_ID, flags); 462691226790SDmitry Kravkov tx_data->tunnel_non_lso_pcsum_location = 462791226790SDmitry Kravkov test_bit(BNX2X_Q_FLG_PCSUM_ON_PKT, flags) ? PCSUM_ON_PKT : 462891226790SDmitry Kravkov PCSUM_ON_BD; 462991226790SDmitry Kravkov 4630adfc5217SJeff Kirsher tx_data->tx_status_block_id = params->fw_sb_id; 4631adfc5217SJeff Kirsher tx_data->tx_sb_index_number = params->sb_cq_index; 4632adfc5217SJeff Kirsher tx_data->tss_leading_client_id = params->tss_leading_cl_id; 4633adfc5217SJeff Kirsher 4634adfc5217SJeff Kirsher tx_data->tx_bd_page_base.lo = 4635adfc5217SJeff Kirsher cpu_to_le32(U64_LO(params->dscr_map)); 4636adfc5217SJeff Kirsher tx_data->tx_bd_page_base.hi = 4637adfc5217SJeff Kirsher cpu_to_le32(U64_HI(params->dscr_map)); 4638adfc5217SJeff Kirsher 4639adfc5217SJeff Kirsher /* Don't configure any Tx switching mode during queue SETUP */ 4640adfc5217SJeff Kirsher tx_data->state = 0; 4641adfc5217SJeff Kirsher } 4642adfc5217SJeff Kirsher 4643adfc5217SJeff Kirsher static void bnx2x_q_fill_init_pause_data(struct bnx2x_queue_sp_obj *o, 4644adfc5217SJeff Kirsher struct rxq_pause_params *params, 4645adfc5217SJeff Kirsher struct client_init_rx_data *rx_data) 4646adfc5217SJeff Kirsher { 4647adfc5217SJeff Kirsher /* flow control data */ 4648adfc5217SJeff Kirsher rx_data->cqe_pause_thr_low = cpu_to_le16(params->rcq_th_lo); 4649adfc5217SJeff Kirsher rx_data->cqe_pause_thr_high = cpu_to_le16(params->rcq_th_hi); 4650adfc5217SJeff Kirsher rx_data->bd_pause_thr_low = cpu_to_le16(params->bd_th_lo); 4651adfc5217SJeff Kirsher rx_data->bd_pause_thr_high = cpu_to_le16(params->bd_th_hi); 4652adfc5217SJeff Kirsher rx_data->sge_pause_thr_low = cpu_to_le16(params->sge_th_lo); 4653adfc5217SJeff Kirsher rx_data->sge_pause_thr_high = cpu_to_le16(params->sge_th_hi); 4654adfc5217SJeff Kirsher rx_data->rx_cos_mask = cpu_to_le16(params->pri_map); 4655adfc5217SJeff Kirsher } 4656adfc5217SJeff Kirsher 4657adfc5217SJeff Kirsher static void bnx2x_q_fill_init_rx_data(struct bnx2x_queue_sp_obj *o, 4658adfc5217SJeff Kirsher struct bnx2x_rxq_setup_params *params, 4659adfc5217SJeff Kirsher struct client_init_rx_data *rx_data, 4660adfc5217SJeff Kirsher unsigned long *flags) 4661adfc5217SJeff Kirsher { 4662adfc5217SJeff Kirsher rx_data->tpa_en = test_bit(BNX2X_Q_FLG_TPA, flags) * 4663adfc5217SJeff Kirsher CLIENT_INIT_RX_DATA_TPA_EN_IPV4; 4664621b4d66SDmitry Kravkov rx_data->tpa_en |= test_bit(BNX2X_Q_FLG_TPA_GRO, flags) * 4665621b4d66SDmitry Kravkov CLIENT_INIT_RX_DATA_TPA_MODE; 4666adfc5217SJeff Kirsher rx_data->vmqueue_mode_en_flg = 0; 4667adfc5217SJeff Kirsher 4668adfc5217SJeff Kirsher rx_data->cache_line_alignment_log_size = 4669adfc5217SJeff Kirsher params->cache_line_log; 4670adfc5217SJeff Kirsher rx_data->enable_dynamic_hc = 4671adfc5217SJeff Kirsher test_bit(BNX2X_Q_FLG_DHC, flags); 4672adfc5217SJeff Kirsher rx_data->max_sges_for_packet = params->max_sges_pkt; 4673adfc5217SJeff Kirsher rx_data->client_qzone_id = params->cl_qzone_id; 4674adfc5217SJeff Kirsher rx_data->max_agg_size = cpu_to_le16(params->tpa_agg_sz); 4675adfc5217SJeff Kirsher 4676adfc5217SJeff Kirsher /* Always start in DROP_ALL mode */ 4677adfc5217SJeff Kirsher rx_data->state = cpu_to_le16(CLIENT_INIT_RX_DATA_UCAST_DROP_ALL | 4678adfc5217SJeff Kirsher CLIENT_INIT_RX_DATA_MCAST_DROP_ALL); 4679adfc5217SJeff Kirsher 4680adfc5217SJeff Kirsher /* We don't set drop flags */ 4681adfc5217SJeff Kirsher rx_data->drop_ip_cs_err_flg = 0; 4682adfc5217SJeff Kirsher rx_data->drop_tcp_cs_err_flg = 0; 4683adfc5217SJeff Kirsher rx_data->drop_ttl0_flg = 0; 4684adfc5217SJeff Kirsher rx_data->drop_udp_cs_err_flg = 0; 4685adfc5217SJeff Kirsher rx_data->inner_vlan_removal_enable_flg = 4686adfc5217SJeff Kirsher test_bit(BNX2X_Q_FLG_VLAN, flags); 4687adfc5217SJeff Kirsher rx_data->outer_vlan_removal_enable_flg = 4688adfc5217SJeff Kirsher test_bit(BNX2X_Q_FLG_OV, flags); 4689adfc5217SJeff Kirsher rx_data->status_block_id = params->fw_sb_id; 4690adfc5217SJeff Kirsher rx_data->rx_sb_index_number = params->sb_cq_index; 4691adfc5217SJeff Kirsher rx_data->max_tpa_queues = params->max_tpa_queues; 4692adfc5217SJeff Kirsher rx_data->max_bytes_on_bd = cpu_to_le16(params->buf_sz); 4693adfc5217SJeff Kirsher rx_data->sge_buff_size = cpu_to_le16(params->sge_buf_sz); 4694adfc5217SJeff Kirsher rx_data->bd_page_base.lo = 4695adfc5217SJeff Kirsher cpu_to_le32(U64_LO(params->dscr_map)); 4696adfc5217SJeff Kirsher rx_data->bd_page_base.hi = 4697adfc5217SJeff Kirsher cpu_to_le32(U64_HI(params->dscr_map)); 4698adfc5217SJeff Kirsher rx_data->sge_page_base.lo = 4699adfc5217SJeff Kirsher cpu_to_le32(U64_LO(params->sge_map)); 4700adfc5217SJeff Kirsher rx_data->sge_page_base.hi = 4701adfc5217SJeff Kirsher cpu_to_le32(U64_HI(params->sge_map)); 4702adfc5217SJeff Kirsher rx_data->cqe_page_base.lo = 4703adfc5217SJeff Kirsher cpu_to_le32(U64_LO(params->rcq_map)); 4704adfc5217SJeff Kirsher rx_data->cqe_page_base.hi = 4705adfc5217SJeff Kirsher cpu_to_le32(U64_HI(params->rcq_map)); 4706adfc5217SJeff Kirsher rx_data->is_leading_rss = test_bit(BNX2X_Q_FLG_LEADING_RSS, flags); 4707adfc5217SJeff Kirsher 4708adfc5217SJeff Kirsher if (test_bit(BNX2X_Q_FLG_MCAST, flags)) { 4709259afa1fSYuval Mintz rx_data->approx_mcast_engine_id = params->mcast_engine_id; 4710adfc5217SJeff Kirsher rx_data->is_approx_mcast = 1; 4711adfc5217SJeff Kirsher } 4712adfc5217SJeff Kirsher 4713adfc5217SJeff Kirsher rx_data->rss_engine_id = params->rss_engine_id; 4714adfc5217SJeff Kirsher 4715adfc5217SJeff Kirsher /* silent vlan removal */ 4716adfc5217SJeff Kirsher rx_data->silent_vlan_removal_flg = 4717adfc5217SJeff Kirsher test_bit(BNX2X_Q_FLG_SILENT_VLAN_REM, flags); 4718adfc5217SJeff Kirsher rx_data->silent_vlan_value = 4719adfc5217SJeff Kirsher cpu_to_le16(params->silent_removal_value); 4720adfc5217SJeff Kirsher rx_data->silent_vlan_mask = 4721adfc5217SJeff Kirsher cpu_to_le16(params->silent_removal_mask); 4722adfc5217SJeff Kirsher } 4723adfc5217SJeff Kirsher 4724adfc5217SJeff Kirsher /* initialize the general, tx and rx parts of a queue object */ 4725adfc5217SJeff Kirsher static void bnx2x_q_fill_setup_data_cmn(struct bnx2x *bp, 4726adfc5217SJeff Kirsher struct bnx2x_queue_state_params *cmd_params, 4727adfc5217SJeff Kirsher struct client_init_ramrod_data *data) 4728adfc5217SJeff Kirsher { 4729adfc5217SJeff Kirsher bnx2x_q_fill_init_general_data(bp, cmd_params->q_obj, 4730adfc5217SJeff Kirsher &cmd_params->params.setup.gen_params, 4731adfc5217SJeff Kirsher &data->general, 4732adfc5217SJeff Kirsher &cmd_params->params.setup.flags); 4733adfc5217SJeff Kirsher 4734adfc5217SJeff Kirsher bnx2x_q_fill_init_tx_data(cmd_params->q_obj, 4735adfc5217SJeff Kirsher &cmd_params->params.setup.txq_params, 4736adfc5217SJeff Kirsher &data->tx, 4737adfc5217SJeff Kirsher &cmd_params->params.setup.flags); 4738adfc5217SJeff Kirsher 4739adfc5217SJeff Kirsher bnx2x_q_fill_init_rx_data(cmd_params->q_obj, 4740adfc5217SJeff Kirsher &cmd_params->params.setup.rxq_params, 4741adfc5217SJeff Kirsher &data->rx, 4742adfc5217SJeff Kirsher &cmd_params->params.setup.flags); 4743adfc5217SJeff Kirsher 4744adfc5217SJeff Kirsher bnx2x_q_fill_init_pause_data(cmd_params->q_obj, 4745adfc5217SJeff Kirsher &cmd_params->params.setup.pause_params, 4746adfc5217SJeff Kirsher &data->rx); 4747adfc5217SJeff Kirsher } 4748adfc5217SJeff Kirsher 4749adfc5217SJeff Kirsher /* initialize the general and tx parts of a tx-only queue object */ 4750adfc5217SJeff Kirsher static void bnx2x_q_fill_setup_tx_only(struct bnx2x *bp, 4751adfc5217SJeff Kirsher struct bnx2x_queue_state_params *cmd_params, 4752adfc5217SJeff Kirsher struct tx_queue_init_ramrod_data *data) 4753adfc5217SJeff Kirsher { 4754adfc5217SJeff Kirsher bnx2x_q_fill_init_general_data(bp, cmd_params->q_obj, 4755adfc5217SJeff Kirsher &cmd_params->params.tx_only.gen_params, 4756adfc5217SJeff Kirsher &data->general, 4757adfc5217SJeff Kirsher &cmd_params->params.tx_only.flags); 4758adfc5217SJeff Kirsher 4759adfc5217SJeff Kirsher bnx2x_q_fill_init_tx_data(cmd_params->q_obj, 4760adfc5217SJeff Kirsher &cmd_params->params.tx_only.txq_params, 4761adfc5217SJeff Kirsher &data->tx, 4762adfc5217SJeff Kirsher &cmd_params->params.tx_only.flags); 4763adfc5217SJeff Kirsher 476451c1a580SMerav Sicron DP(BNX2X_MSG_SP, "cid %d, tx bd page lo %x hi %x", 476551c1a580SMerav Sicron cmd_params->q_obj->cids[0], 476651c1a580SMerav Sicron data->tx.tx_bd_page_base.lo, 476751c1a580SMerav Sicron data->tx.tx_bd_page_base.hi); 4768adfc5217SJeff Kirsher } 4769adfc5217SJeff Kirsher 4770adfc5217SJeff Kirsher /** 4771adfc5217SJeff Kirsher * bnx2x_q_init - init HW/FW queue 4772adfc5217SJeff Kirsher * 4773adfc5217SJeff Kirsher * @bp: device handle 4774adfc5217SJeff Kirsher * @params: 4775adfc5217SJeff Kirsher * 4776adfc5217SJeff Kirsher * HW/FW initial Queue configuration: 4777adfc5217SJeff Kirsher * - HC: Rx and Tx 4778adfc5217SJeff Kirsher * - CDU context validation 4779adfc5217SJeff Kirsher * 4780adfc5217SJeff Kirsher */ 4781adfc5217SJeff Kirsher static inline int bnx2x_q_init(struct bnx2x *bp, 4782adfc5217SJeff Kirsher struct bnx2x_queue_state_params *params) 4783adfc5217SJeff Kirsher { 4784adfc5217SJeff Kirsher struct bnx2x_queue_sp_obj *o = params->q_obj; 4785adfc5217SJeff Kirsher struct bnx2x_queue_init_params *init = ¶ms->params.init; 4786adfc5217SJeff Kirsher u16 hc_usec; 4787adfc5217SJeff Kirsher u8 cos; 4788adfc5217SJeff Kirsher 4789adfc5217SJeff Kirsher /* Tx HC configuration */ 4790adfc5217SJeff Kirsher if (test_bit(BNX2X_Q_TYPE_HAS_TX, &o->type) && 4791adfc5217SJeff Kirsher test_bit(BNX2X_Q_FLG_HC, &init->tx.flags)) { 4792adfc5217SJeff Kirsher hc_usec = init->tx.hc_rate ? 1000000 / init->tx.hc_rate : 0; 4793adfc5217SJeff Kirsher 4794adfc5217SJeff Kirsher bnx2x_update_coalesce_sb_index(bp, init->tx.fw_sb_id, 4795adfc5217SJeff Kirsher init->tx.sb_cq_index, 4796adfc5217SJeff Kirsher !test_bit(BNX2X_Q_FLG_HC_EN, &init->tx.flags), 4797adfc5217SJeff Kirsher hc_usec); 4798adfc5217SJeff Kirsher } 4799adfc5217SJeff Kirsher 4800adfc5217SJeff Kirsher /* Rx HC configuration */ 4801adfc5217SJeff Kirsher if (test_bit(BNX2X_Q_TYPE_HAS_RX, &o->type) && 4802adfc5217SJeff Kirsher test_bit(BNX2X_Q_FLG_HC, &init->rx.flags)) { 4803adfc5217SJeff Kirsher hc_usec = init->rx.hc_rate ? 1000000 / init->rx.hc_rate : 0; 4804adfc5217SJeff Kirsher 4805adfc5217SJeff Kirsher bnx2x_update_coalesce_sb_index(bp, init->rx.fw_sb_id, 4806adfc5217SJeff Kirsher init->rx.sb_cq_index, 4807adfc5217SJeff Kirsher !test_bit(BNX2X_Q_FLG_HC_EN, &init->rx.flags), 4808adfc5217SJeff Kirsher hc_usec); 4809adfc5217SJeff Kirsher } 4810adfc5217SJeff Kirsher 4811adfc5217SJeff Kirsher /* Set CDU context validation values */ 4812adfc5217SJeff Kirsher for (cos = 0; cos < o->max_cos; cos++) { 481394f05b0fSJoe Perches DP(BNX2X_MSG_SP, "setting context validation. cid %d, cos %d\n", 4814adfc5217SJeff Kirsher o->cids[cos], cos); 481594f05b0fSJoe Perches DP(BNX2X_MSG_SP, "context pointer %p\n", init->cxts[cos]); 4816adfc5217SJeff Kirsher bnx2x_set_ctx_validation(bp, init->cxts[cos], o->cids[cos]); 4817adfc5217SJeff Kirsher } 4818adfc5217SJeff Kirsher 4819adfc5217SJeff Kirsher /* As no ramrod is sent, complete the command immediately */ 4820adfc5217SJeff Kirsher o->complete_cmd(bp, o, BNX2X_Q_CMD_INIT); 4821adfc5217SJeff Kirsher 4822adfc5217SJeff Kirsher mmiowb(); 4823adfc5217SJeff Kirsher smp_mb(); 4824adfc5217SJeff Kirsher 4825adfc5217SJeff Kirsher return 0; 4826adfc5217SJeff Kirsher } 4827adfc5217SJeff Kirsher 4828adfc5217SJeff Kirsher static inline int bnx2x_q_send_setup_e1x(struct bnx2x *bp, 4829adfc5217SJeff Kirsher struct bnx2x_queue_state_params *params) 4830adfc5217SJeff Kirsher { 4831adfc5217SJeff Kirsher struct bnx2x_queue_sp_obj *o = params->q_obj; 4832adfc5217SJeff Kirsher struct client_init_ramrod_data *rdata = 4833adfc5217SJeff Kirsher (struct client_init_ramrod_data *)o->rdata; 4834adfc5217SJeff Kirsher dma_addr_t data_mapping = o->rdata_mapping; 4835adfc5217SJeff Kirsher int ramrod = RAMROD_CMD_ID_ETH_CLIENT_SETUP; 4836adfc5217SJeff Kirsher 4837adfc5217SJeff Kirsher /* Clear the ramrod data */ 4838adfc5217SJeff Kirsher memset(rdata, 0, sizeof(*rdata)); 4839adfc5217SJeff Kirsher 4840adfc5217SJeff Kirsher /* Fill the ramrod data */ 4841adfc5217SJeff Kirsher bnx2x_q_fill_setup_data_cmn(bp, params, rdata); 4842adfc5217SJeff Kirsher 484316a5fd92SYuval Mintz /* No need for an explicit memory barrier here as long we would 4844adfc5217SJeff Kirsher * need to ensure the ordering of writing to the SPQ element 4845adfc5217SJeff Kirsher * and updating of the SPQ producer which involves a memory 4846adfc5217SJeff Kirsher * read and we will have to put a full memory barrier there 4847adfc5217SJeff Kirsher * (inside bnx2x_sp_post()). 4848adfc5217SJeff Kirsher */ 4849adfc5217SJeff Kirsher 4850adfc5217SJeff Kirsher return bnx2x_sp_post(bp, ramrod, o->cids[BNX2X_PRIMARY_CID_INDEX], 4851adfc5217SJeff Kirsher U64_HI(data_mapping), 4852adfc5217SJeff Kirsher U64_LO(data_mapping), ETH_CONNECTION_TYPE); 4853adfc5217SJeff Kirsher } 4854adfc5217SJeff Kirsher 4855adfc5217SJeff Kirsher static inline int bnx2x_q_send_setup_e2(struct bnx2x *bp, 4856adfc5217SJeff Kirsher struct bnx2x_queue_state_params *params) 4857adfc5217SJeff Kirsher { 4858adfc5217SJeff Kirsher struct bnx2x_queue_sp_obj *o = params->q_obj; 4859adfc5217SJeff Kirsher struct client_init_ramrod_data *rdata = 4860adfc5217SJeff Kirsher (struct client_init_ramrod_data *)o->rdata; 4861adfc5217SJeff Kirsher dma_addr_t data_mapping = o->rdata_mapping; 4862adfc5217SJeff Kirsher int ramrod = RAMROD_CMD_ID_ETH_CLIENT_SETUP; 4863adfc5217SJeff Kirsher 4864adfc5217SJeff Kirsher /* Clear the ramrod data */ 4865adfc5217SJeff Kirsher memset(rdata, 0, sizeof(*rdata)); 4866adfc5217SJeff Kirsher 4867adfc5217SJeff Kirsher /* Fill the ramrod data */ 4868adfc5217SJeff Kirsher bnx2x_q_fill_setup_data_cmn(bp, params, rdata); 4869adfc5217SJeff Kirsher bnx2x_q_fill_setup_data_e2(bp, params, rdata); 4870adfc5217SJeff Kirsher 487116a5fd92SYuval Mintz /* No need for an explicit memory barrier here as long we would 4872adfc5217SJeff Kirsher * need to ensure the ordering of writing to the SPQ element 4873adfc5217SJeff Kirsher * and updating of the SPQ producer which involves a memory 4874adfc5217SJeff Kirsher * read and we will have to put a full memory barrier there 4875adfc5217SJeff Kirsher * (inside bnx2x_sp_post()). 4876adfc5217SJeff Kirsher */ 4877adfc5217SJeff Kirsher 4878adfc5217SJeff Kirsher return bnx2x_sp_post(bp, ramrod, o->cids[BNX2X_PRIMARY_CID_INDEX], 4879adfc5217SJeff Kirsher U64_HI(data_mapping), 4880adfc5217SJeff Kirsher U64_LO(data_mapping), ETH_CONNECTION_TYPE); 4881adfc5217SJeff Kirsher } 4882adfc5217SJeff Kirsher 4883adfc5217SJeff Kirsher static inline int bnx2x_q_send_setup_tx_only(struct bnx2x *bp, 4884adfc5217SJeff Kirsher struct bnx2x_queue_state_params *params) 4885adfc5217SJeff Kirsher { 4886adfc5217SJeff Kirsher struct bnx2x_queue_sp_obj *o = params->q_obj; 4887adfc5217SJeff Kirsher struct tx_queue_init_ramrod_data *rdata = 4888adfc5217SJeff Kirsher (struct tx_queue_init_ramrod_data *)o->rdata; 4889adfc5217SJeff Kirsher dma_addr_t data_mapping = o->rdata_mapping; 4890adfc5217SJeff Kirsher int ramrod = RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP; 4891adfc5217SJeff Kirsher struct bnx2x_queue_setup_tx_only_params *tx_only_params = 4892adfc5217SJeff Kirsher ¶ms->params.tx_only; 4893adfc5217SJeff Kirsher u8 cid_index = tx_only_params->cid_index; 4894adfc5217SJeff Kirsher 4895adfc5217SJeff Kirsher if (cid_index >= o->max_cos) { 4896adfc5217SJeff Kirsher BNX2X_ERR("queue[%d]: cid_index (%d) is out of range\n", 4897adfc5217SJeff Kirsher o->cl_id, cid_index); 4898adfc5217SJeff Kirsher return -EINVAL; 4899adfc5217SJeff Kirsher } 4900adfc5217SJeff Kirsher 490194f05b0fSJoe Perches DP(BNX2X_MSG_SP, "parameters received: cos: %d sp-id: %d\n", 4902adfc5217SJeff Kirsher tx_only_params->gen_params.cos, 4903adfc5217SJeff Kirsher tx_only_params->gen_params.spcl_id); 4904adfc5217SJeff Kirsher 4905adfc5217SJeff Kirsher /* Clear the ramrod data */ 4906adfc5217SJeff Kirsher memset(rdata, 0, sizeof(*rdata)); 4907adfc5217SJeff Kirsher 4908adfc5217SJeff Kirsher /* Fill the ramrod data */ 4909adfc5217SJeff Kirsher bnx2x_q_fill_setup_tx_only(bp, params, rdata); 4910adfc5217SJeff Kirsher 491151c1a580SMerav Sicron DP(BNX2X_MSG_SP, "sending tx-only ramrod: cid %d, client-id %d, sp-client id %d, cos %d\n", 491251c1a580SMerav Sicron o->cids[cid_index], rdata->general.client_id, 4913adfc5217SJeff Kirsher rdata->general.sp_client_id, rdata->general.cos); 4914adfc5217SJeff Kirsher 491516a5fd92SYuval Mintz /* No need for an explicit memory barrier here as long we would 4916adfc5217SJeff Kirsher * need to ensure the ordering of writing to the SPQ element 4917adfc5217SJeff Kirsher * and updating of the SPQ producer which involves a memory 4918adfc5217SJeff Kirsher * read and we will have to put a full memory barrier there 4919adfc5217SJeff Kirsher * (inside bnx2x_sp_post()). 4920adfc5217SJeff Kirsher */ 4921adfc5217SJeff Kirsher 4922adfc5217SJeff Kirsher return bnx2x_sp_post(bp, ramrod, o->cids[cid_index], 4923adfc5217SJeff Kirsher U64_HI(data_mapping), 4924adfc5217SJeff Kirsher U64_LO(data_mapping), ETH_CONNECTION_TYPE); 4925adfc5217SJeff Kirsher } 4926adfc5217SJeff Kirsher 4927adfc5217SJeff Kirsher static void bnx2x_q_fill_update_data(struct bnx2x *bp, 4928adfc5217SJeff Kirsher struct bnx2x_queue_sp_obj *obj, 4929adfc5217SJeff Kirsher struct bnx2x_queue_update_params *params, 4930adfc5217SJeff Kirsher struct client_update_ramrod_data *data) 4931adfc5217SJeff Kirsher { 4932adfc5217SJeff Kirsher /* Client ID of the client to update */ 4933adfc5217SJeff Kirsher data->client_id = obj->cl_id; 4934adfc5217SJeff Kirsher 4935adfc5217SJeff Kirsher /* Function ID of the client to update */ 4936adfc5217SJeff Kirsher data->func_id = obj->func_id; 4937adfc5217SJeff Kirsher 4938adfc5217SJeff Kirsher /* Default VLAN value */ 4939adfc5217SJeff Kirsher data->default_vlan = cpu_to_le16(params->def_vlan); 4940adfc5217SJeff Kirsher 4941adfc5217SJeff Kirsher /* Inner VLAN stripping */ 4942adfc5217SJeff Kirsher data->inner_vlan_removal_enable_flg = 4943adfc5217SJeff Kirsher test_bit(BNX2X_Q_UPDATE_IN_VLAN_REM, ¶ms->update_flags); 4944adfc5217SJeff Kirsher data->inner_vlan_removal_change_flg = 4945adfc5217SJeff Kirsher test_bit(BNX2X_Q_UPDATE_IN_VLAN_REM_CHNG, 4946adfc5217SJeff Kirsher ¶ms->update_flags); 4947adfc5217SJeff Kirsher 494816a5fd92SYuval Mintz /* Outer VLAN stripping */ 4949adfc5217SJeff Kirsher data->outer_vlan_removal_enable_flg = 4950adfc5217SJeff Kirsher test_bit(BNX2X_Q_UPDATE_OUT_VLAN_REM, ¶ms->update_flags); 4951adfc5217SJeff Kirsher data->outer_vlan_removal_change_flg = 4952adfc5217SJeff Kirsher test_bit(BNX2X_Q_UPDATE_OUT_VLAN_REM_CHNG, 4953adfc5217SJeff Kirsher ¶ms->update_flags); 4954adfc5217SJeff Kirsher 4955adfc5217SJeff Kirsher /* Drop packets that have source MAC that doesn't belong to this 4956adfc5217SJeff Kirsher * Queue. 4957adfc5217SJeff Kirsher */ 4958adfc5217SJeff Kirsher data->anti_spoofing_enable_flg = 4959adfc5217SJeff Kirsher test_bit(BNX2X_Q_UPDATE_ANTI_SPOOF, ¶ms->update_flags); 4960adfc5217SJeff Kirsher data->anti_spoofing_change_flg = 4961adfc5217SJeff Kirsher test_bit(BNX2X_Q_UPDATE_ANTI_SPOOF_CHNG, ¶ms->update_flags); 4962adfc5217SJeff Kirsher 4963adfc5217SJeff Kirsher /* Activate/Deactivate */ 4964adfc5217SJeff Kirsher data->activate_flg = 4965adfc5217SJeff Kirsher test_bit(BNX2X_Q_UPDATE_ACTIVATE, ¶ms->update_flags); 4966adfc5217SJeff Kirsher data->activate_change_flg = 4967adfc5217SJeff Kirsher test_bit(BNX2X_Q_UPDATE_ACTIVATE_CHNG, ¶ms->update_flags); 4968adfc5217SJeff Kirsher 4969adfc5217SJeff Kirsher /* Enable default VLAN */ 4970adfc5217SJeff Kirsher data->default_vlan_enable_flg = 4971adfc5217SJeff Kirsher test_bit(BNX2X_Q_UPDATE_DEF_VLAN_EN, ¶ms->update_flags); 4972adfc5217SJeff Kirsher data->default_vlan_change_flg = 4973adfc5217SJeff Kirsher test_bit(BNX2X_Q_UPDATE_DEF_VLAN_EN_CHNG, 4974adfc5217SJeff Kirsher ¶ms->update_flags); 4975adfc5217SJeff Kirsher 4976adfc5217SJeff Kirsher /* silent vlan removal */ 4977adfc5217SJeff Kirsher data->silent_vlan_change_flg = 4978adfc5217SJeff Kirsher test_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG, 4979adfc5217SJeff Kirsher ¶ms->update_flags); 4980adfc5217SJeff Kirsher data->silent_vlan_removal_flg = 4981adfc5217SJeff Kirsher test_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM, ¶ms->update_flags); 4982adfc5217SJeff Kirsher data->silent_vlan_value = cpu_to_le16(params->silent_removal_value); 4983adfc5217SJeff Kirsher data->silent_vlan_mask = cpu_to_le16(params->silent_removal_mask); 4984adfc5217SJeff Kirsher } 4985adfc5217SJeff Kirsher 4986adfc5217SJeff Kirsher static inline int bnx2x_q_send_update(struct bnx2x *bp, 4987adfc5217SJeff Kirsher struct bnx2x_queue_state_params *params) 4988adfc5217SJeff Kirsher { 4989adfc5217SJeff Kirsher struct bnx2x_queue_sp_obj *o = params->q_obj; 4990adfc5217SJeff Kirsher struct client_update_ramrod_data *rdata = 4991adfc5217SJeff Kirsher (struct client_update_ramrod_data *)o->rdata; 4992adfc5217SJeff Kirsher dma_addr_t data_mapping = o->rdata_mapping; 4993adfc5217SJeff Kirsher struct bnx2x_queue_update_params *update_params = 4994adfc5217SJeff Kirsher ¶ms->params.update; 4995adfc5217SJeff Kirsher u8 cid_index = update_params->cid_index; 4996adfc5217SJeff Kirsher 4997adfc5217SJeff Kirsher if (cid_index >= o->max_cos) { 4998adfc5217SJeff Kirsher BNX2X_ERR("queue[%d]: cid_index (%d) is out of range\n", 4999adfc5217SJeff Kirsher o->cl_id, cid_index); 5000adfc5217SJeff Kirsher return -EINVAL; 5001adfc5217SJeff Kirsher } 5002adfc5217SJeff Kirsher 5003adfc5217SJeff Kirsher /* Clear the ramrod data */ 5004adfc5217SJeff Kirsher memset(rdata, 0, sizeof(*rdata)); 5005adfc5217SJeff Kirsher 5006adfc5217SJeff Kirsher /* Fill the ramrod data */ 5007adfc5217SJeff Kirsher bnx2x_q_fill_update_data(bp, o, update_params, rdata); 5008adfc5217SJeff Kirsher 500916a5fd92SYuval Mintz /* No need for an explicit memory barrier here as long we would 5010adfc5217SJeff Kirsher * need to ensure the ordering of writing to the SPQ element 5011adfc5217SJeff Kirsher * and updating of the SPQ producer which involves a memory 5012adfc5217SJeff Kirsher * read and we will have to put a full memory barrier there 5013adfc5217SJeff Kirsher * (inside bnx2x_sp_post()). 5014adfc5217SJeff Kirsher */ 5015adfc5217SJeff Kirsher 5016adfc5217SJeff Kirsher return bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_CLIENT_UPDATE, 5017adfc5217SJeff Kirsher o->cids[cid_index], U64_HI(data_mapping), 5018adfc5217SJeff Kirsher U64_LO(data_mapping), ETH_CONNECTION_TYPE); 5019adfc5217SJeff Kirsher } 5020adfc5217SJeff Kirsher 5021adfc5217SJeff Kirsher /** 5022adfc5217SJeff Kirsher * bnx2x_q_send_deactivate - send DEACTIVATE command 5023adfc5217SJeff Kirsher * 5024adfc5217SJeff Kirsher * @bp: device handle 5025adfc5217SJeff Kirsher * @params: 5026adfc5217SJeff Kirsher * 5027adfc5217SJeff Kirsher * implemented using the UPDATE command. 5028adfc5217SJeff Kirsher */ 5029adfc5217SJeff Kirsher static inline int bnx2x_q_send_deactivate(struct bnx2x *bp, 5030adfc5217SJeff Kirsher struct bnx2x_queue_state_params *params) 5031adfc5217SJeff Kirsher { 5032adfc5217SJeff Kirsher struct bnx2x_queue_update_params *update = ¶ms->params.update; 5033adfc5217SJeff Kirsher 5034adfc5217SJeff Kirsher memset(update, 0, sizeof(*update)); 5035adfc5217SJeff Kirsher 5036adfc5217SJeff Kirsher __set_bit(BNX2X_Q_UPDATE_ACTIVATE_CHNG, &update->update_flags); 5037adfc5217SJeff Kirsher 5038adfc5217SJeff Kirsher return bnx2x_q_send_update(bp, params); 5039adfc5217SJeff Kirsher } 5040adfc5217SJeff Kirsher 5041adfc5217SJeff Kirsher /** 5042adfc5217SJeff Kirsher * bnx2x_q_send_activate - send ACTIVATE command 5043adfc5217SJeff Kirsher * 5044adfc5217SJeff Kirsher * @bp: device handle 5045adfc5217SJeff Kirsher * @params: 5046adfc5217SJeff Kirsher * 5047adfc5217SJeff Kirsher * implemented using the UPDATE command. 5048adfc5217SJeff Kirsher */ 5049adfc5217SJeff Kirsher static inline int bnx2x_q_send_activate(struct bnx2x *bp, 5050adfc5217SJeff Kirsher struct bnx2x_queue_state_params *params) 5051adfc5217SJeff Kirsher { 5052adfc5217SJeff Kirsher struct bnx2x_queue_update_params *update = ¶ms->params.update; 5053adfc5217SJeff Kirsher 5054adfc5217SJeff Kirsher memset(update, 0, sizeof(*update)); 5055adfc5217SJeff Kirsher 5056adfc5217SJeff Kirsher __set_bit(BNX2X_Q_UPDATE_ACTIVATE, &update->update_flags); 5057adfc5217SJeff Kirsher __set_bit(BNX2X_Q_UPDATE_ACTIVATE_CHNG, &update->update_flags); 5058adfc5217SJeff Kirsher 5059adfc5217SJeff Kirsher return bnx2x_q_send_update(bp, params); 5060adfc5217SJeff Kirsher } 5061adfc5217SJeff Kirsher 5062adfc5217SJeff Kirsher static inline int bnx2x_q_send_update_tpa(struct bnx2x *bp, 5063adfc5217SJeff Kirsher struct bnx2x_queue_state_params *params) 5064adfc5217SJeff Kirsher { 5065adfc5217SJeff Kirsher /* TODO: Not implemented yet. */ 5066adfc5217SJeff Kirsher return -1; 5067adfc5217SJeff Kirsher } 5068adfc5217SJeff Kirsher 5069adfc5217SJeff Kirsher static inline int bnx2x_q_send_halt(struct bnx2x *bp, 5070adfc5217SJeff Kirsher struct bnx2x_queue_state_params *params) 5071adfc5217SJeff Kirsher { 5072adfc5217SJeff Kirsher struct bnx2x_queue_sp_obj *o = params->q_obj; 5073adfc5217SJeff Kirsher 5074adfc5217SJeff Kirsher return bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_HALT, 5075adfc5217SJeff Kirsher o->cids[BNX2X_PRIMARY_CID_INDEX], 0, o->cl_id, 5076adfc5217SJeff Kirsher ETH_CONNECTION_TYPE); 5077adfc5217SJeff Kirsher } 5078adfc5217SJeff Kirsher 5079adfc5217SJeff Kirsher static inline int bnx2x_q_send_cfc_del(struct bnx2x *bp, 5080adfc5217SJeff Kirsher struct bnx2x_queue_state_params *params) 5081adfc5217SJeff Kirsher { 5082adfc5217SJeff Kirsher struct bnx2x_queue_sp_obj *o = params->q_obj; 5083adfc5217SJeff Kirsher u8 cid_idx = params->params.cfc_del.cid_index; 5084adfc5217SJeff Kirsher 5085adfc5217SJeff Kirsher if (cid_idx >= o->max_cos) { 5086adfc5217SJeff Kirsher BNX2X_ERR("queue[%d]: cid_index (%d) is out of range\n", 5087adfc5217SJeff Kirsher o->cl_id, cid_idx); 5088adfc5217SJeff Kirsher return -EINVAL; 5089adfc5217SJeff Kirsher } 5090adfc5217SJeff Kirsher 5091adfc5217SJeff Kirsher return bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_CFC_DEL, 5092adfc5217SJeff Kirsher o->cids[cid_idx], 0, 0, NONE_CONNECTION_TYPE); 5093adfc5217SJeff Kirsher } 5094adfc5217SJeff Kirsher 5095adfc5217SJeff Kirsher static inline int bnx2x_q_send_terminate(struct bnx2x *bp, 5096adfc5217SJeff Kirsher struct bnx2x_queue_state_params *params) 5097adfc5217SJeff Kirsher { 5098adfc5217SJeff Kirsher struct bnx2x_queue_sp_obj *o = params->q_obj; 5099adfc5217SJeff Kirsher u8 cid_index = params->params.terminate.cid_index; 5100adfc5217SJeff Kirsher 5101adfc5217SJeff Kirsher if (cid_index >= o->max_cos) { 5102adfc5217SJeff Kirsher BNX2X_ERR("queue[%d]: cid_index (%d) is out of range\n", 5103adfc5217SJeff Kirsher o->cl_id, cid_index); 5104adfc5217SJeff Kirsher return -EINVAL; 5105adfc5217SJeff Kirsher } 5106adfc5217SJeff Kirsher 5107adfc5217SJeff Kirsher return bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_TERMINATE, 5108adfc5217SJeff Kirsher o->cids[cid_index], 0, 0, ETH_CONNECTION_TYPE); 5109adfc5217SJeff Kirsher } 5110adfc5217SJeff Kirsher 5111adfc5217SJeff Kirsher static inline int bnx2x_q_send_empty(struct bnx2x *bp, 5112adfc5217SJeff Kirsher struct bnx2x_queue_state_params *params) 5113adfc5217SJeff Kirsher { 5114adfc5217SJeff Kirsher struct bnx2x_queue_sp_obj *o = params->q_obj; 5115adfc5217SJeff Kirsher 5116adfc5217SJeff Kirsher return bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_EMPTY, 5117adfc5217SJeff Kirsher o->cids[BNX2X_PRIMARY_CID_INDEX], 0, 0, 5118adfc5217SJeff Kirsher ETH_CONNECTION_TYPE); 5119adfc5217SJeff Kirsher } 5120adfc5217SJeff Kirsher 5121adfc5217SJeff Kirsher static inline int bnx2x_queue_send_cmd_cmn(struct bnx2x *bp, 5122adfc5217SJeff Kirsher struct bnx2x_queue_state_params *params) 5123adfc5217SJeff Kirsher { 5124adfc5217SJeff Kirsher switch (params->cmd) { 5125adfc5217SJeff Kirsher case BNX2X_Q_CMD_INIT: 5126adfc5217SJeff Kirsher return bnx2x_q_init(bp, params); 5127adfc5217SJeff Kirsher case BNX2X_Q_CMD_SETUP_TX_ONLY: 5128adfc5217SJeff Kirsher return bnx2x_q_send_setup_tx_only(bp, params); 5129adfc5217SJeff Kirsher case BNX2X_Q_CMD_DEACTIVATE: 5130adfc5217SJeff Kirsher return bnx2x_q_send_deactivate(bp, params); 5131adfc5217SJeff Kirsher case BNX2X_Q_CMD_ACTIVATE: 5132adfc5217SJeff Kirsher return bnx2x_q_send_activate(bp, params); 5133adfc5217SJeff Kirsher case BNX2X_Q_CMD_UPDATE: 5134adfc5217SJeff Kirsher return bnx2x_q_send_update(bp, params); 5135adfc5217SJeff Kirsher case BNX2X_Q_CMD_UPDATE_TPA: 5136adfc5217SJeff Kirsher return bnx2x_q_send_update_tpa(bp, params); 5137adfc5217SJeff Kirsher case BNX2X_Q_CMD_HALT: 5138adfc5217SJeff Kirsher return bnx2x_q_send_halt(bp, params); 5139adfc5217SJeff Kirsher case BNX2X_Q_CMD_CFC_DEL: 5140adfc5217SJeff Kirsher return bnx2x_q_send_cfc_del(bp, params); 5141adfc5217SJeff Kirsher case BNX2X_Q_CMD_TERMINATE: 5142adfc5217SJeff Kirsher return bnx2x_q_send_terminate(bp, params); 5143adfc5217SJeff Kirsher case BNX2X_Q_CMD_EMPTY: 5144adfc5217SJeff Kirsher return bnx2x_q_send_empty(bp, params); 5145adfc5217SJeff Kirsher default: 5146adfc5217SJeff Kirsher BNX2X_ERR("Unknown command: %d\n", params->cmd); 5147adfc5217SJeff Kirsher return -EINVAL; 5148adfc5217SJeff Kirsher } 5149adfc5217SJeff Kirsher } 5150adfc5217SJeff Kirsher 5151adfc5217SJeff Kirsher static int bnx2x_queue_send_cmd_e1x(struct bnx2x *bp, 5152adfc5217SJeff Kirsher struct bnx2x_queue_state_params *params) 5153adfc5217SJeff Kirsher { 5154adfc5217SJeff Kirsher switch (params->cmd) { 5155adfc5217SJeff Kirsher case BNX2X_Q_CMD_SETUP: 5156adfc5217SJeff Kirsher return bnx2x_q_send_setup_e1x(bp, params); 5157adfc5217SJeff Kirsher case BNX2X_Q_CMD_INIT: 5158adfc5217SJeff Kirsher case BNX2X_Q_CMD_SETUP_TX_ONLY: 5159adfc5217SJeff Kirsher case BNX2X_Q_CMD_DEACTIVATE: 5160adfc5217SJeff Kirsher case BNX2X_Q_CMD_ACTIVATE: 5161adfc5217SJeff Kirsher case BNX2X_Q_CMD_UPDATE: 5162adfc5217SJeff Kirsher case BNX2X_Q_CMD_UPDATE_TPA: 5163adfc5217SJeff Kirsher case BNX2X_Q_CMD_HALT: 5164adfc5217SJeff Kirsher case BNX2X_Q_CMD_CFC_DEL: 5165adfc5217SJeff Kirsher case BNX2X_Q_CMD_TERMINATE: 5166adfc5217SJeff Kirsher case BNX2X_Q_CMD_EMPTY: 5167adfc5217SJeff Kirsher return bnx2x_queue_send_cmd_cmn(bp, params); 5168adfc5217SJeff Kirsher default: 5169adfc5217SJeff Kirsher BNX2X_ERR("Unknown command: %d\n", params->cmd); 5170adfc5217SJeff Kirsher return -EINVAL; 5171adfc5217SJeff Kirsher } 5172adfc5217SJeff Kirsher } 5173adfc5217SJeff Kirsher 5174adfc5217SJeff Kirsher static int bnx2x_queue_send_cmd_e2(struct bnx2x *bp, 5175adfc5217SJeff Kirsher struct bnx2x_queue_state_params *params) 5176adfc5217SJeff Kirsher { 5177adfc5217SJeff Kirsher switch (params->cmd) { 5178adfc5217SJeff Kirsher case BNX2X_Q_CMD_SETUP: 5179adfc5217SJeff Kirsher return bnx2x_q_send_setup_e2(bp, params); 5180adfc5217SJeff Kirsher case BNX2X_Q_CMD_INIT: 5181adfc5217SJeff Kirsher case BNX2X_Q_CMD_SETUP_TX_ONLY: 5182adfc5217SJeff Kirsher case BNX2X_Q_CMD_DEACTIVATE: 5183adfc5217SJeff Kirsher case BNX2X_Q_CMD_ACTIVATE: 5184adfc5217SJeff Kirsher case BNX2X_Q_CMD_UPDATE: 5185adfc5217SJeff Kirsher case BNX2X_Q_CMD_UPDATE_TPA: 5186adfc5217SJeff Kirsher case BNX2X_Q_CMD_HALT: 5187adfc5217SJeff Kirsher case BNX2X_Q_CMD_CFC_DEL: 5188adfc5217SJeff Kirsher case BNX2X_Q_CMD_TERMINATE: 5189adfc5217SJeff Kirsher case BNX2X_Q_CMD_EMPTY: 5190adfc5217SJeff Kirsher return bnx2x_queue_send_cmd_cmn(bp, params); 5191adfc5217SJeff Kirsher default: 5192adfc5217SJeff Kirsher BNX2X_ERR("Unknown command: %d\n", params->cmd); 5193adfc5217SJeff Kirsher return -EINVAL; 5194adfc5217SJeff Kirsher } 5195adfc5217SJeff Kirsher } 5196adfc5217SJeff Kirsher 5197adfc5217SJeff Kirsher /** 5198adfc5217SJeff Kirsher * bnx2x_queue_chk_transition - check state machine of a regular Queue 5199adfc5217SJeff Kirsher * 5200adfc5217SJeff Kirsher * @bp: device handle 5201adfc5217SJeff Kirsher * @o: 5202adfc5217SJeff Kirsher * @params: 5203adfc5217SJeff Kirsher * 5204adfc5217SJeff Kirsher * (not Forwarding) 5205adfc5217SJeff Kirsher * It both checks if the requested command is legal in a current 5206adfc5217SJeff Kirsher * state and, if it's legal, sets a `next_state' in the object 5207adfc5217SJeff Kirsher * that will be used in the completion flow to set the `state' 5208adfc5217SJeff Kirsher * of the object. 5209adfc5217SJeff Kirsher * 5210adfc5217SJeff Kirsher * returns 0 if a requested command is a legal transition, 5211adfc5217SJeff Kirsher * -EINVAL otherwise. 5212adfc5217SJeff Kirsher */ 5213adfc5217SJeff Kirsher static int bnx2x_queue_chk_transition(struct bnx2x *bp, 5214adfc5217SJeff Kirsher struct bnx2x_queue_sp_obj *o, 5215adfc5217SJeff Kirsher struct bnx2x_queue_state_params *params) 5216adfc5217SJeff Kirsher { 5217adfc5217SJeff Kirsher enum bnx2x_q_state state = o->state, next_state = BNX2X_Q_STATE_MAX; 5218adfc5217SJeff Kirsher enum bnx2x_queue_cmd cmd = params->cmd; 5219adfc5217SJeff Kirsher struct bnx2x_queue_update_params *update_params = 5220adfc5217SJeff Kirsher ¶ms->params.update; 5221adfc5217SJeff Kirsher u8 next_tx_only = o->num_tx_only; 5222adfc5217SJeff Kirsher 522316a5fd92SYuval Mintz /* Forget all pending for completion commands if a driver only state 5224adfc5217SJeff Kirsher * transition has been requested. 5225adfc5217SJeff Kirsher */ 5226adfc5217SJeff Kirsher if (test_bit(RAMROD_DRV_CLR_ONLY, ¶ms->ramrod_flags)) { 5227adfc5217SJeff Kirsher o->pending = 0; 5228adfc5217SJeff Kirsher o->next_state = BNX2X_Q_STATE_MAX; 5229adfc5217SJeff Kirsher } 5230adfc5217SJeff Kirsher 523116a5fd92SYuval Mintz /* Don't allow a next state transition if we are in the middle of 5232adfc5217SJeff Kirsher * the previous one. 5233adfc5217SJeff Kirsher */ 523404c46736SYuval Mintz if (o->pending) { 523504c46736SYuval Mintz BNX2X_ERR("Blocking transition since pending was %lx\n", 523604c46736SYuval Mintz o->pending); 5237adfc5217SJeff Kirsher return -EBUSY; 523804c46736SYuval Mintz } 5239adfc5217SJeff Kirsher 5240adfc5217SJeff Kirsher switch (state) { 5241adfc5217SJeff Kirsher case BNX2X_Q_STATE_RESET: 5242adfc5217SJeff Kirsher if (cmd == BNX2X_Q_CMD_INIT) 5243adfc5217SJeff Kirsher next_state = BNX2X_Q_STATE_INITIALIZED; 5244adfc5217SJeff Kirsher 5245adfc5217SJeff Kirsher break; 5246adfc5217SJeff Kirsher case BNX2X_Q_STATE_INITIALIZED: 5247adfc5217SJeff Kirsher if (cmd == BNX2X_Q_CMD_SETUP) { 5248adfc5217SJeff Kirsher if (test_bit(BNX2X_Q_FLG_ACTIVE, 5249adfc5217SJeff Kirsher ¶ms->params.setup.flags)) 5250adfc5217SJeff Kirsher next_state = BNX2X_Q_STATE_ACTIVE; 5251adfc5217SJeff Kirsher else 5252adfc5217SJeff Kirsher next_state = BNX2X_Q_STATE_INACTIVE; 5253adfc5217SJeff Kirsher } 5254adfc5217SJeff Kirsher 5255adfc5217SJeff Kirsher break; 5256adfc5217SJeff Kirsher case BNX2X_Q_STATE_ACTIVE: 5257adfc5217SJeff Kirsher if (cmd == BNX2X_Q_CMD_DEACTIVATE) 5258adfc5217SJeff Kirsher next_state = BNX2X_Q_STATE_INACTIVE; 5259adfc5217SJeff Kirsher 5260adfc5217SJeff Kirsher else if ((cmd == BNX2X_Q_CMD_EMPTY) || 5261adfc5217SJeff Kirsher (cmd == BNX2X_Q_CMD_UPDATE_TPA)) 5262adfc5217SJeff Kirsher next_state = BNX2X_Q_STATE_ACTIVE; 5263adfc5217SJeff Kirsher 5264adfc5217SJeff Kirsher else if (cmd == BNX2X_Q_CMD_SETUP_TX_ONLY) { 5265adfc5217SJeff Kirsher next_state = BNX2X_Q_STATE_MULTI_COS; 5266adfc5217SJeff Kirsher next_tx_only = 1; 5267adfc5217SJeff Kirsher } 5268adfc5217SJeff Kirsher 5269adfc5217SJeff Kirsher else if (cmd == BNX2X_Q_CMD_HALT) 5270adfc5217SJeff Kirsher next_state = BNX2X_Q_STATE_STOPPED; 5271adfc5217SJeff Kirsher 5272adfc5217SJeff Kirsher else if (cmd == BNX2X_Q_CMD_UPDATE) { 5273adfc5217SJeff Kirsher /* If "active" state change is requested, update the 5274adfc5217SJeff Kirsher * state accordingly. 5275adfc5217SJeff Kirsher */ 5276adfc5217SJeff Kirsher if (test_bit(BNX2X_Q_UPDATE_ACTIVATE_CHNG, 5277adfc5217SJeff Kirsher &update_params->update_flags) && 5278adfc5217SJeff Kirsher !test_bit(BNX2X_Q_UPDATE_ACTIVATE, 5279adfc5217SJeff Kirsher &update_params->update_flags)) 5280adfc5217SJeff Kirsher next_state = BNX2X_Q_STATE_INACTIVE; 5281adfc5217SJeff Kirsher else 5282adfc5217SJeff Kirsher next_state = BNX2X_Q_STATE_ACTIVE; 5283adfc5217SJeff Kirsher } 5284adfc5217SJeff Kirsher 5285adfc5217SJeff Kirsher break; 5286adfc5217SJeff Kirsher case BNX2X_Q_STATE_MULTI_COS: 5287adfc5217SJeff Kirsher if (cmd == BNX2X_Q_CMD_TERMINATE) 5288adfc5217SJeff Kirsher next_state = BNX2X_Q_STATE_MCOS_TERMINATED; 5289adfc5217SJeff Kirsher 5290adfc5217SJeff Kirsher else if (cmd == BNX2X_Q_CMD_SETUP_TX_ONLY) { 5291adfc5217SJeff Kirsher next_state = BNX2X_Q_STATE_MULTI_COS; 5292adfc5217SJeff Kirsher next_tx_only = o->num_tx_only + 1; 5293adfc5217SJeff Kirsher } 5294adfc5217SJeff Kirsher 5295adfc5217SJeff Kirsher else if ((cmd == BNX2X_Q_CMD_EMPTY) || 5296adfc5217SJeff Kirsher (cmd == BNX2X_Q_CMD_UPDATE_TPA)) 5297adfc5217SJeff Kirsher next_state = BNX2X_Q_STATE_MULTI_COS; 5298adfc5217SJeff Kirsher 5299adfc5217SJeff Kirsher else if (cmd == BNX2X_Q_CMD_UPDATE) { 5300adfc5217SJeff Kirsher /* If "active" state change is requested, update the 5301adfc5217SJeff Kirsher * state accordingly. 5302adfc5217SJeff Kirsher */ 5303adfc5217SJeff Kirsher if (test_bit(BNX2X_Q_UPDATE_ACTIVATE_CHNG, 5304adfc5217SJeff Kirsher &update_params->update_flags) && 5305adfc5217SJeff Kirsher !test_bit(BNX2X_Q_UPDATE_ACTIVATE, 5306adfc5217SJeff Kirsher &update_params->update_flags)) 5307adfc5217SJeff Kirsher next_state = BNX2X_Q_STATE_INACTIVE; 5308adfc5217SJeff Kirsher else 5309adfc5217SJeff Kirsher next_state = BNX2X_Q_STATE_MULTI_COS; 5310adfc5217SJeff Kirsher } 5311adfc5217SJeff Kirsher 5312adfc5217SJeff Kirsher break; 5313adfc5217SJeff Kirsher case BNX2X_Q_STATE_MCOS_TERMINATED: 5314adfc5217SJeff Kirsher if (cmd == BNX2X_Q_CMD_CFC_DEL) { 5315adfc5217SJeff Kirsher next_tx_only = o->num_tx_only - 1; 5316adfc5217SJeff Kirsher if (next_tx_only == 0) 5317adfc5217SJeff Kirsher next_state = BNX2X_Q_STATE_ACTIVE; 5318adfc5217SJeff Kirsher else 5319adfc5217SJeff Kirsher next_state = BNX2X_Q_STATE_MULTI_COS; 5320adfc5217SJeff Kirsher } 5321adfc5217SJeff Kirsher 5322adfc5217SJeff Kirsher break; 5323adfc5217SJeff Kirsher case BNX2X_Q_STATE_INACTIVE: 5324adfc5217SJeff Kirsher if (cmd == BNX2X_Q_CMD_ACTIVATE) 5325adfc5217SJeff Kirsher next_state = BNX2X_Q_STATE_ACTIVE; 5326adfc5217SJeff Kirsher 5327adfc5217SJeff Kirsher else if ((cmd == BNX2X_Q_CMD_EMPTY) || 5328adfc5217SJeff Kirsher (cmd == BNX2X_Q_CMD_UPDATE_TPA)) 5329adfc5217SJeff Kirsher next_state = BNX2X_Q_STATE_INACTIVE; 5330adfc5217SJeff Kirsher 5331adfc5217SJeff Kirsher else if (cmd == BNX2X_Q_CMD_HALT) 5332adfc5217SJeff Kirsher next_state = BNX2X_Q_STATE_STOPPED; 5333adfc5217SJeff Kirsher 5334adfc5217SJeff Kirsher else if (cmd == BNX2X_Q_CMD_UPDATE) { 5335adfc5217SJeff Kirsher /* If "active" state change is requested, update the 5336adfc5217SJeff Kirsher * state accordingly. 5337adfc5217SJeff Kirsher */ 5338adfc5217SJeff Kirsher if (test_bit(BNX2X_Q_UPDATE_ACTIVATE_CHNG, 5339adfc5217SJeff Kirsher &update_params->update_flags) && 5340adfc5217SJeff Kirsher test_bit(BNX2X_Q_UPDATE_ACTIVATE, 5341adfc5217SJeff Kirsher &update_params->update_flags)){ 5342adfc5217SJeff Kirsher if (o->num_tx_only == 0) 5343adfc5217SJeff Kirsher next_state = BNX2X_Q_STATE_ACTIVE; 5344adfc5217SJeff Kirsher else /* tx only queues exist for this queue */ 5345adfc5217SJeff Kirsher next_state = BNX2X_Q_STATE_MULTI_COS; 5346adfc5217SJeff Kirsher } else 5347adfc5217SJeff Kirsher next_state = BNX2X_Q_STATE_INACTIVE; 5348adfc5217SJeff Kirsher } 5349adfc5217SJeff Kirsher 5350adfc5217SJeff Kirsher break; 5351adfc5217SJeff Kirsher case BNX2X_Q_STATE_STOPPED: 5352adfc5217SJeff Kirsher if (cmd == BNX2X_Q_CMD_TERMINATE) 5353adfc5217SJeff Kirsher next_state = BNX2X_Q_STATE_TERMINATED; 5354adfc5217SJeff Kirsher 5355adfc5217SJeff Kirsher break; 5356adfc5217SJeff Kirsher case BNX2X_Q_STATE_TERMINATED: 5357adfc5217SJeff Kirsher if (cmd == BNX2X_Q_CMD_CFC_DEL) 5358adfc5217SJeff Kirsher next_state = BNX2X_Q_STATE_RESET; 5359adfc5217SJeff Kirsher 5360adfc5217SJeff Kirsher break; 5361adfc5217SJeff Kirsher default: 5362adfc5217SJeff Kirsher BNX2X_ERR("Illegal state: %d\n", state); 5363adfc5217SJeff Kirsher } 5364adfc5217SJeff Kirsher 5365adfc5217SJeff Kirsher /* Transition is assured */ 5366adfc5217SJeff Kirsher if (next_state != BNX2X_Q_STATE_MAX) { 5367adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "Good state transition: %d(%d)->%d\n", 5368adfc5217SJeff Kirsher state, cmd, next_state); 5369adfc5217SJeff Kirsher o->next_state = next_state; 5370adfc5217SJeff Kirsher o->next_tx_only = next_tx_only; 5371adfc5217SJeff Kirsher return 0; 5372adfc5217SJeff Kirsher } 5373adfc5217SJeff Kirsher 5374adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "Bad state transition request: %d %d\n", state, cmd); 5375adfc5217SJeff Kirsher 5376adfc5217SJeff Kirsher return -EINVAL; 5377adfc5217SJeff Kirsher } 5378adfc5217SJeff Kirsher 5379adfc5217SJeff Kirsher void bnx2x_init_queue_obj(struct bnx2x *bp, 5380adfc5217SJeff Kirsher struct bnx2x_queue_sp_obj *obj, 5381adfc5217SJeff Kirsher u8 cl_id, u32 *cids, u8 cid_cnt, u8 func_id, 5382adfc5217SJeff Kirsher void *rdata, 5383adfc5217SJeff Kirsher dma_addr_t rdata_mapping, unsigned long type) 5384adfc5217SJeff Kirsher { 5385adfc5217SJeff Kirsher memset(obj, 0, sizeof(*obj)); 5386adfc5217SJeff Kirsher 5387adfc5217SJeff Kirsher /* We support only BNX2X_MULTI_TX_COS Tx CoS at the moment */ 5388adfc5217SJeff Kirsher BUG_ON(BNX2X_MULTI_TX_COS < cid_cnt); 5389adfc5217SJeff Kirsher 5390adfc5217SJeff Kirsher memcpy(obj->cids, cids, sizeof(obj->cids[0]) * cid_cnt); 5391adfc5217SJeff Kirsher obj->max_cos = cid_cnt; 5392adfc5217SJeff Kirsher obj->cl_id = cl_id; 5393adfc5217SJeff Kirsher obj->func_id = func_id; 5394adfc5217SJeff Kirsher obj->rdata = rdata; 5395adfc5217SJeff Kirsher obj->rdata_mapping = rdata_mapping; 5396adfc5217SJeff Kirsher obj->type = type; 5397adfc5217SJeff Kirsher obj->next_state = BNX2X_Q_STATE_MAX; 5398adfc5217SJeff Kirsher 5399adfc5217SJeff Kirsher if (CHIP_IS_E1x(bp)) 5400adfc5217SJeff Kirsher obj->send_cmd = bnx2x_queue_send_cmd_e1x; 5401adfc5217SJeff Kirsher else 5402adfc5217SJeff Kirsher obj->send_cmd = bnx2x_queue_send_cmd_e2; 5403adfc5217SJeff Kirsher 5404adfc5217SJeff Kirsher obj->check_transition = bnx2x_queue_chk_transition; 5405adfc5217SJeff Kirsher 5406adfc5217SJeff Kirsher obj->complete_cmd = bnx2x_queue_comp_cmd; 5407adfc5217SJeff Kirsher obj->wait_comp = bnx2x_queue_wait_comp; 5408adfc5217SJeff Kirsher obj->set_pending = bnx2x_queue_set_pending; 5409adfc5217SJeff Kirsher } 5410adfc5217SJeff Kirsher 541167c431a5SAriel Elior /* return a queue object's logical state*/ 541267c431a5SAriel Elior int bnx2x_get_q_logical_state(struct bnx2x *bp, 541367c431a5SAriel Elior struct bnx2x_queue_sp_obj *obj) 541467c431a5SAriel Elior { 541567c431a5SAriel Elior switch (obj->state) { 541667c431a5SAriel Elior case BNX2X_Q_STATE_ACTIVE: 541767c431a5SAriel Elior case BNX2X_Q_STATE_MULTI_COS: 541867c431a5SAriel Elior return BNX2X_Q_LOGICAL_STATE_ACTIVE; 541967c431a5SAriel Elior case BNX2X_Q_STATE_RESET: 542067c431a5SAriel Elior case BNX2X_Q_STATE_INITIALIZED: 542167c431a5SAriel Elior case BNX2X_Q_STATE_MCOS_TERMINATED: 542267c431a5SAriel Elior case BNX2X_Q_STATE_INACTIVE: 542367c431a5SAriel Elior case BNX2X_Q_STATE_STOPPED: 542467c431a5SAriel Elior case BNX2X_Q_STATE_TERMINATED: 542567c431a5SAriel Elior case BNX2X_Q_STATE_FLRED: 542667c431a5SAriel Elior return BNX2X_Q_LOGICAL_STATE_STOPPED; 542767c431a5SAriel Elior default: 542867c431a5SAriel Elior return -EINVAL; 542967c431a5SAriel Elior } 543067c431a5SAriel Elior } 543167c431a5SAriel Elior 5432adfc5217SJeff Kirsher /********************** Function state object *********************************/ 5433adfc5217SJeff Kirsher enum bnx2x_func_state bnx2x_func_get_state(struct bnx2x *bp, 5434adfc5217SJeff Kirsher struct bnx2x_func_sp_obj *o) 5435adfc5217SJeff Kirsher { 5436adfc5217SJeff Kirsher /* in the middle of transaction - return INVALID state */ 5437adfc5217SJeff Kirsher if (o->pending) 5438adfc5217SJeff Kirsher return BNX2X_F_STATE_MAX; 5439adfc5217SJeff Kirsher 544016a5fd92SYuval Mintz /* unsure the order of reading of o->pending and o->state 5441adfc5217SJeff Kirsher * o->pending should be read first 5442adfc5217SJeff Kirsher */ 5443adfc5217SJeff Kirsher rmb(); 5444adfc5217SJeff Kirsher 5445adfc5217SJeff Kirsher return o->state; 5446adfc5217SJeff Kirsher } 5447adfc5217SJeff Kirsher 5448adfc5217SJeff Kirsher static int bnx2x_func_wait_comp(struct bnx2x *bp, 5449adfc5217SJeff Kirsher struct bnx2x_func_sp_obj *o, 5450adfc5217SJeff Kirsher enum bnx2x_func_cmd cmd) 5451adfc5217SJeff Kirsher { 5452adfc5217SJeff Kirsher return bnx2x_state_wait(bp, cmd, &o->pending); 5453adfc5217SJeff Kirsher } 5454adfc5217SJeff Kirsher 5455adfc5217SJeff Kirsher /** 5456adfc5217SJeff Kirsher * bnx2x_func_state_change_comp - complete the state machine transition 5457adfc5217SJeff Kirsher * 5458adfc5217SJeff Kirsher * @bp: device handle 5459adfc5217SJeff Kirsher * @o: 5460adfc5217SJeff Kirsher * @cmd: 5461adfc5217SJeff Kirsher * 5462adfc5217SJeff Kirsher * Called on state change transition. Completes the state 5463adfc5217SJeff Kirsher * machine transition only - no HW interaction. 5464adfc5217SJeff Kirsher */ 5465adfc5217SJeff Kirsher static inline int bnx2x_func_state_change_comp(struct bnx2x *bp, 5466adfc5217SJeff Kirsher struct bnx2x_func_sp_obj *o, 5467adfc5217SJeff Kirsher enum bnx2x_func_cmd cmd) 5468adfc5217SJeff Kirsher { 5469adfc5217SJeff Kirsher unsigned long cur_pending = o->pending; 5470adfc5217SJeff Kirsher 5471adfc5217SJeff Kirsher if (!test_and_clear_bit(cmd, &cur_pending)) { 547251c1a580SMerav Sicron BNX2X_ERR("Bad MC reply %d for func %d in state %d pending 0x%lx, next_state %d\n", 547351c1a580SMerav Sicron cmd, BP_FUNC(bp), o->state, 547451c1a580SMerav Sicron cur_pending, o->next_state); 5475adfc5217SJeff Kirsher return -EINVAL; 5476adfc5217SJeff Kirsher } 5477adfc5217SJeff Kirsher 547894f05b0fSJoe Perches DP(BNX2X_MSG_SP, 547994f05b0fSJoe Perches "Completing command %d for func %d, setting state to %d\n", 548094f05b0fSJoe Perches cmd, BP_FUNC(bp), o->next_state); 5481adfc5217SJeff Kirsher 5482adfc5217SJeff Kirsher o->state = o->next_state; 5483adfc5217SJeff Kirsher o->next_state = BNX2X_F_STATE_MAX; 5484adfc5217SJeff Kirsher 5485adfc5217SJeff Kirsher /* It's important that o->state and o->next_state are 5486adfc5217SJeff Kirsher * updated before o->pending. 5487adfc5217SJeff Kirsher */ 5488adfc5217SJeff Kirsher wmb(); 5489adfc5217SJeff Kirsher 5490adfc5217SJeff Kirsher clear_bit(cmd, &o->pending); 5491adfc5217SJeff Kirsher smp_mb__after_clear_bit(); 5492adfc5217SJeff Kirsher 5493adfc5217SJeff Kirsher return 0; 5494adfc5217SJeff Kirsher } 5495adfc5217SJeff Kirsher 5496adfc5217SJeff Kirsher /** 5497adfc5217SJeff Kirsher * bnx2x_func_comp_cmd - complete the state change command 5498adfc5217SJeff Kirsher * 5499adfc5217SJeff Kirsher * @bp: device handle 5500adfc5217SJeff Kirsher * @o: 5501adfc5217SJeff Kirsher * @cmd: 5502adfc5217SJeff Kirsher * 5503adfc5217SJeff Kirsher * Checks that the arrived completion is expected. 5504adfc5217SJeff Kirsher */ 5505adfc5217SJeff Kirsher static int bnx2x_func_comp_cmd(struct bnx2x *bp, 5506adfc5217SJeff Kirsher struct bnx2x_func_sp_obj *o, 5507adfc5217SJeff Kirsher enum bnx2x_func_cmd cmd) 5508adfc5217SJeff Kirsher { 5509adfc5217SJeff Kirsher /* Complete the state machine part first, check if it's a 5510adfc5217SJeff Kirsher * legal completion. 5511adfc5217SJeff Kirsher */ 5512adfc5217SJeff Kirsher int rc = bnx2x_func_state_change_comp(bp, o, cmd); 5513adfc5217SJeff Kirsher return rc; 5514adfc5217SJeff Kirsher } 5515adfc5217SJeff Kirsher 5516adfc5217SJeff Kirsher /** 5517adfc5217SJeff Kirsher * bnx2x_func_chk_transition - perform function state machine transition 5518adfc5217SJeff Kirsher * 5519adfc5217SJeff Kirsher * @bp: device handle 5520adfc5217SJeff Kirsher * @o: 5521adfc5217SJeff Kirsher * @params: 5522adfc5217SJeff Kirsher * 5523adfc5217SJeff Kirsher * It both checks if the requested command is legal in a current 5524adfc5217SJeff Kirsher * state and, if it's legal, sets a `next_state' in the object 5525adfc5217SJeff Kirsher * that will be used in the completion flow to set the `state' 5526adfc5217SJeff Kirsher * of the object. 5527adfc5217SJeff Kirsher * 5528adfc5217SJeff Kirsher * returns 0 if a requested command is a legal transition, 5529adfc5217SJeff Kirsher * -EINVAL otherwise. 5530adfc5217SJeff Kirsher */ 5531adfc5217SJeff Kirsher static int bnx2x_func_chk_transition(struct bnx2x *bp, 5532adfc5217SJeff Kirsher struct bnx2x_func_sp_obj *o, 5533adfc5217SJeff Kirsher struct bnx2x_func_state_params *params) 5534adfc5217SJeff Kirsher { 5535adfc5217SJeff Kirsher enum bnx2x_func_state state = o->state, next_state = BNX2X_F_STATE_MAX; 5536adfc5217SJeff Kirsher enum bnx2x_func_cmd cmd = params->cmd; 5537adfc5217SJeff Kirsher 553816a5fd92SYuval Mintz /* Forget all pending for completion commands if a driver only state 5539adfc5217SJeff Kirsher * transition has been requested. 5540adfc5217SJeff Kirsher */ 5541adfc5217SJeff Kirsher if (test_bit(RAMROD_DRV_CLR_ONLY, ¶ms->ramrod_flags)) { 5542adfc5217SJeff Kirsher o->pending = 0; 5543adfc5217SJeff Kirsher o->next_state = BNX2X_F_STATE_MAX; 5544adfc5217SJeff Kirsher } 5545adfc5217SJeff Kirsher 554616a5fd92SYuval Mintz /* Don't allow a next state transition if we are in the middle of 5547adfc5217SJeff Kirsher * the previous one. 5548adfc5217SJeff Kirsher */ 5549adfc5217SJeff Kirsher if (o->pending) 5550adfc5217SJeff Kirsher return -EBUSY; 5551adfc5217SJeff Kirsher 5552adfc5217SJeff Kirsher switch (state) { 5553adfc5217SJeff Kirsher case BNX2X_F_STATE_RESET: 5554adfc5217SJeff Kirsher if (cmd == BNX2X_F_CMD_HW_INIT) 5555adfc5217SJeff Kirsher next_state = BNX2X_F_STATE_INITIALIZED; 5556adfc5217SJeff Kirsher 5557adfc5217SJeff Kirsher break; 5558adfc5217SJeff Kirsher case BNX2X_F_STATE_INITIALIZED: 5559adfc5217SJeff Kirsher if (cmd == BNX2X_F_CMD_START) 5560adfc5217SJeff Kirsher next_state = BNX2X_F_STATE_STARTED; 5561adfc5217SJeff Kirsher 5562adfc5217SJeff Kirsher else if (cmd == BNX2X_F_CMD_HW_RESET) 5563adfc5217SJeff Kirsher next_state = BNX2X_F_STATE_RESET; 5564adfc5217SJeff Kirsher 5565adfc5217SJeff Kirsher break; 5566adfc5217SJeff Kirsher case BNX2X_F_STATE_STARTED: 5567adfc5217SJeff Kirsher if (cmd == BNX2X_F_CMD_STOP) 5568adfc5217SJeff Kirsher next_state = BNX2X_F_STATE_INITIALIZED; 5569a3348722SBarak Witkowski /* afex ramrods can be sent only in started mode, and only 5570a3348722SBarak Witkowski * if not pending for function_stop ramrod completion 5571a3348722SBarak Witkowski * for these events - next state remained STARTED. 5572a3348722SBarak Witkowski */ 5573a3348722SBarak Witkowski else if ((cmd == BNX2X_F_CMD_AFEX_UPDATE) && 5574a3348722SBarak Witkowski (!test_bit(BNX2X_F_CMD_STOP, &o->pending))) 5575a3348722SBarak Witkowski next_state = BNX2X_F_STATE_STARTED; 5576a3348722SBarak Witkowski 5577a3348722SBarak Witkowski else if ((cmd == BNX2X_F_CMD_AFEX_VIFLISTS) && 5578a3348722SBarak Witkowski (!test_bit(BNX2X_F_CMD_STOP, &o->pending))) 5579a3348722SBarak Witkowski next_state = BNX2X_F_STATE_STARTED; 558055c11941SMerav Sicron 558155c11941SMerav Sicron /* Switch_update ramrod can be sent in either started or 558255c11941SMerav Sicron * tx_stopped state, and it doesn't change the state. 558355c11941SMerav Sicron */ 558455c11941SMerav Sicron else if ((cmd == BNX2X_F_CMD_SWITCH_UPDATE) && 558555c11941SMerav Sicron (!test_bit(BNX2X_F_CMD_STOP, &o->pending))) 558655c11941SMerav Sicron next_state = BNX2X_F_STATE_STARTED; 558755c11941SMerav Sicron 5588adfc5217SJeff Kirsher else if (cmd == BNX2X_F_CMD_TX_STOP) 5589adfc5217SJeff Kirsher next_state = BNX2X_F_STATE_TX_STOPPED; 5590adfc5217SJeff Kirsher 5591adfc5217SJeff Kirsher break; 5592adfc5217SJeff Kirsher case BNX2X_F_STATE_TX_STOPPED: 559355c11941SMerav Sicron if ((cmd == BNX2X_F_CMD_SWITCH_UPDATE) && 559455c11941SMerav Sicron (!test_bit(BNX2X_F_CMD_STOP, &o->pending))) 559555c11941SMerav Sicron next_state = BNX2X_F_STATE_TX_STOPPED; 559655c11941SMerav Sicron 559755c11941SMerav Sicron else if (cmd == BNX2X_F_CMD_TX_START) 5598adfc5217SJeff Kirsher next_state = BNX2X_F_STATE_STARTED; 5599adfc5217SJeff Kirsher 5600adfc5217SJeff Kirsher break; 5601adfc5217SJeff Kirsher default: 5602adfc5217SJeff Kirsher BNX2X_ERR("Unknown state: %d\n", state); 5603adfc5217SJeff Kirsher } 5604adfc5217SJeff Kirsher 5605adfc5217SJeff Kirsher /* Transition is assured */ 5606adfc5217SJeff Kirsher if (next_state != BNX2X_F_STATE_MAX) { 5607adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "Good function state transition: %d(%d)->%d\n", 5608adfc5217SJeff Kirsher state, cmd, next_state); 5609adfc5217SJeff Kirsher o->next_state = next_state; 5610adfc5217SJeff Kirsher return 0; 5611adfc5217SJeff Kirsher } 5612adfc5217SJeff Kirsher 5613adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "Bad function state transition request: %d %d\n", 5614adfc5217SJeff Kirsher state, cmd); 5615adfc5217SJeff Kirsher 5616adfc5217SJeff Kirsher return -EINVAL; 5617adfc5217SJeff Kirsher } 5618adfc5217SJeff Kirsher 5619adfc5217SJeff Kirsher /** 5620adfc5217SJeff Kirsher * bnx2x_func_init_func - performs HW init at function stage 5621adfc5217SJeff Kirsher * 5622adfc5217SJeff Kirsher * @bp: device handle 5623adfc5217SJeff Kirsher * @drv: 5624adfc5217SJeff Kirsher * 5625adfc5217SJeff Kirsher * Init HW when the current phase is 5626adfc5217SJeff Kirsher * FW_MSG_CODE_DRV_LOAD_FUNCTION: initialize only FUNCTION-only 5627adfc5217SJeff Kirsher * HW blocks. 5628adfc5217SJeff Kirsher */ 5629adfc5217SJeff Kirsher static inline int bnx2x_func_init_func(struct bnx2x *bp, 5630adfc5217SJeff Kirsher const struct bnx2x_func_sp_drv_ops *drv) 5631adfc5217SJeff Kirsher { 5632adfc5217SJeff Kirsher return drv->init_hw_func(bp); 5633adfc5217SJeff Kirsher } 5634adfc5217SJeff Kirsher 5635adfc5217SJeff Kirsher /** 5636adfc5217SJeff Kirsher * bnx2x_func_init_port - performs HW init at port stage 5637adfc5217SJeff Kirsher * 5638adfc5217SJeff Kirsher * @bp: device handle 5639adfc5217SJeff Kirsher * @drv: 5640adfc5217SJeff Kirsher * 5641adfc5217SJeff Kirsher * Init HW when the current phase is 5642adfc5217SJeff Kirsher * FW_MSG_CODE_DRV_LOAD_PORT: initialize PORT-only and 5643adfc5217SJeff Kirsher * FUNCTION-only HW blocks. 5644adfc5217SJeff Kirsher * 5645adfc5217SJeff Kirsher */ 5646adfc5217SJeff Kirsher static inline int bnx2x_func_init_port(struct bnx2x *bp, 5647adfc5217SJeff Kirsher const struct bnx2x_func_sp_drv_ops *drv) 5648adfc5217SJeff Kirsher { 5649adfc5217SJeff Kirsher int rc = drv->init_hw_port(bp); 5650adfc5217SJeff Kirsher if (rc) 5651adfc5217SJeff Kirsher return rc; 5652adfc5217SJeff Kirsher 5653adfc5217SJeff Kirsher return bnx2x_func_init_func(bp, drv); 5654adfc5217SJeff Kirsher } 5655adfc5217SJeff Kirsher 5656adfc5217SJeff Kirsher /** 5657adfc5217SJeff Kirsher * bnx2x_func_init_cmn_chip - performs HW init at chip-common stage 5658adfc5217SJeff Kirsher * 5659adfc5217SJeff Kirsher * @bp: device handle 5660adfc5217SJeff Kirsher * @drv: 5661adfc5217SJeff Kirsher * 5662adfc5217SJeff Kirsher * Init HW when the current phase is 5663adfc5217SJeff Kirsher * FW_MSG_CODE_DRV_LOAD_COMMON_CHIP: initialize COMMON_CHIP, 5664adfc5217SJeff Kirsher * PORT-only and FUNCTION-only HW blocks. 5665adfc5217SJeff Kirsher */ 5666adfc5217SJeff Kirsher static inline int bnx2x_func_init_cmn_chip(struct bnx2x *bp, 5667adfc5217SJeff Kirsher const struct bnx2x_func_sp_drv_ops *drv) 5668adfc5217SJeff Kirsher { 5669adfc5217SJeff Kirsher int rc = drv->init_hw_cmn_chip(bp); 5670adfc5217SJeff Kirsher if (rc) 5671adfc5217SJeff Kirsher return rc; 5672adfc5217SJeff Kirsher 5673adfc5217SJeff Kirsher return bnx2x_func_init_port(bp, drv); 5674adfc5217SJeff Kirsher } 5675adfc5217SJeff Kirsher 5676adfc5217SJeff Kirsher /** 5677adfc5217SJeff Kirsher * bnx2x_func_init_cmn - performs HW init at common stage 5678adfc5217SJeff Kirsher * 5679adfc5217SJeff Kirsher * @bp: device handle 5680adfc5217SJeff Kirsher * @drv: 5681adfc5217SJeff Kirsher * 5682adfc5217SJeff Kirsher * Init HW when the current phase is 5683adfc5217SJeff Kirsher * FW_MSG_CODE_DRV_LOAD_COMMON_CHIP: initialize COMMON, 5684adfc5217SJeff Kirsher * PORT-only and FUNCTION-only HW blocks. 5685adfc5217SJeff Kirsher */ 5686adfc5217SJeff Kirsher static inline int bnx2x_func_init_cmn(struct bnx2x *bp, 5687adfc5217SJeff Kirsher const struct bnx2x_func_sp_drv_ops *drv) 5688adfc5217SJeff Kirsher { 5689adfc5217SJeff Kirsher int rc = drv->init_hw_cmn(bp); 5690adfc5217SJeff Kirsher if (rc) 5691adfc5217SJeff Kirsher return rc; 5692adfc5217SJeff Kirsher 5693adfc5217SJeff Kirsher return bnx2x_func_init_port(bp, drv); 5694adfc5217SJeff Kirsher } 5695adfc5217SJeff Kirsher 5696adfc5217SJeff Kirsher static int bnx2x_func_hw_init(struct bnx2x *bp, 5697adfc5217SJeff Kirsher struct bnx2x_func_state_params *params) 5698adfc5217SJeff Kirsher { 5699adfc5217SJeff Kirsher u32 load_code = params->params.hw_init.load_phase; 5700adfc5217SJeff Kirsher struct bnx2x_func_sp_obj *o = params->f_obj; 5701adfc5217SJeff Kirsher const struct bnx2x_func_sp_drv_ops *drv = o->drv; 5702adfc5217SJeff Kirsher int rc = 0; 5703adfc5217SJeff Kirsher 5704adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "function %d load_code %x\n", 5705adfc5217SJeff Kirsher BP_ABS_FUNC(bp), load_code); 5706adfc5217SJeff Kirsher 5707adfc5217SJeff Kirsher /* Prepare buffers for unzipping the FW */ 5708adfc5217SJeff Kirsher rc = drv->gunzip_init(bp); 5709adfc5217SJeff Kirsher if (rc) 5710adfc5217SJeff Kirsher return rc; 5711adfc5217SJeff Kirsher 5712adfc5217SJeff Kirsher /* Prepare FW */ 5713adfc5217SJeff Kirsher rc = drv->init_fw(bp); 5714adfc5217SJeff Kirsher if (rc) { 5715adfc5217SJeff Kirsher BNX2X_ERR("Error loading firmware\n"); 5716eb2afd4aSDmitry Kravkov goto init_err; 5717adfc5217SJeff Kirsher } 5718adfc5217SJeff Kirsher 571916a5fd92SYuval Mintz /* Handle the beginning of COMMON_XXX pases separately... */ 5720adfc5217SJeff Kirsher switch (load_code) { 5721adfc5217SJeff Kirsher case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP: 5722adfc5217SJeff Kirsher rc = bnx2x_func_init_cmn_chip(bp, drv); 5723adfc5217SJeff Kirsher if (rc) 5724eb2afd4aSDmitry Kravkov goto init_err; 5725adfc5217SJeff Kirsher 5726adfc5217SJeff Kirsher break; 5727adfc5217SJeff Kirsher case FW_MSG_CODE_DRV_LOAD_COMMON: 5728adfc5217SJeff Kirsher rc = bnx2x_func_init_cmn(bp, drv); 5729adfc5217SJeff Kirsher if (rc) 5730eb2afd4aSDmitry Kravkov goto init_err; 5731adfc5217SJeff Kirsher 5732adfc5217SJeff Kirsher break; 5733adfc5217SJeff Kirsher case FW_MSG_CODE_DRV_LOAD_PORT: 5734adfc5217SJeff Kirsher rc = bnx2x_func_init_port(bp, drv); 5735adfc5217SJeff Kirsher if (rc) 5736eb2afd4aSDmitry Kravkov goto init_err; 5737adfc5217SJeff Kirsher 5738adfc5217SJeff Kirsher break; 5739adfc5217SJeff Kirsher case FW_MSG_CODE_DRV_LOAD_FUNCTION: 5740adfc5217SJeff Kirsher rc = bnx2x_func_init_func(bp, drv); 5741adfc5217SJeff Kirsher if (rc) 5742eb2afd4aSDmitry Kravkov goto init_err; 5743adfc5217SJeff Kirsher 5744adfc5217SJeff Kirsher break; 5745adfc5217SJeff Kirsher default: 5746adfc5217SJeff Kirsher BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code); 5747adfc5217SJeff Kirsher rc = -EINVAL; 5748adfc5217SJeff Kirsher } 5749adfc5217SJeff Kirsher 5750eb2afd4aSDmitry Kravkov init_err: 5751adfc5217SJeff Kirsher drv->gunzip_end(bp); 5752adfc5217SJeff Kirsher 575316a5fd92SYuval Mintz /* In case of success, complete the command immediately: no ramrods 5754adfc5217SJeff Kirsher * have been sent. 5755adfc5217SJeff Kirsher */ 5756adfc5217SJeff Kirsher if (!rc) 5757adfc5217SJeff Kirsher o->complete_cmd(bp, o, BNX2X_F_CMD_HW_INIT); 5758adfc5217SJeff Kirsher 5759adfc5217SJeff Kirsher return rc; 5760adfc5217SJeff Kirsher } 5761adfc5217SJeff Kirsher 5762adfc5217SJeff Kirsher /** 5763adfc5217SJeff Kirsher * bnx2x_func_reset_func - reset HW at function stage 5764adfc5217SJeff Kirsher * 5765adfc5217SJeff Kirsher * @bp: device handle 5766adfc5217SJeff Kirsher * @drv: 5767adfc5217SJeff Kirsher * 5768adfc5217SJeff Kirsher * Reset HW at FW_MSG_CODE_DRV_UNLOAD_FUNCTION stage: reset only 5769adfc5217SJeff Kirsher * FUNCTION-only HW blocks. 5770adfc5217SJeff Kirsher */ 5771adfc5217SJeff Kirsher static inline void bnx2x_func_reset_func(struct bnx2x *bp, 5772adfc5217SJeff Kirsher const struct bnx2x_func_sp_drv_ops *drv) 5773adfc5217SJeff Kirsher { 5774adfc5217SJeff Kirsher drv->reset_hw_func(bp); 5775adfc5217SJeff Kirsher } 5776adfc5217SJeff Kirsher 5777adfc5217SJeff Kirsher /** 577816a5fd92SYuval Mintz * bnx2x_func_reset_port - reset HW at port stage 5779adfc5217SJeff Kirsher * 5780adfc5217SJeff Kirsher * @bp: device handle 5781adfc5217SJeff Kirsher * @drv: 5782adfc5217SJeff Kirsher * 5783adfc5217SJeff Kirsher * Reset HW at FW_MSG_CODE_DRV_UNLOAD_PORT stage: reset 5784adfc5217SJeff Kirsher * FUNCTION-only and PORT-only HW blocks. 5785adfc5217SJeff Kirsher * 5786adfc5217SJeff Kirsher * !!!IMPORTANT!!! 5787adfc5217SJeff Kirsher * 5788adfc5217SJeff Kirsher * It's important to call reset_port before reset_func() as the last thing 5789adfc5217SJeff Kirsher * reset_func does is pf_disable() thus disabling PGLUE_B, which 5790adfc5217SJeff Kirsher * makes impossible any DMAE transactions. 5791adfc5217SJeff Kirsher */ 5792adfc5217SJeff Kirsher static inline void bnx2x_func_reset_port(struct bnx2x *bp, 5793adfc5217SJeff Kirsher const struct bnx2x_func_sp_drv_ops *drv) 5794adfc5217SJeff Kirsher { 5795adfc5217SJeff Kirsher drv->reset_hw_port(bp); 5796adfc5217SJeff Kirsher bnx2x_func_reset_func(bp, drv); 5797adfc5217SJeff Kirsher } 5798adfc5217SJeff Kirsher 5799adfc5217SJeff Kirsher /** 580016a5fd92SYuval Mintz * bnx2x_func_reset_cmn - reset HW at common stage 5801adfc5217SJeff Kirsher * 5802adfc5217SJeff Kirsher * @bp: device handle 5803adfc5217SJeff Kirsher * @drv: 5804adfc5217SJeff Kirsher * 5805adfc5217SJeff Kirsher * Reset HW at FW_MSG_CODE_DRV_UNLOAD_COMMON and 5806adfc5217SJeff Kirsher * FW_MSG_CODE_DRV_UNLOAD_COMMON_CHIP stages: reset COMMON, 5807adfc5217SJeff Kirsher * COMMON_CHIP, FUNCTION-only and PORT-only HW blocks. 5808adfc5217SJeff Kirsher */ 5809adfc5217SJeff Kirsher static inline void bnx2x_func_reset_cmn(struct bnx2x *bp, 5810adfc5217SJeff Kirsher const struct bnx2x_func_sp_drv_ops *drv) 5811adfc5217SJeff Kirsher { 5812adfc5217SJeff Kirsher bnx2x_func_reset_port(bp, drv); 5813adfc5217SJeff Kirsher drv->reset_hw_cmn(bp); 5814adfc5217SJeff Kirsher } 5815adfc5217SJeff Kirsher 5816adfc5217SJeff Kirsher static inline int bnx2x_func_hw_reset(struct bnx2x *bp, 5817adfc5217SJeff Kirsher struct bnx2x_func_state_params *params) 5818adfc5217SJeff Kirsher { 5819adfc5217SJeff Kirsher u32 reset_phase = params->params.hw_reset.reset_phase; 5820adfc5217SJeff Kirsher struct bnx2x_func_sp_obj *o = params->f_obj; 5821adfc5217SJeff Kirsher const struct bnx2x_func_sp_drv_ops *drv = o->drv; 5822adfc5217SJeff Kirsher 5823adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "function %d reset_phase %x\n", BP_ABS_FUNC(bp), 5824adfc5217SJeff Kirsher reset_phase); 5825adfc5217SJeff Kirsher 5826adfc5217SJeff Kirsher switch (reset_phase) { 5827adfc5217SJeff Kirsher case FW_MSG_CODE_DRV_UNLOAD_COMMON: 5828adfc5217SJeff Kirsher bnx2x_func_reset_cmn(bp, drv); 5829adfc5217SJeff Kirsher break; 5830adfc5217SJeff Kirsher case FW_MSG_CODE_DRV_UNLOAD_PORT: 5831adfc5217SJeff Kirsher bnx2x_func_reset_port(bp, drv); 5832adfc5217SJeff Kirsher break; 5833adfc5217SJeff Kirsher case FW_MSG_CODE_DRV_UNLOAD_FUNCTION: 5834adfc5217SJeff Kirsher bnx2x_func_reset_func(bp, drv); 5835adfc5217SJeff Kirsher break; 5836adfc5217SJeff Kirsher default: 5837adfc5217SJeff Kirsher BNX2X_ERR("Unknown reset_phase (0x%x) from MCP\n", 5838adfc5217SJeff Kirsher reset_phase); 5839adfc5217SJeff Kirsher break; 5840adfc5217SJeff Kirsher } 5841adfc5217SJeff Kirsher 584216a5fd92SYuval Mintz /* Complete the command immediately: no ramrods have been sent. */ 5843adfc5217SJeff Kirsher o->complete_cmd(bp, o, BNX2X_F_CMD_HW_RESET); 5844adfc5217SJeff Kirsher 5845adfc5217SJeff Kirsher return 0; 5846adfc5217SJeff Kirsher } 5847adfc5217SJeff Kirsher 5848adfc5217SJeff Kirsher static inline int bnx2x_func_send_start(struct bnx2x *bp, 5849adfc5217SJeff Kirsher struct bnx2x_func_state_params *params) 5850adfc5217SJeff Kirsher { 5851adfc5217SJeff Kirsher struct bnx2x_func_sp_obj *o = params->f_obj; 5852adfc5217SJeff Kirsher struct function_start_data *rdata = 5853adfc5217SJeff Kirsher (struct function_start_data *)o->rdata; 5854adfc5217SJeff Kirsher dma_addr_t data_mapping = o->rdata_mapping; 5855adfc5217SJeff Kirsher struct bnx2x_func_start_params *start_params = ¶ms->params.start; 5856adfc5217SJeff Kirsher 5857adfc5217SJeff Kirsher memset(rdata, 0, sizeof(*rdata)); 5858adfc5217SJeff Kirsher 5859adfc5217SJeff Kirsher /* Fill the ramrod data with provided parameters */ 586096bed4b9SYuval Mintz rdata->function_mode = (u8)start_params->mf_mode; 5861ab4a7139SAriel Elior rdata->sd_vlan_tag = cpu_to_le16(start_params->sd_vlan_tag); 5862adfc5217SJeff Kirsher rdata->path_id = BP_PATH(bp); 5863adfc5217SJeff Kirsher rdata->network_cos_mode = start_params->network_cos_mode; 58641bc277f7SDmitry Kravkov rdata->gre_tunnel_mode = start_params->gre_tunnel_mode; 58651bc277f7SDmitry Kravkov rdata->gre_tunnel_rss = start_params->gre_tunnel_rss; 5866adfc5217SJeff Kirsher 58671bc277f7SDmitry Kravkov /* No need for an explicit memory barrier here as long we would 5868adfc5217SJeff Kirsher * need to ensure the ordering of writing to the SPQ element 5869adfc5217SJeff Kirsher * and updating of the SPQ producer which involves a memory 5870adfc5217SJeff Kirsher * read and we will have to put a full memory barrier there 5871adfc5217SJeff Kirsher * (inside bnx2x_sp_post()). 5872adfc5217SJeff Kirsher */ 5873adfc5217SJeff Kirsher 5874adfc5217SJeff Kirsher return bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_FUNCTION_START, 0, 5875adfc5217SJeff Kirsher U64_HI(data_mapping), 5876adfc5217SJeff Kirsher U64_LO(data_mapping), NONE_CONNECTION_TYPE); 5877adfc5217SJeff Kirsher } 5878adfc5217SJeff Kirsher 587955c11941SMerav Sicron static inline int bnx2x_func_send_switch_update(struct bnx2x *bp, 588055c11941SMerav Sicron struct bnx2x_func_state_params *params) 588155c11941SMerav Sicron { 588255c11941SMerav Sicron struct bnx2x_func_sp_obj *o = params->f_obj; 588355c11941SMerav Sicron struct function_update_data *rdata = 588455c11941SMerav Sicron (struct function_update_data *)o->rdata; 588555c11941SMerav Sicron dma_addr_t data_mapping = o->rdata_mapping; 588655c11941SMerav Sicron struct bnx2x_func_switch_update_params *switch_update_params = 588755c11941SMerav Sicron ¶ms->params.switch_update; 588855c11941SMerav Sicron 588955c11941SMerav Sicron memset(rdata, 0, sizeof(*rdata)); 589055c11941SMerav Sicron 589155c11941SMerav Sicron /* Fill the ramrod data with provided parameters */ 589255c11941SMerav Sicron rdata->tx_switch_suspend_change_flg = 1; 589355c11941SMerav Sicron rdata->tx_switch_suspend = switch_update_params->suspend; 589455c11941SMerav Sicron rdata->echo = SWITCH_UPDATE; 589555c11941SMerav Sicron 589655c11941SMerav Sicron return bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_FUNCTION_UPDATE, 0, 589755c11941SMerav Sicron U64_HI(data_mapping), 589855c11941SMerav Sicron U64_LO(data_mapping), NONE_CONNECTION_TYPE); 589955c11941SMerav Sicron } 590055c11941SMerav Sicron 5901a3348722SBarak Witkowski static inline int bnx2x_func_send_afex_update(struct bnx2x *bp, 5902a3348722SBarak Witkowski struct bnx2x_func_state_params *params) 5903a3348722SBarak Witkowski { 5904a3348722SBarak Witkowski struct bnx2x_func_sp_obj *o = params->f_obj; 5905a3348722SBarak Witkowski struct function_update_data *rdata = 5906a3348722SBarak Witkowski (struct function_update_data *)o->afex_rdata; 5907a3348722SBarak Witkowski dma_addr_t data_mapping = o->afex_rdata_mapping; 5908a3348722SBarak Witkowski struct bnx2x_func_afex_update_params *afex_update_params = 5909a3348722SBarak Witkowski ¶ms->params.afex_update; 5910a3348722SBarak Witkowski 5911a3348722SBarak Witkowski memset(rdata, 0, sizeof(*rdata)); 5912a3348722SBarak Witkowski 5913a3348722SBarak Witkowski /* Fill the ramrod data with provided parameters */ 5914a3348722SBarak Witkowski rdata->vif_id_change_flg = 1; 5915a3348722SBarak Witkowski rdata->vif_id = cpu_to_le16(afex_update_params->vif_id); 5916a3348722SBarak Witkowski rdata->afex_default_vlan_change_flg = 1; 5917a3348722SBarak Witkowski rdata->afex_default_vlan = 5918a3348722SBarak Witkowski cpu_to_le16(afex_update_params->afex_default_vlan); 5919a3348722SBarak Witkowski rdata->allowed_priorities_change_flg = 1; 5920a3348722SBarak Witkowski rdata->allowed_priorities = afex_update_params->allowed_priorities; 592155c11941SMerav Sicron rdata->echo = AFEX_UPDATE; 5922a3348722SBarak Witkowski 5923a3348722SBarak Witkowski /* No need for an explicit memory barrier here as long we would 5924a3348722SBarak Witkowski * need to ensure the ordering of writing to the SPQ element 5925a3348722SBarak Witkowski * and updating of the SPQ producer which involves a memory 5926a3348722SBarak Witkowski * read and we will have to put a full memory barrier there 5927a3348722SBarak Witkowski * (inside bnx2x_sp_post()). 5928a3348722SBarak Witkowski */ 5929a3348722SBarak Witkowski DP(BNX2X_MSG_SP, 5930a3348722SBarak Witkowski "afex: sending func_update vif_id 0x%x dvlan 0x%x prio 0x%x\n", 5931a3348722SBarak Witkowski rdata->vif_id, 5932a3348722SBarak Witkowski rdata->afex_default_vlan, rdata->allowed_priorities); 5933a3348722SBarak Witkowski 5934a3348722SBarak Witkowski return bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_FUNCTION_UPDATE, 0, 5935a3348722SBarak Witkowski U64_HI(data_mapping), 5936a3348722SBarak Witkowski U64_LO(data_mapping), NONE_CONNECTION_TYPE); 5937a3348722SBarak Witkowski } 5938a3348722SBarak Witkowski 5939a3348722SBarak Witkowski static 5940a3348722SBarak Witkowski inline int bnx2x_func_send_afex_viflists(struct bnx2x *bp, 5941a3348722SBarak Witkowski struct bnx2x_func_state_params *params) 5942a3348722SBarak Witkowski { 5943a3348722SBarak Witkowski struct bnx2x_func_sp_obj *o = params->f_obj; 5944a3348722SBarak Witkowski struct afex_vif_list_ramrod_data *rdata = 5945a3348722SBarak Witkowski (struct afex_vif_list_ramrod_data *)o->afex_rdata; 594686564c3fSYuval Mintz struct bnx2x_func_afex_viflists_params *afex_vif_params = 5947a3348722SBarak Witkowski ¶ms->params.afex_viflists; 5948a3348722SBarak Witkowski u64 *p_rdata = (u64 *)rdata; 5949a3348722SBarak Witkowski 5950a3348722SBarak Witkowski memset(rdata, 0, sizeof(*rdata)); 5951a3348722SBarak Witkowski 5952a3348722SBarak Witkowski /* Fill the ramrod data with provided parameters */ 595386564c3fSYuval Mintz rdata->vif_list_index = cpu_to_le16(afex_vif_params->vif_list_index); 595486564c3fSYuval Mintz rdata->func_bit_map = afex_vif_params->func_bit_map; 595586564c3fSYuval Mintz rdata->afex_vif_list_command = afex_vif_params->afex_vif_list_command; 595686564c3fSYuval Mintz rdata->func_to_clear = afex_vif_params->func_to_clear; 5957a3348722SBarak Witkowski 5958a3348722SBarak Witkowski /* send in echo type of sub command */ 595986564c3fSYuval Mintz rdata->echo = afex_vif_params->afex_vif_list_command; 5960a3348722SBarak Witkowski 5961a3348722SBarak Witkowski /* No need for an explicit memory barrier here as long we would 5962a3348722SBarak Witkowski * need to ensure the ordering of writing to the SPQ element 5963a3348722SBarak Witkowski * and updating of the SPQ producer which involves a memory 5964a3348722SBarak Witkowski * read and we will have to put a full memory barrier there 5965a3348722SBarak Witkowski * (inside bnx2x_sp_post()). 5966a3348722SBarak Witkowski */ 5967a3348722SBarak Witkowski 5968a3348722SBarak Witkowski DP(BNX2X_MSG_SP, "afex: ramrod lists, cmd 0x%x index 0x%x func_bit_map 0x%x func_to_clr 0x%x\n", 5969a3348722SBarak Witkowski rdata->afex_vif_list_command, rdata->vif_list_index, 5970a3348722SBarak Witkowski rdata->func_bit_map, rdata->func_to_clear); 5971a3348722SBarak Witkowski 5972a3348722SBarak Witkowski /* this ramrod sends data directly and not through DMA mapping */ 5973a3348722SBarak Witkowski return bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_AFEX_VIF_LISTS, 0, 5974a3348722SBarak Witkowski U64_HI(*p_rdata), U64_LO(*p_rdata), 5975a3348722SBarak Witkowski NONE_CONNECTION_TYPE); 5976a3348722SBarak Witkowski } 5977a3348722SBarak Witkowski 5978adfc5217SJeff Kirsher static inline int bnx2x_func_send_stop(struct bnx2x *bp, 5979adfc5217SJeff Kirsher struct bnx2x_func_state_params *params) 5980adfc5217SJeff Kirsher { 5981adfc5217SJeff Kirsher return bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_FUNCTION_STOP, 0, 0, 0, 5982adfc5217SJeff Kirsher NONE_CONNECTION_TYPE); 5983adfc5217SJeff Kirsher } 5984adfc5217SJeff Kirsher 5985adfc5217SJeff Kirsher static inline int bnx2x_func_send_tx_stop(struct bnx2x *bp, 5986adfc5217SJeff Kirsher struct bnx2x_func_state_params *params) 5987adfc5217SJeff Kirsher { 5988adfc5217SJeff Kirsher return bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_STOP_TRAFFIC, 0, 0, 0, 5989adfc5217SJeff Kirsher NONE_CONNECTION_TYPE); 5990adfc5217SJeff Kirsher } 5991adfc5217SJeff Kirsher static inline int bnx2x_func_send_tx_start(struct bnx2x *bp, 5992adfc5217SJeff Kirsher struct bnx2x_func_state_params *params) 5993adfc5217SJeff Kirsher { 5994adfc5217SJeff Kirsher struct bnx2x_func_sp_obj *o = params->f_obj; 5995adfc5217SJeff Kirsher struct flow_control_configuration *rdata = 5996adfc5217SJeff Kirsher (struct flow_control_configuration *)o->rdata; 5997adfc5217SJeff Kirsher dma_addr_t data_mapping = o->rdata_mapping; 5998adfc5217SJeff Kirsher struct bnx2x_func_tx_start_params *tx_start_params = 5999adfc5217SJeff Kirsher ¶ms->params.tx_start; 6000adfc5217SJeff Kirsher int i; 6001adfc5217SJeff Kirsher 6002adfc5217SJeff Kirsher memset(rdata, 0, sizeof(*rdata)); 6003adfc5217SJeff Kirsher 6004adfc5217SJeff Kirsher rdata->dcb_enabled = tx_start_params->dcb_enabled; 6005adfc5217SJeff Kirsher rdata->dcb_version = tx_start_params->dcb_version; 6006adfc5217SJeff Kirsher rdata->dont_add_pri_0_en = tx_start_params->dont_add_pri_0_en; 6007adfc5217SJeff Kirsher 6008adfc5217SJeff Kirsher for (i = 0; i < ARRAY_SIZE(rdata->traffic_type_to_priority_cos); i++) 6009adfc5217SJeff Kirsher rdata->traffic_type_to_priority_cos[i] = 6010adfc5217SJeff Kirsher tx_start_params->traffic_type_to_priority_cos[i]; 6011adfc5217SJeff Kirsher 6012adfc5217SJeff Kirsher return bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_START_TRAFFIC, 0, 6013adfc5217SJeff Kirsher U64_HI(data_mapping), 6014adfc5217SJeff Kirsher U64_LO(data_mapping), NONE_CONNECTION_TYPE); 6015adfc5217SJeff Kirsher } 6016adfc5217SJeff Kirsher 6017adfc5217SJeff Kirsher static int bnx2x_func_send_cmd(struct bnx2x *bp, 6018adfc5217SJeff Kirsher struct bnx2x_func_state_params *params) 6019adfc5217SJeff Kirsher { 6020adfc5217SJeff Kirsher switch (params->cmd) { 6021adfc5217SJeff Kirsher case BNX2X_F_CMD_HW_INIT: 6022adfc5217SJeff Kirsher return bnx2x_func_hw_init(bp, params); 6023adfc5217SJeff Kirsher case BNX2X_F_CMD_START: 6024adfc5217SJeff Kirsher return bnx2x_func_send_start(bp, params); 6025adfc5217SJeff Kirsher case BNX2X_F_CMD_STOP: 6026adfc5217SJeff Kirsher return bnx2x_func_send_stop(bp, params); 6027adfc5217SJeff Kirsher case BNX2X_F_CMD_HW_RESET: 6028adfc5217SJeff Kirsher return bnx2x_func_hw_reset(bp, params); 6029a3348722SBarak Witkowski case BNX2X_F_CMD_AFEX_UPDATE: 6030a3348722SBarak Witkowski return bnx2x_func_send_afex_update(bp, params); 6031a3348722SBarak Witkowski case BNX2X_F_CMD_AFEX_VIFLISTS: 6032a3348722SBarak Witkowski return bnx2x_func_send_afex_viflists(bp, params); 6033adfc5217SJeff Kirsher case BNX2X_F_CMD_TX_STOP: 6034adfc5217SJeff Kirsher return bnx2x_func_send_tx_stop(bp, params); 6035adfc5217SJeff Kirsher case BNX2X_F_CMD_TX_START: 6036adfc5217SJeff Kirsher return bnx2x_func_send_tx_start(bp, params); 603755c11941SMerav Sicron case BNX2X_F_CMD_SWITCH_UPDATE: 603855c11941SMerav Sicron return bnx2x_func_send_switch_update(bp, params); 6039adfc5217SJeff Kirsher default: 6040adfc5217SJeff Kirsher BNX2X_ERR("Unknown command: %d\n", params->cmd); 6041adfc5217SJeff Kirsher return -EINVAL; 6042adfc5217SJeff Kirsher } 6043adfc5217SJeff Kirsher } 6044adfc5217SJeff Kirsher 6045adfc5217SJeff Kirsher void bnx2x_init_func_obj(struct bnx2x *bp, 6046adfc5217SJeff Kirsher struct bnx2x_func_sp_obj *obj, 6047adfc5217SJeff Kirsher void *rdata, dma_addr_t rdata_mapping, 6048a3348722SBarak Witkowski void *afex_rdata, dma_addr_t afex_rdata_mapping, 6049adfc5217SJeff Kirsher struct bnx2x_func_sp_drv_ops *drv_iface) 6050adfc5217SJeff Kirsher { 6051adfc5217SJeff Kirsher memset(obj, 0, sizeof(*obj)); 6052adfc5217SJeff Kirsher 6053adfc5217SJeff Kirsher mutex_init(&obj->one_pending_mutex); 6054adfc5217SJeff Kirsher 6055adfc5217SJeff Kirsher obj->rdata = rdata; 6056adfc5217SJeff Kirsher obj->rdata_mapping = rdata_mapping; 6057a3348722SBarak Witkowski obj->afex_rdata = afex_rdata; 6058a3348722SBarak Witkowski obj->afex_rdata_mapping = afex_rdata_mapping; 6059adfc5217SJeff Kirsher obj->send_cmd = bnx2x_func_send_cmd; 6060adfc5217SJeff Kirsher obj->check_transition = bnx2x_func_chk_transition; 6061adfc5217SJeff Kirsher obj->complete_cmd = bnx2x_func_comp_cmd; 6062adfc5217SJeff Kirsher obj->wait_comp = bnx2x_func_wait_comp; 6063adfc5217SJeff Kirsher 6064adfc5217SJeff Kirsher obj->drv = drv_iface; 6065adfc5217SJeff Kirsher } 6066adfc5217SJeff Kirsher 6067adfc5217SJeff Kirsher /** 6068adfc5217SJeff Kirsher * bnx2x_func_state_change - perform Function state change transition 6069adfc5217SJeff Kirsher * 6070adfc5217SJeff Kirsher * @bp: device handle 6071adfc5217SJeff Kirsher * @params: parameters to perform the transaction 6072adfc5217SJeff Kirsher * 6073adfc5217SJeff Kirsher * returns 0 in case of successfully completed transition, 6074adfc5217SJeff Kirsher * negative error code in case of failure, positive 6075adfc5217SJeff Kirsher * (EBUSY) value if there is a completion to that is 6076adfc5217SJeff Kirsher * still pending (possible only if RAMROD_COMP_WAIT is 6077adfc5217SJeff Kirsher * not set in params->ramrod_flags for asynchronous 6078adfc5217SJeff Kirsher * commands). 6079adfc5217SJeff Kirsher */ 6080adfc5217SJeff Kirsher int bnx2x_func_state_change(struct bnx2x *bp, 6081adfc5217SJeff Kirsher struct bnx2x_func_state_params *params) 6082adfc5217SJeff Kirsher { 6083adfc5217SJeff Kirsher struct bnx2x_func_sp_obj *o = params->f_obj; 608455c11941SMerav Sicron int rc, cnt = 300; 6085adfc5217SJeff Kirsher enum bnx2x_func_cmd cmd = params->cmd; 6086adfc5217SJeff Kirsher unsigned long *pending = &o->pending; 6087adfc5217SJeff Kirsher 6088adfc5217SJeff Kirsher mutex_lock(&o->one_pending_mutex); 6089adfc5217SJeff Kirsher 6090adfc5217SJeff Kirsher /* Check that the requested transition is legal */ 609155c11941SMerav Sicron rc = o->check_transition(bp, o, params); 609255c11941SMerav Sicron if ((rc == -EBUSY) && 609355c11941SMerav Sicron (test_bit(RAMROD_RETRY, ¶ms->ramrod_flags))) { 609455c11941SMerav Sicron while ((rc == -EBUSY) && (--cnt > 0)) { 6095adfc5217SJeff Kirsher mutex_unlock(&o->one_pending_mutex); 609655c11941SMerav Sicron msleep(10); 609755c11941SMerav Sicron mutex_lock(&o->one_pending_mutex); 609855c11941SMerav Sicron rc = o->check_transition(bp, o, params); 609955c11941SMerav Sicron } 610055c11941SMerav Sicron if (rc == -EBUSY) { 610155c11941SMerav Sicron mutex_unlock(&o->one_pending_mutex); 610255c11941SMerav Sicron BNX2X_ERR("timeout waiting for previous ramrod completion\n"); 610355c11941SMerav Sicron return rc; 610455c11941SMerav Sicron } 610555c11941SMerav Sicron } else if (rc) { 610655c11941SMerav Sicron mutex_unlock(&o->one_pending_mutex); 610755c11941SMerav Sicron return rc; 6108adfc5217SJeff Kirsher } 6109adfc5217SJeff Kirsher 6110adfc5217SJeff Kirsher /* Set "pending" bit */ 6111adfc5217SJeff Kirsher set_bit(cmd, pending); 6112adfc5217SJeff Kirsher 6113adfc5217SJeff Kirsher /* Don't send a command if only driver cleanup was requested */ 6114adfc5217SJeff Kirsher if (test_bit(RAMROD_DRV_CLR_ONLY, ¶ms->ramrod_flags)) { 6115adfc5217SJeff Kirsher bnx2x_func_state_change_comp(bp, o, cmd); 6116adfc5217SJeff Kirsher mutex_unlock(&o->one_pending_mutex); 6117adfc5217SJeff Kirsher } else { 6118adfc5217SJeff Kirsher /* Send a ramrod */ 6119adfc5217SJeff Kirsher rc = o->send_cmd(bp, params); 6120adfc5217SJeff Kirsher 6121adfc5217SJeff Kirsher mutex_unlock(&o->one_pending_mutex); 6122adfc5217SJeff Kirsher 6123adfc5217SJeff Kirsher if (rc) { 6124adfc5217SJeff Kirsher o->next_state = BNX2X_F_STATE_MAX; 6125adfc5217SJeff Kirsher clear_bit(cmd, pending); 6126adfc5217SJeff Kirsher smp_mb__after_clear_bit(); 6127adfc5217SJeff Kirsher return rc; 6128adfc5217SJeff Kirsher } 6129adfc5217SJeff Kirsher 6130adfc5217SJeff Kirsher if (test_bit(RAMROD_COMP_WAIT, ¶ms->ramrod_flags)) { 6131adfc5217SJeff Kirsher rc = o->wait_comp(bp, o, cmd); 6132adfc5217SJeff Kirsher if (rc) 6133adfc5217SJeff Kirsher return rc; 6134adfc5217SJeff Kirsher 6135adfc5217SJeff Kirsher return 0; 6136adfc5217SJeff Kirsher } 6137adfc5217SJeff Kirsher } 6138adfc5217SJeff Kirsher 6139adfc5217SJeff Kirsher return !!test_bit(cmd, pending); 6140adfc5217SJeff Kirsher } 6141