1adfc5217SJeff Kirsher /* bnx2x_sp.c: Broadcom Everest network driver. 2adfc5217SJeff Kirsher * 3247fa82bSYuval Mintz * Copyright (c) 2011-2013 Broadcom Corporation 4adfc5217SJeff Kirsher * 5adfc5217SJeff Kirsher * Unless you and Broadcom execute a separate written software license 6adfc5217SJeff Kirsher * agreement governing use of this software, this software is licensed to you 7adfc5217SJeff Kirsher * under the terms of the GNU General Public License version 2, available 8adfc5217SJeff Kirsher * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL"). 9adfc5217SJeff Kirsher * 10adfc5217SJeff Kirsher * Notwithstanding the above, under no circumstances may you combine this 11adfc5217SJeff Kirsher * software in any way with any other Broadcom software provided under a 12adfc5217SJeff Kirsher * license other than the GPL, without Broadcom's express prior written 13adfc5217SJeff Kirsher * consent. 14adfc5217SJeff Kirsher * 1508f6dd89SAriel Elior * Maintained by: Ariel Elior <ariel.elior@qlogic.com> 16adfc5217SJeff Kirsher * Written by: Vladislav Zolotarov 17adfc5217SJeff Kirsher * 18adfc5217SJeff Kirsher */ 19f1deab50SJoe Perches 20f1deab50SJoe Perches #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 21f1deab50SJoe Perches 22adfc5217SJeff Kirsher #include <linux/module.h> 23adfc5217SJeff Kirsher #include <linux/crc32.h> 24adfc5217SJeff Kirsher #include <linux/netdevice.h> 25adfc5217SJeff Kirsher #include <linux/etherdevice.h> 26adfc5217SJeff Kirsher #include <linux/crc32c.h> 27adfc5217SJeff Kirsher #include "bnx2x.h" 28adfc5217SJeff Kirsher #include "bnx2x_cmn.h" 29adfc5217SJeff Kirsher #include "bnx2x_sp.h" 30adfc5217SJeff Kirsher 31adfc5217SJeff Kirsher #define BNX2X_MAX_EMUL_MULTI 16 32adfc5217SJeff Kirsher 33adfc5217SJeff Kirsher /**** Exe Queue interfaces ****/ 34adfc5217SJeff Kirsher 35adfc5217SJeff Kirsher /** 36adfc5217SJeff Kirsher * bnx2x_exe_queue_init - init the Exe Queue object 37adfc5217SJeff Kirsher * 3816a5fd92SYuval Mintz * @o: pointer to the object 39adfc5217SJeff Kirsher * @exe_len: length 4016a5fd92SYuval Mintz * @owner: pointer to the owner 41adfc5217SJeff Kirsher * @validate: validate function pointer 42adfc5217SJeff Kirsher * @optimize: optimize function pointer 43adfc5217SJeff Kirsher * @exec: execute function pointer 44adfc5217SJeff Kirsher * @get: get function pointer 45adfc5217SJeff Kirsher */ 46adfc5217SJeff Kirsher static inline void bnx2x_exe_queue_init(struct bnx2x *bp, 47adfc5217SJeff Kirsher struct bnx2x_exe_queue_obj *o, 48adfc5217SJeff Kirsher int exe_len, 49adfc5217SJeff Kirsher union bnx2x_qable_obj *owner, 50adfc5217SJeff Kirsher exe_q_validate validate, 51460a25cdSYuval Mintz exe_q_remove remove, 52adfc5217SJeff Kirsher exe_q_optimize optimize, 53adfc5217SJeff Kirsher exe_q_execute exec, 54adfc5217SJeff Kirsher exe_q_get get) 55adfc5217SJeff Kirsher { 56adfc5217SJeff Kirsher memset(o, 0, sizeof(*o)); 57adfc5217SJeff Kirsher 58adfc5217SJeff Kirsher INIT_LIST_HEAD(&o->exe_queue); 59adfc5217SJeff Kirsher INIT_LIST_HEAD(&o->pending_comp); 60adfc5217SJeff Kirsher 61adfc5217SJeff Kirsher spin_lock_init(&o->lock); 62adfc5217SJeff Kirsher 63adfc5217SJeff Kirsher o->exe_chunk_len = exe_len; 64adfc5217SJeff Kirsher o->owner = owner; 65adfc5217SJeff Kirsher 66adfc5217SJeff Kirsher /* Owner specific callbacks */ 67adfc5217SJeff Kirsher o->validate = validate; 68460a25cdSYuval Mintz o->remove = remove; 69adfc5217SJeff Kirsher o->optimize = optimize; 70adfc5217SJeff Kirsher o->execute = exec; 71adfc5217SJeff Kirsher o->get = get; 72adfc5217SJeff Kirsher 7351c1a580SMerav Sicron DP(BNX2X_MSG_SP, "Setup the execution queue with the chunk length of %d\n", 7451c1a580SMerav Sicron exe_len); 75adfc5217SJeff Kirsher } 76adfc5217SJeff Kirsher 77adfc5217SJeff Kirsher static inline void bnx2x_exe_queue_free_elem(struct bnx2x *bp, 78adfc5217SJeff Kirsher struct bnx2x_exeq_elem *elem) 79adfc5217SJeff Kirsher { 80adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "Deleting an exe_queue element\n"); 81adfc5217SJeff Kirsher kfree(elem); 82adfc5217SJeff Kirsher } 83adfc5217SJeff Kirsher 84adfc5217SJeff Kirsher static inline int bnx2x_exe_queue_length(struct bnx2x_exe_queue_obj *o) 85adfc5217SJeff Kirsher { 86adfc5217SJeff Kirsher struct bnx2x_exeq_elem *elem; 87adfc5217SJeff Kirsher int cnt = 0; 88adfc5217SJeff Kirsher 89adfc5217SJeff Kirsher spin_lock_bh(&o->lock); 90adfc5217SJeff Kirsher 91adfc5217SJeff Kirsher list_for_each_entry(elem, &o->exe_queue, link) 92adfc5217SJeff Kirsher cnt++; 93adfc5217SJeff Kirsher 94adfc5217SJeff Kirsher spin_unlock_bh(&o->lock); 95adfc5217SJeff Kirsher 96adfc5217SJeff Kirsher return cnt; 97adfc5217SJeff Kirsher } 98adfc5217SJeff Kirsher 99adfc5217SJeff Kirsher /** 100adfc5217SJeff Kirsher * bnx2x_exe_queue_add - add a new element to the execution queue 101adfc5217SJeff Kirsher * 102adfc5217SJeff Kirsher * @bp: driver handle 103adfc5217SJeff Kirsher * @o: queue 104adfc5217SJeff Kirsher * @cmd: new command to add 105adfc5217SJeff Kirsher * @restore: true - do not optimize the command 106adfc5217SJeff Kirsher * 107adfc5217SJeff Kirsher * If the element is optimized or is illegal, frees it. 108adfc5217SJeff Kirsher */ 109adfc5217SJeff Kirsher static inline int bnx2x_exe_queue_add(struct bnx2x *bp, 110adfc5217SJeff Kirsher struct bnx2x_exe_queue_obj *o, 111adfc5217SJeff Kirsher struct bnx2x_exeq_elem *elem, 112adfc5217SJeff Kirsher bool restore) 113adfc5217SJeff Kirsher { 114adfc5217SJeff Kirsher int rc; 115adfc5217SJeff Kirsher 116adfc5217SJeff Kirsher spin_lock_bh(&o->lock); 117adfc5217SJeff Kirsher 118adfc5217SJeff Kirsher if (!restore) { 119adfc5217SJeff Kirsher /* Try to cancel this element queue */ 120adfc5217SJeff Kirsher rc = o->optimize(bp, o->owner, elem); 121adfc5217SJeff Kirsher if (rc) 122adfc5217SJeff Kirsher goto free_and_exit; 123adfc5217SJeff Kirsher 124adfc5217SJeff Kirsher /* Check if this request is ok */ 125adfc5217SJeff Kirsher rc = o->validate(bp, o->owner, elem); 126adfc5217SJeff Kirsher if (rc) { 1272384d6aaSDmitry Kravkov DP(BNX2X_MSG_SP, "Preamble failed: %d\n", rc); 128adfc5217SJeff Kirsher goto free_and_exit; 129adfc5217SJeff Kirsher } 130adfc5217SJeff Kirsher } 131adfc5217SJeff Kirsher 132adfc5217SJeff Kirsher /* If so, add it to the execution queue */ 133adfc5217SJeff Kirsher list_add_tail(&elem->link, &o->exe_queue); 134adfc5217SJeff Kirsher 135adfc5217SJeff Kirsher spin_unlock_bh(&o->lock); 136adfc5217SJeff Kirsher 137adfc5217SJeff Kirsher return 0; 138adfc5217SJeff Kirsher 139adfc5217SJeff Kirsher free_and_exit: 140adfc5217SJeff Kirsher bnx2x_exe_queue_free_elem(bp, elem); 141adfc5217SJeff Kirsher 142adfc5217SJeff Kirsher spin_unlock_bh(&o->lock); 143adfc5217SJeff Kirsher 144adfc5217SJeff Kirsher return rc; 145adfc5217SJeff Kirsher } 146adfc5217SJeff Kirsher 147adfc5217SJeff Kirsher static inline void __bnx2x_exe_queue_reset_pending( 148adfc5217SJeff Kirsher struct bnx2x *bp, 149adfc5217SJeff Kirsher struct bnx2x_exe_queue_obj *o) 150adfc5217SJeff Kirsher { 151adfc5217SJeff Kirsher struct bnx2x_exeq_elem *elem; 152adfc5217SJeff Kirsher 153adfc5217SJeff Kirsher while (!list_empty(&o->pending_comp)) { 154adfc5217SJeff Kirsher elem = list_first_entry(&o->pending_comp, 155adfc5217SJeff Kirsher struct bnx2x_exeq_elem, link); 156adfc5217SJeff Kirsher 157adfc5217SJeff Kirsher list_del(&elem->link); 158adfc5217SJeff Kirsher bnx2x_exe_queue_free_elem(bp, elem); 159adfc5217SJeff Kirsher } 160adfc5217SJeff Kirsher } 161adfc5217SJeff Kirsher 162adfc5217SJeff Kirsher /** 163adfc5217SJeff Kirsher * bnx2x_exe_queue_step - execute one execution chunk atomically 164adfc5217SJeff Kirsher * 165adfc5217SJeff Kirsher * @bp: driver handle 166adfc5217SJeff Kirsher * @o: queue 167adfc5217SJeff Kirsher * @ramrod_flags: flags 168adfc5217SJeff Kirsher * 1698b09be5fSYuval Mintz * (Should be called while holding the exe_queue->lock). 170adfc5217SJeff Kirsher */ 171adfc5217SJeff Kirsher static inline int bnx2x_exe_queue_step(struct bnx2x *bp, 172adfc5217SJeff Kirsher struct bnx2x_exe_queue_obj *o, 173adfc5217SJeff Kirsher unsigned long *ramrod_flags) 174adfc5217SJeff Kirsher { 175adfc5217SJeff Kirsher struct bnx2x_exeq_elem *elem, spacer; 176adfc5217SJeff Kirsher int cur_len = 0, rc; 177adfc5217SJeff Kirsher 178adfc5217SJeff Kirsher memset(&spacer, 0, sizeof(spacer)); 179adfc5217SJeff Kirsher 18016a5fd92SYuval Mintz /* Next step should not be performed until the current is finished, 181adfc5217SJeff Kirsher * unless a DRV_CLEAR_ONLY bit is set. In this case we just want to 182adfc5217SJeff Kirsher * properly clear object internals without sending any command to the FW 183adfc5217SJeff Kirsher * which also implies there won't be any completion to clear the 184adfc5217SJeff Kirsher * 'pending' list. 185adfc5217SJeff Kirsher */ 186adfc5217SJeff Kirsher if (!list_empty(&o->pending_comp)) { 187adfc5217SJeff Kirsher if (test_bit(RAMROD_DRV_CLR_ONLY, ramrod_flags)) { 18851c1a580SMerav Sicron DP(BNX2X_MSG_SP, "RAMROD_DRV_CLR_ONLY requested: resetting a pending_comp list\n"); 189adfc5217SJeff Kirsher __bnx2x_exe_queue_reset_pending(bp, o); 190adfc5217SJeff Kirsher } else { 191adfc5217SJeff Kirsher return 1; 192adfc5217SJeff Kirsher } 193adfc5217SJeff Kirsher } 194adfc5217SJeff Kirsher 19516a5fd92SYuval Mintz /* Run through the pending commands list and create a next 196adfc5217SJeff Kirsher * execution chunk. 197adfc5217SJeff Kirsher */ 198adfc5217SJeff Kirsher while (!list_empty(&o->exe_queue)) { 199adfc5217SJeff Kirsher elem = list_first_entry(&o->exe_queue, struct bnx2x_exeq_elem, 200adfc5217SJeff Kirsher link); 201adfc5217SJeff Kirsher WARN_ON(!elem->cmd_len); 202adfc5217SJeff Kirsher 203adfc5217SJeff Kirsher if (cur_len + elem->cmd_len <= o->exe_chunk_len) { 204adfc5217SJeff Kirsher cur_len += elem->cmd_len; 20516a5fd92SYuval Mintz /* Prevent from both lists being empty when moving an 206adfc5217SJeff Kirsher * element. This will allow the call of 207adfc5217SJeff Kirsher * bnx2x_exe_queue_empty() without locking. 208adfc5217SJeff Kirsher */ 209adfc5217SJeff Kirsher list_add_tail(&spacer.link, &o->pending_comp); 210adfc5217SJeff Kirsher mb(); 2117933aa5cSWei Yongjun list_move_tail(&elem->link, &o->pending_comp); 212adfc5217SJeff Kirsher list_del(&spacer.link); 213adfc5217SJeff Kirsher } else 214adfc5217SJeff Kirsher break; 215adfc5217SJeff Kirsher } 216adfc5217SJeff Kirsher 217adfc5217SJeff Kirsher /* Sanity check */ 2188b09be5fSYuval Mintz if (!cur_len) 219adfc5217SJeff Kirsher return 0; 220adfc5217SJeff Kirsher 221adfc5217SJeff Kirsher rc = o->execute(bp, o->owner, &o->pending_comp, ramrod_flags); 222adfc5217SJeff Kirsher if (rc < 0) 22316a5fd92SYuval Mintz /* In case of an error return the commands back to the queue 224adfc5217SJeff Kirsher * and reset the pending_comp. 225adfc5217SJeff Kirsher */ 226adfc5217SJeff Kirsher list_splice_init(&o->pending_comp, &o->exe_queue); 227adfc5217SJeff Kirsher else if (!rc) 22816a5fd92SYuval Mintz /* If zero is returned, means there are no outstanding pending 229adfc5217SJeff Kirsher * completions and we may dismiss the pending list. 230adfc5217SJeff Kirsher */ 231adfc5217SJeff Kirsher __bnx2x_exe_queue_reset_pending(bp, o); 232adfc5217SJeff Kirsher 233adfc5217SJeff Kirsher return rc; 234adfc5217SJeff Kirsher } 235adfc5217SJeff Kirsher 236adfc5217SJeff Kirsher static inline bool bnx2x_exe_queue_empty(struct bnx2x_exe_queue_obj *o) 237adfc5217SJeff Kirsher { 238adfc5217SJeff Kirsher bool empty = list_empty(&o->exe_queue); 239adfc5217SJeff Kirsher 240adfc5217SJeff Kirsher /* Don't reorder!!! */ 241adfc5217SJeff Kirsher mb(); 242adfc5217SJeff Kirsher 243adfc5217SJeff Kirsher return empty && list_empty(&o->pending_comp); 244adfc5217SJeff Kirsher } 245adfc5217SJeff Kirsher 246adfc5217SJeff Kirsher static inline struct bnx2x_exeq_elem *bnx2x_exe_queue_alloc_elem( 247adfc5217SJeff Kirsher struct bnx2x *bp) 248adfc5217SJeff Kirsher { 249adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "Allocating a new exe_queue element\n"); 250adfc5217SJeff Kirsher return kzalloc(sizeof(struct bnx2x_exeq_elem), GFP_ATOMIC); 251adfc5217SJeff Kirsher } 252adfc5217SJeff Kirsher 253adfc5217SJeff Kirsher /************************ raw_obj functions ***********************************/ 254adfc5217SJeff Kirsher static bool bnx2x_raw_check_pending(struct bnx2x_raw_obj *o) 255adfc5217SJeff Kirsher { 256adfc5217SJeff Kirsher return !!test_bit(o->state, o->pstate); 257adfc5217SJeff Kirsher } 258adfc5217SJeff Kirsher 259adfc5217SJeff Kirsher static void bnx2x_raw_clear_pending(struct bnx2x_raw_obj *o) 260adfc5217SJeff Kirsher { 2614e857c58SPeter Zijlstra smp_mb__before_atomic(); 262adfc5217SJeff Kirsher clear_bit(o->state, o->pstate); 2634e857c58SPeter Zijlstra smp_mb__after_atomic(); 264adfc5217SJeff Kirsher } 265adfc5217SJeff Kirsher 266adfc5217SJeff Kirsher static void bnx2x_raw_set_pending(struct bnx2x_raw_obj *o) 267adfc5217SJeff Kirsher { 2684e857c58SPeter Zijlstra smp_mb__before_atomic(); 269adfc5217SJeff Kirsher set_bit(o->state, o->pstate); 2704e857c58SPeter Zijlstra smp_mb__after_atomic(); 271adfc5217SJeff Kirsher } 272adfc5217SJeff Kirsher 273adfc5217SJeff Kirsher /** 274adfc5217SJeff Kirsher * bnx2x_state_wait - wait until the given bit(state) is cleared 275adfc5217SJeff Kirsher * 276adfc5217SJeff Kirsher * @bp: device handle 277adfc5217SJeff Kirsher * @state: state which is to be cleared 278adfc5217SJeff Kirsher * @state_p: state buffer 279adfc5217SJeff Kirsher * 280adfc5217SJeff Kirsher */ 281adfc5217SJeff Kirsher static inline int bnx2x_state_wait(struct bnx2x *bp, int state, 282adfc5217SJeff Kirsher unsigned long *pstate) 283adfc5217SJeff Kirsher { 284adfc5217SJeff Kirsher /* can take a while if any port is running */ 285adfc5217SJeff Kirsher int cnt = 5000; 286adfc5217SJeff Kirsher 287adfc5217SJeff Kirsher if (CHIP_REV_IS_EMUL(bp)) 288adfc5217SJeff Kirsher cnt *= 20; 289adfc5217SJeff Kirsher 290adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "waiting for state to become %d\n", state); 291adfc5217SJeff Kirsher 292adfc5217SJeff Kirsher might_sleep(); 293adfc5217SJeff Kirsher while (cnt--) { 294adfc5217SJeff Kirsher if (!test_bit(state, pstate)) { 295adfc5217SJeff Kirsher #ifdef BNX2X_STOP_ON_ERROR 296adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "exit (cnt %d)\n", 5000 - cnt); 297adfc5217SJeff Kirsher #endif 298adfc5217SJeff Kirsher return 0; 299adfc5217SJeff Kirsher } 300adfc5217SJeff Kirsher 3010926d499SYuval Mintz usleep_range(1000, 2000); 302adfc5217SJeff Kirsher 303adfc5217SJeff Kirsher if (bp->panic) 304adfc5217SJeff Kirsher return -EIO; 305adfc5217SJeff Kirsher } 306adfc5217SJeff Kirsher 307adfc5217SJeff Kirsher /* timeout! */ 308adfc5217SJeff Kirsher BNX2X_ERR("timeout waiting for state %d\n", state); 309adfc5217SJeff Kirsher #ifdef BNX2X_STOP_ON_ERROR 310adfc5217SJeff Kirsher bnx2x_panic(); 311adfc5217SJeff Kirsher #endif 312adfc5217SJeff Kirsher 313adfc5217SJeff Kirsher return -EBUSY; 314adfc5217SJeff Kirsher } 315adfc5217SJeff Kirsher 316adfc5217SJeff Kirsher static int bnx2x_raw_wait(struct bnx2x *bp, struct bnx2x_raw_obj *raw) 317adfc5217SJeff Kirsher { 318adfc5217SJeff Kirsher return bnx2x_state_wait(bp, raw->state, raw->pstate); 319adfc5217SJeff Kirsher } 320adfc5217SJeff Kirsher 321adfc5217SJeff Kirsher /***************** Classification verbs: Set/Del MAC/VLAN/VLAN-MAC ************/ 322adfc5217SJeff Kirsher /* credit handling callbacks */ 323adfc5217SJeff Kirsher static bool bnx2x_get_cam_offset_mac(struct bnx2x_vlan_mac_obj *o, int *offset) 324adfc5217SJeff Kirsher { 325adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *mp = o->macs_pool; 326adfc5217SJeff Kirsher 327adfc5217SJeff Kirsher WARN_ON(!mp); 328adfc5217SJeff Kirsher 329adfc5217SJeff Kirsher return mp->get_entry(mp, offset); 330adfc5217SJeff Kirsher } 331adfc5217SJeff Kirsher 332adfc5217SJeff Kirsher static bool bnx2x_get_credit_mac(struct bnx2x_vlan_mac_obj *o) 333adfc5217SJeff Kirsher { 334adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *mp = o->macs_pool; 335adfc5217SJeff Kirsher 336adfc5217SJeff Kirsher WARN_ON(!mp); 337adfc5217SJeff Kirsher 338adfc5217SJeff Kirsher return mp->get(mp, 1); 339adfc5217SJeff Kirsher } 340adfc5217SJeff Kirsher 341adfc5217SJeff Kirsher static bool bnx2x_get_cam_offset_vlan(struct bnx2x_vlan_mac_obj *o, int *offset) 342adfc5217SJeff Kirsher { 343adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *vp = o->vlans_pool; 344adfc5217SJeff Kirsher 345adfc5217SJeff Kirsher WARN_ON(!vp); 346adfc5217SJeff Kirsher 347adfc5217SJeff Kirsher return vp->get_entry(vp, offset); 348adfc5217SJeff Kirsher } 349adfc5217SJeff Kirsher 350adfc5217SJeff Kirsher static bool bnx2x_get_credit_vlan(struct bnx2x_vlan_mac_obj *o) 351adfc5217SJeff Kirsher { 352adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *vp = o->vlans_pool; 353adfc5217SJeff Kirsher 354adfc5217SJeff Kirsher WARN_ON(!vp); 355adfc5217SJeff Kirsher 356adfc5217SJeff Kirsher return vp->get(vp, 1); 357adfc5217SJeff Kirsher } 358adfc5217SJeff Kirsher static bool bnx2x_put_cam_offset_mac(struct bnx2x_vlan_mac_obj *o, int offset) 359adfc5217SJeff Kirsher { 360adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *mp = o->macs_pool; 361adfc5217SJeff Kirsher 362adfc5217SJeff Kirsher return mp->put_entry(mp, offset); 363adfc5217SJeff Kirsher } 364adfc5217SJeff Kirsher 365adfc5217SJeff Kirsher static bool bnx2x_put_credit_mac(struct bnx2x_vlan_mac_obj *o) 366adfc5217SJeff Kirsher { 367adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *mp = o->macs_pool; 368adfc5217SJeff Kirsher 369adfc5217SJeff Kirsher return mp->put(mp, 1); 370adfc5217SJeff Kirsher } 371adfc5217SJeff Kirsher 372adfc5217SJeff Kirsher static bool bnx2x_put_cam_offset_vlan(struct bnx2x_vlan_mac_obj *o, int offset) 373adfc5217SJeff Kirsher { 374adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *vp = o->vlans_pool; 375adfc5217SJeff Kirsher 376adfc5217SJeff Kirsher return vp->put_entry(vp, offset); 377adfc5217SJeff Kirsher } 378adfc5217SJeff Kirsher 379adfc5217SJeff Kirsher static bool bnx2x_put_credit_vlan(struct bnx2x_vlan_mac_obj *o) 380adfc5217SJeff Kirsher { 381adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *vp = o->vlans_pool; 382adfc5217SJeff Kirsher 383adfc5217SJeff Kirsher return vp->put(vp, 1); 384adfc5217SJeff Kirsher } 385adfc5217SJeff Kirsher 3868b09be5fSYuval Mintz /** 3878b09be5fSYuval Mintz * __bnx2x_vlan_mac_h_write_trylock - try getting the vlan mac writer lock 3888b09be5fSYuval Mintz * 3898b09be5fSYuval Mintz * @bp: device handle 3908b09be5fSYuval Mintz * @o: vlan_mac object 3918b09be5fSYuval Mintz * 3928b09be5fSYuval Mintz * @details: Non-blocking implementation; should be called under execution 3938b09be5fSYuval Mintz * queue lock. 3948b09be5fSYuval Mintz */ 3958b09be5fSYuval Mintz static int __bnx2x_vlan_mac_h_write_trylock(struct bnx2x *bp, 3968b09be5fSYuval Mintz struct bnx2x_vlan_mac_obj *o) 3978b09be5fSYuval Mintz { 3988b09be5fSYuval Mintz if (o->head_reader) { 3998b09be5fSYuval Mintz DP(BNX2X_MSG_SP, "vlan_mac_lock writer - There are readers; Busy\n"); 4008b09be5fSYuval Mintz return -EBUSY; 4018b09be5fSYuval Mintz } 4028b09be5fSYuval Mintz 4038b09be5fSYuval Mintz DP(BNX2X_MSG_SP, "vlan_mac_lock writer - Taken\n"); 4048b09be5fSYuval Mintz return 0; 4058b09be5fSYuval Mintz } 4068b09be5fSYuval Mintz 4078b09be5fSYuval Mintz /** 4088b09be5fSYuval Mintz * __bnx2x_vlan_mac_h_exec_pending - execute step instead of a previous step 4098b09be5fSYuval Mintz * 4108b09be5fSYuval Mintz * @bp: device handle 4118b09be5fSYuval Mintz * @o: vlan_mac object 4128b09be5fSYuval Mintz * 4138b09be5fSYuval Mintz * @details Should be called under execution queue lock; notice it might release 4148b09be5fSYuval Mintz * and reclaim it during its run. 4158b09be5fSYuval Mintz */ 4168b09be5fSYuval Mintz static void __bnx2x_vlan_mac_h_exec_pending(struct bnx2x *bp, 4178b09be5fSYuval Mintz struct bnx2x_vlan_mac_obj *o) 4188b09be5fSYuval Mintz { 4198b09be5fSYuval Mintz int rc; 4208b09be5fSYuval Mintz unsigned long ramrod_flags = o->saved_ramrod_flags; 4218b09be5fSYuval Mintz 4228b09be5fSYuval Mintz DP(BNX2X_MSG_SP, "vlan_mac_lock execute pending command with ramrod flags %lu\n", 4238b09be5fSYuval Mintz ramrod_flags); 4248b09be5fSYuval Mintz o->head_exe_request = false; 4258b09be5fSYuval Mintz o->saved_ramrod_flags = 0; 4268b09be5fSYuval Mintz rc = bnx2x_exe_queue_step(bp, &o->exe_queue, &ramrod_flags); 4279d18d270SYuval Mintz if ((rc != 0) && (rc != 1)) { 4288b09be5fSYuval Mintz BNX2X_ERR("execution of pending commands failed with rc %d\n", 4298b09be5fSYuval Mintz rc); 4308b09be5fSYuval Mintz #ifdef BNX2X_STOP_ON_ERROR 4318b09be5fSYuval Mintz bnx2x_panic(); 4328b09be5fSYuval Mintz #endif 4338b09be5fSYuval Mintz } 4348b09be5fSYuval Mintz } 4358b09be5fSYuval Mintz 4368b09be5fSYuval Mintz /** 4378b09be5fSYuval Mintz * __bnx2x_vlan_mac_h_pend - Pend an execution step which couldn't run 4388b09be5fSYuval Mintz * 4398b09be5fSYuval Mintz * @bp: device handle 4408b09be5fSYuval Mintz * @o: vlan_mac object 4418b09be5fSYuval Mintz * @ramrod_flags: ramrod flags of missed execution 4428b09be5fSYuval Mintz * 4438b09be5fSYuval Mintz * @details Should be called under execution queue lock. 4448b09be5fSYuval Mintz */ 4458b09be5fSYuval Mintz static void __bnx2x_vlan_mac_h_pend(struct bnx2x *bp, 4468b09be5fSYuval Mintz struct bnx2x_vlan_mac_obj *o, 4478b09be5fSYuval Mintz unsigned long ramrod_flags) 4488b09be5fSYuval Mintz { 4498b09be5fSYuval Mintz o->head_exe_request = true; 4508b09be5fSYuval Mintz o->saved_ramrod_flags = ramrod_flags; 4518b09be5fSYuval Mintz DP(BNX2X_MSG_SP, "Placing pending execution with ramrod flags %lu\n", 4528b09be5fSYuval Mintz ramrod_flags); 4538b09be5fSYuval Mintz } 4548b09be5fSYuval Mintz 4558b09be5fSYuval Mintz /** 4568b09be5fSYuval Mintz * __bnx2x_vlan_mac_h_write_unlock - unlock the vlan mac head list writer lock 4578b09be5fSYuval Mintz * 4588b09be5fSYuval Mintz * @bp: device handle 4598b09be5fSYuval Mintz * @o: vlan_mac object 4608b09be5fSYuval Mintz * 4618b09be5fSYuval Mintz * @details Should be called under execution queue lock. Notice if a pending 4628b09be5fSYuval Mintz * execution exists, it would perform it - possibly releasing and 4638b09be5fSYuval Mintz * reclaiming the execution queue lock. 4648b09be5fSYuval Mintz */ 4658b09be5fSYuval Mintz static void __bnx2x_vlan_mac_h_write_unlock(struct bnx2x *bp, 4668b09be5fSYuval Mintz struct bnx2x_vlan_mac_obj *o) 4678b09be5fSYuval Mintz { 4688b09be5fSYuval Mintz /* It's possible a new pending execution was added since this writer 4698b09be5fSYuval Mintz * executed. If so, execute again. [Ad infinitum] 4708b09be5fSYuval Mintz */ 4718b09be5fSYuval Mintz while (o->head_exe_request) { 4728b09be5fSYuval Mintz DP(BNX2X_MSG_SP, "vlan_mac_lock - writer release encountered a pending request\n"); 4738b09be5fSYuval Mintz __bnx2x_vlan_mac_h_exec_pending(bp, o); 4748b09be5fSYuval Mintz } 4758b09be5fSYuval Mintz } 4768b09be5fSYuval Mintz 4778b09be5fSYuval Mintz 4788b09be5fSYuval Mintz /** 4798b09be5fSYuval Mintz * __bnx2x_vlan_mac_h_read_lock - lock the vlan mac head list reader lock 4808b09be5fSYuval Mintz * 4818b09be5fSYuval Mintz * @bp: device handle 4828b09be5fSYuval Mintz * @o: vlan_mac object 4838b09be5fSYuval Mintz * 4848b09be5fSYuval Mintz * @details Should be called under the execution queue lock. May sleep. May 4858b09be5fSYuval Mintz * release and reclaim execution queue lock during its run. 4868b09be5fSYuval Mintz */ 4878b09be5fSYuval Mintz static int __bnx2x_vlan_mac_h_read_lock(struct bnx2x *bp, 4888b09be5fSYuval Mintz struct bnx2x_vlan_mac_obj *o) 4898b09be5fSYuval Mintz { 4908b09be5fSYuval Mintz /* If we got here, we're holding lock --> no WRITER exists */ 4918b09be5fSYuval Mintz o->head_reader++; 4928b09be5fSYuval Mintz DP(BNX2X_MSG_SP, "vlan_mac_lock - locked reader - number %d\n", 4938b09be5fSYuval Mintz o->head_reader); 4948b09be5fSYuval Mintz 4958b09be5fSYuval Mintz return 0; 4968b09be5fSYuval Mintz } 4978b09be5fSYuval Mintz 4988b09be5fSYuval Mintz /** 4998b09be5fSYuval Mintz * bnx2x_vlan_mac_h_read_lock - lock the vlan mac head list reader lock 5008b09be5fSYuval Mintz * 5018b09be5fSYuval Mintz * @bp: device handle 5028b09be5fSYuval Mintz * @o: vlan_mac object 5038b09be5fSYuval Mintz * 5048b09be5fSYuval Mintz * @details May sleep. Claims and releases execution queue lock during its run. 5058b09be5fSYuval Mintz */ 5068b09be5fSYuval Mintz int bnx2x_vlan_mac_h_read_lock(struct bnx2x *bp, 5078b09be5fSYuval Mintz struct bnx2x_vlan_mac_obj *o) 5088b09be5fSYuval Mintz { 5098b09be5fSYuval Mintz int rc; 5108b09be5fSYuval Mintz 5118b09be5fSYuval Mintz spin_lock_bh(&o->exe_queue.lock); 5128b09be5fSYuval Mintz rc = __bnx2x_vlan_mac_h_read_lock(bp, o); 5138b09be5fSYuval Mintz spin_unlock_bh(&o->exe_queue.lock); 5148b09be5fSYuval Mintz 5158b09be5fSYuval Mintz return rc; 5168b09be5fSYuval Mintz } 5178b09be5fSYuval Mintz 5188b09be5fSYuval Mintz /** 5198b09be5fSYuval Mintz * __bnx2x_vlan_mac_h_read_unlock - unlock the vlan mac head list reader lock 5208b09be5fSYuval Mintz * 5218b09be5fSYuval Mintz * @bp: device handle 5228b09be5fSYuval Mintz * @o: vlan_mac object 5238b09be5fSYuval Mintz * 5248b09be5fSYuval Mintz * @details Should be called under execution queue lock. Notice if a pending 5258b09be5fSYuval Mintz * execution exists, it would be performed if this was the last 5268b09be5fSYuval Mintz * reader. possibly releasing and reclaiming the execution queue lock. 5278b09be5fSYuval Mintz */ 5288b09be5fSYuval Mintz static void __bnx2x_vlan_mac_h_read_unlock(struct bnx2x *bp, 5298b09be5fSYuval Mintz struct bnx2x_vlan_mac_obj *o) 5308b09be5fSYuval Mintz { 5318b09be5fSYuval Mintz if (!o->head_reader) { 5328b09be5fSYuval Mintz BNX2X_ERR("Need to release vlan mac reader lock, but lock isn't taken\n"); 5338b09be5fSYuval Mintz #ifdef BNX2X_STOP_ON_ERROR 5348b09be5fSYuval Mintz bnx2x_panic(); 5358b09be5fSYuval Mintz #endif 5368b09be5fSYuval Mintz } else { 5378b09be5fSYuval Mintz o->head_reader--; 5388b09be5fSYuval Mintz DP(BNX2X_MSG_SP, "vlan_mac_lock - decreased readers to %d\n", 5398b09be5fSYuval Mintz o->head_reader); 5408b09be5fSYuval Mintz } 5418b09be5fSYuval Mintz 5428b09be5fSYuval Mintz /* It's possible a new pending execution was added, and that this reader 5438b09be5fSYuval Mintz * was last - if so we need to execute the command. 5448b09be5fSYuval Mintz */ 5458b09be5fSYuval Mintz if (!o->head_reader && o->head_exe_request) { 5468b09be5fSYuval Mintz DP(BNX2X_MSG_SP, "vlan_mac_lock - reader release encountered a pending request\n"); 5478b09be5fSYuval Mintz 5488b09be5fSYuval Mintz /* Writer release will do the trick */ 5498b09be5fSYuval Mintz __bnx2x_vlan_mac_h_write_unlock(bp, o); 5508b09be5fSYuval Mintz } 5518b09be5fSYuval Mintz } 5528b09be5fSYuval Mintz 5538b09be5fSYuval Mintz /** 5548b09be5fSYuval Mintz * bnx2x_vlan_mac_h_read_unlock - unlock the vlan mac head list reader lock 5558b09be5fSYuval Mintz * 5568b09be5fSYuval Mintz * @bp: device handle 5578b09be5fSYuval Mintz * @o: vlan_mac object 5588b09be5fSYuval Mintz * 5598b09be5fSYuval Mintz * @details Notice if a pending execution exists, it would be performed if this 5608b09be5fSYuval Mintz * was the last reader. Claims and releases the execution queue lock 5618b09be5fSYuval Mintz * during its run. 5628b09be5fSYuval Mintz */ 5638b09be5fSYuval Mintz void bnx2x_vlan_mac_h_read_unlock(struct bnx2x *bp, 5648b09be5fSYuval Mintz struct bnx2x_vlan_mac_obj *o) 5658b09be5fSYuval Mintz { 5668b09be5fSYuval Mintz spin_lock_bh(&o->exe_queue.lock); 5678b09be5fSYuval Mintz __bnx2x_vlan_mac_h_read_unlock(bp, o); 5688b09be5fSYuval Mintz spin_unlock_bh(&o->exe_queue.lock); 5698b09be5fSYuval Mintz } 5708b09be5fSYuval Mintz 571ed5162a0SAriel Elior static int bnx2x_get_n_elements(struct bnx2x *bp, struct bnx2x_vlan_mac_obj *o, 5723ec9f9caSAriel Elior int n, u8 *base, u8 stride, u8 size) 573ed5162a0SAriel Elior { 574ed5162a0SAriel Elior struct bnx2x_vlan_mac_registry_elem *pos; 5753ec9f9caSAriel Elior u8 *next = base; 576ed5162a0SAriel Elior int counter = 0; 5778b09be5fSYuval Mintz int read_lock; 5788b09be5fSYuval Mintz 5798b09be5fSYuval Mintz DP(BNX2X_MSG_SP, "get_n_elements - taking vlan_mac_lock (reader)\n"); 5808b09be5fSYuval Mintz read_lock = bnx2x_vlan_mac_h_read_lock(bp, o); 5818b09be5fSYuval Mintz if (read_lock != 0) 5828b09be5fSYuval Mintz BNX2X_ERR("get_n_elements failed to get vlan mac reader lock; Access without lock\n"); 583ed5162a0SAriel Elior 584ed5162a0SAriel Elior /* traverse list */ 585ed5162a0SAriel Elior list_for_each_entry(pos, &o->head, link) { 586ed5162a0SAriel Elior if (counter < n) { 5873ec9f9caSAriel Elior memcpy(next, &pos->u, size); 588ed5162a0SAriel Elior counter++; 5893ec9f9caSAriel Elior DP(BNX2X_MSG_SP, "copied element number %d to address %p element was:\n", 5903ec9f9caSAriel Elior counter, next); 5913ec9f9caSAriel Elior next += stride + size; 592ed5162a0SAriel Elior } 593ed5162a0SAriel Elior } 5948b09be5fSYuval Mintz 5958b09be5fSYuval Mintz if (read_lock == 0) { 5968b09be5fSYuval Mintz DP(BNX2X_MSG_SP, "get_n_elements - releasing vlan_mac_lock (reader)\n"); 5978b09be5fSYuval Mintz bnx2x_vlan_mac_h_read_unlock(bp, o); 5988b09be5fSYuval Mintz } 5998b09be5fSYuval Mintz 600ed5162a0SAriel Elior return counter * ETH_ALEN; 601ed5162a0SAriel Elior } 602ed5162a0SAriel Elior 603adfc5217SJeff Kirsher /* check_add() callbacks */ 60451c1a580SMerav Sicron static int bnx2x_check_mac_add(struct bnx2x *bp, 60551c1a580SMerav Sicron struct bnx2x_vlan_mac_obj *o, 606adfc5217SJeff Kirsher union bnx2x_classification_ramrod_data *data) 607adfc5217SJeff Kirsher { 608adfc5217SJeff Kirsher struct bnx2x_vlan_mac_registry_elem *pos; 609adfc5217SJeff Kirsher 61051c1a580SMerav Sicron DP(BNX2X_MSG_SP, "Checking MAC %pM for ADD command\n", data->mac.mac); 61151c1a580SMerav Sicron 612adfc5217SJeff Kirsher if (!is_valid_ether_addr(data->mac.mac)) 613adfc5217SJeff Kirsher return -EINVAL; 614adfc5217SJeff Kirsher 615adfc5217SJeff Kirsher /* Check if a requested MAC already exists */ 616adfc5217SJeff Kirsher list_for_each_entry(pos, &o->head, link) 6178fd90de8Sdingtianhong if (ether_addr_equal(data->mac.mac, pos->u.mac.mac) && 61891226790SDmitry Kravkov (data->mac.is_inner_mac == pos->u.mac.is_inner_mac)) 619adfc5217SJeff Kirsher return -EEXIST; 620adfc5217SJeff Kirsher 621adfc5217SJeff Kirsher return 0; 622adfc5217SJeff Kirsher } 623adfc5217SJeff Kirsher 62451c1a580SMerav Sicron static int bnx2x_check_vlan_add(struct bnx2x *bp, 62551c1a580SMerav Sicron struct bnx2x_vlan_mac_obj *o, 626adfc5217SJeff Kirsher union bnx2x_classification_ramrod_data *data) 627adfc5217SJeff Kirsher { 628adfc5217SJeff Kirsher struct bnx2x_vlan_mac_registry_elem *pos; 629adfc5217SJeff Kirsher 63051c1a580SMerav Sicron DP(BNX2X_MSG_SP, "Checking VLAN %d for ADD command\n", data->vlan.vlan); 63151c1a580SMerav Sicron 632adfc5217SJeff Kirsher list_for_each_entry(pos, &o->head, link) 633adfc5217SJeff Kirsher if (data->vlan.vlan == pos->u.vlan.vlan) 634adfc5217SJeff Kirsher return -EEXIST; 635adfc5217SJeff Kirsher 636adfc5217SJeff Kirsher return 0; 637adfc5217SJeff Kirsher } 638adfc5217SJeff Kirsher 639adfc5217SJeff Kirsher /* check_del() callbacks */ 640adfc5217SJeff Kirsher static struct bnx2x_vlan_mac_registry_elem * 64151c1a580SMerav Sicron bnx2x_check_mac_del(struct bnx2x *bp, 64251c1a580SMerav Sicron struct bnx2x_vlan_mac_obj *o, 643adfc5217SJeff Kirsher union bnx2x_classification_ramrod_data *data) 644adfc5217SJeff Kirsher { 645adfc5217SJeff Kirsher struct bnx2x_vlan_mac_registry_elem *pos; 646adfc5217SJeff Kirsher 64751c1a580SMerav Sicron DP(BNX2X_MSG_SP, "Checking MAC %pM for DEL command\n", data->mac.mac); 64851c1a580SMerav Sicron 649adfc5217SJeff Kirsher list_for_each_entry(pos, &o->head, link) 6508fd90de8Sdingtianhong if (ether_addr_equal(data->mac.mac, pos->u.mac.mac) && 65191226790SDmitry Kravkov (data->mac.is_inner_mac == pos->u.mac.is_inner_mac)) 652adfc5217SJeff Kirsher return pos; 653adfc5217SJeff Kirsher 654adfc5217SJeff Kirsher return NULL; 655adfc5217SJeff Kirsher } 656adfc5217SJeff Kirsher 657adfc5217SJeff Kirsher static struct bnx2x_vlan_mac_registry_elem * 65851c1a580SMerav Sicron bnx2x_check_vlan_del(struct bnx2x *bp, 65951c1a580SMerav Sicron struct bnx2x_vlan_mac_obj *o, 660adfc5217SJeff Kirsher union bnx2x_classification_ramrod_data *data) 661adfc5217SJeff Kirsher { 662adfc5217SJeff Kirsher struct bnx2x_vlan_mac_registry_elem *pos; 663adfc5217SJeff Kirsher 66451c1a580SMerav Sicron DP(BNX2X_MSG_SP, "Checking VLAN %d for DEL command\n", data->vlan.vlan); 66551c1a580SMerav Sicron 666adfc5217SJeff Kirsher list_for_each_entry(pos, &o->head, link) 667adfc5217SJeff Kirsher if (data->vlan.vlan == pos->u.vlan.vlan) 668adfc5217SJeff Kirsher return pos; 669adfc5217SJeff Kirsher 670adfc5217SJeff Kirsher return NULL; 671adfc5217SJeff Kirsher } 672adfc5217SJeff Kirsher 673adfc5217SJeff Kirsher /* check_move() callback */ 67451c1a580SMerav Sicron static bool bnx2x_check_move(struct bnx2x *bp, 67551c1a580SMerav Sicron struct bnx2x_vlan_mac_obj *src_o, 676adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *dst_o, 677adfc5217SJeff Kirsher union bnx2x_classification_ramrod_data *data) 678adfc5217SJeff Kirsher { 679adfc5217SJeff Kirsher struct bnx2x_vlan_mac_registry_elem *pos; 680adfc5217SJeff Kirsher int rc; 681adfc5217SJeff Kirsher 682adfc5217SJeff Kirsher /* Check if we can delete the requested configuration from the first 683adfc5217SJeff Kirsher * object. 684adfc5217SJeff Kirsher */ 68551c1a580SMerav Sicron pos = src_o->check_del(bp, src_o, data); 686adfc5217SJeff Kirsher 687adfc5217SJeff Kirsher /* check if configuration can be added */ 68851c1a580SMerav Sicron rc = dst_o->check_add(bp, dst_o, data); 689adfc5217SJeff Kirsher 690adfc5217SJeff Kirsher /* If this classification can not be added (is already set) 691adfc5217SJeff Kirsher * or can't be deleted - return an error. 692adfc5217SJeff Kirsher */ 693adfc5217SJeff Kirsher if (rc || !pos) 694adfc5217SJeff Kirsher return false; 695adfc5217SJeff Kirsher 696adfc5217SJeff Kirsher return true; 697adfc5217SJeff Kirsher } 698adfc5217SJeff Kirsher 699adfc5217SJeff Kirsher static bool bnx2x_check_move_always_err( 70051c1a580SMerav Sicron struct bnx2x *bp, 701adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *src_o, 702adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *dst_o, 703adfc5217SJeff Kirsher union bnx2x_classification_ramrod_data *data) 704adfc5217SJeff Kirsher { 705adfc5217SJeff Kirsher return false; 706adfc5217SJeff Kirsher } 707adfc5217SJeff Kirsher 708adfc5217SJeff Kirsher static inline u8 bnx2x_vlan_mac_get_rx_tx_flag(struct bnx2x_vlan_mac_obj *o) 709adfc5217SJeff Kirsher { 710adfc5217SJeff Kirsher struct bnx2x_raw_obj *raw = &o->raw; 711adfc5217SJeff Kirsher u8 rx_tx_flag = 0; 712adfc5217SJeff Kirsher 713adfc5217SJeff Kirsher if ((raw->obj_type == BNX2X_OBJ_TYPE_TX) || 714adfc5217SJeff Kirsher (raw->obj_type == BNX2X_OBJ_TYPE_RX_TX)) 715adfc5217SJeff Kirsher rx_tx_flag |= ETH_CLASSIFY_CMD_HEADER_TX_CMD; 716adfc5217SJeff Kirsher 717adfc5217SJeff Kirsher if ((raw->obj_type == BNX2X_OBJ_TYPE_RX) || 718adfc5217SJeff Kirsher (raw->obj_type == BNX2X_OBJ_TYPE_RX_TX)) 719adfc5217SJeff Kirsher rx_tx_flag |= ETH_CLASSIFY_CMD_HEADER_RX_CMD; 720adfc5217SJeff Kirsher 721adfc5217SJeff Kirsher return rx_tx_flag; 722adfc5217SJeff Kirsher } 723adfc5217SJeff Kirsher 724a8f47eb7Sstephen hemminger static void bnx2x_set_mac_in_nig(struct bnx2x *bp, 725adfc5217SJeff Kirsher bool add, unsigned char *dev_addr, int index) 726adfc5217SJeff Kirsher { 727adfc5217SJeff Kirsher u32 wb_data[2]; 728adfc5217SJeff Kirsher u32 reg_offset = BP_PORT(bp) ? NIG_REG_LLH1_FUNC_MEM : 729adfc5217SJeff Kirsher NIG_REG_LLH0_FUNC_MEM; 730adfc5217SJeff Kirsher 731a3348722SBarak Witkowski if (!IS_MF_SI(bp) && !IS_MF_AFEX(bp)) 732a3348722SBarak Witkowski return; 733a3348722SBarak Witkowski 734a3348722SBarak Witkowski if (index > BNX2X_LLH_CAM_MAX_PF_LINE) 735adfc5217SJeff Kirsher return; 736adfc5217SJeff Kirsher 737adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "Going to %s LLH configuration at entry %d\n", 738adfc5217SJeff Kirsher (add ? "ADD" : "DELETE"), index); 739adfc5217SJeff Kirsher 740adfc5217SJeff Kirsher if (add) { 741adfc5217SJeff Kirsher /* LLH_FUNC_MEM is a u64 WB register */ 742adfc5217SJeff Kirsher reg_offset += 8*index; 743adfc5217SJeff Kirsher 744adfc5217SJeff Kirsher wb_data[0] = ((dev_addr[2] << 24) | (dev_addr[3] << 16) | 745adfc5217SJeff Kirsher (dev_addr[4] << 8) | dev_addr[5]); 746adfc5217SJeff Kirsher wb_data[1] = ((dev_addr[0] << 8) | dev_addr[1]); 747adfc5217SJeff Kirsher 748adfc5217SJeff Kirsher REG_WR_DMAE(bp, reg_offset, wb_data, 2); 749adfc5217SJeff Kirsher } 750adfc5217SJeff Kirsher 751adfc5217SJeff Kirsher REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_FUNC_MEM_ENABLE : 752adfc5217SJeff Kirsher NIG_REG_LLH0_FUNC_MEM_ENABLE) + 4*index, add); 753adfc5217SJeff Kirsher } 754adfc5217SJeff Kirsher 755adfc5217SJeff Kirsher /** 756adfc5217SJeff Kirsher * bnx2x_vlan_mac_set_cmd_hdr_e2 - set a header in a single classify ramrod 757adfc5217SJeff Kirsher * 758adfc5217SJeff Kirsher * @bp: device handle 759adfc5217SJeff Kirsher * @o: queue for which we want to configure this rule 760adfc5217SJeff Kirsher * @add: if true the command is an ADD command, DEL otherwise 761adfc5217SJeff Kirsher * @opcode: CLASSIFY_RULE_OPCODE_XXX 762adfc5217SJeff Kirsher * @hdr: pointer to a header to setup 763adfc5217SJeff Kirsher * 764adfc5217SJeff Kirsher */ 765adfc5217SJeff Kirsher static inline void bnx2x_vlan_mac_set_cmd_hdr_e2(struct bnx2x *bp, 766adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *o, bool add, int opcode, 767adfc5217SJeff Kirsher struct eth_classify_cmd_header *hdr) 768adfc5217SJeff Kirsher { 769adfc5217SJeff Kirsher struct bnx2x_raw_obj *raw = &o->raw; 770adfc5217SJeff Kirsher 771adfc5217SJeff Kirsher hdr->client_id = raw->cl_id; 772adfc5217SJeff Kirsher hdr->func_id = raw->func_id; 773adfc5217SJeff Kirsher 774adfc5217SJeff Kirsher /* Rx or/and Tx (internal switching) configuration ? */ 775adfc5217SJeff Kirsher hdr->cmd_general_data |= 776adfc5217SJeff Kirsher bnx2x_vlan_mac_get_rx_tx_flag(o); 777adfc5217SJeff Kirsher 778adfc5217SJeff Kirsher if (add) 779adfc5217SJeff Kirsher hdr->cmd_general_data |= ETH_CLASSIFY_CMD_HEADER_IS_ADD; 780adfc5217SJeff Kirsher 781adfc5217SJeff Kirsher hdr->cmd_general_data |= 782adfc5217SJeff Kirsher (opcode << ETH_CLASSIFY_CMD_HEADER_OPCODE_SHIFT); 783adfc5217SJeff Kirsher } 784adfc5217SJeff Kirsher 785adfc5217SJeff Kirsher /** 786adfc5217SJeff Kirsher * bnx2x_vlan_mac_set_rdata_hdr_e2 - set the classify ramrod data header 787adfc5217SJeff Kirsher * 788adfc5217SJeff Kirsher * @cid: connection id 789adfc5217SJeff Kirsher * @type: BNX2X_FILTER_XXX_PENDING 79016a5fd92SYuval Mintz * @hdr: pointer to header to setup 791adfc5217SJeff Kirsher * @rule_cnt: 792adfc5217SJeff Kirsher * 793adfc5217SJeff Kirsher * currently we always configure one rule and echo field to contain a CID and an 794adfc5217SJeff Kirsher * opcode type. 795adfc5217SJeff Kirsher */ 796adfc5217SJeff Kirsher static inline void bnx2x_vlan_mac_set_rdata_hdr_e2(u32 cid, int type, 797adfc5217SJeff Kirsher struct eth_classify_header *hdr, int rule_cnt) 798adfc5217SJeff Kirsher { 79986564c3fSYuval Mintz hdr->echo = cpu_to_le32((cid & BNX2X_SWCID_MASK) | 80086564c3fSYuval Mintz (type << BNX2X_SWCID_SHIFT)); 801adfc5217SJeff Kirsher hdr->rule_cnt = (u8)rule_cnt; 802adfc5217SJeff Kirsher } 803adfc5217SJeff Kirsher 804adfc5217SJeff Kirsher /* hw_config() callbacks */ 805adfc5217SJeff Kirsher static void bnx2x_set_one_mac_e2(struct bnx2x *bp, 806adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *o, 807adfc5217SJeff Kirsher struct bnx2x_exeq_elem *elem, int rule_idx, 808adfc5217SJeff Kirsher int cam_offset) 809adfc5217SJeff Kirsher { 810adfc5217SJeff Kirsher struct bnx2x_raw_obj *raw = &o->raw; 811adfc5217SJeff Kirsher struct eth_classify_rules_ramrod_data *data = 812adfc5217SJeff Kirsher (struct eth_classify_rules_ramrod_data *)(raw->rdata); 813adfc5217SJeff Kirsher int rule_cnt = rule_idx + 1, cmd = elem->cmd_data.vlan_mac.cmd; 814adfc5217SJeff Kirsher union eth_classify_rule_cmd *rule_entry = &data->rules[rule_idx]; 815adfc5217SJeff Kirsher bool add = (cmd == BNX2X_VLAN_MAC_ADD) ? true : false; 816adfc5217SJeff Kirsher unsigned long *vlan_mac_flags = &elem->cmd_data.vlan_mac.vlan_mac_flags; 817adfc5217SJeff Kirsher u8 *mac = elem->cmd_data.vlan_mac.u.mac.mac; 818adfc5217SJeff Kirsher 81916a5fd92SYuval Mintz /* Set LLH CAM entry: currently only iSCSI and ETH macs are 820adfc5217SJeff Kirsher * relevant. In addition, current implementation is tuned for a 821adfc5217SJeff Kirsher * single ETH MAC. 822adfc5217SJeff Kirsher * 823adfc5217SJeff Kirsher * When multiple unicast ETH MACs PF configuration in switch 824adfc5217SJeff Kirsher * independent mode is required (NetQ, multiple netdev MACs, 825adfc5217SJeff Kirsher * etc.), consider better utilisation of 8 per function MAC 826adfc5217SJeff Kirsher * entries in the LLH register. There is also 827adfc5217SJeff Kirsher * NIG_REG_P[01]_LLH_FUNC_MEM2 registers that complete the 828adfc5217SJeff Kirsher * total number of CAM entries to 16. 829adfc5217SJeff Kirsher * 830adfc5217SJeff Kirsher * Currently we won't configure NIG for MACs other than a primary ETH 831adfc5217SJeff Kirsher * MAC and iSCSI L2 MAC. 832adfc5217SJeff Kirsher * 833adfc5217SJeff Kirsher * If this MAC is moving from one Queue to another, no need to change 834adfc5217SJeff Kirsher * NIG configuration. 835adfc5217SJeff Kirsher */ 836adfc5217SJeff Kirsher if (cmd != BNX2X_VLAN_MAC_MOVE) { 837adfc5217SJeff Kirsher if (test_bit(BNX2X_ISCSI_ETH_MAC, vlan_mac_flags)) 838adfc5217SJeff Kirsher bnx2x_set_mac_in_nig(bp, add, mac, 8390a52fd01SYuval Mintz BNX2X_LLH_CAM_ISCSI_ETH_LINE); 840adfc5217SJeff Kirsher else if (test_bit(BNX2X_ETH_MAC, vlan_mac_flags)) 8410a52fd01SYuval Mintz bnx2x_set_mac_in_nig(bp, add, mac, 8420a52fd01SYuval Mintz BNX2X_LLH_CAM_ETH_LINE); 843adfc5217SJeff Kirsher } 844adfc5217SJeff Kirsher 845adfc5217SJeff Kirsher /* Reset the ramrod data buffer for the first rule */ 846adfc5217SJeff Kirsher if (rule_idx == 0) 847adfc5217SJeff Kirsher memset(data, 0, sizeof(*data)); 848adfc5217SJeff Kirsher 849adfc5217SJeff Kirsher /* Setup a command header */ 850adfc5217SJeff Kirsher bnx2x_vlan_mac_set_cmd_hdr_e2(bp, o, add, CLASSIFY_RULE_OPCODE_MAC, 851adfc5217SJeff Kirsher &rule_entry->mac.header); 852adfc5217SJeff Kirsher 8530f9dad10SJoe Perches DP(BNX2X_MSG_SP, "About to %s MAC %pM for Queue %d\n", 85451c1a580SMerav Sicron (add ? "add" : "delete"), mac, raw->cl_id); 855adfc5217SJeff Kirsher 856adfc5217SJeff Kirsher /* Set a MAC itself */ 857adfc5217SJeff Kirsher bnx2x_set_fw_mac_addr(&rule_entry->mac.mac_msb, 858adfc5217SJeff Kirsher &rule_entry->mac.mac_mid, 859adfc5217SJeff Kirsher &rule_entry->mac.mac_lsb, mac); 86091226790SDmitry Kravkov rule_entry->mac.inner_mac = 86191226790SDmitry Kravkov cpu_to_le16(elem->cmd_data.vlan_mac.u.mac.is_inner_mac); 862adfc5217SJeff Kirsher 863adfc5217SJeff Kirsher /* MOVE: Add a rule that will add this MAC to the target Queue */ 864adfc5217SJeff Kirsher if (cmd == BNX2X_VLAN_MAC_MOVE) { 865adfc5217SJeff Kirsher rule_entry++; 866adfc5217SJeff Kirsher rule_cnt++; 867adfc5217SJeff Kirsher 868adfc5217SJeff Kirsher /* Setup ramrod data */ 869adfc5217SJeff Kirsher bnx2x_vlan_mac_set_cmd_hdr_e2(bp, 870adfc5217SJeff Kirsher elem->cmd_data.vlan_mac.target_obj, 871adfc5217SJeff Kirsher true, CLASSIFY_RULE_OPCODE_MAC, 872adfc5217SJeff Kirsher &rule_entry->mac.header); 873adfc5217SJeff Kirsher 874adfc5217SJeff Kirsher /* Set a MAC itself */ 875adfc5217SJeff Kirsher bnx2x_set_fw_mac_addr(&rule_entry->mac.mac_msb, 876adfc5217SJeff Kirsher &rule_entry->mac.mac_mid, 877adfc5217SJeff Kirsher &rule_entry->mac.mac_lsb, mac); 87891226790SDmitry Kravkov rule_entry->mac.inner_mac = 87991226790SDmitry Kravkov cpu_to_le16(elem->cmd_data.vlan_mac. 88091226790SDmitry Kravkov u.mac.is_inner_mac); 881adfc5217SJeff Kirsher } 882adfc5217SJeff Kirsher 883adfc5217SJeff Kirsher /* Set the ramrod data header */ 884adfc5217SJeff Kirsher /* TODO: take this to the higher level in order to prevent multiple 885adfc5217SJeff Kirsher writing */ 886adfc5217SJeff Kirsher bnx2x_vlan_mac_set_rdata_hdr_e2(raw->cid, raw->state, &data->header, 887adfc5217SJeff Kirsher rule_cnt); 888adfc5217SJeff Kirsher } 889adfc5217SJeff Kirsher 890adfc5217SJeff Kirsher /** 891adfc5217SJeff Kirsher * bnx2x_vlan_mac_set_rdata_hdr_e1x - set a header in a single classify ramrod 892adfc5217SJeff Kirsher * 893adfc5217SJeff Kirsher * @bp: device handle 894adfc5217SJeff Kirsher * @o: queue 895adfc5217SJeff Kirsher * @type: 896adfc5217SJeff Kirsher * @cam_offset: offset in cam memory 897adfc5217SJeff Kirsher * @hdr: pointer to a header to setup 898adfc5217SJeff Kirsher * 899adfc5217SJeff Kirsher * E1/E1H 900adfc5217SJeff Kirsher */ 901adfc5217SJeff Kirsher static inline void bnx2x_vlan_mac_set_rdata_hdr_e1x(struct bnx2x *bp, 902adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *o, int type, int cam_offset, 903adfc5217SJeff Kirsher struct mac_configuration_hdr *hdr) 904adfc5217SJeff Kirsher { 905adfc5217SJeff Kirsher struct bnx2x_raw_obj *r = &o->raw; 906adfc5217SJeff Kirsher 907adfc5217SJeff Kirsher hdr->length = 1; 908adfc5217SJeff Kirsher hdr->offset = (u8)cam_offset; 90986564c3fSYuval Mintz hdr->client_id = cpu_to_le16(0xff); 91086564c3fSYuval Mintz hdr->echo = cpu_to_le32((r->cid & BNX2X_SWCID_MASK) | 91186564c3fSYuval Mintz (type << BNX2X_SWCID_SHIFT)); 912adfc5217SJeff Kirsher } 913adfc5217SJeff Kirsher 914adfc5217SJeff Kirsher static inline void bnx2x_vlan_mac_set_cfg_entry_e1x(struct bnx2x *bp, 915adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *o, bool add, int opcode, u8 *mac, 916adfc5217SJeff Kirsher u16 vlan_id, struct mac_configuration_entry *cfg_entry) 917adfc5217SJeff Kirsher { 918adfc5217SJeff Kirsher struct bnx2x_raw_obj *r = &o->raw; 919adfc5217SJeff Kirsher u32 cl_bit_vec = (1 << r->cl_id); 920adfc5217SJeff Kirsher 921adfc5217SJeff Kirsher cfg_entry->clients_bit_vector = cpu_to_le32(cl_bit_vec); 922adfc5217SJeff Kirsher cfg_entry->pf_id = r->func_id; 923adfc5217SJeff Kirsher cfg_entry->vlan_id = cpu_to_le16(vlan_id); 924adfc5217SJeff Kirsher 925adfc5217SJeff Kirsher if (add) { 926adfc5217SJeff Kirsher SET_FLAG(cfg_entry->flags, MAC_CONFIGURATION_ENTRY_ACTION_TYPE, 927adfc5217SJeff Kirsher T_ETH_MAC_COMMAND_SET); 928adfc5217SJeff Kirsher SET_FLAG(cfg_entry->flags, 929adfc5217SJeff Kirsher MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE, opcode); 930adfc5217SJeff Kirsher 931adfc5217SJeff Kirsher /* Set a MAC in a ramrod data */ 932adfc5217SJeff Kirsher bnx2x_set_fw_mac_addr(&cfg_entry->msb_mac_addr, 933adfc5217SJeff Kirsher &cfg_entry->middle_mac_addr, 934adfc5217SJeff Kirsher &cfg_entry->lsb_mac_addr, mac); 935adfc5217SJeff Kirsher } else 936adfc5217SJeff Kirsher SET_FLAG(cfg_entry->flags, MAC_CONFIGURATION_ENTRY_ACTION_TYPE, 937adfc5217SJeff Kirsher T_ETH_MAC_COMMAND_INVALIDATE); 938adfc5217SJeff Kirsher } 939adfc5217SJeff Kirsher 940adfc5217SJeff Kirsher static inline void bnx2x_vlan_mac_set_rdata_e1x(struct bnx2x *bp, 941adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *o, int type, int cam_offset, bool add, 942adfc5217SJeff Kirsher u8 *mac, u16 vlan_id, int opcode, struct mac_configuration_cmd *config) 943adfc5217SJeff Kirsher { 944adfc5217SJeff Kirsher struct mac_configuration_entry *cfg_entry = &config->config_table[0]; 945adfc5217SJeff Kirsher struct bnx2x_raw_obj *raw = &o->raw; 946adfc5217SJeff Kirsher 947adfc5217SJeff Kirsher bnx2x_vlan_mac_set_rdata_hdr_e1x(bp, o, type, cam_offset, 948adfc5217SJeff Kirsher &config->hdr); 949adfc5217SJeff Kirsher bnx2x_vlan_mac_set_cfg_entry_e1x(bp, o, add, opcode, mac, vlan_id, 950adfc5217SJeff Kirsher cfg_entry); 951adfc5217SJeff Kirsher 9520f9dad10SJoe Perches DP(BNX2X_MSG_SP, "%s MAC %pM CLID %d CAM offset %d\n", 95351c1a580SMerav Sicron (add ? "setting" : "clearing"), 9540f9dad10SJoe Perches mac, raw->cl_id, cam_offset); 955adfc5217SJeff Kirsher } 956adfc5217SJeff Kirsher 957adfc5217SJeff Kirsher /** 958adfc5217SJeff Kirsher * bnx2x_set_one_mac_e1x - fill a single MAC rule ramrod data 959adfc5217SJeff Kirsher * 960adfc5217SJeff Kirsher * @bp: device handle 961adfc5217SJeff Kirsher * @o: bnx2x_vlan_mac_obj 962adfc5217SJeff Kirsher * @elem: bnx2x_exeq_elem 963adfc5217SJeff Kirsher * @rule_idx: rule_idx 964adfc5217SJeff Kirsher * @cam_offset: cam_offset 965adfc5217SJeff Kirsher */ 966adfc5217SJeff Kirsher static void bnx2x_set_one_mac_e1x(struct bnx2x *bp, 967adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *o, 968adfc5217SJeff Kirsher struct bnx2x_exeq_elem *elem, int rule_idx, 969adfc5217SJeff Kirsher int cam_offset) 970adfc5217SJeff Kirsher { 971adfc5217SJeff Kirsher struct bnx2x_raw_obj *raw = &o->raw; 972adfc5217SJeff Kirsher struct mac_configuration_cmd *config = 973adfc5217SJeff Kirsher (struct mac_configuration_cmd *)(raw->rdata); 97416a5fd92SYuval Mintz /* 57710 and 57711 do not support MOVE command, 975adfc5217SJeff Kirsher * so it's either ADD or DEL 976adfc5217SJeff Kirsher */ 977adfc5217SJeff Kirsher bool add = (elem->cmd_data.vlan_mac.cmd == BNX2X_VLAN_MAC_ADD) ? 978adfc5217SJeff Kirsher true : false; 979adfc5217SJeff Kirsher 980adfc5217SJeff Kirsher /* Reset the ramrod data buffer */ 981adfc5217SJeff Kirsher memset(config, 0, sizeof(*config)); 982adfc5217SJeff Kirsher 98333ac338cSYuval Mintz bnx2x_vlan_mac_set_rdata_e1x(bp, o, raw->state, 984adfc5217SJeff Kirsher cam_offset, add, 985adfc5217SJeff Kirsher elem->cmd_data.vlan_mac.u.mac.mac, 0, 986adfc5217SJeff Kirsher ETH_VLAN_FILTER_ANY_VLAN, config); 987adfc5217SJeff Kirsher } 988adfc5217SJeff Kirsher 989adfc5217SJeff Kirsher static void bnx2x_set_one_vlan_e2(struct bnx2x *bp, 990adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *o, 991adfc5217SJeff Kirsher struct bnx2x_exeq_elem *elem, int rule_idx, 992adfc5217SJeff Kirsher int cam_offset) 993adfc5217SJeff Kirsher { 994adfc5217SJeff Kirsher struct bnx2x_raw_obj *raw = &o->raw; 995adfc5217SJeff Kirsher struct eth_classify_rules_ramrod_data *data = 996adfc5217SJeff Kirsher (struct eth_classify_rules_ramrod_data *)(raw->rdata); 997adfc5217SJeff Kirsher int rule_cnt = rule_idx + 1; 998adfc5217SJeff Kirsher union eth_classify_rule_cmd *rule_entry = &data->rules[rule_idx]; 99986564c3fSYuval Mintz enum bnx2x_vlan_mac_cmd cmd = elem->cmd_data.vlan_mac.cmd; 1000adfc5217SJeff Kirsher bool add = (cmd == BNX2X_VLAN_MAC_ADD) ? true : false; 1001adfc5217SJeff Kirsher u16 vlan = elem->cmd_data.vlan_mac.u.vlan.vlan; 1002adfc5217SJeff Kirsher 1003adfc5217SJeff Kirsher /* Reset the ramrod data buffer for the first rule */ 1004adfc5217SJeff Kirsher if (rule_idx == 0) 1005adfc5217SJeff Kirsher memset(data, 0, sizeof(*data)); 1006adfc5217SJeff Kirsher 1007adfc5217SJeff Kirsher /* Set a rule header */ 1008adfc5217SJeff Kirsher bnx2x_vlan_mac_set_cmd_hdr_e2(bp, o, add, CLASSIFY_RULE_OPCODE_VLAN, 1009adfc5217SJeff Kirsher &rule_entry->vlan.header); 1010adfc5217SJeff Kirsher 1011adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "About to %s VLAN %d\n", (add ? "add" : "delete"), 1012adfc5217SJeff Kirsher vlan); 1013adfc5217SJeff Kirsher 1014adfc5217SJeff Kirsher /* Set a VLAN itself */ 1015adfc5217SJeff Kirsher rule_entry->vlan.vlan = cpu_to_le16(vlan); 1016adfc5217SJeff Kirsher 1017adfc5217SJeff Kirsher /* MOVE: Add a rule that will add this MAC to the target Queue */ 1018adfc5217SJeff Kirsher if (cmd == BNX2X_VLAN_MAC_MOVE) { 1019adfc5217SJeff Kirsher rule_entry++; 1020adfc5217SJeff Kirsher rule_cnt++; 1021adfc5217SJeff Kirsher 1022adfc5217SJeff Kirsher /* Setup ramrod data */ 1023adfc5217SJeff Kirsher bnx2x_vlan_mac_set_cmd_hdr_e2(bp, 1024adfc5217SJeff Kirsher elem->cmd_data.vlan_mac.target_obj, 1025adfc5217SJeff Kirsher true, CLASSIFY_RULE_OPCODE_VLAN, 1026adfc5217SJeff Kirsher &rule_entry->vlan.header); 1027adfc5217SJeff Kirsher 1028adfc5217SJeff Kirsher /* Set a VLAN itself */ 1029adfc5217SJeff Kirsher rule_entry->vlan.vlan = cpu_to_le16(vlan); 1030adfc5217SJeff Kirsher } 1031adfc5217SJeff Kirsher 1032adfc5217SJeff Kirsher /* Set the ramrod data header */ 1033adfc5217SJeff Kirsher /* TODO: take this to the higher level in order to prevent multiple 1034adfc5217SJeff Kirsher writing */ 1035adfc5217SJeff Kirsher bnx2x_vlan_mac_set_rdata_hdr_e2(raw->cid, raw->state, &data->header, 1036adfc5217SJeff Kirsher rule_cnt); 1037adfc5217SJeff Kirsher } 1038adfc5217SJeff Kirsher 1039adfc5217SJeff Kirsher /** 1040adfc5217SJeff Kirsher * bnx2x_vlan_mac_restore - reconfigure next MAC/VLAN/VLAN-MAC element 1041adfc5217SJeff Kirsher * 1042adfc5217SJeff Kirsher * @bp: device handle 1043adfc5217SJeff Kirsher * @p: command parameters 104416a5fd92SYuval Mintz * @ppos: pointer to the cookie 1045adfc5217SJeff Kirsher * 1046adfc5217SJeff Kirsher * reconfigure next MAC/VLAN/VLAN-MAC element from the 1047adfc5217SJeff Kirsher * previously configured elements list. 1048adfc5217SJeff Kirsher * 1049adfc5217SJeff Kirsher * from command parameters only RAMROD_COMP_WAIT bit in ramrod_flags is taken 1050adfc5217SJeff Kirsher * into an account 1051adfc5217SJeff Kirsher * 105216a5fd92SYuval Mintz * pointer to the cookie - that should be given back in the next call to make 1053adfc5217SJeff Kirsher * function handle the next element. If *ppos is set to NULL it will restart the 1054adfc5217SJeff Kirsher * iterator. If returned *ppos == NULL this means that the last element has been 1055adfc5217SJeff Kirsher * handled. 1056adfc5217SJeff Kirsher * 1057adfc5217SJeff Kirsher */ 1058adfc5217SJeff Kirsher static int bnx2x_vlan_mac_restore(struct bnx2x *bp, 1059adfc5217SJeff Kirsher struct bnx2x_vlan_mac_ramrod_params *p, 1060adfc5217SJeff Kirsher struct bnx2x_vlan_mac_registry_elem **ppos) 1061adfc5217SJeff Kirsher { 1062adfc5217SJeff Kirsher struct bnx2x_vlan_mac_registry_elem *pos; 1063adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *o = p->vlan_mac_obj; 1064adfc5217SJeff Kirsher 1065adfc5217SJeff Kirsher /* If list is empty - there is nothing to do here */ 1066adfc5217SJeff Kirsher if (list_empty(&o->head)) { 1067adfc5217SJeff Kirsher *ppos = NULL; 1068adfc5217SJeff Kirsher return 0; 1069adfc5217SJeff Kirsher } 1070adfc5217SJeff Kirsher 1071adfc5217SJeff Kirsher /* make a step... */ 1072adfc5217SJeff Kirsher if (*ppos == NULL) 1073adfc5217SJeff Kirsher *ppos = list_first_entry(&o->head, 1074adfc5217SJeff Kirsher struct bnx2x_vlan_mac_registry_elem, 1075adfc5217SJeff Kirsher link); 1076adfc5217SJeff Kirsher else 1077adfc5217SJeff Kirsher *ppos = list_next_entry(*ppos, link); 1078adfc5217SJeff Kirsher 1079adfc5217SJeff Kirsher pos = *ppos; 1080adfc5217SJeff Kirsher 1081adfc5217SJeff Kirsher /* If it's the last step - return NULL */ 1082adfc5217SJeff Kirsher if (list_is_last(&pos->link, &o->head)) 1083adfc5217SJeff Kirsher *ppos = NULL; 1084adfc5217SJeff Kirsher 1085adfc5217SJeff Kirsher /* Prepare a 'user_req' */ 1086adfc5217SJeff Kirsher memcpy(&p->user_req.u, &pos->u, sizeof(pos->u)); 1087adfc5217SJeff Kirsher 1088adfc5217SJeff Kirsher /* Set the command */ 1089adfc5217SJeff Kirsher p->user_req.cmd = BNX2X_VLAN_MAC_ADD; 1090adfc5217SJeff Kirsher 1091adfc5217SJeff Kirsher /* Set vlan_mac_flags */ 1092adfc5217SJeff Kirsher p->user_req.vlan_mac_flags = pos->vlan_mac_flags; 1093adfc5217SJeff Kirsher 1094adfc5217SJeff Kirsher /* Set a restore bit */ 1095adfc5217SJeff Kirsher __set_bit(RAMROD_RESTORE, &p->ramrod_flags); 1096adfc5217SJeff Kirsher 1097adfc5217SJeff Kirsher return bnx2x_config_vlan_mac(bp, p); 1098adfc5217SJeff Kirsher } 1099adfc5217SJeff Kirsher 110016a5fd92SYuval Mintz /* bnx2x_exeq_get_mac/bnx2x_exeq_get_vlan/bnx2x_exeq_get_vlan_mac return a 1101adfc5217SJeff Kirsher * pointer to an element with a specific criteria and NULL if such an element 1102adfc5217SJeff Kirsher * hasn't been found. 1103adfc5217SJeff Kirsher */ 1104adfc5217SJeff Kirsher static struct bnx2x_exeq_elem *bnx2x_exeq_get_mac( 1105adfc5217SJeff Kirsher struct bnx2x_exe_queue_obj *o, 1106adfc5217SJeff Kirsher struct bnx2x_exeq_elem *elem) 1107adfc5217SJeff Kirsher { 1108adfc5217SJeff Kirsher struct bnx2x_exeq_elem *pos; 1109adfc5217SJeff Kirsher struct bnx2x_mac_ramrod_data *data = &elem->cmd_data.vlan_mac.u.mac; 1110adfc5217SJeff Kirsher 1111adfc5217SJeff Kirsher /* Check pending for execution commands */ 1112adfc5217SJeff Kirsher list_for_each_entry(pos, &o->exe_queue, link) 1113adfc5217SJeff Kirsher if (!memcmp(&pos->cmd_data.vlan_mac.u.mac, data, 1114adfc5217SJeff Kirsher sizeof(*data)) && 1115adfc5217SJeff Kirsher (pos->cmd_data.vlan_mac.cmd == elem->cmd_data.vlan_mac.cmd)) 1116adfc5217SJeff Kirsher return pos; 1117adfc5217SJeff Kirsher 1118adfc5217SJeff Kirsher return NULL; 1119adfc5217SJeff Kirsher } 1120adfc5217SJeff Kirsher 1121adfc5217SJeff Kirsher static struct bnx2x_exeq_elem *bnx2x_exeq_get_vlan( 1122adfc5217SJeff Kirsher struct bnx2x_exe_queue_obj *o, 1123adfc5217SJeff Kirsher struct bnx2x_exeq_elem *elem) 1124adfc5217SJeff Kirsher { 1125adfc5217SJeff Kirsher struct bnx2x_exeq_elem *pos; 1126adfc5217SJeff Kirsher struct bnx2x_vlan_ramrod_data *data = &elem->cmd_data.vlan_mac.u.vlan; 1127adfc5217SJeff Kirsher 1128adfc5217SJeff Kirsher /* Check pending for execution commands */ 1129adfc5217SJeff Kirsher list_for_each_entry(pos, &o->exe_queue, link) 1130adfc5217SJeff Kirsher if (!memcmp(&pos->cmd_data.vlan_mac.u.vlan, data, 1131adfc5217SJeff Kirsher sizeof(*data)) && 1132adfc5217SJeff Kirsher (pos->cmd_data.vlan_mac.cmd == elem->cmd_data.vlan_mac.cmd)) 1133adfc5217SJeff Kirsher return pos; 1134adfc5217SJeff Kirsher 1135adfc5217SJeff Kirsher return NULL; 1136adfc5217SJeff Kirsher } 1137adfc5217SJeff Kirsher 1138adfc5217SJeff Kirsher /** 1139adfc5217SJeff Kirsher * bnx2x_validate_vlan_mac_add - check if an ADD command can be executed 1140adfc5217SJeff Kirsher * 1141adfc5217SJeff Kirsher * @bp: device handle 1142adfc5217SJeff Kirsher * @qo: bnx2x_qable_obj 1143adfc5217SJeff Kirsher * @elem: bnx2x_exeq_elem 1144adfc5217SJeff Kirsher * 1145adfc5217SJeff Kirsher * Checks that the requested configuration can be added. If yes and if 1146adfc5217SJeff Kirsher * requested, consume CAM credit. 1147adfc5217SJeff Kirsher * 1148adfc5217SJeff Kirsher * The 'validate' is run after the 'optimize'. 1149adfc5217SJeff Kirsher * 1150adfc5217SJeff Kirsher */ 1151adfc5217SJeff Kirsher static inline int bnx2x_validate_vlan_mac_add(struct bnx2x *bp, 1152adfc5217SJeff Kirsher union bnx2x_qable_obj *qo, 1153adfc5217SJeff Kirsher struct bnx2x_exeq_elem *elem) 1154adfc5217SJeff Kirsher { 1155adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *o = &qo->vlan_mac; 1156adfc5217SJeff Kirsher struct bnx2x_exe_queue_obj *exeq = &o->exe_queue; 1157adfc5217SJeff Kirsher int rc; 1158adfc5217SJeff Kirsher 1159adfc5217SJeff Kirsher /* Check the registry */ 116051c1a580SMerav Sicron rc = o->check_add(bp, o, &elem->cmd_data.vlan_mac.u); 1161adfc5217SJeff Kirsher if (rc) { 116251c1a580SMerav Sicron DP(BNX2X_MSG_SP, "ADD command is not allowed considering current registry state.\n"); 1163adfc5217SJeff Kirsher return rc; 1164adfc5217SJeff Kirsher } 1165adfc5217SJeff Kirsher 116616a5fd92SYuval Mintz /* Check if there is a pending ADD command for this 1167adfc5217SJeff Kirsher * MAC/VLAN/VLAN-MAC. Return an error if there is. 1168adfc5217SJeff Kirsher */ 1169adfc5217SJeff Kirsher if (exeq->get(exeq, elem)) { 1170adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "There is a pending ADD command already\n"); 1171adfc5217SJeff Kirsher return -EEXIST; 1172adfc5217SJeff Kirsher } 1173adfc5217SJeff Kirsher 117416a5fd92SYuval Mintz /* TODO: Check the pending MOVE from other objects where this 1175adfc5217SJeff Kirsher * object is a destination object. 1176adfc5217SJeff Kirsher */ 1177adfc5217SJeff Kirsher 1178adfc5217SJeff Kirsher /* Consume the credit if not requested not to */ 1179adfc5217SJeff Kirsher if (!(test_bit(BNX2X_DONT_CONSUME_CAM_CREDIT, 1180adfc5217SJeff Kirsher &elem->cmd_data.vlan_mac.vlan_mac_flags) || 1181adfc5217SJeff Kirsher o->get_credit(o))) 1182adfc5217SJeff Kirsher return -EINVAL; 1183adfc5217SJeff Kirsher 1184adfc5217SJeff Kirsher return 0; 1185adfc5217SJeff Kirsher } 1186adfc5217SJeff Kirsher 1187adfc5217SJeff Kirsher /** 1188adfc5217SJeff Kirsher * bnx2x_validate_vlan_mac_del - check if the DEL command can be executed 1189adfc5217SJeff Kirsher * 1190adfc5217SJeff Kirsher * @bp: device handle 1191adfc5217SJeff Kirsher * @qo: quable object to check 1192adfc5217SJeff Kirsher * @elem: element that needs to be deleted 1193adfc5217SJeff Kirsher * 1194adfc5217SJeff Kirsher * Checks that the requested configuration can be deleted. If yes and if 1195adfc5217SJeff Kirsher * requested, returns a CAM credit. 1196adfc5217SJeff Kirsher * 1197adfc5217SJeff Kirsher * The 'validate' is run after the 'optimize'. 1198adfc5217SJeff Kirsher */ 1199adfc5217SJeff Kirsher static inline int bnx2x_validate_vlan_mac_del(struct bnx2x *bp, 1200adfc5217SJeff Kirsher union bnx2x_qable_obj *qo, 1201adfc5217SJeff Kirsher struct bnx2x_exeq_elem *elem) 1202adfc5217SJeff Kirsher { 1203adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *o = &qo->vlan_mac; 1204adfc5217SJeff Kirsher struct bnx2x_vlan_mac_registry_elem *pos; 1205adfc5217SJeff Kirsher struct bnx2x_exe_queue_obj *exeq = &o->exe_queue; 1206adfc5217SJeff Kirsher struct bnx2x_exeq_elem query_elem; 1207adfc5217SJeff Kirsher 1208adfc5217SJeff Kirsher /* If this classification can not be deleted (doesn't exist) 1209adfc5217SJeff Kirsher * - return a BNX2X_EXIST. 1210adfc5217SJeff Kirsher */ 121151c1a580SMerav Sicron pos = o->check_del(bp, o, &elem->cmd_data.vlan_mac.u); 1212adfc5217SJeff Kirsher if (!pos) { 121351c1a580SMerav Sicron DP(BNX2X_MSG_SP, "DEL command is not allowed considering current registry state\n"); 1214adfc5217SJeff Kirsher return -EEXIST; 1215adfc5217SJeff Kirsher } 1216adfc5217SJeff Kirsher 121716a5fd92SYuval Mintz /* Check if there are pending DEL or MOVE commands for this 1218adfc5217SJeff Kirsher * MAC/VLAN/VLAN-MAC. Return an error if so. 1219adfc5217SJeff Kirsher */ 1220adfc5217SJeff Kirsher memcpy(&query_elem, elem, sizeof(query_elem)); 1221adfc5217SJeff Kirsher 1222adfc5217SJeff Kirsher /* Check for MOVE commands */ 1223adfc5217SJeff Kirsher query_elem.cmd_data.vlan_mac.cmd = BNX2X_VLAN_MAC_MOVE; 1224adfc5217SJeff Kirsher if (exeq->get(exeq, &query_elem)) { 1225adfc5217SJeff Kirsher BNX2X_ERR("There is a pending MOVE command already\n"); 1226adfc5217SJeff Kirsher return -EINVAL; 1227adfc5217SJeff Kirsher } 1228adfc5217SJeff Kirsher 1229adfc5217SJeff Kirsher /* Check for DEL commands */ 1230adfc5217SJeff Kirsher if (exeq->get(exeq, elem)) { 1231adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "There is a pending DEL command already\n"); 1232adfc5217SJeff Kirsher return -EEXIST; 1233adfc5217SJeff Kirsher } 1234adfc5217SJeff Kirsher 1235adfc5217SJeff Kirsher /* Return the credit to the credit pool if not requested not to */ 1236adfc5217SJeff Kirsher if (!(test_bit(BNX2X_DONT_CONSUME_CAM_CREDIT, 1237adfc5217SJeff Kirsher &elem->cmd_data.vlan_mac.vlan_mac_flags) || 1238adfc5217SJeff Kirsher o->put_credit(o))) { 1239adfc5217SJeff Kirsher BNX2X_ERR("Failed to return a credit\n"); 1240adfc5217SJeff Kirsher return -EINVAL; 1241adfc5217SJeff Kirsher } 1242adfc5217SJeff Kirsher 1243adfc5217SJeff Kirsher return 0; 1244adfc5217SJeff Kirsher } 1245adfc5217SJeff Kirsher 1246adfc5217SJeff Kirsher /** 1247adfc5217SJeff Kirsher * bnx2x_validate_vlan_mac_move - check if the MOVE command can be executed 1248adfc5217SJeff Kirsher * 1249adfc5217SJeff Kirsher * @bp: device handle 1250adfc5217SJeff Kirsher * @qo: quable object to check (source) 1251adfc5217SJeff Kirsher * @elem: element that needs to be moved 1252adfc5217SJeff Kirsher * 1253adfc5217SJeff Kirsher * Checks that the requested configuration can be moved. If yes and if 1254adfc5217SJeff Kirsher * requested, returns a CAM credit. 1255adfc5217SJeff Kirsher * 1256adfc5217SJeff Kirsher * The 'validate' is run after the 'optimize'. 1257adfc5217SJeff Kirsher */ 1258adfc5217SJeff Kirsher static inline int bnx2x_validate_vlan_mac_move(struct bnx2x *bp, 1259adfc5217SJeff Kirsher union bnx2x_qable_obj *qo, 1260adfc5217SJeff Kirsher struct bnx2x_exeq_elem *elem) 1261adfc5217SJeff Kirsher { 1262adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *src_o = &qo->vlan_mac; 1263adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *dest_o = elem->cmd_data.vlan_mac.target_obj; 1264adfc5217SJeff Kirsher struct bnx2x_exeq_elem query_elem; 1265adfc5217SJeff Kirsher struct bnx2x_exe_queue_obj *src_exeq = &src_o->exe_queue; 1266adfc5217SJeff Kirsher struct bnx2x_exe_queue_obj *dest_exeq = &dest_o->exe_queue; 1267adfc5217SJeff Kirsher 126816a5fd92SYuval Mintz /* Check if we can perform this operation based on the current registry 1269adfc5217SJeff Kirsher * state. 1270adfc5217SJeff Kirsher */ 127151c1a580SMerav Sicron if (!src_o->check_move(bp, src_o, dest_o, 127251c1a580SMerav Sicron &elem->cmd_data.vlan_mac.u)) { 127351c1a580SMerav Sicron DP(BNX2X_MSG_SP, "MOVE command is not allowed considering current registry state\n"); 1274adfc5217SJeff Kirsher return -EINVAL; 1275adfc5217SJeff Kirsher } 1276adfc5217SJeff Kirsher 127716a5fd92SYuval Mintz /* Check if there is an already pending DEL or MOVE command for the 1278adfc5217SJeff Kirsher * source object or ADD command for a destination object. Return an 1279adfc5217SJeff Kirsher * error if so. 1280adfc5217SJeff Kirsher */ 1281adfc5217SJeff Kirsher memcpy(&query_elem, elem, sizeof(query_elem)); 1282adfc5217SJeff Kirsher 1283adfc5217SJeff Kirsher /* Check DEL on source */ 1284adfc5217SJeff Kirsher query_elem.cmd_data.vlan_mac.cmd = BNX2X_VLAN_MAC_DEL; 1285adfc5217SJeff Kirsher if (src_exeq->get(src_exeq, &query_elem)) { 128651c1a580SMerav Sicron BNX2X_ERR("There is a pending DEL command on the source queue already\n"); 1287adfc5217SJeff Kirsher return -EINVAL; 1288adfc5217SJeff Kirsher } 1289adfc5217SJeff Kirsher 1290adfc5217SJeff Kirsher /* Check MOVE on source */ 1291adfc5217SJeff Kirsher if (src_exeq->get(src_exeq, elem)) { 1292adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "There is a pending MOVE command already\n"); 1293adfc5217SJeff Kirsher return -EEXIST; 1294adfc5217SJeff Kirsher } 1295adfc5217SJeff Kirsher 1296adfc5217SJeff Kirsher /* Check ADD on destination */ 1297adfc5217SJeff Kirsher query_elem.cmd_data.vlan_mac.cmd = BNX2X_VLAN_MAC_ADD; 1298adfc5217SJeff Kirsher if (dest_exeq->get(dest_exeq, &query_elem)) { 129951c1a580SMerav Sicron BNX2X_ERR("There is a pending ADD command on the destination queue already\n"); 1300adfc5217SJeff Kirsher return -EINVAL; 1301adfc5217SJeff Kirsher } 1302adfc5217SJeff Kirsher 1303adfc5217SJeff Kirsher /* Consume the credit if not requested not to */ 1304adfc5217SJeff Kirsher if (!(test_bit(BNX2X_DONT_CONSUME_CAM_CREDIT_DEST, 1305adfc5217SJeff Kirsher &elem->cmd_data.vlan_mac.vlan_mac_flags) || 1306adfc5217SJeff Kirsher dest_o->get_credit(dest_o))) 1307adfc5217SJeff Kirsher return -EINVAL; 1308adfc5217SJeff Kirsher 1309adfc5217SJeff Kirsher if (!(test_bit(BNX2X_DONT_CONSUME_CAM_CREDIT, 1310adfc5217SJeff Kirsher &elem->cmd_data.vlan_mac.vlan_mac_flags) || 1311adfc5217SJeff Kirsher src_o->put_credit(src_o))) { 1312adfc5217SJeff Kirsher /* return the credit taken from dest... */ 1313adfc5217SJeff Kirsher dest_o->put_credit(dest_o); 1314adfc5217SJeff Kirsher return -EINVAL; 1315adfc5217SJeff Kirsher } 1316adfc5217SJeff Kirsher 1317adfc5217SJeff Kirsher return 0; 1318adfc5217SJeff Kirsher } 1319adfc5217SJeff Kirsher 1320adfc5217SJeff Kirsher static int bnx2x_validate_vlan_mac(struct bnx2x *bp, 1321adfc5217SJeff Kirsher union bnx2x_qable_obj *qo, 1322adfc5217SJeff Kirsher struct bnx2x_exeq_elem *elem) 1323adfc5217SJeff Kirsher { 1324adfc5217SJeff Kirsher switch (elem->cmd_data.vlan_mac.cmd) { 1325adfc5217SJeff Kirsher case BNX2X_VLAN_MAC_ADD: 1326adfc5217SJeff Kirsher return bnx2x_validate_vlan_mac_add(bp, qo, elem); 1327adfc5217SJeff Kirsher case BNX2X_VLAN_MAC_DEL: 1328adfc5217SJeff Kirsher return bnx2x_validate_vlan_mac_del(bp, qo, elem); 1329adfc5217SJeff Kirsher case BNX2X_VLAN_MAC_MOVE: 1330adfc5217SJeff Kirsher return bnx2x_validate_vlan_mac_move(bp, qo, elem); 1331adfc5217SJeff Kirsher default: 1332adfc5217SJeff Kirsher return -EINVAL; 1333adfc5217SJeff Kirsher } 1334adfc5217SJeff Kirsher } 1335adfc5217SJeff Kirsher 1336460a25cdSYuval Mintz static int bnx2x_remove_vlan_mac(struct bnx2x *bp, 1337460a25cdSYuval Mintz union bnx2x_qable_obj *qo, 1338460a25cdSYuval Mintz struct bnx2x_exeq_elem *elem) 1339460a25cdSYuval Mintz { 1340460a25cdSYuval Mintz int rc = 0; 1341460a25cdSYuval Mintz 1342460a25cdSYuval Mintz /* If consumption wasn't required, nothing to do */ 1343460a25cdSYuval Mintz if (test_bit(BNX2X_DONT_CONSUME_CAM_CREDIT, 1344460a25cdSYuval Mintz &elem->cmd_data.vlan_mac.vlan_mac_flags)) 1345460a25cdSYuval Mintz return 0; 1346460a25cdSYuval Mintz 1347460a25cdSYuval Mintz switch (elem->cmd_data.vlan_mac.cmd) { 1348460a25cdSYuval Mintz case BNX2X_VLAN_MAC_ADD: 1349460a25cdSYuval Mintz case BNX2X_VLAN_MAC_MOVE: 1350460a25cdSYuval Mintz rc = qo->vlan_mac.put_credit(&qo->vlan_mac); 1351460a25cdSYuval Mintz break; 1352460a25cdSYuval Mintz case BNX2X_VLAN_MAC_DEL: 1353460a25cdSYuval Mintz rc = qo->vlan_mac.get_credit(&qo->vlan_mac); 1354460a25cdSYuval Mintz break; 1355460a25cdSYuval Mintz default: 1356460a25cdSYuval Mintz return -EINVAL; 1357460a25cdSYuval Mintz } 1358460a25cdSYuval Mintz 1359460a25cdSYuval Mintz if (rc != true) 1360460a25cdSYuval Mintz return -EINVAL; 1361460a25cdSYuval Mintz 1362460a25cdSYuval Mintz return 0; 1363460a25cdSYuval Mintz } 1364460a25cdSYuval Mintz 1365adfc5217SJeff Kirsher /** 136616a5fd92SYuval Mintz * bnx2x_wait_vlan_mac - passively wait for 5 seconds until all work completes. 1367adfc5217SJeff Kirsher * 1368adfc5217SJeff Kirsher * @bp: device handle 1369adfc5217SJeff Kirsher * @o: bnx2x_vlan_mac_obj 1370adfc5217SJeff Kirsher * 1371adfc5217SJeff Kirsher */ 1372adfc5217SJeff Kirsher static int bnx2x_wait_vlan_mac(struct bnx2x *bp, 1373adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *o) 1374adfc5217SJeff Kirsher { 1375adfc5217SJeff Kirsher int cnt = 5000, rc; 1376adfc5217SJeff Kirsher struct bnx2x_exe_queue_obj *exeq = &o->exe_queue; 1377adfc5217SJeff Kirsher struct bnx2x_raw_obj *raw = &o->raw; 1378adfc5217SJeff Kirsher 1379adfc5217SJeff Kirsher while (cnt--) { 1380adfc5217SJeff Kirsher /* Wait for the current command to complete */ 1381adfc5217SJeff Kirsher rc = raw->wait_comp(bp, raw); 1382adfc5217SJeff Kirsher if (rc) 1383adfc5217SJeff Kirsher return rc; 1384adfc5217SJeff Kirsher 1385adfc5217SJeff Kirsher /* Wait until there are no pending commands */ 1386adfc5217SJeff Kirsher if (!bnx2x_exe_queue_empty(exeq)) 13870926d499SYuval Mintz usleep_range(1000, 2000); 1388adfc5217SJeff Kirsher else 1389adfc5217SJeff Kirsher return 0; 1390adfc5217SJeff Kirsher } 1391adfc5217SJeff Kirsher 1392adfc5217SJeff Kirsher return -EBUSY; 1393adfc5217SJeff Kirsher } 1394adfc5217SJeff Kirsher 13958b09be5fSYuval Mintz static int __bnx2x_vlan_mac_execute_step(struct bnx2x *bp, 13968b09be5fSYuval Mintz struct bnx2x_vlan_mac_obj *o, 13978b09be5fSYuval Mintz unsigned long *ramrod_flags) 13988b09be5fSYuval Mintz { 13998b09be5fSYuval Mintz int rc = 0; 14008b09be5fSYuval Mintz 14018b09be5fSYuval Mintz spin_lock_bh(&o->exe_queue.lock); 14028b09be5fSYuval Mintz 14038b09be5fSYuval Mintz DP(BNX2X_MSG_SP, "vlan_mac_execute_step - trying to take writer lock\n"); 14048b09be5fSYuval Mintz rc = __bnx2x_vlan_mac_h_write_trylock(bp, o); 14058b09be5fSYuval Mintz 14068b09be5fSYuval Mintz if (rc != 0) { 14078b09be5fSYuval Mintz __bnx2x_vlan_mac_h_pend(bp, o, *ramrod_flags); 14088b09be5fSYuval Mintz 14098b09be5fSYuval Mintz /* Calling function should not diffrentiate between this case 14108b09be5fSYuval Mintz * and the case in which there is already a pending ramrod 14118b09be5fSYuval Mintz */ 14128b09be5fSYuval Mintz rc = 1; 14138b09be5fSYuval Mintz } else { 14148b09be5fSYuval Mintz rc = bnx2x_exe_queue_step(bp, &o->exe_queue, ramrod_flags); 14158b09be5fSYuval Mintz } 14168b09be5fSYuval Mintz spin_unlock_bh(&o->exe_queue.lock); 14178b09be5fSYuval Mintz 14188b09be5fSYuval Mintz return rc; 14198b09be5fSYuval Mintz } 14208b09be5fSYuval Mintz 1421adfc5217SJeff Kirsher /** 1422adfc5217SJeff Kirsher * bnx2x_complete_vlan_mac - complete one VLAN-MAC ramrod 1423adfc5217SJeff Kirsher * 1424adfc5217SJeff Kirsher * @bp: device handle 1425adfc5217SJeff Kirsher * @o: bnx2x_vlan_mac_obj 1426adfc5217SJeff Kirsher * @cqe: 1427adfc5217SJeff Kirsher * @cont: if true schedule next execution chunk 1428adfc5217SJeff Kirsher * 1429adfc5217SJeff Kirsher */ 1430adfc5217SJeff Kirsher static int bnx2x_complete_vlan_mac(struct bnx2x *bp, 1431adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *o, 1432adfc5217SJeff Kirsher union event_ring_elem *cqe, 1433adfc5217SJeff Kirsher unsigned long *ramrod_flags) 1434adfc5217SJeff Kirsher { 1435adfc5217SJeff Kirsher struct bnx2x_raw_obj *r = &o->raw; 1436adfc5217SJeff Kirsher int rc; 1437adfc5217SJeff Kirsher 14388b09be5fSYuval Mintz /* Clearing the pending list & raw state should be made 14398b09be5fSYuval Mintz * atomically (as execution flow assumes they represent the same). 14408b09be5fSYuval Mintz */ 14418b09be5fSYuval Mintz spin_lock_bh(&o->exe_queue.lock); 14428b09be5fSYuval Mintz 1443adfc5217SJeff Kirsher /* Reset pending list */ 14448b09be5fSYuval Mintz __bnx2x_exe_queue_reset_pending(bp, &o->exe_queue); 1445adfc5217SJeff Kirsher 1446adfc5217SJeff Kirsher /* Clear pending */ 1447adfc5217SJeff Kirsher r->clear_pending(r); 1448adfc5217SJeff Kirsher 14498b09be5fSYuval Mintz spin_unlock_bh(&o->exe_queue.lock); 14508b09be5fSYuval Mintz 1451adfc5217SJeff Kirsher /* If ramrod failed this is most likely a SW bug */ 1452adfc5217SJeff Kirsher if (cqe->message.error) 1453adfc5217SJeff Kirsher return -EINVAL; 1454adfc5217SJeff Kirsher 14552de67439SYuval Mintz /* Run the next bulk of pending commands if requested */ 1456adfc5217SJeff Kirsher if (test_bit(RAMROD_CONT, ramrod_flags)) { 14578b09be5fSYuval Mintz rc = __bnx2x_vlan_mac_execute_step(bp, o, ramrod_flags); 14588b09be5fSYuval Mintz 1459adfc5217SJeff Kirsher if (rc < 0) 1460adfc5217SJeff Kirsher return rc; 1461adfc5217SJeff Kirsher } 1462adfc5217SJeff Kirsher 1463adfc5217SJeff Kirsher /* If there is more work to do return PENDING */ 1464adfc5217SJeff Kirsher if (!bnx2x_exe_queue_empty(&o->exe_queue)) 1465adfc5217SJeff Kirsher return 1; 1466adfc5217SJeff Kirsher 1467adfc5217SJeff Kirsher return 0; 1468adfc5217SJeff Kirsher } 1469adfc5217SJeff Kirsher 1470adfc5217SJeff Kirsher /** 1471adfc5217SJeff Kirsher * bnx2x_optimize_vlan_mac - optimize ADD and DEL commands. 1472adfc5217SJeff Kirsher * 1473adfc5217SJeff Kirsher * @bp: device handle 1474adfc5217SJeff Kirsher * @o: bnx2x_qable_obj 1475adfc5217SJeff Kirsher * @elem: bnx2x_exeq_elem 1476adfc5217SJeff Kirsher */ 1477adfc5217SJeff Kirsher static int bnx2x_optimize_vlan_mac(struct bnx2x *bp, 1478adfc5217SJeff Kirsher union bnx2x_qable_obj *qo, 1479adfc5217SJeff Kirsher struct bnx2x_exeq_elem *elem) 1480adfc5217SJeff Kirsher { 1481adfc5217SJeff Kirsher struct bnx2x_exeq_elem query, *pos; 1482adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *o = &qo->vlan_mac; 1483adfc5217SJeff Kirsher struct bnx2x_exe_queue_obj *exeq = &o->exe_queue; 1484adfc5217SJeff Kirsher 1485adfc5217SJeff Kirsher memcpy(&query, elem, sizeof(query)); 1486adfc5217SJeff Kirsher 1487adfc5217SJeff Kirsher switch (elem->cmd_data.vlan_mac.cmd) { 1488adfc5217SJeff Kirsher case BNX2X_VLAN_MAC_ADD: 1489adfc5217SJeff Kirsher query.cmd_data.vlan_mac.cmd = BNX2X_VLAN_MAC_DEL; 1490adfc5217SJeff Kirsher break; 1491adfc5217SJeff Kirsher case BNX2X_VLAN_MAC_DEL: 1492adfc5217SJeff Kirsher query.cmd_data.vlan_mac.cmd = BNX2X_VLAN_MAC_ADD; 1493adfc5217SJeff Kirsher break; 1494adfc5217SJeff Kirsher default: 1495adfc5217SJeff Kirsher /* Don't handle anything other than ADD or DEL */ 1496adfc5217SJeff Kirsher return 0; 1497adfc5217SJeff Kirsher } 1498adfc5217SJeff Kirsher 1499adfc5217SJeff Kirsher /* If we found the appropriate element - delete it */ 1500adfc5217SJeff Kirsher pos = exeq->get(exeq, &query); 1501adfc5217SJeff Kirsher if (pos) { 1502adfc5217SJeff Kirsher 1503adfc5217SJeff Kirsher /* Return the credit of the optimized command */ 1504adfc5217SJeff Kirsher if (!test_bit(BNX2X_DONT_CONSUME_CAM_CREDIT, 1505adfc5217SJeff Kirsher &pos->cmd_data.vlan_mac.vlan_mac_flags)) { 1506adfc5217SJeff Kirsher if ((query.cmd_data.vlan_mac.cmd == 1507adfc5217SJeff Kirsher BNX2X_VLAN_MAC_ADD) && !o->put_credit(o)) { 150851c1a580SMerav Sicron BNX2X_ERR("Failed to return the credit for the optimized ADD command\n"); 1509adfc5217SJeff Kirsher return -EINVAL; 1510adfc5217SJeff Kirsher } else if (!o->get_credit(o)) { /* VLAN_MAC_DEL */ 151151c1a580SMerav Sicron BNX2X_ERR("Failed to recover the credit from the optimized DEL command\n"); 1512adfc5217SJeff Kirsher return -EINVAL; 1513adfc5217SJeff Kirsher } 1514adfc5217SJeff Kirsher } 1515adfc5217SJeff Kirsher 1516adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "Optimizing %s command\n", 1517adfc5217SJeff Kirsher (elem->cmd_data.vlan_mac.cmd == BNX2X_VLAN_MAC_ADD) ? 1518adfc5217SJeff Kirsher "ADD" : "DEL"); 1519adfc5217SJeff Kirsher 1520adfc5217SJeff Kirsher list_del(&pos->link); 1521adfc5217SJeff Kirsher bnx2x_exe_queue_free_elem(bp, pos); 1522adfc5217SJeff Kirsher return 1; 1523adfc5217SJeff Kirsher } 1524adfc5217SJeff Kirsher 1525adfc5217SJeff Kirsher return 0; 1526adfc5217SJeff Kirsher } 1527adfc5217SJeff Kirsher 1528adfc5217SJeff Kirsher /** 1529adfc5217SJeff Kirsher * bnx2x_vlan_mac_get_registry_elem - prepare a registry element 1530adfc5217SJeff Kirsher * 1531adfc5217SJeff Kirsher * @bp: device handle 1532adfc5217SJeff Kirsher * @o: 1533adfc5217SJeff Kirsher * @elem: 1534adfc5217SJeff Kirsher * @restore: 1535adfc5217SJeff Kirsher * @re: 1536adfc5217SJeff Kirsher * 1537adfc5217SJeff Kirsher * prepare a registry element according to the current command request. 1538adfc5217SJeff Kirsher */ 1539adfc5217SJeff Kirsher static inline int bnx2x_vlan_mac_get_registry_elem( 1540adfc5217SJeff Kirsher struct bnx2x *bp, 1541adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *o, 1542adfc5217SJeff Kirsher struct bnx2x_exeq_elem *elem, 1543adfc5217SJeff Kirsher bool restore, 1544adfc5217SJeff Kirsher struct bnx2x_vlan_mac_registry_elem **re) 1545adfc5217SJeff Kirsher { 154686564c3fSYuval Mintz enum bnx2x_vlan_mac_cmd cmd = elem->cmd_data.vlan_mac.cmd; 1547adfc5217SJeff Kirsher struct bnx2x_vlan_mac_registry_elem *reg_elem; 1548adfc5217SJeff Kirsher 1549adfc5217SJeff Kirsher /* Allocate a new registry element if needed. */ 1550adfc5217SJeff Kirsher if (!restore && 1551adfc5217SJeff Kirsher ((cmd == BNX2X_VLAN_MAC_ADD) || (cmd == BNX2X_VLAN_MAC_MOVE))) { 1552adfc5217SJeff Kirsher reg_elem = kzalloc(sizeof(*reg_elem), GFP_ATOMIC); 1553adfc5217SJeff Kirsher if (!reg_elem) 1554adfc5217SJeff Kirsher return -ENOMEM; 1555adfc5217SJeff Kirsher 1556adfc5217SJeff Kirsher /* Get a new CAM offset */ 1557adfc5217SJeff Kirsher if (!o->get_cam_offset(o, ®_elem->cam_offset)) { 155816a5fd92SYuval Mintz /* This shall never happen, because we have checked the 155916a5fd92SYuval Mintz * CAM availability in the 'validate'. 1560adfc5217SJeff Kirsher */ 1561adfc5217SJeff Kirsher WARN_ON(1); 1562adfc5217SJeff Kirsher kfree(reg_elem); 1563adfc5217SJeff Kirsher return -EINVAL; 1564adfc5217SJeff Kirsher } 1565adfc5217SJeff Kirsher 1566adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "Got cam offset %d\n", reg_elem->cam_offset); 1567adfc5217SJeff Kirsher 1568adfc5217SJeff Kirsher /* Set a VLAN-MAC data */ 1569adfc5217SJeff Kirsher memcpy(®_elem->u, &elem->cmd_data.vlan_mac.u, 1570adfc5217SJeff Kirsher sizeof(reg_elem->u)); 1571adfc5217SJeff Kirsher 1572adfc5217SJeff Kirsher /* Copy the flags (needed for DEL and RESTORE flows) */ 1573adfc5217SJeff Kirsher reg_elem->vlan_mac_flags = 1574adfc5217SJeff Kirsher elem->cmd_data.vlan_mac.vlan_mac_flags; 1575adfc5217SJeff Kirsher } else /* DEL, RESTORE */ 157651c1a580SMerav Sicron reg_elem = o->check_del(bp, o, &elem->cmd_data.vlan_mac.u); 1577adfc5217SJeff Kirsher 1578adfc5217SJeff Kirsher *re = reg_elem; 1579adfc5217SJeff Kirsher return 0; 1580adfc5217SJeff Kirsher } 1581adfc5217SJeff Kirsher 1582adfc5217SJeff Kirsher /** 1583adfc5217SJeff Kirsher * bnx2x_execute_vlan_mac - execute vlan mac command 1584adfc5217SJeff Kirsher * 1585adfc5217SJeff Kirsher * @bp: device handle 1586adfc5217SJeff Kirsher * @qo: 1587adfc5217SJeff Kirsher * @exe_chunk: 1588adfc5217SJeff Kirsher * @ramrod_flags: 1589adfc5217SJeff Kirsher * 1590adfc5217SJeff Kirsher * go and send a ramrod! 1591adfc5217SJeff Kirsher */ 1592adfc5217SJeff Kirsher static int bnx2x_execute_vlan_mac(struct bnx2x *bp, 1593adfc5217SJeff Kirsher union bnx2x_qable_obj *qo, 1594adfc5217SJeff Kirsher struct list_head *exe_chunk, 1595adfc5217SJeff Kirsher unsigned long *ramrod_flags) 1596adfc5217SJeff Kirsher { 1597adfc5217SJeff Kirsher struct bnx2x_exeq_elem *elem; 1598adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *o = &qo->vlan_mac, *cam_obj; 1599adfc5217SJeff Kirsher struct bnx2x_raw_obj *r = &o->raw; 1600adfc5217SJeff Kirsher int rc, idx = 0; 1601adfc5217SJeff Kirsher bool restore = test_bit(RAMROD_RESTORE, ramrod_flags); 1602adfc5217SJeff Kirsher bool drv_only = test_bit(RAMROD_DRV_CLR_ONLY, ramrod_flags); 1603adfc5217SJeff Kirsher struct bnx2x_vlan_mac_registry_elem *reg_elem; 160486564c3fSYuval Mintz enum bnx2x_vlan_mac_cmd cmd; 1605adfc5217SJeff Kirsher 160616a5fd92SYuval Mintz /* If DRIVER_ONLY execution is requested, cleanup a registry 1607adfc5217SJeff Kirsher * and exit. Otherwise send a ramrod to FW. 1608adfc5217SJeff Kirsher */ 1609adfc5217SJeff Kirsher if (!drv_only) { 1610adfc5217SJeff Kirsher WARN_ON(r->check_pending(r)); 1611adfc5217SJeff Kirsher 1612adfc5217SJeff Kirsher /* Set pending */ 1613adfc5217SJeff Kirsher r->set_pending(r); 1614adfc5217SJeff Kirsher 161516a5fd92SYuval Mintz /* Fill the ramrod data */ 1616adfc5217SJeff Kirsher list_for_each_entry(elem, exe_chunk, link) { 1617adfc5217SJeff Kirsher cmd = elem->cmd_data.vlan_mac.cmd; 161816a5fd92SYuval Mintz /* We will add to the target object in MOVE command, so 1619adfc5217SJeff Kirsher * change the object for a CAM search. 1620adfc5217SJeff Kirsher */ 1621adfc5217SJeff Kirsher if (cmd == BNX2X_VLAN_MAC_MOVE) 1622adfc5217SJeff Kirsher cam_obj = elem->cmd_data.vlan_mac.target_obj; 1623adfc5217SJeff Kirsher else 1624adfc5217SJeff Kirsher cam_obj = o; 1625adfc5217SJeff Kirsher 1626adfc5217SJeff Kirsher rc = bnx2x_vlan_mac_get_registry_elem(bp, cam_obj, 1627adfc5217SJeff Kirsher elem, restore, 1628adfc5217SJeff Kirsher ®_elem); 1629adfc5217SJeff Kirsher if (rc) 1630adfc5217SJeff Kirsher goto error_exit; 1631adfc5217SJeff Kirsher 1632adfc5217SJeff Kirsher WARN_ON(!reg_elem); 1633adfc5217SJeff Kirsher 1634adfc5217SJeff Kirsher /* Push a new entry into the registry */ 1635adfc5217SJeff Kirsher if (!restore && 1636adfc5217SJeff Kirsher ((cmd == BNX2X_VLAN_MAC_ADD) || 1637adfc5217SJeff Kirsher (cmd == BNX2X_VLAN_MAC_MOVE))) 1638adfc5217SJeff Kirsher list_add(®_elem->link, &cam_obj->head); 1639adfc5217SJeff Kirsher 1640adfc5217SJeff Kirsher /* Configure a single command in a ramrod data buffer */ 1641adfc5217SJeff Kirsher o->set_one_rule(bp, o, elem, idx, 1642adfc5217SJeff Kirsher reg_elem->cam_offset); 1643adfc5217SJeff Kirsher 1644adfc5217SJeff Kirsher /* MOVE command consumes 2 entries in the ramrod data */ 1645adfc5217SJeff Kirsher if (cmd == BNX2X_VLAN_MAC_MOVE) 1646adfc5217SJeff Kirsher idx += 2; 1647adfc5217SJeff Kirsher else 1648adfc5217SJeff Kirsher idx++; 1649adfc5217SJeff Kirsher } 1650adfc5217SJeff Kirsher 165116a5fd92SYuval Mintz /* No need for an explicit memory barrier here as long we would 1652adfc5217SJeff Kirsher * need to ensure the ordering of writing to the SPQ element 1653adfc5217SJeff Kirsher * and updating of the SPQ producer which involves a memory 1654adfc5217SJeff Kirsher * read and we will have to put a full memory barrier there 1655adfc5217SJeff Kirsher * (inside bnx2x_sp_post()). 1656adfc5217SJeff Kirsher */ 1657adfc5217SJeff Kirsher 1658adfc5217SJeff Kirsher rc = bnx2x_sp_post(bp, o->ramrod_cmd, r->cid, 1659adfc5217SJeff Kirsher U64_HI(r->rdata_mapping), 1660adfc5217SJeff Kirsher U64_LO(r->rdata_mapping), 1661adfc5217SJeff Kirsher ETH_CONNECTION_TYPE); 1662adfc5217SJeff Kirsher if (rc) 1663adfc5217SJeff Kirsher goto error_exit; 1664adfc5217SJeff Kirsher } 1665adfc5217SJeff Kirsher 1666adfc5217SJeff Kirsher /* Now, when we are done with the ramrod - clean up the registry */ 1667adfc5217SJeff Kirsher list_for_each_entry(elem, exe_chunk, link) { 1668adfc5217SJeff Kirsher cmd = elem->cmd_data.vlan_mac.cmd; 1669adfc5217SJeff Kirsher if ((cmd == BNX2X_VLAN_MAC_DEL) || 1670adfc5217SJeff Kirsher (cmd == BNX2X_VLAN_MAC_MOVE)) { 167151c1a580SMerav Sicron reg_elem = o->check_del(bp, o, 167251c1a580SMerav Sicron &elem->cmd_data.vlan_mac.u); 1673adfc5217SJeff Kirsher 1674adfc5217SJeff Kirsher WARN_ON(!reg_elem); 1675adfc5217SJeff Kirsher 1676adfc5217SJeff Kirsher o->put_cam_offset(o, reg_elem->cam_offset); 1677adfc5217SJeff Kirsher list_del(®_elem->link); 1678adfc5217SJeff Kirsher kfree(reg_elem); 1679adfc5217SJeff Kirsher } 1680adfc5217SJeff Kirsher } 1681adfc5217SJeff Kirsher 1682adfc5217SJeff Kirsher if (!drv_only) 1683adfc5217SJeff Kirsher return 1; 1684adfc5217SJeff Kirsher else 1685adfc5217SJeff Kirsher return 0; 1686adfc5217SJeff Kirsher 1687adfc5217SJeff Kirsher error_exit: 1688adfc5217SJeff Kirsher r->clear_pending(r); 1689adfc5217SJeff Kirsher 1690adfc5217SJeff Kirsher /* Cleanup a registry in case of a failure */ 1691adfc5217SJeff Kirsher list_for_each_entry(elem, exe_chunk, link) { 1692adfc5217SJeff Kirsher cmd = elem->cmd_data.vlan_mac.cmd; 1693adfc5217SJeff Kirsher 1694adfc5217SJeff Kirsher if (cmd == BNX2X_VLAN_MAC_MOVE) 1695adfc5217SJeff Kirsher cam_obj = elem->cmd_data.vlan_mac.target_obj; 1696adfc5217SJeff Kirsher else 1697adfc5217SJeff Kirsher cam_obj = o; 1698adfc5217SJeff Kirsher 1699adfc5217SJeff Kirsher /* Delete all newly added above entries */ 1700adfc5217SJeff Kirsher if (!restore && 1701adfc5217SJeff Kirsher ((cmd == BNX2X_VLAN_MAC_ADD) || 1702adfc5217SJeff Kirsher (cmd == BNX2X_VLAN_MAC_MOVE))) { 170351c1a580SMerav Sicron reg_elem = o->check_del(bp, cam_obj, 1704adfc5217SJeff Kirsher &elem->cmd_data.vlan_mac.u); 1705adfc5217SJeff Kirsher if (reg_elem) { 1706adfc5217SJeff Kirsher list_del(®_elem->link); 1707adfc5217SJeff Kirsher kfree(reg_elem); 1708adfc5217SJeff Kirsher } 1709adfc5217SJeff Kirsher } 1710adfc5217SJeff Kirsher } 1711adfc5217SJeff Kirsher 1712adfc5217SJeff Kirsher return rc; 1713adfc5217SJeff Kirsher } 1714adfc5217SJeff Kirsher 1715adfc5217SJeff Kirsher static inline int bnx2x_vlan_mac_push_new_cmd( 1716adfc5217SJeff Kirsher struct bnx2x *bp, 1717adfc5217SJeff Kirsher struct bnx2x_vlan_mac_ramrod_params *p) 1718adfc5217SJeff Kirsher { 1719adfc5217SJeff Kirsher struct bnx2x_exeq_elem *elem; 1720adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *o = p->vlan_mac_obj; 1721adfc5217SJeff Kirsher bool restore = test_bit(RAMROD_RESTORE, &p->ramrod_flags); 1722adfc5217SJeff Kirsher 1723adfc5217SJeff Kirsher /* Allocate the execution queue element */ 1724adfc5217SJeff Kirsher elem = bnx2x_exe_queue_alloc_elem(bp); 1725adfc5217SJeff Kirsher if (!elem) 1726adfc5217SJeff Kirsher return -ENOMEM; 1727adfc5217SJeff Kirsher 1728adfc5217SJeff Kirsher /* Set the command 'length' */ 1729adfc5217SJeff Kirsher switch (p->user_req.cmd) { 1730adfc5217SJeff Kirsher case BNX2X_VLAN_MAC_MOVE: 1731adfc5217SJeff Kirsher elem->cmd_len = 2; 1732adfc5217SJeff Kirsher break; 1733adfc5217SJeff Kirsher default: 1734adfc5217SJeff Kirsher elem->cmd_len = 1; 1735adfc5217SJeff Kirsher } 1736adfc5217SJeff Kirsher 1737adfc5217SJeff Kirsher /* Fill the object specific info */ 1738adfc5217SJeff Kirsher memcpy(&elem->cmd_data.vlan_mac, &p->user_req, sizeof(p->user_req)); 1739adfc5217SJeff Kirsher 1740adfc5217SJeff Kirsher /* Try to add a new command to the pending list */ 1741adfc5217SJeff Kirsher return bnx2x_exe_queue_add(bp, &o->exe_queue, elem, restore); 1742adfc5217SJeff Kirsher } 1743adfc5217SJeff Kirsher 1744adfc5217SJeff Kirsher /** 1745adfc5217SJeff Kirsher * bnx2x_config_vlan_mac - configure VLAN/MAC/VLAN_MAC filtering rules. 1746adfc5217SJeff Kirsher * 1747adfc5217SJeff Kirsher * @bp: device handle 1748adfc5217SJeff Kirsher * @p: 1749adfc5217SJeff Kirsher * 1750adfc5217SJeff Kirsher */ 17518b09be5fSYuval Mintz int bnx2x_config_vlan_mac(struct bnx2x *bp, 1752adfc5217SJeff Kirsher struct bnx2x_vlan_mac_ramrod_params *p) 1753adfc5217SJeff Kirsher { 1754adfc5217SJeff Kirsher int rc = 0; 1755adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *o = p->vlan_mac_obj; 1756adfc5217SJeff Kirsher unsigned long *ramrod_flags = &p->ramrod_flags; 1757adfc5217SJeff Kirsher bool cont = test_bit(RAMROD_CONT, ramrod_flags); 1758adfc5217SJeff Kirsher struct bnx2x_raw_obj *raw = &o->raw; 1759adfc5217SJeff Kirsher 1760adfc5217SJeff Kirsher /* 1761adfc5217SJeff Kirsher * Add new elements to the execution list for commands that require it. 1762adfc5217SJeff Kirsher */ 1763adfc5217SJeff Kirsher if (!cont) { 1764adfc5217SJeff Kirsher rc = bnx2x_vlan_mac_push_new_cmd(bp, p); 1765adfc5217SJeff Kirsher if (rc) 1766adfc5217SJeff Kirsher return rc; 1767adfc5217SJeff Kirsher } 1768adfc5217SJeff Kirsher 176916a5fd92SYuval Mintz /* If nothing will be executed further in this iteration we want to 1770adfc5217SJeff Kirsher * return PENDING if there are pending commands 1771adfc5217SJeff Kirsher */ 1772adfc5217SJeff Kirsher if (!bnx2x_exe_queue_empty(&o->exe_queue)) 1773adfc5217SJeff Kirsher rc = 1; 1774adfc5217SJeff Kirsher 1775adfc5217SJeff Kirsher if (test_bit(RAMROD_DRV_CLR_ONLY, ramrod_flags)) { 177651c1a580SMerav Sicron DP(BNX2X_MSG_SP, "RAMROD_DRV_CLR_ONLY requested: clearing a pending bit.\n"); 1777adfc5217SJeff Kirsher raw->clear_pending(raw); 1778adfc5217SJeff Kirsher } 1779adfc5217SJeff Kirsher 1780adfc5217SJeff Kirsher /* Execute commands if required */ 1781adfc5217SJeff Kirsher if (cont || test_bit(RAMROD_EXEC, ramrod_flags) || 1782adfc5217SJeff Kirsher test_bit(RAMROD_COMP_WAIT, ramrod_flags)) { 17838b09be5fSYuval Mintz rc = __bnx2x_vlan_mac_execute_step(bp, p->vlan_mac_obj, 17848b09be5fSYuval Mintz &p->ramrod_flags); 1785adfc5217SJeff Kirsher if (rc < 0) 1786adfc5217SJeff Kirsher return rc; 1787adfc5217SJeff Kirsher } 1788adfc5217SJeff Kirsher 178916a5fd92SYuval Mintz /* RAMROD_COMP_WAIT is a superset of RAMROD_EXEC. If it was set 1790adfc5217SJeff Kirsher * then user want to wait until the last command is done. 1791adfc5217SJeff Kirsher */ 1792adfc5217SJeff Kirsher if (test_bit(RAMROD_COMP_WAIT, &p->ramrod_flags)) { 179316a5fd92SYuval Mintz /* Wait maximum for the current exe_queue length iterations plus 1794adfc5217SJeff Kirsher * one (for the current pending command). 1795adfc5217SJeff Kirsher */ 1796adfc5217SJeff Kirsher int max_iterations = bnx2x_exe_queue_length(&o->exe_queue) + 1; 1797adfc5217SJeff Kirsher 1798adfc5217SJeff Kirsher while (!bnx2x_exe_queue_empty(&o->exe_queue) && 1799adfc5217SJeff Kirsher max_iterations--) { 1800adfc5217SJeff Kirsher 1801adfc5217SJeff Kirsher /* Wait for the current command to complete */ 1802adfc5217SJeff Kirsher rc = raw->wait_comp(bp, raw); 1803adfc5217SJeff Kirsher if (rc) 1804adfc5217SJeff Kirsher return rc; 1805adfc5217SJeff Kirsher 1806adfc5217SJeff Kirsher /* Make a next step */ 18078b09be5fSYuval Mintz rc = __bnx2x_vlan_mac_execute_step(bp, 18088b09be5fSYuval Mintz p->vlan_mac_obj, 18098b09be5fSYuval Mintz &p->ramrod_flags); 1810adfc5217SJeff Kirsher if (rc < 0) 1811adfc5217SJeff Kirsher return rc; 1812adfc5217SJeff Kirsher } 1813adfc5217SJeff Kirsher 1814adfc5217SJeff Kirsher return 0; 1815adfc5217SJeff Kirsher } 1816adfc5217SJeff Kirsher 1817adfc5217SJeff Kirsher return rc; 1818adfc5217SJeff Kirsher } 1819adfc5217SJeff Kirsher 1820adfc5217SJeff Kirsher /** 1821adfc5217SJeff Kirsher * bnx2x_vlan_mac_del_all - delete elements with given vlan_mac_flags spec 1822adfc5217SJeff Kirsher * 1823adfc5217SJeff Kirsher * @bp: device handle 1824adfc5217SJeff Kirsher * @o: 1825adfc5217SJeff Kirsher * @vlan_mac_flags: 1826adfc5217SJeff Kirsher * @ramrod_flags: execution flags to be used for this deletion 1827adfc5217SJeff Kirsher * 1828adfc5217SJeff Kirsher * if the last operation has completed successfully and there are no 1829adfc5217SJeff Kirsher * more elements left, positive value if the last operation has completed 1830adfc5217SJeff Kirsher * successfully and there are more previously configured elements, negative 1831adfc5217SJeff Kirsher * value is current operation has failed. 1832adfc5217SJeff Kirsher */ 1833adfc5217SJeff Kirsher static int bnx2x_vlan_mac_del_all(struct bnx2x *bp, 1834adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *o, 1835adfc5217SJeff Kirsher unsigned long *vlan_mac_flags, 1836adfc5217SJeff Kirsher unsigned long *ramrod_flags) 1837adfc5217SJeff Kirsher { 1838adfc5217SJeff Kirsher struct bnx2x_vlan_mac_registry_elem *pos = NULL; 1839adfc5217SJeff Kirsher struct bnx2x_vlan_mac_ramrod_params p; 1840adfc5217SJeff Kirsher struct bnx2x_exe_queue_obj *exeq = &o->exe_queue; 1841adfc5217SJeff Kirsher struct bnx2x_exeq_elem *exeq_pos, *exeq_pos_n; 1842e8379c79SYuval Mintz unsigned long flags; 18438b09be5fSYuval Mintz int read_lock; 18448b09be5fSYuval Mintz int rc = 0; 1845adfc5217SJeff Kirsher 1846adfc5217SJeff Kirsher /* Clear pending commands first */ 1847adfc5217SJeff Kirsher 1848adfc5217SJeff Kirsher spin_lock_bh(&exeq->lock); 1849adfc5217SJeff Kirsher 1850adfc5217SJeff Kirsher list_for_each_entry_safe(exeq_pos, exeq_pos_n, &exeq->exe_queue, link) { 1851e8379c79SYuval Mintz flags = exeq_pos->cmd_data.vlan_mac.vlan_mac_flags; 1852e8379c79SYuval Mintz if (BNX2X_VLAN_MAC_CMP_FLAGS(flags) == 1853e8379c79SYuval Mintz BNX2X_VLAN_MAC_CMP_FLAGS(*vlan_mac_flags)) { 1854460a25cdSYuval Mintz rc = exeq->remove(bp, exeq->owner, exeq_pos); 1855460a25cdSYuval Mintz if (rc) { 1856460a25cdSYuval Mintz BNX2X_ERR("Failed to remove command\n"); 1857a44acd55SDan Carpenter spin_unlock_bh(&exeq->lock); 1858460a25cdSYuval Mintz return rc; 1859460a25cdSYuval Mintz } 1860adfc5217SJeff Kirsher list_del(&exeq_pos->link); 186107ef7becSYuval Mintz bnx2x_exe_queue_free_elem(bp, exeq_pos); 1862adfc5217SJeff Kirsher } 1863460a25cdSYuval Mintz } 1864adfc5217SJeff Kirsher 1865adfc5217SJeff Kirsher spin_unlock_bh(&exeq->lock); 1866adfc5217SJeff Kirsher 1867adfc5217SJeff Kirsher /* Prepare a command request */ 1868adfc5217SJeff Kirsher memset(&p, 0, sizeof(p)); 1869adfc5217SJeff Kirsher p.vlan_mac_obj = o; 1870adfc5217SJeff Kirsher p.ramrod_flags = *ramrod_flags; 1871adfc5217SJeff Kirsher p.user_req.cmd = BNX2X_VLAN_MAC_DEL; 1872adfc5217SJeff Kirsher 187316a5fd92SYuval Mintz /* Add all but the last VLAN-MAC to the execution queue without actually 1874adfc5217SJeff Kirsher * execution anything. 1875adfc5217SJeff Kirsher */ 1876adfc5217SJeff Kirsher __clear_bit(RAMROD_COMP_WAIT, &p.ramrod_flags); 1877adfc5217SJeff Kirsher __clear_bit(RAMROD_EXEC, &p.ramrod_flags); 1878adfc5217SJeff Kirsher __clear_bit(RAMROD_CONT, &p.ramrod_flags); 1879adfc5217SJeff Kirsher 18808b09be5fSYuval Mintz DP(BNX2X_MSG_SP, "vlan_mac_del_all -- taking vlan_mac_lock (reader)\n"); 18818b09be5fSYuval Mintz read_lock = bnx2x_vlan_mac_h_read_lock(bp, o); 18828b09be5fSYuval Mintz if (read_lock != 0) 18838b09be5fSYuval Mintz return read_lock; 18848b09be5fSYuval Mintz 1885adfc5217SJeff Kirsher list_for_each_entry(pos, &o->head, link) { 1886e8379c79SYuval Mintz flags = pos->vlan_mac_flags; 1887e8379c79SYuval Mintz if (BNX2X_VLAN_MAC_CMP_FLAGS(flags) == 1888e8379c79SYuval Mintz BNX2X_VLAN_MAC_CMP_FLAGS(*vlan_mac_flags)) { 1889adfc5217SJeff Kirsher p.user_req.vlan_mac_flags = pos->vlan_mac_flags; 1890adfc5217SJeff Kirsher memcpy(&p.user_req.u, &pos->u, sizeof(pos->u)); 1891adfc5217SJeff Kirsher rc = bnx2x_config_vlan_mac(bp, &p); 1892adfc5217SJeff Kirsher if (rc < 0) { 1893adfc5217SJeff Kirsher BNX2X_ERR("Failed to add a new DEL command\n"); 18948b09be5fSYuval Mintz bnx2x_vlan_mac_h_read_unlock(bp, o); 1895adfc5217SJeff Kirsher return rc; 1896adfc5217SJeff Kirsher } 1897adfc5217SJeff Kirsher } 1898adfc5217SJeff Kirsher } 1899adfc5217SJeff Kirsher 19008b09be5fSYuval Mintz DP(BNX2X_MSG_SP, "vlan_mac_del_all -- releasing vlan_mac_lock (reader)\n"); 19018b09be5fSYuval Mintz bnx2x_vlan_mac_h_read_unlock(bp, o); 19028b09be5fSYuval Mintz 1903adfc5217SJeff Kirsher p.ramrod_flags = *ramrod_flags; 1904adfc5217SJeff Kirsher __set_bit(RAMROD_CONT, &p.ramrod_flags); 1905adfc5217SJeff Kirsher 1906adfc5217SJeff Kirsher return bnx2x_config_vlan_mac(bp, &p); 1907adfc5217SJeff Kirsher } 1908adfc5217SJeff Kirsher 1909adfc5217SJeff Kirsher static inline void bnx2x_init_raw_obj(struct bnx2x_raw_obj *raw, u8 cl_id, 1910adfc5217SJeff Kirsher u32 cid, u8 func_id, void *rdata, dma_addr_t rdata_mapping, int state, 1911adfc5217SJeff Kirsher unsigned long *pstate, bnx2x_obj_type type) 1912adfc5217SJeff Kirsher { 1913adfc5217SJeff Kirsher raw->func_id = func_id; 1914adfc5217SJeff Kirsher raw->cid = cid; 1915adfc5217SJeff Kirsher raw->cl_id = cl_id; 1916adfc5217SJeff Kirsher raw->rdata = rdata; 1917adfc5217SJeff Kirsher raw->rdata_mapping = rdata_mapping; 1918adfc5217SJeff Kirsher raw->state = state; 1919adfc5217SJeff Kirsher raw->pstate = pstate; 1920adfc5217SJeff Kirsher raw->obj_type = type; 1921adfc5217SJeff Kirsher raw->check_pending = bnx2x_raw_check_pending; 1922adfc5217SJeff Kirsher raw->clear_pending = bnx2x_raw_clear_pending; 1923adfc5217SJeff Kirsher raw->set_pending = bnx2x_raw_set_pending; 1924adfc5217SJeff Kirsher raw->wait_comp = bnx2x_raw_wait; 1925adfc5217SJeff Kirsher } 1926adfc5217SJeff Kirsher 1927adfc5217SJeff Kirsher static inline void bnx2x_init_vlan_mac_common(struct bnx2x_vlan_mac_obj *o, 1928adfc5217SJeff Kirsher u8 cl_id, u32 cid, u8 func_id, void *rdata, dma_addr_t rdata_mapping, 1929adfc5217SJeff Kirsher int state, unsigned long *pstate, bnx2x_obj_type type, 1930adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *macs_pool, 1931adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *vlans_pool) 1932adfc5217SJeff Kirsher { 1933adfc5217SJeff Kirsher INIT_LIST_HEAD(&o->head); 19348b09be5fSYuval Mintz o->head_reader = 0; 19358b09be5fSYuval Mintz o->head_exe_request = false; 19368b09be5fSYuval Mintz o->saved_ramrod_flags = 0; 1937adfc5217SJeff Kirsher 1938adfc5217SJeff Kirsher o->macs_pool = macs_pool; 1939adfc5217SJeff Kirsher o->vlans_pool = vlans_pool; 1940adfc5217SJeff Kirsher 1941adfc5217SJeff Kirsher o->delete_all = bnx2x_vlan_mac_del_all; 1942adfc5217SJeff Kirsher o->restore = bnx2x_vlan_mac_restore; 1943adfc5217SJeff Kirsher o->complete = bnx2x_complete_vlan_mac; 1944adfc5217SJeff Kirsher o->wait = bnx2x_wait_vlan_mac; 1945adfc5217SJeff Kirsher 1946adfc5217SJeff Kirsher bnx2x_init_raw_obj(&o->raw, cl_id, cid, func_id, rdata, rdata_mapping, 1947adfc5217SJeff Kirsher state, pstate, type); 1948adfc5217SJeff Kirsher } 1949adfc5217SJeff Kirsher 1950adfc5217SJeff Kirsher void bnx2x_init_mac_obj(struct bnx2x *bp, 1951adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *mac_obj, 1952adfc5217SJeff Kirsher u8 cl_id, u32 cid, u8 func_id, void *rdata, 1953adfc5217SJeff Kirsher dma_addr_t rdata_mapping, int state, 1954adfc5217SJeff Kirsher unsigned long *pstate, bnx2x_obj_type type, 1955adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *macs_pool) 1956adfc5217SJeff Kirsher { 1957adfc5217SJeff Kirsher union bnx2x_qable_obj *qable_obj = (union bnx2x_qable_obj *)mac_obj; 1958adfc5217SJeff Kirsher 1959adfc5217SJeff Kirsher bnx2x_init_vlan_mac_common(mac_obj, cl_id, cid, func_id, rdata, 1960adfc5217SJeff Kirsher rdata_mapping, state, pstate, type, 1961adfc5217SJeff Kirsher macs_pool, NULL); 1962adfc5217SJeff Kirsher 1963adfc5217SJeff Kirsher /* CAM credit pool handling */ 1964adfc5217SJeff Kirsher mac_obj->get_credit = bnx2x_get_credit_mac; 1965adfc5217SJeff Kirsher mac_obj->put_credit = bnx2x_put_credit_mac; 1966adfc5217SJeff Kirsher mac_obj->get_cam_offset = bnx2x_get_cam_offset_mac; 1967adfc5217SJeff Kirsher mac_obj->put_cam_offset = bnx2x_put_cam_offset_mac; 1968adfc5217SJeff Kirsher 1969adfc5217SJeff Kirsher if (CHIP_IS_E1x(bp)) { 1970adfc5217SJeff Kirsher mac_obj->set_one_rule = bnx2x_set_one_mac_e1x; 1971adfc5217SJeff Kirsher mac_obj->check_del = bnx2x_check_mac_del; 1972adfc5217SJeff Kirsher mac_obj->check_add = bnx2x_check_mac_add; 1973adfc5217SJeff Kirsher mac_obj->check_move = bnx2x_check_move_always_err; 1974adfc5217SJeff Kirsher mac_obj->ramrod_cmd = RAMROD_CMD_ID_ETH_SET_MAC; 1975adfc5217SJeff Kirsher 1976adfc5217SJeff Kirsher /* Exe Queue */ 1977adfc5217SJeff Kirsher bnx2x_exe_queue_init(bp, 1978adfc5217SJeff Kirsher &mac_obj->exe_queue, 1, qable_obj, 1979adfc5217SJeff Kirsher bnx2x_validate_vlan_mac, 1980460a25cdSYuval Mintz bnx2x_remove_vlan_mac, 1981adfc5217SJeff Kirsher bnx2x_optimize_vlan_mac, 1982adfc5217SJeff Kirsher bnx2x_execute_vlan_mac, 1983adfc5217SJeff Kirsher bnx2x_exeq_get_mac); 1984adfc5217SJeff Kirsher } else { 1985adfc5217SJeff Kirsher mac_obj->set_one_rule = bnx2x_set_one_mac_e2; 1986adfc5217SJeff Kirsher mac_obj->check_del = bnx2x_check_mac_del; 1987adfc5217SJeff Kirsher mac_obj->check_add = bnx2x_check_mac_add; 1988adfc5217SJeff Kirsher mac_obj->check_move = bnx2x_check_move; 1989adfc5217SJeff Kirsher mac_obj->ramrod_cmd = 1990adfc5217SJeff Kirsher RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES; 1991ed5162a0SAriel Elior mac_obj->get_n_elements = bnx2x_get_n_elements; 1992adfc5217SJeff Kirsher 1993adfc5217SJeff Kirsher /* Exe Queue */ 1994adfc5217SJeff Kirsher bnx2x_exe_queue_init(bp, 1995adfc5217SJeff Kirsher &mac_obj->exe_queue, CLASSIFY_RULES_COUNT, 1996adfc5217SJeff Kirsher qable_obj, bnx2x_validate_vlan_mac, 1997460a25cdSYuval Mintz bnx2x_remove_vlan_mac, 1998adfc5217SJeff Kirsher bnx2x_optimize_vlan_mac, 1999adfc5217SJeff Kirsher bnx2x_execute_vlan_mac, 2000adfc5217SJeff Kirsher bnx2x_exeq_get_mac); 2001adfc5217SJeff Kirsher } 2002adfc5217SJeff Kirsher } 2003adfc5217SJeff Kirsher 2004adfc5217SJeff Kirsher void bnx2x_init_vlan_obj(struct bnx2x *bp, 2005adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *vlan_obj, 2006adfc5217SJeff Kirsher u8 cl_id, u32 cid, u8 func_id, void *rdata, 2007adfc5217SJeff Kirsher dma_addr_t rdata_mapping, int state, 2008adfc5217SJeff Kirsher unsigned long *pstate, bnx2x_obj_type type, 2009adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *vlans_pool) 2010adfc5217SJeff Kirsher { 2011adfc5217SJeff Kirsher union bnx2x_qable_obj *qable_obj = (union bnx2x_qable_obj *)vlan_obj; 2012adfc5217SJeff Kirsher 2013adfc5217SJeff Kirsher bnx2x_init_vlan_mac_common(vlan_obj, cl_id, cid, func_id, rdata, 2014adfc5217SJeff Kirsher rdata_mapping, state, pstate, type, NULL, 2015adfc5217SJeff Kirsher vlans_pool); 2016adfc5217SJeff Kirsher 2017adfc5217SJeff Kirsher vlan_obj->get_credit = bnx2x_get_credit_vlan; 2018adfc5217SJeff Kirsher vlan_obj->put_credit = bnx2x_put_credit_vlan; 2019adfc5217SJeff Kirsher vlan_obj->get_cam_offset = bnx2x_get_cam_offset_vlan; 2020adfc5217SJeff Kirsher vlan_obj->put_cam_offset = bnx2x_put_cam_offset_vlan; 2021adfc5217SJeff Kirsher 2022adfc5217SJeff Kirsher if (CHIP_IS_E1x(bp)) { 2023adfc5217SJeff Kirsher BNX2X_ERR("Do not support chips others than E2 and newer\n"); 2024adfc5217SJeff Kirsher BUG(); 2025adfc5217SJeff Kirsher } else { 2026adfc5217SJeff Kirsher vlan_obj->set_one_rule = bnx2x_set_one_vlan_e2; 2027adfc5217SJeff Kirsher vlan_obj->check_del = bnx2x_check_vlan_del; 2028adfc5217SJeff Kirsher vlan_obj->check_add = bnx2x_check_vlan_add; 2029adfc5217SJeff Kirsher vlan_obj->check_move = bnx2x_check_move; 2030adfc5217SJeff Kirsher vlan_obj->ramrod_cmd = 2031adfc5217SJeff Kirsher RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES; 20323ec9f9caSAriel Elior vlan_obj->get_n_elements = bnx2x_get_n_elements; 2033adfc5217SJeff Kirsher 2034adfc5217SJeff Kirsher /* Exe Queue */ 2035adfc5217SJeff Kirsher bnx2x_exe_queue_init(bp, 2036adfc5217SJeff Kirsher &vlan_obj->exe_queue, CLASSIFY_RULES_COUNT, 2037adfc5217SJeff Kirsher qable_obj, bnx2x_validate_vlan_mac, 2038460a25cdSYuval Mintz bnx2x_remove_vlan_mac, 2039adfc5217SJeff Kirsher bnx2x_optimize_vlan_mac, 2040adfc5217SJeff Kirsher bnx2x_execute_vlan_mac, 2041adfc5217SJeff Kirsher bnx2x_exeq_get_vlan); 2042adfc5217SJeff Kirsher } 2043adfc5217SJeff Kirsher } 2044adfc5217SJeff Kirsher 2045adfc5217SJeff Kirsher /* RX_MODE verbs: DROP_ALL/ACCEPT_ALL/ACCEPT_ALL_MULTI/ACCEPT_ALL_VLAN/NORMAL */ 2046adfc5217SJeff Kirsher static inline void __storm_memset_mac_filters(struct bnx2x *bp, 2047adfc5217SJeff Kirsher struct tstorm_eth_mac_filter_config *mac_filters, 2048adfc5217SJeff Kirsher u16 pf_id) 2049adfc5217SJeff Kirsher { 2050adfc5217SJeff Kirsher size_t size = sizeof(struct tstorm_eth_mac_filter_config); 2051adfc5217SJeff Kirsher 2052adfc5217SJeff Kirsher u32 addr = BAR_TSTRORM_INTMEM + 2053adfc5217SJeff Kirsher TSTORM_MAC_FILTER_CONFIG_OFFSET(pf_id); 2054adfc5217SJeff Kirsher 2055adfc5217SJeff Kirsher __storm_memset_struct(bp, addr, size, (u32 *)mac_filters); 2056adfc5217SJeff Kirsher } 2057adfc5217SJeff Kirsher 2058adfc5217SJeff Kirsher static int bnx2x_set_rx_mode_e1x(struct bnx2x *bp, 2059adfc5217SJeff Kirsher struct bnx2x_rx_mode_ramrod_params *p) 2060adfc5217SJeff Kirsher { 2061adfc5217SJeff Kirsher /* update the bp MAC filter structure */ 2062adfc5217SJeff Kirsher u32 mask = (1 << p->cl_id); 2063adfc5217SJeff Kirsher 2064adfc5217SJeff Kirsher struct tstorm_eth_mac_filter_config *mac_filters = 2065adfc5217SJeff Kirsher (struct tstorm_eth_mac_filter_config *)p->rdata; 2066adfc5217SJeff Kirsher 206716a5fd92SYuval Mintz /* initial setting is drop-all */ 2068adfc5217SJeff Kirsher u8 drop_all_ucast = 1, drop_all_mcast = 1; 2069adfc5217SJeff Kirsher u8 accp_all_ucast = 0, accp_all_bcast = 0, accp_all_mcast = 0; 2070adfc5217SJeff Kirsher u8 unmatched_unicast = 0; 2071adfc5217SJeff Kirsher 207216a5fd92SYuval Mintz /* In e1x there we only take into account rx accept flag since tx switching 2073adfc5217SJeff Kirsher * isn't enabled. */ 2074adfc5217SJeff Kirsher if (test_bit(BNX2X_ACCEPT_UNICAST, &p->rx_accept_flags)) 2075adfc5217SJeff Kirsher /* accept matched ucast */ 2076adfc5217SJeff Kirsher drop_all_ucast = 0; 2077adfc5217SJeff Kirsher 2078adfc5217SJeff Kirsher if (test_bit(BNX2X_ACCEPT_MULTICAST, &p->rx_accept_flags)) 2079adfc5217SJeff Kirsher /* accept matched mcast */ 2080adfc5217SJeff Kirsher drop_all_mcast = 0; 2081adfc5217SJeff Kirsher 2082adfc5217SJeff Kirsher if (test_bit(BNX2X_ACCEPT_ALL_UNICAST, &p->rx_accept_flags)) { 2083adfc5217SJeff Kirsher /* accept all mcast */ 2084adfc5217SJeff Kirsher drop_all_ucast = 0; 2085adfc5217SJeff Kirsher accp_all_ucast = 1; 2086adfc5217SJeff Kirsher } 2087adfc5217SJeff Kirsher if (test_bit(BNX2X_ACCEPT_ALL_MULTICAST, &p->rx_accept_flags)) { 2088adfc5217SJeff Kirsher /* accept all mcast */ 2089adfc5217SJeff Kirsher drop_all_mcast = 0; 2090adfc5217SJeff Kirsher accp_all_mcast = 1; 2091adfc5217SJeff Kirsher } 2092adfc5217SJeff Kirsher if (test_bit(BNX2X_ACCEPT_BROADCAST, &p->rx_accept_flags)) 2093adfc5217SJeff Kirsher /* accept (all) bcast */ 2094adfc5217SJeff Kirsher accp_all_bcast = 1; 2095adfc5217SJeff Kirsher if (test_bit(BNX2X_ACCEPT_UNMATCHED, &p->rx_accept_flags)) 2096adfc5217SJeff Kirsher /* accept unmatched unicasts */ 2097adfc5217SJeff Kirsher unmatched_unicast = 1; 2098adfc5217SJeff Kirsher 2099adfc5217SJeff Kirsher mac_filters->ucast_drop_all = drop_all_ucast ? 2100adfc5217SJeff Kirsher mac_filters->ucast_drop_all | mask : 2101adfc5217SJeff Kirsher mac_filters->ucast_drop_all & ~mask; 2102adfc5217SJeff Kirsher 2103adfc5217SJeff Kirsher mac_filters->mcast_drop_all = drop_all_mcast ? 2104adfc5217SJeff Kirsher mac_filters->mcast_drop_all | mask : 2105adfc5217SJeff Kirsher mac_filters->mcast_drop_all & ~mask; 2106adfc5217SJeff Kirsher 2107adfc5217SJeff Kirsher mac_filters->ucast_accept_all = accp_all_ucast ? 2108adfc5217SJeff Kirsher mac_filters->ucast_accept_all | mask : 2109adfc5217SJeff Kirsher mac_filters->ucast_accept_all & ~mask; 2110adfc5217SJeff Kirsher 2111adfc5217SJeff Kirsher mac_filters->mcast_accept_all = accp_all_mcast ? 2112adfc5217SJeff Kirsher mac_filters->mcast_accept_all | mask : 2113adfc5217SJeff Kirsher mac_filters->mcast_accept_all & ~mask; 2114adfc5217SJeff Kirsher 2115adfc5217SJeff Kirsher mac_filters->bcast_accept_all = accp_all_bcast ? 2116adfc5217SJeff Kirsher mac_filters->bcast_accept_all | mask : 2117adfc5217SJeff Kirsher mac_filters->bcast_accept_all & ~mask; 2118adfc5217SJeff Kirsher 2119adfc5217SJeff Kirsher mac_filters->unmatched_unicast = unmatched_unicast ? 2120adfc5217SJeff Kirsher mac_filters->unmatched_unicast | mask : 2121adfc5217SJeff Kirsher mac_filters->unmatched_unicast & ~mask; 2122adfc5217SJeff Kirsher 2123adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "drop_ucast 0x%x\ndrop_mcast 0x%x\n accp_ucast 0x%x\n" 2124adfc5217SJeff Kirsher "accp_mcast 0x%x\naccp_bcast 0x%x\n", 212551c1a580SMerav Sicron mac_filters->ucast_drop_all, mac_filters->mcast_drop_all, 212651c1a580SMerav Sicron mac_filters->ucast_accept_all, mac_filters->mcast_accept_all, 2127adfc5217SJeff Kirsher mac_filters->bcast_accept_all); 2128adfc5217SJeff Kirsher 2129adfc5217SJeff Kirsher /* write the MAC filter structure*/ 2130adfc5217SJeff Kirsher __storm_memset_mac_filters(bp, mac_filters, p->func_id); 2131adfc5217SJeff Kirsher 2132adfc5217SJeff Kirsher /* The operation is completed */ 2133adfc5217SJeff Kirsher clear_bit(p->state, p->pstate); 21344e857c58SPeter Zijlstra smp_mb__after_atomic(); 2135adfc5217SJeff Kirsher 2136adfc5217SJeff Kirsher return 0; 2137adfc5217SJeff Kirsher } 2138adfc5217SJeff Kirsher 2139adfc5217SJeff Kirsher /* Setup ramrod data */ 2140adfc5217SJeff Kirsher static inline void bnx2x_rx_mode_set_rdata_hdr_e2(u32 cid, 2141adfc5217SJeff Kirsher struct eth_classify_header *hdr, 2142adfc5217SJeff Kirsher u8 rule_cnt) 2143adfc5217SJeff Kirsher { 214486564c3fSYuval Mintz hdr->echo = cpu_to_le32(cid); 2145adfc5217SJeff Kirsher hdr->rule_cnt = rule_cnt; 2146adfc5217SJeff Kirsher } 2147adfc5217SJeff Kirsher 2148adfc5217SJeff Kirsher static inline void bnx2x_rx_mode_set_cmd_state_e2(struct bnx2x *bp, 2149924d75abSYuval Mintz unsigned long *accept_flags, 2150adfc5217SJeff Kirsher struct eth_filter_rules_cmd *cmd, 2151adfc5217SJeff Kirsher bool clear_accept_all) 2152adfc5217SJeff Kirsher { 2153adfc5217SJeff Kirsher u16 state; 2154adfc5217SJeff Kirsher 2155adfc5217SJeff Kirsher /* start with 'drop-all' */ 2156adfc5217SJeff Kirsher state = ETH_FILTER_RULES_CMD_UCAST_DROP_ALL | 2157adfc5217SJeff Kirsher ETH_FILTER_RULES_CMD_MCAST_DROP_ALL; 2158adfc5217SJeff Kirsher 2159924d75abSYuval Mintz if (test_bit(BNX2X_ACCEPT_UNICAST, accept_flags)) 2160adfc5217SJeff Kirsher state &= ~ETH_FILTER_RULES_CMD_UCAST_DROP_ALL; 2161adfc5217SJeff Kirsher 2162924d75abSYuval Mintz if (test_bit(BNX2X_ACCEPT_MULTICAST, accept_flags)) 2163adfc5217SJeff Kirsher state &= ~ETH_FILTER_RULES_CMD_MCAST_DROP_ALL; 2164adfc5217SJeff Kirsher 2165924d75abSYuval Mintz if (test_bit(BNX2X_ACCEPT_ALL_UNICAST, accept_flags)) { 2166adfc5217SJeff Kirsher state &= ~ETH_FILTER_RULES_CMD_UCAST_DROP_ALL; 2167adfc5217SJeff Kirsher state |= ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL; 2168adfc5217SJeff Kirsher } 2169adfc5217SJeff Kirsher 2170924d75abSYuval Mintz if (test_bit(BNX2X_ACCEPT_ALL_MULTICAST, accept_flags)) { 2171adfc5217SJeff Kirsher state |= ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL; 2172adfc5217SJeff Kirsher state &= ~ETH_FILTER_RULES_CMD_MCAST_DROP_ALL; 2173adfc5217SJeff Kirsher } 2174924d75abSYuval Mintz 2175924d75abSYuval Mintz if (test_bit(BNX2X_ACCEPT_BROADCAST, accept_flags)) 2176adfc5217SJeff Kirsher state |= ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL; 2177adfc5217SJeff Kirsher 2178924d75abSYuval Mintz if (test_bit(BNX2X_ACCEPT_UNMATCHED, accept_flags)) { 2179adfc5217SJeff Kirsher state &= ~ETH_FILTER_RULES_CMD_UCAST_DROP_ALL; 2180adfc5217SJeff Kirsher state |= ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED; 2181adfc5217SJeff Kirsher } 2182924d75abSYuval Mintz 2183924d75abSYuval Mintz if (test_bit(BNX2X_ACCEPT_ANY_VLAN, accept_flags)) 2184adfc5217SJeff Kirsher state |= ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN; 2185adfc5217SJeff Kirsher 2186adfc5217SJeff Kirsher /* Clear ACCEPT_ALL_XXX flags for FCoE L2 Queue */ 2187adfc5217SJeff Kirsher if (clear_accept_all) { 2188adfc5217SJeff Kirsher state &= ~ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL; 2189adfc5217SJeff Kirsher state &= ~ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL; 2190adfc5217SJeff Kirsher state &= ~ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL; 2191adfc5217SJeff Kirsher state &= ~ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED; 2192adfc5217SJeff Kirsher } 2193adfc5217SJeff Kirsher 2194adfc5217SJeff Kirsher cmd->state = cpu_to_le16(state); 2195adfc5217SJeff Kirsher } 2196adfc5217SJeff Kirsher 2197adfc5217SJeff Kirsher static int bnx2x_set_rx_mode_e2(struct bnx2x *bp, 2198adfc5217SJeff Kirsher struct bnx2x_rx_mode_ramrod_params *p) 2199adfc5217SJeff Kirsher { 2200adfc5217SJeff Kirsher struct eth_filter_rules_ramrod_data *data = p->rdata; 2201adfc5217SJeff Kirsher int rc; 2202adfc5217SJeff Kirsher u8 rule_idx = 0; 2203adfc5217SJeff Kirsher 2204adfc5217SJeff Kirsher /* Reset the ramrod data buffer */ 2205adfc5217SJeff Kirsher memset(data, 0, sizeof(*data)); 2206adfc5217SJeff Kirsher 2207adfc5217SJeff Kirsher /* Setup ramrod data */ 2208adfc5217SJeff Kirsher 2209adfc5217SJeff Kirsher /* Tx (internal switching) */ 2210adfc5217SJeff Kirsher if (test_bit(RAMROD_TX, &p->ramrod_flags)) { 2211adfc5217SJeff Kirsher data->rules[rule_idx].client_id = p->cl_id; 2212adfc5217SJeff Kirsher data->rules[rule_idx].func_id = p->func_id; 2213adfc5217SJeff Kirsher 2214adfc5217SJeff Kirsher data->rules[rule_idx].cmd_general_data = 2215adfc5217SJeff Kirsher ETH_FILTER_RULES_CMD_TX_CMD; 2216adfc5217SJeff Kirsher 2217924d75abSYuval Mintz bnx2x_rx_mode_set_cmd_state_e2(bp, &p->tx_accept_flags, 2218924d75abSYuval Mintz &(data->rules[rule_idx++]), 2219924d75abSYuval Mintz false); 2220adfc5217SJeff Kirsher } 2221adfc5217SJeff Kirsher 2222adfc5217SJeff Kirsher /* Rx */ 2223adfc5217SJeff Kirsher if (test_bit(RAMROD_RX, &p->ramrod_flags)) { 2224adfc5217SJeff Kirsher data->rules[rule_idx].client_id = p->cl_id; 2225adfc5217SJeff Kirsher data->rules[rule_idx].func_id = p->func_id; 2226adfc5217SJeff Kirsher 2227adfc5217SJeff Kirsher data->rules[rule_idx].cmd_general_data = 2228adfc5217SJeff Kirsher ETH_FILTER_RULES_CMD_RX_CMD; 2229adfc5217SJeff Kirsher 2230924d75abSYuval Mintz bnx2x_rx_mode_set_cmd_state_e2(bp, &p->rx_accept_flags, 2231924d75abSYuval Mintz &(data->rules[rule_idx++]), 2232924d75abSYuval Mintz false); 2233adfc5217SJeff Kirsher } 2234adfc5217SJeff Kirsher 223516a5fd92SYuval Mintz /* If FCoE Queue configuration has been requested configure the Rx and 2236adfc5217SJeff Kirsher * internal switching modes for this queue in separate rules. 2237adfc5217SJeff Kirsher * 2238adfc5217SJeff Kirsher * FCoE queue shell never be set to ACCEPT_ALL packets of any sort: 2239adfc5217SJeff Kirsher * MCAST_ALL, UCAST_ALL, BCAST_ALL and UNMATCHED. 2240adfc5217SJeff Kirsher */ 2241adfc5217SJeff Kirsher if (test_bit(BNX2X_RX_MODE_FCOE_ETH, &p->rx_mode_flags)) { 2242adfc5217SJeff Kirsher /* Tx (internal switching) */ 2243adfc5217SJeff Kirsher if (test_bit(RAMROD_TX, &p->ramrod_flags)) { 2244adfc5217SJeff Kirsher data->rules[rule_idx].client_id = bnx2x_fcoe(bp, cl_id); 2245adfc5217SJeff Kirsher data->rules[rule_idx].func_id = p->func_id; 2246adfc5217SJeff Kirsher 2247adfc5217SJeff Kirsher data->rules[rule_idx].cmd_general_data = 2248adfc5217SJeff Kirsher ETH_FILTER_RULES_CMD_TX_CMD; 2249adfc5217SJeff Kirsher 2250924d75abSYuval Mintz bnx2x_rx_mode_set_cmd_state_e2(bp, &p->tx_accept_flags, 2251924d75abSYuval Mintz &(data->rules[rule_idx]), 2252adfc5217SJeff Kirsher true); 2253924d75abSYuval Mintz rule_idx++; 2254adfc5217SJeff Kirsher } 2255adfc5217SJeff Kirsher 2256adfc5217SJeff Kirsher /* Rx */ 2257adfc5217SJeff Kirsher if (test_bit(RAMROD_RX, &p->ramrod_flags)) { 2258adfc5217SJeff Kirsher data->rules[rule_idx].client_id = bnx2x_fcoe(bp, cl_id); 2259adfc5217SJeff Kirsher data->rules[rule_idx].func_id = p->func_id; 2260adfc5217SJeff Kirsher 2261adfc5217SJeff Kirsher data->rules[rule_idx].cmd_general_data = 2262adfc5217SJeff Kirsher ETH_FILTER_RULES_CMD_RX_CMD; 2263adfc5217SJeff Kirsher 2264924d75abSYuval Mintz bnx2x_rx_mode_set_cmd_state_e2(bp, &p->rx_accept_flags, 2265924d75abSYuval Mintz &(data->rules[rule_idx]), 2266adfc5217SJeff Kirsher true); 2267924d75abSYuval Mintz rule_idx++; 2268adfc5217SJeff Kirsher } 2269adfc5217SJeff Kirsher } 2270adfc5217SJeff Kirsher 227116a5fd92SYuval Mintz /* Set the ramrod header (most importantly - number of rules to 2272adfc5217SJeff Kirsher * configure). 2273adfc5217SJeff Kirsher */ 2274adfc5217SJeff Kirsher bnx2x_rx_mode_set_rdata_hdr_e2(p->cid, &data->header, rule_idx); 2275adfc5217SJeff Kirsher 227651c1a580SMerav Sicron DP(BNX2X_MSG_SP, "About to configure %d rules, rx_accept_flags 0x%lx, tx_accept_flags 0x%lx\n", 2277adfc5217SJeff Kirsher data->header.rule_cnt, p->rx_accept_flags, 2278adfc5217SJeff Kirsher p->tx_accept_flags); 2279adfc5217SJeff Kirsher 228014a94ebdSMichal Kalderon /* No need for an explicit memory barrier here as long as we 228114a94ebdSMichal Kalderon * ensure the ordering of writing to the SPQ element 2282adfc5217SJeff Kirsher * and updating of the SPQ producer which involves a memory 228314a94ebdSMichal Kalderon * read. If the memory read is removed we will have to put a 228414a94ebdSMichal Kalderon * full memory barrier there (inside bnx2x_sp_post()). 2285adfc5217SJeff Kirsher */ 2286adfc5217SJeff Kirsher 2287adfc5217SJeff Kirsher /* Send a ramrod */ 2288adfc5217SJeff Kirsher rc = bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_FILTER_RULES, p->cid, 2289adfc5217SJeff Kirsher U64_HI(p->rdata_mapping), 2290adfc5217SJeff Kirsher U64_LO(p->rdata_mapping), 2291adfc5217SJeff Kirsher ETH_CONNECTION_TYPE); 2292adfc5217SJeff Kirsher if (rc) 2293adfc5217SJeff Kirsher return rc; 2294adfc5217SJeff Kirsher 2295adfc5217SJeff Kirsher /* Ramrod completion is pending */ 2296adfc5217SJeff Kirsher return 1; 2297adfc5217SJeff Kirsher } 2298adfc5217SJeff Kirsher 2299adfc5217SJeff Kirsher static int bnx2x_wait_rx_mode_comp_e2(struct bnx2x *bp, 2300adfc5217SJeff Kirsher struct bnx2x_rx_mode_ramrod_params *p) 2301adfc5217SJeff Kirsher { 2302adfc5217SJeff Kirsher return bnx2x_state_wait(bp, p->state, p->pstate); 2303adfc5217SJeff Kirsher } 2304adfc5217SJeff Kirsher 2305adfc5217SJeff Kirsher static int bnx2x_empty_rx_mode_wait(struct bnx2x *bp, 2306adfc5217SJeff Kirsher struct bnx2x_rx_mode_ramrod_params *p) 2307adfc5217SJeff Kirsher { 2308adfc5217SJeff Kirsher /* Do nothing */ 2309adfc5217SJeff Kirsher return 0; 2310adfc5217SJeff Kirsher } 2311adfc5217SJeff Kirsher 2312adfc5217SJeff Kirsher int bnx2x_config_rx_mode(struct bnx2x *bp, 2313adfc5217SJeff Kirsher struct bnx2x_rx_mode_ramrod_params *p) 2314adfc5217SJeff Kirsher { 2315adfc5217SJeff Kirsher int rc; 2316adfc5217SJeff Kirsher 2317adfc5217SJeff Kirsher /* Configure the new classification in the chip */ 2318adfc5217SJeff Kirsher rc = p->rx_mode_obj->config_rx_mode(bp, p); 2319adfc5217SJeff Kirsher if (rc < 0) 2320adfc5217SJeff Kirsher return rc; 2321adfc5217SJeff Kirsher 2322adfc5217SJeff Kirsher /* Wait for a ramrod completion if was requested */ 2323adfc5217SJeff Kirsher if (test_bit(RAMROD_COMP_WAIT, &p->ramrod_flags)) { 2324adfc5217SJeff Kirsher rc = p->rx_mode_obj->wait_comp(bp, p); 2325adfc5217SJeff Kirsher if (rc) 2326adfc5217SJeff Kirsher return rc; 2327adfc5217SJeff Kirsher } 2328adfc5217SJeff Kirsher 2329adfc5217SJeff Kirsher return rc; 2330adfc5217SJeff Kirsher } 2331adfc5217SJeff Kirsher 2332adfc5217SJeff Kirsher void bnx2x_init_rx_mode_obj(struct bnx2x *bp, 2333adfc5217SJeff Kirsher struct bnx2x_rx_mode_obj *o) 2334adfc5217SJeff Kirsher { 2335adfc5217SJeff Kirsher if (CHIP_IS_E1x(bp)) { 2336adfc5217SJeff Kirsher o->wait_comp = bnx2x_empty_rx_mode_wait; 2337adfc5217SJeff Kirsher o->config_rx_mode = bnx2x_set_rx_mode_e1x; 2338adfc5217SJeff Kirsher } else { 2339adfc5217SJeff Kirsher o->wait_comp = bnx2x_wait_rx_mode_comp_e2; 2340adfc5217SJeff Kirsher o->config_rx_mode = bnx2x_set_rx_mode_e2; 2341adfc5217SJeff Kirsher } 2342adfc5217SJeff Kirsher } 2343adfc5217SJeff Kirsher 2344adfc5217SJeff Kirsher /********************* Multicast verbs: SET, CLEAR ****************************/ 2345adfc5217SJeff Kirsher static inline u8 bnx2x_mcast_bin_from_mac(u8 *mac) 2346adfc5217SJeff Kirsher { 2347adfc5217SJeff Kirsher return (crc32c_le(0, mac, ETH_ALEN) >> 24) & 0xff; 2348adfc5217SJeff Kirsher } 2349adfc5217SJeff Kirsher 2350adfc5217SJeff Kirsher struct bnx2x_mcast_mac_elem { 2351adfc5217SJeff Kirsher struct list_head link; 2352adfc5217SJeff Kirsher u8 mac[ETH_ALEN]; 2353adfc5217SJeff Kirsher u8 pad[2]; /* For a natural alignment of the following buffer */ 2354adfc5217SJeff Kirsher }; 2355adfc5217SJeff Kirsher 2356adfc5217SJeff Kirsher struct bnx2x_pending_mcast_cmd { 2357adfc5217SJeff Kirsher struct list_head link; 2358adfc5217SJeff Kirsher int type; /* BNX2X_MCAST_CMD_X */ 2359adfc5217SJeff Kirsher union { 2360adfc5217SJeff Kirsher struct list_head macs_head; 2361adfc5217SJeff Kirsher u32 macs_num; /* Needed for DEL command */ 2362adfc5217SJeff Kirsher int next_bin; /* Needed for RESTORE flow with aprox match */ 2363adfc5217SJeff Kirsher } data; 2364adfc5217SJeff Kirsher 2365adfc5217SJeff Kirsher bool done; /* set to true, when the command has been handled, 2366adfc5217SJeff Kirsher * practically used in 57712 handling only, where one pending 2367adfc5217SJeff Kirsher * command may be handled in a few operations. As long as for 2368adfc5217SJeff Kirsher * other chips every operation handling is completed in a 2369adfc5217SJeff Kirsher * single ramrod, there is no need to utilize this field. 2370adfc5217SJeff Kirsher */ 2371adfc5217SJeff Kirsher }; 2372adfc5217SJeff Kirsher 2373adfc5217SJeff Kirsher static int bnx2x_mcast_wait(struct bnx2x *bp, 2374adfc5217SJeff Kirsher struct bnx2x_mcast_obj *o) 2375adfc5217SJeff Kirsher { 2376adfc5217SJeff Kirsher if (bnx2x_state_wait(bp, o->sched_state, o->raw.pstate) || 2377adfc5217SJeff Kirsher o->raw.wait_comp(bp, &o->raw)) 2378adfc5217SJeff Kirsher return -EBUSY; 2379adfc5217SJeff Kirsher 2380adfc5217SJeff Kirsher return 0; 2381adfc5217SJeff Kirsher } 2382adfc5217SJeff Kirsher 2383adfc5217SJeff Kirsher static int bnx2x_mcast_enqueue_cmd(struct bnx2x *bp, 2384adfc5217SJeff Kirsher struct bnx2x_mcast_obj *o, 2385adfc5217SJeff Kirsher struct bnx2x_mcast_ramrod_params *p, 238686564c3fSYuval Mintz enum bnx2x_mcast_cmd cmd) 2387adfc5217SJeff Kirsher { 2388adfc5217SJeff Kirsher int total_sz; 2389adfc5217SJeff Kirsher struct bnx2x_pending_mcast_cmd *new_cmd; 2390adfc5217SJeff Kirsher struct bnx2x_mcast_mac_elem *cur_mac = NULL; 2391adfc5217SJeff Kirsher struct bnx2x_mcast_list_elem *pos; 2392adfc5217SJeff Kirsher int macs_list_len = ((cmd == BNX2X_MCAST_CMD_ADD) ? 2393adfc5217SJeff Kirsher p->mcast_list_len : 0); 2394adfc5217SJeff Kirsher 2395adfc5217SJeff Kirsher /* If the command is empty ("handle pending commands only"), break */ 2396adfc5217SJeff Kirsher if (!p->mcast_list_len) 2397adfc5217SJeff Kirsher return 0; 2398adfc5217SJeff Kirsher 2399adfc5217SJeff Kirsher total_sz = sizeof(*new_cmd) + 2400adfc5217SJeff Kirsher macs_list_len * sizeof(struct bnx2x_mcast_mac_elem); 2401adfc5217SJeff Kirsher 2402adfc5217SJeff Kirsher /* Add mcast is called under spin_lock, thus calling with GFP_ATOMIC */ 2403adfc5217SJeff Kirsher new_cmd = kzalloc(total_sz, GFP_ATOMIC); 2404adfc5217SJeff Kirsher 2405adfc5217SJeff Kirsher if (!new_cmd) 2406adfc5217SJeff Kirsher return -ENOMEM; 2407adfc5217SJeff Kirsher 240851c1a580SMerav Sicron DP(BNX2X_MSG_SP, "About to enqueue a new %d command. macs_list_len=%d\n", 240951c1a580SMerav Sicron cmd, macs_list_len); 2410adfc5217SJeff Kirsher 2411adfc5217SJeff Kirsher INIT_LIST_HEAD(&new_cmd->data.macs_head); 2412adfc5217SJeff Kirsher 2413adfc5217SJeff Kirsher new_cmd->type = cmd; 2414adfc5217SJeff Kirsher new_cmd->done = false; 2415adfc5217SJeff Kirsher 2416adfc5217SJeff Kirsher switch (cmd) { 2417adfc5217SJeff Kirsher case BNX2X_MCAST_CMD_ADD: 2418adfc5217SJeff Kirsher cur_mac = (struct bnx2x_mcast_mac_elem *) 2419adfc5217SJeff Kirsher ((u8 *)new_cmd + sizeof(*new_cmd)); 2420adfc5217SJeff Kirsher 242116a5fd92SYuval Mintz /* Push the MACs of the current command into the pending command 2422adfc5217SJeff Kirsher * MACs list: FIFO 2423adfc5217SJeff Kirsher */ 2424adfc5217SJeff Kirsher list_for_each_entry(pos, &p->mcast_list, link) { 2425adfc5217SJeff Kirsher memcpy(cur_mac->mac, pos->mac, ETH_ALEN); 2426adfc5217SJeff Kirsher list_add_tail(&cur_mac->link, &new_cmd->data.macs_head); 2427adfc5217SJeff Kirsher cur_mac++; 2428adfc5217SJeff Kirsher } 2429adfc5217SJeff Kirsher 2430adfc5217SJeff Kirsher break; 2431adfc5217SJeff Kirsher 2432adfc5217SJeff Kirsher case BNX2X_MCAST_CMD_DEL: 2433adfc5217SJeff Kirsher new_cmd->data.macs_num = p->mcast_list_len; 2434adfc5217SJeff Kirsher break; 2435adfc5217SJeff Kirsher 2436adfc5217SJeff Kirsher case BNX2X_MCAST_CMD_RESTORE: 2437adfc5217SJeff Kirsher new_cmd->data.next_bin = 0; 2438adfc5217SJeff Kirsher break; 2439adfc5217SJeff Kirsher 2440adfc5217SJeff Kirsher default: 24418b6d5c09SJesper Juhl kfree(new_cmd); 2442adfc5217SJeff Kirsher BNX2X_ERR("Unknown command: %d\n", cmd); 2443adfc5217SJeff Kirsher return -EINVAL; 2444adfc5217SJeff Kirsher } 2445adfc5217SJeff Kirsher 2446adfc5217SJeff Kirsher /* Push the new pending command to the tail of the pending list: FIFO */ 2447adfc5217SJeff Kirsher list_add_tail(&new_cmd->link, &o->pending_cmds_head); 2448adfc5217SJeff Kirsher 2449adfc5217SJeff Kirsher o->set_sched(o); 2450adfc5217SJeff Kirsher 2451adfc5217SJeff Kirsher return 1; 2452adfc5217SJeff Kirsher } 2453adfc5217SJeff Kirsher 2454adfc5217SJeff Kirsher /** 2455adfc5217SJeff Kirsher * bnx2x_mcast_get_next_bin - get the next set bin (index) 2456adfc5217SJeff Kirsher * 2457adfc5217SJeff Kirsher * @o: 2458adfc5217SJeff Kirsher * @last: index to start looking from (including) 2459adfc5217SJeff Kirsher * 2460adfc5217SJeff Kirsher * returns the next found (set) bin or a negative value if none is found. 2461adfc5217SJeff Kirsher */ 2462adfc5217SJeff Kirsher static inline int bnx2x_mcast_get_next_bin(struct bnx2x_mcast_obj *o, int last) 2463adfc5217SJeff Kirsher { 2464adfc5217SJeff Kirsher int i, j, inner_start = last % BIT_VEC64_ELEM_SZ; 2465adfc5217SJeff Kirsher 2466adfc5217SJeff Kirsher for (i = last / BIT_VEC64_ELEM_SZ; i < BNX2X_MCAST_VEC_SZ; i++) { 2467adfc5217SJeff Kirsher if (o->registry.aprox_match.vec[i]) 2468adfc5217SJeff Kirsher for (j = inner_start; j < BIT_VEC64_ELEM_SZ; j++) { 2469adfc5217SJeff Kirsher int cur_bit = j + BIT_VEC64_ELEM_SZ * i; 2470adfc5217SJeff Kirsher if (BIT_VEC64_TEST_BIT(o->registry.aprox_match. 2471adfc5217SJeff Kirsher vec, cur_bit)) { 2472adfc5217SJeff Kirsher return cur_bit; 2473adfc5217SJeff Kirsher } 2474adfc5217SJeff Kirsher } 2475adfc5217SJeff Kirsher inner_start = 0; 2476adfc5217SJeff Kirsher } 2477adfc5217SJeff Kirsher 2478adfc5217SJeff Kirsher /* None found */ 2479adfc5217SJeff Kirsher return -1; 2480adfc5217SJeff Kirsher } 2481adfc5217SJeff Kirsher 2482adfc5217SJeff Kirsher /** 2483adfc5217SJeff Kirsher * bnx2x_mcast_clear_first_bin - find the first set bin and clear it 2484adfc5217SJeff Kirsher * 2485adfc5217SJeff Kirsher * @o: 2486adfc5217SJeff Kirsher * 2487adfc5217SJeff Kirsher * returns the index of the found bin or -1 if none is found 2488adfc5217SJeff Kirsher */ 2489adfc5217SJeff Kirsher static inline int bnx2x_mcast_clear_first_bin(struct bnx2x_mcast_obj *o) 2490adfc5217SJeff Kirsher { 2491adfc5217SJeff Kirsher int cur_bit = bnx2x_mcast_get_next_bin(o, 0); 2492adfc5217SJeff Kirsher 2493adfc5217SJeff Kirsher if (cur_bit >= 0) 2494adfc5217SJeff Kirsher BIT_VEC64_CLEAR_BIT(o->registry.aprox_match.vec, cur_bit); 2495adfc5217SJeff Kirsher 2496adfc5217SJeff Kirsher return cur_bit; 2497adfc5217SJeff Kirsher } 2498adfc5217SJeff Kirsher 2499adfc5217SJeff Kirsher static inline u8 bnx2x_mcast_get_rx_tx_flag(struct bnx2x_mcast_obj *o) 2500adfc5217SJeff Kirsher { 2501adfc5217SJeff Kirsher struct bnx2x_raw_obj *raw = &o->raw; 2502adfc5217SJeff Kirsher u8 rx_tx_flag = 0; 2503adfc5217SJeff Kirsher 2504adfc5217SJeff Kirsher if ((raw->obj_type == BNX2X_OBJ_TYPE_TX) || 2505adfc5217SJeff Kirsher (raw->obj_type == BNX2X_OBJ_TYPE_RX_TX)) 2506adfc5217SJeff Kirsher rx_tx_flag |= ETH_MULTICAST_RULES_CMD_TX_CMD; 2507adfc5217SJeff Kirsher 2508adfc5217SJeff Kirsher if ((raw->obj_type == BNX2X_OBJ_TYPE_RX) || 2509adfc5217SJeff Kirsher (raw->obj_type == BNX2X_OBJ_TYPE_RX_TX)) 2510adfc5217SJeff Kirsher rx_tx_flag |= ETH_MULTICAST_RULES_CMD_RX_CMD; 2511adfc5217SJeff Kirsher 2512adfc5217SJeff Kirsher return rx_tx_flag; 2513adfc5217SJeff Kirsher } 2514adfc5217SJeff Kirsher 2515adfc5217SJeff Kirsher static void bnx2x_mcast_set_one_rule_e2(struct bnx2x *bp, 2516adfc5217SJeff Kirsher struct bnx2x_mcast_obj *o, int idx, 2517adfc5217SJeff Kirsher union bnx2x_mcast_config_data *cfg_data, 251886564c3fSYuval Mintz enum bnx2x_mcast_cmd cmd) 2519adfc5217SJeff Kirsher { 2520adfc5217SJeff Kirsher struct bnx2x_raw_obj *r = &o->raw; 2521adfc5217SJeff Kirsher struct eth_multicast_rules_ramrod_data *data = 2522adfc5217SJeff Kirsher (struct eth_multicast_rules_ramrod_data *)(r->rdata); 2523adfc5217SJeff Kirsher u8 func_id = r->func_id; 2524adfc5217SJeff Kirsher u8 rx_tx_add_flag = bnx2x_mcast_get_rx_tx_flag(o); 2525adfc5217SJeff Kirsher int bin; 2526adfc5217SJeff Kirsher 2527adfc5217SJeff Kirsher if ((cmd == BNX2X_MCAST_CMD_ADD) || (cmd == BNX2X_MCAST_CMD_RESTORE)) 2528adfc5217SJeff Kirsher rx_tx_add_flag |= ETH_MULTICAST_RULES_CMD_IS_ADD; 2529adfc5217SJeff Kirsher 2530adfc5217SJeff Kirsher data->rules[idx].cmd_general_data |= rx_tx_add_flag; 2531adfc5217SJeff Kirsher 2532adfc5217SJeff Kirsher /* Get a bin and update a bins' vector */ 2533adfc5217SJeff Kirsher switch (cmd) { 2534adfc5217SJeff Kirsher case BNX2X_MCAST_CMD_ADD: 2535adfc5217SJeff Kirsher bin = bnx2x_mcast_bin_from_mac(cfg_data->mac); 2536adfc5217SJeff Kirsher BIT_VEC64_SET_BIT(o->registry.aprox_match.vec, bin); 2537adfc5217SJeff Kirsher break; 2538adfc5217SJeff Kirsher 2539adfc5217SJeff Kirsher case BNX2X_MCAST_CMD_DEL: 2540adfc5217SJeff Kirsher /* If there were no more bins to clear 2541adfc5217SJeff Kirsher * (bnx2x_mcast_clear_first_bin() returns -1) then we would 2542adfc5217SJeff Kirsher * clear any (0xff) bin. 2543adfc5217SJeff Kirsher * See bnx2x_mcast_validate_e2() for explanation when it may 2544adfc5217SJeff Kirsher * happen. 2545adfc5217SJeff Kirsher */ 2546adfc5217SJeff Kirsher bin = bnx2x_mcast_clear_first_bin(o); 2547adfc5217SJeff Kirsher break; 2548adfc5217SJeff Kirsher 2549adfc5217SJeff Kirsher case BNX2X_MCAST_CMD_RESTORE: 2550adfc5217SJeff Kirsher bin = cfg_data->bin; 2551adfc5217SJeff Kirsher break; 2552adfc5217SJeff Kirsher 2553adfc5217SJeff Kirsher default: 2554adfc5217SJeff Kirsher BNX2X_ERR("Unknown command: %d\n", cmd); 2555adfc5217SJeff Kirsher return; 2556adfc5217SJeff Kirsher } 2557adfc5217SJeff Kirsher 2558adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "%s bin %d\n", 2559adfc5217SJeff Kirsher ((rx_tx_add_flag & ETH_MULTICAST_RULES_CMD_IS_ADD) ? 2560adfc5217SJeff Kirsher "Setting" : "Clearing"), bin); 2561adfc5217SJeff Kirsher 2562adfc5217SJeff Kirsher data->rules[idx].bin_id = (u8)bin; 2563adfc5217SJeff Kirsher data->rules[idx].func_id = func_id; 2564adfc5217SJeff Kirsher data->rules[idx].engine_id = o->engine_id; 2565adfc5217SJeff Kirsher } 2566adfc5217SJeff Kirsher 2567adfc5217SJeff Kirsher /** 2568adfc5217SJeff Kirsher * bnx2x_mcast_handle_restore_cmd_e2 - restore configuration from the registry 2569adfc5217SJeff Kirsher * 2570adfc5217SJeff Kirsher * @bp: device handle 2571adfc5217SJeff Kirsher * @o: 2572adfc5217SJeff Kirsher * @start_bin: index in the registry to start from (including) 2573adfc5217SJeff Kirsher * @rdata_idx: index in the ramrod data to start from 2574adfc5217SJeff Kirsher * 2575adfc5217SJeff Kirsher * returns last handled bin index or -1 if all bins have been handled 2576adfc5217SJeff Kirsher */ 2577adfc5217SJeff Kirsher static inline int bnx2x_mcast_handle_restore_cmd_e2( 2578adfc5217SJeff Kirsher struct bnx2x *bp, struct bnx2x_mcast_obj *o , int start_bin, 2579adfc5217SJeff Kirsher int *rdata_idx) 2580adfc5217SJeff Kirsher { 2581adfc5217SJeff Kirsher int cur_bin, cnt = *rdata_idx; 258286564c3fSYuval Mintz union bnx2x_mcast_config_data cfg_data = {NULL}; 2583adfc5217SJeff Kirsher 2584adfc5217SJeff Kirsher /* go through the registry and configure the bins from it */ 2585adfc5217SJeff Kirsher for (cur_bin = bnx2x_mcast_get_next_bin(o, start_bin); cur_bin >= 0; 2586adfc5217SJeff Kirsher cur_bin = bnx2x_mcast_get_next_bin(o, cur_bin + 1)) { 2587adfc5217SJeff Kirsher 2588adfc5217SJeff Kirsher cfg_data.bin = (u8)cur_bin; 2589adfc5217SJeff Kirsher o->set_one_rule(bp, o, cnt, &cfg_data, 2590adfc5217SJeff Kirsher BNX2X_MCAST_CMD_RESTORE); 2591adfc5217SJeff Kirsher 2592adfc5217SJeff Kirsher cnt++; 2593adfc5217SJeff Kirsher 2594adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "About to configure a bin %d\n", cur_bin); 2595adfc5217SJeff Kirsher 2596adfc5217SJeff Kirsher /* Break if we reached the maximum number 2597adfc5217SJeff Kirsher * of rules. 2598adfc5217SJeff Kirsher */ 2599adfc5217SJeff Kirsher if (cnt >= o->max_cmd_len) 2600adfc5217SJeff Kirsher break; 2601adfc5217SJeff Kirsher } 2602adfc5217SJeff Kirsher 2603adfc5217SJeff Kirsher *rdata_idx = cnt; 2604adfc5217SJeff Kirsher 2605adfc5217SJeff Kirsher return cur_bin; 2606adfc5217SJeff Kirsher } 2607adfc5217SJeff Kirsher 2608adfc5217SJeff Kirsher static inline void bnx2x_mcast_hdl_pending_add_e2(struct bnx2x *bp, 2609adfc5217SJeff Kirsher struct bnx2x_mcast_obj *o, struct bnx2x_pending_mcast_cmd *cmd_pos, 2610adfc5217SJeff Kirsher int *line_idx) 2611adfc5217SJeff Kirsher { 2612adfc5217SJeff Kirsher struct bnx2x_mcast_mac_elem *pmac_pos, *pmac_pos_n; 2613adfc5217SJeff Kirsher int cnt = *line_idx; 261486564c3fSYuval Mintz union bnx2x_mcast_config_data cfg_data = {NULL}; 2615adfc5217SJeff Kirsher 2616adfc5217SJeff Kirsher list_for_each_entry_safe(pmac_pos, pmac_pos_n, &cmd_pos->data.macs_head, 2617adfc5217SJeff Kirsher link) { 2618adfc5217SJeff Kirsher 2619adfc5217SJeff Kirsher cfg_data.mac = &pmac_pos->mac[0]; 2620adfc5217SJeff Kirsher o->set_one_rule(bp, o, cnt, &cfg_data, cmd_pos->type); 2621adfc5217SJeff Kirsher 2622adfc5217SJeff Kirsher cnt++; 2623adfc5217SJeff Kirsher 26240f9dad10SJoe Perches DP(BNX2X_MSG_SP, "About to configure %pM mcast MAC\n", 26250f9dad10SJoe Perches pmac_pos->mac); 2626adfc5217SJeff Kirsher 2627adfc5217SJeff Kirsher list_del(&pmac_pos->link); 2628adfc5217SJeff Kirsher 2629adfc5217SJeff Kirsher /* Break if we reached the maximum number 2630adfc5217SJeff Kirsher * of rules. 2631adfc5217SJeff Kirsher */ 2632adfc5217SJeff Kirsher if (cnt >= o->max_cmd_len) 2633adfc5217SJeff Kirsher break; 2634adfc5217SJeff Kirsher } 2635adfc5217SJeff Kirsher 2636adfc5217SJeff Kirsher *line_idx = cnt; 2637adfc5217SJeff Kirsher 2638adfc5217SJeff Kirsher /* if no more MACs to configure - we are done */ 2639adfc5217SJeff Kirsher if (list_empty(&cmd_pos->data.macs_head)) 2640adfc5217SJeff Kirsher cmd_pos->done = true; 2641adfc5217SJeff Kirsher } 2642adfc5217SJeff Kirsher 2643adfc5217SJeff Kirsher static inline void bnx2x_mcast_hdl_pending_del_e2(struct bnx2x *bp, 2644adfc5217SJeff Kirsher struct bnx2x_mcast_obj *o, struct bnx2x_pending_mcast_cmd *cmd_pos, 2645adfc5217SJeff Kirsher int *line_idx) 2646adfc5217SJeff Kirsher { 2647adfc5217SJeff Kirsher int cnt = *line_idx; 2648adfc5217SJeff Kirsher 2649adfc5217SJeff Kirsher while (cmd_pos->data.macs_num) { 2650adfc5217SJeff Kirsher o->set_one_rule(bp, o, cnt, NULL, cmd_pos->type); 2651adfc5217SJeff Kirsher 2652adfc5217SJeff Kirsher cnt++; 2653adfc5217SJeff Kirsher 2654adfc5217SJeff Kirsher cmd_pos->data.macs_num--; 2655adfc5217SJeff Kirsher 2656adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "Deleting MAC. %d left,cnt is %d\n", 2657adfc5217SJeff Kirsher cmd_pos->data.macs_num, cnt); 2658adfc5217SJeff Kirsher 2659adfc5217SJeff Kirsher /* Break if we reached the maximum 2660adfc5217SJeff Kirsher * number of rules. 2661adfc5217SJeff Kirsher */ 2662adfc5217SJeff Kirsher if (cnt >= o->max_cmd_len) 2663adfc5217SJeff Kirsher break; 2664adfc5217SJeff Kirsher } 2665adfc5217SJeff Kirsher 2666adfc5217SJeff Kirsher *line_idx = cnt; 2667adfc5217SJeff Kirsher 2668adfc5217SJeff Kirsher /* If we cleared all bins - we are done */ 2669adfc5217SJeff Kirsher if (!cmd_pos->data.macs_num) 2670adfc5217SJeff Kirsher cmd_pos->done = true; 2671adfc5217SJeff Kirsher } 2672adfc5217SJeff Kirsher 2673adfc5217SJeff Kirsher static inline void bnx2x_mcast_hdl_pending_restore_e2(struct bnx2x *bp, 2674adfc5217SJeff Kirsher struct bnx2x_mcast_obj *o, struct bnx2x_pending_mcast_cmd *cmd_pos, 2675adfc5217SJeff Kirsher int *line_idx) 2676adfc5217SJeff Kirsher { 2677adfc5217SJeff Kirsher cmd_pos->data.next_bin = o->hdl_restore(bp, o, cmd_pos->data.next_bin, 2678adfc5217SJeff Kirsher line_idx); 2679adfc5217SJeff Kirsher 2680adfc5217SJeff Kirsher if (cmd_pos->data.next_bin < 0) 2681adfc5217SJeff Kirsher /* If o->set_restore returned -1 we are done */ 2682adfc5217SJeff Kirsher cmd_pos->done = true; 2683adfc5217SJeff Kirsher else 2684adfc5217SJeff Kirsher /* Start from the next bin next time */ 2685adfc5217SJeff Kirsher cmd_pos->data.next_bin++; 2686adfc5217SJeff Kirsher } 2687adfc5217SJeff Kirsher 2688adfc5217SJeff Kirsher static inline int bnx2x_mcast_handle_pending_cmds_e2(struct bnx2x *bp, 2689adfc5217SJeff Kirsher struct bnx2x_mcast_ramrod_params *p) 2690adfc5217SJeff Kirsher { 2691adfc5217SJeff Kirsher struct bnx2x_pending_mcast_cmd *cmd_pos, *cmd_pos_n; 2692adfc5217SJeff Kirsher int cnt = 0; 2693adfc5217SJeff Kirsher struct bnx2x_mcast_obj *o = p->mcast_obj; 2694adfc5217SJeff Kirsher 2695adfc5217SJeff Kirsher list_for_each_entry_safe(cmd_pos, cmd_pos_n, &o->pending_cmds_head, 2696adfc5217SJeff Kirsher link) { 2697adfc5217SJeff Kirsher switch (cmd_pos->type) { 2698adfc5217SJeff Kirsher case BNX2X_MCAST_CMD_ADD: 2699adfc5217SJeff Kirsher bnx2x_mcast_hdl_pending_add_e2(bp, o, cmd_pos, &cnt); 2700adfc5217SJeff Kirsher break; 2701adfc5217SJeff Kirsher 2702adfc5217SJeff Kirsher case BNX2X_MCAST_CMD_DEL: 2703adfc5217SJeff Kirsher bnx2x_mcast_hdl_pending_del_e2(bp, o, cmd_pos, &cnt); 2704adfc5217SJeff Kirsher break; 2705adfc5217SJeff Kirsher 2706adfc5217SJeff Kirsher case BNX2X_MCAST_CMD_RESTORE: 2707adfc5217SJeff Kirsher bnx2x_mcast_hdl_pending_restore_e2(bp, o, cmd_pos, 2708adfc5217SJeff Kirsher &cnt); 2709adfc5217SJeff Kirsher break; 2710adfc5217SJeff Kirsher 2711adfc5217SJeff Kirsher default: 2712adfc5217SJeff Kirsher BNX2X_ERR("Unknown command: %d\n", cmd_pos->type); 2713adfc5217SJeff Kirsher return -EINVAL; 2714adfc5217SJeff Kirsher } 2715adfc5217SJeff Kirsher 2716adfc5217SJeff Kirsher /* If the command has been completed - remove it from the list 2717adfc5217SJeff Kirsher * and free the memory 2718adfc5217SJeff Kirsher */ 2719adfc5217SJeff Kirsher if (cmd_pos->done) { 2720adfc5217SJeff Kirsher list_del(&cmd_pos->link); 2721adfc5217SJeff Kirsher kfree(cmd_pos); 2722adfc5217SJeff Kirsher } 2723adfc5217SJeff Kirsher 2724adfc5217SJeff Kirsher /* Break if we reached the maximum number of rules */ 2725adfc5217SJeff Kirsher if (cnt >= o->max_cmd_len) 2726adfc5217SJeff Kirsher break; 2727adfc5217SJeff Kirsher } 2728adfc5217SJeff Kirsher 2729adfc5217SJeff Kirsher return cnt; 2730adfc5217SJeff Kirsher } 2731adfc5217SJeff Kirsher 2732adfc5217SJeff Kirsher static inline void bnx2x_mcast_hdl_add(struct bnx2x *bp, 2733adfc5217SJeff Kirsher struct bnx2x_mcast_obj *o, struct bnx2x_mcast_ramrod_params *p, 2734adfc5217SJeff Kirsher int *line_idx) 2735adfc5217SJeff Kirsher { 2736adfc5217SJeff Kirsher struct bnx2x_mcast_list_elem *mlist_pos; 273786564c3fSYuval Mintz union bnx2x_mcast_config_data cfg_data = {NULL}; 2738adfc5217SJeff Kirsher int cnt = *line_idx; 2739adfc5217SJeff Kirsher 2740adfc5217SJeff Kirsher list_for_each_entry(mlist_pos, &p->mcast_list, link) { 2741adfc5217SJeff Kirsher cfg_data.mac = mlist_pos->mac; 2742adfc5217SJeff Kirsher o->set_one_rule(bp, o, cnt, &cfg_data, BNX2X_MCAST_CMD_ADD); 2743adfc5217SJeff Kirsher 2744adfc5217SJeff Kirsher cnt++; 2745adfc5217SJeff Kirsher 27460f9dad10SJoe Perches DP(BNX2X_MSG_SP, "About to configure %pM mcast MAC\n", 27470f9dad10SJoe Perches mlist_pos->mac); 2748adfc5217SJeff Kirsher } 2749adfc5217SJeff Kirsher 2750adfc5217SJeff Kirsher *line_idx = cnt; 2751adfc5217SJeff Kirsher } 2752adfc5217SJeff Kirsher 2753adfc5217SJeff Kirsher static inline void bnx2x_mcast_hdl_del(struct bnx2x *bp, 2754adfc5217SJeff Kirsher struct bnx2x_mcast_obj *o, struct bnx2x_mcast_ramrod_params *p, 2755adfc5217SJeff Kirsher int *line_idx) 2756adfc5217SJeff Kirsher { 2757adfc5217SJeff Kirsher int cnt = *line_idx, i; 2758adfc5217SJeff Kirsher 2759adfc5217SJeff Kirsher for (i = 0; i < p->mcast_list_len; i++) { 2760adfc5217SJeff Kirsher o->set_one_rule(bp, o, cnt, NULL, BNX2X_MCAST_CMD_DEL); 2761adfc5217SJeff Kirsher 2762adfc5217SJeff Kirsher cnt++; 2763adfc5217SJeff Kirsher 2764adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "Deleting MAC. %d left\n", 2765adfc5217SJeff Kirsher p->mcast_list_len - i - 1); 2766adfc5217SJeff Kirsher } 2767adfc5217SJeff Kirsher 2768adfc5217SJeff Kirsher *line_idx = cnt; 2769adfc5217SJeff Kirsher } 2770adfc5217SJeff Kirsher 2771adfc5217SJeff Kirsher /** 2772adfc5217SJeff Kirsher * bnx2x_mcast_handle_current_cmd - 2773adfc5217SJeff Kirsher * 2774adfc5217SJeff Kirsher * @bp: device handle 2775adfc5217SJeff Kirsher * @p: 2776adfc5217SJeff Kirsher * @cmd: 2777adfc5217SJeff Kirsher * @start_cnt: first line in the ramrod data that may be used 2778adfc5217SJeff Kirsher * 2779adfc5217SJeff Kirsher * This function is called iff there is enough place for the current command in 2780adfc5217SJeff Kirsher * the ramrod data. 2781adfc5217SJeff Kirsher * Returns number of lines filled in the ramrod data in total. 2782adfc5217SJeff Kirsher */ 2783adfc5217SJeff Kirsher static inline int bnx2x_mcast_handle_current_cmd(struct bnx2x *bp, 278486564c3fSYuval Mintz struct bnx2x_mcast_ramrod_params *p, 278586564c3fSYuval Mintz enum bnx2x_mcast_cmd cmd, 2786adfc5217SJeff Kirsher int start_cnt) 2787adfc5217SJeff Kirsher { 2788adfc5217SJeff Kirsher struct bnx2x_mcast_obj *o = p->mcast_obj; 2789adfc5217SJeff Kirsher int cnt = start_cnt; 2790adfc5217SJeff Kirsher 2791adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "p->mcast_list_len=%d\n", p->mcast_list_len); 2792adfc5217SJeff Kirsher 2793adfc5217SJeff Kirsher switch (cmd) { 2794adfc5217SJeff Kirsher case BNX2X_MCAST_CMD_ADD: 2795adfc5217SJeff Kirsher bnx2x_mcast_hdl_add(bp, o, p, &cnt); 2796adfc5217SJeff Kirsher break; 2797adfc5217SJeff Kirsher 2798adfc5217SJeff Kirsher case BNX2X_MCAST_CMD_DEL: 2799adfc5217SJeff Kirsher bnx2x_mcast_hdl_del(bp, o, p, &cnt); 2800adfc5217SJeff Kirsher break; 2801adfc5217SJeff Kirsher 2802adfc5217SJeff Kirsher case BNX2X_MCAST_CMD_RESTORE: 2803adfc5217SJeff Kirsher o->hdl_restore(bp, o, 0, &cnt); 2804adfc5217SJeff Kirsher break; 2805adfc5217SJeff Kirsher 2806adfc5217SJeff Kirsher default: 2807adfc5217SJeff Kirsher BNX2X_ERR("Unknown command: %d\n", cmd); 2808adfc5217SJeff Kirsher return -EINVAL; 2809adfc5217SJeff Kirsher } 2810adfc5217SJeff Kirsher 2811adfc5217SJeff Kirsher /* The current command has been handled */ 2812adfc5217SJeff Kirsher p->mcast_list_len = 0; 2813adfc5217SJeff Kirsher 2814adfc5217SJeff Kirsher return cnt; 2815adfc5217SJeff Kirsher } 2816adfc5217SJeff Kirsher 2817adfc5217SJeff Kirsher static int bnx2x_mcast_validate_e2(struct bnx2x *bp, 2818adfc5217SJeff Kirsher struct bnx2x_mcast_ramrod_params *p, 281986564c3fSYuval Mintz enum bnx2x_mcast_cmd cmd) 2820adfc5217SJeff Kirsher { 2821adfc5217SJeff Kirsher struct bnx2x_mcast_obj *o = p->mcast_obj; 2822adfc5217SJeff Kirsher int reg_sz = o->get_registry_size(o); 2823adfc5217SJeff Kirsher 2824adfc5217SJeff Kirsher switch (cmd) { 2825adfc5217SJeff Kirsher /* DEL command deletes all currently configured MACs */ 2826adfc5217SJeff Kirsher case BNX2X_MCAST_CMD_DEL: 2827adfc5217SJeff Kirsher o->set_registry_size(o, 0); 2828adfc5217SJeff Kirsher /* Don't break */ 2829adfc5217SJeff Kirsher 2830adfc5217SJeff Kirsher /* RESTORE command will restore the entire multicast configuration */ 2831adfc5217SJeff Kirsher case BNX2X_MCAST_CMD_RESTORE: 2832adfc5217SJeff Kirsher /* Here we set the approximate amount of work to do, which in 2833adfc5217SJeff Kirsher * fact may be only less as some MACs in postponed ADD 2834adfc5217SJeff Kirsher * command(s) scheduled before this command may fall into 2835adfc5217SJeff Kirsher * the same bin and the actual number of bins set in the 2836adfc5217SJeff Kirsher * registry would be less than we estimated here. See 2837adfc5217SJeff Kirsher * bnx2x_mcast_set_one_rule_e2() for further details. 2838adfc5217SJeff Kirsher */ 2839adfc5217SJeff Kirsher p->mcast_list_len = reg_sz; 2840adfc5217SJeff Kirsher break; 2841adfc5217SJeff Kirsher 2842adfc5217SJeff Kirsher case BNX2X_MCAST_CMD_ADD: 2843adfc5217SJeff Kirsher case BNX2X_MCAST_CMD_CONT: 2844adfc5217SJeff Kirsher /* Here we assume that all new MACs will fall into new bins. 2845adfc5217SJeff Kirsher * However we will correct the real registry size after we 2846adfc5217SJeff Kirsher * handle all pending commands. 2847adfc5217SJeff Kirsher */ 2848adfc5217SJeff Kirsher o->set_registry_size(o, reg_sz + p->mcast_list_len); 2849adfc5217SJeff Kirsher break; 2850adfc5217SJeff Kirsher 2851adfc5217SJeff Kirsher default: 2852adfc5217SJeff Kirsher BNX2X_ERR("Unknown command: %d\n", cmd); 2853adfc5217SJeff Kirsher return -EINVAL; 2854adfc5217SJeff Kirsher } 2855adfc5217SJeff Kirsher 2856adfc5217SJeff Kirsher /* Increase the total number of MACs pending to be configured */ 2857adfc5217SJeff Kirsher o->total_pending_num += p->mcast_list_len; 2858adfc5217SJeff Kirsher 2859adfc5217SJeff Kirsher return 0; 2860adfc5217SJeff Kirsher } 2861adfc5217SJeff Kirsher 2862adfc5217SJeff Kirsher static void bnx2x_mcast_revert_e2(struct bnx2x *bp, 2863adfc5217SJeff Kirsher struct bnx2x_mcast_ramrod_params *p, 2864adfc5217SJeff Kirsher int old_num_bins) 2865adfc5217SJeff Kirsher { 2866adfc5217SJeff Kirsher struct bnx2x_mcast_obj *o = p->mcast_obj; 2867adfc5217SJeff Kirsher 2868adfc5217SJeff Kirsher o->set_registry_size(o, old_num_bins); 2869adfc5217SJeff Kirsher o->total_pending_num -= p->mcast_list_len; 2870adfc5217SJeff Kirsher } 2871adfc5217SJeff Kirsher 2872adfc5217SJeff Kirsher /** 2873adfc5217SJeff Kirsher * bnx2x_mcast_set_rdata_hdr_e2 - sets a header values 2874adfc5217SJeff Kirsher * 2875adfc5217SJeff Kirsher * @bp: device handle 2876adfc5217SJeff Kirsher * @p: 2877adfc5217SJeff Kirsher * @len: number of rules to handle 2878adfc5217SJeff Kirsher */ 2879adfc5217SJeff Kirsher static inline void bnx2x_mcast_set_rdata_hdr_e2(struct bnx2x *bp, 2880adfc5217SJeff Kirsher struct bnx2x_mcast_ramrod_params *p, 2881adfc5217SJeff Kirsher u8 len) 2882adfc5217SJeff Kirsher { 2883adfc5217SJeff Kirsher struct bnx2x_raw_obj *r = &p->mcast_obj->raw; 2884adfc5217SJeff Kirsher struct eth_multicast_rules_ramrod_data *data = 2885adfc5217SJeff Kirsher (struct eth_multicast_rules_ramrod_data *)(r->rdata); 2886adfc5217SJeff Kirsher 288786564c3fSYuval Mintz data->header.echo = cpu_to_le32((r->cid & BNX2X_SWCID_MASK) | 288886564c3fSYuval Mintz (BNX2X_FILTER_MCAST_PENDING << 288986564c3fSYuval Mintz BNX2X_SWCID_SHIFT)); 2890adfc5217SJeff Kirsher data->header.rule_cnt = len; 2891adfc5217SJeff Kirsher } 2892adfc5217SJeff Kirsher 2893adfc5217SJeff Kirsher /** 2894adfc5217SJeff Kirsher * bnx2x_mcast_refresh_registry_e2 - recalculate the actual number of set bins 2895adfc5217SJeff Kirsher * 2896adfc5217SJeff Kirsher * @bp: device handle 2897adfc5217SJeff Kirsher * @o: 2898adfc5217SJeff Kirsher * 2899adfc5217SJeff Kirsher * Recalculate the actual number of set bins in the registry using Brian 2900adfc5217SJeff Kirsher * Kernighan's algorithm: it's execution complexity is as a number of set bins. 2901adfc5217SJeff Kirsher * 2902adfc5217SJeff Kirsher * returns 0 for the compliance with bnx2x_mcast_refresh_registry_e1(). 2903adfc5217SJeff Kirsher */ 2904adfc5217SJeff Kirsher static inline int bnx2x_mcast_refresh_registry_e2(struct bnx2x *bp, 2905adfc5217SJeff Kirsher struct bnx2x_mcast_obj *o) 2906adfc5217SJeff Kirsher { 2907adfc5217SJeff Kirsher int i, cnt = 0; 2908adfc5217SJeff Kirsher u64 elem; 2909adfc5217SJeff Kirsher 2910adfc5217SJeff Kirsher for (i = 0; i < BNX2X_MCAST_VEC_SZ; i++) { 2911adfc5217SJeff Kirsher elem = o->registry.aprox_match.vec[i]; 2912adfc5217SJeff Kirsher for (; elem; cnt++) 2913adfc5217SJeff Kirsher elem &= elem - 1; 2914adfc5217SJeff Kirsher } 2915adfc5217SJeff Kirsher 2916adfc5217SJeff Kirsher o->set_registry_size(o, cnt); 2917adfc5217SJeff Kirsher 2918adfc5217SJeff Kirsher return 0; 2919adfc5217SJeff Kirsher } 2920adfc5217SJeff Kirsher 2921adfc5217SJeff Kirsher static int bnx2x_mcast_setup_e2(struct bnx2x *bp, 2922adfc5217SJeff Kirsher struct bnx2x_mcast_ramrod_params *p, 292386564c3fSYuval Mintz enum bnx2x_mcast_cmd cmd) 2924adfc5217SJeff Kirsher { 2925adfc5217SJeff Kirsher struct bnx2x_raw_obj *raw = &p->mcast_obj->raw; 2926adfc5217SJeff Kirsher struct bnx2x_mcast_obj *o = p->mcast_obj; 2927adfc5217SJeff Kirsher struct eth_multicast_rules_ramrod_data *data = 2928adfc5217SJeff Kirsher (struct eth_multicast_rules_ramrod_data *)(raw->rdata); 2929adfc5217SJeff Kirsher int cnt = 0, rc; 2930adfc5217SJeff Kirsher 2931adfc5217SJeff Kirsher /* Reset the ramrod data buffer */ 2932adfc5217SJeff Kirsher memset(data, 0, sizeof(*data)); 2933adfc5217SJeff Kirsher 2934adfc5217SJeff Kirsher cnt = bnx2x_mcast_handle_pending_cmds_e2(bp, p); 2935adfc5217SJeff Kirsher 2936adfc5217SJeff Kirsher /* If there are no more pending commands - clear SCHEDULED state */ 2937adfc5217SJeff Kirsher if (list_empty(&o->pending_cmds_head)) 2938adfc5217SJeff Kirsher o->clear_sched(o); 2939adfc5217SJeff Kirsher 2940adfc5217SJeff Kirsher /* The below may be true iff there was enough room in ramrod 2941adfc5217SJeff Kirsher * data for all pending commands and for the current 2942adfc5217SJeff Kirsher * command. Otherwise the current command would have been added 2943adfc5217SJeff Kirsher * to the pending commands and p->mcast_list_len would have been 2944adfc5217SJeff Kirsher * zeroed. 2945adfc5217SJeff Kirsher */ 2946adfc5217SJeff Kirsher if (p->mcast_list_len > 0) 2947adfc5217SJeff Kirsher cnt = bnx2x_mcast_handle_current_cmd(bp, p, cmd, cnt); 2948adfc5217SJeff Kirsher 2949adfc5217SJeff Kirsher /* We've pulled out some MACs - update the total number of 2950adfc5217SJeff Kirsher * outstanding. 2951adfc5217SJeff Kirsher */ 2952adfc5217SJeff Kirsher o->total_pending_num -= cnt; 2953adfc5217SJeff Kirsher 2954adfc5217SJeff Kirsher /* send a ramrod */ 2955adfc5217SJeff Kirsher WARN_ON(o->total_pending_num < 0); 2956adfc5217SJeff Kirsher WARN_ON(cnt > o->max_cmd_len); 2957adfc5217SJeff Kirsher 2958adfc5217SJeff Kirsher bnx2x_mcast_set_rdata_hdr_e2(bp, p, (u8)cnt); 2959adfc5217SJeff Kirsher 2960adfc5217SJeff Kirsher /* Update a registry size if there are no more pending operations. 2961adfc5217SJeff Kirsher * 2962adfc5217SJeff Kirsher * We don't want to change the value of the registry size if there are 2963adfc5217SJeff Kirsher * pending operations because we want it to always be equal to the 2964adfc5217SJeff Kirsher * exact or the approximate number (see bnx2x_mcast_validate_e2()) of 2965adfc5217SJeff Kirsher * set bins after the last requested operation in order to properly 2966adfc5217SJeff Kirsher * evaluate the size of the next DEL/RESTORE operation. 2967adfc5217SJeff Kirsher * 2968adfc5217SJeff Kirsher * Note that we update the registry itself during command(s) handling 2969adfc5217SJeff Kirsher * - see bnx2x_mcast_set_one_rule_e2(). That's because for 57712 we 2970adfc5217SJeff Kirsher * aggregate multiple commands (ADD/DEL/RESTORE) into one ramrod but 2971adfc5217SJeff Kirsher * with a limited amount of update commands (per MAC/bin) and we don't 2972adfc5217SJeff Kirsher * know in this scope what the actual state of bins configuration is 2973adfc5217SJeff Kirsher * going to be after this ramrod. 2974adfc5217SJeff Kirsher */ 2975adfc5217SJeff Kirsher if (!o->total_pending_num) 2976adfc5217SJeff Kirsher bnx2x_mcast_refresh_registry_e2(bp, o); 2977adfc5217SJeff Kirsher 297816a5fd92SYuval Mintz /* If CLEAR_ONLY was requested - don't send a ramrod and clear 2979adfc5217SJeff Kirsher * RAMROD_PENDING status immediately. 2980adfc5217SJeff Kirsher */ 2981adfc5217SJeff Kirsher if (test_bit(RAMROD_DRV_CLR_ONLY, &p->ramrod_flags)) { 2982adfc5217SJeff Kirsher raw->clear_pending(raw); 2983adfc5217SJeff Kirsher return 0; 2984adfc5217SJeff Kirsher } else { 298514a94ebdSMichal Kalderon /* No need for an explicit memory barrier here as long as we 298614a94ebdSMichal Kalderon * ensure the ordering of writing to the SPQ element 2987adfc5217SJeff Kirsher * and updating of the SPQ producer which involves a memory 298814a94ebdSMichal Kalderon * read. If the memory read is removed we will have to put a 298914a94ebdSMichal Kalderon * full memory barrier there (inside bnx2x_sp_post()). 2990adfc5217SJeff Kirsher */ 2991adfc5217SJeff Kirsher 2992adfc5217SJeff Kirsher /* Send a ramrod */ 2993adfc5217SJeff Kirsher rc = bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_MULTICAST_RULES, 2994adfc5217SJeff Kirsher raw->cid, U64_HI(raw->rdata_mapping), 2995adfc5217SJeff Kirsher U64_LO(raw->rdata_mapping), 2996adfc5217SJeff Kirsher ETH_CONNECTION_TYPE); 2997adfc5217SJeff Kirsher if (rc) 2998adfc5217SJeff Kirsher return rc; 2999adfc5217SJeff Kirsher 3000adfc5217SJeff Kirsher /* Ramrod completion is pending */ 3001adfc5217SJeff Kirsher return 1; 3002adfc5217SJeff Kirsher } 3003adfc5217SJeff Kirsher } 3004adfc5217SJeff Kirsher 3005adfc5217SJeff Kirsher static int bnx2x_mcast_validate_e1h(struct bnx2x *bp, 3006adfc5217SJeff Kirsher struct bnx2x_mcast_ramrod_params *p, 300786564c3fSYuval Mintz enum bnx2x_mcast_cmd cmd) 3008adfc5217SJeff Kirsher { 3009adfc5217SJeff Kirsher /* Mark, that there is a work to do */ 3010adfc5217SJeff Kirsher if ((cmd == BNX2X_MCAST_CMD_DEL) || (cmd == BNX2X_MCAST_CMD_RESTORE)) 3011adfc5217SJeff Kirsher p->mcast_list_len = 1; 3012adfc5217SJeff Kirsher 3013adfc5217SJeff Kirsher return 0; 3014adfc5217SJeff Kirsher } 3015adfc5217SJeff Kirsher 3016adfc5217SJeff Kirsher static void bnx2x_mcast_revert_e1h(struct bnx2x *bp, 3017adfc5217SJeff Kirsher struct bnx2x_mcast_ramrod_params *p, 3018adfc5217SJeff Kirsher int old_num_bins) 3019adfc5217SJeff Kirsher { 3020adfc5217SJeff Kirsher /* Do nothing */ 3021adfc5217SJeff Kirsher } 3022adfc5217SJeff Kirsher 3023adfc5217SJeff Kirsher #define BNX2X_57711_SET_MC_FILTER(filter, bit) \ 3024adfc5217SJeff Kirsher do { \ 3025adfc5217SJeff Kirsher (filter)[(bit) >> 5] |= (1 << ((bit) & 0x1f)); \ 3026adfc5217SJeff Kirsher } while (0) 3027adfc5217SJeff Kirsher 3028adfc5217SJeff Kirsher static inline void bnx2x_mcast_hdl_add_e1h(struct bnx2x *bp, 3029adfc5217SJeff Kirsher struct bnx2x_mcast_obj *o, 3030adfc5217SJeff Kirsher struct bnx2x_mcast_ramrod_params *p, 3031adfc5217SJeff Kirsher u32 *mc_filter) 3032adfc5217SJeff Kirsher { 3033adfc5217SJeff Kirsher struct bnx2x_mcast_list_elem *mlist_pos; 3034adfc5217SJeff Kirsher int bit; 3035adfc5217SJeff Kirsher 3036adfc5217SJeff Kirsher list_for_each_entry(mlist_pos, &p->mcast_list, link) { 3037adfc5217SJeff Kirsher bit = bnx2x_mcast_bin_from_mac(mlist_pos->mac); 3038adfc5217SJeff Kirsher BNX2X_57711_SET_MC_FILTER(mc_filter, bit); 3039adfc5217SJeff Kirsher 30400f9dad10SJoe Perches DP(BNX2X_MSG_SP, "About to configure %pM mcast MAC, bin %d\n", 30410f9dad10SJoe Perches mlist_pos->mac, bit); 3042adfc5217SJeff Kirsher 3043adfc5217SJeff Kirsher /* bookkeeping... */ 3044adfc5217SJeff Kirsher BIT_VEC64_SET_BIT(o->registry.aprox_match.vec, 3045adfc5217SJeff Kirsher bit); 3046adfc5217SJeff Kirsher } 3047adfc5217SJeff Kirsher } 3048adfc5217SJeff Kirsher 3049adfc5217SJeff Kirsher static inline void bnx2x_mcast_hdl_restore_e1h(struct bnx2x *bp, 3050adfc5217SJeff Kirsher struct bnx2x_mcast_obj *o, struct bnx2x_mcast_ramrod_params *p, 3051adfc5217SJeff Kirsher u32 *mc_filter) 3052adfc5217SJeff Kirsher { 3053adfc5217SJeff Kirsher int bit; 3054adfc5217SJeff Kirsher 3055adfc5217SJeff Kirsher for (bit = bnx2x_mcast_get_next_bin(o, 0); 3056adfc5217SJeff Kirsher bit >= 0; 3057adfc5217SJeff Kirsher bit = bnx2x_mcast_get_next_bin(o, bit + 1)) { 3058adfc5217SJeff Kirsher BNX2X_57711_SET_MC_FILTER(mc_filter, bit); 3059adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "About to set bin %d\n", bit); 3060adfc5217SJeff Kirsher } 3061adfc5217SJeff Kirsher } 3062adfc5217SJeff Kirsher 306316a5fd92SYuval Mintz /* On 57711 we write the multicast MACs' approximate match 3064adfc5217SJeff Kirsher * table by directly into the TSTORM's internal RAM. So we don't 3065adfc5217SJeff Kirsher * really need to handle any tricks to make it work. 3066adfc5217SJeff Kirsher */ 3067adfc5217SJeff Kirsher static int bnx2x_mcast_setup_e1h(struct bnx2x *bp, 3068adfc5217SJeff Kirsher struct bnx2x_mcast_ramrod_params *p, 306986564c3fSYuval Mintz enum bnx2x_mcast_cmd cmd) 3070adfc5217SJeff Kirsher { 3071adfc5217SJeff Kirsher int i; 3072adfc5217SJeff Kirsher struct bnx2x_mcast_obj *o = p->mcast_obj; 3073adfc5217SJeff Kirsher struct bnx2x_raw_obj *r = &o->raw; 3074adfc5217SJeff Kirsher 3075adfc5217SJeff Kirsher /* If CLEAR_ONLY has been requested - clear the registry 3076adfc5217SJeff Kirsher * and clear a pending bit. 3077adfc5217SJeff Kirsher */ 3078adfc5217SJeff Kirsher if (!test_bit(RAMROD_DRV_CLR_ONLY, &p->ramrod_flags)) { 3079adfc5217SJeff Kirsher u32 mc_filter[MC_HASH_SIZE] = {0}; 3080adfc5217SJeff Kirsher 3081adfc5217SJeff Kirsher /* Set the multicast filter bits before writing it into 3082adfc5217SJeff Kirsher * the internal memory. 3083adfc5217SJeff Kirsher */ 3084adfc5217SJeff Kirsher switch (cmd) { 3085adfc5217SJeff Kirsher case BNX2X_MCAST_CMD_ADD: 3086adfc5217SJeff Kirsher bnx2x_mcast_hdl_add_e1h(bp, o, p, mc_filter); 3087adfc5217SJeff Kirsher break; 3088adfc5217SJeff Kirsher 3089adfc5217SJeff Kirsher case BNX2X_MCAST_CMD_DEL: 309094f05b0fSJoe Perches DP(BNX2X_MSG_SP, 309194f05b0fSJoe Perches "Invalidating multicast MACs configuration\n"); 3092adfc5217SJeff Kirsher 3093adfc5217SJeff Kirsher /* clear the registry */ 3094adfc5217SJeff Kirsher memset(o->registry.aprox_match.vec, 0, 3095adfc5217SJeff Kirsher sizeof(o->registry.aprox_match.vec)); 3096adfc5217SJeff Kirsher break; 3097adfc5217SJeff Kirsher 3098adfc5217SJeff Kirsher case BNX2X_MCAST_CMD_RESTORE: 3099adfc5217SJeff Kirsher bnx2x_mcast_hdl_restore_e1h(bp, o, p, mc_filter); 3100adfc5217SJeff Kirsher break; 3101adfc5217SJeff Kirsher 3102adfc5217SJeff Kirsher default: 3103adfc5217SJeff Kirsher BNX2X_ERR("Unknown command: %d\n", cmd); 3104adfc5217SJeff Kirsher return -EINVAL; 3105adfc5217SJeff Kirsher } 3106adfc5217SJeff Kirsher 3107adfc5217SJeff Kirsher /* Set the mcast filter in the internal memory */ 3108adfc5217SJeff Kirsher for (i = 0; i < MC_HASH_SIZE; i++) 3109adfc5217SJeff Kirsher REG_WR(bp, MC_HASH_OFFSET(bp, i), mc_filter[i]); 3110adfc5217SJeff Kirsher } else 3111adfc5217SJeff Kirsher /* clear the registry */ 3112adfc5217SJeff Kirsher memset(o->registry.aprox_match.vec, 0, 3113adfc5217SJeff Kirsher sizeof(o->registry.aprox_match.vec)); 3114adfc5217SJeff Kirsher 3115adfc5217SJeff Kirsher /* We are done */ 3116adfc5217SJeff Kirsher r->clear_pending(r); 3117adfc5217SJeff Kirsher 3118adfc5217SJeff Kirsher return 0; 3119adfc5217SJeff Kirsher } 3120adfc5217SJeff Kirsher 3121adfc5217SJeff Kirsher static int bnx2x_mcast_validate_e1(struct bnx2x *bp, 3122adfc5217SJeff Kirsher struct bnx2x_mcast_ramrod_params *p, 312386564c3fSYuval Mintz enum bnx2x_mcast_cmd cmd) 3124adfc5217SJeff Kirsher { 3125adfc5217SJeff Kirsher struct bnx2x_mcast_obj *o = p->mcast_obj; 3126adfc5217SJeff Kirsher int reg_sz = o->get_registry_size(o); 3127adfc5217SJeff Kirsher 3128adfc5217SJeff Kirsher switch (cmd) { 3129adfc5217SJeff Kirsher /* DEL command deletes all currently configured MACs */ 3130adfc5217SJeff Kirsher case BNX2X_MCAST_CMD_DEL: 3131adfc5217SJeff Kirsher o->set_registry_size(o, 0); 3132adfc5217SJeff Kirsher /* Don't break */ 3133adfc5217SJeff Kirsher 3134adfc5217SJeff Kirsher /* RESTORE command will restore the entire multicast configuration */ 3135adfc5217SJeff Kirsher case BNX2X_MCAST_CMD_RESTORE: 3136adfc5217SJeff Kirsher p->mcast_list_len = reg_sz; 3137adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "Command %d, p->mcast_list_len=%d\n", 3138adfc5217SJeff Kirsher cmd, p->mcast_list_len); 3139adfc5217SJeff Kirsher break; 3140adfc5217SJeff Kirsher 3141adfc5217SJeff Kirsher case BNX2X_MCAST_CMD_ADD: 3142adfc5217SJeff Kirsher case BNX2X_MCAST_CMD_CONT: 3143adfc5217SJeff Kirsher /* Multicast MACs on 57710 are configured as unicast MACs and 3144adfc5217SJeff Kirsher * there is only a limited number of CAM entries for that 3145adfc5217SJeff Kirsher * matter. 3146adfc5217SJeff Kirsher */ 3147adfc5217SJeff Kirsher if (p->mcast_list_len > o->max_cmd_len) { 314851c1a580SMerav Sicron BNX2X_ERR("Can't configure more than %d multicast MACs on 57710\n", 314951c1a580SMerav Sicron o->max_cmd_len); 3150adfc5217SJeff Kirsher return -EINVAL; 3151adfc5217SJeff Kirsher } 3152adfc5217SJeff Kirsher /* Every configured MAC should be cleared if DEL command is 3153adfc5217SJeff Kirsher * called. Only the last ADD command is relevant as long as 3154adfc5217SJeff Kirsher * every ADD commands overrides the previous configuration. 3155adfc5217SJeff Kirsher */ 3156adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "p->mcast_list_len=%d\n", p->mcast_list_len); 3157adfc5217SJeff Kirsher if (p->mcast_list_len > 0) 3158adfc5217SJeff Kirsher o->set_registry_size(o, p->mcast_list_len); 3159adfc5217SJeff Kirsher 3160adfc5217SJeff Kirsher break; 3161adfc5217SJeff Kirsher 3162adfc5217SJeff Kirsher default: 3163adfc5217SJeff Kirsher BNX2X_ERR("Unknown command: %d\n", cmd); 3164adfc5217SJeff Kirsher return -EINVAL; 3165adfc5217SJeff Kirsher } 3166adfc5217SJeff Kirsher 3167adfc5217SJeff Kirsher /* We want to ensure that commands are executed one by one for 57710. 3168adfc5217SJeff Kirsher * Therefore each none-empty command will consume o->max_cmd_len. 3169adfc5217SJeff Kirsher */ 3170adfc5217SJeff Kirsher if (p->mcast_list_len) 3171adfc5217SJeff Kirsher o->total_pending_num += o->max_cmd_len; 3172adfc5217SJeff Kirsher 3173adfc5217SJeff Kirsher return 0; 3174adfc5217SJeff Kirsher } 3175adfc5217SJeff Kirsher 3176adfc5217SJeff Kirsher static void bnx2x_mcast_revert_e1(struct bnx2x *bp, 3177adfc5217SJeff Kirsher struct bnx2x_mcast_ramrod_params *p, 3178adfc5217SJeff Kirsher int old_num_macs) 3179adfc5217SJeff Kirsher { 3180adfc5217SJeff Kirsher struct bnx2x_mcast_obj *o = p->mcast_obj; 3181adfc5217SJeff Kirsher 3182adfc5217SJeff Kirsher o->set_registry_size(o, old_num_macs); 3183adfc5217SJeff Kirsher 3184adfc5217SJeff Kirsher /* If current command hasn't been handled yet and we are 3185adfc5217SJeff Kirsher * here means that it's meant to be dropped and we have to 318616a5fd92SYuval Mintz * update the number of outstanding MACs accordingly. 3187adfc5217SJeff Kirsher */ 3188adfc5217SJeff Kirsher if (p->mcast_list_len) 3189adfc5217SJeff Kirsher o->total_pending_num -= o->max_cmd_len; 3190adfc5217SJeff Kirsher } 3191adfc5217SJeff Kirsher 3192adfc5217SJeff Kirsher static void bnx2x_mcast_set_one_rule_e1(struct bnx2x *bp, 3193adfc5217SJeff Kirsher struct bnx2x_mcast_obj *o, int idx, 3194adfc5217SJeff Kirsher union bnx2x_mcast_config_data *cfg_data, 319586564c3fSYuval Mintz enum bnx2x_mcast_cmd cmd) 3196adfc5217SJeff Kirsher { 3197adfc5217SJeff Kirsher struct bnx2x_raw_obj *r = &o->raw; 3198adfc5217SJeff Kirsher struct mac_configuration_cmd *data = 3199adfc5217SJeff Kirsher (struct mac_configuration_cmd *)(r->rdata); 3200adfc5217SJeff Kirsher 3201adfc5217SJeff Kirsher /* copy mac */ 3202adfc5217SJeff Kirsher if ((cmd == BNX2X_MCAST_CMD_ADD) || (cmd == BNX2X_MCAST_CMD_RESTORE)) { 3203adfc5217SJeff Kirsher bnx2x_set_fw_mac_addr(&data->config_table[idx].msb_mac_addr, 3204adfc5217SJeff Kirsher &data->config_table[idx].middle_mac_addr, 3205adfc5217SJeff Kirsher &data->config_table[idx].lsb_mac_addr, 3206adfc5217SJeff Kirsher cfg_data->mac); 3207adfc5217SJeff Kirsher 3208adfc5217SJeff Kirsher data->config_table[idx].vlan_id = 0; 3209adfc5217SJeff Kirsher data->config_table[idx].pf_id = r->func_id; 3210adfc5217SJeff Kirsher data->config_table[idx].clients_bit_vector = 3211adfc5217SJeff Kirsher cpu_to_le32(1 << r->cl_id); 3212adfc5217SJeff Kirsher 3213adfc5217SJeff Kirsher SET_FLAG(data->config_table[idx].flags, 3214adfc5217SJeff Kirsher MAC_CONFIGURATION_ENTRY_ACTION_TYPE, 3215adfc5217SJeff Kirsher T_ETH_MAC_COMMAND_SET); 3216adfc5217SJeff Kirsher } 3217adfc5217SJeff Kirsher } 3218adfc5217SJeff Kirsher 3219adfc5217SJeff Kirsher /** 3220adfc5217SJeff Kirsher * bnx2x_mcast_set_rdata_hdr_e1 - set header values in mac_configuration_cmd 3221adfc5217SJeff Kirsher * 3222adfc5217SJeff Kirsher * @bp: device handle 3223adfc5217SJeff Kirsher * @p: 3224adfc5217SJeff Kirsher * @len: number of rules to handle 3225adfc5217SJeff Kirsher */ 3226adfc5217SJeff Kirsher static inline void bnx2x_mcast_set_rdata_hdr_e1(struct bnx2x *bp, 3227adfc5217SJeff Kirsher struct bnx2x_mcast_ramrod_params *p, 3228adfc5217SJeff Kirsher u8 len) 3229adfc5217SJeff Kirsher { 3230adfc5217SJeff Kirsher struct bnx2x_raw_obj *r = &p->mcast_obj->raw; 3231adfc5217SJeff Kirsher struct mac_configuration_cmd *data = 3232adfc5217SJeff Kirsher (struct mac_configuration_cmd *)(r->rdata); 3233adfc5217SJeff Kirsher 3234adfc5217SJeff Kirsher u8 offset = (CHIP_REV_IS_SLOW(bp) ? 3235adfc5217SJeff Kirsher BNX2X_MAX_EMUL_MULTI*(1 + r->func_id) : 3236adfc5217SJeff Kirsher BNX2X_MAX_MULTICAST*(1 + r->func_id)); 3237adfc5217SJeff Kirsher 3238adfc5217SJeff Kirsher data->hdr.offset = offset; 323986564c3fSYuval Mintz data->hdr.client_id = cpu_to_le16(0xff); 324086564c3fSYuval Mintz data->hdr.echo = cpu_to_le32((r->cid & BNX2X_SWCID_MASK) | 324186564c3fSYuval Mintz (BNX2X_FILTER_MCAST_PENDING << 324286564c3fSYuval Mintz BNX2X_SWCID_SHIFT)); 3243adfc5217SJeff Kirsher data->hdr.length = len; 3244adfc5217SJeff Kirsher } 3245adfc5217SJeff Kirsher 3246adfc5217SJeff Kirsher /** 3247adfc5217SJeff Kirsher * bnx2x_mcast_handle_restore_cmd_e1 - restore command for 57710 3248adfc5217SJeff Kirsher * 3249adfc5217SJeff Kirsher * @bp: device handle 3250adfc5217SJeff Kirsher * @o: 3251adfc5217SJeff Kirsher * @start_idx: index in the registry to start from 3252adfc5217SJeff Kirsher * @rdata_idx: index in the ramrod data to start from 3253adfc5217SJeff Kirsher * 3254adfc5217SJeff Kirsher * restore command for 57710 is like all other commands - always a stand alone 3255adfc5217SJeff Kirsher * command - start_idx and rdata_idx will always be 0. This function will always 3256adfc5217SJeff Kirsher * succeed. 3257adfc5217SJeff Kirsher * returns -1 to comply with 57712 variant. 3258adfc5217SJeff Kirsher */ 3259adfc5217SJeff Kirsher static inline int bnx2x_mcast_handle_restore_cmd_e1( 3260adfc5217SJeff Kirsher struct bnx2x *bp, struct bnx2x_mcast_obj *o , int start_idx, 3261adfc5217SJeff Kirsher int *rdata_idx) 3262adfc5217SJeff Kirsher { 3263adfc5217SJeff Kirsher struct bnx2x_mcast_mac_elem *elem; 3264adfc5217SJeff Kirsher int i = 0; 326586564c3fSYuval Mintz union bnx2x_mcast_config_data cfg_data = {NULL}; 3266adfc5217SJeff Kirsher 3267adfc5217SJeff Kirsher /* go through the registry and configure the MACs from it. */ 3268adfc5217SJeff Kirsher list_for_each_entry(elem, &o->registry.exact_match.macs, link) { 3269adfc5217SJeff Kirsher cfg_data.mac = &elem->mac[0]; 3270adfc5217SJeff Kirsher o->set_one_rule(bp, o, i, &cfg_data, BNX2X_MCAST_CMD_RESTORE); 3271adfc5217SJeff Kirsher 3272adfc5217SJeff Kirsher i++; 3273adfc5217SJeff Kirsher 32740f9dad10SJoe Perches DP(BNX2X_MSG_SP, "About to configure %pM mcast MAC\n", 32750f9dad10SJoe Perches cfg_data.mac); 3276adfc5217SJeff Kirsher } 3277adfc5217SJeff Kirsher 3278adfc5217SJeff Kirsher *rdata_idx = i; 3279adfc5217SJeff Kirsher 3280adfc5217SJeff Kirsher return -1; 3281adfc5217SJeff Kirsher } 3282adfc5217SJeff Kirsher 3283adfc5217SJeff Kirsher static inline int bnx2x_mcast_handle_pending_cmds_e1( 3284adfc5217SJeff Kirsher struct bnx2x *bp, struct bnx2x_mcast_ramrod_params *p) 3285adfc5217SJeff Kirsher { 3286adfc5217SJeff Kirsher struct bnx2x_pending_mcast_cmd *cmd_pos; 3287adfc5217SJeff Kirsher struct bnx2x_mcast_mac_elem *pmac_pos; 3288adfc5217SJeff Kirsher struct bnx2x_mcast_obj *o = p->mcast_obj; 328986564c3fSYuval Mintz union bnx2x_mcast_config_data cfg_data = {NULL}; 3290adfc5217SJeff Kirsher int cnt = 0; 3291adfc5217SJeff Kirsher 3292adfc5217SJeff Kirsher /* If nothing to be done - return */ 3293adfc5217SJeff Kirsher if (list_empty(&o->pending_cmds_head)) 3294adfc5217SJeff Kirsher return 0; 3295adfc5217SJeff Kirsher 3296adfc5217SJeff Kirsher /* Handle the first command */ 3297adfc5217SJeff Kirsher cmd_pos = list_first_entry(&o->pending_cmds_head, 3298adfc5217SJeff Kirsher struct bnx2x_pending_mcast_cmd, link); 3299adfc5217SJeff Kirsher 3300adfc5217SJeff Kirsher switch (cmd_pos->type) { 3301adfc5217SJeff Kirsher case BNX2X_MCAST_CMD_ADD: 3302adfc5217SJeff Kirsher list_for_each_entry(pmac_pos, &cmd_pos->data.macs_head, link) { 3303adfc5217SJeff Kirsher cfg_data.mac = &pmac_pos->mac[0]; 3304adfc5217SJeff Kirsher o->set_one_rule(bp, o, cnt, &cfg_data, cmd_pos->type); 3305adfc5217SJeff Kirsher 3306adfc5217SJeff Kirsher cnt++; 3307adfc5217SJeff Kirsher 33080f9dad10SJoe Perches DP(BNX2X_MSG_SP, "About to configure %pM mcast MAC\n", 33090f9dad10SJoe Perches pmac_pos->mac); 3310adfc5217SJeff Kirsher } 3311adfc5217SJeff Kirsher break; 3312adfc5217SJeff Kirsher 3313adfc5217SJeff Kirsher case BNX2X_MCAST_CMD_DEL: 3314adfc5217SJeff Kirsher cnt = cmd_pos->data.macs_num; 3315adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "About to delete %d multicast MACs\n", cnt); 3316adfc5217SJeff Kirsher break; 3317adfc5217SJeff Kirsher 3318adfc5217SJeff Kirsher case BNX2X_MCAST_CMD_RESTORE: 3319adfc5217SJeff Kirsher o->hdl_restore(bp, o, 0, &cnt); 3320adfc5217SJeff Kirsher break; 3321adfc5217SJeff Kirsher 3322adfc5217SJeff Kirsher default: 3323adfc5217SJeff Kirsher BNX2X_ERR("Unknown command: %d\n", cmd_pos->type); 3324adfc5217SJeff Kirsher return -EINVAL; 3325adfc5217SJeff Kirsher } 3326adfc5217SJeff Kirsher 3327adfc5217SJeff Kirsher list_del(&cmd_pos->link); 3328adfc5217SJeff Kirsher kfree(cmd_pos); 3329adfc5217SJeff Kirsher 3330adfc5217SJeff Kirsher return cnt; 3331adfc5217SJeff Kirsher } 3332adfc5217SJeff Kirsher 3333adfc5217SJeff Kirsher /** 3334adfc5217SJeff Kirsher * bnx2x_get_fw_mac_addr - revert the bnx2x_set_fw_mac_addr(). 3335adfc5217SJeff Kirsher * 3336adfc5217SJeff Kirsher * @fw_hi: 3337adfc5217SJeff Kirsher * @fw_mid: 3338adfc5217SJeff Kirsher * @fw_lo: 3339adfc5217SJeff Kirsher * @mac: 3340adfc5217SJeff Kirsher */ 3341adfc5217SJeff Kirsher static inline void bnx2x_get_fw_mac_addr(__le16 *fw_hi, __le16 *fw_mid, 3342adfc5217SJeff Kirsher __le16 *fw_lo, u8 *mac) 3343adfc5217SJeff Kirsher { 3344adfc5217SJeff Kirsher mac[1] = ((u8 *)fw_hi)[0]; 3345adfc5217SJeff Kirsher mac[0] = ((u8 *)fw_hi)[1]; 3346adfc5217SJeff Kirsher mac[3] = ((u8 *)fw_mid)[0]; 3347adfc5217SJeff Kirsher mac[2] = ((u8 *)fw_mid)[1]; 3348adfc5217SJeff Kirsher mac[5] = ((u8 *)fw_lo)[0]; 3349adfc5217SJeff Kirsher mac[4] = ((u8 *)fw_lo)[1]; 3350adfc5217SJeff Kirsher } 3351adfc5217SJeff Kirsher 3352adfc5217SJeff Kirsher /** 3353adfc5217SJeff Kirsher * bnx2x_mcast_refresh_registry_e1 - 3354adfc5217SJeff Kirsher * 3355adfc5217SJeff Kirsher * @bp: device handle 3356adfc5217SJeff Kirsher * @cnt: 3357adfc5217SJeff Kirsher * 3358adfc5217SJeff Kirsher * Check the ramrod data first entry flag to see if it's a DELETE or ADD command 3359adfc5217SJeff Kirsher * and update the registry correspondingly: if ADD - allocate a memory and add 3360adfc5217SJeff Kirsher * the entries to the registry (list), if DELETE - clear the registry and free 3361adfc5217SJeff Kirsher * the memory. 3362adfc5217SJeff Kirsher */ 3363adfc5217SJeff Kirsher static inline int bnx2x_mcast_refresh_registry_e1(struct bnx2x *bp, 3364adfc5217SJeff Kirsher struct bnx2x_mcast_obj *o) 3365adfc5217SJeff Kirsher { 3366adfc5217SJeff Kirsher struct bnx2x_raw_obj *raw = &o->raw; 3367adfc5217SJeff Kirsher struct bnx2x_mcast_mac_elem *elem; 3368adfc5217SJeff Kirsher struct mac_configuration_cmd *data = 3369adfc5217SJeff Kirsher (struct mac_configuration_cmd *)(raw->rdata); 3370adfc5217SJeff Kirsher 3371adfc5217SJeff Kirsher /* If first entry contains a SET bit - the command was ADD, 3372adfc5217SJeff Kirsher * otherwise - DEL_ALL 3373adfc5217SJeff Kirsher */ 3374adfc5217SJeff Kirsher if (GET_FLAG(data->config_table[0].flags, 3375adfc5217SJeff Kirsher MAC_CONFIGURATION_ENTRY_ACTION_TYPE)) { 3376adfc5217SJeff Kirsher int i, len = data->hdr.length; 3377adfc5217SJeff Kirsher 3378adfc5217SJeff Kirsher /* Break if it was a RESTORE command */ 3379adfc5217SJeff Kirsher if (!list_empty(&o->registry.exact_match.macs)) 3380adfc5217SJeff Kirsher return 0; 3381adfc5217SJeff Kirsher 338201e23742SThomas Meyer elem = kcalloc(len, sizeof(*elem), GFP_ATOMIC); 3383adfc5217SJeff Kirsher if (!elem) { 3384adfc5217SJeff Kirsher BNX2X_ERR("Failed to allocate registry memory\n"); 3385adfc5217SJeff Kirsher return -ENOMEM; 3386adfc5217SJeff Kirsher } 3387adfc5217SJeff Kirsher 3388adfc5217SJeff Kirsher for (i = 0; i < len; i++, elem++) { 3389adfc5217SJeff Kirsher bnx2x_get_fw_mac_addr( 3390adfc5217SJeff Kirsher &data->config_table[i].msb_mac_addr, 3391adfc5217SJeff Kirsher &data->config_table[i].middle_mac_addr, 3392adfc5217SJeff Kirsher &data->config_table[i].lsb_mac_addr, 3393adfc5217SJeff Kirsher elem->mac); 33940f9dad10SJoe Perches DP(BNX2X_MSG_SP, "Adding registry entry for [%pM]\n", 33950f9dad10SJoe Perches elem->mac); 3396adfc5217SJeff Kirsher list_add_tail(&elem->link, 3397adfc5217SJeff Kirsher &o->registry.exact_match.macs); 3398adfc5217SJeff Kirsher } 3399adfc5217SJeff Kirsher } else { 3400adfc5217SJeff Kirsher elem = list_first_entry(&o->registry.exact_match.macs, 3401adfc5217SJeff Kirsher struct bnx2x_mcast_mac_elem, link); 3402adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "Deleting a registry\n"); 3403adfc5217SJeff Kirsher kfree(elem); 3404adfc5217SJeff Kirsher INIT_LIST_HEAD(&o->registry.exact_match.macs); 3405adfc5217SJeff Kirsher } 3406adfc5217SJeff Kirsher 3407adfc5217SJeff Kirsher return 0; 3408adfc5217SJeff Kirsher } 3409adfc5217SJeff Kirsher 3410adfc5217SJeff Kirsher static int bnx2x_mcast_setup_e1(struct bnx2x *bp, 3411adfc5217SJeff Kirsher struct bnx2x_mcast_ramrod_params *p, 341286564c3fSYuval Mintz enum bnx2x_mcast_cmd cmd) 3413adfc5217SJeff Kirsher { 3414adfc5217SJeff Kirsher struct bnx2x_mcast_obj *o = p->mcast_obj; 3415adfc5217SJeff Kirsher struct bnx2x_raw_obj *raw = &o->raw; 3416adfc5217SJeff Kirsher struct mac_configuration_cmd *data = 3417adfc5217SJeff Kirsher (struct mac_configuration_cmd *)(raw->rdata); 3418adfc5217SJeff Kirsher int cnt = 0, i, rc; 3419adfc5217SJeff Kirsher 3420adfc5217SJeff Kirsher /* Reset the ramrod data buffer */ 3421adfc5217SJeff Kirsher memset(data, 0, sizeof(*data)); 3422adfc5217SJeff Kirsher 3423adfc5217SJeff Kirsher /* First set all entries as invalid */ 3424adfc5217SJeff Kirsher for (i = 0; i < o->max_cmd_len ; i++) 3425adfc5217SJeff Kirsher SET_FLAG(data->config_table[i].flags, 3426adfc5217SJeff Kirsher MAC_CONFIGURATION_ENTRY_ACTION_TYPE, 3427adfc5217SJeff Kirsher T_ETH_MAC_COMMAND_INVALIDATE); 3428adfc5217SJeff Kirsher 3429adfc5217SJeff Kirsher /* Handle pending commands first */ 3430adfc5217SJeff Kirsher cnt = bnx2x_mcast_handle_pending_cmds_e1(bp, p); 3431adfc5217SJeff Kirsher 3432adfc5217SJeff Kirsher /* If there are no more pending commands - clear SCHEDULED state */ 3433adfc5217SJeff Kirsher if (list_empty(&o->pending_cmds_head)) 3434adfc5217SJeff Kirsher o->clear_sched(o); 3435adfc5217SJeff Kirsher 3436adfc5217SJeff Kirsher /* The below may be true iff there were no pending commands */ 3437adfc5217SJeff Kirsher if (!cnt) 3438adfc5217SJeff Kirsher cnt = bnx2x_mcast_handle_current_cmd(bp, p, cmd, 0); 3439adfc5217SJeff Kirsher 3440adfc5217SJeff Kirsher /* For 57710 every command has o->max_cmd_len length to ensure that 3441adfc5217SJeff Kirsher * commands are done one at a time. 3442adfc5217SJeff Kirsher */ 3443adfc5217SJeff Kirsher o->total_pending_num -= o->max_cmd_len; 3444adfc5217SJeff Kirsher 3445adfc5217SJeff Kirsher /* send a ramrod */ 3446adfc5217SJeff Kirsher 3447adfc5217SJeff Kirsher WARN_ON(cnt > o->max_cmd_len); 3448adfc5217SJeff Kirsher 3449adfc5217SJeff Kirsher /* Set ramrod header (in particular, a number of entries to update) */ 3450adfc5217SJeff Kirsher bnx2x_mcast_set_rdata_hdr_e1(bp, p, (u8)cnt); 3451adfc5217SJeff Kirsher 3452adfc5217SJeff Kirsher /* update a registry: we need the registry contents to be always up 3453adfc5217SJeff Kirsher * to date in order to be able to execute a RESTORE opcode. Here 3454adfc5217SJeff Kirsher * we use the fact that for 57710 we sent one command at a time 3455adfc5217SJeff Kirsher * hence we may take the registry update out of the command handling 3456adfc5217SJeff Kirsher * and do it in a simpler way here. 3457adfc5217SJeff Kirsher */ 3458adfc5217SJeff Kirsher rc = bnx2x_mcast_refresh_registry_e1(bp, o); 3459adfc5217SJeff Kirsher if (rc) 3460adfc5217SJeff Kirsher return rc; 3461adfc5217SJeff Kirsher 346216a5fd92SYuval Mintz /* If CLEAR_ONLY was requested - don't send a ramrod and clear 3463adfc5217SJeff Kirsher * RAMROD_PENDING status immediately. 3464adfc5217SJeff Kirsher */ 3465adfc5217SJeff Kirsher if (test_bit(RAMROD_DRV_CLR_ONLY, &p->ramrod_flags)) { 3466adfc5217SJeff Kirsher raw->clear_pending(raw); 3467adfc5217SJeff Kirsher return 0; 3468adfc5217SJeff Kirsher } else { 346914a94ebdSMichal Kalderon /* No need for an explicit memory barrier here as long as we 347014a94ebdSMichal Kalderon * ensure the ordering of writing to the SPQ element 3471adfc5217SJeff Kirsher * and updating of the SPQ producer which involves a memory 347214a94ebdSMichal Kalderon * read. If the memory read is removed we will have to put a 347314a94ebdSMichal Kalderon * full memory barrier there (inside bnx2x_sp_post()). 3474adfc5217SJeff Kirsher */ 3475adfc5217SJeff Kirsher 3476adfc5217SJeff Kirsher /* Send a ramrod */ 3477adfc5217SJeff Kirsher rc = bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_SET_MAC, raw->cid, 3478adfc5217SJeff Kirsher U64_HI(raw->rdata_mapping), 3479adfc5217SJeff Kirsher U64_LO(raw->rdata_mapping), 3480adfc5217SJeff Kirsher ETH_CONNECTION_TYPE); 3481adfc5217SJeff Kirsher if (rc) 3482adfc5217SJeff Kirsher return rc; 3483adfc5217SJeff Kirsher 3484adfc5217SJeff Kirsher /* Ramrod completion is pending */ 3485adfc5217SJeff Kirsher return 1; 3486adfc5217SJeff Kirsher } 3487adfc5217SJeff Kirsher } 3488adfc5217SJeff Kirsher 3489adfc5217SJeff Kirsher static int bnx2x_mcast_get_registry_size_exact(struct bnx2x_mcast_obj *o) 3490adfc5217SJeff Kirsher { 3491adfc5217SJeff Kirsher return o->registry.exact_match.num_macs_set; 3492adfc5217SJeff Kirsher } 3493adfc5217SJeff Kirsher 3494adfc5217SJeff Kirsher static int bnx2x_mcast_get_registry_size_aprox(struct bnx2x_mcast_obj *o) 3495adfc5217SJeff Kirsher { 3496adfc5217SJeff Kirsher return o->registry.aprox_match.num_bins_set; 3497adfc5217SJeff Kirsher } 3498adfc5217SJeff Kirsher 3499adfc5217SJeff Kirsher static void bnx2x_mcast_set_registry_size_exact(struct bnx2x_mcast_obj *o, 3500adfc5217SJeff Kirsher int n) 3501adfc5217SJeff Kirsher { 3502adfc5217SJeff Kirsher o->registry.exact_match.num_macs_set = n; 3503adfc5217SJeff Kirsher } 3504adfc5217SJeff Kirsher 3505adfc5217SJeff Kirsher static void bnx2x_mcast_set_registry_size_aprox(struct bnx2x_mcast_obj *o, 3506adfc5217SJeff Kirsher int n) 3507adfc5217SJeff Kirsher { 3508adfc5217SJeff Kirsher o->registry.aprox_match.num_bins_set = n; 3509adfc5217SJeff Kirsher } 3510adfc5217SJeff Kirsher 3511adfc5217SJeff Kirsher int bnx2x_config_mcast(struct bnx2x *bp, 3512adfc5217SJeff Kirsher struct bnx2x_mcast_ramrod_params *p, 351386564c3fSYuval Mintz enum bnx2x_mcast_cmd cmd) 3514adfc5217SJeff Kirsher { 3515adfc5217SJeff Kirsher struct bnx2x_mcast_obj *o = p->mcast_obj; 3516adfc5217SJeff Kirsher struct bnx2x_raw_obj *r = &o->raw; 3517adfc5217SJeff Kirsher int rc = 0, old_reg_size; 3518adfc5217SJeff Kirsher 3519adfc5217SJeff Kirsher /* This is needed to recover number of currently configured mcast macs 3520adfc5217SJeff Kirsher * in case of failure. 3521adfc5217SJeff Kirsher */ 3522adfc5217SJeff Kirsher old_reg_size = o->get_registry_size(o); 3523adfc5217SJeff Kirsher 3524adfc5217SJeff Kirsher /* Do some calculations and checks */ 3525adfc5217SJeff Kirsher rc = o->validate(bp, p, cmd); 3526adfc5217SJeff Kirsher if (rc) 3527adfc5217SJeff Kirsher return rc; 3528adfc5217SJeff Kirsher 3529adfc5217SJeff Kirsher /* Return if there is no work to do */ 3530adfc5217SJeff Kirsher if ((!p->mcast_list_len) && (!o->check_sched(o))) 3531adfc5217SJeff Kirsher return 0; 3532adfc5217SJeff Kirsher 353351c1a580SMerav Sicron DP(BNX2X_MSG_SP, "o->total_pending_num=%d p->mcast_list_len=%d o->max_cmd_len=%d\n", 353451c1a580SMerav Sicron o->total_pending_num, p->mcast_list_len, o->max_cmd_len); 3535adfc5217SJeff Kirsher 3536adfc5217SJeff Kirsher /* Enqueue the current command to the pending list if we can't complete 3537adfc5217SJeff Kirsher * it in the current iteration 3538adfc5217SJeff Kirsher */ 3539adfc5217SJeff Kirsher if (r->check_pending(r) || 3540adfc5217SJeff Kirsher ((o->max_cmd_len > 0) && (o->total_pending_num > o->max_cmd_len))) { 3541adfc5217SJeff Kirsher rc = o->enqueue_cmd(bp, p->mcast_obj, p, cmd); 3542adfc5217SJeff Kirsher if (rc < 0) 3543adfc5217SJeff Kirsher goto error_exit1; 3544adfc5217SJeff Kirsher 3545adfc5217SJeff Kirsher /* As long as the current command is in a command list we 3546adfc5217SJeff Kirsher * don't need to handle it separately. 3547adfc5217SJeff Kirsher */ 3548adfc5217SJeff Kirsher p->mcast_list_len = 0; 3549adfc5217SJeff Kirsher } 3550adfc5217SJeff Kirsher 3551adfc5217SJeff Kirsher if (!r->check_pending(r)) { 3552adfc5217SJeff Kirsher 3553adfc5217SJeff Kirsher /* Set 'pending' state */ 3554adfc5217SJeff Kirsher r->set_pending(r); 3555adfc5217SJeff Kirsher 3556adfc5217SJeff Kirsher /* Configure the new classification in the chip */ 3557adfc5217SJeff Kirsher rc = o->config_mcast(bp, p, cmd); 3558adfc5217SJeff Kirsher if (rc < 0) 3559adfc5217SJeff Kirsher goto error_exit2; 3560adfc5217SJeff Kirsher 3561adfc5217SJeff Kirsher /* Wait for a ramrod completion if was requested */ 3562adfc5217SJeff Kirsher if (test_bit(RAMROD_COMP_WAIT, &p->ramrod_flags)) 3563adfc5217SJeff Kirsher rc = o->wait_comp(bp, o); 3564adfc5217SJeff Kirsher } 3565adfc5217SJeff Kirsher 3566adfc5217SJeff Kirsher return rc; 3567adfc5217SJeff Kirsher 3568adfc5217SJeff Kirsher error_exit2: 3569adfc5217SJeff Kirsher r->clear_pending(r); 3570adfc5217SJeff Kirsher 3571adfc5217SJeff Kirsher error_exit1: 3572adfc5217SJeff Kirsher o->revert(bp, p, old_reg_size); 3573adfc5217SJeff Kirsher 3574adfc5217SJeff Kirsher return rc; 3575adfc5217SJeff Kirsher } 3576adfc5217SJeff Kirsher 3577adfc5217SJeff Kirsher static void bnx2x_mcast_clear_sched(struct bnx2x_mcast_obj *o) 3578adfc5217SJeff Kirsher { 35794e857c58SPeter Zijlstra smp_mb__before_atomic(); 3580adfc5217SJeff Kirsher clear_bit(o->sched_state, o->raw.pstate); 35814e857c58SPeter Zijlstra smp_mb__after_atomic(); 3582adfc5217SJeff Kirsher } 3583adfc5217SJeff Kirsher 3584adfc5217SJeff Kirsher static void bnx2x_mcast_set_sched(struct bnx2x_mcast_obj *o) 3585adfc5217SJeff Kirsher { 35864e857c58SPeter Zijlstra smp_mb__before_atomic(); 3587adfc5217SJeff Kirsher set_bit(o->sched_state, o->raw.pstate); 35884e857c58SPeter Zijlstra smp_mb__after_atomic(); 3589adfc5217SJeff Kirsher } 3590adfc5217SJeff Kirsher 3591adfc5217SJeff Kirsher static bool bnx2x_mcast_check_sched(struct bnx2x_mcast_obj *o) 3592adfc5217SJeff Kirsher { 3593adfc5217SJeff Kirsher return !!test_bit(o->sched_state, o->raw.pstate); 3594adfc5217SJeff Kirsher } 3595adfc5217SJeff Kirsher 3596adfc5217SJeff Kirsher static bool bnx2x_mcast_check_pending(struct bnx2x_mcast_obj *o) 3597adfc5217SJeff Kirsher { 3598adfc5217SJeff Kirsher return o->raw.check_pending(&o->raw) || o->check_sched(o); 3599adfc5217SJeff Kirsher } 3600adfc5217SJeff Kirsher 3601adfc5217SJeff Kirsher void bnx2x_init_mcast_obj(struct bnx2x *bp, 3602adfc5217SJeff Kirsher struct bnx2x_mcast_obj *mcast_obj, 3603adfc5217SJeff Kirsher u8 mcast_cl_id, u32 mcast_cid, u8 func_id, 3604adfc5217SJeff Kirsher u8 engine_id, void *rdata, dma_addr_t rdata_mapping, 3605adfc5217SJeff Kirsher int state, unsigned long *pstate, bnx2x_obj_type type) 3606adfc5217SJeff Kirsher { 3607adfc5217SJeff Kirsher memset(mcast_obj, 0, sizeof(*mcast_obj)); 3608adfc5217SJeff Kirsher 3609adfc5217SJeff Kirsher bnx2x_init_raw_obj(&mcast_obj->raw, mcast_cl_id, mcast_cid, func_id, 3610adfc5217SJeff Kirsher rdata, rdata_mapping, state, pstate, type); 3611adfc5217SJeff Kirsher 3612adfc5217SJeff Kirsher mcast_obj->engine_id = engine_id; 3613adfc5217SJeff Kirsher 3614adfc5217SJeff Kirsher INIT_LIST_HEAD(&mcast_obj->pending_cmds_head); 3615adfc5217SJeff Kirsher 3616adfc5217SJeff Kirsher mcast_obj->sched_state = BNX2X_FILTER_MCAST_SCHED; 3617adfc5217SJeff Kirsher mcast_obj->check_sched = bnx2x_mcast_check_sched; 3618adfc5217SJeff Kirsher mcast_obj->set_sched = bnx2x_mcast_set_sched; 3619adfc5217SJeff Kirsher mcast_obj->clear_sched = bnx2x_mcast_clear_sched; 3620adfc5217SJeff Kirsher 3621adfc5217SJeff Kirsher if (CHIP_IS_E1(bp)) { 3622adfc5217SJeff Kirsher mcast_obj->config_mcast = bnx2x_mcast_setup_e1; 3623adfc5217SJeff Kirsher mcast_obj->enqueue_cmd = bnx2x_mcast_enqueue_cmd; 3624adfc5217SJeff Kirsher mcast_obj->hdl_restore = 3625adfc5217SJeff Kirsher bnx2x_mcast_handle_restore_cmd_e1; 3626adfc5217SJeff Kirsher mcast_obj->check_pending = bnx2x_mcast_check_pending; 3627adfc5217SJeff Kirsher 3628adfc5217SJeff Kirsher if (CHIP_REV_IS_SLOW(bp)) 3629adfc5217SJeff Kirsher mcast_obj->max_cmd_len = BNX2X_MAX_EMUL_MULTI; 3630adfc5217SJeff Kirsher else 3631adfc5217SJeff Kirsher mcast_obj->max_cmd_len = BNX2X_MAX_MULTICAST; 3632adfc5217SJeff Kirsher 3633adfc5217SJeff Kirsher mcast_obj->wait_comp = bnx2x_mcast_wait; 3634adfc5217SJeff Kirsher mcast_obj->set_one_rule = bnx2x_mcast_set_one_rule_e1; 3635adfc5217SJeff Kirsher mcast_obj->validate = bnx2x_mcast_validate_e1; 3636adfc5217SJeff Kirsher mcast_obj->revert = bnx2x_mcast_revert_e1; 3637adfc5217SJeff Kirsher mcast_obj->get_registry_size = 3638adfc5217SJeff Kirsher bnx2x_mcast_get_registry_size_exact; 3639adfc5217SJeff Kirsher mcast_obj->set_registry_size = 3640adfc5217SJeff Kirsher bnx2x_mcast_set_registry_size_exact; 3641adfc5217SJeff Kirsher 3642adfc5217SJeff Kirsher /* 57710 is the only chip that uses the exact match for mcast 3643adfc5217SJeff Kirsher * at the moment. 3644adfc5217SJeff Kirsher */ 3645adfc5217SJeff Kirsher INIT_LIST_HEAD(&mcast_obj->registry.exact_match.macs); 3646adfc5217SJeff Kirsher 3647adfc5217SJeff Kirsher } else if (CHIP_IS_E1H(bp)) { 3648adfc5217SJeff Kirsher mcast_obj->config_mcast = bnx2x_mcast_setup_e1h; 3649adfc5217SJeff Kirsher mcast_obj->enqueue_cmd = NULL; 3650adfc5217SJeff Kirsher mcast_obj->hdl_restore = NULL; 3651adfc5217SJeff Kirsher mcast_obj->check_pending = bnx2x_mcast_check_pending; 3652adfc5217SJeff Kirsher 3653adfc5217SJeff Kirsher /* 57711 doesn't send a ramrod, so it has unlimited credit 3654adfc5217SJeff Kirsher * for one command. 3655adfc5217SJeff Kirsher */ 3656adfc5217SJeff Kirsher mcast_obj->max_cmd_len = -1; 3657adfc5217SJeff Kirsher mcast_obj->wait_comp = bnx2x_mcast_wait; 3658adfc5217SJeff Kirsher mcast_obj->set_one_rule = NULL; 3659adfc5217SJeff Kirsher mcast_obj->validate = bnx2x_mcast_validate_e1h; 3660adfc5217SJeff Kirsher mcast_obj->revert = bnx2x_mcast_revert_e1h; 3661adfc5217SJeff Kirsher mcast_obj->get_registry_size = 3662adfc5217SJeff Kirsher bnx2x_mcast_get_registry_size_aprox; 3663adfc5217SJeff Kirsher mcast_obj->set_registry_size = 3664adfc5217SJeff Kirsher bnx2x_mcast_set_registry_size_aprox; 3665adfc5217SJeff Kirsher } else { 3666adfc5217SJeff Kirsher mcast_obj->config_mcast = bnx2x_mcast_setup_e2; 3667adfc5217SJeff Kirsher mcast_obj->enqueue_cmd = bnx2x_mcast_enqueue_cmd; 3668adfc5217SJeff Kirsher mcast_obj->hdl_restore = 3669adfc5217SJeff Kirsher bnx2x_mcast_handle_restore_cmd_e2; 3670adfc5217SJeff Kirsher mcast_obj->check_pending = bnx2x_mcast_check_pending; 3671adfc5217SJeff Kirsher /* TODO: There should be a proper HSI define for this number!!! 3672adfc5217SJeff Kirsher */ 3673adfc5217SJeff Kirsher mcast_obj->max_cmd_len = 16; 3674adfc5217SJeff Kirsher mcast_obj->wait_comp = bnx2x_mcast_wait; 3675adfc5217SJeff Kirsher mcast_obj->set_one_rule = bnx2x_mcast_set_one_rule_e2; 3676adfc5217SJeff Kirsher mcast_obj->validate = bnx2x_mcast_validate_e2; 3677adfc5217SJeff Kirsher mcast_obj->revert = bnx2x_mcast_revert_e2; 3678adfc5217SJeff Kirsher mcast_obj->get_registry_size = 3679adfc5217SJeff Kirsher bnx2x_mcast_get_registry_size_aprox; 3680adfc5217SJeff Kirsher mcast_obj->set_registry_size = 3681adfc5217SJeff Kirsher bnx2x_mcast_set_registry_size_aprox; 3682adfc5217SJeff Kirsher } 3683adfc5217SJeff Kirsher } 3684adfc5217SJeff Kirsher 3685adfc5217SJeff Kirsher /*************************** Credit handling **********************************/ 3686adfc5217SJeff Kirsher 3687adfc5217SJeff Kirsher /** 3688adfc5217SJeff Kirsher * atomic_add_ifless - add if the result is less than a given value. 3689adfc5217SJeff Kirsher * 3690adfc5217SJeff Kirsher * @v: pointer of type atomic_t 3691adfc5217SJeff Kirsher * @a: the amount to add to v... 3692adfc5217SJeff Kirsher * @u: ...if (v + a) is less than u. 3693adfc5217SJeff Kirsher * 3694adfc5217SJeff Kirsher * returns true if (v + a) was less than u, and false otherwise. 3695adfc5217SJeff Kirsher * 3696adfc5217SJeff Kirsher */ 3697adfc5217SJeff Kirsher static inline bool __atomic_add_ifless(atomic_t *v, int a, int u) 3698adfc5217SJeff Kirsher { 3699adfc5217SJeff Kirsher int c, old; 3700adfc5217SJeff Kirsher 3701adfc5217SJeff Kirsher c = atomic_read(v); 3702adfc5217SJeff Kirsher for (;;) { 3703adfc5217SJeff Kirsher if (unlikely(c + a >= u)) 3704adfc5217SJeff Kirsher return false; 3705adfc5217SJeff Kirsher 3706adfc5217SJeff Kirsher old = atomic_cmpxchg((v), c, c + a); 3707adfc5217SJeff Kirsher if (likely(old == c)) 3708adfc5217SJeff Kirsher break; 3709adfc5217SJeff Kirsher c = old; 3710adfc5217SJeff Kirsher } 3711adfc5217SJeff Kirsher 3712adfc5217SJeff Kirsher return true; 3713adfc5217SJeff Kirsher } 3714adfc5217SJeff Kirsher 3715adfc5217SJeff Kirsher /** 3716adfc5217SJeff Kirsher * atomic_dec_ifmoe - dec if the result is more or equal than a given value. 3717adfc5217SJeff Kirsher * 3718adfc5217SJeff Kirsher * @v: pointer of type atomic_t 3719adfc5217SJeff Kirsher * @a: the amount to dec from v... 3720adfc5217SJeff Kirsher * @u: ...if (v - a) is more or equal than u. 3721adfc5217SJeff Kirsher * 3722adfc5217SJeff Kirsher * returns true if (v - a) was more or equal than u, and false 3723adfc5217SJeff Kirsher * otherwise. 3724adfc5217SJeff Kirsher */ 3725adfc5217SJeff Kirsher static inline bool __atomic_dec_ifmoe(atomic_t *v, int a, int u) 3726adfc5217SJeff Kirsher { 3727adfc5217SJeff Kirsher int c, old; 3728adfc5217SJeff Kirsher 3729adfc5217SJeff Kirsher c = atomic_read(v); 3730adfc5217SJeff Kirsher for (;;) { 3731adfc5217SJeff Kirsher if (unlikely(c - a < u)) 3732adfc5217SJeff Kirsher return false; 3733adfc5217SJeff Kirsher 3734adfc5217SJeff Kirsher old = atomic_cmpxchg((v), c, c - a); 3735adfc5217SJeff Kirsher if (likely(old == c)) 3736adfc5217SJeff Kirsher break; 3737adfc5217SJeff Kirsher c = old; 3738adfc5217SJeff Kirsher } 3739adfc5217SJeff Kirsher 3740adfc5217SJeff Kirsher return true; 3741adfc5217SJeff Kirsher } 3742adfc5217SJeff Kirsher 3743adfc5217SJeff Kirsher static bool bnx2x_credit_pool_get(struct bnx2x_credit_pool_obj *o, int cnt) 3744adfc5217SJeff Kirsher { 3745adfc5217SJeff Kirsher bool rc; 3746adfc5217SJeff Kirsher 3747adfc5217SJeff Kirsher smp_mb(); 3748adfc5217SJeff Kirsher rc = __atomic_dec_ifmoe(&o->credit, cnt, 0); 3749adfc5217SJeff Kirsher smp_mb(); 3750adfc5217SJeff Kirsher 3751adfc5217SJeff Kirsher return rc; 3752adfc5217SJeff Kirsher } 3753adfc5217SJeff Kirsher 3754adfc5217SJeff Kirsher static bool bnx2x_credit_pool_put(struct bnx2x_credit_pool_obj *o, int cnt) 3755adfc5217SJeff Kirsher { 3756adfc5217SJeff Kirsher bool rc; 3757adfc5217SJeff Kirsher 3758adfc5217SJeff Kirsher smp_mb(); 3759adfc5217SJeff Kirsher 3760adfc5217SJeff Kirsher /* Don't let to refill if credit + cnt > pool_sz */ 3761adfc5217SJeff Kirsher rc = __atomic_add_ifless(&o->credit, cnt, o->pool_sz + 1); 3762adfc5217SJeff Kirsher 3763adfc5217SJeff Kirsher smp_mb(); 3764adfc5217SJeff Kirsher 3765adfc5217SJeff Kirsher return rc; 3766adfc5217SJeff Kirsher } 3767adfc5217SJeff Kirsher 3768adfc5217SJeff Kirsher static int bnx2x_credit_pool_check(struct bnx2x_credit_pool_obj *o) 3769adfc5217SJeff Kirsher { 3770adfc5217SJeff Kirsher int cur_credit; 3771adfc5217SJeff Kirsher 3772adfc5217SJeff Kirsher smp_mb(); 3773adfc5217SJeff Kirsher cur_credit = atomic_read(&o->credit); 3774adfc5217SJeff Kirsher 3775adfc5217SJeff Kirsher return cur_credit; 3776adfc5217SJeff Kirsher } 3777adfc5217SJeff Kirsher 3778adfc5217SJeff Kirsher static bool bnx2x_credit_pool_always_true(struct bnx2x_credit_pool_obj *o, 3779adfc5217SJeff Kirsher int cnt) 3780adfc5217SJeff Kirsher { 3781adfc5217SJeff Kirsher return true; 3782adfc5217SJeff Kirsher } 3783adfc5217SJeff Kirsher 3784adfc5217SJeff Kirsher static bool bnx2x_credit_pool_get_entry( 3785adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *o, 3786adfc5217SJeff Kirsher int *offset) 3787adfc5217SJeff Kirsher { 3788adfc5217SJeff Kirsher int idx, vec, i; 3789adfc5217SJeff Kirsher 3790adfc5217SJeff Kirsher *offset = -1; 3791adfc5217SJeff Kirsher 3792adfc5217SJeff Kirsher /* Find "internal cam-offset" then add to base for this object... */ 3793adfc5217SJeff Kirsher for (vec = 0; vec < BNX2X_POOL_VEC_SIZE; vec++) { 3794adfc5217SJeff Kirsher 3795adfc5217SJeff Kirsher /* Skip the current vector if there are no free entries in it */ 3796adfc5217SJeff Kirsher if (!o->pool_mirror[vec]) 3797adfc5217SJeff Kirsher continue; 3798adfc5217SJeff Kirsher 3799adfc5217SJeff Kirsher /* If we've got here we are going to find a free entry */ 3800c54e9bd3SDmitry Kravkov for (idx = vec * BIT_VEC64_ELEM_SZ, i = 0; 3801adfc5217SJeff Kirsher i < BIT_VEC64_ELEM_SZ; idx++, i++) 3802adfc5217SJeff Kirsher 3803adfc5217SJeff Kirsher if (BIT_VEC64_TEST_BIT(o->pool_mirror, idx)) { 3804adfc5217SJeff Kirsher /* Got one!! */ 3805adfc5217SJeff Kirsher BIT_VEC64_CLEAR_BIT(o->pool_mirror, idx); 3806adfc5217SJeff Kirsher *offset = o->base_pool_offset + idx; 3807adfc5217SJeff Kirsher return true; 3808adfc5217SJeff Kirsher } 3809adfc5217SJeff Kirsher } 3810adfc5217SJeff Kirsher 3811adfc5217SJeff Kirsher return false; 3812adfc5217SJeff Kirsher } 3813adfc5217SJeff Kirsher 3814adfc5217SJeff Kirsher static bool bnx2x_credit_pool_put_entry( 3815adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *o, 3816adfc5217SJeff Kirsher int offset) 3817adfc5217SJeff Kirsher { 3818adfc5217SJeff Kirsher if (offset < o->base_pool_offset) 3819adfc5217SJeff Kirsher return false; 3820adfc5217SJeff Kirsher 3821adfc5217SJeff Kirsher offset -= o->base_pool_offset; 3822adfc5217SJeff Kirsher 3823adfc5217SJeff Kirsher if (offset >= o->pool_sz) 3824adfc5217SJeff Kirsher return false; 3825adfc5217SJeff Kirsher 3826adfc5217SJeff Kirsher /* Return the entry to the pool */ 3827adfc5217SJeff Kirsher BIT_VEC64_SET_BIT(o->pool_mirror, offset); 3828adfc5217SJeff Kirsher 3829adfc5217SJeff Kirsher return true; 3830adfc5217SJeff Kirsher } 3831adfc5217SJeff Kirsher 3832adfc5217SJeff Kirsher static bool bnx2x_credit_pool_put_entry_always_true( 3833adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *o, 3834adfc5217SJeff Kirsher int offset) 3835adfc5217SJeff Kirsher { 3836adfc5217SJeff Kirsher return true; 3837adfc5217SJeff Kirsher } 3838adfc5217SJeff Kirsher 3839adfc5217SJeff Kirsher static bool bnx2x_credit_pool_get_entry_always_true( 3840adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *o, 3841adfc5217SJeff Kirsher int *offset) 3842adfc5217SJeff Kirsher { 3843adfc5217SJeff Kirsher *offset = -1; 3844adfc5217SJeff Kirsher return true; 3845adfc5217SJeff Kirsher } 3846adfc5217SJeff Kirsher /** 3847adfc5217SJeff Kirsher * bnx2x_init_credit_pool - initialize credit pool internals. 3848adfc5217SJeff Kirsher * 3849adfc5217SJeff Kirsher * @p: 3850adfc5217SJeff Kirsher * @base: Base entry in the CAM to use. 3851adfc5217SJeff Kirsher * @credit: pool size. 3852adfc5217SJeff Kirsher * 3853adfc5217SJeff Kirsher * If base is negative no CAM entries handling will be performed. 3854adfc5217SJeff Kirsher * If credit is negative pool operations will always succeed (unlimited pool). 3855adfc5217SJeff Kirsher * 3856adfc5217SJeff Kirsher */ 3857adfc5217SJeff Kirsher static inline void bnx2x_init_credit_pool(struct bnx2x_credit_pool_obj *p, 3858adfc5217SJeff Kirsher int base, int credit) 3859adfc5217SJeff Kirsher { 3860adfc5217SJeff Kirsher /* Zero the object first */ 3861adfc5217SJeff Kirsher memset(p, 0, sizeof(*p)); 3862adfc5217SJeff Kirsher 3863adfc5217SJeff Kirsher /* Set the table to all 1s */ 3864adfc5217SJeff Kirsher memset(&p->pool_mirror, 0xff, sizeof(p->pool_mirror)); 3865adfc5217SJeff Kirsher 3866adfc5217SJeff Kirsher /* Init a pool as full */ 3867adfc5217SJeff Kirsher atomic_set(&p->credit, credit); 3868adfc5217SJeff Kirsher 3869adfc5217SJeff Kirsher /* The total poll size */ 3870adfc5217SJeff Kirsher p->pool_sz = credit; 3871adfc5217SJeff Kirsher 3872adfc5217SJeff Kirsher p->base_pool_offset = base; 3873adfc5217SJeff Kirsher 3874adfc5217SJeff Kirsher /* Commit the change */ 3875adfc5217SJeff Kirsher smp_mb(); 3876adfc5217SJeff Kirsher 3877adfc5217SJeff Kirsher p->check = bnx2x_credit_pool_check; 3878adfc5217SJeff Kirsher 3879adfc5217SJeff Kirsher /* if pool credit is negative - disable the checks */ 3880adfc5217SJeff Kirsher if (credit >= 0) { 3881adfc5217SJeff Kirsher p->put = bnx2x_credit_pool_put; 3882adfc5217SJeff Kirsher p->get = bnx2x_credit_pool_get; 3883adfc5217SJeff Kirsher p->put_entry = bnx2x_credit_pool_put_entry; 3884adfc5217SJeff Kirsher p->get_entry = bnx2x_credit_pool_get_entry; 3885adfc5217SJeff Kirsher } else { 3886adfc5217SJeff Kirsher p->put = bnx2x_credit_pool_always_true; 3887adfc5217SJeff Kirsher p->get = bnx2x_credit_pool_always_true; 3888adfc5217SJeff Kirsher p->put_entry = bnx2x_credit_pool_put_entry_always_true; 3889adfc5217SJeff Kirsher p->get_entry = bnx2x_credit_pool_get_entry_always_true; 3890adfc5217SJeff Kirsher } 3891adfc5217SJeff Kirsher 3892adfc5217SJeff Kirsher /* If base is negative - disable entries handling */ 3893adfc5217SJeff Kirsher if (base < 0) { 3894adfc5217SJeff Kirsher p->put_entry = bnx2x_credit_pool_put_entry_always_true; 3895adfc5217SJeff Kirsher p->get_entry = bnx2x_credit_pool_get_entry_always_true; 3896adfc5217SJeff Kirsher } 3897adfc5217SJeff Kirsher } 3898adfc5217SJeff Kirsher 3899adfc5217SJeff Kirsher void bnx2x_init_mac_credit_pool(struct bnx2x *bp, 3900adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *p, u8 func_id, 3901adfc5217SJeff Kirsher u8 func_num) 3902adfc5217SJeff Kirsher { 3903adfc5217SJeff Kirsher /* TODO: this will be defined in consts as well... */ 3904adfc5217SJeff Kirsher #define BNX2X_CAM_SIZE_EMUL 5 3905adfc5217SJeff Kirsher 3906adfc5217SJeff Kirsher int cam_sz; 3907adfc5217SJeff Kirsher 3908adfc5217SJeff Kirsher if (CHIP_IS_E1(bp)) { 3909adfc5217SJeff Kirsher /* In E1, Multicast is saved in cam... */ 3910adfc5217SJeff Kirsher if (!CHIP_REV_IS_SLOW(bp)) 3911adfc5217SJeff Kirsher cam_sz = (MAX_MAC_CREDIT_E1 / 2) - BNX2X_MAX_MULTICAST; 3912adfc5217SJeff Kirsher else 3913adfc5217SJeff Kirsher cam_sz = BNX2X_CAM_SIZE_EMUL - BNX2X_MAX_EMUL_MULTI; 3914adfc5217SJeff Kirsher 3915adfc5217SJeff Kirsher bnx2x_init_credit_pool(p, func_id * cam_sz, cam_sz); 3916adfc5217SJeff Kirsher 3917adfc5217SJeff Kirsher } else if (CHIP_IS_E1H(bp)) { 3918adfc5217SJeff Kirsher /* CAM credit is equaly divided between all active functions 3919adfc5217SJeff Kirsher * on the PORT!. 3920adfc5217SJeff Kirsher */ 3921adfc5217SJeff Kirsher if ((func_num > 0)) { 3922adfc5217SJeff Kirsher if (!CHIP_REV_IS_SLOW(bp)) 3923adfc5217SJeff Kirsher cam_sz = (MAX_MAC_CREDIT_E1H / (2*func_num)); 3924adfc5217SJeff Kirsher else 3925adfc5217SJeff Kirsher cam_sz = BNX2X_CAM_SIZE_EMUL; 3926adfc5217SJeff Kirsher bnx2x_init_credit_pool(p, func_id * cam_sz, cam_sz); 3927adfc5217SJeff Kirsher } else { 3928adfc5217SJeff Kirsher /* this should never happen! Block MAC operations. */ 3929adfc5217SJeff Kirsher bnx2x_init_credit_pool(p, 0, 0); 3930adfc5217SJeff Kirsher } 3931adfc5217SJeff Kirsher 3932adfc5217SJeff Kirsher } else { 3933adfc5217SJeff Kirsher 393416a5fd92SYuval Mintz /* CAM credit is equaly divided between all active functions 3935adfc5217SJeff Kirsher * on the PATH. 3936adfc5217SJeff Kirsher */ 3937adfc5217SJeff Kirsher if ((func_num > 0)) { 3938adfc5217SJeff Kirsher if (!CHIP_REV_IS_SLOW(bp)) 3939adfc5217SJeff Kirsher cam_sz = (MAX_MAC_CREDIT_E2 / func_num); 3940adfc5217SJeff Kirsher else 3941adfc5217SJeff Kirsher cam_sz = BNX2X_CAM_SIZE_EMUL; 3942adfc5217SJeff Kirsher 394316a5fd92SYuval Mintz /* No need for CAM entries handling for 57712 and 3944adfc5217SJeff Kirsher * newer. 3945adfc5217SJeff Kirsher */ 3946adfc5217SJeff Kirsher bnx2x_init_credit_pool(p, -1, cam_sz); 3947adfc5217SJeff Kirsher } else { 3948adfc5217SJeff Kirsher /* this should never happen! Block MAC operations. */ 3949adfc5217SJeff Kirsher bnx2x_init_credit_pool(p, 0, 0); 3950adfc5217SJeff Kirsher } 3951adfc5217SJeff Kirsher } 3952adfc5217SJeff Kirsher } 3953adfc5217SJeff Kirsher 3954adfc5217SJeff Kirsher void bnx2x_init_vlan_credit_pool(struct bnx2x *bp, 3955adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *p, 3956adfc5217SJeff Kirsher u8 func_id, 3957adfc5217SJeff Kirsher u8 func_num) 3958adfc5217SJeff Kirsher { 3959adfc5217SJeff Kirsher if (CHIP_IS_E1x(bp)) { 396016a5fd92SYuval Mintz /* There is no VLAN credit in HW on 57710 and 57711 only 3961adfc5217SJeff Kirsher * MAC / MAC-VLAN can be set 3962adfc5217SJeff Kirsher */ 3963adfc5217SJeff Kirsher bnx2x_init_credit_pool(p, 0, -1); 3964adfc5217SJeff Kirsher } else { 396516a5fd92SYuval Mintz /* CAM credit is equally divided between all active functions 3966adfc5217SJeff Kirsher * on the PATH. 3967adfc5217SJeff Kirsher */ 3968adfc5217SJeff Kirsher if (func_num > 0) { 3969adfc5217SJeff Kirsher int credit = MAX_VLAN_CREDIT_E2 / func_num; 3970adfc5217SJeff Kirsher bnx2x_init_credit_pool(p, func_id * credit, credit); 3971adfc5217SJeff Kirsher } else 3972adfc5217SJeff Kirsher /* this should never happen! Block VLAN operations. */ 3973adfc5217SJeff Kirsher bnx2x_init_credit_pool(p, 0, 0); 3974adfc5217SJeff Kirsher } 3975adfc5217SJeff Kirsher } 3976adfc5217SJeff Kirsher 3977adfc5217SJeff Kirsher /****************** RSS Configuration ******************/ 3978adfc5217SJeff Kirsher /** 3979adfc5217SJeff Kirsher * bnx2x_debug_print_ind_table - prints the indirection table configuration. 3980adfc5217SJeff Kirsher * 398116a5fd92SYuval Mintz * @bp: driver handle 3982adfc5217SJeff Kirsher * @p: pointer to rss configuration 3983adfc5217SJeff Kirsher * 3984adfc5217SJeff Kirsher * Prints it when NETIF_MSG_IFUP debug level is configured. 3985adfc5217SJeff Kirsher */ 3986adfc5217SJeff Kirsher static inline void bnx2x_debug_print_ind_table(struct bnx2x *bp, 3987adfc5217SJeff Kirsher struct bnx2x_config_rss_params *p) 3988adfc5217SJeff Kirsher { 3989adfc5217SJeff Kirsher int i; 3990adfc5217SJeff Kirsher 3991adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "Setting indirection table to:\n"); 3992adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "0x0000: "); 3993adfc5217SJeff Kirsher for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++) { 3994adfc5217SJeff Kirsher DP_CONT(BNX2X_MSG_SP, "0x%02x ", p->ind_table[i]); 3995adfc5217SJeff Kirsher 3996adfc5217SJeff Kirsher /* Print 4 bytes in a line */ 3997adfc5217SJeff Kirsher if ((i + 1 < T_ETH_INDIRECTION_TABLE_SIZE) && 3998adfc5217SJeff Kirsher (((i + 1) & 0x3) == 0)) { 3999adfc5217SJeff Kirsher DP_CONT(BNX2X_MSG_SP, "\n"); 4000adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "0x%04x: ", i + 1); 4001adfc5217SJeff Kirsher } 4002adfc5217SJeff Kirsher } 4003adfc5217SJeff Kirsher 4004adfc5217SJeff Kirsher DP_CONT(BNX2X_MSG_SP, "\n"); 4005adfc5217SJeff Kirsher } 4006adfc5217SJeff Kirsher 4007adfc5217SJeff Kirsher /** 4008adfc5217SJeff Kirsher * bnx2x_setup_rss - configure RSS 4009adfc5217SJeff Kirsher * 4010adfc5217SJeff Kirsher * @bp: device handle 4011adfc5217SJeff Kirsher * @p: rss configuration 4012adfc5217SJeff Kirsher * 4013adfc5217SJeff Kirsher * sends on UPDATE ramrod for that matter. 4014adfc5217SJeff Kirsher */ 4015adfc5217SJeff Kirsher static int bnx2x_setup_rss(struct bnx2x *bp, 4016adfc5217SJeff Kirsher struct bnx2x_config_rss_params *p) 4017adfc5217SJeff Kirsher { 4018adfc5217SJeff Kirsher struct bnx2x_rss_config_obj *o = p->rss_obj; 4019adfc5217SJeff Kirsher struct bnx2x_raw_obj *r = &o->raw; 4020adfc5217SJeff Kirsher struct eth_rss_update_ramrod_data *data = 4021adfc5217SJeff Kirsher (struct eth_rss_update_ramrod_data *)(r->rdata); 4022e42780b6SDmitry Kravkov u16 caps = 0; 4023adfc5217SJeff Kirsher u8 rss_mode = 0; 4024adfc5217SJeff Kirsher int rc; 4025adfc5217SJeff Kirsher 4026adfc5217SJeff Kirsher memset(data, 0, sizeof(*data)); 4027adfc5217SJeff Kirsher 4028adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "Configuring RSS\n"); 4029adfc5217SJeff Kirsher 4030adfc5217SJeff Kirsher /* Set an echo field */ 403186564c3fSYuval Mintz data->echo = cpu_to_le32((r->cid & BNX2X_SWCID_MASK) | 403286564c3fSYuval Mintz (r->state << BNX2X_SWCID_SHIFT)); 4033adfc5217SJeff Kirsher 4034adfc5217SJeff Kirsher /* RSS mode */ 4035adfc5217SJeff Kirsher if (test_bit(BNX2X_RSS_MODE_DISABLED, &p->rss_flags)) 4036adfc5217SJeff Kirsher rss_mode = ETH_RSS_MODE_DISABLED; 4037adfc5217SJeff Kirsher else if (test_bit(BNX2X_RSS_MODE_REGULAR, &p->rss_flags)) 4038adfc5217SJeff Kirsher rss_mode = ETH_RSS_MODE_REGULAR; 4039adfc5217SJeff Kirsher 4040adfc5217SJeff Kirsher data->rss_mode = rss_mode; 4041adfc5217SJeff Kirsher 4042adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "rss_mode=%d\n", rss_mode); 4043adfc5217SJeff Kirsher 4044adfc5217SJeff Kirsher /* RSS capabilities */ 4045adfc5217SJeff Kirsher if (test_bit(BNX2X_RSS_IPV4, &p->rss_flags)) 4046e42780b6SDmitry Kravkov caps |= ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY; 4047adfc5217SJeff Kirsher 4048adfc5217SJeff Kirsher if (test_bit(BNX2X_RSS_IPV4_TCP, &p->rss_flags)) 4049e42780b6SDmitry Kravkov caps |= ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY; 4050adfc5217SJeff Kirsher 40515d317c6aSMerav Sicron if (test_bit(BNX2X_RSS_IPV4_UDP, &p->rss_flags)) 4052e42780b6SDmitry Kravkov caps |= ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY; 40535d317c6aSMerav Sicron 4054adfc5217SJeff Kirsher if (test_bit(BNX2X_RSS_IPV6, &p->rss_flags)) 4055e42780b6SDmitry Kravkov caps |= ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY; 4056adfc5217SJeff Kirsher 4057adfc5217SJeff Kirsher if (test_bit(BNX2X_RSS_IPV6_TCP, &p->rss_flags)) 4058e42780b6SDmitry Kravkov caps |= ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY; 4059adfc5217SJeff Kirsher 40605d317c6aSMerav Sicron if (test_bit(BNX2X_RSS_IPV6_UDP, &p->rss_flags)) 4061e42780b6SDmitry Kravkov caps |= ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY; 4062e42780b6SDmitry Kravkov 406328311f8eSYuval Mintz if (test_bit(BNX2X_RSS_IPV4_VXLAN, &p->rss_flags)) 406428311f8eSYuval Mintz caps |= ETH_RSS_UPDATE_RAMROD_DATA_IPV4_VXLAN_CAPABILITY; 406528311f8eSYuval Mintz 406628311f8eSYuval Mintz if (test_bit(BNX2X_RSS_IPV6_VXLAN, &p->rss_flags)) 406728311f8eSYuval Mintz caps |= ETH_RSS_UPDATE_RAMROD_DATA_IPV6_VXLAN_CAPABILITY; 406828311f8eSYuval Mintz 406928311f8eSYuval Mintz if (test_bit(BNX2X_RSS_TUNN_INNER_HDRS, &p->rss_flags)) 407028311f8eSYuval Mintz caps |= ETH_RSS_UPDATE_RAMROD_DATA_TUNN_INNER_HDRS_CAPABILITY; 4071e42780b6SDmitry Kravkov 407256daf66dSYuval Mintz /* RSS keys */ 407356daf66dSYuval Mintz if (test_bit(BNX2X_RSS_SET_SRCH, &p->rss_flags)) { 407456daf66dSYuval Mintz memcpy(&data->rss_key[0], &p->rss_key[0], 407556daf66dSYuval Mintz sizeof(data->rss_key)); 407656daf66dSYuval Mintz caps |= ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY; 407756daf66dSYuval Mintz } 407856daf66dSYuval Mintz 4079e42780b6SDmitry Kravkov data->capabilities = cpu_to_le16(caps); 40805d317c6aSMerav Sicron 4081adfc5217SJeff Kirsher /* Hashing mask */ 4082adfc5217SJeff Kirsher data->rss_result_mask = p->rss_result_mask; 4083adfc5217SJeff Kirsher 4084adfc5217SJeff Kirsher /* RSS engine ID */ 4085adfc5217SJeff Kirsher data->rss_engine_id = o->engine_id; 4086adfc5217SJeff Kirsher 4087adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "rss_engine_id=%d\n", data->rss_engine_id); 4088adfc5217SJeff Kirsher 4089adfc5217SJeff Kirsher /* Indirection table */ 4090adfc5217SJeff Kirsher memcpy(data->indirection_table, p->ind_table, 4091adfc5217SJeff Kirsher T_ETH_INDIRECTION_TABLE_SIZE); 4092adfc5217SJeff Kirsher 4093adfc5217SJeff Kirsher /* Remember the last configuration */ 4094adfc5217SJeff Kirsher memcpy(o->ind_table, p->ind_table, T_ETH_INDIRECTION_TABLE_SIZE); 4095adfc5217SJeff Kirsher 4096adfc5217SJeff Kirsher /* Print the indirection table */ 4097adfc5217SJeff Kirsher if (netif_msg_ifup(bp)) 4098adfc5217SJeff Kirsher bnx2x_debug_print_ind_table(bp, p); 4099adfc5217SJeff Kirsher 410014a94ebdSMichal Kalderon /* No need for an explicit memory barrier here as long as we 410114a94ebdSMichal Kalderon * ensure the ordering of writing to the SPQ element 4102adfc5217SJeff Kirsher * and updating of the SPQ producer which involves a memory 410314a94ebdSMichal Kalderon * read. If the memory read is removed we will have to put a 410414a94ebdSMichal Kalderon * full memory barrier there (inside bnx2x_sp_post()). 4105adfc5217SJeff Kirsher */ 4106adfc5217SJeff Kirsher 4107adfc5217SJeff Kirsher /* Send a ramrod */ 4108adfc5217SJeff Kirsher rc = bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_RSS_UPDATE, r->cid, 4109adfc5217SJeff Kirsher U64_HI(r->rdata_mapping), 4110adfc5217SJeff Kirsher U64_LO(r->rdata_mapping), 4111adfc5217SJeff Kirsher ETH_CONNECTION_TYPE); 4112adfc5217SJeff Kirsher 4113adfc5217SJeff Kirsher if (rc < 0) 4114adfc5217SJeff Kirsher return rc; 4115adfc5217SJeff Kirsher 4116adfc5217SJeff Kirsher return 1; 4117adfc5217SJeff Kirsher } 4118adfc5217SJeff Kirsher 4119adfc5217SJeff Kirsher void bnx2x_get_rss_ind_table(struct bnx2x_rss_config_obj *rss_obj, 4120adfc5217SJeff Kirsher u8 *ind_table) 4121adfc5217SJeff Kirsher { 4122adfc5217SJeff Kirsher memcpy(ind_table, rss_obj->ind_table, sizeof(rss_obj->ind_table)); 4123adfc5217SJeff Kirsher } 4124adfc5217SJeff Kirsher 4125adfc5217SJeff Kirsher int bnx2x_config_rss(struct bnx2x *bp, 4126adfc5217SJeff Kirsher struct bnx2x_config_rss_params *p) 4127adfc5217SJeff Kirsher { 4128adfc5217SJeff Kirsher int rc; 4129adfc5217SJeff Kirsher struct bnx2x_rss_config_obj *o = p->rss_obj; 4130adfc5217SJeff Kirsher struct bnx2x_raw_obj *r = &o->raw; 4131adfc5217SJeff Kirsher 4132adfc5217SJeff Kirsher /* Do nothing if only driver cleanup was requested */ 41335b622918SMichal Kalderon if (test_bit(RAMROD_DRV_CLR_ONLY, &p->ramrod_flags)) { 41345b622918SMichal Kalderon DP(BNX2X_MSG_SP, "Not configuring RSS ramrod_flags=%lx\n", 41355b622918SMichal Kalderon p->ramrod_flags); 4136adfc5217SJeff Kirsher return 0; 41375b622918SMichal Kalderon } 4138adfc5217SJeff Kirsher 4139adfc5217SJeff Kirsher r->set_pending(r); 4140adfc5217SJeff Kirsher 4141adfc5217SJeff Kirsher rc = o->config_rss(bp, p); 4142adfc5217SJeff Kirsher if (rc < 0) { 4143adfc5217SJeff Kirsher r->clear_pending(r); 4144adfc5217SJeff Kirsher return rc; 4145adfc5217SJeff Kirsher } 4146adfc5217SJeff Kirsher 4147adfc5217SJeff Kirsher if (test_bit(RAMROD_COMP_WAIT, &p->ramrod_flags)) 4148adfc5217SJeff Kirsher rc = r->wait_comp(bp, r); 4149adfc5217SJeff Kirsher 4150adfc5217SJeff Kirsher return rc; 4151adfc5217SJeff Kirsher } 4152adfc5217SJeff Kirsher 4153adfc5217SJeff Kirsher void bnx2x_init_rss_config_obj(struct bnx2x *bp, 4154adfc5217SJeff Kirsher struct bnx2x_rss_config_obj *rss_obj, 4155adfc5217SJeff Kirsher u8 cl_id, u32 cid, u8 func_id, u8 engine_id, 4156adfc5217SJeff Kirsher void *rdata, dma_addr_t rdata_mapping, 4157adfc5217SJeff Kirsher int state, unsigned long *pstate, 4158adfc5217SJeff Kirsher bnx2x_obj_type type) 4159adfc5217SJeff Kirsher { 4160adfc5217SJeff Kirsher bnx2x_init_raw_obj(&rss_obj->raw, cl_id, cid, func_id, rdata, 4161adfc5217SJeff Kirsher rdata_mapping, state, pstate, type); 4162adfc5217SJeff Kirsher 4163adfc5217SJeff Kirsher rss_obj->engine_id = engine_id; 4164adfc5217SJeff Kirsher rss_obj->config_rss = bnx2x_setup_rss; 4165adfc5217SJeff Kirsher } 4166adfc5217SJeff Kirsher 4167adfc5217SJeff Kirsher /********************** Queue state object ***********************************/ 4168adfc5217SJeff Kirsher 4169adfc5217SJeff Kirsher /** 4170adfc5217SJeff Kirsher * bnx2x_queue_state_change - perform Queue state change transition 4171adfc5217SJeff Kirsher * 4172adfc5217SJeff Kirsher * @bp: device handle 4173adfc5217SJeff Kirsher * @params: parameters to perform the transition 4174adfc5217SJeff Kirsher * 4175adfc5217SJeff Kirsher * returns 0 in case of successfully completed transition, negative error 4176adfc5217SJeff Kirsher * code in case of failure, positive (EBUSY) value if there is a completion 4177adfc5217SJeff Kirsher * to that is still pending (possible only if RAMROD_COMP_WAIT is 4178adfc5217SJeff Kirsher * not set in params->ramrod_flags for asynchronous commands). 4179adfc5217SJeff Kirsher * 4180adfc5217SJeff Kirsher */ 4181adfc5217SJeff Kirsher int bnx2x_queue_state_change(struct bnx2x *bp, 4182adfc5217SJeff Kirsher struct bnx2x_queue_state_params *params) 4183adfc5217SJeff Kirsher { 4184adfc5217SJeff Kirsher struct bnx2x_queue_sp_obj *o = params->q_obj; 4185adfc5217SJeff Kirsher int rc, pending_bit; 4186adfc5217SJeff Kirsher unsigned long *pending = &o->pending; 4187adfc5217SJeff Kirsher 4188adfc5217SJeff Kirsher /* Check that the requested transition is legal */ 418904c46736SYuval Mintz rc = o->check_transition(bp, o, params); 419004c46736SYuval Mintz if (rc) { 419104c46736SYuval Mintz BNX2X_ERR("check transition returned an error. rc %d\n", rc); 4192adfc5217SJeff Kirsher return -EINVAL; 419304c46736SYuval Mintz } 4194adfc5217SJeff Kirsher 4195adfc5217SJeff Kirsher /* Set "pending" bit */ 419604c46736SYuval Mintz DP(BNX2X_MSG_SP, "pending bit was=%lx\n", o->pending); 4197adfc5217SJeff Kirsher pending_bit = o->set_pending(o, params); 419804c46736SYuval Mintz DP(BNX2X_MSG_SP, "pending bit now=%lx\n", o->pending); 4199adfc5217SJeff Kirsher 4200adfc5217SJeff Kirsher /* Don't send a command if only driver cleanup was requested */ 4201adfc5217SJeff Kirsher if (test_bit(RAMROD_DRV_CLR_ONLY, ¶ms->ramrod_flags)) 4202adfc5217SJeff Kirsher o->complete_cmd(bp, o, pending_bit); 4203adfc5217SJeff Kirsher else { 4204adfc5217SJeff Kirsher /* Send a ramrod */ 4205adfc5217SJeff Kirsher rc = o->send_cmd(bp, params); 4206adfc5217SJeff Kirsher if (rc) { 4207adfc5217SJeff Kirsher o->next_state = BNX2X_Q_STATE_MAX; 4208adfc5217SJeff Kirsher clear_bit(pending_bit, pending); 42094e857c58SPeter Zijlstra smp_mb__after_atomic(); 4210adfc5217SJeff Kirsher return rc; 4211adfc5217SJeff Kirsher } 4212adfc5217SJeff Kirsher 4213adfc5217SJeff Kirsher if (test_bit(RAMROD_COMP_WAIT, ¶ms->ramrod_flags)) { 4214adfc5217SJeff Kirsher rc = o->wait_comp(bp, o, pending_bit); 4215adfc5217SJeff Kirsher if (rc) 4216adfc5217SJeff Kirsher return rc; 4217adfc5217SJeff Kirsher 4218adfc5217SJeff Kirsher return 0; 4219adfc5217SJeff Kirsher } 4220adfc5217SJeff Kirsher } 4221adfc5217SJeff Kirsher 4222adfc5217SJeff Kirsher return !!test_bit(pending_bit, pending); 4223adfc5217SJeff Kirsher } 4224adfc5217SJeff Kirsher 4225adfc5217SJeff Kirsher static int bnx2x_queue_set_pending(struct bnx2x_queue_sp_obj *obj, 4226adfc5217SJeff Kirsher struct bnx2x_queue_state_params *params) 4227adfc5217SJeff Kirsher { 4228adfc5217SJeff Kirsher enum bnx2x_queue_cmd cmd = params->cmd, bit; 4229adfc5217SJeff Kirsher 4230adfc5217SJeff Kirsher /* ACTIVATE and DEACTIVATE commands are implemented on top of 4231adfc5217SJeff Kirsher * UPDATE command. 4232adfc5217SJeff Kirsher */ 4233adfc5217SJeff Kirsher if ((cmd == BNX2X_Q_CMD_ACTIVATE) || 4234adfc5217SJeff Kirsher (cmd == BNX2X_Q_CMD_DEACTIVATE)) 4235adfc5217SJeff Kirsher bit = BNX2X_Q_CMD_UPDATE; 4236adfc5217SJeff Kirsher else 4237adfc5217SJeff Kirsher bit = cmd; 4238adfc5217SJeff Kirsher 4239adfc5217SJeff Kirsher set_bit(bit, &obj->pending); 4240adfc5217SJeff Kirsher return bit; 4241adfc5217SJeff Kirsher } 4242adfc5217SJeff Kirsher 4243adfc5217SJeff Kirsher static int bnx2x_queue_wait_comp(struct bnx2x *bp, 4244adfc5217SJeff Kirsher struct bnx2x_queue_sp_obj *o, 4245adfc5217SJeff Kirsher enum bnx2x_queue_cmd cmd) 4246adfc5217SJeff Kirsher { 4247adfc5217SJeff Kirsher return bnx2x_state_wait(bp, cmd, &o->pending); 4248adfc5217SJeff Kirsher } 4249adfc5217SJeff Kirsher 4250adfc5217SJeff Kirsher /** 4251adfc5217SJeff Kirsher * bnx2x_queue_comp_cmd - complete the state change command. 4252adfc5217SJeff Kirsher * 4253adfc5217SJeff Kirsher * @bp: device handle 4254adfc5217SJeff Kirsher * @o: 4255adfc5217SJeff Kirsher * @cmd: 4256adfc5217SJeff Kirsher * 4257adfc5217SJeff Kirsher * Checks that the arrived completion is expected. 4258adfc5217SJeff Kirsher */ 4259adfc5217SJeff Kirsher static int bnx2x_queue_comp_cmd(struct bnx2x *bp, 4260adfc5217SJeff Kirsher struct bnx2x_queue_sp_obj *o, 4261adfc5217SJeff Kirsher enum bnx2x_queue_cmd cmd) 4262adfc5217SJeff Kirsher { 4263adfc5217SJeff Kirsher unsigned long cur_pending = o->pending; 4264adfc5217SJeff Kirsher 4265adfc5217SJeff Kirsher if (!test_and_clear_bit(cmd, &cur_pending)) { 426651c1a580SMerav Sicron BNX2X_ERR("Bad MC reply %d for queue %d in state %d pending 0x%lx, next_state %d\n", 426751c1a580SMerav Sicron cmd, o->cids[BNX2X_PRIMARY_CID_INDEX], 4268adfc5217SJeff Kirsher o->state, cur_pending, o->next_state); 4269adfc5217SJeff Kirsher return -EINVAL; 4270adfc5217SJeff Kirsher } 4271adfc5217SJeff Kirsher 4272adfc5217SJeff Kirsher if (o->next_tx_only >= o->max_cos) 427316a5fd92SYuval Mintz /* >= because tx only must always be smaller than cos since the 427402582e9bSMasanari Iida * primary connection supports COS 0 4275adfc5217SJeff Kirsher */ 4276adfc5217SJeff Kirsher BNX2X_ERR("illegal value for next tx_only: %d. max cos was %d", 4277adfc5217SJeff Kirsher o->next_tx_only, o->max_cos); 4278adfc5217SJeff Kirsher 427951c1a580SMerav Sicron DP(BNX2X_MSG_SP, 428051c1a580SMerav Sicron "Completing command %d for queue %d, setting state to %d\n", 428151c1a580SMerav Sicron cmd, o->cids[BNX2X_PRIMARY_CID_INDEX], o->next_state); 4282adfc5217SJeff Kirsher 4283adfc5217SJeff Kirsher if (o->next_tx_only) /* print num tx-only if any exist */ 428494f05b0fSJoe Perches DP(BNX2X_MSG_SP, "primary cid %d: num tx-only cons %d\n", 4285adfc5217SJeff Kirsher o->cids[BNX2X_PRIMARY_CID_INDEX], o->next_tx_only); 4286adfc5217SJeff Kirsher 4287adfc5217SJeff Kirsher o->state = o->next_state; 4288adfc5217SJeff Kirsher o->num_tx_only = o->next_tx_only; 4289adfc5217SJeff Kirsher o->next_state = BNX2X_Q_STATE_MAX; 4290adfc5217SJeff Kirsher 4291adfc5217SJeff Kirsher /* It's important that o->state and o->next_state are 4292adfc5217SJeff Kirsher * updated before o->pending. 4293adfc5217SJeff Kirsher */ 4294adfc5217SJeff Kirsher wmb(); 4295adfc5217SJeff Kirsher 4296adfc5217SJeff Kirsher clear_bit(cmd, &o->pending); 42974e857c58SPeter Zijlstra smp_mb__after_atomic(); 4298adfc5217SJeff Kirsher 4299adfc5217SJeff Kirsher return 0; 4300adfc5217SJeff Kirsher } 4301adfc5217SJeff Kirsher 4302adfc5217SJeff Kirsher static void bnx2x_q_fill_setup_data_e2(struct bnx2x *bp, 4303adfc5217SJeff Kirsher struct bnx2x_queue_state_params *cmd_params, 4304adfc5217SJeff Kirsher struct client_init_ramrod_data *data) 4305adfc5217SJeff Kirsher { 4306adfc5217SJeff Kirsher struct bnx2x_queue_setup_params *params = &cmd_params->params.setup; 4307adfc5217SJeff Kirsher 4308adfc5217SJeff Kirsher /* Rx data */ 4309adfc5217SJeff Kirsher 4310adfc5217SJeff Kirsher /* IPv6 TPA supported for E2 and above only */ 4311adfc5217SJeff Kirsher data->rx.tpa_en |= test_bit(BNX2X_Q_FLG_TPA_IPV6, ¶ms->flags) * 4312adfc5217SJeff Kirsher CLIENT_INIT_RX_DATA_TPA_EN_IPV6; 4313adfc5217SJeff Kirsher } 4314adfc5217SJeff Kirsher 4315adfc5217SJeff Kirsher static void bnx2x_q_fill_init_general_data(struct bnx2x *bp, 4316adfc5217SJeff Kirsher struct bnx2x_queue_sp_obj *o, 4317adfc5217SJeff Kirsher struct bnx2x_general_setup_params *params, 4318adfc5217SJeff Kirsher struct client_init_general_data *gen_data, 4319adfc5217SJeff Kirsher unsigned long *flags) 4320adfc5217SJeff Kirsher { 4321adfc5217SJeff Kirsher gen_data->client_id = o->cl_id; 4322adfc5217SJeff Kirsher 4323adfc5217SJeff Kirsher if (test_bit(BNX2X_Q_FLG_STATS, flags)) { 4324adfc5217SJeff Kirsher gen_data->statistics_counter_id = 4325adfc5217SJeff Kirsher params->stat_id; 4326adfc5217SJeff Kirsher gen_data->statistics_en_flg = 1; 4327adfc5217SJeff Kirsher gen_data->statistics_zero_flg = 4328adfc5217SJeff Kirsher test_bit(BNX2X_Q_FLG_ZERO_STATS, flags); 4329adfc5217SJeff Kirsher } else 4330adfc5217SJeff Kirsher gen_data->statistics_counter_id = 4331adfc5217SJeff Kirsher DISABLE_STATISTIC_COUNTER_ID_VALUE; 4332adfc5217SJeff Kirsher 4333adfc5217SJeff Kirsher gen_data->is_fcoe_flg = test_bit(BNX2X_Q_FLG_FCOE, flags); 4334adfc5217SJeff Kirsher gen_data->activate_flg = test_bit(BNX2X_Q_FLG_ACTIVE, flags); 4335adfc5217SJeff Kirsher gen_data->sp_client_id = params->spcl_id; 4336adfc5217SJeff Kirsher gen_data->mtu = cpu_to_le16(params->mtu); 4337adfc5217SJeff Kirsher gen_data->func_id = o->func_id; 4338adfc5217SJeff Kirsher 4339adfc5217SJeff Kirsher gen_data->cos = params->cos; 4340adfc5217SJeff Kirsher 4341adfc5217SJeff Kirsher gen_data->traffic_type = 4342adfc5217SJeff Kirsher test_bit(BNX2X_Q_FLG_FCOE, flags) ? 4343adfc5217SJeff Kirsher LLFC_TRAFFIC_TYPE_FCOE : LLFC_TRAFFIC_TYPE_NW; 4344adfc5217SJeff Kirsher 434502dc4025SYuval Mintz gen_data->fp_hsi_ver = params->fp_hsi; 4346e42780b6SDmitry Kravkov 434794f05b0fSJoe Perches DP(BNX2X_MSG_SP, "flags: active %d, cos %d, stats en %d\n", 4348adfc5217SJeff Kirsher gen_data->activate_flg, gen_data->cos, gen_data->statistics_en_flg); 4349adfc5217SJeff Kirsher } 4350adfc5217SJeff Kirsher 4351adfc5217SJeff Kirsher static void bnx2x_q_fill_init_tx_data(struct bnx2x_queue_sp_obj *o, 4352adfc5217SJeff Kirsher struct bnx2x_txq_setup_params *params, 4353adfc5217SJeff Kirsher struct client_init_tx_data *tx_data, 4354adfc5217SJeff Kirsher unsigned long *flags) 4355adfc5217SJeff Kirsher { 4356adfc5217SJeff Kirsher tx_data->enforce_security_flg = 4357adfc5217SJeff Kirsher test_bit(BNX2X_Q_FLG_TX_SEC, flags); 4358adfc5217SJeff Kirsher tx_data->default_vlan = 4359adfc5217SJeff Kirsher cpu_to_le16(params->default_vlan); 4360adfc5217SJeff Kirsher tx_data->default_vlan_flg = 4361adfc5217SJeff Kirsher test_bit(BNX2X_Q_FLG_DEF_VLAN, flags); 4362adfc5217SJeff Kirsher tx_data->tx_switching_flg = 4363adfc5217SJeff Kirsher test_bit(BNX2X_Q_FLG_TX_SWITCH, flags); 4364adfc5217SJeff Kirsher tx_data->anti_spoofing_flg = 4365adfc5217SJeff Kirsher test_bit(BNX2X_Q_FLG_ANTI_SPOOF, flags); 4366a3348722SBarak Witkowski tx_data->force_default_pri_flg = 4367a3348722SBarak Witkowski test_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI, flags); 4368e42780b6SDmitry Kravkov tx_data->refuse_outband_vlan_flg = 4369e42780b6SDmitry Kravkov test_bit(BNX2X_Q_FLG_REFUSE_OUTBAND_VLAN, flags); 4370e287a75cSDmitry Kravkov tx_data->tunnel_lso_inc_ip_id = 4371e287a75cSDmitry Kravkov test_bit(BNX2X_Q_FLG_TUN_INC_INNER_IP_ID, flags); 437291226790SDmitry Kravkov tx_data->tunnel_non_lso_pcsum_location = 4373e42780b6SDmitry Kravkov test_bit(BNX2X_Q_FLG_PCSUM_ON_PKT, flags) ? CSUM_ON_PKT : 4374e42780b6SDmitry Kravkov CSUM_ON_BD; 437591226790SDmitry Kravkov 4376adfc5217SJeff Kirsher tx_data->tx_status_block_id = params->fw_sb_id; 4377adfc5217SJeff Kirsher tx_data->tx_sb_index_number = params->sb_cq_index; 4378adfc5217SJeff Kirsher tx_data->tss_leading_client_id = params->tss_leading_cl_id; 4379adfc5217SJeff Kirsher 4380adfc5217SJeff Kirsher tx_data->tx_bd_page_base.lo = 4381adfc5217SJeff Kirsher cpu_to_le32(U64_LO(params->dscr_map)); 4382adfc5217SJeff Kirsher tx_data->tx_bd_page_base.hi = 4383adfc5217SJeff Kirsher cpu_to_le32(U64_HI(params->dscr_map)); 4384adfc5217SJeff Kirsher 4385adfc5217SJeff Kirsher /* Don't configure any Tx switching mode during queue SETUP */ 4386adfc5217SJeff Kirsher tx_data->state = 0; 4387adfc5217SJeff Kirsher } 4388adfc5217SJeff Kirsher 4389adfc5217SJeff Kirsher static void bnx2x_q_fill_init_pause_data(struct bnx2x_queue_sp_obj *o, 4390adfc5217SJeff Kirsher struct rxq_pause_params *params, 4391adfc5217SJeff Kirsher struct client_init_rx_data *rx_data) 4392adfc5217SJeff Kirsher { 4393adfc5217SJeff Kirsher /* flow control data */ 4394adfc5217SJeff Kirsher rx_data->cqe_pause_thr_low = cpu_to_le16(params->rcq_th_lo); 4395adfc5217SJeff Kirsher rx_data->cqe_pause_thr_high = cpu_to_le16(params->rcq_th_hi); 4396adfc5217SJeff Kirsher rx_data->bd_pause_thr_low = cpu_to_le16(params->bd_th_lo); 4397adfc5217SJeff Kirsher rx_data->bd_pause_thr_high = cpu_to_le16(params->bd_th_hi); 4398adfc5217SJeff Kirsher rx_data->sge_pause_thr_low = cpu_to_le16(params->sge_th_lo); 4399adfc5217SJeff Kirsher rx_data->sge_pause_thr_high = cpu_to_le16(params->sge_th_hi); 4400adfc5217SJeff Kirsher rx_data->rx_cos_mask = cpu_to_le16(params->pri_map); 4401adfc5217SJeff Kirsher } 4402adfc5217SJeff Kirsher 4403adfc5217SJeff Kirsher static void bnx2x_q_fill_init_rx_data(struct bnx2x_queue_sp_obj *o, 4404adfc5217SJeff Kirsher struct bnx2x_rxq_setup_params *params, 4405adfc5217SJeff Kirsher struct client_init_rx_data *rx_data, 4406adfc5217SJeff Kirsher unsigned long *flags) 4407adfc5217SJeff Kirsher { 4408adfc5217SJeff Kirsher rx_data->tpa_en = test_bit(BNX2X_Q_FLG_TPA, flags) * 4409adfc5217SJeff Kirsher CLIENT_INIT_RX_DATA_TPA_EN_IPV4; 4410621b4d66SDmitry Kravkov rx_data->tpa_en |= test_bit(BNX2X_Q_FLG_TPA_GRO, flags) * 4411621b4d66SDmitry Kravkov CLIENT_INIT_RX_DATA_TPA_MODE; 4412adfc5217SJeff Kirsher rx_data->vmqueue_mode_en_flg = 0; 4413adfc5217SJeff Kirsher 4414adfc5217SJeff Kirsher rx_data->cache_line_alignment_log_size = 4415adfc5217SJeff Kirsher params->cache_line_log; 4416adfc5217SJeff Kirsher rx_data->enable_dynamic_hc = 4417adfc5217SJeff Kirsher test_bit(BNX2X_Q_FLG_DHC, flags); 4418adfc5217SJeff Kirsher rx_data->max_sges_for_packet = params->max_sges_pkt; 4419adfc5217SJeff Kirsher rx_data->client_qzone_id = params->cl_qzone_id; 4420adfc5217SJeff Kirsher rx_data->max_agg_size = cpu_to_le16(params->tpa_agg_sz); 4421adfc5217SJeff Kirsher 4422adfc5217SJeff Kirsher /* Always start in DROP_ALL mode */ 4423adfc5217SJeff Kirsher rx_data->state = cpu_to_le16(CLIENT_INIT_RX_DATA_UCAST_DROP_ALL | 4424adfc5217SJeff Kirsher CLIENT_INIT_RX_DATA_MCAST_DROP_ALL); 4425adfc5217SJeff Kirsher 4426adfc5217SJeff Kirsher /* We don't set drop flags */ 4427adfc5217SJeff Kirsher rx_data->drop_ip_cs_err_flg = 0; 4428adfc5217SJeff Kirsher rx_data->drop_tcp_cs_err_flg = 0; 4429adfc5217SJeff Kirsher rx_data->drop_ttl0_flg = 0; 4430adfc5217SJeff Kirsher rx_data->drop_udp_cs_err_flg = 0; 4431adfc5217SJeff Kirsher rx_data->inner_vlan_removal_enable_flg = 4432adfc5217SJeff Kirsher test_bit(BNX2X_Q_FLG_VLAN, flags); 4433adfc5217SJeff Kirsher rx_data->outer_vlan_removal_enable_flg = 4434adfc5217SJeff Kirsher test_bit(BNX2X_Q_FLG_OV, flags); 4435adfc5217SJeff Kirsher rx_data->status_block_id = params->fw_sb_id; 4436adfc5217SJeff Kirsher rx_data->rx_sb_index_number = params->sb_cq_index; 4437adfc5217SJeff Kirsher rx_data->max_tpa_queues = params->max_tpa_queues; 4438adfc5217SJeff Kirsher rx_data->max_bytes_on_bd = cpu_to_le16(params->buf_sz); 4439adfc5217SJeff Kirsher rx_data->sge_buff_size = cpu_to_le16(params->sge_buf_sz); 4440adfc5217SJeff Kirsher rx_data->bd_page_base.lo = 4441adfc5217SJeff Kirsher cpu_to_le32(U64_LO(params->dscr_map)); 4442adfc5217SJeff Kirsher rx_data->bd_page_base.hi = 4443adfc5217SJeff Kirsher cpu_to_le32(U64_HI(params->dscr_map)); 4444adfc5217SJeff Kirsher rx_data->sge_page_base.lo = 4445adfc5217SJeff Kirsher cpu_to_le32(U64_LO(params->sge_map)); 4446adfc5217SJeff Kirsher rx_data->sge_page_base.hi = 4447adfc5217SJeff Kirsher cpu_to_le32(U64_HI(params->sge_map)); 4448adfc5217SJeff Kirsher rx_data->cqe_page_base.lo = 4449adfc5217SJeff Kirsher cpu_to_le32(U64_LO(params->rcq_map)); 4450adfc5217SJeff Kirsher rx_data->cqe_page_base.hi = 4451adfc5217SJeff Kirsher cpu_to_le32(U64_HI(params->rcq_map)); 4452adfc5217SJeff Kirsher rx_data->is_leading_rss = test_bit(BNX2X_Q_FLG_LEADING_RSS, flags); 4453adfc5217SJeff Kirsher 4454adfc5217SJeff Kirsher if (test_bit(BNX2X_Q_FLG_MCAST, flags)) { 4455259afa1fSYuval Mintz rx_data->approx_mcast_engine_id = params->mcast_engine_id; 4456adfc5217SJeff Kirsher rx_data->is_approx_mcast = 1; 4457adfc5217SJeff Kirsher } 4458adfc5217SJeff Kirsher 4459adfc5217SJeff Kirsher rx_data->rss_engine_id = params->rss_engine_id; 4460adfc5217SJeff Kirsher 4461adfc5217SJeff Kirsher /* silent vlan removal */ 4462adfc5217SJeff Kirsher rx_data->silent_vlan_removal_flg = 4463adfc5217SJeff Kirsher test_bit(BNX2X_Q_FLG_SILENT_VLAN_REM, flags); 4464adfc5217SJeff Kirsher rx_data->silent_vlan_value = 4465adfc5217SJeff Kirsher cpu_to_le16(params->silent_removal_value); 4466adfc5217SJeff Kirsher rx_data->silent_vlan_mask = 4467adfc5217SJeff Kirsher cpu_to_le16(params->silent_removal_mask); 4468adfc5217SJeff Kirsher } 4469adfc5217SJeff Kirsher 4470adfc5217SJeff Kirsher /* initialize the general, tx and rx parts of a queue object */ 4471adfc5217SJeff Kirsher static void bnx2x_q_fill_setup_data_cmn(struct bnx2x *bp, 4472adfc5217SJeff Kirsher struct bnx2x_queue_state_params *cmd_params, 4473adfc5217SJeff Kirsher struct client_init_ramrod_data *data) 4474adfc5217SJeff Kirsher { 4475adfc5217SJeff Kirsher bnx2x_q_fill_init_general_data(bp, cmd_params->q_obj, 4476adfc5217SJeff Kirsher &cmd_params->params.setup.gen_params, 4477adfc5217SJeff Kirsher &data->general, 4478adfc5217SJeff Kirsher &cmd_params->params.setup.flags); 4479adfc5217SJeff Kirsher 4480adfc5217SJeff Kirsher bnx2x_q_fill_init_tx_data(cmd_params->q_obj, 4481adfc5217SJeff Kirsher &cmd_params->params.setup.txq_params, 4482adfc5217SJeff Kirsher &data->tx, 4483adfc5217SJeff Kirsher &cmd_params->params.setup.flags); 4484adfc5217SJeff Kirsher 4485adfc5217SJeff Kirsher bnx2x_q_fill_init_rx_data(cmd_params->q_obj, 4486adfc5217SJeff Kirsher &cmd_params->params.setup.rxq_params, 4487adfc5217SJeff Kirsher &data->rx, 4488adfc5217SJeff Kirsher &cmd_params->params.setup.flags); 4489adfc5217SJeff Kirsher 4490adfc5217SJeff Kirsher bnx2x_q_fill_init_pause_data(cmd_params->q_obj, 4491adfc5217SJeff Kirsher &cmd_params->params.setup.pause_params, 4492adfc5217SJeff Kirsher &data->rx); 4493adfc5217SJeff Kirsher } 4494adfc5217SJeff Kirsher 4495adfc5217SJeff Kirsher /* initialize the general and tx parts of a tx-only queue object */ 4496adfc5217SJeff Kirsher static void bnx2x_q_fill_setup_tx_only(struct bnx2x *bp, 4497adfc5217SJeff Kirsher struct bnx2x_queue_state_params *cmd_params, 4498adfc5217SJeff Kirsher struct tx_queue_init_ramrod_data *data) 4499adfc5217SJeff Kirsher { 4500adfc5217SJeff Kirsher bnx2x_q_fill_init_general_data(bp, cmd_params->q_obj, 4501adfc5217SJeff Kirsher &cmd_params->params.tx_only.gen_params, 4502adfc5217SJeff Kirsher &data->general, 4503adfc5217SJeff Kirsher &cmd_params->params.tx_only.flags); 4504adfc5217SJeff Kirsher 4505adfc5217SJeff Kirsher bnx2x_q_fill_init_tx_data(cmd_params->q_obj, 4506adfc5217SJeff Kirsher &cmd_params->params.tx_only.txq_params, 4507adfc5217SJeff Kirsher &data->tx, 4508adfc5217SJeff Kirsher &cmd_params->params.tx_only.flags); 4509adfc5217SJeff Kirsher 451051c1a580SMerav Sicron DP(BNX2X_MSG_SP, "cid %d, tx bd page lo %x hi %x", 451151c1a580SMerav Sicron cmd_params->q_obj->cids[0], 451251c1a580SMerav Sicron data->tx.tx_bd_page_base.lo, 451351c1a580SMerav Sicron data->tx.tx_bd_page_base.hi); 4514adfc5217SJeff Kirsher } 4515adfc5217SJeff Kirsher 4516adfc5217SJeff Kirsher /** 4517adfc5217SJeff Kirsher * bnx2x_q_init - init HW/FW queue 4518adfc5217SJeff Kirsher * 4519adfc5217SJeff Kirsher * @bp: device handle 4520adfc5217SJeff Kirsher * @params: 4521adfc5217SJeff Kirsher * 4522adfc5217SJeff Kirsher * HW/FW initial Queue configuration: 4523adfc5217SJeff Kirsher * - HC: Rx and Tx 4524adfc5217SJeff Kirsher * - CDU context validation 4525adfc5217SJeff Kirsher * 4526adfc5217SJeff Kirsher */ 4527adfc5217SJeff Kirsher static inline int bnx2x_q_init(struct bnx2x *bp, 4528adfc5217SJeff Kirsher struct bnx2x_queue_state_params *params) 4529adfc5217SJeff Kirsher { 4530adfc5217SJeff Kirsher struct bnx2x_queue_sp_obj *o = params->q_obj; 4531adfc5217SJeff Kirsher struct bnx2x_queue_init_params *init = ¶ms->params.init; 4532adfc5217SJeff Kirsher u16 hc_usec; 4533adfc5217SJeff Kirsher u8 cos; 4534adfc5217SJeff Kirsher 4535adfc5217SJeff Kirsher /* Tx HC configuration */ 4536adfc5217SJeff Kirsher if (test_bit(BNX2X_Q_TYPE_HAS_TX, &o->type) && 4537adfc5217SJeff Kirsher test_bit(BNX2X_Q_FLG_HC, &init->tx.flags)) { 4538adfc5217SJeff Kirsher hc_usec = init->tx.hc_rate ? 1000000 / init->tx.hc_rate : 0; 4539adfc5217SJeff Kirsher 4540adfc5217SJeff Kirsher bnx2x_update_coalesce_sb_index(bp, init->tx.fw_sb_id, 4541adfc5217SJeff Kirsher init->tx.sb_cq_index, 4542adfc5217SJeff Kirsher !test_bit(BNX2X_Q_FLG_HC_EN, &init->tx.flags), 4543adfc5217SJeff Kirsher hc_usec); 4544adfc5217SJeff Kirsher } 4545adfc5217SJeff Kirsher 4546adfc5217SJeff Kirsher /* Rx HC configuration */ 4547adfc5217SJeff Kirsher if (test_bit(BNX2X_Q_TYPE_HAS_RX, &o->type) && 4548adfc5217SJeff Kirsher test_bit(BNX2X_Q_FLG_HC, &init->rx.flags)) { 4549adfc5217SJeff Kirsher hc_usec = init->rx.hc_rate ? 1000000 / init->rx.hc_rate : 0; 4550adfc5217SJeff Kirsher 4551adfc5217SJeff Kirsher bnx2x_update_coalesce_sb_index(bp, init->rx.fw_sb_id, 4552adfc5217SJeff Kirsher init->rx.sb_cq_index, 4553adfc5217SJeff Kirsher !test_bit(BNX2X_Q_FLG_HC_EN, &init->rx.flags), 4554adfc5217SJeff Kirsher hc_usec); 4555adfc5217SJeff Kirsher } 4556adfc5217SJeff Kirsher 4557adfc5217SJeff Kirsher /* Set CDU context validation values */ 4558adfc5217SJeff Kirsher for (cos = 0; cos < o->max_cos; cos++) { 455994f05b0fSJoe Perches DP(BNX2X_MSG_SP, "setting context validation. cid %d, cos %d\n", 4560adfc5217SJeff Kirsher o->cids[cos], cos); 456194f05b0fSJoe Perches DP(BNX2X_MSG_SP, "context pointer %p\n", init->cxts[cos]); 4562adfc5217SJeff Kirsher bnx2x_set_ctx_validation(bp, init->cxts[cos], o->cids[cos]); 4563adfc5217SJeff Kirsher } 4564adfc5217SJeff Kirsher 4565adfc5217SJeff Kirsher /* As no ramrod is sent, complete the command immediately */ 4566adfc5217SJeff Kirsher o->complete_cmd(bp, o, BNX2X_Q_CMD_INIT); 4567adfc5217SJeff Kirsher 4568adfc5217SJeff Kirsher mmiowb(); 4569adfc5217SJeff Kirsher smp_mb(); 4570adfc5217SJeff Kirsher 4571adfc5217SJeff Kirsher return 0; 4572adfc5217SJeff Kirsher } 4573adfc5217SJeff Kirsher 4574adfc5217SJeff Kirsher static inline int bnx2x_q_send_setup_e1x(struct bnx2x *bp, 4575adfc5217SJeff Kirsher struct bnx2x_queue_state_params *params) 4576adfc5217SJeff Kirsher { 4577adfc5217SJeff Kirsher struct bnx2x_queue_sp_obj *o = params->q_obj; 4578adfc5217SJeff Kirsher struct client_init_ramrod_data *rdata = 4579adfc5217SJeff Kirsher (struct client_init_ramrod_data *)o->rdata; 4580adfc5217SJeff Kirsher dma_addr_t data_mapping = o->rdata_mapping; 4581adfc5217SJeff Kirsher int ramrod = RAMROD_CMD_ID_ETH_CLIENT_SETUP; 4582adfc5217SJeff Kirsher 4583adfc5217SJeff Kirsher /* Clear the ramrod data */ 4584adfc5217SJeff Kirsher memset(rdata, 0, sizeof(*rdata)); 4585adfc5217SJeff Kirsher 4586adfc5217SJeff Kirsher /* Fill the ramrod data */ 4587adfc5217SJeff Kirsher bnx2x_q_fill_setup_data_cmn(bp, params, rdata); 4588adfc5217SJeff Kirsher 458914a94ebdSMichal Kalderon /* No need for an explicit memory barrier here as long as we 459014a94ebdSMichal Kalderon * ensure the ordering of writing to the SPQ element 4591adfc5217SJeff Kirsher * and updating of the SPQ producer which involves a memory 459214a94ebdSMichal Kalderon * read. If the memory read is removed we will have to put a 459314a94ebdSMichal Kalderon * full memory barrier there (inside bnx2x_sp_post()). 4594adfc5217SJeff Kirsher */ 4595adfc5217SJeff Kirsher return bnx2x_sp_post(bp, ramrod, o->cids[BNX2X_PRIMARY_CID_INDEX], 4596adfc5217SJeff Kirsher U64_HI(data_mapping), 4597adfc5217SJeff Kirsher U64_LO(data_mapping), ETH_CONNECTION_TYPE); 4598adfc5217SJeff Kirsher } 4599adfc5217SJeff Kirsher 4600adfc5217SJeff Kirsher static inline int bnx2x_q_send_setup_e2(struct bnx2x *bp, 4601adfc5217SJeff Kirsher struct bnx2x_queue_state_params *params) 4602adfc5217SJeff Kirsher { 4603adfc5217SJeff Kirsher struct bnx2x_queue_sp_obj *o = params->q_obj; 4604adfc5217SJeff Kirsher struct client_init_ramrod_data *rdata = 4605adfc5217SJeff Kirsher (struct client_init_ramrod_data *)o->rdata; 4606adfc5217SJeff Kirsher dma_addr_t data_mapping = o->rdata_mapping; 4607adfc5217SJeff Kirsher int ramrod = RAMROD_CMD_ID_ETH_CLIENT_SETUP; 4608adfc5217SJeff Kirsher 4609adfc5217SJeff Kirsher /* Clear the ramrod data */ 4610adfc5217SJeff Kirsher memset(rdata, 0, sizeof(*rdata)); 4611adfc5217SJeff Kirsher 4612adfc5217SJeff Kirsher /* Fill the ramrod data */ 4613adfc5217SJeff Kirsher bnx2x_q_fill_setup_data_cmn(bp, params, rdata); 4614adfc5217SJeff Kirsher bnx2x_q_fill_setup_data_e2(bp, params, rdata); 4615adfc5217SJeff Kirsher 461614a94ebdSMichal Kalderon /* No need for an explicit memory barrier here as long as we 461714a94ebdSMichal Kalderon * ensure the ordering of writing to the SPQ element 4618adfc5217SJeff Kirsher * and updating of the SPQ producer which involves a memory 461914a94ebdSMichal Kalderon * read. If the memory read is removed we will have to put a 462014a94ebdSMichal Kalderon * full memory barrier there (inside bnx2x_sp_post()). 4621adfc5217SJeff Kirsher */ 4622adfc5217SJeff Kirsher return bnx2x_sp_post(bp, ramrod, o->cids[BNX2X_PRIMARY_CID_INDEX], 4623adfc5217SJeff Kirsher U64_HI(data_mapping), 4624adfc5217SJeff Kirsher U64_LO(data_mapping), ETH_CONNECTION_TYPE); 4625adfc5217SJeff Kirsher } 4626adfc5217SJeff Kirsher 4627adfc5217SJeff Kirsher static inline int bnx2x_q_send_setup_tx_only(struct bnx2x *bp, 4628adfc5217SJeff Kirsher struct bnx2x_queue_state_params *params) 4629adfc5217SJeff Kirsher { 4630adfc5217SJeff Kirsher struct bnx2x_queue_sp_obj *o = params->q_obj; 4631adfc5217SJeff Kirsher struct tx_queue_init_ramrod_data *rdata = 4632adfc5217SJeff Kirsher (struct tx_queue_init_ramrod_data *)o->rdata; 4633adfc5217SJeff Kirsher dma_addr_t data_mapping = o->rdata_mapping; 4634adfc5217SJeff Kirsher int ramrod = RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP; 4635adfc5217SJeff Kirsher struct bnx2x_queue_setup_tx_only_params *tx_only_params = 4636adfc5217SJeff Kirsher ¶ms->params.tx_only; 4637adfc5217SJeff Kirsher u8 cid_index = tx_only_params->cid_index; 4638adfc5217SJeff Kirsher 4639adfc5217SJeff Kirsher if (cid_index >= o->max_cos) { 4640adfc5217SJeff Kirsher BNX2X_ERR("queue[%d]: cid_index (%d) is out of range\n", 4641adfc5217SJeff Kirsher o->cl_id, cid_index); 4642adfc5217SJeff Kirsher return -EINVAL; 4643adfc5217SJeff Kirsher } 4644adfc5217SJeff Kirsher 464594f05b0fSJoe Perches DP(BNX2X_MSG_SP, "parameters received: cos: %d sp-id: %d\n", 4646adfc5217SJeff Kirsher tx_only_params->gen_params.cos, 4647adfc5217SJeff Kirsher tx_only_params->gen_params.spcl_id); 4648adfc5217SJeff Kirsher 4649adfc5217SJeff Kirsher /* Clear the ramrod data */ 4650adfc5217SJeff Kirsher memset(rdata, 0, sizeof(*rdata)); 4651adfc5217SJeff Kirsher 4652adfc5217SJeff Kirsher /* Fill the ramrod data */ 4653adfc5217SJeff Kirsher bnx2x_q_fill_setup_tx_only(bp, params, rdata); 4654adfc5217SJeff Kirsher 465551c1a580SMerav Sicron DP(BNX2X_MSG_SP, "sending tx-only ramrod: cid %d, client-id %d, sp-client id %d, cos %d\n", 465651c1a580SMerav Sicron o->cids[cid_index], rdata->general.client_id, 4657adfc5217SJeff Kirsher rdata->general.sp_client_id, rdata->general.cos); 4658adfc5217SJeff Kirsher 465914a94ebdSMichal Kalderon /* No need for an explicit memory barrier here as long as we 466014a94ebdSMichal Kalderon * ensure the ordering of writing to the SPQ element 4661adfc5217SJeff Kirsher * and updating of the SPQ producer which involves a memory 466214a94ebdSMichal Kalderon * read. If the memory read is removed we will have to put a 466314a94ebdSMichal Kalderon * full memory barrier there (inside bnx2x_sp_post()). 4664adfc5217SJeff Kirsher */ 4665adfc5217SJeff Kirsher return bnx2x_sp_post(bp, ramrod, o->cids[cid_index], 4666adfc5217SJeff Kirsher U64_HI(data_mapping), 4667adfc5217SJeff Kirsher U64_LO(data_mapping), ETH_CONNECTION_TYPE); 4668adfc5217SJeff Kirsher } 4669adfc5217SJeff Kirsher 4670adfc5217SJeff Kirsher static void bnx2x_q_fill_update_data(struct bnx2x *bp, 4671adfc5217SJeff Kirsher struct bnx2x_queue_sp_obj *obj, 4672adfc5217SJeff Kirsher struct bnx2x_queue_update_params *params, 4673adfc5217SJeff Kirsher struct client_update_ramrod_data *data) 4674adfc5217SJeff Kirsher { 4675adfc5217SJeff Kirsher /* Client ID of the client to update */ 4676adfc5217SJeff Kirsher data->client_id = obj->cl_id; 4677adfc5217SJeff Kirsher 4678adfc5217SJeff Kirsher /* Function ID of the client to update */ 4679adfc5217SJeff Kirsher data->func_id = obj->func_id; 4680adfc5217SJeff Kirsher 4681adfc5217SJeff Kirsher /* Default VLAN value */ 4682adfc5217SJeff Kirsher data->default_vlan = cpu_to_le16(params->def_vlan); 4683adfc5217SJeff Kirsher 4684adfc5217SJeff Kirsher /* Inner VLAN stripping */ 4685adfc5217SJeff Kirsher data->inner_vlan_removal_enable_flg = 4686adfc5217SJeff Kirsher test_bit(BNX2X_Q_UPDATE_IN_VLAN_REM, ¶ms->update_flags); 4687adfc5217SJeff Kirsher data->inner_vlan_removal_change_flg = 4688adfc5217SJeff Kirsher test_bit(BNX2X_Q_UPDATE_IN_VLAN_REM_CHNG, 4689adfc5217SJeff Kirsher ¶ms->update_flags); 4690adfc5217SJeff Kirsher 469116a5fd92SYuval Mintz /* Outer VLAN stripping */ 4692adfc5217SJeff Kirsher data->outer_vlan_removal_enable_flg = 4693adfc5217SJeff Kirsher test_bit(BNX2X_Q_UPDATE_OUT_VLAN_REM, ¶ms->update_flags); 4694adfc5217SJeff Kirsher data->outer_vlan_removal_change_flg = 4695adfc5217SJeff Kirsher test_bit(BNX2X_Q_UPDATE_OUT_VLAN_REM_CHNG, 4696adfc5217SJeff Kirsher ¶ms->update_flags); 4697adfc5217SJeff Kirsher 4698adfc5217SJeff Kirsher /* Drop packets that have source MAC that doesn't belong to this 4699adfc5217SJeff Kirsher * Queue. 4700adfc5217SJeff Kirsher */ 4701adfc5217SJeff Kirsher data->anti_spoofing_enable_flg = 4702adfc5217SJeff Kirsher test_bit(BNX2X_Q_UPDATE_ANTI_SPOOF, ¶ms->update_flags); 4703adfc5217SJeff Kirsher data->anti_spoofing_change_flg = 4704adfc5217SJeff Kirsher test_bit(BNX2X_Q_UPDATE_ANTI_SPOOF_CHNG, ¶ms->update_flags); 4705adfc5217SJeff Kirsher 4706adfc5217SJeff Kirsher /* Activate/Deactivate */ 4707adfc5217SJeff Kirsher data->activate_flg = 4708adfc5217SJeff Kirsher test_bit(BNX2X_Q_UPDATE_ACTIVATE, ¶ms->update_flags); 4709adfc5217SJeff Kirsher data->activate_change_flg = 4710adfc5217SJeff Kirsher test_bit(BNX2X_Q_UPDATE_ACTIVATE_CHNG, ¶ms->update_flags); 4711adfc5217SJeff Kirsher 4712adfc5217SJeff Kirsher /* Enable default VLAN */ 4713adfc5217SJeff Kirsher data->default_vlan_enable_flg = 4714adfc5217SJeff Kirsher test_bit(BNX2X_Q_UPDATE_DEF_VLAN_EN, ¶ms->update_flags); 4715adfc5217SJeff Kirsher data->default_vlan_change_flg = 4716adfc5217SJeff Kirsher test_bit(BNX2X_Q_UPDATE_DEF_VLAN_EN_CHNG, 4717adfc5217SJeff Kirsher ¶ms->update_flags); 4718adfc5217SJeff Kirsher 4719adfc5217SJeff Kirsher /* silent vlan removal */ 4720adfc5217SJeff Kirsher data->silent_vlan_change_flg = 4721adfc5217SJeff Kirsher test_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG, 4722adfc5217SJeff Kirsher ¶ms->update_flags); 4723adfc5217SJeff Kirsher data->silent_vlan_removal_flg = 4724adfc5217SJeff Kirsher test_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM, ¶ms->update_flags); 4725adfc5217SJeff Kirsher data->silent_vlan_value = cpu_to_le16(params->silent_removal_value); 4726adfc5217SJeff Kirsher data->silent_vlan_mask = cpu_to_le16(params->silent_removal_mask); 4727c14db202SYuval Mintz 4728c14db202SYuval Mintz /* tx switching */ 4729c14db202SYuval Mintz data->tx_switching_flg = 4730c14db202SYuval Mintz test_bit(BNX2X_Q_UPDATE_TX_SWITCHING, ¶ms->update_flags); 4731c14db202SYuval Mintz data->tx_switching_change_flg = 4732c14db202SYuval Mintz test_bit(BNX2X_Q_UPDATE_TX_SWITCHING_CHNG, 4733c14db202SYuval Mintz ¶ms->update_flags); 4734eeed018cSMichal Kalderon 4735eeed018cSMichal Kalderon /* PTP */ 4736eeed018cSMichal Kalderon data->handle_ptp_pkts_flg = 4737eeed018cSMichal Kalderon test_bit(BNX2X_Q_UPDATE_PTP_PKTS, ¶ms->update_flags); 4738eeed018cSMichal Kalderon data->handle_ptp_pkts_change_flg = 4739eeed018cSMichal Kalderon test_bit(BNX2X_Q_UPDATE_PTP_PKTS_CHNG, ¶ms->update_flags); 4740adfc5217SJeff Kirsher } 4741adfc5217SJeff Kirsher 4742adfc5217SJeff Kirsher static inline int bnx2x_q_send_update(struct bnx2x *bp, 4743adfc5217SJeff Kirsher struct bnx2x_queue_state_params *params) 4744adfc5217SJeff Kirsher { 4745adfc5217SJeff Kirsher struct bnx2x_queue_sp_obj *o = params->q_obj; 4746adfc5217SJeff Kirsher struct client_update_ramrod_data *rdata = 4747adfc5217SJeff Kirsher (struct client_update_ramrod_data *)o->rdata; 4748adfc5217SJeff Kirsher dma_addr_t data_mapping = o->rdata_mapping; 4749adfc5217SJeff Kirsher struct bnx2x_queue_update_params *update_params = 4750adfc5217SJeff Kirsher ¶ms->params.update; 4751adfc5217SJeff Kirsher u8 cid_index = update_params->cid_index; 4752adfc5217SJeff Kirsher 4753adfc5217SJeff Kirsher if (cid_index >= o->max_cos) { 4754adfc5217SJeff Kirsher BNX2X_ERR("queue[%d]: cid_index (%d) is out of range\n", 4755adfc5217SJeff Kirsher o->cl_id, cid_index); 4756adfc5217SJeff Kirsher return -EINVAL; 4757adfc5217SJeff Kirsher } 4758adfc5217SJeff Kirsher 4759adfc5217SJeff Kirsher /* Clear the ramrod data */ 4760adfc5217SJeff Kirsher memset(rdata, 0, sizeof(*rdata)); 4761adfc5217SJeff Kirsher 4762adfc5217SJeff Kirsher /* Fill the ramrod data */ 4763adfc5217SJeff Kirsher bnx2x_q_fill_update_data(bp, o, update_params, rdata); 4764adfc5217SJeff Kirsher 476514a94ebdSMichal Kalderon /* No need for an explicit memory barrier here as long as we 476614a94ebdSMichal Kalderon * ensure the ordering of writing to the SPQ element 4767adfc5217SJeff Kirsher * and updating of the SPQ producer which involves a memory 476814a94ebdSMichal Kalderon * read. If the memory read is removed we will have to put a 476914a94ebdSMichal Kalderon * full memory barrier there (inside bnx2x_sp_post()). 4770adfc5217SJeff Kirsher */ 4771adfc5217SJeff Kirsher return bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_CLIENT_UPDATE, 4772adfc5217SJeff Kirsher o->cids[cid_index], U64_HI(data_mapping), 4773adfc5217SJeff Kirsher U64_LO(data_mapping), ETH_CONNECTION_TYPE); 4774adfc5217SJeff Kirsher } 4775adfc5217SJeff Kirsher 4776adfc5217SJeff Kirsher /** 4777adfc5217SJeff Kirsher * bnx2x_q_send_deactivate - send DEACTIVATE command 4778adfc5217SJeff Kirsher * 4779adfc5217SJeff Kirsher * @bp: device handle 4780adfc5217SJeff Kirsher * @params: 4781adfc5217SJeff Kirsher * 4782adfc5217SJeff Kirsher * implemented using the UPDATE command. 4783adfc5217SJeff Kirsher */ 4784adfc5217SJeff Kirsher static inline int bnx2x_q_send_deactivate(struct bnx2x *bp, 4785adfc5217SJeff Kirsher struct bnx2x_queue_state_params *params) 4786adfc5217SJeff Kirsher { 4787adfc5217SJeff Kirsher struct bnx2x_queue_update_params *update = ¶ms->params.update; 4788adfc5217SJeff Kirsher 4789adfc5217SJeff Kirsher memset(update, 0, sizeof(*update)); 4790adfc5217SJeff Kirsher 4791adfc5217SJeff Kirsher __set_bit(BNX2X_Q_UPDATE_ACTIVATE_CHNG, &update->update_flags); 4792adfc5217SJeff Kirsher 4793adfc5217SJeff Kirsher return bnx2x_q_send_update(bp, params); 4794adfc5217SJeff Kirsher } 4795adfc5217SJeff Kirsher 4796adfc5217SJeff Kirsher /** 4797adfc5217SJeff Kirsher * bnx2x_q_send_activate - send ACTIVATE command 4798adfc5217SJeff Kirsher * 4799adfc5217SJeff Kirsher * @bp: device handle 4800adfc5217SJeff Kirsher * @params: 4801adfc5217SJeff Kirsher * 4802adfc5217SJeff Kirsher * implemented using the UPDATE command. 4803adfc5217SJeff Kirsher */ 4804adfc5217SJeff Kirsher static inline int bnx2x_q_send_activate(struct bnx2x *bp, 4805adfc5217SJeff Kirsher struct bnx2x_queue_state_params *params) 4806adfc5217SJeff Kirsher { 4807adfc5217SJeff Kirsher struct bnx2x_queue_update_params *update = ¶ms->params.update; 4808adfc5217SJeff Kirsher 4809adfc5217SJeff Kirsher memset(update, 0, sizeof(*update)); 4810adfc5217SJeff Kirsher 4811adfc5217SJeff Kirsher __set_bit(BNX2X_Q_UPDATE_ACTIVATE, &update->update_flags); 4812adfc5217SJeff Kirsher __set_bit(BNX2X_Q_UPDATE_ACTIVATE_CHNG, &update->update_flags); 4813adfc5217SJeff Kirsher 4814adfc5217SJeff Kirsher return bnx2x_q_send_update(bp, params); 4815adfc5217SJeff Kirsher } 4816adfc5217SJeff Kirsher 481714a94ebdSMichal Kalderon static void bnx2x_q_fill_update_tpa_data(struct bnx2x *bp, 481814a94ebdSMichal Kalderon struct bnx2x_queue_sp_obj *obj, 481914a94ebdSMichal Kalderon struct bnx2x_queue_update_tpa_params *params, 482014a94ebdSMichal Kalderon struct tpa_update_ramrod_data *data) 482114a94ebdSMichal Kalderon { 482214a94ebdSMichal Kalderon data->client_id = obj->cl_id; 482314a94ebdSMichal Kalderon data->complete_on_both_clients = params->complete_on_both_clients; 482414a94ebdSMichal Kalderon data->dont_verify_rings_pause_thr_flg = 482514a94ebdSMichal Kalderon params->dont_verify_thr; 482614a94ebdSMichal Kalderon data->max_agg_size = cpu_to_le16(params->max_agg_sz); 482714a94ebdSMichal Kalderon data->max_sges_for_packet = params->max_sges_pkt; 482814a94ebdSMichal Kalderon data->max_tpa_queues = params->max_tpa_queues; 482914a94ebdSMichal Kalderon data->sge_buff_size = cpu_to_le16(params->sge_buff_sz); 483014a94ebdSMichal Kalderon data->sge_page_base_hi = cpu_to_le32(U64_HI(params->sge_map)); 483114a94ebdSMichal Kalderon data->sge_page_base_lo = cpu_to_le32(U64_LO(params->sge_map)); 483214a94ebdSMichal Kalderon data->sge_pause_thr_high = cpu_to_le16(params->sge_pause_thr_high); 483314a94ebdSMichal Kalderon data->sge_pause_thr_low = cpu_to_le16(params->sge_pause_thr_low); 483414a94ebdSMichal Kalderon data->tpa_mode = params->tpa_mode; 483514a94ebdSMichal Kalderon data->update_ipv4 = params->update_ipv4; 483614a94ebdSMichal Kalderon data->update_ipv6 = params->update_ipv6; 483714a94ebdSMichal Kalderon } 483814a94ebdSMichal Kalderon 4839adfc5217SJeff Kirsher static inline int bnx2x_q_send_update_tpa(struct bnx2x *bp, 4840adfc5217SJeff Kirsher struct bnx2x_queue_state_params *params) 4841adfc5217SJeff Kirsher { 484214a94ebdSMichal Kalderon struct bnx2x_queue_sp_obj *o = params->q_obj; 484314a94ebdSMichal Kalderon struct tpa_update_ramrod_data *rdata = 484414a94ebdSMichal Kalderon (struct tpa_update_ramrod_data *)o->rdata; 484514a94ebdSMichal Kalderon dma_addr_t data_mapping = o->rdata_mapping; 484614a94ebdSMichal Kalderon struct bnx2x_queue_update_tpa_params *update_tpa_params = 484714a94ebdSMichal Kalderon ¶ms->params.update_tpa; 484814a94ebdSMichal Kalderon u16 type; 484914a94ebdSMichal Kalderon 485014a94ebdSMichal Kalderon /* Clear the ramrod data */ 485114a94ebdSMichal Kalderon memset(rdata, 0, sizeof(*rdata)); 485214a94ebdSMichal Kalderon 485314a94ebdSMichal Kalderon /* Fill the ramrod data */ 485414a94ebdSMichal Kalderon bnx2x_q_fill_update_tpa_data(bp, o, update_tpa_params, rdata); 485514a94ebdSMichal Kalderon 485614a94ebdSMichal Kalderon /* Add the function id inside the type, so that sp post function 485714a94ebdSMichal Kalderon * doesn't automatically add the PF func-id, this is required 485814a94ebdSMichal Kalderon * for operations done by PFs on behalf of their VFs 485914a94ebdSMichal Kalderon */ 486014a94ebdSMichal Kalderon type = ETH_CONNECTION_TYPE | 486114a94ebdSMichal Kalderon ((o->func_id) << SPE_HDR_FUNCTION_ID_SHIFT); 486214a94ebdSMichal Kalderon 486314a94ebdSMichal Kalderon /* No need for an explicit memory barrier here as long as we 486414a94ebdSMichal Kalderon * ensure the ordering of writing to the SPQ element 486514a94ebdSMichal Kalderon * and updating of the SPQ producer which involves a memory 486614a94ebdSMichal Kalderon * read. If the memory read is removed we will have to put a 486714a94ebdSMichal Kalderon * full memory barrier there (inside bnx2x_sp_post()). 486814a94ebdSMichal Kalderon */ 486914a94ebdSMichal Kalderon return bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_TPA_UPDATE, 487014a94ebdSMichal Kalderon o->cids[BNX2X_PRIMARY_CID_INDEX], 487114a94ebdSMichal Kalderon U64_HI(data_mapping), 487214a94ebdSMichal Kalderon U64_LO(data_mapping), type); 4873adfc5217SJeff Kirsher } 4874adfc5217SJeff Kirsher 4875adfc5217SJeff Kirsher static inline int bnx2x_q_send_halt(struct bnx2x *bp, 4876adfc5217SJeff Kirsher struct bnx2x_queue_state_params *params) 4877adfc5217SJeff Kirsher { 4878adfc5217SJeff Kirsher struct bnx2x_queue_sp_obj *o = params->q_obj; 4879adfc5217SJeff Kirsher 4880adfc5217SJeff Kirsher return bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_HALT, 4881adfc5217SJeff Kirsher o->cids[BNX2X_PRIMARY_CID_INDEX], 0, o->cl_id, 4882adfc5217SJeff Kirsher ETH_CONNECTION_TYPE); 4883adfc5217SJeff Kirsher } 4884adfc5217SJeff Kirsher 4885adfc5217SJeff Kirsher static inline int bnx2x_q_send_cfc_del(struct bnx2x *bp, 4886adfc5217SJeff Kirsher struct bnx2x_queue_state_params *params) 4887adfc5217SJeff Kirsher { 4888adfc5217SJeff Kirsher struct bnx2x_queue_sp_obj *o = params->q_obj; 4889adfc5217SJeff Kirsher u8 cid_idx = params->params.cfc_del.cid_index; 4890adfc5217SJeff Kirsher 4891adfc5217SJeff Kirsher if (cid_idx >= o->max_cos) { 4892adfc5217SJeff Kirsher BNX2X_ERR("queue[%d]: cid_index (%d) is out of range\n", 4893adfc5217SJeff Kirsher o->cl_id, cid_idx); 4894adfc5217SJeff Kirsher return -EINVAL; 4895adfc5217SJeff Kirsher } 4896adfc5217SJeff Kirsher 4897adfc5217SJeff Kirsher return bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_CFC_DEL, 4898adfc5217SJeff Kirsher o->cids[cid_idx], 0, 0, NONE_CONNECTION_TYPE); 4899adfc5217SJeff Kirsher } 4900adfc5217SJeff Kirsher 4901adfc5217SJeff Kirsher static inline int bnx2x_q_send_terminate(struct bnx2x *bp, 4902adfc5217SJeff Kirsher struct bnx2x_queue_state_params *params) 4903adfc5217SJeff Kirsher { 4904adfc5217SJeff Kirsher struct bnx2x_queue_sp_obj *o = params->q_obj; 4905adfc5217SJeff Kirsher u8 cid_index = params->params.terminate.cid_index; 4906adfc5217SJeff Kirsher 4907adfc5217SJeff Kirsher if (cid_index >= o->max_cos) { 4908adfc5217SJeff Kirsher BNX2X_ERR("queue[%d]: cid_index (%d) is out of range\n", 4909adfc5217SJeff Kirsher o->cl_id, cid_index); 4910adfc5217SJeff Kirsher return -EINVAL; 4911adfc5217SJeff Kirsher } 4912adfc5217SJeff Kirsher 4913adfc5217SJeff Kirsher return bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_TERMINATE, 4914adfc5217SJeff Kirsher o->cids[cid_index], 0, 0, ETH_CONNECTION_TYPE); 4915adfc5217SJeff Kirsher } 4916adfc5217SJeff Kirsher 4917adfc5217SJeff Kirsher static inline int bnx2x_q_send_empty(struct bnx2x *bp, 4918adfc5217SJeff Kirsher struct bnx2x_queue_state_params *params) 4919adfc5217SJeff Kirsher { 4920adfc5217SJeff Kirsher struct bnx2x_queue_sp_obj *o = params->q_obj; 4921adfc5217SJeff Kirsher 4922adfc5217SJeff Kirsher return bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_EMPTY, 4923adfc5217SJeff Kirsher o->cids[BNX2X_PRIMARY_CID_INDEX], 0, 0, 4924adfc5217SJeff Kirsher ETH_CONNECTION_TYPE); 4925adfc5217SJeff Kirsher } 4926adfc5217SJeff Kirsher 4927adfc5217SJeff Kirsher static inline int bnx2x_queue_send_cmd_cmn(struct bnx2x *bp, 4928adfc5217SJeff Kirsher struct bnx2x_queue_state_params *params) 4929adfc5217SJeff Kirsher { 4930adfc5217SJeff Kirsher switch (params->cmd) { 4931adfc5217SJeff Kirsher case BNX2X_Q_CMD_INIT: 4932adfc5217SJeff Kirsher return bnx2x_q_init(bp, params); 4933adfc5217SJeff Kirsher case BNX2X_Q_CMD_SETUP_TX_ONLY: 4934adfc5217SJeff Kirsher return bnx2x_q_send_setup_tx_only(bp, params); 4935adfc5217SJeff Kirsher case BNX2X_Q_CMD_DEACTIVATE: 4936adfc5217SJeff Kirsher return bnx2x_q_send_deactivate(bp, params); 4937adfc5217SJeff Kirsher case BNX2X_Q_CMD_ACTIVATE: 4938adfc5217SJeff Kirsher return bnx2x_q_send_activate(bp, params); 4939adfc5217SJeff Kirsher case BNX2X_Q_CMD_UPDATE: 4940adfc5217SJeff Kirsher return bnx2x_q_send_update(bp, params); 4941adfc5217SJeff Kirsher case BNX2X_Q_CMD_UPDATE_TPA: 4942adfc5217SJeff Kirsher return bnx2x_q_send_update_tpa(bp, params); 4943adfc5217SJeff Kirsher case BNX2X_Q_CMD_HALT: 4944adfc5217SJeff Kirsher return bnx2x_q_send_halt(bp, params); 4945adfc5217SJeff Kirsher case BNX2X_Q_CMD_CFC_DEL: 4946adfc5217SJeff Kirsher return bnx2x_q_send_cfc_del(bp, params); 4947adfc5217SJeff Kirsher case BNX2X_Q_CMD_TERMINATE: 4948adfc5217SJeff Kirsher return bnx2x_q_send_terminate(bp, params); 4949adfc5217SJeff Kirsher case BNX2X_Q_CMD_EMPTY: 4950adfc5217SJeff Kirsher return bnx2x_q_send_empty(bp, params); 4951adfc5217SJeff Kirsher default: 4952adfc5217SJeff Kirsher BNX2X_ERR("Unknown command: %d\n", params->cmd); 4953adfc5217SJeff Kirsher return -EINVAL; 4954adfc5217SJeff Kirsher } 4955adfc5217SJeff Kirsher } 4956adfc5217SJeff Kirsher 4957adfc5217SJeff Kirsher static int bnx2x_queue_send_cmd_e1x(struct bnx2x *bp, 4958adfc5217SJeff Kirsher struct bnx2x_queue_state_params *params) 4959adfc5217SJeff Kirsher { 4960adfc5217SJeff Kirsher switch (params->cmd) { 4961adfc5217SJeff Kirsher case BNX2X_Q_CMD_SETUP: 4962adfc5217SJeff Kirsher return bnx2x_q_send_setup_e1x(bp, params); 4963adfc5217SJeff Kirsher case BNX2X_Q_CMD_INIT: 4964adfc5217SJeff Kirsher case BNX2X_Q_CMD_SETUP_TX_ONLY: 4965adfc5217SJeff Kirsher case BNX2X_Q_CMD_DEACTIVATE: 4966adfc5217SJeff Kirsher case BNX2X_Q_CMD_ACTIVATE: 4967adfc5217SJeff Kirsher case BNX2X_Q_CMD_UPDATE: 4968adfc5217SJeff Kirsher case BNX2X_Q_CMD_UPDATE_TPA: 4969adfc5217SJeff Kirsher case BNX2X_Q_CMD_HALT: 4970adfc5217SJeff Kirsher case BNX2X_Q_CMD_CFC_DEL: 4971adfc5217SJeff Kirsher case BNX2X_Q_CMD_TERMINATE: 4972adfc5217SJeff Kirsher case BNX2X_Q_CMD_EMPTY: 4973adfc5217SJeff Kirsher return bnx2x_queue_send_cmd_cmn(bp, params); 4974adfc5217SJeff Kirsher default: 4975adfc5217SJeff Kirsher BNX2X_ERR("Unknown command: %d\n", params->cmd); 4976adfc5217SJeff Kirsher return -EINVAL; 4977adfc5217SJeff Kirsher } 4978adfc5217SJeff Kirsher } 4979adfc5217SJeff Kirsher 4980adfc5217SJeff Kirsher static int bnx2x_queue_send_cmd_e2(struct bnx2x *bp, 4981adfc5217SJeff Kirsher struct bnx2x_queue_state_params *params) 4982adfc5217SJeff Kirsher { 4983adfc5217SJeff Kirsher switch (params->cmd) { 4984adfc5217SJeff Kirsher case BNX2X_Q_CMD_SETUP: 4985adfc5217SJeff Kirsher return bnx2x_q_send_setup_e2(bp, params); 4986adfc5217SJeff Kirsher case BNX2X_Q_CMD_INIT: 4987adfc5217SJeff Kirsher case BNX2X_Q_CMD_SETUP_TX_ONLY: 4988adfc5217SJeff Kirsher case BNX2X_Q_CMD_DEACTIVATE: 4989adfc5217SJeff Kirsher case BNX2X_Q_CMD_ACTIVATE: 4990adfc5217SJeff Kirsher case BNX2X_Q_CMD_UPDATE: 4991adfc5217SJeff Kirsher case BNX2X_Q_CMD_UPDATE_TPA: 4992adfc5217SJeff Kirsher case BNX2X_Q_CMD_HALT: 4993adfc5217SJeff Kirsher case BNX2X_Q_CMD_CFC_DEL: 4994adfc5217SJeff Kirsher case BNX2X_Q_CMD_TERMINATE: 4995adfc5217SJeff Kirsher case BNX2X_Q_CMD_EMPTY: 4996adfc5217SJeff Kirsher return bnx2x_queue_send_cmd_cmn(bp, params); 4997adfc5217SJeff Kirsher default: 4998adfc5217SJeff Kirsher BNX2X_ERR("Unknown command: %d\n", params->cmd); 4999adfc5217SJeff Kirsher return -EINVAL; 5000adfc5217SJeff Kirsher } 5001adfc5217SJeff Kirsher } 5002adfc5217SJeff Kirsher 5003adfc5217SJeff Kirsher /** 5004adfc5217SJeff Kirsher * bnx2x_queue_chk_transition - check state machine of a regular Queue 5005adfc5217SJeff Kirsher * 5006adfc5217SJeff Kirsher * @bp: device handle 5007adfc5217SJeff Kirsher * @o: 5008adfc5217SJeff Kirsher * @params: 5009adfc5217SJeff Kirsher * 5010adfc5217SJeff Kirsher * (not Forwarding) 5011adfc5217SJeff Kirsher * It both checks if the requested command is legal in a current 5012adfc5217SJeff Kirsher * state and, if it's legal, sets a `next_state' in the object 5013adfc5217SJeff Kirsher * that will be used in the completion flow to set the `state' 5014adfc5217SJeff Kirsher * of the object. 5015adfc5217SJeff Kirsher * 5016adfc5217SJeff Kirsher * returns 0 if a requested command is a legal transition, 5017adfc5217SJeff Kirsher * -EINVAL otherwise. 5018adfc5217SJeff Kirsher */ 5019adfc5217SJeff Kirsher static int bnx2x_queue_chk_transition(struct bnx2x *bp, 5020adfc5217SJeff Kirsher struct bnx2x_queue_sp_obj *o, 5021adfc5217SJeff Kirsher struct bnx2x_queue_state_params *params) 5022adfc5217SJeff Kirsher { 5023adfc5217SJeff Kirsher enum bnx2x_q_state state = o->state, next_state = BNX2X_Q_STATE_MAX; 5024adfc5217SJeff Kirsher enum bnx2x_queue_cmd cmd = params->cmd; 5025adfc5217SJeff Kirsher struct bnx2x_queue_update_params *update_params = 5026adfc5217SJeff Kirsher ¶ms->params.update; 5027adfc5217SJeff Kirsher u8 next_tx_only = o->num_tx_only; 5028adfc5217SJeff Kirsher 502916a5fd92SYuval Mintz /* Forget all pending for completion commands if a driver only state 5030adfc5217SJeff Kirsher * transition has been requested. 5031adfc5217SJeff Kirsher */ 5032adfc5217SJeff Kirsher if (test_bit(RAMROD_DRV_CLR_ONLY, ¶ms->ramrod_flags)) { 5033adfc5217SJeff Kirsher o->pending = 0; 5034adfc5217SJeff Kirsher o->next_state = BNX2X_Q_STATE_MAX; 5035adfc5217SJeff Kirsher } 5036adfc5217SJeff Kirsher 503716a5fd92SYuval Mintz /* Don't allow a next state transition if we are in the middle of 5038adfc5217SJeff Kirsher * the previous one. 5039adfc5217SJeff Kirsher */ 504004c46736SYuval Mintz if (o->pending) { 504104c46736SYuval Mintz BNX2X_ERR("Blocking transition since pending was %lx\n", 504204c46736SYuval Mintz o->pending); 5043adfc5217SJeff Kirsher return -EBUSY; 504404c46736SYuval Mintz } 5045adfc5217SJeff Kirsher 5046adfc5217SJeff Kirsher switch (state) { 5047adfc5217SJeff Kirsher case BNX2X_Q_STATE_RESET: 5048adfc5217SJeff Kirsher if (cmd == BNX2X_Q_CMD_INIT) 5049adfc5217SJeff Kirsher next_state = BNX2X_Q_STATE_INITIALIZED; 5050adfc5217SJeff Kirsher 5051adfc5217SJeff Kirsher break; 5052adfc5217SJeff Kirsher case BNX2X_Q_STATE_INITIALIZED: 5053adfc5217SJeff Kirsher if (cmd == BNX2X_Q_CMD_SETUP) { 5054adfc5217SJeff Kirsher if (test_bit(BNX2X_Q_FLG_ACTIVE, 5055adfc5217SJeff Kirsher ¶ms->params.setup.flags)) 5056adfc5217SJeff Kirsher next_state = BNX2X_Q_STATE_ACTIVE; 5057adfc5217SJeff Kirsher else 5058adfc5217SJeff Kirsher next_state = BNX2X_Q_STATE_INACTIVE; 5059adfc5217SJeff Kirsher } 5060adfc5217SJeff Kirsher 5061adfc5217SJeff Kirsher break; 5062adfc5217SJeff Kirsher case BNX2X_Q_STATE_ACTIVE: 5063adfc5217SJeff Kirsher if (cmd == BNX2X_Q_CMD_DEACTIVATE) 5064adfc5217SJeff Kirsher next_state = BNX2X_Q_STATE_INACTIVE; 5065adfc5217SJeff Kirsher 5066adfc5217SJeff Kirsher else if ((cmd == BNX2X_Q_CMD_EMPTY) || 5067adfc5217SJeff Kirsher (cmd == BNX2X_Q_CMD_UPDATE_TPA)) 5068adfc5217SJeff Kirsher next_state = BNX2X_Q_STATE_ACTIVE; 5069adfc5217SJeff Kirsher 5070adfc5217SJeff Kirsher else if (cmd == BNX2X_Q_CMD_SETUP_TX_ONLY) { 5071adfc5217SJeff Kirsher next_state = BNX2X_Q_STATE_MULTI_COS; 5072adfc5217SJeff Kirsher next_tx_only = 1; 5073adfc5217SJeff Kirsher } 5074adfc5217SJeff Kirsher 5075adfc5217SJeff Kirsher else if (cmd == BNX2X_Q_CMD_HALT) 5076adfc5217SJeff Kirsher next_state = BNX2X_Q_STATE_STOPPED; 5077adfc5217SJeff Kirsher 5078adfc5217SJeff Kirsher else if (cmd == BNX2X_Q_CMD_UPDATE) { 5079adfc5217SJeff Kirsher /* If "active" state change is requested, update the 5080adfc5217SJeff Kirsher * state accordingly. 5081adfc5217SJeff Kirsher */ 5082adfc5217SJeff Kirsher if (test_bit(BNX2X_Q_UPDATE_ACTIVATE_CHNG, 5083adfc5217SJeff Kirsher &update_params->update_flags) && 5084adfc5217SJeff Kirsher !test_bit(BNX2X_Q_UPDATE_ACTIVATE, 5085adfc5217SJeff Kirsher &update_params->update_flags)) 5086adfc5217SJeff Kirsher next_state = BNX2X_Q_STATE_INACTIVE; 5087adfc5217SJeff Kirsher else 5088adfc5217SJeff Kirsher next_state = BNX2X_Q_STATE_ACTIVE; 5089adfc5217SJeff Kirsher } 5090adfc5217SJeff Kirsher 5091adfc5217SJeff Kirsher break; 5092adfc5217SJeff Kirsher case BNX2X_Q_STATE_MULTI_COS: 5093adfc5217SJeff Kirsher if (cmd == BNX2X_Q_CMD_TERMINATE) 5094adfc5217SJeff Kirsher next_state = BNX2X_Q_STATE_MCOS_TERMINATED; 5095adfc5217SJeff Kirsher 5096adfc5217SJeff Kirsher else if (cmd == BNX2X_Q_CMD_SETUP_TX_ONLY) { 5097adfc5217SJeff Kirsher next_state = BNX2X_Q_STATE_MULTI_COS; 5098adfc5217SJeff Kirsher next_tx_only = o->num_tx_only + 1; 5099adfc5217SJeff Kirsher } 5100adfc5217SJeff Kirsher 5101adfc5217SJeff Kirsher else if ((cmd == BNX2X_Q_CMD_EMPTY) || 5102adfc5217SJeff Kirsher (cmd == BNX2X_Q_CMD_UPDATE_TPA)) 5103adfc5217SJeff Kirsher next_state = BNX2X_Q_STATE_MULTI_COS; 5104adfc5217SJeff Kirsher 5105adfc5217SJeff Kirsher else if (cmd == BNX2X_Q_CMD_UPDATE) { 5106adfc5217SJeff Kirsher /* If "active" state change is requested, update the 5107adfc5217SJeff Kirsher * state accordingly. 5108adfc5217SJeff Kirsher */ 5109adfc5217SJeff Kirsher if (test_bit(BNX2X_Q_UPDATE_ACTIVATE_CHNG, 5110adfc5217SJeff Kirsher &update_params->update_flags) && 5111adfc5217SJeff Kirsher !test_bit(BNX2X_Q_UPDATE_ACTIVATE, 5112adfc5217SJeff Kirsher &update_params->update_flags)) 5113adfc5217SJeff Kirsher next_state = BNX2X_Q_STATE_INACTIVE; 5114adfc5217SJeff Kirsher else 5115adfc5217SJeff Kirsher next_state = BNX2X_Q_STATE_MULTI_COS; 5116adfc5217SJeff Kirsher } 5117adfc5217SJeff Kirsher 5118adfc5217SJeff Kirsher break; 5119adfc5217SJeff Kirsher case BNX2X_Q_STATE_MCOS_TERMINATED: 5120adfc5217SJeff Kirsher if (cmd == BNX2X_Q_CMD_CFC_DEL) { 5121adfc5217SJeff Kirsher next_tx_only = o->num_tx_only - 1; 5122adfc5217SJeff Kirsher if (next_tx_only == 0) 5123adfc5217SJeff Kirsher next_state = BNX2X_Q_STATE_ACTIVE; 5124adfc5217SJeff Kirsher else 5125adfc5217SJeff Kirsher next_state = BNX2X_Q_STATE_MULTI_COS; 5126adfc5217SJeff Kirsher } 5127adfc5217SJeff Kirsher 5128adfc5217SJeff Kirsher break; 5129adfc5217SJeff Kirsher case BNX2X_Q_STATE_INACTIVE: 5130adfc5217SJeff Kirsher if (cmd == BNX2X_Q_CMD_ACTIVATE) 5131adfc5217SJeff Kirsher next_state = BNX2X_Q_STATE_ACTIVE; 5132adfc5217SJeff Kirsher 5133adfc5217SJeff Kirsher else if ((cmd == BNX2X_Q_CMD_EMPTY) || 5134adfc5217SJeff Kirsher (cmd == BNX2X_Q_CMD_UPDATE_TPA)) 5135adfc5217SJeff Kirsher next_state = BNX2X_Q_STATE_INACTIVE; 5136adfc5217SJeff Kirsher 5137adfc5217SJeff Kirsher else if (cmd == BNX2X_Q_CMD_HALT) 5138adfc5217SJeff Kirsher next_state = BNX2X_Q_STATE_STOPPED; 5139adfc5217SJeff Kirsher 5140adfc5217SJeff Kirsher else if (cmd == BNX2X_Q_CMD_UPDATE) { 5141adfc5217SJeff Kirsher /* If "active" state change is requested, update the 5142adfc5217SJeff Kirsher * state accordingly. 5143adfc5217SJeff Kirsher */ 5144adfc5217SJeff Kirsher if (test_bit(BNX2X_Q_UPDATE_ACTIVATE_CHNG, 5145adfc5217SJeff Kirsher &update_params->update_flags) && 5146adfc5217SJeff Kirsher test_bit(BNX2X_Q_UPDATE_ACTIVATE, 5147adfc5217SJeff Kirsher &update_params->update_flags)){ 5148adfc5217SJeff Kirsher if (o->num_tx_only == 0) 5149adfc5217SJeff Kirsher next_state = BNX2X_Q_STATE_ACTIVE; 5150adfc5217SJeff Kirsher else /* tx only queues exist for this queue */ 5151adfc5217SJeff Kirsher next_state = BNX2X_Q_STATE_MULTI_COS; 5152adfc5217SJeff Kirsher } else 5153adfc5217SJeff Kirsher next_state = BNX2X_Q_STATE_INACTIVE; 5154adfc5217SJeff Kirsher } 5155adfc5217SJeff Kirsher 5156adfc5217SJeff Kirsher break; 5157adfc5217SJeff Kirsher case BNX2X_Q_STATE_STOPPED: 5158adfc5217SJeff Kirsher if (cmd == BNX2X_Q_CMD_TERMINATE) 5159adfc5217SJeff Kirsher next_state = BNX2X_Q_STATE_TERMINATED; 5160adfc5217SJeff Kirsher 5161adfc5217SJeff Kirsher break; 5162adfc5217SJeff Kirsher case BNX2X_Q_STATE_TERMINATED: 5163adfc5217SJeff Kirsher if (cmd == BNX2X_Q_CMD_CFC_DEL) 5164adfc5217SJeff Kirsher next_state = BNX2X_Q_STATE_RESET; 5165adfc5217SJeff Kirsher 5166adfc5217SJeff Kirsher break; 5167adfc5217SJeff Kirsher default: 5168adfc5217SJeff Kirsher BNX2X_ERR("Illegal state: %d\n", state); 5169adfc5217SJeff Kirsher } 5170adfc5217SJeff Kirsher 5171adfc5217SJeff Kirsher /* Transition is assured */ 5172adfc5217SJeff Kirsher if (next_state != BNX2X_Q_STATE_MAX) { 5173adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "Good state transition: %d(%d)->%d\n", 5174adfc5217SJeff Kirsher state, cmd, next_state); 5175adfc5217SJeff Kirsher o->next_state = next_state; 5176adfc5217SJeff Kirsher o->next_tx_only = next_tx_only; 5177adfc5217SJeff Kirsher return 0; 5178adfc5217SJeff Kirsher } 5179adfc5217SJeff Kirsher 5180adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "Bad state transition request: %d %d\n", state, cmd); 5181adfc5217SJeff Kirsher 5182adfc5217SJeff Kirsher return -EINVAL; 5183adfc5217SJeff Kirsher } 5184adfc5217SJeff Kirsher 5185adfc5217SJeff Kirsher void bnx2x_init_queue_obj(struct bnx2x *bp, 5186adfc5217SJeff Kirsher struct bnx2x_queue_sp_obj *obj, 5187adfc5217SJeff Kirsher u8 cl_id, u32 *cids, u8 cid_cnt, u8 func_id, 5188adfc5217SJeff Kirsher void *rdata, 5189adfc5217SJeff Kirsher dma_addr_t rdata_mapping, unsigned long type) 5190adfc5217SJeff Kirsher { 5191adfc5217SJeff Kirsher memset(obj, 0, sizeof(*obj)); 5192adfc5217SJeff Kirsher 5193adfc5217SJeff Kirsher /* We support only BNX2X_MULTI_TX_COS Tx CoS at the moment */ 5194adfc5217SJeff Kirsher BUG_ON(BNX2X_MULTI_TX_COS < cid_cnt); 5195adfc5217SJeff Kirsher 5196adfc5217SJeff Kirsher memcpy(obj->cids, cids, sizeof(obj->cids[0]) * cid_cnt); 5197adfc5217SJeff Kirsher obj->max_cos = cid_cnt; 5198adfc5217SJeff Kirsher obj->cl_id = cl_id; 5199adfc5217SJeff Kirsher obj->func_id = func_id; 5200adfc5217SJeff Kirsher obj->rdata = rdata; 5201adfc5217SJeff Kirsher obj->rdata_mapping = rdata_mapping; 5202adfc5217SJeff Kirsher obj->type = type; 5203adfc5217SJeff Kirsher obj->next_state = BNX2X_Q_STATE_MAX; 5204adfc5217SJeff Kirsher 5205adfc5217SJeff Kirsher if (CHIP_IS_E1x(bp)) 5206adfc5217SJeff Kirsher obj->send_cmd = bnx2x_queue_send_cmd_e1x; 5207adfc5217SJeff Kirsher else 5208adfc5217SJeff Kirsher obj->send_cmd = bnx2x_queue_send_cmd_e2; 5209adfc5217SJeff Kirsher 5210adfc5217SJeff Kirsher obj->check_transition = bnx2x_queue_chk_transition; 5211adfc5217SJeff Kirsher 5212adfc5217SJeff Kirsher obj->complete_cmd = bnx2x_queue_comp_cmd; 5213adfc5217SJeff Kirsher obj->wait_comp = bnx2x_queue_wait_comp; 5214adfc5217SJeff Kirsher obj->set_pending = bnx2x_queue_set_pending; 5215adfc5217SJeff Kirsher } 5216adfc5217SJeff Kirsher 521767c431a5SAriel Elior /* return a queue object's logical state*/ 521867c431a5SAriel Elior int bnx2x_get_q_logical_state(struct bnx2x *bp, 521967c431a5SAriel Elior struct bnx2x_queue_sp_obj *obj) 522067c431a5SAriel Elior { 522167c431a5SAriel Elior switch (obj->state) { 522267c431a5SAriel Elior case BNX2X_Q_STATE_ACTIVE: 522367c431a5SAriel Elior case BNX2X_Q_STATE_MULTI_COS: 522467c431a5SAriel Elior return BNX2X_Q_LOGICAL_STATE_ACTIVE; 522567c431a5SAriel Elior case BNX2X_Q_STATE_RESET: 522667c431a5SAriel Elior case BNX2X_Q_STATE_INITIALIZED: 522767c431a5SAriel Elior case BNX2X_Q_STATE_MCOS_TERMINATED: 522867c431a5SAriel Elior case BNX2X_Q_STATE_INACTIVE: 522967c431a5SAriel Elior case BNX2X_Q_STATE_STOPPED: 523067c431a5SAriel Elior case BNX2X_Q_STATE_TERMINATED: 523167c431a5SAriel Elior case BNX2X_Q_STATE_FLRED: 523267c431a5SAriel Elior return BNX2X_Q_LOGICAL_STATE_STOPPED; 523367c431a5SAriel Elior default: 523467c431a5SAriel Elior return -EINVAL; 523567c431a5SAriel Elior } 523667c431a5SAriel Elior } 523767c431a5SAriel Elior 5238adfc5217SJeff Kirsher /********************** Function state object *********************************/ 5239adfc5217SJeff Kirsher enum bnx2x_func_state bnx2x_func_get_state(struct bnx2x *bp, 5240adfc5217SJeff Kirsher struct bnx2x_func_sp_obj *o) 5241adfc5217SJeff Kirsher { 5242adfc5217SJeff Kirsher /* in the middle of transaction - return INVALID state */ 5243adfc5217SJeff Kirsher if (o->pending) 5244adfc5217SJeff Kirsher return BNX2X_F_STATE_MAX; 5245adfc5217SJeff Kirsher 524616a5fd92SYuval Mintz /* unsure the order of reading of o->pending and o->state 5247adfc5217SJeff Kirsher * o->pending should be read first 5248adfc5217SJeff Kirsher */ 5249adfc5217SJeff Kirsher rmb(); 5250adfc5217SJeff Kirsher 5251adfc5217SJeff Kirsher return o->state; 5252adfc5217SJeff Kirsher } 5253adfc5217SJeff Kirsher 5254adfc5217SJeff Kirsher static int bnx2x_func_wait_comp(struct bnx2x *bp, 5255adfc5217SJeff Kirsher struct bnx2x_func_sp_obj *o, 5256adfc5217SJeff Kirsher enum bnx2x_func_cmd cmd) 5257adfc5217SJeff Kirsher { 5258adfc5217SJeff Kirsher return bnx2x_state_wait(bp, cmd, &o->pending); 5259adfc5217SJeff Kirsher } 5260adfc5217SJeff Kirsher 5261adfc5217SJeff Kirsher /** 5262adfc5217SJeff Kirsher * bnx2x_func_state_change_comp - complete the state machine transition 5263adfc5217SJeff Kirsher * 5264adfc5217SJeff Kirsher * @bp: device handle 5265adfc5217SJeff Kirsher * @o: 5266adfc5217SJeff Kirsher * @cmd: 5267adfc5217SJeff Kirsher * 5268adfc5217SJeff Kirsher * Called on state change transition. Completes the state 5269adfc5217SJeff Kirsher * machine transition only - no HW interaction. 5270adfc5217SJeff Kirsher */ 5271adfc5217SJeff Kirsher static inline int bnx2x_func_state_change_comp(struct bnx2x *bp, 5272adfc5217SJeff Kirsher struct bnx2x_func_sp_obj *o, 5273adfc5217SJeff Kirsher enum bnx2x_func_cmd cmd) 5274adfc5217SJeff Kirsher { 5275adfc5217SJeff Kirsher unsigned long cur_pending = o->pending; 5276adfc5217SJeff Kirsher 5277adfc5217SJeff Kirsher if (!test_and_clear_bit(cmd, &cur_pending)) { 527851c1a580SMerav Sicron BNX2X_ERR("Bad MC reply %d for func %d in state %d pending 0x%lx, next_state %d\n", 527951c1a580SMerav Sicron cmd, BP_FUNC(bp), o->state, 528051c1a580SMerav Sicron cur_pending, o->next_state); 5281adfc5217SJeff Kirsher return -EINVAL; 5282adfc5217SJeff Kirsher } 5283adfc5217SJeff Kirsher 528494f05b0fSJoe Perches DP(BNX2X_MSG_SP, 528594f05b0fSJoe Perches "Completing command %d for func %d, setting state to %d\n", 528694f05b0fSJoe Perches cmd, BP_FUNC(bp), o->next_state); 5287adfc5217SJeff Kirsher 5288adfc5217SJeff Kirsher o->state = o->next_state; 5289adfc5217SJeff Kirsher o->next_state = BNX2X_F_STATE_MAX; 5290adfc5217SJeff Kirsher 5291adfc5217SJeff Kirsher /* It's important that o->state and o->next_state are 5292adfc5217SJeff Kirsher * updated before o->pending. 5293adfc5217SJeff Kirsher */ 5294adfc5217SJeff Kirsher wmb(); 5295adfc5217SJeff Kirsher 5296adfc5217SJeff Kirsher clear_bit(cmd, &o->pending); 52974e857c58SPeter Zijlstra smp_mb__after_atomic(); 5298adfc5217SJeff Kirsher 5299adfc5217SJeff Kirsher return 0; 5300adfc5217SJeff Kirsher } 5301adfc5217SJeff Kirsher 5302adfc5217SJeff Kirsher /** 5303adfc5217SJeff Kirsher * bnx2x_func_comp_cmd - complete the state change command 5304adfc5217SJeff Kirsher * 5305adfc5217SJeff Kirsher * @bp: device handle 5306adfc5217SJeff Kirsher * @o: 5307adfc5217SJeff Kirsher * @cmd: 5308adfc5217SJeff Kirsher * 5309adfc5217SJeff Kirsher * Checks that the arrived completion is expected. 5310adfc5217SJeff Kirsher */ 5311adfc5217SJeff Kirsher static int bnx2x_func_comp_cmd(struct bnx2x *bp, 5312adfc5217SJeff Kirsher struct bnx2x_func_sp_obj *o, 5313adfc5217SJeff Kirsher enum bnx2x_func_cmd cmd) 5314adfc5217SJeff Kirsher { 5315adfc5217SJeff Kirsher /* Complete the state machine part first, check if it's a 5316adfc5217SJeff Kirsher * legal completion. 5317adfc5217SJeff Kirsher */ 5318adfc5217SJeff Kirsher int rc = bnx2x_func_state_change_comp(bp, o, cmd); 5319adfc5217SJeff Kirsher return rc; 5320adfc5217SJeff Kirsher } 5321adfc5217SJeff Kirsher 5322adfc5217SJeff Kirsher /** 5323adfc5217SJeff Kirsher * bnx2x_func_chk_transition - perform function state machine transition 5324adfc5217SJeff Kirsher * 5325adfc5217SJeff Kirsher * @bp: device handle 5326adfc5217SJeff Kirsher * @o: 5327adfc5217SJeff Kirsher * @params: 5328adfc5217SJeff Kirsher * 5329adfc5217SJeff Kirsher * It both checks if the requested command is legal in a current 5330adfc5217SJeff Kirsher * state and, if it's legal, sets a `next_state' in the object 5331adfc5217SJeff Kirsher * that will be used in the completion flow to set the `state' 5332adfc5217SJeff Kirsher * of the object. 5333adfc5217SJeff Kirsher * 5334adfc5217SJeff Kirsher * returns 0 if a requested command is a legal transition, 5335adfc5217SJeff Kirsher * -EINVAL otherwise. 5336adfc5217SJeff Kirsher */ 5337adfc5217SJeff Kirsher static int bnx2x_func_chk_transition(struct bnx2x *bp, 5338adfc5217SJeff Kirsher struct bnx2x_func_sp_obj *o, 5339adfc5217SJeff Kirsher struct bnx2x_func_state_params *params) 5340adfc5217SJeff Kirsher { 5341adfc5217SJeff Kirsher enum bnx2x_func_state state = o->state, next_state = BNX2X_F_STATE_MAX; 5342adfc5217SJeff Kirsher enum bnx2x_func_cmd cmd = params->cmd; 5343adfc5217SJeff Kirsher 534416a5fd92SYuval Mintz /* Forget all pending for completion commands if a driver only state 5345adfc5217SJeff Kirsher * transition has been requested. 5346adfc5217SJeff Kirsher */ 5347adfc5217SJeff Kirsher if (test_bit(RAMROD_DRV_CLR_ONLY, ¶ms->ramrod_flags)) { 5348adfc5217SJeff Kirsher o->pending = 0; 5349adfc5217SJeff Kirsher o->next_state = BNX2X_F_STATE_MAX; 5350adfc5217SJeff Kirsher } 5351adfc5217SJeff Kirsher 535216a5fd92SYuval Mintz /* Don't allow a next state transition if we are in the middle of 5353adfc5217SJeff Kirsher * the previous one. 5354adfc5217SJeff Kirsher */ 5355adfc5217SJeff Kirsher if (o->pending) 5356adfc5217SJeff Kirsher return -EBUSY; 5357adfc5217SJeff Kirsher 5358adfc5217SJeff Kirsher switch (state) { 5359adfc5217SJeff Kirsher case BNX2X_F_STATE_RESET: 5360adfc5217SJeff Kirsher if (cmd == BNX2X_F_CMD_HW_INIT) 5361adfc5217SJeff Kirsher next_state = BNX2X_F_STATE_INITIALIZED; 5362adfc5217SJeff Kirsher 5363adfc5217SJeff Kirsher break; 5364adfc5217SJeff Kirsher case BNX2X_F_STATE_INITIALIZED: 5365adfc5217SJeff Kirsher if (cmd == BNX2X_F_CMD_START) 5366adfc5217SJeff Kirsher next_state = BNX2X_F_STATE_STARTED; 5367adfc5217SJeff Kirsher 5368adfc5217SJeff Kirsher else if (cmd == BNX2X_F_CMD_HW_RESET) 5369adfc5217SJeff Kirsher next_state = BNX2X_F_STATE_RESET; 5370adfc5217SJeff Kirsher 5371adfc5217SJeff Kirsher break; 5372adfc5217SJeff Kirsher case BNX2X_F_STATE_STARTED: 5373adfc5217SJeff Kirsher if (cmd == BNX2X_F_CMD_STOP) 5374adfc5217SJeff Kirsher next_state = BNX2X_F_STATE_INITIALIZED; 5375a3348722SBarak Witkowski /* afex ramrods can be sent only in started mode, and only 5376a3348722SBarak Witkowski * if not pending for function_stop ramrod completion 5377a3348722SBarak Witkowski * for these events - next state remained STARTED. 5378a3348722SBarak Witkowski */ 5379a3348722SBarak Witkowski else if ((cmd == BNX2X_F_CMD_AFEX_UPDATE) && 5380a3348722SBarak Witkowski (!test_bit(BNX2X_F_CMD_STOP, &o->pending))) 5381a3348722SBarak Witkowski next_state = BNX2X_F_STATE_STARTED; 5382a3348722SBarak Witkowski 5383a3348722SBarak Witkowski else if ((cmd == BNX2X_F_CMD_AFEX_VIFLISTS) && 5384a3348722SBarak Witkowski (!test_bit(BNX2X_F_CMD_STOP, &o->pending))) 5385a3348722SBarak Witkowski next_state = BNX2X_F_STATE_STARTED; 538655c11941SMerav Sicron 538755c11941SMerav Sicron /* Switch_update ramrod can be sent in either started or 538855c11941SMerav Sicron * tx_stopped state, and it doesn't change the state. 538955c11941SMerav Sicron */ 539055c11941SMerav Sicron else if ((cmd == BNX2X_F_CMD_SWITCH_UPDATE) && 539155c11941SMerav Sicron (!test_bit(BNX2X_F_CMD_STOP, &o->pending))) 539255c11941SMerav Sicron next_state = BNX2X_F_STATE_STARTED; 539355c11941SMerav Sicron 5394eeed018cSMichal Kalderon else if ((cmd == BNX2X_F_CMD_SET_TIMESYNC) && 5395eeed018cSMichal Kalderon (!test_bit(BNX2X_F_CMD_STOP, &o->pending))) 5396eeed018cSMichal Kalderon next_state = BNX2X_F_STATE_STARTED; 5397eeed018cSMichal Kalderon 5398adfc5217SJeff Kirsher else if (cmd == BNX2X_F_CMD_TX_STOP) 5399adfc5217SJeff Kirsher next_state = BNX2X_F_STATE_TX_STOPPED; 5400adfc5217SJeff Kirsher 5401adfc5217SJeff Kirsher break; 5402adfc5217SJeff Kirsher case BNX2X_F_STATE_TX_STOPPED: 540355c11941SMerav Sicron if ((cmd == BNX2X_F_CMD_SWITCH_UPDATE) && 540455c11941SMerav Sicron (!test_bit(BNX2X_F_CMD_STOP, &o->pending))) 540555c11941SMerav Sicron next_state = BNX2X_F_STATE_TX_STOPPED; 540655c11941SMerav Sicron 5407eeed018cSMichal Kalderon else if ((cmd == BNX2X_F_CMD_SET_TIMESYNC) && 5408eeed018cSMichal Kalderon (!test_bit(BNX2X_F_CMD_STOP, &o->pending))) 5409eeed018cSMichal Kalderon next_state = BNX2X_F_STATE_TX_STOPPED; 5410eeed018cSMichal Kalderon 541155c11941SMerav Sicron else if (cmd == BNX2X_F_CMD_TX_START) 5412adfc5217SJeff Kirsher next_state = BNX2X_F_STATE_STARTED; 5413adfc5217SJeff Kirsher 5414adfc5217SJeff Kirsher break; 5415adfc5217SJeff Kirsher default: 5416adfc5217SJeff Kirsher BNX2X_ERR("Unknown state: %d\n", state); 5417adfc5217SJeff Kirsher } 5418adfc5217SJeff Kirsher 5419adfc5217SJeff Kirsher /* Transition is assured */ 5420adfc5217SJeff Kirsher if (next_state != BNX2X_F_STATE_MAX) { 5421adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "Good function state transition: %d(%d)->%d\n", 5422adfc5217SJeff Kirsher state, cmd, next_state); 5423adfc5217SJeff Kirsher o->next_state = next_state; 5424adfc5217SJeff Kirsher return 0; 5425adfc5217SJeff Kirsher } 5426adfc5217SJeff Kirsher 5427adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "Bad function state transition request: %d %d\n", 5428adfc5217SJeff Kirsher state, cmd); 5429adfc5217SJeff Kirsher 5430adfc5217SJeff Kirsher return -EINVAL; 5431adfc5217SJeff Kirsher } 5432adfc5217SJeff Kirsher 5433adfc5217SJeff Kirsher /** 5434adfc5217SJeff Kirsher * bnx2x_func_init_func - performs HW init at function stage 5435adfc5217SJeff Kirsher * 5436adfc5217SJeff Kirsher * @bp: device handle 5437adfc5217SJeff Kirsher * @drv: 5438adfc5217SJeff Kirsher * 5439adfc5217SJeff Kirsher * Init HW when the current phase is 5440adfc5217SJeff Kirsher * FW_MSG_CODE_DRV_LOAD_FUNCTION: initialize only FUNCTION-only 5441adfc5217SJeff Kirsher * HW blocks. 5442adfc5217SJeff Kirsher */ 5443adfc5217SJeff Kirsher static inline int bnx2x_func_init_func(struct bnx2x *bp, 5444adfc5217SJeff Kirsher const struct bnx2x_func_sp_drv_ops *drv) 5445adfc5217SJeff Kirsher { 5446adfc5217SJeff Kirsher return drv->init_hw_func(bp); 5447adfc5217SJeff Kirsher } 5448adfc5217SJeff Kirsher 5449adfc5217SJeff Kirsher /** 5450adfc5217SJeff Kirsher * bnx2x_func_init_port - performs HW init at port stage 5451adfc5217SJeff Kirsher * 5452adfc5217SJeff Kirsher * @bp: device handle 5453adfc5217SJeff Kirsher * @drv: 5454adfc5217SJeff Kirsher * 5455adfc5217SJeff Kirsher * Init HW when the current phase is 5456adfc5217SJeff Kirsher * FW_MSG_CODE_DRV_LOAD_PORT: initialize PORT-only and 5457adfc5217SJeff Kirsher * FUNCTION-only HW blocks. 5458adfc5217SJeff Kirsher * 5459adfc5217SJeff Kirsher */ 5460adfc5217SJeff Kirsher static inline int bnx2x_func_init_port(struct bnx2x *bp, 5461adfc5217SJeff Kirsher const struct bnx2x_func_sp_drv_ops *drv) 5462adfc5217SJeff Kirsher { 5463adfc5217SJeff Kirsher int rc = drv->init_hw_port(bp); 5464adfc5217SJeff Kirsher if (rc) 5465adfc5217SJeff Kirsher return rc; 5466adfc5217SJeff Kirsher 5467adfc5217SJeff Kirsher return bnx2x_func_init_func(bp, drv); 5468adfc5217SJeff Kirsher } 5469adfc5217SJeff Kirsher 5470adfc5217SJeff Kirsher /** 5471adfc5217SJeff Kirsher * bnx2x_func_init_cmn_chip - performs HW init at chip-common stage 5472adfc5217SJeff Kirsher * 5473adfc5217SJeff Kirsher * @bp: device handle 5474adfc5217SJeff Kirsher * @drv: 5475adfc5217SJeff Kirsher * 5476adfc5217SJeff Kirsher * Init HW when the current phase is 5477adfc5217SJeff Kirsher * FW_MSG_CODE_DRV_LOAD_COMMON_CHIP: initialize COMMON_CHIP, 5478adfc5217SJeff Kirsher * PORT-only and FUNCTION-only HW blocks. 5479adfc5217SJeff Kirsher */ 5480adfc5217SJeff Kirsher static inline int bnx2x_func_init_cmn_chip(struct bnx2x *bp, 5481adfc5217SJeff Kirsher const struct bnx2x_func_sp_drv_ops *drv) 5482adfc5217SJeff Kirsher { 5483adfc5217SJeff Kirsher int rc = drv->init_hw_cmn_chip(bp); 5484adfc5217SJeff Kirsher if (rc) 5485adfc5217SJeff Kirsher return rc; 5486adfc5217SJeff Kirsher 5487adfc5217SJeff Kirsher return bnx2x_func_init_port(bp, drv); 5488adfc5217SJeff Kirsher } 5489adfc5217SJeff Kirsher 5490adfc5217SJeff Kirsher /** 5491adfc5217SJeff Kirsher * bnx2x_func_init_cmn - performs HW init at common stage 5492adfc5217SJeff Kirsher * 5493adfc5217SJeff Kirsher * @bp: device handle 5494adfc5217SJeff Kirsher * @drv: 5495adfc5217SJeff Kirsher * 5496adfc5217SJeff Kirsher * Init HW when the current phase is 5497adfc5217SJeff Kirsher * FW_MSG_CODE_DRV_LOAD_COMMON_CHIP: initialize COMMON, 5498adfc5217SJeff Kirsher * PORT-only and FUNCTION-only HW blocks. 5499adfc5217SJeff Kirsher */ 5500adfc5217SJeff Kirsher static inline int bnx2x_func_init_cmn(struct bnx2x *bp, 5501adfc5217SJeff Kirsher const struct bnx2x_func_sp_drv_ops *drv) 5502adfc5217SJeff Kirsher { 5503adfc5217SJeff Kirsher int rc = drv->init_hw_cmn(bp); 5504adfc5217SJeff Kirsher if (rc) 5505adfc5217SJeff Kirsher return rc; 5506adfc5217SJeff Kirsher 5507adfc5217SJeff Kirsher return bnx2x_func_init_port(bp, drv); 5508adfc5217SJeff Kirsher } 5509adfc5217SJeff Kirsher 5510adfc5217SJeff Kirsher static int bnx2x_func_hw_init(struct bnx2x *bp, 5511adfc5217SJeff Kirsher struct bnx2x_func_state_params *params) 5512adfc5217SJeff Kirsher { 5513adfc5217SJeff Kirsher u32 load_code = params->params.hw_init.load_phase; 5514adfc5217SJeff Kirsher struct bnx2x_func_sp_obj *o = params->f_obj; 5515adfc5217SJeff Kirsher const struct bnx2x_func_sp_drv_ops *drv = o->drv; 5516adfc5217SJeff Kirsher int rc = 0; 5517adfc5217SJeff Kirsher 5518adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "function %d load_code %x\n", 5519adfc5217SJeff Kirsher BP_ABS_FUNC(bp), load_code); 5520adfc5217SJeff Kirsher 5521adfc5217SJeff Kirsher /* Prepare buffers for unzipping the FW */ 5522adfc5217SJeff Kirsher rc = drv->gunzip_init(bp); 5523adfc5217SJeff Kirsher if (rc) 5524adfc5217SJeff Kirsher return rc; 5525adfc5217SJeff Kirsher 5526adfc5217SJeff Kirsher /* Prepare FW */ 5527adfc5217SJeff Kirsher rc = drv->init_fw(bp); 5528adfc5217SJeff Kirsher if (rc) { 5529adfc5217SJeff Kirsher BNX2X_ERR("Error loading firmware\n"); 5530eb2afd4aSDmitry Kravkov goto init_err; 5531adfc5217SJeff Kirsher } 5532adfc5217SJeff Kirsher 553316a5fd92SYuval Mintz /* Handle the beginning of COMMON_XXX pases separately... */ 5534adfc5217SJeff Kirsher switch (load_code) { 5535adfc5217SJeff Kirsher case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP: 5536adfc5217SJeff Kirsher rc = bnx2x_func_init_cmn_chip(bp, drv); 5537adfc5217SJeff Kirsher if (rc) 5538eb2afd4aSDmitry Kravkov goto init_err; 5539adfc5217SJeff Kirsher 5540adfc5217SJeff Kirsher break; 5541adfc5217SJeff Kirsher case FW_MSG_CODE_DRV_LOAD_COMMON: 5542adfc5217SJeff Kirsher rc = bnx2x_func_init_cmn(bp, drv); 5543adfc5217SJeff Kirsher if (rc) 5544eb2afd4aSDmitry Kravkov goto init_err; 5545adfc5217SJeff Kirsher 5546adfc5217SJeff Kirsher break; 5547adfc5217SJeff Kirsher case FW_MSG_CODE_DRV_LOAD_PORT: 5548adfc5217SJeff Kirsher rc = bnx2x_func_init_port(bp, drv); 5549adfc5217SJeff Kirsher if (rc) 5550eb2afd4aSDmitry Kravkov goto init_err; 5551adfc5217SJeff Kirsher 5552adfc5217SJeff Kirsher break; 5553adfc5217SJeff Kirsher case FW_MSG_CODE_DRV_LOAD_FUNCTION: 5554adfc5217SJeff Kirsher rc = bnx2x_func_init_func(bp, drv); 5555adfc5217SJeff Kirsher if (rc) 5556eb2afd4aSDmitry Kravkov goto init_err; 5557adfc5217SJeff Kirsher 5558adfc5217SJeff Kirsher break; 5559adfc5217SJeff Kirsher default: 5560adfc5217SJeff Kirsher BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code); 5561adfc5217SJeff Kirsher rc = -EINVAL; 5562adfc5217SJeff Kirsher } 5563adfc5217SJeff Kirsher 5564eb2afd4aSDmitry Kravkov init_err: 5565adfc5217SJeff Kirsher drv->gunzip_end(bp); 5566adfc5217SJeff Kirsher 556716a5fd92SYuval Mintz /* In case of success, complete the command immediately: no ramrods 5568adfc5217SJeff Kirsher * have been sent. 5569adfc5217SJeff Kirsher */ 5570adfc5217SJeff Kirsher if (!rc) 5571adfc5217SJeff Kirsher o->complete_cmd(bp, o, BNX2X_F_CMD_HW_INIT); 5572adfc5217SJeff Kirsher 5573adfc5217SJeff Kirsher return rc; 5574adfc5217SJeff Kirsher } 5575adfc5217SJeff Kirsher 5576adfc5217SJeff Kirsher /** 5577adfc5217SJeff Kirsher * bnx2x_func_reset_func - reset HW at function stage 5578adfc5217SJeff Kirsher * 5579adfc5217SJeff Kirsher * @bp: device handle 5580adfc5217SJeff Kirsher * @drv: 5581adfc5217SJeff Kirsher * 5582adfc5217SJeff Kirsher * Reset HW at FW_MSG_CODE_DRV_UNLOAD_FUNCTION stage: reset only 5583adfc5217SJeff Kirsher * FUNCTION-only HW blocks. 5584adfc5217SJeff Kirsher */ 5585adfc5217SJeff Kirsher static inline void bnx2x_func_reset_func(struct bnx2x *bp, 5586adfc5217SJeff Kirsher const struct bnx2x_func_sp_drv_ops *drv) 5587adfc5217SJeff Kirsher { 5588adfc5217SJeff Kirsher drv->reset_hw_func(bp); 5589adfc5217SJeff Kirsher } 5590adfc5217SJeff Kirsher 5591adfc5217SJeff Kirsher /** 559216a5fd92SYuval Mintz * bnx2x_func_reset_port - reset HW at port stage 5593adfc5217SJeff Kirsher * 5594adfc5217SJeff Kirsher * @bp: device handle 5595adfc5217SJeff Kirsher * @drv: 5596adfc5217SJeff Kirsher * 5597adfc5217SJeff Kirsher * Reset HW at FW_MSG_CODE_DRV_UNLOAD_PORT stage: reset 5598adfc5217SJeff Kirsher * FUNCTION-only and PORT-only HW blocks. 5599adfc5217SJeff Kirsher * 5600adfc5217SJeff Kirsher * !!!IMPORTANT!!! 5601adfc5217SJeff Kirsher * 5602adfc5217SJeff Kirsher * It's important to call reset_port before reset_func() as the last thing 5603adfc5217SJeff Kirsher * reset_func does is pf_disable() thus disabling PGLUE_B, which 5604adfc5217SJeff Kirsher * makes impossible any DMAE transactions. 5605adfc5217SJeff Kirsher */ 5606adfc5217SJeff Kirsher static inline void bnx2x_func_reset_port(struct bnx2x *bp, 5607adfc5217SJeff Kirsher const struct bnx2x_func_sp_drv_ops *drv) 5608adfc5217SJeff Kirsher { 5609adfc5217SJeff Kirsher drv->reset_hw_port(bp); 5610adfc5217SJeff Kirsher bnx2x_func_reset_func(bp, drv); 5611adfc5217SJeff Kirsher } 5612adfc5217SJeff Kirsher 5613adfc5217SJeff Kirsher /** 561416a5fd92SYuval Mintz * bnx2x_func_reset_cmn - reset HW at common stage 5615adfc5217SJeff Kirsher * 5616adfc5217SJeff Kirsher * @bp: device handle 5617adfc5217SJeff Kirsher * @drv: 5618adfc5217SJeff Kirsher * 5619adfc5217SJeff Kirsher * Reset HW at FW_MSG_CODE_DRV_UNLOAD_COMMON and 5620adfc5217SJeff Kirsher * FW_MSG_CODE_DRV_UNLOAD_COMMON_CHIP stages: reset COMMON, 5621adfc5217SJeff Kirsher * COMMON_CHIP, FUNCTION-only and PORT-only HW blocks. 5622adfc5217SJeff Kirsher */ 5623adfc5217SJeff Kirsher static inline void bnx2x_func_reset_cmn(struct bnx2x *bp, 5624adfc5217SJeff Kirsher const struct bnx2x_func_sp_drv_ops *drv) 5625adfc5217SJeff Kirsher { 5626adfc5217SJeff Kirsher bnx2x_func_reset_port(bp, drv); 5627adfc5217SJeff Kirsher drv->reset_hw_cmn(bp); 5628adfc5217SJeff Kirsher } 5629adfc5217SJeff Kirsher 5630adfc5217SJeff Kirsher static inline int bnx2x_func_hw_reset(struct bnx2x *bp, 5631adfc5217SJeff Kirsher struct bnx2x_func_state_params *params) 5632adfc5217SJeff Kirsher { 5633adfc5217SJeff Kirsher u32 reset_phase = params->params.hw_reset.reset_phase; 5634adfc5217SJeff Kirsher struct bnx2x_func_sp_obj *o = params->f_obj; 5635adfc5217SJeff Kirsher const struct bnx2x_func_sp_drv_ops *drv = o->drv; 5636adfc5217SJeff Kirsher 5637adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "function %d reset_phase %x\n", BP_ABS_FUNC(bp), 5638adfc5217SJeff Kirsher reset_phase); 5639adfc5217SJeff Kirsher 5640adfc5217SJeff Kirsher switch (reset_phase) { 5641adfc5217SJeff Kirsher case FW_MSG_CODE_DRV_UNLOAD_COMMON: 5642adfc5217SJeff Kirsher bnx2x_func_reset_cmn(bp, drv); 5643adfc5217SJeff Kirsher break; 5644adfc5217SJeff Kirsher case FW_MSG_CODE_DRV_UNLOAD_PORT: 5645adfc5217SJeff Kirsher bnx2x_func_reset_port(bp, drv); 5646adfc5217SJeff Kirsher break; 5647adfc5217SJeff Kirsher case FW_MSG_CODE_DRV_UNLOAD_FUNCTION: 5648adfc5217SJeff Kirsher bnx2x_func_reset_func(bp, drv); 5649adfc5217SJeff Kirsher break; 5650adfc5217SJeff Kirsher default: 5651adfc5217SJeff Kirsher BNX2X_ERR("Unknown reset_phase (0x%x) from MCP\n", 5652adfc5217SJeff Kirsher reset_phase); 5653adfc5217SJeff Kirsher break; 5654adfc5217SJeff Kirsher } 5655adfc5217SJeff Kirsher 565616a5fd92SYuval Mintz /* Complete the command immediately: no ramrods have been sent. */ 5657adfc5217SJeff Kirsher o->complete_cmd(bp, o, BNX2X_F_CMD_HW_RESET); 5658adfc5217SJeff Kirsher 5659adfc5217SJeff Kirsher return 0; 5660adfc5217SJeff Kirsher } 5661adfc5217SJeff Kirsher 5662adfc5217SJeff Kirsher static inline int bnx2x_func_send_start(struct bnx2x *bp, 5663adfc5217SJeff Kirsher struct bnx2x_func_state_params *params) 5664adfc5217SJeff Kirsher { 5665adfc5217SJeff Kirsher struct bnx2x_func_sp_obj *o = params->f_obj; 5666adfc5217SJeff Kirsher struct function_start_data *rdata = 5667adfc5217SJeff Kirsher (struct function_start_data *)o->rdata; 5668adfc5217SJeff Kirsher dma_addr_t data_mapping = o->rdata_mapping; 5669adfc5217SJeff Kirsher struct bnx2x_func_start_params *start_params = ¶ms->params.start; 5670adfc5217SJeff Kirsher 5671adfc5217SJeff Kirsher memset(rdata, 0, sizeof(*rdata)); 5672adfc5217SJeff Kirsher 5673adfc5217SJeff Kirsher /* Fill the ramrod data with provided parameters */ 567496bed4b9SYuval Mintz rdata->function_mode = (u8)start_params->mf_mode; 5675ab4a7139SAriel Elior rdata->sd_vlan_tag = cpu_to_le16(start_params->sd_vlan_tag); 5676adfc5217SJeff Kirsher rdata->path_id = BP_PATH(bp); 5677adfc5217SJeff Kirsher rdata->network_cos_mode = start_params->network_cos_mode; 567828311f8eSYuval Mintz 567928311f8eSYuval Mintz rdata->vxlan_dst_port = cpu_to_le16(start_params->vxlan_dst_port); 568028311f8eSYuval Mintz rdata->geneve_dst_port = cpu_to_le16(start_params->geneve_dst_port); 568128311f8eSYuval Mintz rdata->inner_clss_l2gre = start_params->inner_clss_l2gre; 568228311f8eSYuval Mintz rdata->inner_clss_l2geneve = start_params->inner_clss_l2geneve; 568328311f8eSYuval Mintz rdata->inner_clss_vxlan = start_params->inner_clss_vxlan; 568428311f8eSYuval Mintz rdata->inner_rss = start_params->inner_rss; 568528311f8eSYuval Mintz 56867609647eSYuval Mintz rdata->sd_accept_mf_clss_fail = start_params->class_fail; 56877609647eSYuval Mintz if (start_params->class_fail_ethtype) { 56887609647eSYuval Mintz rdata->sd_accept_mf_clss_fail_match_ethtype = 1; 56897609647eSYuval Mintz rdata->sd_accept_mf_clss_fail_ethtype = 56907609647eSYuval Mintz cpu_to_le16(start_params->class_fail_ethtype); 56917609647eSYuval Mintz } 5692adfc5217SJeff Kirsher 56937609647eSYuval Mintz rdata->sd_vlan_force_pri_flg = start_params->sd_vlan_force_pri; 56947609647eSYuval Mintz rdata->sd_vlan_force_pri_val = start_params->sd_vlan_force_pri_val; 56957609647eSYuval Mintz if (start_params->sd_vlan_eth_type) 56967609647eSYuval Mintz rdata->sd_vlan_eth_type = 56977609647eSYuval Mintz cpu_to_le16(start_params->sd_vlan_eth_type); 56987609647eSYuval Mintz else 56997609647eSYuval Mintz rdata->sd_vlan_eth_type = 57007609647eSYuval Mintz cpu_to_le16(0x8100); 57017609647eSYuval Mintz 57027609647eSYuval Mintz rdata->no_added_tags = start_params->no_added_tags; 570328311f8eSYuval Mintz 570428311f8eSYuval Mintz rdata->c2s_pri_tt_valid = start_params->c2s_pri_valid; 570528311f8eSYuval Mintz if (rdata->c2s_pri_tt_valid) { 570628311f8eSYuval Mintz memcpy(rdata->c2s_pri_trans_table.val, 570728311f8eSYuval Mintz start_params->c2s_pri, 570828311f8eSYuval Mintz MAX_VLAN_PRIORITIES); 570928311f8eSYuval Mintz rdata->c2s_pri_default = start_params->c2s_pri_default; 571028311f8eSYuval Mintz } 57111bc277f7SDmitry Kravkov /* No need for an explicit memory barrier here as long we would 5712adfc5217SJeff Kirsher * need to ensure the ordering of writing to the SPQ element 5713adfc5217SJeff Kirsher * and updating of the SPQ producer which involves a memory 5714adfc5217SJeff Kirsher * read and we will have to put a full memory barrier there 5715adfc5217SJeff Kirsher * (inside bnx2x_sp_post()). 5716adfc5217SJeff Kirsher */ 5717adfc5217SJeff Kirsher 5718adfc5217SJeff Kirsher return bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_FUNCTION_START, 0, 5719adfc5217SJeff Kirsher U64_HI(data_mapping), 5720adfc5217SJeff Kirsher U64_LO(data_mapping), NONE_CONNECTION_TYPE); 5721adfc5217SJeff Kirsher } 5722adfc5217SJeff Kirsher 572355c11941SMerav Sicron static inline int bnx2x_func_send_switch_update(struct bnx2x *bp, 572455c11941SMerav Sicron struct bnx2x_func_state_params *params) 572555c11941SMerav Sicron { 572655c11941SMerav Sicron struct bnx2x_func_sp_obj *o = params->f_obj; 572755c11941SMerav Sicron struct function_update_data *rdata = 572855c11941SMerav Sicron (struct function_update_data *)o->rdata; 572955c11941SMerav Sicron dma_addr_t data_mapping = o->rdata_mapping; 573055c11941SMerav Sicron struct bnx2x_func_switch_update_params *switch_update_params = 573155c11941SMerav Sicron ¶ms->params.switch_update; 573255c11941SMerav Sicron 573355c11941SMerav Sicron memset(rdata, 0, sizeof(*rdata)); 573455c11941SMerav Sicron 573555c11941SMerav Sicron /* Fill the ramrod data with provided parameters */ 5736e42780b6SDmitry Kravkov if (test_bit(BNX2X_F_UPDATE_TX_SWITCH_SUSPEND_CHNG, 5737e42780b6SDmitry Kravkov &switch_update_params->changes)) { 573855c11941SMerav Sicron rdata->tx_switch_suspend_change_flg = 1; 5739e42780b6SDmitry Kravkov rdata->tx_switch_suspend = 5740e42780b6SDmitry Kravkov test_bit(BNX2X_F_UPDATE_TX_SWITCH_SUSPEND, 5741e42780b6SDmitry Kravkov &switch_update_params->changes); 5742e42780b6SDmitry Kravkov } 5743e42780b6SDmitry Kravkov 57447609647eSYuval Mintz if (test_bit(BNX2X_F_UPDATE_SD_VLAN_TAG_CHNG, 57457609647eSYuval Mintz &switch_update_params->changes)) { 57467609647eSYuval Mintz rdata->sd_vlan_tag_change_flg = 1; 57477609647eSYuval Mintz rdata->sd_vlan_tag = 57487609647eSYuval Mintz cpu_to_le16(switch_update_params->vlan); 57497609647eSYuval Mintz } 57507609647eSYuval Mintz 57517609647eSYuval Mintz if (test_bit(BNX2X_F_UPDATE_SD_VLAN_ETH_TYPE_CHNG, 57527609647eSYuval Mintz &switch_update_params->changes)) { 57537609647eSYuval Mintz rdata->sd_vlan_eth_type_change_flg = 1; 57547609647eSYuval Mintz rdata->sd_vlan_eth_type = 57557609647eSYuval Mintz cpu_to_le16(switch_update_params->vlan_eth_type); 57567609647eSYuval Mintz } 57577609647eSYuval Mintz 57587609647eSYuval Mintz if (test_bit(BNX2X_F_UPDATE_VLAN_FORCE_PRIO_CHNG, 57597609647eSYuval Mintz &switch_update_params->changes)) { 57607609647eSYuval Mintz rdata->sd_vlan_force_pri_change_flg = 1; 57617609647eSYuval Mintz if (test_bit(BNX2X_F_UPDATE_VLAN_FORCE_PRIO_FLAG, 57627609647eSYuval Mintz &switch_update_params->changes)) 57637609647eSYuval Mintz rdata->sd_vlan_force_pri_flg = 1; 57647609647eSYuval Mintz rdata->sd_vlan_force_pri_flg = 57657609647eSYuval Mintz switch_update_params->vlan_force_prio; 57667609647eSYuval Mintz } 57677609647eSYuval Mintz 5768e42780b6SDmitry Kravkov if (test_bit(BNX2X_F_UPDATE_TUNNEL_CFG_CHNG, 5769e42780b6SDmitry Kravkov &switch_update_params->changes)) { 5770e42780b6SDmitry Kravkov rdata->update_tunn_cfg_flg = 1; 577128311f8eSYuval Mintz if (test_bit(BNX2X_F_UPDATE_TUNNEL_INNER_CLSS_L2GRE, 5772e42780b6SDmitry Kravkov &switch_update_params->changes)) 577328311f8eSYuval Mintz rdata->inner_clss_l2gre = 1; 577428311f8eSYuval Mintz if (test_bit(BNX2X_F_UPDATE_TUNNEL_INNER_CLSS_VXLAN, 5775e42780b6SDmitry Kravkov &switch_update_params->changes)) 577628311f8eSYuval Mintz rdata->inner_clss_vxlan = 1; 577728311f8eSYuval Mintz if (test_bit(BNX2X_F_UPDATE_TUNNEL_INNER_CLSS_L2GENEVE, 577828311f8eSYuval Mintz &switch_update_params->changes)) 577928311f8eSYuval Mintz rdata->inner_clss_l2geneve = 1; 578028311f8eSYuval Mintz if (test_bit(BNX2X_F_UPDATE_TUNNEL_INNER_RSS, 578128311f8eSYuval Mintz &switch_update_params->changes)) 578228311f8eSYuval Mintz rdata->inner_rss = 1; 578328311f8eSYuval Mintz rdata->vxlan_dst_port = 578428311f8eSYuval Mintz cpu_to_le16(switch_update_params->vxlan_dst_port); 578528311f8eSYuval Mintz rdata->geneve_dst_port = 578628311f8eSYuval Mintz cpu_to_le16(switch_update_params->geneve_dst_port); 5787e42780b6SDmitry Kravkov } 5788e42780b6SDmitry Kravkov 578955c11941SMerav Sicron rdata->echo = SWITCH_UPDATE; 579055c11941SMerav Sicron 579114a94ebdSMichal Kalderon /* No need for an explicit memory barrier here as long as we 579214a94ebdSMichal Kalderon * ensure the ordering of writing to the SPQ element 579314a94ebdSMichal Kalderon * and updating of the SPQ producer which involves a memory 579414a94ebdSMichal Kalderon * read. If the memory read is removed we will have to put a 579514a94ebdSMichal Kalderon * full memory barrier there (inside bnx2x_sp_post()). 579614a94ebdSMichal Kalderon */ 579755c11941SMerav Sicron return bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_FUNCTION_UPDATE, 0, 579855c11941SMerav Sicron U64_HI(data_mapping), 579955c11941SMerav Sicron U64_LO(data_mapping), NONE_CONNECTION_TYPE); 580055c11941SMerav Sicron } 580155c11941SMerav Sicron 5802a3348722SBarak Witkowski static inline int bnx2x_func_send_afex_update(struct bnx2x *bp, 5803a3348722SBarak Witkowski struct bnx2x_func_state_params *params) 5804a3348722SBarak Witkowski { 5805a3348722SBarak Witkowski struct bnx2x_func_sp_obj *o = params->f_obj; 5806a3348722SBarak Witkowski struct function_update_data *rdata = 5807a3348722SBarak Witkowski (struct function_update_data *)o->afex_rdata; 5808a3348722SBarak Witkowski dma_addr_t data_mapping = o->afex_rdata_mapping; 5809a3348722SBarak Witkowski struct bnx2x_func_afex_update_params *afex_update_params = 5810a3348722SBarak Witkowski ¶ms->params.afex_update; 5811a3348722SBarak Witkowski 5812a3348722SBarak Witkowski memset(rdata, 0, sizeof(*rdata)); 5813a3348722SBarak Witkowski 5814a3348722SBarak Witkowski /* Fill the ramrod data with provided parameters */ 5815a3348722SBarak Witkowski rdata->vif_id_change_flg = 1; 5816a3348722SBarak Witkowski rdata->vif_id = cpu_to_le16(afex_update_params->vif_id); 5817a3348722SBarak Witkowski rdata->afex_default_vlan_change_flg = 1; 5818a3348722SBarak Witkowski rdata->afex_default_vlan = 5819a3348722SBarak Witkowski cpu_to_le16(afex_update_params->afex_default_vlan); 5820a3348722SBarak Witkowski rdata->allowed_priorities_change_flg = 1; 5821a3348722SBarak Witkowski rdata->allowed_priorities = afex_update_params->allowed_priorities; 582255c11941SMerav Sicron rdata->echo = AFEX_UPDATE; 5823a3348722SBarak Witkowski 582414a94ebdSMichal Kalderon /* No need for an explicit memory barrier here as long as we 582514a94ebdSMichal Kalderon * ensure the ordering of writing to the SPQ element 5826a3348722SBarak Witkowski * and updating of the SPQ producer which involves a memory 582714a94ebdSMichal Kalderon * read. If the memory read is removed we will have to put a 582814a94ebdSMichal Kalderon * full memory barrier there (inside bnx2x_sp_post()). 5829a3348722SBarak Witkowski */ 5830a3348722SBarak Witkowski DP(BNX2X_MSG_SP, 5831a3348722SBarak Witkowski "afex: sending func_update vif_id 0x%x dvlan 0x%x prio 0x%x\n", 5832a3348722SBarak Witkowski rdata->vif_id, 5833a3348722SBarak Witkowski rdata->afex_default_vlan, rdata->allowed_priorities); 5834a3348722SBarak Witkowski 5835a3348722SBarak Witkowski return bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_FUNCTION_UPDATE, 0, 5836a3348722SBarak Witkowski U64_HI(data_mapping), 5837a3348722SBarak Witkowski U64_LO(data_mapping), NONE_CONNECTION_TYPE); 5838a3348722SBarak Witkowski } 5839a3348722SBarak Witkowski 5840a3348722SBarak Witkowski static 5841a3348722SBarak Witkowski inline int bnx2x_func_send_afex_viflists(struct bnx2x *bp, 5842a3348722SBarak Witkowski struct bnx2x_func_state_params *params) 5843a3348722SBarak Witkowski { 5844a3348722SBarak Witkowski struct bnx2x_func_sp_obj *o = params->f_obj; 5845a3348722SBarak Witkowski struct afex_vif_list_ramrod_data *rdata = 5846a3348722SBarak Witkowski (struct afex_vif_list_ramrod_data *)o->afex_rdata; 584786564c3fSYuval Mintz struct bnx2x_func_afex_viflists_params *afex_vif_params = 5848a3348722SBarak Witkowski ¶ms->params.afex_viflists; 5849a3348722SBarak Witkowski u64 *p_rdata = (u64 *)rdata; 5850a3348722SBarak Witkowski 5851a3348722SBarak Witkowski memset(rdata, 0, sizeof(*rdata)); 5852a3348722SBarak Witkowski 5853a3348722SBarak Witkowski /* Fill the ramrod data with provided parameters */ 585486564c3fSYuval Mintz rdata->vif_list_index = cpu_to_le16(afex_vif_params->vif_list_index); 585586564c3fSYuval Mintz rdata->func_bit_map = afex_vif_params->func_bit_map; 585686564c3fSYuval Mintz rdata->afex_vif_list_command = afex_vif_params->afex_vif_list_command; 585786564c3fSYuval Mintz rdata->func_to_clear = afex_vif_params->func_to_clear; 5858a3348722SBarak Witkowski 5859a3348722SBarak Witkowski /* send in echo type of sub command */ 586086564c3fSYuval Mintz rdata->echo = afex_vif_params->afex_vif_list_command; 5861a3348722SBarak Witkowski 5862a3348722SBarak Witkowski /* No need for an explicit memory barrier here as long we would 5863a3348722SBarak Witkowski * need to ensure the ordering of writing to the SPQ element 5864a3348722SBarak Witkowski * and updating of the SPQ producer which involves a memory 5865a3348722SBarak Witkowski * read and we will have to put a full memory barrier there 5866a3348722SBarak Witkowski * (inside bnx2x_sp_post()). 5867a3348722SBarak Witkowski */ 5868a3348722SBarak Witkowski 5869a3348722SBarak Witkowski DP(BNX2X_MSG_SP, "afex: ramrod lists, cmd 0x%x index 0x%x func_bit_map 0x%x func_to_clr 0x%x\n", 5870a3348722SBarak Witkowski rdata->afex_vif_list_command, rdata->vif_list_index, 5871a3348722SBarak Witkowski rdata->func_bit_map, rdata->func_to_clear); 5872a3348722SBarak Witkowski 5873a3348722SBarak Witkowski /* this ramrod sends data directly and not through DMA mapping */ 5874a3348722SBarak Witkowski return bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_AFEX_VIF_LISTS, 0, 5875a3348722SBarak Witkowski U64_HI(*p_rdata), U64_LO(*p_rdata), 5876a3348722SBarak Witkowski NONE_CONNECTION_TYPE); 5877a3348722SBarak Witkowski } 5878a3348722SBarak Witkowski 5879adfc5217SJeff Kirsher static inline int bnx2x_func_send_stop(struct bnx2x *bp, 5880adfc5217SJeff Kirsher struct bnx2x_func_state_params *params) 5881adfc5217SJeff Kirsher { 5882adfc5217SJeff Kirsher return bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_FUNCTION_STOP, 0, 0, 0, 5883adfc5217SJeff Kirsher NONE_CONNECTION_TYPE); 5884adfc5217SJeff Kirsher } 5885adfc5217SJeff Kirsher 5886adfc5217SJeff Kirsher static inline int bnx2x_func_send_tx_stop(struct bnx2x *bp, 5887adfc5217SJeff Kirsher struct bnx2x_func_state_params *params) 5888adfc5217SJeff Kirsher { 5889adfc5217SJeff Kirsher return bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_STOP_TRAFFIC, 0, 0, 0, 5890adfc5217SJeff Kirsher NONE_CONNECTION_TYPE); 5891adfc5217SJeff Kirsher } 5892adfc5217SJeff Kirsher static inline int bnx2x_func_send_tx_start(struct bnx2x *bp, 5893adfc5217SJeff Kirsher struct bnx2x_func_state_params *params) 5894adfc5217SJeff Kirsher { 5895adfc5217SJeff Kirsher struct bnx2x_func_sp_obj *o = params->f_obj; 5896adfc5217SJeff Kirsher struct flow_control_configuration *rdata = 5897adfc5217SJeff Kirsher (struct flow_control_configuration *)o->rdata; 5898adfc5217SJeff Kirsher dma_addr_t data_mapping = o->rdata_mapping; 5899adfc5217SJeff Kirsher struct bnx2x_func_tx_start_params *tx_start_params = 5900adfc5217SJeff Kirsher ¶ms->params.tx_start; 5901adfc5217SJeff Kirsher int i; 5902adfc5217SJeff Kirsher 5903adfc5217SJeff Kirsher memset(rdata, 0, sizeof(*rdata)); 5904adfc5217SJeff Kirsher 5905adfc5217SJeff Kirsher rdata->dcb_enabled = tx_start_params->dcb_enabled; 5906adfc5217SJeff Kirsher rdata->dcb_version = tx_start_params->dcb_version; 5907adfc5217SJeff Kirsher rdata->dont_add_pri_0_en = tx_start_params->dont_add_pri_0_en; 5908adfc5217SJeff Kirsher 5909adfc5217SJeff Kirsher for (i = 0; i < ARRAY_SIZE(rdata->traffic_type_to_priority_cos); i++) 5910adfc5217SJeff Kirsher rdata->traffic_type_to_priority_cos[i] = 5911adfc5217SJeff Kirsher tx_start_params->traffic_type_to_priority_cos[i]; 5912adfc5217SJeff Kirsher 591328311f8eSYuval Mintz for (i = 0; i < MAX_TRAFFIC_TYPES; i++) 591428311f8eSYuval Mintz rdata->dcb_outer_pri[i] = tx_start_params->dcb_outer_pri[i]; 591514a94ebdSMichal Kalderon /* No need for an explicit memory barrier here as long as we 591614a94ebdSMichal Kalderon * ensure the ordering of writing to the SPQ element 591714a94ebdSMichal Kalderon * and updating of the SPQ producer which involves a memory 591814a94ebdSMichal Kalderon * read. If the memory read is removed we will have to put a 591914a94ebdSMichal Kalderon * full memory barrier there (inside bnx2x_sp_post()). 592014a94ebdSMichal Kalderon */ 5921adfc5217SJeff Kirsher return bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_START_TRAFFIC, 0, 5922adfc5217SJeff Kirsher U64_HI(data_mapping), 5923adfc5217SJeff Kirsher U64_LO(data_mapping), NONE_CONNECTION_TYPE); 5924adfc5217SJeff Kirsher } 5925adfc5217SJeff Kirsher 5926eeed018cSMichal Kalderon static inline 5927eeed018cSMichal Kalderon int bnx2x_func_send_set_timesync(struct bnx2x *bp, 5928eeed018cSMichal Kalderon struct bnx2x_func_state_params *params) 5929eeed018cSMichal Kalderon { 5930eeed018cSMichal Kalderon struct bnx2x_func_sp_obj *o = params->f_obj; 5931eeed018cSMichal Kalderon struct set_timesync_ramrod_data *rdata = 5932eeed018cSMichal Kalderon (struct set_timesync_ramrod_data *)o->rdata; 5933eeed018cSMichal Kalderon dma_addr_t data_mapping = o->rdata_mapping; 5934eeed018cSMichal Kalderon struct bnx2x_func_set_timesync_params *set_timesync_params = 5935eeed018cSMichal Kalderon ¶ms->params.set_timesync; 5936eeed018cSMichal Kalderon 5937eeed018cSMichal Kalderon memset(rdata, 0, sizeof(*rdata)); 5938eeed018cSMichal Kalderon 5939eeed018cSMichal Kalderon /* Fill the ramrod data with provided parameters */ 5940eeed018cSMichal Kalderon rdata->drift_adjust_cmd = set_timesync_params->drift_adjust_cmd; 5941eeed018cSMichal Kalderon rdata->offset_cmd = set_timesync_params->offset_cmd; 5942eeed018cSMichal Kalderon rdata->add_sub_drift_adjust_value = 5943eeed018cSMichal Kalderon set_timesync_params->add_sub_drift_adjust_value; 5944eeed018cSMichal Kalderon rdata->drift_adjust_value = set_timesync_params->drift_adjust_value; 5945eeed018cSMichal Kalderon rdata->drift_adjust_period = set_timesync_params->drift_adjust_period; 59468f15c613SMichal Kalderon rdata->offset_delta.lo = 59478f15c613SMichal Kalderon cpu_to_le32(U64_LO(set_timesync_params->offset_delta)); 59488f15c613SMichal Kalderon rdata->offset_delta.hi = 59498f15c613SMichal Kalderon cpu_to_le32(U64_HI(set_timesync_params->offset_delta)); 5950eeed018cSMichal Kalderon 5951eeed018cSMichal Kalderon DP(BNX2X_MSG_SP, "Set timesync command params: drift_cmd = %d, offset_cmd = %d, add_sub_drift = %d, drift_val = %d, drift_period = %d, offset_lo = %d, offset_hi = %d\n", 5952eeed018cSMichal Kalderon rdata->drift_adjust_cmd, rdata->offset_cmd, 5953eeed018cSMichal Kalderon rdata->add_sub_drift_adjust_value, rdata->drift_adjust_value, 5954eeed018cSMichal Kalderon rdata->drift_adjust_period, rdata->offset_delta.lo, 5955eeed018cSMichal Kalderon rdata->offset_delta.hi); 5956eeed018cSMichal Kalderon 5957eeed018cSMichal Kalderon return bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_SET_TIMESYNC, 0, 5958eeed018cSMichal Kalderon U64_HI(data_mapping), 5959eeed018cSMichal Kalderon U64_LO(data_mapping), NONE_CONNECTION_TYPE); 5960eeed018cSMichal Kalderon } 5961eeed018cSMichal Kalderon 5962adfc5217SJeff Kirsher static int bnx2x_func_send_cmd(struct bnx2x *bp, 5963adfc5217SJeff Kirsher struct bnx2x_func_state_params *params) 5964adfc5217SJeff Kirsher { 5965adfc5217SJeff Kirsher switch (params->cmd) { 5966adfc5217SJeff Kirsher case BNX2X_F_CMD_HW_INIT: 5967adfc5217SJeff Kirsher return bnx2x_func_hw_init(bp, params); 5968adfc5217SJeff Kirsher case BNX2X_F_CMD_START: 5969adfc5217SJeff Kirsher return bnx2x_func_send_start(bp, params); 5970adfc5217SJeff Kirsher case BNX2X_F_CMD_STOP: 5971adfc5217SJeff Kirsher return bnx2x_func_send_stop(bp, params); 5972adfc5217SJeff Kirsher case BNX2X_F_CMD_HW_RESET: 5973adfc5217SJeff Kirsher return bnx2x_func_hw_reset(bp, params); 5974a3348722SBarak Witkowski case BNX2X_F_CMD_AFEX_UPDATE: 5975a3348722SBarak Witkowski return bnx2x_func_send_afex_update(bp, params); 5976a3348722SBarak Witkowski case BNX2X_F_CMD_AFEX_VIFLISTS: 5977a3348722SBarak Witkowski return bnx2x_func_send_afex_viflists(bp, params); 5978adfc5217SJeff Kirsher case BNX2X_F_CMD_TX_STOP: 5979adfc5217SJeff Kirsher return bnx2x_func_send_tx_stop(bp, params); 5980adfc5217SJeff Kirsher case BNX2X_F_CMD_TX_START: 5981adfc5217SJeff Kirsher return bnx2x_func_send_tx_start(bp, params); 598255c11941SMerav Sicron case BNX2X_F_CMD_SWITCH_UPDATE: 598355c11941SMerav Sicron return bnx2x_func_send_switch_update(bp, params); 5984eeed018cSMichal Kalderon case BNX2X_F_CMD_SET_TIMESYNC: 5985eeed018cSMichal Kalderon return bnx2x_func_send_set_timesync(bp, params); 5986adfc5217SJeff Kirsher default: 5987adfc5217SJeff Kirsher BNX2X_ERR("Unknown command: %d\n", params->cmd); 5988adfc5217SJeff Kirsher return -EINVAL; 5989adfc5217SJeff Kirsher } 5990adfc5217SJeff Kirsher } 5991adfc5217SJeff Kirsher 5992adfc5217SJeff Kirsher void bnx2x_init_func_obj(struct bnx2x *bp, 5993adfc5217SJeff Kirsher struct bnx2x_func_sp_obj *obj, 5994adfc5217SJeff Kirsher void *rdata, dma_addr_t rdata_mapping, 5995a3348722SBarak Witkowski void *afex_rdata, dma_addr_t afex_rdata_mapping, 5996adfc5217SJeff Kirsher struct bnx2x_func_sp_drv_ops *drv_iface) 5997adfc5217SJeff Kirsher { 5998adfc5217SJeff Kirsher memset(obj, 0, sizeof(*obj)); 5999adfc5217SJeff Kirsher 6000adfc5217SJeff Kirsher mutex_init(&obj->one_pending_mutex); 6001adfc5217SJeff Kirsher 6002adfc5217SJeff Kirsher obj->rdata = rdata; 6003adfc5217SJeff Kirsher obj->rdata_mapping = rdata_mapping; 6004a3348722SBarak Witkowski obj->afex_rdata = afex_rdata; 6005a3348722SBarak Witkowski obj->afex_rdata_mapping = afex_rdata_mapping; 6006adfc5217SJeff Kirsher obj->send_cmd = bnx2x_func_send_cmd; 6007adfc5217SJeff Kirsher obj->check_transition = bnx2x_func_chk_transition; 6008adfc5217SJeff Kirsher obj->complete_cmd = bnx2x_func_comp_cmd; 6009adfc5217SJeff Kirsher obj->wait_comp = bnx2x_func_wait_comp; 6010adfc5217SJeff Kirsher 6011adfc5217SJeff Kirsher obj->drv = drv_iface; 6012adfc5217SJeff Kirsher } 6013adfc5217SJeff Kirsher 6014adfc5217SJeff Kirsher /** 6015adfc5217SJeff Kirsher * bnx2x_func_state_change - perform Function state change transition 6016adfc5217SJeff Kirsher * 6017adfc5217SJeff Kirsher * @bp: device handle 6018adfc5217SJeff Kirsher * @params: parameters to perform the transaction 6019adfc5217SJeff Kirsher * 6020adfc5217SJeff Kirsher * returns 0 in case of successfully completed transition, 6021adfc5217SJeff Kirsher * negative error code in case of failure, positive 6022adfc5217SJeff Kirsher * (EBUSY) value if there is a completion to that is 6023adfc5217SJeff Kirsher * still pending (possible only if RAMROD_COMP_WAIT is 6024adfc5217SJeff Kirsher * not set in params->ramrod_flags for asynchronous 6025adfc5217SJeff Kirsher * commands). 6026adfc5217SJeff Kirsher */ 6027adfc5217SJeff Kirsher int bnx2x_func_state_change(struct bnx2x *bp, 6028adfc5217SJeff Kirsher struct bnx2x_func_state_params *params) 6029adfc5217SJeff Kirsher { 6030adfc5217SJeff Kirsher struct bnx2x_func_sp_obj *o = params->f_obj; 603155c11941SMerav Sicron int rc, cnt = 300; 6032adfc5217SJeff Kirsher enum bnx2x_func_cmd cmd = params->cmd; 6033adfc5217SJeff Kirsher unsigned long *pending = &o->pending; 6034adfc5217SJeff Kirsher 6035adfc5217SJeff Kirsher mutex_lock(&o->one_pending_mutex); 6036adfc5217SJeff Kirsher 6037adfc5217SJeff Kirsher /* Check that the requested transition is legal */ 603855c11941SMerav Sicron rc = o->check_transition(bp, o, params); 603955c11941SMerav Sicron if ((rc == -EBUSY) && 604055c11941SMerav Sicron (test_bit(RAMROD_RETRY, ¶ms->ramrod_flags))) { 604155c11941SMerav Sicron while ((rc == -EBUSY) && (--cnt > 0)) { 6042adfc5217SJeff Kirsher mutex_unlock(&o->one_pending_mutex); 604355c11941SMerav Sicron msleep(10); 604455c11941SMerav Sicron mutex_lock(&o->one_pending_mutex); 604555c11941SMerav Sicron rc = o->check_transition(bp, o, params); 604655c11941SMerav Sicron } 604755c11941SMerav Sicron if (rc == -EBUSY) { 604855c11941SMerav Sicron mutex_unlock(&o->one_pending_mutex); 604955c11941SMerav Sicron BNX2X_ERR("timeout waiting for previous ramrod completion\n"); 605055c11941SMerav Sicron return rc; 605155c11941SMerav Sicron } 605255c11941SMerav Sicron } else if (rc) { 605355c11941SMerav Sicron mutex_unlock(&o->one_pending_mutex); 605455c11941SMerav Sicron return rc; 6055adfc5217SJeff Kirsher } 6056adfc5217SJeff Kirsher 6057adfc5217SJeff Kirsher /* Set "pending" bit */ 6058adfc5217SJeff Kirsher set_bit(cmd, pending); 6059adfc5217SJeff Kirsher 6060adfc5217SJeff Kirsher /* Don't send a command if only driver cleanup was requested */ 6061adfc5217SJeff Kirsher if (test_bit(RAMROD_DRV_CLR_ONLY, ¶ms->ramrod_flags)) { 6062adfc5217SJeff Kirsher bnx2x_func_state_change_comp(bp, o, cmd); 6063adfc5217SJeff Kirsher mutex_unlock(&o->one_pending_mutex); 6064adfc5217SJeff Kirsher } else { 6065adfc5217SJeff Kirsher /* Send a ramrod */ 6066adfc5217SJeff Kirsher rc = o->send_cmd(bp, params); 6067adfc5217SJeff Kirsher 6068adfc5217SJeff Kirsher mutex_unlock(&o->one_pending_mutex); 6069adfc5217SJeff Kirsher 6070adfc5217SJeff Kirsher if (rc) { 6071adfc5217SJeff Kirsher o->next_state = BNX2X_F_STATE_MAX; 6072adfc5217SJeff Kirsher clear_bit(cmd, pending); 60734e857c58SPeter Zijlstra smp_mb__after_atomic(); 6074adfc5217SJeff Kirsher return rc; 6075adfc5217SJeff Kirsher } 6076adfc5217SJeff Kirsher 6077adfc5217SJeff Kirsher if (test_bit(RAMROD_COMP_WAIT, ¶ms->ramrod_flags)) { 6078adfc5217SJeff Kirsher rc = o->wait_comp(bp, o, cmd); 6079adfc5217SJeff Kirsher if (rc) 6080adfc5217SJeff Kirsher return rc; 6081adfc5217SJeff Kirsher 6082adfc5217SJeff Kirsher return 0; 6083adfc5217SJeff Kirsher } 6084adfc5217SJeff Kirsher } 6085adfc5217SJeff Kirsher 6086adfc5217SJeff Kirsher return !!test_bit(cmd, pending); 6087adfc5217SJeff Kirsher } 6088