1adfc5217SJeff Kirsher /* bnx2x_sp.c: Broadcom Everest network driver. 2adfc5217SJeff Kirsher * 3247fa82bSYuval Mintz * Copyright (c) 2011-2013 Broadcom Corporation 4adfc5217SJeff Kirsher * 5adfc5217SJeff Kirsher * Unless you and Broadcom execute a separate written software license 6adfc5217SJeff Kirsher * agreement governing use of this software, this software is licensed to you 7adfc5217SJeff Kirsher * under the terms of the GNU General Public License version 2, available 8adfc5217SJeff Kirsher * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL"). 9adfc5217SJeff Kirsher * 10adfc5217SJeff Kirsher * Notwithstanding the above, under no circumstances may you combine this 11adfc5217SJeff Kirsher * software in any way with any other Broadcom software provided under a 12adfc5217SJeff Kirsher * license other than the GPL, without Broadcom's express prior written 13adfc5217SJeff Kirsher * consent. 14adfc5217SJeff Kirsher * 15adfc5217SJeff Kirsher * Maintained by: Eilon Greenstein <eilong@broadcom.com> 16adfc5217SJeff Kirsher * Written by: Vladislav Zolotarov 17adfc5217SJeff Kirsher * 18adfc5217SJeff Kirsher */ 19f1deab50SJoe Perches 20f1deab50SJoe Perches #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 21f1deab50SJoe Perches 22adfc5217SJeff Kirsher #include <linux/module.h> 23adfc5217SJeff Kirsher #include <linux/crc32.h> 24adfc5217SJeff Kirsher #include <linux/netdevice.h> 25adfc5217SJeff Kirsher #include <linux/etherdevice.h> 26adfc5217SJeff Kirsher #include <linux/crc32c.h> 27adfc5217SJeff Kirsher #include "bnx2x.h" 28adfc5217SJeff Kirsher #include "bnx2x_cmn.h" 29adfc5217SJeff Kirsher #include "bnx2x_sp.h" 30adfc5217SJeff Kirsher 31adfc5217SJeff Kirsher #define BNX2X_MAX_EMUL_MULTI 16 32adfc5217SJeff Kirsher 33adfc5217SJeff Kirsher /**** Exe Queue interfaces ****/ 34adfc5217SJeff Kirsher 35adfc5217SJeff Kirsher /** 36adfc5217SJeff Kirsher * bnx2x_exe_queue_init - init the Exe Queue object 37adfc5217SJeff Kirsher * 3816a5fd92SYuval Mintz * @o: pointer to the object 39adfc5217SJeff Kirsher * @exe_len: length 4016a5fd92SYuval Mintz * @owner: pointer to the owner 41adfc5217SJeff Kirsher * @validate: validate function pointer 42adfc5217SJeff Kirsher * @optimize: optimize function pointer 43adfc5217SJeff Kirsher * @exec: execute function pointer 44adfc5217SJeff Kirsher * @get: get function pointer 45adfc5217SJeff Kirsher */ 46adfc5217SJeff Kirsher static inline void bnx2x_exe_queue_init(struct bnx2x *bp, 47adfc5217SJeff Kirsher struct bnx2x_exe_queue_obj *o, 48adfc5217SJeff Kirsher int exe_len, 49adfc5217SJeff Kirsher union bnx2x_qable_obj *owner, 50adfc5217SJeff Kirsher exe_q_validate validate, 51460a25cdSYuval Mintz exe_q_remove remove, 52adfc5217SJeff Kirsher exe_q_optimize optimize, 53adfc5217SJeff Kirsher exe_q_execute exec, 54adfc5217SJeff Kirsher exe_q_get get) 55adfc5217SJeff Kirsher { 56adfc5217SJeff Kirsher memset(o, 0, sizeof(*o)); 57adfc5217SJeff Kirsher 58adfc5217SJeff Kirsher INIT_LIST_HEAD(&o->exe_queue); 59adfc5217SJeff Kirsher INIT_LIST_HEAD(&o->pending_comp); 60adfc5217SJeff Kirsher 61adfc5217SJeff Kirsher spin_lock_init(&o->lock); 62adfc5217SJeff Kirsher 63adfc5217SJeff Kirsher o->exe_chunk_len = exe_len; 64adfc5217SJeff Kirsher o->owner = owner; 65adfc5217SJeff Kirsher 66adfc5217SJeff Kirsher /* Owner specific callbacks */ 67adfc5217SJeff Kirsher o->validate = validate; 68460a25cdSYuval Mintz o->remove = remove; 69adfc5217SJeff Kirsher o->optimize = optimize; 70adfc5217SJeff Kirsher o->execute = exec; 71adfc5217SJeff Kirsher o->get = get; 72adfc5217SJeff Kirsher 7351c1a580SMerav Sicron DP(BNX2X_MSG_SP, "Setup the execution queue with the chunk length of %d\n", 7451c1a580SMerav Sicron exe_len); 75adfc5217SJeff Kirsher } 76adfc5217SJeff Kirsher 77adfc5217SJeff Kirsher static inline void bnx2x_exe_queue_free_elem(struct bnx2x *bp, 78adfc5217SJeff Kirsher struct bnx2x_exeq_elem *elem) 79adfc5217SJeff Kirsher { 80adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "Deleting an exe_queue element\n"); 81adfc5217SJeff Kirsher kfree(elem); 82adfc5217SJeff Kirsher } 83adfc5217SJeff Kirsher 84adfc5217SJeff Kirsher static inline int bnx2x_exe_queue_length(struct bnx2x_exe_queue_obj *o) 85adfc5217SJeff Kirsher { 86adfc5217SJeff Kirsher struct bnx2x_exeq_elem *elem; 87adfc5217SJeff Kirsher int cnt = 0; 88adfc5217SJeff Kirsher 89adfc5217SJeff Kirsher spin_lock_bh(&o->lock); 90adfc5217SJeff Kirsher 91adfc5217SJeff Kirsher list_for_each_entry(elem, &o->exe_queue, link) 92adfc5217SJeff Kirsher cnt++; 93adfc5217SJeff Kirsher 94adfc5217SJeff Kirsher spin_unlock_bh(&o->lock); 95adfc5217SJeff Kirsher 96adfc5217SJeff Kirsher return cnt; 97adfc5217SJeff Kirsher } 98adfc5217SJeff Kirsher 99adfc5217SJeff Kirsher /** 100adfc5217SJeff Kirsher * bnx2x_exe_queue_add - add a new element to the execution queue 101adfc5217SJeff Kirsher * 102adfc5217SJeff Kirsher * @bp: driver handle 103adfc5217SJeff Kirsher * @o: queue 104adfc5217SJeff Kirsher * @cmd: new command to add 105adfc5217SJeff Kirsher * @restore: true - do not optimize the command 106adfc5217SJeff Kirsher * 107adfc5217SJeff Kirsher * If the element is optimized or is illegal, frees it. 108adfc5217SJeff Kirsher */ 109adfc5217SJeff Kirsher static inline int bnx2x_exe_queue_add(struct bnx2x *bp, 110adfc5217SJeff Kirsher struct bnx2x_exe_queue_obj *o, 111adfc5217SJeff Kirsher struct bnx2x_exeq_elem *elem, 112adfc5217SJeff Kirsher bool restore) 113adfc5217SJeff Kirsher { 114adfc5217SJeff Kirsher int rc; 115adfc5217SJeff Kirsher 116adfc5217SJeff Kirsher spin_lock_bh(&o->lock); 117adfc5217SJeff Kirsher 118adfc5217SJeff Kirsher if (!restore) { 119adfc5217SJeff Kirsher /* Try to cancel this element queue */ 120adfc5217SJeff Kirsher rc = o->optimize(bp, o->owner, elem); 121adfc5217SJeff Kirsher if (rc) 122adfc5217SJeff Kirsher goto free_and_exit; 123adfc5217SJeff Kirsher 124adfc5217SJeff Kirsher /* Check if this request is ok */ 125adfc5217SJeff Kirsher rc = o->validate(bp, o->owner, elem); 126adfc5217SJeff Kirsher if (rc) { 1272384d6aaSDmitry Kravkov DP(BNX2X_MSG_SP, "Preamble failed: %d\n", rc); 128adfc5217SJeff Kirsher goto free_and_exit; 129adfc5217SJeff Kirsher } 130adfc5217SJeff Kirsher } 131adfc5217SJeff Kirsher 132adfc5217SJeff Kirsher /* If so, add it to the execution queue */ 133adfc5217SJeff Kirsher list_add_tail(&elem->link, &o->exe_queue); 134adfc5217SJeff Kirsher 135adfc5217SJeff Kirsher spin_unlock_bh(&o->lock); 136adfc5217SJeff Kirsher 137adfc5217SJeff Kirsher return 0; 138adfc5217SJeff Kirsher 139adfc5217SJeff Kirsher free_and_exit: 140adfc5217SJeff Kirsher bnx2x_exe_queue_free_elem(bp, elem); 141adfc5217SJeff Kirsher 142adfc5217SJeff Kirsher spin_unlock_bh(&o->lock); 143adfc5217SJeff Kirsher 144adfc5217SJeff Kirsher return rc; 145adfc5217SJeff Kirsher } 146adfc5217SJeff Kirsher 147adfc5217SJeff Kirsher static inline void __bnx2x_exe_queue_reset_pending( 148adfc5217SJeff Kirsher struct bnx2x *bp, 149adfc5217SJeff Kirsher struct bnx2x_exe_queue_obj *o) 150adfc5217SJeff Kirsher { 151adfc5217SJeff Kirsher struct bnx2x_exeq_elem *elem; 152adfc5217SJeff Kirsher 153adfc5217SJeff Kirsher while (!list_empty(&o->pending_comp)) { 154adfc5217SJeff Kirsher elem = list_first_entry(&o->pending_comp, 155adfc5217SJeff Kirsher struct bnx2x_exeq_elem, link); 156adfc5217SJeff Kirsher 157adfc5217SJeff Kirsher list_del(&elem->link); 158adfc5217SJeff Kirsher bnx2x_exe_queue_free_elem(bp, elem); 159adfc5217SJeff Kirsher } 160adfc5217SJeff Kirsher } 161adfc5217SJeff Kirsher 162adfc5217SJeff Kirsher static inline void bnx2x_exe_queue_reset_pending(struct bnx2x *bp, 163adfc5217SJeff Kirsher struct bnx2x_exe_queue_obj *o) 164adfc5217SJeff Kirsher { 165adfc5217SJeff Kirsher spin_lock_bh(&o->lock); 166adfc5217SJeff Kirsher 167adfc5217SJeff Kirsher __bnx2x_exe_queue_reset_pending(bp, o); 168adfc5217SJeff Kirsher 169adfc5217SJeff Kirsher spin_unlock_bh(&o->lock); 170adfc5217SJeff Kirsher } 171adfc5217SJeff Kirsher 172adfc5217SJeff Kirsher /** 173adfc5217SJeff Kirsher * bnx2x_exe_queue_step - execute one execution chunk atomically 174adfc5217SJeff Kirsher * 175adfc5217SJeff Kirsher * @bp: driver handle 176adfc5217SJeff Kirsher * @o: queue 177adfc5217SJeff Kirsher * @ramrod_flags: flags 178adfc5217SJeff Kirsher * 17916a5fd92SYuval Mintz * (Atomicity is ensured using the exe_queue->lock). 180adfc5217SJeff Kirsher */ 181adfc5217SJeff Kirsher static inline int bnx2x_exe_queue_step(struct bnx2x *bp, 182adfc5217SJeff Kirsher struct bnx2x_exe_queue_obj *o, 183adfc5217SJeff Kirsher unsigned long *ramrod_flags) 184adfc5217SJeff Kirsher { 185adfc5217SJeff Kirsher struct bnx2x_exeq_elem *elem, spacer; 186adfc5217SJeff Kirsher int cur_len = 0, rc; 187adfc5217SJeff Kirsher 188adfc5217SJeff Kirsher memset(&spacer, 0, sizeof(spacer)); 189adfc5217SJeff Kirsher 190adfc5217SJeff Kirsher spin_lock_bh(&o->lock); 191adfc5217SJeff Kirsher 19216a5fd92SYuval Mintz /* Next step should not be performed until the current is finished, 193adfc5217SJeff Kirsher * unless a DRV_CLEAR_ONLY bit is set. In this case we just want to 194adfc5217SJeff Kirsher * properly clear object internals without sending any command to the FW 195adfc5217SJeff Kirsher * which also implies there won't be any completion to clear the 196adfc5217SJeff Kirsher * 'pending' list. 197adfc5217SJeff Kirsher */ 198adfc5217SJeff Kirsher if (!list_empty(&o->pending_comp)) { 199adfc5217SJeff Kirsher if (test_bit(RAMROD_DRV_CLR_ONLY, ramrod_flags)) { 20051c1a580SMerav Sicron DP(BNX2X_MSG_SP, "RAMROD_DRV_CLR_ONLY requested: resetting a pending_comp list\n"); 201adfc5217SJeff Kirsher __bnx2x_exe_queue_reset_pending(bp, o); 202adfc5217SJeff Kirsher } else { 203adfc5217SJeff Kirsher spin_unlock_bh(&o->lock); 204adfc5217SJeff Kirsher return 1; 205adfc5217SJeff Kirsher } 206adfc5217SJeff Kirsher } 207adfc5217SJeff Kirsher 20816a5fd92SYuval Mintz /* Run through the pending commands list and create a next 209adfc5217SJeff Kirsher * execution chunk. 210adfc5217SJeff Kirsher */ 211adfc5217SJeff Kirsher while (!list_empty(&o->exe_queue)) { 212adfc5217SJeff Kirsher elem = list_first_entry(&o->exe_queue, struct bnx2x_exeq_elem, 213adfc5217SJeff Kirsher link); 214adfc5217SJeff Kirsher WARN_ON(!elem->cmd_len); 215adfc5217SJeff Kirsher 216adfc5217SJeff Kirsher if (cur_len + elem->cmd_len <= o->exe_chunk_len) { 217adfc5217SJeff Kirsher cur_len += elem->cmd_len; 21816a5fd92SYuval Mintz /* Prevent from both lists being empty when moving an 219adfc5217SJeff Kirsher * element. This will allow the call of 220adfc5217SJeff Kirsher * bnx2x_exe_queue_empty() without locking. 221adfc5217SJeff Kirsher */ 222adfc5217SJeff Kirsher list_add_tail(&spacer.link, &o->pending_comp); 223adfc5217SJeff Kirsher mb(); 2247933aa5cSWei Yongjun list_move_tail(&elem->link, &o->pending_comp); 225adfc5217SJeff Kirsher list_del(&spacer.link); 226adfc5217SJeff Kirsher } else 227adfc5217SJeff Kirsher break; 228adfc5217SJeff Kirsher } 229adfc5217SJeff Kirsher 230adfc5217SJeff Kirsher /* Sanity check */ 231adfc5217SJeff Kirsher if (!cur_len) { 232adfc5217SJeff Kirsher spin_unlock_bh(&o->lock); 233adfc5217SJeff Kirsher return 0; 234adfc5217SJeff Kirsher } 235adfc5217SJeff Kirsher 236adfc5217SJeff Kirsher rc = o->execute(bp, o->owner, &o->pending_comp, ramrod_flags); 237adfc5217SJeff Kirsher if (rc < 0) 23816a5fd92SYuval Mintz /* In case of an error return the commands back to the queue 239adfc5217SJeff Kirsher * and reset the pending_comp. 240adfc5217SJeff Kirsher */ 241adfc5217SJeff Kirsher list_splice_init(&o->pending_comp, &o->exe_queue); 242adfc5217SJeff Kirsher else if (!rc) 24316a5fd92SYuval Mintz /* If zero is returned, means there are no outstanding pending 244adfc5217SJeff Kirsher * completions and we may dismiss the pending list. 245adfc5217SJeff Kirsher */ 246adfc5217SJeff Kirsher __bnx2x_exe_queue_reset_pending(bp, o); 247adfc5217SJeff Kirsher 248adfc5217SJeff Kirsher spin_unlock_bh(&o->lock); 249adfc5217SJeff Kirsher return rc; 250adfc5217SJeff Kirsher } 251adfc5217SJeff Kirsher 252adfc5217SJeff Kirsher static inline bool bnx2x_exe_queue_empty(struct bnx2x_exe_queue_obj *o) 253adfc5217SJeff Kirsher { 254adfc5217SJeff Kirsher bool empty = list_empty(&o->exe_queue); 255adfc5217SJeff Kirsher 256adfc5217SJeff Kirsher /* Don't reorder!!! */ 257adfc5217SJeff Kirsher mb(); 258adfc5217SJeff Kirsher 259adfc5217SJeff Kirsher return empty && list_empty(&o->pending_comp); 260adfc5217SJeff Kirsher } 261adfc5217SJeff Kirsher 262adfc5217SJeff Kirsher static inline struct bnx2x_exeq_elem *bnx2x_exe_queue_alloc_elem( 263adfc5217SJeff Kirsher struct bnx2x *bp) 264adfc5217SJeff Kirsher { 265adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "Allocating a new exe_queue element\n"); 266adfc5217SJeff Kirsher return kzalloc(sizeof(struct bnx2x_exeq_elem), GFP_ATOMIC); 267adfc5217SJeff Kirsher } 268adfc5217SJeff Kirsher 269adfc5217SJeff Kirsher /************************ raw_obj functions ***********************************/ 270adfc5217SJeff Kirsher static bool bnx2x_raw_check_pending(struct bnx2x_raw_obj *o) 271adfc5217SJeff Kirsher { 272adfc5217SJeff Kirsher return !!test_bit(o->state, o->pstate); 273adfc5217SJeff Kirsher } 274adfc5217SJeff Kirsher 275adfc5217SJeff Kirsher static void bnx2x_raw_clear_pending(struct bnx2x_raw_obj *o) 276adfc5217SJeff Kirsher { 277adfc5217SJeff Kirsher smp_mb__before_clear_bit(); 278adfc5217SJeff Kirsher clear_bit(o->state, o->pstate); 279adfc5217SJeff Kirsher smp_mb__after_clear_bit(); 280adfc5217SJeff Kirsher } 281adfc5217SJeff Kirsher 282adfc5217SJeff Kirsher static void bnx2x_raw_set_pending(struct bnx2x_raw_obj *o) 283adfc5217SJeff Kirsher { 284adfc5217SJeff Kirsher smp_mb__before_clear_bit(); 285adfc5217SJeff Kirsher set_bit(o->state, o->pstate); 286adfc5217SJeff Kirsher smp_mb__after_clear_bit(); 287adfc5217SJeff Kirsher } 288adfc5217SJeff Kirsher 289adfc5217SJeff Kirsher /** 290adfc5217SJeff Kirsher * bnx2x_state_wait - wait until the given bit(state) is cleared 291adfc5217SJeff Kirsher * 292adfc5217SJeff Kirsher * @bp: device handle 293adfc5217SJeff Kirsher * @state: state which is to be cleared 294adfc5217SJeff Kirsher * @state_p: state buffer 295adfc5217SJeff Kirsher * 296adfc5217SJeff Kirsher */ 297adfc5217SJeff Kirsher static inline int bnx2x_state_wait(struct bnx2x *bp, int state, 298adfc5217SJeff Kirsher unsigned long *pstate) 299adfc5217SJeff Kirsher { 300adfc5217SJeff Kirsher /* can take a while if any port is running */ 301adfc5217SJeff Kirsher int cnt = 5000; 302adfc5217SJeff Kirsher 303adfc5217SJeff Kirsher if (CHIP_REV_IS_EMUL(bp)) 304adfc5217SJeff Kirsher cnt *= 20; 305adfc5217SJeff Kirsher 306adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "waiting for state to become %d\n", state); 307adfc5217SJeff Kirsher 308adfc5217SJeff Kirsher might_sleep(); 309adfc5217SJeff Kirsher while (cnt--) { 310adfc5217SJeff Kirsher if (!test_bit(state, pstate)) { 311adfc5217SJeff Kirsher #ifdef BNX2X_STOP_ON_ERROR 312adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "exit (cnt %d)\n", 5000 - cnt); 313adfc5217SJeff Kirsher #endif 314adfc5217SJeff Kirsher return 0; 315adfc5217SJeff Kirsher } 316adfc5217SJeff Kirsher 3170926d499SYuval Mintz usleep_range(1000, 2000); 318adfc5217SJeff Kirsher 319adfc5217SJeff Kirsher if (bp->panic) 320adfc5217SJeff Kirsher return -EIO; 321adfc5217SJeff Kirsher } 322adfc5217SJeff Kirsher 323adfc5217SJeff Kirsher /* timeout! */ 324adfc5217SJeff Kirsher BNX2X_ERR("timeout waiting for state %d\n", state); 325adfc5217SJeff Kirsher #ifdef BNX2X_STOP_ON_ERROR 326adfc5217SJeff Kirsher bnx2x_panic(); 327adfc5217SJeff Kirsher #endif 328adfc5217SJeff Kirsher 329adfc5217SJeff Kirsher return -EBUSY; 330adfc5217SJeff Kirsher } 331adfc5217SJeff Kirsher 332adfc5217SJeff Kirsher static int bnx2x_raw_wait(struct bnx2x *bp, struct bnx2x_raw_obj *raw) 333adfc5217SJeff Kirsher { 334adfc5217SJeff Kirsher return bnx2x_state_wait(bp, raw->state, raw->pstate); 335adfc5217SJeff Kirsher } 336adfc5217SJeff Kirsher 337adfc5217SJeff Kirsher /***************** Classification verbs: Set/Del MAC/VLAN/VLAN-MAC ************/ 338adfc5217SJeff Kirsher /* credit handling callbacks */ 339adfc5217SJeff Kirsher static bool bnx2x_get_cam_offset_mac(struct bnx2x_vlan_mac_obj *o, int *offset) 340adfc5217SJeff Kirsher { 341adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *mp = o->macs_pool; 342adfc5217SJeff Kirsher 343adfc5217SJeff Kirsher WARN_ON(!mp); 344adfc5217SJeff Kirsher 345adfc5217SJeff Kirsher return mp->get_entry(mp, offset); 346adfc5217SJeff Kirsher } 347adfc5217SJeff Kirsher 348adfc5217SJeff Kirsher static bool bnx2x_get_credit_mac(struct bnx2x_vlan_mac_obj *o) 349adfc5217SJeff Kirsher { 350adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *mp = o->macs_pool; 351adfc5217SJeff Kirsher 352adfc5217SJeff Kirsher WARN_ON(!mp); 353adfc5217SJeff Kirsher 354adfc5217SJeff Kirsher return mp->get(mp, 1); 355adfc5217SJeff Kirsher } 356adfc5217SJeff Kirsher 357adfc5217SJeff Kirsher static bool bnx2x_get_cam_offset_vlan(struct bnx2x_vlan_mac_obj *o, int *offset) 358adfc5217SJeff Kirsher { 359adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *vp = o->vlans_pool; 360adfc5217SJeff Kirsher 361adfc5217SJeff Kirsher WARN_ON(!vp); 362adfc5217SJeff Kirsher 363adfc5217SJeff Kirsher return vp->get_entry(vp, offset); 364adfc5217SJeff Kirsher } 365adfc5217SJeff Kirsher 366adfc5217SJeff Kirsher static bool bnx2x_get_credit_vlan(struct bnx2x_vlan_mac_obj *o) 367adfc5217SJeff Kirsher { 368adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *vp = o->vlans_pool; 369adfc5217SJeff Kirsher 370adfc5217SJeff Kirsher WARN_ON(!vp); 371adfc5217SJeff Kirsher 372adfc5217SJeff Kirsher return vp->get(vp, 1); 373adfc5217SJeff Kirsher } 374adfc5217SJeff Kirsher 375adfc5217SJeff Kirsher static bool bnx2x_get_credit_vlan_mac(struct bnx2x_vlan_mac_obj *o) 376adfc5217SJeff Kirsher { 377adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *mp = o->macs_pool; 378adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *vp = o->vlans_pool; 379adfc5217SJeff Kirsher 380adfc5217SJeff Kirsher if (!mp->get(mp, 1)) 381adfc5217SJeff Kirsher return false; 382adfc5217SJeff Kirsher 383adfc5217SJeff Kirsher if (!vp->get(vp, 1)) { 384adfc5217SJeff Kirsher mp->put(mp, 1); 385adfc5217SJeff Kirsher return false; 386adfc5217SJeff Kirsher } 387adfc5217SJeff Kirsher 388adfc5217SJeff Kirsher return true; 389adfc5217SJeff Kirsher } 390adfc5217SJeff Kirsher 391adfc5217SJeff Kirsher static bool bnx2x_put_cam_offset_mac(struct bnx2x_vlan_mac_obj *o, int offset) 392adfc5217SJeff Kirsher { 393adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *mp = o->macs_pool; 394adfc5217SJeff Kirsher 395adfc5217SJeff Kirsher return mp->put_entry(mp, offset); 396adfc5217SJeff Kirsher } 397adfc5217SJeff Kirsher 398adfc5217SJeff Kirsher static bool bnx2x_put_credit_mac(struct bnx2x_vlan_mac_obj *o) 399adfc5217SJeff Kirsher { 400adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *mp = o->macs_pool; 401adfc5217SJeff Kirsher 402adfc5217SJeff Kirsher return mp->put(mp, 1); 403adfc5217SJeff Kirsher } 404adfc5217SJeff Kirsher 405adfc5217SJeff Kirsher static bool bnx2x_put_cam_offset_vlan(struct bnx2x_vlan_mac_obj *o, int offset) 406adfc5217SJeff Kirsher { 407adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *vp = o->vlans_pool; 408adfc5217SJeff Kirsher 409adfc5217SJeff Kirsher return vp->put_entry(vp, offset); 410adfc5217SJeff Kirsher } 411adfc5217SJeff Kirsher 412adfc5217SJeff Kirsher static bool bnx2x_put_credit_vlan(struct bnx2x_vlan_mac_obj *o) 413adfc5217SJeff Kirsher { 414adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *vp = o->vlans_pool; 415adfc5217SJeff Kirsher 416adfc5217SJeff Kirsher return vp->put(vp, 1); 417adfc5217SJeff Kirsher } 418adfc5217SJeff Kirsher 419adfc5217SJeff Kirsher static bool bnx2x_put_credit_vlan_mac(struct bnx2x_vlan_mac_obj *o) 420adfc5217SJeff Kirsher { 421adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *mp = o->macs_pool; 422adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *vp = o->vlans_pool; 423adfc5217SJeff Kirsher 424adfc5217SJeff Kirsher if (!mp->put(mp, 1)) 425adfc5217SJeff Kirsher return false; 426adfc5217SJeff Kirsher 427adfc5217SJeff Kirsher if (!vp->put(vp, 1)) { 428adfc5217SJeff Kirsher mp->get(mp, 1); 429adfc5217SJeff Kirsher return false; 430adfc5217SJeff Kirsher } 431adfc5217SJeff Kirsher 432adfc5217SJeff Kirsher return true; 433adfc5217SJeff Kirsher } 434adfc5217SJeff Kirsher 435ed5162a0SAriel Elior static int bnx2x_get_n_elements(struct bnx2x *bp, struct bnx2x_vlan_mac_obj *o, 4363ec9f9caSAriel Elior int n, u8 *base, u8 stride, u8 size) 437ed5162a0SAriel Elior { 438ed5162a0SAriel Elior struct bnx2x_vlan_mac_registry_elem *pos; 4393ec9f9caSAriel Elior u8 *next = base; 440ed5162a0SAriel Elior int counter = 0; 441ed5162a0SAriel Elior 442ed5162a0SAriel Elior /* traverse list */ 443ed5162a0SAriel Elior list_for_each_entry(pos, &o->head, link) { 444ed5162a0SAriel Elior if (counter < n) { 4453ec9f9caSAriel Elior memcpy(next, &pos->u, size); 446ed5162a0SAriel Elior counter++; 4473ec9f9caSAriel Elior DP(BNX2X_MSG_SP, "copied element number %d to address %p element was:\n", 4483ec9f9caSAriel Elior counter, next); 4493ec9f9caSAriel Elior next += stride + size; 450ed5162a0SAriel Elior } 451ed5162a0SAriel Elior } 452ed5162a0SAriel Elior return counter * ETH_ALEN; 453ed5162a0SAriel Elior } 454ed5162a0SAriel Elior 455adfc5217SJeff Kirsher /* check_add() callbacks */ 45651c1a580SMerav Sicron static int bnx2x_check_mac_add(struct bnx2x *bp, 45751c1a580SMerav Sicron struct bnx2x_vlan_mac_obj *o, 458adfc5217SJeff Kirsher union bnx2x_classification_ramrod_data *data) 459adfc5217SJeff Kirsher { 460adfc5217SJeff Kirsher struct bnx2x_vlan_mac_registry_elem *pos; 461adfc5217SJeff Kirsher 46251c1a580SMerav Sicron DP(BNX2X_MSG_SP, "Checking MAC %pM for ADD command\n", data->mac.mac); 46351c1a580SMerav Sicron 464adfc5217SJeff Kirsher if (!is_valid_ether_addr(data->mac.mac)) 465adfc5217SJeff Kirsher return -EINVAL; 466adfc5217SJeff Kirsher 467adfc5217SJeff Kirsher /* Check if a requested MAC already exists */ 468adfc5217SJeff Kirsher list_for_each_entry(pos, &o->head, link) 46991226790SDmitry Kravkov if (!memcmp(data->mac.mac, pos->u.mac.mac, ETH_ALEN) && 47091226790SDmitry Kravkov (data->mac.is_inner_mac == pos->u.mac.is_inner_mac)) 471adfc5217SJeff Kirsher return -EEXIST; 472adfc5217SJeff Kirsher 473adfc5217SJeff Kirsher return 0; 474adfc5217SJeff Kirsher } 475adfc5217SJeff Kirsher 47651c1a580SMerav Sicron static int bnx2x_check_vlan_add(struct bnx2x *bp, 47751c1a580SMerav Sicron struct bnx2x_vlan_mac_obj *o, 478adfc5217SJeff Kirsher union bnx2x_classification_ramrod_data *data) 479adfc5217SJeff Kirsher { 480adfc5217SJeff Kirsher struct bnx2x_vlan_mac_registry_elem *pos; 481adfc5217SJeff Kirsher 48251c1a580SMerav Sicron DP(BNX2X_MSG_SP, "Checking VLAN %d for ADD command\n", data->vlan.vlan); 48351c1a580SMerav Sicron 484adfc5217SJeff Kirsher list_for_each_entry(pos, &o->head, link) 485adfc5217SJeff Kirsher if (data->vlan.vlan == pos->u.vlan.vlan) 486adfc5217SJeff Kirsher return -EEXIST; 487adfc5217SJeff Kirsher 488adfc5217SJeff Kirsher return 0; 489adfc5217SJeff Kirsher } 490adfc5217SJeff Kirsher 49151c1a580SMerav Sicron static int bnx2x_check_vlan_mac_add(struct bnx2x *bp, 49251c1a580SMerav Sicron struct bnx2x_vlan_mac_obj *o, 493adfc5217SJeff Kirsher union bnx2x_classification_ramrod_data *data) 494adfc5217SJeff Kirsher { 495adfc5217SJeff Kirsher struct bnx2x_vlan_mac_registry_elem *pos; 496adfc5217SJeff Kirsher 49751c1a580SMerav Sicron DP(BNX2X_MSG_SP, "Checking VLAN_MAC (%pM, %d) for ADD command\n", 49851c1a580SMerav Sicron data->vlan_mac.mac, data->vlan_mac.vlan); 49951c1a580SMerav Sicron 500adfc5217SJeff Kirsher list_for_each_entry(pos, &o->head, link) 501adfc5217SJeff Kirsher if ((data->vlan_mac.vlan == pos->u.vlan_mac.vlan) && 502adfc5217SJeff Kirsher (!memcmp(data->vlan_mac.mac, pos->u.vlan_mac.mac, 50391226790SDmitry Kravkov ETH_ALEN)) && 50491226790SDmitry Kravkov (data->vlan_mac.is_inner_mac == 50591226790SDmitry Kravkov pos->u.vlan_mac.is_inner_mac)) 506adfc5217SJeff Kirsher return -EEXIST; 507adfc5217SJeff Kirsher 508adfc5217SJeff Kirsher return 0; 509adfc5217SJeff Kirsher } 510adfc5217SJeff Kirsher 511adfc5217SJeff Kirsher /* check_del() callbacks */ 512adfc5217SJeff Kirsher static struct bnx2x_vlan_mac_registry_elem * 51351c1a580SMerav Sicron bnx2x_check_mac_del(struct bnx2x *bp, 51451c1a580SMerav Sicron struct bnx2x_vlan_mac_obj *o, 515adfc5217SJeff Kirsher union bnx2x_classification_ramrod_data *data) 516adfc5217SJeff Kirsher { 517adfc5217SJeff Kirsher struct bnx2x_vlan_mac_registry_elem *pos; 518adfc5217SJeff Kirsher 51951c1a580SMerav Sicron DP(BNX2X_MSG_SP, "Checking MAC %pM for DEL command\n", data->mac.mac); 52051c1a580SMerav Sicron 521adfc5217SJeff Kirsher list_for_each_entry(pos, &o->head, link) 52291226790SDmitry Kravkov if ((!memcmp(data->mac.mac, pos->u.mac.mac, ETH_ALEN)) && 52391226790SDmitry Kravkov (data->mac.is_inner_mac == pos->u.mac.is_inner_mac)) 524adfc5217SJeff Kirsher return pos; 525adfc5217SJeff Kirsher 526adfc5217SJeff Kirsher return NULL; 527adfc5217SJeff Kirsher } 528adfc5217SJeff Kirsher 529adfc5217SJeff Kirsher static struct bnx2x_vlan_mac_registry_elem * 53051c1a580SMerav Sicron bnx2x_check_vlan_del(struct bnx2x *bp, 53151c1a580SMerav Sicron struct bnx2x_vlan_mac_obj *o, 532adfc5217SJeff Kirsher union bnx2x_classification_ramrod_data *data) 533adfc5217SJeff Kirsher { 534adfc5217SJeff Kirsher struct bnx2x_vlan_mac_registry_elem *pos; 535adfc5217SJeff Kirsher 53651c1a580SMerav Sicron DP(BNX2X_MSG_SP, "Checking VLAN %d for DEL command\n", data->vlan.vlan); 53751c1a580SMerav Sicron 538adfc5217SJeff Kirsher list_for_each_entry(pos, &o->head, link) 539adfc5217SJeff Kirsher if (data->vlan.vlan == pos->u.vlan.vlan) 540adfc5217SJeff Kirsher return pos; 541adfc5217SJeff Kirsher 542adfc5217SJeff Kirsher return NULL; 543adfc5217SJeff Kirsher } 544adfc5217SJeff Kirsher 545adfc5217SJeff Kirsher static struct bnx2x_vlan_mac_registry_elem * 54651c1a580SMerav Sicron bnx2x_check_vlan_mac_del(struct bnx2x *bp, 54751c1a580SMerav Sicron struct bnx2x_vlan_mac_obj *o, 548adfc5217SJeff Kirsher union bnx2x_classification_ramrod_data *data) 549adfc5217SJeff Kirsher { 550adfc5217SJeff Kirsher struct bnx2x_vlan_mac_registry_elem *pos; 551adfc5217SJeff Kirsher 55251c1a580SMerav Sicron DP(BNX2X_MSG_SP, "Checking VLAN_MAC (%pM, %d) for DEL command\n", 55351c1a580SMerav Sicron data->vlan_mac.mac, data->vlan_mac.vlan); 55451c1a580SMerav Sicron 555adfc5217SJeff Kirsher list_for_each_entry(pos, &o->head, link) 556adfc5217SJeff Kirsher if ((data->vlan_mac.vlan == pos->u.vlan_mac.vlan) && 557adfc5217SJeff Kirsher (!memcmp(data->vlan_mac.mac, pos->u.vlan_mac.mac, 55891226790SDmitry Kravkov ETH_ALEN)) && 55991226790SDmitry Kravkov (data->vlan_mac.is_inner_mac == 56091226790SDmitry Kravkov pos->u.vlan_mac.is_inner_mac)) 561adfc5217SJeff Kirsher return pos; 562adfc5217SJeff Kirsher 563adfc5217SJeff Kirsher return NULL; 564adfc5217SJeff Kirsher } 565adfc5217SJeff Kirsher 566adfc5217SJeff Kirsher /* check_move() callback */ 56751c1a580SMerav Sicron static bool bnx2x_check_move(struct bnx2x *bp, 56851c1a580SMerav Sicron struct bnx2x_vlan_mac_obj *src_o, 569adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *dst_o, 570adfc5217SJeff Kirsher union bnx2x_classification_ramrod_data *data) 571adfc5217SJeff Kirsher { 572adfc5217SJeff Kirsher struct bnx2x_vlan_mac_registry_elem *pos; 573adfc5217SJeff Kirsher int rc; 574adfc5217SJeff Kirsher 575adfc5217SJeff Kirsher /* Check if we can delete the requested configuration from the first 576adfc5217SJeff Kirsher * object. 577adfc5217SJeff Kirsher */ 57851c1a580SMerav Sicron pos = src_o->check_del(bp, src_o, data); 579adfc5217SJeff Kirsher 580adfc5217SJeff Kirsher /* check if configuration can be added */ 58151c1a580SMerav Sicron rc = dst_o->check_add(bp, dst_o, data); 582adfc5217SJeff Kirsher 583adfc5217SJeff Kirsher /* If this classification can not be added (is already set) 584adfc5217SJeff Kirsher * or can't be deleted - return an error. 585adfc5217SJeff Kirsher */ 586adfc5217SJeff Kirsher if (rc || !pos) 587adfc5217SJeff Kirsher return false; 588adfc5217SJeff Kirsher 589adfc5217SJeff Kirsher return true; 590adfc5217SJeff Kirsher } 591adfc5217SJeff Kirsher 592adfc5217SJeff Kirsher static bool bnx2x_check_move_always_err( 59351c1a580SMerav Sicron struct bnx2x *bp, 594adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *src_o, 595adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *dst_o, 596adfc5217SJeff Kirsher union bnx2x_classification_ramrod_data *data) 597adfc5217SJeff Kirsher { 598adfc5217SJeff Kirsher return false; 599adfc5217SJeff Kirsher } 600adfc5217SJeff Kirsher 601adfc5217SJeff Kirsher static inline u8 bnx2x_vlan_mac_get_rx_tx_flag(struct bnx2x_vlan_mac_obj *o) 602adfc5217SJeff Kirsher { 603adfc5217SJeff Kirsher struct bnx2x_raw_obj *raw = &o->raw; 604adfc5217SJeff Kirsher u8 rx_tx_flag = 0; 605adfc5217SJeff Kirsher 606adfc5217SJeff Kirsher if ((raw->obj_type == BNX2X_OBJ_TYPE_TX) || 607adfc5217SJeff Kirsher (raw->obj_type == BNX2X_OBJ_TYPE_RX_TX)) 608adfc5217SJeff Kirsher rx_tx_flag |= ETH_CLASSIFY_CMD_HEADER_TX_CMD; 609adfc5217SJeff Kirsher 610adfc5217SJeff Kirsher if ((raw->obj_type == BNX2X_OBJ_TYPE_RX) || 611adfc5217SJeff Kirsher (raw->obj_type == BNX2X_OBJ_TYPE_RX_TX)) 612adfc5217SJeff Kirsher rx_tx_flag |= ETH_CLASSIFY_CMD_HEADER_RX_CMD; 613adfc5217SJeff Kirsher 614adfc5217SJeff Kirsher return rx_tx_flag; 615adfc5217SJeff Kirsher } 616adfc5217SJeff Kirsher 617a3348722SBarak Witkowski void bnx2x_set_mac_in_nig(struct bnx2x *bp, 618adfc5217SJeff Kirsher bool add, unsigned char *dev_addr, int index) 619adfc5217SJeff Kirsher { 620adfc5217SJeff Kirsher u32 wb_data[2]; 621adfc5217SJeff Kirsher u32 reg_offset = BP_PORT(bp) ? NIG_REG_LLH1_FUNC_MEM : 622adfc5217SJeff Kirsher NIG_REG_LLH0_FUNC_MEM; 623adfc5217SJeff Kirsher 624a3348722SBarak Witkowski if (!IS_MF_SI(bp) && !IS_MF_AFEX(bp)) 625a3348722SBarak Witkowski return; 626a3348722SBarak Witkowski 627a3348722SBarak Witkowski if (index > BNX2X_LLH_CAM_MAX_PF_LINE) 628adfc5217SJeff Kirsher return; 629adfc5217SJeff Kirsher 630adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "Going to %s LLH configuration at entry %d\n", 631adfc5217SJeff Kirsher (add ? "ADD" : "DELETE"), index); 632adfc5217SJeff Kirsher 633adfc5217SJeff Kirsher if (add) { 634adfc5217SJeff Kirsher /* LLH_FUNC_MEM is a u64 WB register */ 635adfc5217SJeff Kirsher reg_offset += 8*index; 636adfc5217SJeff Kirsher 637adfc5217SJeff Kirsher wb_data[0] = ((dev_addr[2] << 24) | (dev_addr[3] << 16) | 638adfc5217SJeff Kirsher (dev_addr[4] << 8) | dev_addr[5]); 639adfc5217SJeff Kirsher wb_data[1] = ((dev_addr[0] << 8) | dev_addr[1]); 640adfc5217SJeff Kirsher 641adfc5217SJeff Kirsher REG_WR_DMAE(bp, reg_offset, wb_data, 2); 642adfc5217SJeff Kirsher } 643adfc5217SJeff Kirsher 644adfc5217SJeff Kirsher REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_FUNC_MEM_ENABLE : 645adfc5217SJeff Kirsher NIG_REG_LLH0_FUNC_MEM_ENABLE) + 4*index, add); 646adfc5217SJeff Kirsher } 647adfc5217SJeff Kirsher 648adfc5217SJeff Kirsher /** 649adfc5217SJeff Kirsher * bnx2x_vlan_mac_set_cmd_hdr_e2 - set a header in a single classify ramrod 650adfc5217SJeff Kirsher * 651adfc5217SJeff Kirsher * @bp: device handle 652adfc5217SJeff Kirsher * @o: queue for which we want to configure this rule 653adfc5217SJeff Kirsher * @add: if true the command is an ADD command, DEL otherwise 654adfc5217SJeff Kirsher * @opcode: CLASSIFY_RULE_OPCODE_XXX 655adfc5217SJeff Kirsher * @hdr: pointer to a header to setup 656adfc5217SJeff Kirsher * 657adfc5217SJeff Kirsher */ 658adfc5217SJeff Kirsher static inline void bnx2x_vlan_mac_set_cmd_hdr_e2(struct bnx2x *bp, 659adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *o, bool add, int opcode, 660adfc5217SJeff Kirsher struct eth_classify_cmd_header *hdr) 661adfc5217SJeff Kirsher { 662adfc5217SJeff Kirsher struct bnx2x_raw_obj *raw = &o->raw; 663adfc5217SJeff Kirsher 664adfc5217SJeff Kirsher hdr->client_id = raw->cl_id; 665adfc5217SJeff Kirsher hdr->func_id = raw->func_id; 666adfc5217SJeff Kirsher 667adfc5217SJeff Kirsher /* Rx or/and Tx (internal switching) configuration ? */ 668adfc5217SJeff Kirsher hdr->cmd_general_data |= 669adfc5217SJeff Kirsher bnx2x_vlan_mac_get_rx_tx_flag(o); 670adfc5217SJeff Kirsher 671adfc5217SJeff Kirsher if (add) 672adfc5217SJeff Kirsher hdr->cmd_general_data |= ETH_CLASSIFY_CMD_HEADER_IS_ADD; 673adfc5217SJeff Kirsher 674adfc5217SJeff Kirsher hdr->cmd_general_data |= 675adfc5217SJeff Kirsher (opcode << ETH_CLASSIFY_CMD_HEADER_OPCODE_SHIFT); 676adfc5217SJeff Kirsher } 677adfc5217SJeff Kirsher 678adfc5217SJeff Kirsher /** 679adfc5217SJeff Kirsher * bnx2x_vlan_mac_set_rdata_hdr_e2 - set the classify ramrod data header 680adfc5217SJeff Kirsher * 681adfc5217SJeff Kirsher * @cid: connection id 682adfc5217SJeff Kirsher * @type: BNX2X_FILTER_XXX_PENDING 68316a5fd92SYuval Mintz * @hdr: pointer to header to setup 684adfc5217SJeff Kirsher * @rule_cnt: 685adfc5217SJeff Kirsher * 686adfc5217SJeff Kirsher * currently we always configure one rule and echo field to contain a CID and an 687adfc5217SJeff Kirsher * opcode type. 688adfc5217SJeff Kirsher */ 689adfc5217SJeff Kirsher static inline void bnx2x_vlan_mac_set_rdata_hdr_e2(u32 cid, int type, 690adfc5217SJeff Kirsher struct eth_classify_header *hdr, int rule_cnt) 691adfc5217SJeff Kirsher { 69286564c3fSYuval Mintz hdr->echo = cpu_to_le32((cid & BNX2X_SWCID_MASK) | 69386564c3fSYuval Mintz (type << BNX2X_SWCID_SHIFT)); 694adfc5217SJeff Kirsher hdr->rule_cnt = (u8)rule_cnt; 695adfc5217SJeff Kirsher } 696adfc5217SJeff Kirsher 697adfc5217SJeff Kirsher /* hw_config() callbacks */ 698adfc5217SJeff Kirsher static void bnx2x_set_one_mac_e2(struct bnx2x *bp, 699adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *o, 700adfc5217SJeff Kirsher struct bnx2x_exeq_elem *elem, int rule_idx, 701adfc5217SJeff Kirsher int cam_offset) 702adfc5217SJeff Kirsher { 703adfc5217SJeff Kirsher struct bnx2x_raw_obj *raw = &o->raw; 704adfc5217SJeff Kirsher struct eth_classify_rules_ramrod_data *data = 705adfc5217SJeff Kirsher (struct eth_classify_rules_ramrod_data *)(raw->rdata); 706adfc5217SJeff Kirsher int rule_cnt = rule_idx + 1, cmd = elem->cmd_data.vlan_mac.cmd; 707adfc5217SJeff Kirsher union eth_classify_rule_cmd *rule_entry = &data->rules[rule_idx]; 708adfc5217SJeff Kirsher bool add = (cmd == BNX2X_VLAN_MAC_ADD) ? true : false; 709adfc5217SJeff Kirsher unsigned long *vlan_mac_flags = &elem->cmd_data.vlan_mac.vlan_mac_flags; 710adfc5217SJeff Kirsher u8 *mac = elem->cmd_data.vlan_mac.u.mac.mac; 711adfc5217SJeff Kirsher 71216a5fd92SYuval Mintz /* Set LLH CAM entry: currently only iSCSI and ETH macs are 713adfc5217SJeff Kirsher * relevant. In addition, current implementation is tuned for a 714adfc5217SJeff Kirsher * single ETH MAC. 715adfc5217SJeff Kirsher * 716adfc5217SJeff Kirsher * When multiple unicast ETH MACs PF configuration in switch 717adfc5217SJeff Kirsher * independent mode is required (NetQ, multiple netdev MACs, 718adfc5217SJeff Kirsher * etc.), consider better utilisation of 8 per function MAC 719adfc5217SJeff Kirsher * entries in the LLH register. There is also 720adfc5217SJeff Kirsher * NIG_REG_P[01]_LLH_FUNC_MEM2 registers that complete the 721adfc5217SJeff Kirsher * total number of CAM entries to 16. 722adfc5217SJeff Kirsher * 723adfc5217SJeff Kirsher * Currently we won't configure NIG for MACs other than a primary ETH 724adfc5217SJeff Kirsher * MAC and iSCSI L2 MAC. 725adfc5217SJeff Kirsher * 726adfc5217SJeff Kirsher * If this MAC is moving from one Queue to another, no need to change 727adfc5217SJeff Kirsher * NIG configuration. 728adfc5217SJeff Kirsher */ 729adfc5217SJeff Kirsher if (cmd != BNX2X_VLAN_MAC_MOVE) { 730adfc5217SJeff Kirsher if (test_bit(BNX2X_ISCSI_ETH_MAC, vlan_mac_flags)) 731adfc5217SJeff Kirsher bnx2x_set_mac_in_nig(bp, add, mac, 7320a52fd01SYuval Mintz BNX2X_LLH_CAM_ISCSI_ETH_LINE); 733adfc5217SJeff Kirsher else if (test_bit(BNX2X_ETH_MAC, vlan_mac_flags)) 7340a52fd01SYuval Mintz bnx2x_set_mac_in_nig(bp, add, mac, 7350a52fd01SYuval Mintz BNX2X_LLH_CAM_ETH_LINE); 736adfc5217SJeff Kirsher } 737adfc5217SJeff Kirsher 738adfc5217SJeff Kirsher /* Reset the ramrod data buffer for the first rule */ 739adfc5217SJeff Kirsher if (rule_idx == 0) 740adfc5217SJeff Kirsher memset(data, 0, sizeof(*data)); 741adfc5217SJeff Kirsher 742adfc5217SJeff Kirsher /* Setup a command header */ 743adfc5217SJeff Kirsher bnx2x_vlan_mac_set_cmd_hdr_e2(bp, o, add, CLASSIFY_RULE_OPCODE_MAC, 744adfc5217SJeff Kirsher &rule_entry->mac.header); 745adfc5217SJeff Kirsher 7460f9dad10SJoe Perches DP(BNX2X_MSG_SP, "About to %s MAC %pM for Queue %d\n", 74751c1a580SMerav Sicron (add ? "add" : "delete"), mac, raw->cl_id); 748adfc5217SJeff Kirsher 749adfc5217SJeff Kirsher /* Set a MAC itself */ 750adfc5217SJeff Kirsher bnx2x_set_fw_mac_addr(&rule_entry->mac.mac_msb, 751adfc5217SJeff Kirsher &rule_entry->mac.mac_mid, 752adfc5217SJeff Kirsher &rule_entry->mac.mac_lsb, mac); 75391226790SDmitry Kravkov rule_entry->mac.inner_mac = 75491226790SDmitry Kravkov cpu_to_le16(elem->cmd_data.vlan_mac.u.mac.is_inner_mac); 755adfc5217SJeff Kirsher 756adfc5217SJeff Kirsher /* MOVE: Add a rule that will add this MAC to the target Queue */ 757adfc5217SJeff Kirsher if (cmd == BNX2X_VLAN_MAC_MOVE) { 758adfc5217SJeff Kirsher rule_entry++; 759adfc5217SJeff Kirsher rule_cnt++; 760adfc5217SJeff Kirsher 761adfc5217SJeff Kirsher /* Setup ramrod data */ 762adfc5217SJeff Kirsher bnx2x_vlan_mac_set_cmd_hdr_e2(bp, 763adfc5217SJeff Kirsher elem->cmd_data.vlan_mac.target_obj, 764adfc5217SJeff Kirsher true, CLASSIFY_RULE_OPCODE_MAC, 765adfc5217SJeff Kirsher &rule_entry->mac.header); 766adfc5217SJeff Kirsher 767adfc5217SJeff Kirsher /* Set a MAC itself */ 768adfc5217SJeff Kirsher bnx2x_set_fw_mac_addr(&rule_entry->mac.mac_msb, 769adfc5217SJeff Kirsher &rule_entry->mac.mac_mid, 770adfc5217SJeff Kirsher &rule_entry->mac.mac_lsb, mac); 77191226790SDmitry Kravkov rule_entry->mac.inner_mac = 77291226790SDmitry Kravkov cpu_to_le16(elem->cmd_data.vlan_mac. 77391226790SDmitry Kravkov u.mac.is_inner_mac); 774adfc5217SJeff Kirsher } 775adfc5217SJeff Kirsher 776adfc5217SJeff Kirsher /* Set the ramrod data header */ 777adfc5217SJeff Kirsher /* TODO: take this to the higher level in order to prevent multiple 778adfc5217SJeff Kirsher writing */ 779adfc5217SJeff Kirsher bnx2x_vlan_mac_set_rdata_hdr_e2(raw->cid, raw->state, &data->header, 780adfc5217SJeff Kirsher rule_cnt); 781adfc5217SJeff Kirsher } 782adfc5217SJeff Kirsher 783adfc5217SJeff Kirsher /** 784adfc5217SJeff Kirsher * bnx2x_vlan_mac_set_rdata_hdr_e1x - set a header in a single classify ramrod 785adfc5217SJeff Kirsher * 786adfc5217SJeff Kirsher * @bp: device handle 787adfc5217SJeff Kirsher * @o: queue 788adfc5217SJeff Kirsher * @type: 789adfc5217SJeff Kirsher * @cam_offset: offset in cam memory 790adfc5217SJeff Kirsher * @hdr: pointer to a header to setup 791adfc5217SJeff Kirsher * 792adfc5217SJeff Kirsher * E1/E1H 793adfc5217SJeff Kirsher */ 794adfc5217SJeff Kirsher static inline void bnx2x_vlan_mac_set_rdata_hdr_e1x(struct bnx2x *bp, 795adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *o, int type, int cam_offset, 796adfc5217SJeff Kirsher struct mac_configuration_hdr *hdr) 797adfc5217SJeff Kirsher { 798adfc5217SJeff Kirsher struct bnx2x_raw_obj *r = &o->raw; 799adfc5217SJeff Kirsher 800adfc5217SJeff Kirsher hdr->length = 1; 801adfc5217SJeff Kirsher hdr->offset = (u8)cam_offset; 80286564c3fSYuval Mintz hdr->client_id = cpu_to_le16(0xff); 80386564c3fSYuval Mintz hdr->echo = cpu_to_le32((r->cid & BNX2X_SWCID_MASK) | 80486564c3fSYuval Mintz (type << BNX2X_SWCID_SHIFT)); 805adfc5217SJeff Kirsher } 806adfc5217SJeff Kirsher 807adfc5217SJeff Kirsher static inline void bnx2x_vlan_mac_set_cfg_entry_e1x(struct bnx2x *bp, 808adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *o, bool add, int opcode, u8 *mac, 809adfc5217SJeff Kirsher u16 vlan_id, struct mac_configuration_entry *cfg_entry) 810adfc5217SJeff Kirsher { 811adfc5217SJeff Kirsher struct bnx2x_raw_obj *r = &o->raw; 812adfc5217SJeff Kirsher u32 cl_bit_vec = (1 << r->cl_id); 813adfc5217SJeff Kirsher 814adfc5217SJeff Kirsher cfg_entry->clients_bit_vector = cpu_to_le32(cl_bit_vec); 815adfc5217SJeff Kirsher cfg_entry->pf_id = r->func_id; 816adfc5217SJeff Kirsher cfg_entry->vlan_id = cpu_to_le16(vlan_id); 817adfc5217SJeff Kirsher 818adfc5217SJeff Kirsher if (add) { 819adfc5217SJeff Kirsher SET_FLAG(cfg_entry->flags, MAC_CONFIGURATION_ENTRY_ACTION_TYPE, 820adfc5217SJeff Kirsher T_ETH_MAC_COMMAND_SET); 821adfc5217SJeff Kirsher SET_FLAG(cfg_entry->flags, 822adfc5217SJeff Kirsher MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE, opcode); 823adfc5217SJeff Kirsher 824adfc5217SJeff Kirsher /* Set a MAC in a ramrod data */ 825adfc5217SJeff Kirsher bnx2x_set_fw_mac_addr(&cfg_entry->msb_mac_addr, 826adfc5217SJeff Kirsher &cfg_entry->middle_mac_addr, 827adfc5217SJeff Kirsher &cfg_entry->lsb_mac_addr, mac); 828adfc5217SJeff Kirsher } else 829adfc5217SJeff Kirsher SET_FLAG(cfg_entry->flags, MAC_CONFIGURATION_ENTRY_ACTION_TYPE, 830adfc5217SJeff Kirsher T_ETH_MAC_COMMAND_INVALIDATE); 831adfc5217SJeff Kirsher } 832adfc5217SJeff Kirsher 833adfc5217SJeff Kirsher static inline void bnx2x_vlan_mac_set_rdata_e1x(struct bnx2x *bp, 834adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *o, int type, int cam_offset, bool add, 835adfc5217SJeff Kirsher u8 *mac, u16 vlan_id, int opcode, struct mac_configuration_cmd *config) 836adfc5217SJeff Kirsher { 837adfc5217SJeff Kirsher struct mac_configuration_entry *cfg_entry = &config->config_table[0]; 838adfc5217SJeff Kirsher struct bnx2x_raw_obj *raw = &o->raw; 839adfc5217SJeff Kirsher 840adfc5217SJeff Kirsher bnx2x_vlan_mac_set_rdata_hdr_e1x(bp, o, type, cam_offset, 841adfc5217SJeff Kirsher &config->hdr); 842adfc5217SJeff Kirsher bnx2x_vlan_mac_set_cfg_entry_e1x(bp, o, add, opcode, mac, vlan_id, 843adfc5217SJeff Kirsher cfg_entry); 844adfc5217SJeff Kirsher 8450f9dad10SJoe Perches DP(BNX2X_MSG_SP, "%s MAC %pM CLID %d CAM offset %d\n", 84651c1a580SMerav Sicron (add ? "setting" : "clearing"), 8470f9dad10SJoe Perches mac, raw->cl_id, cam_offset); 848adfc5217SJeff Kirsher } 849adfc5217SJeff Kirsher 850adfc5217SJeff Kirsher /** 851adfc5217SJeff Kirsher * bnx2x_set_one_mac_e1x - fill a single MAC rule ramrod data 852adfc5217SJeff Kirsher * 853adfc5217SJeff Kirsher * @bp: device handle 854adfc5217SJeff Kirsher * @o: bnx2x_vlan_mac_obj 855adfc5217SJeff Kirsher * @elem: bnx2x_exeq_elem 856adfc5217SJeff Kirsher * @rule_idx: rule_idx 857adfc5217SJeff Kirsher * @cam_offset: cam_offset 858adfc5217SJeff Kirsher */ 859adfc5217SJeff Kirsher static void bnx2x_set_one_mac_e1x(struct bnx2x *bp, 860adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *o, 861adfc5217SJeff Kirsher struct bnx2x_exeq_elem *elem, int rule_idx, 862adfc5217SJeff Kirsher int cam_offset) 863adfc5217SJeff Kirsher { 864adfc5217SJeff Kirsher struct bnx2x_raw_obj *raw = &o->raw; 865adfc5217SJeff Kirsher struct mac_configuration_cmd *config = 866adfc5217SJeff Kirsher (struct mac_configuration_cmd *)(raw->rdata); 86716a5fd92SYuval Mintz /* 57710 and 57711 do not support MOVE command, 868adfc5217SJeff Kirsher * so it's either ADD or DEL 869adfc5217SJeff Kirsher */ 870adfc5217SJeff Kirsher bool add = (elem->cmd_data.vlan_mac.cmd == BNX2X_VLAN_MAC_ADD) ? 871adfc5217SJeff Kirsher true : false; 872adfc5217SJeff Kirsher 873adfc5217SJeff Kirsher /* Reset the ramrod data buffer */ 874adfc5217SJeff Kirsher memset(config, 0, sizeof(*config)); 875adfc5217SJeff Kirsher 87633ac338cSYuval Mintz bnx2x_vlan_mac_set_rdata_e1x(bp, o, raw->state, 877adfc5217SJeff Kirsher cam_offset, add, 878adfc5217SJeff Kirsher elem->cmd_data.vlan_mac.u.mac.mac, 0, 879adfc5217SJeff Kirsher ETH_VLAN_FILTER_ANY_VLAN, config); 880adfc5217SJeff Kirsher } 881adfc5217SJeff Kirsher 882adfc5217SJeff Kirsher static void bnx2x_set_one_vlan_e2(struct bnx2x *bp, 883adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *o, 884adfc5217SJeff Kirsher struct bnx2x_exeq_elem *elem, int rule_idx, 885adfc5217SJeff Kirsher int cam_offset) 886adfc5217SJeff Kirsher { 887adfc5217SJeff Kirsher struct bnx2x_raw_obj *raw = &o->raw; 888adfc5217SJeff Kirsher struct eth_classify_rules_ramrod_data *data = 889adfc5217SJeff Kirsher (struct eth_classify_rules_ramrod_data *)(raw->rdata); 890adfc5217SJeff Kirsher int rule_cnt = rule_idx + 1; 891adfc5217SJeff Kirsher union eth_classify_rule_cmd *rule_entry = &data->rules[rule_idx]; 89286564c3fSYuval Mintz enum bnx2x_vlan_mac_cmd cmd = elem->cmd_data.vlan_mac.cmd; 893adfc5217SJeff Kirsher bool add = (cmd == BNX2X_VLAN_MAC_ADD) ? true : false; 894adfc5217SJeff Kirsher u16 vlan = elem->cmd_data.vlan_mac.u.vlan.vlan; 895adfc5217SJeff Kirsher 896adfc5217SJeff Kirsher /* Reset the ramrod data buffer for the first rule */ 897adfc5217SJeff Kirsher if (rule_idx == 0) 898adfc5217SJeff Kirsher memset(data, 0, sizeof(*data)); 899adfc5217SJeff Kirsher 900adfc5217SJeff Kirsher /* Set a rule header */ 901adfc5217SJeff Kirsher bnx2x_vlan_mac_set_cmd_hdr_e2(bp, o, add, CLASSIFY_RULE_OPCODE_VLAN, 902adfc5217SJeff Kirsher &rule_entry->vlan.header); 903adfc5217SJeff Kirsher 904adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "About to %s VLAN %d\n", (add ? "add" : "delete"), 905adfc5217SJeff Kirsher vlan); 906adfc5217SJeff Kirsher 907adfc5217SJeff Kirsher /* Set a VLAN itself */ 908adfc5217SJeff Kirsher rule_entry->vlan.vlan = cpu_to_le16(vlan); 909adfc5217SJeff Kirsher 910adfc5217SJeff Kirsher /* MOVE: Add a rule that will add this MAC to the target Queue */ 911adfc5217SJeff Kirsher if (cmd == BNX2X_VLAN_MAC_MOVE) { 912adfc5217SJeff Kirsher rule_entry++; 913adfc5217SJeff Kirsher rule_cnt++; 914adfc5217SJeff Kirsher 915adfc5217SJeff Kirsher /* Setup ramrod data */ 916adfc5217SJeff Kirsher bnx2x_vlan_mac_set_cmd_hdr_e2(bp, 917adfc5217SJeff Kirsher elem->cmd_data.vlan_mac.target_obj, 918adfc5217SJeff Kirsher true, CLASSIFY_RULE_OPCODE_VLAN, 919adfc5217SJeff Kirsher &rule_entry->vlan.header); 920adfc5217SJeff Kirsher 921adfc5217SJeff Kirsher /* Set a VLAN itself */ 922adfc5217SJeff Kirsher rule_entry->vlan.vlan = cpu_to_le16(vlan); 923adfc5217SJeff Kirsher } 924adfc5217SJeff Kirsher 925adfc5217SJeff Kirsher /* Set the ramrod data header */ 926adfc5217SJeff Kirsher /* TODO: take this to the higher level in order to prevent multiple 927adfc5217SJeff Kirsher writing */ 928adfc5217SJeff Kirsher bnx2x_vlan_mac_set_rdata_hdr_e2(raw->cid, raw->state, &data->header, 929adfc5217SJeff Kirsher rule_cnt); 930adfc5217SJeff Kirsher } 931adfc5217SJeff Kirsher 932adfc5217SJeff Kirsher static void bnx2x_set_one_vlan_mac_e2(struct bnx2x *bp, 933adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *o, 934adfc5217SJeff Kirsher struct bnx2x_exeq_elem *elem, 935adfc5217SJeff Kirsher int rule_idx, int cam_offset) 936adfc5217SJeff Kirsher { 937adfc5217SJeff Kirsher struct bnx2x_raw_obj *raw = &o->raw; 938adfc5217SJeff Kirsher struct eth_classify_rules_ramrod_data *data = 939adfc5217SJeff Kirsher (struct eth_classify_rules_ramrod_data *)(raw->rdata); 940adfc5217SJeff Kirsher int rule_cnt = rule_idx + 1; 941adfc5217SJeff Kirsher union eth_classify_rule_cmd *rule_entry = &data->rules[rule_idx]; 94286564c3fSYuval Mintz enum bnx2x_vlan_mac_cmd cmd = elem->cmd_data.vlan_mac.cmd; 943adfc5217SJeff Kirsher bool add = (cmd == BNX2X_VLAN_MAC_ADD) ? true : false; 944adfc5217SJeff Kirsher u16 vlan = elem->cmd_data.vlan_mac.u.vlan_mac.vlan; 945adfc5217SJeff Kirsher u8 *mac = elem->cmd_data.vlan_mac.u.vlan_mac.mac; 946adfc5217SJeff Kirsher 947adfc5217SJeff Kirsher /* Reset the ramrod data buffer for the first rule */ 948adfc5217SJeff Kirsher if (rule_idx == 0) 949adfc5217SJeff Kirsher memset(data, 0, sizeof(*data)); 950adfc5217SJeff Kirsher 951adfc5217SJeff Kirsher /* Set a rule header */ 952adfc5217SJeff Kirsher bnx2x_vlan_mac_set_cmd_hdr_e2(bp, o, add, CLASSIFY_RULE_OPCODE_PAIR, 953adfc5217SJeff Kirsher &rule_entry->pair.header); 954adfc5217SJeff Kirsher 95516a5fd92SYuval Mintz /* Set VLAN and MAC themselves */ 956adfc5217SJeff Kirsher rule_entry->pair.vlan = cpu_to_le16(vlan); 957adfc5217SJeff Kirsher bnx2x_set_fw_mac_addr(&rule_entry->pair.mac_msb, 958adfc5217SJeff Kirsher &rule_entry->pair.mac_mid, 959adfc5217SJeff Kirsher &rule_entry->pair.mac_lsb, mac); 96091226790SDmitry Kravkov rule_entry->pair.inner_mac = 96191226790SDmitry Kravkov cpu_to_le16(elem->cmd_data.vlan_mac.u.vlan_mac.is_inner_mac); 962adfc5217SJeff Kirsher /* MOVE: Add a rule that will add this MAC to the target Queue */ 963adfc5217SJeff Kirsher if (cmd == BNX2X_VLAN_MAC_MOVE) { 964adfc5217SJeff Kirsher rule_entry++; 965adfc5217SJeff Kirsher rule_cnt++; 966adfc5217SJeff Kirsher 967adfc5217SJeff Kirsher /* Setup ramrod data */ 968adfc5217SJeff Kirsher bnx2x_vlan_mac_set_cmd_hdr_e2(bp, 969adfc5217SJeff Kirsher elem->cmd_data.vlan_mac.target_obj, 970adfc5217SJeff Kirsher true, CLASSIFY_RULE_OPCODE_PAIR, 971adfc5217SJeff Kirsher &rule_entry->pair.header); 972adfc5217SJeff Kirsher 973adfc5217SJeff Kirsher /* Set a VLAN itself */ 974adfc5217SJeff Kirsher rule_entry->pair.vlan = cpu_to_le16(vlan); 975adfc5217SJeff Kirsher bnx2x_set_fw_mac_addr(&rule_entry->pair.mac_msb, 976adfc5217SJeff Kirsher &rule_entry->pair.mac_mid, 977adfc5217SJeff Kirsher &rule_entry->pair.mac_lsb, mac); 97891226790SDmitry Kravkov rule_entry->pair.inner_mac = 97991226790SDmitry Kravkov cpu_to_le16(elem->cmd_data.vlan_mac.u. 98091226790SDmitry Kravkov vlan_mac.is_inner_mac); 981adfc5217SJeff Kirsher } 982adfc5217SJeff Kirsher 983adfc5217SJeff Kirsher /* Set the ramrod data header */ 984adfc5217SJeff Kirsher /* TODO: take this to the higher level in order to prevent multiple 985adfc5217SJeff Kirsher writing */ 986adfc5217SJeff Kirsher bnx2x_vlan_mac_set_rdata_hdr_e2(raw->cid, raw->state, &data->header, 987adfc5217SJeff Kirsher rule_cnt); 988adfc5217SJeff Kirsher } 989adfc5217SJeff Kirsher 990adfc5217SJeff Kirsher /** 991adfc5217SJeff Kirsher * bnx2x_set_one_vlan_mac_e1h - 992adfc5217SJeff Kirsher * 993adfc5217SJeff Kirsher * @bp: device handle 994adfc5217SJeff Kirsher * @o: bnx2x_vlan_mac_obj 995adfc5217SJeff Kirsher * @elem: bnx2x_exeq_elem 996adfc5217SJeff Kirsher * @rule_idx: rule_idx 997adfc5217SJeff Kirsher * @cam_offset: cam_offset 998adfc5217SJeff Kirsher */ 999adfc5217SJeff Kirsher static void bnx2x_set_one_vlan_mac_e1h(struct bnx2x *bp, 1000adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *o, 1001adfc5217SJeff Kirsher struct bnx2x_exeq_elem *elem, 1002adfc5217SJeff Kirsher int rule_idx, int cam_offset) 1003adfc5217SJeff Kirsher { 1004adfc5217SJeff Kirsher struct bnx2x_raw_obj *raw = &o->raw; 1005adfc5217SJeff Kirsher struct mac_configuration_cmd *config = 1006adfc5217SJeff Kirsher (struct mac_configuration_cmd *)(raw->rdata); 100716a5fd92SYuval Mintz /* 57710 and 57711 do not support MOVE command, 1008adfc5217SJeff Kirsher * so it's either ADD or DEL 1009adfc5217SJeff Kirsher */ 1010adfc5217SJeff Kirsher bool add = (elem->cmd_data.vlan_mac.cmd == BNX2X_VLAN_MAC_ADD) ? 1011adfc5217SJeff Kirsher true : false; 1012adfc5217SJeff Kirsher 1013adfc5217SJeff Kirsher /* Reset the ramrod data buffer */ 1014adfc5217SJeff Kirsher memset(config, 0, sizeof(*config)); 1015adfc5217SJeff Kirsher 1016adfc5217SJeff Kirsher bnx2x_vlan_mac_set_rdata_e1x(bp, o, BNX2X_FILTER_VLAN_MAC_PENDING, 1017adfc5217SJeff Kirsher cam_offset, add, 1018adfc5217SJeff Kirsher elem->cmd_data.vlan_mac.u.vlan_mac.mac, 1019adfc5217SJeff Kirsher elem->cmd_data.vlan_mac.u.vlan_mac.vlan, 1020adfc5217SJeff Kirsher ETH_VLAN_FILTER_CLASSIFY, config); 1021adfc5217SJeff Kirsher } 1022adfc5217SJeff Kirsher 1023adfc5217SJeff Kirsher #define list_next_entry(pos, member) \ 1024adfc5217SJeff Kirsher list_entry((pos)->member.next, typeof(*(pos)), member) 1025adfc5217SJeff Kirsher 1026adfc5217SJeff Kirsher /** 1027adfc5217SJeff Kirsher * bnx2x_vlan_mac_restore - reconfigure next MAC/VLAN/VLAN-MAC element 1028adfc5217SJeff Kirsher * 1029adfc5217SJeff Kirsher * @bp: device handle 1030adfc5217SJeff Kirsher * @p: command parameters 103116a5fd92SYuval Mintz * @ppos: pointer to the cookie 1032adfc5217SJeff Kirsher * 1033adfc5217SJeff Kirsher * reconfigure next MAC/VLAN/VLAN-MAC element from the 1034adfc5217SJeff Kirsher * previously configured elements list. 1035adfc5217SJeff Kirsher * 1036adfc5217SJeff Kirsher * from command parameters only RAMROD_COMP_WAIT bit in ramrod_flags is taken 1037adfc5217SJeff Kirsher * into an account 1038adfc5217SJeff Kirsher * 103916a5fd92SYuval Mintz * pointer to the cookie - that should be given back in the next call to make 1040adfc5217SJeff Kirsher * function handle the next element. If *ppos is set to NULL it will restart the 1041adfc5217SJeff Kirsher * iterator. If returned *ppos == NULL this means that the last element has been 1042adfc5217SJeff Kirsher * handled. 1043adfc5217SJeff Kirsher * 1044adfc5217SJeff Kirsher */ 1045adfc5217SJeff Kirsher static int bnx2x_vlan_mac_restore(struct bnx2x *bp, 1046adfc5217SJeff Kirsher struct bnx2x_vlan_mac_ramrod_params *p, 1047adfc5217SJeff Kirsher struct bnx2x_vlan_mac_registry_elem **ppos) 1048adfc5217SJeff Kirsher { 1049adfc5217SJeff Kirsher struct bnx2x_vlan_mac_registry_elem *pos; 1050adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *o = p->vlan_mac_obj; 1051adfc5217SJeff Kirsher 1052adfc5217SJeff Kirsher /* If list is empty - there is nothing to do here */ 1053adfc5217SJeff Kirsher if (list_empty(&o->head)) { 1054adfc5217SJeff Kirsher *ppos = NULL; 1055adfc5217SJeff Kirsher return 0; 1056adfc5217SJeff Kirsher } 1057adfc5217SJeff Kirsher 1058adfc5217SJeff Kirsher /* make a step... */ 1059adfc5217SJeff Kirsher if (*ppos == NULL) 1060adfc5217SJeff Kirsher *ppos = list_first_entry(&o->head, 1061adfc5217SJeff Kirsher struct bnx2x_vlan_mac_registry_elem, 1062adfc5217SJeff Kirsher link); 1063adfc5217SJeff Kirsher else 1064adfc5217SJeff Kirsher *ppos = list_next_entry(*ppos, link); 1065adfc5217SJeff Kirsher 1066adfc5217SJeff Kirsher pos = *ppos; 1067adfc5217SJeff Kirsher 1068adfc5217SJeff Kirsher /* If it's the last step - return NULL */ 1069adfc5217SJeff Kirsher if (list_is_last(&pos->link, &o->head)) 1070adfc5217SJeff Kirsher *ppos = NULL; 1071adfc5217SJeff Kirsher 1072adfc5217SJeff Kirsher /* Prepare a 'user_req' */ 1073adfc5217SJeff Kirsher memcpy(&p->user_req.u, &pos->u, sizeof(pos->u)); 1074adfc5217SJeff Kirsher 1075adfc5217SJeff Kirsher /* Set the command */ 1076adfc5217SJeff Kirsher p->user_req.cmd = BNX2X_VLAN_MAC_ADD; 1077adfc5217SJeff Kirsher 1078adfc5217SJeff Kirsher /* Set vlan_mac_flags */ 1079adfc5217SJeff Kirsher p->user_req.vlan_mac_flags = pos->vlan_mac_flags; 1080adfc5217SJeff Kirsher 1081adfc5217SJeff Kirsher /* Set a restore bit */ 1082adfc5217SJeff Kirsher __set_bit(RAMROD_RESTORE, &p->ramrod_flags); 1083adfc5217SJeff Kirsher 1084adfc5217SJeff Kirsher return bnx2x_config_vlan_mac(bp, p); 1085adfc5217SJeff Kirsher } 1086adfc5217SJeff Kirsher 108716a5fd92SYuval Mintz /* bnx2x_exeq_get_mac/bnx2x_exeq_get_vlan/bnx2x_exeq_get_vlan_mac return a 1088adfc5217SJeff Kirsher * pointer to an element with a specific criteria and NULL if such an element 1089adfc5217SJeff Kirsher * hasn't been found. 1090adfc5217SJeff Kirsher */ 1091adfc5217SJeff Kirsher static struct bnx2x_exeq_elem *bnx2x_exeq_get_mac( 1092adfc5217SJeff Kirsher struct bnx2x_exe_queue_obj *o, 1093adfc5217SJeff Kirsher struct bnx2x_exeq_elem *elem) 1094adfc5217SJeff Kirsher { 1095adfc5217SJeff Kirsher struct bnx2x_exeq_elem *pos; 1096adfc5217SJeff Kirsher struct bnx2x_mac_ramrod_data *data = &elem->cmd_data.vlan_mac.u.mac; 1097adfc5217SJeff Kirsher 1098adfc5217SJeff Kirsher /* Check pending for execution commands */ 1099adfc5217SJeff Kirsher list_for_each_entry(pos, &o->exe_queue, link) 1100adfc5217SJeff Kirsher if (!memcmp(&pos->cmd_data.vlan_mac.u.mac, data, 1101adfc5217SJeff Kirsher sizeof(*data)) && 1102adfc5217SJeff Kirsher (pos->cmd_data.vlan_mac.cmd == elem->cmd_data.vlan_mac.cmd)) 1103adfc5217SJeff Kirsher return pos; 1104adfc5217SJeff Kirsher 1105adfc5217SJeff Kirsher return NULL; 1106adfc5217SJeff Kirsher } 1107adfc5217SJeff Kirsher 1108adfc5217SJeff Kirsher static struct bnx2x_exeq_elem *bnx2x_exeq_get_vlan( 1109adfc5217SJeff Kirsher struct bnx2x_exe_queue_obj *o, 1110adfc5217SJeff Kirsher struct bnx2x_exeq_elem *elem) 1111adfc5217SJeff Kirsher { 1112adfc5217SJeff Kirsher struct bnx2x_exeq_elem *pos; 1113adfc5217SJeff Kirsher struct bnx2x_vlan_ramrod_data *data = &elem->cmd_data.vlan_mac.u.vlan; 1114adfc5217SJeff Kirsher 1115adfc5217SJeff Kirsher /* Check pending for execution commands */ 1116adfc5217SJeff Kirsher list_for_each_entry(pos, &o->exe_queue, link) 1117adfc5217SJeff Kirsher if (!memcmp(&pos->cmd_data.vlan_mac.u.vlan, data, 1118adfc5217SJeff Kirsher sizeof(*data)) && 1119adfc5217SJeff Kirsher (pos->cmd_data.vlan_mac.cmd == elem->cmd_data.vlan_mac.cmd)) 1120adfc5217SJeff Kirsher return pos; 1121adfc5217SJeff Kirsher 1122adfc5217SJeff Kirsher return NULL; 1123adfc5217SJeff Kirsher } 1124adfc5217SJeff Kirsher 1125adfc5217SJeff Kirsher static struct bnx2x_exeq_elem *bnx2x_exeq_get_vlan_mac( 1126adfc5217SJeff Kirsher struct bnx2x_exe_queue_obj *o, 1127adfc5217SJeff Kirsher struct bnx2x_exeq_elem *elem) 1128adfc5217SJeff Kirsher { 1129adfc5217SJeff Kirsher struct bnx2x_exeq_elem *pos; 1130adfc5217SJeff Kirsher struct bnx2x_vlan_mac_ramrod_data *data = 1131adfc5217SJeff Kirsher &elem->cmd_data.vlan_mac.u.vlan_mac; 1132adfc5217SJeff Kirsher 1133adfc5217SJeff Kirsher /* Check pending for execution commands */ 1134adfc5217SJeff Kirsher list_for_each_entry(pos, &o->exe_queue, link) 1135adfc5217SJeff Kirsher if (!memcmp(&pos->cmd_data.vlan_mac.u.vlan_mac, data, 1136adfc5217SJeff Kirsher sizeof(*data)) && 1137adfc5217SJeff Kirsher (pos->cmd_data.vlan_mac.cmd == elem->cmd_data.vlan_mac.cmd)) 1138adfc5217SJeff Kirsher return pos; 1139adfc5217SJeff Kirsher 1140adfc5217SJeff Kirsher return NULL; 1141adfc5217SJeff Kirsher } 1142adfc5217SJeff Kirsher 1143adfc5217SJeff Kirsher /** 1144adfc5217SJeff Kirsher * bnx2x_validate_vlan_mac_add - check if an ADD command can be executed 1145adfc5217SJeff Kirsher * 1146adfc5217SJeff Kirsher * @bp: device handle 1147adfc5217SJeff Kirsher * @qo: bnx2x_qable_obj 1148adfc5217SJeff Kirsher * @elem: bnx2x_exeq_elem 1149adfc5217SJeff Kirsher * 1150adfc5217SJeff Kirsher * Checks that the requested configuration can be added. If yes and if 1151adfc5217SJeff Kirsher * requested, consume CAM credit. 1152adfc5217SJeff Kirsher * 1153adfc5217SJeff Kirsher * The 'validate' is run after the 'optimize'. 1154adfc5217SJeff Kirsher * 1155adfc5217SJeff Kirsher */ 1156adfc5217SJeff Kirsher static inline int bnx2x_validate_vlan_mac_add(struct bnx2x *bp, 1157adfc5217SJeff Kirsher union bnx2x_qable_obj *qo, 1158adfc5217SJeff Kirsher struct bnx2x_exeq_elem *elem) 1159adfc5217SJeff Kirsher { 1160adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *o = &qo->vlan_mac; 1161adfc5217SJeff Kirsher struct bnx2x_exe_queue_obj *exeq = &o->exe_queue; 1162adfc5217SJeff Kirsher int rc; 1163adfc5217SJeff Kirsher 1164adfc5217SJeff Kirsher /* Check the registry */ 116551c1a580SMerav Sicron rc = o->check_add(bp, o, &elem->cmd_data.vlan_mac.u); 1166adfc5217SJeff Kirsher if (rc) { 116751c1a580SMerav Sicron DP(BNX2X_MSG_SP, "ADD command is not allowed considering current registry state.\n"); 1168adfc5217SJeff Kirsher return rc; 1169adfc5217SJeff Kirsher } 1170adfc5217SJeff Kirsher 117116a5fd92SYuval Mintz /* Check if there is a pending ADD command for this 1172adfc5217SJeff Kirsher * MAC/VLAN/VLAN-MAC. Return an error if there is. 1173adfc5217SJeff Kirsher */ 1174adfc5217SJeff Kirsher if (exeq->get(exeq, elem)) { 1175adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "There is a pending ADD command already\n"); 1176adfc5217SJeff Kirsher return -EEXIST; 1177adfc5217SJeff Kirsher } 1178adfc5217SJeff Kirsher 117916a5fd92SYuval Mintz /* TODO: Check the pending MOVE from other objects where this 1180adfc5217SJeff Kirsher * object is a destination object. 1181adfc5217SJeff Kirsher */ 1182adfc5217SJeff Kirsher 1183adfc5217SJeff Kirsher /* Consume the credit if not requested not to */ 1184adfc5217SJeff Kirsher if (!(test_bit(BNX2X_DONT_CONSUME_CAM_CREDIT, 1185adfc5217SJeff Kirsher &elem->cmd_data.vlan_mac.vlan_mac_flags) || 1186adfc5217SJeff Kirsher o->get_credit(o))) 1187adfc5217SJeff Kirsher return -EINVAL; 1188adfc5217SJeff Kirsher 1189adfc5217SJeff Kirsher return 0; 1190adfc5217SJeff Kirsher } 1191adfc5217SJeff Kirsher 1192adfc5217SJeff Kirsher /** 1193adfc5217SJeff Kirsher * bnx2x_validate_vlan_mac_del - check if the DEL command can be executed 1194adfc5217SJeff Kirsher * 1195adfc5217SJeff Kirsher * @bp: device handle 1196adfc5217SJeff Kirsher * @qo: quable object to check 1197adfc5217SJeff Kirsher * @elem: element that needs to be deleted 1198adfc5217SJeff Kirsher * 1199adfc5217SJeff Kirsher * Checks that the requested configuration can be deleted. If yes and if 1200adfc5217SJeff Kirsher * requested, returns a CAM credit. 1201adfc5217SJeff Kirsher * 1202adfc5217SJeff Kirsher * The 'validate' is run after the 'optimize'. 1203adfc5217SJeff Kirsher */ 1204adfc5217SJeff Kirsher static inline int bnx2x_validate_vlan_mac_del(struct bnx2x *bp, 1205adfc5217SJeff Kirsher union bnx2x_qable_obj *qo, 1206adfc5217SJeff Kirsher struct bnx2x_exeq_elem *elem) 1207adfc5217SJeff Kirsher { 1208adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *o = &qo->vlan_mac; 1209adfc5217SJeff Kirsher struct bnx2x_vlan_mac_registry_elem *pos; 1210adfc5217SJeff Kirsher struct bnx2x_exe_queue_obj *exeq = &o->exe_queue; 1211adfc5217SJeff Kirsher struct bnx2x_exeq_elem query_elem; 1212adfc5217SJeff Kirsher 1213adfc5217SJeff Kirsher /* If this classification can not be deleted (doesn't exist) 1214adfc5217SJeff Kirsher * - return a BNX2X_EXIST. 1215adfc5217SJeff Kirsher */ 121651c1a580SMerav Sicron pos = o->check_del(bp, o, &elem->cmd_data.vlan_mac.u); 1217adfc5217SJeff Kirsher if (!pos) { 121851c1a580SMerav Sicron DP(BNX2X_MSG_SP, "DEL command is not allowed considering current registry state\n"); 1219adfc5217SJeff Kirsher return -EEXIST; 1220adfc5217SJeff Kirsher } 1221adfc5217SJeff Kirsher 122216a5fd92SYuval Mintz /* Check if there are pending DEL or MOVE commands for this 1223adfc5217SJeff Kirsher * MAC/VLAN/VLAN-MAC. Return an error if so. 1224adfc5217SJeff Kirsher */ 1225adfc5217SJeff Kirsher memcpy(&query_elem, elem, sizeof(query_elem)); 1226adfc5217SJeff Kirsher 1227adfc5217SJeff Kirsher /* Check for MOVE commands */ 1228adfc5217SJeff Kirsher query_elem.cmd_data.vlan_mac.cmd = BNX2X_VLAN_MAC_MOVE; 1229adfc5217SJeff Kirsher if (exeq->get(exeq, &query_elem)) { 1230adfc5217SJeff Kirsher BNX2X_ERR("There is a pending MOVE command already\n"); 1231adfc5217SJeff Kirsher return -EINVAL; 1232adfc5217SJeff Kirsher } 1233adfc5217SJeff Kirsher 1234adfc5217SJeff Kirsher /* Check for DEL commands */ 1235adfc5217SJeff Kirsher if (exeq->get(exeq, elem)) { 1236adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "There is a pending DEL command already\n"); 1237adfc5217SJeff Kirsher return -EEXIST; 1238adfc5217SJeff Kirsher } 1239adfc5217SJeff Kirsher 1240adfc5217SJeff Kirsher /* Return the credit to the credit pool if not requested not to */ 1241adfc5217SJeff Kirsher if (!(test_bit(BNX2X_DONT_CONSUME_CAM_CREDIT, 1242adfc5217SJeff Kirsher &elem->cmd_data.vlan_mac.vlan_mac_flags) || 1243adfc5217SJeff Kirsher o->put_credit(o))) { 1244adfc5217SJeff Kirsher BNX2X_ERR("Failed to return a credit\n"); 1245adfc5217SJeff Kirsher return -EINVAL; 1246adfc5217SJeff Kirsher } 1247adfc5217SJeff Kirsher 1248adfc5217SJeff Kirsher return 0; 1249adfc5217SJeff Kirsher } 1250adfc5217SJeff Kirsher 1251adfc5217SJeff Kirsher /** 1252adfc5217SJeff Kirsher * bnx2x_validate_vlan_mac_move - check if the MOVE command can be executed 1253adfc5217SJeff Kirsher * 1254adfc5217SJeff Kirsher * @bp: device handle 1255adfc5217SJeff Kirsher * @qo: quable object to check (source) 1256adfc5217SJeff Kirsher * @elem: element that needs to be moved 1257adfc5217SJeff Kirsher * 1258adfc5217SJeff Kirsher * Checks that the requested configuration can be moved. If yes and if 1259adfc5217SJeff Kirsher * requested, returns a CAM credit. 1260adfc5217SJeff Kirsher * 1261adfc5217SJeff Kirsher * The 'validate' is run after the 'optimize'. 1262adfc5217SJeff Kirsher */ 1263adfc5217SJeff Kirsher static inline int bnx2x_validate_vlan_mac_move(struct bnx2x *bp, 1264adfc5217SJeff Kirsher union bnx2x_qable_obj *qo, 1265adfc5217SJeff Kirsher struct bnx2x_exeq_elem *elem) 1266adfc5217SJeff Kirsher { 1267adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *src_o = &qo->vlan_mac; 1268adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *dest_o = elem->cmd_data.vlan_mac.target_obj; 1269adfc5217SJeff Kirsher struct bnx2x_exeq_elem query_elem; 1270adfc5217SJeff Kirsher struct bnx2x_exe_queue_obj *src_exeq = &src_o->exe_queue; 1271adfc5217SJeff Kirsher struct bnx2x_exe_queue_obj *dest_exeq = &dest_o->exe_queue; 1272adfc5217SJeff Kirsher 127316a5fd92SYuval Mintz /* Check if we can perform this operation based on the current registry 1274adfc5217SJeff Kirsher * state. 1275adfc5217SJeff Kirsher */ 127651c1a580SMerav Sicron if (!src_o->check_move(bp, src_o, dest_o, 127751c1a580SMerav Sicron &elem->cmd_data.vlan_mac.u)) { 127851c1a580SMerav Sicron DP(BNX2X_MSG_SP, "MOVE command is not allowed considering current registry state\n"); 1279adfc5217SJeff Kirsher return -EINVAL; 1280adfc5217SJeff Kirsher } 1281adfc5217SJeff Kirsher 128216a5fd92SYuval Mintz /* Check if there is an already pending DEL or MOVE command for the 1283adfc5217SJeff Kirsher * source object or ADD command for a destination object. Return an 1284adfc5217SJeff Kirsher * error if so. 1285adfc5217SJeff Kirsher */ 1286adfc5217SJeff Kirsher memcpy(&query_elem, elem, sizeof(query_elem)); 1287adfc5217SJeff Kirsher 1288adfc5217SJeff Kirsher /* Check DEL on source */ 1289adfc5217SJeff Kirsher query_elem.cmd_data.vlan_mac.cmd = BNX2X_VLAN_MAC_DEL; 1290adfc5217SJeff Kirsher if (src_exeq->get(src_exeq, &query_elem)) { 129151c1a580SMerav Sicron BNX2X_ERR("There is a pending DEL command on the source queue already\n"); 1292adfc5217SJeff Kirsher return -EINVAL; 1293adfc5217SJeff Kirsher } 1294adfc5217SJeff Kirsher 1295adfc5217SJeff Kirsher /* Check MOVE on source */ 1296adfc5217SJeff Kirsher if (src_exeq->get(src_exeq, elem)) { 1297adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "There is a pending MOVE command already\n"); 1298adfc5217SJeff Kirsher return -EEXIST; 1299adfc5217SJeff Kirsher } 1300adfc5217SJeff Kirsher 1301adfc5217SJeff Kirsher /* Check ADD on destination */ 1302adfc5217SJeff Kirsher query_elem.cmd_data.vlan_mac.cmd = BNX2X_VLAN_MAC_ADD; 1303adfc5217SJeff Kirsher if (dest_exeq->get(dest_exeq, &query_elem)) { 130451c1a580SMerav Sicron BNX2X_ERR("There is a pending ADD command on the destination queue already\n"); 1305adfc5217SJeff Kirsher return -EINVAL; 1306adfc5217SJeff Kirsher } 1307adfc5217SJeff Kirsher 1308adfc5217SJeff Kirsher /* Consume the credit if not requested not to */ 1309adfc5217SJeff Kirsher if (!(test_bit(BNX2X_DONT_CONSUME_CAM_CREDIT_DEST, 1310adfc5217SJeff Kirsher &elem->cmd_data.vlan_mac.vlan_mac_flags) || 1311adfc5217SJeff Kirsher dest_o->get_credit(dest_o))) 1312adfc5217SJeff Kirsher return -EINVAL; 1313adfc5217SJeff Kirsher 1314adfc5217SJeff Kirsher if (!(test_bit(BNX2X_DONT_CONSUME_CAM_CREDIT, 1315adfc5217SJeff Kirsher &elem->cmd_data.vlan_mac.vlan_mac_flags) || 1316adfc5217SJeff Kirsher src_o->put_credit(src_o))) { 1317adfc5217SJeff Kirsher /* return the credit taken from dest... */ 1318adfc5217SJeff Kirsher dest_o->put_credit(dest_o); 1319adfc5217SJeff Kirsher return -EINVAL; 1320adfc5217SJeff Kirsher } 1321adfc5217SJeff Kirsher 1322adfc5217SJeff Kirsher return 0; 1323adfc5217SJeff Kirsher } 1324adfc5217SJeff Kirsher 1325adfc5217SJeff Kirsher static int bnx2x_validate_vlan_mac(struct bnx2x *bp, 1326adfc5217SJeff Kirsher union bnx2x_qable_obj *qo, 1327adfc5217SJeff Kirsher struct bnx2x_exeq_elem *elem) 1328adfc5217SJeff Kirsher { 1329adfc5217SJeff Kirsher switch (elem->cmd_data.vlan_mac.cmd) { 1330adfc5217SJeff Kirsher case BNX2X_VLAN_MAC_ADD: 1331adfc5217SJeff Kirsher return bnx2x_validate_vlan_mac_add(bp, qo, elem); 1332adfc5217SJeff Kirsher case BNX2X_VLAN_MAC_DEL: 1333adfc5217SJeff Kirsher return bnx2x_validate_vlan_mac_del(bp, qo, elem); 1334adfc5217SJeff Kirsher case BNX2X_VLAN_MAC_MOVE: 1335adfc5217SJeff Kirsher return bnx2x_validate_vlan_mac_move(bp, qo, elem); 1336adfc5217SJeff Kirsher default: 1337adfc5217SJeff Kirsher return -EINVAL; 1338adfc5217SJeff Kirsher } 1339adfc5217SJeff Kirsher } 1340adfc5217SJeff Kirsher 1341460a25cdSYuval Mintz static int bnx2x_remove_vlan_mac(struct bnx2x *bp, 1342460a25cdSYuval Mintz union bnx2x_qable_obj *qo, 1343460a25cdSYuval Mintz struct bnx2x_exeq_elem *elem) 1344460a25cdSYuval Mintz { 1345460a25cdSYuval Mintz int rc = 0; 1346460a25cdSYuval Mintz 1347460a25cdSYuval Mintz /* If consumption wasn't required, nothing to do */ 1348460a25cdSYuval Mintz if (test_bit(BNX2X_DONT_CONSUME_CAM_CREDIT, 1349460a25cdSYuval Mintz &elem->cmd_data.vlan_mac.vlan_mac_flags)) 1350460a25cdSYuval Mintz return 0; 1351460a25cdSYuval Mintz 1352460a25cdSYuval Mintz switch (elem->cmd_data.vlan_mac.cmd) { 1353460a25cdSYuval Mintz case BNX2X_VLAN_MAC_ADD: 1354460a25cdSYuval Mintz case BNX2X_VLAN_MAC_MOVE: 1355460a25cdSYuval Mintz rc = qo->vlan_mac.put_credit(&qo->vlan_mac); 1356460a25cdSYuval Mintz break; 1357460a25cdSYuval Mintz case BNX2X_VLAN_MAC_DEL: 1358460a25cdSYuval Mintz rc = qo->vlan_mac.get_credit(&qo->vlan_mac); 1359460a25cdSYuval Mintz break; 1360460a25cdSYuval Mintz default: 1361460a25cdSYuval Mintz return -EINVAL; 1362460a25cdSYuval Mintz } 1363460a25cdSYuval Mintz 1364460a25cdSYuval Mintz if (rc != true) 1365460a25cdSYuval Mintz return -EINVAL; 1366460a25cdSYuval Mintz 1367460a25cdSYuval Mintz return 0; 1368460a25cdSYuval Mintz } 1369460a25cdSYuval Mintz 1370adfc5217SJeff Kirsher /** 137116a5fd92SYuval Mintz * bnx2x_wait_vlan_mac - passively wait for 5 seconds until all work completes. 1372adfc5217SJeff Kirsher * 1373adfc5217SJeff Kirsher * @bp: device handle 1374adfc5217SJeff Kirsher * @o: bnx2x_vlan_mac_obj 1375adfc5217SJeff Kirsher * 1376adfc5217SJeff Kirsher */ 1377adfc5217SJeff Kirsher static int bnx2x_wait_vlan_mac(struct bnx2x *bp, 1378adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *o) 1379adfc5217SJeff Kirsher { 1380adfc5217SJeff Kirsher int cnt = 5000, rc; 1381adfc5217SJeff Kirsher struct bnx2x_exe_queue_obj *exeq = &o->exe_queue; 1382adfc5217SJeff Kirsher struct bnx2x_raw_obj *raw = &o->raw; 1383adfc5217SJeff Kirsher 1384adfc5217SJeff Kirsher while (cnt--) { 1385adfc5217SJeff Kirsher /* Wait for the current command to complete */ 1386adfc5217SJeff Kirsher rc = raw->wait_comp(bp, raw); 1387adfc5217SJeff Kirsher if (rc) 1388adfc5217SJeff Kirsher return rc; 1389adfc5217SJeff Kirsher 1390adfc5217SJeff Kirsher /* Wait until there are no pending commands */ 1391adfc5217SJeff Kirsher if (!bnx2x_exe_queue_empty(exeq)) 13920926d499SYuval Mintz usleep_range(1000, 2000); 1393adfc5217SJeff Kirsher else 1394adfc5217SJeff Kirsher return 0; 1395adfc5217SJeff Kirsher } 1396adfc5217SJeff Kirsher 1397adfc5217SJeff Kirsher return -EBUSY; 1398adfc5217SJeff Kirsher } 1399adfc5217SJeff Kirsher 1400adfc5217SJeff Kirsher /** 1401adfc5217SJeff Kirsher * bnx2x_complete_vlan_mac - complete one VLAN-MAC ramrod 1402adfc5217SJeff Kirsher * 1403adfc5217SJeff Kirsher * @bp: device handle 1404adfc5217SJeff Kirsher * @o: bnx2x_vlan_mac_obj 1405adfc5217SJeff Kirsher * @cqe: 1406adfc5217SJeff Kirsher * @cont: if true schedule next execution chunk 1407adfc5217SJeff Kirsher * 1408adfc5217SJeff Kirsher */ 1409adfc5217SJeff Kirsher static int bnx2x_complete_vlan_mac(struct bnx2x *bp, 1410adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *o, 1411adfc5217SJeff Kirsher union event_ring_elem *cqe, 1412adfc5217SJeff Kirsher unsigned long *ramrod_flags) 1413adfc5217SJeff Kirsher { 1414adfc5217SJeff Kirsher struct bnx2x_raw_obj *r = &o->raw; 1415adfc5217SJeff Kirsher int rc; 1416adfc5217SJeff Kirsher 1417adfc5217SJeff Kirsher /* Reset pending list */ 1418adfc5217SJeff Kirsher bnx2x_exe_queue_reset_pending(bp, &o->exe_queue); 1419adfc5217SJeff Kirsher 1420adfc5217SJeff Kirsher /* Clear pending */ 1421adfc5217SJeff Kirsher r->clear_pending(r); 1422adfc5217SJeff Kirsher 1423adfc5217SJeff Kirsher /* If ramrod failed this is most likely a SW bug */ 1424adfc5217SJeff Kirsher if (cqe->message.error) 1425adfc5217SJeff Kirsher return -EINVAL; 1426adfc5217SJeff Kirsher 14272de67439SYuval Mintz /* Run the next bulk of pending commands if requested */ 1428adfc5217SJeff Kirsher if (test_bit(RAMROD_CONT, ramrod_flags)) { 1429adfc5217SJeff Kirsher rc = bnx2x_exe_queue_step(bp, &o->exe_queue, ramrod_flags); 1430adfc5217SJeff Kirsher if (rc < 0) 1431adfc5217SJeff Kirsher return rc; 1432adfc5217SJeff Kirsher } 1433adfc5217SJeff Kirsher 1434adfc5217SJeff Kirsher /* If there is more work to do return PENDING */ 1435adfc5217SJeff Kirsher if (!bnx2x_exe_queue_empty(&o->exe_queue)) 1436adfc5217SJeff Kirsher return 1; 1437adfc5217SJeff Kirsher 1438adfc5217SJeff Kirsher return 0; 1439adfc5217SJeff Kirsher } 1440adfc5217SJeff Kirsher 1441adfc5217SJeff Kirsher /** 1442adfc5217SJeff Kirsher * bnx2x_optimize_vlan_mac - optimize ADD and DEL commands. 1443adfc5217SJeff Kirsher * 1444adfc5217SJeff Kirsher * @bp: device handle 1445adfc5217SJeff Kirsher * @o: bnx2x_qable_obj 1446adfc5217SJeff Kirsher * @elem: bnx2x_exeq_elem 1447adfc5217SJeff Kirsher */ 1448adfc5217SJeff Kirsher static int bnx2x_optimize_vlan_mac(struct bnx2x *bp, 1449adfc5217SJeff Kirsher union bnx2x_qable_obj *qo, 1450adfc5217SJeff Kirsher struct bnx2x_exeq_elem *elem) 1451adfc5217SJeff Kirsher { 1452adfc5217SJeff Kirsher struct bnx2x_exeq_elem query, *pos; 1453adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *o = &qo->vlan_mac; 1454adfc5217SJeff Kirsher struct bnx2x_exe_queue_obj *exeq = &o->exe_queue; 1455adfc5217SJeff Kirsher 1456adfc5217SJeff Kirsher memcpy(&query, elem, sizeof(query)); 1457adfc5217SJeff Kirsher 1458adfc5217SJeff Kirsher switch (elem->cmd_data.vlan_mac.cmd) { 1459adfc5217SJeff Kirsher case BNX2X_VLAN_MAC_ADD: 1460adfc5217SJeff Kirsher query.cmd_data.vlan_mac.cmd = BNX2X_VLAN_MAC_DEL; 1461adfc5217SJeff Kirsher break; 1462adfc5217SJeff Kirsher case BNX2X_VLAN_MAC_DEL: 1463adfc5217SJeff Kirsher query.cmd_data.vlan_mac.cmd = BNX2X_VLAN_MAC_ADD; 1464adfc5217SJeff Kirsher break; 1465adfc5217SJeff Kirsher default: 1466adfc5217SJeff Kirsher /* Don't handle anything other than ADD or DEL */ 1467adfc5217SJeff Kirsher return 0; 1468adfc5217SJeff Kirsher } 1469adfc5217SJeff Kirsher 1470adfc5217SJeff Kirsher /* If we found the appropriate element - delete it */ 1471adfc5217SJeff Kirsher pos = exeq->get(exeq, &query); 1472adfc5217SJeff Kirsher if (pos) { 1473adfc5217SJeff Kirsher 1474adfc5217SJeff Kirsher /* Return the credit of the optimized command */ 1475adfc5217SJeff Kirsher if (!test_bit(BNX2X_DONT_CONSUME_CAM_CREDIT, 1476adfc5217SJeff Kirsher &pos->cmd_data.vlan_mac.vlan_mac_flags)) { 1477adfc5217SJeff Kirsher if ((query.cmd_data.vlan_mac.cmd == 1478adfc5217SJeff Kirsher BNX2X_VLAN_MAC_ADD) && !o->put_credit(o)) { 147951c1a580SMerav Sicron BNX2X_ERR("Failed to return the credit for the optimized ADD command\n"); 1480adfc5217SJeff Kirsher return -EINVAL; 1481adfc5217SJeff Kirsher } else if (!o->get_credit(o)) { /* VLAN_MAC_DEL */ 148251c1a580SMerav Sicron BNX2X_ERR("Failed to recover the credit from the optimized DEL command\n"); 1483adfc5217SJeff Kirsher return -EINVAL; 1484adfc5217SJeff Kirsher } 1485adfc5217SJeff Kirsher } 1486adfc5217SJeff Kirsher 1487adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "Optimizing %s command\n", 1488adfc5217SJeff Kirsher (elem->cmd_data.vlan_mac.cmd == BNX2X_VLAN_MAC_ADD) ? 1489adfc5217SJeff Kirsher "ADD" : "DEL"); 1490adfc5217SJeff Kirsher 1491adfc5217SJeff Kirsher list_del(&pos->link); 1492adfc5217SJeff Kirsher bnx2x_exe_queue_free_elem(bp, pos); 1493adfc5217SJeff Kirsher return 1; 1494adfc5217SJeff Kirsher } 1495adfc5217SJeff Kirsher 1496adfc5217SJeff Kirsher return 0; 1497adfc5217SJeff Kirsher } 1498adfc5217SJeff Kirsher 1499adfc5217SJeff Kirsher /** 1500adfc5217SJeff Kirsher * bnx2x_vlan_mac_get_registry_elem - prepare a registry element 1501adfc5217SJeff Kirsher * 1502adfc5217SJeff Kirsher * @bp: device handle 1503adfc5217SJeff Kirsher * @o: 1504adfc5217SJeff Kirsher * @elem: 1505adfc5217SJeff Kirsher * @restore: 1506adfc5217SJeff Kirsher * @re: 1507adfc5217SJeff Kirsher * 1508adfc5217SJeff Kirsher * prepare a registry element according to the current command request. 1509adfc5217SJeff Kirsher */ 1510adfc5217SJeff Kirsher static inline int bnx2x_vlan_mac_get_registry_elem( 1511adfc5217SJeff Kirsher struct bnx2x *bp, 1512adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *o, 1513adfc5217SJeff Kirsher struct bnx2x_exeq_elem *elem, 1514adfc5217SJeff Kirsher bool restore, 1515adfc5217SJeff Kirsher struct bnx2x_vlan_mac_registry_elem **re) 1516adfc5217SJeff Kirsher { 151786564c3fSYuval Mintz enum bnx2x_vlan_mac_cmd cmd = elem->cmd_data.vlan_mac.cmd; 1518adfc5217SJeff Kirsher struct bnx2x_vlan_mac_registry_elem *reg_elem; 1519adfc5217SJeff Kirsher 1520adfc5217SJeff Kirsher /* Allocate a new registry element if needed. */ 1521adfc5217SJeff Kirsher if (!restore && 1522adfc5217SJeff Kirsher ((cmd == BNX2X_VLAN_MAC_ADD) || (cmd == BNX2X_VLAN_MAC_MOVE))) { 1523adfc5217SJeff Kirsher reg_elem = kzalloc(sizeof(*reg_elem), GFP_ATOMIC); 1524adfc5217SJeff Kirsher if (!reg_elem) 1525adfc5217SJeff Kirsher return -ENOMEM; 1526adfc5217SJeff Kirsher 1527adfc5217SJeff Kirsher /* Get a new CAM offset */ 1528adfc5217SJeff Kirsher if (!o->get_cam_offset(o, ®_elem->cam_offset)) { 152916a5fd92SYuval Mintz /* This shall never happen, because we have checked the 153016a5fd92SYuval Mintz * CAM availability in the 'validate'. 1531adfc5217SJeff Kirsher */ 1532adfc5217SJeff Kirsher WARN_ON(1); 1533adfc5217SJeff Kirsher kfree(reg_elem); 1534adfc5217SJeff Kirsher return -EINVAL; 1535adfc5217SJeff Kirsher } 1536adfc5217SJeff Kirsher 1537adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "Got cam offset %d\n", reg_elem->cam_offset); 1538adfc5217SJeff Kirsher 1539adfc5217SJeff Kirsher /* Set a VLAN-MAC data */ 1540adfc5217SJeff Kirsher memcpy(®_elem->u, &elem->cmd_data.vlan_mac.u, 1541adfc5217SJeff Kirsher sizeof(reg_elem->u)); 1542adfc5217SJeff Kirsher 1543adfc5217SJeff Kirsher /* Copy the flags (needed for DEL and RESTORE flows) */ 1544adfc5217SJeff Kirsher reg_elem->vlan_mac_flags = 1545adfc5217SJeff Kirsher elem->cmd_data.vlan_mac.vlan_mac_flags; 1546adfc5217SJeff Kirsher } else /* DEL, RESTORE */ 154751c1a580SMerav Sicron reg_elem = o->check_del(bp, o, &elem->cmd_data.vlan_mac.u); 1548adfc5217SJeff Kirsher 1549adfc5217SJeff Kirsher *re = reg_elem; 1550adfc5217SJeff Kirsher return 0; 1551adfc5217SJeff Kirsher } 1552adfc5217SJeff Kirsher 1553adfc5217SJeff Kirsher /** 1554adfc5217SJeff Kirsher * bnx2x_execute_vlan_mac - execute vlan mac command 1555adfc5217SJeff Kirsher * 1556adfc5217SJeff Kirsher * @bp: device handle 1557adfc5217SJeff Kirsher * @qo: 1558adfc5217SJeff Kirsher * @exe_chunk: 1559adfc5217SJeff Kirsher * @ramrod_flags: 1560adfc5217SJeff Kirsher * 1561adfc5217SJeff Kirsher * go and send a ramrod! 1562adfc5217SJeff Kirsher */ 1563adfc5217SJeff Kirsher static int bnx2x_execute_vlan_mac(struct bnx2x *bp, 1564adfc5217SJeff Kirsher union bnx2x_qable_obj *qo, 1565adfc5217SJeff Kirsher struct list_head *exe_chunk, 1566adfc5217SJeff Kirsher unsigned long *ramrod_flags) 1567adfc5217SJeff Kirsher { 1568adfc5217SJeff Kirsher struct bnx2x_exeq_elem *elem; 1569adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *o = &qo->vlan_mac, *cam_obj; 1570adfc5217SJeff Kirsher struct bnx2x_raw_obj *r = &o->raw; 1571adfc5217SJeff Kirsher int rc, idx = 0; 1572adfc5217SJeff Kirsher bool restore = test_bit(RAMROD_RESTORE, ramrod_flags); 1573adfc5217SJeff Kirsher bool drv_only = test_bit(RAMROD_DRV_CLR_ONLY, ramrod_flags); 1574adfc5217SJeff Kirsher struct bnx2x_vlan_mac_registry_elem *reg_elem; 157586564c3fSYuval Mintz enum bnx2x_vlan_mac_cmd cmd; 1576adfc5217SJeff Kirsher 157716a5fd92SYuval Mintz /* If DRIVER_ONLY execution is requested, cleanup a registry 1578adfc5217SJeff Kirsher * and exit. Otherwise send a ramrod to FW. 1579adfc5217SJeff Kirsher */ 1580adfc5217SJeff Kirsher if (!drv_only) { 1581adfc5217SJeff Kirsher WARN_ON(r->check_pending(r)); 1582adfc5217SJeff Kirsher 1583adfc5217SJeff Kirsher /* Set pending */ 1584adfc5217SJeff Kirsher r->set_pending(r); 1585adfc5217SJeff Kirsher 158616a5fd92SYuval Mintz /* Fill the ramrod data */ 1587adfc5217SJeff Kirsher list_for_each_entry(elem, exe_chunk, link) { 1588adfc5217SJeff Kirsher cmd = elem->cmd_data.vlan_mac.cmd; 158916a5fd92SYuval Mintz /* We will add to the target object in MOVE command, so 1590adfc5217SJeff Kirsher * change the object for a CAM search. 1591adfc5217SJeff Kirsher */ 1592adfc5217SJeff Kirsher if (cmd == BNX2X_VLAN_MAC_MOVE) 1593adfc5217SJeff Kirsher cam_obj = elem->cmd_data.vlan_mac.target_obj; 1594adfc5217SJeff Kirsher else 1595adfc5217SJeff Kirsher cam_obj = o; 1596adfc5217SJeff Kirsher 1597adfc5217SJeff Kirsher rc = bnx2x_vlan_mac_get_registry_elem(bp, cam_obj, 1598adfc5217SJeff Kirsher elem, restore, 1599adfc5217SJeff Kirsher ®_elem); 1600adfc5217SJeff Kirsher if (rc) 1601adfc5217SJeff Kirsher goto error_exit; 1602adfc5217SJeff Kirsher 1603adfc5217SJeff Kirsher WARN_ON(!reg_elem); 1604adfc5217SJeff Kirsher 1605adfc5217SJeff Kirsher /* Push a new entry into the registry */ 1606adfc5217SJeff Kirsher if (!restore && 1607adfc5217SJeff Kirsher ((cmd == BNX2X_VLAN_MAC_ADD) || 1608adfc5217SJeff Kirsher (cmd == BNX2X_VLAN_MAC_MOVE))) 1609adfc5217SJeff Kirsher list_add(®_elem->link, &cam_obj->head); 1610adfc5217SJeff Kirsher 1611adfc5217SJeff Kirsher /* Configure a single command in a ramrod data buffer */ 1612adfc5217SJeff Kirsher o->set_one_rule(bp, o, elem, idx, 1613adfc5217SJeff Kirsher reg_elem->cam_offset); 1614adfc5217SJeff Kirsher 1615adfc5217SJeff Kirsher /* MOVE command consumes 2 entries in the ramrod data */ 1616adfc5217SJeff Kirsher if (cmd == BNX2X_VLAN_MAC_MOVE) 1617adfc5217SJeff Kirsher idx += 2; 1618adfc5217SJeff Kirsher else 1619adfc5217SJeff Kirsher idx++; 1620adfc5217SJeff Kirsher } 1621adfc5217SJeff Kirsher 162216a5fd92SYuval Mintz /* No need for an explicit memory barrier here as long we would 1623adfc5217SJeff Kirsher * need to ensure the ordering of writing to the SPQ element 1624adfc5217SJeff Kirsher * and updating of the SPQ producer which involves a memory 1625adfc5217SJeff Kirsher * read and we will have to put a full memory barrier there 1626adfc5217SJeff Kirsher * (inside bnx2x_sp_post()). 1627adfc5217SJeff Kirsher */ 1628adfc5217SJeff Kirsher 1629adfc5217SJeff Kirsher rc = bnx2x_sp_post(bp, o->ramrod_cmd, r->cid, 1630adfc5217SJeff Kirsher U64_HI(r->rdata_mapping), 1631adfc5217SJeff Kirsher U64_LO(r->rdata_mapping), 1632adfc5217SJeff Kirsher ETH_CONNECTION_TYPE); 1633adfc5217SJeff Kirsher if (rc) 1634adfc5217SJeff Kirsher goto error_exit; 1635adfc5217SJeff Kirsher } 1636adfc5217SJeff Kirsher 1637adfc5217SJeff Kirsher /* Now, when we are done with the ramrod - clean up the registry */ 1638adfc5217SJeff Kirsher list_for_each_entry(elem, exe_chunk, link) { 1639adfc5217SJeff Kirsher cmd = elem->cmd_data.vlan_mac.cmd; 1640adfc5217SJeff Kirsher if ((cmd == BNX2X_VLAN_MAC_DEL) || 1641adfc5217SJeff Kirsher (cmd == BNX2X_VLAN_MAC_MOVE)) { 164251c1a580SMerav Sicron reg_elem = o->check_del(bp, o, 164351c1a580SMerav Sicron &elem->cmd_data.vlan_mac.u); 1644adfc5217SJeff Kirsher 1645adfc5217SJeff Kirsher WARN_ON(!reg_elem); 1646adfc5217SJeff Kirsher 1647adfc5217SJeff Kirsher o->put_cam_offset(o, reg_elem->cam_offset); 1648adfc5217SJeff Kirsher list_del(®_elem->link); 1649adfc5217SJeff Kirsher kfree(reg_elem); 1650adfc5217SJeff Kirsher } 1651adfc5217SJeff Kirsher } 1652adfc5217SJeff Kirsher 1653adfc5217SJeff Kirsher if (!drv_only) 1654adfc5217SJeff Kirsher return 1; 1655adfc5217SJeff Kirsher else 1656adfc5217SJeff Kirsher return 0; 1657adfc5217SJeff Kirsher 1658adfc5217SJeff Kirsher error_exit: 1659adfc5217SJeff Kirsher r->clear_pending(r); 1660adfc5217SJeff Kirsher 1661adfc5217SJeff Kirsher /* Cleanup a registry in case of a failure */ 1662adfc5217SJeff Kirsher list_for_each_entry(elem, exe_chunk, link) { 1663adfc5217SJeff Kirsher cmd = elem->cmd_data.vlan_mac.cmd; 1664adfc5217SJeff Kirsher 1665adfc5217SJeff Kirsher if (cmd == BNX2X_VLAN_MAC_MOVE) 1666adfc5217SJeff Kirsher cam_obj = elem->cmd_data.vlan_mac.target_obj; 1667adfc5217SJeff Kirsher else 1668adfc5217SJeff Kirsher cam_obj = o; 1669adfc5217SJeff Kirsher 1670adfc5217SJeff Kirsher /* Delete all newly added above entries */ 1671adfc5217SJeff Kirsher if (!restore && 1672adfc5217SJeff Kirsher ((cmd == BNX2X_VLAN_MAC_ADD) || 1673adfc5217SJeff Kirsher (cmd == BNX2X_VLAN_MAC_MOVE))) { 167451c1a580SMerav Sicron reg_elem = o->check_del(bp, cam_obj, 1675adfc5217SJeff Kirsher &elem->cmd_data.vlan_mac.u); 1676adfc5217SJeff Kirsher if (reg_elem) { 1677adfc5217SJeff Kirsher list_del(®_elem->link); 1678adfc5217SJeff Kirsher kfree(reg_elem); 1679adfc5217SJeff Kirsher } 1680adfc5217SJeff Kirsher } 1681adfc5217SJeff Kirsher } 1682adfc5217SJeff Kirsher 1683adfc5217SJeff Kirsher return rc; 1684adfc5217SJeff Kirsher } 1685adfc5217SJeff Kirsher 1686adfc5217SJeff Kirsher static inline int bnx2x_vlan_mac_push_new_cmd( 1687adfc5217SJeff Kirsher struct bnx2x *bp, 1688adfc5217SJeff Kirsher struct bnx2x_vlan_mac_ramrod_params *p) 1689adfc5217SJeff Kirsher { 1690adfc5217SJeff Kirsher struct bnx2x_exeq_elem *elem; 1691adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *o = p->vlan_mac_obj; 1692adfc5217SJeff Kirsher bool restore = test_bit(RAMROD_RESTORE, &p->ramrod_flags); 1693adfc5217SJeff Kirsher 1694adfc5217SJeff Kirsher /* Allocate the execution queue element */ 1695adfc5217SJeff Kirsher elem = bnx2x_exe_queue_alloc_elem(bp); 1696adfc5217SJeff Kirsher if (!elem) 1697adfc5217SJeff Kirsher return -ENOMEM; 1698adfc5217SJeff Kirsher 1699adfc5217SJeff Kirsher /* Set the command 'length' */ 1700adfc5217SJeff Kirsher switch (p->user_req.cmd) { 1701adfc5217SJeff Kirsher case BNX2X_VLAN_MAC_MOVE: 1702adfc5217SJeff Kirsher elem->cmd_len = 2; 1703adfc5217SJeff Kirsher break; 1704adfc5217SJeff Kirsher default: 1705adfc5217SJeff Kirsher elem->cmd_len = 1; 1706adfc5217SJeff Kirsher } 1707adfc5217SJeff Kirsher 1708adfc5217SJeff Kirsher /* Fill the object specific info */ 1709adfc5217SJeff Kirsher memcpy(&elem->cmd_data.vlan_mac, &p->user_req, sizeof(p->user_req)); 1710adfc5217SJeff Kirsher 1711adfc5217SJeff Kirsher /* Try to add a new command to the pending list */ 1712adfc5217SJeff Kirsher return bnx2x_exe_queue_add(bp, &o->exe_queue, elem, restore); 1713adfc5217SJeff Kirsher } 1714adfc5217SJeff Kirsher 1715adfc5217SJeff Kirsher /** 1716adfc5217SJeff Kirsher * bnx2x_config_vlan_mac - configure VLAN/MAC/VLAN_MAC filtering rules. 1717adfc5217SJeff Kirsher * 1718adfc5217SJeff Kirsher * @bp: device handle 1719adfc5217SJeff Kirsher * @p: 1720adfc5217SJeff Kirsher * 1721adfc5217SJeff Kirsher */ 1722adfc5217SJeff Kirsher int bnx2x_config_vlan_mac( 1723adfc5217SJeff Kirsher struct bnx2x *bp, 1724adfc5217SJeff Kirsher struct bnx2x_vlan_mac_ramrod_params *p) 1725adfc5217SJeff Kirsher { 1726adfc5217SJeff Kirsher int rc = 0; 1727adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *o = p->vlan_mac_obj; 1728adfc5217SJeff Kirsher unsigned long *ramrod_flags = &p->ramrod_flags; 1729adfc5217SJeff Kirsher bool cont = test_bit(RAMROD_CONT, ramrod_flags); 1730adfc5217SJeff Kirsher struct bnx2x_raw_obj *raw = &o->raw; 1731adfc5217SJeff Kirsher 1732adfc5217SJeff Kirsher /* 1733adfc5217SJeff Kirsher * Add new elements to the execution list for commands that require it. 1734adfc5217SJeff Kirsher */ 1735adfc5217SJeff Kirsher if (!cont) { 1736adfc5217SJeff Kirsher rc = bnx2x_vlan_mac_push_new_cmd(bp, p); 1737adfc5217SJeff Kirsher if (rc) 1738adfc5217SJeff Kirsher return rc; 1739adfc5217SJeff Kirsher } 1740adfc5217SJeff Kirsher 174116a5fd92SYuval Mintz /* If nothing will be executed further in this iteration we want to 1742adfc5217SJeff Kirsher * return PENDING if there are pending commands 1743adfc5217SJeff Kirsher */ 1744adfc5217SJeff Kirsher if (!bnx2x_exe_queue_empty(&o->exe_queue)) 1745adfc5217SJeff Kirsher rc = 1; 1746adfc5217SJeff Kirsher 1747adfc5217SJeff Kirsher if (test_bit(RAMROD_DRV_CLR_ONLY, ramrod_flags)) { 174851c1a580SMerav Sicron DP(BNX2X_MSG_SP, "RAMROD_DRV_CLR_ONLY requested: clearing a pending bit.\n"); 1749adfc5217SJeff Kirsher raw->clear_pending(raw); 1750adfc5217SJeff Kirsher } 1751adfc5217SJeff Kirsher 1752adfc5217SJeff Kirsher /* Execute commands if required */ 1753adfc5217SJeff Kirsher if (cont || test_bit(RAMROD_EXEC, ramrod_flags) || 1754adfc5217SJeff Kirsher test_bit(RAMROD_COMP_WAIT, ramrod_flags)) { 1755adfc5217SJeff Kirsher rc = bnx2x_exe_queue_step(bp, &o->exe_queue, ramrod_flags); 1756adfc5217SJeff Kirsher if (rc < 0) 1757adfc5217SJeff Kirsher return rc; 1758adfc5217SJeff Kirsher } 1759adfc5217SJeff Kirsher 176016a5fd92SYuval Mintz /* RAMROD_COMP_WAIT is a superset of RAMROD_EXEC. If it was set 1761adfc5217SJeff Kirsher * then user want to wait until the last command is done. 1762adfc5217SJeff Kirsher */ 1763adfc5217SJeff Kirsher if (test_bit(RAMROD_COMP_WAIT, &p->ramrod_flags)) { 176416a5fd92SYuval Mintz /* Wait maximum for the current exe_queue length iterations plus 1765adfc5217SJeff Kirsher * one (for the current pending command). 1766adfc5217SJeff Kirsher */ 1767adfc5217SJeff Kirsher int max_iterations = bnx2x_exe_queue_length(&o->exe_queue) + 1; 1768adfc5217SJeff Kirsher 1769adfc5217SJeff Kirsher while (!bnx2x_exe_queue_empty(&o->exe_queue) && 1770adfc5217SJeff Kirsher max_iterations--) { 1771adfc5217SJeff Kirsher 1772adfc5217SJeff Kirsher /* Wait for the current command to complete */ 1773adfc5217SJeff Kirsher rc = raw->wait_comp(bp, raw); 1774adfc5217SJeff Kirsher if (rc) 1775adfc5217SJeff Kirsher return rc; 1776adfc5217SJeff Kirsher 1777adfc5217SJeff Kirsher /* Make a next step */ 1778adfc5217SJeff Kirsher rc = bnx2x_exe_queue_step(bp, &o->exe_queue, 1779adfc5217SJeff Kirsher ramrod_flags); 1780adfc5217SJeff Kirsher if (rc < 0) 1781adfc5217SJeff Kirsher return rc; 1782adfc5217SJeff Kirsher } 1783adfc5217SJeff Kirsher 1784adfc5217SJeff Kirsher return 0; 1785adfc5217SJeff Kirsher } 1786adfc5217SJeff Kirsher 1787adfc5217SJeff Kirsher return rc; 1788adfc5217SJeff Kirsher } 1789adfc5217SJeff Kirsher 1790adfc5217SJeff Kirsher /** 1791adfc5217SJeff Kirsher * bnx2x_vlan_mac_del_all - delete elements with given vlan_mac_flags spec 1792adfc5217SJeff Kirsher * 1793adfc5217SJeff Kirsher * @bp: device handle 1794adfc5217SJeff Kirsher * @o: 1795adfc5217SJeff Kirsher * @vlan_mac_flags: 1796adfc5217SJeff Kirsher * @ramrod_flags: execution flags to be used for this deletion 1797adfc5217SJeff Kirsher * 1798adfc5217SJeff Kirsher * if the last operation has completed successfully and there are no 1799adfc5217SJeff Kirsher * more elements left, positive value if the last operation has completed 1800adfc5217SJeff Kirsher * successfully and there are more previously configured elements, negative 1801adfc5217SJeff Kirsher * value is current operation has failed. 1802adfc5217SJeff Kirsher */ 1803adfc5217SJeff Kirsher static int bnx2x_vlan_mac_del_all(struct bnx2x *bp, 1804adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *o, 1805adfc5217SJeff Kirsher unsigned long *vlan_mac_flags, 1806adfc5217SJeff Kirsher unsigned long *ramrod_flags) 1807adfc5217SJeff Kirsher { 1808adfc5217SJeff Kirsher struct bnx2x_vlan_mac_registry_elem *pos = NULL; 1809adfc5217SJeff Kirsher int rc = 0; 1810adfc5217SJeff Kirsher struct bnx2x_vlan_mac_ramrod_params p; 1811adfc5217SJeff Kirsher struct bnx2x_exe_queue_obj *exeq = &o->exe_queue; 1812adfc5217SJeff Kirsher struct bnx2x_exeq_elem *exeq_pos, *exeq_pos_n; 1813adfc5217SJeff Kirsher 1814adfc5217SJeff Kirsher /* Clear pending commands first */ 1815adfc5217SJeff Kirsher 1816adfc5217SJeff Kirsher spin_lock_bh(&exeq->lock); 1817adfc5217SJeff Kirsher 1818adfc5217SJeff Kirsher list_for_each_entry_safe(exeq_pos, exeq_pos_n, &exeq->exe_queue, link) { 1819adfc5217SJeff Kirsher if (exeq_pos->cmd_data.vlan_mac.vlan_mac_flags == 1820460a25cdSYuval Mintz *vlan_mac_flags) { 1821460a25cdSYuval Mintz rc = exeq->remove(bp, exeq->owner, exeq_pos); 1822460a25cdSYuval Mintz if (rc) { 1823460a25cdSYuval Mintz BNX2X_ERR("Failed to remove command\n"); 1824a44acd55SDan Carpenter spin_unlock_bh(&exeq->lock); 1825460a25cdSYuval Mintz return rc; 1826460a25cdSYuval Mintz } 1827adfc5217SJeff Kirsher list_del(&exeq_pos->link); 182807ef7becSYuval Mintz bnx2x_exe_queue_free_elem(bp, exeq_pos); 1829adfc5217SJeff Kirsher } 1830460a25cdSYuval Mintz } 1831adfc5217SJeff Kirsher 1832adfc5217SJeff Kirsher spin_unlock_bh(&exeq->lock); 1833adfc5217SJeff Kirsher 1834adfc5217SJeff Kirsher /* Prepare a command request */ 1835adfc5217SJeff Kirsher memset(&p, 0, sizeof(p)); 1836adfc5217SJeff Kirsher p.vlan_mac_obj = o; 1837adfc5217SJeff Kirsher p.ramrod_flags = *ramrod_flags; 1838adfc5217SJeff Kirsher p.user_req.cmd = BNX2X_VLAN_MAC_DEL; 1839adfc5217SJeff Kirsher 184016a5fd92SYuval Mintz /* Add all but the last VLAN-MAC to the execution queue without actually 1841adfc5217SJeff Kirsher * execution anything. 1842adfc5217SJeff Kirsher */ 1843adfc5217SJeff Kirsher __clear_bit(RAMROD_COMP_WAIT, &p.ramrod_flags); 1844adfc5217SJeff Kirsher __clear_bit(RAMROD_EXEC, &p.ramrod_flags); 1845adfc5217SJeff Kirsher __clear_bit(RAMROD_CONT, &p.ramrod_flags); 1846adfc5217SJeff Kirsher 1847adfc5217SJeff Kirsher list_for_each_entry(pos, &o->head, link) { 1848adfc5217SJeff Kirsher if (pos->vlan_mac_flags == *vlan_mac_flags) { 1849adfc5217SJeff Kirsher p.user_req.vlan_mac_flags = pos->vlan_mac_flags; 1850adfc5217SJeff Kirsher memcpy(&p.user_req.u, &pos->u, sizeof(pos->u)); 1851adfc5217SJeff Kirsher rc = bnx2x_config_vlan_mac(bp, &p); 1852adfc5217SJeff Kirsher if (rc < 0) { 1853adfc5217SJeff Kirsher BNX2X_ERR("Failed to add a new DEL command\n"); 1854adfc5217SJeff Kirsher return rc; 1855adfc5217SJeff Kirsher } 1856adfc5217SJeff Kirsher } 1857adfc5217SJeff Kirsher } 1858adfc5217SJeff Kirsher 1859adfc5217SJeff Kirsher p.ramrod_flags = *ramrod_flags; 1860adfc5217SJeff Kirsher __set_bit(RAMROD_CONT, &p.ramrod_flags); 1861adfc5217SJeff Kirsher 1862adfc5217SJeff Kirsher return bnx2x_config_vlan_mac(bp, &p); 1863adfc5217SJeff Kirsher } 1864adfc5217SJeff Kirsher 1865adfc5217SJeff Kirsher static inline void bnx2x_init_raw_obj(struct bnx2x_raw_obj *raw, u8 cl_id, 1866adfc5217SJeff Kirsher u32 cid, u8 func_id, void *rdata, dma_addr_t rdata_mapping, int state, 1867adfc5217SJeff Kirsher unsigned long *pstate, bnx2x_obj_type type) 1868adfc5217SJeff Kirsher { 1869adfc5217SJeff Kirsher raw->func_id = func_id; 1870adfc5217SJeff Kirsher raw->cid = cid; 1871adfc5217SJeff Kirsher raw->cl_id = cl_id; 1872adfc5217SJeff Kirsher raw->rdata = rdata; 1873adfc5217SJeff Kirsher raw->rdata_mapping = rdata_mapping; 1874adfc5217SJeff Kirsher raw->state = state; 1875adfc5217SJeff Kirsher raw->pstate = pstate; 1876adfc5217SJeff Kirsher raw->obj_type = type; 1877adfc5217SJeff Kirsher raw->check_pending = bnx2x_raw_check_pending; 1878adfc5217SJeff Kirsher raw->clear_pending = bnx2x_raw_clear_pending; 1879adfc5217SJeff Kirsher raw->set_pending = bnx2x_raw_set_pending; 1880adfc5217SJeff Kirsher raw->wait_comp = bnx2x_raw_wait; 1881adfc5217SJeff Kirsher } 1882adfc5217SJeff Kirsher 1883adfc5217SJeff Kirsher static inline void bnx2x_init_vlan_mac_common(struct bnx2x_vlan_mac_obj *o, 1884adfc5217SJeff Kirsher u8 cl_id, u32 cid, u8 func_id, void *rdata, dma_addr_t rdata_mapping, 1885adfc5217SJeff Kirsher int state, unsigned long *pstate, bnx2x_obj_type type, 1886adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *macs_pool, 1887adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *vlans_pool) 1888adfc5217SJeff Kirsher { 1889adfc5217SJeff Kirsher INIT_LIST_HEAD(&o->head); 1890adfc5217SJeff Kirsher 1891adfc5217SJeff Kirsher o->macs_pool = macs_pool; 1892adfc5217SJeff Kirsher o->vlans_pool = vlans_pool; 1893adfc5217SJeff Kirsher 1894adfc5217SJeff Kirsher o->delete_all = bnx2x_vlan_mac_del_all; 1895adfc5217SJeff Kirsher o->restore = bnx2x_vlan_mac_restore; 1896adfc5217SJeff Kirsher o->complete = bnx2x_complete_vlan_mac; 1897adfc5217SJeff Kirsher o->wait = bnx2x_wait_vlan_mac; 1898adfc5217SJeff Kirsher 1899adfc5217SJeff Kirsher bnx2x_init_raw_obj(&o->raw, cl_id, cid, func_id, rdata, rdata_mapping, 1900adfc5217SJeff Kirsher state, pstate, type); 1901adfc5217SJeff Kirsher } 1902adfc5217SJeff Kirsher 1903adfc5217SJeff Kirsher void bnx2x_init_mac_obj(struct bnx2x *bp, 1904adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *mac_obj, 1905adfc5217SJeff Kirsher u8 cl_id, u32 cid, u8 func_id, void *rdata, 1906adfc5217SJeff Kirsher dma_addr_t rdata_mapping, int state, 1907adfc5217SJeff Kirsher unsigned long *pstate, bnx2x_obj_type type, 1908adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *macs_pool) 1909adfc5217SJeff Kirsher { 1910adfc5217SJeff Kirsher union bnx2x_qable_obj *qable_obj = (union bnx2x_qable_obj *)mac_obj; 1911adfc5217SJeff Kirsher 1912adfc5217SJeff Kirsher bnx2x_init_vlan_mac_common(mac_obj, cl_id, cid, func_id, rdata, 1913adfc5217SJeff Kirsher rdata_mapping, state, pstate, type, 1914adfc5217SJeff Kirsher macs_pool, NULL); 1915adfc5217SJeff Kirsher 1916adfc5217SJeff Kirsher /* CAM credit pool handling */ 1917adfc5217SJeff Kirsher mac_obj->get_credit = bnx2x_get_credit_mac; 1918adfc5217SJeff Kirsher mac_obj->put_credit = bnx2x_put_credit_mac; 1919adfc5217SJeff Kirsher mac_obj->get_cam_offset = bnx2x_get_cam_offset_mac; 1920adfc5217SJeff Kirsher mac_obj->put_cam_offset = bnx2x_put_cam_offset_mac; 1921adfc5217SJeff Kirsher 1922adfc5217SJeff Kirsher if (CHIP_IS_E1x(bp)) { 1923adfc5217SJeff Kirsher mac_obj->set_one_rule = bnx2x_set_one_mac_e1x; 1924adfc5217SJeff Kirsher mac_obj->check_del = bnx2x_check_mac_del; 1925adfc5217SJeff Kirsher mac_obj->check_add = bnx2x_check_mac_add; 1926adfc5217SJeff Kirsher mac_obj->check_move = bnx2x_check_move_always_err; 1927adfc5217SJeff Kirsher mac_obj->ramrod_cmd = RAMROD_CMD_ID_ETH_SET_MAC; 1928adfc5217SJeff Kirsher 1929adfc5217SJeff Kirsher /* Exe Queue */ 1930adfc5217SJeff Kirsher bnx2x_exe_queue_init(bp, 1931adfc5217SJeff Kirsher &mac_obj->exe_queue, 1, qable_obj, 1932adfc5217SJeff Kirsher bnx2x_validate_vlan_mac, 1933460a25cdSYuval Mintz bnx2x_remove_vlan_mac, 1934adfc5217SJeff Kirsher bnx2x_optimize_vlan_mac, 1935adfc5217SJeff Kirsher bnx2x_execute_vlan_mac, 1936adfc5217SJeff Kirsher bnx2x_exeq_get_mac); 1937adfc5217SJeff Kirsher } else { 1938adfc5217SJeff Kirsher mac_obj->set_one_rule = bnx2x_set_one_mac_e2; 1939adfc5217SJeff Kirsher mac_obj->check_del = bnx2x_check_mac_del; 1940adfc5217SJeff Kirsher mac_obj->check_add = bnx2x_check_mac_add; 1941adfc5217SJeff Kirsher mac_obj->check_move = bnx2x_check_move; 1942adfc5217SJeff Kirsher mac_obj->ramrod_cmd = 1943adfc5217SJeff Kirsher RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES; 1944ed5162a0SAriel Elior mac_obj->get_n_elements = bnx2x_get_n_elements; 1945adfc5217SJeff Kirsher 1946adfc5217SJeff Kirsher /* Exe Queue */ 1947adfc5217SJeff Kirsher bnx2x_exe_queue_init(bp, 1948adfc5217SJeff Kirsher &mac_obj->exe_queue, CLASSIFY_RULES_COUNT, 1949adfc5217SJeff Kirsher qable_obj, bnx2x_validate_vlan_mac, 1950460a25cdSYuval Mintz bnx2x_remove_vlan_mac, 1951adfc5217SJeff Kirsher bnx2x_optimize_vlan_mac, 1952adfc5217SJeff Kirsher bnx2x_execute_vlan_mac, 1953adfc5217SJeff Kirsher bnx2x_exeq_get_mac); 1954adfc5217SJeff Kirsher } 1955adfc5217SJeff Kirsher } 1956adfc5217SJeff Kirsher 1957adfc5217SJeff Kirsher void bnx2x_init_vlan_obj(struct bnx2x *bp, 1958adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *vlan_obj, 1959adfc5217SJeff Kirsher u8 cl_id, u32 cid, u8 func_id, void *rdata, 1960adfc5217SJeff Kirsher dma_addr_t rdata_mapping, int state, 1961adfc5217SJeff Kirsher unsigned long *pstate, bnx2x_obj_type type, 1962adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *vlans_pool) 1963adfc5217SJeff Kirsher { 1964adfc5217SJeff Kirsher union bnx2x_qable_obj *qable_obj = (union bnx2x_qable_obj *)vlan_obj; 1965adfc5217SJeff Kirsher 1966adfc5217SJeff Kirsher bnx2x_init_vlan_mac_common(vlan_obj, cl_id, cid, func_id, rdata, 1967adfc5217SJeff Kirsher rdata_mapping, state, pstate, type, NULL, 1968adfc5217SJeff Kirsher vlans_pool); 1969adfc5217SJeff Kirsher 1970adfc5217SJeff Kirsher vlan_obj->get_credit = bnx2x_get_credit_vlan; 1971adfc5217SJeff Kirsher vlan_obj->put_credit = bnx2x_put_credit_vlan; 1972adfc5217SJeff Kirsher vlan_obj->get_cam_offset = bnx2x_get_cam_offset_vlan; 1973adfc5217SJeff Kirsher vlan_obj->put_cam_offset = bnx2x_put_cam_offset_vlan; 1974adfc5217SJeff Kirsher 1975adfc5217SJeff Kirsher if (CHIP_IS_E1x(bp)) { 1976adfc5217SJeff Kirsher BNX2X_ERR("Do not support chips others than E2 and newer\n"); 1977adfc5217SJeff Kirsher BUG(); 1978adfc5217SJeff Kirsher } else { 1979adfc5217SJeff Kirsher vlan_obj->set_one_rule = bnx2x_set_one_vlan_e2; 1980adfc5217SJeff Kirsher vlan_obj->check_del = bnx2x_check_vlan_del; 1981adfc5217SJeff Kirsher vlan_obj->check_add = bnx2x_check_vlan_add; 1982adfc5217SJeff Kirsher vlan_obj->check_move = bnx2x_check_move; 1983adfc5217SJeff Kirsher vlan_obj->ramrod_cmd = 1984adfc5217SJeff Kirsher RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES; 19853ec9f9caSAriel Elior vlan_obj->get_n_elements = bnx2x_get_n_elements; 1986adfc5217SJeff Kirsher 1987adfc5217SJeff Kirsher /* Exe Queue */ 1988adfc5217SJeff Kirsher bnx2x_exe_queue_init(bp, 1989adfc5217SJeff Kirsher &vlan_obj->exe_queue, CLASSIFY_RULES_COUNT, 1990adfc5217SJeff Kirsher qable_obj, bnx2x_validate_vlan_mac, 1991460a25cdSYuval Mintz bnx2x_remove_vlan_mac, 1992adfc5217SJeff Kirsher bnx2x_optimize_vlan_mac, 1993adfc5217SJeff Kirsher bnx2x_execute_vlan_mac, 1994adfc5217SJeff Kirsher bnx2x_exeq_get_vlan); 1995adfc5217SJeff Kirsher } 1996adfc5217SJeff Kirsher } 1997adfc5217SJeff Kirsher 1998adfc5217SJeff Kirsher void bnx2x_init_vlan_mac_obj(struct bnx2x *bp, 1999adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *vlan_mac_obj, 2000adfc5217SJeff Kirsher u8 cl_id, u32 cid, u8 func_id, void *rdata, 2001adfc5217SJeff Kirsher dma_addr_t rdata_mapping, int state, 2002adfc5217SJeff Kirsher unsigned long *pstate, bnx2x_obj_type type, 2003adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *macs_pool, 2004adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *vlans_pool) 2005adfc5217SJeff Kirsher { 2006adfc5217SJeff Kirsher union bnx2x_qable_obj *qable_obj = 2007adfc5217SJeff Kirsher (union bnx2x_qable_obj *)vlan_mac_obj; 2008adfc5217SJeff Kirsher 2009adfc5217SJeff Kirsher bnx2x_init_vlan_mac_common(vlan_mac_obj, cl_id, cid, func_id, rdata, 2010adfc5217SJeff Kirsher rdata_mapping, state, pstate, type, 2011adfc5217SJeff Kirsher macs_pool, vlans_pool); 2012adfc5217SJeff Kirsher 2013adfc5217SJeff Kirsher /* CAM pool handling */ 2014adfc5217SJeff Kirsher vlan_mac_obj->get_credit = bnx2x_get_credit_vlan_mac; 2015adfc5217SJeff Kirsher vlan_mac_obj->put_credit = bnx2x_put_credit_vlan_mac; 201616a5fd92SYuval Mintz /* CAM offset is relevant for 57710 and 57711 chips only which have a 2017adfc5217SJeff Kirsher * single CAM for both MACs and VLAN-MAC pairs. So the offset 2018adfc5217SJeff Kirsher * will be taken from MACs' pool object only. 2019adfc5217SJeff Kirsher */ 2020adfc5217SJeff Kirsher vlan_mac_obj->get_cam_offset = bnx2x_get_cam_offset_mac; 2021adfc5217SJeff Kirsher vlan_mac_obj->put_cam_offset = bnx2x_put_cam_offset_mac; 2022adfc5217SJeff Kirsher 2023adfc5217SJeff Kirsher if (CHIP_IS_E1(bp)) { 2024adfc5217SJeff Kirsher BNX2X_ERR("Do not support chips others than E2\n"); 2025adfc5217SJeff Kirsher BUG(); 2026adfc5217SJeff Kirsher } else if (CHIP_IS_E1H(bp)) { 2027adfc5217SJeff Kirsher vlan_mac_obj->set_one_rule = bnx2x_set_one_vlan_mac_e1h; 2028adfc5217SJeff Kirsher vlan_mac_obj->check_del = bnx2x_check_vlan_mac_del; 2029adfc5217SJeff Kirsher vlan_mac_obj->check_add = bnx2x_check_vlan_mac_add; 2030adfc5217SJeff Kirsher vlan_mac_obj->check_move = bnx2x_check_move_always_err; 2031adfc5217SJeff Kirsher vlan_mac_obj->ramrod_cmd = RAMROD_CMD_ID_ETH_SET_MAC; 2032adfc5217SJeff Kirsher 2033adfc5217SJeff Kirsher /* Exe Queue */ 2034adfc5217SJeff Kirsher bnx2x_exe_queue_init(bp, 2035adfc5217SJeff Kirsher &vlan_mac_obj->exe_queue, 1, qable_obj, 2036adfc5217SJeff Kirsher bnx2x_validate_vlan_mac, 2037460a25cdSYuval Mintz bnx2x_remove_vlan_mac, 2038adfc5217SJeff Kirsher bnx2x_optimize_vlan_mac, 2039adfc5217SJeff Kirsher bnx2x_execute_vlan_mac, 2040adfc5217SJeff Kirsher bnx2x_exeq_get_vlan_mac); 2041adfc5217SJeff Kirsher } else { 2042adfc5217SJeff Kirsher vlan_mac_obj->set_one_rule = bnx2x_set_one_vlan_mac_e2; 2043adfc5217SJeff Kirsher vlan_mac_obj->check_del = bnx2x_check_vlan_mac_del; 2044adfc5217SJeff Kirsher vlan_mac_obj->check_add = bnx2x_check_vlan_mac_add; 2045adfc5217SJeff Kirsher vlan_mac_obj->check_move = bnx2x_check_move; 2046adfc5217SJeff Kirsher vlan_mac_obj->ramrod_cmd = 2047adfc5217SJeff Kirsher RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES; 2048adfc5217SJeff Kirsher 2049adfc5217SJeff Kirsher /* Exe Queue */ 2050adfc5217SJeff Kirsher bnx2x_exe_queue_init(bp, 2051adfc5217SJeff Kirsher &vlan_mac_obj->exe_queue, 2052adfc5217SJeff Kirsher CLASSIFY_RULES_COUNT, 2053adfc5217SJeff Kirsher qable_obj, bnx2x_validate_vlan_mac, 2054460a25cdSYuval Mintz bnx2x_remove_vlan_mac, 2055adfc5217SJeff Kirsher bnx2x_optimize_vlan_mac, 2056adfc5217SJeff Kirsher bnx2x_execute_vlan_mac, 2057adfc5217SJeff Kirsher bnx2x_exeq_get_vlan_mac); 2058adfc5217SJeff Kirsher } 2059adfc5217SJeff Kirsher } 2060adfc5217SJeff Kirsher 2061adfc5217SJeff Kirsher /* RX_MODE verbs: DROP_ALL/ACCEPT_ALL/ACCEPT_ALL_MULTI/ACCEPT_ALL_VLAN/NORMAL */ 2062adfc5217SJeff Kirsher static inline void __storm_memset_mac_filters(struct bnx2x *bp, 2063adfc5217SJeff Kirsher struct tstorm_eth_mac_filter_config *mac_filters, 2064adfc5217SJeff Kirsher u16 pf_id) 2065adfc5217SJeff Kirsher { 2066adfc5217SJeff Kirsher size_t size = sizeof(struct tstorm_eth_mac_filter_config); 2067adfc5217SJeff Kirsher 2068adfc5217SJeff Kirsher u32 addr = BAR_TSTRORM_INTMEM + 2069adfc5217SJeff Kirsher TSTORM_MAC_FILTER_CONFIG_OFFSET(pf_id); 2070adfc5217SJeff Kirsher 2071adfc5217SJeff Kirsher __storm_memset_struct(bp, addr, size, (u32 *)mac_filters); 2072adfc5217SJeff Kirsher } 2073adfc5217SJeff Kirsher 2074adfc5217SJeff Kirsher static int bnx2x_set_rx_mode_e1x(struct bnx2x *bp, 2075adfc5217SJeff Kirsher struct bnx2x_rx_mode_ramrod_params *p) 2076adfc5217SJeff Kirsher { 2077adfc5217SJeff Kirsher /* update the bp MAC filter structure */ 2078adfc5217SJeff Kirsher u32 mask = (1 << p->cl_id); 2079adfc5217SJeff Kirsher 2080adfc5217SJeff Kirsher struct tstorm_eth_mac_filter_config *mac_filters = 2081adfc5217SJeff Kirsher (struct tstorm_eth_mac_filter_config *)p->rdata; 2082adfc5217SJeff Kirsher 208316a5fd92SYuval Mintz /* initial setting is drop-all */ 2084adfc5217SJeff Kirsher u8 drop_all_ucast = 1, drop_all_mcast = 1; 2085adfc5217SJeff Kirsher u8 accp_all_ucast = 0, accp_all_bcast = 0, accp_all_mcast = 0; 2086adfc5217SJeff Kirsher u8 unmatched_unicast = 0; 2087adfc5217SJeff Kirsher 208816a5fd92SYuval Mintz /* In e1x there we only take into account rx accept flag since tx switching 2089adfc5217SJeff Kirsher * isn't enabled. */ 2090adfc5217SJeff Kirsher if (test_bit(BNX2X_ACCEPT_UNICAST, &p->rx_accept_flags)) 2091adfc5217SJeff Kirsher /* accept matched ucast */ 2092adfc5217SJeff Kirsher drop_all_ucast = 0; 2093adfc5217SJeff Kirsher 2094adfc5217SJeff Kirsher if (test_bit(BNX2X_ACCEPT_MULTICAST, &p->rx_accept_flags)) 2095adfc5217SJeff Kirsher /* accept matched mcast */ 2096adfc5217SJeff Kirsher drop_all_mcast = 0; 2097adfc5217SJeff Kirsher 2098adfc5217SJeff Kirsher if (test_bit(BNX2X_ACCEPT_ALL_UNICAST, &p->rx_accept_flags)) { 2099adfc5217SJeff Kirsher /* accept all mcast */ 2100adfc5217SJeff Kirsher drop_all_ucast = 0; 2101adfc5217SJeff Kirsher accp_all_ucast = 1; 2102adfc5217SJeff Kirsher } 2103adfc5217SJeff Kirsher if (test_bit(BNX2X_ACCEPT_ALL_MULTICAST, &p->rx_accept_flags)) { 2104adfc5217SJeff Kirsher /* accept all mcast */ 2105adfc5217SJeff Kirsher drop_all_mcast = 0; 2106adfc5217SJeff Kirsher accp_all_mcast = 1; 2107adfc5217SJeff Kirsher } 2108adfc5217SJeff Kirsher if (test_bit(BNX2X_ACCEPT_BROADCAST, &p->rx_accept_flags)) 2109adfc5217SJeff Kirsher /* accept (all) bcast */ 2110adfc5217SJeff Kirsher accp_all_bcast = 1; 2111adfc5217SJeff Kirsher if (test_bit(BNX2X_ACCEPT_UNMATCHED, &p->rx_accept_flags)) 2112adfc5217SJeff Kirsher /* accept unmatched unicasts */ 2113adfc5217SJeff Kirsher unmatched_unicast = 1; 2114adfc5217SJeff Kirsher 2115adfc5217SJeff Kirsher mac_filters->ucast_drop_all = drop_all_ucast ? 2116adfc5217SJeff Kirsher mac_filters->ucast_drop_all | mask : 2117adfc5217SJeff Kirsher mac_filters->ucast_drop_all & ~mask; 2118adfc5217SJeff Kirsher 2119adfc5217SJeff Kirsher mac_filters->mcast_drop_all = drop_all_mcast ? 2120adfc5217SJeff Kirsher mac_filters->mcast_drop_all | mask : 2121adfc5217SJeff Kirsher mac_filters->mcast_drop_all & ~mask; 2122adfc5217SJeff Kirsher 2123adfc5217SJeff Kirsher mac_filters->ucast_accept_all = accp_all_ucast ? 2124adfc5217SJeff Kirsher mac_filters->ucast_accept_all | mask : 2125adfc5217SJeff Kirsher mac_filters->ucast_accept_all & ~mask; 2126adfc5217SJeff Kirsher 2127adfc5217SJeff Kirsher mac_filters->mcast_accept_all = accp_all_mcast ? 2128adfc5217SJeff Kirsher mac_filters->mcast_accept_all | mask : 2129adfc5217SJeff Kirsher mac_filters->mcast_accept_all & ~mask; 2130adfc5217SJeff Kirsher 2131adfc5217SJeff Kirsher mac_filters->bcast_accept_all = accp_all_bcast ? 2132adfc5217SJeff Kirsher mac_filters->bcast_accept_all | mask : 2133adfc5217SJeff Kirsher mac_filters->bcast_accept_all & ~mask; 2134adfc5217SJeff Kirsher 2135adfc5217SJeff Kirsher mac_filters->unmatched_unicast = unmatched_unicast ? 2136adfc5217SJeff Kirsher mac_filters->unmatched_unicast | mask : 2137adfc5217SJeff Kirsher mac_filters->unmatched_unicast & ~mask; 2138adfc5217SJeff Kirsher 2139adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "drop_ucast 0x%x\ndrop_mcast 0x%x\n accp_ucast 0x%x\n" 2140adfc5217SJeff Kirsher "accp_mcast 0x%x\naccp_bcast 0x%x\n", 214151c1a580SMerav Sicron mac_filters->ucast_drop_all, mac_filters->mcast_drop_all, 214251c1a580SMerav Sicron mac_filters->ucast_accept_all, mac_filters->mcast_accept_all, 2143adfc5217SJeff Kirsher mac_filters->bcast_accept_all); 2144adfc5217SJeff Kirsher 2145adfc5217SJeff Kirsher /* write the MAC filter structure*/ 2146adfc5217SJeff Kirsher __storm_memset_mac_filters(bp, mac_filters, p->func_id); 2147adfc5217SJeff Kirsher 2148adfc5217SJeff Kirsher /* The operation is completed */ 2149adfc5217SJeff Kirsher clear_bit(p->state, p->pstate); 2150adfc5217SJeff Kirsher smp_mb__after_clear_bit(); 2151adfc5217SJeff Kirsher 2152adfc5217SJeff Kirsher return 0; 2153adfc5217SJeff Kirsher } 2154adfc5217SJeff Kirsher 2155adfc5217SJeff Kirsher /* Setup ramrod data */ 2156adfc5217SJeff Kirsher static inline void bnx2x_rx_mode_set_rdata_hdr_e2(u32 cid, 2157adfc5217SJeff Kirsher struct eth_classify_header *hdr, 2158adfc5217SJeff Kirsher u8 rule_cnt) 2159adfc5217SJeff Kirsher { 216086564c3fSYuval Mintz hdr->echo = cpu_to_le32(cid); 2161adfc5217SJeff Kirsher hdr->rule_cnt = rule_cnt; 2162adfc5217SJeff Kirsher } 2163adfc5217SJeff Kirsher 2164adfc5217SJeff Kirsher static inline void bnx2x_rx_mode_set_cmd_state_e2(struct bnx2x *bp, 2165924d75abSYuval Mintz unsigned long *accept_flags, 2166adfc5217SJeff Kirsher struct eth_filter_rules_cmd *cmd, 2167adfc5217SJeff Kirsher bool clear_accept_all) 2168adfc5217SJeff Kirsher { 2169adfc5217SJeff Kirsher u16 state; 2170adfc5217SJeff Kirsher 2171adfc5217SJeff Kirsher /* start with 'drop-all' */ 2172adfc5217SJeff Kirsher state = ETH_FILTER_RULES_CMD_UCAST_DROP_ALL | 2173adfc5217SJeff Kirsher ETH_FILTER_RULES_CMD_MCAST_DROP_ALL; 2174adfc5217SJeff Kirsher 2175924d75abSYuval Mintz if (test_bit(BNX2X_ACCEPT_UNICAST, accept_flags)) 2176adfc5217SJeff Kirsher state &= ~ETH_FILTER_RULES_CMD_UCAST_DROP_ALL; 2177adfc5217SJeff Kirsher 2178924d75abSYuval Mintz if (test_bit(BNX2X_ACCEPT_MULTICAST, accept_flags)) 2179adfc5217SJeff Kirsher state &= ~ETH_FILTER_RULES_CMD_MCAST_DROP_ALL; 2180adfc5217SJeff Kirsher 2181924d75abSYuval Mintz if (test_bit(BNX2X_ACCEPT_ALL_UNICAST, accept_flags)) { 2182adfc5217SJeff Kirsher state &= ~ETH_FILTER_RULES_CMD_UCAST_DROP_ALL; 2183adfc5217SJeff Kirsher state |= ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL; 2184adfc5217SJeff Kirsher } 2185adfc5217SJeff Kirsher 2186924d75abSYuval Mintz if (test_bit(BNX2X_ACCEPT_ALL_MULTICAST, accept_flags)) { 2187adfc5217SJeff Kirsher state |= ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL; 2188adfc5217SJeff Kirsher state &= ~ETH_FILTER_RULES_CMD_MCAST_DROP_ALL; 2189adfc5217SJeff Kirsher } 2190924d75abSYuval Mintz 2191924d75abSYuval Mintz if (test_bit(BNX2X_ACCEPT_BROADCAST, accept_flags)) 2192adfc5217SJeff Kirsher state |= ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL; 2193adfc5217SJeff Kirsher 2194924d75abSYuval Mintz if (test_bit(BNX2X_ACCEPT_UNMATCHED, accept_flags)) { 2195adfc5217SJeff Kirsher state &= ~ETH_FILTER_RULES_CMD_UCAST_DROP_ALL; 2196adfc5217SJeff Kirsher state |= ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED; 2197adfc5217SJeff Kirsher } 2198924d75abSYuval Mintz 2199924d75abSYuval Mintz if (test_bit(BNX2X_ACCEPT_ANY_VLAN, accept_flags)) 2200adfc5217SJeff Kirsher state |= ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN; 2201adfc5217SJeff Kirsher 2202adfc5217SJeff Kirsher /* Clear ACCEPT_ALL_XXX flags for FCoE L2 Queue */ 2203adfc5217SJeff Kirsher if (clear_accept_all) { 2204adfc5217SJeff Kirsher state &= ~ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL; 2205adfc5217SJeff Kirsher state &= ~ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL; 2206adfc5217SJeff Kirsher state &= ~ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL; 2207adfc5217SJeff Kirsher state &= ~ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED; 2208adfc5217SJeff Kirsher } 2209adfc5217SJeff Kirsher 2210adfc5217SJeff Kirsher cmd->state = cpu_to_le16(state); 2211adfc5217SJeff Kirsher } 2212adfc5217SJeff Kirsher 2213adfc5217SJeff Kirsher static int bnx2x_set_rx_mode_e2(struct bnx2x *bp, 2214adfc5217SJeff Kirsher struct bnx2x_rx_mode_ramrod_params *p) 2215adfc5217SJeff Kirsher { 2216adfc5217SJeff Kirsher struct eth_filter_rules_ramrod_data *data = p->rdata; 2217adfc5217SJeff Kirsher int rc; 2218adfc5217SJeff Kirsher u8 rule_idx = 0; 2219adfc5217SJeff Kirsher 2220adfc5217SJeff Kirsher /* Reset the ramrod data buffer */ 2221adfc5217SJeff Kirsher memset(data, 0, sizeof(*data)); 2222adfc5217SJeff Kirsher 2223adfc5217SJeff Kirsher /* Setup ramrod data */ 2224adfc5217SJeff Kirsher 2225adfc5217SJeff Kirsher /* Tx (internal switching) */ 2226adfc5217SJeff Kirsher if (test_bit(RAMROD_TX, &p->ramrod_flags)) { 2227adfc5217SJeff Kirsher data->rules[rule_idx].client_id = p->cl_id; 2228adfc5217SJeff Kirsher data->rules[rule_idx].func_id = p->func_id; 2229adfc5217SJeff Kirsher 2230adfc5217SJeff Kirsher data->rules[rule_idx].cmd_general_data = 2231adfc5217SJeff Kirsher ETH_FILTER_RULES_CMD_TX_CMD; 2232adfc5217SJeff Kirsher 2233924d75abSYuval Mintz bnx2x_rx_mode_set_cmd_state_e2(bp, &p->tx_accept_flags, 2234924d75abSYuval Mintz &(data->rules[rule_idx++]), 2235924d75abSYuval Mintz false); 2236adfc5217SJeff Kirsher } 2237adfc5217SJeff Kirsher 2238adfc5217SJeff Kirsher /* Rx */ 2239adfc5217SJeff Kirsher if (test_bit(RAMROD_RX, &p->ramrod_flags)) { 2240adfc5217SJeff Kirsher data->rules[rule_idx].client_id = p->cl_id; 2241adfc5217SJeff Kirsher data->rules[rule_idx].func_id = p->func_id; 2242adfc5217SJeff Kirsher 2243adfc5217SJeff Kirsher data->rules[rule_idx].cmd_general_data = 2244adfc5217SJeff Kirsher ETH_FILTER_RULES_CMD_RX_CMD; 2245adfc5217SJeff Kirsher 2246924d75abSYuval Mintz bnx2x_rx_mode_set_cmd_state_e2(bp, &p->rx_accept_flags, 2247924d75abSYuval Mintz &(data->rules[rule_idx++]), 2248924d75abSYuval Mintz false); 2249adfc5217SJeff Kirsher } 2250adfc5217SJeff Kirsher 225116a5fd92SYuval Mintz /* If FCoE Queue configuration has been requested configure the Rx and 2252adfc5217SJeff Kirsher * internal switching modes for this queue in separate rules. 2253adfc5217SJeff Kirsher * 2254adfc5217SJeff Kirsher * FCoE queue shell never be set to ACCEPT_ALL packets of any sort: 2255adfc5217SJeff Kirsher * MCAST_ALL, UCAST_ALL, BCAST_ALL and UNMATCHED. 2256adfc5217SJeff Kirsher */ 2257adfc5217SJeff Kirsher if (test_bit(BNX2X_RX_MODE_FCOE_ETH, &p->rx_mode_flags)) { 2258adfc5217SJeff Kirsher /* Tx (internal switching) */ 2259adfc5217SJeff Kirsher if (test_bit(RAMROD_TX, &p->ramrod_flags)) { 2260adfc5217SJeff Kirsher data->rules[rule_idx].client_id = bnx2x_fcoe(bp, cl_id); 2261adfc5217SJeff Kirsher data->rules[rule_idx].func_id = p->func_id; 2262adfc5217SJeff Kirsher 2263adfc5217SJeff Kirsher data->rules[rule_idx].cmd_general_data = 2264adfc5217SJeff Kirsher ETH_FILTER_RULES_CMD_TX_CMD; 2265adfc5217SJeff Kirsher 2266924d75abSYuval Mintz bnx2x_rx_mode_set_cmd_state_e2(bp, &p->tx_accept_flags, 2267924d75abSYuval Mintz &(data->rules[rule_idx]), 2268adfc5217SJeff Kirsher true); 2269924d75abSYuval Mintz rule_idx++; 2270adfc5217SJeff Kirsher } 2271adfc5217SJeff Kirsher 2272adfc5217SJeff Kirsher /* Rx */ 2273adfc5217SJeff Kirsher if (test_bit(RAMROD_RX, &p->ramrod_flags)) { 2274adfc5217SJeff Kirsher data->rules[rule_idx].client_id = bnx2x_fcoe(bp, cl_id); 2275adfc5217SJeff Kirsher data->rules[rule_idx].func_id = p->func_id; 2276adfc5217SJeff Kirsher 2277adfc5217SJeff Kirsher data->rules[rule_idx].cmd_general_data = 2278adfc5217SJeff Kirsher ETH_FILTER_RULES_CMD_RX_CMD; 2279adfc5217SJeff Kirsher 2280924d75abSYuval Mintz bnx2x_rx_mode_set_cmd_state_e2(bp, &p->rx_accept_flags, 2281924d75abSYuval Mintz &(data->rules[rule_idx]), 2282adfc5217SJeff Kirsher true); 2283924d75abSYuval Mintz rule_idx++; 2284adfc5217SJeff Kirsher } 2285adfc5217SJeff Kirsher } 2286adfc5217SJeff Kirsher 228716a5fd92SYuval Mintz /* Set the ramrod header (most importantly - number of rules to 2288adfc5217SJeff Kirsher * configure). 2289adfc5217SJeff Kirsher */ 2290adfc5217SJeff Kirsher bnx2x_rx_mode_set_rdata_hdr_e2(p->cid, &data->header, rule_idx); 2291adfc5217SJeff Kirsher 229251c1a580SMerav Sicron DP(BNX2X_MSG_SP, "About to configure %d rules, rx_accept_flags 0x%lx, tx_accept_flags 0x%lx\n", 2293adfc5217SJeff Kirsher data->header.rule_cnt, p->rx_accept_flags, 2294adfc5217SJeff Kirsher p->tx_accept_flags); 2295adfc5217SJeff Kirsher 229616a5fd92SYuval Mintz /* No need for an explicit memory barrier here as long we would 2297adfc5217SJeff Kirsher * need to ensure the ordering of writing to the SPQ element 2298adfc5217SJeff Kirsher * and updating of the SPQ producer which involves a memory 2299adfc5217SJeff Kirsher * read and we will have to put a full memory barrier there 2300adfc5217SJeff Kirsher * (inside bnx2x_sp_post()). 2301adfc5217SJeff Kirsher */ 2302adfc5217SJeff Kirsher 2303adfc5217SJeff Kirsher /* Send a ramrod */ 2304adfc5217SJeff Kirsher rc = bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_FILTER_RULES, p->cid, 2305adfc5217SJeff Kirsher U64_HI(p->rdata_mapping), 2306adfc5217SJeff Kirsher U64_LO(p->rdata_mapping), 2307adfc5217SJeff Kirsher ETH_CONNECTION_TYPE); 2308adfc5217SJeff Kirsher if (rc) 2309adfc5217SJeff Kirsher return rc; 2310adfc5217SJeff Kirsher 2311adfc5217SJeff Kirsher /* Ramrod completion is pending */ 2312adfc5217SJeff Kirsher return 1; 2313adfc5217SJeff Kirsher } 2314adfc5217SJeff Kirsher 2315adfc5217SJeff Kirsher static int bnx2x_wait_rx_mode_comp_e2(struct bnx2x *bp, 2316adfc5217SJeff Kirsher struct bnx2x_rx_mode_ramrod_params *p) 2317adfc5217SJeff Kirsher { 2318adfc5217SJeff Kirsher return bnx2x_state_wait(bp, p->state, p->pstate); 2319adfc5217SJeff Kirsher } 2320adfc5217SJeff Kirsher 2321adfc5217SJeff Kirsher static int bnx2x_empty_rx_mode_wait(struct bnx2x *bp, 2322adfc5217SJeff Kirsher struct bnx2x_rx_mode_ramrod_params *p) 2323adfc5217SJeff Kirsher { 2324adfc5217SJeff Kirsher /* Do nothing */ 2325adfc5217SJeff Kirsher return 0; 2326adfc5217SJeff Kirsher } 2327adfc5217SJeff Kirsher 2328adfc5217SJeff Kirsher int bnx2x_config_rx_mode(struct bnx2x *bp, 2329adfc5217SJeff Kirsher struct bnx2x_rx_mode_ramrod_params *p) 2330adfc5217SJeff Kirsher { 2331adfc5217SJeff Kirsher int rc; 2332adfc5217SJeff Kirsher 2333adfc5217SJeff Kirsher /* Configure the new classification in the chip */ 2334adfc5217SJeff Kirsher rc = p->rx_mode_obj->config_rx_mode(bp, p); 2335adfc5217SJeff Kirsher if (rc < 0) 2336adfc5217SJeff Kirsher return rc; 2337adfc5217SJeff Kirsher 2338adfc5217SJeff Kirsher /* Wait for a ramrod completion if was requested */ 2339adfc5217SJeff Kirsher if (test_bit(RAMROD_COMP_WAIT, &p->ramrod_flags)) { 2340adfc5217SJeff Kirsher rc = p->rx_mode_obj->wait_comp(bp, p); 2341adfc5217SJeff Kirsher if (rc) 2342adfc5217SJeff Kirsher return rc; 2343adfc5217SJeff Kirsher } 2344adfc5217SJeff Kirsher 2345adfc5217SJeff Kirsher return rc; 2346adfc5217SJeff Kirsher } 2347adfc5217SJeff Kirsher 2348adfc5217SJeff Kirsher void bnx2x_init_rx_mode_obj(struct bnx2x *bp, 2349adfc5217SJeff Kirsher struct bnx2x_rx_mode_obj *o) 2350adfc5217SJeff Kirsher { 2351adfc5217SJeff Kirsher if (CHIP_IS_E1x(bp)) { 2352adfc5217SJeff Kirsher o->wait_comp = bnx2x_empty_rx_mode_wait; 2353adfc5217SJeff Kirsher o->config_rx_mode = bnx2x_set_rx_mode_e1x; 2354adfc5217SJeff Kirsher } else { 2355adfc5217SJeff Kirsher o->wait_comp = bnx2x_wait_rx_mode_comp_e2; 2356adfc5217SJeff Kirsher o->config_rx_mode = bnx2x_set_rx_mode_e2; 2357adfc5217SJeff Kirsher } 2358adfc5217SJeff Kirsher } 2359adfc5217SJeff Kirsher 2360adfc5217SJeff Kirsher /********************* Multicast verbs: SET, CLEAR ****************************/ 2361adfc5217SJeff Kirsher static inline u8 bnx2x_mcast_bin_from_mac(u8 *mac) 2362adfc5217SJeff Kirsher { 2363adfc5217SJeff Kirsher return (crc32c_le(0, mac, ETH_ALEN) >> 24) & 0xff; 2364adfc5217SJeff Kirsher } 2365adfc5217SJeff Kirsher 2366adfc5217SJeff Kirsher struct bnx2x_mcast_mac_elem { 2367adfc5217SJeff Kirsher struct list_head link; 2368adfc5217SJeff Kirsher u8 mac[ETH_ALEN]; 2369adfc5217SJeff Kirsher u8 pad[2]; /* For a natural alignment of the following buffer */ 2370adfc5217SJeff Kirsher }; 2371adfc5217SJeff Kirsher 2372adfc5217SJeff Kirsher struct bnx2x_pending_mcast_cmd { 2373adfc5217SJeff Kirsher struct list_head link; 2374adfc5217SJeff Kirsher int type; /* BNX2X_MCAST_CMD_X */ 2375adfc5217SJeff Kirsher union { 2376adfc5217SJeff Kirsher struct list_head macs_head; 2377adfc5217SJeff Kirsher u32 macs_num; /* Needed for DEL command */ 2378adfc5217SJeff Kirsher int next_bin; /* Needed for RESTORE flow with aprox match */ 2379adfc5217SJeff Kirsher } data; 2380adfc5217SJeff Kirsher 2381adfc5217SJeff Kirsher bool done; /* set to true, when the command has been handled, 2382adfc5217SJeff Kirsher * practically used in 57712 handling only, where one pending 2383adfc5217SJeff Kirsher * command may be handled in a few operations. As long as for 2384adfc5217SJeff Kirsher * other chips every operation handling is completed in a 2385adfc5217SJeff Kirsher * single ramrod, there is no need to utilize this field. 2386adfc5217SJeff Kirsher */ 2387adfc5217SJeff Kirsher }; 2388adfc5217SJeff Kirsher 2389adfc5217SJeff Kirsher static int bnx2x_mcast_wait(struct bnx2x *bp, 2390adfc5217SJeff Kirsher struct bnx2x_mcast_obj *o) 2391adfc5217SJeff Kirsher { 2392adfc5217SJeff Kirsher if (bnx2x_state_wait(bp, o->sched_state, o->raw.pstate) || 2393adfc5217SJeff Kirsher o->raw.wait_comp(bp, &o->raw)) 2394adfc5217SJeff Kirsher return -EBUSY; 2395adfc5217SJeff Kirsher 2396adfc5217SJeff Kirsher return 0; 2397adfc5217SJeff Kirsher } 2398adfc5217SJeff Kirsher 2399adfc5217SJeff Kirsher static int bnx2x_mcast_enqueue_cmd(struct bnx2x *bp, 2400adfc5217SJeff Kirsher struct bnx2x_mcast_obj *o, 2401adfc5217SJeff Kirsher struct bnx2x_mcast_ramrod_params *p, 240286564c3fSYuval Mintz enum bnx2x_mcast_cmd cmd) 2403adfc5217SJeff Kirsher { 2404adfc5217SJeff Kirsher int total_sz; 2405adfc5217SJeff Kirsher struct bnx2x_pending_mcast_cmd *new_cmd; 2406adfc5217SJeff Kirsher struct bnx2x_mcast_mac_elem *cur_mac = NULL; 2407adfc5217SJeff Kirsher struct bnx2x_mcast_list_elem *pos; 2408adfc5217SJeff Kirsher int macs_list_len = ((cmd == BNX2X_MCAST_CMD_ADD) ? 2409adfc5217SJeff Kirsher p->mcast_list_len : 0); 2410adfc5217SJeff Kirsher 2411adfc5217SJeff Kirsher /* If the command is empty ("handle pending commands only"), break */ 2412adfc5217SJeff Kirsher if (!p->mcast_list_len) 2413adfc5217SJeff Kirsher return 0; 2414adfc5217SJeff Kirsher 2415adfc5217SJeff Kirsher total_sz = sizeof(*new_cmd) + 2416adfc5217SJeff Kirsher macs_list_len * sizeof(struct bnx2x_mcast_mac_elem); 2417adfc5217SJeff Kirsher 2418adfc5217SJeff Kirsher /* Add mcast is called under spin_lock, thus calling with GFP_ATOMIC */ 2419adfc5217SJeff Kirsher new_cmd = kzalloc(total_sz, GFP_ATOMIC); 2420adfc5217SJeff Kirsher 2421adfc5217SJeff Kirsher if (!new_cmd) 2422adfc5217SJeff Kirsher return -ENOMEM; 2423adfc5217SJeff Kirsher 242451c1a580SMerav Sicron DP(BNX2X_MSG_SP, "About to enqueue a new %d command. macs_list_len=%d\n", 242551c1a580SMerav Sicron cmd, macs_list_len); 2426adfc5217SJeff Kirsher 2427adfc5217SJeff Kirsher INIT_LIST_HEAD(&new_cmd->data.macs_head); 2428adfc5217SJeff Kirsher 2429adfc5217SJeff Kirsher new_cmd->type = cmd; 2430adfc5217SJeff Kirsher new_cmd->done = false; 2431adfc5217SJeff Kirsher 2432adfc5217SJeff Kirsher switch (cmd) { 2433adfc5217SJeff Kirsher case BNX2X_MCAST_CMD_ADD: 2434adfc5217SJeff Kirsher cur_mac = (struct bnx2x_mcast_mac_elem *) 2435adfc5217SJeff Kirsher ((u8 *)new_cmd + sizeof(*new_cmd)); 2436adfc5217SJeff Kirsher 243716a5fd92SYuval Mintz /* Push the MACs of the current command into the pending command 2438adfc5217SJeff Kirsher * MACs list: FIFO 2439adfc5217SJeff Kirsher */ 2440adfc5217SJeff Kirsher list_for_each_entry(pos, &p->mcast_list, link) { 2441adfc5217SJeff Kirsher memcpy(cur_mac->mac, pos->mac, ETH_ALEN); 2442adfc5217SJeff Kirsher list_add_tail(&cur_mac->link, &new_cmd->data.macs_head); 2443adfc5217SJeff Kirsher cur_mac++; 2444adfc5217SJeff Kirsher } 2445adfc5217SJeff Kirsher 2446adfc5217SJeff Kirsher break; 2447adfc5217SJeff Kirsher 2448adfc5217SJeff Kirsher case BNX2X_MCAST_CMD_DEL: 2449adfc5217SJeff Kirsher new_cmd->data.macs_num = p->mcast_list_len; 2450adfc5217SJeff Kirsher break; 2451adfc5217SJeff Kirsher 2452adfc5217SJeff Kirsher case BNX2X_MCAST_CMD_RESTORE: 2453adfc5217SJeff Kirsher new_cmd->data.next_bin = 0; 2454adfc5217SJeff Kirsher break; 2455adfc5217SJeff Kirsher 2456adfc5217SJeff Kirsher default: 24578b6d5c09SJesper Juhl kfree(new_cmd); 2458adfc5217SJeff Kirsher BNX2X_ERR("Unknown command: %d\n", cmd); 2459adfc5217SJeff Kirsher return -EINVAL; 2460adfc5217SJeff Kirsher } 2461adfc5217SJeff Kirsher 2462adfc5217SJeff Kirsher /* Push the new pending command to the tail of the pending list: FIFO */ 2463adfc5217SJeff Kirsher list_add_tail(&new_cmd->link, &o->pending_cmds_head); 2464adfc5217SJeff Kirsher 2465adfc5217SJeff Kirsher o->set_sched(o); 2466adfc5217SJeff Kirsher 2467adfc5217SJeff Kirsher return 1; 2468adfc5217SJeff Kirsher } 2469adfc5217SJeff Kirsher 2470adfc5217SJeff Kirsher /** 2471adfc5217SJeff Kirsher * bnx2x_mcast_get_next_bin - get the next set bin (index) 2472adfc5217SJeff Kirsher * 2473adfc5217SJeff Kirsher * @o: 2474adfc5217SJeff Kirsher * @last: index to start looking from (including) 2475adfc5217SJeff Kirsher * 2476adfc5217SJeff Kirsher * returns the next found (set) bin or a negative value if none is found. 2477adfc5217SJeff Kirsher */ 2478adfc5217SJeff Kirsher static inline int bnx2x_mcast_get_next_bin(struct bnx2x_mcast_obj *o, int last) 2479adfc5217SJeff Kirsher { 2480adfc5217SJeff Kirsher int i, j, inner_start = last % BIT_VEC64_ELEM_SZ; 2481adfc5217SJeff Kirsher 2482adfc5217SJeff Kirsher for (i = last / BIT_VEC64_ELEM_SZ; i < BNX2X_MCAST_VEC_SZ; i++) { 2483adfc5217SJeff Kirsher if (o->registry.aprox_match.vec[i]) 2484adfc5217SJeff Kirsher for (j = inner_start; j < BIT_VEC64_ELEM_SZ; j++) { 2485adfc5217SJeff Kirsher int cur_bit = j + BIT_VEC64_ELEM_SZ * i; 2486adfc5217SJeff Kirsher if (BIT_VEC64_TEST_BIT(o->registry.aprox_match. 2487adfc5217SJeff Kirsher vec, cur_bit)) { 2488adfc5217SJeff Kirsher return cur_bit; 2489adfc5217SJeff Kirsher } 2490adfc5217SJeff Kirsher } 2491adfc5217SJeff Kirsher inner_start = 0; 2492adfc5217SJeff Kirsher } 2493adfc5217SJeff Kirsher 2494adfc5217SJeff Kirsher /* None found */ 2495adfc5217SJeff Kirsher return -1; 2496adfc5217SJeff Kirsher } 2497adfc5217SJeff Kirsher 2498adfc5217SJeff Kirsher /** 2499adfc5217SJeff Kirsher * bnx2x_mcast_clear_first_bin - find the first set bin and clear it 2500adfc5217SJeff Kirsher * 2501adfc5217SJeff Kirsher * @o: 2502adfc5217SJeff Kirsher * 2503adfc5217SJeff Kirsher * returns the index of the found bin or -1 if none is found 2504adfc5217SJeff Kirsher */ 2505adfc5217SJeff Kirsher static inline int bnx2x_mcast_clear_first_bin(struct bnx2x_mcast_obj *o) 2506adfc5217SJeff Kirsher { 2507adfc5217SJeff Kirsher int cur_bit = bnx2x_mcast_get_next_bin(o, 0); 2508adfc5217SJeff Kirsher 2509adfc5217SJeff Kirsher if (cur_bit >= 0) 2510adfc5217SJeff Kirsher BIT_VEC64_CLEAR_BIT(o->registry.aprox_match.vec, cur_bit); 2511adfc5217SJeff Kirsher 2512adfc5217SJeff Kirsher return cur_bit; 2513adfc5217SJeff Kirsher } 2514adfc5217SJeff Kirsher 2515adfc5217SJeff Kirsher static inline u8 bnx2x_mcast_get_rx_tx_flag(struct bnx2x_mcast_obj *o) 2516adfc5217SJeff Kirsher { 2517adfc5217SJeff Kirsher struct bnx2x_raw_obj *raw = &o->raw; 2518adfc5217SJeff Kirsher u8 rx_tx_flag = 0; 2519adfc5217SJeff Kirsher 2520adfc5217SJeff Kirsher if ((raw->obj_type == BNX2X_OBJ_TYPE_TX) || 2521adfc5217SJeff Kirsher (raw->obj_type == BNX2X_OBJ_TYPE_RX_TX)) 2522adfc5217SJeff Kirsher rx_tx_flag |= ETH_MULTICAST_RULES_CMD_TX_CMD; 2523adfc5217SJeff Kirsher 2524adfc5217SJeff Kirsher if ((raw->obj_type == BNX2X_OBJ_TYPE_RX) || 2525adfc5217SJeff Kirsher (raw->obj_type == BNX2X_OBJ_TYPE_RX_TX)) 2526adfc5217SJeff Kirsher rx_tx_flag |= ETH_MULTICAST_RULES_CMD_RX_CMD; 2527adfc5217SJeff Kirsher 2528adfc5217SJeff Kirsher return rx_tx_flag; 2529adfc5217SJeff Kirsher } 2530adfc5217SJeff Kirsher 2531adfc5217SJeff Kirsher static void bnx2x_mcast_set_one_rule_e2(struct bnx2x *bp, 2532adfc5217SJeff Kirsher struct bnx2x_mcast_obj *o, int idx, 2533adfc5217SJeff Kirsher union bnx2x_mcast_config_data *cfg_data, 253486564c3fSYuval Mintz enum bnx2x_mcast_cmd cmd) 2535adfc5217SJeff Kirsher { 2536adfc5217SJeff Kirsher struct bnx2x_raw_obj *r = &o->raw; 2537adfc5217SJeff Kirsher struct eth_multicast_rules_ramrod_data *data = 2538adfc5217SJeff Kirsher (struct eth_multicast_rules_ramrod_data *)(r->rdata); 2539adfc5217SJeff Kirsher u8 func_id = r->func_id; 2540adfc5217SJeff Kirsher u8 rx_tx_add_flag = bnx2x_mcast_get_rx_tx_flag(o); 2541adfc5217SJeff Kirsher int bin; 2542adfc5217SJeff Kirsher 2543adfc5217SJeff Kirsher if ((cmd == BNX2X_MCAST_CMD_ADD) || (cmd == BNX2X_MCAST_CMD_RESTORE)) 2544adfc5217SJeff Kirsher rx_tx_add_flag |= ETH_MULTICAST_RULES_CMD_IS_ADD; 2545adfc5217SJeff Kirsher 2546adfc5217SJeff Kirsher data->rules[idx].cmd_general_data |= rx_tx_add_flag; 2547adfc5217SJeff Kirsher 2548adfc5217SJeff Kirsher /* Get a bin and update a bins' vector */ 2549adfc5217SJeff Kirsher switch (cmd) { 2550adfc5217SJeff Kirsher case BNX2X_MCAST_CMD_ADD: 2551adfc5217SJeff Kirsher bin = bnx2x_mcast_bin_from_mac(cfg_data->mac); 2552adfc5217SJeff Kirsher BIT_VEC64_SET_BIT(o->registry.aprox_match.vec, bin); 2553adfc5217SJeff Kirsher break; 2554adfc5217SJeff Kirsher 2555adfc5217SJeff Kirsher case BNX2X_MCAST_CMD_DEL: 2556adfc5217SJeff Kirsher /* If there were no more bins to clear 2557adfc5217SJeff Kirsher * (bnx2x_mcast_clear_first_bin() returns -1) then we would 2558adfc5217SJeff Kirsher * clear any (0xff) bin. 2559adfc5217SJeff Kirsher * See bnx2x_mcast_validate_e2() for explanation when it may 2560adfc5217SJeff Kirsher * happen. 2561adfc5217SJeff Kirsher */ 2562adfc5217SJeff Kirsher bin = bnx2x_mcast_clear_first_bin(o); 2563adfc5217SJeff Kirsher break; 2564adfc5217SJeff Kirsher 2565adfc5217SJeff Kirsher case BNX2X_MCAST_CMD_RESTORE: 2566adfc5217SJeff Kirsher bin = cfg_data->bin; 2567adfc5217SJeff Kirsher break; 2568adfc5217SJeff Kirsher 2569adfc5217SJeff Kirsher default: 2570adfc5217SJeff Kirsher BNX2X_ERR("Unknown command: %d\n", cmd); 2571adfc5217SJeff Kirsher return; 2572adfc5217SJeff Kirsher } 2573adfc5217SJeff Kirsher 2574adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "%s bin %d\n", 2575adfc5217SJeff Kirsher ((rx_tx_add_flag & ETH_MULTICAST_RULES_CMD_IS_ADD) ? 2576adfc5217SJeff Kirsher "Setting" : "Clearing"), bin); 2577adfc5217SJeff Kirsher 2578adfc5217SJeff Kirsher data->rules[idx].bin_id = (u8)bin; 2579adfc5217SJeff Kirsher data->rules[idx].func_id = func_id; 2580adfc5217SJeff Kirsher data->rules[idx].engine_id = o->engine_id; 2581adfc5217SJeff Kirsher } 2582adfc5217SJeff Kirsher 2583adfc5217SJeff Kirsher /** 2584adfc5217SJeff Kirsher * bnx2x_mcast_handle_restore_cmd_e2 - restore configuration from the registry 2585adfc5217SJeff Kirsher * 2586adfc5217SJeff Kirsher * @bp: device handle 2587adfc5217SJeff Kirsher * @o: 2588adfc5217SJeff Kirsher * @start_bin: index in the registry to start from (including) 2589adfc5217SJeff Kirsher * @rdata_idx: index in the ramrod data to start from 2590adfc5217SJeff Kirsher * 2591adfc5217SJeff Kirsher * returns last handled bin index or -1 if all bins have been handled 2592adfc5217SJeff Kirsher */ 2593adfc5217SJeff Kirsher static inline int bnx2x_mcast_handle_restore_cmd_e2( 2594adfc5217SJeff Kirsher struct bnx2x *bp, struct bnx2x_mcast_obj *o , int start_bin, 2595adfc5217SJeff Kirsher int *rdata_idx) 2596adfc5217SJeff Kirsher { 2597adfc5217SJeff Kirsher int cur_bin, cnt = *rdata_idx; 259886564c3fSYuval Mintz union bnx2x_mcast_config_data cfg_data = {NULL}; 2599adfc5217SJeff Kirsher 2600adfc5217SJeff Kirsher /* go through the registry and configure the bins from it */ 2601adfc5217SJeff Kirsher for (cur_bin = bnx2x_mcast_get_next_bin(o, start_bin); cur_bin >= 0; 2602adfc5217SJeff Kirsher cur_bin = bnx2x_mcast_get_next_bin(o, cur_bin + 1)) { 2603adfc5217SJeff Kirsher 2604adfc5217SJeff Kirsher cfg_data.bin = (u8)cur_bin; 2605adfc5217SJeff Kirsher o->set_one_rule(bp, o, cnt, &cfg_data, 2606adfc5217SJeff Kirsher BNX2X_MCAST_CMD_RESTORE); 2607adfc5217SJeff Kirsher 2608adfc5217SJeff Kirsher cnt++; 2609adfc5217SJeff Kirsher 2610adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "About to configure a bin %d\n", cur_bin); 2611adfc5217SJeff Kirsher 2612adfc5217SJeff Kirsher /* Break if we reached the maximum number 2613adfc5217SJeff Kirsher * of rules. 2614adfc5217SJeff Kirsher */ 2615adfc5217SJeff Kirsher if (cnt >= o->max_cmd_len) 2616adfc5217SJeff Kirsher break; 2617adfc5217SJeff Kirsher } 2618adfc5217SJeff Kirsher 2619adfc5217SJeff Kirsher *rdata_idx = cnt; 2620adfc5217SJeff Kirsher 2621adfc5217SJeff Kirsher return cur_bin; 2622adfc5217SJeff Kirsher } 2623adfc5217SJeff Kirsher 2624adfc5217SJeff Kirsher static inline void bnx2x_mcast_hdl_pending_add_e2(struct bnx2x *bp, 2625adfc5217SJeff Kirsher struct bnx2x_mcast_obj *o, struct bnx2x_pending_mcast_cmd *cmd_pos, 2626adfc5217SJeff Kirsher int *line_idx) 2627adfc5217SJeff Kirsher { 2628adfc5217SJeff Kirsher struct bnx2x_mcast_mac_elem *pmac_pos, *pmac_pos_n; 2629adfc5217SJeff Kirsher int cnt = *line_idx; 263086564c3fSYuval Mintz union bnx2x_mcast_config_data cfg_data = {NULL}; 2631adfc5217SJeff Kirsher 2632adfc5217SJeff Kirsher list_for_each_entry_safe(pmac_pos, pmac_pos_n, &cmd_pos->data.macs_head, 2633adfc5217SJeff Kirsher link) { 2634adfc5217SJeff Kirsher 2635adfc5217SJeff Kirsher cfg_data.mac = &pmac_pos->mac[0]; 2636adfc5217SJeff Kirsher o->set_one_rule(bp, o, cnt, &cfg_data, cmd_pos->type); 2637adfc5217SJeff Kirsher 2638adfc5217SJeff Kirsher cnt++; 2639adfc5217SJeff Kirsher 26400f9dad10SJoe Perches DP(BNX2X_MSG_SP, "About to configure %pM mcast MAC\n", 26410f9dad10SJoe Perches pmac_pos->mac); 2642adfc5217SJeff Kirsher 2643adfc5217SJeff Kirsher list_del(&pmac_pos->link); 2644adfc5217SJeff Kirsher 2645adfc5217SJeff Kirsher /* Break if we reached the maximum number 2646adfc5217SJeff Kirsher * of rules. 2647adfc5217SJeff Kirsher */ 2648adfc5217SJeff Kirsher if (cnt >= o->max_cmd_len) 2649adfc5217SJeff Kirsher break; 2650adfc5217SJeff Kirsher } 2651adfc5217SJeff Kirsher 2652adfc5217SJeff Kirsher *line_idx = cnt; 2653adfc5217SJeff Kirsher 2654adfc5217SJeff Kirsher /* if no more MACs to configure - we are done */ 2655adfc5217SJeff Kirsher if (list_empty(&cmd_pos->data.macs_head)) 2656adfc5217SJeff Kirsher cmd_pos->done = true; 2657adfc5217SJeff Kirsher } 2658adfc5217SJeff Kirsher 2659adfc5217SJeff Kirsher static inline void bnx2x_mcast_hdl_pending_del_e2(struct bnx2x *bp, 2660adfc5217SJeff Kirsher struct bnx2x_mcast_obj *o, struct bnx2x_pending_mcast_cmd *cmd_pos, 2661adfc5217SJeff Kirsher int *line_idx) 2662adfc5217SJeff Kirsher { 2663adfc5217SJeff Kirsher int cnt = *line_idx; 2664adfc5217SJeff Kirsher 2665adfc5217SJeff Kirsher while (cmd_pos->data.macs_num) { 2666adfc5217SJeff Kirsher o->set_one_rule(bp, o, cnt, NULL, cmd_pos->type); 2667adfc5217SJeff Kirsher 2668adfc5217SJeff Kirsher cnt++; 2669adfc5217SJeff Kirsher 2670adfc5217SJeff Kirsher cmd_pos->data.macs_num--; 2671adfc5217SJeff Kirsher 2672adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "Deleting MAC. %d left,cnt is %d\n", 2673adfc5217SJeff Kirsher cmd_pos->data.macs_num, cnt); 2674adfc5217SJeff Kirsher 2675adfc5217SJeff Kirsher /* Break if we reached the maximum 2676adfc5217SJeff Kirsher * number of rules. 2677adfc5217SJeff Kirsher */ 2678adfc5217SJeff Kirsher if (cnt >= o->max_cmd_len) 2679adfc5217SJeff Kirsher break; 2680adfc5217SJeff Kirsher } 2681adfc5217SJeff Kirsher 2682adfc5217SJeff Kirsher *line_idx = cnt; 2683adfc5217SJeff Kirsher 2684adfc5217SJeff Kirsher /* If we cleared all bins - we are done */ 2685adfc5217SJeff Kirsher if (!cmd_pos->data.macs_num) 2686adfc5217SJeff Kirsher cmd_pos->done = true; 2687adfc5217SJeff Kirsher } 2688adfc5217SJeff Kirsher 2689adfc5217SJeff Kirsher static inline void bnx2x_mcast_hdl_pending_restore_e2(struct bnx2x *bp, 2690adfc5217SJeff Kirsher struct bnx2x_mcast_obj *o, struct bnx2x_pending_mcast_cmd *cmd_pos, 2691adfc5217SJeff Kirsher int *line_idx) 2692adfc5217SJeff Kirsher { 2693adfc5217SJeff Kirsher cmd_pos->data.next_bin = o->hdl_restore(bp, o, cmd_pos->data.next_bin, 2694adfc5217SJeff Kirsher line_idx); 2695adfc5217SJeff Kirsher 2696adfc5217SJeff Kirsher if (cmd_pos->data.next_bin < 0) 2697adfc5217SJeff Kirsher /* If o->set_restore returned -1 we are done */ 2698adfc5217SJeff Kirsher cmd_pos->done = true; 2699adfc5217SJeff Kirsher else 2700adfc5217SJeff Kirsher /* Start from the next bin next time */ 2701adfc5217SJeff Kirsher cmd_pos->data.next_bin++; 2702adfc5217SJeff Kirsher } 2703adfc5217SJeff Kirsher 2704adfc5217SJeff Kirsher static inline int bnx2x_mcast_handle_pending_cmds_e2(struct bnx2x *bp, 2705adfc5217SJeff Kirsher struct bnx2x_mcast_ramrod_params *p) 2706adfc5217SJeff Kirsher { 2707adfc5217SJeff Kirsher struct bnx2x_pending_mcast_cmd *cmd_pos, *cmd_pos_n; 2708adfc5217SJeff Kirsher int cnt = 0; 2709adfc5217SJeff Kirsher struct bnx2x_mcast_obj *o = p->mcast_obj; 2710adfc5217SJeff Kirsher 2711adfc5217SJeff Kirsher list_for_each_entry_safe(cmd_pos, cmd_pos_n, &o->pending_cmds_head, 2712adfc5217SJeff Kirsher link) { 2713adfc5217SJeff Kirsher switch (cmd_pos->type) { 2714adfc5217SJeff Kirsher case BNX2X_MCAST_CMD_ADD: 2715adfc5217SJeff Kirsher bnx2x_mcast_hdl_pending_add_e2(bp, o, cmd_pos, &cnt); 2716adfc5217SJeff Kirsher break; 2717adfc5217SJeff Kirsher 2718adfc5217SJeff Kirsher case BNX2X_MCAST_CMD_DEL: 2719adfc5217SJeff Kirsher bnx2x_mcast_hdl_pending_del_e2(bp, o, cmd_pos, &cnt); 2720adfc5217SJeff Kirsher break; 2721adfc5217SJeff Kirsher 2722adfc5217SJeff Kirsher case BNX2X_MCAST_CMD_RESTORE: 2723adfc5217SJeff Kirsher bnx2x_mcast_hdl_pending_restore_e2(bp, o, cmd_pos, 2724adfc5217SJeff Kirsher &cnt); 2725adfc5217SJeff Kirsher break; 2726adfc5217SJeff Kirsher 2727adfc5217SJeff Kirsher default: 2728adfc5217SJeff Kirsher BNX2X_ERR("Unknown command: %d\n", cmd_pos->type); 2729adfc5217SJeff Kirsher return -EINVAL; 2730adfc5217SJeff Kirsher } 2731adfc5217SJeff Kirsher 2732adfc5217SJeff Kirsher /* If the command has been completed - remove it from the list 2733adfc5217SJeff Kirsher * and free the memory 2734adfc5217SJeff Kirsher */ 2735adfc5217SJeff Kirsher if (cmd_pos->done) { 2736adfc5217SJeff Kirsher list_del(&cmd_pos->link); 2737adfc5217SJeff Kirsher kfree(cmd_pos); 2738adfc5217SJeff Kirsher } 2739adfc5217SJeff Kirsher 2740adfc5217SJeff Kirsher /* Break if we reached the maximum number of rules */ 2741adfc5217SJeff Kirsher if (cnt >= o->max_cmd_len) 2742adfc5217SJeff Kirsher break; 2743adfc5217SJeff Kirsher } 2744adfc5217SJeff Kirsher 2745adfc5217SJeff Kirsher return cnt; 2746adfc5217SJeff Kirsher } 2747adfc5217SJeff Kirsher 2748adfc5217SJeff Kirsher static inline void bnx2x_mcast_hdl_add(struct bnx2x *bp, 2749adfc5217SJeff Kirsher struct bnx2x_mcast_obj *o, struct bnx2x_mcast_ramrod_params *p, 2750adfc5217SJeff Kirsher int *line_idx) 2751adfc5217SJeff Kirsher { 2752adfc5217SJeff Kirsher struct bnx2x_mcast_list_elem *mlist_pos; 275386564c3fSYuval Mintz union bnx2x_mcast_config_data cfg_data = {NULL}; 2754adfc5217SJeff Kirsher int cnt = *line_idx; 2755adfc5217SJeff Kirsher 2756adfc5217SJeff Kirsher list_for_each_entry(mlist_pos, &p->mcast_list, link) { 2757adfc5217SJeff Kirsher cfg_data.mac = mlist_pos->mac; 2758adfc5217SJeff Kirsher o->set_one_rule(bp, o, cnt, &cfg_data, BNX2X_MCAST_CMD_ADD); 2759adfc5217SJeff Kirsher 2760adfc5217SJeff Kirsher cnt++; 2761adfc5217SJeff Kirsher 27620f9dad10SJoe Perches DP(BNX2X_MSG_SP, "About to configure %pM mcast MAC\n", 27630f9dad10SJoe Perches mlist_pos->mac); 2764adfc5217SJeff Kirsher } 2765adfc5217SJeff Kirsher 2766adfc5217SJeff Kirsher *line_idx = cnt; 2767adfc5217SJeff Kirsher } 2768adfc5217SJeff Kirsher 2769adfc5217SJeff Kirsher static inline void bnx2x_mcast_hdl_del(struct bnx2x *bp, 2770adfc5217SJeff Kirsher struct bnx2x_mcast_obj *o, struct bnx2x_mcast_ramrod_params *p, 2771adfc5217SJeff Kirsher int *line_idx) 2772adfc5217SJeff Kirsher { 2773adfc5217SJeff Kirsher int cnt = *line_idx, i; 2774adfc5217SJeff Kirsher 2775adfc5217SJeff Kirsher for (i = 0; i < p->mcast_list_len; i++) { 2776adfc5217SJeff Kirsher o->set_one_rule(bp, o, cnt, NULL, BNX2X_MCAST_CMD_DEL); 2777adfc5217SJeff Kirsher 2778adfc5217SJeff Kirsher cnt++; 2779adfc5217SJeff Kirsher 2780adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "Deleting MAC. %d left\n", 2781adfc5217SJeff Kirsher p->mcast_list_len - i - 1); 2782adfc5217SJeff Kirsher } 2783adfc5217SJeff Kirsher 2784adfc5217SJeff Kirsher *line_idx = cnt; 2785adfc5217SJeff Kirsher } 2786adfc5217SJeff Kirsher 2787adfc5217SJeff Kirsher /** 2788adfc5217SJeff Kirsher * bnx2x_mcast_handle_current_cmd - 2789adfc5217SJeff Kirsher * 2790adfc5217SJeff Kirsher * @bp: device handle 2791adfc5217SJeff Kirsher * @p: 2792adfc5217SJeff Kirsher * @cmd: 2793adfc5217SJeff Kirsher * @start_cnt: first line in the ramrod data that may be used 2794adfc5217SJeff Kirsher * 2795adfc5217SJeff Kirsher * This function is called iff there is enough place for the current command in 2796adfc5217SJeff Kirsher * the ramrod data. 2797adfc5217SJeff Kirsher * Returns number of lines filled in the ramrod data in total. 2798adfc5217SJeff Kirsher */ 2799adfc5217SJeff Kirsher static inline int bnx2x_mcast_handle_current_cmd(struct bnx2x *bp, 280086564c3fSYuval Mintz struct bnx2x_mcast_ramrod_params *p, 280186564c3fSYuval Mintz enum bnx2x_mcast_cmd cmd, 2802adfc5217SJeff Kirsher int start_cnt) 2803adfc5217SJeff Kirsher { 2804adfc5217SJeff Kirsher struct bnx2x_mcast_obj *o = p->mcast_obj; 2805adfc5217SJeff Kirsher int cnt = start_cnt; 2806adfc5217SJeff Kirsher 2807adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "p->mcast_list_len=%d\n", p->mcast_list_len); 2808adfc5217SJeff Kirsher 2809adfc5217SJeff Kirsher switch (cmd) { 2810adfc5217SJeff Kirsher case BNX2X_MCAST_CMD_ADD: 2811adfc5217SJeff Kirsher bnx2x_mcast_hdl_add(bp, o, p, &cnt); 2812adfc5217SJeff Kirsher break; 2813adfc5217SJeff Kirsher 2814adfc5217SJeff Kirsher case BNX2X_MCAST_CMD_DEL: 2815adfc5217SJeff Kirsher bnx2x_mcast_hdl_del(bp, o, p, &cnt); 2816adfc5217SJeff Kirsher break; 2817adfc5217SJeff Kirsher 2818adfc5217SJeff Kirsher case BNX2X_MCAST_CMD_RESTORE: 2819adfc5217SJeff Kirsher o->hdl_restore(bp, o, 0, &cnt); 2820adfc5217SJeff Kirsher break; 2821adfc5217SJeff Kirsher 2822adfc5217SJeff Kirsher default: 2823adfc5217SJeff Kirsher BNX2X_ERR("Unknown command: %d\n", cmd); 2824adfc5217SJeff Kirsher return -EINVAL; 2825adfc5217SJeff Kirsher } 2826adfc5217SJeff Kirsher 2827adfc5217SJeff Kirsher /* The current command has been handled */ 2828adfc5217SJeff Kirsher p->mcast_list_len = 0; 2829adfc5217SJeff Kirsher 2830adfc5217SJeff Kirsher return cnt; 2831adfc5217SJeff Kirsher } 2832adfc5217SJeff Kirsher 2833adfc5217SJeff Kirsher static int bnx2x_mcast_validate_e2(struct bnx2x *bp, 2834adfc5217SJeff Kirsher struct bnx2x_mcast_ramrod_params *p, 283586564c3fSYuval Mintz enum bnx2x_mcast_cmd cmd) 2836adfc5217SJeff Kirsher { 2837adfc5217SJeff Kirsher struct bnx2x_mcast_obj *o = p->mcast_obj; 2838adfc5217SJeff Kirsher int reg_sz = o->get_registry_size(o); 2839adfc5217SJeff Kirsher 2840adfc5217SJeff Kirsher switch (cmd) { 2841adfc5217SJeff Kirsher /* DEL command deletes all currently configured MACs */ 2842adfc5217SJeff Kirsher case BNX2X_MCAST_CMD_DEL: 2843adfc5217SJeff Kirsher o->set_registry_size(o, 0); 2844adfc5217SJeff Kirsher /* Don't break */ 2845adfc5217SJeff Kirsher 2846adfc5217SJeff Kirsher /* RESTORE command will restore the entire multicast configuration */ 2847adfc5217SJeff Kirsher case BNX2X_MCAST_CMD_RESTORE: 2848adfc5217SJeff Kirsher /* Here we set the approximate amount of work to do, which in 2849adfc5217SJeff Kirsher * fact may be only less as some MACs in postponed ADD 2850adfc5217SJeff Kirsher * command(s) scheduled before this command may fall into 2851adfc5217SJeff Kirsher * the same bin and the actual number of bins set in the 2852adfc5217SJeff Kirsher * registry would be less than we estimated here. See 2853adfc5217SJeff Kirsher * bnx2x_mcast_set_one_rule_e2() for further details. 2854adfc5217SJeff Kirsher */ 2855adfc5217SJeff Kirsher p->mcast_list_len = reg_sz; 2856adfc5217SJeff Kirsher break; 2857adfc5217SJeff Kirsher 2858adfc5217SJeff Kirsher case BNX2X_MCAST_CMD_ADD: 2859adfc5217SJeff Kirsher case BNX2X_MCAST_CMD_CONT: 2860adfc5217SJeff Kirsher /* Here we assume that all new MACs will fall into new bins. 2861adfc5217SJeff Kirsher * However we will correct the real registry size after we 2862adfc5217SJeff Kirsher * handle all pending commands. 2863adfc5217SJeff Kirsher */ 2864adfc5217SJeff Kirsher o->set_registry_size(o, reg_sz + p->mcast_list_len); 2865adfc5217SJeff Kirsher break; 2866adfc5217SJeff Kirsher 2867adfc5217SJeff Kirsher default: 2868adfc5217SJeff Kirsher BNX2X_ERR("Unknown command: %d\n", cmd); 2869adfc5217SJeff Kirsher return -EINVAL; 2870adfc5217SJeff Kirsher } 2871adfc5217SJeff Kirsher 2872adfc5217SJeff Kirsher /* Increase the total number of MACs pending to be configured */ 2873adfc5217SJeff Kirsher o->total_pending_num += p->mcast_list_len; 2874adfc5217SJeff Kirsher 2875adfc5217SJeff Kirsher return 0; 2876adfc5217SJeff Kirsher } 2877adfc5217SJeff Kirsher 2878adfc5217SJeff Kirsher static void bnx2x_mcast_revert_e2(struct bnx2x *bp, 2879adfc5217SJeff Kirsher struct bnx2x_mcast_ramrod_params *p, 2880adfc5217SJeff Kirsher int old_num_bins) 2881adfc5217SJeff Kirsher { 2882adfc5217SJeff Kirsher struct bnx2x_mcast_obj *o = p->mcast_obj; 2883adfc5217SJeff Kirsher 2884adfc5217SJeff Kirsher o->set_registry_size(o, old_num_bins); 2885adfc5217SJeff Kirsher o->total_pending_num -= p->mcast_list_len; 2886adfc5217SJeff Kirsher } 2887adfc5217SJeff Kirsher 2888adfc5217SJeff Kirsher /** 2889adfc5217SJeff Kirsher * bnx2x_mcast_set_rdata_hdr_e2 - sets a header values 2890adfc5217SJeff Kirsher * 2891adfc5217SJeff Kirsher * @bp: device handle 2892adfc5217SJeff Kirsher * @p: 2893adfc5217SJeff Kirsher * @len: number of rules to handle 2894adfc5217SJeff Kirsher */ 2895adfc5217SJeff Kirsher static inline void bnx2x_mcast_set_rdata_hdr_e2(struct bnx2x *bp, 2896adfc5217SJeff Kirsher struct bnx2x_mcast_ramrod_params *p, 2897adfc5217SJeff Kirsher u8 len) 2898adfc5217SJeff Kirsher { 2899adfc5217SJeff Kirsher struct bnx2x_raw_obj *r = &p->mcast_obj->raw; 2900adfc5217SJeff Kirsher struct eth_multicast_rules_ramrod_data *data = 2901adfc5217SJeff Kirsher (struct eth_multicast_rules_ramrod_data *)(r->rdata); 2902adfc5217SJeff Kirsher 290386564c3fSYuval Mintz data->header.echo = cpu_to_le32((r->cid & BNX2X_SWCID_MASK) | 290486564c3fSYuval Mintz (BNX2X_FILTER_MCAST_PENDING << 290586564c3fSYuval Mintz BNX2X_SWCID_SHIFT)); 2906adfc5217SJeff Kirsher data->header.rule_cnt = len; 2907adfc5217SJeff Kirsher } 2908adfc5217SJeff Kirsher 2909adfc5217SJeff Kirsher /** 2910adfc5217SJeff Kirsher * bnx2x_mcast_refresh_registry_e2 - recalculate the actual number of set bins 2911adfc5217SJeff Kirsher * 2912adfc5217SJeff Kirsher * @bp: device handle 2913adfc5217SJeff Kirsher * @o: 2914adfc5217SJeff Kirsher * 2915adfc5217SJeff Kirsher * Recalculate the actual number of set bins in the registry using Brian 2916adfc5217SJeff Kirsher * Kernighan's algorithm: it's execution complexity is as a number of set bins. 2917adfc5217SJeff Kirsher * 2918adfc5217SJeff Kirsher * returns 0 for the compliance with bnx2x_mcast_refresh_registry_e1(). 2919adfc5217SJeff Kirsher */ 2920adfc5217SJeff Kirsher static inline int bnx2x_mcast_refresh_registry_e2(struct bnx2x *bp, 2921adfc5217SJeff Kirsher struct bnx2x_mcast_obj *o) 2922adfc5217SJeff Kirsher { 2923adfc5217SJeff Kirsher int i, cnt = 0; 2924adfc5217SJeff Kirsher u64 elem; 2925adfc5217SJeff Kirsher 2926adfc5217SJeff Kirsher for (i = 0; i < BNX2X_MCAST_VEC_SZ; i++) { 2927adfc5217SJeff Kirsher elem = o->registry.aprox_match.vec[i]; 2928adfc5217SJeff Kirsher for (; elem; cnt++) 2929adfc5217SJeff Kirsher elem &= elem - 1; 2930adfc5217SJeff Kirsher } 2931adfc5217SJeff Kirsher 2932adfc5217SJeff Kirsher o->set_registry_size(o, cnt); 2933adfc5217SJeff Kirsher 2934adfc5217SJeff Kirsher return 0; 2935adfc5217SJeff Kirsher } 2936adfc5217SJeff Kirsher 2937adfc5217SJeff Kirsher static int bnx2x_mcast_setup_e2(struct bnx2x *bp, 2938adfc5217SJeff Kirsher struct bnx2x_mcast_ramrod_params *p, 293986564c3fSYuval Mintz enum bnx2x_mcast_cmd cmd) 2940adfc5217SJeff Kirsher { 2941adfc5217SJeff Kirsher struct bnx2x_raw_obj *raw = &p->mcast_obj->raw; 2942adfc5217SJeff Kirsher struct bnx2x_mcast_obj *o = p->mcast_obj; 2943adfc5217SJeff Kirsher struct eth_multicast_rules_ramrod_data *data = 2944adfc5217SJeff Kirsher (struct eth_multicast_rules_ramrod_data *)(raw->rdata); 2945adfc5217SJeff Kirsher int cnt = 0, rc; 2946adfc5217SJeff Kirsher 2947adfc5217SJeff Kirsher /* Reset the ramrod data buffer */ 2948adfc5217SJeff Kirsher memset(data, 0, sizeof(*data)); 2949adfc5217SJeff Kirsher 2950adfc5217SJeff Kirsher cnt = bnx2x_mcast_handle_pending_cmds_e2(bp, p); 2951adfc5217SJeff Kirsher 2952adfc5217SJeff Kirsher /* If there are no more pending commands - clear SCHEDULED state */ 2953adfc5217SJeff Kirsher if (list_empty(&o->pending_cmds_head)) 2954adfc5217SJeff Kirsher o->clear_sched(o); 2955adfc5217SJeff Kirsher 2956adfc5217SJeff Kirsher /* The below may be true iff there was enough room in ramrod 2957adfc5217SJeff Kirsher * data for all pending commands and for the current 2958adfc5217SJeff Kirsher * command. Otherwise the current command would have been added 2959adfc5217SJeff Kirsher * to the pending commands and p->mcast_list_len would have been 2960adfc5217SJeff Kirsher * zeroed. 2961adfc5217SJeff Kirsher */ 2962adfc5217SJeff Kirsher if (p->mcast_list_len > 0) 2963adfc5217SJeff Kirsher cnt = bnx2x_mcast_handle_current_cmd(bp, p, cmd, cnt); 2964adfc5217SJeff Kirsher 2965adfc5217SJeff Kirsher /* We've pulled out some MACs - update the total number of 2966adfc5217SJeff Kirsher * outstanding. 2967adfc5217SJeff Kirsher */ 2968adfc5217SJeff Kirsher o->total_pending_num -= cnt; 2969adfc5217SJeff Kirsher 2970adfc5217SJeff Kirsher /* send a ramrod */ 2971adfc5217SJeff Kirsher WARN_ON(o->total_pending_num < 0); 2972adfc5217SJeff Kirsher WARN_ON(cnt > o->max_cmd_len); 2973adfc5217SJeff Kirsher 2974adfc5217SJeff Kirsher bnx2x_mcast_set_rdata_hdr_e2(bp, p, (u8)cnt); 2975adfc5217SJeff Kirsher 2976adfc5217SJeff Kirsher /* Update a registry size if there are no more pending operations. 2977adfc5217SJeff Kirsher * 2978adfc5217SJeff Kirsher * We don't want to change the value of the registry size if there are 2979adfc5217SJeff Kirsher * pending operations because we want it to always be equal to the 2980adfc5217SJeff Kirsher * exact or the approximate number (see bnx2x_mcast_validate_e2()) of 2981adfc5217SJeff Kirsher * set bins after the last requested operation in order to properly 2982adfc5217SJeff Kirsher * evaluate the size of the next DEL/RESTORE operation. 2983adfc5217SJeff Kirsher * 2984adfc5217SJeff Kirsher * Note that we update the registry itself during command(s) handling 2985adfc5217SJeff Kirsher * - see bnx2x_mcast_set_one_rule_e2(). That's because for 57712 we 2986adfc5217SJeff Kirsher * aggregate multiple commands (ADD/DEL/RESTORE) into one ramrod but 2987adfc5217SJeff Kirsher * with a limited amount of update commands (per MAC/bin) and we don't 2988adfc5217SJeff Kirsher * know in this scope what the actual state of bins configuration is 2989adfc5217SJeff Kirsher * going to be after this ramrod. 2990adfc5217SJeff Kirsher */ 2991adfc5217SJeff Kirsher if (!o->total_pending_num) 2992adfc5217SJeff Kirsher bnx2x_mcast_refresh_registry_e2(bp, o); 2993adfc5217SJeff Kirsher 299416a5fd92SYuval Mintz /* If CLEAR_ONLY was requested - don't send a ramrod and clear 2995adfc5217SJeff Kirsher * RAMROD_PENDING status immediately. 2996adfc5217SJeff Kirsher */ 2997adfc5217SJeff Kirsher if (test_bit(RAMROD_DRV_CLR_ONLY, &p->ramrod_flags)) { 2998adfc5217SJeff Kirsher raw->clear_pending(raw); 2999adfc5217SJeff Kirsher return 0; 3000adfc5217SJeff Kirsher } else { 300116a5fd92SYuval Mintz /* No need for an explicit memory barrier here as long we would 3002adfc5217SJeff Kirsher * need to ensure the ordering of writing to the SPQ element 3003adfc5217SJeff Kirsher * and updating of the SPQ producer which involves a memory 3004adfc5217SJeff Kirsher * read and we will have to put a full memory barrier there 3005adfc5217SJeff Kirsher * (inside bnx2x_sp_post()). 3006adfc5217SJeff Kirsher */ 3007adfc5217SJeff Kirsher 3008adfc5217SJeff Kirsher /* Send a ramrod */ 3009adfc5217SJeff Kirsher rc = bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_MULTICAST_RULES, 3010adfc5217SJeff Kirsher raw->cid, U64_HI(raw->rdata_mapping), 3011adfc5217SJeff Kirsher U64_LO(raw->rdata_mapping), 3012adfc5217SJeff Kirsher ETH_CONNECTION_TYPE); 3013adfc5217SJeff Kirsher if (rc) 3014adfc5217SJeff Kirsher return rc; 3015adfc5217SJeff Kirsher 3016adfc5217SJeff Kirsher /* Ramrod completion is pending */ 3017adfc5217SJeff Kirsher return 1; 3018adfc5217SJeff Kirsher } 3019adfc5217SJeff Kirsher } 3020adfc5217SJeff Kirsher 3021adfc5217SJeff Kirsher static int bnx2x_mcast_validate_e1h(struct bnx2x *bp, 3022adfc5217SJeff Kirsher struct bnx2x_mcast_ramrod_params *p, 302386564c3fSYuval Mintz enum bnx2x_mcast_cmd cmd) 3024adfc5217SJeff Kirsher { 3025adfc5217SJeff Kirsher /* Mark, that there is a work to do */ 3026adfc5217SJeff Kirsher if ((cmd == BNX2X_MCAST_CMD_DEL) || (cmd == BNX2X_MCAST_CMD_RESTORE)) 3027adfc5217SJeff Kirsher p->mcast_list_len = 1; 3028adfc5217SJeff Kirsher 3029adfc5217SJeff Kirsher return 0; 3030adfc5217SJeff Kirsher } 3031adfc5217SJeff Kirsher 3032adfc5217SJeff Kirsher static void bnx2x_mcast_revert_e1h(struct bnx2x *bp, 3033adfc5217SJeff Kirsher struct bnx2x_mcast_ramrod_params *p, 3034adfc5217SJeff Kirsher int old_num_bins) 3035adfc5217SJeff Kirsher { 3036adfc5217SJeff Kirsher /* Do nothing */ 3037adfc5217SJeff Kirsher } 3038adfc5217SJeff Kirsher 3039adfc5217SJeff Kirsher #define BNX2X_57711_SET_MC_FILTER(filter, bit) \ 3040adfc5217SJeff Kirsher do { \ 3041adfc5217SJeff Kirsher (filter)[(bit) >> 5] |= (1 << ((bit) & 0x1f)); \ 3042adfc5217SJeff Kirsher } while (0) 3043adfc5217SJeff Kirsher 3044adfc5217SJeff Kirsher static inline void bnx2x_mcast_hdl_add_e1h(struct bnx2x *bp, 3045adfc5217SJeff Kirsher struct bnx2x_mcast_obj *o, 3046adfc5217SJeff Kirsher struct bnx2x_mcast_ramrod_params *p, 3047adfc5217SJeff Kirsher u32 *mc_filter) 3048adfc5217SJeff Kirsher { 3049adfc5217SJeff Kirsher struct bnx2x_mcast_list_elem *mlist_pos; 3050adfc5217SJeff Kirsher int bit; 3051adfc5217SJeff Kirsher 3052adfc5217SJeff Kirsher list_for_each_entry(mlist_pos, &p->mcast_list, link) { 3053adfc5217SJeff Kirsher bit = bnx2x_mcast_bin_from_mac(mlist_pos->mac); 3054adfc5217SJeff Kirsher BNX2X_57711_SET_MC_FILTER(mc_filter, bit); 3055adfc5217SJeff Kirsher 30560f9dad10SJoe Perches DP(BNX2X_MSG_SP, "About to configure %pM mcast MAC, bin %d\n", 30570f9dad10SJoe Perches mlist_pos->mac, bit); 3058adfc5217SJeff Kirsher 3059adfc5217SJeff Kirsher /* bookkeeping... */ 3060adfc5217SJeff Kirsher BIT_VEC64_SET_BIT(o->registry.aprox_match.vec, 3061adfc5217SJeff Kirsher bit); 3062adfc5217SJeff Kirsher } 3063adfc5217SJeff Kirsher } 3064adfc5217SJeff Kirsher 3065adfc5217SJeff Kirsher static inline void bnx2x_mcast_hdl_restore_e1h(struct bnx2x *bp, 3066adfc5217SJeff Kirsher struct bnx2x_mcast_obj *o, struct bnx2x_mcast_ramrod_params *p, 3067adfc5217SJeff Kirsher u32 *mc_filter) 3068adfc5217SJeff Kirsher { 3069adfc5217SJeff Kirsher int bit; 3070adfc5217SJeff Kirsher 3071adfc5217SJeff Kirsher for (bit = bnx2x_mcast_get_next_bin(o, 0); 3072adfc5217SJeff Kirsher bit >= 0; 3073adfc5217SJeff Kirsher bit = bnx2x_mcast_get_next_bin(o, bit + 1)) { 3074adfc5217SJeff Kirsher BNX2X_57711_SET_MC_FILTER(mc_filter, bit); 3075adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "About to set bin %d\n", bit); 3076adfc5217SJeff Kirsher } 3077adfc5217SJeff Kirsher } 3078adfc5217SJeff Kirsher 307916a5fd92SYuval Mintz /* On 57711 we write the multicast MACs' approximate match 3080adfc5217SJeff Kirsher * table by directly into the TSTORM's internal RAM. So we don't 3081adfc5217SJeff Kirsher * really need to handle any tricks to make it work. 3082adfc5217SJeff Kirsher */ 3083adfc5217SJeff Kirsher static int bnx2x_mcast_setup_e1h(struct bnx2x *bp, 3084adfc5217SJeff Kirsher struct bnx2x_mcast_ramrod_params *p, 308586564c3fSYuval Mintz enum bnx2x_mcast_cmd cmd) 3086adfc5217SJeff Kirsher { 3087adfc5217SJeff Kirsher int i; 3088adfc5217SJeff Kirsher struct bnx2x_mcast_obj *o = p->mcast_obj; 3089adfc5217SJeff Kirsher struct bnx2x_raw_obj *r = &o->raw; 3090adfc5217SJeff Kirsher 3091adfc5217SJeff Kirsher /* If CLEAR_ONLY has been requested - clear the registry 3092adfc5217SJeff Kirsher * and clear a pending bit. 3093adfc5217SJeff Kirsher */ 3094adfc5217SJeff Kirsher if (!test_bit(RAMROD_DRV_CLR_ONLY, &p->ramrod_flags)) { 3095adfc5217SJeff Kirsher u32 mc_filter[MC_HASH_SIZE] = {0}; 3096adfc5217SJeff Kirsher 3097adfc5217SJeff Kirsher /* Set the multicast filter bits before writing it into 3098adfc5217SJeff Kirsher * the internal memory. 3099adfc5217SJeff Kirsher */ 3100adfc5217SJeff Kirsher switch (cmd) { 3101adfc5217SJeff Kirsher case BNX2X_MCAST_CMD_ADD: 3102adfc5217SJeff Kirsher bnx2x_mcast_hdl_add_e1h(bp, o, p, mc_filter); 3103adfc5217SJeff Kirsher break; 3104adfc5217SJeff Kirsher 3105adfc5217SJeff Kirsher case BNX2X_MCAST_CMD_DEL: 310694f05b0fSJoe Perches DP(BNX2X_MSG_SP, 310794f05b0fSJoe Perches "Invalidating multicast MACs configuration\n"); 3108adfc5217SJeff Kirsher 3109adfc5217SJeff Kirsher /* clear the registry */ 3110adfc5217SJeff Kirsher memset(o->registry.aprox_match.vec, 0, 3111adfc5217SJeff Kirsher sizeof(o->registry.aprox_match.vec)); 3112adfc5217SJeff Kirsher break; 3113adfc5217SJeff Kirsher 3114adfc5217SJeff Kirsher case BNX2X_MCAST_CMD_RESTORE: 3115adfc5217SJeff Kirsher bnx2x_mcast_hdl_restore_e1h(bp, o, p, mc_filter); 3116adfc5217SJeff Kirsher break; 3117adfc5217SJeff Kirsher 3118adfc5217SJeff Kirsher default: 3119adfc5217SJeff Kirsher BNX2X_ERR("Unknown command: %d\n", cmd); 3120adfc5217SJeff Kirsher return -EINVAL; 3121adfc5217SJeff Kirsher } 3122adfc5217SJeff Kirsher 3123adfc5217SJeff Kirsher /* Set the mcast filter in the internal memory */ 3124adfc5217SJeff Kirsher for (i = 0; i < MC_HASH_SIZE; i++) 3125adfc5217SJeff Kirsher REG_WR(bp, MC_HASH_OFFSET(bp, i), mc_filter[i]); 3126adfc5217SJeff Kirsher } else 3127adfc5217SJeff Kirsher /* clear the registry */ 3128adfc5217SJeff Kirsher memset(o->registry.aprox_match.vec, 0, 3129adfc5217SJeff Kirsher sizeof(o->registry.aprox_match.vec)); 3130adfc5217SJeff Kirsher 3131adfc5217SJeff Kirsher /* We are done */ 3132adfc5217SJeff Kirsher r->clear_pending(r); 3133adfc5217SJeff Kirsher 3134adfc5217SJeff Kirsher return 0; 3135adfc5217SJeff Kirsher } 3136adfc5217SJeff Kirsher 3137adfc5217SJeff Kirsher static int bnx2x_mcast_validate_e1(struct bnx2x *bp, 3138adfc5217SJeff Kirsher struct bnx2x_mcast_ramrod_params *p, 313986564c3fSYuval Mintz enum bnx2x_mcast_cmd cmd) 3140adfc5217SJeff Kirsher { 3141adfc5217SJeff Kirsher struct bnx2x_mcast_obj *o = p->mcast_obj; 3142adfc5217SJeff Kirsher int reg_sz = o->get_registry_size(o); 3143adfc5217SJeff Kirsher 3144adfc5217SJeff Kirsher switch (cmd) { 3145adfc5217SJeff Kirsher /* DEL command deletes all currently configured MACs */ 3146adfc5217SJeff Kirsher case BNX2X_MCAST_CMD_DEL: 3147adfc5217SJeff Kirsher o->set_registry_size(o, 0); 3148adfc5217SJeff Kirsher /* Don't break */ 3149adfc5217SJeff Kirsher 3150adfc5217SJeff Kirsher /* RESTORE command will restore the entire multicast configuration */ 3151adfc5217SJeff Kirsher case BNX2X_MCAST_CMD_RESTORE: 3152adfc5217SJeff Kirsher p->mcast_list_len = reg_sz; 3153adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "Command %d, p->mcast_list_len=%d\n", 3154adfc5217SJeff Kirsher cmd, p->mcast_list_len); 3155adfc5217SJeff Kirsher break; 3156adfc5217SJeff Kirsher 3157adfc5217SJeff Kirsher case BNX2X_MCAST_CMD_ADD: 3158adfc5217SJeff Kirsher case BNX2X_MCAST_CMD_CONT: 3159adfc5217SJeff Kirsher /* Multicast MACs on 57710 are configured as unicast MACs and 3160adfc5217SJeff Kirsher * there is only a limited number of CAM entries for that 3161adfc5217SJeff Kirsher * matter. 3162adfc5217SJeff Kirsher */ 3163adfc5217SJeff Kirsher if (p->mcast_list_len > o->max_cmd_len) { 316451c1a580SMerav Sicron BNX2X_ERR("Can't configure more than %d multicast MACs on 57710\n", 316551c1a580SMerav Sicron o->max_cmd_len); 3166adfc5217SJeff Kirsher return -EINVAL; 3167adfc5217SJeff Kirsher } 3168adfc5217SJeff Kirsher /* Every configured MAC should be cleared if DEL command is 3169adfc5217SJeff Kirsher * called. Only the last ADD command is relevant as long as 3170adfc5217SJeff Kirsher * every ADD commands overrides the previous configuration. 3171adfc5217SJeff Kirsher */ 3172adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "p->mcast_list_len=%d\n", p->mcast_list_len); 3173adfc5217SJeff Kirsher if (p->mcast_list_len > 0) 3174adfc5217SJeff Kirsher o->set_registry_size(o, p->mcast_list_len); 3175adfc5217SJeff Kirsher 3176adfc5217SJeff Kirsher break; 3177adfc5217SJeff Kirsher 3178adfc5217SJeff Kirsher default: 3179adfc5217SJeff Kirsher BNX2X_ERR("Unknown command: %d\n", cmd); 3180adfc5217SJeff Kirsher return -EINVAL; 3181adfc5217SJeff Kirsher } 3182adfc5217SJeff Kirsher 3183adfc5217SJeff Kirsher /* We want to ensure that commands are executed one by one for 57710. 3184adfc5217SJeff Kirsher * Therefore each none-empty command will consume o->max_cmd_len. 3185adfc5217SJeff Kirsher */ 3186adfc5217SJeff Kirsher if (p->mcast_list_len) 3187adfc5217SJeff Kirsher o->total_pending_num += o->max_cmd_len; 3188adfc5217SJeff Kirsher 3189adfc5217SJeff Kirsher return 0; 3190adfc5217SJeff Kirsher } 3191adfc5217SJeff Kirsher 3192adfc5217SJeff Kirsher static void bnx2x_mcast_revert_e1(struct bnx2x *bp, 3193adfc5217SJeff Kirsher struct bnx2x_mcast_ramrod_params *p, 3194adfc5217SJeff Kirsher int old_num_macs) 3195adfc5217SJeff Kirsher { 3196adfc5217SJeff Kirsher struct bnx2x_mcast_obj *o = p->mcast_obj; 3197adfc5217SJeff Kirsher 3198adfc5217SJeff Kirsher o->set_registry_size(o, old_num_macs); 3199adfc5217SJeff Kirsher 3200adfc5217SJeff Kirsher /* If current command hasn't been handled yet and we are 3201adfc5217SJeff Kirsher * here means that it's meant to be dropped and we have to 320216a5fd92SYuval Mintz * update the number of outstanding MACs accordingly. 3203adfc5217SJeff Kirsher */ 3204adfc5217SJeff Kirsher if (p->mcast_list_len) 3205adfc5217SJeff Kirsher o->total_pending_num -= o->max_cmd_len; 3206adfc5217SJeff Kirsher } 3207adfc5217SJeff Kirsher 3208adfc5217SJeff Kirsher static void bnx2x_mcast_set_one_rule_e1(struct bnx2x *bp, 3209adfc5217SJeff Kirsher struct bnx2x_mcast_obj *o, int idx, 3210adfc5217SJeff Kirsher union bnx2x_mcast_config_data *cfg_data, 321186564c3fSYuval Mintz enum bnx2x_mcast_cmd cmd) 3212adfc5217SJeff Kirsher { 3213adfc5217SJeff Kirsher struct bnx2x_raw_obj *r = &o->raw; 3214adfc5217SJeff Kirsher struct mac_configuration_cmd *data = 3215adfc5217SJeff Kirsher (struct mac_configuration_cmd *)(r->rdata); 3216adfc5217SJeff Kirsher 3217adfc5217SJeff Kirsher /* copy mac */ 3218adfc5217SJeff Kirsher if ((cmd == BNX2X_MCAST_CMD_ADD) || (cmd == BNX2X_MCAST_CMD_RESTORE)) { 3219adfc5217SJeff Kirsher bnx2x_set_fw_mac_addr(&data->config_table[idx].msb_mac_addr, 3220adfc5217SJeff Kirsher &data->config_table[idx].middle_mac_addr, 3221adfc5217SJeff Kirsher &data->config_table[idx].lsb_mac_addr, 3222adfc5217SJeff Kirsher cfg_data->mac); 3223adfc5217SJeff Kirsher 3224adfc5217SJeff Kirsher data->config_table[idx].vlan_id = 0; 3225adfc5217SJeff Kirsher data->config_table[idx].pf_id = r->func_id; 3226adfc5217SJeff Kirsher data->config_table[idx].clients_bit_vector = 3227adfc5217SJeff Kirsher cpu_to_le32(1 << r->cl_id); 3228adfc5217SJeff Kirsher 3229adfc5217SJeff Kirsher SET_FLAG(data->config_table[idx].flags, 3230adfc5217SJeff Kirsher MAC_CONFIGURATION_ENTRY_ACTION_TYPE, 3231adfc5217SJeff Kirsher T_ETH_MAC_COMMAND_SET); 3232adfc5217SJeff Kirsher } 3233adfc5217SJeff Kirsher } 3234adfc5217SJeff Kirsher 3235adfc5217SJeff Kirsher /** 3236adfc5217SJeff Kirsher * bnx2x_mcast_set_rdata_hdr_e1 - set header values in mac_configuration_cmd 3237adfc5217SJeff Kirsher * 3238adfc5217SJeff Kirsher * @bp: device handle 3239adfc5217SJeff Kirsher * @p: 3240adfc5217SJeff Kirsher * @len: number of rules to handle 3241adfc5217SJeff Kirsher */ 3242adfc5217SJeff Kirsher static inline void bnx2x_mcast_set_rdata_hdr_e1(struct bnx2x *bp, 3243adfc5217SJeff Kirsher struct bnx2x_mcast_ramrod_params *p, 3244adfc5217SJeff Kirsher u8 len) 3245adfc5217SJeff Kirsher { 3246adfc5217SJeff Kirsher struct bnx2x_raw_obj *r = &p->mcast_obj->raw; 3247adfc5217SJeff Kirsher struct mac_configuration_cmd *data = 3248adfc5217SJeff Kirsher (struct mac_configuration_cmd *)(r->rdata); 3249adfc5217SJeff Kirsher 3250adfc5217SJeff Kirsher u8 offset = (CHIP_REV_IS_SLOW(bp) ? 3251adfc5217SJeff Kirsher BNX2X_MAX_EMUL_MULTI*(1 + r->func_id) : 3252adfc5217SJeff Kirsher BNX2X_MAX_MULTICAST*(1 + r->func_id)); 3253adfc5217SJeff Kirsher 3254adfc5217SJeff Kirsher data->hdr.offset = offset; 325586564c3fSYuval Mintz data->hdr.client_id = cpu_to_le16(0xff); 325686564c3fSYuval Mintz data->hdr.echo = cpu_to_le32((r->cid & BNX2X_SWCID_MASK) | 325786564c3fSYuval Mintz (BNX2X_FILTER_MCAST_PENDING << 325886564c3fSYuval Mintz BNX2X_SWCID_SHIFT)); 3259adfc5217SJeff Kirsher data->hdr.length = len; 3260adfc5217SJeff Kirsher } 3261adfc5217SJeff Kirsher 3262adfc5217SJeff Kirsher /** 3263adfc5217SJeff Kirsher * bnx2x_mcast_handle_restore_cmd_e1 - restore command for 57710 3264adfc5217SJeff Kirsher * 3265adfc5217SJeff Kirsher * @bp: device handle 3266adfc5217SJeff Kirsher * @o: 3267adfc5217SJeff Kirsher * @start_idx: index in the registry to start from 3268adfc5217SJeff Kirsher * @rdata_idx: index in the ramrod data to start from 3269adfc5217SJeff Kirsher * 3270adfc5217SJeff Kirsher * restore command for 57710 is like all other commands - always a stand alone 3271adfc5217SJeff Kirsher * command - start_idx and rdata_idx will always be 0. This function will always 3272adfc5217SJeff Kirsher * succeed. 3273adfc5217SJeff Kirsher * returns -1 to comply with 57712 variant. 3274adfc5217SJeff Kirsher */ 3275adfc5217SJeff Kirsher static inline int bnx2x_mcast_handle_restore_cmd_e1( 3276adfc5217SJeff Kirsher struct bnx2x *bp, struct bnx2x_mcast_obj *o , int start_idx, 3277adfc5217SJeff Kirsher int *rdata_idx) 3278adfc5217SJeff Kirsher { 3279adfc5217SJeff Kirsher struct bnx2x_mcast_mac_elem *elem; 3280adfc5217SJeff Kirsher int i = 0; 328186564c3fSYuval Mintz union bnx2x_mcast_config_data cfg_data = {NULL}; 3282adfc5217SJeff Kirsher 3283adfc5217SJeff Kirsher /* go through the registry and configure the MACs from it. */ 3284adfc5217SJeff Kirsher list_for_each_entry(elem, &o->registry.exact_match.macs, link) { 3285adfc5217SJeff Kirsher cfg_data.mac = &elem->mac[0]; 3286adfc5217SJeff Kirsher o->set_one_rule(bp, o, i, &cfg_data, BNX2X_MCAST_CMD_RESTORE); 3287adfc5217SJeff Kirsher 3288adfc5217SJeff Kirsher i++; 3289adfc5217SJeff Kirsher 32900f9dad10SJoe Perches DP(BNX2X_MSG_SP, "About to configure %pM mcast MAC\n", 32910f9dad10SJoe Perches cfg_data.mac); 3292adfc5217SJeff Kirsher } 3293adfc5217SJeff Kirsher 3294adfc5217SJeff Kirsher *rdata_idx = i; 3295adfc5217SJeff Kirsher 3296adfc5217SJeff Kirsher return -1; 3297adfc5217SJeff Kirsher } 3298adfc5217SJeff Kirsher 3299adfc5217SJeff Kirsher static inline int bnx2x_mcast_handle_pending_cmds_e1( 3300adfc5217SJeff Kirsher struct bnx2x *bp, struct bnx2x_mcast_ramrod_params *p) 3301adfc5217SJeff Kirsher { 3302adfc5217SJeff Kirsher struct bnx2x_pending_mcast_cmd *cmd_pos; 3303adfc5217SJeff Kirsher struct bnx2x_mcast_mac_elem *pmac_pos; 3304adfc5217SJeff Kirsher struct bnx2x_mcast_obj *o = p->mcast_obj; 330586564c3fSYuval Mintz union bnx2x_mcast_config_data cfg_data = {NULL}; 3306adfc5217SJeff Kirsher int cnt = 0; 3307adfc5217SJeff Kirsher 3308adfc5217SJeff Kirsher /* If nothing to be done - return */ 3309adfc5217SJeff Kirsher if (list_empty(&o->pending_cmds_head)) 3310adfc5217SJeff Kirsher return 0; 3311adfc5217SJeff Kirsher 3312adfc5217SJeff Kirsher /* Handle the first command */ 3313adfc5217SJeff Kirsher cmd_pos = list_first_entry(&o->pending_cmds_head, 3314adfc5217SJeff Kirsher struct bnx2x_pending_mcast_cmd, link); 3315adfc5217SJeff Kirsher 3316adfc5217SJeff Kirsher switch (cmd_pos->type) { 3317adfc5217SJeff Kirsher case BNX2X_MCAST_CMD_ADD: 3318adfc5217SJeff Kirsher list_for_each_entry(pmac_pos, &cmd_pos->data.macs_head, link) { 3319adfc5217SJeff Kirsher cfg_data.mac = &pmac_pos->mac[0]; 3320adfc5217SJeff Kirsher o->set_one_rule(bp, o, cnt, &cfg_data, cmd_pos->type); 3321adfc5217SJeff Kirsher 3322adfc5217SJeff Kirsher cnt++; 3323adfc5217SJeff Kirsher 33240f9dad10SJoe Perches DP(BNX2X_MSG_SP, "About to configure %pM mcast MAC\n", 33250f9dad10SJoe Perches pmac_pos->mac); 3326adfc5217SJeff Kirsher } 3327adfc5217SJeff Kirsher break; 3328adfc5217SJeff Kirsher 3329adfc5217SJeff Kirsher case BNX2X_MCAST_CMD_DEL: 3330adfc5217SJeff Kirsher cnt = cmd_pos->data.macs_num; 3331adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "About to delete %d multicast MACs\n", cnt); 3332adfc5217SJeff Kirsher break; 3333adfc5217SJeff Kirsher 3334adfc5217SJeff Kirsher case BNX2X_MCAST_CMD_RESTORE: 3335adfc5217SJeff Kirsher o->hdl_restore(bp, o, 0, &cnt); 3336adfc5217SJeff Kirsher break; 3337adfc5217SJeff Kirsher 3338adfc5217SJeff Kirsher default: 3339adfc5217SJeff Kirsher BNX2X_ERR("Unknown command: %d\n", cmd_pos->type); 3340adfc5217SJeff Kirsher return -EINVAL; 3341adfc5217SJeff Kirsher } 3342adfc5217SJeff Kirsher 3343adfc5217SJeff Kirsher list_del(&cmd_pos->link); 3344adfc5217SJeff Kirsher kfree(cmd_pos); 3345adfc5217SJeff Kirsher 3346adfc5217SJeff Kirsher return cnt; 3347adfc5217SJeff Kirsher } 3348adfc5217SJeff Kirsher 3349adfc5217SJeff Kirsher /** 3350adfc5217SJeff Kirsher * bnx2x_get_fw_mac_addr - revert the bnx2x_set_fw_mac_addr(). 3351adfc5217SJeff Kirsher * 3352adfc5217SJeff Kirsher * @fw_hi: 3353adfc5217SJeff Kirsher * @fw_mid: 3354adfc5217SJeff Kirsher * @fw_lo: 3355adfc5217SJeff Kirsher * @mac: 3356adfc5217SJeff Kirsher */ 3357adfc5217SJeff Kirsher static inline void bnx2x_get_fw_mac_addr(__le16 *fw_hi, __le16 *fw_mid, 3358adfc5217SJeff Kirsher __le16 *fw_lo, u8 *mac) 3359adfc5217SJeff Kirsher { 3360adfc5217SJeff Kirsher mac[1] = ((u8 *)fw_hi)[0]; 3361adfc5217SJeff Kirsher mac[0] = ((u8 *)fw_hi)[1]; 3362adfc5217SJeff Kirsher mac[3] = ((u8 *)fw_mid)[0]; 3363adfc5217SJeff Kirsher mac[2] = ((u8 *)fw_mid)[1]; 3364adfc5217SJeff Kirsher mac[5] = ((u8 *)fw_lo)[0]; 3365adfc5217SJeff Kirsher mac[4] = ((u8 *)fw_lo)[1]; 3366adfc5217SJeff Kirsher } 3367adfc5217SJeff Kirsher 3368adfc5217SJeff Kirsher /** 3369adfc5217SJeff Kirsher * bnx2x_mcast_refresh_registry_e1 - 3370adfc5217SJeff Kirsher * 3371adfc5217SJeff Kirsher * @bp: device handle 3372adfc5217SJeff Kirsher * @cnt: 3373adfc5217SJeff Kirsher * 3374adfc5217SJeff Kirsher * Check the ramrod data first entry flag to see if it's a DELETE or ADD command 3375adfc5217SJeff Kirsher * and update the registry correspondingly: if ADD - allocate a memory and add 3376adfc5217SJeff Kirsher * the entries to the registry (list), if DELETE - clear the registry and free 3377adfc5217SJeff Kirsher * the memory. 3378adfc5217SJeff Kirsher */ 3379adfc5217SJeff Kirsher static inline int bnx2x_mcast_refresh_registry_e1(struct bnx2x *bp, 3380adfc5217SJeff Kirsher struct bnx2x_mcast_obj *o) 3381adfc5217SJeff Kirsher { 3382adfc5217SJeff Kirsher struct bnx2x_raw_obj *raw = &o->raw; 3383adfc5217SJeff Kirsher struct bnx2x_mcast_mac_elem *elem; 3384adfc5217SJeff Kirsher struct mac_configuration_cmd *data = 3385adfc5217SJeff Kirsher (struct mac_configuration_cmd *)(raw->rdata); 3386adfc5217SJeff Kirsher 3387adfc5217SJeff Kirsher /* If first entry contains a SET bit - the command was ADD, 3388adfc5217SJeff Kirsher * otherwise - DEL_ALL 3389adfc5217SJeff Kirsher */ 3390adfc5217SJeff Kirsher if (GET_FLAG(data->config_table[0].flags, 3391adfc5217SJeff Kirsher MAC_CONFIGURATION_ENTRY_ACTION_TYPE)) { 3392adfc5217SJeff Kirsher int i, len = data->hdr.length; 3393adfc5217SJeff Kirsher 3394adfc5217SJeff Kirsher /* Break if it was a RESTORE command */ 3395adfc5217SJeff Kirsher if (!list_empty(&o->registry.exact_match.macs)) 3396adfc5217SJeff Kirsher return 0; 3397adfc5217SJeff Kirsher 339801e23742SThomas Meyer elem = kcalloc(len, sizeof(*elem), GFP_ATOMIC); 3399adfc5217SJeff Kirsher if (!elem) { 3400adfc5217SJeff Kirsher BNX2X_ERR("Failed to allocate registry memory\n"); 3401adfc5217SJeff Kirsher return -ENOMEM; 3402adfc5217SJeff Kirsher } 3403adfc5217SJeff Kirsher 3404adfc5217SJeff Kirsher for (i = 0; i < len; i++, elem++) { 3405adfc5217SJeff Kirsher bnx2x_get_fw_mac_addr( 3406adfc5217SJeff Kirsher &data->config_table[i].msb_mac_addr, 3407adfc5217SJeff Kirsher &data->config_table[i].middle_mac_addr, 3408adfc5217SJeff Kirsher &data->config_table[i].lsb_mac_addr, 3409adfc5217SJeff Kirsher elem->mac); 34100f9dad10SJoe Perches DP(BNX2X_MSG_SP, "Adding registry entry for [%pM]\n", 34110f9dad10SJoe Perches elem->mac); 3412adfc5217SJeff Kirsher list_add_tail(&elem->link, 3413adfc5217SJeff Kirsher &o->registry.exact_match.macs); 3414adfc5217SJeff Kirsher } 3415adfc5217SJeff Kirsher } else { 3416adfc5217SJeff Kirsher elem = list_first_entry(&o->registry.exact_match.macs, 3417adfc5217SJeff Kirsher struct bnx2x_mcast_mac_elem, link); 3418adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "Deleting a registry\n"); 3419adfc5217SJeff Kirsher kfree(elem); 3420adfc5217SJeff Kirsher INIT_LIST_HEAD(&o->registry.exact_match.macs); 3421adfc5217SJeff Kirsher } 3422adfc5217SJeff Kirsher 3423adfc5217SJeff Kirsher return 0; 3424adfc5217SJeff Kirsher } 3425adfc5217SJeff Kirsher 3426adfc5217SJeff Kirsher static int bnx2x_mcast_setup_e1(struct bnx2x *bp, 3427adfc5217SJeff Kirsher struct bnx2x_mcast_ramrod_params *p, 342886564c3fSYuval Mintz enum bnx2x_mcast_cmd cmd) 3429adfc5217SJeff Kirsher { 3430adfc5217SJeff Kirsher struct bnx2x_mcast_obj *o = p->mcast_obj; 3431adfc5217SJeff Kirsher struct bnx2x_raw_obj *raw = &o->raw; 3432adfc5217SJeff Kirsher struct mac_configuration_cmd *data = 3433adfc5217SJeff Kirsher (struct mac_configuration_cmd *)(raw->rdata); 3434adfc5217SJeff Kirsher int cnt = 0, i, rc; 3435adfc5217SJeff Kirsher 3436adfc5217SJeff Kirsher /* Reset the ramrod data buffer */ 3437adfc5217SJeff Kirsher memset(data, 0, sizeof(*data)); 3438adfc5217SJeff Kirsher 3439adfc5217SJeff Kirsher /* First set all entries as invalid */ 3440adfc5217SJeff Kirsher for (i = 0; i < o->max_cmd_len ; i++) 3441adfc5217SJeff Kirsher SET_FLAG(data->config_table[i].flags, 3442adfc5217SJeff Kirsher MAC_CONFIGURATION_ENTRY_ACTION_TYPE, 3443adfc5217SJeff Kirsher T_ETH_MAC_COMMAND_INVALIDATE); 3444adfc5217SJeff Kirsher 3445adfc5217SJeff Kirsher /* Handle pending commands first */ 3446adfc5217SJeff Kirsher cnt = bnx2x_mcast_handle_pending_cmds_e1(bp, p); 3447adfc5217SJeff Kirsher 3448adfc5217SJeff Kirsher /* If there are no more pending commands - clear SCHEDULED state */ 3449adfc5217SJeff Kirsher if (list_empty(&o->pending_cmds_head)) 3450adfc5217SJeff Kirsher o->clear_sched(o); 3451adfc5217SJeff Kirsher 3452adfc5217SJeff Kirsher /* The below may be true iff there were no pending commands */ 3453adfc5217SJeff Kirsher if (!cnt) 3454adfc5217SJeff Kirsher cnt = bnx2x_mcast_handle_current_cmd(bp, p, cmd, 0); 3455adfc5217SJeff Kirsher 3456adfc5217SJeff Kirsher /* For 57710 every command has o->max_cmd_len length to ensure that 3457adfc5217SJeff Kirsher * commands are done one at a time. 3458adfc5217SJeff Kirsher */ 3459adfc5217SJeff Kirsher o->total_pending_num -= o->max_cmd_len; 3460adfc5217SJeff Kirsher 3461adfc5217SJeff Kirsher /* send a ramrod */ 3462adfc5217SJeff Kirsher 3463adfc5217SJeff Kirsher WARN_ON(cnt > o->max_cmd_len); 3464adfc5217SJeff Kirsher 3465adfc5217SJeff Kirsher /* Set ramrod header (in particular, a number of entries to update) */ 3466adfc5217SJeff Kirsher bnx2x_mcast_set_rdata_hdr_e1(bp, p, (u8)cnt); 3467adfc5217SJeff Kirsher 3468adfc5217SJeff Kirsher /* update a registry: we need the registry contents to be always up 3469adfc5217SJeff Kirsher * to date in order to be able to execute a RESTORE opcode. Here 3470adfc5217SJeff Kirsher * we use the fact that for 57710 we sent one command at a time 3471adfc5217SJeff Kirsher * hence we may take the registry update out of the command handling 3472adfc5217SJeff Kirsher * and do it in a simpler way here. 3473adfc5217SJeff Kirsher */ 3474adfc5217SJeff Kirsher rc = bnx2x_mcast_refresh_registry_e1(bp, o); 3475adfc5217SJeff Kirsher if (rc) 3476adfc5217SJeff Kirsher return rc; 3477adfc5217SJeff Kirsher 347816a5fd92SYuval Mintz /* If CLEAR_ONLY was requested - don't send a ramrod and clear 3479adfc5217SJeff Kirsher * RAMROD_PENDING status immediately. 3480adfc5217SJeff Kirsher */ 3481adfc5217SJeff Kirsher if (test_bit(RAMROD_DRV_CLR_ONLY, &p->ramrod_flags)) { 3482adfc5217SJeff Kirsher raw->clear_pending(raw); 3483adfc5217SJeff Kirsher return 0; 3484adfc5217SJeff Kirsher } else { 348516a5fd92SYuval Mintz /* No need for an explicit memory barrier here as long we would 3486adfc5217SJeff Kirsher * need to ensure the ordering of writing to the SPQ element 3487adfc5217SJeff Kirsher * and updating of the SPQ producer which involves a memory 3488adfc5217SJeff Kirsher * read and we will have to put a full memory barrier there 3489adfc5217SJeff Kirsher * (inside bnx2x_sp_post()). 3490adfc5217SJeff Kirsher */ 3491adfc5217SJeff Kirsher 3492adfc5217SJeff Kirsher /* Send a ramrod */ 3493adfc5217SJeff Kirsher rc = bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_SET_MAC, raw->cid, 3494adfc5217SJeff Kirsher U64_HI(raw->rdata_mapping), 3495adfc5217SJeff Kirsher U64_LO(raw->rdata_mapping), 3496adfc5217SJeff Kirsher ETH_CONNECTION_TYPE); 3497adfc5217SJeff Kirsher if (rc) 3498adfc5217SJeff Kirsher return rc; 3499adfc5217SJeff Kirsher 3500adfc5217SJeff Kirsher /* Ramrod completion is pending */ 3501adfc5217SJeff Kirsher return 1; 3502adfc5217SJeff Kirsher } 3503adfc5217SJeff Kirsher } 3504adfc5217SJeff Kirsher 3505adfc5217SJeff Kirsher static int bnx2x_mcast_get_registry_size_exact(struct bnx2x_mcast_obj *o) 3506adfc5217SJeff Kirsher { 3507adfc5217SJeff Kirsher return o->registry.exact_match.num_macs_set; 3508adfc5217SJeff Kirsher } 3509adfc5217SJeff Kirsher 3510adfc5217SJeff Kirsher static int bnx2x_mcast_get_registry_size_aprox(struct bnx2x_mcast_obj *o) 3511adfc5217SJeff Kirsher { 3512adfc5217SJeff Kirsher return o->registry.aprox_match.num_bins_set; 3513adfc5217SJeff Kirsher } 3514adfc5217SJeff Kirsher 3515adfc5217SJeff Kirsher static void bnx2x_mcast_set_registry_size_exact(struct bnx2x_mcast_obj *o, 3516adfc5217SJeff Kirsher int n) 3517adfc5217SJeff Kirsher { 3518adfc5217SJeff Kirsher o->registry.exact_match.num_macs_set = n; 3519adfc5217SJeff Kirsher } 3520adfc5217SJeff Kirsher 3521adfc5217SJeff Kirsher static void bnx2x_mcast_set_registry_size_aprox(struct bnx2x_mcast_obj *o, 3522adfc5217SJeff Kirsher int n) 3523adfc5217SJeff Kirsher { 3524adfc5217SJeff Kirsher o->registry.aprox_match.num_bins_set = n; 3525adfc5217SJeff Kirsher } 3526adfc5217SJeff Kirsher 3527adfc5217SJeff Kirsher int bnx2x_config_mcast(struct bnx2x *bp, 3528adfc5217SJeff Kirsher struct bnx2x_mcast_ramrod_params *p, 352986564c3fSYuval Mintz enum bnx2x_mcast_cmd cmd) 3530adfc5217SJeff Kirsher { 3531adfc5217SJeff Kirsher struct bnx2x_mcast_obj *o = p->mcast_obj; 3532adfc5217SJeff Kirsher struct bnx2x_raw_obj *r = &o->raw; 3533adfc5217SJeff Kirsher int rc = 0, old_reg_size; 3534adfc5217SJeff Kirsher 3535adfc5217SJeff Kirsher /* This is needed to recover number of currently configured mcast macs 3536adfc5217SJeff Kirsher * in case of failure. 3537adfc5217SJeff Kirsher */ 3538adfc5217SJeff Kirsher old_reg_size = o->get_registry_size(o); 3539adfc5217SJeff Kirsher 3540adfc5217SJeff Kirsher /* Do some calculations and checks */ 3541adfc5217SJeff Kirsher rc = o->validate(bp, p, cmd); 3542adfc5217SJeff Kirsher if (rc) 3543adfc5217SJeff Kirsher return rc; 3544adfc5217SJeff Kirsher 3545adfc5217SJeff Kirsher /* Return if there is no work to do */ 3546adfc5217SJeff Kirsher if ((!p->mcast_list_len) && (!o->check_sched(o))) 3547adfc5217SJeff Kirsher return 0; 3548adfc5217SJeff Kirsher 354951c1a580SMerav Sicron DP(BNX2X_MSG_SP, "o->total_pending_num=%d p->mcast_list_len=%d o->max_cmd_len=%d\n", 355051c1a580SMerav Sicron o->total_pending_num, p->mcast_list_len, o->max_cmd_len); 3551adfc5217SJeff Kirsher 3552adfc5217SJeff Kirsher /* Enqueue the current command to the pending list if we can't complete 3553adfc5217SJeff Kirsher * it in the current iteration 3554adfc5217SJeff Kirsher */ 3555adfc5217SJeff Kirsher if (r->check_pending(r) || 3556adfc5217SJeff Kirsher ((o->max_cmd_len > 0) && (o->total_pending_num > o->max_cmd_len))) { 3557adfc5217SJeff Kirsher rc = o->enqueue_cmd(bp, p->mcast_obj, p, cmd); 3558adfc5217SJeff Kirsher if (rc < 0) 3559adfc5217SJeff Kirsher goto error_exit1; 3560adfc5217SJeff Kirsher 3561adfc5217SJeff Kirsher /* As long as the current command is in a command list we 3562adfc5217SJeff Kirsher * don't need to handle it separately. 3563adfc5217SJeff Kirsher */ 3564adfc5217SJeff Kirsher p->mcast_list_len = 0; 3565adfc5217SJeff Kirsher } 3566adfc5217SJeff Kirsher 3567adfc5217SJeff Kirsher if (!r->check_pending(r)) { 3568adfc5217SJeff Kirsher 3569adfc5217SJeff Kirsher /* Set 'pending' state */ 3570adfc5217SJeff Kirsher r->set_pending(r); 3571adfc5217SJeff Kirsher 3572adfc5217SJeff Kirsher /* Configure the new classification in the chip */ 3573adfc5217SJeff Kirsher rc = o->config_mcast(bp, p, cmd); 3574adfc5217SJeff Kirsher if (rc < 0) 3575adfc5217SJeff Kirsher goto error_exit2; 3576adfc5217SJeff Kirsher 3577adfc5217SJeff Kirsher /* Wait for a ramrod completion if was requested */ 3578adfc5217SJeff Kirsher if (test_bit(RAMROD_COMP_WAIT, &p->ramrod_flags)) 3579adfc5217SJeff Kirsher rc = o->wait_comp(bp, o); 3580adfc5217SJeff Kirsher } 3581adfc5217SJeff Kirsher 3582adfc5217SJeff Kirsher return rc; 3583adfc5217SJeff Kirsher 3584adfc5217SJeff Kirsher error_exit2: 3585adfc5217SJeff Kirsher r->clear_pending(r); 3586adfc5217SJeff Kirsher 3587adfc5217SJeff Kirsher error_exit1: 3588adfc5217SJeff Kirsher o->revert(bp, p, old_reg_size); 3589adfc5217SJeff Kirsher 3590adfc5217SJeff Kirsher return rc; 3591adfc5217SJeff Kirsher } 3592adfc5217SJeff Kirsher 3593adfc5217SJeff Kirsher static void bnx2x_mcast_clear_sched(struct bnx2x_mcast_obj *o) 3594adfc5217SJeff Kirsher { 3595adfc5217SJeff Kirsher smp_mb__before_clear_bit(); 3596adfc5217SJeff Kirsher clear_bit(o->sched_state, o->raw.pstate); 3597adfc5217SJeff Kirsher smp_mb__after_clear_bit(); 3598adfc5217SJeff Kirsher } 3599adfc5217SJeff Kirsher 3600adfc5217SJeff Kirsher static void bnx2x_mcast_set_sched(struct bnx2x_mcast_obj *o) 3601adfc5217SJeff Kirsher { 3602adfc5217SJeff Kirsher smp_mb__before_clear_bit(); 3603adfc5217SJeff Kirsher set_bit(o->sched_state, o->raw.pstate); 3604adfc5217SJeff Kirsher smp_mb__after_clear_bit(); 3605adfc5217SJeff Kirsher } 3606adfc5217SJeff Kirsher 3607adfc5217SJeff Kirsher static bool bnx2x_mcast_check_sched(struct bnx2x_mcast_obj *o) 3608adfc5217SJeff Kirsher { 3609adfc5217SJeff Kirsher return !!test_bit(o->sched_state, o->raw.pstate); 3610adfc5217SJeff Kirsher } 3611adfc5217SJeff Kirsher 3612adfc5217SJeff Kirsher static bool bnx2x_mcast_check_pending(struct bnx2x_mcast_obj *o) 3613adfc5217SJeff Kirsher { 3614adfc5217SJeff Kirsher return o->raw.check_pending(&o->raw) || o->check_sched(o); 3615adfc5217SJeff Kirsher } 3616adfc5217SJeff Kirsher 3617adfc5217SJeff Kirsher void bnx2x_init_mcast_obj(struct bnx2x *bp, 3618adfc5217SJeff Kirsher struct bnx2x_mcast_obj *mcast_obj, 3619adfc5217SJeff Kirsher u8 mcast_cl_id, u32 mcast_cid, u8 func_id, 3620adfc5217SJeff Kirsher u8 engine_id, void *rdata, dma_addr_t rdata_mapping, 3621adfc5217SJeff Kirsher int state, unsigned long *pstate, bnx2x_obj_type type) 3622adfc5217SJeff Kirsher { 3623adfc5217SJeff Kirsher memset(mcast_obj, 0, sizeof(*mcast_obj)); 3624adfc5217SJeff Kirsher 3625adfc5217SJeff Kirsher bnx2x_init_raw_obj(&mcast_obj->raw, mcast_cl_id, mcast_cid, func_id, 3626adfc5217SJeff Kirsher rdata, rdata_mapping, state, pstate, type); 3627adfc5217SJeff Kirsher 3628adfc5217SJeff Kirsher mcast_obj->engine_id = engine_id; 3629adfc5217SJeff Kirsher 3630adfc5217SJeff Kirsher INIT_LIST_HEAD(&mcast_obj->pending_cmds_head); 3631adfc5217SJeff Kirsher 3632adfc5217SJeff Kirsher mcast_obj->sched_state = BNX2X_FILTER_MCAST_SCHED; 3633adfc5217SJeff Kirsher mcast_obj->check_sched = bnx2x_mcast_check_sched; 3634adfc5217SJeff Kirsher mcast_obj->set_sched = bnx2x_mcast_set_sched; 3635adfc5217SJeff Kirsher mcast_obj->clear_sched = bnx2x_mcast_clear_sched; 3636adfc5217SJeff Kirsher 3637adfc5217SJeff Kirsher if (CHIP_IS_E1(bp)) { 3638adfc5217SJeff Kirsher mcast_obj->config_mcast = bnx2x_mcast_setup_e1; 3639adfc5217SJeff Kirsher mcast_obj->enqueue_cmd = bnx2x_mcast_enqueue_cmd; 3640adfc5217SJeff Kirsher mcast_obj->hdl_restore = 3641adfc5217SJeff Kirsher bnx2x_mcast_handle_restore_cmd_e1; 3642adfc5217SJeff Kirsher mcast_obj->check_pending = bnx2x_mcast_check_pending; 3643adfc5217SJeff Kirsher 3644adfc5217SJeff Kirsher if (CHIP_REV_IS_SLOW(bp)) 3645adfc5217SJeff Kirsher mcast_obj->max_cmd_len = BNX2X_MAX_EMUL_MULTI; 3646adfc5217SJeff Kirsher else 3647adfc5217SJeff Kirsher mcast_obj->max_cmd_len = BNX2X_MAX_MULTICAST; 3648adfc5217SJeff Kirsher 3649adfc5217SJeff Kirsher mcast_obj->wait_comp = bnx2x_mcast_wait; 3650adfc5217SJeff Kirsher mcast_obj->set_one_rule = bnx2x_mcast_set_one_rule_e1; 3651adfc5217SJeff Kirsher mcast_obj->validate = bnx2x_mcast_validate_e1; 3652adfc5217SJeff Kirsher mcast_obj->revert = bnx2x_mcast_revert_e1; 3653adfc5217SJeff Kirsher mcast_obj->get_registry_size = 3654adfc5217SJeff Kirsher bnx2x_mcast_get_registry_size_exact; 3655adfc5217SJeff Kirsher mcast_obj->set_registry_size = 3656adfc5217SJeff Kirsher bnx2x_mcast_set_registry_size_exact; 3657adfc5217SJeff Kirsher 3658adfc5217SJeff Kirsher /* 57710 is the only chip that uses the exact match for mcast 3659adfc5217SJeff Kirsher * at the moment. 3660adfc5217SJeff Kirsher */ 3661adfc5217SJeff Kirsher INIT_LIST_HEAD(&mcast_obj->registry.exact_match.macs); 3662adfc5217SJeff Kirsher 3663adfc5217SJeff Kirsher } else if (CHIP_IS_E1H(bp)) { 3664adfc5217SJeff Kirsher mcast_obj->config_mcast = bnx2x_mcast_setup_e1h; 3665adfc5217SJeff Kirsher mcast_obj->enqueue_cmd = NULL; 3666adfc5217SJeff Kirsher mcast_obj->hdl_restore = NULL; 3667adfc5217SJeff Kirsher mcast_obj->check_pending = bnx2x_mcast_check_pending; 3668adfc5217SJeff Kirsher 3669adfc5217SJeff Kirsher /* 57711 doesn't send a ramrod, so it has unlimited credit 3670adfc5217SJeff Kirsher * for one command. 3671adfc5217SJeff Kirsher */ 3672adfc5217SJeff Kirsher mcast_obj->max_cmd_len = -1; 3673adfc5217SJeff Kirsher mcast_obj->wait_comp = bnx2x_mcast_wait; 3674adfc5217SJeff Kirsher mcast_obj->set_one_rule = NULL; 3675adfc5217SJeff Kirsher mcast_obj->validate = bnx2x_mcast_validate_e1h; 3676adfc5217SJeff Kirsher mcast_obj->revert = bnx2x_mcast_revert_e1h; 3677adfc5217SJeff Kirsher mcast_obj->get_registry_size = 3678adfc5217SJeff Kirsher bnx2x_mcast_get_registry_size_aprox; 3679adfc5217SJeff Kirsher mcast_obj->set_registry_size = 3680adfc5217SJeff Kirsher bnx2x_mcast_set_registry_size_aprox; 3681adfc5217SJeff Kirsher } else { 3682adfc5217SJeff Kirsher mcast_obj->config_mcast = bnx2x_mcast_setup_e2; 3683adfc5217SJeff Kirsher mcast_obj->enqueue_cmd = bnx2x_mcast_enqueue_cmd; 3684adfc5217SJeff Kirsher mcast_obj->hdl_restore = 3685adfc5217SJeff Kirsher bnx2x_mcast_handle_restore_cmd_e2; 3686adfc5217SJeff Kirsher mcast_obj->check_pending = bnx2x_mcast_check_pending; 3687adfc5217SJeff Kirsher /* TODO: There should be a proper HSI define for this number!!! 3688adfc5217SJeff Kirsher */ 3689adfc5217SJeff Kirsher mcast_obj->max_cmd_len = 16; 3690adfc5217SJeff Kirsher mcast_obj->wait_comp = bnx2x_mcast_wait; 3691adfc5217SJeff Kirsher mcast_obj->set_one_rule = bnx2x_mcast_set_one_rule_e2; 3692adfc5217SJeff Kirsher mcast_obj->validate = bnx2x_mcast_validate_e2; 3693adfc5217SJeff Kirsher mcast_obj->revert = bnx2x_mcast_revert_e2; 3694adfc5217SJeff Kirsher mcast_obj->get_registry_size = 3695adfc5217SJeff Kirsher bnx2x_mcast_get_registry_size_aprox; 3696adfc5217SJeff Kirsher mcast_obj->set_registry_size = 3697adfc5217SJeff Kirsher bnx2x_mcast_set_registry_size_aprox; 3698adfc5217SJeff Kirsher } 3699adfc5217SJeff Kirsher } 3700adfc5217SJeff Kirsher 3701adfc5217SJeff Kirsher /*************************** Credit handling **********************************/ 3702adfc5217SJeff Kirsher 3703adfc5217SJeff Kirsher /** 3704adfc5217SJeff Kirsher * atomic_add_ifless - add if the result is less than a given value. 3705adfc5217SJeff Kirsher * 3706adfc5217SJeff Kirsher * @v: pointer of type atomic_t 3707adfc5217SJeff Kirsher * @a: the amount to add to v... 3708adfc5217SJeff Kirsher * @u: ...if (v + a) is less than u. 3709adfc5217SJeff Kirsher * 3710adfc5217SJeff Kirsher * returns true if (v + a) was less than u, and false otherwise. 3711adfc5217SJeff Kirsher * 3712adfc5217SJeff Kirsher */ 3713adfc5217SJeff Kirsher static inline bool __atomic_add_ifless(atomic_t *v, int a, int u) 3714adfc5217SJeff Kirsher { 3715adfc5217SJeff Kirsher int c, old; 3716adfc5217SJeff Kirsher 3717adfc5217SJeff Kirsher c = atomic_read(v); 3718adfc5217SJeff Kirsher for (;;) { 3719adfc5217SJeff Kirsher if (unlikely(c + a >= u)) 3720adfc5217SJeff Kirsher return false; 3721adfc5217SJeff Kirsher 3722adfc5217SJeff Kirsher old = atomic_cmpxchg((v), c, c + a); 3723adfc5217SJeff Kirsher if (likely(old == c)) 3724adfc5217SJeff Kirsher break; 3725adfc5217SJeff Kirsher c = old; 3726adfc5217SJeff Kirsher } 3727adfc5217SJeff Kirsher 3728adfc5217SJeff Kirsher return true; 3729adfc5217SJeff Kirsher } 3730adfc5217SJeff Kirsher 3731adfc5217SJeff Kirsher /** 3732adfc5217SJeff Kirsher * atomic_dec_ifmoe - dec if the result is more or equal than a given value. 3733adfc5217SJeff Kirsher * 3734adfc5217SJeff Kirsher * @v: pointer of type atomic_t 3735adfc5217SJeff Kirsher * @a: the amount to dec from v... 3736adfc5217SJeff Kirsher * @u: ...if (v - a) is more or equal than u. 3737adfc5217SJeff Kirsher * 3738adfc5217SJeff Kirsher * returns true if (v - a) was more or equal than u, and false 3739adfc5217SJeff Kirsher * otherwise. 3740adfc5217SJeff Kirsher */ 3741adfc5217SJeff Kirsher static inline bool __atomic_dec_ifmoe(atomic_t *v, int a, int u) 3742adfc5217SJeff Kirsher { 3743adfc5217SJeff Kirsher int c, old; 3744adfc5217SJeff Kirsher 3745adfc5217SJeff Kirsher c = atomic_read(v); 3746adfc5217SJeff Kirsher for (;;) { 3747adfc5217SJeff Kirsher if (unlikely(c - a < u)) 3748adfc5217SJeff Kirsher return false; 3749adfc5217SJeff Kirsher 3750adfc5217SJeff Kirsher old = atomic_cmpxchg((v), c, c - a); 3751adfc5217SJeff Kirsher if (likely(old == c)) 3752adfc5217SJeff Kirsher break; 3753adfc5217SJeff Kirsher c = old; 3754adfc5217SJeff Kirsher } 3755adfc5217SJeff Kirsher 3756adfc5217SJeff Kirsher return true; 3757adfc5217SJeff Kirsher } 3758adfc5217SJeff Kirsher 3759adfc5217SJeff Kirsher static bool bnx2x_credit_pool_get(struct bnx2x_credit_pool_obj *o, int cnt) 3760adfc5217SJeff Kirsher { 3761adfc5217SJeff Kirsher bool rc; 3762adfc5217SJeff Kirsher 3763adfc5217SJeff Kirsher smp_mb(); 3764adfc5217SJeff Kirsher rc = __atomic_dec_ifmoe(&o->credit, cnt, 0); 3765adfc5217SJeff Kirsher smp_mb(); 3766adfc5217SJeff Kirsher 3767adfc5217SJeff Kirsher return rc; 3768adfc5217SJeff Kirsher } 3769adfc5217SJeff Kirsher 3770adfc5217SJeff Kirsher static bool bnx2x_credit_pool_put(struct bnx2x_credit_pool_obj *o, int cnt) 3771adfc5217SJeff Kirsher { 3772adfc5217SJeff Kirsher bool rc; 3773adfc5217SJeff Kirsher 3774adfc5217SJeff Kirsher smp_mb(); 3775adfc5217SJeff Kirsher 3776adfc5217SJeff Kirsher /* Don't let to refill if credit + cnt > pool_sz */ 3777adfc5217SJeff Kirsher rc = __atomic_add_ifless(&o->credit, cnt, o->pool_sz + 1); 3778adfc5217SJeff Kirsher 3779adfc5217SJeff Kirsher smp_mb(); 3780adfc5217SJeff Kirsher 3781adfc5217SJeff Kirsher return rc; 3782adfc5217SJeff Kirsher } 3783adfc5217SJeff Kirsher 3784adfc5217SJeff Kirsher static int bnx2x_credit_pool_check(struct bnx2x_credit_pool_obj *o) 3785adfc5217SJeff Kirsher { 3786adfc5217SJeff Kirsher int cur_credit; 3787adfc5217SJeff Kirsher 3788adfc5217SJeff Kirsher smp_mb(); 3789adfc5217SJeff Kirsher cur_credit = atomic_read(&o->credit); 3790adfc5217SJeff Kirsher 3791adfc5217SJeff Kirsher return cur_credit; 3792adfc5217SJeff Kirsher } 3793adfc5217SJeff Kirsher 3794adfc5217SJeff Kirsher static bool bnx2x_credit_pool_always_true(struct bnx2x_credit_pool_obj *o, 3795adfc5217SJeff Kirsher int cnt) 3796adfc5217SJeff Kirsher { 3797adfc5217SJeff Kirsher return true; 3798adfc5217SJeff Kirsher } 3799adfc5217SJeff Kirsher 3800adfc5217SJeff Kirsher static bool bnx2x_credit_pool_get_entry( 3801adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *o, 3802adfc5217SJeff Kirsher int *offset) 3803adfc5217SJeff Kirsher { 3804adfc5217SJeff Kirsher int idx, vec, i; 3805adfc5217SJeff Kirsher 3806adfc5217SJeff Kirsher *offset = -1; 3807adfc5217SJeff Kirsher 3808adfc5217SJeff Kirsher /* Find "internal cam-offset" then add to base for this object... */ 3809adfc5217SJeff Kirsher for (vec = 0; vec < BNX2X_POOL_VEC_SIZE; vec++) { 3810adfc5217SJeff Kirsher 3811adfc5217SJeff Kirsher /* Skip the current vector if there are no free entries in it */ 3812adfc5217SJeff Kirsher if (!o->pool_mirror[vec]) 3813adfc5217SJeff Kirsher continue; 3814adfc5217SJeff Kirsher 3815adfc5217SJeff Kirsher /* If we've got here we are going to find a free entry */ 3816c54e9bd3SDmitry Kravkov for (idx = vec * BIT_VEC64_ELEM_SZ, i = 0; 3817adfc5217SJeff Kirsher i < BIT_VEC64_ELEM_SZ; idx++, i++) 3818adfc5217SJeff Kirsher 3819adfc5217SJeff Kirsher if (BIT_VEC64_TEST_BIT(o->pool_mirror, idx)) { 3820adfc5217SJeff Kirsher /* Got one!! */ 3821adfc5217SJeff Kirsher BIT_VEC64_CLEAR_BIT(o->pool_mirror, idx); 3822adfc5217SJeff Kirsher *offset = o->base_pool_offset + idx; 3823adfc5217SJeff Kirsher return true; 3824adfc5217SJeff Kirsher } 3825adfc5217SJeff Kirsher } 3826adfc5217SJeff Kirsher 3827adfc5217SJeff Kirsher return false; 3828adfc5217SJeff Kirsher } 3829adfc5217SJeff Kirsher 3830adfc5217SJeff Kirsher static bool bnx2x_credit_pool_put_entry( 3831adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *o, 3832adfc5217SJeff Kirsher int offset) 3833adfc5217SJeff Kirsher { 3834adfc5217SJeff Kirsher if (offset < o->base_pool_offset) 3835adfc5217SJeff Kirsher return false; 3836adfc5217SJeff Kirsher 3837adfc5217SJeff Kirsher offset -= o->base_pool_offset; 3838adfc5217SJeff Kirsher 3839adfc5217SJeff Kirsher if (offset >= o->pool_sz) 3840adfc5217SJeff Kirsher return false; 3841adfc5217SJeff Kirsher 3842adfc5217SJeff Kirsher /* Return the entry to the pool */ 3843adfc5217SJeff Kirsher BIT_VEC64_SET_BIT(o->pool_mirror, offset); 3844adfc5217SJeff Kirsher 3845adfc5217SJeff Kirsher return true; 3846adfc5217SJeff Kirsher } 3847adfc5217SJeff Kirsher 3848adfc5217SJeff Kirsher static bool bnx2x_credit_pool_put_entry_always_true( 3849adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *o, 3850adfc5217SJeff Kirsher int offset) 3851adfc5217SJeff Kirsher { 3852adfc5217SJeff Kirsher return true; 3853adfc5217SJeff Kirsher } 3854adfc5217SJeff Kirsher 3855adfc5217SJeff Kirsher static bool bnx2x_credit_pool_get_entry_always_true( 3856adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *o, 3857adfc5217SJeff Kirsher int *offset) 3858adfc5217SJeff Kirsher { 3859adfc5217SJeff Kirsher *offset = -1; 3860adfc5217SJeff Kirsher return true; 3861adfc5217SJeff Kirsher } 3862adfc5217SJeff Kirsher /** 3863adfc5217SJeff Kirsher * bnx2x_init_credit_pool - initialize credit pool internals. 3864adfc5217SJeff Kirsher * 3865adfc5217SJeff Kirsher * @p: 3866adfc5217SJeff Kirsher * @base: Base entry in the CAM to use. 3867adfc5217SJeff Kirsher * @credit: pool size. 3868adfc5217SJeff Kirsher * 3869adfc5217SJeff Kirsher * If base is negative no CAM entries handling will be performed. 3870adfc5217SJeff Kirsher * If credit is negative pool operations will always succeed (unlimited pool). 3871adfc5217SJeff Kirsher * 3872adfc5217SJeff Kirsher */ 3873adfc5217SJeff Kirsher static inline void bnx2x_init_credit_pool(struct bnx2x_credit_pool_obj *p, 3874adfc5217SJeff Kirsher int base, int credit) 3875adfc5217SJeff Kirsher { 3876adfc5217SJeff Kirsher /* Zero the object first */ 3877adfc5217SJeff Kirsher memset(p, 0, sizeof(*p)); 3878adfc5217SJeff Kirsher 3879adfc5217SJeff Kirsher /* Set the table to all 1s */ 3880adfc5217SJeff Kirsher memset(&p->pool_mirror, 0xff, sizeof(p->pool_mirror)); 3881adfc5217SJeff Kirsher 3882adfc5217SJeff Kirsher /* Init a pool as full */ 3883adfc5217SJeff Kirsher atomic_set(&p->credit, credit); 3884adfc5217SJeff Kirsher 3885adfc5217SJeff Kirsher /* The total poll size */ 3886adfc5217SJeff Kirsher p->pool_sz = credit; 3887adfc5217SJeff Kirsher 3888adfc5217SJeff Kirsher p->base_pool_offset = base; 3889adfc5217SJeff Kirsher 3890adfc5217SJeff Kirsher /* Commit the change */ 3891adfc5217SJeff Kirsher smp_mb(); 3892adfc5217SJeff Kirsher 3893adfc5217SJeff Kirsher p->check = bnx2x_credit_pool_check; 3894adfc5217SJeff Kirsher 3895adfc5217SJeff Kirsher /* if pool credit is negative - disable the checks */ 3896adfc5217SJeff Kirsher if (credit >= 0) { 3897adfc5217SJeff Kirsher p->put = bnx2x_credit_pool_put; 3898adfc5217SJeff Kirsher p->get = bnx2x_credit_pool_get; 3899adfc5217SJeff Kirsher p->put_entry = bnx2x_credit_pool_put_entry; 3900adfc5217SJeff Kirsher p->get_entry = bnx2x_credit_pool_get_entry; 3901adfc5217SJeff Kirsher } else { 3902adfc5217SJeff Kirsher p->put = bnx2x_credit_pool_always_true; 3903adfc5217SJeff Kirsher p->get = bnx2x_credit_pool_always_true; 3904adfc5217SJeff Kirsher p->put_entry = bnx2x_credit_pool_put_entry_always_true; 3905adfc5217SJeff Kirsher p->get_entry = bnx2x_credit_pool_get_entry_always_true; 3906adfc5217SJeff Kirsher } 3907adfc5217SJeff Kirsher 3908adfc5217SJeff Kirsher /* If base is negative - disable entries handling */ 3909adfc5217SJeff Kirsher if (base < 0) { 3910adfc5217SJeff Kirsher p->put_entry = bnx2x_credit_pool_put_entry_always_true; 3911adfc5217SJeff Kirsher p->get_entry = bnx2x_credit_pool_get_entry_always_true; 3912adfc5217SJeff Kirsher } 3913adfc5217SJeff Kirsher } 3914adfc5217SJeff Kirsher 3915adfc5217SJeff Kirsher void bnx2x_init_mac_credit_pool(struct bnx2x *bp, 3916adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *p, u8 func_id, 3917adfc5217SJeff Kirsher u8 func_num) 3918adfc5217SJeff Kirsher { 3919adfc5217SJeff Kirsher /* TODO: this will be defined in consts as well... */ 3920adfc5217SJeff Kirsher #define BNX2X_CAM_SIZE_EMUL 5 3921adfc5217SJeff Kirsher 3922adfc5217SJeff Kirsher int cam_sz; 3923adfc5217SJeff Kirsher 3924adfc5217SJeff Kirsher if (CHIP_IS_E1(bp)) { 3925adfc5217SJeff Kirsher /* In E1, Multicast is saved in cam... */ 3926adfc5217SJeff Kirsher if (!CHIP_REV_IS_SLOW(bp)) 3927adfc5217SJeff Kirsher cam_sz = (MAX_MAC_CREDIT_E1 / 2) - BNX2X_MAX_MULTICAST; 3928adfc5217SJeff Kirsher else 3929adfc5217SJeff Kirsher cam_sz = BNX2X_CAM_SIZE_EMUL - BNX2X_MAX_EMUL_MULTI; 3930adfc5217SJeff Kirsher 3931adfc5217SJeff Kirsher bnx2x_init_credit_pool(p, func_id * cam_sz, cam_sz); 3932adfc5217SJeff Kirsher 3933adfc5217SJeff Kirsher } else if (CHIP_IS_E1H(bp)) { 3934adfc5217SJeff Kirsher /* CAM credit is equaly divided between all active functions 3935adfc5217SJeff Kirsher * on the PORT!. 3936adfc5217SJeff Kirsher */ 3937adfc5217SJeff Kirsher if ((func_num > 0)) { 3938adfc5217SJeff Kirsher if (!CHIP_REV_IS_SLOW(bp)) 3939adfc5217SJeff Kirsher cam_sz = (MAX_MAC_CREDIT_E1H / (2*func_num)); 3940adfc5217SJeff Kirsher else 3941adfc5217SJeff Kirsher cam_sz = BNX2X_CAM_SIZE_EMUL; 3942adfc5217SJeff Kirsher bnx2x_init_credit_pool(p, func_id * cam_sz, cam_sz); 3943adfc5217SJeff Kirsher } else { 3944adfc5217SJeff Kirsher /* this should never happen! Block MAC operations. */ 3945adfc5217SJeff Kirsher bnx2x_init_credit_pool(p, 0, 0); 3946adfc5217SJeff Kirsher } 3947adfc5217SJeff Kirsher 3948adfc5217SJeff Kirsher } else { 3949adfc5217SJeff Kirsher 395016a5fd92SYuval Mintz /* CAM credit is equaly divided between all active functions 3951adfc5217SJeff Kirsher * on the PATH. 3952adfc5217SJeff Kirsher */ 3953adfc5217SJeff Kirsher if ((func_num > 0)) { 3954adfc5217SJeff Kirsher if (!CHIP_REV_IS_SLOW(bp)) 3955adfc5217SJeff Kirsher cam_sz = (MAX_MAC_CREDIT_E2 / func_num); 3956adfc5217SJeff Kirsher else 3957adfc5217SJeff Kirsher cam_sz = BNX2X_CAM_SIZE_EMUL; 3958adfc5217SJeff Kirsher 395916a5fd92SYuval Mintz /* No need for CAM entries handling for 57712 and 3960adfc5217SJeff Kirsher * newer. 3961adfc5217SJeff Kirsher */ 3962adfc5217SJeff Kirsher bnx2x_init_credit_pool(p, -1, cam_sz); 3963adfc5217SJeff Kirsher } else { 3964adfc5217SJeff Kirsher /* this should never happen! Block MAC operations. */ 3965adfc5217SJeff Kirsher bnx2x_init_credit_pool(p, 0, 0); 3966adfc5217SJeff Kirsher } 3967adfc5217SJeff Kirsher } 3968adfc5217SJeff Kirsher } 3969adfc5217SJeff Kirsher 3970adfc5217SJeff Kirsher void bnx2x_init_vlan_credit_pool(struct bnx2x *bp, 3971adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj *p, 3972adfc5217SJeff Kirsher u8 func_id, 3973adfc5217SJeff Kirsher u8 func_num) 3974adfc5217SJeff Kirsher { 3975adfc5217SJeff Kirsher if (CHIP_IS_E1x(bp)) { 397616a5fd92SYuval Mintz /* There is no VLAN credit in HW on 57710 and 57711 only 3977adfc5217SJeff Kirsher * MAC / MAC-VLAN can be set 3978adfc5217SJeff Kirsher */ 3979adfc5217SJeff Kirsher bnx2x_init_credit_pool(p, 0, -1); 3980adfc5217SJeff Kirsher } else { 398116a5fd92SYuval Mintz /* CAM credit is equally divided between all active functions 3982adfc5217SJeff Kirsher * on the PATH. 3983adfc5217SJeff Kirsher */ 3984adfc5217SJeff Kirsher if (func_num > 0) { 3985adfc5217SJeff Kirsher int credit = MAX_VLAN_CREDIT_E2 / func_num; 3986adfc5217SJeff Kirsher bnx2x_init_credit_pool(p, func_id * credit, credit); 3987adfc5217SJeff Kirsher } else 3988adfc5217SJeff Kirsher /* this should never happen! Block VLAN operations. */ 3989adfc5217SJeff Kirsher bnx2x_init_credit_pool(p, 0, 0); 3990adfc5217SJeff Kirsher } 3991adfc5217SJeff Kirsher } 3992adfc5217SJeff Kirsher 3993adfc5217SJeff Kirsher /****************** RSS Configuration ******************/ 3994adfc5217SJeff Kirsher /** 3995adfc5217SJeff Kirsher * bnx2x_debug_print_ind_table - prints the indirection table configuration. 3996adfc5217SJeff Kirsher * 399716a5fd92SYuval Mintz * @bp: driver handle 3998adfc5217SJeff Kirsher * @p: pointer to rss configuration 3999adfc5217SJeff Kirsher * 4000adfc5217SJeff Kirsher * Prints it when NETIF_MSG_IFUP debug level is configured. 4001adfc5217SJeff Kirsher */ 4002adfc5217SJeff Kirsher static inline void bnx2x_debug_print_ind_table(struct bnx2x *bp, 4003adfc5217SJeff Kirsher struct bnx2x_config_rss_params *p) 4004adfc5217SJeff Kirsher { 4005adfc5217SJeff Kirsher int i; 4006adfc5217SJeff Kirsher 4007adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "Setting indirection table to:\n"); 4008adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "0x0000: "); 4009adfc5217SJeff Kirsher for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++) { 4010adfc5217SJeff Kirsher DP_CONT(BNX2X_MSG_SP, "0x%02x ", p->ind_table[i]); 4011adfc5217SJeff Kirsher 4012adfc5217SJeff Kirsher /* Print 4 bytes in a line */ 4013adfc5217SJeff Kirsher if ((i + 1 < T_ETH_INDIRECTION_TABLE_SIZE) && 4014adfc5217SJeff Kirsher (((i + 1) & 0x3) == 0)) { 4015adfc5217SJeff Kirsher DP_CONT(BNX2X_MSG_SP, "\n"); 4016adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "0x%04x: ", i + 1); 4017adfc5217SJeff Kirsher } 4018adfc5217SJeff Kirsher } 4019adfc5217SJeff Kirsher 4020adfc5217SJeff Kirsher DP_CONT(BNX2X_MSG_SP, "\n"); 4021adfc5217SJeff Kirsher } 4022adfc5217SJeff Kirsher 4023adfc5217SJeff Kirsher /** 4024adfc5217SJeff Kirsher * bnx2x_setup_rss - configure RSS 4025adfc5217SJeff Kirsher * 4026adfc5217SJeff Kirsher * @bp: device handle 4027adfc5217SJeff Kirsher * @p: rss configuration 4028adfc5217SJeff Kirsher * 4029adfc5217SJeff Kirsher * sends on UPDATE ramrod for that matter. 4030adfc5217SJeff Kirsher */ 4031adfc5217SJeff Kirsher static int bnx2x_setup_rss(struct bnx2x *bp, 4032adfc5217SJeff Kirsher struct bnx2x_config_rss_params *p) 4033adfc5217SJeff Kirsher { 4034adfc5217SJeff Kirsher struct bnx2x_rss_config_obj *o = p->rss_obj; 4035adfc5217SJeff Kirsher struct bnx2x_raw_obj *r = &o->raw; 4036adfc5217SJeff Kirsher struct eth_rss_update_ramrod_data *data = 4037adfc5217SJeff Kirsher (struct eth_rss_update_ramrod_data *)(r->rdata); 4038adfc5217SJeff Kirsher u8 rss_mode = 0; 4039adfc5217SJeff Kirsher int rc; 4040adfc5217SJeff Kirsher 4041adfc5217SJeff Kirsher memset(data, 0, sizeof(*data)); 4042adfc5217SJeff Kirsher 4043adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "Configuring RSS\n"); 4044adfc5217SJeff Kirsher 4045adfc5217SJeff Kirsher /* Set an echo field */ 404686564c3fSYuval Mintz data->echo = cpu_to_le32((r->cid & BNX2X_SWCID_MASK) | 404786564c3fSYuval Mintz (r->state << BNX2X_SWCID_SHIFT)); 4048adfc5217SJeff Kirsher 4049adfc5217SJeff Kirsher /* RSS mode */ 4050adfc5217SJeff Kirsher if (test_bit(BNX2X_RSS_MODE_DISABLED, &p->rss_flags)) 4051adfc5217SJeff Kirsher rss_mode = ETH_RSS_MODE_DISABLED; 4052adfc5217SJeff Kirsher else if (test_bit(BNX2X_RSS_MODE_REGULAR, &p->rss_flags)) 4053adfc5217SJeff Kirsher rss_mode = ETH_RSS_MODE_REGULAR; 4054adfc5217SJeff Kirsher 4055adfc5217SJeff Kirsher data->rss_mode = rss_mode; 4056adfc5217SJeff Kirsher 4057adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "rss_mode=%d\n", rss_mode); 4058adfc5217SJeff Kirsher 4059adfc5217SJeff Kirsher /* RSS capabilities */ 4060adfc5217SJeff Kirsher if (test_bit(BNX2X_RSS_IPV4, &p->rss_flags)) 4061adfc5217SJeff Kirsher data->capabilities |= 4062adfc5217SJeff Kirsher ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY; 4063adfc5217SJeff Kirsher 4064adfc5217SJeff Kirsher if (test_bit(BNX2X_RSS_IPV4_TCP, &p->rss_flags)) 4065adfc5217SJeff Kirsher data->capabilities |= 4066adfc5217SJeff Kirsher ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY; 4067adfc5217SJeff Kirsher 40685d317c6aSMerav Sicron if (test_bit(BNX2X_RSS_IPV4_UDP, &p->rss_flags)) 40695d317c6aSMerav Sicron data->capabilities |= 40705d317c6aSMerav Sicron ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY; 40715d317c6aSMerav Sicron 4072adfc5217SJeff Kirsher if (test_bit(BNX2X_RSS_IPV6, &p->rss_flags)) 4073adfc5217SJeff Kirsher data->capabilities |= 4074adfc5217SJeff Kirsher ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY; 4075adfc5217SJeff Kirsher 4076adfc5217SJeff Kirsher if (test_bit(BNX2X_RSS_IPV6_TCP, &p->rss_flags)) 4077adfc5217SJeff Kirsher data->capabilities |= 4078adfc5217SJeff Kirsher ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY; 4079adfc5217SJeff Kirsher 40805d317c6aSMerav Sicron if (test_bit(BNX2X_RSS_IPV6_UDP, &p->rss_flags)) 40815d317c6aSMerav Sicron data->capabilities |= 40825d317c6aSMerav Sicron ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY; 40835d317c6aSMerav Sicron 4084adfc5217SJeff Kirsher /* Hashing mask */ 4085adfc5217SJeff Kirsher data->rss_result_mask = p->rss_result_mask; 4086adfc5217SJeff Kirsher 4087adfc5217SJeff Kirsher /* RSS engine ID */ 4088adfc5217SJeff Kirsher data->rss_engine_id = o->engine_id; 4089adfc5217SJeff Kirsher 4090adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "rss_engine_id=%d\n", data->rss_engine_id); 4091adfc5217SJeff Kirsher 4092adfc5217SJeff Kirsher /* Indirection table */ 4093adfc5217SJeff Kirsher memcpy(data->indirection_table, p->ind_table, 4094adfc5217SJeff Kirsher T_ETH_INDIRECTION_TABLE_SIZE); 4095adfc5217SJeff Kirsher 4096adfc5217SJeff Kirsher /* Remember the last configuration */ 4097adfc5217SJeff Kirsher memcpy(o->ind_table, p->ind_table, T_ETH_INDIRECTION_TABLE_SIZE); 4098adfc5217SJeff Kirsher 4099adfc5217SJeff Kirsher /* Print the indirection table */ 4100adfc5217SJeff Kirsher if (netif_msg_ifup(bp)) 4101adfc5217SJeff Kirsher bnx2x_debug_print_ind_table(bp, p); 4102adfc5217SJeff Kirsher 4103adfc5217SJeff Kirsher /* RSS keys */ 4104adfc5217SJeff Kirsher if (test_bit(BNX2X_RSS_SET_SRCH, &p->rss_flags)) { 4105adfc5217SJeff Kirsher memcpy(&data->rss_key[0], &p->rss_key[0], 4106adfc5217SJeff Kirsher sizeof(data->rss_key)); 4107adfc5217SJeff Kirsher data->capabilities |= ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY; 4108adfc5217SJeff Kirsher } 4109adfc5217SJeff Kirsher 411016a5fd92SYuval Mintz /* No need for an explicit memory barrier here as long we would 4111adfc5217SJeff Kirsher * need to ensure the ordering of writing to the SPQ element 4112adfc5217SJeff Kirsher * and updating of the SPQ producer which involves a memory 4113adfc5217SJeff Kirsher * read and we will have to put a full memory barrier there 4114adfc5217SJeff Kirsher * (inside bnx2x_sp_post()). 4115adfc5217SJeff Kirsher */ 4116adfc5217SJeff Kirsher 4117adfc5217SJeff Kirsher /* Send a ramrod */ 4118adfc5217SJeff Kirsher rc = bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_RSS_UPDATE, r->cid, 4119adfc5217SJeff Kirsher U64_HI(r->rdata_mapping), 4120adfc5217SJeff Kirsher U64_LO(r->rdata_mapping), 4121adfc5217SJeff Kirsher ETH_CONNECTION_TYPE); 4122adfc5217SJeff Kirsher 4123adfc5217SJeff Kirsher if (rc < 0) 4124adfc5217SJeff Kirsher return rc; 4125adfc5217SJeff Kirsher 4126adfc5217SJeff Kirsher return 1; 4127adfc5217SJeff Kirsher } 4128adfc5217SJeff Kirsher 4129adfc5217SJeff Kirsher void bnx2x_get_rss_ind_table(struct bnx2x_rss_config_obj *rss_obj, 4130adfc5217SJeff Kirsher u8 *ind_table) 4131adfc5217SJeff Kirsher { 4132adfc5217SJeff Kirsher memcpy(ind_table, rss_obj->ind_table, sizeof(rss_obj->ind_table)); 4133adfc5217SJeff Kirsher } 4134adfc5217SJeff Kirsher 4135adfc5217SJeff Kirsher int bnx2x_config_rss(struct bnx2x *bp, 4136adfc5217SJeff Kirsher struct bnx2x_config_rss_params *p) 4137adfc5217SJeff Kirsher { 4138adfc5217SJeff Kirsher int rc; 4139adfc5217SJeff Kirsher struct bnx2x_rss_config_obj *o = p->rss_obj; 4140adfc5217SJeff Kirsher struct bnx2x_raw_obj *r = &o->raw; 4141adfc5217SJeff Kirsher 4142adfc5217SJeff Kirsher /* Do nothing if only driver cleanup was requested */ 4143adfc5217SJeff Kirsher if (test_bit(RAMROD_DRV_CLR_ONLY, &p->ramrod_flags)) 4144adfc5217SJeff Kirsher return 0; 4145adfc5217SJeff Kirsher 4146adfc5217SJeff Kirsher r->set_pending(r); 4147adfc5217SJeff Kirsher 4148adfc5217SJeff Kirsher rc = o->config_rss(bp, p); 4149adfc5217SJeff Kirsher if (rc < 0) { 4150adfc5217SJeff Kirsher r->clear_pending(r); 4151adfc5217SJeff Kirsher return rc; 4152adfc5217SJeff Kirsher } 4153adfc5217SJeff Kirsher 4154adfc5217SJeff Kirsher if (test_bit(RAMROD_COMP_WAIT, &p->ramrod_flags)) 4155adfc5217SJeff Kirsher rc = r->wait_comp(bp, r); 4156adfc5217SJeff Kirsher 4157adfc5217SJeff Kirsher return rc; 4158adfc5217SJeff Kirsher } 4159adfc5217SJeff Kirsher 4160adfc5217SJeff Kirsher void bnx2x_init_rss_config_obj(struct bnx2x *bp, 4161adfc5217SJeff Kirsher struct bnx2x_rss_config_obj *rss_obj, 4162adfc5217SJeff Kirsher u8 cl_id, u32 cid, u8 func_id, u8 engine_id, 4163adfc5217SJeff Kirsher void *rdata, dma_addr_t rdata_mapping, 4164adfc5217SJeff Kirsher int state, unsigned long *pstate, 4165adfc5217SJeff Kirsher bnx2x_obj_type type) 4166adfc5217SJeff Kirsher { 4167adfc5217SJeff Kirsher bnx2x_init_raw_obj(&rss_obj->raw, cl_id, cid, func_id, rdata, 4168adfc5217SJeff Kirsher rdata_mapping, state, pstate, type); 4169adfc5217SJeff Kirsher 4170adfc5217SJeff Kirsher rss_obj->engine_id = engine_id; 4171adfc5217SJeff Kirsher rss_obj->config_rss = bnx2x_setup_rss; 4172adfc5217SJeff Kirsher } 4173adfc5217SJeff Kirsher 4174adfc5217SJeff Kirsher /********************** Queue state object ***********************************/ 4175adfc5217SJeff Kirsher 4176adfc5217SJeff Kirsher /** 4177adfc5217SJeff Kirsher * bnx2x_queue_state_change - perform Queue state change transition 4178adfc5217SJeff Kirsher * 4179adfc5217SJeff Kirsher * @bp: device handle 4180adfc5217SJeff Kirsher * @params: parameters to perform the transition 4181adfc5217SJeff Kirsher * 4182adfc5217SJeff Kirsher * returns 0 in case of successfully completed transition, negative error 4183adfc5217SJeff Kirsher * code in case of failure, positive (EBUSY) value if there is a completion 4184adfc5217SJeff Kirsher * to that is still pending (possible only if RAMROD_COMP_WAIT is 4185adfc5217SJeff Kirsher * not set in params->ramrod_flags for asynchronous commands). 4186adfc5217SJeff Kirsher * 4187adfc5217SJeff Kirsher */ 4188adfc5217SJeff Kirsher int bnx2x_queue_state_change(struct bnx2x *bp, 4189adfc5217SJeff Kirsher struct bnx2x_queue_state_params *params) 4190adfc5217SJeff Kirsher { 4191adfc5217SJeff Kirsher struct bnx2x_queue_sp_obj *o = params->q_obj; 4192adfc5217SJeff Kirsher int rc, pending_bit; 4193adfc5217SJeff Kirsher unsigned long *pending = &o->pending; 4194adfc5217SJeff Kirsher 4195adfc5217SJeff Kirsher /* Check that the requested transition is legal */ 419604c46736SYuval Mintz rc = o->check_transition(bp, o, params); 419704c46736SYuval Mintz if (rc) { 419804c46736SYuval Mintz BNX2X_ERR("check transition returned an error. rc %d\n", rc); 4199adfc5217SJeff Kirsher return -EINVAL; 420004c46736SYuval Mintz } 4201adfc5217SJeff Kirsher 4202adfc5217SJeff Kirsher /* Set "pending" bit */ 420304c46736SYuval Mintz DP(BNX2X_MSG_SP, "pending bit was=%lx\n", o->pending); 4204adfc5217SJeff Kirsher pending_bit = o->set_pending(o, params); 420504c46736SYuval Mintz DP(BNX2X_MSG_SP, "pending bit now=%lx\n", o->pending); 4206adfc5217SJeff Kirsher 4207adfc5217SJeff Kirsher /* Don't send a command if only driver cleanup was requested */ 4208adfc5217SJeff Kirsher if (test_bit(RAMROD_DRV_CLR_ONLY, ¶ms->ramrod_flags)) 4209adfc5217SJeff Kirsher o->complete_cmd(bp, o, pending_bit); 4210adfc5217SJeff Kirsher else { 4211adfc5217SJeff Kirsher /* Send a ramrod */ 4212adfc5217SJeff Kirsher rc = o->send_cmd(bp, params); 4213adfc5217SJeff Kirsher if (rc) { 4214adfc5217SJeff Kirsher o->next_state = BNX2X_Q_STATE_MAX; 4215adfc5217SJeff Kirsher clear_bit(pending_bit, pending); 4216adfc5217SJeff Kirsher smp_mb__after_clear_bit(); 4217adfc5217SJeff Kirsher return rc; 4218adfc5217SJeff Kirsher } 4219adfc5217SJeff Kirsher 4220adfc5217SJeff Kirsher if (test_bit(RAMROD_COMP_WAIT, ¶ms->ramrod_flags)) { 4221adfc5217SJeff Kirsher rc = o->wait_comp(bp, o, pending_bit); 4222adfc5217SJeff Kirsher if (rc) 4223adfc5217SJeff Kirsher return rc; 4224adfc5217SJeff Kirsher 4225adfc5217SJeff Kirsher return 0; 4226adfc5217SJeff Kirsher } 4227adfc5217SJeff Kirsher } 4228adfc5217SJeff Kirsher 4229adfc5217SJeff Kirsher return !!test_bit(pending_bit, pending); 4230adfc5217SJeff Kirsher } 4231adfc5217SJeff Kirsher 4232adfc5217SJeff Kirsher static int bnx2x_queue_set_pending(struct bnx2x_queue_sp_obj *obj, 4233adfc5217SJeff Kirsher struct bnx2x_queue_state_params *params) 4234adfc5217SJeff Kirsher { 4235adfc5217SJeff Kirsher enum bnx2x_queue_cmd cmd = params->cmd, bit; 4236adfc5217SJeff Kirsher 4237adfc5217SJeff Kirsher /* ACTIVATE and DEACTIVATE commands are implemented on top of 4238adfc5217SJeff Kirsher * UPDATE command. 4239adfc5217SJeff Kirsher */ 4240adfc5217SJeff Kirsher if ((cmd == BNX2X_Q_CMD_ACTIVATE) || 4241adfc5217SJeff Kirsher (cmd == BNX2X_Q_CMD_DEACTIVATE)) 4242adfc5217SJeff Kirsher bit = BNX2X_Q_CMD_UPDATE; 4243adfc5217SJeff Kirsher else 4244adfc5217SJeff Kirsher bit = cmd; 4245adfc5217SJeff Kirsher 4246adfc5217SJeff Kirsher set_bit(bit, &obj->pending); 4247adfc5217SJeff Kirsher return bit; 4248adfc5217SJeff Kirsher } 4249adfc5217SJeff Kirsher 4250adfc5217SJeff Kirsher static int bnx2x_queue_wait_comp(struct bnx2x *bp, 4251adfc5217SJeff Kirsher struct bnx2x_queue_sp_obj *o, 4252adfc5217SJeff Kirsher enum bnx2x_queue_cmd cmd) 4253adfc5217SJeff Kirsher { 4254adfc5217SJeff Kirsher return bnx2x_state_wait(bp, cmd, &o->pending); 4255adfc5217SJeff Kirsher } 4256adfc5217SJeff Kirsher 4257adfc5217SJeff Kirsher /** 4258adfc5217SJeff Kirsher * bnx2x_queue_comp_cmd - complete the state change command. 4259adfc5217SJeff Kirsher * 4260adfc5217SJeff Kirsher * @bp: device handle 4261adfc5217SJeff Kirsher * @o: 4262adfc5217SJeff Kirsher * @cmd: 4263adfc5217SJeff Kirsher * 4264adfc5217SJeff Kirsher * Checks that the arrived completion is expected. 4265adfc5217SJeff Kirsher */ 4266adfc5217SJeff Kirsher static int bnx2x_queue_comp_cmd(struct bnx2x *bp, 4267adfc5217SJeff Kirsher struct bnx2x_queue_sp_obj *o, 4268adfc5217SJeff Kirsher enum bnx2x_queue_cmd cmd) 4269adfc5217SJeff Kirsher { 4270adfc5217SJeff Kirsher unsigned long cur_pending = o->pending; 4271adfc5217SJeff Kirsher 4272adfc5217SJeff Kirsher if (!test_and_clear_bit(cmd, &cur_pending)) { 427351c1a580SMerav Sicron BNX2X_ERR("Bad MC reply %d for queue %d in state %d pending 0x%lx, next_state %d\n", 427451c1a580SMerav Sicron cmd, o->cids[BNX2X_PRIMARY_CID_INDEX], 4275adfc5217SJeff Kirsher o->state, cur_pending, o->next_state); 4276adfc5217SJeff Kirsher return -EINVAL; 4277adfc5217SJeff Kirsher } 4278adfc5217SJeff Kirsher 4279adfc5217SJeff Kirsher if (o->next_tx_only >= o->max_cos) 428016a5fd92SYuval Mintz /* >= because tx only must always be smaller than cos since the 428102582e9bSMasanari Iida * primary connection supports COS 0 4282adfc5217SJeff Kirsher */ 4283adfc5217SJeff Kirsher BNX2X_ERR("illegal value for next tx_only: %d. max cos was %d", 4284adfc5217SJeff Kirsher o->next_tx_only, o->max_cos); 4285adfc5217SJeff Kirsher 428651c1a580SMerav Sicron DP(BNX2X_MSG_SP, 428751c1a580SMerav Sicron "Completing command %d for queue %d, setting state to %d\n", 428851c1a580SMerav Sicron cmd, o->cids[BNX2X_PRIMARY_CID_INDEX], o->next_state); 4289adfc5217SJeff Kirsher 4290adfc5217SJeff Kirsher if (o->next_tx_only) /* print num tx-only if any exist */ 429194f05b0fSJoe Perches DP(BNX2X_MSG_SP, "primary cid %d: num tx-only cons %d\n", 4292adfc5217SJeff Kirsher o->cids[BNX2X_PRIMARY_CID_INDEX], o->next_tx_only); 4293adfc5217SJeff Kirsher 4294adfc5217SJeff Kirsher o->state = o->next_state; 4295adfc5217SJeff Kirsher o->num_tx_only = o->next_tx_only; 4296adfc5217SJeff Kirsher o->next_state = BNX2X_Q_STATE_MAX; 4297adfc5217SJeff Kirsher 4298adfc5217SJeff Kirsher /* It's important that o->state and o->next_state are 4299adfc5217SJeff Kirsher * updated before o->pending. 4300adfc5217SJeff Kirsher */ 4301adfc5217SJeff Kirsher wmb(); 4302adfc5217SJeff Kirsher 4303adfc5217SJeff Kirsher clear_bit(cmd, &o->pending); 4304adfc5217SJeff Kirsher smp_mb__after_clear_bit(); 4305adfc5217SJeff Kirsher 4306adfc5217SJeff Kirsher return 0; 4307adfc5217SJeff Kirsher } 4308adfc5217SJeff Kirsher 4309adfc5217SJeff Kirsher static void bnx2x_q_fill_setup_data_e2(struct bnx2x *bp, 4310adfc5217SJeff Kirsher struct bnx2x_queue_state_params *cmd_params, 4311adfc5217SJeff Kirsher struct client_init_ramrod_data *data) 4312adfc5217SJeff Kirsher { 4313adfc5217SJeff Kirsher struct bnx2x_queue_setup_params *params = &cmd_params->params.setup; 4314adfc5217SJeff Kirsher 4315adfc5217SJeff Kirsher /* Rx data */ 4316adfc5217SJeff Kirsher 4317adfc5217SJeff Kirsher /* IPv6 TPA supported for E2 and above only */ 4318adfc5217SJeff Kirsher data->rx.tpa_en |= test_bit(BNX2X_Q_FLG_TPA_IPV6, ¶ms->flags) * 4319adfc5217SJeff Kirsher CLIENT_INIT_RX_DATA_TPA_EN_IPV6; 4320adfc5217SJeff Kirsher } 4321adfc5217SJeff Kirsher 4322adfc5217SJeff Kirsher static void bnx2x_q_fill_init_general_data(struct bnx2x *bp, 4323adfc5217SJeff Kirsher struct bnx2x_queue_sp_obj *o, 4324adfc5217SJeff Kirsher struct bnx2x_general_setup_params *params, 4325adfc5217SJeff Kirsher struct client_init_general_data *gen_data, 4326adfc5217SJeff Kirsher unsigned long *flags) 4327adfc5217SJeff Kirsher { 4328adfc5217SJeff Kirsher gen_data->client_id = o->cl_id; 4329adfc5217SJeff Kirsher 4330adfc5217SJeff Kirsher if (test_bit(BNX2X_Q_FLG_STATS, flags)) { 4331adfc5217SJeff Kirsher gen_data->statistics_counter_id = 4332adfc5217SJeff Kirsher params->stat_id; 4333adfc5217SJeff Kirsher gen_data->statistics_en_flg = 1; 4334adfc5217SJeff Kirsher gen_data->statistics_zero_flg = 4335adfc5217SJeff Kirsher test_bit(BNX2X_Q_FLG_ZERO_STATS, flags); 4336adfc5217SJeff Kirsher } else 4337adfc5217SJeff Kirsher gen_data->statistics_counter_id = 4338adfc5217SJeff Kirsher DISABLE_STATISTIC_COUNTER_ID_VALUE; 4339adfc5217SJeff Kirsher 4340adfc5217SJeff Kirsher gen_data->is_fcoe_flg = test_bit(BNX2X_Q_FLG_FCOE, flags); 4341adfc5217SJeff Kirsher gen_data->activate_flg = test_bit(BNX2X_Q_FLG_ACTIVE, flags); 4342adfc5217SJeff Kirsher gen_data->sp_client_id = params->spcl_id; 4343adfc5217SJeff Kirsher gen_data->mtu = cpu_to_le16(params->mtu); 4344adfc5217SJeff Kirsher gen_data->func_id = o->func_id; 4345adfc5217SJeff Kirsher 4346adfc5217SJeff Kirsher gen_data->cos = params->cos; 4347adfc5217SJeff Kirsher 4348adfc5217SJeff Kirsher gen_data->traffic_type = 4349adfc5217SJeff Kirsher test_bit(BNX2X_Q_FLG_FCOE, flags) ? 4350adfc5217SJeff Kirsher LLFC_TRAFFIC_TYPE_FCOE : LLFC_TRAFFIC_TYPE_NW; 4351adfc5217SJeff Kirsher 435294f05b0fSJoe Perches DP(BNX2X_MSG_SP, "flags: active %d, cos %d, stats en %d\n", 4353adfc5217SJeff Kirsher gen_data->activate_flg, gen_data->cos, gen_data->statistics_en_flg); 4354adfc5217SJeff Kirsher } 4355adfc5217SJeff Kirsher 4356adfc5217SJeff Kirsher static void bnx2x_q_fill_init_tx_data(struct bnx2x_queue_sp_obj *o, 4357adfc5217SJeff Kirsher struct bnx2x_txq_setup_params *params, 4358adfc5217SJeff Kirsher struct client_init_tx_data *tx_data, 4359adfc5217SJeff Kirsher unsigned long *flags) 4360adfc5217SJeff Kirsher { 4361adfc5217SJeff Kirsher tx_data->enforce_security_flg = 4362adfc5217SJeff Kirsher test_bit(BNX2X_Q_FLG_TX_SEC, flags); 4363adfc5217SJeff Kirsher tx_data->default_vlan = 4364adfc5217SJeff Kirsher cpu_to_le16(params->default_vlan); 4365adfc5217SJeff Kirsher tx_data->default_vlan_flg = 4366adfc5217SJeff Kirsher test_bit(BNX2X_Q_FLG_DEF_VLAN, flags); 4367adfc5217SJeff Kirsher tx_data->tx_switching_flg = 4368adfc5217SJeff Kirsher test_bit(BNX2X_Q_FLG_TX_SWITCH, flags); 4369adfc5217SJeff Kirsher tx_data->anti_spoofing_flg = 4370adfc5217SJeff Kirsher test_bit(BNX2X_Q_FLG_ANTI_SPOOF, flags); 4371a3348722SBarak Witkowski tx_data->force_default_pri_flg = 4372a3348722SBarak Witkowski test_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI, flags); 4373a3348722SBarak Witkowski 4374e287a75cSDmitry Kravkov tx_data->tunnel_lso_inc_ip_id = 4375e287a75cSDmitry Kravkov test_bit(BNX2X_Q_FLG_TUN_INC_INNER_IP_ID, flags); 437691226790SDmitry Kravkov tx_data->tunnel_non_lso_pcsum_location = 437791226790SDmitry Kravkov test_bit(BNX2X_Q_FLG_PCSUM_ON_PKT, flags) ? PCSUM_ON_PKT : 437891226790SDmitry Kravkov PCSUM_ON_BD; 437991226790SDmitry Kravkov 4380adfc5217SJeff Kirsher tx_data->tx_status_block_id = params->fw_sb_id; 4381adfc5217SJeff Kirsher tx_data->tx_sb_index_number = params->sb_cq_index; 4382adfc5217SJeff Kirsher tx_data->tss_leading_client_id = params->tss_leading_cl_id; 4383adfc5217SJeff Kirsher 4384adfc5217SJeff Kirsher tx_data->tx_bd_page_base.lo = 4385adfc5217SJeff Kirsher cpu_to_le32(U64_LO(params->dscr_map)); 4386adfc5217SJeff Kirsher tx_data->tx_bd_page_base.hi = 4387adfc5217SJeff Kirsher cpu_to_le32(U64_HI(params->dscr_map)); 4388adfc5217SJeff Kirsher 4389adfc5217SJeff Kirsher /* Don't configure any Tx switching mode during queue SETUP */ 4390adfc5217SJeff Kirsher tx_data->state = 0; 4391adfc5217SJeff Kirsher } 4392adfc5217SJeff Kirsher 4393adfc5217SJeff Kirsher static void bnx2x_q_fill_init_pause_data(struct bnx2x_queue_sp_obj *o, 4394adfc5217SJeff Kirsher struct rxq_pause_params *params, 4395adfc5217SJeff Kirsher struct client_init_rx_data *rx_data) 4396adfc5217SJeff Kirsher { 4397adfc5217SJeff Kirsher /* flow control data */ 4398adfc5217SJeff Kirsher rx_data->cqe_pause_thr_low = cpu_to_le16(params->rcq_th_lo); 4399adfc5217SJeff Kirsher rx_data->cqe_pause_thr_high = cpu_to_le16(params->rcq_th_hi); 4400adfc5217SJeff Kirsher rx_data->bd_pause_thr_low = cpu_to_le16(params->bd_th_lo); 4401adfc5217SJeff Kirsher rx_data->bd_pause_thr_high = cpu_to_le16(params->bd_th_hi); 4402adfc5217SJeff Kirsher rx_data->sge_pause_thr_low = cpu_to_le16(params->sge_th_lo); 4403adfc5217SJeff Kirsher rx_data->sge_pause_thr_high = cpu_to_le16(params->sge_th_hi); 4404adfc5217SJeff Kirsher rx_data->rx_cos_mask = cpu_to_le16(params->pri_map); 4405adfc5217SJeff Kirsher } 4406adfc5217SJeff Kirsher 4407adfc5217SJeff Kirsher static void bnx2x_q_fill_init_rx_data(struct bnx2x_queue_sp_obj *o, 4408adfc5217SJeff Kirsher struct bnx2x_rxq_setup_params *params, 4409adfc5217SJeff Kirsher struct client_init_rx_data *rx_data, 4410adfc5217SJeff Kirsher unsigned long *flags) 4411adfc5217SJeff Kirsher { 4412adfc5217SJeff Kirsher rx_data->tpa_en = test_bit(BNX2X_Q_FLG_TPA, flags) * 4413adfc5217SJeff Kirsher CLIENT_INIT_RX_DATA_TPA_EN_IPV4; 4414621b4d66SDmitry Kravkov rx_data->tpa_en |= test_bit(BNX2X_Q_FLG_TPA_GRO, flags) * 4415621b4d66SDmitry Kravkov CLIENT_INIT_RX_DATA_TPA_MODE; 4416adfc5217SJeff Kirsher rx_data->vmqueue_mode_en_flg = 0; 4417adfc5217SJeff Kirsher 4418adfc5217SJeff Kirsher rx_data->cache_line_alignment_log_size = 4419adfc5217SJeff Kirsher params->cache_line_log; 4420adfc5217SJeff Kirsher rx_data->enable_dynamic_hc = 4421adfc5217SJeff Kirsher test_bit(BNX2X_Q_FLG_DHC, flags); 4422adfc5217SJeff Kirsher rx_data->max_sges_for_packet = params->max_sges_pkt; 4423adfc5217SJeff Kirsher rx_data->client_qzone_id = params->cl_qzone_id; 4424adfc5217SJeff Kirsher rx_data->max_agg_size = cpu_to_le16(params->tpa_agg_sz); 4425adfc5217SJeff Kirsher 4426adfc5217SJeff Kirsher /* Always start in DROP_ALL mode */ 4427adfc5217SJeff Kirsher rx_data->state = cpu_to_le16(CLIENT_INIT_RX_DATA_UCAST_DROP_ALL | 4428adfc5217SJeff Kirsher CLIENT_INIT_RX_DATA_MCAST_DROP_ALL); 4429adfc5217SJeff Kirsher 4430adfc5217SJeff Kirsher /* We don't set drop flags */ 4431adfc5217SJeff Kirsher rx_data->drop_ip_cs_err_flg = 0; 4432adfc5217SJeff Kirsher rx_data->drop_tcp_cs_err_flg = 0; 4433adfc5217SJeff Kirsher rx_data->drop_ttl0_flg = 0; 4434adfc5217SJeff Kirsher rx_data->drop_udp_cs_err_flg = 0; 4435adfc5217SJeff Kirsher rx_data->inner_vlan_removal_enable_flg = 4436adfc5217SJeff Kirsher test_bit(BNX2X_Q_FLG_VLAN, flags); 4437adfc5217SJeff Kirsher rx_data->outer_vlan_removal_enable_flg = 4438adfc5217SJeff Kirsher test_bit(BNX2X_Q_FLG_OV, flags); 4439adfc5217SJeff Kirsher rx_data->status_block_id = params->fw_sb_id; 4440adfc5217SJeff Kirsher rx_data->rx_sb_index_number = params->sb_cq_index; 4441adfc5217SJeff Kirsher rx_data->max_tpa_queues = params->max_tpa_queues; 4442adfc5217SJeff Kirsher rx_data->max_bytes_on_bd = cpu_to_le16(params->buf_sz); 4443adfc5217SJeff Kirsher rx_data->sge_buff_size = cpu_to_le16(params->sge_buf_sz); 4444adfc5217SJeff Kirsher rx_data->bd_page_base.lo = 4445adfc5217SJeff Kirsher cpu_to_le32(U64_LO(params->dscr_map)); 4446adfc5217SJeff Kirsher rx_data->bd_page_base.hi = 4447adfc5217SJeff Kirsher cpu_to_le32(U64_HI(params->dscr_map)); 4448adfc5217SJeff Kirsher rx_data->sge_page_base.lo = 4449adfc5217SJeff Kirsher cpu_to_le32(U64_LO(params->sge_map)); 4450adfc5217SJeff Kirsher rx_data->sge_page_base.hi = 4451adfc5217SJeff Kirsher cpu_to_le32(U64_HI(params->sge_map)); 4452adfc5217SJeff Kirsher rx_data->cqe_page_base.lo = 4453adfc5217SJeff Kirsher cpu_to_le32(U64_LO(params->rcq_map)); 4454adfc5217SJeff Kirsher rx_data->cqe_page_base.hi = 4455adfc5217SJeff Kirsher cpu_to_le32(U64_HI(params->rcq_map)); 4456adfc5217SJeff Kirsher rx_data->is_leading_rss = test_bit(BNX2X_Q_FLG_LEADING_RSS, flags); 4457adfc5217SJeff Kirsher 4458adfc5217SJeff Kirsher if (test_bit(BNX2X_Q_FLG_MCAST, flags)) { 4459259afa1fSYuval Mintz rx_data->approx_mcast_engine_id = params->mcast_engine_id; 4460adfc5217SJeff Kirsher rx_data->is_approx_mcast = 1; 4461adfc5217SJeff Kirsher } 4462adfc5217SJeff Kirsher 4463adfc5217SJeff Kirsher rx_data->rss_engine_id = params->rss_engine_id; 4464adfc5217SJeff Kirsher 4465adfc5217SJeff Kirsher /* silent vlan removal */ 4466adfc5217SJeff Kirsher rx_data->silent_vlan_removal_flg = 4467adfc5217SJeff Kirsher test_bit(BNX2X_Q_FLG_SILENT_VLAN_REM, flags); 4468adfc5217SJeff Kirsher rx_data->silent_vlan_value = 4469adfc5217SJeff Kirsher cpu_to_le16(params->silent_removal_value); 4470adfc5217SJeff Kirsher rx_data->silent_vlan_mask = 4471adfc5217SJeff Kirsher cpu_to_le16(params->silent_removal_mask); 4472adfc5217SJeff Kirsher } 4473adfc5217SJeff Kirsher 4474adfc5217SJeff Kirsher /* initialize the general, tx and rx parts of a queue object */ 4475adfc5217SJeff Kirsher static void bnx2x_q_fill_setup_data_cmn(struct bnx2x *bp, 4476adfc5217SJeff Kirsher struct bnx2x_queue_state_params *cmd_params, 4477adfc5217SJeff Kirsher struct client_init_ramrod_data *data) 4478adfc5217SJeff Kirsher { 4479adfc5217SJeff Kirsher bnx2x_q_fill_init_general_data(bp, cmd_params->q_obj, 4480adfc5217SJeff Kirsher &cmd_params->params.setup.gen_params, 4481adfc5217SJeff Kirsher &data->general, 4482adfc5217SJeff Kirsher &cmd_params->params.setup.flags); 4483adfc5217SJeff Kirsher 4484adfc5217SJeff Kirsher bnx2x_q_fill_init_tx_data(cmd_params->q_obj, 4485adfc5217SJeff Kirsher &cmd_params->params.setup.txq_params, 4486adfc5217SJeff Kirsher &data->tx, 4487adfc5217SJeff Kirsher &cmd_params->params.setup.flags); 4488adfc5217SJeff Kirsher 4489adfc5217SJeff Kirsher bnx2x_q_fill_init_rx_data(cmd_params->q_obj, 4490adfc5217SJeff Kirsher &cmd_params->params.setup.rxq_params, 4491adfc5217SJeff Kirsher &data->rx, 4492adfc5217SJeff Kirsher &cmd_params->params.setup.flags); 4493adfc5217SJeff Kirsher 4494adfc5217SJeff Kirsher bnx2x_q_fill_init_pause_data(cmd_params->q_obj, 4495adfc5217SJeff Kirsher &cmd_params->params.setup.pause_params, 4496adfc5217SJeff Kirsher &data->rx); 4497adfc5217SJeff Kirsher } 4498adfc5217SJeff Kirsher 4499adfc5217SJeff Kirsher /* initialize the general and tx parts of a tx-only queue object */ 4500adfc5217SJeff Kirsher static void bnx2x_q_fill_setup_tx_only(struct bnx2x *bp, 4501adfc5217SJeff Kirsher struct bnx2x_queue_state_params *cmd_params, 4502adfc5217SJeff Kirsher struct tx_queue_init_ramrod_data *data) 4503adfc5217SJeff Kirsher { 4504adfc5217SJeff Kirsher bnx2x_q_fill_init_general_data(bp, cmd_params->q_obj, 4505adfc5217SJeff Kirsher &cmd_params->params.tx_only.gen_params, 4506adfc5217SJeff Kirsher &data->general, 4507adfc5217SJeff Kirsher &cmd_params->params.tx_only.flags); 4508adfc5217SJeff Kirsher 4509adfc5217SJeff Kirsher bnx2x_q_fill_init_tx_data(cmd_params->q_obj, 4510adfc5217SJeff Kirsher &cmd_params->params.tx_only.txq_params, 4511adfc5217SJeff Kirsher &data->tx, 4512adfc5217SJeff Kirsher &cmd_params->params.tx_only.flags); 4513adfc5217SJeff Kirsher 451451c1a580SMerav Sicron DP(BNX2X_MSG_SP, "cid %d, tx bd page lo %x hi %x", 451551c1a580SMerav Sicron cmd_params->q_obj->cids[0], 451651c1a580SMerav Sicron data->tx.tx_bd_page_base.lo, 451751c1a580SMerav Sicron data->tx.tx_bd_page_base.hi); 4518adfc5217SJeff Kirsher } 4519adfc5217SJeff Kirsher 4520adfc5217SJeff Kirsher /** 4521adfc5217SJeff Kirsher * bnx2x_q_init - init HW/FW queue 4522adfc5217SJeff Kirsher * 4523adfc5217SJeff Kirsher * @bp: device handle 4524adfc5217SJeff Kirsher * @params: 4525adfc5217SJeff Kirsher * 4526adfc5217SJeff Kirsher * HW/FW initial Queue configuration: 4527adfc5217SJeff Kirsher * - HC: Rx and Tx 4528adfc5217SJeff Kirsher * - CDU context validation 4529adfc5217SJeff Kirsher * 4530adfc5217SJeff Kirsher */ 4531adfc5217SJeff Kirsher static inline int bnx2x_q_init(struct bnx2x *bp, 4532adfc5217SJeff Kirsher struct bnx2x_queue_state_params *params) 4533adfc5217SJeff Kirsher { 4534adfc5217SJeff Kirsher struct bnx2x_queue_sp_obj *o = params->q_obj; 4535adfc5217SJeff Kirsher struct bnx2x_queue_init_params *init = ¶ms->params.init; 4536adfc5217SJeff Kirsher u16 hc_usec; 4537adfc5217SJeff Kirsher u8 cos; 4538adfc5217SJeff Kirsher 4539adfc5217SJeff Kirsher /* Tx HC configuration */ 4540adfc5217SJeff Kirsher if (test_bit(BNX2X_Q_TYPE_HAS_TX, &o->type) && 4541adfc5217SJeff Kirsher test_bit(BNX2X_Q_FLG_HC, &init->tx.flags)) { 4542adfc5217SJeff Kirsher hc_usec = init->tx.hc_rate ? 1000000 / init->tx.hc_rate : 0; 4543adfc5217SJeff Kirsher 4544adfc5217SJeff Kirsher bnx2x_update_coalesce_sb_index(bp, init->tx.fw_sb_id, 4545adfc5217SJeff Kirsher init->tx.sb_cq_index, 4546adfc5217SJeff Kirsher !test_bit(BNX2X_Q_FLG_HC_EN, &init->tx.flags), 4547adfc5217SJeff Kirsher hc_usec); 4548adfc5217SJeff Kirsher } 4549adfc5217SJeff Kirsher 4550adfc5217SJeff Kirsher /* Rx HC configuration */ 4551adfc5217SJeff Kirsher if (test_bit(BNX2X_Q_TYPE_HAS_RX, &o->type) && 4552adfc5217SJeff Kirsher test_bit(BNX2X_Q_FLG_HC, &init->rx.flags)) { 4553adfc5217SJeff Kirsher hc_usec = init->rx.hc_rate ? 1000000 / init->rx.hc_rate : 0; 4554adfc5217SJeff Kirsher 4555adfc5217SJeff Kirsher bnx2x_update_coalesce_sb_index(bp, init->rx.fw_sb_id, 4556adfc5217SJeff Kirsher init->rx.sb_cq_index, 4557adfc5217SJeff Kirsher !test_bit(BNX2X_Q_FLG_HC_EN, &init->rx.flags), 4558adfc5217SJeff Kirsher hc_usec); 4559adfc5217SJeff Kirsher } 4560adfc5217SJeff Kirsher 4561adfc5217SJeff Kirsher /* Set CDU context validation values */ 4562adfc5217SJeff Kirsher for (cos = 0; cos < o->max_cos; cos++) { 456394f05b0fSJoe Perches DP(BNX2X_MSG_SP, "setting context validation. cid %d, cos %d\n", 4564adfc5217SJeff Kirsher o->cids[cos], cos); 456594f05b0fSJoe Perches DP(BNX2X_MSG_SP, "context pointer %p\n", init->cxts[cos]); 4566adfc5217SJeff Kirsher bnx2x_set_ctx_validation(bp, init->cxts[cos], o->cids[cos]); 4567adfc5217SJeff Kirsher } 4568adfc5217SJeff Kirsher 4569adfc5217SJeff Kirsher /* As no ramrod is sent, complete the command immediately */ 4570adfc5217SJeff Kirsher o->complete_cmd(bp, o, BNX2X_Q_CMD_INIT); 4571adfc5217SJeff Kirsher 4572adfc5217SJeff Kirsher mmiowb(); 4573adfc5217SJeff Kirsher smp_mb(); 4574adfc5217SJeff Kirsher 4575adfc5217SJeff Kirsher return 0; 4576adfc5217SJeff Kirsher } 4577adfc5217SJeff Kirsher 4578adfc5217SJeff Kirsher static inline int bnx2x_q_send_setup_e1x(struct bnx2x *bp, 4579adfc5217SJeff Kirsher struct bnx2x_queue_state_params *params) 4580adfc5217SJeff Kirsher { 4581adfc5217SJeff Kirsher struct bnx2x_queue_sp_obj *o = params->q_obj; 4582adfc5217SJeff Kirsher struct client_init_ramrod_data *rdata = 4583adfc5217SJeff Kirsher (struct client_init_ramrod_data *)o->rdata; 4584adfc5217SJeff Kirsher dma_addr_t data_mapping = o->rdata_mapping; 4585adfc5217SJeff Kirsher int ramrod = RAMROD_CMD_ID_ETH_CLIENT_SETUP; 4586adfc5217SJeff Kirsher 4587adfc5217SJeff Kirsher /* Clear the ramrod data */ 4588adfc5217SJeff Kirsher memset(rdata, 0, sizeof(*rdata)); 4589adfc5217SJeff Kirsher 4590adfc5217SJeff Kirsher /* Fill the ramrod data */ 4591adfc5217SJeff Kirsher bnx2x_q_fill_setup_data_cmn(bp, params, rdata); 4592adfc5217SJeff Kirsher 459316a5fd92SYuval Mintz /* No need for an explicit memory barrier here as long we would 4594adfc5217SJeff Kirsher * need to ensure the ordering of writing to the SPQ element 4595adfc5217SJeff Kirsher * and updating of the SPQ producer which involves a memory 4596adfc5217SJeff Kirsher * read and we will have to put a full memory barrier there 4597adfc5217SJeff Kirsher * (inside bnx2x_sp_post()). 4598adfc5217SJeff Kirsher */ 4599adfc5217SJeff Kirsher 4600adfc5217SJeff Kirsher return bnx2x_sp_post(bp, ramrod, o->cids[BNX2X_PRIMARY_CID_INDEX], 4601adfc5217SJeff Kirsher U64_HI(data_mapping), 4602adfc5217SJeff Kirsher U64_LO(data_mapping), ETH_CONNECTION_TYPE); 4603adfc5217SJeff Kirsher } 4604adfc5217SJeff Kirsher 4605adfc5217SJeff Kirsher static inline int bnx2x_q_send_setup_e2(struct bnx2x *bp, 4606adfc5217SJeff Kirsher struct bnx2x_queue_state_params *params) 4607adfc5217SJeff Kirsher { 4608adfc5217SJeff Kirsher struct bnx2x_queue_sp_obj *o = params->q_obj; 4609adfc5217SJeff Kirsher struct client_init_ramrod_data *rdata = 4610adfc5217SJeff Kirsher (struct client_init_ramrod_data *)o->rdata; 4611adfc5217SJeff Kirsher dma_addr_t data_mapping = o->rdata_mapping; 4612adfc5217SJeff Kirsher int ramrod = RAMROD_CMD_ID_ETH_CLIENT_SETUP; 4613adfc5217SJeff Kirsher 4614adfc5217SJeff Kirsher /* Clear the ramrod data */ 4615adfc5217SJeff Kirsher memset(rdata, 0, sizeof(*rdata)); 4616adfc5217SJeff Kirsher 4617adfc5217SJeff Kirsher /* Fill the ramrod data */ 4618adfc5217SJeff Kirsher bnx2x_q_fill_setup_data_cmn(bp, params, rdata); 4619adfc5217SJeff Kirsher bnx2x_q_fill_setup_data_e2(bp, params, rdata); 4620adfc5217SJeff Kirsher 462116a5fd92SYuval Mintz /* No need for an explicit memory barrier here as long we would 4622adfc5217SJeff Kirsher * need to ensure the ordering of writing to the SPQ element 4623adfc5217SJeff Kirsher * and updating of the SPQ producer which involves a memory 4624adfc5217SJeff Kirsher * read and we will have to put a full memory barrier there 4625adfc5217SJeff Kirsher * (inside bnx2x_sp_post()). 4626adfc5217SJeff Kirsher */ 4627adfc5217SJeff Kirsher 4628adfc5217SJeff Kirsher return bnx2x_sp_post(bp, ramrod, o->cids[BNX2X_PRIMARY_CID_INDEX], 4629adfc5217SJeff Kirsher U64_HI(data_mapping), 4630adfc5217SJeff Kirsher U64_LO(data_mapping), ETH_CONNECTION_TYPE); 4631adfc5217SJeff Kirsher } 4632adfc5217SJeff Kirsher 4633adfc5217SJeff Kirsher static inline int bnx2x_q_send_setup_tx_only(struct bnx2x *bp, 4634adfc5217SJeff Kirsher struct bnx2x_queue_state_params *params) 4635adfc5217SJeff Kirsher { 4636adfc5217SJeff Kirsher struct bnx2x_queue_sp_obj *o = params->q_obj; 4637adfc5217SJeff Kirsher struct tx_queue_init_ramrod_data *rdata = 4638adfc5217SJeff Kirsher (struct tx_queue_init_ramrod_data *)o->rdata; 4639adfc5217SJeff Kirsher dma_addr_t data_mapping = o->rdata_mapping; 4640adfc5217SJeff Kirsher int ramrod = RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP; 4641adfc5217SJeff Kirsher struct bnx2x_queue_setup_tx_only_params *tx_only_params = 4642adfc5217SJeff Kirsher ¶ms->params.tx_only; 4643adfc5217SJeff Kirsher u8 cid_index = tx_only_params->cid_index; 4644adfc5217SJeff Kirsher 4645adfc5217SJeff Kirsher if (cid_index >= o->max_cos) { 4646adfc5217SJeff Kirsher BNX2X_ERR("queue[%d]: cid_index (%d) is out of range\n", 4647adfc5217SJeff Kirsher o->cl_id, cid_index); 4648adfc5217SJeff Kirsher return -EINVAL; 4649adfc5217SJeff Kirsher } 4650adfc5217SJeff Kirsher 465194f05b0fSJoe Perches DP(BNX2X_MSG_SP, "parameters received: cos: %d sp-id: %d\n", 4652adfc5217SJeff Kirsher tx_only_params->gen_params.cos, 4653adfc5217SJeff Kirsher tx_only_params->gen_params.spcl_id); 4654adfc5217SJeff Kirsher 4655adfc5217SJeff Kirsher /* Clear the ramrod data */ 4656adfc5217SJeff Kirsher memset(rdata, 0, sizeof(*rdata)); 4657adfc5217SJeff Kirsher 4658adfc5217SJeff Kirsher /* Fill the ramrod data */ 4659adfc5217SJeff Kirsher bnx2x_q_fill_setup_tx_only(bp, params, rdata); 4660adfc5217SJeff Kirsher 466151c1a580SMerav Sicron DP(BNX2X_MSG_SP, "sending tx-only ramrod: cid %d, client-id %d, sp-client id %d, cos %d\n", 466251c1a580SMerav Sicron o->cids[cid_index], rdata->general.client_id, 4663adfc5217SJeff Kirsher rdata->general.sp_client_id, rdata->general.cos); 4664adfc5217SJeff Kirsher 466516a5fd92SYuval Mintz /* No need for an explicit memory barrier here as long we would 4666adfc5217SJeff Kirsher * need to ensure the ordering of writing to the SPQ element 4667adfc5217SJeff Kirsher * and updating of the SPQ producer which involves a memory 4668adfc5217SJeff Kirsher * read and we will have to put a full memory barrier there 4669adfc5217SJeff Kirsher * (inside bnx2x_sp_post()). 4670adfc5217SJeff Kirsher */ 4671adfc5217SJeff Kirsher 4672adfc5217SJeff Kirsher return bnx2x_sp_post(bp, ramrod, o->cids[cid_index], 4673adfc5217SJeff Kirsher U64_HI(data_mapping), 4674adfc5217SJeff Kirsher U64_LO(data_mapping), ETH_CONNECTION_TYPE); 4675adfc5217SJeff Kirsher } 4676adfc5217SJeff Kirsher 4677adfc5217SJeff Kirsher static void bnx2x_q_fill_update_data(struct bnx2x *bp, 4678adfc5217SJeff Kirsher struct bnx2x_queue_sp_obj *obj, 4679adfc5217SJeff Kirsher struct bnx2x_queue_update_params *params, 4680adfc5217SJeff Kirsher struct client_update_ramrod_data *data) 4681adfc5217SJeff Kirsher { 4682adfc5217SJeff Kirsher /* Client ID of the client to update */ 4683adfc5217SJeff Kirsher data->client_id = obj->cl_id; 4684adfc5217SJeff Kirsher 4685adfc5217SJeff Kirsher /* Function ID of the client to update */ 4686adfc5217SJeff Kirsher data->func_id = obj->func_id; 4687adfc5217SJeff Kirsher 4688adfc5217SJeff Kirsher /* Default VLAN value */ 4689adfc5217SJeff Kirsher data->default_vlan = cpu_to_le16(params->def_vlan); 4690adfc5217SJeff Kirsher 4691adfc5217SJeff Kirsher /* Inner VLAN stripping */ 4692adfc5217SJeff Kirsher data->inner_vlan_removal_enable_flg = 4693adfc5217SJeff Kirsher test_bit(BNX2X_Q_UPDATE_IN_VLAN_REM, ¶ms->update_flags); 4694adfc5217SJeff Kirsher data->inner_vlan_removal_change_flg = 4695adfc5217SJeff Kirsher test_bit(BNX2X_Q_UPDATE_IN_VLAN_REM_CHNG, 4696adfc5217SJeff Kirsher ¶ms->update_flags); 4697adfc5217SJeff Kirsher 469816a5fd92SYuval Mintz /* Outer VLAN stripping */ 4699adfc5217SJeff Kirsher data->outer_vlan_removal_enable_flg = 4700adfc5217SJeff Kirsher test_bit(BNX2X_Q_UPDATE_OUT_VLAN_REM, ¶ms->update_flags); 4701adfc5217SJeff Kirsher data->outer_vlan_removal_change_flg = 4702adfc5217SJeff Kirsher test_bit(BNX2X_Q_UPDATE_OUT_VLAN_REM_CHNG, 4703adfc5217SJeff Kirsher ¶ms->update_flags); 4704adfc5217SJeff Kirsher 4705adfc5217SJeff Kirsher /* Drop packets that have source MAC that doesn't belong to this 4706adfc5217SJeff Kirsher * Queue. 4707adfc5217SJeff Kirsher */ 4708adfc5217SJeff Kirsher data->anti_spoofing_enable_flg = 4709adfc5217SJeff Kirsher test_bit(BNX2X_Q_UPDATE_ANTI_SPOOF, ¶ms->update_flags); 4710adfc5217SJeff Kirsher data->anti_spoofing_change_flg = 4711adfc5217SJeff Kirsher test_bit(BNX2X_Q_UPDATE_ANTI_SPOOF_CHNG, ¶ms->update_flags); 4712adfc5217SJeff Kirsher 4713adfc5217SJeff Kirsher /* Activate/Deactivate */ 4714adfc5217SJeff Kirsher data->activate_flg = 4715adfc5217SJeff Kirsher test_bit(BNX2X_Q_UPDATE_ACTIVATE, ¶ms->update_flags); 4716adfc5217SJeff Kirsher data->activate_change_flg = 4717adfc5217SJeff Kirsher test_bit(BNX2X_Q_UPDATE_ACTIVATE_CHNG, ¶ms->update_flags); 4718adfc5217SJeff Kirsher 4719adfc5217SJeff Kirsher /* Enable default VLAN */ 4720adfc5217SJeff Kirsher data->default_vlan_enable_flg = 4721adfc5217SJeff Kirsher test_bit(BNX2X_Q_UPDATE_DEF_VLAN_EN, ¶ms->update_flags); 4722adfc5217SJeff Kirsher data->default_vlan_change_flg = 4723adfc5217SJeff Kirsher test_bit(BNX2X_Q_UPDATE_DEF_VLAN_EN_CHNG, 4724adfc5217SJeff Kirsher ¶ms->update_flags); 4725adfc5217SJeff Kirsher 4726adfc5217SJeff Kirsher /* silent vlan removal */ 4727adfc5217SJeff Kirsher data->silent_vlan_change_flg = 4728adfc5217SJeff Kirsher test_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG, 4729adfc5217SJeff Kirsher ¶ms->update_flags); 4730adfc5217SJeff Kirsher data->silent_vlan_removal_flg = 4731adfc5217SJeff Kirsher test_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM, ¶ms->update_flags); 4732adfc5217SJeff Kirsher data->silent_vlan_value = cpu_to_le16(params->silent_removal_value); 4733adfc5217SJeff Kirsher data->silent_vlan_mask = cpu_to_le16(params->silent_removal_mask); 4734adfc5217SJeff Kirsher } 4735adfc5217SJeff Kirsher 4736adfc5217SJeff Kirsher static inline int bnx2x_q_send_update(struct bnx2x *bp, 4737adfc5217SJeff Kirsher struct bnx2x_queue_state_params *params) 4738adfc5217SJeff Kirsher { 4739adfc5217SJeff Kirsher struct bnx2x_queue_sp_obj *o = params->q_obj; 4740adfc5217SJeff Kirsher struct client_update_ramrod_data *rdata = 4741adfc5217SJeff Kirsher (struct client_update_ramrod_data *)o->rdata; 4742adfc5217SJeff Kirsher dma_addr_t data_mapping = o->rdata_mapping; 4743adfc5217SJeff Kirsher struct bnx2x_queue_update_params *update_params = 4744adfc5217SJeff Kirsher ¶ms->params.update; 4745adfc5217SJeff Kirsher u8 cid_index = update_params->cid_index; 4746adfc5217SJeff Kirsher 4747adfc5217SJeff Kirsher if (cid_index >= o->max_cos) { 4748adfc5217SJeff Kirsher BNX2X_ERR("queue[%d]: cid_index (%d) is out of range\n", 4749adfc5217SJeff Kirsher o->cl_id, cid_index); 4750adfc5217SJeff Kirsher return -EINVAL; 4751adfc5217SJeff Kirsher } 4752adfc5217SJeff Kirsher 4753adfc5217SJeff Kirsher /* Clear the ramrod data */ 4754adfc5217SJeff Kirsher memset(rdata, 0, sizeof(*rdata)); 4755adfc5217SJeff Kirsher 4756adfc5217SJeff Kirsher /* Fill the ramrod data */ 4757adfc5217SJeff Kirsher bnx2x_q_fill_update_data(bp, o, update_params, rdata); 4758adfc5217SJeff Kirsher 475916a5fd92SYuval Mintz /* No need for an explicit memory barrier here as long we would 4760adfc5217SJeff Kirsher * need to ensure the ordering of writing to the SPQ element 4761adfc5217SJeff Kirsher * and updating of the SPQ producer which involves a memory 4762adfc5217SJeff Kirsher * read and we will have to put a full memory barrier there 4763adfc5217SJeff Kirsher * (inside bnx2x_sp_post()). 4764adfc5217SJeff Kirsher */ 4765adfc5217SJeff Kirsher 4766adfc5217SJeff Kirsher return bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_CLIENT_UPDATE, 4767adfc5217SJeff Kirsher o->cids[cid_index], U64_HI(data_mapping), 4768adfc5217SJeff Kirsher U64_LO(data_mapping), ETH_CONNECTION_TYPE); 4769adfc5217SJeff Kirsher } 4770adfc5217SJeff Kirsher 4771adfc5217SJeff Kirsher /** 4772adfc5217SJeff Kirsher * bnx2x_q_send_deactivate - send DEACTIVATE command 4773adfc5217SJeff Kirsher * 4774adfc5217SJeff Kirsher * @bp: device handle 4775adfc5217SJeff Kirsher * @params: 4776adfc5217SJeff Kirsher * 4777adfc5217SJeff Kirsher * implemented using the UPDATE command. 4778adfc5217SJeff Kirsher */ 4779adfc5217SJeff Kirsher static inline int bnx2x_q_send_deactivate(struct bnx2x *bp, 4780adfc5217SJeff Kirsher struct bnx2x_queue_state_params *params) 4781adfc5217SJeff Kirsher { 4782adfc5217SJeff Kirsher struct bnx2x_queue_update_params *update = ¶ms->params.update; 4783adfc5217SJeff Kirsher 4784adfc5217SJeff Kirsher memset(update, 0, sizeof(*update)); 4785adfc5217SJeff Kirsher 4786adfc5217SJeff Kirsher __set_bit(BNX2X_Q_UPDATE_ACTIVATE_CHNG, &update->update_flags); 4787adfc5217SJeff Kirsher 4788adfc5217SJeff Kirsher return bnx2x_q_send_update(bp, params); 4789adfc5217SJeff Kirsher } 4790adfc5217SJeff Kirsher 4791adfc5217SJeff Kirsher /** 4792adfc5217SJeff Kirsher * bnx2x_q_send_activate - send ACTIVATE command 4793adfc5217SJeff Kirsher * 4794adfc5217SJeff Kirsher * @bp: device handle 4795adfc5217SJeff Kirsher * @params: 4796adfc5217SJeff Kirsher * 4797adfc5217SJeff Kirsher * implemented using the UPDATE command. 4798adfc5217SJeff Kirsher */ 4799adfc5217SJeff Kirsher static inline int bnx2x_q_send_activate(struct bnx2x *bp, 4800adfc5217SJeff Kirsher struct bnx2x_queue_state_params *params) 4801adfc5217SJeff Kirsher { 4802adfc5217SJeff Kirsher struct bnx2x_queue_update_params *update = ¶ms->params.update; 4803adfc5217SJeff Kirsher 4804adfc5217SJeff Kirsher memset(update, 0, sizeof(*update)); 4805adfc5217SJeff Kirsher 4806adfc5217SJeff Kirsher __set_bit(BNX2X_Q_UPDATE_ACTIVATE, &update->update_flags); 4807adfc5217SJeff Kirsher __set_bit(BNX2X_Q_UPDATE_ACTIVATE_CHNG, &update->update_flags); 4808adfc5217SJeff Kirsher 4809adfc5217SJeff Kirsher return bnx2x_q_send_update(bp, params); 4810adfc5217SJeff Kirsher } 4811adfc5217SJeff Kirsher 4812adfc5217SJeff Kirsher static inline int bnx2x_q_send_update_tpa(struct bnx2x *bp, 4813adfc5217SJeff Kirsher struct bnx2x_queue_state_params *params) 4814adfc5217SJeff Kirsher { 4815adfc5217SJeff Kirsher /* TODO: Not implemented yet. */ 4816adfc5217SJeff Kirsher return -1; 4817adfc5217SJeff Kirsher } 4818adfc5217SJeff Kirsher 4819adfc5217SJeff Kirsher static inline int bnx2x_q_send_halt(struct bnx2x *bp, 4820adfc5217SJeff Kirsher struct bnx2x_queue_state_params *params) 4821adfc5217SJeff Kirsher { 4822adfc5217SJeff Kirsher struct bnx2x_queue_sp_obj *o = params->q_obj; 4823adfc5217SJeff Kirsher 4824adfc5217SJeff Kirsher return bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_HALT, 4825adfc5217SJeff Kirsher o->cids[BNX2X_PRIMARY_CID_INDEX], 0, o->cl_id, 4826adfc5217SJeff Kirsher ETH_CONNECTION_TYPE); 4827adfc5217SJeff Kirsher } 4828adfc5217SJeff Kirsher 4829adfc5217SJeff Kirsher static inline int bnx2x_q_send_cfc_del(struct bnx2x *bp, 4830adfc5217SJeff Kirsher struct bnx2x_queue_state_params *params) 4831adfc5217SJeff Kirsher { 4832adfc5217SJeff Kirsher struct bnx2x_queue_sp_obj *o = params->q_obj; 4833adfc5217SJeff Kirsher u8 cid_idx = params->params.cfc_del.cid_index; 4834adfc5217SJeff Kirsher 4835adfc5217SJeff Kirsher if (cid_idx >= o->max_cos) { 4836adfc5217SJeff Kirsher BNX2X_ERR("queue[%d]: cid_index (%d) is out of range\n", 4837adfc5217SJeff Kirsher o->cl_id, cid_idx); 4838adfc5217SJeff Kirsher return -EINVAL; 4839adfc5217SJeff Kirsher } 4840adfc5217SJeff Kirsher 4841adfc5217SJeff Kirsher return bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_CFC_DEL, 4842adfc5217SJeff Kirsher o->cids[cid_idx], 0, 0, NONE_CONNECTION_TYPE); 4843adfc5217SJeff Kirsher } 4844adfc5217SJeff Kirsher 4845adfc5217SJeff Kirsher static inline int bnx2x_q_send_terminate(struct bnx2x *bp, 4846adfc5217SJeff Kirsher struct bnx2x_queue_state_params *params) 4847adfc5217SJeff Kirsher { 4848adfc5217SJeff Kirsher struct bnx2x_queue_sp_obj *o = params->q_obj; 4849adfc5217SJeff Kirsher u8 cid_index = params->params.terminate.cid_index; 4850adfc5217SJeff Kirsher 4851adfc5217SJeff Kirsher if (cid_index >= o->max_cos) { 4852adfc5217SJeff Kirsher BNX2X_ERR("queue[%d]: cid_index (%d) is out of range\n", 4853adfc5217SJeff Kirsher o->cl_id, cid_index); 4854adfc5217SJeff Kirsher return -EINVAL; 4855adfc5217SJeff Kirsher } 4856adfc5217SJeff Kirsher 4857adfc5217SJeff Kirsher return bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_TERMINATE, 4858adfc5217SJeff Kirsher o->cids[cid_index], 0, 0, ETH_CONNECTION_TYPE); 4859adfc5217SJeff Kirsher } 4860adfc5217SJeff Kirsher 4861adfc5217SJeff Kirsher static inline int bnx2x_q_send_empty(struct bnx2x *bp, 4862adfc5217SJeff Kirsher struct bnx2x_queue_state_params *params) 4863adfc5217SJeff Kirsher { 4864adfc5217SJeff Kirsher struct bnx2x_queue_sp_obj *o = params->q_obj; 4865adfc5217SJeff Kirsher 4866adfc5217SJeff Kirsher return bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_EMPTY, 4867adfc5217SJeff Kirsher o->cids[BNX2X_PRIMARY_CID_INDEX], 0, 0, 4868adfc5217SJeff Kirsher ETH_CONNECTION_TYPE); 4869adfc5217SJeff Kirsher } 4870adfc5217SJeff Kirsher 4871adfc5217SJeff Kirsher static inline int bnx2x_queue_send_cmd_cmn(struct bnx2x *bp, 4872adfc5217SJeff Kirsher struct bnx2x_queue_state_params *params) 4873adfc5217SJeff Kirsher { 4874adfc5217SJeff Kirsher switch (params->cmd) { 4875adfc5217SJeff Kirsher case BNX2X_Q_CMD_INIT: 4876adfc5217SJeff Kirsher return bnx2x_q_init(bp, params); 4877adfc5217SJeff Kirsher case BNX2X_Q_CMD_SETUP_TX_ONLY: 4878adfc5217SJeff Kirsher return bnx2x_q_send_setup_tx_only(bp, params); 4879adfc5217SJeff Kirsher case BNX2X_Q_CMD_DEACTIVATE: 4880adfc5217SJeff Kirsher return bnx2x_q_send_deactivate(bp, params); 4881adfc5217SJeff Kirsher case BNX2X_Q_CMD_ACTIVATE: 4882adfc5217SJeff Kirsher return bnx2x_q_send_activate(bp, params); 4883adfc5217SJeff Kirsher case BNX2X_Q_CMD_UPDATE: 4884adfc5217SJeff Kirsher return bnx2x_q_send_update(bp, params); 4885adfc5217SJeff Kirsher case BNX2X_Q_CMD_UPDATE_TPA: 4886adfc5217SJeff Kirsher return bnx2x_q_send_update_tpa(bp, params); 4887adfc5217SJeff Kirsher case BNX2X_Q_CMD_HALT: 4888adfc5217SJeff Kirsher return bnx2x_q_send_halt(bp, params); 4889adfc5217SJeff Kirsher case BNX2X_Q_CMD_CFC_DEL: 4890adfc5217SJeff Kirsher return bnx2x_q_send_cfc_del(bp, params); 4891adfc5217SJeff Kirsher case BNX2X_Q_CMD_TERMINATE: 4892adfc5217SJeff Kirsher return bnx2x_q_send_terminate(bp, params); 4893adfc5217SJeff Kirsher case BNX2X_Q_CMD_EMPTY: 4894adfc5217SJeff Kirsher return bnx2x_q_send_empty(bp, params); 4895adfc5217SJeff Kirsher default: 4896adfc5217SJeff Kirsher BNX2X_ERR("Unknown command: %d\n", params->cmd); 4897adfc5217SJeff Kirsher return -EINVAL; 4898adfc5217SJeff Kirsher } 4899adfc5217SJeff Kirsher } 4900adfc5217SJeff Kirsher 4901adfc5217SJeff Kirsher static int bnx2x_queue_send_cmd_e1x(struct bnx2x *bp, 4902adfc5217SJeff Kirsher struct bnx2x_queue_state_params *params) 4903adfc5217SJeff Kirsher { 4904adfc5217SJeff Kirsher switch (params->cmd) { 4905adfc5217SJeff Kirsher case BNX2X_Q_CMD_SETUP: 4906adfc5217SJeff Kirsher return bnx2x_q_send_setup_e1x(bp, params); 4907adfc5217SJeff Kirsher case BNX2X_Q_CMD_INIT: 4908adfc5217SJeff Kirsher case BNX2X_Q_CMD_SETUP_TX_ONLY: 4909adfc5217SJeff Kirsher case BNX2X_Q_CMD_DEACTIVATE: 4910adfc5217SJeff Kirsher case BNX2X_Q_CMD_ACTIVATE: 4911adfc5217SJeff Kirsher case BNX2X_Q_CMD_UPDATE: 4912adfc5217SJeff Kirsher case BNX2X_Q_CMD_UPDATE_TPA: 4913adfc5217SJeff Kirsher case BNX2X_Q_CMD_HALT: 4914adfc5217SJeff Kirsher case BNX2X_Q_CMD_CFC_DEL: 4915adfc5217SJeff Kirsher case BNX2X_Q_CMD_TERMINATE: 4916adfc5217SJeff Kirsher case BNX2X_Q_CMD_EMPTY: 4917adfc5217SJeff Kirsher return bnx2x_queue_send_cmd_cmn(bp, params); 4918adfc5217SJeff Kirsher default: 4919adfc5217SJeff Kirsher BNX2X_ERR("Unknown command: %d\n", params->cmd); 4920adfc5217SJeff Kirsher return -EINVAL; 4921adfc5217SJeff Kirsher } 4922adfc5217SJeff Kirsher } 4923adfc5217SJeff Kirsher 4924adfc5217SJeff Kirsher static int bnx2x_queue_send_cmd_e2(struct bnx2x *bp, 4925adfc5217SJeff Kirsher struct bnx2x_queue_state_params *params) 4926adfc5217SJeff Kirsher { 4927adfc5217SJeff Kirsher switch (params->cmd) { 4928adfc5217SJeff Kirsher case BNX2X_Q_CMD_SETUP: 4929adfc5217SJeff Kirsher return bnx2x_q_send_setup_e2(bp, params); 4930adfc5217SJeff Kirsher case BNX2X_Q_CMD_INIT: 4931adfc5217SJeff Kirsher case BNX2X_Q_CMD_SETUP_TX_ONLY: 4932adfc5217SJeff Kirsher case BNX2X_Q_CMD_DEACTIVATE: 4933adfc5217SJeff Kirsher case BNX2X_Q_CMD_ACTIVATE: 4934adfc5217SJeff Kirsher case BNX2X_Q_CMD_UPDATE: 4935adfc5217SJeff Kirsher case BNX2X_Q_CMD_UPDATE_TPA: 4936adfc5217SJeff Kirsher case BNX2X_Q_CMD_HALT: 4937adfc5217SJeff Kirsher case BNX2X_Q_CMD_CFC_DEL: 4938adfc5217SJeff Kirsher case BNX2X_Q_CMD_TERMINATE: 4939adfc5217SJeff Kirsher case BNX2X_Q_CMD_EMPTY: 4940adfc5217SJeff Kirsher return bnx2x_queue_send_cmd_cmn(bp, params); 4941adfc5217SJeff Kirsher default: 4942adfc5217SJeff Kirsher BNX2X_ERR("Unknown command: %d\n", params->cmd); 4943adfc5217SJeff Kirsher return -EINVAL; 4944adfc5217SJeff Kirsher } 4945adfc5217SJeff Kirsher } 4946adfc5217SJeff Kirsher 4947adfc5217SJeff Kirsher /** 4948adfc5217SJeff Kirsher * bnx2x_queue_chk_transition - check state machine of a regular Queue 4949adfc5217SJeff Kirsher * 4950adfc5217SJeff Kirsher * @bp: device handle 4951adfc5217SJeff Kirsher * @o: 4952adfc5217SJeff Kirsher * @params: 4953adfc5217SJeff Kirsher * 4954adfc5217SJeff Kirsher * (not Forwarding) 4955adfc5217SJeff Kirsher * It both checks if the requested command is legal in a current 4956adfc5217SJeff Kirsher * state and, if it's legal, sets a `next_state' in the object 4957adfc5217SJeff Kirsher * that will be used in the completion flow to set the `state' 4958adfc5217SJeff Kirsher * of the object. 4959adfc5217SJeff Kirsher * 4960adfc5217SJeff Kirsher * returns 0 if a requested command is a legal transition, 4961adfc5217SJeff Kirsher * -EINVAL otherwise. 4962adfc5217SJeff Kirsher */ 4963adfc5217SJeff Kirsher static int bnx2x_queue_chk_transition(struct bnx2x *bp, 4964adfc5217SJeff Kirsher struct bnx2x_queue_sp_obj *o, 4965adfc5217SJeff Kirsher struct bnx2x_queue_state_params *params) 4966adfc5217SJeff Kirsher { 4967adfc5217SJeff Kirsher enum bnx2x_q_state state = o->state, next_state = BNX2X_Q_STATE_MAX; 4968adfc5217SJeff Kirsher enum bnx2x_queue_cmd cmd = params->cmd; 4969adfc5217SJeff Kirsher struct bnx2x_queue_update_params *update_params = 4970adfc5217SJeff Kirsher ¶ms->params.update; 4971adfc5217SJeff Kirsher u8 next_tx_only = o->num_tx_only; 4972adfc5217SJeff Kirsher 497316a5fd92SYuval Mintz /* Forget all pending for completion commands if a driver only state 4974adfc5217SJeff Kirsher * transition has been requested. 4975adfc5217SJeff Kirsher */ 4976adfc5217SJeff Kirsher if (test_bit(RAMROD_DRV_CLR_ONLY, ¶ms->ramrod_flags)) { 4977adfc5217SJeff Kirsher o->pending = 0; 4978adfc5217SJeff Kirsher o->next_state = BNX2X_Q_STATE_MAX; 4979adfc5217SJeff Kirsher } 4980adfc5217SJeff Kirsher 498116a5fd92SYuval Mintz /* Don't allow a next state transition if we are in the middle of 4982adfc5217SJeff Kirsher * the previous one. 4983adfc5217SJeff Kirsher */ 498404c46736SYuval Mintz if (o->pending) { 498504c46736SYuval Mintz BNX2X_ERR("Blocking transition since pending was %lx\n", 498604c46736SYuval Mintz o->pending); 4987adfc5217SJeff Kirsher return -EBUSY; 498804c46736SYuval Mintz } 4989adfc5217SJeff Kirsher 4990adfc5217SJeff Kirsher switch (state) { 4991adfc5217SJeff Kirsher case BNX2X_Q_STATE_RESET: 4992adfc5217SJeff Kirsher if (cmd == BNX2X_Q_CMD_INIT) 4993adfc5217SJeff Kirsher next_state = BNX2X_Q_STATE_INITIALIZED; 4994adfc5217SJeff Kirsher 4995adfc5217SJeff Kirsher break; 4996adfc5217SJeff Kirsher case BNX2X_Q_STATE_INITIALIZED: 4997adfc5217SJeff Kirsher if (cmd == BNX2X_Q_CMD_SETUP) { 4998adfc5217SJeff Kirsher if (test_bit(BNX2X_Q_FLG_ACTIVE, 4999adfc5217SJeff Kirsher ¶ms->params.setup.flags)) 5000adfc5217SJeff Kirsher next_state = BNX2X_Q_STATE_ACTIVE; 5001adfc5217SJeff Kirsher else 5002adfc5217SJeff Kirsher next_state = BNX2X_Q_STATE_INACTIVE; 5003adfc5217SJeff Kirsher } 5004adfc5217SJeff Kirsher 5005adfc5217SJeff Kirsher break; 5006adfc5217SJeff Kirsher case BNX2X_Q_STATE_ACTIVE: 5007adfc5217SJeff Kirsher if (cmd == BNX2X_Q_CMD_DEACTIVATE) 5008adfc5217SJeff Kirsher next_state = BNX2X_Q_STATE_INACTIVE; 5009adfc5217SJeff Kirsher 5010adfc5217SJeff Kirsher else if ((cmd == BNX2X_Q_CMD_EMPTY) || 5011adfc5217SJeff Kirsher (cmd == BNX2X_Q_CMD_UPDATE_TPA)) 5012adfc5217SJeff Kirsher next_state = BNX2X_Q_STATE_ACTIVE; 5013adfc5217SJeff Kirsher 5014adfc5217SJeff Kirsher else if (cmd == BNX2X_Q_CMD_SETUP_TX_ONLY) { 5015adfc5217SJeff Kirsher next_state = BNX2X_Q_STATE_MULTI_COS; 5016adfc5217SJeff Kirsher next_tx_only = 1; 5017adfc5217SJeff Kirsher } 5018adfc5217SJeff Kirsher 5019adfc5217SJeff Kirsher else if (cmd == BNX2X_Q_CMD_HALT) 5020adfc5217SJeff Kirsher next_state = BNX2X_Q_STATE_STOPPED; 5021adfc5217SJeff Kirsher 5022adfc5217SJeff Kirsher else if (cmd == BNX2X_Q_CMD_UPDATE) { 5023adfc5217SJeff Kirsher /* If "active" state change is requested, update the 5024adfc5217SJeff Kirsher * state accordingly. 5025adfc5217SJeff Kirsher */ 5026adfc5217SJeff Kirsher if (test_bit(BNX2X_Q_UPDATE_ACTIVATE_CHNG, 5027adfc5217SJeff Kirsher &update_params->update_flags) && 5028adfc5217SJeff Kirsher !test_bit(BNX2X_Q_UPDATE_ACTIVATE, 5029adfc5217SJeff Kirsher &update_params->update_flags)) 5030adfc5217SJeff Kirsher next_state = BNX2X_Q_STATE_INACTIVE; 5031adfc5217SJeff Kirsher else 5032adfc5217SJeff Kirsher next_state = BNX2X_Q_STATE_ACTIVE; 5033adfc5217SJeff Kirsher } 5034adfc5217SJeff Kirsher 5035adfc5217SJeff Kirsher break; 5036adfc5217SJeff Kirsher case BNX2X_Q_STATE_MULTI_COS: 5037adfc5217SJeff Kirsher if (cmd == BNX2X_Q_CMD_TERMINATE) 5038adfc5217SJeff Kirsher next_state = BNX2X_Q_STATE_MCOS_TERMINATED; 5039adfc5217SJeff Kirsher 5040adfc5217SJeff Kirsher else if (cmd == BNX2X_Q_CMD_SETUP_TX_ONLY) { 5041adfc5217SJeff Kirsher next_state = BNX2X_Q_STATE_MULTI_COS; 5042adfc5217SJeff Kirsher next_tx_only = o->num_tx_only + 1; 5043adfc5217SJeff Kirsher } 5044adfc5217SJeff Kirsher 5045adfc5217SJeff Kirsher else if ((cmd == BNX2X_Q_CMD_EMPTY) || 5046adfc5217SJeff Kirsher (cmd == BNX2X_Q_CMD_UPDATE_TPA)) 5047adfc5217SJeff Kirsher next_state = BNX2X_Q_STATE_MULTI_COS; 5048adfc5217SJeff Kirsher 5049adfc5217SJeff Kirsher else if (cmd == BNX2X_Q_CMD_UPDATE) { 5050adfc5217SJeff Kirsher /* If "active" state change is requested, update the 5051adfc5217SJeff Kirsher * state accordingly. 5052adfc5217SJeff Kirsher */ 5053adfc5217SJeff Kirsher if (test_bit(BNX2X_Q_UPDATE_ACTIVATE_CHNG, 5054adfc5217SJeff Kirsher &update_params->update_flags) && 5055adfc5217SJeff Kirsher !test_bit(BNX2X_Q_UPDATE_ACTIVATE, 5056adfc5217SJeff Kirsher &update_params->update_flags)) 5057adfc5217SJeff Kirsher next_state = BNX2X_Q_STATE_INACTIVE; 5058adfc5217SJeff Kirsher else 5059adfc5217SJeff Kirsher next_state = BNX2X_Q_STATE_MULTI_COS; 5060adfc5217SJeff Kirsher } 5061adfc5217SJeff Kirsher 5062adfc5217SJeff Kirsher break; 5063adfc5217SJeff Kirsher case BNX2X_Q_STATE_MCOS_TERMINATED: 5064adfc5217SJeff Kirsher if (cmd == BNX2X_Q_CMD_CFC_DEL) { 5065adfc5217SJeff Kirsher next_tx_only = o->num_tx_only - 1; 5066adfc5217SJeff Kirsher if (next_tx_only == 0) 5067adfc5217SJeff Kirsher next_state = BNX2X_Q_STATE_ACTIVE; 5068adfc5217SJeff Kirsher else 5069adfc5217SJeff Kirsher next_state = BNX2X_Q_STATE_MULTI_COS; 5070adfc5217SJeff Kirsher } 5071adfc5217SJeff Kirsher 5072adfc5217SJeff Kirsher break; 5073adfc5217SJeff Kirsher case BNX2X_Q_STATE_INACTIVE: 5074adfc5217SJeff Kirsher if (cmd == BNX2X_Q_CMD_ACTIVATE) 5075adfc5217SJeff Kirsher next_state = BNX2X_Q_STATE_ACTIVE; 5076adfc5217SJeff Kirsher 5077adfc5217SJeff Kirsher else if ((cmd == BNX2X_Q_CMD_EMPTY) || 5078adfc5217SJeff Kirsher (cmd == BNX2X_Q_CMD_UPDATE_TPA)) 5079adfc5217SJeff Kirsher next_state = BNX2X_Q_STATE_INACTIVE; 5080adfc5217SJeff Kirsher 5081adfc5217SJeff Kirsher else if (cmd == BNX2X_Q_CMD_HALT) 5082adfc5217SJeff Kirsher next_state = BNX2X_Q_STATE_STOPPED; 5083adfc5217SJeff Kirsher 5084adfc5217SJeff Kirsher else if (cmd == BNX2X_Q_CMD_UPDATE) { 5085adfc5217SJeff Kirsher /* If "active" state change is requested, update the 5086adfc5217SJeff Kirsher * state accordingly. 5087adfc5217SJeff Kirsher */ 5088adfc5217SJeff Kirsher if (test_bit(BNX2X_Q_UPDATE_ACTIVATE_CHNG, 5089adfc5217SJeff Kirsher &update_params->update_flags) && 5090adfc5217SJeff Kirsher test_bit(BNX2X_Q_UPDATE_ACTIVATE, 5091adfc5217SJeff Kirsher &update_params->update_flags)){ 5092adfc5217SJeff Kirsher if (o->num_tx_only == 0) 5093adfc5217SJeff Kirsher next_state = BNX2X_Q_STATE_ACTIVE; 5094adfc5217SJeff Kirsher else /* tx only queues exist for this queue */ 5095adfc5217SJeff Kirsher next_state = BNX2X_Q_STATE_MULTI_COS; 5096adfc5217SJeff Kirsher } else 5097adfc5217SJeff Kirsher next_state = BNX2X_Q_STATE_INACTIVE; 5098adfc5217SJeff Kirsher } 5099adfc5217SJeff Kirsher 5100adfc5217SJeff Kirsher break; 5101adfc5217SJeff Kirsher case BNX2X_Q_STATE_STOPPED: 5102adfc5217SJeff Kirsher if (cmd == BNX2X_Q_CMD_TERMINATE) 5103adfc5217SJeff Kirsher next_state = BNX2X_Q_STATE_TERMINATED; 5104adfc5217SJeff Kirsher 5105adfc5217SJeff Kirsher break; 5106adfc5217SJeff Kirsher case BNX2X_Q_STATE_TERMINATED: 5107adfc5217SJeff Kirsher if (cmd == BNX2X_Q_CMD_CFC_DEL) 5108adfc5217SJeff Kirsher next_state = BNX2X_Q_STATE_RESET; 5109adfc5217SJeff Kirsher 5110adfc5217SJeff Kirsher break; 5111adfc5217SJeff Kirsher default: 5112adfc5217SJeff Kirsher BNX2X_ERR("Illegal state: %d\n", state); 5113adfc5217SJeff Kirsher } 5114adfc5217SJeff Kirsher 5115adfc5217SJeff Kirsher /* Transition is assured */ 5116adfc5217SJeff Kirsher if (next_state != BNX2X_Q_STATE_MAX) { 5117adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "Good state transition: %d(%d)->%d\n", 5118adfc5217SJeff Kirsher state, cmd, next_state); 5119adfc5217SJeff Kirsher o->next_state = next_state; 5120adfc5217SJeff Kirsher o->next_tx_only = next_tx_only; 5121adfc5217SJeff Kirsher return 0; 5122adfc5217SJeff Kirsher } 5123adfc5217SJeff Kirsher 5124adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "Bad state transition request: %d %d\n", state, cmd); 5125adfc5217SJeff Kirsher 5126adfc5217SJeff Kirsher return -EINVAL; 5127adfc5217SJeff Kirsher } 5128adfc5217SJeff Kirsher 5129adfc5217SJeff Kirsher void bnx2x_init_queue_obj(struct bnx2x *bp, 5130adfc5217SJeff Kirsher struct bnx2x_queue_sp_obj *obj, 5131adfc5217SJeff Kirsher u8 cl_id, u32 *cids, u8 cid_cnt, u8 func_id, 5132adfc5217SJeff Kirsher void *rdata, 5133adfc5217SJeff Kirsher dma_addr_t rdata_mapping, unsigned long type) 5134adfc5217SJeff Kirsher { 5135adfc5217SJeff Kirsher memset(obj, 0, sizeof(*obj)); 5136adfc5217SJeff Kirsher 5137adfc5217SJeff Kirsher /* We support only BNX2X_MULTI_TX_COS Tx CoS at the moment */ 5138adfc5217SJeff Kirsher BUG_ON(BNX2X_MULTI_TX_COS < cid_cnt); 5139adfc5217SJeff Kirsher 5140adfc5217SJeff Kirsher memcpy(obj->cids, cids, sizeof(obj->cids[0]) * cid_cnt); 5141adfc5217SJeff Kirsher obj->max_cos = cid_cnt; 5142adfc5217SJeff Kirsher obj->cl_id = cl_id; 5143adfc5217SJeff Kirsher obj->func_id = func_id; 5144adfc5217SJeff Kirsher obj->rdata = rdata; 5145adfc5217SJeff Kirsher obj->rdata_mapping = rdata_mapping; 5146adfc5217SJeff Kirsher obj->type = type; 5147adfc5217SJeff Kirsher obj->next_state = BNX2X_Q_STATE_MAX; 5148adfc5217SJeff Kirsher 5149adfc5217SJeff Kirsher if (CHIP_IS_E1x(bp)) 5150adfc5217SJeff Kirsher obj->send_cmd = bnx2x_queue_send_cmd_e1x; 5151adfc5217SJeff Kirsher else 5152adfc5217SJeff Kirsher obj->send_cmd = bnx2x_queue_send_cmd_e2; 5153adfc5217SJeff Kirsher 5154adfc5217SJeff Kirsher obj->check_transition = bnx2x_queue_chk_transition; 5155adfc5217SJeff Kirsher 5156adfc5217SJeff Kirsher obj->complete_cmd = bnx2x_queue_comp_cmd; 5157adfc5217SJeff Kirsher obj->wait_comp = bnx2x_queue_wait_comp; 5158adfc5217SJeff Kirsher obj->set_pending = bnx2x_queue_set_pending; 5159adfc5217SJeff Kirsher } 5160adfc5217SJeff Kirsher 516167c431a5SAriel Elior /* return a queue object's logical state*/ 516267c431a5SAriel Elior int bnx2x_get_q_logical_state(struct bnx2x *bp, 516367c431a5SAriel Elior struct bnx2x_queue_sp_obj *obj) 516467c431a5SAriel Elior { 516567c431a5SAriel Elior switch (obj->state) { 516667c431a5SAriel Elior case BNX2X_Q_STATE_ACTIVE: 516767c431a5SAriel Elior case BNX2X_Q_STATE_MULTI_COS: 516867c431a5SAriel Elior return BNX2X_Q_LOGICAL_STATE_ACTIVE; 516967c431a5SAriel Elior case BNX2X_Q_STATE_RESET: 517067c431a5SAriel Elior case BNX2X_Q_STATE_INITIALIZED: 517167c431a5SAriel Elior case BNX2X_Q_STATE_MCOS_TERMINATED: 517267c431a5SAriel Elior case BNX2X_Q_STATE_INACTIVE: 517367c431a5SAriel Elior case BNX2X_Q_STATE_STOPPED: 517467c431a5SAriel Elior case BNX2X_Q_STATE_TERMINATED: 517567c431a5SAriel Elior case BNX2X_Q_STATE_FLRED: 517667c431a5SAriel Elior return BNX2X_Q_LOGICAL_STATE_STOPPED; 517767c431a5SAriel Elior default: 517867c431a5SAriel Elior return -EINVAL; 517967c431a5SAriel Elior } 518067c431a5SAriel Elior } 518167c431a5SAriel Elior 5182adfc5217SJeff Kirsher /********************** Function state object *********************************/ 5183adfc5217SJeff Kirsher enum bnx2x_func_state bnx2x_func_get_state(struct bnx2x *bp, 5184adfc5217SJeff Kirsher struct bnx2x_func_sp_obj *o) 5185adfc5217SJeff Kirsher { 5186adfc5217SJeff Kirsher /* in the middle of transaction - return INVALID state */ 5187adfc5217SJeff Kirsher if (o->pending) 5188adfc5217SJeff Kirsher return BNX2X_F_STATE_MAX; 5189adfc5217SJeff Kirsher 519016a5fd92SYuval Mintz /* unsure the order of reading of o->pending and o->state 5191adfc5217SJeff Kirsher * o->pending should be read first 5192adfc5217SJeff Kirsher */ 5193adfc5217SJeff Kirsher rmb(); 5194adfc5217SJeff Kirsher 5195adfc5217SJeff Kirsher return o->state; 5196adfc5217SJeff Kirsher } 5197adfc5217SJeff Kirsher 5198adfc5217SJeff Kirsher static int bnx2x_func_wait_comp(struct bnx2x *bp, 5199adfc5217SJeff Kirsher struct bnx2x_func_sp_obj *o, 5200adfc5217SJeff Kirsher enum bnx2x_func_cmd cmd) 5201adfc5217SJeff Kirsher { 5202adfc5217SJeff Kirsher return bnx2x_state_wait(bp, cmd, &o->pending); 5203adfc5217SJeff Kirsher } 5204adfc5217SJeff Kirsher 5205adfc5217SJeff Kirsher /** 5206adfc5217SJeff Kirsher * bnx2x_func_state_change_comp - complete the state machine transition 5207adfc5217SJeff Kirsher * 5208adfc5217SJeff Kirsher * @bp: device handle 5209adfc5217SJeff Kirsher * @o: 5210adfc5217SJeff Kirsher * @cmd: 5211adfc5217SJeff Kirsher * 5212adfc5217SJeff Kirsher * Called on state change transition. Completes the state 5213adfc5217SJeff Kirsher * machine transition only - no HW interaction. 5214adfc5217SJeff Kirsher */ 5215adfc5217SJeff Kirsher static inline int bnx2x_func_state_change_comp(struct bnx2x *bp, 5216adfc5217SJeff Kirsher struct bnx2x_func_sp_obj *o, 5217adfc5217SJeff Kirsher enum bnx2x_func_cmd cmd) 5218adfc5217SJeff Kirsher { 5219adfc5217SJeff Kirsher unsigned long cur_pending = o->pending; 5220adfc5217SJeff Kirsher 5221adfc5217SJeff Kirsher if (!test_and_clear_bit(cmd, &cur_pending)) { 522251c1a580SMerav Sicron BNX2X_ERR("Bad MC reply %d for func %d in state %d pending 0x%lx, next_state %d\n", 522351c1a580SMerav Sicron cmd, BP_FUNC(bp), o->state, 522451c1a580SMerav Sicron cur_pending, o->next_state); 5225adfc5217SJeff Kirsher return -EINVAL; 5226adfc5217SJeff Kirsher } 5227adfc5217SJeff Kirsher 522894f05b0fSJoe Perches DP(BNX2X_MSG_SP, 522994f05b0fSJoe Perches "Completing command %d for func %d, setting state to %d\n", 523094f05b0fSJoe Perches cmd, BP_FUNC(bp), o->next_state); 5231adfc5217SJeff Kirsher 5232adfc5217SJeff Kirsher o->state = o->next_state; 5233adfc5217SJeff Kirsher o->next_state = BNX2X_F_STATE_MAX; 5234adfc5217SJeff Kirsher 5235adfc5217SJeff Kirsher /* It's important that o->state and o->next_state are 5236adfc5217SJeff Kirsher * updated before o->pending. 5237adfc5217SJeff Kirsher */ 5238adfc5217SJeff Kirsher wmb(); 5239adfc5217SJeff Kirsher 5240adfc5217SJeff Kirsher clear_bit(cmd, &o->pending); 5241adfc5217SJeff Kirsher smp_mb__after_clear_bit(); 5242adfc5217SJeff Kirsher 5243adfc5217SJeff Kirsher return 0; 5244adfc5217SJeff Kirsher } 5245adfc5217SJeff Kirsher 5246adfc5217SJeff Kirsher /** 5247adfc5217SJeff Kirsher * bnx2x_func_comp_cmd - complete the state change command 5248adfc5217SJeff Kirsher * 5249adfc5217SJeff Kirsher * @bp: device handle 5250adfc5217SJeff Kirsher * @o: 5251adfc5217SJeff Kirsher * @cmd: 5252adfc5217SJeff Kirsher * 5253adfc5217SJeff Kirsher * Checks that the arrived completion is expected. 5254adfc5217SJeff Kirsher */ 5255adfc5217SJeff Kirsher static int bnx2x_func_comp_cmd(struct bnx2x *bp, 5256adfc5217SJeff Kirsher struct bnx2x_func_sp_obj *o, 5257adfc5217SJeff Kirsher enum bnx2x_func_cmd cmd) 5258adfc5217SJeff Kirsher { 5259adfc5217SJeff Kirsher /* Complete the state machine part first, check if it's a 5260adfc5217SJeff Kirsher * legal completion. 5261adfc5217SJeff Kirsher */ 5262adfc5217SJeff Kirsher int rc = bnx2x_func_state_change_comp(bp, o, cmd); 5263adfc5217SJeff Kirsher return rc; 5264adfc5217SJeff Kirsher } 5265adfc5217SJeff Kirsher 5266adfc5217SJeff Kirsher /** 5267adfc5217SJeff Kirsher * bnx2x_func_chk_transition - perform function state machine transition 5268adfc5217SJeff Kirsher * 5269adfc5217SJeff Kirsher * @bp: device handle 5270adfc5217SJeff Kirsher * @o: 5271adfc5217SJeff Kirsher * @params: 5272adfc5217SJeff Kirsher * 5273adfc5217SJeff Kirsher * It both checks if the requested command is legal in a current 5274adfc5217SJeff Kirsher * state and, if it's legal, sets a `next_state' in the object 5275adfc5217SJeff Kirsher * that will be used in the completion flow to set the `state' 5276adfc5217SJeff Kirsher * of the object. 5277adfc5217SJeff Kirsher * 5278adfc5217SJeff Kirsher * returns 0 if a requested command is a legal transition, 5279adfc5217SJeff Kirsher * -EINVAL otherwise. 5280adfc5217SJeff Kirsher */ 5281adfc5217SJeff Kirsher static int bnx2x_func_chk_transition(struct bnx2x *bp, 5282adfc5217SJeff Kirsher struct bnx2x_func_sp_obj *o, 5283adfc5217SJeff Kirsher struct bnx2x_func_state_params *params) 5284adfc5217SJeff Kirsher { 5285adfc5217SJeff Kirsher enum bnx2x_func_state state = o->state, next_state = BNX2X_F_STATE_MAX; 5286adfc5217SJeff Kirsher enum bnx2x_func_cmd cmd = params->cmd; 5287adfc5217SJeff Kirsher 528816a5fd92SYuval Mintz /* Forget all pending for completion commands if a driver only state 5289adfc5217SJeff Kirsher * transition has been requested. 5290adfc5217SJeff Kirsher */ 5291adfc5217SJeff Kirsher if (test_bit(RAMROD_DRV_CLR_ONLY, ¶ms->ramrod_flags)) { 5292adfc5217SJeff Kirsher o->pending = 0; 5293adfc5217SJeff Kirsher o->next_state = BNX2X_F_STATE_MAX; 5294adfc5217SJeff Kirsher } 5295adfc5217SJeff Kirsher 529616a5fd92SYuval Mintz /* Don't allow a next state transition if we are in the middle of 5297adfc5217SJeff Kirsher * the previous one. 5298adfc5217SJeff Kirsher */ 5299adfc5217SJeff Kirsher if (o->pending) 5300adfc5217SJeff Kirsher return -EBUSY; 5301adfc5217SJeff Kirsher 5302adfc5217SJeff Kirsher switch (state) { 5303adfc5217SJeff Kirsher case BNX2X_F_STATE_RESET: 5304adfc5217SJeff Kirsher if (cmd == BNX2X_F_CMD_HW_INIT) 5305adfc5217SJeff Kirsher next_state = BNX2X_F_STATE_INITIALIZED; 5306adfc5217SJeff Kirsher 5307adfc5217SJeff Kirsher break; 5308adfc5217SJeff Kirsher case BNX2X_F_STATE_INITIALIZED: 5309adfc5217SJeff Kirsher if (cmd == BNX2X_F_CMD_START) 5310adfc5217SJeff Kirsher next_state = BNX2X_F_STATE_STARTED; 5311adfc5217SJeff Kirsher 5312adfc5217SJeff Kirsher else if (cmd == BNX2X_F_CMD_HW_RESET) 5313adfc5217SJeff Kirsher next_state = BNX2X_F_STATE_RESET; 5314adfc5217SJeff Kirsher 5315adfc5217SJeff Kirsher break; 5316adfc5217SJeff Kirsher case BNX2X_F_STATE_STARTED: 5317adfc5217SJeff Kirsher if (cmd == BNX2X_F_CMD_STOP) 5318adfc5217SJeff Kirsher next_state = BNX2X_F_STATE_INITIALIZED; 5319a3348722SBarak Witkowski /* afex ramrods can be sent only in started mode, and only 5320a3348722SBarak Witkowski * if not pending for function_stop ramrod completion 5321a3348722SBarak Witkowski * for these events - next state remained STARTED. 5322a3348722SBarak Witkowski */ 5323a3348722SBarak Witkowski else if ((cmd == BNX2X_F_CMD_AFEX_UPDATE) && 5324a3348722SBarak Witkowski (!test_bit(BNX2X_F_CMD_STOP, &o->pending))) 5325a3348722SBarak Witkowski next_state = BNX2X_F_STATE_STARTED; 5326a3348722SBarak Witkowski 5327a3348722SBarak Witkowski else if ((cmd == BNX2X_F_CMD_AFEX_VIFLISTS) && 5328a3348722SBarak Witkowski (!test_bit(BNX2X_F_CMD_STOP, &o->pending))) 5329a3348722SBarak Witkowski next_state = BNX2X_F_STATE_STARTED; 533055c11941SMerav Sicron 533155c11941SMerav Sicron /* Switch_update ramrod can be sent in either started or 533255c11941SMerav Sicron * tx_stopped state, and it doesn't change the state. 533355c11941SMerav Sicron */ 533455c11941SMerav Sicron else if ((cmd == BNX2X_F_CMD_SWITCH_UPDATE) && 533555c11941SMerav Sicron (!test_bit(BNX2X_F_CMD_STOP, &o->pending))) 533655c11941SMerav Sicron next_state = BNX2X_F_STATE_STARTED; 533755c11941SMerav Sicron 5338adfc5217SJeff Kirsher else if (cmd == BNX2X_F_CMD_TX_STOP) 5339adfc5217SJeff Kirsher next_state = BNX2X_F_STATE_TX_STOPPED; 5340adfc5217SJeff Kirsher 5341adfc5217SJeff Kirsher break; 5342adfc5217SJeff Kirsher case BNX2X_F_STATE_TX_STOPPED: 534355c11941SMerav Sicron if ((cmd == BNX2X_F_CMD_SWITCH_UPDATE) && 534455c11941SMerav Sicron (!test_bit(BNX2X_F_CMD_STOP, &o->pending))) 534555c11941SMerav Sicron next_state = BNX2X_F_STATE_TX_STOPPED; 534655c11941SMerav Sicron 534755c11941SMerav Sicron else if (cmd == BNX2X_F_CMD_TX_START) 5348adfc5217SJeff Kirsher next_state = BNX2X_F_STATE_STARTED; 5349adfc5217SJeff Kirsher 5350adfc5217SJeff Kirsher break; 5351adfc5217SJeff Kirsher default: 5352adfc5217SJeff Kirsher BNX2X_ERR("Unknown state: %d\n", state); 5353adfc5217SJeff Kirsher } 5354adfc5217SJeff Kirsher 5355adfc5217SJeff Kirsher /* Transition is assured */ 5356adfc5217SJeff Kirsher if (next_state != BNX2X_F_STATE_MAX) { 5357adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "Good function state transition: %d(%d)->%d\n", 5358adfc5217SJeff Kirsher state, cmd, next_state); 5359adfc5217SJeff Kirsher o->next_state = next_state; 5360adfc5217SJeff Kirsher return 0; 5361adfc5217SJeff Kirsher } 5362adfc5217SJeff Kirsher 5363adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "Bad function state transition request: %d %d\n", 5364adfc5217SJeff Kirsher state, cmd); 5365adfc5217SJeff Kirsher 5366adfc5217SJeff Kirsher return -EINVAL; 5367adfc5217SJeff Kirsher } 5368adfc5217SJeff Kirsher 5369adfc5217SJeff Kirsher /** 5370adfc5217SJeff Kirsher * bnx2x_func_init_func - performs HW init at function stage 5371adfc5217SJeff Kirsher * 5372adfc5217SJeff Kirsher * @bp: device handle 5373adfc5217SJeff Kirsher * @drv: 5374adfc5217SJeff Kirsher * 5375adfc5217SJeff Kirsher * Init HW when the current phase is 5376adfc5217SJeff Kirsher * FW_MSG_CODE_DRV_LOAD_FUNCTION: initialize only FUNCTION-only 5377adfc5217SJeff Kirsher * HW blocks. 5378adfc5217SJeff Kirsher */ 5379adfc5217SJeff Kirsher static inline int bnx2x_func_init_func(struct bnx2x *bp, 5380adfc5217SJeff Kirsher const struct bnx2x_func_sp_drv_ops *drv) 5381adfc5217SJeff Kirsher { 5382adfc5217SJeff Kirsher return drv->init_hw_func(bp); 5383adfc5217SJeff Kirsher } 5384adfc5217SJeff Kirsher 5385adfc5217SJeff Kirsher /** 5386adfc5217SJeff Kirsher * bnx2x_func_init_port - performs HW init at port stage 5387adfc5217SJeff Kirsher * 5388adfc5217SJeff Kirsher * @bp: device handle 5389adfc5217SJeff Kirsher * @drv: 5390adfc5217SJeff Kirsher * 5391adfc5217SJeff Kirsher * Init HW when the current phase is 5392adfc5217SJeff Kirsher * FW_MSG_CODE_DRV_LOAD_PORT: initialize PORT-only and 5393adfc5217SJeff Kirsher * FUNCTION-only HW blocks. 5394adfc5217SJeff Kirsher * 5395adfc5217SJeff Kirsher */ 5396adfc5217SJeff Kirsher static inline int bnx2x_func_init_port(struct bnx2x *bp, 5397adfc5217SJeff Kirsher const struct bnx2x_func_sp_drv_ops *drv) 5398adfc5217SJeff Kirsher { 5399adfc5217SJeff Kirsher int rc = drv->init_hw_port(bp); 5400adfc5217SJeff Kirsher if (rc) 5401adfc5217SJeff Kirsher return rc; 5402adfc5217SJeff Kirsher 5403adfc5217SJeff Kirsher return bnx2x_func_init_func(bp, drv); 5404adfc5217SJeff Kirsher } 5405adfc5217SJeff Kirsher 5406adfc5217SJeff Kirsher /** 5407adfc5217SJeff Kirsher * bnx2x_func_init_cmn_chip - performs HW init at chip-common stage 5408adfc5217SJeff Kirsher * 5409adfc5217SJeff Kirsher * @bp: device handle 5410adfc5217SJeff Kirsher * @drv: 5411adfc5217SJeff Kirsher * 5412adfc5217SJeff Kirsher * Init HW when the current phase is 5413adfc5217SJeff Kirsher * FW_MSG_CODE_DRV_LOAD_COMMON_CHIP: initialize COMMON_CHIP, 5414adfc5217SJeff Kirsher * PORT-only and FUNCTION-only HW blocks. 5415adfc5217SJeff Kirsher */ 5416adfc5217SJeff Kirsher static inline int bnx2x_func_init_cmn_chip(struct bnx2x *bp, 5417adfc5217SJeff Kirsher const struct bnx2x_func_sp_drv_ops *drv) 5418adfc5217SJeff Kirsher { 5419adfc5217SJeff Kirsher int rc = drv->init_hw_cmn_chip(bp); 5420adfc5217SJeff Kirsher if (rc) 5421adfc5217SJeff Kirsher return rc; 5422adfc5217SJeff Kirsher 5423adfc5217SJeff Kirsher return bnx2x_func_init_port(bp, drv); 5424adfc5217SJeff Kirsher } 5425adfc5217SJeff Kirsher 5426adfc5217SJeff Kirsher /** 5427adfc5217SJeff Kirsher * bnx2x_func_init_cmn - performs HW init at common stage 5428adfc5217SJeff Kirsher * 5429adfc5217SJeff Kirsher * @bp: device handle 5430adfc5217SJeff Kirsher * @drv: 5431adfc5217SJeff Kirsher * 5432adfc5217SJeff Kirsher * Init HW when the current phase is 5433adfc5217SJeff Kirsher * FW_MSG_CODE_DRV_LOAD_COMMON_CHIP: initialize COMMON, 5434adfc5217SJeff Kirsher * PORT-only and FUNCTION-only HW blocks. 5435adfc5217SJeff Kirsher */ 5436adfc5217SJeff Kirsher static inline int bnx2x_func_init_cmn(struct bnx2x *bp, 5437adfc5217SJeff Kirsher const struct bnx2x_func_sp_drv_ops *drv) 5438adfc5217SJeff Kirsher { 5439adfc5217SJeff Kirsher int rc = drv->init_hw_cmn(bp); 5440adfc5217SJeff Kirsher if (rc) 5441adfc5217SJeff Kirsher return rc; 5442adfc5217SJeff Kirsher 5443adfc5217SJeff Kirsher return bnx2x_func_init_port(bp, drv); 5444adfc5217SJeff Kirsher } 5445adfc5217SJeff Kirsher 5446adfc5217SJeff Kirsher static int bnx2x_func_hw_init(struct bnx2x *bp, 5447adfc5217SJeff Kirsher struct bnx2x_func_state_params *params) 5448adfc5217SJeff Kirsher { 5449adfc5217SJeff Kirsher u32 load_code = params->params.hw_init.load_phase; 5450adfc5217SJeff Kirsher struct bnx2x_func_sp_obj *o = params->f_obj; 5451adfc5217SJeff Kirsher const struct bnx2x_func_sp_drv_ops *drv = o->drv; 5452adfc5217SJeff Kirsher int rc = 0; 5453adfc5217SJeff Kirsher 5454adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "function %d load_code %x\n", 5455adfc5217SJeff Kirsher BP_ABS_FUNC(bp), load_code); 5456adfc5217SJeff Kirsher 5457adfc5217SJeff Kirsher /* Prepare buffers for unzipping the FW */ 5458adfc5217SJeff Kirsher rc = drv->gunzip_init(bp); 5459adfc5217SJeff Kirsher if (rc) 5460adfc5217SJeff Kirsher return rc; 5461adfc5217SJeff Kirsher 5462adfc5217SJeff Kirsher /* Prepare FW */ 5463adfc5217SJeff Kirsher rc = drv->init_fw(bp); 5464adfc5217SJeff Kirsher if (rc) { 5465adfc5217SJeff Kirsher BNX2X_ERR("Error loading firmware\n"); 5466eb2afd4aSDmitry Kravkov goto init_err; 5467adfc5217SJeff Kirsher } 5468adfc5217SJeff Kirsher 546916a5fd92SYuval Mintz /* Handle the beginning of COMMON_XXX pases separately... */ 5470adfc5217SJeff Kirsher switch (load_code) { 5471adfc5217SJeff Kirsher case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP: 5472adfc5217SJeff Kirsher rc = bnx2x_func_init_cmn_chip(bp, drv); 5473adfc5217SJeff Kirsher if (rc) 5474eb2afd4aSDmitry Kravkov goto init_err; 5475adfc5217SJeff Kirsher 5476adfc5217SJeff Kirsher break; 5477adfc5217SJeff Kirsher case FW_MSG_CODE_DRV_LOAD_COMMON: 5478adfc5217SJeff Kirsher rc = bnx2x_func_init_cmn(bp, drv); 5479adfc5217SJeff Kirsher if (rc) 5480eb2afd4aSDmitry Kravkov goto init_err; 5481adfc5217SJeff Kirsher 5482adfc5217SJeff Kirsher break; 5483adfc5217SJeff Kirsher case FW_MSG_CODE_DRV_LOAD_PORT: 5484adfc5217SJeff Kirsher rc = bnx2x_func_init_port(bp, drv); 5485adfc5217SJeff Kirsher if (rc) 5486eb2afd4aSDmitry Kravkov goto init_err; 5487adfc5217SJeff Kirsher 5488adfc5217SJeff Kirsher break; 5489adfc5217SJeff Kirsher case FW_MSG_CODE_DRV_LOAD_FUNCTION: 5490adfc5217SJeff Kirsher rc = bnx2x_func_init_func(bp, drv); 5491adfc5217SJeff Kirsher if (rc) 5492eb2afd4aSDmitry Kravkov goto init_err; 5493adfc5217SJeff Kirsher 5494adfc5217SJeff Kirsher break; 5495adfc5217SJeff Kirsher default: 5496adfc5217SJeff Kirsher BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code); 5497adfc5217SJeff Kirsher rc = -EINVAL; 5498adfc5217SJeff Kirsher } 5499adfc5217SJeff Kirsher 5500eb2afd4aSDmitry Kravkov init_err: 5501adfc5217SJeff Kirsher drv->gunzip_end(bp); 5502adfc5217SJeff Kirsher 550316a5fd92SYuval Mintz /* In case of success, complete the command immediately: no ramrods 5504adfc5217SJeff Kirsher * have been sent. 5505adfc5217SJeff Kirsher */ 5506adfc5217SJeff Kirsher if (!rc) 5507adfc5217SJeff Kirsher o->complete_cmd(bp, o, BNX2X_F_CMD_HW_INIT); 5508adfc5217SJeff Kirsher 5509adfc5217SJeff Kirsher return rc; 5510adfc5217SJeff Kirsher } 5511adfc5217SJeff Kirsher 5512adfc5217SJeff Kirsher /** 5513adfc5217SJeff Kirsher * bnx2x_func_reset_func - reset HW at function stage 5514adfc5217SJeff Kirsher * 5515adfc5217SJeff Kirsher * @bp: device handle 5516adfc5217SJeff Kirsher * @drv: 5517adfc5217SJeff Kirsher * 5518adfc5217SJeff Kirsher * Reset HW at FW_MSG_CODE_DRV_UNLOAD_FUNCTION stage: reset only 5519adfc5217SJeff Kirsher * FUNCTION-only HW blocks. 5520adfc5217SJeff Kirsher */ 5521adfc5217SJeff Kirsher static inline void bnx2x_func_reset_func(struct bnx2x *bp, 5522adfc5217SJeff Kirsher const struct bnx2x_func_sp_drv_ops *drv) 5523adfc5217SJeff Kirsher { 5524adfc5217SJeff Kirsher drv->reset_hw_func(bp); 5525adfc5217SJeff Kirsher } 5526adfc5217SJeff Kirsher 5527adfc5217SJeff Kirsher /** 552816a5fd92SYuval Mintz * bnx2x_func_reset_port - reset HW at port stage 5529adfc5217SJeff Kirsher * 5530adfc5217SJeff Kirsher * @bp: device handle 5531adfc5217SJeff Kirsher * @drv: 5532adfc5217SJeff Kirsher * 5533adfc5217SJeff Kirsher * Reset HW at FW_MSG_CODE_DRV_UNLOAD_PORT stage: reset 5534adfc5217SJeff Kirsher * FUNCTION-only and PORT-only HW blocks. 5535adfc5217SJeff Kirsher * 5536adfc5217SJeff Kirsher * !!!IMPORTANT!!! 5537adfc5217SJeff Kirsher * 5538adfc5217SJeff Kirsher * It's important to call reset_port before reset_func() as the last thing 5539adfc5217SJeff Kirsher * reset_func does is pf_disable() thus disabling PGLUE_B, which 5540adfc5217SJeff Kirsher * makes impossible any DMAE transactions. 5541adfc5217SJeff Kirsher */ 5542adfc5217SJeff Kirsher static inline void bnx2x_func_reset_port(struct bnx2x *bp, 5543adfc5217SJeff Kirsher const struct bnx2x_func_sp_drv_ops *drv) 5544adfc5217SJeff Kirsher { 5545adfc5217SJeff Kirsher drv->reset_hw_port(bp); 5546adfc5217SJeff Kirsher bnx2x_func_reset_func(bp, drv); 5547adfc5217SJeff Kirsher } 5548adfc5217SJeff Kirsher 5549adfc5217SJeff Kirsher /** 555016a5fd92SYuval Mintz * bnx2x_func_reset_cmn - reset HW at common stage 5551adfc5217SJeff Kirsher * 5552adfc5217SJeff Kirsher * @bp: device handle 5553adfc5217SJeff Kirsher * @drv: 5554adfc5217SJeff Kirsher * 5555adfc5217SJeff Kirsher * Reset HW at FW_MSG_CODE_DRV_UNLOAD_COMMON and 5556adfc5217SJeff Kirsher * FW_MSG_CODE_DRV_UNLOAD_COMMON_CHIP stages: reset COMMON, 5557adfc5217SJeff Kirsher * COMMON_CHIP, FUNCTION-only and PORT-only HW blocks. 5558adfc5217SJeff Kirsher */ 5559adfc5217SJeff Kirsher static inline void bnx2x_func_reset_cmn(struct bnx2x *bp, 5560adfc5217SJeff Kirsher const struct bnx2x_func_sp_drv_ops *drv) 5561adfc5217SJeff Kirsher { 5562adfc5217SJeff Kirsher bnx2x_func_reset_port(bp, drv); 5563adfc5217SJeff Kirsher drv->reset_hw_cmn(bp); 5564adfc5217SJeff Kirsher } 5565adfc5217SJeff Kirsher 5566adfc5217SJeff Kirsher static inline int bnx2x_func_hw_reset(struct bnx2x *bp, 5567adfc5217SJeff Kirsher struct bnx2x_func_state_params *params) 5568adfc5217SJeff Kirsher { 5569adfc5217SJeff Kirsher u32 reset_phase = params->params.hw_reset.reset_phase; 5570adfc5217SJeff Kirsher struct bnx2x_func_sp_obj *o = params->f_obj; 5571adfc5217SJeff Kirsher const struct bnx2x_func_sp_drv_ops *drv = o->drv; 5572adfc5217SJeff Kirsher 5573adfc5217SJeff Kirsher DP(BNX2X_MSG_SP, "function %d reset_phase %x\n", BP_ABS_FUNC(bp), 5574adfc5217SJeff Kirsher reset_phase); 5575adfc5217SJeff Kirsher 5576adfc5217SJeff Kirsher switch (reset_phase) { 5577adfc5217SJeff Kirsher case FW_MSG_CODE_DRV_UNLOAD_COMMON: 5578adfc5217SJeff Kirsher bnx2x_func_reset_cmn(bp, drv); 5579adfc5217SJeff Kirsher break; 5580adfc5217SJeff Kirsher case FW_MSG_CODE_DRV_UNLOAD_PORT: 5581adfc5217SJeff Kirsher bnx2x_func_reset_port(bp, drv); 5582adfc5217SJeff Kirsher break; 5583adfc5217SJeff Kirsher case FW_MSG_CODE_DRV_UNLOAD_FUNCTION: 5584adfc5217SJeff Kirsher bnx2x_func_reset_func(bp, drv); 5585adfc5217SJeff Kirsher break; 5586adfc5217SJeff Kirsher default: 5587adfc5217SJeff Kirsher BNX2X_ERR("Unknown reset_phase (0x%x) from MCP\n", 5588adfc5217SJeff Kirsher reset_phase); 5589adfc5217SJeff Kirsher break; 5590adfc5217SJeff Kirsher } 5591adfc5217SJeff Kirsher 559216a5fd92SYuval Mintz /* Complete the command immediately: no ramrods have been sent. */ 5593adfc5217SJeff Kirsher o->complete_cmd(bp, o, BNX2X_F_CMD_HW_RESET); 5594adfc5217SJeff Kirsher 5595adfc5217SJeff Kirsher return 0; 5596adfc5217SJeff Kirsher } 5597adfc5217SJeff Kirsher 5598adfc5217SJeff Kirsher static inline int bnx2x_func_send_start(struct bnx2x *bp, 5599adfc5217SJeff Kirsher struct bnx2x_func_state_params *params) 5600adfc5217SJeff Kirsher { 5601adfc5217SJeff Kirsher struct bnx2x_func_sp_obj *o = params->f_obj; 5602adfc5217SJeff Kirsher struct function_start_data *rdata = 5603adfc5217SJeff Kirsher (struct function_start_data *)o->rdata; 5604adfc5217SJeff Kirsher dma_addr_t data_mapping = o->rdata_mapping; 5605adfc5217SJeff Kirsher struct bnx2x_func_start_params *start_params = ¶ms->params.start; 5606adfc5217SJeff Kirsher 5607adfc5217SJeff Kirsher memset(rdata, 0, sizeof(*rdata)); 5608adfc5217SJeff Kirsher 5609adfc5217SJeff Kirsher /* Fill the ramrod data with provided parameters */ 561096bed4b9SYuval Mintz rdata->function_mode = (u8)start_params->mf_mode; 5611ab4a7139SAriel Elior rdata->sd_vlan_tag = cpu_to_le16(start_params->sd_vlan_tag); 5612adfc5217SJeff Kirsher rdata->path_id = BP_PATH(bp); 5613adfc5217SJeff Kirsher rdata->network_cos_mode = start_params->network_cos_mode; 56141bc277f7SDmitry Kravkov rdata->gre_tunnel_mode = start_params->gre_tunnel_mode; 56151bc277f7SDmitry Kravkov rdata->gre_tunnel_rss = start_params->gre_tunnel_rss; 5616adfc5217SJeff Kirsher 56171bc277f7SDmitry Kravkov /* No need for an explicit memory barrier here as long we would 5618adfc5217SJeff Kirsher * need to ensure the ordering of writing to the SPQ element 5619adfc5217SJeff Kirsher * and updating of the SPQ producer which involves a memory 5620adfc5217SJeff Kirsher * read and we will have to put a full memory barrier there 5621adfc5217SJeff Kirsher * (inside bnx2x_sp_post()). 5622adfc5217SJeff Kirsher */ 5623adfc5217SJeff Kirsher 5624adfc5217SJeff Kirsher return bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_FUNCTION_START, 0, 5625adfc5217SJeff Kirsher U64_HI(data_mapping), 5626adfc5217SJeff Kirsher U64_LO(data_mapping), NONE_CONNECTION_TYPE); 5627adfc5217SJeff Kirsher } 5628adfc5217SJeff Kirsher 562955c11941SMerav Sicron static inline int bnx2x_func_send_switch_update(struct bnx2x *bp, 563055c11941SMerav Sicron struct bnx2x_func_state_params *params) 563155c11941SMerav Sicron { 563255c11941SMerav Sicron struct bnx2x_func_sp_obj *o = params->f_obj; 563355c11941SMerav Sicron struct function_update_data *rdata = 563455c11941SMerav Sicron (struct function_update_data *)o->rdata; 563555c11941SMerav Sicron dma_addr_t data_mapping = o->rdata_mapping; 563655c11941SMerav Sicron struct bnx2x_func_switch_update_params *switch_update_params = 563755c11941SMerav Sicron ¶ms->params.switch_update; 563855c11941SMerav Sicron 563955c11941SMerav Sicron memset(rdata, 0, sizeof(*rdata)); 564055c11941SMerav Sicron 564155c11941SMerav Sicron /* Fill the ramrod data with provided parameters */ 564255c11941SMerav Sicron rdata->tx_switch_suspend_change_flg = 1; 564355c11941SMerav Sicron rdata->tx_switch_suspend = switch_update_params->suspend; 564455c11941SMerav Sicron rdata->echo = SWITCH_UPDATE; 564555c11941SMerav Sicron 564655c11941SMerav Sicron return bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_FUNCTION_UPDATE, 0, 564755c11941SMerav Sicron U64_HI(data_mapping), 564855c11941SMerav Sicron U64_LO(data_mapping), NONE_CONNECTION_TYPE); 564955c11941SMerav Sicron } 565055c11941SMerav Sicron 5651a3348722SBarak Witkowski static inline int bnx2x_func_send_afex_update(struct bnx2x *bp, 5652a3348722SBarak Witkowski struct bnx2x_func_state_params *params) 5653a3348722SBarak Witkowski { 5654a3348722SBarak Witkowski struct bnx2x_func_sp_obj *o = params->f_obj; 5655a3348722SBarak Witkowski struct function_update_data *rdata = 5656a3348722SBarak Witkowski (struct function_update_data *)o->afex_rdata; 5657a3348722SBarak Witkowski dma_addr_t data_mapping = o->afex_rdata_mapping; 5658a3348722SBarak Witkowski struct bnx2x_func_afex_update_params *afex_update_params = 5659a3348722SBarak Witkowski ¶ms->params.afex_update; 5660a3348722SBarak Witkowski 5661a3348722SBarak Witkowski memset(rdata, 0, sizeof(*rdata)); 5662a3348722SBarak Witkowski 5663a3348722SBarak Witkowski /* Fill the ramrod data with provided parameters */ 5664a3348722SBarak Witkowski rdata->vif_id_change_flg = 1; 5665a3348722SBarak Witkowski rdata->vif_id = cpu_to_le16(afex_update_params->vif_id); 5666a3348722SBarak Witkowski rdata->afex_default_vlan_change_flg = 1; 5667a3348722SBarak Witkowski rdata->afex_default_vlan = 5668a3348722SBarak Witkowski cpu_to_le16(afex_update_params->afex_default_vlan); 5669a3348722SBarak Witkowski rdata->allowed_priorities_change_flg = 1; 5670a3348722SBarak Witkowski rdata->allowed_priorities = afex_update_params->allowed_priorities; 567155c11941SMerav Sicron rdata->echo = AFEX_UPDATE; 5672a3348722SBarak Witkowski 5673a3348722SBarak Witkowski /* No need for an explicit memory barrier here as long we would 5674a3348722SBarak Witkowski * need to ensure the ordering of writing to the SPQ element 5675a3348722SBarak Witkowski * and updating of the SPQ producer which involves a memory 5676a3348722SBarak Witkowski * read and we will have to put a full memory barrier there 5677a3348722SBarak Witkowski * (inside bnx2x_sp_post()). 5678a3348722SBarak Witkowski */ 5679a3348722SBarak Witkowski DP(BNX2X_MSG_SP, 5680a3348722SBarak Witkowski "afex: sending func_update vif_id 0x%x dvlan 0x%x prio 0x%x\n", 5681a3348722SBarak Witkowski rdata->vif_id, 5682a3348722SBarak Witkowski rdata->afex_default_vlan, rdata->allowed_priorities); 5683a3348722SBarak Witkowski 5684a3348722SBarak Witkowski return bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_FUNCTION_UPDATE, 0, 5685a3348722SBarak Witkowski U64_HI(data_mapping), 5686a3348722SBarak Witkowski U64_LO(data_mapping), NONE_CONNECTION_TYPE); 5687a3348722SBarak Witkowski } 5688a3348722SBarak Witkowski 5689a3348722SBarak Witkowski static 5690a3348722SBarak Witkowski inline int bnx2x_func_send_afex_viflists(struct bnx2x *bp, 5691a3348722SBarak Witkowski struct bnx2x_func_state_params *params) 5692a3348722SBarak Witkowski { 5693a3348722SBarak Witkowski struct bnx2x_func_sp_obj *o = params->f_obj; 5694a3348722SBarak Witkowski struct afex_vif_list_ramrod_data *rdata = 5695a3348722SBarak Witkowski (struct afex_vif_list_ramrod_data *)o->afex_rdata; 569686564c3fSYuval Mintz struct bnx2x_func_afex_viflists_params *afex_vif_params = 5697a3348722SBarak Witkowski ¶ms->params.afex_viflists; 5698a3348722SBarak Witkowski u64 *p_rdata = (u64 *)rdata; 5699a3348722SBarak Witkowski 5700a3348722SBarak Witkowski memset(rdata, 0, sizeof(*rdata)); 5701a3348722SBarak Witkowski 5702a3348722SBarak Witkowski /* Fill the ramrod data with provided parameters */ 570386564c3fSYuval Mintz rdata->vif_list_index = cpu_to_le16(afex_vif_params->vif_list_index); 570486564c3fSYuval Mintz rdata->func_bit_map = afex_vif_params->func_bit_map; 570586564c3fSYuval Mintz rdata->afex_vif_list_command = afex_vif_params->afex_vif_list_command; 570686564c3fSYuval Mintz rdata->func_to_clear = afex_vif_params->func_to_clear; 5707a3348722SBarak Witkowski 5708a3348722SBarak Witkowski /* send in echo type of sub command */ 570986564c3fSYuval Mintz rdata->echo = afex_vif_params->afex_vif_list_command; 5710a3348722SBarak Witkowski 5711a3348722SBarak Witkowski /* No need for an explicit memory barrier here as long we would 5712a3348722SBarak Witkowski * need to ensure the ordering of writing to the SPQ element 5713a3348722SBarak Witkowski * and updating of the SPQ producer which involves a memory 5714a3348722SBarak Witkowski * read and we will have to put a full memory barrier there 5715a3348722SBarak Witkowski * (inside bnx2x_sp_post()). 5716a3348722SBarak Witkowski */ 5717a3348722SBarak Witkowski 5718a3348722SBarak Witkowski DP(BNX2X_MSG_SP, "afex: ramrod lists, cmd 0x%x index 0x%x func_bit_map 0x%x func_to_clr 0x%x\n", 5719a3348722SBarak Witkowski rdata->afex_vif_list_command, rdata->vif_list_index, 5720a3348722SBarak Witkowski rdata->func_bit_map, rdata->func_to_clear); 5721a3348722SBarak Witkowski 5722a3348722SBarak Witkowski /* this ramrod sends data directly and not through DMA mapping */ 5723a3348722SBarak Witkowski return bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_AFEX_VIF_LISTS, 0, 5724a3348722SBarak Witkowski U64_HI(*p_rdata), U64_LO(*p_rdata), 5725a3348722SBarak Witkowski NONE_CONNECTION_TYPE); 5726a3348722SBarak Witkowski } 5727a3348722SBarak Witkowski 5728adfc5217SJeff Kirsher static inline int bnx2x_func_send_stop(struct bnx2x *bp, 5729adfc5217SJeff Kirsher struct bnx2x_func_state_params *params) 5730adfc5217SJeff Kirsher { 5731adfc5217SJeff Kirsher return bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_FUNCTION_STOP, 0, 0, 0, 5732adfc5217SJeff Kirsher NONE_CONNECTION_TYPE); 5733adfc5217SJeff Kirsher } 5734adfc5217SJeff Kirsher 5735adfc5217SJeff Kirsher static inline int bnx2x_func_send_tx_stop(struct bnx2x *bp, 5736adfc5217SJeff Kirsher struct bnx2x_func_state_params *params) 5737adfc5217SJeff Kirsher { 5738adfc5217SJeff Kirsher return bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_STOP_TRAFFIC, 0, 0, 0, 5739adfc5217SJeff Kirsher NONE_CONNECTION_TYPE); 5740adfc5217SJeff Kirsher } 5741adfc5217SJeff Kirsher static inline int bnx2x_func_send_tx_start(struct bnx2x *bp, 5742adfc5217SJeff Kirsher struct bnx2x_func_state_params *params) 5743adfc5217SJeff Kirsher { 5744adfc5217SJeff Kirsher struct bnx2x_func_sp_obj *o = params->f_obj; 5745adfc5217SJeff Kirsher struct flow_control_configuration *rdata = 5746adfc5217SJeff Kirsher (struct flow_control_configuration *)o->rdata; 5747adfc5217SJeff Kirsher dma_addr_t data_mapping = o->rdata_mapping; 5748adfc5217SJeff Kirsher struct bnx2x_func_tx_start_params *tx_start_params = 5749adfc5217SJeff Kirsher ¶ms->params.tx_start; 5750adfc5217SJeff Kirsher int i; 5751adfc5217SJeff Kirsher 5752adfc5217SJeff Kirsher memset(rdata, 0, sizeof(*rdata)); 5753adfc5217SJeff Kirsher 5754adfc5217SJeff Kirsher rdata->dcb_enabled = tx_start_params->dcb_enabled; 5755adfc5217SJeff Kirsher rdata->dcb_version = tx_start_params->dcb_version; 5756adfc5217SJeff Kirsher rdata->dont_add_pri_0_en = tx_start_params->dont_add_pri_0_en; 5757adfc5217SJeff Kirsher 5758adfc5217SJeff Kirsher for (i = 0; i < ARRAY_SIZE(rdata->traffic_type_to_priority_cos); i++) 5759adfc5217SJeff Kirsher rdata->traffic_type_to_priority_cos[i] = 5760adfc5217SJeff Kirsher tx_start_params->traffic_type_to_priority_cos[i]; 5761adfc5217SJeff Kirsher 5762adfc5217SJeff Kirsher return bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_START_TRAFFIC, 0, 5763adfc5217SJeff Kirsher U64_HI(data_mapping), 5764adfc5217SJeff Kirsher U64_LO(data_mapping), NONE_CONNECTION_TYPE); 5765adfc5217SJeff Kirsher } 5766adfc5217SJeff Kirsher 5767adfc5217SJeff Kirsher static int bnx2x_func_send_cmd(struct bnx2x *bp, 5768adfc5217SJeff Kirsher struct bnx2x_func_state_params *params) 5769adfc5217SJeff Kirsher { 5770adfc5217SJeff Kirsher switch (params->cmd) { 5771adfc5217SJeff Kirsher case BNX2X_F_CMD_HW_INIT: 5772adfc5217SJeff Kirsher return bnx2x_func_hw_init(bp, params); 5773adfc5217SJeff Kirsher case BNX2X_F_CMD_START: 5774adfc5217SJeff Kirsher return bnx2x_func_send_start(bp, params); 5775adfc5217SJeff Kirsher case BNX2X_F_CMD_STOP: 5776adfc5217SJeff Kirsher return bnx2x_func_send_stop(bp, params); 5777adfc5217SJeff Kirsher case BNX2X_F_CMD_HW_RESET: 5778adfc5217SJeff Kirsher return bnx2x_func_hw_reset(bp, params); 5779a3348722SBarak Witkowski case BNX2X_F_CMD_AFEX_UPDATE: 5780a3348722SBarak Witkowski return bnx2x_func_send_afex_update(bp, params); 5781a3348722SBarak Witkowski case BNX2X_F_CMD_AFEX_VIFLISTS: 5782a3348722SBarak Witkowski return bnx2x_func_send_afex_viflists(bp, params); 5783adfc5217SJeff Kirsher case BNX2X_F_CMD_TX_STOP: 5784adfc5217SJeff Kirsher return bnx2x_func_send_tx_stop(bp, params); 5785adfc5217SJeff Kirsher case BNX2X_F_CMD_TX_START: 5786adfc5217SJeff Kirsher return bnx2x_func_send_tx_start(bp, params); 578755c11941SMerav Sicron case BNX2X_F_CMD_SWITCH_UPDATE: 578855c11941SMerav Sicron return bnx2x_func_send_switch_update(bp, params); 5789adfc5217SJeff Kirsher default: 5790adfc5217SJeff Kirsher BNX2X_ERR("Unknown command: %d\n", params->cmd); 5791adfc5217SJeff Kirsher return -EINVAL; 5792adfc5217SJeff Kirsher } 5793adfc5217SJeff Kirsher } 5794adfc5217SJeff Kirsher 5795adfc5217SJeff Kirsher void bnx2x_init_func_obj(struct bnx2x *bp, 5796adfc5217SJeff Kirsher struct bnx2x_func_sp_obj *obj, 5797adfc5217SJeff Kirsher void *rdata, dma_addr_t rdata_mapping, 5798a3348722SBarak Witkowski void *afex_rdata, dma_addr_t afex_rdata_mapping, 5799adfc5217SJeff Kirsher struct bnx2x_func_sp_drv_ops *drv_iface) 5800adfc5217SJeff Kirsher { 5801adfc5217SJeff Kirsher memset(obj, 0, sizeof(*obj)); 5802adfc5217SJeff Kirsher 5803adfc5217SJeff Kirsher mutex_init(&obj->one_pending_mutex); 5804adfc5217SJeff Kirsher 5805adfc5217SJeff Kirsher obj->rdata = rdata; 5806adfc5217SJeff Kirsher obj->rdata_mapping = rdata_mapping; 5807a3348722SBarak Witkowski obj->afex_rdata = afex_rdata; 5808a3348722SBarak Witkowski obj->afex_rdata_mapping = afex_rdata_mapping; 5809adfc5217SJeff Kirsher obj->send_cmd = bnx2x_func_send_cmd; 5810adfc5217SJeff Kirsher obj->check_transition = bnx2x_func_chk_transition; 5811adfc5217SJeff Kirsher obj->complete_cmd = bnx2x_func_comp_cmd; 5812adfc5217SJeff Kirsher obj->wait_comp = bnx2x_func_wait_comp; 5813adfc5217SJeff Kirsher 5814adfc5217SJeff Kirsher obj->drv = drv_iface; 5815adfc5217SJeff Kirsher } 5816adfc5217SJeff Kirsher 5817adfc5217SJeff Kirsher /** 5818adfc5217SJeff Kirsher * bnx2x_func_state_change - perform Function state change transition 5819adfc5217SJeff Kirsher * 5820adfc5217SJeff Kirsher * @bp: device handle 5821adfc5217SJeff Kirsher * @params: parameters to perform the transaction 5822adfc5217SJeff Kirsher * 5823adfc5217SJeff Kirsher * returns 0 in case of successfully completed transition, 5824adfc5217SJeff Kirsher * negative error code in case of failure, positive 5825adfc5217SJeff Kirsher * (EBUSY) value if there is a completion to that is 5826adfc5217SJeff Kirsher * still pending (possible only if RAMROD_COMP_WAIT is 5827adfc5217SJeff Kirsher * not set in params->ramrod_flags for asynchronous 5828adfc5217SJeff Kirsher * commands). 5829adfc5217SJeff Kirsher */ 5830adfc5217SJeff Kirsher int bnx2x_func_state_change(struct bnx2x *bp, 5831adfc5217SJeff Kirsher struct bnx2x_func_state_params *params) 5832adfc5217SJeff Kirsher { 5833adfc5217SJeff Kirsher struct bnx2x_func_sp_obj *o = params->f_obj; 583455c11941SMerav Sicron int rc, cnt = 300; 5835adfc5217SJeff Kirsher enum bnx2x_func_cmd cmd = params->cmd; 5836adfc5217SJeff Kirsher unsigned long *pending = &o->pending; 5837adfc5217SJeff Kirsher 5838adfc5217SJeff Kirsher mutex_lock(&o->one_pending_mutex); 5839adfc5217SJeff Kirsher 5840adfc5217SJeff Kirsher /* Check that the requested transition is legal */ 584155c11941SMerav Sicron rc = o->check_transition(bp, o, params); 584255c11941SMerav Sicron if ((rc == -EBUSY) && 584355c11941SMerav Sicron (test_bit(RAMROD_RETRY, ¶ms->ramrod_flags))) { 584455c11941SMerav Sicron while ((rc == -EBUSY) && (--cnt > 0)) { 5845adfc5217SJeff Kirsher mutex_unlock(&o->one_pending_mutex); 584655c11941SMerav Sicron msleep(10); 584755c11941SMerav Sicron mutex_lock(&o->one_pending_mutex); 584855c11941SMerav Sicron rc = o->check_transition(bp, o, params); 584955c11941SMerav Sicron } 585055c11941SMerav Sicron if (rc == -EBUSY) { 585155c11941SMerav Sicron mutex_unlock(&o->one_pending_mutex); 585255c11941SMerav Sicron BNX2X_ERR("timeout waiting for previous ramrod completion\n"); 585355c11941SMerav Sicron return rc; 585455c11941SMerav Sicron } 585555c11941SMerav Sicron } else if (rc) { 585655c11941SMerav Sicron mutex_unlock(&o->one_pending_mutex); 585755c11941SMerav Sicron return rc; 5858adfc5217SJeff Kirsher } 5859adfc5217SJeff Kirsher 5860adfc5217SJeff Kirsher /* Set "pending" bit */ 5861adfc5217SJeff Kirsher set_bit(cmd, pending); 5862adfc5217SJeff Kirsher 5863adfc5217SJeff Kirsher /* Don't send a command if only driver cleanup was requested */ 5864adfc5217SJeff Kirsher if (test_bit(RAMROD_DRV_CLR_ONLY, ¶ms->ramrod_flags)) { 5865adfc5217SJeff Kirsher bnx2x_func_state_change_comp(bp, o, cmd); 5866adfc5217SJeff Kirsher mutex_unlock(&o->one_pending_mutex); 5867adfc5217SJeff Kirsher } else { 5868adfc5217SJeff Kirsher /* Send a ramrod */ 5869adfc5217SJeff Kirsher rc = o->send_cmd(bp, params); 5870adfc5217SJeff Kirsher 5871adfc5217SJeff Kirsher mutex_unlock(&o->one_pending_mutex); 5872adfc5217SJeff Kirsher 5873adfc5217SJeff Kirsher if (rc) { 5874adfc5217SJeff Kirsher o->next_state = BNX2X_F_STATE_MAX; 5875adfc5217SJeff Kirsher clear_bit(cmd, pending); 5876adfc5217SJeff Kirsher smp_mb__after_clear_bit(); 5877adfc5217SJeff Kirsher return rc; 5878adfc5217SJeff Kirsher } 5879adfc5217SJeff Kirsher 5880adfc5217SJeff Kirsher if (test_bit(RAMROD_COMP_WAIT, ¶ms->ramrod_flags)) { 5881adfc5217SJeff Kirsher rc = o->wait_comp(bp, o, cmd); 5882adfc5217SJeff Kirsher if (rc) 5883adfc5217SJeff Kirsher return rc; 5884adfc5217SJeff Kirsher 5885adfc5217SJeff Kirsher return 0; 5886adfc5217SJeff Kirsher } 5887adfc5217SJeff Kirsher } 5888adfc5217SJeff Kirsher 5889adfc5217SJeff Kirsher return !!test_bit(cmd, pending); 5890adfc5217SJeff Kirsher } 5891