1 /* Copyright 2008-2013 Broadcom Corporation 2 * Copyright (c) 2014 QLogic Corporation 3 * All rights reserved 4 * 5 * Unless you and QLogic execute a separate written software license 6 * agreement governing use of this software, this software is licensed to you 7 * under the terms of the GNU General Public License version 2, available 8 * at http://www.gnu.org/licenses/gpl-2.0.html (the "GPL"). 9 * 10 * Notwithstanding the above, under no circumstances may you combine this 11 * software in any way with any other Qlogic software provided under a 12 * license other than the GPL, without Qlogic's express prior written 13 * consent. 14 * 15 * Written by Yaniv Rosner 16 * 17 */ 18 19 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 20 21 #include <linux/kernel.h> 22 #include <linux/errno.h> 23 #include <linux/pci.h> 24 #include <linux/netdevice.h> 25 #include <linux/delay.h> 26 #include <linux/ethtool.h> 27 #include <linux/mutex.h> 28 29 #include "bnx2x.h" 30 #include "bnx2x_cmn.h" 31 32 typedef int (*read_sfp_module_eeprom_func_p)(struct bnx2x_phy *phy, 33 struct link_params *params, 34 u8 dev_addr, u16 addr, u8 byte_cnt, 35 u8 *o_buf, u8); 36 /********************************************************/ 37 #define MDIO_ACCESS_TIMEOUT 1000 38 #define WC_LANE_MAX 4 39 #define I2C_SWITCH_WIDTH 2 40 #define I2C_BSC0 0 41 #define I2C_BSC1 1 42 #define I2C_WA_RETRY_CNT 3 43 #define I2C_WA_PWR_ITER (I2C_WA_RETRY_CNT - 1) 44 #define MCPR_IMC_COMMAND_READ_OP 1 45 #define MCPR_IMC_COMMAND_WRITE_OP 2 46 47 /* LED Blink rate that will achieve ~15.9Hz */ 48 #define LED_BLINK_RATE_VAL_E3 354 49 #define LED_BLINK_RATE_VAL_E1X_E2 480 50 /***********************************************************/ 51 /* Shortcut definitions */ 52 /***********************************************************/ 53 54 #define NIG_LATCH_BC_ENABLE_MI_INT 0 55 56 #define NIG_STATUS_EMAC0_MI_INT \ 57 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT 58 #define NIG_STATUS_XGXS0_LINK10G \ 59 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G 60 #define NIG_STATUS_XGXS0_LINK_STATUS \ 61 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS 62 #define NIG_STATUS_XGXS0_LINK_STATUS_SIZE \ 63 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE 64 #define NIG_STATUS_SERDES0_LINK_STATUS \ 65 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS 66 #define NIG_MASK_MI_INT \ 67 NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT 68 #define NIG_MASK_XGXS0_LINK10G \ 69 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G 70 #define NIG_MASK_XGXS0_LINK_STATUS \ 71 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS 72 #define NIG_MASK_SERDES0_LINK_STATUS \ 73 NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS 74 75 #define MDIO_AN_CL73_OR_37_COMPLETE \ 76 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \ 77 MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE) 78 79 #define XGXS_RESET_BITS \ 80 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW | \ 81 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ | \ 82 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN | \ 83 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \ 84 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB) 85 86 #define SERDES_RESET_BITS \ 87 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \ 88 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ | \ 89 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN | \ 90 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD) 91 92 #define AUTONEG_CL37 SHARED_HW_CFG_AN_ENABLE_CL37 93 #define AUTONEG_CL73 SHARED_HW_CFG_AN_ENABLE_CL73 94 #define AUTONEG_BAM SHARED_HW_CFG_AN_ENABLE_BAM 95 #define AUTONEG_PARALLEL \ 96 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION 97 #define AUTONEG_SGMII_FIBER_AUTODET \ 98 SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT 99 #define AUTONEG_REMOTE_PHY SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY 100 101 #define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \ 102 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE 103 #define GP_STATUS_PAUSE_RSOLUTION_RXSIDE \ 104 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE 105 #define GP_STATUS_SPEED_MASK \ 106 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK 107 #define GP_STATUS_10M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M 108 #define GP_STATUS_100M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M 109 #define GP_STATUS_1G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G 110 #define GP_STATUS_2_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G 111 #define GP_STATUS_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G 112 #define GP_STATUS_6G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G 113 #define GP_STATUS_10G_HIG \ 114 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG 115 #define GP_STATUS_10G_CX4 \ 116 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4 117 #define GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX 118 #define GP_STATUS_10G_KX4 \ 119 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4 120 #define GP_STATUS_10G_KR MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR 121 #define GP_STATUS_10G_XFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI 122 #define GP_STATUS_20G_DXGXS MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS 123 #define GP_STATUS_10G_SFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI 124 #define GP_STATUS_20G_KR2 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_KR2 125 #define LINK_10THD LINK_STATUS_SPEED_AND_DUPLEX_10THD 126 #define LINK_10TFD LINK_STATUS_SPEED_AND_DUPLEX_10TFD 127 #define LINK_100TXHD LINK_STATUS_SPEED_AND_DUPLEX_100TXHD 128 #define LINK_100T4 LINK_STATUS_SPEED_AND_DUPLEX_100T4 129 #define LINK_100TXFD LINK_STATUS_SPEED_AND_DUPLEX_100TXFD 130 #define LINK_1000THD LINK_STATUS_SPEED_AND_DUPLEX_1000THD 131 #define LINK_1000TFD LINK_STATUS_SPEED_AND_DUPLEX_1000TFD 132 #define LINK_1000XFD LINK_STATUS_SPEED_AND_DUPLEX_1000XFD 133 #define LINK_2500THD LINK_STATUS_SPEED_AND_DUPLEX_2500THD 134 #define LINK_2500TFD LINK_STATUS_SPEED_AND_DUPLEX_2500TFD 135 #define LINK_2500XFD LINK_STATUS_SPEED_AND_DUPLEX_2500XFD 136 #define LINK_10GTFD LINK_STATUS_SPEED_AND_DUPLEX_10GTFD 137 #define LINK_10GXFD LINK_STATUS_SPEED_AND_DUPLEX_10GXFD 138 #define LINK_20GTFD LINK_STATUS_SPEED_AND_DUPLEX_20GTFD 139 #define LINK_20GXFD LINK_STATUS_SPEED_AND_DUPLEX_20GXFD 140 141 #define LINK_UPDATE_MASK \ 142 (LINK_STATUS_SPEED_AND_DUPLEX_MASK | \ 143 LINK_STATUS_LINK_UP | \ 144 LINK_STATUS_PHYSICAL_LINK_FLAG | \ 145 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE | \ 146 LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK | \ 147 LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK | \ 148 LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK | \ 149 LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE | \ 150 LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE) 151 152 #define SFP_EEPROM_CON_TYPE_ADDR 0x2 153 #define SFP_EEPROM_CON_TYPE_VAL_UNKNOWN 0x0 154 #define SFP_EEPROM_CON_TYPE_VAL_LC 0x7 155 #define SFP_EEPROM_CON_TYPE_VAL_COPPER 0x21 156 #define SFP_EEPROM_CON_TYPE_VAL_RJ45 0x22 157 158 159 #define SFP_EEPROM_10G_COMP_CODE_ADDR 0x3 160 #define SFP_EEPROM_10G_COMP_CODE_SR_MASK (1<<4) 161 #define SFP_EEPROM_10G_COMP_CODE_LR_MASK (1<<5) 162 #define SFP_EEPROM_10G_COMP_CODE_LRM_MASK (1<<6) 163 164 #define SFP_EEPROM_1G_COMP_CODE_ADDR 0x6 165 #define SFP_EEPROM_1G_COMP_CODE_SX (1<<0) 166 #define SFP_EEPROM_1G_COMP_CODE_LX (1<<1) 167 #define SFP_EEPROM_1G_COMP_CODE_CX (1<<2) 168 #define SFP_EEPROM_1G_COMP_CODE_BASE_T (1<<3) 169 170 #define SFP_EEPROM_FC_TX_TECH_ADDR 0x8 171 #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4 172 #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE 0x8 173 174 #define SFP_EEPROM_OPTIONS_ADDR 0x40 175 #define SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1 176 #define SFP_EEPROM_OPTIONS_SIZE 2 177 178 #define EDC_MODE_LINEAR 0x0022 179 #define EDC_MODE_LIMITING 0x0044 180 #define EDC_MODE_PASSIVE_DAC 0x0055 181 #define EDC_MODE_ACTIVE_DAC 0x0066 182 183 /* ETS defines*/ 184 #define DCBX_INVALID_COS (0xFF) 185 186 #define ETS_BW_LIMIT_CREDIT_UPPER_BOUND (0x5000) 187 #define ETS_BW_LIMIT_CREDIT_WEIGHT (0x5000) 188 #define ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS (1360) 189 #define ETS_E3B0_NIG_MIN_W_VAL_20GBPS (2720) 190 #define ETS_E3B0_PBF_MIN_W_VAL (10000) 191 192 #define MAX_PACKET_SIZE (9700) 193 #define MAX_KR_LINK_RETRY 4 194 #define DEFAULT_TX_DRV_BRDCT 2 195 #define DEFAULT_TX_DRV_IFIR 0 196 #define DEFAULT_TX_DRV_POST2 3 197 #define DEFAULT_TX_DRV_IPRE_DRIVER 6 198 199 /**********************************************************/ 200 /* INTERFACE */ 201 /**********************************************************/ 202 203 #define CL22_WR_OVER_CL45(_bp, _phy, _bank, _addr, _val) \ 204 bnx2x_cl45_write(_bp, _phy, \ 205 (_phy)->def_md_devad, \ 206 (_bank + (_addr & 0xf)), \ 207 _val) 208 209 #define CL22_RD_OVER_CL45(_bp, _phy, _bank, _addr, _val) \ 210 bnx2x_cl45_read(_bp, _phy, \ 211 (_phy)->def_md_devad, \ 212 (_bank + (_addr & 0xf)), \ 213 _val) 214 215 static int bnx2x_check_half_open_conn(struct link_params *params, 216 struct link_vars *vars, u8 notify); 217 static int bnx2x_sfp_module_detection(struct bnx2x_phy *phy, 218 struct link_params *params); 219 220 static u32 bnx2x_bits_en(struct bnx2x *bp, u32 reg, u32 bits) 221 { 222 u32 val = REG_RD(bp, reg); 223 224 val |= bits; 225 REG_WR(bp, reg, val); 226 return val; 227 } 228 229 static u32 bnx2x_bits_dis(struct bnx2x *bp, u32 reg, u32 bits) 230 { 231 u32 val = REG_RD(bp, reg); 232 233 val &= ~bits; 234 REG_WR(bp, reg, val); 235 return val; 236 } 237 238 /* 239 * bnx2x_check_lfa - This function checks if link reinitialization is required, 240 * or link flap can be avoided. 241 * 242 * @params: link parameters 243 * Returns 0 if Link Flap Avoidance conditions are met otherwise, the failed 244 * condition code. 245 */ 246 static int bnx2x_check_lfa(struct link_params *params) 247 { 248 u32 link_status, cfg_idx, lfa_mask, cfg_size; 249 u32 cur_speed_cap_mask, cur_req_fc_auto_adv, additional_config; 250 u32 saved_val, req_val, eee_status; 251 struct bnx2x *bp = params->bp; 252 253 additional_config = 254 REG_RD(bp, params->lfa_base + 255 offsetof(struct shmem_lfa, additional_config)); 256 257 /* NOTE: must be first condition checked - 258 * to verify DCC bit is cleared in any case! 259 */ 260 if (additional_config & NO_LFA_DUE_TO_DCC_MASK) { 261 DP(NETIF_MSG_LINK, "No LFA due to DCC flap after clp exit\n"); 262 REG_WR(bp, params->lfa_base + 263 offsetof(struct shmem_lfa, additional_config), 264 additional_config & ~NO_LFA_DUE_TO_DCC_MASK); 265 return LFA_DCC_LFA_DISABLED; 266 } 267 268 /* Verify that link is up */ 269 link_status = REG_RD(bp, params->shmem_base + 270 offsetof(struct shmem_region, 271 port_mb[params->port].link_status)); 272 if (!(link_status & LINK_STATUS_LINK_UP)) 273 return LFA_LINK_DOWN; 274 275 /* if loaded after BOOT from SAN, don't flap the link in any case and 276 * rely on link set by preboot driver 277 */ 278 if (params->feature_config_flags & FEATURE_CONFIG_BOOT_FROM_SAN) 279 return 0; 280 281 /* Verify that loopback mode is not set */ 282 if (params->loopback_mode) 283 return LFA_LOOPBACK_ENABLED; 284 285 /* Verify that MFW supports LFA */ 286 if (!params->lfa_base) 287 return LFA_MFW_IS_TOO_OLD; 288 289 if (params->num_phys == 3) { 290 cfg_size = 2; 291 lfa_mask = 0xffffffff; 292 } else { 293 cfg_size = 1; 294 lfa_mask = 0xffff; 295 } 296 297 /* Compare Duplex */ 298 saved_val = REG_RD(bp, params->lfa_base + 299 offsetof(struct shmem_lfa, req_duplex)); 300 req_val = params->req_duplex[0] | (params->req_duplex[1] << 16); 301 if ((saved_val & lfa_mask) != (req_val & lfa_mask)) { 302 DP(NETIF_MSG_LINK, "Duplex mismatch %x vs. %x\n", 303 (saved_val & lfa_mask), (req_val & lfa_mask)); 304 return LFA_DUPLEX_MISMATCH; 305 } 306 /* Compare Flow Control */ 307 saved_val = REG_RD(bp, params->lfa_base + 308 offsetof(struct shmem_lfa, req_flow_ctrl)); 309 req_val = params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16); 310 if ((saved_val & lfa_mask) != (req_val & lfa_mask)) { 311 DP(NETIF_MSG_LINK, "Flow control mismatch %x vs. %x\n", 312 (saved_val & lfa_mask), (req_val & lfa_mask)); 313 return LFA_FLOW_CTRL_MISMATCH; 314 } 315 /* Compare Link Speed */ 316 saved_val = REG_RD(bp, params->lfa_base + 317 offsetof(struct shmem_lfa, req_line_speed)); 318 req_val = params->req_line_speed[0] | (params->req_line_speed[1] << 16); 319 if ((saved_val & lfa_mask) != (req_val & lfa_mask)) { 320 DP(NETIF_MSG_LINK, "Link speed mismatch %x vs. %x\n", 321 (saved_val & lfa_mask), (req_val & lfa_mask)); 322 return LFA_LINK_SPEED_MISMATCH; 323 } 324 325 for (cfg_idx = 0; cfg_idx < cfg_size; cfg_idx++) { 326 cur_speed_cap_mask = REG_RD(bp, params->lfa_base + 327 offsetof(struct shmem_lfa, 328 speed_cap_mask[cfg_idx])); 329 330 if (cur_speed_cap_mask != params->speed_cap_mask[cfg_idx]) { 331 DP(NETIF_MSG_LINK, "Speed Cap mismatch %x vs. %x\n", 332 cur_speed_cap_mask, 333 params->speed_cap_mask[cfg_idx]); 334 return LFA_SPEED_CAP_MISMATCH; 335 } 336 } 337 338 cur_req_fc_auto_adv = 339 REG_RD(bp, params->lfa_base + 340 offsetof(struct shmem_lfa, additional_config)) & 341 REQ_FC_AUTO_ADV_MASK; 342 343 if ((u16)cur_req_fc_auto_adv != params->req_fc_auto_adv) { 344 DP(NETIF_MSG_LINK, "Flow Ctrl AN mismatch %x vs. %x\n", 345 cur_req_fc_auto_adv, params->req_fc_auto_adv); 346 return LFA_FLOW_CTRL_MISMATCH; 347 } 348 349 eee_status = REG_RD(bp, params->shmem2_base + 350 offsetof(struct shmem2_region, 351 eee_status[params->port])); 352 353 if (((eee_status & SHMEM_EEE_LPI_REQUESTED_BIT) ^ 354 (params->eee_mode & EEE_MODE_ENABLE_LPI)) || 355 ((eee_status & SHMEM_EEE_REQUESTED_BIT) ^ 356 (params->eee_mode & EEE_MODE_ADV_LPI))) { 357 DP(NETIF_MSG_LINK, "EEE mismatch %x vs. %x\n", params->eee_mode, 358 eee_status); 359 return LFA_EEE_MISMATCH; 360 } 361 362 /* LFA conditions are met */ 363 return 0; 364 } 365 /******************************************************************/ 366 /* EPIO/GPIO section */ 367 /******************************************************************/ 368 static void bnx2x_get_epio(struct bnx2x *bp, u32 epio_pin, u32 *en) 369 { 370 u32 epio_mask, gp_oenable; 371 *en = 0; 372 /* Sanity check */ 373 if (epio_pin > 31) { 374 DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to get\n", epio_pin); 375 return; 376 } 377 378 epio_mask = 1 << epio_pin; 379 /* Set this EPIO to output */ 380 gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE); 381 REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable & ~epio_mask); 382 383 *en = (REG_RD(bp, MCP_REG_MCPR_GP_INPUTS) & epio_mask) >> epio_pin; 384 } 385 static void bnx2x_set_epio(struct bnx2x *bp, u32 epio_pin, u32 en) 386 { 387 u32 epio_mask, gp_output, gp_oenable; 388 389 /* Sanity check */ 390 if (epio_pin > 31) { 391 DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to set\n", epio_pin); 392 return; 393 } 394 DP(NETIF_MSG_LINK, "Setting EPIO pin %d to %d\n", epio_pin, en); 395 epio_mask = 1 << epio_pin; 396 /* Set this EPIO to output */ 397 gp_output = REG_RD(bp, MCP_REG_MCPR_GP_OUTPUTS); 398 if (en) 399 gp_output |= epio_mask; 400 else 401 gp_output &= ~epio_mask; 402 403 REG_WR(bp, MCP_REG_MCPR_GP_OUTPUTS, gp_output); 404 405 /* Set the value for this EPIO */ 406 gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE); 407 REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable | epio_mask); 408 } 409 410 static void bnx2x_set_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 val) 411 { 412 if (pin_cfg == PIN_CFG_NA) 413 return; 414 if (pin_cfg >= PIN_CFG_EPIO0) { 415 bnx2x_set_epio(bp, pin_cfg - PIN_CFG_EPIO0, val); 416 } else { 417 u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3; 418 u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2; 419 bnx2x_set_gpio(bp, gpio_num, (u8)val, gpio_port); 420 } 421 } 422 423 static u32 bnx2x_get_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 *val) 424 { 425 if (pin_cfg == PIN_CFG_NA) 426 return -EINVAL; 427 if (pin_cfg >= PIN_CFG_EPIO0) { 428 bnx2x_get_epio(bp, pin_cfg - PIN_CFG_EPIO0, val); 429 } else { 430 u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3; 431 u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2; 432 *val = bnx2x_get_gpio(bp, gpio_num, gpio_port); 433 } 434 return 0; 435 436 } 437 /******************************************************************/ 438 /* ETS section */ 439 /******************************************************************/ 440 static void bnx2x_ets_e2e3a0_disabled(struct link_params *params) 441 { 442 /* ETS disabled configuration*/ 443 struct bnx2x *bp = params->bp; 444 445 DP(NETIF_MSG_LINK, "ETS E2E3 disabled configuration\n"); 446 447 /* mapping between entry priority to client number (0,1,2 -debug and 448 * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST) 449 * 3bits client num. 450 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0 451 * cos1-100 cos0-011 dbg1-010 dbg0-001 MCP-000 452 */ 453 454 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, 0x4688); 455 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves 456 * as strict. Bits 0,1,2 - debug and management entries, 3 - 457 * COS0 entry, 4 - COS1 entry. 458 * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT 459 * bit4 bit3 bit2 bit1 bit0 460 * MCP and debug are strict 461 */ 462 463 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7); 464 /* defines which entries (clients) are subjected to WFQ arbitration */ 465 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0); 466 /* For strict priority entries defines the number of consecutive 467 * slots for the highest priority. 468 */ 469 REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100); 470 /* mapping between the CREDIT_WEIGHT registers and actual client 471 * numbers 472 */ 473 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0); 474 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0); 475 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0); 476 477 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 0); 478 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 0); 479 REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, 0); 480 /* ETS mode disable */ 481 REG_WR(bp, PBF_REG_ETS_ENABLED, 0); 482 /* If ETS mode is enabled (there is no strict priority) defines a WFQ 483 * weight for COS0/COS1. 484 */ 485 REG_WR(bp, PBF_REG_COS0_WEIGHT, 0x2710); 486 REG_WR(bp, PBF_REG_COS1_WEIGHT, 0x2710); 487 /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter */ 488 REG_WR(bp, PBF_REG_COS0_UPPER_BOUND, 0x989680); 489 REG_WR(bp, PBF_REG_COS1_UPPER_BOUND, 0x989680); 490 /* Defines the number of consecutive slots for the strict priority */ 491 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0); 492 } 493 /****************************************************************************** 494 * Description: 495 * Getting min_w_val will be set according to line speed . 496 *. 497 ******************************************************************************/ 498 static u32 bnx2x_ets_get_min_w_val_nig(const struct link_vars *vars) 499 { 500 u32 min_w_val = 0; 501 /* Calculate min_w_val.*/ 502 if (vars->link_up) { 503 if (vars->line_speed == SPEED_20000) 504 min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS; 505 else 506 min_w_val = ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS; 507 } else 508 min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS; 509 /* If the link isn't up (static configuration for example ) The 510 * link will be according to 20GBPS. 511 */ 512 return min_w_val; 513 } 514 /****************************************************************************** 515 * Description: 516 * Getting credit upper bound form min_w_val. 517 *. 518 ******************************************************************************/ 519 static u32 bnx2x_ets_get_credit_upper_bound(const u32 min_w_val) 520 { 521 const u32 credit_upper_bound = (u32)MAXVAL((150 * min_w_val), 522 MAX_PACKET_SIZE); 523 return credit_upper_bound; 524 } 525 /****************************************************************************** 526 * Description: 527 * Set credit upper bound for NIG. 528 *. 529 ******************************************************************************/ 530 static void bnx2x_ets_e3b0_set_credit_upper_bound_nig( 531 const struct link_params *params, 532 const u32 min_w_val) 533 { 534 struct bnx2x *bp = params->bp; 535 const u8 port = params->port; 536 const u32 credit_upper_bound = 537 bnx2x_ets_get_credit_upper_bound(min_w_val); 538 539 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 : 540 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, credit_upper_bound); 541 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 : 542 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, credit_upper_bound); 543 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 : 544 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_2, credit_upper_bound); 545 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 : 546 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_3, credit_upper_bound); 547 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 : 548 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_4, credit_upper_bound); 549 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 : 550 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_5, credit_upper_bound); 551 552 if (!port) { 553 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6, 554 credit_upper_bound); 555 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7, 556 credit_upper_bound); 557 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8, 558 credit_upper_bound); 559 } 560 } 561 /****************************************************************************** 562 * Description: 563 * Will return the NIG ETS registers to init values.Except 564 * credit_upper_bound. 565 * That isn't used in this configuration (No WFQ is enabled) and will be 566 * configured according to spec 567 *. 568 ******************************************************************************/ 569 static void bnx2x_ets_e3b0_nig_disabled(const struct link_params *params, 570 const struct link_vars *vars) 571 { 572 struct bnx2x *bp = params->bp; 573 const u8 port = params->port; 574 const u32 min_w_val = bnx2x_ets_get_min_w_val_nig(vars); 575 /* Mapping between entry priority to client number (0,1,2 -debug and 576 * management clients, 3 - COS0 client, 4 - COS1, ... 8 - 577 * COS5)(HIGHEST) 4bits client num.TODO_ETS - Should be done by 578 * reset value or init tool 579 */ 580 if (port) { 581 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, 0x543210); 582 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB, 0x0); 583 } else { 584 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, 0x76543210); 585 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, 0x8); 586 } 587 /* For strict priority entries defines the number of consecutive 588 * slots for the highest priority. 589 */ 590 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS : 591 NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100); 592 /* Mapping between the CREDIT_WEIGHT registers and actual client 593 * numbers 594 */ 595 if (port) { 596 /*Port 1 has 6 COS*/ 597 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB, 0x210543); 598 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x0); 599 } else { 600 /*Port 0 has 9 COS*/ 601 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB, 602 0x43210876); 603 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x5); 604 } 605 606 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves 607 * as strict. Bits 0,1,2 - debug and management entries, 3 - 608 * COS0 entry, 4 - COS1 entry. 609 * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT 610 * bit4 bit3 bit2 bit1 bit0 611 * MCP and debug are strict 612 */ 613 if (port) 614 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT, 0x3f); 615 else 616 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1ff); 617 /* defines which entries (clients) are subjected to WFQ arbitration */ 618 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ : 619 NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0); 620 621 /* Please notice the register address are note continuous and a 622 * for here is note appropriate.In 2 port mode port0 only COS0-5 623 * can be used. DEBUG1,DEBUG1,MGMT are never used for WFQ* In 4 624 * port mode port1 only COS0-2 can be used. DEBUG1,DEBUG1,MGMT 625 * are never used for WFQ 626 */ 627 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 : 628 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0x0); 629 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 : 630 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0x0); 631 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 : 632 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2, 0x0); 633 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 : 634 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3, 0x0); 635 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 : 636 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4, 0x0); 637 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 : 638 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5, 0x0); 639 if (!port) { 640 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6, 0x0); 641 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7, 0x0); 642 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8, 0x0); 643 } 644 645 bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val); 646 } 647 /****************************************************************************** 648 * Description: 649 * Set credit upper bound for PBF. 650 *. 651 ******************************************************************************/ 652 static void bnx2x_ets_e3b0_set_credit_upper_bound_pbf( 653 const struct link_params *params, 654 const u32 min_w_val) 655 { 656 struct bnx2x *bp = params->bp; 657 const u32 credit_upper_bound = 658 bnx2x_ets_get_credit_upper_bound(min_w_val); 659 const u8 port = params->port; 660 u32 base_upper_bound = 0; 661 u8 max_cos = 0; 662 u8 i = 0; 663 /* In 2 port mode port0 has COS0-5 that can be used for WFQ.In 4 664 * port mode port1 has COS0-2 that can be used for WFQ. 665 */ 666 if (!port) { 667 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P0; 668 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0; 669 } else { 670 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P1; 671 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT1; 672 } 673 674 for (i = 0; i < max_cos; i++) 675 REG_WR(bp, base_upper_bound + (i << 2), credit_upper_bound); 676 } 677 678 /****************************************************************************** 679 * Description: 680 * Will return the PBF ETS registers to init values.Except 681 * credit_upper_bound. 682 * That isn't used in this configuration (No WFQ is enabled) and will be 683 * configured according to spec 684 *. 685 ******************************************************************************/ 686 static void bnx2x_ets_e3b0_pbf_disabled(const struct link_params *params) 687 { 688 struct bnx2x *bp = params->bp; 689 const u8 port = params->port; 690 const u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL; 691 u8 i = 0; 692 u32 base_weight = 0; 693 u8 max_cos = 0; 694 695 /* Mapping between entry priority to client number 0 - COS0 696 * client, 2 - COS1, ... 5 - COS5)(HIGHEST) 4bits client num. 697 * TODO_ETS - Should be done by reset value or init tool 698 */ 699 if (port) 700 /* 0x688 (|011|0 10|00 1|000) */ 701 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , 0x688); 702 else 703 /* (10 1|100 |011|0 10|00 1|000) */ 704 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , 0x2C688); 705 706 /* TODO_ETS - Should be done by reset value or init tool */ 707 if (port) 708 /* 0x688 (|011|0 10|00 1|000)*/ 709 REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1, 0x688); 710 else 711 /* 0x2C688 (10 1|100 |011|0 10|00 1|000) */ 712 REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0, 0x2C688); 713 714 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 : 715 PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0 , 0x100); 716 717 718 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 : 719 PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , 0); 720 721 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 : 722 PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0 , 0); 723 /* In 2 port mode port0 has COS0-5 that can be used for WFQ. 724 * In 4 port mode port1 has COS0-2 that can be used for WFQ. 725 */ 726 if (!port) { 727 base_weight = PBF_REG_COS0_WEIGHT_P0; 728 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0; 729 } else { 730 base_weight = PBF_REG_COS0_WEIGHT_P1; 731 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT1; 732 } 733 734 for (i = 0; i < max_cos; i++) 735 REG_WR(bp, base_weight + (0x4 * i), 0); 736 737 bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf); 738 } 739 /****************************************************************************** 740 * Description: 741 * E3B0 disable will return basically the values to init values. 742 *. 743 ******************************************************************************/ 744 static int bnx2x_ets_e3b0_disabled(const struct link_params *params, 745 const struct link_vars *vars) 746 { 747 struct bnx2x *bp = params->bp; 748 749 if (!CHIP_IS_E3B0(bp)) { 750 DP(NETIF_MSG_LINK, 751 "bnx2x_ets_e3b0_disabled the chip isn't E3B0\n"); 752 return -EINVAL; 753 } 754 755 bnx2x_ets_e3b0_nig_disabled(params, vars); 756 757 bnx2x_ets_e3b0_pbf_disabled(params); 758 759 return 0; 760 } 761 762 /****************************************************************************** 763 * Description: 764 * Disable will return basically the values to init values. 765 * 766 ******************************************************************************/ 767 int bnx2x_ets_disabled(struct link_params *params, 768 struct link_vars *vars) 769 { 770 struct bnx2x *bp = params->bp; 771 int bnx2x_status = 0; 772 773 if ((CHIP_IS_E2(bp)) || (CHIP_IS_E3A0(bp))) 774 bnx2x_ets_e2e3a0_disabled(params); 775 else if (CHIP_IS_E3B0(bp)) 776 bnx2x_status = bnx2x_ets_e3b0_disabled(params, vars); 777 else { 778 DP(NETIF_MSG_LINK, "bnx2x_ets_disabled - chip not supported\n"); 779 return -EINVAL; 780 } 781 782 return bnx2x_status; 783 } 784 785 /****************************************************************************** 786 * Description 787 * Set the COS mappimg to SP and BW until this point all the COS are not 788 * set as SP or BW. 789 ******************************************************************************/ 790 static int bnx2x_ets_e3b0_cli_map(const struct link_params *params, 791 const struct bnx2x_ets_params *ets_params, 792 const u8 cos_sp_bitmap, 793 const u8 cos_bw_bitmap) 794 { 795 struct bnx2x *bp = params->bp; 796 const u8 port = params->port; 797 const u8 nig_cli_sp_bitmap = 0x7 | (cos_sp_bitmap << 3); 798 const u8 pbf_cli_sp_bitmap = cos_sp_bitmap; 799 const u8 nig_cli_subject2wfq_bitmap = cos_bw_bitmap << 3; 800 const u8 pbf_cli_subject2wfq_bitmap = cos_bw_bitmap; 801 802 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT : 803 NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, nig_cli_sp_bitmap); 804 805 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 : 806 PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , pbf_cli_sp_bitmap); 807 808 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ : 809 NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 810 nig_cli_subject2wfq_bitmap); 811 812 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 : 813 PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0, 814 pbf_cli_subject2wfq_bitmap); 815 816 return 0; 817 } 818 819 /****************************************************************************** 820 * Description: 821 * This function is needed because NIG ARB_CREDIT_WEIGHT_X are 822 * not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable. 823 ******************************************************************************/ 824 static int bnx2x_ets_e3b0_set_cos_bw(struct bnx2x *bp, 825 const u8 cos_entry, 826 const u32 min_w_val_nig, 827 const u32 min_w_val_pbf, 828 const u16 total_bw, 829 const u8 bw, 830 const u8 port) 831 { 832 u32 nig_reg_adress_crd_weight = 0; 833 u32 pbf_reg_adress_crd_weight = 0; 834 /* Calculate and set BW for this COS - use 1 instead of 0 for BW */ 835 const u32 cos_bw_nig = ((bw ? bw : 1) * min_w_val_nig) / total_bw; 836 const u32 cos_bw_pbf = ((bw ? bw : 1) * min_w_val_pbf) / total_bw; 837 838 switch (cos_entry) { 839 case 0: 840 nig_reg_adress_crd_weight = 841 (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 : 842 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0; 843 pbf_reg_adress_crd_weight = (port) ? 844 PBF_REG_COS0_WEIGHT_P1 : PBF_REG_COS0_WEIGHT_P0; 845 break; 846 case 1: 847 nig_reg_adress_crd_weight = (port) ? 848 NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 : 849 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1; 850 pbf_reg_adress_crd_weight = (port) ? 851 PBF_REG_COS1_WEIGHT_P1 : PBF_REG_COS1_WEIGHT_P0; 852 break; 853 case 2: 854 nig_reg_adress_crd_weight = (port) ? 855 NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 : 856 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2; 857 858 pbf_reg_adress_crd_weight = (port) ? 859 PBF_REG_COS2_WEIGHT_P1 : PBF_REG_COS2_WEIGHT_P0; 860 break; 861 case 3: 862 if (port) 863 return -EINVAL; 864 nig_reg_adress_crd_weight = 865 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3; 866 pbf_reg_adress_crd_weight = 867 PBF_REG_COS3_WEIGHT_P0; 868 break; 869 case 4: 870 if (port) 871 return -EINVAL; 872 nig_reg_adress_crd_weight = 873 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4; 874 pbf_reg_adress_crd_weight = PBF_REG_COS4_WEIGHT_P0; 875 break; 876 case 5: 877 if (port) 878 return -EINVAL; 879 nig_reg_adress_crd_weight = 880 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5; 881 pbf_reg_adress_crd_weight = PBF_REG_COS5_WEIGHT_P0; 882 break; 883 } 884 885 REG_WR(bp, nig_reg_adress_crd_weight, cos_bw_nig); 886 887 REG_WR(bp, pbf_reg_adress_crd_weight, cos_bw_pbf); 888 889 return 0; 890 } 891 /****************************************************************************** 892 * Description: 893 * Calculate the total BW.A value of 0 isn't legal. 894 * 895 ******************************************************************************/ 896 static int bnx2x_ets_e3b0_get_total_bw( 897 const struct link_params *params, 898 struct bnx2x_ets_params *ets_params, 899 u16 *total_bw) 900 { 901 struct bnx2x *bp = params->bp; 902 u8 cos_idx = 0; 903 u8 is_bw_cos_exist = 0; 904 905 *total_bw = 0 ; 906 /* Calculate total BW requested */ 907 for (cos_idx = 0; cos_idx < ets_params->num_of_cos; cos_idx++) { 908 if (ets_params->cos[cos_idx].state == bnx2x_cos_state_bw) { 909 is_bw_cos_exist = 1; 910 if (!ets_params->cos[cos_idx].params.bw_params.bw) { 911 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config BW" 912 "was set to 0\n"); 913 /* This is to prevent a state when ramrods 914 * can't be sent 915 */ 916 ets_params->cos[cos_idx].params.bw_params.bw 917 = 1; 918 } 919 *total_bw += 920 ets_params->cos[cos_idx].params.bw_params.bw; 921 } 922 } 923 924 /* Check total BW is valid */ 925 if ((is_bw_cos_exist == 1) && (*total_bw != 100)) { 926 if (*total_bw == 0) { 927 DP(NETIF_MSG_LINK, 928 "bnx2x_ets_E3B0_config total BW shouldn't be 0\n"); 929 return -EINVAL; 930 } 931 DP(NETIF_MSG_LINK, 932 "bnx2x_ets_E3B0_config total BW should be 100\n"); 933 /* We can handle a case whre the BW isn't 100 this can happen 934 * if the TC are joined. 935 */ 936 } 937 return 0; 938 } 939 940 /****************************************************************************** 941 * Description: 942 * Invalidate all the sp_pri_to_cos. 943 * 944 ******************************************************************************/ 945 static void bnx2x_ets_e3b0_sp_pri_to_cos_init(u8 *sp_pri_to_cos) 946 { 947 u8 pri = 0; 948 for (pri = 0; pri < DCBX_MAX_NUM_COS; pri++) 949 sp_pri_to_cos[pri] = DCBX_INVALID_COS; 950 } 951 /****************************************************************************** 952 * Description: 953 * Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers 954 * according to sp_pri_to_cos. 955 * 956 ******************************************************************************/ 957 static int bnx2x_ets_e3b0_sp_pri_to_cos_set(const struct link_params *params, 958 u8 *sp_pri_to_cos, const u8 pri, 959 const u8 cos_entry) 960 { 961 struct bnx2x *bp = params->bp; 962 const u8 port = params->port; 963 const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 : 964 DCBX_E3B0_MAX_NUM_COS_PORT0; 965 966 if (pri >= max_num_of_cos) { 967 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid " 968 "parameter Illegal strict priority\n"); 969 return -EINVAL; 970 } 971 972 if (sp_pri_to_cos[pri] != DCBX_INVALID_COS) { 973 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid " 974 "parameter There can't be two COS's with " 975 "the same strict pri\n"); 976 return -EINVAL; 977 } 978 979 sp_pri_to_cos[pri] = cos_entry; 980 return 0; 981 982 } 983 984 /****************************************************************************** 985 * Description: 986 * Returns the correct value according to COS and priority in 987 * the sp_pri_cli register. 988 * 989 ******************************************************************************/ 990 static u64 bnx2x_e3b0_sp_get_pri_cli_reg(const u8 cos, const u8 cos_offset, 991 const u8 pri_set, 992 const u8 pri_offset, 993 const u8 entry_size) 994 { 995 u64 pri_cli_nig = 0; 996 pri_cli_nig = ((u64)(cos + cos_offset)) << (entry_size * 997 (pri_set + pri_offset)); 998 999 return pri_cli_nig; 1000 } 1001 /****************************************************************************** 1002 * Description: 1003 * Returns the correct value according to COS and priority in the 1004 * sp_pri_cli register for NIG. 1005 * 1006 ******************************************************************************/ 1007 static u64 bnx2x_e3b0_sp_get_pri_cli_reg_nig(const u8 cos, const u8 pri_set) 1008 { 1009 /* MCP Dbg0 and dbg1 are always with higher strict pri*/ 1010 const u8 nig_cos_offset = 3; 1011 const u8 nig_pri_offset = 3; 1012 1013 return bnx2x_e3b0_sp_get_pri_cli_reg(cos, nig_cos_offset, pri_set, 1014 nig_pri_offset, 4); 1015 1016 } 1017 /****************************************************************************** 1018 * Description: 1019 * Returns the correct value according to COS and priority in the 1020 * sp_pri_cli register for PBF. 1021 * 1022 ******************************************************************************/ 1023 static u64 bnx2x_e3b0_sp_get_pri_cli_reg_pbf(const u8 cos, const u8 pri_set) 1024 { 1025 const u8 pbf_cos_offset = 0; 1026 const u8 pbf_pri_offset = 0; 1027 1028 return bnx2x_e3b0_sp_get_pri_cli_reg(cos, pbf_cos_offset, pri_set, 1029 pbf_pri_offset, 3); 1030 1031 } 1032 1033 /****************************************************************************** 1034 * Description: 1035 * Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers 1036 * according to sp_pri_to_cos.(which COS has higher priority) 1037 * 1038 ******************************************************************************/ 1039 static int bnx2x_ets_e3b0_sp_set_pri_cli_reg(const struct link_params *params, 1040 u8 *sp_pri_to_cos) 1041 { 1042 struct bnx2x *bp = params->bp; 1043 u8 i = 0; 1044 const u8 port = params->port; 1045 /* MCP Dbg0 and dbg1 are always with higher strict pri*/ 1046 u64 pri_cli_nig = 0x210; 1047 u32 pri_cli_pbf = 0x0; 1048 u8 pri_set = 0; 1049 u8 pri_bitmask = 0; 1050 const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 : 1051 DCBX_E3B0_MAX_NUM_COS_PORT0; 1052 1053 u8 cos_bit_to_set = (1 << max_num_of_cos) - 1; 1054 1055 /* Set all the strict priority first */ 1056 for (i = 0; i < max_num_of_cos; i++) { 1057 if (sp_pri_to_cos[i] != DCBX_INVALID_COS) { 1058 if (sp_pri_to_cos[i] >= DCBX_MAX_NUM_COS) { 1059 DP(NETIF_MSG_LINK, 1060 "bnx2x_ets_e3b0_sp_set_pri_cli_reg " 1061 "invalid cos entry\n"); 1062 return -EINVAL; 1063 } 1064 1065 pri_cli_nig |= bnx2x_e3b0_sp_get_pri_cli_reg_nig( 1066 sp_pri_to_cos[i], pri_set); 1067 1068 pri_cli_pbf |= bnx2x_e3b0_sp_get_pri_cli_reg_pbf( 1069 sp_pri_to_cos[i], pri_set); 1070 pri_bitmask = 1 << sp_pri_to_cos[i]; 1071 /* COS is used remove it from bitmap.*/ 1072 if (!(pri_bitmask & cos_bit_to_set)) { 1073 DP(NETIF_MSG_LINK, 1074 "bnx2x_ets_e3b0_sp_set_pri_cli_reg " 1075 "invalid There can't be two COS's with" 1076 " the same strict pri\n"); 1077 return -EINVAL; 1078 } 1079 cos_bit_to_set &= ~pri_bitmask; 1080 pri_set++; 1081 } 1082 } 1083 1084 /* Set all the Non strict priority i= COS*/ 1085 for (i = 0; i < max_num_of_cos; i++) { 1086 pri_bitmask = 1 << i; 1087 /* Check if COS was already used for SP */ 1088 if (pri_bitmask & cos_bit_to_set) { 1089 /* COS wasn't used for SP */ 1090 pri_cli_nig |= bnx2x_e3b0_sp_get_pri_cli_reg_nig( 1091 i, pri_set); 1092 1093 pri_cli_pbf |= bnx2x_e3b0_sp_get_pri_cli_reg_pbf( 1094 i, pri_set); 1095 /* COS is used remove it from bitmap.*/ 1096 cos_bit_to_set &= ~pri_bitmask; 1097 pri_set++; 1098 } 1099 } 1100 1101 if (pri_set != max_num_of_cos) { 1102 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_set_pri_cli_reg not all " 1103 "entries were set\n"); 1104 return -EINVAL; 1105 } 1106 1107 if (port) { 1108 /* Only 6 usable clients*/ 1109 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, 1110 (u32)pri_cli_nig); 1111 1112 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , pri_cli_pbf); 1113 } else { 1114 /* Only 9 usable clients*/ 1115 const u32 pri_cli_nig_lsb = (u32) (pri_cli_nig); 1116 const u32 pri_cli_nig_msb = (u32) ((pri_cli_nig >> 32) & 0xF); 1117 1118 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, 1119 pri_cli_nig_lsb); 1120 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, 1121 pri_cli_nig_msb); 1122 1123 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , pri_cli_pbf); 1124 } 1125 return 0; 1126 } 1127 1128 /****************************************************************************** 1129 * Description: 1130 * Configure the COS to ETS according to BW and SP settings. 1131 ******************************************************************************/ 1132 int bnx2x_ets_e3b0_config(const struct link_params *params, 1133 const struct link_vars *vars, 1134 struct bnx2x_ets_params *ets_params) 1135 { 1136 struct bnx2x *bp = params->bp; 1137 int bnx2x_status = 0; 1138 const u8 port = params->port; 1139 u16 total_bw = 0; 1140 const u32 min_w_val_nig = bnx2x_ets_get_min_w_val_nig(vars); 1141 const u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL; 1142 u8 cos_bw_bitmap = 0; 1143 u8 cos_sp_bitmap = 0; 1144 u8 sp_pri_to_cos[DCBX_MAX_NUM_COS] = {0}; 1145 const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 : 1146 DCBX_E3B0_MAX_NUM_COS_PORT0; 1147 u8 cos_entry = 0; 1148 1149 if (!CHIP_IS_E3B0(bp)) { 1150 DP(NETIF_MSG_LINK, 1151 "bnx2x_ets_e3b0_disabled the chip isn't E3B0\n"); 1152 return -EINVAL; 1153 } 1154 1155 if ((ets_params->num_of_cos > max_num_of_cos)) { 1156 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config the number of COS " 1157 "isn't supported\n"); 1158 return -EINVAL; 1159 } 1160 1161 /* Prepare sp strict priority parameters*/ 1162 bnx2x_ets_e3b0_sp_pri_to_cos_init(sp_pri_to_cos); 1163 1164 /* Prepare BW parameters*/ 1165 bnx2x_status = bnx2x_ets_e3b0_get_total_bw(params, ets_params, 1166 &total_bw); 1167 if (bnx2x_status) { 1168 DP(NETIF_MSG_LINK, 1169 "bnx2x_ets_E3B0_config get_total_bw failed\n"); 1170 return -EINVAL; 1171 } 1172 1173 /* Upper bound is set according to current link speed (min_w_val 1174 * should be the same for upper bound and COS credit val). 1175 */ 1176 bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val_nig); 1177 bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf); 1178 1179 1180 for (cos_entry = 0; cos_entry < ets_params->num_of_cos; cos_entry++) { 1181 if (bnx2x_cos_state_bw == ets_params->cos[cos_entry].state) { 1182 cos_bw_bitmap |= (1 << cos_entry); 1183 /* The function also sets the BW in HW(not the mappin 1184 * yet) 1185 */ 1186 bnx2x_status = bnx2x_ets_e3b0_set_cos_bw( 1187 bp, cos_entry, min_w_val_nig, min_w_val_pbf, 1188 total_bw, 1189 ets_params->cos[cos_entry].params.bw_params.bw, 1190 port); 1191 } else if (bnx2x_cos_state_strict == 1192 ets_params->cos[cos_entry].state){ 1193 cos_sp_bitmap |= (1 << cos_entry); 1194 1195 bnx2x_status = bnx2x_ets_e3b0_sp_pri_to_cos_set( 1196 params, 1197 sp_pri_to_cos, 1198 ets_params->cos[cos_entry].params.sp_params.pri, 1199 cos_entry); 1200 1201 } else { 1202 DP(NETIF_MSG_LINK, 1203 "bnx2x_ets_e3b0_config cos state not valid\n"); 1204 return -EINVAL; 1205 } 1206 if (bnx2x_status) { 1207 DP(NETIF_MSG_LINK, 1208 "bnx2x_ets_e3b0_config set cos bw failed\n"); 1209 return bnx2x_status; 1210 } 1211 } 1212 1213 /* Set SP register (which COS has higher priority) */ 1214 bnx2x_status = bnx2x_ets_e3b0_sp_set_pri_cli_reg(params, 1215 sp_pri_to_cos); 1216 1217 if (bnx2x_status) { 1218 DP(NETIF_MSG_LINK, 1219 "bnx2x_ets_E3B0_config set_pri_cli_reg failed\n"); 1220 return bnx2x_status; 1221 } 1222 1223 /* Set client mapping of BW and strict */ 1224 bnx2x_status = bnx2x_ets_e3b0_cli_map(params, ets_params, 1225 cos_sp_bitmap, 1226 cos_bw_bitmap); 1227 1228 if (bnx2x_status) { 1229 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config SP failed\n"); 1230 return bnx2x_status; 1231 } 1232 return 0; 1233 } 1234 static void bnx2x_ets_bw_limit_common(const struct link_params *params) 1235 { 1236 /* ETS disabled configuration */ 1237 struct bnx2x *bp = params->bp; 1238 DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n"); 1239 /* Defines which entries (clients) are subjected to WFQ arbitration 1240 * COS0 0x8 1241 * COS1 0x10 1242 */ 1243 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0x18); 1244 /* Mapping between the ARB_CREDIT_WEIGHT registers and actual 1245 * client numbers (WEIGHT_0 does not actually have to represent 1246 * client 0) 1247 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0 1248 * cos1-001 cos0-000 dbg1-100 dbg0-011 MCP-010 1249 */ 1250 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0x111A); 1251 1252 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 1253 ETS_BW_LIMIT_CREDIT_UPPER_BOUND); 1254 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 1255 ETS_BW_LIMIT_CREDIT_UPPER_BOUND); 1256 1257 /* ETS mode enabled*/ 1258 REG_WR(bp, PBF_REG_ETS_ENABLED, 1); 1259 1260 /* Defines the number of consecutive slots for the strict priority */ 1261 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0); 1262 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves 1263 * as strict. Bits 0,1,2 - debug and management entries, 3 - COS0 1264 * entry, 4 - COS1 entry. 1265 * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT 1266 * bit4 bit3 bit2 bit1 bit0 1267 * MCP and debug are strict 1268 */ 1269 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7); 1270 1271 /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter.*/ 1272 REG_WR(bp, PBF_REG_COS0_UPPER_BOUND, 1273 ETS_BW_LIMIT_CREDIT_UPPER_BOUND); 1274 REG_WR(bp, PBF_REG_COS1_UPPER_BOUND, 1275 ETS_BW_LIMIT_CREDIT_UPPER_BOUND); 1276 } 1277 1278 void bnx2x_ets_bw_limit(const struct link_params *params, const u32 cos0_bw, 1279 const u32 cos1_bw) 1280 { 1281 /* ETS disabled configuration*/ 1282 struct bnx2x *bp = params->bp; 1283 const u32 total_bw = cos0_bw + cos1_bw; 1284 u32 cos0_credit_weight = 0; 1285 u32 cos1_credit_weight = 0; 1286 1287 DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n"); 1288 1289 if ((!total_bw) || 1290 (!cos0_bw) || 1291 (!cos1_bw)) { 1292 DP(NETIF_MSG_LINK, "Total BW can't be zero\n"); 1293 return; 1294 } 1295 1296 cos0_credit_weight = (cos0_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/ 1297 total_bw; 1298 cos1_credit_weight = (cos1_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/ 1299 total_bw; 1300 1301 bnx2x_ets_bw_limit_common(params); 1302 1303 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, cos0_credit_weight); 1304 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, cos1_credit_weight); 1305 1306 REG_WR(bp, PBF_REG_COS0_WEIGHT, cos0_credit_weight); 1307 REG_WR(bp, PBF_REG_COS1_WEIGHT, cos1_credit_weight); 1308 } 1309 1310 int bnx2x_ets_strict(const struct link_params *params, const u8 strict_cos) 1311 { 1312 /* ETS disabled configuration*/ 1313 struct bnx2x *bp = params->bp; 1314 u32 val = 0; 1315 1316 DP(NETIF_MSG_LINK, "ETS enabled strict configuration\n"); 1317 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves 1318 * as strict. Bits 0,1,2 - debug and management entries, 1319 * 3 - COS0 entry, 4 - COS1 entry. 1320 * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT 1321 * bit4 bit3 bit2 bit1 bit0 1322 * MCP and debug are strict 1323 */ 1324 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1F); 1325 /* For strict priority entries defines the number of consecutive slots 1326 * for the highest priority. 1327 */ 1328 REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100); 1329 /* ETS mode disable */ 1330 REG_WR(bp, PBF_REG_ETS_ENABLED, 0); 1331 /* Defines the number of consecutive slots for the strict priority */ 1332 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0x100); 1333 1334 /* Defines the number of consecutive slots for the strict priority */ 1335 REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, strict_cos); 1336 1337 /* Mapping between entry priority to client number (0,1,2 -debug and 1338 * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST) 1339 * 3bits client num. 1340 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0 1341 * dbg0-010 dbg1-001 cos1-100 cos0-011 MCP-000 1342 * dbg0-010 dbg1-001 cos0-011 cos1-100 MCP-000 1343 */ 1344 val = (!strict_cos) ? 0x2318 : 0x22E0; 1345 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, val); 1346 1347 return 0; 1348 } 1349 1350 /******************************************************************/ 1351 /* PFC section */ 1352 /******************************************************************/ 1353 static void bnx2x_update_pfc_xmac(struct link_params *params, 1354 struct link_vars *vars, 1355 u8 is_lb) 1356 { 1357 struct bnx2x *bp = params->bp; 1358 u32 xmac_base; 1359 u32 pause_val, pfc0_val, pfc1_val; 1360 1361 /* XMAC base adrr */ 1362 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; 1363 1364 /* Initialize pause and pfc registers */ 1365 pause_val = 0x18000; 1366 pfc0_val = 0xFFFF8000; 1367 pfc1_val = 0x2; 1368 1369 /* No PFC support */ 1370 if (!(params->feature_config_flags & 1371 FEATURE_CONFIG_PFC_ENABLED)) { 1372 1373 /* RX flow control - Process pause frame in receive direction 1374 */ 1375 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX) 1376 pause_val |= XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN; 1377 1378 /* TX flow control - Send pause packet when buffer is full */ 1379 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) 1380 pause_val |= XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN; 1381 } else {/* PFC support */ 1382 pfc1_val |= XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN | 1383 XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN | 1384 XMAC_PFC_CTRL_HI_REG_RX_PFC_EN | 1385 XMAC_PFC_CTRL_HI_REG_TX_PFC_EN | 1386 XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON; 1387 /* Write pause and PFC registers */ 1388 REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val); 1389 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val); 1390 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val); 1391 pfc1_val &= ~XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON; 1392 1393 } 1394 1395 /* Write pause and PFC registers */ 1396 REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val); 1397 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val); 1398 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val); 1399 1400 1401 /* Set MAC address for source TX Pause/PFC frames */ 1402 REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_LO, 1403 ((params->mac_addr[2] << 24) | 1404 (params->mac_addr[3] << 16) | 1405 (params->mac_addr[4] << 8) | 1406 (params->mac_addr[5]))); 1407 REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_HI, 1408 ((params->mac_addr[0] << 8) | 1409 (params->mac_addr[1]))); 1410 1411 udelay(30); 1412 } 1413 1414 /******************************************************************/ 1415 /* MAC/PBF section */ 1416 /******************************************************************/ 1417 static void bnx2x_set_mdio_clk(struct bnx2x *bp, u32 chip_id, 1418 u32 emac_base) 1419 { 1420 u32 new_mode, cur_mode; 1421 u32 clc_cnt; 1422 /* Set clause 45 mode, slow down the MDIO clock to 2.5MHz 1423 * (a value of 49==0x31) and make sure that the AUTO poll is off 1424 */ 1425 cur_mode = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE); 1426 1427 if (USES_WARPCORE(bp)) 1428 clc_cnt = 74L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT; 1429 else 1430 clc_cnt = 49L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT; 1431 1432 if (((cur_mode & EMAC_MDIO_MODE_CLOCK_CNT) == clc_cnt) && 1433 (cur_mode & (EMAC_MDIO_MODE_CLAUSE_45))) 1434 return; 1435 1436 new_mode = cur_mode & 1437 ~(EMAC_MDIO_MODE_AUTO_POLL | EMAC_MDIO_MODE_CLOCK_CNT); 1438 new_mode |= clc_cnt; 1439 new_mode |= (EMAC_MDIO_MODE_CLAUSE_45); 1440 1441 DP(NETIF_MSG_LINK, "Changing emac_mode from 0x%x to 0x%x\n", 1442 cur_mode, new_mode); 1443 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE, new_mode); 1444 udelay(40); 1445 } 1446 1447 static void bnx2x_set_mdio_emac_per_phy(struct bnx2x *bp, 1448 struct link_params *params) 1449 { 1450 u8 phy_index; 1451 /* Set mdio clock per phy */ 1452 for (phy_index = INT_PHY; phy_index < params->num_phys; 1453 phy_index++) 1454 bnx2x_set_mdio_clk(bp, params->chip_id, 1455 params->phy[phy_index].mdio_ctrl); 1456 } 1457 1458 static u8 bnx2x_is_4_port_mode(struct bnx2x *bp) 1459 { 1460 u32 port4mode_ovwr_val; 1461 /* Check 4-port override enabled */ 1462 port4mode_ovwr_val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR); 1463 if (port4mode_ovwr_val & (1<<0)) { 1464 /* Return 4-port mode override value */ 1465 return ((port4mode_ovwr_val & (1<<1)) == (1<<1)); 1466 } 1467 /* Return 4-port mode from input pin */ 1468 return (u8)REG_RD(bp, MISC_REG_PORT4MODE_EN); 1469 } 1470 1471 static void bnx2x_emac_init(struct link_params *params, 1472 struct link_vars *vars) 1473 { 1474 /* reset and unreset the emac core */ 1475 struct bnx2x *bp = params->bp; 1476 u8 port = params->port; 1477 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; 1478 u32 val; 1479 u16 timeout; 1480 1481 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 1482 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port)); 1483 udelay(5); 1484 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 1485 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port)); 1486 1487 /* init emac - use read-modify-write */ 1488 /* self clear reset */ 1489 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE); 1490 EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET)); 1491 1492 timeout = 200; 1493 do { 1494 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE); 1495 DP(NETIF_MSG_LINK, "EMAC reset reg is %u\n", val); 1496 if (!timeout) { 1497 DP(NETIF_MSG_LINK, "EMAC timeout!\n"); 1498 return; 1499 } 1500 timeout--; 1501 } while (val & EMAC_MODE_RESET); 1502 1503 bnx2x_set_mdio_emac_per_phy(bp, params); 1504 /* Set mac address */ 1505 val = ((params->mac_addr[0] << 8) | 1506 params->mac_addr[1]); 1507 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH, val); 1508 1509 val = ((params->mac_addr[2] << 24) | 1510 (params->mac_addr[3] << 16) | 1511 (params->mac_addr[4] << 8) | 1512 params->mac_addr[5]); 1513 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + 4, val); 1514 } 1515 1516 static void bnx2x_set_xumac_nig(struct link_params *params, 1517 u16 tx_pause_en, 1518 u8 enable) 1519 { 1520 struct bnx2x *bp = params->bp; 1521 1522 REG_WR(bp, params->port ? NIG_REG_P1_MAC_IN_EN : NIG_REG_P0_MAC_IN_EN, 1523 enable); 1524 REG_WR(bp, params->port ? NIG_REG_P1_MAC_OUT_EN : NIG_REG_P0_MAC_OUT_EN, 1525 enable); 1526 REG_WR(bp, params->port ? NIG_REG_P1_MAC_PAUSE_OUT_EN : 1527 NIG_REG_P0_MAC_PAUSE_OUT_EN, tx_pause_en); 1528 } 1529 1530 static void bnx2x_set_umac_rxtx(struct link_params *params, u8 en) 1531 { 1532 u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0; 1533 u32 val; 1534 struct bnx2x *bp = params->bp; 1535 if (!(REG_RD(bp, MISC_REG_RESET_REG_2) & 1536 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port))) 1537 return; 1538 val = REG_RD(bp, umac_base + UMAC_REG_COMMAND_CONFIG); 1539 if (en) 1540 val |= (UMAC_COMMAND_CONFIG_REG_TX_ENA | 1541 UMAC_COMMAND_CONFIG_REG_RX_ENA); 1542 else 1543 val &= ~(UMAC_COMMAND_CONFIG_REG_TX_ENA | 1544 UMAC_COMMAND_CONFIG_REG_RX_ENA); 1545 /* Disable RX and TX */ 1546 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val); 1547 } 1548 1549 static void bnx2x_umac_enable(struct link_params *params, 1550 struct link_vars *vars, u8 lb) 1551 { 1552 u32 val; 1553 u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0; 1554 struct bnx2x *bp = params->bp; 1555 /* Reset UMAC */ 1556 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 1557 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port)); 1558 usleep_range(1000, 2000); 1559 1560 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 1561 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port)); 1562 1563 DP(NETIF_MSG_LINK, "enabling UMAC\n"); 1564 1565 /* This register opens the gate for the UMAC despite its name */ 1566 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1); 1567 1568 val = UMAC_COMMAND_CONFIG_REG_PROMIS_EN | 1569 UMAC_COMMAND_CONFIG_REG_PAD_EN | 1570 UMAC_COMMAND_CONFIG_REG_SW_RESET | 1571 UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK; 1572 switch (vars->line_speed) { 1573 case SPEED_10: 1574 val |= (0<<2); 1575 break; 1576 case SPEED_100: 1577 val |= (1<<2); 1578 break; 1579 case SPEED_1000: 1580 val |= (2<<2); 1581 break; 1582 case SPEED_2500: 1583 val |= (3<<2); 1584 break; 1585 default: 1586 DP(NETIF_MSG_LINK, "Invalid speed for UMAC %d\n", 1587 vars->line_speed); 1588 break; 1589 } 1590 if (!(vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)) 1591 val |= UMAC_COMMAND_CONFIG_REG_IGNORE_TX_PAUSE; 1592 1593 if (!(vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)) 1594 val |= UMAC_COMMAND_CONFIG_REG_PAUSE_IGNORE; 1595 1596 if (vars->duplex == DUPLEX_HALF) 1597 val |= UMAC_COMMAND_CONFIG_REG_HD_ENA; 1598 1599 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val); 1600 udelay(50); 1601 1602 /* Configure UMAC for EEE */ 1603 if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) { 1604 DP(NETIF_MSG_LINK, "configured UMAC for EEE\n"); 1605 REG_WR(bp, umac_base + UMAC_REG_UMAC_EEE_CTRL, 1606 UMAC_UMAC_EEE_CTRL_REG_EEE_EN); 1607 REG_WR(bp, umac_base + UMAC_REG_EEE_WAKE_TIMER, 0x11); 1608 } else { 1609 REG_WR(bp, umac_base + UMAC_REG_UMAC_EEE_CTRL, 0x0); 1610 } 1611 1612 /* Set MAC address for source TX Pause/PFC frames (under SW reset) */ 1613 REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR0, 1614 ((params->mac_addr[2] << 24) | 1615 (params->mac_addr[3] << 16) | 1616 (params->mac_addr[4] << 8) | 1617 (params->mac_addr[5]))); 1618 REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR1, 1619 ((params->mac_addr[0] << 8) | 1620 (params->mac_addr[1]))); 1621 1622 /* Enable RX and TX */ 1623 val &= ~UMAC_COMMAND_CONFIG_REG_PAD_EN; 1624 val |= UMAC_COMMAND_CONFIG_REG_TX_ENA | 1625 UMAC_COMMAND_CONFIG_REG_RX_ENA; 1626 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val); 1627 udelay(50); 1628 1629 /* Remove SW Reset */ 1630 val &= ~UMAC_COMMAND_CONFIG_REG_SW_RESET; 1631 1632 /* Check loopback mode */ 1633 if (lb) 1634 val |= UMAC_COMMAND_CONFIG_REG_LOOP_ENA; 1635 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val); 1636 1637 /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame 1638 * length used by the MAC receive logic to check frames. 1639 */ 1640 REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710); 1641 bnx2x_set_xumac_nig(params, 1642 ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1); 1643 vars->mac_type = MAC_TYPE_UMAC; 1644 1645 } 1646 1647 /* Define the XMAC mode */ 1648 static void bnx2x_xmac_init(struct link_params *params, u32 max_speed) 1649 { 1650 struct bnx2x *bp = params->bp; 1651 u32 is_port4mode = bnx2x_is_4_port_mode(bp); 1652 1653 /* In 4-port mode, need to set the mode only once, so if XMAC is 1654 * already out of reset, it means the mode has already been set, 1655 * and it must not* reset the XMAC again, since it controls both 1656 * ports of the path 1657 */ 1658 1659 if (((CHIP_NUM(bp) == CHIP_NUM_57840_4_10) || 1660 (CHIP_NUM(bp) == CHIP_NUM_57840_2_20) || 1661 (CHIP_NUM(bp) == CHIP_NUM_57840_OBSOLETE)) && 1662 is_port4mode && 1663 (REG_RD(bp, MISC_REG_RESET_REG_2) & 1664 MISC_REGISTERS_RESET_REG_2_XMAC)) { 1665 DP(NETIF_MSG_LINK, 1666 "XMAC already out of reset in 4-port mode\n"); 1667 return; 1668 } 1669 1670 /* Hard reset */ 1671 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 1672 MISC_REGISTERS_RESET_REG_2_XMAC); 1673 usleep_range(1000, 2000); 1674 1675 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 1676 MISC_REGISTERS_RESET_REG_2_XMAC); 1677 if (is_port4mode) { 1678 DP(NETIF_MSG_LINK, "Init XMAC to 2 ports x 10G per path\n"); 1679 1680 /* Set the number of ports on the system side to up to 2 */ 1681 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 1); 1682 1683 /* Set the number of ports on the Warp Core to 10G */ 1684 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3); 1685 } else { 1686 /* Set the number of ports on the system side to 1 */ 1687 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 0); 1688 if (max_speed == SPEED_10000) { 1689 DP(NETIF_MSG_LINK, 1690 "Init XMAC to 10G x 1 port per path\n"); 1691 /* Set the number of ports on the Warp Core to 10G */ 1692 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3); 1693 } else { 1694 DP(NETIF_MSG_LINK, 1695 "Init XMAC to 20G x 2 ports per path\n"); 1696 /* Set the number of ports on the Warp Core to 20G */ 1697 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 1); 1698 } 1699 } 1700 /* Soft reset */ 1701 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 1702 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT); 1703 usleep_range(1000, 2000); 1704 1705 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 1706 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT); 1707 1708 } 1709 1710 static void bnx2x_set_xmac_rxtx(struct link_params *params, u8 en) 1711 { 1712 u8 port = params->port; 1713 struct bnx2x *bp = params->bp; 1714 u32 pfc_ctrl, xmac_base = (port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; 1715 u32 val; 1716 1717 if (REG_RD(bp, MISC_REG_RESET_REG_2) & 1718 MISC_REGISTERS_RESET_REG_2_XMAC) { 1719 /* Send an indication to change the state in the NIG back to XON 1720 * Clearing this bit enables the next set of this bit to get 1721 * rising edge 1722 */ 1723 pfc_ctrl = REG_RD(bp, xmac_base + XMAC_REG_PFC_CTRL_HI); 1724 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, 1725 (pfc_ctrl & ~(1<<1))); 1726 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, 1727 (pfc_ctrl | (1<<1))); 1728 DP(NETIF_MSG_LINK, "Disable XMAC on port %x\n", port); 1729 val = REG_RD(bp, xmac_base + XMAC_REG_CTRL); 1730 if (en) 1731 val |= (XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN); 1732 else 1733 val &= ~(XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN); 1734 REG_WR(bp, xmac_base + XMAC_REG_CTRL, val); 1735 } 1736 } 1737 1738 static int bnx2x_xmac_enable(struct link_params *params, 1739 struct link_vars *vars, u8 lb) 1740 { 1741 u32 val, xmac_base; 1742 struct bnx2x *bp = params->bp; 1743 DP(NETIF_MSG_LINK, "enabling XMAC\n"); 1744 1745 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; 1746 1747 bnx2x_xmac_init(params, vars->line_speed); 1748 1749 /* This register determines on which events the MAC will assert 1750 * error on the i/f to the NIG along w/ EOP. 1751 */ 1752 1753 /* This register tells the NIG whether to send traffic to UMAC 1754 * or XMAC 1755 */ 1756 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 0); 1757 1758 /* When XMAC is in XLGMII mode, disable sending idles for fault 1759 * detection. 1760 */ 1761 if (!(params->phy[INT_PHY].flags & FLAGS_TX_ERROR_CHECK)) { 1762 REG_WR(bp, xmac_base + XMAC_REG_RX_LSS_CTRL, 1763 (XMAC_RX_LSS_CTRL_REG_LOCAL_FAULT_DISABLE | 1764 XMAC_RX_LSS_CTRL_REG_REMOTE_FAULT_DISABLE)); 1765 REG_WR(bp, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0); 1766 REG_WR(bp, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 1767 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS | 1768 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS); 1769 } 1770 /* Set Max packet size */ 1771 REG_WR(bp, xmac_base + XMAC_REG_RX_MAX_SIZE, 0x2710); 1772 1773 /* CRC append for Tx packets */ 1774 REG_WR(bp, xmac_base + XMAC_REG_TX_CTRL, 0xC800); 1775 1776 /* update PFC */ 1777 bnx2x_update_pfc_xmac(params, vars, 0); 1778 1779 if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) { 1780 DP(NETIF_MSG_LINK, "Setting XMAC for EEE\n"); 1781 REG_WR(bp, xmac_base + XMAC_REG_EEE_TIMERS_HI, 0x1380008); 1782 REG_WR(bp, xmac_base + XMAC_REG_EEE_CTRL, 0x1); 1783 } else { 1784 REG_WR(bp, xmac_base + XMAC_REG_EEE_CTRL, 0x0); 1785 } 1786 1787 /* Enable TX and RX */ 1788 val = XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN; 1789 1790 /* Set MAC in XLGMII mode for dual-mode */ 1791 if ((vars->line_speed == SPEED_20000) && 1792 (params->phy[INT_PHY].supported & 1793 SUPPORTED_20000baseKR2_Full)) 1794 val |= XMAC_CTRL_REG_XLGMII_ALIGN_ENB; 1795 1796 /* Check loopback mode */ 1797 if (lb) 1798 val |= XMAC_CTRL_REG_LINE_LOCAL_LPBK; 1799 REG_WR(bp, xmac_base + XMAC_REG_CTRL, val); 1800 bnx2x_set_xumac_nig(params, 1801 ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1); 1802 1803 vars->mac_type = MAC_TYPE_XMAC; 1804 1805 return 0; 1806 } 1807 1808 static int bnx2x_emac_enable(struct link_params *params, 1809 struct link_vars *vars, u8 lb) 1810 { 1811 struct bnx2x *bp = params->bp; 1812 u8 port = params->port; 1813 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; 1814 u32 val; 1815 1816 DP(NETIF_MSG_LINK, "enabling EMAC\n"); 1817 1818 /* Disable BMAC */ 1819 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 1820 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); 1821 1822 /* enable emac and not bmac */ 1823 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 1); 1824 1825 /* ASIC */ 1826 if (vars->phy_flags & PHY_XGXS_FLAG) { 1827 u32 ser_lane = ((params->lane_config & 1828 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >> 1829 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT); 1830 1831 DP(NETIF_MSG_LINK, "XGXS\n"); 1832 /* select the master lanes (out of 0-3) */ 1833 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, ser_lane); 1834 /* select XGXS */ 1835 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1); 1836 1837 } else { /* SerDes */ 1838 DP(NETIF_MSG_LINK, "SerDes\n"); 1839 /* select SerDes */ 1840 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0); 1841 } 1842 1843 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_RX_MODE, 1844 EMAC_RX_MODE_RESET); 1845 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE, 1846 EMAC_TX_MODE_RESET); 1847 1848 /* pause enable/disable */ 1849 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_RX_MODE, 1850 EMAC_RX_MODE_FLOW_EN); 1851 1852 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_TX_MODE, 1853 (EMAC_TX_MODE_EXT_PAUSE_EN | 1854 EMAC_TX_MODE_FLOW_EN)); 1855 if (!(params->feature_config_flags & 1856 FEATURE_CONFIG_PFC_ENABLED)) { 1857 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX) 1858 bnx2x_bits_en(bp, emac_base + 1859 EMAC_REG_EMAC_RX_MODE, 1860 EMAC_RX_MODE_FLOW_EN); 1861 1862 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) 1863 bnx2x_bits_en(bp, emac_base + 1864 EMAC_REG_EMAC_TX_MODE, 1865 (EMAC_TX_MODE_EXT_PAUSE_EN | 1866 EMAC_TX_MODE_FLOW_EN)); 1867 } else 1868 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE, 1869 EMAC_TX_MODE_FLOW_EN); 1870 1871 /* KEEP_VLAN_TAG, promiscuous */ 1872 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE); 1873 val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS; 1874 1875 /* Setting this bit causes MAC control frames (except for pause 1876 * frames) to be passed on for processing. This setting has no 1877 * affect on the operation of the pause frames. This bit effects 1878 * all packets regardless of RX Parser packet sorting logic. 1879 * Turn the PFC off to make sure we are in Xon state before 1880 * enabling it. 1881 */ 1882 EMAC_WR(bp, EMAC_REG_RX_PFC_MODE, 0); 1883 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) { 1884 DP(NETIF_MSG_LINK, "PFC is enabled\n"); 1885 /* Enable PFC again */ 1886 EMAC_WR(bp, EMAC_REG_RX_PFC_MODE, 1887 EMAC_REG_RX_PFC_MODE_RX_EN | 1888 EMAC_REG_RX_PFC_MODE_TX_EN | 1889 EMAC_REG_RX_PFC_MODE_PRIORITIES); 1890 1891 EMAC_WR(bp, EMAC_REG_RX_PFC_PARAM, 1892 ((0x0101 << 1893 EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT) | 1894 (0x00ff << 1895 EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT))); 1896 val |= EMAC_RX_MODE_KEEP_MAC_CONTROL; 1897 } 1898 EMAC_WR(bp, EMAC_REG_EMAC_RX_MODE, val); 1899 1900 /* Set Loopback */ 1901 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE); 1902 if (lb) 1903 val |= 0x810; 1904 else 1905 val &= ~0x810; 1906 EMAC_WR(bp, EMAC_REG_EMAC_MODE, val); 1907 1908 /* Enable emac */ 1909 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 1); 1910 1911 /* Enable emac for jumbo packets */ 1912 EMAC_WR(bp, EMAC_REG_EMAC_RX_MTU_SIZE, 1913 (EMAC_RX_MTU_SIZE_JUMBO_ENA | 1914 (ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVERHEAD))); 1915 1916 /* Strip CRC */ 1917 REG_WR(bp, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1); 1918 1919 /* Disable the NIG in/out to the bmac */ 1920 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x0); 1921 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0); 1922 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x0); 1923 1924 /* Enable the NIG in/out to the emac */ 1925 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x1); 1926 val = 0; 1927 if ((params->feature_config_flags & 1928 FEATURE_CONFIG_PFC_ENABLED) || 1929 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)) 1930 val = 1; 1931 1932 REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val); 1933 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1); 1934 1935 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x0); 1936 1937 vars->mac_type = MAC_TYPE_EMAC; 1938 return 0; 1939 } 1940 1941 static void bnx2x_update_pfc_bmac1(struct link_params *params, 1942 struct link_vars *vars) 1943 { 1944 u32 wb_data[2]; 1945 struct bnx2x *bp = params->bp; 1946 u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM : 1947 NIG_REG_INGRESS_BMAC0_MEM; 1948 1949 u32 val = 0x14; 1950 if ((!(params->feature_config_flags & 1951 FEATURE_CONFIG_PFC_ENABLED)) && 1952 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)) 1953 /* Enable BigMAC to react on received Pause packets */ 1954 val |= (1<<5); 1955 wb_data[0] = val; 1956 wb_data[1] = 0; 1957 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_CONTROL, wb_data, 2); 1958 1959 /* TX control */ 1960 val = 0xc0; 1961 if (!(params->feature_config_flags & 1962 FEATURE_CONFIG_PFC_ENABLED) && 1963 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)) 1964 val |= 0x800000; 1965 wb_data[0] = val; 1966 wb_data[1] = 0; 1967 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_CONTROL, wb_data, 2); 1968 } 1969 1970 static void bnx2x_update_pfc_bmac2(struct link_params *params, 1971 struct link_vars *vars, 1972 u8 is_lb) 1973 { 1974 /* Set rx control: Strip CRC and enable BigMAC to relay 1975 * control packets to the system as well 1976 */ 1977 u32 wb_data[2]; 1978 struct bnx2x *bp = params->bp; 1979 u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM : 1980 NIG_REG_INGRESS_BMAC0_MEM; 1981 u32 val = 0x14; 1982 1983 if ((!(params->feature_config_flags & 1984 FEATURE_CONFIG_PFC_ENABLED)) && 1985 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)) 1986 /* Enable BigMAC to react on received Pause packets */ 1987 val |= (1<<5); 1988 wb_data[0] = val; 1989 wb_data[1] = 0; 1990 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_CONTROL, wb_data, 2); 1991 udelay(30); 1992 1993 /* Tx control */ 1994 val = 0xc0; 1995 if (!(params->feature_config_flags & 1996 FEATURE_CONFIG_PFC_ENABLED) && 1997 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)) 1998 val |= 0x800000; 1999 wb_data[0] = val; 2000 wb_data[1] = 0; 2001 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_CONTROL, wb_data, 2); 2002 2003 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) { 2004 DP(NETIF_MSG_LINK, "PFC is enabled\n"); 2005 /* Enable PFC RX & TX & STATS and set 8 COS */ 2006 wb_data[0] = 0x0; 2007 wb_data[0] |= (1<<0); /* RX */ 2008 wb_data[0] |= (1<<1); /* TX */ 2009 wb_data[0] |= (1<<2); /* Force initial Xon */ 2010 wb_data[0] |= (1<<3); /* 8 cos */ 2011 wb_data[0] |= (1<<5); /* STATS */ 2012 wb_data[1] = 0; 2013 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, 2014 wb_data, 2); 2015 /* Clear the force Xon */ 2016 wb_data[0] &= ~(1<<2); 2017 } else { 2018 DP(NETIF_MSG_LINK, "PFC is disabled\n"); 2019 /* Disable PFC RX & TX & STATS and set 8 COS */ 2020 wb_data[0] = 0x8; 2021 wb_data[1] = 0; 2022 } 2023 2024 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, wb_data, 2); 2025 2026 /* Set Time (based unit is 512 bit time) between automatic 2027 * re-sending of PP packets amd enable automatic re-send of 2028 * Per-Priroity Packet as long as pp_gen is asserted and 2029 * pp_disable is low. 2030 */ 2031 val = 0x8000; 2032 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) 2033 val |= (1<<16); /* enable automatic re-send */ 2034 2035 wb_data[0] = val; 2036 wb_data[1] = 0; 2037 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_PAUSE_CONTROL, 2038 wb_data, 2); 2039 2040 /* mac control */ 2041 val = 0x3; /* Enable RX and TX */ 2042 if (is_lb) { 2043 val |= 0x4; /* Local loopback */ 2044 DP(NETIF_MSG_LINK, "enable bmac loopback\n"); 2045 } 2046 /* When PFC enabled, Pass pause frames towards the NIG. */ 2047 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) 2048 val |= ((1<<6)|(1<<5)); 2049 2050 wb_data[0] = val; 2051 wb_data[1] = 0; 2052 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2); 2053 } 2054 2055 /****************************************************************************** 2056 * Description: 2057 * This function is needed because NIG ARB_CREDIT_WEIGHT_X are 2058 * not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable. 2059 ******************************************************************************/ 2060 static int bnx2x_pfc_nig_rx_priority_mask(struct bnx2x *bp, 2061 u8 cos_entry, 2062 u32 priority_mask, u8 port) 2063 { 2064 u32 nig_reg_rx_priority_mask_add = 0; 2065 2066 switch (cos_entry) { 2067 case 0: 2068 nig_reg_rx_priority_mask_add = (port) ? 2069 NIG_REG_P1_RX_COS0_PRIORITY_MASK : 2070 NIG_REG_P0_RX_COS0_PRIORITY_MASK; 2071 break; 2072 case 1: 2073 nig_reg_rx_priority_mask_add = (port) ? 2074 NIG_REG_P1_RX_COS1_PRIORITY_MASK : 2075 NIG_REG_P0_RX_COS1_PRIORITY_MASK; 2076 break; 2077 case 2: 2078 nig_reg_rx_priority_mask_add = (port) ? 2079 NIG_REG_P1_RX_COS2_PRIORITY_MASK : 2080 NIG_REG_P0_RX_COS2_PRIORITY_MASK; 2081 break; 2082 case 3: 2083 if (port) 2084 return -EINVAL; 2085 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS3_PRIORITY_MASK; 2086 break; 2087 case 4: 2088 if (port) 2089 return -EINVAL; 2090 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS4_PRIORITY_MASK; 2091 break; 2092 case 5: 2093 if (port) 2094 return -EINVAL; 2095 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS5_PRIORITY_MASK; 2096 break; 2097 } 2098 2099 REG_WR(bp, nig_reg_rx_priority_mask_add, priority_mask); 2100 2101 return 0; 2102 } 2103 static void bnx2x_update_mng(struct link_params *params, u32 link_status) 2104 { 2105 struct bnx2x *bp = params->bp; 2106 2107 REG_WR(bp, params->shmem_base + 2108 offsetof(struct shmem_region, 2109 port_mb[params->port].link_status), link_status); 2110 } 2111 2112 static void bnx2x_update_link_attr(struct link_params *params, u32 link_attr) 2113 { 2114 struct bnx2x *bp = params->bp; 2115 2116 if (SHMEM2_HAS(bp, link_attr_sync)) 2117 REG_WR(bp, params->shmem2_base + 2118 offsetof(struct shmem2_region, 2119 link_attr_sync[params->port]), link_attr); 2120 } 2121 2122 static void bnx2x_update_pfc_nig(struct link_params *params, 2123 struct link_vars *vars, 2124 struct bnx2x_nig_brb_pfc_port_params *nig_params) 2125 { 2126 u32 xcm_mask = 0, ppp_enable = 0, pause_enable = 0, llfc_out_en = 0; 2127 u32 llfc_enable = 0, xcm_out_en = 0, hwpfc_enable = 0; 2128 u32 pkt_priority_to_cos = 0; 2129 struct bnx2x *bp = params->bp; 2130 u8 port = params->port; 2131 2132 int set_pfc = params->feature_config_flags & 2133 FEATURE_CONFIG_PFC_ENABLED; 2134 DP(NETIF_MSG_LINK, "updating pfc nig parameters\n"); 2135 2136 /* When NIG_LLH0_XCM_MASK_REG_LLHX_XCM_MASK_BCN bit is set 2137 * MAC control frames (that are not pause packets) 2138 * will be forwarded to the XCM. 2139 */ 2140 xcm_mask = REG_RD(bp, port ? NIG_REG_LLH1_XCM_MASK : 2141 NIG_REG_LLH0_XCM_MASK); 2142 /* NIG params will override non PFC params, since it's possible to 2143 * do transition from PFC to SAFC 2144 */ 2145 if (set_pfc) { 2146 pause_enable = 0; 2147 llfc_out_en = 0; 2148 llfc_enable = 0; 2149 if (CHIP_IS_E3(bp)) 2150 ppp_enable = 0; 2151 else 2152 ppp_enable = 1; 2153 xcm_mask &= ~(port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN : 2154 NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN); 2155 xcm_out_en = 0; 2156 hwpfc_enable = 1; 2157 } else { 2158 if (nig_params) { 2159 llfc_out_en = nig_params->llfc_out_en; 2160 llfc_enable = nig_params->llfc_enable; 2161 pause_enable = nig_params->pause_enable; 2162 } else /* Default non PFC mode - PAUSE */ 2163 pause_enable = 1; 2164 2165 xcm_mask |= (port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN : 2166 NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN); 2167 xcm_out_en = 1; 2168 } 2169 2170 if (CHIP_IS_E3(bp)) 2171 REG_WR(bp, port ? NIG_REG_BRB1_PAUSE_IN_EN : 2172 NIG_REG_BRB0_PAUSE_IN_EN, pause_enable); 2173 REG_WR(bp, port ? NIG_REG_LLFC_OUT_EN_1 : 2174 NIG_REG_LLFC_OUT_EN_0, llfc_out_en); 2175 REG_WR(bp, port ? NIG_REG_LLFC_ENABLE_1 : 2176 NIG_REG_LLFC_ENABLE_0, llfc_enable); 2177 REG_WR(bp, port ? NIG_REG_PAUSE_ENABLE_1 : 2178 NIG_REG_PAUSE_ENABLE_0, pause_enable); 2179 2180 REG_WR(bp, port ? NIG_REG_PPP_ENABLE_1 : 2181 NIG_REG_PPP_ENABLE_0, ppp_enable); 2182 2183 REG_WR(bp, port ? NIG_REG_LLH1_XCM_MASK : 2184 NIG_REG_LLH0_XCM_MASK, xcm_mask); 2185 2186 REG_WR(bp, port ? NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 : 2187 NIG_REG_LLFC_EGRESS_SRC_ENABLE_0, 0x7); 2188 2189 /* Output enable for RX_XCM # IF */ 2190 REG_WR(bp, port ? NIG_REG_XCM1_OUT_EN : 2191 NIG_REG_XCM0_OUT_EN, xcm_out_en); 2192 2193 /* HW PFC TX enable */ 2194 REG_WR(bp, port ? NIG_REG_P1_HWPFC_ENABLE : 2195 NIG_REG_P0_HWPFC_ENABLE, hwpfc_enable); 2196 2197 if (nig_params) { 2198 u8 i = 0; 2199 pkt_priority_to_cos = nig_params->pkt_priority_to_cos; 2200 2201 for (i = 0; i < nig_params->num_of_rx_cos_priority_mask; i++) 2202 bnx2x_pfc_nig_rx_priority_mask(bp, i, 2203 nig_params->rx_cos_priority_mask[i], port); 2204 2205 REG_WR(bp, port ? NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 : 2206 NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0, 2207 nig_params->llfc_high_priority_classes); 2208 2209 REG_WR(bp, port ? NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 : 2210 NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0, 2211 nig_params->llfc_low_priority_classes); 2212 } 2213 REG_WR(bp, port ? NIG_REG_P1_PKT_PRIORITY_TO_COS : 2214 NIG_REG_P0_PKT_PRIORITY_TO_COS, 2215 pkt_priority_to_cos); 2216 } 2217 2218 int bnx2x_update_pfc(struct link_params *params, 2219 struct link_vars *vars, 2220 struct bnx2x_nig_brb_pfc_port_params *pfc_params) 2221 { 2222 /* The PFC and pause are orthogonal to one another, meaning when 2223 * PFC is enabled, the pause are disabled, and when PFC is 2224 * disabled, pause are set according to the pause result. 2225 */ 2226 u32 val; 2227 struct bnx2x *bp = params->bp; 2228 u8 bmac_loopback = (params->loopback_mode == LOOPBACK_BMAC); 2229 2230 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) 2231 vars->link_status |= LINK_STATUS_PFC_ENABLED; 2232 else 2233 vars->link_status &= ~LINK_STATUS_PFC_ENABLED; 2234 2235 bnx2x_update_mng(params, vars->link_status); 2236 2237 /* Update NIG params */ 2238 bnx2x_update_pfc_nig(params, vars, pfc_params); 2239 2240 if (!vars->link_up) 2241 return 0; 2242 2243 DP(NETIF_MSG_LINK, "About to update PFC in BMAC\n"); 2244 2245 if (CHIP_IS_E3(bp)) { 2246 if (vars->mac_type == MAC_TYPE_XMAC) 2247 bnx2x_update_pfc_xmac(params, vars, 0); 2248 } else { 2249 val = REG_RD(bp, MISC_REG_RESET_REG_2); 2250 if ((val & 2251 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port)) 2252 == 0) { 2253 DP(NETIF_MSG_LINK, "About to update PFC in EMAC\n"); 2254 bnx2x_emac_enable(params, vars, 0); 2255 return 0; 2256 } 2257 if (CHIP_IS_E2(bp)) 2258 bnx2x_update_pfc_bmac2(params, vars, bmac_loopback); 2259 else 2260 bnx2x_update_pfc_bmac1(params, vars); 2261 2262 val = 0; 2263 if ((params->feature_config_flags & 2264 FEATURE_CONFIG_PFC_ENABLED) || 2265 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)) 2266 val = 1; 2267 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port*4, val); 2268 } 2269 return 0; 2270 } 2271 2272 static int bnx2x_bmac1_enable(struct link_params *params, 2273 struct link_vars *vars, 2274 u8 is_lb) 2275 { 2276 struct bnx2x *bp = params->bp; 2277 u8 port = params->port; 2278 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM : 2279 NIG_REG_INGRESS_BMAC0_MEM; 2280 u32 wb_data[2]; 2281 u32 val; 2282 2283 DP(NETIF_MSG_LINK, "Enabling BigMAC1\n"); 2284 2285 /* XGXS control */ 2286 wb_data[0] = 0x3c; 2287 wb_data[1] = 0; 2288 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_XGXS_CONTROL, 2289 wb_data, 2); 2290 2291 /* TX MAC SA */ 2292 wb_data[0] = ((params->mac_addr[2] << 24) | 2293 (params->mac_addr[3] << 16) | 2294 (params->mac_addr[4] << 8) | 2295 params->mac_addr[5]); 2296 wb_data[1] = ((params->mac_addr[0] << 8) | 2297 params->mac_addr[1]); 2298 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR, wb_data, 2); 2299 2300 /* MAC control */ 2301 val = 0x3; 2302 if (is_lb) { 2303 val |= 0x4; 2304 DP(NETIF_MSG_LINK, "enable bmac loopback\n"); 2305 } 2306 wb_data[0] = val; 2307 wb_data[1] = 0; 2308 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL, wb_data, 2); 2309 2310 /* Set rx mtu */ 2311 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVERHEAD; 2312 wb_data[1] = 0; 2313 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE, wb_data, 2); 2314 2315 bnx2x_update_pfc_bmac1(params, vars); 2316 2317 /* Set tx mtu */ 2318 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVERHEAD; 2319 wb_data[1] = 0; 2320 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE, wb_data, 2); 2321 2322 /* Set cnt max size */ 2323 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVERHEAD; 2324 wb_data[1] = 0; 2325 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE, wb_data, 2); 2326 2327 /* Configure SAFC */ 2328 wb_data[0] = 0x1000200; 2329 wb_data[1] = 0; 2330 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS, 2331 wb_data, 2); 2332 2333 return 0; 2334 } 2335 2336 static int bnx2x_bmac2_enable(struct link_params *params, 2337 struct link_vars *vars, 2338 u8 is_lb) 2339 { 2340 struct bnx2x *bp = params->bp; 2341 u8 port = params->port; 2342 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM : 2343 NIG_REG_INGRESS_BMAC0_MEM; 2344 u32 wb_data[2]; 2345 2346 DP(NETIF_MSG_LINK, "Enabling BigMAC2\n"); 2347 2348 wb_data[0] = 0; 2349 wb_data[1] = 0; 2350 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2); 2351 udelay(30); 2352 2353 /* XGXS control: Reset phy HW, MDIO registers, PHY PLL and BMAC */ 2354 wb_data[0] = 0x3c; 2355 wb_data[1] = 0; 2356 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_XGXS_CONTROL, 2357 wb_data, 2); 2358 2359 udelay(30); 2360 2361 /* TX MAC SA */ 2362 wb_data[0] = ((params->mac_addr[2] << 24) | 2363 (params->mac_addr[3] << 16) | 2364 (params->mac_addr[4] << 8) | 2365 params->mac_addr[5]); 2366 wb_data[1] = ((params->mac_addr[0] << 8) | 2367 params->mac_addr[1]); 2368 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_SOURCE_ADDR, 2369 wb_data, 2); 2370 2371 udelay(30); 2372 2373 /* Configure SAFC */ 2374 wb_data[0] = 0x1000200; 2375 wb_data[1] = 0; 2376 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS, 2377 wb_data, 2); 2378 udelay(30); 2379 2380 /* Set RX MTU */ 2381 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVERHEAD; 2382 wb_data[1] = 0; 2383 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_MAX_SIZE, wb_data, 2); 2384 udelay(30); 2385 2386 /* Set TX MTU */ 2387 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVERHEAD; 2388 wb_data[1] = 0; 2389 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_MAX_SIZE, wb_data, 2); 2390 udelay(30); 2391 /* Set cnt max size */ 2392 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVERHEAD - 2; 2393 wb_data[1] = 0; 2394 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_CNT_MAX_SIZE, wb_data, 2); 2395 udelay(30); 2396 bnx2x_update_pfc_bmac2(params, vars, is_lb); 2397 2398 return 0; 2399 } 2400 2401 static int bnx2x_bmac_enable(struct link_params *params, 2402 struct link_vars *vars, 2403 u8 is_lb, u8 reset_bmac) 2404 { 2405 int rc = 0; 2406 u8 port = params->port; 2407 struct bnx2x *bp = params->bp; 2408 u32 val; 2409 /* Reset and unreset the BigMac */ 2410 if (reset_bmac) { 2411 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 2412 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); 2413 usleep_range(1000, 2000); 2414 } 2415 2416 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 2417 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); 2418 2419 /* Enable access for bmac registers */ 2420 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1); 2421 2422 /* Enable BMAC according to BMAC type*/ 2423 if (CHIP_IS_E2(bp)) 2424 rc = bnx2x_bmac2_enable(params, vars, is_lb); 2425 else 2426 rc = bnx2x_bmac1_enable(params, vars, is_lb); 2427 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1); 2428 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0); 2429 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0); 2430 val = 0; 2431 if ((params->feature_config_flags & 2432 FEATURE_CONFIG_PFC_ENABLED) || 2433 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)) 2434 val = 1; 2435 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val); 2436 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0); 2437 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x0); 2438 REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0); 2439 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x1); 2440 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x1); 2441 2442 vars->mac_type = MAC_TYPE_BMAC; 2443 return rc; 2444 } 2445 2446 static void bnx2x_set_bmac_rx(struct bnx2x *bp, u32 chip_id, u8 port, u8 en) 2447 { 2448 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM : 2449 NIG_REG_INGRESS_BMAC0_MEM; 2450 u32 wb_data[2]; 2451 u32 nig_bmac_enable = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4); 2452 2453 if (CHIP_IS_E2(bp)) 2454 bmac_addr += BIGMAC2_REGISTER_BMAC_CONTROL; 2455 else 2456 bmac_addr += BIGMAC_REGISTER_BMAC_CONTROL; 2457 /* Only if the bmac is out of reset */ 2458 if (REG_RD(bp, MISC_REG_RESET_REG_2) & 2459 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) && 2460 nig_bmac_enable) { 2461 /* Clear Rx Enable bit in BMAC_CONTROL register */ 2462 REG_RD_DMAE(bp, bmac_addr, wb_data, 2); 2463 if (en) 2464 wb_data[0] |= BMAC_CONTROL_RX_ENABLE; 2465 else 2466 wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE; 2467 REG_WR_DMAE(bp, bmac_addr, wb_data, 2); 2468 usleep_range(1000, 2000); 2469 } 2470 } 2471 2472 static int bnx2x_pbf_update(struct link_params *params, u32 flow_ctrl, 2473 u32 line_speed) 2474 { 2475 struct bnx2x *bp = params->bp; 2476 u8 port = params->port; 2477 u32 init_crd, crd; 2478 u32 count = 1000; 2479 2480 /* Disable port */ 2481 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1); 2482 2483 /* Wait for init credit */ 2484 init_crd = REG_RD(bp, PBF_REG_P0_INIT_CRD + port*4); 2485 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8); 2486 DP(NETIF_MSG_LINK, "init_crd 0x%x crd 0x%x\n", init_crd, crd); 2487 2488 while ((init_crd != crd) && count) { 2489 usleep_range(5000, 10000); 2490 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8); 2491 count--; 2492 } 2493 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8); 2494 if (init_crd != crd) { 2495 DP(NETIF_MSG_LINK, "BUG! init_crd 0x%x != crd 0x%x\n", 2496 init_crd, crd); 2497 return -EINVAL; 2498 } 2499 2500 if (flow_ctrl & BNX2X_FLOW_CTRL_RX || 2501 line_speed == SPEED_10 || 2502 line_speed == SPEED_100 || 2503 line_speed == SPEED_1000 || 2504 line_speed == SPEED_2500) { 2505 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 1); 2506 /* Update threshold */ 2507 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, 0); 2508 /* Update init credit */ 2509 init_crd = 778; /* (800-18-4) */ 2510 2511 } else { 2512 u32 thresh = (ETH_MAX_JUMBO_PACKET_SIZE + 2513 ETH_OVERHEAD)/16; 2514 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0); 2515 /* Update threshold */ 2516 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, thresh); 2517 /* Update init credit */ 2518 switch (line_speed) { 2519 case SPEED_10000: 2520 init_crd = thresh + 553 - 22; 2521 break; 2522 default: 2523 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n", 2524 line_speed); 2525 return -EINVAL; 2526 } 2527 } 2528 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, init_crd); 2529 DP(NETIF_MSG_LINK, "PBF updated to speed %d credit %d\n", 2530 line_speed, init_crd); 2531 2532 /* Probe the credit changes */ 2533 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x1); 2534 usleep_range(5000, 10000); 2535 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x0); 2536 2537 /* Enable port */ 2538 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0); 2539 return 0; 2540 } 2541 2542 /** 2543 * bnx2x_get_emac_base - retrive emac base address 2544 * 2545 * @bp: driver handle 2546 * @mdc_mdio_access: access type 2547 * @port: port id 2548 * 2549 * This function selects the MDC/MDIO access (through emac0 or 2550 * emac1) depend on the mdc_mdio_access, port, port swapped. Each 2551 * phy has a default access mode, which could also be overridden 2552 * by nvram configuration. This parameter, whether this is the 2553 * default phy configuration, or the nvram overrun 2554 * configuration, is passed here as mdc_mdio_access and selects 2555 * the emac_base for the CL45 read/writes operations 2556 */ 2557 static u32 bnx2x_get_emac_base(struct bnx2x *bp, 2558 u32 mdc_mdio_access, u8 port) 2559 { 2560 u32 emac_base = 0; 2561 switch (mdc_mdio_access) { 2562 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE: 2563 break; 2564 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0: 2565 if (REG_RD(bp, NIG_REG_PORT_SWAP)) 2566 emac_base = GRCBASE_EMAC1; 2567 else 2568 emac_base = GRCBASE_EMAC0; 2569 break; 2570 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1: 2571 if (REG_RD(bp, NIG_REG_PORT_SWAP)) 2572 emac_base = GRCBASE_EMAC0; 2573 else 2574 emac_base = GRCBASE_EMAC1; 2575 break; 2576 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH: 2577 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0; 2578 break; 2579 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED: 2580 emac_base = (port) ? GRCBASE_EMAC0 : GRCBASE_EMAC1; 2581 break; 2582 default: 2583 break; 2584 } 2585 return emac_base; 2586 2587 } 2588 2589 /******************************************************************/ 2590 /* CL22 access functions */ 2591 /******************************************************************/ 2592 static int bnx2x_cl22_write(struct bnx2x *bp, 2593 struct bnx2x_phy *phy, 2594 u16 reg, u16 val) 2595 { 2596 u32 tmp, mode; 2597 u8 i; 2598 int rc = 0; 2599 /* Switch to CL22 */ 2600 mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE); 2601 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, 2602 mode & ~EMAC_MDIO_MODE_CLAUSE_45); 2603 2604 /* Address */ 2605 tmp = ((phy->addr << 21) | (reg << 16) | val | 2606 EMAC_MDIO_COMM_COMMAND_WRITE_22 | 2607 EMAC_MDIO_COMM_START_BUSY); 2608 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); 2609 2610 for (i = 0; i < 50; i++) { 2611 udelay(10); 2612 2613 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); 2614 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) { 2615 udelay(5); 2616 break; 2617 } 2618 } 2619 if (tmp & EMAC_MDIO_COMM_START_BUSY) { 2620 DP(NETIF_MSG_LINK, "write phy register failed\n"); 2621 rc = -EFAULT; 2622 } 2623 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode); 2624 return rc; 2625 } 2626 2627 static int bnx2x_cl22_read(struct bnx2x *bp, 2628 struct bnx2x_phy *phy, 2629 u16 reg, u16 *ret_val) 2630 { 2631 u32 val, mode; 2632 u16 i; 2633 int rc = 0; 2634 2635 /* Switch to CL22 */ 2636 mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE); 2637 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, 2638 mode & ~EMAC_MDIO_MODE_CLAUSE_45); 2639 2640 /* Address */ 2641 val = ((phy->addr << 21) | (reg << 16) | 2642 EMAC_MDIO_COMM_COMMAND_READ_22 | 2643 EMAC_MDIO_COMM_START_BUSY); 2644 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); 2645 2646 for (i = 0; i < 50; i++) { 2647 udelay(10); 2648 2649 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); 2650 if (!(val & EMAC_MDIO_COMM_START_BUSY)) { 2651 *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA); 2652 udelay(5); 2653 break; 2654 } 2655 } 2656 if (val & EMAC_MDIO_COMM_START_BUSY) { 2657 DP(NETIF_MSG_LINK, "read phy register failed\n"); 2658 2659 *ret_val = 0; 2660 rc = -EFAULT; 2661 } 2662 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode); 2663 return rc; 2664 } 2665 2666 /******************************************************************/ 2667 /* CL45 access functions */ 2668 /******************************************************************/ 2669 static int bnx2x_cl45_read(struct bnx2x *bp, struct bnx2x_phy *phy, 2670 u8 devad, u16 reg, u16 *ret_val) 2671 { 2672 u32 val; 2673 u16 i; 2674 int rc = 0; 2675 u32 chip_id; 2676 if (phy->flags & FLAGS_MDC_MDIO_WA_G) { 2677 chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) | 2678 ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12); 2679 bnx2x_set_mdio_clk(bp, chip_id, phy->mdio_ctrl); 2680 } 2681 2682 if (phy->flags & FLAGS_MDC_MDIO_WA_B0) 2683 bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, 2684 EMAC_MDIO_STATUS_10MB); 2685 /* Address */ 2686 val = ((phy->addr << 21) | (devad << 16) | reg | 2687 EMAC_MDIO_COMM_COMMAND_ADDRESS | 2688 EMAC_MDIO_COMM_START_BUSY); 2689 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); 2690 2691 for (i = 0; i < 50; i++) { 2692 udelay(10); 2693 2694 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); 2695 if (!(val & EMAC_MDIO_COMM_START_BUSY)) { 2696 udelay(5); 2697 break; 2698 } 2699 } 2700 if (val & EMAC_MDIO_COMM_START_BUSY) { 2701 DP(NETIF_MSG_LINK, "read phy register failed\n"); 2702 netdev_err(bp->dev, "MDC/MDIO access timeout\n"); 2703 *ret_val = 0; 2704 rc = -EFAULT; 2705 } else { 2706 /* Data */ 2707 val = ((phy->addr << 21) | (devad << 16) | 2708 EMAC_MDIO_COMM_COMMAND_READ_45 | 2709 EMAC_MDIO_COMM_START_BUSY); 2710 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); 2711 2712 for (i = 0; i < 50; i++) { 2713 udelay(10); 2714 2715 val = REG_RD(bp, phy->mdio_ctrl + 2716 EMAC_REG_EMAC_MDIO_COMM); 2717 if (!(val & EMAC_MDIO_COMM_START_BUSY)) { 2718 *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA); 2719 break; 2720 } 2721 } 2722 if (val & EMAC_MDIO_COMM_START_BUSY) { 2723 DP(NETIF_MSG_LINK, "read phy register failed\n"); 2724 netdev_err(bp->dev, "MDC/MDIO access timeout\n"); 2725 *ret_val = 0; 2726 rc = -EFAULT; 2727 } 2728 } 2729 /* Work around for E3 A0 */ 2730 if (phy->flags & FLAGS_MDC_MDIO_WA) { 2731 phy->flags ^= FLAGS_DUMMY_READ; 2732 if (phy->flags & FLAGS_DUMMY_READ) { 2733 u16 temp_val; 2734 bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val); 2735 } 2736 } 2737 2738 if (phy->flags & FLAGS_MDC_MDIO_WA_B0) 2739 bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, 2740 EMAC_MDIO_STATUS_10MB); 2741 return rc; 2742 } 2743 2744 static int bnx2x_cl45_write(struct bnx2x *bp, struct bnx2x_phy *phy, 2745 u8 devad, u16 reg, u16 val) 2746 { 2747 u32 tmp; 2748 u8 i; 2749 int rc = 0; 2750 u32 chip_id; 2751 if (phy->flags & FLAGS_MDC_MDIO_WA_G) { 2752 chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) | 2753 ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12); 2754 bnx2x_set_mdio_clk(bp, chip_id, phy->mdio_ctrl); 2755 } 2756 2757 if (phy->flags & FLAGS_MDC_MDIO_WA_B0) 2758 bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, 2759 EMAC_MDIO_STATUS_10MB); 2760 2761 /* Address */ 2762 tmp = ((phy->addr << 21) | (devad << 16) | reg | 2763 EMAC_MDIO_COMM_COMMAND_ADDRESS | 2764 EMAC_MDIO_COMM_START_BUSY); 2765 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); 2766 2767 for (i = 0; i < 50; i++) { 2768 udelay(10); 2769 2770 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); 2771 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) { 2772 udelay(5); 2773 break; 2774 } 2775 } 2776 if (tmp & EMAC_MDIO_COMM_START_BUSY) { 2777 DP(NETIF_MSG_LINK, "write phy register failed\n"); 2778 netdev_err(bp->dev, "MDC/MDIO access timeout\n"); 2779 rc = -EFAULT; 2780 } else { 2781 /* Data */ 2782 tmp = ((phy->addr << 21) | (devad << 16) | val | 2783 EMAC_MDIO_COMM_COMMAND_WRITE_45 | 2784 EMAC_MDIO_COMM_START_BUSY); 2785 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); 2786 2787 for (i = 0; i < 50; i++) { 2788 udelay(10); 2789 2790 tmp = REG_RD(bp, phy->mdio_ctrl + 2791 EMAC_REG_EMAC_MDIO_COMM); 2792 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) { 2793 udelay(5); 2794 break; 2795 } 2796 } 2797 if (tmp & EMAC_MDIO_COMM_START_BUSY) { 2798 DP(NETIF_MSG_LINK, "write phy register failed\n"); 2799 netdev_err(bp->dev, "MDC/MDIO access timeout\n"); 2800 rc = -EFAULT; 2801 } 2802 } 2803 /* Work around for E3 A0 */ 2804 if (phy->flags & FLAGS_MDC_MDIO_WA) { 2805 phy->flags ^= FLAGS_DUMMY_READ; 2806 if (phy->flags & FLAGS_DUMMY_READ) { 2807 u16 temp_val; 2808 bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val); 2809 } 2810 } 2811 if (phy->flags & FLAGS_MDC_MDIO_WA_B0) 2812 bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, 2813 EMAC_MDIO_STATUS_10MB); 2814 return rc; 2815 } 2816 2817 /******************************************************************/ 2818 /* EEE section */ 2819 /******************************************************************/ 2820 static u8 bnx2x_eee_has_cap(struct link_params *params) 2821 { 2822 struct bnx2x *bp = params->bp; 2823 2824 if (REG_RD(bp, params->shmem2_base) <= 2825 offsetof(struct shmem2_region, eee_status[params->port])) 2826 return 0; 2827 2828 return 1; 2829 } 2830 2831 static int bnx2x_eee_nvram_to_time(u32 nvram_mode, u32 *idle_timer) 2832 { 2833 switch (nvram_mode) { 2834 case PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED: 2835 *idle_timer = EEE_MODE_NVRAM_BALANCED_TIME; 2836 break; 2837 case PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE: 2838 *idle_timer = EEE_MODE_NVRAM_AGGRESSIVE_TIME; 2839 break; 2840 case PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY: 2841 *idle_timer = EEE_MODE_NVRAM_LATENCY_TIME; 2842 break; 2843 default: 2844 *idle_timer = 0; 2845 break; 2846 } 2847 2848 return 0; 2849 } 2850 2851 static int bnx2x_eee_time_to_nvram(u32 idle_timer, u32 *nvram_mode) 2852 { 2853 switch (idle_timer) { 2854 case EEE_MODE_NVRAM_BALANCED_TIME: 2855 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED; 2856 break; 2857 case EEE_MODE_NVRAM_AGGRESSIVE_TIME: 2858 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE; 2859 break; 2860 case EEE_MODE_NVRAM_LATENCY_TIME: 2861 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY; 2862 break; 2863 default: 2864 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED; 2865 break; 2866 } 2867 2868 return 0; 2869 } 2870 2871 static u32 bnx2x_eee_calc_timer(struct link_params *params) 2872 { 2873 u32 eee_mode, eee_idle; 2874 struct bnx2x *bp = params->bp; 2875 2876 if (params->eee_mode & EEE_MODE_OVERRIDE_NVRAM) { 2877 if (params->eee_mode & EEE_MODE_OUTPUT_TIME) { 2878 /* time value in eee_mode --> used directly*/ 2879 eee_idle = params->eee_mode & EEE_MODE_TIMER_MASK; 2880 } else { 2881 /* hsi value in eee_mode --> time */ 2882 if (bnx2x_eee_nvram_to_time(params->eee_mode & 2883 EEE_MODE_NVRAM_MASK, 2884 &eee_idle)) 2885 return 0; 2886 } 2887 } else { 2888 /* hsi values in nvram --> time*/ 2889 eee_mode = ((REG_RD(bp, params->shmem_base + 2890 offsetof(struct shmem_region, dev_info. 2891 port_feature_config[params->port]. 2892 eee_power_mode)) & 2893 PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >> 2894 PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT); 2895 2896 if (bnx2x_eee_nvram_to_time(eee_mode, &eee_idle)) 2897 return 0; 2898 } 2899 2900 return eee_idle; 2901 } 2902 2903 static int bnx2x_eee_set_timers(struct link_params *params, 2904 struct link_vars *vars) 2905 { 2906 u32 eee_idle = 0, eee_mode; 2907 struct bnx2x *bp = params->bp; 2908 2909 eee_idle = bnx2x_eee_calc_timer(params); 2910 2911 if (eee_idle) { 2912 REG_WR(bp, MISC_REG_CPMU_LP_IDLE_THR_P0 + (params->port << 2), 2913 eee_idle); 2914 } else if ((params->eee_mode & EEE_MODE_ENABLE_LPI) && 2915 (params->eee_mode & EEE_MODE_OVERRIDE_NVRAM) && 2916 (params->eee_mode & EEE_MODE_OUTPUT_TIME)) { 2917 DP(NETIF_MSG_LINK, "Error: Tx LPI is enabled with timer 0\n"); 2918 return -EINVAL; 2919 } 2920 2921 vars->eee_status &= ~(SHMEM_EEE_TIMER_MASK | SHMEM_EEE_TIME_OUTPUT_BIT); 2922 if (params->eee_mode & EEE_MODE_OUTPUT_TIME) { 2923 /* eee_idle in 1u --> eee_status in 16u */ 2924 eee_idle >>= 4; 2925 vars->eee_status |= (eee_idle & SHMEM_EEE_TIMER_MASK) | 2926 SHMEM_EEE_TIME_OUTPUT_BIT; 2927 } else { 2928 if (bnx2x_eee_time_to_nvram(eee_idle, &eee_mode)) 2929 return -EINVAL; 2930 vars->eee_status |= eee_mode; 2931 } 2932 2933 return 0; 2934 } 2935 2936 static int bnx2x_eee_initial_config(struct link_params *params, 2937 struct link_vars *vars, u8 mode) 2938 { 2939 vars->eee_status |= ((u32) mode) << SHMEM_EEE_SUPPORTED_SHIFT; 2940 2941 /* Propagate params' bits --> vars (for migration exposure) */ 2942 if (params->eee_mode & EEE_MODE_ENABLE_LPI) 2943 vars->eee_status |= SHMEM_EEE_LPI_REQUESTED_BIT; 2944 else 2945 vars->eee_status &= ~SHMEM_EEE_LPI_REQUESTED_BIT; 2946 2947 if (params->eee_mode & EEE_MODE_ADV_LPI) 2948 vars->eee_status |= SHMEM_EEE_REQUESTED_BIT; 2949 else 2950 vars->eee_status &= ~SHMEM_EEE_REQUESTED_BIT; 2951 2952 return bnx2x_eee_set_timers(params, vars); 2953 } 2954 2955 static int bnx2x_eee_disable(struct bnx2x_phy *phy, 2956 struct link_params *params, 2957 struct link_vars *vars) 2958 { 2959 struct bnx2x *bp = params->bp; 2960 2961 /* Make Certain LPI is disabled */ 2962 REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2), 0); 2963 2964 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, 0x0); 2965 2966 vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK; 2967 2968 return 0; 2969 } 2970 2971 static int bnx2x_eee_advertise(struct bnx2x_phy *phy, 2972 struct link_params *params, 2973 struct link_vars *vars, u8 modes) 2974 { 2975 struct bnx2x *bp = params->bp; 2976 u16 val = 0; 2977 2978 /* Mask events preventing LPI generation */ 2979 REG_WR(bp, MISC_REG_CPMU_LP_MASK_EXT_P0 + (params->port << 2), 0xfc20); 2980 2981 if (modes & SHMEM_EEE_10G_ADV) { 2982 DP(NETIF_MSG_LINK, "Advertise 10GBase-T EEE\n"); 2983 val |= 0x8; 2984 } 2985 if (modes & SHMEM_EEE_1G_ADV) { 2986 DP(NETIF_MSG_LINK, "Advertise 1GBase-T EEE\n"); 2987 val |= 0x4; 2988 } 2989 2990 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, val); 2991 2992 vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK; 2993 vars->eee_status |= (modes << SHMEM_EEE_ADV_STATUS_SHIFT); 2994 2995 return 0; 2996 } 2997 2998 static void bnx2x_update_mng_eee(struct link_params *params, u32 eee_status) 2999 { 3000 struct bnx2x *bp = params->bp; 3001 3002 if (bnx2x_eee_has_cap(params)) 3003 REG_WR(bp, params->shmem2_base + 3004 offsetof(struct shmem2_region, 3005 eee_status[params->port]), eee_status); 3006 } 3007 3008 static void bnx2x_eee_an_resolve(struct bnx2x_phy *phy, 3009 struct link_params *params, 3010 struct link_vars *vars) 3011 { 3012 struct bnx2x *bp = params->bp; 3013 u16 adv = 0, lp = 0; 3014 u32 lp_adv = 0; 3015 u8 neg = 0; 3016 3017 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, &adv); 3018 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_LP_EEE_ADV, &lp); 3019 3020 if (lp & 0x2) { 3021 lp_adv |= SHMEM_EEE_100M_ADV; 3022 if (adv & 0x2) { 3023 if (vars->line_speed == SPEED_100) 3024 neg = 1; 3025 DP(NETIF_MSG_LINK, "EEE negotiated - 100M\n"); 3026 } 3027 } 3028 if (lp & 0x14) { 3029 lp_adv |= SHMEM_EEE_1G_ADV; 3030 if (adv & 0x14) { 3031 if (vars->line_speed == SPEED_1000) 3032 neg = 1; 3033 DP(NETIF_MSG_LINK, "EEE negotiated - 1G\n"); 3034 } 3035 } 3036 if (lp & 0x68) { 3037 lp_adv |= SHMEM_EEE_10G_ADV; 3038 if (adv & 0x68) { 3039 if (vars->line_speed == SPEED_10000) 3040 neg = 1; 3041 DP(NETIF_MSG_LINK, "EEE negotiated - 10G\n"); 3042 } 3043 } 3044 3045 vars->eee_status &= ~SHMEM_EEE_LP_ADV_STATUS_MASK; 3046 vars->eee_status |= (lp_adv << SHMEM_EEE_LP_ADV_STATUS_SHIFT); 3047 3048 if (neg) { 3049 DP(NETIF_MSG_LINK, "EEE is active\n"); 3050 vars->eee_status |= SHMEM_EEE_ACTIVE_BIT; 3051 } 3052 3053 } 3054 3055 /******************************************************************/ 3056 /* BSC access functions from E3 */ 3057 /******************************************************************/ 3058 static void bnx2x_bsc_module_sel(struct link_params *params) 3059 { 3060 int idx; 3061 u32 board_cfg, sfp_ctrl; 3062 u32 i2c_pins[I2C_SWITCH_WIDTH], i2c_val[I2C_SWITCH_WIDTH]; 3063 struct bnx2x *bp = params->bp; 3064 u8 port = params->port; 3065 /* Read I2C output PINs */ 3066 board_cfg = REG_RD(bp, params->shmem_base + 3067 offsetof(struct shmem_region, 3068 dev_info.shared_hw_config.board)); 3069 i2c_pins[I2C_BSC0] = board_cfg & SHARED_HW_CFG_E3_I2C_MUX0_MASK; 3070 i2c_pins[I2C_BSC1] = (board_cfg & SHARED_HW_CFG_E3_I2C_MUX1_MASK) >> 3071 SHARED_HW_CFG_E3_I2C_MUX1_SHIFT; 3072 3073 /* Read I2C output value */ 3074 sfp_ctrl = REG_RD(bp, params->shmem_base + 3075 offsetof(struct shmem_region, 3076 dev_info.port_hw_config[port].e3_cmn_pin_cfg)); 3077 i2c_val[I2C_BSC0] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX0_MASK) > 0; 3078 i2c_val[I2C_BSC1] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX1_MASK) > 0; 3079 DP(NETIF_MSG_LINK, "Setting BSC switch\n"); 3080 for (idx = 0; idx < I2C_SWITCH_WIDTH; idx++) 3081 bnx2x_set_cfg_pin(bp, i2c_pins[idx], i2c_val[idx]); 3082 } 3083 3084 static int bnx2x_bsc_read(struct link_params *params, 3085 struct bnx2x *bp, 3086 u8 sl_devid, 3087 u16 sl_addr, 3088 u8 lc_addr, 3089 u8 xfer_cnt, 3090 u32 *data_array) 3091 { 3092 u32 val, i; 3093 int rc = 0; 3094 3095 if (xfer_cnt > 16) { 3096 DP(NETIF_MSG_LINK, "invalid xfer_cnt %d. Max is 16 bytes\n", 3097 xfer_cnt); 3098 return -EINVAL; 3099 } 3100 bnx2x_bsc_module_sel(params); 3101 3102 xfer_cnt = 16 - lc_addr; 3103 3104 /* Enable the engine */ 3105 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND); 3106 val |= MCPR_IMC_COMMAND_ENABLE; 3107 REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val); 3108 3109 /* Program slave device ID */ 3110 val = (sl_devid << 16) | sl_addr; 3111 REG_WR(bp, MCP_REG_MCPR_IMC_SLAVE_CONTROL, val); 3112 3113 /* Start xfer with 0 byte to update the address pointer ???*/ 3114 val = (MCPR_IMC_COMMAND_ENABLE) | 3115 (MCPR_IMC_COMMAND_WRITE_OP << 3116 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) | 3117 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) | (0); 3118 REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val); 3119 3120 /* Poll for completion */ 3121 i = 0; 3122 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND); 3123 while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) { 3124 udelay(10); 3125 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND); 3126 if (i++ > 1000) { 3127 DP(NETIF_MSG_LINK, "wr 0 byte timed out after %d try\n", 3128 i); 3129 rc = -EFAULT; 3130 break; 3131 } 3132 } 3133 if (rc == -EFAULT) 3134 return rc; 3135 3136 /* Start xfer with read op */ 3137 val = (MCPR_IMC_COMMAND_ENABLE) | 3138 (MCPR_IMC_COMMAND_READ_OP << 3139 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) | 3140 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) | 3141 (xfer_cnt); 3142 REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val); 3143 3144 /* Poll for completion */ 3145 i = 0; 3146 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND); 3147 while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) { 3148 udelay(10); 3149 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND); 3150 if (i++ > 1000) { 3151 DP(NETIF_MSG_LINK, "rd op timed out after %d try\n", i); 3152 rc = -EFAULT; 3153 break; 3154 } 3155 } 3156 if (rc == -EFAULT) 3157 return rc; 3158 3159 for (i = (lc_addr >> 2); i < 4; i++) { 3160 data_array[i] = REG_RD(bp, (MCP_REG_MCPR_IMC_DATAREG0 + i*4)); 3161 #ifdef __BIG_ENDIAN 3162 data_array[i] = ((data_array[i] & 0x000000ff) << 24) | 3163 ((data_array[i] & 0x0000ff00) << 8) | 3164 ((data_array[i] & 0x00ff0000) >> 8) | 3165 ((data_array[i] & 0xff000000) >> 24); 3166 #endif 3167 } 3168 return rc; 3169 } 3170 3171 static void bnx2x_cl45_read_or_write(struct bnx2x *bp, struct bnx2x_phy *phy, 3172 u8 devad, u16 reg, u16 or_val) 3173 { 3174 u16 val; 3175 bnx2x_cl45_read(bp, phy, devad, reg, &val); 3176 bnx2x_cl45_write(bp, phy, devad, reg, val | or_val); 3177 } 3178 3179 static void bnx2x_cl45_read_and_write(struct bnx2x *bp, 3180 struct bnx2x_phy *phy, 3181 u8 devad, u16 reg, u16 and_val) 3182 { 3183 u16 val; 3184 bnx2x_cl45_read(bp, phy, devad, reg, &val); 3185 bnx2x_cl45_write(bp, phy, devad, reg, val & and_val); 3186 } 3187 3188 int bnx2x_phy_read(struct link_params *params, u8 phy_addr, 3189 u8 devad, u16 reg, u16 *ret_val) 3190 { 3191 u8 phy_index; 3192 /* Probe for the phy according to the given phy_addr, and execute 3193 * the read request on it 3194 */ 3195 for (phy_index = 0; phy_index < params->num_phys; phy_index++) { 3196 if (params->phy[phy_index].addr == phy_addr) { 3197 return bnx2x_cl45_read(params->bp, 3198 ¶ms->phy[phy_index], devad, 3199 reg, ret_val); 3200 } 3201 } 3202 return -EINVAL; 3203 } 3204 3205 int bnx2x_phy_write(struct link_params *params, u8 phy_addr, 3206 u8 devad, u16 reg, u16 val) 3207 { 3208 u8 phy_index; 3209 /* Probe for the phy according to the given phy_addr, and execute 3210 * the write request on it 3211 */ 3212 for (phy_index = 0; phy_index < params->num_phys; phy_index++) { 3213 if (params->phy[phy_index].addr == phy_addr) { 3214 return bnx2x_cl45_write(params->bp, 3215 ¶ms->phy[phy_index], devad, 3216 reg, val); 3217 } 3218 } 3219 return -EINVAL; 3220 } 3221 static u8 bnx2x_get_warpcore_lane(struct bnx2x_phy *phy, 3222 struct link_params *params) 3223 { 3224 u8 lane = 0; 3225 struct bnx2x *bp = params->bp; 3226 u32 path_swap, path_swap_ovr; 3227 u8 path, port; 3228 3229 path = BP_PATH(bp); 3230 port = params->port; 3231 3232 if (bnx2x_is_4_port_mode(bp)) { 3233 u32 port_swap, port_swap_ovr; 3234 3235 /* Figure out path swap value */ 3236 path_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP_OVWR); 3237 if (path_swap_ovr & 0x1) 3238 path_swap = (path_swap_ovr & 0x2); 3239 else 3240 path_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP); 3241 3242 if (path_swap) 3243 path = path ^ 1; 3244 3245 /* Figure out port swap value */ 3246 port_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP_OVWR); 3247 if (port_swap_ovr & 0x1) 3248 port_swap = (port_swap_ovr & 0x2); 3249 else 3250 port_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP); 3251 3252 if (port_swap) 3253 port = port ^ 1; 3254 3255 lane = (port<<1) + path; 3256 } else { /* Two port mode - no port swap */ 3257 3258 /* Figure out path swap value */ 3259 path_swap_ovr = 3260 REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP_OVWR); 3261 if (path_swap_ovr & 0x1) { 3262 path_swap = (path_swap_ovr & 0x2); 3263 } else { 3264 path_swap = 3265 REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP); 3266 } 3267 if (path_swap) 3268 path = path ^ 1; 3269 3270 lane = path << 1 ; 3271 } 3272 return lane; 3273 } 3274 3275 static void bnx2x_set_aer_mmd(struct link_params *params, 3276 struct bnx2x_phy *phy) 3277 { 3278 u32 ser_lane; 3279 u16 offset, aer_val; 3280 struct bnx2x *bp = params->bp; 3281 ser_lane = ((params->lane_config & 3282 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >> 3283 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT); 3284 3285 offset = (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ? 3286 (phy->addr + ser_lane) : 0; 3287 3288 if (USES_WARPCORE(bp)) { 3289 aer_val = bnx2x_get_warpcore_lane(phy, params); 3290 /* In Dual-lane mode, two lanes are joined together, 3291 * so in order to configure them, the AER broadcast method is 3292 * used here. 3293 * 0x200 is the broadcast address for lanes 0,1 3294 * 0x201 is the broadcast address for lanes 2,3 3295 */ 3296 if (phy->flags & FLAGS_WC_DUAL_MODE) 3297 aer_val = (aer_val >> 1) | 0x200; 3298 } else if (CHIP_IS_E2(bp)) 3299 aer_val = 0x3800 + offset - 1; 3300 else 3301 aer_val = 0x3800 + offset; 3302 3303 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, 3304 MDIO_AER_BLOCK_AER_REG, aer_val); 3305 3306 } 3307 3308 /******************************************************************/ 3309 /* Internal phy section */ 3310 /******************************************************************/ 3311 3312 static void bnx2x_set_serdes_access(struct bnx2x *bp, u8 port) 3313 { 3314 u32 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0; 3315 3316 /* Set Clause 22 */ 3317 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 1); 3318 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000); 3319 udelay(500); 3320 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f); 3321 udelay(500); 3322 /* Set Clause 45 */ 3323 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 0); 3324 } 3325 3326 static void bnx2x_serdes_deassert(struct bnx2x *bp, u8 port) 3327 { 3328 u32 val; 3329 3330 DP(NETIF_MSG_LINK, "bnx2x_serdes_deassert\n"); 3331 3332 val = SERDES_RESET_BITS << (port*16); 3333 3334 /* Reset and unreset the SerDes/XGXS */ 3335 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val); 3336 udelay(500); 3337 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val); 3338 3339 bnx2x_set_serdes_access(bp, port); 3340 3341 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_DEVAD + port*0x10, 3342 DEFAULT_PHY_DEV_ADDR); 3343 } 3344 3345 static void bnx2x_xgxs_specific_func(struct bnx2x_phy *phy, 3346 struct link_params *params, 3347 u32 action) 3348 { 3349 struct bnx2x *bp = params->bp; 3350 switch (action) { 3351 case PHY_INIT: 3352 /* Set correct devad */ 3353 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_ST + params->port*0x18, 0); 3354 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + params->port*0x18, 3355 phy->def_md_devad); 3356 break; 3357 } 3358 } 3359 3360 static void bnx2x_xgxs_deassert(struct link_params *params) 3361 { 3362 struct bnx2x *bp = params->bp; 3363 u8 port; 3364 u32 val; 3365 DP(NETIF_MSG_LINK, "bnx2x_xgxs_deassert\n"); 3366 port = params->port; 3367 3368 val = XGXS_RESET_BITS << (port*16); 3369 3370 /* Reset and unreset the SerDes/XGXS */ 3371 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val); 3372 udelay(500); 3373 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val); 3374 bnx2x_xgxs_specific_func(¶ms->phy[INT_PHY], params, 3375 PHY_INIT); 3376 } 3377 3378 static void bnx2x_calc_ieee_aneg_adv(struct bnx2x_phy *phy, 3379 struct link_params *params, u16 *ieee_fc) 3380 { 3381 struct bnx2x *bp = params->bp; 3382 *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX; 3383 /* Resolve pause mode and advertisement Please refer to Table 3384 * 28B-3 of the 802.3ab-1999 spec 3385 */ 3386 3387 switch (phy->req_flow_ctrl) { 3388 case BNX2X_FLOW_CTRL_AUTO: 3389 switch (params->req_fc_auto_adv) { 3390 case BNX2X_FLOW_CTRL_BOTH: 3391 case BNX2X_FLOW_CTRL_RX: 3392 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; 3393 break; 3394 case BNX2X_FLOW_CTRL_TX: 3395 *ieee_fc |= 3396 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC; 3397 break; 3398 default: 3399 break; 3400 } 3401 break; 3402 case BNX2X_FLOW_CTRL_TX: 3403 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC; 3404 break; 3405 3406 case BNX2X_FLOW_CTRL_RX: 3407 case BNX2X_FLOW_CTRL_BOTH: 3408 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; 3409 break; 3410 3411 case BNX2X_FLOW_CTRL_NONE: 3412 default: 3413 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE; 3414 break; 3415 } 3416 DP(NETIF_MSG_LINK, "ieee_fc = 0x%x\n", *ieee_fc); 3417 } 3418 3419 static void set_phy_vars(struct link_params *params, 3420 struct link_vars *vars) 3421 { 3422 struct bnx2x *bp = params->bp; 3423 u8 actual_phy_idx, phy_index, link_cfg_idx; 3424 u8 phy_config_swapped = params->multi_phy_config & 3425 PORT_HW_CFG_PHY_SWAPPED_ENABLED; 3426 for (phy_index = INT_PHY; phy_index < params->num_phys; 3427 phy_index++) { 3428 link_cfg_idx = LINK_CONFIG_IDX(phy_index); 3429 actual_phy_idx = phy_index; 3430 if (phy_config_swapped) { 3431 if (phy_index == EXT_PHY1) 3432 actual_phy_idx = EXT_PHY2; 3433 else if (phy_index == EXT_PHY2) 3434 actual_phy_idx = EXT_PHY1; 3435 } 3436 params->phy[actual_phy_idx].req_flow_ctrl = 3437 params->req_flow_ctrl[link_cfg_idx]; 3438 3439 params->phy[actual_phy_idx].req_line_speed = 3440 params->req_line_speed[link_cfg_idx]; 3441 3442 params->phy[actual_phy_idx].speed_cap_mask = 3443 params->speed_cap_mask[link_cfg_idx]; 3444 3445 params->phy[actual_phy_idx].req_duplex = 3446 params->req_duplex[link_cfg_idx]; 3447 3448 if (params->req_line_speed[link_cfg_idx] == 3449 SPEED_AUTO_NEG) 3450 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED; 3451 3452 DP(NETIF_MSG_LINK, "req_flow_ctrl %x, req_line_speed %x," 3453 " speed_cap_mask %x\n", 3454 params->phy[actual_phy_idx].req_flow_ctrl, 3455 params->phy[actual_phy_idx].req_line_speed, 3456 params->phy[actual_phy_idx].speed_cap_mask); 3457 } 3458 } 3459 3460 static void bnx2x_ext_phy_set_pause(struct link_params *params, 3461 struct bnx2x_phy *phy, 3462 struct link_vars *vars) 3463 { 3464 u16 val; 3465 struct bnx2x *bp = params->bp; 3466 /* Read modify write pause advertizing */ 3467 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &val); 3468 3469 val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH; 3470 3471 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */ 3472 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); 3473 if ((vars->ieee_fc & 3474 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) == 3475 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) { 3476 val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC; 3477 } 3478 if ((vars->ieee_fc & 3479 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) == 3480 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) { 3481 val |= MDIO_AN_REG_ADV_PAUSE_PAUSE; 3482 } 3483 DP(NETIF_MSG_LINK, "Ext phy AN advertize 0x%x\n", val); 3484 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val); 3485 } 3486 3487 static void bnx2x_pause_resolve(struct bnx2x_phy *phy, 3488 struct link_params *params, 3489 struct link_vars *vars, 3490 u32 pause_result) 3491 { 3492 struct bnx2x *bp = params->bp; 3493 /* LD LP */ 3494 switch (pause_result) { /* ASYM P ASYM P */ 3495 case 0xb: /* 1 0 1 1 */ 3496 DP(NETIF_MSG_LINK, "Flow Control: TX only\n"); 3497 vars->flow_ctrl = BNX2X_FLOW_CTRL_TX; 3498 break; 3499 3500 case 0xe: /* 1 1 1 0 */ 3501 DP(NETIF_MSG_LINK, "Flow Control: RX only\n"); 3502 vars->flow_ctrl = BNX2X_FLOW_CTRL_RX; 3503 break; 3504 3505 case 0x5: /* 0 1 0 1 */ 3506 case 0x7: /* 0 1 1 1 */ 3507 case 0xd: /* 1 1 0 1 */ 3508 case 0xf: /* 1 1 1 1 */ 3509 /* If the user selected to advertise RX ONLY, 3510 * although we advertised both, need to enable 3511 * RX only. 3512 */ 3513 if (params->req_fc_auto_adv == BNX2X_FLOW_CTRL_BOTH) { 3514 DP(NETIF_MSG_LINK, "Flow Control: RX & TX\n"); 3515 vars->flow_ctrl = BNX2X_FLOW_CTRL_BOTH; 3516 } else { 3517 DP(NETIF_MSG_LINK, "Flow Control: RX only\n"); 3518 vars->flow_ctrl = BNX2X_FLOW_CTRL_RX; 3519 } 3520 break; 3521 3522 default: 3523 DP(NETIF_MSG_LINK, "Flow Control: None\n"); 3524 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; 3525 break; 3526 } 3527 if (pause_result & (1<<0)) 3528 vars->link_status |= LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE; 3529 if (pause_result & (1<<1)) 3530 vars->link_status |= LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE; 3531 3532 } 3533 3534 static void bnx2x_ext_phy_update_adv_fc(struct bnx2x_phy *phy, 3535 struct link_params *params, 3536 struct link_vars *vars) 3537 { 3538 u16 ld_pause; /* local */ 3539 u16 lp_pause; /* link partner */ 3540 u16 pause_result; 3541 struct bnx2x *bp = params->bp; 3542 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) { 3543 bnx2x_cl22_read(bp, phy, 0x4, &ld_pause); 3544 bnx2x_cl22_read(bp, phy, 0x5, &lp_pause); 3545 } else if (CHIP_IS_E3(bp) && 3546 SINGLE_MEDIA_DIRECT(params)) { 3547 u8 lane = bnx2x_get_warpcore_lane(phy, params); 3548 u16 gp_status, gp_mask; 3549 bnx2x_cl45_read(bp, phy, 3550 MDIO_AN_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_4, 3551 &gp_status); 3552 gp_mask = (MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL | 3553 MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP) << 3554 lane; 3555 if ((gp_status & gp_mask) == gp_mask) { 3556 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, 3557 MDIO_AN_REG_ADV_PAUSE, &ld_pause); 3558 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, 3559 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause); 3560 } else { 3561 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, 3562 MDIO_AN_REG_CL37_FC_LD, &ld_pause); 3563 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, 3564 MDIO_AN_REG_CL37_FC_LP, &lp_pause); 3565 ld_pause = ((ld_pause & 3566 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) 3567 << 3); 3568 lp_pause = ((lp_pause & 3569 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) 3570 << 3); 3571 } 3572 } else { 3573 bnx2x_cl45_read(bp, phy, 3574 MDIO_AN_DEVAD, 3575 MDIO_AN_REG_ADV_PAUSE, &ld_pause); 3576 bnx2x_cl45_read(bp, phy, 3577 MDIO_AN_DEVAD, 3578 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause); 3579 } 3580 pause_result = (ld_pause & 3581 MDIO_AN_REG_ADV_PAUSE_MASK) >> 8; 3582 pause_result |= (lp_pause & 3583 MDIO_AN_REG_ADV_PAUSE_MASK) >> 10; 3584 DP(NETIF_MSG_LINK, "Ext PHY pause result 0x%x\n", pause_result); 3585 bnx2x_pause_resolve(phy, params, vars, pause_result); 3586 3587 } 3588 3589 static u8 bnx2x_ext_phy_resolve_fc(struct bnx2x_phy *phy, 3590 struct link_params *params, 3591 struct link_vars *vars) 3592 { 3593 u8 ret = 0; 3594 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; 3595 if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO) { 3596 /* Update the advertised flow-controled of LD/LP in AN */ 3597 if (phy->req_line_speed == SPEED_AUTO_NEG) 3598 bnx2x_ext_phy_update_adv_fc(phy, params, vars); 3599 /* But set the flow-control result as the requested one */ 3600 vars->flow_ctrl = phy->req_flow_ctrl; 3601 } else if (phy->req_line_speed != SPEED_AUTO_NEG) 3602 vars->flow_ctrl = params->req_fc_auto_adv; 3603 else if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) { 3604 ret = 1; 3605 bnx2x_ext_phy_update_adv_fc(phy, params, vars); 3606 } 3607 return ret; 3608 } 3609 /******************************************************************/ 3610 /* Warpcore section */ 3611 /******************************************************************/ 3612 /* The init_internal_warpcore should mirror the xgxs, 3613 * i.e. reset the lane (if needed), set aer for the 3614 * init configuration, and set/clear SGMII flag. Internal 3615 * phy init is done purely in phy_init stage. 3616 */ 3617 #define WC_TX_DRIVER(post2, idriver, ipre, ifir) \ 3618 ((post2 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) | \ 3619 (idriver << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) | \ 3620 (ipre << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET) | \ 3621 (ifir << MDIO_WC_REG_TX0_TX_DRIVER_IFIR_OFFSET)) 3622 3623 #define WC_TX_FIR(post, main, pre) \ 3624 ((post << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) | \ 3625 (main << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) | \ 3626 (pre << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET)) 3627 3628 static void bnx2x_warpcore_enable_AN_KR2(struct bnx2x_phy *phy, 3629 struct link_params *params, 3630 struct link_vars *vars) 3631 { 3632 struct bnx2x *bp = params->bp; 3633 u16 i; 3634 static struct bnx2x_reg_set reg_set[] = { 3635 /* Step 1 - Program the TX/RX alignment markers */ 3636 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL5, 0xa157}, 3637 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL7, 0xcbe2}, 3638 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL6, 0x7537}, 3639 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL9, 0xa157}, 3640 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL11, 0xcbe2}, 3641 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL10, 0x7537}, 3642 /* Step 2 - Configure the NP registers */ 3643 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_USERB0_CTRL, 0x000a}, 3644 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL1, 0x6400}, 3645 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL3, 0x0620}, 3646 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CODE_FIELD, 0x0157}, 3647 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI1, 0x6464}, 3648 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI2, 0x3150}, 3649 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI3, 0x3150}, 3650 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0157}, 3651 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0620} 3652 }; 3653 DP(NETIF_MSG_LINK, "Enabling 20G-KR2\n"); 3654 3655 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 3656 MDIO_WC_REG_CL49_USERB0_CTRL, (3<<6)); 3657 3658 for (i = 0; i < ARRAY_SIZE(reg_set); i++) 3659 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg, 3660 reg_set[i].val); 3661 3662 /* Start KR2 work-around timer which handles BCM8073 link-parner */ 3663 params->link_attr_sync |= LINK_ATTR_SYNC_KR2_ENABLE; 3664 bnx2x_update_link_attr(params, params->link_attr_sync); 3665 } 3666 3667 static void bnx2x_disable_kr2(struct link_params *params, 3668 struct link_vars *vars, 3669 struct bnx2x_phy *phy) 3670 { 3671 struct bnx2x *bp = params->bp; 3672 int i; 3673 static struct bnx2x_reg_set reg_set[] = { 3674 /* Step 1 - Program the TX/RX alignment markers */ 3675 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL5, 0x7690}, 3676 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL7, 0xe647}, 3677 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL6, 0xc4f0}, 3678 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL9, 0x7690}, 3679 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL11, 0xe647}, 3680 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL10, 0xc4f0}, 3681 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_USERB0_CTRL, 0x000c}, 3682 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL1, 0x6000}, 3683 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL3, 0x0000}, 3684 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CODE_FIELD, 0x0002}, 3685 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI1, 0x0000}, 3686 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI2, 0x0af7}, 3687 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI3, 0x0af7}, 3688 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0002}, 3689 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0000} 3690 }; 3691 DP(NETIF_MSG_LINK, "Disabling 20G-KR2\n"); 3692 3693 for (i = 0; i < ARRAY_SIZE(reg_set); i++) 3694 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg, 3695 reg_set[i].val); 3696 params->link_attr_sync &= ~LINK_ATTR_SYNC_KR2_ENABLE; 3697 bnx2x_update_link_attr(params, params->link_attr_sync); 3698 3699 vars->check_kr2_recovery_cnt = CHECK_KR2_RECOVERY_CNT; 3700 } 3701 3702 static void bnx2x_warpcore_set_lpi_passthrough(struct bnx2x_phy *phy, 3703 struct link_params *params) 3704 { 3705 struct bnx2x *bp = params->bp; 3706 3707 DP(NETIF_MSG_LINK, "Configure WC for LPI pass through\n"); 3708 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3709 MDIO_WC_REG_EEE_COMBO_CONTROL0, 0x7c); 3710 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 3711 MDIO_WC_REG_DIGITAL4_MISC5, 0xc000); 3712 } 3713 3714 static void bnx2x_warpcore_restart_AN_KR(struct bnx2x_phy *phy, 3715 struct link_params *params) 3716 { 3717 /* Restart autoneg on the leading lane only */ 3718 struct bnx2x *bp = params->bp; 3719 u16 lane = bnx2x_get_warpcore_lane(phy, params); 3720 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, 3721 MDIO_AER_BLOCK_AER_REG, lane); 3722 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, 3723 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200); 3724 3725 /* Restore AER */ 3726 bnx2x_set_aer_mmd(params, phy); 3727 } 3728 3729 static void bnx2x_warpcore_enable_AN_KR(struct bnx2x_phy *phy, 3730 struct link_params *params, 3731 struct link_vars *vars) { 3732 u16 lane, i, cl72_ctrl, an_adv = 0, val; 3733 u32 wc_lane_config; 3734 struct bnx2x *bp = params->bp; 3735 static struct bnx2x_reg_set reg_set[] = { 3736 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7}, 3737 {MDIO_PMA_DEVAD, MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0x0}, 3738 {MDIO_WC_DEVAD, MDIO_WC_REG_RX66_CONTROL, 0x7415}, 3739 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x6190}, 3740 /* Disable Autoneg: re-enable it after adv is done. */ 3741 {MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0}, 3742 {MDIO_PMA_DEVAD, MDIO_WC_REG_PMD_KR_CONTROL, 0x2}, 3743 {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP, 0}, 3744 }; 3745 DP(NETIF_MSG_LINK, "Enable Auto Negotiation for KR\n"); 3746 /* Set to default registers that may be overriden by 10G force */ 3747 for (i = 0; i < ARRAY_SIZE(reg_set); i++) 3748 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg, 3749 reg_set[i].val); 3750 3751 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 3752 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, &cl72_ctrl); 3753 cl72_ctrl &= 0x08ff; 3754 cl72_ctrl |= 0x3800; 3755 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3756 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, cl72_ctrl); 3757 3758 /* Check adding advertisement for 1G KX */ 3759 if (((vars->line_speed == SPEED_AUTO_NEG) && 3760 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) || 3761 (vars->line_speed == SPEED_1000)) { 3762 u16 addr = MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2; 3763 an_adv |= (1<<5); 3764 3765 /* Enable CL37 1G Parallel Detect */ 3766 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, addr, 0x1); 3767 DP(NETIF_MSG_LINK, "Advertize 1G\n"); 3768 } 3769 if (((vars->line_speed == SPEED_AUTO_NEG) && 3770 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) || 3771 (vars->line_speed == SPEED_10000)) { 3772 /* Check adding advertisement for 10G KR */ 3773 an_adv |= (1<<7); 3774 /* Enable 10G Parallel Detect */ 3775 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, 3776 MDIO_AER_BLOCK_AER_REG, 0); 3777 3778 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, 3779 MDIO_WC_REG_PAR_DET_10G_CTRL, 1); 3780 bnx2x_set_aer_mmd(params, phy); 3781 DP(NETIF_MSG_LINK, "Advertize 10G\n"); 3782 } 3783 3784 /* Set Transmit PMD settings */ 3785 lane = bnx2x_get_warpcore_lane(phy, params); 3786 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3787 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 3788 WC_TX_DRIVER(0x02, 0x06, 0x09, 0)); 3789 /* Configure the next lane if dual mode */ 3790 if (phy->flags & FLAGS_WC_DUAL_MODE) 3791 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3792 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*(lane+1), 3793 WC_TX_DRIVER(0x02, 0x06, 0x09, 0)); 3794 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3795 MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL, 3796 0x03f0); 3797 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3798 MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL, 3799 0x03f0); 3800 3801 /* Advertised speeds */ 3802 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, 3803 MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, an_adv); 3804 3805 /* Advertised and set FEC (Forward Error Correction) */ 3806 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, 3807 MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2, 3808 (MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY | 3809 MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ)); 3810 3811 /* Enable CL37 BAM */ 3812 if (REG_RD(bp, params->shmem_base + 3813 offsetof(struct shmem_region, dev_info. 3814 port_hw_config[params->port].default_cfg)) & 3815 PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) { 3816 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 3817 MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL, 3818 1); 3819 DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n"); 3820 } 3821 3822 /* Advertise pause */ 3823 bnx2x_ext_phy_set_pause(params, phy, vars); 3824 vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY; 3825 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 3826 MDIO_WC_REG_DIGITAL5_MISC7, 0x100); 3827 3828 /* Over 1G - AN local device user page 1 */ 3829 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3830 MDIO_WC_REG_DIGITAL3_UP1, 0x1f); 3831 3832 if (((phy->req_line_speed == SPEED_AUTO_NEG) && 3833 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) || 3834 (phy->req_line_speed == SPEED_20000)) { 3835 3836 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, 3837 MDIO_AER_BLOCK_AER_REG, lane); 3838 3839 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 3840 MDIO_WC_REG_RX1_PCI_CTRL + (0x10*lane), 3841 (1<<11)); 3842 3843 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3844 MDIO_WC_REG_XGXS_X2_CONTROL3, 0x7); 3845 bnx2x_set_aer_mmd(params, phy); 3846 3847 bnx2x_warpcore_enable_AN_KR2(phy, params, vars); 3848 } else { 3849 /* Enable Auto-Detect to support 1G over CL37 as well */ 3850 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3851 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0x10); 3852 wc_lane_config = REG_RD(bp, params->shmem_base + 3853 offsetof(struct shmem_region, dev_info. 3854 shared_hw_config.wc_lane_config)); 3855 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 3856 MDIO_WC_REG_RX0_PCI_CTRL + (lane << 4), &val); 3857 /* Force cl48 sync_status LOW to avoid getting stuck in CL73 3858 * parallel-detect loop when CL73 and CL37 are enabled. 3859 */ 3860 val |= 1 << 11; 3861 3862 /* Restore Polarity settings in case it was run over by 3863 * previous link owner 3864 */ 3865 if (wc_lane_config & 3866 (SHARED_HW_CFG_RX_LANE0_POL_FLIP_ENABLED << lane)) 3867 val |= 3 << 2; 3868 else 3869 val &= ~(3 << 2); 3870 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3871 MDIO_WC_REG_RX0_PCI_CTRL + (lane << 4), 3872 val); 3873 3874 bnx2x_disable_kr2(params, vars, phy); 3875 } 3876 3877 /* Enable Autoneg: only on the main lane */ 3878 bnx2x_warpcore_restart_AN_KR(phy, params); 3879 } 3880 3881 static void bnx2x_warpcore_set_10G_KR(struct bnx2x_phy *phy, 3882 struct link_params *params, 3883 struct link_vars *vars) 3884 { 3885 struct bnx2x *bp = params->bp; 3886 u16 val16, i, lane; 3887 static struct bnx2x_reg_set reg_set[] = { 3888 /* Disable Autoneg */ 3889 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7}, 3890 {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, 3891 0x3f00}, 3892 {MDIO_AN_DEVAD, MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, 0}, 3893 {MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0}, 3894 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL3_UP1, 0x1}, 3895 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL5_MISC7, 0xa}, 3896 /* Leave cl72 training enable, needed for KR */ 3897 {MDIO_PMA_DEVAD, MDIO_WC_REG_PMD_KR_CONTROL, 0x2} 3898 }; 3899 3900 for (i = 0; i < ARRAY_SIZE(reg_set); i++) 3901 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg, 3902 reg_set[i].val); 3903 3904 lane = bnx2x_get_warpcore_lane(phy, params); 3905 /* Global registers */ 3906 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, 3907 MDIO_AER_BLOCK_AER_REG, 0); 3908 /* Disable CL36 PCS Tx */ 3909 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 3910 MDIO_WC_REG_XGXSBLK1_LANECTRL0, &val16); 3911 val16 &= ~(0x0011 << lane); 3912 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3913 MDIO_WC_REG_XGXSBLK1_LANECTRL0, val16); 3914 3915 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 3916 MDIO_WC_REG_XGXSBLK1_LANECTRL1, &val16); 3917 val16 |= (0x0303 << (lane << 1)); 3918 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3919 MDIO_WC_REG_XGXSBLK1_LANECTRL1, val16); 3920 /* Restore AER */ 3921 bnx2x_set_aer_mmd(params, phy); 3922 /* Set speed via PMA/PMD register */ 3923 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 3924 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040); 3925 3926 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 3927 MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0xB); 3928 3929 /* Enable encoded forced speed */ 3930 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3931 MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x30); 3932 3933 /* Turn TX scramble payload only the 64/66 scrambler */ 3934 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3935 MDIO_WC_REG_TX66_CONTROL, 0x9); 3936 3937 /* Turn RX scramble payload only the 64/66 scrambler */ 3938 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 3939 MDIO_WC_REG_RX66_CONTROL, 0xF9); 3940 3941 /* Set and clear loopback to cause a reset to 64/66 decoder */ 3942 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3943 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x4000); 3944 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3945 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0); 3946 3947 } 3948 3949 static void bnx2x_warpcore_set_10G_XFI(struct bnx2x_phy *phy, 3950 struct link_params *params, 3951 u8 is_xfi) 3952 { 3953 struct bnx2x *bp = params->bp; 3954 u16 misc1_val, tap_val, tx_driver_val, lane, val; 3955 u32 cfg_tap_val, tx_drv_brdct, tx_equal; 3956 u32 ifir_val, ipost2_val, ipre_driver_val; 3957 3958 /* Hold rxSeqStart */ 3959 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 3960 MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x8000); 3961 3962 /* Hold tx_fifo_reset */ 3963 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 3964 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, 0x1); 3965 3966 /* Disable CL73 AN */ 3967 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0); 3968 3969 /* Disable 100FX Enable and Auto-Detect */ 3970 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, 3971 MDIO_WC_REG_FX100_CTRL1, 0xFFFA); 3972 3973 /* Disable 100FX Idle detect */ 3974 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 3975 MDIO_WC_REG_FX100_CTRL3, 0x0080); 3976 3977 /* Set Block address to Remote PHY & Clear forced_speed[5] */ 3978 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, 3979 MDIO_WC_REG_DIGITAL4_MISC3, 0xFF7F); 3980 3981 /* Turn off auto-detect & fiber mode */ 3982 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, 3983 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 3984 0xFFEE); 3985 3986 /* Set filter_force_link, disable_false_link and parallel_detect */ 3987 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 3988 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &val); 3989 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3990 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 3991 ((val | 0x0006) & 0xFFFE)); 3992 3993 /* Set XFI / SFI */ 3994 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 3995 MDIO_WC_REG_SERDESDIGITAL_MISC1, &misc1_val); 3996 3997 misc1_val &= ~(0x1f); 3998 3999 if (is_xfi) { 4000 misc1_val |= 0x5; 4001 tap_val = WC_TX_FIR(0x08, 0x37, 0x00); 4002 tx_driver_val = WC_TX_DRIVER(0x00, 0x02, 0x03, 0); 4003 } else { 4004 cfg_tap_val = REG_RD(bp, params->shmem_base + 4005 offsetof(struct shmem_region, dev_info. 4006 port_hw_config[params->port]. 4007 sfi_tap_values)); 4008 4009 tx_equal = cfg_tap_val & PORT_HW_CFG_TX_EQUALIZATION_MASK; 4010 4011 misc1_val |= 0x9; 4012 4013 /* TAP values are controlled by nvram, if value there isn't 0 */ 4014 if (tx_equal) 4015 tap_val = (u16)tx_equal; 4016 else 4017 tap_val = WC_TX_FIR(0x0f, 0x2b, 0x02); 4018 4019 ifir_val = DEFAULT_TX_DRV_IFIR; 4020 ipost2_val = DEFAULT_TX_DRV_POST2; 4021 ipre_driver_val = DEFAULT_TX_DRV_IPRE_DRIVER; 4022 tx_drv_brdct = DEFAULT_TX_DRV_BRDCT; 4023 4024 /* If any of the IFIR/IPRE_DRIVER/POST@ is set, apply all 4025 * configuration. 4026 */ 4027 if (cfg_tap_val & (PORT_HW_CFG_TX_DRV_IFIR_MASK | 4028 PORT_HW_CFG_TX_DRV_IPREDRIVER_MASK | 4029 PORT_HW_CFG_TX_DRV_POST2_MASK)) { 4030 ifir_val = (cfg_tap_val & 4031 PORT_HW_CFG_TX_DRV_IFIR_MASK) >> 4032 PORT_HW_CFG_TX_DRV_IFIR_SHIFT; 4033 ipre_driver_val = (cfg_tap_val & 4034 PORT_HW_CFG_TX_DRV_IPREDRIVER_MASK) 4035 >> PORT_HW_CFG_TX_DRV_IPREDRIVER_SHIFT; 4036 ipost2_val = (cfg_tap_val & 4037 PORT_HW_CFG_TX_DRV_POST2_MASK) >> 4038 PORT_HW_CFG_TX_DRV_POST2_SHIFT; 4039 } 4040 4041 if (cfg_tap_val & PORT_HW_CFG_TX_DRV_BROADCAST_MASK) { 4042 tx_drv_brdct = (cfg_tap_val & 4043 PORT_HW_CFG_TX_DRV_BROADCAST_MASK) >> 4044 PORT_HW_CFG_TX_DRV_BROADCAST_SHIFT; 4045 } 4046 4047 tx_driver_val = WC_TX_DRIVER(ipost2_val, tx_drv_brdct, 4048 ipre_driver_val, ifir_val); 4049 } 4050 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4051 MDIO_WC_REG_SERDESDIGITAL_MISC1, misc1_val); 4052 4053 /* Set Transmit PMD settings */ 4054 lane = bnx2x_get_warpcore_lane(phy, params); 4055 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4056 MDIO_WC_REG_TX_FIR_TAP, 4057 tap_val | MDIO_WC_REG_TX_FIR_TAP_ENABLE); 4058 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4059 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 4060 tx_driver_val); 4061 4062 /* Enable fiber mode, enable and invert sig_det */ 4063 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 4064 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0xd); 4065 4066 /* Set Block address to Remote PHY & Set forced_speed[5], 40bit mode */ 4067 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 4068 MDIO_WC_REG_DIGITAL4_MISC3, 0x8080); 4069 4070 bnx2x_warpcore_set_lpi_passthrough(phy, params); 4071 4072 /* 10G XFI Full Duplex */ 4073 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4074 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x100); 4075 4076 /* Release tx_fifo_reset */ 4077 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, 4078 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, 4079 0xFFFE); 4080 /* Release rxSeqStart */ 4081 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, 4082 MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x7FFF); 4083 } 4084 4085 static void bnx2x_warpcore_set_20G_force_KR2(struct bnx2x_phy *phy, 4086 struct link_params *params) 4087 { 4088 u16 val; 4089 struct bnx2x *bp = params->bp; 4090 /* Set global registers, so set AER lane to 0 */ 4091 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, 4092 MDIO_AER_BLOCK_AER_REG, 0); 4093 4094 /* Disable sequencer */ 4095 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, 4096 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, ~(1<<13)); 4097 4098 bnx2x_set_aer_mmd(params, phy); 4099 4100 bnx2x_cl45_read_and_write(bp, phy, MDIO_PMA_DEVAD, 4101 MDIO_WC_REG_PMD_KR_CONTROL, ~(1<<1)); 4102 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, 4103 MDIO_AN_REG_CTRL, 0); 4104 /* Turn off CL73 */ 4105 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 4106 MDIO_WC_REG_CL73_USERB0_CTRL, &val); 4107 val &= ~(1<<5); 4108 val |= (1<<6); 4109 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4110 MDIO_WC_REG_CL73_USERB0_CTRL, val); 4111 4112 /* Set 20G KR2 force speed */ 4113 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 4114 MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x1f); 4115 4116 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 4117 MDIO_WC_REG_DIGITAL4_MISC3, (1<<7)); 4118 4119 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 4120 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, &val); 4121 val &= ~(3<<14); 4122 val |= (1<<15); 4123 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4124 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, val); 4125 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4126 MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP, 0x835A); 4127 4128 /* Enable sequencer (over lane 0) */ 4129 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, 4130 MDIO_AER_BLOCK_AER_REG, 0); 4131 4132 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 4133 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, (1<<13)); 4134 4135 bnx2x_set_aer_mmd(params, phy); 4136 } 4137 4138 static void bnx2x_warpcore_set_20G_DXGXS(struct bnx2x *bp, 4139 struct bnx2x_phy *phy, 4140 u16 lane) 4141 { 4142 /* Rx0 anaRxControl1G */ 4143 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4144 MDIO_WC_REG_RX0_ANARXCONTROL1G, 0x90); 4145 4146 /* Rx2 anaRxControl1G */ 4147 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4148 MDIO_WC_REG_RX2_ANARXCONTROL1G, 0x90); 4149 4150 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4151 MDIO_WC_REG_RX66_SCW0, 0xE070); 4152 4153 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4154 MDIO_WC_REG_RX66_SCW1, 0xC0D0); 4155 4156 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4157 MDIO_WC_REG_RX66_SCW2, 0xA0B0); 4158 4159 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4160 MDIO_WC_REG_RX66_SCW3, 0x8090); 4161 4162 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4163 MDIO_WC_REG_RX66_SCW0_MASK, 0xF0F0); 4164 4165 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4166 MDIO_WC_REG_RX66_SCW1_MASK, 0xF0F0); 4167 4168 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4169 MDIO_WC_REG_RX66_SCW2_MASK, 0xF0F0); 4170 4171 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4172 MDIO_WC_REG_RX66_SCW3_MASK, 0xF0F0); 4173 4174 /* Serdes Digital Misc1 */ 4175 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4176 MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6008); 4177 4178 /* Serdes Digital4 Misc3 */ 4179 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4180 MDIO_WC_REG_DIGITAL4_MISC3, 0x8088); 4181 4182 /* Set Transmit PMD settings */ 4183 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4184 MDIO_WC_REG_TX_FIR_TAP, 4185 (WC_TX_FIR(0x12, 0x2d, 0x00) | 4186 MDIO_WC_REG_TX_FIR_TAP_ENABLE)); 4187 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4188 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 4189 WC_TX_DRIVER(0x02, 0x02, 0x02, 0)); 4190 } 4191 4192 static void bnx2x_warpcore_set_sgmii_speed(struct bnx2x_phy *phy, 4193 struct link_params *params, 4194 u8 fiber_mode, 4195 u8 always_autoneg) 4196 { 4197 struct bnx2x *bp = params->bp; 4198 u16 val16, digctrl_kx1, digctrl_kx2; 4199 4200 /* Clear XFI clock comp in non-10G single lane mode. */ 4201 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, 4202 MDIO_WC_REG_RX66_CONTROL, ~(3<<13)); 4203 4204 bnx2x_warpcore_set_lpi_passthrough(phy, params); 4205 4206 if (always_autoneg || phy->req_line_speed == SPEED_AUTO_NEG) { 4207 /* SGMII Autoneg */ 4208 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 4209 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 4210 0x1000); 4211 DP(NETIF_MSG_LINK, "set SGMII AUTONEG\n"); 4212 } else { 4213 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 4214 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16); 4215 val16 &= 0xcebf; 4216 switch (phy->req_line_speed) { 4217 case SPEED_10: 4218 break; 4219 case SPEED_100: 4220 val16 |= 0x2000; 4221 break; 4222 case SPEED_1000: 4223 val16 |= 0x0040; 4224 break; 4225 default: 4226 DP(NETIF_MSG_LINK, 4227 "Speed not supported: 0x%x\n", phy->req_line_speed); 4228 return; 4229 } 4230 4231 if (phy->req_duplex == DUPLEX_FULL) 4232 val16 |= 0x0100; 4233 4234 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4235 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16); 4236 4237 DP(NETIF_MSG_LINK, "set SGMII force speed %d\n", 4238 phy->req_line_speed); 4239 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 4240 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16); 4241 DP(NETIF_MSG_LINK, " (readback) %x\n", val16); 4242 } 4243 4244 /* SGMII Slave mode and disable signal detect */ 4245 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 4246 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &digctrl_kx1); 4247 if (fiber_mode) 4248 digctrl_kx1 = 1; 4249 else 4250 digctrl_kx1 &= 0xff4a; 4251 4252 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4253 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 4254 digctrl_kx1); 4255 4256 /* Turn off parallel detect */ 4257 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 4258 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &digctrl_kx2); 4259 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4260 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 4261 (digctrl_kx2 & ~(1<<2))); 4262 4263 /* Re-enable parallel detect */ 4264 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4265 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 4266 (digctrl_kx2 | (1<<2))); 4267 4268 /* Enable autodet */ 4269 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4270 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 4271 (digctrl_kx1 | 0x10)); 4272 } 4273 4274 static void bnx2x_warpcore_reset_lane(struct bnx2x *bp, 4275 struct bnx2x_phy *phy, 4276 u8 reset) 4277 { 4278 u16 val; 4279 /* Take lane out of reset after configuration is finished */ 4280 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 4281 MDIO_WC_REG_DIGITAL5_MISC6, &val); 4282 if (reset) 4283 val |= 0xC000; 4284 else 4285 val &= 0x3FFF; 4286 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4287 MDIO_WC_REG_DIGITAL5_MISC6, val); 4288 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 4289 MDIO_WC_REG_DIGITAL5_MISC6, &val); 4290 } 4291 /* Clear SFI/XFI link settings registers */ 4292 static void bnx2x_warpcore_clear_regs(struct bnx2x_phy *phy, 4293 struct link_params *params, 4294 u16 lane) 4295 { 4296 struct bnx2x *bp = params->bp; 4297 u16 i; 4298 static struct bnx2x_reg_set wc_regs[] = { 4299 {MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0}, 4300 {MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL1, 0x014a}, 4301 {MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL3, 0x0800}, 4302 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL4_MISC3, 0x8008}, 4303 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 4304 0x0195}, 4305 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 4306 0x0007}, 4307 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, 4308 0x0002}, 4309 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6000}, 4310 {MDIO_WC_DEVAD, MDIO_WC_REG_TX_FIR_TAP, 0x0000}, 4311 {MDIO_WC_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040}, 4312 {MDIO_WC_DEVAD, MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0x0140} 4313 }; 4314 /* Set XFI clock comp as default. */ 4315 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 4316 MDIO_WC_REG_RX66_CONTROL, (3<<13)); 4317 4318 for (i = 0; i < ARRAY_SIZE(wc_regs); i++) 4319 bnx2x_cl45_write(bp, phy, wc_regs[i].devad, wc_regs[i].reg, 4320 wc_regs[i].val); 4321 4322 lane = bnx2x_get_warpcore_lane(phy, params); 4323 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4324 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 0x0990); 4325 4326 } 4327 4328 static int bnx2x_get_mod_abs_int_cfg(struct bnx2x *bp, 4329 u32 chip_id, 4330 u32 shmem_base, u8 port, 4331 u8 *gpio_num, u8 *gpio_port) 4332 { 4333 u32 cfg_pin; 4334 *gpio_num = 0; 4335 *gpio_port = 0; 4336 if (CHIP_IS_E3(bp)) { 4337 cfg_pin = (REG_RD(bp, shmem_base + 4338 offsetof(struct shmem_region, 4339 dev_info.port_hw_config[port].e3_sfp_ctrl)) & 4340 PORT_HW_CFG_E3_MOD_ABS_MASK) >> 4341 PORT_HW_CFG_E3_MOD_ABS_SHIFT; 4342 4343 /* Should not happen. This function called upon interrupt 4344 * triggered by GPIO ( since EPIO can only generate interrupts 4345 * to MCP). 4346 * So if this function was called and none of the GPIOs was set, 4347 * it means the shit hit the fan. 4348 */ 4349 if ((cfg_pin < PIN_CFG_GPIO0_P0) || 4350 (cfg_pin > PIN_CFG_GPIO3_P1)) { 4351 DP(NETIF_MSG_LINK, 4352 "No cfg pin %x for module detect indication\n", 4353 cfg_pin); 4354 return -EINVAL; 4355 } 4356 4357 *gpio_num = (cfg_pin - PIN_CFG_GPIO0_P0) & 0x3; 4358 *gpio_port = (cfg_pin - PIN_CFG_GPIO0_P0) >> 2; 4359 } else { 4360 *gpio_num = MISC_REGISTERS_GPIO_3; 4361 *gpio_port = port; 4362 } 4363 4364 return 0; 4365 } 4366 4367 static int bnx2x_is_sfp_module_plugged(struct bnx2x_phy *phy, 4368 struct link_params *params) 4369 { 4370 struct bnx2x *bp = params->bp; 4371 u8 gpio_num, gpio_port; 4372 u32 gpio_val; 4373 if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id, 4374 params->shmem_base, params->port, 4375 &gpio_num, &gpio_port) != 0) 4376 return 0; 4377 gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port); 4378 4379 /* Call the handling function in case module is detected */ 4380 if (gpio_val == 0) 4381 return 1; 4382 else 4383 return 0; 4384 } 4385 static int bnx2x_warpcore_get_sigdet(struct bnx2x_phy *phy, 4386 struct link_params *params) 4387 { 4388 u16 gp2_status_reg0, lane; 4389 struct bnx2x *bp = params->bp; 4390 4391 lane = bnx2x_get_warpcore_lane(phy, params); 4392 4393 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_0, 4394 &gp2_status_reg0); 4395 4396 return (gp2_status_reg0 >> (8+lane)) & 0x1; 4397 } 4398 4399 static void bnx2x_warpcore_config_runtime(struct bnx2x_phy *phy, 4400 struct link_params *params, 4401 struct link_vars *vars) 4402 { 4403 struct bnx2x *bp = params->bp; 4404 u32 serdes_net_if; 4405 u16 gp_status1 = 0, lnkup = 0, lnkup_kr = 0; 4406 4407 vars->turn_to_run_wc_rt = vars->turn_to_run_wc_rt ? 0 : 1; 4408 4409 if (!vars->turn_to_run_wc_rt) 4410 return; 4411 4412 if (vars->rx_tx_asic_rst) { 4413 u16 lane = bnx2x_get_warpcore_lane(phy, params); 4414 serdes_net_if = (REG_RD(bp, params->shmem_base + 4415 offsetof(struct shmem_region, dev_info. 4416 port_hw_config[params->port].default_cfg)) & 4417 PORT_HW_CFG_NET_SERDES_IF_MASK); 4418 4419 switch (serdes_net_if) { 4420 case PORT_HW_CFG_NET_SERDES_IF_KR: 4421 /* Do we get link yet? */ 4422 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 0x81d1, 4423 &gp_status1); 4424 lnkup = (gp_status1 >> (8+lane)) & 0x1;/* 1G */ 4425 /*10G KR*/ 4426 lnkup_kr = (gp_status1 >> (12+lane)) & 0x1; 4427 4428 if (lnkup_kr || lnkup) { 4429 vars->rx_tx_asic_rst = 0; 4430 } else { 4431 /* Reset the lane to see if link comes up.*/ 4432 bnx2x_warpcore_reset_lane(bp, phy, 1); 4433 bnx2x_warpcore_reset_lane(bp, phy, 0); 4434 4435 /* Restart Autoneg */ 4436 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, 4437 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200); 4438 4439 vars->rx_tx_asic_rst--; 4440 DP(NETIF_MSG_LINK, "0x%x retry left\n", 4441 vars->rx_tx_asic_rst); 4442 } 4443 break; 4444 4445 default: 4446 break; 4447 } 4448 4449 } /*params->rx_tx_asic_rst*/ 4450 4451 } 4452 static void bnx2x_warpcore_config_sfi(struct bnx2x_phy *phy, 4453 struct link_params *params) 4454 { 4455 u16 lane = bnx2x_get_warpcore_lane(phy, params); 4456 struct bnx2x *bp = params->bp; 4457 bnx2x_warpcore_clear_regs(phy, params, lane); 4458 if ((params->req_line_speed[LINK_CONFIG_IDX(INT_PHY)] == 4459 SPEED_10000) && 4460 (phy->media_type != ETH_PHY_SFP_1G_FIBER)) { 4461 DP(NETIF_MSG_LINK, "Setting 10G SFI\n"); 4462 bnx2x_warpcore_set_10G_XFI(phy, params, 0); 4463 } else { 4464 DP(NETIF_MSG_LINK, "Setting 1G Fiber\n"); 4465 bnx2x_warpcore_set_sgmii_speed(phy, params, 1, 0); 4466 } 4467 } 4468 4469 static void bnx2x_sfp_e3_set_transmitter(struct link_params *params, 4470 struct bnx2x_phy *phy, 4471 u8 tx_en) 4472 { 4473 struct bnx2x *bp = params->bp; 4474 u32 cfg_pin; 4475 u8 port = params->port; 4476 4477 cfg_pin = REG_RD(bp, params->shmem_base + 4478 offsetof(struct shmem_region, 4479 dev_info.port_hw_config[port].e3_sfp_ctrl)) & 4480 PORT_HW_CFG_E3_TX_LASER_MASK; 4481 /* Set the !tx_en since this pin is DISABLE_TX_LASER */ 4482 DP(NETIF_MSG_LINK, "Setting WC TX to %d\n", tx_en); 4483 4484 /* For 20G, the expected pin to be used is 3 pins after the current */ 4485 bnx2x_set_cfg_pin(bp, cfg_pin, tx_en ^ 1); 4486 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G) 4487 bnx2x_set_cfg_pin(bp, cfg_pin + 3, tx_en ^ 1); 4488 } 4489 4490 static void bnx2x_warpcore_config_init(struct bnx2x_phy *phy, 4491 struct link_params *params, 4492 struct link_vars *vars) 4493 { 4494 struct bnx2x *bp = params->bp; 4495 u32 serdes_net_if; 4496 u8 fiber_mode; 4497 u16 lane = bnx2x_get_warpcore_lane(phy, params); 4498 serdes_net_if = (REG_RD(bp, params->shmem_base + 4499 offsetof(struct shmem_region, dev_info. 4500 port_hw_config[params->port].default_cfg)) & 4501 PORT_HW_CFG_NET_SERDES_IF_MASK); 4502 DP(NETIF_MSG_LINK, "Begin Warpcore init, link_speed %d, " 4503 "serdes_net_if = 0x%x\n", 4504 vars->line_speed, serdes_net_if); 4505 bnx2x_set_aer_mmd(params, phy); 4506 bnx2x_warpcore_reset_lane(bp, phy, 1); 4507 vars->phy_flags |= PHY_XGXS_FLAG; 4508 if ((serdes_net_if == PORT_HW_CFG_NET_SERDES_IF_SGMII) || 4509 (phy->req_line_speed && 4510 ((phy->req_line_speed == SPEED_100) || 4511 (phy->req_line_speed == SPEED_10)))) { 4512 vars->phy_flags |= PHY_SGMII_FLAG; 4513 DP(NETIF_MSG_LINK, "Setting SGMII mode\n"); 4514 bnx2x_warpcore_clear_regs(phy, params, lane); 4515 bnx2x_warpcore_set_sgmii_speed(phy, params, 0, 1); 4516 } else { 4517 switch (serdes_net_if) { 4518 case PORT_HW_CFG_NET_SERDES_IF_KR: 4519 /* Enable KR Auto Neg */ 4520 if (params->loopback_mode != LOOPBACK_EXT) 4521 bnx2x_warpcore_enable_AN_KR(phy, params, vars); 4522 else { 4523 DP(NETIF_MSG_LINK, "Setting KR 10G-Force\n"); 4524 bnx2x_warpcore_set_10G_KR(phy, params, vars); 4525 } 4526 break; 4527 4528 case PORT_HW_CFG_NET_SERDES_IF_XFI: 4529 bnx2x_warpcore_clear_regs(phy, params, lane); 4530 if (vars->line_speed == SPEED_10000) { 4531 DP(NETIF_MSG_LINK, "Setting 10G XFI\n"); 4532 bnx2x_warpcore_set_10G_XFI(phy, params, 1); 4533 } else { 4534 if (SINGLE_MEDIA_DIRECT(params)) { 4535 DP(NETIF_MSG_LINK, "1G Fiber\n"); 4536 fiber_mode = 1; 4537 } else { 4538 DP(NETIF_MSG_LINK, "10/100/1G SGMII\n"); 4539 fiber_mode = 0; 4540 } 4541 bnx2x_warpcore_set_sgmii_speed(phy, 4542 params, 4543 fiber_mode, 4544 0); 4545 } 4546 4547 break; 4548 4549 case PORT_HW_CFG_NET_SERDES_IF_SFI: 4550 /* Issue Module detection if module is plugged, or 4551 * enabled transmitter to avoid current leakage in case 4552 * no module is connected 4553 */ 4554 if ((params->loopback_mode == LOOPBACK_NONE) || 4555 (params->loopback_mode == LOOPBACK_EXT)) { 4556 if (bnx2x_is_sfp_module_plugged(phy, params)) 4557 bnx2x_sfp_module_detection(phy, params); 4558 else 4559 bnx2x_sfp_e3_set_transmitter(params, 4560 phy, 1); 4561 } 4562 4563 bnx2x_warpcore_config_sfi(phy, params); 4564 break; 4565 4566 case PORT_HW_CFG_NET_SERDES_IF_DXGXS: 4567 if (vars->line_speed != SPEED_20000) { 4568 DP(NETIF_MSG_LINK, "Speed not supported yet\n"); 4569 return; 4570 } 4571 DP(NETIF_MSG_LINK, "Setting 20G DXGXS\n"); 4572 bnx2x_warpcore_set_20G_DXGXS(bp, phy, lane); 4573 /* Issue Module detection */ 4574 4575 bnx2x_sfp_module_detection(phy, params); 4576 break; 4577 case PORT_HW_CFG_NET_SERDES_IF_KR2: 4578 if (!params->loopback_mode) { 4579 bnx2x_warpcore_enable_AN_KR(phy, params, vars); 4580 } else { 4581 DP(NETIF_MSG_LINK, "Setting KR 20G-Force\n"); 4582 bnx2x_warpcore_set_20G_force_KR2(phy, params); 4583 } 4584 break; 4585 default: 4586 DP(NETIF_MSG_LINK, 4587 "Unsupported Serdes Net Interface 0x%x\n", 4588 serdes_net_if); 4589 return; 4590 } 4591 } 4592 4593 /* Take lane out of reset after configuration is finished */ 4594 bnx2x_warpcore_reset_lane(bp, phy, 0); 4595 DP(NETIF_MSG_LINK, "Exit config init\n"); 4596 } 4597 4598 static void bnx2x_warpcore_link_reset(struct bnx2x_phy *phy, 4599 struct link_params *params) 4600 { 4601 struct bnx2x *bp = params->bp; 4602 u16 val16, lane; 4603 bnx2x_sfp_e3_set_transmitter(params, phy, 0); 4604 bnx2x_set_mdio_emac_per_phy(bp, params); 4605 bnx2x_set_aer_mmd(params, phy); 4606 /* Global register */ 4607 bnx2x_warpcore_reset_lane(bp, phy, 1); 4608 4609 /* Clear loopback settings (if any) */ 4610 /* 10G & 20G */ 4611 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, 4612 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0xBFFF); 4613 4614 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, 4615 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0xfffe); 4616 4617 /* Update those 1-copy registers */ 4618 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, 4619 MDIO_AER_BLOCK_AER_REG, 0); 4620 /* Enable 1G MDIO (1-copy) */ 4621 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, 4622 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, 4623 ~0x10); 4624 4625 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, 4626 MDIO_WC_REG_XGXSBLK1_LANECTRL2, 0xff00); 4627 lane = bnx2x_get_warpcore_lane(phy, params); 4628 /* Disable CL36 PCS Tx */ 4629 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 4630 MDIO_WC_REG_XGXSBLK1_LANECTRL0, &val16); 4631 val16 |= (0x11 << lane); 4632 if (phy->flags & FLAGS_WC_DUAL_MODE) 4633 val16 |= (0x22 << lane); 4634 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4635 MDIO_WC_REG_XGXSBLK1_LANECTRL0, val16); 4636 4637 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 4638 MDIO_WC_REG_XGXSBLK1_LANECTRL1, &val16); 4639 val16 &= ~(0x0303 << (lane << 1)); 4640 val16 |= (0x0101 << (lane << 1)); 4641 if (phy->flags & FLAGS_WC_DUAL_MODE) { 4642 val16 &= ~(0x0c0c << (lane << 1)); 4643 val16 |= (0x0404 << (lane << 1)); 4644 } 4645 4646 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4647 MDIO_WC_REG_XGXSBLK1_LANECTRL1, val16); 4648 /* Restore AER */ 4649 bnx2x_set_aer_mmd(params, phy); 4650 4651 } 4652 4653 static void bnx2x_set_warpcore_loopback(struct bnx2x_phy *phy, 4654 struct link_params *params) 4655 { 4656 struct bnx2x *bp = params->bp; 4657 u16 val16; 4658 u32 lane; 4659 DP(NETIF_MSG_LINK, "Setting Warpcore loopback type %x, speed %d\n", 4660 params->loopback_mode, phy->req_line_speed); 4661 4662 if (phy->req_line_speed < SPEED_10000 || 4663 phy->supported & SUPPORTED_20000baseKR2_Full) { 4664 /* 10/100/1000/20G-KR2 */ 4665 4666 /* Update those 1-copy registers */ 4667 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, 4668 MDIO_AER_BLOCK_AER_REG, 0); 4669 /* Enable 1G MDIO (1-copy) */ 4670 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 4671 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, 4672 0x10); 4673 /* Set 1G loopback based on lane (1-copy) */ 4674 lane = bnx2x_get_warpcore_lane(phy, params); 4675 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 4676 MDIO_WC_REG_XGXSBLK1_LANECTRL2, &val16); 4677 val16 |= (1<<lane); 4678 if (phy->flags & FLAGS_WC_DUAL_MODE) 4679 val16 |= (2<<lane); 4680 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4681 MDIO_WC_REG_XGXSBLK1_LANECTRL2, 4682 val16); 4683 4684 /* Switch back to 4-copy registers */ 4685 bnx2x_set_aer_mmd(params, phy); 4686 } else { 4687 /* 10G / 20G-DXGXS */ 4688 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 4689 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 4690 0x4000); 4691 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 4692 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1); 4693 } 4694 } 4695 4696 4697 4698 static void bnx2x_sync_link(struct link_params *params, 4699 struct link_vars *vars) 4700 { 4701 struct bnx2x *bp = params->bp; 4702 u8 link_10g_plus; 4703 if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG) 4704 vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG; 4705 vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP); 4706 if (vars->link_up) { 4707 DP(NETIF_MSG_LINK, "phy link up\n"); 4708 4709 vars->phy_link_up = 1; 4710 vars->duplex = DUPLEX_FULL; 4711 switch (vars->link_status & 4712 LINK_STATUS_SPEED_AND_DUPLEX_MASK) { 4713 case LINK_10THD: 4714 vars->duplex = DUPLEX_HALF; 4715 /* Fall thru */ 4716 case LINK_10TFD: 4717 vars->line_speed = SPEED_10; 4718 break; 4719 4720 case LINK_100TXHD: 4721 vars->duplex = DUPLEX_HALF; 4722 /* Fall thru */ 4723 case LINK_100T4: 4724 case LINK_100TXFD: 4725 vars->line_speed = SPEED_100; 4726 break; 4727 4728 case LINK_1000THD: 4729 vars->duplex = DUPLEX_HALF; 4730 /* Fall thru */ 4731 case LINK_1000TFD: 4732 vars->line_speed = SPEED_1000; 4733 break; 4734 4735 case LINK_2500THD: 4736 vars->duplex = DUPLEX_HALF; 4737 /* Fall thru */ 4738 case LINK_2500TFD: 4739 vars->line_speed = SPEED_2500; 4740 break; 4741 4742 case LINK_10GTFD: 4743 vars->line_speed = SPEED_10000; 4744 break; 4745 case LINK_20GTFD: 4746 vars->line_speed = SPEED_20000; 4747 break; 4748 default: 4749 break; 4750 } 4751 vars->flow_ctrl = 0; 4752 if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED) 4753 vars->flow_ctrl |= BNX2X_FLOW_CTRL_TX; 4754 4755 if (vars->link_status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED) 4756 vars->flow_ctrl |= BNX2X_FLOW_CTRL_RX; 4757 4758 if (!vars->flow_ctrl) 4759 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; 4760 4761 if (vars->line_speed && 4762 ((vars->line_speed == SPEED_10) || 4763 (vars->line_speed == SPEED_100))) { 4764 vars->phy_flags |= PHY_SGMII_FLAG; 4765 } else { 4766 vars->phy_flags &= ~PHY_SGMII_FLAG; 4767 } 4768 if (vars->line_speed && 4769 USES_WARPCORE(bp) && 4770 (vars->line_speed == SPEED_1000)) 4771 vars->phy_flags |= PHY_SGMII_FLAG; 4772 /* Anything 10 and over uses the bmac */ 4773 link_10g_plus = (vars->line_speed >= SPEED_10000); 4774 4775 if (link_10g_plus) { 4776 if (USES_WARPCORE(bp)) 4777 vars->mac_type = MAC_TYPE_XMAC; 4778 else 4779 vars->mac_type = MAC_TYPE_BMAC; 4780 } else { 4781 if (USES_WARPCORE(bp)) 4782 vars->mac_type = MAC_TYPE_UMAC; 4783 else 4784 vars->mac_type = MAC_TYPE_EMAC; 4785 } 4786 } else { /* Link down */ 4787 DP(NETIF_MSG_LINK, "phy link down\n"); 4788 4789 vars->phy_link_up = 0; 4790 4791 vars->line_speed = 0; 4792 vars->duplex = DUPLEX_FULL; 4793 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; 4794 4795 /* Indicate no mac active */ 4796 vars->mac_type = MAC_TYPE_NONE; 4797 if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG) 4798 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG; 4799 if (vars->link_status & LINK_STATUS_SFP_TX_FAULT) 4800 vars->phy_flags |= PHY_SFP_TX_FAULT_FLAG; 4801 } 4802 } 4803 4804 void bnx2x_link_status_update(struct link_params *params, 4805 struct link_vars *vars) 4806 { 4807 struct bnx2x *bp = params->bp; 4808 u8 port = params->port; 4809 u32 sync_offset, media_types; 4810 /* Update PHY configuration */ 4811 set_phy_vars(params, vars); 4812 4813 vars->link_status = REG_RD(bp, params->shmem_base + 4814 offsetof(struct shmem_region, 4815 port_mb[port].link_status)); 4816 4817 /* Force link UP in non LOOPBACK_EXT loopback mode(s) */ 4818 if (params->loopback_mode != LOOPBACK_NONE && 4819 params->loopback_mode != LOOPBACK_EXT) 4820 vars->link_status |= LINK_STATUS_LINK_UP; 4821 4822 if (bnx2x_eee_has_cap(params)) 4823 vars->eee_status = REG_RD(bp, params->shmem2_base + 4824 offsetof(struct shmem2_region, 4825 eee_status[params->port])); 4826 4827 vars->phy_flags = PHY_XGXS_FLAG; 4828 bnx2x_sync_link(params, vars); 4829 /* Sync media type */ 4830 sync_offset = params->shmem_base + 4831 offsetof(struct shmem_region, 4832 dev_info.port_hw_config[port].media_type); 4833 media_types = REG_RD(bp, sync_offset); 4834 4835 params->phy[INT_PHY].media_type = 4836 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) >> 4837 PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT; 4838 params->phy[EXT_PHY1].media_type = 4839 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK) >> 4840 PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT; 4841 params->phy[EXT_PHY2].media_type = 4842 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK) >> 4843 PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT; 4844 DP(NETIF_MSG_LINK, "media_types = 0x%x\n", media_types); 4845 4846 /* Sync AEU offset */ 4847 sync_offset = params->shmem_base + 4848 offsetof(struct shmem_region, 4849 dev_info.port_hw_config[port].aeu_int_mask); 4850 4851 vars->aeu_int_mask = REG_RD(bp, sync_offset); 4852 4853 /* Sync PFC status */ 4854 if (vars->link_status & LINK_STATUS_PFC_ENABLED) 4855 params->feature_config_flags |= 4856 FEATURE_CONFIG_PFC_ENABLED; 4857 else 4858 params->feature_config_flags &= 4859 ~FEATURE_CONFIG_PFC_ENABLED; 4860 4861 if (SHMEM2_HAS(bp, link_attr_sync)) 4862 params->link_attr_sync = SHMEM2_RD(bp, 4863 link_attr_sync[params->port]); 4864 4865 DP(NETIF_MSG_LINK, "link_status 0x%x phy_link_up %x int_mask 0x%x\n", 4866 vars->link_status, vars->phy_link_up, vars->aeu_int_mask); 4867 DP(NETIF_MSG_LINK, "line_speed %x duplex %x flow_ctrl 0x%x\n", 4868 vars->line_speed, vars->duplex, vars->flow_ctrl); 4869 } 4870 4871 static void bnx2x_set_master_ln(struct link_params *params, 4872 struct bnx2x_phy *phy) 4873 { 4874 struct bnx2x *bp = params->bp; 4875 u16 new_master_ln, ser_lane; 4876 ser_lane = ((params->lane_config & 4877 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >> 4878 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT); 4879 4880 /* Set the master_ln for AN */ 4881 CL22_RD_OVER_CL45(bp, phy, 4882 MDIO_REG_BANK_XGXS_BLOCK2, 4883 MDIO_XGXS_BLOCK2_TEST_MODE_LANE, 4884 &new_master_ln); 4885 4886 CL22_WR_OVER_CL45(bp, phy, 4887 MDIO_REG_BANK_XGXS_BLOCK2 , 4888 MDIO_XGXS_BLOCK2_TEST_MODE_LANE, 4889 (new_master_ln | ser_lane)); 4890 } 4891 4892 static int bnx2x_reset_unicore(struct link_params *params, 4893 struct bnx2x_phy *phy, 4894 u8 set_serdes) 4895 { 4896 struct bnx2x *bp = params->bp; 4897 u16 mii_control; 4898 u16 i; 4899 CL22_RD_OVER_CL45(bp, phy, 4900 MDIO_REG_BANK_COMBO_IEEE0, 4901 MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control); 4902 4903 /* Reset the unicore */ 4904 CL22_WR_OVER_CL45(bp, phy, 4905 MDIO_REG_BANK_COMBO_IEEE0, 4906 MDIO_COMBO_IEEE0_MII_CONTROL, 4907 (mii_control | 4908 MDIO_COMBO_IEEO_MII_CONTROL_RESET)); 4909 if (set_serdes) 4910 bnx2x_set_serdes_access(bp, params->port); 4911 4912 /* Wait for the reset to self clear */ 4913 for (i = 0; i < MDIO_ACCESS_TIMEOUT; i++) { 4914 udelay(5); 4915 4916 /* The reset erased the previous bank value */ 4917 CL22_RD_OVER_CL45(bp, phy, 4918 MDIO_REG_BANK_COMBO_IEEE0, 4919 MDIO_COMBO_IEEE0_MII_CONTROL, 4920 &mii_control); 4921 4922 if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) { 4923 udelay(5); 4924 return 0; 4925 } 4926 } 4927 4928 netdev_err(bp->dev, "Warning: PHY was not initialized," 4929 " Port %d\n", 4930 params->port); 4931 DP(NETIF_MSG_LINK, "BUG! XGXS is still in reset!\n"); 4932 return -EINVAL; 4933 4934 } 4935 4936 static void bnx2x_set_swap_lanes(struct link_params *params, 4937 struct bnx2x_phy *phy) 4938 { 4939 struct bnx2x *bp = params->bp; 4940 /* Each two bits represents a lane number: 4941 * No swap is 0123 => 0x1b no need to enable the swap 4942 */ 4943 u16 rx_lane_swap, tx_lane_swap; 4944 4945 rx_lane_swap = ((params->lane_config & 4946 PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >> 4947 PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT); 4948 tx_lane_swap = ((params->lane_config & 4949 PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >> 4950 PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT); 4951 4952 if (rx_lane_swap != 0x1b) { 4953 CL22_WR_OVER_CL45(bp, phy, 4954 MDIO_REG_BANK_XGXS_BLOCK2, 4955 MDIO_XGXS_BLOCK2_RX_LN_SWAP, 4956 (rx_lane_swap | 4957 MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE | 4958 MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE)); 4959 } else { 4960 CL22_WR_OVER_CL45(bp, phy, 4961 MDIO_REG_BANK_XGXS_BLOCK2, 4962 MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0); 4963 } 4964 4965 if (tx_lane_swap != 0x1b) { 4966 CL22_WR_OVER_CL45(bp, phy, 4967 MDIO_REG_BANK_XGXS_BLOCK2, 4968 MDIO_XGXS_BLOCK2_TX_LN_SWAP, 4969 (tx_lane_swap | 4970 MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE)); 4971 } else { 4972 CL22_WR_OVER_CL45(bp, phy, 4973 MDIO_REG_BANK_XGXS_BLOCK2, 4974 MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0); 4975 } 4976 } 4977 4978 static void bnx2x_set_parallel_detection(struct bnx2x_phy *phy, 4979 struct link_params *params) 4980 { 4981 struct bnx2x *bp = params->bp; 4982 u16 control2; 4983 CL22_RD_OVER_CL45(bp, phy, 4984 MDIO_REG_BANK_SERDES_DIGITAL, 4985 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2, 4986 &control2); 4987 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) 4988 control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN; 4989 else 4990 control2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN; 4991 DP(NETIF_MSG_LINK, "phy->speed_cap_mask = 0x%x, control2 = 0x%x\n", 4992 phy->speed_cap_mask, control2); 4993 CL22_WR_OVER_CL45(bp, phy, 4994 MDIO_REG_BANK_SERDES_DIGITAL, 4995 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2, 4996 control2); 4997 4998 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) && 4999 (phy->speed_cap_mask & 5000 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) { 5001 DP(NETIF_MSG_LINK, "XGXS\n"); 5002 5003 CL22_WR_OVER_CL45(bp, phy, 5004 MDIO_REG_BANK_10G_PARALLEL_DETECT, 5005 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK, 5006 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT); 5007 5008 CL22_RD_OVER_CL45(bp, phy, 5009 MDIO_REG_BANK_10G_PARALLEL_DETECT, 5010 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL, 5011 &control2); 5012 5013 5014 control2 |= 5015 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN; 5016 5017 CL22_WR_OVER_CL45(bp, phy, 5018 MDIO_REG_BANK_10G_PARALLEL_DETECT, 5019 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL, 5020 control2); 5021 5022 /* Disable parallel detection of HiG */ 5023 CL22_WR_OVER_CL45(bp, phy, 5024 MDIO_REG_BANK_XGXS_BLOCK2, 5025 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G, 5026 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS | 5027 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS); 5028 } 5029 } 5030 5031 static void bnx2x_set_autoneg(struct bnx2x_phy *phy, 5032 struct link_params *params, 5033 struct link_vars *vars, 5034 u8 enable_cl73) 5035 { 5036 struct bnx2x *bp = params->bp; 5037 u16 reg_val; 5038 5039 /* CL37 Autoneg */ 5040 CL22_RD_OVER_CL45(bp, phy, 5041 MDIO_REG_BANK_COMBO_IEEE0, 5042 MDIO_COMBO_IEEE0_MII_CONTROL, ®_val); 5043 5044 /* CL37 Autoneg Enabled */ 5045 if (vars->line_speed == SPEED_AUTO_NEG) 5046 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN; 5047 else /* CL37 Autoneg Disabled */ 5048 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN | 5049 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN); 5050 5051 CL22_WR_OVER_CL45(bp, phy, 5052 MDIO_REG_BANK_COMBO_IEEE0, 5053 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val); 5054 5055 /* Enable/Disable Autodetection */ 5056 5057 CL22_RD_OVER_CL45(bp, phy, 5058 MDIO_REG_BANK_SERDES_DIGITAL, 5059 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, ®_val); 5060 reg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN | 5061 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT); 5062 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE; 5063 if (vars->line_speed == SPEED_AUTO_NEG) 5064 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET; 5065 else 5066 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET; 5067 5068 CL22_WR_OVER_CL45(bp, phy, 5069 MDIO_REG_BANK_SERDES_DIGITAL, 5070 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val); 5071 5072 /* Enable TetonII and BAM autoneg */ 5073 CL22_RD_OVER_CL45(bp, phy, 5074 MDIO_REG_BANK_BAM_NEXT_PAGE, 5075 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL, 5076 ®_val); 5077 if (vars->line_speed == SPEED_AUTO_NEG) { 5078 /* Enable BAM aneg Mode and TetonII aneg Mode */ 5079 reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE | 5080 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN); 5081 } else { 5082 /* TetonII and BAM Autoneg Disabled */ 5083 reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE | 5084 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN); 5085 } 5086 CL22_WR_OVER_CL45(bp, phy, 5087 MDIO_REG_BANK_BAM_NEXT_PAGE, 5088 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL, 5089 reg_val); 5090 5091 if (enable_cl73) { 5092 /* Enable Cl73 FSM status bits */ 5093 CL22_WR_OVER_CL45(bp, phy, 5094 MDIO_REG_BANK_CL73_USERB0, 5095 MDIO_CL73_USERB0_CL73_UCTRL, 5096 0xe); 5097 5098 /* Enable BAM Station Manager*/ 5099 CL22_WR_OVER_CL45(bp, phy, 5100 MDIO_REG_BANK_CL73_USERB0, 5101 MDIO_CL73_USERB0_CL73_BAM_CTRL1, 5102 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN | 5103 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN | 5104 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN); 5105 5106 /* Advertise CL73 link speeds */ 5107 CL22_RD_OVER_CL45(bp, phy, 5108 MDIO_REG_BANK_CL73_IEEEB1, 5109 MDIO_CL73_IEEEB1_AN_ADV2, 5110 ®_val); 5111 if (phy->speed_cap_mask & 5112 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) 5113 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4; 5114 if (phy->speed_cap_mask & 5115 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) 5116 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX; 5117 5118 CL22_WR_OVER_CL45(bp, phy, 5119 MDIO_REG_BANK_CL73_IEEEB1, 5120 MDIO_CL73_IEEEB1_AN_ADV2, 5121 reg_val); 5122 5123 /* CL73 Autoneg Enabled */ 5124 reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN; 5125 5126 } else /* CL73 Autoneg Disabled */ 5127 reg_val = 0; 5128 5129 CL22_WR_OVER_CL45(bp, phy, 5130 MDIO_REG_BANK_CL73_IEEEB0, 5131 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val); 5132 } 5133 5134 /* Program SerDes, forced speed */ 5135 static void bnx2x_program_serdes(struct bnx2x_phy *phy, 5136 struct link_params *params, 5137 struct link_vars *vars) 5138 { 5139 struct bnx2x *bp = params->bp; 5140 u16 reg_val; 5141 5142 /* Program duplex, disable autoneg and sgmii*/ 5143 CL22_RD_OVER_CL45(bp, phy, 5144 MDIO_REG_BANK_COMBO_IEEE0, 5145 MDIO_COMBO_IEEE0_MII_CONTROL, ®_val); 5146 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX | 5147 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN | 5148 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK); 5149 if (phy->req_duplex == DUPLEX_FULL) 5150 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX; 5151 CL22_WR_OVER_CL45(bp, phy, 5152 MDIO_REG_BANK_COMBO_IEEE0, 5153 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val); 5154 5155 /* Program speed 5156 * - needed only if the speed is greater than 1G (2.5G or 10G) 5157 */ 5158 CL22_RD_OVER_CL45(bp, phy, 5159 MDIO_REG_BANK_SERDES_DIGITAL, 5160 MDIO_SERDES_DIGITAL_MISC1, ®_val); 5161 /* Clearing the speed value before setting the right speed */ 5162 DP(NETIF_MSG_LINK, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val); 5163 5164 reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK | 5165 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL); 5166 5167 if (!((vars->line_speed == SPEED_1000) || 5168 (vars->line_speed == SPEED_100) || 5169 (vars->line_speed == SPEED_10))) { 5170 5171 reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M | 5172 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL); 5173 if (vars->line_speed == SPEED_10000) 5174 reg_val |= 5175 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4; 5176 } 5177 5178 CL22_WR_OVER_CL45(bp, phy, 5179 MDIO_REG_BANK_SERDES_DIGITAL, 5180 MDIO_SERDES_DIGITAL_MISC1, reg_val); 5181 5182 } 5183 5184 static void bnx2x_set_brcm_cl37_advertisement(struct bnx2x_phy *phy, 5185 struct link_params *params) 5186 { 5187 struct bnx2x *bp = params->bp; 5188 u16 val = 0; 5189 5190 /* Set extended capabilities */ 5191 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) 5192 val |= MDIO_OVER_1G_UP1_2_5G; 5193 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) 5194 val |= MDIO_OVER_1G_UP1_10G; 5195 CL22_WR_OVER_CL45(bp, phy, 5196 MDIO_REG_BANK_OVER_1G, 5197 MDIO_OVER_1G_UP1, val); 5198 5199 CL22_WR_OVER_CL45(bp, phy, 5200 MDIO_REG_BANK_OVER_1G, 5201 MDIO_OVER_1G_UP3, 0x400); 5202 } 5203 5204 static void bnx2x_set_ieee_aneg_advertisement(struct bnx2x_phy *phy, 5205 struct link_params *params, 5206 u16 ieee_fc) 5207 { 5208 struct bnx2x *bp = params->bp; 5209 u16 val; 5210 /* For AN, we are always publishing full duplex */ 5211 5212 CL22_WR_OVER_CL45(bp, phy, 5213 MDIO_REG_BANK_COMBO_IEEE0, 5214 MDIO_COMBO_IEEE0_AUTO_NEG_ADV, ieee_fc); 5215 CL22_RD_OVER_CL45(bp, phy, 5216 MDIO_REG_BANK_CL73_IEEEB1, 5217 MDIO_CL73_IEEEB1_AN_ADV1, &val); 5218 val &= ~MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH; 5219 val |= ((ieee_fc<<3) & MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK); 5220 CL22_WR_OVER_CL45(bp, phy, 5221 MDIO_REG_BANK_CL73_IEEEB1, 5222 MDIO_CL73_IEEEB1_AN_ADV1, val); 5223 } 5224 5225 static void bnx2x_restart_autoneg(struct bnx2x_phy *phy, 5226 struct link_params *params, 5227 u8 enable_cl73) 5228 { 5229 struct bnx2x *bp = params->bp; 5230 u16 mii_control; 5231 5232 DP(NETIF_MSG_LINK, "bnx2x_restart_autoneg\n"); 5233 /* Enable and restart BAM/CL37 aneg */ 5234 5235 if (enable_cl73) { 5236 CL22_RD_OVER_CL45(bp, phy, 5237 MDIO_REG_BANK_CL73_IEEEB0, 5238 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, 5239 &mii_control); 5240 5241 CL22_WR_OVER_CL45(bp, phy, 5242 MDIO_REG_BANK_CL73_IEEEB0, 5243 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, 5244 (mii_control | 5245 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN | 5246 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN)); 5247 } else { 5248 5249 CL22_RD_OVER_CL45(bp, phy, 5250 MDIO_REG_BANK_COMBO_IEEE0, 5251 MDIO_COMBO_IEEE0_MII_CONTROL, 5252 &mii_control); 5253 DP(NETIF_MSG_LINK, 5254 "bnx2x_restart_autoneg mii_control before = 0x%x\n", 5255 mii_control); 5256 CL22_WR_OVER_CL45(bp, phy, 5257 MDIO_REG_BANK_COMBO_IEEE0, 5258 MDIO_COMBO_IEEE0_MII_CONTROL, 5259 (mii_control | 5260 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN | 5261 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN)); 5262 } 5263 } 5264 5265 static void bnx2x_initialize_sgmii_process(struct bnx2x_phy *phy, 5266 struct link_params *params, 5267 struct link_vars *vars) 5268 { 5269 struct bnx2x *bp = params->bp; 5270 u16 control1; 5271 5272 /* In SGMII mode, the unicore is always slave */ 5273 5274 CL22_RD_OVER_CL45(bp, phy, 5275 MDIO_REG_BANK_SERDES_DIGITAL, 5276 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, 5277 &control1); 5278 control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT; 5279 /* Set sgmii mode (and not fiber) */ 5280 control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE | 5281 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET | 5282 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE); 5283 CL22_WR_OVER_CL45(bp, phy, 5284 MDIO_REG_BANK_SERDES_DIGITAL, 5285 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, 5286 control1); 5287 5288 /* If forced speed */ 5289 if (!(vars->line_speed == SPEED_AUTO_NEG)) { 5290 /* Set speed, disable autoneg */ 5291 u16 mii_control; 5292 5293 CL22_RD_OVER_CL45(bp, phy, 5294 MDIO_REG_BANK_COMBO_IEEE0, 5295 MDIO_COMBO_IEEE0_MII_CONTROL, 5296 &mii_control); 5297 mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN | 5298 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK| 5299 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX); 5300 5301 switch (vars->line_speed) { 5302 case SPEED_100: 5303 mii_control |= 5304 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100; 5305 break; 5306 case SPEED_1000: 5307 mii_control |= 5308 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000; 5309 break; 5310 case SPEED_10: 5311 /* There is nothing to set for 10M */ 5312 break; 5313 default: 5314 /* Invalid speed for SGMII */ 5315 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n", 5316 vars->line_speed); 5317 break; 5318 } 5319 5320 /* Setting the full duplex */ 5321 if (phy->req_duplex == DUPLEX_FULL) 5322 mii_control |= 5323 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX; 5324 CL22_WR_OVER_CL45(bp, phy, 5325 MDIO_REG_BANK_COMBO_IEEE0, 5326 MDIO_COMBO_IEEE0_MII_CONTROL, 5327 mii_control); 5328 5329 } else { /* AN mode */ 5330 /* Enable and restart AN */ 5331 bnx2x_restart_autoneg(phy, params, 0); 5332 } 5333 } 5334 5335 /* Link management 5336 */ 5337 static int bnx2x_direct_parallel_detect_used(struct bnx2x_phy *phy, 5338 struct link_params *params) 5339 { 5340 struct bnx2x *bp = params->bp; 5341 u16 pd_10g, status2_1000x; 5342 if (phy->req_line_speed != SPEED_AUTO_NEG) 5343 return 0; 5344 CL22_RD_OVER_CL45(bp, phy, 5345 MDIO_REG_BANK_SERDES_DIGITAL, 5346 MDIO_SERDES_DIGITAL_A_1000X_STATUS2, 5347 &status2_1000x); 5348 CL22_RD_OVER_CL45(bp, phy, 5349 MDIO_REG_BANK_SERDES_DIGITAL, 5350 MDIO_SERDES_DIGITAL_A_1000X_STATUS2, 5351 &status2_1000x); 5352 if (status2_1000x & MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED) { 5353 DP(NETIF_MSG_LINK, "1G parallel detect link on port %d\n", 5354 params->port); 5355 return 1; 5356 } 5357 5358 CL22_RD_OVER_CL45(bp, phy, 5359 MDIO_REG_BANK_10G_PARALLEL_DETECT, 5360 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS, 5361 &pd_10g); 5362 5363 if (pd_10g & MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK) { 5364 DP(NETIF_MSG_LINK, "10G parallel detect link on port %d\n", 5365 params->port); 5366 return 1; 5367 } 5368 return 0; 5369 } 5370 5371 static void bnx2x_update_adv_fc(struct bnx2x_phy *phy, 5372 struct link_params *params, 5373 struct link_vars *vars, 5374 u32 gp_status) 5375 { 5376 u16 ld_pause; /* local driver */ 5377 u16 lp_pause; /* link partner */ 5378 u16 pause_result; 5379 struct bnx2x *bp = params->bp; 5380 if ((gp_status & 5381 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | 5382 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) == 5383 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | 5384 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) { 5385 5386 CL22_RD_OVER_CL45(bp, phy, 5387 MDIO_REG_BANK_CL73_IEEEB1, 5388 MDIO_CL73_IEEEB1_AN_ADV1, 5389 &ld_pause); 5390 CL22_RD_OVER_CL45(bp, phy, 5391 MDIO_REG_BANK_CL73_IEEEB1, 5392 MDIO_CL73_IEEEB1_AN_LP_ADV1, 5393 &lp_pause); 5394 pause_result = (ld_pause & 5395 MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK) >> 8; 5396 pause_result |= (lp_pause & 5397 MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK) >> 10; 5398 DP(NETIF_MSG_LINK, "pause_result CL73 0x%x\n", pause_result); 5399 } else { 5400 CL22_RD_OVER_CL45(bp, phy, 5401 MDIO_REG_BANK_COMBO_IEEE0, 5402 MDIO_COMBO_IEEE0_AUTO_NEG_ADV, 5403 &ld_pause); 5404 CL22_RD_OVER_CL45(bp, phy, 5405 MDIO_REG_BANK_COMBO_IEEE0, 5406 MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1, 5407 &lp_pause); 5408 pause_result = (ld_pause & 5409 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>5; 5410 pause_result |= (lp_pause & 5411 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7; 5412 DP(NETIF_MSG_LINK, "pause_result CL37 0x%x\n", pause_result); 5413 } 5414 bnx2x_pause_resolve(phy, params, vars, pause_result); 5415 5416 } 5417 5418 static void bnx2x_flow_ctrl_resolve(struct bnx2x_phy *phy, 5419 struct link_params *params, 5420 struct link_vars *vars, 5421 u32 gp_status) 5422 { 5423 struct bnx2x *bp = params->bp; 5424 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; 5425 5426 /* Resolve from gp_status in case of AN complete and not sgmii */ 5427 if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO) { 5428 /* Update the advertised flow-controled of LD/LP in AN */ 5429 if (phy->req_line_speed == SPEED_AUTO_NEG) 5430 bnx2x_update_adv_fc(phy, params, vars, gp_status); 5431 /* But set the flow-control result as the requested one */ 5432 vars->flow_ctrl = phy->req_flow_ctrl; 5433 } else if (phy->req_line_speed != SPEED_AUTO_NEG) 5434 vars->flow_ctrl = params->req_fc_auto_adv; 5435 else if ((gp_status & MDIO_AN_CL73_OR_37_COMPLETE) && 5436 (!(vars->phy_flags & PHY_SGMII_FLAG))) { 5437 if (bnx2x_direct_parallel_detect_used(phy, params)) { 5438 vars->flow_ctrl = params->req_fc_auto_adv; 5439 return; 5440 } 5441 bnx2x_update_adv_fc(phy, params, vars, gp_status); 5442 } 5443 DP(NETIF_MSG_LINK, "flow_ctrl 0x%x\n", vars->flow_ctrl); 5444 } 5445 5446 static void bnx2x_check_fallback_to_cl37(struct bnx2x_phy *phy, 5447 struct link_params *params) 5448 { 5449 struct bnx2x *bp = params->bp; 5450 u16 rx_status, ustat_val, cl37_fsm_received; 5451 DP(NETIF_MSG_LINK, "bnx2x_check_fallback_to_cl37\n"); 5452 /* Step 1: Make sure signal is detected */ 5453 CL22_RD_OVER_CL45(bp, phy, 5454 MDIO_REG_BANK_RX0, 5455 MDIO_RX0_RX_STATUS, 5456 &rx_status); 5457 if ((rx_status & MDIO_RX0_RX_STATUS_SIGDET) != 5458 (MDIO_RX0_RX_STATUS_SIGDET)) { 5459 DP(NETIF_MSG_LINK, "Signal is not detected. Restoring CL73." 5460 "rx_status(0x80b0) = 0x%x\n", rx_status); 5461 CL22_WR_OVER_CL45(bp, phy, 5462 MDIO_REG_BANK_CL73_IEEEB0, 5463 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, 5464 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN); 5465 return; 5466 } 5467 /* Step 2: Check CL73 state machine */ 5468 CL22_RD_OVER_CL45(bp, phy, 5469 MDIO_REG_BANK_CL73_USERB0, 5470 MDIO_CL73_USERB0_CL73_USTAT1, 5471 &ustat_val); 5472 if ((ustat_val & 5473 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK | 5474 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) != 5475 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK | 5476 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) { 5477 DP(NETIF_MSG_LINK, "CL73 state-machine is not stable. " 5478 "ustat_val(0x8371) = 0x%x\n", ustat_val); 5479 return; 5480 } 5481 /* Step 3: Check CL37 Message Pages received to indicate LP 5482 * supports only CL37 5483 */ 5484 CL22_RD_OVER_CL45(bp, phy, 5485 MDIO_REG_BANK_REMOTE_PHY, 5486 MDIO_REMOTE_PHY_MISC_RX_STATUS, 5487 &cl37_fsm_received); 5488 if ((cl37_fsm_received & 5489 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG | 5490 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) != 5491 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG | 5492 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) { 5493 DP(NETIF_MSG_LINK, "No CL37 FSM were received. " 5494 "misc_rx_status(0x8330) = 0x%x\n", 5495 cl37_fsm_received); 5496 return; 5497 } 5498 /* The combined cl37/cl73 fsm state information indicating that 5499 * we are connected to a device which does not support cl73, but 5500 * does support cl37 BAM. In this case we disable cl73 and 5501 * restart cl37 auto-neg 5502 */ 5503 5504 /* Disable CL73 */ 5505 CL22_WR_OVER_CL45(bp, phy, 5506 MDIO_REG_BANK_CL73_IEEEB0, 5507 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, 5508 0); 5509 /* Restart CL37 autoneg */ 5510 bnx2x_restart_autoneg(phy, params, 0); 5511 DP(NETIF_MSG_LINK, "Disabling CL73, and restarting CL37 autoneg\n"); 5512 } 5513 5514 static void bnx2x_xgxs_an_resolve(struct bnx2x_phy *phy, 5515 struct link_params *params, 5516 struct link_vars *vars, 5517 u32 gp_status) 5518 { 5519 if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE) 5520 vars->link_status |= 5521 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; 5522 5523 if (bnx2x_direct_parallel_detect_used(phy, params)) 5524 vars->link_status |= 5525 LINK_STATUS_PARALLEL_DETECTION_USED; 5526 } 5527 static int bnx2x_get_link_speed_duplex(struct bnx2x_phy *phy, 5528 struct link_params *params, 5529 struct link_vars *vars, 5530 u16 is_link_up, 5531 u16 speed_mask, 5532 u16 is_duplex) 5533 { 5534 struct bnx2x *bp = params->bp; 5535 if (phy->req_line_speed == SPEED_AUTO_NEG) 5536 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED; 5537 if (is_link_up) { 5538 DP(NETIF_MSG_LINK, "phy link up\n"); 5539 5540 vars->phy_link_up = 1; 5541 vars->link_status |= LINK_STATUS_LINK_UP; 5542 5543 switch (speed_mask) { 5544 case GP_STATUS_10M: 5545 vars->line_speed = SPEED_10; 5546 if (is_duplex == DUPLEX_FULL) 5547 vars->link_status |= LINK_10TFD; 5548 else 5549 vars->link_status |= LINK_10THD; 5550 break; 5551 5552 case GP_STATUS_100M: 5553 vars->line_speed = SPEED_100; 5554 if (is_duplex == DUPLEX_FULL) 5555 vars->link_status |= LINK_100TXFD; 5556 else 5557 vars->link_status |= LINK_100TXHD; 5558 break; 5559 5560 case GP_STATUS_1G: 5561 case GP_STATUS_1G_KX: 5562 vars->line_speed = SPEED_1000; 5563 if (is_duplex == DUPLEX_FULL) 5564 vars->link_status |= LINK_1000TFD; 5565 else 5566 vars->link_status |= LINK_1000THD; 5567 break; 5568 5569 case GP_STATUS_2_5G: 5570 vars->line_speed = SPEED_2500; 5571 if (is_duplex == DUPLEX_FULL) 5572 vars->link_status |= LINK_2500TFD; 5573 else 5574 vars->link_status |= LINK_2500THD; 5575 break; 5576 5577 case GP_STATUS_5G: 5578 case GP_STATUS_6G: 5579 DP(NETIF_MSG_LINK, 5580 "link speed unsupported gp_status 0x%x\n", 5581 speed_mask); 5582 return -EINVAL; 5583 5584 case GP_STATUS_10G_KX4: 5585 case GP_STATUS_10G_HIG: 5586 case GP_STATUS_10G_CX4: 5587 case GP_STATUS_10G_KR: 5588 case GP_STATUS_10G_SFI: 5589 case GP_STATUS_10G_XFI: 5590 vars->line_speed = SPEED_10000; 5591 vars->link_status |= LINK_10GTFD; 5592 break; 5593 case GP_STATUS_20G_DXGXS: 5594 case GP_STATUS_20G_KR2: 5595 vars->line_speed = SPEED_20000; 5596 vars->link_status |= LINK_20GTFD; 5597 break; 5598 default: 5599 DP(NETIF_MSG_LINK, 5600 "link speed unsupported gp_status 0x%x\n", 5601 speed_mask); 5602 return -EINVAL; 5603 } 5604 } else { /* link_down */ 5605 DP(NETIF_MSG_LINK, "phy link down\n"); 5606 5607 vars->phy_link_up = 0; 5608 5609 vars->duplex = DUPLEX_FULL; 5610 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; 5611 vars->mac_type = MAC_TYPE_NONE; 5612 } 5613 DP(NETIF_MSG_LINK, " phy_link_up %x line_speed %d\n", 5614 vars->phy_link_up, vars->line_speed); 5615 return 0; 5616 } 5617 5618 static int bnx2x_link_settings_status(struct bnx2x_phy *phy, 5619 struct link_params *params, 5620 struct link_vars *vars) 5621 { 5622 struct bnx2x *bp = params->bp; 5623 5624 u16 gp_status, duplex = DUPLEX_HALF, link_up = 0, speed_mask; 5625 int rc = 0; 5626 5627 /* Read gp_status */ 5628 CL22_RD_OVER_CL45(bp, phy, 5629 MDIO_REG_BANK_GP_STATUS, 5630 MDIO_GP_STATUS_TOP_AN_STATUS1, 5631 &gp_status); 5632 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS) 5633 duplex = DUPLEX_FULL; 5634 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) 5635 link_up = 1; 5636 speed_mask = gp_status & GP_STATUS_SPEED_MASK; 5637 DP(NETIF_MSG_LINK, "gp_status 0x%x, is_link_up %d, speed_mask 0x%x\n", 5638 gp_status, link_up, speed_mask); 5639 rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, speed_mask, 5640 duplex); 5641 if (rc == -EINVAL) 5642 return rc; 5643 5644 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) { 5645 if (SINGLE_MEDIA_DIRECT(params)) { 5646 vars->duplex = duplex; 5647 bnx2x_flow_ctrl_resolve(phy, params, vars, gp_status); 5648 if (phy->req_line_speed == SPEED_AUTO_NEG) 5649 bnx2x_xgxs_an_resolve(phy, params, vars, 5650 gp_status); 5651 } 5652 } else { /* Link_down */ 5653 if ((phy->req_line_speed == SPEED_AUTO_NEG) && 5654 SINGLE_MEDIA_DIRECT(params)) { 5655 /* Check signal is detected */ 5656 bnx2x_check_fallback_to_cl37(phy, params); 5657 } 5658 } 5659 5660 /* Read LP advertised speeds*/ 5661 if (SINGLE_MEDIA_DIRECT(params) && 5662 (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)) { 5663 u16 val; 5664 5665 CL22_RD_OVER_CL45(bp, phy, MDIO_REG_BANK_CL73_IEEEB1, 5666 MDIO_CL73_IEEEB1_AN_LP_ADV2, &val); 5667 5668 if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX) 5669 vars->link_status |= 5670 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; 5671 if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 | 5672 MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR)) 5673 vars->link_status |= 5674 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; 5675 5676 CL22_RD_OVER_CL45(bp, phy, MDIO_REG_BANK_OVER_1G, 5677 MDIO_OVER_1G_LP_UP1, &val); 5678 5679 if (val & MDIO_OVER_1G_UP1_2_5G) 5680 vars->link_status |= 5681 LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE; 5682 if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH)) 5683 vars->link_status |= 5684 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; 5685 } 5686 5687 DP(NETIF_MSG_LINK, "duplex %x flow_ctrl 0x%x link_status 0x%x\n", 5688 vars->duplex, vars->flow_ctrl, vars->link_status); 5689 return rc; 5690 } 5691 5692 static int bnx2x_warpcore_read_status(struct bnx2x_phy *phy, 5693 struct link_params *params, 5694 struct link_vars *vars) 5695 { 5696 struct bnx2x *bp = params->bp; 5697 u8 lane; 5698 u16 gp_status1, gp_speed, link_up, duplex = DUPLEX_FULL; 5699 int rc = 0; 5700 lane = bnx2x_get_warpcore_lane(phy, params); 5701 /* Read gp_status */ 5702 if ((params->loopback_mode) && 5703 (phy->flags & FLAGS_WC_DUAL_MODE)) { 5704 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 5705 MDIO_WC_REG_DIGITAL5_LINK_STATUS, &link_up); 5706 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 5707 MDIO_WC_REG_DIGITAL5_LINK_STATUS, &link_up); 5708 link_up &= 0x1; 5709 } else if ((phy->req_line_speed > SPEED_10000) && 5710 (phy->supported & SUPPORTED_20000baseMLD2_Full)) { 5711 u16 temp_link_up; 5712 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 5713 1, &temp_link_up); 5714 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 5715 1, &link_up); 5716 DP(NETIF_MSG_LINK, "PCS RX link status = 0x%x-->0x%x\n", 5717 temp_link_up, link_up); 5718 link_up &= (1<<2); 5719 if (link_up) 5720 bnx2x_ext_phy_resolve_fc(phy, params, vars); 5721 } else { 5722 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 5723 MDIO_WC_REG_GP2_STATUS_GP_2_1, 5724 &gp_status1); 5725 DP(NETIF_MSG_LINK, "0x81d1 = 0x%x\n", gp_status1); 5726 /* Check for either KR, 1G, or AN up. */ 5727 link_up = ((gp_status1 >> 8) | 5728 (gp_status1 >> 12) | 5729 (gp_status1)) & 5730 (1 << lane); 5731 if (phy->supported & SUPPORTED_20000baseKR2_Full) { 5732 u16 an_link; 5733 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, 5734 MDIO_AN_REG_STATUS, &an_link); 5735 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, 5736 MDIO_AN_REG_STATUS, &an_link); 5737 link_up |= (an_link & (1<<2)); 5738 } 5739 if (link_up && SINGLE_MEDIA_DIRECT(params)) { 5740 u16 pd, gp_status4; 5741 if (phy->req_line_speed == SPEED_AUTO_NEG) { 5742 /* Check Autoneg complete */ 5743 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 5744 MDIO_WC_REG_GP2_STATUS_GP_2_4, 5745 &gp_status4); 5746 if (gp_status4 & ((1<<12)<<lane)) 5747 vars->link_status |= 5748 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; 5749 5750 /* Check parallel detect used */ 5751 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 5752 MDIO_WC_REG_PAR_DET_10G_STATUS, 5753 &pd); 5754 if (pd & (1<<15)) 5755 vars->link_status |= 5756 LINK_STATUS_PARALLEL_DETECTION_USED; 5757 } 5758 bnx2x_ext_phy_resolve_fc(phy, params, vars); 5759 vars->duplex = duplex; 5760 } 5761 } 5762 5763 if ((vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) && 5764 SINGLE_MEDIA_DIRECT(params)) { 5765 u16 val; 5766 5767 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, 5768 MDIO_AN_REG_LP_AUTO_NEG2, &val); 5769 5770 if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX) 5771 vars->link_status |= 5772 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; 5773 if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 | 5774 MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR)) 5775 vars->link_status |= 5776 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; 5777 5778 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 5779 MDIO_WC_REG_DIGITAL3_LP_UP1, &val); 5780 5781 if (val & MDIO_OVER_1G_UP1_2_5G) 5782 vars->link_status |= 5783 LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE; 5784 if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH)) 5785 vars->link_status |= 5786 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; 5787 5788 } 5789 5790 5791 if (lane < 2) { 5792 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 5793 MDIO_WC_REG_GP2_STATUS_GP_2_2, &gp_speed); 5794 } else { 5795 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 5796 MDIO_WC_REG_GP2_STATUS_GP_2_3, &gp_speed); 5797 } 5798 DP(NETIF_MSG_LINK, "lane %d gp_speed 0x%x\n", lane, gp_speed); 5799 5800 if ((lane & 1) == 0) 5801 gp_speed <<= 8; 5802 gp_speed &= 0x3f00; 5803 link_up = !!link_up; 5804 5805 rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, gp_speed, 5806 duplex); 5807 5808 /* In case of KR link down, start up the recovering procedure */ 5809 if ((!link_up) && (phy->media_type == ETH_PHY_KR) && 5810 (!(phy->flags & FLAGS_WC_DUAL_MODE))) 5811 vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY; 5812 5813 DP(NETIF_MSG_LINK, "duplex %x flow_ctrl 0x%x link_status 0x%x\n", 5814 vars->duplex, vars->flow_ctrl, vars->link_status); 5815 return rc; 5816 } 5817 static void bnx2x_set_gmii_tx_driver(struct link_params *params) 5818 { 5819 struct bnx2x *bp = params->bp; 5820 struct bnx2x_phy *phy = ¶ms->phy[INT_PHY]; 5821 u16 lp_up2; 5822 u16 tx_driver; 5823 u16 bank; 5824 5825 /* Read precomp */ 5826 CL22_RD_OVER_CL45(bp, phy, 5827 MDIO_REG_BANK_OVER_1G, 5828 MDIO_OVER_1G_LP_UP2, &lp_up2); 5829 5830 /* Bits [10:7] at lp_up2, positioned at [15:12] */ 5831 lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >> 5832 MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) << 5833 MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT); 5834 5835 if (lp_up2 == 0) 5836 return; 5837 5838 for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3; 5839 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) { 5840 CL22_RD_OVER_CL45(bp, phy, 5841 bank, 5842 MDIO_TX0_TX_DRIVER, &tx_driver); 5843 5844 /* Replace tx_driver bits [15:12] */ 5845 if (lp_up2 != 5846 (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) { 5847 tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK; 5848 tx_driver |= lp_up2; 5849 CL22_WR_OVER_CL45(bp, phy, 5850 bank, 5851 MDIO_TX0_TX_DRIVER, tx_driver); 5852 } 5853 } 5854 } 5855 5856 static int bnx2x_emac_program(struct link_params *params, 5857 struct link_vars *vars) 5858 { 5859 struct bnx2x *bp = params->bp; 5860 u8 port = params->port; 5861 u16 mode = 0; 5862 5863 DP(NETIF_MSG_LINK, "setting link speed & duplex\n"); 5864 bnx2x_bits_dis(bp, GRCBASE_EMAC0 + port*0x400 + 5865 EMAC_REG_EMAC_MODE, 5866 (EMAC_MODE_25G_MODE | 5867 EMAC_MODE_PORT_MII_10M | 5868 EMAC_MODE_HALF_DUPLEX)); 5869 switch (vars->line_speed) { 5870 case SPEED_10: 5871 mode |= EMAC_MODE_PORT_MII_10M; 5872 break; 5873 5874 case SPEED_100: 5875 mode |= EMAC_MODE_PORT_MII; 5876 break; 5877 5878 case SPEED_1000: 5879 mode |= EMAC_MODE_PORT_GMII; 5880 break; 5881 5882 case SPEED_2500: 5883 mode |= (EMAC_MODE_25G_MODE | EMAC_MODE_PORT_GMII); 5884 break; 5885 5886 default: 5887 /* 10G not valid for EMAC */ 5888 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n", 5889 vars->line_speed); 5890 return -EINVAL; 5891 } 5892 5893 if (vars->duplex == DUPLEX_HALF) 5894 mode |= EMAC_MODE_HALF_DUPLEX; 5895 bnx2x_bits_en(bp, 5896 GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE, 5897 mode); 5898 5899 bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed); 5900 return 0; 5901 } 5902 5903 static void bnx2x_set_preemphasis(struct bnx2x_phy *phy, 5904 struct link_params *params) 5905 { 5906 5907 u16 bank, i = 0; 5908 struct bnx2x *bp = params->bp; 5909 5910 for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3; 5911 bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0), i++) { 5912 CL22_WR_OVER_CL45(bp, phy, 5913 bank, 5914 MDIO_RX0_RX_EQ_BOOST, 5915 phy->rx_preemphasis[i]); 5916 } 5917 5918 for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3; 5919 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) { 5920 CL22_WR_OVER_CL45(bp, phy, 5921 bank, 5922 MDIO_TX0_TX_DRIVER, 5923 phy->tx_preemphasis[i]); 5924 } 5925 } 5926 5927 static void bnx2x_xgxs_config_init(struct bnx2x_phy *phy, 5928 struct link_params *params, 5929 struct link_vars *vars) 5930 { 5931 struct bnx2x *bp = params->bp; 5932 u8 enable_cl73 = (SINGLE_MEDIA_DIRECT(params) || 5933 (params->loopback_mode == LOOPBACK_XGXS)); 5934 if (!(vars->phy_flags & PHY_SGMII_FLAG)) { 5935 if (SINGLE_MEDIA_DIRECT(params) && 5936 (params->feature_config_flags & 5937 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) 5938 bnx2x_set_preemphasis(phy, params); 5939 5940 /* Forced speed requested? */ 5941 if (vars->line_speed != SPEED_AUTO_NEG || 5942 (SINGLE_MEDIA_DIRECT(params) && 5943 params->loopback_mode == LOOPBACK_EXT)) { 5944 DP(NETIF_MSG_LINK, "not SGMII, no AN\n"); 5945 5946 /* Disable autoneg */ 5947 bnx2x_set_autoneg(phy, params, vars, 0); 5948 5949 /* Program speed and duplex */ 5950 bnx2x_program_serdes(phy, params, vars); 5951 5952 } else { /* AN_mode */ 5953 DP(NETIF_MSG_LINK, "not SGMII, AN\n"); 5954 5955 /* AN enabled */ 5956 bnx2x_set_brcm_cl37_advertisement(phy, params); 5957 5958 /* Program duplex & pause advertisement (for aneg) */ 5959 bnx2x_set_ieee_aneg_advertisement(phy, params, 5960 vars->ieee_fc); 5961 5962 /* Enable autoneg */ 5963 bnx2x_set_autoneg(phy, params, vars, enable_cl73); 5964 5965 /* Enable and restart AN */ 5966 bnx2x_restart_autoneg(phy, params, enable_cl73); 5967 } 5968 5969 } else { /* SGMII mode */ 5970 DP(NETIF_MSG_LINK, "SGMII\n"); 5971 5972 bnx2x_initialize_sgmii_process(phy, params, vars); 5973 } 5974 } 5975 5976 static int bnx2x_prepare_xgxs(struct bnx2x_phy *phy, 5977 struct link_params *params, 5978 struct link_vars *vars) 5979 { 5980 int rc; 5981 vars->phy_flags |= PHY_XGXS_FLAG; 5982 if ((phy->req_line_speed && 5983 ((phy->req_line_speed == SPEED_100) || 5984 (phy->req_line_speed == SPEED_10))) || 5985 (!phy->req_line_speed && 5986 (phy->speed_cap_mask >= 5987 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) && 5988 (phy->speed_cap_mask < 5989 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) || 5990 (phy->type == PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD)) 5991 vars->phy_flags |= PHY_SGMII_FLAG; 5992 else 5993 vars->phy_flags &= ~PHY_SGMII_FLAG; 5994 5995 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); 5996 bnx2x_set_aer_mmd(params, phy); 5997 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) 5998 bnx2x_set_master_ln(params, phy); 5999 6000 rc = bnx2x_reset_unicore(params, phy, 0); 6001 /* Reset the SerDes and wait for reset bit return low */ 6002 if (rc) 6003 return rc; 6004 6005 bnx2x_set_aer_mmd(params, phy); 6006 /* Setting the masterLn_def again after the reset */ 6007 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) { 6008 bnx2x_set_master_ln(params, phy); 6009 bnx2x_set_swap_lanes(params, phy); 6010 } 6011 6012 return rc; 6013 } 6014 6015 static u16 bnx2x_wait_reset_complete(struct bnx2x *bp, 6016 struct bnx2x_phy *phy, 6017 struct link_params *params) 6018 { 6019 u16 cnt, ctrl; 6020 /* Wait for soft reset to get cleared up to 1 sec */ 6021 for (cnt = 0; cnt < 1000; cnt++) { 6022 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) 6023 bnx2x_cl22_read(bp, phy, 6024 MDIO_PMA_REG_CTRL, &ctrl); 6025 else 6026 bnx2x_cl45_read(bp, phy, 6027 MDIO_PMA_DEVAD, 6028 MDIO_PMA_REG_CTRL, &ctrl); 6029 if (!(ctrl & (1<<15))) 6030 break; 6031 usleep_range(1000, 2000); 6032 } 6033 6034 if (cnt == 1000) 6035 netdev_err(bp->dev, "Warning: PHY was not initialized," 6036 " Port %d\n", 6037 params->port); 6038 DP(NETIF_MSG_LINK, "control reg 0x%x (after %d ms)\n", ctrl, cnt); 6039 return cnt; 6040 } 6041 6042 static void bnx2x_link_int_enable(struct link_params *params) 6043 { 6044 u8 port = params->port; 6045 u32 mask; 6046 struct bnx2x *bp = params->bp; 6047 6048 /* Setting the status to report on link up for either XGXS or SerDes */ 6049 if (CHIP_IS_E3(bp)) { 6050 mask = NIG_MASK_XGXS0_LINK_STATUS; 6051 if (!(SINGLE_MEDIA_DIRECT(params))) 6052 mask |= NIG_MASK_MI_INT; 6053 } else if (params->switch_cfg == SWITCH_CFG_10G) { 6054 mask = (NIG_MASK_XGXS0_LINK10G | 6055 NIG_MASK_XGXS0_LINK_STATUS); 6056 DP(NETIF_MSG_LINK, "enabled XGXS interrupt\n"); 6057 if (!(SINGLE_MEDIA_DIRECT(params)) && 6058 params->phy[INT_PHY].type != 6059 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) { 6060 mask |= NIG_MASK_MI_INT; 6061 DP(NETIF_MSG_LINK, "enabled external phy int\n"); 6062 } 6063 6064 } else { /* SerDes */ 6065 mask = NIG_MASK_SERDES0_LINK_STATUS; 6066 DP(NETIF_MSG_LINK, "enabled SerDes interrupt\n"); 6067 if (!(SINGLE_MEDIA_DIRECT(params)) && 6068 params->phy[INT_PHY].type != 6069 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN) { 6070 mask |= NIG_MASK_MI_INT; 6071 DP(NETIF_MSG_LINK, "enabled external phy int\n"); 6072 } 6073 } 6074 bnx2x_bits_en(bp, 6075 NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 6076 mask); 6077 6078 DP(NETIF_MSG_LINK, "port %x, is_xgxs %x, int_status 0x%x\n", port, 6079 (params->switch_cfg == SWITCH_CFG_10G), 6080 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4)); 6081 DP(NETIF_MSG_LINK, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x\n", 6082 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4), 6083 REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18), 6084 REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS+port*0x3c)); 6085 DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n", 6086 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68), 6087 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68)); 6088 } 6089 6090 static void bnx2x_rearm_latch_signal(struct bnx2x *bp, u8 port, 6091 u8 exp_mi_int) 6092 { 6093 u32 latch_status = 0; 6094 6095 /* Disable the MI INT ( external phy int ) by writing 1 to the 6096 * status register. Link down indication is high-active-signal, 6097 * so in this case we need to write the status to clear the XOR 6098 */ 6099 /* Read Latched signals */ 6100 latch_status = REG_RD(bp, 6101 NIG_REG_LATCH_STATUS_0 + port*8); 6102 DP(NETIF_MSG_LINK, "latch_status = 0x%x\n", latch_status); 6103 /* Handle only those with latched-signal=up.*/ 6104 if (exp_mi_int) 6105 bnx2x_bits_en(bp, 6106 NIG_REG_STATUS_INTERRUPT_PORT0 6107 + port*4, 6108 NIG_STATUS_EMAC0_MI_INT); 6109 else 6110 bnx2x_bits_dis(bp, 6111 NIG_REG_STATUS_INTERRUPT_PORT0 6112 + port*4, 6113 NIG_STATUS_EMAC0_MI_INT); 6114 6115 if (latch_status & 1) { 6116 6117 /* For all latched-signal=up : Re-Arm Latch signals */ 6118 REG_WR(bp, NIG_REG_LATCH_STATUS_0 + port*8, 6119 (latch_status & 0xfffe) | (latch_status & 1)); 6120 } 6121 /* For all latched-signal=up,Write original_signal to status */ 6122 } 6123 6124 static void bnx2x_link_int_ack(struct link_params *params, 6125 struct link_vars *vars, u8 is_10g_plus) 6126 { 6127 struct bnx2x *bp = params->bp; 6128 u8 port = params->port; 6129 u32 mask; 6130 /* First reset all status we assume only one line will be 6131 * change at a time 6132 */ 6133 bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4, 6134 (NIG_STATUS_XGXS0_LINK10G | 6135 NIG_STATUS_XGXS0_LINK_STATUS | 6136 NIG_STATUS_SERDES0_LINK_STATUS)); 6137 if (vars->phy_link_up) { 6138 if (USES_WARPCORE(bp)) 6139 mask = NIG_STATUS_XGXS0_LINK_STATUS; 6140 else { 6141 if (is_10g_plus) 6142 mask = NIG_STATUS_XGXS0_LINK10G; 6143 else if (params->switch_cfg == SWITCH_CFG_10G) { 6144 /* Disable the link interrupt by writing 1 to 6145 * the relevant lane in the status register 6146 */ 6147 u32 ser_lane = 6148 ((params->lane_config & 6149 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >> 6150 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT); 6151 mask = ((1 << ser_lane) << 6152 NIG_STATUS_XGXS0_LINK_STATUS_SIZE); 6153 } else 6154 mask = NIG_STATUS_SERDES0_LINK_STATUS; 6155 } 6156 DP(NETIF_MSG_LINK, "Ack link up interrupt with mask 0x%x\n", 6157 mask); 6158 bnx2x_bits_en(bp, 6159 NIG_REG_STATUS_INTERRUPT_PORT0 + port*4, 6160 mask); 6161 } 6162 } 6163 6164 static int bnx2x_null_format_ver(u32 spirom_ver, u8 *str, u16 *len) 6165 { 6166 str[0] = '\0'; 6167 (*len)--; 6168 return 0; 6169 } 6170 6171 static int bnx2x_format_ver(u32 num, u8 *str, u16 *len) 6172 { 6173 u16 ret; 6174 6175 if (*len < 10) { 6176 /* Need more than 10chars for this format */ 6177 bnx2x_null_format_ver(num, str, len); 6178 return -EINVAL; 6179 } 6180 6181 ret = scnprintf(str, *len, "%hx.%hx", num >> 16, num); 6182 *len -= ret; 6183 return 0; 6184 } 6185 6186 static int bnx2x_3_seq_format_ver(u32 num, u8 *str, u16 *len) 6187 { 6188 u16 ret; 6189 6190 if (*len < 10) { 6191 /* Need more than 10chars for this format */ 6192 bnx2x_null_format_ver(num, str, len); 6193 return -EINVAL; 6194 } 6195 6196 ret = scnprintf(str, *len, "%hhx.%hhx.%hhx", num >> 16, num >> 8, num); 6197 *len -= ret; 6198 return 0; 6199 } 6200 6201 int bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 *version, 6202 u16 len) 6203 { 6204 struct bnx2x *bp; 6205 u32 spirom_ver = 0; 6206 int status = 0; 6207 u8 *ver_p = version; 6208 u16 remain_len = len; 6209 if (version == NULL || params == NULL) 6210 return -EINVAL; 6211 bp = params->bp; 6212 6213 /* Extract first external phy*/ 6214 version[0] = '\0'; 6215 spirom_ver = REG_RD(bp, params->phy[EXT_PHY1].ver_addr); 6216 6217 if (params->phy[EXT_PHY1].format_fw_ver) { 6218 status |= params->phy[EXT_PHY1].format_fw_ver(spirom_ver, 6219 ver_p, 6220 &remain_len); 6221 ver_p += (len - remain_len); 6222 } 6223 if ((params->num_phys == MAX_PHYS) && 6224 (params->phy[EXT_PHY2].ver_addr != 0)) { 6225 spirom_ver = REG_RD(bp, params->phy[EXT_PHY2].ver_addr); 6226 if (params->phy[EXT_PHY2].format_fw_ver) { 6227 *ver_p = '/'; 6228 ver_p++; 6229 remain_len--; 6230 status |= params->phy[EXT_PHY2].format_fw_ver( 6231 spirom_ver, 6232 ver_p, 6233 &remain_len); 6234 ver_p = version + (len - remain_len); 6235 } 6236 } 6237 *ver_p = '\0'; 6238 return status; 6239 } 6240 6241 static void bnx2x_set_xgxs_loopback(struct bnx2x_phy *phy, 6242 struct link_params *params) 6243 { 6244 u8 port = params->port; 6245 struct bnx2x *bp = params->bp; 6246 6247 if (phy->req_line_speed != SPEED_1000) { 6248 u32 md_devad = 0; 6249 6250 DP(NETIF_MSG_LINK, "XGXS 10G loopback enable\n"); 6251 6252 if (!CHIP_IS_E3(bp)) { 6253 /* Change the uni_phy_addr in the nig */ 6254 md_devad = REG_RD(bp, (NIG_REG_XGXS0_CTRL_MD_DEVAD + 6255 port*0x18)); 6256 6257 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, 6258 0x5); 6259 } 6260 6261 bnx2x_cl45_write(bp, phy, 6262 5, 6263 (MDIO_REG_BANK_AER_BLOCK + 6264 (MDIO_AER_BLOCK_AER_REG & 0xf)), 6265 0x2800); 6266 6267 bnx2x_cl45_write(bp, phy, 6268 5, 6269 (MDIO_REG_BANK_CL73_IEEEB0 + 6270 (MDIO_CL73_IEEEB0_CL73_AN_CONTROL & 0xf)), 6271 0x6041); 6272 msleep(200); 6273 /* Set aer mmd back */ 6274 bnx2x_set_aer_mmd(params, phy); 6275 6276 if (!CHIP_IS_E3(bp)) { 6277 /* And md_devad */ 6278 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, 6279 md_devad); 6280 } 6281 } else { 6282 u16 mii_ctrl; 6283 DP(NETIF_MSG_LINK, "XGXS 1G loopback enable\n"); 6284 bnx2x_cl45_read(bp, phy, 5, 6285 (MDIO_REG_BANK_COMBO_IEEE0 + 6286 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)), 6287 &mii_ctrl); 6288 bnx2x_cl45_write(bp, phy, 5, 6289 (MDIO_REG_BANK_COMBO_IEEE0 + 6290 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)), 6291 mii_ctrl | 6292 MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK); 6293 } 6294 } 6295 6296 int bnx2x_set_led(struct link_params *params, 6297 struct link_vars *vars, u8 mode, u32 speed) 6298 { 6299 u8 port = params->port; 6300 u16 hw_led_mode = params->hw_led_mode; 6301 int rc = 0; 6302 u8 phy_idx; 6303 u32 tmp; 6304 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; 6305 struct bnx2x *bp = params->bp; 6306 DP(NETIF_MSG_LINK, "bnx2x_set_led: port %x, mode %d\n", port, mode); 6307 DP(NETIF_MSG_LINK, "speed 0x%x, hw_led_mode 0x%x\n", 6308 speed, hw_led_mode); 6309 /* In case */ 6310 for (phy_idx = EXT_PHY1; phy_idx < MAX_PHYS; phy_idx++) { 6311 if (params->phy[phy_idx].set_link_led) { 6312 params->phy[phy_idx].set_link_led( 6313 ¶ms->phy[phy_idx], params, mode); 6314 } 6315 } 6316 6317 switch (mode) { 6318 case LED_MODE_FRONT_PANEL_OFF: 6319 case LED_MODE_OFF: 6320 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 0); 6321 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 6322 SHARED_HW_CFG_LED_MAC1); 6323 6324 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED); 6325 if (params->phy[EXT_PHY1].type == 6326 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) 6327 tmp &= ~(EMAC_LED_1000MB_OVERRIDE | 6328 EMAC_LED_100MB_OVERRIDE | 6329 EMAC_LED_10MB_OVERRIDE); 6330 else 6331 tmp |= EMAC_LED_OVERRIDE; 6332 6333 EMAC_WR(bp, EMAC_REG_EMAC_LED, tmp); 6334 break; 6335 6336 case LED_MODE_OPER: 6337 /* For all other phys, OPER mode is same as ON, so in case 6338 * link is down, do nothing 6339 */ 6340 if (!vars->link_up) 6341 break; 6342 case LED_MODE_ON: 6343 if (((params->phy[EXT_PHY1].type == 6344 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) || 6345 (params->phy[EXT_PHY1].type == 6346 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722)) && 6347 CHIP_IS_E2(bp) && params->num_phys == 2) { 6348 /* This is a work-around for E2+8727 Configurations */ 6349 if (mode == LED_MODE_ON || 6350 speed == SPEED_10000){ 6351 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0); 6352 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1); 6353 6354 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED); 6355 EMAC_WR(bp, EMAC_REG_EMAC_LED, 6356 (tmp | EMAC_LED_OVERRIDE)); 6357 /* Return here without enabling traffic 6358 * LED blink and setting rate in ON mode. 6359 * In oper mode, enabling LED blink 6360 * and setting rate is needed. 6361 */ 6362 if (mode == LED_MODE_ON) 6363 return rc; 6364 } 6365 } else if (SINGLE_MEDIA_DIRECT(params)) { 6366 /* This is a work-around for HW issue found when link 6367 * is up in CL73 6368 */ 6369 if ((!CHIP_IS_E3(bp)) || 6370 (CHIP_IS_E3(bp) && 6371 mode == LED_MODE_ON)) 6372 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1); 6373 6374 if (CHIP_IS_E1x(bp) || 6375 CHIP_IS_E2(bp) || 6376 (mode == LED_MODE_ON)) 6377 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0); 6378 else 6379 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 6380 hw_led_mode); 6381 } else if ((params->phy[EXT_PHY1].type == 6382 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) && 6383 (mode == LED_MODE_ON)) { 6384 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0); 6385 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED); 6386 EMAC_WR(bp, EMAC_REG_EMAC_LED, tmp | 6387 EMAC_LED_OVERRIDE | EMAC_LED_1000MB_OVERRIDE); 6388 /* Break here; otherwise, it'll disable the 6389 * intended override. 6390 */ 6391 break; 6392 } else { 6393 u32 nig_led_mode = ((params->hw_led_mode << 6394 SHARED_HW_CFG_LED_MODE_SHIFT) == 6395 SHARED_HW_CFG_LED_EXTPHY2) ? 6396 (SHARED_HW_CFG_LED_PHY1 >> 6397 SHARED_HW_CFG_LED_MODE_SHIFT) : hw_led_mode; 6398 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 6399 nig_led_mode); 6400 } 6401 6402 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 0); 6403 /* Set blinking rate to ~15.9Hz */ 6404 if (CHIP_IS_E3(bp)) 6405 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4, 6406 LED_BLINK_RATE_VAL_E3); 6407 else 6408 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4, 6409 LED_BLINK_RATE_VAL_E1X_E2); 6410 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 + 6411 port*4, 1); 6412 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED); 6413 EMAC_WR(bp, EMAC_REG_EMAC_LED, 6414 (tmp & (~EMAC_LED_OVERRIDE))); 6415 6416 if (CHIP_IS_E1(bp) && 6417 ((speed == SPEED_2500) || 6418 (speed == SPEED_1000) || 6419 (speed == SPEED_100) || 6420 (speed == SPEED_10))) { 6421 /* For speeds less than 10G LED scheme is different */ 6422 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 6423 + port*4, 1); 6424 REG_WR(bp, NIG_REG_LED_CONTROL_TRAFFIC_P0 + 6425 port*4, 0); 6426 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 + 6427 port*4, 1); 6428 } 6429 break; 6430 6431 default: 6432 rc = -EINVAL; 6433 DP(NETIF_MSG_LINK, "bnx2x_set_led: Invalid led mode %d\n", 6434 mode); 6435 break; 6436 } 6437 return rc; 6438 6439 } 6440 6441 /* This function comes to reflect the actual link state read DIRECTLY from the 6442 * HW 6443 */ 6444 int bnx2x_test_link(struct link_params *params, struct link_vars *vars, 6445 u8 is_serdes) 6446 { 6447 struct bnx2x *bp = params->bp; 6448 u16 gp_status = 0, phy_index = 0; 6449 u8 ext_phy_link_up = 0, serdes_phy_type; 6450 struct link_vars temp_vars; 6451 struct bnx2x_phy *int_phy = ¶ms->phy[INT_PHY]; 6452 6453 if (CHIP_IS_E3(bp)) { 6454 u16 link_up; 6455 if (params->req_line_speed[LINK_CONFIG_IDX(INT_PHY)] 6456 > SPEED_10000) { 6457 /* Check 20G link */ 6458 bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD, 6459 1, &link_up); 6460 bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD, 6461 1, &link_up); 6462 link_up &= (1<<2); 6463 } else { 6464 /* Check 10G link and below*/ 6465 u8 lane = bnx2x_get_warpcore_lane(int_phy, params); 6466 bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD, 6467 MDIO_WC_REG_GP2_STATUS_GP_2_1, 6468 &gp_status); 6469 gp_status = ((gp_status >> 8) & 0xf) | 6470 ((gp_status >> 12) & 0xf); 6471 link_up = gp_status & (1 << lane); 6472 } 6473 if (!link_up) 6474 return -ESRCH; 6475 } else { 6476 CL22_RD_OVER_CL45(bp, int_phy, 6477 MDIO_REG_BANK_GP_STATUS, 6478 MDIO_GP_STATUS_TOP_AN_STATUS1, 6479 &gp_status); 6480 /* Link is up only if both local phy and external phy are up */ 6481 if (!(gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS)) 6482 return -ESRCH; 6483 } 6484 /* In XGXS loopback mode, do not check external PHY */ 6485 if (params->loopback_mode == LOOPBACK_XGXS) 6486 return 0; 6487 6488 switch (params->num_phys) { 6489 case 1: 6490 /* No external PHY */ 6491 return 0; 6492 case 2: 6493 ext_phy_link_up = params->phy[EXT_PHY1].read_status( 6494 ¶ms->phy[EXT_PHY1], 6495 params, &temp_vars); 6496 break; 6497 case 3: /* Dual Media */ 6498 for (phy_index = EXT_PHY1; phy_index < params->num_phys; 6499 phy_index++) { 6500 serdes_phy_type = ((params->phy[phy_index].media_type == 6501 ETH_PHY_SFPP_10G_FIBER) || 6502 (params->phy[phy_index].media_type == 6503 ETH_PHY_SFP_1G_FIBER) || 6504 (params->phy[phy_index].media_type == 6505 ETH_PHY_XFP_FIBER) || 6506 (params->phy[phy_index].media_type == 6507 ETH_PHY_DA_TWINAX)); 6508 6509 if (is_serdes != serdes_phy_type) 6510 continue; 6511 if (params->phy[phy_index].read_status) { 6512 ext_phy_link_up |= 6513 params->phy[phy_index].read_status( 6514 ¶ms->phy[phy_index], 6515 params, &temp_vars); 6516 } 6517 } 6518 break; 6519 } 6520 if (ext_phy_link_up) 6521 return 0; 6522 return -ESRCH; 6523 } 6524 6525 static int bnx2x_link_initialize(struct link_params *params, 6526 struct link_vars *vars) 6527 { 6528 u8 phy_index, non_ext_phy; 6529 struct bnx2x *bp = params->bp; 6530 /* In case of external phy existence, the line speed would be the 6531 * line speed linked up by the external phy. In case it is direct 6532 * only, then the line_speed during initialization will be 6533 * equal to the req_line_speed 6534 */ 6535 vars->line_speed = params->phy[INT_PHY].req_line_speed; 6536 6537 /* Initialize the internal phy in case this is a direct board 6538 * (no external phys), or this board has external phy which requires 6539 * to first. 6540 */ 6541 if (!USES_WARPCORE(bp)) 6542 bnx2x_prepare_xgxs(¶ms->phy[INT_PHY], params, vars); 6543 /* init ext phy and enable link state int */ 6544 non_ext_phy = (SINGLE_MEDIA_DIRECT(params) || 6545 (params->loopback_mode == LOOPBACK_XGXS)); 6546 6547 if (non_ext_phy || 6548 (params->phy[EXT_PHY1].flags & FLAGS_INIT_XGXS_FIRST) || 6549 (params->loopback_mode == LOOPBACK_EXT_PHY)) { 6550 struct bnx2x_phy *phy = ¶ms->phy[INT_PHY]; 6551 if (vars->line_speed == SPEED_AUTO_NEG && 6552 (CHIP_IS_E1x(bp) || 6553 CHIP_IS_E2(bp))) 6554 bnx2x_set_parallel_detection(phy, params); 6555 if (params->phy[INT_PHY].config_init) 6556 params->phy[INT_PHY].config_init(phy, params, vars); 6557 } 6558 6559 /* Re-read this value in case it was changed inside config_init due to 6560 * limitations of optic module 6561 */ 6562 vars->line_speed = params->phy[INT_PHY].req_line_speed; 6563 6564 /* Init external phy*/ 6565 if (non_ext_phy) { 6566 if (params->phy[INT_PHY].supported & 6567 SUPPORTED_FIBRE) 6568 vars->link_status |= LINK_STATUS_SERDES_LINK; 6569 } else { 6570 for (phy_index = EXT_PHY1; phy_index < params->num_phys; 6571 phy_index++) { 6572 /* No need to initialize second phy in case of first 6573 * phy only selection. In case of second phy, we do 6574 * need to initialize the first phy, since they are 6575 * connected. 6576 */ 6577 if (params->phy[phy_index].supported & 6578 SUPPORTED_FIBRE) 6579 vars->link_status |= LINK_STATUS_SERDES_LINK; 6580 6581 if (phy_index == EXT_PHY2 && 6582 (bnx2x_phy_selection(params) == 6583 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY)) { 6584 DP(NETIF_MSG_LINK, 6585 "Not initializing second phy\n"); 6586 continue; 6587 } 6588 params->phy[phy_index].config_init( 6589 ¶ms->phy[phy_index], 6590 params, vars); 6591 } 6592 } 6593 /* Reset the interrupt indication after phy was initialized */ 6594 bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + 6595 params->port*4, 6596 (NIG_STATUS_XGXS0_LINK10G | 6597 NIG_STATUS_XGXS0_LINK_STATUS | 6598 NIG_STATUS_SERDES0_LINK_STATUS | 6599 NIG_MASK_MI_INT)); 6600 return 0; 6601 } 6602 6603 static void bnx2x_int_link_reset(struct bnx2x_phy *phy, 6604 struct link_params *params) 6605 { 6606 /* Reset the SerDes/XGXS */ 6607 REG_WR(params->bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, 6608 (0x1ff << (params->port*16))); 6609 } 6610 6611 static void bnx2x_common_ext_link_reset(struct bnx2x_phy *phy, 6612 struct link_params *params) 6613 { 6614 struct bnx2x *bp = params->bp; 6615 u8 gpio_port; 6616 /* HW reset */ 6617 if (CHIP_IS_E2(bp)) 6618 gpio_port = BP_PATH(bp); 6619 else 6620 gpio_port = params->port; 6621 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, 6622 MISC_REGISTERS_GPIO_OUTPUT_LOW, 6623 gpio_port); 6624 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 6625 MISC_REGISTERS_GPIO_OUTPUT_LOW, 6626 gpio_port); 6627 DP(NETIF_MSG_LINK, "reset external PHY\n"); 6628 } 6629 6630 static int bnx2x_update_link_down(struct link_params *params, 6631 struct link_vars *vars) 6632 { 6633 struct bnx2x *bp = params->bp; 6634 u8 port = params->port; 6635 6636 DP(NETIF_MSG_LINK, "Port %x: Link is down\n", port); 6637 bnx2x_set_led(params, vars, LED_MODE_OFF, 0); 6638 vars->phy_flags &= ~PHY_PHYSICAL_LINK_FLAG; 6639 /* Indicate no mac active */ 6640 vars->mac_type = MAC_TYPE_NONE; 6641 6642 /* Update shared memory */ 6643 vars->link_status &= ~LINK_UPDATE_MASK; 6644 vars->line_speed = 0; 6645 bnx2x_update_mng(params, vars->link_status); 6646 6647 /* Activate nig drain */ 6648 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1); 6649 6650 /* Disable emac */ 6651 if (!CHIP_IS_E3(bp)) 6652 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0); 6653 6654 usleep_range(10000, 20000); 6655 /* Reset BigMac/Xmac */ 6656 if (CHIP_IS_E1x(bp) || 6657 CHIP_IS_E2(bp)) 6658 bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 0); 6659 6660 if (CHIP_IS_E3(bp)) { 6661 /* Prevent LPI Generation by chip */ 6662 REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2), 6663 0); 6664 REG_WR(bp, MISC_REG_CPMU_LP_MASK_ENT_P0 + (params->port << 2), 6665 0); 6666 vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK | 6667 SHMEM_EEE_ACTIVE_BIT); 6668 6669 bnx2x_update_mng_eee(params, vars->eee_status); 6670 bnx2x_set_xmac_rxtx(params, 0); 6671 bnx2x_set_umac_rxtx(params, 0); 6672 } 6673 6674 return 0; 6675 } 6676 6677 static int bnx2x_update_link_up(struct link_params *params, 6678 struct link_vars *vars, 6679 u8 link_10g) 6680 { 6681 struct bnx2x *bp = params->bp; 6682 u8 phy_idx, port = params->port; 6683 int rc = 0; 6684 6685 vars->link_status |= (LINK_STATUS_LINK_UP | 6686 LINK_STATUS_PHYSICAL_LINK_FLAG); 6687 vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG; 6688 6689 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) 6690 vars->link_status |= 6691 LINK_STATUS_TX_FLOW_CONTROL_ENABLED; 6692 6693 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX) 6694 vars->link_status |= 6695 LINK_STATUS_RX_FLOW_CONTROL_ENABLED; 6696 if (USES_WARPCORE(bp)) { 6697 if (link_10g) { 6698 if (bnx2x_xmac_enable(params, vars, 0) == 6699 -ESRCH) { 6700 DP(NETIF_MSG_LINK, "Found errors on XMAC\n"); 6701 vars->link_up = 0; 6702 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG; 6703 vars->link_status &= ~LINK_STATUS_LINK_UP; 6704 } 6705 } else 6706 bnx2x_umac_enable(params, vars, 0); 6707 bnx2x_set_led(params, vars, 6708 LED_MODE_OPER, vars->line_speed); 6709 6710 if ((vars->eee_status & SHMEM_EEE_ACTIVE_BIT) && 6711 (vars->eee_status & SHMEM_EEE_LPI_REQUESTED_BIT)) { 6712 DP(NETIF_MSG_LINK, "Enabling LPI assertion\n"); 6713 REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + 6714 (params->port << 2), 1); 6715 REG_WR(bp, MISC_REG_CPMU_LP_DR_ENABLE, 1); 6716 REG_WR(bp, MISC_REG_CPMU_LP_MASK_ENT_P0 + 6717 (params->port << 2), 0xfc20); 6718 } 6719 } 6720 if ((CHIP_IS_E1x(bp) || 6721 CHIP_IS_E2(bp))) { 6722 if (link_10g) { 6723 if (bnx2x_bmac_enable(params, vars, 0, 1) == 6724 -ESRCH) { 6725 DP(NETIF_MSG_LINK, "Found errors on BMAC\n"); 6726 vars->link_up = 0; 6727 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG; 6728 vars->link_status &= ~LINK_STATUS_LINK_UP; 6729 } 6730 6731 bnx2x_set_led(params, vars, 6732 LED_MODE_OPER, SPEED_10000); 6733 } else { 6734 rc = bnx2x_emac_program(params, vars); 6735 bnx2x_emac_enable(params, vars, 0); 6736 6737 /* AN complete? */ 6738 if ((vars->link_status & 6739 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) 6740 && (!(vars->phy_flags & PHY_SGMII_FLAG)) && 6741 SINGLE_MEDIA_DIRECT(params)) 6742 bnx2x_set_gmii_tx_driver(params); 6743 } 6744 } 6745 6746 /* PBF - link up */ 6747 if (CHIP_IS_E1x(bp)) 6748 rc |= bnx2x_pbf_update(params, vars->flow_ctrl, 6749 vars->line_speed); 6750 6751 /* Disable drain */ 6752 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0); 6753 6754 /* Update shared memory */ 6755 bnx2x_update_mng(params, vars->link_status); 6756 bnx2x_update_mng_eee(params, vars->eee_status); 6757 /* Check remote fault */ 6758 for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) { 6759 if (params->phy[phy_idx].flags & FLAGS_TX_ERROR_CHECK) { 6760 bnx2x_check_half_open_conn(params, vars, 0); 6761 break; 6762 } 6763 } 6764 msleep(20); 6765 return rc; 6766 } 6767 6768 static void bnx2x_chng_link_count(struct link_params *params, bool clear) 6769 { 6770 struct bnx2x *bp = params->bp; 6771 u32 addr, val; 6772 6773 /* Verify the link_change_count is supported by the MFW */ 6774 if (!(SHMEM2_HAS(bp, link_change_count))) 6775 return; 6776 6777 addr = params->shmem2_base + 6778 offsetof(struct shmem2_region, link_change_count[params->port]); 6779 if (clear) 6780 val = 0; 6781 else 6782 val = REG_RD(bp, addr) + 1; 6783 REG_WR(bp, addr, val); 6784 } 6785 6786 /* The bnx2x_link_update function should be called upon link 6787 * interrupt. 6788 * Link is considered up as follows: 6789 * - DIRECT_SINGLE_MEDIA - Only XGXS link (internal link) needs 6790 * to be up 6791 * - SINGLE_MEDIA - The link between the 577xx and the external 6792 * phy (XGXS) need to up as well as the external link of the 6793 * phy (PHY_EXT1) 6794 * - DUAL_MEDIA - The link between the 577xx and the first 6795 * external phy needs to be up, and at least one of the 2 6796 * external phy link must be up. 6797 */ 6798 int bnx2x_link_update(struct link_params *params, struct link_vars *vars) 6799 { 6800 struct bnx2x *bp = params->bp; 6801 struct link_vars phy_vars[MAX_PHYS]; 6802 u8 port = params->port; 6803 u8 link_10g_plus, phy_index; 6804 u32 prev_link_status = vars->link_status; 6805 u8 ext_phy_link_up = 0, cur_link_up; 6806 int rc = 0; 6807 u8 is_mi_int = 0; 6808 u16 ext_phy_line_speed = 0, prev_line_speed = vars->line_speed; 6809 u8 active_external_phy = INT_PHY; 6810 vars->phy_flags &= ~PHY_HALF_OPEN_CONN_FLAG; 6811 vars->link_status &= ~LINK_UPDATE_MASK; 6812 for (phy_index = INT_PHY; phy_index < params->num_phys; 6813 phy_index++) { 6814 phy_vars[phy_index].flow_ctrl = 0; 6815 phy_vars[phy_index].link_status = 0; 6816 phy_vars[phy_index].line_speed = 0; 6817 phy_vars[phy_index].duplex = DUPLEX_FULL; 6818 phy_vars[phy_index].phy_link_up = 0; 6819 phy_vars[phy_index].link_up = 0; 6820 phy_vars[phy_index].fault_detected = 0; 6821 /* different consideration, since vars holds inner state */ 6822 phy_vars[phy_index].eee_status = vars->eee_status; 6823 } 6824 6825 if (USES_WARPCORE(bp)) 6826 bnx2x_set_aer_mmd(params, ¶ms->phy[INT_PHY]); 6827 6828 DP(NETIF_MSG_LINK, "port %x, XGXS?%x, int_status 0x%x\n", 6829 port, (vars->phy_flags & PHY_XGXS_FLAG), 6830 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4)); 6831 6832 is_mi_int = (u8)(REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + 6833 port*0x18) > 0); 6834 DP(NETIF_MSG_LINK, "int_mask 0x%x MI_INT %x, SERDES_LINK %x\n", 6835 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4), 6836 is_mi_int, 6837 REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c)); 6838 6839 DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n", 6840 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68), 6841 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68)); 6842 6843 /* Disable emac */ 6844 if (!CHIP_IS_E3(bp)) 6845 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0); 6846 6847 /* Step 1: 6848 * Check external link change only for external phys, and apply 6849 * priority selection between them in case the link on both phys 6850 * is up. Note that instead of the common vars, a temporary 6851 * vars argument is used since each phy may have different link/ 6852 * speed/duplex result 6853 */ 6854 for (phy_index = EXT_PHY1; phy_index < params->num_phys; 6855 phy_index++) { 6856 struct bnx2x_phy *phy = ¶ms->phy[phy_index]; 6857 if (!phy->read_status) 6858 continue; 6859 /* Read link status and params of this ext phy */ 6860 cur_link_up = phy->read_status(phy, params, 6861 &phy_vars[phy_index]); 6862 if (cur_link_up) { 6863 DP(NETIF_MSG_LINK, "phy in index %d link is up\n", 6864 phy_index); 6865 } else { 6866 DP(NETIF_MSG_LINK, "phy in index %d link is down\n", 6867 phy_index); 6868 continue; 6869 } 6870 6871 if (!ext_phy_link_up) { 6872 ext_phy_link_up = 1; 6873 active_external_phy = phy_index; 6874 } else { 6875 switch (bnx2x_phy_selection(params)) { 6876 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT: 6877 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY: 6878 /* In this option, the first PHY makes sure to pass the 6879 * traffic through itself only. 6880 * Its not clear how to reset the link on the second phy 6881 */ 6882 active_external_phy = EXT_PHY1; 6883 break; 6884 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY: 6885 /* In this option, the first PHY makes sure to pass the 6886 * traffic through the second PHY. 6887 */ 6888 active_external_phy = EXT_PHY2; 6889 break; 6890 default: 6891 /* Link indication on both PHYs with the following cases 6892 * is invalid: 6893 * - FIRST_PHY means that second phy wasn't initialized, 6894 * hence its link is expected to be down 6895 * - SECOND_PHY means that first phy should not be able 6896 * to link up by itself (using configuration) 6897 * - DEFAULT should be overridden during initialization 6898 */ 6899 DP(NETIF_MSG_LINK, "Invalid link indication" 6900 "mpc=0x%x. DISABLING LINK !!!\n", 6901 params->multi_phy_config); 6902 ext_phy_link_up = 0; 6903 break; 6904 } 6905 } 6906 } 6907 prev_line_speed = vars->line_speed; 6908 /* Step 2: 6909 * Read the status of the internal phy. In case of 6910 * DIRECT_SINGLE_MEDIA board, this link is the external link, 6911 * otherwise this is the link between the 577xx and the first 6912 * external phy 6913 */ 6914 if (params->phy[INT_PHY].read_status) 6915 params->phy[INT_PHY].read_status( 6916 ¶ms->phy[INT_PHY], 6917 params, vars); 6918 /* The INT_PHY flow control reside in the vars. This include the 6919 * case where the speed or flow control are not set to AUTO. 6920 * Otherwise, the active external phy flow control result is set 6921 * to the vars. The ext_phy_line_speed is needed to check if the 6922 * speed is different between the internal phy and external phy. 6923 * This case may be result of intermediate link speed change. 6924 */ 6925 if (active_external_phy > INT_PHY) { 6926 vars->flow_ctrl = phy_vars[active_external_phy].flow_ctrl; 6927 /* Link speed is taken from the XGXS. AN and FC result from 6928 * the external phy. 6929 */ 6930 vars->link_status |= phy_vars[active_external_phy].link_status; 6931 6932 /* if active_external_phy is first PHY and link is up - disable 6933 * disable TX on second external PHY 6934 */ 6935 if (active_external_phy == EXT_PHY1) { 6936 if (params->phy[EXT_PHY2].phy_specific_func) { 6937 DP(NETIF_MSG_LINK, 6938 "Disabling TX on EXT_PHY2\n"); 6939 params->phy[EXT_PHY2].phy_specific_func( 6940 ¶ms->phy[EXT_PHY2], 6941 params, DISABLE_TX); 6942 } 6943 } 6944 6945 ext_phy_line_speed = phy_vars[active_external_phy].line_speed; 6946 vars->duplex = phy_vars[active_external_phy].duplex; 6947 if (params->phy[active_external_phy].supported & 6948 SUPPORTED_FIBRE) 6949 vars->link_status |= LINK_STATUS_SERDES_LINK; 6950 else 6951 vars->link_status &= ~LINK_STATUS_SERDES_LINK; 6952 6953 vars->eee_status = phy_vars[active_external_phy].eee_status; 6954 6955 DP(NETIF_MSG_LINK, "Active external phy selected: %x\n", 6956 active_external_phy); 6957 } 6958 6959 for (phy_index = EXT_PHY1; phy_index < params->num_phys; 6960 phy_index++) { 6961 if (params->phy[phy_index].flags & 6962 FLAGS_REARM_LATCH_SIGNAL) { 6963 bnx2x_rearm_latch_signal(bp, port, 6964 phy_index == 6965 active_external_phy); 6966 break; 6967 } 6968 } 6969 DP(NETIF_MSG_LINK, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x," 6970 " ext_phy_line_speed = %d\n", vars->flow_ctrl, 6971 vars->link_status, ext_phy_line_speed); 6972 /* Upon link speed change set the NIG into drain mode. Comes to 6973 * deals with possible FIFO glitch due to clk change when speed 6974 * is decreased without link down indicator 6975 */ 6976 6977 if (vars->phy_link_up) { 6978 if (!(SINGLE_MEDIA_DIRECT(params)) && ext_phy_link_up && 6979 (ext_phy_line_speed != vars->line_speed)) { 6980 DP(NETIF_MSG_LINK, "Internal link speed %d is" 6981 " different than the external" 6982 " link speed %d\n", vars->line_speed, 6983 ext_phy_line_speed); 6984 vars->phy_link_up = 0; 6985 } else if (prev_line_speed != vars->line_speed) { 6986 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 6987 0); 6988 usleep_range(1000, 2000); 6989 } 6990 } 6991 6992 /* Anything 10 and over uses the bmac */ 6993 link_10g_plus = (vars->line_speed >= SPEED_10000); 6994 6995 bnx2x_link_int_ack(params, vars, link_10g_plus); 6996 6997 /* In case external phy link is up, and internal link is down 6998 * (not initialized yet probably after link initialization, it 6999 * needs to be initialized. 7000 * Note that after link down-up as result of cable plug, the xgxs 7001 * link would probably become up again without the need 7002 * initialize it 7003 */ 7004 if (!(SINGLE_MEDIA_DIRECT(params))) { 7005 DP(NETIF_MSG_LINK, "ext_phy_link_up = %d, int_link_up = %d," 7006 " init_preceding = %d\n", ext_phy_link_up, 7007 vars->phy_link_up, 7008 params->phy[EXT_PHY1].flags & 7009 FLAGS_INIT_XGXS_FIRST); 7010 if (!(params->phy[EXT_PHY1].flags & 7011 FLAGS_INIT_XGXS_FIRST) 7012 && ext_phy_link_up && !vars->phy_link_up) { 7013 vars->line_speed = ext_phy_line_speed; 7014 if (vars->line_speed < SPEED_1000) 7015 vars->phy_flags |= PHY_SGMII_FLAG; 7016 else 7017 vars->phy_flags &= ~PHY_SGMII_FLAG; 7018 7019 if (params->phy[INT_PHY].config_init) 7020 params->phy[INT_PHY].config_init( 7021 ¶ms->phy[INT_PHY], params, 7022 vars); 7023 } 7024 } 7025 /* Link is up only if both local phy and external phy (in case of 7026 * non-direct board) are up and no fault detected on active PHY. 7027 */ 7028 vars->link_up = (vars->phy_link_up && 7029 (ext_phy_link_up || 7030 SINGLE_MEDIA_DIRECT(params)) && 7031 (phy_vars[active_external_phy].fault_detected == 0)); 7032 7033 /* Update the PFC configuration in case it was changed */ 7034 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) 7035 vars->link_status |= LINK_STATUS_PFC_ENABLED; 7036 else 7037 vars->link_status &= ~LINK_STATUS_PFC_ENABLED; 7038 7039 if (vars->link_up) 7040 rc = bnx2x_update_link_up(params, vars, link_10g_plus); 7041 else 7042 rc = bnx2x_update_link_down(params, vars); 7043 7044 if ((prev_link_status ^ vars->link_status) & LINK_STATUS_LINK_UP) 7045 bnx2x_chng_link_count(params, false); 7046 7047 /* Update MCP link status was changed */ 7048 if (params->feature_config_flags & FEATURE_CONFIG_BC_SUPPORTS_AFEX) 7049 bnx2x_fw_command(bp, DRV_MSG_CODE_LINK_STATUS_CHANGED, 0); 7050 7051 return rc; 7052 } 7053 7054 /*****************************************************************************/ 7055 /* External Phy section */ 7056 /*****************************************************************************/ 7057 void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port) 7058 { 7059 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, 7060 MISC_REGISTERS_GPIO_OUTPUT_LOW, port); 7061 usleep_range(1000, 2000); 7062 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, 7063 MISC_REGISTERS_GPIO_OUTPUT_HIGH, port); 7064 } 7065 7066 static void bnx2x_save_spirom_version(struct bnx2x *bp, u8 port, 7067 u32 spirom_ver, u32 ver_addr) 7068 { 7069 DP(NETIF_MSG_LINK, "FW version 0x%x:0x%x for port %d\n", 7070 (u16)(spirom_ver>>16), (u16)spirom_ver, port); 7071 7072 if (ver_addr) 7073 REG_WR(bp, ver_addr, spirom_ver); 7074 } 7075 7076 static void bnx2x_save_bcm_spirom_ver(struct bnx2x *bp, 7077 struct bnx2x_phy *phy, 7078 u8 port) 7079 { 7080 u16 fw_ver1, fw_ver2; 7081 7082 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 7083 MDIO_PMA_REG_ROM_VER1, &fw_ver1); 7084 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 7085 MDIO_PMA_REG_ROM_VER2, &fw_ver2); 7086 bnx2x_save_spirom_version(bp, port, (u32)(fw_ver1<<16 | fw_ver2), 7087 phy->ver_addr); 7088 } 7089 7090 static void bnx2x_ext_phy_10G_an_resolve(struct bnx2x *bp, 7091 struct bnx2x_phy *phy, 7092 struct link_vars *vars) 7093 { 7094 u16 val; 7095 bnx2x_cl45_read(bp, phy, 7096 MDIO_AN_DEVAD, 7097 MDIO_AN_REG_STATUS, &val); 7098 bnx2x_cl45_read(bp, phy, 7099 MDIO_AN_DEVAD, 7100 MDIO_AN_REG_STATUS, &val); 7101 if (val & (1<<5)) 7102 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; 7103 if ((val & (1<<0)) == 0) 7104 vars->link_status |= LINK_STATUS_PARALLEL_DETECTION_USED; 7105 } 7106 7107 /******************************************************************/ 7108 /* common BCM8073/BCM8727 PHY SECTION */ 7109 /******************************************************************/ 7110 static void bnx2x_8073_resolve_fc(struct bnx2x_phy *phy, 7111 struct link_params *params, 7112 struct link_vars *vars) 7113 { 7114 struct bnx2x *bp = params->bp; 7115 if (phy->req_line_speed == SPEED_10 || 7116 phy->req_line_speed == SPEED_100) { 7117 vars->flow_ctrl = phy->req_flow_ctrl; 7118 return; 7119 } 7120 7121 if (bnx2x_ext_phy_resolve_fc(phy, params, vars) && 7122 (vars->flow_ctrl == BNX2X_FLOW_CTRL_NONE)) { 7123 u16 pause_result; 7124 u16 ld_pause; /* local */ 7125 u16 lp_pause; /* link partner */ 7126 bnx2x_cl45_read(bp, phy, 7127 MDIO_AN_DEVAD, 7128 MDIO_AN_REG_CL37_FC_LD, &ld_pause); 7129 7130 bnx2x_cl45_read(bp, phy, 7131 MDIO_AN_DEVAD, 7132 MDIO_AN_REG_CL37_FC_LP, &lp_pause); 7133 pause_result = (ld_pause & 7134 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 5; 7135 pause_result |= (lp_pause & 7136 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 7; 7137 7138 bnx2x_pause_resolve(phy, params, vars, pause_result); 7139 DP(NETIF_MSG_LINK, "Ext PHY CL37 pause result 0x%x\n", 7140 pause_result); 7141 } 7142 } 7143 static int bnx2x_8073_8727_external_rom_boot(struct bnx2x *bp, 7144 struct bnx2x_phy *phy, 7145 u8 port) 7146 { 7147 u32 count = 0; 7148 u16 fw_ver1, fw_msgout; 7149 int rc = 0; 7150 7151 /* Boot port from external ROM */ 7152 /* EDC grst */ 7153 bnx2x_cl45_write(bp, phy, 7154 MDIO_PMA_DEVAD, 7155 MDIO_PMA_REG_GEN_CTRL, 7156 0x0001); 7157 7158 /* Ucode reboot and rst */ 7159 bnx2x_cl45_write(bp, phy, 7160 MDIO_PMA_DEVAD, 7161 MDIO_PMA_REG_GEN_CTRL, 7162 0x008c); 7163 7164 bnx2x_cl45_write(bp, phy, 7165 MDIO_PMA_DEVAD, 7166 MDIO_PMA_REG_MISC_CTRL1, 0x0001); 7167 7168 /* Reset internal microprocessor */ 7169 bnx2x_cl45_write(bp, phy, 7170 MDIO_PMA_DEVAD, 7171 MDIO_PMA_REG_GEN_CTRL, 7172 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET); 7173 7174 /* Release srst bit */ 7175 bnx2x_cl45_write(bp, phy, 7176 MDIO_PMA_DEVAD, 7177 MDIO_PMA_REG_GEN_CTRL, 7178 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP); 7179 7180 /* Delay 100ms per the PHY specifications */ 7181 msleep(100); 7182 7183 /* 8073 sometimes taking longer to download */ 7184 do { 7185 count++; 7186 if (count > 300) { 7187 DP(NETIF_MSG_LINK, 7188 "bnx2x_8073_8727_external_rom_boot port %x:" 7189 "Download failed. fw version = 0x%x\n", 7190 port, fw_ver1); 7191 rc = -EINVAL; 7192 break; 7193 } 7194 7195 bnx2x_cl45_read(bp, phy, 7196 MDIO_PMA_DEVAD, 7197 MDIO_PMA_REG_ROM_VER1, &fw_ver1); 7198 bnx2x_cl45_read(bp, phy, 7199 MDIO_PMA_DEVAD, 7200 MDIO_PMA_REG_M8051_MSGOUT_REG, &fw_msgout); 7201 7202 usleep_range(1000, 2000); 7203 } while (fw_ver1 == 0 || fw_ver1 == 0x4321 || 7204 ((fw_msgout & 0xff) != 0x03 && (phy->type == 7205 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073))); 7206 7207 /* Clear ser_boot_ctl bit */ 7208 bnx2x_cl45_write(bp, phy, 7209 MDIO_PMA_DEVAD, 7210 MDIO_PMA_REG_MISC_CTRL1, 0x0000); 7211 bnx2x_save_bcm_spirom_ver(bp, phy, port); 7212 7213 DP(NETIF_MSG_LINK, 7214 "bnx2x_8073_8727_external_rom_boot port %x:" 7215 "Download complete. fw version = 0x%x\n", 7216 port, fw_ver1); 7217 7218 return rc; 7219 } 7220 7221 /******************************************************************/ 7222 /* BCM8073 PHY SECTION */ 7223 /******************************************************************/ 7224 static int bnx2x_8073_is_snr_needed(struct bnx2x *bp, struct bnx2x_phy *phy) 7225 { 7226 /* This is only required for 8073A1, version 102 only */ 7227 u16 val; 7228 7229 /* Read 8073 HW revision*/ 7230 bnx2x_cl45_read(bp, phy, 7231 MDIO_PMA_DEVAD, 7232 MDIO_PMA_REG_8073_CHIP_REV, &val); 7233 7234 if (val != 1) { 7235 /* No need to workaround in 8073 A1 */ 7236 return 0; 7237 } 7238 7239 bnx2x_cl45_read(bp, phy, 7240 MDIO_PMA_DEVAD, 7241 MDIO_PMA_REG_ROM_VER2, &val); 7242 7243 /* SNR should be applied only for version 0x102 */ 7244 if (val != 0x102) 7245 return 0; 7246 7247 return 1; 7248 } 7249 7250 static int bnx2x_8073_xaui_wa(struct bnx2x *bp, struct bnx2x_phy *phy) 7251 { 7252 u16 val, cnt, cnt1 ; 7253 7254 bnx2x_cl45_read(bp, phy, 7255 MDIO_PMA_DEVAD, 7256 MDIO_PMA_REG_8073_CHIP_REV, &val); 7257 7258 if (val > 0) { 7259 /* No need to workaround in 8073 A1 */ 7260 return 0; 7261 } 7262 /* XAUI workaround in 8073 A0: */ 7263 7264 /* After loading the boot ROM and restarting Autoneg, poll 7265 * Dev1, Reg $C820: 7266 */ 7267 7268 for (cnt = 0; cnt < 1000; cnt++) { 7269 bnx2x_cl45_read(bp, phy, 7270 MDIO_PMA_DEVAD, 7271 MDIO_PMA_REG_8073_SPEED_LINK_STATUS, 7272 &val); 7273 /* If bit [14] = 0 or bit [13] = 0, continue on with 7274 * system initialization (XAUI work-around not required, as 7275 * these bits indicate 2.5G or 1G link up). 7276 */ 7277 if (!(val & (1<<14)) || !(val & (1<<13))) { 7278 DP(NETIF_MSG_LINK, "XAUI work-around not required\n"); 7279 return 0; 7280 } else if (!(val & (1<<15))) { 7281 DP(NETIF_MSG_LINK, "bit 15 went off\n"); 7282 /* If bit 15 is 0, then poll Dev1, Reg $C841 until it's 7283 * MSB (bit15) goes to 1 (indicating that the XAUI 7284 * workaround has completed), then continue on with 7285 * system initialization. 7286 */ 7287 for (cnt1 = 0; cnt1 < 1000; cnt1++) { 7288 bnx2x_cl45_read(bp, phy, 7289 MDIO_PMA_DEVAD, 7290 MDIO_PMA_REG_8073_XAUI_WA, &val); 7291 if (val & (1<<15)) { 7292 DP(NETIF_MSG_LINK, 7293 "XAUI workaround has completed\n"); 7294 return 0; 7295 } 7296 usleep_range(3000, 6000); 7297 } 7298 break; 7299 } 7300 usleep_range(3000, 6000); 7301 } 7302 DP(NETIF_MSG_LINK, "Warning: XAUI work-around timeout !!!\n"); 7303 return -EINVAL; 7304 } 7305 7306 static void bnx2x_807x_force_10G(struct bnx2x *bp, struct bnx2x_phy *phy) 7307 { 7308 /* Force KR or KX */ 7309 bnx2x_cl45_write(bp, phy, 7310 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040); 7311 bnx2x_cl45_write(bp, phy, 7312 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0x000b); 7313 bnx2x_cl45_write(bp, phy, 7314 MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0000); 7315 bnx2x_cl45_write(bp, phy, 7316 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000); 7317 } 7318 7319 static void bnx2x_8073_set_pause_cl37(struct link_params *params, 7320 struct bnx2x_phy *phy, 7321 struct link_vars *vars) 7322 { 7323 u16 cl37_val; 7324 struct bnx2x *bp = params->bp; 7325 bnx2x_cl45_read(bp, phy, 7326 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &cl37_val); 7327 7328 cl37_val &= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; 7329 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */ 7330 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); 7331 if ((vars->ieee_fc & 7332 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) == 7333 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) { 7334 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC; 7335 } 7336 if ((vars->ieee_fc & 7337 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) == 7338 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) { 7339 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC; 7340 } 7341 if ((vars->ieee_fc & 7342 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) == 7343 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) { 7344 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; 7345 } 7346 DP(NETIF_MSG_LINK, 7347 "Ext phy AN advertize cl37 0x%x\n", cl37_val); 7348 7349 bnx2x_cl45_write(bp, phy, 7350 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, cl37_val); 7351 msleep(500); 7352 } 7353 7354 static void bnx2x_8073_specific_func(struct bnx2x_phy *phy, 7355 struct link_params *params, 7356 u32 action) 7357 { 7358 struct bnx2x *bp = params->bp; 7359 switch (action) { 7360 case PHY_INIT: 7361 /* Enable LASI */ 7362 bnx2x_cl45_write(bp, phy, 7363 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, (1<<2)); 7364 bnx2x_cl45_write(bp, phy, 7365 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0004); 7366 break; 7367 } 7368 } 7369 7370 static int bnx2x_8073_config_init(struct bnx2x_phy *phy, 7371 struct link_params *params, 7372 struct link_vars *vars) 7373 { 7374 struct bnx2x *bp = params->bp; 7375 u16 val = 0, tmp1; 7376 u8 gpio_port; 7377 DP(NETIF_MSG_LINK, "Init 8073\n"); 7378 7379 if (CHIP_IS_E2(bp)) 7380 gpio_port = BP_PATH(bp); 7381 else 7382 gpio_port = params->port; 7383 /* Restore normal power mode*/ 7384 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 7385 MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port); 7386 7387 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, 7388 MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port); 7389 7390 bnx2x_8073_specific_func(phy, params, PHY_INIT); 7391 bnx2x_8073_set_pause_cl37(params, phy, vars); 7392 7393 bnx2x_cl45_read(bp, phy, 7394 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1); 7395 7396 bnx2x_cl45_read(bp, phy, 7397 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1); 7398 7399 DP(NETIF_MSG_LINK, "Before rom RX_ALARM(port1): 0x%x\n", tmp1); 7400 7401 /* Swap polarity if required - Must be done only in non-1G mode */ 7402 if (params->lane_config & PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) { 7403 /* Configure the 8073 to swap _P and _N of the KR lines */ 7404 DP(NETIF_MSG_LINK, "Swapping polarity for the 8073\n"); 7405 /* 10G Rx/Tx and 1G Tx signal polarity swap */ 7406 bnx2x_cl45_read(bp, phy, 7407 MDIO_PMA_DEVAD, 7408 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL, &val); 7409 bnx2x_cl45_write(bp, phy, 7410 MDIO_PMA_DEVAD, 7411 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL, 7412 (val | (3<<9))); 7413 } 7414 7415 7416 /* Enable CL37 BAM */ 7417 if (REG_RD(bp, params->shmem_base + 7418 offsetof(struct shmem_region, dev_info. 7419 port_hw_config[params->port].default_cfg)) & 7420 PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) { 7421 7422 bnx2x_cl45_read(bp, phy, 7423 MDIO_AN_DEVAD, 7424 MDIO_AN_REG_8073_BAM, &val); 7425 bnx2x_cl45_write(bp, phy, 7426 MDIO_AN_DEVAD, 7427 MDIO_AN_REG_8073_BAM, val | 1); 7428 DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n"); 7429 } 7430 if (params->loopback_mode == LOOPBACK_EXT) { 7431 bnx2x_807x_force_10G(bp, phy); 7432 DP(NETIF_MSG_LINK, "Forced speed 10G on 807X\n"); 7433 return 0; 7434 } else { 7435 bnx2x_cl45_write(bp, phy, 7436 MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0002); 7437 } 7438 if (phy->req_line_speed != SPEED_AUTO_NEG) { 7439 if (phy->req_line_speed == SPEED_10000) { 7440 val = (1<<7); 7441 } else if (phy->req_line_speed == SPEED_2500) { 7442 val = (1<<5); 7443 /* Note that 2.5G works only when used with 1G 7444 * advertisement 7445 */ 7446 } else 7447 val = (1<<5); 7448 } else { 7449 val = 0; 7450 if (phy->speed_cap_mask & 7451 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) 7452 val |= (1<<7); 7453 7454 /* Note that 2.5G works only when used with 1G advertisement */ 7455 if (phy->speed_cap_mask & 7456 (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G | 7457 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) 7458 val |= (1<<5); 7459 DP(NETIF_MSG_LINK, "807x autoneg val = 0x%x\n", val); 7460 } 7461 7462 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val); 7463 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, &tmp1); 7464 7465 if (((phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) && 7466 (phy->req_line_speed == SPEED_AUTO_NEG)) || 7467 (phy->req_line_speed == SPEED_2500)) { 7468 u16 phy_ver; 7469 /* Allow 2.5G for A1 and above */ 7470 bnx2x_cl45_read(bp, phy, 7471 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV, 7472 &phy_ver); 7473 DP(NETIF_MSG_LINK, "Add 2.5G\n"); 7474 if (phy_ver > 0) 7475 tmp1 |= 1; 7476 else 7477 tmp1 &= 0xfffe; 7478 } else { 7479 DP(NETIF_MSG_LINK, "Disable 2.5G\n"); 7480 tmp1 &= 0xfffe; 7481 } 7482 7483 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, tmp1); 7484 /* Add support for CL37 (passive mode) II */ 7485 7486 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &tmp1); 7487 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, 7488 (tmp1 | ((phy->req_duplex == DUPLEX_FULL) ? 7489 0x20 : 0x40))); 7490 7491 /* Add support for CL37 (passive mode) III */ 7492 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000); 7493 7494 /* The SNR will improve about 2db by changing BW and FEE main 7495 * tap. Rest commands are executed after link is up 7496 * Change FFE main cursor to 5 in EDC register 7497 */ 7498 if (bnx2x_8073_is_snr_needed(bp, phy)) 7499 bnx2x_cl45_write(bp, phy, 7500 MDIO_PMA_DEVAD, MDIO_PMA_REG_EDC_FFE_MAIN, 7501 0xFB0C); 7502 7503 /* Enable FEC (Forware Error Correction) Request in the AN */ 7504 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, &tmp1); 7505 tmp1 |= (1<<15); 7506 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, tmp1); 7507 7508 bnx2x_ext_phy_set_pause(params, phy, vars); 7509 7510 /* Restart autoneg */ 7511 msleep(500); 7512 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200); 7513 DP(NETIF_MSG_LINK, "807x Autoneg Restart: Advertise 1G=%x, 10G=%x\n", 7514 ((val & (1<<5)) > 0), ((val & (1<<7)) > 0)); 7515 return 0; 7516 } 7517 7518 static u8 bnx2x_8073_read_status(struct bnx2x_phy *phy, 7519 struct link_params *params, 7520 struct link_vars *vars) 7521 { 7522 struct bnx2x *bp = params->bp; 7523 u8 link_up = 0; 7524 u16 val1, val2; 7525 u16 link_status = 0; 7526 u16 an1000_status = 0; 7527 7528 bnx2x_cl45_read(bp, phy, 7529 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1); 7530 7531 DP(NETIF_MSG_LINK, "8703 LASI status 0x%x\n", val1); 7532 7533 /* Clear the interrupt LASI status register */ 7534 bnx2x_cl45_read(bp, phy, 7535 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2); 7536 bnx2x_cl45_read(bp, phy, 7537 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val1); 7538 DP(NETIF_MSG_LINK, "807x PCS status 0x%x->0x%x\n", val2, val1); 7539 /* Clear MSG-OUT */ 7540 bnx2x_cl45_read(bp, phy, 7541 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1); 7542 7543 /* Check the LASI */ 7544 bnx2x_cl45_read(bp, phy, 7545 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2); 7546 7547 DP(NETIF_MSG_LINK, "KR 0x9003 0x%x\n", val2); 7548 7549 /* Check the link status */ 7550 bnx2x_cl45_read(bp, phy, 7551 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2); 7552 DP(NETIF_MSG_LINK, "KR PCS status 0x%x\n", val2); 7553 7554 bnx2x_cl45_read(bp, phy, 7555 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2); 7556 bnx2x_cl45_read(bp, phy, 7557 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1); 7558 link_up = ((val1 & 4) == 4); 7559 DP(NETIF_MSG_LINK, "PMA_REG_STATUS=0x%x\n", val1); 7560 7561 if (link_up && 7562 ((phy->req_line_speed != SPEED_10000))) { 7563 if (bnx2x_8073_xaui_wa(bp, phy) != 0) 7564 return 0; 7565 } 7566 bnx2x_cl45_read(bp, phy, 7567 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status); 7568 bnx2x_cl45_read(bp, phy, 7569 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status); 7570 7571 /* Check the link status on 1.1.2 */ 7572 bnx2x_cl45_read(bp, phy, 7573 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2); 7574 bnx2x_cl45_read(bp, phy, 7575 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1); 7576 DP(NETIF_MSG_LINK, "KR PMA status 0x%x->0x%x," 7577 "an_link_status=0x%x\n", val2, val1, an1000_status); 7578 7579 link_up = (((val1 & 4) == 4) || (an1000_status & (1<<1))); 7580 if (link_up && bnx2x_8073_is_snr_needed(bp, phy)) { 7581 /* The SNR will improve about 2dbby changing the BW and FEE main 7582 * tap. The 1st write to change FFE main tap is set before 7583 * restart AN. Change PLL Bandwidth in EDC register 7584 */ 7585 bnx2x_cl45_write(bp, phy, 7586 MDIO_PMA_DEVAD, MDIO_PMA_REG_PLL_BANDWIDTH, 7587 0x26BC); 7588 7589 /* Change CDR Bandwidth in EDC register */ 7590 bnx2x_cl45_write(bp, phy, 7591 MDIO_PMA_DEVAD, MDIO_PMA_REG_CDR_BANDWIDTH, 7592 0x0333); 7593 } 7594 bnx2x_cl45_read(bp, phy, 7595 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_SPEED_LINK_STATUS, 7596 &link_status); 7597 7598 /* Bits 0..2 --> speed detected, bits 13..15--> link is down */ 7599 if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) { 7600 link_up = 1; 7601 vars->line_speed = SPEED_10000; 7602 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n", 7603 params->port); 7604 } else if ((link_status & (1<<1)) && (!(link_status & (1<<14)))) { 7605 link_up = 1; 7606 vars->line_speed = SPEED_2500; 7607 DP(NETIF_MSG_LINK, "port %x: External link up in 2.5G\n", 7608 params->port); 7609 } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) { 7610 link_up = 1; 7611 vars->line_speed = SPEED_1000; 7612 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n", 7613 params->port); 7614 } else { 7615 link_up = 0; 7616 DP(NETIF_MSG_LINK, "port %x: External link is down\n", 7617 params->port); 7618 } 7619 7620 if (link_up) { 7621 /* Swap polarity if required */ 7622 if (params->lane_config & 7623 PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) { 7624 /* Configure the 8073 to swap P and N of the KR lines */ 7625 bnx2x_cl45_read(bp, phy, 7626 MDIO_XS_DEVAD, 7627 MDIO_XS_REG_8073_RX_CTRL_PCIE, &val1); 7628 /* Set bit 3 to invert Rx in 1G mode and clear this bit 7629 * when it`s in 10G mode. 7630 */ 7631 if (vars->line_speed == SPEED_1000) { 7632 DP(NETIF_MSG_LINK, "Swapping 1G polarity for" 7633 "the 8073\n"); 7634 val1 |= (1<<3); 7635 } else 7636 val1 &= ~(1<<3); 7637 7638 bnx2x_cl45_write(bp, phy, 7639 MDIO_XS_DEVAD, 7640 MDIO_XS_REG_8073_RX_CTRL_PCIE, 7641 val1); 7642 } 7643 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars); 7644 bnx2x_8073_resolve_fc(phy, params, vars); 7645 vars->duplex = DUPLEX_FULL; 7646 } 7647 7648 if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) { 7649 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, 7650 MDIO_AN_REG_LP_AUTO_NEG2, &val1); 7651 7652 if (val1 & (1<<5)) 7653 vars->link_status |= 7654 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; 7655 if (val1 & (1<<7)) 7656 vars->link_status |= 7657 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; 7658 } 7659 7660 return link_up; 7661 } 7662 7663 static void bnx2x_8073_link_reset(struct bnx2x_phy *phy, 7664 struct link_params *params) 7665 { 7666 struct bnx2x *bp = params->bp; 7667 u8 gpio_port; 7668 if (CHIP_IS_E2(bp)) 7669 gpio_port = BP_PATH(bp); 7670 else 7671 gpio_port = params->port; 7672 DP(NETIF_MSG_LINK, "Setting 8073 port %d into low power mode\n", 7673 gpio_port); 7674 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 7675 MISC_REGISTERS_GPIO_OUTPUT_LOW, 7676 gpio_port); 7677 } 7678 7679 /******************************************************************/ 7680 /* BCM8705 PHY SECTION */ 7681 /******************************************************************/ 7682 static int bnx2x_8705_config_init(struct bnx2x_phy *phy, 7683 struct link_params *params, 7684 struct link_vars *vars) 7685 { 7686 struct bnx2x *bp = params->bp; 7687 DP(NETIF_MSG_LINK, "init 8705\n"); 7688 /* Restore normal power mode*/ 7689 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 7690 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); 7691 /* HW reset */ 7692 bnx2x_ext_phy_hw_reset(bp, params->port); 7693 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040); 7694 bnx2x_wait_reset_complete(bp, phy, params); 7695 7696 bnx2x_cl45_write(bp, phy, 7697 MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL, 0x8288); 7698 bnx2x_cl45_write(bp, phy, 7699 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 0x7fbf); 7700 bnx2x_cl45_write(bp, phy, 7701 MDIO_PMA_DEVAD, MDIO_PMA_REG_CMU_PLL_BYPASS, 0x0100); 7702 bnx2x_cl45_write(bp, phy, 7703 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_CNTL, 0x1); 7704 /* BCM8705 doesn't have microcode, hence the 0 */ 7705 bnx2x_save_spirom_version(bp, params->port, params->shmem_base, 0); 7706 return 0; 7707 } 7708 7709 static u8 bnx2x_8705_read_status(struct bnx2x_phy *phy, 7710 struct link_params *params, 7711 struct link_vars *vars) 7712 { 7713 u8 link_up = 0; 7714 u16 val1, rx_sd; 7715 struct bnx2x *bp = params->bp; 7716 DP(NETIF_MSG_LINK, "read status 8705\n"); 7717 bnx2x_cl45_read(bp, phy, 7718 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1); 7719 DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1); 7720 7721 bnx2x_cl45_read(bp, phy, 7722 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1); 7723 DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1); 7724 7725 bnx2x_cl45_read(bp, phy, 7726 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd); 7727 7728 bnx2x_cl45_read(bp, phy, 7729 MDIO_PMA_DEVAD, 0xc809, &val1); 7730 bnx2x_cl45_read(bp, phy, 7731 MDIO_PMA_DEVAD, 0xc809, &val1); 7732 7733 DP(NETIF_MSG_LINK, "8705 1.c809 val=0x%x\n", val1); 7734 link_up = ((rx_sd & 0x1) && (val1 & (1<<9)) && ((val1 & (1<<8)) == 0)); 7735 if (link_up) { 7736 vars->line_speed = SPEED_10000; 7737 bnx2x_ext_phy_resolve_fc(phy, params, vars); 7738 } 7739 return link_up; 7740 } 7741 7742 /******************************************************************/ 7743 /* SFP+ module Section */ 7744 /******************************************************************/ 7745 static void bnx2x_set_disable_pmd_transmit(struct link_params *params, 7746 struct bnx2x_phy *phy, 7747 u8 pmd_dis) 7748 { 7749 struct bnx2x *bp = params->bp; 7750 /* Disable transmitter only for bootcodes which can enable it afterwards 7751 * (for D3 link) 7752 */ 7753 if (pmd_dis) { 7754 if (params->feature_config_flags & 7755 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED) 7756 DP(NETIF_MSG_LINK, "Disabling PMD transmitter\n"); 7757 else { 7758 DP(NETIF_MSG_LINK, "NOT disabling PMD transmitter\n"); 7759 return; 7760 } 7761 } else 7762 DP(NETIF_MSG_LINK, "Enabling PMD transmitter\n"); 7763 bnx2x_cl45_write(bp, phy, 7764 MDIO_PMA_DEVAD, 7765 MDIO_PMA_REG_TX_DISABLE, pmd_dis); 7766 } 7767 7768 static u8 bnx2x_get_gpio_port(struct link_params *params) 7769 { 7770 u8 gpio_port; 7771 u32 swap_val, swap_override; 7772 struct bnx2x *bp = params->bp; 7773 if (CHIP_IS_E2(bp)) 7774 gpio_port = BP_PATH(bp); 7775 else 7776 gpio_port = params->port; 7777 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); 7778 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); 7779 return gpio_port ^ (swap_val && swap_override); 7780 } 7781 7782 static void bnx2x_sfp_e1e2_set_transmitter(struct link_params *params, 7783 struct bnx2x_phy *phy, 7784 u8 tx_en) 7785 { 7786 u16 val; 7787 u8 port = params->port; 7788 struct bnx2x *bp = params->bp; 7789 u32 tx_en_mode; 7790 7791 /* Disable/Enable transmitter ( TX laser of the SFP+ module.)*/ 7792 tx_en_mode = REG_RD(bp, params->shmem_base + 7793 offsetof(struct shmem_region, 7794 dev_info.port_hw_config[port].sfp_ctrl)) & 7795 PORT_HW_CFG_TX_LASER_MASK; 7796 DP(NETIF_MSG_LINK, "Setting transmitter tx_en=%x for port %x " 7797 "mode = %x\n", tx_en, port, tx_en_mode); 7798 switch (tx_en_mode) { 7799 case PORT_HW_CFG_TX_LASER_MDIO: 7800 7801 bnx2x_cl45_read(bp, phy, 7802 MDIO_PMA_DEVAD, 7803 MDIO_PMA_REG_PHY_IDENTIFIER, 7804 &val); 7805 7806 if (tx_en) 7807 val &= ~(1<<15); 7808 else 7809 val |= (1<<15); 7810 7811 bnx2x_cl45_write(bp, phy, 7812 MDIO_PMA_DEVAD, 7813 MDIO_PMA_REG_PHY_IDENTIFIER, 7814 val); 7815 break; 7816 case PORT_HW_CFG_TX_LASER_GPIO0: 7817 case PORT_HW_CFG_TX_LASER_GPIO1: 7818 case PORT_HW_CFG_TX_LASER_GPIO2: 7819 case PORT_HW_CFG_TX_LASER_GPIO3: 7820 { 7821 u16 gpio_pin; 7822 u8 gpio_port, gpio_mode; 7823 if (tx_en) 7824 gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_HIGH; 7825 else 7826 gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_LOW; 7827 7828 gpio_pin = tx_en_mode - PORT_HW_CFG_TX_LASER_GPIO0; 7829 gpio_port = bnx2x_get_gpio_port(params); 7830 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port); 7831 break; 7832 } 7833 default: 7834 DP(NETIF_MSG_LINK, "Invalid TX_LASER_MDIO 0x%x\n", tx_en_mode); 7835 break; 7836 } 7837 } 7838 7839 static void bnx2x_sfp_set_transmitter(struct link_params *params, 7840 struct bnx2x_phy *phy, 7841 u8 tx_en) 7842 { 7843 struct bnx2x *bp = params->bp; 7844 DP(NETIF_MSG_LINK, "Setting SFP+ transmitter to %d\n", tx_en); 7845 if (CHIP_IS_E3(bp)) 7846 bnx2x_sfp_e3_set_transmitter(params, phy, tx_en); 7847 else 7848 bnx2x_sfp_e1e2_set_transmitter(params, phy, tx_en); 7849 } 7850 7851 static int bnx2x_8726_read_sfp_module_eeprom(struct bnx2x_phy *phy, 7852 struct link_params *params, 7853 u8 dev_addr, u16 addr, u8 byte_cnt, 7854 u8 *o_buf, u8 is_init) 7855 { 7856 struct bnx2x *bp = params->bp; 7857 u16 val = 0; 7858 u16 i; 7859 if (byte_cnt > SFP_EEPROM_PAGE_SIZE) { 7860 DP(NETIF_MSG_LINK, 7861 "Reading from eeprom is limited to 0xf\n"); 7862 return -EINVAL; 7863 } 7864 /* Set the read command byte count */ 7865 bnx2x_cl45_write(bp, phy, 7866 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT, 7867 (byte_cnt | (dev_addr << 8))); 7868 7869 /* Set the read command address */ 7870 bnx2x_cl45_write(bp, phy, 7871 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR, 7872 addr); 7873 7874 /* Activate read command */ 7875 bnx2x_cl45_write(bp, phy, 7876 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, 7877 0x2c0f); 7878 7879 /* Wait up to 500us for command complete status */ 7880 for (i = 0; i < 100; i++) { 7881 bnx2x_cl45_read(bp, phy, 7882 MDIO_PMA_DEVAD, 7883 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); 7884 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == 7885 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) 7886 break; 7887 udelay(5); 7888 } 7889 7890 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) != 7891 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) { 7892 DP(NETIF_MSG_LINK, 7893 "Got bad status 0x%x when reading from SFP+ EEPROM\n", 7894 (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK)); 7895 return -EINVAL; 7896 } 7897 7898 /* Read the buffer */ 7899 for (i = 0; i < byte_cnt; i++) { 7900 bnx2x_cl45_read(bp, phy, 7901 MDIO_PMA_DEVAD, 7902 MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i, &val); 7903 o_buf[i] = (u8)(val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK); 7904 } 7905 7906 for (i = 0; i < 100; i++) { 7907 bnx2x_cl45_read(bp, phy, 7908 MDIO_PMA_DEVAD, 7909 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); 7910 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == 7911 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE) 7912 return 0; 7913 usleep_range(1000, 2000); 7914 } 7915 return -EINVAL; 7916 } 7917 7918 static void bnx2x_warpcore_power_module(struct link_params *params, 7919 u8 power) 7920 { 7921 u32 pin_cfg; 7922 struct bnx2x *bp = params->bp; 7923 7924 pin_cfg = (REG_RD(bp, params->shmem_base + 7925 offsetof(struct shmem_region, 7926 dev_info.port_hw_config[params->port].e3_sfp_ctrl)) & 7927 PORT_HW_CFG_E3_PWR_DIS_MASK) >> 7928 PORT_HW_CFG_E3_PWR_DIS_SHIFT; 7929 7930 if (pin_cfg == PIN_CFG_NA) 7931 return; 7932 DP(NETIF_MSG_LINK, "Setting SFP+ module power to %d using pin cfg %d\n", 7933 power, pin_cfg); 7934 /* Low ==> corresponding SFP+ module is powered 7935 * high ==> the SFP+ module is powered down 7936 */ 7937 bnx2x_set_cfg_pin(bp, pin_cfg, power ^ 1); 7938 } 7939 static int bnx2x_warpcore_read_sfp_module_eeprom(struct bnx2x_phy *phy, 7940 struct link_params *params, 7941 u8 dev_addr, 7942 u16 addr, u8 byte_cnt, 7943 u8 *o_buf, u8 is_init) 7944 { 7945 int rc = 0; 7946 u8 i, j = 0, cnt = 0; 7947 u32 data_array[4]; 7948 u16 addr32; 7949 struct bnx2x *bp = params->bp; 7950 7951 if (byte_cnt > SFP_EEPROM_PAGE_SIZE) { 7952 DP(NETIF_MSG_LINK, 7953 "Reading from eeprom is limited to 16 bytes\n"); 7954 return -EINVAL; 7955 } 7956 7957 /* 4 byte aligned address */ 7958 addr32 = addr & (~0x3); 7959 do { 7960 if ((!is_init) && (cnt == I2C_WA_PWR_ITER)) { 7961 bnx2x_warpcore_power_module(params, 0); 7962 /* Note that 100us are not enough here */ 7963 usleep_range(1000, 2000); 7964 bnx2x_warpcore_power_module(params, 1); 7965 } 7966 rc = bnx2x_bsc_read(params, bp, dev_addr, addr32, 0, byte_cnt, 7967 data_array); 7968 } while ((rc != 0) && (++cnt < I2C_WA_RETRY_CNT)); 7969 7970 if (rc == 0) { 7971 for (i = (addr - addr32); i < byte_cnt + (addr - addr32); i++) { 7972 o_buf[j] = *((u8 *)data_array + i); 7973 j++; 7974 } 7975 } 7976 7977 return rc; 7978 } 7979 7980 static int bnx2x_8727_read_sfp_module_eeprom(struct bnx2x_phy *phy, 7981 struct link_params *params, 7982 u8 dev_addr, u16 addr, u8 byte_cnt, 7983 u8 *o_buf, u8 is_init) 7984 { 7985 struct bnx2x *bp = params->bp; 7986 u16 val, i; 7987 7988 if (byte_cnt > SFP_EEPROM_PAGE_SIZE) { 7989 DP(NETIF_MSG_LINK, 7990 "Reading from eeprom is limited to 0xf\n"); 7991 return -EINVAL; 7992 } 7993 7994 /* Set 2-wire transfer rate of SFP+ module EEPROM 7995 * to 100Khz since some DACs(direct attached cables) do 7996 * not work at 400Khz. 7997 */ 7998 bnx2x_cl45_write(bp, phy, 7999 MDIO_PMA_DEVAD, 8000 MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR, 8001 ((dev_addr << 8) | 1)); 8002 8003 /* Need to read from 1.8000 to clear it */ 8004 bnx2x_cl45_read(bp, phy, 8005 MDIO_PMA_DEVAD, 8006 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, 8007 &val); 8008 8009 /* Set the read command byte count */ 8010 bnx2x_cl45_write(bp, phy, 8011 MDIO_PMA_DEVAD, 8012 MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT, 8013 ((byte_cnt < 2) ? 2 : byte_cnt)); 8014 8015 /* Set the read command address */ 8016 bnx2x_cl45_write(bp, phy, 8017 MDIO_PMA_DEVAD, 8018 MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR, 8019 addr); 8020 /* Set the destination address */ 8021 bnx2x_cl45_write(bp, phy, 8022 MDIO_PMA_DEVAD, 8023 0x8004, 8024 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF); 8025 8026 /* Activate read command */ 8027 bnx2x_cl45_write(bp, phy, 8028 MDIO_PMA_DEVAD, 8029 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, 8030 0x8002); 8031 /* Wait appropriate time for two-wire command to finish before 8032 * polling the status register 8033 */ 8034 usleep_range(1000, 2000); 8035 8036 /* Wait up to 500us for command complete status */ 8037 for (i = 0; i < 100; i++) { 8038 bnx2x_cl45_read(bp, phy, 8039 MDIO_PMA_DEVAD, 8040 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); 8041 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == 8042 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) 8043 break; 8044 udelay(5); 8045 } 8046 8047 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) != 8048 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) { 8049 DP(NETIF_MSG_LINK, 8050 "Got bad status 0x%x when reading from SFP+ EEPROM\n", 8051 (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK)); 8052 return -EFAULT; 8053 } 8054 8055 /* Read the buffer */ 8056 for (i = 0; i < byte_cnt; i++) { 8057 bnx2x_cl45_read(bp, phy, 8058 MDIO_PMA_DEVAD, 8059 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF + i, &val); 8060 o_buf[i] = (u8)(val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK); 8061 } 8062 8063 for (i = 0; i < 100; i++) { 8064 bnx2x_cl45_read(bp, phy, 8065 MDIO_PMA_DEVAD, 8066 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); 8067 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == 8068 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE) 8069 return 0; 8070 usleep_range(1000, 2000); 8071 } 8072 8073 return -EINVAL; 8074 } 8075 int bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy, 8076 struct link_params *params, u8 dev_addr, 8077 u16 addr, u16 byte_cnt, u8 *o_buf) 8078 { 8079 int rc = 0; 8080 struct bnx2x *bp = params->bp; 8081 u8 xfer_size; 8082 u8 *user_data = o_buf; 8083 read_sfp_module_eeprom_func_p read_func; 8084 8085 if ((dev_addr != 0xa0) && (dev_addr != 0xa2)) { 8086 DP(NETIF_MSG_LINK, "invalid dev_addr 0x%x\n", dev_addr); 8087 return -EINVAL; 8088 } 8089 8090 switch (phy->type) { 8091 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: 8092 read_func = bnx2x_8726_read_sfp_module_eeprom; 8093 break; 8094 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: 8095 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722: 8096 read_func = bnx2x_8727_read_sfp_module_eeprom; 8097 break; 8098 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT: 8099 read_func = bnx2x_warpcore_read_sfp_module_eeprom; 8100 break; 8101 default: 8102 return -EOPNOTSUPP; 8103 } 8104 8105 while (!rc && (byte_cnt > 0)) { 8106 xfer_size = (byte_cnt > SFP_EEPROM_PAGE_SIZE) ? 8107 SFP_EEPROM_PAGE_SIZE : byte_cnt; 8108 rc = read_func(phy, params, dev_addr, addr, xfer_size, 8109 user_data, 0); 8110 byte_cnt -= xfer_size; 8111 user_data += xfer_size; 8112 addr += xfer_size; 8113 } 8114 return rc; 8115 } 8116 8117 static int bnx2x_get_edc_mode(struct bnx2x_phy *phy, 8118 struct link_params *params, 8119 u16 *edc_mode) 8120 { 8121 struct bnx2x *bp = params->bp; 8122 u32 sync_offset = 0, phy_idx, media_types; 8123 u8 val[SFP_EEPROM_FC_TX_TECH_ADDR + 1], check_limiting_mode = 0; 8124 *edc_mode = EDC_MODE_LIMITING; 8125 phy->media_type = ETH_PHY_UNSPECIFIED; 8126 /* First check for copper cable */ 8127 if (bnx2x_read_sfp_module_eeprom(phy, 8128 params, 8129 I2C_DEV_ADDR_A0, 8130 0, 8131 SFP_EEPROM_FC_TX_TECH_ADDR + 1, 8132 (u8 *)val) != 0) { 8133 DP(NETIF_MSG_LINK, "Failed to read from SFP+ module EEPROM\n"); 8134 return -EINVAL; 8135 } 8136 params->link_attr_sync &= ~LINK_SFP_EEPROM_COMP_CODE_MASK; 8137 params->link_attr_sync |= val[SFP_EEPROM_10G_COMP_CODE_ADDR] << 8138 LINK_SFP_EEPROM_COMP_CODE_SHIFT; 8139 bnx2x_update_link_attr(params, params->link_attr_sync); 8140 switch (val[SFP_EEPROM_CON_TYPE_ADDR]) { 8141 case SFP_EEPROM_CON_TYPE_VAL_COPPER: 8142 { 8143 u8 copper_module_type; 8144 phy->media_type = ETH_PHY_DA_TWINAX; 8145 /* Check if its active cable (includes SFP+ module) 8146 * of passive cable 8147 */ 8148 copper_module_type = val[SFP_EEPROM_FC_TX_TECH_ADDR]; 8149 8150 if (copper_module_type & 8151 SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) { 8152 DP(NETIF_MSG_LINK, "Active Copper cable detected\n"); 8153 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) 8154 *edc_mode = EDC_MODE_ACTIVE_DAC; 8155 else 8156 check_limiting_mode = 1; 8157 } else { 8158 *edc_mode = EDC_MODE_PASSIVE_DAC; 8159 /* Even in case PASSIVE_DAC indication is not set, 8160 * treat it as a passive DAC cable, since some cables 8161 * don't have this indication. 8162 */ 8163 if (copper_module_type & 8164 SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE) { 8165 DP(NETIF_MSG_LINK, 8166 "Passive Copper cable detected\n"); 8167 } else { 8168 DP(NETIF_MSG_LINK, 8169 "Unknown copper-cable-type\n"); 8170 } 8171 } 8172 break; 8173 } 8174 case SFP_EEPROM_CON_TYPE_VAL_UNKNOWN: 8175 case SFP_EEPROM_CON_TYPE_VAL_LC: 8176 case SFP_EEPROM_CON_TYPE_VAL_RJ45: 8177 check_limiting_mode = 1; 8178 if (((val[SFP_EEPROM_10G_COMP_CODE_ADDR] & 8179 (SFP_EEPROM_10G_COMP_CODE_SR_MASK | 8180 SFP_EEPROM_10G_COMP_CODE_LR_MASK | 8181 SFP_EEPROM_10G_COMP_CODE_LRM_MASK)) == 0) && 8182 (val[SFP_EEPROM_1G_COMP_CODE_ADDR] != 0)) { 8183 DP(NETIF_MSG_LINK, "1G SFP module detected\n"); 8184 phy->media_type = ETH_PHY_SFP_1G_FIBER; 8185 if (phy->req_line_speed != SPEED_1000) { 8186 u8 gport = params->port; 8187 phy->req_line_speed = SPEED_1000; 8188 if (!CHIP_IS_E1x(bp)) { 8189 gport = BP_PATH(bp) + 8190 (params->port << 1); 8191 } 8192 netdev_err(bp->dev, 8193 "Warning: Link speed was forced to 1000Mbps. Current SFP module in port %d is not compliant with 10G Ethernet\n", 8194 gport); 8195 } 8196 if (val[SFP_EEPROM_1G_COMP_CODE_ADDR] & 8197 SFP_EEPROM_1G_COMP_CODE_BASE_T) { 8198 bnx2x_sfp_set_transmitter(params, phy, 0); 8199 msleep(40); 8200 bnx2x_sfp_set_transmitter(params, phy, 1); 8201 } 8202 } else { 8203 int idx, cfg_idx = 0; 8204 DP(NETIF_MSG_LINK, "10G Optic module detected\n"); 8205 for (idx = INT_PHY; idx < MAX_PHYS; idx++) { 8206 if (params->phy[idx].type == phy->type) { 8207 cfg_idx = LINK_CONFIG_IDX(idx); 8208 break; 8209 } 8210 } 8211 phy->media_type = ETH_PHY_SFPP_10G_FIBER; 8212 phy->req_line_speed = params->req_line_speed[cfg_idx]; 8213 } 8214 break; 8215 default: 8216 DP(NETIF_MSG_LINK, "Unable to determine module type 0x%x !!!\n", 8217 val[SFP_EEPROM_CON_TYPE_ADDR]); 8218 return -EINVAL; 8219 } 8220 sync_offset = params->shmem_base + 8221 offsetof(struct shmem_region, 8222 dev_info.port_hw_config[params->port].media_type); 8223 media_types = REG_RD(bp, sync_offset); 8224 /* Update media type for non-PMF sync */ 8225 for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) { 8226 if (&(params->phy[phy_idx]) == phy) { 8227 media_types &= ~(PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK << 8228 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx)); 8229 media_types |= ((phy->media_type & 8230 PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) << 8231 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx)); 8232 break; 8233 } 8234 } 8235 REG_WR(bp, sync_offset, media_types); 8236 if (check_limiting_mode) { 8237 u8 options[SFP_EEPROM_OPTIONS_SIZE]; 8238 if (bnx2x_read_sfp_module_eeprom(phy, 8239 params, 8240 I2C_DEV_ADDR_A0, 8241 SFP_EEPROM_OPTIONS_ADDR, 8242 SFP_EEPROM_OPTIONS_SIZE, 8243 options) != 0) { 8244 DP(NETIF_MSG_LINK, 8245 "Failed to read Option field from module EEPROM\n"); 8246 return -EINVAL; 8247 } 8248 if ((options[0] & SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK)) 8249 *edc_mode = EDC_MODE_LINEAR; 8250 else 8251 *edc_mode = EDC_MODE_LIMITING; 8252 } 8253 DP(NETIF_MSG_LINK, "EDC mode is set to 0x%x\n", *edc_mode); 8254 return 0; 8255 } 8256 /* This function read the relevant field from the module (SFP+), and verify it 8257 * is compliant with this board 8258 */ 8259 static int bnx2x_verify_sfp_module(struct bnx2x_phy *phy, 8260 struct link_params *params) 8261 { 8262 struct bnx2x *bp = params->bp; 8263 u32 val, cmd; 8264 u32 fw_resp, fw_cmd_param; 8265 char vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE+1]; 8266 char vendor_pn[SFP_EEPROM_PART_NO_SIZE+1]; 8267 phy->flags &= ~FLAGS_SFP_NOT_APPROVED; 8268 val = REG_RD(bp, params->shmem_base + 8269 offsetof(struct shmem_region, dev_info. 8270 port_feature_config[params->port].config)); 8271 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == 8272 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT) { 8273 DP(NETIF_MSG_LINK, "NOT enforcing module verification\n"); 8274 return 0; 8275 } 8276 8277 if (params->feature_config_flags & 8278 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY) { 8279 /* Use specific phy request */ 8280 cmd = DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL; 8281 } else if (params->feature_config_flags & 8282 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY) { 8283 /* Use first phy request only in case of non-dual media*/ 8284 if (DUAL_MEDIA(params)) { 8285 DP(NETIF_MSG_LINK, 8286 "FW does not support OPT MDL verification\n"); 8287 return -EINVAL; 8288 } 8289 cmd = DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL; 8290 } else { 8291 /* No support in OPT MDL detection */ 8292 DP(NETIF_MSG_LINK, 8293 "FW does not support OPT MDL verification\n"); 8294 return -EINVAL; 8295 } 8296 8297 fw_cmd_param = FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl); 8298 fw_resp = bnx2x_fw_command(bp, cmd, fw_cmd_param); 8299 if (fw_resp == FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS) { 8300 DP(NETIF_MSG_LINK, "Approved module\n"); 8301 return 0; 8302 } 8303 8304 /* Format the warning message */ 8305 if (bnx2x_read_sfp_module_eeprom(phy, 8306 params, 8307 I2C_DEV_ADDR_A0, 8308 SFP_EEPROM_VENDOR_NAME_ADDR, 8309 SFP_EEPROM_VENDOR_NAME_SIZE, 8310 (u8 *)vendor_name)) 8311 vendor_name[0] = '\0'; 8312 else 8313 vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE] = '\0'; 8314 if (bnx2x_read_sfp_module_eeprom(phy, 8315 params, 8316 I2C_DEV_ADDR_A0, 8317 SFP_EEPROM_PART_NO_ADDR, 8318 SFP_EEPROM_PART_NO_SIZE, 8319 (u8 *)vendor_pn)) 8320 vendor_pn[0] = '\0'; 8321 else 8322 vendor_pn[SFP_EEPROM_PART_NO_SIZE] = '\0'; 8323 8324 netdev_err(bp->dev, "Warning: Unqualified SFP+ module detected," 8325 " Port %d from %s part number %s\n", 8326 params->port, vendor_name, vendor_pn); 8327 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) != 8328 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG) 8329 phy->flags |= FLAGS_SFP_NOT_APPROVED; 8330 return -EINVAL; 8331 } 8332 8333 static int bnx2x_wait_for_sfp_module_initialized(struct bnx2x_phy *phy, 8334 struct link_params *params) 8335 8336 { 8337 u8 val; 8338 int rc; 8339 struct bnx2x *bp = params->bp; 8340 u16 timeout; 8341 /* Initialization time after hot-plug may take up to 300ms for 8342 * some phys type ( e.g. JDSU ) 8343 */ 8344 8345 for (timeout = 0; timeout < 60; timeout++) { 8346 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) 8347 rc = bnx2x_warpcore_read_sfp_module_eeprom( 8348 phy, params, I2C_DEV_ADDR_A0, 1, 1, &val, 8349 1); 8350 else 8351 rc = bnx2x_read_sfp_module_eeprom(phy, params, 8352 I2C_DEV_ADDR_A0, 8353 1, 1, &val); 8354 if (rc == 0) { 8355 DP(NETIF_MSG_LINK, 8356 "SFP+ module initialization took %d ms\n", 8357 timeout * 5); 8358 return 0; 8359 } 8360 usleep_range(5000, 10000); 8361 } 8362 rc = bnx2x_read_sfp_module_eeprom(phy, params, I2C_DEV_ADDR_A0, 8363 1, 1, &val); 8364 return rc; 8365 } 8366 8367 static void bnx2x_8727_power_module(struct bnx2x *bp, 8368 struct bnx2x_phy *phy, 8369 u8 is_power_up) { 8370 /* Make sure GPIOs are not using for LED mode */ 8371 u16 val; 8372 /* In the GPIO register, bit 4 is use to determine if the GPIOs are 8373 * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for 8374 * output 8375 * Bits 0-1 determine the GPIOs value for OUTPUT in case bit 4 val is 0 8376 * Bits 8-9 determine the GPIOs value for INPUT in case bit 4 val is 1 8377 * where the 1st bit is the over-current(only input), and 2nd bit is 8378 * for power( only output ) 8379 * 8380 * In case of NOC feature is disabled and power is up, set GPIO control 8381 * as input to enable listening of over-current indication 8382 */ 8383 if (phy->flags & FLAGS_NOC) 8384 return; 8385 if (is_power_up) 8386 val = (1<<4); 8387 else 8388 /* Set GPIO control to OUTPUT, and set the power bit 8389 * to according to the is_power_up 8390 */ 8391 val = (1<<1); 8392 8393 bnx2x_cl45_write(bp, phy, 8394 MDIO_PMA_DEVAD, 8395 MDIO_PMA_REG_8727_GPIO_CTRL, 8396 val); 8397 } 8398 8399 static int bnx2x_8726_set_limiting_mode(struct bnx2x *bp, 8400 struct bnx2x_phy *phy, 8401 u16 edc_mode) 8402 { 8403 u16 cur_limiting_mode; 8404 8405 bnx2x_cl45_read(bp, phy, 8406 MDIO_PMA_DEVAD, 8407 MDIO_PMA_REG_ROM_VER2, 8408 &cur_limiting_mode); 8409 DP(NETIF_MSG_LINK, "Current Limiting mode is 0x%x\n", 8410 cur_limiting_mode); 8411 8412 if (edc_mode == EDC_MODE_LIMITING) { 8413 DP(NETIF_MSG_LINK, "Setting LIMITING MODE\n"); 8414 bnx2x_cl45_write(bp, phy, 8415 MDIO_PMA_DEVAD, 8416 MDIO_PMA_REG_ROM_VER2, 8417 EDC_MODE_LIMITING); 8418 } else { /* LRM mode ( default )*/ 8419 8420 DP(NETIF_MSG_LINK, "Setting LRM MODE\n"); 8421 8422 /* Changing to LRM mode takes quite few seconds. So do it only 8423 * if current mode is limiting (default is LRM) 8424 */ 8425 if (cur_limiting_mode != EDC_MODE_LIMITING) 8426 return 0; 8427 8428 bnx2x_cl45_write(bp, phy, 8429 MDIO_PMA_DEVAD, 8430 MDIO_PMA_REG_LRM_MODE, 8431 0); 8432 bnx2x_cl45_write(bp, phy, 8433 MDIO_PMA_DEVAD, 8434 MDIO_PMA_REG_ROM_VER2, 8435 0x128); 8436 bnx2x_cl45_write(bp, phy, 8437 MDIO_PMA_DEVAD, 8438 MDIO_PMA_REG_MISC_CTRL0, 8439 0x4008); 8440 bnx2x_cl45_write(bp, phy, 8441 MDIO_PMA_DEVAD, 8442 MDIO_PMA_REG_LRM_MODE, 8443 0xaaaa); 8444 } 8445 return 0; 8446 } 8447 8448 static int bnx2x_8727_set_limiting_mode(struct bnx2x *bp, 8449 struct bnx2x_phy *phy, 8450 u16 edc_mode) 8451 { 8452 u16 phy_identifier; 8453 u16 rom_ver2_val; 8454 bnx2x_cl45_read(bp, phy, 8455 MDIO_PMA_DEVAD, 8456 MDIO_PMA_REG_PHY_IDENTIFIER, 8457 &phy_identifier); 8458 8459 bnx2x_cl45_write(bp, phy, 8460 MDIO_PMA_DEVAD, 8461 MDIO_PMA_REG_PHY_IDENTIFIER, 8462 (phy_identifier & ~(1<<9))); 8463 8464 bnx2x_cl45_read(bp, phy, 8465 MDIO_PMA_DEVAD, 8466 MDIO_PMA_REG_ROM_VER2, 8467 &rom_ver2_val); 8468 /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */ 8469 bnx2x_cl45_write(bp, phy, 8470 MDIO_PMA_DEVAD, 8471 MDIO_PMA_REG_ROM_VER2, 8472 (rom_ver2_val & 0xff00) | (edc_mode & 0x00ff)); 8473 8474 bnx2x_cl45_write(bp, phy, 8475 MDIO_PMA_DEVAD, 8476 MDIO_PMA_REG_PHY_IDENTIFIER, 8477 (phy_identifier | (1<<9))); 8478 8479 return 0; 8480 } 8481 8482 static void bnx2x_8727_specific_func(struct bnx2x_phy *phy, 8483 struct link_params *params, 8484 u32 action) 8485 { 8486 struct bnx2x *bp = params->bp; 8487 u16 val; 8488 switch (action) { 8489 case DISABLE_TX: 8490 bnx2x_sfp_set_transmitter(params, phy, 0); 8491 break; 8492 case ENABLE_TX: 8493 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED)) 8494 bnx2x_sfp_set_transmitter(params, phy, 1); 8495 break; 8496 case PHY_INIT: 8497 bnx2x_cl45_write(bp, phy, 8498 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, 8499 (1<<2) | (1<<5)); 8500 bnx2x_cl45_write(bp, phy, 8501 MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL, 8502 0); 8503 bnx2x_cl45_write(bp, phy, 8504 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0006); 8505 /* Make MOD_ABS give interrupt on change */ 8506 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 8507 MDIO_PMA_REG_8727_PCS_OPT_CTRL, 8508 &val); 8509 val |= (1<<12); 8510 if (phy->flags & FLAGS_NOC) 8511 val |= (3<<5); 8512 /* Set 8727 GPIOs to input to allow reading from the 8727 GPIO0 8513 * status which reflect SFP+ module over-current 8514 */ 8515 if (!(phy->flags & FLAGS_NOC)) 8516 val &= 0xff8f; /* Reset bits 4-6 */ 8517 bnx2x_cl45_write(bp, phy, 8518 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL, 8519 val); 8520 break; 8521 default: 8522 DP(NETIF_MSG_LINK, "Function 0x%x not supported by 8727\n", 8523 action); 8524 return; 8525 } 8526 } 8527 8528 static void bnx2x_set_e1e2_module_fault_led(struct link_params *params, 8529 u8 gpio_mode) 8530 { 8531 struct bnx2x *bp = params->bp; 8532 8533 u32 fault_led_gpio = REG_RD(bp, params->shmem_base + 8534 offsetof(struct shmem_region, 8535 dev_info.port_hw_config[params->port].sfp_ctrl)) & 8536 PORT_HW_CFG_FAULT_MODULE_LED_MASK; 8537 switch (fault_led_gpio) { 8538 case PORT_HW_CFG_FAULT_MODULE_LED_DISABLED: 8539 return; 8540 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO0: 8541 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO1: 8542 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO2: 8543 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO3: 8544 { 8545 u8 gpio_port = bnx2x_get_gpio_port(params); 8546 u16 gpio_pin = fault_led_gpio - 8547 PORT_HW_CFG_FAULT_MODULE_LED_GPIO0; 8548 DP(NETIF_MSG_LINK, "Set fault module-detected led " 8549 "pin %x port %x mode %x\n", 8550 gpio_pin, gpio_port, gpio_mode); 8551 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port); 8552 } 8553 break; 8554 default: 8555 DP(NETIF_MSG_LINK, "Error: Invalid fault led mode 0x%x\n", 8556 fault_led_gpio); 8557 } 8558 } 8559 8560 static void bnx2x_set_e3_module_fault_led(struct link_params *params, 8561 u8 gpio_mode) 8562 { 8563 u32 pin_cfg; 8564 u8 port = params->port; 8565 struct bnx2x *bp = params->bp; 8566 pin_cfg = (REG_RD(bp, params->shmem_base + 8567 offsetof(struct shmem_region, 8568 dev_info.port_hw_config[port].e3_sfp_ctrl)) & 8569 PORT_HW_CFG_E3_FAULT_MDL_LED_MASK) >> 8570 PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT; 8571 DP(NETIF_MSG_LINK, "Setting Fault LED to %d using pin cfg %d\n", 8572 gpio_mode, pin_cfg); 8573 bnx2x_set_cfg_pin(bp, pin_cfg, gpio_mode); 8574 } 8575 8576 static void bnx2x_set_sfp_module_fault_led(struct link_params *params, 8577 u8 gpio_mode) 8578 { 8579 struct bnx2x *bp = params->bp; 8580 DP(NETIF_MSG_LINK, "Setting SFP+ module fault LED to %d\n", gpio_mode); 8581 if (CHIP_IS_E3(bp)) { 8582 /* Low ==> if SFP+ module is supported otherwise 8583 * High ==> if SFP+ module is not on the approved vendor list 8584 */ 8585 bnx2x_set_e3_module_fault_led(params, gpio_mode); 8586 } else 8587 bnx2x_set_e1e2_module_fault_led(params, gpio_mode); 8588 } 8589 8590 static void bnx2x_warpcore_hw_reset(struct bnx2x_phy *phy, 8591 struct link_params *params) 8592 { 8593 struct bnx2x *bp = params->bp; 8594 bnx2x_warpcore_power_module(params, 0); 8595 /* Put Warpcore in low power mode */ 8596 REG_WR(bp, MISC_REG_WC0_RESET, 0x0c0e); 8597 8598 /* Put LCPLL in low power mode */ 8599 REG_WR(bp, MISC_REG_LCPLL_E40_PWRDWN, 1); 8600 REG_WR(bp, MISC_REG_LCPLL_E40_RESETB_ANA, 0); 8601 REG_WR(bp, MISC_REG_LCPLL_E40_RESETB_DIG, 0); 8602 } 8603 8604 static void bnx2x_power_sfp_module(struct link_params *params, 8605 struct bnx2x_phy *phy, 8606 u8 power) 8607 { 8608 struct bnx2x *bp = params->bp; 8609 DP(NETIF_MSG_LINK, "Setting SFP+ power to %x\n", power); 8610 8611 switch (phy->type) { 8612 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: 8613 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722: 8614 bnx2x_8727_power_module(params->bp, phy, power); 8615 break; 8616 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT: 8617 bnx2x_warpcore_power_module(params, power); 8618 break; 8619 default: 8620 break; 8621 } 8622 } 8623 static void bnx2x_warpcore_set_limiting_mode(struct link_params *params, 8624 struct bnx2x_phy *phy, 8625 u16 edc_mode) 8626 { 8627 u16 val = 0; 8628 u16 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT; 8629 struct bnx2x *bp = params->bp; 8630 8631 u8 lane = bnx2x_get_warpcore_lane(phy, params); 8632 /* This is a global register which controls all lanes */ 8633 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 8634 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val); 8635 val &= ~(0xf << (lane << 2)); 8636 8637 switch (edc_mode) { 8638 case EDC_MODE_LINEAR: 8639 case EDC_MODE_LIMITING: 8640 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT; 8641 break; 8642 case EDC_MODE_PASSIVE_DAC: 8643 case EDC_MODE_ACTIVE_DAC: 8644 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC; 8645 break; 8646 default: 8647 break; 8648 } 8649 8650 val |= (mode << (lane << 2)); 8651 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 8652 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, val); 8653 /* A must read */ 8654 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 8655 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val); 8656 8657 /* Restart microcode to re-read the new mode */ 8658 bnx2x_warpcore_reset_lane(bp, phy, 1); 8659 bnx2x_warpcore_reset_lane(bp, phy, 0); 8660 8661 } 8662 8663 static void bnx2x_set_limiting_mode(struct link_params *params, 8664 struct bnx2x_phy *phy, 8665 u16 edc_mode) 8666 { 8667 switch (phy->type) { 8668 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: 8669 bnx2x_8726_set_limiting_mode(params->bp, phy, edc_mode); 8670 break; 8671 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: 8672 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722: 8673 bnx2x_8727_set_limiting_mode(params->bp, phy, edc_mode); 8674 break; 8675 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT: 8676 bnx2x_warpcore_set_limiting_mode(params, phy, edc_mode); 8677 break; 8678 } 8679 } 8680 8681 static int bnx2x_sfp_module_detection(struct bnx2x_phy *phy, 8682 struct link_params *params) 8683 { 8684 struct bnx2x *bp = params->bp; 8685 u16 edc_mode; 8686 int rc = 0; 8687 8688 u32 val = REG_RD(bp, params->shmem_base + 8689 offsetof(struct shmem_region, dev_info. 8690 port_feature_config[params->port].config)); 8691 /* Enabled transmitter by default */ 8692 bnx2x_sfp_set_transmitter(params, phy, 1); 8693 DP(NETIF_MSG_LINK, "SFP+ module plugged in/out detected on port %d\n", 8694 params->port); 8695 /* Power up module */ 8696 bnx2x_power_sfp_module(params, phy, 1); 8697 if (bnx2x_get_edc_mode(phy, params, &edc_mode) != 0) { 8698 DP(NETIF_MSG_LINK, "Failed to get valid module type\n"); 8699 return -EINVAL; 8700 } else if (bnx2x_verify_sfp_module(phy, params) != 0) { 8701 /* Check SFP+ module compatibility */ 8702 DP(NETIF_MSG_LINK, "Module verification failed!!\n"); 8703 rc = -EINVAL; 8704 /* Turn on fault module-detected led */ 8705 bnx2x_set_sfp_module_fault_led(params, 8706 MISC_REGISTERS_GPIO_HIGH); 8707 8708 /* Check if need to power down the SFP+ module */ 8709 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == 8710 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN) { 8711 DP(NETIF_MSG_LINK, "Shutdown SFP+ module!!\n"); 8712 bnx2x_power_sfp_module(params, phy, 0); 8713 return rc; 8714 } 8715 } else { 8716 /* Turn off fault module-detected led */ 8717 bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_LOW); 8718 } 8719 8720 /* Check and set limiting mode / LRM mode on 8726. On 8727 it 8721 * is done automatically 8722 */ 8723 bnx2x_set_limiting_mode(params, phy, edc_mode); 8724 8725 /* Disable transmit for this module if the module is not approved, and 8726 * laser needs to be disabled. 8727 */ 8728 if ((rc) && 8729 ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == 8730 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)) 8731 bnx2x_sfp_set_transmitter(params, phy, 0); 8732 8733 return rc; 8734 } 8735 8736 void bnx2x_handle_module_detect_int(struct link_params *params) 8737 { 8738 struct bnx2x *bp = params->bp; 8739 struct bnx2x_phy *phy; 8740 u32 gpio_val; 8741 u8 gpio_num, gpio_port; 8742 if (CHIP_IS_E3(bp)) { 8743 phy = ¶ms->phy[INT_PHY]; 8744 /* Always enable TX laser,will be disabled in case of fault */ 8745 bnx2x_sfp_set_transmitter(params, phy, 1); 8746 } else { 8747 phy = ¶ms->phy[EXT_PHY1]; 8748 } 8749 if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id, params->shmem_base, 8750 params->port, &gpio_num, &gpio_port) == 8751 -EINVAL) { 8752 DP(NETIF_MSG_LINK, "Failed to get MOD_ABS interrupt config\n"); 8753 return; 8754 } 8755 8756 /* Set valid module led off */ 8757 bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_HIGH); 8758 8759 /* Get current gpio val reflecting module plugged in / out*/ 8760 gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port); 8761 8762 /* Call the handling function in case module is detected */ 8763 if (gpio_val == 0) { 8764 bnx2x_set_mdio_emac_per_phy(bp, params); 8765 bnx2x_set_aer_mmd(params, phy); 8766 8767 bnx2x_power_sfp_module(params, phy, 1); 8768 bnx2x_set_gpio_int(bp, gpio_num, 8769 MISC_REGISTERS_GPIO_INT_OUTPUT_CLR, 8770 gpio_port); 8771 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0) { 8772 bnx2x_sfp_module_detection(phy, params); 8773 if (CHIP_IS_E3(bp)) { 8774 u16 rx_tx_in_reset; 8775 /* In case WC is out of reset, reconfigure the 8776 * link speed while taking into account 1G 8777 * module limitation. 8778 */ 8779 bnx2x_cl45_read(bp, phy, 8780 MDIO_WC_DEVAD, 8781 MDIO_WC_REG_DIGITAL5_MISC6, 8782 &rx_tx_in_reset); 8783 if ((!rx_tx_in_reset) && 8784 (params->link_flags & 8785 PHY_INITIALIZED)) { 8786 bnx2x_warpcore_reset_lane(bp, phy, 1); 8787 bnx2x_warpcore_config_sfi(phy, params); 8788 bnx2x_warpcore_reset_lane(bp, phy, 0); 8789 } 8790 } 8791 } else { 8792 DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n"); 8793 } 8794 } else { 8795 bnx2x_set_gpio_int(bp, gpio_num, 8796 MISC_REGISTERS_GPIO_INT_OUTPUT_SET, 8797 gpio_port); 8798 /* Module was plugged out. 8799 * Disable transmit for this module 8800 */ 8801 phy->media_type = ETH_PHY_NOT_PRESENT; 8802 } 8803 } 8804 8805 /******************************************************************/ 8806 /* Used by 8706 and 8727 */ 8807 /******************************************************************/ 8808 static void bnx2x_sfp_mask_fault(struct bnx2x *bp, 8809 struct bnx2x_phy *phy, 8810 u16 alarm_status_offset, 8811 u16 alarm_ctrl_offset) 8812 { 8813 u16 alarm_status, val; 8814 bnx2x_cl45_read(bp, phy, 8815 MDIO_PMA_DEVAD, alarm_status_offset, 8816 &alarm_status); 8817 bnx2x_cl45_read(bp, phy, 8818 MDIO_PMA_DEVAD, alarm_status_offset, 8819 &alarm_status); 8820 /* Mask or enable the fault event. */ 8821 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, &val); 8822 if (alarm_status & (1<<0)) 8823 val &= ~(1<<0); 8824 else 8825 val |= (1<<0); 8826 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, val); 8827 } 8828 /******************************************************************/ 8829 /* common BCM8706/BCM8726 PHY SECTION */ 8830 /******************************************************************/ 8831 static u8 bnx2x_8706_8726_read_status(struct bnx2x_phy *phy, 8832 struct link_params *params, 8833 struct link_vars *vars) 8834 { 8835 u8 link_up = 0; 8836 u16 val1, val2, rx_sd, pcs_status; 8837 struct bnx2x *bp = params->bp; 8838 DP(NETIF_MSG_LINK, "XGXS 8706/8726\n"); 8839 /* Clear RX Alarm*/ 8840 bnx2x_cl45_read(bp, phy, 8841 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2); 8842 8843 bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT, 8844 MDIO_PMA_LASI_TXCTRL); 8845 8846 /* Clear LASI indication*/ 8847 bnx2x_cl45_read(bp, phy, 8848 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1); 8849 bnx2x_cl45_read(bp, phy, 8850 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2); 8851 DP(NETIF_MSG_LINK, "8706/8726 LASI status 0x%x--> 0x%x\n", val1, val2); 8852 8853 bnx2x_cl45_read(bp, phy, 8854 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd); 8855 bnx2x_cl45_read(bp, phy, 8856 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &pcs_status); 8857 bnx2x_cl45_read(bp, phy, 8858 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2); 8859 bnx2x_cl45_read(bp, phy, 8860 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2); 8861 8862 DP(NETIF_MSG_LINK, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps" 8863 " link_status 0x%x\n", rx_sd, pcs_status, val2); 8864 /* Link is up if both bit 0 of pmd_rx_sd and bit 0 of pcs_status 8865 * are set, or if the autoneg bit 1 is set 8866 */ 8867 link_up = ((rx_sd & pcs_status & 0x1) || (val2 & (1<<1))); 8868 if (link_up) { 8869 if (val2 & (1<<1)) 8870 vars->line_speed = SPEED_1000; 8871 else 8872 vars->line_speed = SPEED_10000; 8873 bnx2x_ext_phy_resolve_fc(phy, params, vars); 8874 vars->duplex = DUPLEX_FULL; 8875 } 8876 8877 /* Capture 10G link fault. Read twice to clear stale value. */ 8878 if (vars->line_speed == SPEED_10000) { 8879 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 8880 MDIO_PMA_LASI_TXSTAT, &val1); 8881 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 8882 MDIO_PMA_LASI_TXSTAT, &val1); 8883 if (val1 & (1<<0)) 8884 vars->fault_detected = 1; 8885 } 8886 8887 return link_up; 8888 } 8889 8890 /******************************************************************/ 8891 /* BCM8706 PHY SECTION */ 8892 /******************************************************************/ 8893 static u8 bnx2x_8706_config_init(struct bnx2x_phy *phy, 8894 struct link_params *params, 8895 struct link_vars *vars) 8896 { 8897 u32 tx_en_mode; 8898 u16 cnt, val, tmp1; 8899 struct bnx2x *bp = params->bp; 8900 8901 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 8902 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); 8903 /* HW reset */ 8904 bnx2x_ext_phy_hw_reset(bp, params->port); 8905 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040); 8906 bnx2x_wait_reset_complete(bp, phy, params); 8907 8908 /* Wait until fw is loaded */ 8909 for (cnt = 0; cnt < 100; cnt++) { 8910 bnx2x_cl45_read(bp, phy, 8911 MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER1, &val); 8912 if (val) 8913 break; 8914 usleep_range(10000, 20000); 8915 } 8916 DP(NETIF_MSG_LINK, "XGXS 8706 is initialized after %d ms\n", cnt); 8917 if ((params->feature_config_flags & 8918 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) { 8919 u8 i; 8920 u16 reg; 8921 for (i = 0; i < 4; i++) { 8922 reg = MDIO_XS_8706_REG_BANK_RX0 + 8923 i*(MDIO_XS_8706_REG_BANK_RX1 - 8924 MDIO_XS_8706_REG_BANK_RX0); 8925 bnx2x_cl45_read(bp, phy, MDIO_XS_DEVAD, reg, &val); 8926 /* Clear first 3 bits of the control */ 8927 val &= ~0x7; 8928 /* Set control bits according to configuration */ 8929 val |= (phy->rx_preemphasis[i] & 0x7); 8930 DP(NETIF_MSG_LINK, "Setting RX Equalizer to BCM8706" 8931 " reg 0x%x <-- val 0x%x\n", reg, val); 8932 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, reg, val); 8933 } 8934 } 8935 /* Force speed */ 8936 if (phy->req_line_speed == SPEED_10000) { 8937 DP(NETIF_MSG_LINK, "XGXS 8706 force 10Gbps\n"); 8938 8939 bnx2x_cl45_write(bp, phy, 8940 MDIO_PMA_DEVAD, 8941 MDIO_PMA_REG_DIGITAL_CTRL, 0x400); 8942 bnx2x_cl45_write(bp, phy, 8943 MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL, 8944 0); 8945 /* Arm LASI for link and Tx fault. */ 8946 bnx2x_cl45_write(bp, phy, 8947 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 3); 8948 } else { 8949 /* Force 1Gbps using autoneg with 1G advertisement */ 8950 8951 /* Allow CL37 through CL73 */ 8952 DP(NETIF_MSG_LINK, "XGXS 8706 AutoNeg\n"); 8953 bnx2x_cl45_write(bp, phy, 8954 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c); 8955 8956 /* Enable Full-Duplex advertisement on CL37 */ 8957 bnx2x_cl45_write(bp, phy, 8958 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LP, 0x0020); 8959 /* Enable CL37 AN */ 8960 bnx2x_cl45_write(bp, phy, 8961 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000); 8962 /* 1G support */ 8963 bnx2x_cl45_write(bp, phy, 8964 MDIO_AN_DEVAD, MDIO_AN_REG_ADV, (1<<5)); 8965 8966 /* Enable clause 73 AN */ 8967 bnx2x_cl45_write(bp, phy, 8968 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200); 8969 bnx2x_cl45_write(bp, phy, 8970 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, 8971 0x0400); 8972 bnx2x_cl45_write(bp, phy, 8973 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 8974 0x0004); 8975 } 8976 bnx2x_save_bcm_spirom_ver(bp, phy, params->port); 8977 8978 /* If TX Laser is controlled by GPIO_0, do not let PHY go into low 8979 * power mode, if TX Laser is disabled 8980 */ 8981 8982 tx_en_mode = REG_RD(bp, params->shmem_base + 8983 offsetof(struct shmem_region, 8984 dev_info.port_hw_config[params->port].sfp_ctrl)) 8985 & PORT_HW_CFG_TX_LASER_MASK; 8986 8987 if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) { 8988 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n"); 8989 bnx2x_cl45_read(bp, phy, 8990 MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, &tmp1); 8991 tmp1 |= 0x1; 8992 bnx2x_cl45_write(bp, phy, 8993 MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, tmp1); 8994 } 8995 8996 return 0; 8997 } 8998 8999 static int bnx2x_8706_read_status(struct bnx2x_phy *phy, 9000 struct link_params *params, 9001 struct link_vars *vars) 9002 { 9003 return bnx2x_8706_8726_read_status(phy, params, vars); 9004 } 9005 9006 /******************************************************************/ 9007 /* BCM8726 PHY SECTION */ 9008 /******************************************************************/ 9009 static void bnx2x_8726_config_loopback(struct bnx2x_phy *phy, 9010 struct link_params *params) 9011 { 9012 struct bnx2x *bp = params->bp; 9013 DP(NETIF_MSG_LINK, "PMA/PMD ext_phy_loopback: 8726\n"); 9014 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001); 9015 } 9016 9017 static void bnx2x_8726_external_rom_boot(struct bnx2x_phy *phy, 9018 struct link_params *params) 9019 { 9020 struct bnx2x *bp = params->bp; 9021 /* Need to wait 100ms after reset */ 9022 msleep(100); 9023 9024 /* Micro controller re-boot */ 9025 bnx2x_cl45_write(bp, phy, 9026 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x018B); 9027 9028 /* Set soft reset */ 9029 bnx2x_cl45_write(bp, phy, 9030 MDIO_PMA_DEVAD, 9031 MDIO_PMA_REG_GEN_CTRL, 9032 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET); 9033 9034 bnx2x_cl45_write(bp, phy, 9035 MDIO_PMA_DEVAD, 9036 MDIO_PMA_REG_MISC_CTRL1, 0x0001); 9037 9038 bnx2x_cl45_write(bp, phy, 9039 MDIO_PMA_DEVAD, 9040 MDIO_PMA_REG_GEN_CTRL, 9041 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP); 9042 9043 /* Wait for 150ms for microcode load */ 9044 msleep(150); 9045 9046 /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */ 9047 bnx2x_cl45_write(bp, phy, 9048 MDIO_PMA_DEVAD, 9049 MDIO_PMA_REG_MISC_CTRL1, 0x0000); 9050 9051 msleep(200); 9052 bnx2x_save_bcm_spirom_ver(bp, phy, params->port); 9053 } 9054 9055 static u8 bnx2x_8726_read_status(struct bnx2x_phy *phy, 9056 struct link_params *params, 9057 struct link_vars *vars) 9058 { 9059 struct bnx2x *bp = params->bp; 9060 u16 val1; 9061 u8 link_up = bnx2x_8706_8726_read_status(phy, params, vars); 9062 if (link_up) { 9063 bnx2x_cl45_read(bp, phy, 9064 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 9065 &val1); 9066 if (val1 & (1<<15)) { 9067 DP(NETIF_MSG_LINK, "Tx is disabled\n"); 9068 link_up = 0; 9069 vars->line_speed = 0; 9070 } 9071 } 9072 return link_up; 9073 } 9074 9075 9076 static int bnx2x_8726_config_init(struct bnx2x_phy *phy, 9077 struct link_params *params, 9078 struct link_vars *vars) 9079 { 9080 struct bnx2x *bp = params->bp; 9081 DP(NETIF_MSG_LINK, "Initializing BCM8726\n"); 9082 9083 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15); 9084 bnx2x_wait_reset_complete(bp, phy, params); 9085 9086 bnx2x_8726_external_rom_boot(phy, params); 9087 9088 /* Need to call module detected on initialization since the module 9089 * detection triggered by actual module insertion might occur before 9090 * driver is loaded, and when driver is loaded, it reset all 9091 * registers, including the transmitter 9092 */ 9093 bnx2x_sfp_module_detection(phy, params); 9094 9095 if (phy->req_line_speed == SPEED_1000) { 9096 DP(NETIF_MSG_LINK, "Setting 1G force\n"); 9097 bnx2x_cl45_write(bp, phy, 9098 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40); 9099 bnx2x_cl45_write(bp, phy, 9100 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD); 9101 bnx2x_cl45_write(bp, phy, 9102 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x5); 9103 bnx2x_cl45_write(bp, phy, 9104 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, 9105 0x400); 9106 } else if ((phy->req_line_speed == SPEED_AUTO_NEG) && 9107 (phy->speed_cap_mask & 9108 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) && 9109 ((phy->speed_cap_mask & 9110 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) != 9111 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) { 9112 DP(NETIF_MSG_LINK, "Setting 1G clause37\n"); 9113 /* Set Flow control */ 9114 bnx2x_ext_phy_set_pause(params, phy, vars); 9115 bnx2x_cl45_write(bp, phy, 9116 MDIO_AN_DEVAD, MDIO_AN_REG_ADV, 0x20); 9117 bnx2x_cl45_write(bp, phy, 9118 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c); 9119 bnx2x_cl45_write(bp, phy, 9120 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, 0x0020); 9121 bnx2x_cl45_write(bp, phy, 9122 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000); 9123 bnx2x_cl45_write(bp, phy, 9124 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200); 9125 /* Enable RX-ALARM control to receive interrupt for 1G speed 9126 * change 9127 */ 9128 bnx2x_cl45_write(bp, phy, 9129 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x4); 9130 bnx2x_cl45_write(bp, phy, 9131 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, 9132 0x400); 9133 9134 } else { /* Default 10G. Set only LASI control */ 9135 bnx2x_cl45_write(bp, phy, 9136 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 1); 9137 } 9138 9139 /* Set TX PreEmphasis if needed */ 9140 if ((params->feature_config_flags & 9141 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) { 9142 DP(NETIF_MSG_LINK, 9143 "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n", 9144 phy->tx_preemphasis[0], 9145 phy->tx_preemphasis[1]); 9146 bnx2x_cl45_write(bp, phy, 9147 MDIO_PMA_DEVAD, 9148 MDIO_PMA_REG_8726_TX_CTRL1, 9149 phy->tx_preemphasis[0]); 9150 9151 bnx2x_cl45_write(bp, phy, 9152 MDIO_PMA_DEVAD, 9153 MDIO_PMA_REG_8726_TX_CTRL2, 9154 phy->tx_preemphasis[1]); 9155 } 9156 9157 return 0; 9158 9159 } 9160 9161 static void bnx2x_8726_link_reset(struct bnx2x_phy *phy, 9162 struct link_params *params) 9163 { 9164 struct bnx2x *bp = params->bp; 9165 DP(NETIF_MSG_LINK, "bnx2x_8726_link_reset port %d\n", params->port); 9166 /* Set serial boot control for external load */ 9167 bnx2x_cl45_write(bp, phy, 9168 MDIO_PMA_DEVAD, 9169 MDIO_PMA_REG_GEN_CTRL, 0x0001); 9170 } 9171 9172 /******************************************************************/ 9173 /* BCM8727 PHY SECTION */ 9174 /******************************************************************/ 9175 9176 static void bnx2x_8727_set_link_led(struct bnx2x_phy *phy, 9177 struct link_params *params, u8 mode) 9178 { 9179 struct bnx2x *bp = params->bp; 9180 u16 led_mode_bitmask = 0; 9181 u16 gpio_pins_bitmask = 0; 9182 u16 val; 9183 /* Only NOC flavor requires to set the LED specifically */ 9184 if (!(phy->flags & FLAGS_NOC)) 9185 return; 9186 switch (mode) { 9187 case LED_MODE_FRONT_PANEL_OFF: 9188 case LED_MODE_OFF: 9189 led_mode_bitmask = 0; 9190 gpio_pins_bitmask = 0x03; 9191 break; 9192 case LED_MODE_ON: 9193 led_mode_bitmask = 0; 9194 gpio_pins_bitmask = 0x02; 9195 break; 9196 case LED_MODE_OPER: 9197 led_mode_bitmask = 0x60; 9198 gpio_pins_bitmask = 0x11; 9199 break; 9200 } 9201 bnx2x_cl45_read(bp, phy, 9202 MDIO_PMA_DEVAD, 9203 MDIO_PMA_REG_8727_PCS_OPT_CTRL, 9204 &val); 9205 val &= 0xff8f; 9206 val |= led_mode_bitmask; 9207 bnx2x_cl45_write(bp, phy, 9208 MDIO_PMA_DEVAD, 9209 MDIO_PMA_REG_8727_PCS_OPT_CTRL, 9210 val); 9211 bnx2x_cl45_read(bp, phy, 9212 MDIO_PMA_DEVAD, 9213 MDIO_PMA_REG_8727_GPIO_CTRL, 9214 &val); 9215 val &= 0xffe0; 9216 val |= gpio_pins_bitmask; 9217 bnx2x_cl45_write(bp, phy, 9218 MDIO_PMA_DEVAD, 9219 MDIO_PMA_REG_8727_GPIO_CTRL, 9220 val); 9221 } 9222 static void bnx2x_8727_hw_reset(struct bnx2x_phy *phy, 9223 struct link_params *params) { 9224 u32 swap_val, swap_override; 9225 u8 port; 9226 /* The PHY reset is controlled by GPIO 1. Fake the port number 9227 * to cancel the swap done in set_gpio() 9228 */ 9229 struct bnx2x *bp = params->bp; 9230 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); 9231 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); 9232 port = (swap_val && swap_override) ^ 1; 9233 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, 9234 MISC_REGISTERS_GPIO_OUTPUT_LOW, port); 9235 } 9236 9237 static void bnx2x_8727_config_speed(struct bnx2x_phy *phy, 9238 struct link_params *params) 9239 { 9240 struct bnx2x *bp = params->bp; 9241 u16 tmp1, val; 9242 /* Set option 1G speed */ 9243 if ((phy->req_line_speed == SPEED_1000) || 9244 (phy->media_type == ETH_PHY_SFP_1G_FIBER)) { 9245 DP(NETIF_MSG_LINK, "Setting 1G force\n"); 9246 bnx2x_cl45_write(bp, phy, 9247 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40); 9248 bnx2x_cl45_write(bp, phy, 9249 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD); 9250 bnx2x_cl45_read(bp, phy, 9251 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, &tmp1); 9252 DP(NETIF_MSG_LINK, "1.7 = 0x%x\n", tmp1); 9253 /* Power down the XAUI until link is up in case of dual-media 9254 * and 1G 9255 */ 9256 if (DUAL_MEDIA(params)) { 9257 bnx2x_cl45_read(bp, phy, 9258 MDIO_PMA_DEVAD, 9259 MDIO_PMA_REG_8727_PCS_GP, &val); 9260 val |= (3<<10); 9261 bnx2x_cl45_write(bp, phy, 9262 MDIO_PMA_DEVAD, 9263 MDIO_PMA_REG_8727_PCS_GP, val); 9264 } 9265 } else if ((phy->req_line_speed == SPEED_AUTO_NEG) && 9266 ((phy->speed_cap_mask & 9267 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) && 9268 ((phy->speed_cap_mask & 9269 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) != 9270 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) { 9271 9272 DP(NETIF_MSG_LINK, "Setting 1G clause37\n"); 9273 bnx2x_cl45_write(bp, phy, 9274 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 0); 9275 bnx2x_cl45_write(bp, phy, 9276 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1300); 9277 } else { 9278 /* Since the 8727 has only single reset pin, need to set the 10G 9279 * registers although it is default 9280 */ 9281 bnx2x_cl45_write(bp, phy, 9282 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 9283 0x0020); 9284 bnx2x_cl45_write(bp, phy, 9285 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x0100); 9286 bnx2x_cl45_write(bp, phy, 9287 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040); 9288 bnx2x_cl45_write(bp, phy, 9289 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 9290 0x0008); 9291 } 9292 } 9293 9294 static int bnx2x_8727_config_init(struct bnx2x_phy *phy, 9295 struct link_params *params, 9296 struct link_vars *vars) 9297 { 9298 u32 tx_en_mode; 9299 u16 tmp1, mod_abs, tmp2; 9300 struct bnx2x *bp = params->bp; 9301 /* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */ 9302 9303 bnx2x_wait_reset_complete(bp, phy, params); 9304 9305 DP(NETIF_MSG_LINK, "Initializing BCM8727\n"); 9306 9307 bnx2x_8727_specific_func(phy, params, PHY_INIT); 9308 /* Initially configure MOD_ABS to interrupt when module is 9309 * presence( bit 8) 9310 */ 9311 bnx2x_cl45_read(bp, phy, 9312 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs); 9313 /* Set EDC off by setting OPTXLOS signal input to low (bit 9). 9314 * When the EDC is off it locks onto a reference clock and avoids 9315 * becoming 'lost' 9316 */ 9317 mod_abs &= ~(1<<8); 9318 if (!(phy->flags & FLAGS_NOC)) 9319 mod_abs &= ~(1<<9); 9320 bnx2x_cl45_write(bp, phy, 9321 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs); 9322 9323 /* Enable/Disable PHY transmitter output */ 9324 bnx2x_set_disable_pmd_transmit(params, phy, 0); 9325 9326 bnx2x_8727_power_module(bp, phy, 1); 9327 9328 bnx2x_cl45_read(bp, phy, 9329 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1); 9330 9331 bnx2x_cl45_read(bp, phy, 9332 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1); 9333 9334 bnx2x_8727_config_speed(phy, params); 9335 9336 9337 /* Set TX PreEmphasis if needed */ 9338 if ((params->feature_config_flags & 9339 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) { 9340 DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n", 9341 phy->tx_preemphasis[0], 9342 phy->tx_preemphasis[1]); 9343 bnx2x_cl45_write(bp, phy, 9344 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL1, 9345 phy->tx_preemphasis[0]); 9346 9347 bnx2x_cl45_write(bp, phy, 9348 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL2, 9349 phy->tx_preemphasis[1]); 9350 } 9351 9352 /* If TX Laser is controlled by GPIO_0, do not let PHY go into low 9353 * power mode, if TX Laser is disabled 9354 */ 9355 tx_en_mode = REG_RD(bp, params->shmem_base + 9356 offsetof(struct shmem_region, 9357 dev_info.port_hw_config[params->port].sfp_ctrl)) 9358 & PORT_HW_CFG_TX_LASER_MASK; 9359 9360 if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) { 9361 9362 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n"); 9363 bnx2x_cl45_read(bp, phy, 9364 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, &tmp2); 9365 tmp2 |= 0x1000; 9366 tmp2 &= 0xFFEF; 9367 bnx2x_cl45_write(bp, phy, 9368 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, tmp2); 9369 bnx2x_cl45_read(bp, phy, 9370 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 9371 &tmp2); 9372 bnx2x_cl45_write(bp, phy, 9373 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 9374 (tmp2 & 0x7fff)); 9375 } 9376 9377 return 0; 9378 } 9379 9380 static void bnx2x_8727_handle_mod_abs(struct bnx2x_phy *phy, 9381 struct link_params *params) 9382 { 9383 struct bnx2x *bp = params->bp; 9384 u16 mod_abs, rx_alarm_status; 9385 u32 val = REG_RD(bp, params->shmem_base + 9386 offsetof(struct shmem_region, dev_info. 9387 port_feature_config[params->port]. 9388 config)); 9389 bnx2x_cl45_read(bp, phy, 9390 MDIO_PMA_DEVAD, 9391 MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs); 9392 if (mod_abs & (1<<8)) { 9393 9394 /* Module is absent */ 9395 DP(NETIF_MSG_LINK, 9396 "MOD_ABS indication show module is absent\n"); 9397 phy->media_type = ETH_PHY_NOT_PRESENT; 9398 /* 1. Set mod_abs to detect next module 9399 * presence event 9400 * 2. Set EDC off by setting OPTXLOS signal input to low 9401 * (bit 9). 9402 * When the EDC is off it locks onto a reference clock and 9403 * avoids becoming 'lost'. 9404 */ 9405 mod_abs &= ~(1<<8); 9406 if (!(phy->flags & FLAGS_NOC)) 9407 mod_abs &= ~(1<<9); 9408 bnx2x_cl45_write(bp, phy, 9409 MDIO_PMA_DEVAD, 9410 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs); 9411 9412 /* Clear RX alarm since it stays up as long as 9413 * the mod_abs wasn't changed 9414 */ 9415 bnx2x_cl45_read(bp, phy, 9416 MDIO_PMA_DEVAD, 9417 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status); 9418 9419 } else { 9420 /* Module is present */ 9421 DP(NETIF_MSG_LINK, 9422 "MOD_ABS indication show module is present\n"); 9423 /* First disable transmitter, and if the module is ok, the 9424 * module_detection will enable it 9425 * 1. Set mod_abs to detect next module absent event ( bit 8) 9426 * 2. Restore the default polarity of the OPRXLOS signal and 9427 * this signal will then correctly indicate the presence or 9428 * absence of the Rx signal. (bit 9) 9429 */ 9430 mod_abs |= (1<<8); 9431 if (!(phy->flags & FLAGS_NOC)) 9432 mod_abs |= (1<<9); 9433 bnx2x_cl45_write(bp, phy, 9434 MDIO_PMA_DEVAD, 9435 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs); 9436 9437 /* Clear RX alarm since it stays up as long as the mod_abs 9438 * wasn't changed. This is need to be done before calling the 9439 * module detection, otherwise it will clear* the link update 9440 * alarm 9441 */ 9442 bnx2x_cl45_read(bp, phy, 9443 MDIO_PMA_DEVAD, 9444 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status); 9445 9446 9447 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == 9448 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER) 9449 bnx2x_sfp_set_transmitter(params, phy, 0); 9450 9451 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0) 9452 bnx2x_sfp_module_detection(phy, params); 9453 else 9454 DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n"); 9455 9456 /* Reconfigure link speed based on module type limitations */ 9457 bnx2x_8727_config_speed(phy, params); 9458 } 9459 9460 DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n", 9461 rx_alarm_status); 9462 /* No need to check link status in case of module plugged in/out */ 9463 } 9464 9465 static u8 bnx2x_8727_read_status(struct bnx2x_phy *phy, 9466 struct link_params *params, 9467 struct link_vars *vars) 9468 9469 { 9470 struct bnx2x *bp = params->bp; 9471 u8 link_up = 0, oc_port = params->port; 9472 u16 link_status = 0; 9473 u16 rx_alarm_status, lasi_ctrl, val1; 9474 9475 /* If PHY is not initialized, do not check link status */ 9476 bnx2x_cl45_read(bp, phy, 9477 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 9478 &lasi_ctrl); 9479 if (!lasi_ctrl) 9480 return 0; 9481 9482 /* Check the LASI on Rx */ 9483 bnx2x_cl45_read(bp, phy, 9484 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, 9485 &rx_alarm_status); 9486 vars->line_speed = 0; 9487 DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n", rx_alarm_status); 9488 9489 bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT, 9490 MDIO_PMA_LASI_TXCTRL); 9491 9492 bnx2x_cl45_read(bp, phy, 9493 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1); 9494 9495 DP(NETIF_MSG_LINK, "8727 LASI status 0x%x\n", val1); 9496 9497 /* Clear MSG-OUT */ 9498 bnx2x_cl45_read(bp, phy, 9499 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1); 9500 9501 /* If a module is present and there is need to check 9502 * for over current 9503 */ 9504 if (!(phy->flags & FLAGS_NOC) && !(rx_alarm_status & (1<<5))) { 9505 /* Check over-current using 8727 GPIO0 input*/ 9506 bnx2x_cl45_read(bp, phy, 9507 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL, 9508 &val1); 9509 9510 if ((val1 & (1<<8)) == 0) { 9511 if (!CHIP_IS_E1x(bp)) 9512 oc_port = BP_PATH(bp) + (params->port << 1); 9513 DP(NETIF_MSG_LINK, 9514 "8727 Power fault has been detected on port %d\n", 9515 oc_port); 9516 netdev_err(bp->dev, "Error: Power fault on Port %d has " 9517 "been detected and the power to " 9518 "that SFP+ module has been removed " 9519 "to prevent failure of the card. " 9520 "Please remove the SFP+ module and " 9521 "restart the system to clear this " 9522 "error.\n", 9523 oc_port); 9524 /* Disable all RX_ALARMs except for mod_abs */ 9525 bnx2x_cl45_write(bp, phy, 9526 MDIO_PMA_DEVAD, 9527 MDIO_PMA_LASI_RXCTRL, (1<<5)); 9528 9529 bnx2x_cl45_read(bp, phy, 9530 MDIO_PMA_DEVAD, 9531 MDIO_PMA_REG_PHY_IDENTIFIER, &val1); 9532 /* Wait for module_absent_event */ 9533 val1 |= (1<<8); 9534 bnx2x_cl45_write(bp, phy, 9535 MDIO_PMA_DEVAD, 9536 MDIO_PMA_REG_PHY_IDENTIFIER, val1); 9537 /* Clear RX alarm */ 9538 bnx2x_cl45_read(bp, phy, 9539 MDIO_PMA_DEVAD, 9540 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status); 9541 bnx2x_8727_power_module(params->bp, phy, 0); 9542 return 0; 9543 } 9544 } /* Over current check */ 9545 9546 /* When module absent bit is set, check module */ 9547 if (rx_alarm_status & (1<<5)) { 9548 bnx2x_8727_handle_mod_abs(phy, params); 9549 /* Enable all mod_abs and link detection bits */ 9550 bnx2x_cl45_write(bp, phy, 9551 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, 9552 ((1<<5) | (1<<2))); 9553 } 9554 9555 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED)) { 9556 DP(NETIF_MSG_LINK, "Enabling 8727 TX laser\n"); 9557 bnx2x_sfp_set_transmitter(params, phy, 1); 9558 } else { 9559 DP(NETIF_MSG_LINK, "Tx is disabled\n"); 9560 return 0; 9561 } 9562 9563 bnx2x_cl45_read(bp, phy, 9564 MDIO_PMA_DEVAD, 9565 MDIO_PMA_REG_8073_SPEED_LINK_STATUS, &link_status); 9566 9567 /* Bits 0..2 --> speed detected, 9568 * Bits 13..15--> link is down 9569 */ 9570 if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) { 9571 link_up = 1; 9572 vars->line_speed = SPEED_10000; 9573 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n", 9574 params->port); 9575 } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) { 9576 link_up = 1; 9577 vars->line_speed = SPEED_1000; 9578 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n", 9579 params->port); 9580 } else { 9581 link_up = 0; 9582 DP(NETIF_MSG_LINK, "port %x: External link is down\n", 9583 params->port); 9584 } 9585 9586 /* Capture 10G link fault. */ 9587 if (vars->line_speed == SPEED_10000) { 9588 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 9589 MDIO_PMA_LASI_TXSTAT, &val1); 9590 9591 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 9592 MDIO_PMA_LASI_TXSTAT, &val1); 9593 9594 if (val1 & (1<<0)) { 9595 vars->fault_detected = 1; 9596 } 9597 } 9598 9599 if (link_up) { 9600 bnx2x_ext_phy_resolve_fc(phy, params, vars); 9601 vars->duplex = DUPLEX_FULL; 9602 DP(NETIF_MSG_LINK, "duplex = 0x%x\n", vars->duplex); 9603 } 9604 9605 if ((DUAL_MEDIA(params)) && 9606 (phy->req_line_speed == SPEED_1000)) { 9607 bnx2x_cl45_read(bp, phy, 9608 MDIO_PMA_DEVAD, 9609 MDIO_PMA_REG_8727_PCS_GP, &val1); 9610 /* In case of dual-media board and 1G, power up the XAUI side, 9611 * otherwise power it down. For 10G it is done automatically 9612 */ 9613 if (link_up) 9614 val1 &= ~(3<<10); 9615 else 9616 val1 |= (3<<10); 9617 bnx2x_cl45_write(bp, phy, 9618 MDIO_PMA_DEVAD, 9619 MDIO_PMA_REG_8727_PCS_GP, val1); 9620 } 9621 return link_up; 9622 } 9623 9624 static void bnx2x_8727_link_reset(struct bnx2x_phy *phy, 9625 struct link_params *params) 9626 { 9627 struct bnx2x *bp = params->bp; 9628 9629 /* Enable/Disable PHY transmitter output */ 9630 bnx2x_set_disable_pmd_transmit(params, phy, 1); 9631 9632 /* Disable Transmitter */ 9633 bnx2x_sfp_set_transmitter(params, phy, 0); 9634 /* Clear LASI */ 9635 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0); 9636 9637 } 9638 9639 /******************************************************************/ 9640 /* BCM8481/BCM84823/BCM84833 PHY SECTION */ 9641 /******************************************************************/ 9642 static int bnx2x_is_8483x_8485x(struct bnx2x_phy *phy) 9643 { 9644 return ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) || 9645 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) || 9646 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858)); 9647 } 9648 9649 static void bnx2x_save_848xx_spirom_version(struct bnx2x_phy *phy, 9650 struct bnx2x *bp, 9651 u8 port) 9652 { 9653 u16 val, fw_ver2, cnt, i; 9654 static struct bnx2x_reg_set reg_set[] = { 9655 {MDIO_PMA_DEVAD, 0xA819, 0x0014}, 9656 {MDIO_PMA_DEVAD, 0xA81A, 0xc200}, 9657 {MDIO_PMA_DEVAD, 0xA81B, 0x0000}, 9658 {MDIO_PMA_DEVAD, 0xA81C, 0x0300}, 9659 {MDIO_PMA_DEVAD, 0xA817, 0x0009} 9660 }; 9661 u16 fw_ver1; 9662 9663 if (bnx2x_is_8483x_8485x(phy)) { 9664 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 0x400f, &fw_ver1); 9665 if (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858) 9666 fw_ver1 &= 0xfff; 9667 bnx2x_save_spirom_version(bp, port, fw_ver1, phy->ver_addr); 9668 } else { 9669 /* For 32-bit registers in 848xx, access via MDIO2ARM i/f. */ 9670 /* (1) set reg 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */ 9671 for (i = 0; i < ARRAY_SIZE(reg_set); i++) 9672 bnx2x_cl45_write(bp, phy, reg_set[i].devad, 9673 reg_set[i].reg, reg_set[i].val); 9674 9675 for (cnt = 0; cnt < 100; cnt++) { 9676 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val); 9677 if (val & 1) 9678 break; 9679 udelay(5); 9680 } 9681 if (cnt == 100) { 9682 DP(NETIF_MSG_LINK, "Unable to read 848xx " 9683 "phy fw version(1)\n"); 9684 bnx2x_save_spirom_version(bp, port, 0, 9685 phy->ver_addr); 9686 return; 9687 } 9688 9689 9690 /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */ 9691 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0000); 9692 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200); 9693 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x000A); 9694 for (cnt = 0; cnt < 100; cnt++) { 9695 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val); 9696 if (val & 1) 9697 break; 9698 udelay(5); 9699 } 9700 if (cnt == 100) { 9701 DP(NETIF_MSG_LINK, "Unable to read 848xx phy fw " 9702 "version(2)\n"); 9703 bnx2x_save_spirom_version(bp, port, 0, 9704 phy->ver_addr); 9705 return; 9706 } 9707 9708 /* lower 16 bits of the register SPI_FW_STATUS */ 9709 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81B, &fw_ver1); 9710 /* upper 16 bits of register SPI_FW_STATUS */ 9711 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81C, &fw_ver2); 9712 9713 bnx2x_save_spirom_version(bp, port, (fw_ver2<<16) | fw_ver1, 9714 phy->ver_addr); 9715 } 9716 9717 } 9718 static void bnx2x_848xx_set_led(struct bnx2x *bp, 9719 struct bnx2x_phy *phy) 9720 { 9721 u16 val, led3_blink_rate, offset, i; 9722 static struct bnx2x_reg_set reg_set[] = { 9723 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED1_MASK, 0x0080}, 9724 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED2_MASK, 0x0018}, 9725 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED3_MASK, 0x0006}, 9726 {MDIO_PMA_DEVAD, MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH, 9727 MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ}, 9728 {MDIO_AN_DEVAD, 0xFFFB, 0xFFFD} 9729 }; 9730 9731 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858) { 9732 /* Set LED5 source */ 9733 bnx2x_cl45_write(bp, phy, 9734 MDIO_PMA_DEVAD, 9735 MDIO_PMA_REG_8481_LED5_MASK, 9736 0x90); 9737 led3_blink_rate = 0x000f; 9738 } else { 9739 led3_blink_rate = 0x0000; 9740 } 9741 /* Set LED3 BLINK */ 9742 bnx2x_cl45_write(bp, phy, 9743 MDIO_PMA_DEVAD, 9744 MDIO_PMA_REG_8481_LED3_BLINK, 9745 led3_blink_rate); 9746 9747 /* PHYC_CTL_LED_CTL */ 9748 bnx2x_cl45_read(bp, phy, 9749 MDIO_PMA_DEVAD, 9750 MDIO_PMA_REG_8481_LINK_SIGNAL, &val); 9751 val &= 0xFE00; 9752 val |= 0x0092; 9753 9754 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858) 9755 val |= 2 << 12; /* LED5 ON based on source */ 9756 9757 bnx2x_cl45_write(bp, phy, 9758 MDIO_PMA_DEVAD, 9759 MDIO_PMA_REG_8481_LINK_SIGNAL, val); 9760 9761 for (i = 0; i < ARRAY_SIZE(reg_set); i++) 9762 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg, 9763 reg_set[i].val); 9764 9765 if (bnx2x_is_8483x_8485x(phy)) 9766 offset = MDIO_PMA_REG_84833_CTL_LED_CTL_1; 9767 else 9768 offset = MDIO_PMA_REG_84823_CTL_LED_CTL_1; 9769 9770 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858) 9771 val = MDIO_PMA_REG_84858_ALLOW_GPHY_ACT | 9772 MDIO_PMA_REG_84823_LED3_STRETCH_EN; 9773 else 9774 val = MDIO_PMA_REG_84823_LED3_STRETCH_EN; 9775 9776 /* stretch_en for LEDs */ 9777 bnx2x_cl45_read_or_write(bp, phy, 9778 MDIO_PMA_DEVAD, 9779 offset, 9780 val); 9781 } 9782 9783 static void bnx2x_848xx_specific_func(struct bnx2x_phy *phy, 9784 struct link_params *params, 9785 u32 action) 9786 { 9787 struct bnx2x *bp = params->bp; 9788 switch (action) { 9789 case PHY_INIT: 9790 if (bnx2x_is_8483x_8485x(phy)) { 9791 /* Save spirom version */ 9792 bnx2x_save_848xx_spirom_version(phy, bp, params->port); 9793 } 9794 /* This phy uses the NIG latch mechanism since link indication 9795 * arrives through its LED4 and not via its LASI signal, so we 9796 * get steady signal instead of clear on read 9797 */ 9798 bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4, 9799 1 << NIG_LATCH_BC_ENABLE_MI_INT); 9800 9801 bnx2x_848xx_set_led(bp, phy); 9802 break; 9803 } 9804 } 9805 9806 static int bnx2x_848xx_cmn_config_init(struct bnx2x_phy *phy, 9807 struct link_params *params, 9808 struct link_vars *vars) 9809 { 9810 struct bnx2x *bp = params->bp; 9811 u16 autoneg_val, an_1000_val, an_10_100_val; 9812 9813 bnx2x_848xx_specific_func(phy, params, PHY_INIT); 9814 bnx2x_cl45_write(bp, phy, 9815 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0000); 9816 9817 /* set 1000 speed advertisement */ 9818 bnx2x_cl45_read(bp, phy, 9819 MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL, 9820 &an_1000_val); 9821 9822 bnx2x_ext_phy_set_pause(params, phy, vars); 9823 bnx2x_cl45_read(bp, phy, 9824 MDIO_AN_DEVAD, 9825 MDIO_AN_REG_8481_LEGACY_AN_ADV, 9826 &an_10_100_val); 9827 bnx2x_cl45_read(bp, phy, 9828 MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_MII_CTRL, 9829 &autoneg_val); 9830 /* Disable forced speed */ 9831 autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13)); 9832 an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8)); 9833 9834 if (((phy->req_line_speed == SPEED_AUTO_NEG) && 9835 (phy->speed_cap_mask & 9836 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) || 9837 (phy->req_line_speed == SPEED_1000)) { 9838 an_1000_val |= (1<<8); 9839 autoneg_val |= (1<<9 | 1<<12); 9840 if (phy->req_duplex == DUPLEX_FULL) 9841 an_1000_val |= (1<<9); 9842 DP(NETIF_MSG_LINK, "Advertising 1G\n"); 9843 } else 9844 an_1000_val &= ~((1<<8) | (1<<9)); 9845 9846 bnx2x_cl45_write(bp, phy, 9847 MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL, 9848 an_1000_val); 9849 9850 /* Set 10/100 speed advertisement */ 9851 if (phy->req_line_speed == SPEED_AUTO_NEG) { 9852 if (phy->speed_cap_mask & 9853 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL) { 9854 /* Enable autoneg and restart autoneg for legacy speeds 9855 */ 9856 autoneg_val |= (1<<9 | 1<<12); 9857 an_10_100_val |= (1<<8); 9858 DP(NETIF_MSG_LINK, "Advertising 100M-FD\n"); 9859 } 9860 9861 if (phy->speed_cap_mask & 9862 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF) { 9863 /* Enable autoneg and restart autoneg for legacy speeds 9864 */ 9865 autoneg_val |= (1<<9 | 1<<12); 9866 an_10_100_val |= (1<<7); 9867 DP(NETIF_MSG_LINK, "Advertising 100M-HD\n"); 9868 } 9869 9870 if ((phy->speed_cap_mask & 9871 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) && 9872 (phy->supported & SUPPORTED_10baseT_Full)) { 9873 an_10_100_val |= (1<<6); 9874 autoneg_val |= (1<<9 | 1<<12); 9875 DP(NETIF_MSG_LINK, "Advertising 10M-FD\n"); 9876 } 9877 9878 if ((phy->speed_cap_mask & 9879 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF) && 9880 (phy->supported & SUPPORTED_10baseT_Half)) { 9881 an_10_100_val |= (1<<5); 9882 autoneg_val |= (1<<9 | 1<<12); 9883 DP(NETIF_MSG_LINK, "Advertising 10M-HD\n"); 9884 } 9885 } 9886 9887 /* Only 10/100 are allowed to work in FORCE mode */ 9888 if ((phy->req_line_speed == SPEED_100) && 9889 (phy->supported & 9890 (SUPPORTED_100baseT_Half | 9891 SUPPORTED_100baseT_Full))) { 9892 autoneg_val |= (1<<13); 9893 /* Enabled AUTO-MDIX when autoneg is disabled */ 9894 bnx2x_cl45_write(bp, phy, 9895 MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL, 9896 (1<<15 | 1<<9 | 7<<0)); 9897 /* The PHY needs this set even for forced link. */ 9898 an_10_100_val |= (1<<8) | (1<<7); 9899 DP(NETIF_MSG_LINK, "Setting 100M force\n"); 9900 } 9901 if ((phy->req_line_speed == SPEED_10) && 9902 (phy->supported & 9903 (SUPPORTED_10baseT_Half | 9904 SUPPORTED_10baseT_Full))) { 9905 /* Enabled AUTO-MDIX when autoneg is disabled */ 9906 bnx2x_cl45_write(bp, phy, 9907 MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL, 9908 (1<<15 | 1<<9 | 7<<0)); 9909 DP(NETIF_MSG_LINK, "Setting 10M force\n"); 9910 } 9911 9912 bnx2x_cl45_write(bp, phy, 9913 MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_AN_ADV, 9914 an_10_100_val); 9915 9916 if (phy->req_duplex == DUPLEX_FULL) 9917 autoneg_val |= (1<<8); 9918 9919 /* Always write this if this is not 84833/4. 9920 * For 84833/4, write it only when it's a forced speed. 9921 */ 9922 if (!bnx2x_is_8483x_8485x(phy) || 9923 ((autoneg_val & (1<<12)) == 0)) 9924 bnx2x_cl45_write(bp, phy, 9925 MDIO_AN_DEVAD, 9926 MDIO_AN_REG_8481_LEGACY_MII_CTRL, autoneg_val); 9927 9928 if (((phy->req_line_speed == SPEED_AUTO_NEG) && 9929 (phy->speed_cap_mask & 9930 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) || 9931 (phy->req_line_speed == SPEED_10000)) { 9932 DP(NETIF_MSG_LINK, "Advertising 10G\n"); 9933 /* Restart autoneg for 10G*/ 9934 9935 bnx2x_cl45_read_or_write( 9936 bp, phy, 9937 MDIO_AN_DEVAD, 9938 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL, 9939 0x1000); 9940 bnx2x_cl45_write(bp, phy, 9941 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 9942 0x3200); 9943 } else 9944 bnx2x_cl45_write(bp, phy, 9945 MDIO_AN_DEVAD, 9946 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL, 9947 1); 9948 9949 return 0; 9950 } 9951 9952 static int bnx2x_8481_config_init(struct bnx2x_phy *phy, 9953 struct link_params *params, 9954 struct link_vars *vars) 9955 { 9956 struct bnx2x *bp = params->bp; 9957 /* Restore normal power mode*/ 9958 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 9959 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); 9960 9961 /* HW reset */ 9962 bnx2x_ext_phy_hw_reset(bp, params->port); 9963 bnx2x_wait_reset_complete(bp, phy, params); 9964 9965 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15); 9966 return bnx2x_848xx_cmn_config_init(phy, params, vars); 9967 } 9968 9969 #define PHY848xx_CMDHDLR_WAIT 300 9970 #define PHY848xx_CMDHDLR_MAX_ARGS 5 9971 9972 static int bnx2x_84858_cmd_hdlr(struct bnx2x_phy *phy, 9973 struct link_params *params, 9974 u16 fw_cmd, 9975 u16 cmd_args[], int argc) 9976 { 9977 int idx; 9978 u16 val; 9979 struct bnx2x *bp = params->bp; 9980 9981 /* Step 1: Poll the STATUS register to see whether the previous command 9982 * is in progress or the system is busy (CMD_IN_PROGRESS or 9983 * SYSTEM_BUSY). If previous command is in progress or system is busy, 9984 * check again until the previous command finishes execution and the 9985 * system is available for taking command 9986 */ 9987 9988 for (idx = 0; idx < PHY848xx_CMDHDLR_WAIT; idx++) { 9989 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 9990 MDIO_848xx_CMD_HDLR_STATUS, &val); 9991 if ((val != PHY84858_STATUS_CMD_IN_PROGRESS) && 9992 (val != PHY84858_STATUS_CMD_SYSTEM_BUSY)) 9993 break; 9994 usleep_range(1000, 2000); 9995 } 9996 if (idx >= PHY848xx_CMDHDLR_WAIT) { 9997 DP(NETIF_MSG_LINK, "FW cmd: FW not ready.\n"); 9998 return -EINVAL; 9999 } 10000 10001 /* Step2: If any parameters are required for the function, write them 10002 * to the required DATA registers 10003 */ 10004 10005 for (idx = 0; idx < argc; idx++) { 10006 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, 10007 MDIO_848xx_CMD_HDLR_DATA1 + idx, 10008 cmd_args[idx]); 10009 } 10010 10011 /* Step3: When the firmware is ready for commands, write the 'Command 10012 * code' to the CMD register 10013 */ 10014 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, 10015 MDIO_848xx_CMD_HDLR_COMMAND, fw_cmd); 10016 10017 /* Step4: Once the command has been written, poll the STATUS register 10018 * to check whether the command has completed (CMD_COMPLETED_PASS/ 10019 * CMD_FOR_CMDS or CMD_COMPLETED_ERROR). 10020 */ 10021 10022 for (idx = 0; idx < PHY848xx_CMDHDLR_WAIT; idx++) { 10023 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 10024 MDIO_848xx_CMD_HDLR_STATUS, &val); 10025 if ((val == PHY84858_STATUS_CMD_COMPLETE_PASS) || 10026 (val == PHY84858_STATUS_CMD_COMPLETE_ERROR)) 10027 break; 10028 usleep_range(1000, 2000); 10029 } 10030 if ((idx >= PHY848xx_CMDHDLR_WAIT) || 10031 (val == PHY84858_STATUS_CMD_COMPLETE_ERROR)) { 10032 DP(NETIF_MSG_LINK, "FW cmd failed.\n"); 10033 return -EINVAL; 10034 } 10035 /* Step5: Once the command has completed, read the specficied DATA 10036 * registers for any saved results for the command, if applicable 10037 */ 10038 10039 /* Gather returning data */ 10040 for (idx = 0; idx < argc; idx++) { 10041 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 10042 MDIO_848xx_CMD_HDLR_DATA1 + idx, 10043 &cmd_args[idx]); 10044 } 10045 10046 return 0; 10047 } 10048 10049 static int bnx2x_84833_cmd_hdlr(struct bnx2x_phy *phy, 10050 struct link_params *params, u16 fw_cmd, 10051 u16 cmd_args[], int argc, int process) 10052 { 10053 int idx; 10054 u16 val; 10055 struct bnx2x *bp = params->bp; 10056 int rc = 0; 10057 10058 if (process == PHY84833_MB_PROCESS2) { 10059 /* Write CMD_OPEN_OVERRIDE to STATUS reg */ 10060 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, 10061 MDIO_848xx_CMD_HDLR_STATUS, 10062 PHY84833_STATUS_CMD_OPEN_OVERRIDE); 10063 } 10064 10065 for (idx = 0; idx < PHY848xx_CMDHDLR_WAIT; idx++) { 10066 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 10067 MDIO_848xx_CMD_HDLR_STATUS, &val); 10068 if (val == PHY84833_STATUS_CMD_OPEN_FOR_CMDS) 10069 break; 10070 usleep_range(1000, 2000); 10071 } 10072 if (idx >= PHY848xx_CMDHDLR_WAIT) { 10073 DP(NETIF_MSG_LINK, "FW cmd: FW not ready.\n"); 10074 /* if the status is CMD_COMPLETE_PASS or CMD_COMPLETE_ERROR 10075 * clear the status to CMD_CLEAR_COMPLETE 10076 */ 10077 if (val == PHY84833_STATUS_CMD_COMPLETE_PASS || 10078 val == PHY84833_STATUS_CMD_COMPLETE_ERROR) { 10079 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, 10080 MDIO_848xx_CMD_HDLR_STATUS, 10081 PHY84833_STATUS_CMD_CLEAR_COMPLETE); 10082 } 10083 return -EINVAL; 10084 } 10085 if (process == PHY84833_MB_PROCESS1 || 10086 process == PHY84833_MB_PROCESS2) { 10087 /* Prepare argument(s) */ 10088 for (idx = 0; idx < argc; idx++) { 10089 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, 10090 MDIO_848xx_CMD_HDLR_DATA1 + idx, 10091 cmd_args[idx]); 10092 } 10093 } 10094 10095 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, 10096 MDIO_848xx_CMD_HDLR_COMMAND, fw_cmd); 10097 for (idx = 0; idx < PHY848xx_CMDHDLR_WAIT; idx++) { 10098 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 10099 MDIO_848xx_CMD_HDLR_STATUS, &val); 10100 if ((val == PHY84833_STATUS_CMD_COMPLETE_PASS) || 10101 (val == PHY84833_STATUS_CMD_COMPLETE_ERROR)) 10102 break; 10103 usleep_range(1000, 2000); 10104 } 10105 if ((idx >= PHY848xx_CMDHDLR_WAIT) || 10106 (val == PHY84833_STATUS_CMD_COMPLETE_ERROR)) { 10107 DP(NETIF_MSG_LINK, "FW cmd failed.\n"); 10108 rc = -EINVAL; 10109 } 10110 if (process == PHY84833_MB_PROCESS3 && rc == 0) { 10111 /* Gather returning data */ 10112 for (idx = 0; idx < argc; idx++) { 10113 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 10114 MDIO_848xx_CMD_HDLR_DATA1 + idx, 10115 &cmd_args[idx]); 10116 } 10117 } 10118 if (val == PHY84833_STATUS_CMD_COMPLETE_ERROR || 10119 val == PHY84833_STATUS_CMD_COMPLETE_PASS) { 10120 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, 10121 MDIO_848xx_CMD_HDLR_STATUS, 10122 PHY84833_STATUS_CMD_CLEAR_COMPLETE); 10123 } 10124 return rc; 10125 } 10126 10127 static int bnx2x_848xx_cmd_hdlr(struct bnx2x_phy *phy, 10128 struct link_params *params, 10129 u16 fw_cmd, 10130 u16 cmd_args[], int argc, 10131 int process) 10132 { 10133 struct bnx2x *bp = params->bp; 10134 10135 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858) || 10136 (REG_RD(bp, params->shmem2_base + 10137 offsetof(struct shmem2_region, 10138 link_attr_sync[params->port])) & 10139 LINK_ATTR_84858)) { 10140 return bnx2x_84858_cmd_hdlr(phy, params, fw_cmd, cmd_args, 10141 argc); 10142 } else { 10143 return bnx2x_84833_cmd_hdlr(phy, params, fw_cmd, cmd_args, 10144 argc, process); 10145 } 10146 } 10147 10148 static int bnx2x_848xx_pair_swap_cfg(struct bnx2x_phy *phy, 10149 struct link_params *params, 10150 struct link_vars *vars) 10151 { 10152 u32 pair_swap; 10153 u16 data[PHY848xx_CMDHDLR_MAX_ARGS]; 10154 int status; 10155 struct bnx2x *bp = params->bp; 10156 10157 /* Check for configuration. */ 10158 pair_swap = REG_RD(bp, params->shmem_base + 10159 offsetof(struct shmem_region, 10160 dev_info.port_hw_config[params->port].xgbt_phy_cfg)) & 10161 PORT_HW_CFG_RJ45_PAIR_SWAP_MASK; 10162 10163 if (pair_swap == 0) 10164 return 0; 10165 10166 /* Only the second argument is used for this command */ 10167 data[1] = (u16)pair_swap; 10168 10169 status = bnx2x_848xx_cmd_hdlr(phy, params, 10170 PHY848xx_CMD_SET_PAIR_SWAP, data, 10171 2, PHY84833_MB_PROCESS2); 10172 if (status == 0) 10173 DP(NETIF_MSG_LINK, "Pairswap OK, val=0x%x\n", data[1]); 10174 10175 return status; 10176 } 10177 10178 static u8 bnx2x_84833_get_reset_gpios(struct bnx2x *bp, 10179 u32 shmem_base_path[], 10180 u32 chip_id) 10181 { 10182 u32 reset_pin[2]; 10183 u32 idx; 10184 u8 reset_gpios; 10185 if (CHIP_IS_E3(bp)) { 10186 /* Assume that these will be GPIOs, not EPIOs. */ 10187 for (idx = 0; idx < 2; idx++) { 10188 /* Map config param to register bit. */ 10189 reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] + 10190 offsetof(struct shmem_region, 10191 dev_info.port_hw_config[0].e3_cmn_pin_cfg)); 10192 reset_pin[idx] = (reset_pin[idx] & 10193 PORT_HW_CFG_E3_PHY_RESET_MASK) >> 10194 PORT_HW_CFG_E3_PHY_RESET_SHIFT; 10195 reset_pin[idx] -= PIN_CFG_GPIO0_P0; 10196 reset_pin[idx] = (1 << reset_pin[idx]); 10197 } 10198 reset_gpios = (u8)(reset_pin[0] | reset_pin[1]); 10199 } else { 10200 /* E2, look from diff place of shmem. */ 10201 for (idx = 0; idx < 2; idx++) { 10202 reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] + 10203 offsetof(struct shmem_region, 10204 dev_info.port_hw_config[0].default_cfg)); 10205 reset_pin[idx] &= PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK; 10206 reset_pin[idx] -= PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0; 10207 reset_pin[idx] >>= PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT; 10208 reset_pin[idx] = (1 << reset_pin[idx]); 10209 } 10210 reset_gpios = (u8)(reset_pin[0] | reset_pin[1]); 10211 } 10212 10213 return reset_gpios; 10214 } 10215 10216 static int bnx2x_84833_hw_reset_phy(struct bnx2x_phy *phy, 10217 struct link_params *params) 10218 { 10219 struct bnx2x *bp = params->bp; 10220 u8 reset_gpios; 10221 u32 other_shmem_base_addr = REG_RD(bp, params->shmem2_base + 10222 offsetof(struct shmem2_region, 10223 other_shmem_base_addr)); 10224 10225 u32 shmem_base_path[2]; 10226 10227 /* Work around for 84833 LED failure inside RESET status */ 10228 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, 10229 MDIO_AN_REG_8481_LEGACY_MII_CTRL, 10230 MDIO_AN_REG_8481_MII_CTRL_FORCE_1G); 10231 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, 10232 MDIO_AN_REG_8481_1G_100T_EXT_CTRL, 10233 MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF); 10234 10235 shmem_base_path[0] = params->shmem_base; 10236 shmem_base_path[1] = other_shmem_base_addr; 10237 10238 reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path, 10239 params->chip_id); 10240 10241 bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW); 10242 udelay(10); 10243 DP(NETIF_MSG_LINK, "84833 hw reset on pin values 0x%x\n", 10244 reset_gpios); 10245 10246 return 0; 10247 } 10248 10249 static int bnx2x_8483x_disable_eee(struct bnx2x_phy *phy, 10250 struct link_params *params, 10251 struct link_vars *vars) 10252 { 10253 int rc; 10254 struct bnx2x *bp = params->bp; 10255 u16 cmd_args = 0; 10256 10257 DP(NETIF_MSG_LINK, "Don't Advertise 10GBase-T EEE\n"); 10258 10259 /* Prevent Phy from working in EEE and advertising it */ 10260 rc = bnx2x_848xx_cmd_hdlr(phy, params, PHY848xx_CMD_SET_EEE_MODE, 10261 &cmd_args, 1, PHY84833_MB_PROCESS1); 10262 if (rc) { 10263 DP(NETIF_MSG_LINK, "EEE disable failed.\n"); 10264 return rc; 10265 } 10266 10267 return bnx2x_eee_disable(phy, params, vars); 10268 } 10269 10270 static int bnx2x_8483x_enable_eee(struct bnx2x_phy *phy, 10271 struct link_params *params, 10272 struct link_vars *vars) 10273 { 10274 int rc; 10275 struct bnx2x *bp = params->bp; 10276 u16 cmd_args = 1; 10277 10278 rc = bnx2x_848xx_cmd_hdlr(phy, params, PHY848xx_CMD_SET_EEE_MODE, 10279 &cmd_args, 1, PHY84833_MB_PROCESS1); 10280 if (rc) { 10281 DP(NETIF_MSG_LINK, "EEE enable failed.\n"); 10282 return rc; 10283 } 10284 10285 return bnx2x_eee_advertise(phy, params, vars, SHMEM_EEE_10G_ADV); 10286 } 10287 10288 #define PHY84833_CONSTANT_LATENCY 1193 10289 static int bnx2x_848x3_config_init(struct bnx2x_phy *phy, 10290 struct link_params *params, 10291 struct link_vars *vars) 10292 { 10293 struct bnx2x *bp = params->bp; 10294 u8 port, initialize = 1; 10295 u16 val; 10296 u32 actual_phy_selection; 10297 u16 cmd_args[PHY848xx_CMDHDLR_MAX_ARGS]; 10298 int rc = 0; 10299 10300 usleep_range(1000, 2000); 10301 10302 if (!(CHIP_IS_E1x(bp))) 10303 port = BP_PATH(bp); 10304 else 10305 port = params->port; 10306 10307 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) { 10308 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3, 10309 MISC_REGISTERS_GPIO_OUTPUT_HIGH, 10310 port); 10311 } else { 10312 /* MDIO reset */ 10313 bnx2x_cl45_write(bp, phy, 10314 MDIO_PMA_DEVAD, 10315 MDIO_PMA_REG_CTRL, 0x8000); 10316 } 10317 10318 bnx2x_wait_reset_complete(bp, phy, params); 10319 10320 /* Wait for GPHY to come out of reset */ 10321 msleep(50); 10322 if (!bnx2x_is_8483x_8485x(phy)) { 10323 /* BCM84823 requires that XGXS links up first @ 10G for normal 10324 * behavior. 10325 */ 10326 u16 temp; 10327 temp = vars->line_speed; 10328 vars->line_speed = SPEED_10000; 10329 bnx2x_set_autoneg(¶ms->phy[INT_PHY], params, vars, 0); 10330 bnx2x_program_serdes(¶ms->phy[INT_PHY], params, vars); 10331 vars->line_speed = temp; 10332 } 10333 /* Check if this is actually BCM84858 */ 10334 if (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858) { 10335 u16 hw_rev; 10336 10337 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, 10338 MDIO_AN_REG_848xx_ID_MSB, &hw_rev); 10339 if (hw_rev == BCM84858_PHY_ID) { 10340 params->link_attr_sync |= LINK_ATTR_84858; 10341 bnx2x_update_link_attr(params, params->link_attr_sync); 10342 } 10343 } 10344 10345 /* Set dual-media configuration according to configuration */ 10346 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 10347 MDIO_CTL_REG_84823_MEDIA, &val); 10348 val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK | 10349 MDIO_CTL_REG_84823_MEDIA_LINE_MASK | 10350 MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN | 10351 MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK | 10352 MDIO_CTL_REG_84823_MEDIA_FIBER_1G); 10353 10354 if (CHIP_IS_E3(bp)) { 10355 val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK | 10356 MDIO_CTL_REG_84823_MEDIA_LINE_MASK); 10357 } else { 10358 val |= (MDIO_CTL_REG_84823_CTRL_MAC_XFI | 10359 MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L); 10360 } 10361 10362 actual_phy_selection = bnx2x_phy_selection(params); 10363 10364 switch (actual_phy_selection) { 10365 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT: 10366 /* Do nothing. Essentially this is like the priority copper */ 10367 break; 10368 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY: 10369 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER; 10370 break; 10371 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY: 10372 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER; 10373 break; 10374 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY: 10375 /* Do nothing here. The first PHY won't be initialized at all */ 10376 break; 10377 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY: 10378 val |= MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN; 10379 initialize = 0; 10380 break; 10381 } 10382 if (params->phy[EXT_PHY2].req_line_speed == SPEED_1000) 10383 val |= MDIO_CTL_REG_84823_MEDIA_FIBER_1G; 10384 10385 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, 10386 MDIO_CTL_REG_84823_MEDIA, val); 10387 DP(NETIF_MSG_LINK, "Multi_phy config = 0x%x, Media control = 0x%x\n", 10388 params->multi_phy_config, val); 10389 10390 if (bnx2x_is_8483x_8485x(phy)) { 10391 bnx2x_848xx_pair_swap_cfg(phy, params, vars); 10392 10393 /* Keep AutogrEEEn disabled. */ 10394 cmd_args[0] = 0x0; 10395 cmd_args[1] = 0x0; 10396 cmd_args[2] = PHY84833_CONSTANT_LATENCY + 1; 10397 cmd_args[3] = PHY84833_CONSTANT_LATENCY; 10398 rc = bnx2x_848xx_cmd_hdlr(phy, params, 10399 PHY848xx_CMD_SET_EEE_MODE, cmd_args, 10400 4, PHY84833_MB_PROCESS1); 10401 if (rc) 10402 DP(NETIF_MSG_LINK, "Cfg AutogrEEEn failed.\n"); 10403 } 10404 if (initialize) 10405 rc = bnx2x_848xx_cmn_config_init(phy, params, vars); 10406 else 10407 bnx2x_save_848xx_spirom_version(phy, bp, params->port); 10408 /* 84833 PHY has a better feature and doesn't need to support this. */ 10409 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) { 10410 u32 cms_enable = REG_RD(bp, params->shmem_base + 10411 offsetof(struct shmem_region, 10412 dev_info.port_hw_config[params->port].default_cfg)) & 10413 PORT_HW_CFG_ENABLE_CMS_MASK; 10414 10415 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 10416 MDIO_CTL_REG_84823_USER_CTRL_REG, &val); 10417 if (cms_enable) 10418 val |= MDIO_CTL_REG_84823_USER_CTRL_CMS; 10419 else 10420 val &= ~MDIO_CTL_REG_84823_USER_CTRL_CMS; 10421 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, 10422 MDIO_CTL_REG_84823_USER_CTRL_REG, val); 10423 } 10424 10425 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 10426 MDIO_84833_TOP_CFG_FW_REV, &val); 10427 10428 /* Configure EEE support */ 10429 if ((val >= MDIO_84833_TOP_CFG_FW_EEE) && 10430 (val != MDIO_84833_TOP_CFG_FW_NO_EEE) && 10431 bnx2x_eee_has_cap(params)) { 10432 rc = bnx2x_eee_initial_config(params, vars, SHMEM_EEE_10G_ADV); 10433 if (rc) { 10434 DP(NETIF_MSG_LINK, "Failed to configure EEE timers\n"); 10435 bnx2x_8483x_disable_eee(phy, params, vars); 10436 return rc; 10437 } 10438 10439 if ((phy->req_duplex == DUPLEX_FULL) && 10440 (params->eee_mode & EEE_MODE_ADV_LPI) && 10441 (bnx2x_eee_calc_timer(params) || 10442 !(params->eee_mode & EEE_MODE_ENABLE_LPI))) 10443 rc = bnx2x_8483x_enable_eee(phy, params, vars); 10444 else 10445 rc = bnx2x_8483x_disable_eee(phy, params, vars); 10446 if (rc) { 10447 DP(NETIF_MSG_LINK, "Failed to set EEE advertisement\n"); 10448 return rc; 10449 } 10450 } else { 10451 vars->eee_status &= ~SHMEM_EEE_SUPPORTED_MASK; 10452 } 10453 10454 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) { 10455 /* Additional settings for jumbo packets in 1000BASE-T mode */ 10456 /* Allow rx extended length */ 10457 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, 10458 MDIO_AN_REG_8481_AUX_CTRL, &val); 10459 val |= 0x4000; 10460 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, 10461 MDIO_AN_REG_8481_AUX_CTRL, val); 10462 /* TX FIFO Elasticity LSB */ 10463 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, 10464 MDIO_AN_REG_8481_1G_100T_EXT_CTRL, &val); 10465 val |= 0x1; 10466 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, 10467 MDIO_AN_REG_8481_1G_100T_EXT_CTRL, val); 10468 /* TX FIFO Elasticity MSB */ 10469 /* Enable expansion register 0x46 (Pattern Generator status) */ 10470 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, 10471 MDIO_AN_REG_8481_EXPANSION_REG_ACCESS, 0xf46); 10472 10473 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, 10474 MDIO_AN_REG_8481_EXPANSION_REG_RD_RW, &val); 10475 val |= 0x4000; 10476 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, 10477 MDIO_AN_REG_8481_EXPANSION_REG_RD_RW, val); 10478 } 10479 10480 if (bnx2x_is_8483x_8485x(phy)) { 10481 /* Bring PHY out of super isolate mode as the final step. */ 10482 bnx2x_cl45_read_and_write(bp, phy, 10483 MDIO_CTL_DEVAD, 10484 MDIO_84833_TOP_CFG_XGPHY_STRAP1, 10485 (u16)~MDIO_84833_SUPER_ISOLATE); 10486 } 10487 return rc; 10488 } 10489 10490 static u8 bnx2x_848xx_read_status(struct bnx2x_phy *phy, 10491 struct link_params *params, 10492 struct link_vars *vars) 10493 { 10494 struct bnx2x *bp = params->bp; 10495 u16 val, val1, val2; 10496 u8 link_up = 0; 10497 10498 10499 /* Check 10G-BaseT link status */ 10500 /* Check PMD signal ok */ 10501 bnx2x_cl45_read(bp, phy, 10502 MDIO_AN_DEVAD, 0xFFFA, &val1); 10503 bnx2x_cl45_read(bp, phy, 10504 MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_PMD_SIGNAL, 10505 &val2); 10506 DP(NETIF_MSG_LINK, "BCM848xx: PMD_SIGNAL 1.a811 = 0x%x\n", val2); 10507 10508 /* Check link 10G */ 10509 if (val2 & (1<<11)) { 10510 vars->line_speed = SPEED_10000; 10511 vars->duplex = DUPLEX_FULL; 10512 link_up = 1; 10513 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars); 10514 } else { /* Check Legacy speed link */ 10515 u16 legacy_status, legacy_speed; 10516 10517 /* Enable expansion register 0x42 (Operation mode status) */ 10518 bnx2x_cl45_write(bp, phy, 10519 MDIO_AN_DEVAD, 10520 MDIO_AN_REG_8481_EXPANSION_REG_ACCESS, 0xf42); 10521 10522 /* Get legacy speed operation status */ 10523 bnx2x_cl45_read(bp, phy, 10524 MDIO_AN_DEVAD, 10525 MDIO_AN_REG_8481_EXPANSION_REG_RD_RW, 10526 &legacy_status); 10527 10528 DP(NETIF_MSG_LINK, "Legacy speed status = 0x%x\n", 10529 legacy_status); 10530 link_up = ((legacy_status & (1<<11)) == (1<<11)); 10531 legacy_speed = (legacy_status & (3<<9)); 10532 if (legacy_speed == (0<<9)) 10533 vars->line_speed = SPEED_10; 10534 else if (legacy_speed == (1<<9)) 10535 vars->line_speed = SPEED_100; 10536 else if (legacy_speed == (2<<9)) 10537 vars->line_speed = SPEED_1000; 10538 else { /* Should not happen: Treat as link down */ 10539 vars->line_speed = 0; 10540 link_up = 0; 10541 } 10542 10543 if (link_up) { 10544 if (legacy_status & (1<<8)) 10545 vars->duplex = DUPLEX_FULL; 10546 else 10547 vars->duplex = DUPLEX_HALF; 10548 10549 DP(NETIF_MSG_LINK, 10550 "Link is up in %dMbps, is_duplex_full= %d\n", 10551 vars->line_speed, 10552 (vars->duplex == DUPLEX_FULL)); 10553 /* Check legacy speed AN resolution */ 10554 bnx2x_cl45_read(bp, phy, 10555 MDIO_AN_DEVAD, 10556 MDIO_AN_REG_8481_LEGACY_MII_STATUS, 10557 &val); 10558 if (val & (1<<5)) 10559 vars->link_status |= 10560 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; 10561 bnx2x_cl45_read(bp, phy, 10562 MDIO_AN_DEVAD, 10563 MDIO_AN_REG_8481_LEGACY_AN_EXPANSION, 10564 &val); 10565 if ((val & (1<<0)) == 0) 10566 vars->link_status |= 10567 LINK_STATUS_PARALLEL_DETECTION_USED; 10568 } 10569 } 10570 if (link_up) { 10571 DP(NETIF_MSG_LINK, "BCM848x3: link speed is %d\n", 10572 vars->line_speed); 10573 bnx2x_ext_phy_resolve_fc(phy, params, vars); 10574 10575 /* Read LP advertised speeds */ 10576 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, 10577 MDIO_AN_REG_CL37_FC_LP, &val); 10578 if (val & (1<<5)) 10579 vars->link_status |= 10580 LINK_STATUS_LINK_PARTNER_10THD_CAPABLE; 10581 if (val & (1<<6)) 10582 vars->link_status |= 10583 LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE; 10584 if (val & (1<<7)) 10585 vars->link_status |= 10586 LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE; 10587 if (val & (1<<8)) 10588 vars->link_status |= 10589 LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE; 10590 if (val & (1<<9)) 10591 vars->link_status |= 10592 LINK_STATUS_LINK_PARTNER_100T4_CAPABLE; 10593 10594 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, 10595 MDIO_AN_REG_1000T_STATUS, &val); 10596 10597 if (val & (1<<10)) 10598 vars->link_status |= 10599 LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE; 10600 if (val & (1<<11)) 10601 vars->link_status |= 10602 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; 10603 10604 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, 10605 MDIO_AN_REG_MASTER_STATUS, &val); 10606 10607 if (val & (1<<11)) 10608 vars->link_status |= 10609 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; 10610 10611 /* Determine if EEE was negotiated */ 10612 if (bnx2x_is_8483x_8485x(phy)) 10613 bnx2x_eee_an_resolve(phy, params, vars); 10614 } 10615 10616 return link_up; 10617 } 10618 10619 static int bnx2x_8485x_format_ver(u32 raw_ver, u8 *str, u16 *len) 10620 { 10621 u32 num; 10622 10623 num = ((raw_ver & 0xF80) >> 7) << 16 | ((raw_ver & 0x7F) << 8) | 10624 ((raw_ver & 0xF000) >> 12); 10625 return bnx2x_3_seq_format_ver(num, str, len); 10626 } 10627 10628 static int bnx2x_848xx_format_ver(u32 raw_ver, u8 *str, u16 *len) 10629 { 10630 u32 spirom_ver; 10631 10632 spirom_ver = ((raw_ver & 0xF80) >> 7) << 16 | (raw_ver & 0x7F); 10633 return bnx2x_format_ver(spirom_ver, str, len); 10634 } 10635 10636 static void bnx2x_8481_hw_reset(struct bnx2x_phy *phy, 10637 struct link_params *params) 10638 { 10639 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1, 10640 MISC_REGISTERS_GPIO_OUTPUT_LOW, 0); 10641 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1, 10642 MISC_REGISTERS_GPIO_OUTPUT_LOW, 1); 10643 } 10644 10645 static void bnx2x_8481_link_reset(struct bnx2x_phy *phy, 10646 struct link_params *params) 10647 { 10648 bnx2x_cl45_write(params->bp, phy, 10649 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000); 10650 bnx2x_cl45_write(params->bp, phy, 10651 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1); 10652 } 10653 10654 static void bnx2x_848x3_link_reset(struct bnx2x_phy *phy, 10655 struct link_params *params) 10656 { 10657 struct bnx2x *bp = params->bp; 10658 u8 port; 10659 u16 val16; 10660 10661 if (!(CHIP_IS_E1x(bp))) 10662 port = BP_PATH(bp); 10663 else 10664 port = params->port; 10665 10666 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) { 10667 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3, 10668 MISC_REGISTERS_GPIO_OUTPUT_LOW, 10669 port); 10670 } else { 10671 bnx2x_cl45_read(bp, phy, 10672 MDIO_CTL_DEVAD, 10673 MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val16); 10674 val16 |= MDIO_84833_SUPER_ISOLATE; 10675 bnx2x_cl45_write(bp, phy, 10676 MDIO_CTL_DEVAD, 10677 MDIO_84833_TOP_CFG_XGPHY_STRAP1, val16); 10678 } 10679 } 10680 10681 static void bnx2x_848xx_set_link_led(struct bnx2x_phy *phy, 10682 struct link_params *params, u8 mode) 10683 { 10684 struct bnx2x *bp = params->bp; 10685 u16 val; 10686 u8 port; 10687 10688 if (!(CHIP_IS_E1x(bp))) 10689 port = BP_PATH(bp); 10690 else 10691 port = params->port; 10692 10693 switch (mode) { 10694 case LED_MODE_OFF: 10695 10696 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OFF\n", port); 10697 10698 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) == 10699 SHARED_HW_CFG_LED_EXTPHY1) { 10700 10701 /* Set LED masks */ 10702 bnx2x_cl45_write(bp, phy, 10703 MDIO_PMA_DEVAD, 10704 MDIO_PMA_REG_8481_LED1_MASK, 10705 0x0); 10706 10707 bnx2x_cl45_write(bp, phy, 10708 MDIO_PMA_DEVAD, 10709 MDIO_PMA_REG_8481_LED2_MASK, 10710 0x0); 10711 10712 bnx2x_cl45_write(bp, phy, 10713 MDIO_PMA_DEVAD, 10714 MDIO_PMA_REG_8481_LED3_MASK, 10715 0x0); 10716 10717 bnx2x_cl45_write(bp, phy, 10718 MDIO_PMA_DEVAD, 10719 MDIO_PMA_REG_8481_LED5_MASK, 10720 0x0); 10721 10722 } else { 10723 /* LED 1 OFF */ 10724 bnx2x_cl45_write(bp, phy, 10725 MDIO_PMA_DEVAD, 10726 MDIO_PMA_REG_8481_LED1_MASK, 10727 0x0); 10728 10729 if (phy->type == 10730 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858) { 10731 /* LED 2 OFF */ 10732 bnx2x_cl45_write(bp, phy, 10733 MDIO_PMA_DEVAD, 10734 MDIO_PMA_REG_8481_LED2_MASK, 10735 0x0); 10736 /* LED 3 OFF */ 10737 bnx2x_cl45_write(bp, phy, 10738 MDIO_PMA_DEVAD, 10739 MDIO_PMA_REG_8481_LED3_MASK, 10740 0x0); 10741 } 10742 } 10743 break; 10744 case LED_MODE_FRONT_PANEL_OFF: 10745 10746 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE FRONT PANEL OFF\n", 10747 port); 10748 10749 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) == 10750 SHARED_HW_CFG_LED_EXTPHY1) { 10751 10752 /* Set LED masks */ 10753 bnx2x_cl45_write(bp, phy, 10754 MDIO_PMA_DEVAD, 10755 MDIO_PMA_REG_8481_LED1_MASK, 10756 0x0); 10757 10758 bnx2x_cl45_write(bp, phy, 10759 MDIO_PMA_DEVAD, 10760 MDIO_PMA_REG_8481_LED2_MASK, 10761 0x0); 10762 10763 bnx2x_cl45_write(bp, phy, 10764 MDIO_PMA_DEVAD, 10765 MDIO_PMA_REG_8481_LED3_MASK, 10766 0x0); 10767 10768 bnx2x_cl45_write(bp, phy, 10769 MDIO_PMA_DEVAD, 10770 MDIO_PMA_REG_8481_LED5_MASK, 10771 0x20); 10772 10773 } else { 10774 bnx2x_cl45_write(bp, phy, 10775 MDIO_PMA_DEVAD, 10776 MDIO_PMA_REG_8481_LED1_MASK, 10777 0x0); 10778 if (phy->type == 10779 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) { 10780 /* Disable MI_INT interrupt before setting LED4 10781 * source to constant off. 10782 */ 10783 if (REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + 10784 params->port*4) & 10785 NIG_MASK_MI_INT) { 10786 params->link_flags |= 10787 LINK_FLAGS_INT_DISABLED; 10788 10789 bnx2x_bits_dis( 10790 bp, 10791 NIG_REG_MASK_INTERRUPT_PORT0 + 10792 params->port*4, 10793 NIG_MASK_MI_INT); 10794 } 10795 bnx2x_cl45_write(bp, phy, 10796 MDIO_PMA_DEVAD, 10797 MDIO_PMA_REG_8481_SIGNAL_MASK, 10798 0x0); 10799 } 10800 if (phy->type == 10801 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858) { 10802 /* LED 2 OFF */ 10803 bnx2x_cl45_write(bp, phy, 10804 MDIO_PMA_DEVAD, 10805 MDIO_PMA_REG_8481_LED2_MASK, 10806 0x0); 10807 /* LED 3 OFF */ 10808 bnx2x_cl45_write(bp, phy, 10809 MDIO_PMA_DEVAD, 10810 MDIO_PMA_REG_8481_LED3_MASK, 10811 0x0); 10812 } 10813 } 10814 break; 10815 case LED_MODE_ON: 10816 10817 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE ON\n", port); 10818 10819 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) == 10820 SHARED_HW_CFG_LED_EXTPHY1) { 10821 /* Set control reg */ 10822 bnx2x_cl45_read(bp, phy, 10823 MDIO_PMA_DEVAD, 10824 MDIO_PMA_REG_8481_LINK_SIGNAL, 10825 &val); 10826 val &= 0x8000; 10827 val |= 0x2492; 10828 10829 bnx2x_cl45_write(bp, phy, 10830 MDIO_PMA_DEVAD, 10831 MDIO_PMA_REG_8481_LINK_SIGNAL, 10832 val); 10833 10834 /* Set LED masks */ 10835 bnx2x_cl45_write(bp, phy, 10836 MDIO_PMA_DEVAD, 10837 MDIO_PMA_REG_8481_LED1_MASK, 10838 0x0); 10839 10840 bnx2x_cl45_write(bp, phy, 10841 MDIO_PMA_DEVAD, 10842 MDIO_PMA_REG_8481_LED2_MASK, 10843 0x20); 10844 10845 bnx2x_cl45_write(bp, phy, 10846 MDIO_PMA_DEVAD, 10847 MDIO_PMA_REG_8481_LED3_MASK, 10848 0x20); 10849 10850 bnx2x_cl45_write(bp, phy, 10851 MDIO_PMA_DEVAD, 10852 MDIO_PMA_REG_8481_LED5_MASK, 10853 0x0); 10854 } else { 10855 bnx2x_cl45_write(bp, phy, 10856 MDIO_PMA_DEVAD, 10857 MDIO_PMA_REG_8481_LED1_MASK, 10858 0x20); 10859 if (phy->type == 10860 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) { 10861 /* Disable MI_INT interrupt before setting LED4 10862 * source to constant on. 10863 */ 10864 if (REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + 10865 params->port*4) & 10866 NIG_MASK_MI_INT) { 10867 params->link_flags |= 10868 LINK_FLAGS_INT_DISABLED; 10869 10870 bnx2x_bits_dis( 10871 bp, 10872 NIG_REG_MASK_INTERRUPT_PORT0 + 10873 params->port*4, 10874 NIG_MASK_MI_INT); 10875 } 10876 } 10877 if (phy->type == 10878 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858) { 10879 /* Tell LED3 to constant on */ 10880 bnx2x_cl45_read(bp, phy, 10881 MDIO_PMA_DEVAD, 10882 MDIO_PMA_REG_8481_LINK_SIGNAL, 10883 &val); 10884 val &= ~(7<<6); 10885 val |= (2<<6); /* A83B[8:6]= 2 */ 10886 bnx2x_cl45_write(bp, phy, 10887 MDIO_PMA_DEVAD, 10888 MDIO_PMA_REG_8481_LINK_SIGNAL, 10889 val); 10890 bnx2x_cl45_write(bp, phy, 10891 MDIO_PMA_DEVAD, 10892 MDIO_PMA_REG_8481_LED3_MASK, 10893 0x20); 10894 } else { 10895 bnx2x_cl45_write(bp, phy, 10896 MDIO_PMA_DEVAD, 10897 MDIO_PMA_REG_8481_SIGNAL_MASK, 10898 0x20); 10899 } 10900 } 10901 break; 10902 10903 case LED_MODE_OPER: 10904 10905 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OPER\n", port); 10906 10907 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) == 10908 SHARED_HW_CFG_LED_EXTPHY1) { 10909 10910 /* Set control reg */ 10911 bnx2x_cl45_read(bp, phy, 10912 MDIO_PMA_DEVAD, 10913 MDIO_PMA_REG_8481_LINK_SIGNAL, 10914 &val); 10915 10916 if (!((val & 10917 MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK) 10918 >> MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT)) { 10919 DP(NETIF_MSG_LINK, "Setting LINK_SIGNAL\n"); 10920 bnx2x_cl45_write(bp, phy, 10921 MDIO_PMA_DEVAD, 10922 MDIO_PMA_REG_8481_LINK_SIGNAL, 10923 0xa492); 10924 } 10925 10926 /* Set LED masks */ 10927 bnx2x_cl45_write(bp, phy, 10928 MDIO_PMA_DEVAD, 10929 MDIO_PMA_REG_8481_LED1_MASK, 10930 0x10); 10931 10932 bnx2x_cl45_write(bp, phy, 10933 MDIO_PMA_DEVAD, 10934 MDIO_PMA_REG_8481_LED2_MASK, 10935 0x80); 10936 10937 bnx2x_cl45_write(bp, phy, 10938 MDIO_PMA_DEVAD, 10939 MDIO_PMA_REG_8481_LED3_MASK, 10940 0x98); 10941 10942 bnx2x_cl45_write(bp, phy, 10943 MDIO_PMA_DEVAD, 10944 MDIO_PMA_REG_8481_LED5_MASK, 10945 0x40); 10946 10947 } else { 10948 /* EXTPHY2 LED mode indicate that the 100M/1G/10G LED 10949 * sources are all wired through LED1, rather than only 10950 * 10G in other modes. 10951 */ 10952 val = ((params->hw_led_mode << 10953 SHARED_HW_CFG_LED_MODE_SHIFT) == 10954 SHARED_HW_CFG_LED_EXTPHY2) ? 0x98 : 0x80; 10955 10956 bnx2x_cl45_write(bp, phy, 10957 MDIO_PMA_DEVAD, 10958 MDIO_PMA_REG_8481_LED1_MASK, 10959 val); 10960 10961 /* Tell LED3 to blink on source */ 10962 bnx2x_cl45_read(bp, phy, 10963 MDIO_PMA_DEVAD, 10964 MDIO_PMA_REG_8481_LINK_SIGNAL, 10965 &val); 10966 val &= ~(7<<6); 10967 val |= (1<<6); /* A83B[8:6]= 1 */ 10968 bnx2x_cl45_write(bp, phy, 10969 MDIO_PMA_DEVAD, 10970 MDIO_PMA_REG_8481_LINK_SIGNAL, 10971 val); 10972 if (phy->type == 10973 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858) { 10974 bnx2x_cl45_write(bp, phy, 10975 MDIO_PMA_DEVAD, 10976 MDIO_PMA_REG_8481_LED2_MASK, 10977 0x18); 10978 bnx2x_cl45_write(bp, phy, 10979 MDIO_PMA_DEVAD, 10980 MDIO_PMA_REG_8481_LED3_MASK, 10981 0x06); 10982 } 10983 if (phy->type == 10984 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) { 10985 /* Restore LED4 source to external link, 10986 * and re-enable interrupts. 10987 */ 10988 bnx2x_cl45_write(bp, phy, 10989 MDIO_PMA_DEVAD, 10990 MDIO_PMA_REG_8481_SIGNAL_MASK, 10991 0x40); 10992 if (params->link_flags & 10993 LINK_FLAGS_INT_DISABLED) { 10994 bnx2x_link_int_enable(params); 10995 params->link_flags &= 10996 ~LINK_FLAGS_INT_DISABLED; 10997 } 10998 } 10999 } 11000 break; 11001 } 11002 11003 /* This is a workaround for E3+84833 until autoneg 11004 * restart is fixed in f/w 11005 */ 11006 if (CHIP_IS_E3(bp)) { 11007 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 11008 MDIO_WC_REG_GP2_STATUS_GP_2_1, &val); 11009 } 11010 } 11011 11012 /******************************************************************/ 11013 /* 54618SE PHY SECTION */ 11014 /******************************************************************/ 11015 static void bnx2x_54618se_specific_func(struct bnx2x_phy *phy, 11016 struct link_params *params, 11017 u32 action) 11018 { 11019 struct bnx2x *bp = params->bp; 11020 u16 temp; 11021 switch (action) { 11022 case PHY_INIT: 11023 /* Configure LED4: set to INTR (0x6). */ 11024 /* Accessing shadow register 0xe. */ 11025 bnx2x_cl22_write(bp, phy, 11026 MDIO_REG_GPHY_SHADOW, 11027 MDIO_REG_GPHY_SHADOW_LED_SEL2); 11028 bnx2x_cl22_read(bp, phy, 11029 MDIO_REG_GPHY_SHADOW, 11030 &temp); 11031 temp &= ~(0xf << 4); 11032 temp |= (0x6 << 4); 11033 bnx2x_cl22_write(bp, phy, 11034 MDIO_REG_GPHY_SHADOW, 11035 MDIO_REG_GPHY_SHADOW_WR_ENA | temp); 11036 /* Configure INTR based on link status change. */ 11037 bnx2x_cl22_write(bp, phy, 11038 MDIO_REG_INTR_MASK, 11039 ~MDIO_REG_INTR_MASK_LINK_STATUS); 11040 break; 11041 } 11042 } 11043 11044 static int bnx2x_54618se_config_init(struct bnx2x_phy *phy, 11045 struct link_params *params, 11046 struct link_vars *vars) 11047 { 11048 struct bnx2x *bp = params->bp; 11049 u8 port; 11050 u16 autoneg_val, an_1000_val, an_10_100_val, fc_val, temp; 11051 u32 cfg_pin; 11052 11053 DP(NETIF_MSG_LINK, "54618SE cfg init\n"); 11054 usleep_range(1000, 2000); 11055 11056 /* This works with E3 only, no need to check the chip 11057 * before determining the port. 11058 */ 11059 port = params->port; 11060 11061 cfg_pin = (REG_RD(bp, params->shmem_base + 11062 offsetof(struct shmem_region, 11063 dev_info.port_hw_config[port].e3_cmn_pin_cfg)) & 11064 PORT_HW_CFG_E3_PHY_RESET_MASK) >> 11065 PORT_HW_CFG_E3_PHY_RESET_SHIFT; 11066 11067 /* Drive pin high to bring the GPHY out of reset. */ 11068 bnx2x_set_cfg_pin(bp, cfg_pin, 1); 11069 11070 /* wait for GPHY to reset */ 11071 msleep(50); 11072 11073 /* reset phy */ 11074 bnx2x_cl22_write(bp, phy, 11075 MDIO_PMA_REG_CTRL, 0x8000); 11076 bnx2x_wait_reset_complete(bp, phy, params); 11077 11078 /* Wait for GPHY to reset */ 11079 msleep(50); 11080 11081 11082 bnx2x_54618se_specific_func(phy, params, PHY_INIT); 11083 /* Flip the signal detect polarity (set 0x1c.0x1e[8]). */ 11084 bnx2x_cl22_write(bp, phy, 11085 MDIO_REG_GPHY_SHADOW, 11086 MDIO_REG_GPHY_SHADOW_AUTO_DET_MED); 11087 bnx2x_cl22_read(bp, phy, 11088 MDIO_REG_GPHY_SHADOW, 11089 &temp); 11090 temp |= MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD; 11091 bnx2x_cl22_write(bp, phy, 11092 MDIO_REG_GPHY_SHADOW, 11093 MDIO_REG_GPHY_SHADOW_WR_ENA | temp); 11094 11095 /* Set up fc */ 11096 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */ 11097 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); 11098 fc_val = 0; 11099 if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) == 11100 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) 11101 fc_val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC; 11102 11103 if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) == 11104 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) 11105 fc_val |= MDIO_AN_REG_ADV_PAUSE_PAUSE; 11106 11107 /* Read all advertisement */ 11108 bnx2x_cl22_read(bp, phy, 11109 0x09, 11110 &an_1000_val); 11111 11112 bnx2x_cl22_read(bp, phy, 11113 0x04, 11114 &an_10_100_val); 11115 11116 bnx2x_cl22_read(bp, phy, 11117 MDIO_PMA_REG_CTRL, 11118 &autoneg_val); 11119 11120 /* Disable forced speed */ 11121 autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13)); 11122 an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8) | (1<<10) | 11123 (1<<11)); 11124 11125 if (((phy->req_line_speed == SPEED_AUTO_NEG) && 11126 (phy->speed_cap_mask & 11127 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) || 11128 (phy->req_line_speed == SPEED_1000)) { 11129 an_1000_val |= (1<<8); 11130 autoneg_val |= (1<<9 | 1<<12); 11131 if (phy->req_duplex == DUPLEX_FULL) 11132 an_1000_val |= (1<<9); 11133 DP(NETIF_MSG_LINK, "Advertising 1G\n"); 11134 } else 11135 an_1000_val &= ~((1<<8) | (1<<9)); 11136 11137 bnx2x_cl22_write(bp, phy, 11138 0x09, 11139 an_1000_val); 11140 bnx2x_cl22_read(bp, phy, 11141 0x09, 11142 &an_1000_val); 11143 11144 /* Advertise 10/100 link speed */ 11145 if (phy->req_line_speed == SPEED_AUTO_NEG) { 11146 if (phy->speed_cap_mask & 11147 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF) { 11148 an_10_100_val |= (1<<5); 11149 autoneg_val |= (1<<9 | 1<<12); 11150 DP(NETIF_MSG_LINK, "Advertising 10M-HD\n"); 11151 } 11152 if (phy->speed_cap_mask & 11153 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) { 11154 an_10_100_val |= (1<<6); 11155 autoneg_val |= (1<<9 | 1<<12); 11156 DP(NETIF_MSG_LINK, "Advertising 10M-FD\n"); 11157 } 11158 if (phy->speed_cap_mask & 11159 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF) { 11160 an_10_100_val |= (1<<7); 11161 autoneg_val |= (1<<9 | 1<<12); 11162 DP(NETIF_MSG_LINK, "Advertising 100M-HD\n"); 11163 } 11164 if (phy->speed_cap_mask & 11165 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL) { 11166 an_10_100_val |= (1<<8); 11167 autoneg_val |= (1<<9 | 1<<12); 11168 DP(NETIF_MSG_LINK, "Advertising 100M-FD\n"); 11169 } 11170 } 11171 11172 /* Only 10/100 are allowed to work in FORCE mode */ 11173 if (phy->req_line_speed == SPEED_100) { 11174 autoneg_val |= (1<<13); 11175 /* Enabled AUTO-MDIX when autoneg is disabled */ 11176 bnx2x_cl22_write(bp, phy, 11177 0x18, 11178 (1<<15 | 1<<9 | 7<<0)); 11179 DP(NETIF_MSG_LINK, "Setting 100M force\n"); 11180 } 11181 if (phy->req_line_speed == SPEED_10) { 11182 /* Enabled AUTO-MDIX when autoneg is disabled */ 11183 bnx2x_cl22_write(bp, phy, 11184 0x18, 11185 (1<<15 | 1<<9 | 7<<0)); 11186 DP(NETIF_MSG_LINK, "Setting 10M force\n"); 11187 } 11188 11189 if ((phy->flags & FLAGS_EEE) && bnx2x_eee_has_cap(params)) { 11190 int rc; 11191 11192 bnx2x_cl22_write(bp, phy, MDIO_REG_GPHY_EXP_ACCESS, 11193 MDIO_REG_GPHY_EXP_ACCESS_TOP | 11194 MDIO_REG_GPHY_EXP_TOP_2K_BUF); 11195 bnx2x_cl22_read(bp, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, &temp); 11196 temp &= 0xfffe; 11197 bnx2x_cl22_write(bp, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, temp); 11198 11199 rc = bnx2x_eee_initial_config(params, vars, SHMEM_EEE_1G_ADV); 11200 if (rc) { 11201 DP(NETIF_MSG_LINK, "Failed to configure EEE timers\n"); 11202 bnx2x_eee_disable(phy, params, vars); 11203 } else if ((params->eee_mode & EEE_MODE_ADV_LPI) && 11204 (phy->req_duplex == DUPLEX_FULL) && 11205 (bnx2x_eee_calc_timer(params) || 11206 !(params->eee_mode & EEE_MODE_ENABLE_LPI))) { 11207 /* Need to advertise EEE only when requested, 11208 * and either no LPI assertion was requested, 11209 * or it was requested and a valid timer was set. 11210 * Also notice full duplex is required for EEE. 11211 */ 11212 bnx2x_eee_advertise(phy, params, vars, 11213 SHMEM_EEE_1G_ADV); 11214 } else { 11215 DP(NETIF_MSG_LINK, "Don't Advertise 1GBase-T EEE\n"); 11216 bnx2x_eee_disable(phy, params, vars); 11217 } 11218 } else { 11219 vars->eee_status &= ~SHMEM_EEE_1G_ADV << 11220 SHMEM_EEE_SUPPORTED_SHIFT; 11221 11222 if (phy->flags & FLAGS_EEE) { 11223 /* Handle legacy auto-grEEEn */ 11224 if (params->feature_config_flags & 11225 FEATURE_CONFIG_AUTOGREEEN_ENABLED) { 11226 temp = 6; 11227 DP(NETIF_MSG_LINK, "Enabling Auto-GrEEEn\n"); 11228 } else { 11229 temp = 0; 11230 DP(NETIF_MSG_LINK, "Don't Adv. EEE\n"); 11231 } 11232 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, 11233 MDIO_AN_REG_EEE_ADV, temp); 11234 } 11235 } 11236 11237 bnx2x_cl22_write(bp, phy, 11238 0x04, 11239 an_10_100_val | fc_val); 11240 11241 if (phy->req_duplex == DUPLEX_FULL) 11242 autoneg_val |= (1<<8); 11243 11244 bnx2x_cl22_write(bp, phy, 11245 MDIO_PMA_REG_CTRL, autoneg_val); 11246 11247 return 0; 11248 } 11249 11250 11251 static void bnx2x_5461x_set_link_led(struct bnx2x_phy *phy, 11252 struct link_params *params, u8 mode) 11253 { 11254 struct bnx2x *bp = params->bp; 11255 u16 temp; 11256 11257 bnx2x_cl22_write(bp, phy, 11258 MDIO_REG_GPHY_SHADOW, 11259 MDIO_REG_GPHY_SHADOW_LED_SEL1); 11260 bnx2x_cl22_read(bp, phy, 11261 MDIO_REG_GPHY_SHADOW, 11262 &temp); 11263 temp &= 0xff00; 11264 11265 DP(NETIF_MSG_LINK, "54618x set link led (mode=%x)\n", mode); 11266 switch (mode) { 11267 case LED_MODE_FRONT_PANEL_OFF: 11268 case LED_MODE_OFF: 11269 temp |= 0x00ee; 11270 break; 11271 case LED_MODE_OPER: 11272 temp |= 0x0001; 11273 break; 11274 case LED_MODE_ON: 11275 temp |= 0x00ff; 11276 break; 11277 default: 11278 break; 11279 } 11280 bnx2x_cl22_write(bp, phy, 11281 MDIO_REG_GPHY_SHADOW, 11282 MDIO_REG_GPHY_SHADOW_WR_ENA | temp); 11283 return; 11284 } 11285 11286 11287 static void bnx2x_54618se_link_reset(struct bnx2x_phy *phy, 11288 struct link_params *params) 11289 { 11290 struct bnx2x *bp = params->bp; 11291 u32 cfg_pin; 11292 u8 port; 11293 11294 /* In case of no EPIO routed to reset the GPHY, put it 11295 * in low power mode. 11296 */ 11297 bnx2x_cl22_write(bp, phy, MDIO_PMA_REG_CTRL, 0x800); 11298 /* This works with E3 only, no need to check the chip 11299 * before determining the port. 11300 */ 11301 port = params->port; 11302 cfg_pin = (REG_RD(bp, params->shmem_base + 11303 offsetof(struct shmem_region, 11304 dev_info.port_hw_config[port].e3_cmn_pin_cfg)) & 11305 PORT_HW_CFG_E3_PHY_RESET_MASK) >> 11306 PORT_HW_CFG_E3_PHY_RESET_SHIFT; 11307 11308 /* Drive pin low to put GPHY in reset. */ 11309 bnx2x_set_cfg_pin(bp, cfg_pin, 0); 11310 } 11311 11312 static u8 bnx2x_54618se_read_status(struct bnx2x_phy *phy, 11313 struct link_params *params, 11314 struct link_vars *vars) 11315 { 11316 struct bnx2x *bp = params->bp; 11317 u16 val; 11318 u8 link_up = 0; 11319 u16 legacy_status, legacy_speed; 11320 11321 /* Get speed operation status */ 11322 bnx2x_cl22_read(bp, phy, 11323 MDIO_REG_GPHY_AUX_STATUS, 11324 &legacy_status); 11325 DP(NETIF_MSG_LINK, "54618SE read_status: 0x%x\n", legacy_status); 11326 11327 /* Read status to clear the PHY interrupt. */ 11328 bnx2x_cl22_read(bp, phy, 11329 MDIO_REG_INTR_STATUS, 11330 &val); 11331 11332 link_up = ((legacy_status & (1<<2)) == (1<<2)); 11333 11334 if (link_up) { 11335 legacy_speed = (legacy_status & (7<<8)); 11336 if (legacy_speed == (7<<8)) { 11337 vars->line_speed = SPEED_1000; 11338 vars->duplex = DUPLEX_FULL; 11339 } else if (legacy_speed == (6<<8)) { 11340 vars->line_speed = SPEED_1000; 11341 vars->duplex = DUPLEX_HALF; 11342 } else if (legacy_speed == (5<<8)) { 11343 vars->line_speed = SPEED_100; 11344 vars->duplex = DUPLEX_FULL; 11345 } 11346 /* Omitting 100Base-T4 for now */ 11347 else if (legacy_speed == (3<<8)) { 11348 vars->line_speed = SPEED_100; 11349 vars->duplex = DUPLEX_HALF; 11350 } else if (legacy_speed == (2<<8)) { 11351 vars->line_speed = SPEED_10; 11352 vars->duplex = DUPLEX_FULL; 11353 } else if (legacy_speed == (1<<8)) { 11354 vars->line_speed = SPEED_10; 11355 vars->duplex = DUPLEX_HALF; 11356 } else /* Should not happen */ 11357 vars->line_speed = 0; 11358 11359 DP(NETIF_MSG_LINK, 11360 "Link is up in %dMbps, is_duplex_full= %d\n", 11361 vars->line_speed, 11362 (vars->duplex == DUPLEX_FULL)); 11363 11364 /* Check legacy speed AN resolution */ 11365 bnx2x_cl22_read(bp, phy, 11366 0x01, 11367 &val); 11368 if (val & (1<<5)) 11369 vars->link_status |= 11370 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; 11371 bnx2x_cl22_read(bp, phy, 11372 0x06, 11373 &val); 11374 if ((val & (1<<0)) == 0) 11375 vars->link_status |= 11376 LINK_STATUS_PARALLEL_DETECTION_USED; 11377 11378 DP(NETIF_MSG_LINK, "BCM54618SE: link speed is %d\n", 11379 vars->line_speed); 11380 11381 bnx2x_ext_phy_resolve_fc(phy, params, vars); 11382 11383 if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) { 11384 /* Report LP advertised speeds */ 11385 bnx2x_cl22_read(bp, phy, 0x5, &val); 11386 11387 if (val & (1<<5)) 11388 vars->link_status |= 11389 LINK_STATUS_LINK_PARTNER_10THD_CAPABLE; 11390 if (val & (1<<6)) 11391 vars->link_status |= 11392 LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE; 11393 if (val & (1<<7)) 11394 vars->link_status |= 11395 LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE; 11396 if (val & (1<<8)) 11397 vars->link_status |= 11398 LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE; 11399 if (val & (1<<9)) 11400 vars->link_status |= 11401 LINK_STATUS_LINK_PARTNER_100T4_CAPABLE; 11402 11403 bnx2x_cl22_read(bp, phy, 0xa, &val); 11404 if (val & (1<<10)) 11405 vars->link_status |= 11406 LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE; 11407 if (val & (1<<11)) 11408 vars->link_status |= 11409 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; 11410 11411 if ((phy->flags & FLAGS_EEE) && 11412 bnx2x_eee_has_cap(params)) 11413 bnx2x_eee_an_resolve(phy, params, vars); 11414 } 11415 } 11416 return link_up; 11417 } 11418 11419 static void bnx2x_54618se_config_loopback(struct bnx2x_phy *phy, 11420 struct link_params *params) 11421 { 11422 struct bnx2x *bp = params->bp; 11423 u16 val; 11424 u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0; 11425 11426 DP(NETIF_MSG_LINK, "2PMA/PMD ext_phy_loopback: 54618se\n"); 11427 11428 /* Enable master/slave manual mmode and set to master */ 11429 /* mii write 9 [bits set 11 12] */ 11430 bnx2x_cl22_write(bp, phy, 0x09, 3<<11); 11431 11432 /* forced 1G and disable autoneg */ 11433 /* set val [mii read 0] */ 11434 /* set val [expr $val & [bits clear 6 12 13]] */ 11435 /* set val [expr $val | [bits set 6 8]] */ 11436 /* mii write 0 $val */ 11437 bnx2x_cl22_read(bp, phy, 0x00, &val); 11438 val &= ~((1<<6) | (1<<12) | (1<<13)); 11439 val |= (1<<6) | (1<<8); 11440 bnx2x_cl22_write(bp, phy, 0x00, val); 11441 11442 /* Set external loopback and Tx using 6dB coding */ 11443 /* mii write 0x18 7 */ 11444 /* set val [mii read 0x18] */ 11445 /* mii write 0x18 [expr $val | [bits set 10 15]] */ 11446 bnx2x_cl22_write(bp, phy, 0x18, 7); 11447 bnx2x_cl22_read(bp, phy, 0x18, &val); 11448 bnx2x_cl22_write(bp, phy, 0x18, val | (1<<10) | (1<<15)); 11449 11450 /* This register opens the gate for the UMAC despite its name */ 11451 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1); 11452 11453 /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame 11454 * length used by the MAC receive logic to check frames. 11455 */ 11456 REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710); 11457 } 11458 11459 /******************************************************************/ 11460 /* SFX7101 PHY SECTION */ 11461 /******************************************************************/ 11462 static void bnx2x_7101_config_loopback(struct bnx2x_phy *phy, 11463 struct link_params *params) 11464 { 11465 struct bnx2x *bp = params->bp; 11466 /* SFX7101_XGXS_TEST1 */ 11467 bnx2x_cl45_write(bp, phy, 11468 MDIO_XS_DEVAD, MDIO_XS_SFX7101_XGXS_TEST1, 0x100); 11469 } 11470 11471 static int bnx2x_7101_config_init(struct bnx2x_phy *phy, 11472 struct link_params *params, 11473 struct link_vars *vars) 11474 { 11475 u16 fw_ver1, fw_ver2, val; 11476 struct bnx2x *bp = params->bp; 11477 DP(NETIF_MSG_LINK, "Setting the SFX7101 LASI indication\n"); 11478 11479 /* Restore normal power mode*/ 11480 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 11481 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); 11482 /* HW reset */ 11483 bnx2x_ext_phy_hw_reset(bp, params->port); 11484 bnx2x_wait_reset_complete(bp, phy, params); 11485 11486 bnx2x_cl45_write(bp, phy, 11487 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x1); 11488 DP(NETIF_MSG_LINK, "Setting the SFX7101 LED to blink on traffic\n"); 11489 bnx2x_cl45_write(bp, phy, 11490 MDIO_PMA_DEVAD, MDIO_PMA_REG_7107_LED_CNTL, (1<<3)); 11491 11492 bnx2x_ext_phy_set_pause(params, phy, vars); 11493 /* Restart autoneg */ 11494 bnx2x_cl45_read(bp, phy, 11495 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, &val); 11496 val |= 0x200; 11497 bnx2x_cl45_write(bp, phy, 11498 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, val); 11499 11500 /* Save spirom version */ 11501 bnx2x_cl45_read(bp, phy, 11502 MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER1, &fw_ver1); 11503 11504 bnx2x_cl45_read(bp, phy, 11505 MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER2, &fw_ver2); 11506 bnx2x_save_spirom_version(bp, params->port, 11507 (u32)(fw_ver1<<16 | fw_ver2), phy->ver_addr); 11508 return 0; 11509 } 11510 11511 static u8 bnx2x_7101_read_status(struct bnx2x_phy *phy, 11512 struct link_params *params, 11513 struct link_vars *vars) 11514 { 11515 struct bnx2x *bp = params->bp; 11516 u8 link_up; 11517 u16 val1, val2; 11518 bnx2x_cl45_read(bp, phy, 11519 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2); 11520 bnx2x_cl45_read(bp, phy, 11521 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1); 11522 DP(NETIF_MSG_LINK, "10G-base-T LASI status 0x%x->0x%x\n", 11523 val2, val1); 11524 bnx2x_cl45_read(bp, phy, 11525 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2); 11526 bnx2x_cl45_read(bp, phy, 11527 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1); 11528 DP(NETIF_MSG_LINK, "10G-base-T PMA status 0x%x->0x%x\n", 11529 val2, val1); 11530 link_up = ((val1 & 4) == 4); 11531 /* If link is up print the AN outcome of the SFX7101 PHY */ 11532 if (link_up) { 11533 bnx2x_cl45_read(bp, phy, 11534 MDIO_AN_DEVAD, MDIO_AN_REG_MASTER_STATUS, 11535 &val2); 11536 vars->line_speed = SPEED_10000; 11537 vars->duplex = DUPLEX_FULL; 11538 DP(NETIF_MSG_LINK, "SFX7101 AN status 0x%x->Master=%x\n", 11539 val2, (val2 & (1<<14))); 11540 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars); 11541 bnx2x_ext_phy_resolve_fc(phy, params, vars); 11542 11543 /* Read LP advertised speeds */ 11544 if (val2 & (1<<11)) 11545 vars->link_status |= 11546 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; 11547 } 11548 return link_up; 11549 } 11550 11551 static int bnx2x_7101_format_ver(u32 spirom_ver, u8 *str, u16 *len) 11552 { 11553 if (*len < 5) 11554 return -EINVAL; 11555 str[0] = (spirom_ver & 0xFF); 11556 str[1] = (spirom_ver & 0xFF00) >> 8; 11557 str[2] = (spirom_ver & 0xFF0000) >> 16; 11558 str[3] = (spirom_ver & 0xFF000000) >> 24; 11559 str[4] = '\0'; 11560 *len -= 5; 11561 return 0; 11562 } 11563 11564 void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, struct bnx2x_phy *phy) 11565 { 11566 u16 val, cnt; 11567 11568 bnx2x_cl45_read(bp, phy, 11569 MDIO_PMA_DEVAD, 11570 MDIO_PMA_REG_7101_RESET, &val); 11571 11572 for (cnt = 0; cnt < 10; cnt++) { 11573 msleep(50); 11574 /* Writes a self-clearing reset */ 11575 bnx2x_cl45_write(bp, phy, 11576 MDIO_PMA_DEVAD, 11577 MDIO_PMA_REG_7101_RESET, 11578 (val | (1<<15))); 11579 /* Wait for clear */ 11580 bnx2x_cl45_read(bp, phy, 11581 MDIO_PMA_DEVAD, 11582 MDIO_PMA_REG_7101_RESET, &val); 11583 11584 if ((val & (1<<15)) == 0) 11585 break; 11586 } 11587 } 11588 11589 static void bnx2x_7101_hw_reset(struct bnx2x_phy *phy, 11590 struct link_params *params) { 11591 /* Low power mode is controlled by GPIO 2 */ 11592 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_2, 11593 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port); 11594 /* The PHY reset is controlled by GPIO 1 */ 11595 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1, 11596 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port); 11597 } 11598 11599 static void bnx2x_7101_set_link_led(struct bnx2x_phy *phy, 11600 struct link_params *params, u8 mode) 11601 { 11602 u16 val = 0; 11603 struct bnx2x *bp = params->bp; 11604 switch (mode) { 11605 case LED_MODE_FRONT_PANEL_OFF: 11606 case LED_MODE_OFF: 11607 val = 2; 11608 break; 11609 case LED_MODE_ON: 11610 val = 1; 11611 break; 11612 case LED_MODE_OPER: 11613 val = 0; 11614 break; 11615 } 11616 bnx2x_cl45_write(bp, phy, 11617 MDIO_PMA_DEVAD, 11618 MDIO_PMA_REG_7107_LINK_LED_CNTL, 11619 val); 11620 } 11621 11622 /******************************************************************/ 11623 /* STATIC PHY DECLARATION */ 11624 /******************************************************************/ 11625 11626 static const struct bnx2x_phy phy_null = { 11627 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN, 11628 .addr = 0, 11629 .def_md_devad = 0, 11630 .flags = FLAGS_INIT_XGXS_FIRST, 11631 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11632 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11633 .mdio_ctrl = 0, 11634 .supported = 0, 11635 .media_type = ETH_PHY_NOT_PRESENT, 11636 .ver_addr = 0, 11637 .req_flow_ctrl = 0, 11638 .req_line_speed = 0, 11639 .speed_cap_mask = 0, 11640 .req_duplex = 0, 11641 .rsrv = 0, 11642 .config_init = (config_init_t)NULL, 11643 .read_status = (read_status_t)NULL, 11644 .link_reset = (link_reset_t)NULL, 11645 .config_loopback = (config_loopback_t)NULL, 11646 .format_fw_ver = (format_fw_ver_t)NULL, 11647 .hw_reset = (hw_reset_t)NULL, 11648 .set_link_led = (set_link_led_t)NULL, 11649 .phy_specific_func = (phy_specific_func_t)NULL 11650 }; 11651 11652 static const struct bnx2x_phy phy_serdes = { 11653 .type = PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT, 11654 .addr = 0xff, 11655 .def_md_devad = 0, 11656 .flags = 0, 11657 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11658 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11659 .mdio_ctrl = 0, 11660 .supported = (SUPPORTED_10baseT_Half | 11661 SUPPORTED_10baseT_Full | 11662 SUPPORTED_100baseT_Half | 11663 SUPPORTED_100baseT_Full | 11664 SUPPORTED_1000baseT_Full | 11665 SUPPORTED_2500baseX_Full | 11666 SUPPORTED_TP | 11667 SUPPORTED_Autoneg | 11668 SUPPORTED_Pause | 11669 SUPPORTED_Asym_Pause), 11670 .media_type = ETH_PHY_BASE_T, 11671 .ver_addr = 0, 11672 .req_flow_ctrl = 0, 11673 .req_line_speed = 0, 11674 .speed_cap_mask = 0, 11675 .req_duplex = 0, 11676 .rsrv = 0, 11677 .config_init = (config_init_t)bnx2x_xgxs_config_init, 11678 .read_status = (read_status_t)bnx2x_link_settings_status, 11679 .link_reset = (link_reset_t)bnx2x_int_link_reset, 11680 .config_loopback = (config_loopback_t)NULL, 11681 .format_fw_ver = (format_fw_ver_t)NULL, 11682 .hw_reset = (hw_reset_t)NULL, 11683 .set_link_led = (set_link_led_t)NULL, 11684 .phy_specific_func = (phy_specific_func_t)NULL 11685 }; 11686 11687 static const struct bnx2x_phy phy_xgxs = { 11688 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT, 11689 .addr = 0xff, 11690 .def_md_devad = 0, 11691 .flags = 0, 11692 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11693 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11694 .mdio_ctrl = 0, 11695 .supported = (SUPPORTED_10baseT_Half | 11696 SUPPORTED_10baseT_Full | 11697 SUPPORTED_100baseT_Half | 11698 SUPPORTED_100baseT_Full | 11699 SUPPORTED_1000baseT_Full | 11700 SUPPORTED_2500baseX_Full | 11701 SUPPORTED_10000baseT_Full | 11702 SUPPORTED_FIBRE | 11703 SUPPORTED_Autoneg | 11704 SUPPORTED_Pause | 11705 SUPPORTED_Asym_Pause), 11706 .media_type = ETH_PHY_CX4, 11707 .ver_addr = 0, 11708 .req_flow_ctrl = 0, 11709 .req_line_speed = 0, 11710 .speed_cap_mask = 0, 11711 .req_duplex = 0, 11712 .rsrv = 0, 11713 .config_init = (config_init_t)bnx2x_xgxs_config_init, 11714 .read_status = (read_status_t)bnx2x_link_settings_status, 11715 .link_reset = (link_reset_t)bnx2x_int_link_reset, 11716 .config_loopback = (config_loopback_t)bnx2x_set_xgxs_loopback, 11717 .format_fw_ver = (format_fw_ver_t)NULL, 11718 .hw_reset = (hw_reset_t)NULL, 11719 .set_link_led = (set_link_led_t)NULL, 11720 .phy_specific_func = (phy_specific_func_t)bnx2x_xgxs_specific_func 11721 }; 11722 static const struct bnx2x_phy phy_warpcore = { 11723 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT, 11724 .addr = 0xff, 11725 .def_md_devad = 0, 11726 .flags = FLAGS_TX_ERROR_CHECK, 11727 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11728 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11729 .mdio_ctrl = 0, 11730 .supported = (SUPPORTED_10baseT_Half | 11731 SUPPORTED_10baseT_Full | 11732 SUPPORTED_100baseT_Half | 11733 SUPPORTED_100baseT_Full | 11734 SUPPORTED_1000baseT_Full | 11735 SUPPORTED_1000baseKX_Full | 11736 SUPPORTED_10000baseT_Full | 11737 SUPPORTED_10000baseKR_Full | 11738 SUPPORTED_20000baseKR2_Full | 11739 SUPPORTED_20000baseMLD2_Full | 11740 SUPPORTED_FIBRE | 11741 SUPPORTED_Autoneg | 11742 SUPPORTED_Pause | 11743 SUPPORTED_Asym_Pause), 11744 .media_type = ETH_PHY_UNSPECIFIED, 11745 .ver_addr = 0, 11746 .req_flow_ctrl = 0, 11747 .req_line_speed = 0, 11748 .speed_cap_mask = 0, 11749 /* req_duplex = */0, 11750 /* rsrv = */0, 11751 .config_init = (config_init_t)bnx2x_warpcore_config_init, 11752 .read_status = (read_status_t)bnx2x_warpcore_read_status, 11753 .link_reset = (link_reset_t)bnx2x_warpcore_link_reset, 11754 .config_loopback = (config_loopback_t)bnx2x_set_warpcore_loopback, 11755 .format_fw_ver = (format_fw_ver_t)NULL, 11756 .hw_reset = (hw_reset_t)bnx2x_warpcore_hw_reset, 11757 .set_link_led = (set_link_led_t)NULL, 11758 .phy_specific_func = (phy_specific_func_t)NULL 11759 }; 11760 11761 11762 static const struct bnx2x_phy phy_7101 = { 11763 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101, 11764 .addr = 0xff, 11765 .def_md_devad = 0, 11766 .flags = FLAGS_FAN_FAILURE_DET_REQ, 11767 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11768 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11769 .mdio_ctrl = 0, 11770 .supported = (SUPPORTED_10000baseT_Full | 11771 SUPPORTED_TP | 11772 SUPPORTED_Autoneg | 11773 SUPPORTED_Pause | 11774 SUPPORTED_Asym_Pause), 11775 .media_type = ETH_PHY_BASE_T, 11776 .ver_addr = 0, 11777 .req_flow_ctrl = 0, 11778 .req_line_speed = 0, 11779 .speed_cap_mask = 0, 11780 .req_duplex = 0, 11781 .rsrv = 0, 11782 .config_init = (config_init_t)bnx2x_7101_config_init, 11783 .read_status = (read_status_t)bnx2x_7101_read_status, 11784 .link_reset = (link_reset_t)bnx2x_common_ext_link_reset, 11785 .config_loopback = (config_loopback_t)bnx2x_7101_config_loopback, 11786 .format_fw_ver = (format_fw_ver_t)bnx2x_7101_format_ver, 11787 .hw_reset = (hw_reset_t)bnx2x_7101_hw_reset, 11788 .set_link_led = (set_link_led_t)bnx2x_7101_set_link_led, 11789 .phy_specific_func = (phy_specific_func_t)NULL 11790 }; 11791 static const struct bnx2x_phy phy_8073 = { 11792 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073, 11793 .addr = 0xff, 11794 .def_md_devad = 0, 11795 .flags = 0, 11796 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11797 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11798 .mdio_ctrl = 0, 11799 .supported = (SUPPORTED_10000baseT_Full | 11800 SUPPORTED_2500baseX_Full | 11801 SUPPORTED_1000baseT_Full | 11802 SUPPORTED_FIBRE | 11803 SUPPORTED_Autoneg | 11804 SUPPORTED_Pause | 11805 SUPPORTED_Asym_Pause), 11806 .media_type = ETH_PHY_KR, 11807 .ver_addr = 0, 11808 .req_flow_ctrl = 0, 11809 .req_line_speed = 0, 11810 .speed_cap_mask = 0, 11811 .req_duplex = 0, 11812 .rsrv = 0, 11813 .config_init = (config_init_t)bnx2x_8073_config_init, 11814 .read_status = (read_status_t)bnx2x_8073_read_status, 11815 .link_reset = (link_reset_t)bnx2x_8073_link_reset, 11816 .config_loopback = (config_loopback_t)NULL, 11817 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver, 11818 .hw_reset = (hw_reset_t)NULL, 11819 .set_link_led = (set_link_led_t)NULL, 11820 .phy_specific_func = (phy_specific_func_t)bnx2x_8073_specific_func 11821 }; 11822 static const struct bnx2x_phy phy_8705 = { 11823 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705, 11824 .addr = 0xff, 11825 .def_md_devad = 0, 11826 .flags = FLAGS_INIT_XGXS_FIRST, 11827 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11828 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11829 .mdio_ctrl = 0, 11830 .supported = (SUPPORTED_10000baseT_Full | 11831 SUPPORTED_FIBRE | 11832 SUPPORTED_Pause | 11833 SUPPORTED_Asym_Pause), 11834 .media_type = ETH_PHY_XFP_FIBER, 11835 .ver_addr = 0, 11836 .req_flow_ctrl = 0, 11837 .req_line_speed = 0, 11838 .speed_cap_mask = 0, 11839 .req_duplex = 0, 11840 .rsrv = 0, 11841 .config_init = (config_init_t)bnx2x_8705_config_init, 11842 .read_status = (read_status_t)bnx2x_8705_read_status, 11843 .link_reset = (link_reset_t)bnx2x_common_ext_link_reset, 11844 .config_loopback = (config_loopback_t)NULL, 11845 .format_fw_ver = (format_fw_ver_t)bnx2x_null_format_ver, 11846 .hw_reset = (hw_reset_t)NULL, 11847 .set_link_led = (set_link_led_t)NULL, 11848 .phy_specific_func = (phy_specific_func_t)NULL 11849 }; 11850 static const struct bnx2x_phy phy_8706 = { 11851 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706, 11852 .addr = 0xff, 11853 .def_md_devad = 0, 11854 .flags = FLAGS_INIT_XGXS_FIRST, 11855 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11856 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11857 .mdio_ctrl = 0, 11858 .supported = (SUPPORTED_10000baseT_Full | 11859 SUPPORTED_1000baseT_Full | 11860 SUPPORTED_FIBRE | 11861 SUPPORTED_Pause | 11862 SUPPORTED_Asym_Pause), 11863 .media_type = ETH_PHY_SFPP_10G_FIBER, 11864 .ver_addr = 0, 11865 .req_flow_ctrl = 0, 11866 .req_line_speed = 0, 11867 .speed_cap_mask = 0, 11868 .req_duplex = 0, 11869 .rsrv = 0, 11870 .config_init = (config_init_t)bnx2x_8706_config_init, 11871 .read_status = (read_status_t)bnx2x_8706_read_status, 11872 .link_reset = (link_reset_t)bnx2x_common_ext_link_reset, 11873 .config_loopback = (config_loopback_t)NULL, 11874 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver, 11875 .hw_reset = (hw_reset_t)NULL, 11876 .set_link_led = (set_link_led_t)NULL, 11877 .phy_specific_func = (phy_specific_func_t)NULL 11878 }; 11879 11880 static const struct bnx2x_phy phy_8726 = { 11881 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726, 11882 .addr = 0xff, 11883 .def_md_devad = 0, 11884 .flags = (FLAGS_INIT_XGXS_FIRST | 11885 FLAGS_TX_ERROR_CHECK), 11886 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11887 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11888 .mdio_ctrl = 0, 11889 .supported = (SUPPORTED_10000baseT_Full | 11890 SUPPORTED_1000baseT_Full | 11891 SUPPORTED_Autoneg | 11892 SUPPORTED_FIBRE | 11893 SUPPORTED_Pause | 11894 SUPPORTED_Asym_Pause), 11895 .media_type = ETH_PHY_NOT_PRESENT, 11896 .ver_addr = 0, 11897 .req_flow_ctrl = 0, 11898 .req_line_speed = 0, 11899 .speed_cap_mask = 0, 11900 .req_duplex = 0, 11901 .rsrv = 0, 11902 .config_init = (config_init_t)bnx2x_8726_config_init, 11903 .read_status = (read_status_t)bnx2x_8726_read_status, 11904 .link_reset = (link_reset_t)bnx2x_8726_link_reset, 11905 .config_loopback = (config_loopback_t)bnx2x_8726_config_loopback, 11906 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver, 11907 .hw_reset = (hw_reset_t)NULL, 11908 .set_link_led = (set_link_led_t)NULL, 11909 .phy_specific_func = (phy_specific_func_t)NULL 11910 }; 11911 11912 static const struct bnx2x_phy phy_8727 = { 11913 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727, 11914 .addr = 0xff, 11915 .def_md_devad = 0, 11916 .flags = (FLAGS_FAN_FAILURE_DET_REQ | 11917 FLAGS_TX_ERROR_CHECK), 11918 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11919 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11920 .mdio_ctrl = 0, 11921 .supported = (SUPPORTED_10000baseT_Full | 11922 SUPPORTED_1000baseT_Full | 11923 SUPPORTED_FIBRE | 11924 SUPPORTED_Pause | 11925 SUPPORTED_Asym_Pause), 11926 .media_type = ETH_PHY_NOT_PRESENT, 11927 .ver_addr = 0, 11928 .req_flow_ctrl = 0, 11929 .req_line_speed = 0, 11930 .speed_cap_mask = 0, 11931 .req_duplex = 0, 11932 .rsrv = 0, 11933 .config_init = (config_init_t)bnx2x_8727_config_init, 11934 .read_status = (read_status_t)bnx2x_8727_read_status, 11935 .link_reset = (link_reset_t)bnx2x_8727_link_reset, 11936 .config_loopback = (config_loopback_t)NULL, 11937 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver, 11938 .hw_reset = (hw_reset_t)bnx2x_8727_hw_reset, 11939 .set_link_led = (set_link_led_t)bnx2x_8727_set_link_led, 11940 .phy_specific_func = (phy_specific_func_t)bnx2x_8727_specific_func 11941 }; 11942 static const struct bnx2x_phy phy_8481 = { 11943 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481, 11944 .addr = 0xff, 11945 .def_md_devad = 0, 11946 .flags = FLAGS_FAN_FAILURE_DET_REQ | 11947 FLAGS_REARM_LATCH_SIGNAL, 11948 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11949 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11950 .mdio_ctrl = 0, 11951 .supported = (SUPPORTED_10baseT_Half | 11952 SUPPORTED_10baseT_Full | 11953 SUPPORTED_100baseT_Half | 11954 SUPPORTED_100baseT_Full | 11955 SUPPORTED_1000baseT_Full | 11956 SUPPORTED_10000baseT_Full | 11957 SUPPORTED_TP | 11958 SUPPORTED_Autoneg | 11959 SUPPORTED_Pause | 11960 SUPPORTED_Asym_Pause), 11961 .media_type = ETH_PHY_BASE_T, 11962 .ver_addr = 0, 11963 .req_flow_ctrl = 0, 11964 .req_line_speed = 0, 11965 .speed_cap_mask = 0, 11966 .req_duplex = 0, 11967 .rsrv = 0, 11968 .config_init = (config_init_t)bnx2x_8481_config_init, 11969 .read_status = (read_status_t)bnx2x_848xx_read_status, 11970 .link_reset = (link_reset_t)bnx2x_8481_link_reset, 11971 .config_loopback = (config_loopback_t)NULL, 11972 .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver, 11973 .hw_reset = (hw_reset_t)bnx2x_8481_hw_reset, 11974 .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led, 11975 .phy_specific_func = (phy_specific_func_t)NULL 11976 }; 11977 11978 static const struct bnx2x_phy phy_84823 = { 11979 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823, 11980 .addr = 0xff, 11981 .def_md_devad = 0, 11982 .flags = (FLAGS_FAN_FAILURE_DET_REQ | 11983 FLAGS_REARM_LATCH_SIGNAL | 11984 FLAGS_TX_ERROR_CHECK), 11985 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11986 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11987 .mdio_ctrl = 0, 11988 .supported = (SUPPORTED_10baseT_Half | 11989 SUPPORTED_10baseT_Full | 11990 SUPPORTED_100baseT_Half | 11991 SUPPORTED_100baseT_Full | 11992 SUPPORTED_1000baseT_Full | 11993 SUPPORTED_10000baseT_Full | 11994 SUPPORTED_TP | 11995 SUPPORTED_Autoneg | 11996 SUPPORTED_Pause | 11997 SUPPORTED_Asym_Pause), 11998 .media_type = ETH_PHY_BASE_T, 11999 .ver_addr = 0, 12000 .req_flow_ctrl = 0, 12001 .req_line_speed = 0, 12002 .speed_cap_mask = 0, 12003 .req_duplex = 0, 12004 .rsrv = 0, 12005 .config_init = (config_init_t)bnx2x_848x3_config_init, 12006 .read_status = (read_status_t)bnx2x_848xx_read_status, 12007 .link_reset = (link_reset_t)bnx2x_848x3_link_reset, 12008 .config_loopback = (config_loopback_t)NULL, 12009 .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver, 12010 .hw_reset = (hw_reset_t)NULL, 12011 .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led, 12012 .phy_specific_func = (phy_specific_func_t)bnx2x_848xx_specific_func 12013 }; 12014 12015 static const struct bnx2x_phy phy_84833 = { 12016 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833, 12017 .addr = 0xff, 12018 .def_md_devad = 0, 12019 .flags = (FLAGS_FAN_FAILURE_DET_REQ | 12020 FLAGS_REARM_LATCH_SIGNAL | 12021 FLAGS_TX_ERROR_CHECK), 12022 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 12023 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 12024 .mdio_ctrl = 0, 12025 .supported = (SUPPORTED_100baseT_Half | 12026 SUPPORTED_100baseT_Full | 12027 SUPPORTED_1000baseT_Full | 12028 SUPPORTED_10000baseT_Full | 12029 SUPPORTED_TP | 12030 SUPPORTED_Autoneg | 12031 SUPPORTED_Pause | 12032 SUPPORTED_Asym_Pause), 12033 .media_type = ETH_PHY_BASE_T, 12034 .ver_addr = 0, 12035 .req_flow_ctrl = 0, 12036 .req_line_speed = 0, 12037 .speed_cap_mask = 0, 12038 .req_duplex = 0, 12039 .rsrv = 0, 12040 .config_init = (config_init_t)bnx2x_848x3_config_init, 12041 .read_status = (read_status_t)bnx2x_848xx_read_status, 12042 .link_reset = (link_reset_t)bnx2x_848x3_link_reset, 12043 .config_loopback = (config_loopback_t)NULL, 12044 .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver, 12045 .hw_reset = (hw_reset_t)bnx2x_84833_hw_reset_phy, 12046 .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led, 12047 .phy_specific_func = (phy_specific_func_t)bnx2x_848xx_specific_func 12048 }; 12049 12050 static const struct bnx2x_phy phy_84834 = { 12051 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834, 12052 .addr = 0xff, 12053 .def_md_devad = 0, 12054 .flags = FLAGS_FAN_FAILURE_DET_REQ | 12055 FLAGS_REARM_LATCH_SIGNAL, 12056 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 12057 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 12058 .mdio_ctrl = 0, 12059 .supported = (SUPPORTED_100baseT_Half | 12060 SUPPORTED_100baseT_Full | 12061 SUPPORTED_1000baseT_Full | 12062 SUPPORTED_10000baseT_Full | 12063 SUPPORTED_TP | 12064 SUPPORTED_Autoneg | 12065 SUPPORTED_Pause | 12066 SUPPORTED_Asym_Pause), 12067 .media_type = ETH_PHY_BASE_T, 12068 .ver_addr = 0, 12069 .req_flow_ctrl = 0, 12070 .req_line_speed = 0, 12071 .speed_cap_mask = 0, 12072 .req_duplex = 0, 12073 .rsrv = 0, 12074 .config_init = (config_init_t)bnx2x_848x3_config_init, 12075 .read_status = (read_status_t)bnx2x_848xx_read_status, 12076 .link_reset = (link_reset_t)bnx2x_848x3_link_reset, 12077 .config_loopback = (config_loopback_t)NULL, 12078 .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver, 12079 .hw_reset = (hw_reset_t)bnx2x_84833_hw_reset_phy, 12080 .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led, 12081 .phy_specific_func = (phy_specific_func_t)bnx2x_848xx_specific_func 12082 }; 12083 12084 static const struct bnx2x_phy phy_84858 = { 12085 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858, 12086 .addr = 0xff, 12087 .def_md_devad = 0, 12088 .flags = FLAGS_FAN_FAILURE_DET_REQ | 12089 FLAGS_REARM_LATCH_SIGNAL, 12090 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 12091 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 12092 .mdio_ctrl = 0, 12093 .supported = (SUPPORTED_100baseT_Half | 12094 SUPPORTED_100baseT_Full | 12095 SUPPORTED_1000baseT_Full | 12096 SUPPORTED_10000baseT_Full | 12097 SUPPORTED_TP | 12098 SUPPORTED_Autoneg | 12099 SUPPORTED_Pause | 12100 SUPPORTED_Asym_Pause), 12101 .media_type = ETH_PHY_BASE_T, 12102 .ver_addr = 0, 12103 .req_flow_ctrl = 0, 12104 .req_line_speed = 0, 12105 .speed_cap_mask = 0, 12106 .req_duplex = 0, 12107 .rsrv = 0, 12108 .config_init = (config_init_t)bnx2x_848x3_config_init, 12109 .read_status = (read_status_t)bnx2x_848xx_read_status, 12110 .link_reset = (link_reset_t)bnx2x_848x3_link_reset, 12111 .config_loopback = (config_loopback_t)NULL, 12112 .format_fw_ver = (format_fw_ver_t)bnx2x_8485x_format_ver, 12113 .hw_reset = (hw_reset_t)bnx2x_84833_hw_reset_phy, 12114 .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led, 12115 .phy_specific_func = (phy_specific_func_t)bnx2x_848xx_specific_func 12116 }; 12117 12118 static const struct bnx2x_phy phy_54618se = { 12119 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE, 12120 .addr = 0xff, 12121 .def_md_devad = 0, 12122 .flags = FLAGS_INIT_XGXS_FIRST, 12123 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 12124 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 12125 .mdio_ctrl = 0, 12126 .supported = (SUPPORTED_10baseT_Half | 12127 SUPPORTED_10baseT_Full | 12128 SUPPORTED_100baseT_Half | 12129 SUPPORTED_100baseT_Full | 12130 SUPPORTED_1000baseT_Full | 12131 SUPPORTED_TP | 12132 SUPPORTED_Autoneg | 12133 SUPPORTED_Pause | 12134 SUPPORTED_Asym_Pause), 12135 .media_type = ETH_PHY_BASE_T, 12136 .ver_addr = 0, 12137 .req_flow_ctrl = 0, 12138 .req_line_speed = 0, 12139 .speed_cap_mask = 0, 12140 /* req_duplex = */0, 12141 /* rsrv = */0, 12142 .config_init = (config_init_t)bnx2x_54618se_config_init, 12143 .read_status = (read_status_t)bnx2x_54618se_read_status, 12144 .link_reset = (link_reset_t)bnx2x_54618se_link_reset, 12145 .config_loopback = (config_loopback_t)bnx2x_54618se_config_loopback, 12146 .format_fw_ver = (format_fw_ver_t)NULL, 12147 .hw_reset = (hw_reset_t)NULL, 12148 .set_link_led = (set_link_led_t)bnx2x_5461x_set_link_led, 12149 .phy_specific_func = (phy_specific_func_t)bnx2x_54618se_specific_func 12150 }; 12151 /*****************************************************************/ 12152 /* */ 12153 /* Populate the phy according. Main function: bnx2x_populate_phy */ 12154 /* */ 12155 /*****************************************************************/ 12156 12157 static void bnx2x_populate_preemphasis(struct bnx2x *bp, u32 shmem_base, 12158 struct bnx2x_phy *phy, u8 port, 12159 u8 phy_index) 12160 { 12161 /* Get the 4 lanes xgxs config rx and tx */ 12162 u32 rx = 0, tx = 0, i; 12163 for (i = 0; i < 2; i++) { 12164 /* INT_PHY and EXT_PHY1 share the same value location in 12165 * the shmem. When num_phys is greater than 1, than this value 12166 * applies only to EXT_PHY1 12167 */ 12168 if (phy_index == INT_PHY || phy_index == EXT_PHY1) { 12169 rx = REG_RD(bp, shmem_base + 12170 offsetof(struct shmem_region, 12171 dev_info.port_hw_config[port].xgxs_config_rx[i<<1])); 12172 12173 tx = REG_RD(bp, shmem_base + 12174 offsetof(struct shmem_region, 12175 dev_info.port_hw_config[port].xgxs_config_tx[i<<1])); 12176 } else { 12177 rx = REG_RD(bp, shmem_base + 12178 offsetof(struct shmem_region, 12179 dev_info.port_hw_config[port].xgxs_config2_rx[i<<1])); 12180 12181 tx = REG_RD(bp, shmem_base + 12182 offsetof(struct shmem_region, 12183 dev_info.port_hw_config[port].xgxs_config2_rx[i<<1])); 12184 } 12185 12186 phy->rx_preemphasis[i << 1] = ((rx>>16) & 0xffff); 12187 phy->rx_preemphasis[(i << 1) + 1] = (rx & 0xffff); 12188 12189 phy->tx_preemphasis[i << 1] = ((tx>>16) & 0xffff); 12190 phy->tx_preemphasis[(i << 1) + 1] = (tx & 0xffff); 12191 } 12192 } 12193 12194 static u32 bnx2x_get_ext_phy_config(struct bnx2x *bp, u32 shmem_base, 12195 u8 phy_index, u8 port) 12196 { 12197 u32 ext_phy_config = 0; 12198 switch (phy_index) { 12199 case EXT_PHY1: 12200 ext_phy_config = REG_RD(bp, shmem_base + 12201 offsetof(struct shmem_region, 12202 dev_info.port_hw_config[port].external_phy_config)); 12203 break; 12204 case EXT_PHY2: 12205 ext_phy_config = REG_RD(bp, shmem_base + 12206 offsetof(struct shmem_region, 12207 dev_info.port_hw_config[port].external_phy_config2)); 12208 break; 12209 default: 12210 DP(NETIF_MSG_LINK, "Invalid phy_index %d\n", phy_index); 12211 return -EINVAL; 12212 } 12213 12214 return ext_phy_config; 12215 } 12216 static int bnx2x_populate_int_phy(struct bnx2x *bp, u32 shmem_base, u8 port, 12217 struct bnx2x_phy *phy) 12218 { 12219 u32 phy_addr; 12220 u32 chip_id; 12221 u32 switch_cfg = (REG_RD(bp, shmem_base + 12222 offsetof(struct shmem_region, 12223 dev_info.port_feature_config[port].link_config)) & 12224 PORT_FEATURE_CONNECTED_SWITCH_MASK); 12225 chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) | 12226 ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12); 12227 12228 DP(NETIF_MSG_LINK, ":chip_id = 0x%x\n", chip_id); 12229 if (USES_WARPCORE(bp)) { 12230 u32 serdes_net_if; 12231 phy_addr = REG_RD(bp, 12232 MISC_REG_WC0_CTRL_PHY_ADDR); 12233 *phy = phy_warpcore; 12234 if (REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR) == 0x3) 12235 phy->flags |= FLAGS_4_PORT_MODE; 12236 else 12237 phy->flags &= ~FLAGS_4_PORT_MODE; 12238 /* Check Dual mode */ 12239 serdes_net_if = (REG_RD(bp, shmem_base + 12240 offsetof(struct shmem_region, dev_info. 12241 port_hw_config[port].default_cfg)) & 12242 PORT_HW_CFG_NET_SERDES_IF_MASK); 12243 /* Set the appropriate supported and flags indications per 12244 * interface type of the chip 12245 */ 12246 switch (serdes_net_if) { 12247 case PORT_HW_CFG_NET_SERDES_IF_SGMII: 12248 phy->supported &= (SUPPORTED_10baseT_Half | 12249 SUPPORTED_10baseT_Full | 12250 SUPPORTED_100baseT_Half | 12251 SUPPORTED_100baseT_Full | 12252 SUPPORTED_1000baseT_Full | 12253 SUPPORTED_FIBRE | 12254 SUPPORTED_Autoneg | 12255 SUPPORTED_Pause | 12256 SUPPORTED_Asym_Pause); 12257 phy->media_type = ETH_PHY_BASE_T; 12258 break; 12259 case PORT_HW_CFG_NET_SERDES_IF_XFI: 12260 phy->supported &= (SUPPORTED_1000baseT_Full | 12261 SUPPORTED_10000baseT_Full | 12262 SUPPORTED_FIBRE | 12263 SUPPORTED_Pause | 12264 SUPPORTED_Asym_Pause); 12265 phy->media_type = ETH_PHY_XFP_FIBER; 12266 break; 12267 case PORT_HW_CFG_NET_SERDES_IF_SFI: 12268 phy->supported &= (SUPPORTED_1000baseT_Full | 12269 SUPPORTED_10000baseT_Full | 12270 SUPPORTED_FIBRE | 12271 SUPPORTED_Pause | 12272 SUPPORTED_Asym_Pause); 12273 phy->media_type = ETH_PHY_SFPP_10G_FIBER; 12274 break; 12275 case PORT_HW_CFG_NET_SERDES_IF_KR: 12276 phy->media_type = ETH_PHY_KR; 12277 phy->supported &= (SUPPORTED_1000baseKX_Full | 12278 SUPPORTED_10000baseKR_Full | 12279 SUPPORTED_FIBRE | 12280 SUPPORTED_Autoneg | 12281 SUPPORTED_Pause | 12282 SUPPORTED_Asym_Pause); 12283 break; 12284 case PORT_HW_CFG_NET_SERDES_IF_DXGXS: 12285 phy->media_type = ETH_PHY_KR; 12286 phy->flags |= FLAGS_WC_DUAL_MODE; 12287 phy->supported &= (SUPPORTED_20000baseMLD2_Full | 12288 SUPPORTED_FIBRE | 12289 SUPPORTED_Pause | 12290 SUPPORTED_Asym_Pause); 12291 break; 12292 case PORT_HW_CFG_NET_SERDES_IF_KR2: 12293 phy->media_type = ETH_PHY_KR; 12294 phy->flags |= FLAGS_WC_DUAL_MODE; 12295 phy->supported &= (SUPPORTED_20000baseKR2_Full | 12296 SUPPORTED_10000baseKR_Full | 12297 SUPPORTED_1000baseKX_Full | 12298 SUPPORTED_Autoneg | 12299 SUPPORTED_FIBRE | 12300 SUPPORTED_Pause | 12301 SUPPORTED_Asym_Pause); 12302 phy->flags &= ~FLAGS_TX_ERROR_CHECK; 12303 break; 12304 default: 12305 DP(NETIF_MSG_LINK, "Unknown WC interface type 0x%x\n", 12306 serdes_net_if); 12307 break; 12308 } 12309 12310 /* Enable MDC/MDIO work-around for E3 A0 since free running MDC 12311 * was not set as expected. For B0, ECO will be enabled so there 12312 * won't be an issue there 12313 */ 12314 if (CHIP_REV(bp) == CHIP_REV_Ax) 12315 phy->flags |= FLAGS_MDC_MDIO_WA; 12316 else 12317 phy->flags |= FLAGS_MDC_MDIO_WA_B0; 12318 } else { 12319 switch (switch_cfg) { 12320 case SWITCH_CFG_1G: 12321 phy_addr = REG_RD(bp, 12322 NIG_REG_SERDES0_CTRL_PHY_ADDR + 12323 port * 0x10); 12324 *phy = phy_serdes; 12325 break; 12326 case SWITCH_CFG_10G: 12327 phy_addr = REG_RD(bp, 12328 NIG_REG_XGXS0_CTRL_PHY_ADDR + 12329 port * 0x18); 12330 *phy = phy_xgxs; 12331 break; 12332 default: 12333 DP(NETIF_MSG_LINK, "Invalid switch_cfg\n"); 12334 return -EINVAL; 12335 } 12336 } 12337 phy->addr = (u8)phy_addr; 12338 phy->mdio_ctrl = bnx2x_get_emac_base(bp, 12339 SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH, 12340 port); 12341 if (CHIP_IS_E2(bp)) 12342 phy->def_md_devad = E2_DEFAULT_PHY_DEV_ADDR; 12343 else 12344 phy->def_md_devad = DEFAULT_PHY_DEV_ADDR; 12345 12346 DP(NETIF_MSG_LINK, "Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x\n", 12347 port, phy->addr, phy->mdio_ctrl); 12348 12349 bnx2x_populate_preemphasis(bp, shmem_base, phy, port, INT_PHY); 12350 return 0; 12351 } 12352 12353 static int bnx2x_populate_ext_phy(struct bnx2x *bp, 12354 u8 phy_index, 12355 u32 shmem_base, 12356 u32 shmem2_base, 12357 u8 port, 12358 struct bnx2x_phy *phy) 12359 { 12360 u32 ext_phy_config, phy_type, config2; 12361 u32 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH; 12362 ext_phy_config = bnx2x_get_ext_phy_config(bp, shmem_base, 12363 phy_index, port); 12364 phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config); 12365 /* Select the phy type */ 12366 switch (phy_type) { 12367 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073: 12368 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED; 12369 *phy = phy_8073; 12370 break; 12371 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705: 12372 *phy = phy_8705; 12373 break; 12374 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706: 12375 *phy = phy_8706; 12376 break; 12377 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: 12378 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1; 12379 *phy = phy_8726; 12380 break; 12381 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC: 12382 /* BCM8727_NOC => BCM8727 no over current */ 12383 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1; 12384 *phy = phy_8727; 12385 phy->flags |= FLAGS_NOC; 12386 break; 12387 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722: 12388 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: 12389 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1; 12390 *phy = phy_8727; 12391 break; 12392 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481: 12393 *phy = phy_8481; 12394 break; 12395 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823: 12396 *phy = phy_84823; 12397 break; 12398 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833: 12399 *phy = phy_84833; 12400 break; 12401 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834: 12402 *phy = phy_84834; 12403 break; 12404 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858: 12405 *phy = phy_84858; 12406 break; 12407 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616: 12408 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE: 12409 *phy = phy_54618se; 12410 if (phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) 12411 phy->flags |= FLAGS_EEE; 12412 break; 12413 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101: 12414 *phy = phy_7101; 12415 break; 12416 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE: 12417 *phy = phy_null; 12418 return -EINVAL; 12419 default: 12420 *phy = phy_null; 12421 /* In case external PHY wasn't found */ 12422 if ((phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) && 12423 (phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)) 12424 return -EINVAL; 12425 return 0; 12426 } 12427 12428 phy->addr = XGXS_EXT_PHY_ADDR(ext_phy_config); 12429 bnx2x_populate_preemphasis(bp, shmem_base, phy, port, phy_index); 12430 12431 /* The shmem address of the phy version is located on different 12432 * structures. In case this structure is too old, do not set 12433 * the address 12434 */ 12435 config2 = REG_RD(bp, shmem_base + offsetof(struct shmem_region, 12436 dev_info.shared_hw_config.config2)); 12437 if (phy_index == EXT_PHY1) { 12438 phy->ver_addr = shmem_base + offsetof(struct shmem_region, 12439 port_mb[port].ext_phy_fw_version); 12440 12441 /* Check specific mdc mdio settings */ 12442 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK) 12443 mdc_mdio_access = config2 & 12444 SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK; 12445 } else { 12446 u32 size = REG_RD(bp, shmem2_base); 12447 12448 if (size > 12449 offsetof(struct shmem2_region, ext_phy_fw_version2)) { 12450 phy->ver_addr = shmem2_base + 12451 offsetof(struct shmem2_region, 12452 ext_phy_fw_version2[port]); 12453 } 12454 /* Check specific mdc mdio settings */ 12455 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) 12456 mdc_mdio_access = (config2 & 12457 SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) >> 12458 (SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT - 12459 SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT); 12460 } 12461 phy->mdio_ctrl = bnx2x_get_emac_base(bp, mdc_mdio_access, port); 12462 12463 if (bnx2x_is_8483x_8485x(phy) && (phy->ver_addr)) { 12464 /* Remove 100Mb link supported for BCM84833/4 when phy fw 12465 * version lower than or equal to 1.39 12466 */ 12467 u32 raw_ver = REG_RD(bp, phy->ver_addr); 12468 if (((raw_ver & 0x7F) <= 39) && 12469 (((raw_ver & 0xF80) >> 7) <= 1)) 12470 phy->supported &= ~(SUPPORTED_100baseT_Half | 12471 SUPPORTED_100baseT_Full); 12472 } 12473 12474 DP(NETIF_MSG_LINK, "phy_type 0x%x port %d found in index %d\n", 12475 phy_type, port, phy_index); 12476 DP(NETIF_MSG_LINK, " addr=0x%x, mdio_ctl=0x%x\n", 12477 phy->addr, phy->mdio_ctrl); 12478 return 0; 12479 } 12480 12481 static int bnx2x_populate_phy(struct bnx2x *bp, u8 phy_index, u32 shmem_base, 12482 u32 shmem2_base, u8 port, struct bnx2x_phy *phy) 12483 { 12484 phy->type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN; 12485 if (phy_index == INT_PHY) 12486 return bnx2x_populate_int_phy(bp, shmem_base, port, phy); 12487 12488 return bnx2x_populate_ext_phy(bp, phy_index, shmem_base, shmem2_base, 12489 port, phy); 12490 } 12491 12492 static void bnx2x_phy_def_cfg(struct link_params *params, 12493 struct bnx2x_phy *phy, 12494 u8 phy_index) 12495 { 12496 struct bnx2x *bp = params->bp; 12497 u32 link_config; 12498 /* Populate the default phy configuration for MF mode */ 12499 if (phy_index == EXT_PHY2) { 12500 link_config = REG_RD(bp, params->shmem_base + 12501 offsetof(struct shmem_region, dev_info. 12502 port_feature_config[params->port].link_config2)); 12503 phy->speed_cap_mask = REG_RD(bp, params->shmem_base + 12504 offsetof(struct shmem_region, 12505 dev_info. 12506 port_hw_config[params->port].speed_capability_mask2)); 12507 } else { 12508 link_config = REG_RD(bp, params->shmem_base + 12509 offsetof(struct shmem_region, dev_info. 12510 port_feature_config[params->port].link_config)); 12511 phy->speed_cap_mask = REG_RD(bp, params->shmem_base + 12512 offsetof(struct shmem_region, 12513 dev_info. 12514 port_hw_config[params->port].speed_capability_mask)); 12515 } 12516 DP(NETIF_MSG_LINK, 12517 "Default config phy idx %x cfg 0x%x speed_cap_mask 0x%x\n", 12518 phy_index, link_config, phy->speed_cap_mask); 12519 12520 phy->req_duplex = DUPLEX_FULL; 12521 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) { 12522 case PORT_FEATURE_LINK_SPEED_10M_HALF: 12523 phy->req_duplex = DUPLEX_HALF; 12524 case PORT_FEATURE_LINK_SPEED_10M_FULL: 12525 phy->req_line_speed = SPEED_10; 12526 break; 12527 case PORT_FEATURE_LINK_SPEED_100M_HALF: 12528 phy->req_duplex = DUPLEX_HALF; 12529 case PORT_FEATURE_LINK_SPEED_100M_FULL: 12530 phy->req_line_speed = SPEED_100; 12531 break; 12532 case PORT_FEATURE_LINK_SPEED_1G: 12533 phy->req_line_speed = SPEED_1000; 12534 break; 12535 case PORT_FEATURE_LINK_SPEED_2_5G: 12536 phy->req_line_speed = SPEED_2500; 12537 break; 12538 case PORT_FEATURE_LINK_SPEED_10G_CX4: 12539 phy->req_line_speed = SPEED_10000; 12540 break; 12541 default: 12542 phy->req_line_speed = SPEED_AUTO_NEG; 12543 break; 12544 } 12545 12546 switch (link_config & PORT_FEATURE_FLOW_CONTROL_MASK) { 12547 case PORT_FEATURE_FLOW_CONTROL_AUTO: 12548 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_AUTO; 12549 break; 12550 case PORT_FEATURE_FLOW_CONTROL_TX: 12551 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_TX; 12552 break; 12553 case PORT_FEATURE_FLOW_CONTROL_RX: 12554 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_RX; 12555 break; 12556 case PORT_FEATURE_FLOW_CONTROL_BOTH: 12557 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_BOTH; 12558 break; 12559 default: 12560 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_NONE; 12561 break; 12562 } 12563 } 12564 12565 u32 bnx2x_phy_selection(struct link_params *params) 12566 { 12567 u32 phy_config_swapped, prio_cfg; 12568 u32 return_cfg = PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT; 12569 12570 phy_config_swapped = params->multi_phy_config & 12571 PORT_HW_CFG_PHY_SWAPPED_ENABLED; 12572 12573 prio_cfg = params->multi_phy_config & 12574 PORT_HW_CFG_PHY_SELECTION_MASK; 12575 12576 if (phy_config_swapped) { 12577 switch (prio_cfg) { 12578 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY: 12579 return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY; 12580 break; 12581 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY: 12582 return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY; 12583 break; 12584 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY: 12585 return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY; 12586 break; 12587 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY: 12588 return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY; 12589 break; 12590 } 12591 } else 12592 return_cfg = prio_cfg; 12593 12594 return return_cfg; 12595 } 12596 12597 int bnx2x_phy_probe(struct link_params *params) 12598 { 12599 u8 phy_index, actual_phy_idx; 12600 u32 phy_config_swapped, sync_offset, media_types; 12601 struct bnx2x *bp = params->bp; 12602 struct bnx2x_phy *phy; 12603 params->num_phys = 0; 12604 DP(NETIF_MSG_LINK, "Begin phy probe\n"); 12605 phy_config_swapped = params->multi_phy_config & 12606 PORT_HW_CFG_PHY_SWAPPED_ENABLED; 12607 12608 for (phy_index = INT_PHY; phy_index < MAX_PHYS; 12609 phy_index++) { 12610 actual_phy_idx = phy_index; 12611 if (phy_config_swapped) { 12612 if (phy_index == EXT_PHY1) 12613 actual_phy_idx = EXT_PHY2; 12614 else if (phy_index == EXT_PHY2) 12615 actual_phy_idx = EXT_PHY1; 12616 } 12617 DP(NETIF_MSG_LINK, "phy_config_swapped %x, phy_index %x," 12618 " actual_phy_idx %x\n", phy_config_swapped, 12619 phy_index, actual_phy_idx); 12620 phy = ¶ms->phy[actual_phy_idx]; 12621 if (bnx2x_populate_phy(bp, phy_index, params->shmem_base, 12622 params->shmem2_base, params->port, 12623 phy) != 0) { 12624 params->num_phys = 0; 12625 DP(NETIF_MSG_LINK, "phy probe failed in phy index %d\n", 12626 phy_index); 12627 for (phy_index = INT_PHY; 12628 phy_index < MAX_PHYS; 12629 phy_index++) 12630 *phy = phy_null; 12631 return -EINVAL; 12632 } 12633 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN) 12634 break; 12635 12636 if (params->feature_config_flags & 12637 FEATURE_CONFIG_DISABLE_REMOTE_FAULT_DET) 12638 phy->flags &= ~FLAGS_TX_ERROR_CHECK; 12639 12640 if (!(params->feature_config_flags & 12641 FEATURE_CONFIG_MT_SUPPORT)) 12642 phy->flags |= FLAGS_MDC_MDIO_WA_G; 12643 12644 sync_offset = params->shmem_base + 12645 offsetof(struct shmem_region, 12646 dev_info.port_hw_config[params->port].media_type); 12647 media_types = REG_RD(bp, sync_offset); 12648 12649 /* Update media type for non-PMF sync only for the first time 12650 * In case the media type changes afterwards, it will be updated 12651 * using the update_status function 12652 */ 12653 if ((media_types & (PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK << 12654 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * 12655 actual_phy_idx))) == 0) { 12656 media_types |= ((phy->media_type & 12657 PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) << 12658 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * 12659 actual_phy_idx)); 12660 } 12661 REG_WR(bp, sync_offset, media_types); 12662 12663 bnx2x_phy_def_cfg(params, phy, phy_index); 12664 params->num_phys++; 12665 } 12666 12667 DP(NETIF_MSG_LINK, "End phy probe. #phys found %x\n", params->num_phys); 12668 return 0; 12669 } 12670 12671 static void bnx2x_init_bmac_loopback(struct link_params *params, 12672 struct link_vars *vars) 12673 { 12674 struct bnx2x *bp = params->bp; 12675 vars->link_up = 1; 12676 vars->line_speed = SPEED_10000; 12677 vars->duplex = DUPLEX_FULL; 12678 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; 12679 vars->mac_type = MAC_TYPE_BMAC; 12680 12681 vars->phy_flags = PHY_XGXS_FLAG; 12682 12683 bnx2x_xgxs_deassert(params); 12684 12685 /* Set bmac loopback */ 12686 bnx2x_bmac_enable(params, vars, 1, 1); 12687 12688 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); 12689 } 12690 12691 static void bnx2x_init_emac_loopback(struct link_params *params, 12692 struct link_vars *vars) 12693 { 12694 struct bnx2x *bp = params->bp; 12695 vars->link_up = 1; 12696 vars->line_speed = SPEED_1000; 12697 vars->duplex = DUPLEX_FULL; 12698 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; 12699 vars->mac_type = MAC_TYPE_EMAC; 12700 12701 vars->phy_flags = PHY_XGXS_FLAG; 12702 12703 bnx2x_xgxs_deassert(params); 12704 /* Set bmac loopback */ 12705 bnx2x_emac_enable(params, vars, 1); 12706 bnx2x_emac_program(params, vars); 12707 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); 12708 } 12709 12710 static void bnx2x_init_xmac_loopback(struct link_params *params, 12711 struct link_vars *vars) 12712 { 12713 struct bnx2x *bp = params->bp; 12714 vars->link_up = 1; 12715 if (!params->req_line_speed[0]) 12716 vars->line_speed = SPEED_10000; 12717 else 12718 vars->line_speed = params->req_line_speed[0]; 12719 vars->duplex = DUPLEX_FULL; 12720 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; 12721 vars->mac_type = MAC_TYPE_XMAC; 12722 vars->phy_flags = PHY_XGXS_FLAG; 12723 /* Set WC to loopback mode since link is required to provide clock 12724 * to the XMAC in 20G mode 12725 */ 12726 bnx2x_set_aer_mmd(params, ¶ms->phy[0]); 12727 bnx2x_warpcore_reset_lane(bp, ¶ms->phy[0], 0); 12728 params->phy[INT_PHY].config_loopback( 12729 ¶ms->phy[INT_PHY], 12730 params); 12731 12732 bnx2x_xmac_enable(params, vars, 1); 12733 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); 12734 } 12735 12736 static void bnx2x_init_umac_loopback(struct link_params *params, 12737 struct link_vars *vars) 12738 { 12739 struct bnx2x *bp = params->bp; 12740 vars->link_up = 1; 12741 vars->line_speed = SPEED_1000; 12742 vars->duplex = DUPLEX_FULL; 12743 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; 12744 vars->mac_type = MAC_TYPE_UMAC; 12745 vars->phy_flags = PHY_XGXS_FLAG; 12746 bnx2x_umac_enable(params, vars, 1); 12747 12748 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); 12749 } 12750 12751 static void bnx2x_init_xgxs_loopback(struct link_params *params, 12752 struct link_vars *vars) 12753 { 12754 struct bnx2x *bp = params->bp; 12755 struct bnx2x_phy *int_phy = ¶ms->phy[INT_PHY]; 12756 vars->link_up = 1; 12757 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; 12758 vars->duplex = DUPLEX_FULL; 12759 if (params->req_line_speed[0] == SPEED_1000) 12760 vars->line_speed = SPEED_1000; 12761 else if ((params->req_line_speed[0] == SPEED_20000) || 12762 (int_phy->flags & FLAGS_WC_DUAL_MODE)) 12763 vars->line_speed = SPEED_20000; 12764 else 12765 vars->line_speed = SPEED_10000; 12766 12767 if (!USES_WARPCORE(bp)) 12768 bnx2x_xgxs_deassert(params); 12769 bnx2x_link_initialize(params, vars); 12770 12771 if (params->req_line_speed[0] == SPEED_1000) { 12772 if (USES_WARPCORE(bp)) 12773 bnx2x_umac_enable(params, vars, 0); 12774 else { 12775 bnx2x_emac_program(params, vars); 12776 bnx2x_emac_enable(params, vars, 0); 12777 } 12778 } else { 12779 if (USES_WARPCORE(bp)) 12780 bnx2x_xmac_enable(params, vars, 0); 12781 else 12782 bnx2x_bmac_enable(params, vars, 0, 1); 12783 } 12784 12785 if (params->loopback_mode == LOOPBACK_XGXS) { 12786 /* Set 10G XGXS loopback */ 12787 int_phy->config_loopback(int_phy, params); 12788 } else { 12789 /* Set external phy loopback */ 12790 u8 phy_index; 12791 for (phy_index = EXT_PHY1; 12792 phy_index < params->num_phys; phy_index++) 12793 if (params->phy[phy_index].config_loopback) 12794 params->phy[phy_index].config_loopback( 12795 ¶ms->phy[phy_index], 12796 params); 12797 } 12798 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); 12799 12800 bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed); 12801 } 12802 12803 void bnx2x_set_rx_filter(struct link_params *params, u8 en) 12804 { 12805 struct bnx2x *bp = params->bp; 12806 u8 val = en * 0x1F; 12807 12808 /* Open / close the gate between the NIG and the BRB */ 12809 if (!CHIP_IS_E1x(bp)) 12810 val |= en * 0x20; 12811 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + params->port*4, val); 12812 12813 if (!CHIP_IS_E1(bp)) { 12814 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + params->port*4, 12815 en*0x3); 12816 } 12817 12818 REG_WR(bp, (params->port ? NIG_REG_LLH1_BRB1_NOT_MCP : 12819 NIG_REG_LLH0_BRB1_NOT_MCP), en); 12820 } 12821 static int bnx2x_avoid_link_flap(struct link_params *params, 12822 struct link_vars *vars) 12823 { 12824 u32 phy_idx; 12825 u32 dont_clear_stat, lfa_sts; 12826 struct bnx2x *bp = params->bp; 12827 12828 bnx2x_set_mdio_emac_per_phy(bp, params); 12829 /* Sync the link parameters */ 12830 bnx2x_link_status_update(params, vars); 12831 12832 /* 12833 * The module verification was already done by previous link owner, 12834 * so this call is meant only to get warning message 12835 */ 12836 12837 for (phy_idx = INT_PHY; phy_idx < params->num_phys; phy_idx++) { 12838 struct bnx2x_phy *phy = ¶ms->phy[phy_idx]; 12839 if (phy->phy_specific_func) { 12840 DP(NETIF_MSG_LINK, "Calling PHY specific func\n"); 12841 phy->phy_specific_func(phy, params, PHY_INIT); 12842 } 12843 if ((phy->media_type == ETH_PHY_SFPP_10G_FIBER) || 12844 (phy->media_type == ETH_PHY_SFP_1G_FIBER) || 12845 (phy->media_type == ETH_PHY_DA_TWINAX)) 12846 bnx2x_verify_sfp_module(phy, params); 12847 } 12848 lfa_sts = REG_RD(bp, params->lfa_base + 12849 offsetof(struct shmem_lfa, 12850 lfa_sts)); 12851 12852 dont_clear_stat = lfa_sts & SHMEM_LFA_DONT_CLEAR_STAT; 12853 12854 /* Re-enable the NIG/MAC */ 12855 if (CHIP_IS_E3(bp)) { 12856 if (!dont_clear_stat) { 12857 REG_WR(bp, GRCBASE_MISC + 12858 MISC_REGISTERS_RESET_REG_2_CLEAR, 12859 (MISC_REGISTERS_RESET_REG_2_MSTAT0 << 12860 params->port)); 12861 REG_WR(bp, GRCBASE_MISC + 12862 MISC_REGISTERS_RESET_REG_2_SET, 12863 (MISC_REGISTERS_RESET_REG_2_MSTAT0 << 12864 params->port)); 12865 } 12866 if (vars->line_speed < SPEED_10000) 12867 bnx2x_umac_enable(params, vars, 0); 12868 else 12869 bnx2x_xmac_enable(params, vars, 0); 12870 } else { 12871 if (vars->line_speed < SPEED_10000) 12872 bnx2x_emac_enable(params, vars, 0); 12873 else 12874 bnx2x_bmac_enable(params, vars, 0, !dont_clear_stat); 12875 } 12876 12877 /* Increment LFA count */ 12878 lfa_sts = ((lfa_sts & ~LINK_FLAP_AVOIDANCE_COUNT_MASK) | 12879 (((((lfa_sts & LINK_FLAP_AVOIDANCE_COUNT_MASK) >> 12880 LINK_FLAP_AVOIDANCE_COUNT_OFFSET) + 1) & 0xff) 12881 << LINK_FLAP_AVOIDANCE_COUNT_OFFSET)); 12882 /* Clear link flap reason */ 12883 lfa_sts &= ~LFA_LINK_FLAP_REASON_MASK; 12884 12885 REG_WR(bp, params->lfa_base + 12886 offsetof(struct shmem_lfa, lfa_sts), lfa_sts); 12887 12888 /* Disable NIG DRAIN */ 12889 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); 12890 12891 /* Enable interrupts */ 12892 bnx2x_link_int_enable(params); 12893 return 0; 12894 } 12895 12896 static void bnx2x_cannot_avoid_link_flap(struct link_params *params, 12897 struct link_vars *vars, 12898 int lfa_status) 12899 { 12900 u32 lfa_sts, cfg_idx, tmp_val; 12901 struct bnx2x *bp = params->bp; 12902 12903 bnx2x_link_reset(params, vars, 1); 12904 12905 if (!params->lfa_base) 12906 return; 12907 /* Store the new link parameters */ 12908 REG_WR(bp, params->lfa_base + 12909 offsetof(struct shmem_lfa, req_duplex), 12910 params->req_duplex[0] | (params->req_duplex[1] << 16)); 12911 12912 REG_WR(bp, params->lfa_base + 12913 offsetof(struct shmem_lfa, req_flow_ctrl), 12914 params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16)); 12915 12916 REG_WR(bp, params->lfa_base + 12917 offsetof(struct shmem_lfa, req_line_speed), 12918 params->req_line_speed[0] | (params->req_line_speed[1] << 16)); 12919 12920 for (cfg_idx = 0; cfg_idx < SHMEM_LINK_CONFIG_SIZE; cfg_idx++) { 12921 REG_WR(bp, params->lfa_base + 12922 offsetof(struct shmem_lfa, 12923 speed_cap_mask[cfg_idx]), 12924 params->speed_cap_mask[cfg_idx]); 12925 } 12926 12927 tmp_val = REG_RD(bp, params->lfa_base + 12928 offsetof(struct shmem_lfa, additional_config)); 12929 tmp_val &= ~REQ_FC_AUTO_ADV_MASK; 12930 tmp_val |= params->req_fc_auto_adv; 12931 12932 REG_WR(bp, params->lfa_base + 12933 offsetof(struct shmem_lfa, additional_config), tmp_val); 12934 12935 lfa_sts = REG_RD(bp, params->lfa_base + 12936 offsetof(struct shmem_lfa, lfa_sts)); 12937 12938 /* Clear the "Don't Clear Statistics" bit, and set reason */ 12939 lfa_sts &= ~SHMEM_LFA_DONT_CLEAR_STAT; 12940 12941 /* Set link flap reason */ 12942 lfa_sts &= ~LFA_LINK_FLAP_REASON_MASK; 12943 lfa_sts |= ((lfa_status & LFA_LINK_FLAP_REASON_MASK) << 12944 LFA_LINK_FLAP_REASON_OFFSET); 12945 12946 /* Increment link flap counter */ 12947 lfa_sts = ((lfa_sts & ~LINK_FLAP_COUNT_MASK) | 12948 (((((lfa_sts & LINK_FLAP_COUNT_MASK) >> 12949 LINK_FLAP_COUNT_OFFSET) + 1) & 0xff) 12950 << LINK_FLAP_COUNT_OFFSET)); 12951 REG_WR(bp, params->lfa_base + 12952 offsetof(struct shmem_lfa, lfa_sts), lfa_sts); 12953 /* Proceed with regular link initialization */ 12954 } 12955 12956 int bnx2x_phy_init(struct link_params *params, struct link_vars *vars) 12957 { 12958 int lfa_status; 12959 struct bnx2x *bp = params->bp; 12960 DP(NETIF_MSG_LINK, "Phy Initialization started\n"); 12961 DP(NETIF_MSG_LINK, "(1) req_speed %d, req_flowctrl %d\n", 12962 params->req_line_speed[0], params->req_flow_ctrl[0]); 12963 DP(NETIF_MSG_LINK, "(2) req_speed %d, req_flowctrl %d\n", 12964 params->req_line_speed[1], params->req_flow_ctrl[1]); 12965 DP(NETIF_MSG_LINK, "req_adv_flow_ctrl 0x%x\n", params->req_fc_auto_adv); 12966 vars->link_status = 0; 12967 vars->phy_link_up = 0; 12968 vars->link_up = 0; 12969 vars->line_speed = 0; 12970 vars->duplex = DUPLEX_FULL; 12971 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; 12972 vars->mac_type = MAC_TYPE_NONE; 12973 vars->phy_flags = 0; 12974 vars->check_kr2_recovery_cnt = 0; 12975 params->link_flags = PHY_INITIALIZED; 12976 /* Driver opens NIG-BRB filters */ 12977 bnx2x_set_rx_filter(params, 1); 12978 bnx2x_chng_link_count(params, true); 12979 /* Check if link flap can be avoided */ 12980 lfa_status = bnx2x_check_lfa(params); 12981 12982 if (lfa_status == 0) { 12983 DP(NETIF_MSG_LINK, "Link Flap Avoidance in progress\n"); 12984 return bnx2x_avoid_link_flap(params, vars); 12985 } 12986 12987 DP(NETIF_MSG_LINK, "Cannot avoid link flap lfa_sta=0x%x\n", 12988 lfa_status); 12989 bnx2x_cannot_avoid_link_flap(params, vars, lfa_status); 12990 12991 /* Disable attentions */ 12992 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4, 12993 (NIG_MASK_XGXS0_LINK_STATUS | 12994 NIG_MASK_XGXS0_LINK10G | 12995 NIG_MASK_SERDES0_LINK_STATUS | 12996 NIG_MASK_MI_INT)); 12997 12998 bnx2x_emac_init(params, vars); 12999 13000 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) 13001 vars->link_status |= LINK_STATUS_PFC_ENABLED; 13002 13003 if (params->num_phys == 0) { 13004 DP(NETIF_MSG_LINK, "No phy found for initialization !!\n"); 13005 return -EINVAL; 13006 } 13007 set_phy_vars(params, vars); 13008 13009 DP(NETIF_MSG_LINK, "Num of phys on board: %d\n", params->num_phys); 13010 switch (params->loopback_mode) { 13011 case LOOPBACK_BMAC: 13012 bnx2x_init_bmac_loopback(params, vars); 13013 break; 13014 case LOOPBACK_EMAC: 13015 bnx2x_init_emac_loopback(params, vars); 13016 break; 13017 case LOOPBACK_XMAC: 13018 bnx2x_init_xmac_loopback(params, vars); 13019 break; 13020 case LOOPBACK_UMAC: 13021 bnx2x_init_umac_loopback(params, vars); 13022 break; 13023 case LOOPBACK_XGXS: 13024 case LOOPBACK_EXT_PHY: 13025 bnx2x_init_xgxs_loopback(params, vars); 13026 break; 13027 default: 13028 if (!CHIP_IS_E3(bp)) { 13029 if (params->switch_cfg == SWITCH_CFG_10G) 13030 bnx2x_xgxs_deassert(params); 13031 else 13032 bnx2x_serdes_deassert(bp, params->port); 13033 } 13034 bnx2x_link_initialize(params, vars); 13035 msleep(30); 13036 bnx2x_link_int_enable(params); 13037 break; 13038 } 13039 bnx2x_update_mng(params, vars->link_status); 13040 13041 bnx2x_update_mng_eee(params, vars->eee_status); 13042 return 0; 13043 } 13044 13045 int bnx2x_link_reset(struct link_params *params, struct link_vars *vars, 13046 u8 reset_ext_phy) 13047 { 13048 struct bnx2x *bp = params->bp; 13049 u8 phy_index, port = params->port, clear_latch_ind = 0; 13050 DP(NETIF_MSG_LINK, "Resetting the link of port %d\n", port); 13051 /* Disable attentions */ 13052 vars->link_status = 0; 13053 bnx2x_chng_link_count(params, true); 13054 bnx2x_update_mng(params, vars->link_status); 13055 vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK | 13056 SHMEM_EEE_ACTIVE_BIT); 13057 bnx2x_update_mng_eee(params, vars->eee_status); 13058 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 13059 (NIG_MASK_XGXS0_LINK_STATUS | 13060 NIG_MASK_XGXS0_LINK10G | 13061 NIG_MASK_SERDES0_LINK_STATUS | 13062 NIG_MASK_MI_INT)); 13063 13064 /* Activate nig drain */ 13065 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1); 13066 13067 /* Disable nig egress interface */ 13068 if (!CHIP_IS_E3(bp)) { 13069 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0); 13070 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0); 13071 } 13072 13073 if (!CHIP_IS_E3(bp)) { 13074 bnx2x_set_bmac_rx(bp, params->chip_id, port, 0); 13075 } else { 13076 bnx2x_set_xmac_rxtx(params, 0); 13077 bnx2x_set_umac_rxtx(params, 0); 13078 } 13079 /* Disable emac */ 13080 if (!CHIP_IS_E3(bp)) 13081 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0); 13082 13083 usleep_range(10000, 20000); 13084 /* The PHY reset is controlled by GPIO 1 13085 * Hold it as vars low 13086 */ 13087 /* Clear link led */ 13088 bnx2x_set_mdio_emac_per_phy(bp, params); 13089 bnx2x_set_led(params, vars, LED_MODE_OFF, 0); 13090 13091 if (reset_ext_phy) { 13092 for (phy_index = EXT_PHY1; phy_index < params->num_phys; 13093 phy_index++) { 13094 if (params->phy[phy_index].link_reset) { 13095 bnx2x_set_aer_mmd(params, 13096 ¶ms->phy[phy_index]); 13097 params->phy[phy_index].link_reset( 13098 ¶ms->phy[phy_index], 13099 params); 13100 } 13101 if (params->phy[phy_index].flags & 13102 FLAGS_REARM_LATCH_SIGNAL) 13103 clear_latch_ind = 1; 13104 } 13105 } 13106 13107 if (clear_latch_ind) { 13108 /* Clear latching indication */ 13109 bnx2x_rearm_latch_signal(bp, port, 0); 13110 bnx2x_bits_dis(bp, NIG_REG_LATCH_BC_0 + port*4, 13111 1 << NIG_LATCH_BC_ENABLE_MI_INT); 13112 } 13113 if (params->phy[INT_PHY].link_reset) 13114 params->phy[INT_PHY].link_reset( 13115 ¶ms->phy[INT_PHY], params); 13116 13117 /* Disable nig ingress interface */ 13118 if (!CHIP_IS_E3(bp)) { 13119 /* Reset BigMac */ 13120 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 13121 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); 13122 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0); 13123 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0); 13124 } else { 13125 u32 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; 13126 bnx2x_set_xumac_nig(params, 0, 0); 13127 if (REG_RD(bp, MISC_REG_RESET_REG_2) & 13128 MISC_REGISTERS_RESET_REG_2_XMAC) 13129 REG_WR(bp, xmac_base + XMAC_REG_CTRL, 13130 XMAC_CTRL_REG_SOFT_RESET); 13131 } 13132 vars->link_up = 0; 13133 vars->phy_flags = 0; 13134 return 0; 13135 } 13136 int bnx2x_lfa_reset(struct link_params *params, 13137 struct link_vars *vars) 13138 { 13139 struct bnx2x *bp = params->bp; 13140 vars->link_up = 0; 13141 vars->phy_flags = 0; 13142 params->link_flags &= ~PHY_INITIALIZED; 13143 if (!params->lfa_base) 13144 return bnx2x_link_reset(params, vars, 1); 13145 /* 13146 * Activate NIG drain so that during this time the device won't send 13147 * anything while it is unable to response. 13148 */ 13149 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1); 13150 13151 /* 13152 * Close gracefully the gate from BMAC to NIG such that no half packets 13153 * are passed. 13154 */ 13155 if (!CHIP_IS_E3(bp)) 13156 bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 0); 13157 13158 if (CHIP_IS_E3(bp)) { 13159 bnx2x_set_xmac_rxtx(params, 0); 13160 bnx2x_set_umac_rxtx(params, 0); 13161 } 13162 /* Wait 10ms for the pipe to clean up*/ 13163 usleep_range(10000, 20000); 13164 13165 /* Clean the NIG-BRB using the network filters in a way that will 13166 * not cut a packet in the middle. 13167 */ 13168 bnx2x_set_rx_filter(params, 0); 13169 13170 /* 13171 * Re-open the gate between the BMAC and the NIG, after verifying the 13172 * gate to the BRB is closed, otherwise packets may arrive to the 13173 * firmware before driver had initialized it. The target is to achieve 13174 * minimum management protocol down time. 13175 */ 13176 if (!CHIP_IS_E3(bp)) 13177 bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 1); 13178 13179 if (CHIP_IS_E3(bp)) { 13180 bnx2x_set_xmac_rxtx(params, 1); 13181 bnx2x_set_umac_rxtx(params, 1); 13182 } 13183 /* Disable NIG drain */ 13184 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); 13185 return 0; 13186 } 13187 13188 /****************************************************************************/ 13189 /* Common function */ 13190 /****************************************************************************/ 13191 static int bnx2x_8073_common_init_phy(struct bnx2x *bp, 13192 u32 shmem_base_path[], 13193 u32 shmem2_base_path[], u8 phy_index, 13194 u32 chip_id) 13195 { 13196 struct bnx2x_phy phy[PORT_MAX]; 13197 struct bnx2x_phy *phy_blk[PORT_MAX]; 13198 u16 val; 13199 s8 port = 0; 13200 s8 port_of_path = 0; 13201 u32 swap_val, swap_override; 13202 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); 13203 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); 13204 port ^= (swap_val && swap_override); 13205 bnx2x_ext_phy_hw_reset(bp, port); 13206 /* PART1 - Reset both phys */ 13207 for (port = PORT_MAX - 1; port >= PORT_0; port--) { 13208 u32 shmem_base, shmem2_base; 13209 /* In E2, same phy is using for port0 of the two paths */ 13210 if (CHIP_IS_E1x(bp)) { 13211 shmem_base = shmem_base_path[0]; 13212 shmem2_base = shmem2_base_path[0]; 13213 port_of_path = port; 13214 } else { 13215 shmem_base = shmem_base_path[port]; 13216 shmem2_base = shmem2_base_path[port]; 13217 port_of_path = 0; 13218 } 13219 13220 /* Extract the ext phy address for the port */ 13221 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base, 13222 port_of_path, &phy[port]) != 13223 0) { 13224 DP(NETIF_MSG_LINK, "populate_phy failed\n"); 13225 return -EINVAL; 13226 } 13227 /* Disable attentions */ 13228 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + 13229 port_of_path*4, 13230 (NIG_MASK_XGXS0_LINK_STATUS | 13231 NIG_MASK_XGXS0_LINK10G | 13232 NIG_MASK_SERDES0_LINK_STATUS | 13233 NIG_MASK_MI_INT)); 13234 13235 /* Need to take the phy out of low power mode in order 13236 * to write to access its registers 13237 */ 13238 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 13239 MISC_REGISTERS_GPIO_OUTPUT_HIGH, 13240 port); 13241 13242 /* Reset the phy */ 13243 bnx2x_cl45_write(bp, &phy[port], 13244 MDIO_PMA_DEVAD, 13245 MDIO_PMA_REG_CTRL, 13246 1<<15); 13247 } 13248 13249 /* Add delay of 150ms after reset */ 13250 msleep(150); 13251 13252 if (phy[PORT_0].addr & 0x1) { 13253 phy_blk[PORT_0] = &(phy[PORT_1]); 13254 phy_blk[PORT_1] = &(phy[PORT_0]); 13255 } else { 13256 phy_blk[PORT_0] = &(phy[PORT_0]); 13257 phy_blk[PORT_1] = &(phy[PORT_1]); 13258 } 13259 13260 /* PART2 - Download firmware to both phys */ 13261 for (port = PORT_MAX - 1; port >= PORT_0; port--) { 13262 if (CHIP_IS_E1x(bp)) 13263 port_of_path = port; 13264 else 13265 port_of_path = 0; 13266 13267 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n", 13268 phy_blk[port]->addr); 13269 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port], 13270 port_of_path)) 13271 return -EINVAL; 13272 13273 /* Only set bit 10 = 1 (Tx power down) */ 13274 bnx2x_cl45_read(bp, phy_blk[port], 13275 MDIO_PMA_DEVAD, 13276 MDIO_PMA_REG_TX_POWER_DOWN, &val); 13277 13278 /* Phase1 of TX_POWER_DOWN reset */ 13279 bnx2x_cl45_write(bp, phy_blk[port], 13280 MDIO_PMA_DEVAD, 13281 MDIO_PMA_REG_TX_POWER_DOWN, 13282 (val | 1<<10)); 13283 } 13284 13285 /* Toggle Transmitter: Power down and then up with 600ms delay 13286 * between 13287 */ 13288 msleep(600); 13289 13290 /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */ 13291 for (port = PORT_MAX - 1; port >= PORT_0; port--) { 13292 /* Phase2 of POWER_DOWN_RESET */ 13293 /* Release bit 10 (Release Tx power down) */ 13294 bnx2x_cl45_read(bp, phy_blk[port], 13295 MDIO_PMA_DEVAD, 13296 MDIO_PMA_REG_TX_POWER_DOWN, &val); 13297 13298 bnx2x_cl45_write(bp, phy_blk[port], 13299 MDIO_PMA_DEVAD, 13300 MDIO_PMA_REG_TX_POWER_DOWN, (val & (~(1<<10)))); 13301 usleep_range(15000, 30000); 13302 13303 /* Read modify write the SPI-ROM version select register */ 13304 bnx2x_cl45_read(bp, phy_blk[port], 13305 MDIO_PMA_DEVAD, 13306 MDIO_PMA_REG_EDC_FFE_MAIN, &val); 13307 bnx2x_cl45_write(bp, phy_blk[port], 13308 MDIO_PMA_DEVAD, 13309 MDIO_PMA_REG_EDC_FFE_MAIN, (val | (1<<12))); 13310 13311 /* set GPIO2 back to LOW */ 13312 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 13313 MISC_REGISTERS_GPIO_OUTPUT_LOW, port); 13314 } 13315 return 0; 13316 } 13317 static int bnx2x_8726_common_init_phy(struct bnx2x *bp, 13318 u32 shmem_base_path[], 13319 u32 shmem2_base_path[], u8 phy_index, 13320 u32 chip_id) 13321 { 13322 u32 val; 13323 s8 port; 13324 struct bnx2x_phy phy; 13325 /* Use port1 because of the static port-swap */ 13326 /* Enable the module detection interrupt */ 13327 val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN); 13328 val |= ((1<<MISC_REGISTERS_GPIO_3)| 13329 (1<<(MISC_REGISTERS_GPIO_3 + MISC_REGISTERS_GPIO_PORT_SHIFT))); 13330 REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val); 13331 13332 bnx2x_ext_phy_hw_reset(bp, 0); 13333 usleep_range(5000, 10000); 13334 for (port = 0; port < PORT_MAX; port++) { 13335 u32 shmem_base, shmem2_base; 13336 13337 /* In E2, same phy is using for port0 of the two paths */ 13338 if (CHIP_IS_E1x(bp)) { 13339 shmem_base = shmem_base_path[0]; 13340 shmem2_base = shmem2_base_path[0]; 13341 } else { 13342 shmem_base = shmem_base_path[port]; 13343 shmem2_base = shmem2_base_path[port]; 13344 } 13345 /* Extract the ext phy address for the port */ 13346 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base, 13347 port, &phy) != 13348 0) { 13349 DP(NETIF_MSG_LINK, "populate phy failed\n"); 13350 return -EINVAL; 13351 } 13352 13353 /* Reset phy*/ 13354 bnx2x_cl45_write(bp, &phy, 13355 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001); 13356 13357 13358 /* Set fault module detected LED on */ 13359 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0, 13360 MISC_REGISTERS_GPIO_HIGH, 13361 port); 13362 } 13363 13364 return 0; 13365 } 13366 static void bnx2x_get_ext_phy_reset_gpio(struct bnx2x *bp, u32 shmem_base, 13367 u8 *io_gpio, u8 *io_port) 13368 { 13369 13370 u32 phy_gpio_reset = REG_RD(bp, shmem_base + 13371 offsetof(struct shmem_region, 13372 dev_info.port_hw_config[PORT_0].default_cfg)); 13373 switch (phy_gpio_reset) { 13374 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0: 13375 *io_gpio = 0; 13376 *io_port = 0; 13377 break; 13378 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0: 13379 *io_gpio = 1; 13380 *io_port = 0; 13381 break; 13382 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0: 13383 *io_gpio = 2; 13384 *io_port = 0; 13385 break; 13386 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0: 13387 *io_gpio = 3; 13388 *io_port = 0; 13389 break; 13390 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1: 13391 *io_gpio = 0; 13392 *io_port = 1; 13393 break; 13394 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1: 13395 *io_gpio = 1; 13396 *io_port = 1; 13397 break; 13398 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1: 13399 *io_gpio = 2; 13400 *io_port = 1; 13401 break; 13402 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1: 13403 *io_gpio = 3; 13404 *io_port = 1; 13405 break; 13406 default: 13407 /* Don't override the io_gpio and io_port */ 13408 break; 13409 } 13410 } 13411 13412 static int bnx2x_8727_common_init_phy(struct bnx2x *bp, 13413 u32 shmem_base_path[], 13414 u32 shmem2_base_path[], u8 phy_index, 13415 u32 chip_id) 13416 { 13417 s8 port, reset_gpio; 13418 u32 swap_val, swap_override; 13419 struct bnx2x_phy phy[PORT_MAX]; 13420 struct bnx2x_phy *phy_blk[PORT_MAX]; 13421 s8 port_of_path; 13422 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); 13423 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); 13424 13425 reset_gpio = MISC_REGISTERS_GPIO_1; 13426 port = 1; 13427 13428 /* Retrieve the reset gpio/port which control the reset. 13429 * Default is GPIO1, PORT1 13430 */ 13431 bnx2x_get_ext_phy_reset_gpio(bp, shmem_base_path[0], 13432 (u8 *)&reset_gpio, (u8 *)&port); 13433 13434 /* Calculate the port based on port swap */ 13435 port ^= (swap_val && swap_override); 13436 13437 /* Initiate PHY reset*/ 13438 bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_LOW, 13439 port); 13440 usleep_range(1000, 2000); 13441 bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_HIGH, 13442 port); 13443 13444 usleep_range(5000, 10000); 13445 13446 /* PART1 - Reset both phys */ 13447 for (port = PORT_MAX - 1; port >= PORT_0; port--) { 13448 u32 shmem_base, shmem2_base; 13449 13450 /* In E2, same phy is using for port0 of the two paths */ 13451 if (CHIP_IS_E1x(bp)) { 13452 shmem_base = shmem_base_path[0]; 13453 shmem2_base = shmem2_base_path[0]; 13454 port_of_path = port; 13455 } else { 13456 shmem_base = shmem_base_path[port]; 13457 shmem2_base = shmem2_base_path[port]; 13458 port_of_path = 0; 13459 } 13460 13461 /* Extract the ext phy address for the port */ 13462 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base, 13463 port_of_path, &phy[port]) != 13464 0) { 13465 DP(NETIF_MSG_LINK, "populate phy failed\n"); 13466 return -EINVAL; 13467 } 13468 /* disable attentions */ 13469 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + 13470 port_of_path*4, 13471 (NIG_MASK_XGXS0_LINK_STATUS | 13472 NIG_MASK_XGXS0_LINK10G | 13473 NIG_MASK_SERDES0_LINK_STATUS | 13474 NIG_MASK_MI_INT)); 13475 13476 13477 /* Reset the phy */ 13478 bnx2x_cl45_write(bp, &phy[port], 13479 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15); 13480 } 13481 13482 /* Add delay of 150ms after reset */ 13483 msleep(150); 13484 if (phy[PORT_0].addr & 0x1) { 13485 phy_blk[PORT_0] = &(phy[PORT_1]); 13486 phy_blk[PORT_1] = &(phy[PORT_0]); 13487 } else { 13488 phy_blk[PORT_0] = &(phy[PORT_0]); 13489 phy_blk[PORT_1] = &(phy[PORT_1]); 13490 } 13491 /* PART2 - Download firmware to both phys */ 13492 for (port = PORT_MAX - 1; port >= PORT_0; port--) { 13493 if (CHIP_IS_E1x(bp)) 13494 port_of_path = port; 13495 else 13496 port_of_path = 0; 13497 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n", 13498 phy_blk[port]->addr); 13499 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port], 13500 port_of_path)) 13501 return -EINVAL; 13502 /* Disable PHY transmitter output */ 13503 bnx2x_cl45_write(bp, phy_blk[port], 13504 MDIO_PMA_DEVAD, 13505 MDIO_PMA_REG_TX_DISABLE, 1); 13506 13507 } 13508 return 0; 13509 } 13510 13511 static int bnx2x_84833_common_init_phy(struct bnx2x *bp, 13512 u32 shmem_base_path[], 13513 u32 shmem2_base_path[], 13514 u8 phy_index, 13515 u32 chip_id) 13516 { 13517 u8 reset_gpios; 13518 reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path, chip_id); 13519 bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW); 13520 udelay(10); 13521 bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_HIGH); 13522 DP(NETIF_MSG_LINK, "84833 reset pulse on pin values 0x%x\n", 13523 reset_gpios); 13524 return 0; 13525 } 13526 13527 static int bnx2x_ext_phy_common_init(struct bnx2x *bp, u32 shmem_base_path[], 13528 u32 shmem2_base_path[], u8 phy_index, 13529 u32 ext_phy_type, u32 chip_id) 13530 { 13531 int rc = 0; 13532 13533 switch (ext_phy_type) { 13534 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073: 13535 rc = bnx2x_8073_common_init_phy(bp, shmem_base_path, 13536 shmem2_base_path, 13537 phy_index, chip_id); 13538 break; 13539 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722: 13540 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: 13541 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC: 13542 rc = bnx2x_8727_common_init_phy(bp, shmem_base_path, 13543 shmem2_base_path, 13544 phy_index, chip_id); 13545 break; 13546 13547 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: 13548 /* GPIO1 affects both ports, so there's need to pull 13549 * it for single port alone 13550 */ 13551 rc = bnx2x_8726_common_init_phy(bp, shmem_base_path, 13552 shmem2_base_path, 13553 phy_index, chip_id); 13554 break; 13555 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833: 13556 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834: 13557 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858: 13558 /* GPIO3's are linked, and so both need to be toggled 13559 * to obtain required 2us pulse. 13560 */ 13561 rc = bnx2x_84833_common_init_phy(bp, shmem_base_path, 13562 shmem2_base_path, 13563 phy_index, chip_id); 13564 break; 13565 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE: 13566 rc = -EINVAL; 13567 break; 13568 default: 13569 DP(NETIF_MSG_LINK, 13570 "ext_phy 0x%x common init not required\n", 13571 ext_phy_type); 13572 break; 13573 } 13574 13575 if (rc) 13576 netdev_err(bp->dev, "Warning: PHY was not initialized," 13577 " Port %d\n", 13578 0); 13579 return rc; 13580 } 13581 13582 int bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base_path[], 13583 u32 shmem2_base_path[], u32 chip_id) 13584 { 13585 int rc = 0; 13586 u32 phy_ver, val; 13587 u8 phy_index = 0; 13588 u32 ext_phy_type, ext_phy_config; 13589 13590 bnx2x_set_mdio_clk(bp, chip_id, GRCBASE_EMAC0); 13591 bnx2x_set_mdio_clk(bp, chip_id, GRCBASE_EMAC1); 13592 DP(NETIF_MSG_LINK, "Begin common phy init\n"); 13593 if (CHIP_IS_E3(bp)) { 13594 /* Enable EPIO */ 13595 val = REG_RD(bp, MISC_REG_GEN_PURP_HWG); 13596 REG_WR(bp, MISC_REG_GEN_PURP_HWG, val | 1); 13597 } 13598 /* Check if common init was already done */ 13599 phy_ver = REG_RD(bp, shmem_base_path[0] + 13600 offsetof(struct shmem_region, 13601 port_mb[PORT_0].ext_phy_fw_version)); 13602 if (phy_ver) { 13603 DP(NETIF_MSG_LINK, "Not doing common init; phy ver is 0x%x\n", 13604 phy_ver); 13605 return 0; 13606 } 13607 13608 /* Read the ext_phy_type for arbitrary port(0) */ 13609 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS; 13610 phy_index++) { 13611 ext_phy_config = bnx2x_get_ext_phy_config(bp, 13612 shmem_base_path[0], 13613 phy_index, 0); 13614 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config); 13615 rc |= bnx2x_ext_phy_common_init(bp, shmem_base_path, 13616 shmem2_base_path, 13617 phy_index, ext_phy_type, 13618 chip_id); 13619 } 13620 return rc; 13621 } 13622 13623 static void bnx2x_check_over_curr(struct link_params *params, 13624 struct link_vars *vars) 13625 { 13626 struct bnx2x *bp = params->bp; 13627 u32 cfg_pin; 13628 u8 port = params->port; 13629 u32 pin_val; 13630 13631 cfg_pin = (REG_RD(bp, params->shmem_base + 13632 offsetof(struct shmem_region, 13633 dev_info.port_hw_config[port].e3_cmn_pin_cfg1)) & 13634 PORT_HW_CFG_E3_OVER_CURRENT_MASK) >> 13635 PORT_HW_CFG_E3_OVER_CURRENT_SHIFT; 13636 13637 /* Ignore check if no external input PIN available */ 13638 if (bnx2x_get_cfg_pin(bp, cfg_pin, &pin_val) != 0) 13639 return; 13640 13641 if (!pin_val) { 13642 if ((vars->phy_flags & PHY_OVER_CURRENT_FLAG) == 0) { 13643 netdev_err(bp->dev, "Error: Power fault on Port %d has" 13644 " been detected and the power to " 13645 "that SFP+ module has been removed" 13646 " to prevent failure of the card." 13647 " Please remove the SFP+ module and" 13648 " restart the system to clear this" 13649 " error.\n", 13650 params->port); 13651 vars->phy_flags |= PHY_OVER_CURRENT_FLAG; 13652 bnx2x_warpcore_power_module(params, 0); 13653 } 13654 } else 13655 vars->phy_flags &= ~PHY_OVER_CURRENT_FLAG; 13656 } 13657 13658 /* Returns 0 if no change occurred since last check; 1 otherwise. */ 13659 static u8 bnx2x_analyze_link_error(struct link_params *params, 13660 struct link_vars *vars, u32 status, 13661 u32 phy_flag, u32 link_flag, u8 notify) 13662 { 13663 struct bnx2x *bp = params->bp; 13664 /* Compare new value with previous value */ 13665 u8 led_mode; 13666 u32 old_status = (vars->phy_flags & phy_flag) ? 1 : 0; 13667 13668 if ((status ^ old_status) == 0) 13669 return 0; 13670 13671 /* If values differ */ 13672 switch (phy_flag) { 13673 case PHY_HALF_OPEN_CONN_FLAG: 13674 DP(NETIF_MSG_LINK, "Analyze Remote Fault\n"); 13675 break; 13676 case PHY_SFP_TX_FAULT_FLAG: 13677 DP(NETIF_MSG_LINK, "Analyze TX Fault\n"); 13678 break; 13679 default: 13680 DP(NETIF_MSG_LINK, "Analyze UNKNOWN\n"); 13681 } 13682 DP(NETIF_MSG_LINK, "Link changed:[%x %x]->%x\n", vars->link_up, 13683 old_status, status); 13684 13685 /* Do not touch the link in case physical link down */ 13686 if ((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0) 13687 return 1; 13688 13689 /* a. Update shmem->link_status accordingly 13690 * b. Update link_vars->link_up 13691 */ 13692 if (status) { 13693 vars->link_status &= ~LINK_STATUS_LINK_UP; 13694 vars->link_status |= link_flag; 13695 vars->link_up = 0; 13696 vars->phy_flags |= phy_flag; 13697 13698 /* activate nig drain */ 13699 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1); 13700 /* Set LED mode to off since the PHY doesn't know about these 13701 * errors 13702 */ 13703 led_mode = LED_MODE_OFF; 13704 } else { 13705 vars->link_status |= LINK_STATUS_LINK_UP; 13706 vars->link_status &= ~link_flag; 13707 vars->link_up = 1; 13708 vars->phy_flags &= ~phy_flag; 13709 led_mode = LED_MODE_OPER; 13710 13711 /* Clear nig drain */ 13712 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); 13713 } 13714 bnx2x_sync_link(params, vars); 13715 /* Update the LED according to the link state */ 13716 bnx2x_set_led(params, vars, led_mode, SPEED_10000); 13717 13718 /* Update link status in the shared memory */ 13719 bnx2x_update_mng(params, vars->link_status); 13720 13721 /* C. Trigger General Attention */ 13722 vars->periodic_flags |= PERIODIC_FLAGS_LINK_EVENT; 13723 if (notify) 13724 bnx2x_notify_link_changed(bp); 13725 13726 return 1; 13727 } 13728 13729 /****************************************************************************** 13730 * Description: 13731 * This function checks for half opened connection change indication. 13732 * When such change occurs, it calls the bnx2x_analyze_link_error 13733 * to check if Remote Fault is set or cleared. Reception of remote fault 13734 * status message in the MAC indicates that the peer's MAC has detected 13735 * a fault, for example, due to break in the TX side of fiber. 13736 * 13737 ******************************************************************************/ 13738 static int bnx2x_check_half_open_conn(struct link_params *params, 13739 struct link_vars *vars, 13740 u8 notify) 13741 { 13742 struct bnx2x *bp = params->bp; 13743 u32 lss_status = 0; 13744 u32 mac_base; 13745 /* In case link status is physically up @ 10G do */ 13746 if (((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0) || 13747 (REG_RD(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4))) 13748 return 0; 13749 13750 if (CHIP_IS_E3(bp) && 13751 (REG_RD(bp, MISC_REG_RESET_REG_2) & 13752 (MISC_REGISTERS_RESET_REG_2_XMAC))) { 13753 /* Check E3 XMAC */ 13754 /* Note that link speed cannot be queried here, since it may be 13755 * zero while link is down. In case UMAC is active, LSS will 13756 * simply not be set 13757 */ 13758 mac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; 13759 13760 /* Clear stick bits (Requires rising edge) */ 13761 REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0); 13762 REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 13763 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS | 13764 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS); 13765 if (REG_RD(bp, mac_base + XMAC_REG_RX_LSS_STATUS)) 13766 lss_status = 1; 13767 13768 bnx2x_analyze_link_error(params, vars, lss_status, 13769 PHY_HALF_OPEN_CONN_FLAG, 13770 LINK_STATUS_NONE, notify); 13771 } else if (REG_RD(bp, MISC_REG_RESET_REG_2) & 13772 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port)) { 13773 /* Check E1X / E2 BMAC */ 13774 u32 lss_status_reg; 13775 u32 wb_data[2]; 13776 mac_base = params->port ? NIG_REG_INGRESS_BMAC1_MEM : 13777 NIG_REG_INGRESS_BMAC0_MEM; 13778 /* Read BIGMAC_REGISTER_RX_LSS_STATUS */ 13779 if (CHIP_IS_E2(bp)) 13780 lss_status_reg = BIGMAC2_REGISTER_RX_LSS_STAT; 13781 else 13782 lss_status_reg = BIGMAC_REGISTER_RX_LSS_STATUS; 13783 13784 REG_RD_DMAE(bp, mac_base + lss_status_reg, wb_data, 2); 13785 lss_status = (wb_data[0] > 0); 13786 13787 bnx2x_analyze_link_error(params, vars, lss_status, 13788 PHY_HALF_OPEN_CONN_FLAG, 13789 LINK_STATUS_NONE, notify); 13790 } 13791 return 0; 13792 } 13793 static void bnx2x_sfp_tx_fault_detection(struct bnx2x_phy *phy, 13794 struct link_params *params, 13795 struct link_vars *vars) 13796 { 13797 struct bnx2x *bp = params->bp; 13798 u32 cfg_pin, value = 0; 13799 u8 led_change, port = params->port; 13800 13801 /* Get The SFP+ TX_Fault controlling pin ([eg]pio) */ 13802 cfg_pin = (REG_RD(bp, params->shmem_base + offsetof(struct shmem_region, 13803 dev_info.port_hw_config[port].e3_cmn_pin_cfg)) & 13804 PORT_HW_CFG_E3_TX_FAULT_MASK) >> 13805 PORT_HW_CFG_E3_TX_FAULT_SHIFT; 13806 13807 if (bnx2x_get_cfg_pin(bp, cfg_pin, &value)) { 13808 DP(NETIF_MSG_LINK, "Failed to read pin 0x%02x\n", cfg_pin); 13809 return; 13810 } 13811 13812 led_change = bnx2x_analyze_link_error(params, vars, value, 13813 PHY_SFP_TX_FAULT_FLAG, 13814 LINK_STATUS_SFP_TX_FAULT, 1); 13815 13816 if (led_change) { 13817 /* Change TX_Fault led, set link status for further syncs */ 13818 u8 led_mode; 13819 13820 if (vars->phy_flags & PHY_SFP_TX_FAULT_FLAG) { 13821 led_mode = MISC_REGISTERS_GPIO_HIGH; 13822 vars->link_status |= LINK_STATUS_SFP_TX_FAULT; 13823 } else { 13824 led_mode = MISC_REGISTERS_GPIO_LOW; 13825 vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT; 13826 } 13827 13828 /* If module is unapproved, led should be on regardless */ 13829 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED)) { 13830 DP(NETIF_MSG_LINK, "Change TX_Fault LED: ->%x\n", 13831 led_mode); 13832 bnx2x_set_e3_module_fault_led(params, led_mode); 13833 } 13834 } 13835 } 13836 static void bnx2x_kr2_recovery(struct link_params *params, 13837 struct link_vars *vars, 13838 struct bnx2x_phy *phy) 13839 { 13840 struct bnx2x *bp = params->bp; 13841 DP(NETIF_MSG_LINK, "KR2 recovery\n"); 13842 bnx2x_warpcore_enable_AN_KR2(phy, params, vars); 13843 bnx2x_warpcore_restart_AN_KR(phy, params); 13844 } 13845 13846 static void bnx2x_check_kr2_wa(struct link_params *params, 13847 struct link_vars *vars, 13848 struct bnx2x_phy *phy) 13849 { 13850 struct bnx2x *bp = params->bp; 13851 u16 base_page, next_page, not_kr2_device, lane; 13852 int sigdet; 13853 13854 /* Once KR2 was disabled, wait 5 seconds before checking KR2 recovery 13855 * Since some switches tend to reinit the AN process and clear the 13856 * the advertised BP/NP after ~2 seconds causing the KR2 to be disabled 13857 * and recovered many times 13858 */ 13859 if (vars->check_kr2_recovery_cnt > 0) { 13860 vars->check_kr2_recovery_cnt--; 13861 return; 13862 } 13863 13864 sigdet = bnx2x_warpcore_get_sigdet(phy, params); 13865 if (!sigdet) { 13866 if (!(params->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) { 13867 bnx2x_kr2_recovery(params, vars, phy); 13868 DP(NETIF_MSG_LINK, "No sigdet\n"); 13869 } 13870 return; 13871 } 13872 13873 lane = bnx2x_get_warpcore_lane(phy, params); 13874 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, 13875 MDIO_AER_BLOCK_AER_REG, lane); 13876 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, 13877 MDIO_AN_REG_LP_AUTO_NEG, &base_page); 13878 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, 13879 MDIO_AN_REG_LP_AUTO_NEG2, &next_page); 13880 bnx2x_set_aer_mmd(params, phy); 13881 13882 /* CL73 has not begun yet */ 13883 if (base_page == 0) { 13884 if (!(params->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) { 13885 bnx2x_kr2_recovery(params, vars, phy); 13886 DP(NETIF_MSG_LINK, "No BP\n"); 13887 } 13888 return; 13889 } 13890 13891 /* In case NP bit is not set in the BasePage, or it is set, 13892 * but only KX is advertised, declare this link partner as non-KR2 13893 * device. 13894 */ 13895 not_kr2_device = (((base_page & 0x8000) == 0) || 13896 (((base_page & 0x8000) && 13897 ((next_page & 0xe0) == 0x20)))); 13898 13899 /* In case KR2 is already disabled, check if we need to re-enable it */ 13900 if (!(params->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) { 13901 if (!not_kr2_device) { 13902 DP(NETIF_MSG_LINK, "BP=0x%x, NP=0x%x\n", base_page, 13903 next_page); 13904 bnx2x_kr2_recovery(params, vars, phy); 13905 } 13906 return; 13907 } 13908 /* KR2 is enabled, but not KR2 device */ 13909 if (not_kr2_device) { 13910 /* Disable KR2 on both lanes */ 13911 DP(NETIF_MSG_LINK, "BP=0x%x, NP=0x%x\n", base_page, next_page); 13912 bnx2x_disable_kr2(params, vars, phy); 13913 /* Restart AN on leading lane */ 13914 bnx2x_warpcore_restart_AN_KR(phy, params); 13915 return; 13916 } 13917 } 13918 13919 void bnx2x_period_func(struct link_params *params, struct link_vars *vars) 13920 { 13921 u16 phy_idx; 13922 struct bnx2x *bp = params->bp; 13923 for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) { 13924 if (params->phy[phy_idx].flags & FLAGS_TX_ERROR_CHECK) { 13925 bnx2x_set_aer_mmd(params, ¶ms->phy[phy_idx]); 13926 if (bnx2x_check_half_open_conn(params, vars, 1) != 13927 0) 13928 DP(NETIF_MSG_LINK, "Fault detection failed\n"); 13929 break; 13930 } 13931 } 13932 13933 if (CHIP_IS_E3(bp)) { 13934 struct bnx2x_phy *phy = ¶ms->phy[INT_PHY]; 13935 bnx2x_set_aer_mmd(params, phy); 13936 if (((phy->req_line_speed == SPEED_AUTO_NEG) && 13937 (phy->speed_cap_mask & 13938 PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) || 13939 (phy->req_line_speed == SPEED_20000)) 13940 bnx2x_check_kr2_wa(params, vars, phy); 13941 bnx2x_check_over_curr(params, vars); 13942 if (vars->rx_tx_asic_rst) 13943 bnx2x_warpcore_config_runtime(phy, params, vars); 13944 13945 if ((REG_RD(bp, params->shmem_base + 13946 offsetof(struct shmem_region, dev_info. 13947 port_hw_config[params->port].default_cfg)) 13948 & PORT_HW_CFG_NET_SERDES_IF_MASK) == 13949 PORT_HW_CFG_NET_SERDES_IF_SFI) { 13950 if (bnx2x_is_sfp_module_plugged(phy, params)) { 13951 bnx2x_sfp_tx_fault_detection(phy, params, vars); 13952 } else if (vars->link_status & 13953 LINK_STATUS_SFP_TX_FAULT) { 13954 /* Clean trail, interrupt corrects the leds */ 13955 vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT; 13956 vars->phy_flags &= ~PHY_SFP_TX_FAULT_FLAG; 13957 /* Update link status in the shared memory */ 13958 bnx2x_update_mng(params, vars->link_status); 13959 } 13960 } 13961 } 13962 } 13963 13964 u8 bnx2x_fan_failure_det_req(struct bnx2x *bp, 13965 u32 shmem_base, 13966 u32 shmem2_base, 13967 u8 port) 13968 { 13969 u8 phy_index, fan_failure_det_req = 0; 13970 struct bnx2x_phy phy; 13971 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS; 13972 phy_index++) { 13973 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base, 13974 port, &phy) 13975 != 0) { 13976 DP(NETIF_MSG_LINK, "populate phy failed\n"); 13977 return 0; 13978 } 13979 fan_failure_det_req |= (phy.flags & 13980 FLAGS_FAN_FAILURE_DET_REQ); 13981 } 13982 return fan_failure_det_req; 13983 } 13984 13985 void bnx2x_hw_reset_phy(struct link_params *params) 13986 { 13987 u8 phy_index; 13988 struct bnx2x *bp = params->bp; 13989 bnx2x_update_mng(params, 0); 13990 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4, 13991 (NIG_MASK_XGXS0_LINK_STATUS | 13992 NIG_MASK_XGXS0_LINK10G | 13993 NIG_MASK_SERDES0_LINK_STATUS | 13994 NIG_MASK_MI_INT)); 13995 13996 for (phy_index = INT_PHY; phy_index < MAX_PHYS; 13997 phy_index++) { 13998 if (params->phy[phy_index].hw_reset) { 13999 params->phy[phy_index].hw_reset( 14000 ¶ms->phy[phy_index], 14001 params); 14002 params->phy[phy_index] = phy_null; 14003 } 14004 } 14005 } 14006 14007 void bnx2x_init_mod_abs_int(struct bnx2x *bp, struct link_vars *vars, 14008 u32 chip_id, u32 shmem_base, u32 shmem2_base, 14009 u8 port) 14010 { 14011 u8 gpio_num = 0xff, gpio_port = 0xff, phy_index; 14012 u32 val; 14013 u32 offset, aeu_mask, swap_val, swap_override, sync_offset; 14014 if (CHIP_IS_E3(bp)) { 14015 if (bnx2x_get_mod_abs_int_cfg(bp, chip_id, 14016 shmem_base, 14017 port, 14018 &gpio_num, 14019 &gpio_port) != 0) 14020 return; 14021 } else { 14022 struct bnx2x_phy phy; 14023 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS; 14024 phy_index++) { 14025 if (bnx2x_populate_phy(bp, phy_index, shmem_base, 14026 shmem2_base, port, &phy) 14027 != 0) { 14028 DP(NETIF_MSG_LINK, "populate phy failed\n"); 14029 return; 14030 } 14031 if (phy.type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) { 14032 gpio_num = MISC_REGISTERS_GPIO_3; 14033 gpio_port = port; 14034 break; 14035 } 14036 } 14037 } 14038 14039 if (gpio_num == 0xff) 14040 return; 14041 14042 /* Set GPIO3 to trigger SFP+ module insertion/removal */ 14043 bnx2x_set_gpio(bp, gpio_num, MISC_REGISTERS_GPIO_INPUT_HI_Z, gpio_port); 14044 14045 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); 14046 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); 14047 gpio_port ^= (swap_val && swap_override); 14048 14049 vars->aeu_int_mask = AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 << 14050 (gpio_num + (gpio_port << 2)); 14051 14052 sync_offset = shmem_base + 14053 offsetof(struct shmem_region, 14054 dev_info.port_hw_config[port].aeu_int_mask); 14055 REG_WR(bp, sync_offset, vars->aeu_int_mask); 14056 14057 DP(NETIF_MSG_LINK, "Setting MOD_ABS (GPIO%d_P%d) AEU to 0x%x\n", 14058 gpio_num, gpio_port, vars->aeu_int_mask); 14059 14060 if (port == 0) 14061 offset = MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0; 14062 else 14063 offset = MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0; 14064 14065 /* Open appropriate AEU for interrupts */ 14066 aeu_mask = REG_RD(bp, offset); 14067 aeu_mask |= vars->aeu_int_mask; 14068 REG_WR(bp, offset, aeu_mask); 14069 14070 /* Enable the GPIO to trigger interrupt */ 14071 val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN); 14072 val |= 1 << (gpio_num + (gpio_port << 2)); 14073 REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val); 14074 } 14075