1 /* Copyright 2008-2013 Broadcom Corporation 2 * 3 * Unless you and Broadcom execute a separate written software license 4 * agreement governing use of this software, this software is licensed to you 5 * under the terms of the GNU General Public License version 2, available 6 * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL"). 7 * 8 * Notwithstanding the above, under no circumstances may you combine this 9 * software in any way with any other Broadcom software provided under a 10 * license other than the GPL, without Broadcom's express prior written 11 * consent. 12 * 13 * Written by Yaniv Rosner 14 * 15 */ 16 17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 18 19 #include <linux/kernel.h> 20 #include <linux/errno.h> 21 #include <linux/pci.h> 22 #include <linux/netdevice.h> 23 #include <linux/delay.h> 24 #include <linux/ethtool.h> 25 #include <linux/mutex.h> 26 27 #include "bnx2x.h" 28 #include "bnx2x_cmn.h" 29 30 typedef int (*read_sfp_module_eeprom_func_p)(struct bnx2x_phy *phy, 31 struct link_params *params, 32 u8 dev_addr, u16 addr, u8 byte_cnt, 33 u8 *o_buf, u8); 34 /********************************************************/ 35 #define ETH_HLEN 14 36 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */ 37 #define ETH_OVREHEAD (ETH_HLEN + 8 + 8) 38 #define ETH_MIN_PACKET_SIZE 60 39 #define ETH_MAX_PACKET_SIZE 1500 40 #define ETH_MAX_JUMBO_PACKET_SIZE 9600 41 #define MDIO_ACCESS_TIMEOUT 1000 42 #define WC_LANE_MAX 4 43 #define I2C_SWITCH_WIDTH 2 44 #define I2C_BSC0 0 45 #define I2C_BSC1 1 46 #define I2C_WA_RETRY_CNT 3 47 #define I2C_WA_PWR_ITER (I2C_WA_RETRY_CNT - 1) 48 #define MCPR_IMC_COMMAND_READ_OP 1 49 #define MCPR_IMC_COMMAND_WRITE_OP 2 50 51 /* LED Blink rate that will achieve ~15.9Hz */ 52 #define LED_BLINK_RATE_VAL_E3 354 53 #define LED_BLINK_RATE_VAL_E1X_E2 480 54 /***********************************************************/ 55 /* Shortcut definitions */ 56 /***********************************************************/ 57 58 #define NIG_LATCH_BC_ENABLE_MI_INT 0 59 60 #define NIG_STATUS_EMAC0_MI_INT \ 61 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT 62 #define NIG_STATUS_XGXS0_LINK10G \ 63 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G 64 #define NIG_STATUS_XGXS0_LINK_STATUS \ 65 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS 66 #define NIG_STATUS_XGXS0_LINK_STATUS_SIZE \ 67 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE 68 #define NIG_STATUS_SERDES0_LINK_STATUS \ 69 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS 70 #define NIG_MASK_MI_INT \ 71 NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT 72 #define NIG_MASK_XGXS0_LINK10G \ 73 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G 74 #define NIG_MASK_XGXS0_LINK_STATUS \ 75 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS 76 #define NIG_MASK_SERDES0_LINK_STATUS \ 77 NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS 78 79 #define MDIO_AN_CL73_OR_37_COMPLETE \ 80 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \ 81 MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE) 82 83 #define XGXS_RESET_BITS \ 84 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW | \ 85 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ | \ 86 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN | \ 87 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \ 88 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB) 89 90 #define SERDES_RESET_BITS \ 91 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \ 92 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ | \ 93 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN | \ 94 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD) 95 96 #define AUTONEG_CL37 SHARED_HW_CFG_AN_ENABLE_CL37 97 #define AUTONEG_CL73 SHARED_HW_CFG_AN_ENABLE_CL73 98 #define AUTONEG_BAM SHARED_HW_CFG_AN_ENABLE_BAM 99 #define AUTONEG_PARALLEL \ 100 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION 101 #define AUTONEG_SGMII_FIBER_AUTODET \ 102 SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT 103 #define AUTONEG_REMOTE_PHY SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY 104 105 #define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \ 106 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE 107 #define GP_STATUS_PAUSE_RSOLUTION_RXSIDE \ 108 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE 109 #define GP_STATUS_SPEED_MASK \ 110 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK 111 #define GP_STATUS_10M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M 112 #define GP_STATUS_100M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M 113 #define GP_STATUS_1G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G 114 #define GP_STATUS_2_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G 115 #define GP_STATUS_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G 116 #define GP_STATUS_6G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G 117 #define GP_STATUS_10G_HIG \ 118 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG 119 #define GP_STATUS_10G_CX4 \ 120 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4 121 #define GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX 122 #define GP_STATUS_10G_KX4 \ 123 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4 124 #define GP_STATUS_10G_KR MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR 125 #define GP_STATUS_10G_XFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI 126 #define GP_STATUS_20G_DXGXS MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS 127 #define GP_STATUS_10G_SFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI 128 #define GP_STATUS_20G_KR2 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_KR2 129 #define LINK_10THD LINK_STATUS_SPEED_AND_DUPLEX_10THD 130 #define LINK_10TFD LINK_STATUS_SPEED_AND_DUPLEX_10TFD 131 #define LINK_100TXHD LINK_STATUS_SPEED_AND_DUPLEX_100TXHD 132 #define LINK_100T4 LINK_STATUS_SPEED_AND_DUPLEX_100T4 133 #define LINK_100TXFD LINK_STATUS_SPEED_AND_DUPLEX_100TXFD 134 #define LINK_1000THD LINK_STATUS_SPEED_AND_DUPLEX_1000THD 135 #define LINK_1000TFD LINK_STATUS_SPEED_AND_DUPLEX_1000TFD 136 #define LINK_1000XFD LINK_STATUS_SPEED_AND_DUPLEX_1000XFD 137 #define LINK_2500THD LINK_STATUS_SPEED_AND_DUPLEX_2500THD 138 #define LINK_2500TFD LINK_STATUS_SPEED_AND_DUPLEX_2500TFD 139 #define LINK_2500XFD LINK_STATUS_SPEED_AND_DUPLEX_2500XFD 140 #define LINK_10GTFD LINK_STATUS_SPEED_AND_DUPLEX_10GTFD 141 #define LINK_10GXFD LINK_STATUS_SPEED_AND_DUPLEX_10GXFD 142 #define LINK_20GTFD LINK_STATUS_SPEED_AND_DUPLEX_20GTFD 143 #define LINK_20GXFD LINK_STATUS_SPEED_AND_DUPLEX_20GXFD 144 145 #define LINK_UPDATE_MASK \ 146 (LINK_STATUS_SPEED_AND_DUPLEX_MASK | \ 147 LINK_STATUS_LINK_UP | \ 148 LINK_STATUS_PHYSICAL_LINK_FLAG | \ 149 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE | \ 150 LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK | \ 151 LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK | \ 152 LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK | \ 153 LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE | \ 154 LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE) 155 156 #define SFP_EEPROM_CON_TYPE_ADDR 0x2 157 #define SFP_EEPROM_CON_TYPE_VAL_UNKNOWN 0x0 158 #define SFP_EEPROM_CON_TYPE_VAL_LC 0x7 159 #define SFP_EEPROM_CON_TYPE_VAL_COPPER 0x21 160 #define SFP_EEPROM_CON_TYPE_VAL_RJ45 0x22 161 162 163 #define SFP_EEPROM_10G_COMP_CODE_ADDR 0x3 164 #define SFP_EEPROM_10G_COMP_CODE_SR_MASK (1<<4) 165 #define SFP_EEPROM_10G_COMP_CODE_LR_MASK (1<<5) 166 #define SFP_EEPROM_10G_COMP_CODE_LRM_MASK (1<<6) 167 168 #define SFP_EEPROM_1G_COMP_CODE_ADDR 0x6 169 #define SFP_EEPROM_1G_COMP_CODE_SX (1<<0) 170 #define SFP_EEPROM_1G_COMP_CODE_LX (1<<1) 171 #define SFP_EEPROM_1G_COMP_CODE_CX (1<<2) 172 #define SFP_EEPROM_1G_COMP_CODE_BASE_T (1<<3) 173 174 #define SFP_EEPROM_FC_TX_TECH_ADDR 0x8 175 #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4 176 #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE 0x8 177 178 #define SFP_EEPROM_OPTIONS_ADDR 0x40 179 #define SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1 180 #define SFP_EEPROM_OPTIONS_SIZE 2 181 182 #define EDC_MODE_LINEAR 0x0022 183 #define EDC_MODE_LIMITING 0x0044 184 #define EDC_MODE_PASSIVE_DAC 0x0055 185 #define EDC_MODE_ACTIVE_DAC 0x0066 186 187 /* ETS defines*/ 188 #define DCBX_INVALID_COS (0xFF) 189 190 #define ETS_BW_LIMIT_CREDIT_UPPER_BOUND (0x5000) 191 #define ETS_BW_LIMIT_CREDIT_WEIGHT (0x5000) 192 #define ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS (1360) 193 #define ETS_E3B0_NIG_MIN_W_VAL_20GBPS (2720) 194 #define ETS_E3B0_PBF_MIN_W_VAL (10000) 195 196 #define MAX_PACKET_SIZE (9700) 197 #define MAX_KR_LINK_RETRY 4 198 #define DEFAULT_TX_DRV_BRDCT 2 199 #define DEFAULT_TX_DRV_IFIR 0 200 #define DEFAULT_TX_DRV_POST2 3 201 #define DEFAULT_TX_DRV_IPRE_DRIVER 6 202 203 /**********************************************************/ 204 /* INTERFACE */ 205 /**********************************************************/ 206 207 #define CL22_WR_OVER_CL45(_bp, _phy, _bank, _addr, _val) \ 208 bnx2x_cl45_write(_bp, _phy, \ 209 (_phy)->def_md_devad, \ 210 (_bank + (_addr & 0xf)), \ 211 _val) 212 213 #define CL22_RD_OVER_CL45(_bp, _phy, _bank, _addr, _val) \ 214 bnx2x_cl45_read(_bp, _phy, \ 215 (_phy)->def_md_devad, \ 216 (_bank + (_addr & 0xf)), \ 217 _val) 218 219 static int bnx2x_check_half_open_conn(struct link_params *params, 220 struct link_vars *vars, u8 notify); 221 static int bnx2x_sfp_module_detection(struct bnx2x_phy *phy, 222 struct link_params *params); 223 224 static u32 bnx2x_bits_en(struct bnx2x *bp, u32 reg, u32 bits) 225 { 226 u32 val = REG_RD(bp, reg); 227 228 val |= bits; 229 REG_WR(bp, reg, val); 230 return val; 231 } 232 233 static u32 bnx2x_bits_dis(struct bnx2x *bp, u32 reg, u32 bits) 234 { 235 u32 val = REG_RD(bp, reg); 236 237 val &= ~bits; 238 REG_WR(bp, reg, val); 239 return val; 240 } 241 242 /* 243 * bnx2x_check_lfa - This function checks if link reinitialization is required, 244 * or link flap can be avoided. 245 * 246 * @params: link parameters 247 * Returns 0 if Link Flap Avoidance conditions are met otherwise, the failed 248 * condition code. 249 */ 250 static int bnx2x_check_lfa(struct link_params *params) 251 { 252 u32 link_status, cfg_idx, lfa_mask, cfg_size; 253 u32 cur_speed_cap_mask, cur_req_fc_auto_adv, additional_config; 254 u32 saved_val, req_val, eee_status; 255 struct bnx2x *bp = params->bp; 256 257 additional_config = 258 REG_RD(bp, params->lfa_base + 259 offsetof(struct shmem_lfa, additional_config)); 260 261 /* NOTE: must be first condition checked - 262 * to verify DCC bit is cleared in any case! 263 */ 264 if (additional_config & NO_LFA_DUE_TO_DCC_MASK) { 265 DP(NETIF_MSG_LINK, "No LFA due to DCC flap after clp exit\n"); 266 REG_WR(bp, params->lfa_base + 267 offsetof(struct shmem_lfa, additional_config), 268 additional_config & ~NO_LFA_DUE_TO_DCC_MASK); 269 return LFA_DCC_LFA_DISABLED; 270 } 271 272 /* Verify that link is up */ 273 link_status = REG_RD(bp, params->shmem_base + 274 offsetof(struct shmem_region, 275 port_mb[params->port].link_status)); 276 if (!(link_status & LINK_STATUS_LINK_UP)) 277 return LFA_LINK_DOWN; 278 279 /* if loaded after BOOT from SAN, don't flap the link in any case and 280 * rely on link set by preboot driver 281 */ 282 if (params->feature_config_flags & FEATURE_CONFIG_BOOT_FROM_SAN) 283 return 0; 284 285 /* Verify that loopback mode is not set */ 286 if (params->loopback_mode) 287 return LFA_LOOPBACK_ENABLED; 288 289 /* Verify that MFW supports LFA */ 290 if (!params->lfa_base) 291 return LFA_MFW_IS_TOO_OLD; 292 293 if (params->num_phys == 3) { 294 cfg_size = 2; 295 lfa_mask = 0xffffffff; 296 } else { 297 cfg_size = 1; 298 lfa_mask = 0xffff; 299 } 300 301 /* Compare Duplex */ 302 saved_val = REG_RD(bp, params->lfa_base + 303 offsetof(struct shmem_lfa, req_duplex)); 304 req_val = params->req_duplex[0] | (params->req_duplex[1] << 16); 305 if ((saved_val & lfa_mask) != (req_val & lfa_mask)) { 306 DP(NETIF_MSG_LINK, "Duplex mismatch %x vs. %x\n", 307 (saved_val & lfa_mask), (req_val & lfa_mask)); 308 return LFA_DUPLEX_MISMATCH; 309 } 310 /* Compare Flow Control */ 311 saved_val = REG_RD(bp, params->lfa_base + 312 offsetof(struct shmem_lfa, req_flow_ctrl)); 313 req_val = params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16); 314 if ((saved_val & lfa_mask) != (req_val & lfa_mask)) { 315 DP(NETIF_MSG_LINK, "Flow control mismatch %x vs. %x\n", 316 (saved_val & lfa_mask), (req_val & lfa_mask)); 317 return LFA_FLOW_CTRL_MISMATCH; 318 } 319 /* Compare Link Speed */ 320 saved_val = REG_RD(bp, params->lfa_base + 321 offsetof(struct shmem_lfa, req_line_speed)); 322 req_val = params->req_line_speed[0] | (params->req_line_speed[1] << 16); 323 if ((saved_val & lfa_mask) != (req_val & lfa_mask)) { 324 DP(NETIF_MSG_LINK, "Link speed mismatch %x vs. %x\n", 325 (saved_val & lfa_mask), (req_val & lfa_mask)); 326 return LFA_LINK_SPEED_MISMATCH; 327 } 328 329 for (cfg_idx = 0; cfg_idx < cfg_size; cfg_idx++) { 330 cur_speed_cap_mask = REG_RD(bp, params->lfa_base + 331 offsetof(struct shmem_lfa, 332 speed_cap_mask[cfg_idx])); 333 334 if (cur_speed_cap_mask != params->speed_cap_mask[cfg_idx]) { 335 DP(NETIF_MSG_LINK, "Speed Cap mismatch %x vs. %x\n", 336 cur_speed_cap_mask, 337 params->speed_cap_mask[cfg_idx]); 338 return LFA_SPEED_CAP_MISMATCH; 339 } 340 } 341 342 cur_req_fc_auto_adv = 343 REG_RD(bp, params->lfa_base + 344 offsetof(struct shmem_lfa, additional_config)) & 345 REQ_FC_AUTO_ADV_MASK; 346 347 if ((u16)cur_req_fc_auto_adv != params->req_fc_auto_adv) { 348 DP(NETIF_MSG_LINK, "Flow Ctrl AN mismatch %x vs. %x\n", 349 cur_req_fc_auto_adv, params->req_fc_auto_adv); 350 return LFA_FLOW_CTRL_MISMATCH; 351 } 352 353 eee_status = REG_RD(bp, params->shmem2_base + 354 offsetof(struct shmem2_region, 355 eee_status[params->port])); 356 357 if (((eee_status & SHMEM_EEE_LPI_REQUESTED_BIT) ^ 358 (params->eee_mode & EEE_MODE_ENABLE_LPI)) || 359 ((eee_status & SHMEM_EEE_REQUESTED_BIT) ^ 360 (params->eee_mode & EEE_MODE_ADV_LPI))) { 361 DP(NETIF_MSG_LINK, "EEE mismatch %x vs. %x\n", params->eee_mode, 362 eee_status); 363 return LFA_EEE_MISMATCH; 364 } 365 366 /* LFA conditions are met */ 367 return 0; 368 } 369 /******************************************************************/ 370 /* EPIO/GPIO section */ 371 /******************************************************************/ 372 static void bnx2x_get_epio(struct bnx2x *bp, u32 epio_pin, u32 *en) 373 { 374 u32 epio_mask, gp_oenable; 375 *en = 0; 376 /* Sanity check */ 377 if (epio_pin > 31) { 378 DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to get\n", epio_pin); 379 return; 380 } 381 382 epio_mask = 1 << epio_pin; 383 /* Set this EPIO to output */ 384 gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE); 385 REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable & ~epio_mask); 386 387 *en = (REG_RD(bp, MCP_REG_MCPR_GP_INPUTS) & epio_mask) >> epio_pin; 388 } 389 static void bnx2x_set_epio(struct bnx2x *bp, u32 epio_pin, u32 en) 390 { 391 u32 epio_mask, gp_output, gp_oenable; 392 393 /* Sanity check */ 394 if (epio_pin > 31) { 395 DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to set\n", epio_pin); 396 return; 397 } 398 DP(NETIF_MSG_LINK, "Setting EPIO pin %d to %d\n", epio_pin, en); 399 epio_mask = 1 << epio_pin; 400 /* Set this EPIO to output */ 401 gp_output = REG_RD(bp, MCP_REG_MCPR_GP_OUTPUTS); 402 if (en) 403 gp_output |= epio_mask; 404 else 405 gp_output &= ~epio_mask; 406 407 REG_WR(bp, MCP_REG_MCPR_GP_OUTPUTS, gp_output); 408 409 /* Set the value for this EPIO */ 410 gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE); 411 REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable | epio_mask); 412 } 413 414 static void bnx2x_set_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 val) 415 { 416 if (pin_cfg == PIN_CFG_NA) 417 return; 418 if (pin_cfg >= PIN_CFG_EPIO0) { 419 bnx2x_set_epio(bp, pin_cfg - PIN_CFG_EPIO0, val); 420 } else { 421 u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3; 422 u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2; 423 bnx2x_set_gpio(bp, gpio_num, (u8)val, gpio_port); 424 } 425 } 426 427 static u32 bnx2x_get_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 *val) 428 { 429 if (pin_cfg == PIN_CFG_NA) 430 return -EINVAL; 431 if (pin_cfg >= PIN_CFG_EPIO0) { 432 bnx2x_get_epio(bp, pin_cfg - PIN_CFG_EPIO0, val); 433 } else { 434 u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3; 435 u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2; 436 *val = bnx2x_get_gpio(bp, gpio_num, gpio_port); 437 } 438 return 0; 439 440 } 441 /******************************************************************/ 442 /* ETS section */ 443 /******************************************************************/ 444 static void bnx2x_ets_e2e3a0_disabled(struct link_params *params) 445 { 446 /* ETS disabled configuration*/ 447 struct bnx2x *bp = params->bp; 448 449 DP(NETIF_MSG_LINK, "ETS E2E3 disabled configuration\n"); 450 451 /* mapping between entry priority to client number (0,1,2 -debug and 452 * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST) 453 * 3bits client num. 454 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0 455 * cos1-100 cos0-011 dbg1-010 dbg0-001 MCP-000 456 */ 457 458 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, 0x4688); 459 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves 460 * as strict. Bits 0,1,2 - debug and management entries, 3 - 461 * COS0 entry, 4 - COS1 entry. 462 * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT 463 * bit4 bit3 bit2 bit1 bit0 464 * MCP and debug are strict 465 */ 466 467 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7); 468 /* defines which entries (clients) are subjected to WFQ arbitration */ 469 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0); 470 /* For strict priority entries defines the number of consecutive 471 * slots for the highest priority. 472 */ 473 REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100); 474 /* mapping between the CREDIT_WEIGHT registers and actual client 475 * numbers 476 */ 477 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0); 478 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0); 479 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0); 480 481 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 0); 482 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 0); 483 REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, 0); 484 /* ETS mode disable */ 485 REG_WR(bp, PBF_REG_ETS_ENABLED, 0); 486 /* If ETS mode is enabled (there is no strict priority) defines a WFQ 487 * weight for COS0/COS1. 488 */ 489 REG_WR(bp, PBF_REG_COS0_WEIGHT, 0x2710); 490 REG_WR(bp, PBF_REG_COS1_WEIGHT, 0x2710); 491 /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter */ 492 REG_WR(bp, PBF_REG_COS0_UPPER_BOUND, 0x989680); 493 REG_WR(bp, PBF_REG_COS1_UPPER_BOUND, 0x989680); 494 /* Defines the number of consecutive slots for the strict priority */ 495 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0); 496 } 497 /****************************************************************************** 498 * Description: 499 * Getting min_w_val will be set according to line speed . 500 *. 501 ******************************************************************************/ 502 static u32 bnx2x_ets_get_min_w_val_nig(const struct link_vars *vars) 503 { 504 u32 min_w_val = 0; 505 /* Calculate min_w_val.*/ 506 if (vars->link_up) { 507 if (vars->line_speed == SPEED_20000) 508 min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS; 509 else 510 min_w_val = ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS; 511 } else 512 min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS; 513 /* If the link isn't up (static configuration for example ) The 514 * link will be according to 20GBPS. 515 */ 516 return min_w_val; 517 } 518 /****************************************************************************** 519 * Description: 520 * Getting credit upper bound form min_w_val. 521 *. 522 ******************************************************************************/ 523 static u32 bnx2x_ets_get_credit_upper_bound(const u32 min_w_val) 524 { 525 const u32 credit_upper_bound = (u32)MAXVAL((150 * min_w_val), 526 MAX_PACKET_SIZE); 527 return credit_upper_bound; 528 } 529 /****************************************************************************** 530 * Description: 531 * Set credit upper bound for NIG. 532 *. 533 ******************************************************************************/ 534 static void bnx2x_ets_e3b0_set_credit_upper_bound_nig( 535 const struct link_params *params, 536 const u32 min_w_val) 537 { 538 struct bnx2x *bp = params->bp; 539 const u8 port = params->port; 540 const u32 credit_upper_bound = 541 bnx2x_ets_get_credit_upper_bound(min_w_val); 542 543 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 : 544 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, credit_upper_bound); 545 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 : 546 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, credit_upper_bound); 547 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 : 548 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_2, credit_upper_bound); 549 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 : 550 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_3, credit_upper_bound); 551 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 : 552 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_4, credit_upper_bound); 553 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 : 554 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_5, credit_upper_bound); 555 556 if (!port) { 557 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6, 558 credit_upper_bound); 559 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7, 560 credit_upper_bound); 561 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8, 562 credit_upper_bound); 563 } 564 } 565 /****************************************************************************** 566 * Description: 567 * Will return the NIG ETS registers to init values.Except 568 * credit_upper_bound. 569 * That isn't used in this configuration (No WFQ is enabled) and will be 570 * configured according to spec 571 *. 572 ******************************************************************************/ 573 static void bnx2x_ets_e3b0_nig_disabled(const struct link_params *params, 574 const struct link_vars *vars) 575 { 576 struct bnx2x *bp = params->bp; 577 const u8 port = params->port; 578 const u32 min_w_val = bnx2x_ets_get_min_w_val_nig(vars); 579 /* Mapping between entry priority to client number (0,1,2 -debug and 580 * management clients, 3 - COS0 client, 4 - COS1, ... 8 - 581 * COS5)(HIGHEST) 4bits client num.TODO_ETS - Should be done by 582 * reset value or init tool 583 */ 584 if (port) { 585 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, 0x543210); 586 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB, 0x0); 587 } else { 588 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, 0x76543210); 589 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, 0x8); 590 } 591 /* For strict priority entries defines the number of consecutive 592 * slots for the highest priority. 593 */ 594 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS : 595 NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100); 596 /* Mapping between the CREDIT_WEIGHT registers and actual client 597 * numbers 598 */ 599 if (port) { 600 /*Port 1 has 6 COS*/ 601 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB, 0x210543); 602 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x0); 603 } else { 604 /*Port 0 has 9 COS*/ 605 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB, 606 0x43210876); 607 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x5); 608 } 609 610 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves 611 * as strict. Bits 0,1,2 - debug and management entries, 3 - 612 * COS0 entry, 4 - COS1 entry. 613 * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT 614 * bit4 bit3 bit2 bit1 bit0 615 * MCP and debug are strict 616 */ 617 if (port) 618 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT, 0x3f); 619 else 620 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1ff); 621 /* defines which entries (clients) are subjected to WFQ arbitration */ 622 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ : 623 NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0); 624 625 /* Please notice the register address are note continuous and a 626 * for here is note appropriate.In 2 port mode port0 only COS0-5 627 * can be used. DEBUG1,DEBUG1,MGMT are never used for WFQ* In 4 628 * port mode port1 only COS0-2 can be used. DEBUG1,DEBUG1,MGMT 629 * are never used for WFQ 630 */ 631 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 : 632 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0x0); 633 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 : 634 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0x0); 635 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 : 636 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2, 0x0); 637 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 : 638 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3, 0x0); 639 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 : 640 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4, 0x0); 641 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 : 642 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5, 0x0); 643 if (!port) { 644 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6, 0x0); 645 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7, 0x0); 646 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8, 0x0); 647 } 648 649 bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val); 650 } 651 /****************************************************************************** 652 * Description: 653 * Set credit upper bound for PBF. 654 *. 655 ******************************************************************************/ 656 static void bnx2x_ets_e3b0_set_credit_upper_bound_pbf( 657 const struct link_params *params, 658 const u32 min_w_val) 659 { 660 struct bnx2x *bp = params->bp; 661 const u32 credit_upper_bound = 662 bnx2x_ets_get_credit_upper_bound(min_w_val); 663 const u8 port = params->port; 664 u32 base_upper_bound = 0; 665 u8 max_cos = 0; 666 u8 i = 0; 667 /* In 2 port mode port0 has COS0-5 that can be used for WFQ.In 4 668 * port mode port1 has COS0-2 that can be used for WFQ. 669 */ 670 if (!port) { 671 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P0; 672 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0; 673 } else { 674 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P1; 675 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT1; 676 } 677 678 for (i = 0; i < max_cos; i++) 679 REG_WR(bp, base_upper_bound + (i << 2), credit_upper_bound); 680 } 681 682 /****************************************************************************** 683 * Description: 684 * Will return the PBF ETS registers to init values.Except 685 * credit_upper_bound. 686 * That isn't used in this configuration (No WFQ is enabled) and will be 687 * configured according to spec 688 *. 689 ******************************************************************************/ 690 static void bnx2x_ets_e3b0_pbf_disabled(const struct link_params *params) 691 { 692 struct bnx2x *bp = params->bp; 693 const u8 port = params->port; 694 const u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL; 695 u8 i = 0; 696 u32 base_weight = 0; 697 u8 max_cos = 0; 698 699 /* Mapping between entry priority to client number 0 - COS0 700 * client, 2 - COS1, ... 5 - COS5)(HIGHEST) 4bits client num. 701 * TODO_ETS - Should be done by reset value or init tool 702 */ 703 if (port) 704 /* 0x688 (|011|0 10|00 1|000) */ 705 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , 0x688); 706 else 707 /* (10 1|100 |011|0 10|00 1|000) */ 708 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , 0x2C688); 709 710 /* TODO_ETS - Should be done by reset value or init tool */ 711 if (port) 712 /* 0x688 (|011|0 10|00 1|000)*/ 713 REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1, 0x688); 714 else 715 /* 0x2C688 (10 1|100 |011|0 10|00 1|000) */ 716 REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0, 0x2C688); 717 718 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 : 719 PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0 , 0x100); 720 721 722 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 : 723 PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , 0); 724 725 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 : 726 PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0 , 0); 727 /* In 2 port mode port0 has COS0-5 that can be used for WFQ. 728 * In 4 port mode port1 has COS0-2 that can be used for WFQ. 729 */ 730 if (!port) { 731 base_weight = PBF_REG_COS0_WEIGHT_P0; 732 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0; 733 } else { 734 base_weight = PBF_REG_COS0_WEIGHT_P1; 735 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT1; 736 } 737 738 for (i = 0; i < max_cos; i++) 739 REG_WR(bp, base_weight + (0x4 * i), 0); 740 741 bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf); 742 } 743 /****************************************************************************** 744 * Description: 745 * E3B0 disable will return basically the values to init values. 746 *. 747 ******************************************************************************/ 748 static int bnx2x_ets_e3b0_disabled(const struct link_params *params, 749 const struct link_vars *vars) 750 { 751 struct bnx2x *bp = params->bp; 752 753 if (!CHIP_IS_E3B0(bp)) { 754 DP(NETIF_MSG_LINK, 755 "bnx2x_ets_e3b0_disabled the chip isn't E3B0\n"); 756 return -EINVAL; 757 } 758 759 bnx2x_ets_e3b0_nig_disabled(params, vars); 760 761 bnx2x_ets_e3b0_pbf_disabled(params); 762 763 return 0; 764 } 765 766 /****************************************************************************** 767 * Description: 768 * Disable will return basically the values to init values. 769 * 770 ******************************************************************************/ 771 int bnx2x_ets_disabled(struct link_params *params, 772 struct link_vars *vars) 773 { 774 struct bnx2x *bp = params->bp; 775 int bnx2x_status = 0; 776 777 if ((CHIP_IS_E2(bp)) || (CHIP_IS_E3A0(bp))) 778 bnx2x_ets_e2e3a0_disabled(params); 779 else if (CHIP_IS_E3B0(bp)) 780 bnx2x_status = bnx2x_ets_e3b0_disabled(params, vars); 781 else { 782 DP(NETIF_MSG_LINK, "bnx2x_ets_disabled - chip not supported\n"); 783 return -EINVAL; 784 } 785 786 return bnx2x_status; 787 } 788 789 /****************************************************************************** 790 * Description 791 * Set the COS mappimg to SP and BW until this point all the COS are not 792 * set as SP or BW. 793 ******************************************************************************/ 794 static int bnx2x_ets_e3b0_cli_map(const struct link_params *params, 795 const struct bnx2x_ets_params *ets_params, 796 const u8 cos_sp_bitmap, 797 const u8 cos_bw_bitmap) 798 { 799 struct bnx2x *bp = params->bp; 800 const u8 port = params->port; 801 const u8 nig_cli_sp_bitmap = 0x7 | (cos_sp_bitmap << 3); 802 const u8 pbf_cli_sp_bitmap = cos_sp_bitmap; 803 const u8 nig_cli_subject2wfq_bitmap = cos_bw_bitmap << 3; 804 const u8 pbf_cli_subject2wfq_bitmap = cos_bw_bitmap; 805 806 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT : 807 NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, nig_cli_sp_bitmap); 808 809 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 : 810 PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , pbf_cli_sp_bitmap); 811 812 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ : 813 NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 814 nig_cli_subject2wfq_bitmap); 815 816 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 : 817 PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0, 818 pbf_cli_subject2wfq_bitmap); 819 820 return 0; 821 } 822 823 /****************************************************************************** 824 * Description: 825 * This function is needed because NIG ARB_CREDIT_WEIGHT_X are 826 * not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable. 827 ******************************************************************************/ 828 static int bnx2x_ets_e3b0_set_cos_bw(struct bnx2x *bp, 829 const u8 cos_entry, 830 const u32 min_w_val_nig, 831 const u32 min_w_val_pbf, 832 const u16 total_bw, 833 const u8 bw, 834 const u8 port) 835 { 836 u32 nig_reg_adress_crd_weight = 0; 837 u32 pbf_reg_adress_crd_weight = 0; 838 /* Calculate and set BW for this COS - use 1 instead of 0 for BW */ 839 const u32 cos_bw_nig = ((bw ? bw : 1) * min_w_val_nig) / total_bw; 840 const u32 cos_bw_pbf = ((bw ? bw : 1) * min_w_val_pbf) / total_bw; 841 842 switch (cos_entry) { 843 case 0: 844 nig_reg_adress_crd_weight = 845 (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 : 846 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0; 847 pbf_reg_adress_crd_weight = (port) ? 848 PBF_REG_COS0_WEIGHT_P1 : PBF_REG_COS0_WEIGHT_P0; 849 break; 850 case 1: 851 nig_reg_adress_crd_weight = (port) ? 852 NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 : 853 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1; 854 pbf_reg_adress_crd_weight = (port) ? 855 PBF_REG_COS1_WEIGHT_P1 : PBF_REG_COS1_WEIGHT_P0; 856 break; 857 case 2: 858 nig_reg_adress_crd_weight = (port) ? 859 NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 : 860 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2; 861 862 pbf_reg_adress_crd_weight = (port) ? 863 PBF_REG_COS2_WEIGHT_P1 : PBF_REG_COS2_WEIGHT_P0; 864 break; 865 case 3: 866 if (port) 867 return -EINVAL; 868 nig_reg_adress_crd_weight = 869 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3; 870 pbf_reg_adress_crd_weight = 871 PBF_REG_COS3_WEIGHT_P0; 872 break; 873 case 4: 874 if (port) 875 return -EINVAL; 876 nig_reg_adress_crd_weight = 877 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4; 878 pbf_reg_adress_crd_weight = PBF_REG_COS4_WEIGHT_P0; 879 break; 880 case 5: 881 if (port) 882 return -EINVAL; 883 nig_reg_adress_crd_weight = 884 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5; 885 pbf_reg_adress_crd_weight = PBF_REG_COS5_WEIGHT_P0; 886 break; 887 } 888 889 REG_WR(bp, nig_reg_adress_crd_weight, cos_bw_nig); 890 891 REG_WR(bp, pbf_reg_adress_crd_weight, cos_bw_pbf); 892 893 return 0; 894 } 895 /****************************************************************************** 896 * Description: 897 * Calculate the total BW.A value of 0 isn't legal. 898 * 899 ******************************************************************************/ 900 static int bnx2x_ets_e3b0_get_total_bw( 901 const struct link_params *params, 902 struct bnx2x_ets_params *ets_params, 903 u16 *total_bw) 904 { 905 struct bnx2x *bp = params->bp; 906 u8 cos_idx = 0; 907 u8 is_bw_cos_exist = 0; 908 909 *total_bw = 0 ; 910 /* Calculate total BW requested */ 911 for (cos_idx = 0; cos_idx < ets_params->num_of_cos; cos_idx++) { 912 if (ets_params->cos[cos_idx].state == bnx2x_cos_state_bw) { 913 is_bw_cos_exist = 1; 914 if (!ets_params->cos[cos_idx].params.bw_params.bw) { 915 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config BW" 916 "was set to 0\n"); 917 /* This is to prevent a state when ramrods 918 * can't be sent 919 */ 920 ets_params->cos[cos_idx].params.bw_params.bw 921 = 1; 922 } 923 *total_bw += 924 ets_params->cos[cos_idx].params.bw_params.bw; 925 } 926 } 927 928 /* Check total BW is valid */ 929 if ((is_bw_cos_exist == 1) && (*total_bw != 100)) { 930 if (*total_bw == 0) { 931 DP(NETIF_MSG_LINK, 932 "bnx2x_ets_E3B0_config total BW shouldn't be 0\n"); 933 return -EINVAL; 934 } 935 DP(NETIF_MSG_LINK, 936 "bnx2x_ets_E3B0_config total BW should be 100\n"); 937 /* We can handle a case whre the BW isn't 100 this can happen 938 * if the TC are joined. 939 */ 940 } 941 return 0; 942 } 943 944 /****************************************************************************** 945 * Description: 946 * Invalidate all the sp_pri_to_cos. 947 * 948 ******************************************************************************/ 949 static void bnx2x_ets_e3b0_sp_pri_to_cos_init(u8 *sp_pri_to_cos) 950 { 951 u8 pri = 0; 952 for (pri = 0; pri < DCBX_MAX_NUM_COS; pri++) 953 sp_pri_to_cos[pri] = DCBX_INVALID_COS; 954 } 955 /****************************************************************************** 956 * Description: 957 * Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers 958 * according to sp_pri_to_cos. 959 * 960 ******************************************************************************/ 961 static int bnx2x_ets_e3b0_sp_pri_to_cos_set(const struct link_params *params, 962 u8 *sp_pri_to_cos, const u8 pri, 963 const u8 cos_entry) 964 { 965 struct bnx2x *bp = params->bp; 966 const u8 port = params->port; 967 const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 : 968 DCBX_E3B0_MAX_NUM_COS_PORT0; 969 970 if (pri >= max_num_of_cos) { 971 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid " 972 "parameter Illegal strict priority\n"); 973 return -EINVAL; 974 } 975 976 if (sp_pri_to_cos[pri] != DCBX_INVALID_COS) { 977 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid " 978 "parameter There can't be two COS's with " 979 "the same strict pri\n"); 980 return -EINVAL; 981 } 982 983 sp_pri_to_cos[pri] = cos_entry; 984 return 0; 985 986 } 987 988 /****************************************************************************** 989 * Description: 990 * Returns the correct value according to COS and priority in 991 * the sp_pri_cli register. 992 * 993 ******************************************************************************/ 994 static u64 bnx2x_e3b0_sp_get_pri_cli_reg(const u8 cos, const u8 cos_offset, 995 const u8 pri_set, 996 const u8 pri_offset, 997 const u8 entry_size) 998 { 999 u64 pri_cli_nig = 0; 1000 pri_cli_nig = ((u64)(cos + cos_offset)) << (entry_size * 1001 (pri_set + pri_offset)); 1002 1003 return pri_cli_nig; 1004 } 1005 /****************************************************************************** 1006 * Description: 1007 * Returns the correct value according to COS and priority in the 1008 * sp_pri_cli register for NIG. 1009 * 1010 ******************************************************************************/ 1011 static u64 bnx2x_e3b0_sp_get_pri_cli_reg_nig(const u8 cos, const u8 pri_set) 1012 { 1013 /* MCP Dbg0 and dbg1 are always with higher strict pri*/ 1014 const u8 nig_cos_offset = 3; 1015 const u8 nig_pri_offset = 3; 1016 1017 return bnx2x_e3b0_sp_get_pri_cli_reg(cos, nig_cos_offset, pri_set, 1018 nig_pri_offset, 4); 1019 1020 } 1021 /****************************************************************************** 1022 * Description: 1023 * Returns the correct value according to COS and priority in the 1024 * sp_pri_cli register for PBF. 1025 * 1026 ******************************************************************************/ 1027 static u64 bnx2x_e3b0_sp_get_pri_cli_reg_pbf(const u8 cos, const u8 pri_set) 1028 { 1029 const u8 pbf_cos_offset = 0; 1030 const u8 pbf_pri_offset = 0; 1031 1032 return bnx2x_e3b0_sp_get_pri_cli_reg(cos, pbf_cos_offset, pri_set, 1033 pbf_pri_offset, 3); 1034 1035 } 1036 1037 /****************************************************************************** 1038 * Description: 1039 * Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers 1040 * according to sp_pri_to_cos.(which COS has higher priority) 1041 * 1042 ******************************************************************************/ 1043 static int bnx2x_ets_e3b0_sp_set_pri_cli_reg(const struct link_params *params, 1044 u8 *sp_pri_to_cos) 1045 { 1046 struct bnx2x *bp = params->bp; 1047 u8 i = 0; 1048 const u8 port = params->port; 1049 /* MCP Dbg0 and dbg1 are always with higher strict pri*/ 1050 u64 pri_cli_nig = 0x210; 1051 u32 pri_cli_pbf = 0x0; 1052 u8 pri_set = 0; 1053 u8 pri_bitmask = 0; 1054 const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 : 1055 DCBX_E3B0_MAX_NUM_COS_PORT0; 1056 1057 u8 cos_bit_to_set = (1 << max_num_of_cos) - 1; 1058 1059 /* Set all the strict priority first */ 1060 for (i = 0; i < max_num_of_cos; i++) { 1061 if (sp_pri_to_cos[i] != DCBX_INVALID_COS) { 1062 if (sp_pri_to_cos[i] >= DCBX_MAX_NUM_COS) { 1063 DP(NETIF_MSG_LINK, 1064 "bnx2x_ets_e3b0_sp_set_pri_cli_reg " 1065 "invalid cos entry\n"); 1066 return -EINVAL; 1067 } 1068 1069 pri_cli_nig |= bnx2x_e3b0_sp_get_pri_cli_reg_nig( 1070 sp_pri_to_cos[i], pri_set); 1071 1072 pri_cli_pbf |= bnx2x_e3b0_sp_get_pri_cli_reg_pbf( 1073 sp_pri_to_cos[i], pri_set); 1074 pri_bitmask = 1 << sp_pri_to_cos[i]; 1075 /* COS is used remove it from bitmap.*/ 1076 if (!(pri_bitmask & cos_bit_to_set)) { 1077 DP(NETIF_MSG_LINK, 1078 "bnx2x_ets_e3b0_sp_set_pri_cli_reg " 1079 "invalid There can't be two COS's with" 1080 " the same strict pri\n"); 1081 return -EINVAL; 1082 } 1083 cos_bit_to_set &= ~pri_bitmask; 1084 pri_set++; 1085 } 1086 } 1087 1088 /* Set all the Non strict priority i= COS*/ 1089 for (i = 0; i < max_num_of_cos; i++) { 1090 pri_bitmask = 1 << i; 1091 /* Check if COS was already used for SP */ 1092 if (pri_bitmask & cos_bit_to_set) { 1093 /* COS wasn't used for SP */ 1094 pri_cli_nig |= bnx2x_e3b0_sp_get_pri_cli_reg_nig( 1095 i, pri_set); 1096 1097 pri_cli_pbf |= bnx2x_e3b0_sp_get_pri_cli_reg_pbf( 1098 i, pri_set); 1099 /* COS is used remove it from bitmap.*/ 1100 cos_bit_to_set &= ~pri_bitmask; 1101 pri_set++; 1102 } 1103 } 1104 1105 if (pri_set != max_num_of_cos) { 1106 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_set_pri_cli_reg not all " 1107 "entries were set\n"); 1108 return -EINVAL; 1109 } 1110 1111 if (port) { 1112 /* Only 6 usable clients*/ 1113 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, 1114 (u32)pri_cli_nig); 1115 1116 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , pri_cli_pbf); 1117 } else { 1118 /* Only 9 usable clients*/ 1119 const u32 pri_cli_nig_lsb = (u32) (pri_cli_nig); 1120 const u32 pri_cli_nig_msb = (u32) ((pri_cli_nig >> 32) & 0xF); 1121 1122 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, 1123 pri_cli_nig_lsb); 1124 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, 1125 pri_cli_nig_msb); 1126 1127 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , pri_cli_pbf); 1128 } 1129 return 0; 1130 } 1131 1132 /****************************************************************************** 1133 * Description: 1134 * Configure the COS to ETS according to BW and SP settings. 1135 ******************************************************************************/ 1136 int bnx2x_ets_e3b0_config(const struct link_params *params, 1137 const struct link_vars *vars, 1138 struct bnx2x_ets_params *ets_params) 1139 { 1140 struct bnx2x *bp = params->bp; 1141 int bnx2x_status = 0; 1142 const u8 port = params->port; 1143 u16 total_bw = 0; 1144 const u32 min_w_val_nig = bnx2x_ets_get_min_w_val_nig(vars); 1145 const u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL; 1146 u8 cos_bw_bitmap = 0; 1147 u8 cos_sp_bitmap = 0; 1148 u8 sp_pri_to_cos[DCBX_MAX_NUM_COS] = {0}; 1149 const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 : 1150 DCBX_E3B0_MAX_NUM_COS_PORT0; 1151 u8 cos_entry = 0; 1152 1153 if (!CHIP_IS_E3B0(bp)) { 1154 DP(NETIF_MSG_LINK, 1155 "bnx2x_ets_e3b0_disabled the chip isn't E3B0\n"); 1156 return -EINVAL; 1157 } 1158 1159 if ((ets_params->num_of_cos > max_num_of_cos)) { 1160 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config the number of COS " 1161 "isn't supported\n"); 1162 return -EINVAL; 1163 } 1164 1165 /* Prepare sp strict priority parameters*/ 1166 bnx2x_ets_e3b0_sp_pri_to_cos_init(sp_pri_to_cos); 1167 1168 /* Prepare BW parameters*/ 1169 bnx2x_status = bnx2x_ets_e3b0_get_total_bw(params, ets_params, 1170 &total_bw); 1171 if (bnx2x_status) { 1172 DP(NETIF_MSG_LINK, 1173 "bnx2x_ets_E3B0_config get_total_bw failed\n"); 1174 return -EINVAL; 1175 } 1176 1177 /* Upper bound is set according to current link speed (min_w_val 1178 * should be the same for upper bound and COS credit val). 1179 */ 1180 bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val_nig); 1181 bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf); 1182 1183 1184 for (cos_entry = 0; cos_entry < ets_params->num_of_cos; cos_entry++) { 1185 if (bnx2x_cos_state_bw == ets_params->cos[cos_entry].state) { 1186 cos_bw_bitmap |= (1 << cos_entry); 1187 /* The function also sets the BW in HW(not the mappin 1188 * yet) 1189 */ 1190 bnx2x_status = bnx2x_ets_e3b0_set_cos_bw( 1191 bp, cos_entry, min_w_val_nig, min_w_val_pbf, 1192 total_bw, 1193 ets_params->cos[cos_entry].params.bw_params.bw, 1194 port); 1195 } else if (bnx2x_cos_state_strict == 1196 ets_params->cos[cos_entry].state){ 1197 cos_sp_bitmap |= (1 << cos_entry); 1198 1199 bnx2x_status = bnx2x_ets_e3b0_sp_pri_to_cos_set( 1200 params, 1201 sp_pri_to_cos, 1202 ets_params->cos[cos_entry].params.sp_params.pri, 1203 cos_entry); 1204 1205 } else { 1206 DP(NETIF_MSG_LINK, 1207 "bnx2x_ets_e3b0_config cos state not valid\n"); 1208 return -EINVAL; 1209 } 1210 if (bnx2x_status) { 1211 DP(NETIF_MSG_LINK, 1212 "bnx2x_ets_e3b0_config set cos bw failed\n"); 1213 return bnx2x_status; 1214 } 1215 } 1216 1217 /* Set SP register (which COS has higher priority) */ 1218 bnx2x_status = bnx2x_ets_e3b0_sp_set_pri_cli_reg(params, 1219 sp_pri_to_cos); 1220 1221 if (bnx2x_status) { 1222 DP(NETIF_MSG_LINK, 1223 "bnx2x_ets_E3B0_config set_pri_cli_reg failed\n"); 1224 return bnx2x_status; 1225 } 1226 1227 /* Set client mapping of BW and strict */ 1228 bnx2x_status = bnx2x_ets_e3b0_cli_map(params, ets_params, 1229 cos_sp_bitmap, 1230 cos_bw_bitmap); 1231 1232 if (bnx2x_status) { 1233 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config SP failed\n"); 1234 return bnx2x_status; 1235 } 1236 return 0; 1237 } 1238 static void bnx2x_ets_bw_limit_common(const struct link_params *params) 1239 { 1240 /* ETS disabled configuration */ 1241 struct bnx2x *bp = params->bp; 1242 DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n"); 1243 /* Defines which entries (clients) are subjected to WFQ arbitration 1244 * COS0 0x8 1245 * COS1 0x10 1246 */ 1247 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0x18); 1248 /* Mapping between the ARB_CREDIT_WEIGHT registers and actual 1249 * client numbers (WEIGHT_0 does not actually have to represent 1250 * client 0) 1251 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0 1252 * cos1-001 cos0-000 dbg1-100 dbg0-011 MCP-010 1253 */ 1254 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0x111A); 1255 1256 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 1257 ETS_BW_LIMIT_CREDIT_UPPER_BOUND); 1258 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 1259 ETS_BW_LIMIT_CREDIT_UPPER_BOUND); 1260 1261 /* ETS mode enabled*/ 1262 REG_WR(bp, PBF_REG_ETS_ENABLED, 1); 1263 1264 /* Defines the number of consecutive slots for the strict priority */ 1265 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0); 1266 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves 1267 * as strict. Bits 0,1,2 - debug and management entries, 3 - COS0 1268 * entry, 4 - COS1 entry. 1269 * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT 1270 * bit4 bit3 bit2 bit1 bit0 1271 * MCP and debug are strict 1272 */ 1273 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7); 1274 1275 /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter.*/ 1276 REG_WR(bp, PBF_REG_COS0_UPPER_BOUND, 1277 ETS_BW_LIMIT_CREDIT_UPPER_BOUND); 1278 REG_WR(bp, PBF_REG_COS1_UPPER_BOUND, 1279 ETS_BW_LIMIT_CREDIT_UPPER_BOUND); 1280 } 1281 1282 void bnx2x_ets_bw_limit(const struct link_params *params, const u32 cos0_bw, 1283 const u32 cos1_bw) 1284 { 1285 /* ETS disabled configuration*/ 1286 struct bnx2x *bp = params->bp; 1287 const u32 total_bw = cos0_bw + cos1_bw; 1288 u32 cos0_credit_weight = 0; 1289 u32 cos1_credit_weight = 0; 1290 1291 DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n"); 1292 1293 if ((!total_bw) || 1294 (!cos0_bw) || 1295 (!cos1_bw)) { 1296 DP(NETIF_MSG_LINK, "Total BW can't be zero\n"); 1297 return; 1298 } 1299 1300 cos0_credit_weight = (cos0_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/ 1301 total_bw; 1302 cos1_credit_weight = (cos1_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/ 1303 total_bw; 1304 1305 bnx2x_ets_bw_limit_common(params); 1306 1307 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, cos0_credit_weight); 1308 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, cos1_credit_weight); 1309 1310 REG_WR(bp, PBF_REG_COS0_WEIGHT, cos0_credit_weight); 1311 REG_WR(bp, PBF_REG_COS1_WEIGHT, cos1_credit_weight); 1312 } 1313 1314 int bnx2x_ets_strict(const struct link_params *params, const u8 strict_cos) 1315 { 1316 /* ETS disabled configuration*/ 1317 struct bnx2x *bp = params->bp; 1318 u32 val = 0; 1319 1320 DP(NETIF_MSG_LINK, "ETS enabled strict configuration\n"); 1321 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves 1322 * as strict. Bits 0,1,2 - debug and management entries, 1323 * 3 - COS0 entry, 4 - COS1 entry. 1324 * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT 1325 * bit4 bit3 bit2 bit1 bit0 1326 * MCP and debug are strict 1327 */ 1328 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1F); 1329 /* For strict priority entries defines the number of consecutive slots 1330 * for the highest priority. 1331 */ 1332 REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100); 1333 /* ETS mode disable */ 1334 REG_WR(bp, PBF_REG_ETS_ENABLED, 0); 1335 /* Defines the number of consecutive slots for the strict priority */ 1336 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0x100); 1337 1338 /* Defines the number of consecutive slots for the strict priority */ 1339 REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, strict_cos); 1340 1341 /* Mapping between entry priority to client number (0,1,2 -debug and 1342 * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST) 1343 * 3bits client num. 1344 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0 1345 * dbg0-010 dbg1-001 cos1-100 cos0-011 MCP-000 1346 * dbg0-010 dbg1-001 cos0-011 cos1-100 MCP-000 1347 */ 1348 val = (!strict_cos) ? 0x2318 : 0x22E0; 1349 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, val); 1350 1351 return 0; 1352 } 1353 1354 /******************************************************************/ 1355 /* PFC section */ 1356 /******************************************************************/ 1357 static void bnx2x_update_pfc_xmac(struct link_params *params, 1358 struct link_vars *vars, 1359 u8 is_lb) 1360 { 1361 struct bnx2x *bp = params->bp; 1362 u32 xmac_base; 1363 u32 pause_val, pfc0_val, pfc1_val; 1364 1365 /* XMAC base adrr */ 1366 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; 1367 1368 /* Initialize pause and pfc registers */ 1369 pause_val = 0x18000; 1370 pfc0_val = 0xFFFF8000; 1371 pfc1_val = 0x2; 1372 1373 /* No PFC support */ 1374 if (!(params->feature_config_flags & 1375 FEATURE_CONFIG_PFC_ENABLED)) { 1376 1377 /* RX flow control - Process pause frame in receive direction 1378 */ 1379 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX) 1380 pause_val |= XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN; 1381 1382 /* TX flow control - Send pause packet when buffer is full */ 1383 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) 1384 pause_val |= XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN; 1385 } else {/* PFC support */ 1386 pfc1_val |= XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN | 1387 XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN | 1388 XMAC_PFC_CTRL_HI_REG_RX_PFC_EN | 1389 XMAC_PFC_CTRL_HI_REG_TX_PFC_EN | 1390 XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON; 1391 /* Write pause and PFC registers */ 1392 REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val); 1393 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val); 1394 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val); 1395 pfc1_val &= ~XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON; 1396 1397 } 1398 1399 /* Write pause and PFC registers */ 1400 REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val); 1401 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val); 1402 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val); 1403 1404 1405 /* Set MAC address for source TX Pause/PFC frames */ 1406 REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_LO, 1407 ((params->mac_addr[2] << 24) | 1408 (params->mac_addr[3] << 16) | 1409 (params->mac_addr[4] << 8) | 1410 (params->mac_addr[5]))); 1411 REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_HI, 1412 ((params->mac_addr[0] << 8) | 1413 (params->mac_addr[1]))); 1414 1415 udelay(30); 1416 } 1417 1418 /******************************************************************/ 1419 /* MAC/PBF section */ 1420 /******************************************************************/ 1421 static void bnx2x_set_mdio_clk(struct bnx2x *bp, u32 chip_id, 1422 u32 emac_base) 1423 { 1424 u32 new_mode, cur_mode; 1425 u32 clc_cnt; 1426 /* Set clause 45 mode, slow down the MDIO clock to 2.5MHz 1427 * (a value of 49==0x31) and make sure that the AUTO poll is off 1428 */ 1429 cur_mode = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE); 1430 1431 if (USES_WARPCORE(bp)) 1432 clc_cnt = 74L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT; 1433 else 1434 clc_cnt = 49L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT; 1435 1436 if (((cur_mode & EMAC_MDIO_MODE_CLOCK_CNT) == clc_cnt) && 1437 (cur_mode & (EMAC_MDIO_MODE_CLAUSE_45))) 1438 return; 1439 1440 new_mode = cur_mode & 1441 ~(EMAC_MDIO_MODE_AUTO_POLL | EMAC_MDIO_MODE_CLOCK_CNT); 1442 new_mode |= clc_cnt; 1443 new_mode |= (EMAC_MDIO_MODE_CLAUSE_45); 1444 1445 DP(NETIF_MSG_LINK, "Changing emac_mode from 0x%x to 0x%x\n", 1446 cur_mode, new_mode); 1447 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE, new_mode); 1448 udelay(40); 1449 } 1450 1451 static void bnx2x_set_mdio_emac_per_phy(struct bnx2x *bp, 1452 struct link_params *params) 1453 { 1454 u8 phy_index; 1455 /* Set mdio clock per phy */ 1456 for (phy_index = INT_PHY; phy_index < params->num_phys; 1457 phy_index++) 1458 bnx2x_set_mdio_clk(bp, params->chip_id, 1459 params->phy[phy_index].mdio_ctrl); 1460 } 1461 1462 static u8 bnx2x_is_4_port_mode(struct bnx2x *bp) 1463 { 1464 u32 port4mode_ovwr_val; 1465 /* Check 4-port override enabled */ 1466 port4mode_ovwr_val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR); 1467 if (port4mode_ovwr_val & (1<<0)) { 1468 /* Return 4-port mode override value */ 1469 return ((port4mode_ovwr_val & (1<<1)) == (1<<1)); 1470 } 1471 /* Return 4-port mode from input pin */ 1472 return (u8)REG_RD(bp, MISC_REG_PORT4MODE_EN); 1473 } 1474 1475 static void bnx2x_emac_init(struct link_params *params, 1476 struct link_vars *vars) 1477 { 1478 /* reset and unreset the emac core */ 1479 struct bnx2x *bp = params->bp; 1480 u8 port = params->port; 1481 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; 1482 u32 val; 1483 u16 timeout; 1484 1485 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 1486 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port)); 1487 udelay(5); 1488 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 1489 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port)); 1490 1491 /* init emac - use read-modify-write */ 1492 /* self clear reset */ 1493 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE); 1494 EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET)); 1495 1496 timeout = 200; 1497 do { 1498 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE); 1499 DP(NETIF_MSG_LINK, "EMAC reset reg is %u\n", val); 1500 if (!timeout) { 1501 DP(NETIF_MSG_LINK, "EMAC timeout!\n"); 1502 return; 1503 } 1504 timeout--; 1505 } while (val & EMAC_MODE_RESET); 1506 1507 bnx2x_set_mdio_emac_per_phy(bp, params); 1508 /* Set mac address */ 1509 val = ((params->mac_addr[0] << 8) | 1510 params->mac_addr[1]); 1511 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH, val); 1512 1513 val = ((params->mac_addr[2] << 24) | 1514 (params->mac_addr[3] << 16) | 1515 (params->mac_addr[4] << 8) | 1516 params->mac_addr[5]); 1517 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + 4, val); 1518 } 1519 1520 static void bnx2x_set_xumac_nig(struct link_params *params, 1521 u16 tx_pause_en, 1522 u8 enable) 1523 { 1524 struct bnx2x *bp = params->bp; 1525 1526 REG_WR(bp, params->port ? NIG_REG_P1_MAC_IN_EN : NIG_REG_P0_MAC_IN_EN, 1527 enable); 1528 REG_WR(bp, params->port ? NIG_REG_P1_MAC_OUT_EN : NIG_REG_P0_MAC_OUT_EN, 1529 enable); 1530 REG_WR(bp, params->port ? NIG_REG_P1_MAC_PAUSE_OUT_EN : 1531 NIG_REG_P0_MAC_PAUSE_OUT_EN, tx_pause_en); 1532 } 1533 1534 static void bnx2x_set_umac_rxtx(struct link_params *params, u8 en) 1535 { 1536 u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0; 1537 u32 val; 1538 struct bnx2x *bp = params->bp; 1539 if (!(REG_RD(bp, MISC_REG_RESET_REG_2) & 1540 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port))) 1541 return; 1542 val = REG_RD(bp, umac_base + UMAC_REG_COMMAND_CONFIG); 1543 if (en) 1544 val |= (UMAC_COMMAND_CONFIG_REG_TX_ENA | 1545 UMAC_COMMAND_CONFIG_REG_RX_ENA); 1546 else 1547 val &= ~(UMAC_COMMAND_CONFIG_REG_TX_ENA | 1548 UMAC_COMMAND_CONFIG_REG_RX_ENA); 1549 /* Disable RX and TX */ 1550 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val); 1551 } 1552 1553 static void bnx2x_umac_enable(struct link_params *params, 1554 struct link_vars *vars, u8 lb) 1555 { 1556 u32 val; 1557 u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0; 1558 struct bnx2x *bp = params->bp; 1559 /* Reset UMAC */ 1560 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 1561 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port)); 1562 usleep_range(1000, 2000); 1563 1564 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 1565 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port)); 1566 1567 DP(NETIF_MSG_LINK, "enabling UMAC\n"); 1568 1569 /* This register opens the gate for the UMAC despite its name */ 1570 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1); 1571 1572 val = UMAC_COMMAND_CONFIG_REG_PROMIS_EN | 1573 UMAC_COMMAND_CONFIG_REG_PAD_EN | 1574 UMAC_COMMAND_CONFIG_REG_SW_RESET | 1575 UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK; 1576 switch (vars->line_speed) { 1577 case SPEED_10: 1578 val |= (0<<2); 1579 break; 1580 case SPEED_100: 1581 val |= (1<<2); 1582 break; 1583 case SPEED_1000: 1584 val |= (2<<2); 1585 break; 1586 case SPEED_2500: 1587 val |= (3<<2); 1588 break; 1589 default: 1590 DP(NETIF_MSG_LINK, "Invalid speed for UMAC %d\n", 1591 vars->line_speed); 1592 break; 1593 } 1594 if (!(vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)) 1595 val |= UMAC_COMMAND_CONFIG_REG_IGNORE_TX_PAUSE; 1596 1597 if (!(vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)) 1598 val |= UMAC_COMMAND_CONFIG_REG_PAUSE_IGNORE; 1599 1600 if (vars->duplex == DUPLEX_HALF) 1601 val |= UMAC_COMMAND_CONFIG_REG_HD_ENA; 1602 1603 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val); 1604 udelay(50); 1605 1606 /* Configure UMAC for EEE */ 1607 if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) { 1608 DP(NETIF_MSG_LINK, "configured UMAC for EEE\n"); 1609 REG_WR(bp, umac_base + UMAC_REG_UMAC_EEE_CTRL, 1610 UMAC_UMAC_EEE_CTRL_REG_EEE_EN); 1611 REG_WR(bp, umac_base + UMAC_REG_EEE_WAKE_TIMER, 0x11); 1612 } else { 1613 REG_WR(bp, umac_base + UMAC_REG_UMAC_EEE_CTRL, 0x0); 1614 } 1615 1616 /* Set MAC address for source TX Pause/PFC frames (under SW reset) */ 1617 REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR0, 1618 ((params->mac_addr[2] << 24) | 1619 (params->mac_addr[3] << 16) | 1620 (params->mac_addr[4] << 8) | 1621 (params->mac_addr[5]))); 1622 REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR1, 1623 ((params->mac_addr[0] << 8) | 1624 (params->mac_addr[1]))); 1625 1626 /* Enable RX and TX */ 1627 val &= ~UMAC_COMMAND_CONFIG_REG_PAD_EN; 1628 val |= UMAC_COMMAND_CONFIG_REG_TX_ENA | 1629 UMAC_COMMAND_CONFIG_REG_RX_ENA; 1630 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val); 1631 udelay(50); 1632 1633 /* Remove SW Reset */ 1634 val &= ~UMAC_COMMAND_CONFIG_REG_SW_RESET; 1635 1636 /* Check loopback mode */ 1637 if (lb) 1638 val |= UMAC_COMMAND_CONFIG_REG_LOOP_ENA; 1639 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val); 1640 1641 /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame 1642 * length used by the MAC receive logic to check frames. 1643 */ 1644 REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710); 1645 bnx2x_set_xumac_nig(params, 1646 ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1); 1647 vars->mac_type = MAC_TYPE_UMAC; 1648 1649 } 1650 1651 /* Define the XMAC mode */ 1652 static void bnx2x_xmac_init(struct link_params *params, u32 max_speed) 1653 { 1654 struct bnx2x *bp = params->bp; 1655 u32 is_port4mode = bnx2x_is_4_port_mode(bp); 1656 1657 /* In 4-port mode, need to set the mode only once, so if XMAC is 1658 * already out of reset, it means the mode has already been set, 1659 * and it must not* reset the XMAC again, since it controls both 1660 * ports of the path 1661 */ 1662 1663 if (((CHIP_NUM(bp) == CHIP_NUM_57840_4_10) || 1664 (CHIP_NUM(bp) == CHIP_NUM_57840_2_20) || 1665 (CHIP_NUM(bp) == CHIP_NUM_57840_OBSOLETE)) && 1666 is_port4mode && 1667 (REG_RD(bp, MISC_REG_RESET_REG_2) & 1668 MISC_REGISTERS_RESET_REG_2_XMAC)) { 1669 DP(NETIF_MSG_LINK, 1670 "XMAC already out of reset in 4-port mode\n"); 1671 return; 1672 } 1673 1674 /* Hard reset */ 1675 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 1676 MISC_REGISTERS_RESET_REG_2_XMAC); 1677 usleep_range(1000, 2000); 1678 1679 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 1680 MISC_REGISTERS_RESET_REG_2_XMAC); 1681 if (is_port4mode) { 1682 DP(NETIF_MSG_LINK, "Init XMAC to 2 ports x 10G per path\n"); 1683 1684 /* Set the number of ports on the system side to up to 2 */ 1685 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 1); 1686 1687 /* Set the number of ports on the Warp Core to 10G */ 1688 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3); 1689 } else { 1690 /* Set the number of ports on the system side to 1 */ 1691 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 0); 1692 if (max_speed == SPEED_10000) { 1693 DP(NETIF_MSG_LINK, 1694 "Init XMAC to 10G x 1 port per path\n"); 1695 /* Set the number of ports on the Warp Core to 10G */ 1696 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3); 1697 } else { 1698 DP(NETIF_MSG_LINK, 1699 "Init XMAC to 20G x 2 ports per path\n"); 1700 /* Set the number of ports on the Warp Core to 20G */ 1701 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 1); 1702 } 1703 } 1704 /* Soft reset */ 1705 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 1706 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT); 1707 usleep_range(1000, 2000); 1708 1709 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 1710 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT); 1711 1712 } 1713 1714 static void bnx2x_set_xmac_rxtx(struct link_params *params, u8 en) 1715 { 1716 u8 port = params->port; 1717 struct bnx2x *bp = params->bp; 1718 u32 pfc_ctrl, xmac_base = (port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; 1719 u32 val; 1720 1721 if (REG_RD(bp, MISC_REG_RESET_REG_2) & 1722 MISC_REGISTERS_RESET_REG_2_XMAC) { 1723 /* Send an indication to change the state in the NIG back to XON 1724 * Clearing this bit enables the next set of this bit to get 1725 * rising edge 1726 */ 1727 pfc_ctrl = REG_RD(bp, xmac_base + XMAC_REG_PFC_CTRL_HI); 1728 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, 1729 (pfc_ctrl & ~(1<<1))); 1730 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, 1731 (pfc_ctrl | (1<<1))); 1732 DP(NETIF_MSG_LINK, "Disable XMAC on port %x\n", port); 1733 val = REG_RD(bp, xmac_base + XMAC_REG_CTRL); 1734 if (en) 1735 val |= (XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN); 1736 else 1737 val &= ~(XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN); 1738 REG_WR(bp, xmac_base + XMAC_REG_CTRL, val); 1739 } 1740 } 1741 1742 static int bnx2x_xmac_enable(struct link_params *params, 1743 struct link_vars *vars, u8 lb) 1744 { 1745 u32 val, xmac_base; 1746 struct bnx2x *bp = params->bp; 1747 DP(NETIF_MSG_LINK, "enabling XMAC\n"); 1748 1749 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; 1750 1751 bnx2x_xmac_init(params, vars->line_speed); 1752 1753 /* This register determines on which events the MAC will assert 1754 * error on the i/f to the NIG along w/ EOP. 1755 */ 1756 1757 /* This register tells the NIG whether to send traffic to UMAC 1758 * or XMAC 1759 */ 1760 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 0); 1761 1762 /* When XMAC is in XLGMII mode, disable sending idles for fault 1763 * detection. 1764 */ 1765 if (!(params->phy[INT_PHY].flags & FLAGS_TX_ERROR_CHECK)) { 1766 REG_WR(bp, xmac_base + XMAC_REG_RX_LSS_CTRL, 1767 (XMAC_RX_LSS_CTRL_REG_LOCAL_FAULT_DISABLE | 1768 XMAC_RX_LSS_CTRL_REG_REMOTE_FAULT_DISABLE)); 1769 REG_WR(bp, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0); 1770 REG_WR(bp, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 1771 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS | 1772 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS); 1773 } 1774 /* Set Max packet size */ 1775 REG_WR(bp, xmac_base + XMAC_REG_RX_MAX_SIZE, 0x2710); 1776 1777 /* CRC append for Tx packets */ 1778 REG_WR(bp, xmac_base + XMAC_REG_TX_CTRL, 0xC800); 1779 1780 /* update PFC */ 1781 bnx2x_update_pfc_xmac(params, vars, 0); 1782 1783 if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) { 1784 DP(NETIF_MSG_LINK, "Setting XMAC for EEE\n"); 1785 REG_WR(bp, xmac_base + XMAC_REG_EEE_TIMERS_HI, 0x1380008); 1786 REG_WR(bp, xmac_base + XMAC_REG_EEE_CTRL, 0x1); 1787 } else { 1788 REG_WR(bp, xmac_base + XMAC_REG_EEE_CTRL, 0x0); 1789 } 1790 1791 /* Enable TX and RX */ 1792 val = XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN; 1793 1794 /* Set MAC in XLGMII mode for dual-mode */ 1795 if ((vars->line_speed == SPEED_20000) && 1796 (params->phy[INT_PHY].supported & 1797 SUPPORTED_20000baseKR2_Full)) 1798 val |= XMAC_CTRL_REG_XLGMII_ALIGN_ENB; 1799 1800 /* Check loopback mode */ 1801 if (lb) 1802 val |= XMAC_CTRL_REG_LINE_LOCAL_LPBK; 1803 REG_WR(bp, xmac_base + XMAC_REG_CTRL, val); 1804 bnx2x_set_xumac_nig(params, 1805 ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1); 1806 1807 vars->mac_type = MAC_TYPE_XMAC; 1808 1809 return 0; 1810 } 1811 1812 static int bnx2x_emac_enable(struct link_params *params, 1813 struct link_vars *vars, u8 lb) 1814 { 1815 struct bnx2x *bp = params->bp; 1816 u8 port = params->port; 1817 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; 1818 u32 val; 1819 1820 DP(NETIF_MSG_LINK, "enabling EMAC\n"); 1821 1822 /* Disable BMAC */ 1823 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 1824 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); 1825 1826 /* enable emac and not bmac */ 1827 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 1); 1828 1829 /* ASIC */ 1830 if (vars->phy_flags & PHY_XGXS_FLAG) { 1831 u32 ser_lane = ((params->lane_config & 1832 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >> 1833 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT); 1834 1835 DP(NETIF_MSG_LINK, "XGXS\n"); 1836 /* select the master lanes (out of 0-3) */ 1837 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, ser_lane); 1838 /* select XGXS */ 1839 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1); 1840 1841 } else { /* SerDes */ 1842 DP(NETIF_MSG_LINK, "SerDes\n"); 1843 /* select SerDes */ 1844 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0); 1845 } 1846 1847 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_RX_MODE, 1848 EMAC_RX_MODE_RESET); 1849 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE, 1850 EMAC_TX_MODE_RESET); 1851 1852 /* pause enable/disable */ 1853 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_RX_MODE, 1854 EMAC_RX_MODE_FLOW_EN); 1855 1856 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_TX_MODE, 1857 (EMAC_TX_MODE_EXT_PAUSE_EN | 1858 EMAC_TX_MODE_FLOW_EN)); 1859 if (!(params->feature_config_flags & 1860 FEATURE_CONFIG_PFC_ENABLED)) { 1861 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX) 1862 bnx2x_bits_en(bp, emac_base + 1863 EMAC_REG_EMAC_RX_MODE, 1864 EMAC_RX_MODE_FLOW_EN); 1865 1866 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) 1867 bnx2x_bits_en(bp, emac_base + 1868 EMAC_REG_EMAC_TX_MODE, 1869 (EMAC_TX_MODE_EXT_PAUSE_EN | 1870 EMAC_TX_MODE_FLOW_EN)); 1871 } else 1872 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE, 1873 EMAC_TX_MODE_FLOW_EN); 1874 1875 /* KEEP_VLAN_TAG, promiscuous */ 1876 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE); 1877 val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS; 1878 1879 /* Setting this bit causes MAC control frames (except for pause 1880 * frames) to be passed on for processing. This setting has no 1881 * affect on the operation of the pause frames. This bit effects 1882 * all packets regardless of RX Parser packet sorting logic. 1883 * Turn the PFC off to make sure we are in Xon state before 1884 * enabling it. 1885 */ 1886 EMAC_WR(bp, EMAC_REG_RX_PFC_MODE, 0); 1887 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) { 1888 DP(NETIF_MSG_LINK, "PFC is enabled\n"); 1889 /* Enable PFC again */ 1890 EMAC_WR(bp, EMAC_REG_RX_PFC_MODE, 1891 EMAC_REG_RX_PFC_MODE_RX_EN | 1892 EMAC_REG_RX_PFC_MODE_TX_EN | 1893 EMAC_REG_RX_PFC_MODE_PRIORITIES); 1894 1895 EMAC_WR(bp, EMAC_REG_RX_PFC_PARAM, 1896 ((0x0101 << 1897 EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT) | 1898 (0x00ff << 1899 EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT))); 1900 val |= EMAC_RX_MODE_KEEP_MAC_CONTROL; 1901 } 1902 EMAC_WR(bp, EMAC_REG_EMAC_RX_MODE, val); 1903 1904 /* Set Loopback */ 1905 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE); 1906 if (lb) 1907 val |= 0x810; 1908 else 1909 val &= ~0x810; 1910 EMAC_WR(bp, EMAC_REG_EMAC_MODE, val); 1911 1912 /* Enable emac */ 1913 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 1); 1914 1915 /* Enable emac for jumbo packets */ 1916 EMAC_WR(bp, EMAC_REG_EMAC_RX_MTU_SIZE, 1917 (EMAC_RX_MTU_SIZE_JUMBO_ENA | 1918 (ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD))); 1919 1920 /* Strip CRC */ 1921 REG_WR(bp, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1); 1922 1923 /* Disable the NIG in/out to the bmac */ 1924 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x0); 1925 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0); 1926 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x0); 1927 1928 /* Enable the NIG in/out to the emac */ 1929 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x1); 1930 val = 0; 1931 if ((params->feature_config_flags & 1932 FEATURE_CONFIG_PFC_ENABLED) || 1933 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)) 1934 val = 1; 1935 1936 REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val); 1937 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1); 1938 1939 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x0); 1940 1941 vars->mac_type = MAC_TYPE_EMAC; 1942 return 0; 1943 } 1944 1945 static void bnx2x_update_pfc_bmac1(struct link_params *params, 1946 struct link_vars *vars) 1947 { 1948 u32 wb_data[2]; 1949 struct bnx2x *bp = params->bp; 1950 u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM : 1951 NIG_REG_INGRESS_BMAC0_MEM; 1952 1953 u32 val = 0x14; 1954 if ((!(params->feature_config_flags & 1955 FEATURE_CONFIG_PFC_ENABLED)) && 1956 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)) 1957 /* Enable BigMAC to react on received Pause packets */ 1958 val |= (1<<5); 1959 wb_data[0] = val; 1960 wb_data[1] = 0; 1961 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_CONTROL, wb_data, 2); 1962 1963 /* TX control */ 1964 val = 0xc0; 1965 if (!(params->feature_config_flags & 1966 FEATURE_CONFIG_PFC_ENABLED) && 1967 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)) 1968 val |= 0x800000; 1969 wb_data[0] = val; 1970 wb_data[1] = 0; 1971 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_CONTROL, wb_data, 2); 1972 } 1973 1974 static void bnx2x_update_pfc_bmac2(struct link_params *params, 1975 struct link_vars *vars, 1976 u8 is_lb) 1977 { 1978 /* Set rx control: Strip CRC and enable BigMAC to relay 1979 * control packets to the system as well 1980 */ 1981 u32 wb_data[2]; 1982 struct bnx2x *bp = params->bp; 1983 u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM : 1984 NIG_REG_INGRESS_BMAC0_MEM; 1985 u32 val = 0x14; 1986 1987 if ((!(params->feature_config_flags & 1988 FEATURE_CONFIG_PFC_ENABLED)) && 1989 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)) 1990 /* Enable BigMAC to react on received Pause packets */ 1991 val |= (1<<5); 1992 wb_data[0] = val; 1993 wb_data[1] = 0; 1994 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_CONTROL, wb_data, 2); 1995 udelay(30); 1996 1997 /* Tx control */ 1998 val = 0xc0; 1999 if (!(params->feature_config_flags & 2000 FEATURE_CONFIG_PFC_ENABLED) && 2001 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)) 2002 val |= 0x800000; 2003 wb_data[0] = val; 2004 wb_data[1] = 0; 2005 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_CONTROL, wb_data, 2); 2006 2007 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) { 2008 DP(NETIF_MSG_LINK, "PFC is enabled\n"); 2009 /* Enable PFC RX & TX & STATS and set 8 COS */ 2010 wb_data[0] = 0x0; 2011 wb_data[0] |= (1<<0); /* RX */ 2012 wb_data[0] |= (1<<1); /* TX */ 2013 wb_data[0] |= (1<<2); /* Force initial Xon */ 2014 wb_data[0] |= (1<<3); /* 8 cos */ 2015 wb_data[0] |= (1<<5); /* STATS */ 2016 wb_data[1] = 0; 2017 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, 2018 wb_data, 2); 2019 /* Clear the force Xon */ 2020 wb_data[0] &= ~(1<<2); 2021 } else { 2022 DP(NETIF_MSG_LINK, "PFC is disabled\n"); 2023 /* Disable PFC RX & TX & STATS and set 8 COS */ 2024 wb_data[0] = 0x8; 2025 wb_data[1] = 0; 2026 } 2027 2028 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, wb_data, 2); 2029 2030 /* Set Time (based unit is 512 bit time) between automatic 2031 * re-sending of PP packets amd enable automatic re-send of 2032 * Per-Priroity Packet as long as pp_gen is asserted and 2033 * pp_disable is low. 2034 */ 2035 val = 0x8000; 2036 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) 2037 val |= (1<<16); /* enable automatic re-send */ 2038 2039 wb_data[0] = val; 2040 wb_data[1] = 0; 2041 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_PAUSE_CONTROL, 2042 wb_data, 2); 2043 2044 /* mac control */ 2045 val = 0x3; /* Enable RX and TX */ 2046 if (is_lb) { 2047 val |= 0x4; /* Local loopback */ 2048 DP(NETIF_MSG_LINK, "enable bmac loopback\n"); 2049 } 2050 /* When PFC enabled, Pass pause frames towards the NIG. */ 2051 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) 2052 val |= ((1<<6)|(1<<5)); 2053 2054 wb_data[0] = val; 2055 wb_data[1] = 0; 2056 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2); 2057 } 2058 2059 /****************************************************************************** 2060 * Description: 2061 * This function is needed because NIG ARB_CREDIT_WEIGHT_X are 2062 * not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable. 2063 ******************************************************************************/ 2064 static int bnx2x_pfc_nig_rx_priority_mask(struct bnx2x *bp, 2065 u8 cos_entry, 2066 u32 priority_mask, u8 port) 2067 { 2068 u32 nig_reg_rx_priority_mask_add = 0; 2069 2070 switch (cos_entry) { 2071 case 0: 2072 nig_reg_rx_priority_mask_add = (port) ? 2073 NIG_REG_P1_RX_COS0_PRIORITY_MASK : 2074 NIG_REG_P0_RX_COS0_PRIORITY_MASK; 2075 break; 2076 case 1: 2077 nig_reg_rx_priority_mask_add = (port) ? 2078 NIG_REG_P1_RX_COS1_PRIORITY_MASK : 2079 NIG_REG_P0_RX_COS1_PRIORITY_MASK; 2080 break; 2081 case 2: 2082 nig_reg_rx_priority_mask_add = (port) ? 2083 NIG_REG_P1_RX_COS2_PRIORITY_MASK : 2084 NIG_REG_P0_RX_COS2_PRIORITY_MASK; 2085 break; 2086 case 3: 2087 if (port) 2088 return -EINVAL; 2089 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS3_PRIORITY_MASK; 2090 break; 2091 case 4: 2092 if (port) 2093 return -EINVAL; 2094 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS4_PRIORITY_MASK; 2095 break; 2096 case 5: 2097 if (port) 2098 return -EINVAL; 2099 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS5_PRIORITY_MASK; 2100 break; 2101 } 2102 2103 REG_WR(bp, nig_reg_rx_priority_mask_add, priority_mask); 2104 2105 return 0; 2106 } 2107 static void bnx2x_update_mng(struct link_params *params, u32 link_status) 2108 { 2109 struct bnx2x *bp = params->bp; 2110 2111 REG_WR(bp, params->shmem_base + 2112 offsetof(struct shmem_region, 2113 port_mb[params->port].link_status), link_status); 2114 } 2115 2116 static void bnx2x_update_link_attr(struct link_params *params, u32 link_attr) 2117 { 2118 struct bnx2x *bp = params->bp; 2119 2120 if (SHMEM2_HAS(bp, link_attr_sync)) 2121 REG_WR(bp, params->shmem2_base + 2122 offsetof(struct shmem2_region, 2123 link_attr_sync[params->port]), link_attr); 2124 } 2125 2126 static void bnx2x_update_pfc_nig(struct link_params *params, 2127 struct link_vars *vars, 2128 struct bnx2x_nig_brb_pfc_port_params *nig_params) 2129 { 2130 u32 xcm_mask = 0, ppp_enable = 0, pause_enable = 0, llfc_out_en = 0; 2131 u32 llfc_enable = 0, xcm_out_en = 0, hwpfc_enable = 0; 2132 u32 pkt_priority_to_cos = 0; 2133 struct bnx2x *bp = params->bp; 2134 u8 port = params->port; 2135 2136 int set_pfc = params->feature_config_flags & 2137 FEATURE_CONFIG_PFC_ENABLED; 2138 DP(NETIF_MSG_LINK, "updating pfc nig parameters\n"); 2139 2140 /* When NIG_LLH0_XCM_MASK_REG_LLHX_XCM_MASK_BCN bit is set 2141 * MAC control frames (that are not pause packets) 2142 * will be forwarded to the XCM. 2143 */ 2144 xcm_mask = REG_RD(bp, port ? NIG_REG_LLH1_XCM_MASK : 2145 NIG_REG_LLH0_XCM_MASK); 2146 /* NIG params will override non PFC params, since it's possible to 2147 * do transition from PFC to SAFC 2148 */ 2149 if (set_pfc) { 2150 pause_enable = 0; 2151 llfc_out_en = 0; 2152 llfc_enable = 0; 2153 if (CHIP_IS_E3(bp)) 2154 ppp_enable = 0; 2155 else 2156 ppp_enable = 1; 2157 xcm_mask &= ~(port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN : 2158 NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN); 2159 xcm_out_en = 0; 2160 hwpfc_enable = 1; 2161 } else { 2162 if (nig_params) { 2163 llfc_out_en = nig_params->llfc_out_en; 2164 llfc_enable = nig_params->llfc_enable; 2165 pause_enable = nig_params->pause_enable; 2166 } else /* Default non PFC mode - PAUSE */ 2167 pause_enable = 1; 2168 2169 xcm_mask |= (port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN : 2170 NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN); 2171 xcm_out_en = 1; 2172 } 2173 2174 if (CHIP_IS_E3(bp)) 2175 REG_WR(bp, port ? NIG_REG_BRB1_PAUSE_IN_EN : 2176 NIG_REG_BRB0_PAUSE_IN_EN, pause_enable); 2177 REG_WR(bp, port ? NIG_REG_LLFC_OUT_EN_1 : 2178 NIG_REG_LLFC_OUT_EN_0, llfc_out_en); 2179 REG_WR(bp, port ? NIG_REG_LLFC_ENABLE_1 : 2180 NIG_REG_LLFC_ENABLE_0, llfc_enable); 2181 REG_WR(bp, port ? NIG_REG_PAUSE_ENABLE_1 : 2182 NIG_REG_PAUSE_ENABLE_0, pause_enable); 2183 2184 REG_WR(bp, port ? NIG_REG_PPP_ENABLE_1 : 2185 NIG_REG_PPP_ENABLE_0, ppp_enable); 2186 2187 REG_WR(bp, port ? NIG_REG_LLH1_XCM_MASK : 2188 NIG_REG_LLH0_XCM_MASK, xcm_mask); 2189 2190 REG_WR(bp, port ? NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 : 2191 NIG_REG_LLFC_EGRESS_SRC_ENABLE_0, 0x7); 2192 2193 /* Output enable for RX_XCM # IF */ 2194 REG_WR(bp, port ? NIG_REG_XCM1_OUT_EN : 2195 NIG_REG_XCM0_OUT_EN, xcm_out_en); 2196 2197 /* HW PFC TX enable */ 2198 REG_WR(bp, port ? NIG_REG_P1_HWPFC_ENABLE : 2199 NIG_REG_P0_HWPFC_ENABLE, hwpfc_enable); 2200 2201 if (nig_params) { 2202 u8 i = 0; 2203 pkt_priority_to_cos = nig_params->pkt_priority_to_cos; 2204 2205 for (i = 0; i < nig_params->num_of_rx_cos_priority_mask; i++) 2206 bnx2x_pfc_nig_rx_priority_mask(bp, i, 2207 nig_params->rx_cos_priority_mask[i], port); 2208 2209 REG_WR(bp, port ? NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 : 2210 NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0, 2211 nig_params->llfc_high_priority_classes); 2212 2213 REG_WR(bp, port ? NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 : 2214 NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0, 2215 nig_params->llfc_low_priority_classes); 2216 } 2217 REG_WR(bp, port ? NIG_REG_P1_PKT_PRIORITY_TO_COS : 2218 NIG_REG_P0_PKT_PRIORITY_TO_COS, 2219 pkt_priority_to_cos); 2220 } 2221 2222 int bnx2x_update_pfc(struct link_params *params, 2223 struct link_vars *vars, 2224 struct bnx2x_nig_brb_pfc_port_params *pfc_params) 2225 { 2226 /* The PFC and pause are orthogonal to one another, meaning when 2227 * PFC is enabled, the pause are disabled, and when PFC is 2228 * disabled, pause are set according to the pause result. 2229 */ 2230 u32 val; 2231 struct bnx2x *bp = params->bp; 2232 u8 bmac_loopback = (params->loopback_mode == LOOPBACK_BMAC); 2233 2234 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) 2235 vars->link_status |= LINK_STATUS_PFC_ENABLED; 2236 else 2237 vars->link_status &= ~LINK_STATUS_PFC_ENABLED; 2238 2239 bnx2x_update_mng(params, vars->link_status); 2240 2241 /* Update NIG params */ 2242 bnx2x_update_pfc_nig(params, vars, pfc_params); 2243 2244 if (!vars->link_up) 2245 return 0; 2246 2247 DP(NETIF_MSG_LINK, "About to update PFC in BMAC\n"); 2248 2249 if (CHIP_IS_E3(bp)) { 2250 if (vars->mac_type == MAC_TYPE_XMAC) 2251 bnx2x_update_pfc_xmac(params, vars, 0); 2252 } else { 2253 val = REG_RD(bp, MISC_REG_RESET_REG_2); 2254 if ((val & 2255 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port)) 2256 == 0) { 2257 DP(NETIF_MSG_LINK, "About to update PFC in EMAC\n"); 2258 bnx2x_emac_enable(params, vars, 0); 2259 return 0; 2260 } 2261 if (CHIP_IS_E2(bp)) 2262 bnx2x_update_pfc_bmac2(params, vars, bmac_loopback); 2263 else 2264 bnx2x_update_pfc_bmac1(params, vars); 2265 2266 val = 0; 2267 if ((params->feature_config_flags & 2268 FEATURE_CONFIG_PFC_ENABLED) || 2269 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)) 2270 val = 1; 2271 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port*4, val); 2272 } 2273 return 0; 2274 } 2275 2276 static int bnx2x_bmac1_enable(struct link_params *params, 2277 struct link_vars *vars, 2278 u8 is_lb) 2279 { 2280 struct bnx2x *bp = params->bp; 2281 u8 port = params->port; 2282 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM : 2283 NIG_REG_INGRESS_BMAC0_MEM; 2284 u32 wb_data[2]; 2285 u32 val; 2286 2287 DP(NETIF_MSG_LINK, "Enabling BigMAC1\n"); 2288 2289 /* XGXS control */ 2290 wb_data[0] = 0x3c; 2291 wb_data[1] = 0; 2292 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_XGXS_CONTROL, 2293 wb_data, 2); 2294 2295 /* TX MAC SA */ 2296 wb_data[0] = ((params->mac_addr[2] << 24) | 2297 (params->mac_addr[3] << 16) | 2298 (params->mac_addr[4] << 8) | 2299 params->mac_addr[5]); 2300 wb_data[1] = ((params->mac_addr[0] << 8) | 2301 params->mac_addr[1]); 2302 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR, wb_data, 2); 2303 2304 /* MAC control */ 2305 val = 0x3; 2306 if (is_lb) { 2307 val |= 0x4; 2308 DP(NETIF_MSG_LINK, "enable bmac loopback\n"); 2309 } 2310 wb_data[0] = val; 2311 wb_data[1] = 0; 2312 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL, wb_data, 2); 2313 2314 /* Set rx mtu */ 2315 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD; 2316 wb_data[1] = 0; 2317 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE, wb_data, 2); 2318 2319 bnx2x_update_pfc_bmac1(params, vars); 2320 2321 /* Set tx mtu */ 2322 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD; 2323 wb_data[1] = 0; 2324 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE, wb_data, 2); 2325 2326 /* Set cnt max size */ 2327 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD; 2328 wb_data[1] = 0; 2329 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE, wb_data, 2); 2330 2331 /* Configure SAFC */ 2332 wb_data[0] = 0x1000200; 2333 wb_data[1] = 0; 2334 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS, 2335 wb_data, 2); 2336 2337 return 0; 2338 } 2339 2340 static int bnx2x_bmac2_enable(struct link_params *params, 2341 struct link_vars *vars, 2342 u8 is_lb) 2343 { 2344 struct bnx2x *bp = params->bp; 2345 u8 port = params->port; 2346 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM : 2347 NIG_REG_INGRESS_BMAC0_MEM; 2348 u32 wb_data[2]; 2349 2350 DP(NETIF_MSG_LINK, "Enabling BigMAC2\n"); 2351 2352 wb_data[0] = 0; 2353 wb_data[1] = 0; 2354 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2); 2355 udelay(30); 2356 2357 /* XGXS control: Reset phy HW, MDIO registers, PHY PLL and BMAC */ 2358 wb_data[0] = 0x3c; 2359 wb_data[1] = 0; 2360 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_XGXS_CONTROL, 2361 wb_data, 2); 2362 2363 udelay(30); 2364 2365 /* TX MAC SA */ 2366 wb_data[0] = ((params->mac_addr[2] << 24) | 2367 (params->mac_addr[3] << 16) | 2368 (params->mac_addr[4] << 8) | 2369 params->mac_addr[5]); 2370 wb_data[1] = ((params->mac_addr[0] << 8) | 2371 params->mac_addr[1]); 2372 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_SOURCE_ADDR, 2373 wb_data, 2); 2374 2375 udelay(30); 2376 2377 /* Configure SAFC */ 2378 wb_data[0] = 0x1000200; 2379 wb_data[1] = 0; 2380 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS, 2381 wb_data, 2); 2382 udelay(30); 2383 2384 /* Set RX MTU */ 2385 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD; 2386 wb_data[1] = 0; 2387 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_MAX_SIZE, wb_data, 2); 2388 udelay(30); 2389 2390 /* Set TX MTU */ 2391 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD; 2392 wb_data[1] = 0; 2393 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_MAX_SIZE, wb_data, 2); 2394 udelay(30); 2395 /* Set cnt max size */ 2396 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD - 2; 2397 wb_data[1] = 0; 2398 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_CNT_MAX_SIZE, wb_data, 2); 2399 udelay(30); 2400 bnx2x_update_pfc_bmac2(params, vars, is_lb); 2401 2402 return 0; 2403 } 2404 2405 static int bnx2x_bmac_enable(struct link_params *params, 2406 struct link_vars *vars, 2407 u8 is_lb, u8 reset_bmac) 2408 { 2409 int rc = 0; 2410 u8 port = params->port; 2411 struct bnx2x *bp = params->bp; 2412 u32 val; 2413 /* Reset and unreset the BigMac */ 2414 if (reset_bmac) { 2415 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 2416 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); 2417 usleep_range(1000, 2000); 2418 } 2419 2420 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 2421 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); 2422 2423 /* Enable access for bmac registers */ 2424 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1); 2425 2426 /* Enable BMAC according to BMAC type*/ 2427 if (CHIP_IS_E2(bp)) 2428 rc = bnx2x_bmac2_enable(params, vars, is_lb); 2429 else 2430 rc = bnx2x_bmac1_enable(params, vars, is_lb); 2431 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1); 2432 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0); 2433 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0); 2434 val = 0; 2435 if ((params->feature_config_flags & 2436 FEATURE_CONFIG_PFC_ENABLED) || 2437 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)) 2438 val = 1; 2439 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val); 2440 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0); 2441 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x0); 2442 REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0); 2443 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x1); 2444 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x1); 2445 2446 vars->mac_type = MAC_TYPE_BMAC; 2447 return rc; 2448 } 2449 2450 static void bnx2x_set_bmac_rx(struct bnx2x *bp, u32 chip_id, u8 port, u8 en) 2451 { 2452 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM : 2453 NIG_REG_INGRESS_BMAC0_MEM; 2454 u32 wb_data[2]; 2455 u32 nig_bmac_enable = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4); 2456 2457 if (CHIP_IS_E2(bp)) 2458 bmac_addr += BIGMAC2_REGISTER_BMAC_CONTROL; 2459 else 2460 bmac_addr += BIGMAC_REGISTER_BMAC_CONTROL; 2461 /* Only if the bmac is out of reset */ 2462 if (REG_RD(bp, MISC_REG_RESET_REG_2) & 2463 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) && 2464 nig_bmac_enable) { 2465 /* Clear Rx Enable bit in BMAC_CONTROL register */ 2466 REG_RD_DMAE(bp, bmac_addr, wb_data, 2); 2467 if (en) 2468 wb_data[0] |= BMAC_CONTROL_RX_ENABLE; 2469 else 2470 wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE; 2471 REG_WR_DMAE(bp, bmac_addr, wb_data, 2); 2472 usleep_range(1000, 2000); 2473 } 2474 } 2475 2476 static int bnx2x_pbf_update(struct link_params *params, u32 flow_ctrl, 2477 u32 line_speed) 2478 { 2479 struct bnx2x *bp = params->bp; 2480 u8 port = params->port; 2481 u32 init_crd, crd; 2482 u32 count = 1000; 2483 2484 /* Disable port */ 2485 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1); 2486 2487 /* Wait for init credit */ 2488 init_crd = REG_RD(bp, PBF_REG_P0_INIT_CRD + port*4); 2489 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8); 2490 DP(NETIF_MSG_LINK, "init_crd 0x%x crd 0x%x\n", init_crd, crd); 2491 2492 while ((init_crd != crd) && count) { 2493 usleep_range(5000, 10000); 2494 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8); 2495 count--; 2496 } 2497 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8); 2498 if (init_crd != crd) { 2499 DP(NETIF_MSG_LINK, "BUG! init_crd 0x%x != crd 0x%x\n", 2500 init_crd, crd); 2501 return -EINVAL; 2502 } 2503 2504 if (flow_ctrl & BNX2X_FLOW_CTRL_RX || 2505 line_speed == SPEED_10 || 2506 line_speed == SPEED_100 || 2507 line_speed == SPEED_1000 || 2508 line_speed == SPEED_2500) { 2509 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 1); 2510 /* Update threshold */ 2511 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, 0); 2512 /* Update init credit */ 2513 init_crd = 778; /* (800-18-4) */ 2514 2515 } else { 2516 u32 thresh = (ETH_MAX_JUMBO_PACKET_SIZE + 2517 ETH_OVREHEAD)/16; 2518 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0); 2519 /* Update threshold */ 2520 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, thresh); 2521 /* Update init credit */ 2522 switch (line_speed) { 2523 case SPEED_10000: 2524 init_crd = thresh + 553 - 22; 2525 break; 2526 default: 2527 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n", 2528 line_speed); 2529 return -EINVAL; 2530 } 2531 } 2532 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, init_crd); 2533 DP(NETIF_MSG_LINK, "PBF updated to speed %d credit %d\n", 2534 line_speed, init_crd); 2535 2536 /* Probe the credit changes */ 2537 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x1); 2538 usleep_range(5000, 10000); 2539 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x0); 2540 2541 /* Enable port */ 2542 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0); 2543 return 0; 2544 } 2545 2546 /** 2547 * bnx2x_get_emac_base - retrive emac base address 2548 * 2549 * @bp: driver handle 2550 * @mdc_mdio_access: access type 2551 * @port: port id 2552 * 2553 * This function selects the MDC/MDIO access (through emac0 or 2554 * emac1) depend on the mdc_mdio_access, port, port swapped. Each 2555 * phy has a default access mode, which could also be overridden 2556 * by nvram configuration. This parameter, whether this is the 2557 * default phy configuration, or the nvram overrun 2558 * configuration, is passed here as mdc_mdio_access and selects 2559 * the emac_base for the CL45 read/writes operations 2560 */ 2561 static u32 bnx2x_get_emac_base(struct bnx2x *bp, 2562 u32 mdc_mdio_access, u8 port) 2563 { 2564 u32 emac_base = 0; 2565 switch (mdc_mdio_access) { 2566 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE: 2567 break; 2568 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0: 2569 if (REG_RD(bp, NIG_REG_PORT_SWAP)) 2570 emac_base = GRCBASE_EMAC1; 2571 else 2572 emac_base = GRCBASE_EMAC0; 2573 break; 2574 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1: 2575 if (REG_RD(bp, NIG_REG_PORT_SWAP)) 2576 emac_base = GRCBASE_EMAC0; 2577 else 2578 emac_base = GRCBASE_EMAC1; 2579 break; 2580 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH: 2581 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0; 2582 break; 2583 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED: 2584 emac_base = (port) ? GRCBASE_EMAC0 : GRCBASE_EMAC1; 2585 break; 2586 default: 2587 break; 2588 } 2589 return emac_base; 2590 2591 } 2592 2593 /******************************************************************/ 2594 /* CL22 access functions */ 2595 /******************************************************************/ 2596 static int bnx2x_cl22_write(struct bnx2x *bp, 2597 struct bnx2x_phy *phy, 2598 u16 reg, u16 val) 2599 { 2600 u32 tmp, mode; 2601 u8 i; 2602 int rc = 0; 2603 /* Switch to CL22 */ 2604 mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE); 2605 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, 2606 mode & ~EMAC_MDIO_MODE_CLAUSE_45); 2607 2608 /* Address */ 2609 tmp = ((phy->addr << 21) | (reg << 16) | val | 2610 EMAC_MDIO_COMM_COMMAND_WRITE_22 | 2611 EMAC_MDIO_COMM_START_BUSY); 2612 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); 2613 2614 for (i = 0; i < 50; i++) { 2615 udelay(10); 2616 2617 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); 2618 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) { 2619 udelay(5); 2620 break; 2621 } 2622 } 2623 if (tmp & EMAC_MDIO_COMM_START_BUSY) { 2624 DP(NETIF_MSG_LINK, "write phy register failed\n"); 2625 rc = -EFAULT; 2626 } 2627 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode); 2628 return rc; 2629 } 2630 2631 static int bnx2x_cl22_read(struct bnx2x *bp, 2632 struct bnx2x_phy *phy, 2633 u16 reg, u16 *ret_val) 2634 { 2635 u32 val, mode; 2636 u16 i; 2637 int rc = 0; 2638 2639 /* Switch to CL22 */ 2640 mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE); 2641 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, 2642 mode & ~EMAC_MDIO_MODE_CLAUSE_45); 2643 2644 /* Address */ 2645 val = ((phy->addr << 21) | (reg << 16) | 2646 EMAC_MDIO_COMM_COMMAND_READ_22 | 2647 EMAC_MDIO_COMM_START_BUSY); 2648 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); 2649 2650 for (i = 0; i < 50; i++) { 2651 udelay(10); 2652 2653 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); 2654 if (!(val & EMAC_MDIO_COMM_START_BUSY)) { 2655 *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA); 2656 udelay(5); 2657 break; 2658 } 2659 } 2660 if (val & EMAC_MDIO_COMM_START_BUSY) { 2661 DP(NETIF_MSG_LINK, "read phy register failed\n"); 2662 2663 *ret_val = 0; 2664 rc = -EFAULT; 2665 } 2666 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode); 2667 return rc; 2668 } 2669 2670 /******************************************************************/ 2671 /* CL45 access functions */ 2672 /******************************************************************/ 2673 static int bnx2x_cl45_read(struct bnx2x *bp, struct bnx2x_phy *phy, 2674 u8 devad, u16 reg, u16 *ret_val) 2675 { 2676 u32 val; 2677 u16 i; 2678 int rc = 0; 2679 u32 chip_id; 2680 if (phy->flags & FLAGS_MDC_MDIO_WA_G) { 2681 chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) | 2682 ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12); 2683 bnx2x_set_mdio_clk(bp, chip_id, phy->mdio_ctrl); 2684 } 2685 2686 if (phy->flags & FLAGS_MDC_MDIO_WA_B0) 2687 bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, 2688 EMAC_MDIO_STATUS_10MB); 2689 /* Address */ 2690 val = ((phy->addr << 21) | (devad << 16) | reg | 2691 EMAC_MDIO_COMM_COMMAND_ADDRESS | 2692 EMAC_MDIO_COMM_START_BUSY); 2693 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); 2694 2695 for (i = 0; i < 50; i++) { 2696 udelay(10); 2697 2698 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); 2699 if (!(val & EMAC_MDIO_COMM_START_BUSY)) { 2700 udelay(5); 2701 break; 2702 } 2703 } 2704 if (val & EMAC_MDIO_COMM_START_BUSY) { 2705 DP(NETIF_MSG_LINK, "read phy register failed\n"); 2706 netdev_err(bp->dev, "MDC/MDIO access timeout\n"); 2707 *ret_val = 0; 2708 rc = -EFAULT; 2709 } else { 2710 /* Data */ 2711 val = ((phy->addr << 21) | (devad << 16) | 2712 EMAC_MDIO_COMM_COMMAND_READ_45 | 2713 EMAC_MDIO_COMM_START_BUSY); 2714 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); 2715 2716 for (i = 0; i < 50; i++) { 2717 udelay(10); 2718 2719 val = REG_RD(bp, phy->mdio_ctrl + 2720 EMAC_REG_EMAC_MDIO_COMM); 2721 if (!(val & EMAC_MDIO_COMM_START_BUSY)) { 2722 *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA); 2723 break; 2724 } 2725 } 2726 if (val & EMAC_MDIO_COMM_START_BUSY) { 2727 DP(NETIF_MSG_LINK, "read phy register failed\n"); 2728 netdev_err(bp->dev, "MDC/MDIO access timeout\n"); 2729 *ret_val = 0; 2730 rc = -EFAULT; 2731 } 2732 } 2733 /* Work around for E3 A0 */ 2734 if (phy->flags & FLAGS_MDC_MDIO_WA) { 2735 phy->flags ^= FLAGS_DUMMY_READ; 2736 if (phy->flags & FLAGS_DUMMY_READ) { 2737 u16 temp_val; 2738 bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val); 2739 } 2740 } 2741 2742 if (phy->flags & FLAGS_MDC_MDIO_WA_B0) 2743 bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, 2744 EMAC_MDIO_STATUS_10MB); 2745 return rc; 2746 } 2747 2748 static int bnx2x_cl45_write(struct bnx2x *bp, struct bnx2x_phy *phy, 2749 u8 devad, u16 reg, u16 val) 2750 { 2751 u32 tmp; 2752 u8 i; 2753 int rc = 0; 2754 u32 chip_id; 2755 if (phy->flags & FLAGS_MDC_MDIO_WA_G) { 2756 chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) | 2757 ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12); 2758 bnx2x_set_mdio_clk(bp, chip_id, phy->mdio_ctrl); 2759 } 2760 2761 if (phy->flags & FLAGS_MDC_MDIO_WA_B0) 2762 bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, 2763 EMAC_MDIO_STATUS_10MB); 2764 2765 /* Address */ 2766 tmp = ((phy->addr << 21) | (devad << 16) | reg | 2767 EMAC_MDIO_COMM_COMMAND_ADDRESS | 2768 EMAC_MDIO_COMM_START_BUSY); 2769 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); 2770 2771 for (i = 0; i < 50; i++) { 2772 udelay(10); 2773 2774 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); 2775 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) { 2776 udelay(5); 2777 break; 2778 } 2779 } 2780 if (tmp & EMAC_MDIO_COMM_START_BUSY) { 2781 DP(NETIF_MSG_LINK, "write phy register failed\n"); 2782 netdev_err(bp->dev, "MDC/MDIO access timeout\n"); 2783 rc = -EFAULT; 2784 } else { 2785 /* Data */ 2786 tmp = ((phy->addr << 21) | (devad << 16) | val | 2787 EMAC_MDIO_COMM_COMMAND_WRITE_45 | 2788 EMAC_MDIO_COMM_START_BUSY); 2789 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); 2790 2791 for (i = 0; i < 50; i++) { 2792 udelay(10); 2793 2794 tmp = REG_RD(bp, phy->mdio_ctrl + 2795 EMAC_REG_EMAC_MDIO_COMM); 2796 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) { 2797 udelay(5); 2798 break; 2799 } 2800 } 2801 if (tmp & EMAC_MDIO_COMM_START_BUSY) { 2802 DP(NETIF_MSG_LINK, "write phy register failed\n"); 2803 netdev_err(bp->dev, "MDC/MDIO access timeout\n"); 2804 rc = -EFAULT; 2805 } 2806 } 2807 /* Work around for E3 A0 */ 2808 if (phy->flags & FLAGS_MDC_MDIO_WA) { 2809 phy->flags ^= FLAGS_DUMMY_READ; 2810 if (phy->flags & FLAGS_DUMMY_READ) { 2811 u16 temp_val; 2812 bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val); 2813 } 2814 } 2815 if (phy->flags & FLAGS_MDC_MDIO_WA_B0) 2816 bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, 2817 EMAC_MDIO_STATUS_10MB); 2818 return rc; 2819 } 2820 2821 /******************************************************************/ 2822 /* EEE section */ 2823 /******************************************************************/ 2824 static u8 bnx2x_eee_has_cap(struct link_params *params) 2825 { 2826 struct bnx2x *bp = params->bp; 2827 2828 if (REG_RD(bp, params->shmem2_base) <= 2829 offsetof(struct shmem2_region, eee_status[params->port])) 2830 return 0; 2831 2832 return 1; 2833 } 2834 2835 static int bnx2x_eee_nvram_to_time(u32 nvram_mode, u32 *idle_timer) 2836 { 2837 switch (nvram_mode) { 2838 case PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED: 2839 *idle_timer = EEE_MODE_NVRAM_BALANCED_TIME; 2840 break; 2841 case PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE: 2842 *idle_timer = EEE_MODE_NVRAM_AGGRESSIVE_TIME; 2843 break; 2844 case PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY: 2845 *idle_timer = EEE_MODE_NVRAM_LATENCY_TIME; 2846 break; 2847 default: 2848 *idle_timer = 0; 2849 break; 2850 } 2851 2852 return 0; 2853 } 2854 2855 static int bnx2x_eee_time_to_nvram(u32 idle_timer, u32 *nvram_mode) 2856 { 2857 switch (idle_timer) { 2858 case EEE_MODE_NVRAM_BALANCED_TIME: 2859 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED; 2860 break; 2861 case EEE_MODE_NVRAM_AGGRESSIVE_TIME: 2862 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE; 2863 break; 2864 case EEE_MODE_NVRAM_LATENCY_TIME: 2865 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY; 2866 break; 2867 default: 2868 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED; 2869 break; 2870 } 2871 2872 return 0; 2873 } 2874 2875 static u32 bnx2x_eee_calc_timer(struct link_params *params) 2876 { 2877 u32 eee_mode, eee_idle; 2878 struct bnx2x *bp = params->bp; 2879 2880 if (params->eee_mode & EEE_MODE_OVERRIDE_NVRAM) { 2881 if (params->eee_mode & EEE_MODE_OUTPUT_TIME) { 2882 /* time value in eee_mode --> used directly*/ 2883 eee_idle = params->eee_mode & EEE_MODE_TIMER_MASK; 2884 } else { 2885 /* hsi value in eee_mode --> time */ 2886 if (bnx2x_eee_nvram_to_time(params->eee_mode & 2887 EEE_MODE_NVRAM_MASK, 2888 &eee_idle)) 2889 return 0; 2890 } 2891 } else { 2892 /* hsi values in nvram --> time*/ 2893 eee_mode = ((REG_RD(bp, params->shmem_base + 2894 offsetof(struct shmem_region, dev_info. 2895 port_feature_config[params->port]. 2896 eee_power_mode)) & 2897 PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >> 2898 PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT); 2899 2900 if (bnx2x_eee_nvram_to_time(eee_mode, &eee_idle)) 2901 return 0; 2902 } 2903 2904 return eee_idle; 2905 } 2906 2907 static int bnx2x_eee_set_timers(struct link_params *params, 2908 struct link_vars *vars) 2909 { 2910 u32 eee_idle = 0, eee_mode; 2911 struct bnx2x *bp = params->bp; 2912 2913 eee_idle = bnx2x_eee_calc_timer(params); 2914 2915 if (eee_idle) { 2916 REG_WR(bp, MISC_REG_CPMU_LP_IDLE_THR_P0 + (params->port << 2), 2917 eee_idle); 2918 } else if ((params->eee_mode & EEE_MODE_ENABLE_LPI) && 2919 (params->eee_mode & EEE_MODE_OVERRIDE_NVRAM) && 2920 (params->eee_mode & EEE_MODE_OUTPUT_TIME)) { 2921 DP(NETIF_MSG_LINK, "Error: Tx LPI is enabled with timer 0\n"); 2922 return -EINVAL; 2923 } 2924 2925 vars->eee_status &= ~(SHMEM_EEE_TIMER_MASK | SHMEM_EEE_TIME_OUTPUT_BIT); 2926 if (params->eee_mode & EEE_MODE_OUTPUT_TIME) { 2927 /* eee_idle in 1u --> eee_status in 16u */ 2928 eee_idle >>= 4; 2929 vars->eee_status |= (eee_idle & SHMEM_EEE_TIMER_MASK) | 2930 SHMEM_EEE_TIME_OUTPUT_BIT; 2931 } else { 2932 if (bnx2x_eee_time_to_nvram(eee_idle, &eee_mode)) 2933 return -EINVAL; 2934 vars->eee_status |= eee_mode; 2935 } 2936 2937 return 0; 2938 } 2939 2940 static int bnx2x_eee_initial_config(struct link_params *params, 2941 struct link_vars *vars, u8 mode) 2942 { 2943 vars->eee_status |= ((u32) mode) << SHMEM_EEE_SUPPORTED_SHIFT; 2944 2945 /* Propagate params' bits --> vars (for migration exposure) */ 2946 if (params->eee_mode & EEE_MODE_ENABLE_LPI) 2947 vars->eee_status |= SHMEM_EEE_LPI_REQUESTED_BIT; 2948 else 2949 vars->eee_status &= ~SHMEM_EEE_LPI_REQUESTED_BIT; 2950 2951 if (params->eee_mode & EEE_MODE_ADV_LPI) 2952 vars->eee_status |= SHMEM_EEE_REQUESTED_BIT; 2953 else 2954 vars->eee_status &= ~SHMEM_EEE_REQUESTED_BIT; 2955 2956 return bnx2x_eee_set_timers(params, vars); 2957 } 2958 2959 static int bnx2x_eee_disable(struct bnx2x_phy *phy, 2960 struct link_params *params, 2961 struct link_vars *vars) 2962 { 2963 struct bnx2x *bp = params->bp; 2964 2965 /* Make Certain LPI is disabled */ 2966 REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2), 0); 2967 2968 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, 0x0); 2969 2970 vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK; 2971 2972 return 0; 2973 } 2974 2975 static int bnx2x_eee_advertise(struct bnx2x_phy *phy, 2976 struct link_params *params, 2977 struct link_vars *vars, u8 modes) 2978 { 2979 struct bnx2x *bp = params->bp; 2980 u16 val = 0; 2981 2982 /* Mask events preventing LPI generation */ 2983 REG_WR(bp, MISC_REG_CPMU_LP_MASK_EXT_P0 + (params->port << 2), 0xfc20); 2984 2985 if (modes & SHMEM_EEE_10G_ADV) { 2986 DP(NETIF_MSG_LINK, "Advertise 10GBase-T EEE\n"); 2987 val |= 0x8; 2988 } 2989 if (modes & SHMEM_EEE_1G_ADV) { 2990 DP(NETIF_MSG_LINK, "Advertise 1GBase-T EEE\n"); 2991 val |= 0x4; 2992 } 2993 2994 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, val); 2995 2996 vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK; 2997 vars->eee_status |= (modes << SHMEM_EEE_ADV_STATUS_SHIFT); 2998 2999 return 0; 3000 } 3001 3002 static void bnx2x_update_mng_eee(struct link_params *params, u32 eee_status) 3003 { 3004 struct bnx2x *bp = params->bp; 3005 3006 if (bnx2x_eee_has_cap(params)) 3007 REG_WR(bp, params->shmem2_base + 3008 offsetof(struct shmem2_region, 3009 eee_status[params->port]), eee_status); 3010 } 3011 3012 static void bnx2x_eee_an_resolve(struct bnx2x_phy *phy, 3013 struct link_params *params, 3014 struct link_vars *vars) 3015 { 3016 struct bnx2x *bp = params->bp; 3017 u16 adv = 0, lp = 0; 3018 u32 lp_adv = 0; 3019 u8 neg = 0; 3020 3021 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, &adv); 3022 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_LP_EEE_ADV, &lp); 3023 3024 if (lp & 0x2) { 3025 lp_adv |= SHMEM_EEE_100M_ADV; 3026 if (adv & 0x2) { 3027 if (vars->line_speed == SPEED_100) 3028 neg = 1; 3029 DP(NETIF_MSG_LINK, "EEE negotiated - 100M\n"); 3030 } 3031 } 3032 if (lp & 0x14) { 3033 lp_adv |= SHMEM_EEE_1G_ADV; 3034 if (adv & 0x14) { 3035 if (vars->line_speed == SPEED_1000) 3036 neg = 1; 3037 DP(NETIF_MSG_LINK, "EEE negotiated - 1G\n"); 3038 } 3039 } 3040 if (lp & 0x68) { 3041 lp_adv |= SHMEM_EEE_10G_ADV; 3042 if (adv & 0x68) { 3043 if (vars->line_speed == SPEED_10000) 3044 neg = 1; 3045 DP(NETIF_MSG_LINK, "EEE negotiated - 10G\n"); 3046 } 3047 } 3048 3049 vars->eee_status &= ~SHMEM_EEE_LP_ADV_STATUS_MASK; 3050 vars->eee_status |= (lp_adv << SHMEM_EEE_LP_ADV_STATUS_SHIFT); 3051 3052 if (neg) { 3053 DP(NETIF_MSG_LINK, "EEE is active\n"); 3054 vars->eee_status |= SHMEM_EEE_ACTIVE_BIT; 3055 } 3056 3057 } 3058 3059 /******************************************************************/ 3060 /* BSC access functions from E3 */ 3061 /******************************************************************/ 3062 static void bnx2x_bsc_module_sel(struct link_params *params) 3063 { 3064 int idx; 3065 u32 board_cfg, sfp_ctrl; 3066 u32 i2c_pins[I2C_SWITCH_WIDTH], i2c_val[I2C_SWITCH_WIDTH]; 3067 struct bnx2x *bp = params->bp; 3068 u8 port = params->port; 3069 /* Read I2C output PINs */ 3070 board_cfg = REG_RD(bp, params->shmem_base + 3071 offsetof(struct shmem_region, 3072 dev_info.shared_hw_config.board)); 3073 i2c_pins[I2C_BSC0] = board_cfg & SHARED_HW_CFG_E3_I2C_MUX0_MASK; 3074 i2c_pins[I2C_BSC1] = (board_cfg & SHARED_HW_CFG_E3_I2C_MUX1_MASK) >> 3075 SHARED_HW_CFG_E3_I2C_MUX1_SHIFT; 3076 3077 /* Read I2C output value */ 3078 sfp_ctrl = REG_RD(bp, params->shmem_base + 3079 offsetof(struct shmem_region, 3080 dev_info.port_hw_config[port].e3_cmn_pin_cfg)); 3081 i2c_val[I2C_BSC0] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX0_MASK) > 0; 3082 i2c_val[I2C_BSC1] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX1_MASK) > 0; 3083 DP(NETIF_MSG_LINK, "Setting BSC switch\n"); 3084 for (idx = 0; idx < I2C_SWITCH_WIDTH; idx++) 3085 bnx2x_set_cfg_pin(bp, i2c_pins[idx], i2c_val[idx]); 3086 } 3087 3088 static int bnx2x_bsc_read(struct link_params *params, 3089 struct bnx2x *bp, 3090 u8 sl_devid, 3091 u16 sl_addr, 3092 u8 lc_addr, 3093 u8 xfer_cnt, 3094 u32 *data_array) 3095 { 3096 u32 val, i; 3097 int rc = 0; 3098 3099 if (xfer_cnt > 16) { 3100 DP(NETIF_MSG_LINK, "invalid xfer_cnt %d. Max is 16 bytes\n", 3101 xfer_cnt); 3102 return -EINVAL; 3103 } 3104 bnx2x_bsc_module_sel(params); 3105 3106 xfer_cnt = 16 - lc_addr; 3107 3108 /* Enable the engine */ 3109 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND); 3110 val |= MCPR_IMC_COMMAND_ENABLE; 3111 REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val); 3112 3113 /* Program slave device ID */ 3114 val = (sl_devid << 16) | sl_addr; 3115 REG_WR(bp, MCP_REG_MCPR_IMC_SLAVE_CONTROL, val); 3116 3117 /* Start xfer with 0 byte to update the address pointer ???*/ 3118 val = (MCPR_IMC_COMMAND_ENABLE) | 3119 (MCPR_IMC_COMMAND_WRITE_OP << 3120 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) | 3121 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) | (0); 3122 REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val); 3123 3124 /* Poll for completion */ 3125 i = 0; 3126 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND); 3127 while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) { 3128 udelay(10); 3129 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND); 3130 if (i++ > 1000) { 3131 DP(NETIF_MSG_LINK, "wr 0 byte timed out after %d try\n", 3132 i); 3133 rc = -EFAULT; 3134 break; 3135 } 3136 } 3137 if (rc == -EFAULT) 3138 return rc; 3139 3140 /* Start xfer with read op */ 3141 val = (MCPR_IMC_COMMAND_ENABLE) | 3142 (MCPR_IMC_COMMAND_READ_OP << 3143 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) | 3144 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) | 3145 (xfer_cnt); 3146 REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val); 3147 3148 /* Poll for completion */ 3149 i = 0; 3150 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND); 3151 while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) { 3152 udelay(10); 3153 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND); 3154 if (i++ > 1000) { 3155 DP(NETIF_MSG_LINK, "rd op timed out after %d try\n", i); 3156 rc = -EFAULT; 3157 break; 3158 } 3159 } 3160 if (rc == -EFAULT) 3161 return rc; 3162 3163 for (i = (lc_addr >> 2); i < 4; i++) { 3164 data_array[i] = REG_RD(bp, (MCP_REG_MCPR_IMC_DATAREG0 + i*4)); 3165 #ifdef __BIG_ENDIAN 3166 data_array[i] = ((data_array[i] & 0x000000ff) << 24) | 3167 ((data_array[i] & 0x0000ff00) << 8) | 3168 ((data_array[i] & 0x00ff0000) >> 8) | 3169 ((data_array[i] & 0xff000000) >> 24); 3170 #endif 3171 } 3172 return rc; 3173 } 3174 3175 static void bnx2x_cl45_read_or_write(struct bnx2x *bp, struct bnx2x_phy *phy, 3176 u8 devad, u16 reg, u16 or_val) 3177 { 3178 u16 val; 3179 bnx2x_cl45_read(bp, phy, devad, reg, &val); 3180 bnx2x_cl45_write(bp, phy, devad, reg, val | or_val); 3181 } 3182 3183 static void bnx2x_cl45_read_and_write(struct bnx2x *bp, 3184 struct bnx2x_phy *phy, 3185 u8 devad, u16 reg, u16 and_val) 3186 { 3187 u16 val; 3188 bnx2x_cl45_read(bp, phy, devad, reg, &val); 3189 bnx2x_cl45_write(bp, phy, devad, reg, val & and_val); 3190 } 3191 3192 int bnx2x_phy_read(struct link_params *params, u8 phy_addr, 3193 u8 devad, u16 reg, u16 *ret_val) 3194 { 3195 u8 phy_index; 3196 /* Probe for the phy according to the given phy_addr, and execute 3197 * the read request on it 3198 */ 3199 for (phy_index = 0; phy_index < params->num_phys; phy_index++) { 3200 if (params->phy[phy_index].addr == phy_addr) { 3201 return bnx2x_cl45_read(params->bp, 3202 ¶ms->phy[phy_index], devad, 3203 reg, ret_val); 3204 } 3205 } 3206 return -EINVAL; 3207 } 3208 3209 int bnx2x_phy_write(struct link_params *params, u8 phy_addr, 3210 u8 devad, u16 reg, u16 val) 3211 { 3212 u8 phy_index; 3213 /* Probe for the phy according to the given phy_addr, and execute 3214 * the write request on it 3215 */ 3216 for (phy_index = 0; phy_index < params->num_phys; phy_index++) { 3217 if (params->phy[phy_index].addr == phy_addr) { 3218 return bnx2x_cl45_write(params->bp, 3219 ¶ms->phy[phy_index], devad, 3220 reg, val); 3221 } 3222 } 3223 return -EINVAL; 3224 } 3225 static u8 bnx2x_get_warpcore_lane(struct bnx2x_phy *phy, 3226 struct link_params *params) 3227 { 3228 u8 lane = 0; 3229 struct bnx2x *bp = params->bp; 3230 u32 path_swap, path_swap_ovr; 3231 u8 path, port; 3232 3233 path = BP_PATH(bp); 3234 port = params->port; 3235 3236 if (bnx2x_is_4_port_mode(bp)) { 3237 u32 port_swap, port_swap_ovr; 3238 3239 /* Figure out path swap value */ 3240 path_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP_OVWR); 3241 if (path_swap_ovr & 0x1) 3242 path_swap = (path_swap_ovr & 0x2); 3243 else 3244 path_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP); 3245 3246 if (path_swap) 3247 path = path ^ 1; 3248 3249 /* Figure out port swap value */ 3250 port_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP_OVWR); 3251 if (port_swap_ovr & 0x1) 3252 port_swap = (port_swap_ovr & 0x2); 3253 else 3254 port_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP); 3255 3256 if (port_swap) 3257 port = port ^ 1; 3258 3259 lane = (port<<1) + path; 3260 } else { /* Two port mode - no port swap */ 3261 3262 /* Figure out path swap value */ 3263 path_swap_ovr = 3264 REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP_OVWR); 3265 if (path_swap_ovr & 0x1) { 3266 path_swap = (path_swap_ovr & 0x2); 3267 } else { 3268 path_swap = 3269 REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP); 3270 } 3271 if (path_swap) 3272 path = path ^ 1; 3273 3274 lane = path << 1 ; 3275 } 3276 return lane; 3277 } 3278 3279 static void bnx2x_set_aer_mmd(struct link_params *params, 3280 struct bnx2x_phy *phy) 3281 { 3282 u32 ser_lane; 3283 u16 offset, aer_val; 3284 struct bnx2x *bp = params->bp; 3285 ser_lane = ((params->lane_config & 3286 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >> 3287 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT); 3288 3289 offset = (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ? 3290 (phy->addr + ser_lane) : 0; 3291 3292 if (USES_WARPCORE(bp)) { 3293 aer_val = bnx2x_get_warpcore_lane(phy, params); 3294 /* In Dual-lane mode, two lanes are joined together, 3295 * so in order to configure them, the AER broadcast method is 3296 * used here. 3297 * 0x200 is the broadcast address for lanes 0,1 3298 * 0x201 is the broadcast address for lanes 2,3 3299 */ 3300 if (phy->flags & FLAGS_WC_DUAL_MODE) 3301 aer_val = (aer_val >> 1) | 0x200; 3302 } else if (CHIP_IS_E2(bp)) 3303 aer_val = 0x3800 + offset - 1; 3304 else 3305 aer_val = 0x3800 + offset; 3306 3307 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, 3308 MDIO_AER_BLOCK_AER_REG, aer_val); 3309 3310 } 3311 3312 /******************************************************************/ 3313 /* Internal phy section */ 3314 /******************************************************************/ 3315 3316 static void bnx2x_set_serdes_access(struct bnx2x *bp, u8 port) 3317 { 3318 u32 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0; 3319 3320 /* Set Clause 22 */ 3321 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 1); 3322 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000); 3323 udelay(500); 3324 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f); 3325 udelay(500); 3326 /* Set Clause 45 */ 3327 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 0); 3328 } 3329 3330 static void bnx2x_serdes_deassert(struct bnx2x *bp, u8 port) 3331 { 3332 u32 val; 3333 3334 DP(NETIF_MSG_LINK, "bnx2x_serdes_deassert\n"); 3335 3336 val = SERDES_RESET_BITS << (port*16); 3337 3338 /* Reset and unreset the SerDes/XGXS */ 3339 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val); 3340 udelay(500); 3341 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val); 3342 3343 bnx2x_set_serdes_access(bp, port); 3344 3345 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_DEVAD + port*0x10, 3346 DEFAULT_PHY_DEV_ADDR); 3347 } 3348 3349 static void bnx2x_xgxs_specific_func(struct bnx2x_phy *phy, 3350 struct link_params *params, 3351 u32 action) 3352 { 3353 struct bnx2x *bp = params->bp; 3354 switch (action) { 3355 case PHY_INIT: 3356 /* Set correct devad */ 3357 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_ST + params->port*0x18, 0); 3358 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + params->port*0x18, 3359 phy->def_md_devad); 3360 break; 3361 } 3362 } 3363 3364 static void bnx2x_xgxs_deassert(struct link_params *params) 3365 { 3366 struct bnx2x *bp = params->bp; 3367 u8 port; 3368 u32 val; 3369 DP(NETIF_MSG_LINK, "bnx2x_xgxs_deassert\n"); 3370 port = params->port; 3371 3372 val = XGXS_RESET_BITS << (port*16); 3373 3374 /* Reset and unreset the SerDes/XGXS */ 3375 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val); 3376 udelay(500); 3377 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val); 3378 bnx2x_xgxs_specific_func(¶ms->phy[INT_PHY], params, 3379 PHY_INIT); 3380 } 3381 3382 static void bnx2x_calc_ieee_aneg_adv(struct bnx2x_phy *phy, 3383 struct link_params *params, u16 *ieee_fc) 3384 { 3385 struct bnx2x *bp = params->bp; 3386 *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX; 3387 /* Resolve pause mode and advertisement Please refer to Table 3388 * 28B-3 of the 802.3ab-1999 spec 3389 */ 3390 3391 switch (phy->req_flow_ctrl) { 3392 case BNX2X_FLOW_CTRL_AUTO: 3393 switch (params->req_fc_auto_adv) { 3394 case BNX2X_FLOW_CTRL_BOTH: 3395 case BNX2X_FLOW_CTRL_RX: 3396 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; 3397 break; 3398 case BNX2X_FLOW_CTRL_TX: 3399 *ieee_fc |= 3400 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC; 3401 break; 3402 default: 3403 break; 3404 } 3405 break; 3406 case BNX2X_FLOW_CTRL_TX: 3407 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC; 3408 break; 3409 3410 case BNX2X_FLOW_CTRL_RX: 3411 case BNX2X_FLOW_CTRL_BOTH: 3412 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; 3413 break; 3414 3415 case BNX2X_FLOW_CTRL_NONE: 3416 default: 3417 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE; 3418 break; 3419 } 3420 DP(NETIF_MSG_LINK, "ieee_fc = 0x%x\n", *ieee_fc); 3421 } 3422 3423 static void set_phy_vars(struct link_params *params, 3424 struct link_vars *vars) 3425 { 3426 struct bnx2x *bp = params->bp; 3427 u8 actual_phy_idx, phy_index, link_cfg_idx; 3428 u8 phy_config_swapped = params->multi_phy_config & 3429 PORT_HW_CFG_PHY_SWAPPED_ENABLED; 3430 for (phy_index = INT_PHY; phy_index < params->num_phys; 3431 phy_index++) { 3432 link_cfg_idx = LINK_CONFIG_IDX(phy_index); 3433 actual_phy_idx = phy_index; 3434 if (phy_config_swapped) { 3435 if (phy_index == EXT_PHY1) 3436 actual_phy_idx = EXT_PHY2; 3437 else if (phy_index == EXT_PHY2) 3438 actual_phy_idx = EXT_PHY1; 3439 } 3440 params->phy[actual_phy_idx].req_flow_ctrl = 3441 params->req_flow_ctrl[link_cfg_idx]; 3442 3443 params->phy[actual_phy_idx].req_line_speed = 3444 params->req_line_speed[link_cfg_idx]; 3445 3446 params->phy[actual_phy_idx].speed_cap_mask = 3447 params->speed_cap_mask[link_cfg_idx]; 3448 3449 params->phy[actual_phy_idx].req_duplex = 3450 params->req_duplex[link_cfg_idx]; 3451 3452 if (params->req_line_speed[link_cfg_idx] == 3453 SPEED_AUTO_NEG) 3454 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED; 3455 3456 DP(NETIF_MSG_LINK, "req_flow_ctrl %x, req_line_speed %x," 3457 " speed_cap_mask %x\n", 3458 params->phy[actual_phy_idx].req_flow_ctrl, 3459 params->phy[actual_phy_idx].req_line_speed, 3460 params->phy[actual_phy_idx].speed_cap_mask); 3461 } 3462 } 3463 3464 static void bnx2x_ext_phy_set_pause(struct link_params *params, 3465 struct bnx2x_phy *phy, 3466 struct link_vars *vars) 3467 { 3468 u16 val; 3469 struct bnx2x *bp = params->bp; 3470 /* Read modify write pause advertizing */ 3471 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &val); 3472 3473 val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH; 3474 3475 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */ 3476 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); 3477 if ((vars->ieee_fc & 3478 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) == 3479 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) { 3480 val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC; 3481 } 3482 if ((vars->ieee_fc & 3483 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) == 3484 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) { 3485 val |= MDIO_AN_REG_ADV_PAUSE_PAUSE; 3486 } 3487 DP(NETIF_MSG_LINK, "Ext phy AN advertize 0x%x\n", val); 3488 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val); 3489 } 3490 3491 static void bnx2x_pause_resolve(struct bnx2x_phy *phy, 3492 struct link_params *params, 3493 struct link_vars *vars, 3494 u32 pause_result) 3495 { 3496 struct bnx2x *bp = params->bp; 3497 /* LD LP */ 3498 switch (pause_result) { /* ASYM P ASYM P */ 3499 case 0xb: /* 1 0 1 1 */ 3500 DP(NETIF_MSG_LINK, "Flow Control: TX only\n"); 3501 vars->flow_ctrl = BNX2X_FLOW_CTRL_TX; 3502 break; 3503 3504 case 0xe: /* 1 1 1 0 */ 3505 DP(NETIF_MSG_LINK, "Flow Control: RX only\n"); 3506 vars->flow_ctrl = BNX2X_FLOW_CTRL_RX; 3507 break; 3508 3509 case 0x5: /* 0 1 0 1 */ 3510 case 0x7: /* 0 1 1 1 */ 3511 case 0xd: /* 1 1 0 1 */ 3512 case 0xf: /* 1 1 1 1 */ 3513 /* If the user selected to advertise RX ONLY, 3514 * although we advertised both, need to enable 3515 * RX only. 3516 */ 3517 if (params->req_fc_auto_adv == BNX2X_FLOW_CTRL_BOTH) { 3518 DP(NETIF_MSG_LINK, "Flow Control: RX & TX\n"); 3519 vars->flow_ctrl = BNX2X_FLOW_CTRL_BOTH; 3520 } else { 3521 DP(NETIF_MSG_LINK, "Flow Control: RX only\n"); 3522 vars->flow_ctrl = BNX2X_FLOW_CTRL_RX; 3523 } 3524 break; 3525 3526 default: 3527 DP(NETIF_MSG_LINK, "Flow Control: None\n"); 3528 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; 3529 break; 3530 } 3531 if (pause_result & (1<<0)) 3532 vars->link_status |= LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE; 3533 if (pause_result & (1<<1)) 3534 vars->link_status |= LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE; 3535 3536 } 3537 3538 static void bnx2x_ext_phy_update_adv_fc(struct bnx2x_phy *phy, 3539 struct link_params *params, 3540 struct link_vars *vars) 3541 { 3542 u16 ld_pause; /* local */ 3543 u16 lp_pause; /* link partner */ 3544 u16 pause_result; 3545 struct bnx2x *bp = params->bp; 3546 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) { 3547 bnx2x_cl22_read(bp, phy, 0x4, &ld_pause); 3548 bnx2x_cl22_read(bp, phy, 0x5, &lp_pause); 3549 } else if (CHIP_IS_E3(bp) && 3550 SINGLE_MEDIA_DIRECT(params)) { 3551 u8 lane = bnx2x_get_warpcore_lane(phy, params); 3552 u16 gp_status, gp_mask; 3553 bnx2x_cl45_read(bp, phy, 3554 MDIO_AN_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_4, 3555 &gp_status); 3556 gp_mask = (MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL | 3557 MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP) << 3558 lane; 3559 if ((gp_status & gp_mask) == gp_mask) { 3560 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, 3561 MDIO_AN_REG_ADV_PAUSE, &ld_pause); 3562 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, 3563 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause); 3564 } else { 3565 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, 3566 MDIO_AN_REG_CL37_FC_LD, &ld_pause); 3567 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, 3568 MDIO_AN_REG_CL37_FC_LP, &lp_pause); 3569 ld_pause = ((ld_pause & 3570 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) 3571 << 3); 3572 lp_pause = ((lp_pause & 3573 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) 3574 << 3); 3575 } 3576 } else { 3577 bnx2x_cl45_read(bp, phy, 3578 MDIO_AN_DEVAD, 3579 MDIO_AN_REG_ADV_PAUSE, &ld_pause); 3580 bnx2x_cl45_read(bp, phy, 3581 MDIO_AN_DEVAD, 3582 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause); 3583 } 3584 pause_result = (ld_pause & 3585 MDIO_AN_REG_ADV_PAUSE_MASK) >> 8; 3586 pause_result |= (lp_pause & 3587 MDIO_AN_REG_ADV_PAUSE_MASK) >> 10; 3588 DP(NETIF_MSG_LINK, "Ext PHY pause result 0x%x\n", pause_result); 3589 bnx2x_pause_resolve(phy, params, vars, pause_result); 3590 3591 } 3592 3593 static u8 bnx2x_ext_phy_resolve_fc(struct bnx2x_phy *phy, 3594 struct link_params *params, 3595 struct link_vars *vars) 3596 { 3597 u8 ret = 0; 3598 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; 3599 if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO) { 3600 /* Update the advertised flow-controled of LD/LP in AN */ 3601 if (phy->req_line_speed == SPEED_AUTO_NEG) 3602 bnx2x_ext_phy_update_adv_fc(phy, params, vars); 3603 /* But set the flow-control result as the requested one */ 3604 vars->flow_ctrl = phy->req_flow_ctrl; 3605 } else if (phy->req_line_speed != SPEED_AUTO_NEG) 3606 vars->flow_ctrl = params->req_fc_auto_adv; 3607 else if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) { 3608 ret = 1; 3609 bnx2x_ext_phy_update_adv_fc(phy, params, vars); 3610 } 3611 return ret; 3612 } 3613 /******************************************************************/ 3614 /* Warpcore section */ 3615 /******************************************************************/ 3616 /* The init_internal_warpcore should mirror the xgxs, 3617 * i.e. reset the lane (if needed), set aer for the 3618 * init configuration, and set/clear SGMII flag. Internal 3619 * phy init is done purely in phy_init stage. 3620 */ 3621 #define WC_TX_DRIVER(post2, idriver, ipre, ifir) \ 3622 ((post2 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) | \ 3623 (idriver << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) | \ 3624 (ipre << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET) | \ 3625 (ifir << MDIO_WC_REG_TX0_TX_DRIVER_IFIR_OFFSET)) 3626 3627 #define WC_TX_FIR(post, main, pre) \ 3628 ((post << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) | \ 3629 (main << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) | \ 3630 (pre << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET)) 3631 3632 static void bnx2x_warpcore_enable_AN_KR2(struct bnx2x_phy *phy, 3633 struct link_params *params, 3634 struct link_vars *vars) 3635 { 3636 struct bnx2x *bp = params->bp; 3637 u16 i; 3638 static struct bnx2x_reg_set reg_set[] = { 3639 /* Step 1 - Program the TX/RX alignment markers */ 3640 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL5, 0xa157}, 3641 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL7, 0xcbe2}, 3642 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL6, 0x7537}, 3643 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL9, 0xa157}, 3644 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL11, 0xcbe2}, 3645 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL10, 0x7537}, 3646 /* Step 2 - Configure the NP registers */ 3647 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_USERB0_CTRL, 0x000a}, 3648 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL1, 0x6400}, 3649 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL3, 0x0620}, 3650 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CODE_FIELD, 0x0157}, 3651 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI1, 0x6464}, 3652 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI2, 0x3150}, 3653 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI3, 0x3150}, 3654 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0157}, 3655 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0620} 3656 }; 3657 DP(NETIF_MSG_LINK, "Enabling 20G-KR2\n"); 3658 3659 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 3660 MDIO_WC_REG_CL49_USERB0_CTRL, (3<<6)); 3661 3662 for (i = 0; i < ARRAY_SIZE(reg_set); i++) 3663 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg, 3664 reg_set[i].val); 3665 3666 /* Start KR2 work-around timer which handles BCM8073 link-parner */ 3667 params->link_attr_sync |= LINK_ATTR_SYNC_KR2_ENABLE; 3668 bnx2x_update_link_attr(params, params->link_attr_sync); 3669 } 3670 3671 static void bnx2x_disable_kr2(struct link_params *params, 3672 struct link_vars *vars, 3673 struct bnx2x_phy *phy) 3674 { 3675 struct bnx2x *bp = params->bp; 3676 int i; 3677 static struct bnx2x_reg_set reg_set[] = { 3678 /* Step 1 - Program the TX/RX alignment markers */ 3679 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL5, 0x7690}, 3680 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL7, 0xe647}, 3681 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL6, 0xc4f0}, 3682 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL9, 0x7690}, 3683 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL11, 0xe647}, 3684 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL10, 0xc4f0}, 3685 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_USERB0_CTRL, 0x000c}, 3686 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL1, 0x6000}, 3687 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL3, 0x0000}, 3688 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CODE_FIELD, 0x0002}, 3689 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI1, 0x0000}, 3690 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI2, 0x0af7}, 3691 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI3, 0x0af7}, 3692 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0002}, 3693 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0000} 3694 }; 3695 DP(NETIF_MSG_LINK, "Disabling 20G-KR2\n"); 3696 3697 for (i = 0; i < ARRAY_SIZE(reg_set); i++) 3698 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg, 3699 reg_set[i].val); 3700 params->link_attr_sync &= ~LINK_ATTR_SYNC_KR2_ENABLE; 3701 bnx2x_update_link_attr(params, params->link_attr_sync); 3702 3703 vars->check_kr2_recovery_cnt = CHECK_KR2_RECOVERY_CNT; 3704 } 3705 3706 static void bnx2x_warpcore_set_lpi_passthrough(struct bnx2x_phy *phy, 3707 struct link_params *params) 3708 { 3709 struct bnx2x *bp = params->bp; 3710 3711 DP(NETIF_MSG_LINK, "Configure WC for LPI pass through\n"); 3712 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3713 MDIO_WC_REG_EEE_COMBO_CONTROL0, 0x7c); 3714 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 3715 MDIO_WC_REG_DIGITAL4_MISC5, 0xc000); 3716 } 3717 3718 static void bnx2x_warpcore_restart_AN_KR(struct bnx2x_phy *phy, 3719 struct link_params *params) 3720 { 3721 /* Restart autoneg on the leading lane only */ 3722 struct bnx2x *bp = params->bp; 3723 u16 lane = bnx2x_get_warpcore_lane(phy, params); 3724 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, 3725 MDIO_AER_BLOCK_AER_REG, lane); 3726 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, 3727 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200); 3728 3729 /* Restore AER */ 3730 bnx2x_set_aer_mmd(params, phy); 3731 } 3732 3733 static void bnx2x_warpcore_enable_AN_KR(struct bnx2x_phy *phy, 3734 struct link_params *params, 3735 struct link_vars *vars) { 3736 u16 lane, i, cl72_ctrl, an_adv = 0, val; 3737 u32 wc_lane_config; 3738 struct bnx2x *bp = params->bp; 3739 static struct bnx2x_reg_set reg_set[] = { 3740 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7}, 3741 {MDIO_PMA_DEVAD, MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0x0}, 3742 {MDIO_WC_DEVAD, MDIO_WC_REG_RX66_CONTROL, 0x7415}, 3743 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x6190}, 3744 /* Disable Autoneg: re-enable it after adv is done. */ 3745 {MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0}, 3746 {MDIO_PMA_DEVAD, MDIO_WC_REG_PMD_KR_CONTROL, 0x2}, 3747 {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP, 0}, 3748 }; 3749 DP(NETIF_MSG_LINK, "Enable Auto Negotiation for KR\n"); 3750 /* Set to default registers that may be overriden by 10G force */ 3751 for (i = 0; i < ARRAY_SIZE(reg_set); i++) 3752 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg, 3753 reg_set[i].val); 3754 3755 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 3756 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, &cl72_ctrl); 3757 cl72_ctrl &= 0x08ff; 3758 cl72_ctrl |= 0x3800; 3759 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3760 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, cl72_ctrl); 3761 3762 /* Check adding advertisement for 1G KX */ 3763 if (((vars->line_speed == SPEED_AUTO_NEG) && 3764 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) || 3765 (vars->line_speed == SPEED_1000)) { 3766 u16 addr = MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2; 3767 an_adv |= (1<<5); 3768 3769 /* Enable CL37 1G Parallel Detect */ 3770 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, addr, 0x1); 3771 DP(NETIF_MSG_LINK, "Advertize 1G\n"); 3772 } 3773 if (((vars->line_speed == SPEED_AUTO_NEG) && 3774 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) || 3775 (vars->line_speed == SPEED_10000)) { 3776 /* Check adding advertisement for 10G KR */ 3777 an_adv |= (1<<7); 3778 /* Enable 10G Parallel Detect */ 3779 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, 3780 MDIO_AER_BLOCK_AER_REG, 0); 3781 3782 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, 3783 MDIO_WC_REG_PAR_DET_10G_CTRL, 1); 3784 bnx2x_set_aer_mmd(params, phy); 3785 DP(NETIF_MSG_LINK, "Advertize 10G\n"); 3786 } 3787 3788 /* Set Transmit PMD settings */ 3789 lane = bnx2x_get_warpcore_lane(phy, params); 3790 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3791 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 3792 WC_TX_DRIVER(0x02, 0x06, 0x09, 0)); 3793 /* Configure the next lane if dual mode */ 3794 if (phy->flags & FLAGS_WC_DUAL_MODE) 3795 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3796 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*(lane+1), 3797 WC_TX_DRIVER(0x02, 0x06, 0x09, 0)); 3798 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3799 MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL, 3800 0x03f0); 3801 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3802 MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL, 3803 0x03f0); 3804 3805 /* Advertised speeds */ 3806 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, 3807 MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, an_adv); 3808 3809 /* Advertised and set FEC (Forward Error Correction) */ 3810 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, 3811 MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2, 3812 (MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY | 3813 MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ)); 3814 3815 /* Enable CL37 BAM */ 3816 if (REG_RD(bp, params->shmem_base + 3817 offsetof(struct shmem_region, dev_info. 3818 port_hw_config[params->port].default_cfg)) & 3819 PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) { 3820 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 3821 MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL, 3822 1); 3823 DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n"); 3824 } 3825 3826 /* Advertise pause */ 3827 bnx2x_ext_phy_set_pause(params, phy, vars); 3828 vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY; 3829 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 3830 MDIO_WC_REG_DIGITAL5_MISC7, 0x100); 3831 3832 /* Over 1G - AN local device user page 1 */ 3833 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3834 MDIO_WC_REG_DIGITAL3_UP1, 0x1f); 3835 3836 if (((phy->req_line_speed == SPEED_AUTO_NEG) && 3837 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) || 3838 (phy->req_line_speed == SPEED_20000)) { 3839 3840 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, 3841 MDIO_AER_BLOCK_AER_REG, lane); 3842 3843 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 3844 MDIO_WC_REG_RX1_PCI_CTRL + (0x10*lane), 3845 (1<<11)); 3846 3847 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3848 MDIO_WC_REG_XGXS_X2_CONTROL3, 0x7); 3849 bnx2x_set_aer_mmd(params, phy); 3850 3851 bnx2x_warpcore_enable_AN_KR2(phy, params, vars); 3852 } else { 3853 /* Enable Auto-Detect to support 1G over CL37 as well */ 3854 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3855 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0x10); 3856 wc_lane_config = REG_RD(bp, params->shmem_base + 3857 offsetof(struct shmem_region, dev_info. 3858 shared_hw_config.wc_lane_config)); 3859 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 3860 MDIO_WC_REG_RX0_PCI_CTRL + (lane << 4), &val); 3861 /* Force cl48 sync_status LOW to avoid getting stuck in CL73 3862 * parallel-detect loop when CL73 and CL37 are enabled. 3863 */ 3864 val |= 1 << 11; 3865 3866 /* Restore Polarity settings in case it was run over by 3867 * previous link owner 3868 */ 3869 if (wc_lane_config & 3870 (SHARED_HW_CFG_RX_LANE0_POL_FLIP_ENABLED << lane)) 3871 val |= 3 << 2; 3872 else 3873 val &= ~(3 << 2); 3874 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3875 MDIO_WC_REG_RX0_PCI_CTRL + (lane << 4), 3876 val); 3877 3878 bnx2x_disable_kr2(params, vars, phy); 3879 } 3880 3881 /* Enable Autoneg: only on the main lane */ 3882 bnx2x_warpcore_restart_AN_KR(phy, params); 3883 } 3884 3885 static void bnx2x_warpcore_set_10G_KR(struct bnx2x_phy *phy, 3886 struct link_params *params, 3887 struct link_vars *vars) 3888 { 3889 struct bnx2x *bp = params->bp; 3890 u16 val16, i, lane; 3891 static struct bnx2x_reg_set reg_set[] = { 3892 /* Disable Autoneg */ 3893 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7}, 3894 {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, 3895 0x3f00}, 3896 {MDIO_AN_DEVAD, MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, 0}, 3897 {MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0}, 3898 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL3_UP1, 0x1}, 3899 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL5_MISC7, 0xa}, 3900 /* Leave cl72 training enable, needed for KR */ 3901 {MDIO_PMA_DEVAD, MDIO_WC_REG_PMD_KR_CONTROL, 0x2} 3902 }; 3903 3904 for (i = 0; i < ARRAY_SIZE(reg_set); i++) 3905 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg, 3906 reg_set[i].val); 3907 3908 lane = bnx2x_get_warpcore_lane(phy, params); 3909 /* Global registers */ 3910 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, 3911 MDIO_AER_BLOCK_AER_REG, 0); 3912 /* Disable CL36 PCS Tx */ 3913 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 3914 MDIO_WC_REG_XGXSBLK1_LANECTRL0, &val16); 3915 val16 &= ~(0x0011 << lane); 3916 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3917 MDIO_WC_REG_XGXSBLK1_LANECTRL0, val16); 3918 3919 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 3920 MDIO_WC_REG_XGXSBLK1_LANECTRL1, &val16); 3921 val16 |= (0x0303 << (lane << 1)); 3922 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3923 MDIO_WC_REG_XGXSBLK1_LANECTRL1, val16); 3924 /* Restore AER */ 3925 bnx2x_set_aer_mmd(params, phy); 3926 /* Set speed via PMA/PMD register */ 3927 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 3928 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040); 3929 3930 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 3931 MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0xB); 3932 3933 /* Enable encoded forced speed */ 3934 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3935 MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x30); 3936 3937 /* Turn TX scramble payload only the 64/66 scrambler */ 3938 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3939 MDIO_WC_REG_TX66_CONTROL, 0x9); 3940 3941 /* Turn RX scramble payload only the 64/66 scrambler */ 3942 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 3943 MDIO_WC_REG_RX66_CONTROL, 0xF9); 3944 3945 /* Set and clear loopback to cause a reset to 64/66 decoder */ 3946 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3947 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x4000); 3948 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3949 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0); 3950 3951 } 3952 3953 static void bnx2x_warpcore_set_10G_XFI(struct bnx2x_phy *phy, 3954 struct link_params *params, 3955 u8 is_xfi) 3956 { 3957 struct bnx2x *bp = params->bp; 3958 u16 misc1_val, tap_val, tx_driver_val, lane, val; 3959 u32 cfg_tap_val, tx_drv_brdct, tx_equal; 3960 u32 ifir_val, ipost2_val, ipre_driver_val; 3961 3962 /* Hold rxSeqStart */ 3963 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 3964 MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x8000); 3965 3966 /* Hold tx_fifo_reset */ 3967 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 3968 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, 0x1); 3969 3970 /* Disable CL73 AN */ 3971 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0); 3972 3973 /* Disable 100FX Enable and Auto-Detect */ 3974 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, 3975 MDIO_WC_REG_FX100_CTRL1, 0xFFFA); 3976 3977 /* Disable 100FX Idle detect */ 3978 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 3979 MDIO_WC_REG_FX100_CTRL3, 0x0080); 3980 3981 /* Set Block address to Remote PHY & Clear forced_speed[5] */ 3982 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, 3983 MDIO_WC_REG_DIGITAL4_MISC3, 0xFF7F); 3984 3985 /* Turn off auto-detect & fiber mode */ 3986 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, 3987 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 3988 0xFFEE); 3989 3990 /* Set filter_force_link, disable_false_link and parallel_detect */ 3991 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 3992 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &val); 3993 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3994 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 3995 ((val | 0x0006) & 0xFFFE)); 3996 3997 /* Set XFI / SFI */ 3998 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 3999 MDIO_WC_REG_SERDESDIGITAL_MISC1, &misc1_val); 4000 4001 misc1_val &= ~(0x1f); 4002 4003 if (is_xfi) { 4004 misc1_val |= 0x5; 4005 tap_val = WC_TX_FIR(0x08, 0x37, 0x00); 4006 tx_driver_val = WC_TX_DRIVER(0x00, 0x02, 0x03, 0); 4007 } else { 4008 cfg_tap_val = REG_RD(bp, params->shmem_base + 4009 offsetof(struct shmem_region, dev_info. 4010 port_hw_config[params->port]. 4011 sfi_tap_values)); 4012 4013 tx_equal = cfg_tap_val & PORT_HW_CFG_TX_EQUALIZATION_MASK; 4014 4015 misc1_val |= 0x9; 4016 4017 /* TAP values are controlled by nvram, if value there isn't 0 */ 4018 if (tx_equal) 4019 tap_val = (u16)tx_equal; 4020 else 4021 tap_val = WC_TX_FIR(0x0f, 0x2b, 0x02); 4022 4023 ifir_val = DEFAULT_TX_DRV_IFIR; 4024 ipost2_val = DEFAULT_TX_DRV_POST2; 4025 ipre_driver_val = DEFAULT_TX_DRV_IPRE_DRIVER; 4026 tx_drv_brdct = DEFAULT_TX_DRV_BRDCT; 4027 4028 /* If any of the IFIR/IPRE_DRIVER/POST@ is set, apply all 4029 * configuration. 4030 */ 4031 if (cfg_tap_val & (PORT_HW_CFG_TX_DRV_IFIR_MASK | 4032 PORT_HW_CFG_TX_DRV_IPREDRIVER_MASK | 4033 PORT_HW_CFG_TX_DRV_POST2_MASK)) { 4034 ifir_val = (cfg_tap_val & 4035 PORT_HW_CFG_TX_DRV_IFIR_MASK) >> 4036 PORT_HW_CFG_TX_DRV_IFIR_SHIFT; 4037 ipre_driver_val = (cfg_tap_val & 4038 PORT_HW_CFG_TX_DRV_IPREDRIVER_MASK) 4039 >> PORT_HW_CFG_TX_DRV_IPREDRIVER_SHIFT; 4040 ipost2_val = (cfg_tap_val & 4041 PORT_HW_CFG_TX_DRV_POST2_MASK) >> 4042 PORT_HW_CFG_TX_DRV_POST2_SHIFT; 4043 } 4044 4045 if (cfg_tap_val & PORT_HW_CFG_TX_DRV_BROADCAST_MASK) { 4046 tx_drv_brdct = (cfg_tap_val & 4047 PORT_HW_CFG_TX_DRV_BROADCAST_MASK) >> 4048 PORT_HW_CFG_TX_DRV_BROADCAST_SHIFT; 4049 } 4050 4051 tx_driver_val = WC_TX_DRIVER(ipost2_val, tx_drv_brdct, 4052 ipre_driver_val, ifir_val); 4053 } 4054 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4055 MDIO_WC_REG_SERDESDIGITAL_MISC1, misc1_val); 4056 4057 /* Set Transmit PMD settings */ 4058 lane = bnx2x_get_warpcore_lane(phy, params); 4059 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4060 MDIO_WC_REG_TX_FIR_TAP, 4061 tap_val | MDIO_WC_REG_TX_FIR_TAP_ENABLE); 4062 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4063 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 4064 tx_driver_val); 4065 4066 /* Enable fiber mode, enable and invert sig_det */ 4067 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 4068 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0xd); 4069 4070 /* Set Block address to Remote PHY & Set forced_speed[5], 40bit mode */ 4071 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 4072 MDIO_WC_REG_DIGITAL4_MISC3, 0x8080); 4073 4074 bnx2x_warpcore_set_lpi_passthrough(phy, params); 4075 4076 /* 10G XFI Full Duplex */ 4077 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4078 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x100); 4079 4080 /* Release tx_fifo_reset */ 4081 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, 4082 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, 4083 0xFFFE); 4084 /* Release rxSeqStart */ 4085 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, 4086 MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x7FFF); 4087 } 4088 4089 static void bnx2x_warpcore_set_20G_force_KR2(struct bnx2x_phy *phy, 4090 struct link_params *params) 4091 { 4092 u16 val; 4093 struct bnx2x *bp = params->bp; 4094 /* Set global registers, so set AER lane to 0 */ 4095 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, 4096 MDIO_AER_BLOCK_AER_REG, 0); 4097 4098 /* Disable sequencer */ 4099 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, 4100 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, ~(1<<13)); 4101 4102 bnx2x_set_aer_mmd(params, phy); 4103 4104 bnx2x_cl45_read_and_write(bp, phy, MDIO_PMA_DEVAD, 4105 MDIO_WC_REG_PMD_KR_CONTROL, ~(1<<1)); 4106 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, 4107 MDIO_AN_REG_CTRL, 0); 4108 /* Turn off CL73 */ 4109 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 4110 MDIO_WC_REG_CL73_USERB0_CTRL, &val); 4111 val &= ~(1<<5); 4112 val |= (1<<6); 4113 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4114 MDIO_WC_REG_CL73_USERB0_CTRL, val); 4115 4116 /* Set 20G KR2 force speed */ 4117 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 4118 MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x1f); 4119 4120 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 4121 MDIO_WC_REG_DIGITAL4_MISC3, (1<<7)); 4122 4123 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 4124 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, &val); 4125 val &= ~(3<<14); 4126 val |= (1<<15); 4127 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4128 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, val); 4129 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4130 MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP, 0x835A); 4131 4132 /* Enable sequencer (over lane 0) */ 4133 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, 4134 MDIO_AER_BLOCK_AER_REG, 0); 4135 4136 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 4137 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, (1<<13)); 4138 4139 bnx2x_set_aer_mmd(params, phy); 4140 } 4141 4142 static void bnx2x_warpcore_set_20G_DXGXS(struct bnx2x *bp, 4143 struct bnx2x_phy *phy, 4144 u16 lane) 4145 { 4146 /* Rx0 anaRxControl1G */ 4147 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4148 MDIO_WC_REG_RX0_ANARXCONTROL1G, 0x90); 4149 4150 /* Rx2 anaRxControl1G */ 4151 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4152 MDIO_WC_REG_RX2_ANARXCONTROL1G, 0x90); 4153 4154 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4155 MDIO_WC_REG_RX66_SCW0, 0xE070); 4156 4157 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4158 MDIO_WC_REG_RX66_SCW1, 0xC0D0); 4159 4160 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4161 MDIO_WC_REG_RX66_SCW2, 0xA0B0); 4162 4163 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4164 MDIO_WC_REG_RX66_SCW3, 0x8090); 4165 4166 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4167 MDIO_WC_REG_RX66_SCW0_MASK, 0xF0F0); 4168 4169 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4170 MDIO_WC_REG_RX66_SCW1_MASK, 0xF0F0); 4171 4172 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4173 MDIO_WC_REG_RX66_SCW2_MASK, 0xF0F0); 4174 4175 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4176 MDIO_WC_REG_RX66_SCW3_MASK, 0xF0F0); 4177 4178 /* Serdes Digital Misc1 */ 4179 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4180 MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6008); 4181 4182 /* Serdes Digital4 Misc3 */ 4183 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4184 MDIO_WC_REG_DIGITAL4_MISC3, 0x8088); 4185 4186 /* Set Transmit PMD settings */ 4187 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4188 MDIO_WC_REG_TX_FIR_TAP, 4189 (WC_TX_FIR(0x12, 0x2d, 0x00) | 4190 MDIO_WC_REG_TX_FIR_TAP_ENABLE)); 4191 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4192 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 4193 WC_TX_DRIVER(0x02, 0x02, 0x02, 0)); 4194 } 4195 4196 static void bnx2x_warpcore_set_sgmii_speed(struct bnx2x_phy *phy, 4197 struct link_params *params, 4198 u8 fiber_mode, 4199 u8 always_autoneg) 4200 { 4201 struct bnx2x *bp = params->bp; 4202 u16 val16, digctrl_kx1, digctrl_kx2; 4203 4204 /* Clear XFI clock comp in non-10G single lane mode. */ 4205 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, 4206 MDIO_WC_REG_RX66_CONTROL, ~(3<<13)); 4207 4208 bnx2x_warpcore_set_lpi_passthrough(phy, params); 4209 4210 if (always_autoneg || phy->req_line_speed == SPEED_AUTO_NEG) { 4211 /* SGMII Autoneg */ 4212 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 4213 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 4214 0x1000); 4215 DP(NETIF_MSG_LINK, "set SGMII AUTONEG\n"); 4216 } else { 4217 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 4218 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16); 4219 val16 &= 0xcebf; 4220 switch (phy->req_line_speed) { 4221 case SPEED_10: 4222 break; 4223 case SPEED_100: 4224 val16 |= 0x2000; 4225 break; 4226 case SPEED_1000: 4227 val16 |= 0x0040; 4228 break; 4229 default: 4230 DP(NETIF_MSG_LINK, 4231 "Speed not supported: 0x%x\n", phy->req_line_speed); 4232 return; 4233 } 4234 4235 if (phy->req_duplex == DUPLEX_FULL) 4236 val16 |= 0x0100; 4237 4238 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4239 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16); 4240 4241 DP(NETIF_MSG_LINK, "set SGMII force speed %d\n", 4242 phy->req_line_speed); 4243 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 4244 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16); 4245 DP(NETIF_MSG_LINK, " (readback) %x\n", val16); 4246 } 4247 4248 /* SGMII Slave mode and disable signal detect */ 4249 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 4250 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &digctrl_kx1); 4251 if (fiber_mode) 4252 digctrl_kx1 = 1; 4253 else 4254 digctrl_kx1 &= 0xff4a; 4255 4256 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4257 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 4258 digctrl_kx1); 4259 4260 /* Turn off parallel detect */ 4261 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 4262 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &digctrl_kx2); 4263 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4264 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 4265 (digctrl_kx2 & ~(1<<2))); 4266 4267 /* Re-enable parallel detect */ 4268 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4269 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 4270 (digctrl_kx2 | (1<<2))); 4271 4272 /* Enable autodet */ 4273 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4274 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 4275 (digctrl_kx1 | 0x10)); 4276 } 4277 4278 static void bnx2x_warpcore_reset_lane(struct bnx2x *bp, 4279 struct bnx2x_phy *phy, 4280 u8 reset) 4281 { 4282 u16 val; 4283 /* Take lane out of reset after configuration is finished */ 4284 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 4285 MDIO_WC_REG_DIGITAL5_MISC6, &val); 4286 if (reset) 4287 val |= 0xC000; 4288 else 4289 val &= 0x3FFF; 4290 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4291 MDIO_WC_REG_DIGITAL5_MISC6, val); 4292 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 4293 MDIO_WC_REG_DIGITAL5_MISC6, &val); 4294 } 4295 /* Clear SFI/XFI link settings registers */ 4296 static void bnx2x_warpcore_clear_regs(struct bnx2x_phy *phy, 4297 struct link_params *params, 4298 u16 lane) 4299 { 4300 struct bnx2x *bp = params->bp; 4301 u16 i; 4302 static struct bnx2x_reg_set wc_regs[] = { 4303 {MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0}, 4304 {MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL1, 0x014a}, 4305 {MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL3, 0x0800}, 4306 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL4_MISC3, 0x8008}, 4307 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 4308 0x0195}, 4309 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 4310 0x0007}, 4311 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, 4312 0x0002}, 4313 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6000}, 4314 {MDIO_WC_DEVAD, MDIO_WC_REG_TX_FIR_TAP, 0x0000}, 4315 {MDIO_WC_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040}, 4316 {MDIO_WC_DEVAD, MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0x0140} 4317 }; 4318 /* Set XFI clock comp as default. */ 4319 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 4320 MDIO_WC_REG_RX66_CONTROL, (3<<13)); 4321 4322 for (i = 0; i < ARRAY_SIZE(wc_regs); i++) 4323 bnx2x_cl45_write(bp, phy, wc_regs[i].devad, wc_regs[i].reg, 4324 wc_regs[i].val); 4325 4326 lane = bnx2x_get_warpcore_lane(phy, params); 4327 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4328 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 0x0990); 4329 4330 } 4331 4332 static int bnx2x_get_mod_abs_int_cfg(struct bnx2x *bp, 4333 u32 chip_id, 4334 u32 shmem_base, u8 port, 4335 u8 *gpio_num, u8 *gpio_port) 4336 { 4337 u32 cfg_pin; 4338 *gpio_num = 0; 4339 *gpio_port = 0; 4340 if (CHIP_IS_E3(bp)) { 4341 cfg_pin = (REG_RD(bp, shmem_base + 4342 offsetof(struct shmem_region, 4343 dev_info.port_hw_config[port].e3_sfp_ctrl)) & 4344 PORT_HW_CFG_E3_MOD_ABS_MASK) >> 4345 PORT_HW_CFG_E3_MOD_ABS_SHIFT; 4346 4347 /* Should not happen. This function called upon interrupt 4348 * triggered by GPIO ( since EPIO can only generate interrupts 4349 * to MCP). 4350 * So if this function was called and none of the GPIOs was set, 4351 * it means the shit hit the fan. 4352 */ 4353 if ((cfg_pin < PIN_CFG_GPIO0_P0) || 4354 (cfg_pin > PIN_CFG_GPIO3_P1)) { 4355 DP(NETIF_MSG_LINK, 4356 "No cfg pin %x for module detect indication\n", 4357 cfg_pin); 4358 return -EINVAL; 4359 } 4360 4361 *gpio_num = (cfg_pin - PIN_CFG_GPIO0_P0) & 0x3; 4362 *gpio_port = (cfg_pin - PIN_CFG_GPIO0_P0) >> 2; 4363 } else { 4364 *gpio_num = MISC_REGISTERS_GPIO_3; 4365 *gpio_port = port; 4366 } 4367 4368 return 0; 4369 } 4370 4371 static int bnx2x_is_sfp_module_plugged(struct bnx2x_phy *phy, 4372 struct link_params *params) 4373 { 4374 struct bnx2x *bp = params->bp; 4375 u8 gpio_num, gpio_port; 4376 u32 gpio_val; 4377 if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id, 4378 params->shmem_base, params->port, 4379 &gpio_num, &gpio_port) != 0) 4380 return 0; 4381 gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port); 4382 4383 /* Call the handling function in case module is detected */ 4384 if (gpio_val == 0) 4385 return 1; 4386 else 4387 return 0; 4388 } 4389 static int bnx2x_warpcore_get_sigdet(struct bnx2x_phy *phy, 4390 struct link_params *params) 4391 { 4392 u16 gp2_status_reg0, lane; 4393 struct bnx2x *bp = params->bp; 4394 4395 lane = bnx2x_get_warpcore_lane(phy, params); 4396 4397 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_0, 4398 &gp2_status_reg0); 4399 4400 return (gp2_status_reg0 >> (8+lane)) & 0x1; 4401 } 4402 4403 static void bnx2x_warpcore_config_runtime(struct bnx2x_phy *phy, 4404 struct link_params *params, 4405 struct link_vars *vars) 4406 { 4407 struct bnx2x *bp = params->bp; 4408 u32 serdes_net_if; 4409 u16 gp_status1 = 0, lnkup = 0, lnkup_kr = 0; 4410 4411 vars->turn_to_run_wc_rt = vars->turn_to_run_wc_rt ? 0 : 1; 4412 4413 if (!vars->turn_to_run_wc_rt) 4414 return; 4415 4416 if (vars->rx_tx_asic_rst) { 4417 u16 lane = bnx2x_get_warpcore_lane(phy, params); 4418 serdes_net_if = (REG_RD(bp, params->shmem_base + 4419 offsetof(struct shmem_region, dev_info. 4420 port_hw_config[params->port].default_cfg)) & 4421 PORT_HW_CFG_NET_SERDES_IF_MASK); 4422 4423 switch (serdes_net_if) { 4424 case PORT_HW_CFG_NET_SERDES_IF_KR: 4425 /* Do we get link yet? */ 4426 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 0x81d1, 4427 &gp_status1); 4428 lnkup = (gp_status1 >> (8+lane)) & 0x1;/* 1G */ 4429 /*10G KR*/ 4430 lnkup_kr = (gp_status1 >> (12+lane)) & 0x1; 4431 4432 if (lnkup_kr || lnkup) { 4433 vars->rx_tx_asic_rst = 0; 4434 } else { 4435 /* Reset the lane to see if link comes up.*/ 4436 bnx2x_warpcore_reset_lane(bp, phy, 1); 4437 bnx2x_warpcore_reset_lane(bp, phy, 0); 4438 4439 /* Restart Autoneg */ 4440 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, 4441 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200); 4442 4443 vars->rx_tx_asic_rst--; 4444 DP(NETIF_MSG_LINK, "0x%x retry left\n", 4445 vars->rx_tx_asic_rst); 4446 } 4447 break; 4448 4449 default: 4450 break; 4451 } 4452 4453 } /*params->rx_tx_asic_rst*/ 4454 4455 } 4456 static void bnx2x_warpcore_config_sfi(struct bnx2x_phy *phy, 4457 struct link_params *params) 4458 { 4459 u16 lane = bnx2x_get_warpcore_lane(phy, params); 4460 struct bnx2x *bp = params->bp; 4461 bnx2x_warpcore_clear_regs(phy, params, lane); 4462 if ((params->req_line_speed[LINK_CONFIG_IDX(INT_PHY)] == 4463 SPEED_10000) && 4464 (phy->media_type != ETH_PHY_SFP_1G_FIBER)) { 4465 DP(NETIF_MSG_LINK, "Setting 10G SFI\n"); 4466 bnx2x_warpcore_set_10G_XFI(phy, params, 0); 4467 } else { 4468 DP(NETIF_MSG_LINK, "Setting 1G Fiber\n"); 4469 bnx2x_warpcore_set_sgmii_speed(phy, params, 1, 0); 4470 } 4471 } 4472 4473 static void bnx2x_sfp_e3_set_transmitter(struct link_params *params, 4474 struct bnx2x_phy *phy, 4475 u8 tx_en) 4476 { 4477 struct bnx2x *bp = params->bp; 4478 u32 cfg_pin; 4479 u8 port = params->port; 4480 4481 cfg_pin = REG_RD(bp, params->shmem_base + 4482 offsetof(struct shmem_region, 4483 dev_info.port_hw_config[port].e3_sfp_ctrl)) & 4484 PORT_HW_CFG_E3_TX_LASER_MASK; 4485 /* Set the !tx_en since this pin is DISABLE_TX_LASER */ 4486 DP(NETIF_MSG_LINK, "Setting WC TX to %d\n", tx_en); 4487 4488 /* For 20G, the expected pin to be used is 3 pins after the current */ 4489 bnx2x_set_cfg_pin(bp, cfg_pin, tx_en ^ 1); 4490 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G) 4491 bnx2x_set_cfg_pin(bp, cfg_pin + 3, tx_en ^ 1); 4492 } 4493 4494 static void bnx2x_warpcore_config_init(struct bnx2x_phy *phy, 4495 struct link_params *params, 4496 struct link_vars *vars) 4497 { 4498 struct bnx2x *bp = params->bp; 4499 u32 serdes_net_if; 4500 u8 fiber_mode; 4501 u16 lane = bnx2x_get_warpcore_lane(phy, params); 4502 serdes_net_if = (REG_RD(bp, params->shmem_base + 4503 offsetof(struct shmem_region, dev_info. 4504 port_hw_config[params->port].default_cfg)) & 4505 PORT_HW_CFG_NET_SERDES_IF_MASK); 4506 DP(NETIF_MSG_LINK, "Begin Warpcore init, link_speed %d, " 4507 "serdes_net_if = 0x%x\n", 4508 vars->line_speed, serdes_net_if); 4509 bnx2x_set_aer_mmd(params, phy); 4510 bnx2x_warpcore_reset_lane(bp, phy, 1); 4511 vars->phy_flags |= PHY_XGXS_FLAG; 4512 if ((serdes_net_if == PORT_HW_CFG_NET_SERDES_IF_SGMII) || 4513 (phy->req_line_speed && 4514 ((phy->req_line_speed == SPEED_100) || 4515 (phy->req_line_speed == SPEED_10)))) { 4516 vars->phy_flags |= PHY_SGMII_FLAG; 4517 DP(NETIF_MSG_LINK, "Setting SGMII mode\n"); 4518 bnx2x_warpcore_clear_regs(phy, params, lane); 4519 bnx2x_warpcore_set_sgmii_speed(phy, params, 0, 1); 4520 } else { 4521 switch (serdes_net_if) { 4522 case PORT_HW_CFG_NET_SERDES_IF_KR: 4523 /* Enable KR Auto Neg */ 4524 if (params->loopback_mode != LOOPBACK_EXT) 4525 bnx2x_warpcore_enable_AN_KR(phy, params, vars); 4526 else { 4527 DP(NETIF_MSG_LINK, "Setting KR 10G-Force\n"); 4528 bnx2x_warpcore_set_10G_KR(phy, params, vars); 4529 } 4530 break; 4531 4532 case PORT_HW_CFG_NET_SERDES_IF_XFI: 4533 bnx2x_warpcore_clear_regs(phy, params, lane); 4534 if (vars->line_speed == SPEED_10000) { 4535 DP(NETIF_MSG_LINK, "Setting 10G XFI\n"); 4536 bnx2x_warpcore_set_10G_XFI(phy, params, 1); 4537 } else { 4538 if (SINGLE_MEDIA_DIRECT(params)) { 4539 DP(NETIF_MSG_LINK, "1G Fiber\n"); 4540 fiber_mode = 1; 4541 } else { 4542 DP(NETIF_MSG_LINK, "10/100/1G SGMII\n"); 4543 fiber_mode = 0; 4544 } 4545 bnx2x_warpcore_set_sgmii_speed(phy, 4546 params, 4547 fiber_mode, 4548 0); 4549 } 4550 4551 break; 4552 4553 case PORT_HW_CFG_NET_SERDES_IF_SFI: 4554 /* Issue Module detection if module is plugged, or 4555 * enabled transmitter to avoid current leakage in case 4556 * no module is connected 4557 */ 4558 if ((params->loopback_mode == LOOPBACK_NONE) || 4559 (params->loopback_mode == LOOPBACK_EXT)) { 4560 if (bnx2x_is_sfp_module_plugged(phy, params)) 4561 bnx2x_sfp_module_detection(phy, params); 4562 else 4563 bnx2x_sfp_e3_set_transmitter(params, 4564 phy, 1); 4565 } 4566 4567 bnx2x_warpcore_config_sfi(phy, params); 4568 break; 4569 4570 case PORT_HW_CFG_NET_SERDES_IF_DXGXS: 4571 if (vars->line_speed != SPEED_20000) { 4572 DP(NETIF_MSG_LINK, "Speed not supported yet\n"); 4573 return; 4574 } 4575 DP(NETIF_MSG_LINK, "Setting 20G DXGXS\n"); 4576 bnx2x_warpcore_set_20G_DXGXS(bp, phy, lane); 4577 /* Issue Module detection */ 4578 4579 bnx2x_sfp_module_detection(phy, params); 4580 break; 4581 case PORT_HW_CFG_NET_SERDES_IF_KR2: 4582 if (!params->loopback_mode) { 4583 bnx2x_warpcore_enable_AN_KR(phy, params, vars); 4584 } else { 4585 DP(NETIF_MSG_LINK, "Setting KR 20G-Force\n"); 4586 bnx2x_warpcore_set_20G_force_KR2(phy, params); 4587 } 4588 break; 4589 default: 4590 DP(NETIF_MSG_LINK, 4591 "Unsupported Serdes Net Interface 0x%x\n", 4592 serdes_net_if); 4593 return; 4594 } 4595 } 4596 4597 /* Take lane out of reset after configuration is finished */ 4598 bnx2x_warpcore_reset_lane(bp, phy, 0); 4599 DP(NETIF_MSG_LINK, "Exit config init\n"); 4600 } 4601 4602 static void bnx2x_warpcore_link_reset(struct bnx2x_phy *phy, 4603 struct link_params *params) 4604 { 4605 struct bnx2x *bp = params->bp; 4606 u16 val16, lane; 4607 bnx2x_sfp_e3_set_transmitter(params, phy, 0); 4608 bnx2x_set_mdio_emac_per_phy(bp, params); 4609 bnx2x_set_aer_mmd(params, phy); 4610 /* Global register */ 4611 bnx2x_warpcore_reset_lane(bp, phy, 1); 4612 4613 /* Clear loopback settings (if any) */ 4614 /* 10G & 20G */ 4615 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, 4616 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0xBFFF); 4617 4618 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, 4619 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0xfffe); 4620 4621 /* Update those 1-copy registers */ 4622 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, 4623 MDIO_AER_BLOCK_AER_REG, 0); 4624 /* Enable 1G MDIO (1-copy) */ 4625 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, 4626 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, 4627 ~0x10); 4628 4629 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, 4630 MDIO_WC_REG_XGXSBLK1_LANECTRL2, 0xff00); 4631 lane = bnx2x_get_warpcore_lane(phy, params); 4632 /* Disable CL36 PCS Tx */ 4633 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 4634 MDIO_WC_REG_XGXSBLK1_LANECTRL0, &val16); 4635 val16 |= (0x11 << lane); 4636 if (phy->flags & FLAGS_WC_DUAL_MODE) 4637 val16 |= (0x22 << lane); 4638 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4639 MDIO_WC_REG_XGXSBLK1_LANECTRL0, val16); 4640 4641 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 4642 MDIO_WC_REG_XGXSBLK1_LANECTRL1, &val16); 4643 val16 &= ~(0x0303 << (lane << 1)); 4644 val16 |= (0x0101 << (lane << 1)); 4645 if (phy->flags & FLAGS_WC_DUAL_MODE) { 4646 val16 &= ~(0x0c0c << (lane << 1)); 4647 val16 |= (0x0404 << (lane << 1)); 4648 } 4649 4650 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4651 MDIO_WC_REG_XGXSBLK1_LANECTRL1, val16); 4652 /* Restore AER */ 4653 bnx2x_set_aer_mmd(params, phy); 4654 4655 } 4656 4657 static void bnx2x_set_warpcore_loopback(struct bnx2x_phy *phy, 4658 struct link_params *params) 4659 { 4660 struct bnx2x *bp = params->bp; 4661 u16 val16; 4662 u32 lane; 4663 DP(NETIF_MSG_LINK, "Setting Warpcore loopback type %x, speed %d\n", 4664 params->loopback_mode, phy->req_line_speed); 4665 4666 if (phy->req_line_speed < SPEED_10000 || 4667 phy->supported & SUPPORTED_20000baseKR2_Full) { 4668 /* 10/100/1000/20G-KR2 */ 4669 4670 /* Update those 1-copy registers */ 4671 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, 4672 MDIO_AER_BLOCK_AER_REG, 0); 4673 /* Enable 1G MDIO (1-copy) */ 4674 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 4675 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, 4676 0x10); 4677 /* Set 1G loopback based on lane (1-copy) */ 4678 lane = bnx2x_get_warpcore_lane(phy, params); 4679 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 4680 MDIO_WC_REG_XGXSBLK1_LANECTRL2, &val16); 4681 val16 |= (1<<lane); 4682 if (phy->flags & FLAGS_WC_DUAL_MODE) 4683 val16 |= (2<<lane); 4684 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4685 MDIO_WC_REG_XGXSBLK1_LANECTRL2, 4686 val16); 4687 4688 /* Switch back to 4-copy registers */ 4689 bnx2x_set_aer_mmd(params, phy); 4690 } else { 4691 /* 10G / 20G-DXGXS */ 4692 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 4693 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 4694 0x4000); 4695 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 4696 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1); 4697 } 4698 } 4699 4700 4701 4702 static void bnx2x_sync_link(struct link_params *params, 4703 struct link_vars *vars) 4704 { 4705 struct bnx2x *bp = params->bp; 4706 u8 link_10g_plus; 4707 if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG) 4708 vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG; 4709 vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP); 4710 if (vars->link_up) { 4711 DP(NETIF_MSG_LINK, "phy link up\n"); 4712 4713 vars->phy_link_up = 1; 4714 vars->duplex = DUPLEX_FULL; 4715 switch (vars->link_status & 4716 LINK_STATUS_SPEED_AND_DUPLEX_MASK) { 4717 case LINK_10THD: 4718 vars->duplex = DUPLEX_HALF; 4719 /* Fall thru */ 4720 case LINK_10TFD: 4721 vars->line_speed = SPEED_10; 4722 break; 4723 4724 case LINK_100TXHD: 4725 vars->duplex = DUPLEX_HALF; 4726 /* Fall thru */ 4727 case LINK_100T4: 4728 case LINK_100TXFD: 4729 vars->line_speed = SPEED_100; 4730 break; 4731 4732 case LINK_1000THD: 4733 vars->duplex = DUPLEX_HALF; 4734 /* Fall thru */ 4735 case LINK_1000TFD: 4736 vars->line_speed = SPEED_1000; 4737 break; 4738 4739 case LINK_2500THD: 4740 vars->duplex = DUPLEX_HALF; 4741 /* Fall thru */ 4742 case LINK_2500TFD: 4743 vars->line_speed = SPEED_2500; 4744 break; 4745 4746 case LINK_10GTFD: 4747 vars->line_speed = SPEED_10000; 4748 break; 4749 case LINK_20GTFD: 4750 vars->line_speed = SPEED_20000; 4751 break; 4752 default: 4753 break; 4754 } 4755 vars->flow_ctrl = 0; 4756 if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED) 4757 vars->flow_ctrl |= BNX2X_FLOW_CTRL_TX; 4758 4759 if (vars->link_status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED) 4760 vars->flow_ctrl |= BNX2X_FLOW_CTRL_RX; 4761 4762 if (!vars->flow_ctrl) 4763 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; 4764 4765 if (vars->line_speed && 4766 ((vars->line_speed == SPEED_10) || 4767 (vars->line_speed == SPEED_100))) { 4768 vars->phy_flags |= PHY_SGMII_FLAG; 4769 } else { 4770 vars->phy_flags &= ~PHY_SGMII_FLAG; 4771 } 4772 if (vars->line_speed && 4773 USES_WARPCORE(bp) && 4774 (vars->line_speed == SPEED_1000)) 4775 vars->phy_flags |= PHY_SGMII_FLAG; 4776 /* Anything 10 and over uses the bmac */ 4777 link_10g_plus = (vars->line_speed >= SPEED_10000); 4778 4779 if (link_10g_plus) { 4780 if (USES_WARPCORE(bp)) 4781 vars->mac_type = MAC_TYPE_XMAC; 4782 else 4783 vars->mac_type = MAC_TYPE_BMAC; 4784 } else { 4785 if (USES_WARPCORE(bp)) 4786 vars->mac_type = MAC_TYPE_UMAC; 4787 else 4788 vars->mac_type = MAC_TYPE_EMAC; 4789 } 4790 } else { /* Link down */ 4791 DP(NETIF_MSG_LINK, "phy link down\n"); 4792 4793 vars->phy_link_up = 0; 4794 4795 vars->line_speed = 0; 4796 vars->duplex = DUPLEX_FULL; 4797 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; 4798 4799 /* Indicate no mac active */ 4800 vars->mac_type = MAC_TYPE_NONE; 4801 if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG) 4802 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG; 4803 if (vars->link_status & LINK_STATUS_SFP_TX_FAULT) 4804 vars->phy_flags |= PHY_SFP_TX_FAULT_FLAG; 4805 } 4806 } 4807 4808 void bnx2x_link_status_update(struct link_params *params, 4809 struct link_vars *vars) 4810 { 4811 struct bnx2x *bp = params->bp; 4812 u8 port = params->port; 4813 u32 sync_offset, media_types; 4814 /* Update PHY configuration */ 4815 set_phy_vars(params, vars); 4816 4817 vars->link_status = REG_RD(bp, params->shmem_base + 4818 offsetof(struct shmem_region, 4819 port_mb[port].link_status)); 4820 4821 /* Force link UP in non LOOPBACK_EXT loopback mode(s) */ 4822 if (params->loopback_mode != LOOPBACK_NONE && 4823 params->loopback_mode != LOOPBACK_EXT) 4824 vars->link_status |= LINK_STATUS_LINK_UP; 4825 4826 if (bnx2x_eee_has_cap(params)) 4827 vars->eee_status = REG_RD(bp, params->shmem2_base + 4828 offsetof(struct shmem2_region, 4829 eee_status[params->port])); 4830 4831 vars->phy_flags = PHY_XGXS_FLAG; 4832 bnx2x_sync_link(params, vars); 4833 /* Sync media type */ 4834 sync_offset = params->shmem_base + 4835 offsetof(struct shmem_region, 4836 dev_info.port_hw_config[port].media_type); 4837 media_types = REG_RD(bp, sync_offset); 4838 4839 params->phy[INT_PHY].media_type = 4840 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) >> 4841 PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT; 4842 params->phy[EXT_PHY1].media_type = 4843 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK) >> 4844 PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT; 4845 params->phy[EXT_PHY2].media_type = 4846 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK) >> 4847 PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT; 4848 DP(NETIF_MSG_LINK, "media_types = 0x%x\n", media_types); 4849 4850 /* Sync AEU offset */ 4851 sync_offset = params->shmem_base + 4852 offsetof(struct shmem_region, 4853 dev_info.port_hw_config[port].aeu_int_mask); 4854 4855 vars->aeu_int_mask = REG_RD(bp, sync_offset); 4856 4857 /* Sync PFC status */ 4858 if (vars->link_status & LINK_STATUS_PFC_ENABLED) 4859 params->feature_config_flags |= 4860 FEATURE_CONFIG_PFC_ENABLED; 4861 else 4862 params->feature_config_flags &= 4863 ~FEATURE_CONFIG_PFC_ENABLED; 4864 4865 if (SHMEM2_HAS(bp, link_attr_sync)) 4866 params->link_attr_sync = SHMEM2_RD(bp, 4867 link_attr_sync[params->port]); 4868 4869 DP(NETIF_MSG_LINK, "link_status 0x%x phy_link_up %x int_mask 0x%x\n", 4870 vars->link_status, vars->phy_link_up, vars->aeu_int_mask); 4871 DP(NETIF_MSG_LINK, "line_speed %x duplex %x flow_ctrl 0x%x\n", 4872 vars->line_speed, vars->duplex, vars->flow_ctrl); 4873 } 4874 4875 static void bnx2x_set_master_ln(struct link_params *params, 4876 struct bnx2x_phy *phy) 4877 { 4878 struct bnx2x *bp = params->bp; 4879 u16 new_master_ln, ser_lane; 4880 ser_lane = ((params->lane_config & 4881 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >> 4882 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT); 4883 4884 /* Set the master_ln for AN */ 4885 CL22_RD_OVER_CL45(bp, phy, 4886 MDIO_REG_BANK_XGXS_BLOCK2, 4887 MDIO_XGXS_BLOCK2_TEST_MODE_LANE, 4888 &new_master_ln); 4889 4890 CL22_WR_OVER_CL45(bp, phy, 4891 MDIO_REG_BANK_XGXS_BLOCK2 , 4892 MDIO_XGXS_BLOCK2_TEST_MODE_LANE, 4893 (new_master_ln | ser_lane)); 4894 } 4895 4896 static int bnx2x_reset_unicore(struct link_params *params, 4897 struct bnx2x_phy *phy, 4898 u8 set_serdes) 4899 { 4900 struct bnx2x *bp = params->bp; 4901 u16 mii_control; 4902 u16 i; 4903 CL22_RD_OVER_CL45(bp, phy, 4904 MDIO_REG_BANK_COMBO_IEEE0, 4905 MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control); 4906 4907 /* Reset the unicore */ 4908 CL22_WR_OVER_CL45(bp, phy, 4909 MDIO_REG_BANK_COMBO_IEEE0, 4910 MDIO_COMBO_IEEE0_MII_CONTROL, 4911 (mii_control | 4912 MDIO_COMBO_IEEO_MII_CONTROL_RESET)); 4913 if (set_serdes) 4914 bnx2x_set_serdes_access(bp, params->port); 4915 4916 /* Wait for the reset to self clear */ 4917 for (i = 0; i < MDIO_ACCESS_TIMEOUT; i++) { 4918 udelay(5); 4919 4920 /* The reset erased the previous bank value */ 4921 CL22_RD_OVER_CL45(bp, phy, 4922 MDIO_REG_BANK_COMBO_IEEE0, 4923 MDIO_COMBO_IEEE0_MII_CONTROL, 4924 &mii_control); 4925 4926 if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) { 4927 udelay(5); 4928 return 0; 4929 } 4930 } 4931 4932 netdev_err(bp->dev, "Warning: PHY was not initialized," 4933 " Port %d\n", 4934 params->port); 4935 DP(NETIF_MSG_LINK, "BUG! XGXS is still in reset!\n"); 4936 return -EINVAL; 4937 4938 } 4939 4940 static void bnx2x_set_swap_lanes(struct link_params *params, 4941 struct bnx2x_phy *phy) 4942 { 4943 struct bnx2x *bp = params->bp; 4944 /* Each two bits represents a lane number: 4945 * No swap is 0123 => 0x1b no need to enable the swap 4946 */ 4947 u16 rx_lane_swap, tx_lane_swap; 4948 4949 rx_lane_swap = ((params->lane_config & 4950 PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >> 4951 PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT); 4952 tx_lane_swap = ((params->lane_config & 4953 PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >> 4954 PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT); 4955 4956 if (rx_lane_swap != 0x1b) { 4957 CL22_WR_OVER_CL45(bp, phy, 4958 MDIO_REG_BANK_XGXS_BLOCK2, 4959 MDIO_XGXS_BLOCK2_RX_LN_SWAP, 4960 (rx_lane_swap | 4961 MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE | 4962 MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE)); 4963 } else { 4964 CL22_WR_OVER_CL45(bp, phy, 4965 MDIO_REG_BANK_XGXS_BLOCK2, 4966 MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0); 4967 } 4968 4969 if (tx_lane_swap != 0x1b) { 4970 CL22_WR_OVER_CL45(bp, phy, 4971 MDIO_REG_BANK_XGXS_BLOCK2, 4972 MDIO_XGXS_BLOCK2_TX_LN_SWAP, 4973 (tx_lane_swap | 4974 MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE)); 4975 } else { 4976 CL22_WR_OVER_CL45(bp, phy, 4977 MDIO_REG_BANK_XGXS_BLOCK2, 4978 MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0); 4979 } 4980 } 4981 4982 static void bnx2x_set_parallel_detection(struct bnx2x_phy *phy, 4983 struct link_params *params) 4984 { 4985 struct bnx2x *bp = params->bp; 4986 u16 control2; 4987 CL22_RD_OVER_CL45(bp, phy, 4988 MDIO_REG_BANK_SERDES_DIGITAL, 4989 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2, 4990 &control2); 4991 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) 4992 control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN; 4993 else 4994 control2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN; 4995 DP(NETIF_MSG_LINK, "phy->speed_cap_mask = 0x%x, control2 = 0x%x\n", 4996 phy->speed_cap_mask, control2); 4997 CL22_WR_OVER_CL45(bp, phy, 4998 MDIO_REG_BANK_SERDES_DIGITAL, 4999 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2, 5000 control2); 5001 5002 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) && 5003 (phy->speed_cap_mask & 5004 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) { 5005 DP(NETIF_MSG_LINK, "XGXS\n"); 5006 5007 CL22_WR_OVER_CL45(bp, phy, 5008 MDIO_REG_BANK_10G_PARALLEL_DETECT, 5009 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK, 5010 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT); 5011 5012 CL22_RD_OVER_CL45(bp, phy, 5013 MDIO_REG_BANK_10G_PARALLEL_DETECT, 5014 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL, 5015 &control2); 5016 5017 5018 control2 |= 5019 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN; 5020 5021 CL22_WR_OVER_CL45(bp, phy, 5022 MDIO_REG_BANK_10G_PARALLEL_DETECT, 5023 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL, 5024 control2); 5025 5026 /* Disable parallel detection of HiG */ 5027 CL22_WR_OVER_CL45(bp, phy, 5028 MDIO_REG_BANK_XGXS_BLOCK2, 5029 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G, 5030 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS | 5031 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS); 5032 } 5033 } 5034 5035 static void bnx2x_set_autoneg(struct bnx2x_phy *phy, 5036 struct link_params *params, 5037 struct link_vars *vars, 5038 u8 enable_cl73) 5039 { 5040 struct bnx2x *bp = params->bp; 5041 u16 reg_val; 5042 5043 /* CL37 Autoneg */ 5044 CL22_RD_OVER_CL45(bp, phy, 5045 MDIO_REG_BANK_COMBO_IEEE0, 5046 MDIO_COMBO_IEEE0_MII_CONTROL, ®_val); 5047 5048 /* CL37 Autoneg Enabled */ 5049 if (vars->line_speed == SPEED_AUTO_NEG) 5050 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN; 5051 else /* CL37 Autoneg Disabled */ 5052 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN | 5053 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN); 5054 5055 CL22_WR_OVER_CL45(bp, phy, 5056 MDIO_REG_BANK_COMBO_IEEE0, 5057 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val); 5058 5059 /* Enable/Disable Autodetection */ 5060 5061 CL22_RD_OVER_CL45(bp, phy, 5062 MDIO_REG_BANK_SERDES_DIGITAL, 5063 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, ®_val); 5064 reg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN | 5065 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT); 5066 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE; 5067 if (vars->line_speed == SPEED_AUTO_NEG) 5068 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET; 5069 else 5070 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET; 5071 5072 CL22_WR_OVER_CL45(bp, phy, 5073 MDIO_REG_BANK_SERDES_DIGITAL, 5074 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val); 5075 5076 /* Enable TetonII and BAM autoneg */ 5077 CL22_RD_OVER_CL45(bp, phy, 5078 MDIO_REG_BANK_BAM_NEXT_PAGE, 5079 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL, 5080 ®_val); 5081 if (vars->line_speed == SPEED_AUTO_NEG) { 5082 /* Enable BAM aneg Mode and TetonII aneg Mode */ 5083 reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE | 5084 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN); 5085 } else { 5086 /* TetonII and BAM Autoneg Disabled */ 5087 reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE | 5088 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN); 5089 } 5090 CL22_WR_OVER_CL45(bp, phy, 5091 MDIO_REG_BANK_BAM_NEXT_PAGE, 5092 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL, 5093 reg_val); 5094 5095 if (enable_cl73) { 5096 /* Enable Cl73 FSM status bits */ 5097 CL22_WR_OVER_CL45(bp, phy, 5098 MDIO_REG_BANK_CL73_USERB0, 5099 MDIO_CL73_USERB0_CL73_UCTRL, 5100 0xe); 5101 5102 /* Enable BAM Station Manager*/ 5103 CL22_WR_OVER_CL45(bp, phy, 5104 MDIO_REG_BANK_CL73_USERB0, 5105 MDIO_CL73_USERB0_CL73_BAM_CTRL1, 5106 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN | 5107 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN | 5108 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN); 5109 5110 /* Advertise CL73 link speeds */ 5111 CL22_RD_OVER_CL45(bp, phy, 5112 MDIO_REG_BANK_CL73_IEEEB1, 5113 MDIO_CL73_IEEEB1_AN_ADV2, 5114 ®_val); 5115 if (phy->speed_cap_mask & 5116 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) 5117 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4; 5118 if (phy->speed_cap_mask & 5119 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) 5120 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX; 5121 5122 CL22_WR_OVER_CL45(bp, phy, 5123 MDIO_REG_BANK_CL73_IEEEB1, 5124 MDIO_CL73_IEEEB1_AN_ADV2, 5125 reg_val); 5126 5127 /* CL73 Autoneg Enabled */ 5128 reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN; 5129 5130 } else /* CL73 Autoneg Disabled */ 5131 reg_val = 0; 5132 5133 CL22_WR_OVER_CL45(bp, phy, 5134 MDIO_REG_BANK_CL73_IEEEB0, 5135 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val); 5136 } 5137 5138 /* Program SerDes, forced speed */ 5139 static void bnx2x_program_serdes(struct bnx2x_phy *phy, 5140 struct link_params *params, 5141 struct link_vars *vars) 5142 { 5143 struct bnx2x *bp = params->bp; 5144 u16 reg_val; 5145 5146 /* Program duplex, disable autoneg and sgmii*/ 5147 CL22_RD_OVER_CL45(bp, phy, 5148 MDIO_REG_BANK_COMBO_IEEE0, 5149 MDIO_COMBO_IEEE0_MII_CONTROL, ®_val); 5150 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX | 5151 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN | 5152 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK); 5153 if (phy->req_duplex == DUPLEX_FULL) 5154 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX; 5155 CL22_WR_OVER_CL45(bp, phy, 5156 MDIO_REG_BANK_COMBO_IEEE0, 5157 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val); 5158 5159 /* Program speed 5160 * - needed only if the speed is greater than 1G (2.5G or 10G) 5161 */ 5162 CL22_RD_OVER_CL45(bp, phy, 5163 MDIO_REG_BANK_SERDES_DIGITAL, 5164 MDIO_SERDES_DIGITAL_MISC1, ®_val); 5165 /* Clearing the speed value before setting the right speed */ 5166 DP(NETIF_MSG_LINK, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val); 5167 5168 reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK | 5169 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL); 5170 5171 if (!((vars->line_speed == SPEED_1000) || 5172 (vars->line_speed == SPEED_100) || 5173 (vars->line_speed == SPEED_10))) { 5174 5175 reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M | 5176 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL); 5177 if (vars->line_speed == SPEED_10000) 5178 reg_val |= 5179 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4; 5180 } 5181 5182 CL22_WR_OVER_CL45(bp, phy, 5183 MDIO_REG_BANK_SERDES_DIGITAL, 5184 MDIO_SERDES_DIGITAL_MISC1, reg_val); 5185 5186 } 5187 5188 static void bnx2x_set_brcm_cl37_advertisement(struct bnx2x_phy *phy, 5189 struct link_params *params) 5190 { 5191 struct bnx2x *bp = params->bp; 5192 u16 val = 0; 5193 5194 /* Set extended capabilities */ 5195 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) 5196 val |= MDIO_OVER_1G_UP1_2_5G; 5197 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) 5198 val |= MDIO_OVER_1G_UP1_10G; 5199 CL22_WR_OVER_CL45(bp, phy, 5200 MDIO_REG_BANK_OVER_1G, 5201 MDIO_OVER_1G_UP1, val); 5202 5203 CL22_WR_OVER_CL45(bp, phy, 5204 MDIO_REG_BANK_OVER_1G, 5205 MDIO_OVER_1G_UP3, 0x400); 5206 } 5207 5208 static void bnx2x_set_ieee_aneg_advertisement(struct bnx2x_phy *phy, 5209 struct link_params *params, 5210 u16 ieee_fc) 5211 { 5212 struct bnx2x *bp = params->bp; 5213 u16 val; 5214 /* For AN, we are always publishing full duplex */ 5215 5216 CL22_WR_OVER_CL45(bp, phy, 5217 MDIO_REG_BANK_COMBO_IEEE0, 5218 MDIO_COMBO_IEEE0_AUTO_NEG_ADV, ieee_fc); 5219 CL22_RD_OVER_CL45(bp, phy, 5220 MDIO_REG_BANK_CL73_IEEEB1, 5221 MDIO_CL73_IEEEB1_AN_ADV1, &val); 5222 val &= ~MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH; 5223 val |= ((ieee_fc<<3) & MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK); 5224 CL22_WR_OVER_CL45(bp, phy, 5225 MDIO_REG_BANK_CL73_IEEEB1, 5226 MDIO_CL73_IEEEB1_AN_ADV1, val); 5227 } 5228 5229 static void bnx2x_restart_autoneg(struct bnx2x_phy *phy, 5230 struct link_params *params, 5231 u8 enable_cl73) 5232 { 5233 struct bnx2x *bp = params->bp; 5234 u16 mii_control; 5235 5236 DP(NETIF_MSG_LINK, "bnx2x_restart_autoneg\n"); 5237 /* Enable and restart BAM/CL37 aneg */ 5238 5239 if (enable_cl73) { 5240 CL22_RD_OVER_CL45(bp, phy, 5241 MDIO_REG_BANK_CL73_IEEEB0, 5242 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, 5243 &mii_control); 5244 5245 CL22_WR_OVER_CL45(bp, phy, 5246 MDIO_REG_BANK_CL73_IEEEB0, 5247 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, 5248 (mii_control | 5249 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN | 5250 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN)); 5251 } else { 5252 5253 CL22_RD_OVER_CL45(bp, phy, 5254 MDIO_REG_BANK_COMBO_IEEE0, 5255 MDIO_COMBO_IEEE0_MII_CONTROL, 5256 &mii_control); 5257 DP(NETIF_MSG_LINK, 5258 "bnx2x_restart_autoneg mii_control before = 0x%x\n", 5259 mii_control); 5260 CL22_WR_OVER_CL45(bp, phy, 5261 MDIO_REG_BANK_COMBO_IEEE0, 5262 MDIO_COMBO_IEEE0_MII_CONTROL, 5263 (mii_control | 5264 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN | 5265 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN)); 5266 } 5267 } 5268 5269 static void bnx2x_initialize_sgmii_process(struct bnx2x_phy *phy, 5270 struct link_params *params, 5271 struct link_vars *vars) 5272 { 5273 struct bnx2x *bp = params->bp; 5274 u16 control1; 5275 5276 /* In SGMII mode, the unicore is always slave */ 5277 5278 CL22_RD_OVER_CL45(bp, phy, 5279 MDIO_REG_BANK_SERDES_DIGITAL, 5280 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, 5281 &control1); 5282 control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT; 5283 /* Set sgmii mode (and not fiber) */ 5284 control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE | 5285 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET | 5286 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE); 5287 CL22_WR_OVER_CL45(bp, phy, 5288 MDIO_REG_BANK_SERDES_DIGITAL, 5289 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, 5290 control1); 5291 5292 /* If forced speed */ 5293 if (!(vars->line_speed == SPEED_AUTO_NEG)) { 5294 /* Set speed, disable autoneg */ 5295 u16 mii_control; 5296 5297 CL22_RD_OVER_CL45(bp, phy, 5298 MDIO_REG_BANK_COMBO_IEEE0, 5299 MDIO_COMBO_IEEE0_MII_CONTROL, 5300 &mii_control); 5301 mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN | 5302 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK| 5303 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX); 5304 5305 switch (vars->line_speed) { 5306 case SPEED_100: 5307 mii_control |= 5308 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100; 5309 break; 5310 case SPEED_1000: 5311 mii_control |= 5312 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000; 5313 break; 5314 case SPEED_10: 5315 /* There is nothing to set for 10M */ 5316 break; 5317 default: 5318 /* Invalid speed for SGMII */ 5319 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n", 5320 vars->line_speed); 5321 break; 5322 } 5323 5324 /* Setting the full duplex */ 5325 if (phy->req_duplex == DUPLEX_FULL) 5326 mii_control |= 5327 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX; 5328 CL22_WR_OVER_CL45(bp, phy, 5329 MDIO_REG_BANK_COMBO_IEEE0, 5330 MDIO_COMBO_IEEE0_MII_CONTROL, 5331 mii_control); 5332 5333 } else { /* AN mode */ 5334 /* Enable and restart AN */ 5335 bnx2x_restart_autoneg(phy, params, 0); 5336 } 5337 } 5338 5339 /* Link management 5340 */ 5341 static int bnx2x_direct_parallel_detect_used(struct bnx2x_phy *phy, 5342 struct link_params *params) 5343 { 5344 struct bnx2x *bp = params->bp; 5345 u16 pd_10g, status2_1000x; 5346 if (phy->req_line_speed != SPEED_AUTO_NEG) 5347 return 0; 5348 CL22_RD_OVER_CL45(bp, phy, 5349 MDIO_REG_BANK_SERDES_DIGITAL, 5350 MDIO_SERDES_DIGITAL_A_1000X_STATUS2, 5351 &status2_1000x); 5352 CL22_RD_OVER_CL45(bp, phy, 5353 MDIO_REG_BANK_SERDES_DIGITAL, 5354 MDIO_SERDES_DIGITAL_A_1000X_STATUS2, 5355 &status2_1000x); 5356 if (status2_1000x & MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED) { 5357 DP(NETIF_MSG_LINK, "1G parallel detect link on port %d\n", 5358 params->port); 5359 return 1; 5360 } 5361 5362 CL22_RD_OVER_CL45(bp, phy, 5363 MDIO_REG_BANK_10G_PARALLEL_DETECT, 5364 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS, 5365 &pd_10g); 5366 5367 if (pd_10g & MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK) { 5368 DP(NETIF_MSG_LINK, "10G parallel detect link on port %d\n", 5369 params->port); 5370 return 1; 5371 } 5372 return 0; 5373 } 5374 5375 static void bnx2x_update_adv_fc(struct bnx2x_phy *phy, 5376 struct link_params *params, 5377 struct link_vars *vars, 5378 u32 gp_status) 5379 { 5380 u16 ld_pause; /* local driver */ 5381 u16 lp_pause; /* link partner */ 5382 u16 pause_result; 5383 struct bnx2x *bp = params->bp; 5384 if ((gp_status & 5385 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | 5386 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) == 5387 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | 5388 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) { 5389 5390 CL22_RD_OVER_CL45(bp, phy, 5391 MDIO_REG_BANK_CL73_IEEEB1, 5392 MDIO_CL73_IEEEB1_AN_ADV1, 5393 &ld_pause); 5394 CL22_RD_OVER_CL45(bp, phy, 5395 MDIO_REG_BANK_CL73_IEEEB1, 5396 MDIO_CL73_IEEEB1_AN_LP_ADV1, 5397 &lp_pause); 5398 pause_result = (ld_pause & 5399 MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK) >> 8; 5400 pause_result |= (lp_pause & 5401 MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK) >> 10; 5402 DP(NETIF_MSG_LINK, "pause_result CL73 0x%x\n", pause_result); 5403 } else { 5404 CL22_RD_OVER_CL45(bp, phy, 5405 MDIO_REG_BANK_COMBO_IEEE0, 5406 MDIO_COMBO_IEEE0_AUTO_NEG_ADV, 5407 &ld_pause); 5408 CL22_RD_OVER_CL45(bp, phy, 5409 MDIO_REG_BANK_COMBO_IEEE0, 5410 MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1, 5411 &lp_pause); 5412 pause_result = (ld_pause & 5413 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>5; 5414 pause_result |= (lp_pause & 5415 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7; 5416 DP(NETIF_MSG_LINK, "pause_result CL37 0x%x\n", pause_result); 5417 } 5418 bnx2x_pause_resolve(phy, params, vars, pause_result); 5419 5420 } 5421 5422 static void bnx2x_flow_ctrl_resolve(struct bnx2x_phy *phy, 5423 struct link_params *params, 5424 struct link_vars *vars, 5425 u32 gp_status) 5426 { 5427 struct bnx2x *bp = params->bp; 5428 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; 5429 5430 /* Resolve from gp_status in case of AN complete and not sgmii */ 5431 if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO) { 5432 /* Update the advertised flow-controled of LD/LP in AN */ 5433 if (phy->req_line_speed == SPEED_AUTO_NEG) 5434 bnx2x_update_adv_fc(phy, params, vars, gp_status); 5435 /* But set the flow-control result as the requested one */ 5436 vars->flow_ctrl = phy->req_flow_ctrl; 5437 } else if (phy->req_line_speed != SPEED_AUTO_NEG) 5438 vars->flow_ctrl = params->req_fc_auto_adv; 5439 else if ((gp_status & MDIO_AN_CL73_OR_37_COMPLETE) && 5440 (!(vars->phy_flags & PHY_SGMII_FLAG))) { 5441 if (bnx2x_direct_parallel_detect_used(phy, params)) { 5442 vars->flow_ctrl = params->req_fc_auto_adv; 5443 return; 5444 } 5445 bnx2x_update_adv_fc(phy, params, vars, gp_status); 5446 } 5447 DP(NETIF_MSG_LINK, "flow_ctrl 0x%x\n", vars->flow_ctrl); 5448 } 5449 5450 static void bnx2x_check_fallback_to_cl37(struct bnx2x_phy *phy, 5451 struct link_params *params) 5452 { 5453 struct bnx2x *bp = params->bp; 5454 u16 rx_status, ustat_val, cl37_fsm_received; 5455 DP(NETIF_MSG_LINK, "bnx2x_check_fallback_to_cl37\n"); 5456 /* Step 1: Make sure signal is detected */ 5457 CL22_RD_OVER_CL45(bp, phy, 5458 MDIO_REG_BANK_RX0, 5459 MDIO_RX0_RX_STATUS, 5460 &rx_status); 5461 if ((rx_status & MDIO_RX0_RX_STATUS_SIGDET) != 5462 (MDIO_RX0_RX_STATUS_SIGDET)) { 5463 DP(NETIF_MSG_LINK, "Signal is not detected. Restoring CL73." 5464 "rx_status(0x80b0) = 0x%x\n", rx_status); 5465 CL22_WR_OVER_CL45(bp, phy, 5466 MDIO_REG_BANK_CL73_IEEEB0, 5467 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, 5468 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN); 5469 return; 5470 } 5471 /* Step 2: Check CL73 state machine */ 5472 CL22_RD_OVER_CL45(bp, phy, 5473 MDIO_REG_BANK_CL73_USERB0, 5474 MDIO_CL73_USERB0_CL73_USTAT1, 5475 &ustat_val); 5476 if ((ustat_val & 5477 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK | 5478 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) != 5479 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK | 5480 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) { 5481 DP(NETIF_MSG_LINK, "CL73 state-machine is not stable. " 5482 "ustat_val(0x8371) = 0x%x\n", ustat_val); 5483 return; 5484 } 5485 /* Step 3: Check CL37 Message Pages received to indicate LP 5486 * supports only CL37 5487 */ 5488 CL22_RD_OVER_CL45(bp, phy, 5489 MDIO_REG_BANK_REMOTE_PHY, 5490 MDIO_REMOTE_PHY_MISC_RX_STATUS, 5491 &cl37_fsm_received); 5492 if ((cl37_fsm_received & 5493 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG | 5494 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) != 5495 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG | 5496 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) { 5497 DP(NETIF_MSG_LINK, "No CL37 FSM were received. " 5498 "misc_rx_status(0x8330) = 0x%x\n", 5499 cl37_fsm_received); 5500 return; 5501 } 5502 /* The combined cl37/cl73 fsm state information indicating that 5503 * we are connected to a device which does not support cl73, but 5504 * does support cl37 BAM. In this case we disable cl73 and 5505 * restart cl37 auto-neg 5506 */ 5507 5508 /* Disable CL73 */ 5509 CL22_WR_OVER_CL45(bp, phy, 5510 MDIO_REG_BANK_CL73_IEEEB0, 5511 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, 5512 0); 5513 /* Restart CL37 autoneg */ 5514 bnx2x_restart_autoneg(phy, params, 0); 5515 DP(NETIF_MSG_LINK, "Disabling CL73, and restarting CL37 autoneg\n"); 5516 } 5517 5518 static void bnx2x_xgxs_an_resolve(struct bnx2x_phy *phy, 5519 struct link_params *params, 5520 struct link_vars *vars, 5521 u32 gp_status) 5522 { 5523 if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE) 5524 vars->link_status |= 5525 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; 5526 5527 if (bnx2x_direct_parallel_detect_used(phy, params)) 5528 vars->link_status |= 5529 LINK_STATUS_PARALLEL_DETECTION_USED; 5530 } 5531 static int bnx2x_get_link_speed_duplex(struct bnx2x_phy *phy, 5532 struct link_params *params, 5533 struct link_vars *vars, 5534 u16 is_link_up, 5535 u16 speed_mask, 5536 u16 is_duplex) 5537 { 5538 struct bnx2x *bp = params->bp; 5539 if (phy->req_line_speed == SPEED_AUTO_NEG) 5540 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED; 5541 if (is_link_up) { 5542 DP(NETIF_MSG_LINK, "phy link up\n"); 5543 5544 vars->phy_link_up = 1; 5545 vars->link_status |= LINK_STATUS_LINK_UP; 5546 5547 switch (speed_mask) { 5548 case GP_STATUS_10M: 5549 vars->line_speed = SPEED_10; 5550 if (is_duplex == DUPLEX_FULL) 5551 vars->link_status |= LINK_10TFD; 5552 else 5553 vars->link_status |= LINK_10THD; 5554 break; 5555 5556 case GP_STATUS_100M: 5557 vars->line_speed = SPEED_100; 5558 if (is_duplex == DUPLEX_FULL) 5559 vars->link_status |= LINK_100TXFD; 5560 else 5561 vars->link_status |= LINK_100TXHD; 5562 break; 5563 5564 case GP_STATUS_1G: 5565 case GP_STATUS_1G_KX: 5566 vars->line_speed = SPEED_1000; 5567 if (is_duplex == DUPLEX_FULL) 5568 vars->link_status |= LINK_1000TFD; 5569 else 5570 vars->link_status |= LINK_1000THD; 5571 break; 5572 5573 case GP_STATUS_2_5G: 5574 vars->line_speed = SPEED_2500; 5575 if (is_duplex == DUPLEX_FULL) 5576 vars->link_status |= LINK_2500TFD; 5577 else 5578 vars->link_status |= LINK_2500THD; 5579 break; 5580 5581 case GP_STATUS_5G: 5582 case GP_STATUS_6G: 5583 DP(NETIF_MSG_LINK, 5584 "link speed unsupported gp_status 0x%x\n", 5585 speed_mask); 5586 return -EINVAL; 5587 5588 case GP_STATUS_10G_KX4: 5589 case GP_STATUS_10G_HIG: 5590 case GP_STATUS_10G_CX4: 5591 case GP_STATUS_10G_KR: 5592 case GP_STATUS_10G_SFI: 5593 case GP_STATUS_10G_XFI: 5594 vars->line_speed = SPEED_10000; 5595 vars->link_status |= LINK_10GTFD; 5596 break; 5597 case GP_STATUS_20G_DXGXS: 5598 case GP_STATUS_20G_KR2: 5599 vars->line_speed = SPEED_20000; 5600 vars->link_status |= LINK_20GTFD; 5601 break; 5602 default: 5603 DP(NETIF_MSG_LINK, 5604 "link speed unsupported gp_status 0x%x\n", 5605 speed_mask); 5606 return -EINVAL; 5607 } 5608 } else { /* link_down */ 5609 DP(NETIF_MSG_LINK, "phy link down\n"); 5610 5611 vars->phy_link_up = 0; 5612 5613 vars->duplex = DUPLEX_FULL; 5614 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; 5615 vars->mac_type = MAC_TYPE_NONE; 5616 } 5617 DP(NETIF_MSG_LINK, " phy_link_up %x line_speed %d\n", 5618 vars->phy_link_up, vars->line_speed); 5619 return 0; 5620 } 5621 5622 static int bnx2x_link_settings_status(struct bnx2x_phy *phy, 5623 struct link_params *params, 5624 struct link_vars *vars) 5625 { 5626 struct bnx2x *bp = params->bp; 5627 5628 u16 gp_status, duplex = DUPLEX_HALF, link_up = 0, speed_mask; 5629 int rc = 0; 5630 5631 /* Read gp_status */ 5632 CL22_RD_OVER_CL45(bp, phy, 5633 MDIO_REG_BANK_GP_STATUS, 5634 MDIO_GP_STATUS_TOP_AN_STATUS1, 5635 &gp_status); 5636 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS) 5637 duplex = DUPLEX_FULL; 5638 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) 5639 link_up = 1; 5640 speed_mask = gp_status & GP_STATUS_SPEED_MASK; 5641 DP(NETIF_MSG_LINK, "gp_status 0x%x, is_link_up %d, speed_mask 0x%x\n", 5642 gp_status, link_up, speed_mask); 5643 rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, speed_mask, 5644 duplex); 5645 if (rc == -EINVAL) 5646 return rc; 5647 5648 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) { 5649 if (SINGLE_MEDIA_DIRECT(params)) { 5650 vars->duplex = duplex; 5651 bnx2x_flow_ctrl_resolve(phy, params, vars, gp_status); 5652 if (phy->req_line_speed == SPEED_AUTO_NEG) 5653 bnx2x_xgxs_an_resolve(phy, params, vars, 5654 gp_status); 5655 } 5656 } else { /* Link_down */ 5657 if ((phy->req_line_speed == SPEED_AUTO_NEG) && 5658 SINGLE_MEDIA_DIRECT(params)) { 5659 /* Check signal is detected */ 5660 bnx2x_check_fallback_to_cl37(phy, params); 5661 } 5662 } 5663 5664 /* Read LP advertised speeds*/ 5665 if (SINGLE_MEDIA_DIRECT(params) && 5666 (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)) { 5667 u16 val; 5668 5669 CL22_RD_OVER_CL45(bp, phy, MDIO_REG_BANK_CL73_IEEEB1, 5670 MDIO_CL73_IEEEB1_AN_LP_ADV2, &val); 5671 5672 if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX) 5673 vars->link_status |= 5674 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; 5675 if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 | 5676 MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR)) 5677 vars->link_status |= 5678 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; 5679 5680 CL22_RD_OVER_CL45(bp, phy, MDIO_REG_BANK_OVER_1G, 5681 MDIO_OVER_1G_LP_UP1, &val); 5682 5683 if (val & MDIO_OVER_1G_UP1_2_5G) 5684 vars->link_status |= 5685 LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE; 5686 if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH)) 5687 vars->link_status |= 5688 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; 5689 } 5690 5691 DP(NETIF_MSG_LINK, "duplex %x flow_ctrl 0x%x link_status 0x%x\n", 5692 vars->duplex, vars->flow_ctrl, vars->link_status); 5693 return rc; 5694 } 5695 5696 static int bnx2x_warpcore_read_status(struct bnx2x_phy *phy, 5697 struct link_params *params, 5698 struct link_vars *vars) 5699 { 5700 struct bnx2x *bp = params->bp; 5701 u8 lane; 5702 u16 gp_status1, gp_speed, link_up, duplex = DUPLEX_FULL; 5703 int rc = 0; 5704 lane = bnx2x_get_warpcore_lane(phy, params); 5705 /* Read gp_status */ 5706 if ((params->loopback_mode) && 5707 (phy->flags & FLAGS_WC_DUAL_MODE)) { 5708 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 5709 MDIO_WC_REG_DIGITAL5_LINK_STATUS, &link_up); 5710 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 5711 MDIO_WC_REG_DIGITAL5_LINK_STATUS, &link_up); 5712 link_up &= 0x1; 5713 } else if ((phy->req_line_speed > SPEED_10000) && 5714 (phy->supported & SUPPORTED_20000baseMLD2_Full)) { 5715 u16 temp_link_up; 5716 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 5717 1, &temp_link_up); 5718 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 5719 1, &link_up); 5720 DP(NETIF_MSG_LINK, "PCS RX link status = 0x%x-->0x%x\n", 5721 temp_link_up, link_up); 5722 link_up &= (1<<2); 5723 if (link_up) 5724 bnx2x_ext_phy_resolve_fc(phy, params, vars); 5725 } else { 5726 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 5727 MDIO_WC_REG_GP2_STATUS_GP_2_1, 5728 &gp_status1); 5729 DP(NETIF_MSG_LINK, "0x81d1 = 0x%x\n", gp_status1); 5730 /* Check for either KR, 1G, or AN up. */ 5731 link_up = ((gp_status1 >> 8) | 5732 (gp_status1 >> 12) | 5733 (gp_status1)) & 5734 (1 << lane); 5735 if (phy->supported & SUPPORTED_20000baseKR2_Full) { 5736 u16 an_link; 5737 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, 5738 MDIO_AN_REG_STATUS, &an_link); 5739 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, 5740 MDIO_AN_REG_STATUS, &an_link); 5741 link_up |= (an_link & (1<<2)); 5742 } 5743 if (link_up && SINGLE_MEDIA_DIRECT(params)) { 5744 u16 pd, gp_status4; 5745 if (phy->req_line_speed == SPEED_AUTO_NEG) { 5746 /* Check Autoneg complete */ 5747 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 5748 MDIO_WC_REG_GP2_STATUS_GP_2_4, 5749 &gp_status4); 5750 if (gp_status4 & ((1<<12)<<lane)) 5751 vars->link_status |= 5752 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; 5753 5754 /* Check parallel detect used */ 5755 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 5756 MDIO_WC_REG_PAR_DET_10G_STATUS, 5757 &pd); 5758 if (pd & (1<<15)) 5759 vars->link_status |= 5760 LINK_STATUS_PARALLEL_DETECTION_USED; 5761 } 5762 bnx2x_ext_phy_resolve_fc(phy, params, vars); 5763 vars->duplex = duplex; 5764 } 5765 } 5766 5767 if ((vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) && 5768 SINGLE_MEDIA_DIRECT(params)) { 5769 u16 val; 5770 5771 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, 5772 MDIO_AN_REG_LP_AUTO_NEG2, &val); 5773 5774 if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX) 5775 vars->link_status |= 5776 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; 5777 if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 | 5778 MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR)) 5779 vars->link_status |= 5780 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; 5781 5782 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 5783 MDIO_WC_REG_DIGITAL3_LP_UP1, &val); 5784 5785 if (val & MDIO_OVER_1G_UP1_2_5G) 5786 vars->link_status |= 5787 LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE; 5788 if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH)) 5789 vars->link_status |= 5790 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; 5791 5792 } 5793 5794 5795 if (lane < 2) { 5796 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 5797 MDIO_WC_REG_GP2_STATUS_GP_2_2, &gp_speed); 5798 } else { 5799 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 5800 MDIO_WC_REG_GP2_STATUS_GP_2_3, &gp_speed); 5801 } 5802 DP(NETIF_MSG_LINK, "lane %d gp_speed 0x%x\n", lane, gp_speed); 5803 5804 if ((lane & 1) == 0) 5805 gp_speed <<= 8; 5806 gp_speed &= 0x3f00; 5807 link_up = !!link_up; 5808 5809 rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, gp_speed, 5810 duplex); 5811 5812 /* In case of KR link down, start up the recovering procedure */ 5813 if ((!link_up) && (phy->media_type == ETH_PHY_KR) && 5814 (!(phy->flags & FLAGS_WC_DUAL_MODE))) 5815 vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY; 5816 5817 DP(NETIF_MSG_LINK, "duplex %x flow_ctrl 0x%x link_status 0x%x\n", 5818 vars->duplex, vars->flow_ctrl, vars->link_status); 5819 return rc; 5820 } 5821 static void bnx2x_set_gmii_tx_driver(struct link_params *params) 5822 { 5823 struct bnx2x *bp = params->bp; 5824 struct bnx2x_phy *phy = ¶ms->phy[INT_PHY]; 5825 u16 lp_up2; 5826 u16 tx_driver; 5827 u16 bank; 5828 5829 /* Read precomp */ 5830 CL22_RD_OVER_CL45(bp, phy, 5831 MDIO_REG_BANK_OVER_1G, 5832 MDIO_OVER_1G_LP_UP2, &lp_up2); 5833 5834 /* Bits [10:7] at lp_up2, positioned at [15:12] */ 5835 lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >> 5836 MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) << 5837 MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT); 5838 5839 if (lp_up2 == 0) 5840 return; 5841 5842 for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3; 5843 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) { 5844 CL22_RD_OVER_CL45(bp, phy, 5845 bank, 5846 MDIO_TX0_TX_DRIVER, &tx_driver); 5847 5848 /* Replace tx_driver bits [15:12] */ 5849 if (lp_up2 != 5850 (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) { 5851 tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK; 5852 tx_driver |= lp_up2; 5853 CL22_WR_OVER_CL45(bp, phy, 5854 bank, 5855 MDIO_TX0_TX_DRIVER, tx_driver); 5856 } 5857 } 5858 } 5859 5860 static int bnx2x_emac_program(struct link_params *params, 5861 struct link_vars *vars) 5862 { 5863 struct bnx2x *bp = params->bp; 5864 u8 port = params->port; 5865 u16 mode = 0; 5866 5867 DP(NETIF_MSG_LINK, "setting link speed & duplex\n"); 5868 bnx2x_bits_dis(bp, GRCBASE_EMAC0 + port*0x400 + 5869 EMAC_REG_EMAC_MODE, 5870 (EMAC_MODE_25G_MODE | 5871 EMAC_MODE_PORT_MII_10M | 5872 EMAC_MODE_HALF_DUPLEX)); 5873 switch (vars->line_speed) { 5874 case SPEED_10: 5875 mode |= EMAC_MODE_PORT_MII_10M; 5876 break; 5877 5878 case SPEED_100: 5879 mode |= EMAC_MODE_PORT_MII; 5880 break; 5881 5882 case SPEED_1000: 5883 mode |= EMAC_MODE_PORT_GMII; 5884 break; 5885 5886 case SPEED_2500: 5887 mode |= (EMAC_MODE_25G_MODE | EMAC_MODE_PORT_GMII); 5888 break; 5889 5890 default: 5891 /* 10G not valid for EMAC */ 5892 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n", 5893 vars->line_speed); 5894 return -EINVAL; 5895 } 5896 5897 if (vars->duplex == DUPLEX_HALF) 5898 mode |= EMAC_MODE_HALF_DUPLEX; 5899 bnx2x_bits_en(bp, 5900 GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE, 5901 mode); 5902 5903 bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed); 5904 return 0; 5905 } 5906 5907 static void bnx2x_set_preemphasis(struct bnx2x_phy *phy, 5908 struct link_params *params) 5909 { 5910 5911 u16 bank, i = 0; 5912 struct bnx2x *bp = params->bp; 5913 5914 for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3; 5915 bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0), i++) { 5916 CL22_WR_OVER_CL45(bp, phy, 5917 bank, 5918 MDIO_RX0_RX_EQ_BOOST, 5919 phy->rx_preemphasis[i]); 5920 } 5921 5922 for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3; 5923 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) { 5924 CL22_WR_OVER_CL45(bp, phy, 5925 bank, 5926 MDIO_TX0_TX_DRIVER, 5927 phy->tx_preemphasis[i]); 5928 } 5929 } 5930 5931 static void bnx2x_xgxs_config_init(struct bnx2x_phy *phy, 5932 struct link_params *params, 5933 struct link_vars *vars) 5934 { 5935 struct bnx2x *bp = params->bp; 5936 u8 enable_cl73 = (SINGLE_MEDIA_DIRECT(params) || 5937 (params->loopback_mode == LOOPBACK_XGXS)); 5938 if (!(vars->phy_flags & PHY_SGMII_FLAG)) { 5939 if (SINGLE_MEDIA_DIRECT(params) && 5940 (params->feature_config_flags & 5941 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) 5942 bnx2x_set_preemphasis(phy, params); 5943 5944 /* Forced speed requested? */ 5945 if (vars->line_speed != SPEED_AUTO_NEG || 5946 (SINGLE_MEDIA_DIRECT(params) && 5947 params->loopback_mode == LOOPBACK_EXT)) { 5948 DP(NETIF_MSG_LINK, "not SGMII, no AN\n"); 5949 5950 /* Disable autoneg */ 5951 bnx2x_set_autoneg(phy, params, vars, 0); 5952 5953 /* Program speed and duplex */ 5954 bnx2x_program_serdes(phy, params, vars); 5955 5956 } else { /* AN_mode */ 5957 DP(NETIF_MSG_LINK, "not SGMII, AN\n"); 5958 5959 /* AN enabled */ 5960 bnx2x_set_brcm_cl37_advertisement(phy, params); 5961 5962 /* Program duplex & pause advertisement (for aneg) */ 5963 bnx2x_set_ieee_aneg_advertisement(phy, params, 5964 vars->ieee_fc); 5965 5966 /* Enable autoneg */ 5967 bnx2x_set_autoneg(phy, params, vars, enable_cl73); 5968 5969 /* Enable and restart AN */ 5970 bnx2x_restart_autoneg(phy, params, enable_cl73); 5971 } 5972 5973 } else { /* SGMII mode */ 5974 DP(NETIF_MSG_LINK, "SGMII\n"); 5975 5976 bnx2x_initialize_sgmii_process(phy, params, vars); 5977 } 5978 } 5979 5980 static int bnx2x_prepare_xgxs(struct bnx2x_phy *phy, 5981 struct link_params *params, 5982 struct link_vars *vars) 5983 { 5984 int rc; 5985 vars->phy_flags |= PHY_XGXS_FLAG; 5986 if ((phy->req_line_speed && 5987 ((phy->req_line_speed == SPEED_100) || 5988 (phy->req_line_speed == SPEED_10))) || 5989 (!phy->req_line_speed && 5990 (phy->speed_cap_mask >= 5991 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) && 5992 (phy->speed_cap_mask < 5993 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) || 5994 (phy->type == PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD)) 5995 vars->phy_flags |= PHY_SGMII_FLAG; 5996 else 5997 vars->phy_flags &= ~PHY_SGMII_FLAG; 5998 5999 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); 6000 bnx2x_set_aer_mmd(params, phy); 6001 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) 6002 bnx2x_set_master_ln(params, phy); 6003 6004 rc = bnx2x_reset_unicore(params, phy, 0); 6005 /* Reset the SerDes and wait for reset bit return low */ 6006 if (rc) 6007 return rc; 6008 6009 bnx2x_set_aer_mmd(params, phy); 6010 /* Setting the masterLn_def again after the reset */ 6011 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) { 6012 bnx2x_set_master_ln(params, phy); 6013 bnx2x_set_swap_lanes(params, phy); 6014 } 6015 6016 return rc; 6017 } 6018 6019 static u16 bnx2x_wait_reset_complete(struct bnx2x *bp, 6020 struct bnx2x_phy *phy, 6021 struct link_params *params) 6022 { 6023 u16 cnt, ctrl; 6024 /* Wait for soft reset to get cleared up to 1 sec */ 6025 for (cnt = 0; cnt < 1000; cnt++) { 6026 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) 6027 bnx2x_cl22_read(bp, phy, 6028 MDIO_PMA_REG_CTRL, &ctrl); 6029 else 6030 bnx2x_cl45_read(bp, phy, 6031 MDIO_PMA_DEVAD, 6032 MDIO_PMA_REG_CTRL, &ctrl); 6033 if (!(ctrl & (1<<15))) 6034 break; 6035 usleep_range(1000, 2000); 6036 } 6037 6038 if (cnt == 1000) 6039 netdev_err(bp->dev, "Warning: PHY was not initialized," 6040 " Port %d\n", 6041 params->port); 6042 DP(NETIF_MSG_LINK, "control reg 0x%x (after %d ms)\n", ctrl, cnt); 6043 return cnt; 6044 } 6045 6046 static void bnx2x_link_int_enable(struct link_params *params) 6047 { 6048 u8 port = params->port; 6049 u32 mask; 6050 struct bnx2x *bp = params->bp; 6051 6052 /* Setting the status to report on link up for either XGXS or SerDes */ 6053 if (CHIP_IS_E3(bp)) { 6054 mask = NIG_MASK_XGXS0_LINK_STATUS; 6055 if (!(SINGLE_MEDIA_DIRECT(params))) 6056 mask |= NIG_MASK_MI_INT; 6057 } else if (params->switch_cfg == SWITCH_CFG_10G) { 6058 mask = (NIG_MASK_XGXS0_LINK10G | 6059 NIG_MASK_XGXS0_LINK_STATUS); 6060 DP(NETIF_MSG_LINK, "enabled XGXS interrupt\n"); 6061 if (!(SINGLE_MEDIA_DIRECT(params)) && 6062 params->phy[INT_PHY].type != 6063 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) { 6064 mask |= NIG_MASK_MI_INT; 6065 DP(NETIF_MSG_LINK, "enabled external phy int\n"); 6066 } 6067 6068 } else { /* SerDes */ 6069 mask = NIG_MASK_SERDES0_LINK_STATUS; 6070 DP(NETIF_MSG_LINK, "enabled SerDes interrupt\n"); 6071 if (!(SINGLE_MEDIA_DIRECT(params)) && 6072 params->phy[INT_PHY].type != 6073 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN) { 6074 mask |= NIG_MASK_MI_INT; 6075 DP(NETIF_MSG_LINK, "enabled external phy int\n"); 6076 } 6077 } 6078 bnx2x_bits_en(bp, 6079 NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 6080 mask); 6081 6082 DP(NETIF_MSG_LINK, "port %x, is_xgxs %x, int_status 0x%x\n", port, 6083 (params->switch_cfg == SWITCH_CFG_10G), 6084 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4)); 6085 DP(NETIF_MSG_LINK, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x\n", 6086 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4), 6087 REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18), 6088 REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS+port*0x3c)); 6089 DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n", 6090 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68), 6091 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68)); 6092 } 6093 6094 static void bnx2x_rearm_latch_signal(struct bnx2x *bp, u8 port, 6095 u8 exp_mi_int) 6096 { 6097 u32 latch_status = 0; 6098 6099 /* Disable the MI INT ( external phy int ) by writing 1 to the 6100 * status register. Link down indication is high-active-signal, 6101 * so in this case we need to write the status to clear the XOR 6102 */ 6103 /* Read Latched signals */ 6104 latch_status = REG_RD(bp, 6105 NIG_REG_LATCH_STATUS_0 + port*8); 6106 DP(NETIF_MSG_LINK, "latch_status = 0x%x\n", latch_status); 6107 /* Handle only those with latched-signal=up.*/ 6108 if (exp_mi_int) 6109 bnx2x_bits_en(bp, 6110 NIG_REG_STATUS_INTERRUPT_PORT0 6111 + port*4, 6112 NIG_STATUS_EMAC0_MI_INT); 6113 else 6114 bnx2x_bits_dis(bp, 6115 NIG_REG_STATUS_INTERRUPT_PORT0 6116 + port*4, 6117 NIG_STATUS_EMAC0_MI_INT); 6118 6119 if (latch_status & 1) { 6120 6121 /* For all latched-signal=up : Re-Arm Latch signals */ 6122 REG_WR(bp, NIG_REG_LATCH_STATUS_0 + port*8, 6123 (latch_status & 0xfffe) | (latch_status & 1)); 6124 } 6125 /* For all latched-signal=up,Write original_signal to status */ 6126 } 6127 6128 static void bnx2x_link_int_ack(struct link_params *params, 6129 struct link_vars *vars, u8 is_10g_plus) 6130 { 6131 struct bnx2x *bp = params->bp; 6132 u8 port = params->port; 6133 u32 mask; 6134 /* First reset all status we assume only one line will be 6135 * change at a time 6136 */ 6137 bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4, 6138 (NIG_STATUS_XGXS0_LINK10G | 6139 NIG_STATUS_XGXS0_LINK_STATUS | 6140 NIG_STATUS_SERDES0_LINK_STATUS)); 6141 if (vars->phy_link_up) { 6142 if (USES_WARPCORE(bp)) 6143 mask = NIG_STATUS_XGXS0_LINK_STATUS; 6144 else { 6145 if (is_10g_plus) 6146 mask = NIG_STATUS_XGXS0_LINK10G; 6147 else if (params->switch_cfg == SWITCH_CFG_10G) { 6148 /* Disable the link interrupt by writing 1 to 6149 * the relevant lane in the status register 6150 */ 6151 u32 ser_lane = 6152 ((params->lane_config & 6153 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >> 6154 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT); 6155 mask = ((1 << ser_lane) << 6156 NIG_STATUS_XGXS0_LINK_STATUS_SIZE); 6157 } else 6158 mask = NIG_STATUS_SERDES0_LINK_STATUS; 6159 } 6160 DP(NETIF_MSG_LINK, "Ack link up interrupt with mask 0x%x\n", 6161 mask); 6162 bnx2x_bits_en(bp, 6163 NIG_REG_STATUS_INTERRUPT_PORT0 + port*4, 6164 mask); 6165 } 6166 } 6167 6168 static int bnx2x_format_ver(u32 num, u8 *str, u16 *len) 6169 { 6170 u8 *str_ptr = str; 6171 u32 mask = 0xf0000000; 6172 u8 shift = 8*4; 6173 u8 digit; 6174 u8 remove_leading_zeros = 1; 6175 if (*len < 10) { 6176 /* Need more than 10chars for this format */ 6177 *str_ptr = '\0'; 6178 (*len)--; 6179 return -EINVAL; 6180 } 6181 while (shift > 0) { 6182 6183 shift -= 4; 6184 digit = ((num & mask) >> shift); 6185 if (digit == 0 && remove_leading_zeros) { 6186 mask = mask >> 4; 6187 continue; 6188 } else if (digit < 0xa) 6189 *str_ptr = digit + '0'; 6190 else 6191 *str_ptr = digit - 0xa + 'a'; 6192 remove_leading_zeros = 0; 6193 str_ptr++; 6194 (*len)--; 6195 mask = mask >> 4; 6196 if (shift == 4*4) { 6197 *str_ptr = '.'; 6198 str_ptr++; 6199 (*len)--; 6200 remove_leading_zeros = 1; 6201 } 6202 } 6203 return 0; 6204 } 6205 6206 6207 static int bnx2x_null_format_ver(u32 spirom_ver, u8 *str, u16 *len) 6208 { 6209 str[0] = '\0'; 6210 (*len)--; 6211 return 0; 6212 } 6213 6214 int bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 *version, 6215 u16 len) 6216 { 6217 struct bnx2x *bp; 6218 u32 spirom_ver = 0; 6219 int status = 0; 6220 u8 *ver_p = version; 6221 u16 remain_len = len; 6222 if (version == NULL || params == NULL) 6223 return -EINVAL; 6224 bp = params->bp; 6225 6226 /* Extract first external phy*/ 6227 version[0] = '\0'; 6228 spirom_ver = REG_RD(bp, params->phy[EXT_PHY1].ver_addr); 6229 6230 if (params->phy[EXT_PHY1].format_fw_ver) { 6231 status |= params->phy[EXT_PHY1].format_fw_ver(spirom_ver, 6232 ver_p, 6233 &remain_len); 6234 ver_p += (len - remain_len); 6235 } 6236 if ((params->num_phys == MAX_PHYS) && 6237 (params->phy[EXT_PHY2].ver_addr != 0)) { 6238 spirom_ver = REG_RD(bp, params->phy[EXT_PHY2].ver_addr); 6239 if (params->phy[EXT_PHY2].format_fw_ver) { 6240 *ver_p = '/'; 6241 ver_p++; 6242 remain_len--; 6243 status |= params->phy[EXT_PHY2].format_fw_ver( 6244 spirom_ver, 6245 ver_p, 6246 &remain_len); 6247 ver_p = version + (len - remain_len); 6248 } 6249 } 6250 *ver_p = '\0'; 6251 return status; 6252 } 6253 6254 static void bnx2x_set_xgxs_loopback(struct bnx2x_phy *phy, 6255 struct link_params *params) 6256 { 6257 u8 port = params->port; 6258 struct bnx2x *bp = params->bp; 6259 6260 if (phy->req_line_speed != SPEED_1000) { 6261 u32 md_devad = 0; 6262 6263 DP(NETIF_MSG_LINK, "XGXS 10G loopback enable\n"); 6264 6265 if (!CHIP_IS_E3(bp)) { 6266 /* Change the uni_phy_addr in the nig */ 6267 md_devad = REG_RD(bp, (NIG_REG_XGXS0_CTRL_MD_DEVAD + 6268 port*0x18)); 6269 6270 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, 6271 0x5); 6272 } 6273 6274 bnx2x_cl45_write(bp, phy, 6275 5, 6276 (MDIO_REG_BANK_AER_BLOCK + 6277 (MDIO_AER_BLOCK_AER_REG & 0xf)), 6278 0x2800); 6279 6280 bnx2x_cl45_write(bp, phy, 6281 5, 6282 (MDIO_REG_BANK_CL73_IEEEB0 + 6283 (MDIO_CL73_IEEEB0_CL73_AN_CONTROL & 0xf)), 6284 0x6041); 6285 msleep(200); 6286 /* Set aer mmd back */ 6287 bnx2x_set_aer_mmd(params, phy); 6288 6289 if (!CHIP_IS_E3(bp)) { 6290 /* And md_devad */ 6291 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, 6292 md_devad); 6293 } 6294 } else { 6295 u16 mii_ctrl; 6296 DP(NETIF_MSG_LINK, "XGXS 1G loopback enable\n"); 6297 bnx2x_cl45_read(bp, phy, 5, 6298 (MDIO_REG_BANK_COMBO_IEEE0 + 6299 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)), 6300 &mii_ctrl); 6301 bnx2x_cl45_write(bp, phy, 5, 6302 (MDIO_REG_BANK_COMBO_IEEE0 + 6303 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)), 6304 mii_ctrl | 6305 MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK); 6306 } 6307 } 6308 6309 int bnx2x_set_led(struct link_params *params, 6310 struct link_vars *vars, u8 mode, u32 speed) 6311 { 6312 u8 port = params->port; 6313 u16 hw_led_mode = params->hw_led_mode; 6314 int rc = 0; 6315 u8 phy_idx; 6316 u32 tmp; 6317 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; 6318 struct bnx2x *bp = params->bp; 6319 DP(NETIF_MSG_LINK, "bnx2x_set_led: port %x, mode %d\n", port, mode); 6320 DP(NETIF_MSG_LINK, "speed 0x%x, hw_led_mode 0x%x\n", 6321 speed, hw_led_mode); 6322 /* In case */ 6323 for (phy_idx = EXT_PHY1; phy_idx < MAX_PHYS; phy_idx++) { 6324 if (params->phy[phy_idx].set_link_led) { 6325 params->phy[phy_idx].set_link_led( 6326 ¶ms->phy[phy_idx], params, mode); 6327 } 6328 } 6329 6330 switch (mode) { 6331 case LED_MODE_FRONT_PANEL_OFF: 6332 case LED_MODE_OFF: 6333 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 0); 6334 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 6335 SHARED_HW_CFG_LED_MAC1); 6336 6337 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED); 6338 if (params->phy[EXT_PHY1].type == 6339 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) 6340 tmp &= ~(EMAC_LED_1000MB_OVERRIDE | 6341 EMAC_LED_100MB_OVERRIDE | 6342 EMAC_LED_10MB_OVERRIDE); 6343 else 6344 tmp |= EMAC_LED_OVERRIDE; 6345 6346 EMAC_WR(bp, EMAC_REG_EMAC_LED, tmp); 6347 break; 6348 6349 case LED_MODE_OPER: 6350 /* For all other phys, OPER mode is same as ON, so in case 6351 * link is down, do nothing 6352 */ 6353 if (!vars->link_up) 6354 break; 6355 case LED_MODE_ON: 6356 if (((params->phy[EXT_PHY1].type == 6357 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) || 6358 (params->phy[EXT_PHY1].type == 6359 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722)) && 6360 CHIP_IS_E2(bp) && params->num_phys == 2) { 6361 /* This is a work-around for E2+8727 Configurations */ 6362 if (mode == LED_MODE_ON || 6363 speed == SPEED_10000){ 6364 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0); 6365 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1); 6366 6367 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED); 6368 EMAC_WR(bp, EMAC_REG_EMAC_LED, 6369 (tmp | EMAC_LED_OVERRIDE)); 6370 /* Return here without enabling traffic 6371 * LED blink and setting rate in ON mode. 6372 * In oper mode, enabling LED blink 6373 * and setting rate is needed. 6374 */ 6375 if (mode == LED_MODE_ON) 6376 return rc; 6377 } 6378 } else if (SINGLE_MEDIA_DIRECT(params)) { 6379 /* This is a work-around for HW issue found when link 6380 * is up in CL73 6381 */ 6382 if ((!CHIP_IS_E3(bp)) || 6383 (CHIP_IS_E3(bp) && 6384 mode == LED_MODE_ON)) 6385 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1); 6386 6387 if (CHIP_IS_E1x(bp) || 6388 CHIP_IS_E2(bp) || 6389 (mode == LED_MODE_ON)) 6390 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0); 6391 else 6392 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 6393 hw_led_mode); 6394 } else if ((params->phy[EXT_PHY1].type == 6395 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) && 6396 (mode == LED_MODE_ON)) { 6397 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0); 6398 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED); 6399 EMAC_WR(bp, EMAC_REG_EMAC_LED, tmp | 6400 EMAC_LED_OVERRIDE | EMAC_LED_1000MB_OVERRIDE); 6401 /* Break here; otherwise, it'll disable the 6402 * intended override. 6403 */ 6404 break; 6405 } else { 6406 u32 nig_led_mode = ((params->hw_led_mode << 6407 SHARED_HW_CFG_LED_MODE_SHIFT) == 6408 SHARED_HW_CFG_LED_EXTPHY2) ? 6409 (SHARED_HW_CFG_LED_PHY1 >> 6410 SHARED_HW_CFG_LED_MODE_SHIFT) : hw_led_mode; 6411 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 6412 nig_led_mode); 6413 } 6414 6415 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 0); 6416 /* Set blinking rate to ~15.9Hz */ 6417 if (CHIP_IS_E3(bp)) 6418 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4, 6419 LED_BLINK_RATE_VAL_E3); 6420 else 6421 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4, 6422 LED_BLINK_RATE_VAL_E1X_E2); 6423 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 + 6424 port*4, 1); 6425 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED); 6426 EMAC_WR(bp, EMAC_REG_EMAC_LED, 6427 (tmp & (~EMAC_LED_OVERRIDE))); 6428 6429 if (CHIP_IS_E1(bp) && 6430 ((speed == SPEED_2500) || 6431 (speed == SPEED_1000) || 6432 (speed == SPEED_100) || 6433 (speed == SPEED_10))) { 6434 /* For speeds less than 10G LED scheme is different */ 6435 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 6436 + port*4, 1); 6437 REG_WR(bp, NIG_REG_LED_CONTROL_TRAFFIC_P0 + 6438 port*4, 0); 6439 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 + 6440 port*4, 1); 6441 } 6442 break; 6443 6444 default: 6445 rc = -EINVAL; 6446 DP(NETIF_MSG_LINK, "bnx2x_set_led: Invalid led mode %d\n", 6447 mode); 6448 break; 6449 } 6450 return rc; 6451 6452 } 6453 6454 /* This function comes to reflect the actual link state read DIRECTLY from the 6455 * HW 6456 */ 6457 int bnx2x_test_link(struct link_params *params, struct link_vars *vars, 6458 u8 is_serdes) 6459 { 6460 struct bnx2x *bp = params->bp; 6461 u16 gp_status = 0, phy_index = 0; 6462 u8 ext_phy_link_up = 0, serdes_phy_type; 6463 struct link_vars temp_vars; 6464 struct bnx2x_phy *int_phy = ¶ms->phy[INT_PHY]; 6465 6466 if (CHIP_IS_E3(bp)) { 6467 u16 link_up; 6468 if (params->req_line_speed[LINK_CONFIG_IDX(INT_PHY)] 6469 > SPEED_10000) { 6470 /* Check 20G link */ 6471 bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD, 6472 1, &link_up); 6473 bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD, 6474 1, &link_up); 6475 link_up &= (1<<2); 6476 } else { 6477 /* Check 10G link and below*/ 6478 u8 lane = bnx2x_get_warpcore_lane(int_phy, params); 6479 bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD, 6480 MDIO_WC_REG_GP2_STATUS_GP_2_1, 6481 &gp_status); 6482 gp_status = ((gp_status >> 8) & 0xf) | 6483 ((gp_status >> 12) & 0xf); 6484 link_up = gp_status & (1 << lane); 6485 } 6486 if (!link_up) 6487 return -ESRCH; 6488 } else { 6489 CL22_RD_OVER_CL45(bp, int_phy, 6490 MDIO_REG_BANK_GP_STATUS, 6491 MDIO_GP_STATUS_TOP_AN_STATUS1, 6492 &gp_status); 6493 /* Link is up only if both local phy and external phy are up */ 6494 if (!(gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS)) 6495 return -ESRCH; 6496 } 6497 /* In XGXS loopback mode, do not check external PHY */ 6498 if (params->loopback_mode == LOOPBACK_XGXS) 6499 return 0; 6500 6501 switch (params->num_phys) { 6502 case 1: 6503 /* No external PHY */ 6504 return 0; 6505 case 2: 6506 ext_phy_link_up = params->phy[EXT_PHY1].read_status( 6507 ¶ms->phy[EXT_PHY1], 6508 params, &temp_vars); 6509 break; 6510 case 3: /* Dual Media */ 6511 for (phy_index = EXT_PHY1; phy_index < params->num_phys; 6512 phy_index++) { 6513 serdes_phy_type = ((params->phy[phy_index].media_type == 6514 ETH_PHY_SFPP_10G_FIBER) || 6515 (params->phy[phy_index].media_type == 6516 ETH_PHY_SFP_1G_FIBER) || 6517 (params->phy[phy_index].media_type == 6518 ETH_PHY_XFP_FIBER) || 6519 (params->phy[phy_index].media_type == 6520 ETH_PHY_DA_TWINAX)); 6521 6522 if (is_serdes != serdes_phy_type) 6523 continue; 6524 if (params->phy[phy_index].read_status) { 6525 ext_phy_link_up |= 6526 params->phy[phy_index].read_status( 6527 ¶ms->phy[phy_index], 6528 params, &temp_vars); 6529 } 6530 } 6531 break; 6532 } 6533 if (ext_phy_link_up) 6534 return 0; 6535 return -ESRCH; 6536 } 6537 6538 static int bnx2x_link_initialize(struct link_params *params, 6539 struct link_vars *vars) 6540 { 6541 u8 phy_index, non_ext_phy; 6542 struct bnx2x *bp = params->bp; 6543 /* In case of external phy existence, the line speed would be the 6544 * line speed linked up by the external phy. In case it is direct 6545 * only, then the line_speed during initialization will be 6546 * equal to the req_line_speed 6547 */ 6548 vars->line_speed = params->phy[INT_PHY].req_line_speed; 6549 6550 /* Initialize the internal phy in case this is a direct board 6551 * (no external phys), or this board has external phy which requires 6552 * to first. 6553 */ 6554 if (!USES_WARPCORE(bp)) 6555 bnx2x_prepare_xgxs(¶ms->phy[INT_PHY], params, vars); 6556 /* init ext phy and enable link state int */ 6557 non_ext_phy = (SINGLE_MEDIA_DIRECT(params) || 6558 (params->loopback_mode == LOOPBACK_XGXS)); 6559 6560 if (non_ext_phy || 6561 (params->phy[EXT_PHY1].flags & FLAGS_INIT_XGXS_FIRST) || 6562 (params->loopback_mode == LOOPBACK_EXT_PHY)) { 6563 struct bnx2x_phy *phy = ¶ms->phy[INT_PHY]; 6564 if (vars->line_speed == SPEED_AUTO_NEG && 6565 (CHIP_IS_E1x(bp) || 6566 CHIP_IS_E2(bp))) 6567 bnx2x_set_parallel_detection(phy, params); 6568 if (params->phy[INT_PHY].config_init) 6569 params->phy[INT_PHY].config_init(phy, params, vars); 6570 } 6571 6572 /* Re-read this value in case it was changed inside config_init due to 6573 * limitations of optic module 6574 */ 6575 vars->line_speed = params->phy[INT_PHY].req_line_speed; 6576 6577 /* Init external phy*/ 6578 if (non_ext_phy) { 6579 if (params->phy[INT_PHY].supported & 6580 SUPPORTED_FIBRE) 6581 vars->link_status |= LINK_STATUS_SERDES_LINK; 6582 } else { 6583 for (phy_index = EXT_PHY1; phy_index < params->num_phys; 6584 phy_index++) { 6585 /* No need to initialize second phy in case of first 6586 * phy only selection. In case of second phy, we do 6587 * need to initialize the first phy, since they are 6588 * connected. 6589 */ 6590 if (params->phy[phy_index].supported & 6591 SUPPORTED_FIBRE) 6592 vars->link_status |= LINK_STATUS_SERDES_LINK; 6593 6594 if (phy_index == EXT_PHY2 && 6595 (bnx2x_phy_selection(params) == 6596 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY)) { 6597 DP(NETIF_MSG_LINK, 6598 "Not initializing second phy\n"); 6599 continue; 6600 } 6601 params->phy[phy_index].config_init( 6602 ¶ms->phy[phy_index], 6603 params, vars); 6604 } 6605 } 6606 /* Reset the interrupt indication after phy was initialized */ 6607 bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + 6608 params->port*4, 6609 (NIG_STATUS_XGXS0_LINK10G | 6610 NIG_STATUS_XGXS0_LINK_STATUS | 6611 NIG_STATUS_SERDES0_LINK_STATUS | 6612 NIG_MASK_MI_INT)); 6613 return 0; 6614 } 6615 6616 static void bnx2x_int_link_reset(struct bnx2x_phy *phy, 6617 struct link_params *params) 6618 { 6619 /* Reset the SerDes/XGXS */ 6620 REG_WR(params->bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, 6621 (0x1ff << (params->port*16))); 6622 } 6623 6624 static void bnx2x_common_ext_link_reset(struct bnx2x_phy *phy, 6625 struct link_params *params) 6626 { 6627 struct bnx2x *bp = params->bp; 6628 u8 gpio_port; 6629 /* HW reset */ 6630 if (CHIP_IS_E2(bp)) 6631 gpio_port = BP_PATH(bp); 6632 else 6633 gpio_port = params->port; 6634 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, 6635 MISC_REGISTERS_GPIO_OUTPUT_LOW, 6636 gpio_port); 6637 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 6638 MISC_REGISTERS_GPIO_OUTPUT_LOW, 6639 gpio_port); 6640 DP(NETIF_MSG_LINK, "reset external PHY\n"); 6641 } 6642 6643 static int bnx2x_update_link_down(struct link_params *params, 6644 struct link_vars *vars) 6645 { 6646 struct bnx2x *bp = params->bp; 6647 u8 port = params->port; 6648 6649 DP(NETIF_MSG_LINK, "Port %x: Link is down\n", port); 6650 bnx2x_set_led(params, vars, LED_MODE_OFF, 0); 6651 vars->phy_flags &= ~PHY_PHYSICAL_LINK_FLAG; 6652 /* Indicate no mac active */ 6653 vars->mac_type = MAC_TYPE_NONE; 6654 6655 /* Update shared memory */ 6656 vars->link_status &= ~LINK_UPDATE_MASK; 6657 vars->line_speed = 0; 6658 bnx2x_update_mng(params, vars->link_status); 6659 6660 /* Activate nig drain */ 6661 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1); 6662 6663 /* Disable emac */ 6664 if (!CHIP_IS_E3(bp)) 6665 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0); 6666 6667 usleep_range(10000, 20000); 6668 /* Reset BigMac/Xmac */ 6669 if (CHIP_IS_E1x(bp) || 6670 CHIP_IS_E2(bp)) 6671 bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 0); 6672 6673 if (CHIP_IS_E3(bp)) { 6674 /* Prevent LPI Generation by chip */ 6675 REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2), 6676 0); 6677 REG_WR(bp, MISC_REG_CPMU_LP_MASK_ENT_P0 + (params->port << 2), 6678 0); 6679 vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK | 6680 SHMEM_EEE_ACTIVE_BIT); 6681 6682 bnx2x_update_mng_eee(params, vars->eee_status); 6683 bnx2x_set_xmac_rxtx(params, 0); 6684 bnx2x_set_umac_rxtx(params, 0); 6685 } 6686 6687 return 0; 6688 } 6689 6690 static int bnx2x_update_link_up(struct link_params *params, 6691 struct link_vars *vars, 6692 u8 link_10g) 6693 { 6694 struct bnx2x *bp = params->bp; 6695 u8 phy_idx, port = params->port; 6696 int rc = 0; 6697 6698 vars->link_status |= (LINK_STATUS_LINK_UP | 6699 LINK_STATUS_PHYSICAL_LINK_FLAG); 6700 vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG; 6701 6702 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) 6703 vars->link_status |= 6704 LINK_STATUS_TX_FLOW_CONTROL_ENABLED; 6705 6706 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX) 6707 vars->link_status |= 6708 LINK_STATUS_RX_FLOW_CONTROL_ENABLED; 6709 if (USES_WARPCORE(bp)) { 6710 if (link_10g) { 6711 if (bnx2x_xmac_enable(params, vars, 0) == 6712 -ESRCH) { 6713 DP(NETIF_MSG_LINK, "Found errors on XMAC\n"); 6714 vars->link_up = 0; 6715 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG; 6716 vars->link_status &= ~LINK_STATUS_LINK_UP; 6717 } 6718 } else 6719 bnx2x_umac_enable(params, vars, 0); 6720 bnx2x_set_led(params, vars, 6721 LED_MODE_OPER, vars->line_speed); 6722 6723 if ((vars->eee_status & SHMEM_EEE_ACTIVE_BIT) && 6724 (vars->eee_status & SHMEM_EEE_LPI_REQUESTED_BIT)) { 6725 DP(NETIF_MSG_LINK, "Enabling LPI assertion\n"); 6726 REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + 6727 (params->port << 2), 1); 6728 REG_WR(bp, MISC_REG_CPMU_LP_DR_ENABLE, 1); 6729 REG_WR(bp, MISC_REG_CPMU_LP_MASK_ENT_P0 + 6730 (params->port << 2), 0xfc20); 6731 } 6732 } 6733 if ((CHIP_IS_E1x(bp) || 6734 CHIP_IS_E2(bp))) { 6735 if (link_10g) { 6736 if (bnx2x_bmac_enable(params, vars, 0, 1) == 6737 -ESRCH) { 6738 DP(NETIF_MSG_LINK, "Found errors on BMAC\n"); 6739 vars->link_up = 0; 6740 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG; 6741 vars->link_status &= ~LINK_STATUS_LINK_UP; 6742 } 6743 6744 bnx2x_set_led(params, vars, 6745 LED_MODE_OPER, SPEED_10000); 6746 } else { 6747 rc = bnx2x_emac_program(params, vars); 6748 bnx2x_emac_enable(params, vars, 0); 6749 6750 /* AN complete? */ 6751 if ((vars->link_status & 6752 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) 6753 && (!(vars->phy_flags & PHY_SGMII_FLAG)) && 6754 SINGLE_MEDIA_DIRECT(params)) 6755 bnx2x_set_gmii_tx_driver(params); 6756 } 6757 } 6758 6759 /* PBF - link up */ 6760 if (CHIP_IS_E1x(bp)) 6761 rc |= bnx2x_pbf_update(params, vars->flow_ctrl, 6762 vars->line_speed); 6763 6764 /* Disable drain */ 6765 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0); 6766 6767 /* Update shared memory */ 6768 bnx2x_update_mng(params, vars->link_status); 6769 bnx2x_update_mng_eee(params, vars->eee_status); 6770 /* Check remote fault */ 6771 for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) { 6772 if (params->phy[phy_idx].flags & FLAGS_TX_ERROR_CHECK) { 6773 bnx2x_check_half_open_conn(params, vars, 0); 6774 break; 6775 } 6776 } 6777 msleep(20); 6778 return rc; 6779 } 6780 6781 static void bnx2x_chng_link_count(struct link_params *params, bool clear) 6782 { 6783 struct bnx2x *bp = params->bp; 6784 u32 addr, val; 6785 6786 /* Verify the link_change_count is supported by the MFW */ 6787 if (!(SHMEM2_HAS(bp, link_change_count))) 6788 return; 6789 6790 addr = params->shmem2_base + 6791 offsetof(struct shmem2_region, link_change_count[params->port]); 6792 if (clear) 6793 val = 0; 6794 else 6795 val = REG_RD(bp, addr) + 1; 6796 REG_WR(bp, addr, val); 6797 } 6798 6799 /* The bnx2x_link_update function should be called upon link 6800 * interrupt. 6801 * Link is considered up as follows: 6802 * - DIRECT_SINGLE_MEDIA - Only XGXS link (internal link) needs 6803 * to be up 6804 * - SINGLE_MEDIA - The link between the 577xx and the external 6805 * phy (XGXS) need to up as well as the external link of the 6806 * phy (PHY_EXT1) 6807 * - DUAL_MEDIA - The link between the 577xx and the first 6808 * external phy needs to be up, and at least one of the 2 6809 * external phy link must be up. 6810 */ 6811 int bnx2x_link_update(struct link_params *params, struct link_vars *vars) 6812 { 6813 struct bnx2x *bp = params->bp; 6814 struct link_vars phy_vars[MAX_PHYS]; 6815 u8 port = params->port; 6816 u8 link_10g_plus, phy_index; 6817 u32 prev_link_status = vars->link_status; 6818 u8 ext_phy_link_up = 0, cur_link_up; 6819 int rc = 0; 6820 u8 is_mi_int = 0; 6821 u16 ext_phy_line_speed = 0, prev_line_speed = vars->line_speed; 6822 u8 active_external_phy = INT_PHY; 6823 vars->phy_flags &= ~PHY_HALF_OPEN_CONN_FLAG; 6824 vars->link_status &= ~LINK_UPDATE_MASK; 6825 for (phy_index = INT_PHY; phy_index < params->num_phys; 6826 phy_index++) { 6827 phy_vars[phy_index].flow_ctrl = 0; 6828 phy_vars[phy_index].link_status = 0; 6829 phy_vars[phy_index].line_speed = 0; 6830 phy_vars[phy_index].duplex = DUPLEX_FULL; 6831 phy_vars[phy_index].phy_link_up = 0; 6832 phy_vars[phy_index].link_up = 0; 6833 phy_vars[phy_index].fault_detected = 0; 6834 /* different consideration, since vars holds inner state */ 6835 phy_vars[phy_index].eee_status = vars->eee_status; 6836 } 6837 6838 if (USES_WARPCORE(bp)) 6839 bnx2x_set_aer_mmd(params, ¶ms->phy[INT_PHY]); 6840 6841 DP(NETIF_MSG_LINK, "port %x, XGXS?%x, int_status 0x%x\n", 6842 port, (vars->phy_flags & PHY_XGXS_FLAG), 6843 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4)); 6844 6845 is_mi_int = (u8)(REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + 6846 port*0x18) > 0); 6847 DP(NETIF_MSG_LINK, "int_mask 0x%x MI_INT %x, SERDES_LINK %x\n", 6848 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4), 6849 is_mi_int, 6850 REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c)); 6851 6852 DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n", 6853 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68), 6854 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68)); 6855 6856 /* Disable emac */ 6857 if (!CHIP_IS_E3(bp)) 6858 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0); 6859 6860 /* Step 1: 6861 * Check external link change only for external phys, and apply 6862 * priority selection between them in case the link on both phys 6863 * is up. Note that instead of the common vars, a temporary 6864 * vars argument is used since each phy may have different link/ 6865 * speed/duplex result 6866 */ 6867 for (phy_index = EXT_PHY1; phy_index < params->num_phys; 6868 phy_index++) { 6869 struct bnx2x_phy *phy = ¶ms->phy[phy_index]; 6870 if (!phy->read_status) 6871 continue; 6872 /* Read link status and params of this ext phy */ 6873 cur_link_up = phy->read_status(phy, params, 6874 &phy_vars[phy_index]); 6875 if (cur_link_up) { 6876 DP(NETIF_MSG_LINK, "phy in index %d link is up\n", 6877 phy_index); 6878 } else { 6879 DP(NETIF_MSG_LINK, "phy in index %d link is down\n", 6880 phy_index); 6881 continue; 6882 } 6883 6884 if (!ext_phy_link_up) { 6885 ext_phy_link_up = 1; 6886 active_external_phy = phy_index; 6887 } else { 6888 switch (bnx2x_phy_selection(params)) { 6889 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT: 6890 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY: 6891 /* In this option, the first PHY makes sure to pass the 6892 * traffic through itself only. 6893 * Its not clear how to reset the link on the second phy 6894 */ 6895 active_external_phy = EXT_PHY1; 6896 break; 6897 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY: 6898 /* In this option, the first PHY makes sure to pass the 6899 * traffic through the second PHY. 6900 */ 6901 active_external_phy = EXT_PHY2; 6902 break; 6903 default: 6904 /* Link indication on both PHYs with the following cases 6905 * is invalid: 6906 * - FIRST_PHY means that second phy wasn't initialized, 6907 * hence its link is expected to be down 6908 * - SECOND_PHY means that first phy should not be able 6909 * to link up by itself (using configuration) 6910 * - DEFAULT should be overriden during initialiazation 6911 */ 6912 DP(NETIF_MSG_LINK, "Invalid link indication" 6913 "mpc=0x%x. DISABLING LINK !!!\n", 6914 params->multi_phy_config); 6915 ext_phy_link_up = 0; 6916 break; 6917 } 6918 } 6919 } 6920 prev_line_speed = vars->line_speed; 6921 /* Step 2: 6922 * Read the status of the internal phy. In case of 6923 * DIRECT_SINGLE_MEDIA board, this link is the external link, 6924 * otherwise this is the link between the 577xx and the first 6925 * external phy 6926 */ 6927 if (params->phy[INT_PHY].read_status) 6928 params->phy[INT_PHY].read_status( 6929 ¶ms->phy[INT_PHY], 6930 params, vars); 6931 /* The INT_PHY flow control reside in the vars. This include the 6932 * case where the speed or flow control are not set to AUTO. 6933 * Otherwise, the active external phy flow control result is set 6934 * to the vars. The ext_phy_line_speed is needed to check if the 6935 * speed is different between the internal phy and external phy. 6936 * This case may be result of intermediate link speed change. 6937 */ 6938 if (active_external_phy > INT_PHY) { 6939 vars->flow_ctrl = phy_vars[active_external_phy].flow_ctrl; 6940 /* Link speed is taken from the XGXS. AN and FC result from 6941 * the external phy. 6942 */ 6943 vars->link_status |= phy_vars[active_external_phy].link_status; 6944 6945 /* if active_external_phy is first PHY and link is up - disable 6946 * disable TX on second external PHY 6947 */ 6948 if (active_external_phy == EXT_PHY1) { 6949 if (params->phy[EXT_PHY2].phy_specific_func) { 6950 DP(NETIF_MSG_LINK, 6951 "Disabling TX on EXT_PHY2\n"); 6952 params->phy[EXT_PHY2].phy_specific_func( 6953 ¶ms->phy[EXT_PHY2], 6954 params, DISABLE_TX); 6955 } 6956 } 6957 6958 ext_phy_line_speed = phy_vars[active_external_phy].line_speed; 6959 vars->duplex = phy_vars[active_external_phy].duplex; 6960 if (params->phy[active_external_phy].supported & 6961 SUPPORTED_FIBRE) 6962 vars->link_status |= LINK_STATUS_SERDES_LINK; 6963 else 6964 vars->link_status &= ~LINK_STATUS_SERDES_LINK; 6965 6966 vars->eee_status = phy_vars[active_external_phy].eee_status; 6967 6968 DP(NETIF_MSG_LINK, "Active external phy selected: %x\n", 6969 active_external_phy); 6970 } 6971 6972 for (phy_index = EXT_PHY1; phy_index < params->num_phys; 6973 phy_index++) { 6974 if (params->phy[phy_index].flags & 6975 FLAGS_REARM_LATCH_SIGNAL) { 6976 bnx2x_rearm_latch_signal(bp, port, 6977 phy_index == 6978 active_external_phy); 6979 break; 6980 } 6981 } 6982 DP(NETIF_MSG_LINK, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x," 6983 " ext_phy_line_speed = %d\n", vars->flow_ctrl, 6984 vars->link_status, ext_phy_line_speed); 6985 /* Upon link speed change set the NIG into drain mode. Comes to 6986 * deals with possible FIFO glitch due to clk change when speed 6987 * is decreased without link down indicator 6988 */ 6989 6990 if (vars->phy_link_up) { 6991 if (!(SINGLE_MEDIA_DIRECT(params)) && ext_phy_link_up && 6992 (ext_phy_line_speed != vars->line_speed)) { 6993 DP(NETIF_MSG_LINK, "Internal link speed %d is" 6994 " different than the external" 6995 " link speed %d\n", vars->line_speed, 6996 ext_phy_line_speed); 6997 vars->phy_link_up = 0; 6998 } else if (prev_line_speed != vars->line_speed) { 6999 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 7000 0); 7001 usleep_range(1000, 2000); 7002 } 7003 } 7004 7005 /* Anything 10 and over uses the bmac */ 7006 link_10g_plus = (vars->line_speed >= SPEED_10000); 7007 7008 bnx2x_link_int_ack(params, vars, link_10g_plus); 7009 7010 /* In case external phy link is up, and internal link is down 7011 * (not initialized yet probably after link initialization, it 7012 * needs to be initialized. 7013 * Note that after link down-up as result of cable plug, the xgxs 7014 * link would probably become up again without the need 7015 * initialize it 7016 */ 7017 if (!(SINGLE_MEDIA_DIRECT(params))) { 7018 DP(NETIF_MSG_LINK, "ext_phy_link_up = %d, int_link_up = %d," 7019 " init_preceding = %d\n", ext_phy_link_up, 7020 vars->phy_link_up, 7021 params->phy[EXT_PHY1].flags & 7022 FLAGS_INIT_XGXS_FIRST); 7023 if (!(params->phy[EXT_PHY1].flags & 7024 FLAGS_INIT_XGXS_FIRST) 7025 && ext_phy_link_up && !vars->phy_link_up) { 7026 vars->line_speed = ext_phy_line_speed; 7027 if (vars->line_speed < SPEED_1000) 7028 vars->phy_flags |= PHY_SGMII_FLAG; 7029 else 7030 vars->phy_flags &= ~PHY_SGMII_FLAG; 7031 7032 if (params->phy[INT_PHY].config_init) 7033 params->phy[INT_PHY].config_init( 7034 ¶ms->phy[INT_PHY], params, 7035 vars); 7036 } 7037 } 7038 /* Link is up only if both local phy and external phy (in case of 7039 * non-direct board) are up and no fault detected on active PHY. 7040 */ 7041 vars->link_up = (vars->phy_link_up && 7042 (ext_phy_link_up || 7043 SINGLE_MEDIA_DIRECT(params)) && 7044 (phy_vars[active_external_phy].fault_detected == 0)); 7045 7046 /* Update the PFC configuration in case it was changed */ 7047 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) 7048 vars->link_status |= LINK_STATUS_PFC_ENABLED; 7049 else 7050 vars->link_status &= ~LINK_STATUS_PFC_ENABLED; 7051 7052 if (vars->link_up) 7053 rc = bnx2x_update_link_up(params, vars, link_10g_plus); 7054 else 7055 rc = bnx2x_update_link_down(params, vars); 7056 7057 if ((prev_link_status ^ vars->link_status) & LINK_STATUS_LINK_UP) 7058 bnx2x_chng_link_count(params, false); 7059 7060 /* Update MCP link status was changed */ 7061 if (params->feature_config_flags & FEATURE_CONFIG_BC_SUPPORTS_AFEX) 7062 bnx2x_fw_command(bp, DRV_MSG_CODE_LINK_STATUS_CHANGED, 0); 7063 7064 return rc; 7065 } 7066 7067 /*****************************************************************************/ 7068 /* External Phy section */ 7069 /*****************************************************************************/ 7070 void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port) 7071 { 7072 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, 7073 MISC_REGISTERS_GPIO_OUTPUT_LOW, port); 7074 usleep_range(1000, 2000); 7075 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, 7076 MISC_REGISTERS_GPIO_OUTPUT_HIGH, port); 7077 } 7078 7079 static void bnx2x_save_spirom_version(struct bnx2x *bp, u8 port, 7080 u32 spirom_ver, u32 ver_addr) 7081 { 7082 DP(NETIF_MSG_LINK, "FW version 0x%x:0x%x for port %d\n", 7083 (u16)(spirom_ver>>16), (u16)spirom_ver, port); 7084 7085 if (ver_addr) 7086 REG_WR(bp, ver_addr, spirom_ver); 7087 } 7088 7089 static void bnx2x_save_bcm_spirom_ver(struct bnx2x *bp, 7090 struct bnx2x_phy *phy, 7091 u8 port) 7092 { 7093 u16 fw_ver1, fw_ver2; 7094 7095 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 7096 MDIO_PMA_REG_ROM_VER1, &fw_ver1); 7097 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 7098 MDIO_PMA_REG_ROM_VER2, &fw_ver2); 7099 bnx2x_save_spirom_version(bp, port, (u32)(fw_ver1<<16 | fw_ver2), 7100 phy->ver_addr); 7101 } 7102 7103 static void bnx2x_ext_phy_10G_an_resolve(struct bnx2x *bp, 7104 struct bnx2x_phy *phy, 7105 struct link_vars *vars) 7106 { 7107 u16 val; 7108 bnx2x_cl45_read(bp, phy, 7109 MDIO_AN_DEVAD, 7110 MDIO_AN_REG_STATUS, &val); 7111 bnx2x_cl45_read(bp, phy, 7112 MDIO_AN_DEVAD, 7113 MDIO_AN_REG_STATUS, &val); 7114 if (val & (1<<5)) 7115 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; 7116 if ((val & (1<<0)) == 0) 7117 vars->link_status |= LINK_STATUS_PARALLEL_DETECTION_USED; 7118 } 7119 7120 /******************************************************************/ 7121 /* common BCM8073/BCM8727 PHY SECTION */ 7122 /******************************************************************/ 7123 static void bnx2x_8073_resolve_fc(struct bnx2x_phy *phy, 7124 struct link_params *params, 7125 struct link_vars *vars) 7126 { 7127 struct bnx2x *bp = params->bp; 7128 if (phy->req_line_speed == SPEED_10 || 7129 phy->req_line_speed == SPEED_100) { 7130 vars->flow_ctrl = phy->req_flow_ctrl; 7131 return; 7132 } 7133 7134 if (bnx2x_ext_phy_resolve_fc(phy, params, vars) && 7135 (vars->flow_ctrl == BNX2X_FLOW_CTRL_NONE)) { 7136 u16 pause_result; 7137 u16 ld_pause; /* local */ 7138 u16 lp_pause; /* link partner */ 7139 bnx2x_cl45_read(bp, phy, 7140 MDIO_AN_DEVAD, 7141 MDIO_AN_REG_CL37_FC_LD, &ld_pause); 7142 7143 bnx2x_cl45_read(bp, phy, 7144 MDIO_AN_DEVAD, 7145 MDIO_AN_REG_CL37_FC_LP, &lp_pause); 7146 pause_result = (ld_pause & 7147 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 5; 7148 pause_result |= (lp_pause & 7149 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 7; 7150 7151 bnx2x_pause_resolve(phy, params, vars, pause_result); 7152 DP(NETIF_MSG_LINK, "Ext PHY CL37 pause result 0x%x\n", 7153 pause_result); 7154 } 7155 } 7156 static int bnx2x_8073_8727_external_rom_boot(struct bnx2x *bp, 7157 struct bnx2x_phy *phy, 7158 u8 port) 7159 { 7160 u32 count = 0; 7161 u16 fw_ver1, fw_msgout; 7162 int rc = 0; 7163 7164 /* Boot port from external ROM */ 7165 /* EDC grst */ 7166 bnx2x_cl45_write(bp, phy, 7167 MDIO_PMA_DEVAD, 7168 MDIO_PMA_REG_GEN_CTRL, 7169 0x0001); 7170 7171 /* Ucode reboot and rst */ 7172 bnx2x_cl45_write(bp, phy, 7173 MDIO_PMA_DEVAD, 7174 MDIO_PMA_REG_GEN_CTRL, 7175 0x008c); 7176 7177 bnx2x_cl45_write(bp, phy, 7178 MDIO_PMA_DEVAD, 7179 MDIO_PMA_REG_MISC_CTRL1, 0x0001); 7180 7181 /* Reset internal microprocessor */ 7182 bnx2x_cl45_write(bp, phy, 7183 MDIO_PMA_DEVAD, 7184 MDIO_PMA_REG_GEN_CTRL, 7185 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET); 7186 7187 /* Release srst bit */ 7188 bnx2x_cl45_write(bp, phy, 7189 MDIO_PMA_DEVAD, 7190 MDIO_PMA_REG_GEN_CTRL, 7191 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP); 7192 7193 /* Delay 100ms per the PHY specifications */ 7194 msleep(100); 7195 7196 /* 8073 sometimes taking longer to download */ 7197 do { 7198 count++; 7199 if (count > 300) { 7200 DP(NETIF_MSG_LINK, 7201 "bnx2x_8073_8727_external_rom_boot port %x:" 7202 "Download failed. fw version = 0x%x\n", 7203 port, fw_ver1); 7204 rc = -EINVAL; 7205 break; 7206 } 7207 7208 bnx2x_cl45_read(bp, phy, 7209 MDIO_PMA_DEVAD, 7210 MDIO_PMA_REG_ROM_VER1, &fw_ver1); 7211 bnx2x_cl45_read(bp, phy, 7212 MDIO_PMA_DEVAD, 7213 MDIO_PMA_REG_M8051_MSGOUT_REG, &fw_msgout); 7214 7215 usleep_range(1000, 2000); 7216 } while (fw_ver1 == 0 || fw_ver1 == 0x4321 || 7217 ((fw_msgout & 0xff) != 0x03 && (phy->type == 7218 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073))); 7219 7220 /* Clear ser_boot_ctl bit */ 7221 bnx2x_cl45_write(bp, phy, 7222 MDIO_PMA_DEVAD, 7223 MDIO_PMA_REG_MISC_CTRL1, 0x0000); 7224 bnx2x_save_bcm_spirom_ver(bp, phy, port); 7225 7226 DP(NETIF_MSG_LINK, 7227 "bnx2x_8073_8727_external_rom_boot port %x:" 7228 "Download complete. fw version = 0x%x\n", 7229 port, fw_ver1); 7230 7231 return rc; 7232 } 7233 7234 /******************************************************************/ 7235 /* BCM8073 PHY SECTION */ 7236 /******************************************************************/ 7237 static int bnx2x_8073_is_snr_needed(struct bnx2x *bp, struct bnx2x_phy *phy) 7238 { 7239 /* This is only required for 8073A1, version 102 only */ 7240 u16 val; 7241 7242 /* Read 8073 HW revision*/ 7243 bnx2x_cl45_read(bp, phy, 7244 MDIO_PMA_DEVAD, 7245 MDIO_PMA_REG_8073_CHIP_REV, &val); 7246 7247 if (val != 1) { 7248 /* No need to workaround in 8073 A1 */ 7249 return 0; 7250 } 7251 7252 bnx2x_cl45_read(bp, phy, 7253 MDIO_PMA_DEVAD, 7254 MDIO_PMA_REG_ROM_VER2, &val); 7255 7256 /* SNR should be applied only for version 0x102 */ 7257 if (val != 0x102) 7258 return 0; 7259 7260 return 1; 7261 } 7262 7263 static int bnx2x_8073_xaui_wa(struct bnx2x *bp, struct bnx2x_phy *phy) 7264 { 7265 u16 val, cnt, cnt1 ; 7266 7267 bnx2x_cl45_read(bp, phy, 7268 MDIO_PMA_DEVAD, 7269 MDIO_PMA_REG_8073_CHIP_REV, &val); 7270 7271 if (val > 0) { 7272 /* No need to workaround in 8073 A1 */ 7273 return 0; 7274 } 7275 /* XAUI workaround in 8073 A0: */ 7276 7277 /* After loading the boot ROM and restarting Autoneg, poll 7278 * Dev1, Reg $C820: 7279 */ 7280 7281 for (cnt = 0; cnt < 1000; cnt++) { 7282 bnx2x_cl45_read(bp, phy, 7283 MDIO_PMA_DEVAD, 7284 MDIO_PMA_REG_8073_SPEED_LINK_STATUS, 7285 &val); 7286 /* If bit [14] = 0 or bit [13] = 0, continue on with 7287 * system initialization (XAUI work-around not required, as 7288 * these bits indicate 2.5G or 1G link up). 7289 */ 7290 if (!(val & (1<<14)) || !(val & (1<<13))) { 7291 DP(NETIF_MSG_LINK, "XAUI work-around not required\n"); 7292 return 0; 7293 } else if (!(val & (1<<15))) { 7294 DP(NETIF_MSG_LINK, "bit 15 went off\n"); 7295 /* If bit 15 is 0, then poll Dev1, Reg $C841 until it's 7296 * MSB (bit15) goes to 1 (indicating that the XAUI 7297 * workaround has completed), then continue on with 7298 * system initialization. 7299 */ 7300 for (cnt1 = 0; cnt1 < 1000; cnt1++) { 7301 bnx2x_cl45_read(bp, phy, 7302 MDIO_PMA_DEVAD, 7303 MDIO_PMA_REG_8073_XAUI_WA, &val); 7304 if (val & (1<<15)) { 7305 DP(NETIF_MSG_LINK, 7306 "XAUI workaround has completed\n"); 7307 return 0; 7308 } 7309 usleep_range(3000, 6000); 7310 } 7311 break; 7312 } 7313 usleep_range(3000, 6000); 7314 } 7315 DP(NETIF_MSG_LINK, "Warning: XAUI work-around timeout !!!\n"); 7316 return -EINVAL; 7317 } 7318 7319 static void bnx2x_807x_force_10G(struct bnx2x *bp, struct bnx2x_phy *phy) 7320 { 7321 /* Force KR or KX */ 7322 bnx2x_cl45_write(bp, phy, 7323 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040); 7324 bnx2x_cl45_write(bp, phy, 7325 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0x000b); 7326 bnx2x_cl45_write(bp, phy, 7327 MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0000); 7328 bnx2x_cl45_write(bp, phy, 7329 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000); 7330 } 7331 7332 static void bnx2x_8073_set_pause_cl37(struct link_params *params, 7333 struct bnx2x_phy *phy, 7334 struct link_vars *vars) 7335 { 7336 u16 cl37_val; 7337 struct bnx2x *bp = params->bp; 7338 bnx2x_cl45_read(bp, phy, 7339 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &cl37_val); 7340 7341 cl37_val &= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; 7342 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */ 7343 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); 7344 if ((vars->ieee_fc & 7345 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) == 7346 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) { 7347 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC; 7348 } 7349 if ((vars->ieee_fc & 7350 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) == 7351 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) { 7352 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC; 7353 } 7354 if ((vars->ieee_fc & 7355 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) == 7356 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) { 7357 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; 7358 } 7359 DP(NETIF_MSG_LINK, 7360 "Ext phy AN advertize cl37 0x%x\n", cl37_val); 7361 7362 bnx2x_cl45_write(bp, phy, 7363 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, cl37_val); 7364 msleep(500); 7365 } 7366 7367 static void bnx2x_8073_specific_func(struct bnx2x_phy *phy, 7368 struct link_params *params, 7369 u32 action) 7370 { 7371 struct bnx2x *bp = params->bp; 7372 switch (action) { 7373 case PHY_INIT: 7374 /* Enable LASI */ 7375 bnx2x_cl45_write(bp, phy, 7376 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, (1<<2)); 7377 bnx2x_cl45_write(bp, phy, 7378 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0004); 7379 break; 7380 } 7381 } 7382 7383 static int bnx2x_8073_config_init(struct bnx2x_phy *phy, 7384 struct link_params *params, 7385 struct link_vars *vars) 7386 { 7387 struct bnx2x *bp = params->bp; 7388 u16 val = 0, tmp1; 7389 u8 gpio_port; 7390 DP(NETIF_MSG_LINK, "Init 8073\n"); 7391 7392 if (CHIP_IS_E2(bp)) 7393 gpio_port = BP_PATH(bp); 7394 else 7395 gpio_port = params->port; 7396 /* Restore normal power mode*/ 7397 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 7398 MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port); 7399 7400 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, 7401 MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port); 7402 7403 bnx2x_8073_specific_func(phy, params, PHY_INIT); 7404 bnx2x_8073_set_pause_cl37(params, phy, vars); 7405 7406 bnx2x_cl45_read(bp, phy, 7407 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1); 7408 7409 bnx2x_cl45_read(bp, phy, 7410 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1); 7411 7412 DP(NETIF_MSG_LINK, "Before rom RX_ALARM(port1): 0x%x\n", tmp1); 7413 7414 /* Swap polarity if required - Must be done only in non-1G mode */ 7415 if (params->lane_config & PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) { 7416 /* Configure the 8073 to swap _P and _N of the KR lines */ 7417 DP(NETIF_MSG_LINK, "Swapping polarity for the 8073\n"); 7418 /* 10G Rx/Tx and 1G Tx signal polarity swap */ 7419 bnx2x_cl45_read(bp, phy, 7420 MDIO_PMA_DEVAD, 7421 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL, &val); 7422 bnx2x_cl45_write(bp, phy, 7423 MDIO_PMA_DEVAD, 7424 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL, 7425 (val | (3<<9))); 7426 } 7427 7428 7429 /* Enable CL37 BAM */ 7430 if (REG_RD(bp, params->shmem_base + 7431 offsetof(struct shmem_region, dev_info. 7432 port_hw_config[params->port].default_cfg)) & 7433 PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) { 7434 7435 bnx2x_cl45_read(bp, phy, 7436 MDIO_AN_DEVAD, 7437 MDIO_AN_REG_8073_BAM, &val); 7438 bnx2x_cl45_write(bp, phy, 7439 MDIO_AN_DEVAD, 7440 MDIO_AN_REG_8073_BAM, val | 1); 7441 DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n"); 7442 } 7443 if (params->loopback_mode == LOOPBACK_EXT) { 7444 bnx2x_807x_force_10G(bp, phy); 7445 DP(NETIF_MSG_LINK, "Forced speed 10G on 807X\n"); 7446 return 0; 7447 } else { 7448 bnx2x_cl45_write(bp, phy, 7449 MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0002); 7450 } 7451 if (phy->req_line_speed != SPEED_AUTO_NEG) { 7452 if (phy->req_line_speed == SPEED_10000) { 7453 val = (1<<7); 7454 } else if (phy->req_line_speed == SPEED_2500) { 7455 val = (1<<5); 7456 /* Note that 2.5G works only when used with 1G 7457 * advertisement 7458 */ 7459 } else 7460 val = (1<<5); 7461 } else { 7462 val = 0; 7463 if (phy->speed_cap_mask & 7464 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) 7465 val |= (1<<7); 7466 7467 /* Note that 2.5G works only when used with 1G advertisement */ 7468 if (phy->speed_cap_mask & 7469 (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G | 7470 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) 7471 val |= (1<<5); 7472 DP(NETIF_MSG_LINK, "807x autoneg val = 0x%x\n", val); 7473 } 7474 7475 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val); 7476 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, &tmp1); 7477 7478 if (((phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) && 7479 (phy->req_line_speed == SPEED_AUTO_NEG)) || 7480 (phy->req_line_speed == SPEED_2500)) { 7481 u16 phy_ver; 7482 /* Allow 2.5G for A1 and above */ 7483 bnx2x_cl45_read(bp, phy, 7484 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV, 7485 &phy_ver); 7486 DP(NETIF_MSG_LINK, "Add 2.5G\n"); 7487 if (phy_ver > 0) 7488 tmp1 |= 1; 7489 else 7490 tmp1 &= 0xfffe; 7491 } else { 7492 DP(NETIF_MSG_LINK, "Disable 2.5G\n"); 7493 tmp1 &= 0xfffe; 7494 } 7495 7496 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, tmp1); 7497 /* Add support for CL37 (passive mode) II */ 7498 7499 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &tmp1); 7500 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, 7501 (tmp1 | ((phy->req_duplex == DUPLEX_FULL) ? 7502 0x20 : 0x40))); 7503 7504 /* Add support for CL37 (passive mode) III */ 7505 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000); 7506 7507 /* The SNR will improve about 2db by changing BW and FEE main 7508 * tap. Rest commands are executed after link is up 7509 * Change FFE main cursor to 5 in EDC register 7510 */ 7511 if (bnx2x_8073_is_snr_needed(bp, phy)) 7512 bnx2x_cl45_write(bp, phy, 7513 MDIO_PMA_DEVAD, MDIO_PMA_REG_EDC_FFE_MAIN, 7514 0xFB0C); 7515 7516 /* Enable FEC (Forware Error Correction) Request in the AN */ 7517 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, &tmp1); 7518 tmp1 |= (1<<15); 7519 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, tmp1); 7520 7521 bnx2x_ext_phy_set_pause(params, phy, vars); 7522 7523 /* Restart autoneg */ 7524 msleep(500); 7525 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200); 7526 DP(NETIF_MSG_LINK, "807x Autoneg Restart: Advertise 1G=%x, 10G=%x\n", 7527 ((val & (1<<5)) > 0), ((val & (1<<7)) > 0)); 7528 return 0; 7529 } 7530 7531 static u8 bnx2x_8073_read_status(struct bnx2x_phy *phy, 7532 struct link_params *params, 7533 struct link_vars *vars) 7534 { 7535 struct bnx2x *bp = params->bp; 7536 u8 link_up = 0; 7537 u16 val1, val2; 7538 u16 link_status = 0; 7539 u16 an1000_status = 0; 7540 7541 bnx2x_cl45_read(bp, phy, 7542 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1); 7543 7544 DP(NETIF_MSG_LINK, "8703 LASI status 0x%x\n", val1); 7545 7546 /* Clear the interrupt LASI status register */ 7547 bnx2x_cl45_read(bp, phy, 7548 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2); 7549 bnx2x_cl45_read(bp, phy, 7550 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val1); 7551 DP(NETIF_MSG_LINK, "807x PCS status 0x%x->0x%x\n", val2, val1); 7552 /* Clear MSG-OUT */ 7553 bnx2x_cl45_read(bp, phy, 7554 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1); 7555 7556 /* Check the LASI */ 7557 bnx2x_cl45_read(bp, phy, 7558 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2); 7559 7560 DP(NETIF_MSG_LINK, "KR 0x9003 0x%x\n", val2); 7561 7562 /* Check the link status */ 7563 bnx2x_cl45_read(bp, phy, 7564 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2); 7565 DP(NETIF_MSG_LINK, "KR PCS status 0x%x\n", val2); 7566 7567 bnx2x_cl45_read(bp, phy, 7568 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2); 7569 bnx2x_cl45_read(bp, phy, 7570 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1); 7571 link_up = ((val1 & 4) == 4); 7572 DP(NETIF_MSG_LINK, "PMA_REG_STATUS=0x%x\n", val1); 7573 7574 if (link_up && 7575 ((phy->req_line_speed != SPEED_10000))) { 7576 if (bnx2x_8073_xaui_wa(bp, phy) != 0) 7577 return 0; 7578 } 7579 bnx2x_cl45_read(bp, phy, 7580 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status); 7581 bnx2x_cl45_read(bp, phy, 7582 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status); 7583 7584 /* Check the link status on 1.1.2 */ 7585 bnx2x_cl45_read(bp, phy, 7586 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2); 7587 bnx2x_cl45_read(bp, phy, 7588 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1); 7589 DP(NETIF_MSG_LINK, "KR PMA status 0x%x->0x%x," 7590 "an_link_status=0x%x\n", val2, val1, an1000_status); 7591 7592 link_up = (((val1 & 4) == 4) || (an1000_status & (1<<1))); 7593 if (link_up && bnx2x_8073_is_snr_needed(bp, phy)) { 7594 /* The SNR will improve about 2dbby changing the BW and FEE main 7595 * tap. The 1st write to change FFE main tap is set before 7596 * restart AN. Change PLL Bandwidth in EDC register 7597 */ 7598 bnx2x_cl45_write(bp, phy, 7599 MDIO_PMA_DEVAD, MDIO_PMA_REG_PLL_BANDWIDTH, 7600 0x26BC); 7601 7602 /* Change CDR Bandwidth in EDC register */ 7603 bnx2x_cl45_write(bp, phy, 7604 MDIO_PMA_DEVAD, MDIO_PMA_REG_CDR_BANDWIDTH, 7605 0x0333); 7606 } 7607 bnx2x_cl45_read(bp, phy, 7608 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_SPEED_LINK_STATUS, 7609 &link_status); 7610 7611 /* Bits 0..2 --> speed detected, bits 13..15--> link is down */ 7612 if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) { 7613 link_up = 1; 7614 vars->line_speed = SPEED_10000; 7615 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n", 7616 params->port); 7617 } else if ((link_status & (1<<1)) && (!(link_status & (1<<14)))) { 7618 link_up = 1; 7619 vars->line_speed = SPEED_2500; 7620 DP(NETIF_MSG_LINK, "port %x: External link up in 2.5G\n", 7621 params->port); 7622 } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) { 7623 link_up = 1; 7624 vars->line_speed = SPEED_1000; 7625 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n", 7626 params->port); 7627 } else { 7628 link_up = 0; 7629 DP(NETIF_MSG_LINK, "port %x: External link is down\n", 7630 params->port); 7631 } 7632 7633 if (link_up) { 7634 /* Swap polarity if required */ 7635 if (params->lane_config & 7636 PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) { 7637 /* Configure the 8073 to swap P and N of the KR lines */ 7638 bnx2x_cl45_read(bp, phy, 7639 MDIO_XS_DEVAD, 7640 MDIO_XS_REG_8073_RX_CTRL_PCIE, &val1); 7641 /* Set bit 3 to invert Rx in 1G mode and clear this bit 7642 * when it`s in 10G mode. 7643 */ 7644 if (vars->line_speed == SPEED_1000) { 7645 DP(NETIF_MSG_LINK, "Swapping 1G polarity for" 7646 "the 8073\n"); 7647 val1 |= (1<<3); 7648 } else 7649 val1 &= ~(1<<3); 7650 7651 bnx2x_cl45_write(bp, phy, 7652 MDIO_XS_DEVAD, 7653 MDIO_XS_REG_8073_RX_CTRL_PCIE, 7654 val1); 7655 } 7656 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars); 7657 bnx2x_8073_resolve_fc(phy, params, vars); 7658 vars->duplex = DUPLEX_FULL; 7659 } 7660 7661 if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) { 7662 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, 7663 MDIO_AN_REG_LP_AUTO_NEG2, &val1); 7664 7665 if (val1 & (1<<5)) 7666 vars->link_status |= 7667 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; 7668 if (val1 & (1<<7)) 7669 vars->link_status |= 7670 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; 7671 } 7672 7673 return link_up; 7674 } 7675 7676 static void bnx2x_8073_link_reset(struct bnx2x_phy *phy, 7677 struct link_params *params) 7678 { 7679 struct bnx2x *bp = params->bp; 7680 u8 gpio_port; 7681 if (CHIP_IS_E2(bp)) 7682 gpio_port = BP_PATH(bp); 7683 else 7684 gpio_port = params->port; 7685 DP(NETIF_MSG_LINK, "Setting 8073 port %d into low power mode\n", 7686 gpio_port); 7687 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 7688 MISC_REGISTERS_GPIO_OUTPUT_LOW, 7689 gpio_port); 7690 } 7691 7692 /******************************************************************/ 7693 /* BCM8705 PHY SECTION */ 7694 /******************************************************************/ 7695 static int bnx2x_8705_config_init(struct bnx2x_phy *phy, 7696 struct link_params *params, 7697 struct link_vars *vars) 7698 { 7699 struct bnx2x *bp = params->bp; 7700 DP(NETIF_MSG_LINK, "init 8705\n"); 7701 /* Restore normal power mode*/ 7702 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 7703 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); 7704 /* HW reset */ 7705 bnx2x_ext_phy_hw_reset(bp, params->port); 7706 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040); 7707 bnx2x_wait_reset_complete(bp, phy, params); 7708 7709 bnx2x_cl45_write(bp, phy, 7710 MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL, 0x8288); 7711 bnx2x_cl45_write(bp, phy, 7712 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 0x7fbf); 7713 bnx2x_cl45_write(bp, phy, 7714 MDIO_PMA_DEVAD, MDIO_PMA_REG_CMU_PLL_BYPASS, 0x0100); 7715 bnx2x_cl45_write(bp, phy, 7716 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_CNTL, 0x1); 7717 /* BCM8705 doesn't have microcode, hence the 0 */ 7718 bnx2x_save_spirom_version(bp, params->port, params->shmem_base, 0); 7719 return 0; 7720 } 7721 7722 static u8 bnx2x_8705_read_status(struct bnx2x_phy *phy, 7723 struct link_params *params, 7724 struct link_vars *vars) 7725 { 7726 u8 link_up = 0; 7727 u16 val1, rx_sd; 7728 struct bnx2x *bp = params->bp; 7729 DP(NETIF_MSG_LINK, "read status 8705\n"); 7730 bnx2x_cl45_read(bp, phy, 7731 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1); 7732 DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1); 7733 7734 bnx2x_cl45_read(bp, phy, 7735 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1); 7736 DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1); 7737 7738 bnx2x_cl45_read(bp, phy, 7739 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd); 7740 7741 bnx2x_cl45_read(bp, phy, 7742 MDIO_PMA_DEVAD, 0xc809, &val1); 7743 bnx2x_cl45_read(bp, phy, 7744 MDIO_PMA_DEVAD, 0xc809, &val1); 7745 7746 DP(NETIF_MSG_LINK, "8705 1.c809 val=0x%x\n", val1); 7747 link_up = ((rx_sd & 0x1) && (val1 & (1<<9)) && ((val1 & (1<<8)) == 0)); 7748 if (link_up) { 7749 vars->line_speed = SPEED_10000; 7750 bnx2x_ext_phy_resolve_fc(phy, params, vars); 7751 } 7752 return link_up; 7753 } 7754 7755 /******************************************************************/ 7756 /* SFP+ module Section */ 7757 /******************************************************************/ 7758 static void bnx2x_set_disable_pmd_transmit(struct link_params *params, 7759 struct bnx2x_phy *phy, 7760 u8 pmd_dis) 7761 { 7762 struct bnx2x *bp = params->bp; 7763 /* Disable transmitter only for bootcodes which can enable it afterwards 7764 * (for D3 link) 7765 */ 7766 if (pmd_dis) { 7767 if (params->feature_config_flags & 7768 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED) 7769 DP(NETIF_MSG_LINK, "Disabling PMD transmitter\n"); 7770 else { 7771 DP(NETIF_MSG_LINK, "NOT disabling PMD transmitter\n"); 7772 return; 7773 } 7774 } else 7775 DP(NETIF_MSG_LINK, "Enabling PMD transmitter\n"); 7776 bnx2x_cl45_write(bp, phy, 7777 MDIO_PMA_DEVAD, 7778 MDIO_PMA_REG_TX_DISABLE, pmd_dis); 7779 } 7780 7781 static u8 bnx2x_get_gpio_port(struct link_params *params) 7782 { 7783 u8 gpio_port; 7784 u32 swap_val, swap_override; 7785 struct bnx2x *bp = params->bp; 7786 if (CHIP_IS_E2(bp)) 7787 gpio_port = BP_PATH(bp); 7788 else 7789 gpio_port = params->port; 7790 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); 7791 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); 7792 return gpio_port ^ (swap_val && swap_override); 7793 } 7794 7795 static void bnx2x_sfp_e1e2_set_transmitter(struct link_params *params, 7796 struct bnx2x_phy *phy, 7797 u8 tx_en) 7798 { 7799 u16 val; 7800 u8 port = params->port; 7801 struct bnx2x *bp = params->bp; 7802 u32 tx_en_mode; 7803 7804 /* Disable/Enable transmitter ( TX laser of the SFP+ module.)*/ 7805 tx_en_mode = REG_RD(bp, params->shmem_base + 7806 offsetof(struct shmem_region, 7807 dev_info.port_hw_config[port].sfp_ctrl)) & 7808 PORT_HW_CFG_TX_LASER_MASK; 7809 DP(NETIF_MSG_LINK, "Setting transmitter tx_en=%x for port %x " 7810 "mode = %x\n", tx_en, port, tx_en_mode); 7811 switch (tx_en_mode) { 7812 case PORT_HW_CFG_TX_LASER_MDIO: 7813 7814 bnx2x_cl45_read(bp, phy, 7815 MDIO_PMA_DEVAD, 7816 MDIO_PMA_REG_PHY_IDENTIFIER, 7817 &val); 7818 7819 if (tx_en) 7820 val &= ~(1<<15); 7821 else 7822 val |= (1<<15); 7823 7824 bnx2x_cl45_write(bp, phy, 7825 MDIO_PMA_DEVAD, 7826 MDIO_PMA_REG_PHY_IDENTIFIER, 7827 val); 7828 break; 7829 case PORT_HW_CFG_TX_LASER_GPIO0: 7830 case PORT_HW_CFG_TX_LASER_GPIO1: 7831 case PORT_HW_CFG_TX_LASER_GPIO2: 7832 case PORT_HW_CFG_TX_LASER_GPIO3: 7833 { 7834 u16 gpio_pin; 7835 u8 gpio_port, gpio_mode; 7836 if (tx_en) 7837 gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_HIGH; 7838 else 7839 gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_LOW; 7840 7841 gpio_pin = tx_en_mode - PORT_HW_CFG_TX_LASER_GPIO0; 7842 gpio_port = bnx2x_get_gpio_port(params); 7843 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port); 7844 break; 7845 } 7846 default: 7847 DP(NETIF_MSG_LINK, "Invalid TX_LASER_MDIO 0x%x\n", tx_en_mode); 7848 break; 7849 } 7850 } 7851 7852 static void bnx2x_sfp_set_transmitter(struct link_params *params, 7853 struct bnx2x_phy *phy, 7854 u8 tx_en) 7855 { 7856 struct bnx2x *bp = params->bp; 7857 DP(NETIF_MSG_LINK, "Setting SFP+ transmitter to %d\n", tx_en); 7858 if (CHIP_IS_E3(bp)) 7859 bnx2x_sfp_e3_set_transmitter(params, phy, tx_en); 7860 else 7861 bnx2x_sfp_e1e2_set_transmitter(params, phy, tx_en); 7862 } 7863 7864 static int bnx2x_8726_read_sfp_module_eeprom(struct bnx2x_phy *phy, 7865 struct link_params *params, 7866 u8 dev_addr, u16 addr, u8 byte_cnt, 7867 u8 *o_buf, u8 is_init) 7868 { 7869 struct bnx2x *bp = params->bp; 7870 u16 val = 0; 7871 u16 i; 7872 if (byte_cnt > SFP_EEPROM_PAGE_SIZE) { 7873 DP(NETIF_MSG_LINK, 7874 "Reading from eeprom is limited to 0xf\n"); 7875 return -EINVAL; 7876 } 7877 /* Set the read command byte count */ 7878 bnx2x_cl45_write(bp, phy, 7879 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT, 7880 (byte_cnt | (dev_addr << 8))); 7881 7882 /* Set the read command address */ 7883 bnx2x_cl45_write(bp, phy, 7884 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR, 7885 addr); 7886 7887 /* Activate read command */ 7888 bnx2x_cl45_write(bp, phy, 7889 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, 7890 0x2c0f); 7891 7892 /* Wait up to 500us for command complete status */ 7893 for (i = 0; i < 100; i++) { 7894 bnx2x_cl45_read(bp, phy, 7895 MDIO_PMA_DEVAD, 7896 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); 7897 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == 7898 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) 7899 break; 7900 udelay(5); 7901 } 7902 7903 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) != 7904 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) { 7905 DP(NETIF_MSG_LINK, 7906 "Got bad status 0x%x when reading from SFP+ EEPROM\n", 7907 (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK)); 7908 return -EINVAL; 7909 } 7910 7911 /* Read the buffer */ 7912 for (i = 0; i < byte_cnt; i++) { 7913 bnx2x_cl45_read(bp, phy, 7914 MDIO_PMA_DEVAD, 7915 MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i, &val); 7916 o_buf[i] = (u8)(val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK); 7917 } 7918 7919 for (i = 0; i < 100; i++) { 7920 bnx2x_cl45_read(bp, phy, 7921 MDIO_PMA_DEVAD, 7922 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); 7923 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == 7924 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE) 7925 return 0; 7926 usleep_range(1000, 2000); 7927 } 7928 return -EINVAL; 7929 } 7930 7931 static void bnx2x_warpcore_power_module(struct link_params *params, 7932 u8 power) 7933 { 7934 u32 pin_cfg; 7935 struct bnx2x *bp = params->bp; 7936 7937 pin_cfg = (REG_RD(bp, params->shmem_base + 7938 offsetof(struct shmem_region, 7939 dev_info.port_hw_config[params->port].e3_sfp_ctrl)) & 7940 PORT_HW_CFG_E3_PWR_DIS_MASK) >> 7941 PORT_HW_CFG_E3_PWR_DIS_SHIFT; 7942 7943 if (pin_cfg == PIN_CFG_NA) 7944 return; 7945 DP(NETIF_MSG_LINK, "Setting SFP+ module power to %d using pin cfg %d\n", 7946 power, pin_cfg); 7947 /* Low ==> corresponding SFP+ module is powered 7948 * high ==> the SFP+ module is powered down 7949 */ 7950 bnx2x_set_cfg_pin(bp, pin_cfg, power ^ 1); 7951 } 7952 static int bnx2x_warpcore_read_sfp_module_eeprom(struct bnx2x_phy *phy, 7953 struct link_params *params, 7954 u8 dev_addr, 7955 u16 addr, u8 byte_cnt, 7956 u8 *o_buf, u8 is_init) 7957 { 7958 int rc = 0; 7959 u8 i, j = 0, cnt = 0; 7960 u32 data_array[4]; 7961 u16 addr32; 7962 struct bnx2x *bp = params->bp; 7963 7964 if (byte_cnt > SFP_EEPROM_PAGE_SIZE) { 7965 DP(NETIF_MSG_LINK, 7966 "Reading from eeprom is limited to 16 bytes\n"); 7967 return -EINVAL; 7968 } 7969 7970 /* 4 byte aligned address */ 7971 addr32 = addr & (~0x3); 7972 do { 7973 if ((!is_init) && (cnt == I2C_WA_PWR_ITER)) { 7974 bnx2x_warpcore_power_module(params, 0); 7975 /* Note that 100us are not enough here */ 7976 usleep_range(1000, 2000); 7977 bnx2x_warpcore_power_module(params, 1); 7978 } 7979 rc = bnx2x_bsc_read(params, bp, dev_addr, addr32, 0, byte_cnt, 7980 data_array); 7981 } while ((rc != 0) && (++cnt < I2C_WA_RETRY_CNT)); 7982 7983 if (rc == 0) { 7984 for (i = (addr - addr32); i < byte_cnt + (addr - addr32); i++) { 7985 o_buf[j] = *((u8 *)data_array + i); 7986 j++; 7987 } 7988 } 7989 7990 return rc; 7991 } 7992 7993 static int bnx2x_8727_read_sfp_module_eeprom(struct bnx2x_phy *phy, 7994 struct link_params *params, 7995 u8 dev_addr, u16 addr, u8 byte_cnt, 7996 u8 *o_buf, u8 is_init) 7997 { 7998 struct bnx2x *bp = params->bp; 7999 u16 val, i; 8000 8001 if (byte_cnt > SFP_EEPROM_PAGE_SIZE) { 8002 DP(NETIF_MSG_LINK, 8003 "Reading from eeprom is limited to 0xf\n"); 8004 return -EINVAL; 8005 } 8006 8007 /* Set 2-wire transfer rate of SFP+ module EEPROM 8008 * to 100Khz since some DACs(direct attached cables) do 8009 * not work at 400Khz. 8010 */ 8011 bnx2x_cl45_write(bp, phy, 8012 MDIO_PMA_DEVAD, 8013 MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR, 8014 ((dev_addr << 8) | 1)); 8015 8016 /* Need to read from 1.8000 to clear it */ 8017 bnx2x_cl45_read(bp, phy, 8018 MDIO_PMA_DEVAD, 8019 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, 8020 &val); 8021 8022 /* Set the read command byte count */ 8023 bnx2x_cl45_write(bp, phy, 8024 MDIO_PMA_DEVAD, 8025 MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT, 8026 ((byte_cnt < 2) ? 2 : byte_cnt)); 8027 8028 /* Set the read command address */ 8029 bnx2x_cl45_write(bp, phy, 8030 MDIO_PMA_DEVAD, 8031 MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR, 8032 addr); 8033 /* Set the destination address */ 8034 bnx2x_cl45_write(bp, phy, 8035 MDIO_PMA_DEVAD, 8036 0x8004, 8037 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF); 8038 8039 /* Activate read command */ 8040 bnx2x_cl45_write(bp, phy, 8041 MDIO_PMA_DEVAD, 8042 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, 8043 0x8002); 8044 /* Wait appropriate time for two-wire command to finish before 8045 * polling the status register 8046 */ 8047 usleep_range(1000, 2000); 8048 8049 /* Wait up to 500us for command complete status */ 8050 for (i = 0; i < 100; i++) { 8051 bnx2x_cl45_read(bp, phy, 8052 MDIO_PMA_DEVAD, 8053 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); 8054 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == 8055 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) 8056 break; 8057 udelay(5); 8058 } 8059 8060 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) != 8061 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) { 8062 DP(NETIF_MSG_LINK, 8063 "Got bad status 0x%x when reading from SFP+ EEPROM\n", 8064 (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK)); 8065 return -EFAULT; 8066 } 8067 8068 /* Read the buffer */ 8069 for (i = 0; i < byte_cnt; i++) { 8070 bnx2x_cl45_read(bp, phy, 8071 MDIO_PMA_DEVAD, 8072 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF + i, &val); 8073 o_buf[i] = (u8)(val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK); 8074 } 8075 8076 for (i = 0; i < 100; i++) { 8077 bnx2x_cl45_read(bp, phy, 8078 MDIO_PMA_DEVAD, 8079 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); 8080 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == 8081 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE) 8082 return 0; 8083 usleep_range(1000, 2000); 8084 } 8085 8086 return -EINVAL; 8087 } 8088 int bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy, 8089 struct link_params *params, u8 dev_addr, 8090 u16 addr, u16 byte_cnt, u8 *o_buf) 8091 { 8092 int rc = 0; 8093 struct bnx2x *bp = params->bp; 8094 u8 xfer_size; 8095 u8 *user_data = o_buf; 8096 read_sfp_module_eeprom_func_p read_func; 8097 8098 if ((dev_addr != 0xa0) && (dev_addr != 0xa2)) { 8099 DP(NETIF_MSG_LINK, "invalid dev_addr 0x%x\n", dev_addr); 8100 return -EINVAL; 8101 } 8102 8103 switch (phy->type) { 8104 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: 8105 read_func = bnx2x_8726_read_sfp_module_eeprom; 8106 break; 8107 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: 8108 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722: 8109 read_func = bnx2x_8727_read_sfp_module_eeprom; 8110 break; 8111 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT: 8112 read_func = bnx2x_warpcore_read_sfp_module_eeprom; 8113 break; 8114 default: 8115 return -EOPNOTSUPP; 8116 } 8117 8118 while (!rc && (byte_cnt > 0)) { 8119 xfer_size = (byte_cnt > SFP_EEPROM_PAGE_SIZE) ? 8120 SFP_EEPROM_PAGE_SIZE : byte_cnt; 8121 rc = read_func(phy, params, dev_addr, addr, xfer_size, 8122 user_data, 0); 8123 byte_cnt -= xfer_size; 8124 user_data += xfer_size; 8125 addr += xfer_size; 8126 } 8127 return rc; 8128 } 8129 8130 static int bnx2x_get_edc_mode(struct bnx2x_phy *phy, 8131 struct link_params *params, 8132 u16 *edc_mode) 8133 { 8134 struct bnx2x *bp = params->bp; 8135 u32 sync_offset = 0, phy_idx, media_types; 8136 u8 val[SFP_EEPROM_FC_TX_TECH_ADDR + 1], check_limiting_mode = 0; 8137 *edc_mode = EDC_MODE_LIMITING; 8138 phy->media_type = ETH_PHY_UNSPECIFIED; 8139 /* First check for copper cable */ 8140 if (bnx2x_read_sfp_module_eeprom(phy, 8141 params, 8142 I2C_DEV_ADDR_A0, 8143 0, 8144 SFP_EEPROM_FC_TX_TECH_ADDR + 1, 8145 (u8 *)val) != 0) { 8146 DP(NETIF_MSG_LINK, "Failed to read from SFP+ module EEPROM\n"); 8147 return -EINVAL; 8148 } 8149 params->link_attr_sync &= ~LINK_SFP_EEPROM_COMP_CODE_MASK; 8150 params->link_attr_sync |= val[SFP_EEPROM_10G_COMP_CODE_ADDR] << 8151 LINK_SFP_EEPROM_COMP_CODE_SHIFT; 8152 bnx2x_update_link_attr(params, params->link_attr_sync); 8153 switch (val[SFP_EEPROM_CON_TYPE_ADDR]) { 8154 case SFP_EEPROM_CON_TYPE_VAL_COPPER: 8155 { 8156 u8 copper_module_type; 8157 phy->media_type = ETH_PHY_DA_TWINAX; 8158 /* Check if its active cable (includes SFP+ module) 8159 * of passive cable 8160 */ 8161 copper_module_type = val[SFP_EEPROM_FC_TX_TECH_ADDR]; 8162 8163 if (copper_module_type & 8164 SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) { 8165 DP(NETIF_MSG_LINK, "Active Copper cable detected\n"); 8166 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) 8167 *edc_mode = EDC_MODE_ACTIVE_DAC; 8168 else 8169 check_limiting_mode = 1; 8170 } else { 8171 *edc_mode = EDC_MODE_PASSIVE_DAC; 8172 /* Even in case PASSIVE_DAC indication is not set, 8173 * treat it as a passive DAC cable, since some cables 8174 * don't have this indication. 8175 */ 8176 if (copper_module_type & 8177 SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE) { 8178 DP(NETIF_MSG_LINK, 8179 "Passive Copper cable detected\n"); 8180 } else { 8181 DP(NETIF_MSG_LINK, 8182 "Unknown copper-cable-type\n"); 8183 } 8184 } 8185 break; 8186 } 8187 case SFP_EEPROM_CON_TYPE_VAL_UNKNOWN: 8188 case SFP_EEPROM_CON_TYPE_VAL_LC: 8189 case SFP_EEPROM_CON_TYPE_VAL_RJ45: 8190 check_limiting_mode = 1; 8191 if (((val[SFP_EEPROM_10G_COMP_CODE_ADDR] & 8192 (SFP_EEPROM_10G_COMP_CODE_SR_MASK | 8193 SFP_EEPROM_10G_COMP_CODE_LR_MASK | 8194 SFP_EEPROM_10G_COMP_CODE_LRM_MASK)) == 0) && 8195 (val[SFP_EEPROM_1G_COMP_CODE_ADDR] != 0)) { 8196 DP(NETIF_MSG_LINK, "1G SFP module detected\n"); 8197 phy->media_type = ETH_PHY_SFP_1G_FIBER; 8198 if (phy->req_line_speed != SPEED_1000) { 8199 u8 gport = params->port; 8200 phy->req_line_speed = SPEED_1000; 8201 if (!CHIP_IS_E1x(bp)) { 8202 gport = BP_PATH(bp) + 8203 (params->port << 1); 8204 } 8205 netdev_err(bp->dev, 8206 "Warning: Link speed was forced to 1000Mbps. Current SFP module in port %d is not compliant with 10G Ethernet\n", 8207 gport); 8208 } 8209 if (val[SFP_EEPROM_1G_COMP_CODE_ADDR] & 8210 SFP_EEPROM_1G_COMP_CODE_BASE_T) { 8211 bnx2x_sfp_set_transmitter(params, phy, 0); 8212 msleep(40); 8213 bnx2x_sfp_set_transmitter(params, phy, 1); 8214 } 8215 } else { 8216 int idx, cfg_idx = 0; 8217 DP(NETIF_MSG_LINK, "10G Optic module detected\n"); 8218 for (idx = INT_PHY; idx < MAX_PHYS; idx++) { 8219 if (params->phy[idx].type == phy->type) { 8220 cfg_idx = LINK_CONFIG_IDX(idx); 8221 break; 8222 } 8223 } 8224 phy->media_type = ETH_PHY_SFPP_10G_FIBER; 8225 phy->req_line_speed = params->req_line_speed[cfg_idx]; 8226 } 8227 break; 8228 default: 8229 DP(NETIF_MSG_LINK, "Unable to determine module type 0x%x !!!\n", 8230 val[SFP_EEPROM_CON_TYPE_ADDR]); 8231 return -EINVAL; 8232 } 8233 sync_offset = params->shmem_base + 8234 offsetof(struct shmem_region, 8235 dev_info.port_hw_config[params->port].media_type); 8236 media_types = REG_RD(bp, sync_offset); 8237 /* Update media type for non-PMF sync */ 8238 for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) { 8239 if (&(params->phy[phy_idx]) == phy) { 8240 media_types &= ~(PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK << 8241 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx)); 8242 media_types |= ((phy->media_type & 8243 PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) << 8244 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx)); 8245 break; 8246 } 8247 } 8248 REG_WR(bp, sync_offset, media_types); 8249 if (check_limiting_mode) { 8250 u8 options[SFP_EEPROM_OPTIONS_SIZE]; 8251 if (bnx2x_read_sfp_module_eeprom(phy, 8252 params, 8253 I2C_DEV_ADDR_A0, 8254 SFP_EEPROM_OPTIONS_ADDR, 8255 SFP_EEPROM_OPTIONS_SIZE, 8256 options) != 0) { 8257 DP(NETIF_MSG_LINK, 8258 "Failed to read Option field from module EEPROM\n"); 8259 return -EINVAL; 8260 } 8261 if ((options[0] & SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK)) 8262 *edc_mode = EDC_MODE_LINEAR; 8263 else 8264 *edc_mode = EDC_MODE_LIMITING; 8265 } 8266 DP(NETIF_MSG_LINK, "EDC mode is set to 0x%x\n", *edc_mode); 8267 return 0; 8268 } 8269 /* This function read the relevant field from the module (SFP+), and verify it 8270 * is compliant with this board 8271 */ 8272 static int bnx2x_verify_sfp_module(struct bnx2x_phy *phy, 8273 struct link_params *params) 8274 { 8275 struct bnx2x *bp = params->bp; 8276 u32 val, cmd; 8277 u32 fw_resp, fw_cmd_param; 8278 char vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE+1]; 8279 char vendor_pn[SFP_EEPROM_PART_NO_SIZE+1]; 8280 phy->flags &= ~FLAGS_SFP_NOT_APPROVED; 8281 val = REG_RD(bp, params->shmem_base + 8282 offsetof(struct shmem_region, dev_info. 8283 port_feature_config[params->port].config)); 8284 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == 8285 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT) { 8286 DP(NETIF_MSG_LINK, "NOT enforcing module verification\n"); 8287 return 0; 8288 } 8289 8290 if (params->feature_config_flags & 8291 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY) { 8292 /* Use specific phy request */ 8293 cmd = DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL; 8294 } else if (params->feature_config_flags & 8295 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY) { 8296 /* Use first phy request only in case of non-dual media*/ 8297 if (DUAL_MEDIA(params)) { 8298 DP(NETIF_MSG_LINK, 8299 "FW does not support OPT MDL verification\n"); 8300 return -EINVAL; 8301 } 8302 cmd = DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL; 8303 } else { 8304 /* No support in OPT MDL detection */ 8305 DP(NETIF_MSG_LINK, 8306 "FW does not support OPT MDL verification\n"); 8307 return -EINVAL; 8308 } 8309 8310 fw_cmd_param = FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl); 8311 fw_resp = bnx2x_fw_command(bp, cmd, fw_cmd_param); 8312 if (fw_resp == FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS) { 8313 DP(NETIF_MSG_LINK, "Approved module\n"); 8314 return 0; 8315 } 8316 8317 /* Format the warning message */ 8318 if (bnx2x_read_sfp_module_eeprom(phy, 8319 params, 8320 I2C_DEV_ADDR_A0, 8321 SFP_EEPROM_VENDOR_NAME_ADDR, 8322 SFP_EEPROM_VENDOR_NAME_SIZE, 8323 (u8 *)vendor_name)) 8324 vendor_name[0] = '\0'; 8325 else 8326 vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE] = '\0'; 8327 if (bnx2x_read_sfp_module_eeprom(phy, 8328 params, 8329 I2C_DEV_ADDR_A0, 8330 SFP_EEPROM_PART_NO_ADDR, 8331 SFP_EEPROM_PART_NO_SIZE, 8332 (u8 *)vendor_pn)) 8333 vendor_pn[0] = '\0'; 8334 else 8335 vendor_pn[SFP_EEPROM_PART_NO_SIZE] = '\0'; 8336 8337 netdev_err(bp->dev, "Warning: Unqualified SFP+ module detected," 8338 " Port %d from %s part number %s\n", 8339 params->port, vendor_name, vendor_pn); 8340 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) != 8341 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG) 8342 phy->flags |= FLAGS_SFP_NOT_APPROVED; 8343 return -EINVAL; 8344 } 8345 8346 static int bnx2x_wait_for_sfp_module_initialized(struct bnx2x_phy *phy, 8347 struct link_params *params) 8348 8349 { 8350 u8 val; 8351 int rc; 8352 struct bnx2x *bp = params->bp; 8353 u16 timeout; 8354 /* Initialization time after hot-plug may take up to 300ms for 8355 * some phys type ( e.g. JDSU ) 8356 */ 8357 8358 for (timeout = 0; timeout < 60; timeout++) { 8359 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) 8360 rc = bnx2x_warpcore_read_sfp_module_eeprom( 8361 phy, params, I2C_DEV_ADDR_A0, 1, 1, &val, 8362 1); 8363 else 8364 rc = bnx2x_read_sfp_module_eeprom(phy, params, 8365 I2C_DEV_ADDR_A0, 8366 1, 1, &val); 8367 if (rc == 0) { 8368 DP(NETIF_MSG_LINK, 8369 "SFP+ module initialization took %d ms\n", 8370 timeout * 5); 8371 return 0; 8372 } 8373 usleep_range(5000, 10000); 8374 } 8375 rc = bnx2x_read_sfp_module_eeprom(phy, params, I2C_DEV_ADDR_A0, 8376 1, 1, &val); 8377 return rc; 8378 } 8379 8380 static void bnx2x_8727_power_module(struct bnx2x *bp, 8381 struct bnx2x_phy *phy, 8382 u8 is_power_up) { 8383 /* Make sure GPIOs are not using for LED mode */ 8384 u16 val; 8385 /* In the GPIO register, bit 4 is use to determine if the GPIOs are 8386 * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for 8387 * output 8388 * Bits 0-1 determine the GPIOs value for OUTPUT in case bit 4 val is 0 8389 * Bits 8-9 determine the GPIOs value for INPUT in case bit 4 val is 1 8390 * where the 1st bit is the over-current(only input), and 2nd bit is 8391 * for power( only output ) 8392 * 8393 * In case of NOC feature is disabled and power is up, set GPIO control 8394 * as input to enable listening of over-current indication 8395 */ 8396 if (phy->flags & FLAGS_NOC) 8397 return; 8398 if (is_power_up) 8399 val = (1<<4); 8400 else 8401 /* Set GPIO control to OUTPUT, and set the power bit 8402 * to according to the is_power_up 8403 */ 8404 val = (1<<1); 8405 8406 bnx2x_cl45_write(bp, phy, 8407 MDIO_PMA_DEVAD, 8408 MDIO_PMA_REG_8727_GPIO_CTRL, 8409 val); 8410 } 8411 8412 static int bnx2x_8726_set_limiting_mode(struct bnx2x *bp, 8413 struct bnx2x_phy *phy, 8414 u16 edc_mode) 8415 { 8416 u16 cur_limiting_mode; 8417 8418 bnx2x_cl45_read(bp, phy, 8419 MDIO_PMA_DEVAD, 8420 MDIO_PMA_REG_ROM_VER2, 8421 &cur_limiting_mode); 8422 DP(NETIF_MSG_LINK, "Current Limiting mode is 0x%x\n", 8423 cur_limiting_mode); 8424 8425 if (edc_mode == EDC_MODE_LIMITING) { 8426 DP(NETIF_MSG_LINK, "Setting LIMITING MODE\n"); 8427 bnx2x_cl45_write(bp, phy, 8428 MDIO_PMA_DEVAD, 8429 MDIO_PMA_REG_ROM_VER2, 8430 EDC_MODE_LIMITING); 8431 } else { /* LRM mode ( default )*/ 8432 8433 DP(NETIF_MSG_LINK, "Setting LRM MODE\n"); 8434 8435 /* Changing to LRM mode takes quite few seconds. So do it only 8436 * if current mode is limiting (default is LRM) 8437 */ 8438 if (cur_limiting_mode != EDC_MODE_LIMITING) 8439 return 0; 8440 8441 bnx2x_cl45_write(bp, phy, 8442 MDIO_PMA_DEVAD, 8443 MDIO_PMA_REG_LRM_MODE, 8444 0); 8445 bnx2x_cl45_write(bp, phy, 8446 MDIO_PMA_DEVAD, 8447 MDIO_PMA_REG_ROM_VER2, 8448 0x128); 8449 bnx2x_cl45_write(bp, phy, 8450 MDIO_PMA_DEVAD, 8451 MDIO_PMA_REG_MISC_CTRL0, 8452 0x4008); 8453 bnx2x_cl45_write(bp, phy, 8454 MDIO_PMA_DEVAD, 8455 MDIO_PMA_REG_LRM_MODE, 8456 0xaaaa); 8457 } 8458 return 0; 8459 } 8460 8461 static int bnx2x_8727_set_limiting_mode(struct bnx2x *bp, 8462 struct bnx2x_phy *phy, 8463 u16 edc_mode) 8464 { 8465 u16 phy_identifier; 8466 u16 rom_ver2_val; 8467 bnx2x_cl45_read(bp, phy, 8468 MDIO_PMA_DEVAD, 8469 MDIO_PMA_REG_PHY_IDENTIFIER, 8470 &phy_identifier); 8471 8472 bnx2x_cl45_write(bp, phy, 8473 MDIO_PMA_DEVAD, 8474 MDIO_PMA_REG_PHY_IDENTIFIER, 8475 (phy_identifier & ~(1<<9))); 8476 8477 bnx2x_cl45_read(bp, phy, 8478 MDIO_PMA_DEVAD, 8479 MDIO_PMA_REG_ROM_VER2, 8480 &rom_ver2_val); 8481 /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */ 8482 bnx2x_cl45_write(bp, phy, 8483 MDIO_PMA_DEVAD, 8484 MDIO_PMA_REG_ROM_VER2, 8485 (rom_ver2_val & 0xff00) | (edc_mode & 0x00ff)); 8486 8487 bnx2x_cl45_write(bp, phy, 8488 MDIO_PMA_DEVAD, 8489 MDIO_PMA_REG_PHY_IDENTIFIER, 8490 (phy_identifier | (1<<9))); 8491 8492 return 0; 8493 } 8494 8495 static void bnx2x_8727_specific_func(struct bnx2x_phy *phy, 8496 struct link_params *params, 8497 u32 action) 8498 { 8499 struct bnx2x *bp = params->bp; 8500 u16 val; 8501 switch (action) { 8502 case DISABLE_TX: 8503 bnx2x_sfp_set_transmitter(params, phy, 0); 8504 break; 8505 case ENABLE_TX: 8506 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED)) 8507 bnx2x_sfp_set_transmitter(params, phy, 1); 8508 break; 8509 case PHY_INIT: 8510 bnx2x_cl45_write(bp, phy, 8511 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, 8512 (1<<2) | (1<<5)); 8513 bnx2x_cl45_write(bp, phy, 8514 MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL, 8515 0); 8516 bnx2x_cl45_write(bp, phy, 8517 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0006); 8518 /* Make MOD_ABS give interrupt on change */ 8519 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 8520 MDIO_PMA_REG_8727_PCS_OPT_CTRL, 8521 &val); 8522 val |= (1<<12); 8523 if (phy->flags & FLAGS_NOC) 8524 val |= (3<<5); 8525 /* Set 8727 GPIOs to input to allow reading from the 8727 GPIO0 8526 * status which reflect SFP+ module over-current 8527 */ 8528 if (!(phy->flags & FLAGS_NOC)) 8529 val &= 0xff8f; /* Reset bits 4-6 */ 8530 bnx2x_cl45_write(bp, phy, 8531 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL, 8532 val); 8533 break; 8534 default: 8535 DP(NETIF_MSG_LINK, "Function 0x%x not supported by 8727\n", 8536 action); 8537 return; 8538 } 8539 } 8540 8541 static void bnx2x_set_e1e2_module_fault_led(struct link_params *params, 8542 u8 gpio_mode) 8543 { 8544 struct bnx2x *bp = params->bp; 8545 8546 u32 fault_led_gpio = REG_RD(bp, params->shmem_base + 8547 offsetof(struct shmem_region, 8548 dev_info.port_hw_config[params->port].sfp_ctrl)) & 8549 PORT_HW_CFG_FAULT_MODULE_LED_MASK; 8550 switch (fault_led_gpio) { 8551 case PORT_HW_CFG_FAULT_MODULE_LED_DISABLED: 8552 return; 8553 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO0: 8554 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO1: 8555 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO2: 8556 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO3: 8557 { 8558 u8 gpio_port = bnx2x_get_gpio_port(params); 8559 u16 gpio_pin = fault_led_gpio - 8560 PORT_HW_CFG_FAULT_MODULE_LED_GPIO0; 8561 DP(NETIF_MSG_LINK, "Set fault module-detected led " 8562 "pin %x port %x mode %x\n", 8563 gpio_pin, gpio_port, gpio_mode); 8564 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port); 8565 } 8566 break; 8567 default: 8568 DP(NETIF_MSG_LINK, "Error: Invalid fault led mode 0x%x\n", 8569 fault_led_gpio); 8570 } 8571 } 8572 8573 static void bnx2x_set_e3_module_fault_led(struct link_params *params, 8574 u8 gpio_mode) 8575 { 8576 u32 pin_cfg; 8577 u8 port = params->port; 8578 struct bnx2x *bp = params->bp; 8579 pin_cfg = (REG_RD(bp, params->shmem_base + 8580 offsetof(struct shmem_region, 8581 dev_info.port_hw_config[port].e3_sfp_ctrl)) & 8582 PORT_HW_CFG_E3_FAULT_MDL_LED_MASK) >> 8583 PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT; 8584 DP(NETIF_MSG_LINK, "Setting Fault LED to %d using pin cfg %d\n", 8585 gpio_mode, pin_cfg); 8586 bnx2x_set_cfg_pin(bp, pin_cfg, gpio_mode); 8587 } 8588 8589 static void bnx2x_set_sfp_module_fault_led(struct link_params *params, 8590 u8 gpio_mode) 8591 { 8592 struct bnx2x *bp = params->bp; 8593 DP(NETIF_MSG_LINK, "Setting SFP+ module fault LED to %d\n", gpio_mode); 8594 if (CHIP_IS_E3(bp)) { 8595 /* Low ==> if SFP+ module is supported otherwise 8596 * High ==> if SFP+ module is not on the approved vendor list 8597 */ 8598 bnx2x_set_e3_module_fault_led(params, gpio_mode); 8599 } else 8600 bnx2x_set_e1e2_module_fault_led(params, gpio_mode); 8601 } 8602 8603 static void bnx2x_warpcore_hw_reset(struct bnx2x_phy *phy, 8604 struct link_params *params) 8605 { 8606 struct bnx2x *bp = params->bp; 8607 bnx2x_warpcore_power_module(params, 0); 8608 /* Put Warpcore in low power mode */ 8609 REG_WR(bp, MISC_REG_WC0_RESET, 0x0c0e); 8610 8611 /* Put LCPLL in low power mode */ 8612 REG_WR(bp, MISC_REG_LCPLL_E40_PWRDWN, 1); 8613 REG_WR(bp, MISC_REG_LCPLL_E40_RESETB_ANA, 0); 8614 REG_WR(bp, MISC_REG_LCPLL_E40_RESETB_DIG, 0); 8615 } 8616 8617 static void bnx2x_power_sfp_module(struct link_params *params, 8618 struct bnx2x_phy *phy, 8619 u8 power) 8620 { 8621 struct bnx2x *bp = params->bp; 8622 DP(NETIF_MSG_LINK, "Setting SFP+ power to %x\n", power); 8623 8624 switch (phy->type) { 8625 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: 8626 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722: 8627 bnx2x_8727_power_module(params->bp, phy, power); 8628 break; 8629 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT: 8630 bnx2x_warpcore_power_module(params, power); 8631 break; 8632 default: 8633 break; 8634 } 8635 } 8636 static void bnx2x_warpcore_set_limiting_mode(struct link_params *params, 8637 struct bnx2x_phy *phy, 8638 u16 edc_mode) 8639 { 8640 u16 val = 0; 8641 u16 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT; 8642 struct bnx2x *bp = params->bp; 8643 8644 u8 lane = bnx2x_get_warpcore_lane(phy, params); 8645 /* This is a global register which controls all lanes */ 8646 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 8647 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val); 8648 val &= ~(0xf << (lane << 2)); 8649 8650 switch (edc_mode) { 8651 case EDC_MODE_LINEAR: 8652 case EDC_MODE_LIMITING: 8653 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT; 8654 break; 8655 case EDC_MODE_PASSIVE_DAC: 8656 case EDC_MODE_ACTIVE_DAC: 8657 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC; 8658 break; 8659 default: 8660 break; 8661 } 8662 8663 val |= (mode << (lane << 2)); 8664 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 8665 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, val); 8666 /* A must read */ 8667 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 8668 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val); 8669 8670 /* Restart microcode to re-read the new mode */ 8671 bnx2x_warpcore_reset_lane(bp, phy, 1); 8672 bnx2x_warpcore_reset_lane(bp, phy, 0); 8673 8674 } 8675 8676 static void bnx2x_set_limiting_mode(struct link_params *params, 8677 struct bnx2x_phy *phy, 8678 u16 edc_mode) 8679 { 8680 switch (phy->type) { 8681 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: 8682 bnx2x_8726_set_limiting_mode(params->bp, phy, edc_mode); 8683 break; 8684 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: 8685 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722: 8686 bnx2x_8727_set_limiting_mode(params->bp, phy, edc_mode); 8687 break; 8688 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT: 8689 bnx2x_warpcore_set_limiting_mode(params, phy, edc_mode); 8690 break; 8691 } 8692 } 8693 8694 static int bnx2x_sfp_module_detection(struct bnx2x_phy *phy, 8695 struct link_params *params) 8696 { 8697 struct bnx2x *bp = params->bp; 8698 u16 edc_mode; 8699 int rc = 0; 8700 8701 u32 val = REG_RD(bp, params->shmem_base + 8702 offsetof(struct shmem_region, dev_info. 8703 port_feature_config[params->port].config)); 8704 /* Enabled transmitter by default */ 8705 bnx2x_sfp_set_transmitter(params, phy, 1); 8706 DP(NETIF_MSG_LINK, "SFP+ module plugged in/out detected on port %d\n", 8707 params->port); 8708 /* Power up module */ 8709 bnx2x_power_sfp_module(params, phy, 1); 8710 if (bnx2x_get_edc_mode(phy, params, &edc_mode) != 0) { 8711 DP(NETIF_MSG_LINK, "Failed to get valid module type\n"); 8712 return -EINVAL; 8713 } else if (bnx2x_verify_sfp_module(phy, params) != 0) { 8714 /* Check SFP+ module compatibility */ 8715 DP(NETIF_MSG_LINK, "Module verification failed!!\n"); 8716 rc = -EINVAL; 8717 /* Turn on fault module-detected led */ 8718 bnx2x_set_sfp_module_fault_led(params, 8719 MISC_REGISTERS_GPIO_HIGH); 8720 8721 /* Check if need to power down the SFP+ module */ 8722 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == 8723 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN) { 8724 DP(NETIF_MSG_LINK, "Shutdown SFP+ module!!\n"); 8725 bnx2x_power_sfp_module(params, phy, 0); 8726 return rc; 8727 } 8728 } else { 8729 /* Turn off fault module-detected led */ 8730 bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_LOW); 8731 } 8732 8733 /* Check and set limiting mode / LRM mode on 8726. On 8727 it 8734 * is done automatically 8735 */ 8736 bnx2x_set_limiting_mode(params, phy, edc_mode); 8737 8738 /* Disable transmit for this module if the module is not approved, and 8739 * laser needs to be disabled. 8740 */ 8741 if ((rc) && 8742 ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == 8743 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)) 8744 bnx2x_sfp_set_transmitter(params, phy, 0); 8745 8746 return rc; 8747 } 8748 8749 void bnx2x_handle_module_detect_int(struct link_params *params) 8750 { 8751 struct bnx2x *bp = params->bp; 8752 struct bnx2x_phy *phy; 8753 u32 gpio_val; 8754 u8 gpio_num, gpio_port; 8755 if (CHIP_IS_E3(bp)) { 8756 phy = ¶ms->phy[INT_PHY]; 8757 /* Always enable TX laser,will be disabled in case of fault */ 8758 bnx2x_sfp_set_transmitter(params, phy, 1); 8759 } else { 8760 phy = ¶ms->phy[EXT_PHY1]; 8761 } 8762 if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id, params->shmem_base, 8763 params->port, &gpio_num, &gpio_port) == 8764 -EINVAL) { 8765 DP(NETIF_MSG_LINK, "Failed to get MOD_ABS interrupt config\n"); 8766 return; 8767 } 8768 8769 /* Set valid module led off */ 8770 bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_HIGH); 8771 8772 /* Get current gpio val reflecting module plugged in / out*/ 8773 gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port); 8774 8775 /* Call the handling function in case module is detected */ 8776 if (gpio_val == 0) { 8777 bnx2x_set_mdio_emac_per_phy(bp, params); 8778 bnx2x_set_aer_mmd(params, phy); 8779 8780 bnx2x_power_sfp_module(params, phy, 1); 8781 bnx2x_set_gpio_int(bp, gpio_num, 8782 MISC_REGISTERS_GPIO_INT_OUTPUT_CLR, 8783 gpio_port); 8784 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0) { 8785 bnx2x_sfp_module_detection(phy, params); 8786 if (CHIP_IS_E3(bp)) { 8787 u16 rx_tx_in_reset; 8788 /* In case WC is out of reset, reconfigure the 8789 * link speed while taking into account 1G 8790 * module limitation. 8791 */ 8792 bnx2x_cl45_read(bp, phy, 8793 MDIO_WC_DEVAD, 8794 MDIO_WC_REG_DIGITAL5_MISC6, 8795 &rx_tx_in_reset); 8796 if ((!rx_tx_in_reset) && 8797 (params->link_flags & 8798 PHY_INITIALIZED)) { 8799 bnx2x_warpcore_reset_lane(bp, phy, 1); 8800 bnx2x_warpcore_config_sfi(phy, params); 8801 bnx2x_warpcore_reset_lane(bp, phy, 0); 8802 } 8803 } 8804 } else { 8805 DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n"); 8806 } 8807 } else { 8808 bnx2x_set_gpio_int(bp, gpio_num, 8809 MISC_REGISTERS_GPIO_INT_OUTPUT_SET, 8810 gpio_port); 8811 /* Module was plugged out. 8812 * Disable transmit for this module 8813 */ 8814 phy->media_type = ETH_PHY_NOT_PRESENT; 8815 } 8816 } 8817 8818 /******************************************************************/ 8819 /* Used by 8706 and 8727 */ 8820 /******************************************************************/ 8821 static void bnx2x_sfp_mask_fault(struct bnx2x *bp, 8822 struct bnx2x_phy *phy, 8823 u16 alarm_status_offset, 8824 u16 alarm_ctrl_offset) 8825 { 8826 u16 alarm_status, val; 8827 bnx2x_cl45_read(bp, phy, 8828 MDIO_PMA_DEVAD, alarm_status_offset, 8829 &alarm_status); 8830 bnx2x_cl45_read(bp, phy, 8831 MDIO_PMA_DEVAD, alarm_status_offset, 8832 &alarm_status); 8833 /* Mask or enable the fault event. */ 8834 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, &val); 8835 if (alarm_status & (1<<0)) 8836 val &= ~(1<<0); 8837 else 8838 val |= (1<<0); 8839 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, val); 8840 } 8841 /******************************************************************/ 8842 /* common BCM8706/BCM8726 PHY SECTION */ 8843 /******************************************************************/ 8844 static u8 bnx2x_8706_8726_read_status(struct bnx2x_phy *phy, 8845 struct link_params *params, 8846 struct link_vars *vars) 8847 { 8848 u8 link_up = 0; 8849 u16 val1, val2, rx_sd, pcs_status; 8850 struct bnx2x *bp = params->bp; 8851 DP(NETIF_MSG_LINK, "XGXS 8706/8726\n"); 8852 /* Clear RX Alarm*/ 8853 bnx2x_cl45_read(bp, phy, 8854 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2); 8855 8856 bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT, 8857 MDIO_PMA_LASI_TXCTRL); 8858 8859 /* Clear LASI indication*/ 8860 bnx2x_cl45_read(bp, phy, 8861 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1); 8862 bnx2x_cl45_read(bp, phy, 8863 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2); 8864 DP(NETIF_MSG_LINK, "8706/8726 LASI status 0x%x--> 0x%x\n", val1, val2); 8865 8866 bnx2x_cl45_read(bp, phy, 8867 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd); 8868 bnx2x_cl45_read(bp, phy, 8869 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &pcs_status); 8870 bnx2x_cl45_read(bp, phy, 8871 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2); 8872 bnx2x_cl45_read(bp, phy, 8873 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2); 8874 8875 DP(NETIF_MSG_LINK, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps" 8876 " link_status 0x%x\n", rx_sd, pcs_status, val2); 8877 /* Link is up if both bit 0 of pmd_rx_sd and bit 0 of pcs_status 8878 * are set, or if the autoneg bit 1 is set 8879 */ 8880 link_up = ((rx_sd & pcs_status & 0x1) || (val2 & (1<<1))); 8881 if (link_up) { 8882 if (val2 & (1<<1)) 8883 vars->line_speed = SPEED_1000; 8884 else 8885 vars->line_speed = SPEED_10000; 8886 bnx2x_ext_phy_resolve_fc(phy, params, vars); 8887 vars->duplex = DUPLEX_FULL; 8888 } 8889 8890 /* Capture 10G link fault. Read twice to clear stale value. */ 8891 if (vars->line_speed == SPEED_10000) { 8892 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 8893 MDIO_PMA_LASI_TXSTAT, &val1); 8894 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 8895 MDIO_PMA_LASI_TXSTAT, &val1); 8896 if (val1 & (1<<0)) 8897 vars->fault_detected = 1; 8898 } 8899 8900 return link_up; 8901 } 8902 8903 /******************************************************************/ 8904 /* BCM8706 PHY SECTION */ 8905 /******************************************************************/ 8906 static u8 bnx2x_8706_config_init(struct bnx2x_phy *phy, 8907 struct link_params *params, 8908 struct link_vars *vars) 8909 { 8910 u32 tx_en_mode; 8911 u16 cnt, val, tmp1; 8912 struct bnx2x *bp = params->bp; 8913 8914 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 8915 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); 8916 /* HW reset */ 8917 bnx2x_ext_phy_hw_reset(bp, params->port); 8918 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040); 8919 bnx2x_wait_reset_complete(bp, phy, params); 8920 8921 /* Wait until fw is loaded */ 8922 for (cnt = 0; cnt < 100; cnt++) { 8923 bnx2x_cl45_read(bp, phy, 8924 MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER1, &val); 8925 if (val) 8926 break; 8927 usleep_range(10000, 20000); 8928 } 8929 DP(NETIF_MSG_LINK, "XGXS 8706 is initialized after %d ms\n", cnt); 8930 if ((params->feature_config_flags & 8931 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) { 8932 u8 i; 8933 u16 reg; 8934 for (i = 0; i < 4; i++) { 8935 reg = MDIO_XS_8706_REG_BANK_RX0 + 8936 i*(MDIO_XS_8706_REG_BANK_RX1 - 8937 MDIO_XS_8706_REG_BANK_RX0); 8938 bnx2x_cl45_read(bp, phy, MDIO_XS_DEVAD, reg, &val); 8939 /* Clear first 3 bits of the control */ 8940 val &= ~0x7; 8941 /* Set control bits according to configuration */ 8942 val |= (phy->rx_preemphasis[i] & 0x7); 8943 DP(NETIF_MSG_LINK, "Setting RX Equalizer to BCM8706" 8944 " reg 0x%x <-- val 0x%x\n", reg, val); 8945 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, reg, val); 8946 } 8947 } 8948 /* Force speed */ 8949 if (phy->req_line_speed == SPEED_10000) { 8950 DP(NETIF_MSG_LINK, "XGXS 8706 force 10Gbps\n"); 8951 8952 bnx2x_cl45_write(bp, phy, 8953 MDIO_PMA_DEVAD, 8954 MDIO_PMA_REG_DIGITAL_CTRL, 0x400); 8955 bnx2x_cl45_write(bp, phy, 8956 MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL, 8957 0); 8958 /* Arm LASI for link and Tx fault. */ 8959 bnx2x_cl45_write(bp, phy, 8960 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 3); 8961 } else { 8962 /* Force 1Gbps using autoneg with 1G advertisement */ 8963 8964 /* Allow CL37 through CL73 */ 8965 DP(NETIF_MSG_LINK, "XGXS 8706 AutoNeg\n"); 8966 bnx2x_cl45_write(bp, phy, 8967 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c); 8968 8969 /* Enable Full-Duplex advertisement on CL37 */ 8970 bnx2x_cl45_write(bp, phy, 8971 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LP, 0x0020); 8972 /* Enable CL37 AN */ 8973 bnx2x_cl45_write(bp, phy, 8974 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000); 8975 /* 1G support */ 8976 bnx2x_cl45_write(bp, phy, 8977 MDIO_AN_DEVAD, MDIO_AN_REG_ADV, (1<<5)); 8978 8979 /* Enable clause 73 AN */ 8980 bnx2x_cl45_write(bp, phy, 8981 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200); 8982 bnx2x_cl45_write(bp, phy, 8983 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, 8984 0x0400); 8985 bnx2x_cl45_write(bp, phy, 8986 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 8987 0x0004); 8988 } 8989 bnx2x_save_bcm_spirom_ver(bp, phy, params->port); 8990 8991 /* If TX Laser is controlled by GPIO_0, do not let PHY go into low 8992 * power mode, if TX Laser is disabled 8993 */ 8994 8995 tx_en_mode = REG_RD(bp, params->shmem_base + 8996 offsetof(struct shmem_region, 8997 dev_info.port_hw_config[params->port].sfp_ctrl)) 8998 & PORT_HW_CFG_TX_LASER_MASK; 8999 9000 if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) { 9001 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n"); 9002 bnx2x_cl45_read(bp, phy, 9003 MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, &tmp1); 9004 tmp1 |= 0x1; 9005 bnx2x_cl45_write(bp, phy, 9006 MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, tmp1); 9007 } 9008 9009 return 0; 9010 } 9011 9012 static int bnx2x_8706_read_status(struct bnx2x_phy *phy, 9013 struct link_params *params, 9014 struct link_vars *vars) 9015 { 9016 return bnx2x_8706_8726_read_status(phy, params, vars); 9017 } 9018 9019 /******************************************************************/ 9020 /* BCM8726 PHY SECTION */ 9021 /******************************************************************/ 9022 static void bnx2x_8726_config_loopback(struct bnx2x_phy *phy, 9023 struct link_params *params) 9024 { 9025 struct bnx2x *bp = params->bp; 9026 DP(NETIF_MSG_LINK, "PMA/PMD ext_phy_loopback: 8726\n"); 9027 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001); 9028 } 9029 9030 static void bnx2x_8726_external_rom_boot(struct bnx2x_phy *phy, 9031 struct link_params *params) 9032 { 9033 struct bnx2x *bp = params->bp; 9034 /* Need to wait 100ms after reset */ 9035 msleep(100); 9036 9037 /* Micro controller re-boot */ 9038 bnx2x_cl45_write(bp, phy, 9039 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x018B); 9040 9041 /* Set soft reset */ 9042 bnx2x_cl45_write(bp, phy, 9043 MDIO_PMA_DEVAD, 9044 MDIO_PMA_REG_GEN_CTRL, 9045 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET); 9046 9047 bnx2x_cl45_write(bp, phy, 9048 MDIO_PMA_DEVAD, 9049 MDIO_PMA_REG_MISC_CTRL1, 0x0001); 9050 9051 bnx2x_cl45_write(bp, phy, 9052 MDIO_PMA_DEVAD, 9053 MDIO_PMA_REG_GEN_CTRL, 9054 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP); 9055 9056 /* Wait for 150ms for microcode load */ 9057 msleep(150); 9058 9059 /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */ 9060 bnx2x_cl45_write(bp, phy, 9061 MDIO_PMA_DEVAD, 9062 MDIO_PMA_REG_MISC_CTRL1, 0x0000); 9063 9064 msleep(200); 9065 bnx2x_save_bcm_spirom_ver(bp, phy, params->port); 9066 } 9067 9068 static u8 bnx2x_8726_read_status(struct bnx2x_phy *phy, 9069 struct link_params *params, 9070 struct link_vars *vars) 9071 { 9072 struct bnx2x *bp = params->bp; 9073 u16 val1; 9074 u8 link_up = bnx2x_8706_8726_read_status(phy, params, vars); 9075 if (link_up) { 9076 bnx2x_cl45_read(bp, phy, 9077 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 9078 &val1); 9079 if (val1 & (1<<15)) { 9080 DP(NETIF_MSG_LINK, "Tx is disabled\n"); 9081 link_up = 0; 9082 vars->line_speed = 0; 9083 } 9084 } 9085 return link_up; 9086 } 9087 9088 9089 static int bnx2x_8726_config_init(struct bnx2x_phy *phy, 9090 struct link_params *params, 9091 struct link_vars *vars) 9092 { 9093 struct bnx2x *bp = params->bp; 9094 DP(NETIF_MSG_LINK, "Initializing BCM8726\n"); 9095 9096 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15); 9097 bnx2x_wait_reset_complete(bp, phy, params); 9098 9099 bnx2x_8726_external_rom_boot(phy, params); 9100 9101 /* Need to call module detected on initialization since the module 9102 * detection triggered by actual module insertion might occur before 9103 * driver is loaded, and when driver is loaded, it reset all 9104 * registers, including the transmitter 9105 */ 9106 bnx2x_sfp_module_detection(phy, params); 9107 9108 if (phy->req_line_speed == SPEED_1000) { 9109 DP(NETIF_MSG_LINK, "Setting 1G force\n"); 9110 bnx2x_cl45_write(bp, phy, 9111 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40); 9112 bnx2x_cl45_write(bp, phy, 9113 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD); 9114 bnx2x_cl45_write(bp, phy, 9115 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x5); 9116 bnx2x_cl45_write(bp, phy, 9117 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, 9118 0x400); 9119 } else if ((phy->req_line_speed == SPEED_AUTO_NEG) && 9120 (phy->speed_cap_mask & 9121 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) && 9122 ((phy->speed_cap_mask & 9123 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) != 9124 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) { 9125 DP(NETIF_MSG_LINK, "Setting 1G clause37\n"); 9126 /* Set Flow control */ 9127 bnx2x_ext_phy_set_pause(params, phy, vars); 9128 bnx2x_cl45_write(bp, phy, 9129 MDIO_AN_DEVAD, MDIO_AN_REG_ADV, 0x20); 9130 bnx2x_cl45_write(bp, phy, 9131 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c); 9132 bnx2x_cl45_write(bp, phy, 9133 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, 0x0020); 9134 bnx2x_cl45_write(bp, phy, 9135 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000); 9136 bnx2x_cl45_write(bp, phy, 9137 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200); 9138 /* Enable RX-ALARM control to receive interrupt for 1G speed 9139 * change 9140 */ 9141 bnx2x_cl45_write(bp, phy, 9142 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x4); 9143 bnx2x_cl45_write(bp, phy, 9144 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, 9145 0x400); 9146 9147 } else { /* Default 10G. Set only LASI control */ 9148 bnx2x_cl45_write(bp, phy, 9149 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 1); 9150 } 9151 9152 /* Set TX PreEmphasis if needed */ 9153 if ((params->feature_config_flags & 9154 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) { 9155 DP(NETIF_MSG_LINK, 9156 "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n", 9157 phy->tx_preemphasis[0], 9158 phy->tx_preemphasis[1]); 9159 bnx2x_cl45_write(bp, phy, 9160 MDIO_PMA_DEVAD, 9161 MDIO_PMA_REG_8726_TX_CTRL1, 9162 phy->tx_preemphasis[0]); 9163 9164 bnx2x_cl45_write(bp, phy, 9165 MDIO_PMA_DEVAD, 9166 MDIO_PMA_REG_8726_TX_CTRL2, 9167 phy->tx_preemphasis[1]); 9168 } 9169 9170 return 0; 9171 9172 } 9173 9174 static void bnx2x_8726_link_reset(struct bnx2x_phy *phy, 9175 struct link_params *params) 9176 { 9177 struct bnx2x *bp = params->bp; 9178 DP(NETIF_MSG_LINK, "bnx2x_8726_link_reset port %d\n", params->port); 9179 /* Set serial boot control for external load */ 9180 bnx2x_cl45_write(bp, phy, 9181 MDIO_PMA_DEVAD, 9182 MDIO_PMA_REG_GEN_CTRL, 0x0001); 9183 } 9184 9185 /******************************************************************/ 9186 /* BCM8727 PHY SECTION */ 9187 /******************************************************************/ 9188 9189 static void bnx2x_8727_set_link_led(struct bnx2x_phy *phy, 9190 struct link_params *params, u8 mode) 9191 { 9192 struct bnx2x *bp = params->bp; 9193 u16 led_mode_bitmask = 0; 9194 u16 gpio_pins_bitmask = 0; 9195 u16 val; 9196 /* Only NOC flavor requires to set the LED specifically */ 9197 if (!(phy->flags & FLAGS_NOC)) 9198 return; 9199 switch (mode) { 9200 case LED_MODE_FRONT_PANEL_OFF: 9201 case LED_MODE_OFF: 9202 led_mode_bitmask = 0; 9203 gpio_pins_bitmask = 0x03; 9204 break; 9205 case LED_MODE_ON: 9206 led_mode_bitmask = 0; 9207 gpio_pins_bitmask = 0x02; 9208 break; 9209 case LED_MODE_OPER: 9210 led_mode_bitmask = 0x60; 9211 gpio_pins_bitmask = 0x11; 9212 break; 9213 } 9214 bnx2x_cl45_read(bp, phy, 9215 MDIO_PMA_DEVAD, 9216 MDIO_PMA_REG_8727_PCS_OPT_CTRL, 9217 &val); 9218 val &= 0xff8f; 9219 val |= led_mode_bitmask; 9220 bnx2x_cl45_write(bp, phy, 9221 MDIO_PMA_DEVAD, 9222 MDIO_PMA_REG_8727_PCS_OPT_CTRL, 9223 val); 9224 bnx2x_cl45_read(bp, phy, 9225 MDIO_PMA_DEVAD, 9226 MDIO_PMA_REG_8727_GPIO_CTRL, 9227 &val); 9228 val &= 0xffe0; 9229 val |= gpio_pins_bitmask; 9230 bnx2x_cl45_write(bp, phy, 9231 MDIO_PMA_DEVAD, 9232 MDIO_PMA_REG_8727_GPIO_CTRL, 9233 val); 9234 } 9235 static void bnx2x_8727_hw_reset(struct bnx2x_phy *phy, 9236 struct link_params *params) { 9237 u32 swap_val, swap_override; 9238 u8 port; 9239 /* The PHY reset is controlled by GPIO 1. Fake the port number 9240 * to cancel the swap done in set_gpio() 9241 */ 9242 struct bnx2x *bp = params->bp; 9243 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); 9244 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); 9245 port = (swap_val && swap_override) ^ 1; 9246 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, 9247 MISC_REGISTERS_GPIO_OUTPUT_LOW, port); 9248 } 9249 9250 static void bnx2x_8727_config_speed(struct bnx2x_phy *phy, 9251 struct link_params *params) 9252 { 9253 struct bnx2x *bp = params->bp; 9254 u16 tmp1, val; 9255 /* Set option 1G speed */ 9256 if ((phy->req_line_speed == SPEED_1000) || 9257 (phy->media_type == ETH_PHY_SFP_1G_FIBER)) { 9258 DP(NETIF_MSG_LINK, "Setting 1G force\n"); 9259 bnx2x_cl45_write(bp, phy, 9260 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40); 9261 bnx2x_cl45_write(bp, phy, 9262 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD); 9263 bnx2x_cl45_read(bp, phy, 9264 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, &tmp1); 9265 DP(NETIF_MSG_LINK, "1.7 = 0x%x\n", tmp1); 9266 /* Power down the XAUI until link is up in case of dual-media 9267 * and 1G 9268 */ 9269 if (DUAL_MEDIA(params)) { 9270 bnx2x_cl45_read(bp, phy, 9271 MDIO_PMA_DEVAD, 9272 MDIO_PMA_REG_8727_PCS_GP, &val); 9273 val |= (3<<10); 9274 bnx2x_cl45_write(bp, phy, 9275 MDIO_PMA_DEVAD, 9276 MDIO_PMA_REG_8727_PCS_GP, val); 9277 } 9278 } else if ((phy->req_line_speed == SPEED_AUTO_NEG) && 9279 ((phy->speed_cap_mask & 9280 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) && 9281 ((phy->speed_cap_mask & 9282 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) != 9283 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) { 9284 9285 DP(NETIF_MSG_LINK, "Setting 1G clause37\n"); 9286 bnx2x_cl45_write(bp, phy, 9287 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 0); 9288 bnx2x_cl45_write(bp, phy, 9289 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1300); 9290 } else { 9291 /* Since the 8727 has only single reset pin, need to set the 10G 9292 * registers although it is default 9293 */ 9294 bnx2x_cl45_write(bp, phy, 9295 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 9296 0x0020); 9297 bnx2x_cl45_write(bp, phy, 9298 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x0100); 9299 bnx2x_cl45_write(bp, phy, 9300 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040); 9301 bnx2x_cl45_write(bp, phy, 9302 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 9303 0x0008); 9304 } 9305 } 9306 9307 static int bnx2x_8727_config_init(struct bnx2x_phy *phy, 9308 struct link_params *params, 9309 struct link_vars *vars) 9310 { 9311 u32 tx_en_mode; 9312 u16 tmp1, mod_abs, tmp2; 9313 struct bnx2x *bp = params->bp; 9314 /* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */ 9315 9316 bnx2x_wait_reset_complete(bp, phy, params); 9317 9318 DP(NETIF_MSG_LINK, "Initializing BCM8727\n"); 9319 9320 bnx2x_8727_specific_func(phy, params, PHY_INIT); 9321 /* Initially configure MOD_ABS to interrupt when module is 9322 * presence( bit 8) 9323 */ 9324 bnx2x_cl45_read(bp, phy, 9325 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs); 9326 /* Set EDC off by setting OPTXLOS signal input to low (bit 9). 9327 * When the EDC is off it locks onto a reference clock and avoids 9328 * becoming 'lost' 9329 */ 9330 mod_abs &= ~(1<<8); 9331 if (!(phy->flags & FLAGS_NOC)) 9332 mod_abs &= ~(1<<9); 9333 bnx2x_cl45_write(bp, phy, 9334 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs); 9335 9336 /* Enable/Disable PHY transmitter output */ 9337 bnx2x_set_disable_pmd_transmit(params, phy, 0); 9338 9339 bnx2x_8727_power_module(bp, phy, 1); 9340 9341 bnx2x_cl45_read(bp, phy, 9342 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1); 9343 9344 bnx2x_cl45_read(bp, phy, 9345 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1); 9346 9347 bnx2x_8727_config_speed(phy, params); 9348 9349 9350 /* Set TX PreEmphasis if needed */ 9351 if ((params->feature_config_flags & 9352 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) { 9353 DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n", 9354 phy->tx_preemphasis[0], 9355 phy->tx_preemphasis[1]); 9356 bnx2x_cl45_write(bp, phy, 9357 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL1, 9358 phy->tx_preemphasis[0]); 9359 9360 bnx2x_cl45_write(bp, phy, 9361 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL2, 9362 phy->tx_preemphasis[1]); 9363 } 9364 9365 /* If TX Laser is controlled by GPIO_0, do not let PHY go into low 9366 * power mode, if TX Laser is disabled 9367 */ 9368 tx_en_mode = REG_RD(bp, params->shmem_base + 9369 offsetof(struct shmem_region, 9370 dev_info.port_hw_config[params->port].sfp_ctrl)) 9371 & PORT_HW_CFG_TX_LASER_MASK; 9372 9373 if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) { 9374 9375 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n"); 9376 bnx2x_cl45_read(bp, phy, 9377 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, &tmp2); 9378 tmp2 |= 0x1000; 9379 tmp2 &= 0xFFEF; 9380 bnx2x_cl45_write(bp, phy, 9381 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, tmp2); 9382 bnx2x_cl45_read(bp, phy, 9383 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 9384 &tmp2); 9385 bnx2x_cl45_write(bp, phy, 9386 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 9387 (tmp2 & 0x7fff)); 9388 } 9389 9390 return 0; 9391 } 9392 9393 static void bnx2x_8727_handle_mod_abs(struct bnx2x_phy *phy, 9394 struct link_params *params) 9395 { 9396 struct bnx2x *bp = params->bp; 9397 u16 mod_abs, rx_alarm_status; 9398 u32 val = REG_RD(bp, params->shmem_base + 9399 offsetof(struct shmem_region, dev_info. 9400 port_feature_config[params->port]. 9401 config)); 9402 bnx2x_cl45_read(bp, phy, 9403 MDIO_PMA_DEVAD, 9404 MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs); 9405 if (mod_abs & (1<<8)) { 9406 9407 /* Module is absent */ 9408 DP(NETIF_MSG_LINK, 9409 "MOD_ABS indication show module is absent\n"); 9410 phy->media_type = ETH_PHY_NOT_PRESENT; 9411 /* 1. Set mod_abs to detect next module 9412 * presence event 9413 * 2. Set EDC off by setting OPTXLOS signal input to low 9414 * (bit 9). 9415 * When the EDC is off it locks onto a reference clock and 9416 * avoids becoming 'lost'. 9417 */ 9418 mod_abs &= ~(1<<8); 9419 if (!(phy->flags & FLAGS_NOC)) 9420 mod_abs &= ~(1<<9); 9421 bnx2x_cl45_write(bp, phy, 9422 MDIO_PMA_DEVAD, 9423 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs); 9424 9425 /* Clear RX alarm since it stays up as long as 9426 * the mod_abs wasn't changed 9427 */ 9428 bnx2x_cl45_read(bp, phy, 9429 MDIO_PMA_DEVAD, 9430 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status); 9431 9432 } else { 9433 /* Module is present */ 9434 DP(NETIF_MSG_LINK, 9435 "MOD_ABS indication show module is present\n"); 9436 /* First disable transmitter, and if the module is ok, the 9437 * module_detection will enable it 9438 * 1. Set mod_abs to detect next module absent event ( bit 8) 9439 * 2. Restore the default polarity of the OPRXLOS signal and 9440 * this signal will then correctly indicate the presence or 9441 * absence of the Rx signal. (bit 9) 9442 */ 9443 mod_abs |= (1<<8); 9444 if (!(phy->flags & FLAGS_NOC)) 9445 mod_abs |= (1<<9); 9446 bnx2x_cl45_write(bp, phy, 9447 MDIO_PMA_DEVAD, 9448 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs); 9449 9450 /* Clear RX alarm since it stays up as long as the mod_abs 9451 * wasn't changed. This is need to be done before calling the 9452 * module detection, otherwise it will clear* the link update 9453 * alarm 9454 */ 9455 bnx2x_cl45_read(bp, phy, 9456 MDIO_PMA_DEVAD, 9457 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status); 9458 9459 9460 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == 9461 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER) 9462 bnx2x_sfp_set_transmitter(params, phy, 0); 9463 9464 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0) 9465 bnx2x_sfp_module_detection(phy, params); 9466 else 9467 DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n"); 9468 9469 /* Reconfigure link speed based on module type limitations */ 9470 bnx2x_8727_config_speed(phy, params); 9471 } 9472 9473 DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n", 9474 rx_alarm_status); 9475 /* No need to check link status in case of module plugged in/out */ 9476 } 9477 9478 static u8 bnx2x_8727_read_status(struct bnx2x_phy *phy, 9479 struct link_params *params, 9480 struct link_vars *vars) 9481 9482 { 9483 struct bnx2x *bp = params->bp; 9484 u8 link_up = 0, oc_port = params->port; 9485 u16 link_status = 0; 9486 u16 rx_alarm_status, lasi_ctrl, val1; 9487 9488 /* If PHY is not initialized, do not check link status */ 9489 bnx2x_cl45_read(bp, phy, 9490 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 9491 &lasi_ctrl); 9492 if (!lasi_ctrl) 9493 return 0; 9494 9495 /* Check the LASI on Rx */ 9496 bnx2x_cl45_read(bp, phy, 9497 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, 9498 &rx_alarm_status); 9499 vars->line_speed = 0; 9500 DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n", rx_alarm_status); 9501 9502 bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT, 9503 MDIO_PMA_LASI_TXCTRL); 9504 9505 bnx2x_cl45_read(bp, phy, 9506 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1); 9507 9508 DP(NETIF_MSG_LINK, "8727 LASI status 0x%x\n", val1); 9509 9510 /* Clear MSG-OUT */ 9511 bnx2x_cl45_read(bp, phy, 9512 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1); 9513 9514 /* If a module is present and there is need to check 9515 * for over current 9516 */ 9517 if (!(phy->flags & FLAGS_NOC) && !(rx_alarm_status & (1<<5))) { 9518 /* Check over-current using 8727 GPIO0 input*/ 9519 bnx2x_cl45_read(bp, phy, 9520 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL, 9521 &val1); 9522 9523 if ((val1 & (1<<8)) == 0) { 9524 if (!CHIP_IS_E1x(bp)) 9525 oc_port = BP_PATH(bp) + (params->port << 1); 9526 DP(NETIF_MSG_LINK, 9527 "8727 Power fault has been detected on port %d\n", 9528 oc_port); 9529 netdev_err(bp->dev, "Error: Power fault on Port %d has " 9530 "been detected and the power to " 9531 "that SFP+ module has been removed " 9532 "to prevent failure of the card. " 9533 "Please remove the SFP+ module and " 9534 "restart the system to clear this " 9535 "error.\n", 9536 oc_port); 9537 /* Disable all RX_ALARMs except for mod_abs */ 9538 bnx2x_cl45_write(bp, phy, 9539 MDIO_PMA_DEVAD, 9540 MDIO_PMA_LASI_RXCTRL, (1<<5)); 9541 9542 bnx2x_cl45_read(bp, phy, 9543 MDIO_PMA_DEVAD, 9544 MDIO_PMA_REG_PHY_IDENTIFIER, &val1); 9545 /* Wait for module_absent_event */ 9546 val1 |= (1<<8); 9547 bnx2x_cl45_write(bp, phy, 9548 MDIO_PMA_DEVAD, 9549 MDIO_PMA_REG_PHY_IDENTIFIER, val1); 9550 /* Clear RX alarm */ 9551 bnx2x_cl45_read(bp, phy, 9552 MDIO_PMA_DEVAD, 9553 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status); 9554 bnx2x_8727_power_module(params->bp, phy, 0); 9555 return 0; 9556 } 9557 } /* Over current check */ 9558 9559 /* When module absent bit is set, check module */ 9560 if (rx_alarm_status & (1<<5)) { 9561 bnx2x_8727_handle_mod_abs(phy, params); 9562 /* Enable all mod_abs and link detection bits */ 9563 bnx2x_cl45_write(bp, phy, 9564 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, 9565 ((1<<5) | (1<<2))); 9566 } 9567 9568 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED)) { 9569 DP(NETIF_MSG_LINK, "Enabling 8727 TX laser\n"); 9570 bnx2x_sfp_set_transmitter(params, phy, 1); 9571 } else { 9572 DP(NETIF_MSG_LINK, "Tx is disabled\n"); 9573 return 0; 9574 } 9575 9576 bnx2x_cl45_read(bp, phy, 9577 MDIO_PMA_DEVAD, 9578 MDIO_PMA_REG_8073_SPEED_LINK_STATUS, &link_status); 9579 9580 /* Bits 0..2 --> speed detected, 9581 * Bits 13..15--> link is down 9582 */ 9583 if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) { 9584 link_up = 1; 9585 vars->line_speed = SPEED_10000; 9586 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n", 9587 params->port); 9588 } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) { 9589 link_up = 1; 9590 vars->line_speed = SPEED_1000; 9591 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n", 9592 params->port); 9593 } else { 9594 link_up = 0; 9595 DP(NETIF_MSG_LINK, "port %x: External link is down\n", 9596 params->port); 9597 } 9598 9599 /* Capture 10G link fault. */ 9600 if (vars->line_speed == SPEED_10000) { 9601 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 9602 MDIO_PMA_LASI_TXSTAT, &val1); 9603 9604 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 9605 MDIO_PMA_LASI_TXSTAT, &val1); 9606 9607 if (val1 & (1<<0)) { 9608 vars->fault_detected = 1; 9609 } 9610 } 9611 9612 if (link_up) { 9613 bnx2x_ext_phy_resolve_fc(phy, params, vars); 9614 vars->duplex = DUPLEX_FULL; 9615 DP(NETIF_MSG_LINK, "duplex = 0x%x\n", vars->duplex); 9616 } 9617 9618 if ((DUAL_MEDIA(params)) && 9619 (phy->req_line_speed == SPEED_1000)) { 9620 bnx2x_cl45_read(bp, phy, 9621 MDIO_PMA_DEVAD, 9622 MDIO_PMA_REG_8727_PCS_GP, &val1); 9623 /* In case of dual-media board and 1G, power up the XAUI side, 9624 * otherwise power it down. For 10G it is done automatically 9625 */ 9626 if (link_up) 9627 val1 &= ~(3<<10); 9628 else 9629 val1 |= (3<<10); 9630 bnx2x_cl45_write(bp, phy, 9631 MDIO_PMA_DEVAD, 9632 MDIO_PMA_REG_8727_PCS_GP, val1); 9633 } 9634 return link_up; 9635 } 9636 9637 static void bnx2x_8727_link_reset(struct bnx2x_phy *phy, 9638 struct link_params *params) 9639 { 9640 struct bnx2x *bp = params->bp; 9641 9642 /* Enable/Disable PHY transmitter output */ 9643 bnx2x_set_disable_pmd_transmit(params, phy, 1); 9644 9645 /* Disable Transmitter */ 9646 bnx2x_sfp_set_transmitter(params, phy, 0); 9647 /* Clear LASI */ 9648 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0); 9649 9650 } 9651 9652 /******************************************************************/ 9653 /* BCM8481/BCM84823/BCM84833 PHY SECTION */ 9654 /******************************************************************/ 9655 static void bnx2x_save_848xx_spirom_version(struct bnx2x_phy *phy, 9656 struct bnx2x *bp, 9657 u8 port) 9658 { 9659 u16 val, fw_ver2, cnt, i; 9660 static struct bnx2x_reg_set reg_set[] = { 9661 {MDIO_PMA_DEVAD, 0xA819, 0x0014}, 9662 {MDIO_PMA_DEVAD, 0xA81A, 0xc200}, 9663 {MDIO_PMA_DEVAD, 0xA81B, 0x0000}, 9664 {MDIO_PMA_DEVAD, 0xA81C, 0x0300}, 9665 {MDIO_PMA_DEVAD, 0xA817, 0x0009} 9666 }; 9667 u16 fw_ver1; 9668 9669 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) || 9670 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) { 9671 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 0x400f, &fw_ver1); 9672 bnx2x_save_spirom_version(bp, port, fw_ver1 & 0xfff, 9673 phy->ver_addr); 9674 } else { 9675 /* For 32-bit registers in 848xx, access via MDIO2ARM i/f. */ 9676 /* (1) set reg 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */ 9677 for (i = 0; i < ARRAY_SIZE(reg_set); i++) 9678 bnx2x_cl45_write(bp, phy, reg_set[i].devad, 9679 reg_set[i].reg, reg_set[i].val); 9680 9681 for (cnt = 0; cnt < 100; cnt++) { 9682 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val); 9683 if (val & 1) 9684 break; 9685 udelay(5); 9686 } 9687 if (cnt == 100) { 9688 DP(NETIF_MSG_LINK, "Unable to read 848xx " 9689 "phy fw version(1)\n"); 9690 bnx2x_save_spirom_version(bp, port, 0, 9691 phy->ver_addr); 9692 return; 9693 } 9694 9695 9696 /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */ 9697 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0000); 9698 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200); 9699 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x000A); 9700 for (cnt = 0; cnt < 100; cnt++) { 9701 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val); 9702 if (val & 1) 9703 break; 9704 udelay(5); 9705 } 9706 if (cnt == 100) { 9707 DP(NETIF_MSG_LINK, "Unable to read 848xx phy fw " 9708 "version(2)\n"); 9709 bnx2x_save_spirom_version(bp, port, 0, 9710 phy->ver_addr); 9711 return; 9712 } 9713 9714 /* lower 16 bits of the register SPI_FW_STATUS */ 9715 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81B, &fw_ver1); 9716 /* upper 16 bits of register SPI_FW_STATUS */ 9717 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81C, &fw_ver2); 9718 9719 bnx2x_save_spirom_version(bp, port, (fw_ver2<<16) | fw_ver1, 9720 phy->ver_addr); 9721 } 9722 9723 } 9724 static void bnx2x_848xx_set_led(struct bnx2x *bp, 9725 struct bnx2x_phy *phy) 9726 { 9727 u16 val, offset, i; 9728 static struct bnx2x_reg_set reg_set[] = { 9729 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED1_MASK, 0x0080}, 9730 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED2_MASK, 0x0018}, 9731 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED3_MASK, 0x0006}, 9732 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED3_BLINK, 0x0000}, 9733 {MDIO_PMA_DEVAD, MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH, 9734 MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ}, 9735 {MDIO_AN_DEVAD, 0xFFFB, 0xFFFD} 9736 }; 9737 /* PHYC_CTL_LED_CTL */ 9738 bnx2x_cl45_read(bp, phy, 9739 MDIO_PMA_DEVAD, 9740 MDIO_PMA_REG_8481_LINK_SIGNAL, &val); 9741 val &= 0xFE00; 9742 val |= 0x0092; 9743 9744 bnx2x_cl45_write(bp, phy, 9745 MDIO_PMA_DEVAD, 9746 MDIO_PMA_REG_8481_LINK_SIGNAL, val); 9747 9748 for (i = 0; i < ARRAY_SIZE(reg_set); i++) 9749 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg, 9750 reg_set[i].val); 9751 9752 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) || 9753 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) 9754 offset = MDIO_PMA_REG_84833_CTL_LED_CTL_1; 9755 else 9756 offset = MDIO_PMA_REG_84823_CTL_LED_CTL_1; 9757 9758 /* stretch_en for LED3*/ 9759 bnx2x_cl45_read_or_write(bp, phy, 9760 MDIO_PMA_DEVAD, offset, 9761 MDIO_PMA_REG_84823_LED3_STRETCH_EN); 9762 } 9763 9764 static void bnx2x_848xx_specific_func(struct bnx2x_phy *phy, 9765 struct link_params *params, 9766 u32 action) 9767 { 9768 struct bnx2x *bp = params->bp; 9769 switch (action) { 9770 case PHY_INIT: 9771 if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) && 9772 (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) { 9773 /* Save spirom version */ 9774 bnx2x_save_848xx_spirom_version(phy, bp, params->port); 9775 } 9776 /* This phy uses the NIG latch mechanism since link indication 9777 * arrives through its LED4 and not via its LASI signal, so we 9778 * get steady signal instead of clear on read 9779 */ 9780 bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4, 9781 1 << NIG_LATCH_BC_ENABLE_MI_INT); 9782 9783 bnx2x_848xx_set_led(bp, phy); 9784 break; 9785 } 9786 } 9787 9788 static int bnx2x_848xx_cmn_config_init(struct bnx2x_phy *phy, 9789 struct link_params *params, 9790 struct link_vars *vars) 9791 { 9792 struct bnx2x *bp = params->bp; 9793 u16 autoneg_val, an_1000_val, an_10_100_val; 9794 9795 bnx2x_848xx_specific_func(phy, params, PHY_INIT); 9796 bnx2x_cl45_write(bp, phy, 9797 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0000); 9798 9799 /* set 1000 speed advertisement */ 9800 bnx2x_cl45_read(bp, phy, 9801 MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL, 9802 &an_1000_val); 9803 9804 bnx2x_ext_phy_set_pause(params, phy, vars); 9805 bnx2x_cl45_read(bp, phy, 9806 MDIO_AN_DEVAD, 9807 MDIO_AN_REG_8481_LEGACY_AN_ADV, 9808 &an_10_100_val); 9809 bnx2x_cl45_read(bp, phy, 9810 MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_MII_CTRL, 9811 &autoneg_val); 9812 /* Disable forced speed */ 9813 autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13)); 9814 an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8)); 9815 9816 if (((phy->req_line_speed == SPEED_AUTO_NEG) && 9817 (phy->speed_cap_mask & 9818 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) || 9819 (phy->req_line_speed == SPEED_1000)) { 9820 an_1000_val |= (1<<8); 9821 autoneg_val |= (1<<9 | 1<<12); 9822 if (phy->req_duplex == DUPLEX_FULL) 9823 an_1000_val |= (1<<9); 9824 DP(NETIF_MSG_LINK, "Advertising 1G\n"); 9825 } else 9826 an_1000_val &= ~((1<<8) | (1<<9)); 9827 9828 bnx2x_cl45_write(bp, phy, 9829 MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL, 9830 an_1000_val); 9831 9832 /* Set 10/100 speed advertisement */ 9833 if (phy->req_line_speed == SPEED_AUTO_NEG) { 9834 if (phy->speed_cap_mask & 9835 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL) { 9836 /* Enable autoneg and restart autoneg for legacy speeds 9837 */ 9838 autoneg_val |= (1<<9 | 1<<12); 9839 an_10_100_val |= (1<<8); 9840 DP(NETIF_MSG_LINK, "Advertising 100M-FD\n"); 9841 } 9842 9843 if (phy->speed_cap_mask & 9844 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF) { 9845 /* Enable autoneg and restart autoneg for legacy speeds 9846 */ 9847 autoneg_val |= (1<<9 | 1<<12); 9848 an_10_100_val |= (1<<7); 9849 DP(NETIF_MSG_LINK, "Advertising 100M-HD\n"); 9850 } 9851 9852 if ((phy->speed_cap_mask & 9853 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) && 9854 (phy->supported & SUPPORTED_10baseT_Full)) { 9855 an_10_100_val |= (1<<6); 9856 autoneg_val |= (1<<9 | 1<<12); 9857 DP(NETIF_MSG_LINK, "Advertising 10M-FD\n"); 9858 } 9859 9860 if ((phy->speed_cap_mask & 9861 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF) && 9862 (phy->supported & SUPPORTED_10baseT_Half)) { 9863 an_10_100_val |= (1<<5); 9864 autoneg_val |= (1<<9 | 1<<12); 9865 DP(NETIF_MSG_LINK, "Advertising 10M-HD\n"); 9866 } 9867 } 9868 9869 /* Only 10/100 are allowed to work in FORCE mode */ 9870 if ((phy->req_line_speed == SPEED_100) && 9871 (phy->supported & 9872 (SUPPORTED_100baseT_Half | 9873 SUPPORTED_100baseT_Full))) { 9874 autoneg_val |= (1<<13); 9875 /* Enabled AUTO-MDIX when autoneg is disabled */ 9876 bnx2x_cl45_write(bp, phy, 9877 MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL, 9878 (1<<15 | 1<<9 | 7<<0)); 9879 /* The PHY needs this set even for forced link. */ 9880 an_10_100_val |= (1<<8) | (1<<7); 9881 DP(NETIF_MSG_LINK, "Setting 100M force\n"); 9882 } 9883 if ((phy->req_line_speed == SPEED_10) && 9884 (phy->supported & 9885 (SUPPORTED_10baseT_Half | 9886 SUPPORTED_10baseT_Full))) { 9887 /* Enabled AUTO-MDIX when autoneg is disabled */ 9888 bnx2x_cl45_write(bp, phy, 9889 MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL, 9890 (1<<15 | 1<<9 | 7<<0)); 9891 DP(NETIF_MSG_LINK, "Setting 10M force\n"); 9892 } 9893 9894 bnx2x_cl45_write(bp, phy, 9895 MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_AN_ADV, 9896 an_10_100_val); 9897 9898 if (phy->req_duplex == DUPLEX_FULL) 9899 autoneg_val |= (1<<8); 9900 9901 /* Always write this if this is not 84833/4. 9902 * For 84833/4, write it only when it's a forced speed. 9903 */ 9904 if (((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) && 9905 (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) || 9906 ((autoneg_val & (1<<12)) == 0)) 9907 bnx2x_cl45_write(bp, phy, 9908 MDIO_AN_DEVAD, 9909 MDIO_AN_REG_8481_LEGACY_MII_CTRL, autoneg_val); 9910 9911 if (((phy->req_line_speed == SPEED_AUTO_NEG) && 9912 (phy->speed_cap_mask & 9913 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) || 9914 (phy->req_line_speed == SPEED_10000)) { 9915 DP(NETIF_MSG_LINK, "Advertising 10G\n"); 9916 /* Restart autoneg for 10G*/ 9917 9918 bnx2x_cl45_read_or_write( 9919 bp, phy, 9920 MDIO_AN_DEVAD, 9921 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL, 9922 0x1000); 9923 bnx2x_cl45_write(bp, phy, 9924 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 9925 0x3200); 9926 } else 9927 bnx2x_cl45_write(bp, phy, 9928 MDIO_AN_DEVAD, 9929 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL, 9930 1); 9931 9932 return 0; 9933 } 9934 9935 static int bnx2x_8481_config_init(struct bnx2x_phy *phy, 9936 struct link_params *params, 9937 struct link_vars *vars) 9938 { 9939 struct bnx2x *bp = params->bp; 9940 /* Restore normal power mode*/ 9941 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 9942 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); 9943 9944 /* HW reset */ 9945 bnx2x_ext_phy_hw_reset(bp, params->port); 9946 bnx2x_wait_reset_complete(bp, phy, params); 9947 9948 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15); 9949 return bnx2x_848xx_cmn_config_init(phy, params, vars); 9950 } 9951 9952 #define PHY84833_CMDHDLR_WAIT 300 9953 #define PHY84833_CMDHDLR_MAX_ARGS 5 9954 static int bnx2x_84833_cmd_hdlr(struct bnx2x_phy *phy, 9955 struct link_params *params, u16 fw_cmd, 9956 u16 cmd_args[], int argc) 9957 { 9958 int idx; 9959 u16 val; 9960 struct bnx2x *bp = params->bp; 9961 /* Write CMD_OPEN_OVERRIDE to STATUS reg */ 9962 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, 9963 MDIO_84833_CMD_HDLR_STATUS, 9964 PHY84833_STATUS_CMD_OPEN_OVERRIDE); 9965 for (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) { 9966 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 9967 MDIO_84833_CMD_HDLR_STATUS, &val); 9968 if (val == PHY84833_STATUS_CMD_OPEN_FOR_CMDS) 9969 break; 9970 usleep_range(1000, 2000); 9971 } 9972 if (idx >= PHY84833_CMDHDLR_WAIT) { 9973 DP(NETIF_MSG_LINK, "FW cmd: FW not ready.\n"); 9974 return -EINVAL; 9975 } 9976 9977 /* Prepare argument(s) and issue command */ 9978 for (idx = 0; idx < argc; idx++) { 9979 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, 9980 MDIO_84833_CMD_HDLR_DATA1 + idx, 9981 cmd_args[idx]); 9982 } 9983 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, 9984 MDIO_84833_CMD_HDLR_COMMAND, fw_cmd); 9985 for (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) { 9986 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 9987 MDIO_84833_CMD_HDLR_STATUS, &val); 9988 if ((val == PHY84833_STATUS_CMD_COMPLETE_PASS) || 9989 (val == PHY84833_STATUS_CMD_COMPLETE_ERROR)) 9990 break; 9991 usleep_range(1000, 2000); 9992 } 9993 if ((idx >= PHY84833_CMDHDLR_WAIT) || 9994 (val == PHY84833_STATUS_CMD_COMPLETE_ERROR)) { 9995 DP(NETIF_MSG_LINK, "FW cmd failed.\n"); 9996 return -EINVAL; 9997 } 9998 /* Gather returning data */ 9999 for (idx = 0; idx < argc; idx++) { 10000 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 10001 MDIO_84833_CMD_HDLR_DATA1 + idx, 10002 &cmd_args[idx]); 10003 } 10004 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, 10005 MDIO_84833_CMD_HDLR_STATUS, 10006 PHY84833_STATUS_CMD_CLEAR_COMPLETE); 10007 return 0; 10008 } 10009 10010 static int bnx2x_84833_pair_swap_cfg(struct bnx2x_phy *phy, 10011 struct link_params *params, 10012 struct link_vars *vars) 10013 { 10014 u32 pair_swap; 10015 u16 data[PHY84833_CMDHDLR_MAX_ARGS]; 10016 int status; 10017 struct bnx2x *bp = params->bp; 10018 10019 /* Check for configuration. */ 10020 pair_swap = REG_RD(bp, params->shmem_base + 10021 offsetof(struct shmem_region, 10022 dev_info.port_hw_config[params->port].xgbt_phy_cfg)) & 10023 PORT_HW_CFG_RJ45_PAIR_SWAP_MASK; 10024 10025 if (pair_swap == 0) 10026 return 0; 10027 10028 /* Only the second argument is used for this command */ 10029 data[1] = (u16)pair_swap; 10030 10031 status = bnx2x_84833_cmd_hdlr(phy, params, 10032 PHY84833_CMD_SET_PAIR_SWAP, data, PHY84833_CMDHDLR_MAX_ARGS); 10033 if (status == 0) 10034 DP(NETIF_MSG_LINK, "Pairswap OK, val=0x%x\n", data[1]); 10035 10036 return status; 10037 } 10038 10039 static u8 bnx2x_84833_get_reset_gpios(struct bnx2x *bp, 10040 u32 shmem_base_path[], 10041 u32 chip_id) 10042 { 10043 u32 reset_pin[2]; 10044 u32 idx; 10045 u8 reset_gpios; 10046 if (CHIP_IS_E3(bp)) { 10047 /* Assume that these will be GPIOs, not EPIOs. */ 10048 for (idx = 0; idx < 2; idx++) { 10049 /* Map config param to register bit. */ 10050 reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] + 10051 offsetof(struct shmem_region, 10052 dev_info.port_hw_config[0].e3_cmn_pin_cfg)); 10053 reset_pin[idx] = (reset_pin[idx] & 10054 PORT_HW_CFG_E3_PHY_RESET_MASK) >> 10055 PORT_HW_CFG_E3_PHY_RESET_SHIFT; 10056 reset_pin[idx] -= PIN_CFG_GPIO0_P0; 10057 reset_pin[idx] = (1 << reset_pin[idx]); 10058 } 10059 reset_gpios = (u8)(reset_pin[0] | reset_pin[1]); 10060 } else { 10061 /* E2, look from diff place of shmem. */ 10062 for (idx = 0; idx < 2; idx++) { 10063 reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] + 10064 offsetof(struct shmem_region, 10065 dev_info.port_hw_config[0].default_cfg)); 10066 reset_pin[idx] &= PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK; 10067 reset_pin[idx] -= PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0; 10068 reset_pin[idx] >>= PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT; 10069 reset_pin[idx] = (1 << reset_pin[idx]); 10070 } 10071 reset_gpios = (u8)(reset_pin[0] | reset_pin[1]); 10072 } 10073 10074 return reset_gpios; 10075 } 10076 10077 static int bnx2x_84833_hw_reset_phy(struct bnx2x_phy *phy, 10078 struct link_params *params) 10079 { 10080 struct bnx2x *bp = params->bp; 10081 u8 reset_gpios; 10082 u32 other_shmem_base_addr = REG_RD(bp, params->shmem2_base + 10083 offsetof(struct shmem2_region, 10084 other_shmem_base_addr)); 10085 10086 u32 shmem_base_path[2]; 10087 10088 /* Work around for 84833 LED failure inside RESET status */ 10089 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, 10090 MDIO_AN_REG_8481_LEGACY_MII_CTRL, 10091 MDIO_AN_REG_8481_MII_CTRL_FORCE_1G); 10092 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, 10093 MDIO_AN_REG_8481_1G_100T_EXT_CTRL, 10094 MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF); 10095 10096 shmem_base_path[0] = params->shmem_base; 10097 shmem_base_path[1] = other_shmem_base_addr; 10098 10099 reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path, 10100 params->chip_id); 10101 10102 bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW); 10103 udelay(10); 10104 DP(NETIF_MSG_LINK, "84833 hw reset on pin values 0x%x\n", 10105 reset_gpios); 10106 10107 return 0; 10108 } 10109 10110 static int bnx2x_8483x_disable_eee(struct bnx2x_phy *phy, 10111 struct link_params *params, 10112 struct link_vars *vars) 10113 { 10114 int rc; 10115 struct bnx2x *bp = params->bp; 10116 u16 cmd_args = 0; 10117 10118 DP(NETIF_MSG_LINK, "Don't Advertise 10GBase-T EEE\n"); 10119 10120 /* Prevent Phy from working in EEE and advertising it */ 10121 rc = bnx2x_84833_cmd_hdlr(phy, params, 10122 PHY84833_CMD_SET_EEE_MODE, &cmd_args, 1); 10123 if (rc) { 10124 DP(NETIF_MSG_LINK, "EEE disable failed.\n"); 10125 return rc; 10126 } 10127 10128 return bnx2x_eee_disable(phy, params, vars); 10129 } 10130 10131 static int bnx2x_8483x_enable_eee(struct bnx2x_phy *phy, 10132 struct link_params *params, 10133 struct link_vars *vars) 10134 { 10135 int rc; 10136 struct bnx2x *bp = params->bp; 10137 u16 cmd_args = 1; 10138 10139 rc = bnx2x_84833_cmd_hdlr(phy, params, 10140 PHY84833_CMD_SET_EEE_MODE, &cmd_args, 1); 10141 if (rc) { 10142 DP(NETIF_MSG_LINK, "EEE enable failed.\n"); 10143 return rc; 10144 } 10145 10146 return bnx2x_eee_advertise(phy, params, vars, SHMEM_EEE_10G_ADV); 10147 } 10148 10149 #define PHY84833_CONSTANT_LATENCY 1193 10150 static int bnx2x_848x3_config_init(struct bnx2x_phy *phy, 10151 struct link_params *params, 10152 struct link_vars *vars) 10153 { 10154 struct bnx2x *bp = params->bp; 10155 u8 port, initialize = 1; 10156 u16 val; 10157 u32 actual_phy_selection; 10158 u16 cmd_args[PHY84833_CMDHDLR_MAX_ARGS]; 10159 int rc = 0; 10160 10161 usleep_range(1000, 2000); 10162 10163 if (!(CHIP_IS_E1x(bp))) 10164 port = BP_PATH(bp); 10165 else 10166 port = params->port; 10167 10168 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) { 10169 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3, 10170 MISC_REGISTERS_GPIO_OUTPUT_HIGH, 10171 port); 10172 } else { 10173 /* MDIO reset */ 10174 bnx2x_cl45_write(bp, phy, 10175 MDIO_PMA_DEVAD, 10176 MDIO_PMA_REG_CTRL, 0x8000); 10177 } 10178 10179 bnx2x_wait_reset_complete(bp, phy, params); 10180 10181 /* Wait for GPHY to come out of reset */ 10182 msleep(50); 10183 if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) && 10184 (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) { 10185 /* BCM84823 requires that XGXS links up first @ 10G for normal 10186 * behavior. 10187 */ 10188 u16 temp; 10189 temp = vars->line_speed; 10190 vars->line_speed = SPEED_10000; 10191 bnx2x_set_autoneg(¶ms->phy[INT_PHY], params, vars, 0); 10192 bnx2x_program_serdes(¶ms->phy[INT_PHY], params, vars); 10193 vars->line_speed = temp; 10194 } 10195 10196 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 10197 MDIO_CTL_REG_84823_MEDIA, &val); 10198 val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK | 10199 MDIO_CTL_REG_84823_MEDIA_LINE_MASK | 10200 MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN | 10201 MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK | 10202 MDIO_CTL_REG_84823_MEDIA_FIBER_1G); 10203 10204 if (CHIP_IS_E3(bp)) { 10205 val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK | 10206 MDIO_CTL_REG_84823_MEDIA_LINE_MASK); 10207 } else { 10208 val |= (MDIO_CTL_REG_84823_CTRL_MAC_XFI | 10209 MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L); 10210 } 10211 10212 actual_phy_selection = bnx2x_phy_selection(params); 10213 10214 switch (actual_phy_selection) { 10215 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT: 10216 /* Do nothing. Essentially this is like the priority copper */ 10217 break; 10218 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY: 10219 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER; 10220 break; 10221 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY: 10222 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER; 10223 break; 10224 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY: 10225 /* Do nothing here. The first PHY won't be initialized at all */ 10226 break; 10227 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY: 10228 val |= MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN; 10229 initialize = 0; 10230 break; 10231 } 10232 if (params->phy[EXT_PHY2].req_line_speed == SPEED_1000) 10233 val |= MDIO_CTL_REG_84823_MEDIA_FIBER_1G; 10234 10235 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, 10236 MDIO_CTL_REG_84823_MEDIA, val); 10237 DP(NETIF_MSG_LINK, "Multi_phy config = 0x%x, Media control = 0x%x\n", 10238 params->multi_phy_config, val); 10239 10240 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) || 10241 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) { 10242 bnx2x_84833_pair_swap_cfg(phy, params, vars); 10243 10244 /* Keep AutogrEEEn disabled. */ 10245 cmd_args[0] = 0x0; 10246 cmd_args[1] = 0x0; 10247 cmd_args[2] = PHY84833_CONSTANT_LATENCY + 1; 10248 cmd_args[3] = PHY84833_CONSTANT_LATENCY; 10249 rc = bnx2x_84833_cmd_hdlr(phy, params, 10250 PHY84833_CMD_SET_EEE_MODE, cmd_args, 10251 PHY84833_CMDHDLR_MAX_ARGS); 10252 if (rc) 10253 DP(NETIF_MSG_LINK, "Cfg AutogrEEEn failed.\n"); 10254 } 10255 if (initialize) 10256 rc = bnx2x_848xx_cmn_config_init(phy, params, vars); 10257 else 10258 bnx2x_save_848xx_spirom_version(phy, bp, params->port); 10259 /* 84833 PHY has a better feature and doesn't need to support this. */ 10260 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) { 10261 u32 cms_enable = REG_RD(bp, params->shmem_base + 10262 offsetof(struct shmem_region, 10263 dev_info.port_hw_config[params->port].default_cfg)) & 10264 PORT_HW_CFG_ENABLE_CMS_MASK; 10265 10266 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 10267 MDIO_CTL_REG_84823_USER_CTRL_REG, &val); 10268 if (cms_enable) 10269 val |= MDIO_CTL_REG_84823_USER_CTRL_CMS; 10270 else 10271 val &= ~MDIO_CTL_REG_84823_USER_CTRL_CMS; 10272 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, 10273 MDIO_CTL_REG_84823_USER_CTRL_REG, val); 10274 } 10275 10276 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 10277 MDIO_84833_TOP_CFG_FW_REV, &val); 10278 10279 /* Configure EEE support */ 10280 if ((val >= MDIO_84833_TOP_CFG_FW_EEE) && 10281 (val != MDIO_84833_TOP_CFG_FW_NO_EEE) && 10282 bnx2x_eee_has_cap(params)) { 10283 rc = bnx2x_eee_initial_config(params, vars, SHMEM_EEE_10G_ADV); 10284 if (rc) { 10285 DP(NETIF_MSG_LINK, "Failed to configure EEE timers\n"); 10286 bnx2x_8483x_disable_eee(phy, params, vars); 10287 return rc; 10288 } 10289 10290 if ((phy->req_duplex == DUPLEX_FULL) && 10291 (params->eee_mode & EEE_MODE_ADV_LPI) && 10292 (bnx2x_eee_calc_timer(params) || 10293 !(params->eee_mode & EEE_MODE_ENABLE_LPI))) 10294 rc = bnx2x_8483x_enable_eee(phy, params, vars); 10295 else 10296 rc = bnx2x_8483x_disable_eee(phy, params, vars); 10297 if (rc) { 10298 DP(NETIF_MSG_LINK, "Failed to set EEE advertisement\n"); 10299 return rc; 10300 } 10301 } else { 10302 vars->eee_status &= ~SHMEM_EEE_SUPPORTED_MASK; 10303 } 10304 10305 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) || 10306 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) { 10307 /* Bring PHY out of super isolate mode as the final step. */ 10308 bnx2x_cl45_read_and_write(bp, phy, 10309 MDIO_CTL_DEVAD, 10310 MDIO_84833_TOP_CFG_XGPHY_STRAP1, 10311 (u16)~MDIO_84833_SUPER_ISOLATE); 10312 } 10313 return rc; 10314 } 10315 10316 static u8 bnx2x_848xx_read_status(struct bnx2x_phy *phy, 10317 struct link_params *params, 10318 struct link_vars *vars) 10319 { 10320 struct bnx2x *bp = params->bp; 10321 u16 val, val1, val2; 10322 u8 link_up = 0; 10323 10324 10325 /* Check 10G-BaseT link status */ 10326 /* Check PMD signal ok */ 10327 bnx2x_cl45_read(bp, phy, 10328 MDIO_AN_DEVAD, 0xFFFA, &val1); 10329 bnx2x_cl45_read(bp, phy, 10330 MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_PMD_SIGNAL, 10331 &val2); 10332 DP(NETIF_MSG_LINK, "BCM848xx: PMD_SIGNAL 1.a811 = 0x%x\n", val2); 10333 10334 /* Check link 10G */ 10335 if (val2 & (1<<11)) { 10336 vars->line_speed = SPEED_10000; 10337 vars->duplex = DUPLEX_FULL; 10338 link_up = 1; 10339 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars); 10340 } else { /* Check Legacy speed link */ 10341 u16 legacy_status, legacy_speed; 10342 10343 /* Enable expansion register 0x42 (Operation mode status) */ 10344 bnx2x_cl45_write(bp, phy, 10345 MDIO_AN_DEVAD, 10346 MDIO_AN_REG_8481_EXPANSION_REG_ACCESS, 0xf42); 10347 10348 /* Get legacy speed operation status */ 10349 bnx2x_cl45_read(bp, phy, 10350 MDIO_AN_DEVAD, 10351 MDIO_AN_REG_8481_EXPANSION_REG_RD_RW, 10352 &legacy_status); 10353 10354 DP(NETIF_MSG_LINK, "Legacy speed status = 0x%x\n", 10355 legacy_status); 10356 link_up = ((legacy_status & (1<<11)) == (1<<11)); 10357 legacy_speed = (legacy_status & (3<<9)); 10358 if (legacy_speed == (0<<9)) 10359 vars->line_speed = SPEED_10; 10360 else if (legacy_speed == (1<<9)) 10361 vars->line_speed = SPEED_100; 10362 else if (legacy_speed == (2<<9)) 10363 vars->line_speed = SPEED_1000; 10364 else { /* Should not happen: Treat as link down */ 10365 vars->line_speed = 0; 10366 link_up = 0; 10367 } 10368 10369 if (link_up) { 10370 if (legacy_status & (1<<8)) 10371 vars->duplex = DUPLEX_FULL; 10372 else 10373 vars->duplex = DUPLEX_HALF; 10374 10375 DP(NETIF_MSG_LINK, 10376 "Link is up in %dMbps, is_duplex_full= %d\n", 10377 vars->line_speed, 10378 (vars->duplex == DUPLEX_FULL)); 10379 /* Check legacy speed AN resolution */ 10380 bnx2x_cl45_read(bp, phy, 10381 MDIO_AN_DEVAD, 10382 MDIO_AN_REG_8481_LEGACY_MII_STATUS, 10383 &val); 10384 if (val & (1<<5)) 10385 vars->link_status |= 10386 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; 10387 bnx2x_cl45_read(bp, phy, 10388 MDIO_AN_DEVAD, 10389 MDIO_AN_REG_8481_LEGACY_AN_EXPANSION, 10390 &val); 10391 if ((val & (1<<0)) == 0) 10392 vars->link_status |= 10393 LINK_STATUS_PARALLEL_DETECTION_USED; 10394 } 10395 } 10396 if (link_up) { 10397 DP(NETIF_MSG_LINK, "BCM848x3: link speed is %d\n", 10398 vars->line_speed); 10399 bnx2x_ext_phy_resolve_fc(phy, params, vars); 10400 10401 /* Read LP advertised speeds */ 10402 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, 10403 MDIO_AN_REG_CL37_FC_LP, &val); 10404 if (val & (1<<5)) 10405 vars->link_status |= 10406 LINK_STATUS_LINK_PARTNER_10THD_CAPABLE; 10407 if (val & (1<<6)) 10408 vars->link_status |= 10409 LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE; 10410 if (val & (1<<7)) 10411 vars->link_status |= 10412 LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE; 10413 if (val & (1<<8)) 10414 vars->link_status |= 10415 LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE; 10416 if (val & (1<<9)) 10417 vars->link_status |= 10418 LINK_STATUS_LINK_PARTNER_100T4_CAPABLE; 10419 10420 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, 10421 MDIO_AN_REG_1000T_STATUS, &val); 10422 10423 if (val & (1<<10)) 10424 vars->link_status |= 10425 LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE; 10426 if (val & (1<<11)) 10427 vars->link_status |= 10428 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; 10429 10430 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, 10431 MDIO_AN_REG_MASTER_STATUS, &val); 10432 10433 if (val & (1<<11)) 10434 vars->link_status |= 10435 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; 10436 10437 /* Determine if EEE was negotiated */ 10438 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) || 10439 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) 10440 bnx2x_eee_an_resolve(phy, params, vars); 10441 } 10442 10443 return link_up; 10444 } 10445 10446 static int bnx2x_848xx_format_ver(u32 raw_ver, u8 *str, u16 *len) 10447 { 10448 int status = 0; 10449 u32 spirom_ver; 10450 spirom_ver = ((raw_ver & 0xF80) >> 7) << 16 | (raw_ver & 0x7F); 10451 status = bnx2x_format_ver(spirom_ver, str, len); 10452 return status; 10453 } 10454 10455 static void bnx2x_8481_hw_reset(struct bnx2x_phy *phy, 10456 struct link_params *params) 10457 { 10458 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1, 10459 MISC_REGISTERS_GPIO_OUTPUT_LOW, 0); 10460 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1, 10461 MISC_REGISTERS_GPIO_OUTPUT_LOW, 1); 10462 } 10463 10464 static void bnx2x_8481_link_reset(struct bnx2x_phy *phy, 10465 struct link_params *params) 10466 { 10467 bnx2x_cl45_write(params->bp, phy, 10468 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000); 10469 bnx2x_cl45_write(params->bp, phy, 10470 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1); 10471 } 10472 10473 static void bnx2x_848x3_link_reset(struct bnx2x_phy *phy, 10474 struct link_params *params) 10475 { 10476 struct bnx2x *bp = params->bp; 10477 u8 port; 10478 u16 val16; 10479 10480 if (!(CHIP_IS_E1x(bp))) 10481 port = BP_PATH(bp); 10482 else 10483 port = params->port; 10484 10485 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) { 10486 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3, 10487 MISC_REGISTERS_GPIO_OUTPUT_LOW, 10488 port); 10489 } else { 10490 bnx2x_cl45_read(bp, phy, 10491 MDIO_CTL_DEVAD, 10492 MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val16); 10493 val16 |= MDIO_84833_SUPER_ISOLATE; 10494 bnx2x_cl45_write(bp, phy, 10495 MDIO_CTL_DEVAD, 10496 MDIO_84833_TOP_CFG_XGPHY_STRAP1, val16); 10497 } 10498 } 10499 10500 static void bnx2x_848xx_set_link_led(struct bnx2x_phy *phy, 10501 struct link_params *params, u8 mode) 10502 { 10503 struct bnx2x *bp = params->bp; 10504 u16 val; 10505 u8 port; 10506 10507 if (!(CHIP_IS_E1x(bp))) 10508 port = BP_PATH(bp); 10509 else 10510 port = params->port; 10511 10512 switch (mode) { 10513 case LED_MODE_OFF: 10514 10515 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OFF\n", port); 10516 10517 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) == 10518 SHARED_HW_CFG_LED_EXTPHY1) { 10519 10520 /* Set LED masks */ 10521 bnx2x_cl45_write(bp, phy, 10522 MDIO_PMA_DEVAD, 10523 MDIO_PMA_REG_8481_LED1_MASK, 10524 0x0); 10525 10526 bnx2x_cl45_write(bp, phy, 10527 MDIO_PMA_DEVAD, 10528 MDIO_PMA_REG_8481_LED2_MASK, 10529 0x0); 10530 10531 bnx2x_cl45_write(bp, phy, 10532 MDIO_PMA_DEVAD, 10533 MDIO_PMA_REG_8481_LED3_MASK, 10534 0x0); 10535 10536 bnx2x_cl45_write(bp, phy, 10537 MDIO_PMA_DEVAD, 10538 MDIO_PMA_REG_8481_LED5_MASK, 10539 0x0); 10540 10541 } else { 10542 bnx2x_cl45_write(bp, phy, 10543 MDIO_PMA_DEVAD, 10544 MDIO_PMA_REG_8481_LED1_MASK, 10545 0x0); 10546 } 10547 break; 10548 case LED_MODE_FRONT_PANEL_OFF: 10549 10550 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE FRONT PANEL OFF\n", 10551 port); 10552 10553 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) == 10554 SHARED_HW_CFG_LED_EXTPHY1) { 10555 10556 /* Set LED masks */ 10557 bnx2x_cl45_write(bp, phy, 10558 MDIO_PMA_DEVAD, 10559 MDIO_PMA_REG_8481_LED1_MASK, 10560 0x0); 10561 10562 bnx2x_cl45_write(bp, phy, 10563 MDIO_PMA_DEVAD, 10564 MDIO_PMA_REG_8481_LED2_MASK, 10565 0x0); 10566 10567 bnx2x_cl45_write(bp, phy, 10568 MDIO_PMA_DEVAD, 10569 MDIO_PMA_REG_8481_LED3_MASK, 10570 0x0); 10571 10572 bnx2x_cl45_write(bp, phy, 10573 MDIO_PMA_DEVAD, 10574 MDIO_PMA_REG_8481_LED5_MASK, 10575 0x20); 10576 10577 } else { 10578 bnx2x_cl45_write(bp, phy, 10579 MDIO_PMA_DEVAD, 10580 MDIO_PMA_REG_8481_LED1_MASK, 10581 0x0); 10582 if (phy->type == 10583 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) { 10584 /* Disable MI_INT interrupt before setting LED4 10585 * source to constant off. 10586 */ 10587 if (REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + 10588 params->port*4) & 10589 NIG_MASK_MI_INT) { 10590 params->link_flags |= 10591 LINK_FLAGS_INT_DISABLED; 10592 10593 bnx2x_bits_dis( 10594 bp, 10595 NIG_REG_MASK_INTERRUPT_PORT0 + 10596 params->port*4, 10597 NIG_MASK_MI_INT); 10598 } 10599 bnx2x_cl45_write(bp, phy, 10600 MDIO_PMA_DEVAD, 10601 MDIO_PMA_REG_8481_SIGNAL_MASK, 10602 0x0); 10603 } 10604 } 10605 break; 10606 case LED_MODE_ON: 10607 10608 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE ON\n", port); 10609 10610 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) == 10611 SHARED_HW_CFG_LED_EXTPHY1) { 10612 /* Set control reg */ 10613 bnx2x_cl45_read(bp, phy, 10614 MDIO_PMA_DEVAD, 10615 MDIO_PMA_REG_8481_LINK_SIGNAL, 10616 &val); 10617 val &= 0x8000; 10618 val |= 0x2492; 10619 10620 bnx2x_cl45_write(bp, phy, 10621 MDIO_PMA_DEVAD, 10622 MDIO_PMA_REG_8481_LINK_SIGNAL, 10623 val); 10624 10625 /* Set LED masks */ 10626 bnx2x_cl45_write(bp, phy, 10627 MDIO_PMA_DEVAD, 10628 MDIO_PMA_REG_8481_LED1_MASK, 10629 0x0); 10630 10631 bnx2x_cl45_write(bp, phy, 10632 MDIO_PMA_DEVAD, 10633 MDIO_PMA_REG_8481_LED2_MASK, 10634 0x20); 10635 10636 bnx2x_cl45_write(bp, phy, 10637 MDIO_PMA_DEVAD, 10638 MDIO_PMA_REG_8481_LED3_MASK, 10639 0x20); 10640 10641 bnx2x_cl45_write(bp, phy, 10642 MDIO_PMA_DEVAD, 10643 MDIO_PMA_REG_8481_LED5_MASK, 10644 0x0); 10645 } else { 10646 bnx2x_cl45_write(bp, phy, 10647 MDIO_PMA_DEVAD, 10648 MDIO_PMA_REG_8481_LED1_MASK, 10649 0x20); 10650 if (phy->type == 10651 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) { 10652 /* Disable MI_INT interrupt before setting LED4 10653 * source to constant on. 10654 */ 10655 if (REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + 10656 params->port*4) & 10657 NIG_MASK_MI_INT) { 10658 params->link_flags |= 10659 LINK_FLAGS_INT_DISABLED; 10660 10661 bnx2x_bits_dis( 10662 bp, 10663 NIG_REG_MASK_INTERRUPT_PORT0 + 10664 params->port*4, 10665 NIG_MASK_MI_INT); 10666 } 10667 bnx2x_cl45_write(bp, phy, 10668 MDIO_PMA_DEVAD, 10669 MDIO_PMA_REG_8481_SIGNAL_MASK, 10670 0x20); 10671 } 10672 } 10673 break; 10674 10675 case LED_MODE_OPER: 10676 10677 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OPER\n", port); 10678 10679 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) == 10680 SHARED_HW_CFG_LED_EXTPHY1) { 10681 10682 /* Set control reg */ 10683 bnx2x_cl45_read(bp, phy, 10684 MDIO_PMA_DEVAD, 10685 MDIO_PMA_REG_8481_LINK_SIGNAL, 10686 &val); 10687 10688 if (!((val & 10689 MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK) 10690 >> MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT)) { 10691 DP(NETIF_MSG_LINK, "Setting LINK_SIGNAL\n"); 10692 bnx2x_cl45_write(bp, phy, 10693 MDIO_PMA_DEVAD, 10694 MDIO_PMA_REG_8481_LINK_SIGNAL, 10695 0xa492); 10696 } 10697 10698 /* Set LED masks */ 10699 bnx2x_cl45_write(bp, phy, 10700 MDIO_PMA_DEVAD, 10701 MDIO_PMA_REG_8481_LED1_MASK, 10702 0x10); 10703 10704 bnx2x_cl45_write(bp, phy, 10705 MDIO_PMA_DEVAD, 10706 MDIO_PMA_REG_8481_LED2_MASK, 10707 0x80); 10708 10709 bnx2x_cl45_write(bp, phy, 10710 MDIO_PMA_DEVAD, 10711 MDIO_PMA_REG_8481_LED3_MASK, 10712 0x98); 10713 10714 bnx2x_cl45_write(bp, phy, 10715 MDIO_PMA_DEVAD, 10716 MDIO_PMA_REG_8481_LED5_MASK, 10717 0x40); 10718 10719 } else { 10720 /* EXTPHY2 LED mode indicate that the 100M/1G/10G LED 10721 * sources are all wired through LED1, rather than only 10722 * 10G in other modes. 10723 */ 10724 val = ((params->hw_led_mode << 10725 SHARED_HW_CFG_LED_MODE_SHIFT) == 10726 SHARED_HW_CFG_LED_EXTPHY2) ? 0x98 : 0x80; 10727 10728 bnx2x_cl45_write(bp, phy, 10729 MDIO_PMA_DEVAD, 10730 MDIO_PMA_REG_8481_LED1_MASK, 10731 val); 10732 10733 /* Tell LED3 to blink on source */ 10734 bnx2x_cl45_read(bp, phy, 10735 MDIO_PMA_DEVAD, 10736 MDIO_PMA_REG_8481_LINK_SIGNAL, 10737 &val); 10738 val &= ~(7<<6); 10739 val |= (1<<6); /* A83B[8:6]= 1 */ 10740 bnx2x_cl45_write(bp, phy, 10741 MDIO_PMA_DEVAD, 10742 MDIO_PMA_REG_8481_LINK_SIGNAL, 10743 val); 10744 if (phy->type == 10745 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) { 10746 /* Restore LED4 source to external link, 10747 * and re-enable interrupts. 10748 */ 10749 bnx2x_cl45_write(bp, phy, 10750 MDIO_PMA_DEVAD, 10751 MDIO_PMA_REG_8481_SIGNAL_MASK, 10752 0x40); 10753 if (params->link_flags & 10754 LINK_FLAGS_INT_DISABLED) { 10755 bnx2x_link_int_enable(params); 10756 params->link_flags &= 10757 ~LINK_FLAGS_INT_DISABLED; 10758 } 10759 } 10760 } 10761 break; 10762 } 10763 10764 /* This is a workaround for E3+84833 until autoneg 10765 * restart is fixed in f/w 10766 */ 10767 if (CHIP_IS_E3(bp)) { 10768 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 10769 MDIO_WC_REG_GP2_STATUS_GP_2_1, &val); 10770 } 10771 } 10772 10773 /******************************************************************/ 10774 /* 54618SE PHY SECTION */ 10775 /******************************************************************/ 10776 static void bnx2x_54618se_specific_func(struct bnx2x_phy *phy, 10777 struct link_params *params, 10778 u32 action) 10779 { 10780 struct bnx2x *bp = params->bp; 10781 u16 temp; 10782 switch (action) { 10783 case PHY_INIT: 10784 /* Configure LED4: set to INTR (0x6). */ 10785 /* Accessing shadow register 0xe. */ 10786 bnx2x_cl22_write(bp, phy, 10787 MDIO_REG_GPHY_SHADOW, 10788 MDIO_REG_GPHY_SHADOW_LED_SEL2); 10789 bnx2x_cl22_read(bp, phy, 10790 MDIO_REG_GPHY_SHADOW, 10791 &temp); 10792 temp &= ~(0xf << 4); 10793 temp |= (0x6 << 4); 10794 bnx2x_cl22_write(bp, phy, 10795 MDIO_REG_GPHY_SHADOW, 10796 MDIO_REG_GPHY_SHADOW_WR_ENA | temp); 10797 /* Configure INTR based on link status change. */ 10798 bnx2x_cl22_write(bp, phy, 10799 MDIO_REG_INTR_MASK, 10800 ~MDIO_REG_INTR_MASK_LINK_STATUS); 10801 break; 10802 } 10803 } 10804 10805 static int bnx2x_54618se_config_init(struct bnx2x_phy *phy, 10806 struct link_params *params, 10807 struct link_vars *vars) 10808 { 10809 struct bnx2x *bp = params->bp; 10810 u8 port; 10811 u16 autoneg_val, an_1000_val, an_10_100_val, fc_val, temp; 10812 u32 cfg_pin; 10813 10814 DP(NETIF_MSG_LINK, "54618SE cfg init\n"); 10815 usleep_range(1000, 2000); 10816 10817 /* This works with E3 only, no need to check the chip 10818 * before determining the port. 10819 */ 10820 port = params->port; 10821 10822 cfg_pin = (REG_RD(bp, params->shmem_base + 10823 offsetof(struct shmem_region, 10824 dev_info.port_hw_config[port].e3_cmn_pin_cfg)) & 10825 PORT_HW_CFG_E3_PHY_RESET_MASK) >> 10826 PORT_HW_CFG_E3_PHY_RESET_SHIFT; 10827 10828 /* Drive pin high to bring the GPHY out of reset. */ 10829 bnx2x_set_cfg_pin(bp, cfg_pin, 1); 10830 10831 /* wait for GPHY to reset */ 10832 msleep(50); 10833 10834 /* reset phy */ 10835 bnx2x_cl22_write(bp, phy, 10836 MDIO_PMA_REG_CTRL, 0x8000); 10837 bnx2x_wait_reset_complete(bp, phy, params); 10838 10839 /* Wait for GPHY to reset */ 10840 msleep(50); 10841 10842 10843 bnx2x_54618se_specific_func(phy, params, PHY_INIT); 10844 /* Flip the signal detect polarity (set 0x1c.0x1e[8]). */ 10845 bnx2x_cl22_write(bp, phy, 10846 MDIO_REG_GPHY_SHADOW, 10847 MDIO_REG_GPHY_SHADOW_AUTO_DET_MED); 10848 bnx2x_cl22_read(bp, phy, 10849 MDIO_REG_GPHY_SHADOW, 10850 &temp); 10851 temp |= MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD; 10852 bnx2x_cl22_write(bp, phy, 10853 MDIO_REG_GPHY_SHADOW, 10854 MDIO_REG_GPHY_SHADOW_WR_ENA | temp); 10855 10856 /* Set up fc */ 10857 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */ 10858 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); 10859 fc_val = 0; 10860 if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) == 10861 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) 10862 fc_val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC; 10863 10864 if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) == 10865 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) 10866 fc_val |= MDIO_AN_REG_ADV_PAUSE_PAUSE; 10867 10868 /* Read all advertisement */ 10869 bnx2x_cl22_read(bp, phy, 10870 0x09, 10871 &an_1000_val); 10872 10873 bnx2x_cl22_read(bp, phy, 10874 0x04, 10875 &an_10_100_val); 10876 10877 bnx2x_cl22_read(bp, phy, 10878 MDIO_PMA_REG_CTRL, 10879 &autoneg_val); 10880 10881 /* Disable forced speed */ 10882 autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13)); 10883 an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8) | (1<<10) | 10884 (1<<11)); 10885 10886 if (((phy->req_line_speed == SPEED_AUTO_NEG) && 10887 (phy->speed_cap_mask & 10888 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) || 10889 (phy->req_line_speed == SPEED_1000)) { 10890 an_1000_val |= (1<<8); 10891 autoneg_val |= (1<<9 | 1<<12); 10892 if (phy->req_duplex == DUPLEX_FULL) 10893 an_1000_val |= (1<<9); 10894 DP(NETIF_MSG_LINK, "Advertising 1G\n"); 10895 } else 10896 an_1000_val &= ~((1<<8) | (1<<9)); 10897 10898 bnx2x_cl22_write(bp, phy, 10899 0x09, 10900 an_1000_val); 10901 bnx2x_cl22_read(bp, phy, 10902 0x09, 10903 &an_1000_val); 10904 10905 /* Advertise 10/100 link speed */ 10906 if (phy->req_line_speed == SPEED_AUTO_NEG) { 10907 if (phy->speed_cap_mask & 10908 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF) { 10909 an_10_100_val |= (1<<5); 10910 autoneg_val |= (1<<9 | 1<<12); 10911 DP(NETIF_MSG_LINK, "Advertising 10M-HD\n"); 10912 } 10913 if (phy->speed_cap_mask & 10914 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) { 10915 an_10_100_val |= (1<<6); 10916 autoneg_val |= (1<<9 | 1<<12); 10917 DP(NETIF_MSG_LINK, "Advertising 10M-FD\n"); 10918 } 10919 if (phy->speed_cap_mask & 10920 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF) { 10921 an_10_100_val |= (1<<7); 10922 autoneg_val |= (1<<9 | 1<<12); 10923 DP(NETIF_MSG_LINK, "Advertising 100M-HD\n"); 10924 } 10925 if (phy->speed_cap_mask & 10926 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL) { 10927 an_10_100_val |= (1<<8); 10928 autoneg_val |= (1<<9 | 1<<12); 10929 DP(NETIF_MSG_LINK, "Advertising 100M-FD\n"); 10930 } 10931 } 10932 10933 /* Only 10/100 are allowed to work in FORCE mode */ 10934 if (phy->req_line_speed == SPEED_100) { 10935 autoneg_val |= (1<<13); 10936 /* Enabled AUTO-MDIX when autoneg is disabled */ 10937 bnx2x_cl22_write(bp, phy, 10938 0x18, 10939 (1<<15 | 1<<9 | 7<<0)); 10940 DP(NETIF_MSG_LINK, "Setting 100M force\n"); 10941 } 10942 if (phy->req_line_speed == SPEED_10) { 10943 /* Enabled AUTO-MDIX when autoneg is disabled */ 10944 bnx2x_cl22_write(bp, phy, 10945 0x18, 10946 (1<<15 | 1<<9 | 7<<0)); 10947 DP(NETIF_MSG_LINK, "Setting 10M force\n"); 10948 } 10949 10950 if ((phy->flags & FLAGS_EEE) && bnx2x_eee_has_cap(params)) { 10951 int rc; 10952 10953 bnx2x_cl22_write(bp, phy, MDIO_REG_GPHY_EXP_ACCESS, 10954 MDIO_REG_GPHY_EXP_ACCESS_TOP | 10955 MDIO_REG_GPHY_EXP_TOP_2K_BUF); 10956 bnx2x_cl22_read(bp, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, &temp); 10957 temp &= 0xfffe; 10958 bnx2x_cl22_write(bp, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, temp); 10959 10960 rc = bnx2x_eee_initial_config(params, vars, SHMEM_EEE_1G_ADV); 10961 if (rc) { 10962 DP(NETIF_MSG_LINK, "Failed to configure EEE timers\n"); 10963 bnx2x_eee_disable(phy, params, vars); 10964 } else if ((params->eee_mode & EEE_MODE_ADV_LPI) && 10965 (phy->req_duplex == DUPLEX_FULL) && 10966 (bnx2x_eee_calc_timer(params) || 10967 !(params->eee_mode & EEE_MODE_ENABLE_LPI))) { 10968 /* Need to advertise EEE only when requested, 10969 * and either no LPI assertion was requested, 10970 * or it was requested and a valid timer was set. 10971 * Also notice full duplex is required for EEE. 10972 */ 10973 bnx2x_eee_advertise(phy, params, vars, 10974 SHMEM_EEE_1G_ADV); 10975 } else { 10976 DP(NETIF_MSG_LINK, "Don't Advertise 1GBase-T EEE\n"); 10977 bnx2x_eee_disable(phy, params, vars); 10978 } 10979 } else { 10980 vars->eee_status &= ~SHMEM_EEE_1G_ADV << 10981 SHMEM_EEE_SUPPORTED_SHIFT; 10982 10983 if (phy->flags & FLAGS_EEE) { 10984 /* Handle legacy auto-grEEEn */ 10985 if (params->feature_config_flags & 10986 FEATURE_CONFIG_AUTOGREEEN_ENABLED) { 10987 temp = 6; 10988 DP(NETIF_MSG_LINK, "Enabling Auto-GrEEEn\n"); 10989 } else { 10990 temp = 0; 10991 DP(NETIF_MSG_LINK, "Don't Adv. EEE\n"); 10992 } 10993 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, 10994 MDIO_AN_REG_EEE_ADV, temp); 10995 } 10996 } 10997 10998 bnx2x_cl22_write(bp, phy, 10999 0x04, 11000 an_10_100_val | fc_val); 11001 11002 if (phy->req_duplex == DUPLEX_FULL) 11003 autoneg_val |= (1<<8); 11004 11005 bnx2x_cl22_write(bp, phy, 11006 MDIO_PMA_REG_CTRL, autoneg_val); 11007 11008 return 0; 11009 } 11010 11011 11012 static void bnx2x_5461x_set_link_led(struct bnx2x_phy *phy, 11013 struct link_params *params, u8 mode) 11014 { 11015 struct bnx2x *bp = params->bp; 11016 u16 temp; 11017 11018 bnx2x_cl22_write(bp, phy, 11019 MDIO_REG_GPHY_SHADOW, 11020 MDIO_REG_GPHY_SHADOW_LED_SEL1); 11021 bnx2x_cl22_read(bp, phy, 11022 MDIO_REG_GPHY_SHADOW, 11023 &temp); 11024 temp &= 0xff00; 11025 11026 DP(NETIF_MSG_LINK, "54618x set link led (mode=%x)\n", mode); 11027 switch (mode) { 11028 case LED_MODE_FRONT_PANEL_OFF: 11029 case LED_MODE_OFF: 11030 temp |= 0x00ee; 11031 break; 11032 case LED_MODE_OPER: 11033 temp |= 0x0001; 11034 break; 11035 case LED_MODE_ON: 11036 temp |= 0x00ff; 11037 break; 11038 default: 11039 break; 11040 } 11041 bnx2x_cl22_write(bp, phy, 11042 MDIO_REG_GPHY_SHADOW, 11043 MDIO_REG_GPHY_SHADOW_WR_ENA | temp); 11044 return; 11045 } 11046 11047 11048 static void bnx2x_54618se_link_reset(struct bnx2x_phy *phy, 11049 struct link_params *params) 11050 { 11051 struct bnx2x *bp = params->bp; 11052 u32 cfg_pin; 11053 u8 port; 11054 11055 /* In case of no EPIO routed to reset the GPHY, put it 11056 * in low power mode. 11057 */ 11058 bnx2x_cl22_write(bp, phy, MDIO_PMA_REG_CTRL, 0x800); 11059 /* This works with E3 only, no need to check the chip 11060 * before determining the port. 11061 */ 11062 port = params->port; 11063 cfg_pin = (REG_RD(bp, params->shmem_base + 11064 offsetof(struct shmem_region, 11065 dev_info.port_hw_config[port].e3_cmn_pin_cfg)) & 11066 PORT_HW_CFG_E3_PHY_RESET_MASK) >> 11067 PORT_HW_CFG_E3_PHY_RESET_SHIFT; 11068 11069 /* Drive pin low to put GPHY in reset. */ 11070 bnx2x_set_cfg_pin(bp, cfg_pin, 0); 11071 } 11072 11073 static u8 bnx2x_54618se_read_status(struct bnx2x_phy *phy, 11074 struct link_params *params, 11075 struct link_vars *vars) 11076 { 11077 struct bnx2x *bp = params->bp; 11078 u16 val; 11079 u8 link_up = 0; 11080 u16 legacy_status, legacy_speed; 11081 11082 /* Get speed operation status */ 11083 bnx2x_cl22_read(bp, phy, 11084 MDIO_REG_GPHY_AUX_STATUS, 11085 &legacy_status); 11086 DP(NETIF_MSG_LINK, "54618SE read_status: 0x%x\n", legacy_status); 11087 11088 /* Read status to clear the PHY interrupt. */ 11089 bnx2x_cl22_read(bp, phy, 11090 MDIO_REG_INTR_STATUS, 11091 &val); 11092 11093 link_up = ((legacy_status & (1<<2)) == (1<<2)); 11094 11095 if (link_up) { 11096 legacy_speed = (legacy_status & (7<<8)); 11097 if (legacy_speed == (7<<8)) { 11098 vars->line_speed = SPEED_1000; 11099 vars->duplex = DUPLEX_FULL; 11100 } else if (legacy_speed == (6<<8)) { 11101 vars->line_speed = SPEED_1000; 11102 vars->duplex = DUPLEX_HALF; 11103 } else if (legacy_speed == (5<<8)) { 11104 vars->line_speed = SPEED_100; 11105 vars->duplex = DUPLEX_FULL; 11106 } 11107 /* Omitting 100Base-T4 for now */ 11108 else if (legacy_speed == (3<<8)) { 11109 vars->line_speed = SPEED_100; 11110 vars->duplex = DUPLEX_HALF; 11111 } else if (legacy_speed == (2<<8)) { 11112 vars->line_speed = SPEED_10; 11113 vars->duplex = DUPLEX_FULL; 11114 } else if (legacy_speed == (1<<8)) { 11115 vars->line_speed = SPEED_10; 11116 vars->duplex = DUPLEX_HALF; 11117 } else /* Should not happen */ 11118 vars->line_speed = 0; 11119 11120 DP(NETIF_MSG_LINK, 11121 "Link is up in %dMbps, is_duplex_full= %d\n", 11122 vars->line_speed, 11123 (vars->duplex == DUPLEX_FULL)); 11124 11125 /* Check legacy speed AN resolution */ 11126 bnx2x_cl22_read(bp, phy, 11127 0x01, 11128 &val); 11129 if (val & (1<<5)) 11130 vars->link_status |= 11131 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; 11132 bnx2x_cl22_read(bp, phy, 11133 0x06, 11134 &val); 11135 if ((val & (1<<0)) == 0) 11136 vars->link_status |= 11137 LINK_STATUS_PARALLEL_DETECTION_USED; 11138 11139 DP(NETIF_MSG_LINK, "BCM54618SE: link speed is %d\n", 11140 vars->line_speed); 11141 11142 bnx2x_ext_phy_resolve_fc(phy, params, vars); 11143 11144 if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) { 11145 /* Report LP advertised speeds */ 11146 bnx2x_cl22_read(bp, phy, 0x5, &val); 11147 11148 if (val & (1<<5)) 11149 vars->link_status |= 11150 LINK_STATUS_LINK_PARTNER_10THD_CAPABLE; 11151 if (val & (1<<6)) 11152 vars->link_status |= 11153 LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE; 11154 if (val & (1<<7)) 11155 vars->link_status |= 11156 LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE; 11157 if (val & (1<<8)) 11158 vars->link_status |= 11159 LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE; 11160 if (val & (1<<9)) 11161 vars->link_status |= 11162 LINK_STATUS_LINK_PARTNER_100T4_CAPABLE; 11163 11164 bnx2x_cl22_read(bp, phy, 0xa, &val); 11165 if (val & (1<<10)) 11166 vars->link_status |= 11167 LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE; 11168 if (val & (1<<11)) 11169 vars->link_status |= 11170 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; 11171 11172 if ((phy->flags & FLAGS_EEE) && 11173 bnx2x_eee_has_cap(params)) 11174 bnx2x_eee_an_resolve(phy, params, vars); 11175 } 11176 } 11177 return link_up; 11178 } 11179 11180 static void bnx2x_54618se_config_loopback(struct bnx2x_phy *phy, 11181 struct link_params *params) 11182 { 11183 struct bnx2x *bp = params->bp; 11184 u16 val; 11185 u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0; 11186 11187 DP(NETIF_MSG_LINK, "2PMA/PMD ext_phy_loopback: 54618se\n"); 11188 11189 /* Enable master/slave manual mmode and set to master */ 11190 /* mii write 9 [bits set 11 12] */ 11191 bnx2x_cl22_write(bp, phy, 0x09, 3<<11); 11192 11193 /* forced 1G and disable autoneg */ 11194 /* set val [mii read 0] */ 11195 /* set val [expr $val & [bits clear 6 12 13]] */ 11196 /* set val [expr $val | [bits set 6 8]] */ 11197 /* mii write 0 $val */ 11198 bnx2x_cl22_read(bp, phy, 0x00, &val); 11199 val &= ~((1<<6) | (1<<12) | (1<<13)); 11200 val |= (1<<6) | (1<<8); 11201 bnx2x_cl22_write(bp, phy, 0x00, val); 11202 11203 /* Set external loopback and Tx using 6dB coding */ 11204 /* mii write 0x18 7 */ 11205 /* set val [mii read 0x18] */ 11206 /* mii write 0x18 [expr $val | [bits set 10 15]] */ 11207 bnx2x_cl22_write(bp, phy, 0x18, 7); 11208 bnx2x_cl22_read(bp, phy, 0x18, &val); 11209 bnx2x_cl22_write(bp, phy, 0x18, val | (1<<10) | (1<<15)); 11210 11211 /* This register opens the gate for the UMAC despite its name */ 11212 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1); 11213 11214 /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame 11215 * length used by the MAC receive logic to check frames. 11216 */ 11217 REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710); 11218 } 11219 11220 /******************************************************************/ 11221 /* SFX7101 PHY SECTION */ 11222 /******************************************************************/ 11223 static void bnx2x_7101_config_loopback(struct bnx2x_phy *phy, 11224 struct link_params *params) 11225 { 11226 struct bnx2x *bp = params->bp; 11227 /* SFX7101_XGXS_TEST1 */ 11228 bnx2x_cl45_write(bp, phy, 11229 MDIO_XS_DEVAD, MDIO_XS_SFX7101_XGXS_TEST1, 0x100); 11230 } 11231 11232 static int bnx2x_7101_config_init(struct bnx2x_phy *phy, 11233 struct link_params *params, 11234 struct link_vars *vars) 11235 { 11236 u16 fw_ver1, fw_ver2, val; 11237 struct bnx2x *bp = params->bp; 11238 DP(NETIF_MSG_LINK, "Setting the SFX7101 LASI indication\n"); 11239 11240 /* Restore normal power mode*/ 11241 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 11242 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); 11243 /* HW reset */ 11244 bnx2x_ext_phy_hw_reset(bp, params->port); 11245 bnx2x_wait_reset_complete(bp, phy, params); 11246 11247 bnx2x_cl45_write(bp, phy, 11248 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x1); 11249 DP(NETIF_MSG_LINK, "Setting the SFX7101 LED to blink on traffic\n"); 11250 bnx2x_cl45_write(bp, phy, 11251 MDIO_PMA_DEVAD, MDIO_PMA_REG_7107_LED_CNTL, (1<<3)); 11252 11253 bnx2x_ext_phy_set_pause(params, phy, vars); 11254 /* Restart autoneg */ 11255 bnx2x_cl45_read(bp, phy, 11256 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, &val); 11257 val |= 0x200; 11258 bnx2x_cl45_write(bp, phy, 11259 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, val); 11260 11261 /* Save spirom version */ 11262 bnx2x_cl45_read(bp, phy, 11263 MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER1, &fw_ver1); 11264 11265 bnx2x_cl45_read(bp, phy, 11266 MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER2, &fw_ver2); 11267 bnx2x_save_spirom_version(bp, params->port, 11268 (u32)(fw_ver1<<16 | fw_ver2), phy->ver_addr); 11269 return 0; 11270 } 11271 11272 static u8 bnx2x_7101_read_status(struct bnx2x_phy *phy, 11273 struct link_params *params, 11274 struct link_vars *vars) 11275 { 11276 struct bnx2x *bp = params->bp; 11277 u8 link_up; 11278 u16 val1, val2; 11279 bnx2x_cl45_read(bp, phy, 11280 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2); 11281 bnx2x_cl45_read(bp, phy, 11282 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1); 11283 DP(NETIF_MSG_LINK, "10G-base-T LASI status 0x%x->0x%x\n", 11284 val2, val1); 11285 bnx2x_cl45_read(bp, phy, 11286 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2); 11287 bnx2x_cl45_read(bp, phy, 11288 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1); 11289 DP(NETIF_MSG_LINK, "10G-base-T PMA status 0x%x->0x%x\n", 11290 val2, val1); 11291 link_up = ((val1 & 4) == 4); 11292 /* If link is up print the AN outcome of the SFX7101 PHY */ 11293 if (link_up) { 11294 bnx2x_cl45_read(bp, phy, 11295 MDIO_AN_DEVAD, MDIO_AN_REG_MASTER_STATUS, 11296 &val2); 11297 vars->line_speed = SPEED_10000; 11298 vars->duplex = DUPLEX_FULL; 11299 DP(NETIF_MSG_LINK, "SFX7101 AN status 0x%x->Master=%x\n", 11300 val2, (val2 & (1<<14))); 11301 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars); 11302 bnx2x_ext_phy_resolve_fc(phy, params, vars); 11303 11304 /* Read LP advertised speeds */ 11305 if (val2 & (1<<11)) 11306 vars->link_status |= 11307 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; 11308 } 11309 return link_up; 11310 } 11311 11312 static int bnx2x_7101_format_ver(u32 spirom_ver, u8 *str, u16 *len) 11313 { 11314 if (*len < 5) 11315 return -EINVAL; 11316 str[0] = (spirom_ver & 0xFF); 11317 str[1] = (spirom_ver & 0xFF00) >> 8; 11318 str[2] = (spirom_ver & 0xFF0000) >> 16; 11319 str[3] = (spirom_ver & 0xFF000000) >> 24; 11320 str[4] = '\0'; 11321 *len -= 5; 11322 return 0; 11323 } 11324 11325 void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, struct bnx2x_phy *phy) 11326 { 11327 u16 val, cnt; 11328 11329 bnx2x_cl45_read(bp, phy, 11330 MDIO_PMA_DEVAD, 11331 MDIO_PMA_REG_7101_RESET, &val); 11332 11333 for (cnt = 0; cnt < 10; cnt++) { 11334 msleep(50); 11335 /* Writes a self-clearing reset */ 11336 bnx2x_cl45_write(bp, phy, 11337 MDIO_PMA_DEVAD, 11338 MDIO_PMA_REG_7101_RESET, 11339 (val | (1<<15))); 11340 /* Wait for clear */ 11341 bnx2x_cl45_read(bp, phy, 11342 MDIO_PMA_DEVAD, 11343 MDIO_PMA_REG_7101_RESET, &val); 11344 11345 if ((val & (1<<15)) == 0) 11346 break; 11347 } 11348 } 11349 11350 static void bnx2x_7101_hw_reset(struct bnx2x_phy *phy, 11351 struct link_params *params) { 11352 /* Low power mode is controlled by GPIO 2 */ 11353 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_2, 11354 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port); 11355 /* The PHY reset is controlled by GPIO 1 */ 11356 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1, 11357 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port); 11358 } 11359 11360 static void bnx2x_7101_set_link_led(struct bnx2x_phy *phy, 11361 struct link_params *params, u8 mode) 11362 { 11363 u16 val = 0; 11364 struct bnx2x *bp = params->bp; 11365 switch (mode) { 11366 case LED_MODE_FRONT_PANEL_OFF: 11367 case LED_MODE_OFF: 11368 val = 2; 11369 break; 11370 case LED_MODE_ON: 11371 val = 1; 11372 break; 11373 case LED_MODE_OPER: 11374 val = 0; 11375 break; 11376 } 11377 bnx2x_cl45_write(bp, phy, 11378 MDIO_PMA_DEVAD, 11379 MDIO_PMA_REG_7107_LINK_LED_CNTL, 11380 val); 11381 } 11382 11383 /******************************************************************/ 11384 /* STATIC PHY DECLARATION */ 11385 /******************************************************************/ 11386 11387 static const struct bnx2x_phy phy_null = { 11388 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN, 11389 .addr = 0, 11390 .def_md_devad = 0, 11391 .flags = FLAGS_INIT_XGXS_FIRST, 11392 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11393 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11394 .mdio_ctrl = 0, 11395 .supported = 0, 11396 .media_type = ETH_PHY_NOT_PRESENT, 11397 .ver_addr = 0, 11398 .req_flow_ctrl = 0, 11399 .req_line_speed = 0, 11400 .speed_cap_mask = 0, 11401 .req_duplex = 0, 11402 .rsrv = 0, 11403 .config_init = (config_init_t)NULL, 11404 .read_status = (read_status_t)NULL, 11405 .link_reset = (link_reset_t)NULL, 11406 .config_loopback = (config_loopback_t)NULL, 11407 .format_fw_ver = (format_fw_ver_t)NULL, 11408 .hw_reset = (hw_reset_t)NULL, 11409 .set_link_led = (set_link_led_t)NULL, 11410 .phy_specific_func = (phy_specific_func_t)NULL 11411 }; 11412 11413 static const struct bnx2x_phy phy_serdes = { 11414 .type = PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT, 11415 .addr = 0xff, 11416 .def_md_devad = 0, 11417 .flags = 0, 11418 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11419 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11420 .mdio_ctrl = 0, 11421 .supported = (SUPPORTED_10baseT_Half | 11422 SUPPORTED_10baseT_Full | 11423 SUPPORTED_100baseT_Half | 11424 SUPPORTED_100baseT_Full | 11425 SUPPORTED_1000baseT_Full | 11426 SUPPORTED_2500baseX_Full | 11427 SUPPORTED_TP | 11428 SUPPORTED_Autoneg | 11429 SUPPORTED_Pause | 11430 SUPPORTED_Asym_Pause), 11431 .media_type = ETH_PHY_BASE_T, 11432 .ver_addr = 0, 11433 .req_flow_ctrl = 0, 11434 .req_line_speed = 0, 11435 .speed_cap_mask = 0, 11436 .req_duplex = 0, 11437 .rsrv = 0, 11438 .config_init = (config_init_t)bnx2x_xgxs_config_init, 11439 .read_status = (read_status_t)bnx2x_link_settings_status, 11440 .link_reset = (link_reset_t)bnx2x_int_link_reset, 11441 .config_loopback = (config_loopback_t)NULL, 11442 .format_fw_ver = (format_fw_ver_t)NULL, 11443 .hw_reset = (hw_reset_t)NULL, 11444 .set_link_led = (set_link_led_t)NULL, 11445 .phy_specific_func = (phy_specific_func_t)NULL 11446 }; 11447 11448 static const struct bnx2x_phy phy_xgxs = { 11449 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT, 11450 .addr = 0xff, 11451 .def_md_devad = 0, 11452 .flags = 0, 11453 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11454 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11455 .mdio_ctrl = 0, 11456 .supported = (SUPPORTED_10baseT_Half | 11457 SUPPORTED_10baseT_Full | 11458 SUPPORTED_100baseT_Half | 11459 SUPPORTED_100baseT_Full | 11460 SUPPORTED_1000baseT_Full | 11461 SUPPORTED_2500baseX_Full | 11462 SUPPORTED_10000baseT_Full | 11463 SUPPORTED_FIBRE | 11464 SUPPORTED_Autoneg | 11465 SUPPORTED_Pause | 11466 SUPPORTED_Asym_Pause), 11467 .media_type = ETH_PHY_CX4, 11468 .ver_addr = 0, 11469 .req_flow_ctrl = 0, 11470 .req_line_speed = 0, 11471 .speed_cap_mask = 0, 11472 .req_duplex = 0, 11473 .rsrv = 0, 11474 .config_init = (config_init_t)bnx2x_xgxs_config_init, 11475 .read_status = (read_status_t)bnx2x_link_settings_status, 11476 .link_reset = (link_reset_t)bnx2x_int_link_reset, 11477 .config_loopback = (config_loopback_t)bnx2x_set_xgxs_loopback, 11478 .format_fw_ver = (format_fw_ver_t)NULL, 11479 .hw_reset = (hw_reset_t)NULL, 11480 .set_link_led = (set_link_led_t)NULL, 11481 .phy_specific_func = (phy_specific_func_t)bnx2x_xgxs_specific_func 11482 }; 11483 static const struct bnx2x_phy phy_warpcore = { 11484 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT, 11485 .addr = 0xff, 11486 .def_md_devad = 0, 11487 .flags = FLAGS_TX_ERROR_CHECK, 11488 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11489 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11490 .mdio_ctrl = 0, 11491 .supported = (SUPPORTED_10baseT_Half | 11492 SUPPORTED_10baseT_Full | 11493 SUPPORTED_100baseT_Half | 11494 SUPPORTED_100baseT_Full | 11495 SUPPORTED_1000baseT_Full | 11496 SUPPORTED_1000baseKX_Full | 11497 SUPPORTED_10000baseT_Full | 11498 SUPPORTED_10000baseKR_Full | 11499 SUPPORTED_20000baseKR2_Full | 11500 SUPPORTED_20000baseMLD2_Full | 11501 SUPPORTED_FIBRE | 11502 SUPPORTED_Autoneg | 11503 SUPPORTED_Pause | 11504 SUPPORTED_Asym_Pause), 11505 .media_type = ETH_PHY_UNSPECIFIED, 11506 .ver_addr = 0, 11507 .req_flow_ctrl = 0, 11508 .req_line_speed = 0, 11509 .speed_cap_mask = 0, 11510 /* req_duplex = */0, 11511 /* rsrv = */0, 11512 .config_init = (config_init_t)bnx2x_warpcore_config_init, 11513 .read_status = (read_status_t)bnx2x_warpcore_read_status, 11514 .link_reset = (link_reset_t)bnx2x_warpcore_link_reset, 11515 .config_loopback = (config_loopback_t)bnx2x_set_warpcore_loopback, 11516 .format_fw_ver = (format_fw_ver_t)NULL, 11517 .hw_reset = (hw_reset_t)bnx2x_warpcore_hw_reset, 11518 .set_link_led = (set_link_led_t)NULL, 11519 .phy_specific_func = (phy_specific_func_t)NULL 11520 }; 11521 11522 11523 static const struct bnx2x_phy phy_7101 = { 11524 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101, 11525 .addr = 0xff, 11526 .def_md_devad = 0, 11527 .flags = FLAGS_FAN_FAILURE_DET_REQ, 11528 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11529 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11530 .mdio_ctrl = 0, 11531 .supported = (SUPPORTED_10000baseT_Full | 11532 SUPPORTED_TP | 11533 SUPPORTED_Autoneg | 11534 SUPPORTED_Pause | 11535 SUPPORTED_Asym_Pause), 11536 .media_type = ETH_PHY_BASE_T, 11537 .ver_addr = 0, 11538 .req_flow_ctrl = 0, 11539 .req_line_speed = 0, 11540 .speed_cap_mask = 0, 11541 .req_duplex = 0, 11542 .rsrv = 0, 11543 .config_init = (config_init_t)bnx2x_7101_config_init, 11544 .read_status = (read_status_t)bnx2x_7101_read_status, 11545 .link_reset = (link_reset_t)bnx2x_common_ext_link_reset, 11546 .config_loopback = (config_loopback_t)bnx2x_7101_config_loopback, 11547 .format_fw_ver = (format_fw_ver_t)bnx2x_7101_format_ver, 11548 .hw_reset = (hw_reset_t)bnx2x_7101_hw_reset, 11549 .set_link_led = (set_link_led_t)bnx2x_7101_set_link_led, 11550 .phy_specific_func = (phy_specific_func_t)NULL 11551 }; 11552 static const struct bnx2x_phy phy_8073 = { 11553 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073, 11554 .addr = 0xff, 11555 .def_md_devad = 0, 11556 .flags = 0, 11557 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11558 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11559 .mdio_ctrl = 0, 11560 .supported = (SUPPORTED_10000baseT_Full | 11561 SUPPORTED_2500baseX_Full | 11562 SUPPORTED_1000baseT_Full | 11563 SUPPORTED_FIBRE | 11564 SUPPORTED_Autoneg | 11565 SUPPORTED_Pause | 11566 SUPPORTED_Asym_Pause), 11567 .media_type = ETH_PHY_KR, 11568 .ver_addr = 0, 11569 .req_flow_ctrl = 0, 11570 .req_line_speed = 0, 11571 .speed_cap_mask = 0, 11572 .req_duplex = 0, 11573 .rsrv = 0, 11574 .config_init = (config_init_t)bnx2x_8073_config_init, 11575 .read_status = (read_status_t)bnx2x_8073_read_status, 11576 .link_reset = (link_reset_t)bnx2x_8073_link_reset, 11577 .config_loopback = (config_loopback_t)NULL, 11578 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver, 11579 .hw_reset = (hw_reset_t)NULL, 11580 .set_link_led = (set_link_led_t)NULL, 11581 .phy_specific_func = (phy_specific_func_t)bnx2x_8073_specific_func 11582 }; 11583 static const struct bnx2x_phy phy_8705 = { 11584 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705, 11585 .addr = 0xff, 11586 .def_md_devad = 0, 11587 .flags = FLAGS_INIT_XGXS_FIRST, 11588 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11589 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11590 .mdio_ctrl = 0, 11591 .supported = (SUPPORTED_10000baseT_Full | 11592 SUPPORTED_FIBRE | 11593 SUPPORTED_Pause | 11594 SUPPORTED_Asym_Pause), 11595 .media_type = ETH_PHY_XFP_FIBER, 11596 .ver_addr = 0, 11597 .req_flow_ctrl = 0, 11598 .req_line_speed = 0, 11599 .speed_cap_mask = 0, 11600 .req_duplex = 0, 11601 .rsrv = 0, 11602 .config_init = (config_init_t)bnx2x_8705_config_init, 11603 .read_status = (read_status_t)bnx2x_8705_read_status, 11604 .link_reset = (link_reset_t)bnx2x_common_ext_link_reset, 11605 .config_loopback = (config_loopback_t)NULL, 11606 .format_fw_ver = (format_fw_ver_t)bnx2x_null_format_ver, 11607 .hw_reset = (hw_reset_t)NULL, 11608 .set_link_led = (set_link_led_t)NULL, 11609 .phy_specific_func = (phy_specific_func_t)NULL 11610 }; 11611 static const struct bnx2x_phy phy_8706 = { 11612 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706, 11613 .addr = 0xff, 11614 .def_md_devad = 0, 11615 .flags = FLAGS_INIT_XGXS_FIRST, 11616 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11617 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11618 .mdio_ctrl = 0, 11619 .supported = (SUPPORTED_10000baseT_Full | 11620 SUPPORTED_1000baseT_Full | 11621 SUPPORTED_FIBRE | 11622 SUPPORTED_Pause | 11623 SUPPORTED_Asym_Pause), 11624 .media_type = ETH_PHY_SFPP_10G_FIBER, 11625 .ver_addr = 0, 11626 .req_flow_ctrl = 0, 11627 .req_line_speed = 0, 11628 .speed_cap_mask = 0, 11629 .req_duplex = 0, 11630 .rsrv = 0, 11631 .config_init = (config_init_t)bnx2x_8706_config_init, 11632 .read_status = (read_status_t)bnx2x_8706_read_status, 11633 .link_reset = (link_reset_t)bnx2x_common_ext_link_reset, 11634 .config_loopback = (config_loopback_t)NULL, 11635 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver, 11636 .hw_reset = (hw_reset_t)NULL, 11637 .set_link_led = (set_link_led_t)NULL, 11638 .phy_specific_func = (phy_specific_func_t)NULL 11639 }; 11640 11641 static const struct bnx2x_phy phy_8726 = { 11642 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726, 11643 .addr = 0xff, 11644 .def_md_devad = 0, 11645 .flags = (FLAGS_INIT_XGXS_FIRST | 11646 FLAGS_TX_ERROR_CHECK), 11647 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11648 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11649 .mdio_ctrl = 0, 11650 .supported = (SUPPORTED_10000baseT_Full | 11651 SUPPORTED_1000baseT_Full | 11652 SUPPORTED_Autoneg | 11653 SUPPORTED_FIBRE | 11654 SUPPORTED_Pause | 11655 SUPPORTED_Asym_Pause), 11656 .media_type = ETH_PHY_NOT_PRESENT, 11657 .ver_addr = 0, 11658 .req_flow_ctrl = 0, 11659 .req_line_speed = 0, 11660 .speed_cap_mask = 0, 11661 .req_duplex = 0, 11662 .rsrv = 0, 11663 .config_init = (config_init_t)bnx2x_8726_config_init, 11664 .read_status = (read_status_t)bnx2x_8726_read_status, 11665 .link_reset = (link_reset_t)bnx2x_8726_link_reset, 11666 .config_loopback = (config_loopback_t)bnx2x_8726_config_loopback, 11667 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver, 11668 .hw_reset = (hw_reset_t)NULL, 11669 .set_link_led = (set_link_led_t)NULL, 11670 .phy_specific_func = (phy_specific_func_t)NULL 11671 }; 11672 11673 static const struct bnx2x_phy phy_8727 = { 11674 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727, 11675 .addr = 0xff, 11676 .def_md_devad = 0, 11677 .flags = (FLAGS_FAN_FAILURE_DET_REQ | 11678 FLAGS_TX_ERROR_CHECK), 11679 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11680 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11681 .mdio_ctrl = 0, 11682 .supported = (SUPPORTED_10000baseT_Full | 11683 SUPPORTED_1000baseT_Full | 11684 SUPPORTED_FIBRE | 11685 SUPPORTED_Pause | 11686 SUPPORTED_Asym_Pause), 11687 .media_type = ETH_PHY_NOT_PRESENT, 11688 .ver_addr = 0, 11689 .req_flow_ctrl = 0, 11690 .req_line_speed = 0, 11691 .speed_cap_mask = 0, 11692 .req_duplex = 0, 11693 .rsrv = 0, 11694 .config_init = (config_init_t)bnx2x_8727_config_init, 11695 .read_status = (read_status_t)bnx2x_8727_read_status, 11696 .link_reset = (link_reset_t)bnx2x_8727_link_reset, 11697 .config_loopback = (config_loopback_t)NULL, 11698 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver, 11699 .hw_reset = (hw_reset_t)bnx2x_8727_hw_reset, 11700 .set_link_led = (set_link_led_t)bnx2x_8727_set_link_led, 11701 .phy_specific_func = (phy_specific_func_t)bnx2x_8727_specific_func 11702 }; 11703 static const struct bnx2x_phy phy_8481 = { 11704 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481, 11705 .addr = 0xff, 11706 .def_md_devad = 0, 11707 .flags = FLAGS_FAN_FAILURE_DET_REQ | 11708 FLAGS_REARM_LATCH_SIGNAL, 11709 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11710 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11711 .mdio_ctrl = 0, 11712 .supported = (SUPPORTED_10baseT_Half | 11713 SUPPORTED_10baseT_Full | 11714 SUPPORTED_100baseT_Half | 11715 SUPPORTED_100baseT_Full | 11716 SUPPORTED_1000baseT_Full | 11717 SUPPORTED_10000baseT_Full | 11718 SUPPORTED_TP | 11719 SUPPORTED_Autoneg | 11720 SUPPORTED_Pause | 11721 SUPPORTED_Asym_Pause), 11722 .media_type = ETH_PHY_BASE_T, 11723 .ver_addr = 0, 11724 .req_flow_ctrl = 0, 11725 .req_line_speed = 0, 11726 .speed_cap_mask = 0, 11727 .req_duplex = 0, 11728 .rsrv = 0, 11729 .config_init = (config_init_t)bnx2x_8481_config_init, 11730 .read_status = (read_status_t)bnx2x_848xx_read_status, 11731 .link_reset = (link_reset_t)bnx2x_8481_link_reset, 11732 .config_loopback = (config_loopback_t)NULL, 11733 .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver, 11734 .hw_reset = (hw_reset_t)bnx2x_8481_hw_reset, 11735 .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led, 11736 .phy_specific_func = (phy_specific_func_t)NULL 11737 }; 11738 11739 static const struct bnx2x_phy phy_84823 = { 11740 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823, 11741 .addr = 0xff, 11742 .def_md_devad = 0, 11743 .flags = (FLAGS_FAN_FAILURE_DET_REQ | 11744 FLAGS_REARM_LATCH_SIGNAL | 11745 FLAGS_TX_ERROR_CHECK), 11746 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11747 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11748 .mdio_ctrl = 0, 11749 .supported = (SUPPORTED_10baseT_Half | 11750 SUPPORTED_10baseT_Full | 11751 SUPPORTED_100baseT_Half | 11752 SUPPORTED_100baseT_Full | 11753 SUPPORTED_1000baseT_Full | 11754 SUPPORTED_10000baseT_Full | 11755 SUPPORTED_TP | 11756 SUPPORTED_Autoneg | 11757 SUPPORTED_Pause | 11758 SUPPORTED_Asym_Pause), 11759 .media_type = ETH_PHY_BASE_T, 11760 .ver_addr = 0, 11761 .req_flow_ctrl = 0, 11762 .req_line_speed = 0, 11763 .speed_cap_mask = 0, 11764 .req_duplex = 0, 11765 .rsrv = 0, 11766 .config_init = (config_init_t)bnx2x_848x3_config_init, 11767 .read_status = (read_status_t)bnx2x_848xx_read_status, 11768 .link_reset = (link_reset_t)bnx2x_848x3_link_reset, 11769 .config_loopback = (config_loopback_t)NULL, 11770 .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver, 11771 .hw_reset = (hw_reset_t)NULL, 11772 .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led, 11773 .phy_specific_func = (phy_specific_func_t)bnx2x_848xx_specific_func 11774 }; 11775 11776 static const struct bnx2x_phy phy_84833 = { 11777 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833, 11778 .addr = 0xff, 11779 .def_md_devad = 0, 11780 .flags = (FLAGS_FAN_FAILURE_DET_REQ | 11781 FLAGS_REARM_LATCH_SIGNAL | 11782 FLAGS_TX_ERROR_CHECK), 11783 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11784 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11785 .mdio_ctrl = 0, 11786 .supported = (SUPPORTED_100baseT_Half | 11787 SUPPORTED_100baseT_Full | 11788 SUPPORTED_1000baseT_Full | 11789 SUPPORTED_10000baseT_Full | 11790 SUPPORTED_TP | 11791 SUPPORTED_Autoneg | 11792 SUPPORTED_Pause | 11793 SUPPORTED_Asym_Pause), 11794 .media_type = ETH_PHY_BASE_T, 11795 .ver_addr = 0, 11796 .req_flow_ctrl = 0, 11797 .req_line_speed = 0, 11798 .speed_cap_mask = 0, 11799 .req_duplex = 0, 11800 .rsrv = 0, 11801 .config_init = (config_init_t)bnx2x_848x3_config_init, 11802 .read_status = (read_status_t)bnx2x_848xx_read_status, 11803 .link_reset = (link_reset_t)bnx2x_848x3_link_reset, 11804 .config_loopback = (config_loopback_t)NULL, 11805 .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver, 11806 .hw_reset = (hw_reset_t)bnx2x_84833_hw_reset_phy, 11807 .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led, 11808 .phy_specific_func = (phy_specific_func_t)bnx2x_848xx_specific_func 11809 }; 11810 11811 static const struct bnx2x_phy phy_84834 = { 11812 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834, 11813 .addr = 0xff, 11814 .def_md_devad = 0, 11815 .flags = FLAGS_FAN_FAILURE_DET_REQ | 11816 FLAGS_REARM_LATCH_SIGNAL, 11817 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11818 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11819 .mdio_ctrl = 0, 11820 .supported = (SUPPORTED_100baseT_Half | 11821 SUPPORTED_100baseT_Full | 11822 SUPPORTED_1000baseT_Full | 11823 SUPPORTED_10000baseT_Full | 11824 SUPPORTED_TP | 11825 SUPPORTED_Autoneg | 11826 SUPPORTED_Pause | 11827 SUPPORTED_Asym_Pause), 11828 .media_type = ETH_PHY_BASE_T, 11829 .ver_addr = 0, 11830 .req_flow_ctrl = 0, 11831 .req_line_speed = 0, 11832 .speed_cap_mask = 0, 11833 .req_duplex = 0, 11834 .rsrv = 0, 11835 .config_init = (config_init_t)bnx2x_848x3_config_init, 11836 .read_status = (read_status_t)bnx2x_848xx_read_status, 11837 .link_reset = (link_reset_t)bnx2x_848x3_link_reset, 11838 .config_loopback = (config_loopback_t)NULL, 11839 .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver, 11840 .hw_reset = (hw_reset_t)bnx2x_84833_hw_reset_phy, 11841 .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led, 11842 .phy_specific_func = (phy_specific_func_t)bnx2x_848xx_specific_func 11843 }; 11844 11845 static const struct bnx2x_phy phy_54618se = { 11846 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE, 11847 .addr = 0xff, 11848 .def_md_devad = 0, 11849 .flags = FLAGS_INIT_XGXS_FIRST, 11850 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11851 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11852 .mdio_ctrl = 0, 11853 .supported = (SUPPORTED_10baseT_Half | 11854 SUPPORTED_10baseT_Full | 11855 SUPPORTED_100baseT_Half | 11856 SUPPORTED_100baseT_Full | 11857 SUPPORTED_1000baseT_Full | 11858 SUPPORTED_TP | 11859 SUPPORTED_Autoneg | 11860 SUPPORTED_Pause | 11861 SUPPORTED_Asym_Pause), 11862 .media_type = ETH_PHY_BASE_T, 11863 .ver_addr = 0, 11864 .req_flow_ctrl = 0, 11865 .req_line_speed = 0, 11866 .speed_cap_mask = 0, 11867 /* req_duplex = */0, 11868 /* rsrv = */0, 11869 .config_init = (config_init_t)bnx2x_54618se_config_init, 11870 .read_status = (read_status_t)bnx2x_54618se_read_status, 11871 .link_reset = (link_reset_t)bnx2x_54618se_link_reset, 11872 .config_loopback = (config_loopback_t)bnx2x_54618se_config_loopback, 11873 .format_fw_ver = (format_fw_ver_t)NULL, 11874 .hw_reset = (hw_reset_t)NULL, 11875 .set_link_led = (set_link_led_t)bnx2x_5461x_set_link_led, 11876 .phy_specific_func = (phy_specific_func_t)bnx2x_54618se_specific_func 11877 }; 11878 /*****************************************************************/ 11879 /* */ 11880 /* Populate the phy according. Main function: bnx2x_populate_phy */ 11881 /* */ 11882 /*****************************************************************/ 11883 11884 static void bnx2x_populate_preemphasis(struct bnx2x *bp, u32 shmem_base, 11885 struct bnx2x_phy *phy, u8 port, 11886 u8 phy_index) 11887 { 11888 /* Get the 4 lanes xgxs config rx and tx */ 11889 u32 rx = 0, tx = 0, i; 11890 for (i = 0; i < 2; i++) { 11891 /* INT_PHY and EXT_PHY1 share the same value location in 11892 * the shmem. When num_phys is greater than 1, than this value 11893 * applies only to EXT_PHY1 11894 */ 11895 if (phy_index == INT_PHY || phy_index == EXT_PHY1) { 11896 rx = REG_RD(bp, shmem_base + 11897 offsetof(struct shmem_region, 11898 dev_info.port_hw_config[port].xgxs_config_rx[i<<1])); 11899 11900 tx = REG_RD(bp, shmem_base + 11901 offsetof(struct shmem_region, 11902 dev_info.port_hw_config[port].xgxs_config_tx[i<<1])); 11903 } else { 11904 rx = REG_RD(bp, shmem_base + 11905 offsetof(struct shmem_region, 11906 dev_info.port_hw_config[port].xgxs_config2_rx[i<<1])); 11907 11908 tx = REG_RD(bp, shmem_base + 11909 offsetof(struct shmem_region, 11910 dev_info.port_hw_config[port].xgxs_config2_rx[i<<1])); 11911 } 11912 11913 phy->rx_preemphasis[i << 1] = ((rx>>16) & 0xffff); 11914 phy->rx_preemphasis[(i << 1) + 1] = (rx & 0xffff); 11915 11916 phy->tx_preemphasis[i << 1] = ((tx>>16) & 0xffff); 11917 phy->tx_preemphasis[(i << 1) + 1] = (tx & 0xffff); 11918 } 11919 } 11920 11921 static u32 bnx2x_get_ext_phy_config(struct bnx2x *bp, u32 shmem_base, 11922 u8 phy_index, u8 port) 11923 { 11924 u32 ext_phy_config = 0; 11925 switch (phy_index) { 11926 case EXT_PHY1: 11927 ext_phy_config = REG_RD(bp, shmem_base + 11928 offsetof(struct shmem_region, 11929 dev_info.port_hw_config[port].external_phy_config)); 11930 break; 11931 case EXT_PHY2: 11932 ext_phy_config = REG_RD(bp, shmem_base + 11933 offsetof(struct shmem_region, 11934 dev_info.port_hw_config[port].external_phy_config2)); 11935 break; 11936 default: 11937 DP(NETIF_MSG_LINK, "Invalid phy_index %d\n", phy_index); 11938 return -EINVAL; 11939 } 11940 11941 return ext_phy_config; 11942 } 11943 static int bnx2x_populate_int_phy(struct bnx2x *bp, u32 shmem_base, u8 port, 11944 struct bnx2x_phy *phy) 11945 { 11946 u32 phy_addr; 11947 u32 chip_id; 11948 u32 switch_cfg = (REG_RD(bp, shmem_base + 11949 offsetof(struct shmem_region, 11950 dev_info.port_feature_config[port].link_config)) & 11951 PORT_FEATURE_CONNECTED_SWITCH_MASK); 11952 chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) | 11953 ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12); 11954 11955 DP(NETIF_MSG_LINK, ":chip_id = 0x%x\n", chip_id); 11956 if (USES_WARPCORE(bp)) { 11957 u32 serdes_net_if; 11958 phy_addr = REG_RD(bp, 11959 MISC_REG_WC0_CTRL_PHY_ADDR); 11960 *phy = phy_warpcore; 11961 if (REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR) == 0x3) 11962 phy->flags |= FLAGS_4_PORT_MODE; 11963 else 11964 phy->flags &= ~FLAGS_4_PORT_MODE; 11965 /* Check Dual mode */ 11966 serdes_net_if = (REG_RD(bp, shmem_base + 11967 offsetof(struct shmem_region, dev_info. 11968 port_hw_config[port].default_cfg)) & 11969 PORT_HW_CFG_NET_SERDES_IF_MASK); 11970 /* Set the appropriate supported and flags indications per 11971 * interface type of the chip 11972 */ 11973 switch (serdes_net_if) { 11974 case PORT_HW_CFG_NET_SERDES_IF_SGMII: 11975 phy->supported &= (SUPPORTED_10baseT_Half | 11976 SUPPORTED_10baseT_Full | 11977 SUPPORTED_100baseT_Half | 11978 SUPPORTED_100baseT_Full | 11979 SUPPORTED_1000baseT_Full | 11980 SUPPORTED_FIBRE | 11981 SUPPORTED_Autoneg | 11982 SUPPORTED_Pause | 11983 SUPPORTED_Asym_Pause); 11984 phy->media_type = ETH_PHY_BASE_T; 11985 break; 11986 case PORT_HW_CFG_NET_SERDES_IF_XFI: 11987 phy->supported &= (SUPPORTED_1000baseT_Full | 11988 SUPPORTED_10000baseT_Full | 11989 SUPPORTED_FIBRE | 11990 SUPPORTED_Pause | 11991 SUPPORTED_Asym_Pause); 11992 phy->media_type = ETH_PHY_XFP_FIBER; 11993 break; 11994 case PORT_HW_CFG_NET_SERDES_IF_SFI: 11995 phy->supported &= (SUPPORTED_1000baseT_Full | 11996 SUPPORTED_10000baseT_Full | 11997 SUPPORTED_FIBRE | 11998 SUPPORTED_Pause | 11999 SUPPORTED_Asym_Pause); 12000 phy->media_type = ETH_PHY_SFPP_10G_FIBER; 12001 break; 12002 case PORT_HW_CFG_NET_SERDES_IF_KR: 12003 phy->media_type = ETH_PHY_KR; 12004 phy->supported &= (SUPPORTED_1000baseKX_Full | 12005 SUPPORTED_10000baseKR_Full | 12006 SUPPORTED_FIBRE | 12007 SUPPORTED_Autoneg | 12008 SUPPORTED_Pause | 12009 SUPPORTED_Asym_Pause); 12010 break; 12011 case PORT_HW_CFG_NET_SERDES_IF_DXGXS: 12012 phy->media_type = ETH_PHY_KR; 12013 phy->flags |= FLAGS_WC_DUAL_MODE; 12014 phy->supported &= (SUPPORTED_20000baseMLD2_Full | 12015 SUPPORTED_FIBRE | 12016 SUPPORTED_Pause | 12017 SUPPORTED_Asym_Pause); 12018 break; 12019 case PORT_HW_CFG_NET_SERDES_IF_KR2: 12020 phy->media_type = ETH_PHY_KR; 12021 phy->flags |= FLAGS_WC_DUAL_MODE; 12022 phy->supported &= (SUPPORTED_20000baseKR2_Full | 12023 SUPPORTED_10000baseKR_Full | 12024 SUPPORTED_1000baseKX_Full | 12025 SUPPORTED_Autoneg | 12026 SUPPORTED_FIBRE | 12027 SUPPORTED_Pause | 12028 SUPPORTED_Asym_Pause); 12029 phy->flags &= ~FLAGS_TX_ERROR_CHECK; 12030 break; 12031 default: 12032 DP(NETIF_MSG_LINK, "Unknown WC interface type 0x%x\n", 12033 serdes_net_if); 12034 break; 12035 } 12036 12037 /* Enable MDC/MDIO work-around for E3 A0 since free running MDC 12038 * was not set as expected. For B0, ECO will be enabled so there 12039 * won't be an issue there 12040 */ 12041 if (CHIP_REV(bp) == CHIP_REV_Ax) 12042 phy->flags |= FLAGS_MDC_MDIO_WA; 12043 else 12044 phy->flags |= FLAGS_MDC_MDIO_WA_B0; 12045 } else { 12046 switch (switch_cfg) { 12047 case SWITCH_CFG_1G: 12048 phy_addr = REG_RD(bp, 12049 NIG_REG_SERDES0_CTRL_PHY_ADDR + 12050 port * 0x10); 12051 *phy = phy_serdes; 12052 break; 12053 case SWITCH_CFG_10G: 12054 phy_addr = REG_RD(bp, 12055 NIG_REG_XGXS0_CTRL_PHY_ADDR + 12056 port * 0x18); 12057 *phy = phy_xgxs; 12058 break; 12059 default: 12060 DP(NETIF_MSG_LINK, "Invalid switch_cfg\n"); 12061 return -EINVAL; 12062 } 12063 } 12064 phy->addr = (u8)phy_addr; 12065 phy->mdio_ctrl = bnx2x_get_emac_base(bp, 12066 SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH, 12067 port); 12068 if (CHIP_IS_E2(bp)) 12069 phy->def_md_devad = E2_DEFAULT_PHY_DEV_ADDR; 12070 else 12071 phy->def_md_devad = DEFAULT_PHY_DEV_ADDR; 12072 12073 DP(NETIF_MSG_LINK, "Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x\n", 12074 port, phy->addr, phy->mdio_ctrl); 12075 12076 bnx2x_populate_preemphasis(bp, shmem_base, phy, port, INT_PHY); 12077 return 0; 12078 } 12079 12080 static int bnx2x_populate_ext_phy(struct bnx2x *bp, 12081 u8 phy_index, 12082 u32 shmem_base, 12083 u32 shmem2_base, 12084 u8 port, 12085 struct bnx2x_phy *phy) 12086 { 12087 u32 ext_phy_config, phy_type, config2; 12088 u32 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH; 12089 ext_phy_config = bnx2x_get_ext_phy_config(bp, shmem_base, 12090 phy_index, port); 12091 phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config); 12092 /* Select the phy type */ 12093 switch (phy_type) { 12094 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073: 12095 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED; 12096 *phy = phy_8073; 12097 break; 12098 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705: 12099 *phy = phy_8705; 12100 break; 12101 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706: 12102 *phy = phy_8706; 12103 break; 12104 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: 12105 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1; 12106 *phy = phy_8726; 12107 break; 12108 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC: 12109 /* BCM8727_NOC => BCM8727 no over current */ 12110 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1; 12111 *phy = phy_8727; 12112 phy->flags |= FLAGS_NOC; 12113 break; 12114 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722: 12115 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: 12116 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1; 12117 *phy = phy_8727; 12118 break; 12119 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481: 12120 *phy = phy_8481; 12121 break; 12122 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823: 12123 *phy = phy_84823; 12124 break; 12125 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833: 12126 *phy = phy_84833; 12127 break; 12128 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834: 12129 *phy = phy_84834; 12130 break; 12131 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616: 12132 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE: 12133 *phy = phy_54618se; 12134 if (phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) 12135 phy->flags |= FLAGS_EEE; 12136 break; 12137 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101: 12138 *phy = phy_7101; 12139 break; 12140 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE: 12141 *phy = phy_null; 12142 return -EINVAL; 12143 default: 12144 *phy = phy_null; 12145 /* In case external PHY wasn't found */ 12146 if ((phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) && 12147 (phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)) 12148 return -EINVAL; 12149 return 0; 12150 } 12151 12152 phy->addr = XGXS_EXT_PHY_ADDR(ext_phy_config); 12153 bnx2x_populate_preemphasis(bp, shmem_base, phy, port, phy_index); 12154 12155 /* The shmem address of the phy version is located on different 12156 * structures. In case this structure is too old, do not set 12157 * the address 12158 */ 12159 config2 = REG_RD(bp, shmem_base + offsetof(struct shmem_region, 12160 dev_info.shared_hw_config.config2)); 12161 if (phy_index == EXT_PHY1) { 12162 phy->ver_addr = shmem_base + offsetof(struct shmem_region, 12163 port_mb[port].ext_phy_fw_version); 12164 12165 /* Check specific mdc mdio settings */ 12166 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK) 12167 mdc_mdio_access = config2 & 12168 SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK; 12169 } else { 12170 u32 size = REG_RD(bp, shmem2_base); 12171 12172 if (size > 12173 offsetof(struct shmem2_region, ext_phy_fw_version2)) { 12174 phy->ver_addr = shmem2_base + 12175 offsetof(struct shmem2_region, 12176 ext_phy_fw_version2[port]); 12177 } 12178 /* Check specific mdc mdio settings */ 12179 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) 12180 mdc_mdio_access = (config2 & 12181 SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) >> 12182 (SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT - 12183 SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT); 12184 } 12185 phy->mdio_ctrl = bnx2x_get_emac_base(bp, mdc_mdio_access, port); 12186 12187 if (((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) || 12188 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) && 12189 (phy->ver_addr)) { 12190 /* Remove 100Mb link supported for BCM84833/4 when phy fw 12191 * version lower than or equal to 1.39 12192 */ 12193 u32 raw_ver = REG_RD(bp, phy->ver_addr); 12194 if (((raw_ver & 0x7F) <= 39) && 12195 (((raw_ver & 0xF80) >> 7) <= 1)) 12196 phy->supported &= ~(SUPPORTED_100baseT_Half | 12197 SUPPORTED_100baseT_Full); 12198 } 12199 12200 DP(NETIF_MSG_LINK, "phy_type 0x%x port %d found in index %d\n", 12201 phy_type, port, phy_index); 12202 DP(NETIF_MSG_LINK, " addr=0x%x, mdio_ctl=0x%x\n", 12203 phy->addr, phy->mdio_ctrl); 12204 return 0; 12205 } 12206 12207 static int bnx2x_populate_phy(struct bnx2x *bp, u8 phy_index, u32 shmem_base, 12208 u32 shmem2_base, u8 port, struct bnx2x_phy *phy) 12209 { 12210 int status = 0; 12211 phy->type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN; 12212 if (phy_index == INT_PHY) 12213 return bnx2x_populate_int_phy(bp, shmem_base, port, phy); 12214 status = bnx2x_populate_ext_phy(bp, phy_index, shmem_base, shmem2_base, 12215 port, phy); 12216 return status; 12217 } 12218 12219 static void bnx2x_phy_def_cfg(struct link_params *params, 12220 struct bnx2x_phy *phy, 12221 u8 phy_index) 12222 { 12223 struct bnx2x *bp = params->bp; 12224 u32 link_config; 12225 /* Populate the default phy configuration for MF mode */ 12226 if (phy_index == EXT_PHY2) { 12227 link_config = REG_RD(bp, params->shmem_base + 12228 offsetof(struct shmem_region, dev_info. 12229 port_feature_config[params->port].link_config2)); 12230 phy->speed_cap_mask = REG_RD(bp, params->shmem_base + 12231 offsetof(struct shmem_region, 12232 dev_info. 12233 port_hw_config[params->port].speed_capability_mask2)); 12234 } else { 12235 link_config = REG_RD(bp, params->shmem_base + 12236 offsetof(struct shmem_region, dev_info. 12237 port_feature_config[params->port].link_config)); 12238 phy->speed_cap_mask = REG_RD(bp, params->shmem_base + 12239 offsetof(struct shmem_region, 12240 dev_info. 12241 port_hw_config[params->port].speed_capability_mask)); 12242 } 12243 DP(NETIF_MSG_LINK, 12244 "Default config phy idx %x cfg 0x%x speed_cap_mask 0x%x\n", 12245 phy_index, link_config, phy->speed_cap_mask); 12246 12247 phy->req_duplex = DUPLEX_FULL; 12248 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) { 12249 case PORT_FEATURE_LINK_SPEED_10M_HALF: 12250 phy->req_duplex = DUPLEX_HALF; 12251 case PORT_FEATURE_LINK_SPEED_10M_FULL: 12252 phy->req_line_speed = SPEED_10; 12253 break; 12254 case PORT_FEATURE_LINK_SPEED_100M_HALF: 12255 phy->req_duplex = DUPLEX_HALF; 12256 case PORT_FEATURE_LINK_SPEED_100M_FULL: 12257 phy->req_line_speed = SPEED_100; 12258 break; 12259 case PORT_FEATURE_LINK_SPEED_1G: 12260 phy->req_line_speed = SPEED_1000; 12261 break; 12262 case PORT_FEATURE_LINK_SPEED_2_5G: 12263 phy->req_line_speed = SPEED_2500; 12264 break; 12265 case PORT_FEATURE_LINK_SPEED_10G_CX4: 12266 phy->req_line_speed = SPEED_10000; 12267 break; 12268 default: 12269 phy->req_line_speed = SPEED_AUTO_NEG; 12270 break; 12271 } 12272 12273 switch (link_config & PORT_FEATURE_FLOW_CONTROL_MASK) { 12274 case PORT_FEATURE_FLOW_CONTROL_AUTO: 12275 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_AUTO; 12276 break; 12277 case PORT_FEATURE_FLOW_CONTROL_TX: 12278 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_TX; 12279 break; 12280 case PORT_FEATURE_FLOW_CONTROL_RX: 12281 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_RX; 12282 break; 12283 case PORT_FEATURE_FLOW_CONTROL_BOTH: 12284 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_BOTH; 12285 break; 12286 default: 12287 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_NONE; 12288 break; 12289 } 12290 } 12291 12292 u32 bnx2x_phy_selection(struct link_params *params) 12293 { 12294 u32 phy_config_swapped, prio_cfg; 12295 u32 return_cfg = PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT; 12296 12297 phy_config_swapped = params->multi_phy_config & 12298 PORT_HW_CFG_PHY_SWAPPED_ENABLED; 12299 12300 prio_cfg = params->multi_phy_config & 12301 PORT_HW_CFG_PHY_SELECTION_MASK; 12302 12303 if (phy_config_swapped) { 12304 switch (prio_cfg) { 12305 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY: 12306 return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY; 12307 break; 12308 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY: 12309 return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY; 12310 break; 12311 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY: 12312 return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY; 12313 break; 12314 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY: 12315 return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY; 12316 break; 12317 } 12318 } else 12319 return_cfg = prio_cfg; 12320 12321 return return_cfg; 12322 } 12323 12324 int bnx2x_phy_probe(struct link_params *params) 12325 { 12326 u8 phy_index, actual_phy_idx; 12327 u32 phy_config_swapped, sync_offset, media_types; 12328 struct bnx2x *bp = params->bp; 12329 struct bnx2x_phy *phy; 12330 params->num_phys = 0; 12331 DP(NETIF_MSG_LINK, "Begin phy probe\n"); 12332 phy_config_swapped = params->multi_phy_config & 12333 PORT_HW_CFG_PHY_SWAPPED_ENABLED; 12334 12335 for (phy_index = INT_PHY; phy_index < MAX_PHYS; 12336 phy_index++) { 12337 actual_phy_idx = phy_index; 12338 if (phy_config_swapped) { 12339 if (phy_index == EXT_PHY1) 12340 actual_phy_idx = EXT_PHY2; 12341 else if (phy_index == EXT_PHY2) 12342 actual_phy_idx = EXT_PHY1; 12343 } 12344 DP(NETIF_MSG_LINK, "phy_config_swapped %x, phy_index %x," 12345 " actual_phy_idx %x\n", phy_config_swapped, 12346 phy_index, actual_phy_idx); 12347 phy = ¶ms->phy[actual_phy_idx]; 12348 if (bnx2x_populate_phy(bp, phy_index, params->shmem_base, 12349 params->shmem2_base, params->port, 12350 phy) != 0) { 12351 params->num_phys = 0; 12352 DP(NETIF_MSG_LINK, "phy probe failed in phy index %d\n", 12353 phy_index); 12354 for (phy_index = INT_PHY; 12355 phy_index < MAX_PHYS; 12356 phy_index++) 12357 *phy = phy_null; 12358 return -EINVAL; 12359 } 12360 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN) 12361 break; 12362 12363 if (params->feature_config_flags & 12364 FEATURE_CONFIG_DISABLE_REMOTE_FAULT_DET) 12365 phy->flags &= ~FLAGS_TX_ERROR_CHECK; 12366 12367 if (!(params->feature_config_flags & 12368 FEATURE_CONFIG_MT_SUPPORT)) 12369 phy->flags |= FLAGS_MDC_MDIO_WA_G; 12370 12371 sync_offset = params->shmem_base + 12372 offsetof(struct shmem_region, 12373 dev_info.port_hw_config[params->port].media_type); 12374 media_types = REG_RD(bp, sync_offset); 12375 12376 /* Update media type for non-PMF sync only for the first time 12377 * In case the media type changes afterwards, it will be updated 12378 * using the update_status function 12379 */ 12380 if ((media_types & (PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK << 12381 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * 12382 actual_phy_idx))) == 0) { 12383 media_types |= ((phy->media_type & 12384 PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) << 12385 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * 12386 actual_phy_idx)); 12387 } 12388 REG_WR(bp, sync_offset, media_types); 12389 12390 bnx2x_phy_def_cfg(params, phy, phy_index); 12391 params->num_phys++; 12392 } 12393 12394 DP(NETIF_MSG_LINK, "End phy probe. #phys found %x\n", params->num_phys); 12395 return 0; 12396 } 12397 12398 static void bnx2x_init_bmac_loopback(struct link_params *params, 12399 struct link_vars *vars) 12400 { 12401 struct bnx2x *bp = params->bp; 12402 vars->link_up = 1; 12403 vars->line_speed = SPEED_10000; 12404 vars->duplex = DUPLEX_FULL; 12405 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; 12406 vars->mac_type = MAC_TYPE_BMAC; 12407 12408 vars->phy_flags = PHY_XGXS_FLAG; 12409 12410 bnx2x_xgxs_deassert(params); 12411 12412 /* Set bmac loopback */ 12413 bnx2x_bmac_enable(params, vars, 1, 1); 12414 12415 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); 12416 } 12417 12418 static void bnx2x_init_emac_loopback(struct link_params *params, 12419 struct link_vars *vars) 12420 { 12421 struct bnx2x *bp = params->bp; 12422 vars->link_up = 1; 12423 vars->line_speed = SPEED_1000; 12424 vars->duplex = DUPLEX_FULL; 12425 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; 12426 vars->mac_type = MAC_TYPE_EMAC; 12427 12428 vars->phy_flags = PHY_XGXS_FLAG; 12429 12430 bnx2x_xgxs_deassert(params); 12431 /* Set bmac loopback */ 12432 bnx2x_emac_enable(params, vars, 1); 12433 bnx2x_emac_program(params, vars); 12434 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); 12435 } 12436 12437 static void bnx2x_init_xmac_loopback(struct link_params *params, 12438 struct link_vars *vars) 12439 { 12440 struct bnx2x *bp = params->bp; 12441 vars->link_up = 1; 12442 if (!params->req_line_speed[0]) 12443 vars->line_speed = SPEED_10000; 12444 else 12445 vars->line_speed = params->req_line_speed[0]; 12446 vars->duplex = DUPLEX_FULL; 12447 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; 12448 vars->mac_type = MAC_TYPE_XMAC; 12449 vars->phy_flags = PHY_XGXS_FLAG; 12450 /* Set WC to loopback mode since link is required to provide clock 12451 * to the XMAC in 20G mode 12452 */ 12453 bnx2x_set_aer_mmd(params, ¶ms->phy[0]); 12454 bnx2x_warpcore_reset_lane(bp, ¶ms->phy[0], 0); 12455 params->phy[INT_PHY].config_loopback( 12456 ¶ms->phy[INT_PHY], 12457 params); 12458 12459 bnx2x_xmac_enable(params, vars, 1); 12460 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); 12461 } 12462 12463 static void bnx2x_init_umac_loopback(struct link_params *params, 12464 struct link_vars *vars) 12465 { 12466 struct bnx2x *bp = params->bp; 12467 vars->link_up = 1; 12468 vars->line_speed = SPEED_1000; 12469 vars->duplex = DUPLEX_FULL; 12470 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; 12471 vars->mac_type = MAC_TYPE_UMAC; 12472 vars->phy_flags = PHY_XGXS_FLAG; 12473 bnx2x_umac_enable(params, vars, 1); 12474 12475 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); 12476 } 12477 12478 static void bnx2x_init_xgxs_loopback(struct link_params *params, 12479 struct link_vars *vars) 12480 { 12481 struct bnx2x *bp = params->bp; 12482 struct bnx2x_phy *int_phy = ¶ms->phy[INT_PHY]; 12483 vars->link_up = 1; 12484 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; 12485 vars->duplex = DUPLEX_FULL; 12486 if (params->req_line_speed[0] == SPEED_1000) 12487 vars->line_speed = SPEED_1000; 12488 else if ((params->req_line_speed[0] == SPEED_20000) || 12489 (int_phy->flags & FLAGS_WC_DUAL_MODE)) 12490 vars->line_speed = SPEED_20000; 12491 else 12492 vars->line_speed = SPEED_10000; 12493 12494 if (!USES_WARPCORE(bp)) 12495 bnx2x_xgxs_deassert(params); 12496 bnx2x_link_initialize(params, vars); 12497 12498 if (params->req_line_speed[0] == SPEED_1000) { 12499 if (USES_WARPCORE(bp)) 12500 bnx2x_umac_enable(params, vars, 0); 12501 else { 12502 bnx2x_emac_program(params, vars); 12503 bnx2x_emac_enable(params, vars, 0); 12504 } 12505 } else { 12506 if (USES_WARPCORE(bp)) 12507 bnx2x_xmac_enable(params, vars, 0); 12508 else 12509 bnx2x_bmac_enable(params, vars, 0, 1); 12510 } 12511 12512 if (params->loopback_mode == LOOPBACK_XGXS) { 12513 /* Set 10G XGXS loopback */ 12514 int_phy->config_loopback(int_phy, params); 12515 } else { 12516 /* Set external phy loopback */ 12517 u8 phy_index; 12518 for (phy_index = EXT_PHY1; 12519 phy_index < params->num_phys; phy_index++) 12520 if (params->phy[phy_index].config_loopback) 12521 params->phy[phy_index].config_loopback( 12522 ¶ms->phy[phy_index], 12523 params); 12524 } 12525 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); 12526 12527 bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed); 12528 } 12529 12530 void bnx2x_set_rx_filter(struct link_params *params, u8 en) 12531 { 12532 struct bnx2x *bp = params->bp; 12533 u8 val = en * 0x1F; 12534 12535 /* Open / close the gate between the NIG and the BRB */ 12536 if (!CHIP_IS_E1x(bp)) 12537 val |= en * 0x20; 12538 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + params->port*4, val); 12539 12540 if (!CHIP_IS_E1(bp)) { 12541 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + params->port*4, 12542 en*0x3); 12543 } 12544 12545 REG_WR(bp, (params->port ? NIG_REG_LLH1_BRB1_NOT_MCP : 12546 NIG_REG_LLH0_BRB1_NOT_MCP), en); 12547 } 12548 static int bnx2x_avoid_link_flap(struct link_params *params, 12549 struct link_vars *vars) 12550 { 12551 u32 phy_idx; 12552 u32 dont_clear_stat, lfa_sts; 12553 struct bnx2x *bp = params->bp; 12554 12555 bnx2x_set_mdio_emac_per_phy(bp, params); 12556 /* Sync the link parameters */ 12557 bnx2x_link_status_update(params, vars); 12558 12559 /* 12560 * The module verification was already done by previous link owner, 12561 * so this call is meant only to get warning message 12562 */ 12563 12564 for (phy_idx = INT_PHY; phy_idx < params->num_phys; phy_idx++) { 12565 struct bnx2x_phy *phy = ¶ms->phy[phy_idx]; 12566 if (phy->phy_specific_func) { 12567 DP(NETIF_MSG_LINK, "Calling PHY specific func\n"); 12568 phy->phy_specific_func(phy, params, PHY_INIT); 12569 } 12570 if ((phy->media_type == ETH_PHY_SFPP_10G_FIBER) || 12571 (phy->media_type == ETH_PHY_SFP_1G_FIBER) || 12572 (phy->media_type == ETH_PHY_DA_TWINAX)) 12573 bnx2x_verify_sfp_module(phy, params); 12574 } 12575 lfa_sts = REG_RD(bp, params->lfa_base + 12576 offsetof(struct shmem_lfa, 12577 lfa_sts)); 12578 12579 dont_clear_stat = lfa_sts & SHMEM_LFA_DONT_CLEAR_STAT; 12580 12581 /* Re-enable the NIG/MAC */ 12582 if (CHIP_IS_E3(bp)) { 12583 if (!dont_clear_stat) { 12584 REG_WR(bp, GRCBASE_MISC + 12585 MISC_REGISTERS_RESET_REG_2_CLEAR, 12586 (MISC_REGISTERS_RESET_REG_2_MSTAT0 << 12587 params->port)); 12588 REG_WR(bp, GRCBASE_MISC + 12589 MISC_REGISTERS_RESET_REG_2_SET, 12590 (MISC_REGISTERS_RESET_REG_2_MSTAT0 << 12591 params->port)); 12592 } 12593 if (vars->line_speed < SPEED_10000) 12594 bnx2x_umac_enable(params, vars, 0); 12595 else 12596 bnx2x_xmac_enable(params, vars, 0); 12597 } else { 12598 if (vars->line_speed < SPEED_10000) 12599 bnx2x_emac_enable(params, vars, 0); 12600 else 12601 bnx2x_bmac_enable(params, vars, 0, !dont_clear_stat); 12602 } 12603 12604 /* Increment LFA count */ 12605 lfa_sts = ((lfa_sts & ~LINK_FLAP_AVOIDANCE_COUNT_MASK) | 12606 (((((lfa_sts & LINK_FLAP_AVOIDANCE_COUNT_MASK) >> 12607 LINK_FLAP_AVOIDANCE_COUNT_OFFSET) + 1) & 0xff) 12608 << LINK_FLAP_AVOIDANCE_COUNT_OFFSET)); 12609 /* Clear link flap reason */ 12610 lfa_sts &= ~LFA_LINK_FLAP_REASON_MASK; 12611 12612 REG_WR(bp, params->lfa_base + 12613 offsetof(struct shmem_lfa, lfa_sts), lfa_sts); 12614 12615 /* Disable NIG DRAIN */ 12616 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); 12617 12618 /* Enable interrupts */ 12619 bnx2x_link_int_enable(params); 12620 return 0; 12621 } 12622 12623 static void bnx2x_cannot_avoid_link_flap(struct link_params *params, 12624 struct link_vars *vars, 12625 int lfa_status) 12626 { 12627 u32 lfa_sts, cfg_idx, tmp_val; 12628 struct bnx2x *bp = params->bp; 12629 12630 bnx2x_link_reset(params, vars, 1); 12631 12632 if (!params->lfa_base) 12633 return; 12634 /* Store the new link parameters */ 12635 REG_WR(bp, params->lfa_base + 12636 offsetof(struct shmem_lfa, req_duplex), 12637 params->req_duplex[0] | (params->req_duplex[1] << 16)); 12638 12639 REG_WR(bp, params->lfa_base + 12640 offsetof(struct shmem_lfa, req_flow_ctrl), 12641 params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16)); 12642 12643 REG_WR(bp, params->lfa_base + 12644 offsetof(struct shmem_lfa, req_line_speed), 12645 params->req_line_speed[0] | (params->req_line_speed[1] << 16)); 12646 12647 for (cfg_idx = 0; cfg_idx < SHMEM_LINK_CONFIG_SIZE; cfg_idx++) { 12648 REG_WR(bp, params->lfa_base + 12649 offsetof(struct shmem_lfa, 12650 speed_cap_mask[cfg_idx]), 12651 params->speed_cap_mask[cfg_idx]); 12652 } 12653 12654 tmp_val = REG_RD(bp, params->lfa_base + 12655 offsetof(struct shmem_lfa, additional_config)); 12656 tmp_val &= ~REQ_FC_AUTO_ADV_MASK; 12657 tmp_val |= params->req_fc_auto_adv; 12658 12659 REG_WR(bp, params->lfa_base + 12660 offsetof(struct shmem_lfa, additional_config), tmp_val); 12661 12662 lfa_sts = REG_RD(bp, params->lfa_base + 12663 offsetof(struct shmem_lfa, lfa_sts)); 12664 12665 /* Clear the "Don't Clear Statistics" bit, and set reason */ 12666 lfa_sts &= ~SHMEM_LFA_DONT_CLEAR_STAT; 12667 12668 /* Set link flap reason */ 12669 lfa_sts &= ~LFA_LINK_FLAP_REASON_MASK; 12670 lfa_sts |= ((lfa_status & LFA_LINK_FLAP_REASON_MASK) << 12671 LFA_LINK_FLAP_REASON_OFFSET); 12672 12673 /* Increment link flap counter */ 12674 lfa_sts = ((lfa_sts & ~LINK_FLAP_COUNT_MASK) | 12675 (((((lfa_sts & LINK_FLAP_COUNT_MASK) >> 12676 LINK_FLAP_COUNT_OFFSET) + 1) & 0xff) 12677 << LINK_FLAP_COUNT_OFFSET)); 12678 REG_WR(bp, params->lfa_base + 12679 offsetof(struct shmem_lfa, lfa_sts), lfa_sts); 12680 /* Proceed with regular link initialization */ 12681 } 12682 12683 int bnx2x_phy_init(struct link_params *params, struct link_vars *vars) 12684 { 12685 int lfa_status; 12686 struct bnx2x *bp = params->bp; 12687 DP(NETIF_MSG_LINK, "Phy Initialization started\n"); 12688 DP(NETIF_MSG_LINK, "(1) req_speed %d, req_flowctrl %d\n", 12689 params->req_line_speed[0], params->req_flow_ctrl[0]); 12690 DP(NETIF_MSG_LINK, "(2) req_speed %d, req_flowctrl %d\n", 12691 params->req_line_speed[1], params->req_flow_ctrl[1]); 12692 DP(NETIF_MSG_LINK, "req_adv_flow_ctrl 0x%x\n", params->req_fc_auto_adv); 12693 vars->link_status = 0; 12694 vars->phy_link_up = 0; 12695 vars->link_up = 0; 12696 vars->line_speed = 0; 12697 vars->duplex = DUPLEX_FULL; 12698 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; 12699 vars->mac_type = MAC_TYPE_NONE; 12700 vars->phy_flags = 0; 12701 vars->check_kr2_recovery_cnt = 0; 12702 params->link_flags = PHY_INITIALIZED; 12703 /* Driver opens NIG-BRB filters */ 12704 bnx2x_set_rx_filter(params, 1); 12705 bnx2x_chng_link_count(params, true); 12706 /* Check if link flap can be avoided */ 12707 lfa_status = bnx2x_check_lfa(params); 12708 12709 if (lfa_status == 0) { 12710 DP(NETIF_MSG_LINK, "Link Flap Avoidance in progress\n"); 12711 return bnx2x_avoid_link_flap(params, vars); 12712 } 12713 12714 DP(NETIF_MSG_LINK, "Cannot avoid link flap lfa_sta=0x%x\n", 12715 lfa_status); 12716 bnx2x_cannot_avoid_link_flap(params, vars, lfa_status); 12717 12718 /* Disable attentions */ 12719 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4, 12720 (NIG_MASK_XGXS0_LINK_STATUS | 12721 NIG_MASK_XGXS0_LINK10G | 12722 NIG_MASK_SERDES0_LINK_STATUS | 12723 NIG_MASK_MI_INT)); 12724 12725 bnx2x_emac_init(params, vars); 12726 12727 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) 12728 vars->link_status |= LINK_STATUS_PFC_ENABLED; 12729 12730 if (params->num_phys == 0) { 12731 DP(NETIF_MSG_LINK, "No phy found for initialization !!\n"); 12732 return -EINVAL; 12733 } 12734 set_phy_vars(params, vars); 12735 12736 DP(NETIF_MSG_LINK, "Num of phys on board: %d\n", params->num_phys); 12737 switch (params->loopback_mode) { 12738 case LOOPBACK_BMAC: 12739 bnx2x_init_bmac_loopback(params, vars); 12740 break; 12741 case LOOPBACK_EMAC: 12742 bnx2x_init_emac_loopback(params, vars); 12743 break; 12744 case LOOPBACK_XMAC: 12745 bnx2x_init_xmac_loopback(params, vars); 12746 break; 12747 case LOOPBACK_UMAC: 12748 bnx2x_init_umac_loopback(params, vars); 12749 break; 12750 case LOOPBACK_XGXS: 12751 case LOOPBACK_EXT_PHY: 12752 bnx2x_init_xgxs_loopback(params, vars); 12753 break; 12754 default: 12755 if (!CHIP_IS_E3(bp)) { 12756 if (params->switch_cfg == SWITCH_CFG_10G) 12757 bnx2x_xgxs_deassert(params); 12758 else 12759 bnx2x_serdes_deassert(bp, params->port); 12760 } 12761 bnx2x_link_initialize(params, vars); 12762 msleep(30); 12763 bnx2x_link_int_enable(params); 12764 break; 12765 } 12766 bnx2x_update_mng(params, vars->link_status); 12767 12768 bnx2x_update_mng_eee(params, vars->eee_status); 12769 return 0; 12770 } 12771 12772 int bnx2x_link_reset(struct link_params *params, struct link_vars *vars, 12773 u8 reset_ext_phy) 12774 { 12775 struct bnx2x *bp = params->bp; 12776 u8 phy_index, port = params->port, clear_latch_ind = 0; 12777 DP(NETIF_MSG_LINK, "Resetting the link of port %d\n", port); 12778 /* Disable attentions */ 12779 vars->link_status = 0; 12780 bnx2x_chng_link_count(params, true); 12781 bnx2x_update_mng(params, vars->link_status); 12782 vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK | 12783 SHMEM_EEE_ACTIVE_BIT); 12784 bnx2x_update_mng_eee(params, vars->eee_status); 12785 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 12786 (NIG_MASK_XGXS0_LINK_STATUS | 12787 NIG_MASK_XGXS0_LINK10G | 12788 NIG_MASK_SERDES0_LINK_STATUS | 12789 NIG_MASK_MI_INT)); 12790 12791 /* Activate nig drain */ 12792 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1); 12793 12794 /* Disable nig egress interface */ 12795 if (!CHIP_IS_E3(bp)) { 12796 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0); 12797 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0); 12798 } 12799 12800 if (!CHIP_IS_E3(bp)) { 12801 bnx2x_set_bmac_rx(bp, params->chip_id, port, 0); 12802 } else { 12803 bnx2x_set_xmac_rxtx(params, 0); 12804 bnx2x_set_umac_rxtx(params, 0); 12805 } 12806 /* Disable emac */ 12807 if (!CHIP_IS_E3(bp)) 12808 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0); 12809 12810 usleep_range(10000, 20000); 12811 /* The PHY reset is controlled by GPIO 1 12812 * Hold it as vars low 12813 */ 12814 /* Clear link led */ 12815 bnx2x_set_mdio_emac_per_phy(bp, params); 12816 bnx2x_set_led(params, vars, LED_MODE_OFF, 0); 12817 12818 if (reset_ext_phy) { 12819 for (phy_index = EXT_PHY1; phy_index < params->num_phys; 12820 phy_index++) { 12821 if (params->phy[phy_index].link_reset) { 12822 bnx2x_set_aer_mmd(params, 12823 ¶ms->phy[phy_index]); 12824 params->phy[phy_index].link_reset( 12825 ¶ms->phy[phy_index], 12826 params); 12827 } 12828 if (params->phy[phy_index].flags & 12829 FLAGS_REARM_LATCH_SIGNAL) 12830 clear_latch_ind = 1; 12831 } 12832 } 12833 12834 if (clear_latch_ind) { 12835 /* Clear latching indication */ 12836 bnx2x_rearm_latch_signal(bp, port, 0); 12837 bnx2x_bits_dis(bp, NIG_REG_LATCH_BC_0 + port*4, 12838 1 << NIG_LATCH_BC_ENABLE_MI_INT); 12839 } 12840 if (params->phy[INT_PHY].link_reset) 12841 params->phy[INT_PHY].link_reset( 12842 ¶ms->phy[INT_PHY], params); 12843 12844 /* Disable nig ingress interface */ 12845 if (!CHIP_IS_E3(bp)) { 12846 /* Reset BigMac */ 12847 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 12848 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); 12849 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0); 12850 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0); 12851 } else { 12852 u32 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; 12853 bnx2x_set_xumac_nig(params, 0, 0); 12854 if (REG_RD(bp, MISC_REG_RESET_REG_2) & 12855 MISC_REGISTERS_RESET_REG_2_XMAC) 12856 REG_WR(bp, xmac_base + XMAC_REG_CTRL, 12857 XMAC_CTRL_REG_SOFT_RESET); 12858 } 12859 vars->link_up = 0; 12860 vars->phy_flags = 0; 12861 return 0; 12862 } 12863 int bnx2x_lfa_reset(struct link_params *params, 12864 struct link_vars *vars) 12865 { 12866 struct bnx2x *bp = params->bp; 12867 vars->link_up = 0; 12868 vars->phy_flags = 0; 12869 params->link_flags &= ~PHY_INITIALIZED; 12870 if (!params->lfa_base) 12871 return bnx2x_link_reset(params, vars, 1); 12872 /* 12873 * Activate NIG drain so that during this time the device won't send 12874 * anything while it is unable to response. 12875 */ 12876 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1); 12877 12878 /* 12879 * Close gracefully the gate from BMAC to NIG such that no half packets 12880 * are passed. 12881 */ 12882 if (!CHIP_IS_E3(bp)) 12883 bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 0); 12884 12885 if (CHIP_IS_E3(bp)) { 12886 bnx2x_set_xmac_rxtx(params, 0); 12887 bnx2x_set_umac_rxtx(params, 0); 12888 } 12889 /* Wait 10ms for the pipe to clean up*/ 12890 usleep_range(10000, 20000); 12891 12892 /* Clean the NIG-BRB using the network filters in a way that will 12893 * not cut a packet in the middle. 12894 */ 12895 bnx2x_set_rx_filter(params, 0); 12896 12897 /* 12898 * Re-open the gate between the BMAC and the NIG, after verifying the 12899 * gate to the BRB is closed, otherwise packets may arrive to the 12900 * firmware before driver had initialized it. The target is to achieve 12901 * minimum management protocol down time. 12902 */ 12903 if (!CHIP_IS_E3(bp)) 12904 bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 1); 12905 12906 if (CHIP_IS_E3(bp)) { 12907 bnx2x_set_xmac_rxtx(params, 1); 12908 bnx2x_set_umac_rxtx(params, 1); 12909 } 12910 /* Disable NIG drain */ 12911 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); 12912 return 0; 12913 } 12914 12915 /****************************************************************************/ 12916 /* Common function */ 12917 /****************************************************************************/ 12918 static int bnx2x_8073_common_init_phy(struct bnx2x *bp, 12919 u32 shmem_base_path[], 12920 u32 shmem2_base_path[], u8 phy_index, 12921 u32 chip_id) 12922 { 12923 struct bnx2x_phy phy[PORT_MAX]; 12924 struct bnx2x_phy *phy_blk[PORT_MAX]; 12925 u16 val; 12926 s8 port = 0; 12927 s8 port_of_path = 0; 12928 u32 swap_val, swap_override; 12929 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); 12930 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); 12931 port ^= (swap_val && swap_override); 12932 bnx2x_ext_phy_hw_reset(bp, port); 12933 /* PART1 - Reset both phys */ 12934 for (port = PORT_MAX - 1; port >= PORT_0; port--) { 12935 u32 shmem_base, shmem2_base; 12936 /* In E2, same phy is using for port0 of the two paths */ 12937 if (CHIP_IS_E1x(bp)) { 12938 shmem_base = shmem_base_path[0]; 12939 shmem2_base = shmem2_base_path[0]; 12940 port_of_path = port; 12941 } else { 12942 shmem_base = shmem_base_path[port]; 12943 shmem2_base = shmem2_base_path[port]; 12944 port_of_path = 0; 12945 } 12946 12947 /* Extract the ext phy address for the port */ 12948 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base, 12949 port_of_path, &phy[port]) != 12950 0) { 12951 DP(NETIF_MSG_LINK, "populate_phy failed\n"); 12952 return -EINVAL; 12953 } 12954 /* Disable attentions */ 12955 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + 12956 port_of_path*4, 12957 (NIG_MASK_XGXS0_LINK_STATUS | 12958 NIG_MASK_XGXS0_LINK10G | 12959 NIG_MASK_SERDES0_LINK_STATUS | 12960 NIG_MASK_MI_INT)); 12961 12962 /* Need to take the phy out of low power mode in order 12963 * to write to access its registers 12964 */ 12965 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 12966 MISC_REGISTERS_GPIO_OUTPUT_HIGH, 12967 port); 12968 12969 /* Reset the phy */ 12970 bnx2x_cl45_write(bp, &phy[port], 12971 MDIO_PMA_DEVAD, 12972 MDIO_PMA_REG_CTRL, 12973 1<<15); 12974 } 12975 12976 /* Add delay of 150ms after reset */ 12977 msleep(150); 12978 12979 if (phy[PORT_0].addr & 0x1) { 12980 phy_blk[PORT_0] = &(phy[PORT_1]); 12981 phy_blk[PORT_1] = &(phy[PORT_0]); 12982 } else { 12983 phy_blk[PORT_0] = &(phy[PORT_0]); 12984 phy_blk[PORT_1] = &(phy[PORT_1]); 12985 } 12986 12987 /* PART2 - Download firmware to both phys */ 12988 for (port = PORT_MAX - 1; port >= PORT_0; port--) { 12989 if (CHIP_IS_E1x(bp)) 12990 port_of_path = port; 12991 else 12992 port_of_path = 0; 12993 12994 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n", 12995 phy_blk[port]->addr); 12996 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port], 12997 port_of_path)) 12998 return -EINVAL; 12999 13000 /* Only set bit 10 = 1 (Tx power down) */ 13001 bnx2x_cl45_read(bp, phy_blk[port], 13002 MDIO_PMA_DEVAD, 13003 MDIO_PMA_REG_TX_POWER_DOWN, &val); 13004 13005 /* Phase1 of TX_POWER_DOWN reset */ 13006 bnx2x_cl45_write(bp, phy_blk[port], 13007 MDIO_PMA_DEVAD, 13008 MDIO_PMA_REG_TX_POWER_DOWN, 13009 (val | 1<<10)); 13010 } 13011 13012 /* Toggle Transmitter: Power down and then up with 600ms delay 13013 * between 13014 */ 13015 msleep(600); 13016 13017 /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */ 13018 for (port = PORT_MAX - 1; port >= PORT_0; port--) { 13019 /* Phase2 of POWER_DOWN_RESET */ 13020 /* Release bit 10 (Release Tx power down) */ 13021 bnx2x_cl45_read(bp, phy_blk[port], 13022 MDIO_PMA_DEVAD, 13023 MDIO_PMA_REG_TX_POWER_DOWN, &val); 13024 13025 bnx2x_cl45_write(bp, phy_blk[port], 13026 MDIO_PMA_DEVAD, 13027 MDIO_PMA_REG_TX_POWER_DOWN, (val & (~(1<<10)))); 13028 usleep_range(15000, 30000); 13029 13030 /* Read modify write the SPI-ROM version select register */ 13031 bnx2x_cl45_read(bp, phy_blk[port], 13032 MDIO_PMA_DEVAD, 13033 MDIO_PMA_REG_EDC_FFE_MAIN, &val); 13034 bnx2x_cl45_write(bp, phy_blk[port], 13035 MDIO_PMA_DEVAD, 13036 MDIO_PMA_REG_EDC_FFE_MAIN, (val | (1<<12))); 13037 13038 /* set GPIO2 back to LOW */ 13039 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 13040 MISC_REGISTERS_GPIO_OUTPUT_LOW, port); 13041 } 13042 return 0; 13043 } 13044 static int bnx2x_8726_common_init_phy(struct bnx2x *bp, 13045 u32 shmem_base_path[], 13046 u32 shmem2_base_path[], u8 phy_index, 13047 u32 chip_id) 13048 { 13049 u32 val; 13050 s8 port; 13051 struct bnx2x_phy phy; 13052 /* Use port1 because of the static port-swap */ 13053 /* Enable the module detection interrupt */ 13054 val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN); 13055 val |= ((1<<MISC_REGISTERS_GPIO_3)| 13056 (1<<(MISC_REGISTERS_GPIO_3 + MISC_REGISTERS_GPIO_PORT_SHIFT))); 13057 REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val); 13058 13059 bnx2x_ext_phy_hw_reset(bp, 0); 13060 usleep_range(5000, 10000); 13061 for (port = 0; port < PORT_MAX; port++) { 13062 u32 shmem_base, shmem2_base; 13063 13064 /* In E2, same phy is using for port0 of the two paths */ 13065 if (CHIP_IS_E1x(bp)) { 13066 shmem_base = shmem_base_path[0]; 13067 shmem2_base = shmem2_base_path[0]; 13068 } else { 13069 shmem_base = shmem_base_path[port]; 13070 shmem2_base = shmem2_base_path[port]; 13071 } 13072 /* Extract the ext phy address for the port */ 13073 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base, 13074 port, &phy) != 13075 0) { 13076 DP(NETIF_MSG_LINK, "populate phy failed\n"); 13077 return -EINVAL; 13078 } 13079 13080 /* Reset phy*/ 13081 bnx2x_cl45_write(bp, &phy, 13082 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001); 13083 13084 13085 /* Set fault module detected LED on */ 13086 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0, 13087 MISC_REGISTERS_GPIO_HIGH, 13088 port); 13089 } 13090 13091 return 0; 13092 } 13093 static void bnx2x_get_ext_phy_reset_gpio(struct bnx2x *bp, u32 shmem_base, 13094 u8 *io_gpio, u8 *io_port) 13095 { 13096 13097 u32 phy_gpio_reset = REG_RD(bp, shmem_base + 13098 offsetof(struct shmem_region, 13099 dev_info.port_hw_config[PORT_0].default_cfg)); 13100 switch (phy_gpio_reset) { 13101 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0: 13102 *io_gpio = 0; 13103 *io_port = 0; 13104 break; 13105 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0: 13106 *io_gpio = 1; 13107 *io_port = 0; 13108 break; 13109 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0: 13110 *io_gpio = 2; 13111 *io_port = 0; 13112 break; 13113 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0: 13114 *io_gpio = 3; 13115 *io_port = 0; 13116 break; 13117 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1: 13118 *io_gpio = 0; 13119 *io_port = 1; 13120 break; 13121 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1: 13122 *io_gpio = 1; 13123 *io_port = 1; 13124 break; 13125 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1: 13126 *io_gpio = 2; 13127 *io_port = 1; 13128 break; 13129 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1: 13130 *io_gpio = 3; 13131 *io_port = 1; 13132 break; 13133 default: 13134 /* Don't override the io_gpio and io_port */ 13135 break; 13136 } 13137 } 13138 13139 static int bnx2x_8727_common_init_phy(struct bnx2x *bp, 13140 u32 shmem_base_path[], 13141 u32 shmem2_base_path[], u8 phy_index, 13142 u32 chip_id) 13143 { 13144 s8 port, reset_gpio; 13145 u32 swap_val, swap_override; 13146 struct bnx2x_phy phy[PORT_MAX]; 13147 struct bnx2x_phy *phy_blk[PORT_MAX]; 13148 s8 port_of_path; 13149 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); 13150 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); 13151 13152 reset_gpio = MISC_REGISTERS_GPIO_1; 13153 port = 1; 13154 13155 /* Retrieve the reset gpio/port which control the reset. 13156 * Default is GPIO1, PORT1 13157 */ 13158 bnx2x_get_ext_phy_reset_gpio(bp, shmem_base_path[0], 13159 (u8 *)&reset_gpio, (u8 *)&port); 13160 13161 /* Calculate the port based on port swap */ 13162 port ^= (swap_val && swap_override); 13163 13164 /* Initiate PHY reset*/ 13165 bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_LOW, 13166 port); 13167 usleep_range(1000, 2000); 13168 bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_HIGH, 13169 port); 13170 13171 usleep_range(5000, 10000); 13172 13173 /* PART1 - Reset both phys */ 13174 for (port = PORT_MAX - 1; port >= PORT_0; port--) { 13175 u32 shmem_base, shmem2_base; 13176 13177 /* In E2, same phy is using for port0 of the two paths */ 13178 if (CHIP_IS_E1x(bp)) { 13179 shmem_base = shmem_base_path[0]; 13180 shmem2_base = shmem2_base_path[0]; 13181 port_of_path = port; 13182 } else { 13183 shmem_base = shmem_base_path[port]; 13184 shmem2_base = shmem2_base_path[port]; 13185 port_of_path = 0; 13186 } 13187 13188 /* Extract the ext phy address for the port */ 13189 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base, 13190 port_of_path, &phy[port]) != 13191 0) { 13192 DP(NETIF_MSG_LINK, "populate phy failed\n"); 13193 return -EINVAL; 13194 } 13195 /* disable attentions */ 13196 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + 13197 port_of_path*4, 13198 (NIG_MASK_XGXS0_LINK_STATUS | 13199 NIG_MASK_XGXS0_LINK10G | 13200 NIG_MASK_SERDES0_LINK_STATUS | 13201 NIG_MASK_MI_INT)); 13202 13203 13204 /* Reset the phy */ 13205 bnx2x_cl45_write(bp, &phy[port], 13206 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15); 13207 } 13208 13209 /* Add delay of 150ms after reset */ 13210 msleep(150); 13211 if (phy[PORT_0].addr & 0x1) { 13212 phy_blk[PORT_0] = &(phy[PORT_1]); 13213 phy_blk[PORT_1] = &(phy[PORT_0]); 13214 } else { 13215 phy_blk[PORT_0] = &(phy[PORT_0]); 13216 phy_blk[PORT_1] = &(phy[PORT_1]); 13217 } 13218 /* PART2 - Download firmware to both phys */ 13219 for (port = PORT_MAX - 1; port >= PORT_0; port--) { 13220 if (CHIP_IS_E1x(bp)) 13221 port_of_path = port; 13222 else 13223 port_of_path = 0; 13224 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n", 13225 phy_blk[port]->addr); 13226 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port], 13227 port_of_path)) 13228 return -EINVAL; 13229 /* Disable PHY transmitter output */ 13230 bnx2x_cl45_write(bp, phy_blk[port], 13231 MDIO_PMA_DEVAD, 13232 MDIO_PMA_REG_TX_DISABLE, 1); 13233 13234 } 13235 return 0; 13236 } 13237 13238 static int bnx2x_84833_common_init_phy(struct bnx2x *bp, 13239 u32 shmem_base_path[], 13240 u32 shmem2_base_path[], 13241 u8 phy_index, 13242 u32 chip_id) 13243 { 13244 u8 reset_gpios; 13245 reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path, chip_id); 13246 bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW); 13247 udelay(10); 13248 bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_HIGH); 13249 DP(NETIF_MSG_LINK, "84833 reset pulse on pin values 0x%x\n", 13250 reset_gpios); 13251 return 0; 13252 } 13253 13254 static int bnx2x_ext_phy_common_init(struct bnx2x *bp, u32 shmem_base_path[], 13255 u32 shmem2_base_path[], u8 phy_index, 13256 u32 ext_phy_type, u32 chip_id) 13257 { 13258 int rc = 0; 13259 13260 switch (ext_phy_type) { 13261 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073: 13262 rc = bnx2x_8073_common_init_phy(bp, shmem_base_path, 13263 shmem2_base_path, 13264 phy_index, chip_id); 13265 break; 13266 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722: 13267 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: 13268 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC: 13269 rc = bnx2x_8727_common_init_phy(bp, shmem_base_path, 13270 shmem2_base_path, 13271 phy_index, chip_id); 13272 break; 13273 13274 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: 13275 /* GPIO1 affects both ports, so there's need to pull 13276 * it for single port alone 13277 */ 13278 rc = bnx2x_8726_common_init_phy(bp, shmem_base_path, 13279 shmem2_base_path, 13280 phy_index, chip_id); 13281 break; 13282 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833: 13283 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834: 13284 /* GPIO3's are linked, and so both need to be toggled 13285 * to obtain required 2us pulse. 13286 */ 13287 rc = bnx2x_84833_common_init_phy(bp, shmem_base_path, 13288 shmem2_base_path, 13289 phy_index, chip_id); 13290 break; 13291 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE: 13292 rc = -EINVAL; 13293 break; 13294 default: 13295 DP(NETIF_MSG_LINK, 13296 "ext_phy 0x%x common init not required\n", 13297 ext_phy_type); 13298 break; 13299 } 13300 13301 if (rc) 13302 netdev_err(bp->dev, "Warning: PHY was not initialized," 13303 " Port %d\n", 13304 0); 13305 return rc; 13306 } 13307 13308 int bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base_path[], 13309 u32 shmem2_base_path[], u32 chip_id) 13310 { 13311 int rc = 0; 13312 u32 phy_ver, val; 13313 u8 phy_index = 0; 13314 u32 ext_phy_type, ext_phy_config; 13315 13316 bnx2x_set_mdio_clk(bp, chip_id, GRCBASE_EMAC0); 13317 bnx2x_set_mdio_clk(bp, chip_id, GRCBASE_EMAC1); 13318 DP(NETIF_MSG_LINK, "Begin common phy init\n"); 13319 if (CHIP_IS_E3(bp)) { 13320 /* Enable EPIO */ 13321 val = REG_RD(bp, MISC_REG_GEN_PURP_HWG); 13322 REG_WR(bp, MISC_REG_GEN_PURP_HWG, val | 1); 13323 } 13324 /* Check if common init was already done */ 13325 phy_ver = REG_RD(bp, shmem_base_path[0] + 13326 offsetof(struct shmem_region, 13327 port_mb[PORT_0].ext_phy_fw_version)); 13328 if (phy_ver) { 13329 DP(NETIF_MSG_LINK, "Not doing common init; phy ver is 0x%x\n", 13330 phy_ver); 13331 return 0; 13332 } 13333 13334 /* Read the ext_phy_type for arbitrary port(0) */ 13335 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS; 13336 phy_index++) { 13337 ext_phy_config = bnx2x_get_ext_phy_config(bp, 13338 shmem_base_path[0], 13339 phy_index, 0); 13340 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config); 13341 rc |= bnx2x_ext_phy_common_init(bp, shmem_base_path, 13342 shmem2_base_path, 13343 phy_index, ext_phy_type, 13344 chip_id); 13345 } 13346 return rc; 13347 } 13348 13349 static void bnx2x_check_over_curr(struct link_params *params, 13350 struct link_vars *vars) 13351 { 13352 struct bnx2x *bp = params->bp; 13353 u32 cfg_pin; 13354 u8 port = params->port; 13355 u32 pin_val; 13356 13357 cfg_pin = (REG_RD(bp, params->shmem_base + 13358 offsetof(struct shmem_region, 13359 dev_info.port_hw_config[port].e3_cmn_pin_cfg1)) & 13360 PORT_HW_CFG_E3_OVER_CURRENT_MASK) >> 13361 PORT_HW_CFG_E3_OVER_CURRENT_SHIFT; 13362 13363 /* Ignore check if no external input PIN available */ 13364 if (bnx2x_get_cfg_pin(bp, cfg_pin, &pin_val) != 0) 13365 return; 13366 13367 if (!pin_val) { 13368 if ((vars->phy_flags & PHY_OVER_CURRENT_FLAG) == 0) { 13369 netdev_err(bp->dev, "Error: Power fault on Port %d has" 13370 " been detected and the power to " 13371 "that SFP+ module has been removed" 13372 " to prevent failure of the card." 13373 " Please remove the SFP+ module and" 13374 " restart the system to clear this" 13375 " error.\n", 13376 params->port); 13377 vars->phy_flags |= PHY_OVER_CURRENT_FLAG; 13378 bnx2x_warpcore_power_module(params, 0); 13379 } 13380 } else 13381 vars->phy_flags &= ~PHY_OVER_CURRENT_FLAG; 13382 } 13383 13384 /* Returns 0 if no change occurred since last check; 1 otherwise. */ 13385 static u8 bnx2x_analyze_link_error(struct link_params *params, 13386 struct link_vars *vars, u32 status, 13387 u32 phy_flag, u32 link_flag, u8 notify) 13388 { 13389 struct bnx2x *bp = params->bp; 13390 /* Compare new value with previous value */ 13391 u8 led_mode; 13392 u32 old_status = (vars->phy_flags & phy_flag) ? 1 : 0; 13393 13394 if ((status ^ old_status) == 0) 13395 return 0; 13396 13397 /* If values differ */ 13398 switch (phy_flag) { 13399 case PHY_HALF_OPEN_CONN_FLAG: 13400 DP(NETIF_MSG_LINK, "Analyze Remote Fault\n"); 13401 break; 13402 case PHY_SFP_TX_FAULT_FLAG: 13403 DP(NETIF_MSG_LINK, "Analyze TX Fault\n"); 13404 break; 13405 default: 13406 DP(NETIF_MSG_LINK, "Analyze UNKNOWN\n"); 13407 } 13408 DP(NETIF_MSG_LINK, "Link changed:[%x %x]->%x\n", vars->link_up, 13409 old_status, status); 13410 13411 /* Do not touch the link in case physical link down */ 13412 if ((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0) 13413 return 1; 13414 13415 /* a. Update shmem->link_status accordingly 13416 * b. Update link_vars->link_up 13417 */ 13418 if (status) { 13419 vars->link_status &= ~LINK_STATUS_LINK_UP; 13420 vars->link_status |= link_flag; 13421 vars->link_up = 0; 13422 vars->phy_flags |= phy_flag; 13423 13424 /* activate nig drain */ 13425 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1); 13426 /* Set LED mode to off since the PHY doesn't know about these 13427 * errors 13428 */ 13429 led_mode = LED_MODE_OFF; 13430 } else { 13431 vars->link_status |= LINK_STATUS_LINK_UP; 13432 vars->link_status &= ~link_flag; 13433 vars->link_up = 1; 13434 vars->phy_flags &= ~phy_flag; 13435 led_mode = LED_MODE_OPER; 13436 13437 /* Clear nig drain */ 13438 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); 13439 } 13440 bnx2x_sync_link(params, vars); 13441 /* Update the LED according to the link state */ 13442 bnx2x_set_led(params, vars, led_mode, SPEED_10000); 13443 13444 /* Update link status in the shared memory */ 13445 bnx2x_update_mng(params, vars->link_status); 13446 13447 /* C. Trigger General Attention */ 13448 vars->periodic_flags |= PERIODIC_FLAGS_LINK_EVENT; 13449 if (notify) 13450 bnx2x_notify_link_changed(bp); 13451 13452 return 1; 13453 } 13454 13455 /****************************************************************************** 13456 * Description: 13457 * This function checks for half opened connection change indication. 13458 * When such change occurs, it calls the bnx2x_analyze_link_error 13459 * to check if Remote Fault is set or cleared. Reception of remote fault 13460 * status message in the MAC indicates that the peer's MAC has detected 13461 * a fault, for example, due to break in the TX side of fiber. 13462 * 13463 ******************************************************************************/ 13464 static int bnx2x_check_half_open_conn(struct link_params *params, 13465 struct link_vars *vars, 13466 u8 notify) 13467 { 13468 struct bnx2x *bp = params->bp; 13469 u32 lss_status = 0; 13470 u32 mac_base; 13471 /* In case link status is physically up @ 10G do */ 13472 if (((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0) || 13473 (REG_RD(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4))) 13474 return 0; 13475 13476 if (CHIP_IS_E3(bp) && 13477 (REG_RD(bp, MISC_REG_RESET_REG_2) & 13478 (MISC_REGISTERS_RESET_REG_2_XMAC))) { 13479 /* Check E3 XMAC */ 13480 /* Note that link speed cannot be queried here, since it may be 13481 * zero while link is down. In case UMAC is active, LSS will 13482 * simply not be set 13483 */ 13484 mac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; 13485 13486 /* Clear stick bits (Requires rising edge) */ 13487 REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0); 13488 REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 13489 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS | 13490 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS); 13491 if (REG_RD(bp, mac_base + XMAC_REG_RX_LSS_STATUS)) 13492 lss_status = 1; 13493 13494 bnx2x_analyze_link_error(params, vars, lss_status, 13495 PHY_HALF_OPEN_CONN_FLAG, 13496 LINK_STATUS_NONE, notify); 13497 } else if (REG_RD(bp, MISC_REG_RESET_REG_2) & 13498 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port)) { 13499 /* Check E1X / E2 BMAC */ 13500 u32 lss_status_reg; 13501 u32 wb_data[2]; 13502 mac_base = params->port ? NIG_REG_INGRESS_BMAC1_MEM : 13503 NIG_REG_INGRESS_BMAC0_MEM; 13504 /* Read BIGMAC_REGISTER_RX_LSS_STATUS */ 13505 if (CHIP_IS_E2(bp)) 13506 lss_status_reg = BIGMAC2_REGISTER_RX_LSS_STAT; 13507 else 13508 lss_status_reg = BIGMAC_REGISTER_RX_LSS_STATUS; 13509 13510 REG_RD_DMAE(bp, mac_base + lss_status_reg, wb_data, 2); 13511 lss_status = (wb_data[0] > 0); 13512 13513 bnx2x_analyze_link_error(params, vars, lss_status, 13514 PHY_HALF_OPEN_CONN_FLAG, 13515 LINK_STATUS_NONE, notify); 13516 } 13517 return 0; 13518 } 13519 static void bnx2x_sfp_tx_fault_detection(struct bnx2x_phy *phy, 13520 struct link_params *params, 13521 struct link_vars *vars) 13522 { 13523 struct bnx2x *bp = params->bp; 13524 u32 cfg_pin, value = 0; 13525 u8 led_change, port = params->port; 13526 13527 /* Get The SFP+ TX_Fault controlling pin ([eg]pio) */ 13528 cfg_pin = (REG_RD(bp, params->shmem_base + offsetof(struct shmem_region, 13529 dev_info.port_hw_config[port].e3_cmn_pin_cfg)) & 13530 PORT_HW_CFG_E3_TX_FAULT_MASK) >> 13531 PORT_HW_CFG_E3_TX_FAULT_SHIFT; 13532 13533 if (bnx2x_get_cfg_pin(bp, cfg_pin, &value)) { 13534 DP(NETIF_MSG_LINK, "Failed to read pin 0x%02x\n", cfg_pin); 13535 return; 13536 } 13537 13538 led_change = bnx2x_analyze_link_error(params, vars, value, 13539 PHY_SFP_TX_FAULT_FLAG, 13540 LINK_STATUS_SFP_TX_FAULT, 1); 13541 13542 if (led_change) { 13543 /* Change TX_Fault led, set link status for further syncs */ 13544 u8 led_mode; 13545 13546 if (vars->phy_flags & PHY_SFP_TX_FAULT_FLAG) { 13547 led_mode = MISC_REGISTERS_GPIO_HIGH; 13548 vars->link_status |= LINK_STATUS_SFP_TX_FAULT; 13549 } else { 13550 led_mode = MISC_REGISTERS_GPIO_LOW; 13551 vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT; 13552 } 13553 13554 /* If module is unapproved, led should be on regardless */ 13555 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED)) { 13556 DP(NETIF_MSG_LINK, "Change TX_Fault LED: ->%x\n", 13557 led_mode); 13558 bnx2x_set_e3_module_fault_led(params, led_mode); 13559 } 13560 } 13561 } 13562 static void bnx2x_kr2_recovery(struct link_params *params, 13563 struct link_vars *vars, 13564 struct bnx2x_phy *phy) 13565 { 13566 struct bnx2x *bp = params->bp; 13567 DP(NETIF_MSG_LINK, "KR2 recovery\n"); 13568 bnx2x_warpcore_enable_AN_KR2(phy, params, vars); 13569 bnx2x_warpcore_restart_AN_KR(phy, params); 13570 } 13571 13572 static void bnx2x_check_kr2_wa(struct link_params *params, 13573 struct link_vars *vars, 13574 struct bnx2x_phy *phy) 13575 { 13576 struct bnx2x *bp = params->bp; 13577 u16 base_page, next_page, not_kr2_device, lane; 13578 int sigdet; 13579 13580 /* Once KR2 was disabled, wait 5 seconds before checking KR2 recovery 13581 * Since some switches tend to reinit the AN process and clear the 13582 * the advertised BP/NP after ~2 seconds causing the KR2 to be disabled 13583 * and recovered many times 13584 */ 13585 if (vars->check_kr2_recovery_cnt > 0) { 13586 vars->check_kr2_recovery_cnt--; 13587 return; 13588 } 13589 13590 sigdet = bnx2x_warpcore_get_sigdet(phy, params); 13591 if (!sigdet) { 13592 if (!(params->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) { 13593 bnx2x_kr2_recovery(params, vars, phy); 13594 DP(NETIF_MSG_LINK, "No sigdet\n"); 13595 } 13596 return; 13597 } 13598 13599 lane = bnx2x_get_warpcore_lane(phy, params); 13600 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, 13601 MDIO_AER_BLOCK_AER_REG, lane); 13602 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, 13603 MDIO_AN_REG_LP_AUTO_NEG, &base_page); 13604 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, 13605 MDIO_AN_REG_LP_AUTO_NEG2, &next_page); 13606 bnx2x_set_aer_mmd(params, phy); 13607 13608 /* CL73 has not begun yet */ 13609 if (base_page == 0) { 13610 if (!(params->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) { 13611 bnx2x_kr2_recovery(params, vars, phy); 13612 DP(NETIF_MSG_LINK, "No BP\n"); 13613 } 13614 return; 13615 } 13616 13617 /* In case NP bit is not set in the BasePage, or it is set, 13618 * but only KX is advertised, declare this link partner as non-KR2 13619 * device. 13620 */ 13621 not_kr2_device = (((base_page & 0x8000) == 0) || 13622 (((base_page & 0x8000) && 13623 ((next_page & 0xe0) == 0x20)))); 13624 13625 /* In case KR2 is already disabled, check if we need to re-enable it */ 13626 if (!(params->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) { 13627 if (!not_kr2_device) { 13628 DP(NETIF_MSG_LINK, "BP=0x%x, NP=0x%x\n", base_page, 13629 next_page); 13630 bnx2x_kr2_recovery(params, vars, phy); 13631 } 13632 return; 13633 } 13634 /* KR2 is enabled, but not KR2 device */ 13635 if (not_kr2_device) { 13636 /* Disable KR2 on both lanes */ 13637 DP(NETIF_MSG_LINK, "BP=0x%x, NP=0x%x\n", base_page, next_page); 13638 bnx2x_disable_kr2(params, vars, phy); 13639 /* Restart AN on leading lane */ 13640 bnx2x_warpcore_restart_AN_KR(phy, params); 13641 return; 13642 } 13643 } 13644 13645 void bnx2x_period_func(struct link_params *params, struct link_vars *vars) 13646 { 13647 u16 phy_idx; 13648 struct bnx2x *bp = params->bp; 13649 for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) { 13650 if (params->phy[phy_idx].flags & FLAGS_TX_ERROR_CHECK) { 13651 bnx2x_set_aer_mmd(params, ¶ms->phy[phy_idx]); 13652 if (bnx2x_check_half_open_conn(params, vars, 1) != 13653 0) 13654 DP(NETIF_MSG_LINK, "Fault detection failed\n"); 13655 break; 13656 } 13657 } 13658 13659 if (CHIP_IS_E3(bp)) { 13660 struct bnx2x_phy *phy = ¶ms->phy[INT_PHY]; 13661 bnx2x_set_aer_mmd(params, phy); 13662 if ((phy->supported & SUPPORTED_20000baseKR2_Full) && 13663 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) 13664 bnx2x_check_kr2_wa(params, vars, phy); 13665 bnx2x_check_over_curr(params, vars); 13666 if (vars->rx_tx_asic_rst) 13667 bnx2x_warpcore_config_runtime(phy, params, vars); 13668 13669 if ((REG_RD(bp, params->shmem_base + 13670 offsetof(struct shmem_region, dev_info. 13671 port_hw_config[params->port].default_cfg)) 13672 & PORT_HW_CFG_NET_SERDES_IF_MASK) == 13673 PORT_HW_CFG_NET_SERDES_IF_SFI) { 13674 if (bnx2x_is_sfp_module_plugged(phy, params)) { 13675 bnx2x_sfp_tx_fault_detection(phy, params, vars); 13676 } else if (vars->link_status & 13677 LINK_STATUS_SFP_TX_FAULT) { 13678 /* Clean trail, interrupt corrects the leds */ 13679 vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT; 13680 vars->phy_flags &= ~PHY_SFP_TX_FAULT_FLAG; 13681 /* Update link status in the shared memory */ 13682 bnx2x_update_mng(params, vars->link_status); 13683 } 13684 } 13685 } 13686 } 13687 13688 u8 bnx2x_fan_failure_det_req(struct bnx2x *bp, 13689 u32 shmem_base, 13690 u32 shmem2_base, 13691 u8 port) 13692 { 13693 u8 phy_index, fan_failure_det_req = 0; 13694 struct bnx2x_phy phy; 13695 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS; 13696 phy_index++) { 13697 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base, 13698 port, &phy) 13699 != 0) { 13700 DP(NETIF_MSG_LINK, "populate phy failed\n"); 13701 return 0; 13702 } 13703 fan_failure_det_req |= (phy.flags & 13704 FLAGS_FAN_FAILURE_DET_REQ); 13705 } 13706 return fan_failure_det_req; 13707 } 13708 13709 void bnx2x_hw_reset_phy(struct link_params *params) 13710 { 13711 u8 phy_index; 13712 struct bnx2x *bp = params->bp; 13713 bnx2x_update_mng(params, 0); 13714 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4, 13715 (NIG_MASK_XGXS0_LINK_STATUS | 13716 NIG_MASK_XGXS0_LINK10G | 13717 NIG_MASK_SERDES0_LINK_STATUS | 13718 NIG_MASK_MI_INT)); 13719 13720 for (phy_index = INT_PHY; phy_index < MAX_PHYS; 13721 phy_index++) { 13722 if (params->phy[phy_index].hw_reset) { 13723 params->phy[phy_index].hw_reset( 13724 ¶ms->phy[phy_index], 13725 params); 13726 params->phy[phy_index] = phy_null; 13727 } 13728 } 13729 } 13730 13731 void bnx2x_init_mod_abs_int(struct bnx2x *bp, struct link_vars *vars, 13732 u32 chip_id, u32 shmem_base, u32 shmem2_base, 13733 u8 port) 13734 { 13735 u8 gpio_num = 0xff, gpio_port = 0xff, phy_index; 13736 u32 val; 13737 u32 offset, aeu_mask, swap_val, swap_override, sync_offset; 13738 if (CHIP_IS_E3(bp)) { 13739 if (bnx2x_get_mod_abs_int_cfg(bp, chip_id, 13740 shmem_base, 13741 port, 13742 &gpio_num, 13743 &gpio_port) != 0) 13744 return; 13745 } else { 13746 struct bnx2x_phy phy; 13747 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS; 13748 phy_index++) { 13749 if (bnx2x_populate_phy(bp, phy_index, shmem_base, 13750 shmem2_base, port, &phy) 13751 != 0) { 13752 DP(NETIF_MSG_LINK, "populate phy failed\n"); 13753 return; 13754 } 13755 if (phy.type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) { 13756 gpio_num = MISC_REGISTERS_GPIO_3; 13757 gpio_port = port; 13758 break; 13759 } 13760 } 13761 } 13762 13763 if (gpio_num == 0xff) 13764 return; 13765 13766 /* Set GPIO3 to trigger SFP+ module insertion/removal */ 13767 bnx2x_set_gpio(bp, gpio_num, MISC_REGISTERS_GPIO_INPUT_HI_Z, gpio_port); 13768 13769 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); 13770 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); 13771 gpio_port ^= (swap_val && swap_override); 13772 13773 vars->aeu_int_mask = AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 << 13774 (gpio_num + (gpio_port << 2)); 13775 13776 sync_offset = shmem_base + 13777 offsetof(struct shmem_region, 13778 dev_info.port_hw_config[port].aeu_int_mask); 13779 REG_WR(bp, sync_offset, vars->aeu_int_mask); 13780 13781 DP(NETIF_MSG_LINK, "Setting MOD_ABS (GPIO%d_P%d) AEU to 0x%x\n", 13782 gpio_num, gpio_port, vars->aeu_int_mask); 13783 13784 if (port == 0) 13785 offset = MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0; 13786 else 13787 offset = MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0; 13788 13789 /* Open appropriate AEU for interrupts */ 13790 aeu_mask = REG_RD(bp, offset); 13791 aeu_mask |= vars->aeu_int_mask; 13792 REG_WR(bp, offset, aeu_mask); 13793 13794 /* Enable the GPIO to trigger interrupt */ 13795 val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN); 13796 val |= 1 << (gpio_num + (gpio_port << 2)); 13797 REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val); 13798 } 13799