1 /* Copyright 2008-2013 Broadcom Corporation 2 * 3 * Unless you and Broadcom execute a separate written software license 4 * agreement governing use of this software, this software is licensed to you 5 * under the terms of the GNU General Public License version 2, available 6 * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL"). 7 * 8 * Notwithstanding the above, under no circumstances may you combine this 9 * software in any way with any other Broadcom software provided under a 10 * license other than the GPL, without Broadcom's express prior written 11 * consent. 12 * 13 * Written by Yaniv Rosner 14 * 15 */ 16 17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 18 19 #include <linux/kernel.h> 20 #include <linux/errno.h> 21 #include <linux/pci.h> 22 #include <linux/netdevice.h> 23 #include <linux/delay.h> 24 #include <linux/ethtool.h> 25 #include <linux/mutex.h> 26 27 #include "bnx2x.h" 28 #include "bnx2x_cmn.h" 29 30 typedef int (*read_sfp_module_eeprom_func_p)(struct bnx2x_phy *phy, 31 struct link_params *params, 32 u8 dev_addr, u16 addr, u8 byte_cnt, 33 u8 *o_buf, u8); 34 /********************************************************/ 35 #define ETH_HLEN 14 36 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */ 37 #define ETH_OVREHEAD (ETH_HLEN + 8 + 8) 38 #define ETH_MIN_PACKET_SIZE 60 39 #define ETH_MAX_PACKET_SIZE 1500 40 #define ETH_MAX_JUMBO_PACKET_SIZE 9600 41 #define MDIO_ACCESS_TIMEOUT 1000 42 #define WC_LANE_MAX 4 43 #define I2C_SWITCH_WIDTH 2 44 #define I2C_BSC0 0 45 #define I2C_BSC1 1 46 #define I2C_WA_RETRY_CNT 3 47 #define I2C_WA_PWR_ITER (I2C_WA_RETRY_CNT - 1) 48 #define MCPR_IMC_COMMAND_READ_OP 1 49 #define MCPR_IMC_COMMAND_WRITE_OP 2 50 51 /* LED Blink rate that will achieve ~15.9Hz */ 52 #define LED_BLINK_RATE_VAL_E3 354 53 #define LED_BLINK_RATE_VAL_E1X_E2 480 54 /***********************************************************/ 55 /* Shortcut definitions */ 56 /***********************************************************/ 57 58 #define NIG_LATCH_BC_ENABLE_MI_INT 0 59 60 #define NIG_STATUS_EMAC0_MI_INT \ 61 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT 62 #define NIG_STATUS_XGXS0_LINK10G \ 63 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G 64 #define NIG_STATUS_XGXS0_LINK_STATUS \ 65 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS 66 #define NIG_STATUS_XGXS0_LINK_STATUS_SIZE \ 67 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE 68 #define NIG_STATUS_SERDES0_LINK_STATUS \ 69 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS 70 #define NIG_MASK_MI_INT \ 71 NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT 72 #define NIG_MASK_XGXS0_LINK10G \ 73 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G 74 #define NIG_MASK_XGXS0_LINK_STATUS \ 75 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS 76 #define NIG_MASK_SERDES0_LINK_STATUS \ 77 NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS 78 79 #define MDIO_AN_CL73_OR_37_COMPLETE \ 80 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \ 81 MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE) 82 83 #define XGXS_RESET_BITS \ 84 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW | \ 85 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ | \ 86 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN | \ 87 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \ 88 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB) 89 90 #define SERDES_RESET_BITS \ 91 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \ 92 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ | \ 93 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN | \ 94 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD) 95 96 #define AUTONEG_CL37 SHARED_HW_CFG_AN_ENABLE_CL37 97 #define AUTONEG_CL73 SHARED_HW_CFG_AN_ENABLE_CL73 98 #define AUTONEG_BAM SHARED_HW_CFG_AN_ENABLE_BAM 99 #define AUTONEG_PARALLEL \ 100 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION 101 #define AUTONEG_SGMII_FIBER_AUTODET \ 102 SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT 103 #define AUTONEG_REMOTE_PHY SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY 104 105 #define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \ 106 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE 107 #define GP_STATUS_PAUSE_RSOLUTION_RXSIDE \ 108 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE 109 #define GP_STATUS_SPEED_MASK \ 110 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK 111 #define GP_STATUS_10M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M 112 #define GP_STATUS_100M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M 113 #define GP_STATUS_1G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G 114 #define GP_STATUS_2_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G 115 #define GP_STATUS_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G 116 #define GP_STATUS_6G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G 117 #define GP_STATUS_10G_HIG \ 118 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG 119 #define GP_STATUS_10G_CX4 \ 120 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4 121 #define GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX 122 #define GP_STATUS_10G_KX4 \ 123 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4 124 #define GP_STATUS_10G_KR MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR 125 #define GP_STATUS_10G_XFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI 126 #define GP_STATUS_20G_DXGXS MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS 127 #define GP_STATUS_10G_SFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI 128 #define GP_STATUS_20G_KR2 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_KR2 129 #define LINK_10THD LINK_STATUS_SPEED_AND_DUPLEX_10THD 130 #define LINK_10TFD LINK_STATUS_SPEED_AND_DUPLEX_10TFD 131 #define LINK_100TXHD LINK_STATUS_SPEED_AND_DUPLEX_100TXHD 132 #define LINK_100T4 LINK_STATUS_SPEED_AND_DUPLEX_100T4 133 #define LINK_100TXFD LINK_STATUS_SPEED_AND_DUPLEX_100TXFD 134 #define LINK_1000THD LINK_STATUS_SPEED_AND_DUPLEX_1000THD 135 #define LINK_1000TFD LINK_STATUS_SPEED_AND_DUPLEX_1000TFD 136 #define LINK_1000XFD LINK_STATUS_SPEED_AND_DUPLEX_1000XFD 137 #define LINK_2500THD LINK_STATUS_SPEED_AND_DUPLEX_2500THD 138 #define LINK_2500TFD LINK_STATUS_SPEED_AND_DUPLEX_2500TFD 139 #define LINK_2500XFD LINK_STATUS_SPEED_AND_DUPLEX_2500XFD 140 #define LINK_10GTFD LINK_STATUS_SPEED_AND_DUPLEX_10GTFD 141 #define LINK_10GXFD LINK_STATUS_SPEED_AND_DUPLEX_10GXFD 142 #define LINK_20GTFD LINK_STATUS_SPEED_AND_DUPLEX_20GTFD 143 #define LINK_20GXFD LINK_STATUS_SPEED_AND_DUPLEX_20GXFD 144 145 #define LINK_UPDATE_MASK \ 146 (LINK_STATUS_SPEED_AND_DUPLEX_MASK | \ 147 LINK_STATUS_LINK_UP | \ 148 LINK_STATUS_PHYSICAL_LINK_FLAG | \ 149 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE | \ 150 LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK | \ 151 LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK | \ 152 LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK | \ 153 LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE | \ 154 LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE) 155 156 #define SFP_EEPROM_CON_TYPE_ADDR 0x2 157 #define SFP_EEPROM_CON_TYPE_VAL_UNKNOWN 0x0 158 #define SFP_EEPROM_CON_TYPE_VAL_LC 0x7 159 #define SFP_EEPROM_CON_TYPE_VAL_COPPER 0x21 160 #define SFP_EEPROM_CON_TYPE_VAL_RJ45 0x22 161 162 163 #define SFP_EEPROM_10G_COMP_CODE_ADDR 0x3 164 #define SFP_EEPROM_10G_COMP_CODE_SR_MASK (1<<4) 165 #define SFP_EEPROM_10G_COMP_CODE_LR_MASK (1<<5) 166 #define SFP_EEPROM_10G_COMP_CODE_LRM_MASK (1<<6) 167 168 #define SFP_EEPROM_1G_COMP_CODE_ADDR 0x6 169 #define SFP_EEPROM_1G_COMP_CODE_SX (1<<0) 170 #define SFP_EEPROM_1G_COMP_CODE_LX (1<<1) 171 #define SFP_EEPROM_1G_COMP_CODE_CX (1<<2) 172 #define SFP_EEPROM_1G_COMP_CODE_BASE_T (1<<3) 173 174 #define SFP_EEPROM_FC_TX_TECH_ADDR 0x8 175 #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4 176 #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE 0x8 177 178 #define SFP_EEPROM_OPTIONS_ADDR 0x40 179 #define SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1 180 #define SFP_EEPROM_OPTIONS_SIZE 2 181 182 #define EDC_MODE_LINEAR 0x0022 183 #define EDC_MODE_LIMITING 0x0044 184 #define EDC_MODE_PASSIVE_DAC 0x0055 185 #define EDC_MODE_ACTIVE_DAC 0x0066 186 187 /* ETS defines*/ 188 #define DCBX_INVALID_COS (0xFF) 189 190 #define ETS_BW_LIMIT_CREDIT_UPPER_BOUND (0x5000) 191 #define ETS_BW_LIMIT_CREDIT_WEIGHT (0x5000) 192 #define ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS (1360) 193 #define ETS_E3B0_NIG_MIN_W_VAL_20GBPS (2720) 194 #define ETS_E3B0_PBF_MIN_W_VAL (10000) 195 196 #define MAX_PACKET_SIZE (9700) 197 #define MAX_KR_LINK_RETRY 4 198 199 /**********************************************************/ 200 /* INTERFACE */ 201 /**********************************************************/ 202 203 #define CL22_WR_OVER_CL45(_bp, _phy, _bank, _addr, _val) \ 204 bnx2x_cl45_write(_bp, _phy, \ 205 (_phy)->def_md_devad, \ 206 (_bank + (_addr & 0xf)), \ 207 _val) 208 209 #define CL22_RD_OVER_CL45(_bp, _phy, _bank, _addr, _val) \ 210 bnx2x_cl45_read(_bp, _phy, \ 211 (_phy)->def_md_devad, \ 212 (_bank + (_addr & 0xf)), \ 213 _val) 214 215 static int bnx2x_check_half_open_conn(struct link_params *params, 216 struct link_vars *vars, u8 notify); 217 static int bnx2x_sfp_module_detection(struct bnx2x_phy *phy, 218 struct link_params *params); 219 220 static u32 bnx2x_bits_en(struct bnx2x *bp, u32 reg, u32 bits) 221 { 222 u32 val = REG_RD(bp, reg); 223 224 val |= bits; 225 REG_WR(bp, reg, val); 226 return val; 227 } 228 229 static u32 bnx2x_bits_dis(struct bnx2x *bp, u32 reg, u32 bits) 230 { 231 u32 val = REG_RD(bp, reg); 232 233 val &= ~bits; 234 REG_WR(bp, reg, val); 235 return val; 236 } 237 238 /* 239 * bnx2x_check_lfa - This function checks if link reinitialization is required, 240 * or link flap can be avoided. 241 * 242 * @params: link parameters 243 * Returns 0 if Link Flap Avoidance conditions are met otherwise, the failed 244 * condition code. 245 */ 246 static int bnx2x_check_lfa(struct link_params *params) 247 { 248 u32 link_status, cfg_idx, lfa_mask, cfg_size; 249 u32 cur_speed_cap_mask, cur_req_fc_auto_adv, additional_config; 250 u32 saved_val, req_val, eee_status; 251 struct bnx2x *bp = params->bp; 252 253 additional_config = 254 REG_RD(bp, params->lfa_base + 255 offsetof(struct shmem_lfa, additional_config)); 256 257 /* NOTE: must be first condition checked - 258 * to verify DCC bit is cleared in any case! 259 */ 260 if (additional_config & NO_LFA_DUE_TO_DCC_MASK) { 261 DP(NETIF_MSG_LINK, "No LFA due to DCC flap after clp exit\n"); 262 REG_WR(bp, params->lfa_base + 263 offsetof(struct shmem_lfa, additional_config), 264 additional_config & ~NO_LFA_DUE_TO_DCC_MASK); 265 return LFA_DCC_LFA_DISABLED; 266 } 267 268 /* Verify that link is up */ 269 link_status = REG_RD(bp, params->shmem_base + 270 offsetof(struct shmem_region, 271 port_mb[params->port].link_status)); 272 if (!(link_status & LINK_STATUS_LINK_UP)) 273 return LFA_LINK_DOWN; 274 275 /* if loaded after BOOT from SAN, don't flap the link in any case and 276 * rely on link set by preboot driver 277 */ 278 if (params->feature_config_flags & FEATURE_CONFIG_BOOT_FROM_SAN) 279 return 0; 280 281 /* Verify that loopback mode is not set */ 282 if (params->loopback_mode) 283 return LFA_LOOPBACK_ENABLED; 284 285 /* Verify that MFW supports LFA */ 286 if (!params->lfa_base) 287 return LFA_MFW_IS_TOO_OLD; 288 289 if (params->num_phys == 3) { 290 cfg_size = 2; 291 lfa_mask = 0xffffffff; 292 } else { 293 cfg_size = 1; 294 lfa_mask = 0xffff; 295 } 296 297 /* Compare Duplex */ 298 saved_val = REG_RD(bp, params->lfa_base + 299 offsetof(struct shmem_lfa, req_duplex)); 300 req_val = params->req_duplex[0] | (params->req_duplex[1] << 16); 301 if ((saved_val & lfa_mask) != (req_val & lfa_mask)) { 302 DP(NETIF_MSG_LINK, "Duplex mismatch %x vs. %x\n", 303 (saved_val & lfa_mask), (req_val & lfa_mask)); 304 return LFA_DUPLEX_MISMATCH; 305 } 306 /* Compare Flow Control */ 307 saved_val = REG_RD(bp, params->lfa_base + 308 offsetof(struct shmem_lfa, req_flow_ctrl)); 309 req_val = params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16); 310 if ((saved_val & lfa_mask) != (req_val & lfa_mask)) { 311 DP(NETIF_MSG_LINK, "Flow control mismatch %x vs. %x\n", 312 (saved_val & lfa_mask), (req_val & lfa_mask)); 313 return LFA_FLOW_CTRL_MISMATCH; 314 } 315 /* Compare Link Speed */ 316 saved_val = REG_RD(bp, params->lfa_base + 317 offsetof(struct shmem_lfa, req_line_speed)); 318 req_val = params->req_line_speed[0] | (params->req_line_speed[1] << 16); 319 if ((saved_val & lfa_mask) != (req_val & lfa_mask)) { 320 DP(NETIF_MSG_LINK, "Link speed mismatch %x vs. %x\n", 321 (saved_val & lfa_mask), (req_val & lfa_mask)); 322 return LFA_LINK_SPEED_MISMATCH; 323 } 324 325 for (cfg_idx = 0; cfg_idx < cfg_size; cfg_idx++) { 326 cur_speed_cap_mask = REG_RD(bp, params->lfa_base + 327 offsetof(struct shmem_lfa, 328 speed_cap_mask[cfg_idx])); 329 330 if (cur_speed_cap_mask != params->speed_cap_mask[cfg_idx]) { 331 DP(NETIF_MSG_LINK, "Speed Cap mismatch %x vs. %x\n", 332 cur_speed_cap_mask, 333 params->speed_cap_mask[cfg_idx]); 334 return LFA_SPEED_CAP_MISMATCH; 335 } 336 } 337 338 cur_req_fc_auto_adv = 339 REG_RD(bp, params->lfa_base + 340 offsetof(struct shmem_lfa, additional_config)) & 341 REQ_FC_AUTO_ADV_MASK; 342 343 if ((u16)cur_req_fc_auto_adv != params->req_fc_auto_adv) { 344 DP(NETIF_MSG_LINK, "Flow Ctrl AN mismatch %x vs. %x\n", 345 cur_req_fc_auto_adv, params->req_fc_auto_adv); 346 return LFA_FLOW_CTRL_MISMATCH; 347 } 348 349 eee_status = REG_RD(bp, params->shmem2_base + 350 offsetof(struct shmem2_region, 351 eee_status[params->port])); 352 353 if (((eee_status & SHMEM_EEE_LPI_REQUESTED_BIT) ^ 354 (params->eee_mode & EEE_MODE_ENABLE_LPI)) || 355 ((eee_status & SHMEM_EEE_REQUESTED_BIT) ^ 356 (params->eee_mode & EEE_MODE_ADV_LPI))) { 357 DP(NETIF_MSG_LINK, "EEE mismatch %x vs. %x\n", params->eee_mode, 358 eee_status); 359 return LFA_EEE_MISMATCH; 360 } 361 362 /* LFA conditions are met */ 363 return 0; 364 } 365 /******************************************************************/ 366 /* EPIO/GPIO section */ 367 /******************************************************************/ 368 static void bnx2x_get_epio(struct bnx2x *bp, u32 epio_pin, u32 *en) 369 { 370 u32 epio_mask, gp_oenable; 371 *en = 0; 372 /* Sanity check */ 373 if (epio_pin > 31) { 374 DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to get\n", epio_pin); 375 return; 376 } 377 378 epio_mask = 1 << epio_pin; 379 /* Set this EPIO to output */ 380 gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE); 381 REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable & ~epio_mask); 382 383 *en = (REG_RD(bp, MCP_REG_MCPR_GP_INPUTS) & epio_mask) >> epio_pin; 384 } 385 static void bnx2x_set_epio(struct bnx2x *bp, u32 epio_pin, u32 en) 386 { 387 u32 epio_mask, gp_output, gp_oenable; 388 389 /* Sanity check */ 390 if (epio_pin > 31) { 391 DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to set\n", epio_pin); 392 return; 393 } 394 DP(NETIF_MSG_LINK, "Setting EPIO pin %d to %d\n", epio_pin, en); 395 epio_mask = 1 << epio_pin; 396 /* Set this EPIO to output */ 397 gp_output = REG_RD(bp, MCP_REG_MCPR_GP_OUTPUTS); 398 if (en) 399 gp_output |= epio_mask; 400 else 401 gp_output &= ~epio_mask; 402 403 REG_WR(bp, MCP_REG_MCPR_GP_OUTPUTS, gp_output); 404 405 /* Set the value for this EPIO */ 406 gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE); 407 REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable | epio_mask); 408 } 409 410 static void bnx2x_set_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 val) 411 { 412 if (pin_cfg == PIN_CFG_NA) 413 return; 414 if (pin_cfg >= PIN_CFG_EPIO0) { 415 bnx2x_set_epio(bp, pin_cfg - PIN_CFG_EPIO0, val); 416 } else { 417 u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3; 418 u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2; 419 bnx2x_set_gpio(bp, gpio_num, (u8)val, gpio_port); 420 } 421 } 422 423 static u32 bnx2x_get_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 *val) 424 { 425 if (pin_cfg == PIN_CFG_NA) 426 return -EINVAL; 427 if (pin_cfg >= PIN_CFG_EPIO0) { 428 bnx2x_get_epio(bp, pin_cfg - PIN_CFG_EPIO0, val); 429 } else { 430 u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3; 431 u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2; 432 *val = bnx2x_get_gpio(bp, gpio_num, gpio_port); 433 } 434 return 0; 435 436 } 437 /******************************************************************/ 438 /* ETS section */ 439 /******************************************************************/ 440 static void bnx2x_ets_e2e3a0_disabled(struct link_params *params) 441 { 442 /* ETS disabled configuration*/ 443 struct bnx2x *bp = params->bp; 444 445 DP(NETIF_MSG_LINK, "ETS E2E3 disabled configuration\n"); 446 447 /* mapping between entry priority to client number (0,1,2 -debug and 448 * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST) 449 * 3bits client num. 450 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0 451 * cos1-100 cos0-011 dbg1-010 dbg0-001 MCP-000 452 */ 453 454 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, 0x4688); 455 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves 456 * as strict. Bits 0,1,2 - debug and management entries, 3 - 457 * COS0 entry, 4 - COS1 entry. 458 * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT 459 * bit4 bit3 bit2 bit1 bit0 460 * MCP and debug are strict 461 */ 462 463 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7); 464 /* defines which entries (clients) are subjected to WFQ arbitration */ 465 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0); 466 /* For strict priority entries defines the number of consecutive 467 * slots for the highest priority. 468 */ 469 REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100); 470 /* mapping between the CREDIT_WEIGHT registers and actual client 471 * numbers 472 */ 473 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0); 474 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0); 475 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0); 476 477 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 0); 478 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 0); 479 REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, 0); 480 /* ETS mode disable */ 481 REG_WR(bp, PBF_REG_ETS_ENABLED, 0); 482 /* If ETS mode is enabled (there is no strict priority) defines a WFQ 483 * weight for COS0/COS1. 484 */ 485 REG_WR(bp, PBF_REG_COS0_WEIGHT, 0x2710); 486 REG_WR(bp, PBF_REG_COS1_WEIGHT, 0x2710); 487 /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter */ 488 REG_WR(bp, PBF_REG_COS0_UPPER_BOUND, 0x989680); 489 REG_WR(bp, PBF_REG_COS1_UPPER_BOUND, 0x989680); 490 /* Defines the number of consecutive slots for the strict priority */ 491 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0); 492 } 493 /****************************************************************************** 494 * Description: 495 * Getting min_w_val will be set according to line speed . 496 *. 497 ******************************************************************************/ 498 static u32 bnx2x_ets_get_min_w_val_nig(const struct link_vars *vars) 499 { 500 u32 min_w_val = 0; 501 /* Calculate min_w_val.*/ 502 if (vars->link_up) { 503 if (vars->line_speed == SPEED_20000) 504 min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS; 505 else 506 min_w_val = ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS; 507 } else 508 min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS; 509 /* If the link isn't up (static configuration for example ) The 510 * link will be according to 20GBPS. 511 */ 512 return min_w_val; 513 } 514 /****************************************************************************** 515 * Description: 516 * Getting credit upper bound form min_w_val. 517 *. 518 ******************************************************************************/ 519 static u32 bnx2x_ets_get_credit_upper_bound(const u32 min_w_val) 520 { 521 const u32 credit_upper_bound = (u32)MAXVAL((150 * min_w_val), 522 MAX_PACKET_SIZE); 523 return credit_upper_bound; 524 } 525 /****************************************************************************** 526 * Description: 527 * Set credit upper bound for NIG. 528 *. 529 ******************************************************************************/ 530 static void bnx2x_ets_e3b0_set_credit_upper_bound_nig( 531 const struct link_params *params, 532 const u32 min_w_val) 533 { 534 struct bnx2x *bp = params->bp; 535 const u8 port = params->port; 536 const u32 credit_upper_bound = 537 bnx2x_ets_get_credit_upper_bound(min_w_val); 538 539 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 : 540 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, credit_upper_bound); 541 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 : 542 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, credit_upper_bound); 543 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 : 544 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_2, credit_upper_bound); 545 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 : 546 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_3, credit_upper_bound); 547 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 : 548 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_4, credit_upper_bound); 549 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 : 550 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_5, credit_upper_bound); 551 552 if (!port) { 553 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6, 554 credit_upper_bound); 555 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7, 556 credit_upper_bound); 557 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8, 558 credit_upper_bound); 559 } 560 } 561 /****************************************************************************** 562 * Description: 563 * Will return the NIG ETS registers to init values.Except 564 * credit_upper_bound. 565 * That isn't used in this configuration (No WFQ is enabled) and will be 566 * configured acording to spec 567 *. 568 ******************************************************************************/ 569 static void bnx2x_ets_e3b0_nig_disabled(const struct link_params *params, 570 const struct link_vars *vars) 571 { 572 struct bnx2x *bp = params->bp; 573 const u8 port = params->port; 574 const u32 min_w_val = bnx2x_ets_get_min_w_val_nig(vars); 575 /* Mapping between entry priority to client number (0,1,2 -debug and 576 * management clients, 3 - COS0 client, 4 - COS1, ... 8 - 577 * COS5)(HIGHEST) 4bits client num.TODO_ETS - Should be done by 578 * reset value or init tool 579 */ 580 if (port) { 581 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, 0x543210); 582 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB, 0x0); 583 } else { 584 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, 0x76543210); 585 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, 0x8); 586 } 587 /* For strict priority entries defines the number of consecutive 588 * slots for the highest priority. 589 */ 590 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS : 591 NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100); 592 /* Mapping between the CREDIT_WEIGHT registers and actual client 593 * numbers 594 */ 595 if (port) { 596 /*Port 1 has 6 COS*/ 597 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB, 0x210543); 598 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x0); 599 } else { 600 /*Port 0 has 9 COS*/ 601 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB, 602 0x43210876); 603 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x5); 604 } 605 606 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves 607 * as strict. Bits 0,1,2 - debug and management entries, 3 - 608 * COS0 entry, 4 - COS1 entry. 609 * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT 610 * bit4 bit3 bit2 bit1 bit0 611 * MCP and debug are strict 612 */ 613 if (port) 614 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT, 0x3f); 615 else 616 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1ff); 617 /* defines which entries (clients) are subjected to WFQ arbitration */ 618 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ : 619 NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0); 620 621 /* Please notice the register address are note continuous and a 622 * for here is note appropriate.In 2 port mode port0 only COS0-5 623 * can be used. DEBUG1,DEBUG1,MGMT are never used for WFQ* In 4 624 * port mode port1 only COS0-2 can be used. DEBUG1,DEBUG1,MGMT 625 * are never used for WFQ 626 */ 627 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 : 628 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0x0); 629 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 : 630 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0x0); 631 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 : 632 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2, 0x0); 633 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 : 634 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3, 0x0); 635 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 : 636 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4, 0x0); 637 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 : 638 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5, 0x0); 639 if (!port) { 640 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6, 0x0); 641 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7, 0x0); 642 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8, 0x0); 643 } 644 645 bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val); 646 } 647 /****************************************************************************** 648 * Description: 649 * Set credit upper bound for PBF. 650 *. 651 ******************************************************************************/ 652 static void bnx2x_ets_e3b0_set_credit_upper_bound_pbf( 653 const struct link_params *params, 654 const u32 min_w_val) 655 { 656 struct bnx2x *bp = params->bp; 657 const u32 credit_upper_bound = 658 bnx2x_ets_get_credit_upper_bound(min_w_val); 659 const u8 port = params->port; 660 u32 base_upper_bound = 0; 661 u8 max_cos = 0; 662 u8 i = 0; 663 /* In 2 port mode port0 has COS0-5 that can be used for WFQ.In 4 664 * port mode port1 has COS0-2 that can be used for WFQ. 665 */ 666 if (!port) { 667 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P0; 668 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0; 669 } else { 670 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P1; 671 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT1; 672 } 673 674 for (i = 0; i < max_cos; i++) 675 REG_WR(bp, base_upper_bound + (i << 2), credit_upper_bound); 676 } 677 678 /****************************************************************************** 679 * Description: 680 * Will return the PBF ETS registers to init values.Except 681 * credit_upper_bound. 682 * That isn't used in this configuration (No WFQ is enabled) and will be 683 * configured acording to spec 684 *. 685 ******************************************************************************/ 686 static void bnx2x_ets_e3b0_pbf_disabled(const struct link_params *params) 687 { 688 struct bnx2x *bp = params->bp; 689 const u8 port = params->port; 690 const u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL; 691 u8 i = 0; 692 u32 base_weight = 0; 693 u8 max_cos = 0; 694 695 /* Mapping between entry priority to client number 0 - COS0 696 * client, 2 - COS1, ... 5 - COS5)(HIGHEST) 4bits client num. 697 * TODO_ETS - Should be done by reset value or init tool 698 */ 699 if (port) 700 /* 0x688 (|011|0 10|00 1|000) */ 701 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , 0x688); 702 else 703 /* (10 1|100 |011|0 10|00 1|000) */ 704 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , 0x2C688); 705 706 /* TODO_ETS - Should be done by reset value or init tool */ 707 if (port) 708 /* 0x688 (|011|0 10|00 1|000)*/ 709 REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1, 0x688); 710 else 711 /* 0x2C688 (10 1|100 |011|0 10|00 1|000) */ 712 REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0, 0x2C688); 713 714 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 : 715 PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0 , 0x100); 716 717 718 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 : 719 PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , 0); 720 721 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 : 722 PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0 , 0); 723 /* In 2 port mode port0 has COS0-5 that can be used for WFQ. 724 * In 4 port mode port1 has COS0-2 that can be used for WFQ. 725 */ 726 if (!port) { 727 base_weight = PBF_REG_COS0_WEIGHT_P0; 728 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0; 729 } else { 730 base_weight = PBF_REG_COS0_WEIGHT_P1; 731 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT1; 732 } 733 734 for (i = 0; i < max_cos; i++) 735 REG_WR(bp, base_weight + (0x4 * i), 0); 736 737 bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf); 738 } 739 /****************************************************************************** 740 * Description: 741 * E3B0 disable will return basicly the values to init values. 742 *. 743 ******************************************************************************/ 744 static int bnx2x_ets_e3b0_disabled(const struct link_params *params, 745 const struct link_vars *vars) 746 { 747 struct bnx2x *bp = params->bp; 748 749 if (!CHIP_IS_E3B0(bp)) { 750 DP(NETIF_MSG_LINK, 751 "bnx2x_ets_e3b0_disabled the chip isn't E3B0\n"); 752 return -EINVAL; 753 } 754 755 bnx2x_ets_e3b0_nig_disabled(params, vars); 756 757 bnx2x_ets_e3b0_pbf_disabled(params); 758 759 return 0; 760 } 761 762 /****************************************************************************** 763 * Description: 764 * Disable will return basicly the values to init values. 765 * 766 ******************************************************************************/ 767 int bnx2x_ets_disabled(struct link_params *params, 768 struct link_vars *vars) 769 { 770 struct bnx2x *bp = params->bp; 771 int bnx2x_status = 0; 772 773 if ((CHIP_IS_E2(bp)) || (CHIP_IS_E3A0(bp))) 774 bnx2x_ets_e2e3a0_disabled(params); 775 else if (CHIP_IS_E3B0(bp)) 776 bnx2x_status = bnx2x_ets_e3b0_disabled(params, vars); 777 else { 778 DP(NETIF_MSG_LINK, "bnx2x_ets_disabled - chip not supported\n"); 779 return -EINVAL; 780 } 781 782 return bnx2x_status; 783 } 784 785 /****************************************************************************** 786 * Description 787 * Set the COS mappimg to SP and BW until this point all the COS are not 788 * set as SP or BW. 789 ******************************************************************************/ 790 static int bnx2x_ets_e3b0_cli_map(const struct link_params *params, 791 const struct bnx2x_ets_params *ets_params, 792 const u8 cos_sp_bitmap, 793 const u8 cos_bw_bitmap) 794 { 795 struct bnx2x *bp = params->bp; 796 const u8 port = params->port; 797 const u8 nig_cli_sp_bitmap = 0x7 | (cos_sp_bitmap << 3); 798 const u8 pbf_cli_sp_bitmap = cos_sp_bitmap; 799 const u8 nig_cli_subject2wfq_bitmap = cos_bw_bitmap << 3; 800 const u8 pbf_cli_subject2wfq_bitmap = cos_bw_bitmap; 801 802 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT : 803 NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, nig_cli_sp_bitmap); 804 805 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 : 806 PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , pbf_cli_sp_bitmap); 807 808 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ : 809 NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 810 nig_cli_subject2wfq_bitmap); 811 812 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 : 813 PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0, 814 pbf_cli_subject2wfq_bitmap); 815 816 return 0; 817 } 818 819 /****************************************************************************** 820 * Description: 821 * This function is needed because NIG ARB_CREDIT_WEIGHT_X are 822 * not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable. 823 ******************************************************************************/ 824 static int bnx2x_ets_e3b0_set_cos_bw(struct bnx2x *bp, 825 const u8 cos_entry, 826 const u32 min_w_val_nig, 827 const u32 min_w_val_pbf, 828 const u16 total_bw, 829 const u8 bw, 830 const u8 port) 831 { 832 u32 nig_reg_adress_crd_weight = 0; 833 u32 pbf_reg_adress_crd_weight = 0; 834 /* Calculate and set BW for this COS - use 1 instead of 0 for BW */ 835 const u32 cos_bw_nig = ((bw ? bw : 1) * min_w_val_nig) / total_bw; 836 const u32 cos_bw_pbf = ((bw ? bw : 1) * min_w_val_pbf) / total_bw; 837 838 switch (cos_entry) { 839 case 0: 840 nig_reg_adress_crd_weight = 841 (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 : 842 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0; 843 pbf_reg_adress_crd_weight = (port) ? 844 PBF_REG_COS0_WEIGHT_P1 : PBF_REG_COS0_WEIGHT_P0; 845 break; 846 case 1: 847 nig_reg_adress_crd_weight = (port) ? 848 NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 : 849 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1; 850 pbf_reg_adress_crd_weight = (port) ? 851 PBF_REG_COS1_WEIGHT_P1 : PBF_REG_COS1_WEIGHT_P0; 852 break; 853 case 2: 854 nig_reg_adress_crd_weight = (port) ? 855 NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 : 856 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2; 857 858 pbf_reg_adress_crd_weight = (port) ? 859 PBF_REG_COS2_WEIGHT_P1 : PBF_REG_COS2_WEIGHT_P0; 860 break; 861 case 3: 862 if (port) 863 return -EINVAL; 864 nig_reg_adress_crd_weight = 865 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3; 866 pbf_reg_adress_crd_weight = 867 PBF_REG_COS3_WEIGHT_P0; 868 break; 869 case 4: 870 if (port) 871 return -EINVAL; 872 nig_reg_adress_crd_weight = 873 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4; 874 pbf_reg_adress_crd_weight = PBF_REG_COS4_WEIGHT_P0; 875 break; 876 case 5: 877 if (port) 878 return -EINVAL; 879 nig_reg_adress_crd_weight = 880 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5; 881 pbf_reg_adress_crd_weight = PBF_REG_COS5_WEIGHT_P0; 882 break; 883 } 884 885 REG_WR(bp, nig_reg_adress_crd_weight, cos_bw_nig); 886 887 REG_WR(bp, pbf_reg_adress_crd_weight, cos_bw_pbf); 888 889 return 0; 890 } 891 /****************************************************************************** 892 * Description: 893 * Calculate the total BW.A value of 0 isn't legal. 894 * 895 ******************************************************************************/ 896 static int bnx2x_ets_e3b0_get_total_bw( 897 const struct link_params *params, 898 struct bnx2x_ets_params *ets_params, 899 u16 *total_bw) 900 { 901 struct bnx2x *bp = params->bp; 902 u8 cos_idx = 0; 903 u8 is_bw_cos_exist = 0; 904 905 *total_bw = 0 ; 906 /* Calculate total BW requested */ 907 for (cos_idx = 0; cos_idx < ets_params->num_of_cos; cos_idx++) { 908 if (ets_params->cos[cos_idx].state == bnx2x_cos_state_bw) { 909 is_bw_cos_exist = 1; 910 if (!ets_params->cos[cos_idx].params.bw_params.bw) { 911 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config BW" 912 "was set to 0\n"); 913 /* This is to prevent a state when ramrods 914 * can't be sent 915 */ 916 ets_params->cos[cos_idx].params.bw_params.bw 917 = 1; 918 } 919 *total_bw += 920 ets_params->cos[cos_idx].params.bw_params.bw; 921 } 922 } 923 924 /* Check total BW is valid */ 925 if ((is_bw_cos_exist == 1) && (*total_bw != 100)) { 926 if (*total_bw == 0) { 927 DP(NETIF_MSG_LINK, 928 "bnx2x_ets_E3B0_config total BW shouldn't be 0\n"); 929 return -EINVAL; 930 } 931 DP(NETIF_MSG_LINK, 932 "bnx2x_ets_E3B0_config total BW should be 100\n"); 933 /* We can handle a case whre the BW isn't 100 this can happen 934 * if the TC are joined. 935 */ 936 } 937 return 0; 938 } 939 940 /****************************************************************************** 941 * Description: 942 * Invalidate all the sp_pri_to_cos. 943 * 944 ******************************************************************************/ 945 static void bnx2x_ets_e3b0_sp_pri_to_cos_init(u8 *sp_pri_to_cos) 946 { 947 u8 pri = 0; 948 for (pri = 0; pri < DCBX_MAX_NUM_COS; pri++) 949 sp_pri_to_cos[pri] = DCBX_INVALID_COS; 950 } 951 /****************************************************************************** 952 * Description: 953 * Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers 954 * according to sp_pri_to_cos. 955 * 956 ******************************************************************************/ 957 static int bnx2x_ets_e3b0_sp_pri_to_cos_set(const struct link_params *params, 958 u8 *sp_pri_to_cos, const u8 pri, 959 const u8 cos_entry) 960 { 961 struct bnx2x *bp = params->bp; 962 const u8 port = params->port; 963 const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 : 964 DCBX_E3B0_MAX_NUM_COS_PORT0; 965 966 if (pri >= max_num_of_cos) { 967 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid " 968 "parameter Illegal strict priority\n"); 969 return -EINVAL; 970 } 971 972 if (sp_pri_to_cos[pri] != DCBX_INVALID_COS) { 973 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid " 974 "parameter There can't be two COS's with " 975 "the same strict pri\n"); 976 return -EINVAL; 977 } 978 979 sp_pri_to_cos[pri] = cos_entry; 980 return 0; 981 982 } 983 984 /****************************************************************************** 985 * Description: 986 * Returns the correct value according to COS and priority in 987 * the sp_pri_cli register. 988 * 989 ******************************************************************************/ 990 static u64 bnx2x_e3b0_sp_get_pri_cli_reg(const u8 cos, const u8 cos_offset, 991 const u8 pri_set, 992 const u8 pri_offset, 993 const u8 entry_size) 994 { 995 u64 pri_cli_nig = 0; 996 pri_cli_nig = ((u64)(cos + cos_offset)) << (entry_size * 997 (pri_set + pri_offset)); 998 999 return pri_cli_nig; 1000 } 1001 /****************************************************************************** 1002 * Description: 1003 * Returns the correct value according to COS and priority in the 1004 * sp_pri_cli register for NIG. 1005 * 1006 ******************************************************************************/ 1007 static u64 bnx2x_e3b0_sp_get_pri_cli_reg_nig(const u8 cos, const u8 pri_set) 1008 { 1009 /* MCP Dbg0 and dbg1 are always with higher strict pri*/ 1010 const u8 nig_cos_offset = 3; 1011 const u8 nig_pri_offset = 3; 1012 1013 return bnx2x_e3b0_sp_get_pri_cli_reg(cos, nig_cos_offset, pri_set, 1014 nig_pri_offset, 4); 1015 1016 } 1017 /****************************************************************************** 1018 * Description: 1019 * Returns the correct value according to COS and priority in the 1020 * sp_pri_cli register for PBF. 1021 * 1022 ******************************************************************************/ 1023 static u64 bnx2x_e3b0_sp_get_pri_cli_reg_pbf(const u8 cos, const u8 pri_set) 1024 { 1025 const u8 pbf_cos_offset = 0; 1026 const u8 pbf_pri_offset = 0; 1027 1028 return bnx2x_e3b0_sp_get_pri_cli_reg(cos, pbf_cos_offset, pri_set, 1029 pbf_pri_offset, 3); 1030 1031 } 1032 1033 /****************************************************************************** 1034 * Description: 1035 * Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers 1036 * according to sp_pri_to_cos.(which COS has higher priority) 1037 * 1038 ******************************************************************************/ 1039 static int bnx2x_ets_e3b0_sp_set_pri_cli_reg(const struct link_params *params, 1040 u8 *sp_pri_to_cos) 1041 { 1042 struct bnx2x *bp = params->bp; 1043 u8 i = 0; 1044 const u8 port = params->port; 1045 /* MCP Dbg0 and dbg1 are always with higher strict pri*/ 1046 u64 pri_cli_nig = 0x210; 1047 u32 pri_cli_pbf = 0x0; 1048 u8 pri_set = 0; 1049 u8 pri_bitmask = 0; 1050 const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 : 1051 DCBX_E3B0_MAX_NUM_COS_PORT0; 1052 1053 u8 cos_bit_to_set = (1 << max_num_of_cos) - 1; 1054 1055 /* Set all the strict priority first */ 1056 for (i = 0; i < max_num_of_cos; i++) { 1057 if (sp_pri_to_cos[i] != DCBX_INVALID_COS) { 1058 if (sp_pri_to_cos[i] >= DCBX_MAX_NUM_COS) { 1059 DP(NETIF_MSG_LINK, 1060 "bnx2x_ets_e3b0_sp_set_pri_cli_reg " 1061 "invalid cos entry\n"); 1062 return -EINVAL; 1063 } 1064 1065 pri_cli_nig |= bnx2x_e3b0_sp_get_pri_cli_reg_nig( 1066 sp_pri_to_cos[i], pri_set); 1067 1068 pri_cli_pbf |= bnx2x_e3b0_sp_get_pri_cli_reg_pbf( 1069 sp_pri_to_cos[i], pri_set); 1070 pri_bitmask = 1 << sp_pri_to_cos[i]; 1071 /* COS is used remove it from bitmap.*/ 1072 if (!(pri_bitmask & cos_bit_to_set)) { 1073 DP(NETIF_MSG_LINK, 1074 "bnx2x_ets_e3b0_sp_set_pri_cli_reg " 1075 "invalid There can't be two COS's with" 1076 " the same strict pri\n"); 1077 return -EINVAL; 1078 } 1079 cos_bit_to_set &= ~pri_bitmask; 1080 pri_set++; 1081 } 1082 } 1083 1084 /* Set all the Non strict priority i= COS*/ 1085 for (i = 0; i < max_num_of_cos; i++) { 1086 pri_bitmask = 1 << i; 1087 /* Check if COS was already used for SP */ 1088 if (pri_bitmask & cos_bit_to_set) { 1089 /* COS wasn't used for SP */ 1090 pri_cli_nig |= bnx2x_e3b0_sp_get_pri_cli_reg_nig( 1091 i, pri_set); 1092 1093 pri_cli_pbf |= bnx2x_e3b0_sp_get_pri_cli_reg_pbf( 1094 i, pri_set); 1095 /* COS is used remove it from bitmap.*/ 1096 cos_bit_to_set &= ~pri_bitmask; 1097 pri_set++; 1098 } 1099 } 1100 1101 if (pri_set != max_num_of_cos) { 1102 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_set_pri_cli_reg not all " 1103 "entries were set\n"); 1104 return -EINVAL; 1105 } 1106 1107 if (port) { 1108 /* Only 6 usable clients*/ 1109 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, 1110 (u32)pri_cli_nig); 1111 1112 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , pri_cli_pbf); 1113 } else { 1114 /* Only 9 usable clients*/ 1115 const u32 pri_cli_nig_lsb = (u32) (pri_cli_nig); 1116 const u32 pri_cli_nig_msb = (u32) ((pri_cli_nig >> 32) & 0xF); 1117 1118 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, 1119 pri_cli_nig_lsb); 1120 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, 1121 pri_cli_nig_msb); 1122 1123 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , pri_cli_pbf); 1124 } 1125 return 0; 1126 } 1127 1128 /****************************************************************************** 1129 * Description: 1130 * Configure the COS to ETS according to BW and SP settings. 1131 ******************************************************************************/ 1132 int bnx2x_ets_e3b0_config(const struct link_params *params, 1133 const struct link_vars *vars, 1134 struct bnx2x_ets_params *ets_params) 1135 { 1136 struct bnx2x *bp = params->bp; 1137 int bnx2x_status = 0; 1138 const u8 port = params->port; 1139 u16 total_bw = 0; 1140 const u32 min_w_val_nig = bnx2x_ets_get_min_w_val_nig(vars); 1141 const u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL; 1142 u8 cos_bw_bitmap = 0; 1143 u8 cos_sp_bitmap = 0; 1144 u8 sp_pri_to_cos[DCBX_MAX_NUM_COS] = {0}; 1145 const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 : 1146 DCBX_E3B0_MAX_NUM_COS_PORT0; 1147 u8 cos_entry = 0; 1148 1149 if (!CHIP_IS_E3B0(bp)) { 1150 DP(NETIF_MSG_LINK, 1151 "bnx2x_ets_e3b0_disabled the chip isn't E3B0\n"); 1152 return -EINVAL; 1153 } 1154 1155 if ((ets_params->num_of_cos > max_num_of_cos)) { 1156 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config the number of COS " 1157 "isn't supported\n"); 1158 return -EINVAL; 1159 } 1160 1161 /* Prepare sp strict priority parameters*/ 1162 bnx2x_ets_e3b0_sp_pri_to_cos_init(sp_pri_to_cos); 1163 1164 /* Prepare BW parameters*/ 1165 bnx2x_status = bnx2x_ets_e3b0_get_total_bw(params, ets_params, 1166 &total_bw); 1167 if (bnx2x_status) { 1168 DP(NETIF_MSG_LINK, 1169 "bnx2x_ets_E3B0_config get_total_bw failed\n"); 1170 return -EINVAL; 1171 } 1172 1173 /* Upper bound is set according to current link speed (min_w_val 1174 * should be the same for upper bound and COS credit val). 1175 */ 1176 bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val_nig); 1177 bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf); 1178 1179 1180 for (cos_entry = 0; cos_entry < ets_params->num_of_cos; cos_entry++) { 1181 if (bnx2x_cos_state_bw == ets_params->cos[cos_entry].state) { 1182 cos_bw_bitmap |= (1 << cos_entry); 1183 /* The function also sets the BW in HW(not the mappin 1184 * yet) 1185 */ 1186 bnx2x_status = bnx2x_ets_e3b0_set_cos_bw( 1187 bp, cos_entry, min_w_val_nig, min_w_val_pbf, 1188 total_bw, 1189 ets_params->cos[cos_entry].params.bw_params.bw, 1190 port); 1191 } else if (bnx2x_cos_state_strict == 1192 ets_params->cos[cos_entry].state){ 1193 cos_sp_bitmap |= (1 << cos_entry); 1194 1195 bnx2x_status = bnx2x_ets_e3b0_sp_pri_to_cos_set( 1196 params, 1197 sp_pri_to_cos, 1198 ets_params->cos[cos_entry].params.sp_params.pri, 1199 cos_entry); 1200 1201 } else { 1202 DP(NETIF_MSG_LINK, 1203 "bnx2x_ets_e3b0_config cos state not valid\n"); 1204 return -EINVAL; 1205 } 1206 if (bnx2x_status) { 1207 DP(NETIF_MSG_LINK, 1208 "bnx2x_ets_e3b0_config set cos bw failed\n"); 1209 return bnx2x_status; 1210 } 1211 } 1212 1213 /* Set SP register (which COS has higher priority) */ 1214 bnx2x_status = bnx2x_ets_e3b0_sp_set_pri_cli_reg(params, 1215 sp_pri_to_cos); 1216 1217 if (bnx2x_status) { 1218 DP(NETIF_MSG_LINK, 1219 "bnx2x_ets_E3B0_config set_pri_cli_reg failed\n"); 1220 return bnx2x_status; 1221 } 1222 1223 /* Set client mapping of BW and strict */ 1224 bnx2x_status = bnx2x_ets_e3b0_cli_map(params, ets_params, 1225 cos_sp_bitmap, 1226 cos_bw_bitmap); 1227 1228 if (bnx2x_status) { 1229 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config SP failed\n"); 1230 return bnx2x_status; 1231 } 1232 return 0; 1233 } 1234 static void bnx2x_ets_bw_limit_common(const struct link_params *params) 1235 { 1236 /* ETS disabled configuration */ 1237 struct bnx2x *bp = params->bp; 1238 DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n"); 1239 /* Defines which entries (clients) are subjected to WFQ arbitration 1240 * COS0 0x8 1241 * COS1 0x10 1242 */ 1243 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0x18); 1244 /* Mapping between the ARB_CREDIT_WEIGHT registers and actual 1245 * client numbers (WEIGHT_0 does not actually have to represent 1246 * client 0) 1247 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0 1248 * cos1-001 cos0-000 dbg1-100 dbg0-011 MCP-010 1249 */ 1250 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0x111A); 1251 1252 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 1253 ETS_BW_LIMIT_CREDIT_UPPER_BOUND); 1254 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 1255 ETS_BW_LIMIT_CREDIT_UPPER_BOUND); 1256 1257 /* ETS mode enabled*/ 1258 REG_WR(bp, PBF_REG_ETS_ENABLED, 1); 1259 1260 /* Defines the number of consecutive slots for the strict priority */ 1261 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0); 1262 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves 1263 * as strict. Bits 0,1,2 - debug and management entries, 3 - COS0 1264 * entry, 4 - COS1 entry. 1265 * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT 1266 * bit4 bit3 bit2 bit1 bit0 1267 * MCP and debug are strict 1268 */ 1269 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7); 1270 1271 /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter.*/ 1272 REG_WR(bp, PBF_REG_COS0_UPPER_BOUND, 1273 ETS_BW_LIMIT_CREDIT_UPPER_BOUND); 1274 REG_WR(bp, PBF_REG_COS1_UPPER_BOUND, 1275 ETS_BW_LIMIT_CREDIT_UPPER_BOUND); 1276 } 1277 1278 void bnx2x_ets_bw_limit(const struct link_params *params, const u32 cos0_bw, 1279 const u32 cos1_bw) 1280 { 1281 /* ETS disabled configuration*/ 1282 struct bnx2x *bp = params->bp; 1283 const u32 total_bw = cos0_bw + cos1_bw; 1284 u32 cos0_credit_weight = 0; 1285 u32 cos1_credit_weight = 0; 1286 1287 DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n"); 1288 1289 if ((!total_bw) || 1290 (!cos0_bw) || 1291 (!cos1_bw)) { 1292 DP(NETIF_MSG_LINK, "Total BW can't be zero\n"); 1293 return; 1294 } 1295 1296 cos0_credit_weight = (cos0_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/ 1297 total_bw; 1298 cos1_credit_weight = (cos1_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/ 1299 total_bw; 1300 1301 bnx2x_ets_bw_limit_common(params); 1302 1303 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, cos0_credit_weight); 1304 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, cos1_credit_weight); 1305 1306 REG_WR(bp, PBF_REG_COS0_WEIGHT, cos0_credit_weight); 1307 REG_WR(bp, PBF_REG_COS1_WEIGHT, cos1_credit_weight); 1308 } 1309 1310 int bnx2x_ets_strict(const struct link_params *params, const u8 strict_cos) 1311 { 1312 /* ETS disabled configuration*/ 1313 struct bnx2x *bp = params->bp; 1314 u32 val = 0; 1315 1316 DP(NETIF_MSG_LINK, "ETS enabled strict configuration\n"); 1317 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves 1318 * as strict. Bits 0,1,2 - debug and management entries, 1319 * 3 - COS0 entry, 4 - COS1 entry. 1320 * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT 1321 * bit4 bit3 bit2 bit1 bit0 1322 * MCP and debug are strict 1323 */ 1324 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1F); 1325 /* For strict priority entries defines the number of consecutive slots 1326 * for the highest priority. 1327 */ 1328 REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100); 1329 /* ETS mode disable */ 1330 REG_WR(bp, PBF_REG_ETS_ENABLED, 0); 1331 /* Defines the number of consecutive slots for the strict priority */ 1332 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0x100); 1333 1334 /* Defines the number of consecutive slots for the strict priority */ 1335 REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, strict_cos); 1336 1337 /* Mapping between entry priority to client number (0,1,2 -debug and 1338 * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST) 1339 * 3bits client num. 1340 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0 1341 * dbg0-010 dbg1-001 cos1-100 cos0-011 MCP-000 1342 * dbg0-010 dbg1-001 cos0-011 cos1-100 MCP-000 1343 */ 1344 val = (!strict_cos) ? 0x2318 : 0x22E0; 1345 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, val); 1346 1347 return 0; 1348 } 1349 1350 /******************************************************************/ 1351 /* PFC section */ 1352 /******************************************************************/ 1353 static void bnx2x_update_pfc_xmac(struct link_params *params, 1354 struct link_vars *vars, 1355 u8 is_lb) 1356 { 1357 struct bnx2x *bp = params->bp; 1358 u32 xmac_base; 1359 u32 pause_val, pfc0_val, pfc1_val; 1360 1361 /* XMAC base adrr */ 1362 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; 1363 1364 /* Initialize pause and pfc registers */ 1365 pause_val = 0x18000; 1366 pfc0_val = 0xFFFF8000; 1367 pfc1_val = 0x2; 1368 1369 /* No PFC support */ 1370 if (!(params->feature_config_flags & 1371 FEATURE_CONFIG_PFC_ENABLED)) { 1372 1373 /* RX flow control - Process pause frame in receive direction 1374 */ 1375 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX) 1376 pause_val |= XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN; 1377 1378 /* TX flow control - Send pause packet when buffer is full */ 1379 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) 1380 pause_val |= XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN; 1381 } else {/* PFC support */ 1382 pfc1_val |= XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN | 1383 XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN | 1384 XMAC_PFC_CTRL_HI_REG_RX_PFC_EN | 1385 XMAC_PFC_CTRL_HI_REG_TX_PFC_EN | 1386 XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON; 1387 /* Write pause and PFC registers */ 1388 REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val); 1389 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val); 1390 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val); 1391 pfc1_val &= ~XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON; 1392 1393 } 1394 1395 /* Write pause and PFC registers */ 1396 REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val); 1397 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val); 1398 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val); 1399 1400 1401 /* Set MAC address for source TX Pause/PFC frames */ 1402 REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_LO, 1403 ((params->mac_addr[2] << 24) | 1404 (params->mac_addr[3] << 16) | 1405 (params->mac_addr[4] << 8) | 1406 (params->mac_addr[5]))); 1407 REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_HI, 1408 ((params->mac_addr[0] << 8) | 1409 (params->mac_addr[1]))); 1410 1411 udelay(30); 1412 } 1413 1414 /******************************************************************/ 1415 /* MAC/PBF section */ 1416 /******************************************************************/ 1417 static void bnx2x_set_mdio_clk(struct bnx2x *bp, u32 chip_id, 1418 u32 emac_base) 1419 { 1420 u32 new_mode, cur_mode; 1421 u32 clc_cnt; 1422 /* Set clause 45 mode, slow down the MDIO clock to 2.5MHz 1423 * (a value of 49==0x31) and make sure that the AUTO poll is off 1424 */ 1425 cur_mode = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE); 1426 1427 if (USES_WARPCORE(bp)) 1428 clc_cnt = 74L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT; 1429 else 1430 clc_cnt = 49L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT; 1431 1432 if (((cur_mode & EMAC_MDIO_MODE_CLOCK_CNT) == clc_cnt) && 1433 (cur_mode & (EMAC_MDIO_MODE_CLAUSE_45))) 1434 return; 1435 1436 new_mode = cur_mode & 1437 ~(EMAC_MDIO_MODE_AUTO_POLL | EMAC_MDIO_MODE_CLOCK_CNT); 1438 new_mode |= clc_cnt; 1439 new_mode |= (EMAC_MDIO_MODE_CLAUSE_45); 1440 1441 DP(NETIF_MSG_LINK, "Changing emac_mode from 0x%x to 0x%x\n", 1442 cur_mode, new_mode); 1443 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE, new_mode); 1444 udelay(40); 1445 } 1446 1447 static void bnx2x_set_mdio_emac_per_phy(struct bnx2x *bp, 1448 struct link_params *params) 1449 { 1450 u8 phy_index; 1451 /* Set mdio clock per phy */ 1452 for (phy_index = INT_PHY; phy_index < params->num_phys; 1453 phy_index++) 1454 bnx2x_set_mdio_clk(bp, params->chip_id, 1455 params->phy[phy_index].mdio_ctrl); 1456 } 1457 1458 static u8 bnx2x_is_4_port_mode(struct bnx2x *bp) 1459 { 1460 u32 port4mode_ovwr_val; 1461 /* Check 4-port override enabled */ 1462 port4mode_ovwr_val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR); 1463 if (port4mode_ovwr_val & (1<<0)) { 1464 /* Return 4-port mode override value */ 1465 return ((port4mode_ovwr_val & (1<<1)) == (1<<1)); 1466 } 1467 /* Return 4-port mode from input pin */ 1468 return (u8)REG_RD(bp, MISC_REG_PORT4MODE_EN); 1469 } 1470 1471 static void bnx2x_emac_init(struct link_params *params, 1472 struct link_vars *vars) 1473 { 1474 /* reset and unreset the emac core */ 1475 struct bnx2x *bp = params->bp; 1476 u8 port = params->port; 1477 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; 1478 u32 val; 1479 u16 timeout; 1480 1481 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 1482 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port)); 1483 udelay(5); 1484 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 1485 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port)); 1486 1487 /* init emac - use read-modify-write */ 1488 /* self clear reset */ 1489 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE); 1490 EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET)); 1491 1492 timeout = 200; 1493 do { 1494 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE); 1495 DP(NETIF_MSG_LINK, "EMAC reset reg is %u\n", val); 1496 if (!timeout) { 1497 DP(NETIF_MSG_LINK, "EMAC timeout!\n"); 1498 return; 1499 } 1500 timeout--; 1501 } while (val & EMAC_MODE_RESET); 1502 1503 bnx2x_set_mdio_emac_per_phy(bp, params); 1504 /* Set mac address */ 1505 val = ((params->mac_addr[0] << 8) | 1506 params->mac_addr[1]); 1507 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH, val); 1508 1509 val = ((params->mac_addr[2] << 24) | 1510 (params->mac_addr[3] << 16) | 1511 (params->mac_addr[4] << 8) | 1512 params->mac_addr[5]); 1513 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + 4, val); 1514 } 1515 1516 static void bnx2x_set_xumac_nig(struct link_params *params, 1517 u16 tx_pause_en, 1518 u8 enable) 1519 { 1520 struct bnx2x *bp = params->bp; 1521 1522 REG_WR(bp, params->port ? NIG_REG_P1_MAC_IN_EN : NIG_REG_P0_MAC_IN_EN, 1523 enable); 1524 REG_WR(bp, params->port ? NIG_REG_P1_MAC_OUT_EN : NIG_REG_P0_MAC_OUT_EN, 1525 enable); 1526 REG_WR(bp, params->port ? NIG_REG_P1_MAC_PAUSE_OUT_EN : 1527 NIG_REG_P0_MAC_PAUSE_OUT_EN, tx_pause_en); 1528 } 1529 1530 static void bnx2x_set_umac_rxtx(struct link_params *params, u8 en) 1531 { 1532 u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0; 1533 u32 val; 1534 struct bnx2x *bp = params->bp; 1535 if (!(REG_RD(bp, MISC_REG_RESET_REG_2) & 1536 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port))) 1537 return; 1538 val = REG_RD(bp, umac_base + UMAC_REG_COMMAND_CONFIG); 1539 if (en) 1540 val |= (UMAC_COMMAND_CONFIG_REG_TX_ENA | 1541 UMAC_COMMAND_CONFIG_REG_RX_ENA); 1542 else 1543 val &= ~(UMAC_COMMAND_CONFIG_REG_TX_ENA | 1544 UMAC_COMMAND_CONFIG_REG_RX_ENA); 1545 /* Disable RX and TX */ 1546 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val); 1547 } 1548 1549 static void bnx2x_umac_enable(struct link_params *params, 1550 struct link_vars *vars, u8 lb) 1551 { 1552 u32 val; 1553 u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0; 1554 struct bnx2x *bp = params->bp; 1555 /* Reset UMAC */ 1556 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 1557 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port)); 1558 usleep_range(1000, 2000); 1559 1560 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 1561 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port)); 1562 1563 DP(NETIF_MSG_LINK, "enabling UMAC\n"); 1564 1565 /* This register opens the gate for the UMAC despite its name */ 1566 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1); 1567 1568 val = UMAC_COMMAND_CONFIG_REG_PROMIS_EN | 1569 UMAC_COMMAND_CONFIG_REG_PAD_EN | 1570 UMAC_COMMAND_CONFIG_REG_SW_RESET | 1571 UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK; 1572 switch (vars->line_speed) { 1573 case SPEED_10: 1574 val |= (0<<2); 1575 break; 1576 case SPEED_100: 1577 val |= (1<<2); 1578 break; 1579 case SPEED_1000: 1580 val |= (2<<2); 1581 break; 1582 case SPEED_2500: 1583 val |= (3<<2); 1584 break; 1585 default: 1586 DP(NETIF_MSG_LINK, "Invalid speed for UMAC %d\n", 1587 vars->line_speed); 1588 break; 1589 } 1590 if (!(vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)) 1591 val |= UMAC_COMMAND_CONFIG_REG_IGNORE_TX_PAUSE; 1592 1593 if (!(vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)) 1594 val |= UMAC_COMMAND_CONFIG_REG_PAUSE_IGNORE; 1595 1596 if (vars->duplex == DUPLEX_HALF) 1597 val |= UMAC_COMMAND_CONFIG_REG_HD_ENA; 1598 1599 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val); 1600 udelay(50); 1601 1602 /* Configure UMAC for EEE */ 1603 if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) { 1604 DP(NETIF_MSG_LINK, "configured UMAC for EEE\n"); 1605 REG_WR(bp, umac_base + UMAC_REG_UMAC_EEE_CTRL, 1606 UMAC_UMAC_EEE_CTRL_REG_EEE_EN); 1607 REG_WR(bp, umac_base + UMAC_REG_EEE_WAKE_TIMER, 0x11); 1608 } else { 1609 REG_WR(bp, umac_base + UMAC_REG_UMAC_EEE_CTRL, 0x0); 1610 } 1611 1612 /* Set MAC address for source TX Pause/PFC frames (under SW reset) */ 1613 REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR0, 1614 ((params->mac_addr[2] << 24) | 1615 (params->mac_addr[3] << 16) | 1616 (params->mac_addr[4] << 8) | 1617 (params->mac_addr[5]))); 1618 REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR1, 1619 ((params->mac_addr[0] << 8) | 1620 (params->mac_addr[1]))); 1621 1622 /* Enable RX and TX */ 1623 val &= ~UMAC_COMMAND_CONFIG_REG_PAD_EN; 1624 val |= UMAC_COMMAND_CONFIG_REG_TX_ENA | 1625 UMAC_COMMAND_CONFIG_REG_RX_ENA; 1626 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val); 1627 udelay(50); 1628 1629 /* Remove SW Reset */ 1630 val &= ~UMAC_COMMAND_CONFIG_REG_SW_RESET; 1631 1632 /* Check loopback mode */ 1633 if (lb) 1634 val |= UMAC_COMMAND_CONFIG_REG_LOOP_ENA; 1635 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val); 1636 1637 /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame 1638 * length used by the MAC receive logic to check frames. 1639 */ 1640 REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710); 1641 bnx2x_set_xumac_nig(params, 1642 ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1); 1643 vars->mac_type = MAC_TYPE_UMAC; 1644 1645 } 1646 1647 /* Define the XMAC mode */ 1648 static void bnx2x_xmac_init(struct link_params *params, u32 max_speed) 1649 { 1650 struct bnx2x *bp = params->bp; 1651 u32 is_port4mode = bnx2x_is_4_port_mode(bp); 1652 1653 /* In 4-port mode, need to set the mode only once, so if XMAC is 1654 * already out of reset, it means the mode has already been set, 1655 * and it must not* reset the XMAC again, since it controls both 1656 * ports of the path 1657 */ 1658 1659 if (((CHIP_NUM(bp) == CHIP_NUM_57840_4_10) || 1660 (CHIP_NUM(bp) == CHIP_NUM_57840_2_20) || 1661 (CHIP_NUM(bp) == CHIP_NUM_57840_OBSOLETE)) && 1662 is_port4mode && 1663 (REG_RD(bp, MISC_REG_RESET_REG_2) & 1664 MISC_REGISTERS_RESET_REG_2_XMAC)) { 1665 DP(NETIF_MSG_LINK, 1666 "XMAC already out of reset in 4-port mode\n"); 1667 return; 1668 } 1669 1670 /* Hard reset */ 1671 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 1672 MISC_REGISTERS_RESET_REG_2_XMAC); 1673 usleep_range(1000, 2000); 1674 1675 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 1676 MISC_REGISTERS_RESET_REG_2_XMAC); 1677 if (is_port4mode) { 1678 DP(NETIF_MSG_LINK, "Init XMAC to 2 ports x 10G per path\n"); 1679 1680 /* Set the number of ports on the system side to up to 2 */ 1681 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 1); 1682 1683 /* Set the number of ports on the Warp Core to 10G */ 1684 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3); 1685 } else { 1686 /* Set the number of ports on the system side to 1 */ 1687 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 0); 1688 if (max_speed == SPEED_10000) { 1689 DP(NETIF_MSG_LINK, 1690 "Init XMAC to 10G x 1 port per path\n"); 1691 /* Set the number of ports on the Warp Core to 10G */ 1692 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3); 1693 } else { 1694 DP(NETIF_MSG_LINK, 1695 "Init XMAC to 20G x 2 ports per path\n"); 1696 /* Set the number of ports on the Warp Core to 20G */ 1697 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 1); 1698 } 1699 } 1700 /* Soft reset */ 1701 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 1702 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT); 1703 usleep_range(1000, 2000); 1704 1705 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 1706 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT); 1707 1708 } 1709 1710 static void bnx2x_set_xmac_rxtx(struct link_params *params, u8 en) 1711 { 1712 u8 port = params->port; 1713 struct bnx2x *bp = params->bp; 1714 u32 pfc_ctrl, xmac_base = (port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; 1715 u32 val; 1716 1717 if (REG_RD(bp, MISC_REG_RESET_REG_2) & 1718 MISC_REGISTERS_RESET_REG_2_XMAC) { 1719 /* Send an indication to change the state in the NIG back to XON 1720 * Clearing this bit enables the next set of this bit to get 1721 * rising edge 1722 */ 1723 pfc_ctrl = REG_RD(bp, xmac_base + XMAC_REG_PFC_CTRL_HI); 1724 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, 1725 (pfc_ctrl & ~(1<<1))); 1726 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, 1727 (pfc_ctrl | (1<<1))); 1728 DP(NETIF_MSG_LINK, "Disable XMAC on port %x\n", port); 1729 val = REG_RD(bp, xmac_base + XMAC_REG_CTRL); 1730 if (en) 1731 val |= (XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN); 1732 else 1733 val &= ~(XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN); 1734 REG_WR(bp, xmac_base + XMAC_REG_CTRL, val); 1735 } 1736 } 1737 1738 static int bnx2x_xmac_enable(struct link_params *params, 1739 struct link_vars *vars, u8 lb) 1740 { 1741 u32 val, xmac_base; 1742 struct bnx2x *bp = params->bp; 1743 DP(NETIF_MSG_LINK, "enabling XMAC\n"); 1744 1745 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; 1746 1747 bnx2x_xmac_init(params, vars->line_speed); 1748 1749 /* This register determines on which events the MAC will assert 1750 * error on the i/f to the NIG along w/ EOP. 1751 */ 1752 1753 /* This register tells the NIG whether to send traffic to UMAC 1754 * or XMAC 1755 */ 1756 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 0); 1757 1758 /* When XMAC is in XLGMII mode, disable sending idles for fault 1759 * detection. 1760 */ 1761 if (!(params->phy[INT_PHY].flags & FLAGS_TX_ERROR_CHECK)) { 1762 REG_WR(bp, xmac_base + XMAC_REG_RX_LSS_CTRL, 1763 (XMAC_RX_LSS_CTRL_REG_LOCAL_FAULT_DISABLE | 1764 XMAC_RX_LSS_CTRL_REG_REMOTE_FAULT_DISABLE)); 1765 REG_WR(bp, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0); 1766 REG_WR(bp, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 1767 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS | 1768 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS); 1769 } 1770 /* Set Max packet size */ 1771 REG_WR(bp, xmac_base + XMAC_REG_RX_MAX_SIZE, 0x2710); 1772 1773 /* CRC append for Tx packets */ 1774 REG_WR(bp, xmac_base + XMAC_REG_TX_CTRL, 0xC800); 1775 1776 /* update PFC */ 1777 bnx2x_update_pfc_xmac(params, vars, 0); 1778 1779 if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) { 1780 DP(NETIF_MSG_LINK, "Setting XMAC for EEE\n"); 1781 REG_WR(bp, xmac_base + XMAC_REG_EEE_TIMERS_HI, 0x1380008); 1782 REG_WR(bp, xmac_base + XMAC_REG_EEE_CTRL, 0x1); 1783 } else { 1784 REG_WR(bp, xmac_base + XMAC_REG_EEE_CTRL, 0x0); 1785 } 1786 1787 /* Enable TX and RX */ 1788 val = XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN; 1789 1790 /* Set MAC in XLGMII mode for dual-mode */ 1791 if ((vars->line_speed == SPEED_20000) && 1792 (params->phy[INT_PHY].supported & 1793 SUPPORTED_20000baseKR2_Full)) 1794 val |= XMAC_CTRL_REG_XLGMII_ALIGN_ENB; 1795 1796 /* Check loopback mode */ 1797 if (lb) 1798 val |= XMAC_CTRL_REG_LINE_LOCAL_LPBK; 1799 REG_WR(bp, xmac_base + XMAC_REG_CTRL, val); 1800 bnx2x_set_xumac_nig(params, 1801 ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1); 1802 1803 vars->mac_type = MAC_TYPE_XMAC; 1804 1805 return 0; 1806 } 1807 1808 static int bnx2x_emac_enable(struct link_params *params, 1809 struct link_vars *vars, u8 lb) 1810 { 1811 struct bnx2x *bp = params->bp; 1812 u8 port = params->port; 1813 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; 1814 u32 val; 1815 1816 DP(NETIF_MSG_LINK, "enabling EMAC\n"); 1817 1818 /* Disable BMAC */ 1819 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 1820 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); 1821 1822 /* enable emac and not bmac */ 1823 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 1); 1824 1825 /* ASIC */ 1826 if (vars->phy_flags & PHY_XGXS_FLAG) { 1827 u32 ser_lane = ((params->lane_config & 1828 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >> 1829 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT); 1830 1831 DP(NETIF_MSG_LINK, "XGXS\n"); 1832 /* select the master lanes (out of 0-3) */ 1833 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, ser_lane); 1834 /* select XGXS */ 1835 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1); 1836 1837 } else { /* SerDes */ 1838 DP(NETIF_MSG_LINK, "SerDes\n"); 1839 /* select SerDes */ 1840 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0); 1841 } 1842 1843 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_RX_MODE, 1844 EMAC_RX_MODE_RESET); 1845 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE, 1846 EMAC_TX_MODE_RESET); 1847 1848 /* pause enable/disable */ 1849 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_RX_MODE, 1850 EMAC_RX_MODE_FLOW_EN); 1851 1852 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_TX_MODE, 1853 (EMAC_TX_MODE_EXT_PAUSE_EN | 1854 EMAC_TX_MODE_FLOW_EN)); 1855 if (!(params->feature_config_flags & 1856 FEATURE_CONFIG_PFC_ENABLED)) { 1857 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX) 1858 bnx2x_bits_en(bp, emac_base + 1859 EMAC_REG_EMAC_RX_MODE, 1860 EMAC_RX_MODE_FLOW_EN); 1861 1862 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) 1863 bnx2x_bits_en(bp, emac_base + 1864 EMAC_REG_EMAC_TX_MODE, 1865 (EMAC_TX_MODE_EXT_PAUSE_EN | 1866 EMAC_TX_MODE_FLOW_EN)); 1867 } else 1868 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE, 1869 EMAC_TX_MODE_FLOW_EN); 1870 1871 /* KEEP_VLAN_TAG, promiscuous */ 1872 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE); 1873 val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS; 1874 1875 /* Setting this bit causes MAC control frames (except for pause 1876 * frames) to be passed on for processing. This setting has no 1877 * affect on the operation of the pause frames. This bit effects 1878 * all packets regardless of RX Parser packet sorting logic. 1879 * Turn the PFC off to make sure we are in Xon state before 1880 * enabling it. 1881 */ 1882 EMAC_WR(bp, EMAC_REG_RX_PFC_MODE, 0); 1883 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) { 1884 DP(NETIF_MSG_LINK, "PFC is enabled\n"); 1885 /* Enable PFC again */ 1886 EMAC_WR(bp, EMAC_REG_RX_PFC_MODE, 1887 EMAC_REG_RX_PFC_MODE_RX_EN | 1888 EMAC_REG_RX_PFC_MODE_TX_EN | 1889 EMAC_REG_RX_PFC_MODE_PRIORITIES); 1890 1891 EMAC_WR(bp, EMAC_REG_RX_PFC_PARAM, 1892 ((0x0101 << 1893 EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT) | 1894 (0x00ff << 1895 EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT))); 1896 val |= EMAC_RX_MODE_KEEP_MAC_CONTROL; 1897 } 1898 EMAC_WR(bp, EMAC_REG_EMAC_RX_MODE, val); 1899 1900 /* Set Loopback */ 1901 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE); 1902 if (lb) 1903 val |= 0x810; 1904 else 1905 val &= ~0x810; 1906 EMAC_WR(bp, EMAC_REG_EMAC_MODE, val); 1907 1908 /* Enable emac */ 1909 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 1); 1910 1911 /* Enable emac for jumbo packets */ 1912 EMAC_WR(bp, EMAC_REG_EMAC_RX_MTU_SIZE, 1913 (EMAC_RX_MTU_SIZE_JUMBO_ENA | 1914 (ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD))); 1915 1916 /* Strip CRC */ 1917 REG_WR(bp, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1); 1918 1919 /* Disable the NIG in/out to the bmac */ 1920 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x0); 1921 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0); 1922 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x0); 1923 1924 /* Enable the NIG in/out to the emac */ 1925 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x1); 1926 val = 0; 1927 if ((params->feature_config_flags & 1928 FEATURE_CONFIG_PFC_ENABLED) || 1929 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)) 1930 val = 1; 1931 1932 REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val); 1933 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1); 1934 1935 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x0); 1936 1937 vars->mac_type = MAC_TYPE_EMAC; 1938 return 0; 1939 } 1940 1941 static void bnx2x_update_pfc_bmac1(struct link_params *params, 1942 struct link_vars *vars) 1943 { 1944 u32 wb_data[2]; 1945 struct bnx2x *bp = params->bp; 1946 u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM : 1947 NIG_REG_INGRESS_BMAC0_MEM; 1948 1949 u32 val = 0x14; 1950 if ((!(params->feature_config_flags & 1951 FEATURE_CONFIG_PFC_ENABLED)) && 1952 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)) 1953 /* Enable BigMAC to react on received Pause packets */ 1954 val |= (1<<5); 1955 wb_data[0] = val; 1956 wb_data[1] = 0; 1957 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_CONTROL, wb_data, 2); 1958 1959 /* TX control */ 1960 val = 0xc0; 1961 if (!(params->feature_config_flags & 1962 FEATURE_CONFIG_PFC_ENABLED) && 1963 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)) 1964 val |= 0x800000; 1965 wb_data[0] = val; 1966 wb_data[1] = 0; 1967 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_CONTROL, wb_data, 2); 1968 } 1969 1970 static void bnx2x_update_pfc_bmac2(struct link_params *params, 1971 struct link_vars *vars, 1972 u8 is_lb) 1973 { 1974 /* Set rx control: Strip CRC and enable BigMAC to relay 1975 * control packets to the system as well 1976 */ 1977 u32 wb_data[2]; 1978 struct bnx2x *bp = params->bp; 1979 u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM : 1980 NIG_REG_INGRESS_BMAC0_MEM; 1981 u32 val = 0x14; 1982 1983 if ((!(params->feature_config_flags & 1984 FEATURE_CONFIG_PFC_ENABLED)) && 1985 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)) 1986 /* Enable BigMAC to react on received Pause packets */ 1987 val |= (1<<5); 1988 wb_data[0] = val; 1989 wb_data[1] = 0; 1990 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_CONTROL, wb_data, 2); 1991 udelay(30); 1992 1993 /* Tx control */ 1994 val = 0xc0; 1995 if (!(params->feature_config_flags & 1996 FEATURE_CONFIG_PFC_ENABLED) && 1997 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)) 1998 val |= 0x800000; 1999 wb_data[0] = val; 2000 wb_data[1] = 0; 2001 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_CONTROL, wb_data, 2); 2002 2003 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) { 2004 DP(NETIF_MSG_LINK, "PFC is enabled\n"); 2005 /* Enable PFC RX & TX & STATS and set 8 COS */ 2006 wb_data[0] = 0x0; 2007 wb_data[0] |= (1<<0); /* RX */ 2008 wb_data[0] |= (1<<1); /* TX */ 2009 wb_data[0] |= (1<<2); /* Force initial Xon */ 2010 wb_data[0] |= (1<<3); /* 8 cos */ 2011 wb_data[0] |= (1<<5); /* STATS */ 2012 wb_data[1] = 0; 2013 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, 2014 wb_data, 2); 2015 /* Clear the force Xon */ 2016 wb_data[0] &= ~(1<<2); 2017 } else { 2018 DP(NETIF_MSG_LINK, "PFC is disabled\n"); 2019 /* Disable PFC RX & TX & STATS and set 8 COS */ 2020 wb_data[0] = 0x8; 2021 wb_data[1] = 0; 2022 } 2023 2024 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, wb_data, 2); 2025 2026 /* Set Time (based unit is 512 bit time) between automatic 2027 * re-sending of PP packets amd enable automatic re-send of 2028 * Per-Priroity Packet as long as pp_gen is asserted and 2029 * pp_disable is low. 2030 */ 2031 val = 0x8000; 2032 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) 2033 val |= (1<<16); /* enable automatic re-send */ 2034 2035 wb_data[0] = val; 2036 wb_data[1] = 0; 2037 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_PAUSE_CONTROL, 2038 wb_data, 2); 2039 2040 /* mac control */ 2041 val = 0x3; /* Enable RX and TX */ 2042 if (is_lb) { 2043 val |= 0x4; /* Local loopback */ 2044 DP(NETIF_MSG_LINK, "enable bmac loopback\n"); 2045 } 2046 /* When PFC enabled, Pass pause frames towards the NIG. */ 2047 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) 2048 val |= ((1<<6)|(1<<5)); 2049 2050 wb_data[0] = val; 2051 wb_data[1] = 0; 2052 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2); 2053 } 2054 2055 /****************************************************************************** 2056 * Description: 2057 * This function is needed because NIG ARB_CREDIT_WEIGHT_X are 2058 * not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable. 2059 ******************************************************************************/ 2060 static int bnx2x_pfc_nig_rx_priority_mask(struct bnx2x *bp, 2061 u8 cos_entry, 2062 u32 priority_mask, u8 port) 2063 { 2064 u32 nig_reg_rx_priority_mask_add = 0; 2065 2066 switch (cos_entry) { 2067 case 0: 2068 nig_reg_rx_priority_mask_add = (port) ? 2069 NIG_REG_P1_RX_COS0_PRIORITY_MASK : 2070 NIG_REG_P0_RX_COS0_PRIORITY_MASK; 2071 break; 2072 case 1: 2073 nig_reg_rx_priority_mask_add = (port) ? 2074 NIG_REG_P1_RX_COS1_PRIORITY_MASK : 2075 NIG_REG_P0_RX_COS1_PRIORITY_MASK; 2076 break; 2077 case 2: 2078 nig_reg_rx_priority_mask_add = (port) ? 2079 NIG_REG_P1_RX_COS2_PRIORITY_MASK : 2080 NIG_REG_P0_RX_COS2_PRIORITY_MASK; 2081 break; 2082 case 3: 2083 if (port) 2084 return -EINVAL; 2085 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS3_PRIORITY_MASK; 2086 break; 2087 case 4: 2088 if (port) 2089 return -EINVAL; 2090 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS4_PRIORITY_MASK; 2091 break; 2092 case 5: 2093 if (port) 2094 return -EINVAL; 2095 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS5_PRIORITY_MASK; 2096 break; 2097 } 2098 2099 REG_WR(bp, nig_reg_rx_priority_mask_add, priority_mask); 2100 2101 return 0; 2102 } 2103 static void bnx2x_update_mng(struct link_params *params, u32 link_status) 2104 { 2105 struct bnx2x *bp = params->bp; 2106 2107 REG_WR(bp, params->shmem_base + 2108 offsetof(struct shmem_region, 2109 port_mb[params->port].link_status), link_status); 2110 } 2111 2112 static void bnx2x_update_link_attr(struct link_params *params, u32 link_attr) 2113 { 2114 struct bnx2x *bp = params->bp; 2115 2116 if (SHMEM2_HAS(bp, link_attr_sync)) 2117 REG_WR(bp, params->shmem2_base + 2118 offsetof(struct shmem2_region, 2119 link_attr_sync[params->port]), link_attr); 2120 } 2121 2122 static void bnx2x_update_pfc_nig(struct link_params *params, 2123 struct link_vars *vars, 2124 struct bnx2x_nig_brb_pfc_port_params *nig_params) 2125 { 2126 u32 xcm_mask = 0, ppp_enable = 0, pause_enable = 0, llfc_out_en = 0; 2127 u32 llfc_enable = 0, xcm_out_en = 0, hwpfc_enable = 0; 2128 u32 pkt_priority_to_cos = 0; 2129 struct bnx2x *bp = params->bp; 2130 u8 port = params->port; 2131 2132 int set_pfc = params->feature_config_flags & 2133 FEATURE_CONFIG_PFC_ENABLED; 2134 DP(NETIF_MSG_LINK, "updating pfc nig parameters\n"); 2135 2136 /* When NIG_LLH0_XCM_MASK_REG_LLHX_XCM_MASK_BCN bit is set 2137 * MAC control frames (that are not pause packets) 2138 * will be forwarded to the XCM. 2139 */ 2140 xcm_mask = REG_RD(bp, port ? NIG_REG_LLH1_XCM_MASK : 2141 NIG_REG_LLH0_XCM_MASK); 2142 /* NIG params will override non PFC params, since it's possible to 2143 * do transition from PFC to SAFC 2144 */ 2145 if (set_pfc) { 2146 pause_enable = 0; 2147 llfc_out_en = 0; 2148 llfc_enable = 0; 2149 if (CHIP_IS_E3(bp)) 2150 ppp_enable = 0; 2151 else 2152 ppp_enable = 1; 2153 xcm_mask &= ~(port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN : 2154 NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN); 2155 xcm_out_en = 0; 2156 hwpfc_enable = 1; 2157 } else { 2158 if (nig_params) { 2159 llfc_out_en = nig_params->llfc_out_en; 2160 llfc_enable = nig_params->llfc_enable; 2161 pause_enable = nig_params->pause_enable; 2162 } else /* Default non PFC mode - PAUSE */ 2163 pause_enable = 1; 2164 2165 xcm_mask |= (port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN : 2166 NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN); 2167 xcm_out_en = 1; 2168 } 2169 2170 if (CHIP_IS_E3(bp)) 2171 REG_WR(bp, port ? NIG_REG_BRB1_PAUSE_IN_EN : 2172 NIG_REG_BRB0_PAUSE_IN_EN, pause_enable); 2173 REG_WR(bp, port ? NIG_REG_LLFC_OUT_EN_1 : 2174 NIG_REG_LLFC_OUT_EN_0, llfc_out_en); 2175 REG_WR(bp, port ? NIG_REG_LLFC_ENABLE_1 : 2176 NIG_REG_LLFC_ENABLE_0, llfc_enable); 2177 REG_WR(bp, port ? NIG_REG_PAUSE_ENABLE_1 : 2178 NIG_REG_PAUSE_ENABLE_0, pause_enable); 2179 2180 REG_WR(bp, port ? NIG_REG_PPP_ENABLE_1 : 2181 NIG_REG_PPP_ENABLE_0, ppp_enable); 2182 2183 REG_WR(bp, port ? NIG_REG_LLH1_XCM_MASK : 2184 NIG_REG_LLH0_XCM_MASK, xcm_mask); 2185 2186 REG_WR(bp, port ? NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 : 2187 NIG_REG_LLFC_EGRESS_SRC_ENABLE_0, 0x7); 2188 2189 /* Output enable for RX_XCM # IF */ 2190 REG_WR(bp, port ? NIG_REG_XCM1_OUT_EN : 2191 NIG_REG_XCM0_OUT_EN, xcm_out_en); 2192 2193 /* HW PFC TX enable */ 2194 REG_WR(bp, port ? NIG_REG_P1_HWPFC_ENABLE : 2195 NIG_REG_P0_HWPFC_ENABLE, hwpfc_enable); 2196 2197 if (nig_params) { 2198 u8 i = 0; 2199 pkt_priority_to_cos = nig_params->pkt_priority_to_cos; 2200 2201 for (i = 0; i < nig_params->num_of_rx_cos_priority_mask; i++) 2202 bnx2x_pfc_nig_rx_priority_mask(bp, i, 2203 nig_params->rx_cos_priority_mask[i], port); 2204 2205 REG_WR(bp, port ? NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 : 2206 NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0, 2207 nig_params->llfc_high_priority_classes); 2208 2209 REG_WR(bp, port ? NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 : 2210 NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0, 2211 nig_params->llfc_low_priority_classes); 2212 } 2213 REG_WR(bp, port ? NIG_REG_P1_PKT_PRIORITY_TO_COS : 2214 NIG_REG_P0_PKT_PRIORITY_TO_COS, 2215 pkt_priority_to_cos); 2216 } 2217 2218 int bnx2x_update_pfc(struct link_params *params, 2219 struct link_vars *vars, 2220 struct bnx2x_nig_brb_pfc_port_params *pfc_params) 2221 { 2222 /* The PFC and pause are orthogonal to one another, meaning when 2223 * PFC is enabled, the pause are disabled, and when PFC is 2224 * disabled, pause are set according to the pause result. 2225 */ 2226 u32 val; 2227 struct bnx2x *bp = params->bp; 2228 u8 bmac_loopback = (params->loopback_mode == LOOPBACK_BMAC); 2229 2230 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) 2231 vars->link_status |= LINK_STATUS_PFC_ENABLED; 2232 else 2233 vars->link_status &= ~LINK_STATUS_PFC_ENABLED; 2234 2235 bnx2x_update_mng(params, vars->link_status); 2236 2237 /* Update NIG params */ 2238 bnx2x_update_pfc_nig(params, vars, pfc_params); 2239 2240 if (!vars->link_up) 2241 return 0; 2242 2243 DP(NETIF_MSG_LINK, "About to update PFC in BMAC\n"); 2244 2245 if (CHIP_IS_E3(bp)) { 2246 if (vars->mac_type == MAC_TYPE_XMAC) 2247 bnx2x_update_pfc_xmac(params, vars, 0); 2248 } else { 2249 val = REG_RD(bp, MISC_REG_RESET_REG_2); 2250 if ((val & 2251 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port)) 2252 == 0) { 2253 DP(NETIF_MSG_LINK, "About to update PFC in EMAC\n"); 2254 bnx2x_emac_enable(params, vars, 0); 2255 return 0; 2256 } 2257 if (CHIP_IS_E2(bp)) 2258 bnx2x_update_pfc_bmac2(params, vars, bmac_loopback); 2259 else 2260 bnx2x_update_pfc_bmac1(params, vars); 2261 2262 val = 0; 2263 if ((params->feature_config_flags & 2264 FEATURE_CONFIG_PFC_ENABLED) || 2265 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)) 2266 val = 1; 2267 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port*4, val); 2268 } 2269 return 0; 2270 } 2271 2272 static int bnx2x_bmac1_enable(struct link_params *params, 2273 struct link_vars *vars, 2274 u8 is_lb) 2275 { 2276 struct bnx2x *bp = params->bp; 2277 u8 port = params->port; 2278 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM : 2279 NIG_REG_INGRESS_BMAC0_MEM; 2280 u32 wb_data[2]; 2281 u32 val; 2282 2283 DP(NETIF_MSG_LINK, "Enabling BigMAC1\n"); 2284 2285 /* XGXS control */ 2286 wb_data[0] = 0x3c; 2287 wb_data[1] = 0; 2288 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_XGXS_CONTROL, 2289 wb_data, 2); 2290 2291 /* TX MAC SA */ 2292 wb_data[0] = ((params->mac_addr[2] << 24) | 2293 (params->mac_addr[3] << 16) | 2294 (params->mac_addr[4] << 8) | 2295 params->mac_addr[5]); 2296 wb_data[1] = ((params->mac_addr[0] << 8) | 2297 params->mac_addr[1]); 2298 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR, wb_data, 2); 2299 2300 /* MAC control */ 2301 val = 0x3; 2302 if (is_lb) { 2303 val |= 0x4; 2304 DP(NETIF_MSG_LINK, "enable bmac loopback\n"); 2305 } 2306 wb_data[0] = val; 2307 wb_data[1] = 0; 2308 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL, wb_data, 2); 2309 2310 /* Set rx mtu */ 2311 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD; 2312 wb_data[1] = 0; 2313 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE, wb_data, 2); 2314 2315 bnx2x_update_pfc_bmac1(params, vars); 2316 2317 /* Set tx mtu */ 2318 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD; 2319 wb_data[1] = 0; 2320 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE, wb_data, 2); 2321 2322 /* Set cnt max size */ 2323 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD; 2324 wb_data[1] = 0; 2325 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE, wb_data, 2); 2326 2327 /* Configure SAFC */ 2328 wb_data[0] = 0x1000200; 2329 wb_data[1] = 0; 2330 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS, 2331 wb_data, 2); 2332 2333 return 0; 2334 } 2335 2336 static int bnx2x_bmac2_enable(struct link_params *params, 2337 struct link_vars *vars, 2338 u8 is_lb) 2339 { 2340 struct bnx2x *bp = params->bp; 2341 u8 port = params->port; 2342 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM : 2343 NIG_REG_INGRESS_BMAC0_MEM; 2344 u32 wb_data[2]; 2345 2346 DP(NETIF_MSG_LINK, "Enabling BigMAC2\n"); 2347 2348 wb_data[0] = 0; 2349 wb_data[1] = 0; 2350 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2); 2351 udelay(30); 2352 2353 /* XGXS control: Reset phy HW, MDIO registers, PHY PLL and BMAC */ 2354 wb_data[0] = 0x3c; 2355 wb_data[1] = 0; 2356 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_XGXS_CONTROL, 2357 wb_data, 2); 2358 2359 udelay(30); 2360 2361 /* TX MAC SA */ 2362 wb_data[0] = ((params->mac_addr[2] << 24) | 2363 (params->mac_addr[3] << 16) | 2364 (params->mac_addr[4] << 8) | 2365 params->mac_addr[5]); 2366 wb_data[1] = ((params->mac_addr[0] << 8) | 2367 params->mac_addr[1]); 2368 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_SOURCE_ADDR, 2369 wb_data, 2); 2370 2371 udelay(30); 2372 2373 /* Configure SAFC */ 2374 wb_data[0] = 0x1000200; 2375 wb_data[1] = 0; 2376 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS, 2377 wb_data, 2); 2378 udelay(30); 2379 2380 /* Set RX MTU */ 2381 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD; 2382 wb_data[1] = 0; 2383 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_MAX_SIZE, wb_data, 2); 2384 udelay(30); 2385 2386 /* Set TX MTU */ 2387 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD; 2388 wb_data[1] = 0; 2389 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_MAX_SIZE, wb_data, 2); 2390 udelay(30); 2391 /* Set cnt max size */ 2392 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD - 2; 2393 wb_data[1] = 0; 2394 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_CNT_MAX_SIZE, wb_data, 2); 2395 udelay(30); 2396 bnx2x_update_pfc_bmac2(params, vars, is_lb); 2397 2398 return 0; 2399 } 2400 2401 static int bnx2x_bmac_enable(struct link_params *params, 2402 struct link_vars *vars, 2403 u8 is_lb, u8 reset_bmac) 2404 { 2405 int rc = 0; 2406 u8 port = params->port; 2407 struct bnx2x *bp = params->bp; 2408 u32 val; 2409 /* Reset and unreset the BigMac */ 2410 if (reset_bmac) { 2411 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 2412 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); 2413 usleep_range(1000, 2000); 2414 } 2415 2416 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 2417 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); 2418 2419 /* Enable access for bmac registers */ 2420 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1); 2421 2422 /* Enable BMAC according to BMAC type*/ 2423 if (CHIP_IS_E2(bp)) 2424 rc = bnx2x_bmac2_enable(params, vars, is_lb); 2425 else 2426 rc = bnx2x_bmac1_enable(params, vars, is_lb); 2427 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1); 2428 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0); 2429 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0); 2430 val = 0; 2431 if ((params->feature_config_flags & 2432 FEATURE_CONFIG_PFC_ENABLED) || 2433 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)) 2434 val = 1; 2435 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val); 2436 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0); 2437 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x0); 2438 REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0); 2439 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x1); 2440 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x1); 2441 2442 vars->mac_type = MAC_TYPE_BMAC; 2443 return rc; 2444 } 2445 2446 static void bnx2x_set_bmac_rx(struct bnx2x *bp, u32 chip_id, u8 port, u8 en) 2447 { 2448 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM : 2449 NIG_REG_INGRESS_BMAC0_MEM; 2450 u32 wb_data[2]; 2451 u32 nig_bmac_enable = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4); 2452 2453 if (CHIP_IS_E2(bp)) 2454 bmac_addr += BIGMAC2_REGISTER_BMAC_CONTROL; 2455 else 2456 bmac_addr += BIGMAC_REGISTER_BMAC_CONTROL; 2457 /* Only if the bmac is out of reset */ 2458 if (REG_RD(bp, MISC_REG_RESET_REG_2) & 2459 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) && 2460 nig_bmac_enable) { 2461 /* Clear Rx Enable bit in BMAC_CONTROL register */ 2462 REG_RD_DMAE(bp, bmac_addr, wb_data, 2); 2463 if (en) 2464 wb_data[0] |= BMAC_CONTROL_RX_ENABLE; 2465 else 2466 wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE; 2467 REG_WR_DMAE(bp, bmac_addr, wb_data, 2); 2468 usleep_range(1000, 2000); 2469 } 2470 } 2471 2472 static int bnx2x_pbf_update(struct link_params *params, u32 flow_ctrl, 2473 u32 line_speed) 2474 { 2475 struct bnx2x *bp = params->bp; 2476 u8 port = params->port; 2477 u32 init_crd, crd; 2478 u32 count = 1000; 2479 2480 /* Disable port */ 2481 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1); 2482 2483 /* Wait for init credit */ 2484 init_crd = REG_RD(bp, PBF_REG_P0_INIT_CRD + port*4); 2485 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8); 2486 DP(NETIF_MSG_LINK, "init_crd 0x%x crd 0x%x\n", init_crd, crd); 2487 2488 while ((init_crd != crd) && count) { 2489 usleep_range(5000, 10000); 2490 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8); 2491 count--; 2492 } 2493 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8); 2494 if (init_crd != crd) { 2495 DP(NETIF_MSG_LINK, "BUG! init_crd 0x%x != crd 0x%x\n", 2496 init_crd, crd); 2497 return -EINVAL; 2498 } 2499 2500 if (flow_ctrl & BNX2X_FLOW_CTRL_RX || 2501 line_speed == SPEED_10 || 2502 line_speed == SPEED_100 || 2503 line_speed == SPEED_1000 || 2504 line_speed == SPEED_2500) { 2505 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 1); 2506 /* Update threshold */ 2507 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, 0); 2508 /* Update init credit */ 2509 init_crd = 778; /* (800-18-4) */ 2510 2511 } else { 2512 u32 thresh = (ETH_MAX_JUMBO_PACKET_SIZE + 2513 ETH_OVREHEAD)/16; 2514 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0); 2515 /* Update threshold */ 2516 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, thresh); 2517 /* Update init credit */ 2518 switch (line_speed) { 2519 case SPEED_10000: 2520 init_crd = thresh + 553 - 22; 2521 break; 2522 default: 2523 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n", 2524 line_speed); 2525 return -EINVAL; 2526 } 2527 } 2528 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, init_crd); 2529 DP(NETIF_MSG_LINK, "PBF updated to speed %d credit %d\n", 2530 line_speed, init_crd); 2531 2532 /* Probe the credit changes */ 2533 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x1); 2534 usleep_range(5000, 10000); 2535 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x0); 2536 2537 /* Enable port */ 2538 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0); 2539 return 0; 2540 } 2541 2542 /** 2543 * bnx2x_get_emac_base - retrive emac base address 2544 * 2545 * @bp: driver handle 2546 * @mdc_mdio_access: access type 2547 * @port: port id 2548 * 2549 * This function selects the MDC/MDIO access (through emac0 or 2550 * emac1) depend on the mdc_mdio_access, port, port swapped. Each 2551 * phy has a default access mode, which could also be overridden 2552 * by nvram configuration. This parameter, whether this is the 2553 * default phy configuration, or the nvram overrun 2554 * configuration, is passed here as mdc_mdio_access and selects 2555 * the emac_base for the CL45 read/writes operations 2556 */ 2557 static u32 bnx2x_get_emac_base(struct bnx2x *bp, 2558 u32 mdc_mdio_access, u8 port) 2559 { 2560 u32 emac_base = 0; 2561 switch (mdc_mdio_access) { 2562 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE: 2563 break; 2564 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0: 2565 if (REG_RD(bp, NIG_REG_PORT_SWAP)) 2566 emac_base = GRCBASE_EMAC1; 2567 else 2568 emac_base = GRCBASE_EMAC0; 2569 break; 2570 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1: 2571 if (REG_RD(bp, NIG_REG_PORT_SWAP)) 2572 emac_base = GRCBASE_EMAC0; 2573 else 2574 emac_base = GRCBASE_EMAC1; 2575 break; 2576 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH: 2577 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0; 2578 break; 2579 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED: 2580 emac_base = (port) ? GRCBASE_EMAC0 : GRCBASE_EMAC1; 2581 break; 2582 default: 2583 break; 2584 } 2585 return emac_base; 2586 2587 } 2588 2589 /******************************************************************/ 2590 /* CL22 access functions */ 2591 /******************************************************************/ 2592 static int bnx2x_cl22_write(struct bnx2x *bp, 2593 struct bnx2x_phy *phy, 2594 u16 reg, u16 val) 2595 { 2596 u32 tmp, mode; 2597 u8 i; 2598 int rc = 0; 2599 /* Switch to CL22 */ 2600 mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE); 2601 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, 2602 mode & ~EMAC_MDIO_MODE_CLAUSE_45); 2603 2604 /* Address */ 2605 tmp = ((phy->addr << 21) | (reg << 16) | val | 2606 EMAC_MDIO_COMM_COMMAND_WRITE_22 | 2607 EMAC_MDIO_COMM_START_BUSY); 2608 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); 2609 2610 for (i = 0; i < 50; i++) { 2611 udelay(10); 2612 2613 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); 2614 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) { 2615 udelay(5); 2616 break; 2617 } 2618 } 2619 if (tmp & EMAC_MDIO_COMM_START_BUSY) { 2620 DP(NETIF_MSG_LINK, "write phy register failed\n"); 2621 rc = -EFAULT; 2622 } 2623 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode); 2624 return rc; 2625 } 2626 2627 static int bnx2x_cl22_read(struct bnx2x *bp, 2628 struct bnx2x_phy *phy, 2629 u16 reg, u16 *ret_val) 2630 { 2631 u32 val, mode; 2632 u16 i; 2633 int rc = 0; 2634 2635 /* Switch to CL22 */ 2636 mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE); 2637 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, 2638 mode & ~EMAC_MDIO_MODE_CLAUSE_45); 2639 2640 /* Address */ 2641 val = ((phy->addr << 21) | (reg << 16) | 2642 EMAC_MDIO_COMM_COMMAND_READ_22 | 2643 EMAC_MDIO_COMM_START_BUSY); 2644 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); 2645 2646 for (i = 0; i < 50; i++) { 2647 udelay(10); 2648 2649 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); 2650 if (!(val & EMAC_MDIO_COMM_START_BUSY)) { 2651 *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA); 2652 udelay(5); 2653 break; 2654 } 2655 } 2656 if (val & EMAC_MDIO_COMM_START_BUSY) { 2657 DP(NETIF_MSG_LINK, "read phy register failed\n"); 2658 2659 *ret_val = 0; 2660 rc = -EFAULT; 2661 } 2662 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode); 2663 return rc; 2664 } 2665 2666 /******************************************************************/ 2667 /* CL45 access functions */ 2668 /******************************************************************/ 2669 static int bnx2x_cl45_read(struct bnx2x *bp, struct bnx2x_phy *phy, 2670 u8 devad, u16 reg, u16 *ret_val) 2671 { 2672 u32 val; 2673 u16 i; 2674 int rc = 0; 2675 u32 chip_id; 2676 if (phy->flags & FLAGS_MDC_MDIO_WA_G) { 2677 chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) | 2678 ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12); 2679 bnx2x_set_mdio_clk(bp, chip_id, phy->mdio_ctrl); 2680 } 2681 2682 if (phy->flags & FLAGS_MDC_MDIO_WA_B0) 2683 bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, 2684 EMAC_MDIO_STATUS_10MB); 2685 /* Address */ 2686 val = ((phy->addr << 21) | (devad << 16) | reg | 2687 EMAC_MDIO_COMM_COMMAND_ADDRESS | 2688 EMAC_MDIO_COMM_START_BUSY); 2689 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); 2690 2691 for (i = 0; i < 50; i++) { 2692 udelay(10); 2693 2694 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); 2695 if (!(val & EMAC_MDIO_COMM_START_BUSY)) { 2696 udelay(5); 2697 break; 2698 } 2699 } 2700 if (val & EMAC_MDIO_COMM_START_BUSY) { 2701 DP(NETIF_MSG_LINK, "read phy register failed\n"); 2702 netdev_err(bp->dev, "MDC/MDIO access timeout\n"); 2703 *ret_val = 0; 2704 rc = -EFAULT; 2705 } else { 2706 /* Data */ 2707 val = ((phy->addr << 21) | (devad << 16) | 2708 EMAC_MDIO_COMM_COMMAND_READ_45 | 2709 EMAC_MDIO_COMM_START_BUSY); 2710 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); 2711 2712 for (i = 0; i < 50; i++) { 2713 udelay(10); 2714 2715 val = REG_RD(bp, phy->mdio_ctrl + 2716 EMAC_REG_EMAC_MDIO_COMM); 2717 if (!(val & EMAC_MDIO_COMM_START_BUSY)) { 2718 *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA); 2719 break; 2720 } 2721 } 2722 if (val & EMAC_MDIO_COMM_START_BUSY) { 2723 DP(NETIF_MSG_LINK, "read phy register failed\n"); 2724 netdev_err(bp->dev, "MDC/MDIO access timeout\n"); 2725 *ret_val = 0; 2726 rc = -EFAULT; 2727 } 2728 } 2729 /* Work around for E3 A0 */ 2730 if (phy->flags & FLAGS_MDC_MDIO_WA) { 2731 phy->flags ^= FLAGS_DUMMY_READ; 2732 if (phy->flags & FLAGS_DUMMY_READ) { 2733 u16 temp_val; 2734 bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val); 2735 } 2736 } 2737 2738 if (phy->flags & FLAGS_MDC_MDIO_WA_B0) 2739 bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, 2740 EMAC_MDIO_STATUS_10MB); 2741 return rc; 2742 } 2743 2744 static int bnx2x_cl45_write(struct bnx2x *bp, struct bnx2x_phy *phy, 2745 u8 devad, u16 reg, u16 val) 2746 { 2747 u32 tmp; 2748 u8 i; 2749 int rc = 0; 2750 u32 chip_id; 2751 if (phy->flags & FLAGS_MDC_MDIO_WA_G) { 2752 chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) | 2753 ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12); 2754 bnx2x_set_mdio_clk(bp, chip_id, phy->mdio_ctrl); 2755 } 2756 2757 if (phy->flags & FLAGS_MDC_MDIO_WA_B0) 2758 bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, 2759 EMAC_MDIO_STATUS_10MB); 2760 2761 /* Address */ 2762 tmp = ((phy->addr << 21) | (devad << 16) | reg | 2763 EMAC_MDIO_COMM_COMMAND_ADDRESS | 2764 EMAC_MDIO_COMM_START_BUSY); 2765 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); 2766 2767 for (i = 0; i < 50; i++) { 2768 udelay(10); 2769 2770 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); 2771 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) { 2772 udelay(5); 2773 break; 2774 } 2775 } 2776 if (tmp & EMAC_MDIO_COMM_START_BUSY) { 2777 DP(NETIF_MSG_LINK, "write phy register failed\n"); 2778 netdev_err(bp->dev, "MDC/MDIO access timeout\n"); 2779 rc = -EFAULT; 2780 } else { 2781 /* Data */ 2782 tmp = ((phy->addr << 21) | (devad << 16) | val | 2783 EMAC_MDIO_COMM_COMMAND_WRITE_45 | 2784 EMAC_MDIO_COMM_START_BUSY); 2785 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); 2786 2787 for (i = 0; i < 50; i++) { 2788 udelay(10); 2789 2790 tmp = REG_RD(bp, phy->mdio_ctrl + 2791 EMAC_REG_EMAC_MDIO_COMM); 2792 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) { 2793 udelay(5); 2794 break; 2795 } 2796 } 2797 if (tmp & EMAC_MDIO_COMM_START_BUSY) { 2798 DP(NETIF_MSG_LINK, "write phy register failed\n"); 2799 netdev_err(bp->dev, "MDC/MDIO access timeout\n"); 2800 rc = -EFAULT; 2801 } 2802 } 2803 /* Work around for E3 A0 */ 2804 if (phy->flags & FLAGS_MDC_MDIO_WA) { 2805 phy->flags ^= FLAGS_DUMMY_READ; 2806 if (phy->flags & FLAGS_DUMMY_READ) { 2807 u16 temp_val; 2808 bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val); 2809 } 2810 } 2811 if (phy->flags & FLAGS_MDC_MDIO_WA_B0) 2812 bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, 2813 EMAC_MDIO_STATUS_10MB); 2814 return rc; 2815 } 2816 2817 /******************************************************************/ 2818 /* EEE section */ 2819 /******************************************************************/ 2820 static u8 bnx2x_eee_has_cap(struct link_params *params) 2821 { 2822 struct bnx2x *bp = params->bp; 2823 2824 if (REG_RD(bp, params->shmem2_base) <= 2825 offsetof(struct shmem2_region, eee_status[params->port])) 2826 return 0; 2827 2828 return 1; 2829 } 2830 2831 static int bnx2x_eee_nvram_to_time(u32 nvram_mode, u32 *idle_timer) 2832 { 2833 switch (nvram_mode) { 2834 case PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED: 2835 *idle_timer = EEE_MODE_NVRAM_BALANCED_TIME; 2836 break; 2837 case PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE: 2838 *idle_timer = EEE_MODE_NVRAM_AGGRESSIVE_TIME; 2839 break; 2840 case PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY: 2841 *idle_timer = EEE_MODE_NVRAM_LATENCY_TIME; 2842 break; 2843 default: 2844 *idle_timer = 0; 2845 break; 2846 } 2847 2848 return 0; 2849 } 2850 2851 static int bnx2x_eee_time_to_nvram(u32 idle_timer, u32 *nvram_mode) 2852 { 2853 switch (idle_timer) { 2854 case EEE_MODE_NVRAM_BALANCED_TIME: 2855 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED; 2856 break; 2857 case EEE_MODE_NVRAM_AGGRESSIVE_TIME: 2858 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE; 2859 break; 2860 case EEE_MODE_NVRAM_LATENCY_TIME: 2861 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY; 2862 break; 2863 default: 2864 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED; 2865 break; 2866 } 2867 2868 return 0; 2869 } 2870 2871 static u32 bnx2x_eee_calc_timer(struct link_params *params) 2872 { 2873 u32 eee_mode, eee_idle; 2874 struct bnx2x *bp = params->bp; 2875 2876 if (params->eee_mode & EEE_MODE_OVERRIDE_NVRAM) { 2877 if (params->eee_mode & EEE_MODE_OUTPUT_TIME) { 2878 /* time value in eee_mode --> used directly*/ 2879 eee_idle = params->eee_mode & EEE_MODE_TIMER_MASK; 2880 } else { 2881 /* hsi value in eee_mode --> time */ 2882 if (bnx2x_eee_nvram_to_time(params->eee_mode & 2883 EEE_MODE_NVRAM_MASK, 2884 &eee_idle)) 2885 return 0; 2886 } 2887 } else { 2888 /* hsi values in nvram --> time*/ 2889 eee_mode = ((REG_RD(bp, params->shmem_base + 2890 offsetof(struct shmem_region, dev_info. 2891 port_feature_config[params->port]. 2892 eee_power_mode)) & 2893 PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >> 2894 PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT); 2895 2896 if (bnx2x_eee_nvram_to_time(eee_mode, &eee_idle)) 2897 return 0; 2898 } 2899 2900 return eee_idle; 2901 } 2902 2903 static int bnx2x_eee_set_timers(struct link_params *params, 2904 struct link_vars *vars) 2905 { 2906 u32 eee_idle = 0, eee_mode; 2907 struct bnx2x *bp = params->bp; 2908 2909 eee_idle = bnx2x_eee_calc_timer(params); 2910 2911 if (eee_idle) { 2912 REG_WR(bp, MISC_REG_CPMU_LP_IDLE_THR_P0 + (params->port << 2), 2913 eee_idle); 2914 } else if ((params->eee_mode & EEE_MODE_ENABLE_LPI) && 2915 (params->eee_mode & EEE_MODE_OVERRIDE_NVRAM) && 2916 (params->eee_mode & EEE_MODE_OUTPUT_TIME)) { 2917 DP(NETIF_MSG_LINK, "Error: Tx LPI is enabled with timer 0\n"); 2918 return -EINVAL; 2919 } 2920 2921 vars->eee_status &= ~(SHMEM_EEE_TIMER_MASK | SHMEM_EEE_TIME_OUTPUT_BIT); 2922 if (params->eee_mode & EEE_MODE_OUTPUT_TIME) { 2923 /* eee_idle in 1u --> eee_status in 16u */ 2924 eee_idle >>= 4; 2925 vars->eee_status |= (eee_idle & SHMEM_EEE_TIMER_MASK) | 2926 SHMEM_EEE_TIME_OUTPUT_BIT; 2927 } else { 2928 if (bnx2x_eee_time_to_nvram(eee_idle, &eee_mode)) 2929 return -EINVAL; 2930 vars->eee_status |= eee_mode; 2931 } 2932 2933 return 0; 2934 } 2935 2936 static int bnx2x_eee_initial_config(struct link_params *params, 2937 struct link_vars *vars, u8 mode) 2938 { 2939 vars->eee_status |= ((u32) mode) << SHMEM_EEE_SUPPORTED_SHIFT; 2940 2941 /* Propogate params' bits --> vars (for migration exposure) */ 2942 if (params->eee_mode & EEE_MODE_ENABLE_LPI) 2943 vars->eee_status |= SHMEM_EEE_LPI_REQUESTED_BIT; 2944 else 2945 vars->eee_status &= ~SHMEM_EEE_LPI_REQUESTED_BIT; 2946 2947 if (params->eee_mode & EEE_MODE_ADV_LPI) 2948 vars->eee_status |= SHMEM_EEE_REQUESTED_BIT; 2949 else 2950 vars->eee_status &= ~SHMEM_EEE_REQUESTED_BIT; 2951 2952 return bnx2x_eee_set_timers(params, vars); 2953 } 2954 2955 static int bnx2x_eee_disable(struct bnx2x_phy *phy, 2956 struct link_params *params, 2957 struct link_vars *vars) 2958 { 2959 struct bnx2x *bp = params->bp; 2960 2961 /* Make Certain LPI is disabled */ 2962 REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2), 0); 2963 2964 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, 0x0); 2965 2966 vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK; 2967 2968 return 0; 2969 } 2970 2971 static int bnx2x_eee_advertise(struct bnx2x_phy *phy, 2972 struct link_params *params, 2973 struct link_vars *vars, u8 modes) 2974 { 2975 struct bnx2x *bp = params->bp; 2976 u16 val = 0; 2977 2978 /* Mask events preventing LPI generation */ 2979 REG_WR(bp, MISC_REG_CPMU_LP_MASK_EXT_P0 + (params->port << 2), 0xfc20); 2980 2981 if (modes & SHMEM_EEE_10G_ADV) { 2982 DP(NETIF_MSG_LINK, "Advertise 10GBase-T EEE\n"); 2983 val |= 0x8; 2984 } 2985 if (modes & SHMEM_EEE_1G_ADV) { 2986 DP(NETIF_MSG_LINK, "Advertise 1GBase-T EEE\n"); 2987 val |= 0x4; 2988 } 2989 2990 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, val); 2991 2992 vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK; 2993 vars->eee_status |= (modes << SHMEM_EEE_ADV_STATUS_SHIFT); 2994 2995 return 0; 2996 } 2997 2998 static void bnx2x_update_mng_eee(struct link_params *params, u32 eee_status) 2999 { 3000 struct bnx2x *bp = params->bp; 3001 3002 if (bnx2x_eee_has_cap(params)) 3003 REG_WR(bp, params->shmem2_base + 3004 offsetof(struct shmem2_region, 3005 eee_status[params->port]), eee_status); 3006 } 3007 3008 static void bnx2x_eee_an_resolve(struct bnx2x_phy *phy, 3009 struct link_params *params, 3010 struct link_vars *vars) 3011 { 3012 struct bnx2x *bp = params->bp; 3013 u16 adv = 0, lp = 0; 3014 u32 lp_adv = 0; 3015 u8 neg = 0; 3016 3017 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, &adv); 3018 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_LP_EEE_ADV, &lp); 3019 3020 if (lp & 0x2) { 3021 lp_adv |= SHMEM_EEE_100M_ADV; 3022 if (adv & 0x2) { 3023 if (vars->line_speed == SPEED_100) 3024 neg = 1; 3025 DP(NETIF_MSG_LINK, "EEE negotiated - 100M\n"); 3026 } 3027 } 3028 if (lp & 0x14) { 3029 lp_adv |= SHMEM_EEE_1G_ADV; 3030 if (adv & 0x14) { 3031 if (vars->line_speed == SPEED_1000) 3032 neg = 1; 3033 DP(NETIF_MSG_LINK, "EEE negotiated - 1G\n"); 3034 } 3035 } 3036 if (lp & 0x68) { 3037 lp_adv |= SHMEM_EEE_10G_ADV; 3038 if (adv & 0x68) { 3039 if (vars->line_speed == SPEED_10000) 3040 neg = 1; 3041 DP(NETIF_MSG_LINK, "EEE negotiated - 10G\n"); 3042 } 3043 } 3044 3045 vars->eee_status &= ~SHMEM_EEE_LP_ADV_STATUS_MASK; 3046 vars->eee_status |= (lp_adv << SHMEM_EEE_LP_ADV_STATUS_SHIFT); 3047 3048 if (neg) { 3049 DP(NETIF_MSG_LINK, "EEE is active\n"); 3050 vars->eee_status |= SHMEM_EEE_ACTIVE_BIT; 3051 } 3052 3053 } 3054 3055 /******************************************************************/ 3056 /* BSC access functions from E3 */ 3057 /******************************************************************/ 3058 static void bnx2x_bsc_module_sel(struct link_params *params) 3059 { 3060 int idx; 3061 u32 board_cfg, sfp_ctrl; 3062 u32 i2c_pins[I2C_SWITCH_WIDTH], i2c_val[I2C_SWITCH_WIDTH]; 3063 struct bnx2x *bp = params->bp; 3064 u8 port = params->port; 3065 /* Read I2C output PINs */ 3066 board_cfg = REG_RD(bp, params->shmem_base + 3067 offsetof(struct shmem_region, 3068 dev_info.shared_hw_config.board)); 3069 i2c_pins[I2C_BSC0] = board_cfg & SHARED_HW_CFG_E3_I2C_MUX0_MASK; 3070 i2c_pins[I2C_BSC1] = (board_cfg & SHARED_HW_CFG_E3_I2C_MUX1_MASK) >> 3071 SHARED_HW_CFG_E3_I2C_MUX1_SHIFT; 3072 3073 /* Read I2C output value */ 3074 sfp_ctrl = REG_RD(bp, params->shmem_base + 3075 offsetof(struct shmem_region, 3076 dev_info.port_hw_config[port].e3_cmn_pin_cfg)); 3077 i2c_val[I2C_BSC0] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX0_MASK) > 0; 3078 i2c_val[I2C_BSC1] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX1_MASK) > 0; 3079 DP(NETIF_MSG_LINK, "Setting BSC switch\n"); 3080 for (idx = 0; idx < I2C_SWITCH_WIDTH; idx++) 3081 bnx2x_set_cfg_pin(bp, i2c_pins[idx], i2c_val[idx]); 3082 } 3083 3084 static int bnx2x_bsc_read(struct link_params *params, 3085 struct bnx2x *bp, 3086 u8 sl_devid, 3087 u16 sl_addr, 3088 u8 lc_addr, 3089 u8 xfer_cnt, 3090 u32 *data_array) 3091 { 3092 u32 val, i; 3093 int rc = 0; 3094 3095 if (xfer_cnt > 16) { 3096 DP(NETIF_MSG_LINK, "invalid xfer_cnt %d. Max is 16 bytes\n", 3097 xfer_cnt); 3098 return -EINVAL; 3099 } 3100 bnx2x_bsc_module_sel(params); 3101 3102 xfer_cnt = 16 - lc_addr; 3103 3104 /* Enable the engine */ 3105 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND); 3106 val |= MCPR_IMC_COMMAND_ENABLE; 3107 REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val); 3108 3109 /* Program slave device ID */ 3110 val = (sl_devid << 16) | sl_addr; 3111 REG_WR(bp, MCP_REG_MCPR_IMC_SLAVE_CONTROL, val); 3112 3113 /* Start xfer with 0 byte to update the address pointer ???*/ 3114 val = (MCPR_IMC_COMMAND_ENABLE) | 3115 (MCPR_IMC_COMMAND_WRITE_OP << 3116 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) | 3117 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) | (0); 3118 REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val); 3119 3120 /* Poll for completion */ 3121 i = 0; 3122 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND); 3123 while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) { 3124 udelay(10); 3125 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND); 3126 if (i++ > 1000) { 3127 DP(NETIF_MSG_LINK, "wr 0 byte timed out after %d try\n", 3128 i); 3129 rc = -EFAULT; 3130 break; 3131 } 3132 } 3133 if (rc == -EFAULT) 3134 return rc; 3135 3136 /* Start xfer with read op */ 3137 val = (MCPR_IMC_COMMAND_ENABLE) | 3138 (MCPR_IMC_COMMAND_READ_OP << 3139 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) | 3140 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) | 3141 (xfer_cnt); 3142 REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val); 3143 3144 /* Poll for completion */ 3145 i = 0; 3146 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND); 3147 while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) { 3148 udelay(10); 3149 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND); 3150 if (i++ > 1000) { 3151 DP(NETIF_MSG_LINK, "rd op timed out after %d try\n", i); 3152 rc = -EFAULT; 3153 break; 3154 } 3155 } 3156 if (rc == -EFAULT) 3157 return rc; 3158 3159 for (i = (lc_addr >> 2); i < 4; i++) { 3160 data_array[i] = REG_RD(bp, (MCP_REG_MCPR_IMC_DATAREG0 + i*4)); 3161 #ifdef __BIG_ENDIAN 3162 data_array[i] = ((data_array[i] & 0x000000ff) << 24) | 3163 ((data_array[i] & 0x0000ff00) << 8) | 3164 ((data_array[i] & 0x00ff0000) >> 8) | 3165 ((data_array[i] & 0xff000000) >> 24); 3166 #endif 3167 } 3168 return rc; 3169 } 3170 3171 static void bnx2x_cl45_read_or_write(struct bnx2x *bp, struct bnx2x_phy *phy, 3172 u8 devad, u16 reg, u16 or_val) 3173 { 3174 u16 val; 3175 bnx2x_cl45_read(bp, phy, devad, reg, &val); 3176 bnx2x_cl45_write(bp, phy, devad, reg, val | or_val); 3177 } 3178 3179 static void bnx2x_cl45_read_and_write(struct bnx2x *bp, 3180 struct bnx2x_phy *phy, 3181 u8 devad, u16 reg, u16 and_val) 3182 { 3183 u16 val; 3184 bnx2x_cl45_read(bp, phy, devad, reg, &val); 3185 bnx2x_cl45_write(bp, phy, devad, reg, val & and_val); 3186 } 3187 3188 int bnx2x_phy_read(struct link_params *params, u8 phy_addr, 3189 u8 devad, u16 reg, u16 *ret_val) 3190 { 3191 u8 phy_index; 3192 /* Probe for the phy according to the given phy_addr, and execute 3193 * the read request on it 3194 */ 3195 for (phy_index = 0; phy_index < params->num_phys; phy_index++) { 3196 if (params->phy[phy_index].addr == phy_addr) { 3197 return bnx2x_cl45_read(params->bp, 3198 ¶ms->phy[phy_index], devad, 3199 reg, ret_val); 3200 } 3201 } 3202 return -EINVAL; 3203 } 3204 3205 int bnx2x_phy_write(struct link_params *params, u8 phy_addr, 3206 u8 devad, u16 reg, u16 val) 3207 { 3208 u8 phy_index; 3209 /* Probe for the phy according to the given phy_addr, and execute 3210 * the write request on it 3211 */ 3212 for (phy_index = 0; phy_index < params->num_phys; phy_index++) { 3213 if (params->phy[phy_index].addr == phy_addr) { 3214 return bnx2x_cl45_write(params->bp, 3215 ¶ms->phy[phy_index], devad, 3216 reg, val); 3217 } 3218 } 3219 return -EINVAL; 3220 } 3221 static u8 bnx2x_get_warpcore_lane(struct bnx2x_phy *phy, 3222 struct link_params *params) 3223 { 3224 u8 lane = 0; 3225 struct bnx2x *bp = params->bp; 3226 u32 path_swap, path_swap_ovr; 3227 u8 path, port; 3228 3229 path = BP_PATH(bp); 3230 port = params->port; 3231 3232 if (bnx2x_is_4_port_mode(bp)) { 3233 u32 port_swap, port_swap_ovr; 3234 3235 /* Figure out path swap value */ 3236 path_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP_OVWR); 3237 if (path_swap_ovr & 0x1) 3238 path_swap = (path_swap_ovr & 0x2); 3239 else 3240 path_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP); 3241 3242 if (path_swap) 3243 path = path ^ 1; 3244 3245 /* Figure out port swap value */ 3246 port_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP_OVWR); 3247 if (port_swap_ovr & 0x1) 3248 port_swap = (port_swap_ovr & 0x2); 3249 else 3250 port_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP); 3251 3252 if (port_swap) 3253 port = port ^ 1; 3254 3255 lane = (port<<1) + path; 3256 } else { /* Two port mode - no port swap */ 3257 3258 /* Figure out path swap value */ 3259 path_swap_ovr = 3260 REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP_OVWR); 3261 if (path_swap_ovr & 0x1) { 3262 path_swap = (path_swap_ovr & 0x2); 3263 } else { 3264 path_swap = 3265 REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP); 3266 } 3267 if (path_swap) 3268 path = path ^ 1; 3269 3270 lane = path << 1 ; 3271 } 3272 return lane; 3273 } 3274 3275 static void bnx2x_set_aer_mmd(struct link_params *params, 3276 struct bnx2x_phy *phy) 3277 { 3278 u32 ser_lane; 3279 u16 offset, aer_val; 3280 struct bnx2x *bp = params->bp; 3281 ser_lane = ((params->lane_config & 3282 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >> 3283 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT); 3284 3285 offset = (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ? 3286 (phy->addr + ser_lane) : 0; 3287 3288 if (USES_WARPCORE(bp)) { 3289 aer_val = bnx2x_get_warpcore_lane(phy, params); 3290 /* In Dual-lane mode, two lanes are joined together, 3291 * so in order to configure them, the AER broadcast method is 3292 * used here. 3293 * 0x200 is the broadcast address for lanes 0,1 3294 * 0x201 is the broadcast address for lanes 2,3 3295 */ 3296 if (phy->flags & FLAGS_WC_DUAL_MODE) 3297 aer_val = (aer_val >> 1) | 0x200; 3298 } else if (CHIP_IS_E2(bp)) 3299 aer_val = 0x3800 + offset - 1; 3300 else 3301 aer_val = 0x3800 + offset; 3302 3303 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, 3304 MDIO_AER_BLOCK_AER_REG, aer_val); 3305 3306 } 3307 3308 /******************************************************************/ 3309 /* Internal phy section */ 3310 /******************************************************************/ 3311 3312 static void bnx2x_set_serdes_access(struct bnx2x *bp, u8 port) 3313 { 3314 u32 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0; 3315 3316 /* Set Clause 22 */ 3317 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 1); 3318 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000); 3319 udelay(500); 3320 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f); 3321 udelay(500); 3322 /* Set Clause 45 */ 3323 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 0); 3324 } 3325 3326 static void bnx2x_serdes_deassert(struct bnx2x *bp, u8 port) 3327 { 3328 u32 val; 3329 3330 DP(NETIF_MSG_LINK, "bnx2x_serdes_deassert\n"); 3331 3332 val = SERDES_RESET_BITS << (port*16); 3333 3334 /* Reset and unreset the SerDes/XGXS */ 3335 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val); 3336 udelay(500); 3337 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val); 3338 3339 bnx2x_set_serdes_access(bp, port); 3340 3341 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_DEVAD + port*0x10, 3342 DEFAULT_PHY_DEV_ADDR); 3343 } 3344 3345 static void bnx2x_xgxs_specific_func(struct bnx2x_phy *phy, 3346 struct link_params *params, 3347 u32 action) 3348 { 3349 struct bnx2x *bp = params->bp; 3350 switch (action) { 3351 case PHY_INIT: 3352 /* Set correct devad */ 3353 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_ST + params->port*0x18, 0); 3354 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + params->port*0x18, 3355 phy->def_md_devad); 3356 break; 3357 } 3358 } 3359 3360 static void bnx2x_xgxs_deassert(struct link_params *params) 3361 { 3362 struct bnx2x *bp = params->bp; 3363 u8 port; 3364 u32 val; 3365 DP(NETIF_MSG_LINK, "bnx2x_xgxs_deassert\n"); 3366 port = params->port; 3367 3368 val = XGXS_RESET_BITS << (port*16); 3369 3370 /* Reset and unreset the SerDes/XGXS */ 3371 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val); 3372 udelay(500); 3373 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val); 3374 bnx2x_xgxs_specific_func(¶ms->phy[INT_PHY], params, 3375 PHY_INIT); 3376 } 3377 3378 static void bnx2x_calc_ieee_aneg_adv(struct bnx2x_phy *phy, 3379 struct link_params *params, u16 *ieee_fc) 3380 { 3381 struct bnx2x *bp = params->bp; 3382 *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX; 3383 /* Resolve pause mode and advertisement Please refer to Table 3384 * 28B-3 of the 802.3ab-1999 spec 3385 */ 3386 3387 switch (phy->req_flow_ctrl) { 3388 case BNX2X_FLOW_CTRL_AUTO: 3389 switch (params->req_fc_auto_adv) { 3390 case BNX2X_FLOW_CTRL_BOTH: 3391 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; 3392 break; 3393 case BNX2X_FLOW_CTRL_RX: 3394 case BNX2X_FLOW_CTRL_TX: 3395 *ieee_fc |= 3396 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC; 3397 break; 3398 default: 3399 break; 3400 } 3401 break; 3402 case BNX2X_FLOW_CTRL_TX: 3403 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC; 3404 break; 3405 3406 case BNX2X_FLOW_CTRL_RX: 3407 case BNX2X_FLOW_CTRL_BOTH: 3408 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; 3409 break; 3410 3411 case BNX2X_FLOW_CTRL_NONE: 3412 default: 3413 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE; 3414 break; 3415 } 3416 DP(NETIF_MSG_LINK, "ieee_fc = 0x%x\n", *ieee_fc); 3417 } 3418 3419 static void set_phy_vars(struct link_params *params, 3420 struct link_vars *vars) 3421 { 3422 struct bnx2x *bp = params->bp; 3423 u8 actual_phy_idx, phy_index, link_cfg_idx; 3424 u8 phy_config_swapped = params->multi_phy_config & 3425 PORT_HW_CFG_PHY_SWAPPED_ENABLED; 3426 for (phy_index = INT_PHY; phy_index < params->num_phys; 3427 phy_index++) { 3428 link_cfg_idx = LINK_CONFIG_IDX(phy_index); 3429 actual_phy_idx = phy_index; 3430 if (phy_config_swapped) { 3431 if (phy_index == EXT_PHY1) 3432 actual_phy_idx = EXT_PHY2; 3433 else if (phy_index == EXT_PHY2) 3434 actual_phy_idx = EXT_PHY1; 3435 } 3436 params->phy[actual_phy_idx].req_flow_ctrl = 3437 params->req_flow_ctrl[link_cfg_idx]; 3438 3439 params->phy[actual_phy_idx].req_line_speed = 3440 params->req_line_speed[link_cfg_idx]; 3441 3442 params->phy[actual_phy_idx].speed_cap_mask = 3443 params->speed_cap_mask[link_cfg_idx]; 3444 3445 params->phy[actual_phy_idx].req_duplex = 3446 params->req_duplex[link_cfg_idx]; 3447 3448 if (params->req_line_speed[link_cfg_idx] == 3449 SPEED_AUTO_NEG) 3450 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED; 3451 3452 DP(NETIF_MSG_LINK, "req_flow_ctrl %x, req_line_speed %x," 3453 " speed_cap_mask %x\n", 3454 params->phy[actual_phy_idx].req_flow_ctrl, 3455 params->phy[actual_phy_idx].req_line_speed, 3456 params->phy[actual_phy_idx].speed_cap_mask); 3457 } 3458 } 3459 3460 static void bnx2x_ext_phy_set_pause(struct link_params *params, 3461 struct bnx2x_phy *phy, 3462 struct link_vars *vars) 3463 { 3464 u16 val; 3465 struct bnx2x *bp = params->bp; 3466 /* Read modify write pause advertizing */ 3467 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &val); 3468 3469 val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH; 3470 3471 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */ 3472 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); 3473 if ((vars->ieee_fc & 3474 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) == 3475 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) { 3476 val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC; 3477 } 3478 if ((vars->ieee_fc & 3479 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) == 3480 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) { 3481 val |= MDIO_AN_REG_ADV_PAUSE_PAUSE; 3482 } 3483 DP(NETIF_MSG_LINK, "Ext phy AN advertize 0x%x\n", val); 3484 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val); 3485 } 3486 3487 static void bnx2x_pause_resolve(struct link_vars *vars, u32 pause_result) 3488 { /* LD LP */ 3489 switch (pause_result) { /* ASYM P ASYM P */ 3490 case 0xb: /* 1 0 1 1 */ 3491 vars->flow_ctrl = BNX2X_FLOW_CTRL_TX; 3492 break; 3493 3494 case 0xe: /* 1 1 1 0 */ 3495 vars->flow_ctrl = BNX2X_FLOW_CTRL_RX; 3496 break; 3497 3498 case 0x5: /* 0 1 0 1 */ 3499 case 0x7: /* 0 1 1 1 */ 3500 case 0xd: /* 1 1 0 1 */ 3501 case 0xf: /* 1 1 1 1 */ 3502 vars->flow_ctrl = BNX2X_FLOW_CTRL_BOTH; 3503 break; 3504 3505 default: 3506 break; 3507 } 3508 if (pause_result & (1<<0)) 3509 vars->link_status |= LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE; 3510 if (pause_result & (1<<1)) 3511 vars->link_status |= LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE; 3512 3513 } 3514 3515 static void bnx2x_ext_phy_update_adv_fc(struct bnx2x_phy *phy, 3516 struct link_params *params, 3517 struct link_vars *vars) 3518 { 3519 u16 ld_pause; /* local */ 3520 u16 lp_pause; /* link partner */ 3521 u16 pause_result; 3522 struct bnx2x *bp = params->bp; 3523 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) { 3524 bnx2x_cl22_read(bp, phy, 0x4, &ld_pause); 3525 bnx2x_cl22_read(bp, phy, 0x5, &lp_pause); 3526 } else if (CHIP_IS_E3(bp) && 3527 SINGLE_MEDIA_DIRECT(params)) { 3528 u8 lane = bnx2x_get_warpcore_lane(phy, params); 3529 u16 gp_status, gp_mask; 3530 bnx2x_cl45_read(bp, phy, 3531 MDIO_AN_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_4, 3532 &gp_status); 3533 gp_mask = (MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL | 3534 MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP) << 3535 lane; 3536 if ((gp_status & gp_mask) == gp_mask) { 3537 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, 3538 MDIO_AN_REG_ADV_PAUSE, &ld_pause); 3539 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, 3540 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause); 3541 } else { 3542 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, 3543 MDIO_AN_REG_CL37_FC_LD, &ld_pause); 3544 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, 3545 MDIO_AN_REG_CL37_FC_LP, &lp_pause); 3546 ld_pause = ((ld_pause & 3547 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) 3548 << 3); 3549 lp_pause = ((lp_pause & 3550 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) 3551 << 3); 3552 } 3553 } else { 3554 bnx2x_cl45_read(bp, phy, 3555 MDIO_AN_DEVAD, 3556 MDIO_AN_REG_ADV_PAUSE, &ld_pause); 3557 bnx2x_cl45_read(bp, phy, 3558 MDIO_AN_DEVAD, 3559 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause); 3560 } 3561 pause_result = (ld_pause & 3562 MDIO_AN_REG_ADV_PAUSE_MASK) >> 8; 3563 pause_result |= (lp_pause & 3564 MDIO_AN_REG_ADV_PAUSE_MASK) >> 10; 3565 DP(NETIF_MSG_LINK, "Ext PHY pause result 0x%x\n", pause_result); 3566 bnx2x_pause_resolve(vars, pause_result); 3567 3568 } 3569 3570 static u8 bnx2x_ext_phy_resolve_fc(struct bnx2x_phy *phy, 3571 struct link_params *params, 3572 struct link_vars *vars) 3573 { 3574 u8 ret = 0; 3575 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; 3576 if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO) { 3577 /* Update the advertised flow-controled of LD/LP in AN */ 3578 if (phy->req_line_speed == SPEED_AUTO_NEG) 3579 bnx2x_ext_phy_update_adv_fc(phy, params, vars); 3580 /* But set the flow-control result as the requested one */ 3581 vars->flow_ctrl = phy->req_flow_ctrl; 3582 } else if (phy->req_line_speed != SPEED_AUTO_NEG) 3583 vars->flow_ctrl = params->req_fc_auto_adv; 3584 else if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) { 3585 ret = 1; 3586 bnx2x_ext_phy_update_adv_fc(phy, params, vars); 3587 } 3588 return ret; 3589 } 3590 /******************************************************************/ 3591 /* Warpcore section */ 3592 /******************************************************************/ 3593 /* The init_internal_warpcore should mirror the xgxs, 3594 * i.e. reset the lane (if needed), set aer for the 3595 * init configuration, and set/clear SGMII flag. Internal 3596 * phy init is done purely in phy_init stage. 3597 */ 3598 #define WC_TX_DRIVER(post2, idriver, ipre) \ 3599 ((post2 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) | \ 3600 (idriver << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) | \ 3601 (ipre << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET)) 3602 3603 #define WC_TX_FIR(post, main, pre) \ 3604 ((post << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) | \ 3605 (main << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) | \ 3606 (pre << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET)) 3607 3608 static void bnx2x_warpcore_enable_AN_KR2(struct bnx2x_phy *phy, 3609 struct link_params *params, 3610 struct link_vars *vars) 3611 { 3612 struct bnx2x *bp = params->bp; 3613 u16 i; 3614 static struct bnx2x_reg_set reg_set[] = { 3615 /* Step 1 - Program the TX/RX alignment markers */ 3616 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL5, 0xa157}, 3617 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL7, 0xcbe2}, 3618 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL6, 0x7537}, 3619 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL9, 0xa157}, 3620 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL11, 0xcbe2}, 3621 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL10, 0x7537}, 3622 /* Step 2 - Configure the NP registers */ 3623 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_USERB0_CTRL, 0x000a}, 3624 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL1, 0x6400}, 3625 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL3, 0x0620}, 3626 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CODE_FIELD, 0x0157}, 3627 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI1, 0x6464}, 3628 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI2, 0x3150}, 3629 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI3, 0x3150}, 3630 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0157}, 3631 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0620} 3632 }; 3633 DP(NETIF_MSG_LINK, "Enabling 20G-KR2\n"); 3634 3635 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 3636 MDIO_WC_REG_CL49_USERB0_CTRL, (3<<6)); 3637 3638 for (i = 0; i < ARRAY_SIZE(reg_set); i++) 3639 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg, 3640 reg_set[i].val); 3641 3642 /* Start KR2 work-around timer which handles BCM8073 link-parner */ 3643 params->link_attr_sync |= LINK_ATTR_SYNC_KR2_ENABLE; 3644 bnx2x_update_link_attr(params, params->link_attr_sync); 3645 } 3646 3647 static void bnx2x_disable_kr2(struct link_params *params, 3648 struct link_vars *vars, 3649 struct bnx2x_phy *phy) 3650 { 3651 struct bnx2x *bp = params->bp; 3652 int i; 3653 static struct bnx2x_reg_set reg_set[] = { 3654 /* Step 1 - Program the TX/RX alignment markers */ 3655 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL5, 0x7690}, 3656 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL7, 0xe647}, 3657 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL6, 0xc4f0}, 3658 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL9, 0x7690}, 3659 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL11, 0xe647}, 3660 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL10, 0xc4f0}, 3661 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_USERB0_CTRL, 0x000c}, 3662 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL1, 0x6000}, 3663 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL3, 0x0000}, 3664 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CODE_FIELD, 0x0002}, 3665 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI1, 0x0000}, 3666 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI2, 0x0af7}, 3667 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI3, 0x0af7}, 3668 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0002}, 3669 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0000} 3670 }; 3671 DP(NETIF_MSG_LINK, "Disabling 20G-KR2\n"); 3672 3673 for (i = 0; i < ARRAY_SIZE(reg_set); i++) 3674 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg, 3675 reg_set[i].val); 3676 params->link_attr_sync &= ~LINK_ATTR_SYNC_KR2_ENABLE; 3677 bnx2x_update_link_attr(params, params->link_attr_sync); 3678 3679 vars->check_kr2_recovery_cnt = CHECK_KR2_RECOVERY_CNT; 3680 } 3681 3682 static void bnx2x_warpcore_set_lpi_passthrough(struct bnx2x_phy *phy, 3683 struct link_params *params) 3684 { 3685 struct bnx2x *bp = params->bp; 3686 3687 DP(NETIF_MSG_LINK, "Configure WC for LPI pass through\n"); 3688 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3689 MDIO_WC_REG_EEE_COMBO_CONTROL0, 0x7c); 3690 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 3691 MDIO_WC_REG_DIGITAL4_MISC5, 0xc000); 3692 } 3693 3694 static void bnx2x_warpcore_restart_AN_KR(struct bnx2x_phy *phy, 3695 struct link_params *params) 3696 { 3697 /* Restart autoneg on the leading lane only */ 3698 struct bnx2x *bp = params->bp; 3699 u16 lane = bnx2x_get_warpcore_lane(phy, params); 3700 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, 3701 MDIO_AER_BLOCK_AER_REG, lane); 3702 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, 3703 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200); 3704 3705 /* Restore AER */ 3706 bnx2x_set_aer_mmd(params, phy); 3707 } 3708 3709 static void bnx2x_warpcore_enable_AN_KR(struct bnx2x_phy *phy, 3710 struct link_params *params, 3711 struct link_vars *vars) { 3712 u16 lane, i, cl72_ctrl, an_adv = 0, val; 3713 u32 wc_lane_config; 3714 struct bnx2x *bp = params->bp; 3715 static struct bnx2x_reg_set reg_set[] = { 3716 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7}, 3717 {MDIO_PMA_DEVAD, MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0x0}, 3718 {MDIO_WC_DEVAD, MDIO_WC_REG_RX66_CONTROL, 0x7415}, 3719 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x6190}, 3720 /* Disable Autoneg: re-enable it after adv is done. */ 3721 {MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0}, 3722 {MDIO_PMA_DEVAD, MDIO_WC_REG_PMD_KR_CONTROL, 0x2}, 3723 {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP, 0}, 3724 }; 3725 DP(NETIF_MSG_LINK, "Enable Auto Negotiation for KR\n"); 3726 /* Set to default registers that may be overriden by 10G force */ 3727 for (i = 0; i < ARRAY_SIZE(reg_set); i++) 3728 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg, 3729 reg_set[i].val); 3730 3731 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 3732 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, &cl72_ctrl); 3733 cl72_ctrl &= 0x08ff; 3734 cl72_ctrl |= 0x3800; 3735 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3736 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, cl72_ctrl); 3737 3738 /* Check adding advertisement for 1G KX */ 3739 if (((vars->line_speed == SPEED_AUTO_NEG) && 3740 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) || 3741 (vars->line_speed == SPEED_1000)) { 3742 u16 addr = MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2; 3743 an_adv |= (1<<5); 3744 3745 /* Enable CL37 1G Parallel Detect */ 3746 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, addr, 0x1); 3747 DP(NETIF_MSG_LINK, "Advertize 1G\n"); 3748 } 3749 if (((vars->line_speed == SPEED_AUTO_NEG) && 3750 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) || 3751 (vars->line_speed == SPEED_10000)) { 3752 /* Check adding advertisement for 10G KR */ 3753 an_adv |= (1<<7); 3754 /* Enable 10G Parallel Detect */ 3755 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, 3756 MDIO_AER_BLOCK_AER_REG, 0); 3757 3758 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, 3759 MDIO_WC_REG_PAR_DET_10G_CTRL, 1); 3760 bnx2x_set_aer_mmd(params, phy); 3761 DP(NETIF_MSG_LINK, "Advertize 10G\n"); 3762 } 3763 3764 /* Set Transmit PMD settings */ 3765 lane = bnx2x_get_warpcore_lane(phy, params); 3766 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3767 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 3768 WC_TX_DRIVER(0x02, 0x06, 0x09)); 3769 /* Configure the next lane if dual mode */ 3770 if (phy->flags & FLAGS_WC_DUAL_MODE) 3771 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3772 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*(lane+1), 3773 WC_TX_DRIVER(0x02, 0x06, 0x09)); 3774 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3775 MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL, 3776 0x03f0); 3777 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3778 MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL, 3779 0x03f0); 3780 3781 /* Advertised speeds */ 3782 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, 3783 MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, an_adv); 3784 3785 /* Advertised and set FEC (Forward Error Correction) */ 3786 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, 3787 MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2, 3788 (MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY | 3789 MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ)); 3790 3791 /* Enable CL37 BAM */ 3792 if (REG_RD(bp, params->shmem_base + 3793 offsetof(struct shmem_region, dev_info. 3794 port_hw_config[params->port].default_cfg)) & 3795 PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) { 3796 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 3797 MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL, 3798 1); 3799 DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n"); 3800 } 3801 3802 /* Advertise pause */ 3803 bnx2x_ext_phy_set_pause(params, phy, vars); 3804 vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY; 3805 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 3806 MDIO_WC_REG_DIGITAL5_MISC7, 0x100); 3807 3808 /* Over 1G - AN local device user page 1 */ 3809 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3810 MDIO_WC_REG_DIGITAL3_UP1, 0x1f); 3811 3812 if (((phy->req_line_speed == SPEED_AUTO_NEG) && 3813 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) || 3814 (phy->req_line_speed == SPEED_20000)) { 3815 3816 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, 3817 MDIO_AER_BLOCK_AER_REG, lane); 3818 3819 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 3820 MDIO_WC_REG_RX1_PCI_CTRL + (0x10*lane), 3821 (1<<11)); 3822 3823 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3824 MDIO_WC_REG_XGXS_X2_CONTROL3, 0x7); 3825 bnx2x_set_aer_mmd(params, phy); 3826 3827 bnx2x_warpcore_enable_AN_KR2(phy, params, vars); 3828 } else { 3829 /* Enable Auto-Detect to support 1G over CL37 as well */ 3830 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3831 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0x10); 3832 wc_lane_config = REG_RD(bp, params->shmem_base + 3833 offsetof(struct shmem_region, dev_info. 3834 shared_hw_config.wc_lane_config)); 3835 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 3836 MDIO_WC_REG_RX0_PCI_CTRL + (lane << 4), &val); 3837 /* Force cl48 sync_status LOW to avoid getting stuck in CL73 3838 * parallel-detect loop when CL73 and CL37 are enabled. 3839 */ 3840 val |= 1 << 11; 3841 3842 /* Restore Polarity settings in case it was run over by 3843 * previous link owner 3844 */ 3845 if (wc_lane_config & 3846 (SHARED_HW_CFG_RX_LANE0_POL_FLIP_ENABLED << lane)) 3847 val |= 3 << 2; 3848 else 3849 val &= ~(3 << 2); 3850 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3851 MDIO_WC_REG_RX0_PCI_CTRL + (lane << 4), 3852 val); 3853 3854 bnx2x_disable_kr2(params, vars, phy); 3855 } 3856 3857 /* Enable Autoneg: only on the main lane */ 3858 bnx2x_warpcore_restart_AN_KR(phy, params); 3859 } 3860 3861 static void bnx2x_warpcore_set_10G_KR(struct bnx2x_phy *phy, 3862 struct link_params *params, 3863 struct link_vars *vars) 3864 { 3865 struct bnx2x *bp = params->bp; 3866 u16 val16, i, lane; 3867 static struct bnx2x_reg_set reg_set[] = { 3868 /* Disable Autoneg */ 3869 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7}, 3870 {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, 3871 0x3f00}, 3872 {MDIO_AN_DEVAD, MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, 0}, 3873 {MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0}, 3874 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL3_UP1, 0x1}, 3875 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL5_MISC7, 0xa}, 3876 /* Leave cl72 training enable, needed for KR */ 3877 {MDIO_PMA_DEVAD, MDIO_WC_REG_PMD_KR_CONTROL, 0x2} 3878 }; 3879 3880 for (i = 0; i < ARRAY_SIZE(reg_set); i++) 3881 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg, 3882 reg_set[i].val); 3883 3884 lane = bnx2x_get_warpcore_lane(phy, params); 3885 /* Global registers */ 3886 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, 3887 MDIO_AER_BLOCK_AER_REG, 0); 3888 /* Disable CL36 PCS Tx */ 3889 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 3890 MDIO_WC_REG_XGXSBLK1_LANECTRL0, &val16); 3891 val16 &= ~(0x0011 << lane); 3892 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3893 MDIO_WC_REG_XGXSBLK1_LANECTRL0, val16); 3894 3895 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 3896 MDIO_WC_REG_XGXSBLK1_LANECTRL1, &val16); 3897 val16 |= (0x0303 << (lane << 1)); 3898 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3899 MDIO_WC_REG_XGXSBLK1_LANECTRL1, val16); 3900 /* Restore AER */ 3901 bnx2x_set_aer_mmd(params, phy); 3902 /* Set speed via PMA/PMD register */ 3903 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 3904 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040); 3905 3906 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 3907 MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0xB); 3908 3909 /* Enable encoded forced speed */ 3910 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3911 MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x30); 3912 3913 /* Turn TX scramble payload only the 64/66 scrambler */ 3914 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3915 MDIO_WC_REG_TX66_CONTROL, 0x9); 3916 3917 /* Turn RX scramble payload only the 64/66 scrambler */ 3918 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 3919 MDIO_WC_REG_RX66_CONTROL, 0xF9); 3920 3921 /* Set and clear loopback to cause a reset to 64/66 decoder */ 3922 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3923 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x4000); 3924 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3925 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0); 3926 3927 } 3928 3929 static void bnx2x_warpcore_set_10G_XFI(struct bnx2x_phy *phy, 3930 struct link_params *params, 3931 u8 is_xfi) 3932 { 3933 struct bnx2x *bp = params->bp; 3934 u16 misc1_val, tap_val, tx_driver_val, lane, val; 3935 u32 cfg_tap_val, tx_drv_brdct, tx_equal; 3936 3937 /* Hold rxSeqStart */ 3938 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 3939 MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x8000); 3940 3941 /* Hold tx_fifo_reset */ 3942 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 3943 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, 0x1); 3944 3945 /* Disable CL73 AN */ 3946 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0); 3947 3948 /* Disable 100FX Enable and Auto-Detect */ 3949 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, 3950 MDIO_WC_REG_FX100_CTRL1, 0xFFFA); 3951 3952 /* Disable 100FX Idle detect */ 3953 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 3954 MDIO_WC_REG_FX100_CTRL3, 0x0080); 3955 3956 /* Set Block address to Remote PHY & Clear forced_speed[5] */ 3957 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, 3958 MDIO_WC_REG_DIGITAL4_MISC3, 0xFF7F); 3959 3960 /* Turn off auto-detect & fiber mode */ 3961 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, 3962 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 3963 0xFFEE); 3964 3965 /* Set filter_force_link, disable_false_link and parallel_detect */ 3966 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 3967 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &val); 3968 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3969 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 3970 ((val | 0x0006) & 0xFFFE)); 3971 3972 /* Set XFI / SFI */ 3973 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 3974 MDIO_WC_REG_SERDESDIGITAL_MISC1, &misc1_val); 3975 3976 misc1_val &= ~(0x1f); 3977 3978 if (is_xfi) { 3979 misc1_val |= 0x5; 3980 tap_val = WC_TX_FIR(0x08, 0x37, 0x00); 3981 tx_driver_val = WC_TX_DRIVER(0x00, 0x02, 0x03); 3982 } else { 3983 cfg_tap_val = REG_RD(bp, params->shmem_base + 3984 offsetof(struct shmem_region, dev_info. 3985 port_hw_config[params->port]. 3986 sfi_tap_values)); 3987 3988 tx_equal = cfg_tap_val & PORT_HW_CFG_TX_EQUALIZATION_MASK; 3989 3990 tx_drv_brdct = (cfg_tap_val & 3991 PORT_HW_CFG_TX_DRV_BROADCAST_MASK) >> 3992 PORT_HW_CFG_TX_DRV_BROADCAST_SHIFT; 3993 3994 misc1_val |= 0x9; 3995 3996 /* TAP values are controlled by nvram, if value there isn't 0 */ 3997 if (tx_equal) 3998 tap_val = (u16)tx_equal; 3999 else 4000 tap_val = WC_TX_FIR(0x0f, 0x2b, 0x02); 4001 4002 if (tx_drv_brdct) 4003 tx_driver_val = WC_TX_DRIVER(0x03, (u16)tx_drv_brdct, 4004 0x06); 4005 else 4006 tx_driver_val = WC_TX_DRIVER(0x03, 0x02, 0x06); 4007 } 4008 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4009 MDIO_WC_REG_SERDESDIGITAL_MISC1, misc1_val); 4010 4011 /* Set Transmit PMD settings */ 4012 lane = bnx2x_get_warpcore_lane(phy, params); 4013 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4014 MDIO_WC_REG_TX_FIR_TAP, 4015 tap_val | MDIO_WC_REG_TX_FIR_TAP_ENABLE); 4016 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4017 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 4018 tx_driver_val); 4019 4020 /* Enable fiber mode, enable and invert sig_det */ 4021 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 4022 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0xd); 4023 4024 /* Set Block address to Remote PHY & Set forced_speed[5], 40bit mode */ 4025 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 4026 MDIO_WC_REG_DIGITAL4_MISC3, 0x8080); 4027 4028 bnx2x_warpcore_set_lpi_passthrough(phy, params); 4029 4030 /* 10G XFI Full Duplex */ 4031 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4032 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x100); 4033 4034 /* Release tx_fifo_reset */ 4035 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, 4036 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, 4037 0xFFFE); 4038 /* Release rxSeqStart */ 4039 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, 4040 MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x7FFF); 4041 } 4042 4043 static void bnx2x_warpcore_set_20G_force_KR2(struct bnx2x_phy *phy, 4044 struct link_params *params) 4045 { 4046 u16 val; 4047 struct bnx2x *bp = params->bp; 4048 /* Set global registers, so set AER lane to 0 */ 4049 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, 4050 MDIO_AER_BLOCK_AER_REG, 0); 4051 4052 /* Disable sequencer */ 4053 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, 4054 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, ~(1<<13)); 4055 4056 bnx2x_set_aer_mmd(params, phy); 4057 4058 bnx2x_cl45_read_and_write(bp, phy, MDIO_PMA_DEVAD, 4059 MDIO_WC_REG_PMD_KR_CONTROL, ~(1<<1)); 4060 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, 4061 MDIO_AN_REG_CTRL, 0); 4062 /* Turn off CL73 */ 4063 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 4064 MDIO_WC_REG_CL73_USERB0_CTRL, &val); 4065 val &= ~(1<<5); 4066 val |= (1<<6); 4067 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4068 MDIO_WC_REG_CL73_USERB0_CTRL, val); 4069 4070 /* Set 20G KR2 force speed */ 4071 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 4072 MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x1f); 4073 4074 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 4075 MDIO_WC_REG_DIGITAL4_MISC3, (1<<7)); 4076 4077 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 4078 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, &val); 4079 val &= ~(3<<14); 4080 val |= (1<<15); 4081 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4082 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, val); 4083 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4084 MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP, 0x835A); 4085 4086 /* Enable sequencer (over lane 0) */ 4087 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, 4088 MDIO_AER_BLOCK_AER_REG, 0); 4089 4090 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 4091 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, (1<<13)); 4092 4093 bnx2x_set_aer_mmd(params, phy); 4094 } 4095 4096 static void bnx2x_warpcore_set_20G_DXGXS(struct bnx2x *bp, 4097 struct bnx2x_phy *phy, 4098 u16 lane) 4099 { 4100 /* Rx0 anaRxControl1G */ 4101 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4102 MDIO_WC_REG_RX0_ANARXCONTROL1G, 0x90); 4103 4104 /* Rx2 anaRxControl1G */ 4105 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4106 MDIO_WC_REG_RX2_ANARXCONTROL1G, 0x90); 4107 4108 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4109 MDIO_WC_REG_RX66_SCW0, 0xE070); 4110 4111 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4112 MDIO_WC_REG_RX66_SCW1, 0xC0D0); 4113 4114 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4115 MDIO_WC_REG_RX66_SCW2, 0xA0B0); 4116 4117 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4118 MDIO_WC_REG_RX66_SCW3, 0x8090); 4119 4120 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4121 MDIO_WC_REG_RX66_SCW0_MASK, 0xF0F0); 4122 4123 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4124 MDIO_WC_REG_RX66_SCW1_MASK, 0xF0F0); 4125 4126 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4127 MDIO_WC_REG_RX66_SCW2_MASK, 0xF0F0); 4128 4129 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4130 MDIO_WC_REG_RX66_SCW3_MASK, 0xF0F0); 4131 4132 /* Serdes Digital Misc1 */ 4133 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4134 MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6008); 4135 4136 /* Serdes Digital4 Misc3 */ 4137 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4138 MDIO_WC_REG_DIGITAL4_MISC3, 0x8088); 4139 4140 /* Set Transmit PMD settings */ 4141 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4142 MDIO_WC_REG_TX_FIR_TAP, 4143 (WC_TX_FIR(0x12, 0x2d, 0x00) | 4144 MDIO_WC_REG_TX_FIR_TAP_ENABLE)); 4145 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4146 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 4147 WC_TX_DRIVER(0x02, 0x02, 0x02)); 4148 } 4149 4150 static void bnx2x_warpcore_set_sgmii_speed(struct bnx2x_phy *phy, 4151 struct link_params *params, 4152 u8 fiber_mode, 4153 u8 always_autoneg) 4154 { 4155 struct bnx2x *bp = params->bp; 4156 u16 val16, digctrl_kx1, digctrl_kx2; 4157 4158 /* Clear XFI clock comp in non-10G single lane mode. */ 4159 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, 4160 MDIO_WC_REG_RX66_CONTROL, ~(3<<13)); 4161 4162 bnx2x_warpcore_set_lpi_passthrough(phy, params); 4163 4164 if (always_autoneg || phy->req_line_speed == SPEED_AUTO_NEG) { 4165 /* SGMII Autoneg */ 4166 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 4167 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 4168 0x1000); 4169 DP(NETIF_MSG_LINK, "set SGMII AUTONEG\n"); 4170 } else { 4171 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 4172 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16); 4173 val16 &= 0xcebf; 4174 switch (phy->req_line_speed) { 4175 case SPEED_10: 4176 break; 4177 case SPEED_100: 4178 val16 |= 0x2000; 4179 break; 4180 case SPEED_1000: 4181 val16 |= 0x0040; 4182 break; 4183 default: 4184 DP(NETIF_MSG_LINK, 4185 "Speed not supported: 0x%x\n", phy->req_line_speed); 4186 return; 4187 } 4188 4189 if (phy->req_duplex == DUPLEX_FULL) 4190 val16 |= 0x0100; 4191 4192 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4193 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16); 4194 4195 DP(NETIF_MSG_LINK, "set SGMII force speed %d\n", 4196 phy->req_line_speed); 4197 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 4198 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16); 4199 DP(NETIF_MSG_LINK, " (readback) %x\n", val16); 4200 } 4201 4202 /* SGMII Slave mode and disable signal detect */ 4203 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 4204 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &digctrl_kx1); 4205 if (fiber_mode) 4206 digctrl_kx1 = 1; 4207 else 4208 digctrl_kx1 &= 0xff4a; 4209 4210 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4211 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 4212 digctrl_kx1); 4213 4214 /* Turn off parallel detect */ 4215 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 4216 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &digctrl_kx2); 4217 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4218 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 4219 (digctrl_kx2 & ~(1<<2))); 4220 4221 /* Re-enable parallel detect */ 4222 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4223 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 4224 (digctrl_kx2 | (1<<2))); 4225 4226 /* Enable autodet */ 4227 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4228 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 4229 (digctrl_kx1 | 0x10)); 4230 } 4231 4232 static void bnx2x_warpcore_reset_lane(struct bnx2x *bp, 4233 struct bnx2x_phy *phy, 4234 u8 reset) 4235 { 4236 u16 val; 4237 /* Take lane out of reset after configuration is finished */ 4238 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 4239 MDIO_WC_REG_DIGITAL5_MISC6, &val); 4240 if (reset) 4241 val |= 0xC000; 4242 else 4243 val &= 0x3FFF; 4244 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4245 MDIO_WC_REG_DIGITAL5_MISC6, val); 4246 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 4247 MDIO_WC_REG_DIGITAL5_MISC6, &val); 4248 } 4249 /* Clear SFI/XFI link settings registers */ 4250 static void bnx2x_warpcore_clear_regs(struct bnx2x_phy *phy, 4251 struct link_params *params, 4252 u16 lane) 4253 { 4254 struct bnx2x *bp = params->bp; 4255 u16 i; 4256 static struct bnx2x_reg_set wc_regs[] = { 4257 {MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0}, 4258 {MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL1, 0x014a}, 4259 {MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL3, 0x0800}, 4260 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL4_MISC3, 0x8008}, 4261 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 4262 0x0195}, 4263 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 4264 0x0007}, 4265 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, 4266 0x0002}, 4267 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6000}, 4268 {MDIO_WC_DEVAD, MDIO_WC_REG_TX_FIR_TAP, 0x0000}, 4269 {MDIO_WC_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040}, 4270 {MDIO_WC_DEVAD, MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0x0140} 4271 }; 4272 /* Set XFI clock comp as default. */ 4273 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 4274 MDIO_WC_REG_RX66_CONTROL, (3<<13)); 4275 4276 for (i = 0; i < ARRAY_SIZE(wc_regs); i++) 4277 bnx2x_cl45_write(bp, phy, wc_regs[i].devad, wc_regs[i].reg, 4278 wc_regs[i].val); 4279 4280 lane = bnx2x_get_warpcore_lane(phy, params); 4281 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4282 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 0x0990); 4283 4284 } 4285 4286 static int bnx2x_get_mod_abs_int_cfg(struct bnx2x *bp, 4287 u32 chip_id, 4288 u32 shmem_base, u8 port, 4289 u8 *gpio_num, u8 *gpio_port) 4290 { 4291 u32 cfg_pin; 4292 *gpio_num = 0; 4293 *gpio_port = 0; 4294 if (CHIP_IS_E3(bp)) { 4295 cfg_pin = (REG_RD(bp, shmem_base + 4296 offsetof(struct shmem_region, 4297 dev_info.port_hw_config[port].e3_sfp_ctrl)) & 4298 PORT_HW_CFG_E3_MOD_ABS_MASK) >> 4299 PORT_HW_CFG_E3_MOD_ABS_SHIFT; 4300 4301 /* Should not happen. This function called upon interrupt 4302 * triggered by GPIO ( since EPIO can only generate interrupts 4303 * to MCP). 4304 * So if this function was called and none of the GPIOs was set, 4305 * it means the shit hit the fan. 4306 */ 4307 if ((cfg_pin < PIN_CFG_GPIO0_P0) || 4308 (cfg_pin > PIN_CFG_GPIO3_P1)) { 4309 DP(NETIF_MSG_LINK, 4310 "No cfg pin %x for module detect indication\n", 4311 cfg_pin); 4312 return -EINVAL; 4313 } 4314 4315 *gpio_num = (cfg_pin - PIN_CFG_GPIO0_P0) & 0x3; 4316 *gpio_port = (cfg_pin - PIN_CFG_GPIO0_P0) >> 2; 4317 } else { 4318 *gpio_num = MISC_REGISTERS_GPIO_3; 4319 *gpio_port = port; 4320 } 4321 4322 return 0; 4323 } 4324 4325 static int bnx2x_is_sfp_module_plugged(struct bnx2x_phy *phy, 4326 struct link_params *params) 4327 { 4328 struct bnx2x *bp = params->bp; 4329 u8 gpio_num, gpio_port; 4330 u32 gpio_val; 4331 if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id, 4332 params->shmem_base, params->port, 4333 &gpio_num, &gpio_port) != 0) 4334 return 0; 4335 gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port); 4336 4337 /* Call the handling function in case module is detected */ 4338 if (gpio_val == 0) 4339 return 1; 4340 else 4341 return 0; 4342 } 4343 static int bnx2x_warpcore_get_sigdet(struct bnx2x_phy *phy, 4344 struct link_params *params) 4345 { 4346 u16 gp2_status_reg0, lane; 4347 struct bnx2x *bp = params->bp; 4348 4349 lane = bnx2x_get_warpcore_lane(phy, params); 4350 4351 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_0, 4352 &gp2_status_reg0); 4353 4354 return (gp2_status_reg0 >> (8+lane)) & 0x1; 4355 } 4356 4357 static void bnx2x_warpcore_config_runtime(struct bnx2x_phy *phy, 4358 struct link_params *params, 4359 struct link_vars *vars) 4360 { 4361 struct bnx2x *bp = params->bp; 4362 u32 serdes_net_if; 4363 u16 gp_status1 = 0, lnkup = 0, lnkup_kr = 0; 4364 4365 vars->turn_to_run_wc_rt = vars->turn_to_run_wc_rt ? 0 : 1; 4366 4367 if (!vars->turn_to_run_wc_rt) 4368 return; 4369 4370 if (vars->rx_tx_asic_rst) { 4371 u16 lane = bnx2x_get_warpcore_lane(phy, params); 4372 serdes_net_if = (REG_RD(bp, params->shmem_base + 4373 offsetof(struct shmem_region, dev_info. 4374 port_hw_config[params->port].default_cfg)) & 4375 PORT_HW_CFG_NET_SERDES_IF_MASK); 4376 4377 switch (serdes_net_if) { 4378 case PORT_HW_CFG_NET_SERDES_IF_KR: 4379 /* Do we get link yet? */ 4380 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 0x81d1, 4381 &gp_status1); 4382 lnkup = (gp_status1 >> (8+lane)) & 0x1;/* 1G */ 4383 /*10G KR*/ 4384 lnkup_kr = (gp_status1 >> (12+lane)) & 0x1; 4385 4386 if (lnkup_kr || lnkup) { 4387 vars->rx_tx_asic_rst = 0; 4388 } else { 4389 /* Reset the lane to see if link comes up.*/ 4390 bnx2x_warpcore_reset_lane(bp, phy, 1); 4391 bnx2x_warpcore_reset_lane(bp, phy, 0); 4392 4393 /* Restart Autoneg */ 4394 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, 4395 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200); 4396 4397 vars->rx_tx_asic_rst--; 4398 DP(NETIF_MSG_LINK, "0x%x retry left\n", 4399 vars->rx_tx_asic_rst); 4400 } 4401 break; 4402 4403 default: 4404 break; 4405 } 4406 4407 } /*params->rx_tx_asic_rst*/ 4408 4409 } 4410 static void bnx2x_warpcore_config_sfi(struct bnx2x_phy *phy, 4411 struct link_params *params) 4412 { 4413 u16 lane = bnx2x_get_warpcore_lane(phy, params); 4414 struct bnx2x *bp = params->bp; 4415 bnx2x_warpcore_clear_regs(phy, params, lane); 4416 if ((params->req_line_speed[LINK_CONFIG_IDX(INT_PHY)] == 4417 SPEED_10000) && 4418 (phy->media_type != ETH_PHY_SFP_1G_FIBER)) { 4419 DP(NETIF_MSG_LINK, "Setting 10G SFI\n"); 4420 bnx2x_warpcore_set_10G_XFI(phy, params, 0); 4421 } else { 4422 DP(NETIF_MSG_LINK, "Setting 1G Fiber\n"); 4423 bnx2x_warpcore_set_sgmii_speed(phy, params, 1, 0); 4424 } 4425 } 4426 4427 static void bnx2x_sfp_e3_set_transmitter(struct link_params *params, 4428 struct bnx2x_phy *phy, 4429 u8 tx_en) 4430 { 4431 struct bnx2x *bp = params->bp; 4432 u32 cfg_pin; 4433 u8 port = params->port; 4434 4435 cfg_pin = REG_RD(bp, params->shmem_base + 4436 offsetof(struct shmem_region, 4437 dev_info.port_hw_config[port].e3_sfp_ctrl)) & 4438 PORT_HW_CFG_E3_TX_LASER_MASK; 4439 /* Set the !tx_en since this pin is DISABLE_TX_LASER */ 4440 DP(NETIF_MSG_LINK, "Setting WC TX to %d\n", tx_en); 4441 4442 /* For 20G, the expected pin to be used is 3 pins after the current */ 4443 bnx2x_set_cfg_pin(bp, cfg_pin, tx_en ^ 1); 4444 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G) 4445 bnx2x_set_cfg_pin(bp, cfg_pin + 3, tx_en ^ 1); 4446 } 4447 4448 static void bnx2x_warpcore_config_init(struct bnx2x_phy *phy, 4449 struct link_params *params, 4450 struct link_vars *vars) 4451 { 4452 struct bnx2x *bp = params->bp; 4453 u32 serdes_net_if; 4454 u8 fiber_mode; 4455 u16 lane = bnx2x_get_warpcore_lane(phy, params); 4456 serdes_net_if = (REG_RD(bp, params->shmem_base + 4457 offsetof(struct shmem_region, dev_info. 4458 port_hw_config[params->port].default_cfg)) & 4459 PORT_HW_CFG_NET_SERDES_IF_MASK); 4460 DP(NETIF_MSG_LINK, "Begin Warpcore init, link_speed %d, " 4461 "serdes_net_if = 0x%x\n", 4462 vars->line_speed, serdes_net_if); 4463 bnx2x_set_aer_mmd(params, phy); 4464 bnx2x_warpcore_reset_lane(bp, phy, 1); 4465 vars->phy_flags |= PHY_XGXS_FLAG; 4466 if ((serdes_net_if == PORT_HW_CFG_NET_SERDES_IF_SGMII) || 4467 (phy->req_line_speed && 4468 ((phy->req_line_speed == SPEED_100) || 4469 (phy->req_line_speed == SPEED_10)))) { 4470 vars->phy_flags |= PHY_SGMII_FLAG; 4471 DP(NETIF_MSG_LINK, "Setting SGMII mode\n"); 4472 bnx2x_warpcore_clear_regs(phy, params, lane); 4473 bnx2x_warpcore_set_sgmii_speed(phy, params, 0, 1); 4474 } else { 4475 switch (serdes_net_if) { 4476 case PORT_HW_CFG_NET_SERDES_IF_KR: 4477 /* Enable KR Auto Neg */ 4478 if (params->loopback_mode != LOOPBACK_EXT) 4479 bnx2x_warpcore_enable_AN_KR(phy, params, vars); 4480 else { 4481 DP(NETIF_MSG_LINK, "Setting KR 10G-Force\n"); 4482 bnx2x_warpcore_set_10G_KR(phy, params, vars); 4483 } 4484 break; 4485 4486 case PORT_HW_CFG_NET_SERDES_IF_XFI: 4487 bnx2x_warpcore_clear_regs(phy, params, lane); 4488 if (vars->line_speed == SPEED_10000) { 4489 DP(NETIF_MSG_LINK, "Setting 10G XFI\n"); 4490 bnx2x_warpcore_set_10G_XFI(phy, params, 1); 4491 } else { 4492 if (SINGLE_MEDIA_DIRECT(params)) { 4493 DP(NETIF_MSG_LINK, "1G Fiber\n"); 4494 fiber_mode = 1; 4495 } else { 4496 DP(NETIF_MSG_LINK, "10/100/1G SGMII\n"); 4497 fiber_mode = 0; 4498 } 4499 bnx2x_warpcore_set_sgmii_speed(phy, 4500 params, 4501 fiber_mode, 4502 0); 4503 } 4504 4505 break; 4506 4507 case PORT_HW_CFG_NET_SERDES_IF_SFI: 4508 /* Issue Module detection if module is plugged, or 4509 * enabled transmitter to avoid current leakage in case 4510 * no module is connected 4511 */ 4512 if ((params->loopback_mode == LOOPBACK_NONE) || 4513 (params->loopback_mode == LOOPBACK_EXT)) { 4514 if (bnx2x_is_sfp_module_plugged(phy, params)) 4515 bnx2x_sfp_module_detection(phy, params); 4516 else 4517 bnx2x_sfp_e3_set_transmitter(params, 4518 phy, 1); 4519 } 4520 4521 bnx2x_warpcore_config_sfi(phy, params); 4522 break; 4523 4524 case PORT_HW_CFG_NET_SERDES_IF_DXGXS: 4525 if (vars->line_speed != SPEED_20000) { 4526 DP(NETIF_MSG_LINK, "Speed not supported yet\n"); 4527 return; 4528 } 4529 DP(NETIF_MSG_LINK, "Setting 20G DXGXS\n"); 4530 bnx2x_warpcore_set_20G_DXGXS(bp, phy, lane); 4531 /* Issue Module detection */ 4532 4533 bnx2x_sfp_module_detection(phy, params); 4534 break; 4535 case PORT_HW_CFG_NET_SERDES_IF_KR2: 4536 if (!params->loopback_mode) { 4537 bnx2x_warpcore_enable_AN_KR(phy, params, vars); 4538 } else { 4539 DP(NETIF_MSG_LINK, "Setting KR 20G-Force\n"); 4540 bnx2x_warpcore_set_20G_force_KR2(phy, params); 4541 } 4542 break; 4543 default: 4544 DP(NETIF_MSG_LINK, 4545 "Unsupported Serdes Net Interface 0x%x\n", 4546 serdes_net_if); 4547 return; 4548 } 4549 } 4550 4551 /* Take lane out of reset after configuration is finished */ 4552 bnx2x_warpcore_reset_lane(bp, phy, 0); 4553 DP(NETIF_MSG_LINK, "Exit config init\n"); 4554 } 4555 4556 static void bnx2x_warpcore_link_reset(struct bnx2x_phy *phy, 4557 struct link_params *params) 4558 { 4559 struct bnx2x *bp = params->bp; 4560 u16 val16, lane; 4561 bnx2x_sfp_e3_set_transmitter(params, phy, 0); 4562 bnx2x_set_mdio_emac_per_phy(bp, params); 4563 bnx2x_set_aer_mmd(params, phy); 4564 /* Global register */ 4565 bnx2x_warpcore_reset_lane(bp, phy, 1); 4566 4567 /* Clear loopback settings (if any) */ 4568 /* 10G & 20G */ 4569 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, 4570 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0xBFFF); 4571 4572 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, 4573 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0xfffe); 4574 4575 /* Update those 1-copy registers */ 4576 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, 4577 MDIO_AER_BLOCK_AER_REG, 0); 4578 /* Enable 1G MDIO (1-copy) */ 4579 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, 4580 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, 4581 ~0x10); 4582 4583 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, 4584 MDIO_WC_REG_XGXSBLK1_LANECTRL2, 0xff00); 4585 lane = bnx2x_get_warpcore_lane(phy, params); 4586 /* Disable CL36 PCS Tx */ 4587 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 4588 MDIO_WC_REG_XGXSBLK1_LANECTRL0, &val16); 4589 val16 |= (0x11 << lane); 4590 if (phy->flags & FLAGS_WC_DUAL_MODE) 4591 val16 |= (0x22 << lane); 4592 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4593 MDIO_WC_REG_XGXSBLK1_LANECTRL0, val16); 4594 4595 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 4596 MDIO_WC_REG_XGXSBLK1_LANECTRL1, &val16); 4597 val16 &= ~(0x0303 << (lane << 1)); 4598 val16 |= (0x0101 << (lane << 1)); 4599 if (phy->flags & FLAGS_WC_DUAL_MODE) { 4600 val16 &= ~(0x0c0c << (lane << 1)); 4601 val16 |= (0x0404 << (lane << 1)); 4602 } 4603 4604 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4605 MDIO_WC_REG_XGXSBLK1_LANECTRL1, val16); 4606 /* Restore AER */ 4607 bnx2x_set_aer_mmd(params, phy); 4608 4609 } 4610 4611 static void bnx2x_set_warpcore_loopback(struct bnx2x_phy *phy, 4612 struct link_params *params) 4613 { 4614 struct bnx2x *bp = params->bp; 4615 u16 val16; 4616 u32 lane; 4617 DP(NETIF_MSG_LINK, "Setting Warpcore loopback type %x, speed %d\n", 4618 params->loopback_mode, phy->req_line_speed); 4619 4620 if (phy->req_line_speed < SPEED_10000 || 4621 phy->supported & SUPPORTED_20000baseKR2_Full) { 4622 /* 10/100/1000/20G-KR2 */ 4623 4624 /* Update those 1-copy registers */ 4625 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, 4626 MDIO_AER_BLOCK_AER_REG, 0); 4627 /* Enable 1G MDIO (1-copy) */ 4628 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 4629 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, 4630 0x10); 4631 /* Set 1G loopback based on lane (1-copy) */ 4632 lane = bnx2x_get_warpcore_lane(phy, params); 4633 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 4634 MDIO_WC_REG_XGXSBLK1_LANECTRL2, &val16); 4635 val16 |= (1<<lane); 4636 if (phy->flags & FLAGS_WC_DUAL_MODE) 4637 val16 |= (2<<lane); 4638 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4639 MDIO_WC_REG_XGXSBLK1_LANECTRL2, 4640 val16); 4641 4642 /* Switch back to 4-copy registers */ 4643 bnx2x_set_aer_mmd(params, phy); 4644 } else { 4645 /* 10G / 20G-DXGXS */ 4646 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 4647 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 4648 0x4000); 4649 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 4650 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1); 4651 } 4652 } 4653 4654 4655 4656 static void bnx2x_sync_link(struct link_params *params, 4657 struct link_vars *vars) 4658 { 4659 struct bnx2x *bp = params->bp; 4660 u8 link_10g_plus; 4661 if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG) 4662 vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG; 4663 vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP); 4664 if (vars->link_up) { 4665 DP(NETIF_MSG_LINK, "phy link up\n"); 4666 4667 vars->phy_link_up = 1; 4668 vars->duplex = DUPLEX_FULL; 4669 switch (vars->link_status & 4670 LINK_STATUS_SPEED_AND_DUPLEX_MASK) { 4671 case LINK_10THD: 4672 vars->duplex = DUPLEX_HALF; 4673 /* Fall thru */ 4674 case LINK_10TFD: 4675 vars->line_speed = SPEED_10; 4676 break; 4677 4678 case LINK_100TXHD: 4679 vars->duplex = DUPLEX_HALF; 4680 /* Fall thru */ 4681 case LINK_100T4: 4682 case LINK_100TXFD: 4683 vars->line_speed = SPEED_100; 4684 break; 4685 4686 case LINK_1000THD: 4687 vars->duplex = DUPLEX_HALF; 4688 /* Fall thru */ 4689 case LINK_1000TFD: 4690 vars->line_speed = SPEED_1000; 4691 break; 4692 4693 case LINK_2500THD: 4694 vars->duplex = DUPLEX_HALF; 4695 /* Fall thru */ 4696 case LINK_2500TFD: 4697 vars->line_speed = SPEED_2500; 4698 break; 4699 4700 case LINK_10GTFD: 4701 vars->line_speed = SPEED_10000; 4702 break; 4703 case LINK_20GTFD: 4704 vars->line_speed = SPEED_20000; 4705 break; 4706 default: 4707 break; 4708 } 4709 vars->flow_ctrl = 0; 4710 if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED) 4711 vars->flow_ctrl |= BNX2X_FLOW_CTRL_TX; 4712 4713 if (vars->link_status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED) 4714 vars->flow_ctrl |= BNX2X_FLOW_CTRL_RX; 4715 4716 if (!vars->flow_ctrl) 4717 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; 4718 4719 if (vars->line_speed && 4720 ((vars->line_speed == SPEED_10) || 4721 (vars->line_speed == SPEED_100))) { 4722 vars->phy_flags |= PHY_SGMII_FLAG; 4723 } else { 4724 vars->phy_flags &= ~PHY_SGMII_FLAG; 4725 } 4726 if (vars->line_speed && 4727 USES_WARPCORE(bp) && 4728 (vars->line_speed == SPEED_1000)) 4729 vars->phy_flags |= PHY_SGMII_FLAG; 4730 /* Anything 10 and over uses the bmac */ 4731 link_10g_plus = (vars->line_speed >= SPEED_10000); 4732 4733 if (link_10g_plus) { 4734 if (USES_WARPCORE(bp)) 4735 vars->mac_type = MAC_TYPE_XMAC; 4736 else 4737 vars->mac_type = MAC_TYPE_BMAC; 4738 } else { 4739 if (USES_WARPCORE(bp)) 4740 vars->mac_type = MAC_TYPE_UMAC; 4741 else 4742 vars->mac_type = MAC_TYPE_EMAC; 4743 } 4744 } else { /* Link down */ 4745 DP(NETIF_MSG_LINK, "phy link down\n"); 4746 4747 vars->phy_link_up = 0; 4748 4749 vars->line_speed = 0; 4750 vars->duplex = DUPLEX_FULL; 4751 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; 4752 4753 /* Indicate no mac active */ 4754 vars->mac_type = MAC_TYPE_NONE; 4755 if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG) 4756 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG; 4757 if (vars->link_status & LINK_STATUS_SFP_TX_FAULT) 4758 vars->phy_flags |= PHY_SFP_TX_FAULT_FLAG; 4759 } 4760 } 4761 4762 void bnx2x_link_status_update(struct link_params *params, 4763 struct link_vars *vars) 4764 { 4765 struct bnx2x *bp = params->bp; 4766 u8 port = params->port; 4767 u32 sync_offset, media_types; 4768 /* Update PHY configuration */ 4769 set_phy_vars(params, vars); 4770 4771 vars->link_status = REG_RD(bp, params->shmem_base + 4772 offsetof(struct shmem_region, 4773 port_mb[port].link_status)); 4774 4775 /* Force link UP in non LOOPBACK_EXT loopback mode(s) */ 4776 if (params->loopback_mode != LOOPBACK_NONE && 4777 params->loopback_mode != LOOPBACK_EXT) 4778 vars->link_status |= LINK_STATUS_LINK_UP; 4779 4780 if (bnx2x_eee_has_cap(params)) 4781 vars->eee_status = REG_RD(bp, params->shmem2_base + 4782 offsetof(struct shmem2_region, 4783 eee_status[params->port])); 4784 4785 vars->phy_flags = PHY_XGXS_FLAG; 4786 bnx2x_sync_link(params, vars); 4787 /* Sync media type */ 4788 sync_offset = params->shmem_base + 4789 offsetof(struct shmem_region, 4790 dev_info.port_hw_config[port].media_type); 4791 media_types = REG_RD(bp, sync_offset); 4792 4793 params->phy[INT_PHY].media_type = 4794 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) >> 4795 PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT; 4796 params->phy[EXT_PHY1].media_type = 4797 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK) >> 4798 PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT; 4799 params->phy[EXT_PHY2].media_type = 4800 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK) >> 4801 PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT; 4802 DP(NETIF_MSG_LINK, "media_types = 0x%x\n", media_types); 4803 4804 /* Sync AEU offset */ 4805 sync_offset = params->shmem_base + 4806 offsetof(struct shmem_region, 4807 dev_info.port_hw_config[port].aeu_int_mask); 4808 4809 vars->aeu_int_mask = REG_RD(bp, sync_offset); 4810 4811 /* Sync PFC status */ 4812 if (vars->link_status & LINK_STATUS_PFC_ENABLED) 4813 params->feature_config_flags |= 4814 FEATURE_CONFIG_PFC_ENABLED; 4815 else 4816 params->feature_config_flags &= 4817 ~FEATURE_CONFIG_PFC_ENABLED; 4818 4819 if (SHMEM2_HAS(bp, link_attr_sync)) 4820 params->link_attr_sync = SHMEM2_RD(bp, 4821 link_attr_sync[params->port]); 4822 4823 DP(NETIF_MSG_LINK, "link_status 0x%x phy_link_up %x int_mask 0x%x\n", 4824 vars->link_status, vars->phy_link_up, vars->aeu_int_mask); 4825 DP(NETIF_MSG_LINK, "line_speed %x duplex %x flow_ctrl 0x%x\n", 4826 vars->line_speed, vars->duplex, vars->flow_ctrl); 4827 } 4828 4829 static void bnx2x_set_master_ln(struct link_params *params, 4830 struct bnx2x_phy *phy) 4831 { 4832 struct bnx2x *bp = params->bp; 4833 u16 new_master_ln, ser_lane; 4834 ser_lane = ((params->lane_config & 4835 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >> 4836 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT); 4837 4838 /* Set the master_ln for AN */ 4839 CL22_RD_OVER_CL45(bp, phy, 4840 MDIO_REG_BANK_XGXS_BLOCK2, 4841 MDIO_XGXS_BLOCK2_TEST_MODE_LANE, 4842 &new_master_ln); 4843 4844 CL22_WR_OVER_CL45(bp, phy, 4845 MDIO_REG_BANK_XGXS_BLOCK2 , 4846 MDIO_XGXS_BLOCK2_TEST_MODE_LANE, 4847 (new_master_ln | ser_lane)); 4848 } 4849 4850 static int bnx2x_reset_unicore(struct link_params *params, 4851 struct bnx2x_phy *phy, 4852 u8 set_serdes) 4853 { 4854 struct bnx2x *bp = params->bp; 4855 u16 mii_control; 4856 u16 i; 4857 CL22_RD_OVER_CL45(bp, phy, 4858 MDIO_REG_BANK_COMBO_IEEE0, 4859 MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control); 4860 4861 /* Reset the unicore */ 4862 CL22_WR_OVER_CL45(bp, phy, 4863 MDIO_REG_BANK_COMBO_IEEE0, 4864 MDIO_COMBO_IEEE0_MII_CONTROL, 4865 (mii_control | 4866 MDIO_COMBO_IEEO_MII_CONTROL_RESET)); 4867 if (set_serdes) 4868 bnx2x_set_serdes_access(bp, params->port); 4869 4870 /* Wait for the reset to self clear */ 4871 for (i = 0; i < MDIO_ACCESS_TIMEOUT; i++) { 4872 udelay(5); 4873 4874 /* The reset erased the previous bank value */ 4875 CL22_RD_OVER_CL45(bp, phy, 4876 MDIO_REG_BANK_COMBO_IEEE0, 4877 MDIO_COMBO_IEEE0_MII_CONTROL, 4878 &mii_control); 4879 4880 if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) { 4881 udelay(5); 4882 return 0; 4883 } 4884 } 4885 4886 netdev_err(bp->dev, "Warning: PHY was not initialized," 4887 " Port %d\n", 4888 params->port); 4889 DP(NETIF_MSG_LINK, "BUG! XGXS is still in reset!\n"); 4890 return -EINVAL; 4891 4892 } 4893 4894 static void bnx2x_set_swap_lanes(struct link_params *params, 4895 struct bnx2x_phy *phy) 4896 { 4897 struct bnx2x *bp = params->bp; 4898 /* Each two bits represents a lane number: 4899 * No swap is 0123 => 0x1b no need to enable the swap 4900 */ 4901 u16 rx_lane_swap, tx_lane_swap; 4902 4903 rx_lane_swap = ((params->lane_config & 4904 PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >> 4905 PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT); 4906 tx_lane_swap = ((params->lane_config & 4907 PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >> 4908 PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT); 4909 4910 if (rx_lane_swap != 0x1b) { 4911 CL22_WR_OVER_CL45(bp, phy, 4912 MDIO_REG_BANK_XGXS_BLOCK2, 4913 MDIO_XGXS_BLOCK2_RX_LN_SWAP, 4914 (rx_lane_swap | 4915 MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE | 4916 MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE)); 4917 } else { 4918 CL22_WR_OVER_CL45(bp, phy, 4919 MDIO_REG_BANK_XGXS_BLOCK2, 4920 MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0); 4921 } 4922 4923 if (tx_lane_swap != 0x1b) { 4924 CL22_WR_OVER_CL45(bp, phy, 4925 MDIO_REG_BANK_XGXS_BLOCK2, 4926 MDIO_XGXS_BLOCK2_TX_LN_SWAP, 4927 (tx_lane_swap | 4928 MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE)); 4929 } else { 4930 CL22_WR_OVER_CL45(bp, phy, 4931 MDIO_REG_BANK_XGXS_BLOCK2, 4932 MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0); 4933 } 4934 } 4935 4936 static void bnx2x_set_parallel_detection(struct bnx2x_phy *phy, 4937 struct link_params *params) 4938 { 4939 struct bnx2x *bp = params->bp; 4940 u16 control2; 4941 CL22_RD_OVER_CL45(bp, phy, 4942 MDIO_REG_BANK_SERDES_DIGITAL, 4943 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2, 4944 &control2); 4945 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) 4946 control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN; 4947 else 4948 control2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN; 4949 DP(NETIF_MSG_LINK, "phy->speed_cap_mask = 0x%x, control2 = 0x%x\n", 4950 phy->speed_cap_mask, control2); 4951 CL22_WR_OVER_CL45(bp, phy, 4952 MDIO_REG_BANK_SERDES_DIGITAL, 4953 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2, 4954 control2); 4955 4956 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) && 4957 (phy->speed_cap_mask & 4958 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) { 4959 DP(NETIF_MSG_LINK, "XGXS\n"); 4960 4961 CL22_WR_OVER_CL45(bp, phy, 4962 MDIO_REG_BANK_10G_PARALLEL_DETECT, 4963 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK, 4964 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT); 4965 4966 CL22_RD_OVER_CL45(bp, phy, 4967 MDIO_REG_BANK_10G_PARALLEL_DETECT, 4968 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL, 4969 &control2); 4970 4971 4972 control2 |= 4973 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN; 4974 4975 CL22_WR_OVER_CL45(bp, phy, 4976 MDIO_REG_BANK_10G_PARALLEL_DETECT, 4977 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL, 4978 control2); 4979 4980 /* Disable parallel detection of HiG */ 4981 CL22_WR_OVER_CL45(bp, phy, 4982 MDIO_REG_BANK_XGXS_BLOCK2, 4983 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G, 4984 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS | 4985 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS); 4986 } 4987 } 4988 4989 static void bnx2x_set_autoneg(struct bnx2x_phy *phy, 4990 struct link_params *params, 4991 struct link_vars *vars, 4992 u8 enable_cl73) 4993 { 4994 struct bnx2x *bp = params->bp; 4995 u16 reg_val; 4996 4997 /* CL37 Autoneg */ 4998 CL22_RD_OVER_CL45(bp, phy, 4999 MDIO_REG_BANK_COMBO_IEEE0, 5000 MDIO_COMBO_IEEE0_MII_CONTROL, ®_val); 5001 5002 /* CL37 Autoneg Enabled */ 5003 if (vars->line_speed == SPEED_AUTO_NEG) 5004 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN; 5005 else /* CL37 Autoneg Disabled */ 5006 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN | 5007 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN); 5008 5009 CL22_WR_OVER_CL45(bp, phy, 5010 MDIO_REG_BANK_COMBO_IEEE0, 5011 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val); 5012 5013 /* Enable/Disable Autodetection */ 5014 5015 CL22_RD_OVER_CL45(bp, phy, 5016 MDIO_REG_BANK_SERDES_DIGITAL, 5017 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, ®_val); 5018 reg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN | 5019 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT); 5020 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE; 5021 if (vars->line_speed == SPEED_AUTO_NEG) 5022 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET; 5023 else 5024 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET; 5025 5026 CL22_WR_OVER_CL45(bp, phy, 5027 MDIO_REG_BANK_SERDES_DIGITAL, 5028 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val); 5029 5030 /* Enable TetonII and BAM autoneg */ 5031 CL22_RD_OVER_CL45(bp, phy, 5032 MDIO_REG_BANK_BAM_NEXT_PAGE, 5033 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL, 5034 ®_val); 5035 if (vars->line_speed == SPEED_AUTO_NEG) { 5036 /* Enable BAM aneg Mode and TetonII aneg Mode */ 5037 reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE | 5038 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN); 5039 } else { 5040 /* TetonII and BAM Autoneg Disabled */ 5041 reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE | 5042 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN); 5043 } 5044 CL22_WR_OVER_CL45(bp, phy, 5045 MDIO_REG_BANK_BAM_NEXT_PAGE, 5046 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL, 5047 reg_val); 5048 5049 if (enable_cl73) { 5050 /* Enable Cl73 FSM status bits */ 5051 CL22_WR_OVER_CL45(bp, phy, 5052 MDIO_REG_BANK_CL73_USERB0, 5053 MDIO_CL73_USERB0_CL73_UCTRL, 5054 0xe); 5055 5056 /* Enable BAM Station Manager*/ 5057 CL22_WR_OVER_CL45(bp, phy, 5058 MDIO_REG_BANK_CL73_USERB0, 5059 MDIO_CL73_USERB0_CL73_BAM_CTRL1, 5060 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN | 5061 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN | 5062 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN); 5063 5064 /* Advertise CL73 link speeds */ 5065 CL22_RD_OVER_CL45(bp, phy, 5066 MDIO_REG_BANK_CL73_IEEEB1, 5067 MDIO_CL73_IEEEB1_AN_ADV2, 5068 ®_val); 5069 if (phy->speed_cap_mask & 5070 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) 5071 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4; 5072 if (phy->speed_cap_mask & 5073 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) 5074 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX; 5075 5076 CL22_WR_OVER_CL45(bp, phy, 5077 MDIO_REG_BANK_CL73_IEEEB1, 5078 MDIO_CL73_IEEEB1_AN_ADV2, 5079 reg_val); 5080 5081 /* CL73 Autoneg Enabled */ 5082 reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN; 5083 5084 } else /* CL73 Autoneg Disabled */ 5085 reg_val = 0; 5086 5087 CL22_WR_OVER_CL45(bp, phy, 5088 MDIO_REG_BANK_CL73_IEEEB0, 5089 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val); 5090 } 5091 5092 /* Program SerDes, forced speed */ 5093 static void bnx2x_program_serdes(struct bnx2x_phy *phy, 5094 struct link_params *params, 5095 struct link_vars *vars) 5096 { 5097 struct bnx2x *bp = params->bp; 5098 u16 reg_val; 5099 5100 /* Program duplex, disable autoneg and sgmii*/ 5101 CL22_RD_OVER_CL45(bp, phy, 5102 MDIO_REG_BANK_COMBO_IEEE0, 5103 MDIO_COMBO_IEEE0_MII_CONTROL, ®_val); 5104 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX | 5105 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN | 5106 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK); 5107 if (phy->req_duplex == DUPLEX_FULL) 5108 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX; 5109 CL22_WR_OVER_CL45(bp, phy, 5110 MDIO_REG_BANK_COMBO_IEEE0, 5111 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val); 5112 5113 /* Program speed 5114 * - needed only if the speed is greater than 1G (2.5G or 10G) 5115 */ 5116 CL22_RD_OVER_CL45(bp, phy, 5117 MDIO_REG_BANK_SERDES_DIGITAL, 5118 MDIO_SERDES_DIGITAL_MISC1, ®_val); 5119 /* Clearing the speed value before setting the right speed */ 5120 DP(NETIF_MSG_LINK, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val); 5121 5122 reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK | 5123 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL); 5124 5125 if (!((vars->line_speed == SPEED_1000) || 5126 (vars->line_speed == SPEED_100) || 5127 (vars->line_speed == SPEED_10))) { 5128 5129 reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M | 5130 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL); 5131 if (vars->line_speed == SPEED_10000) 5132 reg_val |= 5133 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4; 5134 } 5135 5136 CL22_WR_OVER_CL45(bp, phy, 5137 MDIO_REG_BANK_SERDES_DIGITAL, 5138 MDIO_SERDES_DIGITAL_MISC1, reg_val); 5139 5140 } 5141 5142 static void bnx2x_set_brcm_cl37_advertisement(struct bnx2x_phy *phy, 5143 struct link_params *params) 5144 { 5145 struct bnx2x *bp = params->bp; 5146 u16 val = 0; 5147 5148 /* Set extended capabilities */ 5149 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) 5150 val |= MDIO_OVER_1G_UP1_2_5G; 5151 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) 5152 val |= MDIO_OVER_1G_UP1_10G; 5153 CL22_WR_OVER_CL45(bp, phy, 5154 MDIO_REG_BANK_OVER_1G, 5155 MDIO_OVER_1G_UP1, val); 5156 5157 CL22_WR_OVER_CL45(bp, phy, 5158 MDIO_REG_BANK_OVER_1G, 5159 MDIO_OVER_1G_UP3, 0x400); 5160 } 5161 5162 static void bnx2x_set_ieee_aneg_advertisement(struct bnx2x_phy *phy, 5163 struct link_params *params, 5164 u16 ieee_fc) 5165 { 5166 struct bnx2x *bp = params->bp; 5167 u16 val; 5168 /* For AN, we are always publishing full duplex */ 5169 5170 CL22_WR_OVER_CL45(bp, phy, 5171 MDIO_REG_BANK_COMBO_IEEE0, 5172 MDIO_COMBO_IEEE0_AUTO_NEG_ADV, ieee_fc); 5173 CL22_RD_OVER_CL45(bp, phy, 5174 MDIO_REG_BANK_CL73_IEEEB1, 5175 MDIO_CL73_IEEEB1_AN_ADV1, &val); 5176 val &= ~MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH; 5177 val |= ((ieee_fc<<3) & MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK); 5178 CL22_WR_OVER_CL45(bp, phy, 5179 MDIO_REG_BANK_CL73_IEEEB1, 5180 MDIO_CL73_IEEEB1_AN_ADV1, val); 5181 } 5182 5183 static void bnx2x_restart_autoneg(struct bnx2x_phy *phy, 5184 struct link_params *params, 5185 u8 enable_cl73) 5186 { 5187 struct bnx2x *bp = params->bp; 5188 u16 mii_control; 5189 5190 DP(NETIF_MSG_LINK, "bnx2x_restart_autoneg\n"); 5191 /* Enable and restart BAM/CL37 aneg */ 5192 5193 if (enable_cl73) { 5194 CL22_RD_OVER_CL45(bp, phy, 5195 MDIO_REG_BANK_CL73_IEEEB0, 5196 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, 5197 &mii_control); 5198 5199 CL22_WR_OVER_CL45(bp, phy, 5200 MDIO_REG_BANK_CL73_IEEEB0, 5201 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, 5202 (mii_control | 5203 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN | 5204 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN)); 5205 } else { 5206 5207 CL22_RD_OVER_CL45(bp, phy, 5208 MDIO_REG_BANK_COMBO_IEEE0, 5209 MDIO_COMBO_IEEE0_MII_CONTROL, 5210 &mii_control); 5211 DP(NETIF_MSG_LINK, 5212 "bnx2x_restart_autoneg mii_control before = 0x%x\n", 5213 mii_control); 5214 CL22_WR_OVER_CL45(bp, phy, 5215 MDIO_REG_BANK_COMBO_IEEE0, 5216 MDIO_COMBO_IEEE0_MII_CONTROL, 5217 (mii_control | 5218 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN | 5219 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN)); 5220 } 5221 } 5222 5223 static void bnx2x_initialize_sgmii_process(struct bnx2x_phy *phy, 5224 struct link_params *params, 5225 struct link_vars *vars) 5226 { 5227 struct bnx2x *bp = params->bp; 5228 u16 control1; 5229 5230 /* In SGMII mode, the unicore is always slave */ 5231 5232 CL22_RD_OVER_CL45(bp, phy, 5233 MDIO_REG_BANK_SERDES_DIGITAL, 5234 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, 5235 &control1); 5236 control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT; 5237 /* Set sgmii mode (and not fiber) */ 5238 control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE | 5239 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET | 5240 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE); 5241 CL22_WR_OVER_CL45(bp, phy, 5242 MDIO_REG_BANK_SERDES_DIGITAL, 5243 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, 5244 control1); 5245 5246 /* If forced speed */ 5247 if (!(vars->line_speed == SPEED_AUTO_NEG)) { 5248 /* Set speed, disable autoneg */ 5249 u16 mii_control; 5250 5251 CL22_RD_OVER_CL45(bp, phy, 5252 MDIO_REG_BANK_COMBO_IEEE0, 5253 MDIO_COMBO_IEEE0_MII_CONTROL, 5254 &mii_control); 5255 mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN | 5256 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK| 5257 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX); 5258 5259 switch (vars->line_speed) { 5260 case SPEED_100: 5261 mii_control |= 5262 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100; 5263 break; 5264 case SPEED_1000: 5265 mii_control |= 5266 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000; 5267 break; 5268 case SPEED_10: 5269 /* There is nothing to set for 10M */ 5270 break; 5271 default: 5272 /* Invalid speed for SGMII */ 5273 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n", 5274 vars->line_speed); 5275 break; 5276 } 5277 5278 /* Setting the full duplex */ 5279 if (phy->req_duplex == DUPLEX_FULL) 5280 mii_control |= 5281 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX; 5282 CL22_WR_OVER_CL45(bp, phy, 5283 MDIO_REG_BANK_COMBO_IEEE0, 5284 MDIO_COMBO_IEEE0_MII_CONTROL, 5285 mii_control); 5286 5287 } else { /* AN mode */ 5288 /* Enable and restart AN */ 5289 bnx2x_restart_autoneg(phy, params, 0); 5290 } 5291 } 5292 5293 /* Link management 5294 */ 5295 static int bnx2x_direct_parallel_detect_used(struct bnx2x_phy *phy, 5296 struct link_params *params) 5297 { 5298 struct bnx2x *bp = params->bp; 5299 u16 pd_10g, status2_1000x; 5300 if (phy->req_line_speed != SPEED_AUTO_NEG) 5301 return 0; 5302 CL22_RD_OVER_CL45(bp, phy, 5303 MDIO_REG_BANK_SERDES_DIGITAL, 5304 MDIO_SERDES_DIGITAL_A_1000X_STATUS2, 5305 &status2_1000x); 5306 CL22_RD_OVER_CL45(bp, phy, 5307 MDIO_REG_BANK_SERDES_DIGITAL, 5308 MDIO_SERDES_DIGITAL_A_1000X_STATUS2, 5309 &status2_1000x); 5310 if (status2_1000x & MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED) { 5311 DP(NETIF_MSG_LINK, "1G parallel detect link on port %d\n", 5312 params->port); 5313 return 1; 5314 } 5315 5316 CL22_RD_OVER_CL45(bp, phy, 5317 MDIO_REG_BANK_10G_PARALLEL_DETECT, 5318 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS, 5319 &pd_10g); 5320 5321 if (pd_10g & MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK) { 5322 DP(NETIF_MSG_LINK, "10G parallel detect link on port %d\n", 5323 params->port); 5324 return 1; 5325 } 5326 return 0; 5327 } 5328 5329 static void bnx2x_update_adv_fc(struct bnx2x_phy *phy, 5330 struct link_params *params, 5331 struct link_vars *vars, 5332 u32 gp_status) 5333 { 5334 u16 ld_pause; /* local driver */ 5335 u16 lp_pause; /* link partner */ 5336 u16 pause_result; 5337 struct bnx2x *bp = params->bp; 5338 if ((gp_status & 5339 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | 5340 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) == 5341 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | 5342 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) { 5343 5344 CL22_RD_OVER_CL45(bp, phy, 5345 MDIO_REG_BANK_CL73_IEEEB1, 5346 MDIO_CL73_IEEEB1_AN_ADV1, 5347 &ld_pause); 5348 CL22_RD_OVER_CL45(bp, phy, 5349 MDIO_REG_BANK_CL73_IEEEB1, 5350 MDIO_CL73_IEEEB1_AN_LP_ADV1, 5351 &lp_pause); 5352 pause_result = (ld_pause & 5353 MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK) >> 8; 5354 pause_result |= (lp_pause & 5355 MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK) >> 10; 5356 DP(NETIF_MSG_LINK, "pause_result CL73 0x%x\n", pause_result); 5357 } else { 5358 CL22_RD_OVER_CL45(bp, phy, 5359 MDIO_REG_BANK_COMBO_IEEE0, 5360 MDIO_COMBO_IEEE0_AUTO_NEG_ADV, 5361 &ld_pause); 5362 CL22_RD_OVER_CL45(bp, phy, 5363 MDIO_REG_BANK_COMBO_IEEE0, 5364 MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1, 5365 &lp_pause); 5366 pause_result = (ld_pause & 5367 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>5; 5368 pause_result |= (lp_pause & 5369 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7; 5370 DP(NETIF_MSG_LINK, "pause_result CL37 0x%x\n", pause_result); 5371 } 5372 bnx2x_pause_resolve(vars, pause_result); 5373 5374 } 5375 5376 static void bnx2x_flow_ctrl_resolve(struct bnx2x_phy *phy, 5377 struct link_params *params, 5378 struct link_vars *vars, 5379 u32 gp_status) 5380 { 5381 struct bnx2x *bp = params->bp; 5382 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; 5383 5384 /* Resolve from gp_status in case of AN complete and not sgmii */ 5385 if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO) { 5386 /* Update the advertised flow-controled of LD/LP in AN */ 5387 if (phy->req_line_speed == SPEED_AUTO_NEG) 5388 bnx2x_update_adv_fc(phy, params, vars, gp_status); 5389 /* But set the flow-control result as the requested one */ 5390 vars->flow_ctrl = phy->req_flow_ctrl; 5391 } else if (phy->req_line_speed != SPEED_AUTO_NEG) 5392 vars->flow_ctrl = params->req_fc_auto_adv; 5393 else if ((gp_status & MDIO_AN_CL73_OR_37_COMPLETE) && 5394 (!(vars->phy_flags & PHY_SGMII_FLAG))) { 5395 if (bnx2x_direct_parallel_detect_used(phy, params)) { 5396 vars->flow_ctrl = params->req_fc_auto_adv; 5397 return; 5398 } 5399 bnx2x_update_adv_fc(phy, params, vars, gp_status); 5400 } 5401 DP(NETIF_MSG_LINK, "flow_ctrl 0x%x\n", vars->flow_ctrl); 5402 } 5403 5404 static void bnx2x_check_fallback_to_cl37(struct bnx2x_phy *phy, 5405 struct link_params *params) 5406 { 5407 struct bnx2x *bp = params->bp; 5408 u16 rx_status, ustat_val, cl37_fsm_received; 5409 DP(NETIF_MSG_LINK, "bnx2x_check_fallback_to_cl37\n"); 5410 /* Step 1: Make sure signal is detected */ 5411 CL22_RD_OVER_CL45(bp, phy, 5412 MDIO_REG_BANK_RX0, 5413 MDIO_RX0_RX_STATUS, 5414 &rx_status); 5415 if ((rx_status & MDIO_RX0_RX_STATUS_SIGDET) != 5416 (MDIO_RX0_RX_STATUS_SIGDET)) { 5417 DP(NETIF_MSG_LINK, "Signal is not detected. Restoring CL73." 5418 "rx_status(0x80b0) = 0x%x\n", rx_status); 5419 CL22_WR_OVER_CL45(bp, phy, 5420 MDIO_REG_BANK_CL73_IEEEB0, 5421 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, 5422 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN); 5423 return; 5424 } 5425 /* Step 2: Check CL73 state machine */ 5426 CL22_RD_OVER_CL45(bp, phy, 5427 MDIO_REG_BANK_CL73_USERB0, 5428 MDIO_CL73_USERB0_CL73_USTAT1, 5429 &ustat_val); 5430 if ((ustat_val & 5431 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK | 5432 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) != 5433 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK | 5434 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) { 5435 DP(NETIF_MSG_LINK, "CL73 state-machine is not stable. " 5436 "ustat_val(0x8371) = 0x%x\n", ustat_val); 5437 return; 5438 } 5439 /* Step 3: Check CL37 Message Pages received to indicate LP 5440 * supports only CL37 5441 */ 5442 CL22_RD_OVER_CL45(bp, phy, 5443 MDIO_REG_BANK_REMOTE_PHY, 5444 MDIO_REMOTE_PHY_MISC_RX_STATUS, 5445 &cl37_fsm_received); 5446 if ((cl37_fsm_received & 5447 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG | 5448 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) != 5449 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG | 5450 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) { 5451 DP(NETIF_MSG_LINK, "No CL37 FSM were received. " 5452 "misc_rx_status(0x8330) = 0x%x\n", 5453 cl37_fsm_received); 5454 return; 5455 } 5456 /* The combined cl37/cl73 fsm state information indicating that 5457 * we are connected to a device which does not support cl73, but 5458 * does support cl37 BAM. In this case we disable cl73 and 5459 * restart cl37 auto-neg 5460 */ 5461 5462 /* Disable CL73 */ 5463 CL22_WR_OVER_CL45(bp, phy, 5464 MDIO_REG_BANK_CL73_IEEEB0, 5465 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, 5466 0); 5467 /* Restart CL37 autoneg */ 5468 bnx2x_restart_autoneg(phy, params, 0); 5469 DP(NETIF_MSG_LINK, "Disabling CL73, and restarting CL37 autoneg\n"); 5470 } 5471 5472 static void bnx2x_xgxs_an_resolve(struct bnx2x_phy *phy, 5473 struct link_params *params, 5474 struct link_vars *vars, 5475 u32 gp_status) 5476 { 5477 if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE) 5478 vars->link_status |= 5479 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; 5480 5481 if (bnx2x_direct_parallel_detect_used(phy, params)) 5482 vars->link_status |= 5483 LINK_STATUS_PARALLEL_DETECTION_USED; 5484 } 5485 static int bnx2x_get_link_speed_duplex(struct bnx2x_phy *phy, 5486 struct link_params *params, 5487 struct link_vars *vars, 5488 u16 is_link_up, 5489 u16 speed_mask, 5490 u16 is_duplex) 5491 { 5492 struct bnx2x *bp = params->bp; 5493 if (phy->req_line_speed == SPEED_AUTO_NEG) 5494 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED; 5495 if (is_link_up) { 5496 DP(NETIF_MSG_LINK, "phy link up\n"); 5497 5498 vars->phy_link_up = 1; 5499 vars->link_status |= LINK_STATUS_LINK_UP; 5500 5501 switch (speed_mask) { 5502 case GP_STATUS_10M: 5503 vars->line_speed = SPEED_10; 5504 if (is_duplex == DUPLEX_FULL) 5505 vars->link_status |= LINK_10TFD; 5506 else 5507 vars->link_status |= LINK_10THD; 5508 break; 5509 5510 case GP_STATUS_100M: 5511 vars->line_speed = SPEED_100; 5512 if (is_duplex == DUPLEX_FULL) 5513 vars->link_status |= LINK_100TXFD; 5514 else 5515 vars->link_status |= LINK_100TXHD; 5516 break; 5517 5518 case GP_STATUS_1G: 5519 case GP_STATUS_1G_KX: 5520 vars->line_speed = SPEED_1000; 5521 if (is_duplex == DUPLEX_FULL) 5522 vars->link_status |= LINK_1000TFD; 5523 else 5524 vars->link_status |= LINK_1000THD; 5525 break; 5526 5527 case GP_STATUS_2_5G: 5528 vars->line_speed = SPEED_2500; 5529 if (is_duplex == DUPLEX_FULL) 5530 vars->link_status |= LINK_2500TFD; 5531 else 5532 vars->link_status |= LINK_2500THD; 5533 break; 5534 5535 case GP_STATUS_5G: 5536 case GP_STATUS_6G: 5537 DP(NETIF_MSG_LINK, 5538 "link speed unsupported gp_status 0x%x\n", 5539 speed_mask); 5540 return -EINVAL; 5541 5542 case GP_STATUS_10G_KX4: 5543 case GP_STATUS_10G_HIG: 5544 case GP_STATUS_10G_CX4: 5545 case GP_STATUS_10G_KR: 5546 case GP_STATUS_10G_SFI: 5547 case GP_STATUS_10G_XFI: 5548 vars->line_speed = SPEED_10000; 5549 vars->link_status |= LINK_10GTFD; 5550 break; 5551 case GP_STATUS_20G_DXGXS: 5552 case GP_STATUS_20G_KR2: 5553 vars->line_speed = SPEED_20000; 5554 vars->link_status |= LINK_20GTFD; 5555 break; 5556 default: 5557 DP(NETIF_MSG_LINK, 5558 "link speed unsupported gp_status 0x%x\n", 5559 speed_mask); 5560 return -EINVAL; 5561 } 5562 } else { /* link_down */ 5563 DP(NETIF_MSG_LINK, "phy link down\n"); 5564 5565 vars->phy_link_up = 0; 5566 5567 vars->duplex = DUPLEX_FULL; 5568 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; 5569 vars->mac_type = MAC_TYPE_NONE; 5570 } 5571 DP(NETIF_MSG_LINK, " phy_link_up %x line_speed %d\n", 5572 vars->phy_link_up, vars->line_speed); 5573 return 0; 5574 } 5575 5576 static int bnx2x_link_settings_status(struct bnx2x_phy *phy, 5577 struct link_params *params, 5578 struct link_vars *vars) 5579 { 5580 struct bnx2x *bp = params->bp; 5581 5582 u16 gp_status, duplex = DUPLEX_HALF, link_up = 0, speed_mask; 5583 int rc = 0; 5584 5585 /* Read gp_status */ 5586 CL22_RD_OVER_CL45(bp, phy, 5587 MDIO_REG_BANK_GP_STATUS, 5588 MDIO_GP_STATUS_TOP_AN_STATUS1, 5589 &gp_status); 5590 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS) 5591 duplex = DUPLEX_FULL; 5592 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) 5593 link_up = 1; 5594 speed_mask = gp_status & GP_STATUS_SPEED_MASK; 5595 DP(NETIF_MSG_LINK, "gp_status 0x%x, is_link_up %d, speed_mask 0x%x\n", 5596 gp_status, link_up, speed_mask); 5597 rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, speed_mask, 5598 duplex); 5599 if (rc == -EINVAL) 5600 return rc; 5601 5602 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) { 5603 if (SINGLE_MEDIA_DIRECT(params)) { 5604 vars->duplex = duplex; 5605 bnx2x_flow_ctrl_resolve(phy, params, vars, gp_status); 5606 if (phy->req_line_speed == SPEED_AUTO_NEG) 5607 bnx2x_xgxs_an_resolve(phy, params, vars, 5608 gp_status); 5609 } 5610 } else { /* Link_down */ 5611 if ((phy->req_line_speed == SPEED_AUTO_NEG) && 5612 SINGLE_MEDIA_DIRECT(params)) { 5613 /* Check signal is detected */ 5614 bnx2x_check_fallback_to_cl37(phy, params); 5615 } 5616 } 5617 5618 /* Read LP advertised speeds*/ 5619 if (SINGLE_MEDIA_DIRECT(params) && 5620 (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)) { 5621 u16 val; 5622 5623 CL22_RD_OVER_CL45(bp, phy, MDIO_REG_BANK_CL73_IEEEB1, 5624 MDIO_CL73_IEEEB1_AN_LP_ADV2, &val); 5625 5626 if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX) 5627 vars->link_status |= 5628 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; 5629 if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 | 5630 MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR)) 5631 vars->link_status |= 5632 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; 5633 5634 CL22_RD_OVER_CL45(bp, phy, MDIO_REG_BANK_OVER_1G, 5635 MDIO_OVER_1G_LP_UP1, &val); 5636 5637 if (val & MDIO_OVER_1G_UP1_2_5G) 5638 vars->link_status |= 5639 LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE; 5640 if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH)) 5641 vars->link_status |= 5642 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; 5643 } 5644 5645 DP(NETIF_MSG_LINK, "duplex %x flow_ctrl 0x%x link_status 0x%x\n", 5646 vars->duplex, vars->flow_ctrl, vars->link_status); 5647 return rc; 5648 } 5649 5650 static int bnx2x_warpcore_read_status(struct bnx2x_phy *phy, 5651 struct link_params *params, 5652 struct link_vars *vars) 5653 { 5654 struct bnx2x *bp = params->bp; 5655 u8 lane; 5656 u16 gp_status1, gp_speed, link_up, duplex = DUPLEX_FULL; 5657 int rc = 0; 5658 lane = bnx2x_get_warpcore_lane(phy, params); 5659 /* Read gp_status */ 5660 if ((params->loopback_mode) && 5661 (phy->flags & FLAGS_WC_DUAL_MODE)) { 5662 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 5663 MDIO_WC_REG_DIGITAL5_LINK_STATUS, &link_up); 5664 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 5665 MDIO_WC_REG_DIGITAL5_LINK_STATUS, &link_up); 5666 link_up &= 0x1; 5667 } else if ((phy->req_line_speed > SPEED_10000) && 5668 (phy->supported & SUPPORTED_20000baseMLD2_Full)) { 5669 u16 temp_link_up; 5670 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 5671 1, &temp_link_up); 5672 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 5673 1, &link_up); 5674 DP(NETIF_MSG_LINK, "PCS RX link status = 0x%x-->0x%x\n", 5675 temp_link_up, link_up); 5676 link_up &= (1<<2); 5677 if (link_up) 5678 bnx2x_ext_phy_resolve_fc(phy, params, vars); 5679 } else { 5680 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 5681 MDIO_WC_REG_GP2_STATUS_GP_2_1, 5682 &gp_status1); 5683 DP(NETIF_MSG_LINK, "0x81d1 = 0x%x\n", gp_status1); 5684 /* Check for either KR, 1G, or AN up. */ 5685 link_up = ((gp_status1 >> 8) | 5686 (gp_status1 >> 12) | 5687 (gp_status1)) & 5688 (1 << lane); 5689 if (phy->supported & SUPPORTED_20000baseKR2_Full) { 5690 u16 an_link; 5691 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, 5692 MDIO_AN_REG_STATUS, &an_link); 5693 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, 5694 MDIO_AN_REG_STATUS, &an_link); 5695 link_up |= (an_link & (1<<2)); 5696 } 5697 if (link_up && SINGLE_MEDIA_DIRECT(params)) { 5698 u16 pd, gp_status4; 5699 if (phy->req_line_speed == SPEED_AUTO_NEG) { 5700 /* Check Autoneg complete */ 5701 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 5702 MDIO_WC_REG_GP2_STATUS_GP_2_4, 5703 &gp_status4); 5704 if (gp_status4 & ((1<<12)<<lane)) 5705 vars->link_status |= 5706 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; 5707 5708 /* Check parallel detect used */ 5709 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 5710 MDIO_WC_REG_PAR_DET_10G_STATUS, 5711 &pd); 5712 if (pd & (1<<15)) 5713 vars->link_status |= 5714 LINK_STATUS_PARALLEL_DETECTION_USED; 5715 } 5716 bnx2x_ext_phy_resolve_fc(phy, params, vars); 5717 vars->duplex = duplex; 5718 } 5719 } 5720 5721 if ((vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) && 5722 SINGLE_MEDIA_DIRECT(params)) { 5723 u16 val; 5724 5725 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, 5726 MDIO_AN_REG_LP_AUTO_NEG2, &val); 5727 5728 if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX) 5729 vars->link_status |= 5730 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; 5731 if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 | 5732 MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR)) 5733 vars->link_status |= 5734 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; 5735 5736 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 5737 MDIO_WC_REG_DIGITAL3_LP_UP1, &val); 5738 5739 if (val & MDIO_OVER_1G_UP1_2_5G) 5740 vars->link_status |= 5741 LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE; 5742 if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH)) 5743 vars->link_status |= 5744 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; 5745 5746 } 5747 5748 5749 if (lane < 2) { 5750 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 5751 MDIO_WC_REG_GP2_STATUS_GP_2_2, &gp_speed); 5752 } else { 5753 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 5754 MDIO_WC_REG_GP2_STATUS_GP_2_3, &gp_speed); 5755 } 5756 DP(NETIF_MSG_LINK, "lane %d gp_speed 0x%x\n", lane, gp_speed); 5757 5758 if ((lane & 1) == 0) 5759 gp_speed <<= 8; 5760 gp_speed &= 0x3f00; 5761 link_up = !!link_up; 5762 5763 rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, gp_speed, 5764 duplex); 5765 5766 /* In case of KR link down, start up the recovering procedure */ 5767 if ((!link_up) && (phy->media_type == ETH_PHY_KR) && 5768 (!(phy->flags & FLAGS_WC_DUAL_MODE))) 5769 vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY; 5770 5771 DP(NETIF_MSG_LINK, "duplex %x flow_ctrl 0x%x link_status 0x%x\n", 5772 vars->duplex, vars->flow_ctrl, vars->link_status); 5773 return rc; 5774 } 5775 static void bnx2x_set_gmii_tx_driver(struct link_params *params) 5776 { 5777 struct bnx2x *bp = params->bp; 5778 struct bnx2x_phy *phy = ¶ms->phy[INT_PHY]; 5779 u16 lp_up2; 5780 u16 tx_driver; 5781 u16 bank; 5782 5783 /* Read precomp */ 5784 CL22_RD_OVER_CL45(bp, phy, 5785 MDIO_REG_BANK_OVER_1G, 5786 MDIO_OVER_1G_LP_UP2, &lp_up2); 5787 5788 /* Bits [10:7] at lp_up2, positioned at [15:12] */ 5789 lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >> 5790 MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) << 5791 MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT); 5792 5793 if (lp_up2 == 0) 5794 return; 5795 5796 for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3; 5797 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) { 5798 CL22_RD_OVER_CL45(bp, phy, 5799 bank, 5800 MDIO_TX0_TX_DRIVER, &tx_driver); 5801 5802 /* Replace tx_driver bits [15:12] */ 5803 if (lp_up2 != 5804 (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) { 5805 tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK; 5806 tx_driver |= lp_up2; 5807 CL22_WR_OVER_CL45(bp, phy, 5808 bank, 5809 MDIO_TX0_TX_DRIVER, tx_driver); 5810 } 5811 } 5812 } 5813 5814 static int bnx2x_emac_program(struct link_params *params, 5815 struct link_vars *vars) 5816 { 5817 struct bnx2x *bp = params->bp; 5818 u8 port = params->port; 5819 u16 mode = 0; 5820 5821 DP(NETIF_MSG_LINK, "setting link speed & duplex\n"); 5822 bnx2x_bits_dis(bp, GRCBASE_EMAC0 + port*0x400 + 5823 EMAC_REG_EMAC_MODE, 5824 (EMAC_MODE_25G_MODE | 5825 EMAC_MODE_PORT_MII_10M | 5826 EMAC_MODE_HALF_DUPLEX)); 5827 switch (vars->line_speed) { 5828 case SPEED_10: 5829 mode |= EMAC_MODE_PORT_MII_10M; 5830 break; 5831 5832 case SPEED_100: 5833 mode |= EMAC_MODE_PORT_MII; 5834 break; 5835 5836 case SPEED_1000: 5837 mode |= EMAC_MODE_PORT_GMII; 5838 break; 5839 5840 case SPEED_2500: 5841 mode |= (EMAC_MODE_25G_MODE | EMAC_MODE_PORT_GMII); 5842 break; 5843 5844 default: 5845 /* 10G not valid for EMAC */ 5846 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n", 5847 vars->line_speed); 5848 return -EINVAL; 5849 } 5850 5851 if (vars->duplex == DUPLEX_HALF) 5852 mode |= EMAC_MODE_HALF_DUPLEX; 5853 bnx2x_bits_en(bp, 5854 GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE, 5855 mode); 5856 5857 bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed); 5858 return 0; 5859 } 5860 5861 static void bnx2x_set_preemphasis(struct bnx2x_phy *phy, 5862 struct link_params *params) 5863 { 5864 5865 u16 bank, i = 0; 5866 struct bnx2x *bp = params->bp; 5867 5868 for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3; 5869 bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0), i++) { 5870 CL22_WR_OVER_CL45(bp, phy, 5871 bank, 5872 MDIO_RX0_RX_EQ_BOOST, 5873 phy->rx_preemphasis[i]); 5874 } 5875 5876 for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3; 5877 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) { 5878 CL22_WR_OVER_CL45(bp, phy, 5879 bank, 5880 MDIO_TX0_TX_DRIVER, 5881 phy->tx_preemphasis[i]); 5882 } 5883 } 5884 5885 static void bnx2x_xgxs_config_init(struct bnx2x_phy *phy, 5886 struct link_params *params, 5887 struct link_vars *vars) 5888 { 5889 struct bnx2x *bp = params->bp; 5890 u8 enable_cl73 = (SINGLE_MEDIA_DIRECT(params) || 5891 (params->loopback_mode == LOOPBACK_XGXS)); 5892 if (!(vars->phy_flags & PHY_SGMII_FLAG)) { 5893 if (SINGLE_MEDIA_DIRECT(params) && 5894 (params->feature_config_flags & 5895 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) 5896 bnx2x_set_preemphasis(phy, params); 5897 5898 /* Forced speed requested? */ 5899 if (vars->line_speed != SPEED_AUTO_NEG || 5900 (SINGLE_MEDIA_DIRECT(params) && 5901 params->loopback_mode == LOOPBACK_EXT)) { 5902 DP(NETIF_MSG_LINK, "not SGMII, no AN\n"); 5903 5904 /* Disable autoneg */ 5905 bnx2x_set_autoneg(phy, params, vars, 0); 5906 5907 /* Program speed and duplex */ 5908 bnx2x_program_serdes(phy, params, vars); 5909 5910 } else { /* AN_mode */ 5911 DP(NETIF_MSG_LINK, "not SGMII, AN\n"); 5912 5913 /* AN enabled */ 5914 bnx2x_set_brcm_cl37_advertisement(phy, params); 5915 5916 /* Program duplex & pause advertisement (for aneg) */ 5917 bnx2x_set_ieee_aneg_advertisement(phy, params, 5918 vars->ieee_fc); 5919 5920 /* Enable autoneg */ 5921 bnx2x_set_autoneg(phy, params, vars, enable_cl73); 5922 5923 /* Enable and restart AN */ 5924 bnx2x_restart_autoneg(phy, params, enable_cl73); 5925 } 5926 5927 } else { /* SGMII mode */ 5928 DP(NETIF_MSG_LINK, "SGMII\n"); 5929 5930 bnx2x_initialize_sgmii_process(phy, params, vars); 5931 } 5932 } 5933 5934 static int bnx2x_prepare_xgxs(struct bnx2x_phy *phy, 5935 struct link_params *params, 5936 struct link_vars *vars) 5937 { 5938 int rc; 5939 vars->phy_flags |= PHY_XGXS_FLAG; 5940 if ((phy->req_line_speed && 5941 ((phy->req_line_speed == SPEED_100) || 5942 (phy->req_line_speed == SPEED_10))) || 5943 (!phy->req_line_speed && 5944 (phy->speed_cap_mask >= 5945 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) && 5946 (phy->speed_cap_mask < 5947 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) || 5948 (phy->type == PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD)) 5949 vars->phy_flags |= PHY_SGMII_FLAG; 5950 else 5951 vars->phy_flags &= ~PHY_SGMII_FLAG; 5952 5953 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); 5954 bnx2x_set_aer_mmd(params, phy); 5955 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) 5956 bnx2x_set_master_ln(params, phy); 5957 5958 rc = bnx2x_reset_unicore(params, phy, 0); 5959 /* Reset the SerDes and wait for reset bit return low */ 5960 if (rc) 5961 return rc; 5962 5963 bnx2x_set_aer_mmd(params, phy); 5964 /* Setting the masterLn_def again after the reset */ 5965 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) { 5966 bnx2x_set_master_ln(params, phy); 5967 bnx2x_set_swap_lanes(params, phy); 5968 } 5969 5970 return rc; 5971 } 5972 5973 static u16 bnx2x_wait_reset_complete(struct bnx2x *bp, 5974 struct bnx2x_phy *phy, 5975 struct link_params *params) 5976 { 5977 u16 cnt, ctrl; 5978 /* Wait for soft reset to get cleared up to 1 sec */ 5979 for (cnt = 0; cnt < 1000; cnt++) { 5980 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) 5981 bnx2x_cl22_read(bp, phy, 5982 MDIO_PMA_REG_CTRL, &ctrl); 5983 else 5984 bnx2x_cl45_read(bp, phy, 5985 MDIO_PMA_DEVAD, 5986 MDIO_PMA_REG_CTRL, &ctrl); 5987 if (!(ctrl & (1<<15))) 5988 break; 5989 usleep_range(1000, 2000); 5990 } 5991 5992 if (cnt == 1000) 5993 netdev_err(bp->dev, "Warning: PHY was not initialized," 5994 " Port %d\n", 5995 params->port); 5996 DP(NETIF_MSG_LINK, "control reg 0x%x (after %d ms)\n", ctrl, cnt); 5997 return cnt; 5998 } 5999 6000 static void bnx2x_link_int_enable(struct link_params *params) 6001 { 6002 u8 port = params->port; 6003 u32 mask; 6004 struct bnx2x *bp = params->bp; 6005 6006 /* Setting the status to report on link up for either XGXS or SerDes */ 6007 if (CHIP_IS_E3(bp)) { 6008 mask = NIG_MASK_XGXS0_LINK_STATUS; 6009 if (!(SINGLE_MEDIA_DIRECT(params))) 6010 mask |= NIG_MASK_MI_INT; 6011 } else if (params->switch_cfg == SWITCH_CFG_10G) { 6012 mask = (NIG_MASK_XGXS0_LINK10G | 6013 NIG_MASK_XGXS0_LINK_STATUS); 6014 DP(NETIF_MSG_LINK, "enabled XGXS interrupt\n"); 6015 if (!(SINGLE_MEDIA_DIRECT(params)) && 6016 params->phy[INT_PHY].type != 6017 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) { 6018 mask |= NIG_MASK_MI_INT; 6019 DP(NETIF_MSG_LINK, "enabled external phy int\n"); 6020 } 6021 6022 } else { /* SerDes */ 6023 mask = NIG_MASK_SERDES0_LINK_STATUS; 6024 DP(NETIF_MSG_LINK, "enabled SerDes interrupt\n"); 6025 if (!(SINGLE_MEDIA_DIRECT(params)) && 6026 params->phy[INT_PHY].type != 6027 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN) { 6028 mask |= NIG_MASK_MI_INT; 6029 DP(NETIF_MSG_LINK, "enabled external phy int\n"); 6030 } 6031 } 6032 bnx2x_bits_en(bp, 6033 NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 6034 mask); 6035 6036 DP(NETIF_MSG_LINK, "port %x, is_xgxs %x, int_status 0x%x\n", port, 6037 (params->switch_cfg == SWITCH_CFG_10G), 6038 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4)); 6039 DP(NETIF_MSG_LINK, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x\n", 6040 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4), 6041 REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18), 6042 REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS+port*0x3c)); 6043 DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n", 6044 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68), 6045 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68)); 6046 } 6047 6048 static void bnx2x_rearm_latch_signal(struct bnx2x *bp, u8 port, 6049 u8 exp_mi_int) 6050 { 6051 u32 latch_status = 0; 6052 6053 /* Disable the MI INT ( external phy int ) by writing 1 to the 6054 * status register. Link down indication is high-active-signal, 6055 * so in this case we need to write the status to clear the XOR 6056 */ 6057 /* Read Latched signals */ 6058 latch_status = REG_RD(bp, 6059 NIG_REG_LATCH_STATUS_0 + port*8); 6060 DP(NETIF_MSG_LINK, "latch_status = 0x%x\n", latch_status); 6061 /* Handle only those with latched-signal=up.*/ 6062 if (exp_mi_int) 6063 bnx2x_bits_en(bp, 6064 NIG_REG_STATUS_INTERRUPT_PORT0 6065 + port*4, 6066 NIG_STATUS_EMAC0_MI_INT); 6067 else 6068 bnx2x_bits_dis(bp, 6069 NIG_REG_STATUS_INTERRUPT_PORT0 6070 + port*4, 6071 NIG_STATUS_EMAC0_MI_INT); 6072 6073 if (latch_status & 1) { 6074 6075 /* For all latched-signal=up : Re-Arm Latch signals */ 6076 REG_WR(bp, NIG_REG_LATCH_STATUS_0 + port*8, 6077 (latch_status & 0xfffe) | (latch_status & 1)); 6078 } 6079 /* For all latched-signal=up,Write original_signal to status */ 6080 } 6081 6082 static void bnx2x_link_int_ack(struct link_params *params, 6083 struct link_vars *vars, u8 is_10g_plus) 6084 { 6085 struct bnx2x *bp = params->bp; 6086 u8 port = params->port; 6087 u32 mask; 6088 /* First reset all status we assume only one line will be 6089 * change at a time 6090 */ 6091 bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4, 6092 (NIG_STATUS_XGXS0_LINK10G | 6093 NIG_STATUS_XGXS0_LINK_STATUS | 6094 NIG_STATUS_SERDES0_LINK_STATUS)); 6095 if (vars->phy_link_up) { 6096 if (USES_WARPCORE(bp)) 6097 mask = NIG_STATUS_XGXS0_LINK_STATUS; 6098 else { 6099 if (is_10g_plus) 6100 mask = NIG_STATUS_XGXS0_LINK10G; 6101 else if (params->switch_cfg == SWITCH_CFG_10G) { 6102 /* Disable the link interrupt by writing 1 to 6103 * the relevant lane in the status register 6104 */ 6105 u32 ser_lane = 6106 ((params->lane_config & 6107 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >> 6108 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT); 6109 mask = ((1 << ser_lane) << 6110 NIG_STATUS_XGXS0_LINK_STATUS_SIZE); 6111 } else 6112 mask = NIG_STATUS_SERDES0_LINK_STATUS; 6113 } 6114 DP(NETIF_MSG_LINK, "Ack link up interrupt with mask 0x%x\n", 6115 mask); 6116 bnx2x_bits_en(bp, 6117 NIG_REG_STATUS_INTERRUPT_PORT0 + port*4, 6118 mask); 6119 } 6120 } 6121 6122 static int bnx2x_format_ver(u32 num, u8 *str, u16 *len) 6123 { 6124 u8 *str_ptr = str; 6125 u32 mask = 0xf0000000; 6126 u8 shift = 8*4; 6127 u8 digit; 6128 u8 remove_leading_zeros = 1; 6129 if (*len < 10) { 6130 /* Need more than 10chars for this format */ 6131 *str_ptr = '\0'; 6132 (*len)--; 6133 return -EINVAL; 6134 } 6135 while (shift > 0) { 6136 6137 shift -= 4; 6138 digit = ((num & mask) >> shift); 6139 if (digit == 0 && remove_leading_zeros) { 6140 mask = mask >> 4; 6141 continue; 6142 } else if (digit < 0xa) 6143 *str_ptr = digit + '0'; 6144 else 6145 *str_ptr = digit - 0xa + 'a'; 6146 remove_leading_zeros = 0; 6147 str_ptr++; 6148 (*len)--; 6149 mask = mask >> 4; 6150 if (shift == 4*4) { 6151 *str_ptr = '.'; 6152 str_ptr++; 6153 (*len)--; 6154 remove_leading_zeros = 1; 6155 } 6156 } 6157 return 0; 6158 } 6159 6160 6161 static int bnx2x_null_format_ver(u32 spirom_ver, u8 *str, u16 *len) 6162 { 6163 str[0] = '\0'; 6164 (*len)--; 6165 return 0; 6166 } 6167 6168 int bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 *version, 6169 u16 len) 6170 { 6171 struct bnx2x *bp; 6172 u32 spirom_ver = 0; 6173 int status = 0; 6174 u8 *ver_p = version; 6175 u16 remain_len = len; 6176 if (version == NULL || params == NULL) 6177 return -EINVAL; 6178 bp = params->bp; 6179 6180 /* Extract first external phy*/ 6181 version[0] = '\0'; 6182 spirom_ver = REG_RD(bp, params->phy[EXT_PHY1].ver_addr); 6183 6184 if (params->phy[EXT_PHY1].format_fw_ver) { 6185 status |= params->phy[EXT_PHY1].format_fw_ver(spirom_ver, 6186 ver_p, 6187 &remain_len); 6188 ver_p += (len - remain_len); 6189 } 6190 if ((params->num_phys == MAX_PHYS) && 6191 (params->phy[EXT_PHY2].ver_addr != 0)) { 6192 spirom_ver = REG_RD(bp, params->phy[EXT_PHY2].ver_addr); 6193 if (params->phy[EXT_PHY2].format_fw_ver) { 6194 *ver_p = '/'; 6195 ver_p++; 6196 remain_len--; 6197 status |= params->phy[EXT_PHY2].format_fw_ver( 6198 spirom_ver, 6199 ver_p, 6200 &remain_len); 6201 ver_p = version + (len - remain_len); 6202 } 6203 } 6204 *ver_p = '\0'; 6205 return status; 6206 } 6207 6208 static void bnx2x_set_xgxs_loopback(struct bnx2x_phy *phy, 6209 struct link_params *params) 6210 { 6211 u8 port = params->port; 6212 struct bnx2x *bp = params->bp; 6213 6214 if (phy->req_line_speed != SPEED_1000) { 6215 u32 md_devad = 0; 6216 6217 DP(NETIF_MSG_LINK, "XGXS 10G loopback enable\n"); 6218 6219 if (!CHIP_IS_E3(bp)) { 6220 /* Change the uni_phy_addr in the nig */ 6221 md_devad = REG_RD(bp, (NIG_REG_XGXS0_CTRL_MD_DEVAD + 6222 port*0x18)); 6223 6224 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, 6225 0x5); 6226 } 6227 6228 bnx2x_cl45_write(bp, phy, 6229 5, 6230 (MDIO_REG_BANK_AER_BLOCK + 6231 (MDIO_AER_BLOCK_AER_REG & 0xf)), 6232 0x2800); 6233 6234 bnx2x_cl45_write(bp, phy, 6235 5, 6236 (MDIO_REG_BANK_CL73_IEEEB0 + 6237 (MDIO_CL73_IEEEB0_CL73_AN_CONTROL & 0xf)), 6238 0x6041); 6239 msleep(200); 6240 /* Set aer mmd back */ 6241 bnx2x_set_aer_mmd(params, phy); 6242 6243 if (!CHIP_IS_E3(bp)) { 6244 /* And md_devad */ 6245 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, 6246 md_devad); 6247 } 6248 } else { 6249 u16 mii_ctrl; 6250 DP(NETIF_MSG_LINK, "XGXS 1G loopback enable\n"); 6251 bnx2x_cl45_read(bp, phy, 5, 6252 (MDIO_REG_BANK_COMBO_IEEE0 + 6253 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)), 6254 &mii_ctrl); 6255 bnx2x_cl45_write(bp, phy, 5, 6256 (MDIO_REG_BANK_COMBO_IEEE0 + 6257 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)), 6258 mii_ctrl | 6259 MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK); 6260 } 6261 } 6262 6263 int bnx2x_set_led(struct link_params *params, 6264 struct link_vars *vars, u8 mode, u32 speed) 6265 { 6266 u8 port = params->port; 6267 u16 hw_led_mode = params->hw_led_mode; 6268 int rc = 0; 6269 u8 phy_idx; 6270 u32 tmp; 6271 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; 6272 struct bnx2x *bp = params->bp; 6273 DP(NETIF_MSG_LINK, "bnx2x_set_led: port %x, mode %d\n", port, mode); 6274 DP(NETIF_MSG_LINK, "speed 0x%x, hw_led_mode 0x%x\n", 6275 speed, hw_led_mode); 6276 /* In case */ 6277 for (phy_idx = EXT_PHY1; phy_idx < MAX_PHYS; phy_idx++) { 6278 if (params->phy[phy_idx].set_link_led) { 6279 params->phy[phy_idx].set_link_led( 6280 ¶ms->phy[phy_idx], params, mode); 6281 } 6282 } 6283 6284 switch (mode) { 6285 case LED_MODE_FRONT_PANEL_OFF: 6286 case LED_MODE_OFF: 6287 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 0); 6288 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 6289 SHARED_HW_CFG_LED_MAC1); 6290 6291 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED); 6292 if (params->phy[EXT_PHY1].type == 6293 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) 6294 tmp &= ~(EMAC_LED_1000MB_OVERRIDE | 6295 EMAC_LED_100MB_OVERRIDE | 6296 EMAC_LED_10MB_OVERRIDE); 6297 else 6298 tmp |= EMAC_LED_OVERRIDE; 6299 6300 EMAC_WR(bp, EMAC_REG_EMAC_LED, tmp); 6301 break; 6302 6303 case LED_MODE_OPER: 6304 /* For all other phys, OPER mode is same as ON, so in case 6305 * link is down, do nothing 6306 */ 6307 if (!vars->link_up) 6308 break; 6309 case LED_MODE_ON: 6310 if (((params->phy[EXT_PHY1].type == 6311 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) || 6312 (params->phy[EXT_PHY1].type == 6313 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722)) && 6314 CHIP_IS_E2(bp) && params->num_phys == 2) { 6315 /* This is a work-around for E2+8727 Configurations */ 6316 if (mode == LED_MODE_ON || 6317 speed == SPEED_10000){ 6318 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0); 6319 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1); 6320 6321 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED); 6322 EMAC_WR(bp, EMAC_REG_EMAC_LED, 6323 (tmp | EMAC_LED_OVERRIDE)); 6324 /* Return here without enabling traffic 6325 * LED blink and setting rate in ON mode. 6326 * In oper mode, enabling LED blink 6327 * and setting rate is needed. 6328 */ 6329 if (mode == LED_MODE_ON) 6330 return rc; 6331 } 6332 } else if (SINGLE_MEDIA_DIRECT(params)) { 6333 /* This is a work-around for HW issue found when link 6334 * is up in CL73 6335 */ 6336 if ((!CHIP_IS_E3(bp)) || 6337 (CHIP_IS_E3(bp) && 6338 mode == LED_MODE_ON)) 6339 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1); 6340 6341 if (CHIP_IS_E1x(bp) || 6342 CHIP_IS_E2(bp) || 6343 (mode == LED_MODE_ON)) 6344 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0); 6345 else 6346 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 6347 hw_led_mode); 6348 } else if ((params->phy[EXT_PHY1].type == 6349 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) && 6350 (mode == LED_MODE_ON)) { 6351 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0); 6352 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED); 6353 EMAC_WR(bp, EMAC_REG_EMAC_LED, tmp | 6354 EMAC_LED_OVERRIDE | EMAC_LED_1000MB_OVERRIDE); 6355 /* Break here; otherwise, it'll disable the 6356 * intended override. 6357 */ 6358 break; 6359 } else { 6360 u32 nig_led_mode = ((params->hw_led_mode << 6361 SHARED_HW_CFG_LED_MODE_SHIFT) == 6362 SHARED_HW_CFG_LED_EXTPHY2) ? 6363 (SHARED_HW_CFG_LED_PHY1 >> 6364 SHARED_HW_CFG_LED_MODE_SHIFT) : hw_led_mode; 6365 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 6366 nig_led_mode); 6367 } 6368 6369 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 0); 6370 /* Set blinking rate to ~15.9Hz */ 6371 if (CHIP_IS_E3(bp)) 6372 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4, 6373 LED_BLINK_RATE_VAL_E3); 6374 else 6375 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4, 6376 LED_BLINK_RATE_VAL_E1X_E2); 6377 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 + 6378 port*4, 1); 6379 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED); 6380 EMAC_WR(bp, EMAC_REG_EMAC_LED, 6381 (tmp & (~EMAC_LED_OVERRIDE))); 6382 6383 if (CHIP_IS_E1(bp) && 6384 ((speed == SPEED_2500) || 6385 (speed == SPEED_1000) || 6386 (speed == SPEED_100) || 6387 (speed == SPEED_10))) { 6388 /* For speeds less than 10G LED scheme is different */ 6389 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 6390 + port*4, 1); 6391 REG_WR(bp, NIG_REG_LED_CONTROL_TRAFFIC_P0 + 6392 port*4, 0); 6393 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 + 6394 port*4, 1); 6395 } 6396 break; 6397 6398 default: 6399 rc = -EINVAL; 6400 DP(NETIF_MSG_LINK, "bnx2x_set_led: Invalid led mode %d\n", 6401 mode); 6402 break; 6403 } 6404 return rc; 6405 6406 } 6407 6408 /* This function comes to reflect the actual link state read DIRECTLY from the 6409 * HW 6410 */ 6411 int bnx2x_test_link(struct link_params *params, struct link_vars *vars, 6412 u8 is_serdes) 6413 { 6414 struct bnx2x *bp = params->bp; 6415 u16 gp_status = 0, phy_index = 0; 6416 u8 ext_phy_link_up = 0, serdes_phy_type; 6417 struct link_vars temp_vars; 6418 struct bnx2x_phy *int_phy = ¶ms->phy[INT_PHY]; 6419 6420 if (CHIP_IS_E3(bp)) { 6421 u16 link_up; 6422 if (params->req_line_speed[LINK_CONFIG_IDX(INT_PHY)] 6423 > SPEED_10000) { 6424 /* Check 20G link */ 6425 bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD, 6426 1, &link_up); 6427 bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD, 6428 1, &link_up); 6429 link_up &= (1<<2); 6430 } else { 6431 /* Check 10G link and below*/ 6432 u8 lane = bnx2x_get_warpcore_lane(int_phy, params); 6433 bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD, 6434 MDIO_WC_REG_GP2_STATUS_GP_2_1, 6435 &gp_status); 6436 gp_status = ((gp_status >> 8) & 0xf) | 6437 ((gp_status >> 12) & 0xf); 6438 link_up = gp_status & (1 << lane); 6439 } 6440 if (!link_up) 6441 return -ESRCH; 6442 } else { 6443 CL22_RD_OVER_CL45(bp, int_phy, 6444 MDIO_REG_BANK_GP_STATUS, 6445 MDIO_GP_STATUS_TOP_AN_STATUS1, 6446 &gp_status); 6447 /* Link is up only if both local phy and external phy are up */ 6448 if (!(gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS)) 6449 return -ESRCH; 6450 } 6451 /* In XGXS loopback mode, do not check external PHY */ 6452 if (params->loopback_mode == LOOPBACK_XGXS) 6453 return 0; 6454 6455 switch (params->num_phys) { 6456 case 1: 6457 /* No external PHY */ 6458 return 0; 6459 case 2: 6460 ext_phy_link_up = params->phy[EXT_PHY1].read_status( 6461 ¶ms->phy[EXT_PHY1], 6462 params, &temp_vars); 6463 break; 6464 case 3: /* Dual Media */ 6465 for (phy_index = EXT_PHY1; phy_index < params->num_phys; 6466 phy_index++) { 6467 serdes_phy_type = ((params->phy[phy_index].media_type == 6468 ETH_PHY_SFPP_10G_FIBER) || 6469 (params->phy[phy_index].media_type == 6470 ETH_PHY_SFP_1G_FIBER) || 6471 (params->phy[phy_index].media_type == 6472 ETH_PHY_XFP_FIBER) || 6473 (params->phy[phy_index].media_type == 6474 ETH_PHY_DA_TWINAX)); 6475 6476 if (is_serdes != serdes_phy_type) 6477 continue; 6478 if (params->phy[phy_index].read_status) { 6479 ext_phy_link_up |= 6480 params->phy[phy_index].read_status( 6481 ¶ms->phy[phy_index], 6482 params, &temp_vars); 6483 } 6484 } 6485 break; 6486 } 6487 if (ext_phy_link_up) 6488 return 0; 6489 return -ESRCH; 6490 } 6491 6492 static int bnx2x_link_initialize(struct link_params *params, 6493 struct link_vars *vars) 6494 { 6495 u8 phy_index, non_ext_phy; 6496 struct bnx2x *bp = params->bp; 6497 /* In case of external phy existence, the line speed would be the 6498 * line speed linked up by the external phy. In case it is direct 6499 * only, then the line_speed during initialization will be 6500 * equal to the req_line_speed 6501 */ 6502 vars->line_speed = params->phy[INT_PHY].req_line_speed; 6503 6504 /* Initialize the internal phy in case this is a direct board 6505 * (no external phys), or this board has external phy which requires 6506 * to first. 6507 */ 6508 if (!USES_WARPCORE(bp)) 6509 bnx2x_prepare_xgxs(¶ms->phy[INT_PHY], params, vars); 6510 /* init ext phy and enable link state int */ 6511 non_ext_phy = (SINGLE_MEDIA_DIRECT(params) || 6512 (params->loopback_mode == LOOPBACK_XGXS)); 6513 6514 if (non_ext_phy || 6515 (params->phy[EXT_PHY1].flags & FLAGS_INIT_XGXS_FIRST) || 6516 (params->loopback_mode == LOOPBACK_EXT_PHY)) { 6517 struct bnx2x_phy *phy = ¶ms->phy[INT_PHY]; 6518 if (vars->line_speed == SPEED_AUTO_NEG && 6519 (CHIP_IS_E1x(bp) || 6520 CHIP_IS_E2(bp))) 6521 bnx2x_set_parallel_detection(phy, params); 6522 if (params->phy[INT_PHY].config_init) 6523 params->phy[INT_PHY].config_init(phy, params, vars); 6524 } 6525 6526 /* Re-read this value in case it was changed inside config_init due to 6527 * limitations of optic module 6528 */ 6529 vars->line_speed = params->phy[INT_PHY].req_line_speed; 6530 6531 /* Init external phy*/ 6532 if (non_ext_phy) { 6533 if (params->phy[INT_PHY].supported & 6534 SUPPORTED_FIBRE) 6535 vars->link_status |= LINK_STATUS_SERDES_LINK; 6536 } else { 6537 for (phy_index = EXT_PHY1; phy_index < params->num_phys; 6538 phy_index++) { 6539 /* No need to initialize second phy in case of first 6540 * phy only selection. In case of second phy, we do 6541 * need to initialize the first phy, since they are 6542 * connected. 6543 */ 6544 if (params->phy[phy_index].supported & 6545 SUPPORTED_FIBRE) 6546 vars->link_status |= LINK_STATUS_SERDES_LINK; 6547 6548 if (phy_index == EXT_PHY2 && 6549 (bnx2x_phy_selection(params) == 6550 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY)) { 6551 DP(NETIF_MSG_LINK, 6552 "Not initializing second phy\n"); 6553 continue; 6554 } 6555 params->phy[phy_index].config_init( 6556 ¶ms->phy[phy_index], 6557 params, vars); 6558 } 6559 } 6560 /* Reset the interrupt indication after phy was initialized */ 6561 bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + 6562 params->port*4, 6563 (NIG_STATUS_XGXS0_LINK10G | 6564 NIG_STATUS_XGXS0_LINK_STATUS | 6565 NIG_STATUS_SERDES0_LINK_STATUS | 6566 NIG_MASK_MI_INT)); 6567 return 0; 6568 } 6569 6570 static void bnx2x_int_link_reset(struct bnx2x_phy *phy, 6571 struct link_params *params) 6572 { 6573 /* Reset the SerDes/XGXS */ 6574 REG_WR(params->bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, 6575 (0x1ff << (params->port*16))); 6576 } 6577 6578 static void bnx2x_common_ext_link_reset(struct bnx2x_phy *phy, 6579 struct link_params *params) 6580 { 6581 struct bnx2x *bp = params->bp; 6582 u8 gpio_port; 6583 /* HW reset */ 6584 if (CHIP_IS_E2(bp)) 6585 gpio_port = BP_PATH(bp); 6586 else 6587 gpio_port = params->port; 6588 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, 6589 MISC_REGISTERS_GPIO_OUTPUT_LOW, 6590 gpio_port); 6591 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 6592 MISC_REGISTERS_GPIO_OUTPUT_LOW, 6593 gpio_port); 6594 DP(NETIF_MSG_LINK, "reset external PHY\n"); 6595 } 6596 6597 static int bnx2x_update_link_down(struct link_params *params, 6598 struct link_vars *vars) 6599 { 6600 struct bnx2x *bp = params->bp; 6601 u8 port = params->port; 6602 6603 DP(NETIF_MSG_LINK, "Port %x: Link is down\n", port); 6604 bnx2x_set_led(params, vars, LED_MODE_OFF, 0); 6605 vars->phy_flags &= ~PHY_PHYSICAL_LINK_FLAG; 6606 /* Indicate no mac active */ 6607 vars->mac_type = MAC_TYPE_NONE; 6608 6609 /* Update shared memory */ 6610 vars->link_status &= ~LINK_UPDATE_MASK; 6611 vars->line_speed = 0; 6612 bnx2x_update_mng(params, vars->link_status); 6613 6614 /* Activate nig drain */ 6615 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1); 6616 6617 /* Disable emac */ 6618 if (!CHIP_IS_E3(bp)) 6619 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0); 6620 6621 usleep_range(10000, 20000); 6622 /* Reset BigMac/Xmac */ 6623 if (CHIP_IS_E1x(bp) || 6624 CHIP_IS_E2(bp)) 6625 bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 0); 6626 6627 if (CHIP_IS_E3(bp)) { 6628 /* Prevent LPI Generation by chip */ 6629 REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2), 6630 0); 6631 REG_WR(bp, MISC_REG_CPMU_LP_MASK_ENT_P0 + (params->port << 2), 6632 0); 6633 vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK | 6634 SHMEM_EEE_ACTIVE_BIT); 6635 6636 bnx2x_update_mng_eee(params, vars->eee_status); 6637 bnx2x_set_xmac_rxtx(params, 0); 6638 bnx2x_set_umac_rxtx(params, 0); 6639 } 6640 6641 return 0; 6642 } 6643 6644 static int bnx2x_update_link_up(struct link_params *params, 6645 struct link_vars *vars, 6646 u8 link_10g) 6647 { 6648 struct bnx2x *bp = params->bp; 6649 u8 phy_idx, port = params->port; 6650 int rc = 0; 6651 6652 vars->link_status |= (LINK_STATUS_LINK_UP | 6653 LINK_STATUS_PHYSICAL_LINK_FLAG); 6654 vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG; 6655 6656 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) 6657 vars->link_status |= 6658 LINK_STATUS_TX_FLOW_CONTROL_ENABLED; 6659 6660 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX) 6661 vars->link_status |= 6662 LINK_STATUS_RX_FLOW_CONTROL_ENABLED; 6663 if (USES_WARPCORE(bp)) { 6664 if (link_10g) { 6665 if (bnx2x_xmac_enable(params, vars, 0) == 6666 -ESRCH) { 6667 DP(NETIF_MSG_LINK, "Found errors on XMAC\n"); 6668 vars->link_up = 0; 6669 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG; 6670 vars->link_status &= ~LINK_STATUS_LINK_UP; 6671 } 6672 } else 6673 bnx2x_umac_enable(params, vars, 0); 6674 bnx2x_set_led(params, vars, 6675 LED_MODE_OPER, vars->line_speed); 6676 6677 if ((vars->eee_status & SHMEM_EEE_ACTIVE_BIT) && 6678 (vars->eee_status & SHMEM_EEE_LPI_REQUESTED_BIT)) { 6679 DP(NETIF_MSG_LINK, "Enabling LPI assertion\n"); 6680 REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + 6681 (params->port << 2), 1); 6682 REG_WR(bp, MISC_REG_CPMU_LP_DR_ENABLE, 1); 6683 REG_WR(bp, MISC_REG_CPMU_LP_MASK_ENT_P0 + 6684 (params->port << 2), 0xfc20); 6685 } 6686 } 6687 if ((CHIP_IS_E1x(bp) || 6688 CHIP_IS_E2(bp))) { 6689 if (link_10g) { 6690 if (bnx2x_bmac_enable(params, vars, 0, 1) == 6691 -ESRCH) { 6692 DP(NETIF_MSG_LINK, "Found errors on BMAC\n"); 6693 vars->link_up = 0; 6694 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG; 6695 vars->link_status &= ~LINK_STATUS_LINK_UP; 6696 } 6697 6698 bnx2x_set_led(params, vars, 6699 LED_MODE_OPER, SPEED_10000); 6700 } else { 6701 rc = bnx2x_emac_program(params, vars); 6702 bnx2x_emac_enable(params, vars, 0); 6703 6704 /* AN complete? */ 6705 if ((vars->link_status & 6706 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) 6707 && (!(vars->phy_flags & PHY_SGMII_FLAG)) && 6708 SINGLE_MEDIA_DIRECT(params)) 6709 bnx2x_set_gmii_tx_driver(params); 6710 } 6711 } 6712 6713 /* PBF - link up */ 6714 if (CHIP_IS_E1x(bp)) 6715 rc |= bnx2x_pbf_update(params, vars->flow_ctrl, 6716 vars->line_speed); 6717 6718 /* Disable drain */ 6719 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0); 6720 6721 /* Update shared memory */ 6722 bnx2x_update_mng(params, vars->link_status); 6723 bnx2x_update_mng_eee(params, vars->eee_status); 6724 /* Check remote fault */ 6725 for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) { 6726 if (params->phy[phy_idx].flags & FLAGS_TX_ERROR_CHECK) { 6727 bnx2x_check_half_open_conn(params, vars, 0); 6728 break; 6729 } 6730 } 6731 msleep(20); 6732 return rc; 6733 } 6734 /* The bnx2x_link_update function should be called upon link 6735 * interrupt. 6736 * Link is considered up as follows: 6737 * - DIRECT_SINGLE_MEDIA - Only XGXS link (internal link) needs 6738 * to be up 6739 * - SINGLE_MEDIA - The link between the 577xx and the external 6740 * phy (XGXS) need to up as well as the external link of the 6741 * phy (PHY_EXT1) 6742 * - DUAL_MEDIA - The link between the 577xx and the first 6743 * external phy needs to be up, and at least one of the 2 6744 * external phy link must be up. 6745 */ 6746 int bnx2x_link_update(struct link_params *params, struct link_vars *vars) 6747 { 6748 struct bnx2x *bp = params->bp; 6749 struct link_vars phy_vars[MAX_PHYS]; 6750 u8 port = params->port; 6751 u8 link_10g_plus, phy_index; 6752 u8 ext_phy_link_up = 0, cur_link_up; 6753 int rc = 0; 6754 u8 is_mi_int = 0; 6755 u16 ext_phy_line_speed = 0, prev_line_speed = vars->line_speed; 6756 u8 active_external_phy = INT_PHY; 6757 vars->phy_flags &= ~PHY_HALF_OPEN_CONN_FLAG; 6758 vars->link_status &= ~LINK_UPDATE_MASK; 6759 for (phy_index = INT_PHY; phy_index < params->num_phys; 6760 phy_index++) { 6761 phy_vars[phy_index].flow_ctrl = 0; 6762 phy_vars[phy_index].link_status = 0; 6763 phy_vars[phy_index].line_speed = 0; 6764 phy_vars[phy_index].duplex = DUPLEX_FULL; 6765 phy_vars[phy_index].phy_link_up = 0; 6766 phy_vars[phy_index].link_up = 0; 6767 phy_vars[phy_index].fault_detected = 0; 6768 /* different consideration, since vars holds inner state */ 6769 phy_vars[phy_index].eee_status = vars->eee_status; 6770 } 6771 6772 if (USES_WARPCORE(bp)) 6773 bnx2x_set_aer_mmd(params, ¶ms->phy[INT_PHY]); 6774 6775 DP(NETIF_MSG_LINK, "port %x, XGXS?%x, int_status 0x%x\n", 6776 port, (vars->phy_flags & PHY_XGXS_FLAG), 6777 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4)); 6778 6779 is_mi_int = (u8)(REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + 6780 port*0x18) > 0); 6781 DP(NETIF_MSG_LINK, "int_mask 0x%x MI_INT %x, SERDES_LINK %x\n", 6782 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4), 6783 is_mi_int, 6784 REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c)); 6785 6786 DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n", 6787 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68), 6788 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68)); 6789 6790 /* Disable emac */ 6791 if (!CHIP_IS_E3(bp)) 6792 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0); 6793 6794 /* Step 1: 6795 * Check external link change only for external phys, and apply 6796 * priority selection between them in case the link on both phys 6797 * is up. Note that instead of the common vars, a temporary 6798 * vars argument is used since each phy may have different link/ 6799 * speed/duplex result 6800 */ 6801 for (phy_index = EXT_PHY1; phy_index < params->num_phys; 6802 phy_index++) { 6803 struct bnx2x_phy *phy = ¶ms->phy[phy_index]; 6804 if (!phy->read_status) 6805 continue; 6806 /* Read link status and params of this ext phy */ 6807 cur_link_up = phy->read_status(phy, params, 6808 &phy_vars[phy_index]); 6809 if (cur_link_up) { 6810 DP(NETIF_MSG_LINK, "phy in index %d link is up\n", 6811 phy_index); 6812 } else { 6813 DP(NETIF_MSG_LINK, "phy in index %d link is down\n", 6814 phy_index); 6815 continue; 6816 } 6817 6818 if (!ext_phy_link_up) { 6819 ext_phy_link_up = 1; 6820 active_external_phy = phy_index; 6821 } else { 6822 switch (bnx2x_phy_selection(params)) { 6823 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT: 6824 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY: 6825 /* In this option, the first PHY makes sure to pass the 6826 * traffic through itself only. 6827 * Its not clear how to reset the link on the second phy 6828 */ 6829 active_external_phy = EXT_PHY1; 6830 break; 6831 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY: 6832 /* In this option, the first PHY makes sure to pass the 6833 * traffic through the second PHY. 6834 */ 6835 active_external_phy = EXT_PHY2; 6836 break; 6837 default: 6838 /* Link indication on both PHYs with the following cases 6839 * is invalid: 6840 * - FIRST_PHY means that second phy wasn't initialized, 6841 * hence its link is expected to be down 6842 * - SECOND_PHY means that first phy should not be able 6843 * to link up by itself (using configuration) 6844 * - DEFAULT should be overriden during initialiazation 6845 */ 6846 DP(NETIF_MSG_LINK, "Invalid link indication" 6847 "mpc=0x%x. DISABLING LINK !!!\n", 6848 params->multi_phy_config); 6849 ext_phy_link_up = 0; 6850 break; 6851 } 6852 } 6853 } 6854 prev_line_speed = vars->line_speed; 6855 /* Step 2: 6856 * Read the status of the internal phy. In case of 6857 * DIRECT_SINGLE_MEDIA board, this link is the external link, 6858 * otherwise this is the link between the 577xx and the first 6859 * external phy 6860 */ 6861 if (params->phy[INT_PHY].read_status) 6862 params->phy[INT_PHY].read_status( 6863 ¶ms->phy[INT_PHY], 6864 params, vars); 6865 /* The INT_PHY flow control reside in the vars. This include the 6866 * case where the speed or flow control are not set to AUTO. 6867 * Otherwise, the active external phy flow control result is set 6868 * to the vars. The ext_phy_line_speed is needed to check if the 6869 * speed is different between the internal phy and external phy. 6870 * This case may be result of intermediate link speed change. 6871 */ 6872 if (active_external_phy > INT_PHY) { 6873 vars->flow_ctrl = phy_vars[active_external_phy].flow_ctrl; 6874 /* Link speed is taken from the XGXS. AN and FC result from 6875 * the external phy. 6876 */ 6877 vars->link_status |= phy_vars[active_external_phy].link_status; 6878 6879 /* if active_external_phy is first PHY and link is up - disable 6880 * disable TX on second external PHY 6881 */ 6882 if (active_external_phy == EXT_PHY1) { 6883 if (params->phy[EXT_PHY2].phy_specific_func) { 6884 DP(NETIF_MSG_LINK, 6885 "Disabling TX on EXT_PHY2\n"); 6886 params->phy[EXT_PHY2].phy_specific_func( 6887 ¶ms->phy[EXT_PHY2], 6888 params, DISABLE_TX); 6889 } 6890 } 6891 6892 ext_phy_line_speed = phy_vars[active_external_phy].line_speed; 6893 vars->duplex = phy_vars[active_external_phy].duplex; 6894 if (params->phy[active_external_phy].supported & 6895 SUPPORTED_FIBRE) 6896 vars->link_status |= LINK_STATUS_SERDES_LINK; 6897 else 6898 vars->link_status &= ~LINK_STATUS_SERDES_LINK; 6899 6900 vars->eee_status = phy_vars[active_external_phy].eee_status; 6901 6902 DP(NETIF_MSG_LINK, "Active external phy selected: %x\n", 6903 active_external_phy); 6904 } 6905 6906 for (phy_index = EXT_PHY1; phy_index < params->num_phys; 6907 phy_index++) { 6908 if (params->phy[phy_index].flags & 6909 FLAGS_REARM_LATCH_SIGNAL) { 6910 bnx2x_rearm_latch_signal(bp, port, 6911 phy_index == 6912 active_external_phy); 6913 break; 6914 } 6915 } 6916 DP(NETIF_MSG_LINK, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x," 6917 " ext_phy_line_speed = %d\n", vars->flow_ctrl, 6918 vars->link_status, ext_phy_line_speed); 6919 /* Upon link speed change set the NIG into drain mode. Comes to 6920 * deals with possible FIFO glitch due to clk change when speed 6921 * is decreased without link down indicator 6922 */ 6923 6924 if (vars->phy_link_up) { 6925 if (!(SINGLE_MEDIA_DIRECT(params)) && ext_phy_link_up && 6926 (ext_phy_line_speed != vars->line_speed)) { 6927 DP(NETIF_MSG_LINK, "Internal link speed %d is" 6928 " different than the external" 6929 " link speed %d\n", vars->line_speed, 6930 ext_phy_line_speed); 6931 vars->phy_link_up = 0; 6932 } else if (prev_line_speed != vars->line_speed) { 6933 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 6934 0); 6935 usleep_range(1000, 2000); 6936 } 6937 } 6938 6939 /* Anything 10 and over uses the bmac */ 6940 link_10g_plus = (vars->line_speed >= SPEED_10000); 6941 6942 bnx2x_link_int_ack(params, vars, link_10g_plus); 6943 6944 /* In case external phy link is up, and internal link is down 6945 * (not initialized yet probably after link initialization, it 6946 * needs to be initialized. 6947 * Note that after link down-up as result of cable plug, the xgxs 6948 * link would probably become up again without the need 6949 * initialize it 6950 */ 6951 if (!(SINGLE_MEDIA_DIRECT(params))) { 6952 DP(NETIF_MSG_LINK, "ext_phy_link_up = %d, int_link_up = %d," 6953 " init_preceding = %d\n", ext_phy_link_up, 6954 vars->phy_link_up, 6955 params->phy[EXT_PHY1].flags & 6956 FLAGS_INIT_XGXS_FIRST); 6957 if (!(params->phy[EXT_PHY1].flags & 6958 FLAGS_INIT_XGXS_FIRST) 6959 && ext_phy_link_up && !vars->phy_link_up) { 6960 vars->line_speed = ext_phy_line_speed; 6961 if (vars->line_speed < SPEED_1000) 6962 vars->phy_flags |= PHY_SGMII_FLAG; 6963 else 6964 vars->phy_flags &= ~PHY_SGMII_FLAG; 6965 6966 if (params->phy[INT_PHY].config_init) 6967 params->phy[INT_PHY].config_init( 6968 ¶ms->phy[INT_PHY], params, 6969 vars); 6970 } 6971 } 6972 /* Link is up only if both local phy and external phy (in case of 6973 * non-direct board) are up and no fault detected on active PHY. 6974 */ 6975 vars->link_up = (vars->phy_link_up && 6976 (ext_phy_link_up || 6977 SINGLE_MEDIA_DIRECT(params)) && 6978 (phy_vars[active_external_phy].fault_detected == 0)); 6979 6980 /* Update the PFC configuration in case it was changed */ 6981 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) 6982 vars->link_status |= LINK_STATUS_PFC_ENABLED; 6983 else 6984 vars->link_status &= ~LINK_STATUS_PFC_ENABLED; 6985 6986 if (vars->link_up) 6987 rc = bnx2x_update_link_up(params, vars, link_10g_plus); 6988 else 6989 rc = bnx2x_update_link_down(params, vars); 6990 6991 /* Update MCP link status was changed */ 6992 if (params->feature_config_flags & FEATURE_CONFIG_BC_SUPPORTS_AFEX) 6993 bnx2x_fw_command(bp, DRV_MSG_CODE_LINK_STATUS_CHANGED, 0); 6994 6995 return rc; 6996 } 6997 6998 /*****************************************************************************/ 6999 /* External Phy section */ 7000 /*****************************************************************************/ 7001 void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port) 7002 { 7003 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, 7004 MISC_REGISTERS_GPIO_OUTPUT_LOW, port); 7005 usleep_range(1000, 2000); 7006 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, 7007 MISC_REGISTERS_GPIO_OUTPUT_HIGH, port); 7008 } 7009 7010 static void bnx2x_save_spirom_version(struct bnx2x *bp, u8 port, 7011 u32 spirom_ver, u32 ver_addr) 7012 { 7013 DP(NETIF_MSG_LINK, "FW version 0x%x:0x%x for port %d\n", 7014 (u16)(spirom_ver>>16), (u16)spirom_ver, port); 7015 7016 if (ver_addr) 7017 REG_WR(bp, ver_addr, spirom_ver); 7018 } 7019 7020 static void bnx2x_save_bcm_spirom_ver(struct bnx2x *bp, 7021 struct bnx2x_phy *phy, 7022 u8 port) 7023 { 7024 u16 fw_ver1, fw_ver2; 7025 7026 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 7027 MDIO_PMA_REG_ROM_VER1, &fw_ver1); 7028 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 7029 MDIO_PMA_REG_ROM_VER2, &fw_ver2); 7030 bnx2x_save_spirom_version(bp, port, (u32)(fw_ver1<<16 | fw_ver2), 7031 phy->ver_addr); 7032 } 7033 7034 static void bnx2x_ext_phy_10G_an_resolve(struct bnx2x *bp, 7035 struct bnx2x_phy *phy, 7036 struct link_vars *vars) 7037 { 7038 u16 val; 7039 bnx2x_cl45_read(bp, phy, 7040 MDIO_AN_DEVAD, 7041 MDIO_AN_REG_STATUS, &val); 7042 bnx2x_cl45_read(bp, phy, 7043 MDIO_AN_DEVAD, 7044 MDIO_AN_REG_STATUS, &val); 7045 if (val & (1<<5)) 7046 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; 7047 if ((val & (1<<0)) == 0) 7048 vars->link_status |= LINK_STATUS_PARALLEL_DETECTION_USED; 7049 } 7050 7051 /******************************************************************/ 7052 /* common BCM8073/BCM8727 PHY SECTION */ 7053 /******************************************************************/ 7054 static void bnx2x_8073_resolve_fc(struct bnx2x_phy *phy, 7055 struct link_params *params, 7056 struct link_vars *vars) 7057 { 7058 struct bnx2x *bp = params->bp; 7059 if (phy->req_line_speed == SPEED_10 || 7060 phy->req_line_speed == SPEED_100) { 7061 vars->flow_ctrl = phy->req_flow_ctrl; 7062 return; 7063 } 7064 7065 if (bnx2x_ext_phy_resolve_fc(phy, params, vars) && 7066 (vars->flow_ctrl == BNX2X_FLOW_CTRL_NONE)) { 7067 u16 pause_result; 7068 u16 ld_pause; /* local */ 7069 u16 lp_pause; /* link partner */ 7070 bnx2x_cl45_read(bp, phy, 7071 MDIO_AN_DEVAD, 7072 MDIO_AN_REG_CL37_FC_LD, &ld_pause); 7073 7074 bnx2x_cl45_read(bp, phy, 7075 MDIO_AN_DEVAD, 7076 MDIO_AN_REG_CL37_FC_LP, &lp_pause); 7077 pause_result = (ld_pause & 7078 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 5; 7079 pause_result |= (lp_pause & 7080 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 7; 7081 7082 bnx2x_pause_resolve(vars, pause_result); 7083 DP(NETIF_MSG_LINK, "Ext PHY CL37 pause result 0x%x\n", 7084 pause_result); 7085 } 7086 } 7087 static int bnx2x_8073_8727_external_rom_boot(struct bnx2x *bp, 7088 struct bnx2x_phy *phy, 7089 u8 port) 7090 { 7091 u32 count = 0; 7092 u16 fw_ver1, fw_msgout; 7093 int rc = 0; 7094 7095 /* Boot port from external ROM */ 7096 /* EDC grst */ 7097 bnx2x_cl45_write(bp, phy, 7098 MDIO_PMA_DEVAD, 7099 MDIO_PMA_REG_GEN_CTRL, 7100 0x0001); 7101 7102 /* Ucode reboot and rst */ 7103 bnx2x_cl45_write(bp, phy, 7104 MDIO_PMA_DEVAD, 7105 MDIO_PMA_REG_GEN_CTRL, 7106 0x008c); 7107 7108 bnx2x_cl45_write(bp, phy, 7109 MDIO_PMA_DEVAD, 7110 MDIO_PMA_REG_MISC_CTRL1, 0x0001); 7111 7112 /* Reset internal microprocessor */ 7113 bnx2x_cl45_write(bp, phy, 7114 MDIO_PMA_DEVAD, 7115 MDIO_PMA_REG_GEN_CTRL, 7116 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET); 7117 7118 /* Release srst bit */ 7119 bnx2x_cl45_write(bp, phy, 7120 MDIO_PMA_DEVAD, 7121 MDIO_PMA_REG_GEN_CTRL, 7122 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP); 7123 7124 /* Delay 100ms per the PHY specifications */ 7125 msleep(100); 7126 7127 /* 8073 sometimes taking longer to download */ 7128 do { 7129 count++; 7130 if (count > 300) { 7131 DP(NETIF_MSG_LINK, 7132 "bnx2x_8073_8727_external_rom_boot port %x:" 7133 "Download failed. fw version = 0x%x\n", 7134 port, fw_ver1); 7135 rc = -EINVAL; 7136 break; 7137 } 7138 7139 bnx2x_cl45_read(bp, phy, 7140 MDIO_PMA_DEVAD, 7141 MDIO_PMA_REG_ROM_VER1, &fw_ver1); 7142 bnx2x_cl45_read(bp, phy, 7143 MDIO_PMA_DEVAD, 7144 MDIO_PMA_REG_M8051_MSGOUT_REG, &fw_msgout); 7145 7146 usleep_range(1000, 2000); 7147 } while (fw_ver1 == 0 || fw_ver1 == 0x4321 || 7148 ((fw_msgout & 0xff) != 0x03 && (phy->type == 7149 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073))); 7150 7151 /* Clear ser_boot_ctl bit */ 7152 bnx2x_cl45_write(bp, phy, 7153 MDIO_PMA_DEVAD, 7154 MDIO_PMA_REG_MISC_CTRL1, 0x0000); 7155 bnx2x_save_bcm_spirom_ver(bp, phy, port); 7156 7157 DP(NETIF_MSG_LINK, 7158 "bnx2x_8073_8727_external_rom_boot port %x:" 7159 "Download complete. fw version = 0x%x\n", 7160 port, fw_ver1); 7161 7162 return rc; 7163 } 7164 7165 /******************************************************************/ 7166 /* BCM8073 PHY SECTION */ 7167 /******************************************************************/ 7168 static int bnx2x_8073_is_snr_needed(struct bnx2x *bp, struct bnx2x_phy *phy) 7169 { 7170 /* This is only required for 8073A1, version 102 only */ 7171 u16 val; 7172 7173 /* Read 8073 HW revision*/ 7174 bnx2x_cl45_read(bp, phy, 7175 MDIO_PMA_DEVAD, 7176 MDIO_PMA_REG_8073_CHIP_REV, &val); 7177 7178 if (val != 1) { 7179 /* No need to workaround in 8073 A1 */ 7180 return 0; 7181 } 7182 7183 bnx2x_cl45_read(bp, phy, 7184 MDIO_PMA_DEVAD, 7185 MDIO_PMA_REG_ROM_VER2, &val); 7186 7187 /* SNR should be applied only for version 0x102 */ 7188 if (val != 0x102) 7189 return 0; 7190 7191 return 1; 7192 } 7193 7194 static int bnx2x_8073_xaui_wa(struct bnx2x *bp, struct bnx2x_phy *phy) 7195 { 7196 u16 val, cnt, cnt1 ; 7197 7198 bnx2x_cl45_read(bp, phy, 7199 MDIO_PMA_DEVAD, 7200 MDIO_PMA_REG_8073_CHIP_REV, &val); 7201 7202 if (val > 0) { 7203 /* No need to workaround in 8073 A1 */ 7204 return 0; 7205 } 7206 /* XAUI workaround in 8073 A0: */ 7207 7208 /* After loading the boot ROM and restarting Autoneg, poll 7209 * Dev1, Reg $C820: 7210 */ 7211 7212 for (cnt = 0; cnt < 1000; cnt++) { 7213 bnx2x_cl45_read(bp, phy, 7214 MDIO_PMA_DEVAD, 7215 MDIO_PMA_REG_8073_SPEED_LINK_STATUS, 7216 &val); 7217 /* If bit [14] = 0 or bit [13] = 0, continue on with 7218 * system initialization (XAUI work-around not required, as 7219 * these bits indicate 2.5G or 1G link up). 7220 */ 7221 if (!(val & (1<<14)) || !(val & (1<<13))) { 7222 DP(NETIF_MSG_LINK, "XAUI work-around not required\n"); 7223 return 0; 7224 } else if (!(val & (1<<15))) { 7225 DP(NETIF_MSG_LINK, "bit 15 went off\n"); 7226 /* If bit 15 is 0, then poll Dev1, Reg $C841 until it's 7227 * MSB (bit15) goes to 1 (indicating that the XAUI 7228 * workaround has completed), then continue on with 7229 * system initialization. 7230 */ 7231 for (cnt1 = 0; cnt1 < 1000; cnt1++) { 7232 bnx2x_cl45_read(bp, phy, 7233 MDIO_PMA_DEVAD, 7234 MDIO_PMA_REG_8073_XAUI_WA, &val); 7235 if (val & (1<<15)) { 7236 DP(NETIF_MSG_LINK, 7237 "XAUI workaround has completed\n"); 7238 return 0; 7239 } 7240 usleep_range(3000, 6000); 7241 } 7242 break; 7243 } 7244 usleep_range(3000, 6000); 7245 } 7246 DP(NETIF_MSG_LINK, "Warning: XAUI work-around timeout !!!\n"); 7247 return -EINVAL; 7248 } 7249 7250 static void bnx2x_807x_force_10G(struct bnx2x *bp, struct bnx2x_phy *phy) 7251 { 7252 /* Force KR or KX */ 7253 bnx2x_cl45_write(bp, phy, 7254 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040); 7255 bnx2x_cl45_write(bp, phy, 7256 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0x000b); 7257 bnx2x_cl45_write(bp, phy, 7258 MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0000); 7259 bnx2x_cl45_write(bp, phy, 7260 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000); 7261 } 7262 7263 static void bnx2x_8073_set_pause_cl37(struct link_params *params, 7264 struct bnx2x_phy *phy, 7265 struct link_vars *vars) 7266 { 7267 u16 cl37_val; 7268 struct bnx2x *bp = params->bp; 7269 bnx2x_cl45_read(bp, phy, 7270 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &cl37_val); 7271 7272 cl37_val &= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; 7273 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */ 7274 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); 7275 if ((vars->ieee_fc & 7276 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) == 7277 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) { 7278 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC; 7279 } 7280 if ((vars->ieee_fc & 7281 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) == 7282 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) { 7283 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC; 7284 } 7285 if ((vars->ieee_fc & 7286 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) == 7287 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) { 7288 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; 7289 } 7290 DP(NETIF_MSG_LINK, 7291 "Ext phy AN advertize cl37 0x%x\n", cl37_val); 7292 7293 bnx2x_cl45_write(bp, phy, 7294 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, cl37_val); 7295 msleep(500); 7296 } 7297 7298 static void bnx2x_8073_specific_func(struct bnx2x_phy *phy, 7299 struct link_params *params, 7300 u32 action) 7301 { 7302 struct bnx2x *bp = params->bp; 7303 switch (action) { 7304 case PHY_INIT: 7305 /* Enable LASI */ 7306 bnx2x_cl45_write(bp, phy, 7307 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, (1<<2)); 7308 bnx2x_cl45_write(bp, phy, 7309 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0004); 7310 break; 7311 } 7312 } 7313 7314 static int bnx2x_8073_config_init(struct bnx2x_phy *phy, 7315 struct link_params *params, 7316 struct link_vars *vars) 7317 { 7318 struct bnx2x *bp = params->bp; 7319 u16 val = 0, tmp1; 7320 u8 gpio_port; 7321 DP(NETIF_MSG_LINK, "Init 8073\n"); 7322 7323 if (CHIP_IS_E2(bp)) 7324 gpio_port = BP_PATH(bp); 7325 else 7326 gpio_port = params->port; 7327 /* Restore normal power mode*/ 7328 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 7329 MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port); 7330 7331 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, 7332 MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port); 7333 7334 bnx2x_8073_specific_func(phy, params, PHY_INIT); 7335 bnx2x_8073_set_pause_cl37(params, phy, vars); 7336 7337 bnx2x_cl45_read(bp, phy, 7338 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1); 7339 7340 bnx2x_cl45_read(bp, phy, 7341 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1); 7342 7343 DP(NETIF_MSG_LINK, "Before rom RX_ALARM(port1): 0x%x\n", tmp1); 7344 7345 /* Swap polarity if required - Must be done only in non-1G mode */ 7346 if (params->lane_config & PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) { 7347 /* Configure the 8073 to swap _P and _N of the KR lines */ 7348 DP(NETIF_MSG_LINK, "Swapping polarity for the 8073\n"); 7349 /* 10G Rx/Tx and 1G Tx signal polarity swap */ 7350 bnx2x_cl45_read(bp, phy, 7351 MDIO_PMA_DEVAD, 7352 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL, &val); 7353 bnx2x_cl45_write(bp, phy, 7354 MDIO_PMA_DEVAD, 7355 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL, 7356 (val | (3<<9))); 7357 } 7358 7359 7360 /* Enable CL37 BAM */ 7361 if (REG_RD(bp, params->shmem_base + 7362 offsetof(struct shmem_region, dev_info. 7363 port_hw_config[params->port].default_cfg)) & 7364 PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) { 7365 7366 bnx2x_cl45_read(bp, phy, 7367 MDIO_AN_DEVAD, 7368 MDIO_AN_REG_8073_BAM, &val); 7369 bnx2x_cl45_write(bp, phy, 7370 MDIO_AN_DEVAD, 7371 MDIO_AN_REG_8073_BAM, val | 1); 7372 DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n"); 7373 } 7374 if (params->loopback_mode == LOOPBACK_EXT) { 7375 bnx2x_807x_force_10G(bp, phy); 7376 DP(NETIF_MSG_LINK, "Forced speed 10G on 807X\n"); 7377 return 0; 7378 } else { 7379 bnx2x_cl45_write(bp, phy, 7380 MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0002); 7381 } 7382 if (phy->req_line_speed != SPEED_AUTO_NEG) { 7383 if (phy->req_line_speed == SPEED_10000) { 7384 val = (1<<7); 7385 } else if (phy->req_line_speed == SPEED_2500) { 7386 val = (1<<5); 7387 /* Note that 2.5G works only when used with 1G 7388 * advertisement 7389 */ 7390 } else 7391 val = (1<<5); 7392 } else { 7393 val = 0; 7394 if (phy->speed_cap_mask & 7395 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) 7396 val |= (1<<7); 7397 7398 /* Note that 2.5G works only when used with 1G advertisement */ 7399 if (phy->speed_cap_mask & 7400 (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G | 7401 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) 7402 val |= (1<<5); 7403 DP(NETIF_MSG_LINK, "807x autoneg val = 0x%x\n", val); 7404 } 7405 7406 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val); 7407 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, &tmp1); 7408 7409 if (((phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) && 7410 (phy->req_line_speed == SPEED_AUTO_NEG)) || 7411 (phy->req_line_speed == SPEED_2500)) { 7412 u16 phy_ver; 7413 /* Allow 2.5G for A1 and above */ 7414 bnx2x_cl45_read(bp, phy, 7415 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV, 7416 &phy_ver); 7417 DP(NETIF_MSG_LINK, "Add 2.5G\n"); 7418 if (phy_ver > 0) 7419 tmp1 |= 1; 7420 else 7421 tmp1 &= 0xfffe; 7422 } else { 7423 DP(NETIF_MSG_LINK, "Disable 2.5G\n"); 7424 tmp1 &= 0xfffe; 7425 } 7426 7427 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, tmp1); 7428 /* Add support for CL37 (passive mode) II */ 7429 7430 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &tmp1); 7431 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, 7432 (tmp1 | ((phy->req_duplex == DUPLEX_FULL) ? 7433 0x20 : 0x40))); 7434 7435 /* Add support for CL37 (passive mode) III */ 7436 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000); 7437 7438 /* The SNR will improve about 2db by changing BW and FEE main 7439 * tap. Rest commands are executed after link is up 7440 * Change FFE main cursor to 5 in EDC register 7441 */ 7442 if (bnx2x_8073_is_snr_needed(bp, phy)) 7443 bnx2x_cl45_write(bp, phy, 7444 MDIO_PMA_DEVAD, MDIO_PMA_REG_EDC_FFE_MAIN, 7445 0xFB0C); 7446 7447 /* Enable FEC (Forware Error Correction) Request in the AN */ 7448 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, &tmp1); 7449 tmp1 |= (1<<15); 7450 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, tmp1); 7451 7452 bnx2x_ext_phy_set_pause(params, phy, vars); 7453 7454 /* Restart autoneg */ 7455 msleep(500); 7456 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200); 7457 DP(NETIF_MSG_LINK, "807x Autoneg Restart: Advertise 1G=%x, 10G=%x\n", 7458 ((val & (1<<5)) > 0), ((val & (1<<7)) > 0)); 7459 return 0; 7460 } 7461 7462 static u8 bnx2x_8073_read_status(struct bnx2x_phy *phy, 7463 struct link_params *params, 7464 struct link_vars *vars) 7465 { 7466 struct bnx2x *bp = params->bp; 7467 u8 link_up = 0; 7468 u16 val1, val2; 7469 u16 link_status = 0; 7470 u16 an1000_status = 0; 7471 7472 bnx2x_cl45_read(bp, phy, 7473 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1); 7474 7475 DP(NETIF_MSG_LINK, "8703 LASI status 0x%x\n", val1); 7476 7477 /* Clear the interrupt LASI status register */ 7478 bnx2x_cl45_read(bp, phy, 7479 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2); 7480 bnx2x_cl45_read(bp, phy, 7481 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val1); 7482 DP(NETIF_MSG_LINK, "807x PCS status 0x%x->0x%x\n", val2, val1); 7483 /* Clear MSG-OUT */ 7484 bnx2x_cl45_read(bp, phy, 7485 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1); 7486 7487 /* Check the LASI */ 7488 bnx2x_cl45_read(bp, phy, 7489 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2); 7490 7491 DP(NETIF_MSG_LINK, "KR 0x9003 0x%x\n", val2); 7492 7493 /* Check the link status */ 7494 bnx2x_cl45_read(bp, phy, 7495 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2); 7496 DP(NETIF_MSG_LINK, "KR PCS status 0x%x\n", val2); 7497 7498 bnx2x_cl45_read(bp, phy, 7499 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2); 7500 bnx2x_cl45_read(bp, phy, 7501 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1); 7502 link_up = ((val1 & 4) == 4); 7503 DP(NETIF_MSG_LINK, "PMA_REG_STATUS=0x%x\n", val1); 7504 7505 if (link_up && 7506 ((phy->req_line_speed != SPEED_10000))) { 7507 if (bnx2x_8073_xaui_wa(bp, phy) != 0) 7508 return 0; 7509 } 7510 bnx2x_cl45_read(bp, phy, 7511 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status); 7512 bnx2x_cl45_read(bp, phy, 7513 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status); 7514 7515 /* Check the link status on 1.1.2 */ 7516 bnx2x_cl45_read(bp, phy, 7517 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2); 7518 bnx2x_cl45_read(bp, phy, 7519 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1); 7520 DP(NETIF_MSG_LINK, "KR PMA status 0x%x->0x%x," 7521 "an_link_status=0x%x\n", val2, val1, an1000_status); 7522 7523 link_up = (((val1 & 4) == 4) || (an1000_status & (1<<1))); 7524 if (link_up && bnx2x_8073_is_snr_needed(bp, phy)) { 7525 /* The SNR will improve about 2dbby changing the BW and FEE main 7526 * tap. The 1st write to change FFE main tap is set before 7527 * restart AN. Change PLL Bandwidth in EDC register 7528 */ 7529 bnx2x_cl45_write(bp, phy, 7530 MDIO_PMA_DEVAD, MDIO_PMA_REG_PLL_BANDWIDTH, 7531 0x26BC); 7532 7533 /* Change CDR Bandwidth in EDC register */ 7534 bnx2x_cl45_write(bp, phy, 7535 MDIO_PMA_DEVAD, MDIO_PMA_REG_CDR_BANDWIDTH, 7536 0x0333); 7537 } 7538 bnx2x_cl45_read(bp, phy, 7539 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_SPEED_LINK_STATUS, 7540 &link_status); 7541 7542 /* Bits 0..2 --> speed detected, bits 13..15--> link is down */ 7543 if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) { 7544 link_up = 1; 7545 vars->line_speed = SPEED_10000; 7546 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n", 7547 params->port); 7548 } else if ((link_status & (1<<1)) && (!(link_status & (1<<14)))) { 7549 link_up = 1; 7550 vars->line_speed = SPEED_2500; 7551 DP(NETIF_MSG_LINK, "port %x: External link up in 2.5G\n", 7552 params->port); 7553 } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) { 7554 link_up = 1; 7555 vars->line_speed = SPEED_1000; 7556 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n", 7557 params->port); 7558 } else { 7559 link_up = 0; 7560 DP(NETIF_MSG_LINK, "port %x: External link is down\n", 7561 params->port); 7562 } 7563 7564 if (link_up) { 7565 /* Swap polarity if required */ 7566 if (params->lane_config & 7567 PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) { 7568 /* Configure the 8073 to swap P and N of the KR lines */ 7569 bnx2x_cl45_read(bp, phy, 7570 MDIO_XS_DEVAD, 7571 MDIO_XS_REG_8073_RX_CTRL_PCIE, &val1); 7572 /* Set bit 3 to invert Rx in 1G mode and clear this bit 7573 * when it`s in 10G mode. 7574 */ 7575 if (vars->line_speed == SPEED_1000) { 7576 DP(NETIF_MSG_LINK, "Swapping 1G polarity for" 7577 "the 8073\n"); 7578 val1 |= (1<<3); 7579 } else 7580 val1 &= ~(1<<3); 7581 7582 bnx2x_cl45_write(bp, phy, 7583 MDIO_XS_DEVAD, 7584 MDIO_XS_REG_8073_RX_CTRL_PCIE, 7585 val1); 7586 } 7587 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars); 7588 bnx2x_8073_resolve_fc(phy, params, vars); 7589 vars->duplex = DUPLEX_FULL; 7590 } 7591 7592 if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) { 7593 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, 7594 MDIO_AN_REG_LP_AUTO_NEG2, &val1); 7595 7596 if (val1 & (1<<5)) 7597 vars->link_status |= 7598 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; 7599 if (val1 & (1<<7)) 7600 vars->link_status |= 7601 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; 7602 } 7603 7604 return link_up; 7605 } 7606 7607 static void bnx2x_8073_link_reset(struct bnx2x_phy *phy, 7608 struct link_params *params) 7609 { 7610 struct bnx2x *bp = params->bp; 7611 u8 gpio_port; 7612 if (CHIP_IS_E2(bp)) 7613 gpio_port = BP_PATH(bp); 7614 else 7615 gpio_port = params->port; 7616 DP(NETIF_MSG_LINK, "Setting 8073 port %d into low power mode\n", 7617 gpio_port); 7618 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 7619 MISC_REGISTERS_GPIO_OUTPUT_LOW, 7620 gpio_port); 7621 } 7622 7623 /******************************************************************/ 7624 /* BCM8705 PHY SECTION */ 7625 /******************************************************************/ 7626 static int bnx2x_8705_config_init(struct bnx2x_phy *phy, 7627 struct link_params *params, 7628 struct link_vars *vars) 7629 { 7630 struct bnx2x *bp = params->bp; 7631 DP(NETIF_MSG_LINK, "init 8705\n"); 7632 /* Restore normal power mode*/ 7633 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 7634 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); 7635 /* HW reset */ 7636 bnx2x_ext_phy_hw_reset(bp, params->port); 7637 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040); 7638 bnx2x_wait_reset_complete(bp, phy, params); 7639 7640 bnx2x_cl45_write(bp, phy, 7641 MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL, 0x8288); 7642 bnx2x_cl45_write(bp, phy, 7643 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 0x7fbf); 7644 bnx2x_cl45_write(bp, phy, 7645 MDIO_PMA_DEVAD, MDIO_PMA_REG_CMU_PLL_BYPASS, 0x0100); 7646 bnx2x_cl45_write(bp, phy, 7647 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_CNTL, 0x1); 7648 /* BCM8705 doesn't have microcode, hence the 0 */ 7649 bnx2x_save_spirom_version(bp, params->port, params->shmem_base, 0); 7650 return 0; 7651 } 7652 7653 static u8 bnx2x_8705_read_status(struct bnx2x_phy *phy, 7654 struct link_params *params, 7655 struct link_vars *vars) 7656 { 7657 u8 link_up = 0; 7658 u16 val1, rx_sd; 7659 struct bnx2x *bp = params->bp; 7660 DP(NETIF_MSG_LINK, "read status 8705\n"); 7661 bnx2x_cl45_read(bp, phy, 7662 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1); 7663 DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1); 7664 7665 bnx2x_cl45_read(bp, phy, 7666 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1); 7667 DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1); 7668 7669 bnx2x_cl45_read(bp, phy, 7670 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd); 7671 7672 bnx2x_cl45_read(bp, phy, 7673 MDIO_PMA_DEVAD, 0xc809, &val1); 7674 bnx2x_cl45_read(bp, phy, 7675 MDIO_PMA_DEVAD, 0xc809, &val1); 7676 7677 DP(NETIF_MSG_LINK, "8705 1.c809 val=0x%x\n", val1); 7678 link_up = ((rx_sd & 0x1) && (val1 & (1<<9)) && ((val1 & (1<<8)) == 0)); 7679 if (link_up) { 7680 vars->line_speed = SPEED_10000; 7681 bnx2x_ext_phy_resolve_fc(phy, params, vars); 7682 } 7683 return link_up; 7684 } 7685 7686 /******************************************************************/ 7687 /* SFP+ module Section */ 7688 /******************************************************************/ 7689 static void bnx2x_set_disable_pmd_transmit(struct link_params *params, 7690 struct bnx2x_phy *phy, 7691 u8 pmd_dis) 7692 { 7693 struct bnx2x *bp = params->bp; 7694 /* Disable transmitter only for bootcodes which can enable it afterwards 7695 * (for D3 link) 7696 */ 7697 if (pmd_dis) { 7698 if (params->feature_config_flags & 7699 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED) 7700 DP(NETIF_MSG_LINK, "Disabling PMD transmitter\n"); 7701 else { 7702 DP(NETIF_MSG_LINK, "NOT disabling PMD transmitter\n"); 7703 return; 7704 } 7705 } else 7706 DP(NETIF_MSG_LINK, "Enabling PMD transmitter\n"); 7707 bnx2x_cl45_write(bp, phy, 7708 MDIO_PMA_DEVAD, 7709 MDIO_PMA_REG_TX_DISABLE, pmd_dis); 7710 } 7711 7712 static u8 bnx2x_get_gpio_port(struct link_params *params) 7713 { 7714 u8 gpio_port; 7715 u32 swap_val, swap_override; 7716 struct bnx2x *bp = params->bp; 7717 if (CHIP_IS_E2(bp)) 7718 gpio_port = BP_PATH(bp); 7719 else 7720 gpio_port = params->port; 7721 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); 7722 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); 7723 return gpio_port ^ (swap_val && swap_override); 7724 } 7725 7726 static void bnx2x_sfp_e1e2_set_transmitter(struct link_params *params, 7727 struct bnx2x_phy *phy, 7728 u8 tx_en) 7729 { 7730 u16 val; 7731 u8 port = params->port; 7732 struct bnx2x *bp = params->bp; 7733 u32 tx_en_mode; 7734 7735 /* Disable/Enable transmitter ( TX laser of the SFP+ module.)*/ 7736 tx_en_mode = REG_RD(bp, params->shmem_base + 7737 offsetof(struct shmem_region, 7738 dev_info.port_hw_config[port].sfp_ctrl)) & 7739 PORT_HW_CFG_TX_LASER_MASK; 7740 DP(NETIF_MSG_LINK, "Setting transmitter tx_en=%x for port %x " 7741 "mode = %x\n", tx_en, port, tx_en_mode); 7742 switch (tx_en_mode) { 7743 case PORT_HW_CFG_TX_LASER_MDIO: 7744 7745 bnx2x_cl45_read(bp, phy, 7746 MDIO_PMA_DEVAD, 7747 MDIO_PMA_REG_PHY_IDENTIFIER, 7748 &val); 7749 7750 if (tx_en) 7751 val &= ~(1<<15); 7752 else 7753 val |= (1<<15); 7754 7755 bnx2x_cl45_write(bp, phy, 7756 MDIO_PMA_DEVAD, 7757 MDIO_PMA_REG_PHY_IDENTIFIER, 7758 val); 7759 break; 7760 case PORT_HW_CFG_TX_LASER_GPIO0: 7761 case PORT_HW_CFG_TX_LASER_GPIO1: 7762 case PORT_HW_CFG_TX_LASER_GPIO2: 7763 case PORT_HW_CFG_TX_LASER_GPIO3: 7764 { 7765 u16 gpio_pin; 7766 u8 gpio_port, gpio_mode; 7767 if (tx_en) 7768 gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_HIGH; 7769 else 7770 gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_LOW; 7771 7772 gpio_pin = tx_en_mode - PORT_HW_CFG_TX_LASER_GPIO0; 7773 gpio_port = bnx2x_get_gpio_port(params); 7774 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port); 7775 break; 7776 } 7777 default: 7778 DP(NETIF_MSG_LINK, "Invalid TX_LASER_MDIO 0x%x\n", tx_en_mode); 7779 break; 7780 } 7781 } 7782 7783 static void bnx2x_sfp_set_transmitter(struct link_params *params, 7784 struct bnx2x_phy *phy, 7785 u8 tx_en) 7786 { 7787 struct bnx2x *bp = params->bp; 7788 DP(NETIF_MSG_LINK, "Setting SFP+ transmitter to %d\n", tx_en); 7789 if (CHIP_IS_E3(bp)) 7790 bnx2x_sfp_e3_set_transmitter(params, phy, tx_en); 7791 else 7792 bnx2x_sfp_e1e2_set_transmitter(params, phy, tx_en); 7793 } 7794 7795 static int bnx2x_8726_read_sfp_module_eeprom(struct bnx2x_phy *phy, 7796 struct link_params *params, 7797 u8 dev_addr, u16 addr, u8 byte_cnt, 7798 u8 *o_buf, u8 is_init) 7799 { 7800 struct bnx2x *bp = params->bp; 7801 u16 val = 0; 7802 u16 i; 7803 if (byte_cnt > SFP_EEPROM_PAGE_SIZE) { 7804 DP(NETIF_MSG_LINK, 7805 "Reading from eeprom is limited to 0xf\n"); 7806 return -EINVAL; 7807 } 7808 /* Set the read command byte count */ 7809 bnx2x_cl45_write(bp, phy, 7810 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT, 7811 (byte_cnt | (dev_addr << 8))); 7812 7813 /* Set the read command address */ 7814 bnx2x_cl45_write(bp, phy, 7815 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR, 7816 addr); 7817 7818 /* Activate read command */ 7819 bnx2x_cl45_write(bp, phy, 7820 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, 7821 0x2c0f); 7822 7823 /* Wait up to 500us for command complete status */ 7824 for (i = 0; i < 100; i++) { 7825 bnx2x_cl45_read(bp, phy, 7826 MDIO_PMA_DEVAD, 7827 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); 7828 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == 7829 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) 7830 break; 7831 udelay(5); 7832 } 7833 7834 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) != 7835 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) { 7836 DP(NETIF_MSG_LINK, 7837 "Got bad status 0x%x when reading from SFP+ EEPROM\n", 7838 (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK)); 7839 return -EINVAL; 7840 } 7841 7842 /* Read the buffer */ 7843 for (i = 0; i < byte_cnt; i++) { 7844 bnx2x_cl45_read(bp, phy, 7845 MDIO_PMA_DEVAD, 7846 MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i, &val); 7847 o_buf[i] = (u8)(val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK); 7848 } 7849 7850 for (i = 0; i < 100; i++) { 7851 bnx2x_cl45_read(bp, phy, 7852 MDIO_PMA_DEVAD, 7853 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); 7854 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == 7855 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE) 7856 return 0; 7857 usleep_range(1000, 2000); 7858 } 7859 return -EINVAL; 7860 } 7861 7862 static void bnx2x_warpcore_power_module(struct link_params *params, 7863 u8 power) 7864 { 7865 u32 pin_cfg; 7866 struct bnx2x *bp = params->bp; 7867 7868 pin_cfg = (REG_RD(bp, params->shmem_base + 7869 offsetof(struct shmem_region, 7870 dev_info.port_hw_config[params->port].e3_sfp_ctrl)) & 7871 PORT_HW_CFG_E3_PWR_DIS_MASK) >> 7872 PORT_HW_CFG_E3_PWR_DIS_SHIFT; 7873 7874 if (pin_cfg == PIN_CFG_NA) 7875 return; 7876 DP(NETIF_MSG_LINK, "Setting SFP+ module power to %d using pin cfg %d\n", 7877 power, pin_cfg); 7878 /* Low ==> corresponding SFP+ module is powered 7879 * high ==> the SFP+ module is powered down 7880 */ 7881 bnx2x_set_cfg_pin(bp, pin_cfg, power ^ 1); 7882 } 7883 static int bnx2x_warpcore_read_sfp_module_eeprom(struct bnx2x_phy *phy, 7884 struct link_params *params, 7885 u8 dev_addr, 7886 u16 addr, u8 byte_cnt, 7887 u8 *o_buf, u8 is_init) 7888 { 7889 int rc = 0; 7890 u8 i, j = 0, cnt = 0; 7891 u32 data_array[4]; 7892 u16 addr32; 7893 struct bnx2x *bp = params->bp; 7894 7895 if (byte_cnt > SFP_EEPROM_PAGE_SIZE) { 7896 DP(NETIF_MSG_LINK, 7897 "Reading from eeprom is limited to 16 bytes\n"); 7898 return -EINVAL; 7899 } 7900 7901 /* 4 byte aligned address */ 7902 addr32 = addr & (~0x3); 7903 do { 7904 if ((!is_init) && (cnt == I2C_WA_PWR_ITER)) { 7905 bnx2x_warpcore_power_module(params, 0); 7906 /* Note that 100us are not enough here */ 7907 usleep_range(1000, 2000); 7908 bnx2x_warpcore_power_module(params, 1); 7909 } 7910 rc = bnx2x_bsc_read(params, bp, dev_addr, addr32, 0, byte_cnt, 7911 data_array); 7912 } while ((rc != 0) && (++cnt < I2C_WA_RETRY_CNT)); 7913 7914 if (rc == 0) { 7915 for (i = (addr - addr32); i < byte_cnt + (addr - addr32); i++) { 7916 o_buf[j] = *((u8 *)data_array + i); 7917 j++; 7918 } 7919 } 7920 7921 return rc; 7922 } 7923 7924 static int bnx2x_8727_read_sfp_module_eeprom(struct bnx2x_phy *phy, 7925 struct link_params *params, 7926 u8 dev_addr, u16 addr, u8 byte_cnt, 7927 u8 *o_buf, u8 is_init) 7928 { 7929 struct bnx2x *bp = params->bp; 7930 u16 val, i; 7931 7932 if (byte_cnt > SFP_EEPROM_PAGE_SIZE) { 7933 DP(NETIF_MSG_LINK, 7934 "Reading from eeprom is limited to 0xf\n"); 7935 return -EINVAL; 7936 } 7937 7938 /* Set 2-wire transfer rate of SFP+ module EEPROM 7939 * to 100Khz since some DACs(direct attached cables) do 7940 * not work at 400Khz. 7941 */ 7942 bnx2x_cl45_write(bp, phy, 7943 MDIO_PMA_DEVAD, 7944 MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR, 7945 ((dev_addr << 8) | 1)); 7946 7947 /* Need to read from 1.8000 to clear it */ 7948 bnx2x_cl45_read(bp, phy, 7949 MDIO_PMA_DEVAD, 7950 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, 7951 &val); 7952 7953 /* Set the read command byte count */ 7954 bnx2x_cl45_write(bp, phy, 7955 MDIO_PMA_DEVAD, 7956 MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT, 7957 ((byte_cnt < 2) ? 2 : byte_cnt)); 7958 7959 /* Set the read command address */ 7960 bnx2x_cl45_write(bp, phy, 7961 MDIO_PMA_DEVAD, 7962 MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR, 7963 addr); 7964 /* Set the destination address */ 7965 bnx2x_cl45_write(bp, phy, 7966 MDIO_PMA_DEVAD, 7967 0x8004, 7968 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF); 7969 7970 /* Activate read command */ 7971 bnx2x_cl45_write(bp, phy, 7972 MDIO_PMA_DEVAD, 7973 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, 7974 0x8002); 7975 /* Wait appropriate time for two-wire command to finish before 7976 * polling the status register 7977 */ 7978 usleep_range(1000, 2000); 7979 7980 /* Wait up to 500us for command complete status */ 7981 for (i = 0; i < 100; i++) { 7982 bnx2x_cl45_read(bp, phy, 7983 MDIO_PMA_DEVAD, 7984 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); 7985 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == 7986 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) 7987 break; 7988 udelay(5); 7989 } 7990 7991 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) != 7992 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) { 7993 DP(NETIF_MSG_LINK, 7994 "Got bad status 0x%x when reading from SFP+ EEPROM\n", 7995 (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK)); 7996 return -EFAULT; 7997 } 7998 7999 /* Read the buffer */ 8000 for (i = 0; i < byte_cnt; i++) { 8001 bnx2x_cl45_read(bp, phy, 8002 MDIO_PMA_DEVAD, 8003 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF + i, &val); 8004 o_buf[i] = (u8)(val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK); 8005 } 8006 8007 for (i = 0; i < 100; i++) { 8008 bnx2x_cl45_read(bp, phy, 8009 MDIO_PMA_DEVAD, 8010 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); 8011 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == 8012 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE) 8013 return 0; 8014 usleep_range(1000, 2000); 8015 } 8016 8017 return -EINVAL; 8018 } 8019 int bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy, 8020 struct link_params *params, u8 dev_addr, 8021 u16 addr, u16 byte_cnt, u8 *o_buf) 8022 { 8023 int rc = 0; 8024 struct bnx2x *bp = params->bp; 8025 u8 xfer_size; 8026 u8 *user_data = o_buf; 8027 read_sfp_module_eeprom_func_p read_func; 8028 8029 if ((dev_addr != 0xa0) && (dev_addr != 0xa2)) { 8030 DP(NETIF_MSG_LINK, "invalid dev_addr 0x%x\n", dev_addr); 8031 return -EINVAL; 8032 } 8033 8034 switch (phy->type) { 8035 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: 8036 read_func = bnx2x_8726_read_sfp_module_eeprom; 8037 break; 8038 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: 8039 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722: 8040 read_func = bnx2x_8727_read_sfp_module_eeprom; 8041 break; 8042 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT: 8043 read_func = bnx2x_warpcore_read_sfp_module_eeprom; 8044 break; 8045 default: 8046 return -EOPNOTSUPP; 8047 } 8048 8049 while (!rc && (byte_cnt > 0)) { 8050 xfer_size = (byte_cnt > SFP_EEPROM_PAGE_SIZE) ? 8051 SFP_EEPROM_PAGE_SIZE : byte_cnt; 8052 rc = read_func(phy, params, dev_addr, addr, xfer_size, 8053 user_data, 0); 8054 byte_cnt -= xfer_size; 8055 user_data += xfer_size; 8056 addr += xfer_size; 8057 } 8058 return rc; 8059 } 8060 8061 static int bnx2x_get_edc_mode(struct bnx2x_phy *phy, 8062 struct link_params *params, 8063 u16 *edc_mode) 8064 { 8065 struct bnx2x *bp = params->bp; 8066 u32 sync_offset = 0, phy_idx, media_types; 8067 u8 val[SFP_EEPROM_FC_TX_TECH_ADDR + 1], check_limiting_mode = 0; 8068 *edc_mode = EDC_MODE_LIMITING; 8069 phy->media_type = ETH_PHY_UNSPECIFIED; 8070 /* First check for copper cable */ 8071 if (bnx2x_read_sfp_module_eeprom(phy, 8072 params, 8073 I2C_DEV_ADDR_A0, 8074 0, 8075 SFP_EEPROM_FC_TX_TECH_ADDR + 1, 8076 (u8 *)val) != 0) { 8077 DP(NETIF_MSG_LINK, "Failed to read from SFP+ module EEPROM\n"); 8078 return -EINVAL; 8079 } 8080 params->link_attr_sync &= ~LINK_SFP_EEPROM_COMP_CODE_MASK; 8081 params->link_attr_sync |= val[SFP_EEPROM_10G_COMP_CODE_ADDR] << 8082 LINK_SFP_EEPROM_COMP_CODE_SHIFT; 8083 bnx2x_update_link_attr(params, params->link_attr_sync); 8084 switch (val[SFP_EEPROM_CON_TYPE_ADDR]) { 8085 case SFP_EEPROM_CON_TYPE_VAL_COPPER: 8086 { 8087 u8 copper_module_type; 8088 phy->media_type = ETH_PHY_DA_TWINAX; 8089 /* Check if its active cable (includes SFP+ module) 8090 * of passive cable 8091 */ 8092 copper_module_type = val[SFP_EEPROM_FC_TX_TECH_ADDR]; 8093 8094 if (copper_module_type & 8095 SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) { 8096 DP(NETIF_MSG_LINK, "Active Copper cable detected\n"); 8097 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) 8098 *edc_mode = EDC_MODE_ACTIVE_DAC; 8099 else 8100 check_limiting_mode = 1; 8101 } else { 8102 *edc_mode = EDC_MODE_PASSIVE_DAC; 8103 /* Even in case PASSIVE_DAC indication is not set, 8104 * treat it as a passive DAC cable, since some cables 8105 * don't have this indication. 8106 */ 8107 if (copper_module_type & 8108 SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE) { 8109 DP(NETIF_MSG_LINK, 8110 "Passive Copper cable detected\n"); 8111 } else { 8112 DP(NETIF_MSG_LINK, 8113 "Unknown copper-cable-type\n"); 8114 } 8115 } 8116 break; 8117 } 8118 case SFP_EEPROM_CON_TYPE_VAL_UNKNOWN: 8119 case SFP_EEPROM_CON_TYPE_VAL_LC: 8120 case SFP_EEPROM_CON_TYPE_VAL_RJ45: 8121 check_limiting_mode = 1; 8122 if (((val[SFP_EEPROM_10G_COMP_CODE_ADDR] & 8123 (SFP_EEPROM_10G_COMP_CODE_SR_MASK | 8124 SFP_EEPROM_10G_COMP_CODE_LR_MASK | 8125 SFP_EEPROM_10G_COMP_CODE_LRM_MASK)) == 0) && 8126 (val[SFP_EEPROM_1G_COMP_CODE_ADDR] != 0)) { 8127 DP(NETIF_MSG_LINK, "1G SFP module detected\n"); 8128 phy->media_type = ETH_PHY_SFP_1G_FIBER; 8129 if (phy->req_line_speed != SPEED_1000) { 8130 u8 gport = params->port; 8131 phy->req_line_speed = SPEED_1000; 8132 if (!CHIP_IS_E1x(bp)) { 8133 gport = BP_PATH(bp) + 8134 (params->port << 1); 8135 } 8136 netdev_err(bp->dev, 8137 "Warning: Link speed was forced to 1000Mbps. Current SFP module in port %d is not compliant with 10G Ethernet\n", 8138 gport); 8139 } 8140 if (val[SFP_EEPROM_1G_COMP_CODE_ADDR] & 8141 SFP_EEPROM_1G_COMP_CODE_BASE_T) { 8142 bnx2x_sfp_set_transmitter(params, phy, 0); 8143 msleep(40); 8144 bnx2x_sfp_set_transmitter(params, phy, 1); 8145 } 8146 } else { 8147 int idx, cfg_idx = 0; 8148 DP(NETIF_MSG_LINK, "10G Optic module detected\n"); 8149 for (idx = INT_PHY; idx < MAX_PHYS; idx++) { 8150 if (params->phy[idx].type == phy->type) { 8151 cfg_idx = LINK_CONFIG_IDX(idx); 8152 break; 8153 } 8154 } 8155 phy->media_type = ETH_PHY_SFPP_10G_FIBER; 8156 phy->req_line_speed = params->req_line_speed[cfg_idx]; 8157 } 8158 break; 8159 default: 8160 DP(NETIF_MSG_LINK, "Unable to determine module type 0x%x !!!\n", 8161 val[SFP_EEPROM_CON_TYPE_ADDR]); 8162 return -EINVAL; 8163 } 8164 sync_offset = params->shmem_base + 8165 offsetof(struct shmem_region, 8166 dev_info.port_hw_config[params->port].media_type); 8167 media_types = REG_RD(bp, sync_offset); 8168 /* Update media type for non-PMF sync */ 8169 for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) { 8170 if (&(params->phy[phy_idx]) == phy) { 8171 media_types &= ~(PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK << 8172 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx)); 8173 media_types |= ((phy->media_type & 8174 PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) << 8175 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx)); 8176 break; 8177 } 8178 } 8179 REG_WR(bp, sync_offset, media_types); 8180 if (check_limiting_mode) { 8181 u8 options[SFP_EEPROM_OPTIONS_SIZE]; 8182 if (bnx2x_read_sfp_module_eeprom(phy, 8183 params, 8184 I2C_DEV_ADDR_A0, 8185 SFP_EEPROM_OPTIONS_ADDR, 8186 SFP_EEPROM_OPTIONS_SIZE, 8187 options) != 0) { 8188 DP(NETIF_MSG_LINK, 8189 "Failed to read Option field from module EEPROM\n"); 8190 return -EINVAL; 8191 } 8192 if ((options[0] & SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK)) 8193 *edc_mode = EDC_MODE_LINEAR; 8194 else 8195 *edc_mode = EDC_MODE_LIMITING; 8196 } 8197 DP(NETIF_MSG_LINK, "EDC mode is set to 0x%x\n", *edc_mode); 8198 return 0; 8199 } 8200 /* This function read the relevant field from the module (SFP+), and verify it 8201 * is compliant with this board 8202 */ 8203 static int bnx2x_verify_sfp_module(struct bnx2x_phy *phy, 8204 struct link_params *params) 8205 { 8206 struct bnx2x *bp = params->bp; 8207 u32 val, cmd; 8208 u32 fw_resp, fw_cmd_param; 8209 char vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE+1]; 8210 char vendor_pn[SFP_EEPROM_PART_NO_SIZE+1]; 8211 phy->flags &= ~FLAGS_SFP_NOT_APPROVED; 8212 val = REG_RD(bp, params->shmem_base + 8213 offsetof(struct shmem_region, dev_info. 8214 port_feature_config[params->port].config)); 8215 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == 8216 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT) { 8217 DP(NETIF_MSG_LINK, "NOT enforcing module verification\n"); 8218 return 0; 8219 } 8220 8221 if (params->feature_config_flags & 8222 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY) { 8223 /* Use specific phy request */ 8224 cmd = DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL; 8225 } else if (params->feature_config_flags & 8226 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY) { 8227 /* Use first phy request only in case of non-dual media*/ 8228 if (DUAL_MEDIA(params)) { 8229 DP(NETIF_MSG_LINK, 8230 "FW does not support OPT MDL verification\n"); 8231 return -EINVAL; 8232 } 8233 cmd = DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL; 8234 } else { 8235 /* No support in OPT MDL detection */ 8236 DP(NETIF_MSG_LINK, 8237 "FW does not support OPT MDL verification\n"); 8238 return -EINVAL; 8239 } 8240 8241 fw_cmd_param = FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl); 8242 fw_resp = bnx2x_fw_command(bp, cmd, fw_cmd_param); 8243 if (fw_resp == FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS) { 8244 DP(NETIF_MSG_LINK, "Approved module\n"); 8245 return 0; 8246 } 8247 8248 /* Format the warning message */ 8249 if (bnx2x_read_sfp_module_eeprom(phy, 8250 params, 8251 I2C_DEV_ADDR_A0, 8252 SFP_EEPROM_VENDOR_NAME_ADDR, 8253 SFP_EEPROM_VENDOR_NAME_SIZE, 8254 (u8 *)vendor_name)) 8255 vendor_name[0] = '\0'; 8256 else 8257 vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE] = '\0'; 8258 if (bnx2x_read_sfp_module_eeprom(phy, 8259 params, 8260 I2C_DEV_ADDR_A0, 8261 SFP_EEPROM_PART_NO_ADDR, 8262 SFP_EEPROM_PART_NO_SIZE, 8263 (u8 *)vendor_pn)) 8264 vendor_pn[0] = '\0'; 8265 else 8266 vendor_pn[SFP_EEPROM_PART_NO_SIZE] = '\0'; 8267 8268 netdev_err(bp->dev, "Warning: Unqualified SFP+ module detected," 8269 " Port %d from %s part number %s\n", 8270 params->port, vendor_name, vendor_pn); 8271 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) != 8272 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG) 8273 phy->flags |= FLAGS_SFP_NOT_APPROVED; 8274 return -EINVAL; 8275 } 8276 8277 static int bnx2x_wait_for_sfp_module_initialized(struct bnx2x_phy *phy, 8278 struct link_params *params) 8279 8280 { 8281 u8 val; 8282 int rc; 8283 struct bnx2x *bp = params->bp; 8284 u16 timeout; 8285 /* Initialization time after hot-plug may take up to 300ms for 8286 * some phys type ( e.g. JDSU ) 8287 */ 8288 8289 for (timeout = 0; timeout < 60; timeout++) { 8290 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) 8291 rc = bnx2x_warpcore_read_sfp_module_eeprom( 8292 phy, params, I2C_DEV_ADDR_A0, 1, 1, &val, 8293 1); 8294 else 8295 rc = bnx2x_read_sfp_module_eeprom(phy, params, 8296 I2C_DEV_ADDR_A0, 8297 1, 1, &val); 8298 if (rc == 0) { 8299 DP(NETIF_MSG_LINK, 8300 "SFP+ module initialization took %d ms\n", 8301 timeout * 5); 8302 return 0; 8303 } 8304 usleep_range(5000, 10000); 8305 } 8306 rc = bnx2x_read_sfp_module_eeprom(phy, params, I2C_DEV_ADDR_A0, 8307 1, 1, &val); 8308 return rc; 8309 } 8310 8311 static void bnx2x_8727_power_module(struct bnx2x *bp, 8312 struct bnx2x_phy *phy, 8313 u8 is_power_up) { 8314 /* Make sure GPIOs are not using for LED mode */ 8315 u16 val; 8316 /* In the GPIO register, bit 4 is use to determine if the GPIOs are 8317 * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for 8318 * output 8319 * Bits 0-1 determine the GPIOs value for OUTPUT in case bit 4 val is 0 8320 * Bits 8-9 determine the GPIOs value for INPUT in case bit 4 val is 1 8321 * where the 1st bit is the over-current(only input), and 2nd bit is 8322 * for power( only output ) 8323 * 8324 * In case of NOC feature is disabled and power is up, set GPIO control 8325 * as input to enable listening of over-current indication 8326 */ 8327 if (phy->flags & FLAGS_NOC) 8328 return; 8329 if (is_power_up) 8330 val = (1<<4); 8331 else 8332 /* Set GPIO control to OUTPUT, and set the power bit 8333 * to according to the is_power_up 8334 */ 8335 val = (1<<1); 8336 8337 bnx2x_cl45_write(bp, phy, 8338 MDIO_PMA_DEVAD, 8339 MDIO_PMA_REG_8727_GPIO_CTRL, 8340 val); 8341 } 8342 8343 static int bnx2x_8726_set_limiting_mode(struct bnx2x *bp, 8344 struct bnx2x_phy *phy, 8345 u16 edc_mode) 8346 { 8347 u16 cur_limiting_mode; 8348 8349 bnx2x_cl45_read(bp, phy, 8350 MDIO_PMA_DEVAD, 8351 MDIO_PMA_REG_ROM_VER2, 8352 &cur_limiting_mode); 8353 DP(NETIF_MSG_LINK, "Current Limiting mode is 0x%x\n", 8354 cur_limiting_mode); 8355 8356 if (edc_mode == EDC_MODE_LIMITING) { 8357 DP(NETIF_MSG_LINK, "Setting LIMITING MODE\n"); 8358 bnx2x_cl45_write(bp, phy, 8359 MDIO_PMA_DEVAD, 8360 MDIO_PMA_REG_ROM_VER2, 8361 EDC_MODE_LIMITING); 8362 } else { /* LRM mode ( default )*/ 8363 8364 DP(NETIF_MSG_LINK, "Setting LRM MODE\n"); 8365 8366 /* Changing to LRM mode takes quite few seconds. So do it only 8367 * if current mode is limiting (default is LRM) 8368 */ 8369 if (cur_limiting_mode != EDC_MODE_LIMITING) 8370 return 0; 8371 8372 bnx2x_cl45_write(bp, phy, 8373 MDIO_PMA_DEVAD, 8374 MDIO_PMA_REG_LRM_MODE, 8375 0); 8376 bnx2x_cl45_write(bp, phy, 8377 MDIO_PMA_DEVAD, 8378 MDIO_PMA_REG_ROM_VER2, 8379 0x128); 8380 bnx2x_cl45_write(bp, phy, 8381 MDIO_PMA_DEVAD, 8382 MDIO_PMA_REG_MISC_CTRL0, 8383 0x4008); 8384 bnx2x_cl45_write(bp, phy, 8385 MDIO_PMA_DEVAD, 8386 MDIO_PMA_REG_LRM_MODE, 8387 0xaaaa); 8388 } 8389 return 0; 8390 } 8391 8392 static int bnx2x_8727_set_limiting_mode(struct bnx2x *bp, 8393 struct bnx2x_phy *phy, 8394 u16 edc_mode) 8395 { 8396 u16 phy_identifier; 8397 u16 rom_ver2_val; 8398 bnx2x_cl45_read(bp, phy, 8399 MDIO_PMA_DEVAD, 8400 MDIO_PMA_REG_PHY_IDENTIFIER, 8401 &phy_identifier); 8402 8403 bnx2x_cl45_write(bp, phy, 8404 MDIO_PMA_DEVAD, 8405 MDIO_PMA_REG_PHY_IDENTIFIER, 8406 (phy_identifier & ~(1<<9))); 8407 8408 bnx2x_cl45_read(bp, phy, 8409 MDIO_PMA_DEVAD, 8410 MDIO_PMA_REG_ROM_VER2, 8411 &rom_ver2_val); 8412 /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */ 8413 bnx2x_cl45_write(bp, phy, 8414 MDIO_PMA_DEVAD, 8415 MDIO_PMA_REG_ROM_VER2, 8416 (rom_ver2_val & 0xff00) | (edc_mode & 0x00ff)); 8417 8418 bnx2x_cl45_write(bp, phy, 8419 MDIO_PMA_DEVAD, 8420 MDIO_PMA_REG_PHY_IDENTIFIER, 8421 (phy_identifier | (1<<9))); 8422 8423 return 0; 8424 } 8425 8426 static void bnx2x_8727_specific_func(struct bnx2x_phy *phy, 8427 struct link_params *params, 8428 u32 action) 8429 { 8430 struct bnx2x *bp = params->bp; 8431 u16 val; 8432 switch (action) { 8433 case DISABLE_TX: 8434 bnx2x_sfp_set_transmitter(params, phy, 0); 8435 break; 8436 case ENABLE_TX: 8437 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED)) 8438 bnx2x_sfp_set_transmitter(params, phy, 1); 8439 break; 8440 case PHY_INIT: 8441 bnx2x_cl45_write(bp, phy, 8442 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, 8443 (1<<2) | (1<<5)); 8444 bnx2x_cl45_write(bp, phy, 8445 MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL, 8446 0); 8447 bnx2x_cl45_write(bp, phy, 8448 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0006); 8449 /* Make MOD_ABS give interrupt on change */ 8450 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 8451 MDIO_PMA_REG_8727_PCS_OPT_CTRL, 8452 &val); 8453 val |= (1<<12); 8454 if (phy->flags & FLAGS_NOC) 8455 val |= (3<<5); 8456 /* Set 8727 GPIOs to input to allow reading from the 8727 GPIO0 8457 * status which reflect SFP+ module over-current 8458 */ 8459 if (!(phy->flags & FLAGS_NOC)) 8460 val &= 0xff8f; /* Reset bits 4-6 */ 8461 bnx2x_cl45_write(bp, phy, 8462 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL, 8463 val); 8464 break; 8465 default: 8466 DP(NETIF_MSG_LINK, "Function 0x%x not supported by 8727\n", 8467 action); 8468 return; 8469 } 8470 } 8471 8472 static void bnx2x_set_e1e2_module_fault_led(struct link_params *params, 8473 u8 gpio_mode) 8474 { 8475 struct bnx2x *bp = params->bp; 8476 8477 u32 fault_led_gpio = REG_RD(bp, params->shmem_base + 8478 offsetof(struct shmem_region, 8479 dev_info.port_hw_config[params->port].sfp_ctrl)) & 8480 PORT_HW_CFG_FAULT_MODULE_LED_MASK; 8481 switch (fault_led_gpio) { 8482 case PORT_HW_CFG_FAULT_MODULE_LED_DISABLED: 8483 return; 8484 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO0: 8485 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO1: 8486 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO2: 8487 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO3: 8488 { 8489 u8 gpio_port = bnx2x_get_gpio_port(params); 8490 u16 gpio_pin = fault_led_gpio - 8491 PORT_HW_CFG_FAULT_MODULE_LED_GPIO0; 8492 DP(NETIF_MSG_LINK, "Set fault module-detected led " 8493 "pin %x port %x mode %x\n", 8494 gpio_pin, gpio_port, gpio_mode); 8495 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port); 8496 } 8497 break; 8498 default: 8499 DP(NETIF_MSG_LINK, "Error: Invalid fault led mode 0x%x\n", 8500 fault_led_gpio); 8501 } 8502 } 8503 8504 static void bnx2x_set_e3_module_fault_led(struct link_params *params, 8505 u8 gpio_mode) 8506 { 8507 u32 pin_cfg; 8508 u8 port = params->port; 8509 struct bnx2x *bp = params->bp; 8510 pin_cfg = (REG_RD(bp, params->shmem_base + 8511 offsetof(struct shmem_region, 8512 dev_info.port_hw_config[port].e3_sfp_ctrl)) & 8513 PORT_HW_CFG_E3_FAULT_MDL_LED_MASK) >> 8514 PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT; 8515 DP(NETIF_MSG_LINK, "Setting Fault LED to %d using pin cfg %d\n", 8516 gpio_mode, pin_cfg); 8517 bnx2x_set_cfg_pin(bp, pin_cfg, gpio_mode); 8518 } 8519 8520 static void bnx2x_set_sfp_module_fault_led(struct link_params *params, 8521 u8 gpio_mode) 8522 { 8523 struct bnx2x *bp = params->bp; 8524 DP(NETIF_MSG_LINK, "Setting SFP+ module fault LED to %d\n", gpio_mode); 8525 if (CHIP_IS_E3(bp)) { 8526 /* Low ==> if SFP+ module is supported otherwise 8527 * High ==> if SFP+ module is not on the approved vendor list 8528 */ 8529 bnx2x_set_e3_module_fault_led(params, gpio_mode); 8530 } else 8531 bnx2x_set_e1e2_module_fault_led(params, gpio_mode); 8532 } 8533 8534 static void bnx2x_warpcore_hw_reset(struct bnx2x_phy *phy, 8535 struct link_params *params) 8536 { 8537 struct bnx2x *bp = params->bp; 8538 bnx2x_warpcore_power_module(params, 0); 8539 /* Put Warpcore in low power mode */ 8540 REG_WR(bp, MISC_REG_WC0_RESET, 0x0c0e); 8541 8542 /* Put LCPLL in low power mode */ 8543 REG_WR(bp, MISC_REG_LCPLL_E40_PWRDWN, 1); 8544 REG_WR(bp, MISC_REG_LCPLL_E40_RESETB_ANA, 0); 8545 REG_WR(bp, MISC_REG_LCPLL_E40_RESETB_DIG, 0); 8546 } 8547 8548 static void bnx2x_power_sfp_module(struct link_params *params, 8549 struct bnx2x_phy *phy, 8550 u8 power) 8551 { 8552 struct bnx2x *bp = params->bp; 8553 DP(NETIF_MSG_LINK, "Setting SFP+ power to %x\n", power); 8554 8555 switch (phy->type) { 8556 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: 8557 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722: 8558 bnx2x_8727_power_module(params->bp, phy, power); 8559 break; 8560 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT: 8561 bnx2x_warpcore_power_module(params, power); 8562 break; 8563 default: 8564 break; 8565 } 8566 } 8567 static void bnx2x_warpcore_set_limiting_mode(struct link_params *params, 8568 struct bnx2x_phy *phy, 8569 u16 edc_mode) 8570 { 8571 u16 val = 0; 8572 u16 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT; 8573 struct bnx2x *bp = params->bp; 8574 8575 u8 lane = bnx2x_get_warpcore_lane(phy, params); 8576 /* This is a global register which controls all lanes */ 8577 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 8578 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val); 8579 val &= ~(0xf << (lane << 2)); 8580 8581 switch (edc_mode) { 8582 case EDC_MODE_LINEAR: 8583 case EDC_MODE_LIMITING: 8584 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT; 8585 break; 8586 case EDC_MODE_PASSIVE_DAC: 8587 case EDC_MODE_ACTIVE_DAC: 8588 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC; 8589 break; 8590 default: 8591 break; 8592 } 8593 8594 val |= (mode << (lane << 2)); 8595 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 8596 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, val); 8597 /* A must read */ 8598 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 8599 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val); 8600 8601 /* Restart microcode to re-read the new mode */ 8602 bnx2x_warpcore_reset_lane(bp, phy, 1); 8603 bnx2x_warpcore_reset_lane(bp, phy, 0); 8604 8605 } 8606 8607 static void bnx2x_set_limiting_mode(struct link_params *params, 8608 struct bnx2x_phy *phy, 8609 u16 edc_mode) 8610 { 8611 switch (phy->type) { 8612 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: 8613 bnx2x_8726_set_limiting_mode(params->bp, phy, edc_mode); 8614 break; 8615 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: 8616 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722: 8617 bnx2x_8727_set_limiting_mode(params->bp, phy, edc_mode); 8618 break; 8619 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT: 8620 bnx2x_warpcore_set_limiting_mode(params, phy, edc_mode); 8621 break; 8622 } 8623 } 8624 8625 static int bnx2x_sfp_module_detection(struct bnx2x_phy *phy, 8626 struct link_params *params) 8627 { 8628 struct bnx2x *bp = params->bp; 8629 u16 edc_mode; 8630 int rc = 0; 8631 8632 u32 val = REG_RD(bp, params->shmem_base + 8633 offsetof(struct shmem_region, dev_info. 8634 port_feature_config[params->port].config)); 8635 /* Enabled transmitter by default */ 8636 bnx2x_sfp_set_transmitter(params, phy, 1); 8637 DP(NETIF_MSG_LINK, "SFP+ module plugged in/out detected on port %d\n", 8638 params->port); 8639 /* Power up module */ 8640 bnx2x_power_sfp_module(params, phy, 1); 8641 if (bnx2x_get_edc_mode(phy, params, &edc_mode) != 0) { 8642 DP(NETIF_MSG_LINK, "Failed to get valid module type\n"); 8643 return -EINVAL; 8644 } else if (bnx2x_verify_sfp_module(phy, params) != 0) { 8645 /* Check SFP+ module compatibility */ 8646 DP(NETIF_MSG_LINK, "Module verification failed!!\n"); 8647 rc = -EINVAL; 8648 /* Turn on fault module-detected led */ 8649 bnx2x_set_sfp_module_fault_led(params, 8650 MISC_REGISTERS_GPIO_HIGH); 8651 8652 /* Check if need to power down the SFP+ module */ 8653 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == 8654 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN) { 8655 DP(NETIF_MSG_LINK, "Shutdown SFP+ module!!\n"); 8656 bnx2x_power_sfp_module(params, phy, 0); 8657 return rc; 8658 } 8659 } else { 8660 /* Turn off fault module-detected led */ 8661 bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_LOW); 8662 } 8663 8664 /* Check and set limiting mode / LRM mode on 8726. On 8727 it 8665 * is done automatically 8666 */ 8667 bnx2x_set_limiting_mode(params, phy, edc_mode); 8668 8669 /* Disable transmit for this module if the module is not approved, and 8670 * laser needs to be disabled. 8671 */ 8672 if ((rc) && 8673 ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == 8674 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)) 8675 bnx2x_sfp_set_transmitter(params, phy, 0); 8676 8677 return rc; 8678 } 8679 8680 void bnx2x_handle_module_detect_int(struct link_params *params) 8681 { 8682 struct bnx2x *bp = params->bp; 8683 struct bnx2x_phy *phy; 8684 u32 gpio_val; 8685 u8 gpio_num, gpio_port; 8686 if (CHIP_IS_E3(bp)) { 8687 phy = ¶ms->phy[INT_PHY]; 8688 /* Always enable TX laser,will be disabled in case of fault */ 8689 bnx2x_sfp_set_transmitter(params, phy, 1); 8690 } else { 8691 phy = ¶ms->phy[EXT_PHY1]; 8692 } 8693 if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id, params->shmem_base, 8694 params->port, &gpio_num, &gpio_port) == 8695 -EINVAL) { 8696 DP(NETIF_MSG_LINK, "Failed to get MOD_ABS interrupt config\n"); 8697 return; 8698 } 8699 8700 /* Set valid module led off */ 8701 bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_HIGH); 8702 8703 /* Get current gpio val reflecting module plugged in / out*/ 8704 gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port); 8705 8706 /* Call the handling function in case module is detected */ 8707 if (gpio_val == 0) { 8708 bnx2x_set_mdio_emac_per_phy(bp, params); 8709 bnx2x_set_aer_mmd(params, phy); 8710 8711 bnx2x_power_sfp_module(params, phy, 1); 8712 bnx2x_set_gpio_int(bp, gpio_num, 8713 MISC_REGISTERS_GPIO_INT_OUTPUT_CLR, 8714 gpio_port); 8715 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0) { 8716 bnx2x_sfp_module_detection(phy, params); 8717 if (CHIP_IS_E3(bp)) { 8718 u16 rx_tx_in_reset; 8719 /* In case WC is out of reset, reconfigure the 8720 * link speed while taking into account 1G 8721 * module limitation. 8722 */ 8723 bnx2x_cl45_read(bp, phy, 8724 MDIO_WC_DEVAD, 8725 MDIO_WC_REG_DIGITAL5_MISC6, 8726 &rx_tx_in_reset); 8727 if ((!rx_tx_in_reset) && 8728 (params->link_flags & 8729 PHY_INITIALIZED)) { 8730 bnx2x_warpcore_reset_lane(bp, phy, 1); 8731 bnx2x_warpcore_config_sfi(phy, params); 8732 bnx2x_warpcore_reset_lane(bp, phy, 0); 8733 } 8734 } 8735 } else { 8736 DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n"); 8737 } 8738 } else { 8739 bnx2x_set_gpio_int(bp, gpio_num, 8740 MISC_REGISTERS_GPIO_INT_OUTPUT_SET, 8741 gpio_port); 8742 /* Module was plugged out. 8743 * Disable transmit for this module 8744 */ 8745 phy->media_type = ETH_PHY_NOT_PRESENT; 8746 } 8747 } 8748 8749 /******************************************************************/ 8750 /* Used by 8706 and 8727 */ 8751 /******************************************************************/ 8752 static void bnx2x_sfp_mask_fault(struct bnx2x *bp, 8753 struct bnx2x_phy *phy, 8754 u16 alarm_status_offset, 8755 u16 alarm_ctrl_offset) 8756 { 8757 u16 alarm_status, val; 8758 bnx2x_cl45_read(bp, phy, 8759 MDIO_PMA_DEVAD, alarm_status_offset, 8760 &alarm_status); 8761 bnx2x_cl45_read(bp, phy, 8762 MDIO_PMA_DEVAD, alarm_status_offset, 8763 &alarm_status); 8764 /* Mask or enable the fault event. */ 8765 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, &val); 8766 if (alarm_status & (1<<0)) 8767 val &= ~(1<<0); 8768 else 8769 val |= (1<<0); 8770 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, val); 8771 } 8772 /******************************************************************/ 8773 /* common BCM8706/BCM8726 PHY SECTION */ 8774 /******************************************************************/ 8775 static u8 bnx2x_8706_8726_read_status(struct bnx2x_phy *phy, 8776 struct link_params *params, 8777 struct link_vars *vars) 8778 { 8779 u8 link_up = 0; 8780 u16 val1, val2, rx_sd, pcs_status; 8781 struct bnx2x *bp = params->bp; 8782 DP(NETIF_MSG_LINK, "XGXS 8706/8726\n"); 8783 /* Clear RX Alarm*/ 8784 bnx2x_cl45_read(bp, phy, 8785 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2); 8786 8787 bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT, 8788 MDIO_PMA_LASI_TXCTRL); 8789 8790 /* Clear LASI indication*/ 8791 bnx2x_cl45_read(bp, phy, 8792 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1); 8793 bnx2x_cl45_read(bp, phy, 8794 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2); 8795 DP(NETIF_MSG_LINK, "8706/8726 LASI status 0x%x--> 0x%x\n", val1, val2); 8796 8797 bnx2x_cl45_read(bp, phy, 8798 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd); 8799 bnx2x_cl45_read(bp, phy, 8800 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &pcs_status); 8801 bnx2x_cl45_read(bp, phy, 8802 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2); 8803 bnx2x_cl45_read(bp, phy, 8804 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2); 8805 8806 DP(NETIF_MSG_LINK, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps" 8807 " link_status 0x%x\n", rx_sd, pcs_status, val2); 8808 /* Link is up if both bit 0 of pmd_rx_sd and bit 0 of pcs_status 8809 * are set, or if the autoneg bit 1 is set 8810 */ 8811 link_up = ((rx_sd & pcs_status & 0x1) || (val2 & (1<<1))); 8812 if (link_up) { 8813 if (val2 & (1<<1)) 8814 vars->line_speed = SPEED_1000; 8815 else 8816 vars->line_speed = SPEED_10000; 8817 bnx2x_ext_phy_resolve_fc(phy, params, vars); 8818 vars->duplex = DUPLEX_FULL; 8819 } 8820 8821 /* Capture 10G link fault. Read twice to clear stale value. */ 8822 if (vars->line_speed == SPEED_10000) { 8823 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 8824 MDIO_PMA_LASI_TXSTAT, &val1); 8825 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 8826 MDIO_PMA_LASI_TXSTAT, &val1); 8827 if (val1 & (1<<0)) 8828 vars->fault_detected = 1; 8829 } 8830 8831 return link_up; 8832 } 8833 8834 /******************************************************************/ 8835 /* BCM8706 PHY SECTION */ 8836 /******************************************************************/ 8837 static u8 bnx2x_8706_config_init(struct bnx2x_phy *phy, 8838 struct link_params *params, 8839 struct link_vars *vars) 8840 { 8841 u32 tx_en_mode; 8842 u16 cnt, val, tmp1; 8843 struct bnx2x *bp = params->bp; 8844 8845 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 8846 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); 8847 /* HW reset */ 8848 bnx2x_ext_phy_hw_reset(bp, params->port); 8849 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040); 8850 bnx2x_wait_reset_complete(bp, phy, params); 8851 8852 /* Wait until fw is loaded */ 8853 for (cnt = 0; cnt < 100; cnt++) { 8854 bnx2x_cl45_read(bp, phy, 8855 MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER1, &val); 8856 if (val) 8857 break; 8858 usleep_range(10000, 20000); 8859 } 8860 DP(NETIF_MSG_LINK, "XGXS 8706 is initialized after %d ms\n", cnt); 8861 if ((params->feature_config_flags & 8862 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) { 8863 u8 i; 8864 u16 reg; 8865 for (i = 0; i < 4; i++) { 8866 reg = MDIO_XS_8706_REG_BANK_RX0 + 8867 i*(MDIO_XS_8706_REG_BANK_RX1 - 8868 MDIO_XS_8706_REG_BANK_RX0); 8869 bnx2x_cl45_read(bp, phy, MDIO_XS_DEVAD, reg, &val); 8870 /* Clear first 3 bits of the control */ 8871 val &= ~0x7; 8872 /* Set control bits according to configuration */ 8873 val |= (phy->rx_preemphasis[i] & 0x7); 8874 DP(NETIF_MSG_LINK, "Setting RX Equalizer to BCM8706" 8875 " reg 0x%x <-- val 0x%x\n", reg, val); 8876 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, reg, val); 8877 } 8878 } 8879 /* Force speed */ 8880 if (phy->req_line_speed == SPEED_10000) { 8881 DP(NETIF_MSG_LINK, "XGXS 8706 force 10Gbps\n"); 8882 8883 bnx2x_cl45_write(bp, phy, 8884 MDIO_PMA_DEVAD, 8885 MDIO_PMA_REG_DIGITAL_CTRL, 0x400); 8886 bnx2x_cl45_write(bp, phy, 8887 MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL, 8888 0); 8889 /* Arm LASI for link and Tx fault. */ 8890 bnx2x_cl45_write(bp, phy, 8891 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 3); 8892 } else { 8893 /* Force 1Gbps using autoneg with 1G advertisement */ 8894 8895 /* Allow CL37 through CL73 */ 8896 DP(NETIF_MSG_LINK, "XGXS 8706 AutoNeg\n"); 8897 bnx2x_cl45_write(bp, phy, 8898 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c); 8899 8900 /* Enable Full-Duplex advertisement on CL37 */ 8901 bnx2x_cl45_write(bp, phy, 8902 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LP, 0x0020); 8903 /* Enable CL37 AN */ 8904 bnx2x_cl45_write(bp, phy, 8905 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000); 8906 /* 1G support */ 8907 bnx2x_cl45_write(bp, phy, 8908 MDIO_AN_DEVAD, MDIO_AN_REG_ADV, (1<<5)); 8909 8910 /* Enable clause 73 AN */ 8911 bnx2x_cl45_write(bp, phy, 8912 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200); 8913 bnx2x_cl45_write(bp, phy, 8914 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, 8915 0x0400); 8916 bnx2x_cl45_write(bp, phy, 8917 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 8918 0x0004); 8919 } 8920 bnx2x_save_bcm_spirom_ver(bp, phy, params->port); 8921 8922 /* If TX Laser is controlled by GPIO_0, do not let PHY go into low 8923 * power mode, if TX Laser is disabled 8924 */ 8925 8926 tx_en_mode = REG_RD(bp, params->shmem_base + 8927 offsetof(struct shmem_region, 8928 dev_info.port_hw_config[params->port].sfp_ctrl)) 8929 & PORT_HW_CFG_TX_LASER_MASK; 8930 8931 if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) { 8932 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n"); 8933 bnx2x_cl45_read(bp, phy, 8934 MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, &tmp1); 8935 tmp1 |= 0x1; 8936 bnx2x_cl45_write(bp, phy, 8937 MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, tmp1); 8938 } 8939 8940 return 0; 8941 } 8942 8943 static int bnx2x_8706_read_status(struct bnx2x_phy *phy, 8944 struct link_params *params, 8945 struct link_vars *vars) 8946 { 8947 return bnx2x_8706_8726_read_status(phy, params, vars); 8948 } 8949 8950 /******************************************************************/ 8951 /* BCM8726 PHY SECTION */ 8952 /******************************************************************/ 8953 static void bnx2x_8726_config_loopback(struct bnx2x_phy *phy, 8954 struct link_params *params) 8955 { 8956 struct bnx2x *bp = params->bp; 8957 DP(NETIF_MSG_LINK, "PMA/PMD ext_phy_loopback: 8726\n"); 8958 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001); 8959 } 8960 8961 static void bnx2x_8726_external_rom_boot(struct bnx2x_phy *phy, 8962 struct link_params *params) 8963 { 8964 struct bnx2x *bp = params->bp; 8965 /* Need to wait 100ms after reset */ 8966 msleep(100); 8967 8968 /* Micro controller re-boot */ 8969 bnx2x_cl45_write(bp, phy, 8970 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x018B); 8971 8972 /* Set soft reset */ 8973 bnx2x_cl45_write(bp, phy, 8974 MDIO_PMA_DEVAD, 8975 MDIO_PMA_REG_GEN_CTRL, 8976 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET); 8977 8978 bnx2x_cl45_write(bp, phy, 8979 MDIO_PMA_DEVAD, 8980 MDIO_PMA_REG_MISC_CTRL1, 0x0001); 8981 8982 bnx2x_cl45_write(bp, phy, 8983 MDIO_PMA_DEVAD, 8984 MDIO_PMA_REG_GEN_CTRL, 8985 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP); 8986 8987 /* Wait for 150ms for microcode load */ 8988 msleep(150); 8989 8990 /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */ 8991 bnx2x_cl45_write(bp, phy, 8992 MDIO_PMA_DEVAD, 8993 MDIO_PMA_REG_MISC_CTRL1, 0x0000); 8994 8995 msleep(200); 8996 bnx2x_save_bcm_spirom_ver(bp, phy, params->port); 8997 } 8998 8999 static u8 bnx2x_8726_read_status(struct bnx2x_phy *phy, 9000 struct link_params *params, 9001 struct link_vars *vars) 9002 { 9003 struct bnx2x *bp = params->bp; 9004 u16 val1; 9005 u8 link_up = bnx2x_8706_8726_read_status(phy, params, vars); 9006 if (link_up) { 9007 bnx2x_cl45_read(bp, phy, 9008 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 9009 &val1); 9010 if (val1 & (1<<15)) { 9011 DP(NETIF_MSG_LINK, "Tx is disabled\n"); 9012 link_up = 0; 9013 vars->line_speed = 0; 9014 } 9015 } 9016 return link_up; 9017 } 9018 9019 9020 static int bnx2x_8726_config_init(struct bnx2x_phy *phy, 9021 struct link_params *params, 9022 struct link_vars *vars) 9023 { 9024 struct bnx2x *bp = params->bp; 9025 DP(NETIF_MSG_LINK, "Initializing BCM8726\n"); 9026 9027 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15); 9028 bnx2x_wait_reset_complete(bp, phy, params); 9029 9030 bnx2x_8726_external_rom_boot(phy, params); 9031 9032 /* Need to call module detected on initialization since the module 9033 * detection triggered by actual module insertion might occur before 9034 * driver is loaded, and when driver is loaded, it reset all 9035 * registers, including the transmitter 9036 */ 9037 bnx2x_sfp_module_detection(phy, params); 9038 9039 if (phy->req_line_speed == SPEED_1000) { 9040 DP(NETIF_MSG_LINK, "Setting 1G force\n"); 9041 bnx2x_cl45_write(bp, phy, 9042 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40); 9043 bnx2x_cl45_write(bp, phy, 9044 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD); 9045 bnx2x_cl45_write(bp, phy, 9046 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x5); 9047 bnx2x_cl45_write(bp, phy, 9048 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, 9049 0x400); 9050 } else if ((phy->req_line_speed == SPEED_AUTO_NEG) && 9051 (phy->speed_cap_mask & 9052 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) && 9053 ((phy->speed_cap_mask & 9054 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) != 9055 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) { 9056 DP(NETIF_MSG_LINK, "Setting 1G clause37\n"); 9057 /* Set Flow control */ 9058 bnx2x_ext_phy_set_pause(params, phy, vars); 9059 bnx2x_cl45_write(bp, phy, 9060 MDIO_AN_DEVAD, MDIO_AN_REG_ADV, 0x20); 9061 bnx2x_cl45_write(bp, phy, 9062 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c); 9063 bnx2x_cl45_write(bp, phy, 9064 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, 0x0020); 9065 bnx2x_cl45_write(bp, phy, 9066 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000); 9067 bnx2x_cl45_write(bp, phy, 9068 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200); 9069 /* Enable RX-ALARM control to receive interrupt for 1G speed 9070 * change 9071 */ 9072 bnx2x_cl45_write(bp, phy, 9073 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x4); 9074 bnx2x_cl45_write(bp, phy, 9075 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, 9076 0x400); 9077 9078 } else { /* Default 10G. Set only LASI control */ 9079 bnx2x_cl45_write(bp, phy, 9080 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 1); 9081 } 9082 9083 /* Set TX PreEmphasis if needed */ 9084 if ((params->feature_config_flags & 9085 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) { 9086 DP(NETIF_MSG_LINK, 9087 "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n", 9088 phy->tx_preemphasis[0], 9089 phy->tx_preemphasis[1]); 9090 bnx2x_cl45_write(bp, phy, 9091 MDIO_PMA_DEVAD, 9092 MDIO_PMA_REG_8726_TX_CTRL1, 9093 phy->tx_preemphasis[0]); 9094 9095 bnx2x_cl45_write(bp, phy, 9096 MDIO_PMA_DEVAD, 9097 MDIO_PMA_REG_8726_TX_CTRL2, 9098 phy->tx_preemphasis[1]); 9099 } 9100 9101 return 0; 9102 9103 } 9104 9105 static void bnx2x_8726_link_reset(struct bnx2x_phy *phy, 9106 struct link_params *params) 9107 { 9108 struct bnx2x *bp = params->bp; 9109 DP(NETIF_MSG_LINK, "bnx2x_8726_link_reset port %d\n", params->port); 9110 /* Set serial boot control for external load */ 9111 bnx2x_cl45_write(bp, phy, 9112 MDIO_PMA_DEVAD, 9113 MDIO_PMA_REG_GEN_CTRL, 0x0001); 9114 } 9115 9116 /******************************************************************/ 9117 /* BCM8727 PHY SECTION */ 9118 /******************************************************************/ 9119 9120 static void bnx2x_8727_set_link_led(struct bnx2x_phy *phy, 9121 struct link_params *params, u8 mode) 9122 { 9123 struct bnx2x *bp = params->bp; 9124 u16 led_mode_bitmask = 0; 9125 u16 gpio_pins_bitmask = 0; 9126 u16 val; 9127 /* Only NOC flavor requires to set the LED specifically */ 9128 if (!(phy->flags & FLAGS_NOC)) 9129 return; 9130 switch (mode) { 9131 case LED_MODE_FRONT_PANEL_OFF: 9132 case LED_MODE_OFF: 9133 led_mode_bitmask = 0; 9134 gpio_pins_bitmask = 0x03; 9135 break; 9136 case LED_MODE_ON: 9137 led_mode_bitmask = 0; 9138 gpio_pins_bitmask = 0x02; 9139 break; 9140 case LED_MODE_OPER: 9141 led_mode_bitmask = 0x60; 9142 gpio_pins_bitmask = 0x11; 9143 break; 9144 } 9145 bnx2x_cl45_read(bp, phy, 9146 MDIO_PMA_DEVAD, 9147 MDIO_PMA_REG_8727_PCS_OPT_CTRL, 9148 &val); 9149 val &= 0xff8f; 9150 val |= led_mode_bitmask; 9151 bnx2x_cl45_write(bp, phy, 9152 MDIO_PMA_DEVAD, 9153 MDIO_PMA_REG_8727_PCS_OPT_CTRL, 9154 val); 9155 bnx2x_cl45_read(bp, phy, 9156 MDIO_PMA_DEVAD, 9157 MDIO_PMA_REG_8727_GPIO_CTRL, 9158 &val); 9159 val &= 0xffe0; 9160 val |= gpio_pins_bitmask; 9161 bnx2x_cl45_write(bp, phy, 9162 MDIO_PMA_DEVAD, 9163 MDIO_PMA_REG_8727_GPIO_CTRL, 9164 val); 9165 } 9166 static void bnx2x_8727_hw_reset(struct bnx2x_phy *phy, 9167 struct link_params *params) { 9168 u32 swap_val, swap_override; 9169 u8 port; 9170 /* The PHY reset is controlled by GPIO 1. Fake the port number 9171 * to cancel the swap done in set_gpio() 9172 */ 9173 struct bnx2x *bp = params->bp; 9174 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); 9175 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); 9176 port = (swap_val && swap_override) ^ 1; 9177 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, 9178 MISC_REGISTERS_GPIO_OUTPUT_LOW, port); 9179 } 9180 9181 static void bnx2x_8727_config_speed(struct bnx2x_phy *phy, 9182 struct link_params *params) 9183 { 9184 struct bnx2x *bp = params->bp; 9185 u16 tmp1, val; 9186 /* Set option 1G speed */ 9187 if ((phy->req_line_speed == SPEED_1000) || 9188 (phy->media_type == ETH_PHY_SFP_1G_FIBER)) { 9189 DP(NETIF_MSG_LINK, "Setting 1G force\n"); 9190 bnx2x_cl45_write(bp, phy, 9191 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40); 9192 bnx2x_cl45_write(bp, phy, 9193 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD); 9194 bnx2x_cl45_read(bp, phy, 9195 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, &tmp1); 9196 DP(NETIF_MSG_LINK, "1.7 = 0x%x\n", tmp1); 9197 /* Power down the XAUI until link is up in case of dual-media 9198 * and 1G 9199 */ 9200 if (DUAL_MEDIA(params)) { 9201 bnx2x_cl45_read(bp, phy, 9202 MDIO_PMA_DEVAD, 9203 MDIO_PMA_REG_8727_PCS_GP, &val); 9204 val |= (3<<10); 9205 bnx2x_cl45_write(bp, phy, 9206 MDIO_PMA_DEVAD, 9207 MDIO_PMA_REG_8727_PCS_GP, val); 9208 } 9209 } else if ((phy->req_line_speed == SPEED_AUTO_NEG) && 9210 ((phy->speed_cap_mask & 9211 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) && 9212 ((phy->speed_cap_mask & 9213 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) != 9214 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) { 9215 9216 DP(NETIF_MSG_LINK, "Setting 1G clause37\n"); 9217 bnx2x_cl45_write(bp, phy, 9218 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 0); 9219 bnx2x_cl45_write(bp, phy, 9220 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1300); 9221 } else { 9222 /* Since the 8727 has only single reset pin, need to set the 10G 9223 * registers although it is default 9224 */ 9225 bnx2x_cl45_write(bp, phy, 9226 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 9227 0x0020); 9228 bnx2x_cl45_write(bp, phy, 9229 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x0100); 9230 bnx2x_cl45_write(bp, phy, 9231 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040); 9232 bnx2x_cl45_write(bp, phy, 9233 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 9234 0x0008); 9235 } 9236 } 9237 9238 static int bnx2x_8727_config_init(struct bnx2x_phy *phy, 9239 struct link_params *params, 9240 struct link_vars *vars) 9241 { 9242 u32 tx_en_mode; 9243 u16 tmp1, mod_abs, tmp2; 9244 struct bnx2x *bp = params->bp; 9245 /* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */ 9246 9247 bnx2x_wait_reset_complete(bp, phy, params); 9248 9249 DP(NETIF_MSG_LINK, "Initializing BCM8727\n"); 9250 9251 bnx2x_8727_specific_func(phy, params, PHY_INIT); 9252 /* Initially configure MOD_ABS to interrupt when module is 9253 * presence( bit 8) 9254 */ 9255 bnx2x_cl45_read(bp, phy, 9256 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs); 9257 /* Set EDC off by setting OPTXLOS signal input to low (bit 9). 9258 * When the EDC is off it locks onto a reference clock and avoids 9259 * becoming 'lost' 9260 */ 9261 mod_abs &= ~(1<<8); 9262 if (!(phy->flags & FLAGS_NOC)) 9263 mod_abs &= ~(1<<9); 9264 bnx2x_cl45_write(bp, phy, 9265 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs); 9266 9267 /* Enable/Disable PHY transmitter output */ 9268 bnx2x_set_disable_pmd_transmit(params, phy, 0); 9269 9270 bnx2x_8727_power_module(bp, phy, 1); 9271 9272 bnx2x_cl45_read(bp, phy, 9273 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1); 9274 9275 bnx2x_cl45_read(bp, phy, 9276 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1); 9277 9278 bnx2x_8727_config_speed(phy, params); 9279 9280 9281 /* Set TX PreEmphasis if needed */ 9282 if ((params->feature_config_flags & 9283 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) { 9284 DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n", 9285 phy->tx_preemphasis[0], 9286 phy->tx_preemphasis[1]); 9287 bnx2x_cl45_write(bp, phy, 9288 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL1, 9289 phy->tx_preemphasis[0]); 9290 9291 bnx2x_cl45_write(bp, phy, 9292 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL2, 9293 phy->tx_preemphasis[1]); 9294 } 9295 9296 /* If TX Laser is controlled by GPIO_0, do not let PHY go into low 9297 * power mode, if TX Laser is disabled 9298 */ 9299 tx_en_mode = REG_RD(bp, params->shmem_base + 9300 offsetof(struct shmem_region, 9301 dev_info.port_hw_config[params->port].sfp_ctrl)) 9302 & PORT_HW_CFG_TX_LASER_MASK; 9303 9304 if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) { 9305 9306 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n"); 9307 bnx2x_cl45_read(bp, phy, 9308 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, &tmp2); 9309 tmp2 |= 0x1000; 9310 tmp2 &= 0xFFEF; 9311 bnx2x_cl45_write(bp, phy, 9312 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, tmp2); 9313 bnx2x_cl45_read(bp, phy, 9314 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 9315 &tmp2); 9316 bnx2x_cl45_write(bp, phy, 9317 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 9318 (tmp2 & 0x7fff)); 9319 } 9320 9321 return 0; 9322 } 9323 9324 static void bnx2x_8727_handle_mod_abs(struct bnx2x_phy *phy, 9325 struct link_params *params) 9326 { 9327 struct bnx2x *bp = params->bp; 9328 u16 mod_abs, rx_alarm_status; 9329 u32 val = REG_RD(bp, params->shmem_base + 9330 offsetof(struct shmem_region, dev_info. 9331 port_feature_config[params->port]. 9332 config)); 9333 bnx2x_cl45_read(bp, phy, 9334 MDIO_PMA_DEVAD, 9335 MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs); 9336 if (mod_abs & (1<<8)) { 9337 9338 /* Module is absent */ 9339 DP(NETIF_MSG_LINK, 9340 "MOD_ABS indication show module is absent\n"); 9341 phy->media_type = ETH_PHY_NOT_PRESENT; 9342 /* 1. Set mod_abs to detect next module 9343 * presence event 9344 * 2. Set EDC off by setting OPTXLOS signal input to low 9345 * (bit 9). 9346 * When the EDC is off it locks onto a reference clock and 9347 * avoids becoming 'lost'. 9348 */ 9349 mod_abs &= ~(1<<8); 9350 if (!(phy->flags & FLAGS_NOC)) 9351 mod_abs &= ~(1<<9); 9352 bnx2x_cl45_write(bp, phy, 9353 MDIO_PMA_DEVAD, 9354 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs); 9355 9356 /* Clear RX alarm since it stays up as long as 9357 * the mod_abs wasn't changed 9358 */ 9359 bnx2x_cl45_read(bp, phy, 9360 MDIO_PMA_DEVAD, 9361 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status); 9362 9363 } else { 9364 /* Module is present */ 9365 DP(NETIF_MSG_LINK, 9366 "MOD_ABS indication show module is present\n"); 9367 /* First disable transmitter, and if the module is ok, the 9368 * module_detection will enable it 9369 * 1. Set mod_abs to detect next module absent event ( bit 8) 9370 * 2. Restore the default polarity of the OPRXLOS signal and 9371 * this signal will then correctly indicate the presence or 9372 * absence of the Rx signal. (bit 9) 9373 */ 9374 mod_abs |= (1<<8); 9375 if (!(phy->flags & FLAGS_NOC)) 9376 mod_abs |= (1<<9); 9377 bnx2x_cl45_write(bp, phy, 9378 MDIO_PMA_DEVAD, 9379 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs); 9380 9381 /* Clear RX alarm since it stays up as long as the mod_abs 9382 * wasn't changed. This is need to be done before calling the 9383 * module detection, otherwise it will clear* the link update 9384 * alarm 9385 */ 9386 bnx2x_cl45_read(bp, phy, 9387 MDIO_PMA_DEVAD, 9388 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status); 9389 9390 9391 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == 9392 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER) 9393 bnx2x_sfp_set_transmitter(params, phy, 0); 9394 9395 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0) 9396 bnx2x_sfp_module_detection(phy, params); 9397 else 9398 DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n"); 9399 9400 /* Reconfigure link speed based on module type limitations */ 9401 bnx2x_8727_config_speed(phy, params); 9402 } 9403 9404 DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n", 9405 rx_alarm_status); 9406 /* No need to check link status in case of module plugged in/out */ 9407 } 9408 9409 static u8 bnx2x_8727_read_status(struct bnx2x_phy *phy, 9410 struct link_params *params, 9411 struct link_vars *vars) 9412 9413 { 9414 struct bnx2x *bp = params->bp; 9415 u8 link_up = 0, oc_port = params->port; 9416 u16 link_status = 0; 9417 u16 rx_alarm_status, lasi_ctrl, val1; 9418 9419 /* If PHY is not initialized, do not check link status */ 9420 bnx2x_cl45_read(bp, phy, 9421 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 9422 &lasi_ctrl); 9423 if (!lasi_ctrl) 9424 return 0; 9425 9426 /* Check the LASI on Rx */ 9427 bnx2x_cl45_read(bp, phy, 9428 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, 9429 &rx_alarm_status); 9430 vars->line_speed = 0; 9431 DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n", rx_alarm_status); 9432 9433 bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT, 9434 MDIO_PMA_LASI_TXCTRL); 9435 9436 bnx2x_cl45_read(bp, phy, 9437 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1); 9438 9439 DP(NETIF_MSG_LINK, "8727 LASI status 0x%x\n", val1); 9440 9441 /* Clear MSG-OUT */ 9442 bnx2x_cl45_read(bp, phy, 9443 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1); 9444 9445 /* If a module is present and there is need to check 9446 * for over current 9447 */ 9448 if (!(phy->flags & FLAGS_NOC) && !(rx_alarm_status & (1<<5))) { 9449 /* Check over-current using 8727 GPIO0 input*/ 9450 bnx2x_cl45_read(bp, phy, 9451 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL, 9452 &val1); 9453 9454 if ((val1 & (1<<8)) == 0) { 9455 if (!CHIP_IS_E1x(bp)) 9456 oc_port = BP_PATH(bp) + (params->port << 1); 9457 DP(NETIF_MSG_LINK, 9458 "8727 Power fault has been detected on port %d\n", 9459 oc_port); 9460 netdev_err(bp->dev, "Error: Power fault on Port %d has " 9461 "been detected and the power to " 9462 "that SFP+ module has been removed " 9463 "to prevent failure of the card. " 9464 "Please remove the SFP+ module and " 9465 "restart the system to clear this " 9466 "error.\n", 9467 oc_port); 9468 /* Disable all RX_ALARMs except for mod_abs */ 9469 bnx2x_cl45_write(bp, phy, 9470 MDIO_PMA_DEVAD, 9471 MDIO_PMA_LASI_RXCTRL, (1<<5)); 9472 9473 bnx2x_cl45_read(bp, phy, 9474 MDIO_PMA_DEVAD, 9475 MDIO_PMA_REG_PHY_IDENTIFIER, &val1); 9476 /* Wait for module_absent_event */ 9477 val1 |= (1<<8); 9478 bnx2x_cl45_write(bp, phy, 9479 MDIO_PMA_DEVAD, 9480 MDIO_PMA_REG_PHY_IDENTIFIER, val1); 9481 /* Clear RX alarm */ 9482 bnx2x_cl45_read(bp, phy, 9483 MDIO_PMA_DEVAD, 9484 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status); 9485 bnx2x_8727_power_module(params->bp, phy, 0); 9486 return 0; 9487 } 9488 } /* Over current check */ 9489 9490 /* When module absent bit is set, check module */ 9491 if (rx_alarm_status & (1<<5)) { 9492 bnx2x_8727_handle_mod_abs(phy, params); 9493 /* Enable all mod_abs and link detection bits */ 9494 bnx2x_cl45_write(bp, phy, 9495 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, 9496 ((1<<5) | (1<<2))); 9497 } 9498 9499 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED)) { 9500 DP(NETIF_MSG_LINK, "Enabling 8727 TX laser\n"); 9501 bnx2x_sfp_set_transmitter(params, phy, 1); 9502 } else { 9503 DP(NETIF_MSG_LINK, "Tx is disabled\n"); 9504 return 0; 9505 } 9506 9507 bnx2x_cl45_read(bp, phy, 9508 MDIO_PMA_DEVAD, 9509 MDIO_PMA_REG_8073_SPEED_LINK_STATUS, &link_status); 9510 9511 /* Bits 0..2 --> speed detected, 9512 * Bits 13..15--> link is down 9513 */ 9514 if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) { 9515 link_up = 1; 9516 vars->line_speed = SPEED_10000; 9517 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n", 9518 params->port); 9519 } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) { 9520 link_up = 1; 9521 vars->line_speed = SPEED_1000; 9522 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n", 9523 params->port); 9524 } else { 9525 link_up = 0; 9526 DP(NETIF_MSG_LINK, "port %x: External link is down\n", 9527 params->port); 9528 } 9529 9530 /* Capture 10G link fault. */ 9531 if (vars->line_speed == SPEED_10000) { 9532 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 9533 MDIO_PMA_LASI_TXSTAT, &val1); 9534 9535 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 9536 MDIO_PMA_LASI_TXSTAT, &val1); 9537 9538 if (val1 & (1<<0)) { 9539 vars->fault_detected = 1; 9540 } 9541 } 9542 9543 if (link_up) { 9544 bnx2x_ext_phy_resolve_fc(phy, params, vars); 9545 vars->duplex = DUPLEX_FULL; 9546 DP(NETIF_MSG_LINK, "duplex = 0x%x\n", vars->duplex); 9547 } 9548 9549 if ((DUAL_MEDIA(params)) && 9550 (phy->req_line_speed == SPEED_1000)) { 9551 bnx2x_cl45_read(bp, phy, 9552 MDIO_PMA_DEVAD, 9553 MDIO_PMA_REG_8727_PCS_GP, &val1); 9554 /* In case of dual-media board and 1G, power up the XAUI side, 9555 * otherwise power it down. For 10G it is done automatically 9556 */ 9557 if (link_up) 9558 val1 &= ~(3<<10); 9559 else 9560 val1 |= (3<<10); 9561 bnx2x_cl45_write(bp, phy, 9562 MDIO_PMA_DEVAD, 9563 MDIO_PMA_REG_8727_PCS_GP, val1); 9564 } 9565 return link_up; 9566 } 9567 9568 static void bnx2x_8727_link_reset(struct bnx2x_phy *phy, 9569 struct link_params *params) 9570 { 9571 struct bnx2x *bp = params->bp; 9572 9573 /* Enable/Disable PHY transmitter output */ 9574 bnx2x_set_disable_pmd_transmit(params, phy, 1); 9575 9576 /* Disable Transmitter */ 9577 bnx2x_sfp_set_transmitter(params, phy, 0); 9578 /* Clear LASI */ 9579 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0); 9580 9581 } 9582 9583 /******************************************************************/ 9584 /* BCM8481/BCM84823/BCM84833 PHY SECTION */ 9585 /******************************************************************/ 9586 static void bnx2x_save_848xx_spirom_version(struct bnx2x_phy *phy, 9587 struct bnx2x *bp, 9588 u8 port) 9589 { 9590 u16 val, fw_ver2, cnt, i; 9591 static struct bnx2x_reg_set reg_set[] = { 9592 {MDIO_PMA_DEVAD, 0xA819, 0x0014}, 9593 {MDIO_PMA_DEVAD, 0xA81A, 0xc200}, 9594 {MDIO_PMA_DEVAD, 0xA81B, 0x0000}, 9595 {MDIO_PMA_DEVAD, 0xA81C, 0x0300}, 9596 {MDIO_PMA_DEVAD, 0xA817, 0x0009} 9597 }; 9598 u16 fw_ver1; 9599 9600 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) || 9601 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) { 9602 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 0x400f, &fw_ver1); 9603 bnx2x_save_spirom_version(bp, port, fw_ver1 & 0xfff, 9604 phy->ver_addr); 9605 } else { 9606 /* For 32-bit registers in 848xx, access via MDIO2ARM i/f. */ 9607 /* (1) set reg 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */ 9608 for (i = 0; i < ARRAY_SIZE(reg_set); i++) 9609 bnx2x_cl45_write(bp, phy, reg_set[i].devad, 9610 reg_set[i].reg, reg_set[i].val); 9611 9612 for (cnt = 0; cnt < 100; cnt++) { 9613 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val); 9614 if (val & 1) 9615 break; 9616 udelay(5); 9617 } 9618 if (cnt == 100) { 9619 DP(NETIF_MSG_LINK, "Unable to read 848xx " 9620 "phy fw version(1)\n"); 9621 bnx2x_save_spirom_version(bp, port, 0, 9622 phy->ver_addr); 9623 return; 9624 } 9625 9626 9627 /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */ 9628 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0000); 9629 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200); 9630 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x000A); 9631 for (cnt = 0; cnt < 100; cnt++) { 9632 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val); 9633 if (val & 1) 9634 break; 9635 udelay(5); 9636 } 9637 if (cnt == 100) { 9638 DP(NETIF_MSG_LINK, "Unable to read 848xx phy fw " 9639 "version(2)\n"); 9640 bnx2x_save_spirom_version(bp, port, 0, 9641 phy->ver_addr); 9642 return; 9643 } 9644 9645 /* lower 16 bits of the register SPI_FW_STATUS */ 9646 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81B, &fw_ver1); 9647 /* upper 16 bits of register SPI_FW_STATUS */ 9648 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81C, &fw_ver2); 9649 9650 bnx2x_save_spirom_version(bp, port, (fw_ver2<<16) | fw_ver1, 9651 phy->ver_addr); 9652 } 9653 9654 } 9655 static void bnx2x_848xx_set_led(struct bnx2x *bp, 9656 struct bnx2x_phy *phy) 9657 { 9658 u16 val, offset, i; 9659 static struct bnx2x_reg_set reg_set[] = { 9660 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED1_MASK, 0x0080}, 9661 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED2_MASK, 0x0018}, 9662 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED3_MASK, 0x0006}, 9663 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED3_BLINK, 0x0000}, 9664 {MDIO_PMA_DEVAD, MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH, 9665 MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ}, 9666 {MDIO_AN_DEVAD, 0xFFFB, 0xFFFD} 9667 }; 9668 /* PHYC_CTL_LED_CTL */ 9669 bnx2x_cl45_read(bp, phy, 9670 MDIO_PMA_DEVAD, 9671 MDIO_PMA_REG_8481_LINK_SIGNAL, &val); 9672 val &= 0xFE00; 9673 val |= 0x0092; 9674 9675 bnx2x_cl45_write(bp, phy, 9676 MDIO_PMA_DEVAD, 9677 MDIO_PMA_REG_8481_LINK_SIGNAL, val); 9678 9679 for (i = 0; i < ARRAY_SIZE(reg_set); i++) 9680 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg, 9681 reg_set[i].val); 9682 9683 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) || 9684 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) 9685 offset = MDIO_PMA_REG_84833_CTL_LED_CTL_1; 9686 else 9687 offset = MDIO_PMA_REG_84823_CTL_LED_CTL_1; 9688 9689 /* stretch_en for LED3*/ 9690 bnx2x_cl45_read_or_write(bp, phy, 9691 MDIO_PMA_DEVAD, offset, 9692 MDIO_PMA_REG_84823_LED3_STRETCH_EN); 9693 } 9694 9695 static void bnx2x_848xx_specific_func(struct bnx2x_phy *phy, 9696 struct link_params *params, 9697 u32 action) 9698 { 9699 struct bnx2x *bp = params->bp; 9700 switch (action) { 9701 case PHY_INIT: 9702 if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) && 9703 (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) { 9704 /* Save spirom version */ 9705 bnx2x_save_848xx_spirom_version(phy, bp, params->port); 9706 } 9707 /* This phy uses the NIG latch mechanism since link indication 9708 * arrives through its LED4 and not via its LASI signal, so we 9709 * get steady signal instead of clear on read 9710 */ 9711 bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4, 9712 1 << NIG_LATCH_BC_ENABLE_MI_INT); 9713 9714 bnx2x_848xx_set_led(bp, phy); 9715 break; 9716 } 9717 } 9718 9719 static int bnx2x_848xx_cmn_config_init(struct bnx2x_phy *phy, 9720 struct link_params *params, 9721 struct link_vars *vars) 9722 { 9723 struct bnx2x *bp = params->bp; 9724 u16 autoneg_val, an_1000_val, an_10_100_val; 9725 9726 bnx2x_848xx_specific_func(phy, params, PHY_INIT); 9727 bnx2x_cl45_write(bp, phy, 9728 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0000); 9729 9730 /* set 1000 speed advertisement */ 9731 bnx2x_cl45_read(bp, phy, 9732 MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL, 9733 &an_1000_val); 9734 9735 bnx2x_ext_phy_set_pause(params, phy, vars); 9736 bnx2x_cl45_read(bp, phy, 9737 MDIO_AN_DEVAD, 9738 MDIO_AN_REG_8481_LEGACY_AN_ADV, 9739 &an_10_100_val); 9740 bnx2x_cl45_read(bp, phy, 9741 MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_MII_CTRL, 9742 &autoneg_val); 9743 /* Disable forced speed */ 9744 autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13)); 9745 an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8)); 9746 9747 if (((phy->req_line_speed == SPEED_AUTO_NEG) && 9748 (phy->speed_cap_mask & 9749 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) || 9750 (phy->req_line_speed == SPEED_1000)) { 9751 an_1000_val |= (1<<8); 9752 autoneg_val |= (1<<9 | 1<<12); 9753 if (phy->req_duplex == DUPLEX_FULL) 9754 an_1000_val |= (1<<9); 9755 DP(NETIF_MSG_LINK, "Advertising 1G\n"); 9756 } else 9757 an_1000_val &= ~((1<<8) | (1<<9)); 9758 9759 bnx2x_cl45_write(bp, phy, 9760 MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL, 9761 an_1000_val); 9762 9763 /* Set 10/100 speed advertisement */ 9764 if (phy->req_line_speed == SPEED_AUTO_NEG) { 9765 if (phy->speed_cap_mask & 9766 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL) { 9767 /* Enable autoneg and restart autoneg for legacy speeds 9768 */ 9769 autoneg_val |= (1<<9 | 1<<12); 9770 an_10_100_val |= (1<<8); 9771 DP(NETIF_MSG_LINK, "Advertising 100M-FD\n"); 9772 } 9773 9774 if (phy->speed_cap_mask & 9775 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF) { 9776 /* Enable autoneg and restart autoneg for legacy speeds 9777 */ 9778 autoneg_val |= (1<<9 | 1<<12); 9779 an_10_100_val |= (1<<7); 9780 DP(NETIF_MSG_LINK, "Advertising 100M-HD\n"); 9781 } 9782 9783 if ((phy->speed_cap_mask & 9784 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) && 9785 (phy->supported & SUPPORTED_10baseT_Full)) { 9786 an_10_100_val |= (1<<6); 9787 autoneg_val |= (1<<9 | 1<<12); 9788 DP(NETIF_MSG_LINK, "Advertising 10M-FD\n"); 9789 } 9790 9791 if ((phy->speed_cap_mask & 9792 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF) && 9793 (phy->supported & SUPPORTED_10baseT_Half)) { 9794 an_10_100_val |= (1<<5); 9795 autoneg_val |= (1<<9 | 1<<12); 9796 DP(NETIF_MSG_LINK, "Advertising 10M-HD\n"); 9797 } 9798 } 9799 9800 /* Only 10/100 are allowed to work in FORCE mode */ 9801 if ((phy->req_line_speed == SPEED_100) && 9802 (phy->supported & 9803 (SUPPORTED_100baseT_Half | 9804 SUPPORTED_100baseT_Full))) { 9805 autoneg_val |= (1<<13); 9806 /* Enabled AUTO-MDIX when autoneg is disabled */ 9807 bnx2x_cl45_write(bp, phy, 9808 MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL, 9809 (1<<15 | 1<<9 | 7<<0)); 9810 /* The PHY needs this set even for forced link. */ 9811 an_10_100_val |= (1<<8) | (1<<7); 9812 DP(NETIF_MSG_LINK, "Setting 100M force\n"); 9813 } 9814 if ((phy->req_line_speed == SPEED_10) && 9815 (phy->supported & 9816 (SUPPORTED_10baseT_Half | 9817 SUPPORTED_10baseT_Full))) { 9818 /* Enabled AUTO-MDIX when autoneg is disabled */ 9819 bnx2x_cl45_write(bp, phy, 9820 MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL, 9821 (1<<15 | 1<<9 | 7<<0)); 9822 DP(NETIF_MSG_LINK, "Setting 10M force\n"); 9823 } 9824 9825 bnx2x_cl45_write(bp, phy, 9826 MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_AN_ADV, 9827 an_10_100_val); 9828 9829 if (phy->req_duplex == DUPLEX_FULL) 9830 autoneg_val |= (1<<8); 9831 9832 /* Always write this if this is not 84833/4. 9833 * For 84833/4, write it only when it's a forced speed. 9834 */ 9835 if (((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) && 9836 (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) || 9837 ((autoneg_val & (1<<12)) == 0)) 9838 bnx2x_cl45_write(bp, phy, 9839 MDIO_AN_DEVAD, 9840 MDIO_AN_REG_8481_LEGACY_MII_CTRL, autoneg_val); 9841 9842 if (((phy->req_line_speed == SPEED_AUTO_NEG) && 9843 (phy->speed_cap_mask & 9844 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) || 9845 (phy->req_line_speed == SPEED_10000)) { 9846 DP(NETIF_MSG_LINK, "Advertising 10G\n"); 9847 /* Restart autoneg for 10G*/ 9848 9849 bnx2x_cl45_read_or_write( 9850 bp, phy, 9851 MDIO_AN_DEVAD, 9852 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL, 9853 0x1000); 9854 bnx2x_cl45_write(bp, phy, 9855 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 9856 0x3200); 9857 } else 9858 bnx2x_cl45_write(bp, phy, 9859 MDIO_AN_DEVAD, 9860 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL, 9861 1); 9862 9863 return 0; 9864 } 9865 9866 static int bnx2x_8481_config_init(struct bnx2x_phy *phy, 9867 struct link_params *params, 9868 struct link_vars *vars) 9869 { 9870 struct bnx2x *bp = params->bp; 9871 /* Restore normal power mode*/ 9872 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 9873 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); 9874 9875 /* HW reset */ 9876 bnx2x_ext_phy_hw_reset(bp, params->port); 9877 bnx2x_wait_reset_complete(bp, phy, params); 9878 9879 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15); 9880 return bnx2x_848xx_cmn_config_init(phy, params, vars); 9881 } 9882 9883 #define PHY84833_CMDHDLR_WAIT 300 9884 #define PHY84833_CMDHDLR_MAX_ARGS 5 9885 static int bnx2x_84833_cmd_hdlr(struct bnx2x_phy *phy, 9886 struct link_params *params, u16 fw_cmd, 9887 u16 cmd_args[], int argc) 9888 { 9889 int idx; 9890 u16 val; 9891 struct bnx2x *bp = params->bp; 9892 /* Write CMD_OPEN_OVERRIDE to STATUS reg */ 9893 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, 9894 MDIO_84833_CMD_HDLR_STATUS, 9895 PHY84833_STATUS_CMD_OPEN_OVERRIDE); 9896 for (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) { 9897 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 9898 MDIO_84833_CMD_HDLR_STATUS, &val); 9899 if (val == PHY84833_STATUS_CMD_OPEN_FOR_CMDS) 9900 break; 9901 usleep_range(1000, 2000); 9902 } 9903 if (idx >= PHY84833_CMDHDLR_WAIT) { 9904 DP(NETIF_MSG_LINK, "FW cmd: FW not ready.\n"); 9905 return -EINVAL; 9906 } 9907 9908 /* Prepare argument(s) and issue command */ 9909 for (idx = 0; idx < argc; idx++) { 9910 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, 9911 MDIO_84833_CMD_HDLR_DATA1 + idx, 9912 cmd_args[idx]); 9913 } 9914 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, 9915 MDIO_84833_CMD_HDLR_COMMAND, fw_cmd); 9916 for (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) { 9917 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 9918 MDIO_84833_CMD_HDLR_STATUS, &val); 9919 if ((val == PHY84833_STATUS_CMD_COMPLETE_PASS) || 9920 (val == PHY84833_STATUS_CMD_COMPLETE_ERROR)) 9921 break; 9922 usleep_range(1000, 2000); 9923 } 9924 if ((idx >= PHY84833_CMDHDLR_WAIT) || 9925 (val == PHY84833_STATUS_CMD_COMPLETE_ERROR)) { 9926 DP(NETIF_MSG_LINK, "FW cmd failed.\n"); 9927 return -EINVAL; 9928 } 9929 /* Gather returning data */ 9930 for (idx = 0; idx < argc; idx++) { 9931 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 9932 MDIO_84833_CMD_HDLR_DATA1 + idx, 9933 &cmd_args[idx]); 9934 } 9935 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, 9936 MDIO_84833_CMD_HDLR_STATUS, 9937 PHY84833_STATUS_CMD_CLEAR_COMPLETE); 9938 return 0; 9939 } 9940 9941 static int bnx2x_84833_pair_swap_cfg(struct bnx2x_phy *phy, 9942 struct link_params *params, 9943 struct link_vars *vars) 9944 { 9945 u32 pair_swap; 9946 u16 data[PHY84833_CMDHDLR_MAX_ARGS]; 9947 int status; 9948 struct bnx2x *bp = params->bp; 9949 9950 /* Check for configuration. */ 9951 pair_swap = REG_RD(bp, params->shmem_base + 9952 offsetof(struct shmem_region, 9953 dev_info.port_hw_config[params->port].xgbt_phy_cfg)) & 9954 PORT_HW_CFG_RJ45_PAIR_SWAP_MASK; 9955 9956 if (pair_swap == 0) 9957 return 0; 9958 9959 /* Only the second argument is used for this command */ 9960 data[1] = (u16)pair_swap; 9961 9962 status = bnx2x_84833_cmd_hdlr(phy, params, 9963 PHY84833_CMD_SET_PAIR_SWAP, data, PHY84833_CMDHDLR_MAX_ARGS); 9964 if (status == 0) 9965 DP(NETIF_MSG_LINK, "Pairswap OK, val=0x%x\n", data[1]); 9966 9967 return status; 9968 } 9969 9970 static u8 bnx2x_84833_get_reset_gpios(struct bnx2x *bp, 9971 u32 shmem_base_path[], 9972 u32 chip_id) 9973 { 9974 u32 reset_pin[2]; 9975 u32 idx; 9976 u8 reset_gpios; 9977 if (CHIP_IS_E3(bp)) { 9978 /* Assume that these will be GPIOs, not EPIOs. */ 9979 for (idx = 0; idx < 2; idx++) { 9980 /* Map config param to register bit. */ 9981 reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] + 9982 offsetof(struct shmem_region, 9983 dev_info.port_hw_config[0].e3_cmn_pin_cfg)); 9984 reset_pin[idx] = (reset_pin[idx] & 9985 PORT_HW_CFG_E3_PHY_RESET_MASK) >> 9986 PORT_HW_CFG_E3_PHY_RESET_SHIFT; 9987 reset_pin[idx] -= PIN_CFG_GPIO0_P0; 9988 reset_pin[idx] = (1 << reset_pin[idx]); 9989 } 9990 reset_gpios = (u8)(reset_pin[0] | reset_pin[1]); 9991 } else { 9992 /* E2, look from diff place of shmem. */ 9993 for (idx = 0; idx < 2; idx++) { 9994 reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] + 9995 offsetof(struct shmem_region, 9996 dev_info.port_hw_config[0].default_cfg)); 9997 reset_pin[idx] &= PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK; 9998 reset_pin[idx] -= PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0; 9999 reset_pin[idx] >>= PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT; 10000 reset_pin[idx] = (1 << reset_pin[idx]); 10001 } 10002 reset_gpios = (u8)(reset_pin[0] | reset_pin[1]); 10003 } 10004 10005 return reset_gpios; 10006 } 10007 10008 static int bnx2x_84833_hw_reset_phy(struct bnx2x_phy *phy, 10009 struct link_params *params) 10010 { 10011 struct bnx2x *bp = params->bp; 10012 u8 reset_gpios; 10013 u32 other_shmem_base_addr = REG_RD(bp, params->shmem2_base + 10014 offsetof(struct shmem2_region, 10015 other_shmem_base_addr)); 10016 10017 u32 shmem_base_path[2]; 10018 10019 /* Work around for 84833 LED failure inside RESET status */ 10020 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, 10021 MDIO_AN_REG_8481_LEGACY_MII_CTRL, 10022 MDIO_AN_REG_8481_MII_CTRL_FORCE_1G); 10023 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, 10024 MDIO_AN_REG_8481_1G_100T_EXT_CTRL, 10025 MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF); 10026 10027 shmem_base_path[0] = params->shmem_base; 10028 shmem_base_path[1] = other_shmem_base_addr; 10029 10030 reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path, 10031 params->chip_id); 10032 10033 bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW); 10034 udelay(10); 10035 DP(NETIF_MSG_LINK, "84833 hw reset on pin values 0x%x\n", 10036 reset_gpios); 10037 10038 return 0; 10039 } 10040 10041 static int bnx2x_8483x_disable_eee(struct bnx2x_phy *phy, 10042 struct link_params *params, 10043 struct link_vars *vars) 10044 { 10045 int rc; 10046 struct bnx2x *bp = params->bp; 10047 u16 cmd_args = 0; 10048 10049 DP(NETIF_MSG_LINK, "Don't Advertise 10GBase-T EEE\n"); 10050 10051 /* Prevent Phy from working in EEE and advertising it */ 10052 rc = bnx2x_84833_cmd_hdlr(phy, params, 10053 PHY84833_CMD_SET_EEE_MODE, &cmd_args, 1); 10054 if (rc) { 10055 DP(NETIF_MSG_LINK, "EEE disable failed.\n"); 10056 return rc; 10057 } 10058 10059 return bnx2x_eee_disable(phy, params, vars); 10060 } 10061 10062 static int bnx2x_8483x_enable_eee(struct bnx2x_phy *phy, 10063 struct link_params *params, 10064 struct link_vars *vars) 10065 { 10066 int rc; 10067 struct bnx2x *bp = params->bp; 10068 u16 cmd_args = 1; 10069 10070 rc = bnx2x_84833_cmd_hdlr(phy, params, 10071 PHY84833_CMD_SET_EEE_MODE, &cmd_args, 1); 10072 if (rc) { 10073 DP(NETIF_MSG_LINK, "EEE enable failed.\n"); 10074 return rc; 10075 } 10076 10077 return bnx2x_eee_advertise(phy, params, vars, SHMEM_EEE_10G_ADV); 10078 } 10079 10080 #define PHY84833_CONSTANT_LATENCY 1193 10081 static int bnx2x_848x3_config_init(struct bnx2x_phy *phy, 10082 struct link_params *params, 10083 struct link_vars *vars) 10084 { 10085 struct bnx2x *bp = params->bp; 10086 u8 port, initialize = 1; 10087 u16 val; 10088 u32 actual_phy_selection; 10089 u16 cmd_args[PHY84833_CMDHDLR_MAX_ARGS]; 10090 int rc = 0; 10091 10092 usleep_range(1000, 2000); 10093 10094 if (!(CHIP_IS_E1x(bp))) 10095 port = BP_PATH(bp); 10096 else 10097 port = params->port; 10098 10099 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) { 10100 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3, 10101 MISC_REGISTERS_GPIO_OUTPUT_HIGH, 10102 port); 10103 } else { 10104 /* MDIO reset */ 10105 bnx2x_cl45_write(bp, phy, 10106 MDIO_PMA_DEVAD, 10107 MDIO_PMA_REG_CTRL, 0x8000); 10108 } 10109 10110 bnx2x_wait_reset_complete(bp, phy, params); 10111 10112 /* Wait for GPHY to come out of reset */ 10113 msleep(50); 10114 if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) && 10115 (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) { 10116 /* BCM84823 requires that XGXS links up first @ 10G for normal 10117 * behavior. 10118 */ 10119 u16 temp; 10120 temp = vars->line_speed; 10121 vars->line_speed = SPEED_10000; 10122 bnx2x_set_autoneg(¶ms->phy[INT_PHY], params, vars, 0); 10123 bnx2x_program_serdes(¶ms->phy[INT_PHY], params, vars); 10124 vars->line_speed = temp; 10125 } 10126 10127 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 10128 MDIO_CTL_REG_84823_MEDIA, &val); 10129 val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK | 10130 MDIO_CTL_REG_84823_MEDIA_LINE_MASK | 10131 MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN | 10132 MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK | 10133 MDIO_CTL_REG_84823_MEDIA_FIBER_1G); 10134 10135 if (CHIP_IS_E3(bp)) { 10136 val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK | 10137 MDIO_CTL_REG_84823_MEDIA_LINE_MASK); 10138 } else { 10139 val |= (MDIO_CTL_REG_84823_CTRL_MAC_XFI | 10140 MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L); 10141 } 10142 10143 actual_phy_selection = bnx2x_phy_selection(params); 10144 10145 switch (actual_phy_selection) { 10146 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT: 10147 /* Do nothing. Essentially this is like the priority copper */ 10148 break; 10149 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY: 10150 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER; 10151 break; 10152 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY: 10153 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER; 10154 break; 10155 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY: 10156 /* Do nothing here. The first PHY won't be initialized at all */ 10157 break; 10158 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY: 10159 val |= MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN; 10160 initialize = 0; 10161 break; 10162 } 10163 if (params->phy[EXT_PHY2].req_line_speed == SPEED_1000) 10164 val |= MDIO_CTL_REG_84823_MEDIA_FIBER_1G; 10165 10166 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, 10167 MDIO_CTL_REG_84823_MEDIA, val); 10168 DP(NETIF_MSG_LINK, "Multi_phy config = 0x%x, Media control = 0x%x\n", 10169 params->multi_phy_config, val); 10170 10171 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) || 10172 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) { 10173 bnx2x_84833_pair_swap_cfg(phy, params, vars); 10174 10175 /* Keep AutogrEEEn disabled. */ 10176 cmd_args[0] = 0x0; 10177 cmd_args[1] = 0x0; 10178 cmd_args[2] = PHY84833_CONSTANT_LATENCY + 1; 10179 cmd_args[3] = PHY84833_CONSTANT_LATENCY; 10180 rc = bnx2x_84833_cmd_hdlr(phy, params, 10181 PHY84833_CMD_SET_EEE_MODE, cmd_args, 10182 PHY84833_CMDHDLR_MAX_ARGS); 10183 if (rc) 10184 DP(NETIF_MSG_LINK, "Cfg AutogrEEEn failed.\n"); 10185 } 10186 if (initialize) 10187 rc = bnx2x_848xx_cmn_config_init(phy, params, vars); 10188 else 10189 bnx2x_save_848xx_spirom_version(phy, bp, params->port); 10190 /* 84833 PHY has a better feature and doesn't need to support this. */ 10191 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) { 10192 u32 cms_enable = REG_RD(bp, params->shmem_base + 10193 offsetof(struct shmem_region, 10194 dev_info.port_hw_config[params->port].default_cfg)) & 10195 PORT_HW_CFG_ENABLE_CMS_MASK; 10196 10197 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 10198 MDIO_CTL_REG_84823_USER_CTRL_REG, &val); 10199 if (cms_enable) 10200 val |= MDIO_CTL_REG_84823_USER_CTRL_CMS; 10201 else 10202 val &= ~MDIO_CTL_REG_84823_USER_CTRL_CMS; 10203 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, 10204 MDIO_CTL_REG_84823_USER_CTRL_REG, val); 10205 } 10206 10207 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 10208 MDIO_84833_TOP_CFG_FW_REV, &val); 10209 10210 /* Configure EEE support */ 10211 if ((val >= MDIO_84833_TOP_CFG_FW_EEE) && 10212 (val != MDIO_84833_TOP_CFG_FW_NO_EEE) && 10213 bnx2x_eee_has_cap(params)) { 10214 rc = bnx2x_eee_initial_config(params, vars, SHMEM_EEE_10G_ADV); 10215 if (rc) { 10216 DP(NETIF_MSG_LINK, "Failed to configure EEE timers\n"); 10217 bnx2x_8483x_disable_eee(phy, params, vars); 10218 return rc; 10219 } 10220 10221 if ((phy->req_duplex == DUPLEX_FULL) && 10222 (params->eee_mode & EEE_MODE_ADV_LPI) && 10223 (bnx2x_eee_calc_timer(params) || 10224 !(params->eee_mode & EEE_MODE_ENABLE_LPI))) 10225 rc = bnx2x_8483x_enable_eee(phy, params, vars); 10226 else 10227 rc = bnx2x_8483x_disable_eee(phy, params, vars); 10228 if (rc) { 10229 DP(NETIF_MSG_LINK, "Failed to set EEE advertisement\n"); 10230 return rc; 10231 } 10232 } else { 10233 vars->eee_status &= ~SHMEM_EEE_SUPPORTED_MASK; 10234 } 10235 10236 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) || 10237 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) { 10238 /* Bring PHY out of super isolate mode as the final step. */ 10239 bnx2x_cl45_read_and_write(bp, phy, 10240 MDIO_CTL_DEVAD, 10241 MDIO_84833_TOP_CFG_XGPHY_STRAP1, 10242 (u16)~MDIO_84833_SUPER_ISOLATE); 10243 } 10244 return rc; 10245 } 10246 10247 static u8 bnx2x_848xx_read_status(struct bnx2x_phy *phy, 10248 struct link_params *params, 10249 struct link_vars *vars) 10250 { 10251 struct bnx2x *bp = params->bp; 10252 u16 val, val1, val2; 10253 u8 link_up = 0; 10254 10255 10256 /* Check 10G-BaseT link status */ 10257 /* Check PMD signal ok */ 10258 bnx2x_cl45_read(bp, phy, 10259 MDIO_AN_DEVAD, 0xFFFA, &val1); 10260 bnx2x_cl45_read(bp, phy, 10261 MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_PMD_SIGNAL, 10262 &val2); 10263 DP(NETIF_MSG_LINK, "BCM848xx: PMD_SIGNAL 1.a811 = 0x%x\n", val2); 10264 10265 /* Check link 10G */ 10266 if (val2 & (1<<11)) { 10267 vars->line_speed = SPEED_10000; 10268 vars->duplex = DUPLEX_FULL; 10269 link_up = 1; 10270 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars); 10271 } else { /* Check Legacy speed link */ 10272 u16 legacy_status, legacy_speed; 10273 10274 /* Enable expansion register 0x42 (Operation mode status) */ 10275 bnx2x_cl45_write(bp, phy, 10276 MDIO_AN_DEVAD, 10277 MDIO_AN_REG_8481_EXPANSION_REG_ACCESS, 0xf42); 10278 10279 /* Get legacy speed operation status */ 10280 bnx2x_cl45_read(bp, phy, 10281 MDIO_AN_DEVAD, 10282 MDIO_AN_REG_8481_EXPANSION_REG_RD_RW, 10283 &legacy_status); 10284 10285 DP(NETIF_MSG_LINK, "Legacy speed status = 0x%x\n", 10286 legacy_status); 10287 link_up = ((legacy_status & (1<<11)) == (1<<11)); 10288 legacy_speed = (legacy_status & (3<<9)); 10289 if (legacy_speed == (0<<9)) 10290 vars->line_speed = SPEED_10; 10291 else if (legacy_speed == (1<<9)) 10292 vars->line_speed = SPEED_100; 10293 else if (legacy_speed == (2<<9)) 10294 vars->line_speed = SPEED_1000; 10295 else { /* Should not happen: Treat as link down */ 10296 vars->line_speed = 0; 10297 link_up = 0; 10298 } 10299 10300 if (link_up) { 10301 if (legacy_status & (1<<8)) 10302 vars->duplex = DUPLEX_FULL; 10303 else 10304 vars->duplex = DUPLEX_HALF; 10305 10306 DP(NETIF_MSG_LINK, 10307 "Link is up in %dMbps, is_duplex_full= %d\n", 10308 vars->line_speed, 10309 (vars->duplex == DUPLEX_FULL)); 10310 /* Check legacy speed AN resolution */ 10311 bnx2x_cl45_read(bp, phy, 10312 MDIO_AN_DEVAD, 10313 MDIO_AN_REG_8481_LEGACY_MII_STATUS, 10314 &val); 10315 if (val & (1<<5)) 10316 vars->link_status |= 10317 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; 10318 bnx2x_cl45_read(bp, phy, 10319 MDIO_AN_DEVAD, 10320 MDIO_AN_REG_8481_LEGACY_AN_EXPANSION, 10321 &val); 10322 if ((val & (1<<0)) == 0) 10323 vars->link_status |= 10324 LINK_STATUS_PARALLEL_DETECTION_USED; 10325 } 10326 } 10327 if (link_up) { 10328 DP(NETIF_MSG_LINK, "BCM848x3: link speed is %d\n", 10329 vars->line_speed); 10330 bnx2x_ext_phy_resolve_fc(phy, params, vars); 10331 10332 /* Read LP advertised speeds */ 10333 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, 10334 MDIO_AN_REG_CL37_FC_LP, &val); 10335 if (val & (1<<5)) 10336 vars->link_status |= 10337 LINK_STATUS_LINK_PARTNER_10THD_CAPABLE; 10338 if (val & (1<<6)) 10339 vars->link_status |= 10340 LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE; 10341 if (val & (1<<7)) 10342 vars->link_status |= 10343 LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE; 10344 if (val & (1<<8)) 10345 vars->link_status |= 10346 LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE; 10347 if (val & (1<<9)) 10348 vars->link_status |= 10349 LINK_STATUS_LINK_PARTNER_100T4_CAPABLE; 10350 10351 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, 10352 MDIO_AN_REG_1000T_STATUS, &val); 10353 10354 if (val & (1<<10)) 10355 vars->link_status |= 10356 LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE; 10357 if (val & (1<<11)) 10358 vars->link_status |= 10359 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; 10360 10361 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, 10362 MDIO_AN_REG_MASTER_STATUS, &val); 10363 10364 if (val & (1<<11)) 10365 vars->link_status |= 10366 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; 10367 10368 /* Determine if EEE was negotiated */ 10369 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) || 10370 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) 10371 bnx2x_eee_an_resolve(phy, params, vars); 10372 } 10373 10374 return link_up; 10375 } 10376 10377 static int bnx2x_848xx_format_ver(u32 raw_ver, u8 *str, u16 *len) 10378 { 10379 int status = 0; 10380 u32 spirom_ver; 10381 spirom_ver = ((raw_ver & 0xF80) >> 7) << 16 | (raw_ver & 0x7F); 10382 status = bnx2x_format_ver(spirom_ver, str, len); 10383 return status; 10384 } 10385 10386 static void bnx2x_8481_hw_reset(struct bnx2x_phy *phy, 10387 struct link_params *params) 10388 { 10389 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1, 10390 MISC_REGISTERS_GPIO_OUTPUT_LOW, 0); 10391 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1, 10392 MISC_REGISTERS_GPIO_OUTPUT_LOW, 1); 10393 } 10394 10395 static void bnx2x_8481_link_reset(struct bnx2x_phy *phy, 10396 struct link_params *params) 10397 { 10398 bnx2x_cl45_write(params->bp, phy, 10399 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000); 10400 bnx2x_cl45_write(params->bp, phy, 10401 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1); 10402 } 10403 10404 static void bnx2x_848x3_link_reset(struct bnx2x_phy *phy, 10405 struct link_params *params) 10406 { 10407 struct bnx2x *bp = params->bp; 10408 u8 port; 10409 u16 val16; 10410 10411 if (!(CHIP_IS_E1x(bp))) 10412 port = BP_PATH(bp); 10413 else 10414 port = params->port; 10415 10416 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) { 10417 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3, 10418 MISC_REGISTERS_GPIO_OUTPUT_LOW, 10419 port); 10420 } else { 10421 bnx2x_cl45_read(bp, phy, 10422 MDIO_CTL_DEVAD, 10423 MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val16); 10424 val16 |= MDIO_84833_SUPER_ISOLATE; 10425 bnx2x_cl45_write(bp, phy, 10426 MDIO_CTL_DEVAD, 10427 MDIO_84833_TOP_CFG_XGPHY_STRAP1, val16); 10428 } 10429 } 10430 10431 static void bnx2x_848xx_set_link_led(struct bnx2x_phy *phy, 10432 struct link_params *params, u8 mode) 10433 { 10434 struct bnx2x *bp = params->bp; 10435 u16 val; 10436 u8 port; 10437 10438 if (!(CHIP_IS_E1x(bp))) 10439 port = BP_PATH(bp); 10440 else 10441 port = params->port; 10442 10443 switch (mode) { 10444 case LED_MODE_OFF: 10445 10446 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OFF\n", port); 10447 10448 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) == 10449 SHARED_HW_CFG_LED_EXTPHY1) { 10450 10451 /* Set LED masks */ 10452 bnx2x_cl45_write(bp, phy, 10453 MDIO_PMA_DEVAD, 10454 MDIO_PMA_REG_8481_LED1_MASK, 10455 0x0); 10456 10457 bnx2x_cl45_write(bp, phy, 10458 MDIO_PMA_DEVAD, 10459 MDIO_PMA_REG_8481_LED2_MASK, 10460 0x0); 10461 10462 bnx2x_cl45_write(bp, phy, 10463 MDIO_PMA_DEVAD, 10464 MDIO_PMA_REG_8481_LED3_MASK, 10465 0x0); 10466 10467 bnx2x_cl45_write(bp, phy, 10468 MDIO_PMA_DEVAD, 10469 MDIO_PMA_REG_8481_LED5_MASK, 10470 0x0); 10471 10472 } else { 10473 bnx2x_cl45_write(bp, phy, 10474 MDIO_PMA_DEVAD, 10475 MDIO_PMA_REG_8481_LED1_MASK, 10476 0x0); 10477 } 10478 break; 10479 case LED_MODE_FRONT_PANEL_OFF: 10480 10481 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE FRONT PANEL OFF\n", 10482 port); 10483 10484 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) == 10485 SHARED_HW_CFG_LED_EXTPHY1) { 10486 10487 /* Set LED masks */ 10488 bnx2x_cl45_write(bp, phy, 10489 MDIO_PMA_DEVAD, 10490 MDIO_PMA_REG_8481_LED1_MASK, 10491 0x0); 10492 10493 bnx2x_cl45_write(bp, phy, 10494 MDIO_PMA_DEVAD, 10495 MDIO_PMA_REG_8481_LED2_MASK, 10496 0x0); 10497 10498 bnx2x_cl45_write(bp, phy, 10499 MDIO_PMA_DEVAD, 10500 MDIO_PMA_REG_8481_LED3_MASK, 10501 0x0); 10502 10503 bnx2x_cl45_write(bp, phy, 10504 MDIO_PMA_DEVAD, 10505 MDIO_PMA_REG_8481_LED5_MASK, 10506 0x20); 10507 10508 } else { 10509 bnx2x_cl45_write(bp, phy, 10510 MDIO_PMA_DEVAD, 10511 MDIO_PMA_REG_8481_LED1_MASK, 10512 0x0); 10513 if (phy->type == 10514 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) { 10515 /* Disable MI_INT interrupt before setting LED4 10516 * source to constant off. 10517 */ 10518 if (REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + 10519 params->port*4) & 10520 NIG_MASK_MI_INT) { 10521 params->link_flags |= 10522 LINK_FLAGS_INT_DISABLED; 10523 10524 bnx2x_bits_dis( 10525 bp, 10526 NIG_REG_MASK_INTERRUPT_PORT0 + 10527 params->port*4, 10528 NIG_MASK_MI_INT); 10529 } 10530 bnx2x_cl45_write(bp, phy, 10531 MDIO_PMA_DEVAD, 10532 MDIO_PMA_REG_8481_SIGNAL_MASK, 10533 0x0); 10534 } 10535 } 10536 break; 10537 case LED_MODE_ON: 10538 10539 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE ON\n", port); 10540 10541 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) == 10542 SHARED_HW_CFG_LED_EXTPHY1) { 10543 /* Set control reg */ 10544 bnx2x_cl45_read(bp, phy, 10545 MDIO_PMA_DEVAD, 10546 MDIO_PMA_REG_8481_LINK_SIGNAL, 10547 &val); 10548 val &= 0x8000; 10549 val |= 0x2492; 10550 10551 bnx2x_cl45_write(bp, phy, 10552 MDIO_PMA_DEVAD, 10553 MDIO_PMA_REG_8481_LINK_SIGNAL, 10554 val); 10555 10556 /* Set LED masks */ 10557 bnx2x_cl45_write(bp, phy, 10558 MDIO_PMA_DEVAD, 10559 MDIO_PMA_REG_8481_LED1_MASK, 10560 0x0); 10561 10562 bnx2x_cl45_write(bp, phy, 10563 MDIO_PMA_DEVAD, 10564 MDIO_PMA_REG_8481_LED2_MASK, 10565 0x20); 10566 10567 bnx2x_cl45_write(bp, phy, 10568 MDIO_PMA_DEVAD, 10569 MDIO_PMA_REG_8481_LED3_MASK, 10570 0x20); 10571 10572 bnx2x_cl45_write(bp, phy, 10573 MDIO_PMA_DEVAD, 10574 MDIO_PMA_REG_8481_LED5_MASK, 10575 0x0); 10576 } else { 10577 bnx2x_cl45_write(bp, phy, 10578 MDIO_PMA_DEVAD, 10579 MDIO_PMA_REG_8481_LED1_MASK, 10580 0x20); 10581 if (phy->type == 10582 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) { 10583 /* Disable MI_INT interrupt before setting LED4 10584 * source to constant on. 10585 */ 10586 if (REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + 10587 params->port*4) & 10588 NIG_MASK_MI_INT) { 10589 params->link_flags |= 10590 LINK_FLAGS_INT_DISABLED; 10591 10592 bnx2x_bits_dis( 10593 bp, 10594 NIG_REG_MASK_INTERRUPT_PORT0 + 10595 params->port*4, 10596 NIG_MASK_MI_INT); 10597 } 10598 bnx2x_cl45_write(bp, phy, 10599 MDIO_PMA_DEVAD, 10600 MDIO_PMA_REG_8481_SIGNAL_MASK, 10601 0x20); 10602 } 10603 } 10604 break; 10605 10606 case LED_MODE_OPER: 10607 10608 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OPER\n", port); 10609 10610 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) == 10611 SHARED_HW_CFG_LED_EXTPHY1) { 10612 10613 /* Set control reg */ 10614 bnx2x_cl45_read(bp, phy, 10615 MDIO_PMA_DEVAD, 10616 MDIO_PMA_REG_8481_LINK_SIGNAL, 10617 &val); 10618 10619 if (!((val & 10620 MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK) 10621 >> MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT)) { 10622 DP(NETIF_MSG_LINK, "Setting LINK_SIGNAL\n"); 10623 bnx2x_cl45_write(bp, phy, 10624 MDIO_PMA_DEVAD, 10625 MDIO_PMA_REG_8481_LINK_SIGNAL, 10626 0xa492); 10627 } 10628 10629 /* Set LED masks */ 10630 bnx2x_cl45_write(bp, phy, 10631 MDIO_PMA_DEVAD, 10632 MDIO_PMA_REG_8481_LED1_MASK, 10633 0x10); 10634 10635 bnx2x_cl45_write(bp, phy, 10636 MDIO_PMA_DEVAD, 10637 MDIO_PMA_REG_8481_LED2_MASK, 10638 0x80); 10639 10640 bnx2x_cl45_write(bp, phy, 10641 MDIO_PMA_DEVAD, 10642 MDIO_PMA_REG_8481_LED3_MASK, 10643 0x98); 10644 10645 bnx2x_cl45_write(bp, phy, 10646 MDIO_PMA_DEVAD, 10647 MDIO_PMA_REG_8481_LED5_MASK, 10648 0x40); 10649 10650 } else { 10651 /* EXTPHY2 LED mode indicate that the 100M/1G/10G LED 10652 * sources are all wired through LED1, rather than only 10653 * 10G in other modes. 10654 */ 10655 val = ((params->hw_led_mode << 10656 SHARED_HW_CFG_LED_MODE_SHIFT) == 10657 SHARED_HW_CFG_LED_EXTPHY2) ? 0x98 : 0x80; 10658 10659 bnx2x_cl45_write(bp, phy, 10660 MDIO_PMA_DEVAD, 10661 MDIO_PMA_REG_8481_LED1_MASK, 10662 val); 10663 10664 /* Tell LED3 to blink on source */ 10665 bnx2x_cl45_read(bp, phy, 10666 MDIO_PMA_DEVAD, 10667 MDIO_PMA_REG_8481_LINK_SIGNAL, 10668 &val); 10669 val &= ~(7<<6); 10670 val |= (1<<6); /* A83B[8:6]= 1 */ 10671 bnx2x_cl45_write(bp, phy, 10672 MDIO_PMA_DEVAD, 10673 MDIO_PMA_REG_8481_LINK_SIGNAL, 10674 val); 10675 if (phy->type == 10676 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) { 10677 /* Restore LED4 source to external link, 10678 * and re-enable interrupts. 10679 */ 10680 bnx2x_cl45_write(bp, phy, 10681 MDIO_PMA_DEVAD, 10682 MDIO_PMA_REG_8481_SIGNAL_MASK, 10683 0x40); 10684 if (params->link_flags & 10685 LINK_FLAGS_INT_DISABLED) { 10686 bnx2x_link_int_enable(params); 10687 params->link_flags &= 10688 ~LINK_FLAGS_INT_DISABLED; 10689 } 10690 } 10691 } 10692 break; 10693 } 10694 10695 /* This is a workaround for E3+84833 until autoneg 10696 * restart is fixed in f/w 10697 */ 10698 if (CHIP_IS_E3(bp)) { 10699 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 10700 MDIO_WC_REG_GP2_STATUS_GP_2_1, &val); 10701 } 10702 } 10703 10704 /******************************************************************/ 10705 /* 54618SE PHY SECTION */ 10706 /******************************************************************/ 10707 static void bnx2x_54618se_specific_func(struct bnx2x_phy *phy, 10708 struct link_params *params, 10709 u32 action) 10710 { 10711 struct bnx2x *bp = params->bp; 10712 u16 temp; 10713 switch (action) { 10714 case PHY_INIT: 10715 /* Configure LED4: set to INTR (0x6). */ 10716 /* Accessing shadow register 0xe. */ 10717 bnx2x_cl22_write(bp, phy, 10718 MDIO_REG_GPHY_SHADOW, 10719 MDIO_REG_GPHY_SHADOW_LED_SEL2); 10720 bnx2x_cl22_read(bp, phy, 10721 MDIO_REG_GPHY_SHADOW, 10722 &temp); 10723 temp &= ~(0xf << 4); 10724 temp |= (0x6 << 4); 10725 bnx2x_cl22_write(bp, phy, 10726 MDIO_REG_GPHY_SHADOW, 10727 MDIO_REG_GPHY_SHADOW_WR_ENA | temp); 10728 /* Configure INTR based on link status change. */ 10729 bnx2x_cl22_write(bp, phy, 10730 MDIO_REG_INTR_MASK, 10731 ~MDIO_REG_INTR_MASK_LINK_STATUS); 10732 break; 10733 } 10734 } 10735 10736 static int bnx2x_54618se_config_init(struct bnx2x_phy *phy, 10737 struct link_params *params, 10738 struct link_vars *vars) 10739 { 10740 struct bnx2x *bp = params->bp; 10741 u8 port; 10742 u16 autoneg_val, an_1000_val, an_10_100_val, fc_val, temp; 10743 u32 cfg_pin; 10744 10745 DP(NETIF_MSG_LINK, "54618SE cfg init\n"); 10746 usleep_range(1000, 2000); 10747 10748 /* This works with E3 only, no need to check the chip 10749 * before determining the port. 10750 */ 10751 port = params->port; 10752 10753 cfg_pin = (REG_RD(bp, params->shmem_base + 10754 offsetof(struct shmem_region, 10755 dev_info.port_hw_config[port].e3_cmn_pin_cfg)) & 10756 PORT_HW_CFG_E3_PHY_RESET_MASK) >> 10757 PORT_HW_CFG_E3_PHY_RESET_SHIFT; 10758 10759 /* Drive pin high to bring the GPHY out of reset. */ 10760 bnx2x_set_cfg_pin(bp, cfg_pin, 1); 10761 10762 /* wait for GPHY to reset */ 10763 msleep(50); 10764 10765 /* reset phy */ 10766 bnx2x_cl22_write(bp, phy, 10767 MDIO_PMA_REG_CTRL, 0x8000); 10768 bnx2x_wait_reset_complete(bp, phy, params); 10769 10770 /* Wait for GPHY to reset */ 10771 msleep(50); 10772 10773 10774 bnx2x_54618se_specific_func(phy, params, PHY_INIT); 10775 /* Flip the signal detect polarity (set 0x1c.0x1e[8]). */ 10776 bnx2x_cl22_write(bp, phy, 10777 MDIO_REG_GPHY_SHADOW, 10778 MDIO_REG_GPHY_SHADOW_AUTO_DET_MED); 10779 bnx2x_cl22_read(bp, phy, 10780 MDIO_REG_GPHY_SHADOW, 10781 &temp); 10782 temp |= MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD; 10783 bnx2x_cl22_write(bp, phy, 10784 MDIO_REG_GPHY_SHADOW, 10785 MDIO_REG_GPHY_SHADOW_WR_ENA | temp); 10786 10787 /* Set up fc */ 10788 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */ 10789 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); 10790 fc_val = 0; 10791 if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) == 10792 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) 10793 fc_val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC; 10794 10795 if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) == 10796 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) 10797 fc_val |= MDIO_AN_REG_ADV_PAUSE_PAUSE; 10798 10799 /* Read all advertisement */ 10800 bnx2x_cl22_read(bp, phy, 10801 0x09, 10802 &an_1000_val); 10803 10804 bnx2x_cl22_read(bp, phy, 10805 0x04, 10806 &an_10_100_val); 10807 10808 bnx2x_cl22_read(bp, phy, 10809 MDIO_PMA_REG_CTRL, 10810 &autoneg_val); 10811 10812 /* Disable forced speed */ 10813 autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13)); 10814 an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8) | (1<<10) | 10815 (1<<11)); 10816 10817 if (((phy->req_line_speed == SPEED_AUTO_NEG) && 10818 (phy->speed_cap_mask & 10819 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) || 10820 (phy->req_line_speed == SPEED_1000)) { 10821 an_1000_val |= (1<<8); 10822 autoneg_val |= (1<<9 | 1<<12); 10823 if (phy->req_duplex == DUPLEX_FULL) 10824 an_1000_val |= (1<<9); 10825 DP(NETIF_MSG_LINK, "Advertising 1G\n"); 10826 } else 10827 an_1000_val &= ~((1<<8) | (1<<9)); 10828 10829 bnx2x_cl22_write(bp, phy, 10830 0x09, 10831 an_1000_val); 10832 bnx2x_cl22_read(bp, phy, 10833 0x09, 10834 &an_1000_val); 10835 10836 /* Advertise 10/100 link speed */ 10837 if (phy->req_line_speed == SPEED_AUTO_NEG) { 10838 if (phy->speed_cap_mask & 10839 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF) { 10840 an_10_100_val |= (1<<5); 10841 autoneg_val |= (1<<9 | 1<<12); 10842 DP(NETIF_MSG_LINK, "Advertising 10M-HD\n"); 10843 } 10844 if (phy->speed_cap_mask & 10845 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) { 10846 an_10_100_val |= (1<<6); 10847 autoneg_val |= (1<<9 | 1<<12); 10848 DP(NETIF_MSG_LINK, "Advertising 10M-FD\n"); 10849 } 10850 if (phy->speed_cap_mask & 10851 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF) { 10852 an_10_100_val |= (1<<7); 10853 autoneg_val |= (1<<9 | 1<<12); 10854 DP(NETIF_MSG_LINK, "Advertising 100M-HD\n"); 10855 } 10856 if (phy->speed_cap_mask & 10857 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL) { 10858 an_10_100_val |= (1<<8); 10859 autoneg_val |= (1<<9 | 1<<12); 10860 DP(NETIF_MSG_LINK, "Advertising 100M-FD\n"); 10861 } 10862 } 10863 10864 /* Only 10/100 are allowed to work in FORCE mode */ 10865 if (phy->req_line_speed == SPEED_100) { 10866 autoneg_val |= (1<<13); 10867 /* Enabled AUTO-MDIX when autoneg is disabled */ 10868 bnx2x_cl22_write(bp, phy, 10869 0x18, 10870 (1<<15 | 1<<9 | 7<<0)); 10871 DP(NETIF_MSG_LINK, "Setting 100M force\n"); 10872 } 10873 if (phy->req_line_speed == SPEED_10) { 10874 /* Enabled AUTO-MDIX when autoneg is disabled */ 10875 bnx2x_cl22_write(bp, phy, 10876 0x18, 10877 (1<<15 | 1<<9 | 7<<0)); 10878 DP(NETIF_MSG_LINK, "Setting 10M force\n"); 10879 } 10880 10881 if ((phy->flags & FLAGS_EEE) && bnx2x_eee_has_cap(params)) { 10882 int rc; 10883 10884 bnx2x_cl22_write(bp, phy, MDIO_REG_GPHY_EXP_ACCESS, 10885 MDIO_REG_GPHY_EXP_ACCESS_TOP | 10886 MDIO_REG_GPHY_EXP_TOP_2K_BUF); 10887 bnx2x_cl22_read(bp, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, &temp); 10888 temp &= 0xfffe; 10889 bnx2x_cl22_write(bp, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, temp); 10890 10891 rc = bnx2x_eee_initial_config(params, vars, SHMEM_EEE_1G_ADV); 10892 if (rc) { 10893 DP(NETIF_MSG_LINK, "Failed to configure EEE timers\n"); 10894 bnx2x_eee_disable(phy, params, vars); 10895 } else if ((params->eee_mode & EEE_MODE_ADV_LPI) && 10896 (phy->req_duplex == DUPLEX_FULL) && 10897 (bnx2x_eee_calc_timer(params) || 10898 !(params->eee_mode & EEE_MODE_ENABLE_LPI))) { 10899 /* Need to advertise EEE only when requested, 10900 * and either no LPI assertion was requested, 10901 * or it was requested and a valid timer was set. 10902 * Also notice full duplex is required for EEE. 10903 */ 10904 bnx2x_eee_advertise(phy, params, vars, 10905 SHMEM_EEE_1G_ADV); 10906 } else { 10907 DP(NETIF_MSG_LINK, "Don't Advertise 1GBase-T EEE\n"); 10908 bnx2x_eee_disable(phy, params, vars); 10909 } 10910 } else { 10911 vars->eee_status &= ~SHMEM_EEE_1G_ADV << 10912 SHMEM_EEE_SUPPORTED_SHIFT; 10913 10914 if (phy->flags & FLAGS_EEE) { 10915 /* Handle legacy auto-grEEEn */ 10916 if (params->feature_config_flags & 10917 FEATURE_CONFIG_AUTOGREEEN_ENABLED) { 10918 temp = 6; 10919 DP(NETIF_MSG_LINK, "Enabling Auto-GrEEEn\n"); 10920 } else { 10921 temp = 0; 10922 DP(NETIF_MSG_LINK, "Don't Adv. EEE\n"); 10923 } 10924 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, 10925 MDIO_AN_REG_EEE_ADV, temp); 10926 } 10927 } 10928 10929 bnx2x_cl22_write(bp, phy, 10930 0x04, 10931 an_10_100_val | fc_val); 10932 10933 if (phy->req_duplex == DUPLEX_FULL) 10934 autoneg_val |= (1<<8); 10935 10936 bnx2x_cl22_write(bp, phy, 10937 MDIO_PMA_REG_CTRL, autoneg_val); 10938 10939 return 0; 10940 } 10941 10942 10943 static void bnx2x_5461x_set_link_led(struct bnx2x_phy *phy, 10944 struct link_params *params, u8 mode) 10945 { 10946 struct bnx2x *bp = params->bp; 10947 u16 temp; 10948 10949 bnx2x_cl22_write(bp, phy, 10950 MDIO_REG_GPHY_SHADOW, 10951 MDIO_REG_GPHY_SHADOW_LED_SEL1); 10952 bnx2x_cl22_read(bp, phy, 10953 MDIO_REG_GPHY_SHADOW, 10954 &temp); 10955 temp &= 0xff00; 10956 10957 DP(NETIF_MSG_LINK, "54618x set link led (mode=%x)\n", mode); 10958 switch (mode) { 10959 case LED_MODE_FRONT_PANEL_OFF: 10960 case LED_MODE_OFF: 10961 temp |= 0x00ee; 10962 break; 10963 case LED_MODE_OPER: 10964 temp |= 0x0001; 10965 break; 10966 case LED_MODE_ON: 10967 temp |= 0x00ff; 10968 break; 10969 default: 10970 break; 10971 } 10972 bnx2x_cl22_write(bp, phy, 10973 MDIO_REG_GPHY_SHADOW, 10974 MDIO_REG_GPHY_SHADOW_WR_ENA | temp); 10975 return; 10976 } 10977 10978 10979 static void bnx2x_54618se_link_reset(struct bnx2x_phy *phy, 10980 struct link_params *params) 10981 { 10982 struct bnx2x *bp = params->bp; 10983 u32 cfg_pin; 10984 u8 port; 10985 10986 /* In case of no EPIO routed to reset the GPHY, put it 10987 * in low power mode. 10988 */ 10989 bnx2x_cl22_write(bp, phy, MDIO_PMA_REG_CTRL, 0x800); 10990 /* This works with E3 only, no need to check the chip 10991 * before determining the port. 10992 */ 10993 port = params->port; 10994 cfg_pin = (REG_RD(bp, params->shmem_base + 10995 offsetof(struct shmem_region, 10996 dev_info.port_hw_config[port].e3_cmn_pin_cfg)) & 10997 PORT_HW_CFG_E3_PHY_RESET_MASK) >> 10998 PORT_HW_CFG_E3_PHY_RESET_SHIFT; 10999 11000 /* Drive pin low to put GPHY in reset. */ 11001 bnx2x_set_cfg_pin(bp, cfg_pin, 0); 11002 } 11003 11004 static u8 bnx2x_54618se_read_status(struct bnx2x_phy *phy, 11005 struct link_params *params, 11006 struct link_vars *vars) 11007 { 11008 struct bnx2x *bp = params->bp; 11009 u16 val; 11010 u8 link_up = 0; 11011 u16 legacy_status, legacy_speed; 11012 11013 /* Get speed operation status */ 11014 bnx2x_cl22_read(bp, phy, 11015 MDIO_REG_GPHY_AUX_STATUS, 11016 &legacy_status); 11017 DP(NETIF_MSG_LINK, "54618SE read_status: 0x%x\n", legacy_status); 11018 11019 /* Read status to clear the PHY interrupt. */ 11020 bnx2x_cl22_read(bp, phy, 11021 MDIO_REG_INTR_STATUS, 11022 &val); 11023 11024 link_up = ((legacy_status & (1<<2)) == (1<<2)); 11025 11026 if (link_up) { 11027 legacy_speed = (legacy_status & (7<<8)); 11028 if (legacy_speed == (7<<8)) { 11029 vars->line_speed = SPEED_1000; 11030 vars->duplex = DUPLEX_FULL; 11031 } else if (legacy_speed == (6<<8)) { 11032 vars->line_speed = SPEED_1000; 11033 vars->duplex = DUPLEX_HALF; 11034 } else if (legacy_speed == (5<<8)) { 11035 vars->line_speed = SPEED_100; 11036 vars->duplex = DUPLEX_FULL; 11037 } 11038 /* Omitting 100Base-T4 for now */ 11039 else if (legacy_speed == (3<<8)) { 11040 vars->line_speed = SPEED_100; 11041 vars->duplex = DUPLEX_HALF; 11042 } else if (legacy_speed == (2<<8)) { 11043 vars->line_speed = SPEED_10; 11044 vars->duplex = DUPLEX_FULL; 11045 } else if (legacy_speed == (1<<8)) { 11046 vars->line_speed = SPEED_10; 11047 vars->duplex = DUPLEX_HALF; 11048 } else /* Should not happen */ 11049 vars->line_speed = 0; 11050 11051 DP(NETIF_MSG_LINK, 11052 "Link is up in %dMbps, is_duplex_full= %d\n", 11053 vars->line_speed, 11054 (vars->duplex == DUPLEX_FULL)); 11055 11056 /* Check legacy speed AN resolution */ 11057 bnx2x_cl22_read(bp, phy, 11058 0x01, 11059 &val); 11060 if (val & (1<<5)) 11061 vars->link_status |= 11062 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; 11063 bnx2x_cl22_read(bp, phy, 11064 0x06, 11065 &val); 11066 if ((val & (1<<0)) == 0) 11067 vars->link_status |= 11068 LINK_STATUS_PARALLEL_DETECTION_USED; 11069 11070 DP(NETIF_MSG_LINK, "BCM54618SE: link speed is %d\n", 11071 vars->line_speed); 11072 11073 bnx2x_ext_phy_resolve_fc(phy, params, vars); 11074 11075 if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) { 11076 /* Report LP advertised speeds */ 11077 bnx2x_cl22_read(bp, phy, 0x5, &val); 11078 11079 if (val & (1<<5)) 11080 vars->link_status |= 11081 LINK_STATUS_LINK_PARTNER_10THD_CAPABLE; 11082 if (val & (1<<6)) 11083 vars->link_status |= 11084 LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE; 11085 if (val & (1<<7)) 11086 vars->link_status |= 11087 LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE; 11088 if (val & (1<<8)) 11089 vars->link_status |= 11090 LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE; 11091 if (val & (1<<9)) 11092 vars->link_status |= 11093 LINK_STATUS_LINK_PARTNER_100T4_CAPABLE; 11094 11095 bnx2x_cl22_read(bp, phy, 0xa, &val); 11096 if (val & (1<<10)) 11097 vars->link_status |= 11098 LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE; 11099 if (val & (1<<11)) 11100 vars->link_status |= 11101 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; 11102 11103 if ((phy->flags & FLAGS_EEE) && 11104 bnx2x_eee_has_cap(params)) 11105 bnx2x_eee_an_resolve(phy, params, vars); 11106 } 11107 } 11108 return link_up; 11109 } 11110 11111 static void bnx2x_54618se_config_loopback(struct bnx2x_phy *phy, 11112 struct link_params *params) 11113 { 11114 struct bnx2x *bp = params->bp; 11115 u16 val; 11116 u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0; 11117 11118 DP(NETIF_MSG_LINK, "2PMA/PMD ext_phy_loopback: 54618se\n"); 11119 11120 /* Enable master/slave manual mmode and set to master */ 11121 /* mii write 9 [bits set 11 12] */ 11122 bnx2x_cl22_write(bp, phy, 0x09, 3<<11); 11123 11124 /* forced 1G and disable autoneg */ 11125 /* set val [mii read 0] */ 11126 /* set val [expr $val & [bits clear 6 12 13]] */ 11127 /* set val [expr $val | [bits set 6 8]] */ 11128 /* mii write 0 $val */ 11129 bnx2x_cl22_read(bp, phy, 0x00, &val); 11130 val &= ~((1<<6) | (1<<12) | (1<<13)); 11131 val |= (1<<6) | (1<<8); 11132 bnx2x_cl22_write(bp, phy, 0x00, val); 11133 11134 /* Set external loopback and Tx using 6dB coding */ 11135 /* mii write 0x18 7 */ 11136 /* set val [mii read 0x18] */ 11137 /* mii write 0x18 [expr $val | [bits set 10 15]] */ 11138 bnx2x_cl22_write(bp, phy, 0x18, 7); 11139 bnx2x_cl22_read(bp, phy, 0x18, &val); 11140 bnx2x_cl22_write(bp, phy, 0x18, val | (1<<10) | (1<<15)); 11141 11142 /* This register opens the gate for the UMAC despite its name */ 11143 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1); 11144 11145 /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame 11146 * length used by the MAC receive logic to check frames. 11147 */ 11148 REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710); 11149 } 11150 11151 /******************************************************************/ 11152 /* SFX7101 PHY SECTION */ 11153 /******************************************************************/ 11154 static void bnx2x_7101_config_loopback(struct bnx2x_phy *phy, 11155 struct link_params *params) 11156 { 11157 struct bnx2x *bp = params->bp; 11158 /* SFX7101_XGXS_TEST1 */ 11159 bnx2x_cl45_write(bp, phy, 11160 MDIO_XS_DEVAD, MDIO_XS_SFX7101_XGXS_TEST1, 0x100); 11161 } 11162 11163 static int bnx2x_7101_config_init(struct bnx2x_phy *phy, 11164 struct link_params *params, 11165 struct link_vars *vars) 11166 { 11167 u16 fw_ver1, fw_ver2, val; 11168 struct bnx2x *bp = params->bp; 11169 DP(NETIF_MSG_LINK, "Setting the SFX7101 LASI indication\n"); 11170 11171 /* Restore normal power mode*/ 11172 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 11173 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); 11174 /* HW reset */ 11175 bnx2x_ext_phy_hw_reset(bp, params->port); 11176 bnx2x_wait_reset_complete(bp, phy, params); 11177 11178 bnx2x_cl45_write(bp, phy, 11179 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x1); 11180 DP(NETIF_MSG_LINK, "Setting the SFX7101 LED to blink on traffic\n"); 11181 bnx2x_cl45_write(bp, phy, 11182 MDIO_PMA_DEVAD, MDIO_PMA_REG_7107_LED_CNTL, (1<<3)); 11183 11184 bnx2x_ext_phy_set_pause(params, phy, vars); 11185 /* Restart autoneg */ 11186 bnx2x_cl45_read(bp, phy, 11187 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, &val); 11188 val |= 0x200; 11189 bnx2x_cl45_write(bp, phy, 11190 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, val); 11191 11192 /* Save spirom version */ 11193 bnx2x_cl45_read(bp, phy, 11194 MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER1, &fw_ver1); 11195 11196 bnx2x_cl45_read(bp, phy, 11197 MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER2, &fw_ver2); 11198 bnx2x_save_spirom_version(bp, params->port, 11199 (u32)(fw_ver1<<16 | fw_ver2), phy->ver_addr); 11200 return 0; 11201 } 11202 11203 static u8 bnx2x_7101_read_status(struct bnx2x_phy *phy, 11204 struct link_params *params, 11205 struct link_vars *vars) 11206 { 11207 struct bnx2x *bp = params->bp; 11208 u8 link_up; 11209 u16 val1, val2; 11210 bnx2x_cl45_read(bp, phy, 11211 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2); 11212 bnx2x_cl45_read(bp, phy, 11213 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1); 11214 DP(NETIF_MSG_LINK, "10G-base-T LASI status 0x%x->0x%x\n", 11215 val2, val1); 11216 bnx2x_cl45_read(bp, phy, 11217 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2); 11218 bnx2x_cl45_read(bp, phy, 11219 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1); 11220 DP(NETIF_MSG_LINK, "10G-base-T PMA status 0x%x->0x%x\n", 11221 val2, val1); 11222 link_up = ((val1 & 4) == 4); 11223 /* If link is up print the AN outcome of the SFX7101 PHY */ 11224 if (link_up) { 11225 bnx2x_cl45_read(bp, phy, 11226 MDIO_AN_DEVAD, MDIO_AN_REG_MASTER_STATUS, 11227 &val2); 11228 vars->line_speed = SPEED_10000; 11229 vars->duplex = DUPLEX_FULL; 11230 DP(NETIF_MSG_LINK, "SFX7101 AN status 0x%x->Master=%x\n", 11231 val2, (val2 & (1<<14))); 11232 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars); 11233 bnx2x_ext_phy_resolve_fc(phy, params, vars); 11234 11235 /* Read LP advertised speeds */ 11236 if (val2 & (1<<11)) 11237 vars->link_status |= 11238 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; 11239 } 11240 return link_up; 11241 } 11242 11243 static int bnx2x_7101_format_ver(u32 spirom_ver, u8 *str, u16 *len) 11244 { 11245 if (*len < 5) 11246 return -EINVAL; 11247 str[0] = (spirom_ver & 0xFF); 11248 str[1] = (spirom_ver & 0xFF00) >> 8; 11249 str[2] = (spirom_ver & 0xFF0000) >> 16; 11250 str[3] = (spirom_ver & 0xFF000000) >> 24; 11251 str[4] = '\0'; 11252 *len -= 5; 11253 return 0; 11254 } 11255 11256 void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, struct bnx2x_phy *phy) 11257 { 11258 u16 val, cnt; 11259 11260 bnx2x_cl45_read(bp, phy, 11261 MDIO_PMA_DEVAD, 11262 MDIO_PMA_REG_7101_RESET, &val); 11263 11264 for (cnt = 0; cnt < 10; cnt++) { 11265 msleep(50); 11266 /* Writes a self-clearing reset */ 11267 bnx2x_cl45_write(bp, phy, 11268 MDIO_PMA_DEVAD, 11269 MDIO_PMA_REG_7101_RESET, 11270 (val | (1<<15))); 11271 /* Wait for clear */ 11272 bnx2x_cl45_read(bp, phy, 11273 MDIO_PMA_DEVAD, 11274 MDIO_PMA_REG_7101_RESET, &val); 11275 11276 if ((val & (1<<15)) == 0) 11277 break; 11278 } 11279 } 11280 11281 static void bnx2x_7101_hw_reset(struct bnx2x_phy *phy, 11282 struct link_params *params) { 11283 /* Low power mode is controlled by GPIO 2 */ 11284 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_2, 11285 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port); 11286 /* The PHY reset is controlled by GPIO 1 */ 11287 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1, 11288 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port); 11289 } 11290 11291 static void bnx2x_7101_set_link_led(struct bnx2x_phy *phy, 11292 struct link_params *params, u8 mode) 11293 { 11294 u16 val = 0; 11295 struct bnx2x *bp = params->bp; 11296 switch (mode) { 11297 case LED_MODE_FRONT_PANEL_OFF: 11298 case LED_MODE_OFF: 11299 val = 2; 11300 break; 11301 case LED_MODE_ON: 11302 val = 1; 11303 break; 11304 case LED_MODE_OPER: 11305 val = 0; 11306 break; 11307 } 11308 bnx2x_cl45_write(bp, phy, 11309 MDIO_PMA_DEVAD, 11310 MDIO_PMA_REG_7107_LINK_LED_CNTL, 11311 val); 11312 } 11313 11314 /******************************************************************/ 11315 /* STATIC PHY DECLARATION */ 11316 /******************************************************************/ 11317 11318 static const struct bnx2x_phy phy_null = { 11319 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN, 11320 .addr = 0, 11321 .def_md_devad = 0, 11322 .flags = FLAGS_INIT_XGXS_FIRST, 11323 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11324 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11325 .mdio_ctrl = 0, 11326 .supported = 0, 11327 .media_type = ETH_PHY_NOT_PRESENT, 11328 .ver_addr = 0, 11329 .req_flow_ctrl = 0, 11330 .req_line_speed = 0, 11331 .speed_cap_mask = 0, 11332 .req_duplex = 0, 11333 .rsrv = 0, 11334 .config_init = (config_init_t)NULL, 11335 .read_status = (read_status_t)NULL, 11336 .link_reset = (link_reset_t)NULL, 11337 .config_loopback = (config_loopback_t)NULL, 11338 .format_fw_ver = (format_fw_ver_t)NULL, 11339 .hw_reset = (hw_reset_t)NULL, 11340 .set_link_led = (set_link_led_t)NULL, 11341 .phy_specific_func = (phy_specific_func_t)NULL 11342 }; 11343 11344 static const struct bnx2x_phy phy_serdes = { 11345 .type = PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT, 11346 .addr = 0xff, 11347 .def_md_devad = 0, 11348 .flags = 0, 11349 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11350 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11351 .mdio_ctrl = 0, 11352 .supported = (SUPPORTED_10baseT_Half | 11353 SUPPORTED_10baseT_Full | 11354 SUPPORTED_100baseT_Half | 11355 SUPPORTED_100baseT_Full | 11356 SUPPORTED_1000baseT_Full | 11357 SUPPORTED_2500baseX_Full | 11358 SUPPORTED_TP | 11359 SUPPORTED_Autoneg | 11360 SUPPORTED_Pause | 11361 SUPPORTED_Asym_Pause), 11362 .media_type = ETH_PHY_BASE_T, 11363 .ver_addr = 0, 11364 .req_flow_ctrl = 0, 11365 .req_line_speed = 0, 11366 .speed_cap_mask = 0, 11367 .req_duplex = 0, 11368 .rsrv = 0, 11369 .config_init = (config_init_t)bnx2x_xgxs_config_init, 11370 .read_status = (read_status_t)bnx2x_link_settings_status, 11371 .link_reset = (link_reset_t)bnx2x_int_link_reset, 11372 .config_loopback = (config_loopback_t)NULL, 11373 .format_fw_ver = (format_fw_ver_t)NULL, 11374 .hw_reset = (hw_reset_t)NULL, 11375 .set_link_led = (set_link_led_t)NULL, 11376 .phy_specific_func = (phy_specific_func_t)NULL 11377 }; 11378 11379 static const struct bnx2x_phy phy_xgxs = { 11380 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT, 11381 .addr = 0xff, 11382 .def_md_devad = 0, 11383 .flags = 0, 11384 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11385 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11386 .mdio_ctrl = 0, 11387 .supported = (SUPPORTED_10baseT_Half | 11388 SUPPORTED_10baseT_Full | 11389 SUPPORTED_100baseT_Half | 11390 SUPPORTED_100baseT_Full | 11391 SUPPORTED_1000baseT_Full | 11392 SUPPORTED_2500baseX_Full | 11393 SUPPORTED_10000baseT_Full | 11394 SUPPORTED_FIBRE | 11395 SUPPORTED_Autoneg | 11396 SUPPORTED_Pause | 11397 SUPPORTED_Asym_Pause), 11398 .media_type = ETH_PHY_CX4, 11399 .ver_addr = 0, 11400 .req_flow_ctrl = 0, 11401 .req_line_speed = 0, 11402 .speed_cap_mask = 0, 11403 .req_duplex = 0, 11404 .rsrv = 0, 11405 .config_init = (config_init_t)bnx2x_xgxs_config_init, 11406 .read_status = (read_status_t)bnx2x_link_settings_status, 11407 .link_reset = (link_reset_t)bnx2x_int_link_reset, 11408 .config_loopback = (config_loopback_t)bnx2x_set_xgxs_loopback, 11409 .format_fw_ver = (format_fw_ver_t)NULL, 11410 .hw_reset = (hw_reset_t)NULL, 11411 .set_link_led = (set_link_led_t)NULL, 11412 .phy_specific_func = (phy_specific_func_t)bnx2x_xgxs_specific_func 11413 }; 11414 static const struct bnx2x_phy phy_warpcore = { 11415 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT, 11416 .addr = 0xff, 11417 .def_md_devad = 0, 11418 .flags = FLAGS_TX_ERROR_CHECK, 11419 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11420 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11421 .mdio_ctrl = 0, 11422 .supported = (SUPPORTED_10baseT_Half | 11423 SUPPORTED_10baseT_Full | 11424 SUPPORTED_100baseT_Half | 11425 SUPPORTED_100baseT_Full | 11426 SUPPORTED_1000baseT_Full | 11427 SUPPORTED_10000baseT_Full | 11428 SUPPORTED_20000baseKR2_Full | 11429 SUPPORTED_20000baseMLD2_Full | 11430 SUPPORTED_FIBRE | 11431 SUPPORTED_Autoneg | 11432 SUPPORTED_Pause | 11433 SUPPORTED_Asym_Pause), 11434 .media_type = ETH_PHY_UNSPECIFIED, 11435 .ver_addr = 0, 11436 .req_flow_ctrl = 0, 11437 .req_line_speed = 0, 11438 .speed_cap_mask = 0, 11439 /* req_duplex = */0, 11440 /* rsrv = */0, 11441 .config_init = (config_init_t)bnx2x_warpcore_config_init, 11442 .read_status = (read_status_t)bnx2x_warpcore_read_status, 11443 .link_reset = (link_reset_t)bnx2x_warpcore_link_reset, 11444 .config_loopback = (config_loopback_t)bnx2x_set_warpcore_loopback, 11445 .format_fw_ver = (format_fw_ver_t)NULL, 11446 .hw_reset = (hw_reset_t)bnx2x_warpcore_hw_reset, 11447 .set_link_led = (set_link_led_t)NULL, 11448 .phy_specific_func = (phy_specific_func_t)NULL 11449 }; 11450 11451 11452 static const struct bnx2x_phy phy_7101 = { 11453 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101, 11454 .addr = 0xff, 11455 .def_md_devad = 0, 11456 .flags = FLAGS_FAN_FAILURE_DET_REQ, 11457 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11458 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11459 .mdio_ctrl = 0, 11460 .supported = (SUPPORTED_10000baseT_Full | 11461 SUPPORTED_TP | 11462 SUPPORTED_Autoneg | 11463 SUPPORTED_Pause | 11464 SUPPORTED_Asym_Pause), 11465 .media_type = ETH_PHY_BASE_T, 11466 .ver_addr = 0, 11467 .req_flow_ctrl = 0, 11468 .req_line_speed = 0, 11469 .speed_cap_mask = 0, 11470 .req_duplex = 0, 11471 .rsrv = 0, 11472 .config_init = (config_init_t)bnx2x_7101_config_init, 11473 .read_status = (read_status_t)bnx2x_7101_read_status, 11474 .link_reset = (link_reset_t)bnx2x_common_ext_link_reset, 11475 .config_loopback = (config_loopback_t)bnx2x_7101_config_loopback, 11476 .format_fw_ver = (format_fw_ver_t)bnx2x_7101_format_ver, 11477 .hw_reset = (hw_reset_t)bnx2x_7101_hw_reset, 11478 .set_link_led = (set_link_led_t)bnx2x_7101_set_link_led, 11479 .phy_specific_func = (phy_specific_func_t)NULL 11480 }; 11481 static const struct bnx2x_phy phy_8073 = { 11482 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073, 11483 .addr = 0xff, 11484 .def_md_devad = 0, 11485 .flags = 0, 11486 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11487 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11488 .mdio_ctrl = 0, 11489 .supported = (SUPPORTED_10000baseT_Full | 11490 SUPPORTED_2500baseX_Full | 11491 SUPPORTED_1000baseT_Full | 11492 SUPPORTED_FIBRE | 11493 SUPPORTED_Autoneg | 11494 SUPPORTED_Pause | 11495 SUPPORTED_Asym_Pause), 11496 .media_type = ETH_PHY_KR, 11497 .ver_addr = 0, 11498 .req_flow_ctrl = 0, 11499 .req_line_speed = 0, 11500 .speed_cap_mask = 0, 11501 .req_duplex = 0, 11502 .rsrv = 0, 11503 .config_init = (config_init_t)bnx2x_8073_config_init, 11504 .read_status = (read_status_t)bnx2x_8073_read_status, 11505 .link_reset = (link_reset_t)bnx2x_8073_link_reset, 11506 .config_loopback = (config_loopback_t)NULL, 11507 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver, 11508 .hw_reset = (hw_reset_t)NULL, 11509 .set_link_led = (set_link_led_t)NULL, 11510 .phy_specific_func = (phy_specific_func_t)bnx2x_8073_specific_func 11511 }; 11512 static const struct bnx2x_phy phy_8705 = { 11513 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705, 11514 .addr = 0xff, 11515 .def_md_devad = 0, 11516 .flags = FLAGS_INIT_XGXS_FIRST, 11517 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11518 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11519 .mdio_ctrl = 0, 11520 .supported = (SUPPORTED_10000baseT_Full | 11521 SUPPORTED_FIBRE | 11522 SUPPORTED_Pause | 11523 SUPPORTED_Asym_Pause), 11524 .media_type = ETH_PHY_XFP_FIBER, 11525 .ver_addr = 0, 11526 .req_flow_ctrl = 0, 11527 .req_line_speed = 0, 11528 .speed_cap_mask = 0, 11529 .req_duplex = 0, 11530 .rsrv = 0, 11531 .config_init = (config_init_t)bnx2x_8705_config_init, 11532 .read_status = (read_status_t)bnx2x_8705_read_status, 11533 .link_reset = (link_reset_t)bnx2x_common_ext_link_reset, 11534 .config_loopback = (config_loopback_t)NULL, 11535 .format_fw_ver = (format_fw_ver_t)bnx2x_null_format_ver, 11536 .hw_reset = (hw_reset_t)NULL, 11537 .set_link_led = (set_link_led_t)NULL, 11538 .phy_specific_func = (phy_specific_func_t)NULL 11539 }; 11540 static const struct bnx2x_phy phy_8706 = { 11541 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706, 11542 .addr = 0xff, 11543 .def_md_devad = 0, 11544 .flags = FLAGS_INIT_XGXS_FIRST, 11545 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11546 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11547 .mdio_ctrl = 0, 11548 .supported = (SUPPORTED_10000baseT_Full | 11549 SUPPORTED_1000baseT_Full | 11550 SUPPORTED_FIBRE | 11551 SUPPORTED_Pause | 11552 SUPPORTED_Asym_Pause), 11553 .media_type = ETH_PHY_SFPP_10G_FIBER, 11554 .ver_addr = 0, 11555 .req_flow_ctrl = 0, 11556 .req_line_speed = 0, 11557 .speed_cap_mask = 0, 11558 .req_duplex = 0, 11559 .rsrv = 0, 11560 .config_init = (config_init_t)bnx2x_8706_config_init, 11561 .read_status = (read_status_t)bnx2x_8706_read_status, 11562 .link_reset = (link_reset_t)bnx2x_common_ext_link_reset, 11563 .config_loopback = (config_loopback_t)NULL, 11564 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver, 11565 .hw_reset = (hw_reset_t)NULL, 11566 .set_link_led = (set_link_led_t)NULL, 11567 .phy_specific_func = (phy_specific_func_t)NULL 11568 }; 11569 11570 static const struct bnx2x_phy phy_8726 = { 11571 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726, 11572 .addr = 0xff, 11573 .def_md_devad = 0, 11574 .flags = (FLAGS_INIT_XGXS_FIRST | 11575 FLAGS_TX_ERROR_CHECK), 11576 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11577 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11578 .mdio_ctrl = 0, 11579 .supported = (SUPPORTED_10000baseT_Full | 11580 SUPPORTED_1000baseT_Full | 11581 SUPPORTED_Autoneg | 11582 SUPPORTED_FIBRE | 11583 SUPPORTED_Pause | 11584 SUPPORTED_Asym_Pause), 11585 .media_type = ETH_PHY_NOT_PRESENT, 11586 .ver_addr = 0, 11587 .req_flow_ctrl = 0, 11588 .req_line_speed = 0, 11589 .speed_cap_mask = 0, 11590 .req_duplex = 0, 11591 .rsrv = 0, 11592 .config_init = (config_init_t)bnx2x_8726_config_init, 11593 .read_status = (read_status_t)bnx2x_8726_read_status, 11594 .link_reset = (link_reset_t)bnx2x_8726_link_reset, 11595 .config_loopback = (config_loopback_t)bnx2x_8726_config_loopback, 11596 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver, 11597 .hw_reset = (hw_reset_t)NULL, 11598 .set_link_led = (set_link_led_t)NULL, 11599 .phy_specific_func = (phy_specific_func_t)NULL 11600 }; 11601 11602 static const struct bnx2x_phy phy_8727 = { 11603 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727, 11604 .addr = 0xff, 11605 .def_md_devad = 0, 11606 .flags = (FLAGS_FAN_FAILURE_DET_REQ | 11607 FLAGS_TX_ERROR_CHECK), 11608 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11609 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11610 .mdio_ctrl = 0, 11611 .supported = (SUPPORTED_10000baseT_Full | 11612 SUPPORTED_1000baseT_Full | 11613 SUPPORTED_FIBRE | 11614 SUPPORTED_Pause | 11615 SUPPORTED_Asym_Pause), 11616 .media_type = ETH_PHY_NOT_PRESENT, 11617 .ver_addr = 0, 11618 .req_flow_ctrl = 0, 11619 .req_line_speed = 0, 11620 .speed_cap_mask = 0, 11621 .req_duplex = 0, 11622 .rsrv = 0, 11623 .config_init = (config_init_t)bnx2x_8727_config_init, 11624 .read_status = (read_status_t)bnx2x_8727_read_status, 11625 .link_reset = (link_reset_t)bnx2x_8727_link_reset, 11626 .config_loopback = (config_loopback_t)NULL, 11627 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver, 11628 .hw_reset = (hw_reset_t)bnx2x_8727_hw_reset, 11629 .set_link_led = (set_link_led_t)bnx2x_8727_set_link_led, 11630 .phy_specific_func = (phy_specific_func_t)bnx2x_8727_specific_func 11631 }; 11632 static const struct bnx2x_phy phy_8481 = { 11633 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481, 11634 .addr = 0xff, 11635 .def_md_devad = 0, 11636 .flags = FLAGS_FAN_FAILURE_DET_REQ | 11637 FLAGS_REARM_LATCH_SIGNAL, 11638 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11639 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11640 .mdio_ctrl = 0, 11641 .supported = (SUPPORTED_10baseT_Half | 11642 SUPPORTED_10baseT_Full | 11643 SUPPORTED_100baseT_Half | 11644 SUPPORTED_100baseT_Full | 11645 SUPPORTED_1000baseT_Full | 11646 SUPPORTED_10000baseT_Full | 11647 SUPPORTED_TP | 11648 SUPPORTED_Autoneg | 11649 SUPPORTED_Pause | 11650 SUPPORTED_Asym_Pause), 11651 .media_type = ETH_PHY_BASE_T, 11652 .ver_addr = 0, 11653 .req_flow_ctrl = 0, 11654 .req_line_speed = 0, 11655 .speed_cap_mask = 0, 11656 .req_duplex = 0, 11657 .rsrv = 0, 11658 .config_init = (config_init_t)bnx2x_8481_config_init, 11659 .read_status = (read_status_t)bnx2x_848xx_read_status, 11660 .link_reset = (link_reset_t)bnx2x_8481_link_reset, 11661 .config_loopback = (config_loopback_t)NULL, 11662 .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver, 11663 .hw_reset = (hw_reset_t)bnx2x_8481_hw_reset, 11664 .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led, 11665 .phy_specific_func = (phy_specific_func_t)NULL 11666 }; 11667 11668 static const struct bnx2x_phy phy_84823 = { 11669 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823, 11670 .addr = 0xff, 11671 .def_md_devad = 0, 11672 .flags = (FLAGS_FAN_FAILURE_DET_REQ | 11673 FLAGS_REARM_LATCH_SIGNAL | 11674 FLAGS_TX_ERROR_CHECK), 11675 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11676 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11677 .mdio_ctrl = 0, 11678 .supported = (SUPPORTED_10baseT_Half | 11679 SUPPORTED_10baseT_Full | 11680 SUPPORTED_100baseT_Half | 11681 SUPPORTED_100baseT_Full | 11682 SUPPORTED_1000baseT_Full | 11683 SUPPORTED_10000baseT_Full | 11684 SUPPORTED_TP | 11685 SUPPORTED_Autoneg | 11686 SUPPORTED_Pause | 11687 SUPPORTED_Asym_Pause), 11688 .media_type = ETH_PHY_BASE_T, 11689 .ver_addr = 0, 11690 .req_flow_ctrl = 0, 11691 .req_line_speed = 0, 11692 .speed_cap_mask = 0, 11693 .req_duplex = 0, 11694 .rsrv = 0, 11695 .config_init = (config_init_t)bnx2x_848x3_config_init, 11696 .read_status = (read_status_t)bnx2x_848xx_read_status, 11697 .link_reset = (link_reset_t)bnx2x_848x3_link_reset, 11698 .config_loopback = (config_loopback_t)NULL, 11699 .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver, 11700 .hw_reset = (hw_reset_t)NULL, 11701 .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led, 11702 .phy_specific_func = (phy_specific_func_t)bnx2x_848xx_specific_func 11703 }; 11704 11705 static const struct bnx2x_phy phy_84833 = { 11706 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833, 11707 .addr = 0xff, 11708 .def_md_devad = 0, 11709 .flags = (FLAGS_FAN_FAILURE_DET_REQ | 11710 FLAGS_REARM_LATCH_SIGNAL | 11711 FLAGS_TX_ERROR_CHECK), 11712 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11713 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11714 .mdio_ctrl = 0, 11715 .supported = (SUPPORTED_100baseT_Half | 11716 SUPPORTED_100baseT_Full | 11717 SUPPORTED_1000baseT_Full | 11718 SUPPORTED_10000baseT_Full | 11719 SUPPORTED_TP | 11720 SUPPORTED_Autoneg | 11721 SUPPORTED_Pause | 11722 SUPPORTED_Asym_Pause), 11723 .media_type = ETH_PHY_BASE_T, 11724 .ver_addr = 0, 11725 .req_flow_ctrl = 0, 11726 .req_line_speed = 0, 11727 .speed_cap_mask = 0, 11728 .req_duplex = 0, 11729 .rsrv = 0, 11730 .config_init = (config_init_t)bnx2x_848x3_config_init, 11731 .read_status = (read_status_t)bnx2x_848xx_read_status, 11732 .link_reset = (link_reset_t)bnx2x_848x3_link_reset, 11733 .config_loopback = (config_loopback_t)NULL, 11734 .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver, 11735 .hw_reset = (hw_reset_t)bnx2x_84833_hw_reset_phy, 11736 .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led, 11737 .phy_specific_func = (phy_specific_func_t)bnx2x_848xx_specific_func 11738 }; 11739 11740 static const struct bnx2x_phy phy_84834 = { 11741 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834, 11742 .addr = 0xff, 11743 .def_md_devad = 0, 11744 .flags = FLAGS_FAN_FAILURE_DET_REQ | 11745 FLAGS_REARM_LATCH_SIGNAL, 11746 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11747 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11748 .mdio_ctrl = 0, 11749 .supported = (SUPPORTED_100baseT_Half | 11750 SUPPORTED_100baseT_Full | 11751 SUPPORTED_1000baseT_Full | 11752 SUPPORTED_10000baseT_Full | 11753 SUPPORTED_TP | 11754 SUPPORTED_Autoneg | 11755 SUPPORTED_Pause | 11756 SUPPORTED_Asym_Pause), 11757 .media_type = ETH_PHY_BASE_T, 11758 .ver_addr = 0, 11759 .req_flow_ctrl = 0, 11760 .req_line_speed = 0, 11761 .speed_cap_mask = 0, 11762 .req_duplex = 0, 11763 .rsrv = 0, 11764 .config_init = (config_init_t)bnx2x_848x3_config_init, 11765 .read_status = (read_status_t)bnx2x_848xx_read_status, 11766 .link_reset = (link_reset_t)bnx2x_848x3_link_reset, 11767 .config_loopback = (config_loopback_t)NULL, 11768 .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver, 11769 .hw_reset = (hw_reset_t)bnx2x_84833_hw_reset_phy, 11770 .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led, 11771 .phy_specific_func = (phy_specific_func_t)bnx2x_848xx_specific_func 11772 }; 11773 11774 static const struct bnx2x_phy phy_54618se = { 11775 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE, 11776 .addr = 0xff, 11777 .def_md_devad = 0, 11778 .flags = FLAGS_INIT_XGXS_FIRST, 11779 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11780 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11781 .mdio_ctrl = 0, 11782 .supported = (SUPPORTED_10baseT_Half | 11783 SUPPORTED_10baseT_Full | 11784 SUPPORTED_100baseT_Half | 11785 SUPPORTED_100baseT_Full | 11786 SUPPORTED_1000baseT_Full | 11787 SUPPORTED_TP | 11788 SUPPORTED_Autoneg | 11789 SUPPORTED_Pause | 11790 SUPPORTED_Asym_Pause), 11791 .media_type = ETH_PHY_BASE_T, 11792 .ver_addr = 0, 11793 .req_flow_ctrl = 0, 11794 .req_line_speed = 0, 11795 .speed_cap_mask = 0, 11796 /* req_duplex = */0, 11797 /* rsrv = */0, 11798 .config_init = (config_init_t)bnx2x_54618se_config_init, 11799 .read_status = (read_status_t)bnx2x_54618se_read_status, 11800 .link_reset = (link_reset_t)bnx2x_54618se_link_reset, 11801 .config_loopback = (config_loopback_t)bnx2x_54618se_config_loopback, 11802 .format_fw_ver = (format_fw_ver_t)NULL, 11803 .hw_reset = (hw_reset_t)NULL, 11804 .set_link_led = (set_link_led_t)bnx2x_5461x_set_link_led, 11805 .phy_specific_func = (phy_specific_func_t)bnx2x_54618se_specific_func 11806 }; 11807 /*****************************************************************/ 11808 /* */ 11809 /* Populate the phy according. Main function: bnx2x_populate_phy */ 11810 /* */ 11811 /*****************************************************************/ 11812 11813 static void bnx2x_populate_preemphasis(struct bnx2x *bp, u32 shmem_base, 11814 struct bnx2x_phy *phy, u8 port, 11815 u8 phy_index) 11816 { 11817 /* Get the 4 lanes xgxs config rx and tx */ 11818 u32 rx = 0, tx = 0, i; 11819 for (i = 0; i < 2; i++) { 11820 /* INT_PHY and EXT_PHY1 share the same value location in 11821 * the shmem. When num_phys is greater than 1, than this value 11822 * applies only to EXT_PHY1 11823 */ 11824 if (phy_index == INT_PHY || phy_index == EXT_PHY1) { 11825 rx = REG_RD(bp, shmem_base + 11826 offsetof(struct shmem_region, 11827 dev_info.port_hw_config[port].xgxs_config_rx[i<<1])); 11828 11829 tx = REG_RD(bp, shmem_base + 11830 offsetof(struct shmem_region, 11831 dev_info.port_hw_config[port].xgxs_config_tx[i<<1])); 11832 } else { 11833 rx = REG_RD(bp, shmem_base + 11834 offsetof(struct shmem_region, 11835 dev_info.port_hw_config[port].xgxs_config2_rx[i<<1])); 11836 11837 tx = REG_RD(bp, shmem_base + 11838 offsetof(struct shmem_region, 11839 dev_info.port_hw_config[port].xgxs_config2_rx[i<<1])); 11840 } 11841 11842 phy->rx_preemphasis[i << 1] = ((rx>>16) & 0xffff); 11843 phy->rx_preemphasis[(i << 1) + 1] = (rx & 0xffff); 11844 11845 phy->tx_preemphasis[i << 1] = ((tx>>16) & 0xffff); 11846 phy->tx_preemphasis[(i << 1) + 1] = (tx & 0xffff); 11847 } 11848 } 11849 11850 static u32 bnx2x_get_ext_phy_config(struct bnx2x *bp, u32 shmem_base, 11851 u8 phy_index, u8 port) 11852 { 11853 u32 ext_phy_config = 0; 11854 switch (phy_index) { 11855 case EXT_PHY1: 11856 ext_phy_config = REG_RD(bp, shmem_base + 11857 offsetof(struct shmem_region, 11858 dev_info.port_hw_config[port].external_phy_config)); 11859 break; 11860 case EXT_PHY2: 11861 ext_phy_config = REG_RD(bp, shmem_base + 11862 offsetof(struct shmem_region, 11863 dev_info.port_hw_config[port].external_phy_config2)); 11864 break; 11865 default: 11866 DP(NETIF_MSG_LINK, "Invalid phy_index %d\n", phy_index); 11867 return -EINVAL; 11868 } 11869 11870 return ext_phy_config; 11871 } 11872 static int bnx2x_populate_int_phy(struct bnx2x *bp, u32 shmem_base, u8 port, 11873 struct bnx2x_phy *phy) 11874 { 11875 u32 phy_addr; 11876 u32 chip_id; 11877 u32 switch_cfg = (REG_RD(bp, shmem_base + 11878 offsetof(struct shmem_region, 11879 dev_info.port_feature_config[port].link_config)) & 11880 PORT_FEATURE_CONNECTED_SWITCH_MASK); 11881 chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) | 11882 ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12); 11883 11884 DP(NETIF_MSG_LINK, ":chip_id = 0x%x\n", chip_id); 11885 if (USES_WARPCORE(bp)) { 11886 u32 serdes_net_if; 11887 phy_addr = REG_RD(bp, 11888 MISC_REG_WC0_CTRL_PHY_ADDR); 11889 *phy = phy_warpcore; 11890 if (REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR) == 0x3) 11891 phy->flags |= FLAGS_4_PORT_MODE; 11892 else 11893 phy->flags &= ~FLAGS_4_PORT_MODE; 11894 /* Check Dual mode */ 11895 serdes_net_if = (REG_RD(bp, shmem_base + 11896 offsetof(struct shmem_region, dev_info. 11897 port_hw_config[port].default_cfg)) & 11898 PORT_HW_CFG_NET_SERDES_IF_MASK); 11899 /* Set the appropriate supported and flags indications per 11900 * interface type of the chip 11901 */ 11902 switch (serdes_net_if) { 11903 case PORT_HW_CFG_NET_SERDES_IF_SGMII: 11904 phy->supported &= (SUPPORTED_10baseT_Half | 11905 SUPPORTED_10baseT_Full | 11906 SUPPORTED_100baseT_Half | 11907 SUPPORTED_100baseT_Full | 11908 SUPPORTED_1000baseT_Full | 11909 SUPPORTED_FIBRE | 11910 SUPPORTED_Autoneg | 11911 SUPPORTED_Pause | 11912 SUPPORTED_Asym_Pause); 11913 phy->media_type = ETH_PHY_BASE_T; 11914 break; 11915 case PORT_HW_CFG_NET_SERDES_IF_XFI: 11916 phy->supported &= (SUPPORTED_1000baseT_Full | 11917 SUPPORTED_10000baseT_Full | 11918 SUPPORTED_FIBRE | 11919 SUPPORTED_Pause | 11920 SUPPORTED_Asym_Pause); 11921 phy->media_type = ETH_PHY_XFP_FIBER; 11922 break; 11923 case PORT_HW_CFG_NET_SERDES_IF_SFI: 11924 phy->supported &= (SUPPORTED_1000baseT_Full | 11925 SUPPORTED_10000baseT_Full | 11926 SUPPORTED_FIBRE | 11927 SUPPORTED_Pause | 11928 SUPPORTED_Asym_Pause); 11929 phy->media_type = ETH_PHY_SFPP_10G_FIBER; 11930 break; 11931 case PORT_HW_CFG_NET_SERDES_IF_KR: 11932 phy->media_type = ETH_PHY_KR; 11933 phy->supported &= (SUPPORTED_1000baseT_Full | 11934 SUPPORTED_10000baseT_Full | 11935 SUPPORTED_FIBRE | 11936 SUPPORTED_Autoneg | 11937 SUPPORTED_Pause | 11938 SUPPORTED_Asym_Pause); 11939 break; 11940 case PORT_HW_CFG_NET_SERDES_IF_DXGXS: 11941 phy->media_type = ETH_PHY_KR; 11942 phy->flags |= FLAGS_WC_DUAL_MODE; 11943 phy->supported &= (SUPPORTED_20000baseMLD2_Full | 11944 SUPPORTED_FIBRE | 11945 SUPPORTED_Pause | 11946 SUPPORTED_Asym_Pause); 11947 break; 11948 case PORT_HW_CFG_NET_SERDES_IF_KR2: 11949 phy->media_type = ETH_PHY_KR; 11950 phy->flags |= FLAGS_WC_DUAL_MODE; 11951 phy->supported &= (SUPPORTED_20000baseKR2_Full | 11952 SUPPORTED_10000baseT_Full | 11953 SUPPORTED_1000baseT_Full | 11954 SUPPORTED_Autoneg | 11955 SUPPORTED_FIBRE | 11956 SUPPORTED_Pause | 11957 SUPPORTED_Asym_Pause); 11958 phy->flags &= ~FLAGS_TX_ERROR_CHECK; 11959 break; 11960 default: 11961 DP(NETIF_MSG_LINK, "Unknown WC interface type 0x%x\n", 11962 serdes_net_if); 11963 break; 11964 } 11965 11966 /* Enable MDC/MDIO work-around for E3 A0 since free running MDC 11967 * was not set as expected. For B0, ECO will be enabled so there 11968 * won't be an issue there 11969 */ 11970 if (CHIP_REV(bp) == CHIP_REV_Ax) 11971 phy->flags |= FLAGS_MDC_MDIO_WA; 11972 else 11973 phy->flags |= FLAGS_MDC_MDIO_WA_B0; 11974 } else { 11975 switch (switch_cfg) { 11976 case SWITCH_CFG_1G: 11977 phy_addr = REG_RD(bp, 11978 NIG_REG_SERDES0_CTRL_PHY_ADDR + 11979 port * 0x10); 11980 *phy = phy_serdes; 11981 break; 11982 case SWITCH_CFG_10G: 11983 phy_addr = REG_RD(bp, 11984 NIG_REG_XGXS0_CTRL_PHY_ADDR + 11985 port * 0x18); 11986 *phy = phy_xgxs; 11987 break; 11988 default: 11989 DP(NETIF_MSG_LINK, "Invalid switch_cfg\n"); 11990 return -EINVAL; 11991 } 11992 } 11993 phy->addr = (u8)phy_addr; 11994 phy->mdio_ctrl = bnx2x_get_emac_base(bp, 11995 SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH, 11996 port); 11997 if (CHIP_IS_E2(bp)) 11998 phy->def_md_devad = E2_DEFAULT_PHY_DEV_ADDR; 11999 else 12000 phy->def_md_devad = DEFAULT_PHY_DEV_ADDR; 12001 12002 DP(NETIF_MSG_LINK, "Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x\n", 12003 port, phy->addr, phy->mdio_ctrl); 12004 12005 bnx2x_populate_preemphasis(bp, shmem_base, phy, port, INT_PHY); 12006 return 0; 12007 } 12008 12009 static int bnx2x_populate_ext_phy(struct bnx2x *bp, 12010 u8 phy_index, 12011 u32 shmem_base, 12012 u32 shmem2_base, 12013 u8 port, 12014 struct bnx2x_phy *phy) 12015 { 12016 u32 ext_phy_config, phy_type, config2; 12017 u32 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH; 12018 ext_phy_config = bnx2x_get_ext_phy_config(bp, shmem_base, 12019 phy_index, port); 12020 phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config); 12021 /* Select the phy type */ 12022 switch (phy_type) { 12023 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073: 12024 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED; 12025 *phy = phy_8073; 12026 break; 12027 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705: 12028 *phy = phy_8705; 12029 break; 12030 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706: 12031 *phy = phy_8706; 12032 break; 12033 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: 12034 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1; 12035 *phy = phy_8726; 12036 break; 12037 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC: 12038 /* BCM8727_NOC => BCM8727 no over current */ 12039 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1; 12040 *phy = phy_8727; 12041 phy->flags |= FLAGS_NOC; 12042 break; 12043 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722: 12044 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: 12045 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1; 12046 *phy = phy_8727; 12047 break; 12048 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481: 12049 *phy = phy_8481; 12050 break; 12051 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823: 12052 *phy = phy_84823; 12053 break; 12054 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833: 12055 *phy = phy_84833; 12056 break; 12057 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834: 12058 *phy = phy_84834; 12059 break; 12060 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616: 12061 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE: 12062 *phy = phy_54618se; 12063 if (phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) 12064 phy->flags |= FLAGS_EEE; 12065 break; 12066 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101: 12067 *phy = phy_7101; 12068 break; 12069 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE: 12070 *phy = phy_null; 12071 return -EINVAL; 12072 default: 12073 *phy = phy_null; 12074 /* In case external PHY wasn't found */ 12075 if ((phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) && 12076 (phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)) 12077 return -EINVAL; 12078 return 0; 12079 } 12080 12081 phy->addr = XGXS_EXT_PHY_ADDR(ext_phy_config); 12082 bnx2x_populate_preemphasis(bp, shmem_base, phy, port, phy_index); 12083 12084 /* The shmem address of the phy version is located on different 12085 * structures. In case this structure is too old, do not set 12086 * the address 12087 */ 12088 config2 = REG_RD(bp, shmem_base + offsetof(struct shmem_region, 12089 dev_info.shared_hw_config.config2)); 12090 if (phy_index == EXT_PHY1) { 12091 phy->ver_addr = shmem_base + offsetof(struct shmem_region, 12092 port_mb[port].ext_phy_fw_version); 12093 12094 /* Check specific mdc mdio settings */ 12095 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK) 12096 mdc_mdio_access = config2 & 12097 SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK; 12098 } else { 12099 u32 size = REG_RD(bp, shmem2_base); 12100 12101 if (size > 12102 offsetof(struct shmem2_region, ext_phy_fw_version2)) { 12103 phy->ver_addr = shmem2_base + 12104 offsetof(struct shmem2_region, 12105 ext_phy_fw_version2[port]); 12106 } 12107 /* Check specific mdc mdio settings */ 12108 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) 12109 mdc_mdio_access = (config2 & 12110 SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) >> 12111 (SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT - 12112 SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT); 12113 } 12114 phy->mdio_ctrl = bnx2x_get_emac_base(bp, mdc_mdio_access, port); 12115 12116 if (((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) || 12117 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) && 12118 (phy->ver_addr)) { 12119 /* Remove 100Mb link supported for BCM84833/4 when phy fw 12120 * version lower than or equal to 1.39 12121 */ 12122 u32 raw_ver = REG_RD(bp, phy->ver_addr); 12123 if (((raw_ver & 0x7F) <= 39) && 12124 (((raw_ver & 0xF80) >> 7) <= 1)) 12125 phy->supported &= ~(SUPPORTED_100baseT_Half | 12126 SUPPORTED_100baseT_Full); 12127 } 12128 12129 DP(NETIF_MSG_LINK, "phy_type 0x%x port %d found in index %d\n", 12130 phy_type, port, phy_index); 12131 DP(NETIF_MSG_LINK, " addr=0x%x, mdio_ctl=0x%x\n", 12132 phy->addr, phy->mdio_ctrl); 12133 return 0; 12134 } 12135 12136 static int bnx2x_populate_phy(struct bnx2x *bp, u8 phy_index, u32 shmem_base, 12137 u32 shmem2_base, u8 port, struct bnx2x_phy *phy) 12138 { 12139 int status = 0; 12140 phy->type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN; 12141 if (phy_index == INT_PHY) 12142 return bnx2x_populate_int_phy(bp, shmem_base, port, phy); 12143 status = bnx2x_populate_ext_phy(bp, phy_index, shmem_base, shmem2_base, 12144 port, phy); 12145 return status; 12146 } 12147 12148 static void bnx2x_phy_def_cfg(struct link_params *params, 12149 struct bnx2x_phy *phy, 12150 u8 phy_index) 12151 { 12152 struct bnx2x *bp = params->bp; 12153 u32 link_config; 12154 /* Populate the default phy configuration for MF mode */ 12155 if (phy_index == EXT_PHY2) { 12156 link_config = REG_RD(bp, params->shmem_base + 12157 offsetof(struct shmem_region, dev_info. 12158 port_feature_config[params->port].link_config2)); 12159 phy->speed_cap_mask = REG_RD(bp, params->shmem_base + 12160 offsetof(struct shmem_region, 12161 dev_info. 12162 port_hw_config[params->port].speed_capability_mask2)); 12163 } else { 12164 link_config = REG_RD(bp, params->shmem_base + 12165 offsetof(struct shmem_region, dev_info. 12166 port_feature_config[params->port].link_config)); 12167 phy->speed_cap_mask = REG_RD(bp, params->shmem_base + 12168 offsetof(struct shmem_region, 12169 dev_info. 12170 port_hw_config[params->port].speed_capability_mask)); 12171 } 12172 DP(NETIF_MSG_LINK, 12173 "Default config phy idx %x cfg 0x%x speed_cap_mask 0x%x\n", 12174 phy_index, link_config, phy->speed_cap_mask); 12175 12176 phy->req_duplex = DUPLEX_FULL; 12177 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) { 12178 case PORT_FEATURE_LINK_SPEED_10M_HALF: 12179 phy->req_duplex = DUPLEX_HALF; 12180 case PORT_FEATURE_LINK_SPEED_10M_FULL: 12181 phy->req_line_speed = SPEED_10; 12182 break; 12183 case PORT_FEATURE_LINK_SPEED_100M_HALF: 12184 phy->req_duplex = DUPLEX_HALF; 12185 case PORT_FEATURE_LINK_SPEED_100M_FULL: 12186 phy->req_line_speed = SPEED_100; 12187 break; 12188 case PORT_FEATURE_LINK_SPEED_1G: 12189 phy->req_line_speed = SPEED_1000; 12190 break; 12191 case PORT_FEATURE_LINK_SPEED_2_5G: 12192 phy->req_line_speed = SPEED_2500; 12193 break; 12194 case PORT_FEATURE_LINK_SPEED_10G_CX4: 12195 phy->req_line_speed = SPEED_10000; 12196 break; 12197 default: 12198 phy->req_line_speed = SPEED_AUTO_NEG; 12199 break; 12200 } 12201 12202 switch (link_config & PORT_FEATURE_FLOW_CONTROL_MASK) { 12203 case PORT_FEATURE_FLOW_CONTROL_AUTO: 12204 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_AUTO; 12205 break; 12206 case PORT_FEATURE_FLOW_CONTROL_TX: 12207 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_TX; 12208 break; 12209 case PORT_FEATURE_FLOW_CONTROL_RX: 12210 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_RX; 12211 break; 12212 case PORT_FEATURE_FLOW_CONTROL_BOTH: 12213 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_BOTH; 12214 break; 12215 default: 12216 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_NONE; 12217 break; 12218 } 12219 } 12220 12221 u32 bnx2x_phy_selection(struct link_params *params) 12222 { 12223 u32 phy_config_swapped, prio_cfg; 12224 u32 return_cfg = PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT; 12225 12226 phy_config_swapped = params->multi_phy_config & 12227 PORT_HW_CFG_PHY_SWAPPED_ENABLED; 12228 12229 prio_cfg = params->multi_phy_config & 12230 PORT_HW_CFG_PHY_SELECTION_MASK; 12231 12232 if (phy_config_swapped) { 12233 switch (prio_cfg) { 12234 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY: 12235 return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY; 12236 break; 12237 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY: 12238 return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY; 12239 break; 12240 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY: 12241 return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY; 12242 break; 12243 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY: 12244 return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY; 12245 break; 12246 } 12247 } else 12248 return_cfg = prio_cfg; 12249 12250 return return_cfg; 12251 } 12252 12253 int bnx2x_phy_probe(struct link_params *params) 12254 { 12255 u8 phy_index, actual_phy_idx; 12256 u32 phy_config_swapped, sync_offset, media_types; 12257 struct bnx2x *bp = params->bp; 12258 struct bnx2x_phy *phy; 12259 params->num_phys = 0; 12260 DP(NETIF_MSG_LINK, "Begin phy probe\n"); 12261 phy_config_swapped = params->multi_phy_config & 12262 PORT_HW_CFG_PHY_SWAPPED_ENABLED; 12263 12264 for (phy_index = INT_PHY; phy_index < MAX_PHYS; 12265 phy_index++) { 12266 actual_phy_idx = phy_index; 12267 if (phy_config_swapped) { 12268 if (phy_index == EXT_PHY1) 12269 actual_phy_idx = EXT_PHY2; 12270 else if (phy_index == EXT_PHY2) 12271 actual_phy_idx = EXT_PHY1; 12272 } 12273 DP(NETIF_MSG_LINK, "phy_config_swapped %x, phy_index %x," 12274 " actual_phy_idx %x\n", phy_config_swapped, 12275 phy_index, actual_phy_idx); 12276 phy = ¶ms->phy[actual_phy_idx]; 12277 if (bnx2x_populate_phy(bp, phy_index, params->shmem_base, 12278 params->shmem2_base, params->port, 12279 phy) != 0) { 12280 params->num_phys = 0; 12281 DP(NETIF_MSG_LINK, "phy probe failed in phy index %d\n", 12282 phy_index); 12283 for (phy_index = INT_PHY; 12284 phy_index < MAX_PHYS; 12285 phy_index++) 12286 *phy = phy_null; 12287 return -EINVAL; 12288 } 12289 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN) 12290 break; 12291 12292 if (params->feature_config_flags & 12293 FEATURE_CONFIG_DISABLE_REMOTE_FAULT_DET) 12294 phy->flags &= ~FLAGS_TX_ERROR_CHECK; 12295 12296 if (!(params->feature_config_flags & 12297 FEATURE_CONFIG_MT_SUPPORT)) 12298 phy->flags |= FLAGS_MDC_MDIO_WA_G; 12299 12300 sync_offset = params->shmem_base + 12301 offsetof(struct shmem_region, 12302 dev_info.port_hw_config[params->port].media_type); 12303 media_types = REG_RD(bp, sync_offset); 12304 12305 /* Update media type for non-PMF sync only for the first time 12306 * In case the media type changes afterwards, it will be updated 12307 * using the update_status function 12308 */ 12309 if ((media_types & (PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK << 12310 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * 12311 actual_phy_idx))) == 0) { 12312 media_types |= ((phy->media_type & 12313 PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) << 12314 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * 12315 actual_phy_idx)); 12316 } 12317 REG_WR(bp, sync_offset, media_types); 12318 12319 bnx2x_phy_def_cfg(params, phy, phy_index); 12320 params->num_phys++; 12321 } 12322 12323 DP(NETIF_MSG_LINK, "End phy probe. #phys found %x\n", params->num_phys); 12324 return 0; 12325 } 12326 12327 static void bnx2x_init_bmac_loopback(struct link_params *params, 12328 struct link_vars *vars) 12329 { 12330 struct bnx2x *bp = params->bp; 12331 vars->link_up = 1; 12332 vars->line_speed = SPEED_10000; 12333 vars->duplex = DUPLEX_FULL; 12334 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; 12335 vars->mac_type = MAC_TYPE_BMAC; 12336 12337 vars->phy_flags = PHY_XGXS_FLAG; 12338 12339 bnx2x_xgxs_deassert(params); 12340 12341 /* Set bmac loopback */ 12342 bnx2x_bmac_enable(params, vars, 1, 1); 12343 12344 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); 12345 } 12346 12347 static void bnx2x_init_emac_loopback(struct link_params *params, 12348 struct link_vars *vars) 12349 { 12350 struct bnx2x *bp = params->bp; 12351 vars->link_up = 1; 12352 vars->line_speed = SPEED_1000; 12353 vars->duplex = DUPLEX_FULL; 12354 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; 12355 vars->mac_type = MAC_TYPE_EMAC; 12356 12357 vars->phy_flags = PHY_XGXS_FLAG; 12358 12359 bnx2x_xgxs_deassert(params); 12360 /* Set bmac loopback */ 12361 bnx2x_emac_enable(params, vars, 1); 12362 bnx2x_emac_program(params, vars); 12363 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); 12364 } 12365 12366 static void bnx2x_init_xmac_loopback(struct link_params *params, 12367 struct link_vars *vars) 12368 { 12369 struct bnx2x *bp = params->bp; 12370 vars->link_up = 1; 12371 if (!params->req_line_speed[0]) 12372 vars->line_speed = SPEED_10000; 12373 else 12374 vars->line_speed = params->req_line_speed[0]; 12375 vars->duplex = DUPLEX_FULL; 12376 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; 12377 vars->mac_type = MAC_TYPE_XMAC; 12378 vars->phy_flags = PHY_XGXS_FLAG; 12379 /* Set WC to loopback mode since link is required to provide clock 12380 * to the XMAC in 20G mode 12381 */ 12382 bnx2x_set_aer_mmd(params, ¶ms->phy[0]); 12383 bnx2x_warpcore_reset_lane(bp, ¶ms->phy[0], 0); 12384 params->phy[INT_PHY].config_loopback( 12385 ¶ms->phy[INT_PHY], 12386 params); 12387 12388 bnx2x_xmac_enable(params, vars, 1); 12389 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); 12390 } 12391 12392 static void bnx2x_init_umac_loopback(struct link_params *params, 12393 struct link_vars *vars) 12394 { 12395 struct bnx2x *bp = params->bp; 12396 vars->link_up = 1; 12397 vars->line_speed = SPEED_1000; 12398 vars->duplex = DUPLEX_FULL; 12399 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; 12400 vars->mac_type = MAC_TYPE_UMAC; 12401 vars->phy_flags = PHY_XGXS_FLAG; 12402 bnx2x_umac_enable(params, vars, 1); 12403 12404 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); 12405 } 12406 12407 static void bnx2x_init_xgxs_loopback(struct link_params *params, 12408 struct link_vars *vars) 12409 { 12410 struct bnx2x *bp = params->bp; 12411 struct bnx2x_phy *int_phy = ¶ms->phy[INT_PHY]; 12412 vars->link_up = 1; 12413 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; 12414 vars->duplex = DUPLEX_FULL; 12415 if (params->req_line_speed[0] == SPEED_1000) 12416 vars->line_speed = SPEED_1000; 12417 else if ((params->req_line_speed[0] == SPEED_20000) || 12418 (int_phy->flags & FLAGS_WC_DUAL_MODE)) 12419 vars->line_speed = SPEED_20000; 12420 else 12421 vars->line_speed = SPEED_10000; 12422 12423 if (!USES_WARPCORE(bp)) 12424 bnx2x_xgxs_deassert(params); 12425 bnx2x_link_initialize(params, vars); 12426 12427 if (params->req_line_speed[0] == SPEED_1000) { 12428 if (USES_WARPCORE(bp)) 12429 bnx2x_umac_enable(params, vars, 0); 12430 else { 12431 bnx2x_emac_program(params, vars); 12432 bnx2x_emac_enable(params, vars, 0); 12433 } 12434 } else { 12435 if (USES_WARPCORE(bp)) 12436 bnx2x_xmac_enable(params, vars, 0); 12437 else 12438 bnx2x_bmac_enable(params, vars, 0, 1); 12439 } 12440 12441 if (params->loopback_mode == LOOPBACK_XGXS) { 12442 /* Set 10G XGXS loopback */ 12443 int_phy->config_loopback(int_phy, params); 12444 } else { 12445 /* Set external phy loopback */ 12446 u8 phy_index; 12447 for (phy_index = EXT_PHY1; 12448 phy_index < params->num_phys; phy_index++) 12449 if (params->phy[phy_index].config_loopback) 12450 params->phy[phy_index].config_loopback( 12451 ¶ms->phy[phy_index], 12452 params); 12453 } 12454 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); 12455 12456 bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed); 12457 } 12458 12459 void bnx2x_set_rx_filter(struct link_params *params, u8 en) 12460 { 12461 struct bnx2x *bp = params->bp; 12462 u8 val = en * 0x1F; 12463 12464 /* Open / close the gate between the NIG and the BRB */ 12465 if (!CHIP_IS_E1x(bp)) 12466 val |= en * 0x20; 12467 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + params->port*4, val); 12468 12469 if (!CHIP_IS_E1(bp)) { 12470 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + params->port*4, 12471 en*0x3); 12472 } 12473 12474 REG_WR(bp, (params->port ? NIG_REG_LLH1_BRB1_NOT_MCP : 12475 NIG_REG_LLH0_BRB1_NOT_MCP), en); 12476 } 12477 static int bnx2x_avoid_link_flap(struct link_params *params, 12478 struct link_vars *vars) 12479 { 12480 u32 phy_idx; 12481 u32 dont_clear_stat, lfa_sts; 12482 struct bnx2x *bp = params->bp; 12483 12484 bnx2x_set_mdio_emac_per_phy(bp, params); 12485 /* Sync the link parameters */ 12486 bnx2x_link_status_update(params, vars); 12487 12488 /* 12489 * The module verification was already done by previous link owner, 12490 * so this call is meant only to get warning message 12491 */ 12492 12493 for (phy_idx = INT_PHY; phy_idx < params->num_phys; phy_idx++) { 12494 struct bnx2x_phy *phy = ¶ms->phy[phy_idx]; 12495 if (phy->phy_specific_func) { 12496 DP(NETIF_MSG_LINK, "Calling PHY specific func\n"); 12497 phy->phy_specific_func(phy, params, PHY_INIT); 12498 } 12499 if ((phy->media_type == ETH_PHY_SFPP_10G_FIBER) || 12500 (phy->media_type == ETH_PHY_SFP_1G_FIBER) || 12501 (phy->media_type == ETH_PHY_DA_TWINAX)) 12502 bnx2x_verify_sfp_module(phy, params); 12503 } 12504 lfa_sts = REG_RD(bp, params->lfa_base + 12505 offsetof(struct shmem_lfa, 12506 lfa_sts)); 12507 12508 dont_clear_stat = lfa_sts & SHMEM_LFA_DONT_CLEAR_STAT; 12509 12510 /* Re-enable the NIG/MAC */ 12511 if (CHIP_IS_E3(bp)) { 12512 if (!dont_clear_stat) { 12513 REG_WR(bp, GRCBASE_MISC + 12514 MISC_REGISTERS_RESET_REG_2_CLEAR, 12515 (MISC_REGISTERS_RESET_REG_2_MSTAT0 << 12516 params->port)); 12517 REG_WR(bp, GRCBASE_MISC + 12518 MISC_REGISTERS_RESET_REG_2_SET, 12519 (MISC_REGISTERS_RESET_REG_2_MSTAT0 << 12520 params->port)); 12521 } 12522 if (vars->line_speed < SPEED_10000) 12523 bnx2x_umac_enable(params, vars, 0); 12524 else 12525 bnx2x_xmac_enable(params, vars, 0); 12526 } else { 12527 if (vars->line_speed < SPEED_10000) 12528 bnx2x_emac_enable(params, vars, 0); 12529 else 12530 bnx2x_bmac_enable(params, vars, 0, !dont_clear_stat); 12531 } 12532 12533 /* Increment LFA count */ 12534 lfa_sts = ((lfa_sts & ~LINK_FLAP_AVOIDANCE_COUNT_MASK) | 12535 (((((lfa_sts & LINK_FLAP_AVOIDANCE_COUNT_MASK) >> 12536 LINK_FLAP_AVOIDANCE_COUNT_OFFSET) + 1) & 0xff) 12537 << LINK_FLAP_AVOIDANCE_COUNT_OFFSET)); 12538 /* Clear link flap reason */ 12539 lfa_sts &= ~LFA_LINK_FLAP_REASON_MASK; 12540 12541 REG_WR(bp, params->lfa_base + 12542 offsetof(struct shmem_lfa, lfa_sts), lfa_sts); 12543 12544 /* Disable NIG DRAIN */ 12545 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); 12546 12547 /* Enable interrupts */ 12548 bnx2x_link_int_enable(params); 12549 return 0; 12550 } 12551 12552 static void bnx2x_cannot_avoid_link_flap(struct link_params *params, 12553 struct link_vars *vars, 12554 int lfa_status) 12555 { 12556 u32 lfa_sts, cfg_idx, tmp_val; 12557 struct bnx2x *bp = params->bp; 12558 12559 bnx2x_link_reset(params, vars, 1); 12560 12561 if (!params->lfa_base) 12562 return; 12563 /* Store the new link parameters */ 12564 REG_WR(bp, params->lfa_base + 12565 offsetof(struct shmem_lfa, req_duplex), 12566 params->req_duplex[0] | (params->req_duplex[1] << 16)); 12567 12568 REG_WR(bp, params->lfa_base + 12569 offsetof(struct shmem_lfa, req_flow_ctrl), 12570 params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16)); 12571 12572 REG_WR(bp, params->lfa_base + 12573 offsetof(struct shmem_lfa, req_line_speed), 12574 params->req_line_speed[0] | (params->req_line_speed[1] << 16)); 12575 12576 for (cfg_idx = 0; cfg_idx < SHMEM_LINK_CONFIG_SIZE; cfg_idx++) { 12577 REG_WR(bp, params->lfa_base + 12578 offsetof(struct shmem_lfa, 12579 speed_cap_mask[cfg_idx]), 12580 params->speed_cap_mask[cfg_idx]); 12581 } 12582 12583 tmp_val = REG_RD(bp, params->lfa_base + 12584 offsetof(struct shmem_lfa, additional_config)); 12585 tmp_val &= ~REQ_FC_AUTO_ADV_MASK; 12586 tmp_val |= params->req_fc_auto_adv; 12587 12588 REG_WR(bp, params->lfa_base + 12589 offsetof(struct shmem_lfa, additional_config), tmp_val); 12590 12591 lfa_sts = REG_RD(bp, params->lfa_base + 12592 offsetof(struct shmem_lfa, lfa_sts)); 12593 12594 /* Clear the "Don't Clear Statistics" bit, and set reason */ 12595 lfa_sts &= ~SHMEM_LFA_DONT_CLEAR_STAT; 12596 12597 /* Set link flap reason */ 12598 lfa_sts &= ~LFA_LINK_FLAP_REASON_MASK; 12599 lfa_sts |= ((lfa_status & LFA_LINK_FLAP_REASON_MASK) << 12600 LFA_LINK_FLAP_REASON_OFFSET); 12601 12602 /* Increment link flap counter */ 12603 lfa_sts = ((lfa_sts & ~LINK_FLAP_COUNT_MASK) | 12604 (((((lfa_sts & LINK_FLAP_COUNT_MASK) >> 12605 LINK_FLAP_COUNT_OFFSET) + 1) & 0xff) 12606 << LINK_FLAP_COUNT_OFFSET)); 12607 REG_WR(bp, params->lfa_base + 12608 offsetof(struct shmem_lfa, lfa_sts), lfa_sts); 12609 /* Proceed with regular link initialization */ 12610 } 12611 12612 int bnx2x_phy_init(struct link_params *params, struct link_vars *vars) 12613 { 12614 int lfa_status; 12615 struct bnx2x *bp = params->bp; 12616 DP(NETIF_MSG_LINK, "Phy Initialization started\n"); 12617 DP(NETIF_MSG_LINK, "(1) req_speed %d, req_flowctrl %d\n", 12618 params->req_line_speed[0], params->req_flow_ctrl[0]); 12619 DP(NETIF_MSG_LINK, "(2) req_speed %d, req_flowctrl %d\n", 12620 params->req_line_speed[1], params->req_flow_ctrl[1]); 12621 DP(NETIF_MSG_LINK, "req_adv_flow_ctrl 0x%x\n", params->req_fc_auto_adv); 12622 vars->link_status = 0; 12623 vars->phy_link_up = 0; 12624 vars->link_up = 0; 12625 vars->line_speed = 0; 12626 vars->duplex = DUPLEX_FULL; 12627 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; 12628 vars->mac_type = MAC_TYPE_NONE; 12629 vars->phy_flags = 0; 12630 vars->check_kr2_recovery_cnt = 0; 12631 params->link_flags = PHY_INITIALIZED; 12632 /* Driver opens NIG-BRB filters */ 12633 bnx2x_set_rx_filter(params, 1); 12634 /* Check if link flap can be avoided */ 12635 lfa_status = bnx2x_check_lfa(params); 12636 12637 if (lfa_status == 0) { 12638 DP(NETIF_MSG_LINK, "Link Flap Avoidance in progress\n"); 12639 return bnx2x_avoid_link_flap(params, vars); 12640 } 12641 12642 DP(NETIF_MSG_LINK, "Cannot avoid link flap lfa_sta=0x%x\n", 12643 lfa_status); 12644 bnx2x_cannot_avoid_link_flap(params, vars, lfa_status); 12645 12646 /* Disable attentions */ 12647 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4, 12648 (NIG_MASK_XGXS0_LINK_STATUS | 12649 NIG_MASK_XGXS0_LINK10G | 12650 NIG_MASK_SERDES0_LINK_STATUS | 12651 NIG_MASK_MI_INT)); 12652 12653 bnx2x_emac_init(params, vars); 12654 12655 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) 12656 vars->link_status |= LINK_STATUS_PFC_ENABLED; 12657 12658 if (params->num_phys == 0) { 12659 DP(NETIF_MSG_LINK, "No phy found for initialization !!\n"); 12660 return -EINVAL; 12661 } 12662 set_phy_vars(params, vars); 12663 12664 DP(NETIF_MSG_LINK, "Num of phys on board: %d\n", params->num_phys); 12665 switch (params->loopback_mode) { 12666 case LOOPBACK_BMAC: 12667 bnx2x_init_bmac_loopback(params, vars); 12668 break; 12669 case LOOPBACK_EMAC: 12670 bnx2x_init_emac_loopback(params, vars); 12671 break; 12672 case LOOPBACK_XMAC: 12673 bnx2x_init_xmac_loopback(params, vars); 12674 break; 12675 case LOOPBACK_UMAC: 12676 bnx2x_init_umac_loopback(params, vars); 12677 break; 12678 case LOOPBACK_XGXS: 12679 case LOOPBACK_EXT_PHY: 12680 bnx2x_init_xgxs_loopback(params, vars); 12681 break; 12682 default: 12683 if (!CHIP_IS_E3(bp)) { 12684 if (params->switch_cfg == SWITCH_CFG_10G) 12685 bnx2x_xgxs_deassert(params); 12686 else 12687 bnx2x_serdes_deassert(bp, params->port); 12688 } 12689 bnx2x_link_initialize(params, vars); 12690 msleep(30); 12691 bnx2x_link_int_enable(params); 12692 break; 12693 } 12694 bnx2x_update_mng(params, vars->link_status); 12695 12696 bnx2x_update_mng_eee(params, vars->eee_status); 12697 return 0; 12698 } 12699 12700 int bnx2x_link_reset(struct link_params *params, struct link_vars *vars, 12701 u8 reset_ext_phy) 12702 { 12703 struct bnx2x *bp = params->bp; 12704 u8 phy_index, port = params->port, clear_latch_ind = 0; 12705 DP(NETIF_MSG_LINK, "Resetting the link of port %d\n", port); 12706 /* Disable attentions */ 12707 vars->link_status = 0; 12708 bnx2x_update_mng(params, vars->link_status); 12709 vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK | 12710 SHMEM_EEE_ACTIVE_BIT); 12711 bnx2x_update_mng_eee(params, vars->eee_status); 12712 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 12713 (NIG_MASK_XGXS0_LINK_STATUS | 12714 NIG_MASK_XGXS0_LINK10G | 12715 NIG_MASK_SERDES0_LINK_STATUS | 12716 NIG_MASK_MI_INT)); 12717 12718 /* Activate nig drain */ 12719 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1); 12720 12721 /* Disable nig egress interface */ 12722 if (!CHIP_IS_E3(bp)) { 12723 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0); 12724 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0); 12725 } 12726 12727 if (!CHIP_IS_E3(bp)) { 12728 bnx2x_set_bmac_rx(bp, params->chip_id, port, 0); 12729 } else { 12730 bnx2x_set_xmac_rxtx(params, 0); 12731 bnx2x_set_umac_rxtx(params, 0); 12732 } 12733 /* Disable emac */ 12734 if (!CHIP_IS_E3(bp)) 12735 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0); 12736 12737 usleep_range(10000, 20000); 12738 /* The PHY reset is controlled by GPIO 1 12739 * Hold it as vars low 12740 */ 12741 /* Clear link led */ 12742 bnx2x_set_mdio_emac_per_phy(bp, params); 12743 bnx2x_set_led(params, vars, LED_MODE_OFF, 0); 12744 12745 if (reset_ext_phy) { 12746 for (phy_index = EXT_PHY1; phy_index < params->num_phys; 12747 phy_index++) { 12748 if (params->phy[phy_index].link_reset) { 12749 bnx2x_set_aer_mmd(params, 12750 ¶ms->phy[phy_index]); 12751 params->phy[phy_index].link_reset( 12752 ¶ms->phy[phy_index], 12753 params); 12754 } 12755 if (params->phy[phy_index].flags & 12756 FLAGS_REARM_LATCH_SIGNAL) 12757 clear_latch_ind = 1; 12758 } 12759 } 12760 12761 if (clear_latch_ind) { 12762 /* Clear latching indication */ 12763 bnx2x_rearm_latch_signal(bp, port, 0); 12764 bnx2x_bits_dis(bp, NIG_REG_LATCH_BC_0 + port*4, 12765 1 << NIG_LATCH_BC_ENABLE_MI_INT); 12766 } 12767 if (params->phy[INT_PHY].link_reset) 12768 params->phy[INT_PHY].link_reset( 12769 ¶ms->phy[INT_PHY], params); 12770 12771 /* Disable nig ingress interface */ 12772 if (!CHIP_IS_E3(bp)) { 12773 /* Reset BigMac */ 12774 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 12775 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); 12776 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0); 12777 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0); 12778 } else { 12779 u32 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; 12780 bnx2x_set_xumac_nig(params, 0, 0); 12781 if (REG_RD(bp, MISC_REG_RESET_REG_2) & 12782 MISC_REGISTERS_RESET_REG_2_XMAC) 12783 REG_WR(bp, xmac_base + XMAC_REG_CTRL, 12784 XMAC_CTRL_REG_SOFT_RESET); 12785 } 12786 vars->link_up = 0; 12787 vars->phy_flags = 0; 12788 return 0; 12789 } 12790 int bnx2x_lfa_reset(struct link_params *params, 12791 struct link_vars *vars) 12792 { 12793 struct bnx2x *bp = params->bp; 12794 vars->link_up = 0; 12795 vars->phy_flags = 0; 12796 params->link_flags &= ~PHY_INITIALIZED; 12797 if (!params->lfa_base) 12798 return bnx2x_link_reset(params, vars, 1); 12799 /* 12800 * Activate NIG drain so that during this time the device won't send 12801 * anything while it is unable to response. 12802 */ 12803 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1); 12804 12805 /* 12806 * Close gracefully the gate from BMAC to NIG such that no half packets 12807 * are passed. 12808 */ 12809 if (!CHIP_IS_E3(bp)) 12810 bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 0); 12811 12812 if (CHIP_IS_E3(bp)) { 12813 bnx2x_set_xmac_rxtx(params, 0); 12814 bnx2x_set_umac_rxtx(params, 0); 12815 } 12816 /* Wait 10ms for the pipe to clean up*/ 12817 usleep_range(10000, 20000); 12818 12819 /* Clean the NIG-BRB using the network filters in a way that will 12820 * not cut a packet in the middle. 12821 */ 12822 bnx2x_set_rx_filter(params, 0); 12823 12824 /* 12825 * Re-open the gate between the BMAC and the NIG, after verifying the 12826 * gate to the BRB is closed, otherwise packets may arrive to the 12827 * firmware before driver had initialized it. The target is to achieve 12828 * minimum management protocol down time. 12829 */ 12830 if (!CHIP_IS_E3(bp)) 12831 bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 1); 12832 12833 if (CHIP_IS_E3(bp)) { 12834 bnx2x_set_xmac_rxtx(params, 1); 12835 bnx2x_set_umac_rxtx(params, 1); 12836 } 12837 /* Disable NIG drain */ 12838 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); 12839 return 0; 12840 } 12841 12842 /****************************************************************************/ 12843 /* Common function */ 12844 /****************************************************************************/ 12845 static int bnx2x_8073_common_init_phy(struct bnx2x *bp, 12846 u32 shmem_base_path[], 12847 u32 shmem2_base_path[], u8 phy_index, 12848 u32 chip_id) 12849 { 12850 struct bnx2x_phy phy[PORT_MAX]; 12851 struct bnx2x_phy *phy_blk[PORT_MAX]; 12852 u16 val; 12853 s8 port = 0; 12854 s8 port_of_path = 0; 12855 u32 swap_val, swap_override; 12856 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); 12857 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); 12858 port ^= (swap_val && swap_override); 12859 bnx2x_ext_phy_hw_reset(bp, port); 12860 /* PART1 - Reset both phys */ 12861 for (port = PORT_MAX - 1; port >= PORT_0; port--) { 12862 u32 shmem_base, shmem2_base; 12863 /* In E2, same phy is using for port0 of the two paths */ 12864 if (CHIP_IS_E1x(bp)) { 12865 shmem_base = shmem_base_path[0]; 12866 shmem2_base = shmem2_base_path[0]; 12867 port_of_path = port; 12868 } else { 12869 shmem_base = shmem_base_path[port]; 12870 shmem2_base = shmem2_base_path[port]; 12871 port_of_path = 0; 12872 } 12873 12874 /* Extract the ext phy address for the port */ 12875 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base, 12876 port_of_path, &phy[port]) != 12877 0) { 12878 DP(NETIF_MSG_LINK, "populate_phy failed\n"); 12879 return -EINVAL; 12880 } 12881 /* Disable attentions */ 12882 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + 12883 port_of_path*4, 12884 (NIG_MASK_XGXS0_LINK_STATUS | 12885 NIG_MASK_XGXS0_LINK10G | 12886 NIG_MASK_SERDES0_LINK_STATUS | 12887 NIG_MASK_MI_INT)); 12888 12889 /* Need to take the phy out of low power mode in order 12890 * to write to access its registers 12891 */ 12892 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 12893 MISC_REGISTERS_GPIO_OUTPUT_HIGH, 12894 port); 12895 12896 /* Reset the phy */ 12897 bnx2x_cl45_write(bp, &phy[port], 12898 MDIO_PMA_DEVAD, 12899 MDIO_PMA_REG_CTRL, 12900 1<<15); 12901 } 12902 12903 /* Add delay of 150ms after reset */ 12904 msleep(150); 12905 12906 if (phy[PORT_0].addr & 0x1) { 12907 phy_blk[PORT_0] = &(phy[PORT_1]); 12908 phy_blk[PORT_1] = &(phy[PORT_0]); 12909 } else { 12910 phy_blk[PORT_0] = &(phy[PORT_0]); 12911 phy_blk[PORT_1] = &(phy[PORT_1]); 12912 } 12913 12914 /* PART2 - Download firmware to both phys */ 12915 for (port = PORT_MAX - 1; port >= PORT_0; port--) { 12916 if (CHIP_IS_E1x(bp)) 12917 port_of_path = port; 12918 else 12919 port_of_path = 0; 12920 12921 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n", 12922 phy_blk[port]->addr); 12923 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port], 12924 port_of_path)) 12925 return -EINVAL; 12926 12927 /* Only set bit 10 = 1 (Tx power down) */ 12928 bnx2x_cl45_read(bp, phy_blk[port], 12929 MDIO_PMA_DEVAD, 12930 MDIO_PMA_REG_TX_POWER_DOWN, &val); 12931 12932 /* Phase1 of TX_POWER_DOWN reset */ 12933 bnx2x_cl45_write(bp, phy_blk[port], 12934 MDIO_PMA_DEVAD, 12935 MDIO_PMA_REG_TX_POWER_DOWN, 12936 (val | 1<<10)); 12937 } 12938 12939 /* Toggle Transmitter: Power down and then up with 600ms delay 12940 * between 12941 */ 12942 msleep(600); 12943 12944 /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */ 12945 for (port = PORT_MAX - 1; port >= PORT_0; port--) { 12946 /* Phase2 of POWER_DOWN_RESET */ 12947 /* Release bit 10 (Release Tx power down) */ 12948 bnx2x_cl45_read(bp, phy_blk[port], 12949 MDIO_PMA_DEVAD, 12950 MDIO_PMA_REG_TX_POWER_DOWN, &val); 12951 12952 bnx2x_cl45_write(bp, phy_blk[port], 12953 MDIO_PMA_DEVAD, 12954 MDIO_PMA_REG_TX_POWER_DOWN, (val & (~(1<<10)))); 12955 usleep_range(15000, 30000); 12956 12957 /* Read modify write the SPI-ROM version select register */ 12958 bnx2x_cl45_read(bp, phy_blk[port], 12959 MDIO_PMA_DEVAD, 12960 MDIO_PMA_REG_EDC_FFE_MAIN, &val); 12961 bnx2x_cl45_write(bp, phy_blk[port], 12962 MDIO_PMA_DEVAD, 12963 MDIO_PMA_REG_EDC_FFE_MAIN, (val | (1<<12))); 12964 12965 /* set GPIO2 back to LOW */ 12966 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 12967 MISC_REGISTERS_GPIO_OUTPUT_LOW, port); 12968 } 12969 return 0; 12970 } 12971 static int bnx2x_8726_common_init_phy(struct bnx2x *bp, 12972 u32 shmem_base_path[], 12973 u32 shmem2_base_path[], u8 phy_index, 12974 u32 chip_id) 12975 { 12976 u32 val; 12977 s8 port; 12978 struct bnx2x_phy phy; 12979 /* Use port1 because of the static port-swap */ 12980 /* Enable the module detection interrupt */ 12981 val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN); 12982 val |= ((1<<MISC_REGISTERS_GPIO_3)| 12983 (1<<(MISC_REGISTERS_GPIO_3 + MISC_REGISTERS_GPIO_PORT_SHIFT))); 12984 REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val); 12985 12986 bnx2x_ext_phy_hw_reset(bp, 0); 12987 usleep_range(5000, 10000); 12988 for (port = 0; port < PORT_MAX; port++) { 12989 u32 shmem_base, shmem2_base; 12990 12991 /* In E2, same phy is using for port0 of the two paths */ 12992 if (CHIP_IS_E1x(bp)) { 12993 shmem_base = shmem_base_path[0]; 12994 shmem2_base = shmem2_base_path[0]; 12995 } else { 12996 shmem_base = shmem_base_path[port]; 12997 shmem2_base = shmem2_base_path[port]; 12998 } 12999 /* Extract the ext phy address for the port */ 13000 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base, 13001 port, &phy) != 13002 0) { 13003 DP(NETIF_MSG_LINK, "populate phy failed\n"); 13004 return -EINVAL; 13005 } 13006 13007 /* Reset phy*/ 13008 bnx2x_cl45_write(bp, &phy, 13009 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001); 13010 13011 13012 /* Set fault module detected LED on */ 13013 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0, 13014 MISC_REGISTERS_GPIO_HIGH, 13015 port); 13016 } 13017 13018 return 0; 13019 } 13020 static void bnx2x_get_ext_phy_reset_gpio(struct bnx2x *bp, u32 shmem_base, 13021 u8 *io_gpio, u8 *io_port) 13022 { 13023 13024 u32 phy_gpio_reset = REG_RD(bp, shmem_base + 13025 offsetof(struct shmem_region, 13026 dev_info.port_hw_config[PORT_0].default_cfg)); 13027 switch (phy_gpio_reset) { 13028 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0: 13029 *io_gpio = 0; 13030 *io_port = 0; 13031 break; 13032 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0: 13033 *io_gpio = 1; 13034 *io_port = 0; 13035 break; 13036 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0: 13037 *io_gpio = 2; 13038 *io_port = 0; 13039 break; 13040 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0: 13041 *io_gpio = 3; 13042 *io_port = 0; 13043 break; 13044 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1: 13045 *io_gpio = 0; 13046 *io_port = 1; 13047 break; 13048 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1: 13049 *io_gpio = 1; 13050 *io_port = 1; 13051 break; 13052 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1: 13053 *io_gpio = 2; 13054 *io_port = 1; 13055 break; 13056 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1: 13057 *io_gpio = 3; 13058 *io_port = 1; 13059 break; 13060 default: 13061 /* Don't override the io_gpio and io_port */ 13062 break; 13063 } 13064 } 13065 13066 static int bnx2x_8727_common_init_phy(struct bnx2x *bp, 13067 u32 shmem_base_path[], 13068 u32 shmem2_base_path[], u8 phy_index, 13069 u32 chip_id) 13070 { 13071 s8 port, reset_gpio; 13072 u32 swap_val, swap_override; 13073 struct bnx2x_phy phy[PORT_MAX]; 13074 struct bnx2x_phy *phy_blk[PORT_MAX]; 13075 s8 port_of_path; 13076 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); 13077 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); 13078 13079 reset_gpio = MISC_REGISTERS_GPIO_1; 13080 port = 1; 13081 13082 /* Retrieve the reset gpio/port which control the reset. 13083 * Default is GPIO1, PORT1 13084 */ 13085 bnx2x_get_ext_phy_reset_gpio(bp, shmem_base_path[0], 13086 (u8 *)&reset_gpio, (u8 *)&port); 13087 13088 /* Calculate the port based on port swap */ 13089 port ^= (swap_val && swap_override); 13090 13091 /* Initiate PHY reset*/ 13092 bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_LOW, 13093 port); 13094 usleep_range(1000, 2000); 13095 bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_HIGH, 13096 port); 13097 13098 usleep_range(5000, 10000); 13099 13100 /* PART1 - Reset both phys */ 13101 for (port = PORT_MAX - 1; port >= PORT_0; port--) { 13102 u32 shmem_base, shmem2_base; 13103 13104 /* In E2, same phy is using for port0 of the two paths */ 13105 if (CHIP_IS_E1x(bp)) { 13106 shmem_base = shmem_base_path[0]; 13107 shmem2_base = shmem2_base_path[0]; 13108 port_of_path = port; 13109 } else { 13110 shmem_base = shmem_base_path[port]; 13111 shmem2_base = shmem2_base_path[port]; 13112 port_of_path = 0; 13113 } 13114 13115 /* Extract the ext phy address for the port */ 13116 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base, 13117 port_of_path, &phy[port]) != 13118 0) { 13119 DP(NETIF_MSG_LINK, "populate phy failed\n"); 13120 return -EINVAL; 13121 } 13122 /* disable attentions */ 13123 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + 13124 port_of_path*4, 13125 (NIG_MASK_XGXS0_LINK_STATUS | 13126 NIG_MASK_XGXS0_LINK10G | 13127 NIG_MASK_SERDES0_LINK_STATUS | 13128 NIG_MASK_MI_INT)); 13129 13130 13131 /* Reset the phy */ 13132 bnx2x_cl45_write(bp, &phy[port], 13133 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15); 13134 } 13135 13136 /* Add delay of 150ms after reset */ 13137 msleep(150); 13138 if (phy[PORT_0].addr & 0x1) { 13139 phy_blk[PORT_0] = &(phy[PORT_1]); 13140 phy_blk[PORT_1] = &(phy[PORT_0]); 13141 } else { 13142 phy_blk[PORT_0] = &(phy[PORT_0]); 13143 phy_blk[PORT_1] = &(phy[PORT_1]); 13144 } 13145 /* PART2 - Download firmware to both phys */ 13146 for (port = PORT_MAX - 1; port >= PORT_0; port--) { 13147 if (CHIP_IS_E1x(bp)) 13148 port_of_path = port; 13149 else 13150 port_of_path = 0; 13151 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n", 13152 phy_blk[port]->addr); 13153 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port], 13154 port_of_path)) 13155 return -EINVAL; 13156 /* Disable PHY transmitter output */ 13157 bnx2x_cl45_write(bp, phy_blk[port], 13158 MDIO_PMA_DEVAD, 13159 MDIO_PMA_REG_TX_DISABLE, 1); 13160 13161 } 13162 return 0; 13163 } 13164 13165 static int bnx2x_84833_common_init_phy(struct bnx2x *bp, 13166 u32 shmem_base_path[], 13167 u32 shmem2_base_path[], 13168 u8 phy_index, 13169 u32 chip_id) 13170 { 13171 u8 reset_gpios; 13172 reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path, chip_id); 13173 bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW); 13174 udelay(10); 13175 bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_HIGH); 13176 DP(NETIF_MSG_LINK, "84833 reset pulse on pin values 0x%x\n", 13177 reset_gpios); 13178 return 0; 13179 } 13180 13181 static int bnx2x_ext_phy_common_init(struct bnx2x *bp, u32 shmem_base_path[], 13182 u32 shmem2_base_path[], u8 phy_index, 13183 u32 ext_phy_type, u32 chip_id) 13184 { 13185 int rc = 0; 13186 13187 switch (ext_phy_type) { 13188 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073: 13189 rc = bnx2x_8073_common_init_phy(bp, shmem_base_path, 13190 shmem2_base_path, 13191 phy_index, chip_id); 13192 break; 13193 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722: 13194 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: 13195 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC: 13196 rc = bnx2x_8727_common_init_phy(bp, shmem_base_path, 13197 shmem2_base_path, 13198 phy_index, chip_id); 13199 break; 13200 13201 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: 13202 /* GPIO1 affects both ports, so there's need to pull 13203 * it for single port alone 13204 */ 13205 rc = bnx2x_8726_common_init_phy(bp, shmem_base_path, 13206 shmem2_base_path, 13207 phy_index, chip_id); 13208 break; 13209 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833: 13210 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834: 13211 /* GPIO3's are linked, and so both need to be toggled 13212 * to obtain required 2us pulse. 13213 */ 13214 rc = bnx2x_84833_common_init_phy(bp, shmem_base_path, 13215 shmem2_base_path, 13216 phy_index, chip_id); 13217 break; 13218 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE: 13219 rc = -EINVAL; 13220 break; 13221 default: 13222 DP(NETIF_MSG_LINK, 13223 "ext_phy 0x%x common init not required\n", 13224 ext_phy_type); 13225 break; 13226 } 13227 13228 if (rc) 13229 netdev_err(bp->dev, "Warning: PHY was not initialized," 13230 " Port %d\n", 13231 0); 13232 return rc; 13233 } 13234 13235 int bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base_path[], 13236 u32 shmem2_base_path[], u32 chip_id) 13237 { 13238 int rc = 0; 13239 u32 phy_ver, val; 13240 u8 phy_index = 0; 13241 u32 ext_phy_type, ext_phy_config; 13242 13243 bnx2x_set_mdio_clk(bp, chip_id, GRCBASE_EMAC0); 13244 bnx2x_set_mdio_clk(bp, chip_id, GRCBASE_EMAC1); 13245 DP(NETIF_MSG_LINK, "Begin common phy init\n"); 13246 if (CHIP_IS_E3(bp)) { 13247 /* Enable EPIO */ 13248 val = REG_RD(bp, MISC_REG_GEN_PURP_HWG); 13249 REG_WR(bp, MISC_REG_GEN_PURP_HWG, val | 1); 13250 } 13251 /* Check if common init was already done */ 13252 phy_ver = REG_RD(bp, shmem_base_path[0] + 13253 offsetof(struct shmem_region, 13254 port_mb[PORT_0].ext_phy_fw_version)); 13255 if (phy_ver) { 13256 DP(NETIF_MSG_LINK, "Not doing common init; phy ver is 0x%x\n", 13257 phy_ver); 13258 return 0; 13259 } 13260 13261 /* Read the ext_phy_type for arbitrary port(0) */ 13262 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS; 13263 phy_index++) { 13264 ext_phy_config = bnx2x_get_ext_phy_config(bp, 13265 shmem_base_path[0], 13266 phy_index, 0); 13267 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config); 13268 rc |= bnx2x_ext_phy_common_init(bp, shmem_base_path, 13269 shmem2_base_path, 13270 phy_index, ext_phy_type, 13271 chip_id); 13272 } 13273 return rc; 13274 } 13275 13276 static void bnx2x_check_over_curr(struct link_params *params, 13277 struct link_vars *vars) 13278 { 13279 struct bnx2x *bp = params->bp; 13280 u32 cfg_pin; 13281 u8 port = params->port; 13282 u32 pin_val; 13283 13284 cfg_pin = (REG_RD(bp, params->shmem_base + 13285 offsetof(struct shmem_region, 13286 dev_info.port_hw_config[port].e3_cmn_pin_cfg1)) & 13287 PORT_HW_CFG_E3_OVER_CURRENT_MASK) >> 13288 PORT_HW_CFG_E3_OVER_CURRENT_SHIFT; 13289 13290 /* Ignore check if no external input PIN available */ 13291 if (bnx2x_get_cfg_pin(bp, cfg_pin, &pin_val) != 0) 13292 return; 13293 13294 if (!pin_val) { 13295 if ((vars->phy_flags & PHY_OVER_CURRENT_FLAG) == 0) { 13296 netdev_err(bp->dev, "Error: Power fault on Port %d has" 13297 " been detected and the power to " 13298 "that SFP+ module has been removed" 13299 " to prevent failure of the card." 13300 " Please remove the SFP+ module and" 13301 " restart the system to clear this" 13302 " error.\n", 13303 params->port); 13304 vars->phy_flags |= PHY_OVER_CURRENT_FLAG; 13305 bnx2x_warpcore_power_module(params, 0); 13306 } 13307 } else 13308 vars->phy_flags &= ~PHY_OVER_CURRENT_FLAG; 13309 } 13310 13311 /* Returns 0 if no change occured since last check; 1 otherwise. */ 13312 static u8 bnx2x_analyze_link_error(struct link_params *params, 13313 struct link_vars *vars, u32 status, 13314 u32 phy_flag, u32 link_flag, u8 notify) 13315 { 13316 struct bnx2x *bp = params->bp; 13317 /* Compare new value with previous value */ 13318 u8 led_mode; 13319 u32 old_status = (vars->phy_flags & phy_flag) ? 1 : 0; 13320 13321 if ((status ^ old_status) == 0) 13322 return 0; 13323 13324 /* If values differ */ 13325 switch (phy_flag) { 13326 case PHY_HALF_OPEN_CONN_FLAG: 13327 DP(NETIF_MSG_LINK, "Analyze Remote Fault\n"); 13328 break; 13329 case PHY_SFP_TX_FAULT_FLAG: 13330 DP(NETIF_MSG_LINK, "Analyze TX Fault\n"); 13331 break; 13332 default: 13333 DP(NETIF_MSG_LINK, "Analyze UNKNOWN\n"); 13334 } 13335 DP(NETIF_MSG_LINK, "Link changed:[%x %x]->%x\n", vars->link_up, 13336 old_status, status); 13337 13338 /* Do not touch the link in case physical link down */ 13339 if ((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0) 13340 return 1; 13341 13342 /* a. Update shmem->link_status accordingly 13343 * b. Update link_vars->link_up 13344 */ 13345 if (status) { 13346 vars->link_status &= ~LINK_STATUS_LINK_UP; 13347 vars->link_status |= link_flag; 13348 vars->link_up = 0; 13349 vars->phy_flags |= phy_flag; 13350 13351 /* activate nig drain */ 13352 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1); 13353 /* Set LED mode to off since the PHY doesn't know about these 13354 * errors 13355 */ 13356 led_mode = LED_MODE_OFF; 13357 } else { 13358 vars->link_status |= LINK_STATUS_LINK_UP; 13359 vars->link_status &= ~link_flag; 13360 vars->link_up = 1; 13361 vars->phy_flags &= ~phy_flag; 13362 led_mode = LED_MODE_OPER; 13363 13364 /* Clear nig drain */ 13365 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); 13366 } 13367 bnx2x_sync_link(params, vars); 13368 /* Update the LED according to the link state */ 13369 bnx2x_set_led(params, vars, led_mode, SPEED_10000); 13370 13371 /* Update link status in the shared memory */ 13372 bnx2x_update_mng(params, vars->link_status); 13373 13374 /* C. Trigger General Attention */ 13375 vars->periodic_flags |= PERIODIC_FLAGS_LINK_EVENT; 13376 if (notify) 13377 bnx2x_notify_link_changed(bp); 13378 13379 return 1; 13380 } 13381 13382 /****************************************************************************** 13383 * Description: 13384 * This function checks for half opened connection change indication. 13385 * When such change occurs, it calls the bnx2x_analyze_link_error 13386 * to check if Remote Fault is set or cleared. Reception of remote fault 13387 * status message in the MAC indicates that the peer's MAC has detected 13388 * a fault, for example, due to break in the TX side of fiber. 13389 * 13390 ******************************************************************************/ 13391 static int bnx2x_check_half_open_conn(struct link_params *params, 13392 struct link_vars *vars, 13393 u8 notify) 13394 { 13395 struct bnx2x *bp = params->bp; 13396 u32 lss_status = 0; 13397 u32 mac_base; 13398 /* In case link status is physically up @ 10G do */ 13399 if (((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0) || 13400 (REG_RD(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4))) 13401 return 0; 13402 13403 if (CHIP_IS_E3(bp) && 13404 (REG_RD(bp, MISC_REG_RESET_REG_2) & 13405 (MISC_REGISTERS_RESET_REG_2_XMAC))) { 13406 /* Check E3 XMAC */ 13407 /* Note that link speed cannot be queried here, since it may be 13408 * zero while link is down. In case UMAC is active, LSS will 13409 * simply not be set 13410 */ 13411 mac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; 13412 13413 /* Clear stick bits (Requires rising edge) */ 13414 REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0); 13415 REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 13416 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS | 13417 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS); 13418 if (REG_RD(bp, mac_base + XMAC_REG_RX_LSS_STATUS)) 13419 lss_status = 1; 13420 13421 bnx2x_analyze_link_error(params, vars, lss_status, 13422 PHY_HALF_OPEN_CONN_FLAG, 13423 LINK_STATUS_NONE, notify); 13424 } else if (REG_RD(bp, MISC_REG_RESET_REG_2) & 13425 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port)) { 13426 /* Check E1X / E2 BMAC */ 13427 u32 lss_status_reg; 13428 u32 wb_data[2]; 13429 mac_base = params->port ? NIG_REG_INGRESS_BMAC1_MEM : 13430 NIG_REG_INGRESS_BMAC0_MEM; 13431 /* Read BIGMAC_REGISTER_RX_LSS_STATUS */ 13432 if (CHIP_IS_E2(bp)) 13433 lss_status_reg = BIGMAC2_REGISTER_RX_LSS_STAT; 13434 else 13435 lss_status_reg = BIGMAC_REGISTER_RX_LSS_STATUS; 13436 13437 REG_RD_DMAE(bp, mac_base + lss_status_reg, wb_data, 2); 13438 lss_status = (wb_data[0] > 0); 13439 13440 bnx2x_analyze_link_error(params, vars, lss_status, 13441 PHY_HALF_OPEN_CONN_FLAG, 13442 LINK_STATUS_NONE, notify); 13443 } 13444 return 0; 13445 } 13446 static void bnx2x_sfp_tx_fault_detection(struct bnx2x_phy *phy, 13447 struct link_params *params, 13448 struct link_vars *vars) 13449 { 13450 struct bnx2x *bp = params->bp; 13451 u32 cfg_pin, value = 0; 13452 u8 led_change, port = params->port; 13453 13454 /* Get The SFP+ TX_Fault controlling pin ([eg]pio) */ 13455 cfg_pin = (REG_RD(bp, params->shmem_base + offsetof(struct shmem_region, 13456 dev_info.port_hw_config[port].e3_cmn_pin_cfg)) & 13457 PORT_HW_CFG_E3_TX_FAULT_MASK) >> 13458 PORT_HW_CFG_E3_TX_FAULT_SHIFT; 13459 13460 if (bnx2x_get_cfg_pin(bp, cfg_pin, &value)) { 13461 DP(NETIF_MSG_LINK, "Failed to read pin 0x%02x\n", cfg_pin); 13462 return; 13463 } 13464 13465 led_change = bnx2x_analyze_link_error(params, vars, value, 13466 PHY_SFP_TX_FAULT_FLAG, 13467 LINK_STATUS_SFP_TX_FAULT, 1); 13468 13469 if (led_change) { 13470 /* Change TX_Fault led, set link status for further syncs */ 13471 u8 led_mode; 13472 13473 if (vars->phy_flags & PHY_SFP_TX_FAULT_FLAG) { 13474 led_mode = MISC_REGISTERS_GPIO_HIGH; 13475 vars->link_status |= LINK_STATUS_SFP_TX_FAULT; 13476 } else { 13477 led_mode = MISC_REGISTERS_GPIO_LOW; 13478 vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT; 13479 } 13480 13481 /* If module is unapproved, led should be on regardless */ 13482 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED)) { 13483 DP(NETIF_MSG_LINK, "Change TX_Fault LED: ->%x\n", 13484 led_mode); 13485 bnx2x_set_e3_module_fault_led(params, led_mode); 13486 } 13487 } 13488 } 13489 static void bnx2x_kr2_recovery(struct link_params *params, 13490 struct link_vars *vars, 13491 struct bnx2x_phy *phy) 13492 { 13493 struct bnx2x *bp = params->bp; 13494 DP(NETIF_MSG_LINK, "KR2 recovery\n"); 13495 bnx2x_warpcore_enable_AN_KR2(phy, params, vars); 13496 bnx2x_warpcore_restart_AN_KR(phy, params); 13497 } 13498 13499 static void bnx2x_check_kr2_wa(struct link_params *params, 13500 struct link_vars *vars, 13501 struct bnx2x_phy *phy) 13502 { 13503 struct bnx2x *bp = params->bp; 13504 u16 base_page, next_page, not_kr2_device, lane; 13505 int sigdet; 13506 13507 /* Once KR2 was disabled, wait 5 seconds before checking KR2 recovery 13508 * Since some switches tend to reinit the AN process and clear the 13509 * the advertised BP/NP after ~2 seconds causing the KR2 to be disabled 13510 * and recovered many times 13511 */ 13512 if (vars->check_kr2_recovery_cnt > 0) { 13513 vars->check_kr2_recovery_cnt--; 13514 return; 13515 } 13516 13517 sigdet = bnx2x_warpcore_get_sigdet(phy, params); 13518 if (!sigdet) { 13519 if (!(params->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) { 13520 bnx2x_kr2_recovery(params, vars, phy); 13521 DP(NETIF_MSG_LINK, "No sigdet\n"); 13522 } 13523 return; 13524 } 13525 13526 lane = bnx2x_get_warpcore_lane(phy, params); 13527 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, 13528 MDIO_AER_BLOCK_AER_REG, lane); 13529 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, 13530 MDIO_AN_REG_LP_AUTO_NEG, &base_page); 13531 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, 13532 MDIO_AN_REG_LP_AUTO_NEG2, &next_page); 13533 bnx2x_set_aer_mmd(params, phy); 13534 13535 /* CL73 has not begun yet */ 13536 if (base_page == 0) { 13537 if (!(params->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) { 13538 bnx2x_kr2_recovery(params, vars, phy); 13539 DP(NETIF_MSG_LINK, "No BP\n"); 13540 } 13541 return; 13542 } 13543 13544 /* In case NP bit is not set in the BasePage, or it is set, 13545 * but only KX is advertised, declare this link partner as non-KR2 13546 * device. 13547 */ 13548 not_kr2_device = (((base_page & 0x8000) == 0) || 13549 (((base_page & 0x8000) && 13550 ((next_page & 0xe0) == 0x20)))); 13551 13552 /* In case KR2 is already disabled, check if we need to re-enable it */ 13553 if (!(params->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) { 13554 if (!not_kr2_device) { 13555 DP(NETIF_MSG_LINK, "BP=0x%x, NP=0x%x\n", base_page, 13556 next_page); 13557 bnx2x_kr2_recovery(params, vars, phy); 13558 } 13559 return; 13560 } 13561 /* KR2 is enabled, but not KR2 device */ 13562 if (not_kr2_device) { 13563 /* Disable KR2 on both lanes */ 13564 DP(NETIF_MSG_LINK, "BP=0x%x, NP=0x%x\n", base_page, next_page); 13565 bnx2x_disable_kr2(params, vars, phy); 13566 /* Restart AN on leading lane */ 13567 bnx2x_warpcore_restart_AN_KR(phy, params); 13568 return; 13569 } 13570 } 13571 13572 void bnx2x_period_func(struct link_params *params, struct link_vars *vars) 13573 { 13574 u16 phy_idx; 13575 struct bnx2x *bp = params->bp; 13576 for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) { 13577 if (params->phy[phy_idx].flags & FLAGS_TX_ERROR_CHECK) { 13578 bnx2x_set_aer_mmd(params, ¶ms->phy[phy_idx]); 13579 if (bnx2x_check_half_open_conn(params, vars, 1) != 13580 0) 13581 DP(NETIF_MSG_LINK, "Fault detection failed\n"); 13582 break; 13583 } 13584 } 13585 13586 if (CHIP_IS_E3(bp)) { 13587 struct bnx2x_phy *phy = ¶ms->phy[INT_PHY]; 13588 bnx2x_set_aer_mmd(params, phy); 13589 if ((phy->supported & SUPPORTED_20000baseKR2_Full) && 13590 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) 13591 bnx2x_check_kr2_wa(params, vars, phy); 13592 bnx2x_check_over_curr(params, vars); 13593 if (vars->rx_tx_asic_rst) 13594 bnx2x_warpcore_config_runtime(phy, params, vars); 13595 13596 if ((REG_RD(bp, params->shmem_base + 13597 offsetof(struct shmem_region, dev_info. 13598 port_hw_config[params->port].default_cfg)) 13599 & PORT_HW_CFG_NET_SERDES_IF_MASK) == 13600 PORT_HW_CFG_NET_SERDES_IF_SFI) { 13601 if (bnx2x_is_sfp_module_plugged(phy, params)) { 13602 bnx2x_sfp_tx_fault_detection(phy, params, vars); 13603 } else if (vars->link_status & 13604 LINK_STATUS_SFP_TX_FAULT) { 13605 /* Clean trail, interrupt corrects the leds */ 13606 vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT; 13607 vars->phy_flags &= ~PHY_SFP_TX_FAULT_FLAG; 13608 /* Update link status in the shared memory */ 13609 bnx2x_update_mng(params, vars->link_status); 13610 } 13611 } 13612 } 13613 } 13614 13615 u8 bnx2x_fan_failure_det_req(struct bnx2x *bp, 13616 u32 shmem_base, 13617 u32 shmem2_base, 13618 u8 port) 13619 { 13620 u8 phy_index, fan_failure_det_req = 0; 13621 struct bnx2x_phy phy; 13622 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS; 13623 phy_index++) { 13624 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base, 13625 port, &phy) 13626 != 0) { 13627 DP(NETIF_MSG_LINK, "populate phy failed\n"); 13628 return 0; 13629 } 13630 fan_failure_det_req |= (phy.flags & 13631 FLAGS_FAN_FAILURE_DET_REQ); 13632 } 13633 return fan_failure_det_req; 13634 } 13635 13636 void bnx2x_hw_reset_phy(struct link_params *params) 13637 { 13638 u8 phy_index; 13639 struct bnx2x *bp = params->bp; 13640 bnx2x_update_mng(params, 0); 13641 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4, 13642 (NIG_MASK_XGXS0_LINK_STATUS | 13643 NIG_MASK_XGXS0_LINK10G | 13644 NIG_MASK_SERDES0_LINK_STATUS | 13645 NIG_MASK_MI_INT)); 13646 13647 for (phy_index = INT_PHY; phy_index < MAX_PHYS; 13648 phy_index++) { 13649 if (params->phy[phy_index].hw_reset) { 13650 params->phy[phy_index].hw_reset( 13651 ¶ms->phy[phy_index], 13652 params); 13653 params->phy[phy_index] = phy_null; 13654 } 13655 } 13656 } 13657 13658 void bnx2x_init_mod_abs_int(struct bnx2x *bp, struct link_vars *vars, 13659 u32 chip_id, u32 shmem_base, u32 shmem2_base, 13660 u8 port) 13661 { 13662 u8 gpio_num = 0xff, gpio_port = 0xff, phy_index; 13663 u32 val; 13664 u32 offset, aeu_mask, swap_val, swap_override, sync_offset; 13665 if (CHIP_IS_E3(bp)) { 13666 if (bnx2x_get_mod_abs_int_cfg(bp, chip_id, 13667 shmem_base, 13668 port, 13669 &gpio_num, 13670 &gpio_port) != 0) 13671 return; 13672 } else { 13673 struct bnx2x_phy phy; 13674 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS; 13675 phy_index++) { 13676 if (bnx2x_populate_phy(bp, phy_index, shmem_base, 13677 shmem2_base, port, &phy) 13678 != 0) { 13679 DP(NETIF_MSG_LINK, "populate phy failed\n"); 13680 return; 13681 } 13682 if (phy.type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) { 13683 gpio_num = MISC_REGISTERS_GPIO_3; 13684 gpio_port = port; 13685 break; 13686 } 13687 } 13688 } 13689 13690 if (gpio_num == 0xff) 13691 return; 13692 13693 /* Set GPIO3 to trigger SFP+ module insertion/removal */ 13694 bnx2x_set_gpio(bp, gpio_num, MISC_REGISTERS_GPIO_INPUT_HI_Z, gpio_port); 13695 13696 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); 13697 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); 13698 gpio_port ^= (swap_val && swap_override); 13699 13700 vars->aeu_int_mask = AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 << 13701 (gpio_num + (gpio_port << 2)); 13702 13703 sync_offset = shmem_base + 13704 offsetof(struct shmem_region, 13705 dev_info.port_hw_config[port].aeu_int_mask); 13706 REG_WR(bp, sync_offset, vars->aeu_int_mask); 13707 13708 DP(NETIF_MSG_LINK, "Setting MOD_ABS (GPIO%d_P%d) AEU to 0x%x\n", 13709 gpio_num, gpio_port, vars->aeu_int_mask); 13710 13711 if (port == 0) 13712 offset = MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0; 13713 else 13714 offset = MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0; 13715 13716 /* Open appropriate AEU for interrupts */ 13717 aeu_mask = REG_RD(bp, offset); 13718 aeu_mask |= vars->aeu_int_mask; 13719 REG_WR(bp, offset, aeu_mask); 13720 13721 /* Enable the GPIO to trigger interrupt */ 13722 val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN); 13723 val |= 1 << (gpio_num + (gpio_port << 2)); 13724 REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val); 13725 } 13726