1 /* Copyright 2008-2013 Broadcom Corporation 2 * 3 * Unless you and Broadcom execute a separate written software license 4 * agreement governing use of this software, this software is licensed to you 5 * under the terms of the GNU General Public License version 2, available 6 * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL"). 7 * 8 * Notwithstanding the above, under no circumstances may you combine this 9 * software in any way with any other Broadcom software provided under a 10 * license other than the GPL, without Broadcom's express prior written 11 * consent. 12 * 13 * Written by Yaniv Rosner 14 * 15 */ 16 17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 18 19 #include <linux/kernel.h> 20 #include <linux/errno.h> 21 #include <linux/pci.h> 22 #include <linux/netdevice.h> 23 #include <linux/delay.h> 24 #include <linux/ethtool.h> 25 #include <linux/mutex.h> 26 27 #include "bnx2x.h" 28 #include "bnx2x_cmn.h" 29 30 typedef int (*read_sfp_module_eeprom_func_p)(struct bnx2x_phy *phy, 31 struct link_params *params, 32 u8 dev_addr, u16 addr, u8 byte_cnt, 33 u8 *o_buf, u8); 34 /********************************************************/ 35 #define ETH_HLEN 14 36 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */ 37 #define ETH_OVREHEAD (ETH_HLEN + 8 + 8) 38 #define ETH_MIN_PACKET_SIZE 60 39 #define ETH_MAX_PACKET_SIZE 1500 40 #define ETH_MAX_JUMBO_PACKET_SIZE 9600 41 #define MDIO_ACCESS_TIMEOUT 1000 42 #define WC_LANE_MAX 4 43 #define I2C_SWITCH_WIDTH 2 44 #define I2C_BSC0 0 45 #define I2C_BSC1 1 46 #define I2C_WA_RETRY_CNT 3 47 #define I2C_WA_PWR_ITER (I2C_WA_RETRY_CNT - 1) 48 #define MCPR_IMC_COMMAND_READ_OP 1 49 #define MCPR_IMC_COMMAND_WRITE_OP 2 50 51 /* LED Blink rate that will achieve ~15.9Hz */ 52 #define LED_BLINK_RATE_VAL_E3 354 53 #define LED_BLINK_RATE_VAL_E1X_E2 480 54 /***********************************************************/ 55 /* Shortcut definitions */ 56 /***********************************************************/ 57 58 #define NIG_LATCH_BC_ENABLE_MI_INT 0 59 60 #define NIG_STATUS_EMAC0_MI_INT \ 61 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT 62 #define NIG_STATUS_XGXS0_LINK10G \ 63 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G 64 #define NIG_STATUS_XGXS0_LINK_STATUS \ 65 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS 66 #define NIG_STATUS_XGXS0_LINK_STATUS_SIZE \ 67 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE 68 #define NIG_STATUS_SERDES0_LINK_STATUS \ 69 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS 70 #define NIG_MASK_MI_INT \ 71 NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT 72 #define NIG_MASK_XGXS0_LINK10G \ 73 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G 74 #define NIG_MASK_XGXS0_LINK_STATUS \ 75 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS 76 #define NIG_MASK_SERDES0_LINK_STATUS \ 77 NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS 78 79 #define MDIO_AN_CL73_OR_37_COMPLETE \ 80 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \ 81 MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE) 82 83 #define XGXS_RESET_BITS \ 84 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW | \ 85 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ | \ 86 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN | \ 87 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \ 88 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB) 89 90 #define SERDES_RESET_BITS \ 91 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \ 92 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ | \ 93 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN | \ 94 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD) 95 96 #define AUTONEG_CL37 SHARED_HW_CFG_AN_ENABLE_CL37 97 #define AUTONEG_CL73 SHARED_HW_CFG_AN_ENABLE_CL73 98 #define AUTONEG_BAM SHARED_HW_CFG_AN_ENABLE_BAM 99 #define AUTONEG_PARALLEL \ 100 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION 101 #define AUTONEG_SGMII_FIBER_AUTODET \ 102 SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT 103 #define AUTONEG_REMOTE_PHY SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY 104 105 #define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \ 106 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE 107 #define GP_STATUS_PAUSE_RSOLUTION_RXSIDE \ 108 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE 109 #define GP_STATUS_SPEED_MASK \ 110 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK 111 #define GP_STATUS_10M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M 112 #define GP_STATUS_100M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M 113 #define GP_STATUS_1G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G 114 #define GP_STATUS_2_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G 115 #define GP_STATUS_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G 116 #define GP_STATUS_6G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G 117 #define GP_STATUS_10G_HIG \ 118 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG 119 #define GP_STATUS_10G_CX4 \ 120 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4 121 #define GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX 122 #define GP_STATUS_10G_KX4 \ 123 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4 124 #define GP_STATUS_10G_KR MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR 125 #define GP_STATUS_10G_XFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI 126 #define GP_STATUS_20G_DXGXS MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS 127 #define GP_STATUS_10G_SFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI 128 #define GP_STATUS_20G_KR2 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_KR2 129 #define LINK_10THD LINK_STATUS_SPEED_AND_DUPLEX_10THD 130 #define LINK_10TFD LINK_STATUS_SPEED_AND_DUPLEX_10TFD 131 #define LINK_100TXHD LINK_STATUS_SPEED_AND_DUPLEX_100TXHD 132 #define LINK_100T4 LINK_STATUS_SPEED_AND_DUPLEX_100T4 133 #define LINK_100TXFD LINK_STATUS_SPEED_AND_DUPLEX_100TXFD 134 #define LINK_1000THD LINK_STATUS_SPEED_AND_DUPLEX_1000THD 135 #define LINK_1000TFD LINK_STATUS_SPEED_AND_DUPLEX_1000TFD 136 #define LINK_1000XFD LINK_STATUS_SPEED_AND_DUPLEX_1000XFD 137 #define LINK_2500THD LINK_STATUS_SPEED_AND_DUPLEX_2500THD 138 #define LINK_2500TFD LINK_STATUS_SPEED_AND_DUPLEX_2500TFD 139 #define LINK_2500XFD LINK_STATUS_SPEED_AND_DUPLEX_2500XFD 140 #define LINK_10GTFD LINK_STATUS_SPEED_AND_DUPLEX_10GTFD 141 #define LINK_10GXFD LINK_STATUS_SPEED_AND_DUPLEX_10GXFD 142 #define LINK_20GTFD LINK_STATUS_SPEED_AND_DUPLEX_20GTFD 143 #define LINK_20GXFD LINK_STATUS_SPEED_AND_DUPLEX_20GXFD 144 145 #define LINK_UPDATE_MASK \ 146 (LINK_STATUS_SPEED_AND_DUPLEX_MASK | \ 147 LINK_STATUS_LINK_UP | \ 148 LINK_STATUS_PHYSICAL_LINK_FLAG | \ 149 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE | \ 150 LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK | \ 151 LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK | \ 152 LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK | \ 153 LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE | \ 154 LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE) 155 156 #define SFP_EEPROM_CON_TYPE_ADDR 0x2 157 #define SFP_EEPROM_CON_TYPE_VAL_LC 0x7 158 #define SFP_EEPROM_CON_TYPE_VAL_COPPER 0x21 159 #define SFP_EEPROM_CON_TYPE_VAL_RJ45 0x22 160 161 162 #define SFP_EEPROM_COMP_CODE_ADDR 0x3 163 #define SFP_EEPROM_COMP_CODE_SR_MASK (1<<4) 164 #define SFP_EEPROM_COMP_CODE_LR_MASK (1<<5) 165 #define SFP_EEPROM_COMP_CODE_LRM_MASK (1<<6) 166 167 #define SFP_EEPROM_FC_TX_TECH_ADDR 0x8 168 #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4 169 #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE 0x8 170 171 #define SFP_EEPROM_OPTIONS_ADDR 0x40 172 #define SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1 173 #define SFP_EEPROM_OPTIONS_SIZE 2 174 175 #define EDC_MODE_LINEAR 0x0022 176 #define EDC_MODE_LIMITING 0x0044 177 #define EDC_MODE_PASSIVE_DAC 0x0055 178 #define EDC_MODE_ACTIVE_DAC 0x0066 179 180 /* ETS defines*/ 181 #define DCBX_INVALID_COS (0xFF) 182 183 #define ETS_BW_LIMIT_CREDIT_UPPER_BOUND (0x5000) 184 #define ETS_BW_LIMIT_CREDIT_WEIGHT (0x5000) 185 #define ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS (1360) 186 #define ETS_E3B0_NIG_MIN_W_VAL_20GBPS (2720) 187 #define ETS_E3B0_PBF_MIN_W_VAL (10000) 188 189 #define MAX_PACKET_SIZE (9700) 190 #define MAX_KR_LINK_RETRY 4 191 192 /**********************************************************/ 193 /* INTERFACE */ 194 /**********************************************************/ 195 196 #define CL22_WR_OVER_CL45(_bp, _phy, _bank, _addr, _val) \ 197 bnx2x_cl45_write(_bp, _phy, \ 198 (_phy)->def_md_devad, \ 199 (_bank + (_addr & 0xf)), \ 200 _val) 201 202 #define CL22_RD_OVER_CL45(_bp, _phy, _bank, _addr, _val) \ 203 bnx2x_cl45_read(_bp, _phy, \ 204 (_phy)->def_md_devad, \ 205 (_bank + (_addr & 0xf)), \ 206 _val) 207 208 static int bnx2x_check_half_open_conn(struct link_params *params, 209 struct link_vars *vars, u8 notify); 210 static int bnx2x_sfp_module_detection(struct bnx2x_phy *phy, 211 struct link_params *params); 212 213 static u32 bnx2x_bits_en(struct bnx2x *bp, u32 reg, u32 bits) 214 { 215 u32 val = REG_RD(bp, reg); 216 217 val |= bits; 218 REG_WR(bp, reg, val); 219 return val; 220 } 221 222 static u32 bnx2x_bits_dis(struct bnx2x *bp, u32 reg, u32 bits) 223 { 224 u32 val = REG_RD(bp, reg); 225 226 val &= ~bits; 227 REG_WR(bp, reg, val); 228 return val; 229 } 230 231 /* 232 * bnx2x_check_lfa - This function checks if link reinitialization is required, 233 * or link flap can be avoided. 234 * 235 * @params: link parameters 236 * Returns 0 if Link Flap Avoidance conditions are met otherwise, the failed 237 * condition code. 238 */ 239 static int bnx2x_check_lfa(struct link_params *params) 240 { 241 u32 link_status, cfg_idx, lfa_mask, cfg_size; 242 u32 cur_speed_cap_mask, cur_req_fc_auto_adv, additional_config; 243 u32 saved_val, req_val, eee_status; 244 struct bnx2x *bp = params->bp; 245 246 additional_config = 247 REG_RD(bp, params->lfa_base + 248 offsetof(struct shmem_lfa, additional_config)); 249 250 /* NOTE: must be first condition checked - 251 * to verify DCC bit is cleared in any case! 252 */ 253 if (additional_config & NO_LFA_DUE_TO_DCC_MASK) { 254 DP(NETIF_MSG_LINK, "No LFA due to DCC flap after clp exit\n"); 255 REG_WR(bp, params->lfa_base + 256 offsetof(struct shmem_lfa, additional_config), 257 additional_config & ~NO_LFA_DUE_TO_DCC_MASK); 258 return LFA_DCC_LFA_DISABLED; 259 } 260 261 /* Verify that link is up */ 262 link_status = REG_RD(bp, params->shmem_base + 263 offsetof(struct shmem_region, 264 port_mb[params->port].link_status)); 265 if (!(link_status & LINK_STATUS_LINK_UP)) 266 return LFA_LINK_DOWN; 267 268 /* if loaded after BOOT from SAN, don't flap the link in any case and 269 * rely on link set by preboot driver 270 */ 271 if (params->feature_config_flags & FEATURE_CONFIG_BOOT_FROM_SAN) 272 return 0; 273 274 /* Verify that loopback mode is not set */ 275 if (params->loopback_mode) 276 return LFA_LOOPBACK_ENABLED; 277 278 /* Verify that MFW supports LFA */ 279 if (!params->lfa_base) 280 return LFA_MFW_IS_TOO_OLD; 281 282 if (params->num_phys == 3) { 283 cfg_size = 2; 284 lfa_mask = 0xffffffff; 285 } else { 286 cfg_size = 1; 287 lfa_mask = 0xffff; 288 } 289 290 /* Compare Duplex */ 291 saved_val = REG_RD(bp, params->lfa_base + 292 offsetof(struct shmem_lfa, req_duplex)); 293 req_val = params->req_duplex[0] | (params->req_duplex[1] << 16); 294 if ((saved_val & lfa_mask) != (req_val & lfa_mask)) { 295 DP(NETIF_MSG_LINK, "Duplex mismatch %x vs. %x\n", 296 (saved_val & lfa_mask), (req_val & lfa_mask)); 297 return LFA_DUPLEX_MISMATCH; 298 } 299 /* Compare Flow Control */ 300 saved_val = REG_RD(bp, params->lfa_base + 301 offsetof(struct shmem_lfa, req_flow_ctrl)); 302 req_val = params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16); 303 if ((saved_val & lfa_mask) != (req_val & lfa_mask)) { 304 DP(NETIF_MSG_LINK, "Flow control mismatch %x vs. %x\n", 305 (saved_val & lfa_mask), (req_val & lfa_mask)); 306 return LFA_FLOW_CTRL_MISMATCH; 307 } 308 /* Compare Link Speed */ 309 saved_val = REG_RD(bp, params->lfa_base + 310 offsetof(struct shmem_lfa, req_line_speed)); 311 req_val = params->req_line_speed[0] | (params->req_line_speed[1] << 16); 312 if ((saved_val & lfa_mask) != (req_val & lfa_mask)) { 313 DP(NETIF_MSG_LINK, "Link speed mismatch %x vs. %x\n", 314 (saved_val & lfa_mask), (req_val & lfa_mask)); 315 return LFA_LINK_SPEED_MISMATCH; 316 } 317 318 for (cfg_idx = 0; cfg_idx < cfg_size; cfg_idx++) { 319 cur_speed_cap_mask = REG_RD(bp, params->lfa_base + 320 offsetof(struct shmem_lfa, 321 speed_cap_mask[cfg_idx])); 322 323 if (cur_speed_cap_mask != params->speed_cap_mask[cfg_idx]) { 324 DP(NETIF_MSG_LINK, "Speed Cap mismatch %x vs. %x\n", 325 cur_speed_cap_mask, 326 params->speed_cap_mask[cfg_idx]); 327 return LFA_SPEED_CAP_MISMATCH; 328 } 329 } 330 331 cur_req_fc_auto_adv = 332 REG_RD(bp, params->lfa_base + 333 offsetof(struct shmem_lfa, additional_config)) & 334 REQ_FC_AUTO_ADV_MASK; 335 336 if ((u16)cur_req_fc_auto_adv != params->req_fc_auto_adv) { 337 DP(NETIF_MSG_LINK, "Flow Ctrl AN mismatch %x vs. %x\n", 338 cur_req_fc_auto_adv, params->req_fc_auto_adv); 339 return LFA_FLOW_CTRL_MISMATCH; 340 } 341 342 eee_status = REG_RD(bp, params->shmem2_base + 343 offsetof(struct shmem2_region, 344 eee_status[params->port])); 345 346 if (((eee_status & SHMEM_EEE_LPI_REQUESTED_BIT) ^ 347 (params->eee_mode & EEE_MODE_ENABLE_LPI)) || 348 ((eee_status & SHMEM_EEE_REQUESTED_BIT) ^ 349 (params->eee_mode & EEE_MODE_ADV_LPI))) { 350 DP(NETIF_MSG_LINK, "EEE mismatch %x vs. %x\n", params->eee_mode, 351 eee_status); 352 return LFA_EEE_MISMATCH; 353 } 354 355 /* LFA conditions are met */ 356 return 0; 357 } 358 /******************************************************************/ 359 /* EPIO/GPIO section */ 360 /******************************************************************/ 361 static void bnx2x_get_epio(struct bnx2x *bp, u32 epio_pin, u32 *en) 362 { 363 u32 epio_mask, gp_oenable; 364 *en = 0; 365 /* Sanity check */ 366 if (epio_pin > 31) { 367 DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to get\n", epio_pin); 368 return; 369 } 370 371 epio_mask = 1 << epio_pin; 372 /* Set this EPIO to output */ 373 gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE); 374 REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable & ~epio_mask); 375 376 *en = (REG_RD(bp, MCP_REG_MCPR_GP_INPUTS) & epio_mask) >> epio_pin; 377 } 378 static void bnx2x_set_epio(struct bnx2x *bp, u32 epio_pin, u32 en) 379 { 380 u32 epio_mask, gp_output, gp_oenable; 381 382 /* Sanity check */ 383 if (epio_pin > 31) { 384 DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to set\n", epio_pin); 385 return; 386 } 387 DP(NETIF_MSG_LINK, "Setting EPIO pin %d to %d\n", epio_pin, en); 388 epio_mask = 1 << epio_pin; 389 /* Set this EPIO to output */ 390 gp_output = REG_RD(bp, MCP_REG_MCPR_GP_OUTPUTS); 391 if (en) 392 gp_output |= epio_mask; 393 else 394 gp_output &= ~epio_mask; 395 396 REG_WR(bp, MCP_REG_MCPR_GP_OUTPUTS, gp_output); 397 398 /* Set the value for this EPIO */ 399 gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE); 400 REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable | epio_mask); 401 } 402 403 static void bnx2x_set_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 val) 404 { 405 if (pin_cfg == PIN_CFG_NA) 406 return; 407 if (pin_cfg >= PIN_CFG_EPIO0) { 408 bnx2x_set_epio(bp, pin_cfg - PIN_CFG_EPIO0, val); 409 } else { 410 u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3; 411 u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2; 412 bnx2x_set_gpio(bp, gpio_num, (u8)val, gpio_port); 413 } 414 } 415 416 static u32 bnx2x_get_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 *val) 417 { 418 if (pin_cfg == PIN_CFG_NA) 419 return -EINVAL; 420 if (pin_cfg >= PIN_CFG_EPIO0) { 421 bnx2x_get_epio(bp, pin_cfg - PIN_CFG_EPIO0, val); 422 } else { 423 u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3; 424 u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2; 425 *val = bnx2x_get_gpio(bp, gpio_num, gpio_port); 426 } 427 return 0; 428 429 } 430 /******************************************************************/ 431 /* ETS section */ 432 /******************************************************************/ 433 static void bnx2x_ets_e2e3a0_disabled(struct link_params *params) 434 { 435 /* ETS disabled configuration*/ 436 struct bnx2x *bp = params->bp; 437 438 DP(NETIF_MSG_LINK, "ETS E2E3 disabled configuration\n"); 439 440 /* mapping between entry priority to client number (0,1,2 -debug and 441 * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST) 442 * 3bits client num. 443 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0 444 * cos1-100 cos0-011 dbg1-010 dbg0-001 MCP-000 445 */ 446 447 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, 0x4688); 448 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves 449 * as strict. Bits 0,1,2 - debug and management entries, 3 - 450 * COS0 entry, 4 - COS1 entry. 451 * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT 452 * bit4 bit3 bit2 bit1 bit0 453 * MCP and debug are strict 454 */ 455 456 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7); 457 /* defines which entries (clients) are subjected to WFQ arbitration */ 458 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0); 459 /* For strict priority entries defines the number of consecutive 460 * slots for the highest priority. 461 */ 462 REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100); 463 /* mapping between the CREDIT_WEIGHT registers and actual client 464 * numbers 465 */ 466 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0); 467 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0); 468 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0); 469 470 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 0); 471 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 0); 472 REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, 0); 473 /* ETS mode disable */ 474 REG_WR(bp, PBF_REG_ETS_ENABLED, 0); 475 /* If ETS mode is enabled (there is no strict priority) defines a WFQ 476 * weight for COS0/COS1. 477 */ 478 REG_WR(bp, PBF_REG_COS0_WEIGHT, 0x2710); 479 REG_WR(bp, PBF_REG_COS1_WEIGHT, 0x2710); 480 /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter */ 481 REG_WR(bp, PBF_REG_COS0_UPPER_BOUND, 0x989680); 482 REG_WR(bp, PBF_REG_COS1_UPPER_BOUND, 0x989680); 483 /* Defines the number of consecutive slots for the strict priority */ 484 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0); 485 } 486 /****************************************************************************** 487 * Description: 488 * Getting min_w_val will be set according to line speed . 489 *. 490 ******************************************************************************/ 491 static u32 bnx2x_ets_get_min_w_val_nig(const struct link_vars *vars) 492 { 493 u32 min_w_val = 0; 494 /* Calculate min_w_val.*/ 495 if (vars->link_up) { 496 if (vars->line_speed == SPEED_20000) 497 min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS; 498 else 499 min_w_val = ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS; 500 } else 501 min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS; 502 /* If the link isn't up (static configuration for example ) The 503 * link will be according to 20GBPS. 504 */ 505 return min_w_val; 506 } 507 /****************************************************************************** 508 * Description: 509 * Getting credit upper bound form min_w_val. 510 *. 511 ******************************************************************************/ 512 static u32 bnx2x_ets_get_credit_upper_bound(const u32 min_w_val) 513 { 514 const u32 credit_upper_bound = (u32)MAXVAL((150 * min_w_val), 515 MAX_PACKET_SIZE); 516 return credit_upper_bound; 517 } 518 /****************************************************************************** 519 * Description: 520 * Set credit upper bound for NIG. 521 *. 522 ******************************************************************************/ 523 static void bnx2x_ets_e3b0_set_credit_upper_bound_nig( 524 const struct link_params *params, 525 const u32 min_w_val) 526 { 527 struct bnx2x *bp = params->bp; 528 const u8 port = params->port; 529 const u32 credit_upper_bound = 530 bnx2x_ets_get_credit_upper_bound(min_w_val); 531 532 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 : 533 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, credit_upper_bound); 534 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 : 535 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, credit_upper_bound); 536 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 : 537 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_2, credit_upper_bound); 538 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 : 539 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_3, credit_upper_bound); 540 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 : 541 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_4, credit_upper_bound); 542 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 : 543 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_5, credit_upper_bound); 544 545 if (!port) { 546 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6, 547 credit_upper_bound); 548 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7, 549 credit_upper_bound); 550 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8, 551 credit_upper_bound); 552 } 553 } 554 /****************************************************************************** 555 * Description: 556 * Will return the NIG ETS registers to init values.Except 557 * credit_upper_bound. 558 * That isn't used in this configuration (No WFQ is enabled) and will be 559 * configured acording to spec 560 *. 561 ******************************************************************************/ 562 static void bnx2x_ets_e3b0_nig_disabled(const struct link_params *params, 563 const struct link_vars *vars) 564 { 565 struct bnx2x *bp = params->bp; 566 const u8 port = params->port; 567 const u32 min_w_val = bnx2x_ets_get_min_w_val_nig(vars); 568 /* Mapping between entry priority to client number (0,1,2 -debug and 569 * management clients, 3 - COS0 client, 4 - COS1, ... 8 - 570 * COS5)(HIGHEST) 4bits client num.TODO_ETS - Should be done by 571 * reset value or init tool 572 */ 573 if (port) { 574 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, 0x543210); 575 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB, 0x0); 576 } else { 577 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, 0x76543210); 578 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, 0x8); 579 } 580 /* For strict priority entries defines the number of consecutive 581 * slots for the highest priority. 582 */ 583 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS : 584 NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100); 585 /* Mapping between the CREDIT_WEIGHT registers and actual client 586 * numbers 587 */ 588 if (port) { 589 /*Port 1 has 6 COS*/ 590 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB, 0x210543); 591 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x0); 592 } else { 593 /*Port 0 has 9 COS*/ 594 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB, 595 0x43210876); 596 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x5); 597 } 598 599 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves 600 * as strict. Bits 0,1,2 - debug and management entries, 3 - 601 * COS0 entry, 4 - COS1 entry. 602 * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT 603 * bit4 bit3 bit2 bit1 bit0 604 * MCP and debug are strict 605 */ 606 if (port) 607 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT, 0x3f); 608 else 609 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1ff); 610 /* defines which entries (clients) are subjected to WFQ arbitration */ 611 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ : 612 NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0); 613 614 /* Please notice the register address are note continuous and a 615 * for here is note appropriate.In 2 port mode port0 only COS0-5 616 * can be used. DEBUG1,DEBUG1,MGMT are never used for WFQ* In 4 617 * port mode port1 only COS0-2 can be used. DEBUG1,DEBUG1,MGMT 618 * are never used for WFQ 619 */ 620 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 : 621 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0x0); 622 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 : 623 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0x0); 624 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 : 625 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2, 0x0); 626 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 : 627 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3, 0x0); 628 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 : 629 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4, 0x0); 630 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 : 631 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5, 0x0); 632 if (!port) { 633 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6, 0x0); 634 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7, 0x0); 635 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8, 0x0); 636 } 637 638 bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val); 639 } 640 /****************************************************************************** 641 * Description: 642 * Set credit upper bound for PBF. 643 *. 644 ******************************************************************************/ 645 static void bnx2x_ets_e3b0_set_credit_upper_bound_pbf( 646 const struct link_params *params, 647 const u32 min_w_val) 648 { 649 struct bnx2x *bp = params->bp; 650 const u32 credit_upper_bound = 651 bnx2x_ets_get_credit_upper_bound(min_w_val); 652 const u8 port = params->port; 653 u32 base_upper_bound = 0; 654 u8 max_cos = 0; 655 u8 i = 0; 656 /* In 2 port mode port0 has COS0-5 that can be used for WFQ.In 4 657 * port mode port1 has COS0-2 that can be used for WFQ. 658 */ 659 if (!port) { 660 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P0; 661 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0; 662 } else { 663 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P1; 664 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT1; 665 } 666 667 for (i = 0; i < max_cos; i++) 668 REG_WR(bp, base_upper_bound + (i << 2), credit_upper_bound); 669 } 670 671 /****************************************************************************** 672 * Description: 673 * Will return the PBF ETS registers to init values.Except 674 * credit_upper_bound. 675 * That isn't used in this configuration (No WFQ is enabled) and will be 676 * configured acording to spec 677 *. 678 ******************************************************************************/ 679 static void bnx2x_ets_e3b0_pbf_disabled(const struct link_params *params) 680 { 681 struct bnx2x *bp = params->bp; 682 const u8 port = params->port; 683 const u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL; 684 u8 i = 0; 685 u32 base_weight = 0; 686 u8 max_cos = 0; 687 688 /* Mapping between entry priority to client number 0 - COS0 689 * client, 2 - COS1, ... 5 - COS5)(HIGHEST) 4bits client num. 690 * TODO_ETS - Should be done by reset value or init tool 691 */ 692 if (port) 693 /* 0x688 (|011|0 10|00 1|000) */ 694 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , 0x688); 695 else 696 /* (10 1|100 |011|0 10|00 1|000) */ 697 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , 0x2C688); 698 699 /* TODO_ETS - Should be done by reset value or init tool */ 700 if (port) 701 /* 0x688 (|011|0 10|00 1|000)*/ 702 REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1, 0x688); 703 else 704 /* 0x2C688 (10 1|100 |011|0 10|00 1|000) */ 705 REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0, 0x2C688); 706 707 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 : 708 PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0 , 0x100); 709 710 711 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 : 712 PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , 0); 713 714 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 : 715 PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0 , 0); 716 /* In 2 port mode port0 has COS0-5 that can be used for WFQ. 717 * In 4 port mode port1 has COS0-2 that can be used for WFQ. 718 */ 719 if (!port) { 720 base_weight = PBF_REG_COS0_WEIGHT_P0; 721 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0; 722 } else { 723 base_weight = PBF_REG_COS0_WEIGHT_P1; 724 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT1; 725 } 726 727 for (i = 0; i < max_cos; i++) 728 REG_WR(bp, base_weight + (0x4 * i), 0); 729 730 bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf); 731 } 732 /****************************************************************************** 733 * Description: 734 * E3B0 disable will return basicly the values to init values. 735 *. 736 ******************************************************************************/ 737 static int bnx2x_ets_e3b0_disabled(const struct link_params *params, 738 const struct link_vars *vars) 739 { 740 struct bnx2x *bp = params->bp; 741 742 if (!CHIP_IS_E3B0(bp)) { 743 DP(NETIF_MSG_LINK, 744 "bnx2x_ets_e3b0_disabled the chip isn't E3B0\n"); 745 return -EINVAL; 746 } 747 748 bnx2x_ets_e3b0_nig_disabled(params, vars); 749 750 bnx2x_ets_e3b0_pbf_disabled(params); 751 752 return 0; 753 } 754 755 /****************************************************************************** 756 * Description: 757 * Disable will return basicly the values to init values. 758 * 759 ******************************************************************************/ 760 int bnx2x_ets_disabled(struct link_params *params, 761 struct link_vars *vars) 762 { 763 struct bnx2x *bp = params->bp; 764 int bnx2x_status = 0; 765 766 if ((CHIP_IS_E2(bp)) || (CHIP_IS_E3A0(bp))) 767 bnx2x_ets_e2e3a0_disabled(params); 768 else if (CHIP_IS_E3B0(bp)) 769 bnx2x_status = bnx2x_ets_e3b0_disabled(params, vars); 770 else { 771 DP(NETIF_MSG_LINK, "bnx2x_ets_disabled - chip not supported\n"); 772 return -EINVAL; 773 } 774 775 return bnx2x_status; 776 } 777 778 /****************************************************************************** 779 * Description 780 * Set the COS mappimg to SP and BW until this point all the COS are not 781 * set as SP or BW. 782 ******************************************************************************/ 783 static int bnx2x_ets_e3b0_cli_map(const struct link_params *params, 784 const struct bnx2x_ets_params *ets_params, 785 const u8 cos_sp_bitmap, 786 const u8 cos_bw_bitmap) 787 { 788 struct bnx2x *bp = params->bp; 789 const u8 port = params->port; 790 const u8 nig_cli_sp_bitmap = 0x7 | (cos_sp_bitmap << 3); 791 const u8 pbf_cli_sp_bitmap = cos_sp_bitmap; 792 const u8 nig_cli_subject2wfq_bitmap = cos_bw_bitmap << 3; 793 const u8 pbf_cli_subject2wfq_bitmap = cos_bw_bitmap; 794 795 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT : 796 NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, nig_cli_sp_bitmap); 797 798 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 : 799 PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , pbf_cli_sp_bitmap); 800 801 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ : 802 NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 803 nig_cli_subject2wfq_bitmap); 804 805 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 : 806 PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0, 807 pbf_cli_subject2wfq_bitmap); 808 809 return 0; 810 } 811 812 /****************************************************************************** 813 * Description: 814 * This function is needed because NIG ARB_CREDIT_WEIGHT_X are 815 * not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable. 816 ******************************************************************************/ 817 static int bnx2x_ets_e3b0_set_cos_bw(struct bnx2x *bp, 818 const u8 cos_entry, 819 const u32 min_w_val_nig, 820 const u32 min_w_val_pbf, 821 const u16 total_bw, 822 const u8 bw, 823 const u8 port) 824 { 825 u32 nig_reg_adress_crd_weight = 0; 826 u32 pbf_reg_adress_crd_weight = 0; 827 /* Calculate and set BW for this COS - use 1 instead of 0 for BW */ 828 const u32 cos_bw_nig = ((bw ? bw : 1) * min_w_val_nig) / total_bw; 829 const u32 cos_bw_pbf = ((bw ? bw : 1) * min_w_val_pbf) / total_bw; 830 831 switch (cos_entry) { 832 case 0: 833 nig_reg_adress_crd_weight = 834 (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 : 835 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0; 836 pbf_reg_adress_crd_weight = (port) ? 837 PBF_REG_COS0_WEIGHT_P1 : PBF_REG_COS0_WEIGHT_P0; 838 break; 839 case 1: 840 nig_reg_adress_crd_weight = (port) ? 841 NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 : 842 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1; 843 pbf_reg_adress_crd_weight = (port) ? 844 PBF_REG_COS1_WEIGHT_P1 : PBF_REG_COS1_WEIGHT_P0; 845 break; 846 case 2: 847 nig_reg_adress_crd_weight = (port) ? 848 NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 : 849 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2; 850 851 pbf_reg_adress_crd_weight = (port) ? 852 PBF_REG_COS2_WEIGHT_P1 : PBF_REG_COS2_WEIGHT_P0; 853 break; 854 case 3: 855 if (port) 856 return -EINVAL; 857 nig_reg_adress_crd_weight = 858 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3; 859 pbf_reg_adress_crd_weight = 860 PBF_REG_COS3_WEIGHT_P0; 861 break; 862 case 4: 863 if (port) 864 return -EINVAL; 865 nig_reg_adress_crd_weight = 866 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4; 867 pbf_reg_adress_crd_weight = PBF_REG_COS4_WEIGHT_P0; 868 break; 869 case 5: 870 if (port) 871 return -EINVAL; 872 nig_reg_adress_crd_weight = 873 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5; 874 pbf_reg_adress_crd_weight = PBF_REG_COS5_WEIGHT_P0; 875 break; 876 } 877 878 REG_WR(bp, nig_reg_adress_crd_weight, cos_bw_nig); 879 880 REG_WR(bp, pbf_reg_adress_crd_weight, cos_bw_pbf); 881 882 return 0; 883 } 884 /****************************************************************************** 885 * Description: 886 * Calculate the total BW.A value of 0 isn't legal. 887 * 888 ******************************************************************************/ 889 static int bnx2x_ets_e3b0_get_total_bw( 890 const struct link_params *params, 891 struct bnx2x_ets_params *ets_params, 892 u16 *total_bw) 893 { 894 struct bnx2x *bp = params->bp; 895 u8 cos_idx = 0; 896 u8 is_bw_cos_exist = 0; 897 898 *total_bw = 0 ; 899 /* Calculate total BW requested */ 900 for (cos_idx = 0; cos_idx < ets_params->num_of_cos; cos_idx++) { 901 if (ets_params->cos[cos_idx].state == bnx2x_cos_state_bw) { 902 is_bw_cos_exist = 1; 903 if (!ets_params->cos[cos_idx].params.bw_params.bw) { 904 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config BW" 905 "was set to 0\n"); 906 /* This is to prevent a state when ramrods 907 * can't be sent 908 */ 909 ets_params->cos[cos_idx].params.bw_params.bw 910 = 1; 911 } 912 *total_bw += 913 ets_params->cos[cos_idx].params.bw_params.bw; 914 } 915 } 916 917 /* Check total BW is valid */ 918 if ((is_bw_cos_exist == 1) && (*total_bw != 100)) { 919 if (*total_bw == 0) { 920 DP(NETIF_MSG_LINK, 921 "bnx2x_ets_E3B0_config total BW shouldn't be 0\n"); 922 return -EINVAL; 923 } 924 DP(NETIF_MSG_LINK, 925 "bnx2x_ets_E3B0_config total BW should be 100\n"); 926 /* We can handle a case whre the BW isn't 100 this can happen 927 * if the TC are joined. 928 */ 929 } 930 return 0; 931 } 932 933 /****************************************************************************** 934 * Description: 935 * Invalidate all the sp_pri_to_cos. 936 * 937 ******************************************************************************/ 938 static void bnx2x_ets_e3b0_sp_pri_to_cos_init(u8 *sp_pri_to_cos) 939 { 940 u8 pri = 0; 941 for (pri = 0; pri < DCBX_MAX_NUM_COS; pri++) 942 sp_pri_to_cos[pri] = DCBX_INVALID_COS; 943 } 944 /****************************************************************************** 945 * Description: 946 * Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers 947 * according to sp_pri_to_cos. 948 * 949 ******************************************************************************/ 950 static int bnx2x_ets_e3b0_sp_pri_to_cos_set(const struct link_params *params, 951 u8 *sp_pri_to_cos, const u8 pri, 952 const u8 cos_entry) 953 { 954 struct bnx2x *bp = params->bp; 955 const u8 port = params->port; 956 const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 : 957 DCBX_E3B0_MAX_NUM_COS_PORT0; 958 959 if (pri >= max_num_of_cos) { 960 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid " 961 "parameter Illegal strict priority\n"); 962 return -EINVAL; 963 } 964 965 if (sp_pri_to_cos[pri] != DCBX_INVALID_COS) { 966 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid " 967 "parameter There can't be two COS's with " 968 "the same strict pri\n"); 969 return -EINVAL; 970 } 971 972 sp_pri_to_cos[pri] = cos_entry; 973 return 0; 974 975 } 976 977 /****************************************************************************** 978 * Description: 979 * Returns the correct value according to COS and priority in 980 * the sp_pri_cli register. 981 * 982 ******************************************************************************/ 983 static u64 bnx2x_e3b0_sp_get_pri_cli_reg(const u8 cos, const u8 cos_offset, 984 const u8 pri_set, 985 const u8 pri_offset, 986 const u8 entry_size) 987 { 988 u64 pri_cli_nig = 0; 989 pri_cli_nig = ((u64)(cos + cos_offset)) << (entry_size * 990 (pri_set + pri_offset)); 991 992 return pri_cli_nig; 993 } 994 /****************************************************************************** 995 * Description: 996 * Returns the correct value according to COS and priority in the 997 * sp_pri_cli register for NIG. 998 * 999 ******************************************************************************/ 1000 static u64 bnx2x_e3b0_sp_get_pri_cli_reg_nig(const u8 cos, const u8 pri_set) 1001 { 1002 /* MCP Dbg0 and dbg1 are always with higher strict pri*/ 1003 const u8 nig_cos_offset = 3; 1004 const u8 nig_pri_offset = 3; 1005 1006 return bnx2x_e3b0_sp_get_pri_cli_reg(cos, nig_cos_offset, pri_set, 1007 nig_pri_offset, 4); 1008 1009 } 1010 /****************************************************************************** 1011 * Description: 1012 * Returns the correct value according to COS and priority in the 1013 * sp_pri_cli register for PBF. 1014 * 1015 ******************************************************************************/ 1016 static u64 bnx2x_e3b0_sp_get_pri_cli_reg_pbf(const u8 cos, const u8 pri_set) 1017 { 1018 const u8 pbf_cos_offset = 0; 1019 const u8 pbf_pri_offset = 0; 1020 1021 return bnx2x_e3b0_sp_get_pri_cli_reg(cos, pbf_cos_offset, pri_set, 1022 pbf_pri_offset, 3); 1023 1024 } 1025 1026 /****************************************************************************** 1027 * Description: 1028 * Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers 1029 * according to sp_pri_to_cos.(which COS has higher priority) 1030 * 1031 ******************************************************************************/ 1032 static int bnx2x_ets_e3b0_sp_set_pri_cli_reg(const struct link_params *params, 1033 u8 *sp_pri_to_cos) 1034 { 1035 struct bnx2x *bp = params->bp; 1036 u8 i = 0; 1037 const u8 port = params->port; 1038 /* MCP Dbg0 and dbg1 are always with higher strict pri*/ 1039 u64 pri_cli_nig = 0x210; 1040 u32 pri_cli_pbf = 0x0; 1041 u8 pri_set = 0; 1042 u8 pri_bitmask = 0; 1043 const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 : 1044 DCBX_E3B0_MAX_NUM_COS_PORT0; 1045 1046 u8 cos_bit_to_set = (1 << max_num_of_cos) - 1; 1047 1048 /* Set all the strict priority first */ 1049 for (i = 0; i < max_num_of_cos; i++) { 1050 if (sp_pri_to_cos[i] != DCBX_INVALID_COS) { 1051 if (sp_pri_to_cos[i] >= DCBX_MAX_NUM_COS) { 1052 DP(NETIF_MSG_LINK, 1053 "bnx2x_ets_e3b0_sp_set_pri_cli_reg " 1054 "invalid cos entry\n"); 1055 return -EINVAL; 1056 } 1057 1058 pri_cli_nig |= bnx2x_e3b0_sp_get_pri_cli_reg_nig( 1059 sp_pri_to_cos[i], pri_set); 1060 1061 pri_cli_pbf |= bnx2x_e3b0_sp_get_pri_cli_reg_pbf( 1062 sp_pri_to_cos[i], pri_set); 1063 pri_bitmask = 1 << sp_pri_to_cos[i]; 1064 /* COS is used remove it from bitmap.*/ 1065 if (!(pri_bitmask & cos_bit_to_set)) { 1066 DP(NETIF_MSG_LINK, 1067 "bnx2x_ets_e3b0_sp_set_pri_cli_reg " 1068 "invalid There can't be two COS's with" 1069 " the same strict pri\n"); 1070 return -EINVAL; 1071 } 1072 cos_bit_to_set &= ~pri_bitmask; 1073 pri_set++; 1074 } 1075 } 1076 1077 /* Set all the Non strict priority i= COS*/ 1078 for (i = 0; i < max_num_of_cos; i++) { 1079 pri_bitmask = 1 << i; 1080 /* Check if COS was already used for SP */ 1081 if (pri_bitmask & cos_bit_to_set) { 1082 /* COS wasn't used for SP */ 1083 pri_cli_nig |= bnx2x_e3b0_sp_get_pri_cli_reg_nig( 1084 i, pri_set); 1085 1086 pri_cli_pbf |= bnx2x_e3b0_sp_get_pri_cli_reg_pbf( 1087 i, pri_set); 1088 /* COS is used remove it from bitmap.*/ 1089 cos_bit_to_set &= ~pri_bitmask; 1090 pri_set++; 1091 } 1092 } 1093 1094 if (pri_set != max_num_of_cos) { 1095 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_set_pri_cli_reg not all " 1096 "entries were set\n"); 1097 return -EINVAL; 1098 } 1099 1100 if (port) { 1101 /* Only 6 usable clients*/ 1102 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, 1103 (u32)pri_cli_nig); 1104 1105 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , pri_cli_pbf); 1106 } else { 1107 /* Only 9 usable clients*/ 1108 const u32 pri_cli_nig_lsb = (u32) (pri_cli_nig); 1109 const u32 pri_cli_nig_msb = (u32) ((pri_cli_nig >> 32) & 0xF); 1110 1111 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, 1112 pri_cli_nig_lsb); 1113 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, 1114 pri_cli_nig_msb); 1115 1116 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , pri_cli_pbf); 1117 } 1118 return 0; 1119 } 1120 1121 /****************************************************************************** 1122 * Description: 1123 * Configure the COS to ETS according to BW and SP settings. 1124 ******************************************************************************/ 1125 int bnx2x_ets_e3b0_config(const struct link_params *params, 1126 const struct link_vars *vars, 1127 struct bnx2x_ets_params *ets_params) 1128 { 1129 struct bnx2x *bp = params->bp; 1130 int bnx2x_status = 0; 1131 const u8 port = params->port; 1132 u16 total_bw = 0; 1133 const u32 min_w_val_nig = bnx2x_ets_get_min_w_val_nig(vars); 1134 const u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL; 1135 u8 cos_bw_bitmap = 0; 1136 u8 cos_sp_bitmap = 0; 1137 u8 sp_pri_to_cos[DCBX_MAX_NUM_COS] = {0}; 1138 const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 : 1139 DCBX_E3B0_MAX_NUM_COS_PORT0; 1140 u8 cos_entry = 0; 1141 1142 if (!CHIP_IS_E3B0(bp)) { 1143 DP(NETIF_MSG_LINK, 1144 "bnx2x_ets_e3b0_disabled the chip isn't E3B0\n"); 1145 return -EINVAL; 1146 } 1147 1148 if ((ets_params->num_of_cos > max_num_of_cos)) { 1149 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config the number of COS " 1150 "isn't supported\n"); 1151 return -EINVAL; 1152 } 1153 1154 /* Prepare sp strict priority parameters*/ 1155 bnx2x_ets_e3b0_sp_pri_to_cos_init(sp_pri_to_cos); 1156 1157 /* Prepare BW parameters*/ 1158 bnx2x_status = bnx2x_ets_e3b0_get_total_bw(params, ets_params, 1159 &total_bw); 1160 if (bnx2x_status) { 1161 DP(NETIF_MSG_LINK, 1162 "bnx2x_ets_E3B0_config get_total_bw failed\n"); 1163 return -EINVAL; 1164 } 1165 1166 /* Upper bound is set according to current link speed (min_w_val 1167 * should be the same for upper bound and COS credit val). 1168 */ 1169 bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val_nig); 1170 bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf); 1171 1172 1173 for (cos_entry = 0; cos_entry < ets_params->num_of_cos; cos_entry++) { 1174 if (bnx2x_cos_state_bw == ets_params->cos[cos_entry].state) { 1175 cos_bw_bitmap |= (1 << cos_entry); 1176 /* The function also sets the BW in HW(not the mappin 1177 * yet) 1178 */ 1179 bnx2x_status = bnx2x_ets_e3b0_set_cos_bw( 1180 bp, cos_entry, min_w_val_nig, min_w_val_pbf, 1181 total_bw, 1182 ets_params->cos[cos_entry].params.bw_params.bw, 1183 port); 1184 } else if (bnx2x_cos_state_strict == 1185 ets_params->cos[cos_entry].state){ 1186 cos_sp_bitmap |= (1 << cos_entry); 1187 1188 bnx2x_status = bnx2x_ets_e3b0_sp_pri_to_cos_set( 1189 params, 1190 sp_pri_to_cos, 1191 ets_params->cos[cos_entry].params.sp_params.pri, 1192 cos_entry); 1193 1194 } else { 1195 DP(NETIF_MSG_LINK, 1196 "bnx2x_ets_e3b0_config cos state not valid\n"); 1197 return -EINVAL; 1198 } 1199 if (bnx2x_status) { 1200 DP(NETIF_MSG_LINK, 1201 "bnx2x_ets_e3b0_config set cos bw failed\n"); 1202 return bnx2x_status; 1203 } 1204 } 1205 1206 /* Set SP register (which COS has higher priority) */ 1207 bnx2x_status = bnx2x_ets_e3b0_sp_set_pri_cli_reg(params, 1208 sp_pri_to_cos); 1209 1210 if (bnx2x_status) { 1211 DP(NETIF_MSG_LINK, 1212 "bnx2x_ets_E3B0_config set_pri_cli_reg failed\n"); 1213 return bnx2x_status; 1214 } 1215 1216 /* Set client mapping of BW and strict */ 1217 bnx2x_status = bnx2x_ets_e3b0_cli_map(params, ets_params, 1218 cos_sp_bitmap, 1219 cos_bw_bitmap); 1220 1221 if (bnx2x_status) { 1222 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config SP failed\n"); 1223 return bnx2x_status; 1224 } 1225 return 0; 1226 } 1227 static void bnx2x_ets_bw_limit_common(const struct link_params *params) 1228 { 1229 /* ETS disabled configuration */ 1230 struct bnx2x *bp = params->bp; 1231 DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n"); 1232 /* Defines which entries (clients) are subjected to WFQ arbitration 1233 * COS0 0x8 1234 * COS1 0x10 1235 */ 1236 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0x18); 1237 /* Mapping between the ARB_CREDIT_WEIGHT registers and actual 1238 * client numbers (WEIGHT_0 does not actually have to represent 1239 * client 0) 1240 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0 1241 * cos1-001 cos0-000 dbg1-100 dbg0-011 MCP-010 1242 */ 1243 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0x111A); 1244 1245 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 1246 ETS_BW_LIMIT_CREDIT_UPPER_BOUND); 1247 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 1248 ETS_BW_LIMIT_CREDIT_UPPER_BOUND); 1249 1250 /* ETS mode enabled*/ 1251 REG_WR(bp, PBF_REG_ETS_ENABLED, 1); 1252 1253 /* Defines the number of consecutive slots for the strict priority */ 1254 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0); 1255 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves 1256 * as strict. Bits 0,1,2 - debug and management entries, 3 - COS0 1257 * entry, 4 - COS1 entry. 1258 * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT 1259 * bit4 bit3 bit2 bit1 bit0 1260 * MCP and debug are strict 1261 */ 1262 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7); 1263 1264 /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter.*/ 1265 REG_WR(bp, PBF_REG_COS0_UPPER_BOUND, 1266 ETS_BW_LIMIT_CREDIT_UPPER_BOUND); 1267 REG_WR(bp, PBF_REG_COS1_UPPER_BOUND, 1268 ETS_BW_LIMIT_CREDIT_UPPER_BOUND); 1269 } 1270 1271 void bnx2x_ets_bw_limit(const struct link_params *params, const u32 cos0_bw, 1272 const u32 cos1_bw) 1273 { 1274 /* ETS disabled configuration*/ 1275 struct bnx2x *bp = params->bp; 1276 const u32 total_bw = cos0_bw + cos1_bw; 1277 u32 cos0_credit_weight = 0; 1278 u32 cos1_credit_weight = 0; 1279 1280 DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n"); 1281 1282 if ((!total_bw) || 1283 (!cos0_bw) || 1284 (!cos1_bw)) { 1285 DP(NETIF_MSG_LINK, "Total BW can't be zero\n"); 1286 return; 1287 } 1288 1289 cos0_credit_weight = (cos0_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/ 1290 total_bw; 1291 cos1_credit_weight = (cos1_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/ 1292 total_bw; 1293 1294 bnx2x_ets_bw_limit_common(params); 1295 1296 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, cos0_credit_weight); 1297 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, cos1_credit_weight); 1298 1299 REG_WR(bp, PBF_REG_COS0_WEIGHT, cos0_credit_weight); 1300 REG_WR(bp, PBF_REG_COS1_WEIGHT, cos1_credit_weight); 1301 } 1302 1303 int bnx2x_ets_strict(const struct link_params *params, const u8 strict_cos) 1304 { 1305 /* ETS disabled configuration*/ 1306 struct bnx2x *bp = params->bp; 1307 u32 val = 0; 1308 1309 DP(NETIF_MSG_LINK, "ETS enabled strict configuration\n"); 1310 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves 1311 * as strict. Bits 0,1,2 - debug and management entries, 1312 * 3 - COS0 entry, 4 - COS1 entry. 1313 * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT 1314 * bit4 bit3 bit2 bit1 bit0 1315 * MCP and debug are strict 1316 */ 1317 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1F); 1318 /* For strict priority entries defines the number of consecutive slots 1319 * for the highest priority. 1320 */ 1321 REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100); 1322 /* ETS mode disable */ 1323 REG_WR(bp, PBF_REG_ETS_ENABLED, 0); 1324 /* Defines the number of consecutive slots for the strict priority */ 1325 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0x100); 1326 1327 /* Defines the number of consecutive slots for the strict priority */ 1328 REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, strict_cos); 1329 1330 /* Mapping between entry priority to client number (0,1,2 -debug and 1331 * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST) 1332 * 3bits client num. 1333 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0 1334 * dbg0-010 dbg1-001 cos1-100 cos0-011 MCP-000 1335 * dbg0-010 dbg1-001 cos0-011 cos1-100 MCP-000 1336 */ 1337 val = (!strict_cos) ? 0x2318 : 0x22E0; 1338 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, val); 1339 1340 return 0; 1341 } 1342 1343 /******************************************************************/ 1344 /* PFC section */ 1345 /******************************************************************/ 1346 static void bnx2x_update_pfc_xmac(struct link_params *params, 1347 struct link_vars *vars, 1348 u8 is_lb) 1349 { 1350 struct bnx2x *bp = params->bp; 1351 u32 xmac_base; 1352 u32 pause_val, pfc0_val, pfc1_val; 1353 1354 /* XMAC base adrr */ 1355 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; 1356 1357 /* Initialize pause and pfc registers */ 1358 pause_val = 0x18000; 1359 pfc0_val = 0xFFFF8000; 1360 pfc1_val = 0x2; 1361 1362 /* No PFC support */ 1363 if (!(params->feature_config_flags & 1364 FEATURE_CONFIG_PFC_ENABLED)) { 1365 1366 /* RX flow control - Process pause frame in receive direction 1367 */ 1368 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX) 1369 pause_val |= XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN; 1370 1371 /* TX flow control - Send pause packet when buffer is full */ 1372 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) 1373 pause_val |= XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN; 1374 } else {/* PFC support */ 1375 pfc1_val |= XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN | 1376 XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN | 1377 XMAC_PFC_CTRL_HI_REG_RX_PFC_EN | 1378 XMAC_PFC_CTRL_HI_REG_TX_PFC_EN | 1379 XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON; 1380 /* Write pause and PFC registers */ 1381 REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val); 1382 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val); 1383 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val); 1384 pfc1_val &= ~XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON; 1385 1386 } 1387 1388 /* Write pause and PFC registers */ 1389 REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val); 1390 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val); 1391 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val); 1392 1393 1394 /* Set MAC address for source TX Pause/PFC frames */ 1395 REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_LO, 1396 ((params->mac_addr[2] << 24) | 1397 (params->mac_addr[3] << 16) | 1398 (params->mac_addr[4] << 8) | 1399 (params->mac_addr[5]))); 1400 REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_HI, 1401 ((params->mac_addr[0] << 8) | 1402 (params->mac_addr[1]))); 1403 1404 udelay(30); 1405 } 1406 1407 /******************************************************************/ 1408 /* MAC/PBF section */ 1409 /******************************************************************/ 1410 static void bnx2x_set_mdio_clk(struct bnx2x *bp, u32 chip_id, 1411 u32 emac_base) 1412 { 1413 u32 new_mode, cur_mode; 1414 u32 clc_cnt; 1415 /* Set clause 45 mode, slow down the MDIO clock to 2.5MHz 1416 * (a value of 49==0x31) and make sure that the AUTO poll is off 1417 */ 1418 cur_mode = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE); 1419 1420 if (USES_WARPCORE(bp)) 1421 clc_cnt = 74L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT; 1422 else 1423 clc_cnt = 49L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT; 1424 1425 if (((cur_mode & EMAC_MDIO_MODE_CLOCK_CNT) == clc_cnt) && 1426 (cur_mode & (EMAC_MDIO_MODE_CLAUSE_45))) 1427 return; 1428 1429 new_mode = cur_mode & 1430 ~(EMAC_MDIO_MODE_AUTO_POLL | EMAC_MDIO_MODE_CLOCK_CNT); 1431 new_mode |= clc_cnt; 1432 new_mode |= (EMAC_MDIO_MODE_CLAUSE_45); 1433 1434 DP(NETIF_MSG_LINK, "Changing emac_mode from 0x%x to 0x%x\n", 1435 cur_mode, new_mode); 1436 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE, new_mode); 1437 udelay(40); 1438 } 1439 1440 static void bnx2x_set_mdio_emac_per_phy(struct bnx2x *bp, 1441 struct link_params *params) 1442 { 1443 u8 phy_index; 1444 /* Set mdio clock per phy */ 1445 for (phy_index = INT_PHY; phy_index < params->num_phys; 1446 phy_index++) 1447 bnx2x_set_mdio_clk(bp, params->chip_id, 1448 params->phy[phy_index].mdio_ctrl); 1449 } 1450 1451 static u8 bnx2x_is_4_port_mode(struct bnx2x *bp) 1452 { 1453 u32 port4mode_ovwr_val; 1454 /* Check 4-port override enabled */ 1455 port4mode_ovwr_val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR); 1456 if (port4mode_ovwr_val & (1<<0)) { 1457 /* Return 4-port mode override value */ 1458 return ((port4mode_ovwr_val & (1<<1)) == (1<<1)); 1459 } 1460 /* Return 4-port mode from input pin */ 1461 return (u8)REG_RD(bp, MISC_REG_PORT4MODE_EN); 1462 } 1463 1464 static void bnx2x_emac_init(struct link_params *params, 1465 struct link_vars *vars) 1466 { 1467 /* reset and unreset the emac core */ 1468 struct bnx2x *bp = params->bp; 1469 u8 port = params->port; 1470 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; 1471 u32 val; 1472 u16 timeout; 1473 1474 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 1475 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port)); 1476 udelay(5); 1477 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 1478 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port)); 1479 1480 /* init emac - use read-modify-write */ 1481 /* self clear reset */ 1482 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE); 1483 EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET)); 1484 1485 timeout = 200; 1486 do { 1487 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE); 1488 DP(NETIF_MSG_LINK, "EMAC reset reg is %u\n", val); 1489 if (!timeout) { 1490 DP(NETIF_MSG_LINK, "EMAC timeout!\n"); 1491 return; 1492 } 1493 timeout--; 1494 } while (val & EMAC_MODE_RESET); 1495 1496 bnx2x_set_mdio_emac_per_phy(bp, params); 1497 /* Set mac address */ 1498 val = ((params->mac_addr[0] << 8) | 1499 params->mac_addr[1]); 1500 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH, val); 1501 1502 val = ((params->mac_addr[2] << 24) | 1503 (params->mac_addr[3] << 16) | 1504 (params->mac_addr[4] << 8) | 1505 params->mac_addr[5]); 1506 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + 4, val); 1507 } 1508 1509 static void bnx2x_set_xumac_nig(struct link_params *params, 1510 u16 tx_pause_en, 1511 u8 enable) 1512 { 1513 struct bnx2x *bp = params->bp; 1514 1515 REG_WR(bp, params->port ? NIG_REG_P1_MAC_IN_EN : NIG_REG_P0_MAC_IN_EN, 1516 enable); 1517 REG_WR(bp, params->port ? NIG_REG_P1_MAC_OUT_EN : NIG_REG_P0_MAC_OUT_EN, 1518 enable); 1519 REG_WR(bp, params->port ? NIG_REG_P1_MAC_PAUSE_OUT_EN : 1520 NIG_REG_P0_MAC_PAUSE_OUT_EN, tx_pause_en); 1521 } 1522 1523 static void bnx2x_set_umac_rxtx(struct link_params *params, u8 en) 1524 { 1525 u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0; 1526 u32 val; 1527 struct bnx2x *bp = params->bp; 1528 if (!(REG_RD(bp, MISC_REG_RESET_REG_2) & 1529 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port))) 1530 return; 1531 val = REG_RD(bp, umac_base + UMAC_REG_COMMAND_CONFIG); 1532 if (en) 1533 val |= (UMAC_COMMAND_CONFIG_REG_TX_ENA | 1534 UMAC_COMMAND_CONFIG_REG_RX_ENA); 1535 else 1536 val &= ~(UMAC_COMMAND_CONFIG_REG_TX_ENA | 1537 UMAC_COMMAND_CONFIG_REG_RX_ENA); 1538 /* Disable RX and TX */ 1539 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val); 1540 } 1541 1542 static void bnx2x_umac_enable(struct link_params *params, 1543 struct link_vars *vars, u8 lb) 1544 { 1545 u32 val; 1546 u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0; 1547 struct bnx2x *bp = params->bp; 1548 /* Reset UMAC */ 1549 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 1550 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port)); 1551 usleep_range(1000, 2000); 1552 1553 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 1554 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port)); 1555 1556 DP(NETIF_MSG_LINK, "enabling UMAC\n"); 1557 1558 /* This register opens the gate for the UMAC despite its name */ 1559 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1); 1560 1561 val = UMAC_COMMAND_CONFIG_REG_PROMIS_EN | 1562 UMAC_COMMAND_CONFIG_REG_PAD_EN | 1563 UMAC_COMMAND_CONFIG_REG_SW_RESET | 1564 UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK; 1565 switch (vars->line_speed) { 1566 case SPEED_10: 1567 val |= (0<<2); 1568 break; 1569 case SPEED_100: 1570 val |= (1<<2); 1571 break; 1572 case SPEED_1000: 1573 val |= (2<<2); 1574 break; 1575 case SPEED_2500: 1576 val |= (3<<2); 1577 break; 1578 default: 1579 DP(NETIF_MSG_LINK, "Invalid speed for UMAC %d\n", 1580 vars->line_speed); 1581 break; 1582 } 1583 if (!(vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)) 1584 val |= UMAC_COMMAND_CONFIG_REG_IGNORE_TX_PAUSE; 1585 1586 if (!(vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)) 1587 val |= UMAC_COMMAND_CONFIG_REG_PAUSE_IGNORE; 1588 1589 if (vars->duplex == DUPLEX_HALF) 1590 val |= UMAC_COMMAND_CONFIG_REG_HD_ENA; 1591 1592 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val); 1593 udelay(50); 1594 1595 /* Configure UMAC for EEE */ 1596 if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) { 1597 DP(NETIF_MSG_LINK, "configured UMAC for EEE\n"); 1598 REG_WR(bp, umac_base + UMAC_REG_UMAC_EEE_CTRL, 1599 UMAC_UMAC_EEE_CTRL_REG_EEE_EN); 1600 REG_WR(bp, umac_base + UMAC_REG_EEE_WAKE_TIMER, 0x11); 1601 } else { 1602 REG_WR(bp, umac_base + UMAC_REG_UMAC_EEE_CTRL, 0x0); 1603 } 1604 1605 /* Set MAC address for source TX Pause/PFC frames (under SW reset) */ 1606 REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR0, 1607 ((params->mac_addr[2] << 24) | 1608 (params->mac_addr[3] << 16) | 1609 (params->mac_addr[4] << 8) | 1610 (params->mac_addr[5]))); 1611 REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR1, 1612 ((params->mac_addr[0] << 8) | 1613 (params->mac_addr[1]))); 1614 1615 /* Enable RX and TX */ 1616 val &= ~UMAC_COMMAND_CONFIG_REG_PAD_EN; 1617 val |= UMAC_COMMAND_CONFIG_REG_TX_ENA | 1618 UMAC_COMMAND_CONFIG_REG_RX_ENA; 1619 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val); 1620 udelay(50); 1621 1622 /* Remove SW Reset */ 1623 val &= ~UMAC_COMMAND_CONFIG_REG_SW_RESET; 1624 1625 /* Check loopback mode */ 1626 if (lb) 1627 val |= UMAC_COMMAND_CONFIG_REG_LOOP_ENA; 1628 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val); 1629 1630 /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame 1631 * length used by the MAC receive logic to check frames. 1632 */ 1633 REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710); 1634 bnx2x_set_xumac_nig(params, 1635 ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1); 1636 vars->mac_type = MAC_TYPE_UMAC; 1637 1638 } 1639 1640 /* Define the XMAC mode */ 1641 static void bnx2x_xmac_init(struct link_params *params, u32 max_speed) 1642 { 1643 struct bnx2x *bp = params->bp; 1644 u32 is_port4mode = bnx2x_is_4_port_mode(bp); 1645 1646 /* In 4-port mode, need to set the mode only once, so if XMAC is 1647 * already out of reset, it means the mode has already been set, 1648 * and it must not* reset the XMAC again, since it controls both 1649 * ports of the path 1650 */ 1651 1652 if (((CHIP_NUM(bp) == CHIP_NUM_57840_4_10) || 1653 (CHIP_NUM(bp) == CHIP_NUM_57840_2_20) || 1654 (CHIP_NUM(bp) == CHIP_NUM_57840_OBSOLETE)) && 1655 is_port4mode && 1656 (REG_RD(bp, MISC_REG_RESET_REG_2) & 1657 MISC_REGISTERS_RESET_REG_2_XMAC)) { 1658 DP(NETIF_MSG_LINK, 1659 "XMAC already out of reset in 4-port mode\n"); 1660 return; 1661 } 1662 1663 /* Hard reset */ 1664 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 1665 MISC_REGISTERS_RESET_REG_2_XMAC); 1666 usleep_range(1000, 2000); 1667 1668 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 1669 MISC_REGISTERS_RESET_REG_2_XMAC); 1670 if (is_port4mode) { 1671 DP(NETIF_MSG_LINK, "Init XMAC to 2 ports x 10G per path\n"); 1672 1673 /* Set the number of ports on the system side to up to 2 */ 1674 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 1); 1675 1676 /* Set the number of ports on the Warp Core to 10G */ 1677 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3); 1678 } else { 1679 /* Set the number of ports on the system side to 1 */ 1680 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 0); 1681 if (max_speed == SPEED_10000) { 1682 DP(NETIF_MSG_LINK, 1683 "Init XMAC to 10G x 1 port per path\n"); 1684 /* Set the number of ports on the Warp Core to 10G */ 1685 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3); 1686 } else { 1687 DP(NETIF_MSG_LINK, 1688 "Init XMAC to 20G x 2 ports per path\n"); 1689 /* Set the number of ports on the Warp Core to 20G */ 1690 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 1); 1691 } 1692 } 1693 /* Soft reset */ 1694 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 1695 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT); 1696 usleep_range(1000, 2000); 1697 1698 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 1699 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT); 1700 1701 } 1702 1703 static void bnx2x_set_xmac_rxtx(struct link_params *params, u8 en) 1704 { 1705 u8 port = params->port; 1706 struct bnx2x *bp = params->bp; 1707 u32 pfc_ctrl, xmac_base = (port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; 1708 u32 val; 1709 1710 if (REG_RD(bp, MISC_REG_RESET_REG_2) & 1711 MISC_REGISTERS_RESET_REG_2_XMAC) { 1712 /* Send an indication to change the state in the NIG back to XON 1713 * Clearing this bit enables the next set of this bit to get 1714 * rising edge 1715 */ 1716 pfc_ctrl = REG_RD(bp, xmac_base + XMAC_REG_PFC_CTRL_HI); 1717 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, 1718 (pfc_ctrl & ~(1<<1))); 1719 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, 1720 (pfc_ctrl | (1<<1))); 1721 DP(NETIF_MSG_LINK, "Disable XMAC on port %x\n", port); 1722 val = REG_RD(bp, xmac_base + XMAC_REG_CTRL); 1723 if (en) 1724 val |= (XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN); 1725 else 1726 val &= ~(XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN); 1727 REG_WR(bp, xmac_base + XMAC_REG_CTRL, val); 1728 } 1729 } 1730 1731 static int bnx2x_xmac_enable(struct link_params *params, 1732 struct link_vars *vars, u8 lb) 1733 { 1734 u32 val, xmac_base; 1735 struct bnx2x *bp = params->bp; 1736 DP(NETIF_MSG_LINK, "enabling XMAC\n"); 1737 1738 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; 1739 1740 bnx2x_xmac_init(params, vars->line_speed); 1741 1742 /* This register determines on which events the MAC will assert 1743 * error on the i/f to the NIG along w/ EOP. 1744 */ 1745 1746 /* This register tells the NIG whether to send traffic to UMAC 1747 * or XMAC 1748 */ 1749 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 0); 1750 1751 /* When XMAC is in XLGMII mode, disable sending idles for fault 1752 * detection. 1753 */ 1754 if (!(params->phy[INT_PHY].flags & FLAGS_TX_ERROR_CHECK)) { 1755 REG_WR(bp, xmac_base + XMAC_REG_RX_LSS_CTRL, 1756 (XMAC_RX_LSS_CTRL_REG_LOCAL_FAULT_DISABLE | 1757 XMAC_RX_LSS_CTRL_REG_REMOTE_FAULT_DISABLE)); 1758 REG_WR(bp, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0); 1759 REG_WR(bp, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 1760 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS | 1761 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS); 1762 } 1763 /* Set Max packet size */ 1764 REG_WR(bp, xmac_base + XMAC_REG_RX_MAX_SIZE, 0x2710); 1765 1766 /* CRC append for Tx packets */ 1767 REG_WR(bp, xmac_base + XMAC_REG_TX_CTRL, 0xC800); 1768 1769 /* update PFC */ 1770 bnx2x_update_pfc_xmac(params, vars, 0); 1771 1772 if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) { 1773 DP(NETIF_MSG_LINK, "Setting XMAC for EEE\n"); 1774 REG_WR(bp, xmac_base + XMAC_REG_EEE_TIMERS_HI, 0x1380008); 1775 REG_WR(bp, xmac_base + XMAC_REG_EEE_CTRL, 0x1); 1776 } else { 1777 REG_WR(bp, xmac_base + XMAC_REG_EEE_CTRL, 0x0); 1778 } 1779 1780 /* Enable TX and RX */ 1781 val = XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN; 1782 1783 /* Set MAC in XLGMII mode for dual-mode */ 1784 if ((vars->line_speed == SPEED_20000) && 1785 (params->phy[INT_PHY].supported & 1786 SUPPORTED_20000baseKR2_Full)) 1787 val |= XMAC_CTRL_REG_XLGMII_ALIGN_ENB; 1788 1789 /* Check loopback mode */ 1790 if (lb) 1791 val |= XMAC_CTRL_REG_LINE_LOCAL_LPBK; 1792 REG_WR(bp, xmac_base + XMAC_REG_CTRL, val); 1793 bnx2x_set_xumac_nig(params, 1794 ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1); 1795 1796 vars->mac_type = MAC_TYPE_XMAC; 1797 1798 return 0; 1799 } 1800 1801 static int bnx2x_emac_enable(struct link_params *params, 1802 struct link_vars *vars, u8 lb) 1803 { 1804 struct bnx2x *bp = params->bp; 1805 u8 port = params->port; 1806 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; 1807 u32 val; 1808 1809 DP(NETIF_MSG_LINK, "enabling EMAC\n"); 1810 1811 /* Disable BMAC */ 1812 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 1813 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); 1814 1815 /* enable emac and not bmac */ 1816 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 1); 1817 1818 /* ASIC */ 1819 if (vars->phy_flags & PHY_XGXS_FLAG) { 1820 u32 ser_lane = ((params->lane_config & 1821 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >> 1822 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT); 1823 1824 DP(NETIF_MSG_LINK, "XGXS\n"); 1825 /* select the master lanes (out of 0-3) */ 1826 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, ser_lane); 1827 /* select XGXS */ 1828 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1); 1829 1830 } else { /* SerDes */ 1831 DP(NETIF_MSG_LINK, "SerDes\n"); 1832 /* select SerDes */ 1833 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0); 1834 } 1835 1836 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_RX_MODE, 1837 EMAC_RX_MODE_RESET); 1838 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE, 1839 EMAC_TX_MODE_RESET); 1840 1841 /* pause enable/disable */ 1842 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_RX_MODE, 1843 EMAC_RX_MODE_FLOW_EN); 1844 1845 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_TX_MODE, 1846 (EMAC_TX_MODE_EXT_PAUSE_EN | 1847 EMAC_TX_MODE_FLOW_EN)); 1848 if (!(params->feature_config_flags & 1849 FEATURE_CONFIG_PFC_ENABLED)) { 1850 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX) 1851 bnx2x_bits_en(bp, emac_base + 1852 EMAC_REG_EMAC_RX_MODE, 1853 EMAC_RX_MODE_FLOW_EN); 1854 1855 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) 1856 bnx2x_bits_en(bp, emac_base + 1857 EMAC_REG_EMAC_TX_MODE, 1858 (EMAC_TX_MODE_EXT_PAUSE_EN | 1859 EMAC_TX_MODE_FLOW_EN)); 1860 } else 1861 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE, 1862 EMAC_TX_MODE_FLOW_EN); 1863 1864 /* KEEP_VLAN_TAG, promiscuous */ 1865 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE); 1866 val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS; 1867 1868 /* Setting this bit causes MAC control frames (except for pause 1869 * frames) to be passed on for processing. This setting has no 1870 * affect on the operation of the pause frames. This bit effects 1871 * all packets regardless of RX Parser packet sorting logic. 1872 * Turn the PFC off to make sure we are in Xon state before 1873 * enabling it. 1874 */ 1875 EMAC_WR(bp, EMAC_REG_RX_PFC_MODE, 0); 1876 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) { 1877 DP(NETIF_MSG_LINK, "PFC is enabled\n"); 1878 /* Enable PFC again */ 1879 EMAC_WR(bp, EMAC_REG_RX_PFC_MODE, 1880 EMAC_REG_RX_PFC_MODE_RX_EN | 1881 EMAC_REG_RX_PFC_MODE_TX_EN | 1882 EMAC_REG_RX_PFC_MODE_PRIORITIES); 1883 1884 EMAC_WR(bp, EMAC_REG_RX_PFC_PARAM, 1885 ((0x0101 << 1886 EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT) | 1887 (0x00ff << 1888 EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT))); 1889 val |= EMAC_RX_MODE_KEEP_MAC_CONTROL; 1890 } 1891 EMAC_WR(bp, EMAC_REG_EMAC_RX_MODE, val); 1892 1893 /* Set Loopback */ 1894 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE); 1895 if (lb) 1896 val |= 0x810; 1897 else 1898 val &= ~0x810; 1899 EMAC_WR(bp, EMAC_REG_EMAC_MODE, val); 1900 1901 /* Enable emac */ 1902 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 1); 1903 1904 /* Enable emac for jumbo packets */ 1905 EMAC_WR(bp, EMAC_REG_EMAC_RX_MTU_SIZE, 1906 (EMAC_RX_MTU_SIZE_JUMBO_ENA | 1907 (ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD))); 1908 1909 /* Strip CRC */ 1910 REG_WR(bp, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1); 1911 1912 /* Disable the NIG in/out to the bmac */ 1913 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x0); 1914 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0); 1915 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x0); 1916 1917 /* Enable the NIG in/out to the emac */ 1918 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x1); 1919 val = 0; 1920 if ((params->feature_config_flags & 1921 FEATURE_CONFIG_PFC_ENABLED) || 1922 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)) 1923 val = 1; 1924 1925 REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val); 1926 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1); 1927 1928 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x0); 1929 1930 vars->mac_type = MAC_TYPE_EMAC; 1931 return 0; 1932 } 1933 1934 static void bnx2x_update_pfc_bmac1(struct link_params *params, 1935 struct link_vars *vars) 1936 { 1937 u32 wb_data[2]; 1938 struct bnx2x *bp = params->bp; 1939 u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM : 1940 NIG_REG_INGRESS_BMAC0_MEM; 1941 1942 u32 val = 0x14; 1943 if ((!(params->feature_config_flags & 1944 FEATURE_CONFIG_PFC_ENABLED)) && 1945 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)) 1946 /* Enable BigMAC to react on received Pause packets */ 1947 val |= (1<<5); 1948 wb_data[0] = val; 1949 wb_data[1] = 0; 1950 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_CONTROL, wb_data, 2); 1951 1952 /* TX control */ 1953 val = 0xc0; 1954 if (!(params->feature_config_flags & 1955 FEATURE_CONFIG_PFC_ENABLED) && 1956 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)) 1957 val |= 0x800000; 1958 wb_data[0] = val; 1959 wb_data[1] = 0; 1960 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_CONTROL, wb_data, 2); 1961 } 1962 1963 static void bnx2x_update_pfc_bmac2(struct link_params *params, 1964 struct link_vars *vars, 1965 u8 is_lb) 1966 { 1967 /* Set rx control: Strip CRC and enable BigMAC to relay 1968 * control packets to the system as well 1969 */ 1970 u32 wb_data[2]; 1971 struct bnx2x *bp = params->bp; 1972 u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM : 1973 NIG_REG_INGRESS_BMAC0_MEM; 1974 u32 val = 0x14; 1975 1976 if ((!(params->feature_config_flags & 1977 FEATURE_CONFIG_PFC_ENABLED)) && 1978 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)) 1979 /* Enable BigMAC to react on received Pause packets */ 1980 val |= (1<<5); 1981 wb_data[0] = val; 1982 wb_data[1] = 0; 1983 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_CONTROL, wb_data, 2); 1984 udelay(30); 1985 1986 /* Tx control */ 1987 val = 0xc0; 1988 if (!(params->feature_config_flags & 1989 FEATURE_CONFIG_PFC_ENABLED) && 1990 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)) 1991 val |= 0x800000; 1992 wb_data[0] = val; 1993 wb_data[1] = 0; 1994 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_CONTROL, wb_data, 2); 1995 1996 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) { 1997 DP(NETIF_MSG_LINK, "PFC is enabled\n"); 1998 /* Enable PFC RX & TX & STATS and set 8 COS */ 1999 wb_data[0] = 0x0; 2000 wb_data[0] |= (1<<0); /* RX */ 2001 wb_data[0] |= (1<<1); /* TX */ 2002 wb_data[0] |= (1<<2); /* Force initial Xon */ 2003 wb_data[0] |= (1<<3); /* 8 cos */ 2004 wb_data[0] |= (1<<5); /* STATS */ 2005 wb_data[1] = 0; 2006 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, 2007 wb_data, 2); 2008 /* Clear the force Xon */ 2009 wb_data[0] &= ~(1<<2); 2010 } else { 2011 DP(NETIF_MSG_LINK, "PFC is disabled\n"); 2012 /* Disable PFC RX & TX & STATS and set 8 COS */ 2013 wb_data[0] = 0x8; 2014 wb_data[1] = 0; 2015 } 2016 2017 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, wb_data, 2); 2018 2019 /* Set Time (based unit is 512 bit time) between automatic 2020 * re-sending of PP packets amd enable automatic re-send of 2021 * Per-Priroity Packet as long as pp_gen is asserted and 2022 * pp_disable is low. 2023 */ 2024 val = 0x8000; 2025 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) 2026 val |= (1<<16); /* enable automatic re-send */ 2027 2028 wb_data[0] = val; 2029 wb_data[1] = 0; 2030 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_PAUSE_CONTROL, 2031 wb_data, 2); 2032 2033 /* mac control */ 2034 val = 0x3; /* Enable RX and TX */ 2035 if (is_lb) { 2036 val |= 0x4; /* Local loopback */ 2037 DP(NETIF_MSG_LINK, "enable bmac loopback\n"); 2038 } 2039 /* When PFC enabled, Pass pause frames towards the NIG. */ 2040 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) 2041 val |= ((1<<6)|(1<<5)); 2042 2043 wb_data[0] = val; 2044 wb_data[1] = 0; 2045 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2); 2046 } 2047 2048 /****************************************************************************** 2049 * Description: 2050 * This function is needed because NIG ARB_CREDIT_WEIGHT_X are 2051 * not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable. 2052 ******************************************************************************/ 2053 static int bnx2x_pfc_nig_rx_priority_mask(struct bnx2x *bp, 2054 u8 cos_entry, 2055 u32 priority_mask, u8 port) 2056 { 2057 u32 nig_reg_rx_priority_mask_add = 0; 2058 2059 switch (cos_entry) { 2060 case 0: 2061 nig_reg_rx_priority_mask_add = (port) ? 2062 NIG_REG_P1_RX_COS0_PRIORITY_MASK : 2063 NIG_REG_P0_RX_COS0_PRIORITY_MASK; 2064 break; 2065 case 1: 2066 nig_reg_rx_priority_mask_add = (port) ? 2067 NIG_REG_P1_RX_COS1_PRIORITY_MASK : 2068 NIG_REG_P0_RX_COS1_PRIORITY_MASK; 2069 break; 2070 case 2: 2071 nig_reg_rx_priority_mask_add = (port) ? 2072 NIG_REG_P1_RX_COS2_PRIORITY_MASK : 2073 NIG_REG_P0_RX_COS2_PRIORITY_MASK; 2074 break; 2075 case 3: 2076 if (port) 2077 return -EINVAL; 2078 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS3_PRIORITY_MASK; 2079 break; 2080 case 4: 2081 if (port) 2082 return -EINVAL; 2083 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS4_PRIORITY_MASK; 2084 break; 2085 case 5: 2086 if (port) 2087 return -EINVAL; 2088 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS5_PRIORITY_MASK; 2089 break; 2090 } 2091 2092 REG_WR(bp, nig_reg_rx_priority_mask_add, priority_mask); 2093 2094 return 0; 2095 } 2096 static void bnx2x_update_mng(struct link_params *params, u32 link_status) 2097 { 2098 struct bnx2x *bp = params->bp; 2099 2100 REG_WR(bp, params->shmem_base + 2101 offsetof(struct shmem_region, 2102 port_mb[params->port].link_status), link_status); 2103 } 2104 2105 static void bnx2x_update_link_attr(struct link_params *params, u32 link_attr) 2106 { 2107 struct bnx2x *bp = params->bp; 2108 2109 if (SHMEM2_HAS(bp, link_attr_sync)) 2110 REG_WR(bp, params->shmem2_base + 2111 offsetof(struct shmem2_region, 2112 link_attr_sync[params->port]), link_attr); 2113 } 2114 2115 static void bnx2x_update_pfc_nig(struct link_params *params, 2116 struct link_vars *vars, 2117 struct bnx2x_nig_brb_pfc_port_params *nig_params) 2118 { 2119 u32 xcm_mask = 0, ppp_enable = 0, pause_enable = 0, llfc_out_en = 0; 2120 u32 llfc_enable = 0, xcm_out_en = 0, hwpfc_enable = 0; 2121 u32 pkt_priority_to_cos = 0; 2122 struct bnx2x *bp = params->bp; 2123 u8 port = params->port; 2124 2125 int set_pfc = params->feature_config_flags & 2126 FEATURE_CONFIG_PFC_ENABLED; 2127 DP(NETIF_MSG_LINK, "updating pfc nig parameters\n"); 2128 2129 /* When NIG_LLH0_XCM_MASK_REG_LLHX_XCM_MASK_BCN bit is set 2130 * MAC control frames (that are not pause packets) 2131 * will be forwarded to the XCM. 2132 */ 2133 xcm_mask = REG_RD(bp, port ? NIG_REG_LLH1_XCM_MASK : 2134 NIG_REG_LLH0_XCM_MASK); 2135 /* NIG params will override non PFC params, since it's possible to 2136 * do transition from PFC to SAFC 2137 */ 2138 if (set_pfc) { 2139 pause_enable = 0; 2140 llfc_out_en = 0; 2141 llfc_enable = 0; 2142 if (CHIP_IS_E3(bp)) 2143 ppp_enable = 0; 2144 else 2145 ppp_enable = 1; 2146 xcm_mask &= ~(port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN : 2147 NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN); 2148 xcm_out_en = 0; 2149 hwpfc_enable = 1; 2150 } else { 2151 if (nig_params) { 2152 llfc_out_en = nig_params->llfc_out_en; 2153 llfc_enable = nig_params->llfc_enable; 2154 pause_enable = nig_params->pause_enable; 2155 } else /* Default non PFC mode - PAUSE */ 2156 pause_enable = 1; 2157 2158 xcm_mask |= (port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN : 2159 NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN); 2160 xcm_out_en = 1; 2161 } 2162 2163 if (CHIP_IS_E3(bp)) 2164 REG_WR(bp, port ? NIG_REG_BRB1_PAUSE_IN_EN : 2165 NIG_REG_BRB0_PAUSE_IN_EN, pause_enable); 2166 REG_WR(bp, port ? NIG_REG_LLFC_OUT_EN_1 : 2167 NIG_REG_LLFC_OUT_EN_0, llfc_out_en); 2168 REG_WR(bp, port ? NIG_REG_LLFC_ENABLE_1 : 2169 NIG_REG_LLFC_ENABLE_0, llfc_enable); 2170 REG_WR(bp, port ? NIG_REG_PAUSE_ENABLE_1 : 2171 NIG_REG_PAUSE_ENABLE_0, pause_enable); 2172 2173 REG_WR(bp, port ? NIG_REG_PPP_ENABLE_1 : 2174 NIG_REG_PPP_ENABLE_0, ppp_enable); 2175 2176 REG_WR(bp, port ? NIG_REG_LLH1_XCM_MASK : 2177 NIG_REG_LLH0_XCM_MASK, xcm_mask); 2178 2179 REG_WR(bp, port ? NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 : 2180 NIG_REG_LLFC_EGRESS_SRC_ENABLE_0, 0x7); 2181 2182 /* Output enable for RX_XCM # IF */ 2183 REG_WR(bp, port ? NIG_REG_XCM1_OUT_EN : 2184 NIG_REG_XCM0_OUT_EN, xcm_out_en); 2185 2186 /* HW PFC TX enable */ 2187 REG_WR(bp, port ? NIG_REG_P1_HWPFC_ENABLE : 2188 NIG_REG_P0_HWPFC_ENABLE, hwpfc_enable); 2189 2190 if (nig_params) { 2191 u8 i = 0; 2192 pkt_priority_to_cos = nig_params->pkt_priority_to_cos; 2193 2194 for (i = 0; i < nig_params->num_of_rx_cos_priority_mask; i++) 2195 bnx2x_pfc_nig_rx_priority_mask(bp, i, 2196 nig_params->rx_cos_priority_mask[i], port); 2197 2198 REG_WR(bp, port ? NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 : 2199 NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0, 2200 nig_params->llfc_high_priority_classes); 2201 2202 REG_WR(bp, port ? NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 : 2203 NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0, 2204 nig_params->llfc_low_priority_classes); 2205 } 2206 REG_WR(bp, port ? NIG_REG_P1_PKT_PRIORITY_TO_COS : 2207 NIG_REG_P0_PKT_PRIORITY_TO_COS, 2208 pkt_priority_to_cos); 2209 } 2210 2211 int bnx2x_update_pfc(struct link_params *params, 2212 struct link_vars *vars, 2213 struct bnx2x_nig_brb_pfc_port_params *pfc_params) 2214 { 2215 /* The PFC and pause are orthogonal to one another, meaning when 2216 * PFC is enabled, the pause are disabled, and when PFC is 2217 * disabled, pause are set according to the pause result. 2218 */ 2219 u32 val; 2220 struct bnx2x *bp = params->bp; 2221 u8 bmac_loopback = (params->loopback_mode == LOOPBACK_BMAC); 2222 2223 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) 2224 vars->link_status |= LINK_STATUS_PFC_ENABLED; 2225 else 2226 vars->link_status &= ~LINK_STATUS_PFC_ENABLED; 2227 2228 bnx2x_update_mng(params, vars->link_status); 2229 2230 /* Update NIG params */ 2231 bnx2x_update_pfc_nig(params, vars, pfc_params); 2232 2233 if (!vars->link_up) 2234 return 0; 2235 2236 DP(NETIF_MSG_LINK, "About to update PFC in BMAC\n"); 2237 2238 if (CHIP_IS_E3(bp)) { 2239 if (vars->mac_type == MAC_TYPE_XMAC) 2240 bnx2x_update_pfc_xmac(params, vars, 0); 2241 } else { 2242 val = REG_RD(bp, MISC_REG_RESET_REG_2); 2243 if ((val & 2244 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port)) 2245 == 0) { 2246 DP(NETIF_MSG_LINK, "About to update PFC in EMAC\n"); 2247 bnx2x_emac_enable(params, vars, 0); 2248 return 0; 2249 } 2250 if (CHIP_IS_E2(bp)) 2251 bnx2x_update_pfc_bmac2(params, vars, bmac_loopback); 2252 else 2253 bnx2x_update_pfc_bmac1(params, vars); 2254 2255 val = 0; 2256 if ((params->feature_config_flags & 2257 FEATURE_CONFIG_PFC_ENABLED) || 2258 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)) 2259 val = 1; 2260 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port*4, val); 2261 } 2262 return 0; 2263 } 2264 2265 static int bnx2x_bmac1_enable(struct link_params *params, 2266 struct link_vars *vars, 2267 u8 is_lb) 2268 { 2269 struct bnx2x *bp = params->bp; 2270 u8 port = params->port; 2271 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM : 2272 NIG_REG_INGRESS_BMAC0_MEM; 2273 u32 wb_data[2]; 2274 u32 val; 2275 2276 DP(NETIF_MSG_LINK, "Enabling BigMAC1\n"); 2277 2278 /* XGXS control */ 2279 wb_data[0] = 0x3c; 2280 wb_data[1] = 0; 2281 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_XGXS_CONTROL, 2282 wb_data, 2); 2283 2284 /* TX MAC SA */ 2285 wb_data[0] = ((params->mac_addr[2] << 24) | 2286 (params->mac_addr[3] << 16) | 2287 (params->mac_addr[4] << 8) | 2288 params->mac_addr[5]); 2289 wb_data[1] = ((params->mac_addr[0] << 8) | 2290 params->mac_addr[1]); 2291 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR, wb_data, 2); 2292 2293 /* MAC control */ 2294 val = 0x3; 2295 if (is_lb) { 2296 val |= 0x4; 2297 DP(NETIF_MSG_LINK, "enable bmac loopback\n"); 2298 } 2299 wb_data[0] = val; 2300 wb_data[1] = 0; 2301 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL, wb_data, 2); 2302 2303 /* Set rx mtu */ 2304 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD; 2305 wb_data[1] = 0; 2306 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE, wb_data, 2); 2307 2308 bnx2x_update_pfc_bmac1(params, vars); 2309 2310 /* Set tx mtu */ 2311 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD; 2312 wb_data[1] = 0; 2313 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE, wb_data, 2); 2314 2315 /* Set cnt max size */ 2316 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD; 2317 wb_data[1] = 0; 2318 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE, wb_data, 2); 2319 2320 /* Configure SAFC */ 2321 wb_data[0] = 0x1000200; 2322 wb_data[1] = 0; 2323 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS, 2324 wb_data, 2); 2325 2326 return 0; 2327 } 2328 2329 static int bnx2x_bmac2_enable(struct link_params *params, 2330 struct link_vars *vars, 2331 u8 is_lb) 2332 { 2333 struct bnx2x *bp = params->bp; 2334 u8 port = params->port; 2335 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM : 2336 NIG_REG_INGRESS_BMAC0_MEM; 2337 u32 wb_data[2]; 2338 2339 DP(NETIF_MSG_LINK, "Enabling BigMAC2\n"); 2340 2341 wb_data[0] = 0; 2342 wb_data[1] = 0; 2343 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2); 2344 udelay(30); 2345 2346 /* XGXS control: Reset phy HW, MDIO registers, PHY PLL and BMAC */ 2347 wb_data[0] = 0x3c; 2348 wb_data[1] = 0; 2349 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_XGXS_CONTROL, 2350 wb_data, 2); 2351 2352 udelay(30); 2353 2354 /* TX MAC SA */ 2355 wb_data[0] = ((params->mac_addr[2] << 24) | 2356 (params->mac_addr[3] << 16) | 2357 (params->mac_addr[4] << 8) | 2358 params->mac_addr[5]); 2359 wb_data[1] = ((params->mac_addr[0] << 8) | 2360 params->mac_addr[1]); 2361 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_SOURCE_ADDR, 2362 wb_data, 2); 2363 2364 udelay(30); 2365 2366 /* Configure SAFC */ 2367 wb_data[0] = 0x1000200; 2368 wb_data[1] = 0; 2369 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS, 2370 wb_data, 2); 2371 udelay(30); 2372 2373 /* Set RX MTU */ 2374 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD; 2375 wb_data[1] = 0; 2376 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_MAX_SIZE, wb_data, 2); 2377 udelay(30); 2378 2379 /* Set TX MTU */ 2380 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD; 2381 wb_data[1] = 0; 2382 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_MAX_SIZE, wb_data, 2); 2383 udelay(30); 2384 /* Set cnt max size */ 2385 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD - 2; 2386 wb_data[1] = 0; 2387 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_CNT_MAX_SIZE, wb_data, 2); 2388 udelay(30); 2389 bnx2x_update_pfc_bmac2(params, vars, is_lb); 2390 2391 return 0; 2392 } 2393 2394 static int bnx2x_bmac_enable(struct link_params *params, 2395 struct link_vars *vars, 2396 u8 is_lb, u8 reset_bmac) 2397 { 2398 int rc = 0; 2399 u8 port = params->port; 2400 struct bnx2x *bp = params->bp; 2401 u32 val; 2402 /* Reset and unreset the BigMac */ 2403 if (reset_bmac) { 2404 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 2405 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); 2406 usleep_range(1000, 2000); 2407 } 2408 2409 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 2410 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); 2411 2412 /* Enable access for bmac registers */ 2413 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1); 2414 2415 /* Enable BMAC according to BMAC type*/ 2416 if (CHIP_IS_E2(bp)) 2417 rc = bnx2x_bmac2_enable(params, vars, is_lb); 2418 else 2419 rc = bnx2x_bmac1_enable(params, vars, is_lb); 2420 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1); 2421 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0); 2422 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0); 2423 val = 0; 2424 if ((params->feature_config_flags & 2425 FEATURE_CONFIG_PFC_ENABLED) || 2426 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)) 2427 val = 1; 2428 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val); 2429 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0); 2430 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x0); 2431 REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0); 2432 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x1); 2433 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x1); 2434 2435 vars->mac_type = MAC_TYPE_BMAC; 2436 return rc; 2437 } 2438 2439 static void bnx2x_set_bmac_rx(struct bnx2x *bp, u32 chip_id, u8 port, u8 en) 2440 { 2441 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM : 2442 NIG_REG_INGRESS_BMAC0_MEM; 2443 u32 wb_data[2]; 2444 u32 nig_bmac_enable = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4); 2445 2446 if (CHIP_IS_E2(bp)) 2447 bmac_addr += BIGMAC2_REGISTER_BMAC_CONTROL; 2448 else 2449 bmac_addr += BIGMAC_REGISTER_BMAC_CONTROL; 2450 /* Only if the bmac is out of reset */ 2451 if (REG_RD(bp, MISC_REG_RESET_REG_2) & 2452 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) && 2453 nig_bmac_enable) { 2454 /* Clear Rx Enable bit in BMAC_CONTROL register */ 2455 REG_RD_DMAE(bp, bmac_addr, wb_data, 2); 2456 if (en) 2457 wb_data[0] |= BMAC_CONTROL_RX_ENABLE; 2458 else 2459 wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE; 2460 REG_WR_DMAE(bp, bmac_addr, wb_data, 2); 2461 usleep_range(1000, 2000); 2462 } 2463 } 2464 2465 static int bnx2x_pbf_update(struct link_params *params, u32 flow_ctrl, 2466 u32 line_speed) 2467 { 2468 struct bnx2x *bp = params->bp; 2469 u8 port = params->port; 2470 u32 init_crd, crd; 2471 u32 count = 1000; 2472 2473 /* Disable port */ 2474 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1); 2475 2476 /* Wait for init credit */ 2477 init_crd = REG_RD(bp, PBF_REG_P0_INIT_CRD + port*4); 2478 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8); 2479 DP(NETIF_MSG_LINK, "init_crd 0x%x crd 0x%x\n", init_crd, crd); 2480 2481 while ((init_crd != crd) && count) { 2482 usleep_range(5000, 10000); 2483 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8); 2484 count--; 2485 } 2486 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8); 2487 if (init_crd != crd) { 2488 DP(NETIF_MSG_LINK, "BUG! init_crd 0x%x != crd 0x%x\n", 2489 init_crd, crd); 2490 return -EINVAL; 2491 } 2492 2493 if (flow_ctrl & BNX2X_FLOW_CTRL_RX || 2494 line_speed == SPEED_10 || 2495 line_speed == SPEED_100 || 2496 line_speed == SPEED_1000 || 2497 line_speed == SPEED_2500) { 2498 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 1); 2499 /* Update threshold */ 2500 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, 0); 2501 /* Update init credit */ 2502 init_crd = 778; /* (800-18-4) */ 2503 2504 } else { 2505 u32 thresh = (ETH_MAX_JUMBO_PACKET_SIZE + 2506 ETH_OVREHEAD)/16; 2507 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0); 2508 /* Update threshold */ 2509 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, thresh); 2510 /* Update init credit */ 2511 switch (line_speed) { 2512 case SPEED_10000: 2513 init_crd = thresh + 553 - 22; 2514 break; 2515 default: 2516 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n", 2517 line_speed); 2518 return -EINVAL; 2519 } 2520 } 2521 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, init_crd); 2522 DP(NETIF_MSG_LINK, "PBF updated to speed %d credit %d\n", 2523 line_speed, init_crd); 2524 2525 /* Probe the credit changes */ 2526 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x1); 2527 usleep_range(5000, 10000); 2528 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x0); 2529 2530 /* Enable port */ 2531 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0); 2532 return 0; 2533 } 2534 2535 /** 2536 * bnx2x_get_emac_base - retrive emac base address 2537 * 2538 * @bp: driver handle 2539 * @mdc_mdio_access: access type 2540 * @port: port id 2541 * 2542 * This function selects the MDC/MDIO access (through emac0 or 2543 * emac1) depend on the mdc_mdio_access, port, port swapped. Each 2544 * phy has a default access mode, which could also be overridden 2545 * by nvram configuration. This parameter, whether this is the 2546 * default phy configuration, or the nvram overrun 2547 * configuration, is passed here as mdc_mdio_access and selects 2548 * the emac_base for the CL45 read/writes operations 2549 */ 2550 static u32 bnx2x_get_emac_base(struct bnx2x *bp, 2551 u32 mdc_mdio_access, u8 port) 2552 { 2553 u32 emac_base = 0; 2554 switch (mdc_mdio_access) { 2555 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE: 2556 break; 2557 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0: 2558 if (REG_RD(bp, NIG_REG_PORT_SWAP)) 2559 emac_base = GRCBASE_EMAC1; 2560 else 2561 emac_base = GRCBASE_EMAC0; 2562 break; 2563 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1: 2564 if (REG_RD(bp, NIG_REG_PORT_SWAP)) 2565 emac_base = GRCBASE_EMAC0; 2566 else 2567 emac_base = GRCBASE_EMAC1; 2568 break; 2569 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH: 2570 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0; 2571 break; 2572 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED: 2573 emac_base = (port) ? GRCBASE_EMAC0 : GRCBASE_EMAC1; 2574 break; 2575 default: 2576 break; 2577 } 2578 return emac_base; 2579 2580 } 2581 2582 /******************************************************************/ 2583 /* CL22 access functions */ 2584 /******************************************************************/ 2585 static int bnx2x_cl22_write(struct bnx2x *bp, 2586 struct bnx2x_phy *phy, 2587 u16 reg, u16 val) 2588 { 2589 u32 tmp, mode; 2590 u8 i; 2591 int rc = 0; 2592 /* Switch to CL22 */ 2593 mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE); 2594 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, 2595 mode & ~EMAC_MDIO_MODE_CLAUSE_45); 2596 2597 /* Address */ 2598 tmp = ((phy->addr << 21) | (reg << 16) | val | 2599 EMAC_MDIO_COMM_COMMAND_WRITE_22 | 2600 EMAC_MDIO_COMM_START_BUSY); 2601 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); 2602 2603 for (i = 0; i < 50; i++) { 2604 udelay(10); 2605 2606 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); 2607 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) { 2608 udelay(5); 2609 break; 2610 } 2611 } 2612 if (tmp & EMAC_MDIO_COMM_START_BUSY) { 2613 DP(NETIF_MSG_LINK, "write phy register failed\n"); 2614 rc = -EFAULT; 2615 } 2616 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode); 2617 return rc; 2618 } 2619 2620 static int bnx2x_cl22_read(struct bnx2x *bp, 2621 struct bnx2x_phy *phy, 2622 u16 reg, u16 *ret_val) 2623 { 2624 u32 val, mode; 2625 u16 i; 2626 int rc = 0; 2627 2628 /* Switch to CL22 */ 2629 mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE); 2630 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, 2631 mode & ~EMAC_MDIO_MODE_CLAUSE_45); 2632 2633 /* Address */ 2634 val = ((phy->addr << 21) | (reg << 16) | 2635 EMAC_MDIO_COMM_COMMAND_READ_22 | 2636 EMAC_MDIO_COMM_START_BUSY); 2637 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); 2638 2639 for (i = 0; i < 50; i++) { 2640 udelay(10); 2641 2642 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); 2643 if (!(val & EMAC_MDIO_COMM_START_BUSY)) { 2644 *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA); 2645 udelay(5); 2646 break; 2647 } 2648 } 2649 if (val & EMAC_MDIO_COMM_START_BUSY) { 2650 DP(NETIF_MSG_LINK, "read phy register failed\n"); 2651 2652 *ret_val = 0; 2653 rc = -EFAULT; 2654 } 2655 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode); 2656 return rc; 2657 } 2658 2659 /******************************************************************/ 2660 /* CL45 access functions */ 2661 /******************************************************************/ 2662 static int bnx2x_cl45_read(struct bnx2x *bp, struct bnx2x_phy *phy, 2663 u8 devad, u16 reg, u16 *ret_val) 2664 { 2665 u32 val; 2666 u16 i; 2667 int rc = 0; 2668 u32 chip_id; 2669 if (phy->flags & FLAGS_MDC_MDIO_WA_G) { 2670 chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) | 2671 ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12); 2672 bnx2x_set_mdio_clk(bp, chip_id, phy->mdio_ctrl); 2673 } 2674 2675 if (phy->flags & FLAGS_MDC_MDIO_WA_B0) 2676 bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, 2677 EMAC_MDIO_STATUS_10MB); 2678 /* Address */ 2679 val = ((phy->addr << 21) | (devad << 16) | reg | 2680 EMAC_MDIO_COMM_COMMAND_ADDRESS | 2681 EMAC_MDIO_COMM_START_BUSY); 2682 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); 2683 2684 for (i = 0; i < 50; i++) { 2685 udelay(10); 2686 2687 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); 2688 if (!(val & EMAC_MDIO_COMM_START_BUSY)) { 2689 udelay(5); 2690 break; 2691 } 2692 } 2693 if (val & EMAC_MDIO_COMM_START_BUSY) { 2694 DP(NETIF_MSG_LINK, "read phy register failed\n"); 2695 netdev_err(bp->dev, "MDC/MDIO access timeout\n"); 2696 *ret_val = 0; 2697 rc = -EFAULT; 2698 } else { 2699 /* Data */ 2700 val = ((phy->addr << 21) | (devad << 16) | 2701 EMAC_MDIO_COMM_COMMAND_READ_45 | 2702 EMAC_MDIO_COMM_START_BUSY); 2703 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); 2704 2705 for (i = 0; i < 50; i++) { 2706 udelay(10); 2707 2708 val = REG_RD(bp, phy->mdio_ctrl + 2709 EMAC_REG_EMAC_MDIO_COMM); 2710 if (!(val & EMAC_MDIO_COMM_START_BUSY)) { 2711 *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA); 2712 break; 2713 } 2714 } 2715 if (val & EMAC_MDIO_COMM_START_BUSY) { 2716 DP(NETIF_MSG_LINK, "read phy register failed\n"); 2717 netdev_err(bp->dev, "MDC/MDIO access timeout\n"); 2718 *ret_val = 0; 2719 rc = -EFAULT; 2720 } 2721 } 2722 /* Work around for E3 A0 */ 2723 if (phy->flags & FLAGS_MDC_MDIO_WA) { 2724 phy->flags ^= FLAGS_DUMMY_READ; 2725 if (phy->flags & FLAGS_DUMMY_READ) { 2726 u16 temp_val; 2727 bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val); 2728 } 2729 } 2730 2731 if (phy->flags & FLAGS_MDC_MDIO_WA_B0) 2732 bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, 2733 EMAC_MDIO_STATUS_10MB); 2734 return rc; 2735 } 2736 2737 static int bnx2x_cl45_write(struct bnx2x *bp, struct bnx2x_phy *phy, 2738 u8 devad, u16 reg, u16 val) 2739 { 2740 u32 tmp; 2741 u8 i; 2742 int rc = 0; 2743 u32 chip_id; 2744 if (phy->flags & FLAGS_MDC_MDIO_WA_G) { 2745 chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) | 2746 ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12); 2747 bnx2x_set_mdio_clk(bp, chip_id, phy->mdio_ctrl); 2748 } 2749 2750 if (phy->flags & FLAGS_MDC_MDIO_WA_B0) 2751 bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, 2752 EMAC_MDIO_STATUS_10MB); 2753 2754 /* Address */ 2755 tmp = ((phy->addr << 21) | (devad << 16) | reg | 2756 EMAC_MDIO_COMM_COMMAND_ADDRESS | 2757 EMAC_MDIO_COMM_START_BUSY); 2758 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); 2759 2760 for (i = 0; i < 50; i++) { 2761 udelay(10); 2762 2763 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); 2764 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) { 2765 udelay(5); 2766 break; 2767 } 2768 } 2769 if (tmp & EMAC_MDIO_COMM_START_BUSY) { 2770 DP(NETIF_MSG_LINK, "write phy register failed\n"); 2771 netdev_err(bp->dev, "MDC/MDIO access timeout\n"); 2772 rc = -EFAULT; 2773 } else { 2774 /* Data */ 2775 tmp = ((phy->addr << 21) | (devad << 16) | val | 2776 EMAC_MDIO_COMM_COMMAND_WRITE_45 | 2777 EMAC_MDIO_COMM_START_BUSY); 2778 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); 2779 2780 for (i = 0; i < 50; i++) { 2781 udelay(10); 2782 2783 tmp = REG_RD(bp, phy->mdio_ctrl + 2784 EMAC_REG_EMAC_MDIO_COMM); 2785 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) { 2786 udelay(5); 2787 break; 2788 } 2789 } 2790 if (tmp & EMAC_MDIO_COMM_START_BUSY) { 2791 DP(NETIF_MSG_LINK, "write phy register failed\n"); 2792 netdev_err(bp->dev, "MDC/MDIO access timeout\n"); 2793 rc = -EFAULT; 2794 } 2795 } 2796 /* Work around for E3 A0 */ 2797 if (phy->flags & FLAGS_MDC_MDIO_WA) { 2798 phy->flags ^= FLAGS_DUMMY_READ; 2799 if (phy->flags & FLAGS_DUMMY_READ) { 2800 u16 temp_val; 2801 bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val); 2802 } 2803 } 2804 if (phy->flags & FLAGS_MDC_MDIO_WA_B0) 2805 bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, 2806 EMAC_MDIO_STATUS_10MB); 2807 return rc; 2808 } 2809 2810 /******************************************************************/ 2811 /* EEE section */ 2812 /******************************************************************/ 2813 static u8 bnx2x_eee_has_cap(struct link_params *params) 2814 { 2815 struct bnx2x *bp = params->bp; 2816 2817 if (REG_RD(bp, params->shmem2_base) <= 2818 offsetof(struct shmem2_region, eee_status[params->port])) 2819 return 0; 2820 2821 return 1; 2822 } 2823 2824 static int bnx2x_eee_nvram_to_time(u32 nvram_mode, u32 *idle_timer) 2825 { 2826 switch (nvram_mode) { 2827 case PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED: 2828 *idle_timer = EEE_MODE_NVRAM_BALANCED_TIME; 2829 break; 2830 case PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE: 2831 *idle_timer = EEE_MODE_NVRAM_AGGRESSIVE_TIME; 2832 break; 2833 case PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY: 2834 *idle_timer = EEE_MODE_NVRAM_LATENCY_TIME; 2835 break; 2836 default: 2837 *idle_timer = 0; 2838 break; 2839 } 2840 2841 return 0; 2842 } 2843 2844 static int bnx2x_eee_time_to_nvram(u32 idle_timer, u32 *nvram_mode) 2845 { 2846 switch (idle_timer) { 2847 case EEE_MODE_NVRAM_BALANCED_TIME: 2848 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED; 2849 break; 2850 case EEE_MODE_NVRAM_AGGRESSIVE_TIME: 2851 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE; 2852 break; 2853 case EEE_MODE_NVRAM_LATENCY_TIME: 2854 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY; 2855 break; 2856 default: 2857 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED; 2858 break; 2859 } 2860 2861 return 0; 2862 } 2863 2864 static u32 bnx2x_eee_calc_timer(struct link_params *params) 2865 { 2866 u32 eee_mode, eee_idle; 2867 struct bnx2x *bp = params->bp; 2868 2869 if (params->eee_mode & EEE_MODE_OVERRIDE_NVRAM) { 2870 if (params->eee_mode & EEE_MODE_OUTPUT_TIME) { 2871 /* time value in eee_mode --> used directly*/ 2872 eee_idle = params->eee_mode & EEE_MODE_TIMER_MASK; 2873 } else { 2874 /* hsi value in eee_mode --> time */ 2875 if (bnx2x_eee_nvram_to_time(params->eee_mode & 2876 EEE_MODE_NVRAM_MASK, 2877 &eee_idle)) 2878 return 0; 2879 } 2880 } else { 2881 /* hsi values in nvram --> time*/ 2882 eee_mode = ((REG_RD(bp, params->shmem_base + 2883 offsetof(struct shmem_region, dev_info. 2884 port_feature_config[params->port]. 2885 eee_power_mode)) & 2886 PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >> 2887 PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT); 2888 2889 if (bnx2x_eee_nvram_to_time(eee_mode, &eee_idle)) 2890 return 0; 2891 } 2892 2893 return eee_idle; 2894 } 2895 2896 static int bnx2x_eee_set_timers(struct link_params *params, 2897 struct link_vars *vars) 2898 { 2899 u32 eee_idle = 0, eee_mode; 2900 struct bnx2x *bp = params->bp; 2901 2902 eee_idle = bnx2x_eee_calc_timer(params); 2903 2904 if (eee_idle) { 2905 REG_WR(bp, MISC_REG_CPMU_LP_IDLE_THR_P0 + (params->port << 2), 2906 eee_idle); 2907 } else if ((params->eee_mode & EEE_MODE_ENABLE_LPI) && 2908 (params->eee_mode & EEE_MODE_OVERRIDE_NVRAM) && 2909 (params->eee_mode & EEE_MODE_OUTPUT_TIME)) { 2910 DP(NETIF_MSG_LINK, "Error: Tx LPI is enabled with timer 0\n"); 2911 return -EINVAL; 2912 } 2913 2914 vars->eee_status &= ~(SHMEM_EEE_TIMER_MASK | SHMEM_EEE_TIME_OUTPUT_BIT); 2915 if (params->eee_mode & EEE_MODE_OUTPUT_TIME) { 2916 /* eee_idle in 1u --> eee_status in 16u */ 2917 eee_idle >>= 4; 2918 vars->eee_status |= (eee_idle & SHMEM_EEE_TIMER_MASK) | 2919 SHMEM_EEE_TIME_OUTPUT_BIT; 2920 } else { 2921 if (bnx2x_eee_time_to_nvram(eee_idle, &eee_mode)) 2922 return -EINVAL; 2923 vars->eee_status |= eee_mode; 2924 } 2925 2926 return 0; 2927 } 2928 2929 static int bnx2x_eee_initial_config(struct link_params *params, 2930 struct link_vars *vars, u8 mode) 2931 { 2932 vars->eee_status |= ((u32) mode) << SHMEM_EEE_SUPPORTED_SHIFT; 2933 2934 /* Propogate params' bits --> vars (for migration exposure) */ 2935 if (params->eee_mode & EEE_MODE_ENABLE_LPI) 2936 vars->eee_status |= SHMEM_EEE_LPI_REQUESTED_BIT; 2937 else 2938 vars->eee_status &= ~SHMEM_EEE_LPI_REQUESTED_BIT; 2939 2940 if (params->eee_mode & EEE_MODE_ADV_LPI) 2941 vars->eee_status |= SHMEM_EEE_REQUESTED_BIT; 2942 else 2943 vars->eee_status &= ~SHMEM_EEE_REQUESTED_BIT; 2944 2945 return bnx2x_eee_set_timers(params, vars); 2946 } 2947 2948 static int bnx2x_eee_disable(struct bnx2x_phy *phy, 2949 struct link_params *params, 2950 struct link_vars *vars) 2951 { 2952 struct bnx2x *bp = params->bp; 2953 2954 /* Make Certain LPI is disabled */ 2955 REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2), 0); 2956 2957 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, 0x0); 2958 2959 vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK; 2960 2961 return 0; 2962 } 2963 2964 static int bnx2x_eee_advertise(struct bnx2x_phy *phy, 2965 struct link_params *params, 2966 struct link_vars *vars, u8 modes) 2967 { 2968 struct bnx2x *bp = params->bp; 2969 u16 val = 0; 2970 2971 /* Mask events preventing LPI generation */ 2972 REG_WR(bp, MISC_REG_CPMU_LP_MASK_EXT_P0 + (params->port << 2), 0xfc20); 2973 2974 if (modes & SHMEM_EEE_10G_ADV) { 2975 DP(NETIF_MSG_LINK, "Advertise 10GBase-T EEE\n"); 2976 val |= 0x8; 2977 } 2978 if (modes & SHMEM_EEE_1G_ADV) { 2979 DP(NETIF_MSG_LINK, "Advertise 1GBase-T EEE\n"); 2980 val |= 0x4; 2981 } 2982 2983 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, val); 2984 2985 vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK; 2986 vars->eee_status |= (modes << SHMEM_EEE_ADV_STATUS_SHIFT); 2987 2988 return 0; 2989 } 2990 2991 static void bnx2x_update_mng_eee(struct link_params *params, u32 eee_status) 2992 { 2993 struct bnx2x *bp = params->bp; 2994 2995 if (bnx2x_eee_has_cap(params)) 2996 REG_WR(bp, params->shmem2_base + 2997 offsetof(struct shmem2_region, 2998 eee_status[params->port]), eee_status); 2999 } 3000 3001 static void bnx2x_eee_an_resolve(struct bnx2x_phy *phy, 3002 struct link_params *params, 3003 struct link_vars *vars) 3004 { 3005 struct bnx2x *bp = params->bp; 3006 u16 adv = 0, lp = 0; 3007 u32 lp_adv = 0; 3008 u8 neg = 0; 3009 3010 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, &adv); 3011 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_LP_EEE_ADV, &lp); 3012 3013 if (lp & 0x2) { 3014 lp_adv |= SHMEM_EEE_100M_ADV; 3015 if (adv & 0x2) { 3016 if (vars->line_speed == SPEED_100) 3017 neg = 1; 3018 DP(NETIF_MSG_LINK, "EEE negotiated - 100M\n"); 3019 } 3020 } 3021 if (lp & 0x14) { 3022 lp_adv |= SHMEM_EEE_1G_ADV; 3023 if (adv & 0x14) { 3024 if (vars->line_speed == SPEED_1000) 3025 neg = 1; 3026 DP(NETIF_MSG_LINK, "EEE negotiated - 1G\n"); 3027 } 3028 } 3029 if (lp & 0x68) { 3030 lp_adv |= SHMEM_EEE_10G_ADV; 3031 if (adv & 0x68) { 3032 if (vars->line_speed == SPEED_10000) 3033 neg = 1; 3034 DP(NETIF_MSG_LINK, "EEE negotiated - 10G\n"); 3035 } 3036 } 3037 3038 vars->eee_status &= ~SHMEM_EEE_LP_ADV_STATUS_MASK; 3039 vars->eee_status |= (lp_adv << SHMEM_EEE_LP_ADV_STATUS_SHIFT); 3040 3041 if (neg) { 3042 DP(NETIF_MSG_LINK, "EEE is active\n"); 3043 vars->eee_status |= SHMEM_EEE_ACTIVE_BIT; 3044 } 3045 3046 } 3047 3048 /******************************************************************/ 3049 /* BSC access functions from E3 */ 3050 /******************************************************************/ 3051 static void bnx2x_bsc_module_sel(struct link_params *params) 3052 { 3053 int idx; 3054 u32 board_cfg, sfp_ctrl; 3055 u32 i2c_pins[I2C_SWITCH_WIDTH], i2c_val[I2C_SWITCH_WIDTH]; 3056 struct bnx2x *bp = params->bp; 3057 u8 port = params->port; 3058 /* Read I2C output PINs */ 3059 board_cfg = REG_RD(bp, params->shmem_base + 3060 offsetof(struct shmem_region, 3061 dev_info.shared_hw_config.board)); 3062 i2c_pins[I2C_BSC0] = board_cfg & SHARED_HW_CFG_E3_I2C_MUX0_MASK; 3063 i2c_pins[I2C_BSC1] = (board_cfg & SHARED_HW_CFG_E3_I2C_MUX1_MASK) >> 3064 SHARED_HW_CFG_E3_I2C_MUX1_SHIFT; 3065 3066 /* Read I2C output value */ 3067 sfp_ctrl = REG_RD(bp, params->shmem_base + 3068 offsetof(struct shmem_region, 3069 dev_info.port_hw_config[port].e3_cmn_pin_cfg)); 3070 i2c_val[I2C_BSC0] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX0_MASK) > 0; 3071 i2c_val[I2C_BSC1] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX1_MASK) > 0; 3072 DP(NETIF_MSG_LINK, "Setting BSC switch\n"); 3073 for (idx = 0; idx < I2C_SWITCH_WIDTH; idx++) 3074 bnx2x_set_cfg_pin(bp, i2c_pins[idx], i2c_val[idx]); 3075 } 3076 3077 static int bnx2x_bsc_read(struct link_params *params, 3078 struct bnx2x *bp, 3079 u8 sl_devid, 3080 u16 sl_addr, 3081 u8 lc_addr, 3082 u8 xfer_cnt, 3083 u32 *data_array) 3084 { 3085 u32 val, i; 3086 int rc = 0; 3087 3088 if (xfer_cnt > 16) { 3089 DP(NETIF_MSG_LINK, "invalid xfer_cnt %d. Max is 16 bytes\n", 3090 xfer_cnt); 3091 return -EINVAL; 3092 } 3093 bnx2x_bsc_module_sel(params); 3094 3095 xfer_cnt = 16 - lc_addr; 3096 3097 /* Enable the engine */ 3098 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND); 3099 val |= MCPR_IMC_COMMAND_ENABLE; 3100 REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val); 3101 3102 /* Program slave device ID */ 3103 val = (sl_devid << 16) | sl_addr; 3104 REG_WR(bp, MCP_REG_MCPR_IMC_SLAVE_CONTROL, val); 3105 3106 /* Start xfer with 0 byte to update the address pointer ???*/ 3107 val = (MCPR_IMC_COMMAND_ENABLE) | 3108 (MCPR_IMC_COMMAND_WRITE_OP << 3109 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) | 3110 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) | (0); 3111 REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val); 3112 3113 /* Poll for completion */ 3114 i = 0; 3115 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND); 3116 while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) { 3117 udelay(10); 3118 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND); 3119 if (i++ > 1000) { 3120 DP(NETIF_MSG_LINK, "wr 0 byte timed out after %d try\n", 3121 i); 3122 rc = -EFAULT; 3123 break; 3124 } 3125 } 3126 if (rc == -EFAULT) 3127 return rc; 3128 3129 /* Start xfer with read op */ 3130 val = (MCPR_IMC_COMMAND_ENABLE) | 3131 (MCPR_IMC_COMMAND_READ_OP << 3132 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) | 3133 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) | 3134 (xfer_cnt); 3135 REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val); 3136 3137 /* Poll for completion */ 3138 i = 0; 3139 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND); 3140 while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) { 3141 udelay(10); 3142 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND); 3143 if (i++ > 1000) { 3144 DP(NETIF_MSG_LINK, "rd op timed out after %d try\n", i); 3145 rc = -EFAULT; 3146 break; 3147 } 3148 } 3149 if (rc == -EFAULT) 3150 return rc; 3151 3152 for (i = (lc_addr >> 2); i < 4; i++) { 3153 data_array[i] = REG_RD(bp, (MCP_REG_MCPR_IMC_DATAREG0 + i*4)); 3154 #ifdef __BIG_ENDIAN 3155 data_array[i] = ((data_array[i] & 0x000000ff) << 24) | 3156 ((data_array[i] & 0x0000ff00) << 8) | 3157 ((data_array[i] & 0x00ff0000) >> 8) | 3158 ((data_array[i] & 0xff000000) >> 24); 3159 #endif 3160 } 3161 return rc; 3162 } 3163 3164 static void bnx2x_cl45_read_or_write(struct bnx2x *bp, struct bnx2x_phy *phy, 3165 u8 devad, u16 reg, u16 or_val) 3166 { 3167 u16 val; 3168 bnx2x_cl45_read(bp, phy, devad, reg, &val); 3169 bnx2x_cl45_write(bp, phy, devad, reg, val | or_val); 3170 } 3171 3172 static void bnx2x_cl45_read_and_write(struct bnx2x *bp, 3173 struct bnx2x_phy *phy, 3174 u8 devad, u16 reg, u16 and_val) 3175 { 3176 u16 val; 3177 bnx2x_cl45_read(bp, phy, devad, reg, &val); 3178 bnx2x_cl45_write(bp, phy, devad, reg, val & and_val); 3179 } 3180 3181 int bnx2x_phy_read(struct link_params *params, u8 phy_addr, 3182 u8 devad, u16 reg, u16 *ret_val) 3183 { 3184 u8 phy_index; 3185 /* Probe for the phy according to the given phy_addr, and execute 3186 * the read request on it 3187 */ 3188 for (phy_index = 0; phy_index < params->num_phys; phy_index++) { 3189 if (params->phy[phy_index].addr == phy_addr) { 3190 return bnx2x_cl45_read(params->bp, 3191 ¶ms->phy[phy_index], devad, 3192 reg, ret_val); 3193 } 3194 } 3195 return -EINVAL; 3196 } 3197 3198 int bnx2x_phy_write(struct link_params *params, u8 phy_addr, 3199 u8 devad, u16 reg, u16 val) 3200 { 3201 u8 phy_index; 3202 /* Probe for the phy according to the given phy_addr, and execute 3203 * the write request on it 3204 */ 3205 for (phy_index = 0; phy_index < params->num_phys; phy_index++) { 3206 if (params->phy[phy_index].addr == phy_addr) { 3207 return bnx2x_cl45_write(params->bp, 3208 ¶ms->phy[phy_index], devad, 3209 reg, val); 3210 } 3211 } 3212 return -EINVAL; 3213 } 3214 static u8 bnx2x_get_warpcore_lane(struct bnx2x_phy *phy, 3215 struct link_params *params) 3216 { 3217 u8 lane = 0; 3218 struct bnx2x *bp = params->bp; 3219 u32 path_swap, path_swap_ovr; 3220 u8 path, port; 3221 3222 path = BP_PATH(bp); 3223 port = params->port; 3224 3225 if (bnx2x_is_4_port_mode(bp)) { 3226 u32 port_swap, port_swap_ovr; 3227 3228 /* Figure out path swap value */ 3229 path_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP_OVWR); 3230 if (path_swap_ovr & 0x1) 3231 path_swap = (path_swap_ovr & 0x2); 3232 else 3233 path_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP); 3234 3235 if (path_swap) 3236 path = path ^ 1; 3237 3238 /* Figure out port swap value */ 3239 port_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP_OVWR); 3240 if (port_swap_ovr & 0x1) 3241 port_swap = (port_swap_ovr & 0x2); 3242 else 3243 port_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP); 3244 3245 if (port_swap) 3246 port = port ^ 1; 3247 3248 lane = (port<<1) + path; 3249 } else { /* Two port mode - no port swap */ 3250 3251 /* Figure out path swap value */ 3252 path_swap_ovr = 3253 REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP_OVWR); 3254 if (path_swap_ovr & 0x1) { 3255 path_swap = (path_swap_ovr & 0x2); 3256 } else { 3257 path_swap = 3258 REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP); 3259 } 3260 if (path_swap) 3261 path = path ^ 1; 3262 3263 lane = path << 1 ; 3264 } 3265 return lane; 3266 } 3267 3268 static void bnx2x_set_aer_mmd(struct link_params *params, 3269 struct bnx2x_phy *phy) 3270 { 3271 u32 ser_lane; 3272 u16 offset, aer_val; 3273 struct bnx2x *bp = params->bp; 3274 ser_lane = ((params->lane_config & 3275 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >> 3276 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT); 3277 3278 offset = (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ? 3279 (phy->addr + ser_lane) : 0; 3280 3281 if (USES_WARPCORE(bp)) { 3282 aer_val = bnx2x_get_warpcore_lane(phy, params); 3283 /* In Dual-lane mode, two lanes are joined together, 3284 * so in order to configure them, the AER broadcast method is 3285 * used here. 3286 * 0x200 is the broadcast address for lanes 0,1 3287 * 0x201 is the broadcast address for lanes 2,3 3288 */ 3289 if (phy->flags & FLAGS_WC_DUAL_MODE) 3290 aer_val = (aer_val >> 1) | 0x200; 3291 } else if (CHIP_IS_E2(bp)) 3292 aer_val = 0x3800 + offset - 1; 3293 else 3294 aer_val = 0x3800 + offset; 3295 3296 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, 3297 MDIO_AER_BLOCK_AER_REG, aer_val); 3298 3299 } 3300 3301 /******************************************************************/ 3302 /* Internal phy section */ 3303 /******************************************************************/ 3304 3305 static void bnx2x_set_serdes_access(struct bnx2x *bp, u8 port) 3306 { 3307 u32 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0; 3308 3309 /* Set Clause 22 */ 3310 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 1); 3311 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000); 3312 udelay(500); 3313 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f); 3314 udelay(500); 3315 /* Set Clause 45 */ 3316 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 0); 3317 } 3318 3319 static void bnx2x_serdes_deassert(struct bnx2x *bp, u8 port) 3320 { 3321 u32 val; 3322 3323 DP(NETIF_MSG_LINK, "bnx2x_serdes_deassert\n"); 3324 3325 val = SERDES_RESET_BITS << (port*16); 3326 3327 /* Reset and unreset the SerDes/XGXS */ 3328 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val); 3329 udelay(500); 3330 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val); 3331 3332 bnx2x_set_serdes_access(bp, port); 3333 3334 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_DEVAD + port*0x10, 3335 DEFAULT_PHY_DEV_ADDR); 3336 } 3337 3338 static void bnx2x_xgxs_specific_func(struct bnx2x_phy *phy, 3339 struct link_params *params, 3340 u32 action) 3341 { 3342 struct bnx2x *bp = params->bp; 3343 switch (action) { 3344 case PHY_INIT: 3345 /* Set correct devad */ 3346 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_ST + params->port*0x18, 0); 3347 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + params->port*0x18, 3348 phy->def_md_devad); 3349 break; 3350 } 3351 } 3352 3353 static void bnx2x_xgxs_deassert(struct link_params *params) 3354 { 3355 struct bnx2x *bp = params->bp; 3356 u8 port; 3357 u32 val; 3358 DP(NETIF_MSG_LINK, "bnx2x_xgxs_deassert\n"); 3359 port = params->port; 3360 3361 val = XGXS_RESET_BITS << (port*16); 3362 3363 /* Reset and unreset the SerDes/XGXS */ 3364 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val); 3365 udelay(500); 3366 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val); 3367 bnx2x_xgxs_specific_func(¶ms->phy[INT_PHY], params, 3368 PHY_INIT); 3369 } 3370 3371 static void bnx2x_calc_ieee_aneg_adv(struct bnx2x_phy *phy, 3372 struct link_params *params, u16 *ieee_fc) 3373 { 3374 struct bnx2x *bp = params->bp; 3375 *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX; 3376 /* Resolve pause mode and advertisement Please refer to Table 3377 * 28B-3 of the 802.3ab-1999 spec 3378 */ 3379 3380 switch (phy->req_flow_ctrl) { 3381 case BNX2X_FLOW_CTRL_AUTO: 3382 switch (params->req_fc_auto_adv) { 3383 case BNX2X_FLOW_CTRL_BOTH: 3384 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; 3385 break; 3386 case BNX2X_FLOW_CTRL_RX: 3387 case BNX2X_FLOW_CTRL_TX: 3388 *ieee_fc |= 3389 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC; 3390 break; 3391 default: 3392 break; 3393 } 3394 break; 3395 case BNX2X_FLOW_CTRL_TX: 3396 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC; 3397 break; 3398 3399 case BNX2X_FLOW_CTRL_RX: 3400 case BNX2X_FLOW_CTRL_BOTH: 3401 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; 3402 break; 3403 3404 case BNX2X_FLOW_CTRL_NONE: 3405 default: 3406 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE; 3407 break; 3408 } 3409 DP(NETIF_MSG_LINK, "ieee_fc = 0x%x\n", *ieee_fc); 3410 } 3411 3412 static void set_phy_vars(struct link_params *params, 3413 struct link_vars *vars) 3414 { 3415 struct bnx2x *bp = params->bp; 3416 u8 actual_phy_idx, phy_index, link_cfg_idx; 3417 u8 phy_config_swapped = params->multi_phy_config & 3418 PORT_HW_CFG_PHY_SWAPPED_ENABLED; 3419 for (phy_index = INT_PHY; phy_index < params->num_phys; 3420 phy_index++) { 3421 link_cfg_idx = LINK_CONFIG_IDX(phy_index); 3422 actual_phy_idx = phy_index; 3423 if (phy_config_swapped) { 3424 if (phy_index == EXT_PHY1) 3425 actual_phy_idx = EXT_PHY2; 3426 else if (phy_index == EXT_PHY2) 3427 actual_phy_idx = EXT_PHY1; 3428 } 3429 params->phy[actual_phy_idx].req_flow_ctrl = 3430 params->req_flow_ctrl[link_cfg_idx]; 3431 3432 params->phy[actual_phy_idx].req_line_speed = 3433 params->req_line_speed[link_cfg_idx]; 3434 3435 params->phy[actual_phy_idx].speed_cap_mask = 3436 params->speed_cap_mask[link_cfg_idx]; 3437 3438 params->phy[actual_phy_idx].req_duplex = 3439 params->req_duplex[link_cfg_idx]; 3440 3441 if (params->req_line_speed[link_cfg_idx] == 3442 SPEED_AUTO_NEG) 3443 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED; 3444 3445 DP(NETIF_MSG_LINK, "req_flow_ctrl %x, req_line_speed %x," 3446 " speed_cap_mask %x\n", 3447 params->phy[actual_phy_idx].req_flow_ctrl, 3448 params->phy[actual_phy_idx].req_line_speed, 3449 params->phy[actual_phy_idx].speed_cap_mask); 3450 } 3451 } 3452 3453 static void bnx2x_ext_phy_set_pause(struct link_params *params, 3454 struct bnx2x_phy *phy, 3455 struct link_vars *vars) 3456 { 3457 u16 val; 3458 struct bnx2x *bp = params->bp; 3459 /* Read modify write pause advertizing */ 3460 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &val); 3461 3462 val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH; 3463 3464 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */ 3465 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); 3466 if ((vars->ieee_fc & 3467 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) == 3468 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) { 3469 val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC; 3470 } 3471 if ((vars->ieee_fc & 3472 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) == 3473 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) { 3474 val |= MDIO_AN_REG_ADV_PAUSE_PAUSE; 3475 } 3476 DP(NETIF_MSG_LINK, "Ext phy AN advertize 0x%x\n", val); 3477 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val); 3478 } 3479 3480 static void bnx2x_pause_resolve(struct link_vars *vars, u32 pause_result) 3481 { /* LD LP */ 3482 switch (pause_result) { /* ASYM P ASYM P */ 3483 case 0xb: /* 1 0 1 1 */ 3484 vars->flow_ctrl = BNX2X_FLOW_CTRL_TX; 3485 break; 3486 3487 case 0xe: /* 1 1 1 0 */ 3488 vars->flow_ctrl = BNX2X_FLOW_CTRL_RX; 3489 break; 3490 3491 case 0x5: /* 0 1 0 1 */ 3492 case 0x7: /* 0 1 1 1 */ 3493 case 0xd: /* 1 1 0 1 */ 3494 case 0xf: /* 1 1 1 1 */ 3495 vars->flow_ctrl = BNX2X_FLOW_CTRL_BOTH; 3496 break; 3497 3498 default: 3499 break; 3500 } 3501 if (pause_result & (1<<0)) 3502 vars->link_status |= LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE; 3503 if (pause_result & (1<<1)) 3504 vars->link_status |= LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE; 3505 3506 } 3507 3508 static void bnx2x_ext_phy_update_adv_fc(struct bnx2x_phy *phy, 3509 struct link_params *params, 3510 struct link_vars *vars) 3511 { 3512 u16 ld_pause; /* local */ 3513 u16 lp_pause; /* link partner */ 3514 u16 pause_result; 3515 struct bnx2x *bp = params->bp; 3516 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) { 3517 bnx2x_cl22_read(bp, phy, 0x4, &ld_pause); 3518 bnx2x_cl22_read(bp, phy, 0x5, &lp_pause); 3519 } else if (CHIP_IS_E3(bp) && 3520 SINGLE_MEDIA_DIRECT(params)) { 3521 u8 lane = bnx2x_get_warpcore_lane(phy, params); 3522 u16 gp_status, gp_mask; 3523 bnx2x_cl45_read(bp, phy, 3524 MDIO_AN_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_4, 3525 &gp_status); 3526 gp_mask = (MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL | 3527 MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP) << 3528 lane; 3529 if ((gp_status & gp_mask) == gp_mask) { 3530 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, 3531 MDIO_AN_REG_ADV_PAUSE, &ld_pause); 3532 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, 3533 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause); 3534 } else { 3535 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, 3536 MDIO_AN_REG_CL37_FC_LD, &ld_pause); 3537 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, 3538 MDIO_AN_REG_CL37_FC_LP, &lp_pause); 3539 ld_pause = ((ld_pause & 3540 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) 3541 << 3); 3542 lp_pause = ((lp_pause & 3543 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) 3544 << 3); 3545 } 3546 } else { 3547 bnx2x_cl45_read(bp, phy, 3548 MDIO_AN_DEVAD, 3549 MDIO_AN_REG_ADV_PAUSE, &ld_pause); 3550 bnx2x_cl45_read(bp, phy, 3551 MDIO_AN_DEVAD, 3552 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause); 3553 } 3554 pause_result = (ld_pause & 3555 MDIO_AN_REG_ADV_PAUSE_MASK) >> 8; 3556 pause_result |= (lp_pause & 3557 MDIO_AN_REG_ADV_PAUSE_MASK) >> 10; 3558 DP(NETIF_MSG_LINK, "Ext PHY pause result 0x%x\n", pause_result); 3559 bnx2x_pause_resolve(vars, pause_result); 3560 3561 } 3562 3563 static u8 bnx2x_ext_phy_resolve_fc(struct bnx2x_phy *phy, 3564 struct link_params *params, 3565 struct link_vars *vars) 3566 { 3567 u8 ret = 0; 3568 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; 3569 if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO) { 3570 /* Update the advertised flow-controled of LD/LP in AN */ 3571 if (phy->req_line_speed == SPEED_AUTO_NEG) 3572 bnx2x_ext_phy_update_adv_fc(phy, params, vars); 3573 /* But set the flow-control result as the requested one */ 3574 vars->flow_ctrl = phy->req_flow_ctrl; 3575 } else if (phy->req_line_speed != SPEED_AUTO_NEG) 3576 vars->flow_ctrl = params->req_fc_auto_adv; 3577 else if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) { 3578 ret = 1; 3579 bnx2x_ext_phy_update_adv_fc(phy, params, vars); 3580 } 3581 return ret; 3582 } 3583 /******************************************************************/ 3584 /* Warpcore section */ 3585 /******************************************************************/ 3586 /* The init_internal_warpcore should mirror the xgxs, 3587 * i.e. reset the lane (if needed), set aer for the 3588 * init configuration, and set/clear SGMII flag. Internal 3589 * phy init is done purely in phy_init stage. 3590 */ 3591 #define WC_TX_DRIVER(post2, idriver, ipre) \ 3592 ((post2 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) | \ 3593 (idriver << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) | \ 3594 (ipre << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET)) 3595 3596 #define WC_TX_FIR(post, main, pre) \ 3597 ((post << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) | \ 3598 (main << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) | \ 3599 (pre << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET)) 3600 3601 static void bnx2x_warpcore_enable_AN_KR2(struct bnx2x_phy *phy, 3602 struct link_params *params, 3603 struct link_vars *vars) 3604 { 3605 struct bnx2x *bp = params->bp; 3606 u16 i; 3607 static struct bnx2x_reg_set reg_set[] = { 3608 /* Step 1 - Program the TX/RX alignment markers */ 3609 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL5, 0xa157}, 3610 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL7, 0xcbe2}, 3611 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL6, 0x7537}, 3612 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL9, 0xa157}, 3613 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL11, 0xcbe2}, 3614 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL10, 0x7537}, 3615 /* Step 2 - Configure the NP registers */ 3616 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_USERB0_CTRL, 0x000a}, 3617 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL1, 0x6400}, 3618 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL3, 0x0620}, 3619 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CODE_FIELD, 0x0157}, 3620 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI1, 0x6464}, 3621 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI2, 0x3150}, 3622 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI3, 0x3150}, 3623 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0157}, 3624 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0620} 3625 }; 3626 DP(NETIF_MSG_LINK, "Enabling 20G-KR2\n"); 3627 3628 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 3629 MDIO_WC_REG_CL49_USERB0_CTRL, (3<<6)); 3630 3631 for (i = 0; i < ARRAY_SIZE(reg_set); i++) 3632 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg, 3633 reg_set[i].val); 3634 3635 /* Start KR2 work-around timer which handles BCM8073 link-parner */ 3636 vars->link_attr_sync |= LINK_ATTR_SYNC_KR2_ENABLE; 3637 bnx2x_update_link_attr(params, vars->link_attr_sync); 3638 } 3639 3640 static void bnx2x_disable_kr2(struct link_params *params, 3641 struct link_vars *vars, 3642 struct bnx2x_phy *phy) 3643 { 3644 struct bnx2x *bp = params->bp; 3645 int i; 3646 static struct bnx2x_reg_set reg_set[] = { 3647 /* Step 1 - Program the TX/RX alignment markers */ 3648 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL5, 0x7690}, 3649 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL7, 0xe647}, 3650 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL6, 0xc4f0}, 3651 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL9, 0x7690}, 3652 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL11, 0xe647}, 3653 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL10, 0xc4f0}, 3654 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_USERB0_CTRL, 0x000c}, 3655 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL1, 0x6000}, 3656 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL3, 0x0000}, 3657 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CODE_FIELD, 0x0002}, 3658 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI1, 0x0000}, 3659 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI2, 0x0af7}, 3660 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI3, 0x0af7}, 3661 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0002}, 3662 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0000} 3663 }; 3664 DP(NETIF_MSG_LINK, "Disabling 20G-KR2\n"); 3665 3666 for (i = 0; i < ARRAY_SIZE(reg_set); i++) 3667 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg, 3668 reg_set[i].val); 3669 vars->link_attr_sync &= ~LINK_ATTR_SYNC_KR2_ENABLE; 3670 bnx2x_update_link_attr(params, vars->link_attr_sync); 3671 3672 vars->check_kr2_recovery_cnt = CHECK_KR2_RECOVERY_CNT; 3673 } 3674 3675 static void bnx2x_warpcore_set_lpi_passthrough(struct bnx2x_phy *phy, 3676 struct link_params *params) 3677 { 3678 struct bnx2x *bp = params->bp; 3679 3680 DP(NETIF_MSG_LINK, "Configure WC for LPI pass through\n"); 3681 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3682 MDIO_WC_REG_EEE_COMBO_CONTROL0, 0x7c); 3683 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 3684 MDIO_WC_REG_DIGITAL4_MISC5, 0xc000); 3685 } 3686 3687 static void bnx2x_warpcore_restart_AN_KR(struct bnx2x_phy *phy, 3688 struct link_params *params) 3689 { 3690 /* Restart autoneg on the leading lane only */ 3691 struct bnx2x *bp = params->bp; 3692 u16 lane = bnx2x_get_warpcore_lane(phy, params); 3693 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, 3694 MDIO_AER_BLOCK_AER_REG, lane); 3695 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, 3696 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200); 3697 3698 /* Restore AER */ 3699 bnx2x_set_aer_mmd(params, phy); 3700 } 3701 3702 static void bnx2x_warpcore_enable_AN_KR(struct bnx2x_phy *phy, 3703 struct link_params *params, 3704 struct link_vars *vars) { 3705 u16 lane, i, cl72_ctrl, an_adv = 0, val; 3706 u32 wc_lane_config; 3707 struct bnx2x *bp = params->bp; 3708 static struct bnx2x_reg_set reg_set[] = { 3709 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7}, 3710 {MDIO_PMA_DEVAD, MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0x0}, 3711 {MDIO_WC_DEVAD, MDIO_WC_REG_RX66_CONTROL, 0x7415}, 3712 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x6190}, 3713 /* Disable Autoneg: re-enable it after adv is done. */ 3714 {MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0}, 3715 {MDIO_PMA_DEVAD, MDIO_WC_REG_PMD_KR_CONTROL, 0x2}, 3716 {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP, 0}, 3717 }; 3718 DP(NETIF_MSG_LINK, "Enable Auto Negotiation for KR\n"); 3719 /* Set to default registers that may be overriden by 10G force */ 3720 for (i = 0; i < ARRAY_SIZE(reg_set); i++) 3721 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg, 3722 reg_set[i].val); 3723 3724 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 3725 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, &cl72_ctrl); 3726 cl72_ctrl &= 0x08ff; 3727 cl72_ctrl |= 0x3800; 3728 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3729 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, cl72_ctrl); 3730 3731 /* Check adding advertisement for 1G KX */ 3732 if (((vars->line_speed == SPEED_AUTO_NEG) && 3733 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) || 3734 (vars->line_speed == SPEED_1000)) { 3735 u16 addr = MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2; 3736 an_adv |= (1<<5); 3737 3738 /* Enable CL37 1G Parallel Detect */ 3739 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, addr, 0x1); 3740 DP(NETIF_MSG_LINK, "Advertize 1G\n"); 3741 } 3742 if (((vars->line_speed == SPEED_AUTO_NEG) && 3743 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) || 3744 (vars->line_speed == SPEED_10000)) { 3745 /* Check adding advertisement for 10G KR */ 3746 an_adv |= (1<<7); 3747 /* Enable 10G Parallel Detect */ 3748 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, 3749 MDIO_AER_BLOCK_AER_REG, 0); 3750 3751 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, 3752 MDIO_WC_REG_PAR_DET_10G_CTRL, 1); 3753 bnx2x_set_aer_mmd(params, phy); 3754 DP(NETIF_MSG_LINK, "Advertize 10G\n"); 3755 } 3756 3757 /* Set Transmit PMD settings */ 3758 lane = bnx2x_get_warpcore_lane(phy, params); 3759 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3760 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 3761 WC_TX_DRIVER(0x02, 0x06, 0x09)); 3762 /* Configure the next lane if dual mode */ 3763 if (phy->flags & FLAGS_WC_DUAL_MODE) 3764 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3765 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*(lane+1), 3766 WC_TX_DRIVER(0x02, 0x06, 0x09)); 3767 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3768 MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL, 3769 0x03f0); 3770 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3771 MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL, 3772 0x03f0); 3773 3774 /* Advertised speeds */ 3775 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, 3776 MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, an_adv); 3777 3778 /* Advertised and set FEC (Forward Error Correction) */ 3779 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, 3780 MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2, 3781 (MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY | 3782 MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ)); 3783 3784 /* Enable CL37 BAM */ 3785 if (REG_RD(bp, params->shmem_base + 3786 offsetof(struct shmem_region, dev_info. 3787 port_hw_config[params->port].default_cfg)) & 3788 PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) { 3789 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 3790 MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL, 3791 1); 3792 DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n"); 3793 } 3794 3795 /* Advertise pause */ 3796 bnx2x_ext_phy_set_pause(params, phy, vars); 3797 vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY; 3798 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 3799 MDIO_WC_REG_DIGITAL5_MISC7, 0x100); 3800 3801 /* Over 1G - AN local device user page 1 */ 3802 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3803 MDIO_WC_REG_DIGITAL3_UP1, 0x1f); 3804 3805 if (((phy->req_line_speed == SPEED_AUTO_NEG) && 3806 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) || 3807 (phy->req_line_speed == SPEED_20000)) { 3808 3809 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, 3810 MDIO_AER_BLOCK_AER_REG, lane); 3811 3812 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 3813 MDIO_WC_REG_RX1_PCI_CTRL + (0x10*lane), 3814 (1<<11)); 3815 3816 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3817 MDIO_WC_REG_XGXS_X2_CONTROL3, 0x7); 3818 bnx2x_set_aer_mmd(params, phy); 3819 3820 bnx2x_warpcore_enable_AN_KR2(phy, params, vars); 3821 } else { 3822 /* Enable Auto-Detect to support 1G over CL37 as well */ 3823 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3824 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0x10); 3825 wc_lane_config = REG_RD(bp, params->shmem_base + 3826 offsetof(struct shmem_region, dev_info. 3827 shared_hw_config.wc_lane_config)); 3828 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 3829 MDIO_WC_REG_RX0_PCI_CTRL + (lane << 4), &val); 3830 /* Force cl48 sync_status LOW to avoid getting stuck in CL73 3831 * parallel-detect loop when CL73 and CL37 are enabled. 3832 */ 3833 val |= 1 << 11; 3834 3835 /* Restore Polarity settings in case it was run over by 3836 * previous link owner 3837 */ 3838 if (wc_lane_config & 3839 (SHARED_HW_CFG_RX_LANE0_POL_FLIP_ENABLED << lane)) 3840 val |= 3 << 2; 3841 else 3842 val &= ~(3 << 2); 3843 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3844 MDIO_WC_REG_RX0_PCI_CTRL + (lane << 4), 3845 val); 3846 3847 bnx2x_disable_kr2(params, vars, phy); 3848 } 3849 3850 /* Enable Autoneg: only on the main lane */ 3851 bnx2x_warpcore_restart_AN_KR(phy, params); 3852 } 3853 3854 static void bnx2x_warpcore_set_10G_KR(struct bnx2x_phy *phy, 3855 struct link_params *params, 3856 struct link_vars *vars) 3857 { 3858 struct bnx2x *bp = params->bp; 3859 u16 val16, i, lane; 3860 static struct bnx2x_reg_set reg_set[] = { 3861 /* Disable Autoneg */ 3862 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7}, 3863 {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, 3864 0x3f00}, 3865 {MDIO_AN_DEVAD, MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, 0}, 3866 {MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0}, 3867 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL3_UP1, 0x1}, 3868 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL5_MISC7, 0xa}, 3869 /* Leave cl72 training enable, needed for KR */ 3870 {MDIO_PMA_DEVAD, MDIO_WC_REG_PMD_KR_CONTROL, 0x2} 3871 }; 3872 3873 for (i = 0; i < ARRAY_SIZE(reg_set); i++) 3874 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg, 3875 reg_set[i].val); 3876 3877 lane = bnx2x_get_warpcore_lane(phy, params); 3878 /* Global registers */ 3879 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, 3880 MDIO_AER_BLOCK_AER_REG, 0); 3881 /* Disable CL36 PCS Tx */ 3882 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 3883 MDIO_WC_REG_XGXSBLK1_LANECTRL0, &val16); 3884 val16 &= ~(0x0011 << lane); 3885 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3886 MDIO_WC_REG_XGXSBLK1_LANECTRL0, val16); 3887 3888 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 3889 MDIO_WC_REG_XGXSBLK1_LANECTRL1, &val16); 3890 val16 |= (0x0303 << (lane << 1)); 3891 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3892 MDIO_WC_REG_XGXSBLK1_LANECTRL1, val16); 3893 /* Restore AER */ 3894 bnx2x_set_aer_mmd(params, phy); 3895 /* Set speed via PMA/PMD register */ 3896 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 3897 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040); 3898 3899 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 3900 MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0xB); 3901 3902 /* Enable encoded forced speed */ 3903 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3904 MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x30); 3905 3906 /* Turn TX scramble payload only the 64/66 scrambler */ 3907 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3908 MDIO_WC_REG_TX66_CONTROL, 0x9); 3909 3910 /* Turn RX scramble payload only the 64/66 scrambler */ 3911 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 3912 MDIO_WC_REG_RX66_CONTROL, 0xF9); 3913 3914 /* Set and clear loopback to cause a reset to 64/66 decoder */ 3915 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3916 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x4000); 3917 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3918 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0); 3919 3920 } 3921 3922 static void bnx2x_warpcore_set_10G_XFI(struct bnx2x_phy *phy, 3923 struct link_params *params, 3924 u8 is_xfi) 3925 { 3926 struct bnx2x *bp = params->bp; 3927 u16 misc1_val, tap_val, tx_driver_val, lane, val; 3928 u32 cfg_tap_val, tx_drv_brdct, tx_equal; 3929 3930 /* Hold rxSeqStart */ 3931 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 3932 MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x8000); 3933 3934 /* Hold tx_fifo_reset */ 3935 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 3936 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, 0x1); 3937 3938 /* Disable CL73 AN */ 3939 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0); 3940 3941 /* Disable 100FX Enable and Auto-Detect */ 3942 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, 3943 MDIO_WC_REG_FX100_CTRL1, 0xFFFA); 3944 3945 /* Disable 100FX Idle detect */ 3946 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 3947 MDIO_WC_REG_FX100_CTRL3, 0x0080); 3948 3949 /* Set Block address to Remote PHY & Clear forced_speed[5] */ 3950 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, 3951 MDIO_WC_REG_DIGITAL4_MISC3, 0xFF7F); 3952 3953 /* Turn off auto-detect & fiber mode */ 3954 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, 3955 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 3956 0xFFEE); 3957 3958 /* Set filter_force_link, disable_false_link and parallel_detect */ 3959 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 3960 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &val); 3961 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3962 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 3963 ((val | 0x0006) & 0xFFFE)); 3964 3965 /* Set XFI / SFI */ 3966 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 3967 MDIO_WC_REG_SERDESDIGITAL_MISC1, &misc1_val); 3968 3969 misc1_val &= ~(0x1f); 3970 3971 if (is_xfi) { 3972 misc1_val |= 0x5; 3973 tap_val = WC_TX_FIR(0x08, 0x37, 0x00); 3974 tx_driver_val = WC_TX_DRIVER(0x00, 0x02, 0x03); 3975 } else { 3976 cfg_tap_val = REG_RD(bp, params->shmem_base + 3977 offsetof(struct shmem_region, dev_info. 3978 port_hw_config[params->port]. 3979 sfi_tap_values)); 3980 3981 tx_equal = cfg_tap_val & PORT_HW_CFG_TX_EQUALIZATION_MASK; 3982 3983 tx_drv_brdct = (cfg_tap_val & 3984 PORT_HW_CFG_TX_DRV_BROADCAST_MASK) >> 3985 PORT_HW_CFG_TX_DRV_BROADCAST_SHIFT; 3986 3987 misc1_val |= 0x9; 3988 3989 /* TAP values are controlled by nvram, if value there isn't 0 */ 3990 if (tx_equal) 3991 tap_val = (u16)tx_equal; 3992 else 3993 tap_val = WC_TX_FIR(0x0f, 0x2b, 0x02); 3994 3995 if (tx_drv_brdct) 3996 tx_driver_val = WC_TX_DRIVER(0x03, (u16)tx_drv_brdct, 3997 0x06); 3998 else 3999 tx_driver_val = WC_TX_DRIVER(0x03, 0x02, 0x06); 4000 } 4001 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4002 MDIO_WC_REG_SERDESDIGITAL_MISC1, misc1_val); 4003 4004 /* Set Transmit PMD settings */ 4005 lane = bnx2x_get_warpcore_lane(phy, params); 4006 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4007 MDIO_WC_REG_TX_FIR_TAP, 4008 tap_val | MDIO_WC_REG_TX_FIR_TAP_ENABLE); 4009 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4010 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 4011 tx_driver_val); 4012 4013 /* Enable fiber mode, enable and invert sig_det */ 4014 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 4015 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0xd); 4016 4017 /* Set Block address to Remote PHY & Set forced_speed[5], 40bit mode */ 4018 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 4019 MDIO_WC_REG_DIGITAL4_MISC3, 0x8080); 4020 4021 bnx2x_warpcore_set_lpi_passthrough(phy, params); 4022 4023 /* 10G XFI Full Duplex */ 4024 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4025 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x100); 4026 4027 /* Release tx_fifo_reset */ 4028 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, 4029 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, 4030 0xFFFE); 4031 /* Release rxSeqStart */ 4032 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, 4033 MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x7FFF); 4034 } 4035 4036 static void bnx2x_warpcore_set_20G_force_KR2(struct bnx2x_phy *phy, 4037 struct link_params *params) 4038 { 4039 u16 val; 4040 struct bnx2x *bp = params->bp; 4041 /* Set global registers, so set AER lane to 0 */ 4042 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, 4043 MDIO_AER_BLOCK_AER_REG, 0); 4044 4045 /* Disable sequencer */ 4046 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, 4047 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, ~(1<<13)); 4048 4049 bnx2x_set_aer_mmd(params, phy); 4050 4051 bnx2x_cl45_read_and_write(bp, phy, MDIO_PMA_DEVAD, 4052 MDIO_WC_REG_PMD_KR_CONTROL, ~(1<<1)); 4053 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, 4054 MDIO_AN_REG_CTRL, 0); 4055 /* Turn off CL73 */ 4056 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 4057 MDIO_WC_REG_CL73_USERB0_CTRL, &val); 4058 val &= ~(1<<5); 4059 val |= (1<<6); 4060 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4061 MDIO_WC_REG_CL73_USERB0_CTRL, val); 4062 4063 /* Set 20G KR2 force speed */ 4064 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 4065 MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x1f); 4066 4067 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 4068 MDIO_WC_REG_DIGITAL4_MISC3, (1<<7)); 4069 4070 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 4071 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, &val); 4072 val &= ~(3<<14); 4073 val |= (1<<15); 4074 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4075 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, val); 4076 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4077 MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP, 0x835A); 4078 4079 /* Enable sequencer (over lane 0) */ 4080 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, 4081 MDIO_AER_BLOCK_AER_REG, 0); 4082 4083 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 4084 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, (1<<13)); 4085 4086 bnx2x_set_aer_mmd(params, phy); 4087 } 4088 4089 static void bnx2x_warpcore_set_20G_DXGXS(struct bnx2x *bp, 4090 struct bnx2x_phy *phy, 4091 u16 lane) 4092 { 4093 /* Rx0 anaRxControl1G */ 4094 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4095 MDIO_WC_REG_RX0_ANARXCONTROL1G, 0x90); 4096 4097 /* Rx2 anaRxControl1G */ 4098 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4099 MDIO_WC_REG_RX2_ANARXCONTROL1G, 0x90); 4100 4101 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4102 MDIO_WC_REG_RX66_SCW0, 0xE070); 4103 4104 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4105 MDIO_WC_REG_RX66_SCW1, 0xC0D0); 4106 4107 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4108 MDIO_WC_REG_RX66_SCW2, 0xA0B0); 4109 4110 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4111 MDIO_WC_REG_RX66_SCW3, 0x8090); 4112 4113 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4114 MDIO_WC_REG_RX66_SCW0_MASK, 0xF0F0); 4115 4116 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4117 MDIO_WC_REG_RX66_SCW1_MASK, 0xF0F0); 4118 4119 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4120 MDIO_WC_REG_RX66_SCW2_MASK, 0xF0F0); 4121 4122 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4123 MDIO_WC_REG_RX66_SCW3_MASK, 0xF0F0); 4124 4125 /* Serdes Digital Misc1 */ 4126 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4127 MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6008); 4128 4129 /* Serdes Digital4 Misc3 */ 4130 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4131 MDIO_WC_REG_DIGITAL4_MISC3, 0x8088); 4132 4133 /* Set Transmit PMD settings */ 4134 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4135 MDIO_WC_REG_TX_FIR_TAP, 4136 (WC_TX_FIR(0x12, 0x2d, 0x00) | 4137 MDIO_WC_REG_TX_FIR_TAP_ENABLE)); 4138 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4139 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 4140 WC_TX_DRIVER(0x02, 0x02, 0x02)); 4141 } 4142 4143 static void bnx2x_warpcore_set_sgmii_speed(struct bnx2x_phy *phy, 4144 struct link_params *params, 4145 u8 fiber_mode, 4146 u8 always_autoneg) 4147 { 4148 struct bnx2x *bp = params->bp; 4149 u16 val16, digctrl_kx1, digctrl_kx2; 4150 4151 /* Clear XFI clock comp in non-10G single lane mode. */ 4152 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, 4153 MDIO_WC_REG_RX66_CONTROL, ~(3<<13)); 4154 4155 bnx2x_warpcore_set_lpi_passthrough(phy, params); 4156 4157 if (always_autoneg || phy->req_line_speed == SPEED_AUTO_NEG) { 4158 /* SGMII Autoneg */ 4159 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 4160 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 4161 0x1000); 4162 DP(NETIF_MSG_LINK, "set SGMII AUTONEG\n"); 4163 } else { 4164 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 4165 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16); 4166 val16 &= 0xcebf; 4167 switch (phy->req_line_speed) { 4168 case SPEED_10: 4169 break; 4170 case SPEED_100: 4171 val16 |= 0x2000; 4172 break; 4173 case SPEED_1000: 4174 val16 |= 0x0040; 4175 break; 4176 default: 4177 DP(NETIF_MSG_LINK, 4178 "Speed not supported: 0x%x\n", phy->req_line_speed); 4179 return; 4180 } 4181 4182 if (phy->req_duplex == DUPLEX_FULL) 4183 val16 |= 0x0100; 4184 4185 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4186 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16); 4187 4188 DP(NETIF_MSG_LINK, "set SGMII force speed %d\n", 4189 phy->req_line_speed); 4190 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 4191 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16); 4192 DP(NETIF_MSG_LINK, " (readback) %x\n", val16); 4193 } 4194 4195 /* SGMII Slave mode and disable signal detect */ 4196 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 4197 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &digctrl_kx1); 4198 if (fiber_mode) 4199 digctrl_kx1 = 1; 4200 else 4201 digctrl_kx1 &= 0xff4a; 4202 4203 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4204 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 4205 digctrl_kx1); 4206 4207 /* Turn off parallel detect */ 4208 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 4209 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &digctrl_kx2); 4210 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4211 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 4212 (digctrl_kx2 & ~(1<<2))); 4213 4214 /* Re-enable parallel detect */ 4215 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4216 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 4217 (digctrl_kx2 | (1<<2))); 4218 4219 /* Enable autodet */ 4220 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4221 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 4222 (digctrl_kx1 | 0x10)); 4223 } 4224 4225 static void bnx2x_warpcore_reset_lane(struct bnx2x *bp, 4226 struct bnx2x_phy *phy, 4227 u8 reset) 4228 { 4229 u16 val; 4230 /* Take lane out of reset after configuration is finished */ 4231 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 4232 MDIO_WC_REG_DIGITAL5_MISC6, &val); 4233 if (reset) 4234 val |= 0xC000; 4235 else 4236 val &= 0x3FFF; 4237 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4238 MDIO_WC_REG_DIGITAL5_MISC6, val); 4239 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 4240 MDIO_WC_REG_DIGITAL5_MISC6, &val); 4241 } 4242 /* Clear SFI/XFI link settings registers */ 4243 static void bnx2x_warpcore_clear_regs(struct bnx2x_phy *phy, 4244 struct link_params *params, 4245 u16 lane) 4246 { 4247 struct bnx2x *bp = params->bp; 4248 u16 i; 4249 static struct bnx2x_reg_set wc_regs[] = { 4250 {MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0}, 4251 {MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL1, 0x014a}, 4252 {MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL3, 0x0800}, 4253 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL4_MISC3, 0x8008}, 4254 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 4255 0x0195}, 4256 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 4257 0x0007}, 4258 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, 4259 0x0002}, 4260 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6000}, 4261 {MDIO_WC_DEVAD, MDIO_WC_REG_TX_FIR_TAP, 0x0000}, 4262 {MDIO_WC_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040}, 4263 {MDIO_WC_DEVAD, MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0x0140} 4264 }; 4265 /* Set XFI clock comp as default. */ 4266 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 4267 MDIO_WC_REG_RX66_CONTROL, (3<<13)); 4268 4269 for (i = 0; i < ARRAY_SIZE(wc_regs); i++) 4270 bnx2x_cl45_write(bp, phy, wc_regs[i].devad, wc_regs[i].reg, 4271 wc_regs[i].val); 4272 4273 lane = bnx2x_get_warpcore_lane(phy, params); 4274 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4275 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 0x0990); 4276 4277 } 4278 4279 static int bnx2x_get_mod_abs_int_cfg(struct bnx2x *bp, 4280 u32 chip_id, 4281 u32 shmem_base, u8 port, 4282 u8 *gpio_num, u8 *gpio_port) 4283 { 4284 u32 cfg_pin; 4285 *gpio_num = 0; 4286 *gpio_port = 0; 4287 if (CHIP_IS_E3(bp)) { 4288 cfg_pin = (REG_RD(bp, shmem_base + 4289 offsetof(struct shmem_region, 4290 dev_info.port_hw_config[port].e3_sfp_ctrl)) & 4291 PORT_HW_CFG_E3_MOD_ABS_MASK) >> 4292 PORT_HW_CFG_E3_MOD_ABS_SHIFT; 4293 4294 /* Should not happen. This function called upon interrupt 4295 * triggered by GPIO ( since EPIO can only generate interrupts 4296 * to MCP). 4297 * So if this function was called and none of the GPIOs was set, 4298 * it means the shit hit the fan. 4299 */ 4300 if ((cfg_pin < PIN_CFG_GPIO0_P0) || 4301 (cfg_pin > PIN_CFG_GPIO3_P1)) { 4302 DP(NETIF_MSG_LINK, 4303 "No cfg pin %x for module detect indication\n", 4304 cfg_pin); 4305 return -EINVAL; 4306 } 4307 4308 *gpio_num = (cfg_pin - PIN_CFG_GPIO0_P0) & 0x3; 4309 *gpio_port = (cfg_pin - PIN_CFG_GPIO0_P0) >> 2; 4310 } else { 4311 *gpio_num = MISC_REGISTERS_GPIO_3; 4312 *gpio_port = port; 4313 } 4314 4315 return 0; 4316 } 4317 4318 static int bnx2x_is_sfp_module_plugged(struct bnx2x_phy *phy, 4319 struct link_params *params) 4320 { 4321 struct bnx2x *bp = params->bp; 4322 u8 gpio_num, gpio_port; 4323 u32 gpio_val; 4324 if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id, 4325 params->shmem_base, params->port, 4326 &gpio_num, &gpio_port) != 0) 4327 return 0; 4328 gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port); 4329 4330 /* Call the handling function in case module is detected */ 4331 if (gpio_val == 0) 4332 return 1; 4333 else 4334 return 0; 4335 } 4336 static int bnx2x_warpcore_get_sigdet(struct bnx2x_phy *phy, 4337 struct link_params *params) 4338 { 4339 u16 gp2_status_reg0, lane; 4340 struct bnx2x *bp = params->bp; 4341 4342 lane = bnx2x_get_warpcore_lane(phy, params); 4343 4344 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_0, 4345 &gp2_status_reg0); 4346 4347 return (gp2_status_reg0 >> (8+lane)) & 0x1; 4348 } 4349 4350 static void bnx2x_warpcore_config_runtime(struct bnx2x_phy *phy, 4351 struct link_params *params, 4352 struct link_vars *vars) 4353 { 4354 struct bnx2x *bp = params->bp; 4355 u32 serdes_net_if; 4356 u16 gp_status1 = 0, lnkup = 0, lnkup_kr = 0; 4357 4358 vars->turn_to_run_wc_rt = vars->turn_to_run_wc_rt ? 0 : 1; 4359 4360 if (!vars->turn_to_run_wc_rt) 4361 return; 4362 4363 if (vars->rx_tx_asic_rst) { 4364 u16 lane = bnx2x_get_warpcore_lane(phy, params); 4365 serdes_net_if = (REG_RD(bp, params->shmem_base + 4366 offsetof(struct shmem_region, dev_info. 4367 port_hw_config[params->port].default_cfg)) & 4368 PORT_HW_CFG_NET_SERDES_IF_MASK); 4369 4370 switch (serdes_net_if) { 4371 case PORT_HW_CFG_NET_SERDES_IF_KR: 4372 /* Do we get link yet? */ 4373 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 0x81d1, 4374 &gp_status1); 4375 lnkup = (gp_status1 >> (8+lane)) & 0x1;/* 1G */ 4376 /*10G KR*/ 4377 lnkup_kr = (gp_status1 >> (12+lane)) & 0x1; 4378 4379 if (lnkup_kr || lnkup) { 4380 vars->rx_tx_asic_rst = 0; 4381 } else { 4382 /* Reset the lane to see if link comes up.*/ 4383 bnx2x_warpcore_reset_lane(bp, phy, 1); 4384 bnx2x_warpcore_reset_lane(bp, phy, 0); 4385 4386 /* Restart Autoneg */ 4387 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, 4388 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200); 4389 4390 vars->rx_tx_asic_rst--; 4391 DP(NETIF_MSG_LINK, "0x%x retry left\n", 4392 vars->rx_tx_asic_rst); 4393 } 4394 break; 4395 4396 default: 4397 break; 4398 } 4399 4400 } /*params->rx_tx_asic_rst*/ 4401 4402 } 4403 static void bnx2x_warpcore_config_sfi(struct bnx2x_phy *phy, 4404 struct link_params *params) 4405 { 4406 u16 lane = bnx2x_get_warpcore_lane(phy, params); 4407 struct bnx2x *bp = params->bp; 4408 bnx2x_warpcore_clear_regs(phy, params, lane); 4409 if ((params->req_line_speed[LINK_CONFIG_IDX(INT_PHY)] == 4410 SPEED_10000) && 4411 (phy->media_type != ETH_PHY_SFP_1G_FIBER)) { 4412 DP(NETIF_MSG_LINK, "Setting 10G SFI\n"); 4413 bnx2x_warpcore_set_10G_XFI(phy, params, 0); 4414 } else { 4415 DP(NETIF_MSG_LINK, "Setting 1G Fiber\n"); 4416 bnx2x_warpcore_set_sgmii_speed(phy, params, 1, 0); 4417 } 4418 } 4419 4420 static void bnx2x_sfp_e3_set_transmitter(struct link_params *params, 4421 struct bnx2x_phy *phy, 4422 u8 tx_en) 4423 { 4424 struct bnx2x *bp = params->bp; 4425 u32 cfg_pin; 4426 u8 port = params->port; 4427 4428 cfg_pin = REG_RD(bp, params->shmem_base + 4429 offsetof(struct shmem_region, 4430 dev_info.port_hw_config[port].e3_sfp_ctrl)) & 4431 PORT_HW_CFG_E3_TX_LASER_MASK; 4432 /* Set the !tx_en since this pin is DISABLE_TX_LASER */ 4433 DP(NETIF_MSG_LINK, "Setting WC TX to %d\n", tx_en); 4434 4435 /* For 20G, the expected pin to be used is 3 pins after the current */ 4436 bnx2x_set_cfg_pin(bp, cfg_pin, tx_en ^ 1); 4437 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G) 4438 bnx2x_set_cfg_pin(bp, cfg_pin + 3, tx_en ^ 1); 4439 } 4440 4441 static void bnx2x_warpcore_config_init(struct bnx2x_phy *phy, 4442 struct link_params *params, 4443 struct link_vars *vars) 4444 { 4445 struct bnx2x *bp = params->bp; 4446 u32 serdes_net_if; 4447 u8 fiber_mode; 4448 u16 lane = bnx2x_get_warpcore_lane(phy, params); 4449 serdes_net_if = (REG_RD(bp, params->shmem_base + 4450 offsetof(struct shmem_region, dev_info. 4451 port_hw_config[params->port].default_cfg)) & 4452 PORT_HW_CFG_NET_SERDES_IF_MASK); 4453 DP(NETIF_MSG_LINK, "Begin Warpcore init, link_speed %d, " 4454 "serdes_net_if = 0x%x\n", 4455 vars->line_speed, serdes_net_if); 4456 bnx2x_set_aer_mmd(params, phy); 4457 bnx2x_warpcore_reset_lane(bp, phy, 1); 4458 vars->phy_flags |= PHY_XGXS_FLAG; 4459 if ((serdes_net_if == PORT_HW_CFG_NET_SERDES_IF_SGMII) || 4460 (phy->req_line_speed && 4461 ((phy->req_line_speed == SPEED_100) || 4462 (phy->req_line_speed == SPEED_10)))) { 4463 vars->phy_flags |= PHY_SGMII_FLAG; 4464 DP(NETIF_MSG_LINK, "Setting SGMII mode\n"); 4465 bnx2x_warpcore_clear_regs(phy, params, lane); 4466 bnx2x_warpcore_set_sgmii_speed(phy, params, 0, 1); 4467 } else { 4468 switch (serdes_net_if) { 4469 case PORT_HW_CFG_NET_SERDES_IF_KR: 4470 /* Enable KR Auto Neg */ 4471 if (params->loopback_mode != LOOPBACK_EXT) 4472 bnx2x_warpcore_enable_AN_KR(phy, params, vars); 4473 else { 4474 DP(NETIF_MSG_LINK, "Setting KR 10G-Force\n"); 4475 bnx2x_warpcore_set_10G_KR(phy, params, vars); 4476 } 4477 break; 4478 4479 case PORT_HW_CFG_NET_SERDES_IF_XFI: 4480 bnx2x_warpcore_clear_regs(phy, params, lane); 4481 if (vars->line_speed == SPEED_10000) { 4482 DP(NETIF_MSG_LINK, "Setting 10G XFI\n"); 4483 bnx2x_warpcore_set_10G_XFI(phy, params, 1); 4484 } else { 4485 if (SINGLE_MEDIA_DIRECT(params)) { 4486 DP(NETIF_MSG_LINK, "1G Fiber\n"); 4487 fiber_mode = 1; 4488 } else { 4489 DP(NETIF_MSG_LINK, "10/100/1G SGMII\n"); 4490 fiber_mode = 0; 4491 } 4492 bnx2x_warpcore_set_sgmii_speed(phy, 4493 params, 4494 fiber_mode, 4495 0); 4496 } 4497 4498 break; 4499 4500 case PORT_HW_CFG_NET_SERDES_IF_SFI: 4501 /* Issue Module detection if module is plugged, or 4502 * enabled transmitter to avoid current leakage in case 4503 * no module is connected 4504 */ 4505 if ((params->loopback_mode == LOOPBACK_NONE) || 4506 (params->loopback_mode == LOOPBACK_EXT)) { 4507 if (bnx2x_is_sfp_module_plugged(phy, params)) 4508 bnx2x_sfp_module_detection(phy, params); 4509 else 4510 bnx2x_sfp_e3_set_transmitter(params, 4511 phy, 1); 4512 } 4513 4514 bnx2x_warpcore_config_sfi(phy, params); 4515 break; 4516 4517 case PORT_HW_CFG_NET_SERDES_IF_DXGXS: 4518 if (vars->line_speed != SPEED_20000) { 4519 DP(NETIF_MSG_LINK, "Speed not supported yet\n"); 4520 return; 4521 } 4522 DP(NETIF_MSG_LINK, "Setting 20G DXGXS\n"); 4523 bnx2x_warpcore_set_20G_DXGXS(bp, phy, lane); 4524 /* Issue Module detection */ 4525 4526 bnx2x_sfp_module_detection(phy, params); 4527 break; 4528 case PORT_HW_CFG_NET_SERDES_IF_KR2: 4529 if (!params->loopback_mode) { 4530 bnx2x_warpcore_enable_AN_KR(phy, params, vars); 4531 } else { 4532 DP(NETIF_MSG_LINK, "Setting KR 20G-Force\n"); 4533 bnx2x_warpcore_set_20G_force_KR2(phy, params); 4534 } 4535 break; 4536 default: 4537 DP(NETIF_MSG_LINK, 4538 "Unsupported Serdes Net Interface 0x%x\n", 4539 serdes_net_if); 4540 return; 4541 } 4542 } 4543 4544 /* Take lane out of reset after configuration is finished */ 4545 bnx2x_warpcore_reset_lane(bp, phy, 0); 4546 DP(NETIF_MSG_LINK, "Exit config init\n"); 4547 } 4548 4549 static void bnx2x_warpcore_link_reset(struct bnx2x_phy *phy, 4550 struct link_params *params) 4551 { 4552 struct bnx2x *bp = params->bp; 4553 u16 val16, lane; 4554 bnx2x_sfp_e3_set_transmitter(params, phy, 0); 4555 bnx2x_set_mdio_emac_per_phy(bp, params); 4556 bnx2x_set_aer_mmd(params, phy); 4557 /* Global register */ 4558 bnx2x_warpcore_reset_lane(bp, phy, 1); 4559 4560 /* Clear loopback settings (if any) */ 4561 /* 10G & 20G */ 4562 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, 4563 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0xBFFF); 4564 4565 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, 4566 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0xfffe); 4567 4568 /* Update those 1-copy registers */ 4569 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, 4570 MDIO_AER_BLOCK_AER_REG, 0); 4571 /* Enable 1G MDIO (1-copy) */ 4572 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, 4573 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, 4574 ~0x10); 4575 4576 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, 4577 MDIO_WC_REG_XGXSBLK1_LANECTRL2, 0xff00); 4578 lane = bnx2x_get_warpcore_lane(phy, params); 4579 /* Disable CL36 PCS Tx */ 4580 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 4581 MDIO_WC_REG_XGXSBLK1_LANECTRL0, &val16); 4582 val16 |= (0x11 << lane); 4583 if (phy->flags & FLAGS_WC_DUAL_MODE) 4584 val16 |= (0x22 << lane); 4585 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4586 MDIO_WC_REG_XGXSBLK1_LANECTRL0, val16); 4587 4588 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 4589 MDIO_WC_REG_XGXSBLK1_LANECTRL1, &val16); 4590 val16 &= ~(0x0303 << (lane << 1)); 4591 val16 |= (0x0101 << (lane << 1)); 4592 if (phy->flags & FLAGS_WC_DUAL_MODE) { 4593 val16 &= ~(0x0c0c << (lane << 1)); 4594 val16 |= (0x0404 << (lane << 1)); 4595 } 4596 4597 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4598 MDIO_WC_REG_XGXSBLK1_LANECTRL1, val16); 4599 /* Restore AER */ 4600 bnx2x_set_aer_mmd(params, phy); 4601 4602 } 4603 4604 static void bnx2x_set_warpcore_loopback(struct bnx2x_phy *phy, 4605 struct link_params *params) 4606 { 4607 struct bnx2x *bp = params->bp; 4608 u16 val16; 4609 u32 lane; 4610 DP(NETIF_MSG_LINK, "Setting Warpcore loopback type %x, speed %d\n", 4611 params->loopback_mode, phy->req_line_speed); 4612 4613 if (phy->req_line_speed < SPEED_10000 || 4614 phy->supported & SUPPORTED_20000baseKR2_Full) { 4615 /* 10/100/1000/20G-KR2 */ 4616 4617 /* Update those 1-copy registers */ 4618 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, 4619 MDIO_AER_BLOCK_AER_REG, 0); 4620 /* Enable 1G MDIO (1-copy) */ 4621 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 4622 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, 4623 0x10); 4624 /* Set 1G loopback based on lane (1-copy) */ 4625 lane = bnx2x_get_warpcore_lane(phy, params); 4626 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 4627 MDIO_WC_REG_XGXSBLK1_LANECTRL2, &val16); 4628 val16 |= (1<<lane); 4629 if (phy->flags & FLAGS_WC_DUAL_MODE) 4630 val16 |= (2<<lane); 4631 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4632 MDIO_WC_REG_XGXSBLK1_LANECTRL2, 4633 val16); 4634 4635 /* Switch back to 4-copy registers */ 4636 bnx2x_set_aer_mmd(params, phy); 4637 } else { 4638 /* 10G / 20G-DXGXS */ 4639 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 4640 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 4641 0x4000); 4642 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 4643 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1); 4644 } 4645 } 4646 4647 4648 4649 static void bnx2x_sync_link(struct link_params *params, 4650 struct link_vars *vars) 4651 { 4652 struct bnx2x *bp = params->bp; 4653 u8 link_10g_plus; 4654 if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG) 4655 vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG; 4656 vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP); 4657 if (vars->link_up) { 4658 DP(NETIF_MSG_LINK, "phy link up\n"); 4659 4660 vars->phy_link_up = 1; 4661 vars->duplex = DUPLEX_FULL; 4662 switch (vars->link_status & 4663 LINK_STATUS_SPEED_AND_DUPLEX_MASK) { 4664 case LINK_10THD: 4665 vars->duplex = DUPLEX_HALF; 4666 /* Fall thru */ 4667 case LINK_10TFD: 4668 vars->line_speed = SPEED_10; 4669 break; 4670 4671 case LINK_100TXHD: 4672 vars->duplex = DUPLEX_HALF; 4673 /* Fall thru */ 4674 case LINK_100T4: 4675 case LINK_100TXFD: 4676 vars->line_speed = SPEED_100; 4677 break; 4678 4679 case LINK_1000THD: 4680 vars->duplex = DUPLEX_HALF; 4681 /* Fall thru */ 4682 case LINK_1000TFD: 4683 vars->line_speed = SPEED_1000; 4684 break; 4685 4686 case LINK_2500THD: 4687 vars->duplex = DUPLEX_HALF; 4688 /* Fall thru */ 4689 case LINK_2500TFD: 4690 vars->line_speed = SPEED_2500; 4691 break; 4692 4693 case LINK_10GTFD: 4694 vars->line_speed = SPEED_10000; 4695 break; 4696 case LINK_20GTFD: 4697 vars->line_speed = SPEED_20000; 4698 break; 4699 default: 4700 break; 4701 } 4702 vars->flow_ctrl = 0; 4703 if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED) 4704 vars->flow_ctrl |= BNX2X_FLOW_CTRL_TX; 4705 4706 if (vars->link_status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED) 4707 vars->flow_ctrl |= BNX2X_FLOW_CTRL_RX; 4708 4709 if (!vars->flow_ctrl) 4710 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; 4711 4712 if (vars->line_speed && 4713 ((vars->line_speed == SPEED_10) || 4714 (vars->line_speed == SPEED_100))) { 4715 vars->phy_flags |= PHY_SGMII_FLAG; 4716 } else { 4717 vars->phy_flags &= ~PHY_SGMII_FLAG; 4718 } 4719 if (vars->line_speed && 4720 USES_WARPCORE(bp) && 4721 (vars->line_speed == SPEED_1000)) 4722 vars->phy_flags |= PHY_SGMII_FLAG; 4723 /* Anything 10 and over uses the bmac */ 4724 link_10g_plus = (vars->line_speed >= SPEED_10000); 4725 4726 if (link_10g_plus) { 4727 if (USES_WARPCORE(bp)) 4728 vars->mac_type = MAC_TYPE_XMAC; 4729 else 4730 vars->mac_type = MAC_TYPE_BMAC; 4731 } else { 4732 if (USES_WARPCORE(bp)) 4733 vars->mac_type = MAC_TYPE_UMAC; 4734 else 4735 vars->mac_type = MAC_TYPE_EMAC; 4736 } 4737 } else { /* Link down */ 4738 DP(NETIF_MSG_LINK, "phy link down\n"); 4739 4740 vars->phy_link_up = 0; 4741 4742 vars->line_speed = 0; 4743 vars->duplex = DUPLEX_FULL; 4744 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; 4745 4746 /* Indicate no mac active */ 4747 vars->mac_type = MAC_TYPE_NONE; 4748 if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG) 4749 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG; 4750 if (vars->link_status & LINK_STATUS_SFP_TX_FAULT) 4751 vars->phy_flags |= PHY_SFP_TX_FAULT_FLAG; 4752 } 4753 } 4754 4755 void bnx2x_link_status_update(struct link_params *params, 4756 struct link_vars *vars) 4757 { 4758 struct bnx2x *bp = params->bp; 4759 u8 port = params->port; 4760 u32 sync_offset, media_types; 4761 /* Update PHY configuration */ 4762 set_phy_vars(params, vars); 4763 4764 vars->link_status = REG_RD(bp, params->shmem_base + 4765 offsetof(struct shmem_region, 4766 port_mb[port].link_status)); 4767 4768 /* Force link UP in non LOOPBACK_EXT loopback mode(s) */ 4769 if (params->loopback_mode != LOOPBACK_NONE && 4770 params->loopback_mode != LOOPBACK_EXT) 4771 vars->link_status |= LINK_STATUS_LINK_UP; 4772 4773 if (bnx2x_eee_has_cap(params)) 4774 vars->eee_status = REG_RD(bp, params->shmem2_base + 4775 offsetof(struct shmem2_region, 4776 eee_status[params->port])); 4777 4778 vars->phy_flags = PHY_XGXS_FLAG; 4779 bnx2x_sync_link(params, vars); 4780 /* Sync media type */ 4781 sync_offset = params->shmem_base + 4782 offsetof(struct shmem_region, 4783 dev_info.port_hw_config[port].media_type); 4784 media_types = REG_RD(bp, sync_offset); 4785 4786 params->phy[INT_PHY].media_type = 4787 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) >> 4788 PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT; 4789 params->phy[EXT_PHY1].media_type = 4790 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK) >> 4791 PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT; 4792 params->phy[EXT_PHY2].media_type = 4793 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK) >> 4794 PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT; 4795 DP(NETIF_MSG_LINK, "media_types = 0x%x\n", media_types); 4796 4797 /* Sync AEU offset */ 4798 sync_offset = params->shmem_base + 4799 offsetof(struct shmem_region, 4800 dev_info.port_hw_config[port].aeu_int_mask); 4801 4802 vars->aeu_int_mask = REG_RD(bp, sync_offset); 4803 4804 /* Sync PFC status */ 4805 if (vars->link_status & LINK_STATUS_PFC_ENABLED) 4806 params->feature_config_flags |= 4807 FEATURE_CONFIG_PFC_ENABLED; 4808 else 4809 params->feature_config_flags &= 4810 ~FEATURE_CONFIG_PFC_ENABLED; 4811 4812 if (SHMEM2_HAS(bp, link_attr_sync)) 4813 vars->link_attr_sync = SHMEM2_RD(bp, 4814 link_attr_sync[params->port]); 4815 4816 DP(NETIF_MSG_LINK, "link_status 0x%x phy_link_up %x int_mask 0x%x\n", 4817 vars->link_status, vars->phy_link_up, vars->aeu_int_mask); 4818 DP(NETIF_MSG_LINK, "line_speed %x duplex %x flow_ctrl 0x%x\n", 4819 vars->line_speed, vars->duplex, vars->flow_ctrl); 4820 } 4821 4822 static void bnx2x_set_master_ln(struct link_params *params, 4823 struct bnx2x_phy *phy) 4824 { 4825 struct bnx2x *bp = params->bp; 4826 u16 new_master_ln, ser_lane; 4827 ser_lane = ((params->lane_config & 4828 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >> 4829 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT); 4830 4831 /* Set the master_ln for AN */ 4832 CL22_RD_OVER_CL45(bp, phy, 4833 MDIO_REG_BANK_XGXS_BLOCK2, 4834 MDIO_XGXS_BLOCK2_TEST_MODE_LANE, 4835 &new_master_ln); 4836 4837 CL22_WR_OVER_CL45(bp, phy, 4838 MDIO_REG_BANK_XGXS_BLOCK2 , 4839 MDIO_XGXS_BLOCK2_TEST_MODE_LANE, 4840 (new_master_ln | ser_lane)); 4841 } 4842 4843 static int bnx2x_reset_unicore(struct link_params *params, 4844 struct bnx2x_phy *phy, 4845 u8 set_serdes) 4846 { 4847 struct bnx2x *bp = params->bp; 4848 u16 mii_control; 4849 u16 i; 4850 CL22_RD_OVER_CL45(bp, phy, 4851 MDIO_REG_BANK_COMBO_IEEE0, 4852 MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control); 4853 4854 /* Reset the unicore */ 4855 CL22_WR_OVER_CL45(bp, phy, 4856 MDIO_REG_BANK_COMBO_IEEE0, 4857 MDIO_COMBO_IEEE0_MII_CONTROL, 4858 (mii_control | 4859 MDIO_COMBO_IEEO_MII_CONTROL_RESET)); 4860 if (set_serdes) 4861 bnx2x_set_serdes_access(bp, params->port); 4862 4863 /* Wait for the reset to self clear */ 4864 for (i = 0; i < MDIO_ACCESS_TIMEOUT; i++) { 4865 udelay(5); 4866 4867 /* The reset erased the previous bank value */ 4868 CL22_RD_OVER_CL45(bp, phy, 4869 MDIO_REG_BANK_COMBO_IEEE0, 4870 MDIO_COMBO_IEEE0_MII_CONTROL, 4871 &mii_control); 4872 4873 if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) { 4874 udelay(5); 4875 return 0; 4876 } 4877 } 4878 4879 netdev_err(bp->dev, "Warning: PHY was not initialized," 4880 " Port %d\n", 4881 params->port); 4882 DP(NETIF_MSG_LINK, "BUG! XGXS is still in reset!\n"); 4883 return -EINVAL; 4884 4885 } 4886 4887 static void bnx2x_set_swap_lanes(struct link_params *params, 4888 struct bnx2x_phy *phy) 4889 { 4890 struct bnx2x *bp = params->bp; 4891 /* Each two bits represents a lane number: 4892 * No swap is 0123 => 0x1b no need to enable the swap 4893 */ 4894 u16 rx_lane_swap, tx_lane_swap; 4895 4896 rx_lane_swap = ((params->lane_config & 4897 PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >> 4898 PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT); 4899 tx_lane_swap = ((params->lane_config & 4900 PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >> 4901 PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT); 4902 4903 if (rx_lane_swap != 0x1b) { 4904 CL22_WR_OVER_CL45(bp, phy, 4905 MDIO_REG_BANK_XGXS_BLOCK2, 4906 MDIO_XGXS_BLOCK2_RX_LN_SWAP, 4907 (rx_lane_swap | 4908 MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE | 4909 MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE)); 4910 } else { 4911 CL22_WR_OVER_CL45(bp, phy, 4912 MDIO_REG_BANK_XGXS_BLOCK2, 4913 MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0); 4914 } 4915 4916 if (tx_lane_swap != 0x1b) { 4917 CL22_WR_OVER_CL45(bp, phy, 4918 MDIO_REG_BANK_XGXS_BLOCK2, 4919 MDIO_XGXS_BLOCK2_TX_LN_SWAP, 4920 (tx_lane_swap | 4921 MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE)); 4922 } else { 4923 CL22_WR_OVER_CL45(bp, phy, 4924 MDIO_REG_BANK_XGXS_BLOCK2, 4925 MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0); 4926 } 4927 } 4928 4929 static void bnx2x_set_parallel_detection(struct bnx2x_phy *phy, 4930 struct link_params *params) 4931 { 4932 struct bnx2x *bp = params->bp; 4933 u16 control2; 4934 CL22_RD_OVER_CL45(bp, phy, 4935 MDIO_REG_BANK_SERDES_DIGITAL, 4936 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2, 4937 &control2); 4938 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) 4939 control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN; 4940 else 4941 control2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN; 4942 DP(NETIF_MSG_LINK, "phy->speed_cap_mask = 0x%x, control2 = 0x%x\n", 4943 phy->speed_cap_mask, control2); 4944 CL22_WR_OVER_CL45(bp, phy, 4945 MDIO_REG_BANK_SERDES_DIGITAL, 4946 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2, 4947 control2); 4948 4949 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) && 4950 (phy->speed_cap_mask & 4951 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) { 4952 DP(NETIF_MSG_LINK, "XGXS\n"); 4953 4954 CL22_WR_OVER_CL45(bp, phy, 4955 MDIO_REG_BANK_10G_PARALLEL_DETECT, 4956 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK, 4957 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT); 4958 4959 CL22_RD_OVER_CL45(bp, phy, 4960 MDIO_REG_BANK_10G_PARALLEL_DETECT, 4961 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL, 4962 &control2); 4963 4964 4965 control2 |= 4966 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN; 4967 4968 CL22_WR_OVER_CL45(bp, phy, 4969 MDIO_REG_BANK_10G_PARALLEL_DETECT, 4970 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL, 4971 control2); 4972 4973 /* Disable parallel detection of HiG */ 4974 CL22_WR_OVER_CL45(bp, phy, 4975 MDIO_REG_BANK_XGXS_BLOCK2, 4976 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G, 4977 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS | 4978 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS); 4979 } 4980 } 4981 4982 static void bnx2x_set_autoneg(struct bnx2x_phy *phy, 4983 struct link_params *params, 4984 struct link_vars *vars, 4985 u8 enable_cl73) 4986 { 4987 struct bnx2x *bp = params->bp; 4988 u16 reg_val; 4989 4990 /* CL37 Autoneg */ 4991 CL22_RD_OVER_CL45(bp, phy, 4992 MDIO_REG_BANK_COMBO_IEEE0, 4993 MDIO_COMBO_IEEE0_MII_CONTROL, ®_val); 4994 4995 /* CL37 Autoneg Enabled */ 4996 if (vars->line_speed == SPEED_AUTO_NEG) 4997 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN; 4998 else /* CL37 Autoneg Disabled */ 4999 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN | 5000 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN); 5001 5002 CL22_WR_OVER_CL45(bp, phy, 5003 MDIO_REG_BANK_COMBO_IEEE0, 5004 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val); 5005 5006 /* Enable/Disable Autodetection */ 5007 5008 CL22_RD_OVER_CL45(bp, phy, 5009 MDIO_REG_BANK_SERDES_DIGITAL, 5010 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, ®_val); 5011 reg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN | 5012 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT); 5013 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE; 5014 if (vars->line_speed == SPEED_AUTO_NEG) 5015 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET; 5016 else 5017 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET; 5018 5019 CL22_WR_OVER_CL45(bp, phy, 5020 MDIO_REG_BANK_SERDES_DIGITAL, 5021 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val); 5022 5023 /* Enable TetonII and BAM autoneg */ 5024 CL22_RD_OVER_CL45(bp, phy, 5025 MDIO_REG_BANK_BAM_NEXT_PAGE, 5026 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL, 5027 ®_val); 5028 if (vars->line_speed == SPEED_AUTO_NEG) { 5029 /* Enable BAM aneg Mode and TetonII aneg Mode */ 5030 reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE | 5031 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN); 5032 } else { 5033 /* TetonII and BAM Autoneg Disabled */ 5034 reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE | 5035 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN); 5036 } 5037 CL22_WR_OVER_CL45(bp, phy, 5038 MDIO_REG_BANK_BAM_NEXT_PAGE, 5039 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL, 5040 reg_val); 5041 5042 if (enable_cl73) { 5043 /* Enable Cl73 FSM status bits */ 5044 CL22_WR_OVER_CL45(bp, phy, 5045 MDIO_REG_BANK_CL73_USERB0, 5046 MDIO_CL73_USERB0_CL73_UCTRL, 5047 0xe); 5048 5049 /* Enable BAM Station Manager*/ 5050 CL22_WR_OVER_CL45(bp, phy, 5051 MDIO_REG_BANK_CL73_USERB0, 5052 MDIO_CL73_USERB0_CL73_BAM_CTRL1, 5053 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN | 5054 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN | 5055 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN); 5056 5057 /* Advertise CL73 link speeds */ 5058 CL22_RD_OVER_CL45(bp, phy, 5059 MDIO_REG_BANK_CL73_IEEEB1, 5060 MDIO_CL73_IEEEB1_AN_ADV2, 5061 ®_val); 5062 if (phy->speed_cap_mask & 5063 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) 5064 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4; 5065 if (phy->speed_cap_mask & 5066 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) 5067 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX; 5068 5069 CL22_WR_OVER_CL45(bp, phy, 5070 MDIO_REG_BANK_CL73_IEEEB1, 5071 MDIO_CL73_IEEEB1_AN_ADV2, 5072 reg_val); 5073 5074 /* CL73 Autoneg Enabled */ 5075 reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN; 5076 5077 } else /* CL73 Autoneg Disabled */ 5078 reg_val = 0; 5079 5080 CL22_WR_OVER_CL45(bp, phy, 5081 MDIO_REG_BANK_CL73_IEEEB0, 5082 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val); 5083 } 5084 5085 /* Program SerDes, forced speed */ 5086 static void bnx2x_program_serdes(struct bnx2x_phy *phy, 5087 struct link_params *params, 5088 struct link_vars *vars) 5089 { 5090 struct bnx2x *bp = params->bp; 5091 u16 reg_val; 5092 5093 /* Program duplex, disable autoneg and sgmii*/ 5094 CL22_RD_OVER_CL45(bp, phy, 5095 MDIO_REG_BANK_COMBO_IEEE0, 5096 MDIO_COMBO_IEEE0_MII_CONTROL, ®_val); 5097 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX | 5098 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN | 5099 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK); 5100 if (phy->req_duplex == DUPLEX_FULL) 5101 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX; 5102 CL22_WR_OVER_CL45(bp, phy, 5103 MDIO_REG_BANK_COMBO_IEEE0, 5104 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val); 5105 5106 /* Program speed 5107 * - needed only if the speed is greater than 1G (2.5G or 10G) 5108 */ 5109 CL22_RD_OVER_CL45(bp, phy, 5110 MDIO_REG_BANK_SERDES_DIGITAL, 5111 MDIO_SERDES_DIGITAL_MISC1, ®_val); 5112 /* Clearing the speed value before setting the right speed */ 5113 DP(NETIF_MSG_LINK, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val); 5114 5115 reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK | 5116 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL); 5117 5118 if (!((vars->line_speed == SPEED_1000) || 5119 (vars->line_speed == SPEED_100) || 5120 (vars->line_speed == SPEED_10))) { 5121 5122 reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M | 5123 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL); 5124 if (vars->line_speed == SPEED_10000) 5125 reg_val |= 5126 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4; 5127 } 5128 5129 CL22_WR_OVER_CL45(bp, phy, 5130 MDIO_REG_BANK_SERDES_DIGITAL, 5131 MDIO_SERDES_DIGITAL_MISC1, reg_val); 5132 5133 } 5134 5135 static void bnx2x_set_brcm_cl37_advertisement(struct bnx2x_phy *phy, 5136 struct link_params *params) 5137 { 5138 struct bnx2x *bp = params->bp; 5139 u16 val = 0; 5140 5141 /* Set extended capabilities */ 5142 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) 5143 val |= MDIO_OVER_1G_UP1_2_5G; 5144 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) 5145 val |= MDIO_OVER_1G_UP1_10G; 5146 CL22_WR_OVER_CL45(bp, phy, 5147 MDIO_REG_BANK_OVER_1G, 5148 MDIO_OVER_1G_UP1, val); 5149 5150 CL22_WR_OVER_CL45(bp, phy, 5151 MDIO_REG_BANK_OVER_1G, 5152 MDIO_OVER_1G_UP3, 0x400); 5153 } 5154 5155 static void bnx2x_set_ieee_aneg_advertisement(struct bnx2x_phy *phy, 5156 struct link_params *params, 5157 u16 ieee_fc) 5158 { 5159 struct bnx2x *bp = params->bp; 5160 u16 val; 5161 /* For AN, we are always publishing full duplex */ 5162 5163 CL22_WR_OVER_CL45(bp, phy, 5164 MDIO_REG_BANK_COMBO_IEEE0, 5165 MDIO_COMBO_IEEE0_AUTO_NEG_ADV, ieee_fc); 5166 CL22_RD_OVER_CL45(bp, phy, 5167 MDIO_REG_BANK_CL73_IEEEB1, 5168 MDIO_CL73_IEEEB1_AN_ADV1, &val); 5169 val &= ~MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH; 5170 val |= ((ieee_fc<<3) & MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK); 5171 CL22_WR_OVER_CL45(bp, phy, 5172 MDIO_REG_BANK_CL73_IEEEB1, 5173 MDIO_CL73_IEEEB1_AN_ADV1, val); 5174 } 5175 5176 static void bnx2x_restart_autoneg(struct bnx2x_phy *phy, 5177 struct link_params *params, 5178 u8 enable_cl73) 5179 { 5180 struct bnx2x *bp = params->bp; 5181 u16 mii_control; 5182 5183 DP(NETIF_MSG_LINK, "bnx2x_restart_autoneg\n"); 5184 /* Enable and restart BAM/CL37 aneg */ 5185 5186 if (enable_cl73) { 5187 CL22_RD_OVER_CL45(bp, phy, 5188 MDIO_REG_BANK_CL73_IEEEB0, 5189 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, 5190 &mii_control); 5191 5192 CL22_WR_OVER_CL45(bp, phy, 5193 MDIO_REG_BANK_CL73_IEEEB0, 5194 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, 5195 (mii_control | 5196 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN | 5197 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN)); 5198 } else { 5199 5200 CL22_RD_OVER_CL45(bp, phy, 5201 MDIO_REG_BANK_COMBO_IEEE0, 5202 MDIO_COMBO_IEEE0_MII_CONTROL, 5203 &mii_control); 5204 DP(NETIF_MSG_LINK, 5205 "bnx2x_restart_autoneg mii_control before = 0x%x\n", 5206 mii_control); 5207 CL22_WR_OVER_CL45(bp, phy, 5208 MDIO_REG_BANK_COMBO_IEEE0, 5209 MDIO_COMBO_IEEE0_MII_CONTROL, 5210 (mii_control | 5211 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN | 5212 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN)); 5213 } 5214 } 5215 5216 static void bnx2x_initialize_sgmii_process(struct bnx2x_phy *phy, 5217 struct link_params *params, 5218 struct link_vars *vars) 5219 { 5220 struct bnx2x *bp = params->bp; 5221 u16 control1; 5222 5223 /* In SGMII mode, the unicore is always slave */ 5224 5225 CL22_RD_OVER_CL45(bp, phy, 5226 MDIO_REG_BANK_SERDES_DIGITAL, 5227 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, 5228 &control1); 5229 control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT; 5230 /* Set sgmii mode (and not fiber) */ 5231 control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE | 5232 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET | 5233 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE); 5234 CL22_WR_OVER_CL45(bp, phy, 5235 MDIO_REG_BANK_SERDES_DIGITAL, 5236 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, 5237 control1); 5238 5239 /* If forced speed */ 5240 if (!(vars->line_speed == SPEED_AUTO_NEG)) { 5241 /* Set speed, disable autoneg */ 5242 u16 mii_control; 5243 5244 CL22_RD_OVER_CL45(bp, phy, 5245 MDIO_REG_BANK_COMBO_IEEE0, 5246 MDIO_COMBO_IEEE0_MII_CONTROL, 5247 &mii_control); 5248 mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN | 5249 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK| 5250 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX); 5251 5252 switch (vars->line_speed) { 5253 case SPEED_100: 5254 mii_control |= 5255 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100; 5256 break; 5257 case SPEED_1000: 5258 mii_control |= 5259 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000; 5260 break; 5261 case SPEED_10: 5262 /* There is nothing to set for 10M */ 5263 break; 5264 default: 5265 /* Invalid speed for SGMII */ 5266 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n", 5267 vars->line_speed); 5268 break; 5269 } 5270 5271 /* Setting the full duplex */ 5272 if (phy->req_duplex == DUPLEX_FULL) 5273 mii_control |= 5274 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX; 5275 CL22_WR_OVER_CL45(bp, phy, 5276 MDIO_REG_BANK_COMBO_IEEE0, 5277 MDIO_COMBO_IEEE0_MII_CONTROL, 5278 mii_control); 5279 5280 } else { /* AN mode */ 5281 /* Enable and restart AN */ 5282 bnx2x_restart_autoneg(phy, params, 0); 5283 } 5284 } 5285 5286 /* Link management 5287 */ 5288 static int bnx2x_direct_parallel_detect_used(struct bnx2x_phy *phy, 5289 struct link_params *params) 5290 { 5291 struct bnx2x *bp = params->bp; 5292 u16 pd_10g, status2_1000x; 5293 if (phy->req_line_speed != SPEED_AUTO_NEG) 5294 return 0; 5295 CL22_RD_OVER_CL45(bp, phy, 5296 MDIO_REG_BANK_SERDES_DIGITAL, 5297 MDIO_SERDES_DIGITAL_A_1000X_STATUS2, 5298 &status2_1000x); 5299 CL22_RD_OVER_CL45(bp, phy, 5300 MDIO_REG_BANK_SERDES_DIGITAL, 5301 MDIO_SERDES_DIGITAL_A_1000X_STATUS2, 5302 &status2_1000x); 5303 if (status2_1000x & MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED) { 5304 DP(NETIF_MSG_LINK, "1G parallel detect link on port %d\n", 5305 params->port); 5306 return 1; 5307 } 5308 5309 CL22_RD_OVER_CL45(bp, phy, 5310 MDIO_REG_BANK_10G_PARALLEL_DETECT, 5311 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS, 5312 &pd_10g); 5313 5314 if (pd_10g & MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK) { 5315 DP(NETIF_MSG_LINK, "10G parallel detect link on port %d\n", 5316 params->port); 5317 return 1; 5318 } 5319 return 0; 5320 } 5321 5322 static void bnx2x_update_adv_fc(struct bnx2x_phy *phy, 5323 struct link_params *params, 5324 struct link_vars *vars, 5325 u32 gp_status) 5326 { 5327 u16 ld_pause; /* local driver */ 5328 u16 lp_pause; /* link partner */ 5329 u16 pause_result; 5330 struct bnx2x *bp = params->bp; 5331 if ((gp_status & 5332 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | 5333 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) == 5334 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | 5335 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) { 5336 5337 CL22_RD_OVER_CL45(bp, phy, 5338 MDIO_REG_BANK_CL73_IEEEB1, 5339 MDIO_CL73_IEEEB1_AN_ADV1, 5340 &ld_pause); 5341 CL22_RD_OVER_CL45(bp, phy, 5342 MDIO_REG_BANK_CL73_IEEEB1, 5343 MDIO_CL73_IEEEB1_AN_LP_ADV1, 5344 &lp_pause); 5345 pause_result = (ld_pause & 5346 MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK) >> 8; 5347 pause_result |= (lp_pause & 5348 MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK) >> 10; 5349 DP(NETIF_MSG_LINK, "pause_result CL73 0x%x\n", pause_result); 5350 } else { 5351 CL22_RD_OVER_CL45(bp, phy, 5352 MDIO_REG_BANK_COMBO_IEEE0, 5353 MDIO_COMBO_IEEE0_AUTO_NEG_ADV, 5354 &ld_pause); 5355 CL22_RD_OVER_CL45(bp, phy, 5356 MDIO_REG_BANK_COMBO_IEEE0, 5357 MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1, 5358 &lp_pause); 5359 pause_result = (ld_pause & 5360 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>5; 5361 pause_result |= (lp_pause & 5362 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7; 5363 DP(NETIF_MSG_LINK, "pause_result CL37 0x%x\n", pause_result); 5364 } 5365 bnx2x_pause_resolve(vars, pause_result); 5366 5367 } 5368 5369 static void bnx2x_flow_ctrl_resolve(struct bnx2x_phy *phy, 5370 struct link_params *params, 5371 struct link_vars *vars, 5372 u32 gp_status) 5373 { 5374 struct bnx2x *bp = params->bp; 5375 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; 5376 5377 /* Resolve from gp_status in case of AN complete and not sgmii */ 5378 if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO) { 5379 /* Update the advertised flow-controled of LD/LP in AN */ 5380 if (phy->req_line_speed == SPEED_AUTO_NEG) 5381 bnx2x_update_adv_fc(phy, params, vars, gp_status); 5382 /* But set the flow-control result as the requested one */ 5383 vars->flow_ctrl = phy->req_flow_ctrl; 5384 } else if (phy->req_line_speed != SPEED_AUTO_NEG) 5385 vars->flow_ctrl = params->req_fc_auto_adv; 5386 else if ((gp_status & MDIO_AN_CL73_OR_37_COMPLETE) && 5387 (!(vars->phy_flags & PHY_SGMII_FLAG))) { 5388 if (bnx2x_direct_parallel_detect_used(phy, params)) { 5389 vars->flow_ctrl = params->req_fc_auto_adv; 5390 return; 5391 } 5392 bnx2x_update_adv_fc(phy, params, vars, gp_status); 5393 } 5394 DP(NETIF_MSG_LINK, "flow_ctrl 0x%x\n", vars->flow_ctrl); 5395 } 5396 5397 static void bnx2x_check_fallback_to_cl37(struct bnx2x_phy *phy, 5398 struct link_params *params) 5399 { 5400 struct bnx2x *bp = params->bp; 5401 u16 rx_status, ustat_val, cl37_fsm_received; 5402 DP(NETIF_MSG_LINK, "bnx2x_check_fallback_to_cl37\n"); 5403 /* Step 1: Make sure signal is detected */ 5404 CL22_RD_OVER_CL45(bp, phy, 5405 MDIO_REG_BANK_RX0, 5406 MDIO_RX0_RX_STATUS, 5407 &rx_status); 5408 if ((rx_status & MDIO_RX0_RX_STATUS_SIGDET) != 5409 (MDIO_RX0_RX_STATUS_SIGDET)) { 5410 DP(NETIF_MSG_LINK, "Signal is not detected. Restoring CL73." 5411 "rx_status(0x80b0) = 0x%x\n", rx_status); 5412 CL22_WR_OVER_CL45(bp, phy, 5413 MDIO_REG_BANK_CL73_IEEEB0, 5414 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, 5415 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN); 5416 return; 5417 } 5418 /* Step 2: Check CL73 state machine */ 5419 CL22_RD_OVER_CL45(bp, phy, 5420 MDIO_REG_BANK_CL73_USERB0, 5421 MDIO_CL73_USERB0_CL73_USTAT1, 5422 &ustat_val); 5423 if ((ustat_val & 5424 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK | 5425 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) != 5426 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK | 5427 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) { 5428 DP(NETIF_MSG_LINK, "CL73 state-machine is not stable. " 5429 "ustat_val(0x8371) = 0x%x\n", ustat_val); 5430 return; 5431 } 5432 /* Step 3: Check CL37 Message Pages received to indicate LP 5433 * supports only CL37 5434 */ 5435 CL22_RD_OVER_CL45(bp, phy, 5436 MDIO_REG_BANK_REMOTE_PHY, 5437 MDIO_REMOTE_PHY_MISC_RX_STATUS, 5438 &cl37_fsm_received); 5439 if ((cl37_fsm_received & 5440 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG | 5441 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) != 5442 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG | 5443 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) { 5444 DP(NETIF_MSG_LINK, "No CL37 FSM were received. " 5445 "misc_rx_status(0x8330) = 0x%x\n", 5446 cl37_fsm_received); 5447 return; 5448 } 5449 /* The combined cl37/cl73 fsm state information indicating that 5450 * we are connected to a device which does not support cl73, but 5451 * does support cl37 BAM. In this case we disable cl73 and 5452 * restart cl37 auto-neg 5453 */ 5454 5455 /* Disable CL73 */ 5456 CL22_WR_OVER_CL45(bp, phy, 5457 MDIO_REG_BANK_CL73_IEEEB0, 5458 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, 5459 0); 5460 /* Restart CL37 autoneg */ 5461 bnx2x_restart_autoneg(phy, params, 0); 5462 DP(NETIF_MSG_LINK, "Disabling CL73, and restarting CL37 autoneg\n"); 5463 } 5464 5465 static void bnx2x_xgxs_an_resolve(struct bnx2x_phy *phy, 5466 struct link_params *params, 5467 struct link_vars *vars, 5468 u32 gp_status) 5469 { 5470 if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE) 5471 vars->link_status |= 5472 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; 5473 5474 if (bnx2x_direct_parallel_detect_used(phy, params)) 5475 vars->link_status |= 5476 LINK_STATUS_PARALLEL_DETECTION_USED; 5477 } 5478 static int bnx2x_get_link_speed_duplex(struct bnx2x_phy *phy, 5479 struct link_params *params, 5480 struct link_vars *vars, 5481 u16 is_link_up, 5482 u16 speed_mask, 5483 u16 is_duplex) 5484 { 5485 struct bnx2x *bp = params->bp; 5486 if (phy->req_line_speed == SPEED_AUTO_NEG) 5487 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED; 5488 if (is_link_up) { 5489 DP(NETIF_MSG_LINK, "phy link up\n"); 5490 5491 vars->phy_link_up = 1; 5492 vars->link_status |= LINK_STATUS_LINK_UP; 5493 5494 switch (speed_mask) { 5495 case GP_STATUS_10M: 5496 vars->line_speed = SPEED_10; 5497 if (is_duplex == DUPLEX_FULL) 5498 vars->link_status |= LINK_10TFD; 5499 else 5500 vars->link_status |= LINK_10THD; 5501 break; 5502 5503 case GP_STATUS_100M: 5504 vars->line_speed = SPEED_100; 5505 if (is_duplex == DUPLEX_FULL) 5506 vars->link_status |= LINK_100TXFD; 5507 else 5508 vars->link_status |= LINK_100TXHD; 5509 break; 5510 5511 case GP_STATUS_1G: 5512 case GP_STATUS_1G_KX: 5513 vars->line_speed = SPEED_1000; 5514 if (is_duplex == DUPLEX_FULL) 5515 vars->link_status |= LINK_1000TFD; 5516 else 5517 vars->link_status |= LINK_1000THD; 5518 break; 5519 5520 case GP_STATUS_2_5G: 5521 vars->line_speed = SPEED_2500; 5522 if (is_duplex == DUPLEX_FULL) 5523 vars->link_status |= LINK_2500TFD; 5524 else 5525 vars->link_status |= LINK_2500THD; 5526 break; 5527 5528 case GP_STATUS_5G: 5529 case GP_STATUS_6G: 5530 DP(NETIF_MSG_LINK, 5531 "link speed unsupported gp_status 0x%x\n", 5532 speed_mask); 5533 return -EINVAL; 5534 5535 case GP_STATUS_10G_KX4: 5536 case GP_STATUS_10G_HIG: 5537 case GP_STATUS_10G_CX4: 5538 case GP_STATUS_10G_KR: 5539 case GP_STATUS_10G_SFI: 5540 case GP_STATUS_10G_XFI: 5541 vars->line_speed = SPEED_10000; 5542 vars->link_status |= LINK_10GTFD; 5543 break; 5544 case GP_STATUS_20G_DXGXS: 5545 case GP_STATUS_20G_KR2: 5546 vars->line_speed = SPEED_20000; 5547 vars->link_status |= LINK_20GTFD; 5548 break; 5549 default: 5550 DP(NETIF_MSG_LINK, 5551 "link speed unsupported gp_status 0x%x\n", 5552 speed_mask); 5553 return -EINVAL; 5554 } 5555 } else { /* link_down */ 5556 DP(NETIF_MSG_LINK, "phy link down\n"); 5557 5558 vars->phy_link_up = 0; 5559 5560 vars->duplex = DUPLEX_FULL; 5561 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; 5562 vars->mac_type = MAC_TYPE_NONE; 5563 } 5564 DP(NETIF_MSG_LINK, " phy_link_up %x line_speed %d\n", 5565 vars->phy_link_up, vars->line_speed); 5566 return 0; 5567 } 5568 5569 static int bnx2x_link_settings_status(struct bnx2x_phy *phy, 5570 struct link_params *params, 5571 struct link_vars *vars) 5572 { 5573 struct bnx2x *bp = params->bp; 5574 5575 u16 gp_status, duplex = DUPLEX_HALF, link_up = 0, speed_mask; 5576 int rc = 0; 5577 5578 /* Read gp_status */ 5579 CL22_RD_OVER_CL45(bp, phy, 5580 MDIO_REG_BANK_GP_STATUS, 5581 MDIO_GP_STATUS_TOP_AN_STATUS1, 5582 &gp_status); 5583 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS) 5584 duplex = DUPLEX_FULL; 5585 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) 5586 link_up = 1; 5587 speed_mask = gp_status & GP_STATUS_SPEED_MASK; 5588 DP(NETIF_MSG_LINK, "gp_status 0x%x, is_link_up %d, speed_mask 0x%x\n", 5589 gp_status, link_up, speed_mask); 5590 rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, speed_mask, 5591 duplex); 5592 if (rc == -EINVAL) 5593 return rc; 5594 5595 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) { 5596 if (SINGLE_MEDIA_DIRECT(params)) { 5597 vars->duplex = duplex; 5598 bnx2x_flow_ctrl_resolve(phy, params, vars, gp_status); 5599 if (phy->req_line_speed == SPEED_AUTO_NEG) 5600 bnx2x_xgxs_an_resolve(phy, params, vars, 5601 gp_status); 5602 } 5603 } else { /* Link_down */ 5604 if ((phy->req_line_speed == SPEED_AUTO_NEG) && 5605 SINGLE_MEDIA_DIRECT(params)) { 5606 /* Check signal is detected */ 5607 bnx2x_check_fallback_to_cl37(phy, params); 5608 } 5609 } 5610 5611 /* Read LP advertised speeds*/ 5612 if (SINGLE_MEDIA_DIRECT(params) && 5613 (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)) { 5614 u16 val; 5615 5616 CL22_RD_OVER_CL45(bp, phy, MDIO_REG_BANK_CL73_IEEEB1, 5617 MDIO_CL73_IEEEB1_AN_LP_ADV2, &val); 5618 5619 if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX) 5620 vars->link_status |= 5621 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; 5622 if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 | 5623 MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR)) 5624 vars->link_status |= 5625 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; 5626 5627 CL22_RD_OVER_CL45(bp, phy, MDIO_REG_BANK_OVER_1G, 5628 MDIO_OVER_1G_LP_UP1, &val); 5629 5630 if (val & MDIO_OVER_1G_UP1_2_5G) 5631 vars->link_status |= 5632 LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE; 5633 if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH)) 5634 vars->link_status |= 5635 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; 5636 } 5637 5638 DP(NETIF_MSG_LINK, "duplex %x flow_ctrl 0x%x link_status 0x%x\n", 5639 vars->duplex, vars->flow_ctrl, vars->link_status); 5640 return rc; 5641 } 5642 5643 static int bnx2x_warpcore_read_status(struct bnx2x_phy *phy, 5644 struct link_params *params, 5645 struct link_vars *vars) 5646 { 5647 struct bnx2x *bp = params->bp; 5648 u8 lane; 5649 u16 gp_status1, gp_speed, link_up, duplex = DUPLEX_FULL; 5650 int rc = 0; 5651 lane = bnx2x_get_warpcore_lane(phy, params); 5652 /* Read gp_status */ 5653 if ((params->loopback_mode) && 5654 (phy->flags & FLAGS_WC_DUAL_MODE)) { 5655 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 5656 MDIO_WC_REG_DIGITAL5_LINK_STATUS, &link_up); 5657 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 5658 MDIO_WC_REG_DIGITAL5_LINK_STATUS, &link_up); 5659 link_up &= 0x1; 5660 } else if ((phy->req_line_speed > SPEED_10000) && 5661 (phy->supported & SUPPORTED_20000baseMLD2_Full)) { 5662 u16 temp_link_up; 5663 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 5664 1, &temp_link_up); 5665 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 5666 1, &link_up); 5667 DP(NETIF_MSG_LINK, "PCS RX link status = 0x%x-->0x%x\n", 5668 temp_link_up, link_up); 5669 link_up &= (1<<2); 5670 if (link_up) 5671 bnx2x_ext_phy_resolve_fc(phy, params, vars); 5672 } else { 5673 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 5674 MDIO_WC_REG_GP2_STATUS_GP_2_1, 5675 &gp_status1); 5676 DP(NETIF_MSG_LINK, "0x81d1 = 0x%x\n", gp_status1); 5677 /* Check for either KR, 1G, or AN up. */ 5678 link_up = ((gp_status1 >> 8) | 5679 (gp_status1 >> 12) | 5680 (gp_status1)) & 5681 (1 << lane); 5682 if (phy->supported & SUPPORTED_20000baseKR2_Full) { 5683 u16 an_link; 5684 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, 5685 MDIO_AN_REG_STATUS, &an_link); 5686 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, 5687 MDIO_AN_REG_STATUS, &an_link); 5688 link_up |= (an_link & (1<<2)); 5689 } 5690 if (link_up && SINGLE_MEDIA_DIRECT(params)) { 5691 u16 pd, gp_status4; 5692 if (phy->req_line_speed == SPEED_AUTO_NEG) { 5693 /* Check Autoneg complete */ 5694 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 5695 MDIO_WC_REG_GP2_STATUS_GP_2_4, 5696 &gp_status4); 5697 if (gp_status4 & ((1<<12)<<lane)) 5698 vars->link_status |= 5699 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; 5700 5701 /* Check parallel detect used */ 5702 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 5703 MDIO_WC_REG_PAR_DET_10G_STATUS, 5704 &pd); 5705 if (pd & (1<<15)) 5706 vars->link_status |= 5707 LINK_STATUS_PARALLEL_DETECTION_USED; 5708 } 5709 bnx2x_ext_phy_resolve_fc(phy, params, vars); 5710 vars->duplex = duplex; 5711 } 5712 } 5713 5714 if ((vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) && 5715 SINGLE_MEDIA_DIRECT(params)) { 5716 u16 val; 5717 5718 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, 5719 MDIO_AN_REG_LP_AUTO_NEG2, &val); 5720 5721 if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX) 5722 vars->link_status |= 5723 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; 5724 if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 | 5725 MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR)) 5726 vars->link_status |= 5727 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; 5728 5729 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 5730 MDIO_WC_REG_DIGITAL3_LP_UP1, &val); 5731 5732 if (val & MDIO_OVER_1G_UP1_2_5G) 5733 vars->link_status |= 5734 LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE; 5735 if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH)) 5736 vars->link_status |= 5737 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; 5738 5739 } 5740 5741 5742 if (lane < 2) { 5743 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 5744 MDIO_WC_REG_GP2_STATUS_GP_2_2, &gp_speed); 5745 } else { 5746 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 5747 MDIO_WC_REG_GP2_STATUS_GP_2_3, &gp_speed); 5748 } 5749 DP(NETIF_MSG_LINK, "lane %d gp_speed 0x%x\n", lane, gp_speed); 5750 5751 if ((lane & 1) == 0) 5752 gp_speed <<= 8; 5753 gp_speed &= 0x3f00; 5754 link_up = !!link_up; 5755 5756 rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, gp_speed, 5757 duplex); 5758 5759 /* In case of KR link down, start up the recovering procedure */ 5760 if ((!link_up) && (phy->media_type == ETH_PHY_KR) && 5761 (!(phy->flags & FLAGS_WC_DUAL_MODE))) 5762 vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY; 5763 5764 DP(NETIF_MSG_LINK, "duplex %x flow_ctrl 0x%x link_status 0x%x\n", 5765 vars->duplex, vars->flow_ctrl, vars->link_status); 5766 return rc; 5767 } 5768 static void bnx2x_set_gmii_tx_driver(struct link_params *params) 5769 { 5770 struct bnx2x *bp = params->bp; 5771 struct bnx2x_phy *phy = ¶ms->phy[INT_PHY]; 5772 u16 lp_up2; 5773 u16 tx_driver; 5774 u16 bank; 5775 5776 /* Read precomp */ 5777 CL22_RD_OVER_CL45(bp, phy, 5778 MDIO_REG_BANK_OVER_1G, 5779 MDIO_OVER_1G_LP_UP2, &lp_up2); 5780 5781 /* Bits [10:7] at lp_up2, positioned at [15:12] */ 5782 lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >> 5783 MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) << 5784 MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT); 5785 5786 if (lp_up2 == 0) 5787 return; 5788 5789 for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3; 5790 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) { 5791 CL22_RD_OVER_CL45(bp, phy, 5792 bank, 5793 MDIO_TX0_TX_DRIVER, &tx_driver); 5794 5795 /* Replace tx_driver bits [15:12] */ 5796 if (lp_up2 != 5797 (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) { 5798 tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK; 5799 tx_driver |= lp_up2; 5800 CL22_WR_OVER_CL45(bp, phy, 5801 bank, 5802 MDIO_TX0_TX_DRIVER, tx_driver); 5803 } 5804 } 5805 } 5806 5807 static int bnx2x_emac_program(struct link_params *params, 5808 struct link_vars *vars) 5809 { 5810 struct bnx2x *bp = params->bp; 5811 u8 port = params->port; 5812 u16 mode = 0; 5813 5814 DP(NETIF_MSG_LINK, "setting link speed & duplex\n"); 5815 bnx2x_bits_dis(bp, GRCBASE_EMAC0 + port*0x400 + 5816 EMAC_REG_EMAC_MODE, 5817 (EMAC_MODE_25G_MODE | 5818 EMAC_MODE_PORT_MII_10M | 5819 EMAC_MODE_HALF_DUPLEX)); 5820 switch (vars->line_speed) { 5821 case SPEED_10: 5822 mode |= EMAC_MODE_PORT_MII_10M; 5823 break; 5824 5825 case SPEED_100: 5826 mode |= EMAC_MODE_PORT_MII; 5827 break; 5828 5829 case SPEED_1000: 5830 mode |= EMAC_MODE_PORT_GMII; 5831 break; 5832 5833 case SPEED_2500: 5834 mode |= (EMAC_MODE_25G_MODE | EMAC_MODE_PORT_GMII); 5835 break; 5836 5837 default: 5838 /* 10G not valid for EMAC */ 5839 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n", 5840 vars->line_speed); 5841 return -EINVAL; 5842 } 5843 5844 if (vars->duplex == DUPLEX_HALF) 5845 mode |= EMAC_MODE_HALF_DUPLEX; 5846 bnx2x_bits_en(bp, 5847 GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE, 5848 mode); 5849 5850 bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed); 5851 return 0; 5852 } 5853 5854 static void bnx2x_set_preemphasis(struct bnx2x_phy *phy, 5855 struct link_params *params) 5856 { 5857 5858 u16 bank, i = 0; 5859 struct bnx2x *bp = params->bp; 5860 5861 for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3; 5862 bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0), i++) { 5863 CL22_WR_OVER_CL45(bp, phy, 5864 bank, 5865 MDIO_RX0_RX_EQ_BOOST, 5866 phy->rx_preemphasis[i]); 5867 } 5868 5869 for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3; 5870 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) { 5871 CL22_WR_OVER_CL45(bp, phy, 5872 bank, 5873 MDIO_TX0_TX_DRIVER, 5874 phy->tx_preemphasis[i]); 5875 } 5876 } 5877 5878 static void bnx2x_xgxs_config_init(struct bnx2x_phy *phy, 5879 struct link_params *params, 5880 struct link_vars *vars) 5881 { 5882 struct bnx2x *bp = params->bp; 5883 u8 enable_cl73 = (SINGLE_MEDIA_DIRECT(params) || 5884 (params->loopback_mode == LOOPBACK_XGXS)); 5885 if (!(vars->phy_flags & PHY_SGMII_FLAG)) { 5886 if (SINGLE_MEDIA_DIRECT(params) && 5887 (params->feature_config_flags & 5888 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) 5889 bnx2x_set_preemphasis(phy, params); 5890 5891 /* Forced speed requested? */ 5892 if (vars->line_speed != SPEED_AUTO_NEG || 5893 (SINGLE_MEDIA_DIRECT(params) && 5894 params->loopback_mode == LOOPBACK_EXT)) { 5895 DP(NETIF_MSG_LINK, "not SGMII, no AN\n"); 5896 5897 /* Disable autoneg */ 5898 bnx2x_set_autoneg(phy, params, vars, 0); 5899 5900 /* Program speed and duplex */ 5901 bnx2x_program_serdes(phy, params, vars); 5902 5903 } else { /* AN_mode */ 5904 DP(NETIF_MSG_LINK, "not SGMII, AN\n"); 5905 5906 /* AN enabled */ 5907 bnx2x_set_brcm_cl37_advertisement(phy, params); 5908 5909 /* Program duplex & pause advertisement (for aneg) */ 5910 bnx2x_set_ieee_aneg_advertisement(phy, params, 5911 vars->ieee_fc); 5912 5913 /* Enable autoneg */ 5914 bnx2x_set_autoneg(phy, params, vars, enable_cl73); 5915 5916 /* Enable and restart AN */ 5917 bnx2x_restart_autoneg(phy, params, enable_cl73); 5918 } 5919 5920 } else { /* SGMII mode */ 5921 DP(NETIF_MSG_LINK, "SGMII\n"); 5922 5923 bnx2x_initialize_sgmii_process(phy, params, vars); 5924 } 5925 } 5926 5927 static int bnx2x_prepare_xgxs(struct bnx2x_phy *phy, 5928 struct link_params *params, 5929 struct link_vars *vars) 5930 { 5931 int rc; 5932 vars->phy_flags |= PHY_XGXS_FLAG; 5933 if ((phy->req_line_speed && 5934 ((phy->req_line_speed == SPEED_100) || 5935 (phy->req_line_speed == SPEED_10))) || 5936 (!phy->req_line_speed && 5937 (phy->speed_cap_mask >= 5938 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) && 5939 (phy->speed_cap_mask < 5940 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) || 5941 (phy->type == PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD)) 5942 vars->phy_flags |= PHY_SGMII_FLAG; 5943 else 5944 vars->phy_flags &= ~PHY_SGMII_FLAG; 5945 5946 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); 5947 bnx2x_set_aer_mmd(params, phy); 5948 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) 5949 bnx2x_set_master_ln(params, phy); 5950 5951 rc = bnx2x_reset_unicore(params, phy, 0); 5952 /* Reset the SerDes and wait for reset bit return low */ 5953 if (rc) 5954 return rc; 5955 5956 bnx2x_set_aer_mmd(params, phy); 5957 /* Setting the masterLn_def again after the reset */ 5958 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) { 5959 bnx2x_set_master_ln(params, phy); 5960 bnx2x_set_swap_lanes(params, phy); 5961 } 5962 5963 return rc; 5964 } 5965 5966 static u16 bnx2x_wait_reset_complete(struct bnx2x *bp, 5967 struct bnx2x_phy *phy, 5968 struct link_params *params) 5969 { 5970 u16 cnt, ctrl; 5971 /* Wait for soft reset to get cleared up to 1 sec */ 5972 for (cnt = 0; cnt < 1000; cnt++) { 5973 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) 5974 bnx2x_cl22_read(bp, phy, 5975 MDIO_PMA_REG_CTRL, &ctrl); 5976 else 5977 bnx2x_cl45_read(bp, phy, 5978 MDIO_PMA_DEVAD, 5979 MDIO_PMA_REG_CTRL, &ctrl); 5980 if (!(ctrl & (1<<15))) 5981 break; 5982 usleep_range(1000, 2000); 5983 } 5984 5985 if (cnt == 1000) 5986 netdev_err(bp->dev, "Warning: PHY was not initialized," 5987 " Port %d\n", 5988 params->port); 5989 DP(NETIF_MSG_LINK, "control reg 0x%x (after %d ms)\n", ctrl, cnt); 5990 return cnt; 5991 } 5992 5993 static void bnx2x_link_int_enable(struct link_params *params) 5994 { 5995 u8 port = params->port; 5996 u32 mask; 5997 struct bnx2x *bp = params->bp; 5998 5999 /* Setting the status to report on link up for either XGXS or SerDes */ 6000 if (CHIP_IS_E3(bp)) { 6001 mask = NIG_MASK_XGXS0_LINK_STATUS; 6002 if (!(SINGLE_MEDIA_DIRECT(params))) 6003 mask |= NIG_MASK_MI_INT; 6004 } else if (params->switch_cfg == SWITCH_CFG_10G) { 6005 mask = (NIG_MASK_XGXS0_LINK10G | 6006 NIG_MASK_XGXS0_LINK_STATUS); 6007 DP(NETIF_MSG_LINK, "enabled XGXS interrupt\n"); 6008 if (!(SINGLE_MEDIA_DIRECT(params)) && 6009 params->phy[INT_PHY].type != 6010 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) { 6011 mask |= NIG_MASK_MI_INT; 6012 DP(NETIF_MSG_LINK, "enabled external phy int\n"); 6013 } 6014 6015 } else { /* SerDes */ 6016 mask = NIG_MASK_SERDES0_LINK_STATUS; 6017 DP(NETIF_MSG_LINK, "enabled SerDes interrupt\n"); 6018 if (!(SINGLE_MEDIA_DIRECT(params)) && 6019 params->phy[INT_PHY].type != 6020 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN) { 6021 mask |= NIG_MASK_MI_INT; 6022 DP(NETIF_MSG_LINK, "enabled external phy int\n"); 6023 } 6024 } 6025 bnx2x_bits_en(bp, 6026 NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 6027 mask); 6028 6029 DP(NETIF_MSG_LINK, "port %x, is_xgxs %x, int_status 0x%x\n", port, 6030 (params->switch_cfg == SWITCH_CFG_10G), 6031 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4)); 6032 DP(NETIF_MSG_LINK, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x\n", 6033 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4), 6034 REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18), 6035 REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS+port*0x3c)); 6036 DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n", 6037 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68), 6038 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68)); 6039 } 6040 6041 static void bnx2x_rearm_latch_signal(struct bnx2x *bp, u8 port, 6042 u8 exp_mi_int) 6043 { 6044 u32 latch_status = 0; 6045 6046 /* Disable the MI INT ( external phy int ) by writing 1 to the 6047 * status register. Link down indication is high-active-signal, 6048 * so in this case we need to write the status to clear the XOR 6049 */ 6050 /* Read Latched signals */ 6051 latch_status = REG_RD(bp, 6052 NIG_REG_LATCH_STATUS_0 + port*8); 6053 DP(NETIF_MSG_LINK, "latch_status = 0x%x\n", latch_status); 6054 /* Handle only those with latched-signal=up.*/ 6055 if (exp_mi_int) 6056 bnx2x_bits_en(bp, 6057 NIG_REG_STATUS_INTERRUPT_PORT0 6058 + port*4, 6059 NIG_STATUS_EMAC0_MI_INT); 6060 else 6061 bnx2x_bits_dis(bp, 6062 NIG_REG_STATUS_INTERRUPT_PORT0 6063 + port*4, 6064 NIG_STATUS_EMAC0_MI_INT); 6065 6066 if (latch_status & 1) { 6067 6068 /* For all latched-signal=up : Re-Arm Latch signals */ 6069 REG_WR(bp, NIG_REG_LATCH_STATUS_0 + port*8, 6070 (latch_status & 0xfffe) | (latch_status & 1)); 6071 } 6072 /* For all latched-signal=up,Write original_signal to status */ 6073 } 6074 6075 static void bnx2x_link_int_ack(struct link_params *params, 6076 struct link_vars *vars, u8 is_10g_plus) 6077 { 6078 struct bnx2x *bp = params->bp; 6079 u8 port = params->port; 6080 u32 mask; 6081 /* First reset all status we assume only one line will be 6082 * change at a time 6083 */ 6084 bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4, 6085 (NIG_STATUS_XGXS0_LINK10G | 6086 NIG_STATUS_XGXS0_LINK_STATUS | 6087 NIG_STATUS_SERDES0_LINK_STATUS)); 6088 if (vars->phy_link_up) { 6089 if (USES_WARPCORE(bp)) 6090 mask = NIG_STATUS_XGXS0_LINK_STATUS; 6091 else { 6092 if (is_10g_plus) 6093 mask = NIG_STATUS_XGXS0_LINK10G; 6094 else if (params->switch_cfg == SWITCH_CFG_10G) { 6095 /* Disable the link interrupt by writing 1 to 6096 * the relevant lane in the status register 6097 */ 6098 u32 ser_lane = 6099 ((params->lane_config & 6100 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >> 6101 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT); 6102 mask = ((1 << ser_lane) << 6103 NIG_STATUS_XGXS0_LINK_STATUS_SIZE); 6104 } else 6105 mask = NIG_STATUS_SERDES0_LINK_STATUS; 6106 } 6107 DP(NETIF_MSG_LINK, "Ack link up interrupt with mask 0x%x\n", 6108 mask); 6109 bnx2x_bits_en(bp, 6110 NIG_REG_STATUS_INTERRUPT_PORT0 + port*4, 6111 mask); 6112 } 6113 } 6114 6115 static int bnx2x_format_ver(u32 num, u8 *str, u16 *len) 6116 { 6117 u8 *str_ptr = str; 6118 u32 mask = 0xf0000000; 6119 u8 shift = 8*4; 6120 u8 digit; 6121 u8 remove_leading_zeros = 1; 6122 if (*len < 10) { 6123 /* Need more than 10chars for this format */ 6124 *str_ptr = '\0'; 6125 (*len)--; 6126 return -EINVAL; 6127 } 6128 while (shift > 0) { 6129 6130 shift -= 4; 6131 digit = ((num & mask) >> shift); 6132 if (digit == 0 && remove_leading_zeros) { 6133 mask = mask >> 4; 6134 continue; 6135 } else if (digit < 0xa) 6136 *str_ptr = digit + '0'; 6137 else 6138 *str_ptr = digit - 0xa + 'a'; 6139 remove_leading_zeros = 0; 6140 str_ptr++; 6141 (*len)--; 6142 mask = mask >> 4; 6143 if (shift == 4*4) { 6144 *str_ptr = '.'; 6145 str_ptr++; 6146 (*len)--; 6147 remove_leading_zeros = 1; 6148 } 6149 } 6150 return 0; 6151 } 6152 6153 6154 static int bnx2x_null_format_ver(u32 spirom_ver, u8 *str, u16 *len) 6155 { 6156 str[0] = '\0'; 6157 (*len)--; 6158 return 0; 6159 } 6160 6161 int bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 *version, 6162 u16 len) 6163 { 6164 struct bnx2x *bp; 6165 u32 spirom_ver = 0; 6166 int status = 0; 6167 u8 *ver_p = version; 6168 u16 remain_len = len; 6169 if (version == NULL || params == NULL) 6170 return -EINVAL; 6171 bp = params->bp; 6172 6173 /* Extract first external phy*/ 6174 version[0] = '\0'; 6175 spirom_ver = REG_RD(bp, params->phy[EXT_PHY1].ver_addr); 6176 6177 if (params->phy[EXT_PHY1].format_fw_ver) { 6178 status |= params->phy[EXT_PHY1].format_fw_ver(spirom_ver, 6179 ver_p, 6180 &remain_len); 6181 ver_p += (len - remain_len); 6182 } 6183 if ((params->num_phys == MAX_PHYS) && 6184 (params->phy[EXT_PHY2].ver_addr != 0)) { 6185 spirom_ver = REG_RD(bp, params->phy[EXT_PHY2].ver_addr); 6186 if (params->phy[EXT_PHY2].format_fw_ver) { 6187 *ver_p = '/'; 6188 ver_p++; 6189 remain_len--; 6190 status |= params->phy[EXT_PHY2].format_fw_ver( 6191 spirom_ver, 6192 ver_p, 6193 &remain_len); 6194 ver_p = version + (len - remain_len); 6195 } 6196 } 6197 *ver_p = '\0'; 6198 return status; 6199 } 6200 6201 static void bnx2x_set_xgxs_loopback(struct bnx2x_phy *phy, 6202 struct link_params *params) 6203 { 6204 u8 port = params->port; 6205 struct bnx2x *bp = params->bp; 6206 6207 if (phy->req_line_speed != SPEED_1000) { 6208 u32 md_devad = 0; 6209 6210 DP(NETIF_MSG_LINK, "XGXS 10G loopback enable\n"); 6211 6212 if (!CHIP_IS_E3(bp)) { 6213 /* Change the uni_phy_addr in the nig */ 6214 md_devad = REG_RD(bp, (NIG_REG_XGXS0_CTRL_MD_DEVAD + 6215 port*0x18)); 6216 6217 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, 6218 0x5); 6219 } 6220 6221 bnx2x_cl45_write(bp, phy, 6222 5, 6223 (MDIO_REG_BANK_AER_BLOCK + 6224 (MDIO_AER_BLOCK_AER_REG & 0xf)), 6225 0x2800); 6226 6227 bnx2x_cl45_write(bp, phy, 6228 5, 6229 (MDIO_REG_BANK_CL73_IEEEB0 + 6230 (MDIO_CL73_IEEEB0_CL73_AN_CONTROL & 0xf)), 6231 0x6041); 6232 msleep(200); 6233 /* Set aer mmd back */ 6234 bnx2x_set_aer_mmd(params, phy); 6235 6236 if (!CHIP_IS_E3(bp)) { 6237 /* And md_devad */ 6238 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, 6239 md_devad); 6240 } 6241 } else { 6242 u16 mii_ctrl; 6243 DP(NETIF_MSG_LINK, "XGXS 1G loopback enable\n"); 6244 bnx2x_cl45_read(bp, phy, 5, 6245 (MDIO_REG_BANK_COMBO_IEEE0 + 6246 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)), 6247 &mii_ctrl); 6248 bnx2x_cl45_write(bp, phy, 5, 6249 (MDIO_REG_BANK_COMBO_IEEE0 + 6250 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)), 6251 mii_ctrl | 6252 MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK); 6253 } 6254 } 6255 6256 int bnx2x_set_led(struct link_params *params, 6257 struct link_vars *vars, u8 mode, u32 speed) 6258 { 6259 u8 port = params->port; 6260 u16 hw_led_mode = params->hw_led_mode; 6261 int rc = 0; 6262 u8 phy_idx; 6263 u32 tmp; 6264 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; 6265 struct bnx2x *bp = params->bp; 6266 DP(NETIF_MSG_LINK, "bnx2x_set_led: port %x, mode %d\n", port, mode); 6267 DP(NETIF_MSG_LINK, "speed 0x%x, hw_led_mode 0x%x\n", 6268 speed, hw_led_mode); 6269 /* In case */ 6270 for (phy_idx = EXT_PHY1; phy_idx < MAX_PHYS; phy_idx++) { 6271 if (params->phy[phy_idx].set_link_led) { 6272 params->phy[phy_idx].set_link_led( 6273 ¶ms->phy[phy_idx], params, mode); 6274 } 6275 } 6276 6277 switch (mode) { 6278 case LED_MODE_FRONT_PANEL_OFF: 6279 case LED_MODE_OFF: 6280 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 0); 6281 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 6282 SHARED_HW_CFG_LED_MAC1); 6283 6284 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED); 6285 if (params->phy[EXT_PHY1].type == 6286 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) 6287 tmp &= ~(EMAC_LED_1000MB_OVERRIDE | 6288 EMAC_LED_100MB_OVERRIDE | 6289 EMAC_LED_10MB_OVERRIDE); 6290 else 6291 tmp |= EMAC_LED_OVERRIDE; 6292 6293 EMAC_WR(bp, EMAC_REG_EMAC_LED, tmp); 6294 break; 6295 6296 case LED_MODE_OPER: 6297 /* For all other phys, OPER mode is same as ON, so in case 6298 * link is down, do nothing 6299 */ 6300 if (!vars->link_up) 6301 break; 6302 case LED_MODE_ON: 6303 if (((params->phy[EXT_PHY1].type == 6304 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) || 6305 (params->phy[EXT_PHY1].type == 6306 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722)) && 6307 CHIP_IS_E2(bp) && params->num_phys == 2) { 6308 /* This is a work-around for E2+8727 Configurations */ 6309 if (mode == LED_MODE_ON || 6310 speed == SPEED_10000){ 6311 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0); 6312 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1); 6313 6314 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED); 6315 EMAC_WR(bp, EMAC_REG_EMAC_LED, 6316 (tmp | EMAC_LED_OVERRIDE)); 6317 /* Return here without enabling traffic 6318 * LED blink and setting rate in ON mode. 6319 * In oper mode, enabling LED blink 6320 * and setting rate is needed. 6321 */ 6322 if (mode == LED_MODE_ON) 6323 return rc; 6324 } 6325 } else if (SINGLE_MEDIA_DIRECT(params)) { 6326 /* This is a work-around for HW issue found when link 6327 * is up in CL73 6328 */ 6329 if ((!CHIP_IS_E3(bp)) || 6330 (CHIP_IS_E3(bp) && 6331 mode == LED_MODE_ON)) 6332 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1); 6333 6334 if (CHIP_IS_E1x(bp) || 6335 CHIP_IS_E2(bp) || 6336 (mode == LED_MODE_ON)) 6337 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0); 6338 else 6339 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 6340 hw_led_mode); 6341 } else if ((params->phy[EXT_PHY1].type == 6342 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) && 6343 (mode == LED_MODE_ON)) { 6344 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0); 6345 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED); 6346 EMAC_WR(bp, EMAC_REG_EMAC_LED, tmp | 6347 EMAC_LED_OVERRIDE | EMAC_LED_1000MB_OVERRIDE); 6348 /* Break here; otherwise, it'll disable the 6349 * intended override. 6350 */ 6351 break; 6352 } else { 6353 u32 nig_led_mode = ((params->hw_led_mode << 6354 SHARED_HW_CFG_LED_MODE_SHIFT) == 6355 SHARED_HW_CFG_LED_EXTPHY2) ? 6356 (SHARED_HW_CFG_LED_PHY1 >> 6357 SHARED_HW_CFG_LED_MODE_SHIFT) : hw_led_mode; 6358 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 6359 nig_led_mode); 6360 } 6361 6362 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 0); 6363 /* Set blinking rate to ~15.9Hz */ 6364 if (CHIP_IS_E3(bp)) 6365 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4, 6366 LED_BLINK_RATE_VAL_E3); 6367 else 6368 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4, 6369 LED_BLINK_RATE_VAL_E1X_E2); 6370 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 + 6371 port*4, 1); 6372 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED); 6373 EMAC_WR(bp, EMAC_REG_EMAC_LED, 6374 (tmp & (~EMAC_LED_OVERRIDE))); 6375 6376 if (CHIP_IS_E1(bp) && 6377 ((speed == SPEED_2500) || 6378 (speed == SPEED_1000) || 6379 (speed == SPEED_100) || 6380 (speed == SPEED_10))) { 6381 /* For speeds less than 10G LED scheme is different */ 6382 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 6383 + port*4, 1); 6384 REG_WR(bp, NIG_REG_LED_CONTROL_TRAFFIC_P0 + 6385 port*4, 0); 6386 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 + 6387 port*4, 1); 6388 } 6389 break; 6390 6391 default: 6392 rc = -EINVAL; 6393 DP(NETIF_MSG_LINK, "bnx2x_set_led: Invalid led mode %d\n", 6394 mode); 6395 break; 6396 } 6397 return rc; 6398 6399 } 6400 6401 /* This function comes to reflect the actual link state read DIRECTLY from the 6402 * HW 6403 */ 6404 int bnx2x_test_link(struct link_params *params, struct link_vars *vars, 6405 u8 is_serdes) 6406 { 6407 struct bnx2x *bp = params->bp; 6408 u16 gp_status = 0, phy_index = 0; 6409 u8 ext_phy_link_up = 0, serdes_phy_type; 6410 struct link_vars temp_vars; 6411 struct bnx2x_phy *int_phy = ¶ms->phy[INT_PHY]; 6412 6413 if (CHIP_IS_E3(bp)) { 6414 u16 link_up; 6415 if (params->req_line_speed[LINK_CONFIG_IDX(INT_PHY)] 6416 > SPEED_10000) { 6417 /* Check 20G link */ 6418 bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD, 6419 1, &link_up); 6420 bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD, 6421 1, &link_up); 6422 link_up &= (1<<2); 6423 } else { 6424 /* Check 10G link and below*/ 6425 u8 lane = bnx2x_get_warpcore_lane(int_phy, params); 6426 bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD, 6427 MDIO_WC_REG_GP2_STATUS_GP_2_1, 6428 &gp_status); 6429 gp_status = ((gp_status >> 8) & 0xf) | 6430 ((gp_status >> 12) & 0xf); 6431 link_up = gp_status & (1 << lane); 6432 } 6433 if (!link_up) 6434 return -ESRCH; 6435 } else { 6436 CL22_RD_OVER_CL45(bp, int_phy, 6437 MDIO_REG_BANK_GP_STATUS, 6438 MDIO_GP_STATUS_TOP_AN_STATUS1, 6439 &gp_status); 6440 /* Link is up only if both local phy and external phy are up */ 6441 if (!(gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS)) 6442 return -ESRCH; 6443 } 6444 /* In XGXS loopback mode, do not check external PHY */ 6445 if (params->loopback_mode == LOOPBACK_XGXS) 6446 return 0; 6447 6448 switch (params->num_phys) { 6449 case 1: 6450 /* No external PHY */ 6451 return 0; 6452 case 2: 6453 ext_phy_link_up = params->phy[EXT_PHY1].read_status( 6454 ¶ms->phy[EXT_PHY1], 6455 params, &temp_vars); 6456 break; 6457 case 3: /* Dual Media */ 6458 for (phy_index = EXT_PHY1; phy_index < params->num_phys; 6459 phy_index++) { 6460 serdes_phy_type = ((params->phy[phy_index].media_type == 6461 ETH_PHY_SFPP_10G_FIBER) || 6462 (params->phy[phy_index].media_type == 6463 ETH_PHY_SFP_1G_FIBER) || 6464 (params->phy[phy_index].media_type == 6465 ETH_PHY_XFP_FIBER) || 6466 (params->phy[phy_index].media_type == 6467 ETH_PHY_DA_TWINAX)); 6468 6469 if (is_serdes != serdes_phy_type) 6470 continue; 6471 if (params->phy[phy_index].read_status) { 6472 ext_phy_link_up |= 6473 params->phy[phy_index].read_status( 6474 ¶ms->phy[phy_index], 6475 params, &temp_vars); 6476 } 6477 } 6478 break; 6479 } 6480 if (ext_phy_link_up) 6481 return 0; 6482 return -ESRCH; 6483 } 6484 6485 static int bnx2x_link_initialize(struct link_params *params, 6486 struct link_vars *vars) 6487 { 6488 u8 phy_index, non_ext_phy; 6489 struct bnx2x *bp = params->bp; 6490 /* In case of external phy existence, the line speed would be the 6491 * line speed linked up by the external phy. In case it is direct 6492 * only, then the line_speed during initialization will be 6493 * equal to the req_line_speed 6494 */ 6495 vars->line_speed = params->phy[INT_PHY].req_line_speed; 6496 6497 /* Initialize the internal phy in case this is a direct board 6498 * (no external phys), or this board has external phy which requires 6499 * to first. 6500 */ 6501 if (!USES_WARPCORE(bp)) 6502 bnx2x_prepare_xgxs(¶ms->phy[INT_PHY], params, vars); 6503 /* init ext phy and enable link state int */ 6504 non_ext_phy = (SINGLE_MEDIA_DIRECT(params) || 6505 (params->loopback_mode == LOOPBACK_XGXS)); 6506 6507 if (non_ext_phy || 6508 (params->phy[EXT_PHY1].flags & FLAGS_INIT_XGXS_FIRST) || 6509 (params->loopback_mode == LOOPBACK_EXT_PHY)) { 6510 struct bnx2x_phy *phy = ¶ms->phy[INT_PHY]; 6511 if (vars->line_speed == SPEED_AUTO_NEG && 6512 (CHIP_IS_E1x(bp) || 6513 CHIP_IS_E2(bp))) 6514 bnx2x_set_parallel_detection(phy, params); 6515 if (params->phy[INT_PHY].config_init) 6516 params->phy[INT_PHY].config_init(phy, params, vars); 6517 } 6518 6519 /* Re-read this value in case it was changed inside config_init due to 6520 * limitations of optic module 6521 */ 6522 vars->line_speed = params->phy[INT_PHY].req_line_speed; 6523 6524 /* Init external phy*/ 6525 if (non_ext_phy) { 6526 if (params->phy[INT_PHY].supported & 6527 SUPPORTED_FIBRE) 6528 vars->link_status |= LINK_STATUS_SERDES_LINK; 6529 } else { 6530 for (phy_index = EXT_PHY1; phy_index < params->num_phys; 6531 phy_index++) { 6532 /* No need to initialize second phy in case of first 6533 * phy only selection. In case of second phy, we do 6534 * need to initialize the first phy, since they are 6535 * connected. 6536 */ 6537 if (params->phy[phy_index].supported & 6538 SUPPORTED_FIBRE) 6539 vars->link_status |= LINK_STATUS_SERDES_LINK; 6540 6541 if (phy_index == EXT_PHY2 && 6542 (bnx2x_phy_selection(params) == 6543 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY)) { 6544 DP(NETIF_MSG_LINK, 6545 "Not initializing second phy\n"); 6546 continue; 6547 } 6548 params->phy[phy_index].config_init( 6549 ¶ms->phy[phy_index], 6550 params, vars); 6551 } 6552 } 6553 /* Reset the interrupt indication after phy was initialized */ 6554 bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + 6555 params->port*4, 6556 (NIG_STATUS_XGXS0_LINK10G | 6557 NIG_STATUS_XGXS0_LINK_STATUS | 6558 NIG_STATUS_SERDES0_LINK_STATUS | 6559 NIG_MASK_MI_INT)); 6560 return 0; 6561 } 6562 6563 static void bnx2x_int_link_reset(struct bnx2x_phy *phy, 6564 struct link_params *params) 6565 { 6566 /* Reset the SerDes/XGXS */ 6567 REG_WR(params->bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, 6568 (0x1ff << (params->port*16))); 6569 } 6570 6571 static void bnx2x_common_ext_link_reset(struct bnx2x_phy *phy, 6572 struct link_params *params) 6573 { 6574 struct bnx2x *bp = params->bp; 6575 u8 gpio_port; 6576 /* HW reset */ 6577 if (CHIP_IS_E2(bp)) 6578 gpio_port = BP_PATH(bp); 6579 else 6580 gpio_port = params->port; 6581 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, 6582 MISC_REGISTERS_GPIO_OUTPUT_LOW, 6583 gpio_port); 6584 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 6585 MISC_REGISTERS_GPIO_OUTPUT_LOW, 6586 gpio_port); 6587 DP(NETIF_MSG_LINK, "reset external PHY\n"); 6588 } 6589 6590 static int bnx2x_update_link_down(struct link_params *params, 6591 struct link_vars *vars) 6592 { 6593 struct bnx2x *bp = params->bp; 6594 u8 port = params->port; 6595 6596 DP(NETIF_MSG_LINK, "Port %x: Link is down\n", port); 6597 bnx2x_set_led(params, vars, LED_MODE_OFF, 0); 6598 vars->phy_flags &= ~PHY_PHYSICAL_LINK_FLAG; 6599 /* Indicate no mac active */ 6600 vars->mac_type = MAC_TYPE_NONE; 6601 6602 /* Update shared memory */ 6603 vars->link_status &= ~LINK_UPDATE_MASK; 6604 vars->line_speed = 0; 6605 bnx2x_update_mng(params, vars->link_status); 6606 6607 /* Activate nig drain */ 6608 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1); 6609 6610 /* Disable emac */ 6611 if (!CHIP_IS_E3(bp)) 6612 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0); 6613 6614 usleep_range(10000, 20000); 6615 /* Reset BigMac/Xmac */ 6616 if (CHIP_IS_E1x(bp) || 6617 CHIP_IS_E2(bp)) 6618 bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 0); 6619 6620 if (CHIP_IS_E3(bp)) { 6621 /* Prevent LPI Generation by chip */ 6622 REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2), 6623 0); 6624 REG_WR(bp, MISC_REG_CPMU_LP_MASK_ENT_P0 + (params->port << 2), 6625 0); 6626 vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK | 6627 SHMEM_EEE_ACTIVE_BIT); 6628 6629 bnx2x_update_mng_eee(params, vars->eee_status); 6630 bnx2x_set_xmac_rxtx(params, 0); 6631 bnx2x_set_umac_rxtx(params, 0); 6632 } 6633 6634 return 0; 6635 } 6636 6637 static int bnx2x_update_link_up(struct link_params *params, 6638 struct link_vars *vars, 6639 u8 link_10g) 6640 { 6641 struct bnx2x *bp = params->bp; 6642 u8 phy_idx, port = params->port; 6643 int rc = 0; 6644 6645 vars->link_status |= (LINK_STATUS_LINK_UP | 6646 LINK_STATUS_PHYSICAL_LINK_FLAG); 6647 vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG; 6648 6649 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) 6650 vars->link_status |= 6651 LINK_STATUS_TX_FLOW_CONTROL_ENABLED; 6652 6653 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX) 6654 vars->link_status |= 6655 LINK_STATUS_RX_FLOW_CONTROL_ENABLED; 6656 if (USES_WARPCORE(bp)) { 6657 if (link_10g) { 6658 if (bnx2x_xmac_enable(params, vars, 0) == 6659 -ESRCH) { 6660 DP(NETIF_MSG_LINK, "Found errors on XMAC\n"); 6661 vars->link_up = 0; 6662 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG; 6663 vars->link_status &= ~LINK_STATUS_LINK_UP; 6664 } 6665 } else 6666 bnx2x_umac_enable(params, vars, 0); 6667 bnx2x_set_led(params, vars, 6668 LED_MODE_OPER, vars->line_speed); 6669 6670 if ((vars->eee_status & SHMEM_EEE_ACTIVE_BIT) && 6671 (vars->eee_status & SHMEM_EEE_LPI_REQUESTED_BIT)) { 6672 DP(NETIF_MSG_LINK, "Enabling LPI assertion\n"); 6673 REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + 6674 (params->port << 2), 1); 6675 REG_WR(bp, MISC_REG_CPMU_LP_DR_ENABLE, 1); 6676 REG_WR(bp, MISC_REG_CPMU_LP_MASK_ENT_P0 + 6677 (params->port << 2), 0xfc20); 6678 } 6679 } 6680 if ((CHIP_IS_E1x(bp) || 6681 CHIP_IS_E2(bp))) { 6682 if (link_10g) { 6683 if (bnx2x_bmac_enable(params, vars, 0, 1) == 6684 -ESRCH) { 6685 DP(NETIF_MSG_LINK, "Found errors on BMAC\n"); 6686 vars->link_up = 0; 6687 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG; 6688 vars->link_status &= ~LINK_STATUS_LINK_UP; 6689 } 6690 6691 bnx2x_set_led(params, vars, 6692 LED_MODE_OPER, SPEED_10000); 6693 } else { 6694 rc = bnx2x_emac_program(params, vars); 6695 bnx2x_emac_enable(params, vars, 0); 6696 6697 /* AN complete? */ 6698 if ((vars->link_status & 6699 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) 6700 && (!(vars->phy_flags & PHY_SGMII_FLAG)) && 6701 SINGLE_MEDIA_DIRECT(params)) 6702 bnx2x_set_gmii_tx_driver(params); 6703 } 6704 } 6705 6706 /* PBF - link up */ 6707 if (CHIP_IS_E1x(bp)) 6708 rc |= bnx2x_pbf_update(params, vars->flow_ctrl, 6709 vars->line_speed); 6710 6711 /* Disable drain */ 6712 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0); 6713 6714 /* Update shared memory */ 6715 bnx2x_update_mng(params, vars->link_status); 6716 bnx2x_update_mng_eee(params, vars->eee_status); 6717 /* Check remote fault */ 6718 for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) { 6719 if (params->phy[phy_idx].flags & FLAGS_TX_ERROR_CHECK) { 6720 bnx2x_check_half_open_conn(params, vars, 0); 6721 break; 6722 } 6723 } 6724 msleep(20); 6725 return rc; 6726 } 6727 /* The bnx2x_link_update function should be called upon link 6728 * interrupt. 6729 * Link is considered up as follows: 6730 * - DIRECT_SINGLE_MEDIA - Only XGXS link (internal link) needs 6731 * to be up 6732 * - SINGLE_MEDIA - The link between the 577xx and the external 6733 * phy (XGXS) need to up as well as the external link of the 6734 * phy (PHY_EXT1) 6735 * - DUAL_MEDIA - The link between the 577xx and the first 6736 * external phy needs to be up, and at least one of the 2 6737 * external phy link must be up. 6738 */ 6739 int bnx2x_link_update(struct link_params *params, struct link_vars *vars) 6740 { 6741 struct bnx2x *bp = params->bp; 6742 struct link_vars phy_vars[MAX_PHYS]; 6743 u8 port = params->port; 6744 u8 link_10g_plus, phy_index; 6745 u8 ext_phy_link_up = 0, cur_link_up; 6746 int rc = 0; 6747 u8 is_mi_int = 0; 6748 u16 ext_phy_line_speed = 0, prev_line_speed = vars->line_speed; 6749 u8 active_external_phy = INT_PHY; 6750 vars->phy_flags &= ~PHY_HALF_OPEN_CONN_FLAG; 6751 vars->link_status &= ~LINK_UPDATE_MASK; 6752 for (phy_index = INT_PHY; phy_index < params->num_phys; 6753 phy_index++) { 6754 phy_vars[phy_index].flow_ctrl = 0; 6755 phy_vars[phy_index].link_status = 0; 6756 phy_vars[phy_index].line_speed = 0; 6757 phy_vars[phy_index].duplex = DUPLEX_FULL; 6758 phy_vars[phy_index].phy_link_up = 0; 6759 phy_vars[phy_index].link_up = 0; 6760 phy_vars[phy_index].fault_detected = 0; 6761 /* different consideration, since vars holds inner state */ 6762 phy_vars[phy_index].eee_status = vars->eee_status; 6763 } 6764 6765 if (USES_WARPCORE(bp)) 6766 bnx2x_set_aer_mmd(params, ¶ms->phy[INT_PHY]); 6767 6768 DP(NETIF_MSG_LINK, "port %x, XGXS?%x, int_status 0x%x\n", 6769 port, (vars->phy_flags & PHY_XGXS_FLAG), 6770 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4)); 6771 6772 is_mi_int = (u8)(REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + 6773 port*0x18) > 0); 6774 DP(NETIF_MSG_LINK, "int_mask 0x%x MI_INT %x, SERDES_LINK %x\n", 6775 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4), 6776 is_mi_int, 6777 REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c)); 6778 6779 DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n", 6780 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68), 6781 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68)); 6782 6783 /* Disable emac */ 6784 if (!CHIP_IS_E3(bp)) 6785 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0); 6786 6787 /* Step 1: 6788 * Check external link change only for external phys, and apply 6789 * priority selection between them in case the link on both phys 6790 * is up. Note that instead of the common vars, a temporary 6791 * vars argument is used since each phy may have different link/ 6792 * speed/duplex result 6793 */ 6794 for (phy_index = EXT_PHY1; phy_index < params->num_phys; 6795 phy_index++) { 6796 struct bnx2x_phy *phy = ¶ms->phy[phy_index]; 6797 if (!phy->read_status) 6798 continue; 6799 /* Read link status and params of this ext phy */ 6800 cur_link_up = phy->read_status(phy, params, 6801 &phy_vars[phy_index]); 6802 if (cur_link_up) { 6803 DP(NETIF_MSG_LINK, "phy in index %d link is up\n", 6804 phy_index); 6805 } else { 6806 DP(NETIF_MSG_LINK, "phy in index %d link is down\n", 6807 phy_index); 6808 continue; 6809 } 6810 6811 if (!ext_phy_link_up) { 6812 ext_phy_link_up = 1; 6813 active_external_phy = phy_index; 6814 } else { 6815 switch (bnx2x_phy_selection(params)) { 6816 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT: 6817 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY: 6818 /* In this option, the first PHY makes sure to pass the 6819 * traffic through itself only. 6820 * Its not clear how to reset the link on the second phy 6821 */ 6822 active_external_phy = EXT_PHY1; 6823 break; 6824 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY: 6825 /* In this option, the first PHY makes sure to pass the 6826 * traffic through the second PHY. 6827 */ 6828 active_external_phy = EXT_PHY2; 6829 break; 6830 default: 6831 /* Link indication on both PHYs with the following cases 6832 * is invalid: 6833 * - FIRST_PHY means that second phy wasn't initialized, 6834 * hence its link is expected to be down 6835 * - SECOND_PHY means that first phy should not be able 6836 * to link up by itself (using configuration) 6837 * - DEFAULT should be overriden during initialiazation 6838 */ 6839 DP(NETIF_MSG_LINK, "Invalid link indication" 6840 "mpc=0x%x. DISABLING LINK !!!\n", 6841 params->multi_phy_config); 6842 ext_phy_link_up = 0; 6843 break; 6844 } 6845 } 6846 } 6847 prev_line_speed = vars->line_speed; 6848 /* Step 2: 6849 * Read the status of the internal phy. In case of 6850 * DIRECT_SINGLE_MEDIA board, this link is the external link, 6851 * otherwise this is the link between the 577xx and the first 6852 * external phy 6853 */ 6854 if (params->phy[INT_PHY].read_status) 6855 params->phy[INT_PHY].read_status( 6856 ¶ms->phy[INT_PHY], 6857 params, vars); 6858 /* The INT_PHY flow control reside in the vars. This include the 6859 * case where the speed or flow control are not set to AUTO. 6860 * Otherwise, the active external phy flow control result is set 6861 * to the vars. The ext_phy_line_speed is needed to check if the 6862 * speed is different between the internal phy and external phy. 6863 * This case may be result of intermediate link speed change. 6864 */ 6865 if (active_external_phy > INT_PHY) { 6866 vars->flow_ctrl = phy_vars[active_external_phy].flow_ctrl; 6867 /* Link speed is taken from the XGXS. AN and FC result from 6868 * the external phy. 6869 */ 6870 vars->link_status |= phy_vars[active_external_phy].link_status; 6871 6872 /* if active_external_phy is first PHY and link is up - disable 6873 * disable TX on second external PHY 6874 */ 6875 if (active_external_phy == EXT_PHY1) { 6876 if (params->phy[EXT_PHY2].phy_specific_func) { 6877 DP(NETIF_MSG_LINK, 6878 "Disabling TX on EXT_PHY2\n"); 6879 params->phy[EXT_PHY2].phy_specific_func( 6880 ¶ms->phy[EXT_PHY2], 6881 params, DISABLE_TX); 6882 } 6883 } 6884 6885 ext_phy_line_speed = phy_vars[active_external_phy].line_speed; 6886 vars->duplex = phy_vars[active_external_phy].duplex; 6887 if (params->phy[active_external_phy].supported & 6888 SUPPORTED_FIBRE) 6889 vars->link_status |= LINK_STATUS_SERDES_LINK; 6890 else 6891 vars->link_status &= ~LINK_STATUS_SERDES_LINK; 6892 6893 vars->eee_status = phy_vars[active_external_phy].eee_status; 6894 6895 DP(NETIF_MSG_LINK, "Active external phy selected: %x\n", 6896 active_external_phy); 6897 } 6898 6899 for (phy_index = EXT_PHY1; phy_index < params->num_phys; 6900 phy_index++) { 6901 if (params->phy[phy_index].flags & 6902 FLAGS_REARM_LATCH_SIGNAL) { 6903 bnx2x_rearm_latch_signal(bp, port, 6904 phy_index == 6905 active_external_phy); 6906 break; 6907 } 6908 } 6909 DP(NETIF_MSG_LINK, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x," 6910 " ext_phy_line_speed = %d\n", vars->flow_ctrl, 6911 vars->link_status, ext_phy_line_speed); 6912 /* Upon link speed change set the NIG into drain mode. Comes to 6913 * deals with possible FIFO glitch due to clk change when speed 6914 * is decreased without link down indicator 6915 */ 6916 6917 if (vars->phy_link_up) { 6918 if (!(SINGLE_MEDIA_DIRECT(params)) && ext_phy_link_up && 6919 (ext_phy_line_speed != vars->line_speed)) { 6920 DP(NETIF_MSG_LINK, "Internal link speed %d is" 6921 " different than the external" 6922 " link speed %d\n", vars->line_speed, 6923 ext_phy_line_speed); 6924 vars->phy_link_up = 0; 6925 } else if (prev_line_speed != vars->line_speed) { 6926 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 6927 0); 6928 usleep_range(1000, 2000); 6929 } 6930 } 6931 6932 /* Anything 10 and over uses the bmac */ 6933 link_10g_plus = (vars->line_speed >= SPEED_10000); 6934 6935 bnx2x_link_int_ack(params, vars, link_10g_plus); 6936 6937 /* In case external phy link is up, and internal link is down 6938 * (not initialized yet probably after link initialization, it 6939 * needs to be initialized. 6940 * Note that after link down-up as result of cable plug, the xgxs 6941 * link would probably become up again without the need 6942 * initialize it 6943 */ 6944 if (!(SINGLE_MEDIA_DIRECT(params))) { 6945 DP(NETIF_MSG_LINK, "ext_phy_link_up = %d, int_link_up = %d," 6946 " init_preceding = %d\n", ext_phy_link_up, 6947 vars->phy_link_up, 6948 params->phy[EXT_PHY1].flags & 6949 FLAGS_INIT_XGXS_FIRST); 6950 if (!(params->phy[EXT_PHY1].flags & 6951 FLAGS_INIT_XGXS_FIRST) 6952 && ext_phy_link_up && !vars->phy_link_up) { 6953 vars->line_speed = ext_phy_line_speed; 6954 if (vars->line_speed < SPEED_1000) 6955 vars->phy_flags |= PHY_SGMII_FLAG; 6956 else 6957 vars->phy_flags &= ~PHY_SGMII_FLAG; 6958 6959 if (params->phy[INT_PHY].config_init) 6960 params->phy[INT_PHY].config_init( 6961 ¶ms->phy[INT_PHY], params, 6962 vars); 6963 } 6964 } 6965 /* Link is up only if both local phy and external phy (in case of 6966 * non-direct board) are up and no fault detected on active PHY. 6967 */ 6968 vars->link_up = (vars->phy_link_up && 6969 (ext_phy_link_up || 6970 SINGLE_MEDIA_DIRECT(params)) && 6971 (phy_vars[active_external_phy].fault_detected == 0)); 6972 6973 /* Update the PFC configuration in case it was changed */ 6974 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) 6975 vars->link_status |= LINK_STATUS_PFC_ENABLED; 6976 else 6977 vars->link_status &= ~LINK_STATUS_PFC_ENABLED; 6978 6979 if (vars->link_up) 6980 rc = bnx2x_update_link_up(params, vars, link_10g_plus); 6981 else 6982 rc = bnx2x_update_link_down(params, vars); 6983 6984 /* Update MCP link status was changed */ 6985 if (params->feature_config_flags & FEATURE_CONFIG_BC_SUPPORTS_AFEX) 6986 bnx2x_fw_command(bp, DRV_MSG_CODE_LINK_STATUS_CHANGED, 0); 6987 6988 return rc; 6989 } 6990 6991 /*****************************************************************************/ 6992 /* External Phy section */ 6993 /*****************************************************************************/ 6994 void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port) 6995 { 6996 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, 6997 MISC_REGISTERS_GPIO_OUTPUT_LOW, port); 6998 usleep_range(1000, 2000); 6999 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, 7000 MISC_REGISTERS_GPIO_OUTPUT_HIGH, port); 7001 } 7002 7003 static void bnx2x_save_spirom_version(struct bnx2x *bp, u8 port, 7004 u32 spirom_ver, u32 ver_addr) 7005 { 7006 DP(NETIF_MSG_LINK, "FW version 0x%x:0x%x for port %d\n", 7007 (u16)(spirom_ver>>16), (u16)spirom_ver, port); 7008 7009 if (ver_addr) 7010 REG_WR(bp, ver_addr, spirom_ver); 7011 } 7012 7013 static void bnx2x_save_bcm_spirom_ver(struct bnx2x *bp, 7014 struct bnx2x_phy *phy, 7015 u8 port) 7016 { 7017 u16 fw_ver1, fw_ver2; 7018 7019 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 7020 MDIO_PMA_REG_ROM_VER1, &fw_ver1); 7021 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 7022 MDIO_PMA_REG_ROM_VER2, &fw_ver2); 7023 bnx2x_save_spirom_version(bp, port, (u32)(fw_ver1<<16 | fw_ver2), 7024 phy->ver_addr); 7025 } 7026 7027 static void bnx2x_ext_phy_10G_an_resolve(struct bnx2x *bp, 7028 struct bnx2x_phy *phy, 7029 struct link_vars *vars) 7030 { 7031 u16 val; 7032 bnx2x_cl45_read(bp, phy, 7033 MDIO_AN_DEVAD, 7034 MDIO_AN_REG_STATUS, &val); 7035 bnx2x_cl45_read(bp, phy, 7036 MDIO_AN_DEVAD, 7037 MDIO_AN_REG_STATUS, &val); 7038 if (val & (1<<5)) 7039 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; 7040 if ((val & (1<<0)) == 0) 7041 vars->link_status |= LINK_STATUS_PARALLEL_DETECTION_USED; 7042 } 7043 7044 /******************************************************************/ 7045 /* common BCM8073/BCM8727 PHY SECTION */ 7046 /******************************************************************/ 7047 static void bnx2x_8073_resolve_fc(struct bnx2x_phy *phy, 7048 struct link_params *params, 7049 struct link_vars *vars) 7050 { 7051 struct bnx2x *bp = params->bp; 7052 if (phy->req_line_speed == SPEED_10 || 7053 phy->req_line_speed == SPEED_100) { 7054 vars->flow_ctrl = phy->req_flow_ctrl; 7055 return; 7056 } 7057 7058 if (bnx2x_ext_phy_resolve_fc(phy, params, vars) && 7059 (vars->flow_ctrl == BNX2X_FLOW_CTRL_NONE)) { 7060 u16 pause_result; 7061 u16 ld_pause; /* local */ 7062 u16 lp_pause; /* link partner */ 7063 bnx2x_cl45_read(bp, phy, 7064 MDIO_AN_DEVAD, 7065 MDIO_AN_REG_CL37_FC_LD, &ld_pause); 7066 7067 bnx2x_cl45_read(bp, phy, 7068 MDIO_AN_DEVAD, 7069 MDIO_AN_REG_CL37_FC_LP, &lp_pause); 7070 pause_result = (ld_pause & 7071 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 5; 7072 pause_result |= (lp_pause & 7073 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 7; 7074 7075 bnx2x_pause_resolve(vars, pause_result); 7076 DP(NETIF_MSG_LINK, "Ext PHY CL37 pause result 0x%x\n", 7077 pause_result); 7078 } 7079 } 7080 static int bnx2x_8073_8727_external_rom_boot(struct bnx2x *bp, 7081 struct bnx2x_phy *phy, 7082 u8 port) 7083 { 7084 u32 count = 0; 7085 u16 fw_ver1, fw_msgout; 7086 int rc = 0; 7087 7088 /* Boot port from external ROM */ 7089 /* EDC grst */ 7090 bnx2x_cl45_write(bp, phy, 7091 MDIO_PMA_DEVAD, 7092 MDIO_PMA_REG_GEN_CTRL, 7093 0x0001); 7094 7095 /* Ucode reboot and rst */ 7096 bnx2x_cl45_write(bp, phy, 7097 MDIO_PMA_DEVAD, 7098 MDIO_PMA_REG_GEN_CTRL, 7099 0x008c); 7100 7101 bnx2x_cl45_write(bp, phy, 7102 MDIO_PMA_DEVAD, 7103 MDIO_PMA_REG_MISC_CTRL1, 0x0001); 7104 7105 /* Reset internal microprocessor */ 7106 bnx2x_cl45_write(bp, phy, 7107 MDIO_PMA_DEVAD, 7108 MDIO_PMA_REG_GEN_CTRL, 7109 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET); 7110 7111 /* Release srst bit */ 7112 bnx2x_cl45_write(bp, phy, 7113 MDIO_PMA_DEVAD, 7114 MDIO_PMA_REG_GEN_CTRL, 7115 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP); 7116 7117 /* Delay 100ms per the PHY specifications */ 7118 msleep(100); 7119 7120 /* 8073 sometimes taking longer to download */ 7121 do { 7122 count++; 7123 if (count > 300) { 7124 DP(NETIF_MSG_LINK, 7125 "bnx2x_8073_8727_external_rom_boot port %x:" 7126 "Download failed. fw version = 0x%x\n", 7127 port, fw_ver1); 7128 rc = -EINVAL; 7129 break; 7130 } 7131 7132 bnx2x_cl45_read(bp, phy, 7133 MDIO_PMA_DEVAD, 7134 MDIO_PMA_REG_ROM_VER1, &fw_ver1); 7135 bnx2x_cl45_read(bp, phy, 7136 MDIO_PMA_DEVAD, 7137 MDIO_PMA_REG_M8051_MSGOUT_REG, &fw_msgout); 7138 7139 usleep_range(1000, 2000); 7140 } while (fw_ver1 == 0 || fw_ver1 == 0x4321 || 7141 ((fw_msgout & 0xff) != 0x03 && (phy->type == 7142 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073))); 7143 7144 /* Clear ser_boot_ctl bit */ 7145 bnx2x_cl45_write(bp, phy, 7146 MDIO_PMA_DEVAD, 7147 MDIO_PMA_REG_MISC_CTRL1, 0x0000); 7148 bnx2x_save_bcm_spirom_ver(bp, phy, port); 7149 7150 DP(NETIF_MSG_LINK, 7151 "bnx2x_8073_8727_external_rom_boot port %x:" 7152 "Download complete. fw version = 0x%x\n", 7153 port, fw_ver1); 7154 7155 return rc; 7156 } 7157 7158 /******************************************************************/ 7159 /* BCM8073 PHY SECTION */ 7160 /******************************************************************/ 7161 static int bnx2x_8073_is_snr_needed(struct bnx2x *bp, struct bnx2x_phy *phy) 7162 { 7163 /* This is only required for 8073A1, version 102 only */ 7164 u16 val; 7165 7166 /* Read 8073 HW revision*/ 7167 bnx2x_cl45_read(bp, phy, 7168 MDIO_PMA_DEVAD, 7169 MDIO_PMA_REG_8073_CHIP_REV, &val); 7170 7171 if (val != 1) { 7172 /* No need to workaround in 8073 A1 */ 7173 return 0; 7174 } 7175 7176 bnx2x_cl45_read(bp, phy, 7177 MDIO_PMA_DEVAD, 7178 MDIO_PMA_REG_ROM_VER2, &val); 7179 7180 /* SNR should be applied only for version 0x102 */ 7181 if (val != 0x102) 7182 return 0; 7183 7184 return 1; 7185 } 7186 7187 static int bnx2x_8073_xaui_wa(struct bnx2x *bp, struct bnx2x_phy *phy) 7188 { 7189 u16 val, cnt, cnt1 ; 7190 7191 bnx2x_cl45_read(bp, phy, 7192 MDIO_PMA_DEVAD, 7193 MDIO_PMA_REG_8073_CHIP_REV, &val); 7194 7195 if (val > 0) { 7196 /* No need to workaround in 8073 A1 */ 7197 return 0; 7198 } 7199 /* XAUI workaround in 8073 A0: */ 7200 7201 /* After loading the boot ROM and restarting Autoneg, poll 7202 * Dev1, Reg $C820: 7203 */ 7204 7205 for (cnt = 0; cnt < 1000; cnt++) { 7206 bnx2x_cl45_read(bp, phy, 7207 MDIO_PMA_DEVAD, 7208 MDIO_PMA_REG_8073_SPEED_LINK_STATUS, 7209 &val); 7210 /* If bit [14] = 0 or bit [13] = 0, continue on with 7211 * system initialization (XAUI work-around not required, as 7212 * these bits indicate 2.5G or 1G link up). 7213 */ 7214 if (!(val & (1<<14)) || !(val & (1<<13))) { 7215 DP(NETIF_MSG_LINK, "XAUI work-around not required\n"); 7216 return 0; 7217 } else if (!(val & (1<<15))) { 7218 DP(NETIF_MSG_LINK, "bit 15 went off\n"); 7219 /* If bit 15 is 0, then poll Dev1, Reg $C841 until it's 7220 * MSB (bit15) goes to 1 (indicating that the XAUI 7221 * workaround has completed), then continue on with 7222 * system initialization. 7223 */ 7224 for (cnt1 = 0; cnt1 < 1000; cnt1++) { 7225 bnx2x_cl45_read(bp, phy, 7226 MDIO_PMA_DEVAD, 7227 MDIO_PMA_REG_8073_XAUI_WA, &val); 7228 if (val & (1<<15)) { 7229 DP(NETIF_MSG_LINK, 7230 "XAUI workaround has completed\n"); 7231 return 0; 7232 } 7233 usleep_range(3000, 6000); 7234 } 7235 break; 7236 } 7237 usleep_range(3000, 6000); 7238 } 7239 DP(NETIF_MSG_LINK, "Warning: XAUI work-around timeout !!!\n"); 7240 return -EINVAL; 7241 } 7242 7243 static void bnx2x_807x_force_10G(struct bnx2x *bp, struct bnx2x_phy *phy) 7244 { 7245 /* Force KR or KX */ 7246 bnx2x_cl45_write(bp, phy, 7247 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040); 7248 bnx2x_cl45_write(bp, phy, 7249 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0x000b); 7250 bnx2x_cl45_write(bp, phy, 7251 MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0000); 7252 bnx2x_cl45_write(bp, phy, 7253 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000); 7254 } 7255 7256 static void bnx2x_8073_set_pause_cl37(struct link_params *params, 7257 struct bnx2x_phy *phy, 7258 struct link_vars *vars) 7259 { 7260 u16 cl37_val; 7261 struct bnx2x *bp = params->bp; 7262 bnx2x_cl45_read(bp, phy, 7263 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &cl37_val); 7264 7265 cl37_val &= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; 7266 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */ 7267 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); 7268 if ((vars->ieee_fc & 7269 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) == 7270 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) { 7271 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC; 7272 } 7273 if ((vars->ieee_fc & 7274 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) == 7275 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) { 7276 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC; 7277 } 7278 if ((vars->ieee_fc & 7279 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) == 7280 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) { 7281 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; 7282 } 7283 DP(NETIF_MSG_LINK, 7284 "Ext phy AN advertize cl37 0x%x\n", cl37_val); 7285 7286 bnx2x_cl45_write(bp, phy, 7287 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, cl37_val); 7288 msleep(500); 7289 } 7290 7291 static void bnx2x_8073_specific_func(struct bnx2x_phy *phy, 7292 struct link_params *params, 7293 u32 action) 7294 { 7295 struct bnx2x *bp = params->bp; 7296 switch (action) { 7297 case PHY_INIT: 7298 /* Enable LASI */ 7299 bnx2x_cl45_write(bp, phy, 7300 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, (1<<2)); 7301 bnx2x_cl45_write(bp, phy, 7302 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0004); 7303 break; 7304 } 7305 } 7306 7307 static int bnx2x_8073_config_init(struct bnx2x_phy *phy, 7308 struct link_params *params, 7309 struct link_vars *vars) 7310 { 7311 struct bnx2x *bp = params->bp; 7312 u16 val = 0, tmp1; 7313 u8 gpio_port; 7314 DP(NETIF_MSG_LINK, "Init 8073\n"); 7315 7316 if (CHIP_IS_E2(bp)) 7317 gpio_port = BP_PATH(bp); 7318 else 7319 gpio_port = params->port; 7320 /* Restore normal power mode*/ 7321 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 7322 MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port); 7323 7324 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, 7325 MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port); 7326 7327 bnx2x_8073_specific_func(phy, params, PHY_INIT); 7328 bnx2x_8073_set_pause_cl37(params, phy, vars); 7329 7330 bnx2x_cl45_read(bp, phy, 7331 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1); 7332 7333 bnx2x_cl45_read(bp, phy, 7334 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1); 7335 7336 DP(NETIF_MSG_LINK, "Before rom RX_ALARM(port1): 0x%x\n", tmp1); 7337 7338 /* Swap polarity if required - Must be done only in non-1G mode */ 7339 if (params->lane_config & PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) { 7340 /* Configure the 8073 to swap _P and _N of the KR lines */ 7341 DP(NETIF_MSG_LINK, "Swapping polarity for the 8073\n"); 7342 /* 10G Rx/Tx and 1G Tx signal polarity swap */ 7343 bnx2x_cl45_read(bp, phy, 7344 MDIO_PMA_DEVAD, 7345 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL, &val); 7346 bnx2x_cl45_write(bp, phy, 7347 MDIO_PMA_DEVAD, 7348 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL, 7349 (val | (3<<9))); 7350 } 7351 7352 7353 /* Enable CL37 BAM */ 7354 if (REG_RD(bp, params->shmem_base + 7355 offsetof(struct shmem_region, dev_info. 7356 port_hw_config[params->port].default_cfg)) & 7357 PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) { 7358 7359 bnx2x_cl45_read(bp, phy, 7360 MDIO_AN_DEVAD, 7361 MDIO_AN_REG_8073_BAM, &val); 7362 bnx2x_cl45_write(bp, phy, 7363 MDIO_AN_DEVAD, 7364 MDIO_AN_REG_8073_BAM, val | 1); 7365 DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n"); 7366 } 7367 if (params->loopback_mode == LOOPBACK_EXT) { 7368 bnx2x_807x_force_10G(bp, phy); 7369 DP(NETIF_MSG_LINK, "Forced speed 10G on 807X\n"); 7370 return 0; 7371 } else { 7372 bnx2x_cl45_write(bp, phy, 7373 MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0002); 7374 } 7375 if (phy->req_line_speed != SPEED_AUTO_NEG) { 7376 if (phy->req_line_speed == SPEED_10000) { 7377 val = (1<<7); 7378 } else if (phy->req_line_speed == SPEED_2500) { 7379 val = (1<<5); 7380 /* Note that 2.5G works only when used with 1G 7381 * advertisement 7382 */ 7383 } else 7384 val = (1<<5); 7385 } else { 7386 val = 0; 7387 if (phy->speed_cap_mask & 7388 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) 7389 val |= (1<<7); 7390 7391 /* Note that 2.5G works only when used with 1G advertisement */ 7392 if (phy->speed_cap_mask & 7393 (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G | 7394 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) 7395 val |= (1<<5); 7396 DP(NETIF_MSG_LINK, "807x autoneg val = 0x%x\n", val); 7397 } 7398 7399 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val); 7400 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, &tmp1); 7401 7402 if (((phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) && 7403 (phy->req_line_speed == SPEED_AUTO_NEG)) || 7404 (phy->req_line_speed == SPEED_2500)) { 7405 u16 phy_ver; 7406 /* Allow 2.5G for A1 and above */ 7407 bnx2x_cl45_read(bp, phy, 7408 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV, 7409 &phy_ver); 7410 DP(NETIF_MSG_LINK, "Add 2.5G\n"); 7411 if (phy_ver > 0) 7412 tmp1 |= 1; 7413 else 7414 tmp1 &= 0xfffe; 7415 } else { 7416 DP(NETIF_MSG_LINK, "Disable 2.5G\n"); 7417 tmp1 &= 0xfffe; 7418 } 7419 7420 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, tmp1); 7421 /* Add support for CL37 (passive mode) II */ 7422 7423 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &tmp1); 7424 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, 7425 (tmp1 | ((phy->req_duplex == DUPLEX_FULL) ? 7426 0x20 : 0x40))); 7427 7428 /* Add support for CL37 (passive mode) III */ 7429 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000); 7430 7431 /* The SNR will improve about 2db by changing BW and FEE main 7432 * tap. Rest commands are executed after link is up 7433 * Change FFE main cursor to 5 in EDC register 7434 */ 7435 if (bnx2x_8073_is_snr_needed(bp, phy)) 7436 bnx2x_cl45_write(bp, phy, 7437 MDIO_PMA_DEVAD, MDIO_PMA_REG_EDC_FFE_MAIN, 7438 0xFB0C); 7439 7440 /* Enable FEC (Forware Error Correction) Request in the AN */ 7441 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, &tmp1); 7442 tmp1 |= (1<<15); 7443 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, tmp1); 7444 7445 bnx2x_ext_phy_set_pause(params, phy, vars); 7446 7447 /* Restart autoneg */ 7448 msleep(500); 7449 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200); 7450 DP(NETIF_MSG_LINK, "807x Autoneg Restart: Advertise 1G=%x, 10G=%x\n", 7451 ((val & (1<<5)) > 0), ((val & (1<<7)) > 0)); 7452 return 0; 7453 } 7454 7455 static u8 bnx2x_8073_read_status(struct bnx2x_phy *phy, 7456 struct link_params *params, 7457 struct link_vars *vars) 7458 { 7459 struct bnx2x *bp = params->bp; 7460 u8 link_up = 0; 7461 u16 val1, val2; 7462 u16 link_status = 0; 7463 u16 an1000_status = 0; 7464 7465 bnx2x_cl45_read(bp, phy, 7466 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1); 7467 7468 DP(NETIF_MSG_LINK, "8703 LASI status 0x%x\n", val1); 7469 7470 /* Clear the interrupt LASI status register */ 7471 bnx2x_cl45_read(bp, phy, 7472 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2); 7473 bnx2x_cl45_read(bp, phy, 7474 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val1); 7475 DP(NETIF_MSG_LINK, "807x PCS status 0x%x->0x%x\n", val2, val1); 7476 /* Clear MSG-OUT */ 7477 bnx2x_cl45_read(bp, phy, 7478 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1); 7479 7480 /* Check the LASI */ 7481 bnx2x_cl45_read(bp, phy, 7482 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2); 7483 7484 DP(NETIF_MSG_LINK, "KR 0x9003 0x%x\n", val2); 7485 7486 /* Check the link status */ 7487 bnx2x_cl45_read(bp, phy, 7488 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2); 7489 DP(NETIF_MSG_LINK, "KR PCS status 0x%x\n", val2); 7490 7491 bnx2x_cl45_read(bp, phy, 7492 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2); 7493 bnx2x_cl45_read(bp, phy, 7494 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1); 7495 link_up = ((val1 & 4) == 4); 7496 DP(NETIF_MSG_LINK, "PMA_REG_STATUS=0x%x\n", val1); 7497 7498 if (link_up && 7499 ((phy->req_line_speed != SPEED_10000))) { 7500 if (bnx2x_8073_xaui_wa(bp, phy) != 0) 7501 return 0; 7502 } 7503 bnx2x_cl45_read(bp, phy, 7504 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status); 7505 bnx2x_cl45_read(bp, phy, 7506 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status); 7507 7508 /* Check the link status on 1.1.2 */ 7509 bnx2x_cl45_read(bp, phy, 7510 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2); 7511 bnx2x_cl45_read(bp, phy, 7512 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1); 7513 DP(NETIF_MSG_LINK, "KR PMA status 0x%x->0x%x," 7514 "an_link_status=0x%x\n", val2, val1, an1000_status); 7515 7516 link_up = (((val1 & 4) == 4) || (an1000_status & (1<<1))); 7517 if (link_up && bnx2x_8073_is_snr_needed(bp, phy)) { 7518 /* The SNR will improve about 2dbby changing the BW and FEE main 7519 * tap. The 1st write to change FFE main tap is set before 7520 * restart AN. Change PLL Bandwidth in EDC register 7521 */ 7522 bnx2x_cl45_write(bp, phy, 7523 MDIO_PMA_DEVAD, MDIO_PMA_REG_PLL_BANDWIDTH, 7524 0x26BC); 7525 7526 /* Change CDR Bandwidth in EDC register */ 7527 bnx2x_cl45_write(bp, phy, 7528 MDIO_PMA_DEVAD, MDIO_PMA_REG_CDR_BANDWIDTH, 7529 0x0333); 7530 } 7531 bnx2x_cl45_read(bp, phy, 7532 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_SPEED_LINK_STATUS, 7533 &link_status); 7534 7535 /* Bits 0..2 --> speed detected, bits 13..15--> link is down */ 7536 if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) { 7537 link_up = 1; 7538 vars->line_speed = SPEED_10000; 7539 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n", 7540 params->port); 7541 } else if ((link_status & (1<<1)) && (!(link_status & (1<<14)))) { 7542 link_up = 1; 7543 vars->line_speed = SPEED_2500; 7544 DP(NETIF_MSG_LINK, "port %x: External link up in 2.5G\n", 7545 params->port); 7546 } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) { 7547 link_up = 1; 7548 vars->line_speed = SPEED_1000; 7549 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n", 7550 params->port); 7551 } else { 7552 link_up = 0; 7553 DP(NETIF_MSG_LINK, "port %x: External link is down\n", 7554 params->port); 7555 } 7556 7557 if (link_up) { 7558 /* Swap polarity if required */ 7559 if (params->lane_config & 7560 PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) { 7561 /* Configure the 8073 to swap P and N of the KR lines */ 7562 bnx2x_cl45_read(bp, phy, 7563 MDIO_XS_DEVAD, 7564 MDIO_XS_REG_8073_RX_CTRL_PCIE, &val1); 7565 /* Set bit 3 to invert Rx in 1G mode and clear this bit 7566 * when it`s in 10G mode. 7567 */ 7568 if (vars->line_speed == SPEED_1000) { 7569 DP(NETIF_MSG_LINK, "Swapping 1G polarity for" 7570 "the 8073\n"); 7571 val1 |= (1<<3); 7572 } else 7573 val1 &= ~(1<<3); 7574 7575 bnx2x_cl45_write(bp, phy, 7576 MDIO_XS_DEVAD, 7577 MDIO_XS_REG_8073_RX_CTRL_PCIE, 7578 val1); 7579 } 7580 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars); 7581 bnx2x_8073_resolve_fc(phy, params, vars); 7582 vars->duplex = DUPLEX_FULL; 7583 } 7584 7585 if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) { 7586 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, 7587 MDIO_AN_REG_LP_AUTO_NEG2, &val1); 7588 7589 if (val1 & (1<<5)) 7590 vars->link_status |= 7591 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; 7592 if (val1 & (1<<7)) 7593 vars->link_status |= 7594 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; 7595 } 7596 7597 return link_up; 7598 } 7599 7600 static void bnx2x_8073_link_reset(struct bnx2x_phy *phy, 7601 struct link_params *params) 7602 { 7603 struct bnx2x *bp = params->bp; 7604 u8 gpio_port; 7605 if (CHIP_IS_E2(bp)) 7606 gpio_port = BP_PATH(bp); 7607 else 7608 gpio_port = params->port; 7609 DP(NETIF_MSG_LINK, "Setting 8073 port %d into low power mode\n", 7610 gpio_port); 7611 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 7612 MISC_REGISTERS_GPIO_OUTPUT_LOW, 7613 gpio_port); 7614 } 7615 7616 /******************************************************************/ 7617 /* BCM8705 PHY SECTION */ 7618 /******************************************************************/ 7619 static int bnx2x_8705_config_init(struct bnx2x_phy *phy, 7620 struct link_params *params, 7621 struct link_vars *vars) 7622 { 7623 struct bnx2x *bp = params->bp; 7624 DP(NETIF_MSG_LINK, "init 8705\n"); 7625 /* Restore normal power mode*/ 7626 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 7627 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); 7628 /* HW reset */ 7629 bnx2x_ext_phy_hw_reset(bp, params->port); 7630 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040); 7631 bnx2x_wait_reset_complete(bp, phy, params); 7632 7633 bnx2x_cl45_write(bp, phy, 7634 MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL, 0x8288); 7635 bnx2x_cl45_write(bp, phy, 7636 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 0x7fbf); 7637 bnx2x_cl45_write(bp, phy, 7638 MDIO_PMA_DEVAD, MDIO_PMA_REG_CMU_PLL_BYPASS, 0x0100); 7639 bnx2x_cl45_write(bp, phy, 7640 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_CNTL, 0x1); 7641 /* BCM8705 doesn't have microcode, hence the 0 */ 7642 bnx2x_save_spirom_version(bp, params->port, params->shmem_base, 0); 7643 return 0; 7644 } 7645 7646 static u8 bnx2x_8705_read_status(struct bnx2x_phy *phy, 7647 struct link_params *params, 7648 struct link_vars *vars) 7649 { 7650 u8 link_up = 0; 7651 u16 val1, rx_sd; 7652 struct bnx2x *bp = params->bp; 7653 DP(NETIF_MSG_LINK, "read status 8705\n"); 7654 bnx2x_cl45_read(bp, phy, 7655 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1); 7656 DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1); 7657 7658 bnx2x_cl45_read(bp, phy, 7659 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1); 7660 DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1); 7661 7662 bnx2x_cl45_read(bp, phy, 7663 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd); 7664 7665 bnx2x_cl45_read(bp, phy, 7666 MDIO_PMA_DEVAD, 0xc809, &val1); 7667 bnx2x_cl45_read(bp, phy, 7668 MDIO_PMA_DEVAD, 0xc809, &val1); 7669 7670 DP(NETIF_MSG_LINK, "8705 1.c809 val=0x%x\n", val1); 7671 link_up = ((rx_sd & 0x1) && (val1 & (1<<9)) && ((val1 & (1<<8)) == 0)); 7672 if (link_up) { 7673 vars->line_speed = SPEED_10000; 7674 bnx2x_ext_phy_resolve_fc(phy, params, vars); 7675 } 7676 return link_up; 7677 } 7678 7679 /******************************************************************/ 7680 /* SFP+ module Section */ 7681 /******************************************************************/ 7682 static void bnx2x_set_disable_pmd_transmit(struct link_params *params, 7683 struct bnx2x_phy *phy, 7684 u8 pmd_dis) 7685 { 7686 struct bnx2x *bp = params->bp; 7687 /* Disable transmitter only for bootcodes which can enable it afterwards 7688 * (for D3 link) 7689 */ 7690 if (pmd_dis) { 7691 if (params->feature_config_flags & 7692 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED) 7693 DP(NETIF_MSG_LINK, "Disabling PMD transmitter\n"); 7694 else { 7695 DP(NETIF_MSG_LINK, "NOT disabling PMD transmitter\n"); 7696 return; 7697 } 7698 } else 7699 DP(NETIF_MSG_LINK, "Enabling PMD transmitter\n"); 7700 bnx2x_cl45_write(bp, phy, 7701 MDIO_PMA_DEVAD, 7702 MDIO_PMA_REG_TX_DISABLE, pmd_dis); 7703 } 7704 7705 static u8 bnx2x_get_gpio_port(struct link_params *params) 7706 { 7707 u8 gpio_port; 7708 u32 swap_val, swap_override; 7709 struct bnx2x *bp = params->bp; 7710 if (CHIP_IS_E2(bp)) 7711 gpio_port = BP_PATH(bp); 7712 else 7713 gpio_port = params->port; 7714 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); 7715 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); 7716 return gpio_port ^ (swap_val && swap_override); 7717 } 7718 7719 static void bnx2x_sfp_e1e2_set_transmitter(struct link_params *params, 7720 struct bnx2x_phy *phy, 7721 u8 tx_en) 7722 { 7723 u16 val; 7724 u8 port = params->port; 7725 struct bnx2x *bp = params->bp; 7726 u32 tx_en_mode; 7727 7728 /* Disable/Enable transmitter ( TX laser of the SFP+ module.)*/ 7729 tx_en_mode = REG_RD(bp, params->shmem_base + 7730 offsetof(struct shmem_region, 7731 dev_info.port_hw_config[port].sfp_ctrl)) & 7732 PORT_HW_CFG_TX_LASER_MASK; 7733 DP(NETIF_MSG_LINK, "Setting transmitter tx_en=%x for port %x " 7734 "mode = %x\n", tx_en, port, tx_en_mode); 7735 switch (tx_en_mode) { 7736 case PORT_HW_CFG_TX_LASER_MDIO: 7737 7738 bnx2x_cl45_read(bp, phy, 7739 MDIO_PMA_DEVAD, 7740 MDIO_PMA_REG_PHY_IDENTIFIER, 7741 &val); 7742 7743 if (tx_en) 7744 val &= ~(1<<15); 7745 else 7746 val |= (1<<15); 7747 7748 bnx2x_cl45_write(bp, phy, 7749 MDIO_PMA_DEVAD, 7750 MDIO_PMA_REG_PHY_IDENTIFIER, 7751 val); 7752 break; 7753 case PORT_HW_CFG_TX_LASER_GPIO0: 7754 case PORT_HW_CFG_TX_LASER_GPIO1: 7755 case PORT_HW_CFG_TX_LASER_GPIO2: 7756 case PORT_HW_CFG_TX_LASER_GPIO3: 7757 { 7758 u16 gpio_pin; 7759 u8 gpio_port, gpio_mode; 7760 if (tx_en) 7761 gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_HIGH; 7762 else 7763 gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_LOW; 7764 7765 gpio_pin = tx_en_mode - PORT_HW_CFG_TX_LASER_GPIO0; 7766 gpio_port = bnx2x_get_gpio_port(params); 7767 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port); 7768 break; 7769 } 7770 default: 7771 DP(NETIF_MSG_LINK, "Invalid TX_LASER_MDIO 0x%x\n", tx_en_mode); 7772 break; 7773 } 7774 } 7775 7776 static void bnx2x_sfp_set_transmitter(struct link_params *params, 7777 struct bnx2x_phy *phy, 7778 u8 tx_en) 7779 { 7780 struct bnx2x *bp = params->bp; 7781 DP(NETIF_MSG_LINK, "Setting SFP+ transmitter to %d\n", tx_en); 7782 if (CHIP_IS_E3(bp)) 7783 bnx2x_sfp_e3_set_transmitter(params, phy, tx_en); 7784 else 7785 bnx2x_sfp_e1e2_set_transmitter(params, phy, tx_en); 7786 } 7787 7788 static int bnx2x_8726_read_sfp_module_eeprom(struct bnx2x_phy *phy, 7789 struct link_params *params, 7790 u8 dev_addr, u16 addr, u8 byte_cnt, 7791 u8 *o_buf, u8 is_init) 7792 { 7793 struct bnx2x *bp = params->bp; 7794 u16 val = 0; 7795 u16 i; 7796 if (byte_cnt > SFP_EEPROM_PAGE_SIZE) { 7797 DP(NETIF_MSG_LINK, 7798 "Reading from eeprom is limited to 0xf\n"); 7799 return -EINVAL; 7800 } 7801 /* Set the read command byte count */ 7802 bnx2x_cl45_write(bp, phy, 7803 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT, 7804 (byte_cnt | (dev_addr << 8))); 7805 7806 /* Set the read command address */ 7807 bnx2x_cl45_write(bp, phy, 7808 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR, 7809 addr); 7810 7811 /* Activate read command */ 7812 bnx2x_cl45_write(bp, phy, 7813 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, 7814 0x2c0f); 7815 7816 /* Wait up to 500us for command complete status */ 7817 for (i = 0; i < 100; i++) { 7818 bnx2x_cl45_read(bp, phy, 7819 MDIO_PMA_DEVAD, 7820 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); 7821 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == 7822 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) 7823 break; 7824 udelay(5); 7825 } 7826 7827 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) != 7828 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) { 7829 DP(NETIF_MSG_LINK, 7830 "Got bad status 0x%x when reading from SFP+ EEPROM\n", 7831 (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK)); 7832 return -EINVAL; 7833 } 7834 7835 /* Read the buffer */ 7836 for (i = 0; i < byte_cnt; i++) { 7837 bnx2x_cl45_read(bp, phy, 7838 MDIO_PMA_DEVAD, 7839 MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i, &val); 7840 o_buf[i] = (u8)(val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK); 7841 } 7842 7843 for (i = 0; i < 100; i++) { 7844 bnx2x_cl45_read(bp, phy, 7845 MDIO_PMA_DEVAD, 7846 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); 7847 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == 7848 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE) 7849 return 0; 7850 usleep_range(1000, 2000); 7851 } 7852 return -EINVAL; 7853 } 7854 7855 static void bnx2x_warpcore_power_module(struct link_params *params, 7856 u8 power) 7857 { 7858 u32 pin_cfg; 7859 struct bnx2x *bp = params->bp; 7860 7861 pin_cfg = (REG_RD(bp, params->shmem_base + 7862 offsetof(struct shmem_region, 7863 dev_info.port_hw_config[params->port].e3_sfp_ctrl)) & 7864 PORT_HW_CFG_E3_PWR_DIS_MASK) >> 7865 PORT_HW_CFG_E3_PWR_DIS_SHIFT; 7866 7867 if (pin_cfg == PIN_CFG_NA) 7868 return; 7869 DP(NETIF_MSG_LINK, "Setting SFP+ module power to %d using pin cfg %d\n", 7870 power, pin_cfg); 7871 /* Low ==> corresponding SFP+ module is powered 7872 * high ==> the SFP+ module is powered down 7873 */ 7874 bnx2x_set_cfg_pin(bp, pin_cfg, power ^ 1); 7875 } 7876 static int bnx2x_warpcore_read_sfp_module_eeprom(struct bnx2x_phy *phy, 7877 struct link_params *params, 7878 u8 dev_addr, 7879 u16 addr, u8 byte_cnt, 7880 u8 *o_buf, u8 is_init) 7881 { 7882 int rc = 0; 7883 u8 i, j = 0, cnt = 0; 7884 u32 data_array[4]; 7885 u16 addr32; 7886 struct bnx2x *bp = params->bp; 7887 7888 if (byte_cnt > SFP_EEPROM_PAGE_SIZE) { 7889 DP(NETIF_MSG_LINK, 7890 "Reading from eeprom is limited to 16 bytes\n"); 7891 return -EINVAL; 7892 } 7893 7894 /* 4 byte aligned address */ 7895 addr32 = addr & (~0x3); 7896 do { 7897 if ((!is_init) && (cnt == I2C_WA_PWR_ITER)) { 7898 bnx2x_warpcore_power_module(params, 0); 7899 /* Note that 100us are not enough here */ 7900 usleep_range(1000, 2000); 7901 bnx2x_warpcore_power_module(params, 1); 7902 } 7903 rc = bnx2x_bsc_read(params, bp, dev_addr, addr32, 0, byte_cnt, 7904 data_array); 7905 } while ((rc != 0) && (++cnt < I2C_WA_RETRY_CNT)); 7906 7907 if (rc == 0) { 7908 for (i = (addr - addr32); i < byte_cnt + (addr - addr32); i++) { 7909 o_buf[j] = *((u8 *)data_array + i); 7910 j++; 7911 } 7912 } 7913 7914 return rc; 7915 } 7916 7917 static int bnx2x_8727_read_sfp_module_eeprom(struct bnx2x_phy *phy, 7918 struct link_params *params, 7919 u8 dev_addr, u16 addr, u8 byte_cnt, 7920 u8 *o_buf, u8 is_init) 7921 { 7922 struct bnx2x *bp = params->bp; 7923 u16 val, i; 7924 7925 if (byte_cnt > SFP_EEPROM_PAGE_SIZE) { 7926 DP(NETIF_MSG_LINK, 7927 "Reading from eeprom is limited to 0xf\n"); 7928 return -EINVAL; 7929 } 7930 7931 /* Set 2-wire transfer rate of SFP+ module EEPROM 7932 * to 100Khz since some DACs(direct attached cables) do 7933 * not work at 400Khz. 7934 */ 7935 bnx2x_cl45_write(bp, phy, 7936 MDIO_PMA_DEVAD, 7937 MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR, 7938 ((dev_addr << 8) | 1)); 7939 7940 /* Need to read from 1.8000 to clear it */ 7941 bnx2x_cl45_read(bp, phy, 7942 MDIO_PMA_DEVAD, 7943 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, 7944 &val); 7945 7946 /* Set the read command byte count */ 7947 bnx2x_cl45_write(bp, phy, 7948 MDIO_PMA_DEVAD, 7949 MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT, 7950 ((byte_cnt < 2) ? 2 : byte_cnt)); 7951 7952 /* Set the read command address */ 7953 bnx2x_cl45_write(bp, phy, 7954 MDIO_PMA_DEVAD, 7955 MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR, 7956 addr); 7957 /* Set the destination address */ 7958 bnx2x_cl45_write(bp, phy, 7959 MDIO_PMA_DEVAD, 7960 0x8004, 7961 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF); 7962 7963 /* Activate read command */ 7964 bnx2x_cl45_write(bp, phy, 7965 MDIO_PMA_DEVAD, 7966 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, 7967 0x8002); 7968 /* Wait appropriate time for two-wire command to finish before 7969 * polling the status register 7970 */ 7971 usleep_range(1000, 2000); 7972 7973 /* Wait up to 500us for command complete status */ 7974 for (i = 0; i < 100; i++) { 7975 bnx2x_cl45_read(bp, phy, 7976 MDIO_PMA_DEVAD, 7977 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); 7978 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == 7979 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) 7980 break; 7981 udelay(5); 7982 } 7983 7984 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) != 7985 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) { 7986 DP(NETIF_MSG_LINK, 7987 "Got bad status 0x%x when reading from SFP+ EEPROM\n", 7988 (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK)); 7989 return -EFAULT; 7990 } 7991 7992 /* Read the buffer */ 7993 for (i = 0; i < byte_cnt; i++) { 7994 bnx2x_cl45_read(bp, phy, 7995 MDIO_PMA_DEVAD, 7996 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF + i, &val); 7997 o_buf[i] = (u8)(val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK); 7998 } 7999 8000 for (i = 0; i < 100; i++) { 8001 bnx2x_cl45_read(bp, phy, 8002 MDIO_PMA_DEVAD, 8003 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); 8004 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == 8005 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE) 8006 return 0; 8007 usleep_range(1000, 2000); 8008 } 8009 8010 return -EINVAL; 8011 } 8012 int bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy, 8013 struct link_params *params, u8 dev_addr, 8014 u16 addr, u16 byte_cnt, u8 *o_buf) 8015 { 8016 int rc = 0; 8017 struct bnx2x *bp = params->bp; 8018 u8 xfer_size; 8019 u8 *user_data = o_buf; 8020 read_sfp_module_eeprom_func_p read_func; 8021 8022 if ((dev_addr != 0xa0) && (dev_addr != 0xa2)) { 8023 DP(NETIF_MSG_LINK, "invalid dev_addr 0x%x\n", dev_addr); 8024 return -EINVAL; 8025 } 8026 8027 switch (phy->type) { 8028 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: 8029 read_func = bnx2x_8726_read_sfp_module_eeprom; 8030 break; 8031 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: 8032 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722: 8033 read_func = bnx2x_8727_read_sfp_module_eeprom; 8034 break; 8035 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT: 8036 read_func = bnx2x_warpcore_read_sfp_module_eeprom; 8037 break; 8038 default: 8039 return -EOPNOTSUPP; 8040 } 8041 8042 while (!rc && (byte_cnt > 0)) { 8043 xfer_size = (byte_cnt > SFP_EEPROM_PAGE_SIZE) ? 8044 SFP_EEPROM_PAGE_SIZE : byte_cnt; 8045 rc = read_func(phy, params, dev_addr, addr, xfer_size, 8046 user_data, 0); 8047 byte_cnt -= xfer_size; 8048 user_data += xfer_size; 8049 addr += xfer_size; 8050 } 8051 return rc; 8052 } 8053 8054 static int bnx2x_get_edc_mode(struct bnx2x_phy *phy, 8055 struct link_params *params, 8056 u16 *edc_mode) 8057 { 8058 struct bnx2x *bp = params->bp; 8059 u32 sync_offset = 0, phy_idx, media_types; 8060 u8 gport, val[2], check_limiting_mode = 0; 8061 *edc_mode = EDC_MODE_LIMITING; 8062 phy->media_type = ETH_PHY_UNSPECIFIED; 8063 /* First check for copper cable */ 8064 if (bnx2x_read_sfp_module_eeprom(phy, 8065 params, 8066 I2C_DEV_ADDR_A0, 8067 SFP_EEPROM_CON_TYPE_ADDR, 8068 2, 8069 (u8 *)val) != 0) { 8070 DP(NETIF_MSG_LINK, "Failed to read from SFP+ module EEPROM\n"); 8071 return -EINVAL; 8072 } 8073 8074 switch (val[0]) { 8075 case SFP_EEPROM_CON_TYPE_VAL_COPPER: 8076 { 8077 u8 copper_module_type; 8078 phy->media_type = ETH_PHY_DA_TWINAX; 8079 /* Check if its active cable (includes SFP+ module) 8080 * of passive cable 8081 */ 8082 if (bnx2x_read_sfp_module_eeprom(phy, 8083 params, 8084 I2C_DEV_ADDR_A0, 8085 SFP_EEPROM_FC_TX_TECH_ADDR, 8086 1, 8087 &copper_module_type) != 0) { 8088 DP(NETIF_MSG_LINK, 8089 "Failed to read copper-cable-type" 8090 " from SFP+ EEPROM\n"); 8091 return -EINVAL; 8092 } 8093 8094 if (copper_module_type & 8095 SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) { 8096 DP(NETIF_MSG_LINK, "Active Copper cable detected\n"); 8097 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) 8098 *edc_mode = EDC_MODE_ACTIVE_DAC; 8099 else 8100 check_limiting_mode = 1; 8101 } else { 8102 *edc_mode = EDC_MODE_PASSIVE_DAC; 8103 /* Even in case PASSIVE_DAC indication is not set, 8104 * treat it as a passive DAC cable, since some cables 8105 * don't have this indication. 8106 */ 8107 if (copper_module_type & 8108 SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE) { 8109 DP(NETIF_MSG_LINK, 8110 "Passive Copper cable detected\n"); 8111 } else { 8112 DP(NETIF_MSG_LINK, 8113 "Unknown copper-cable-type\n"); 8114 } 8115 } 8116 break; 8117 } 8118 case SFP_EEPROM_CON_TYPE_VAL_LC: 8119 case SFP_EEPROM_CON_TYPE_VAL_RJ45: 8120 check_limiting_mode = 1; 8121 if ((val[1] & (SFP_EEPROM_COMP_CODE_SR_MASK | 8122 SFP_EEPROM_COMP_CODE_LR_MASK | 8123 SFP_EEPROM_COMP_CODE_LRM_MASK)) == 0) { 8124 DP(NETIF_MSG_LINK, "1G SFP module detected\n"); 8125 gport = params->port; 8126 phy->media_type = ETH_PHY_SFP_1G_FIBER; 8127 if (phy->req_line_speed != SPEED_1000) { 8128 phy->req_line_speed = SPEED_1000; 8129 if (!CHIP_IS_E1x(bp)) { 8130 gport = BP_PATH(bp) + 8131 (params->port << 1); 8132 } 8133 netdev_err(bp->dev, 8134 "Warning: Link speed was forced to 1000Mbps. Current SFP module in port %d is not compliant with 10G Ethernet\n", 8135 gport); 8136 } 8137 } else { 8138 int idx, cfg_idx = 0; 8139 DP(NETIF_MSG_LINK, "10G Optic module detected\n"); 8140 for (idx = INT_PHY; idx < MAX_PHYS; idx++) { 8141 if (params->phy[idx].type == phy->type) { 8142 cfg_idx = LINK_CONFIG_IDX(idx); 8143 break; 8144 } 8145 } 8146 phy->media_type = ETH_PHY_SFPP_10G_FIBER; 8147 phy->req_line_speed = params->req_line_speed[cfg_idx]; 8148 } 8149 break; 8150 default: 8151 DP(NETIF_MSG_LINK, "Unable to determine module type 0x%x !!!\n", 8152 val[0]); 8153 return -EINVAL; 8154 } 8155 sync_offset = params->shmem_base + 8156 offsetof(struct shmem_region, 8157 dev_info.port_hw_config[params->port].media_type); 8158 media_types = REG_RD(bp, sync_offset); 8159 /* Update media type for non-PMF sync */ 8160 for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) { 8161 if (&(params->phy[phy_idx]) == phy) { 8162 media_types &= ~(PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK << 8163 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx)); 8164 media_types |= ((phy->media_type & 8165 PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) << 8166 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx)); 8167 break; 8168 } 8169 } 8170 REG_WR(bp, sync_offset, media_types); 8171 if (check_limiting_mode) { 8172 u8 options[SFP_EEPROM_OPTIONS_SIZE]; 8173 if (bnx2x_read_sfp_module_eeprom(phy, 8174 params, 8175 I2C_DEV_ADDR_A0, 8176 SFP_EEPROM_OPTIONS_ADDR, 8177 SFP_EEPROM_OPTIONS_SIZE, 8178 options) != 0) { 8179 DP(NETIF_MSG_LINK, 8180 "Failed to read Option field from module EEPROM\n"); 8181 return -EINVAL; 8182 } 8183 if ((options[0] & SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK)) 8184 *edc_mode = EDC_MODE_LINEAR; 8185 else 8186 *edc_mode = EDC_MODE_LIMITING; 8187 } 8188 DP(NETIF_MSG_LINK, "EDC mode is set to 0x%x\n", *edc_mode); 8189 return 0; 8190 } 8191 /* This function read the relevant field from the module (SFP+), and verify it 8192 * is compliant with this board 8193 */ 8194 static int bnx2x_verify_sfp_module(struct bnx2x_phy *phy, 8195 struct link_params *params) 8196 { 8197 struct bnx2x *bp = params->bp; 8198 u32 val, cmd; 8199 u32 fw_resp, fw_cmd_param; 8200 char vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE+1]; 8201 char vendor_pn[SFP_EEPROM_PART_NO_SIZE+1]; 8202 phy->flags &= ~FLAGS_SFP_NOT_APPROVED; 8203 val = REG_RD(bp, params->shmem_base + 8204 offsetof(struct shmem_region, dev_info. 8205 port_feature_config[params->port].config)); 8206 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == 8207 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT) { 8208 DP(NETIF_MSG_LINK, "NOT enforcing module verification\n"); 8209 return 0; 8210 } 8211 8212 if (params->feature_config_flags & 8213 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY) { 8214 /* Use specific phy request */ 8215 cmd = DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL; 8216 } else if (params->feature_config_flags & 8217 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY) { 8218 /* Use first phy request only in case of non-dual media*/ 8219 if (DUAL_MEDIA(params)) { 8220 DP(NETIF_MSG_LINK, 8221 "FW does not support OPT MDL verification\n"); 8222 return -EINVAL; 8223 } 8224 cmd = DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL; 8225 } else { 8226 /* No support in OPT MDL detection */ 8227 DP(NETIF_MSG_LINK, 8228 "FW does not support OPT MDL verification\n"); 8229 return -EINVAL; 8230 } 8231 8232 fw_cmd_param = FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl); 8233 fw_resp = bnx2x_fw_command(bp, cmd, fw_cmd_param); 8234 if (fw_resp == FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS) { 8235 DP(NETIF_MSG_LINK, "Approved module\n"); 8236 return 0; 8237 } 8238 8239 /* Format the warning message */ 8240 if (bnx2x_read_sfp_module_eeprom(phy, 8241 params, 8242 I2C_DEV_ADDR_A0, 8243 SFP_EEPROM_VENDOR_NAME_ADDR, 8244 SFP_EEPROM_VENDOR_NAME_SIZE, 8245 (u8 *)vendor_name)) 8246 vendor_name[0] = '\0'; 8247 else 8248 vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE] = '\0'; 8249 if (bnx2x_read_sfp_module_eeprom(phy, 8250 params, 8251 I2C_DEV_ADDR_A0, 8252 SFP_EEPROM_PART_NO_ADDR, 8253 SFP_EEPROM_PART_NO_SIZE, 8254 (u8 *)vendor_pn)) 8255 vendor_pn[0] = '\0'; 8256 else 8257 vendor_pn[SFP_EEPROM_PART_NO_SIZE] = '\0'; 8258 8259 netdev_err(bp->dev, "Warning: Unqualified SFP+ module detected," 8260 " Port %d from %s part number %s\n", 8261 params->port, vendor_name, vendor_pn); 8262 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) != 8263 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG) 8264 phy->flags |= FLAGS_SFP_NOT_APPROVED; 8265 return -EINVAL; 8266 } 8267 8268 static int bnx2x_wait_for_sfp_module_initialized(struct bnx2x_phy *phy, 8269 struct link_params *params) 8270 8271 { 8272 u8 val; 8273 int rc; 8274 struct bnx2x *bp = params->bp; 8275 u16 timeout; 8276 /* Initialization time after hot-plug may take up to 300ms for 8277 * some phys type ( e.g. JDSU ) 8278 */ 8279 8280 for (timeout = 0; timeout < 60; timeout++) { 8281 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) 8282 rc = bnx2x_warpcore_read_sfp_module_eeprom( 8283 phy, params, I2C_DEV_ADDR_A0, 1, 1, &val, 8284 1); 8285 else 8286 rc = bnx2x_read_sfp_module_eeprom(phy, params, 8287 I2C_DEV_ADDR_A0, 8288 1, 1, &val); 8289 if (rc == 0) { 8290 DP(NETIF_MSG_LINK, 8291 "SFP+ module initialization took %d ms\n", 8292 timeout * 5); 8293 return 0; 8294 } 8295 usleep_range(5000, 10000); 8296 } 8297 rc = bnx2x_read_sfp_module_eeprom(phy, params, I2C_DEV_ADDR_A0, 8298 1, 1, &val); 8299 return rc; 8300 } 8301 8302 static void bnx2x_8727_power_module(struct bnx2x *bp, 8303 struct bnx2x_phy *phy, 8304 u8 is_power_up) { 8305 /* Make sure GPIOs are not using for LED mode */ 8306 u16 val; 8307 /* In the GPIO register, bit 4 is use to determine if the GPIOs are 8308 * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for 8309 * output 8310 * Bits 0-1 determine the GPIOs value for OUTPUT in case bit 4 val is 0 8311 * Bits 8-9 determine the GPIOs value for INPUT in case bit 4 val is 1 8312 * where the 1st bit is the over-current(only input), and 2nd bit is 8313 * for power( only output ) 8314 * 8315 * In case of NOC feature is disabled and power is up, set GPIO control 8316 * as input to enable listening of over-current indication 8317 */ 8318 if (phy->flags & FLAGS_NOC) 8319 return; 8320 if (is_power_up) 8321 val = (1<<4); 8322 else 8323 /* Set GPIO control to OUTPUT, and set the power bit 8324 * to according to the is_power_up 8325 */ 8326 val = (1<<1); 8327 8328 bnx2x_cl45_write(bp, phy, 8329 MDIO_PMA_DEVAD, 8330 MDIO_PMA_REG_8727_GPIO_CTRL, 8331 val); 8332 } 8333 8334 static int bnx2x_8726_set_limiting_mode(struct bnx2x *bp, 8335 struct bnx2x_phy *phy, 8336 u16 edc_mode) 8337 { 8338 u16 cur_limiting_mode; 8339 8340 bnx2x_cl45_read(bp, phy, 8341 MDIO_PMA_DEVAD, 8342 MDIO_PMA_REG_ROM_VER2, 8343 &cur_limiting_mode); 8344 DP(NETIF_MSG_LINK, "Current Limiting mode is 0x%x\n", 8345 cur_limiting_mode); 8346 8347 if (edc_mode == EDC_MODE_LIMITING) { 8348 DP(NETIF_MSG_LINK, "Setting LIMITING MODE\n"); 8349 bnx2x_cl45_write(bp, phy, 8350 MDIO_PMA_DEVAD, 8351 MDIO_PMA_REG_ROM_VER2, 8352 EDC_MODE_LIMITING); 8353 } else { /* LRM mode ( default )*/ 8354 8355 DP(NETIF_MSG_LINK, "Setting LRM MODE\n"); 8356 8357 /* Changing to LRM mode takes quite few seconds. So do it only 8358 * if current mode is limiting (default is LRM) 8359 */ 8360 if (cur_limiting_mode != EDC_MODE_LIMITING) 8361 return 0; 8362 8363 bnx2x_cl45_write(bp, phy, 8364 MDIO_PMA_DEVAD, 8365 MDIO_PMA_REG_LRM_MODE, 8366 0); 8367 bnx2x_cl45_write(bp, phy, 8368 MDIO_PMA_DEVAD, 8369 MDIO_PMA_REG_ROM_VER2, 8370 0x128); 8371 bnx2x_cl45_write(bp, phy, 8372 MDIO_PMA_DEVAD, 8373 MDIO_PMA_REG_MISC_CTRL0, 8374 0x4008); 8375 bnx2x_cl45_write(bp, phy, 8376 MDIO_PMA_DEVAD, 8377 MDIO_PMA_REG_LRM_MODE, 8378 0xaaaa); 8379 } 8380 return 0; 8381 } 8382 8383 static int bnx2x_8727_set_limiting_mode(struct bnx2x *bp, 8384 struct bnx2x_phy *phy, 8385 u16 edc_mode) 8386 { 8387 u16 phy_identifier; 8388 u16 rom_ver2_val; 8389 bnx2x_cl45_read(bp, phy, 8390 MDIO_PMA_DEVAD, 8391 MDIO_PMA_REG_PHY_IDENTIFIER, 8392 &phy_identifier); 8393 8394 bnx2x_cl45_write(bp, phy, 8395 MDIO_PMA_DEVAD, 8396 MDIO_PMA_REG_PHY_IDENTIFIER, 8397 (phy_identifier & ~(1<<9))); 8398 8399 bnx2x_cl45_read(bp, phy, 8400 MDIO_PMA_DEVAD, 8401 MDIO_PMA_REG_ROM_VER2, 8402 &rom_ver2_val); 8403 /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */ 8404 bnx2x_cl45_write(bp, phy, 8405 MDIO_PMA_DEVAD, 8406 MDIO_PMA_REG_ROM_VER2, 8407 (rom_ver2_val & 0xff00) | (edc_mode & 0x00ff)); 8408 8409 bnx2x_cl45_write(bp, phy, 8410 MDIO_PMA_DEVAD, 8411 MDIO_PMA_REG_PHY_IDENTIFIER, 8412 (phy_identifier | (1<<9))); 8413 8414 return 0; 8415 } 8416 8417 static void bnx2x_8727_specific_func(struct bnx2x_phy *phy, 8418 struct link_params *params, 8419 u32 action) 8420 { 8421 struct bnx2x *bp = params->bp; 8422 u16 val; 8423 switch (action) { 8424 case DISABLE_TX: 8425 bnx2x_sfp_set_transmitter(params, phy, 0); 8426 break; 8427 case ENABLE_TX: 8428 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED)) 8429 bnx2x_sfp_set_transmitter(params, phy, 1); 8430 break; 8431 case PHY_INIT: 8432 bnx2x_cl45_write(bp, phy, 8433 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, 8434 (1<<2) | (1<<5)); 8435 bnx2x_cl45_write(bp, phy, 8436 MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL, 8437 0); 8438 bnx2x_cl45_write(bp, phy, 8439 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0006); 8440 /* Make MOD_ABS give interrupt on change */ 8441 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 8442 MDIO_PMA_REG_8727_PCS_OPT_CTRL, 8443 &val); 8444 val |= (1<<12); 8445 if (phy->flags & FLAGS_NOC) 8446 val |= (3<<5); 8447 /* Set 8727 GPIOs to input to allow reading from the 8727 GPIO0 8448 * status which reflect SFP+ module over-current 8449 */ 8450 if (!(phy->flags & FLAGS_NOC)) 8451 val &= 0xff8f; /* Reset bits 4-6 */ 8452 bnx2x_cl45_write(bp, phy, 8453 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL, 8454 val); 8455 break; 8456 default: 8457 DP(NETIF_MSG_LINK, "Function 0x%x not supported by 8727\n", 8458 action); 8459 return; 8460 } 8461 } 8462 8463 static void bnx2x_set_e1e2_module_fault_led(struct link_params *params, 8464 u8 gpio_mode) 8465 { 8466 struct bnx2x *bp = params->bp; 8467 8468 u32 fault_led_gpio = REG_RD(bp, params->shmem_base + 8469 offsetof(struct shmem_region, 8470 dev_info.port_hw_config[params->port].sfp_ctrl)) & 8471 PORT_HW_CFG_FAULT_MODULE_LED_MASK; 8472 switch (fault_led_gpio) { 8473 case PORT_HW_CFG_FAULT_MODULE_LED_DISABLED: 8474 return; 8475 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO0: 8476 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO1: 8477 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO2: 8478 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO3: 8479 { 8480 u8 gpio_port = bnx2x_get_gpio_port(params); 8481 u16 gpio_pin = fault_led_gpio - 8482 PORT_HW_CFG_FAULT_MODULE_LED_GPIO0; 8483 DP(NETIF_MSG_LINK, "Set fault module-detected led " 8484 "pin %x port %x mode %x\n", 8485 gpio_pin, gpio_port, gpio_mode); 8486 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port); 8487 } 8488 break; 8489 default: 8490 DP(NETIF_MSG_LINK, "Error: Invalid fault led mode 0x%x\n", 8491 fault_led_gpio); 8492 } 8493 } 8494 8495 static void bnx2x_set_e3_module_fault_led(struct link_params *params, 8496 u8 gpio_mode) 8497 { 8498 u32 pin_cfg; 8499 u8 port = params->port; 8500 struct bnx2x *bp = params->bp; 8501 pin_cfg = (REG_RD(bp, params->shmem_base + 8502 offsetof(struct shmem_region, 8503 dev_info.port_hw_config[port].e3_sfp_ctrl)) & 8504 PORT_HW_CFG_E3_FAULT_MDL_LED_MASK) >> 8505 PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT; 8506 DP(NETIF_MSG_LINK, "Setting Fault LED to %d using pin cfg %d\n", 8507 gpio_mode, pin_cfg); 8508 bnx2x_set_cfg_pin(bp, pin_cfg, gpio_mode); 8509 } 8510 8511 static void bnx2x_set_sfp_module_fault_led(struct link_params *params, 8512 u8 gpio_mode) 8513 { 8514 struct bnx2x *bp = params->bp; 8515 DP(NETIF_MSG_LINK, "Setting SFP+ module fault LED to %d\n", gpio_mode); 8516 if (CHIP_IS_E3(bp)) { 8517 /* Low ==> if SFP+ module is supported otherwise 8518 * High ==> if SFP+ module is not on the approved vendor list 8519 */ 8520 bnx2x_set_e3_module_fault_led(params, gpio_mode); 8521 } else 8522 bnx2x_set_e1e2_module_fault_led(params, gpio_mode); 8523 } 8524 8525 static void bnx2x_warpcore_hw_reset(struct bnx2x_phy *phy, 8526 struct link_params *params) 8527 { 8528 struct bnx2x *bp = params->bp; 8529 bnx2x_warpcore_power_module(params, 0); 8530 /* Put Warpcore in low power mode */ 8531 REG_WR(bp, MISC_REG_WC0_RESET, 0x0c0e); 8532 8533 /* Put LCPLL in low power mode */ 8534 REG_WR(bp, MISC_REG_LCPLL_E40_PWRDWN, 1); 8535 REG_WR(bp, MISC_REG_LCPLL_E40_RESETB_ANA, 0); 8536 REG_WR(bp, MISC_REG_LCPLL_E40_RESETB_DIG, 0); 8537 } 8538 8539 static void bnx2x_power_sfp_module(struct link_params *params, 8540 struct bnx2x_phy *phy, 8541 u8 power) 8542 { 8543 struct bnx2x *bp = params->bp; 8544 DP(NETIF_MSG_LINK, "Setting SFP+ power to %x\n", power); 8545 8546 switch (phy->type) { 8547 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: 8548 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722: 8549 bnx2x_8727_power_module(params->bp, phy, power); 8550 break; 8551 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT: 8552 bnx2x_warpcore_power_module(params, power); 8553 break; 8554 default: 8555 break; 8556 } 8557 } 8558 static void bnx2x_warpcore_set_limiting_mode(struct link_params *params, 8559 struct bnx2x_phy *phy, 8560 u16 edc_mode) 8561 { 8562 u16 val = 0; 8563 u16 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT; 8564 struct bnx2x *bp = params->bp; 8565 8566 u8 lane = bnx2x_get_warpcore_lane(phy, params); 8567 /* This is a global register which controls all lanes */ 8568 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 8569 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val); 8570 val &= ~(0xf << (lane << 2)); 8571 8572 switch (edc_mode) { 8573 case EDC_MODE_LINEAR: 8574 case EDC_MODE_LIMITING: 8575 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT; 8576 break; 8577 case EDC_MODE_PASSIVE_DAC: 8578 case EDC_MODE_ACTIVE_DAC: 8579 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC; 8580 break; 8581 default: 8582 break; 8583 } 8584 8585 val |= (mode << (lane << 2)); 8586 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 8587 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, val); 8588 /* A must read */ 8589 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 8590 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val); 8591 8592 /* Restart microcode to re-read the new mode */ 8593 bnx2x_warpcore_reset_lane(bp, phy, 1); 8594 bnx2x_warpcore_reset_lane(bp, phy, 0); 8595 8596 } 8597 8598 static void bnx2x_set_limiting_mode(struct link_params *params, 8599 struct bnx2x_phy *phy, 8600 u16 edc_mode) 8601 { 8602 switch (phy->type) { 8603 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: 8604 bnx2x_8726_set_limiting_mode(params->bp, phy, edc_mode); 8605 break; 8606 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: 8607 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722: 8608 bnx2x_8727_set_limiting_mode(params->bp, phy, edc_mode); 8609 break; 8610 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT: 8611 bnx2x_warpcore_set_limiting_mode(params, phy, edc_mode); 8612 break; 8613 } 8614 } 8615 8616 static int bnx2x_sfp_module_detection(struct bnx2x_phy *phy, 8617 struct link_params *params) 8618 { 8619 struct bnx2x *bp = params->bp; 8620 u16 edc_mode; 8621 int rc = 0; 8622 8623 u32 val = REG_RD(bp, params->shmem_base + 8624 offsetof(struct shmem_region, dev_info. 8625 port_feature_config[params->port].config)); 8626 /* Enabled transmitter by default */ 8627 bnx2x_sfp_set_transmitter(params, phy, 1); 8628 DP(NETIF_MSG_LINK, "SFP+ module plugged in/out detected on port %d\n", 8629 params->port); 8630 /* Power up module */ 8631 bnx2x_power_sfp_module(params, phy, 1); 8632 if (bnx2x_get_edc_mode(phy, params, &edc_mode) != 0) { 8633 DP(NETIF_MSG_LINK, "Failed to get valid module type\n"); 8634 return -EINVAL; 8635 } else if (bnx2x_verify_sfp_module(phy, params) != 0) { 8636 /* Check SFP+ module compatibility */ 8637 DP(NETIF_MSG_LINK, "Module verification failed!!\n"); 8638 rc = -EINVAL; 8639 /* Turn on fault module-detected led */ 8640 bnx2x_set_sfp_module_fault_led(params, 8641 MISC_REGISTERS_GPIO_HIGH); 8642 8643 /* Check if need to power down the SFP+ module */ 8644 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == 8645 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN) { 8646 DP(NETIF_MSG_LINK, "Shutdown SFP+ module!!\n"); 8647 bnx2x_power_sfp_module(params, phy, 0); 8648 return rc; 8649 } 8650 } else { 8651 /* Turn off fault module-detected led */ 8652 bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_LOW); 8653 } 8654 8655 /* Check and set limiting mode / LRM mode on 8726. On 8727 it 8656 * is done automatically 8657 */ 8658 bnx2x_set_limiting_mode(params, phy, edc_mode); 8659 8660 /* Disable transmit for this module if the module is not approved, and 8661 * laser needs to be disabled. 8662 */ 8663 if ((rc) && 8664 ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == 8665 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)) 8666 bnx2x_sfp_set_transmitter(params, phy, 0); 8667 8668 return rc; 8669 } 8670 8671 void bnx2x_handle_module_detect_int(struct link_params *params) 8672 { 8673 struct bnx2x *bp = params->bp; 8674 struct bnx2x_phy *phy; 8675 u32 gpio_val; 8676 u8 gpio_num, gpio_port; 8677 if (CHIP_IS_E3(bp)) { 8678 phy = ¶ms->phy[INT_PHY]; 8679 /* Always enable TX laser,will be disabled in case of fault */ 8680 bnx2x_sfp_set_transmitter(params, phy, 1); 8681 } else { 8682 phy = ¶ms->phy[EXT_PHY1]; 8683 } 8684 if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id, params->shmem_base, 8685 params->port, &gpio_num, &gpio_port) == 8686 -EINVAL) { 8687 DP(NETIF_MSG_LINK, "Failed to get MOD_ABS interrupt config\n"); 8688 return; 8689 } 8690 8691 /* Set valid module led off */ 8692 bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_HIGH); 8693 8694 /* Get current gpio val reflecting module plugged in / out*/ 8695 gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port); 8696 8697 /* Call the handling function in case module is detected */ 8698 if (gpio_val == 0) { 8699 bnx2x_set_mdio_emac_per_phy(bp, params); 8700 bnx2x_set_aer_mmd(params, phy); 8701 8702 bnx2x_power_sfp_module(params, phy, 1); 8703 bnx2x_set_gpio_int(bp, gpio_num, 8704 MISC_REGISTERS_GPIO_INT_OUTPUT_CLR, 8705 gpio_port); 8706 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0) { 8707 bnx2x_sfp_module_detection(phy, params); 8708 if (CHIP_IS_E3(bp)) { 8709 u16 rx_tx_in_reset; 8710 /* In case WC is out of reset, reconfigure the 8711 * link speed while taking into account 1G 8712 * module limitation. 8713 */ 8714 bnx2x_cl45_read(bp, phy, 8715 MDIO_WC_DEVAD, 8716 MDIO_WC_REG_DIGITAL5_MISC6, 8717 &rx_tx_in_reset); 8718 if ((!rx_tx_in_reset) && 8719 (params->link_flags & 8720 PHY_INITIALIZED)) { 8721 bnx2x_warpcore_reset_lane(bp, phy, 1); 8722 bnx2x_warpcore_config_sfi(phy, params); 8723 bnx2x_warpcore_reset_lane(bp, phy, 0); 8724 } 8725 } 8726 } else { 8727 DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n"); 8728 } 8729 } else { 8730 bnx2x_set_gpio_int(bp, gpio_num, 8731 MISC_REGISTERS_GPIO_INT_OUTPUT_SET, 8732 gpio_port); 8733 /* Module was plugged out. 8734 * Disable transmit for this module 8735 */ 8736 phy->media_type = ETH_PHY_NOT_PRESENT; 8737 } 8738 } 8739 8740 /******************************************************************/ 8741 /* Used by 8706 and 8727 */ 8742 /******************************************************************/ 8743 static void bnx2x_sfp_mask_fault(struct bnx2x *bp, 8744 struct bnx2x_phy *phy, 8745 u16 alarm_status_offset, 8746 u16 alarm_ctrl_offset) 8747 { 8748 u16 alarm_status, val; 8749 bnx2x_cl45_read(bp, phy, 8750 MDIO_PMA_DEVAD, alarm_status_offset, 8751 &alarm_status); 8752 bnx2x_cl45_read(bp, phy, 8753 MDIO_PMA_DEVAD, alarm_status_offset, 8754 &alarm_status); 8755 /* Mask or enable the fault event. */ 8756 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, &val); 8757 if (alarm_status & (1<<0)) 8758 val &= ~(1<<0); 8759 else 8760 val |= (1<<0); 8761 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, val); 8762 } 8763 /******************************************************************/ 8764 /* common BCM8706/BCM8726 PHY SECTION */ 8765 /******************************************************************/ 8766 static u8 bnx2x_8706_8726_read_status(struct bnx2x_phy *phy, 8767 struct link_params *params, 8768 struct link_vars *vars) 8769 { 8770 u8 link_up = 0; 8771 u16 val1, val2, rx_sd, pcs_status; 8772 struct bnx2x *bp = params->bp; 8773 DP(NETIF_MSG_LINK, "XGXS 8706/8726\n"); 8774 /* Clear RX Alarm*/ 8775 bnx2x_cl45_read(bp, phy, 8776 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2); 8777 8778 bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT, 8779 MDIO_PMA_LASI_TXCTRL); 8780 8781 /* Clear LASI indication*/ 8782 bnx2x_cl45_read(bp, phy, 8783 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1); 8784 bnx2x_cl45_read(bp, phy, 8785 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2); 8786 DP(NETIF_MSG_LINK, "8706/8726 LASI status 0x%x--> 0x%x\n", val1, val2); 8787 8788 bnx2x_cl45_read(bp, phy, 8789 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd); 8790 bnx2x_cl45_read(bp, phy, 8791 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &pcs_status); 8792 bnx2x_cl45_read(bp, phy, 8793 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2); 8794 bnx2x_cl45_read(bp, phy, 8795 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2); 8796 8797 DP(NETIF_MSG_LINK, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps" 8798 " link_status 0x%x\n", rx_sd, pcs_status, val2); 8799 /* Link is up if both bit 0 of pmd_rx_sd and bit 0 of pcs_status 8800 * are set, or if the autoneg bit 1 is set 8801 */ 8802 link_up = ((rx_sd & pcs_status & 0x1) || (val2 & (1<<1))); 8803 if (link_up) { 8804 if (val2 & (1<<1)) 8805 vars->line_speed = SPEED_1000; 8806 else 8807 vars->line_speed = SPEED_10000; 8808 bnx2x_ext_phy_resolve_fc(phy, params, vars); 8809 vars->duplex = DUPLEX_FULL; 8810 } 8811 8812 /* Capture 10G link fault. Read twice to clear stale value. */ 8813 if (vars->line_speed == SPEED_10000) { 8814 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 8815 MDIO_PMA_LASI_TXSTAT, &val1); 8816 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 8817 MDIO_PMA_LASI_TXSTAT, &val1); 8818 if (val1 & (1<<0)) 8819 vars->fault_detected = 1; 8820 } 8821 8822 return link_up; 8823 } 8824 8825 /******************************************************************/ 8826 /* BCM8706 PHY SECTION */ 8827 /******************************************************************/ 8828 static u8 bnx2x_8706_config_init(struct bnx2x_phy *phy, 8829 struct link_params *params, 8830 struct link_vars *vars) 8831 { 8832 u32 tx_en_mode; 8833 u16 cnt, val, tmp1; 8834 struct bnx2x *bp = params->bp; 8835 8836 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 8837 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); 8838 /* HW reset */ 8839 bnx2x_ext_phy_hw_reset(bp, params->port); 8840 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040); 8841 bnx2x_wait_reset_complete(bp, phy, params); 8842 8843 /* Wait until fw is loaded */ 8844 for (cnt = 0; cnt < 100; cnt++) { 8845 bnx2x_cl45_read(bp, phy, 8846 MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER1, &val); 8847 if (val) 8848 break; 8849 usleep_range(10000, 20000); 8850 } 8851 DP(NETIF_MSG_LINK, "XGXS 8706 is initialized after %d ms\n", cnt); 8852 if ((params->feature_config_flags & 8853 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) { 8854 u8 i; 8855 u16 reg; 8856 for (i = 0; i < 4; i++) { 8857 reg = MDIO_XS_8706_REG_BANK_RX0 + 8858 i*(MDIO_XS_8706_REG_BANK_RX1 - 8859 MDIO_XS_8706_REG_BANK_RX0); 8860 bnx2x_cl45_read(bp, phy, MDIO_XS_DEVAD, reg, &val); 8861 /* Clear first 3 bits of the control */ 8862 val &= ~0x7; 8863 /* Set control bits according to configuration */ 8864 val |= (phy->rx_preemphasis[i] & 0x7); 8865 DP(NETIF_MSG_LINK, "Setting RX Equalizer to BCM8706" 8866 " reg 0x%x <-- val 0x%x\n", reg, val); 8867 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, reg, val); 8868 } 8869 } 8870 /* Force speed */ 8871 if (phy->req_line_speed == SPEED_10000) { 8872 DP(NETIF_MSG_LINK, "XGXS 8706 force 10Gbps\n"); 8873 8874 bnx2x_cl45_write(bp, phy, 8875 MDIO_PMA_DEVAD, 8876 MDIO_PMA_REG_DIGITAL_CTRL, 0x400); 8877 bnx2x_cl45_write(bp, phy, 8878 MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL, 8879 0); 8880 /* Arm LASI for link and Tx fault. */ 8881 bnx2x_cl45_write(bp, phy, 8882 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 3); 8883 } else { 8884 /* Force 1Gbps using autoneg with 1G advertisement */ 8885 8886 /* Allow CL37 through CL73 */ 8887 DP(NETIF_MSG_LINK, "XGXS 8706 AutoNeg\n"); 8888 bnx2x_cl45_write(bp, phy, 8889 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c); 8890 8891 /* Enable Full-Duplex advertisement on CL37 */ 8892 bnx2x_cl45_write(bp, phy, 8893 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LP, 0x0020); 8894 /* Enable CL37 AN */ 8895 bnx2x_cl45_write(bp, phy, 8896 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000); 8897 /* 1G support */ 8898 bnx2x_cl45_write(bp, phy, 8899 MDIO_AN_DEVAD, MDIO_AN_REG_ADV, (1<<5)); 8900 8901 /* Enable clause 73 AN */ 8902 bnx2x_cl45_write(bp, phy, 8903 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200); 8904 bnx2x_cl45_write(bp, phy, 8905 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, 8906 0x0400); 8907 bnx2x_cl45_write(bp, phy, 8908 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 8909 0x0004); 8910 } 8911 bnx2x_save_bcm_spirom_ver(bp, phy, params->port); 8912 8913 /* If TX Laser is controlled by GPIO_0, do not let PHY go into low 8914 * power mode, if TX Laser is disabled 8915 */ 8916 8917 tx_en_mode = REG_RD(bp, params->shmem_base + 8918 offsetof(struct shmem_region, 8919 dev_info.port_hw_config[params->port].sfp_ctrl)) 8920 & PORT_HW_CFG_TX_LASER_MASK; 8921 8922 if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) { 8923 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n"); 8924 bnx2x_cl45_read(bp, phy, 8925 MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, &tmp1); 8926 tmp1 |= 0x1; 8927 bnx2x_cl45_write(bp, phy, 8928 MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, tmp1); 8929 } 8930 8931 return 0; 8932 } 8933 8934 static int bnx2x_8706_read_status(struct bnx2x_phy *phy, 8935 struct link_params *params, 8936 struct link_vars *vars) 8937 { 8938 return bnx2x_8706_8726_read_status(phy, params, vars); 8939 } 8940 8941 /******************************************************************/ 8942 /* BCM8726 PHY SECTION */ 8943 /******************************************************************/ 8944 static void bnx2x_8726_config_loopback(struct bnx2x_phy *phy, 8945 struct link_params *params) 8946 { 8947 struct bnx2x *bp = params->bp; 8948 DP(NETIF_MSG_LINK, "PMA/PMD ext_phy_loopback: 8726\n"); 8949 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001); 8950 } 8951 8952 static void bnx2x_8726_external_rom_boot(struct bnx2x_phy *phy, 8953 struct link_params *params) 8954 { 8955 struct bnx2x *bp = params->bp; 8956 /* Need to wait 100ms after reset */ 8957 msleep(100); 8958 8959 /* Micro controller re-boot */ 8960 bnx2x_cl45_write(bp, phy, 8961 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x018B); 8962 8963 /* Set soft reset */ 8964 bnx2x_cl45_write(bp, phy, 8965 MDIO_PMA_DEVAD, 8966 MDIO_PMA_REG_GEN_CTRL, 8967 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET); 8968 8969 bnx2x_cl45_write(bp, phy, 8970 MDIO_PMA_DEVAD, 8971 MDIO_PMA_REG_MISC_CTRL1, 0x0001); 8972 8973 bnx2x_cl45_write(bp, phy, 8974 MDIO_PMA_DEVAD, 8975 MDIO_PMA_REG_GEN_CTRL, 8976 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP); 8977 8978 /* Wait for 150ms for microcode load */ 8979 msleep(150); 8980 8981 /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */ 8982 bnx2x_cl45_write(bp, phy, 8983 MDIO_PMA_DEVAD, 8984 MDIO_PMA_REG_MISC_CTRL1, 0x0000); 8985 8986 msleep(200); 8987 bnx2x_save_bcm_spirom_ver(bp, phy, params->port); 8988 } 8989 8990 static u8 bnx2x_8726_read_status(struct bnx2x_phy *phy, 8991 struct link_params *params, 8992 struct link_vars *vars) 8993 { 8994 struct bnx2x *bp = params->bp; 8995 u16 val1; 8996 u8 link_up = bnx2x_8706_8726_read_status(phy, params, vars); 8997 if (link_up) { 8998 bnx2x_cl45_read(bp, phy, 8999 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 9000 &val1); 9001 if (val1 & (1<<15)) { 9002 DP(NETIF_MSG_LINK, "Tx is disabled\n"); 9003 link_up = 0; 9004 vars->line_speed = 0; 9005 } 9006 } 9007 return link_up; 9008 } 9009 9010 9011 static int bnx2x_8726_config_init(struct bnx2x_phy *phy, 9012 struct link_params *params, 9013 struct link_vars *vars) 9014 { 9015 struct bnx2x *bp = params->bp; 9016 DP(NETIF_MSG_LINK, "Initializing BCM8726\n"); 9017 9018 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15); 9019 bnx2x_wait_reset_complete(bp, phy, params); 9020 9021 bnx2x_8726_external_rom_boot(phy, params); 9022 9023 /* Need to call module detected on initialization since the module 9024 * detection triggered by actual module insertion might occur before 9025 * driver is loaded, and when driver is loaded, it reset all 9026 * registers, including the transmitter 9027 */ 9028 bnx2x_sfp_module_detection(phy, params); 9029 9030 if (phy->req_line_speed == SPEED_1000) { 9031 DP(NETIF_MSG_LINK, "Setting 1G force\n"); 9032 bnx2x_cl45_write(bp, phy, 9033 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40); 9034 bnx2x_cl45_write(bp, phy, 9035 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD); 9036 bnx2x_cl45_write(bp, phy, 9037 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x5); 9038 bnx2x_cl45_write(bp, phy, 9039 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, 9040 0x400); 9041 } else if ((phy->req_line_speed == SPEED_AUTO_NEG) && 9042 (phy->speed_cap_mask & 9043 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) && 9044 ((phy->speed_cap_mask & 9045 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) != 9046 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) { 9047 DP(NETIF_MSG_LINK, "Setting 1G clause37\n"); 9048 /* Set Flow control */ 9049 bnx2x_ext_phy_set_pause(params, phy, vars); 9050 bnx2x_cl45_write(bp, phy, 9051 MDIO_AN_DEVAD, MDIO_AN_REG_ADV, 0x20); 9052 bnx2x_cl45_write(bp, phy, 9053 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c); 9054 bnx2x_cl45_write(bp, phy, 9055 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, 0x0020); 9056 bnx2x_cl45_write(bp, phy, 9057 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000); 9058 bnx2x_cl45_write(bp, phy, 9059 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200); 9060 /* Enable RX-ALARM control to receive interrupt for 1G speed 9061 * change 9062 */ 9063 bnx2x_cl45_write(bp, phy, 9064 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x4); 9065 bnx2x_cl45_write(bp, phy, 9066 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, 9067 0x400); 9068 9069 } else { /* Default 10G. Set only LASI control */ 9070 bnx2x_cl45_write(bp, phy, 9071 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 1); 9072 } 9073 9074 /* Set TX PreEmphasis if needed */ 9075 if ((params->feature_config_flags & 9076 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) { 9077 DP(NETIF_MSG_LINK, 9078 "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n", 9079 phy->tx_preemphasis[0], 9080 phy->tx_preemphasis[1]); 9081 bnx2x_cl45_write(bp, phy, 9082 MDIO_PMA_DEVAD, 9083 MDIO_PMA_REG_8726_TX_CTRL1, 9084 phy->tx_preemphasis[0]); 9085 9086 bnx2x_cl45_write(bp, phy, 9087 MDIO_PMA_DEVAD, 9088 MDIO_PMA_REG_8726_TX_CTRL2, 9089 phy->tx_preemphasis[1]); 9090 } 9091 9092 return 0; 9093 9094 } 9095 9096 static void bnx2x_8726_link_reset(struct bnx2x_phy *phy, 9097 struct link_params *params) 9098 { 9099 struct bnx2x *bp = params->bp; 9100 DP(NETIF_MSG_LINK, "bnx2x_8726_link_reset port %d\n", params->port); 9101 /* Set serial boot control for external load */ 9102 bnx2x_cl45_write(bp, phy, 9103 MDIO_PMA_DEVAD, 9104 MDIO_PMA_REG_GEN_CTRL, 0x0001); 9105 } 9106 9107 /******************************************************************/ 9108 /* BCM8727 PHY SECTION */ 9109 /******************************************************************/ 9110 9111 static void bnx2x_8727_set_link_led(struct bnx2x_phy *phy, 9112 struct link_params *params, u8 mode) 9113 { 9114 struct bnx2x *bp = params->bp; 9115 u16 led_mode_bitmask = 0; 9116 u16 gpio_pins_bitmask = 0; 9117 u16 val; 9118 /* Only NOC flavor requires to set the LED specifically */ 9119 if (!(phy->flags & FLAGS_NOC)) 9120 return; 9121 switch (mode) { 9122 case LED_MODE_FRONT_PANEL_OFF: 9123 case LED_MODE_OFF: 9124 led_mode_bitmask = 0; 9125 gpio_pins_bitmask = 0x03; 9126 break; 9127 case LED_MODE_ON: 9128 led_mode_bitmask = 0; 9129 gpio_pins_bitmask = 0x02; 9130 break; 9131 case LED_MODE_OPER: 9132 led_mode_bitmask = 0x60; 9133 gpio_pins_bitmask = 0x11; 9134 break; 9135 } 9136 bnx2x_cl45_read(bp, phy, 9137 MDIO_PMA_DEVAD, 9138 MDIO_PMA_REG_8727_PCS_OPT_CTRL, 9139 &val); 9140 val &= 0xff8f; 9141 val |= led_mode_bitmask; 9142 bnx2x_cl45_write(bp, phy, 9143 MDIO_PMA_DEVAD, 9144 MDIO_PMA_REG_8727_PCS_OPT_CTRL, 9145 val); 9146 bnx2x_cl45_read(bp, phy, 9147 MDIO_PMA_DEVAD, 9148 MDIO_PMA_REG_8727_GPIO_CTRL, 9149 &val); 9150 val &= 0xffe0; 9151 val |= gpio_pins_bitmask; 9152 bnx2x_cl45_write(bp, phy, 9153 MDIO_PMA_DEVAD, 9154 MDIO_PMA_REG_8727_GPIO_CTRL, 9155 val); 9156 } 9157 static void bnx2x_8727_hw_reset(struct bnx2x_phy *phy, 9158 struct link_params *params) { 9159 u32 swap_val, swap_override; 9160 u8 port; 9161 /* The PHY reset is controlled by GPIO 1. Fake the port number 9162 * to cancel the swap done in set_gpio() 9163 */ 9164 struct bnx2x *bp = params->bp; 9165 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); 9166 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); 9167 port = (swap_val && swap_override) ^ 1; 9168 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, 9169 MISC_REGISTERS_GPIO_OUTPUT_LOW, port); 9170 } 9171 9172 static void bnx2x_8727_config_speed(struct bnx2x_phy *phy, 9173 struct link_params *params) 9174 { 9175 struct bnx2x *bp = params->bp; 9176 u16 tmp1, val; 9177 /* Set option 1G speed */ 9178 if ((phy->req_line_speed == SPEED_1000) || 9179 (phy->media_type == ETH_PHY_SFP_1G_FIBER)) { 9180 DP(NETIF_MSG_LINK, "Setting 1G force\n"); 9181 bnx2x_cl45_write(bp, phy, 9182 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40); 9183 bnx2x_cl45_write(bp, phy, 9184 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD); 9185 bnx2x_cl45_read(bp, phy, 9186 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, &tmp1); 9187 DP(NETIF_MSG_LINK, "1.7 = 0x%x\n", tmp1); 9188 /* Power down the XAUI until link is up in case of dual-media 9189 * and 1G 9190 */ 9191 if (DUAL_MEDIA(params)) { 9192 bnx2x_cl45_read(bp, phy, 9193 MDIO_PMA_DEVAD, 9194 MDIO_PMA_REG_8727_PCS_GP, &val); 9195 val |= (3<<10); 9196 bnx2x_cl45_write(bp, phy, 9197 MDIO_PMA_DEVAD, 9198 MDIO_PMA_REG_8727_PCS_GP, val); 9199 } 9200 } else if ((phy->req_line_speed == SPEED_AUTO_NEG) && 9201 ((phy->speed_cap_mask & 9202 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) && 9203 ((phy->speed_cap_mask & 9204 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) != 9205 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) { 9206 9207 DP(NETIF_MSG_LINK, "Setting 1G clause37\n"); 9208 bnx2x_cl45_write(bp, phy, 9209 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 0); 9210 bnx2x_cl45_write(bp, phy, 9211 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1300); 9212 } else { 9213 /* Since the 8727 has only single reset pin, need to set the 10G 9214 * registers although it is default 9215 */ 9216 bnx2x_cl45_write(bp, phy, 9217 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 9218 0x0020); 9219 bnx2x_cl45_write(bp, phy, 9220 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x0100); 9221 bnx2x_cl45_write(bp, phy, 9222 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040); 9223 bnx2x_cl45_write(bp, phy, 9224 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 9225 0x0008); 9226 } 9227 } 9228 9229 static int bnx2x_8727_config_init(struct bnx2x_phy *phy, 9230 struct link_params *params, 9231 struct link_vars *vars) 9232 { 9233 u32 tx_en_mode; 9234 u16 tmp1, mod_abs, tmp2; 9235 struct bnx2x *bp = params->bp; 9236 /* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */ 9237 9238 bnx2x_wait_reset_complete(bp, phy, params); 9239 9240 DP(NETIF_MSG_LINK, "Initializing BCM8727\n"); 9241 9242 bnx2x_8727_specific_func(phy, params, PHY_INIT); 9243 /* Initially configure MOD_ABS to interrupt when module is 9244 * presence( bit 8) 9245 */ 9246 bnx2x_cl45_read(bp, phy, 9247 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs); 9248 /* Set EDC off by setting OPTXLOS signal input to low (bit 9). 9249 * When the EDC is off it locks onto a reference clock and avoids 9250 * becoming 'lost' 9251 */ 9252 mod_abs &= ~(1<<8); 9253 if (!(phy->flags & FLAGS_NOC)) 9254 mod_abs &= ~(1<<9); 9255 bnx2x_cl45_write(bp, phy, 9256 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs); 9257 9258 /* Enable/Disable PHY transmitter output */ 9259 bnx2x_set_disable_pmd_transmit(params, phy, 0); 9260 9261 bnx2x_8727_power_module(bp, phy, 1); 9262 9263 bnx2x_cl45_read(bp, phy, 9264 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1); 9265 9266 bnx2x_cl45_read(bp, phy, 9267 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1); 9268 9269 bnx2x_8727_config_speed(phy, params); 9270 9271 9272 /* Set TX PreEmphasis if needed */ 9273 if ((params->feature_config_flags & 9274 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) { 9275 DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n", 9276 phy->tx_preemphasis[0], 9277 phy->tx_preemphasis[1]); 9278 bnx2x_cl45_write(bp, phy, 9279 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL1, 9280 phy->tx_preemphasis[0]); 9281 9282 bnx2x_cl45_write(bp, phy, 9283 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL2, 9284 phy->tx_preemphasis[1]); 9285 } 9286 9287 /* If TX Laser is controlled by GPIO_0, do not let PHY go into low 9288 * power mode, if TX Laser is disabled 9289 */ 9290 tx_en_mode = REG_RD(bp, params->shmem_base + 9291 offsetof(struct shmem_region, 9292 dev_info.port_hw_config[params->port].sfp_ctrl)) 9293 & PORT_HW_CFG_TX_LASER_MASK; 9294 9295 if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) { 9296 9297 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n"); 9298 bnx2x_cl45_read(bp, phy, 9299 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, &tmp2); 9300 tmp2 |= 0x1000; 9301 tmp2 &= 0xFFEF; 9302 bnx2x_cl45_write(bp, phy, 9303 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, tmp2); 9304 bnx2x_cl45_read(bp, phy, 9305 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 9306 &tmp2); 9307 bnx2x_cl45_write(bp, phy, 9308 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 9309 (tmp2 & 0x7fff)); 9310 } 9311 9312 return 0; 9313 } 9314 9315 static void bnx2x_8727_handle_mod_abs(struct bnx2x_phy *phy, 9316 struct link_params *params) 9317 { 9318 struct bnx2x *bp = params->bp; 9319 u16 mod_abs, rx_alarm_status; 9320 u32 val = REG_RD(bp, params->shmem_base + 9321 offsetof(struct shmem_region, dev_info. 9322 port_feature_config[params->port]. 9323 config)); 9324 bnx2x_cl45_read(bp, phy, 9325 MDIO_PMA_DEVAD, 9326 MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs); 9327 if (mod_abs & (1<<8)) { 9328 9329 /* Module is absent */ 9330 DP(NETIF_MSG_LINK, 9331 "MOD_ABS indication show module is absent\n"); 9332 phy->media_type = ETH_PHY_NOT_PRESENT; 9333 /* 1. Set mod_abs to detect next module 9334 * presence event 9335 * 2. Set EDC off by setting OPTXLOS signal input to low 9336 * (bit 9). 9337 * When the EDC is off it locks onto a reference clock and 9338 * avoids becoming 'lost'. 9339 */ 9340 mod_abs &= ~(1<<8); 9341 if (!(phy->flags & FLAGS_NOC)) 9342 mod_abs &= ~(1<<9); 9343 bnx2x_cl45_write(bp, phy, 9344 MDIO_PMA_DEVAD, 9345 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs); 9346 9347 /* Clear RX alarm since it stays up as long as 9348 * the mod_abs wasn't changed 9349 */ 9350 bnx2x_cl45_read(bp, phy, 9351 MDIO_PMA_DEVAD, 9352 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status); 9353 9354 } else { 9355 /* Module is present */ 9356 DP(NETIF_MSG_LINK, 9357 "MOD_ABS indication show module is present\n"); 9358 /* First disable transmitter, and if the module is ok, the 9359 * module_detection will enable it 9360 * 1. Set mod_abs to detect next module absent event ( bit 8) 9361 * 2. Restore the default polarity of the OPRXLOS signal and 9362 * this signal will then correctly indicate the presence or 9363 * absence of the Rx signal. (bit 9) 9364 */ 9365 mod_abs |= (1<<8); 9366 if (!(phy->flags & FLAGS_NOC)) 9367 mod_abs |= (1<<9); 9368 bnx2x_cl45_write(bp, phy, 9369 MDIO_PMA_DEVAD, 9370 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs); 9371 9372 /* Clear RX alarm since it stays up as long as the mod_abs 9373 * wasn't changed. This is need to be done before calling the 9374 * module detection, otherwise it will clear* the link update 9375 * alarm 9376 */ 9377 bnx2x_cl45_read(bp, phy, 9378 MDIO_PMA_DEVAD, 9379 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status); 9380 9381 9382 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == 9383 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER) 9384 bnx2x_sfp_set_transmitter(params, phy, 0); 9385 9386 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0) 9387 bnx2x_sfp_module_detection(phy, params); 9388 else 9389 DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n"); 9390 9391 /* Reconfigure link speed based on module type limitations */ 9392 bnx2x_8727_config_speed(phy, params); 9393 } 9394 9395 DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n", 9396 rx_alarm_status); 9397 /* No need to check link status in case of module plugged in/out */ 9398 } 9399 9400 static u8 bnx2x_8727_read_status(struct bnx2x_phy *phy, 9401 struct link_params *params, 9402 struct link_vars *vars) 9403 9404 { 9405 struct bnx2x *bp = params->bp; 9406 u8 link_up = 0, oc_port = params->port; 9407 u16 link_status = 0; 9408 u16 rx_alarm_status, lasi_ctrl, val1; 9409 9410 /* If PHY is not initialized, do not check link status */ 9411 bnx2x_cl45_read(bp, phy, 9412 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 9413 &lasi_ctrl); 9414 if (!lasi_ctrl) 9415 return 0; 9416 9417 /* Check the LASI on Rx */ 9418 bnx2x_cl45_read(bp, phy, 9419 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, 9420 &rx_alarm_status); 9421 vars->line_speed = 0; 9422 DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n", rx_alarm_status); 9423 9424 bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT, 9425 MDIO_PMA_LASI_TXCTRL); 9426 9427 bnx2x_cl45_read(bp, phy, 9428 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1); 9429 9430 DP(NETIF_MSG_LINK, "8727 LASI status 0x%x\n", val1); 9431 9432 /* Clear MSG-OUT */ 9433 bnx2x_cl45_read(bp, phy, 9434 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1); 9435 9436 /* If a module is present and there is need to check 9437 * for over current 9438 */ 9439 if (!(phy->flags & FLAGS_NOC) && !(rx_alarm_status & (1<<5))) { 9440 /* Check over-current using 8727 GPIO0 input*/ 9441 bnx2x_cl45_read(bp, phy, 9442 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL, 9443 &val1); 9444 9445 if ((val1 & (1<<8)) == 0) { 9446 if (!CHIP_IS_E1x(bp)) 9447 oc_port = BP_PATH(bp) + (params->port << 1); 9448 DP(NETIF_MSG_LINK, 9449 "8727 Power fault has been detected on port %d\n", 9450 oc_port); 9451 netdev_err(bp->dev, "Error: Power fault on Port %d has " 9452 "been detected and the power to " 9453 "that SFP+ module has been removed " 9454 "to prevent failure of the card. " 9455 "Please remove the SFP+ module and " 9456 "restart the system to clear this " 9457 "error.\n", 9458 oc_port); 9459 /* Disable all RX_ALARMs except for mod_abs */ 9460 bnx2x_cl45_write(bp, phy, 9461 MDIO_PMA_DEVAD, 9462 MDIO_PMA_LASI_RXCTRL, (1<<5)); 9463 9464 bnx2x_cl45_read(bp, phy, 9465 MDIO_PMA_DEVAD, 9466 MDIO_PMA_REG_PHY_IDENTIFIER, &val1); 9467 /* Wait for module_absent_event */ 9468 val1 |= (1<<8); 9469 bnx2x_cl45_write(bp, phy, 9470 MDIO_PMA_DEVAD, 9471 MDIO_PMA_REG_PHY_IDENTIFIER, val1); 9472 /* Clear RX alarm */ 9473 bnx2x_cl45_read(bp, phy, 9474 MDIO_PMA_DEVAD, 9475 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status); 9476 bnx2x_8727_power_module(params->bp, phy, 0); 9477 return 0; 9478 } 9479 } /* Over current check */ 9480 9481 /* When module absent bit is set, check module */ 9482 if (rx_alarm_status & (1<<5)) { 9483 bnx2x_8727_handle_mod_abs(phy, params); 9484 /* Enable all mod_abs and link detection bits */ 9485 bnx2x_cl45_write(bp, phy, 9486 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, 9487 ((1<<5) | (1<<2))); 9488 } 9489 9490 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED)) { 9491 DP(NETIF_MSG_LINK, "Enabling 8727 TX laser\n"); 9492 bnx2x_sfp_set_transmitter(params, phy, 1); 9493 } else { 9494 DP(NETIF_MSG_LINK, "Tx is disabled\n"); 9495 return 0; 9496 } 9497 9498 bnx2x_cl45_read(bp, phy, 9499 MDIO_PMA_DEVAD, 9500 MDIO_PMA_REG_8073_SPEED_LINK_STATUS, &link_status); 9501 9502 /* Bits 0..2 --> speed detected, 9503 * Bits 13..15--> link is down 9504 */ 9505 if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) { 9506 link_up = 1; 9507 vars->line_speed = SPEED_10000; 9508 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n", 9509 params->port); 9510 } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) { 9511 link_up = 1; 9512 vars->line_speed = SPEED_1000; 9513 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n", 9514 params->port); 9515 } else { 9516 link_up = 0; 9517 DP(NETIF_MSG_LINK, "port %x: External link is down\n", 9518 params->port); 9519 } 9520 9521 /* Capture 10G link fault. */ 9522 if (vars->line_speed == SPEED_10000) { 9523 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 9524 MDIO_PMA_LASI_TXSTAT, &val1); 9525 9526 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 9527 MDIO_PMA_LASI_TXSTAT, &val1); 9528 9529 if (val1 & (1<<0)) { 9530 vars->fault_detected = 1; 9531 } 9532 } 9533 9534 if (link_up) { 9535 bnx2x_ext_phy_resolve_fc(phy, params, vars); 9536 vars->duplex = DUPLEX_FULL; 9537 DP(NETIF_MSG_LINK, "duplex = 0x%x\n", vars->duplex); 9538 } 9539 9540 if ((DUAL_MEDIA(params)) && 9541 (phy->req_line_speed == SPEED_1000)) { 9542 bnx2x_cl45_read(bp, phy, 9543 MDIO_PMA_DEVAD, 9544 MDIO_PMA_REG_8727_PCS_GP, &val1); 9545 /* In case of dual-media board and 1G, power up the XAUI side, 9546 * otherwise power it down. For 10G it is done automatically 9547 */ 9548 if (link_up) 9549 val1 &= ~(3<<10); 9550 else 9551 val1 |= (3<<10); 9552 bnx2x_cl45_write(bp, phy, 9553 MDIO_PMA_DEVAD, 9554 MDIO_PMA_REG_8727_PCS_GP, val1); 9555 } 9556 return link_up; 9557 } 9558 9559 static void bnx2x_8727_link_reset(struct bnx2x_phy *phy, 9560 struct link_params *params) 9561 { 9562 struct bnx2x *bp = params->bp; 9563 9564 /* Enable/Disable PHY transmitter output */ 9565 bnx2x_set_disable_pmd_transmit(params, phy, 1); 9566 9567 /* Disable Transmitter */ 9568 bnx2x_sfp_set_transmitter(params, phy, 0); 9569 /* Clear LASI */ 9570 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0); 9571 9572 } 9573 9574 /******************************************************************/ 9575 /* BCM8481/BCM84823/BCM84833 PHY SECTION */ 9576 /******************************************************************/ 9577 static void bnx2x_save_848xx_spirom_version(struct bnx2x_phy *phy, 9578 struct bnx2x *bp, 9579 u8 port) 9580 { 9581 u16 val, fw_ver2, cnt, i; 9582 static struct bnx2x_reg_set reg_set[] = { 9583 {MDIO_PMA_DEVAD, 0xA819, 0x0014}, 9584 {MDIO_PMA_DEVAD, 0xA81A, 0xc200}, 9585 {MDIO_PMA_DEVAD, 0xA81B, 0x0000}, 9586 {MDIO_PMA_DEVAD, 0xA81C, 0x0300}, 9587 {MDIO_PMA_DEVAD, 0xA817, 0x0009} 9588 }; 9589 u16 fw_ver1; 9590 9591 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) || 9592 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) { 9593 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 0x400f, &fw_ver1); 9594 bnx2x_save_spirom_version(bp, port, fw_ver1 & 0xfff, 9595 phy->ver_addr); 9596 } else { 9597 /* For 32-bit registers in 848xx, access via MDIO2ARM i/f. */ 9598 /* (1) set reg 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */ 9599 for (i = 0; i < ARRAY_SIZE(reg_set); i++) 9600 bnx2x_cl45_write(bp, phy, reg_set[i].devad, 9601 reg_set[i].reg, reg_set[i].val); 9602 9603 for (cnt = 0; cnt < 100; cnt++) { 9604 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val); 9605 if (val & 1) 9606 break; 9607 udelay(5); 9608 } 9609 if (cnt == 100) { 9610 DP(NETIF_MSG_LINK, "Unable to read 848xx " 9611 "phy fw version(1)\n"); 9612 bnx2x_save_spirom_version(bp, port, 0, 9613 phy->ver_addr); 9614 return; 9615 } 9616 9617 9618 /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */ 9619 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0000); 9620 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200); 9621 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x000A); 9622 for (cnt = 0; cnt < 100; cnt++) { 9623 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val); 9624 if (val & 1) 9625 break; 9626 udelay(5); 9627 } 9628 if (cnt == 100) { 9629 DP(NETIF_MSG_LINK, "Unable to read 848xx phy fw " 9630 "version(2)\n"); 9631 bnx2x_save_spirom_version(bp, port, 0, 9632 phy->ver_addr); 9633 return; 9634 } 9635 9636 /* lower 16 bits of the register SPI_FW_STATUS */ 9637 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81B, &fw_ver1); 9638 /* upper 16 bits of register SPI_FW_STATUS */ 9639 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81C, &fw_ver2); 9640 9641 bnx2x_save_spirom_version(bp, port, (fw_ver2<<16) | fw_ver1, 9642 phy->ver_addr); 9643 } 9644 9645 } 9646 static void bnx2x_848xx_set_led(struct bnx2x *bp, 9647 struct bnx2x_phy *phy) 9648 { 9649 u16 val, offset, i; 9650 static struct bnx2x_reg_set reg_set[] = { 9651 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED1_MASK, 0x0080}, 9652 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED2_MASK, 0x0018}, 9653 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED3_MASK, 0x0006}, 9654 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED3_BLINK, 0x0000}, 9655 {MDIO_PMA_DEVAD, MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH, 9656 MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ}, 9657 {MDIO_AN_DEVAD, 0xFFFB, 0xFFFD} 9658 }; 9659 /* PHYC_CTL_LED_CTL */ 9660 bnx2x_cl45_read(bp, phy, 9661 MDIO_PMA_DEVAD, 9662 MDIO_PMA_REG_8481_LINK_SIGNAL, &val); 9663 val &= 0xFE00; 9664 val |= 0x0092; 9665 9666 bnx2x_cl45_write(bp, phy, 9667 MDIO_PMA_DEVAD, 9668 MDIO_PMA_REG_8481_LINK_SIGNAL, val); 9669 9670 for (i = 0; i < ARRAY_SIZE(reg_set); i++) 9671 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg, 9672 reg_set[i].val); 9673 9674 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) || 9675 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) 9676 offset = MDIO_PMA_REG_84833_CTL_LED_CTL_1; 9677 else 9678 offset = MDIO_PMA_REG_84823_CTL_LED_CTL_1; 9679 9680 /* stretch_en for LED3*/ 9681 bnx2x_cl45_read_or_write(bp, phy, 9682 MDIO_PMA_DEVAD, offset, 9683 MDIO_PMA_REG_84823_LED3_STRETCH_EN); 9684 } 9685 9686 static void bnx2x_848xx_specific_func(struct bnx2x_phy *phy, 9687 struct link_params *params, 9688 u32 action) 9689 { 9690 struct bnx2x *bp = params->bp; 9691 switch (action) { 9692 case PHY_INIT: 9693 if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) && 9694 (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) { 9695 /* Save spirom version */ 9696 bnx2x_save_848xx_spirom_version(phy, bp, params->port); 9697 } 9698 /* This phy uses the NIG latch mechanism since link indication 9699 * arrives through its LED4 and not via its LASI signal, so we 9700 * get steady signal instead of clear on read 9701 */ 9702 bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4, 9703 1 << NIG_LATCH_BC_ENABLE_MI_INT); 9704 9705 bnx2x_848xx_set_led(bp, phy); 9706 break; 9707 } 9708 } 9709 9710 static int bnx2x_848xx_cmn_config_init(struct bnx2x_phy *phy, 9711 struct link_params *params, 9712 struct link_vars *vars) 9713 { 9714 struct bnx2x *bp = params->bp; 9715 u16 autoneg_val, an_1000_val, an_10_100_val; 9716 9717 bnx2x_848xx_specific_func(phy, params, PHY_INIT); 9718 bnx2x_cl45_write(bp, phy, 9719 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0000); 9720 9721 /* set 1000 speed advertisement */ 9722 bnx2x_cl45_read(bp, phy, 9723 MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL, 9724 &an_1000_val); 9725 9726 bnx2x_ext_phy_set_pause(params, phy, vars); 9727 bnx2x_cl45_read(bp, phy, 9728 MDIO_AN_DEVAD, 9729 MDIO_AN_REG_8481_LEGACY_AN_ADV, 9730 &an_10_100_val); 9731 bnx2x_cl45_read(bp, phy, 9732 MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_MII_CTRL, 9733 &autoneg_val); 9734 /* Disable forced speed */ 9735 autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13)); 9736 an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8)); 9737 9738 if (((phy->req_line_speed == SPEED_AUTO_NEG) && 9739 (phy->speed_cap_mask & 9740 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) || 9741 (phy->req_line_speed == SPEED_1000)) { 9742 an_1000_val |= (1<<8); 9743 autoneg_val |= (1<<9 | 1<<12); 9744 if (phy->req_duplex == DUPLEX_FULL) 9745 an_1000_val |= (1<<9); 9746 DP(NETIF_MSG_LINK, "Advertising 1G\n"); 9747 } else 9748 an_1000_val &= ~((1<<8) | (1<<9)); 9749 9750 bnx2x_cl45_write(bp, phy, 9751 MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL, 9752 an_1000_val); 9753 9754 /* Set 10/100 speed advertisement */ 9755 if (phy->req_line_speed == SPEED_AUTO_NEG) { 9756 if (phy->speed_cap_mask & 9757 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL) { 9758 /* Enable autoneg and restart autoneg for legacy speeds 9759 */ 9760 autoneg_val |= (1<<9 | 1<<12); 9761 an_10_100_val |= (1<<8); 9762 DP(NETIF_MSG_LINK, "Advertising 100M-FD\n"); 9763 } 9764 9765 if (phy->speed_cap_mask & 9766 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF) { 9767 /* Enable autoneg and restart autoneg for legacy speeds 9768 */ 9769 autoneg_val |= (1<<9 | 1<<12); 9770 an_10_100_val |= (1<<7); 9771 DP(NETIF_MSG_LINK, "Advertising 100M-HD\n"); 9772 } 9773 9774 if ((phy->speed_cap_mask & 9775 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) && 9776 (phy->supported & SUPPORTED_10baseT_Full)) { 9777 an_10_100_val |= (1<<6); 9778 autoneg_val |= (1<<9 | 1<<12); 9779 DP(NETIF_MSG_LINK, "Advertising 10M-FD\n"); 9780 } 9781 9782 if ((phy->speed_cap_mask & 9783 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF) && 9784 (phy->supported & SUPPORTED_10baseT_Half)) { 9785 an_10_100_val |= (1<<5); 9786 autoneg_val |= (1<<9 | 1<<12); 9787 DP(NETIF_MSG_LINK, "Advertising 10M-HD\n"); 9788 } 9789 } 9790 9791 /* Only 10/100 are allowed to work in FORCE mode */ 9792 if ((phy->req_line_speed == SPEED_100) && 9793 (phy->supported & 9794 (SUPPORTED_100baseT_Half | 9795 SUPPORTED_100baseT_Full))) { 9796 autoneg_val |= (1<<13); 9797 /* Enabled AUTO-MDIX when autoneg is disabled */ 9798 bnx2x_cl45_write(bp, phy, 9799 MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL, 9800 (1<<15 | 1<<9 | 7<<0)); 9801 /* The PHY needs this set even for forced link. */ 9802 an_10_100_val |= (1<<8) | (1<<7); 9803 DP(NETIF_MSG_LINK, "Setting 100M force\n"); 9804 } 9805 if ((phy->req_line_speed == SPEED_10) && 9806 (phy->supported & 9807 (SUPPORTED_10baseT_Half | 9808 SUPPORTED_10baseT_Full))) { 9809 /* Enabled AUTO-MDIX when autoneg is disabled */ 9810 bnx2x_cl45_write(bp, phy, 9811 MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL, 9812 (1<<15 | 1<<9 | 7<<0)); 9813 DP(NETIF_MSG_LINK, "Setting 10M force\n"); 9814 } 9815 9816 bnx2x_cl45_write(bp, phy, 9817 MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_AN_ADV, 9818 an_10_100_val); 9819 9820 if (phy->req_duplex == DUPLEX_FULL) 9821 autoneg_val |= (1<<8); 9822 9823 /* Always write this if this is not 84833/4. 9824 * For 84833/4, write it only when it's a forced speed. 9825 */ 9826 if (((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) && 9827 (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) || 9828 ((autoneg_val & (1<<12)) == 0)) 9829 bnx2x_cl45_write(bp, phy, 9830 MDIO_AN_DEVAD, 9831 MDIO_AN_REG_8481_LEGACY_MII_CTRL, autoneg_val); 9832 9833 if (((phy->req_line_speed == SPEED_AUTO_NEG) && 9834 (phy->speed_cap_mask & 9835 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) || 9836 (phy->req_line_speed == SPEED_10000)) { 9837 DP(NETIF_MSG_LINK, "Advertising 10G\n"); 9838 /* Restart autoneg for 10G*/ 9839 9840 bnx2x_cl45_read_or_write( 9841 bp, phy, 9842 MDIO_AN_DEVAD, 9843 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL, 9844 0x1000); 9845 bnx2x_cl45_write(bp, phy, 9846 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 9847 0x3200); 9848 } else 9849 bnx2x_cl45_write(bp, phy, 9850 MDIO_AN_DEVAD, 9851 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL, 9852 1); 9853 9854 return 0; 9855 } 9856 9857 static int bnx2x_8481_config_init(struct bnx2x_phy *phy, 9858 struct link_params *params, 9859 struct link_vars *vars) 9860 { 9861 struct bnx2x *bp = params->bp; 9862 /* Restore normal power mode*/ 9863 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 9864 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); 9865 9866 /* HW reset */ 9867 bnx2x_ext_phy_hw_reset(bp, params->port); 9868 bnx2x_wait_reset_complete(bp, phy, params); 9869 9870 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15); 9871 return bnx2x_848xx_cmn_config_init(phy, params, vars); 9872 } 9873 9874 #define PHY84833_CMDHDLR_WAIT 300 9875 #define PHY84833_CMDHDLR_MAX_ARGS 5 9876 static int bnx2x_84833_cmd_hdlr(struct bnx2x_phy *phy, 9877 struct link_params *params, u16 fw_cmd, 9878 u16 cmd_args[], int argc) 9879 { 9880 int idx; 9881 u16 val; 9882 struct bnx2x *bp = params->bp; 9883 /* Write CMD_OPEN_OVERRIDE to STATUS reg */ 9884 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, 9885 MDIO_84833_CMD_HDLR_STATUS, 9886 PHY84833_STATUS_CMD_OPEN_OVERRIDE); 9887 for (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) { 9888 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 9889 MDIO_84833_CMD_HDLR_STATUS, &val); 9890 if (val == PHY84833_STATUS_CMD_OPEN_FOR_CMDS) 9891 break; 9892 usleep_range(1000, 2000); 9893 } 9894 if (idx >= PHY84833_CMDHDLR_WAIT) { 9895 DP(NETIF_MSG_LINK, "FW cmd: FW not ready.\n"); 9896 return -EINVAL; 9897 } 9898 9899 /* Prepare argument(s) and issue command */ 9900 for (idx = 0; idx < argc; idx++) { 9901 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, 9902 MDIO_84833_CMD_HDLR_DATA1 + idx, 9903 cmd_args[idx]); 9904 } 9905 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, 9906 MDIO_84833_CMD_HDLR_COMMAND, fw_cmd); 9907 for (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) { 9908 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 9909 MDIO_84833_CMD_HDLR_STATUS, &val); 9910 if ((val == PHY84833_STATUS_CMD_COMPLETE_PASS) || 9911 (val == PHY84833_STATUS_CMD_COMPLETE_ERROR)) 9912 break; 9913 usleep_range(1000, 2000); 9914 } 9915 if ((idx >= PHY84833_CMDHDLR_WAIT) || 9916 (val == PHY84833_STATUS_CMD_COMPLETE_ERROR)) { 9917 DP(NETIF_MSG_LINK, "FW cmd failed.\n"); 9918 return -EINVAL; 9919 } 9920 /* Gather returning data */ 9921 for (idx = 0; idx < argc; idx++) { 9922 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 9923 MDIO_84833_CMD_HDLR_DATA1 + idx, 9924 &cmd_args[idx]); 9925 } 9926 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, 9927 MDIO_84833_CMD_HDLR_STATUS, 9928 PHY84833_STATUS_CMD_CLEAR_COMPLETE); 9929 return 0; 9930 } 9931 9932 static int bnx2x_84833_pair_swap_cfg(struct bnx2x_phy *phy, 9933 struct link_params *params, 9934 struct link_vars *vars) 9935 { 9936 u32 pair_swap; 9937 u16 data[PHY84833_CMDHDLR_MAX_ARGS]; 9938 int status; 9939 struct bnx2x *bp = params->bp; 9940 9941 /* Check for configuration. */ 9942 pair_swap = REG_RD(bp, params->shmem_base + 9943 offsetof(struct shmem_region, 9944 dev_info.port_hw_config[params->port].xgbt_phy_cfg)) & 9945 PORT_HW_CFG_RJ45_PAIR_SWAP_MASK; 9946 9947 if (pair_swap == 0) 9948 return 0; 9949 9950 /* Only the second argument is used for this command */ 9951 data[1] = (u16)pair_swap; 9952 9953 status = bnx2x_84833_cmd_hdlr(phy, params, 9954 PHY84833_CMD_SET_PAIR_SWAP, data, PHY84833_CMDHDLR_MAX_ARGS); 9955 if (status == 0) 9956 DP(NETIF_MSG_LINK, "Pairswap OK, val=0x%x\n", data[1]); 9957 9958 return status; 9959 } 9960 9961 static u8 bnx2x_84833_get_reset_gpios(struct bnx2x *bp, 9962 u32 shmem_base_path[], 9963 u32 chip_id) 9964 { 9965 u32 reset_pin[2]; 9966 u32 idx; 9967 u8 reset_gpios; 9968 if (CHIP_IS_E3(bp)) { 9969 /* Assume that these will be GPIOs, not EPIOs. */ 9970 for (idx = 0; idx < 2; idx++) { 9971 /* Map config param to register bit. */ 9972 reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] + 9973 offsetof(struct shmem_region, 9974 dev_info.port_hw_config[0].e3_cmn_pin_cfg)); 9975 reset_pin[idx] = (reset_pin[idx] & 9976 PORT_HW_CFG_E3_PHY_RESET_MASK) >> 9977 PORT_HW_CFG_E3_PHY_RESET_SHIFT; 9978 reset_pin[idx] -= PIN_CFG_GPIO0_P0; 9979 reset_pin[idx] = (1 << reset_pin[idx]); 9980 } 9981 reset_gpios = (u8)(reset_pin[0] | reset_pin[1]); 9982 } else { 9983 /* E2, look from diff place of shmem. */ 9984 for (idx = 0; idx < 2; idx++) { 9985 reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] + 9986 offsetof(struct shmem_region, 9987 dev_info.port_hw_config[0].default_cfg)); 9988 reset_pin[idx] &= PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK; 9989 reset_pin[idx] -= PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0; 9990 reset_pin[idx] >>= PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT; 9991 reset_pin[idx] = (1 << reset_pin[idx]); 9992 } 9993 reset_gpios = (u8)(reset_pin[0] | reset_pin[1]); 9994 } 9995 9996 return reset_gpios; 9997 } 9998 9999 static int bnx2x_84833_hw_reset_phy(struct bnx2x_phy *phy, 10000 struct link_params *params) 10001 { 10002 struct bnx2x *bp = params->bp; 10003 u8 reset_gpios; 10004 u32 other_shmem_base_addr = REG_RD(bp, params->shmem2_base + 10005 offsetof(struct shmem2_region, 10006 other_shmem_base_addr)); 10007 10008 u32 shmem_base_path[2]; 10009 10010 /* Work around for 84833 LED failure inside RESET status */ 10011 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, 10012 MDIO_AN_REG_8481_LEGACY_MII_CTRL, 10013 MDIO_AN_REG_8481_MII_CTRL_FORCE_1G); 10014 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, 10015 MDIO_AN_REG_8481_1G_100T_EXT_CTRL, 10016 MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF); 10017 10018 shmem_base_path[0] = params->shmem_base; 10019 shmem_base_path[1] = other_shmem_base_addr; 10020 10021 reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path, 10022 params->chip_id); 10023 10024 bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW); 10025 udelay(10); 10026 DP(NETIF_MSG_LINK, "84833 hw reset on pin values 0x%x\n", 10027 reset_gpios); 10028 10029 return 0; 10030 } 10031 10032 static int bnx2x_8483x_disable_eee(struct bnx2x_phy *phy, 10033 struct link_params *params, 10034 struct link_vars *vars) 10035 { 10036 int rc; 10037 struct bnx2x *bp = params->bp; 10038 u16 cmd_args = 0; 10039 10040 DP(NETIF_MSG_LINK, "Don't Advertise 10GBase-T EEE\n"); 10041 10042 /* Prevent Phy from working in EEE and advertising it */ 10043 rc = bnx2x_84833_cmd_hdlr(phy, params, 10044 PHY84833_CMD_SET_EEE_MODE, &cmd_args, 1); 10045 if (rc) { 10046 DP(NETIF_MSG_LINK, "EEE disable failed.\n"); 10047 return rc; 10048 } 10049 10050 return bnx2x_eee_disable(phy, params, vars); 10051 } 10052 10053 static int bnx2x_8483x_enable_eee(struct bnx2x_phy *phy, 10054 struct link_params *params, 10055 struct link_vars *vars) 10056 { 10057 int rc; 10058 struct bnx2x *bp = params->bp; 10059 u16 cmd_args = 1; 10060 10061 rc = bnx2x_84833_cmd_hdlr(phy, params, 10062 PHY84833_CMD_SET_EEE_MODE, &cmd_args, 1); 10063 if (rc) { 10064 DP(NETIF_MSG_LINK, "EEE enable failed.\n"); 10065 return rc; 10066 } 10067 10068 return bnx2x_eee_advertise(phy, params, vars, SHMEM_EEE_10G_ADV); 10069 } 10070 10071 #define PHY84833_CONSTANT_LATENCY 1193 10072 static int bnx2x_848x3_config_init(struct bnx2x_phy *phy, 10073 struct link_params *params, 10074 struct link_vars *vars) 10075 { 10076 struct bnx2x *bp = params->bp; 10077 u8 port, initialize = 1; 10078 u16 val; 10079 u32 actual_phy_selection; 10080 u16 cmd_args[PHY84833_CMDHDLR_MAX_ARGS]; 10081 int rc = 0; 10082 10083 usleep_range(1000, 2000); 10084 10085 if (!(CHIP_IS_E1x(bp))) 10086 port = BP_PATH(bp); 10087 else 10088 port = params->port; 10089 10090 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) { 10091 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3, 10092 MISC_REGISTERS_GPIO_OUTPUT_HIGH, 10093 port); 10094 } else { 10095 /* MDIO reset */ 10096 bnx2x_cl45_write(bp, phy, 10097 MDIO_PMA_DEVAD, 10098 MDIO_PMA_REG_CTRL, 0x8000); 10099 } 10100 10101 bnx2x_wait_reset_complete(bp, phy, params); 10102 10103 /* Wait for GPHY to come out of reset */ 10104 msleep(50); 10105 if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) && 10106 (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) { 10107 /* BCM84823 requires that XGXS links up first @ 10G for normal 10108 * behavior. 10109 */ 10110 u16 temp; 10111 temp = vars->line_speed; 10112 vars->line_speed = SPEED_10000; 10113 bnx2x_set_autoneg(¶ms->phy[INT_PHY], params, vars, 0); 10114 bnx2x_program_serdes(¶ms->phy[INT_PHY], params, vars); 10115 vars->line_speed = temp; 10116 } 10117 10118 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 10119 MDIO_CTL_REG_84823_MEDIA, &val); 10120 val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK | 10121 MDIO_CTL_REG_84823_MEDIA_LINE_MASK | 10122 MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN | 10123 MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK | 10124 MDIO_CTL_REG_84823_MEDIA_FIBER_1G); 10125 10126 if (CHIP_IS_E3(bp)) { 10127 val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK | 10128 MDIO_CTL_REG_84823_MEDIA_LINE_MASK); 10129 } else { 10130 val |= (MDIO_CTL_REG_84823_CTRL_MAC_XFI | 10131 MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L); 10132 } 10133 10134 actual_phy_selection = bnx2x_phy_selection(params); 10135 10136 switch (actual_phy_selection) { 10137 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT: 10138 /* Do nothing. Essentially this is like the priority copper */ 10139 break; 10140 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY: 10141 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER; 10142 break; 10143 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY: 10144 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER; 10145 break; 10146 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY: 10147 /* Do nothing here. The first PHY won't be initialized at all */ 10148 break; 10149 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY: 10150 val |= MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN; 10151 initialize = 0; 10152 break; 10153 } 10154 if (params->phy[EXT_PHY2].req_line_speed == SPEED_1000) 10155 val |= MDIO_CTL_REG_84823_MEDIA_FIBER_1G; 10156 10157 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, 10158 MDIO_CTL_REG_84823_MEDIA, val); 10159 DP(NETIF_MSG_LINK, "Multi_phy config = 0x%x, Media control = 0x%x\n", 10160 params->multi_phy_config, val); 10161 10162 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) || 10163 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) { 10164 bnx2x_84833_pair_swap_cfg(phy, params, vars); 10165 10166 /* Keep AutogrEEEn disabled. */ 10167 cmd_args[0] = 0x0; 10168 cmd_args[1] = 0x0; 10169 cmd_args[2] = PHY84833_CONSTANT_LATENCY + 1; 10170 cmd_args[3] = PHY84833_CONSTANT_LATENCY; 10171 rc = bnx2x_84833_cmd_hdlr(phy, params, 10172 PHY84833_CMD_SET_EEE_MODE, cmd_args, 10173 PHY84833_CMDHDLR_MAX_ARGS); 10174 if (rc) 10175 DP(NETIF_MSG_LINK, "Cfg AutogrEEEn failed.\n"); 10176 } 10177 if (initialize) 10178 rc = bnx2x_848xx_cmn_config_init(phy, params, vars); 10179 else 10180 bnx2x_save_848xx_spirom_version(phy, bp, params->port); 10181 /* 84833 PHY has a better feature and doesn't need to support this. */ 10182 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) { 10183 u32 cms_enable = REG_RD(bp, params->shmem_base + 10184 offsetof(struct shmem_region, 10185 dev_info.port_hw_config[params->port].default_cfg)) & 10186 PORT_HW_CFG_ENABLE_CMS_MASK; 10187 10188 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 10189 MDIO_CTL_REG_84823_USER_CTRL_REG, &val); 10190 if (cms_enable) 10191 val |= MDIO_CTL_REG_84823_USER_CTRL_CMS; 10192 else 10193 val &= ~MDIO_CTL_REG_84823_USER_CTRL_CMS; 10194 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, 10195 MDIO_CTL_REG_84823_USER_CTRL_REG, val); 10196 } 10197 10198 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 10199 MDIO_84833_TOP_CFG_FW_REV, &val); 10200 10201 /* Configure EEE support */ 10202 if ((val >= MDIO_84833_TOP_CFG_FW_EEE) && 10203 (val != MDIO_84833_TOP_CFG_FW_NO_EEE) && 10204 bnx2x_eee_has_cap(params)) { 10205 rc = bnx2x_eee_initial_config(params, vars, SHMEM_EEE_10G_ADV); 10206 if (rc) { 10207 DP(NETIF_MSG_LINK, "Failed to configure EEE timers\n"); 10208 bnx2x_8483x_disable_eee(phy, params, vars); 10209 return rc; 10210 } 10211 10212 if ((phy->req_duplex == DUPLEX_FULL) && 10213 (params->eee_mode & EEE_MODE_ADV_LPI) && 10214 (bnx2x_eee_calc_timer(params) || 10215 !(params->eee_mode & EEE_MODE_ENABLE_LPI))) 10216 rc = bnx2x_8483x_enable_eee(phy, params, vars); 10217 else 10218 rc = bnx2x_8483x_disable_eee(phy, params, vars); 10219 if (rc) { 10220 DP(NETIF_MSG_LINK, "Failed to set EEE advertisement\n"); 10221 return rc; 10222 } 10223 } else { 10224 vars->eee_status &= ~SHMEM_EEE_SUPPORTED_MASK; 10225 } 10226 10227 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) || 10228 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) { 10229 /* Bring PHY out of super isolate mode as the final step. */ 10230 bnx2x_cl45_read_and_write(bp, phy, 10231 MDIO_CTL_DEVAD, 10232 MDIO_84833_TOP_CFG_XGPHY_STRAP1, 10233 (u16)~MDIO_84833_SUPER_ISOLATE); 10234 } 10235 return rc; 10236 } 10237 10238 static u8 bnx2x_848xx_read_status(struct bnx2x_phy *phy, 10239 struct link_params *params, 10240 struct link_vars *vars) 10241 { 10242 struct bnx2x *bp = params->bp; 10243 u16 val, val1, val2; 10244 u8 link_up = 0; 10245 10246 10247 /* Check 10G-BaseT link status */ 10248 /* Check PMD signal ok */ 10249 bnx2x_cl45_read(bp, phy, 10250 MDIO_AN_DEVAD, 0xFFFA, &val1); 10251 bnx2x_cl45_read(bp, phy, 10252 MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_PMD_SIGNAL, 10253 &val2); 10254 DP(NETIF_MSG_LINK, "BCM848xx: PMD_SIGNAL 1.a811 = 0x%x\n", val2); 10255 10256 /* Check link 10G */ 10257 if (val2 & (1<<11)) { 10258 vars->line_speed = SPEED_10000; 10259 vars->duplex = DUPLEX_FULL; 10260 link_up = 1; 10261 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars); 10262 } else { /* Check Legacy speed link */ 10263 u16 legacy_status, legacy_speed; 10264 10265 /* Enable expansion register 0x42 (Operation mode status) */ 10266 bnx2x_cl45_write(bp, phy, 10267 MDIO_AN_DEVAD, 10268 MDIO_AN_REG_8481_EXPANSION_REG_ACCESS, 0xf42); 10269 10270 /* Get legacy speed operation status */ 10271 bnx2x_cl45_read(bp, phy, 10272 MDIO_AN_DEVAD, 10273 MDIO_AN_REG_8481_EXPANSION_REG_RD_RW, 10274 &legacy_status); 10275 10276 DP(NETIF_MSG_LINK, "Legacy speed status = 0x%x\n", 10277 legacy_status); 10278 link_up = ((legacy_status & (1<<11)) == (1<<11)); 10279 legacy_speed = (legacy_status & (3<<9)); 10280 if (legacy_speed == (0<<9)) 10281 vars->line_speed = SPEED_10; 10282 else if (legacy_speed == (1<<9)) 10283 vars->line_speed = SPEED_100; 10284 else if (legacy_speed == (2<<9)) 10285 vars->line_speed = SPEED_1000; 10286 else { /* Should not happen: Treat as link down */ 10287 vars->line_speed = 0; 10288 link_up = 0; 10289 } 10290 10291 if (link_up) { 10292 if (legacy_status & (1<<8)) 10293 vars->duplex = DUPLEX_FULL; 10294 else 10295 vars->duplex = DUPLEX_HALF; 10296 10297 DP(NETIF_MSG_LINK, 10298 "Link is up in %dMbps, is_duplex_full= %d\n", 10299 vars->line_speed, 10300 (vars->duplex == DUPLEX_FULL)); 10301 /* Check legacy speed AN resolution */ 10302 bnx2x_cl45_read(bp, phy, 10303 MDIO_AN_DEVAD, 10304 MDIO_AN_REG_8481_LEGACY_MII_STATUS, 10305 &val); 10306 if (val & (1<<5)) 10307 vars->link_status |= 10308 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; 10309 bnx2x_cl45_read(bp, phy, 10310 MDIO_AN_DEVAD, 10311 MDIO_AN_REG_8481_LEGACY_AN_EXPANSION, 10312 &val); 10313 if ((val & (1<<0)) == 0) 10314 vars->link_status |= 10315 LINK_STATUS_PARALLEL_DETECTION_USED; 10316 } 10317 } 10318 if (link_up) { 10319 DP(NETIF_MSG_LINK, "BCM848x3: link speed is %d\n", 10320 vars->line_speed); 10321 bnx2x_ext_phy_resolve_fc(phy, params, vars); 10322 10323 /* Read LP advertised speeds */ 10324 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, 10325 MDIO_AN_REG_CL37_FC_LP, &val); 10326 if (val & (1<<5)) 10327 vars->link_status |= 10328 LINK_STATUS_LINK_PARTNER_10THD_CAPABLE; 10329 if (val & (1<<6)) 10330 vars->link_status |= 10331 LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE; 10332 if (val & (1<<7)) 10333 vars->link_status |= 10334 LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE; 10335 if (val & (1<<8)) 10336 vars->link_status |= 10337 LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE; 10338 if (val & (1<<9)) 10339 vars->link_status |= 10340 LINK_STATUS_LINK_PARTNER_100T4_CAPABLE; 10341 10342 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, 10343 MDIO_AN_REG_1000T_STATUS, &val); 10344 10345 if (val & (1<<10)) 10346 vars->link_status |= 10347 LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE; 10348 if (val & (1<<11)) 10349 vars->link_status |= 10350 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; 10351 10352 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, 10353 MDIO_AN_REG_MASTER_STATUS, &val); 10354 10355 if (val & (1<<11)) 10356 vars->link_status |= 10357 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; 10358 10359 /* Determine if EEE was negotiated */ 10360 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) || 10361 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) 10362 bnx2x_eee_an_resolve(phy, params, vars); 10363 } 10364 10365 return link_up; 10366 } 10367 10368 static int bnx2x_848xx_format_ver(u32 raw_ver, u8 *str, u16 *len) 10369 { 10370 int status = 0; 10371 u32 spirom_ver; 10372 spirom_ver = ((raw_ver & 0xF80) >> 7) << 16 | (raw_ver & 0x7F); 10373 status = bnx2x_format_ver(spirom_ver, str, len); 10374 return status; 10375 } 10376 10377 static void bnx2x_8481_hw_reset(struct bnx2x_phy *phy, 10378 struct link_params *params) 10379 { 10380 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1, 10381 MISC_REGISTERS_GPIO_OUTPUT_LOW, 0); 10382 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1, 10383 MISC_REGISTERS_GPIO_OUTPUT_LOW, 1); 10384 } 10385 10386 static void bnx2x_8481_link_reset(struct bnx2x_phy *phy, 10387 struct link_params *params) 10388 { 10389 bnx2x_cl45_write(params->bp, phy, 10390 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000); 10391 bnx2x_cl45_write(params->bp, phy, 10392 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1); 10393 } 10394 10395 static void bnx2x_848x3_link_reset(struct bnx2x_phy *phy, 10396 struct link_params *params) 10397 { 10398 struct bnx2x *bp = params->bp; 10399 u8 port; 10400 u16 val16; 10401 10402 if (!(CHIP_IS_E1x(bp))) 10403 port = BP_PATH(bp); 10404 else 10405 port = params->port; 10406 10407 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) { 10408 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3, 10409 MISC_REGISTERS_GPIO_OUTPUT_LOW, 10410 port); 10411 } else { 10412 bnx2x_cl45_read(bp, phy, 10413 MDIO_CTL_DEVAD, 10414 MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val16); 10415 val16 |= MDIO_84833_SUPER_ISOLATE; 10416 bnx2x_cl45_write(bp, phy, 10417 MDIO_CTL_DEVAD, 10418 MDIO_84833_TOP_CFG_XGPHY_STRAP1, val16); 10419 } 10420 } 10421 10422 static void bnx2x_848xx_set_link_led(struct bnx2x_phy *phy, 10423 struct link_params *params, u8 mode) 10424 { 10425 struct bnx2x *bp = params->bp; 10426 u16 val; 10427 u8 port; 10428 10429 if (!(CHIP_IS_E1x(bp))) 10430 port = BP_PATH(bp); 10431 else 10432 port = params->port; 10433 10434 switch (mode) { 10435 case LED_MODE_OFF: 10436 10437 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OFF\n", port); 10438 10439 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) == 10440 SHARED_HW_CFG_LED_EXTPHY1) { 10441 10442 /* Set LED masks */ 10443 bnx2x_cl45_write(bp, phy, 10444 MDIO_PMA_DEVAD, 10445 MDIO_PMA_REG_8481_LED1_MASK, 10446 0x0); 10447 10448 bnx2x_cl45_write(bp, phy, 10449 MDIO_PMA_DEVAD, 10450 MDIO_PMA_REG_8481_LED2_MASK, 10451 0x0); 10452 10453 bnx2x_cl45_write(bp, phy, 10454 MDIO_PMA_DEVAD, 10455 MDIO_PMA_REG_8481_LED3_MASK, 10456 0x0); 10457 10458 bnx2x_cl45_write(bp, phy, 10459 MDIO_PMA_DEVAD, 10460 MDIO_PMA_REG_8481_LED5_MASK, 10461 0x0); 10462 10463 } else { 10464 bnx2x_cl45_write(bp, phy, 10465 MDIO_PMA_DEVAD, 10466 MDIO_PMA_REG_8481_LED1_MASK, 10467 0x0); 10468 } 10469 break; 10470 case LED_MODE_FRONT_PANEL_OFF: 10471 10472 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE FRONT PANEL OFF\n", 10473 port); 10474 10475 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) == 10476 SHARED_HW_CFG_LED_EXTPHY1) { 10477 10478 /* Set LED masks */ 10479 bnx2x_cl45_write(bp, phy, 10480 MDIO_PMA_DEVAD, 10481 MDIO_PMA_REG_8481_LED1_MASK, 10482 0x0); 10483 10484 bnx2x_cl45_write(bp, phy, 10485 MDIO_PMA_DEVAD, 10486 MDIO_PMA_REG_8481_LED2_MASK, 10487 0x0); 10488 10489 bnx2x_cl45_write(bp, phy, 10490 MDIO_PMA_DEVAD, 10491 MDIO_PMA_REG_8481_LED3_MASK, 10492 0x0); 10493 10494 bnx2x_cl45_write(bp, phy, 10495 MDIO_PMA_DEVAD, 10496 MDIO_PMA_REG_8481_LED5_MASK, 10497 0x20); 10498 10499 } else { 10500 bnx2x_cl45_write(bp, phy, 10501 MDIO_PMA_DEVAD, 10502 MDIO_PMA_REG_8481_LED1_MASK, 10503 0x0); 10504 if (phy->type == 10505 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) { 10506 /* Disable MI_INT interrupt before setting LED4 10507 * source to constant off. 10508 */ 10509 if (REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + 10510 params->port*4) & 10511 NIG_MASK_MI_INT) { 10512 params->link_flags |= 10513 LINK_FLAGS_INT_DISABLED; 10514 10515 bnx2x_bits_dis( 10516 bp, 10517 NIG_REG_MASK_INTERRUPT_PORT0 + 10518 params->port*4, 10519 NIG_MASK_MI_INT); 10520 } 10521 bnx2x_cl45_write(bp, phy, 10522 MDIO_PMA_DEVAD, 10523 MDIO_PMA_REG_8481_SIGNAL_MASK, 10524 0x0); 10525 } 10526 } 10527 break; 10528 case LED_MODE_ON: 10529 10530 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE ON\n", port); 10531 10532 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) == 10533 SHARED_HW_CFG_LED_EXTPHY1) { 10534 /* Set control reg */ 10535 bnx2x_cl45_read(bp, phy, 10536 MDIO_PMA_DEVAD, 10537 MDIO_PMA_REG_8481_LINK_SIGNAL, 10538 &val); 10539 val &= 0x8000; 10540 val |= 0x2492; 10541 10542 bnx2x_cl45_write(bp, phy, 10543 MDIO_PMA_DEVAD, 10544 MDIO_PMA_REG_8481_LINK_SIGNAL, 10545 val); 10546 10547 /* Set LED masks */ 10548 bnx2x_cl45_write(bp, phy, 10549 MDIO_PMA_DEVAD, 10550 MDIO_PMA_REG_8481_LED1_MASK, 10551 0x0); 10552 10553 bnx2x_cl45_write(bp, phy, 10554 MDIO_PMA_DEVAD, 10555 MDIO_PMA_REG_8481_LED2_MASK, 10556 0x20); 10557 10558 bnx2x_cl45_write(bp, phy, 10559 MDIO_PMA_DEVAD, 10560 MDIO_PMA_REG_8481_LED3_MASK, 10561 0x20); 10562 10563 bnx2x_cl45_write(bp, phy, 10564 MDIO_PMA_DEVAD, 10565 MDIO_PMA_REG_8481_LED5_MASK, 10566 0x0); 10567 } else { 10568 bnx2x_cl45_write(bp, phy, 10569 MDIO_PMA_DEVAD, 10570 MDIO_PMA_REG_8481_LED1_MASK, 10571 0x20); 10572 if (phy->type == 10573 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) { 10574 /* Disable MI_INT interrupt before setting LED4 10575 * source to constant on. 10576 */ 10577 if (REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + 10578 params->port*4) & 10579 NIG_MASK_MI_INT) { 10580 params->link_flags |= 10581 LINK_FLAGS_INT_DISABLED; 10582 10583 bnx2x_bits_dis( 10584 bp, 10585 NIG_REG_MASK_INTERRUPT_PORT0 + 10586 params->port*4, 10587 NIG_MASK_MI_INT); 10588 } 10589 bnx2x_cl45_write(bp, phy, 10590 MDIO_PMA_DEVAD, 10591 MDIO_PMA_REG_8481_SIGNAL_MASK, 10592 0x20); 10593 } 10594 } 10595 break; 10596 10597 case LED_MODE_OPER: 10598 10599 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OPER\n", port); 10600 10601 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) == 10602 SHARED_HW_CFG_LED_EXTPHY1) { 10603 10604 /* Set control reg */ 10605 bnx2x_cl45_read(bp, phy, 10606 MDIO_PMA_DEVAD, 10607 MDIO_PMA_REG_8481_LINK_SIGNAL, 10608 &val); 10609 10610 if (!((val & 10611 MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK) 10612 >> MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT)) { 10613 DP(NETIF_MSG_LINK, "Setting LINK_SIGNAL\n"); 10614 bnx2x_cl45_write(bp, phy, 10615 MDIO_PMA_DEVAD, 10616 MDIO_PMA_REG_8481_LINK_SIGNAL, 10617 0xa492); 10618 } 10619 10620 /* Set LED masks */ 10621 bnx2x_cl45_write(bp, phy, 10622 MDIO_PMA_DEVAD, 10623 MDIO_PMA_REG_8481_LED1_MASK, 10624 0x10); 10625 10626 bnx2x_cl45_write(bp, phy, 10627 MDIO_PMA_DEVAD, 10628 MDIO_PMA_REG_8481_LED2_MASK, 10629 0x80); 10630 10631 bnx2x_cl45_write(bp, phy, 10632 MDIO_PMA_DEVAD, 10633 MDIO_PMA_REG_8481_LED3_MASK, 10634 0x98); 10635 10636 bnx2x_cl45_write(bp, phy, 10637 MDIO_PMA_DEVAD, 10638 MDIO_PMA_REG_8481_LED5_MASK, 10639 0x40); 10640 10641 } else { 10642 /* EXTPHY2 LED mode indicate that the 100M/1G/10G LED 10643 * sources are all wired through LED1, rather than only 10644 * 10G in other modes. 10645 */ 10646 val = ((params->hw_led_mode << 10647 SHARED_HW_CFG_LED_MODE_SHIFT) == 10648 SHARED_HW_CFG_LED_EXTPHY2) ? 0x98 : 0x80; 10649 10650 bnx2x_cl45_write(bp, phy, 10651 MDIO_PMA_DEVAD, 10652 MDIO_PMA_REG_8481_LED1_MASK, 10653 val); 10654 10655 /* Tell LED3 to blink on source */ 10656 bnx2x_cl45_read(bp, phy, 10657 MDIO_PMA_DEVAD, 10658 MDIO_PMA_REG_8481_LINK_SIGNAL, 10659 &val); 10660 val &= ~(7<<6); 10661 val |= (1<<6); /* A83B[8:6]= 1 */ 10662 bnx2x_cl45_write(bp, phy, 10663 MDIO_PMA_DEVAD, 10664 MDIO_PMA_REG_8481_LINK_SIGNAL, 10665 val); 10666 if (phy->type == 10667 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) { 10668 /* Restore LED4 source to external link, 10669 * and re-enable interrupts. 10670 */ 10671 bnx2x_cl45_write(bp, phy, 10672 MDIO_PMA_DEVAD, 10673 MDIO_PMA_REG_8481_SIGNAL_MASK, 10674 0x40); 10675 if (params->link_flags & 10676 LINK_FLAGS_INT_DISABLED) { 10677 bnx2x_link_int_enable(params); 10678 params->link_flags &= 10679 ~LINK_FLAGS_INT_DISABLED; 10680 } 10681 } 10682 } 10683 break; 10684 } 10685 10686 /* This is a workaround for E3+84833 until autoneg 10687 * restart is fixed in f/w 10688 */ 10689 if (CHIP_IS_E3(bp)) { 10690 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 10691 MDIO_WC_REG_GP2_STATUS_GP_2_1, &val); 10692 } 10693 } 10694 10695 /******************************************************************/ 10696 /* 54618SE PHY SECTION */ 10697 /******************************************************************/ 10698 static void bnx2x_54618se_specific_func(struct bnx2x_phy *phy, 10699 struct link_params *params, 10700 u32 action) 10701 { 10702 struct bnx2x *bp = params->bp; 10703 u16 temp; 10704 switch (action) { 10705 case PHY_INIT: 10706 /* Configure LED4: set to INTR (0x6). */ 10707 /* Accessing shadow register 0xe. */ 10708 bnx2x_cl22_write(bp, phy, 10709 MDIO_REG_GPHY_SHADOW, 10710 MDIO_REG_GPHY_SHADOW_LED_SEL2); 10711 bnx2x_cl22_read(bp, phy, 10712 MDIO_REG_GPHY_SHADOW, 10713 &temp); 10714 temp &= ~(0xf << 4); 10715 temp |= (0x6 << 4); 10716 bnx2x_cl22_write(bp, phy, 10717 MDIO_REG_GPHY_SHADOW, 10718 MDIO_REG_GPHY_SHADOW_WR_ENA | temp); 10719 /* Configure INTR based on link status change. */ 10720 bnx2x_cl22_write(bp, phy, 10721 MDIO_REG_INTR_MASK, 10722 ~MDIO_REG_INTR_MASK_LINK_STATUS); 10723 break; 10724 } 10725 } 10726 10727 static int bnx2x_54618se_config_init(struct bnx2x_phy *phy, 10728 struct link_params *params, 10729 struct link_vars *vars) 10730 { 10731 struct bnx2x *bp = params->bp; 10732 u8 port; 10733 u16 autoneg_val, an_1000_val, an_10_100_val, fc_val, temp; 10734 u32 cfg_pin; 10735 10736 DP(NETIF_MSG_LINK, "54618SE cfg init\n"); 10737 usleep_range(1000, 2000); 10738 10739 /* This works with E3 only, no need to check the chip 10740 * before determining the port. 10741 */ 10742 port = params->port; 10743 10744 cfg_pin = (REG_RD(bp, params->shmem_base + 10745 offsetof(struct shmem_region, 10746 dev_info.port_hw_config[port].e3_cmn_pin_cfg)) & 10747 PORT_HW_CFG_E3_PHY_RESET_MASK) >> 10748 PORT_HW_CFG_E3_PHY_RESET_SHIFT; 10749 10750 /* Drive pin high to bring the GPHY out of reset. */ 10751 bnx2x_set_cfg_pin(bp, cfg_pin, 1); 10752 10753 /* wait for GPHY to reset */ 10754 msleep(50); 10755 10756 /* reset phy */ 10757 bnx2x_cl22_write(bp, phy, 10758 MDIO_PMA_REG_CTRL, 0x8000); 10759 bnx2x_wait_reset_complete(bp, phy, params); 10760 10761 /* Wait for GPHY to reset */ 10762 msleep(50); 10763 10764 10765 bnx2x_54618se_specific_func(phy, params, PHY_INIT); 10766 /* Flip the signal detect polarity (set 0x1c.0x1e[8]). */ 10767 bnx2x_cl22_write(bp, phy, 10768 MDIO_REG_GPHY_SHADOW, 10769 MDIO_REG_GPHY_SHADOW_AUTO_DET_MED); 10770 bnx2x_cl22_read(bp, phy, 10771 MDIO_REG_GPHY_SHADOW, 10772 &temp); 10773 temp |= MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD; 10774 bnx2x_cl22_write(bp, phy, 10775 MDIO_REG_GPHY_SHADOW, 10776 MDIO_REG_GPHY_SHADOW_WR_ENA | temp); 10777 10778 /* Set up fc */ 10779 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */ 10780 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); 10781 fc_val = 0; 10782 if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) == 10783 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) 10784 fc_val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC; 10785 10786 if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) == 10787 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) 10788 fc_val |= MDIO_AN_REG_ADV_PAUSE_PAUSE; 10789 10790 /* Read all advertisement */ 10791 bnx2x_cl22_read(bp, phy, 10792 0x09, 10793 &an_1000_val); 10794 10795 bnx2x_cl22_read(bp, phy, 10796 0x04, 10797 &an_10_100_val); 10798 10799 bnx2x_cl22_read(bp, phy, 10800 MDIO_PMA_REG_CTRL, 10801 &autoneg_val); 10802 10803 /* Disable forced speed */ 10804 autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13)); 10805 an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8) | (1<<10) | 10806 (1<<11)); 10807 10808 if (((phy->req_line_speed == SPEED_AUTO_NEG) && 10809 (phy->speed_cap_mask & 10810 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) || 10811 (phy->req_line_speed == SPEED_1000)) { 10812 an_1000_val |= (1<<8); 10813 autoneg_val |= (1<<9 | 1<<12); 10814 if (phy->req_duplex == DUPLEX_FULL) 10815 an_1000_val |= (1<<9); 10816 DP(NETIF_MSG_LINK, "Advertising 1G\n"); 10817 } else 10818 an_1000_val &= ~((1<<8) | (1<<9)); 10819 10820 bnx2x_cl22_write(bp, phy, 10821 0x09, 10822 an_1000_val); 10823 bnx2x_cl22_read(bp, phy, 10824 0x09, 10825 &an_1000_val); 10826 10827 /* Advertise 10/100 link speed */ 10828 if (phy->req_line_speed == SPEED_AUTO_NEG) { 10829 if (phy->speed_cap_mask & 10830 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF) { 10831 an_10_100_val |= (1<<5); 10832 autoneg_val |= (1<<9 | 1<<12); 10833 DP(NETIF_MSG_LINK, "Advertising 10M-HD\n"); 10834 } 10835 if (phy->speed_cap_mask & 10836 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) { 10837 an_10_100_val |= (1<<6); 10838 autoneg_val |= (1<<9 | 1<<12); 10839 DP(NETIF_MSG_LINK, "Advertising 10M-FD\n"); 10840 } 10841 if (phy->speed_cap_mask & 10842 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF) { 10843 an_10_100_val |= (1<<7); 10844 autoneg_val |= (1<<9 | 1<<12); 10845 DP(NETIF_MSG_LINK, "Advertising 100M-HD\n"); 10846 } 10847 if (phy->speed_cap_mask & 10848 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL) { 10849 an_10_100_val |= (1<<8); 10850 autoneg_val |= (1<<9 | 1<<12); 10851 DP(NETIF_MSG_LINK, "Advertising 100M-FD\n"); 10852 } 10853 } 10854 10855 /* Only 10/100 are allowed to work in FORCE mode */ 10856 if (phy->req_line_speed == SPEED_100) { 10857 autoneg_val |= (1<<13); 10858 /* Enabled AUTO-MDIX when autoneg is disabled */ 10859 bnx2x_cl22_write(bp, phy, 10860 0x18, 10861 (1<<15 | 1<<9 | 7<<0)); 10862 DP(NETIF_MSG_LINK, "Setting 100M force\n"); 10863 } 10864 if (phy->req_line_speed == SPEED_10) { 10865 /* Enabled AUTO-MDIX when autoneg is disabled */ 10866 bnx2x_cl22_write(bp, phy, 10867 0x18, 10868 (1<<15 | 1<<9 | 7<<0)); 10869 DP(NETIF_MSG_LINK, "Setting 10M force\n"); 10870 } 10871 10872 if ((phy->flags & FLAGS_EEE) && bnx2x_eee_has_cap(params)) { 10873 int rc; 10874 10875 bnx2x_cl22_write(bp, phy, MDIO_REG_GPHY_EXP_ACCESS, 10876 MDIO_REG_GPHY_EXP_ACCESS_TOP | 10877 MDIO_REG_GPHY_EXP_TOP_2K_BUF); 10878 bnx2x_cl22_read(bp, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, &temp); 10879 temp &= 0xfffe; 10880 bnx2x_cl22_write(bp, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, temp); 10881 10882 rc = bnx2x_eee_initial_config(params, vars, SHMEM_EEE_1G_ADV); 10883 if (rc) { 10884 DP(NETIF_MSG_LINK, "Failed to configure EEE timers\n"); 10885 bnx2x_eee_disable(phy, params, vars); 10886 } else if ((params->eee_mode & EEE_MODE_ADV_LPI) && 10887 (phy->req_duplex == DUPLEX_FULL) && 10888 (bnx2x_eee_calc_timer(params) || 10889 !(params->eee_mode & EEE_MODE_ENABLE_LPI))) { 10890 /* Need to advertise EEE only when requested, 10891 * and either no LPI assertion was requested, 10892 * or it was requested and a valid timer was set. 10893 * Also notice full duplex is required for EEE. 10894 */ 10895 bnx2x_eee_advertise(phy, params, vars, 10896 SHMEM_EEE_1G_ADV); 10897 } else { 10898 DP(NETIF_MSG_LINK, "Don't Advertise 1GBase-T EEE\n"); 10899 bnx2x_eee_disable(phy, params, vars); 10900 } 10901 } else { 10902 vars->eee_status &= ~SHMEM_EEE_1G_ADV << 10903 SHMEM_EEE_SUPPORTED_SHIFT; 10904 10905 if (phy->flags & FLAGS_EEE) { 10906 /* Handle legacy auto-grEEEn */ 10907 if (params->feature_config_flags & 10908 FEATURE_CONFIG_AUTOGREEEN_ENABLED) { 10909 temp = 6; 10910 DP(NETIF_MSG_LINK, "Enabling Auto-GrEEEn\n"); 10911 } else { 10912 temp = 0; 10913 DP(NETIF_MSG_LINK, "Don't Adv. EEE\n"); 10914 } 10915 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, 10916 MDIO_AN_REG_EEE_ADV, temp); 10917 } 10918 } 10919 10920 bnx2x_cl22_write(bp, phy, 10921 0x04, 10922 an_10_100_val | fc_val); 10923 10924 if (phy->req_duplex == DUPLEX_FULL) 10925 autoneg_val |= (1<<8); 10926 10927 bnx2x_cl22_write(bp, phy, 10928 MDIO_PMA_REG_CTRL, autoneg_val); 10929 10930 return 0; 10931 } 10932 10933 10934 static void bnx2x_5461x_set_link_led(struct bnx2x_phy *phy, 10935 struct link_params *params, u8 mode) 10936 { 10937 struct bnx2x *bp = params->bp; 10938 u16 temp; 10939 10940 bnx2x_cl22_write(bp, phy, 10941 MDIO_REG_GPHY_SHADOW, 10942 MDIO_REG_GPHY_SHADOW_LED_SEL1); 10943 bnx2x_cl22_read(bp, phy, 10944 MDIO_REG_GPHY_SHADOW, 10945 &temp); 10946 temp &= 0xff00; 10947 10948 DP(NETIF_MSG_LINK, "54618x set link led (mode=%x)\n", mode); 10949 switch (mode) { 10950 case LED_MODE_FRONT_PANEL_OFF: 10951 case LED_MODE_OFF: 10952 temp |= 0x00ee; 10953 break; 10954 case LED_MODE_OPER: 10955 temp |= 0x0001; 10956 break; 10957 case LED_MODE_ON: 10958 temp |= 0x00ff; 10959 break; 10960 default: 10961 break; 10962 } 10963 bnx2x_cl22_write(bp, phy, 10964 MDIO_REG_GPHY_SHADOW, 10965 MDIO_REG_GPHY_SHADOW_WR_ENA | temp); 10966 return; 10967 } 10968 10969 10970 static void bnx2x_54618se_link_reset(struct bnx2x_phy *phy, 10971 struct link_params *params) 10972 { 10973 struct bnx2x *bp = params->bp; 10974 u32 cfg_pin; 10975 u8 port; 10976 10977 /* In case of no EPIO routed to reset the GPHY, put it 10978 * in low power mode. 10979 */ 10980 bnx2x_cl22_write(bp, phy, MDIO_PMA_REG_CTRL, 0x800); 10981 /* This works with E3 only, no need to check the chip 10982 * before determining the port. 10983 */ 10984 port = params->port; 10985 cfg_pin = (REG_RD(bp, params->shmem_base + 10986 offsetof(struct shmem_region, 10987 dev_info.port_hw_config[port].e3_cmn_pin_cfg)) & 10988 PORT_HW_CFG_E3_PHY_RESET_MASK) >> 10989 PORT_HW_CFG_E3_PHY_RESET_SHIFT; 10990 10991 /* Drive pin low to put GPHY in reset. */ 10992 bnx2x_set_cfg_pin(bp, cfg_pin, 0); 10993 } 10994 10995 static u8 bnx2x_54618se_read_status(struct bnx2x_phy *phy, 10996 struct link_params *params, 10997 struct link_vars *vars) 10998 { 10999 struct bnx2x *bp = params->bp; 11000 u16 val; 11001 u8 link_up = 0; 11002 u16 legacy_status, legacy_speed; 11003 11004 /* Get speed operation status */ 11005 bnx2x_cl22_read(bp, phy, 11006 MDIO_REG_GPHY_AUX_STATUS, 11007 &legacy_status); 11008 DP(NETIF_MSG_LINK, "54618SE read_status: 0x%x\n", legacy_status); 11009 11010 /* Read status to clear the PHY interrupt. */ 11011 bnx2x_cl22_read(bp, phy, 11012 MDIO_REG_INTR_STATUS, 11013 &val); 11014 11015 link_up = ((legacy_status & (1<<2)) == (1<<2)); 11016 11017 if (link_up) { 11018 legacy_speed = (legacy_status & (7<<8)); 11019 if (legacy_speed == (7<<8)) { 11020 vars->line_speed = SPEED_1000; 11021 vars->duplex = DUPLEX_FULL; 11022 } else if (legacy_speed == (6<<8)) { 11023 vars->line_speed = SPEED_1000; 11024 vars->duplex = DUPLEX_HALF; 11025 } else if (legacy_speed == (5<<8)) { 11026 vars->line_speed = SPEED_100; 11027 vars->duplex = DUPLEX_FULL; 11028 } 11029 /* Omitting 100Base-T4 for now */ 11030 else if (legacy_speed == (3<<8)) { 11031 vars->line_speed = SPEED_100; 11032 vars->duplex = DUPLEX_HALF; 11033 } else if (legacy_speed == (2<<8)) { 11034 vars->line_speed = SPEED_10; 11035 vars->duplex = DUPLEX_FULL; 11036 } else if (legacy_speed == (1<<8)) { 11037 vars->line_speed = SPEED_10; 11038 vars->duplex = DUPLEX_HALF; 11039 } else /* Should not happen */ 11040 vars->line_speed = 0; 11041 11042 DP(NETIF_MSG_LINK, 11043 "Link is up in %dMbps, is_duplex_full= %d\n", 11044 vars->line_speed, 11045 (vars->duplex == DUPLEX_FULL)); 11046 11047 /* Check legacy speed AN resolution */ 11048 bnx2x_cl22_read(bp, phy, 11049 0x01, 11050 &val); 11051 if (val & (1<<5)) 11052 vars->link_status |= 11053 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; 11054 bnx2x_cl22_read(bp, phy, 11055 0x06, 11056 &val); 11057 if ((val & (1<<0)) == 0) 11058 vars->link_status |= 11059 LINK_STATUS_PARALLEL_DETECTION_USED; 11060 11061 DP(NETIF_MSG_LINK, "BCM54618SE: link speed is %d\n", 11062 vars->line_speed); 11063 11064 bnx2x_ext_phy_resolve_fc(phy, params, vars); 11065 11066 if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) { 11067 /* Report LP advertised speeds */ 11068 bnx2x_cl22_read(bp, phy, 0x5, &val); 11069 11070 if (val & (1<<5)) 11071 vars->link_status |= 11072 LINK_STATUS_LINK_PARTNER_10THD_CAPABLE; 11073 if (val & (1<<6)) 11074 vars->link_status |= 11075 LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE; 11076 if (val & (1<<7)) 11077 vars->link_status |= 11078 LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE; 11079 if (val & (1<<8)) 11080 vars->link_status |= 11081 LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE; 11082 if (val & (1<<9)) 11083 vars->link_status |= 11084 LINK_STATUS_LINK_PARTNER_100T4_CAPABLE; 11085 11086 bnx2x_cl22_read(bp, phy, 0xa, &val); 11087 if (val & (1<<10)) 11088 vars->link_status |= 11089 LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE; 11090 if (val & (1<<11)) 11091 vars->link_status |= 11092 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; 11093 11094 if ((phy->flags & FLAGS_EEE) && 11095 bnx2x_eee_has_cap(params)) 11096 bnx2x_eee_an_resolve(phy, params, vars); 11097 } 11098 } 11099 return link_up; 11100 } 11101 11102 static void bnx2x_54618se_config_loopback(struct bnx2x_phy *phy, 11103 struct link_params *params) 11104 { 11105 struct bnx2x *bp = params->bp; 11106 u16 val; 11107 u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0; 11108 11109 DP(NETIF_MSG_LINK, "2PMA/PMD ext_phy_loopback: 54618se\n"); 11110 11111 /* Enable master/slave manual mmode and set to master */ 11112 /* mii write 9 [bits set 11 12] */ 11113 bnx2x_cl22_write(bp, phy, 0x09, 3<<11); 11114 11115 /* forced 1G and disable autoneg */ 11116 /* set val [mii read 0] */ 11117 /* set val [expr $val & [bits clear 6 12 13]] */ 11118 /* set val [expr $val | [bits set 6 8]] */ 11119 /* mii write 0 $val */ 11120 bnx2x_cl22_read(bp, phy, 0x00, &val); 11121 val &= ~((1<<6) | (1<<12) | (1<<13)); 11122 val |= (1<<6) | (1<<8); 11123 bnx2x_cl22_write(bp, phy, 0x00, val); 11124 11125 /* Set external loopback and Tx using 6dB coding */ 11126 /* mii write 0x18 7 */ 11127 /* set val [mii read 0x18] */ 11128 /* mii write 0x18 [expr $val | [bits set 10 15]] */ 11129 bnx2x_cl22_write(bp, phy, 0x18, 7); 11130 bnx2x_cl22_read(bp, phy, 0x18, &val); 11131 bnx2x_cl22_write(bp, phy, 0x18, val | (1<<10) | (1<<15)); 11132 11133 /* This register opens the gate for the UMAC despite its name */ 11134 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1); 11135 11136 /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame 11137 * length used by the MAC receive logic to check frames. 11138 */ 11139 REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710); 11140 } 11141 11142 /******************************************************************/ 11143 /* SFX7101 PHY SECTION */ 11144 /******************************************************************/ 11145 static void bnx2x_7101_config_loopback(struct bnx2x_phy *phy, 11146 struct link_params *params) 11147 { 11148 struct bnx2x *bp = params->bp; 11149 /* SFX7101_XGXS_TEST1 */ 11150 bnx2x_cl45_write(bp, phy, 11151 MDIO_XS_DEVAD, MDIO_XS_SFX7101_XGXS_TEST1, 0x100); 11152 } 11153 11154 static int bnx2x_7101_config_init(struct bnx2x_phy *phy, 11155 struct link_params *params, 11156 struct link_vars *vars) 11157 { 11158 u16 fw_ver1, fw_ver2, val; 11159 struct bnx2x *bp = params->bp; 11160 DP(NETIF_MSG_LINK, "Setting the SFX7101 LASI indication\n"); 11161 11162 /* Restore normal power mode*/ 11163 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 11164 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); 11165 /* HW reset */ 11166 bnx2x_ext_phy_hw_reset(bp, params->port); 11167 bnx2x_wait_reset_complete(bp, phy, params); 11168 11169 bnx2x_cl45_write(bp, phy, 11170 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x1); 11171 DP(NETIF_MSG_LINK, "Setting the SFX7101 LED to blink on traffic\n"); 11172 bnx2x_cl45_write(bp, phy, 11173 MDIO_PMA_DEVAD, MDIO_PMA_REG_7107_LED_CNTL, (1<<3)); 11174 11175 bnx2x_ext_phy_set_pause(params, phy, vars); 11176 /* Restart autoneg */ 11177 bnx2x_cl45_read(bp, phy, 11178 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, &val); 11179 val |= 0x200; 11180 bnx2x_cl45_write(bp, phy, 11181 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, val); 11182 11183 /* Save spirom version */ 11184 bnx2x_cl45_read(bp, phy, 11185 MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER1, &fw_ver1); 11186 11187 bnx2x_cl45_read(bp, phy, 11188 MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER2, &fw_ver2); 11189 bnx2x_save_spirom_version(bp, params->port, 11190 (u32)(fw_ver1<<16 | fw_ver2), phy->ver_addr); 11191 return 0; 11192 } 11193 11194 static u8 bnx2x_7101_read_status(struct bnx2x_phy *phy, 11195 struct link_params *params, 11196 struct link_vars *vars) 11197 { 11198 struct bnx2x *bp = params->bp; 11199 u8 link_up; 11200 u16 val1, val2; 11201 bnx2x_cl45_read(bp, phy, 11202 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2); 11203 bnx2x_cl45_read(bp, phy, 11204 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1); 11205 DP(NETIF_MSG_LINK, "10G-base-T LASI status 0x%x->0x%x\n", 11206 val2, val1); 11207 bnx2x_cl45_read(bp, phy, 11208 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2); 11209 bnx2x_cl45_read(bp, phy, 11210 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1); 11211 DP(NETIF_MSG_LINK, "10G-base-T PMA status 0x%x->0x%x\n", 11212 val2, val1); 11213 link_up = ((val1 & 4) == 4); 11214 /* If link is up print the AN outcome of the SFX7101 PHY */ 11215 if (link_up) { 11216 bnx2x_cl45_read(bp, phy, 11217 MDIO_AN_DEVAD, MDIO_AN_REG_MASTER_STATUS, 11218 &val2); 11219 vars->line_speed = SPEED_10000; 11220 vars->duplex = DUPLEX_FULL; 11221 DP(NETIF_MSG_LINK, "SFX7101 AN status 0x%x->Master=%x\n", 11222 val2, (val2 & (1<<14))); 11223 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars); 11224 bnx2x_ext_phy_resolve_fc(phy, params, vars); 11225 11226 /* Read LP advertised speeds */ 11227 if (val2 & (1<<11)) 11228 vars->link_status |= 11229 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; 11230 } 11231 return link_up; 11232 } 11233 11234 static int bnx2x_7101_format_ver(u32 spirom_ver, u8 *str, u16 *len) 11235 { 11236 if (*len < 5) 11237 return -EINVAL; 11238 str[0] = (spirom_ver & 0xFF); 11239 str[1] = (spirom_ver & 0xFF00) >> 8; 11240 str[2] = (spirom_ver & 0xFF0000) >> 16; 11241 str[3] = (spirom_ver & 0xFF000000) >> 24; 11242 str[4] = '\0'; 11243 *len -= 5; 11244 return 0; 11245 } 11246 11247 void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, struct bnx2x_phy *phy) 11248 { 11249 u16 val, cnt; 11250 11251 bnx2x_cl45_read(bp, phy, 11252 MDIO_PMA_DEVAD, 11253 MDIO_PMA_REG_7101_RESET, &val); 11254 11255 for (cnt = 0; cnt < 10; cnt++) { 11256 msleep(50); 11257 /* Writes a self-clearing reset */ 11258 bnx2x_cl45_write(bp, phy, 11259 MDIO_PMA_DEVAD, 11260 MDIO_PMA_REG_7101_RESET, 11261 (val | (1<<15))); 11262 /* Wait for clear */ 11263 bnx2x_cl45_read(bp, phy, 11264 MDIO_PMA_DEVAD, 11265 MDIO_PMA_REG_7101_RESET, &val); 11266 11267 if ((val & (1<<15)) == 0) 11268 break; 11269 } 11270 } 11271 11272 static void bnx2x_7101_hw_reset(struct bnx2x_phy *phy, 11273 struct link_params *params) { 11274 /* Low power mode is controlled by GPIO 2 */ 11275 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_2, 11276 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port); 11277 /* The PHY reset is controlled by GPIO 1 */ 11278 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1, 11279 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port); 11280 } 11281 11282 static void bnx2x_7101_set_link_led(struct bnx2x_phy *phy, 11283 struct link_params *params, u8 mode) 11284 { 11285 u16 val = 0; 11286 struct bnx2x *bp = params->bp; 11287 switch (mode) { 11288 case LED_MODE_FRONT_PANEL_OFF: 11289 case LED_MODE_OFF: 11290 val = 2; 11291 break; 11292 case LED_MODE_ON: 11293 val = 1; 11294 break; 11295 case LED_MODE_OPER: 11296 val = 0; 11297 break; 11298 } 11299 bnx2x_cl45_write(bp, phy, 11300 MDIO_PMA_DEVAD, 11301 MDIO_PMA_REG_7107_LINK_LED_CNTL, 11302 val); 11303 } 11304 11305 /******************************************************************/ 11306 /* STATIC PHY DECLARATION */ 11307 /******************************************************************/ 11308 11309 static const struct bnx2x_phy phy_null = { 11310 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN, 11311 .addr = 0, 11312 .def_md_devad = 0, 11313 .flags = FLAGS_INIT_XGXS_FIRST, 11314 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11315 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11316 .mdio_ctrl = 0, 11317 .supported = 0, 11318 .media_type = ETH_PHY_NOT_PRESENT, 11319 .ver_addr = 0, 11320 .req_flow_ctrl = 0, 11321 .req_line_speed = 0, 11322 .speed_cap_mask = 0, 11323 .req_duplex = 0, 11324 .rsrv = 0, 11325 .config_init = (config_init_t)NULL, 11326 .read_status = (read_status_t)NULL, 11327 .link_reset = (link_reset_t)NULL, 11328 .config_loopback = (config_loopback_t)NULL, 11329 .format_fw_ver = (format_fw_ver_t)NULL, 11330 .hw_reset = (hw_reset_t)NULL, 11331 .set_link_led = (set_link_led_t)NULL, 11332 .phy_specific_func = (phy_specific_func_t)NULL 11333 }; 11334 11335 static const struct bnx2x_phy phy_serdes = { 11336 .type = PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT, 11337 .addr = 0xff, 11338 .def_md_devad = 0, 11339 .flags = 0, 11340 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11341 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11342 .mdio_ctrl = 0, 11343 .supported = (SUPPORTED_10baseT_Half | 11344 SUPPORTED_10baseT_Full | 11345 SUPPORTED_100baseT_Half | 11346 SUPPORTED_100baseT_Full | 11347 SUPPORTED_1000baseT_Full | 11348 SUPPORTED_2500baseX_Full | 11349 SUPPORTED_TP | 11350 SUPPORTED_Autoneg | 11351 SUPPORTED_Pause | 11352 SUPPORTED_Asym_Pause), 11353 .media_type = ETH_PHY_BASE_T, 11354 .ver_addr = 0, 11355 .req_flow_ctrl = 0, 11356 .req_line_speed = 0, 11357 .speed_cap_mask = 0, 11358 .req_duplex = 0, 11359 .rsrv = 0, 11360 .config_init = (config_init_t)bnx2x_xgxs_config_init, 11361 .read_status = (read_status_t)bnx2x_link_settings_status, 11362 .link_reset = (link_reset_t)bnx2x_int_link_reset, 11363 .config_loopback = (config_loopback_t)NULL, 11364 .format_fw_ver = (format_fw_ver_t)NULL, 11365 .hw_reset = (hw_reset_t)NULL, 11366 .set_link_led = (set_link_led_t)NULL, 11367 .phy_specific_func = (phy_specific_func_t)NULL 11368 }; 11369 11370 static const struct bnx2x_phy phy_xgxs = { 11371 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT, 11372 .addr = 0xff, 11373 .def_md_devad = 0, 11374 .flags = 0, 11375 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11376 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11377 .mdio_ctrl = 0, 11378 .supported = (SUPPORTED_10baseT_Half | 11379 SUPPORTED_10baseT_Full | 11380 SUPPORTED_100baseT_Half | 11381 SUPPORTED_100baseT_Full | 11382 SUPPORTED_1000baseT_Full | 11383 SUPPORTED_2500baseX_Full | 11384 SUPPORTED_10000baseT_Full | 11385 SUPPORTED_FIBRE | 11386 SUPPORTED_Autoneg | 11387 SUPPORTED_Pause | 11388 SUPPORTED_Asym_Pause), 11389 .media_type = ETH_PHY_CX4, 11390 .ver_addr = 0, 11391 .req_flow_ctrl = 0, 11392 .req_line_speed = 0, 11393 .speed_cap_mask = 0, 11394 .req_duplex = 0, 11395 .rsrv = 0, 11396 .config_init = (config_init_t)bnx2x_xgxs_config_init, 11397 .read_status = (read_status_t)bnx2x_link_settings_status, 11398 .link_reset = (link_reset_t)bnx2x_int_link_reset, 11399 .config_loopback = (config_loopback_t)bnx2x_set_xgxs_loopback, 11400 .format_fw_ver = (format_fw_ver_t)NULL, 11401 .hw_reset = (hw_reset_t)NULL, 11402 .set_link_led = (set_link_led_t)NULL, 11403 .phy_specific_func = (phy_specific_func_t)bnx2x_xgxs_specific_func 11404 }; 11405 static const struct bnx2x_phy phy_warpcore = { 11406 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT, 11407 .addr = 0xff, 11408 .def_md_devad = 0, 11409 .flags = FLAGS_TX_ERROR_CHECK, 11410 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11411 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11412 .mdio_ctrl = 0, 11413 .supported = (SUPPORTED_10baseT_Half | 11414 SUPPORTED_10baseT_Full | 11415 SUPPORTED_100baseT_Half | 11416 SUPPORTED_100baseT_Full | 11417 SUPPORTED_1000baseT_Full | 11418 SUPPORTED_10000baseT_Full | 11419 SUPPORTED_20000baseKR2_Full | 11420 SUPPORTED_20000baseMLD2_Full | 11421 SUPPORTED_FIBRE | 11422 SUPPORTED_Autoneg | 11423 SUPPORTED_Pause | 11424 SUPPORTED_Asym_Pause), 11425 .media_type = ETH_PHY_UNSPECIFIED, 11426 .ver_addr = 0, 11427 .req_flow_ctrl = 0, 11428 .req_line_speed = 0, 11429 .speed_cap_mask = 0, 11430 /* req_duplex = */0, 11431 /* rsrv = */0, 11432 .config_init = (config_init_t)bnx2x_warpcore_config_init, 11433 .read_status = (read_status_t)bnx2x_warpcore_read_status, 11434 .link_reset = (link_reset_t)bnx2x_warpcore_link_reset, 11435 .config_loopback = (config_loopback_t)bnx2x_set_warpcore_loopback, 11436 .format_fw_ver = (format_fw_ver_t)NULL, 11437 .hw_reset = (hw_reset_t)bnx2x_warpcore_hw_reset, 11438 .set_link_led = (set_link_led_t)NULL, 11439 .phy_specific_func = (phy_specific_func_t)NULL 11440 }; 11441 11442 11443 static const struct bnx2x_phy phy_7101 = { 11444 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101, 11445 .addr = 0xff, 11446 .def_md_devad = 0, 11447 .flags = FLAGS_FAN_FAILURE_DET_REQ, 11448 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11449 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11450 .mdio_ctrl = 0, 11451 .supported = (SUPPORTED_10000baseT_Full | 11452 SUPPORTED_TP | 11453 SUPPORTED_Autoneg | 11454 SUPPORTED_Pause | 11455 SUPPORTED_Asym_Pause), 11456 .media_type = ETH_PHY_BASE_T, 11457 .ver_addr = 0, 11458 .req_flow_ctrl = 0, 11459 .req_line_speed = 0, 11460 .speed_cap_mask = 0, 11461 .req_duplex = 0, 11462 .rsrv = 0, 11463 .config_init = (config_init_t)bnx2x_7101_config_init, 11464 .read_status = (read_status_t)bnx2x_7101_read_status, 11465 .link_reset = (link_reset_t)bnx2x_common_ext_link_reset, 11466 .config_loopback = (config_loopback_t)bnx2x_7101_config_loopback, 11467 .format_fw_ver = (format_fw_ver_t)bnx2x_7101_format_ver, 11468 .hw_reset = (hw_reset_t)bnx2x_7101_hw_reset, 11469 .set_link_led = (set_link_led_t)bnx2x_7101_set_link_led, 11470 .phy_specific_func = (phy_specific_func_t)NULL 11471 }; 11472 static const struct bnx2x_phy phy_8073 = { 11473 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073, 11474 .addr = 0xff, 11475 .def_md_devad = 0, 11476 .flags = 0, 11477 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11478 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11479 .mdio_ctrl = 0, 11480 .supported = (SUPPORTED_10000baseT_Full | 11481 SUPPORTED_2500baseX_Full | 11482 SUPPORTED_1000baseT_Full | 11483 SUPPORTED_FIBRE | 11484 SUPPORTED_Autoneg | 11485 SUPPORTED_Pause | 11486 SUPPORTED_Asym_Pause), 11487 .media_type = ETH_PHY_KR, 11488 .ver_addr = 0, 11489 .req_flow_ctrl = 0, 11490 .req_line_speed = 0, 11491 .speed_cap_mask = 0, 11492 .req_duplex = 0, 11493 .rsrv = 0, 11494 .config_init = (config_init_t)bnx2x_8073_config_init, 11495 .read_status = (read_status_t)bnx2x_8073_read_status, 11496 .link_reset = (link_reset_t)bnx2x_8073_link_reset, 11497 .config_loopback = (config_loopback_t)NULL, 11498 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver, 11499 .hw_reset = (hw_reset_t)NULL, 11500 .set_link_led = (set_link_led_t)NULL, 11501 .phy_specific_func = (phy_specific_func_t)bnx2x_8073_specific_func 11502 }; 11503 static const struct bnx2x_phy phy_8705 = { 11504 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705, 11505 .addr = 0xff, 11506 .def_md_devad = 0, 11507 .flags = FLAGS_INIT_XGXS_FIRST, 11508 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11509 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11510 .mdio_ctrl = 0, 11511 .supported = (SUPPORTED_10000baseT_Full | 11512 SUPPORTED_FIBRE | 11513 SUPPORTED_Pause | 11514 SUPPORTED_Asym_Pause), 11515 .media_type = ETH_PHY_XFP_FIBER, 11516 .ver_addr = 0, 11517 .req_flow_ctrl = 0, 11518 .req_line_speed = 0, 11519 .speed_cap_mask = 0, 11520 .req_duplex = 0, 11521 .rsrv = 0, 11522 .config_init = (config_init_t)bnx2x_8705_config_init, 11523 .read_status = (read_status_t)bnx2x_8705_read_status, 11524 .link_reset = (link_reset_t)bnx2x_common_ext_link_reset, 11525 .config_loopback = (config_loopback_t)NULL, 11526 .format_fw_ver = (format_fw_ver_t)bnx2x_null_format_ver, 11527 .hw_reset = (hw_reset_t)NULL, 11528 .set_link_led = (set_link_led_t)NULL, 11529 .phy_specific_func = (phy_specific_func_t)NULL 11530 }; 11531 static const struct bnx2x_phy phy_8706 = { 11532 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706, 11533 .addr = 0xff, 11534 .def_md_devad = 0, 11535 .flags = FLAGS_INIT_XGXS_FIRST, 11536 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11537 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11538 .mdio_ctrl = 0, 11539 .supported = (SUPPORTED_10000baseT_Full | 11540 SUPPORTED_1000baseT_Full | 11541 SUPPORTED_FIBRE | 11542 SUPPORTED_Pause | 11543 SUPPORTED_Asym_Pause), 11544 .media_type = ETH_PHY_SFPP_10G_FIBER, 11545 .ver_addr = 0, 11546 .req_flow_ctrl = 0, 11547 .req_line_speed = 0, 11548 .speed_cap_mask = 0, 11549 .req_duplex = 0, 11550 .rsrv = 0, 11551 .config_init = (config_init_t)bnx2x_8706_config_init, 11552 .read_status = (read_status_t)bnx2x_8706_read_status, 11553 .link_reset = (link_reset_t)bnx2x_common_ext_link_reset, 11554 .config_loopback = (config_loopback_t)NULL, 11555 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver, 11556 .hw_reset = (hw_reset_t)NULL, 11557 .set_link_led = (set_link_led_t)NULL, 11558 .phy_specific_func = (phy_specific_func_t)NULL 11559 }; 11560 11561 static const struct bnx2x_phy phy_8726 = { 11562 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726, 11563 .addr = 0xff, 11564 .def_md_devad = 0, 11565 .flags = (FLAGS_INIT_XGXS_FIRST | 11566 FLAGS_TX_ERROR_CHECK), 11567 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11568 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11569 .mdio_ctrl = 0, 11570 .supported = (SUPPORTED_10000baseT_Full | 11571 SUPPORTED_1000baseT_Full | 11572 SUPPORTED_Autoneg | 11573 SUPPORTED_FIBRE | 11574 SUPPORTED_Pause | 11575 SUPPORTED_Asym_Pause), 11576 .media_type = ETH_PHY_NOT_PRESENT, 11577 .ver_addr = 0, 11578 .req_flow_ctrl = 0, 11579 .req_line_speed = 0, 11580 .speed_cap_mask = 0, 11581 .req_duplex = 0, 11582 .rsrv = 0, 11583 .config_init = (config_init_t)bnx2x_8726_config_init, 11584 .read_status = (read_status_t)bnx2x_8726_read_status, 11585 .link_reset = (link_reset_t)bnx2x_8726_link_reset, 11586 .config_loopback = (config_loopback_t)bnx2x_8726_config_loopback, 11587 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver, 11588 .hw_reset = (hw_reset_t)NULL, 11589 .set_link_led = (set_link_led_t)NULL, 11590 .phy_specific_func = (phy_specific_func_t)NULL 11591 }; 11592 11593 static const struct bnx2x_phy phy_8727 = { 11594 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727, 11595 .addr = 0xff, 11596 .def_md_devad = 0, 11597 .flags = (FLAGS_FAN_FAILURE_DET_REQ | 11598 FLAGS_TX_ERROR_CHECK), 11599 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11600 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11601 .mdio_ctrl = 0, 11602 .supported = (SUPPORTED_10000baseT_Full | 11603 SUPPORTED_1000baseT_Full | 11604 SUPPORTED_FIBRE | 11605 SUPPORTED_Pause | 11606 SUPPORTED_Asym_Pause), 11607 .media_type = ETH_PHY_NOT_PRESENT, 11608 .ver_addr = 0, 11609 .req_flow_ctrl = 0, 11610 .req_line_speed = 0, 11611 .speed_cap_mask = 0, 11612 .req_duplex = 0, 11613 .rsrv = 0, 11614 .config_init = (config_init_t)bnx2x_8727_config_init, 11615 .read_status = (read_status_t)bnx2x_8727_read_status, 11616 .link_reset = (link_reset_t)bnx2x_8727_link_reset, 11617 .config_loopback = (config_loopback_t)NULL, 11618 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver, 11619 .hw_reset = (hw_reset_t)bnx2x_8727_hw_reset, 11620 .set_link_led = (set_link_led_t)bnx2x_8727_set_link_led, 11621 .phy_specific_func = (phy_specific_func_t)bnx2x_8727_specific_func 11622 }; 11623 static const struct bnx2x_phy phy_8481 = { 11624 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481, 11625 .addr = 0xff, 11626 .def_md_devad = 0, 11627 .flags = FLAGS_FAN_FAILURE_DET_REQ | 11628 FLAGS_REARM_LATCH_SIGNAL, 11629 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11630 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11631 .mdio_ctrl = 0, 11632 .supported = (SUPPORTED_10baseT_Half | 11633 SUPPORTED_10baseT_Full | 11634 SUPPORTED_100baseT_Half | 11635 SUPPORTED_100baseT_Full | 11636 SUPPORTED_1000baseT_Full | 11637 SUPPORTED_10000baseT_Full | 11638 SUPPORTED_TP | 11639 SUPPORTED_Autoneg | 11640 SUPPORTED_Pause | 11641 SUPPORTED_Asym_Pause), 11642 .media_type = ETH_PHY_BASE_T, 11643 .ver_addr = 0, 11644 .req_flow_ctrl = 0, 11645 .req_line_speed = 0, 11646 .speed_cap_mask = 0, 11647 .req_duplex = 0, 11648 .rsrv = 0, 11649 .config_init = (config_init_t)bnx2x_8481_config_init, 11650 .read_status = (read_status_t)bnx2x_848xx_read_status, 11651 .link_reset = (link_reset_t)bnx2x_8481_link_reset, 11652 .config_loopback = (config_loopback_t)NULL, 11653 .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver, 11654 .hw_reset = (hw_reset_t)bnx2x_8481_hw_reset, 11655 .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led, 11656 .phy_specific_func = (phy_specific_func_t)NULL 11657 }; 11658 11659 static const struct bnx2x_phy phy_84823 = { 11660 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823, 11661 .addr = 0xff, 11662 .def_md_devad = 0, 11663 .flags = (FLAGS_FAN_FAILURE_DET_REQ | 11664 FLAGS_REARM_LATCH_SIGNAL | 11665 FLAGS_TX_ERROR_CHECK), 11666 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11667 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11668 .mdio_ctrl = 0, 11669 .supported = (SUPPORTED_10baseT_Half | 11670 SUPPORTED_10baseT_Full | 11671 SUPPORTED_100baseT_Half | 11672 SUPPORTED_100baseT_Full | 11673 SUPPORTED_1000baseT_Full | 11674 SUPPORTED_10000baseT_Full | 11675 SUPPORTED_TP | 11676 SUPPORTED_Autoneg | 11677 SUPPORTED_Pause | 11678 SUPPORTED_Asym_Pause), 11679 .media_type = ETH_PHY_BASE_T, 11680 .ver_addr = 0, 11681 .req_flow_ctrl = 0, 11682 .req_line_speed = 0, 11683 .speed_cap_mask = 0, 11684 .req_duplex = 0, 11685 .rsrv = 0, 11686 .config_init = (config_init_t)bnx2x_848x3_config_init, 11687 .read_status = (read_status_t)bnx2x_848xx_read_status, 11688 .link_reset = (link_reset_t)bnx2x_848x3_link_reset, 11689 .config_loopback = (config_loopback_t)NULL, 11690 .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver, 11691 .hw_reset = (hw_reset_t)NULL, 11692 .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led, 11693 .phy_specific_func = (phy_specific_func_t)bnx2x_848xx_specific_func 11694 }; 11695 11696 static const struct bnx2x_phy phy_84833 = { 11697 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833, 11698 .addr = 0xff, 11699 .def_md_devad = 0, 11700 .flags = (FLAGS_FAN_FAILURE_DET_REQ | 11701 FLAGS_REARM_LATCH_SIGNAL | 11702 FLAGS_TX_ERROR_CHECK), 11703 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11704 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11705 .mdio_ctrl = 0, 11706 .supported = (SUPPORTED_100baseT_Half | 11707 SUPPORTED_100baseT_Full | 11708 SUPPORTED_1000baseT_Full | 11709 SUPPORTED_10000baseT_Full | 11710 SUPPORTED_TP | 11711 SUPPORTED_Autoneg | 11712 SUPPORTED_Pause | 11713 SUPPORTED_Asym_Pause), 11714 .media_type = ETH_PHY_BASE_T, 11715 .ver_addr = 0, 11716 .req_flow_ctrl = 0, 11717 .req_line_speed = 0, 11718 .speed_cap_mask = 0, 11719 .req_duplex = 0, 11720 .rsrv = 0, 11721 .config_init = (config_init_t)bnx2x_848x3_config_init, 11722 .read_status = (read_status_t)bnx2x_848xx_read_status, 11723 .link_reset = (link_reset_t)bnx2x_848x3_link_reset, 11724 .config_loopback = (config_loopback_t)NULL, 11725 .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver, 11726 .hw_reset = (hw_reset_t)bnx2x_84833_hw_reset_phy, 11727 .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led, 11728 .phy_specific_func = (phy_specific_func_t)bnx2x_848xx_specific_func 11729 }; 11730 11731 static const struct bnx2x_phy phy_84834 = { 11732 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834, 11733 .addr = 0xff, 11734 .def_md_devad = 0, 11735 .flags = FLAGS_FAN_FAILURE_DET_REQ | 11736 FLAGS_REARM_LATCH_SIGNAL, 11737 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11738 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11739 .mdio_ctrl = 0, 11740 .supported = (SUPPORTED_100baseT_Half | 11741 SUPPORTED_100baseT_Full | 11742 SUPPORTED_1000baseT_Full | 11743 SUPPORTED_10000baseT_Full | 11744 SUPPORTED_TP | 11745 SUPPORTED_Autoneg | 11746 SUPPORTED_Pause | 11747 SUPPORTED_Asym_Pause), 11748 .media_type = ETH_PHY_BASE_T, 11749 .ver_addr = 0, 11750 .req_flow_ctrl = 0, 11751 .req_line_speed = 0, 11752 .speed_cap_mask = 0, 11753 .req_duplex = 0, 11754 .rsrv = 0, 11755 .config_init = (config_init_t)bnx2x_848x3_config_init, 11756 .read_status = (read_status_t)bnx2x_848xx_read_status, 11757 .link_reset = (link_reset_t)bnx2x_848x3_link_reset, 11758 .config_loopback = (config_loopback_t)NULL, 11759 .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver, 11760 .hw_reset = (hw_reset_t)bnx2x_84833_hw_reset_phy, 11761 .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led, 11762 .phy_specific_func = (phy_specific_func_t)bnx2x_848xx_specific_func 11763 }; 11764 11765 static const struct bnx2x_phy phy_54618se = { 11766 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE, 11767 .addr = 0xff, 11768 .def_md_devad = 0, 11769 .flags = FLAGS_INIT_XGXS_FIRST, 11770 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11771 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11772 .mdio_ctrl = 0, 11773 .supported = (SUPPORTED_10baseT_Half | 11774 SUPPORTED_10baseT_Full | 11775 SUPPORTED_100baseT_Half | 11776 SUPPORTED_100baseT_Full | 11777 SUPPORTED_1000baseT_Full | 11778 SUPPORTED_TP | 11779 SUPPORTED_Autoneg | 11780 SUPPORTED_Pause | 11781 SUPPORTED_Asym_Pause), 11782 .media_type = ETH_PHY_BASE_T, 11783 .ver_addr = 0, 11784 .req_flow_ctrl = 0, 11785 .req_line_speed = 0, 11786 .speed_cap_mask = 0, 11787 /* req_duplex = */0, 11788 /* rsrv = */0, 11789 .config_init = (config_init_t)bnx2x_54618se_config_init, 11790 .read_status = (read_status_t)bnx2x_54618se_read_status, 11791 .link_reset = (link_reset_t)bnx2x_54618se_link_reset, 11792 .config_loopback = (config_loopback_t)bnx2x_54618se_config_loopback, 11793 .format_fw_ver = (format_fw_ver_t)NULL, 11794 .hw_reset = (hw_reset_t)NULL, 11795 .set_link_led = (set_link_led_t)bnx2x_5461x_set_link_led, 11796 .phy_specific_func = (phy_specific_func_t)bnx2x_54618se_specific_func 11797 }; 11798 /*****************************************************************/ 11799 /* */ 11800 /* Populate the phy according. Main function: bnx2x_populate_phy */ 11801 /* */ 11802 /*****************************************************************/ 11803 11804 static void bnx2x_populate_preemphasis(struct bnx2x *bp, u32 shmem_base, 11805 struct bnx2x_phy *phy, u8 port, 11806 u8 phy_index) 11807 { 11808 /* Get the 4 lanes xgxs config rx and tx */ 11809 u32 rx = 0, tx = 0, i; 11810 for (i = 0; i < 2; i++) { 11811 /* INT_PHY and EXT_PHY1 share the same value location in 11812 * the shmem. When num_phys is greater than 1, than this value 11813 * applies only to EXT_PHY1 11814 */ 11815 if (phy_index == INT_PHY || phy_index == EXT_PHY1) { 11816 rx = REG_RD(bp, shmem_base + 11817 offsetof(struct shmem_region, 11818 dev_info.port_hw_config[port].xgxs_config_rx[i<<1])); 11819 11820 tx = REG_RD(bp, shmem_base + 11821 offsetof(struct shmem_region, 11822 dev_info.port_hw_config[port].xgxs_config_tx[i<<1])); 11823 } else { 11824 rx = REG_RD(bp, shmem_base + 11825 offsetof(struct shmem_region, 11826 dev_info.port_hw_config[port].xgxs_config2_rx[i<<1])); 11827 11828 tx = REG_RD(bp, shmem_base + 11829 offsetof(struct shmem_region, 11830 dev_info.port_hw_config[port].xgxs_config2_rx[i<<1])); 11831 } 11832 11833 phy->rx_preemphasis[i << 1] = ((rx>>16) & 0xffff); 11834 phy->rx_preemphasis[(i << 1) + 1] = (rx & 0xffff); 11835 11836 phy->tx_preemphasis[i << 1] = ((tx>>16) & 0xffff); 11837 phy->tx_preemphasis[(i << 1) + 1] = (tx & 0xffff); 11838 } 11839 } 11840 11841 static u32 bnx2x_get_ext_phy_config(struct bnx2x *bp, u32 shmem_base, 11842 u8 phy_index, u8 port) 11843 { 11844 u32 ext_phy_config = 0; 11845 switch (phy_index) { 11846 case EXT_PHY1: 11847 ext_phy_config = REG_RD(bp, shmem_base + 11848 offsetof(struct shmem_region, 11849 dev_info.port_hw_config[port].external_phy_config)); 11850 break; 11851 case EXT_PHY2: 11852 ext_phy_config = REG_RD(bp, shmem_base + 11853 offsetof(struct shmem_region, 11854 dev_info.port_hw_config[port].external_phy_config2)); 11855 break; 11856 default: 11857 DP(NETIF_MSG_LINK, "Invalid phy_index %d\n", phy_index); 11858 return -EINVAL; 11859 } 11860 11861 return ext_phy_config; 11862 } 11863 static int bnx2x_populate_int_phy(struct bnx2x *bp, u32 shmem_base, u8 port, 11864 struct bnx2x_phy *phy) 11865 { 11866 u32 phy_addr; 11867 u32 chip_id; 11868 u32 switch_cfg = (REG_RD(bp, shmem_base + 11869 offsetof(struct shmem_region, 11870 dev_info.port_feature_config[port].link_config)) & 11871 PORT_FEATURE_CONNECTED_SWITCH_MASK); 11872 chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) | 11873 ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12); 11874 11875 DP(NETIF_MSG_LINK, ":chip_id = 0x%x\n", chip_id); 11876 if (USES_WARPCORE(bp)) { 11877 u32 serdes_net_if; 11878 phy_addr = REG_RD(bp, 11879 MISC_REG_WC0_CTRL_PHY_ADDR); 11880 *phy = phy_warpcore; 11881 if (REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR) == 0x3) 11882 phy->flags |= FLAGS_4_PORT_MODE; 11883 else 11884 phy->flags &= ~FLAGS_4_PORT_MODE; 11885 /* Check Dual mode */ 11886 serdes_net_if = (REG_RD(bp, shmem_base + 11887 offsetof(struct shmem_region, dev_info. 11888 port_hw_config[port].default_cfg)) & 11889 PORT_HW_CFG_NET_SERDES_IF_MASK); 11890 /* Set the appropriate supported and flags indications per 11891 * interface type of the chip 11892 */ 11893 switch (serdes_net_if) { 11894 case PORT_HW_CFG_NET_SERDES_IF_SGMII: 11895 phy->supported &= (SUPPORTED_10baseT_Half | 11896 SUPPORTED_10baseT_Full | 11897 SUPPORTED_100baseT_Half | 11898 SUPPORTED_100baseT_Full | 11899 SUPPORTED_1000baseT_Full | 11900 SUPPORTED_FIBRE | 11901 SUPPORTED_Autoneg | 11902 SUPPORTED_Pause | 11903 SUPPORTED_Asym_Pause); 11904 phy->media_type = ETH_PHY_BASE_T; 11905 break; 11906 case PORT_HW_CFG_NET_SERDES_IF_XFI: 11907 phy->supported &= (SUPPORTED_1000baseT_Full | 11908 SUPPORTED_10000baseT_Full | 11909 SUPPORTED_FIBRE | 11910 SUPPORTED_Pause | 11911 SUPPORTED_Asym_Pause); 11912 phy->media_type = ETH_PHY_XFP_FIBER; 11913 break; 11914 case PORT_HW_CFG_NET_SERDES_IF_SFI: 11915 phy->supported &= (SUPPORTED_1000baseT_Full | 11916 SUPPORTED_10000baseT_Full | 11917 SUPPORTED_FIBRE | 11918 SUPPORTED_Pause | 11919 SUPPORTED_Asym_Pause); 11920 phy->media_type = ETH_PHY_SFPP_10G_FIBER; 11921 break; 11922 case PORT_HW_CFG_NET_SERDES_IF_KR: 11923 phy->media_type = ETH_PHY_KR; 11924 phy->supported &= (SUPPORTED_1000baseT_Full | 11925 SUPPORTED_10000baseT_Full | 11926 SUPPORTED_FIBRE | 11927 SUPPORTED_Autoneg | 11928 SUPPORTED_Pause | 11929 SUPPORTED_Asym_Pause); 11930 break; 11931 case PORT_HW_CFG_NET_SERDES_IF_DXGXS: 11932 phy->media_type = ETH_PHY_KR; 11933 phy->flags |= FLAGS_WC_DUAL_MODE; 11934 phy->supported &= (SUPPORTED_20000baseMLD2_Full | 11935 SUPPORTED_FIBRE | 11936 SUPPORTED_Pause | 11937 SUPPORTED_Asym_Pause); 11938 break; 11939 case PORT_HW_CFG_NET_SERDES_IF_KR2: 11940 phy->media_type = ETH_PHY_KR; 11941 phy->flags |= FLAGS_WC_DUAL_MODE; 11942 phy->supported &= (SUPPORTED_20000baseKR2_Full | 11943 SUPPORTED_10000baseT_Full | 11944 SUPPORTED_1000baseT_Full | 11945 SUPPORTED_Autoneg | 11946 SUPPORTED_FIBRE | 11947 SUPPORTED_Pause | 11948 SUPPORTED_Asym_Pause); 11949 phy->flags &= ~FLAGS_TX_ERROR_CHECK; 11950 break; 11951 default: 11952 DP(NETIF_MSG_LINK, "Unknown WC interface type 0x%x\n", 11953 serdes_net_if); 11954 break; 11955 } 11956 11957 /* Enable MDC/MDIO work-around for E3 A0 since free running MDC 11958 * was not set as expected. For B0, ECO will be enabled so there 11959 * won't be an issue there 11960 */ 11961 if (CHIP_REV(bp) == CHIP_REV_Ax) 11962 phy->flags |= FLAGS_MDC_MDIO_WA; 11963 else 11964 phy->flags |= FLAGS_MDC_MDIO_WA_B0; 11965 } else { 11966 switch (switch_cfg) { 11967 case SWITCH_CFG_1G: 11968 phy_addr = REG_RD(bp, 11969 NIG_REG_SERDES0_CTRL_PHY_ADDR + 11970 port * 0x10); 11971 *phy = phy_serdes; 11972 break; 11973 case SWITCH_CFG_10G: 11974 phy_addr = REG_RD(bp, 11975 NIG_REG_XGXS0_CTRL_PHY_ADDR + 11976 port * 0x18); 11977 *phy = phy_xgxs; 11978 break; 11979 default: 11980 DP(NETIF_MSG_LINK, "Invalid switch_cfg\n"); 11981 return -EINVAL; 11982 } 11983 } 11984 phy->addr = (u8)phy_addr; 11985 phy->mdio_ctrl = bnx2x_get_emac_base(bp, 11986 SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH, 11987 port); 11988 if (CHIP_IS_E2(bp)) 11989 phy->def_md_devad = E2_DEFAULT_PHY_DEV_ADDR; 11990 else 11991 phy->def_md_devad = DEFAULT_PHY_DEV_ADDR; 11992 11993 DP(NETIF_MSG_LINK, "Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x\n", 11994 port, phy->addr, phy->mdio_ctrl); 11995 11996 bnx2x_populate_preemphasis(bp, shmem_base, phy, port, INT_PHY); 11997 return 0; 11998 } 11999 12000 static int bnx2x_populate_ext_phy(struct bnx2x *bp, 12001 u8 phy_index, 12002 u32 shmem_base, 12003 u32 shmem2_base, 12004 u8 port, 12005 struct bnx2x_phy *phy) 12006 { 12007 u32 ext_phy_config, phy_type, config2; 12008 u32 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH; 12009 ext_phy_config = bnx2x_get_ext_phy_config(bp, shmem_base, 12010 phy_index, port); 12011 phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config); 12012 /* Select the phy type */ 12013 switch (phy_type) { 12014 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073: 12015 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED; 12016 *phy = phy_8073; 12017 break; 12018 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705: 12019 *phy = phy_8705; 12020 break; 12021 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706: 12022 *phy = phy_8706; 12023 break; 12024 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: 12025 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1; 12026 *phy = phy_8726; 12027 break; 12028 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC: 12029 /* BCM8727_NOC => BCM8727 no over current */ 12030 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1; 12031 *phy = phy_8727; 12032 phy->flags |= FLAGS_NOC; 12033 break; 12034 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722: 12035 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: 12036 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1; 12037 *phy = phy_8727; 12038 break; 12039 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481: 12040 *phy = phy_8481; 12041 break; 12042 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823: 12043 *phy = phy_84823; 12044 break; 12045 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833: 12046 *phy = phy_84833; 12047 break; 12048 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834: 12049 *phy = phy_84834; 12050 break; 12051 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616: 12052 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE: 12053 *phy = phy_54618se; 12054 if (phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) 12055 phy->flags |= FLAGS_EEE; 12056 break; 12057 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101: 12058 *phy = phy_7101; 12059 break; 12060 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE: 12061 *phy = phy_null; 12062 return -EINVAL; 12063 default: 12064 *phy = phy_null; 12065 /* In case external PHY wasn't found */ 12066 if ((phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) && 12067 (phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)) 12068 return -EINVAL; 12069 return 0; 12070 } 12071 12072 phy->addr = XGXS_EXT_PHY_ADDR(ext_phy_config); 12073 bnx2x_populate_preemphasis(bp, shmem_base, phy, port, phy_index); 12074 12075 /* The shmem address of the phy version is located on different 12076 * structures. In case this structure is too old, do not set 12077 * the address 12078 */ 12079 config2 = REG_RD(bp, shmem_base + offsetof(struct shmem_region, 12080 dev_info.shared_hw_config.config2)); 12081 if (phy_index == EXT_PHY1) { 12082 phy->ver_addr = shmem_base + offsetof(struct shmem_region, 12083 port_mb[port].ext_phy_fw_version); 12084 12085 /* Check specific mdc mdio settings */ 12086 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK) 12087 mdc_mdio_access = config2 & 12088 SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK; 12089 } else { 12090 u32 size = REG_RD(bp, shmem2_base); 12091 12092 if (size > 12093 offsetof(struct shmem2_region, ext_phy_fw_version2)) { 12094 phy->ver_addr = shmem2_base + 12095 offsetof(struct shmem2_region, 12096 ext_phy_fw_version2[port]); 12097 } 12098 /* Check specific mdc mdio settings */ 12099 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) 12100 mdc_mdio_access = (config2 & 12101 SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) >> 12102 (SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT - 12103 SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT); 12104 } 12105 phy->mdio_ctrl = bnx2x_get_emac_base(bp, mdc_mdio_access, port); 12106 12107 if (((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) || 12108 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) && 12109 (phy->ver_addr)) { 12110 /* Remove 100Mb link supported for BCM84833/4 when phy fw 12111 * version lower than or equal to 1.39 12112 */ 12113 u32 raw_ver = REG_RD(bp, phy->ver_addr); 12114 if (((raw_ver & 0x7F) <= 39) && 12115 (((raw_ver & 0xF80) >> 7) <= 1)) 12116 phy->supported &= ~(SUPPORTED_100baseT_Half | 12117 SUPPORTED_100baseT_Full); 12118 } 12119 12120 DP(NETIF_MSG_LINK, "phy_type 0x%x port %d found in index %d\n", 12121 phy_type, port, phy_index); 12122 DP(NETIF_MSG_LINK, " addr=0x%x, mdio_ctl=0x%x\n", 12123 phy->addr, phy->mdio_ctrl); 12124 return 0; 12125 } 12126 12127 static int bnx2x_populate_phy(struct bnx2x *bp, u8 phy_index, u32 shmem_base, 12128 u32 shmem2_base, u8 port, struct bnx2x_phy *phy) 12129 { 12130 int status = 0; 12131 phy->type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN; 12132 if (phy_index == INT_PHY) 12133 return bnx2x_populate_int_phy(bp, shmem_base, port, phy); 12134 status = bnx2x_populate_ext_phy(bp, phy_index, shmem_base, shmem2_base, 12135 port, phy); 12136 return status; 12137 } 12138 12139 static void bnx2x_phy_def_cfg(struct link_params *params, 12140 struct bnx2x_phy *phy, 12141 u8 phy_index) 12142 { 12143 struct bnx2x *bp = params->bp; 12144 u32 link_config; 12145 /* Populate the default phy configuration for MF mode */ 12146 if (phy_index == EXT_PHY2) { 12147 link_config = REG_RD(bp, params->shmem_base + 12148 offsetof(struct shmem_region, dev_info. 12149 port_feature_config[params->port].link_config2)); 12150 phy->speed_cap_mask = REG_RD(bp, params->shmem_base + 12151 offsetof(struct shmem_region, 12152 dev_info. 12153 port_hw_config[params->port].speed_capability_mask2)); 12154 } else { 12155 link_config = REG_RD(bp, params->shmem_base + 12156 offsetof(struct shmem_region, dev_info. 12157 port_feature_config[params->port].link_config)); 12158 phy->speed_cap_mask = REG_RD(bp, params->shmem_base + 12159 offsetof(struct shmem_region, 12160 dev_info. 12161 port_hw_config[params->port].speed_capability_mask)); 12162 } 12163 DP(NETIF_MSG_LINK, 12164 "Default config phy idx %x cfg 0x%x speed_cap_mask 0x%x\n", 12165 phy_index, link_config, phy->speed_cap_mask); 12166 12167 phy->req_duplex = DUPLEX_FULL; 12168 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) { 12169 case PORT_FEATURE_LINK_SPEED_10M_HALF: 12170 phy->req_duplex = DUPLEX_HALF; 12171 case PORT_FEATURE_LINK_SPEED_10M_FULL: 12172 phy->req_line_speed = SPEED_10; 12173 break; 12174 case PORT_FEATURE_LINK_SPEED_100M_HALF: 12175 phy->req_duplex = DUPLEX_HALF; 12176 case PORT_FEATURE_LINK_SPEED_100M_FULL: 12177 phy->req_line_speed = SPEED_100; 12178 break; 12179 case PORT_FEATURE_LINK_SPEED_1G: 12180 phy->req_line_speed = SPEED_1000; 12181 break; 12182 case PORT_FEATURE_LINK_SPEED_2_5G: 12183 phy->req_line_speed = SPEED_2500; 12184 break; 12185 case PORT_FEATURE_LINK_SPEED_10G_CX4: 12186 phy->req_line_speed = SPEED_10000; 12187 break; 12188 default: 12189 phy->req_line_speed = SPEED_AUTO_NEG; 12190 break; 12191 } 12192 12193 switch (link_config & PORT_FEATURE_FLOW_CONTROL_MASK) { 12194 case PORT_FEATURE_FLOW_CONTROL_AUTO: 12195 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_AUTO; 12196 break; 12197 case PORT_FEATURE_FLOW_CONTROL_TX: 12198 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_TX; 12199 break; 12200 case PORT_FEATURE_FLOW_CONTROL_RX: 12201 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_RX; 12202 break; 12203 case PORT_FEATURE_FLOW_CONTROL_BOTH: 12204 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_BOTH; 12205 break; 12206 default: 12207 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_NONE; 12208 break; 12209 } 12210 } 12211 12212 u32 bnx2x_phy_selection(struct link_params *params) 12213 { 12214 u32 phy_config_swapped, prio_cfg; 12215 u32 return_cfg = PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT; 12216 12217 phy_config_swapped = params->multi_phy_config & 12218 PORT_HW_CFG_PHY_SWAPPED_ENABLED; 12219 12220 prio_cfg = params->multi_phy_config & 12221 PORT_HW_CFG_PHY_SELECTION_MASK; 12222 12223 if (phy_config_swapped) { 12224 switch (prio_cfg) { 12225 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY: 12226 return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY; 12227 break; 12228 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY: 12229 return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY; 12230 break; 12231 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY: 12232 return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY; 12233 break; 12234 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY: 12235 return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY; 12236 break; 12237 } 12238 } else 12239 return_cfg = prio_cfg; 12240 12241 return return_cfg; 12242 } 12243 12244 int bnx2x_phy_probe(struct link_params *params) 12245 { 12246 u8 phy_index, actual_phy_idx; 12247 u32 phy_config_swapped, sync_offset, media_types; 12248 struct bnx2x *bp = params->bp; 12249 struct bnx2x_phy *phy; 12250 params->num_phys = 0; 12251 DP(NETIF_MSG_LINK, "Begin phy probe\n"); 12252 phy_config_swapped = params->multi_phy_config & 12253 PORT_HW_CFG_PHY_SWAPPED_ENABLED; 12254 12255 for (phy_index = INT_PHY; phy_index < MAX_PHYS; 12256 phy_index++) { 12257 actual_phy_idx = phy_index; 12258 if (phy_config_swapped) { 12259 if (phy_index == EXT_PHY1) 12260 actual_phy_idx = EXT_PHY2; 12261 else if (phy_index == EXT_PHY2) 12262 actual_phy_idx = EXT_PHY1; 12263 } 12264 DP(NETIF_MSG_LINK, "phy_config_swapped %x, phy_index %x," 12265 " actual_phy_idx %x\n", phy_config_swapped, 12266 phy_index, actual_phy_idx); 12267 phy = ¶ms->phy[actual_phy_idx]; 12268 if (bnx2x_populate_phy(bp, phy_index, params->shmem_base, 12269 params->shmem2_base, params->port, 12270 phy) != 0) { 12271 params->num_phys = 0; 12272 DP(NETIF_MSG_LINK, "phy probe failed in phy index %d\n", 12273 phy_index); 12274 for (phy_index = INT_PHY; 12275 phy_index < MAX_PHYS; 12276 phy_index++) 12277 *phy = phy_null; 12278 return -EINVAL; 12279 } 12280 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN) 12281 break; 12282 12283 if (params->feature_config_flags & 12284 FEATURE_CONFIG_DISABLE_REMOTE_FAULT_DET) 12285 phy->flags &= ~FLAGS_TX_ERROR_CHECK; 12286 12287 if (!(params->feature_config_flags & 12288 FEATURE_CONFIG_MT_SUPPORT)) 12289 phy->flags |= FLAGS_MDC_MDIO_WA_G; 12290 12291 sync_offset = params->shmem_base + 12292 offsetof(struct shmem_region, 12293 dev_info.port_hw_config[params->port].media_type); 12294 media_types = REG_RD(bp, sync_offset); 12295 12296 /* Update media type for non-PMF sync only for the first time 12297 * In case the media type changes afterwards, it will be updated 12298 * using the update_status function 12299 */ 12300 if ((media_types & (PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK << 12301 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * 12302 actual_phy_idx))) == 0) { 12303 media_types |= ((phy->media_type & 12304 PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) << 12305 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * 12306 actual_phy_idx)); 12307 } 12308 REG_WR(bp, sync_offset, media_types); 12309 12310 bnx2x_phy_def_cfg(params, phy, phy_index); 12311 params->num_phys++; 12312 } 12313 12314 DP(NETIF_MSG_LINK, "End phy probe. #phys found %x\n", params->num_phys); 12315 return 0; 12316 } 12317 12318 static void bnx2x_init_bmac_loopback(struct link_params *params, 12319 struct link_vars *vars) 12320 { 12321 struct bnx2x *bp = params->bp; 12322 vars->link_up = 1; 12323 vars->line_speed = SPEED_10000; 12324 vars->duplex = DUPLEX_FULL; 12325 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; 12326 vars->mac_type = MAC_TYPE_BMAC; 12327 12328 vars->phy_flags = PHY_XGXS_FLAG; 12329 12330 bnx2x_xgxs_deassert(params); 12331 12332 /* Set bmac loopback */ 12333 bnx2x_bmac_enable(params, vars, 1, 1); 12334 12335 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); 12336 } 12337 12338 static void bnx2x_init_emac_loopback(struct link_params *params, 12339 struct link_vars *vars) 12340 { 12341 struct bnx2x *bp = params->bp; 12342 vars->link_up = 1; 12343 vars->line_speed = SPEED_1000; 12344 vars->duplex = DUPLEX_FULL; 12345 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; 12346 vars->mac_type = MAC_TYPE_EMAC; 12347 12348 vars->phy_flags = PHY_XGXS_FLAG; 12349 12350 bnx2x_xgxs_deassert(params); 12351 /* Set bmac loopback */ 12352 bnx2x_emac_enable(params, vars, 1); 12353 bnx2x_emac_program(params, vars); 12354 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); 12355 } 12356 12357 static void bnx2x_init_xmac_loopback(struct link_params *params, 12358 struct link_vars *vars) 12359 { 12360 struct bnx2x *bp = params->bp; 12361 vars->link_up = 1; 12362 if (!params->req_line_speed[0]) 12363 vars->line_speed = SPEED_10000; 12364 else 12365 vars->line_speed = params->req_line_speed[0]; 12366 vars->duplex = DUPLEX_FULL; 12367 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; 12368 vars->mac_type = MAC_TYPE_XMAC; 12369 vars->phy_flags = PHY_XGXS_FLAG; 12370 /* Set WC to loopback mode since link is required to provide clock 12371 * to the XMAC in 20G mode 12372 */ 12373 bnx2x_set_aer_mmd(params, ¶ms->phy[0]); 12374 bnx2x_warpcore_reset_lane(bp, ¶ms->phy[0], 0); 12375 params->phy[INT_PHY].config_loopback( 12376 ¶ms->phy[INT_PHY], 12377 params); 12378 12379 bnx2x_xmac_enable(params, vars, 1); 12380 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); 12381 } 12382 12383 static void bnx2x_init_umac_loopback(struct link_params *params, 12384 struct link_vars *vars) 12385 { 12386 struct bnx2x *bp = params->bp; 12387 vars->link_up = 1; 12388 vars->line_speed = SPEED_1000; 12389 vars->duplex = DUPLEX_FULL; 12390 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; 12391 vars->mac_type = MAC_TYPE_UMAC; 12392 vars->phy_flags = PHY_XGXS_FLAG; 12393 bnx2x_umac_enable(params, vars, 1); 12394 12395 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); 12396 } 12397 12398 static void bnx2x_init_xgxs_loopback(struct link_params *params, 12399 struct link_vars *vars) 12400 { 12401 struct bnx2x *bp = params->bp; 12402 struct bnx2x_phy *int_phy = ¶ms->phy[INT_PHY]; 12403 vars->link_up = 1; 12404 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; 12405 vars->duplex = DUPLEX_FULL; 12406 if (params->req_line_speed[0] == SPEED_1000) 12407 vars->line_speed = SPEED_1000; 12408 else if ((params->req_line_speed[0] == SPEED_20000) || 12409 (int_phy->flags & FLAGS_WC_DUAL_MODE)) 12410 vars->line_speed = SPEED_20000; 12411 else 12412 vars->line_speed = SPEED_10000; 12413 12414 if (!USES_WARPCORE(bp)) 12415 bnx2x_xgxs_deassert(params); 12416 bnx2x_link_initialize(params, vars); 12417 12418 if (params->req_line_speed[0] == SPEED_1000) { 12419 if (USES_WARPCORE(bp)) 12420 bnx2x_umac_enable(params, vars, 0); 12421 else { 12422 bnx2x_emac_program(params, vars); 12423 bnx2x_emac_enable(params, vars, 0); 12424 } 12425 } else { 12426 if (USES_WARPCORE(bp)) 12427 bnx2x_xmac_enable(params, vars, 0); 12428 else 12429 bnx2x_bmac_enable(params, vars, 0, 1); 12430 } 12431 12432 if (params->loopback_mode == LOOPBACK_XGXS) { 12433 /* Set 10G XGXS loopback */ 12434 int_phy->config_loopback(int_phy, params); 12435 } else { 12436 /* Set external phy loopback */ 12437 u8 phy_index; 12438 for (phy_index = EXT_PHY1; 12439 phy_index < params->num_phys; phy_index++) 12440 if (params->phy[phy_index].config_loopback) 12441 params->phy[phy_index].config_loopback( 12442 ¶ms->phy[phy_index], 12443 params); 12444 } 12445 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); 12446 12447 bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed); 12448 } 12449 12450 void bnx2x_set_rx_filter(struct link_params *params, u8 en) 12451 { 12452 struct bnx2x *bp = params->bp; 12453 u8 val = en * 0x1F; 12454 12455 /* Open / close the gate between the NIG and the BRB */ 12456 if (!CHIP_IS_E1x(bp)) 12457 val |= en * 0x20; 12458 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + params->port*4, val); 12459 12460 if (!CHIP_IS_E1(bp)) { 12461 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + params->port*4, 12462 en*0x3); 12463 } 12464 12465 REG_WR(bp, (params->port ? NIG_REG_LLH1_BRB1_NOT_MCP : 12466 NIG_REG_LLH0_BRB1_NOT_MCP), en); 12467 } 12468 static int bnx2x_avoid_link_flap(struct link_params *params, 12469 struct link_vars *vars) 12470 { 12471 u32 phy_idx; 12472 u32 dont_clear_stat, lfa_sts; 12473 struct bnx2x *bp = params->bp; 12474 12475 bnx2x_set_mdio_emac_per_phy(bp, params); 12476 /* Sync the link parameters */ 12477 bnx2x_link_status_update(params, vars); 12478 12479 /* 12480 * The module verification was already done by previous link owner, 12481 * so this call is meant only to get warning message 12482 */ 12483 12484 for (phy_idx = INT_PHY; phy_idx < params->num_phys; phy_idx++) { 12485 struct bnx2x_phy *phy = ¶ms->phy[phy_idx]; 12486 if (phy->phy_specific_func) { 12487 DP(NETIF_MSG_LINK, "Calling PHY specific func\n"); 12488 phy->phy_specific_func(phy, params, PHY_INIT); 12489 } 12490 if ((phy->media_type == ETH_PHY_SFPP_10G_FIBER) || 12491 (phy->media_type == ETH_PHY_SFP_1G_FIBER) || 12492 (phy->media_type == ETH_PHY_DA_TWINAX)) 12493 bnx2x_verify_sfp_module(phy, params); 12494 } 12495 lfa_sts = REG_RD(bp, params->lfa_base + 12496 offsetof(struct shmem_lfa, 12497 lfa_sts)); 12498 12499 dont_clear_stat = lfa_sts & SHMEM_LFA_DONT_CLEAR_STAT; 12500 12501 /* Re-enable the NIG/MAC */ 12502 if (CHIP_IS_E3(bp)) { 12503 if (!dont_clear_stat) { 12504 REG_WR(bp, GRCBASE_MISC + 12505 MISC_REGISTERS_RESET_REG_2_CLEAR, 12506 (MISC_REGISTERS_RESET_REG_2_MSTAT0 << 12507 params->port)); 12508 REG_WR(bp, GRCBASE_MISC + 12509 MISC_REGISTERS_RESET_REG_2_SET, 12510 (MISC_REGISTERS_RESET_REG_2_MSTAT0 << 12511 params->port)); 12512 } 12513 if (vars->line_speed < SPEED_10000) 12514 bnx2x_umac_enable(params, vars, 0); 12515 else 12516 bnx2x_xmac_enable(params, vars, 0); 12517 } else { 12518 if (vars->line_speed < SPEED_10000) 12519 bnx2x_emac_enable(params, vars, 0); 12520 else 12521 bnx2x_bmac_enable(params, vars, 0, !dont_clear_stat); 12522 } 12523 12524 /* Increment LFA count */ 12525 lfa_sts = ((lfa_sts & ~LINK_FLAP_AVOIDANCE_COUNT_MASK) | 12526 (((((lfa_sts & LINK_FLAP_AVOIDANCE_COUNT_MASK) >> 12527 LINK_FLAP_AVOIDANCE_COUNT_OFFSET) + 1) & 0xff) 12528 << LINK_FLAP_AVOIDANCE_COUNT_OFFSET)); 12529 /* Clear link flap reason */ 12530 lfa_sts &= ~LFA_LINK_FLAP_REASON_MASK; 12531 12532 REG_WR(bp, params->lfa_base + 12533 offsetof(struct shmem_lfa, lfa_sts), lfa_sts); 12534 12535 /* Disable NIG DRAIN */ 12536 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); 12537 12538 /* Enable interrupts */ 12539 bnx2x_link_int_enable(params); 12540 return 0; 12541 } 12542 12543 static void bnx2x_cannot_avoid_link_flap(struct link_params *params, 12544 struct link_vars *vars, 12545 int lfa_status) 12546 { 12547 u32 lfa_sts, cfg_idx, tmp_val; 12548 struct bnx2x *bp = params->bp; 12549 12550 bnx2x_link_reset(params, vars, 1); 12551 12552 if (!params->lfa_base) 12553 return; 12554 /* Store the new link parameters */ 12555 REG_WR(bp, params->lfa_base + 12556 offsetof(struct shmem_lfa, req_duplex), 12557 params->req_duplex[0] | (params->req_duplex[1] << 16)); 12558 12559 REG_WR(bp, params->lfa_base + 12560 offsetof(struct shmem_lfa, req_flow_ctrl), 12561 params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16)); 12562 12563 REG_WR(bp, params->lfa_base + 12564 offsetof(struct shmem_lfa, req_line_speed), 12565 params->req_line_speed[0] | (params->req_line_speed[1] << 16)); 12566 12567 for (cfg_idx = 0; cfg_idx < SHMEM_LINK_CONFIG_SIZE; cfg_idx++) { 12568 REG_WR(bp, params->lfa_base + 12569 offsetof(struct shmem_lfa, 12570 speed_cap_mask[cfg_idx]), 12571 params->speed_cap_mask[cfg_idx]); 12572 } 12573 12574 tmp_val = REG_RD(bp, params->lfa_base + 12575 offsetof(struct shmem_lfa, additional_config)); 12576 tmp_val &= ~REQ_FC_AUTO_ADV_MASK; 12577 tmp_val |= params->req_fc_auto_adv; 12578 12579 REG_WR(bp, params->lfa_base + 12580 offsetof(struct shmem_lfa, additional_config), tmp_val); 12581 12582 lfa_sts = REG_RD(bp, params->lfa_base + 12583 offsetof(struct shmem_lfa, lfa_sts)); 12584 12585 /* Clear the "Don't Clear Statistics" bit, and set reason */ 12586 lfa_sts &= ~SHMEM_LFA_DONT_CLEAR_STAT; 12587 12588 /* Set link flap reason */ 12589 lfa_sts &= ~LFA_LINK_FLAP_REASON_MASK; 12590 lfa_sts |= ((lfa_status & LFA_LINK_FLAP_REASON_MASK) << 12591 LFA_LINK_FLAP_REASON_OFFSET); 12592 12593 /* Increment link flap counter */ 12594 lfa_sts = ((lfa_sts & ~LINK_FLAP_COUNT_MASK) | 12595 (((((lfa_sts & LINK_FLAP_COUNT_MASK) >> 12596 LINK_FLAP_COUNT_OFFSET) + 1) & 0xff) 12597 << LINK_FLAP_COUNT_OFFSET)); 12598 REG_WR(bp, params->lfa_base + 12599 offsetof(struct shmem_lfa, lfa_sts), lfa_sts); 12600 /* Proceed with regular link initialization */ 12601 } 12602 12603 int bnx2x_phy_init(struct link_params *params, struct link_vars *vars) 12604 { 12605 int lfa_status; 12606 struct bnx2x *bp = params->bp; 12607 DP(NETIF_MSG_LINK, "Phy Initialization started\n"); 12608 DP(NETIF_MSG_LINK, "(1) req_speed %d, req_flowctrl %d\n", 12609 params->req_line_speed[0], params->req_flow_ctrl[0]); 12610 DP(NETIF_MSG_LINK, "(2) req_speed %d, req_flowctrl %d\n", 12611 params->req_line_speed[1], params->req_flow_ctrl[1]); 12612 DP(NETIF_MSG_LINK, "req_adv_flow_ctrl 0x%x\n", params->req_fc_auto_adv); 12613 vars->link_status = 0; 12614 vars->phy_link_up = 0; 12615 vars->link_up = 0; 12616 vars->line_speed = 0; 12617 vars->duplex = DUPLEX_FULL; 12618 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; 12619 vars->mac_type = MAC_TYPE_NONE; 12620 vars->phy_flags = 0; 12621 vars->check_kr2_recovery_cnt = 0; 12622 params->link_flags = PHY_INITIALIZED; 12623 /* Driver opens NIG-BRB filters */ 12624 bnx2x_set_rx_filter(params, 1); 12625 /* Check if link flap can be avoided */ 12626 lfa_status = bnx2x_check_lfa(params); 12627 12628 if (lfa_status == 0) { 12629 DP(NETIF_MSG_LINK, "Link Flap Avoidance in progress\n"); 12630 return bnx2x_avoid_link_flap(params, vars); 12631 } 12632 12633 DP(NETIF_MSG_LINK, "Cannot avoid link flap lfa_sta=0x%x\n", 12634 lfa_status); 12635 bnx2x_cannot_avoid_link_flap(params, vars, lfa_status); 12636 12637 /* Disable attentions */ 12638 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4, 12639 (NIG_MASK_XGXS0_LINK_STATUS | 12640 NIG_MASK_XGXS0_LINK10G | 12641 NIG_MASK_SERDES0_LINK_STATUS | 12642 NIG_MASK_MI_INT)); 12643 12644 bnx2x_emac_init(params, vars); 12645 12646 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) 12647 vars->link_status |= LINK_STATUS_PFC_ENABLED; 12648 12649 if (params->num_phys == 0) { 12650 DP(NETIF_MSG_LINK, "No phy found for initialization !!\n"); 12651 return -EINVAL; 12652 } 12653 set_phy_vars(params, vars); 12654 12655 DP(NETIF_MSG_LINK, "Num of phys on board: %d\n", params->num_phys); 12656 switch (params->loopback_mode) { 12657 case LOOPBACK_BMAC: 12658 bnx2x_init_bmac_loopback(params, vars); 12659 break; 12660 case LOOPBACK_EMAC: 12661 bnx2x_init_emac_loopback(params, vars); 12662 break; 12663 case LOOPBACK_XMAC: 12664 bnx2x_init_xmac_loopback(params, vars); 12665 break; 12666 case LOOPBACK_UMAC: 12667 bnx2x_init_umac_loopback(params, vars); 12668 break; 12669 case LOOPBACK_XGXS: 12670 case LOOPBACK_EXT_PHY: 12671 bnx2x_init_xgxs_loopback(params, vars); 12672 break; 12673 default: 12674 if (!CHIP_IS_E3(bp)) { 12675 if (params->switch_cfg == SWITCH_CFG_10G) 12676 bnx2x_xgxs_deassert(params); 12677 else 12678 bnx2x_serdes_deassert(bp, params->port); 12679 } 12680 bnx2x_link_initialize(params, vars); 12681 msleep(30); 12682 bnx2x_link_int_enable(params); 12683 break; 12684 } 12685 bnx2x_update_mng(params, vars->link_status); 12686 12687 bnx2x_update_mng_eee(params, vars->eee_status); 12688 return 0; 12689 } 12690 12691 int bnx2x_link_reset(struct link_params *params, struct link_vars *vars, 12692 u8 reset_ext_phy) 12693 { 12694 struct bnx2x *bp = params->bp; 12695 u8 phy_index, port = params->port, clear_latch_ind = 0; 12696 DP(NETIF_MSG_LINK, "Resetting the link of port %d\n", port); 12697 /* Disable attentions */ 12698 vars->link_status = 0; 12699 bnx2x_update_mng(params, vars->link_status); 12700 vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK | 12701 SHMEM_EEE_ACTIVE_BIT); 12702 bnx2x_update_mng_eee(params, vars->eee_status); 12703 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 12704 (NIG_MASK_XGXS0_LINK_STATUS | 12705 NIG_MASK_XGXS0_LINK10G | 12706 NIG_MASK_SERDES0_LINK_STATUS | 12707 NIG_MASK_MI_INT)); 12708 12709 /* Activate nig drain */ 12710 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1); 12711 12712 /* Disable nig egress interface */ 12713 if (!CHIP_IS_E3(bp)) { 12714 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0); 12715 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0); 12716 } 12717 12718 if (!CHIP_IS_E3(bp)) { 12719 bnx2x_set_bmac_rx(bp, params->chip_id, port, 0); 12720 } else { 12721 bnx2x_set_xmac_rxtx(params, 0); 12722 bnx2x_set_umac_rxtx(params, 0); 12723 } 12724 /* Disable emac */ 12725 if (!CHIP_IS_E3(bp)) 12726 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0); 12727 12728 usleep_range(10000, 20000); 12729 /* The PHY reset is controlled by GPIO 1 12730 * Hold it as vars low 12731 */ 12732 /* Clear link led */ 12733 bnx2x_set_mdio_emac_per_phy(bp, params); 12734 bnx2x_set_led(params, vars, LED_MODE_OFF, 0); 12735 12736 if (reset_ext_phy) { 12737 for (phy_index = EXT_PHY1; phy_index < params->num_phys; 12738 phy_index++) { 12739 if (params->phy[phy_index].link_reset) { 12740 bnx2x_set_aer_mmd(params, 12741 ¶ms->phy[phy_index]); 12742 params->phy[phy_index].link_reset( 12743 ¶ms->phy[phy_index], 12744 params); 12745 } 12746 if (params->phy[phy_index].flags & 12747 FLAGS_REARM_LATCH_SIGNAL) 12748 clear_latch_ind = 1; 12749 } 12750 } 12751 12752 if (clear_latch_ind) { 12753 /* Clear latching indication */ 12754 bnx2x_rearm_latch_signal(bp, port, 0); 12755 bnx2x_bits_dis(bp, NIG_REG_LATCH_BC_0 + port*4, 12756 1 << NIG_LATCH_BC_ENABLE_MI_INT); 12757 } 12758 if (params->phy[INT_PHY].link_reset) 12759 params->phy[INT_PHY].link_reset( 12760 ¶ms->phy[INT_PHY], params); 12761 12762 /* Disable nig ingress interface */ 12763 if (!CHIP_IS_E3(bp)) { 12764 /* Reset BigMac */ 12765 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 12766 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); 12767 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0); 12768 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0); 12769 } else { 12770 u32 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; 12771 bnx2x_set_xumac_nig(params, 0, 0); 12772 if (REG_RD(bp, MISC_REG_RESET_REG_2) & 12773 MISC_REGISTERS_RESET_REG_2_XMAC) 12774 REG_WR(bp, xmac_base + XMAC_REG_CTRL, 12775 XMAC_CTRL_REG_SOFT_RESET); 12776 } 12777 vars->link_up = 0; 12778 vars->phy_flags = 0; 12779 return 0; 12780 } 12781 int bnx2x_lfa_reset(struct link_params *params, 12782 struct link_vars *vars) 12783 { 12784 struct bnx2x *bp = params->bp; 12785 vars->link_up = 0; 12786 vars->phy_flags = 0; 12787 params->link_flags &= ~PHY_INITIALIZED; 12788 if (!params->lfa_base) 12789 return bnx2x_link_reset(params, vars, 1); 12790 /* 12791 * Activate NIG drain so that during this time the device won't send 12792 * anything while it is unable to response. 12793 */ 12794 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1); 12795 12796 /* 12797 * Close gracefully the gate from BMAC to NIG such that no half packets 12798 * are passed. 12799 */ 12800 if (!CHIP_IS_E3(bp)) 12801 bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 0); 12802 12803 if (CHIP_IS_E3(bp)) { 12804 bnx2x_set_xmac_rxtx(params, 0); 12805 bnx2x_set_umac_rxtx(params, 0); 12806 } 12807 /* Wait 10ms for the pipe to clean up*/ 12808 usleep_range(10000, 20000); 12809 12810 /* Clean the NIG-BRB using the network filters in a way that will 12811 * not cut a packet in the middle. 12812 */ 12813 bnx2x_set_rx_filter(params, 0); 12814 12815 /* 12816 * Re-open the gate between the BMAC and the NIG, after verifying the 12817 * gate to the BRB is closed, otherwise packets may arrive to the 12818 * firmware before driver had initialized it. The target is to achieve 12819 * minimum management protocol down time. 12820 */ 12821 if (!CHIP_IS_E3(bp)) 12822 bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 1); 12823 12824 if (CHIP_IS_E3(bp)) { 12825 bnx2x_set_xmac_rxtx(params, 1); 12826 bnx2x_set_umac_rxtx(params, 1); 12827 } 12828 /* Disable NIG drain */ 12829 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); 12830 return 0; 12831 } 12832 12833 /****************************************************************************/ 12834 /* Common function */ 12835 /****************************************************************************/ 12836 static int bnx2x_8073_common_init_phy(struct bnx2x *bp, 12837 u32 shmem_base_path[], 12838 u32 shmem2_base_path[], u8 phy_index, 12839 u32 chip_id) 12840 { 12841 struct bnx2x_phy phy[PORT_MAX]; 12842 struct bnx2x_phy *phy_blk[PORT_MAX]; 12843 u16 val; 12844 s8 port = 0; 12845 s8 port_of_path = 0; 12846 u32 swap_val, swap_override; 12847 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); 12848 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); 12849 port ^= (swap_val && swap_override); 12850 bnx2x_ext_phy_hw_reset(bp, port); 12851 /* PART1 - Reset both phys */ 12852 for (port = PORT_MAX - 1; port >= PORT_0; port--) { 12853 u32 shmem_base, shmem2_base; 12854 /* In E2, same phy is using for port0 of the two paths */ 12855 if (CHIP_IS_E1x(bp)) { 12856 shmem_base = shmem_base_path[0]; 12857 shmem2_base = shmem2_base_path[0]; 12858 port_of_path = port; 12859 } else { 12860 shmem_base = shmem_base_path[port]; 12861 shmem2_base = shmem2_base_path[port]; 12862 port_of_path = 0; 12863 } 12864 12865 /* Extract the ext phy address for the port */ 12866 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base, 12867 port_of_path, &phy[port]) != 12868 0) { 12869 DP(NETIF_MSG_LINK, "populate_phy failed\n"); 12870 return -EINVAL; 12871 } 12872 /* Disable attentions */ 12873 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + 12874 port_of_path*4, 12875 (NIG_MASK_XGXS0_LINK_STATUS | 12876 NIG_MASK_XGXS0_LINK10G | 12877 NIG_MASK_SERDES0_LINK_STATUS | 12878 NIG_MASK_MI_INT)); 12879 12880 /* Need to take the phy out of low power mode in order 12881 * to write to access its registers 12882 */ 12883 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 12884 MISC_REGISTERS_GPIO_OUTPUT_HIGH, 12885 port); 12886 12887 /* Reset the phy */ 12888 bnx2x_cl45_write(bp, &phy[port], 12889 MDIO_PMA_DEVAD, 12890 MDIO_PMA_REG_CTRL, 12891 1<<15); 12892 } 12893 12894 /* Add delay of 150ms after reset */ 12895 msleep(150); 12896 12897 if (phy[PORT_0].addr & 0x1) { 12898 phy_blk[PORT_0] = &(phy[PORT_1]); 12899 phy_blk[PORT_1] = &(phy[PORT_0]); 12900 } else { 12901 phy_blk[PORT_0] = &(phy[PORT_0]); 12902 phy_blk[PORT_1] = &(phy[PORT_1]); 12903 } 12904 12905 /* PART2 - Download firmware to both phys */ 12906 for (port = PORT_MAX - 1; port >= PORT_0; port--) { 12907 if (CHIP_IS_E1x(bp)) 12908 port_of_path = port; 12909 else 12910 port_of_path = 0; 12911 12912 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n", 12913 phy_blk[port]->addr); 12914 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port], 12915 port_of_path)) 12916 return -EINVAL; 12917 12918 /* Only set bit 10 = 1 (Tx power down) */ 12919 bnx2x_cl45_read(bp, phy_blk[port], 12920 MDIO_PMA_DEVAD, 12921 MDIO_PMA_REG_TX_POWER_DOWN, &val); 12922 12923 /* Phase1 of TX_POWER_DOWN reset */ 12924 bnx2x_cl45_write(bp, phy_blk[port], 12925 MDIO_PMA_DEVAD, 12926 MDIO_PMA_REG_TX_POWER_DOWN, 12927 (val | 1<<10)); 12928 } 12929 12930 /* Toggle Transmitter: Power down and then up with 600ms delay 12931 * between 12932 */ 12933 msleep(600); 12934 12935 /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */ 12936 for (port = PORT_MAX - 1; port >= PORT_0; port--) { 12937 /* Phase2 of POWER_DOWN_RESET */ 12938 /* Release bit 10 (Release Tx power down) */ 12939 bnx2x_cl45_read(bp, phy_blk[port], 12940 MDIO_PMA_DEVAD, 12941 MDIO_PMA_REG_TX_POWER_DOWN, &val); 12942 12943 bnx2x_cl45_write(bp, phy_blk[port], 12944 MDIO_PMA_DEVAD, 12945 MDIO_PMA_REG_TX_POWER_DOWN, (val & (~(1<<10)))); 12946 usleep_range(15000, 30000); 12947 12948 /* Read modify write the SPI-ROM version select register */ 12949 bnx2x_cl45_read(bp, phy_blk[port], 12950 MDIO_PMA_DEVAD, 12951 MDIO_PMA_REG_EDC_FFE_MAIN, &val); 12952 bnx2x_cl45_write(bp, phy_blk[port], 12953 MDIO_PMA_DEVAD, 12954 MDIO_PMA_REG_EDC_FFE_MAIN, (val | (1<<12))); 12955 12956 /* set GPIO2 back to LOW */ 12957 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 12958 MISC_REGISTERS_GPIO_OUTPUT_LOW, port); 12959 } 12960 return 0; 12961 } 12962 static int bnx2x_8726_common_init_phy(struct bnx2x *bp, 12963 u32 shmem_base_path[], 12964 u32 shmem2_base_path[], u8 phy_index, 12965 u32 chip_id) 12966 { 12967 u32 val; 12968 s8 port; 12969 struct bnx2x_phy phy; 12970 /* Use port1 because of the static port-swap */ 12971 /* Enable the module detection interrupt */ 12972 val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN); 12973 val |= ((1<<MISC_REGISTERS_GPIO_3)| 12974 (1<<(MISC_REGISTERS_GPIO_3 + MISC_REGISTERS_GPIO_PORT_SHIFT))); 12975 REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val); 12976 12977 bnx2x_ext_phy_hw_reset(bp, 0); 12978 usleep_range(5000, 10000); 12979 for (port = 0; port < PORT_MAX; port++) { 12980 u32 shmem_base, shmem2_base; 12981 12982 /* In E2, same phy is using for port0 of the two paths */ 12983 if (CHIP_IS_E1x(bp)) { 12984 shmem_base = shmem_base_path[0]; 12985 shmem2_base = shmem2_base_path[0]; 12986 } else { 12987 shmem_base = shmem_base_path[port]; 12988 shmem2_base = shmem2_base_path[port]; 12989 } 12990 /* Extract the ext phy address for the port */ 12991 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base, 12992 port, &phy) != 12993 0) { 12994 DP(NETIF_MSG_LINK, "populate phy failed\n"); 12995 return -EINVAL; 12996 } 12997 12998 /* Reset phy*/ 12999 bnx2x_cl45_write(bp, &phy, 13000 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001); 13001 13002 13003 /* Set fault module detected LED on */ 13004 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0, 13005 MISC_REGISTERS_GPIO_HIGH, 13006 port); 13007 } 13008 13009 return 0; 13010 } 13011 static void bnx2x_get_ext_phy_reset_gpio(struct bnx2x *bp, u32 shmem_base, 13012 u8 *io_gpio, u8 *io_port) 13013 { 13014 13015 u32 phy_gpio_reset = REG_RD(bp, shmem_base + 13016 offsetof(struct shmem_region, 13017 dev_info.port_hw_config[PORT_0].default_cfg)); 13018 switch (phy_gpio_reset) { 13019 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0: 13020 *io_gpio = 0; 13021 *io_port = 0; 13022 break; 13023 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0: 13024 *io_gpio = 1; 13025 *io_port = 0; 13026 break; 13027 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0: 13028 *io_gpio = 2; 13029 *io_port = 0; 13030 break; 13031 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0: 13032 *io_gpio = 3; 13033 *io_port = 0; 13034 break; 13035 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1: 13036 *io_gpio = 0; 13037 *io_port = 1; 13038 break; 13039 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1: 13040 *io_gpio = 1; 13041 *io_port = 1; 13042 break; 13043 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1: 13044 *io_gpio = 2; 13045 *io_port = 1; 13046 break; 13047 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1: 13048 *io_gpio = 3; 13049 *io_port = 1; 13050 break; 13051 default: 13052 /* Don't override the io_gpio and io_port */ 13053 break; 13054 } 13055 } 13056 13057 static int bnx2x_8727_common_init_phy(struct bnx2x *bp, 13058 u32 shmem_base_path[], 13059 u32 shmem2_base_path[], u8 phy_index, 13060 u32 chip_id) 13061 { 13062 s8 port, reset_gpio; 13063 u32 swap_val, swap_override; 13064 struct bnx2x_phy phy[PORT_MAX]; 13065 struct bnx2x_phy *phy_blk[PORT_MAX]; 13066 s8 port_of_path; 13067 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); 13068 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); 13069 13070 reset_gpio = MISC_REGISTERS_GPIO_1; 13071 port = 1; 13072 13073 /* Retrieve the reset gpio/port which control the reset. 13074 * Default is GPIO1, PORT1 13075 */ 13076 bnx2x_get_ext_phy_reset_gpio(bp, shmem_base_path[0], 13077 (u8 *)&reset_gpio, (u8 *)&port); 13078 13079 /* Calculate the port based on port swap */ 13080 port ^= (swap_val && swap_override); 13081 13082 /* Initiate PHY reset*/ 13083 bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_LOW, 13084 port); 13085 usleep_range(1000, 2000); 13086 bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_HIGH, 13087 port); 13088 13089 usleep_range(5000, 10000); 13090 13091 /* PART1 - Reset both phys */ 13092 for (port = PORT_MAX - 1; port >= PORT_0; port--) { 13093 u32 shmem_base, shmem2_base; 13094 13095 /* In E2, same phy is using for port0 of the two paths */ 13096 if (CHIP_IS_E1x(bp)) { 13097 shmem_base = shmem_base_path[0]; 13098 shmem2_base = shmem2_base_path[0]; 13099 port_of_path = port; 13100 } else { 13101 shmem_base = shmem_base_path[port]; 13102 shmem2_base = shmem2_base_path[port]; 13103 port_of_path = 0; 13104 } 13105 13106 /* Extract the ext phy address for the port */ 13107 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base, 13108 port_of_path, &phy[port]) != 13109 0) { 13110 DP(NETIF_MSG_LINK, "populate phy failed\n"); 13111 return -EINVAL; 13112 } 13113 /* disable attentions */ 13114 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + 13115 port_of_path*4, 13116 (NIG_MASK_XGXS0_LINK_STATUS | 13117 NIG_MASK_XGXS0_LINK10G | 13118 NIG_MASK_SERDES0_LINK_STATUS | 13119 NIG_MASK_MI_INT)); 13120 13121 13122 /* Reset the phy */ 13123 bnx2x_cl45_write(bp, &phy[port], 13124 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15); 13125 } 13126 13127 /* Add delay of 150ms after reset */ 13128 msleep(150); 13129 if (phy[PORT_0].addr & 0x1) { 13130 phy_blk[PORT_0] = &(phy[PORT_1]); 13131 phy_blk[PORT_1] = &(phy[PORT_0]); 13132 } else { 13133 phy_blk[PORT_0] = &(phy[PORT_0]); 13134 phy_blk[PORT_1] = &(phy[PORT_1]); 13135 } 13136 /* PART2 - Download firmware to both phys */ 13137 for (port = PORT_MAX - 1; port >= PORT_0; port--) { 13138 if (CHIP_IS_E1x(bp)) 13139 port_of_path = port; 13140 else 13141 port_of_path = 0; 13142 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n", 13143 phy_blk[port]->addr); 13144 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port], 13145 port_of_path)) 13146 return -EINVAL; 13147 /* Disable PHY transmitter output */ 13148 bnx2x_cl45_write(bp, phy_blk[port], 13149 MDIO_PMA_DEVAD, 13150 MDIO_PMA_REG_TX_DISABLE, 1); 13151 13152 } 13153 return 0; 13154 } 13155 13156 static int bnx2x_84833_common_init_phy(struct bnx2x *bp, 13157 u32 shmem_base_path[], 13158 u32 shmem2_base_path[], 13159 u8 phy_index, 13160 u32 chip_id) 13161 { 13162 u8 reset_gpios; 13163 reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path, chip_id); 13164 bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW); 13165 udelay(10); 13166 bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_HIGH); 13167 DP(NETIF_MSG_LINK, "84833 reset pulse on pin values 0x%x\n", 13168 reset_gpios); 13169 return 0; 13170 } 13171 13172 static int bnx2x_ext_phy_common_init(struct bnx2x *bp, u32 shmem_base_path[], 13173 u32 shmem2_base_path[], u8 phy_index, 13174 u32 ext_phy_type, u32 chip_id) 13175 { 13176 int rc = 0; 13177 13178 switch (ext_phy_type) { 13179 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073: 13180 rc = bnx2x_8073_common_init_phy(bp, shmem_base_path, 13181 shmem2_base_path, 13182 phy_index, chip_id); 13183 break; 13184 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722: 13185 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: 13186 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC: 13187 rc = bnx2x_8727_common_init_phy(bp, shmem_base_path, 13188 shmem2_base_path, 13189 phy_index, chip_id); 13190 break; 13191 13192 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: 13193 /* GPIO1 affects both ports, so there's need to pull 13194 * it for single port alone 13195 */ 13196 rc = bnx2x_8726_common_init_phy(bp, shmem_base_path, 13197 shmem2_base_path, 13198 phy_index, chip_id); 13199 break; 13200 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833: 13201 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834: 13202 /* GPIO3's are linked, and so both need to be toggled 13203 * to obtain required 2us pulse. 13204 */ 13205 rc = bnx2x_84833_common_init_phy(bp, shmem_base_path, 13206 shmem2_base_path, 13207 phy_index, chip_id); 13208 break; 13209 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE: 13210 rc = -EINVAL; 13211 break; 13212 default: 13213 DP(NETIF_MSG_LINK, 13214 "ext_phy 0x%x common init not required\n", 13215 ext_phy_type); 13216 break; 13217 } 13218 13219 if (rc) 13220 netdev_err(bp->dev, "Warning: PHY was not initialized," 13221 " Port %d\n", 13222 0); 13223 return rc; 13224 } 13225 13226 int bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base_path[], 13227 u32 shmem2_base_path[], u32 chip_id) 13228 { 13229 int rc = 0; 13230 u32 phy_ver, val; 13231 u8 phy_index = 0; 13232 u32 ext_phy_type, ext_phy_config; 13233 13234 bnx2x_set_mdio_clk(bp, chip_id, GRCBASE_EMAC0); 13235 bnx2x_set_mdio_clk(bp, chip_id, GRCBASE_EMAC1); 13236 DP(NETIF_MSG_LINK, "Begin common phy init\n"); 13237 if (CHIP_IS_E3(bp)) { 13238 /* Enable EPIO */ 13239 val = REG_RD(bp, MISC_REG_GEN_PURP_HWG); 13240 REG_WR(bp, MISC_REG_GEN_PURP_HWG, val | 1); 13241 } 13242 /* Check if common init was already done */ 13243 phy_ver = REG_RD(bp, shmem_base_path[0] + 13244 offsetof(struct shmem_region, 13245 port_mb[PORT_0].ext_phy_fw_version)); 13246 if (phy_ver) { 13247 DP(NETIF_MSG_LINK, "Not doing common init; phy ver is 0x%x\n", 13248 phy_ver); 13249 return 0; 13250 } 13251 13252 /* Read the ext_phy_type for arbitrary port(0) */ 13253 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS; 13254 phy_index++) { 13255 ext_phy_config = bnx2x_get_ext_phy_config(bp, 13256 shmem_base_path[0], 13257 phy_index, 0); 13258 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config); 13259 rc |= bnx2x_ext_phy_common_init(bp, shmem_base_path, 13260 shmem2_base_path, 13261 phy_index, ext_phy_type, 13262 chip_id); 13263 } 13264 return rc; 13265 } 13266 13267 static void bnx2x_check_over_curr(struct link_params *params, 13268 struct link_vars *vars) 13269 { 13270 struct bnx2x *bp = params->bp; 13271 u32 cfg_pin; 13272 u8 port = params->port; 13273 u32 pin_val; 13274 13275 cfg_pin = (REG_RD(bp, params->shmem_base + 13276 offsetof(struct shmem_region, 13277 dev_info.port_hw_config[port].e3_cmn_pin_cfg1)) & 13278 PORT_HW_CFG_E3_OVER_CURRENT_MASK) >> 13279 PORT_HW_CFG_E3_OVER_CURRENT_SHIFT; 13280 13281 /* Ignore check if no external input PIN available */ 13282 if (bnx2x_get_cfg_pin(bp, cfg_pin, &pin_val) != 0) 13283 return; 13284 13285 if (!pin_val) { 13286 if ((vars->phy_flags & PHY_OVER_CURRENT_FLAG) == 0) { 13287 netdev_err(bp->dev, "Error: Power fault on Port %d has" 13288 " been detected and the power to " 13289 "that SFP+ module has been removed" 13290 " to prevent failure of the card." 13291 " Please remove the SFP+ module and" 13292 " restart the system to clear this" 13293 " error.\n", 13294 params->port); 13295 vars->phy_flags |= PHY_OVER_CURRENT_FLAG; 13296 bnx2x_warpcore_power_module(params, 0); 13297 } 13298 } else 13299 vars->phy_flags &= ~PHY_OVER_CURRENT_FLAG; 13300 } 13301 13302 /* Returns 0 if no change occured since last check; 1 otherwise. */ 13303 static u8 bnx2x_analyze_link_error(struct link_params *params, 13304 struct link_vars *vars, u32 status, 13305 u32 phy_flag, u32 link_flag, u8 notify) 13306 { 13307 struct bnx2x *bp = params->bp; 13308 /* Compare new value with previous value */ 13309 u8 led_mode; 13310 u32 old_status = (vars->phy_flags & phy_flag) ? 1 : 0; 13311 13312 if ((status ^ old_status) == 0) 13313 return 0; 13314 13315 /* If values differ */ 13316 switch (phy_flag) { 13317 case PHY_HALF_OPEN_CONN_FLAG: 13318 DP(NETIF_MSG_LINK, "Analyze Remote Fault\n"); 13319 break; 13320 case PHY_SFP_TX_FAULT_FLAG: 13321 DP(NETIF_MSG_LINK, "Analyze TX Fault\n"); 13322 break; 13323 default: 13324 DP(NETIF_MSG_LINK, "Analyze UNKNOWN\n"); 13325 } 13326 DP(NETIF_MSG_LINK, "Link changed:[%x %x]->%x\n", vars->link_up, 13327 old_status, status); 13328 13329 /* Do not touch the link in case physical link down */ 13330 if ((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0) 13331 return 1; 13332 13333 /* a. Update shmem->link_status accordingly 13334 * b. Update link_vars->link_up 13335 */ 13336 if (status) { 13337 vars->link_status &= ~LINK_STATUS_LINK_UP; 13338 vars->link_status |= link_flag; 13339 vars->link_up = 0; 13340 vars->phy_flags |= phy_flag; 13341 13342 /* activate nig drain */ 13343 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1); 13344 /* Set LED mode to off since the PHY doesn't know about these 13345 * errors 13346 */ 13347 led_mode = LED_MODE_OFF; 13348 } else { 13349 vars->link_status |= LINK_STATUS_LINK_UP; 13350 vars->link_status &= ~link_flag; 13351 vars->link_up = 1; 13352 vars->phy_flags &= ~phy_flag; 13353 led_mode = LED_MODE_OPER; 13354 13355 /* Clear nig drain */ 13356 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); 13357 } 13358 bnx2x_sync_link(params, vars); 13359 /* Update the LED according to the link state */ 13360 bnx2x_set_led(params, vars, led_mode, SPEED_10000); 13361 13362 /* Update link status in the shared memory */ 13363 bnx2x_update_mng(params, vars->link_status); 13364 13365 /* C. Trigger General Attention */ 13366 vars->periodic_flags |= PERIODIC_FLAGS_LINK_EVENT; 13367 if (notify) 13368 bnx2x_notify_link_changed(bp); 13369 13370 return 1; 13371 } 13372 13373 /****************************************************************************** 13374 * Description: 13375 * This function checks for half opened connection change indication. 13376 * When such change occurs, it calls the bnx2x_analyze_link_error 13377 * to check if Remote Fault is set or cleared. Reception of remote fault 13378 * status message in the MAC indicates that the peer's MAC has detected 13379 * a fault, for example, due to break in the TX side of fiber. 13380 * 13381 ******************************************************************************/ 13382 static int bnx2x_check_half_open_conn(struct link_params *params, 13383 struct link_vars *vars, 13384 u8 notify) 13385 { 13386 struct bnx2x *bp = params->bp; 13387 u32 lss_status = 0; 13388 u32 mac_base; 13389 /* In case link status is physically up @ 10G do */ 13390 if (((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0) || 13391 (REG_RD(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4))) 13392 return 0; 13393 13394 if (CHIP_IS_E3(bp) && 13395 (REG_RD(bp, MISC_REG_RESET_REG_2) & 13396 (MISC_REGISTERS_RESET_REG_2_XMAC))) { 13397 /* Check E3 XMAC */ 13398 /* Note that link speed cannot be queried here, since it may be 13399 * zero while link is down. In case UMAC is active, LSS will 13400 * simply not be set 13401 */ 13402 mac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; 13403 13404 /* Clear stick bits (Requires rising edge) */ 13405 REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0); 13406 REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 13407 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS | 13408 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS); 13409 if (REG_RD(bp, mac_base + XMAC_REG_RX_LSS_STATUS)) 13410 lss_status = 1; 13411 13412 bnx2x_analyze_link_error(params, vars, lss_status, 13413 PHY_HALF_OPEN_CONN_FLAG, 13414 LINK_STATUS_NONE, notify); 13415 } else if (REG_RD(bp, MISC_REG_RESET_REG_2) & 13416 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port)) { 13417 /* Check E1X / E2 BMAC */ 13418 u32 lss_status_reg; 13419 u32 wb_data[2]; 13420 mac_base = params->port ? NIG_REG_INGRESS_BMAC1_MEM : 13421 NIG_REG_INGRESS_BMAC0_MEM; 13422 /* Read BIGMAC_REGISTER_RX_LSS_STATUS */ 13423 if (CHIP_IS_E2(bp)) 13424 lss_status_reg = BIGMAC2_REGISTER_RX_LSS_STAT; 13425 else 13426 lss_status_reg = BIGMAC_REGISTER_RX_LSS_STATUS; 13427 13428 REG_RD_DMAE(bp, mac_base + lss_status_reg, wb_data, 2); 13429 lss_status = (wb_data[0] > 0); 13430 13431 bnx2x_analyze_link_error(params, vars, lss_status, 13432 PHY_HALF_OPEN_CONN_FLAG, 13433 LINK_STATUS_NONE, notify); 13434 } 13435 return 0; 13436 } 13437 static void bnx2x_sfp_tx_fault_detection(struct bnx2x_phy *phy, 13438 struct link_params *params, 13439 struct link_vars *vars) 13440 { 13441 struct bnx2x *bp = params->bp; 13442 u32 cfg_pin, value = 0; 13443 u8 led_change, port = params->port; 13444 13445 /* Get The SFP+ TX_Fault controlling pin ([eg]pio) */ 13446 cfg_pin = (REG_RD(bp, params->shmem_base + offsetof(struct shmem_region, 13447 dev_info.port_hw_config[port].e3_cmn_pin_cfg)) & 13448 PORT_HW_CFG_E3_TX_FAULT_MASK) >> 13449 PORT_HW_CFG_E3_TX_FAULT_SHIFT; 13450 13451 if (bnx2x_get_cfg_pin(bp, cfg_pin, &value)) { 13452 DP(NETIF_MSG_LINK, "Failed to read pin 0x%02x\n", cfg_pin); 13453 return; 13454 } 13455 13456 led_change = bnx2x_analyze_link_error(params, vars, value, 13457 PHY_SFP_TX_FAULT_FLAG, 13458 LINK_STATUS_SFP_TX_FAULT, 1); 13459 13460 if (led_change) { 13461 /* Change TX_Fault led, set link status for further syncs */ 13462 u8 led_mode; 13463 13464 if (vars->phy_flags & PHY_SFP_TX_FAULT_FLAG) { 13465 led_mode = MISC_REGISTERS_GPIO_HIGH; 13466 vars->link_status |= LINK_STATUS_SFP_TX_FAULT; 13467 } else { 13468 led_mode = MISC_REGISTERS_GPIO_LOW; 13469 vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT; 13470 } 13471 13472 /* If module is unapproved, led should be on regardless */ 13473 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED)) { 13474 DP(NETIF_MSG_LINK, "Change TX_Fault LED: ->%x\n", 13475 led_mode); 13476 bnx2x_set_e3_module_fault_led(params, led_mode); 13477 } 13478 } 13479 } 13480 static void bnx2x_kr2_recovery(struct link_params *params, 13481 struct link_vars *vars, 13482 struct bnx2x_phy *phy) 13483 { 13484 struct bnx2x *bp = params->bp; 13485 DP(NETIF_MSG_LINK, "KR2 recovery\n"); 13486 bnx2x_warpcore_enable_AN_KR2(phy, params, vars); 13487 bnx2x_warpcore_restart_AN_KR(phy, params); 13488 } 13489 13490 static void bnx2x_check_kr2_wa(struct link_params *params, 13491 struct link_vars *vars, 13492 struct bnx2x_phy *phy) 13493 { 13494 struct bnx2x *bp = params->bp; 13495 u16 base_page, next_page, not_kr2_device, lane; 13496 int sigdet; 13497 13498 /* Once KR2 was disabled, wait 5 seconds before checking KR2 recovery 13499 * Since some switches tend to reinit the AN process and clear the 13500 * the advertised BP/NP after ~2 seconds causing the KR2 to be disabled 13501 * and recovered many times 13502 */ 13503 if (vars->check_kr2_recovery_cnt > 0) { 13504 vars->check_kr2_recovery_cnt--; 13505 return; 13506 } 13507 13508 sigdet = bnx2x_warpcore_get_sigdet(phy, params); 13509 if (!sigdet) { 13510 if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) { 13511 bnx2x_kr2_recovery(params, vars, phy); 13512 DP(NETIF_MSG_LINK, "No sigdet\n"); 13513 } 13514 return; 13515 } 13516 13517 lane = bnx2x_get_warpcore_lane(phy, params); 13518 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, 13519 MDIO_AER_BLOCK_AER_REG, lane); 13520 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, 13521 MDIO_AN_REG_LP_AUTO_NEG, &base_page); 13522 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, 13523 MDIO_AN_REG_LP_AUTO_NEG2, &next_page); 13524 bnx2x_set_aer_mmd(params, phy); 13525 13526 /* CL73 has not begun yet */ 13527 if (base_page == 0) { 13528 if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) { 13529 bnx2x_kr2_recovery(params, vars, phy); 13530 DP(NETIF_MSG_LINK, "No BP\n"); 13531 } 13532 return; 13533 } 13534 13535 /* In case NP bit is not set in the BasePage, or it is set, 13536 * but only KX is advertised, declare this link partner as non-KR2 13537 * device. 13538 */ 13539 not_kr2_device = (((base_page & 0x8000) == 0) || 13540 (((base_page & 0x8000) && 13541 ((next_page & 0xe0) == 0x20)))); 13542 13543 /* In case KR2 is already disabled, check if we need to re-enable it */ 13544 if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) { 13545 if (!not_kr2_device) { 13546 DP(NETIF_MSG_LINK, "BP=0x%x, NP=0x%x\n", base_page, 13547 next_page); 13548 bnx2x_kr2_recovery(params, vars, phy); 13549 } 13550 return; 13551 } 13552 /* KR2 is enabled, but not KR2 device */ 13553 if (not_kr2_device) { 13554 /* Disable KR2 on both lanes */ 13555 DP(NETIF_MSG_LINK, "BP=0x%x, NP=0x%x\n", base_page, next_page); 13556 bnx2x_disable_kr2(params, vars, phy); 13557 /* Restart AN on leading lane */ 13558 bnx2x_warpcore_restart_AN_KR(phy, params); 13559 return; 13560 } 13561 } 13562 13563 void bnx2x_period_func(struct link_params *params, struct link_vars *vars) 13564 { 13565 u16 phy_idx; 13566 struct bnx2x *bp = params->bp; 13567 for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) { 13568 if (params->phy[phy_idx].flags & FLAGS_TX_ERROR_CHECK) { 13569 bnx2x_set_aer_mmd(params, ¶ms->phy[phy_idx]); 13570 if (bnx2x_check_half_open_conn(params, vars, 1) != 13571 0) 13572 DP(NETIF_MSG_LINK, "Fault detection failed\n"); 13573 break; 13574 } 13575 } 13576 13577 if (CHIP_IS_E3(bp)) { 13578 struct bnx2x_phy *phy = ¶ms->phy[INT_PHY]; 13579 bnx2x_set_aer_mmd(params, phy); 13580 if ((phy->supported & SUPPORTED_20000baseKR2_Full) && 13581 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) 13582 bnx2x_check_kr2_wa(params, vars, phy); 13583 bnx2x_check_over_curr(params, vars); 13584 if (vars->rx_tx_asic_rst) 13585 bnx2x_warpcore_config_runtime(phy, params, vars); 13586 13587 if ((REG_RD(bp, params->shmem_base + 13588 offsetof(struct shmem_region, dev_info. 13589 port_hw_config[params->port].default_cfg)) 13590 & PORT_HW_CFG_NET_SERDES_IF_MASK) == 13591 PORT_HW_CFG_NET_SERDES_IF_SFI) { 13592 if (bnx2x_is_sfp_module_plugged(phy, params)) { 13593 bnx2x_sfp_tx_fault_detection(phy, params, vars); 13594 } else if (vars->link_status & 13595 LINK_STATUS_SFP_TX_FAULT) { 13596 /* Clean trail, interrupt corrects the leds */ 13597 vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT; 13598 vars->phy_flags &= ~PHY_SFP_TX_FAULT_FLAG; 13599 /* Update link status in the shared memory */ 13600 bnx2x_update_mng(params, vars->link_status); 13601 } 13602 } 13603 } 13604 } 13605 13606 u8 bnx2x_fan_failure_det_req(struct bnx2x *bp, 13607 u32 shmem_base, 13608 u32 shmem2_base, 13609 u8 port) 13610 { 13611 u8 phy_index, fan_failure_det_req = 0; 13612 struct bnx2x_phy phy; 13613 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS; 13614 phy_index++) { 13615 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base, 13616 port, &phy) 13617 != 0) { 13618 DP(NETIF_MSG_LINK, "populate phy failed\n"); 13619 return 0; 13620 } 13621 fan_failure_det_req |= (phy.flags & 13622 FLAGS_FAN_FAILURE_DET_REQ); 13623 } 13624 return fan_failure_det_req; 13625 } 13626 13627 void bnx2x_hw_reset_phy(struct link_params *params) 13628 { 13629 u8 phy_index; 13630 struct bnx2x *bp = params->bp; 13631 bnx2x_update_mng(params, 0); 13632 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4, 13633 (NIG_MASK_XGXS0_LINK_STATUS | 13634 NIG_MASK_XGXS0_LINK10G | 13635 NIG_MASK_SERDES0_LINK_STATUS | 13636 NIG_MASK_MI_INT)); 13637 13638 for (phy_index = INT_PHY; phy_index < MAX_PHYS; 13639 phy_index++) { 13640 if (params->phy[phy_index].hw_reset) { 13641 params->phy[phy_index].hw_reset( 13642 ¶ms->phy[phy_index], 13643 params); 13644 params->phy[phy_index] = phy_null; 13645 } 13646 } 13647 } 13648 13649 void bnx2x_init_mod_abs_int(struct bnx2x *bp, struct link_vars *vars, 13650 u32 chip_id, u32 shmem_base, u32 shmem2_base, 13651 u8 port) 13652 { 13653 u8 gpio_num = 0xff, gpio_port = 0xff, phy_index; 13654 u32 val; 13655 u32 offset, aeu_mask, swap_val, swap_override, sync_offset; 13656 if (CHIP_IS_E3(bp)) { 13657 if (bnx2x_get_mod_abs_int_cfg(bp, chip_id, 13658 shmem_base, 13659 port, 13660 &gpio_num, 13661 &gpio_port) != 0) 13662 return; 13663 } else { 13664 struct bnx2x_phy phy; 13665 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS; 13666 phy_index++) { 13667 if (bnx2x_populate_phy(bp, phy_index, shmem_base, 13668 shmem2_base, port, &phy) 13669 != 0) { 13670 DP(NETIF_MSG_LINK, "populate phy failed\n"); 13671 return; 13672 } 13673 if (phy.type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) { 13674 gpio_num = MISC_REGISTERS_GPIO_3; 13675 gpio_port = port; 13676 break; 13677 } 13678 } 13679 } 13680 13681 if (gpio_num == 0xff) 13682 return; 13683 13684 /* Set GPIO3 to trigger SFP+ module insertion/removal */ 13685 bnx2x_set_gpio(bp, gpio_num, MISC_REGISTERS_GPIO_INPUT_HI_Z, gpio_port); 13686 13687 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); 13688 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); 13689 gpio_port ^= (swap_val && swap_override); 13690 13691 vars->aeu_int_mask = AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 << 13692 (gpio_num + (gpio_port << 2)); 13693 13694 sync_offset = shmem_base + 13695 offsetof(struct shmem_region, 13696 dev_info.port_hw_config[port].aeu_int_mask); 13697 REG_WR(bp, sync_offset, vars->aeu_int_mask); 13698 13699 DP(NETIF_MSG_LINK, "Setting MOD_ABS (GPIO%d_P%d) AEU to 0x%x\n", 13700 gpio_num, gpio_port, vars->aeu_int_mask); 13701 13702 if (port == 0) 13703 offset = MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0; 13704 else 13705 offset = MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0; 13706 13707 /* Open appropriate AEU for interrupts */ 13708 aeu_mask = REG_RD(bp, offset); 13709 aeu_mask |= vars->aeu_int_mask; 13710 REG_WR(bp, offset, aeu_mask); 13711 13712 /* Enable the GPIO to trigger interrupt */ 13713 val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN); 13714 val |= 1 << (gpio_num + (gpio_port << 2)); 13715 REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val); 13716 } 13717