1 /* Copyright 2008-2013 Broadcom Corporation 2 * Copyright (c) 2014 QLogic Corporation 3 * All rights reserved 4 * 5 * Unless you and QLogic execute a separate written software license 6 * agreement governing use of this software, this software is licensed to you 7 * under the terms of the GNU General Public License version 2, available 8 * at http://www.gnu.org/licenses/gpl-2.0.html (the "GPL"). 9 * 10 * Notwithstanding the above, under no circumstances may you combine this 11 * software in any way with any other Qlogic software provided under a 12 * license other than the GPL, without Qlogic's express prior written 13 * consent. 14 * 15 * Written by Yaniv Rosner 16 * 17 */ 18 19 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 20 21 #include <linux/kernel.h> 22 #include <linux/errno.h> 23 #include <linux/pci.h> 24 #include <linux/netdevice.h> 25 #include <linux/delay.h> 26 #include <linux/ethtool.h> 27 #include <linux/mutex.h> 28 29 #include "bnx2x.h" 30 #include "bnx2x_cmn.h" 31 32 typedef int (*read_sfp_module_eeprom_func_p)(struct bnx2x_phy *phy, 33 struct link_params *params, 34 u8 dev_addr, u16 addr, u8 byte_cnt, 35 u8 *o_buf, u8); 36 /********************************************************/ 37 #define MDIO_ACCESS_TIMEOUT 1000 38 #define WC_LANE_MAX 4 39 #define I2C_SWITCH_WIDTH 2 40 #define I2C_BSC0 0 41 #define I2C_BSC1 1 42 #define I2C_WA_RETRY_CNT 3 43 #define I2C_WA_PWR_ITER (I2C_WA_RETRY_CNT - 1) 44 #define MCPR_IMC_COMMAND_READ_OP 1 45 #define MCPR_IMC_COMMAND_WRITE_OP 2 46 47 /* LED Blink rate that will achieve ~15.9Hz */ 48 #define LED_BLINK_RATE_VAL_E3 354 49 #define LED_BLINK_RATE_VAL_E1X_E2 480 50 /***********************************************************/ 51 /* Shortcut definitions */ 52 /***********************************************************/ 53 54 #define NIG_LATCH_BC_ENABLE_MI_INT 0 55 56 #define NIG_STATUS_EMAC0_MI_INT \ 57 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT 58 #define NIG_STATUS_XGXS0_LINK10G \ 59 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G 60 #define NIG_STATUS_XGXS0_LINK_STATUS \ 61 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS 62 #define NIG_STATUS_XGXS0_LINK_STATUS_SIZE \ 63 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE 64 #define NIG_STATUS_SERDES0_LINK_STATUS \ 65 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS 66 #define NIG_MASK_MI_INT \ 67 NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT 68 #define NIG_MASK_XGXS0_LINK10G \ 69 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G 70 #define NIG_MASK_XGXS0_LINK_STATUS \ 71 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS 72 #define NIG_MASK_SERDES0_LINK_STATUS \ 73 NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS 74 75 #define MDIO_AN_CL73_OR_37_COMPLETE \ 76 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \ 77 MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE) 78 79 #define XGXS_RESET_BITS \ 80 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW | \ 81 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ | \ 82 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN | \ 83 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \ 84 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB) 85 86 #define SERDES_RESET_BITS \ 87 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \ 88 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ | \ 89 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN | \ 90 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD) 91 92 #define AUTONEG_CL37 SHARED_HW_CFG_AN_ENABLE_CL37 93 #define AUTONEG_CL73 SHARED_HW_CFG_AN_ENABLE_CL73 94 #define AUTONEG_BAM SHARED_HW_CFG_AN_ENABLE_BAM 95 #define AUTONEG_PARALLEL \ 96 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION 97 #define AUTONEG_SGMII_FIBER_AUTODET \ 98 SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT 99 #define AUTONEG_REMOTE_PHY SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY 100 101 #define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \ 102 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE 103 #define GP_STATUS_PAUSE_RSOLUTION_RXSIDE \ 104 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE 105 #define GP_STATUS_SPEED_MASK \ 106 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK 107 #define GP_STATUS_10M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M 108 #define GP_STATUS_100M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M 109 #define GP_STATUS_1G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G 110 #define GP_STATUS_2_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G 111 #define GP_STATUS_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G 112 #define GP_STATUS_6G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G 113 #define GP_STATUS_10G_HIG \ 114 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG 115 #define GP_STATUS_10G_CX4 \ 116 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4 117 #define GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX 118 #define GP_STATUS_10G_KX4 \ 119 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4 120 #define GP_STATUS_10G_KR MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR 121 #define GP_STATUS_10G_XFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI 122 #define GP_STATUS_20G_DXGXS MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS 123 #define GP_STATUS_10G_SFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI 124 #define GP_STATUS_20G_KR2 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_KR2 125 #define LINK_10THD LINK_STATUS_SPEED_AND_DUPLEX_10THD 126 #define LINK_10TFD LINK_STATUS_SPEED_AND_DUPLEX_10TFD 127 #define LINK_100TXHD LINK_STATUS_SPEED_AND_DUPLEX_100TXHD 128 #define LINK_100T4 LINK_STATUS_SPEED_AND_DUPLEX_100T4 129 #define LINK_100TXFD LINK_STATUS_SPEED_AND_DUPLEX_100TXFD 130 #define LINK_1000THD LINK_STATUS_SPEED_AND_DUPLEX_1000THD 131 #define LINK_1000TFD LINK_STATUS_SPEED_AND_DUPLEX_1000TFD 132 #define LINK_1000XFD LINK_STATUS_SPEED_AND_DUPLEX_1000XFD 133 #define LINK_2500THD LINK_STATUS_SPEED_AND_DUPLEX_2500THD 134 #define LINK_2500TFD LINK_STATUS_SPEED_AND_DUPLEX_2500TFD 135 #define LINK_2500XFD LINK_STATUS_SPEED_AND_DUPLEX_2500XFD 136 #define LINK_10GTFD LINK_STATUS_SPEED_AND_DUPLEX_10GTFD 137 #define LINK_10GXFD LINK_STATUS_SPEED_AND_DUPLEX_10GXFD 138 #define LINK_20GTFD LINK_STATUS_SPEED_AND_DUPLEX_20GTFD 139 #define LINK_20GXFD LINK_STATUS_SPEED_AND_DUPLEX_20GXFD 140 141 #define LINK_UPDATE_MASK \ 142 (LINK_STATUS_SPEED_AND_DUPLEX_MASK | \ 143 LINK_STATUS_LINK_UP | \ 144 LINK_STATUS_PHYSICAL_LINK_FLAG | \ 145 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE | \ 146 LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK | \ 147 LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK | \ 148 LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK | \ 149 LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE | \ 150 LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE) 151 152 #define SFP_EEPROM_CON_TYPE_ADDR 0x2 153 #define SFP_EEPROM_CON_TYPE_VAL_UNKNOWN 0x0 154 #define SFP_EEPROM_CON_TYPE_VAL_LC 0x7 155 #define SFP_EEPROM_CON_TYPE_VAL_COPPER 0x21 156 #define SFP_EEPROM_CON_TYPE_VAL_RJ45 0x22 157 158 159 #define SFP_EEPROM_10G_COMP_CODE_ADDR 0x3 160 #define SFP_EEPROM_10G_COMP_CODE_SR_MASK (1<<4) 161 #define SFP_EEPROM_10G_COMP_CODE_LR_MASK (1<<5) 162 #define SFP_EEPROM_10G_COMP_CODE_LRM_MASK (1<<6) 163 164 #define SFP_EEPROM_1G_COMP_CODE_ADDR 0x6 165 #define SFP_EEPROM_1G_COMP_CODE_SX (1<<0) 166 #define SFP_EEPROM_1G_COMP_CODE_LX (1<<1) 167 #define SFP_EEPROM_1G_COMP_CODE_CX (1<<2) 168 #define SFP_EEPROM_1G_COMP_CODE_BASE_T (1<<3) 169 170 #define SFP_EEPROM_FC_TX_TECH_ADDR 0x8 171 #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4 172 #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE 0x8 173 174 #define SFP_EEPROM_OPTIONS_ADDR 0x40 175 #define SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1 176 #define SFP_EEPROM_OPTIONS_SIZE 2 177 178 #define EDC_MODE_LINEAR 0x0022 179 #define EDC_MODE_LIMITING 0x0044 180 #define EDC_MODE_PASSIVE_DAC 0x0055 181 #define EDC_MODE_ACTIVE_DAC 0x0066 182 183 /* ETS defines*/ 184 #define DCBX_INVALID_COS (0xFF) 185 186 #define ETS_BW_LIMIT_CREDIT_UPPER_BOUND (0x5000) 187 #define ETS_BW_LIMIT_CREDIT_WEIGHT (0x5000) 188 #define ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS (1360) 189 #define ETS_E3B0_NIG_MIN_W_VAL_20GBPS (2720) 190 #define ETS_E3B0_PBF_MIN_W_VAL (10000) 191 192 #define MAX_PACKET_SIZE (9700) 193 #define MAX_KR_LINK_RETRY 4 194 #define DEFAULT_TX_DRV_BRDCT 2 195 #define DEFAULT_TX_DRV_IFIR 0 196 #define DEFAULT_TX_DRV_POST2 3 197 #define DEFAULT_TX_DRV_IPRE_DRIVER 6 198 199 /**********************************************************/ 200 /* INTERFACE */ 201 /**********************************************************/ 202 203 #define CL22_WR_OVER_CL45(_bp, _phy, _bank, _addr, _val) \ 204 bnx2x_cl45_write(_bp, _phy, \ 205 (_phy)->def_md_devad, \ 206 (_bank + (_addr & 0xf)), \ 207 _val) 208 209 #define CL22_RD_OVER_CL45(_bp, _phy, _bank, _addr, _val) \ 210 bnx2x_cl45_read(_bp, _phy, \ 211 (_phy)->def_md_devad, \ 212 (_bank + (_addr & 0xf)), \ 213 _val) 214 215 static int bnx2x_check_half_open_conn(struct link_params *params, 216 struct link_vars *vars, u8 notify); 217 static int bnx2x_sfp_module_detection(struct bnx2x_phy *phy, 218 struct link_params *params); 219 220 static u32 bnx2x_bits_en(struct bnx2x *bp, u32 reg, u32 bits) 221 { 222 u32 val = REG_RD(bp, reg); 223 224 val |= bits; 225 REG_WR(bp, reg, val); 226 return val; 227 } 228 229 static u32 bnx2x_bits_dis(struct bnx2x *bp, u32 reg, u32 bits) 230 { 231 u32 val = REG_RD(bp, reg); 232 233 val &= ~bits; 234 REG_WR(bp, reg, val); 235 return val; 236 } 237 238 /* 239 * bnx2x_check_lfa - This function checks if link reinitialization is required, 240 * or link flap can be avoided. 241 * 242 * @params: link parameters 243 * Returns 0 if Link Flap Avoidance conditions are met otherwise, the failed 244 * condition code. 245 */ 246 static int bnx2x_check_lfa(struct link_params *params) 247 { 248 u32 link_status, cfg_idx, lfa_mask, cfg_size; 249 u32 cur_speed_cap_mask, cur_req_fc_auto_adv, additional_config; 250 u32 saved_val, req_val, eee_status; 251 struct bnx2x *bp = params->bp; 252 253 additional_config = 254 REG_RD(bp, params->lfa_base + 255 offsetof(struct shmem_lfa, additional_config)); 256 257 /* NOTE: must be first condition checked - 258 * to verify DCC bit is cleared in any case! 259 */ 260 if (additional_config & NO_LFA_DUE_TO_DCC_MASK) { 261 DP(NETIF_MSG_LINK, "No LFA due to DCC flap after clp exit\n"); 262 REG_WR(bp, params->lfa_base + 263 offsetof(struct shmem_lfa, additional_config), 264 additional_config & ~NO_LFA_DUE_TO_DCC_MASK); 265 return LFA_DCC_LFA_DISABLED; 266 } 267 268 /* Verify that link is up */ 269 link_status = REG_RD(bp, params->shmem_base + 270 offsetof(struct shmem_region, 271 port_mb[params->port].link_status)); 272 if (!(link_status & LINK_STATUS_LINK_UP)) 273 return LFA_LINK_DOWN; 274 275 /* if loaded after BOOT from SAN, don't flap the link in any case and 276 * rely on link set by preboot driver 277 */ 278 if (params->feature_config_flags & FEATURE_CONFIG_BOOT_FROM_SAN) 279 return 0; 280 281 /* Verify that loopback mode is not set */ 282 if (params->loopback_mode) 283 return LFA_LOOPBACK_ENABLED; 284 285 /* Verify that MFW supports LFA */ 286 if (!params->lfa_base) 287 return LFA_MFW_IS_TOO_OLD; 288 289 if (params->num_phys == 3) { 290 cfg_size = 2; 291 lfa_mask = 0xffffffff; 292 } else { 293 cfg_size = 1; 294 lfa_mask = 0xffff; 295 } 296 297 /* Compare Duplex */ 298 saved_val = REG_RD(bp, params->lfa_base + 299 offsetof(struct shmem_lfa, req_duplex)); 300 req_val = params->req_duplex[0] | (params->req_duplex[1] << 16); 301 if ((saved_val & lfa_mask) != (req_val & lfa_mask)) { 302 DP(NETIF_MSG_LINK, "Duplex mismatch %x vs. %x\n", 303 (saved_val & lfa_mask), (req_val & lfa_mask)); 304 return LFA_DUPLEX_MISMATCH; 305 } 306 /* Compare Flow Control */ 307 saved_val = REG_RD(bp, params->lfa_base + 308 offsetof(struct shmem_lfa, req_flow_ctrl)); 309 req_val = params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16); 310 if ((saved_val & lfa_mask) != (req_val & lfa_mask)) { 311 DP(NETIF_MSG_LINK, "Flow control mismatch %x vs. %x\n", 312 (saved_val & lfa_mask), (req_val & lfa_mask)); 313 return LFA_FLOW_CTRL_MISMATCH; 314 } 315 /* Compare Link Speed */ 316 saved_val = REG_RD(bp, params->lfa_base + 317 offsetof(struct shmem_lfa, req_line_speed)); 318 req_val = params->req_line_speed[0] | (params->req_line_speed[1] << 16); 319 if ((saved_val & lfa_mask) != (req_val & lfa_mask)) { 320 DP(NETIF_MSG_LINK, "Link speed mismatch %x vs. %x\n", 321 (saved_val & lfa_mask), (req_val & lfa_mask)); 322 return LFA_LINK_SPEED_MISMATCH; 323 } 324 325 for (cfg_idx = 0; cfg_idx < cfg_size; cfg_idx++) { 326 cur_speed_cap_mask = REG_RD(bp, params->lfa_base + 327 offsetof(struct shmem_lfa, 328 speed_cap_mask[cfg_idx])); 329 330 if (cur_speed_cap_mask != params->speed_cap_mask[cfg_idx]) { 331 DP(NETIF_MSG_LINK, "Speed Cap mismatch %x vs. %x\n", 332 cur_speed_cap_mask, 333 params->speed_cap_mask[cfg_idx]); 334 return LFA_SPEED_CAP_MISMATCH; 335 } 336 } 337 338 cur_req_fc_auto_adv = 339 REG_RD(bp, params->lfa_base + 340 offsetof(struct shmem_lfa, additional_config)) & 341 REQ_FC_AUTO_ADV_MASK; 342 343 if ((u16)cur_req_fc_auto_adv != params->req_fc_auto_adv) { 344 DP(NETIF_MSG_LINK, "Flow Ctrl AN mismatch %x vs. %x\n", 345 cur_req_fc_auto_adv, params->req_fc_auto_adv); 346 return LFA_FLOW_CTRL_MISMATCH; 347 } 348 349 eee_status = REG_RD(bp, params->shmem2_base + 350 offsetof(struct shmem2_region, 351 eee_status[params->port])); 352 353 if (((eee_status & SHMEM_EEE_LPI_REQUESTED_BIT) ^ 354 (params->eee_mode & EEE_MODE_ENABLE_LPI)) || 355 ((eee_status & SHMEM_EEE_REQUESTED_BIT) ^ 356 (params->eee_mode & EEE_MODE_ADV_LPI))) { 357 DP(NETIF_MSG_LINK, "EEE mismatch %x vs. %x\n", params->eee_mode, 358 eee_status); 359 return LFA_EEE_MISMATCH; 360 } 361 362 /* LFA conditions are met */ 363 return 0; 364 } 365 /******************************************************************/ 366 /* EPIO/GPIO section */ 367 /******************************************************************/ 368 static void bnx2x_get_epio(struct bnx2x *bp, u32 epio_pin, u32 *en) 369 { 370 u32 epio_mask, gp_oenable; 371 *en = 0; 372 /* Sanity check */ 373 if (epio_pin > 31) { 374 DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to get\n", epio_pin); 375 return; 376 } 377 378 epio_mask = 1 << epio_pin; 379 /* Set this EPIO to output */ 380 gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE); 381 REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable & ~epio_mask); 382 383 *en = (REG_RD(bp, MCP_REG_MCPR_GP_INPUTS) & epio_mask) >> epio_pin; 384 } 385 static void bnx2x_set_epio(struct bnx2x *bp, u32 epio_pin, u32 en) 386 { 387 u32 epio_mask, gp_output, gp_oenable; 388 389 /* Sanity check */ 390 if (epio_pin > 31) { 391 DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to set\n", epio_pin); 392 return; 393 } 394 DP(NETIF_MSG_LINK, "Setting EPIO pin %d to %d\n", epio_pin, en); 395 epio_mask = 1 << epio_pin; 396 /* Set this EPIO to output */ 397 gp_output = REG_RD(bp, MCP_REG_MCPR_GP_OUTPUTS); 398 if (en) 399 gp_output |= epio_mask; 400 else 401 gp_output &= ~epio_mask; 402 403 REG_WR(bp, MCP_REG_MCPR_GP_OUTPUTS, gp_output); 404 405 /* Set the value for this EPIO */ 406 gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE); 407 REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable | epio_mask); 408 } 409 410 static void bnx2x_set_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 val) 411 { 412 if (pin_cfg == PIN_CFG_NA) 413 return; 414 if (pin_cfg >= PIN_CFG_EPIO0) { 415 bnx2x_set_epio(bp, pin_cfg - PIN_CFG_EPIO0, val); 416 } else { 417 u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3; 418 u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2; 419 bnx2x_set_gpio(bp, gpio_num, (u8)val, gpio_port); 420 } 421 } 422 423 static u32 bnx2x_get_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 *val) 424 { 425 if (pin_cfg == PIN_CFG_NA) 426 return -EINVAL; 427 if (pin_cfg >= PIN_CFG_EPIO0) { 428 bnx2x_get_epio(bp, pin_cfg - PIN_CFG_EPIO0, val); 429 } else { 430 u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3; 431 u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2; 432 *val = bnx2x_get_gpio(bp, gpio_num, gpio_port); 433 } 434 return 0; 435 436 } 437 /******************************************************************/ 438 /* ETS section */ 439 /******************************************************************/ 440 static void bnx2x_ets_e2e3a0_disabled(struct link_params *params) 441 { 442 /* ETS disabled configuration*/ 443 struct bnx2x *bp = params->bp; 444 445 DP(NETIF_MSG_LINK, "ETS E2E3 disabled configuration\n"); 446 447 /* mapping between entry priority to client number (0,1,2 -debug and 448 * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST) 449 * 3bits client num. 450 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0 451 * cos1-100 cos0-011 dbg1-010 dbg0-001 MCP-000 452 */ 453 454 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, 0x4688); 455 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves 456 * as strict. Bits 0,1,2 - debug and management entries, 3 - 457 * COS0 entry, 4 - COS1 entry. 458 * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT 459 * bit4 bit3 bit2 bit1 bit0 460 * MCP and debug are strict 461 */ 462 463 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7); 464 /* defines which entries (clients) are subjected to WFQ arbitration */ 465 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0); 466 /* For strict priority entries defines the number of consecutive 467 * slots for the highest priority. 468 */ 469 REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100); 470 /* mapping between the CREDIT_WEIGHT registers and actual client 471 * numbers 472 */ 473 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0); 474 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0); 475 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0); 476 477 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 0); 478 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 0); 479 REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, 0); 480 /* ETS mode disable */ 481 REG_WR(bp, PBF_REG_ETS_ENABLED, 0); 482 /* If ETS mode is enabled (there is no strict priority) defines a WFQ 483 * weight for COS0/COS1. 484 */ 485 REG_WR(bp, PBF_REG_COS0_WEIGHT, 0x2710); 486 REG_WR(bp, PBF_REG_COS1_WEIGHT, 0x2710); 487 /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter */ 488 REG_WR(bp, PBF_REG_COS0_UPPER_BOUND, 0x989680); 489 REG_WR(bp, PBF_REG_COS1_UPPER_BOUND, 0x989680); 490 /* Defines the number of consecutive slots for the strict priority */ 491 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0); 492 } 493 /****************************************************************************** 494 * Description: 495 * Getting min_w_val will be set according to line speed . 496 *. 497 ******************************************************************************/ 498 static u32 bnx2x_ets_get_min_w_val_nig(const struct link_vars *vars) 499 { 500 u32 min_w_val = 0; 501 /* Calculate min_w_val.*/ 502 if (vars->link_up) { 503 if (vars->line_speed == SPEED_20000) 504 min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS; 505 else 506 min_w_val = ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS; 507 } else 508 min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS; 509 /* If the link isn't up (static configuration for example ) The 510 * link will be according to 20GBPS. 511 */ 512 return min_w_val; 513 } 514 /****************************************************************************** 515 * Description: 516 * Getting credit upper bound form min_w_val. 517 *. 518 ******************************************************************************/ 519 static u32 bnx2x_ets_get_credit_upper_bound(const u32 min_w_val) 520 { 521 const u32 credit_upper_bound = (u32)MAXVAL((150 * min_w_val), 522 MAX_PACKET_SIZE); 523 return credit_upper_bound; 524 } 525 /****************************************************************************** 526 * Description: 527 * Set credit upper bound for NIG. 528 *. 529 ******************************************************************************/ 530 static void bnx2x_ets_e3b0_set_credit_upper_bound_nig( 531 const struct link_params *params, 532 const u32 min_w_val) 533 { 534 struct bnx2x *bp = params->bp; 535 const u8 port = params->port; 536 const u32 credit_upper_bound = 537 bnx2x_ets_get_credit_upper_bound(min_w_val); 538 539 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 : 540 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, credit_upper_bound); 541 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 : 542 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, credit_upper_bound); 543 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 : 544 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_2, credit_upper_bound); 545 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 : 546 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_3, credit_upper_bound); 547 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 : 548 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_4, credit_upper_bound); 549 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 : 550 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_5, credit_upper_bound); 551 552 if (!port) { 553 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6, 554 credit_upper_bound); 555 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7, 556 credit_upper_bound); 557 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8, 558 credit_upper_bound); 559 } 560 } 561 /****************************************************************************** 562 * Description: 563 * Will return the NIG ETS registers to init values.Except 564 * credit_upper_bound. 565 * That isn't used in this configuration (No WFQ is enabled) and will be 566 * configured according to spec 567 *. 568 ******************************************************************************/ 569 static void bnx2x_ets_e3b0_nig_disabled(const struct link_params *params, 570 const struct link_vars *vars) 571 { 572 struct bnx2x *bp = params->bp; 573 const u8 port = params->port; 574 const u32 min_w_val = bnx2x_ets_get_min_w_val_nig(vars); 575 /* Mapping between entry priority to client number (0,1,2 -debug and 576 * management clients, 3 - COS0 client, 4 - COS1, ... 8 - 577 * COS5)(HIGHEST) 4bits client num.TODO_ETS - Should be done by 578 * reset value or init tool 579 */ 580 if (port) { 581 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, 0x543210); 582 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB, 0x0); 583 } else { 584 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, 0x76543210); 585 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, 0x8); 586 } 587 /* For strict priority entries defines the number of consecutive 588 * slots for the highest priority. 589 */ 590 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS : 591 NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100); 592 /* Mapping between the CREDIT_WEIGHT registers and actual client 593 * numbers 594 */ 595 if (port) { 596 /*Port 1 has 6 COS*/ 597 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB, 0x210543); 598 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x0); 599 } else { 600 /*Port 0 has 9 COS*/ 601 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB, 602 0x43210876); 603 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x5); 604 } 605 606 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves 607 * as strict. Bits 0,1,2 - debug and management entries, 3 - 608 * COS0 entry, 4 - COS1 entry. 609 * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT 610 * bit4 bit3 bit2 bit1 bit0 611 * MCP and debug are strict 612 */ 613 if (port) 614 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT, 0x3f); 615 else 616 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1ff); 617 /* defines which entries (clients) are subjected to WFQ arbitration */ 618 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ : 619 NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0); 620 621 /* Please notice the register address are note continuous and a 622 * for here is note appropriate.In 2 port mode port0 only COS0-5 623 * can be used. DEBUG1,DEBUG1,MGMT are never used for WFQ* In 4 624 * port mode port1 only COS0-2 can be used. DEBUG1,DEBUG1,MGMT 625 * are never used for WFQ 626 */ 627 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 : 628 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0x0); 629 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 : 630 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0x0); 631 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 : 632 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2, 0x0); 633 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 : 634 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3, 0x0); 635 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 : 636 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4, 0x0); 637 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 : 638 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5, 0x0); 639 if (!port) { 640 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6, 0x0); 641 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7, 0x0); 642 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8, 0x0); 643 } 644 645 bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val); 646 } 647 /****************************************************************************** 648 * Description: 649 * Set credit upper bound for PBF. 650 *. 651 ******************************************************************************/ 652 static void bnx2x_ets_e3b0_set_credit_upper_bound_pbf( 653 const struct link_params *params, 654 const u32 min_w_val) 655 { 656 struct bnx2x *bp = params->bp; 657 const u32 credit_upper_bound = 658 bnx2x_ets_get_credit_upper_bound(min_w_val); 659 const u8 port = params->port; 660 u32 base_upper_bound = 0; 661 u8 max_cos = 0; 662 u8 i = 0; 663 /* In 2 port mode port0 has COS0-5 that can be used for WFQ.In 4 664 * port mode port1 has COS0-2 that can be used for WFQ. 665 */ 666 if (!port) { 667 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P0; 668 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0; 669 } else { 670 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P1; 671 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT1; 672 } 673 674 for (i = 0; i < max_cos; i++) 675 REG_WR(bp, base_upper_bound + (i << 2), credit_upper_bound); 676 } 677 678 /****************************************************************************** 679 * Description: 680 * Will return the PBF ETS registers to init values.Except 681 * credit_upper_bound. 682 * That isn't used in this configuration (No WFQ is enabled) and will be 683 * configured according to spec 684 *. 685 ******************************************************************************/ 686 static void bnx2x_ets_e3b0_pbf_disabled(const struct link_params *params) 687 { 688 struct bnx2x *bp = params->bp; 689 const u8 port = params->port; 690 const u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL; 691 u8 i = 0; 692 u32 base_weight = 0; 693 u8 max_cos = 0; 694 695 /* Mapping between entry priority to client number 0 - COS0 696 * client, 2 - COS1, ... 5 - COS5)(HIGHEST) 4bits client num. 697 * TODO_ETS - Should be done by reset value or init tool 698 */ 699 if (port) 700 /* 0x688 (|011|0 10|00 1|000) */ 701 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , 0x688); 702 else 703 /* (10 1|100 |011|0 10|00 1|000) */ 704 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , 0x2C688); 705 706 /* TODO_ETS - Should be done by reset value or init tool */ 707 if (port) 708 /* 0x688 (|011|0 10|00 1|000)*/ 709 REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1, 0x688); 710 else 711 /* 0x2C688 (10 1|100 |011|0 10|00 1|000) */ 712 REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0, 0x2C688); 713 714 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 : 715 PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0 , 0x100); 716 717 718 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 : 719 PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , 0); 720 721 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 : 722 PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0 , 0); 723 /* In 2 port mode port0 has COS0-5 that can be used for WFQ. 724 * In 4 port mode port1 has COS0-2 that can be used for WFQ. 725 */ 726 if (!port) { 727 base_weight = PBF_REG_COS0_WEIGHT_P0; 728 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0; 729 } else { 730 base_weight = PBF_REG_COS0_WEIGHT_P1; 731 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT1; 732 } 733 734 for (i = 0; i < max_cos; i++) 735 REG_WR(bp, base_weight + (0x4 * i), 0); 736 737 bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf); 738 } 739 /****************************************************************************** 740 * Description: 741 * E3B0 disable will return basically the values to init values. 742 *. 743 ******************************************************************************/ 744 static int bnx2x_ets_e3b0_disabled(const struct link_params *params, 745 const struct link_vars *vars) 746 { 747 struct bnx2x *bp = params->bp; 748 749 if (!CHIP_IS_E3B0(bp)) { 750 DP(NETIF_MSG_LINK, 751 "bnx2x_ets_e3b0_disabled the chip isn't E3B0\n"); 752 return -EINVAL; 753 } 754 755 bnx2x_ets_e3b0_nig_disabled(params, vars); 756 757 bnx2x_ets_e3b0_pbf_disabled(params); 758 759 return 0; 760 } 761 762 /****************************************************************************** 763 * Description: 764 * Disable will return basically the values to init values. 765 * 766 ******************************************************************************/ 767 int bnx2x_ets_disabled(struct link_params *params, 768 struct link_vars *vars) 769 { 770 struct bnx2x *bp = params->bp; 771 int bnx2x_status = 0; 772 773 if ((CHIP_IS_E2(bp)) || (CHIP_IS_E3A0(bp))) 774 bnx2x_ets_e2e3a0_disabled(params); 775 else if (CHIP_IS_E3B0(bp)) 776 bnx2x_status = bnx2x_ets_e3b0_disabled(params, vars); 777 else { 778 DP(NETIF_MSG_LINK, "bnx2x_ets_disabled - chip not supported\n"); 779 return -EINVAL; 780 } 781 782 return bnx2x_status; 783 } 784 785 /****************************************************************************** 786 * Description 787 * Set the COS mappimg to SP and BW until this point all the COS are not 788 * set as SP or BW. 789 ******************************************************************************/ 790 static int bnx2x_ets_e3b0_cli_map(const struct link_params *params, 791 const struct bnx2x_ets_params *ets_params, 792 const u8 cos_sp_bitmap, 793 const u8 cos_bw_bitmap) 794 { 795 struct bnx2x *bp = params->bp; 796 const u8 port = params->port; 797 const u8 nig_cli_sp_bitmap = 0x7 | (cos_sp_bitmap << 3); 798 const u8 pbf_cli_sp_bitmap = cos_sp_bitmap; 799 const u8 nig_cli_subject2wfq_bitmap = cos_bw_bitmap << 3; 800 const u8 pbf_cli_subject2wfq_bitmap = cos_bw_bitmap; 801 802 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT : 803 NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, nig_cli_sp_bitmap); 804 805 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 : 806 PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , pbf_cli_sp_bitmap); 807 808 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ : 809 NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 810 nig_cli_subject2wfq_bitmap); 811 812 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 : 813 PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0, 814 pbf_cli_subject2wfq_bitmap); 815 816 return 0; 817 } 818 819 /****************************************************************************** 820 * Description: 821 * This function is needed because NIG ARB_CREDIT_WEIGHT_X are 822 * not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable. 823 ******************************************************************************/ 824 static int bnx2x_ets_e3b0_set_cos_bw(struct bnx2x *bp, 825 const u8 cos_entry, 826 const u32 min_w_val_nig, 827 const u32 min_w_val_pbf, 828 const u16 total_bw, 829 const u8 bw, 830 const u8 port) 831 { 832 u32 nig_reg_adress_crd_weight = 0; 833 u32 pbf_reg_adress_crd_weight = 0; 834 /* Calculate and set BW for this COS - use 1 instead of 0 for BW */ 835 const u32 cos_bw_nig = ((bw ? bw : 1) * min_w_val_nig) / total_bw; 836 const u32 cos_bw_pbf = ((bw ? bw : 1) * min_w_val_pbf) / total_bw; 837 838 switch (cos_entry) { 839 case 0: 840 nig_reg_adress_crd_weight = 841 (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 : 842 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0; 843 pbf_reg_adress_crd_weight = (port) ? 844 PBF_REG_COS0_WEIGHT_P1 : PBF_REG_COS0_WEIGHT_P0; 845 break; 846 case 1: 847 nig_reg_adress_crd_weight = (port) ? 848 NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 : 849 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1; 850 pbf_reg_adress_crd_weight = (port) ? 851 PBF_REG_COS1_WEIGHT_P1 : PBF_REG_COS1_WEIGHT_P0; 852 break; 853 case 2: 854 nig_reg_adress_crd_weight = (port) ? 855 NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 : 856 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2; 857 858 pbf_reg_adress_crd_weight = (port) ? 859 PBF_REG_COS2_WEIGHT_P1 : PBF_REG_COS2_WEIGHT_P0; 860 break; 861 case 3: 862 if (port) 863 return -EINVAL; 864 nig_reg_adress_crd_weight = NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3; 865 pbf_reg_adress_crd_weight = PBF_REG_COS3_WEIGHT_P0; 866 break; 867 case 4: 868 if (port) 869 return -EINVAL; 870 nig_reg_adress_crd_weight = NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4; 871 pbf_reg_adress_crd_weight = PBF_REG_COS4_WEIGHT_P0; 872 break; 873 case 5: 874 if (port) 875 return -EINVAL; 876 nig_reg_adress_crd_weight = NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5; 877 pbf_reg_adress_crd_weight = PBF_REG_COS5_WEIGHT_P0; 878 break; 879 } 880 881 REG_WR(bp, nig_reg_adress_crd_weight, cos_bw_nig); 882 883 REG_WR(bp, pbf_reg_adress_crd_weight, cos_bw_pbf); 884 885 return 0; 886 } 887 /****************************************************************************** 888 * Description: 889 * Calculate the total BW.A value of 0 isn't legal. 890 * 891 ******************************************************************************/ 892 static int bnx2x_ets_e3b0_get_total_bw( 893 const struct link_params *params, 894 struct bnx2x_ets_params *ets_params, 895 u16 *total_bw) 896 { 897 struct bnx2x *bp = params->bp; 898 u8 cos_idx = 0; 899 u8 is_bw_cos_exist = 0; 900 901 *total_bw = 0 ; 902 /* Calculate total BW requested */ 903 for (cos_idx = 0; cos_idx < ets_params->num_of_cos; cos_idx++) { 904 if (ets_params->cos[cos_idx].state == bnx2x_cos_state_bw) { 905 is_bw_cos_exist = 1; 906 if (!ets_params->cos[cos_idx].params.bw_params.bw) { 907 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config BW" 908 "was set to 0\n"); 909 /* This is to prevent a state when ramrods 910 * can't be sent 911 */ 912 ets_params->cos[cos_idx].params.bw_params.bw 913 = 1; 914 } 915 *total_bw += 916 ets_params->cos[cos_idx].params.bw_params.bw; 917 } 918 } 919 920 /* Check total BW is valid */ 921 if ((is_bw_cos_exist == 1) && (*total_bw != 100)) { 922 if (*total_bw == 0) { 923 DP(NETIF_MSG_LINK, 924 "bnx2x_ets_E3B0_config total BW shouldn't be 0\n"); 925 return -EINVAL; 926 } 927 DP(NETIF_MSG_LINK, 928 "bnx2x_ets_E3B0_config total BW should be 100\n"); 929 /* We can handle a case whre the BW isn't 100 this can happen 930 * if the TC are joined. 931 */ 932 } 933 return 0; 934 } 935 936 /****************************************************************************** 937 * Description: 938 * Invalidate all the sp_pri_to_cos. 939 * 940 ******************************************************************************/ 941 static void bnx2x_ets_e3b0_sp_pri_to_cos_init(u8 *sp_pri_to_cos) 942 { 943 u8 pri = 0; 944 for (pri = 0; pri < DCBX_MAX_NUM_COS; pri++) 945 sp_pri_to_cos[pri] = DCBX_INVALID_COS; 946 } 947 /****************************************************************************** 948 * Description: 949 * Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers 950 * according to sp_pri_to_cos. 951 * 952 ******************************************************************************/ 953 static int bnx2x_ets_e3b0_sp_pri_to_cos_set(const struct link_params *params, 954 u8 *sp_pri_to_cos, const u8 pri, 955 const u8 cos_entry) 956 { 957 struct bnx2x *bp = params->bp; 958 const u8 port = params->port; 959 const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 : 960 DCBX_E3B0_MAX_NUM_COS_PORT0; 961 962 if (pri >= max_num_of_cos) { 963 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid " 964 "parameter Illegal strict priority\n"); 965 return -EINVAL; 966 } 967 968 if (sp_pri_to_cos[pri] != DCBX_INVALID_COS) { 969 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid " 970 "parameter There can't be two COS's with " 971 "the same strict pri\n"); 972 return -EINVAL; 973 } 974 975 sp_pri_to_cos[pri] = cos_entry; 976 return 0; 977 978 } 979 980 /****************************************************************************** 981 * Description: 982 * Returns the correct value according to COS and priority in 983 * the sp_pri_cli register. 984 * 985 ******************************************************************************/ 986 static u64 bnx2x_e3b0_sp_get_pri_cli_reg(const u8 cos, const u8 cos_offset, 987 const u8 pri_set, 988 const u8 pri_offset, 989 const u8 entry_size) 990 { 991 u64 pri_cli_nig = 0; 992 pri_cli_nig = ((u64)(cos + cos_offset)) << (entry_size * 993 (pri_set + pri_offset)); 994 995 return pri_cli_nig; 996 } 997 /****************************************************************************** 998 * Description: 999 * Returns the correct value according to COS and priority in the 1000 * sp_pri_cli register for NIG. 1001 * 1002 ******************************************************************************/ 1003 static u64 bnx2x_e3b0_sp_get_pri_cli_reg_nig(const u8 cos, const u8 pri_set) 1004 { 1005 /* MCP Dbg0 and dbg1 are always with higher strict pri*/ 1006 const u8 nig_cos_offset = 3; 1007 const u8 nig_pri_offset = 3; 1008 1009 return bnx2x_e3b0_sp_get_pri_cli_reg(cos, nig_cos_offset, pri_set, 1010 nig_pri_offset, 4); 1011 1012 } 1013 /****************************************************************************** 1014 * Description: 1015 * Returns the correct value according to COS and priority in the 1016 * sp_pri_cli register for PBF. 1017 * 1018 ******************************************************************************/ 1019 static u64 bnx2x_e3b0_sp_get_pri_cli_reg_pbf(const u8 cos, const u8 pri_set) 1020 { 1021 const u8 pbf_cos_offset = 0; 1022 const u8 pbf_pri_offset = 0; 1023 1024 return bnx2x_e3b0_sp_get_pri_cli_reg(cos, pbf_cos_offset, pri_set, 1025 pbf_pri_offset, 3); 1026 1027 } 1028 1029 /****************************************************************************** 1030 * Description: 1031 * Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers 1032 * according to sp_pri_to_cos.(which COS has higher priority) 1033 * 1034 ******************************************************************************/ 1035 static int bnx2x_ets_e3b0_sp_set_pri_cli_reg(const struct link_params *params, 1036 u8 *sp_pri_to_cos) 1037 { 1038 struct bnx2x *bp = params->bp; 1039 u8 i = 0; 1040 const u8 port = params->port; 1041 /* MCP Dbg0 and dbg1 are always with higher strict pri*/ 1042 u64 pri_cli_nig = 0x210; 1043 u32 pri_cli_pbf = 0x0; 1044 u8 pri_set = 0; 1045 u8 pri_bitmask = 0; 1046 const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 : 1047 DCBX_E3B0_MAX_NUM_COS_PORT0; 1048 1049 u8 cos_bit_to_set = (1 << max_num_of_cos) - 1; 1050 1051 /* Set all the strict priority first */ 1052 for (i = 0; i < max_num_of_cos; i++) { 1053 if (sp_pri_to_cos[i] != DCBX_INVALID_COS) { 1054 if (sp_pri_to_cos[i] >= DCBX_MAX_NUM_COS) { 1055 DP(NETIF_MSG_LINK, 1056 "bnx2x_ets_e3b0_sp_set_pri_cli_reg " 1057 "invalid cos entry\n"); 1058 return -EINVAL; 1059 } 1060 1061 pri_cli_nig |= bnx2x_e3b0_sp_get_pri_cli_reg_nig( 1062 sp_pri_to_cos[i], pri_set); 1063 1064 pri_cli_pbf |= bnx2x_e3b0_sp_get_pri_cli_reg_pbf( 1065 sp_pri_to_cos[i], pri_set); 1066 pri_bitmask = 1 << sp_pri_to_cos[i]; 1067 /* COS is used remove it from bitmap.*/ 1068 if (!(pri_bitmask & cos_bit_to_set)) { 1069 DP(NETIF_MSG_LINK, 1070 "bnx2x_ets_e3b0_sp_set_pri_cli_reg " 1071 "invalid There can't be two COS's with" 1072 " the same strict pri\n"); 1073 return -EINVAL; 1074 } 1075 cos_bit_to_set &= ~pri_bitmask; 1076 pri_set++; 1077 } 1078 } 1079 1080 /* Set all the Non strict priority i= COS*/ 1081 for (i = 0; i < max_num_of_cos; i++) { 1082 pri_bitmask = 1 << i; 1083 /* Check if COS was already used for SP */ 1084 if (pri_bitmask & cos_bit_to_set) { 1085 /* COS wasn't used for SP */ 1086 pri_cli_nig |= bnx2x_e3b0_sp_get_pri_cli_reg_nig( 1087 i, pri_set); 1088 1089 pri_cli_pbf |= bnx2x_e3b0_sp_get_pri_cli_reg_pbf( 1090 i, pri_set); 1091 /* COS is used remove it from bitmap.*/ 1092 cos_bit_to_set &= ~pri_bitmask; 1093 pri_set++; 1094 } 1095 } 1096 1097 if (pri_set != max_num_of_cos) { 1098 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_set_pri_cli_reg not all " 1099 "entries were set\n"); 1100 return -EINVAL; 1101 } 1102 1103 if (port) { 1104 /* Only 6 usable clients*/ 1105 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, 1106 (u32)pri_cli_nig); 1107 1108 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , pri_cli_pbf); 1109 } else { 1110 /* Only 9 usable clients*/ 1111 const u32 pri_cli_nig_lsb = (u32) (pri_cli_nig); 1112 const u32 pri_cli_nig_msb = (u32) ((pri_cli_nig >> 32) & 0xF); 1113 1114 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, 1115 pri_cli_nig_lsb); 1116 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, 1117 pri_cli_nig_msb); 1118 1119 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , pri_cli_pbf); 1120 } 1121 return 0; 1122 } 1123 1124 /****************************************************************************** 1125 * Description: 1126 * Configure the COS to ETS according to BW and SP settings. 1127 ******************************************************************************/ 1128 int bnx2x_ets_e3b0_config(const struct link_params *params, 1129 const struct link_vars *vars, 1130 struct bnx2x_ets_params *ets_params) 1131 { 1132 struct bnx2x *bp = params->bp; 1133 int bnx2x_status = 0; 1134 const u8 port = params->port; 1135 u16 total_bw = 0; 1136 const u32 min_w_val_nig = bnx2x_ets_get_min_w_val_nig(vars); 1137 const u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL; 1138 u8 cos_bw_bitmap = 0; 1139 u8 cos_sp_bitmap = 0; 1140 u8 sp_pri_to_cos[DCBX_MAX_NUM_COS] = {0}; 1141 const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 : 1142 DCBX_E3B0_MAX_NUM_COS_PORT0; 1143 u8 cos_entry = 0; 1144 1145 if (!CHIP_IS_E3B0(bp)) { 1146 DP(NETIF_MSG_LINK, 1147 "bnx2x_ets_e3b0_disabled the chip isn't E3B0\n"); 1148 return -EINVAL; 1149 } 1150 1151 if ((ets_params->num_of_cos > max_num_of_cos)) { 1152 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config the number of COS " 1153 "isn't supported\n"); 1154 return -EINVAL; 1155 } 1156 1157 /* Prepare sp strict priority parameters*/ 1158 bnx2x_ets_e3b0_sp_pri_to_cos_init(sp_pri_to_cos); 1159 1160 /* Prepare BW parameters*/ 1161 bnx2x_status = bnx2x_ets_e3b0_get_total_bw(params, ets_params, 1162 &total_bw); 1163 if (bnx2x_status) { 1164 DP(NETIF_MSG_LINK, 1165 "bnx2x_ets_E3B0_config get_total_bw failed\n"); 1166 return -EINVAL; 1167 } 1168 1169 /* Upper bound is set according to current link speed (min_w_val 1170 * should be the same for upper bound and COS credit val). 1171 */ 1172 bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val_nig); 1173 bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf); 1174 1175 1176 for (cos_entry = 0; cos_entry < ets_params->num_of_cos; cos_entry++) { 1177 if (bnx2x_cos_state_bw == ets_params->cos[cos_entry].state) { 1178 cos_bw_bitmap |= (1 << cos_entry); 1179 /* The function also sets the BW in HW(not the mappin 1180 * yet) 1181 */ 1182 bnx2x_status = bnx2x_ets_e3b0_set_cos_bw( 1183 bp, cos_entry, min_w_val_nig, min_w_val_pbf, 1184 total_bw, 1185 ets_params->cos[cos_entry].params.bw_params.bw, 1186 port); 1187 } else if (bnx2x_cos_state_strict == 1188 ets_params->cos[cos_entry].state){ 1189 cos_sp_bitmap |= (1 << cos_entry); 1190 1191 bnx2x_status = bnx2x_ets_e3b0_sp_pri_to_cos_set( 1192 params, 1193 sp_pri_to_cos, 1194 ets_params->cos[cos_entry].params.sp_params.pri, 1195 cos_entry); 1196 1197 } else { 1198 DP(NETIF_MSG_LINK, 1199 "bnx2x_ets_e3b0_config cos state not valid\n"); 1200 return -EINVAL; 1201 } 1202 if (bnx2x_status) { 1203 DP(NETIF_MSG_LINK, 1204 "bnx2x_ets_e3b0_config set cos bw failed\n"); 1205 return bnx2x_status; 1206 } 1207 } 1208 1209 /* Set SP register (which COS has higher priority) */ 1210 bnx2x_status = bnx2x_ets_e3b0_sp_set_pri_cli_reg(params, 1211 sp_pri_to_cos); 1212 1213 if (bnx2x_status) { 1214 DP(NETIF_MSG_LINK, 1215 "bnx2x_ets_E3B0_config set_pri_cli_reg failed\n"); 1216 return bnx2x_status; 1217 } 1218 1219 /* Set client mapping of BW and strict */ 1220 bnx2x_status = bnx2x_ets_e3b0_cli_map(params, ets_params, 1221 cos_sp_bitmap, 1222 cos_bw_bitmap); 1223 1224 if (bnx2x_status) { 1225 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config SP failed\n"); 1226 return bnx2x_status; 1227 } 1228 return 0; 1229 } 1230 static void bnx2x_ets_bw_limit_common(const struct link_params *params) 1231 { 1232 /* ETS disabled configuration */ 1233 struct bnx2x *bp = params->bp; 1234 DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n"); 1235 /* Defines which entries (clients) are subjected to WFQ arbitration 1236 * COS0 0x8 1237 * COS1 0x10 1238 */ 1239 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0x18); 1240 /* Mapping between the ARB_CREDIT_WEIGHT registers and actual 1241 * client numbers (WEIGHT_0 does not actually have to represent 1242 * client 0) 1243 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0 1244 * cos1-001 cos0-000 dbg1-100 dbg0-011 MCP-010 1245 */ 1246 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0x111A); 1247 1248 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 1249 ETS_BW_LIMIT_CREDIT_UPPER_BOUND); 1250 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 1251 ETS_BW_LIMIT_CREDIT_UPPER_BOUND); 1252 1253 /* ETS mode enabled*/ 1254 REG_WR(bp, PBF_REG_ETS_ENABLED, 1); 1255 1256 /* Defines the number of consecutive slots for the strict priority */ 1257 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0); 1258 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves 1259 * as strict. Bits 0,1,2 - debug and management entries, 3 - COS0 1260 * entry, 4 - COS1 entry. 1261 * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT 1262 * bit4 bit3 bit2 bit1 bit0 1263 * MCP and debug are strict 1264 */ 1265 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7); 1266 1267 /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter.*/ 1268 REG_WR(bp, PBF_REG_COS0_UPPER_BOUND, 1269 ETS_BW_LIMIT_CREDIT_UPPER_BOUND); 1270 REG_WR(bp, PBF_REG_COS1_UPPER_BOUND, 1271 ETS_BW_LIMIT_CREDIT_UPPER_BOUND); 1272 } 1273 1274 void bnx2x_ets_bw_limit(const struct link_params *params, const u32 cos0_bw, 1275 const u32 cos1_bw) 1276 { 1277 /* ETS disabled configuration*/ 1278 struct bnx2x *bp = params->bp; 1279 const u32 total_bw = cos0_bw + cos1_bw; 1280 u32 cos0_credit_weight = 0; 1281 u32 cos1_credit_weight = 0; 1282 1283 DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n"); 1284 1285 if ((!total_bw) || 1286 (!cos0_bw) || 1287 (!cos1_bw)) { 1288 DP(NETIF_MSG_LINK, "Total BW can't be zero\n"); 1289 return; 1290 } 1291 1292 cos0_credit_weight = (cos0_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/ 1293 total_bw; 1294 cos1_credit_weight = (cos1_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/ 1295 total_bw; 1296 1297 bnx2x_ets_bw_limit_common(params); 1298 1299 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, cos0_credit_weight); 1300 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, cos1_credit_weight); 1301 1302 REG_WR(bp, PBF_REG_COS0_WEIGHT, cos0_credit_weight); 1303 REG_WR(bp, PBF_REG_COS1_WEIGHT, cos1_credit_weight); 1304 } 1305 1306 int bnx2x_ets_strict(const struct link_params *params, const u8 strict_cos) 1307 { 1308 /* ETS disabled configuration*/ 1309 struct bnx2x *bp = params->bp; 1310 u32 val = 0; 1311 1312 DP(NETIF_MSG_LINK, "ETS enabled strict configuration\n"); 1313 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves 1314 * as strict. Bits 0,1,2 - debug and management entries, 1315 * 3 - COS0 entry, 4 - COS1 entry. 1316 * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT 1317 * bit4 bit3 bit2 bit1 bit0 1318 * MCP and debug are strict 1319 */ 1320 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1F); 1321 /* For strict priority entries defines the number of consecutive slots 1322 * for the highest priority. 1323 */ 1324 REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100); 1325 /* ETS mode disable */ 1326 REG_WR(bp, PBF_REG_ETS_ENABLED, 0); 1327 /* Defines the number of consecutive slots for the strict priority */ 1328 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0x100); 1329 1330 /* Defines the number of consecutive slots for the strict priority */ 1331 REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, strict_cos); 1332 1333 /* Mapping between entry priority to client number (0,1,2 -debug and 1334 * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST) 1335 * 3bits client num. 1336 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0 1337 * dbg0-010 dbg1-001 cos1-100 cos0-011 MCP-000 1338 * dbg0-010 dbg1-001 cos0-011 cos1-100 MCP-000 1339 */ 1340 val = (!strict_cos) ? 0x2318 : 0x22E0; 1341 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, val); 1342 1343 return 0; 1344 } 1345 1346 /******************************************************************/ 1347 /* PFC section */ 1348 /******************************************************************/ 1349 static void bnx2x_update_pfc_xmac(struct link_params *params, 1350 struct link_vars *vars, 1351 u8 is_lb) 1352 { 1353 struct bnx2x *bp = params->bp; 1354 u32 xmac_base; 1355 u32 pause_val, pfc0_val, pfc1_val; 1356 1357 /* XMAC base adrr */ 1358 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; 1359 1360 /* Initialize pause and pfc registers */ 1361 pause_val = 0x18000; 1362 pfc0_val = 0xFFFF8000; 1363 pfc1_val = 0x2; 1364 1365 /* No PFC support */ 1366 if (!(params->feature_config_flags & 1367 FEATURE_CONFIG_PFC_ENABLED)) { 1368 1369 /* RX flow control - Process pause frame in receive direction 1370 */ 1371 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX) 1372 pause_val |= XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN; 1373 1374 /* TX flow control - Send pause packet when buffer is full */ 1375 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) 1376 pause_val |= XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN; 1377 } else {/* PFC support */ 1378 pfc1_val |= XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN | 1379 XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN | 1380 XMAC_PFC_CTRL_HI_REG_RX_PFC_EN | 1381 XMAC_PFC_CTRL_HI_REG_TX_PFC_EN | 1382 XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON; 1383 /* Write pause and PFC registers */ 1384 REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val); 1385 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val); 1386 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val); 1387 pfc1_val &= ~XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON; 1388 1389 } 1390 1391 /* Write pause and PFC registers */ 1392 REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val); 1393 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val); 1394 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val); 1395 1396 1397 /* Set MAC address for source TX Pause/PFC frames */ 1398 REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_LO, 1399 ((params->mac_addr[2] << 24) | 1400 (params->mac_addr[3] << 16) | 1401 (params->mac_addr[4] << 8) | 1402 (params->mac_addr[5]))); 1403 REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_HI, 1404 ((params->mac_addr[0] << 8) | 1405 (params->mac_addr[1]))); 1406 1407 udelay(30); 1408 } 1409 1410 /******************************************************************/ 1411 /* MAC/PBF section */ 1412 /******************************************************************/ 1413 static void bnx2x_set_mdio_clk(struct bnx2x *bp, u32 chip_id, 1414 u32 emac_base) 1415 { 1416 u32 new_mode, cur_mode; 1417 u32 clc_cnt; 1418 /* Set clause 45 mode, slow down the MDIO clock to 2.5MHz 1419 * (a value of 49==0x31) and make sure that the AUTO poll is off 1420 */ 1421 cur_mode = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE); 1422 1423 if (USES_WARPCORE(bp)) 1424 clc_cnt = 74L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT; 1425 else 1426 clc_cnt = 49L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT; 1427 1428 if (((cur_mode & EMAC_MDIO_MODE_CLOCK_CNT) == clc_cnt) && 1429 (cur_mode & (EMAC_MDIO_MODE_CLAUSE_45))) 1430 return; 1431 1432 new_mode = cur_mode & 1433 ~(EMAC_MDIO_MODE_AUTO_POLL | EMAC_MDIO_MODE_CLOCK_CNT); 1434 new_mode |= clc_cnt; 1435 new_mode |= (EMAC_MDIO_MODE_CLAUSE_45); 1436 1437 DP(NETIF_MSG_LINK, "Changing emac_mode from 0x%x to 0x%x\n", 1438 cur_mode, new_mode); 1439 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE, new_mode); 1440 udelay(40); 1441 } 1442 1443 static void bnx2x_set_mdio_emac_per_phy(struct bnx2x *bp, 1444 struct link_params *params) 1445 { 1446 u8 phy_index; 1447 /* Set mdio clock per phy */ 1448 for (phy_index = INT_PHY; phy_index < params->num_phys; 1449 phy_index++) 1450 bnx2x_set_mdio_clk(bp, params->chip_id, 1451 params->phy[phy_index].mdio_ctrl); 1452 } 1453 1454 static u8 bnx2x_is_4_port_mode(struct bnx2x *bp) 1455 { 1456 u32 port4mode_ovwr_val; 1457 /* Check 4-port override enabled */ 1458 port4mode_ovwr_val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR); 1459 if (port4mode_ovwr_val & (1<<0)) { 1460 /* Return 4-port mode override value */ 1461 return ((port4mode_ovwr_val & (1<<1)) == (1<<1)); 1462 } 1463 /* Return 4-port mode from input pin */ 1464 return (u8)REG_RD(bp, MISC_REG_PORT4MODE_EN); 1465 } 1466 1467 static void bnx2x_emac_init(struct link_params *params, 1468 struct link_vars *vars) 1469 { 1470 /* reset and unreset the emac core */ 1471 struct bnx2x *bp = params->bp; 1472 u8 port = params->port; 1473 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; 1474 u32 val; 1475 u16 timeout; 1476 1477 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 1478 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port)); 1479 udelay(5); 1480 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 1481 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port)); 1482 1483 /* init emac - use read-modify-write */ 1484 /* self clear reset */ 1485 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE); 1486 EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET)); 1487 1488 timeout = 200; 1489 do { 1490 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE); 1491 DP(NETIF_MSG_LINK, "EMAC reset reg is %u\n", val); 1492 if (!timeout) { 1493 DP(NETIF_MSG_LINK, "EMAC timeout!\n"); 1494 return; 1495 } 1496 timeout--; 1497 } while (val & EMAC_MODE_RESET); 1498 1499 bnx2x_set_mdio_emac_per_phy(bp, params); 1500 /* Set mac address */ 1501 val = ((params->mac_addr[0] << 8) | 1502 params->mac_addr[1]); 1503 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH, val); 1504 1505 val = ((params->mac_addr[2] << 24) | 1506 (params->mac_addr[3] << 16) | 1507 (params->mac_addr[4] << 8) | 1508 params->mac_addr[5]); 1509 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + 4, val); 1510 } 1511 1512 static void bnx2x_set_xumac_nig(struct link_params *params, 1513 u16 tx_pause_en, 1514 u8 enable) 1515 { 1516 struct bnx2x *bp = params->bp; 1517 1518 REG_WR(bp, params->port ? NIG_REG_P1_MAC_IN_EN : NIG_REG_P0_MAC_IN_EN, 1519 enable); 1520 REG_WR(bp, params->port ? NIG_REG_P1_MAC_OUT_EN : NIG_REG_P0_MAC_OUT_EN, 1521 enable); 1522 REG_WR(bp, params->port ? NIG_REG_P1_MAC_PAUSE_OUT_EN : 1523 NIG_REG_P0_MAC_PAUSE_OUT_EN, tx_pause_en); 1524 } 1525 1526 static void bnx2x_set_umac_rxtx(struct link_params *params, u8 en) 1527 { 1528 u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0; 1529 u32 val; 1530 struct bnx2x *bp = params->bp; 1531 if (!(REG_RD(bp, MISC_REG_RESET_REG_2) & 1532 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port))) 1533 return; 1534 val = REG_RD(bp, umac_base + UMAC_REG_COMMAND_CONFIG); 1535 if (en) 1536 val |= (UMAC_COMMAND_CONFIG_REG_TX_ENA | 1537 UMAC_COMMAND_CONFIG_REG_RX_ENA); 1538 else 1539 val &= ~(UMAC_COMMAND_CONFIG_REG_TX_ENA | 1540 UMAC_COMMAND_CONFIG_REG_RX_ENA); 1541 /* Disable RX and TX */ 1542 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val); 1543 } 1544 1545 static void bnx2x_umac_enable(struct link_params *params, 1546 struct link_vars *vars, u8 lb) 1547 { 1548 u32 val; 1549 u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0; 1550 struct bnx2x *bp = params->bp; 1551 /* Reset UMAC */ 1552 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 1553 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port)); 1554 usleep_range(1000, 2000); 1555 1556 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 1557 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port)); 1558 1559 DP(NETIF_MSG_LINK, "enabling UMAC\n"); 1560 1561 /* This register opens the gate for the UMAC despite its name */ 1562 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1); 1563 1564 val = UMAC_COMMAND_CONFIG_REG_PROMIS_EN | 1565 UMAC_COMMAND_CONFIG_REG_PAD_EN | 1566 UMAC_COMMAND_CONFIG_REG_SW_RESET | 1567 UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK; 1568 switch (vars->line_speed) { 1569 case SPEED_10: 1570 val |= (0<<2); 1571 break; 1572 case SPEED_100: 1573 val |= (1<<2); 1574 break; 1575 case SPEED_1000: 1576 val |= (2<<2); 1577 break; 1578 case SPEED_2500: 1579 val |= (3<<2); 1580 break; 1581 default: 1582 DP(NETIF_MSG_LINK, "Invalid speed for UMAC %d\n", 1583 vars->line_speed); 1584 break; 1585 } 1586 if (!(vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)) 1587 val |= UMAC_COMMAND_CONFIG_REG_IGNORE_TX_PAUSE; 1588 1589 if (!(vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)) 1590 val |= UMAC_COMMAND_CONFIG_REG_PAUSE_IGNORE; 1591 1592 if (vars->duplex == DUPLEX_HALF) 1593 val |= UMAC_COMMAND_CONFIG_REG_HD_ENA; 1594 1595 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val); 1596 udelay(50); 1597 1598 /* Configure UMAC for EEE */ 1599 if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) { 1600 DP(NETIF_MSG_LINK, "configured UMAC for EEE\n"); 1601 REG_WR(bp, umac_base + UMAC_REG_UMAC_EEE_CTRL, 1602 UMAC_UMAC_EEE_CTRL_REG_EEE_EN); 1603 REG_WR(bp, umac_base + UMAC_REG_EEE_WAKE_TIMER, 0x11); 1604 } else { 1605 REG_WR(bp, umac_base + UMAC_REG_UMAC_EEE_CTRL, 0x0); 1606 } 1607 1608 /* Set MAC address for source TX Pause/PFC frames (under SW reset) */ 1609 REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR0, 1610 ((params->mac_addr[2] << 24) | 1611 (params->mac_addr[3] << 16) | 1612 (params->mac_addr[4] << 8) | 1613 (params->mac_addr[5]))); 1614 REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR1, 1615 ((params->mac_addr[0] << 8) | 1616 (params->mac_addr[1]))); 1617 1618 /* Enable RX and TX */ 1619 val &= ~UMAC_COMMAND_CONFIG_REG_PAD_EN; 1620 val |= UMAC_COMMAND_CONFIG_REG_TX_ENA | 1621 UMAC_COMMAND_CONFIG_REG_RX_ENA; 1622 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val); 1623 udelay(50); 1624 1625 /* Remove SW Reset */ 1626 val &= ~UMAC_COMMAND_CONFIG_REG_SW_RESET; 1627 1628 /* Check loopback mode */ 1629 if (lb) 1630 val |= UMAC_COMMAND_CONFIG_REG_LOOP_ENA; 1631 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val); 1632 1633 /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame 1634 * length used by the MAC receive logic to check frames. 1635 */ 1636 REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710); 1637 bnx2x_set_xumac_nig(params, 1638 ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1); 1639 vars->mac_type = MAC_TYPE_UMAC; 1640 1641 } 1642 1643 /* Define the XMAC mode */ 1644 static void bnx2x_xmac_init(struct link_params *params, u32 max_speed) 1645 { 1646 struct bnx2x *bp = params->bp; 1647 u32 is_port4mode = bnx2x_is_4_port_mode(bp); 1648 1649 /* In 4-port mode, need to set the mode only once, so if XMAC is 1650 * already out of reset, it means the mode has already been set, 1651 * and it must not* reset the XMAC again, since it controls both 1652 * ports of the path 1653 */ 1654 1655 if (((CHIP_NUM(bp) == CHIP_NUM_57840_4_10) || 1656 (CHIP_NUM(bp) == CHIP_NUM_57840_2_20) || 1657 (CHIP_NUM(bp) == CHIP_NUM_57840_OBSOLETE)) && 1658 is_port4mode && 1659 (REG_RD(bp, MISC_REG_RESET_REG_2) & 1660 MISC_REGISTERS_RESET_REG_2_XMAC)) { 1661 DP(NETIF_MSG_LINK, 1662 "XMAC already out of reset in 4-port mode\n"); 1663 return; 1664 } 1665 1666 /* Hard reset */ 1667 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 1668 MISC_REGISTERS_RESET_REG_2_XMAC); 1669 usleep_range(1000, 2000); 1670 1671 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 1672 MISC_REGISTERS_RESET_REG_2_XMAC); 1673 if (is_port4mode) { 1674 DP(NETIF_MSG_LINK, "Init XMAC to 2 ports x 10G per path\n"); 1675 1676 /* Set the number of ports on the system side to up to 2 */ 1677 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 1); 1678 1679 /* Set the number of ports on the Warp Core to 10G */ 1680 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3); 1681 } else { 1682 /* Set the number of ports on the system side to 1 */ 1683 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 0); 1684 if (max_speed == SPEED_10000) { 1685 DP(NETIF_MSG_LINK, 1686 "Init XMAC to 10G x 1 port per path\n"); 1687 /* Set the number of ports on the Warp Core to 10G */ 1688 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3); 1689 } else { 1690 DP(NETIF_MSG_LINK, 1691 "Init XMAC to 20G x 2 ports per path\n"); 1692 /* Set the number of ports on the Warp Core to 20G */ 1693 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 1); 1694 } 1695 } 1696 /* Soft reset */ 1697 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 1698 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT); 1699 usleep_range(1000, 2000); 1700 1701 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 1702 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT); 1703 1704 } 1705 1706 static void bnx2x_set_xmac_rxtx(struct link_params *params, u8 en) 1707 { 1708 u8 port = params->port; 1709 struct bnx2x *bp = params->bp; 1710 u32 pfc_ctrl, xmac_base = (port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; 1711 u32 val; 1712 1713 if (REG_RD(bp, MISC_REG_RESET_REG_2) & 1714 MISC_REGISTERS_RESET_REG_2_XMAC) { 1715 /* Send an indication to change the state in the NIG back to XON 1716 * Clearing this bit enables the next set of this bit to get 1717 * rising edge 1718 */ 1719 pfc_ctrl = REG_RD(bp, xmac_base + XMAC_REG_PFC_CTRL_HI); 1720 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, 1721 (pfc_ctrl & ~(1<<1))); 1722 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, 1723 (pfc_ctrl | (1<<1))); 1724 DP(NETIF_MSG_LINK, "Disable XMAC on port %x\n", port); 1725 val = REG_RD(bp, xmac_base + XMAC_REG_CTRL); 1726 if (en) 1727 val |= (XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN); 1728 else 1729 val &= ~(XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN); 1730 REG_WR(bp, xmac_base + XMAC_REG_CTRL, val); 1731 } 1732 } 1733 1734 static int bnx2x_xmac_enable(struct link_params *params, 1735 struct link_vars *vars, u8 lb) 1736 { 1737 u32 val, xmac_base; 1738 struct bnx2x *bp = params->bp; 1739 DP(NETIF_MSG_LINK, "enabling XMAC\n"); 1740 1741 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; 1742 1743 bnx2x_xmac_init(params, vars->line_speed); 1744 1745 /* This register determines on which events the MAC will assert 1746 * error on the i/f to the NIG along w/ EOP. 1747 */ 1748 1749 /* This register tells the NIG whether to send traffic to UMAC 1750 * or XMAC 1751 */ 1752 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 0); 1753 1754 /* When XMAC is in XLGMII mode, disable sending idles for fault 1755 * detection. 1756 */ 1757 if (!(params->phy[INT_PHY].flags & FLAGS_TX_ERROR_CHECK)) { 1758 REG_WR(bp, xmac_base + XMAC_REG_RX_LSS_CTRL, 1759 (XMAC_RX_LSS_CTRL_REG_LOCAL_FAULT_DISABLE | 1760 XMAC_RX_LSS_CTRL_REG_REMOTE_FAULT_DISABLE)); 1761 REG_WR(bp, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0); 1762 REG_WR(bp, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 1763 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS | 1764 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS); 1765 } 1766 /* Set Max packet size */ 1767 REG_WR(bp, xmac_base + XMAC_REG_RX_MAX_SIZE, 0x2710); 1768 1769 /* CRC append for Tx packets */ 1770 REG_WR(bp, xmac_base + XMAC_REG_TX_CTRL, 0xC800); 1771 1772 /* update PFC */ 1773 bnx2x_update_pfc_xmac(params, vars, 0); 1774 1775 if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) { 1776 DP(NETIF_MSG_LINK, "Setting XMAC for EEE\n"); 1777 REG_WR(bp, xmac_base + XMAC_REG_EEE_TIMERS_HI, 0x1380008); 1778 REG_WR(bp, xmac_base + XMAC_REG_EEE_CTRL, 0x1); 1779 } else { 1780 REG_WR(bp, xmac_base + XMAC_REG_EEE_CTRL, 0x0); 1781 } 1782 1783 /* Enable TX and RX */ 1784 val = XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN; 1785 1786 /* Set MAC in XLGMII mode for dual-mode */ 1787 if ((vars->line_speed == SPEED_20000) && 1788 (params->phy[INT_PHY].supported & 1789 SUPPORTED_20000baseKR2_Full)) 1790 val |= XMAC_CTRL_REG_XLGMII_ALIGN_ENB; 1791 1792 /* Check loopback mode */ 1793 if (lb) 1794 val |= XMAC_CTRL_REG_LINE_LOCAL_LPBK; 1795 REG_WR(bp, xmac_base + XMAC_REG_CTRL, val); 1796 bnx2x_set_xumac_nig(params, 1797 ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1); 1798 1799 vars->mac_type = MAC_TYPE_XMAC; 1800 1801 return 0; 1802 } 1803 1804 static int bnx2x_emac_enable(struct link_params *params, 1805 struct link_vars *vars, u8 lb) 1806 { 1807 struct bnx2x *bp = params->bp; 1808 u8 port = params->port; 1809 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; 1810 u32 val; 1811 1812 DP(NETIF_MSG_LINK, "enabling EMAC\n"); 1813 1814 /* Disable BMAC */ 1815 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 1816 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); 1817 1818 /* enable emac and not bmac */ 1819 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 1); 1820 1821 /* ASIC */ 1822 if (vars->phy_flags & PHY_XGXS_FLAG) { 1823 u32 ser_lane = ((params->lane_config & 1824 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >> 1825 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT); 1826 1827 DP(NETIF_MSG_LINK, "XGXS\n"); 1828 /* select the master lanes (out of 0-3) */ 1829 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, ser_lane); 1830 /* select XGXS */ 1831 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1); 1832 1833 } else { /* SerDes */ 1834 DP(NETIF_MSG_LINK, "SerDes\n"); 1835 /* select SerDes */ 1836 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0); 1837 } 1838 1839 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_RX_MODE, 1840 EMAC_RX_MODE_RESET); 1841 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE, 1842 EMAC_TX_MODE_RESET); 1843 1844 /* pause enable/disable */ 1845 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_RX_MODE, 1846 EMAC_RX_MODE_FLOW_EN); 1847 1848 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_TX_MODE, 1849 (EMAC_TX_MODE_EXT_PAUSE_EN | 1850 EMAC_TX_MODE_FLOW_EN)); 1851 if (!(params->feature_config_flags & 1852 FEATURE_CONFIG_PFC_ENABLED)) { 1853 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX) 1854 bnx2x_bits_en(bp, emac_base + 1855 EMAC_REG_EMAC_RX_MODE, 1856 EMAC_RX_MODE_FLOW_EN); 1857 1858 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) 1859 bnx2x_bits_en(bp, emac_base + 1860 EMAC_REG_EMAC_TX_MODE, 1861 (EMAC_TX_MODE_EXT_PAUSE_EN | 1862 EMAC_TX_MODE_FLOW_EN)); 1863 } else 1864 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE, 1865 EMAC_TX_MODE_FLOW_EN); 1866 1867 /* KEEP_VLAN_TAG, promiscuous */ 1868 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE); 1869 val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS; 1870 1871 /* Setting this bit causes MAC control frames (except for pause 1872 * frames) to be passed on for processing. This setting has no 1873 * affect on the operation of the pause frames. This bit effects 1874 * all packets regardless of RX Parser packet sorting logic. 1875 * Turn the PFC off to make sure we are in Xon state before 1876 * enabling it. 1877 */ 1878 EMAC_WR(bp, EMAC_REG_RX_PFC_MODE, 0); 1879 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) { 1880 DP(NETIF_MSG_LINK, "PFC is enabled\n"); 1881 /* Enable PFC again */ 1882 EMAC_WR(bp, EMAC_REG_RX_PFC_MODE, 1883 EMAC_REG_RX_PFC_MODE_RX_EN | 1884 EMAC_REG_RX_PFC_MODE_TX_EN | 1885 EMAC_REG_RX_PFC_MODE_PRIORITIES); 1886 1887 EMAC_WR(bp, EMAC_REG_RX_PFC_PARAM, 1888 ((0x0101 << 1889 EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT) | 1890 (0x00ff << 1891 EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT))); 1892 val |= EMAC_RX_MODE_KEEP_MAC_CONTROL; 1893 } 1894 EMAC_WR(bp, EMAC_REG_EMAC_RX_MODE, val); 1895 1896 /* Set Loopback */ 1897 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE); 1898 if (lb) 1899 val |= 0x810; 1900 else 1901 val &= ~0x810; 1902 EMAC_WR(bp, EMAC_REG_EMAC_MODE, val); 1903 1904 /* Enable emac */ 1905 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 1); 1906 1907 /* Enable emac for jumbo packets */ 1908 EMAC_WR(bp, EMAC_REG_EMAC_RX_MTU_SIZE, 1909 (EMAC_RX_MTU_SIZE_JUMBO_ENA | 1910 (ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVERHEAD))); 1911 1912 /* Strip CRC */ 1913 REG_WR(bp, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1); 1914 1915 /* Disable the NIG in/out to the bmac */ 1916 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x0); 1917 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0); 1918 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x0); 1919 1920 /* Enable the NIG in/out to the emac */ 1921 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x1); 1922 val = 0; 1923 if ((params->feature_config_flags & 1924 FEATURE_CONFIG_PFC_ENABLED) || 1925 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)) 1926 val = 1; 1927 1928 REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val); 1929 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1); 1930 1931 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x0); 1932 1933 vars->mac_type = MAC_TYPE_EMAC; 1934 return 0; 1935 } 1936 1937 static void bnx2x_update_pfc_bmac1(struct link_params *params, 1938 struct link_vars *vars) 1939 { 1940 u32 wb_data[2]; 1941 struct bnx2x *bp = params->bp; 1942 u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM : 1943 NIG_REG_INGRESS_BMAC0_MEM; 1944 1945 u32 val = 0x14; 1946 if ((!(params->feature_config_flags & 1947 FEATURE_CONFIG_PFC_ENABLED)) && 1948 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)) 1949 /* Enable BigMAC to react on received Pause packets */ 1950 val |= (1<<5); 1951 wb_data[0] = val; 1952 wb_data[1] = 0; 1953 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_CONTROL, wb_data, 2); 1954 1955 /* TX control */ 1956 val = 0xc0; 1957 if (!(params->feature_config_flags & 1958 FEATURE_CONFIG_PFC_ENABLED) && 1959 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)) 1960 val |= 0x800000; 1961 wb_data[0] = val; 1962 wb_data[1] = 0; 1963 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_CONTROL, wb_data, 2); 1964 } 1965 1966 static void bnx2x_update_pfc_bmac2(struct link_params *params, 1967 struct link_vars *vars, 1968 u8 is_lb) 1969 { 1970 /* Set rx control: Strip CRC and enable BigMAC to relay 1971 * control packets to the system as well 1972 */ 1973 u32 wb_data[2]; 1974 struct bnx2x *bp = params->bp; 1975 u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM : 1976 NIG_REG_INGRESS_BMAC0_MEM; 1977 u32 val = 0x14; 1978 1979 if ((!(params->feature_config_flags & 1980 FEATURE_CONFIG_PFC_ENABLED)) && 1981 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)) 1982 /* Enable BigMAC to react on received Pause packets */ 1983 val |= (1<<5); 1984 wb_data[0] = val; 1985 wb_data[1] = 0; 1986 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_CONTROL, wb_data, 2); 1987 udelay(30); 1988 1989 /* Tx control */ 1990 val = 0xc0; 1991 if (!(params->feature_config_flags & 1992 FEATURE_CONFIG_PFC_ENABLED) && 1993 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)) 1994 val |= 0x800000; 1995 wb_data[0] = val; 1996 wb_data[1] = 0; 1997 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_CONTROL, wb_data, 2); 1998 1999 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) { 2000 DP(NETIF_MSG_LINK, "PFC is enabled\n"); 2001 /* Enable PFC RX & TX & STATS and set 8 COS */ 2002 wb_data[0] = 0x0; 2003 wb_data[0] |= (1<<0); /* RX */ 2004 wb_data[0] |= (1<<1); /* TX */ 2005 wb_data[0] |= (1<<2); /* Force initial Xon */ 2006 wb_data[0] |= (1<<3); /* 8 cos */ 2007 wb_data[0] |= (1<<5); /* STATS */ 2008 wb_data[1] = 0; 2009 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, 2010 wb_data, 2); 2011 /* Clear the force Xon */ 2012 wb_data[0] &= ~(1<<2); 2013 } else { 2014 DP(NETIF_MSG_LINK, "PFC is disabled\n"); 2015 /* Disable PFC RX & TX & STATS and set 8 COS */ 2016 wb_data[0] = 0x8; 2017 wb_data[1] = 0; 2018 } 2019 2020 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, wb_data, 2); 2021 2022 /* Set Time (based unit is 512 bit time) between automatic 2023 * re-sending of PP packets amd enable automatic re-send of 2024 * Per-Priroity Packet as long as pp_gen is asserted and 2025 * pp_disable is low. 2026 */ 2027 val = 0x8000; 2028 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) 2029 val |= (1<<16); /* enable automatic re-send */ 2030 2031 wb_data[0] = val; 2032 wb_data[1] = 0; 2033 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_PAUSE_CONTROL, 2034 wb_data, 2); 2035 2036 /* mac control */ 2037 val = 0x3; /* Enable RX and TX */ 2038 if (is_lb) { 2039 val |= 0x4; /* Local loopback */ 2040 DP(NETIF_MSG_LINK, "enable bmac loopback\n"); 2041 } 2042 /* When PFC enabled, Pass pause frames towards the NIG. */ 2043 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) 2044 val |= ((1<<6)|(1<<5)); 2045 2046 wb_data[0] = val; 2047 wb_data[1] = 0; 2048 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2); 2049 } 2050 2051 /****************************************************************************** 2052 * Description: 2053 * This function is needed because NIG ARB_CREDIT_WEIGHT_X are 2054 * not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable. 2055 ******************************************************************************/ 2056 static int bnx2x_pfc_nig_rx_priority_mask(struct bnx2x *bp, 2057 u8 cos_entry, 2058 u32 priority_mask, u8 port) 2059 { 2060 u32 nig_reg_rx_priority_mask_add = 0; 2061 2062 switch (cos_entry) { 2063 case 0: 2064 nig_reg_rx_priority_mask_add = (port) ? 2065 NIG_REG_P1_RX_COS0_PRIORITY_MASK : 2066 NIG_REG_P0_RX_COS0_PRIORITY_MASK; 2067 break; 2068 case 1: 2069 nig_reg_rx_priority_mask_add = (port) ? 2070 NIG_REG_P1_RX_COS1_PRIORITY_MASK : 2071 NIG_REG_P0_RX_COS1_PRIORITY_MASK; 2072 break; 2073 case 2: 2074 nig_reg_rx_priority_mask_add = (port) ? 2075 NIG_REG_P1_RX_COS2_PRIORITY_MASK : 2076 NIG_REG_P0_RX_COS2_PRIORITY_MASK; 2077 break; 2078 case 3: 2079 if (port) 2080 return -EINVAL; 2081 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS3_PRIORITY_MASK; 2082 break; 2083 case 4: 2084 if (port) 2085 return -EINVAL; 2086 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS4_PRIORITY_MASK; 2087 break; 2088 case 5: 2089 if (port) 2090 return -EINVAL; 2091 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS5_PRIORITY_MASK; 2092 break; 2093 } 2094 2095 REG_WR(bp, nig_reg_rx_priority_mask_add, priority_mask); 2096 2097 return 0; 2098 } 2099 static void bnx2x_update_mng(struct link_params *params, u32 link_status) 2100 { 2101 struct bnx2x *bp = params->bp; 2102 2103 REG_WR(bp, params->shmem_base + 2104 offsetof(struct shmem_region, 2105 port_mb[params->port].link_status), link_status); 2106 } 2107 2108 static void bnx2x_update_link_attr(struct link_params *params, u32 link_attr) 2109 { 2110 struct bnx2x *bp = params->bp; 2111 2112 if (SHMEM2_HAS(bp, link_attr_sync)) 2113 REG_WR(bp, params->shmem2_base + 2114 offsetof(struct shmem2_region, 2115 link_attr_sync[params->port]), link_attr); 2116 } 2117 2118 static void bnx2x_update_pfc_nig(struct link_params *params, 2119 struct link_vars *vars, 2120 struct bnx2x_nig_brb_pfc_port_params *nig_params) 2121 { 2122 u32 xcm_mask = 0, ppp_enable = 0, pause_enable = 0, llfc_out_en = 0; 2123 u32 llfc_enable = 0, xcm_out_en = 0, hwpfc_enable = 0; 2124 u32 pkt_priority_to_cos = 0; 2125 struct bnx2x *bp = params->bp; 2126 u8 port = params->port; 2127 2128 int set_pfc = params->feature_config_flags & 2129 FEATURE_CONFIG_PFC_ENABLED; 2130 DP(NETIF_MSG_LINK, "updating pfc nig parameters\n"); 2131 2132 /* When NIG_LLH0_XCM_MASK_REG_LLHX_XCM_MASK_BCN bit is set 2133 * MAC control frames (that are not pause packets) 2134 * will be forwarded to the XCM. 2135 */ 2136 xcm_mask = REG_RD(bp, port ? NIG_REG_LLH1_XCM_MASK : 2137 NIG_REG_LLH0_XCM_MASK); 2138 /* NIG params will override non PFC params, since it's possible to 2139 * do transition from PFC to SAFC 2140 */ 2141 if (set_pfc) { 2142 pause_enable = 0; 2143 llfc_out_en = 0; 2144 llfc_enable = 0; 2145 if (CHIP_IS_E3(bp)) 2146 ppp_enable = 0; 2147 else 2148 ppp_enable = 1; 2149 xcm_mask &= ~(port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN : 2150 NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN); 2151 xcm_out_en = 0; 2152 hwpfc_enable = 1; 2153 } else { 2154 if (nig_params) { 2155 llfc_out_en = nig_params->llfc_out_en; 2156 llfc_enable = nig_params->llfc_enable; 2157 pause_enable = nig_params->pause_enable; 2158 } else /* Default non PFC mode - PAUSE */ 2159 pause_enable = 1; 2160 2161 xcm_mask |= (port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN : 2162 NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN); 2163 xcm_out_en = 1; 2164 } 2165 2166 if (CHIP_IS_E3(bp)) 2167 REG_WR(bp, port ? NIG_REG_BRB1_PAUSE_IN_EN : 2168 NIG_REG_BRB0_PAUSE_IN_EN, pause_enable); 2169 REG_WR(bp, port ? NIG_REG_LLFC_OUT_EN_1 : 2170 NIG_REG_LLFC_OUT_EN_0, llfc_out_en); 2171 REG_WR(bp, port ? NIG_REG_LLFC_ENABLE_1 : 2172 NIG_REG_LLFC_ENABLE_0, llfc_enable); 2173 REG_WR(bp, port ? NIG_REG_PAUSE_ENABLE_1 : 2174 NIG_REG_PAUSE_ENABLE_0, pause_enable); 2175 2176 REG_WR(bp, port ? NIG_REG_PPP_ENABLE_1 : 2177 NIG_REG_PPP_ENABLE_0, ppp_enable); 2178 2179 REG_WR(bp, port ? NIG_REG_LLH1_XCM_MASK : 2180 NIG_REG_LLH0_XCM_MASK, xcm_mask); 2181 2182 REG_WR(bp, port ? NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 : 2183 NIG_REG_LLFC_EGRESS_SRC_ENABLE_0, 0x7); 2184 2185 /* Output enable for RX_XCM # IF */ 2186 REG_WR(bp, port ? NIG_REG_XCM1_OUT_EN : 2187 NIG_REG_XCM0_OUT_EN, xcm_out_en); 2188 2189 /* HW PFC TX enable */ 2190 REG_WR(bp, port ? NIG_REG_P1_HWPFC_ENABLE : 2191 NIG_REG_P0_HWPFC_ENABLE, hwpfc_enable); 2192 2193 if (nig_params) { 2194 u8 i = 0; 2195 pkt_priority_to_cos = nig_params->pkt_priority_to_cos; 2196 2197 for (i = 0; i < nig_params->num_of_rx_cos_priority_mask; i++) 2198 bnx2x_pfc_nig_rx_priority_mask(bp, i, 2199 nig_params->rx_cos_priority_mask[i], port); 2200 2201 REG_WR(bp, port ? NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 : 2202 NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0, 2203 nig_params->llfc_high_priority_classes); 2204 2205 REG_WR(bp, port ? NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 : 2206 NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0, 2207 nig_params->llfc_low_priority_classes); 2208 } 2209 REG_WR(bp, port ? NIG_REG_P1_PKT_PRIORITY_TO_COS : 2210 NIG_REG_P0_PKT_PRIORITY_TO_COS, 2211 pkt_priority_to_cos); 2212 } 2213 2214 int bnx2x_update_pfc(struct link_params *params, 2215 struct link_vars *vars, 2216 struct bnx2x_nig_brb_pfc_port_params *pfc_params) 2217 { 2218 /* The PFC and pause are orthogonal to one another, meaning when 2219 * PFC is enabled, the pause are disabled, and when PFC is 2220 * disabled, pause are set according to the pause result. 2221 */ 2222 u32 val; 2223 struct bnx2x *bp = params->bp; 2224 u8 bmac_loopback = (params->loopback_mode == LOOPBACK_BMAC); 2225 2226 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) 2227 vars->link_status |= LINK_STATUS_PFC_ENABLED; 2228 else 2229 vars->link_status &= ~LINK_STATUS_PFC_ENABLED; 2230 2231 bnx2x_update_mng(params, vars->link_status); 2232 2233 /* Update NIG params */ 2234 bnx2x_update_pfc_nig(params, vars, pfc_params); 2235 2236 if (!vars->link_up) 2237 return 0; 2238 2239 DP(NETIF_MSG_LINK, "About to update PFC in BMAC\n"); 2240 2241 if (CHIP_IS_E3(bp)) { 2242 if (vars->mac_type == MAC_TYPE_XMAC) 2243 bnx2x_update_pfc_xmac(params, vars, 0); 2244 } else { 2245 val = REG_RD(bp, MISC_REG_RESET_REG_2); 2246 if ((val & 2247 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port)) 2248 == 0) { 2249 DP(NETIF_MSG_LINK, "About to update PFC in EMAC\n"); 2250 bnx2x_emac_enable(params, vars, 0); 2251 return 0; 2252 } 2253 if (CHIP_IS_E2(bp)) 2254 bnx2x_update_pfc_bmac2(params, vars, bmac_loopback); 2255 else 2256 bnx2x_update_pfc_bmac1(params, vars); 2257 2258 val = 0; 2259 if ((params->feature_config_flags & 2260 FEATURE_CONFIG_PFC_ENABLED) || 2261 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)) 2262 val = 1; 2263 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port*4, val); 2264 } 2265 return 0; 2266 } 2267 2268 static int bnx2x_bmac1_enable(struct link_params *params, 2269 struct link_vars *vars, 2270 u8 is_lb) 2271 { 2272 struct bnx2x *bp = params->bp; 2273 u8 port = params->port; 2274 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM : 2275 NIG_REG_INGRESS_BMAC0_MEM; 2276 u32 wb_data[2]; 2277 u32 val; 2278 2279 DP(NETIF_MSG_LINK, "Enabling BigMAC1\n"); 2280 2281 /* XGXS control */ 2282 wb_data[0] = 0x3c; 2283 wb_data[1] = 0; 2284 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_XGXS_CONTROL, 2285 wb_data, 2); 2286 2287 /* TX MAC SA */ 2288 wb_data[0] = ((params->mac_addr[2] << 24) | 2289 (params->mac_addr[3] << 16) | 2290 (params->mac_addr[4] << 8) | 2291 params->mac_addr[5]); 2292 wb_data[1] = ((params->mac_addr[0] << 8) | 2293 params->mac_addr[1]); 2294 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR, wb_data, 2); 2295 2296 /* MAC control */ 2297 val = 0x3; 2298 if (is_lb) { 2299 val |= 0x4; 2300 DP(NETIF_MSG_LINK, "enable bmac loopback\n"); 2301 } 2302 wb_data[0] = val; 2303 wb_data[1] = 0; 2304 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL, wb_data, 2); 2305 2306 /* Set rx mtu */ 2307 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVERHEAD; 2308 wb_data[1] = 0; 2309 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE, wb_data, 2); 2310 2311 bnx2x_update_pfc_bmac1(params, vars); 2312 2313 /* Set tx mtu */ 2314 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVERHEAD; 2315 wb_data[1] = 0; 2316 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE, wb_data, 2); 2317 2318 /* Set cnt max size */ 2319 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVERHEAD; 2320 wb_data[1] = 0; 2321 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE, wb_data, 2); 2322 2323 /* Configure SAFC */ 2324 wb_data[0] = 0x1000200; 2325 wb_data[1] = 0; 2326 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS, 2327 wb_data, 2); 2328 2329 return 0; 2330 } 2331 2332 static int bnx2x_bmac2_enable(struct link_params *params, 2333 struct link_vars *vars, 2334 u8 is_lb) 2335 { 2336 struct bnx2x *bp = params->bp; 2337 u8 port = params->port; 2338 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM : 2339 NIG_REG_INGRESS_BMAC0_MEM; 2340 u32 wb_data[2]; 2341 2342 DP(NETIF_MSG_LINK, "Enabling BigMAC2\n"); 2343 2344 wb_data[0] = 0; 2345 wb_data[1] = 0; 2346 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2); 2347 udelay(30); 2348 2349 /* XGXS control: Reset phy HW, MDIO registers, PHY PLL and BMAC */ 2350 wb_data[0] = 0x3c; 2351 wb_data[1] = 0; 2352 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_XGXS_CONTROL, 2353 wb_data, 2); 2354 2355 udelay(30); 2356 2357 /* TX MAC SA */ 2358 wb_data[0] = ((params->mac_addr[2] << 24) | 2359 (params->mac_addr[3] << 16) | 2360 (params->mac_addr[4] << 8) | 2361 params->mac_addr[5]); 2362 wb_data[1] = ((params->mac_addr[0] << 8) | 2363 params->mac_addr[1]); 2364 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_SOURCE_ADDR, 2365 wb_data, 2); 2366 2367 udelay(30); 2368 2369 /* Configure SAFC */ 2370 wb_data[0] = 0x1000200; 2371 wb_data[1] = 0; 2372 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS, 2373 wb_data, 2); 2374 udelay(30); 2375 2376 /* Set RX MTU */ 2377 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVERHEAD; 2378 wb_data[1] = 0; 2379 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_MAX_SIZE, wb_data, 2); 2380 udelay(30); 2381 2382 /* Set TX MTU */ 2383 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVERHEAD; 2384 wb_data[1] = 0; 2385 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_MAX_SIZE, wb_data, 2); 2386 udelay(30); 2387 /* Set cnt max size */ 2388 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVERHEAD - 2; 2389 wb_data[1] = 0; 2390 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_CNT_MAX_SIZE, wb_data, 2); 2391 udelay(30); 2392 bnx2x_update_pfc_bmac2(params, vars, is_lb); 2393 2394 return 0; 2395 } 2396 2397 static int bnx2x_bmac_enable(struct link_params *params, 2398 struct link_vars *vars, 2399 u8 is_lb, u8 reset_bmac) 2400 { 2401 int rc = 0; 2402 u8 port = params->port; 2403 struct bnx2x *bp = params->bp; 2404 u32 val; 2405 /* Reset and unreset the BigMac */ 2406 if (reset_bmac) { 2407 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 2408 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); 2409 usleep_range(1000, 2000); 2410 } 2411 2412 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 2413 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); 2414 2415 /* Enable access for bmac registers */ 2416 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1); 2417 2418 /* Enable BMAC according to BMAC type*/ 2419 if (CHIP_IS_E2(bp)) 2420 rc = bnx2x_bmac2_enable(params, vars, is_lb); 2421 else 2422 rc = bnx2x_bmac1_enable(params, vars, is_lb); 2423 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1); 2424 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0); 2425 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0); 2426 val = 0; 2427 if ((params->feature_config_flags & 2428 FEATURE_CONFIG_PFC_ENABLED) || 2429 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)) 2430 val = 1; 2431 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val); 2432 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0); 2433 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x0); 2434 REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0); 2435 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x1); 2436 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x1); 2437 2438 vars->mac_type = MAC_TYPE_BMAC; 2439 return rc; 2440 } 2441 2442 static void bnx2x_set_bmac_rx(struct bnx2x *bp, u32 chip_id, u8 port, u8 en) 2443 { 2444 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM : 2445 NIG_REG_INGRESS_BMAC0_MEM; 2446 u32 wb_data[2]; 2447 u32 nig_bmac_enable = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4); 2448 2449 if (CHIP_IS_E2(bp)) 2450 bmac_addr += BIGMAC2_REGISTER_BMAC_CONTROL; 2451 else 2452 bmac_addr += BIGMAC_REGISTER_BMAC_CONTROL; 2453 /* Only if the bmac is out of reset */ 2454 if (REG_RD(bp, MISC_REG_RESET_REG_2) & 2455 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) && 2456 nig_bmac_enable) { 2457 /* Clear Rx Enable bit in BMAC_CONTROL register */ 2458 REG_RD_DMAE(bp, bmac_addr, wb_data, 2); 2459 if (en) 2460 wb_data[0] |= BMAC_CONTROL_RX_ENABLE; 2461 else 2462 wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE; 2463 REG_WR_DMAE(bp, bmac_addr, wb_data, 2); 2464 usleep_range(1000, 2000); 2465 } 2466 } 2467 2468 static int bnx2x_pbf_update(struct link_params *params, u32 flow_ctrl, 2469 u32 line_speed) 2470 { 2471 struct bnx2x *bp = params->bp; 2472 u8 port = params->port; 2473 u32 init_crd, crd; 2474 u32 count = 1000; 2475 2476 /* Disable port */ 2477 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1); 2478 2479 /* Wait for init credit */ 2480 init_crd = REG_RD(bp, PBF_REG_P0_INIT_CRD + port*4); 2481 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8); 2482 DP(NETIF_MSG_LINK, "init_crd 0x%x crd 0x%x\n", init_crd, crd); 2483 2484 while ((init_crd != crd) && count) { 2485 usleep_range(5000, 10000); 2486 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8); 2487 count--; 2488 } 2489 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8); 2490 if (init_crd != crd) { 2491 DP(NETIF_MSG_LINK, "BUG! init_crd 0x%x != crd 0x%x\n", 2492 init_crd, crd); 2493 return -EINVAL; 2494 } 2495 2496 if (flow_ctrl & BNX2X_FLOW_CTRL_RX || 2497 line_speed == SPEED_10 || 2498 line_speed == SPEED_100 || 2499 line_speed == SPEED_1000 || 2500 line_speed == SPEED_2500) { 2501 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 1); 2502 /* Update threshold */ 2503 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, 0); 2504 /* Update init credit */ 2505 init_crd = 778; /* (800-18-4) */ 2506 2507 } else { 2508 u32 thresh = (ETH_MAX_JUMBO_PACKET_SIZE + 2509 ETH_OVERHEAD)/16; 2510 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0); 2511 /* Update threshold */ 2512 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, thresh); 2513 /* Update init credit */ 2514 switch (line_speed) { 2515 case SPEED_10000: 2516 init_crd = thresh + 553 - 22; 2517 break; 2518 default: 2519 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n", 2520 line_speed); 2521 return -EINVAL; 2522 } 2523 } 2524 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, init_crd); 2525 DP(NETIF_MSG_LINK, "PBF updated to speed %d credit %d\n", 2526 line_speed, init_crd); 2527 2528 /* Probe the credit changes */ 2529 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x1); 2530 usleep_range(5000, 10000); 2531 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x0); 2532 2533 /* Enable port */ 2534 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0); 2535 return 0; 2536 } 2537 2538 /** 2539 * bnx2x_get_emac_base - retrive emac base address 2540 * 2541 * @bp: driver handle 2542 * @mdc_mdio_access: access type 2543 * @port: port id 2544 * 2545 * This function selects the MDC/MDIO access (through emac0 or 2546 * emac1) depend on the mdc_mdio_access, port, port swapped. Each 2547 * phy has a default access mode, which could also be overridden 2548 * by nvram configuration. This parameter, whether this is the 2549 * default phy configuration, or the nvram overrun 2550 * configuration, is passed here as mdc_mdio_access and selects 2551 * the emac_base for the CL45 read/writes operations 2552 */ 2553 static u32 bnx2x_get_emac_base(struct bnx2x *bp, 2554 u32 mdc_mdio_access, u8 port) 2555 { 2556 u32 emac_base = 0; 2557 switch (mdc_mdio_access) { 2558 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE: 2559 break; 2560 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0: 2561 if (REG_RD(bp, NIG_REG_PORT_SWAP)) 2562 emac_base = GRCBASE_EMAC1; 2563 else 2564 emac_base = GRCBASE_EMAC0; 2565 break; 2566 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1: 2567 if (REG_RD(bp, NIG_REG_PORT_SWAP)) 2568 emac_base = GRCBASE_EMAC0; 2569 else 2570 emac_base = GRCBASE_EMAC1; 2571 break; 2572 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH: 2573 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0; 2574 break; 2575 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED: 2576 emac_base = (port) ? GRCBASE_EMAC0 : GRCBASE_EMAC1; 2577 break; 2578 default: 2579 break; 2580 } 2581 return emac_base; 2582 2583 } 2584 2585 /******************************************************************/ 2586 /* CL22 access functions */ 2587 /******************************************************************/ 2588 static int bnx2x_cl22_write(struct bnx2x *bp, 2589 struct bnx2x_phy *phy, 2590 u16 reg, u16 val) 2591 { 2592 u32 tmp, mode; 2593 u8 i; 2594 int rc = 0; 2595 /* Switch to CL22 */ 2596 mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE); 2597 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, 2598 mode & ~EMAC_MDIO_MODE_CLAUSE_45); 2599 2600 /* Address */ 2601 tmp = ((phy->addr << 21) | (reg << 16) | val | 2602 EMAC_MDIO_COMM_COMMAND_WRITE_22 | 2603 EMAC_MDIO_COMM_START_BUSY); 2604 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); 2605 2606 for (i = 0; i < 50; i++) { 2607 udelay(10); 2608 2609 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); 2610 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) { 2611 udelay(5); 2612 break; 2613 } 2614 } 2615 if (tmp & EMAC_MDIO_COMM_START_BUSY) { 2616 DP(NETIF_MSG_LINK, "write phy register failed\n"); 2617 rc = -EFAULT; 2618 } 2619 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode); 2620 return rc; 2621 } 2622 2623 static int bnx2x_cl22_read(struct bnx2x *bp, 2624 struct bnx2x_phy *phy, 2625 u16 reg, u16 *ret_val) 2626 { 2627 u32 val, mode; 2628 u16 i; 2629 int rc = 0; 2630 2631 /* Switch to CL22 */ 2632 mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE); 2633 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, 2634 mode & ~EMAC_MDIO_MODE_CLAUSE_45); 2635 2636 /* Address */ 2637 val = ((phy->addr << 21) | (reg << 16) | 2638 EMAC_MDIO_COMM_COMMAND_READ_22 | 2639 EMAC_MDIO_COMM_START_BUSY); 2640 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); 2641 2642 for (i = 0; i < 50; i++) { 2643 udelay(10); 2644 2645 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); 2646 if (!(val & EMAC_MDIO_COMM_START_BUSY)) { 2647 *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA); 2648 udelay(5); 2649 break; 2650 } 2651 } 2652 if (val & EMAC_MDIO_COMM_START_BUSY) { 2653 DP(NETIF_MSG_LINK, "read phy register failed\n"); 2654 2655 *ret_val = 0; 2656 rc = -EFAULT; 2657 } 2658 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode); 2659 return rc; 2660 } 2661 2662 /******************************************************************/ 2663 /* CL45 access functions */ 2664 /******************************************************************/ 2665 static int bnx2x_cl45_read(struct bnx2x *bp, struct bnx2x_phy *phy, 2666 u8 devad, u16 reg, u16 *ret_val) 2667 { 2668 u32 val; 2669 u16 i; 2670 int rc = 0; 2671 u32 chip_id; 2672 if (phy->flags & FLAGS_MDC_MDIO_WA_G) { 2673 chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) | 2674 ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12); 2675 bnx2x_set_mdio_clk(bp, chip_id, phy->mdio_ctrl); 2676 } 2677 2678 if (phy->flags & FLAGS_MDC_MDIO_WA_B0) 2679 bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, 2680 EMAC_MDIO_STATUS_10MB); 2681 /* Address */ 2682 val = ((phy->addr << 21) | (devad << 16) | reg | 2683 EMAC_MDIO_COMM_COMMAND_ADDRESS | 2684 EMAC_MDIO_COMM_START_BUSY); 2685 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); 2686 2687 for (i = 0; i < 50; i++) { 2688 udelay(10); 2689 2690 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); 2691 if (!(val & EMAC_MDIO_COMM_START_BUSY)) { 2692 udelay(5); 2693 break; 2694 } 2695 } 2696 if (val & EMAC_MDIO_COMM_START_BUSY) { 2697 DP(NETIF_MSG_LINK, "read phy register failed\n"); 2698 netdev_err(bp->dev, "MDC/MDIO access timeout\n"); 2699 *ret_val = 0; 2700 rc = -EFAULT; 2701 } else { 2702 /* Data */ 2703 val = ((phy->addr << 21) | (devad << 16) | 2704 EMAC_MDIO_COMM_COMMAND_READ_45 | 2705 EMAC_MDIO_COMM_START_BUSY); 2706 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); 2707 2708 for (i = 0; i < 50; i++) { 2709 udelay(10); 2710 2711 val = REG_RD(bp, phy->mdio_ctrl + 2712 EMAC_REG_EMAC_MDIO_COMM); 2713 if (!(val & EMAC_MDIO_COMM_START_BUSY)) { 2714 *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA); 2715 break; 2716 } 2717 } 2718 if (val & EMAC_MDIO_COMM_START_BUSY) { 2719 DP(NETIF_MSG_LINK, "read phy register failed\n"); 2720 netdev_err(bp->dev, "MDC/MDIO access timeout\n"); 2721 *ret_val = 0; 2722 rc = -EFAULT; 2723 } 2724 } 2725 /* Work around for E3 A0 */ 2726 if (phy->flags & FLAGS_MDC_MDIO_WA) { 2727 phy->flags ^= FLAGS_DUMMY_READ; 2728 if (phy->flags & FLAGS_DUMMY_READ) { 2729 u16 temp_val; 2730 bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val); 2731 } 2732 } 2733 2734 if (phy->flags & FLAGS_MDC_MDIO_WA_B0) 2735 bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, 2736 EMAC_MDIO_STATUS_10MB); 2737 return rc; 2738 } 2739 2740 static int bnx2x_cl45_write(struct bnx2x *bp, struct bnx2x_phy *phy, 2741 u8 devad, u16 reg, u16 val) 2742 { 2743 u32 tmp; 2744 u8 i; 2745 int rc = 0; 2746 u32 chip_id; 2747 if (phy->flags & FLAGS_MDC_MDIO_WA_G) { 2748 chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) | 2749 ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12); 2750 bnx2x_set_mdio_clk(bp, chip_id, phy->mdio_ctrl); 2751 } 2752 2753 if (phy->flags & FLAGS_MDC_MDIO_WA_B0) 2754 bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, 2755 EMAC_MDIO_STATUS_10MB); 2756 2757 /* Address */ 2758 tmp = ((phy->addr << 21) | (devad << 16) | reg | 2759 EMAC_MDIO_COMM_COMMAND_ADDRESS | 2760 EMAC_MDIO_COMM_START_BUSY); 2761 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); 2762 2763 for (i = 0; i < 50; i++) { 2764 udelay(10); 2765 2766 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); 2767 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) { 2768 udelay(5); 2769 break; 2770 } 2771 } 2772 if (tmp & EMAC_MDIO_COMM_START_BUSY) { 2773 DP(NETIF_MSG_LINK, "write phy register failed\n"); 2774 netdev_err(bp->dev, "MDC/MDIO access timeout\n"); 2775 rc = -EFAULT; 2776 } else { 2777 /* Data */ 2778 tmp = ((phy->addr << 21) | (devad << 16) | val | 2779 EMAC_MDIO_COMM_COMMAND_WRITE_45 | 2780 EMAC_MDIO_COMM_START_BUSY); 2781 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); 2782 2783 for (i = 0; i < 50; i++) { 2784 udelay(10); 2785 2786 tmp = REG_RD(bp, phy->mdio_ctrl + 2787 EMAC_REG_EMAC_MDIO_COMM); 2788 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) { 2789 udelay(5); 2790 break; 2791 } 2792 } 2793 if (tmp & EMAC_MDIO_COMM_START_BUSY) { 2794 DP(NETIF_MSG_LINK, "write phy register failed\n"); 2795 netdev_err(bp->dev, "MDC/MDIO access timeout\n"); 2796 rc = -EFAULT; 2797 } 2798 } 2799 /* Work around for E3 A0 */ 2800 if (phy->flags & FLAGS_MDC_MDIO_WA) { 2801 phy->flags ^= FLAGS_DUMMY_READ; 2802 if (phy->flags & FLAGS_DUMMY_READ) { 2803 u16 temp_val; 2804 bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val); 2805 } 2806 } 2807 if (phy->flags & FLAGS_MDC_MDIO_WA_B0) 2808 bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, 2809 EMAC_MDIO_STATUS_10MB); 2810 return rc; 2811 } 2812 2813 /******************************************************************/ 2814 /* EEE section */ 2815 /******************************************************************/ 2816 static u8 bnx2x_eee_has_cap(struct link_params *params) 2817 { 2818 struct bnx2x *bp = params->bp; 2819 2820 if (REG_RD(bp, params->shmem2_base) <= 2821 offsetof(struct shmem2_region, eee_status[params->port])) 2822 return 0; 2823 2824 return 1; 2825 } 2826 2827 static int bnx2x_eee_nvram_to_time(u32 nvram_mode, u32 *idle_timer) 2828 { 2829 switch (nvram_mode) { 2830 case PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED: 2831 *idle_timer = EEE_MODE_NVRAM_BALANCED_TIME; 2832 break; 2833 case PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE: 2834 *idle_timer = EEE_MODE_NVRAM_AGGRESSIVE_TIME; 2835 break; 2836 case PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY: 2837 *idle_timer = EEE_MODE_NVRAM_LATENCY_TIME; 2838 break; 2839 default: 2840 *idle_timer = 0; 2841 break; 2842 } 2843 2844 return 0; 2845 } 2846 2847 static int bnx2x_eee_time_to_nvram(u32 idle_timer, u32 *nvram_mode) 2848 { 2849 switch (idle_timer) { 2850 case EEE_MODE_NVRAM_BALANCED_TIME: 2851 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED; 2852 break; 2853 case EEE_MODE_NVRAM_AGGRESSIVE_TIME: 2854 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE; 2855 break; 2856 case EEE_MODE_NVRAM_LATENCY_TIME: 2857 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY; 2858 break; 2859 default: 2860 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED; 2861 break; 2862 } 2863 2864 return 0; 2865 } 2866 2867 static u32 bnx2x_eee_calc_timer(struct link_params *params) 2868 { 2869 u32 eee_mode, eee_idle; 2870 struct bnx2x *bp = params->bp; 2871 2872 if (params->eee_mode & EEE_MODE_OVERRIDE_NVRAM) { 2873 if (params->eee_mode & EEE_MODE_OUTPUT_TIME) { 2874 /* time value in eee_mode --> used directly*/ 2875 eee_idle = params->eee_mode & EEE_MODE_TIMER_MASK; 2876 } else { 2877 /* hsi value in eee_mode --> time */ 2878 if (bnx2x_eee_nvram_to_time(params->eee_mode & 2879 EEE_MODE_NVRAM_MASK, 2880 &eee_idle)) 2881 return 0; 2882 } 2883 } else { 2884 /* hsi values in nvram --> time*/ 2885 eee_mode = ((REG_RD(bp, params->shmem_base + 2886 offsetof(struct shmem_region, dev_info. 2887 port_feature_config[params->port]. 2888 eee_power_mode)) & 2889 PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >> 2890 PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT); 2891 2892 if (bnx2x_eee_nvram_to_time(eee_mode, &eee_idle)) 2893 return 0; 2894 } 2895 2896 return eee_idle; 2897 } 2898 2899 static int bnx2x_eee_set_timers(struct link_params *params, 2900 struct link_vars *vars) 2901 { 2902 u32 eee_idle = 0, eee_mode; 2903 struct bnx2x *bp = params->bp; 2904 2905 eee_idle = bnx2x_eee_calc_timer(params); 2906 2907 if (eee_idle) { 2908 REG_WR(bp, MISC_REG_CPMU_LP_IDLE_THR_P0 + (params->port << 2), 2909 eee_idle); 2910 } else if ((params->eee_mode & EEE_MODE_ENABLE_LPI) && 2911 (params->eee_mode & EEE_MODE_OVERRIDE_NVRAM) && 2912 (params->eee_mode & EEE_MODE_OUTPUT_TIME)) { 2913 DP(NETIF_MSG_LINK, "Error: Tx LPI is enabled with timer 0\n"); 2914 return -EINVAL; 2915 } 2916 2917 vars->eee_status &= ~(SHMEM_EEE_TIMER_MASK | SHMEM_EEE_TIME_OUTPUT_BIT); 2918 if (params->eee_mode & EEE_MODE_OUTPUT_TIME) { 2919 /* eee_idle in 1u --> eee_status in 16u */ 2920 eee_idle >>= 4; 2921 vars->eee_status |= (eee_idle & SHMEM_EEE_TIMER_MASK) | 2922 SHMEM_EEE_TIME_OUTPUT_BIT; 2923 } else { 2924 if (bnx2x_eee_time_to_nvram(eee_idle, &eee_mode)) 2925 return -EINVAL; 2926 vars->eee_status |= eee_mode; 2927 } 2928 2929 return 0; 2930 } 2931 2932 static int bnx2x_eee_initial_config(struct link_params *params, 2933 struct link_vars *vars, u8 mode) 2934 { 2935 vars->eee_status |= ((u32) mode) << SHMEM_EEE_SUPPORTED_SHIFT; 2936 2937 /* Propagate params' bits --> vars (for migration exposure) */ 2938 if (params->eee_mode & EEE_MODE_ENABLE_LPI) 2939 vars->eee_status |= SHMEM_EEE_LPI_REQUESTED_BIT; 2940 else 2941 vars->eee_status &= ~SHMEM_EEE_LPI_REQUESTED_BIT; 2942 2943 if (params->eee_mode & EEE_MODE_ADV_LPI) 2944 vars->eee_status |= SHMEM_EEE_REQUESTED_BIT; 2945 else 2946 vars->eee_status &= ~SHMEM_EEE_REQUESTED_BIT; 2947 2948 return bnx2x_eee_set_timers(params, vars); 2949 } 2950 2951 static int bnx2x_eee_disable(struct bnx2x_phy *phy, 2952 struct link_params *params, 2953 struct link_vars *vars) 2954 { 2955 struct bnx2x *bp = params->bp; 2956 2957 /* Make Certain LPI is disabled */ 2958 REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2), 0); 2959 2960 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, 0x0); 2961 2962 vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK; 2963 2964 return 0; 2965 } 2966 2967 static int bnx2x_eee_advertise(struct bnx2x_phy *phy, 2968 struct link_params *params, 2969 struct link_vars *vars, u8 modes) 2970 { 2971 struct bnx2x *bp = params->bp; 2972 u16 val = 0; 2973 2974 /* Mask events preventing LPI generation */ 2975 REG_WR(bp, MISC_REG_CPMU_LP_MASK_EXT_P0 + (params->port << 2), 0xfc20); 2976 2977 if (modes & SHMEM_EEE_10G_ADV) { 2978 DP(NETIF_MSG_LINK, "Advertise 10GBase-T EEE\n"); 2979 val |= 0x8; 2980 } 2981 if (modes & SHMEM_EEE_1G_ADV) { 2982 DP(NETIF_MSG_LINK, "Advertise 1GBase-T EEE\n"); 2983 val |= 0x4; 2984 } 2985 2986 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, val); 2987 2988 vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK; 2989 vars->eee_status |= (modes << SHMEM_EEE_ADV_STATUS_SHIFT); 2990 2991 return 0; 2992 } 2993 2994 static void bnx2x_update_mng_eee(struct link_params *params, u32 eee_status) 2995 { 2996 struct bnx2x *bp = params->bp; 2997 2998 if (bnx2x_eee_has_cap(params)) 2999 REG_WR(bp, params->shmem2_base + 3000 offsetof(struct shmem2_region, 3001 eee_status[params->port]), eee_status); 3002 } 3003 3004 static void bnx2x_eee_an_resolve(struct bnx2x_phy *phy, 3005 struct link_params *params, 3006 struct link_vars *vars) 3007 { 3008 struct bnx2x *bp = params->bp; 3009 u16 adv = 0, lp = 0; 3010 u32 lp_adv = 0; 3011 u8 neg = 0; 3012 3013 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, &adv); 3014 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_LP_EEE_ADV, &lp); 3015 3016 if (lp & 0x2) { 3017 lp_adv |= SHMEM_EEE_100M_ADV; 3018 if (adv & 0x2) { 3019 if (vars->line_speed == SPEED_100) 3020 neg = 1; 3021 DP(NETIF_MSG_LINK, "EEE negotiated - 100M\n"); 3022 } 3023 } 3024 if (lp & 0x14) { 3025 lp_adv |= SHMEM_EEE_1G_ADV; 3026 if (adv & 0x14) { 3027 if (vars->line_speed == SPEED_1000) 3028 neg = 1; 3029 DP(NETIF_MSG_LINK, "EEE negotiated - 1G\n"); 3030 } 3031 } 3032 if (lp & 0x68) { 3033 lp_adv |= SHMEM_EEE_10G_ADV; 3034 if (adv & 0x68) { 3035 if (vars->line_speed == SPEED_10000) 3036 neg = 1; 3037 DP(NETIF_MSG_LINK, "EEE negotiated - 10G\n"); 3038 } 3039 } 3040 3041 vars->eee_status &= ~SHMEM_EEE_LP_ADV_STATUS_MASK; 3042 vars->eee_status |= (lp_adv << SHMEM_EEE_LP_ADV_STATUS_SHIFT); 3043 3044 if (neg) { 3045 DP(NETIF_MSG_LINK, "EEE is active\n"); 3046 vars->eee_status |= SHMEM_EEE_ACTIVE_BIT; 3047 } 3048 3049 } 3050 3051 /******************************************************************/ 3052 /* BSC access functions from E3 */ 3053 /******************************************************************/ 3054 static void bnx2x_bsc_module_sel(struct link_params *params) 3055 { 3056 int idx; 3057 u32 board_cfg, sfp_ctrl; 3058 u32 i2c_pins[I2C_SWITCH_WIDTH], i2c_val[I2C_SWITCH_WIDTH]; 3059 struct bnx2x *bp = params->bp; 3060 u8 port = params->port; 3061 /* Read I2C output PINs */ 3062 board_cfg = REG_RD(bp, params->shmem_base + 3063 offsetof(struct shmem_region, 3064 dev_info.shared_hw_config.board)); 3065 i2c_pins[I2C_BSC0] = board_cfg & SHARED_HW_CFG_E3_I2C_MUX0_MASK; 3066 i2c_pins[I2C_BSC1] = (board_cfg & SHARED_HW_CFG_E3_I2C_MUX1_MASK) >> 3067 SHARED_HW_CFG_E3_I2C_MUX1_SHIFT; 3068 3069 /* Read I2C output value */ 3070 sfp_ctrl = REG_RD(bp, params->shmem_base + 3071 offsetof(struct shmem_region, 3072 dev_info.port_hw_config[port].e3_cmn_pin_cfg)); 3073 i2c_val[I2C_BSC0] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX0_MASK) > 0; 3074 i2c_val[I2C_BSC1] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX1_MASK) > 0; 3075 DP(NETIF_MSG_LINK, "Setting BSC switch\n"); 3076 for (idx = 0; idx < I2C_SWITCH_WIDTH; idx++) 3077 bnx2x_set_cfg_pin(bp, i2c_pins[idx], i2c_val[idx]); 3078 } 3079 3080 static int bnx2x_bsc_read(struct link_params *params, 3081 struct bnx2x *bp, 3082 u8 sl_devid, 3083 u16 sl_addr, 3084 u8 lc_addr, 3085 u8 xfer_cnt, 3086 u32 *data_array) 3087 { 3088 u64 t0, delta; 3089 u32 val, i; 3090 int rc = 0; 3091 3092 if (xfer_cnt > 16) { 3093 DP(NETIF_MSG_LINK, "invalid xfer_cnt %d. Max is 16 bytes\n", 3094 xfer_cnt); 3095 return -EINVAL; 3096 } 3097 bnx2x_bsc_module_sel(params); 3098 3099 xfer_cnt = 16 - lc_addr; 3100 3101 /* Enable the engine */ 3102 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND); 3103 val |= MCPR_IMC_COMMAND_ENABLE; 3104 REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val); 3105 3106 /* Program slave device ID */ 3107 val = (sl_devid << 16) | sl_addr; 3108 REG_WR(bp, MCP_REG_MCPR_IMC_SLAVE_CONTROL, val); 3109 3110 /* Start xfer with 0 byte to update the address pointer ???*/ 3111 val = (MCPR_IMC_COMMAND_ENABLE) | 3112 (MCPR_IMC_COMMAND_WRITE_OP << 3113 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) | 3114 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) | (0); 3115 REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val); 3116 3117 /* Poll for completion */ 3118 t0 = ktime_get_ns(); 3119 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND); 3120 while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) { 3121 delta = ktime_get_ns() - t0; 3122 if (delta > 10 * NSEC_PER_MSEC) { 3123 DP(NETIF_MSG_LINK, "wr 0 byte timed out after %Lu ns\n", 3124 delta); 3125 rc = -EFAULT; 3126 break; 3127 } 3128 usleep_range(10, 20); 3129 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND); 3130 } 3131 if (rc == -EFAULT) 3132 return rc; 3133 3134 /* Start xfer with read op */ 3135 val = (MCPR_IMC_COMMAND_ENABLE) | 3136 (MCPR_IMC_COMMAND_READ_OP << 3137 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) | 3138 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) | 3139 (xfer_cnt); 3140 REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val); 3141 3142 /* Poll for completion */ 3143 t0 = ktime_get_ns(); 3144 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND); 3145 while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) { 3146 delta = ktime_get_ns() - t0; 3147 if (delta > 10 * NSEC_PER_MSEC) { 3148 DP(NETIF_MSG_LINK, "rd op timed out after %Lu ns\n", 3149 delta); 3150 rc = -EFAULT; 3151 break; 3152 } 3153 usleep_range(10, 20); 3154 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND); 3155 } 3156 if (rc == -EFAULT) 3157 return rc; 3158 3159 for (i = (lc_addr >> 2); i < 4; i++) { 3160 data_array[i] = REG_RD(bp, (MCP_REG_MCPR_IMC_DATAREG0 + i*4)); 3161 #ifdef __BIG_ENDIAN 3162 data_array[i] = ((data_array[i] & 0x000000ff) << 24) | 3163 ((data_array[i] & 0x0000ff00) << 8) | 3164 ((data_array[i] & 0x00ff0000) >> 8) | 3165 ((data_array[i] & 0xff000000) >> 24); 3166 #endif 3167 } 3168 return rc; 3169 } 3170 3171 static void bnx2x_cl45_read_or_write(struct bnx2x *bp, struct bnx2x_phy *phy, 3172 u8 devad, u16 reg, u16 or_val) 3173 { 3174 u16 val; 3175 bnx2x_cl45_read(bp, phy, devad, reg, &val); 3176 bnx2x_cl45_write(bp, phy, devad, reg, val | or_val); 3177 } 3178 3179 static void bnx2x_cl45_read_and_write(struct bnx2x *bp, 3180 struct bnx2x_phy *phy, 3181 u8 devad, u16 reg, u16 and_val) 3182 { 3183 u16 val; 3184 bnx2x_cl45_read(bp, phy, devad, reg, &val); 3185 bnx2x_cl45_write(bp, phy, devad, reg, val & and_val); 3186 } 3187 3188 int bnx2x_phy_read(struct link_params *params, u8 phy_addr, 3189 u8 devad, u16 reg, u16 *ret_val) 3190 { 3191 u8 phy_index; 3192 /* Probe for the phy according to the given phy_addr, and execute 3193 * the read request on it 3194 */ 3195 for (phy_index = 0; phy_index < params->num_phys; phy_index++) { 3196 if (params->phy[phy_index].addr == phy_addr) { 3197 return bnx2x_cl45_read(params->bp, 3198 ¶ms->phy[phy_index], devad, 3199 reg, ret_val); 3200 } 3201 } 3202 return -EINVAL; 3203 } 3204 3205 int bnx2x_phy_write(struct link_params *params, u8 phy_addr, 3206 u8 devad, u16 reg, u16 val) 3207 { 3208 u8 phy_index; 3209 /* Probe for the phy according to the given phy_addr, and execute 3210 * the write request on it 3211 */ 3212 for (phy_index = 0; phy_index < params->num_phys; phy_index++) { 3213 if (params->phy[phy_index].addr == phy_addr) { 3214 return bnx2x_cl45_write(params->bp, 3215 ¶ms->phy[phy_index], devad, 3216 reg, val); 3217 } 3218 } 3219 return -EINVAL; 3220 } 3221 static u8 bnx2x_get_warpcore_lane(struct bnx2x_phy *phy, 3222 struct link_params *params) 3223 { 3224 u8 lane = 0; 3225 struct bnx2x *bp = params->bp; 3226 u32 path_swap, path_swap_ovr; 3227 u8 path, port; 3228 3229 path = BP_PATH(bp); 3230 port = params->port; 3231 3232 if (bnx2x_is_4_port_mode(bp)) { 3233 u32 port_swap, port_swap_ovr; 3234 3235 /* Figure out path swap value */ 3236 path_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP_OVWR); 3237 if (path_swap_ovr & 0x1) 3238 path_swap = (path_swap_ovr & 0x2); 3239 else 3240 path_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP); 3241 3242 if (path_swap) 3243 path = path ^ 1; 3244 3245 /* Figure out port swap value */ 3246 port_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP_OVWR); 3247 if (port_swap_ovr & 0x1) 3248 port_swap = (port_swap_ovr & 0x2); 3249 else 3250 port_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP); 3251 3252 if (port_swap) 3253 port = port ^ 1; 3254 3255 lane = (port<<1) + path; 3256 } else { /* Two port mode - no port swap */ 3257 3258 /* Figure out path swap value */ 3259 path_swap_ovr = 3260 REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP_OVWR); 3261 if (path_swap_ovr & 0x1) { 3262 path_swap = (path_swap_ovr & 0x2); 3263 } else { 3264 path_swap = 3265 REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP); 3266 } 3267 if (path_swap) 3268 path = path ^ 1; 3269 3270 lane = path << 1 ; 3271 } 3272 return lane; 3273 } 3274 3275 static void bnx2x_set_aer_mmd(struct link_params *params, 3276 struct bnx2x_phy *phy) 3277 { 3278 u32 ser_lane; 3279 u16 offset, aer_val; 3280 struct bnx2x *bp = params->bp; 3281 ser_lane = ((params->lane_config & 3282 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >> 3283 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT); 3284 3285 offset = (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ? 3286 (phy->addr + ser_lane) : 0; 3287 3288 if (USES_WARPCORE(bp)) { 3289 aer_val = bnx2x_get_warpcore_lane(phy, params); 3290 /* In Dual-lane mode, two lanes are joined together, 3291 * so in order to configure them, the AER broadcast method is 3292 * used here. 3293 * 0x200 is the broadcast address for lanes 0,1 3294 * 0x201 is the broadcast address for lanes 2,3 3295 */ 3296 if (phy->flags & FLAGS_WC_DUAL_MODE) 3297 aer_val = (aer_val >> 1) | 0x200; 3298 } else if (CHIP_IS_E2(bp)) 3299 aer_val = 0x3800 + offset - 1; 3300 else 3301 aer_val = 0x3800 + offset; 3302 3303 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, 3304 MDIO_AER_BLOCK_AER_REG, aer_val); 3305 3306 } 3307 3308 /******************************************************************/ 3309 /* Internal phy section */ 3310 /******************************************************************/ 3311 3312 static void bnx2x_set_serdes_access(struct bnx2x *bp, u8 port) 3313 { 3314 u32 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0; 3315 3316 /* Set Clause 22 */ 3317 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 1); 3318 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000); 3319 udelay(500); 3320 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f); 3321 udelay(500); 3322 /* Set Clause 45 */ 3323 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 0); 3324 } 3325 3326 static void bnx2x_serdes_deassert(struct bnx2x *bp, u8 port) 3327 { 3328 u32 val; 3329 3330 DP(NETIF_MSG_LINK, "bnx2x_serdes_deassert\n"); 3331 3332 val = SERDES_RESET_BITS << (port*16); 3333 3334 /* Reset and unreset the SerDes/XGXS */ 3335 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val); 3336 udelay(500); 3337 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val); 3338 3339 bnx2x_set_serdes_access(bp, port); 3340 3341 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_DEVAD + port*0x10, 3342 DEFAULT_PHY_DEV_ADDR); 3343 } 3344 3345 static void bnx2x_xgxs_specific_func(struct bnx2x_phy *phy, 3346 struct link_params *params, 3347 u32 action) 3348 { 3349 struct bnx2x *bp = params->bp; 3350 switch (action) { 3351 case PHY_INIT: 3352 /* Set correct devad */ 3353 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_ST + params->port*0x18, 0); 3354 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + params->port*0x18, 3355 phy->def_md_devad); 3356 break; 3357 } 3358 } 3359 3360 static void bnx2x_xgxs_deassert(struct link_params *params) 3361 { 3362 struct bnx2x *bp = params->bp; 3363 u8 port; 3364 u32 val; 3365 DP(NETIF_MSG_LINK, "bnx2x_xgxs_deassert\n"); 3366 port = params->port; 3367 3368 val = XGXS_RESET_BITS << (port*16); 3369 3370 /* Reset and unreset the SerDes/XGXS */ 3371 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val); 3372 udelay(500); 3373 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val); 3374 bnx2x_xgxs_specific_func(¶ms->phy[INT_PHY], params, 3375 PHY_INIT); 3376 } 3377 3378 static void bnx2x_calc_ieee_aneg_adv(struct bnx2x_phy *phy, 3379 struct link_params *params, u16 *ieee_fc) 3380 { 3381 struct bnx2x *bp = params->bp; 3382 *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX; 3383 /* Resolve pause mode and advertisement Please refer to Table 3384 * 28B-3 of the 802.3ab-1999 spec 3385 */ 3386 3387 switch (phy->req_flow_ctrl) { 3388 case BNX2X_FLOW_CTRL_AUTO: 3389 switch (params->req_fc_auto_adv) { 3390 case BNX2X_FLOW_CTRL_BOTH: 3391 case BNX2X_FLOW_CTRL_RX: 3392 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; 3393 break; 3394 case BNX2X_FLOW_CTRL_TX: 3395 *ieee_fc |= 3396 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC; 3397 break; 3398 default: 3399 break; 3400 } 3401 break; 3402 case BNX2X_FLOW_CTRL_TX: 3403 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC; 3404 break; 3405 3406 case BNX2X_FLOW_CTRL_RX: 3407 case BNX2X_FLOW_CTRL_BOTH: 3408 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; 3409 break; 3410 3411 case BNX2X_FLOW_CTRL_NONE: 3412 default: 3413 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE; 3414 break; 3415 } 3416 DP(NETIF_MSG_LINK, "ieee_fc = 0x%x\n", *ieee_fc); 3417 } 3418 3419 static void set_phy_vars(struct link_params *params, 3420 struct link_vars *vars) 3421 { 3422 struct bnx2x *bp = params->bp; 3423 u8 actual_phy_idx, phy_index, link_cfg_idx; 3424 u8 phy_config_swapped = params->multi_phy_config & 3425 PORT_HW_CFG_PHY_SWAPPED_ENABLED; 3426 for (phy_index = INT_PHY; phy_index < params->num_phys; 3427 phy_index++) { 3428 link_cfg_idx = LINK_CONFIG_IDX(phy_index); 3429 actual_phy_idx = phy_index; 3430 if (phy_config_swapped) { 3431 if (phy_index == EXT_PHY1) 3432 actual_phy_idx = EXT_PHY2; 3433 else if (phy_index == EXT_PHY2) 3434 actual_phy_idx = EXT_PHY1; 3435 } 3436 params->phy[actual_phy_idx].req_flow_ctrl = 3437 params->req_flow_ctrl[link_cfg_idx]; 3438 3439 params->phy[actual_phy_idx].req_line_speed = 3440 params->req_line_speed[link_cfg_idx]; 3441 3442 params->phy[actual_phy_idx].speed_cap_mask = 3443 params->speed_cap_mask[link_cfg_idx]; 3444 3445 params->phy[actual_phy_idx].req_duplex = 3446 params->req_duplex[link_cfg_idx]; 3447 3448 if (params->req_line_speed[link_cfg_idx] == 3449 SPEED_AUTO_NEG) 3450 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED; 3451 3452 DP(NETIF_MSG_LINK, "req_flow_ctrl %x, req_line_speed %x," 3453 " speed_cap_mask %x\n", 3454 params->phy[actual_phy_idx].req_flow_ctrl, 3455 params->phy[actual_phy_idx].req_line_speed, 3456 params->phy[actual_phy_idx].speed_cap_mask); 3457 } 3458 } 3459 3460 static void bnx2x_ext_phy_set_pause(struct link_params *params, 3461 struct bnx2x_phy *phy, 3462 struct link_vars *vars) 3463 { 3464 u16 val; 3465 struct bnx2x *bp = params->bp; 3466 /* Read modify write pause advertizing */ 3467 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &val); 3468 3469 val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH; 3470 3471 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */ 3472 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); 3473 if ((vars->ieee_fc & 3474 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) == 3475 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) { 3476 val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC; 3477 } 3478 if ((vars->ieee_fc & 3479 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) == 3480 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) { 3481 val |= MDIO_AN_REG_ADV_PAUSE_PAUSE; 3482 } 3483 DP(NETIF_MSG_LINK, "Ext phy AN advertize 0x%x\n", val); 3484 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val); 3485 } 3486 3487 static void bnx2x_pause_resolve(struct bnx2x_phy *phy, 3488 struct link_params *params, 3489 struct link_vars *vars, 3490 u32 pause_result) 3491 { 3492 struct bnx2x *bp = params->bp; 3493 /* LD LP */ 3494 switch (pause_result) { /* ASYM P ASYM P */ 3495 case 0xb: /* 1 0 1 1 */ 3496 DP(NETIF_MSG_LINK, "Flow Control: TX only\n"); 3497 vars->flow_ctrl = BNX2X_FLOW_CTRL_TX; 3498 break; 3499 3500 case 0xe: /* 1 1 1 0 */ 3501 DP(NETIF_MSG_LINK, "Flow Control: RX only\n"); 3502 vars->flow_ctrl = BNX2X_FLOW_CTRL_RX; 3503 break; 3504 3505 case 0x5: /* 0 1 0 1 */ 3506 case 0x7: /* 0 1 1 1 */ 3507 case 0xd: /* 1 1 0 1 */ 3508 case 0xf: /* 1 1 1 1 */ 3509 /* If the user selected to advertise RX ONLY, 3510 * although we advertised both, need to enable 3511 * RX only. 3512 */ 3513 if (params->req_fc_auto_adv == BNX2X_FLOW_CTRL_BOTH) { 3514 DP(NETIF_MSG_LINK, "Flow Control: RX & TX\n"); 3515 vars->flow_ctrl = BNX2X_FLOW_CTRL_BOTH; 3516 } else { 3517 DP(NETIF_MSG_LINK, "Flow Control: RX only\n"); 3518 vars->flow_ctrl = BNX2X_FLOW_CTRL_RX; 3519 } 3520 break; 3521 3522 default: 3523 DP(NETIF_MSG_LINK, "Flow Control: None\n"); 3524 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; 3525 break; 3526 } 3527 if (pause_result & (1<<0)) 3528 vars->link_status |= LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE; 3529 if (pause_result & (1<<1)) 3530 vars->link_status |= LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE; 3531 3532 } 3533 3534 static void bnx2x_ext_phy_update_adv_fc(struct bnx2x_phy *phy, 3535 struct link_params *params, 3536 struct link_vars *vars) 3537 { 3538 u16 ld_pause; /* local */ 3539 u16 lp_pause; /* link partner */ 3540 u16 pause_result; 3541 struct bnx2x *bp = params->bp; 3542 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) { 3543 bnx2x_cl22_read(bp, phy, 0x4, &ld_pause); 3544 bnx2x_cl22_read(bp, phy, 0x5, &lp_pause); 3545 } else if (CHIP_IS_E3(bp) && 3546 SINGLE_MEDIA_DIRECT(params)) { 3547 u8 lane = bnx2x_get_warpcore_lane(phy, params); 3548 u16 gp_status, gp_mask; 3549 bnx2x_cl45_read(bp, phy, 3550 MDIO_AN_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_4, 3551 &gp_status); 3552 gp_mask = (MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL | 3553 MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP) << 3554 lane; 3555 if ((gp_status & gp_mask) == gp_mask) { 3556 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, 3557 MDIO_AN_REG_ADV_PAUSE, &ld_pause); 3558 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, 3559 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause); 3560 } else { 3561 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, 3562 MDIO_AN_REG_CL37_FC_LD, &ld_pause); 3563 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, 3564 MDIO_AN_REG_CL37_FC_LP, &lp_pause); 3565 ld_pause = ((ld_pause & 3566 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) 3567 << 3); 3568 lp_pause = ((lp_pause & 3569 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) 3570 << 3); 3571 } 3572 } else { 3573 bnx2x_cl45_read(bp, phy, 3574 MDIO_AN_DEVAD, 3575 MDIO_AN_REG_ADV_PAUSE, &ld_pause); 3576 bnx2x_cl45_read(bp, phy, 3577 MDIO_AN_DEVAD, 3578 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause); 3579 } 3580 pause_result = (ld_pause & 3581 MDIO_AN_REG_ADV_PAUSE_MASK) >> 8; 3582 pause_result |= (lp_pause & 3583 MDIO_AN_REG_ADV_PAUSE_MASK) >> 10; 3584 DP(NETIF_MSG_LINK, "Ext PHY pause result 0x%x\n", pause_result); 3585 bnx2x_pause_resolve(phy, params, vars, pause_result); 3586 3587 } 3588 3589 static u8 bnx2x_ext_phy_resolve_fc(struct bnx2x_phy *phy, 3590 struct link_params *params, 3591 struct link_vars *vars) 3592 { 3593 u8 ret = 0; 3594 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; 3595 if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO) { 3596 /* Update the advertised flow-controled of LD/LP in AN */ 3597 if (phy->req_line_speed == SPEED_AUTO_NEG) 3598 bnx2x_ext_phy_update_adv_fc(phy, params, vars); 3599 /* But set the flow-control result as the requested one */ 3600 vars->flow_ctrl = phy->req_flow_ctrl; 3601 } else if (phy->req_line_speed != SPEED_AUTO_NEG) 3602 vars->flow_ctrl = params->req_fc_auto_adv; 3603 else if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) { 3604 ret = 1; 3605 bnx2x_ext_phy_update_adv_fc(phy, params, vars); 3606 } 3607 return ret; 3608 } 3609 /******************************************************************/ 3610 /* Warpcore section */ 3611 /******************************************************************/ 3612 /* The init_internal_warpcore should mirror the xgxs, 3613 * i.e. reset the lane (if needed), set aer for the 3614 * init configuration, and set/clear SGMII flag. Internal 3615 * phy init is done purely in phy_init stage. 3616 */ 3617 #define WC_TX_DRIVER(post2, idriver, ipre, ifir) \ 3618 ((post2 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) | \ 3619 (idriver << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) | \ 3620 (ipre << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET) | \ 3621 (ifir << MDIO_WC_REG_TX0_TX_DRIVER_IFIR_OFFSET)) 3622 3623 #define WC_TX_FIR(post, main, pre) \ 3624 ((post << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) | \ 3625 (main << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) | \ 3626 (pre << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET)) 3627 3628 static void bnx2x_warpcore_enable_AN_KR2(struct bnx2x_phy *phy, 3629 struct link_params *params, 3630 struct link_vars *vars) 3631 { 3632 struct bnx2x *bp = params->bp; 3633 u16 i; 3634 static struct bnx2x_reg_set reg_set[] = { 3635 /* Step 1 - Program the TX/RX alignment markers */ 3636 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL5, 0xa157}, 3637 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL7, 0xcbe2}, 3638 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL6, 0x7537}, 3639 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL9, 0xa157}, 3640 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL11, 0xcbe2}, 3641 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL10, 0x7537}, 3642 /* Step 2 - Configure the NP registers */ 3643 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_USERB0_CTRL, 0x000a}, 3644 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL1, 0x6400}, 3645 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL3, 0x0620}, 3646 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CODE_FIELD, 0x0157}, 3647 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI1, 0x6464}, 3648 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI2, 0x3150}, 3649 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI3, 0x3150}, 3650 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0157}, 3651 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0620} 3652 }; 3653 DP(NETIF_MSG_LINK, "Enabling 20G-KR2\n"); 3654 3655 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 3656 MDIO_WC_REG_CL49_USERB0_CTRL, (3<<6)); 3657 3658 for (i = 0; i < ARRAY_SIZE(reg_set); i++) 3659 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg, 3660 reg_set[i].val); 3661 3662 /* Start KR2 work-around timer which handles BCM8073 link-parner */ 3663 params->link_attr_sync |= LINK_ATTR_SYNC_KR2_ENABLE; 3664 bnx2x_update_link_attr(params, params->link_attr_sync); 3665 } 3666 3667 static void bnx2x_disable_kr2(struct link_params *params, 3668 struct link_vars *vars, 3669 struct bnx2x_phy *phy) 3670 { 3671 struct bnx2x *bp = params->bp; 3672 int i; 3673 static struct bnx2x_reg_set reg_set[] = { 3674 /* Step 1 - Program the TX/RX alignment markers */ 3675 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL5, 0x7690}, 3676 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL7, 0xe647}, 3677 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL6, 0xc4f0}, 3678 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL9, 0x7690}, 3679 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL11, 0xe647}, 3680 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL10, 0xc4f0}, 3681 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_USERB0_CTRL, 0x000c}, 3682 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL1, 0x6000}, 3683 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL3, 0x0000}, 3684 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CODE_FIELD, 0x0002}, 3685 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI1, 0x0000}, 3686 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI2, 0x0af7}, 3687 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI3, 0x0af7}, 3688 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0002}, 3689 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0000} 3690 }; 3691 DP(NETIF_MSG_LINK, "Disabling 20G-KR2\n"); 3692 3693 for (i = 0; i < ARRAY_SIZE(reg_set); i++) 3694 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg, 3695 reg_set[i].val); 3696 params->link_attr_sync &= ~LINK_ATTR_SYNC_KR2_ENABLE; 3697 bnx2x_update_link_attr(params, params->link_attr_sync); 3698 3699 vars->check_kr2_recovery_cnt = CHECK_KR2_RECOVERY_CNT; 3700 } 3701 3702 static void bnx2x_warpcore_set_lpi_passthrough(struct bnx2x_phy *phy, 3703 struct link_params *params) 3704 { 3705 struct bnx2x *bp = params->bp; 3706 3707 DP(NETIF_MSG_LINK, "Configure WC for LPI pass through\n"); 3708 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3709 MDIO_WC_REG_EEE_COMBO_CONTROL0, 0x7c); 3710 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 3711 MDIO_WC_REG_DIGITAL4_MISC5, 0xc000); 3712 } 3713 3714 static void bnx2x_warpcore_restart_AN_KR(struct bnx2x_phy *phy, 3715 struct link_params *params) 3716 { 3717 /* Restart autoneg on the leading lane only */ 3718 struct bnx2x *bp = params->bp; 3719 u16 lane = bnx2x_get_warpcore_lane(phy, params); 3720 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, 3721 MDIO_AER_BLOCK_AER_REG, lane); 3722 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, 3723 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200); 3724 3725 /* Restore AER */ 3726 bnx2x_set_aer_mmd(params, phy); 3727 } 3728 3729 static void bnx2x_warpcore_enable_AN_KR(struct bnx2x_phy *phy, 3730 struct link_params *params, 3731 struct link_vars *vars) { 3732 u16 lane, i, cl72_ctrl, an_adv = 0, val; 3733 u32 wc_lane_config; 3734 struct bnx2x *bp = params->bp; 3735 static struct bnx2x_reg_set reg_set[] = { 3736 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7}, 3737 {MDIO_PMA_DEVAD, MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0x0}, 3738 {MDIO_WC_DEVAD, MDIO_WC_REG_RX66_CONTROL, 0x7415}, 3739 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x6190}, 3740 /* Disable Autoneg: re-enable it after adv is done. */ 3741 {MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0}, 3742 {MDIO_PMA_DEVAD, MDIO_WC_REG_PMD_KR_CONTROL, 0x2}, 3743 {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP, 0}, 3744 }; 3745 DP(NETIF_MSG_LINK, "Enable Auto Negotiation for KR\n"); 3746 /* Set to default registers that may be overriden by 10G force */ 3747 for (i = 0; i < ARRAY_SIZE(reg_set); i++) 3748 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg, 3749 reg_set[i].val); 3750 3751 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 3752 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, &cl72_ctrl); 3753 cl72_ctrl &= 0x08ff; 3754 cl72_ctrl |= 0x3800; 3755 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3756 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, cl72_ctrl); 3757 3758 /* Check adding advertisement for 1G KX */ 3759 if (((vars->line_speed == SPEED_AUTO_NEG) && 3760 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) || 3761 (vars->line_speed == SPEED_1000)) { 3762 u16 addr = MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2; 3763 an_adv |= (1<<5); 3764 3765 /* Enable CL37 1G Parallel Detect */ 3766 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, addr, 0x1); 3767 DP(NETIF_MSG_LINK, "Advertize 1G\n"); 3768 } 3769 if (((vars->line_speed == SPEED_AUTO_NEG) && 3770 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) || 3771 (vars->line_speed == SPEED_10000)) { 3772 /* Check adding advertisement for 10G KR */ 3773 an_adv |= (1<<7); 3774 /* Enable 10G Parallel Detect */ 3775 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, 3776 MDIO_AER_BLOCK_AER_REG, 0); 3777 3778 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, 3779 MDIO_WC_REG_PAR_DET_10G_CTRL, 1); 3780 bnx2x_set_aer_mmd(params, phy); 3781 DP(NETIF_MSG_LINK, "Advertize 10G\n"); 3782 } 3783 3784 /* Set Transmit PMD settings */ 3785 lane = bnx2x_get_warpcore_lane(phy, params); 3786 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3787 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 3788 WC_TX_DRIVER(0x02, 0x06, 0x09, 0)); 3789 /* Configure the next lane if dual mode */ 3790 if (phy->flags & FLAGS_WC_DUAL_MODE) 3791 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3792 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*(lane+1), 3793 WC_TX_DRIVER(0x02, 0x06, 0x09, 0)); 3794 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3795 MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL, 3796 0x03f0); 3797 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3798 MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL, 3799 0x03f0); 3800 3801 /* Advertised speeds */ 3802 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, 3803 MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, an_adv); 3804 3805 /* Advertised and set FEC (Forward Error Correction) */ 3806 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, 3807 MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2, 3808 (MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY | 3809 MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ)); 3810 3811 /* Enable CL37 BAM */ 3812 if (REG_RD(bp, params->shmem_base + 3813 offsetof(struct shmem_region, dev_info. 3814 port_hw_config[params->port].default_cfg)) & 3815 PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) { 3816 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 3817 MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL, 3818 1); 3819 DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n"); 3820 } 3821 3822 /* Advertise pause */ 3823 bnx2x_ext_phy_set_pause(params, phy, vars); 3824 vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY; 3825 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 3826 MDIO_WC_REG_DIGITAL5_MISC7, 0x100); 3827 3828 /* Over 1G - AN local device user page 1 */ 3829 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3830 MDIO_WC_REG_DIGITAL3_UP1, 0x1f); 3831 3832 if (((phy->req_line_speed == SPEED_AUTO_NEG) && 3833 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) || 3834 (phy->req_line_speed == SPEED_20000)) { 3835 3836 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, 3837 MDIO_AER_BLOCK_AER_REG, lane); 3838 3839 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 3840 MDIO_WC_REG_RX1_PCI_CTRL + (0x10*lane), 3841 (1<<11)); 3842 3843 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3844 MDIO_WC_REG_XGXS_X2_CONTROL3, 0x7); 3845 bnx2x_set_aer_mmd(params, phy); 3846 3847 bnx2x_warpcore_enable_AN_KR2(phy, params, vars); 3848 } else { 3849 /* Enable Auto-Detect to support 1G over CL37 as well */ 3850 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3851 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0x10); 3852 wc_lane_config = REG_RD(bp, params->shmem_base + 3853 offsetof(struct shmem_region, dev_info. 3854 shared_hw_config.wc_lane_config)); 3855 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 3856 MDIO_WC_REG_RX0_PCI_CTRL + (lane << 4), &val); 3857 /* Force cl48 sync_status LOW to avoid getting stuck in CL73 3858 * parallel-detect loop when CL73 and CL37 are enabled. 3859 */ 3860 val |= 1 << 11; 3861 3862 /* Restore Polarity settings in case it was run over by 3863 * previous link owner 3864 */ 3865 if (wc_lane_config & 3866 (SHARED_HW_CFG_RX_LANE0_POL_FLIP_ENABLED << lane)) 3867 val |= 3 << 2; 3868 else 3869 val &= ~(3 << 2); 3870 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3871 MDIO_WC_REG_RX0_PCI_CTRL + (lane << 4), 3872 val); 3873 3874 bnx2x_disable_kr2(params, vars, phy); 3875 } 3876 3877 /* Enable Autoneg: only on the main lane */ 3878 bnx2x_warpcore_restart_AN_KR(phy, params); 3879 } 3880 3881 static void bnx2x_warpcore_set_10G_KR(struct bnx2x_phy *phy, 3882 struct link_params *params, 3883 struct link_vars *vars) 3884 { 3885 struct bnx2x *bp = params->bp; 3886 u16 val16, i, lane; 3887 static struct bnx2x_reg_set reg_set[] = { 3888 /* Disable Autoneg */ 3889 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7}, 3890 {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, 3891 0x3f00}, 3892 {MDIO_AN_DEVAD, MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, 0}, 3893 {MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0}, 3894 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL3_UP1, 0x1}, 3895 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL5_MISC7, 0xa}, 3896 /* Leave cl72 training enable, needed for KR */ 3897 {MDIO_PMA_DEVAD, MDIO_WC_REG_PMD_KR_CONTROL, 0x2} 3898 }; 3899 3900 for (i = 0; i < ARRAY_SIZE(reg_set); i++) 3901 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg, 3902 reg_set[i].val); 3903 3904 lane = bnx2x_get_warpcore_lane(phy, params); 3905 /* Global registers */ 3906 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, 3907 MDIO_AER_BLOCK_AER_REG, 0); 3908 /* Disable CL36 PCS Tx */ 3909 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 3910 MDIO_WC_REG_XGXSBLK1_LANECTRL0, &val16); 3911 val16 &= ~(0x0011 << lane); 3912 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3913 MDIO_WC_REG_XGXSBLK1_LANECTRL0, val16); 3914 3915 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 3916 MDIO_WC_REG_XGXSBLK1_LANECTRL1, &val16); 3917 val16 |= (0x0303 << (lane << 1)); 3918 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3919 MDIO_WC_REG_XGXSBLK1_LANECTRL1, val16); 3920 /* Restore AER */ 3921 bnx2x_set_aer_mmd(params, phy); 3922 /* Set speed via PMA/PMD register */ 3923 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 3924 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040); 3925 3926 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 3927 MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0xB); 3928 3929 /* Enable encoded forced speed */ 3930 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3931 MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x30); 3932 3933 /* Turn TX scramble payload only the 64/66 scrambler */ 3934 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3935 MDIO_WC_REG_TX66_CONTROL, 0x9); 3936 3937 /* Turn RX scramble payload only the 64/66 scrambler */ 3938 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 3939 MDIO_WC_REG_RX66_CONTROL, 0xF9); 3940 3941 /* Set and clear loopback to cause a reset to 64/66 decoder */ 3942 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3943 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x4000); 3944 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3945 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0); 3946 3947 } 3948 3949 static void bnx2x_warpcore_set_10G_XFI(struct bnx2x_phy *phy, 3950 struct link_params *params, 3951 u8 is_xfi) 3952 { 3953 struct bnx2x *bp = params->bp; 3954 u16 misc1_val, tap_val, tx_driver_val, lane, val; 3955 u32 cfg_tap_val, tx_drv_brdct, tx_equal; 3956 u32 ifir_val, ipost2_val, ipre_driver_val; 3957 3958 /* Hold rxSeqStart */ 3959 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 3960 MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x8000); 3961 3962 /* Hold tx_fifo_reset */ 3963 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 3964 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, 0x1); 3965 3966 /* Disable CL73 AN */ 3967 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0); 3968 3969 /* Disable 100FX Enable and Auto-Detect */ 3970 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, 3971 MDIO_WC_REG_FX100_CTRL1, 0xFFFA); 3972 3973 /* Disable 100FX Idle detect */ 3974 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 3975 MDIO_WC_REG_FX100_CTRL3, 0x0080); 3976 3977 /* Set Block address to Remote PHY & Clear forced_speed[5] */ 3978 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, 3979 MDIO_WC_REG_DIGITAL4_MISC3, 0xFF7F); 3980 3981 /* Turn off auto-detect & fiber mode */ 3982 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, 3983 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 3984 0xFFEE); 3985 3986 /* Set filter_force_link, disable_false_link and parallel_detect */ 3987 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 3988 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &val); 3989 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3990 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 3991 ((val | 0x0006) & 0xFFFE)); 3992 3993 /* Set XFI / SFI */ 3994 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 3995 MDIO_WC_REG_SERDESDIGITAL_MISC1, &misc1_val); 3996 3997 misc1_val &= ~(0x1f); 3998 3999 if (is_xfi) { 4000 misc1_val |= 0x5; 4001 tap_val = WC_TX_FIR(0x08, 0x37, 0x00); 4002 tx_driver_val = WC_TX_DRIVER(0x00, 0x02, 0x03, 0); 4003 } else { 4004 cfg_tap_val = REG_RD(bp, params->shmem_base + 4005 offsetof(struct shmem_region, dev_info. 4006 port_hw_config[params->port]. 4007 sfi_tap_values)); 4008 4009 tx_equal = cfg_tap_val & PORT_HW_CFG_TX_EQUALIZATION_MASK; 4010 4011 misc1_val |= 0x9; 4012 4013 /* TAP values are controlled by nvram, if value there isn't 0 */ 4014 if (tx_equal) 4015 tap_val = (u16)tx_equal; 4016 else 4017 tap_val = WC_TX_FIR(0x0f, 0x2b, 0x02); 4018 4019 ifir_val = DEFAULT_TX_DRV_IFIR; 4020 ipost2_val = DEFAULT_TX_DRV_POST2; 4021 ipre_driver_val = DEFAULT_TX_DRV_IPRE_DRIVER; 4022 tx_drv_brdct = DEFAULT_TX_DRV_BRDCT; 4023 4024 /* If any of the IFIR/IPRE_DRIVER/POST@ is set, apply all 4025 * configuration. 4026 */ 4027 if (cfg_tap_val & (PORT_HW_CFG_TX_DRV_IFIR_MASK | 4028 PORT_HW_CFG_TX_DRV_IPREDRIVER_MASK | 4029 PORT_HW_CFG_TX_DRV_POST2_MASK)) { 4030 ifir_val = (cfg_tap_val & 4031 PORT_HW_CFG_TX_DRV_IFIR_MASK) >> 4032 PORT_HW_CFG_TX_DRV_IFIR_SHIFT; 4033 ipre_driver_val = (cfg_tap_val & 4034 PORT_HW_CFG_TX_DRV_IPREDRIVER_MASK) 4035 >> PORT_HW_CFG_TX_DRV_IPREDRIVER_SHIFT; 4036 ipost2_val = (cfg_tap_val & 4037 PORT_HW_CFG_TX_DRV_POST2_MASK) >> 4038 PORT_HW_CFG_TX_DRV_POST2_SHIFT; 4039 } 4040 4041 if (cfg_tap_val & PORT_HW_CFG_TX_DRV_BROADCAST_MASK) { 4042 tx_drv_brdct = (cfg_tap_val & 4043 PORT_HW_CFG_TX_DRV_BROADCAST_MASK) >> 4044 PORT_HW_CFG_TX_DRV_BROADCAST_SHIFT; 4045 } 4046 4047 tx_driver_val = WC_TX_DRIVER(ipost2_val, tx_drv_brdct, 4048 ipre_driver_val, ifir_val); 4049 } 4050 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4051 MDIO_WC_REG_SERDESDIGITAL_MISC1, misc1_val); 4052 4053 /* Set Transmit PMD settings */ 4054 lane = bnx2x_get_warpcore_lane(phy, params); 4055 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4056 MDIO_WC_REG_TX_FIR_TAP, 4057 tap_val | MDIO_WC_REG_TX_FIR_TAP_ENABLE); 4058 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4059 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 4060 tx_driver_val); 4061 4062 /* Enable fiber mode, enable and invert sig_det */ 4063 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 4064 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0xd); 4065 4066 /* Set Block address to Remote PHY & Set forced_speed[5], 40bit mode */ 4067 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 4068 MDIO_WC_REG_DIGITAL4_MISC3, 0x8080); 4069 4070 bnx2x_warpcore_set_lpi_passthrough(phy, params); 4071 4072 /* 10G XFI Full Duplex */ 4073 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4074 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x100); 4075 4076 /* Release tx_fifo_reset */ 4077 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, 4078 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, 4079 0xFFFE); 4080 /* Release rxSeqStart */ 4081 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, 4082 MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x7FFF); 4083 } 4084 4085 static void bnx2x_warpcore_set_20G_force_KR2(struct bnx2x_phy *phy, 4086 struct link_params *params) 4087 { 4088 u16 val; 4089 struct bnx2x *bp = params->bp; 4090 /* Set global registers, so set AER lane to 0 */ 4091 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, 4092 MDIO_AER_BLOCK_AER_REG, 0); 4093 4094 /* Disable sequencer */ 4095 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, 4096 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, ~(1<<13)); 4097 4098 bnx2x_set_aer_mmd(params, phy); 4099 4100 bnx2x_cl45_read_and_write(bp, phy, MDIO_PMA_DEVAD, 4101 MDIO_WC_REG_PMD_KR_CONTROL, ~(1<<1)); 4102 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, 4103 MDIO_AN_REG_CTRL, 0); 4104 /* Turn off CL73 */ 4105 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 4106 MDIO_WC_REG_CL73_USERB0_CTRL, &val); 4107 val &= ~(1<<5); 4108 val |= (1<<6); 4109 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4110 MDIO_WC_REG_CL73_USERB0_CTRL, val); 4111 4112 /* Set 20G KR2 force speed */ 4113 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 4114 MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x1f); 4115 4116 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 4117 MDIO_WC_REG_DIGITAL4_MISC3, (1<<7)); 4118 4119 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 4120 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, &val); 4121 val &= ~(3<<14); 4122 val |= (1<<15); 4123 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4124 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, val); 4125 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4126 MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP, 0x835A); 4127 4128 /* Enable sequencer (over lane 0) */ 4129 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, 4130 MDIO_AER_BLOCK_AER_REG, 0); 4131 4132 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 4133 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, (1<<13)); 4134 4135 bnx2x_set_aer_mmd(params, phy); 4136 } 4137 4138 static void bnx2x_warpcore_set_20G_DXGXS(struct bnx2x *bp, 4139 struct bnx2x_phy *phy, 4140 u16 lane) 4141 { 4142 /* Rx0 anaRxControl1G */ 4143 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4144 MDIO_WC_REG_RX0_ANARXCONTROL1G, 0x90); 4145 4146 /* Rx2 anaRxControl1G */ 4147 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4148 MDIO_WC_REG_RX2_ANARXCONTROL1G, 0x90); 4149 4150 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4151 MDIO_WC_REG_RX66_SCW0, 0xE070); 4152 4153 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4154 MDIO_WC_REG_RX66_SCW1, 0xC0D0); 4155 4156 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4157 MDIO_WC_REG_RX66_SCW2, 0xA0B0); 4158 4159 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4160 MDIO_WC_REG_RX66_SCW3, 0x8090); 4161 4162 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4163 MDIO_WC_REG_RX66_SCW0_MASK, 0xF0F0); 4164 4165 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4166 MDIO_WC_REG_RX66_SCW1_MASK, 0xF0F0); 4167 4168 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4169 MDIO_WC_REG_RX66_SCW2_MASK, 0xF0F0); 4170 4171 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4172 MDIO_WC_REG_RX66_SCW3_MASK, 0xF0F0); 4173 4174 /* Serdes Digital Misc1 */ 4175 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4176 MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6008); 4177 4178 /* Serdes Digital4 Misc3 */ 4179 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4180 MDIO_WC_REG_DIGITAL4_MISC3, 0x8088); 4181 4182 /* Set Transmit PMD settings */ 4183 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4184 MDIO_WC_REG_TX_FIR_TAP, 4185 (WC_TX_FIR(0x12, 0x2d, 0x00) | 4186 MDIO_WC_REG_TX_FIR_TAP_ENABLE)); 4187 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4188 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 4189 WC_TX_DRIVER(0x02, 0x02, 0x02, 0)); 4190 } 4191 4192 static void bnx2x_warpcore_set_sgmii_speed(struct bnx2x_phy *phy, 4193 struct link_params *params, 4194 u8 fiber_mode, 4195 u8 always_autoneg) 4196 { 4197 struct bnx2x *bp = params->bp; 4198 u16 val16, digctrl_kx1, digctrl_kx2; 4199 4200 /* Clear XFI clock comp in non-10G single lane mode. */ 4201 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, 4202 MDIO_WC_REG_RX66_CONTROL, ~(3<<13)); 4203 4204 bnx2x_warpcore_set_lpi_passthrough(phy, params); 4205 4206 if (always_autoneg || phy->req_line_speed == SPEED_AUTO_NEG) { 4207 /* SGMII Autoneg */ 4208 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 4209 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 4210 0x1000); 4211 DP(NETIF_MSG_LINK, "set SGMII AUTONEG\n"); 4212 } else { 4213 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 4214 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16); 4215 val16 &= 0xcebf; 4216 switch (phy->req_line_speed) { 4217 case SPEED_10: 4218 break; 4219 case SPEED_100: 4220 val16 |= 0x2000; 4221 break; 4222 case SPEED_1000: 4223 val16 |= 0x0040; 4224 break; 4225 default: 4226 DP(NETIF_MSG_LINK, 4227 "Speed not supported: 0x%x\n", phy->req_line_speed); 4228 return; 4229 } 4230 4231 if (phy->req_duplex == DUPLEX_FULL) 4232 val16 |= 0x0100; 4233 4234 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4235 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16); 4236 4237 DP(NETIF_MSG_LINK, "set SGMII force speed %d\n", 4238 phy->req_line_speed); 4239 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 4240 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16); 4241 DP(NETIF_MSG_LINK, " (readback) %x\n", val16); 4242 } 4243 4244 /* SGMII Slave mode and disable signal detect */ 4245 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 4246 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &digctrl_kx1); 4247 if (fiber_mode) 4248 digctrl_kx1 = 1; 4249 else 4250 digctrl_kx1 &= 0xff4a; 4251 4252 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4253 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 4254 digctrl_kx1); 4255 4256 /* Turn off parallel detect */ 4257 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 4258 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &digctrl_kx2); 4259 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4260 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 4261 (digctrl_kx2 & ~(1<<2))); 4262 4263 /* Re-enable parallel detect */ 4264 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4265 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 4266 (digctrl_kx2 | (1<<2))); 4267 4268 /* Enable autodet */ 4269 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4270 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 4271 (digctrl_kx1 | 0x10)); 4272 } 4273 4274 static void bnx2x_warpcore_reset_lane(struct bnx2x *bp, 4275 struct bnx2x_phy *phy, 4276 u8 reset) 4277 { 4278 u16 val; 4279 /* Take lane out of reset after configuration is finished */ 4280 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 4281 MDIO_WC_REG_DIGITAL5_MISC6, &val); 4282 if (reset) 4283 val |= 0xC000; 4284 else 4285 val &= 0x3FFF; 4286 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4287 MDIO_WC_REG_DIGITAL5_MISC6, val); 4288 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 4289 MDIO_WC_REG_DIGITAL5_MISC6, &val); 4290 } 4291 /* Clear SFI/XFI link settings registers */ 4292 static void bnx2x_warpcore_clear_regs(struct bnx2x_phy *phy, 4293 struct link_params *params, 4294 u16 lane) 4295 { 4296 struct bnx2x *bp = params->bp; 4297 u16 i; 4298 static struct bnx2x_reg_set wc_regs[] = { 4299 {MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0}, 4300 {MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL1, 0x014a}, 4301 {MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL3, 0x0800}, 4302 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL4_MISC3, 0x8008}, 4303 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 4304 0x0195}, 4305 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 4306 0x0007}, 4307 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, 4308 0x0002}, 4309 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6000}, 4310 {MDIO_WC_DEVAD, MDIO_WC_REG_TX_FIR_TAP, 0x0000}, 4311 {MDIO_WC_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040}, 4312 {MDIO_WC_DEVAD, MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0x0140} 4313 }; 4314 /* Set XFI clock comp as default. */ 4315 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 4316 MDIO_WC_REG_RX66_CONTROL, (3<<13)); 4317 4318 for (i = 0; i < ARRAY_SIZE(wc_regs); i++) 4319 bnx2x_cl45_write(bp, phy, wc_regs[i].devad, wc_regs[i].reg, 4320 wc_regs[i].val); 4321 4322 lane = bnx2x_get_warpcore_lane(phy, params); 4323 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4324 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 0x0990); 4325 4326 } 4327 4328 static int bnx2x_get_mod_abs_int_cfg(struct bnx2x *bp, 4329 u32 chip_id, 4330 u32 shmem_base, u8 port, 4331 u8 *gpio_num, u8 *gpio_port) 4332 { 4333 u32 cfg_pin; 4334 *gpio_num = 0; 4335 *gpio_port = 0; 4336 if (CHIP_IS_E3(bp)) { 4337 cfg_pin = (REG_RD(bp, shmem_base + 4338 offsetof(struct shmem_region, 4339 dev_info.port_hw_config[port].e3_sfp_ctrl)) & 4340 PORT_HW_CFG_E3_MOD_ABS_MASK) >> 4341 PORT_HW_CFG_E3_MOD_ABS_SHIFT; 4342 4343 /* Should not happen. This function called upon interrupt 4344 * triggered by GPIO ( since EPIO can only generate interrupts 4345 * to MCP). 4346 * So if this function was called and none of the GPIOs was set, 4347 * it means the shit hit the fan. 4348 */ 4349 if ((cfg_pin < PIN_CFG_GPIO0_P0) || 4350 (cfg_pin > PIN_CFG_GPIO3_P1)) { 4351 DP(NETIF_MSG_LINK, 4352 "No cfg pin %x for module detect indication\n", 4353 cfg_pin); 4354 return -EINVAL; 4355 } 4356 4357 *gpio_num = (cfg_pin - PIN_CFG_GPIO0_P0) & 0x3; 4358 *gpio_port = (cfg_pin - PIN_CFG_GPIO0_P0) >> 2; 4359 } else { 4360 *gpio_num = MISC_REGISTERS_GPIO_3; 4361 *gpio_port = port; 4362 } 4363 4364 return 0; 4365 } 4366 4367 static int bnx2x_is_sfp_module_plugged(struct bnx2x_phy *phy, 4368 struct link_params *params) 4369 { 4370 struct bnx2x *bp = params->bp; 4371 u8 gpio_num, gpio_port; 4372 u32 gpio_val; 4373 if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id, 4374 params->shmem_base, params->port, 4375 &gpio_num, &gpio_port) != 0) 4376 return 0; 4377 gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port); 4378 4379 /* Call the handling function in case module is detected */ 4380 if (gpio_val == 0) 4381 return 1; 4382 else 4383 return 0; 4384 } 4385 static int bnx2x_warpcore_get_sigdet(struct bnx2x_phy *phy, 4386 struct link_params *params) 4387 { 4388 u16 gp2_status_reg0, lane; 4389 struct bnx2x *bp = params->bp; 4390 4391 lane = bnx2x_get_warpcore_lane(phy, params); 4392 4393 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_0, 4394 &gp2_status_reg0); 4395 4396 return (gp2_status_reg0 >> (8+lane)) & 0x1; 4397 } 4398 4399 static void bnx2x_warpcore_config_runtime(struct bnx2x_phy *phy, 4400 struct link_params *params, 4401 struct link_vars *vars) 4402 { 4403 struct bnx2x *bp = params->bp; 4404 u32 serdes_net_if; 4405 u16 gp_status1 = 0, lnkup = 0, lnkup_kr = 0; 4406 4407 vars->turn_to_run_wc_rt = vars->turn_to_run_wc_rt ? 0 : 1; 4408 4409 if (!vars->turn_to_run_wc_rt) 4410 return; 4411 4412 if (vars->rx_tx_asic_rst) { 4413 u16 lane = bnx2x_get_warpcore_lane(phy, params); 4414 serdes_net_if = (REG_RD(bp, params->shmem_base + 4415 offsetof(struct shmem_region, dev_info. 4416 port_hw_config[params->port].default_cfg)) & 4417 PORT_HW_CFG_NET_SERDES_IF_MASK); 4418 4419 switch (serdes_net_if) { 4420 case PORT_HW_CFG_NET_SERDES_IF_KR: 4421 /* Do we get link yet? */ 4422 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 0x81d1, 4423 &gp_status1); 4424 lnkup = (gp_status1 >> (8+lane)) & 0x1;/* 1G */ 4425 /*10G KR*/ 4426 lnkup_kr = (gp_status1 >> (12+lane)) & 0x1; 4427 4428 if (lnkup_kr || lnkup) { 4429 vars->rx_tx_asic_rst = 0; 4430 } else { 4431 /* Reset the lane to see if link comes up.*/ 4432 bnx2x_warpcore_reset_lane(bp, phy, 1); 4433 bnx2x_warpcore_reset_lane(bp, phy, 0); 4434 4435 /* Restart Autoneg */ 4436 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, 4437 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200); 4438 4439 vars->rx_tx_asic_rst--; 4440 DP(NETIF_MSG_LINK, "0x%x retry left\n", 4441 vars->rx_tx_asic_rst); 4442 } 4443 break; 4444 4445 default: 4446 break; 4447 } 4448 4449 } /*params->rx_tx_asic_rst*/ 4450 4451 } 4452 static void bnx2x_warpcore_config_sfi(struct bnx2x_phy *phy, 4453 struct link_params *params) 4454 { 4455 u16 lane = bnx2x_get_warpcore_lane(phy, params); 4456 struct bnx2x *bp = params->bp; 4457 bnx2x_warpcore_clear_regs(phy, params, lane); 4458 if ((params->req_line_speed[LINK_CONFIG_IDX(INT_PHY)] == 4459 SPEED_10000) && 4460 (phy->media_type != ETH_PHY_SFP_1G_FIBER)) { 4461 DP(NETIF_MSG_LINK, "Setting 10G SFI\n"); 4462 bnx2x_warpcore_set_10G_XFI(phy, params, 0); 4463 } else { 4464 DP(NETIF_MSG_LINK, "Setting 1G Fiber\n"); 4465 bnx2x_warpcore_set_sgmii_speed(phy, params, 1, 0); 4466 } 4467 } 4468 4469 static void bnx2x_sfp_e3_set_transmitter(struct link_params *params, 4470 struct bnx2x_phy *phy, 4471 u8 tx_en) 4472 { 4473 struct bnx2x *bp = params->bp; 4474 u32 cfg_pin; 4475 u8 port = params->port; 4476 4477 cfg_pin = REG_RD(bp, params->shmem_base + 4478 offsetof(struct shmem_region, 4479 dev_info.port_hw_config[port].e3_sfp_ctrl)) & 4480 PORT_HW_CFG_E3_TX_LASER_MASK; 4481 /* Set the !tx_en since this pin is DISABLE_TX_LASER */ 4482 DP(NETIF_MSG_LINK, "Setting WC TX to %d\n", tx_en); 4483 4484 /* For 20G, the expected pin to be used is 3 pins after the current */ 4485 bnx2x_set_cfg_pin(bp, cfg_pin, tx_en ^ 1); 4486 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G) 4487 bnx2x_set_cfg_pin(bp, cfg_pin + 3, tx_en ^ 1); 4488 } 4489 4490 static void bnx2x_warpcore_config_init(struct bnx2x_phy *phy, 4491 struct link_params *params, 4492 struct link_vars *vars) 4493 { 4494 struct bnx2x *bp = params->bp; 4495 u32 serdes_net_if; 4496 u8 fiber_mode; 4497 u16 lane = bnx2x_get_warpcore_lane(phy, params); 4498 serdes_net_if = (REG_RD(bp, params->shmem_base + 4499 offsetof(struct shmem_region, dev_info. 4500 port_hw_config[params->port].default_cfg)) & 4501 PORT_HW_CFG_NET_SERDES_IF_MASK); 4502 DP(NETIF_MSG_LINK, "Begin Warpcore init, link_speed %d, " 4503 "serdes_net_if = 0x%x\n", 4504 vars->line_speed, serdes_net_if); 4505 bnx2x_set_aer_mmd(params, phy); 4506 bnx2x_warpcore_reset_lane(bp, phy, 1); 4507 vars->phy_flags |= PHY_XGXS_FLAG; 4508 if ((serdes_net_if == PORT_HW_CFG_NET_SERDES_IF_SGMII) || 4509 (phy->req_line_speed && 4510 ((phy->req_line_speed == SPEED_100) || 4511 (phy->req_line_speed == SPEED_10)))) { 4512 vars->phy_flags |= PHY_SGMII_FLAG; 4513 DP(NETIF_MSG_LINK, "Setting SGMII mode\n"); 4514 bnx2x_warpcore_clear_regs(phy, params, lane); 4515 bnx2x_warpcore_set_sgmii_speed(phy, params, 0, 1); 4516 } else { 4517 switch (serdes_net_if) { 4518 case PORT_HW_CFG_NET_SERDES_IF_KR: 4519 /* Enable KR Auto Neg */ 4520 if (params->loopback_mode != LOOPBACK_EXT) 4521 bnx2x_warpcore_enable_AN_KR(phy, params, vars); 4522 else { 4523 DP(NETIF_MSG_LINK, "Setting KR 10G-Force\n"); 4524 bnx2x_warpcore_set_10G_KR(phy, params, vars); 4525 } 4526 break; 4527 4528 case PORT_HW_CFG_NET_SERDES_IF_XFI: 4529 bnx2x_warpcore_clear_regs(phy, params, lane); 4530 if (vars->line_speed == SPEED_10000) { 4531 DP(NETIF_MSG_LINK, "Setting 10G XFI\n"); 4532 bnx2x_warpcore_set_10G_XFI(phy, params, 1); 4533 } else { 4534 if (SINGLE_MEDIA_DIRECT(params)) { 4535 DP(NETIF_MSG_LINK, "1G Fiber\n"); 4536 fiber_mode = 1; 4537 } else { 4538 DP(NETIF_MSG_LINK, "10/100/1G SGMII\n"); 4539 fiber_mode = 0; 4540 } 4541 bnx2x_warpcore_set_sgmii_speed(phy, 4542 params, 4543 fiber_mode, 4544 0); 4545 } 4546 4547 break; 4548 4549 case PORT_HW_CFG_NET_SERDES_IF_SFI: 4550 /* Issue Module detection if module is plugged, or 4551 * enabled transmitter to avoid current leakage in case 4552 * no module is connected 4553 */ 4554 if ((params->loopback_mode == LOOPBACK_NONE) || 4555 (params->loopback_mode == LOOPBACK_EXT)) { 4556 if (bnx2x_is_sfp_module_plugged(phy, params)) 4557 bnx2x_sfp_module_detection(phy, params); 4558 else 4559 bnx2x_sfp_e3_set_transmitter(params, 4560 phy, 1); 4561 } 4562 4563 bnx2x_warpcore_config_sfi(phy, params); 4564 break; 4565 4566 case PORT_HW_CFG_NET_SERDES_IF_DXGXS: 4567 if (vars->line_speed != SPEED_20000) { 4568 DP(NETIF_MSG_LINK, "Speed not supported yet\n"); 4569 return; 4570 } 4571 DP(NETIF_MSG_LINK, "Setting 20G DXGXS\n"); 4572 bnx2x_warpcore_set_20G_DXGXS(bp, phy, lane); 4573 /* Issue Module detection */ 4574 4575 bnx2x_sfp_module_detection(phy, params); 4576 break; 4577 case PORT_HW_CFG_NET_SERDES_IF_KR2: 4578 if (!params->loopback_mode) { 4579 bnx2x_warpcore_enable_AN_KR(phy, params, vars); 4580 } else { 4581 DP(NETIF_MSG_LINK, "Setting KR 20G-Force\n"); 4582 bnx2x_warpcore_set_20G_force_KR2(phy, params); 4583 } 4584 break; 4585 default: 4586 DP(NETIF_MSG_LINK, 4587 "Unsupported Serdes Net Interface 0x%x\n", 4588 serdes_net_if); 4589 return; 4590 } 4591 } 4592 4593 /* Take lane out of reset after configuration is finished */ 4594 bnx2x_warpcore_reset_lane(bp, phy, 0); 4595 DP(NETIF_MSG_LINK, "Exit config init\n"); 4596 } 4597 4598 static void bnx2x_warpcore_link_reset(struct bnx2x_phy *phy, 4599 struct link_params *params) 4600 { 4601 struct bnx2x *bp = params->bp; 4602 u16 val16, lane; 4603 bnx2x_sfp_e3_set_transmitter(params, phy, 0); 4604 bnx2x_set_mdio_emac_per_phy(bp, params); 4605 bnx2x_set_aer_mmd(params, phy); 4606 /* Global register */ 4607 bnx2x_warpcore_reset_lane(bp, phy, 1); 4608 4609 /* Clear loopback settings (if any) */ 4610 /* 10G & 20G */ 4611 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, 4612 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0xBFFF); 4613 4614 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, 4615 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0xfffe); 4616 4617 /* Update those 1-copy registers */ 4618 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, 4619 MDIO_AER_BLOCK_AER_REG, 0); 4620 /* Enable 1G MDIO (1-copy) */ 4621 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, 4622 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, 4623 ~0x10); 4624 4625 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, 4626 MDIO_WC_REG_XGXSBLK1_LANECTRL2, 0xff00); 4627 lane = bnx2x_get_warpcore_lane(phy, params); 4628 /* Disable CL36 PCS Tx */ 4629 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 4630 MDIO_WC_REG_XGXSBLK1_LANECTRL0, &val16); 4631 val16 |= (0x11 << lane); 4632 if (phy->flags & FLAGS_WC_DUAL_MODE) 4633 val16 |= (0x22 << lane); 4634 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4635 MDIO_WC_REG_XGXSBLK1_LANECTRL0, val16); 4636 4637 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 4638 MDIO_WC_REG_XGXSBLK1_LANECTRL1, &val16); 4639 val16 &= ~(0x0303 << (lane << 1)); 4640 val16 |= (0x0101 << (lane << 1)); 4641 if (phy->flags & FLAGS_WC_DUAL_MODE) { 4642 val16 &= ~(0x0c0c << (lane << 1)); 4643 val16 |= (0x0404 << (lane << 1)); 4644 } 4645 4646 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4647 MDIO_WC_REG_XGXSBLK1_LANECTRL1, val16); 4648 /* Restore AER */ 4649 bnx2x_set_aer_mmd(params, phy); 4650 4651 } 4652 4653 static void bnx2x_set_warpcore_loopback(struct bnx2x_phy *phy, 4654 struct link_params *params) 4655 { 4656 struct bnx2x *bp = params->bp; 4657 u16 val16; 4658 u32 lane; 4659 DP(NETIF_MSG_LINK, "Setting Warpcore loopback type %x, speed %d\n", 4660 params->loopback_mode, phy->req_line_speed); 4661 4662 if (phy->req_line_speed < SPEED_10000 || 4663 phy->supported & SUPPORTED_20000baseKR2_Full) { 4664 /* 10/100/1000/20G-KR2 */ 4665 4666 /* Update those 1-copy registers */ 4667 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, 4668 MDIO_AER_BLOCK_AER_REG, 0); 4669 /* Enable 1G MDIO (1-copy) */ 4670 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 4671 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, 4672 0x10); 4673 /* Set 1G loopback based on lane (1-copy) */ 4674 lane = bnx2x_get_warpcore_lane(phy, params); 4675 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 4676 MDIO_WC_REG_XGXSBLK1_LANECTRL2, &val16); 4677 val16 |= (1<<lane); 4678 if (phy->flags & FLAGS_WC_DUAL_MODE) 4679 val16 |= (2<<lane); 4680 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4681 MDIO_WC_REG_XGXSBLK1_LANECTRL2, 4682 val16); 4683 4684 /* Switch back to 4-copy registers */ 4685 bnx2x_set_aer_mmd(params, phy); 4686 } else { 4687 /* 10G / 20G-DXGXS */ 4688 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 4689 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 4690 0x4000); 4691 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 4692 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1); 4693 } 4694 } 4695 4696 4697 4698 static void bnx2x_sync_link(struct link_params *params, 4699 struct link_vars *vars) 4700 { 4701 struct bnx2x *bp = params->bp; 4702 u8 link_10g_plus; 4703 if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG) 4704 vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG; 4705 vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP); 4706 if (vars->link_up) { 4707 DP(NETIF_MSG_LINK, "phy link up\n"); 4708 4709 vars->phy_link_up = 1; 4710 vars->duplex = DUPLEX_FULL; 4711 switch (vars->link_status & 4712 LINK_STATUS_SPEED_AND_DUPLEX_MASK) { 4713 case LINK_10THD: 4714 vars->duplex = DUPLEX_HALF; 4715 fallthrough; 4716 case LINK_10TFD: 4717 vars->line_speed = SPEED_10; 4718 break; 4719 4720 case LINK_100TXHD: 4721 vars->duplex = DUPLEX_HALF; 4722 fallthrough; 4723 case LINK_100T4: 4724 case LINK_100TXFD: 4725 vars->line_speed = SPEED_100; 4726 break; 4727 4728 case LINK_1000THD: 4729 vars->duplex = DUPLEX_HALF; 4730 fallthrough; 4731 case LINK_1000TFD: 4732 vars->line_speed = SPEED_1000; 4733 break; 4734 4735 case LINK_2500THD: 4736 vars->duplex = DUPLEX_HALF; 4737 fallthrough; 4738 case LINK_2500TFD: 4739 vars->line_speed = SPEED_2500; 4740 break; 4741 4742 case LINK_10GTFD: 4743 vars->line_speed = SPEED_10000; 4744 break; 4745 case LINK_20GTFD: 4746 vars->line_speed = SPEED_20000; 4747 break; 4748 default: 4749 break; 4750 } 4751 vars->flow_ctrl = 0; 4752 if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED) 4753 vars->flow_ctrl |= BNX2X_FLOW_CTRL_TX; 4754 4755 if (vars->link_status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED) 4756 vars->flow_ctrl |= BNX2X_FLOW_CTRL_RX; 4757 4758 if (!vars->flow_ctrl) 4759 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; 4760 4761 if (vars->line_speed && 4762 ((vars->line_speed == SPEED_10) || 4763 (vars->line_speed == SPEED_100))) { 4764 vars->phy_flags |= PHY_SGMII_FLAG; 4765 } else { 4766 vars->phy_flags &= ~PHY_SGMII_FLAG; 4767 } 4768 if (vars->line_speed && 4769 USES_WARPCORE(bp) && 4770 (vars->line_speed == SPEED_1000)) 4771 vars->phy_flags |= PHY_SGMII_FLAG; 4772 /* Anything 10 and over uses the bmac */ 4773 link_10g_plus = (vars->line_speed >= SPEED_10000); 4774 4775 if (link_10g_plus) { 4776 if (USES_WARPCORE(bp)) 4777 vars->mac_type = MAC_TYPE_XMAC; 4778 else 4779 vars->mac_type = MAC_TYPE_BMAC; 4780 } else { 4781 if (USES_WARPCORE(bp)) 4782 vars->mac_type = MAC_TYPE_UMAC; 4783 else 4784 vars->mac_type = MAC_TYPE_EMAC; 4785 } 4786 } else { /* Link down */ 4787 DP(NETIF_MSG_LINK, "phy link down\n"); 4788 4789 vars->phy_link_up = 0; 4790 4791 vars->line_speed = 0; 4792 vars->duplex = DUPLEX_FULL; 4793 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; 4794 4795 /* Indicate no mac active */ 4796 vars->mac_type = MAC_TYPE_NONE; 4797 if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG) 4798 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG; 4799 if (vars->link_status & LINK_STATUS_SFP_TX_FAULT) 4800 vars->phy_flags |= PHY_SFP_TX_FAULT_FLAG; 4801 } 4802 } 4803 4804 void bnx2x_link_status_update(struct link_params *params, 4805 struct link_vars *vars) 4806 { 4807 struct bnx2x *bp = params->bp; 4808 u8 port = params->port; 4809 u32 sync_offset, media_types; 4810 /* Update PHY configuration */ 4811 set_phy_vars(params, vars); 4812 4813 vars->link_status = REG_RD(bp, params->shmem_base + 4814 offsetof(struct shmem_region, 4815 port_mb[port].link_status)); 4816 4817 /* Force link UP in non LOOPBACK_EXT loopback mode(s) */ 4818 if (params->loopback_mode != LOOPBACK_NONE && 4819 params->loopback_mode != LOOPBACK_EXT) 4820 vars->link_status |= LINK_STATUS_LINK_UP; 4821 4822 if (bnx2x_eee_has_cap(params)) 4823 vars->eee_status = REG_RD(bp, params->shmem2_base + 4824 offsetof(struct shmem2_region, 4825 eee_status[params->port])); 4826 4827 vars->phy_flags = PHY_XGXS_FLAG; 4828 bnx2x_sync_link(params, vars); 4829 /* Sync media type */ 4830 sync_offset = params->shmem_base + 4831 offsetof(struct shmem_region, 4832 dev_info.port_hw_config[port].media_type); 4833 media_types = REG_RD(bp, sync_offset); 4834 4835 params->phy[INT_PHY].media_type = 4836 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) >> 4837 PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT; 4838 params->phy[EXT_PHY1].media_type = 4839 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK) >> 4840 PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT; 4841 params->phy[EXT_PHY2].media_type = 4842 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK) >> 4843 PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT; 4844 DP(NETIF_MSG_LINK, "media_types = 0x%x\n", media_types); 4845 4846 /* Sync AEU offset */ 4847 sync_offset = params->shmem_base + 4848 offsetof(struct shmem_region, 4849 dev_info.port_hw_config[port].aeu_int_mask); 4850 4851 vars->aeu_int_mask = REG_RD(bp, sync_offset); 4852 4853 /* Sync PFC status */ 4854 if (vars->link_status & LINK_STATUS_PFC_ENABLED) 4855 params->feature_config_flags |= 4856 FEATURE_CONFIG_PFC_ENABLED; 4857 else 4858 params->feature_config_flags &= 4859 ~FEATURE_CONFIG_PFC_ENABLED; 4860 4861 if (SHMEM2_HAS(bp, link_attr_sync)) 4862 params->link_attr_sync = SHMEM2_RD(bp, 4863 link_attr_sync[params->port]); 4864 4865 DP(NETIF_MSG_LINK, "link_status 0x%x phy_link_up %x int_mask 0x%x\n", 4866 vars->link_status, vars->phy_link_up, vars->aeu_int_mask); 4867 DP(NETIF_MSG_LINK, "line_speed %x duplex %x flow_ctrl 0x%x\n", 4868 vars->line_speed, vars->duplex, vars->flow_ctrl); 4869 } 4870 4871 static void bnx2x_set_master_ln(struct link_params *params, 4872 struct bnx2x_phy *phy) 4873 { 4874 struct bnx2x *bp = params->bp; 4875 u16 new_master_ln, ser_lane; 4876 ser_lane = ((params->lane_config & 4877 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >> 4878 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT); 4879 4880 /* Set the master_ln for AN */ 4881 CL22_RD_OVER_CL45(bp, phy, 4882 MDIO_REG_BANK_XGXS_BLOCK2, 4883 MDIO_XGXS_BLOCK2_TEST_MODE_LANE, 4884 &new_master_ln); 4885 4886 CL22_WR_OVER_CL45(bp, phy, 4887 MDIO_REG_BANK_XGXS_BLOCK2 , 4888 MDIO_XGXS_BLOCK2_TEST_MODE_LANE, 4889 (new_master_ln | ser_lane)); 4890 } 4891 4892 static int bnx2x_reset_unicore(struct link_params *params, 4893 struct bnx2x_phy *phy, 4894 u8 set_serdes) 4895 { 4896 struct bnx2x *bp = params->bp; 4897 u16 mii_control; 4898 u16 i; 4899 CL22_RD_OVER_CL45(bp, phy, 4900 MDIO_REG_BANK_COMBO_IEEE0, 4901 MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control); 4902 4903 /* Reset the unicore */ 4904 CL22_WR_OVER_CL45(bp, phy, 4905 MDIO_REG_BANK_COMBO_IEEE0, 4906 MDIO_COMBO_IEEE0_MII_CONTROL, 4907 (mii_control | 4908 MDIO_COMBO_IEEO_MII_CONTROL_RESET)); 4909 if (set_serdes) 4910 bnx2x_set_serdes_access(bp, params->port); 4911 4912 /* Wait for the reset to self clear */ 4913 for (i = 0; i < MDIO_ACCESS_TIMEOUT; i++) { 4914 udelay(5); 4915 4916 /* The reset erased the previous bank value */ 4917 CL22_RD_OVER_CL45(bp, phy, 4918 MDIO_REG_BANK_COMBO_IEEE0, 4919 MDIO_COMBO_IEEE0_MII_CONTROL, 4920 &mii_control); 4921 4922 if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) { 4923 udelay(5); 4924 return 0; 4925 } 4926 } 4927 4928 netdev_err(bp->dev, "Warning: PHY was not initialized," 4929 " Port %d\n", 4930 params->port); 4931 DP(NETIF_MSG_LINK, "BUG! XGXS is still in reset!\n"); 4932 return -EINVAL; 4933 4934 } 4935 4936 static void bnx2x_set_swap_lanes(struct link_params *params, 4937 struct bnx2x_phy *phy) 4938 { 4939 struct bnx2x *bp = params->bp; 4940 /* Each two bits represents a lane number: 4941 * No swap is 0123 => 0x1b no need to enable the swap 4942 */ 4943 u16 rx_lane_swap, tx_lane_swap; 4944 4945 rx_lane_swap = ((params->lane_config & 4946 PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >> 4947 PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT); 4948 tx_lane_swap = ((params->lane_config & 4949 PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >> 4950 PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT); 4951 4952 if (rx_lane_swap != 0x1b) { 4953 CL22_WR_OVER_CL45(bp, phy, 4954 MDIO_REG_BANK_XGXS_BLOCK2, 4955 MDIO_XGXS_BLOCK2_RX_LN_SWAP, 4956 (rx_lane_swap | 4957 MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE | 4958 MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE)); 4959 } else { 4960 CL22_WR_OVER_CL45(bp, phy, 4961 MDIO_REG_BANK_XGXS_BLOCK2, 4962 MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0); 4963 } 4964 4965 if (tx_lane_swap != 0x1b) { 4966 CL22_WR_OVER_CL45(bp, phy, 4967 MDIO_REG_BANK_XGXS_BLOCK2, 4968 MDIO_XGXS_BLOCK2_TX_LN_SWAP, 4969 (tx_lane_swap | 4970 MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE)); 4971 } else { 4972 CL22_WR_OVER_CL45(bp, phy, 4973 MDIO_REG_BANK_XGXS_BLOCK2, 4974 MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0); 4975 } 4976 } 4977 4978 static void bnx2x_set_parallel_detection(struct bnx2x_phy *phy, 4979 struct link_params *params) 4980 { 4981 struct bnx2x *bp = params->bp; 4982 u16 control2; 4983 CL22_RD_OVER_CL45(bp, phy, 4984 MDIO_REG_BANK_SERDES_DIGITAL, 4985 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2, 4986 &control2); 4987 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) 4988 control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN; 4989 else 4990 control2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN; 4991 DP(NETIF_MSG_LINK, "phy->speed_cap_mask = 0x%x, control2 = 0x%x\n", 4992 phy->speed_cap_mask, control2); 4993 CL22_WR_OVER_CL45(bp, phy, 4994 MDIO_REG_BANK_SERDES_DIGITAL, 4995 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2, 4996 control2); 4997 4998 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) && 4999 (phy->speed_cap_mask & 5000 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) { 5001 DP(NETIF_MSG_LINK, "XGXS\n"); 5002 5003 CL22_WR_OVER_CL45(bp, phy, 5004 MDIO_REG_BANK_10G_PARALLEL_DETECT, 5005 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK, 5006 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT); 5007 5008 CL22_RD_OVER_CL45(bp, phy, 5009 MDIO_REG_BANK_10G_PARALLEL_DETECT, 5010 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL, 5011 &control2); 5012 5013 5014 control2 |= 5015 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN; 5016 5017 CL22_WR_OVER_CL45(bp, phy, 5018 MDIO_REG_BANK_10G_PARALLEL_DETECT, 5019 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL, 5020 control2); 5021 5022 /* Disable parallel detection of HiG */ 5023 CL22_WR_OVER_CL45(bp, phy, 5024 MDIO_REG_BANK_XGXS_BLOCK2, 5025 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G, 5026 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS | 5027 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS); 5028 } 5029 } 5030 5031 static void bnx2x_set_autoneg(struct bnx2x_phy *phy, 5032 struct link_params *params, 5033 struct link_vars *vars, 5034 u8 enable_cl73) 5035 { 5036 struct bnx2x *bp = params->bp; 5037 u16 reg_val; 5038 5039 /* CL37 Autoneg */ 5040 CL22_RD_OVER_CL45(bp, phy, 5041 MDIO_REG_BANK_COMBO_IEEE0, 5042 MDIO_COMBO_IEEE0_MII_CONTROL, ®_val); 5043 5044 /* CL37 Autoneg Enabled */ 5045 if (vars->line_speed == SPEED_AUTO_NEG) 5046 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN; 5047 else /* CL37 Autoneg Disabled */ 5048 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN | 5049 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN); 5050 5051 CL22_WR_OVER_CL45(bp, phy, 5052 MDIO_REG_BANK_COMBO_IEEE0, 5053 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val); 5054 5055 /* Enable/Disable Autodetection */ 5056 5057 CL22_RD_OVER_CL45(bp, phy, 5058 MDIO_REG_BANK_SERDES_DIGITAL, 5059 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, ®_val); 5060 reg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN | 5061 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT); 5062 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE; 5063 if (vars->line_speed == SPEED_AUTO_NEG) 5064 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET; 5065 else 5066 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET; 5067 5068 CL22_WR_OVER_CL45(bp, phy, 5069 MDIO_REG_BANK_SERDES_DIGITAL, 5070 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val); 5071 5072 /* Enable TetonII and BAM autoneg */ 5073 CL22_RD_OVER_CL45(bp, phy, 5074 MDIO_REG_BANK_BAM_NEXT_PAGE, 5075 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL, 5076 ®_val); 5077 if (vars->line_speed == SPEED_AUTO_NEG) { 5078 /* Enable BAM aneg Mode and TetonII aneg Mode */ 5079 reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE | 5080 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN); 5081 } else { 5082 /* TetonII and BAM Autoneg Disabled */ 5083 reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE | 5084 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN); 5085 } 5086 CL22_WR_OVER_CL45(bp, phy, 5087 MDIO_REG_BANK_BAM_NEXT_PAGE, 5088 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL, 5089 reg_val); 5090 5091 if (enable_cl73) { 5092 /* Enable Cl73 FSM status bits */ 5093 CL22_WR_OVER_CL45(bp, phy, 5094 MDIO_REG_BANK_CL73_USERB0, 5095 MDIO_CL73_USERB0_CL73_UCTRL, 5096 0xe); 5097 5098 /* Enable BAM Station Manager*/ 5099 CL22_WR_OVER_CL45(bp, phy, 5100 MDIO_REG_BANK_CL73_USERB0, 5101 MDIO_CL73_USERB0_CL73_BAM_CTRL1, 5102 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN | 5103 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN | 5104 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN); 5105 5106 /* Advertise CL73 link speeds */ 5107 CL22_RD_OVER_CL45(bp, phy, 5108 MDIO_REG_BANK_CL73_IEEEB1, 5109 MDIO_CL73_IEEEB1_AN_ADV2, 5110 ®_val); 5111 if (phy->speed_cap_mask & 5112 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) 5113 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4; 5114 if (phy->speed_cap_mask & 5115 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) 5116 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX; 5117 5118 CL22_WR_OVER_CL45(bp, phy, 5119 MDIO_REG_BANK_CL73_IEEEB1, 5120 MDIO_CL73_IEEEB1_AN_ADV2, 5121 reg_val); 5122 5123 /* CL73 Autoneg Enabled */ 5124 reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN; 5125 5126 } else /* CL73 Autoneg Disabled */ 5127 reg_val = 0; 5128 5129 CL22_WR_OVER_CL45(bp, phy, 5130 MDIO_REG_BANK_CL73_IEEEB0, 5131 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val); 5132 } 5133 5134 /* Program SerDes, forced speed */ 5135 static void bnx2x_program_serdes(struct bnx2x_phy *phy, 5136 struct link_params *params, 5137 struct link_vars *vars) 5138 { 5139 struct bnx2x *bp = params->bp; 5140 u16 reg_val; 5141 5142 /* Program duplex, disable autoneg and sgmii*/ 5143 CL22_RD_OVER_CL45(bp, phy, 5144 MDIO_REG_BANK_COMBO_IEEE0, 5145 MDIO_COMBO_IEEE0_MII_CONTROL, ®_val); 5146 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX | 5147 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN | 5148 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK); 5149 if (phy->req_duplex == DUPLEX_FULL) 5150 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX; 5151 CL22_WR_OVER_CL45(bp, phy, 5152 MDIO_REG_BANK_COMBO_IEEE0, 5153 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val); 5154 5155 /* Program speed 5156 * - needed only if the speed is greater than 1G (2.5G or 10G) 5157 */ 5158 CL22_RD_OVER_CL45(bp, phy, 5159 MDIO_REG_BANK_SERDES_DIGITAL, 5160 MDIO_SERDES_DIGITAL_MISC1, ®_val); 5161 /* Clearing the speed value before setting the right speed */ 5162 DP(NETIF_MSG_LINK, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val); 5163 5164 reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK | 5165 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL); 5166 5167 if (!((vars->line_speed == SPEED_1000) || 5168 (vars->line_speed == SPEED_100) || 5169 (vars->line_speed == SPEED_10))) { 5170 5171 reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M | 5172 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL); 5173 if (vars->line_speed == SPEED_10000) 5174 reg_val |= 5175 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4; 5176 } 5177 5178 CL22_WR_OVER_CL45(bp, phy, 5179 MDIO_REG_BANK_SERDES_DIGITAL, 5180 MDIO_SERDES_DIGITAL_MISC1, reg_val); 5181 5182 } 5183 5184 static void bnx2x_set_brcm_cl37_advertisement(struct bnx2x_phy *phy, 5185 struct link_params *params) 5186 { 5187 struct bnx2x *bp = params->bp; 5188 u16 val = 0; 5189 5190 /* Set extended capabilities */ 5191 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) 5192 val |= MDIO_OVER_1G_UP1_2_5G; 5193 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) 5194 val |= MDIO_OVER_1G_UP1_10G; 5195 CL22_WR_OVER_CL45(bp, phy, 5196 MDIO_REG_BANK_OVER_1G, 5197 MDIO_OVER_1G_UP1, val); 5198 5199 CL22_WR_OVER_CL45(bp, phy, 5200 MDIO_REG_BANK_OVER_1G, 5201 MDIO_OVER_1G_UP3, 0x400); 5202 } 5203 5204 static void bnx2x_set_ieee_aneg_advertisement(struct bnx2x_phy *phy, 5205 struct link_params *params, 5206 u16 ieee_fc) 5207 { 5208 struct bnx2x *bp = params->bp; 5209 u16 val; 5210 /* For AN, we are always publishing full duplex */ 5211 5212 CL22_WR_OVER_CL45(bp, phy, 5213 MDIO_REG_BANK_COMBO_IEEE0, 5214 MDIO_COMBO_IEEE0_AUTO_NEG_ADV, ieee_fc); 5215 CL22_RD_OVER_CL45(bp, phy, 5216 MDIO_REG_BANK_CL73_IEEEB1, 5217 MDIO_CL73_IEEEB1_AN_ADV1, &val); 5218 val &= ~MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH; 5219 val |= ((ieee_fc<<3) & MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK); 5220 CL22_WR_OVER_CL45(bp, phy, 5221 MDIO_REG_BANK_CL73_IEEEB1, 5222 MDIO_CL73_IEEEB1_AN_ADV1, val); 5223 } 5224 5225 static void bnx2x_restart_autoneg(struct bnx2x_phy *phy, 5226 struct link_params *params, 5227 u8 enable_cl73) 5228 { 5229 struct bnx2x *bp = params->bp; 5230 u16 mii_control; 5231 5232 DP(NETIF_MSG_LINK, "bnx2x_restart_autoneg\n"); 5233 /* Enable and restart BAM/CL37 aneg */ 5234 5235 if (enable_cl73) { 5236 CL22_RD_OVER_CL45(bp, phy, 5237 MDIO_REG_BANK_CL73_IEEEB0, 5238 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, 5239 &mii_control); 5240 5241 CL22_WR_OVER_CL45(bp, phy, 5242 MDIO_REG_BANK_CL73_IEEEB0, 5243 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, 5244 (mii_control | 5245 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN | 5246 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN)); 5247 } else { 5248 5249 CL22_RD_OVER_CL45(bp, phy, 5250 MDIO_REG_BANK_COMBO_IEEE0, 5251 MDIO_COMBO_IEEE0_MII_CONTROL, 5252 &mii_control); 5253 DP(NETIF_MSG_LINK, 5254 "bnx2x_restart_autoneg mii_control before = 0x%x\n", 5255 mii_control); 5256 CL22_WR_OVER_CL45(bp, phy, 5257 MDIO_REG_BANK_COMBO_IEEE0, 5258 MDIO_COMBO_IEEE0_MII_CONTROL, 5259 (mii_control | 5260 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN | 5261 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN)); 5262 } 5263 } 5264 5265 static void bnx2x_initialize_sgmii_process(struct bnx2x_phy *phy, 5266 struct link_params *params, 5267 struct link_vars *vars) 5268 { 5269 struct bnx2x *bp = params->bp; 5270 u16 control1; 5271 5272 /* In SGMII mode, the unicore is always slave */ 5273 5274 CL22_RD_OVER_CL45(bp, phy, 5275 MDIO_REG_BANK_SERDES_DIGITAL, 5276 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, 5277 &control1); 5278 control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT; 5279 /* Set sgmii mode (and not fiber) */ 5280 control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE | 5281 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET | 5282 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE); 5283 CL22_WR_OVER_CL45(bp, phy, 5284 MDIO_REG_BANK_SERDES_DIGITAL, 5285 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, 5286 control1); 5287 5288 /* If forced speed */ 5289 if (!(vars->line_speed == SPEED_AUTO_NEG)) { 5290 /* Set speed, disable autoneg */ 5291 u16 mii_control; 5292 5293 CL22_RD_OVER_CL45(bp, phy, 5294 MDIO_REG_BANK_COMBO_IEEE0, 5295 MDIO_COMBO_IEEE0_MII_CONTROL, 5296 &mii_control); 5297 mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN | 5298 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK| 5299 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX); 5300 5301 switch (vars->line_speed) { 5302 case SPEED_100: 5303 mii_control |= 5304 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100; 5305 break; 5306 case SPEED_1000: 5307 mii_control |= 5308 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000; 5309 break; 5310 case SPEED_10: 5311 /* There is nothing to set for 10M */ 5312 break; 5313 default: 5314 /* Invalid speed for SGMII */ 5315 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n", 5316 vars->line_speed); 5317 break; 5318 } 5319 5320 /* Setting the full duplex */ 5321 if (phy->req_duplex == DUPLEX_FULL) 5322 mii_control |= 5323 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX; 5324 CL22_WR_OVER_CL45(bp, phy, 5325 MDIO_REG_BANK_COMBO_IEEE0, 5326 MDIO_COMBO_IEEE0_MII_CONTROL, 5327 mii_control); 5328 5329 } else { /* AN mode */ 5330 /* Enable and restart AN */ 5331 bnx2x_restart_autoneg(phy, params, 0); 5332 } 5333 } 5334 5335 /* Link management 5336 */ 5337 static int bnx2x_direct_parallel_detect_used(struct bnx2x_phy *phy, 5338 struct link_params *params) 5339 { 5340 struct bnx2x *bp = params->bp; 5341 u16 pd_10g, status2_1000x; 5342 if (phy->req_line_speed != SPEED_AUTO_NEG) 5343 return 0; 5344 CL22_RD_OVER_CL45(bp, phy, 5345 MDIO_REG_BANK_SERDES_DIGITAL, 5346 MDIO_SERDES_DIGITAL_A_1000X_STATUS2, 5347 &status2_1000x); 5348 CL22_RD_OVER_CL45(bp, phy, 5349 MDIO_REG_BANK_SERDES_DIGITAL, 5350 MDIO_SERDES_DIGITAL_A_1000X_STATUS2, 5351 &status2_1000x); 5352 if (status2_1000x & MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED) { 5353 DP(NETIF_MSG_LINK, "1G parallel detect link on port %d\n", 5354 params->port); 5355 return 1; 5356 } 5357 5358 CL22_RD_OVER_CL45(bp, phy, 5359 MDIO_REG_BANK_10G_PARALLEL_DETECT, 5360 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS, 5361 &pd_10g); 5362 5363 if (pd_10g & MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK) { 5364 DP(NETIF_MSG_LINK, "10G parallel detect link on port %d\n", 5365 params->port); 5366 return 1; 5367 } 5368 return 0; 5369 } 5370 5371 static void bnx2x_update_adv_fc(struct bnx2x_phy *phy, 5372 struct link_params *params, 5373 struct link_vars *vars, 5374 u32 gp_status) 5375 { 5376 u16 ld_pause; /* local driver */ 5377 u16 lp_pause; /* link partner */ 5378 u16 pause_result; 5379 struct bnx2x *bp = params->bp; 5380 if ((gp_status & 5381 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | 5382 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) == 5383 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | 5384 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) { 5385 5386 CL22_RD_OVER_CL45(bp, phy, 5387 MDIO_REG_BANK_CL73_IEEEB1, 5388 MDIO_CL73_IEEEB1_AN_ADV1, 5389 &ld_pause); 5390 CL22_RD_OVER_CL45(bp, phy, 5391 MDIO_REG_BANK_CL73_IEEEB1, 5392 MDIO_CL73_IEEEB1_AN_LP_ADV1, 5393 &lp_pause); 5394 pause_result = (ld_pause & 5395 MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK) >> 8; 5396 pause_result |= (lp_pause & 5397 MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK) >> 10; 5398 DP(NETIF_MSG_LINK, "pause_result CL73 0x%x\n", pause_result); 5399 } else { 5400 CL22_RD_OVER_CL45(bp, phy, 5401 MDIO_REG_BANK_COMBO_IEEE0, 5402 MDIO_COMBO_IEEE0_AUTO_NEG_ADV, 5403 &ld_pause); 5404 CL22_RD_OVER_CL45(bp, phy, 5405 MDIO_REG_BANK_COMBO_IEEE0, 5406 MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1, 5407 &lp_pause); 5408 pause_result = (ld_pause & 5409 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>5; 5410 pause_result |= (lp_pause & 5411 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7; 5412 DP(NETIF_MSG_LINK, "pause_result CL37 0x%x\n", pause_result); 5413 } 5414 bnx2x_pause_resolve(phy, params, vars, pause_result); 5415 5416 } 5417 5418 static void bnx2x_flow_ctrl_resolve(struct bnx2x_phy *phy, 5419 struct link_params *params, 5420 struct link_vars *vars, 5421 u32 gp_status) 5422 { 5423 struct bnx2x *bp = params->bp; 5424 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; 5425 5426 /* Resolve from gp_status in case of AN complete and not sgmii */ 5427 if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO) { 5428 /* Update the advertised flow-controled of LD/LP in AN */ 5429 if (phy->req_line_speed == SPEED_AUTO_NEG) 5430 bnx2x_update_adv_fc(phy, params, vars, gp_status); 5431 /* But set the flow-control result as the requested one */ 5432 vars->flow_ctrl = phy->req_flow_ctrl; 5433 } else if (phy->req_line_speed != SPEED_AUTO_NEG) 5434 vars->flow_ctrl = params->req_fc_auto_adv; 5435 else if ((gp_status & MDIO_AN_CL73_OR_37_COMPLETE) && 5436 (!(vars->phy_flags & PHY_SGMII_FLAG))) { 5437 if (bnx2x_direct_parallel_detect_used(phy, params)) { 5438 vars->flow_ctrl = params->req_fc_auto_adv; 5439 return; 5440 } 5441 bnx2x_update_adv_fc(phy, params, vars, gp_status); 5442 } 5443 DP(NETIF_MSG_LINK, "flow_ctrl 0x%x\n", vars->flow_ctrl); 5444 } 5445 5446 static void bnx2x_check_fallback_to_cl37(struct bnx2x_phy *phy, 5447 struct link_params *params) 5448 { 5449 struct bnx2x *bp = params->bp; 5450 u16 rx_status, ustat_val, cl37_fsm_received; 5451 DP(NETIF_MSG_LINK, "bnx2x_check_fallback_to_cl37\n"); 5452 /* Step 1: Make sure signal is detected */ 5453 CL22_RD_OVER_CL45(bp, phy, 5454 MDIO_REG_BANK_RX0, 5455 MDIO_RX0_RX_STATUS, 5456 &rx_status); 5457 if ((rx_status & MDIO_RX0_RX_STATUS_SIGDET) != 5458 (MDIO_RX0_RX_STATUS_SIGDET)) { 5459 DP(NETIF_MSG_LINK, "Signal is not detected. Restoring CL73." 5460 "rx_status(0x80b0) = 0x%x\n", rx_status); 5461 CL22_WR_OVER_CL45(bp, phy, 5462 MDIO_REG_BANK_CL73_IEEEB0, 5463 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, 5464 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN); 5465 return; 5466 } 5467 /* Step 2: Check CL73 state machine */ 5468 CL22_RD_OVER_CL45(bp, phy, 5469 MDIO_REG_BANK_CL73_USERB0, 5470 MDIO_CL73_USERB0_CL73_USTAT1, 5471 &ustat_val); 5472 if ((ustat_val & 5473 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK | 5474 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) != 5475 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK | 5476 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) { 5477 DP(NETIF_MSG_LINK, "CL73 state-machine is not stable. " 5478 "ustat_val(0x8371) = 0x%x\n", ustat_val); 5479 return; 5480 } 5481 /* Step 3: Check CL37 Message Pages received to indicate LP 5482 * supports only CL37 5483 */ 5484 CL22_RD_OVER_CL45(bp, phy, 5485 MDIO_REG_BANK_REMOTE_PHY, 5486 MDIO_REMOTE_PHY_MISC_RX_STATUS, 5487 &cl37_fsm_received); 5488 if ((cl37_fsm_received & 5489 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG | 5490 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) != 5491 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG | 5492 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) { 5493 DP(NETIF_MSG_LINK, "No CL37 FSM were received. " 5494 "misc_rx_status(0x8330) = 0x%x\n", 5495 cl37_fsm_received); 5496 return; 5497 } 5498 /* The combined cl37/cl73 fsm state information indicating that 5499 * we are connected to a device which does not support cl73, but 5500 * does support cl37 BAM. In this case we disable cl73 and 5501 * restart cl37 auto-neg 5502 */ 5503 5504 /* Disable CL73 */ 5505 CL22_WR_OVER_CL45(bp, phy, 5506 MDIO_REG_BANK_CL73_IEEEB0, 5507 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, 5508 0); 5509 /* Restart CL37 autoneg */ 5510 bnx2x_restart_autoneg(phy, params, 0); 5511 DP(NETIF_MSG_LINK, "Disabling CL73, and restarting CL37 autoneg\n"); 5512 } 5513 5514 static void bnx2x_xgxs_an_resolve(struct bnx2x_phy *phy, 5515 struct link_params *params, 5516 struct link_vars *vars, 5517 u32 gp_status) 5518 { 5519 if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE) 5520 vars->link_status |= 5521 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; 5522 5523 if (bnx2x_direct_parallel_detect_used(phy, params)) 5524 vars->link_status |= 5525 LINK_STATUS_PARALLEL_DETECTION_USED; 5526 } 5527 static int bnx2x_get_link_speed_duplex(struct bnx2x_phy *phy, 5528 struct link_params *params, 5529 struct link_vars *vars, 5530 u16 is_link_up, 5531 u16 speed_mask, 5532 u16 is_duplex) 5533 { 5534 struct bnx2x *bp = params->bp; 5535 if (phy->req_line_speed == SPEED_AUTO_NEG) 5536 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED; 5537 if (is_link_up) { 5538 DP(NETIF_MSG_LINK, "phy link up\n"); 5539 5540 vars->phy_link_up = 1; 5541 vars->link_status |= LINK_STATUS_LINK_UP; 5542 5543 switch (speed_mask) { 5544 case GP_STATUS_10M: 5545 vars->line_speed = SPEED_10; 5546 if (is_duplex == DUPLEX_FULL) 5547 vars->link_status |= LINK_10TFD; 5548 else 5549 vars->link_status |= LINK_10THD; 5550 break; 5551 5552 case GP_STATUS_100M: 5553 vars->line_speed = SPEED_100; 5554 if (is_duplex == DUPLEX_FULL) 5555 vars->link_status |= LINK_100TXFD; 5556 else 5557 vars->link_status |= LINK_100TXHD; 5558 break; 5559 5560 case GP_STATUS_1G: 5561 case GP_STATUS_1G_KX: 5562 vars->line_speed = SPEED_1000; 5563 if (is_duplex == DUPLEX_FULL) 5564 vars->link_status |= LINK_1000TFD; 5565 else 5566 vars->link_status |= LINK_1000THD; 5567 break; 5568 5569 case GP_STATUS_2_5G: 5570 vars->line_speed = SPEED_2500; 5571 if (is_duplex == DUPLEX_FULL) 5572 vars->link_status |= LINK_2500TFD; 5573 else 5574 vars->link_status |= LINK_2500THD; 5575 break; 5576 5577 case GP_STATUS_5G: 5578 case GP_STATUS_6G: 5579 DP(NETIF_MSG_LINK, 5580 "link speed unsupported gp_status 0x%x\n", 5581 speed_mask); 5582 return -EINVAL; 5583 5584 case GP_STATUS_10G_KX4: 5585 case GP_STATUS_10G_HIG: 5586 case GP_STATUS_10G_CX4: 5587 case GP_STATUS_10G_KR: 5588 case GP_STATUS_10G_SFI: 5589 case GP_STATUS_10G_XFI: 5590 vars->line_speed = SPEED_10000; 5591 vars->link_status |= LINK_10GTFD; 5592 break; 5593 case GP_STATUS_20G_DXGXS: 5594 case GP_STATUS_20G_KR2: 5595 vars->line_speed = SPEED_20000; 5596 vars->link_status |= LINK_20GTFD; 5597 break; 5598 default: 5599 DP(NETIF_MSG_LINK, 5600 "link speed unsupported gp_status 0x%x\n", 5601 speed_mask); 5602 return -EINVAL; 5603 } 5604 } else { /* link_down */ 5605 DP(NETIF_MSG_LINK, "phy link down\n"); 5606 5607 vars->phy_link_up = 0; 5608 5609 vars->duplex = DUPLEX_FULL; 5610 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; 5611 vars->mac_type = MAC_TYPE_NONE; 5612 } 5613 DP(NETIF_MSG_LINK, " phy_link_up %x line_speed %d\n", 5614 vars->phy_link_up, vars->line_speed); 5615 return 0; 5616 } 5617 5618 static u8 bnx2x_link_settings_status(struct bnx2x_phy *phy, 5619 struct link_params *params, 5620 struct link_vars *vars) 5621 { 5622 struct bnx2x *bp = params->bp; 5623 5624 u16 gp_status, duplex = DUPLEX_HALF, link_up = 0, speed_mask; 5625 int rc = 0; 5626 5627 /* Read gp_status */ 5628 CL22_RD_OVER_CL45(bp, phy, 5629 MDIO_REG_BANK_GP_STATUS, 5630 MDIO_GP_STATUS_TOP_AN_STATUS1, 5631 &gp_status); 5632 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS) 5633 duplex = DUPLEX_FULL; 5634 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) 5635 link_up = 1; 5636 speed_mask = gp_status & GP_STATUS_SPEED_MASK; 5637 DP(NETIF_MSG_LINK, "gp_status 0x%x, is_link_up %d, speed_mask 0x%x\n", 5638 gp_status, link_up, speed_mask); 5639 rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, speed_mask, 5640 duplex); 5641 if (rc == -EINVAL) 5642 return rc; 5643 5644 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) { 5645 if (SINGLE_MEDIA_DIRECT(params)) { 5646 vars->duplex = duplex; 5647 bnx2x_flow_ctrl_resolve(phy, params, vars, gp_status); 5648 if (phy->req_line_speed == SPEED_AUTO_NEG) 5649 bnx2x_xgxs_an_resolve(phy, params, vars, 5650 gp_status); 5651 } 5652 } else { /* Link_down */ 5653 if ((phy->req_line_speed == SPEED_AUTO_NEG) && 5654 SINGLE_MEDIA_DIRECT(params)) { 5655 /* Check signal is detected */ 5656 bnx2x_check_fallback_to_cl37(phy, params); 5657 } 5658 } 5659 5660 /* Read LP advertised speeds*/ 5661 if (SINGLE_MEDIA_DIRECT(params) && 5662 (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)) { 5663 u16 val; 5664 5665 CL22_RD_OVER_CL45(bp, phy, MDIO_REG_BANK_CL73_IEEEB1, 5666 MDIO_CL73_IEEEB1_AN_LP_ADV2, &val); 5667 5668 if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX) 5669 vars->link_status |= 5670 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; 5671 if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 | 5672 MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR)) 5673 vars->link_status |= 5674 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; 5675 5676 CL22_RD_OVER_CL45(bp, phy, MDIO_REG_BANK_OVER_1G, 5677 MDIO_OVER_1G_LP_UP1, &val); 5678 5679 if (val & MDIO_OVER_1G_UP1_2_5G) 5680 vars->link_status |= 5681 LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE; 5682 if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH)) 5683 vars->link_status |= 5684 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; 5685 } 5686 5687 DP(NETIF_MSG_LINK, "duplex %x flow_ctrl 0x%x link_status 0x%x\n", 5688 vars->duplex, vars->flow_ctrl, vars->link_status); 5689 return rc; 5690 } 5691 5692 static u8 bnx2x_warpcore_read_status(struct bnx2x_phy *phy, 5693 struct link_params *params, 5694 struct link_vars *vars) 5695 { 5696 struct bnx2x *bp = params->bp; 5697 u8 lane; 5698 u16 gp_status1, gp_speed, link_up, duplex = DUPLEX_FULL; 5699 int rc = 0; 5700 lane = bnx2x_get_warpcore_lane(phy, params); 5701 /* Read gp_status */ 5702 if ((params->loopback_mode) && 5703 (phy->flags & FLAGS_WC_DUAL_MODE)) { 5704 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 5705 MDIO_WC_REG_DIGITAL5_LINK_STATUS, &link_up); 5706 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 5707 MDIO_WC_REG_DIGITAL5_LINK_STATUS, &link_up); 5708 link_up &= 0x1; 5709 } else if ((phy->req_line_speed > SPEED_10000) && 5710 (phy->supported & SUPPORTED_20000baseMLD2_Full)) { 5711 u16 temp_link_up; 5712 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 5713 1, &temp_link_up); 5714 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 5715 1, &link_up); 5716 DP(NETIF_MSG_LINK, "PCS RX link status = 0x%x-->0x%x\n", 5717 temp_link_up, link_up); 5718 link_up &= (1<<2); 5719 if (link_up) 5720 bnx2x_ext_phy_resolve_fc(phy, params, vars); 5721 } else { 5722 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 5723 MDIO_WC_REG_GP2_STATUS_GP_2_1, 5724 &gp_status1); 5725 DP(NETIF_MSG_LINK, "0x81d1 = 0x%x\n", gp_status1); 5726 /* Check for either KR, 1G, or AN up. */ 5727 link_up = ((gp_status1 >> 8) | 5728 (gp_status1 >> 12) | 5729 (gp_status1)) & 5730 (1 << lane); 5731 if (phy->supported & SUPPORTED_20000baseKR2_Full) { 5732 u16 an_link; 5733 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, 5734 MDIO_AN_REG_STATUS, &an_link); 5735 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, 5736 MDIO_AN_REG_STATUS, &an_link); 5737 link_up |= (an_link & (1<<2)); 5738 } 5739 if (link_up && SINGLE_MEDIA_DIRECT(params)) { 5740 u16 pd, gp_status4; 5741 if (phy->req_line_speed == SPEED_AUTO_NEG) { 5742 /* Check Autoneg complete */ 5743 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 5744 MDIO_WC_REG_GP2_STATUS_GP_2_4, 5745 &gp_status4); 5746 if (gp_status4 & ((1<<12)<<lane)) 5747 vars->link_status |= 5748 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; 5749 5750 /* Check parallel detect used */ 5751 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 5752 MDIO_WC_REG_PAR_DET_10G_STATUS, 5753 &pd); 5754 if (pd & (1<<15)) 5755 vars->link_status |= 5756 LINK_STATUS_PARALLEL_DETECTION_USED; 5757 } 5758 bnx2x_ext_phy_resolve_fc(phy, params, vars); 5759 vars->duplex = duplex; 5760 } 5761 } 5762 5763 if ((vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) && 5764 SINGLE_MEDIA_DIRECT(params)) { 5765 u16 val; 5766 5767 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, 5768 MDIO_AN_REG_LP_AUTO_NEG2, &val); 5769 5770 if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX) 5771 vars->link_status |= 5772 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; 5773 if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 | 5774 MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR)) 5775 vars->link_status |= 5776 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; 5777 5778 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 5779 MDIO_WC_REG_DIGITAL3_LP_UP1, &val); 5780 5781 if (val & MDIO_OVER_1G_UP1_2_5G) 5782 vars->link_status |= 5783 LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE; 5784 if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH)) 5785 vars->link_status |= 5786 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; 5787 5788 } 5789 5790 5791 if (lane < 2) { 5792 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 5793 MDIO_WC_REG_GP2_STATUS_GP_2_2, &gp_speed); 5794 } else { 5795 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 5796 MDIO_WC_REG_GP2_STATUS_GP_2_3, &gp_speed); 5797 } 5798 DP(NETIF_MSG_LINK, "lane %d gp_speed 0x%x\n", lane, gp_speed); 5799 5800 if ((lane & 1) == 0) 5801 gp_speed <<= 8; 5802 gp_speed &= 0x3f00; 5803 link_up = !!link_up; 5804 5805 rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, gp_speed, 5806 duplex); 5807 5808 /* In case of KR link down, start up the recovering procedure */ 5809 if ((!link_up) && (phy->media_type == ETH_PHY_KR) && 5810 (!(phy->flags & FLAGS_WC_DUAL_MODE))) 5811 vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY; 5812 5813 DP(NETIF_MSG_LINK, "duplex %x flow_ctrl 0x%x link_status 0x%x\n", 5814 vars->duplex, vars->flow_ctrl, vars->link_status); 5815 return rc; 5816 } 5817 static void bnx2x_set_gmii_tx_driver(struct link_params *params) 5818 { 5819 struct bnx2x *bp = params->bp; 5820 struct bnx2x_phy *phy = ¶ms->phy[INT_PHY]; 5821 u16 lp_up2; 5822 u16 tx_driver; 5823 u16 bank; 5824 5825 /* Read precomp */ 5826 CL22_RD_OVER_CL45(bp, phy, 5827 MDIO_REG_BANK_OVER_1G, 5828 MDIO_OVER_1G_LP_UP2, &lp_up2); 5829 5830 /* Bits [10:7] at lp_up2, positioned at [15:12] */ 5831 lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >> 5832 MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) << 5833 MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT); 5834 5835 if (lp_up2 == 0) 5836 return; 5837 5838 for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3; 5839 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) { 5840 CL22_RD_OVER_CL45(bp, phy, 5841 bank, 5842 MDIO_TX0_TX_DRIVER, &tx_driver); 5843 5844 /* Replace tx_driver bits [15:12] */ 5845 if (lp_up2 != 5846 (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) { 5847 tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK; 5848 tx_driver |= lp_up2; 5849 CL22_WR_OVER_CL45(bp, phy, 5850 bank, 5851 MDIO_TX0_TX_DRIVER, tx_driver); 5852 } 5853 } 5854 } 5855 5856 static int bnx2x_emac_program(struct link_params *params, 5857 struct link_vars *vars) 5858 { 5859 struct bnx2x *bp = params->bp; 5860 u8 port = params->port; 5861 u16 mode = 0; 5862 5863 DP(NETIF_MSG_LINK, "setting link speed & duplex\n"); 5864 bnx2x_bits_dis(bp, GRCBASE_EMAC0 + port*0x400 + 5865 EMAC_REG_EMAC_MODE, 5866 (EMAC_MODE_25G_MODE | 5867 EMAC_MODE_PORT_MII_10M | 5868 EMAC_MODE_HALF_DUPLEX)); 5869 switch (vars->line_speed) { 5870 case SPEED_10: 5871 mode |= EMAC_MODE_PORT_MII_10M; 5872 break; 5873 5874 case SPEED_100: 5875 mode |= EMAC_MODE_PORT_MII; 5876 break; 5877 5878 case SPEED_1000: 5879 mode |= EMAC_MODE_PORT_GMII; 5880 break; 5881 5882 case SPEED_2500: 5883 mode |= (EMAC_MODE_25G_MODE | EMAC_MODE_PORT_GMII); 5884 break; 5885 5886 default: 5887 /* 10G not valid for EMAC */ 5888 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n", 5889 vars->line_speed); 5890 return -EINVAL; 5891 } 5892 5893 if (vars->duplex == DUPLEX_HALF) 5894 mode |= EMAC_MODE_HALF_DUPLEX; 5895 bnx2x_bits_en(bp, 5896 GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE, 5897 mode); 5898 5899 bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed); 5900 return 0; 5901 } 5902 5903 static void bnx2x_set_preemphasis(struct bnx2x_phy *phy, 5904 struct link_params *params) 5905 { 5906 5907 u16 bank, i = 0; 5908 struct bnx2x *bp = params->bp; 5909 5910 for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3; 5911 bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0), i++) { 5912 CL22_WR_OVER_CL45(bp, phy, 5913 bank, 5914 MDIO_RX0_RX_EQ_BOOST, 5915 phy->rx_preemphasis[i]); 5916 } 5917 5918 for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3; 5919 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) { 5920 CL22_WR_OVER_CL45(bp, phy, 5921 bank, 5922 MDIO_TX0_TX_DRIVER, 5923 phy->tx_preemphasis[i]); 5924 } 5925 } 5926 5927 static void bnx2x_xgxs_config_init(struct bnx2x_phy *phy, 5928 struct link_params *params, 5929 struct link_vars *vars) 5930 { 5931 struct bnx2x *bp = params->bp; 5932 u8 enable_cl73 = (SINGLE_MEDIA_DIRECT(params) || 5933 (params->loopback_mode == LOOPBACK_XGXS)); 5934 if (!(vars->phy_flags & PHY_SGMII_FLAG)) { 5935 if (SINGLE_MEDIA_DIRECT(params) && 5936 (params->feature_config_flags & 5937 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) 5938 bnx2x_set_preemphasis(phy, params); 5939 5940 /* Forced speed requested? */ 5941 if (vars->line_speed != SPEED_AUTO_NEG || 5942 (SINGLE_MEDIA_DIRECT(params) && 5943 params->loopback_mode == LOOPBACK_EXT)) { 5944 DP(NETIF_MSG_LINK, "not SGMII, no AN\n"); 5945 5946 /* Disable autoneg */ 5947 bnx2x_set_autoneg(phy, params, vars, 0); 5948 5949 /* Program speed and duplex */ 5950 bnx2x_program_serdes(phy, params, vars); 5951 5952 } else { /* AN_mode */ 5953 DP(NETIF_MSG_LINK, "not SGMII, AN\n"); 5954 5955 /* AN enabled */ 5956 bnx2x_set_brcm_cl37_advertisement(phy, params); 5957 5958 /* Program duplex & pause advertisement (for aneg) */ 5959 bnx2x_set_ieee_aneg_advertisement(phy, params, 5960 vars->ieee_fc); 5961 5962 /* Enable autoneg */ 5963 bnx2x_set_autoneg(phy, params, vars, enable_cl73); 5964 5965 /* Enable and restart AN */ 5966 bnx2x_restart_autoneg(phy, params, enable_cl73); 5967 } 5968 5969 } else { /* SGMII mode */ 5970 DP(NETIF_MSG_LINK, "SGMII\n"); 5971 5972 bnx2x_initialize_sgmii_process(phy, params, vars); 5973 } 5974 } 5975 5976 static int bnx2x_prepare_xgxs(struct bnx2x_phy *phy, 5977 struct link_params *params, 5978 struct link_vars *vars) 5979 { 5980 int rc; 5981 vars->phy_flags |= PHY_XGXS_FLAG; 5982 if ((phy->req_line_speed && 5983 ((phy->req_line_speed == SPEED_100) || 5984 (phy->req_line_speed == SPEED_10))) || 5985 (!phy->req_line_speed && 5986 (phy->speed_cap_mask >= 5987 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) && 5988 (phy->speed_cap_mask < 5989 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) || 5990 (phy->type == PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD)) 5991 vars->phy_flags |= PHY_SGMII_FLAG; 5992 else 5993 vars->phy_flags &= ~PHY_SGMII_FLAG; 5994 5995 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); 5996 bnx2x_set_aer_mmd(params, phy); 5997 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) 5998 bnx2x_set_master_ln(params, phy); 5999 6000 rc = bnx2x_reset_unicore(params, phy, 0); 6001 /* Reset the SerDes and wait for reset bit return low */ 6002 if (rc) 6003 return rc; 6004 6005 bnx2x_set_aer_mmd(params, phy); 6006 /* Setting the masterLn_def again after the reset */ 6007 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) { 6008 bnx2x_set_master_ln(params, phy); 6009 bnx2x_set_swap_lanes(params, phy); 6010 } 6011 6012 return rc; 6013 } 6014 6015 static u16 bnx2x_wait_reset_complete(struct bnx2x *bp, 6016 struct bnx2x_phy *phy, 6017 struct link_params *params) 6018 { 6019 u16 cnt, ctrl; 6020 /* Wait for soft reset to get cleared up to 1 sec */ 6021 for (cnt = 0; cnt < 1000; cnt++) { 6022 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) 6023 bnx2x_cl22_read(bp, phy, 6024 MDIO_PMA_REG_CTRL, &ctrl); 6025 else 6026 bnx2x_cl45_read(bp, phy, 6027 MDIO_PMA_DEVAD, 6028 MDIO_PMA_REG_CTRL, &ctrl); 6029 if (!(ctrl & (1<<15))) 6030 break; 6031 usleep_range(1000, 2000); 6032 } 6033 6034 if (cnt == 1000) 6035 netdev_err(bp->dev, "Warning: PHY was not initialized," 6036 " Port %d\n", 6037 params->port); 6038 DP(NETIF_MSG_LINK, "control reg 0x%x (after %d ms)\n", ctrl, cnt); 6039 return cnt; 6040 } 6041 6042 static void bnx2x_link_int_enable(struct link_params *params) 6043 { 6044 u8 port = params->port; 6045 u32 mask; 6046 struct bnx2x *bp = params->bp; 6047 6048 /* Setting the status to report on link up for either XGXS or SerDes */ 6049 if (CHIP_IS_E3(bp)) { 6050 mask = NIG_MASK_XGXS0_LINK_STATUS; 6051 if (!(SINGLE_MEDIA_DIRECT(params))) 6052 mask |= NIG_MASK_MI_INT; 6053 } else if (params->switch_cfg == SWITCH_CFG_10G) { 6054 mask = (NIG_MASK_XGXS0_LINK10G | 6055 NIG_MASK_XGXS0_LINK_STATUS); 6056 DP(NETIF_MSG_LINK, "enabled XGXS interrupt\n"); 6057 if (!(SINGLE_MEDIA_DIRECT(params)) && 6058 params->phy[INT_PHY].type != 6059 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) { 6060 mask |= NIG_MASK_MI_INT; 6061 DP(NETIF_MSG_LINK, "enabled external phy int\n"); 6062 } 6063 6064 } else { /* SerDes */ 6065 mask = NIG_MASK_SERDES0_LINK_STATUS; 6066 DP(NETIF_MSG_LINK, "enabled SerDes interrupt\n"); 6067 if (!(SINGLE_MEDIA_DIRECT(params)) && 6068 params->phy[INT_PHY].type != 6069 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN) { 6070 mask |= NIG_MASK_MI_INT; 6071 DP(NETIF_MSG_LINK, "enabled external phy int\n"); 6072 } 6073 } 6074 bnx2x_bits_en(bp, 6075 NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 6076 mask); 6077 6078 DP(NETIF_MSG_LINK, "port %x, is_xgxs %x, int_status 0x%x\n", port, 6079 (params->switch_cfg == SWITCH_CFG_10G), 6080 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4)); 6081 DP(NETIF_MSG_LINK, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x\n", 6082 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4), 6083 REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18), 6084 REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS+port*0x3c)); 6085 DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n", 6086 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68), 6087 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68)); 6088 } 6089 6090 static void bnx2x_rearm_latch_signal(struct bnx2x *bp, u8 port, 6091 u8 exp_mi_int) 6092 { 6093 u32 latch_status = 0; 6094 6095 /* Disable the MI INT ( external phy int ) by writing 1 to the 6096 * status register. Link down indication is high-active-signal, 6097 * so in this case we need to write the status to clear the XOR 6098 */ 6099 /* Read Latched signals */ 6100 latch_status = REG_RD(bp, 6101 NIG_REG_LATCH_STATUS_0 + port*8); 6102 DP(NETIF_MSG_LINK, "latch_status = 0x%x\n", latch_status); 6103 /* Handle only those with latched-signal=up.*/ 6104 if (exp_mi_int) 6105 bnx2x_bits_en(bp, 6106 NIG_REG_STATUS_INTERRUPT_PORT0 6107 + port*4, 6108 NIG_STATUS_EMAC0_MI_INT); 6109 else 6110 bnx2x_bits_dis(bp, 6111 NIG_REG_STATUS_INTERRUPT_PORT0 6112 + port*4, 6113 NIG_STATUS_EMAC0_MI_INT); 6114 6115 if (latch_status & 1) { 6116 6117 /* For all latched-signal=up : Re-Arm Latch signals */ 6118 REG_WR(bp, NIG_REG_LATCH_STATUS_0 + port*8, 6119 (latch_status & 0xfffe) | (latch_status & 1)); 6120 } 6121 /* For all latched-signal=up,Write original_signal to status */ 6122 } 6123 6124 static void bnx2x_link_int_ack(struct link_params *params, 6125 struct link_vars *vars, u8 is_10g_plus) 6126 { 6127 struct bnx2x *bp = params->bp; 6128 u8 port = params->port; 6129 u32 mask; 6130 /* First reset all status we assume only one line will be 6131 * change at a time 6132 */ 6133 bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4, 6134 (NIG_STATUS_XGXS0_LINK10G | 6135 NIG_STATUS_XGXS0_LINK_STATUS | 6136 NIG_STATUS_SERDES0_LINK_STATUS)); 6137 if (vars->phy_link_up) { 6138 if (USES_WARPCORE(bp)) 6139 mask = NIG_STATUS_XGXS0_LINK_STATUS; 6140 else { 6141 if (is_10g_plus) 6142 mask = NIG_STATUS_XGXS0_LINK10G; 6143 else if (params->switch_cfg == SWITCH_CFG_10G) { 6144 /* Disable the link interrupt by writing 1 to 6145 * the relevant lane in the status register 6146 */ 6147 u32 ser_lane = 6148 ((params->lane_config & 6149 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >> 6150 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT); 6151 mask = ((1 << ser_lane) << 6152 NIG_STATUS_XGXS0_LINK_STATUS_SIZE); 6153 } else 6154 mask = NIG_STATUS_SERDES0_LINK_STATUS; 6155 } 6156 DP(NETIF_MSG_LINK, "Ack link up interrupt with mask 0x%x\n", 6157 mask); 6158 bnx2x_bits_en(bp, 6159 NIG_REG_STATUS_INTERRUPT_PORT0 + port*4, 6160 mask); 6161 } 6162 } 6163 6164 static int bnx2x_null_format_ver(u32 spirom_ver, u8 *str, u16 *len) 6165 { 6166 str[0] = '\0'; 6167 (*len)--; 6168 return 0; 6169 } 6170 6171 static int bnx2x_format_ver(u32 num, u8 *str, u16 *len) 6172 { 6173 u16 ret; 6174 6175 if (*len < 10) { 6176 /* Need more than 10chars for this format */ 6177 bnx2x_null_format_ver(num, str, len); 6178 return -EINVAL; 6179 } 6180 6181 ret = scnprintf(str, *len, "%x.%x", (num >> 16) & 0xFFFF, 6182 num & 0xFFFF); 6183 *len -= ret; 6184 return 0; 6185 } 6186 6187 static int bnx2x_3_seq_format_ver(u32 num, u8 *str, u16 *len) 6188 { 6189 u16 ret; 6190 6191 if (*len < 10) { 6192 /* Need more than 10chars for this format */ 6193 bnx2x_null_format_ver(num, str, len); 6194 return -EINVAL; 6195 } 6196 6197 ret = scnprintf(str, *len, "%x.%x.%x", (num >> 16) & 0xFF, 6198 (num >> 8) & 0xFF, num & 0xFF); 6199 *len -= ret; 6200 return 0; 6201 } 6202 6203 int bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 *version, 6204 u16 len) 6205 { 6206 struct bnx2x *bp; 6207 u32 spirom_ver = 0; 6208 int status = 0; 6209 u8 *ver_p = version; 6210 u16 remain_len = len; 6211 if (version == NULL || params == NULL) 6212 return -EINVAL; 6213 bp = params->bp; 6214 6215 /* Extract first external phy*/ 6216 version[0] = '\0'; 6217 spirom_ver = REG_RD(bp, params->phy[EXT_PHY1].ver_addr); 6218 6219 if (params->phy[EXT_PHY1].format_fw_ver) { 6220 status |= params->phy[EXT_PHY1].format_fw_ver(spirom_ver, 6221 ver_p, 6222 &remain_len); 6223 ver_p += (len - remain_len); 6224 } 6225 if ((params->num_phys == MAX_PHYS) && 6226 (params->phy[EXT_PHY2].ver_addr != 0)) { 6227 spirom_ver = REG_RD(bp, params->phy[EXT_PHY2].ver_addr); 6228 if (params->phy[EXT_PHY2].format_fw_ver) { 6229 *ver_p = '/'; 6230 ver_p++; 6231 remain_len--; 6232 status |= params->phy[EXT_PHY2].format_fw_ver( 6233 spirom_ver, 6234 ver_p, 6235 &remain_len); 6236 ver_p = version + (len - remain_len); 6237 } 6238 } 6239 *ver_p = '\0'; 6240 return status; 6241 } 6242 6243 static void bnx2x_set_xgxs_loopback(struct bnx2x_phy *phy, 6244 struct link_params *params) 6245 { 6246 u8 port = params->port; 6247 struct bnx2x *bp = params->bp; 6248 6249 if (phy->req_line_speed != SPEED_1000) { 6250 u32 md_devad = 0; 6251 6252 DP(NETIF_MSG_LINK, "XGXS 10G loopback enable\n"); 6253 6254 if (!CHIP_IS_E3(bp)) { 6255 /* Change the uni_phy_addr in the nig */ 6256 md_devad = REG_RD(bp, (NIG_REG_XGXS0_CTRL_MD_DEVAD + 6257 port*0x18)); 6258 6259 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, 6260 0x5); 6261 } 6262 6263 bnx2x_cl45_write(bp, phy, 6264 5, 6265 (MDIO_REG_BANK_AER_BLOCK + 6266 (MDIO_AER_BLOCK_AER_REG & 0xf)), 6267 0x2800); 6268 6269 bnx2x_cl45_write(bp, phy, 6270 5, 6271 (MDIO_REG_BANK_CL73_IEEEB0 + 6272 (MDIO_CL73_IEEEB0_CL73_AN_CONTROL & 0xf)), 6273 0x6041); 6274 msleep(200); 6275 /* Set aer mmd back */ 6276 bnx2x_set_aer_mmd(params, phy); 6277 6278 if (!CHIP_IS_E3(bp)) { 6279 /* And md_devad */ 6280 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, 6281 md_devad); 6282 } 6283 } else { 6284 u16 mii_ctrl; 6285 DP(NETIF_MSG_LINK, "XGXS 1G loopback enable\n"); 6286 bnx2x_cl45_read(bp, phy, 5, 6287 (MDIO_REG_BANK_COMBO_IEEE0 + 6288 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)), 6289 &mii_ctrl); 6290 bnx2x_cl45_write(bp, phy, 5, 6291 (MDIO_REG_BANK_COMBO_IEEE0 + 6292 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)), 6293 mii_ctrl | 6294 MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK); 6295 } 6296 } 6297 6298 int bnx2x_set_led(struct link_params *params, 6299 struct link_vars *vars, u8 mode, u32 speed) 6300 { 6301 u8 port = params->port; 6302 u16 hw_led_mode = params->hw_led_mode; 6303 int rc = 0; 6304 u8 phy_idx; 6305 u32 tmp; 6306 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; 6307 struct bnx2x *bp = params->bp; 6308 DP(NETIF_MSG_LINK, "bnx2x_set_led: port %x, mode %d\n", port, mode); 6309 DP(NETIF_MSG_LINK, "speed 0x%x, hw_led_mode 0x%x\n", 6310 speed, hw_led_mode); 6311 /* In case */ 6312 for (phy_idx = EXT_PHY1; phy_idx < MAX_PHYS; phy_idx++) { 6313 if (params->phy[phy_idx].set_link_led) { 6314 params->phy[phy_idx].set_link_led( 6315 ¶ms->phy[phy_idx], params, mode); 6316 } 6317 } 6318 6319 switch (mode) { 6320 case LED_MODE_FRONT_PANEL_OFF: 6321 case LED_MODE_OFF: 6322 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 0); 6323 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 6324 SHARED_HW_CFG_LED_MAC1); 6325 6326 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED); 6327 if (params->phy[EXT_PHY1].type == 6328 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) 6329 tmp &= ~(EMAC_LED_1000MB_OVERRIDE | 6330 EMAC_LED_100MB_OVERRIDE | 6331 EMAC_LED_10MB_OVERRIDE); 6332 else 6333 tmp |= EMAC_LED_OVERRIDE; 6334 6335 EMAC_WR(bp, EMAC_REG_EMAC_LED, tmp); 6336 break; 6337 6338 case LED_MODE_OPER: 6339 /* For all other phys, OPER mode is same as ON, so in case 6340 * link is down, do nothing 6341 */ 6342 if (!vars->link_up) 6343 break; 6344 fallthrough; 6345 case LED_MODE_ON: 6346 if (((params->phy[EXT_PHY1].type == 6347 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) || 6348 (params->phy[EXT_PHY1].type == 6349 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722)) && 6350 CHIP_IS_E2(bp) && params->num_phys == 2) { 6351 /* This is a work-around for E2+8727 Configurations */ 6352 if (mode == LED_MODE_ON || 6353 speed == SPEED_10000){ 6354 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0); 6355 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1); 6356 6357 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED); 6358 EMAC_WR(bp, EMAC_REG_EMAC_LED, 6359 (tmp | EMAC_LED_OVERRIDE)); 6360 /* Return here without enabling traffic 6361 * LED blink and setting rate in ON mode. 6362 * In oper mode, enabling LED blink 6363 * and setting rate is needed. 6364 */ 6365 if (mode == LED_MODE_ON) 6366 return rc; 6367 } 6368 } else if (SINGLE_MEDIA_DIRECT(params)) { 6369 /* This is a work-around for HW issue found when link 6370 * is up in CL73 6371 */ 6372 if ((!CHIP_IS_E3(bp)) || 6373 (CHIP_IS_E3(bp) && 6374 mode == LED_MODE_ON)) 6375 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1); 6376 6377 if (CHIP_IS_E1x(bp) || 6378 CHIP_IS_E2(bp) || 6379 (mode == LED_MODE_ON)) 6380 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0); 6381 else 6382 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 6383 hw_led_mode); 6384 } else if ((params->phy[EXT_PHY1].type == 6385 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) && 6386 (mode == LED_MODE_ON)) { 6387 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0); 6388 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED); 6389 EMAC_WR(bp, EMAC_REG_EMAC_LED, tmp | 6390 EMAC_LED_OVERRIDE | EMAC_LED_1000MB_OVERRIDE); 6391 /* Break here; otherwise, it'll disable the 6392 * intended override. 6393 */ 6394 break; 6395 } else { 6396 u32 nig_led_mode = ((params->hw_led_mode << 6397 SHARED_HW_CFG_LED_MODE_SHIFT) == 6398 SHARED_HW_CFG_LED_EXTPHY2) ? 6399 (SHARED_HW_CFG_LED_PHY1 >> 6400 SHARED_HW_CFG_LED_MODE_SHIFT) : hw_led_mode; 6401 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 6402 nig_led_mode); 6403 } 6404 6405 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 0); 6406 /* Set blinking rate to ~15.9Hz */ 6407 if (CHIP_IS_E3(bp)) 6408 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4, 6409 LED_BLINK_RATE_VAL_E3); 6410 else 6411 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4, 6412 LED_BLINK_RATE_VAL_E1X_E2); 6413 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 + 6414 port*4, 1); 6415 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED); 6416 EMAC_WR(bp, EMAC_REG_EMAC_LED, 6417 (tmp & (~EMAC_LED_OVERRIDE))); 6418 6419 if (CHIP_IS_E1(bp) && 6420 ((speed == SPEED_2500) || 6421 (speed == SPEED_1000) || 6422 (speed == SPEED_100) || 6423 (speed == SPEED_10))) { 6424 /* For speeds less than 10G LED scheme is different */ 6425 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 6426 + port*4, 1); 6427 REG_WR(bp, NIG_REG_LED_CONTROL_TRAFFIC_P0 + 6428 port*4, 0); 6429 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 + 6430 port*4, 1); 6431 } 6432 break; 6433 6434 default: 6435 rc = -EINVAL; 6436 DP(NETIF_MSG_LINK, "bnx2x_set_led: Invalid led mode %d\n", 6437 mode); 6438 break; 6439 } 6440 return rc; 6441 6442 } 6443 6444 /* This function comes to reflect the actual link state read DIRECTLY from the 6445 * HW 6446 */ 6447 int bnx2x_test_link(struct link_params *params, struct link_vars *vars, 6448 u8 is_serdes) 6449 { 6450 struct bnx2x *bp = params->bp; 6451 u16 gp_status = 0, phy_index = 0; 6452 u8 ext_phy_link_up = 0, serdes_phy_type; 6453 struct link_vars temp_vars; 6454 struct bnx2x_phy *int_phy = ¶ms->phy[INT_PHY]; 6455 6456 if (CHIP_IS_E3(bp)) { 6457 u16 link_up; 6458 if (params->req_line_speed[LINK_CONFIG_IDX(INT_PHY)] 6459 > SPEED_10000) { 6460 /* Check 20G link */ 6461 bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD, 6462 1, &link_up); 6463 bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD, 6464 1, &link_up); 6465 link_up &= (1<<2); 6466 } else { 6467 /* Check 10G link and below*/ 6468 u8 lane = bnx2x_get_warpcore_lane(int_phy, params); 6469 bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD, 6470 MDIO_WC_REG_GP2_STATUS_GP_2_1, 6471 &gp_status); 6472 gp_status = ((gp_status >> 8) & 0xf) | 6473 ((gp_status >> 12) & 0xf); 6474 link_up = gp_status & (1 << lane); 6475 } 6476 if (!link_up) 6477 return -ESRCH; 6478 } else { 6479 CL22_RD_OVER_CL45(bp, int_phy, 6480 MDIO_REG_BANK_GP_STATUS, 6481 MDIO_GP_STATUS_TOP_AN_STATUS1, 6482 &gp_status); 6483 /* Link is up only if both local phy and external phy are up */ 6484 if (!(gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS)) 6485 return -ESRCH; 6486 } 6487 /* In XGXS loopback mode, do not check external PHY */ 6488 if (params->loopback_mode == LOOPBACK_XGXS) 6489 return 0; 6490 6491 switch (params->num_phys) { 6492 case 1: 6493 /* No external PHY */ 6494 return 0; 6495 case 2: 6496 ext_phy_link_up = params->phy[EXT_PHY1].read_status( 6497 ¶ms->phy[EXT_PHY1], 6498 params, &temp_vars); 6499 break; 6500 case 3: /* Dual Media */ 6501 for (phy_index = EXT_PHY1; phy_index < params->num_phys; 6502 phy_index++) { 6503 serdes_phy_type = ((params->phy[phy_index].media_type == 6504 ETH_PHY_SFPP_10G_FIBER) || 6505 (params->phy[phy_index].media_type == 6506 ETH_PHY_SFP_1G_FIBER) || 6507 (params->phy[phy_index].media_type == 6508 ETH_PHY_XFP_FIBER) || 6509 (params->phy[phy_index].media_type == 6510 ETH_PHY_DA_TWINAX)); 6511 6512 if (is_serdes != serdes_phy_type) 6513 continue; 6514 if (params->phy[phy_index].read_status) { 6515 ext_phy_link_up |= 6516 params->phy[phy_index].read_status( 6517 ¶ms->phy[phy_index], 6518 params, &temp_vars); 6519 } 6520 } 6521 break; 6522 } 6523 if (ext_phy_link_up) 6524 return 0; 6525 return -ESRCH; 6526 } 6527 6528 static int bnx2x_link_initialize(struct link_params *params, 6529 struct link_vars *vars) 6530 { 6531 u8 phy_index, non_ext_phy; 6532 struct bnx2x *bp = params->bp; 6533 /* In case of external phy existence, the line speed would be the 6534 * line speed linked up by the external phy. In case it is direct 6535 * only, then the line_speed during initialization will be 6536 * equal to the req_line_speed 6537 */ 6538 vars->line_speed = params->phy[INT_PHY].req_line_speed; 6539 6540 /* Initialize the internal phy in case this is a direct board 6541 * (no external phys), or this board has external phy which requires 6542 * to first. 6543 */ 6544 if (!USES_WARPCORE(bp)) 6545 bnx2x_prepare_xgxs(¶ms->phy[INT_PHY], params, vars); 6546 /* init ext phy and enable link state int */ 6547 non_ext_phy = (SINGLE_MEDIA_DIRECT(params) || 6548 (params->loopback_mode == LOOPBACK_XGXS)); 6549 6550 if (non_ext_phy || 6551 (params->phy[EXT_PHY1].flags & FLAGS_INIT_XGXS_FIRST) || 6552 (params->loopback_mode == LOOPBACK_EXT_PHY)) { 6553 struct bnx2x_phy *phy = ¶ms->phy[INT_PHY]; 6554 if (vars->line_speed == SPEED_AUTO_NEG && 6555 (CHIP_IS_E1x(bp) || 6556 CHIP_IS_E2(bp))) 6557 bnx2x_set_parallel_detection(phy, params); 6558 if (params->phy[INT_PHY].config_init) 6559 params->phy[INT_PHY].config_init(phy, params, vars); 6560 } 6561 6562 /* Re-read this value in case it was changed inside config_init due to 6563 * limitations of optic module 6564 */ 6565 vars->line_speed = params->phy[INT_PHY].req_line_speed; 6566 6567 /* Init external phy*/ 6568 if (non_ext_phy) { 6569 if (params->phy[INT_PHY].supported & 6570 SUPPORTED_FIBRE) 6571 vars->link_status |= LINK_STATUS_SERDES_LINK; 6572 } else { 6573 for (phy_index = EXT_PHY1; phy_index < params->num_phys; 6574 phy_index++) { 6575 /* No need to initialize second phy in case of first 6576 * phy only selection. In case of second phy, we do 6577 * need to initialize the first phy, since they are 6578 * connected. 6579 */ 6580 if (params->phy[phy_index].supported & 6581 SUPPORTED_FIBRE) 6582 vars->link_status |= LINK_STATUS_SERDES_LINK; 6583 6584 if (phy_index == EXT_PHY2 && 6585 (bnx2x_phy_selection(params) == 6586 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY)) { 6587 DP(NETIF_MSG_LINK, 6588 "Not initializing second phy\n"); 6589 continue; 6590 } 6591 params->phy[phy_index].config_init( 6592 ¶ms->phy[phy_index], 6593 params, vars); 6594 } 6595 } 6596 /* Reset the interrupt indication after phy was initialized */ 6597 bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + 6598 params->port*4, 6599 (NIG_STATUS_XGXS0_LINK10G | 6600 NIG_STATUS_XGXS0_LINK_STATUS | 6601 NIG_STATUS_SERDES0_LINK_STATUS | 6602 NIG_MASK_MI_INT)); 6603 return 0; 6604 } 6605 6606 static void bnx2x_int_link_reset(struct bnx2x_phy *phy, 6607 struct link_params *params) 6608 { 6609 /* Reset the SerDes/XGXS */ 6610 REG_WR(params->bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, 6611 (0x1ff << (params->port*16))); 6612 } 6613 6614 static void bnx2x_common_ext_link_reset(struct bnx2x_phy *phy, 6615 struct link_params *params) 6616 { 6617 struct bnx2x *bp = params->bp; 6618 u8 gpio_port; 6619 /* HW reset */ 6620 if (CHIP_IS_E2(bp)) 6621 gpio_port = BP_PATH(bp); 6622 else 6623 gpio_port = params->port; 6624 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, 6625 MISC_REGISTERS_GPIO_OUTPUT_LOW, 6626 gpio_port); 6627 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 6628 MISC_REGISTERS_GPIO_OUTPUT_LOW, 6629 gpio_port); 6630 DP(NETIF_MSG_LINK, "reset external PHY\n"); 6631 } 6632 6633 static int bnx2x_update_link_down(struct link_params *params, 6634 struct link_vars *vars) 6635 { 6636 struct bnx2x *bp = params->bp; 6637 u8 port = params->port; 6638 6639 DP(NETIF_MSG_LINK, "Port %x: Link is down\n", port); 6640 bnx2x_set_led(params, vars, LED_MODE_OFF, 0); 6641 vars->phy_flags &= ~PHY_PHYSICAL_LINK_FLAG; 6642 /* Indicate no mac active */ 6643 vars->mac_type = MAC_TYPE_NONE; 6644 6645 /* Update shared memory */ 6646 vars->link_status &= ~LINK_UPDATE_MASK; 6647 vars->line_speed = 0; 6648 bnx2x_update_mng(params, vars->link_status); 6649 6650 /* Activate nig drain */ 6651 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1); 6652 6653 /* Disable emac */ 6654 if (!CHIP_IS_E3(bp)) 6655 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0); 6656 6657 usleep_range(10000, 20000); 6658 /* Reset BigMac/Xmac */ 6659 if (CHIP_IS_E1x(bp) || 6660 CHIP_IS_E2(bp)) 6661 bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 0); 6662 6663 if (CHIP_IS_E3(bp)) { 6664 /* Prevent LPI Generation by chip */ 6665 REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2), 6666 0); 6667 REG_WR(bp, MISC_REG_CPMU_LP_MASK_ENT_P0 + (params->port << 2), 6668 0); 6669 vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK | 6670 SHMEM_EEE_ACTIVE_BIT); 6671 6672 bnx2x_update_mng_eee(params, vars->eee_status); 6673 bnx2x_set_xmac_rxtx(params, 0); 6674 bnx2x_set_umac_rxtx(params, 0); 6675 } 6676 6677 return 0; 6678 } 6679 6680 static int bnx2x_update_link_up(struct link_params *params, 6681 struct link_vars *vars, 6682 u8 link_10g) 6683 { 6684 struct bnx2x *bp = params->bp; 6685 u8 phy_idx, port = params->port; 6686 int rc = 0; 6687 6688 vars->link_status |= (LINK_STATUS_LINK_UP | 6689 LINK_STATUS_PHYSICAL_LINK_FLAG); 6690 vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG; 6691 6692 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) 6693 vars->link_status |= 6694 LINK_STATUS_TX_FLOW_CONTROL_ENABLED; 6695 6696 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX) 6697 vars->link_status |= 6698 LINK_STATUS_RX_FLOW_CONTROL_ENABLED; 6699 if (USES_WARPCORE(bp)) { 6700 if (link_10g) { 6701 if (bnx2x_xmac_enable(params, vars, 0) == 6702 -ESRCH) { 6703 DP(NETIF_MSG_LINK, "Found errors on XMAC\n"); 6704 vars->link_up = 0; 6705 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG; 6706 vars->link_status &= ~LINK_STATUS_LINK_UP; 6707 } 6708 } else 6709 bnx2x_umac_enable(params, vars, 0); 6710 bnx2x_set_led(params, vars, 6711 LED_MODE_OPER, vars->line_speed); 6712 6713 if ((vars->eee_status & SHMEM_EEE_ACTIVE_BIT) && 6714 (vars->eee_status & SHMEM_EEE_LPI_REQUESTED_BIT)) { 6715 DP(NETIF_MSG_LINK, "Enabling LPI assertion\n"); 6716 REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + 6717 (params->port << 2), 1); 6718 REG_WR(bp, MISC_REG_CPMU_LP_DR_ENABLE, 1); 6719 REG_WR(bp, MISC_REG_CPMU_LP_MASK_ENT_P0 + 6720 (params->port << 2), 0xfc20); 6721 } 6722 } 6723 if ((CHIP_IS_E1x(bp) || 6724 CHIP_IS_E2(bp))) { 6725 if (link_10g) { 6726 if (bnx2x_bmac_enable(params, vars, 0, 1) == 6727 -ESRCH) { 6728 DP(NETIF_MSG_LINK, "Found errors on BMAC\n"); 6729 vars->link_up = 0; 6730 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG; 6731 vars->link_status &= ~LINK_STATUS_LINK_UP; 6732 } 6733 6734 bnx2x_set_led(params, vars, 6735 LED_MODE_OPER, SPEED_10000); 6736 } else { 6737 rc = bnx2x_emac_program(params, vars); 6738 bnx2x_emac_enable(params, vars, 0); 6739 6740 /* AN complete? */ 6741 if ((vars->link_status & 6742 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) 6743 && (!(vars->phy_flags & PHY_SGMII_FLAG)) && 6744 SINGLE_MEDIA_DIRECT(params)) 6745 bnx2x_set_gmii_tx_driver(params); 6746 } 6747 } 6748 6749 /* PBF - link up */ 6750 if (CHIP_IS_E1x(bp)) 6751 rc |= bnx2x_pbf_update(params, vars->flow_ctrl, 6752 vars->line_speed); 6753 6754 /* Disable drain */ 6755 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0); 6756 6757 /* Update shared memory */ 6758 bnx2x_update_mng(params, vars->link_status); 6759 bnx2x_update_mng_eee(params, vars->eee_status); 6760 /* Check remote fault */ 6761 for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) { 6762 if (params->phy[phy_idx].flags & FLAGS_TX_ERROR_CHECK) { 6763 bnx2x_check_half_open_conn(params, vars, 0); 6764 break; 6765 } 6766 } 6767 msleep(20); 6768 return rc; 6769 } 6770 6771 static void bnx2x_chng_link_count(struct link_params *params, bool clear) 6772 { 6773 struct bnx2x *bp = params->bp; 6774 u32 addr, val; 6775 6776 /* Verify the link_change_count is supported by the MFW */ 6777 if (!(SHMEM2_HAS(bp, link_change_count))) 6778 return; 6779 6780 addr = params->shmem2_base + 6781 offsetof(struct shmem2_region, link_change_count[params->port]); 6782 if (clear) 6783 val = 0; 6784 else 6785 val = REG_RD(bp, addr) + 1; 6786 REG_WR(bp, addr, val); 6787 } 6788 6789 /* The bnx2x_link_update function should be called upon link 6790 * interrupt. 6791 * Link is considered up as follows: 6792 * - DIRECT_SINGLE_MEDIA - Only XGXS link (internal link) needs 6793 * to be up 6794 * - SINGLE_MEDIA - The link between the 577xx and the external 6795 * phy (XGXS) need to up as well as the external link of the 6796 * phy (PHY_EXT1) 6797 * - DUAL_MEDIA - The link between the 577xx and the first 6798 * external phy needs to be up, and at least one of the 2 6799 * external phy link must be up. 6800 */ 6801 int bnx2x_link_update(struct link_params *params, struct link_vars *vars) 6802 { 6803 struct bnx2x *bp = params->bp; 6804 struct link_vars phy_vars[MAX_PHYS]; 6805 u8 port = params->port; 6806 u8 link_10g_plus, phy_index; 6807 u32 prev_link_status = vars->link_status; 6808 u8 ext_phy_link_up = 0, cur_link_up; 6809 int rc = 0; 6810 u8 is_mi_int = 0; 6811 u16 ext_phy_line_speed = 0, prev_line_speed = vars->line_speed; 6812 u8 active_external_phy = INT_PHY; 6813 vars->phy_flags &= ~PHY_HALF_OPEN_CONN_FLAG; 6814 vars->link_status &= ~LINK_UPDATE_MASK; 6815 for (phy_index = INT_PHY; phy_index < params->num_phys; 6816 phy_index++) { 6817 phy_vars[phy_index].flow_ctrl = 0; 6818 phy_vars[phy_index].link_status = 0; 6819 phy_vars[phy_index].line_speed = 0; 6820 phy_vars[phy_index].duplex = DUPLEX_FULL; 6821 phy_vars[phy_index].phy_link_up = 0; 6822 phy_vars[phy_index].link_up = 0; 6823 phy_vars[phy_index].fault_detected = 0; 6824 /* different consideration, since vars holds inner state */ 6825 phy_vars[phy_index].eee_status = vars->eee_status; 6826 } 6827 6828 if (USES_WARPCORE(bp)) 6829 bnx2x_set_aer_mmd(params, ¶ms->phy[INT_PHY]); 6830 6831 DP(NETIF_MSG_LINK, "port %x, XGXS?%x, int_status 0x%x\n", 6832 port, (vars->phy_flags & PHY_XGXS_FLAG), 6833 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4)); 6834 6835 is_mi_int = (u8)(REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + 6836 port*0x18) > 0); 6837 DP(NETIF_MSG_LINK, "int_mask 0x%x MI_INT %x, SERDES_LINK %x\n", 6838 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4), 6839 is_mi_int, 6840 REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c)); 6841 6842 DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n", 6843 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68), 6844 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68)); 6845 6846 /* Disable emac */ 6847 if (!CHIP_IS_E3(bp)) 6848 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0); 6849 6850 /* Step 1: 6851 * Check external link change only for external phys, and apply 6852 * priority selection between them in case the link on both phys 6853 * is up. Note that instead of the common vars, a temporary 6854 * vars argument is used since each phy may have different link/ 6855 * speed/duplex result 6856 */ 6857 for (phy_index = EXT_PHY1; phy_index < params->num_phys; 6858 phy_index++) { 6859 struct bnx2x_phy *phy = ¶ms->phy[phy_index]; 6860 if (!phy->read_status) 6861 continue; 6862 /* Read link status and params of this ext phy */ 6863 cur_link_up = phy->read_status(phy, params, 6864 &phy_vars[phy_index]); 6865 if (cur_link_up) { 6866 DP(NETIF_MSG_LINK, "phy in index %d link is up\n", 6867 phy_index); 6868 } else { 6869 DP(NETIF_MSG_LINK, "phy in index %d link is down\n", 6870 phy_index); 6871 continue; 6872 } 6873 6874 if (!ext_phy_link_up) { 6875 ext_phy_link_up = 1; 6876 active_external_phy = phy_index; 6877 } else { 6878 switch (bnx2x_phy_selection(params)) { 6879 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT: 6880 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY: 6881 /* In this option, the first PHY makes sure to pass the 6882 * traffic through itself only. 6883 * It's not clear how to reset the link on the second 6884 * phy. 6885 */ 6886 active_external_phy = EXT_PHY1; 6887 break; 6888 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY: 6889 /* In this option, the first PHY makes sure to pass the 6890 * traffic through the second PHY. 6891 */ 6892 active_external_phy = EXT_PHY2; 6893 break; 6894 default: 6895 /* Link indication on both PHYs with the following cases 6896 * is invalid: 6897 * - FIRST_PHY means that second phy wasn't initialized, 6898 * hence its link is expected to be down 6899 * - SECOND_PHY means that first phy should not be able 6900 * to link up by itself (using configuration) 6901 * - DEFAULT should be overridden during initialization 6902 */ 6903 DP(NETIF_MSG_LINK, "Invalid link indication" 6904 "mpc=0x%x. DISABLING LINK !!!\n", 6905 params->multi_phy_config); 6906 ext_phy_link_up = 0; 6907 break; 6908 } 6909 } 6910 } 6911 prev_line_speed = vars->line_speed; 6912 /* Step 2: 6913 * Read the status of the internal phy. In case of 6914 * DIRECT_SINGLE_MEDIA board, this link is the external link, 6915 * otherwise this is the link between the 577xx and the first 6916 * external phy 6917 */ 6918 if (params->phy[INT_PHY].read_status) 6919 params->phy[INT_PHY].read_status( 6920 ¶ms->phy[INT_PHY], 6921 params, vars); 6922 /* The INT_PHY flow control reside in the vars. This include the 6923 * case where the speed or flow control are not set to AUTO. 6924 * Otherwise, the active external phy flow control result is set 6925 * to the vars. The ext_phy_line_speed is needed to check if the 6926 * speed is different between the internal phy and external phy. 6927 * This case may be result of intermediate link speed change. 6928 */ 6929 if (active_external_phy > INT_PHY) { 6930 vars->flow_ctrl = phy_vars[active_external_phy].flow_ctrl; 6931 /* Link speed is taken from the XGXS. AN and FC result from 6932 * the external phy. 6933 */ 6934 vars->link_status |= phy_vars[active_external_phy].link_status; 6935 6936 /* if active_external_phy is first PHY and link is up - disable 6937 * disable TX on second external PHY 6938 */ 6939 if (active_external_phy == EXT_PHY1) { 6940 if (params->phy[EXT_PHY2].phy_specific_func) { 6941 DP(NETIF_MSG_LINK, 6942 "Disabling TX on EXT_PHY2\n"); 6943 params->phy[EXT_PHY2].phy_specific_func( 6944 ¶ms->phy[EXT_PHY2], 6945 params, DISABLE_TX); 6946 } 6947 } 6948 6949 ext_phy_line_speed = phy_vars[active_external_phy].line_speed; 6950 vars->duplex = phy_vars[active_external_phy].duplex; 6951 if (params->phy[active_external_phy].supported & 6952 SUPPORTED_FIBRE) 6953 vars->link_status |= LINK_STATUS_SERDES_LINK; 6954 else 6955 vars->link_status &= ~LINK_STATUS_SERDES_LINK; 6956 6957 vars->eee_status = phy_vars[active_external_phy].eee_status; 6958 6959 DP(NETIF_MSG_LINK, "Active external phy selected: %x\n", 6960 active_external_phy); 6961 } 6962 6963 for (phy_index = EXT_PHY1; phy_index < params->num_phys; 6964 phy_index++) { 6965 if (params->phy[phy_index].flags & 6966 FLAGS_REARM_LATCH_SIGNAL) { 6967 bnx2x_rearm_latch_signal(bp, port, 6968 phy_index == 6969 active_external_phy); 6970 break; 6971 } 6972 } 6973 DP(NETIF_MSG_LINK, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x," 6974 " ext_phy_line_speed = %d\n", vars->flow_ctrl, 6975 vars->link_status, ext_phy_line_speed); 6976 /* Upon link speed change set the NIG into drain mode. Comes to 6977 * deals with possible FIFO glitch due to clk change when speed 6978 * is decreased without link down indicator 6979 */ 6980 6981 if (vars->phy_link_up) { 6982 if (!(SINGLE_MEDIA_DIRECT(params)) && ext_phy_link_up && 6983 (ext_phy_line_speed != vars->line_speed)) { 6984 DP(NETIF_MSG_LINK, "Internal link speed %d is" 6985 " different than the external" 6986 " link speed %d\n", vars->line_speed, 6987 ext_phy_line_speed); 6988 vars->phy_link_up = 0; 6989 } else if (prev_line_speed != vars->line_speed) { 6990 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 6991 0); 6992 usleep_range(1000, 2000); 6993 } 6994 } 6995 6996 /* Anything 10 and over uses the bmac */ 6997 link_10g_plus = (vars->line_speed >= SPEED_10000); 6998 6999 bnx2x_link_int_ack(params, vars, link_10g_plus); 7000 7001 /* In case external phy link is up, and internal link is down 7002 * (not initialized yet probably after link initialization, it 7003 * needs to be initialized. 7004 * Note that after link down-up as result of cable plug, the xgxs 7005 * link would probably become up again without the need 7006 * initialize it 7007 */ 7008 if (!(SINGLE_MEDIA_DIRECT(params))) { 7009 DP(NETIF_MSG_LINK, "ext_phy_link_up = %d, int_link_up = %d," 7010 " init_preceding = %d\n", ext_phy_link_up, 7011 vars->phy_link_up, 7012 params->phy[EXT_PHY1].flags & 7013 FLAGS_INIT_XGXS_FIRST); 7014 if (!(params->phy[EXT_PHY1].flags & 7015 FLAGS_INIT_XGXS_FIRST) 7016 && ext_phy_link_up && !vars->phy_link_up) { 7017 vars->line_speed = ext_phy_line_speed; 7018 if (vars->line_speed < SPEED_1000) 7019 vars->phy_flags |= PHY_SGMII_FLAG; 7020 else 7021 vars->phy_flags &= ~PHY_SGMII_FLAG; 7022 7023 if (params->phy[INT_PHY].config_init) 7024 params->phy[INT_PHY].config_init( 7025 ¶ms->phy[INT_PHY], params, 7026 vars); 7027 } 7028 } 7029 /* Link is up only if both local phy and external phy (in case of 7030 * non-direct board) are up and no fault detected on active PHY. 7031 */ 7032 vars->link_up = (vars->phy_link_up && 7033 (ext_phy_link_up || 7034 SINGLE_MEDIA_DIRECT(params)) && 7035 (phy_vars[active_external_phy].fault_detected == 0)); 7036 7037 /* Update the PFC configuration in case it was changed */ 7038 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) 7039 vars->link_status |= LINK_STATUS_PFC_ENABLED; 7040 else 7041 vars->link_status &= ~LINK_STATUS_PFC_ENABLED; 7042 7043 if (vars->link_up) 7044 rc = bnx2x_update_link_up(params, vars, link_10g_plus); 7045 else 7046 rc = bnx2x_update_link_down(params, vars); 7047 7048 if ((prev_link_status ^ vars->link_status) & LINK_STATUS_LINK_UP) 7049 bnx2x_chng_link_count(params, false); 7050 7051 /* Update MCP link status was changed */ 7052 if (params->feature_config_flags & FEATURE_CONFIG_BC_SUPPORTS_AFEX) 7053 bnx2x_fw_command(bp, DRV_MSG_CODE_LINK_STATUS_CHANGED, 0); 7054 7055 return rc; 7056 } 7057 7058 /*****************************************************************************/ 7059 /* External Phy section */ 7060 /*****************************************************************************/ 7061 void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port) 7062 { 7063 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, 7064 MISC_REGISTERS_GPIO_OUTPUT_LOW, port); 7065 usleep_range(1000, 2000); 7066 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, 7067 MISC_REGISTERS_GPIO_OUTPUT_HIGH, port); 7068 } 7069 7070 static void bnx2x_save_spirom_version(struct bnx2x *bp, u8 port, 7071 u32 spirom_ver, u32 ver_addr) 7072 { 7073 DP(NETIF_MSG_LINK, "FW version 0x%x:0x%x for port %d\n", 7074 (u16)(spirom_ver>>16), (u16)spirom_ver, port); 7075 7076 if (ver_addr) 7077 REG_WR(bp, ver_addr, spirom_ver); 7078 } 7079 7080 static void bnx2x_save_bcm_spirom_ver(struct bnx2x *bp, 7081 struct bnx2x_phy *phy, 7082 u8 port) 7083 { 7084 u16 fw_ver1, fw_ver2; 7085 7086 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 7087 MDIO_PMA_REG_ROM_VER1, &fw_ver1); 7088 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 7089 MDIO_PMA_REG_ROM_VER2, &fw_ver2); 7090 bnx2x_save_spirom_version(bp, port, (u32)(fw_ver1<<16 | fw_ver2), 7091 phy->ver_addr); 7092 } 7093 7094 static void bnx2x_ext_phy_10G_an_resolve(struct bnx2x *bp, 7095 struct bnx2x_phy *phy, 7096 struct link_vars *vars) 7097 { 7098 u16 val; 7099 bnx2x_cl45_read(bp, phy, 7100 MDIO_AN_DEVAD, 7101 MDIO_AN_REG_STATUS, &val); 7102 bnx2x_cl45_read(bp, phy, 7103 MDIO_AN_DEVAD, 7104 MDIO_AN_REG_STATUS, &val); 7105 if (val & (1<<5)) 7106 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; 7107 if ((val & (1<<0)) == 0) 7108 vars->link_status |= LINK_STATUS_PARALLEL_DETECTION_USED; 7109 } 7110 7111 /******************************************************************/ 7112 /* common BCM8073/BCM8727 PHY SECTION */ 7113 /******************************************************************/ 7114 static void bnx2x_8073_resolve_fc(struct bnx2x_phy *phy, 7115 struct link_params *params, 7116 struct link_vars *vars) 7117 { 7118 struct bnx2x *bp = params->bp; 7119 if (phy->req_line_speed == SPEED_10 || 7120 phy->req_line_speed == SPEED_100) { 7121 vars->flow_ctrl = phy->req_flow_ctrl; 7122 return; 7123 } 7124 7125 if (bnx2x_ext_phy_resolve_fc(phy, params, vars) && 7126 (vars->flow_ctrl == BNX2X_FLOW_CTRL_NONE)) { 7127 u16 pause_result; 7128 u16 ld_pause; /* local */ 7129 u16 lp_pause; /* link partner */ 7130 bnx2x_cl45_read(bp, phy, 7131 MDIO_AN_DEVAD, 7132 MDIO_AN_REG_CL37_FC_LD, &ld_pause); 7133 7134 bnx2x_cl45_read(bp, phy, 7135 MDIO_AN_DEVAD, 7136 MDIO_AN_REG_CL37_FC_LP, &lp_pause); 7137 pause_result = (ld_pause & 7138 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 5; 7139 pause_result |= (lp_pause & 7140 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 7; 7141 7142 bnx2x_pause_resolve(phy, params, vars, pause_result); 7143 DP(NETIF_MSG_LINK, "Ext PHY CL37 pause result 0x%x\n", 7144 pause_result); 7145 } 7146 } 7147 static int bnx2x_8073_8727_external_rom_boot(struct bnx2x *bp, 7148 struct bnx2x_phy *phy, 7149 u8 port) 7150 { 7151 u32 count = 0; 7152 u16 fw_ver1, fw_msgout; 7153 int rc = 0; 7154 7155 /* Boot port from external ROM */ 7156 /* EDC grst */ 7157 bnx2x_cl45_write(bp, phy, 7158 MDIO_PMA_DEVAD, 7159 MDIO_PMA_REG_GEN_CTRL, 7160 0x0001); 7161 7162 /* Ucode reboot and rst */ 7163 bnx2x_cl45_write(bp, phy, 7164 MDIO_PMA_DEVAD, 7165 MDIO_PMA_REG_GEN_CTRL, 7166 0x008c); 7167 7168 bnx2x_cl45_write(bp, phy, 7169 MDIO_PMA_DEVAD, 7170 MDIO_PMA_REG_MISC_CTRL1, 0x0001); 7171 7172 /* Reset internal microprocessor */ 7173 bnx2x_cl45_write(bp, phy, 7174 MDIO_PMA_DEVAD, 7175 MDIO_PMA_REG_GEN_CTRL, 7176 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET); 7177 7178 /* Release srst bit */ 7179 bnx2x_cl45_write(bp, phy, 7180 MDIO_PMA_DEVAD, 7181 MDIO_PMA_REG_GEN_CTRL, 7182 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP); 7183 7184 /* Delay 100ms per the PHY specifications */ 7185 msleep(100); 7186 7187 /* 8073 sometimes taking longer to download */ 7188 do { 7189 count++; 7190 if (count > 300) { 7191 DP(NETIF_MSG_LINK, 7192 "bnx2x_8073_8727_external_rom_boot port %x:" 7193 "Download failed. fw version = 0x%x\n", 7194 port, fw_ver1); 7195 rc = -EINVAL; 7196 break; 7197 } 7198 7199 bnx2x_cl45_read(bp, phy, 7200 MDIO_PMA_DEVAD, 7201 MDIO_PMA_REG_ROM_VER1, &fw_ver1); 7202 bnx2x_cl45_read(bp, phy, 7203 MDIO_PMA_DEVAD, 7204 MDIO_PMA_REG_M8051_MSGOUT_REG, &fw_msgout); 7205 7206 usleep_range(1000, 2000); 7207 } while (fw_ver1 == 0 || fw_ver1 == 0x4321 || 7208 ((fw_msgout & 0xff) != 0x03 && (phy->type == 7209 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073))); 7210 7211 /* Clear ser_boot_ctl bit */ 7212 bnx2x_cl45_write(bp, phy, 7213 MDIO_PMA_DEVAD, 7214 MDIO_PMA_REG_MISC_CTRL1, 0x0000); 7215 bnx2x_save_bcm_spirom_ver(bp, phy, port); 7216 7217 DP(NETIF_MSG_LINK, 7218 "bnx2x_8073_8727_external_rom_boot port %x:" 7219 "Download complete. fw version = 0x%x\n", 7220 port, fw_ver1); 7221 7222 return rc; 7223 } 7224 7225 /******************************************************************/ 7226 /* BCM8073 PHY SECTION */ 7227 /******************************************************************/ 7228 static int bnx2x_8073_is_snr_needed(struct bnx2x *bp, struct bnx2x_phy *phy) 7229 { 7230 /* This is only required for 8073A1, version 102 only */ 7231 u16 val; 7232 7233 /* Read 8073 HW revision*/ 7234 bnx2x_cl45_read(bp, phy, 7235 MDIO_PMA_DEVAD, 7236 MDIO_PMA_REG_8073_CHIP_REV, &val); 7237 7238 if (val != 1) { 7239 /* No need to workaround in 8073 A1 */ 7240 return 0; 7241 } 7242 7243 bnx2x_cl45_read(bp, phy, 7244 MDIO_PMA_DEVAD, 7245 MDIO_PMA_REG_ROM_VER2, &val); 7246 7247 /* SNR should be applied only for version 0x102 */ 7248 if (val != 0x102) 7249 return 0; 7250 7251 return 1; 7252 } 7253 7254 static int bnx2x_8073_xaui_wa(struct bnx2x *bp, struct bnx2x_phy *phy) 7255 { 7256 u16 val, cnt, cnt1 ; 7257 7258 bnx2x_cl45_read(bp, phy, 7259 MDIO_PMA_DEVAD, 7260 MDIO_PMA_REG_8073_CHIP_REV, &val); 7261 7262 if (val > 0) { 7263 /* No need to workaround in 8073 A1 */ 7264 return 0; 7265 } 7266 /* XAUI workaround in 8073 A0: */ 7267 7268 /* After loading the boot ROM and restarting Autoneg, poll 7269 * Dev1, Reg $C820: 7270 */ 7271 7272 for (cnt = 0; cnt < 1000; cnt++) { 7273 bnx2x_cl45_read(bp, phy, 7274 MDIO_PMA_DEVAD, 7275 MDIO_PMA_REG_8073_SPEED_LINK_STATUS, 7276 &val); 7277 /* If bit [14] = 0 or bit [13] = 0, continue on with 7278 * system initialization (XAUI work-around not required, as 7279 * these bits indicate 2.5G or 1G link up). 7280 */ 7281 if (!(val & (1<<14)) || !(val & (1<<13))) { 7282 DP(NETIF_MSG_LINK, "XAUI work-around not required\n"); 7283 return 0; 7284 } else if (!(val & (1<<15))) { 7285 DP(NETIF_MSG_LINK, "bit 15 went off\n"); 7286 /* If bit 15 is 0, then poll Dev1, Reg $C841 until it's 7287 * MSB (bit15) goes to 1 (indicating that the XAUI 7288 * workaround has completed), then continue on with 7289 * system initialization. 7290 */ 7291 for (cnt1 = 0; cnt1 < 1000; cnt1++) { 7292 bnx2x_cl45_read(bp, phy, 7293 MDIO_PMA_DEVAD, 7294 MDIO_PMA_REG_8073_XAUI_WA, &val); 7295 if (val & (1<<15)) { 7296 DP(NETIF_MSG_LINK, 7297 "XAUI workaround has completed\n"); 7298 return 0; 7299 } 7300 usleep_range(3000, 6000); 7301 } 7302 break; 7303 } 7304 usleep_range(3000, 6000); 7305 } 7306 DP(NETIF_MSG_LINK, "Warning: XAUI work-around timeout !!!\n"); 7307 return -EINVAL; 7308 } 7309 7310 static void bnx2x_807x_force_10G(struct bnx2x *bp, struct bnx2x_phy *phy) 7311 { 7312 /* Force KR or KX */ 7313 bnx2x_cl45_write(bp, phy, 7314 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040); 7315 bnx2x_cl45_write(bp, phy, 7316 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0x000b); 7317 bnx2x_cl45_write(bp, phy, 7318 MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0000); 7319 bnx2x_cl45_write(bp, phy, 7320 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000); 7321 } 7322 7323 static void bnx2x_8073_set_pause_cl37(struct link_params *params, 7324 struct bnx2x_phy *phy, 7325 struct link_vars *vars) 7326 { 7327 u16 cl37_val; 7328 struct bnx2x *bp = params->bp; 7329 bnx2x_cl45_read(bp, phy, 7330 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &cl37_val); 7331 7332 cl37_val &= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; 7333 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */ 7334 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); 7335 if ((vars->ieee_fc & 7336 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) == 7337 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) { 7338 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC; 7339 } 7340 if ((vars->ieee_fc & 7341 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) == 7342 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) { 7343 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC; 7344 } 7345 if ((vars->ieee_fc & 7346 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) == 7347 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) { 7348 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; 7349 } 7350 DP(NETIF_MSG_LINK, 7351 "Ext phy AN advertize cl37 0x%x\n", cl37_val); 7352 7353 bnx2x_cl45_write(bp, phy, 7354 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, cl37_val); 7355 msleep(500); 7356 } 7357 7358 static void bnx2x_8073_specific_func(struct bnx2x_phy *phy, 7359 struct link_params *params, 7360 u32 action) 7361 { 7362 struct bnx2x *bp = params->bp; 7363 switch (action) { 7364 case PHY_INIT: 7365 /* Enable LASI */ 7366 bnx2x_cl45_write(bp, phy, 7367 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, (1<<2)); 7368 bnx2x_cl45_write(bp, phy, 7369 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0004); 7370 break; 7371 } 7372 } 7373 7374 static void bnx2x_8073_config_init(struct bnx2x_phy *phy, 7375 struct link_params *params, 7376 struct link_vars *vars) 7377 { 7378 struct bnx2x *bp = params->bp; 7379 u16 val = 0, tmp1; 7380 u8 gpio_port; 7381 DP(NETIF_MSG_LINK, "Init 8073\n"); 7382 7383 if (CHIP_IS_E2(bp)) 7384 gpio_port = BP_PATH(bp); 7385 else 7386 gpio_port = params->port; 7387 /* Restore normal power mode*/ 7388 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 7389 MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port); 7390 7391 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, 7392 MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port); 7393 7394 bnx2x_8073_specific_func(phy, params, PHY_INIT); 7395 bnx2x_8073_set_pause_cl37(params, phy, vars); 7396 7397 bnx2x_cl45_read(bp, phy, 7398 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1); 7399 7400 bnx2x_cl45_read(bp, phy, 7401 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1); 7402 7403 DP(NETIF_MSG_LINK, "Before rom RX_ALARM(port1): 0x%x\n", tmp1); 7404 7405 /* Swap polarity if required - Must be done only in non-1G mode */ 7406 if (params->lane_config & PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) { 7407 /* Configure the 8073 to swap _P and _N of the KR lines */ 7408 DP(NETIF_MSG_LINK, "Swapping polarity for the 8073\n"); 7409 /* 10G Rx/Tx and 1G Tx signal polarity swap */ 7410 bnx2x_cl45_read(bp, phy, 7411 MDIO_PMA_DEVAD, 7412 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL, &val); 7413 bnx2x_cl45_write(bp, phy, 7414 MDIO_PMA_DEVAD, 7415 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL, 7416 (val | (3<<9))); 7417 } 7418 7419 7420 /* Enable CL37 BAM */ 7421 if (REG_RD(bp, params->shmem_base + 7422 offsetof(struct shmem_region, dev_info. 7423 port_hw_config[params->port].default_cfg)) & 7424 PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) { 7425 7426 bnx2x_cl45_read(bp, phy, 7427 MDIO_AN_DEVAD, 7428 MDIO_AN_REG_8073_BAM, &val); 7429 bnx2x_cl45_write(bp, phy, 7430 MDIO_AN_DEVAD, 7431 MDIO_AN_REG_8073_BAM, val | 1); 7432 DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n"); 7433 } 7434 if (params->loopback_mode == LOOPBACK_EXT) { 7435 bnx2x_807x_force_10G(bp, phy); 7436 DP(NETIF_MSG_LINK, "Forced speed 10G on 807X\n"); 7437 return; 7438 } else { 7439 bnx2x_cl45_write(bp, phy, 7440 MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0002); 7441 } 7442 if (phy->req_line_speed != SPEED_AUTO_NEG) { 7443 if (phy->req_line_speed == SPEED_10000) { 7444 val = (1<<7); 7445 } else if (phy->req_line_speed == SPEED_2500) { 7446 val = (1<<5); 7447 /* Note that 2.5G works only when used with 1G 7448 * advertisement 7449 */ 7450 } else 7451 val = (1<<5); 7452 } else { 7453 val = 0; 7454 if (phy->speed_cap_mask & 7455 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) 7456 val |= (1<<7); 7457 7458 /* Note that 2.5G works only when used with 1G advertisement */ 7459 if (phy->speed_cap_mask & 7460 (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G | 7461 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) 7462 val |= (1<<5); 7463 DP(NETIF_MSG_LINK, "807x autoneg val = 0x%x\n", val); 7464 } 7465 7466 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val); 7467 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, &tmp1); 7468 7469 if (((phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) && 7470 (phy->req_line_speed == SPEED_AUTO_NEG)) || 7471 (phy->req_line_speed == SPEED_2500)) { 7472 u16 phy_ver; 7473 /* Allow 2.5G for A1 and above */ 7474 bnx2x_cl45_read(bp, phy, 7475 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV, 7476 &phy_ver); 7477 DP(NETIF_MSG_LINK, "Add 2.5G\n"); 7478 if (phy_ver > 0) 7479 tmp1 |= 1; 7480 else 7481 tmp1 &= 0xfffe; 7482 } else { 7483 DP(NETIF_MSG_LINK, "Disable 2.5G\n"); 7484 tmp1 &= 0xfffe; 7485 } 7486 7487 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, tmp1); 7488 /* Add support for CL37 (passive mode) II */ 7489 7490 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &tmp1); 7491 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, 7492 (tmp1 | ((phy->req_duplex == DUPLEX_FULL) ? 7493 0x20 : 0x40))); 7494 7495 /* Add support for CL37 (passive mode) III */ 7496 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000); 7497 7498 /* The SNR will improve about 2db by changing BW and FEE main 7499 * tap. Rest commands are executed after link is up 7500 * Change FFE main cursor to 5 in EDC register 7501 */ 7502 if (bnx2x_8073_is_snr_needed(bp, phy)) 7503 bnx2x_cl45_write(bp, phy, 7504 MDIO_PMA_DEVAD, MDIO_PMA_REG_EDC_FFE_MAIN, 7505 0xFB0C); 7506 7507 /* Enable FEC (Forware Error Correction) Request in the AN */ 7508 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, &tmp1); 7509 tmp1 |= (1<<15); 7510 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, tmp1); 7511 7512 bnx2x_ext_phy_set_pause(params, phy, vars); 7513 7514 /* Restart autoneg */ 7515 msleep(500); 7516 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200); 7517 DP(NETIF_MSG_LINK, "807x Autoneg Restart: Advertise 1G=%x, 10G=%x\n", 7518 ((val & (1<<5)) > 0), ((val & (1<<7)) > 0)); 7519 } 7520 7521 static u8 bnx2x_8073_read_status(struct bnx2x_phy *phy, 7522 struct link_params *params, 7523 struct link_vars *vars) 7524 { 7525 struct bnx2x *bp = params->bp; 7526 u8 link_up = 0; 7527 u16 val1, val2; 7528 u16 link_status = 0; 7529 u16 an1000_status = 0; 7530 7531 bnx2x_cl45_read(bp, phy, 7532 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1); 7533 7534 DP(NETIF_MSG_LINK, "8703 LASI status 0x%x\n", val1); 7535 7536 /* Clear the interrupt LASI status register */ 7537 bnx2x_cl45_read(bp, phy, 7538 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2); 7539 bnx2x_cl45_read(bp, phy, 7540 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val1); 7541 DP(NETIF_MSG_LINK, "807x PCS status 0x%x->0x%x\n", val2, val1); 7542 /* Clear MSG-OUT */ 7543 bnx2x_cl45_read(bp, phy, 7544 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1); 7545 7546 /* Check the LASI */ 7547 bnx2x_cl45_read(bp, phy, 7548 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2); 7549 7550 DP(NETIF_MSG_LINK, "KR 0x9003 0x%x\n", val2); 7551 7552 /* Check the link status */ 7553 bnx2x_cl45_read(bp, phy, 7554 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2); 7555 DP(NETIF_MSG_LINK, "KR PCS status 0x%x\n", val2); 7556 7557 bnx2x_cl45_read(bp, phy, 7558 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2); 7559 bnx2x_cl45_read(bp, phy, 7560 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1); 7561 link_up = ((val1 & 4) == 4); 7562 DP(NETIF_MSG_LINK, "PMA_REG_STATUS=0x%x\n", val1); 7563 7564 if (link_up && 7565 ((phy->req_line_speed != SPEED_10000))) { 7566 if (bnx2x_8073_xaui_wa(bp, phy) != 0) 7567 return 0; 7568 } 7569 bnx2x_cl45_read(bp, phy, 7570 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status); 7571 bnx2x_cl45_read(bp, phy, 7572 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status); 7573 7574 /* Check the link status on 1.1.2 */ 7575 bnx2x_cl45_read(bp, phy, 7576 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2); 7577 bnx2x_cl45_read(bp, phy, 7578 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1); 7579 DP(NETIF_MSG_LINK, "KR PMA status 0x%x->0x%x," 7580 "an_link_status=0x%x\n", val2, val1, an1000_status); 7581 7582 link_up = (((val1 & 4) == 4) || (an1000_status & (1<<1))); 7583 if (link_up && bnx2x_8073_is_snr_needed(bp, phy)) { 7584 /* The SNR will improve about 2dbby changing the BW and FEE main 7585 * tap. The 1st write to change FFE main tap is set before 7586 * restart AN. Change PLL Bandwidth in EDC register 7587 */ 7588 bnx2x_cl45_write(bp, phy, 7589 MDIO_PMA_DEVAD, MDIO_PMA_REG_PLL_BANDWIDTH, 7590 0x26BC); 7591 7592 /* Change CDR Bandwidth in EDC register */ 7593 bnx2x_cl45_write(bp, phy, 7594 MDIO_PMA_DEVAD, MDIO_PMA_REG_CDR_BANDWIDTH, 7595 0x0333); 7596 } 7597 bnx2x_cl45_read(bp, phy, 7598 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_SPEED_LINK_STATUS, 7599 &link_status); 7600 7601 /* Bits 0..2 --> speed detected, bits 13..15--> link is down */ 7602 if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) { 7603 link_up = 1; 7604 vars->line_speed = SPEED_10000; 7605 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n", 7606 params->port); 7607 } else if ((link_status & (1<<1)) && (!(link_status & (1<<14)))) { 7608 link_up = 1; 7609 vars->line_speed = SPEED_2500; 7610 DP(NETIF_MSG_LINK, "port %x: External link up in 2.5G\n", 7611 params->port); 7612 } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) { 7613 link_up = 1; 7614 vars->line_speed = SPEED_1000; 7615 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n", 7616 params->port); 7617 } else { 7618 link_up = 0; 7619 DP(NETIF_MSG_LINK, "port %x: External link is down\n", 7620 params->port); 7621 } 7622 7623 if (link_up) { 7624 /* Swap polarity if required */ 7625 if (params->lane_config & 7626 PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) { 7627 /* Configure the 8073 to swap P and N of the KR lines */ 7628 bnx2x_cl45_read(bp, phy, 7629 MDIO_XS_DEVAD, 7630 MDIO_XS_REG_8073_RX_CTRL_PCIE, &val1); 7631 /* Set bit 3 to invert Rx in 1G mode and clear this bit 7632 * when it`s in 10G mode. 7633 */ 7634 if (vars->line_speed == SPEED_1000) { 7635 DP(NETIF_MSG_LINK, "Swapping 1G polarity for" 7636 "the 8073\n"); 7637 val1 |= (1<<3); 7638 } else 7639 val1 &= ~(1<<3); 7640 7641 bnx2x_cl45_write(bp, phy, 7642 MDIO_XS_DEVAD, 7643 MDIO_XS_REG_8073_RX_CTRL_PCIE, 7644 val1); 7645 } 7646 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars); 7647 bnx2x_8073_resolve_fc(phy, params, vars); 7648 vars->duplex = DUPLEX_FULL; 7649 } 7650 7651 if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) { 7652 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, 7653 MDIO_AN_REG_LP_AUTO_NEG2, &val1); 7654 7655 if (val1 & (1<<5)) 7656 vars->link_status |= 7657 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; 7658 if (val1 & (1<<7)) 7659 vars->link_status |= 7660 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; 7661 } 7662 7663 return link_up; 7664 } 7665 7666 static void bnx2x_8073_link_reset(struct bnx2x_phy *phy, 7667 struct link_params *params) 7668 { 7669 struct bnx2x *bp = params->bp; 7670 u8 gpio_port; 7671 if (CHIP_IS_E2(bp)) 7672 gpio_port = BP_PATH(bp); 7673 else 7674 gpio_port = params->port; 7675 DP(NETIF_MSG_LINK, "Setting 8073 port %d into low power mode\n", 7676 gpio_port); 7677 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 7678 MISC_REGISTERS_GPIO_OUTPUT_LOW, 7679 gpio_port); 7680 } 7681 7682 /******************************************************************/ 7683 /* BCM8705 PHY SECTION */ 7684 /******************************************************************/ 7685 static void bnx2x_8705_config_init(struct bnx2x_phy *phy, 7686 struct link_params *params, 7687 struct link_vars *vars) 7688 { 7689 struct bnx2x *bp = params->bp; 7690 DP(NETIF_MSG_LINK, "init 8705\n"); 7691 /* Restore normal power mode*/ 7692 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 7693 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); 7694 /* HW reset */ 7695 bnx2x_ext_phy_hw_reset(bp, params->port); 7696 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040); 7697 bnx2x_wait_reset_complete(bp, phy, params); 7698 7699 bnx2x_cl45_write(bp, phy, 7700 MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL, 0x8288); 7701 bnx2x_cl45_write(bp, phy, 7702 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 0x7fbf); 7703 bnx2x_cl45_write(bp, phy, 7704 MDIO_PMA_DEVAD, MDIO_PMA_REG_CMU_PLL_BYPASS, 0x0100); 7705 bnx2x_cl45_write(bp, phy, 7706 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_CNTL, 0x1); 7707 /* BCM8705 doesn't have microcode, hence the 0 */ 7708 bnx2x_save_spirom_version(bp, params->port, params->shmem_base, 0); 7709 } 7710 7711 static u8 bnx2x_8705_read_status(struct bnx2x_phy *phy, 7712 struct link_params *params, 7713 struct link_vars *vars) 7714 { 7715 u8 link_up = 0; 7716 u16 val1, rx_sd; 7717 struct bnx2x *bp = params->bp; 7718 DP(NETIF_MSG_LINK, "read status 8705\n"); 7719 bnx2x_cl45_read(bp, phy, 7720 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1); 7721 DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1); 7722 7723 bnx2x_cl45_read(bp, phy, 7724 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1); 7725 DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1); 7726 7727 bnx2x_cl45_read(bp, phy, 7728 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd); 7729 7730 bnx2x_cl45_read(bp, phy, 7731 MDIO_PMA_DEVAD, 0xc809, &val1); 7732 bnx2x_cl45_read(bp, phy, 7733 MDIO_PMA_DEVAD, 0xc809, &val1); 7734 7735 DP(NETIF_MSG_LINK, "8705 1.c809 val=0x%x\n", val1); 7736 link_up = ((rx_sd & 0x1) && (val1 & (1<<9)) && ((val1 & (1<<8)) == 0)); 7737 if (link_up) { 7738 vars->line_speed = SPEED_10000; 7739 bnx2x_ext_phy_resolve_fc(phy, params, vars); 7740 } 7741 return link_up; 7742 } 7743 7744 /******************************************************************/ 7745 /* SFP+ module Section */ 7746 /******************************************************************/ 7747 static void bnx2x_set_disable_pmd_transmit(struct link_params *params, 7748 struct bnx2x_phy *phy, 7749 u8 pmd_dis) 7750 { 7751 struct bnx2x *bp = params->bp; 7752 /* Disable transmitter only for bootcodes which can enable it afterwards 7753 * (for D3 link) 7754 */ 7755 if (pmd_dis) { 7756 if (params->feature_config_flags & 7757 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED) 7758 DP(NETIF_MSG_LINK, "Disabling PMD transmitter\n"); 7759 else { 7760 DP(NETIF_MSG_LINK, "NOT disabling PMD transmitter\n"); 7761 return; 7762 } 7763 } else 7764 DP(NETIF_MSG_LINK, "Enabling PMD transmitter\n"); 7765 bnx2x_cl45_write(bp, phy, 7766 MDIO_PMA_DEVAD, 7767 MDIO_PMA_REG_TX_DISABLE, pmd_dis); 7768 } 7769 7770 static u8 bnx2x_get_gpio_port(struct link_params *params) 7771 { 7772 u8 gpio_port; 7773 u32 swap_val, swap_override; 7774 struct bnx2x *bp = params->bp; 7775 if (CHIP_IS_E2(bp)) 7776 gpio_port = BP_PATH(bp); 7777 else 7778 gpio_port = params->port; 7779 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); 7780 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); 7781 return gpio_port ^ (swap_val && swap_override); 7782 } 7783 7784 static void bnx2x_sfp_e1e2_set_transmitter(struct link_params *params, 7785 struct bnx2x_phy *phy, 7786 u8 tx_en) 7787 { 7788 u16 val; 7789 u8 port = params->port; 7790 struct bnx2x *bp = params->bp; 7791 u32 tx_en_mode; 7792 7793 /* Disable/Enable transmitter ( TX laser of the SFP+ module.)*/ 7794 tx_en_mode = REG_RD(bp, params->shmem_base + 7795 offsetof(struct shmem_region, 7796 dev_info.port_hw_config[port].sfp_ctrl)) & 7797 PORT_HW_CFG_TX_LASER_MASK; 7798 DP(NETIF_MSG_LINK, "Setting transmitter tx_en=%x for port %x " 7799 "mode = %x\n", tx_en, port, tx_en_mode); 7800 switch (tx_en_mode) { 7801 case PORT_HW_CFG_TX_LASER_MDIO: 7802 7803 bnx2x_cl45_read(bp, phy, 7804 MDIO_PMA_DEVAD, 7805 MDIO_PMA_REG_PHY_IDENTIFIER, 7806 &val); 7807 7808 if (tx_en) 7809 val &= ~(1<<15); 7810 else 7811 val |= (1<<15); 7812 7813 bnx2x_cl45_write(bp, phy, 7814 MDIO_PMA_DEVAD, 7815 MDIO_PMA_REG_PHY_IDENTIFIER, 7816 val); 7817 break; 7818 case PORT_HW_CFG_TX_LASER_GPIO0: 7819 case PORT_HW_CFG_TX_LASER_GPIO1: 7820 case PORT_HW_CFG_TX_LASER_GPIO2: 7821 case PORT_HW_CFG_TX_LASER_GPIO3: 7822 { 7823 u16 gpio_pin; 7824 u8 gpio_port, gpio_mode; 7825 if (tx_en) 7826 gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_HIGH; 7827 else 7828 gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_LOW; 7829 7830 gpio_pin = tx_en_mode - PORT_HW_CFG_TX_LASER_GPIO0; 7831 gpio_port = bnx2x_get_gpio_port(params); 7832 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port); 7833 break; 7834 } 7835 default: 7836 DP(NETIF_MSG_LINK, "Invalid TX_LASER_MDIO 0x%x\n", tx_en_mode); 7837 break; 7838 } 7839 } 7840 7841 static void bnx2x_sfp_set_transmitter(struct link_params *params, 7842 struct bnx2x_phy *phy, 7843 u8 tx_en) 7844 { 7845 struct bnx2x *bp = params->bp; 7846 DP(NETIF_MSG_LINK, "Setting SFP+ transmitter to %d\n", tx_en); 7847 if (CHIP_IS_E3(bp)) 7848 bnx2x_sfp_e3_set_transmitter(params, phy, tx_en); 7849 else 7850 bnx2x_sfp_e1e2_set_transmitter(params, phy, tx_en); 7851 } 7852 7853 static int bnx2x_8726_read_sfp_module_eeprom(struct bnx2x_phy *phy, 7854 struct link_params *params, 7855 u8 dev_addr, u16 addr, u8 byte_cnt, 7856 u8 *o_buf, u8 is_init) 7857 { 7858 struct bnx2x *bp = params->bp; 7859 u16 val = 0; 7860 u16 i; 7861 if (byte_cnt > SFP_EEPROM_PAGE_SIZE) { 7862 DP(NETIF_MSG_LINK, 7863 "Reading from eeprom is limited to 0xf\n"); 7864 return -EINVAL; 7865 } 7866 /* Set the read command byte count */ 7867 bnx2x_cl45_write(bp, phy, 7868 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT, 7869 (byte_cnt | (dev_addr << 8))); 7870 7871 /* Set the read command address */ 7872 bnx2x_cl45_write(bp, phy, 7873 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR, 7874 addr); 7875 7876 /* Activate read command */ 7877 bnx2x_cl45_write(bp, phy, 7878 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, 7879 0x2c0f); 7880 7881 /* Wait up to 500us for command complete status */ 7882 for (i = 0; i < 100; i++) { 7883 bnx2x_cl45_read(bp, phy, 7884 MDIO_PMA_DEVAD, 7885 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); 7886 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == 7887 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) 7888 break; 7889 udelay(5); 7890 } 7891 7892 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) != 7893 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) { 7894 DP(NETIF_MSG_LINK, 7895 "Got bad status 0x%x when reading from SFP+ EEPROM\n", 7896 (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK)); 7897 return -EINVAL; 7898 } 7899 7900 /* Read the buffer */ 7901 for (i = 0; i < byte_cnt; i++) { 7902 bnx2x_cl45_read(bp, phy, 7903 MDIO_PMA_DEVAD, 7904 MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i, &val); 7905 o_buf[i] = (u8)(val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK); 7906 } 7907 7908 for (i = 0; i < 100; i++) { 7909 bnx2x_cl45_read(bp, phy, 7910 MDIO_PMA_DEVAD, 7911 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); 7912 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == 7913 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE) 7914 return 0; 7915 usleep_range(1000, 2000); 7916 } 7917 return -EINVAL; 7918 } 7919 7920 static void bnx2x_warpcore_power_module(struct link_params *params, 7921 u8 power) 7922 { 7923 u32 pin_cfg; 7924 struct bnx2x *bp = params->bp; 7925 7926 pin_cfg = (REG_RD(bp, params->shmem_base + 7927 offsetof(struct shmem_region, 7928 dev_info.port_hw_config[params->port].e3_sfp_ctrl)) & 7929 PORT_HW_CFG_E3_PWR_DIS_MASK) >> 7930 PORT_HW_CFG_E3_PWR_DIS_SHIFT; 7931 7932 if (pin_cfg == PIN_CFG_NA) 7933 return; 7934 DP(NETIF_MSG_LINK, "Setting SFP+ module power to %d using pin cfg %d\n", 7935 power, pin_cfg); 7936 /* Low ==> corresponding SFP+ module is powered 7937 * high ==> the SFP+ module is powered down 7938 */ 7939 bnx2x_set_cfg_pin(bp, pin_cfg, power ^ 1); 7940 } 7941 static int bnx2x_warpcore_read_sfp_module_eeprom(struct bnx2x_phy *phy, 7942 struct link_params *params, 7943 u8 dev_addr, 7944 u16 addr, u8 byte_cnt, 7945 u8 *o_buf, u8 is_init) 7946 { 7947 int rc = 0; 7948 u8 i, j = 0, cnt = 0; 7949 u32 data_array[4]; 7950 u16 addr32; 7951 struct bnx2x *bp = params->bp; 7952 7953 if (byte_cnt > SFP_EEPROM_PAGE_SIZE) { 7954 DP(NETIF_MSG_LINK, 7955 "Reading from eeprom is limited to 16 bytes\n"); 7956 return -EINVAL; 7957 } 7958 7959 /* 4 byte aligned address */ 7960 addr32 = addr & (~0x3); 7961 do { 7962 if ((!is_init) && (cnt == I2C_WA_PWR_ITER)) { 7963 bnx2x_warpcore_power_module(params, 0); 7964 /* Note that 100us are not enough here */ 7965 usleep_range(1000, 2000); 7966 bnx2x_warpcore_power_module(params, 1); 7967 } 7968 rc = bnx2x_bsc_read(params, bp, dev_addr, addr32, 0, byte_cnt, 7969 data_array); 7970 } while ((rc != 0) && (++cnt < I2C_WA_RETRY_CNT)); 7971 7972 if (rc == 0) { 7973 for (i = (addr - addr32); i < byte_cnt + (addr - addr32); i++) { 7974 o_buf[j] = *((u8 *)data_array + i); 7975 j++; 7976 } 7977 } 7978 7979 return rc; 7980 } 7981 7982 static int bnx2x_8727_read_sfp_module_eeprom(struct bnx2x_phy *phy, 7983 struct link_params *params, 7984 u8 dev_addr, u16 addr, u8 byte_cnt, 7985 u8 *o_buf, u8 is_init) 7986 { 7987 struct bnx2x *bp = params->bp; 7988 u16 val, i; 7989 7990 if (byte_cnt > SFP_EEPROM_PAGE_SIZE) { 7991 DP(NETIF_MSG_LINK, 7992 "Reading from eeprom is limited to 0xf\n"); 7993 return -EINVAL; 7994 } 7995 7996 /* Set 2-wire transfer rate of SFP+ module EEPROM 7997 * to 100Khz since some DACs(direct attached cables) do 7998 * not work at 400Khz. 7999 */ 8000 bnx2x_cl45_write(bp, phy, 8001 MDIO_PMA_DEVAD, 8002 MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR, 8003 ((dev_addr << 8) | 1)); 8004 8005 /* Need to read from 1.8000 to clear it */ 8006 bnx2x_cl45_read(bp, phy, 8007 MDIO_PMA_DEVAD, 8008 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, 8009 &val); 8010 8011 /* Set the read command byte count */ 8012 bnx2x_cl45_write(bp, phy, 8013 MDIO_PMA_DEVAD, 8014 MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT, 8015 ((byte_cnt < 2) ? 2 : byte_cnt)); 8016 8017 /* Set the read command address */ 8018 bnx2x_cl45_write(bp, phy, 8019 MDIO_PMA_DEVAD, 8020 MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR, 8021 addr); 8022 /* Set the destination address */ 8023 bnx2x_cl45_write(bp, phy, 8024 MDIO_PMA_DEVAD, 8025 0x8004, 8026 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF); 8027 8028 /* Activate read command */ 8029 bnx2x_cl45_write(bp, phy, 8030 MDIO_PMA_DEVAD, 8031 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, 8032 0x8002); 8033 /* Wait appropriate time for two-wire command to finish before 8034 * polling the status register 8035 */ 8036 usleep_range(1000, 2000); 8037 8038 /* Wait up to 500us for command complete status */ 8039 for (i = 0; i < 100; i++) { 8040 bnx2x_cl45_read(bp, phy, 8041 MDIO_PMA_DEVAD, 8042 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); 8043 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == 8044 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) 8045 break; 8046 udelay(5); 8047 } 8048 8049 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) != 8050 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) { 8051 DP(NETIF_MSG_LINK, 8052 "Got bad status 0x%x when reading from SFP+ EEPROM\n", 8053 (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK)); 8054 return -EFAULT; 8055 } 8056 8057 /* Read the buffer */ 8058 for (i = 0; i < byte_cnt; i++) { 8059 bnx2x_cl45_read(bp, phy, 8060 MDIO_PMA_DEVAD, 8061 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF + i, &val); 8062 o_buf[i] = (u8)(val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK); 8063 } 8064 8065 for (i = 0; i < 100; i++) { 8066 bnx2x_cl45_read(bp, phy, 8067 MDIO_PMA_DEVAD, 8068 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); 8069 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == 8070 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE) 8071 return 0; 8072 usleep_range(1000, 2000); 8073 } 8074 8075 return -EINVAL; 8076 } 8077 int bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy, 8078 struct link_params *params, u8 dev_addr, 8079 u16 addr, u16 byte_cnt, u8 *o_buf) 8080 { 8081 int rc = 0; 8082 struct bnx2x *bp = params->bp; 8083 u8 xfer_size; 8084 u8 *user_data = o_buf; 8085 read_sfp_module_eeprom_func_p read_func; 8086 8087 if ((dev_addr != 0xa0) && (dev_addr != 0xa2)) { 8088 DP(NETIF_MSG_LINK, "invalid dev_addr 0x%x\n", dev_addr); 8089 return -EINVAL; 8090 } 8091 8092 switch (phy->type) { 8093 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: 8094 read_func = bnx2x_8726_read_sfp_module_eeprom; 8095 break; 8096 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: 8097 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722: 8098 read_func = bnx2x_8727_read_sfp_module_eeprom; 8099 break; 8100 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT: 8101 read_func = bnx2x_warpcore_read_sfp_module_eeprom; 8102 break; 8103 default: 8104 return -EOPNOTSUPP; 8105 } 8106 8107 while (!rc && (byte_cnt > 0)) { 8108 xfer_size = (byte_cnt > SFP_EEPROM_PAGE_SIZE) ? 8109 SFP_EEPROM_PAGE_SIZE : byte_cnt; 8110 rc = read_func(phy, params, dev_addr, addr, xfer_size, 8111 user_data, 0); 8112 byte_cnt -= xfer_size; 8113 user_data += xfer_size; 8114 addr += xfer_size; 8115 } 8116 return rc; 8117 } 8118 8119 static int bnx2x_get_edc_mode(struct bnx2x_phy *phy, 8120 struct link_params *params, 8121 u16 *edc_mode) 8122 { 8123 struct bnx2x *bp = params->bp; 8124 u32 sync_offset = 0, phy_idx, media_types; 8125 u8 val[SFP_EEPROM_FC_TX_TECH_ADDR + 1], check_limiting_mode = 0; 8126 *edc_mode = EDC_MODE_LIMITING; 8127 phy->media_type = ETH_PHY_UNSPECIFIED; 8128 /* First check for copper cable */ 8129 if (bnx2x_read_sfp_module_eeprom(phy, 8130 params, 8131 I2C_DEV_ADDR_A0, 8132 0, 8133 SFP_EEPROM_FC_TX_TECH_ADDR + 1, 8134 (u8 *)val) != 0) { 8135 DP(NETIF_MSG_LINK, "Failed to read from SFP+ module EEPROM\n"); 8136 return -EINVAL; 8137 } 8138 params->link_attr_sync &= ~LINK_SFP_EEPROM_COMP_CODE_MASK; 8139 params->link_attr_sync |= val[SFP_EEPROM_10G_COMP_CODE_ADDR] << 8140 LINK_SFP_EEPROM_COMP_CODE_SHIFT; 8141 bnx2x_update_link_attr(params, params->link_attr_sync); 8142 switch (val[SFP_EEPROM_CON_TYPE_ADDR]) { 8143 case SFP_EEPROM_CON_TYPE_VAL_COPPER: 8144 { 8145 u8 copper_module_type; 8146 phy->media_type = ETH_PHY_DA_TWINAX; 8147 /* Check if its active cable (includes SFP+ module) 8148 * of passive cable 8149 */ 8150 copper_module_type = val[SFP_EEPROM_FC_TX_TECH_ADDR]; 8151 8152 if (copper_module_type & 8153 SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) { 8154 DP(NETIF_MSG_LINK, "Active Copper cable detected\n"); 8155 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) 8156 *edc_mode = EDC_MODE_ACTIVE_DAC; 8157 else 8158 check_limiting_mode = 1; 8159 } else { 8160 *edc_mode = EDC_MODE_PASSIVE_DAC; 8161 /* Even in case PASSIVE_DAC indication is not set, 8162 * treat it as a passive DAC cable, since some cables 8163 * don't have this indication. 8164 */ 8165 if (copper_module_type & 8166 SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE) { 8167 DP(NETIF_MSG_LINK, 8168 "Passive Copper cable detected\n"); 8169 } else { 8170 DP(NETIF_MSG_LINK, 8171 "Unknown copper-cable-type\n"); 8172 } 8173 } 8174 break; 8175 } 8176 case SFP_EEPROM_CON_TYPE_VAL_UNKNOWN: 8177 case SFP_EEPROM_CON_TYPE_VAL_LC: 8178 case SFP_EEPROM_CON_TYPE_VAL_RJ45: 8179 check_limiting_mode = 1; 8180 if (((val[SFP_EEPROM_10G_COMP_CODE_ADDR] & 8181 (SFP_EEPROM_10G_COMP_CODE_SR_MASK | 8182 SFP_EEPROM_10G_COMP_CODE_LR_MASK | 8183 SFP_EEPROM_10G_COMP_CODE_LRM_MASK)) == 0) && 8184 (val[SFP_EEPROM_1G_COMP_CODE_ADDR] != 0)) { 8185 DP(NETIF_MSG_LINK, "1G SFP module detected\n"); 8186 phy->media_type = ETH_PHY_SFP_1G_FIBER; 8187 if (phy->req_line_speed != SPEED_1000) { 8188 u8 gport = params->port; 8189 phy->req_line_speed = SPEED_1000; 8190 if (!CHIP_IS_E1x(bp)) { 8191 gport = BP_PATH(bp) + 8192 (params->port << 1); 8193 } 8194 netdev_err(bp->dev, 8195 "Warning: Link speed was forced to 1000Mbps. Current SFP module in port %d is not compliant with 10G Ethernet\n", 8196 gport); 8197 } 8198 if (val[SFP_EEPROM_1G_COMP_CODE_ADDR] & 8199 SFP_EEPROM_1G_COMP_CODE_BASE_T) { 8200 bnx2x_sfp_set_transmitter(params, phy, 0); 8201 msleep(40); 8202 bnx2x_sfp_set_transmitter(params, phy, 1); 8203 } 8204 } else { 8205 int idx, cfg_idx = 0; 8206 DP(NETIF_MSG_LINK, "10G Optic module detected\n"); 8207 for (idx = INT_PHY; idx < MAX_PHYS; idx++) { 8208 if (params->phy[idx].type == phy->type) { 8209 cfg_idx = LINK_CONFIG_IDX(idx); 8210 break; 8211 } 8212 } 8213 phy->media_type = ETH_PHY_SFPP_10G_FIBER; 8214 phy->req_line_speed = params->req_line_speed[cfg_idx]; 8215 } 8216 break; 8217 default: 8218 DP(NETIF_MSG_LINK, "Unable to determine module type 0x%x !!!\n", 8219 val[SFP_EEPROM_CON_TYPE_ADDR]); 8220 return -EINVAL; 8221 } 8222 sync_offset = params->shmem_base + 8223 offsetof(struct shmem_region, 8224 dev_info.port_hw_config[params->port].media_type); 8225 media_types = REG_RD(bp, sync_offset); 8226 /* Update media type for non-PMF sync */ 8227 for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) { 8228 if (&(params->phy[phy_idx]) == phy) { 8229 media_types &= ~(PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK << 8230 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx)); 8231 media_types |= ((phy->media_type & 8232 PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) << 8233 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx)); 8234 break; 8235 } 8236 } 8237 REG_WR(bp, sync_offset, media_types); 8238 if (check_limiting_mode) { 8239 u8 options[SFP_EEPROM_OPTIONS_SIZE]; 8240 if (bnx2x_read_sfp_module_eeprom(phy, 8241 params, 8242 I2C_DEV_ADDR_A0, 8243 SFP_EEPROM_OPTIONS_ADDR, 8244 SFP_EEPROM_OPTIONS_SIZE, 8245 options) != 0) { 8246 DP(NETIF_MSG_LINK, 8247 "Failed to read Option field from module EEPROM\n"); 8248 return -EINVAL; 8249 } 8250 if ((options[0] & SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK)) 8251 *edc_mode = EDC_MODE_LINEAR; 8252 else 8253 *edc_mode = EDC_MODE_LIMITING; 8254 } 8255 DP(NETIF_MSG_LINK, "EDC mode is set to 0x%x\n", *edc_mode); 8256 return 0; 8257 } 8258 /* This function read the relevant field from the module (SFP+), and verify it 8259 * is compliant with this board 8260 */ 8261 static int bnx2x_verify_sfp_module(struct bnx2x_phy *phy, 8262 struct link_params *params) 8263 { 8264 struct bnx2x *bp = params->bp; 8265 u32 val, cmd; 8266 u32 fw_resp, fw_cmd_param; 8267 char vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE+1]; 8268 char vendor_pn[SFP_EEPROM_PART_NO_SIZE+1]; 8269 phy->flags &= ~FLAGS_SFP_NOT_APPROVED; 8270 val = REG_RD(bp, params->shmem_base + 8271 offsetof(struct shmem_region, dev_info. 8272 port_feature_config[params->port].config)); 8273 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == 8274 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT) { 8275 DP(NETIF_MSG_LINK, "NOT enforcing module verification\n"); 8276 return 0; 8277 } 8278 8279 if (params->feature_config_flags & 8280 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY) { 8281 /* Use specific phy request */ 8282 cmd = DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL; 8283 } else if (params->feature_config_flags & 8284 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY) { 8285 /* Use first phy request only in case of non-dual media*/ 8286 if (DUAL_MEDIA(params)) { 8287 DP(NETIF_MSG_LINK, 8288 "FW does not support OPT MDL verification\n"); 8289 return -EINVAL; 8290 } 8291 cmd = DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL; 8292 } else { 8293 /* No support in OPT MDL detection */ 8294 DP(NETIF_MSG_LINK, 8295 "FW does not support OPT MDL verification\n"); 8296 return -EINVAL; 8297 } 8298 8299 fw_cmd_param = FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl); 8300 fw_resp = bnx2x_fw_command(bp, cmd, fw_cmd_param); 8301 if (fw_resp == FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS) { 8302 DP(NETIF_MSG_LINK, "Approved module\n"); 8303 return 0; 8304 } 8305 8306 /* Format the warning message */ 8307 if (bnx2x_read_sfp_module_eeprom(phy, 8308 params, 8309 I2C_DEV_ADDR_A0, 8310 SFP_EEPROM_VENDOR_NAME_ADDR, 8311 SFP_EEPROM_VENDOR_NAME_SIZE, 8312 (u8 *)vendor_name)) 8313 vendor_name[0] = '\0'; 8314 else 8315 vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE] = '\0'; 8316 if (bnx2x_read_sfp_module_eeprom(phy, 8317 params, 8318 I2C_DEV_ADDR_A0, 8319 SFP_EEPROM_PART_NO_ADDR, 8320 SFP_EEPROM_PART_NO_SIZE, 8321 (u8 *)vendor_pn)) 8322 vendor_pn[0] = '\0'; 8323 else 8324 vendor_pn[SFP_EEPROM_PART_NO_SIZE] = '\0'; 8325 8326 netdev_err(bp->dev, "Warning: Unqualified SFP+ module detected," 8327 " Port %d from %s part number %s\n", 8328 params->port, vendor_name, vendor_pn); 8329 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) != 8330 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG) 8331 phy->flags |= FLAGS_SFP_NOT_APPROVED; 8332 return -EINVAL; 8333 } 8334 8335 static int bnx2x_wait_for_sfp_module_initialized(struct bnx2x_phy *phy, 8336 struct link_params *params) 8337 8338 { 8339 u8 val; 8340 int rc; 8341 struct bnx2x *bp = params->bp; 8342 u16 timeout; 8343 /* Initialization time after hot-plug may take up to 300ms for 8344 * some phys type ( e.g. JDSU ) 8345 */ 8346 8347 for (timeout = 0; timeout < 60; timeout++) { 8348 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) 8349 rc = bnx2x_warpcore_read_sfp_module_eeprom( 8350 phy, params, I2C_DEV_ADDR_A0, 1, 1, &val, 8351 1); 8352 else 8353 rc = bnx2x_read_sfp_module_eeprom(phy, params, 8354 I2C_DEV_ADDR_A0, 8355 1, 1, &val); 8356 if (rc == 0) { 8357 DP(NETIF_MSG_LINK, 8358 "SFP+ module initialization took %d ms\n", 8359 timeout * 5); 8360 return 0; 8361 } 8362 usleep_range(5000, 10000); 8363 } 8364 rc = bnx2x_read_sfp_module_eeprom(phy, params, I2C_DEV_ADDR_A0, 8365 1, 1, &val); 8366 return rc; 8367 } 8368 8369 static void bnx2x_8727_power_module(struct bnx2x *bp, 8370 struct bnx2x_phy *phy, 8371 u8 is_power_up) { 8372 /* Make sure GPIOs are not using for LED mode */ 8373 u16 val; 8374 /* In the GPIO register, bit 4 is use to determine if the GPIOs are 8375 * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for 8376 * output 8377 * Bits 0-1 determine the GPIOs value for OUTPUT in case bit 4 val is 0 8378 * Bits 8-9 determine the GPIOs value for INPUT in case bit 4 val is 1 8379 * where the 1st bit is the over-current(only input), and 2nd bit is 8380 * for power( only output ) 8381 * 8382 * In case of NOC feature is disabled and power is up, set GPIO control 8383 * as input to enable listening of over-current indication 8384 */ 8385 if (phy->flags & FLAGS_NOC) 8386 return; 8387 if (is_power_up) 8388 val = (1<<4); 8389 else 8390 /* Set GPIO control to OUTPUT, and set the power bit 8391 * to according to the is_power_up 8392 */ 8393 val = (1<<1); 8394 8395 bnx2x_cl45_write(bp, phy, 8396 MDIO_PMA_DEVAD, 8397 MDIO_PMA_REG_8727_GPIO_CTRL, 8398 val); 8399 } 8400 8401 static int bnx2x_8726_set_limiting_mode(struct bnx2x *bp, 8402 struct bnx2x_phy *phy, 8403 u16 edc_mode) 8404 { 8405 u16 cur_limiting_mode; 8406 8407 bnx2x_cl45_read(bp, phy, 8408 MDIO_PMA_DEVAD, 8409 MDIO_PMA_REG_ROM_VER2, 8410 &cur_limiting_mode); 8411 DP(NETIF_MSG_LINK, "Current Limiting mode is 0x%x\n", 8412 cur_limiting_mode); 8413 8414 if (edc_mode == EDC_MODE_LIMITING) { 8415 DP(NETIF_MSG_LINK, "Setting LIMITING MODE\n"); 8416 bnx2x_cl45_write(bp, phy, 8417 MDIO_PMA_DEVAD, 8418 MDIO_PMA_REG_ROM_VER2, 8419 EDC_MODE_LIMITING); 8420 } else { /* LRM mode ( default )*/ 8421 8422 DP(NETIF_MSG_LINK, "Setting LRM MODE\n"); 8423 8424 /* Changing to LRM mode takes quite few seconds. So do it only 8425 * if current mode is limiting (default is LRM) 8426 */ 8427 if (cur_limiting_mode != EDC_MODE_LIMITING) 8428 return 0; 8429 8430 bnx2x_cl45_write(bp, phy, 8431 MDIO_PMA_DEVAD, 8432 MDIO_PMA_REG_LRM_MODE, 8433 0); 8434 bnx2x_cl45_write(bp, phy, 8435 MDIO_PMA_DEVAD, 8436 MDIO_PMA_REG_ROM_VER2, 8437 0x128); 8438 bnx2x_cl45_write(bp, phy, 8439 MDIO_PMA_DEVAD, 8440 MDIO_PMA_REG_MISC_CTRL0, 8441 0x4008); 8442 bnx2x_cl45_write(bp, phy, 8443 MDIO_PMA_DEVAD, 8444 MDIO_PMA_REG_LRM_MODE, 8445 0xaaaa); 8446 } 8447 return 0; 8448 } 8449 8450 static int bnx2x_8727_set_limiting_mode(struct bnx2x *bp, 8451 struct bnx2x_phy *phy, 8452 u16 edc_mode) 8453 { 8454 u16 phy_identifier; 8455 u16 rom_ver2_val; 8456 bnx2x_cl45_read(bp, phy, 8457 MDIO_PMA_DEVAD, 8458 MDIO_PMA_REG_PHY_IDENTIFIER, 8459 &phy_identifier); 8460 8461 bnx2x_cl45_write(bp, phy, 8462 MDIO_PMA_DEVAD, 8463 MDIO_PMA_REG_PHY_IDENTIFIER, 8464 (phy_identifier & ~(1<<9))); 8465 8466 bnx2x_cl45_read(bp, phy, 8467 MDIO_PMA_DEVAD, 8468 MDIO_PMA_REG_ROM_VER2, 8469 &rom_ver2_val); 8470 /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */ 8471 bnx2x_cl45_write(bp, phy, 8472 MDIO_PMA_DEVAD, 8473 MDIO_PMA_REG_ROM_VER2, 8474 (rom_ver2_val & 0xff00) | (edc_mode & 0x00ff)); 8475 8476 bnx2x_cl45_write(bp, phy, 8477 MDIO_PMA_DEVAD, 8478 MDIO_PMA_REG_PHY_IDENTIFIER, 8479 (phy_identifier | (1<<9))); 8480 8481 return 0; 8482 } 8483 8484 static void bnx2x_8727_specific_func(struct bnx2x_phy *phy, 8485 struct link_params *params, 8486 u32 action) 8487 { 8488 struct bnx2x *bp = params->bp; 8489 u16 val; 8490 switch (action) { 8491 case DISABLE_TX: 8492 bnx2x_sfp_set_transmitter(params, phy, 0); 8493 break; 8494 case ENABLE_TX: 8495 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED)) 8496 bnx2x_sfp_set_transmitter(params, phy, 1); 8497 break; 8498 case PHY_INIT: 8499 bnx2x_cl45_write(bp, phy, 8500 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, 8501 (1<<2) | (1<<5)); 8502 bnx2x_cl45_write(bp, phy, 8503 MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL, 8504 0); 8505 bnx2x_cl45_write(bp, phy, 8506 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0006); 8507 /* Make MOD_ABS give interrupt on change */ 8508 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 8509 MDIO_PMA_REG_8727_PCS_OPT_CTRL, 8510 &val); 8511 val |= (1<<12); 8512 if (phy->flags & FLAGS_NOC) 8513 val |= (3<<5); 8514 /* Set 8727 GPIOs to input to allow reading from the 8727 GPIO0 8515 * status which reflect SFP+ module over-current 8516 */ 8517 if (!(phy->flags & FLAGS_NOC)) 8518 val &= 0xff8f; /* Reset bits 4-6 */ 8519 bnx2x_cl45_write(bp, phy, 8520 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL, 8521 val); 8522 break; 8523 default: 8524 DP(NETIF_MSG_LINK, "Function 0x%x not supported by 8727\n", 8525 action); 8526 return; 8527 } 8528 } 8529 8530 static void bnx2x_set_e1e2_module_fault_led(struct link_params *params, 8531 u8 gpio_mode) 8532 { 8533 struct bnx2x *bp = params->bp; 8534 8535 u32 fault_led_gpio = REG_RD(bp, params->shmem_base + 8536 offsetof(struct shmem_region, 8537 dev_info.port_hw_config[params->port].sfp_ctrl)) & 8538 PORT_HW_CFG_FAULT_MODULE_LED_MASK; 8539 switch (fault_led_gpio) { 8540 case PORT_HW_CFG_FAULT_MODULE_LED_DISABLED: 8541 return; 8542 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO0: 8543 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO1: 8544 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO2: 8545 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO3: 8546 { 8547 u8 gpio_port = bnx2x_get_gpio_port(params); 8548 u16 gpio_pin = fault_led_gpio - 8549 PORT_HW_CFG_FAULT_MODULE_LED_GPIO0; 8550 DP(NETIF_MSG_LINK, "Set fault module-detected led " 8551 "pin %x port %x mode %x\n", 8552 gpio_pin, gpio_port, gpio_mode); 8553 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port); 8554 } 8555 break; 8556 default: 8557 DP(NETIF_MSG_LINK, "Error: Invalid fault led mode 0x%x\n", 8558 fault_led_gpio); 8559 } 8560 } 8561 8562 static void bnx2x_set_e3_module_fault_led(struct link_params *params, 8563 u8 gpio_mode) 8564 { 8565 u32 pin_cfg; 8566 u8 port = params->port; 8567 struct bnx2x *bp = params->bp; 8568 pin_cfg = (REG_RD(bp, params->shmem_base + 8569 offsetof(struct shmem_region, 8570 dev_info.port_hw_config[port].e3_sfp_ctrl)) & 8571 PORT_HW_CFG_E3_FAULT_MDL_LED_MASK) >> 8572 PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT; 8573 DP(NETIF_MSG_LINK, "Setting Fault LED to %d using pin cfg %d\n", 8574 gpio_mode, pin_cfg); 8575 bnx2x_set_cfg_pin(bp, pin_cfg, gpio_mode); 8576 } 8577 8578 static void bnx2x_set_sfp_module_fault_led(struct link_params *params, 8579 u8 gpio_mode) 8580 { 8581 struct bnx2x *bp = params->bp; 8582 DP(NETIF_MSG_LINK, "Setting SFP+ module fault LED to %d\n", gpio_mode); 8583 if (CHIP_IS_E3(bp)) { 8584 /* Low ==> if SFP+ module is supported otherwise 8585 * High ==> if SFP+ module is not on the approved vendor list 8586 */ 8587 bnx2x_set_e3_module_fault_led(params, gpio_mode); 8588 } else 8589 bnx2x_set_e1e2_module_fault_led(params, gpio_mode); 8590 } 8591 8592 static void bnx2x_warpcore_hw_reset(struct bnx2x_phy *phy, 8593 struct link_params *params) 8594 { 8595 struct bnx2x *bp = params->bp; 8596 bnx2x_warpcore_power_module(params, 0); 8597 /* Put Warpcore in low power mode */ 8598 REG_WR(bp, MISC_REG_WC0_RESET, 0x0c0e); 8599 8600 /* Put LCPLL in low power mode */ 8601 REG_WR(bp, MISC_REG_LCPLL_E40_PWRDWN, 1); 8602 REG_WR(bp, MISC_REG_LCPLL_E40_RESETB_ANA, 0); 8603 REG_WR(bp, MISC_REG_LCPLL_E40_RESETB_DIG, 0); 8604 } 8605 8606 static void bnx2x_power_sfp_module(struct link_params *params, 8607 struct bnx2x_phy *phy, 8608 u8 power) 8609 { 8610 struct bnx2x *bp = params->bp; 8611 DP(NETIF_MSG_LINK, "Setting SFP+ power to %x\n", power); 8612 8613 switch (phy->type) { 8614 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: 8615 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722: 8616 bnx2x_8727_power_module(params->bp, phy, power); 8617 break; 8618 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT: 8619 bnx2x_warpcore_power_module(params, power); 8620 break; 8621 default: 8622 break; 8623 } 8624 } 8625 static void bnx2x_warpcore_set_limiting_mode(struct link_params *params, 8626 struct bnx2x_phy *phy, 8627 u16 edc_mode) 8628 { 8629 u16 val = 0; 8630 u16 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT; 8631 struct bnx2x *bp = params->bp; 8632 8633 u8 lane = bnx2x_get_warpcore_lane(phy, params); 8634 /* This is a global register which controls all lanes */ 8635 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 8636 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val); 8637 val &= ~(0xf << (lane << 2)); 8638 8639 switch (edc_mode) { 8640 case EDC_MODE_LINEAR: 8641 case EDC_MODE_LIMITING: 8642 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT; 8643 break; 8644 case EDC_MODE_PASSIVE_DAC: 8645 case EDC_MODE_ACTIVE_DAC: 8646 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC; 8647 break; 8648 default: 8649 break; 8650 } 8651 8652 val |= (mode << (lane << 2)); 8653 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 8654 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, val); 8655 /* A must read */ 8656 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 8657 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val); 8658 8659 /* Restart microcode to re-read the new mode */ 8660 bnx2x_warpcore_reset_lane(bp, phy, 1); 8661 bnx2x_warpcore_reset_lane(bp, phy, 0); 8662 8663 } 8664 8665 static void bnx2x_set_limiting_mode(struct link_params *params, 8666 struct bnx2x_phy *phy, 8667 u16 edc_mode) 8668 { 8669 switch (phy->type) { 8670 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: 8671 bnx2x_8726_set_limiting_mode(params->bp, phy, edc_mode); 8672 break; 8673 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: 8674 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722: 8675 bnx2x_8727_set_limiting_mode(params->bp, phy, edc_mode); 8676 break; 8677 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT: 8678 bnx2x_warpcore_set_limiting_mode(params, phy, edc_mode); 8679 break; 8680 } 8681 } 8682 8683 static int bnx2x_sfp_module_detection(struct bnx2x_phy *phy, 8684 struct link_params *params) 8685 { 8686 struct bnx2x *bp = params->bp; 8687 u16 edc_mode; 8688 int rc = 0; 8689 8690 u32 val = REG_RD(bp, params->shmem_base + 8691 offsetof(struct shmem_region, dev_info. 8692 port_feature_config[params->port].config)); 8693 /* Enabled transmitter by default */ 8694 bnx2x_sfp_set_transmitter(params, phy, 1); 8695 DP(NETIF_MSG_LINK, "SFP+ module plugged in/out detected on port %d\n", 8696 params->port); 8697 /* Power up module */ 8698 bnx2x_power_sfp_module(params, phy, 1); 8699 if (bnx2x_get_edc_mode(phy, params, &edc_mode) != 0) { 8700 DP(NETIF_MSG_LINK, "Failed to get valid module type\n"); 8701 return -EINVAL; 8702 } else if (bnx2x_verify_sfp_module(phy, params) != 0) { 8703 /* Check SFP+ module compatibility */ 8704 DP(NETIF_MSG_LINK, "Module verification failed!!\n"); 8705 rc = -EINVAL; 8706 /* Turn on fault module-detected led */ 8707 bnx2x_set_sfp_module_fault_led(params, 8708 MISC_REGISTERS_GPIO_HIGH); 8709 8710 /* Check if need to power down the SFP+ module */ 8711 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == 8712 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN) { 8713 DP(NETIF_MSG_LINK, "Shutdown SFP+ module!!\n"); 8714 bnx2x_power_sfp_module(params, phy, 0); 8715 return rc; 8716 } 8717 } else { 8718 /* Turn off fault module-detected led */ 8719 bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_LOW); 8720 } 8721 8722 /* Check and set limiting mode / LRM mode on 8726. On 8727 it 8723 * is done automatically 8724 */ 8725 bnx2x_set_limiting_mode(params, phy, edc_mode); 8726 8727 /* Disable transmit for this module if the module is not approved, and 8728 * laser needs to be disabled. 8729 */ 8730 if ((rc) && 8731 ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == 8732 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)) 8733 bnx2x_sfp_set_transmitter(params, phy, 0); 8734 8735 return rc; 8736 } 8737 8738 void bnx2x_handle_module_detect_int(struct link_params *params) 8739 { 8740 struct bnx2x *bp = params->bp; 8741 struct bnx2x_phy *phy; 8742 u32 gpio_val; 8743 u8 gpio_num, gpio_port; 8744 if (CHIP_IS_E3(bp)) { 8745 phy = ¶ms->phy[INT_PHY]; 8746 /* Always enable TX laser,will be disabled in case of fault */ 8747 bnx2x_sfp_set_transmitter(params, phy, 1); 8748 } else { 8749 phy = ¶ms->phy[EXT_PHY1]; 8750 } 8751 if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id, params->shmem_base, 8752 params->port, &gpio_num, &gpio_port) == 8753 -EINVAL) { 8754 DP(NETIF_MSG_LINK, "Failed to get MOD_ABS interrupt config\n"); 8755 return; 8756 } 8757 8758 /* Set valid module led off */ 8759 bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_HIGH); 8760 8761 /* Get current gpio val reflecting module plugged in / out*/ 8762 gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port); 8763 8764 /* Call the handling function in case module is detected */ 8765 if (gpio_val == 0) { 8766 bnx2x_set_mdio_emac_per_phy(bp, params); 8767 bnx2x_set_aer_mmd(params, phy); 8768 8769 bnx2x_power_sfp_module(params, phy, 1); 8770 bnx2x_set_gpio_int(bp, gpio_num, 8771 MISC_REGISTERS_GPIO_INT_OUTPUT_CLR, 8772 gpio_port); 8773 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0) { 8774 bnx2x_sfp_module_detection(phy, params); 8775 if (CHIP_IS_E3(bp)) { 8776 u16 rx_tx_in_reset; 8777 /* In case WC is out of reset, reconfigure the 8778 * link speed while taking into account 1G 8779 * module limitation. 8780 */ 8781 bnx2x_cl45_read(bp, phy, 8782 MDIO_WC_DEVAD, 8783 MDIO_WC_REG_DIGITAL5_MISC6, 8784 &rx_tx_in_reset); 8785 if ((!rx_tx_in_reset) && 8786 (params->link_flags & 8787 PHY_INITIALIZED)) { 8788 bnx2x_warpcore_reset_lane(bp, phy, 1); 8789 bnx2x_warpcore_config_sfi(phy, params); 8790 bnx2x_warpcore_reset_lane(bp, phy, 0); 8791 } 8792 } 8793 } else { 8794 DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n"); 8795 } 8796 } else { 8797 bnx2x_set_gpio_int(bp, gpio_num, 8798 MISC_REGISTERS_GPIO_INT_OUTPUT_SET, 8799 gpio_port); 8800 /* Module was plugged out. 8801 * Disable transmit for this module 8802 */ 8803 phy->media_type = ETH_PHY_NOT_PRESENT; 8804 } 8805 } 8806 8807 /******************************************************************/ 8808 /* Used by 8706 and 8727 */ 8809 /******************************************************************/ 8810 static void bnx2x_sfp_mask_fault(struct bnx2x *bp, 8811 struct bnx2x_phy *phy, 8812 u16 alarm_status_offset, 8813 u16 alarm_ctrl_offset) 8814 { 8815 u16 alarm_status, val; 8816 bnx2x_cl45_read(bp, phy, 8817 MDIO_PMA_DEVAD, alarm_status_offset, 8818 &alarm_status); 8819 bnx2x_cl45_read(bp, phy, 8820 MDIO_PMA_DEVAD, alarm_status_offset, 8821 &alarm_status); 8822 /* Mask or enable the fault event. */ 8823 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, &val); 8824 if (alarm_status & (1<<0)) 8825 val &= ~(1<<0); 8826 else 8827 val |= (1<<0); 8828 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, val); 8829 } 8830 /******************************************************************/ 8831 /* common BCM8706/BCM8726 PHY SECTION */ 8832 /******************************************************************/ 8833 static u8 bnx2x_8706_8726_read_status(struct bnx2x_phy *phy, 8834 struct link_params *params, 8835 struct link_vars *vars) 8836 { 8837 u8 link_up = 0; 8838 u16 val1, val2, rx_sd, pcs_status; 8839 struct bnx2x *bp = params->bp; 8840 DP(NETIF_MSG_LINK, "XGXS 8706/8726\n"); 8841 /* Clear RX Alarm*/ 8842 bnx2x_cl45_read(bp, phy, 8843 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2); 8844 8845 bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT, 8846 MDIO_PMA_LASI_TXCTRL); 8847 8848 /* Clear LASI indication*/ 8849 bnx2x_cl45_read(bp, phy, 8850 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1); 8851 bnx2x_cl45_read(bp, phy, 8852 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2); 8853 DP(NETIF_MSG_LINK, "8706/8726 LASI status 0x%x--> 0x%x\n", val1, val2); 8854 8855 bnx2x_cl45_read(bp, phy, 8856 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd); 8857 bnx2x_cl45_read(bp, phy, 8858 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &pcs_status); 8859 bnx2x_cl45_read(bp, phy, 8860 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2); 8861 bnx2x_cl45_read(bp, phy, 8862 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2); 8863 8864 DP(NETIF_MSG_LINK, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps" 8865 " link_status 0x%x\n", rx_sd, pcs_status, val2); 8866 /* Link is up if both bit 0 of pmd_rx_sd and bit 0 of pcs_status 8867 * are set, or if the autoneg bit 1 is set 8868 */ 8869 link_up = ((rx_sd & pcs_status & 0x1) || (val2 & (1<<1))); 8870 if (link_up) { 8871 if (val2 & (1<<1)) 8872 vars->line_speed = SPEED_1000; 8873 else 8874 vars->line_speed = SPEED_10000; 8875 bnx2x_ext_phy_resolve_fc(phy, params, vars); 8876 vars->duplex = DUPLEX_FULL; 8877 } 8878 8879 /* Capture 10G link fault. Read twice to clear stale value. */ 8880 if (vars->line_speed == SPEED_10000) { 8881 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 8882 MDIO_PMA_LASI_TXSTAT, &val1); 8883 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 8884 MDIO_PMA_LASI_TXSTAT, &val1); 8885 if (val1 & (1<<0)) 8886 vars->fault_detected = 1; 8887 } 8888 8889 return link_up; 8890 } 8891 8892 /******************************************************************/ 8893 /* BCM8706 PHY SECTION */ 8894 /******************************************************************/ 8895 static void bnx2x_8706_config_init(struct bnx2x_phy *phy, 8896 struct link_params *params, 8897 struct link_vars *vars) 8898 { 8899 u32 tx_en_mode; 8900 u16 cnt, val, tmp1; 8901 struct bnx2x *bp = params->bp; 8902 8903 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 8904 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); 8905 /* HW reset */ 8906 bnx2x_ext_phy_hw_reset(bp, params->port); 8907 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040); 8908 bnx2x_wait_reset_complete(bp, phy, params); 8909 8910 /* Wait until fw is loaded */ 8911 for (cnt = 0; cnt < 100; cnt++) { 8912 bnx2x_cl45_read(bp, phy, 8913 MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER1, &val); 8914 if (val) 8915 break; 8916 usleep_range(10000, 20000); 8917 } 8918 DP(NETIF_MSG_LINK, "XGXS 8706 is initialized after %d ms\n", cnt); 8919 if ((params->feature_config_flags & 8920 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) { 8921 u8 i; 8922 u16 reg; 8923 for (i = 0; i < 4; i++) { 8924 reg = MDIO_XS_8706_REG_BANK_RX0 + 8925 i*(MDIO_XS_8706_REG_BANK_RX1 - 8926 MDIO_XS_8706_REG_BANK_RX0); 8927 bnx2x_cl45_read(bp, phy, MDIO_XS_DEVAD, reg, &val); 8928 /* Clear first 3 bits of the control */ 8929 val &= ~0x7; 8930 /* Set control bits according to configuration */ 8931 val |= (phy->rx_preemphasis[i] & 0x7); 8932 DP(NETIF_MSG_LINK, "Setting RX Equalizer to BCM8706" 8933 " reg 0x%x <-- val 0x%x\n", reg, val); 8934 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, reg, val); 8935 } 8936 } 8937 /* Force speed */ 8938 if (phy->req_line_speed == SPEED_10000) { 8939 DP(NETIF_MSG_LINK, "XGXS 8706 force 10Gbps\n"); 8940 8941 bnx2x_cl45_write(bp, phy, 8942 MDIO_PMA_DEVAD, 8943 MDIO_PMA_REG_DIGITAL_CTRL, 0x400); 8944 bnx2x_cl45_write(bp, phy, 8945 MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL, 8946 0); 8947 /* Arm LASI for link and Tx fault. */ 8948 bnx2x_cl45_write(bp, phy, 8949 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 3); 8950 } else { 8951 /* Force 1Gbps using autoneg with 1G advertisement */ 8952 8953 /* Allow CL37 through CL73 */ 8954 DP(NETIF_MSG_LINK, "XGXS 8706 AutoNeg\n"); 8955 bnx2x_cl45_write(bp, phy, 8956 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c); 8957 8958 /* Enable Full-Duplex advertisement on CL37 */ 8959 bnx2x_cl45_write(bp, phy, 8960 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LP, 0x0020); 8961 /* Enable CL37 AN */ 8962 bnx2x_cl45_write(bp, phy, 8963 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000); 8964 /* 1G support */ 8965 bnx2x_cl45_write(bp, phy, 8966 MDIO_AN_DEVAD, MDIO_AN_REG_ADV, (1<<5)); 8967 8968 /* Enable clause 73 AN */ 8969 bnx2x_cl45_write(bp, phy, 8970 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200); 8971 bnx2x_cl45_write(bp, phy, 8972 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, 8973 0x0400); 8974 bnx2x_cl45_write(bp, phy, 8975 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 8976 0x0004); 8977 } 8978 bnx2x_save_bcm_spirom_ver(bp, phy, params->port); 8979 8980 /* If TX Laser is controlled by GPIO_0, do not let PHY go into low 8981 * power mode, if TX Laser is disabled 8982 */ 8983 8984 tx_en_mode = REG_RD(bp, params->shmem_base + 8985 offsetof(struct shmem_region, 8986 dev_info.port_hw_config[params->port].sfp_ctrl)) 8987 & PORT_HW_CFG_TX_LASER_MASK; 8988 8989 if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) { 8990 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n"); 8991 bnx2x_cl45_read(bp, phy, 8992 MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, &tmp1); 8993 tmp1 |= 0x1; 8994 bnx2x_cl45_write(bp, phy, 8995 MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, tmp1); 8996 } 8997 } 8998 8999 static u8 bnx2x_8706_read_status(struct bnx2x_phy *phy, 9000 struct link_params *params, 9001 struct link_vars *vars) 9002 { 9003 return bnx2x_8706_8726_read_status(phy, params, vars); 9004 } 9005 9006 /******************************************************************/ 9007 /* BCM8726 PHY SECTION */ 9008 /******************************************************************/ 9009 static void bnx2x_8726_config_loopback(struct bnx2x_phy *phy, 9010 struct link_params *params) 9011 { 9012 struct bnx2x *bp = params->bp; 9013 DP(NETIF_MSG_LINK, "PMA/PMD ext_phy_loopback: 8726\n"); 9014 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001); 9015 } 9016 9017 static void bnx2x_8726_external_rom_boot(struct bnx2x_phy *phy, 9018 struct link_params *params) 9019 { 9020 struct bnx2x *bp = params->bp; 9021 /* Need to wait 100ms after reset */ 9022 msleep(100); 9023 9024 /* Micro controller re-boot */ 9025 bnx2x_cl45_write(bp, phy, 9026 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x018B); 9027 9028 /* Set soft reset */ 9029 bnx2x_cl45_write(bp, phy, 9030 MDIO_PMA_DEVAD, 9031 MDIO_PMA_REG_GEN_CTRL, 9032 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET); 9033 9034 bnx2x_cl45_write(bp, phy, 9035 MDIO_PMA_DEVAD, 9036 MDIO_PMA_REG_MISC_CTRL1, 0x0001); 9037 9038 bnx2x_cl45_write(bp, phy, 9039 MDIO_PMA_DEVAD, 9040 MDIO_PMA_REG_GEN_CTRL, 9041 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP); 9042 9043 /* Wait for 150ms for microcode load */ 9044 msleep(150); 9045 9046 /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */ 9047 bnx2x_cl45_write(bp, phy, 9048 MDIO_PMA_DEVAD, 9049 MDIO_PMA_REG_MISC_CTRL1, 0x0000); 9050 9051 msleep(200); 9052 bnx2x_save_bcm_spirom_ver(bp, phy, params->port); 9053 } 9054 9055 static u8 bnx2x_8726_read_status(struct bnx2x_phy *phy, 9056 struct link_params *params, 9057 struct link_vars *vars) 9058 { 9059 struct bnx2x *bp = params->bp; 9060 u16 val1; 9061 u8 link_up = bnx2x_8706_8726_read_status(phy, params, vars); 9062 if (link_up) { 9063 bnx2x_cl45_read(bp, phy, 9064 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 9065 &val1); 9066 if (val1 & (1<<15)) { 9067 DP(NETIF_MSG_LINK, "Tx is disabled\n"); 9068 link_up = 0; 9069 vars->line_speed = 0; 9070 } 9071 } 9072 return link_up; 9073 } 9074 9075 9076 static void bnx2x_8726_config_init(struct bnx2x_phy *phy, 9077 struct link_params *params, 9078 struct link_vars *vars) 9079 { 9080 struct bnx2x *bp = params->bp; 9081 DP(NETIF_MSG_LINK, "Initializing BCM8726\n"); 9082 9083 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15); 9084 bnx2x_wait_reset_complete(bp, phy, params); 9085 9086 bnx2x_8726_external_rom_boot(phy, params); 9087 9088 /* Need to call module detected on initialization since the module 9089 * detection triggered by actual module insertion might occur before 9090 * driver is loaded, and when driver is loaded, it reset all 9091 * registers, including the transmitter 9092 */ 9093 bnx2x_sfp_module_detection(phy, params); 9094 9095 if (phy->req_line_speed == SPEED_1000) { 9096 DP(NETIF_MSG_LINK, "Setting 1G force\n"); 9097 bnx2x_cl45_write(bp, phy, 9098 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40); 9099 bnx2x_cl45_write(bp, phy, 9100 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD); 9101 bnx2x_cl45_write(bp, phy, 9102 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x5); 9103 bnx2x_cl45_write(bp, phy, 9104 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, 9105 0x400); 9106 } else if ((phy->req_line_speed == SPEED_AUTO_NEG) && 9107 (phy->speed_cap_mask & 9108 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) && 9109 ((phy->speed_cap_mask & 9110 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) != 9111 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) { 9112 DP(NETIF_MSG_LINK, "Setting 1G clause37\n"); 9113 /* Set Flow control */ 9114 bnx2x_ext_phy_set_pause(params, phy, vars); 9115 bnx2x_cl45_write(bp, phy, 9116 MDIO_AN_DEVAD, MDIO_AN_REG_ADV, 0x20); 9117 bnx2x_cl45_write(bp, phy, 9118 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c); 9119 bnx2x_cl45_write(bp, phy, 9120 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, 0x0020); 9121 bnx2x_cl45_write(bp, phy, 9122 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000); 9123 bnx2x_cl45_write(bp, phy, 9124 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200); 9125 /* Enable RX-ALARM control to receive interrupt for 1G speed 9126 * change 9127 */ 9128 bnx2x_cl45_write(bp, phy, 9129 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x4); 9130 bnx2x_cl45_write(bp, phy, 9131 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, 9132 0x400); 9133 9134 } else { /* Default 10G. Set only LASI control */ 9135 bnx2x_cl45_write(bp, phy, 9136 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 1); 9137 } 9138 9139 /* Set TX PreEmphasis if needed */ 9140 if ((params->feature_config_flags & 9141 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) { 9142 DP(NETIF_MSG_LINK, 9143 "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n", 9144 phy->tx_preemphasis[0], 9145 phy->tx_preemphasis[1]); 9146 bnx2x_cl45_write(bp, phy, 9147 MDIO_PMA_DEVAD, 9148 MDIO_PMA_REG_8726_TX_CTRL1, 9149 phy->tx_preemphasis[0]); 9150 9151 bnx2x_cl45_write(bp, phy, 9152 MDIO_PMA_DEVAD, 9153 MDIO_PMA_REG_8726_TX_CTRL2, 9154 phy->tx_preemphasis[1]); 9155 } 9156 } 9157 9158 static void bnx2x_8726_link_reset(struct bnx2x_phy *phy, 9159 struct link_params *params) 9160 { 9161 struct bnx2x *bp = params->bp; 9162 DP(NETIF_MSG_LINK, "bnx2x_8726_link_reset port %d\n", params->port); 9163 /* Set serial boot control for external load */ 9164 bnx2x_cl45_write(bp, phy, 9165 MDIO_PMA_DEVAD, 9166 MDIO_PMA_REG_GEN_CTRL, 0x0001); 9167 } 9168 9169 /******************************************************************/ 9170 /* BCM8727 PHY SECTION */ 9171 /******************************************************************/ 9172 9173 static void bnx2x_8727_set_link_led(struct bnx2x_phy *phy, 9174 struct link_params *params, u8 mode) 9175 { 9176 struct bnx2x *bp = params->bp; 9177 u16 led_mode_bitmask = 0; 9178 u16 gpio_pins_bitmask = 0; 9179 u16 val; 9180 /* Only NOC flavor requires to set the LED specifically */ 9181 if (!(phy->flags & FLAGS_NOC)) 9182 return; 9183 switch (mode) { 9184 case LED_MODE_FRONT_PANEL_OFF: 9185 case LED_MODE_OFF: 9186 led_mode_bitmask = 0; 9187 gpio_pins_bitmask = 0x03; 9188 break; 9189 case LED_MODE_ON: 9190 led_mode_bitmask = 0; 9191 gpio_pins_bitmask = 0x02; 9192 break; 9193 case LED_MODE_OPER: 9194 led_mode_bitmask = 0x60; 9195 gpio_pins_bitmask = 0x11; 9196 break; 9197 } 9198 bnx2x_cl45_read(bp, phy, 9199 MDIO_PMA_DEVAD, 9200 MDIO_PMA_REG_8727_PCS_OPT_CTRL, 9201 &val); 9202 val &= 0xff8f; 9203 val |= led_mode_bitmask; 9204 bnx2x_cl45_write(bp, phy, 9205 MDIO_PMA_DEVAD, 9206 MDIO_PMA_REG_8727_PCS_OPT_CTRL, 9207 val); 9208 bnx2x_cl45_read(bp, phy, 9209 MDIO_PMA_DEVAD, 9210 MDIO_PMA_REG_8727_GPIO_CTRL, 9211 &val); 9212 val &= 0xffe0; 9213 val |= gpio_pins_bitmask; 9214 bnx2x_cl45_write(bp, phy, 9215 MDIO_PMA_DEVAD, 9216 MDIO_PMA_REG_8727_GPIO_CTRL, 9217 val); 9218 } 9219 static void bnx2x_8727_hw_reset(struct bnx2x_phy *phy, 9220 struct link_params *params) { 9221 u32 swap_val, swap_override; 9222 u8 port; 9223 /* The PHY reset is controlled by GPIO 1. Fake the port number 9224 * to cancel the swap done in set_gpio() 9225 */ 9226 struct bnx2x *bp = params->bp; 9227 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); 9228 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); 9229 port = (swap_val && swap_override) ^ 1; 9230 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, 9231 MISC_REGISTERS_GPIO_OUTPUT_LOW, port); 9232 } 9233 9234 static void bnx2x_8727_config_speed(struct bnx2x_phy *phy, 9235 struct link_params *params) 9236 { 9237 struct bnx2x *bp = params->bp; 9238 u16 tmp1, val; 9239 /* Set option 1G speed */ 9240 if ((phy->req_line_speed == SPEED_1000) || 9241 (phy->media_type == ETH_PHY_SFP_1G_FIBER)) { 9242 DP(NETIF_MSG_LINK, "Setting 1G force\n"); 9243 bnx2x_cl45_write(bp, phy, 9244 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40); 9245 bnx2x_cl45_write(bp, phy, 9246 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD); 9247 bnx2x_cl45_read(bp, phy, 9248 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, &tmp1); 9249 DP(NETIF_MSG_LINK, "1.7 = 0x%x\n", tmp1); 9250 /* Power down the XAUI until link is up in case of dual-media 9251 * and 1G 9252 */ 9253 if (DUAL_MEDIA(params)) { 9254 bnx2x_cl45_read(bp, phy, 9255 MDIO_PMA_DEVAD, 9256 MDIO_PMA_REG_8727_PCS_GP, &val); 9257 val |= (3<<10); 9258 bnx2x_cl45_write(bp, phy, 9259 MDIO_PMA_DEVAD, 9260 MDIO_PMA_REG_8727_PCS_GP, val); 9261 } 9262 } else if ((phy->req_line_speed == SPEED_AUTO_NEG) && 9263 ((phy->speed_cap_mask & 9264 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) && 9265 ((phy->speed_cap_mask & 9266 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) != 9267 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) { 9268 9269 DP(NETIF_MSG_LINK, "Setting 1G clause37\n"); 9270 bnx2x_cl45_write(bp, phy, 9271 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 0); 9272 bnx2x_cl45_write(bp, phy, 9273 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1300); 9274 } else { 9275 /* Since the 8727 has only single reset pin, need to set the 10G 9276 * registers although it is default 9277 */ 9278 bnx2x_cl45_write(bp, phy, 9279 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 9280 0x0020); 9281 bnx2x_cl45_write(bp, phy, 9282 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x0100); 9283 bnx2x_cl45_write(bp, phy, 9284 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040); 9285 bnx2x_cl45_write(bp, phy, 9286 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 9287 0x0008); 9288 } 9289 } 9290 9291 static void bnx2x_8727_config_init(struct bnx2x_phy *phy, 9292 struct link_params *params, 9293 struct link_vars *vars) 9294 { 9295 u32 tx_en_mode; 9296 u16 tmp1, mod_abs, tmp2; 9297 struct bnx2x *bp = params->bp; 9298 /* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */ 9299 9300 bnx2x_wait_reset_complete(bp, phy, params); 9301 9302 DP(NETIF_MSG_LINK, "Initializing BCM8727\n"); 9303 9304 bnx2x_8727_specific_func(phy, params, PHY_INIT); 9305 /* Initially configure MOD_ABS to interrupt when module is 9306 * presence( bit 8) 9307 */ 9308 bnx2x_cl45_read(bp, phy, 9309 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs); 9310 /* Set EDC off by setting OPTXLOS signal input to low (bit 9). 9311 * When the EDC is off it locks onto a reference clock and avoids 9312 * becoming 'lost' 9313 */ 9314 mod_abs &= ~(1<<8); 9315 if (!(phy->flags & FLAGS_NOC)) 9316 mod_abs &= ~(1<<9); 9317 bnx2x_cl45_write(bp, phy, 9318 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs); 9319 9320 /* Enable/Disable PHY transmitter output */ 9321 bnx2x_set_disable_pmd_transmit(params, phy, 0); 9322 9323 bnx2x_8727_power_module(bp, phy, 1); 9324 9325 bnx2x_cl45_read(bp, phy, 9326 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1); 9327 9328 bnx2x_cl45_read(bp, phy, 9329 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1); 9330 9331 bnx2x_8727_config_speed(phy, params); 9332 9333 9334 /* Set TX PreEmphasis if needed */ 9335 if ((params->feature_config_flags & 9336 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) { 9337 DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n", 9338 phy->tx_preemphasis[0], 9339 phy->tx_preemphasis[1]); 9340 bnx2x_cl45_write(bp, phy, 9341 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL1, 9342 phy->tx_preemphasis[0]); 9343 9344 bnx2x_cl45_write(bp, phy, 9345 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL2, 9346 phy->tx_preemphasis[1]); 9347 } 9348 9349 /* If TX Laser is controlled by GPIO_0, do not let PHY go into low 9350 * power mode, if TX Laser is disabled 9351 */ 9352 tx_en_mode = REG_RD(bp, params->shmem_base + 9353 offsetof(struct shmem_region, 9354 dev_info.port_hw_config[params->port].sfp_ctrl)) 9355 & PORT_HW_CFG_TX_LASER_MASK; 9356 9357 if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) { 9358 9359 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n"); 9360 bnx2x_cl45_read(bp, phy, 9361 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, &tmp2); 9362 tmp2 |= 0x1000; 9363 tmp2 &= 0xFFEF; 9364 bnx2x_cl45_write(bp, phy, 9365 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, tmp2); 9366 bnx2x_cl45_read(bp, phy, 9367 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 9368 &tmp2); 9369 bnx2x_cl45_write(bp, phy, 9370 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 9371 (tmp2 & 0x7fff)); 9372 } 9373 } 9374 9375 static void bnx2x_8727_handle_mod_abs(struct bnx2x_phy *phy, 9376 struct link_params *params) 9377 { 9378 struct bnx2x *bp = params->bp; 9379 u16 mod_abs, rx_alarm_status; 9380 u32 val = REG_RD(bp, params->shmem_base + 9381 offsetof(struct shmem_region, dev_info. 9382 port_feature_config[params->port]. 9383 config)); 9384 bnx2x_cl45_read(bp, phy, 9385 MDIO_PMA_DEVAD, 9386 MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs); 9387 if (mod_abs & (1<<8)) { 9388 9389 /* Module is absent */ 9390 DP(NETIF_MSG_LINK, 9391 "MOD_ABS indication show module is absent\n"); 9392 phy->media_type = ETH_PHY_NOT_PRESENT; 9393 /* 1. Set mod_abs to detect next module 9394 * presence event 9395 * 2. Set EDC off by setting OPTXLOS signal input to low 9396 * (bit 9). 9397 * When the EDC is off it locks onto a reference clock and 9398 * avoids becoming 'lost'. 9399 */ 9400 mod_abs &= ~(1<<8); 9401 if (!(phy->flags & FLAGS_NOC)) 9402 mod_abs &= ~(1<<9); 9403 bnx2x_cl45_write(bp, phy, 9404 MDIO_PMA_DEVAD, 9405 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs); 9406 9407 /* Clear RX alarm since it stays up as long as 9408 * the mod_abs wasn't changed 9409 */ 9410 bnx2x_cl45_read(bp, phy, 9411 MDIO_PMA_DEVAD, 9412 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status); 9413 9414 } else { 9415 /* Module is present */ 9416 DP(NETIF_MSG_LINK, 9417 "MOD_ABS indication show module is present\n"); 9418 /* First disable transmitter, and if the module is ok, the 9419 * module_detection will enable it 9420 * 1. Set mod_abs to detect next module absent event ( bit 8) 9421 * 2. Restore the default polarity of the OPRXLOS signal and 9422 * this signal will then correctly indicate the presence or 9423 * absence of the Rx signal. (bit 9) 9424 */ 9425 mod_abs |= (1<<8); 9426 if (!(phy->flags & FLAGS_NOC)) 9427 mod_abs |= (1<<9); 9428 bnx2x_cl45_write(bp, phy, 9429 MDIO_PMA_DEVAD, 9430 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs); 9431 9432 /* Clear RX alarm since it stays up as long as the mod_abs 9433 * wasn't changed. This is need to be done before calling the 9434 * module detection, otherwise it will clear* the link update 9435 * alarm 9436 */ 9437 bnx2x_cl45_read(bp, phy, 9438 MDIO_PMA_DEVAD, 9439 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status); 9440 9441 9442 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == 9443 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER) 9444 bnx2x_sfp_set_transmitter(params, phy, 0); 9445 9446 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0) 9447 bnx2x_sfp_module_detection(phy, params); 9448 else 9449 DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n"); 9450 9451 /* Reconfigure link speed based on module type limitations */ 9452 bnx2x_8727_config_speed(phy, params); 9453 } 9454 9455 DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n", 9456 rx_alarm_status); 9457 /* No need to check link status in case of module plugged in/out */ 9458 } 9459 9460 static u8 bnx2x_8727_read_status(struct bnx2x_phy *phy, 9461 struct link_params *params, 9462 struct link_vars *vars) 9463 9464 { 9465 struct bnx2x *bp = params->bp; 9466 u8 link_up = 0, oc_port = params->port; 9467 u16 link_status = 0; 9468 u16 rx_alarm_status, lasi_ctrl, val1; 9469 9470 /* If PHY is not initialized, do not check link status */ 9471 bnx2x_cl45_read(bp, phy, 9472 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 9473 &lasi_ctrl); 9474 if (!lasi_ctrl) 9475 return 0; 9476 9477 /* Check the LASI on Rx */ 9478 bnx2x_cl45_read(bp, phy, 9479 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, 9480 &rx_alarm_status); 9481 vars->line_speed = 0; 9482 DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n", rx_alarm_status); 9483 9484 bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT, 9485 MDIO_PMA_LASI_TXCTRL); 9486 9487 bnx2x_cl45_read(bp, phy, 9488 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1); 9489 9490 DP(NETIF_MSG_LINK, "8727 LASI status 0x%x\n", val1); 9491 9492 /* Clear MSG-OUT */ 9493 bnx2x_cl45_read(bp, phy, 9494 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1); 9495 9496 /* If a module is present and there is need to check 9497 * for over current 9498 */ 9499 if (!(phy->flags & FLAGS_NOC) && !(rx_alarm_status & (1<<5))) { 9500 /* Check over-current using 8727 GPIO0 input*/ 9501 bnx2x_cl45_read(bp, phy, 9502 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL, 9503 &val1); 9504 9505 if ((val1 & (1<<8)) == 0) { 9506 if (!CHIP_IS_E1x(bp)) 9507 oc_port = BP_PATH(bp) + (params->port << 1); 9508 DP(NETIF_MSG_LINK, 9509 "8727 Power fault has been detected on port %d\n", 9510 oc_port); 9511 netdev_err(bp->dev, "Error: Power fault on Port %d has " 9512 "been detected and the power to " 9513 "that SFP+ module has been removed " 9514 "to prevent failure of the card. " 9515 "Please remove the SFP+ module and " 9516 "restart the system to clear this " 9517 "error.\n", 9518 oc_port); 9519 /* Disable all RX_ALARMs except for mod_abs */ 9520 bnx2x_cl45_write(bp, phy, 9521 MDIO_PMA_DEVAD, 9522 MDIO_PMA_LASI_RXCTRL, (1<<5)); 9523 9524 bnx2x_cl45_read(bp, phy, 9525 MDIO_PMA_DEVAD, 9526 MDIO_PMA_REG_PHY_IDENTIFIER, &val1); 9527 /* Wait for module_absent_event */ 9528 val1 |= (1<<8); 9529 bnx2x_cl45_write(bp, phy, 9530 MDIO_PMA_DEVAD, 9531 MDIO_PMA_REG_PHY_IDENTIFIER, val1); 9532 /* Clear RX alarm */ 9533 bnx2x_cl45_read(bp, phy, 9534 MDIO_PMA_DEVAD, 9535 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status); 9536 bnx2x_8727_power_module(params->bp, phy, 0); 9537 return 0; 9538 } 9539 } /* Over current check */ 9540 9541 /* When module absent bit is set, check module */ 9542 if (rx_alarm_status & (1<<5)) { 9543 bnx2x_8727_handle_mod_abs(phy, params); 9544 /* Enable all mod_abs and link detection bits */ 9545 bnx2x_cl45_write(bp, phy, 9546 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, 9547 ((1<<5) | (1<<2))); 9548 } 9549 9550 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED)) { 9551 DP(NETIF_MSG_LINK, "Enabling 8727 TX laser\n"); 9552 bnx2x_sfp_set_transmitter(params, phy, 1); 9553 } else { 9554 DP(NETIF_MSG_LINK, "Tx is disabled\n"); 9555 return 0; 9556 } 9557 9558 bnx2x_cl45_read(bp, phy, 9559 MDIO_PMA_DEVAD, 9560 MDIO_PMA_REG_8073_SPEED_LINK_STATUS, &link_status); 9561 9562 /* Bits 0..2 --> speed detected, 9563 * Bits 13..15--> link is down 9564 */ 9565 if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) { 9566 link_up = 1; 9567 vars->line_speed = SPEED_10000; 9568 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n", 9569 params->port); 9570 } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) { 9571 link_up = 1; 9572 vars->line_speed = SPEED_1000; 9573 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n", 9574 params->port); 9575 } else { 9576 link_up = 0; 9577 DP(NETIF_MSG_LINK, "port %x: External link is down\n", 9578 params->port); 9579 } 9580 9581 /* Capture 10G link fault. */ 9582 if (vars->line_speed == SPEED_10000) { 9583 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 9584 MDIO_PMA_LASI_TXSTAT, &val1); 9585 9586 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 9587 MDIO_PMA_LASI_TXSTAT, &val1); 9588 9589 if (val1 & (1<<0)) { 9590 vars->fault_detected = 1; 9591 } 9592 } 9593 9594 if (link_up) { 9595 bnx2x_ext_phy_resolve_fc(phy, params, vars); 9596 vars->duplex = DUPLEX_FULL; 9597 DP(NETIF_MSG_LINK, "duplex = 0x%x\n", vars->duplex); 9598 } 9599 9600 if ((DUAL_MEDIA(params)) && 9601 (phy->req_line_speed == SPEED_1000)) { 9602 bnx2x_cl45_read(bp, phy, 9603 MDIO_PMA_DEVAD, 9604 MDIO_PMA_REG_8727_PCS_GP, &val1); 9605 /* In case of dual-media board and 1G, power up the XAUI side, 9606 * otherwise power it down. For 10G it is done automatically 9607 */ 9608 if (link_up) 9609 val1 &= ~(3<<10); 9610 else 9611 val1 |= (3<<10); 9612 bnx2x_cl45_write(bp, phy, 9613 MDIO_PMA_DEVAD, 9614 MDIO_PMA_REG_8727_PCS_GP, val1); 9615 } 9616 return link_up; 9617 } 9618 9619 static void bnx2x_8727_link_reset(struct bnx2x_phy *phy, 9620 struct link_params *params) 9621 { 9622 struct bnx2x *bp = params->bp; 9623 9624 /* Enable/Disable PHY transmitter output */ 9625 bnx2x_set_disable_pmd_transmit(params, phy, 1); 9626 9627 /* Disable Transmitter */ 9628 bnx2x_sfp_set_transmitter(params, phy, 0); 9629 /* Clear LASI */ 9630 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0); 9631 9632 } 9633 9634 /******************************************************************/ 9635 /* BCM8481/BCM84823/BCM84833 PHY SECTION */ 9636 /******************************************************************/ 9637 static int bnx2x_is_8483x_8485x(struct bnx2x_phy *phy) 9638 { 9639 return ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) || 9640 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) || 9641 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858)); 9642 } 9643 9644 static void bnx2x_save_848xx_spirom_version(struct bnx2x_phy *phy, 9645 struct bnx2x *bp, 9646 u8 port) 9647 { 9648 u16 val, fw_ver2, cnt, i; 9649 static struct bnx2x_reg_set reg_set[] = { 9650 {MDIO_PMA_DEVAD, 0xA819, 0x0014}, 9651 {MDIO_PMA_DEVAD, 0xA81A, 0xc200}, 9652 {MDIO_PMA_DEVAD, 0xA81B, 0x0000}, 9653 {MDIO_PMA_DEVAD, 0xA81C, 0x0300}, 9654 {MDIO_PMA_DEVAD, 0xA817, 0x0009} 9655 }; 9656 u16 fw_ver1; 9657 9658 if (bnx2x_is_8483x_8485x(phy)) { 9659 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 0x400f, &fw_ver1); 9660 if (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858) 9661 fw_ver1 &= 0xfff; 9662 bnx2x_save_spirom_version(bp, port, fw_ver1, phy->ver_addr); 9663 } else { 9664 /* For 32-bit registers in 848xx, access via MDIO2ARM i/f. */ 9665 /* (1) set reg 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */ 9666 for (i = 0; i < ARRAY_SIZE(reg_set); i++) 9667 bnx2x_cl45_write(bp, phy, reg_set[i].devad, 9668 reg_set[i].reg, reg_set[i].val); 9669 9670 for (cnt = 0; cnt < 100; cnt++) { 9671 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val); 9672 if (val & 1) 9673 break; 9674 udelay(5); 9675 } 9676 if (cnt == 100) { 9677 DP(NETIF_MSG_LINK, "Unable to read 848xx " 9678 "phy fw version(1)\n"); 9679 bnx2x_save_spirom_version(bp, port, 0, 9680 phy->ver_addr); 9681 return; 9682 } 9683 9684 9685 /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */ 9686 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0000); 9687 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200); 9688 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x000A); 9689 for (cnt = 0; cnt < 100; cnt++) { 9690 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val); 9691 if (val & 1) 9692 break; 9693 udelay(5); 9694 } 9695 if (cnt == 100) { 9696 DP(NETIF_MSG_LINK, "Unable to read 848xx phy fw " 9697 "version(2)\n"); 9698 bnx2x_save_spirom_version(bp, port, 0, 9699 phy->ver_addr); 9700 return; 9701 } 9702 9703 /* lower 16 bits of the register SPI_FW_STATUS */ 9704 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81B, &fw_ver1); 9705 /* upper 16 bits of register SPI_FW_STATUS */ 9706 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81C, &fw_ver2); 9707 9708 bnx2x_save_spirom_version(bp, port, (fw_ver2<<16) | fw_ver1, 9709 phy->ver_addr); 9710 } 9711 9712 } 9713 static void bnx2x_848xx_set_led(struct bnx2x *bp, 9714 struct bnx2x_phy *phy) 9715 { 9716 u16 val, led3_blink_rate, offset, i; 9717 static struct bnx2x_reg_set reg_set[] = { 9718 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED1_MASK, 0x0080}, 9719 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED2_MASK, 0x0018}, 9720 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED3_MASK, 0x0006}, 9721 {MDIO_PMA_DEVAD, MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH, 9722 MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ}, 9723 {MDIO_AN_DEVAD, 0xFFFB, 0xFFFD} 9724 }; 9725 9726 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858) { 9727 /* Set LED5 source */ 9728 bnx2x_cl45_write(bp, phy, 9729 MDIO_PMA_DEVAD, 9730 MDIO_PMA_REG_8481_LED5_MASK, 9731 0x90); 9732 led3_blink_rate = 0x000f; 9733 } else { 9734 led3_blink_rate = 0x0000; 9735 } 9736 /* Set LED3 BLINK */ 9737 bnx2x_cl45_write(bp, phy, 9738 MDIO_PMA_DEVAD, 9739 MDIO_PMA_REG_8481_LED3_BLINK, 9740 led3_blink_rate); 9741 9742 /* PHYC_CTL_LED_CTL */ 9743 bnx2x_cl45_read(bp, phy, 9744 MDIO_PMA_DEVAD, 9745 MDIO_PMA_REG_8481_LINK_SIGNAL, &val); 9746 val &= 0xFE00; 9747 val |= 0x0092; 9748 9749 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858) 9750 val |= 2 << 12; /* LED5 ON based on source */ 9751 9752 bnx2x_cl45_write(bp, phy, 9753 MDIO_PMA_DEVAD, 9754 MDIO_PMA_REG_8481_LINK_SIGNAL, val); 9755 9756 for (i = 0; i < ARRAY_SIZE(reg_set); i++) 9757 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg, 9758 reg_set[i].val); 9759 9760 if (bnx2x_is_8483x_8485x(phy)) 9761 offset = MDIO_PMA_REG_84833_CTL_LED_CTL_1; 9762 else 9763 offset = MDIO_PMA_REG_84823_CTL_LED_CTL_1; 9764 9765 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858) 9766 val = MDIO_PMA_REG_84858_ALLOW_GPHY_ACT | 9767 MDIO_PMA_REG_84823_LED3_STRETCH_EN; 9768 else 9769 val = MDIO_PMA_REG_84823_LED3_STRETCH_EN; 9770 9771 /* stretch_en for LEDs */ 9772 bnx2x_cl45_read_or_write(bp, phy, 9773 MDIO_PMA_DEVAD, 9774 offset, 9775 val); 9776 } 9777 9778 static void bnx2x_848xx_specific_func(struct bnx2x_phy *phy, 9779 struct link_params *params, 9780 u32 action) 9781 { 9782 struct bnx2x *bp = params->bp; 9783 switch (action) { 9784 case PHY_INIT: 9785 if (bnx2x_is_8483x_8485x(phy)) { 9786 /* Save spirom version */ 9787 bnx2x_save_848xx_spirom_version(phy, bp, params->port); 9788 } 9789 /* This phy uses the NIG latch mechanism since link indication 9790 * arrives through its LED4 and not via its LASI signal, so we 9791 * get steady signal instead of clear on read 9792 */ 9793 bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4, 9794 1 << NIG_LATCH_BC_ENABLE_MI_INT); 9795 9796 bnx2x_848xx_set_led(bp, phy); 9797 break; 9798 } 9799 } 9800 9801 static int bnx2x_848xx_cmn_config_init(struct bnx2x_phy *phy, 9802 struct link_params *params, 9803 struct link_vars *vars) 9804 { 9805 struct bnx2x *bp = params->bp; 9806 u16 autoneg_val, an_1000_val, an_10_100_val; 9807 9808 bnx2x_848xx_specific_func(phy, params, PHY_INIT); 9809 bnx2x_cl45_write(bp, phy, 9810 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0000); 9811 9812 /* set 1000 speed advertisement */ 9813 bnx2x_cl45_read(bp, phy, 9814 MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL, 9815 &an_1000_val); 9816 9817 bnx2x_ext_phy_set_pause(params, phy, vars); 9818 bnx2x_cl45_read(bp, phy, 9819 MDIO_AN_DEVAD, 9820 MDIO_AN_REG_8481_LEGACY_AN_ADV, 9821 &an_10_100_val); 9822 bnx2x_cl45_read(bp, phy, 9823 MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_MII_CTRL, 9824 &autoneg_val); 9825 /* Disable forced speed */ 9826 autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13)); 9827 an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8)); 9828 9829 if (((phy->req_line_speed == SPEED_AUTO_NEG) && 9830 (phy->speed_cap_mask & 9831 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) || 9832 (phy->req_line_speed == SPEED_1000)) { 9833 an_1000_val |= (1<<8); 9834 autoneg_val |= (1<<9 | 1<<12); 9835 if (phy->req_duplex == DUPLEX_FULL) 9836 an_1000_val |= (1<<9); 9837 DP(NETIF_MSG_LINK, "Advertising 1G\n"); 9838 } else 9839 an_1000_val &= ~((1<<8) | (1<<9)); 9840 9841 bnx2x_cl45_write(bp, phy, 9842 MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL, 9843 an_1000_val); 9844 9845 /* Set 10/100 speed advertisement */ 9846 if (phy->req_line_speed == SPEED_AUTO_NEG) { 9847 if (phy->speed_cap_mask & 9848 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL) { 9849 /* Enable autoneg and restart autoneg for legacy speeds 9850 */ 9851 autoneg_val |= (1<<9 | 1<<12); 9852 an_10_100_val |= (1<<8); 9853 DP(NETIF_MSG_LINK, "Advertising 100M-FD\n"); 9854 } 9855 9856 if (phy->speed_cap_mask & 9857 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF) { 9858 /* Enable autoneg and restart autoneg for legacy speeds 9859 */ 9860 autoneg_val |= (1<<9 | 1<<12); 9861 an_10_100_val |= (1<<7); 9862 DP(NETIF_MSG_LINK, "Advertising 100M-HD\n"); 9863 } 9864 9865 if ((phy->speed_cap_mask & 9866 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) && 9867 (phy->supported & SUPPORTED_10baseT_Full)) { 9868 an_10_100_val |= (1<<6); 9869 autoneg_val |= (1<<9 | 1<<12); 9870 DP(NETIF_MSG_LINK, "Advertising 10M-FD\n"); 9871 } 9872 9873 if ((phy->speed_cap_mask & 9874 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF) && 9875 (phy->supported & SUPPORTED_10baseT_Half)) { 9876 an_10_100_val |= (1<<5); 9877 autoneg_val |= (1<<9 | 1<<12); 9878 DP(NETIF_MSG_LINK, "Advertising 10M-HD\n"); 9879 } 9880 } 9881 9882 /* Only 10/100 are allowed to work in FORCE mode */ 9883 if ((phy->req_line_speed == SPEED_100) && 9884 (phy->supported & 9885 (SUPPORTED_100baseT_Half | 9886 SUPPORTED_100baseT_Full))) { 9887 autoneg_val |= (1<<13); 9888 /* Enabled AUTO-MDIX when autoneg is disabled */ 9889 bnx2x_cl45_write(bp, phy, 9890 MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL, 9891 (1<<15 | 1<<9 | 7<<0)); 9892 /* The PHY needs this set even for forced link. */ 9893 an_10_100_val |= (1<<8) | (1<<7); 9894 DP(NETIF_MSG_LINK, "Setting 100M force\n"); 9895 } 9896 if ((phy->req_line_speed == SPEED_10) && 9897 (phy->supported & 9898 (SUPPORTED_10baseT_Half | 9899 SUPPORTED_10baseT_Full))) { 9900 /* Enabled AUTO-MDIX when autoneg is disabled */ 9901 bnx2x_cl45_write(bp, phy, 9902 MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL, 9903 (1<<15 | 1<<9 | 7<<0)); 9904 DP(NETIF_MSG_LINK, "Setting 10M force\n"); 9905 } 9906 9907 bnx2x_cl45_write(bp, phy, 9908 MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_AN_ADV, 9909 an_10_100_val); 9910 9911 if (phy->req_duplex == DUPLEX_FULL) 9912 autoneg_val |= (1<<8); 9913 9914 /* Always write this if this is not 84833/4. 9915 * For 84833/4, write it only when it's a forced speed. 9916 */ 9917 if (!bnx2x_is_8483x_8485x(phy) || 9918 ((autoneg_val & (1<<12)) == 0)) 9919 bnx2x_cl45_write(bp, phy, 9920 MDIO_AN_DEVAD, 9921 MDIO_AN_REG_8481_LEGACY_MII_CTRL, autoneg_val); 9922 9923 if (((phy->req_line_speed == SPEED_AUTO_NEG) && 9924 (phy->speed_cap_mask & 9925 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) || 9926 (phy->req_line_speed == SPEED_10000)) { 9927 DP(NETIF_MSG_LINK, "Advertising 10G\n"); 9928 /* Restart autoneg for 10G*/ 9929 9930 bnx2x_cl45_read_or_write( 9931 bp, phy, 9932 MDIO_AN_DEVAD, 9933 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL, 9934 0x1000); 9935 bnx2x_cl45_write(bp, phy, 9936 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 9937 0x3200); 9938 } else 9939 bnx2x_cl45_write(bp, phy, 9940 MDIO_AN_DEVAD, 9941 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL, 9942 1); 9943 9944 return 0; 9945 } 9946 9947 static void bnx2x_8481_config_init(struct bnx2x_phy *phy, 9948 struct link_params *params, 9949 struct link_vars *vars) 9950 { 9951 struct bnx2x *bp = params->bp; 9952 /* Restore normal power mode*/ 9953 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 9954 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); 9955 9956 /* HW reset */ 9957 bnx2x_ext_phy_hw_reset(bp, params->port); 9958 bnx2x_wait_reset_complete(bp, phy, params); 9959 9960 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15); 9961 bnx2x_848xx_cmn_config_init(phy, params, vars); 9962 } 9963 9964 #define PHY848xx_CMDHDLR_WAIT 300 9965 #define PHY848xx_CMDHDLR_MAX_ARGS 5 9966 9967 static int bnx2x_84858_cmd_hdlr(struct bnx2x_phy *phy, 9968 struct link_params *params, 9969 u16 fw_cmd, 9970 u16 cmd_args[], int argc) 9971 { 9972 int idx; 9973 u16 val; 9974 struct bnx2x *bp = params->bp; 9975 9976 /* Step 1: Poll the STATUS register to see whether the previous command 9977 * is in progress or the system is busy (CMD_IN_PROGRESS or 9978 * SYSTEM_BUSY). If previous command is in progress or system is busy, 9979 * check again until the previous command finishes execution and the 9980 * system is available for taking command 9981 */ 9982 9983 for (idx = 0; idx < PHY848xx_CMDHDLR_WAIT; idx++) { 9984 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 9985 MDIO_848xx_CMD_HDLR_STATUS, &val); 9986 if ((val != PHY84858_STATUS_CMD_IN_PROGRESS) && 9987 (val != PHY84858_STATUS_CMD_SYSTEM_BUSY)) 9988 break; 9989 usleep_range(1000, 2000); 9990 } 9991 if (idx >= PHY848xx_CMDHDLR_WAIT) { 9992 DP(NETIF_MSG_LINK, "FW cmd: FW not ready.\n"); 9993 return -EINVAL; 9994 } 9995 9996 /* Step2: If any parameters are required for the function, write them 9997 * to the required DATA registers 9998 */ 9999 10000 for (idx = 0; idx < argc; idx++) { 10001 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, 10002 MDIO_848xx_CMD_HDLR_DATA1 + idx, 10003 cmd_args[idx]); 10004 } 10005 10006 /* Step3: When the firmware is ready for commands, write the 'Command 10007 * code' to the CMD register 10008 */ 10009 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, 10010 MDIO_848xx_CMD_HDLR_COMMAND, fw_cmd); 10011 10012 /* Step4: Once the command has been written, poll the STATUS register 10013 * to check whether the command has completed (CMD_COMPLETED_PASS/ 10014 * CMD_FOR_CMDS or CMD_COMPLETED_ERROR). 10015 */ 10016 10017 for (idx = 0; idx < PHY848xx_CMDHDLR_WAIT; idx++) { 10018 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 10019 MDIO_848xx_CMD_HDLR_STATUS, &val); 10020 if ((val == PHY84858_STATUS_CMD_COMPLETE_PASS) || 10021 (val == PHY84858_STATUS_CMD_COMPLETE_ERROR)) 10022 break; 10023 usleep_range(1000, 2000); 10024 } 10025 if ((idx >= PHY848xx_CMDHDLR_WAIT) || 10026 (val == PHY84858_STATUS_CMD_COMPLETE_ERROR)) { 10027 DP(NETIF_MSG_LINK, "FW cmd failed.\n"); 10028 return -EINVAL; 10029 } 10030 /* Step5: Once the command has completed, read the specficied DATA 10031 * registers for any saved results for the command, if applicable 10032 */ 10033 10034 /* Gather returning data */ 10035 for (idx = 0; idx < argc; idx++) { 10036 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 10037 MDIO_848xx_CMD_HDLR_DATA1 + idx, 10038 &cmd_args[idx]); 10039 } 10040 10041 return 0; 10042 } 10043 10044 static int bnx2x_84833_cmd_hdlr(struct bnx2x_phy *phy, 10045 struct link_params *params, u16 fw_cmd, 10046 u16 cmd_args[], int argc, int process) 10047 { 10048 int idx; 10049 u16 val; 10050 struct bnx2x *bp = params->bp; 10051 int rc = 0; 10052 10053 if (process == PHY84833_MB_PROCESS2) { 10054 /* Write CMD_OPEN_OVERRIDE to STATUS reg */ 10055 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, 10056 MDIO_848xx_CMD_HDLR_STATUS, 10057 PHY84833_STATUS_CMD_OPEN_OVERRIDE); 10058 } 10059 10060 for (idx = 0; idx < PHY848xx_CMDHDLR_WAIT; idx++) { 10061 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 10062 MDIO_848xx_CMD_HDLR_STATUS, &val); 10063 if (val == PHY84833_STATUS_CMD_OPEN_FOR_CMDS) 10064 break; 10065 usleep_range(1000, 2000); 10066 } 10067 if (idx >= PHY848xx_CMDHDLR_WAIT) { 10068 DP(NETIF_MSG_LINK, "FW cmd: FW not ready.\n"); 10069 /* if the status is CMD_COMPLETE_PASS or CMD_COMPLETE_ERROR 10070 * clear the status to CMD_CLEAR_COMPLETE 10071 */ 10072 if (val == PHY84833_STATUS_CMD_COMPLETE_PASS || 10073 val == PHY84833_STATUS_CMD_COMPLETE_ERROR) { 10074 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, 10075 MDIO_848xx_CMD_HDLR_STATUS, 10076 PHY84833_STATUS_CMD_CLEAR_COMPLETE); 10077 } 10078 return -EINVAL; 10079 } 10080 if (process == PHY84833_MB_PROCESS1 || 10081 process == PHY84833_MB_PROCESS2) { 10082 /* Prepare argument(s) */ 10083 for (idx = 0; idx < argc; idx++) { 10084 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, 10085 MDIO_848xx_CMD_HDLR_DATA1 + idx, 10086 cmd_args[idx]); 10087 } 10088 } 10089 10090 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, 10091 MDIO_848xx_CMD_HDLR_COMMAND, fw_cmd); 10092 for (idx = 0; idx < PHY848xx_CMDHDLR_WAIT; idx++) { 10093 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 10094 MDIO_848xx_CMD_HDLR_STATUS, &val); 10095 if ((val == PHY84833_STATUS_CMD_COMPLETE_PASS) || 10096 (val == PHY84833_STATUS_CMD_COMPLETE_ERROR)) 10097 break; 10098 usleep_range(1000, 2000); 10099 } 10100 if ((idx >= PHY848xx_CMDHDLR_WAIT) || 10101 (val == PHY84833_STATUS_CMD_COMPLETE_ERROR)) { 10102 DP(NETIF_MSG_LINK, "FW cmd failed.\n"); 10103 rc = -EINVAL; 10104 } 10105 if (process == PHY84833_MB_PROCESS3 && rc == 0) { 10106 /* Gather returning data */ 10107 for (idx = 0; idx < argc; idx++) { 10108 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 10109 MDIO_848xx_CMD_HDLR_DATA1 + idx, 10110 &cmd_args[idx]); 10111 } 10112 } 10113 if (val == PHY84833_STATUS_CMD_COMPLETE_ERROR || 10114 val == PHY84833_STATUS_CMD_COMPLETE_PASS) { 10115 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, 10116 MDIO_848xx_CMD_HDLR_STATUS, 10117 PHY84833_STATUS_CMD_CLEAR_COMPLETE); 10118 } 10119 return rc; 10120 } 10121 10122 static int bnx2x_848xx_cmd_hdlr(struct bnx2x_phy *phy, 10123 struct link_params *params, 10124 u16 fw_cmd, 10125 u16 cmd_args[], int argc, 10126 int process) 10127 { 10128 struct bnx2x *bp = params->bp; 10129 10130 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858) || 10131 (REG_RD(bp, params->shmem2_base + 10132 offsetof(struct shmem2_region, 10133 link_attr_sync[params->port])) & 10134 LINK_ATTR_84858)) { 10135 return bnx2x_84858_cmd_hdlr(phy, params, fw_cmd, cmd_args, 10136 argc); 10137 } else { 10138 return bnx2x_84833_cmd_hdlr(phy, params, fw_cmd, cmd_args, 10139 argc, process); 10140 } 10141 } 10142 10143 static int bnx2x_848xx_pair_swap_cfg(struct bnx2x_phy *phy, 10144 struct link_params *params, 10145 struct link_vars *vars) 10146 { 10147 u32 pair_swap; 10148 u16 data[PHY848xx_CMDHDLR_MAX_ARGS]; 10149 int status; 10150 struct bnx2x *bp = params->bp; 10151 10152 /* Check for configuration. */ 10153 pair_swap = REG_RD(bp, params->shmem_base + 10154 offsetof(struct shmem_region, 10155 dev_info.port_hw_config[params->port].xgbt_phy_cfg)) & 10156 PORT_HW_CFG_RJ45_PAIR_SWAP_MASK; 10157 10158 if (pair_swap == 0) 10159 return 0; 10160 10161 /* Only the second argument is used for this command */ 10162 data[1] = (u16)pair_swap; 10163 10164 status = bnx2x_848xx_cmd_hdlr(phy, params, 10165 PHY848xx_CMD_SET_PAIR_SWAP, data, 10166 2, PHY84833_MB_PROCESS2); 10167 if (status == 0) 10168 DP(NETIF_MSG_LINK, "Pairswap OK, val=0x%x\n", data[1]); 10169 10170 return status; 10171 } 10172 10173 static u8 bnx2x_84833_get_reset_gpios(struct bnx2x *bp, 10174 u32 shmem_base_path[], 10175 u32 chip_id) 10176 { 10177 u32 reset_pin[2]; 10178 u32 idx; 10179 u8 reset_gpios; 10180 if (CHIP_IS_E3(bp)) { 10181 /* Assume that these will be GPIOs, not EPIOs. */ 10182 for (idx = 0; idx < 2; idx++) { 10183 /* Map config param to register bit. */ 10184 reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] + 10185 offsetof(struct shmem_region, 10186 dev_info.port_hw_config[0].e3_cmn_pin_cfg)); 10187 reset_pin[idx] = (reset_pin[idx] & 10188 PORT_HW_CFG_E3_PHY_RESET_MASK) >> 10189 PORT_HW_CFG_E3_PHY_RESET_SHIFT; 10190 reset_pin[idx] -= PIN_CFG_GPIO0_P0; 10191 reset_pin[idx] = (1 << reset_pin[idx]); 10192 } 10193 reset_gpios = (u8)(reset_pin[0] | reset_pin[1]); 10194 } else { 10195 /* E2, look from diff place of shmem. */ 10196 for (idx = 0; idx < 2; idx++) { 10197 reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] + 10198 offsetof(struct shmem_region, 10199 dev_info.port_hw_config[0].default_cfg)); 10200 reset_pin[idx] &= PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK; 10201 reset_pin[idx] -= PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0; 10202 reset_pin[idx] >>= PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT; 10203 reset_pin[idx] = (1 << reset_pin[idx]); 10204 } 10205 reset_gpios = (u8)(reset_pin[0] | reset_pin[1]); 10206 } 10207 10208 return reset_gpios; 10209 } 10210 10211 static void bnx2x_84833_hw_reset_phy(struct bnx2x_phy *phy, 10212 struct link_params *params) 10213 { 10214 struct bnx2x *bp = params->bp; 10215 u8 reset_gpios; 10216 u32 other_shmem_base_addr = REG_RD(bp, params->shmem2_base + 10217 offsetof(struct shmem2_region, 10218 other_shmem_base_addr)); 10219 10220 u32 shmem_base_path[2]; 10221 10222 /* Work around for 84833 LED failure inside RESET status */ 10223 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, 10224 MDIO_AN_REG_8481_LEGACY_MII_CTRL, 10225 MDIO_AN_REG_8481_MII_CTRL_FORCE_1G); 10226 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, 10227 MDIO_AN_REG_8481_1G_100T_EXT_CTRL, 10228 MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF); 10229 10230 shmem_base_path[0] = params->shmem_base; 10231 shmem_base_path[1] = other_shmem_base_addr; 10232 10233 reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path, 10234 params->chip_id); 10235 10236 bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW); 10237 udelay(10); 10238 DP(NETIF_MSG_LINK, "84833 hw reset on pin values 0x%x\n", 10239 reset_gpios); 10240 } 10241 10242 static int bnx2x_8483x_disable_eee(struct bnx2x_phy *phy, 10243 struct link_params *params, 10244 struct link_vars *vars) 10245 { 10246 int rc; 10247 struct bnx2x *bp = params->bp; 10248 u16 cmd_args = 0; 10249 10250 DP(NETIF_MSG_LINK, "Don't Advertise 10GBase-T EEE\n"); 10251 10252 /* Prevent Phy from working in EEE and advertising it */ 10253 rc = bnx2x_848xx_cmd_hdlr(phy, params, PHY848xx_CMD_SET_EEE_MODE, 10254 &cmd_args, 1, PHY84833_MB_PROCESS1); 10255 if (rc) { 10256 DP(NETIF_MSG_LINK, "EEE disable failed.\n"); 10257 return rc; 10258 } 10259 10260 return bnx2x_eee_disable(phy, params, vars); 10261 } 10262 10263 static int bnx2x_8483x_enable_eee(struct bnx2x_phy *phy, 10264 struct link_params *params, 10265 struct link_vars *vars) 10266 { 10267 int rc; 10268 struct bnx2x *bp = params->bp; 10269 u16 cmd_args = 1; 10270 10271 rc = bnx2x_848xx_cmd_hdlr(phy, params, PHY848xx_CMD_SET_EEE_MODE, 10272 &cmd_args, 1, PHY84833_MB_PROCESS1); 10273 if (rc) { 10274 DP(NETIF_MSG_LINK, "EEE enable failed.\n"); 10275 return rc; 10276 } 10277 10278 return bnx2x_eee_advertise(phy, params, vars, SHMEM_EEE_10G_ADV); 10279 } 10280 10281 #define PHY84833_CONSTANT_LATENCY 1193 10282 static void bnx2x_848x3_config_init(struct bnx2x_phy *phy, 10283 struct link_params *params, 10284 struct link_vars *vars) 10285 { 10286 struct bnx2x *bp = params->bp; 10287 u8 port, initialize = 1; 10288 u16 val; 10289 u32 actual_phy_selection; 10290 u16 cmd_args[PHY848xx_CMDHDLR_MAX_ARGS]; 10291 int rc = 0; 10292 10293 usleep_range(1000, 2000); 10294 10295 if (!(CHIP_IS_E1x(bp))) 10296 port = BP_PATH(bp); 10297 else 10298 port = params->port; 10299 10300 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) { 10301 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3, 10302 MISC_REGISTERS_GPIO_OUTPUT_HIGH, 10303 port); 10304 } else { 10305 /* MDIO reset */ 10306 bnx2x_cl45_write(bp, phy, 10307 MDIO_PMA_DEVAD, 10308 MDIO_PMA_REG_CTRL, 0x8000); 10309 } 10310 10311 bnx2x_wait_reset_complete(bp, phy, params); 10312 10313 /* Wait for GPHY to come out of reset */ 10314 msleep(50); 10315 if (!bnx2x_is_8483x_8485x(phy)) { 10316 /* BCM84823 requires that XGXS links up first @ 10G for normal 10317 * behavior. 10318 */ 10319 u16 temp; 10320 temp = vars->line_speed; 10321 vars->line_speed = SPEED_10000; 10322 bnx2x_set_autoneg(¶ms->phy[INT_PHY], params, vars, 0); 10323 bnx2x_program_serdes(¶ms->phy[INT_PHY], params, vars); 10324 vars->line_speed = temp; 10325 } 10326 /* Check if this is actually BCM84858 */ 10327 if (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858) { 10328 u16 hw_rev; 10329 10330 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, 10331 MDIO_AN_REG_848xx_ID_MSB, &hw_rev); 10332 if (hw_rev == BCM84858_PHY_ID) { 10333 params->link_attr_sync |= LINK_ATTR_84858; 10334 bnx2x_update_link_attr(params, params->link_attr_sync); 10335 } 10336 } 10337 10338 /* Set dual-media configuration according to configuration */ 10339 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 10340 MDIO_CTL_REG_84823_MEDIA, &val); 10341 val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK | 10342 MDIO_CTL_REG_84823_MEDIA_LINE_MASK | 10343 MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN | 10344 MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK | 10345 MDIO_CTL_REG_84823_MEDIA_FIBER_1G); 10346 10347 if (CHIP_IS_E3(bp)) { 10348 val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK | 10349 MDIO_CTL_REG_84823_MEDIA_LINE_MASK); 10350 } else { 10351 val |= (MDIO_CTL_REG_84823_CTRL_MAC_XFI | 10352 MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L); 10353 } 10354 10355 actual_phy_selection = bnx2x_phy_selection(params); 10356 10357 switch (actual_phy_selection) { 10358 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT: 10359 /* Do nothing. Essentially this is like the priority copper */ 10360 break; 10361 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY: 10362 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER; 10363 break; 10364 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY: 10365 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER; 10366 break; 10367 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY: 10368 /* Do nothing here. The first PHY won't be initialized at all */ 10369 break; 10370 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY: 10371 val |= MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN; 10372 initialize = 0; 10373 break; 10374 } 10375 if (params->phy[EXT_PHY2].req_line_speed == SPEED_1000) 10376 val |= MDIO_CTL_REG_84823_MEDIA_FIBER_1G; 10377 10378 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, 10379 MDIO_CTL_REG_84823_MEDIA, val); 10380 DP(NETIF_MSG_LINK, "Multi_phy config = 0x%x, Media control = 0x%x\n", 10381 params->multi_phy_config, val); 10382 10383 if (bnx2x_is_8483x_8485x(phy)) { 10384 bnx2x_848xx_pair_swap_cfg(phy, params, vars); 10385 10386 /* Keep AutogrEEEn disabled. */ 10387 cmd_args[0] = 0x0; 10388 cmd_args[1] = 0x0; 10389 cmd_args[2] = PHY84833_CONSTANT_LATENCY + 1; 10390 cmd_args[3] = PHY84833_CONSTANT_LATENCY; 10391 rc = bnx2x_848xx_cmd_hdlr(phy, params, 10392 PHY848xx_CMD_SET_EEE_MODE, cmd_args, 10393 4, PHY84833_MB_PROCESS1); 10394 if (rc) 10395 DP(NETIF_MSG_LINK, "Cfg AutogrEEEn failed.\n"); 10396 } 10397 if (initialize) 10398 rc = bnx2x_848xx_cmn_config_init(phy, params, vars); 10399 else 10400 bnx2x_save_848xx_spirom_version(phy, bp, params->port); 10401 /* 84833 PHY has a better feature and doesn't need to support this. */ 10402 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) { 10403 u32 cms_enable = REG_RD(bp, params->shmem_base + 10404 offsetof(struct shmem_region, 10405 dev_info.port_hw_config[params->port].default_cfg)) & 10406 PORT_HW_CFG_ENABLE_CMS_MASK; 10407 10408 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 10409 MDIO_CTL_REG_84823_USER_CTRL_REG, &val); 10410 if (cms_enable) 10411 val |= MDIO_CTL_REG_84823_USER_CTRL_CMS; 10412 else 10413 val &= ~MDIO_CTL_REG_84823_USER_CTRL_CMS; 10414 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, 10415 MDIO_CTL_REG_84823_USER_CTRL_REG, val); 10416 } 10417 10418 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 10419 MDIO_84833_TOP_CFG_FW_REV, &val); 10420 10421 /* Configure EEE support */ 10422 if ((val >= MDIO_84833_TOP_CFG_FW_EEE) && 10423 (val != MDIO_84833_TOP_CFG_FW_NO_EEE) && 10424 bnx2x_eee_has_cap(params)) { 10425 rc = bnx2x_eee_initial_config(params, vars, SHMEM_EEE_10G_ADV); 10426 if (rc) { 10427 DP(NETIF_MSG_LINK, "Failed to configure EEE timers\n"); 10428 bnx2x_8483x_disable_eee(phy, params, vars); 10429 return; 10430 } 10431 10432 if ((phy->req_duplex == DUPLEX_FULL) && 10433 (params->eee_mode & EEE_MODE_ADV_LPI) && 10434 (bnx2x_eee_calc_timer(params) || 10435 !(params->eee_mode & EEE_MODE_ENABLE_LPI))) 10436 rc = bnx2x_8483x_enable_eee(phy, params, vars); 10437 else 10438 rc = bnx2x_8483x_disable_eee(phy, params, vars); 10439 if (rc) { 10440 DP(NETIF_MSG_LINK, "Failed to set EEE advertisement\n"); 10441 return; 10442 } 10443 } else { 10444 vars->eee_status &= ~SHMEM_EEE_SUPPORTED_MASK; 10445 } 10446 10447 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) { 10448 /* Additional settings for jumbo packets in 1000BASE-T mode */ 10449 /* Allow rx extended length */ 10450 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, 10451 MDIO_AN_REG_8481_AUX_CTRL, &val); 10452 val |= 0x4000; 10453 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, 10454 MDIO_AN_REG_8481_AUX_CTRL, val); 10455 /* TX FIFO Elasticity LSB */ 10456 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, 10457 MDIO_AN_REG_8481_1G_100T_EXT_CTRL, &val); 10458 val |= 0x1; 10459 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, 10460 MDIO_AN_REG_8481_1G_100T_EXT_CTRL, val); 10461 /* TX FIFO Elasticity MSB */ 10462 /* Enable expansion register 0x46 (Pattern Generator status) */ 10463 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, 10464 MDIO_AN_REG_8481_EXPANSION_REG_ACCESS, 0xf46); 10465 10466 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, 10467 MDIO_AN_REG_8481_EXPANSION_REG_RD_RW, &val); 10468 val |= 0x4000; 10469 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, 10470 MDIO_AN_REG_8481_EXPANSION_REG_RD_RW, val); 10471 } 10472 10473 if (bnx2x_is_8483x_8485x(phy)) { 10474 /* Bring PHY out of super isolate mode as the final step. */ 10475 bnx2x_cl45_read_and_write(bp, phy, 10476 MDIO_CTL_DEVAD, 10477 MDIO_84833_TOP_CFG_XGPHY_STRAP1, 10478 (u16)~MDIO_84833_SUPER_ISOLATE); 10479 } 10480 } 10481 10482 static u8 bnx2x_848xx_read_status(struct bnx2x_phy *phy, 10483 struct link_params *params, 10484 struct link_vars *vars) 10485 { 10486 struct bnx2x *bp = params->bp; 10487 u16 val, val1, val2; 10488 u8 link_up = 0; 10489 10490 10491 /* Check 10G-BaseT link status */ 10492 /* Check PMD signal ok */ 10493 bnx2x_cl45_read(bp, phy, 10494 MDIO_AN_DEVAD, 0xFFFA, &val1); 10495 bnx2x_cl45_read(bp, phy, 10496 MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_PMD_SIGNAL, 10497 &val2); 10498 DP(NETIF_MSG_LINK, "BCM848xx: PMD_SIGNAL 1.a811 = 0x%x\n", val2); 10499 10500 /* Check link 10G */ 10501 if (val2 & (1<<11)) { 10502 vars->line_speed = SPEED_10000; 10503 vars->duplex = DUPLEX_FULL; 10504 link_up = 1; 10505 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars); 10506 } else { /* Check Legacy speed link */ 10507 u16 legacy_status, legacy_speed; 10508 10509 /* Enable expansion register 0x42 (Operation mode status) */ 10510 bnx2x_cl45_write(bp, phy, 10511 MDIO_AN_DEVAD, 10512 MDIO_AN_REG_8481_EXPANSION_REG_ACCESS, 0xf42); 10513 10514 /* Get legacy speed operation status */ 10515 bnx2x_cl45_read(bp, phy, 10516 MDIO_AN_DEVAD, 10517 MDIO_AN_REG_8481_EXPANSION_REG_RD_RW, 10518 &legacy_status); 10519 10520 DP(NETIF_MSG_LINK, "Legacy speed status = 0x%x\n", 10521 legacy_status); 10522 link_up = ((legacy_status & (1<<11)) == (1<<11)); 10523 legacy_speed = (legacy_status & (3<<9)); 10524 if (legacy_speed == (0<<9)) 10525 vars->line_speed = SPEED_10; 10526 else if (legacy_speed == (1<<9)) 10527 vars->line_speed = SPEED_100; 10528 else if (legacy_speed == (2<<9)) 10529 vars->line_speed = SPEED_1000; 10530 else { /* Should not happen: Treat as link down */ 10531 vars->line_speed = 0; 10532 link_up = 0; 10533 } 10534 10535 if (link_up) { 10536 if (legacy_status & (1<<8)) 10537 vars->duplex = DUPLEX_FULL; 10538 else 10539 vars->duplex = DUPLEX_HALF; 10540 10541 DP(NETIF_MSG_LINK, 10542 "Link is up in %dMbps, is_duplex_full= %d\n", 10543 vars->line_speed, 10544 (vars->duplex == DUPLEX_FULL)); 10545 /* Check legacy speed AN resolution */ 10546 bnx2x_cl45_read(bp, phy, 10547 MDIO_AN_DEVAD, 10548 MDIO_AN_REG_8481_LEGACY_MII_STATUS, 10549 &val); 10550 if (val & (1<<5)) 10551 vars->link_status |= 10552 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; 10553 bnx2x_cl45_read(bp, phy, 10554 MDIO_AN_DEVAD, 10555 MDIO_AN_REG_8481_LEGACY_AN_EXPANSION, 10556 &val); 10557 if ((val & (1<<0)) == 0) 10558 vars->link_status |= 10559 LINK_STATUS_PARALLEL_DETECTION_USED; 10560 } 10561 } 10562 if (link_up) { 10563 DP(NETIF_MSG_LINK, "BCM848x3: link speed is %d\n", 10564 vars->line_speed); 10565 bnx2x_ext_phy_resolve_fc(phy, params, vars); 10566 10567 /* Read LP advertised speeds */ 10568 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, 10569 MDIO_AN_REG_CL37_FC_LP, &val); 10570 if (val & (1<<5)) 10571 vars->link_status |= 10572 LINK_STATUS_LINK_PARTNER_10THD_CAPABLE; 10573 if (val & (1<<6)) 10574 vars->link_status |= 10575 LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE; 10576 if (val & (1<<7)) 10577 vars->link_status |= 10578 LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE; 10579 if (val & (1<<8)) 10580 vars->link_status |= 10581 LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE; 10582 if (val & (1<<9)) 10583 vars->link_status |= 10584 LINK_STATUS_LINK_PARTNER_100T4_CAPABLE; 10585 10586 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, 10587 MDIO_AN_REG_1000T_STATUS, &val); 10588 10589 if (val & (1<<10)) 10590 vars->link_status |= 10591 LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE; 10592 if (val & (1<<11)) 10593 vars->link_status |= 10594 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; 10595 10596 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, 10597 MDIO_AN_REG_MASTER_STATUS, &val); 10598 10599 if (val & (1<<11)) 10600 vars->link_status |= 10601 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; 10602 10603 /* Determine if EEE was negotiated */ 10604 if (bnx2x_is_8483x_8485x(phy)) 10605 bnx2x_eee_an_resolve(phy, params, vars); 10606 } 10607 10608 return link_up; 10609 } 10610 10611 static int bnx2x_8485x_format_ver(u32 raw_ver, u8 *str, u16 *len) 10612 { 10613 u32 num; 10614 10615 num = ((raw_ver & 0xF80) >> 7) << 16 | ((raw_ver & 0x7F) << 8) | 10616 ((raw_ver & 0xF000) >> 12); 10617 return bnx2x_3_seq_format_ver(num, str, len); 10618 } 10619 10620 static int bnx2x_848xx_format_ver(u32 raw_ver, u8 *str, u16 *len) 10621 { 10622 u32 spirom_ver; 10623 10624 spirom_ver = ((raw_ver & 0xF80) >> 7) << 16 | (raw_ver & 0x7F); 10625 return bnx2x_format_ver(spirom_ver, str, len); 10626 } 10627 10628 static void bnx2x_8481_hw_reset(struct bnx2x_phy *phy, 10629 struct link_params *params) 10630 { 10631 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1, 10632 MISC_REGISTERS_GPIO_OUTPUT_LOW, 0); 10633 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1, 10634 MISC_REGISTERS_GPIO_OUTPUT_LOW, 1); 10635 } 10636 10637 static void bnx2x_8481_link_reset(struct bnx2x_phy *phy, 10638 struct link_params *params) 10639 { 10640 bnx2x_cl45_write(params->bp, phy, 10641 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000); 10642 bnx2x_cl45_write(params->bp, phy, 10643 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1); 10644 } 10645 10646 static void bnx2x_848x3_link_reset(struct bnx2x_phy *phy, 10647 struct link_params *params) 10648 { 10649 struct bnx2x *bp = params->bp; 10650 u8 port; 10651 u16 val16; 10652 10653 if (!(CHIP_IS_E1x(bp))) 10654 port = BP_PATH(bp); 10655 else 10656 port = params->port; 10657 10658 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) { 10659 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3, 10660 MISC_REGISTERS_GPIO_OUTPUT_LOW, 10661 port); 10662 } else { 10663 bnx2x_cl45_read(bp, phy, 10664 MDIO_CTL_DEVAD, 10665 MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val16); 10666 val16 |= MDIO_84833_SUPER_ISOLATE; 10667 bnx2x_cl45_write(bp, phy, 10668 MDIO_CTL_DEVAD, 10669 MDIO_84833_TOP_CFG_XGPHY_STRAP1, val16); 10670 } 10671 } 10672 10673 static void bnx2x_848xx_set_link_led(struct bnx2x_phy *phy, 10674 struct link_params *params, u8 mode) 10675 { 10676 struct bnx2x *bp = params->bp; 10677 u16 val; 10678 u8 port; 10679 10680 if (!(CHIP_IS_E1x(bp))) 10681 port = BP_PATH(bp); 10682 else 10683 port = params->port; 10684 10685 switch (mode) { 10686 case LED_MODE_OFF: 10687 10688 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OFF\n", port); 10689 10690 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) == 10691 SHARED_HW_CFG_LED_EXTPHY1) { 10692 10693 /* Set LED masks */ 10694 bnx2x_cl45_write(bp, phy, 10695 MDIO_PMA_DEVAD, 10696 MDIO_PMA_REG_8481_LED1_MASK, 10697 0x0); 10698 10699 bnx2x_cl45_write(bp, phy, 10700 MDIO_PMA_DEVAD, 10701 MDIO_PMA_REG_8481_LED2_MASK, 10702 0x0); 10703 10704 bnx2x_cl45_write(bp, phy, 10705 MDIO_PMA_DEVAD, 10706 MDIO_PMA_REG_8481_LED3_MASK, 10707 0x0); 10708 10709 bnx2x_cl45_write(bp, phy, 10710 MDIO_PMA_DEVAD, 10711 MDIO_PMA_REG_8481_LED5_MASK, 10712 0x0); 10713 10714 } else { 10715 /* LED 1 OFF */ 10716 bnx2x_cl45_write(bp, phy, 10717 MDIO_PMA_DEVAD, 10718 MDIO_PMA_REG_8481_LED1_MASK, 10719 0x0); 10720 10721 if (phy->type == 10722 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858) { 10723 /* LED 2 OFF */ 10724 bnx2x_cl45_write(bp, phy, 10725 MDIO_PMA_DEVAD, 10726 MDIO_PMA_REG_8481_LED2_MASK, 10727 0x0); 10728 /* LED 3 OFF */ 10729 bnx2x_cl45_write(bp, phy, 10730 MDIO_PMA_DEVAD, 10731 MDIO_PMA_REG_8481_LED3_MASK, 10732 0x0); 10733 } 10734 } 10735 break; 10736 case LED_MODE_FRONT_PANEL_OFF: 10737 10738 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE FRONT PANEL OFF\n", 10739 port); 10740 10741 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) == 10742 SHARED_HW_CFG_LED_EXTPHY1) { 10743 10744 /* Set LED masks */ 10745 bnx2x_cl45_write(bp, phy, 10746 MDIO_PMA_DEVAD, 10747 MDIO_PMA_REG_8481_LED1_MASK, 10748 0x0); 10749 10750 bnx2x_cl45_write(bp, phy, 10751 MDIO_PMA_DEVAD, 10752 MDIO_PMA_REG_8481_LED2_MASK, 10753 0x0); 10754 10755 bnx2x_cl45_write(bp, phy, 10756 MDIO_PMA_DEVAD, 10757 MDIO_PMA_REG_8481_LED3_MASK, 10758 0x0); 10759 10760 bnx2x_cl45_write(bp, phy, 10761 MDIO_PMA_DEVAD, 10762 MDIO_PMA_REG_8481_LED5_MASK, 10763 0x20); 10764 10765 } else { 10766 bnx2x_cl45_write(bp, phy, 10767 MDIO_PMA_DEVAD, 10768 MDIO_PMA_REG_8481_LED1_MASK, 10769 0x0); 10770 if (phy->type == 10771 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) { 10772 /* Disable MI_INT interrupt before setting LED4 10773 * source to constant off. 10774 */ 10775 if (REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + 10776 params->port*4) & 10777 NIG_MASK_MI_INT) { 10778 params->link_flags |= 10779 LINK_FLAGS_INT_DISABLED; 10780 10781 bnx2x_bits_dis( 10782 bp, 10783 NIG_REG_MASK_INTERRUPT_PORT0 + 10784 params->port*4, 10785 NIG_MASK_MI_INT); 10786 } 10787 bnx2x_cl45_write(bp, phy, 10788 MDIO_PMA_DEVAD, 10789 MDIO_PMA_REG_8481_SIGNAL_MASK, 10790 0x0); 10791 } 10792 if (phy->type == 10793 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858) { 10794 /* LED 2 OFF */ 10795 bnx2x_cl45_write(bp, phy, 10796 MDIO_PMA_DEVAD, 10797 MDIO_PMA_REG_8481_LED2_MASK, 10798 0x0); 10799 /* LED 3 OFF */ 10800 bnx2x_cl45_write(bp, phy, 10801 MDIO_PMA_DEVAD, 10802 MDIO_PMA_REG_8481_LED3_MASK, 10803 0x0); 10804 } 10805 } 10806 break; 10807 case LED_MODE_ON: 10808 10809 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE ON\n", port); 10810 10811 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) == 10812 SHARED_HW_CFG_LED_EXTPHY1) { 10813 /* Set control reg */ 10814 bnx2x_cl45_read(bp, phy, 10815 MDIO_PMA_DEVAD, 10816 MDIO_PMA_REG_8481_LINK_SIGNAL, 10817 &val); 10818 val &= 0x8000; 10819 val |= 0x2492; 10820 10821 bnx2x_cl45_write(bp, phy, 10822 MDIO_PMA_DEVAD, 10823 MDIO_PMA_REG_8481_LINK_SIGNAL, 10824 val); 10825 10826 /* Set LED masks */ 10827 bnx2x_cl45_write(bp, phy, 10828 MDIO_PMA_DEVAD, 10829 MDIO_PMA_REG_8481_LED1_MASK, 10830 0x0); 10831 10832 bnx2x_cl45_write(bp, phy, 10833 MDIO_PMA_DEVAD, 10834 MDIO_PMA_REG_8481_LED2_MASK, 10835 0x20); 10836 10837 bnx2x_cl45_write(bp, phy, 10838 MDIO_PMA_DEVAD, 10839 MDIO_PMA_REG_8481_LED3_MASK, 10840 0x20); 10841 10842 bnx2x_cl45_write(bp, phy, 10843 MDIO_PMA_DEVAD, 10844 MDIO_PMA_REG_8481_LED5_MASK, 10845 0x0); 10846 } else { 10847 bnx2x_cl45_write(bp, phy, 10848 MDIO_PMA_DEVAD, 10849 MDIO_PMA_REG_8481_LED1_MASK, 10850 0x20); 10851 if (phy->type == 10852 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) { 10853 /* Disable MI_INT interrupt before setting LED4 10854 * source to constant on. 10855 */ 10856 if (REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + 10857 params->port*4) & 10858 NIG_MASK_MI_INT) { 10859 params->link_flags |= 10860 LINK_FLAGS_INT_DISABLED; 10861 10862 bnx2x_bits_dis( 10863 bp, 10864 NIG_REG_MASK_INTERRUPT_PORT0 + 10865 params->port*4, 10866 NIG_MASK_MI_INT); 10867 } 10868 } 10869 if (phy->type == 10870 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858) { 10871 /* Tell LED3 to constant on */ 10872 bnx2x_cl45_read(bp, phy, 10873 MDIO_PMA_DEVAD, 10874 MDIO_PMA_REG_8481_LINK_SIGNAL, 10875 &val); 10876 val &= ~(7<<6); 10877 val |= (2<<6); /* A83B[8:6]= 2 */ 10878 bnx2x_cl45_write(bp, phy, 10879 MDIO_PMA_DEVAD, 10880 MDIO_PMA_REG_8481_LINK_SIGNAL, 10881 val); 10882 bnx2x_cl45_write(bp, phy, 10883 MDIO_PMA_DEVAD, 10884 MDIO_PMA_REG_8481_LED3_MASK, 10885 0x20); 10886 } else { 10887 bnx2x_cl45_write(bp, phy, 10888 MDIO_PMA_DEVAD, 10889 MDIO_PMA_REG_8481_SIGNAL_MASK, 10890 0x20); 10891 } 10892 } 10893 break; 10894 10895 case LED_MODE_OPER: 10896 10897 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OPER\n", port); 10898 10899 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) == 10900 SHARED_HW_CFG_LED_EXTPHY1) { 10901 10902 /* Set control reg */ 10903 bnx2x_cl45_read(bp, phy, 10904 MDIO_PMA_DEVAD, 10905 MDIO_PMA_REG_8481_LINK_SIGNAL, 10906 &val); 10907 10908 if (!((val & 10909 MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK) 10910 >> MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT)) { 10911 DP(NETIF_MSG_LINK, "Setting LINK_SIGNAL\n"); 10912 bnx2x_cl45_write(bp, phy, 10913 MDIO_PMA_DEVAD, 10914 MDIO_PMA_REG_8481_LINK_SIGNAL, 10915 0xa492); 10916 } 10917 10918 /* Set LED masks */ 10919 bnx2x_cl45_write(bp, phy, 10920 MDIO_PMA_DEVAD, 10921 MDIO_PMA_REG_8481_LED1_MASK, 10922 0x10); 10923 10924 bnx2x_cl45_write(bp, phy, 10925 MDIO_PMA_DEVAD, 10926 MDIO_PMA_REG_8481_LED2_MASK, 10927 0x80); 10928 10929 bnx2x_cl45_write(bp, phy, 10930 MDIO_PMA_DEVAD, 10931 MDIO_PMA_REG_8481_LED3_MASK, 10932 0x98); 10933 10934 bnx2x_cl45_write(bp, phy, 10935 MDIO_PMA_DEVAD, 10936 MDIO_PMA_REG_8481_LED5_MASK, 10937 0x40); 10938 10939 } else { 10940 /* EXTPHY2 LED mode indicate that the 100M/1G/10G LED 10941 * sources are all wired through LED1, rather than only 10942 * 10G in other modes. 10943 */ 10944 val = ((params->hw_led_mode << 10945 SHARED_HW_CFG_LED_MODE_SHIFT) == 10946 SHARED_HW_CFG_LED_EXTPHY2) ? 0x98 : 0x80; 10947 10948 bnx2x_cl45_write(bp, phy, 10949 MDIO_PMA_DEVAD, 10950 MDIO_PMA_REG_8481_LED1_MASK, 10951 val); 10952 10953 /* Tell LED3 to blink on source */ 10954 bnx2x_cl45_read(bp, phy, 10955 MDIO_PMA_DEVAD, 10956 MDIO_PMA_REG_8481_LINK_SIGNAL, 10957 &val); 10958 val &= ~(7<<6); 10959 val |= (1<<6); /* A83B[8:6]= 1 */ 10960 bnx2x_cl45_write(bp, phy, 10961 MDIO_PMA_DEVAD, 10962 MDIO_PMA_REG_8481_LINK_SIGNAL, 10963 val); 10964 if (phy->type == 10965 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858) { 10966 bnx2x_cl45_write(bp, phy, 10967 MDIO_PMA_DEVAD, 10968 MDIO_PMA_REG_8481_LED2_MASK, 10969 0x18); 10970 bnx2x_cl45_write(bp, phy, 10971 MDIO_PMA_DEVAD, 10972 MDIO_PMA_REG_8481_LED3_MASK, 10973 0x06); 10974 } 10975 if (phy->type == 10976 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) { 10977 /* Restore LED4 source to external link, 10978 * and re-enable interrupts. 10979 */ 10980 bnx2x_cl45_write(bp, phy, 10981 MDIO_PMA_DEVAD, 10982 MDIO_PMA_REG_8481_SIGNAL_MASK, 10983 0x40); 10984 if (params->link_flags & 10985 LINK_FLAGS_INT_DISABLED) { 10986 bnx2x_link_int_enable(params); 10987 params->link_flags &= 10988 ~LINK_FLAGS_INT_DISABLED; 10989 } 10990 } 10991 } 10992 break; 10993 } 10994 10995 /* This is a workaround for E3+84833 until autoneg 10996 * restart is fixed in f/w 10997 */ 10998 if (CHIP_IS_E3(bp)) { 10999 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 11000 MDIO_WC_REG_GP2_STATUS_GP_2_1, &val); 11001 } 11002 } 11003 11004 /******************************************************************/ 11005 /* 54618SE PHY SECTION */ 11006 /******************************************************************/ 11007 static void bnx2x_54618se_specific_func(struct bnx2x_phy *phy, 11008 struct link_params *params, 11009 u32 action) 11010 { 11011 struct bnx2x *bp = params->bp; 11012 u16 temp; 11013 switch (action) { 11014 case PHY_INIT: 11015 /* Configure LED4: set to INTR (0x6). */ 11016 /* Accessing shadow register 0xe. */ 11017 bnx2x_cl22_write(bp, phy, 11018 MDIO_REG_GPHY_SHADOW, 11019 MDIO_REG_GPHY_SHADOW_LED_SEL2); 11020 bnx2x_cl22_read(bp, phy, 11021 MDIO_REG_GPHY_SHADOW, 11022 &temp); 11023 temp &= ~(0xf << 4); 11024 temp |= (0x6 << 4); 11025 bnx2x_cl22_write(bp, phy, 11026 MDIO_REG_GPHY_SHADOW, 11027 MDIO_REG_GPHY_SHADOW_WR_ENA | temp); 11028 /* Configure INTR based on link status change. */ 11029 bnx2x_cl22_write(bp, phy, 11030 MDIO_REG_INTR_MASK, 11031 ~MDIO_REG_INTR_MASK_LINK_STATUS); 11032 break; 11033 } 11034 } 11035 11036 static void bnx2x_54618se_config_init(struct bnx2x_phy *phy, 11037 struct link_params *params, 11038 struct link_vars *vars) 11039 { 11040 struct bnx2x *bp = params->bp; 11041 u8 port; 11042 u16 autoneg_val, an_1000_val, an_10_100_val, fc_val, temp; 11043 u32 cfg_pin; 11044 11045 DP(NETIF_MSG_LINK, "54618SE cfg init\n"); 11046 usleep_range(1000, 2000); 11047 11048 /* This works with E3 only, no need to check the chip 11049 * before determining the port. 11050 */ 11051 port = params->port; 11052 11053 cfg_pin = (REG_RD(bp, params->shmem_base + 11054 offsetof(struct shmem_region, 11055 dev_info.port_hw_config[port].e3_cmn_pin_cfg)) & 11056 PORT_HW_CFG_E3_PHY_RESET_MASK) >> 11057 PORT_HW_CFG_E3_PHY_RESET_SHIFT; 11058 11059 /* Drive pin high to bring the GPHY out of reset. */ 11060 bnx2x_set_cfg_pin(bp, cfg_pin, 1); 11061 11062 /* wait for GPHY to reset */ 11063 msleep(50); 11064 11065 /* reset phy */ 11066 bnx2x_cl22_write(bp, phy, 11067 MDIO_PMA_REG_CTRL, 0x8000); 11068 bnx2x_wait_reset_complete(bp, phy, params); 11069 11070 /* Wait for GPHY to reset */ 11071 msleep(50); 11072 11073 11074 bnx2x_54618se_specific_func(phy, params, PHY_INIT); 11075 /* Flip the signal detect polarity (set 0x1c.0x1e[8]). */ 11076 bnx2x_cl22_write(bp, phy, 11077 MDIO_REG_GPHY_SHADOW, 11078 MDIO_REG_GPHY_SHADOW_AUTO_DET_MED); 11079 bnx2x_cl22_read(bp, phy, 11080 MDIO_REG_GPHY_SHADOW, 11081 &temp); 11082 temp |= MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD; 11083 bnx2x_cl22_write(bp, phy, 11084 MDIO_REG_GPHY_SHADOW, 11085 MDIO_REG_GPHY_SHADOW_WR_ENA | temp); 11086 11087 /* Set up fc */ 11088 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */ 11089 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); 11090 fc_val = 0; 11091 if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) == 11092 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) 11093 fc_val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC; 11094 11095 if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) == 11096 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) 11097 fc_val |= MDIO_AN_REG_ADV_PAUSE_PAUSE; 11098 11099 /* Read all advertisement */ 11100 bnx2x_cl22_read(bp, phy, 11101 0x09, 11102 &an_1000_val); 11103 11104 bnx2x_cl22_read(bp, phy, 11105 0x04, 11106 &an_10_100_val); 11107 11108 bnx2x_cl22_read(bp, phy, 11109 MDIO_PMA_REG_CTRL, 11110 &autoneg_val); 11111 11112 /* Disable forced speed */ 11113 autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13)); 11114 an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8) | (1<<10) | 11115 (1<<11)); 11116 11117 if (((phy->req_line_speed == SPEED_AUTO_NEG) && 11118 (phy->speed_cap_mask & 11119 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) || 11120 (phy->req_line_speed == SPEED_1000)) { 11121 an_1000_val |= (1<<8); 11122 autoneg_val |= (1<<9 | 1<<12); 11123 if (phy->req_duplex == DUPLEX_FULL) 11124 an_1000_val |= (1<<9); 11125 DP(NETIF_MSG_LINK, "Advertising 1G\n"); 11126 } else 11127 an_1000_val &= ~((1<<8) | (1<<9)); 11128 11129 bnx2x_cl22_write(bp, phy, 11130 0x09, 11131 an_1000_val); 11132 bnx2x_cl22_read(bp, phy, 11133 0x09, 11134 &an_1000_val); 11135 11136 /* Advertise 10/100 link speed */ 11137 if (phy->req_line_speed == SPEED_AUTO_NEG) { 11138 if (phy->speed_cap_mask & 11139 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF) { 11140 an_10_100_val |= (1<<5); 11141 autoneg_val |= (1<<9 | 1<<12); 11142 DP(NETIF_MSG_LINK, "Advertising 10M-HD\n"); 11143 } 11144 if (phy->speed_cap_mask & 11145 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) { 11146 an_10_100_val |= (1<<6); 11147 autoneg_val |= (1<<9 | 1<<12); 11148 DP(NETIF_MSG_LINK, "Advertising 10M-FD\n"); 11149 } 11150 if (phy->speed_cap_mask & 11151 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF) { 11152 an_10_100_val |= (1<<7); 11153 autoneg_val |= (1<<9 | 1<<12); 11154 DP(NETIF_MSG_LINK, "Advertising 100M-HD\n"); 11155 } 11156 if (phy->speed_cap_mask & 11157 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL) { 11158 an_10_100_val |= (1<<8); 11159 autoneg_val |= (1<<9 | 1<<12); 11160 DP(NETIF_MSG_LINK, "Advertising 100M-FD\n"); 11161 } 11162 } 11163 11164 /* Only 10/100 are allowed to work in FORCE mode */ 11165 if (phy->req_line_speed == SPEED_100) { 11166 autoneg_val |= (1<<13); 11167 /* Enabled AUTO-MDIX when autoneg is disabled */ 11168 bnx2x_cl22_write(bp, phy, 11169 0x18, 11170 (1<<15 | 1<<9 | 7<<0)); 11171 DP(NETIF_MSG_LINK, "Setting 100M force\n"); 11172 } 11173 if (phy->req_line_speed == SPEED_10) { 11174 /* Enabled AUTO-MDIX when autoneg is disabled */ 11175 bnx2x_cl22_write(bp, phy, 11176 0x18, 11177 (1<<15 | 1<<9 | 7<<0)); 11178 DP(NETIF_MSG_LINK, "Setting 10M force\n"); 11179 } 11180 11181 if ((phy->flags & FLAGS_EEE) && bnx2x_eee_has_cap(params)) { 11182 int rc; 11183 11184 bnx2x_cl22_write(bp, phy, MDIO_REG_GPHY_EXP_ACCESS, 11185 MDIO_REG_GPHY_EXP_ACCESS_TOP | 11186 MDIO_REG_GPHY_EXP_TOP_2K_BUF); 11187 bnx2x_cl22_read(bp, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, &temp); 11188 temp &= 0xfffe; 11189 bnx2x_cl22_write(bp, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, temp); 11190 11191 rc = bnx2x_eee_initial_config(params, vars, SHMEM_EEE_1G_ADV); 11192 if (rc) { 11193 DP(NETIF_MSG_LINK, "Failed to configure EEE timers\n"); 11194 bnx2x_eee_disable(phy, params, vars); 11195 } else if ((params->eee_mode & EEE_MODE_ADV_LPI) && 11196 (phy->req_duplex == DUPLEX_FULL) && 11197 (bnx2x_eee_calc_timer(params) || 11198 !(params->eee_mode & EEE_MODE_ENABLE_LPI))) { 11199 /* Need to advertise EEE only when requested, 11200 * and either no LPI assertion was requested, 11201 * or it was requested and a valid timer was set. 11202 * Also notice full duplex is required for EEE. 11203 */ 11204 bnx2x_eee_advertise(phy, params, vars, 11205 SHMEM_EEE_1G_ADV); 11206 } else { 11207 DP(NETIF_MSG_LINK, "Don't Advertise 1GBase-T EEE\n"); 11208 bnx2x_eee_disable(phy, params, vars); 11209 } 11210 } else { 11211 vars->eee_status &= ~SHMEM_EEE_1G_ADV << 11212 SHMEM_EEE_SUPPORTED_SHIFT; 11213 11214 if (phy->flags & FLAGS_EEE) { 11215 /* Handle legacy auto-grEEEn */ 11216 if (params->feature_config_flags & 11217 FEATURE_CONFIG_AUTOGREEEN_ENABLED) { 11218 temp = 6; 11219 DP(NETIF_MSG_LINK, "Enabling Auto-GrEEEn\n"); 11220 } else { 11221 temp = 0; 11222 DP(NETIF_MSG_LINK, "Don't Adv. EEE\n"); 11223 } 11224 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, 11225 MDIO_AN_REG_EEE_ADV, temp); 11226 } 11227 } 11228 11229 bnx2x_cl22_write(bp, phy, 11230 0x04, 11231 an_10_100_val | fc_val); 11232 11233 if (phy->req_duplex == DUPLEX_FULL) 11234 autoneg_val |= (1<<8); 11235 11236 bnx2x_cl22_write(bp, phy, 11237 MDIO_PMA_REG_CTRL, autoneg_val); 11238 } 11239 11240 11241 static void bnx2x_5461x_set_link_led(struct bnx2x_phy *phy, 11242 struct link_params *params, u8 mode) 11243 { 11244 struct bnx2x *bp = params->bp; 11245 u16 temp; 11246 11247 bnx2x_cl22_write(bp, phy, 11248 MDIO_REG_GPHY_SHADOW, 11249 MDIO_REG_GPHY_SHADOW_LED_SEL1); 11250 bnx2x_cl22_read(bp, phy, 11251 MDIO_REG_GPHY_SHADOW, 11252 &temp); 11253 temp &= 0xff00; 11254 11255 DP(NETIF_MSG_LINK, "54618x set link led (mode=%x)\n", mode); 11256 switch (mode) { 11257 case LED_MODE_FRONT_PANEL_OFF: 11258 case LED_MODE_OFF: 11259 temp |= 0x00ee; 11260 break; 11261 case LED_MODE_OPER: 11262 temp |= 0x0001; 11263 break; 11264 case LED_MODE_ON: 11265 temp |= 0x00ff; 11266 break; 11267 default: 11268 break; 11269 } 11270 bnx2x_cl22_write(bp, phy, 11271 MDIO_REG_GPHY_SHADOW, 11272 MDIO_REG_GPHY_SHADOW_WR_ENA | temp); 11273 return; 11274 } 11275 11276 11277 static void bnx2x_54618se_link_reset(struct bnx2x_phy *phy, 11278 struct link_params *params) 11279 { 11280 struct bnx2x *bp = params->bp; 11281 u32 cfg_pin; 11282 u8 port; 11283 11284 /* In case of no EPIO routed to reset the GPHY, put it 11285 * in low power mode. 11286 */ 11287 bnx2x_cl22_write(bp, phy, MDIO_PMA_REG_CTRL, 0x800); 11288 /* This works with E3 only, no need to check the chip 11289 * before determining the port. 11290 */ 11291 port = params->port; 11292 cfg_pin = (REG_RD(bp, params->shmem_base + 11293 offsetof(struct shmem_region, 11294 dev_info.port_hw_config[port].e3_cmn_pin_cfg)) & 11295 PORT_HW_CFG_E3_PHY_RESET_MASK) >> 11296 PORT_HW_CFG_E3_PHY_RESET_SHIFT; 11297 11298 /* Drive pin low to put GPHY in reset. */ 11299 bnx2x_set_cfg_pin(bp, cfg_pin, 0); 11300 } 11301 11302 static u8 bnx2x_54618se_read_status(struct bnx2x_phy *phy, 11303 struct link_params *params, 11304 struct link_vars *vars) 11305 { 11306 struct bnx2x *bp = params->bp; 11307 u16 val; 11308 u8 link_up = 0; 11309 u16 legacy_status, legacy_speed; 11310 11311 /* Get speed operation status */ 11312 bnx2x_cl22_read(bp, phy, 11313 MDIO_REG_GPHY_AUX_STATUS, 11314 &legacy_status); 11315 DP(NETIF_MSG_LINK, "54618SE read_status: 0x%x\n", legacy_status); 11316 11317 /* Read status to clear the PHY interrupt. */ 11318 bnx2x_cl22_read(bp, phy, 11319 MDIO_REG_INTR_STATUS, 11320 &val); 11321 11322 link_up = ((legacy_status & (1<<2)) == (1<<2)); 11323 11324 if (link_up) { 11325 legacy_speed = (legacy_status & (7<<8)); 11326 if (legacy_speed == (7<<8)) { 11327 vars->line_speed = SPEED_1000; 11328 vars->duplex = DUPLEX_FULL; 11329 } else if (legacy_speed == (6<<8)) { 11330 vars->line_speed = SPEED_1000; 11331 vars->duplex = DUPLEX_HALF; 11332 } else if (legacy_speed == (5<<8)) { 11333 vars->line_speed = SPEED_100; 11334 vars->duplex = DUPLEX_FULL; 11335 } 11336 /* Omitting 100Base-T4 for now */ 11337 else if (legacy_speed == (3<<8)) { 11338 vars->line_speed = SPEED_100; 11339 vars->duplex = DUPLEX_HALF; 11340 } else if (legacy_speed == (2<<8)) { 11341 vars->line_speed = SPEED_10; 11342 vars->duplex = DUPLEX_FULL; 11343 } else if (legacy_speed == (1<<8)) { 11344 vars->line_speed = SPEED_10; 11345 vars->duplex = DUPLEX_HALF; 11346 } else /* Should not happen */ 11347 vars->line_speed = 0; 11348 11349 DP(NETIF_MSG_LINK, 11350 "Link is up in %dMbps, is_duplex_full= %d\n", 11351 vars->line_speed, 11352 (vars->duplex == DUPLEX_FULL)); 11353 11354 /* Check legacy speed AN resolution */ 11355 bnx2x_cl22_read(bp, phy, 11356 0x01, 11357 &val); 11358 if (val & (1<<5)) 11359 vars->link_status |= 11360 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; 11361 bnx2x_cl22_read(bp, phy, 11362 0x06, 11363 &val); 11364 if ((val & (1<<0)) == 0) 11365 vars->link_status |= 11366 LINK_STATUS_PARALLEL_DETECTION_USED; 11367 11368 DP(NETIF_MSG_LINK, "BCM54618SE: link speed is %d\n", 11369 vars->line_speed); 11370 11371 bnx2x_ext_phy_resolve_fc(phy, params, vars); 11372 11373 if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) { 11374 /* Report LP advertised speeds */ 11375 bnx2x_cl22_read(bp, phy, 0x5, &val); 11376 11377 if (val & (1<<5)) 11378 vars->link_status |= 11379 LINK_STATUS_LINK_PARTNER_10THD_CAPABLE; 11380 if (val & (1<<6)) 11381 vars->link_status |= 11382 LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE; 11383 if (val & (1<<7)) 11384 vars->link_status |= 11385 LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE; 11386 if (val & (1<<8)) 11387 vars->link_status |= 11388 LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE; 11389 if (val & (1<<9)) 11390 vars->link_status |= 11391 LINK_STATUS_LINK_PARTNER_100T4_CAPABLE; 11392 11393 bnx2x_cl22_read(bp, phy, 0xa, &val); 11394 if (val & (1<<10)) 11395 vars->link_status |= 11396 LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE; 11397 if (val & (1<<11)) 11398 vars->link_status |= 11399 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; 11400 11401 if ((phy->flags & FLAGS_EEE) && 11402 bnx2x_eee_has_cap(params)) 11403 bnx2x_eee_an_resolve(phy, params, vars); 11404 } 11405 } 11406 return link_up; 11407 } 11408 11409 static void bnx2x_54618se_config_loopback(struct bnx2x_phy *phy, 11410 struct link_params *params) 11411 { 11412 struct bnx2x *bp = params->bp; 11413 u16 val; 11414 u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0; 11415 11416 DP(NETIF_MSG_LINK, "2PMA/PMD ext_phy_loopback: 54618se\n"); 11417 11418 /* Enable master/slave manual mmode and set to master */ 11419 /* mii write 9 [bits set 11 12] */ 11420 bnx2x_cl22_write(bp, phy, 0x09, 3<<11); 11421 11422 /* forced 1G and disable autoneg */ 11423 /* set val [mii read 0] */ 11424 /* set val [expr $val & [bits clear 6 12 13]] */ 11425 /* set val [expr $val | [bits set 6 8]] */ 11426 /* mii write 0 $val */ 11427 bnx2x_cl22_read(bp, phy, 0x00, &val); 11428 val &= ~((1<<6) | (1<<12) | (1<<13)); 11429 val |= (1<<6) | (1<<8); 11430 bnx2x_cl22_write(bp, phy, 0x00, val); 11431 11432 /* Set external loopback and Tx using 6dB coding */ 11433 /* mii write 0x18 7 */ 11434 /* set val [mii read 0x18] */ 11435 /* mii write 0x18 [expr $val | [bits set 10 15]] */ 11436 bnx2x_cl22_write(bp, phy, 0x18, 7); 11437 bnx2x_cl22_read(bp, phy, 0x18, &val); 11438 bnx2x_cl22_write(bp, phy, 0x18, val | (1<<10) | (1<<15)); 11439 11440 /* This register opens the gate for the UMAC despite its name */ 11441 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1); 11442 11443 /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame 11444 * length used by the MAC receive logic to check frames. 11445 */ 11446 REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710); 11447 } 11448 11449 /******************************************************************/ 11450 /* SFX7101 PHY SECTION */ 11451 /******************************************************************/ 11452 static void bnx2x_7101_config_loopback(struct bnx2x_phy *phy, 11453 struct link_params *params) 11454 { 11455 struct bnx2x *bp = params->bp; 11456 /* SFX7101_XGXS_TEST1 */ 11457 bnx2x_cl45_write(bp, phy, 11458 MDIO_XS_DEVAD, MDIO_XS_SFX7101_XGXS_TEST1, 0x100); 11459 } 11460 11461 static void bnx2x_7101_config_init(struct bnx2x_phy *phy, 11462 struct link_params *params, 11463 struct link_vars *vars) 11464 { 11465 u16 fw_ver1, fw_ver2, val; 11466 struct bnx2x *bp = params->bp; 11467 DP(NETIF_MSG_LINK, "Setting the SFX7101 LASI indication\n"); 11468 11469 /* Restore normal power mode*/ 11470 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 11471 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); 11472 /* HW reset */ 11473 bnx2x_ext_phy_hw_reset(bp, params->port); 11474 bnx2x_wait_reset_complete(bp, phy, params); 11475 11476 bnx2x_cl45_write(bp, phy, 11477 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x1); 11478 DP(NETIF_MSG_LINK, "Setting the SFX7101 LED to blink on traffic\n"); 11479 bnx2x_cl45_write(bp, phy, 11480 MDIO_PMA_DEVAD, MDIO_PMA_REG_7107_LED_CNTL, (1<<3)); 11481 11482 bnx2x_ext_phy_set_pause(params, phy, vars); 11483 /* Restart autoneg */ 11484 bnx2x_cl45_read(bp, phy, 11485 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, &val); 11486 val |= 0x200; 11487 bnx2x_cl45_write(bp, phy, 11488 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, val); 11489 11490 /* Save spirom version */ 11491 bnx2x_cl45_read(bp, phy, 11492 MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER1, &fw_ver1); 11493 11494 bnx2x_cl45_read(bp, phy, 11495 MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER2, &fw_ver2); 11496 bnx2x_save_spirom_version(bp, params->port, 11497 (u32)(fw_ver1<<16 | fw_ver2), phy->ver_addr); 11498 } 11499 11500 static u8 bnx2x_7101_read_status(struct bnx2x_phy *phy, 11501 struct link_params *params, 11502 struct link_vars *vars) 11503 { 11504 struct bnx2x *bp = params->bp; 11505 u8 link_up; 11506 u16 val1, val2; 11507 bnx2x_cl45_read(bp, phy, 11508 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2); 11509 bnx2x_cl45_read(bp, phy, 11510 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1); 11511 DP(NETIF_MSG_LINK, "10G-base-T LASI status 0x%x->0x%x\n", 11512 val2, val1); 11513 bnx2x_cl45_read(bp, phy, 11514 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2); 11515 bnx2x_cl45_read(bp, phy, 11516 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1); 11517 DP(NETIF_MSG_LINK, "10G-base-T PMA status 0x%x->0x%x\n", 11518 val2, val1); 11519 link_up = ((val1 & 4) == 4); 11520 /* If link is up print the AN outcome of the SFX7101 PHY */ 11521 if (link_up) { 11522 bnx2x_cl45_read(bp, phy, 11523 MDIO_AN_DEVAD, MDIO_AN_REG_MASTER_STATUS, 11524 &val2); 11525 vars->line_speed = SPEED_10000; 11526 vars->duplex = DUPLEX_FULL; 11527 DP(NETIF_MSG_LINK, "SFX7101 AN status 0x%x->Master=%x\n", 11528 val2, (val2 & (1<<14))); 11529 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars); 11530 bnx2x_ext_phy_resolve_fc(phy, params, vars); 11531 11532 /* Read LP advertised speeds */ 11533 if (val2 & (1<<11)) 11534 vars->link_status |= 11535 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; 11536 } 11537 return link_up; 11538 } 11539 11540 static int bnx2x_7101_format_ver(u32 spirom_ver, u8 *str, u16 *len) 11541 { 11542 if (*len < 5) 11543 return -EINVAL; 11544 str[0] = (spirom_ver & 0xFF); 11545 str[1] = (spirom_ver & 0xFF00) >> 8; 11546 str[2] = (spirom_ver & 0xFF0000) >> 16; 11547 str[3] = (spirom_ver & 0xFF000000) >> 24; 11548 str[4] = '\0'; 11549 *len -= 5; 11550 return 0; 11551 } 11552 11553 void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, struct bnx2x_phy *phy) 11554 { 11555 u16 val, cnt; 11556 11557 bnx2x_cl45_read(bp, phy, 11558 MDIO_PMA_DEVAD, 11559 MDIO_PMA_REG_7101_RESET, &val); 11560 11561 for (cnt = 0; cnt < 10; cnt++) { 11562 msleep(50); 11563 /* Writes a self-clearing reset */ 11564 bnx2x_cl45_write(bp, phy, 11565 MDIO_PMA_DEVAD, 11566 MDIO_PMA_REG_7101_RESET, 11567 (val | (1<<15))); 11568 /* Wait for clear */ 11569 bnx2x_cl45_read(bp, phy, 11570 MDIO_PMA_DEVAD, 11571 MDIO_PMA_REG_7101_RESET, &val); 11572 11573 if ((val & (1<<15)) == 0) 11574 break; 11575 } 11576 } 11577 11578 static void bnx2x_7101_hw_reset(struct bnx2x_phy *phy, 11579 struct link_params *params) { 11580 /* Low power mode is controlled by GPIO 2 */ 11581 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_2, 11582 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port); 11583 /* The PHY reset is controlled by GPIO 1 */ 11584 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1, 11585 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port); 11586 } 11587 11588 static void bnx2x_7101_set_link_led(struct bnx2x_phy *phy, 11589 struct link_params *params, u8 mode) 11590 { 11591 u16 val = 0; 11592 struct bnx2x *bp = params->bp; 11593 switch (mode) { 11594 case LED_MODE_FRONT_PANEL_OFF: 11595 case LED_MODE_OFF: 11596 val = 2; 11597 break; 11598 case LED_MODE_ON: 11599 val = 1; 11600 break; 11601 case LED_MODE_OPER: 11602 val = 0; 11603 break; 11604 } 11605 bnx2x_cl45_write(bp, phy, 11606 MDIO_PMA_DEVAD, 11607 MDIO_PMA_REG_7107_LINK_LED_CNTL, 11608 val); 11609 } 11610 11611 /******************************************************************/ 11612 /* STATIC PHY DECLARATION */ 11613 /******************************************************************/ 11614 11615 static const struct bnx2x_phy phy_null = { 11616 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN, 11617 .addr = 0, 11618 .def_md_devad = 0, 11619 .flags = FLAGS_INIT_XGXS_FIRST, 11620 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11621 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11622 .mdio_ctrl = 0, 11623 .supported = 0, 11624 .media_type = ETH_PHY_NOT_PRESENT, 11625 .ver_addr = 0, 11626 .req_flow_ctrl = 0, 11627 .req_line_speed = 0, 11628 .speed_cap_mask = 0, 11629 .req_duplex = 0, 11630 .rsrv = 0, 11631 .config_init = NULL, 11632 .read_status = NULL, 11633 .link_reset = NULL, 11634 .config_loopback = NULL, 11635 .format_fw_ver = NULL, 11636 .hw_reset = NULL, 11637 .set_link_led = NULL, 11638 .phy_specific_func = NULL 11639 }; 11640 11641 static const struct bnx2x_phy phy_serdes = { 11642 .type = PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT, 11643 .addr = 0xff, 11644 .def_md_devad = 0, 11645 .flags = 0, 11646 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11647 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11648 .mdio_ctrl = 0, 11649 .supported = (SUPPORTED_10baseT_Half | 11650 SUPPORTED_10baseT_Full | 11651 SUPPORTED_100baseT_Half | 11652 SUPPORTED_100baseT_Full | 11653 SUPPORTED_1000baseT_Full | 11654 SUPPORTED_2500baseX_Full | 11655 SUPPORTED_TP | 11656 SUPPORTED_Autoneg | 11657 SUPPORTED_Pause | 11658 SUPPORTED_Asym_Pause), 11659 .media_type = ETH_PHY_BASE_T, 11660 .ver_addr = 0, 11661 .req_flow_ctrl = 0, 11662 .req_line_speed = 0, 11663 .speed_cap_mask = 0, 11664 .req_duplex = 0, 11665 .rsrv = 0, 11666 .config_init = bnx2x_xgxs_config_init, 11667 .read_status = bnx2x_link_settings_status, 11668 .link_reset = bnx2x_int_link_reset, 11669 .config_loopback = NULL, 11670 .format_fw_ver = NULL, 11671 .hw_reset = NULL, 11672 .set_link_led = NULL, 11673 .phy_specific_func = NULL 11674 }; 11675 11676 static const struct bnx2x_phy phy_xgxs = { 11677 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT, 11678 .addr = 0xff, 11679 .def_md_devad = 0, 11680 .flags = 0, 11681 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11682 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11683 .mdio_ctrl = 0, 11684 .supported = (SUPPORTED_10baseT_Half | 11685 SUPPORTED_10baseT_Full | 11686 SUPPORTED_100baseT_Half | 11687 SUPPORTED_100baseT_Full | 11688 SUPPORTED_1000baseT_Full | 11689 SUPPORTED_2500baseX_Full | 11690 SUPPORTED_10000baseT_Full | 11691 SUPPORTED_FIBRE | 11692 SUPPORTED_Autoneg | 11693 SUPPORTED_Pause | 11694 SUPPORTED_Asym_Pause), 11695 .media_type = ETH_PHY_CX4, 11696 .ver_addr = 0, 11697 .req_flow_ctrl = 0, 11698 .req_line_speed = 0, 11699 .speed_cap_mask = 0, 11700 .req_duplex = 0, 11701 .rsrv = 0, 11702 .config_init = bnx2x_xgxs_config_init, 11703 .read_status = bnx2x_link_settings_status, 11704 .link_reset = bnx2x_int_link_reset, 11705 .config_loopback = bnx2x_set_xgxs_loopback, 11706 .format_fw_ver = NULL, 11707 .hw_reset = NULL, 11708 .set_link_led = NULL, 11709 .phy_specific_func = bnx2x_xgxs_specific_func 11710 }; 11711 static const struct bnx2x_phy phy_warpcore = { 11712 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT, 11713 .addr = 0xff, 11714 .def_md_devad = 0, 11715 .flags = FLAGS_TX_ERROR_CHECK, 11716 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11717 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11718 .mdio_ctrl = 0, 11719 .supported = (SUPPORTED_10baseT_Half | 11720 SUPPORTED_10baseT_Full | 11721 SUPPORTED_100baseT_Half | 11722 SUPPORTED_100baseT_Full | 11723 SUPPORTED_1000baseT_Full | 11724 SUPPORTED_1000baseKX_Full | 11725 SUPPORTED_10000baseT_Full | 11726 SUPPORTED_10000baseKR_Full | 11727 SUPPORTED_20000baseKR2_Full | 11728 SUPPORTED_20000baseMLD2_Full | 11729 SUPPORTED_FIBRE | 11730 SUPPORTED_Autoneg | 11731 SUPPORTED_Pause | 11732 SUPPORTED_Asym_Pause), 11733 .media_type = ETH_PHY_UNSPECIFIED, 11734 .ver_addr = 0, 11735 .req_flow_ctrl = 0, 11736 .req_line_speed = 0, 11737 .speed_cap_mask = 0, 11738 /* req_duplex = */0, 11739 /* rsrv = */0, 11740 .config_init = bnx2x_warpcore_config_init, 11741 .read_status = bnx2x_warpcore_read_status, 11742 .link_reset = bnx2x_warpcore_link_reset, 11743 .config_loopback = bnx2x_set_warpcore_loopback, 11744 .format_fw_ver = NULL, 11745 .hw_reset = bnx2x_warpcore_hw_reset, 11746 .set_link_led = NULL, 11747 .phy_specific_func = NULL 11748 }; 11749 11750 11751 static const struct bnx2x_phy phy_7101 = { 11752 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101, 11753 .addr = 0xff, 11754 .def_md_devad = 0, 11755 .flags = FLAGS_FAN_FAILURE_DET_REQ, 11756 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11757 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11758 .mdio_ctrl = 0, 11759 .supported = (SUPPORTED_10000baseT_Full | 11760 SUPPORTED_TP | 11761 SUPPORTED_Autoneg | 11762 SUPPORTED_Pause | 11763 SUPPORTED_Asym_Pause), 11764 .media_type = ETH_PHY_BASE_T, 11765 .ver_addr = 0, 11766 .req_flow_ctrl = 0, 11767 .req_line_speed = 0, 11768 .speed_cap_mask = 0, 11769 .req_duplex = 0, 11770 .rsrv = 0, 11771 .config_init = bnx2x_7101_config_init, 11772 .read_status = bnx2x_7101_read_status, 11773 .link_reset = bnx2x_common_ext_link_reset, 11774 .config_loopback = bnx2x_7101_config_loopback, 11775 .format_fw_ver = bnx2x_7101_format_ver, 11776 .hw_reset = bnx2x_7101_hw_reset, 11777 .set_link_led = bnx2x_7101_set_link_led, 11778 .phy_specific_func = NULL 11779 }; 11780 static const struct bnx2x_phy phy_8073 = { 11781 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073, 11782 .addr = 0xff, 11783 .def_md_devad = 0, 11784 .flags = 0, 11785 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11786 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11787 .mdio_ctrl = 0, 11788 .supported = (SUPPORTED_10000baseT_Full | 11789 SUPPORTED_2500baseX_Full | 11790 SUPPORTED_1000baseT_Full | 11791 SUPPORTED_FIBRE | 11792 SUPPORTED_Autoneg | 11793 SUPPORTED_Pause | 11794 SUPPORTED_Asym_Pause), 11795 .media_type = ETH_PHY_KR, 11796 .ver_addr = 0, 11797 .req_flow_ctrl = 0, 11798 .req_line_speed = 0, 11799 .speed_cap_mask = 0, 11800 .req_duplex = 0, 11801 .rsrv = 0, 11802 .config_init = bnx2x_8073_config_init, 11803 .read_status = bnx2x_8073_read_status, 11804 .link_reset = bnx2x_8073_link_reset, 11805 .config_loopback = NULL, 11806 .format_fw_ver = bnx2x_format_ver, 11807 .hw_reset = NULL, 11808 .set_link_led = NULL, 11809 .phy_specific_func = bnx2x_8073_specific_func 11810 }; 11811 static const struct bnx2x_phy phy_8705 = { 11812 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705, 11813 .addr = 0xff, 11814 .def_md_devad = 0, 11815 .flags = FLAGS_INIT_XGXS_FIRST, 11816 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11817 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11818 .mdio_ctrl = 0, 11819 .supported = (SUPPORTED_10000baseT_Full | 11820 SUPPORTED_FIBRE | 11821 SUPPORTED_Pause | 11822 SUPPORTED_Asym_Pause), 11823 .media_type = ETH_PHY_XFP_FIBER, 11824 .ver_addr = 0, 11825 .req_flow_ctrl = 0, 11826 .req_line_speed = 0, 11827 .speed_cap_mask = 0, 11828 .req_duplex = 0, 11829 .rsrv = 0, 11830 .config_init = bnx2x_8705_config_init, 11831 .read_status = bnx2x_8705_read_status, 11832 .link_reset = bnx2x_common_ext_link_reset, 11833 .config_loopback = NULL, 11834 .format_fw_ver = bnx2x_null_format_ver, 11835 .hw_reset = NULL, 11836 .set_link_led = NULL, 11837 .phy_specific_func = NULL 11838 }; 11839 static const struct bnx2x_phy phy_8706 = { 11840 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706, 11841 .addr = 0xff, 11842 .def_md_devad = 0, 11843 .flags = FLAGS_INIT_XGXS_FIRST, 11844 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11845 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11846 .mdio_ctrl = 0, 11847 .supported = (SUPPORTED_10000baseT_Full | 11848 SUPPORTED_1000baseT_Full | 11849 SUPPORTED_FIBRE | 11850 SUPPORTED_Pause | 11851 SUPPORTED_Asym_Pause), 11852 .media_type = ETH_PHY_SFPP_10G_FIBER, 11853 .ver_addr = 0, 11854 .req_flow_ctrl = 0, 11855 .req_line_speed = 0, 11856 .speed_cap_mask = 0, 11857 .req_duplex = 0, 11858 .rsrv = 0, 11859 .config_init = bnx2x_8706_config_init, 11860 .read_status = bnx2x_8706_read_status, 11861 .link_reset = bnx2x_common_ext_link_reset, 11862 .config_loopback = NULL, 11863 .format_fw_ver = bnx2x_format_ver, 11864 .hw_reset = NULL, 11865 .set_link_led = NULL, 11866 .phy_specific_func = NULL 11867 }; 11868 11869 static const struct bnx2x_phy phy_8726 = { 11870 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726, 11871 .addr = 0xff, 11872 .def_md_devad = 0, 11873 .flags = (FLAGS_INIT_XGXS_FIRST | 11874 FLAGS_TX_ERROR_CHECK), 11875 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11876 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11877 .mdio_ctrl = 0, 11878 .supported = (SUPPORTED_10000baseT_Full | 11879 SUPPORTED_1000baseT_Full | 11880 SUPPORTED_Autoneg | 11881 SUPPORTED_FIBRE | 11882 SUPPORTED_Pause | 11883 SUPPORTED_Asym_Pause), 11884 .media_type = ETH_PHY_NOT_PRESENT, 11885 .ver_addr = 0, 11886 .req_flow_ctrl = 0, 11887 .req_line_speed = 0, 11888 .speed_cap_mask = 0, 11889 .req_duplex = 0, 11890 .rsrv = 0, 11891 .config_init = bnx2x_8726_config_init, 11892 .read_status = bnx2x_8726_read_status, 11893 .link_reset = bnx2x_8726_link_reset, 11894 .config_loopback = bnx2x_8726_config_loopback, 11895 .format_fw_ver = bnx2x_format_ver, 11896 .hw_reset = NULL, 11897 .set_link_led = NULL, 11898 .phy_specific_func = NULL 11899 }; 11900 11901 static const struct bnx2x_phy phy_8727 = { 11902 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727, 11903 .addr = 0xff, 11904 .def_md_devad = 0, 11905 .flags = (FLAGS_FAN_FAILURE_DET_REQ | 11906 FLAGS_TX_ERROR_CHECK), 11907 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11908 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11909 .mdio_ctrl = 0, 11910 .supported = (SUPPORTED_10000baseT_Full | 11911 SUPPORTED_1000baseT_Full | 11912 SUPPORTED_FIBRE | 11913 SUPPORTED_Pause | 11914 SUPPORTED_Asym_Pause), 11915 .media_type = ETH_PHY_NOT_PRESENT, 11916 .ver_addr = 0, 11917 .req_flow_ctrl = 0, 11918 .req_line_speed = 0, 11919 .speed_cap_mask = 0, 11920 .req_duplex = 0, 11921 .rsrv = 0, 11922 .config_init = bnx2x_8727_config_init, 11923 .read_status = bnx2x_8727_read_status, 11924 .link_reset = bnx2x_8727_link_reset, 11925 .config_loopback = NULL, 11926 .format_fw_ver = bnx2x_format_ver, 11927 .hw_reset = bnx2x_8727_hw_reset, 11928 .set_link_led = bnx2x_8727_set_link_led, 11929 .phy_specific_func = bnx2x_8727_specific_func 11930 }; 11931 static const struct bnx2x_phy phy_8481 = { 11932 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481, 11933 .addr = 0xff, 11934 .def_md_devad = 0, 11935 .flags = FLAGS_FAN_FAILURE_DET_REQ | 11936 FLAGS_REARM_LATCH_SIGNAL, 11937 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11938 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11939 .mdio_ctrl = 0, 11940 .supported = (SUPPORTED_10baseT_Half | 11941 SUPPORTED_10baseT_Full | 11942 SUPPORTED_100baseT_Half | 11943 SUPPORTED_100baseT_Full | 11944 SUPPORTED_1000baseT_Full | 11945 SUPPORTED_10000baseT_Full | 11946 SUPPORTED_TP | 11947 SUPPORTED_Autoneg | 11948 SUPPORTED_Pause | 11949 SUPPORTED_Asym_Pause), 11950 .media_type = ETH_PHY_BASE_T, 11951 .ver_addr = 0, 11952 .req_flow_ctrl = 0, 11953 .req_line_speed = 0, 11954 .speed_cap_mask = 0, 11955 .req_duplex = 0, 11956 .rsrv = 0, 11957 .config_init = bnx2x_8481_config_init, 11958 .read_status = bnx2x_848xx_read_status, 11959 .link_reset = bnx2x_8481_link_reset, 11960 .config_loopback = NULL, 11961 .format_fw_ver = bnx2x_848xx_format_ver, 11962 .hw_reset = bnx2x_8481_hw_reset, 11963 .set_link_led = bnx2x_848xx_set_link_led, 11964 .phy_specific_func = NULL 11965 }; 11966 11967 static const struct bnx2x_phy phy_84823 = { 11968 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823, 11969 .addr = 0xff, 11970 .def_md_devad = 0, 11971 .flags = (FLAGS_FAN_FAILURE_DET_REQ | 11972 FLAGS_REARM_LATCH_SIGNAL | 11973 FLAGS_TX_ERROR_CHECK), 11974 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11975 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11976 .mdio_ctrl = 0, 11977 .supported = (SUPPORTED_10baseT_Half | 11978 SUPPORTED_10baseT_Full | 11979 SUPPORTED_100baseT_Half | 11980 SUPPORTED_100baseT_Full | 11981 SUPPORTED_1000baseT_Full | 11982 SUPPORTED_10000baseT_Full | 11983 SUPPORTED_TP | 11984 SUPPORTED_Autoneg | 11985 SUPPORTED_Pause | 11986 SUPPORTED_Asym_Pause), 11987 .media_type = ETH_PHY_BASE_T, 11988 .ver_addr = 0, 11989 .req_flow_ctrl = 0, 11990 .req_line_speed = 0, 11991 .speed_cap_mask = 0, 11992 .req_duplex = 0, 11993 .rsrv = 0, 11994 .config_init = bnx2x_848x3_config_init, 11995 .read_status = bnx2x_848xx_read_status, 11996 .link_reset = bnx2x_848x3_link_reset, 11997 .config_loopback = NULL, 11998 .format_fw_ver = bnx2x_848xx_format_ver, 11999 .hw_reset = NULL, 12000 .set_link_led = bnx2x_848xx_set_link_led, 12001 .phy_specific_func = bnx2x_848xx_specific_func 12002 }; 12003 12004 static const struct bnx2x_phy phy_84833 = { 12005 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833, 12006 .addr = 0xff, 12007 .def_md_devad = 0, 12008 .flags = (FLAGS_FAN_FAILURE_DET_REQ | 12009 FLAGS_REARM_LATCH_SIGNAL | 12010 FLAGS_TX_ERROR_CHECK), 12011 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 12012 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 12013 .mdio_ctrl = 0, 12014 .supported = (SUPPORTED_100baseT_Half | 12015 SUPPORTED_100baseT_Full | 12016 SUPPORTED_1000baseT_Full | 12017 SUPPORTED_10000baseT_Full | 12018 SUPPORTED_TP | 12019 SUPPORTED_Autoneg | 12020 SUPPORTED_Pause | 12021 SUPPORTED_Asym_Pause), 12022 .media_type = ETH_PHY_BASE_T, 12023 .ver_addr = 0, 12024 .req_flow_ctrl = 0, 12025 .req_line_speed = 0, 12026 .speed_cap_mask = 0, 12027 .req_duplex = 0, 12028 .rsrv = 0, 12029 .config_init = bnx2x_848x3_config_init, 12030 .read_status = bnx2x_848xx_read_status, 12031 .link_reset = bnx2x_848x3_link_reset, 12032 .config_loopback = NULL, 12033 .format_fw_ver = bnx2x_848xx_format_ver, 12034 .hw_reset = bnx2x_84833_hw_reset_phy, 12035 .set_link_led = bnx2x_848xx_set_link_led, 12036 .phy_specific_func = bnx2x_848xx_specific_func 12037 }; 12038 12039 static const struct bnx2x_phy phy_84834 = { 12040 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834, 12041 .addr = 0xff, 12042 .def_md_devad = 0, 12043 .flags = FLAGS_FAN_FAILURE_DET_REQ | 12044 FLAGS_REARM_LATCH_SIGNAL, 12045 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 12046 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 12047 .mdio_ctrl = 0, 12048 .supported = (SUPPORTED_100baseT_Half | 12049 SUPPORTED_100baseT_Full | 12050 SUPPORTED_1000baseT_Full | 12051 SUPPORTED_10000baseT_Full | 12052 SUPPORTED_TP | 12053 SUPPORTED_Autoneg | 12054 SUPPORTED_Pause | 12055 SUPPORTED_Asym_Pause), 12056 .media_type = ETH_PHY_BASE_T, 12057 .ver_addr = 0, 12058 .req_flow_ctrl = 0, 12059 .req_line_speed = 0, 12060 .speed_cap_mask = 0, 12061 .req_duplex = 0, 12062 .rsrv = 0, 12063 .config_init = bnx2x_848x3_config_init, 12064 .read_status = bnx2x_848xx_read_status, 12065 .link_reset = bnx2x_848x3_link_reset, 12066 .config_loopback = NULL, 12067 .format_fw_ver = bnx2x_848xx_format_ver, 12068 .hw_reset = bnx2x_84833_hw_reset_phy, 12069 .set_link_led = bnx2x_848xx_set_link_led, 12070 .phy_specific_func = bnx2x_848xx_specific_func 12071 }; 12072 12073 static const struct bnx2x_phy phy_84858 = { 12074 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858, 12075 .addr = 0xff, 12076 .def_md_devad = 0, 12077 .flags = FLAGS_FAN_FAILURE_DET_REQ | 12078 FLAGS_REARM_LATCH_SIGNAL, 12079 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 12080 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 12081 .mdio_ctrl = 0, 12082 .supported = (SUPPORTED_100baseT_Half | 12083 SUPPORTED_100baseT_Full | 12084 SUPPORTED_1000baseT_Full | 12085 SUPPORTED_10000baseT_Full | 12086 SUPPORTED_TP | 12087 SUPPORTED_Autoneg | 12088 SUPPORTED_Pause | 12089 SUPPORTED_Asym_Pause), 12090 .media_type = ETH_PHY_BASE_T, 12091 .ver_addr = 0, 12092 .req_flow_ctrl = 0, 12093 .req_line_speed = 0, 12094 .speed_cap_mask = 0, 12095 .req_duplex = 0, 12096 .rsrv = 0, 12097 .config_init = bnx2x_848x3_config_init, 12098 .read_status = bnx2x_848xx_read_status, 12099 .link_reset = bnx2x_848x3_link_reset, 12100 .config_loopback = NULL, 12101 .format_fw_ver = bnx2x_8485x_format_ver, 12102 .hw_reset = bnx2x_84833_hw_reset_phy, 12103 .set_link_led = bnx2x_848xx_set_link_led, 12104 .phy_specific_func = bnx2x_848xx_specific_func 12105 }; 12106 12107 static const struct bnx2x_phy phy_54618se = { 12108 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE, 12109 .addr = 0xff, 12110 .def_md_devad = 0, 12111 .flags = FLAGS_INIT_XGXS_FIRST, 12112 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 12113 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 12114 .mdio_ctrl = 0, 12115 .supported = (SUPPORTED_10baseT_Half | 12116 SUPPORTED_10baseT_Full | 12117 SUPPORTED_100baseT_Half | 12118 SUPPORTED_100baseT_Full | 12119 SUPPORTED_1000baseT_Full | 12120 SUPPORTED_TP | 12121 SUPPORTED_Autoneg | 12122 SUPPORTED_Pause | 12123 SUPPORTED_Asym_Pause), 12124 .media_type = ETH_PHY_BASE_T, 12125 .ver_addr = 0, 12126 .req_flow_ctrl = 0, 12127 .req_line_speed = 0, 12128 .speed_cap_mask = 0, 12129 /* req_duplex = */0, 12130 /* rsrv = */0, 12131 .config_init = bnx2x_54618se_config_init, 12132 .read_status = bnx2x_54618se_read_status, 12133 .link_reset = bnx2x_54618se_link_reset, 12134 .config_loopback = bnx2x_54618se_config_loopback, 12135 .format_fw_ver = NULL, 12136 .hw_reset = NULL, 12137 .set_link_led = bnx2x_5461x_set_link_led, 12138 .phy_specific_func = bnx2x_54618se_specific_func 12139 }; 12140 /*****************************************************************/ 12141 /* */ 12142 /* Populate the phy according. Main function: bnx2x_populate_phy */ 12143 /* */ 12144 /*****************************************************************/ 12145 12146 static void bnx2x_populate_preemphasis(struct bnx2x *bp, u32 shmem_base, 12147 struct bnx2x_phy *phy, u8 port, 12148 u8 phy_index) 12149 { 12150 /* Get the 4 lanes xgxs config rx and tx */ 12151 u32 rx = 0, tx = 0, i; 12152 for (i = 0; i < 2; i++) { 12153 /* INT_PHY and EXT_PHY1 share the same value location in 12154 * the shmem. When num_phys is greater than 1, than this value 12155 * applies only to EXT_PHY1 12156 */ 12157 if (phy_index == INT_PHY || phy_index == EXT_PHY1) { 12158 rx = REG_RD(bp, shmem_base + 12159 offsetof(struct shmem_region, 12160 dev_info.port_hw_config[port].xgxs_config_rx[i<<1])); 12161 12162 tx = REG_RD(bp, shmem_base + 12163 offsetof(struct shmem_region, 12164 dev_info.port_hw_config[port].xgxs_config_tx[i<<1])); 12165 } else { 12166 rx = REG_RD(bp, shmem_base + 12167 offsetof(struct shmem_region, 12168 dev_info.port_hw_config[port].xgxs_config2_rx[i<<1])); 12169 12170 tx = REG_RD(bp, shmem_base + 12171 offsetof(struct shmem_region, 12172 dev_info.port_hw_config[port].xgxs_config2_rx[i<<1])); 12173 } 12174 12175 phy->rx_preemphasis[i << 1] = ((rx>>16) & 0xffff); 12176 phy->rx_preemphasis[(i << 1) + 1] = (rx & 0xffff); 12177 12178 phy->tx_preemphasis[i << 1] = ((tx>>16) & 0xffff); 12179 phy->tx_preemphasis[(i << 1) + 1] = (tx & 0xffff); 12180 } 12181 } 12182 12183 static u32 bnx2x_get_ext_phy_config(struct bnx2x *bp, u32 shmem_base, 12184 u8 phy_index, u8 port) 12185 { 12186 u32 ext_phy_config = 0; 12187 switch (phy_index) { 12188 case EXT_PHY1: 12189 ext_phy_config = REG_RD(bp, shmem_base + 12190 offsetof(struct shmem_region, 12191 dev_info.port_hw_config[port].external_phy_config)); 12192 break; 12193 case EXT_PHY2: 12194 ext_phy_config = REG_RD(bp, shmem_base + 12195 offsetof(struct shmem_region, 12196 dev_info.port_hw_config[port].external_phy_config2)); 12197 break; 12198 default: 12199 DP(NETIF_MSG_LINK, "Invalid phy_index %d\n", phy_index); 12200 return -EINVAL; 12201 } 12202 12203 return ext_phy_config; 12204 } 12205 static int bnx2x_populate_int_phy(struct bnx2x *bp, u32 shmem_base, u8 port, 12206 struct bnx2x_phy *phy) 12207 { 12208 u32 phy_addr; 12209 u32 chip_id; 12210 u32 switch_cfg = (REG_RD(bp, shmem_base + 12211 offsetof(struct shmem_region, 12212 dev_info.port_feature_config[port].link_config)) & 12213 PORT_FEATURE_CONNECTED_SWITCH_MASK); 12214 chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) | 12215 ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12); 12216 12217 DP(NETIF_MSG_LINK, ":chip_id = 0x%x\n", chip_id); 12218 if (USES_WARPCORE(bp)) { 12219 u32 serdes_net_if; 12220 phy_addr = REG_RD(bp, 12221 MISC_REG_WC0_CTRL_PHY_ADDR); 12222 *phy = phy_warpcore; 12223 if (REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR) == 0x3) 12224 phy->flags |= FLAGS_4_PORT_MODE; 12225 else 12226 phy->flags &= ~FLAGS_4_PORT_MODE; 12227 /* Check Dual mode */ 12228 serdes_net_if = (REG_RD(bp, shmem_base + 12229 offsetof(struct shmem_region, dev_info. 12230 port_hw_config[port].default_cfg)) & 12231 PORT_HW_CFG_NET_SERDES_IF_MASK); 12232 /* Set the appropriate supported and flags indications per 12233 * interface type of the chip 12234 */ 12235 switch (serdes_net_if) { 12236 case PORT_HW_CFG_NET_SERDES_IF_SGMII: 12237 phy->supported &= (SUPPORTED_10baseT_Half | 12238 SUPPORTED_10baseT_Full | 12239 SUPPORTED_100baseT_Half | 12240 SUPPORTED_100baseT_Full | 12241 SUPPORTED_1000baseT_Full | 12242 SUPPORTED_FIBRE | 12243 SUPPORTED_Autoneg | 12244 SUPPORTED_Pause | 12245 SUPPORTED_Asym_Pause); 12246 phy->media_type = ETH_PHY_BASE_T; 12247 break; 12248 case PORT_HW_CFG_NET_SERDES_IF_XFI: 12249 phy->supported &= (SUPPORTED_1000baseT_Full | 12250 SUPPORTED_10000baseT_Full | 12251 SUPPORTED_FIBRE | 12252 SUPPORTED_Pause | 12253 SUPPORTED_Asym_Pause); 12254 phy->media_type = ETH_PHY_XFP_FIBER; 12255 break; 12256 case PORT_HW_CFG_NET_SERDES_IF_SFI: 12257 phy->supported &= (SUPPORTED_1000baseT_Full | 12258 SUPPORTED_10000baseT_Full | 12259 SUPPORTED_FIBRE | 12260 SUPPORTED_Pause | 12261 SUPPORTED_Asym_Pause); 12262 phy->media_type = ETH_PHY_SFPP_10G_FIBER; 12263 break; 12264 case PORT_HW_CFG_NET_SERDES_IF_KR: 12265 phy->media_type = ETH_PHY_KR; 12266 phy->supported &= (SUPPORTED_1000baseKX_Full | 12267 SUPPORTED_10000baseKR_Full | 12268 SUPPORTED_FIBRE | 12269 SUPPORTED_Autoneg | 12270 SUPPORTED_Pause | 12271 SUPPORTED_Asym_Pause); 12272 break; 12273 case PORT_HW_CFG_NET_SERDES_IF_DXGXS: 12274 phy->media_type = ETH_PHY_KR; 12275 phy->flags |= FLAGS_WC_DUAL_MODE; 12276 phy->supported &= (SUPPORTED_20000baseMLD2_Full | 12277 SUPPORTED_FIBRE | 12278 SUPPORTED_Pause | 12279 SUPPORTED_Asym_Pause); 12280 break; 12281 case PORT_HW_CFG_NET_SERDES_IF_KR2: 12282 phy->media_type = ETH_PHY_KR; 12283 phy->flags |= FLAGS_WC_DUAL_MODE; 12284 phy->supported &= (SUPPORTED_20000baseKR2_Full | 12285 SUPPORTED_10000baseKR_Full | 12286 SUPPORTED_1000baseKX_Full | 12287 SUPPORTED_Autoneg | 12288 SUPPORTED_FIBRE | 12289 SUPPORTED_Pause | 12290 SUPPORTED_Asym_Pause); 12291 phy->flags &= ~FLAGS_TX_ERROR_CHECK; 12292 break; 12293 default: 12294 DP(NETIF_MSG_LINK, "Unknown WC interface type 0x%x\n", 12295 serdes_net_if); 12296 break; 12297 } 12298 12299 /* Enable MDC/MDIO work-around for E3 A0 since free running MDC 12300 * was not set as expected. For B0, ECO will be enabled so there 12301 * won't be an issue there 12302 */ 12303 if (CHIP_REV(bp) == CHIP_REV_Ax) 12304 phy->flags |= FLAGS_MDC_MDIO_WA; 12305 else 12306 phy->flags |= FLAGS_MDC_MDIO_WA_B0; 12307 } else { 12308 switch (switch_cfg) { 12309 case SWITCH_CFG_1G: 12310 phy_addr = REG_RD(bp, 12311 NIG_REG_SERDES0_CTRL_PHY_ADDR + 12312 port * 0x10); 12313 *phy = phy_serdes; 12314 break; 12315 case SWITCH_CFG_10G: 12316 phy_addr = REG_RD(bp, 12317 NIG_REG_XGXS0_CTRL_PHY_ADDR + 12318 port * 0x18); 12319 *phy = phy_xgxs; 12320 break; 12321 default: 12322 DP(NETIF_MSG_LINK, "Invalid switch_cfg\n"); 12323 return -EINVAL; 12324 } 12325 } 12326 phy->addr = (u8)phy_addr; 12327 phy->mdio_ctrl = bnx2x_get_emac_base(bp, 12328 SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH, 12329 port); 12330 if (CHIP_IS_E2(bp)) 12331 phy->def_md_devad = E2_DEFAULT_PHY_DEV_ADDR; 12332 else 12333 phy->def_md_devad = DEFAULT_PHY_DEV_ADDR; 12334 12335 DP(NETIF_MSG_LINK, "Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x\n", 12336 port, phy->addr, phy->mdio_ctrl); 12337 12338 bnx2x_populate_preemphasis(bp, shmem_base, phy, port, INT_PHY); 12339 return 0; 12340 } 12341 12342 static int bnx2x_populate_ext_phy(struct bnx2x *bp, 12343 u8 phy_index, 12344 u32 shmem_base, 12345 u32 shmem2_base, 12346 u8 port, 12347 struct bnx2x_phy *phy) 12348 { 12349 u32 ext_phy_config, phy_type, config2; 12350 u32 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH; 12351 ext_phy_config = bnx2x_get_ext_phy_config(bp, shmem_base, 12352 phy_index, port); 12353 phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config); 12354 /* Select the phy type */ 12355 switch (phy_type) { 12356 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073: 12357 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED; 12358 *phy = phy_8073; 12359 break; 12360 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705: 12361 *phy = phy_8705; 12362 break; 12363 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706: 12364 *phy = phy_8706; 12365 break; 12366 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: 12367 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1; 12368 *phy = phy_8726; 12369 break; 12370 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC: 12371 /* BCM8727_NOC => BCM8727 no over current */ 12372 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1; 12373 *phy = phy_8727; 12374 phy->flags |= FLAGS_NOC; 12375 break; 12376 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722: 12377 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: 12378 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1; 12379 *phy = phy_8727; 12380 break; 12381 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481: 12382 *phy = phy_8481; 12383 break; 12384 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823: 12385 *phy = phy_84823; 12386 break; 12387 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833: 12388 *phy = phy_84833; 12389 break; 12390 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834: 12391 *phy = phy_84834; 12392 break; 12393 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858: 12394 *phy = phy_84858; 12395 break; 12396 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616: 12397 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE: 12398 *phy = phy_54618se; 12399 if (phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) 12400 phy->flags |= FLAGS_EEE; 12401 break; 12402 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101: 12403 *phy = phy_7101; 12404 break; 12405 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE: 12406 *phy = phy_null; 12407 return -EINVAL; 12408 default: 12409 *phy = phy_null; 12410 /* In case external PHY wasn't found */ 12411 if ((phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) && 12412 (phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)) 12413 return -EINVAL; 12414 return 0; 12415 } 12416 12417 phy->addr = XGXS_EXT_PHY_ADDR(ext_phy_config); 12418 bnx2x_populate_preemphasis(bp, shmem_base, phy, port, phy_index); 12419 12420 /* The shmem address of the phy version is located on different 12421 * structures. In case this structure is too old, do not set 12422 * the address 12423 */ 12424 config2 = REG_RD(bp, shmem_base + offsetof(struct shmem_region, 12425 dev_info.shared_hw_config.config2)); 12426 if (phy_index == EXT_PHY1) { 12427 phy->ver_addr = shmem_base + offsetof(struct shmem_region, 12428 port_mb[port].ext_phy_fw_version); 12429 12430 /* Check specific mdc mdio settings */ 12431 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK) 12432 mdc_mdio_access = config2 & 12433 SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK; 12434 } else { 12435 u32 size = REG_RD(bp, shmem2_base); 12436 12437 if (size > 12438 offsetof(struct shmem2_region, ext_phy_fw_version2)) { 12439 phy->ver_addr = shmem2_base + 12440 offsetof(struct shmem2_region, 12441 ext_phy_fw_version2[port]); 12442 } 12443 /* Check specific mdc mdio settings */ 12444 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) 12445 mdc_mdio_access = (config2 & 12446 SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) >> 12447 (SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT - 12448 SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT); 12449 } 12450 phy->mdio_ctrl = bnx2x_get_emac_base(bp, mdc_mdio_access, port); 12451 12452 if (bnx2x_is_8483x_8485x(phy) && (phy->ver_addr)) { 12453 /* Remove 100Mb link supported for BCM84833/4 when phy fw 12454 * version lower than or equal to 1.39 12455 */ 12456 u32 raw_ver = REG_RD(bp, phy->ver_addr); 12457 if (((raw_ver & 0x7F) <= 39) && 12458 (((raw_ver & 0xF80) >> 7) <= 1)) 12459 phy->supported &= ~(SUPPORTED_100baseT_Half | 12460 SUPPORTED_100baseT_Full); 12461 } 12462 12463 DP(NETIF_MSG_LINK, "phy_type 0x%x port %d found in index %d\n", 12464 phy_type, port, phy_index); 12465 DP(NETIF_MSG_LINK, " addr=0x%x, mdio_ctl=0x%x\n", 12466 phy->addr, phy->mdio_ctrl); 12467 return 0; 12468 } 12469 12470 static int bnx2x_populate_phy(struct bnx2x *bp, u8 phy_index, u32 shmem_base, 12471 u32 shmem2_base, u8 port, struct bnx2x_phy *phy) 12472 { 12473 phy->type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN; 12474 if (phy_index == INT_PHY) 12475 return bnx2x_populate_int_phy(bp, shmem_base, port, phy); 12476 12477 return bnx2x_populate_ext_phy(bp, phy_index, shmem_base, shmem2_base, 12478 port, phy); 12479 } 12480 12481 static void bnx2x_phy_def_cfg(struct link_params *params, 12482 struct bnx2x_phy *phy, 12483 u8 phy_index) 12484 { 12485 struct bnx2x *bp = params->bp; 12486 u32 link_config; 12487 /* Populate the default phy configuration for MF mode */ 12488 if (phy_index == EXT_PHY2) { 12489 link_config = REG_RD(bp, params->shmem_base + 12490 offsetof(struct shmem_region, dev_info. 12491 port_feature_config[params->port].link_config2)); 12492 phy->speed_cap_mask = REG_RD(bp, params->shmem_base + 12493 offsetof(struct shmem_region, 12494 dev_info. 12495 port_hw_config[params->port].speed_capability_mask2)); 12496 } else { 12497 link_config = REG_RD(bp, params->shmem_base + 12498 offsetof(struct shmem_region, dev_info. 12499 port_feature_config[params->port].link_config)); 12500 phy->speed_cap_mask = REG_RD(bp, params->shmem_base + 12501 offsetof(struct shmem_region, 12502 dev_info. 12503 port_hw_config[params->port].speed_capability_mask)); 12504 } 12505 DP(NETIF_MSG_LINK, 12506 "Default config phy idx %x cfg 0x%x speed_cap_mask 0x%x\n", 12507 phy_index, link_config, phy->speed_cap_mask); 12508 12509 phy->req_duplex = DUPLEX_FULL; 12510 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) { 12511 case PORT_FEATURE_LINK_SPEED_10M_HALF: 12512 phy->req_duplex = DUPLEX_HALF; 12513 fallthrough; 12514 case PORT_FEATURE_LINK_SPEED_10M_FULL: 12515 phy->req_line_speed = SPEED_10; 12516 break; 12517 case PORT_FEATURE_LINK_SPEED_100M_HALF: 12518 phy->req_duplex = DUPLEX_HALF; 12519 fallthrough; 12520 case PORT_FEATURE_LINK_SPEED_100M_FULL: 12521 phy->req_line_speed = SPEED_100; 12522 break; 12523 case PORT_FEATURE_LINK_SPEED_1G: 12524 phy->req_line_speed = SPEED_1000; 12525 break; 12526 case PORT_FEATURE_LINK_SPEED_2_5G: 12527 phy->req_line_speed = SPEED_2500; 12528 break; 12529 case PORT_FEATURE_LINK_SPEED_10G_CX4: 12530 phy->req_line_speed = SPEED_10000; 12531 break; 12532 default: 12533 phy->req_line_speed = SPEED_AUTO_NEG; 12534 break; 12535 } 12536 12537 switch (link_config & PORT_FEATURE_FLOW_CONTROL_MASK) { 12538 case PORT_FEATURE_FLOW_CONTROL_AUTO: 12539 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_AUTO; 12540 break; 12541 case PORT_FEATURE_FLOW_CONTROL_TX: 12542 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_TX; 12543 break; 12544 case PORT_FEATURE_FLOW_CONTROL_RX: 12545 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_RX; 12546 break; 12547 case PORT_FEATURE_FLOW_CONTROL_BOTH: 12548 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_BOTH; 12549 break; 12550 default: 12551 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_NONE; 12552 break; 12553 } 12554 } 12555 12556 u32 bnx2x_phy_selection(struct link_params *params) 12557 { 12558 u32 phy_config_swapped, prio_cfg; 12559 u32 return_cfg = PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT; 12560 12561 phy_config_swapped = params->multi_phy_config & 12562 PORT_HW_CFG_PHY_SWAPPED_ENABLED; 12563 12564 prio_cfg = params->multi_phy_config & 12565 PORT_HW_CFG_PHY_SELECTION_MASK; 12566 12567 if (phy_config_swapped) { 12568 switch (prio_cfg) { 12569 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY: 12570 return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY; 12571 break; 12572 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY: 12573 return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY; 12574 break; 12575 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY: 12576 return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY; 12577 break; 12578 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY: 12579 return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY; 12580 break; 12581 } 12582 } else 12583 return_cfg = prio_cfg; 12584 12585 return return_cfg; 12586 } 12587 12588 int bnx2x_phy_probe(struct link_params *params) 12589 { 12590 u8 phy_index, actual_phy_idx; 12591 u32 phy_config_swapped, sync_offset, media_types; 12592 struct bnx2x *bp = params->bp; 12593 struct bnx2x_phy *phy; 12594 params->num_phys = 0; 12595 DP(NETIF_MSG_LINK, "Begin phy probe\n"); 12596 phy_config_swapped = params->multi_phy_config & 12597 PORT_HW_CFG_PHY_SWAPPED_ENABLED; 12598 12599 for (phy_index = INT_PHY; phy_index < MAX_PHYS; 12600 phy_index++) { 12601 actual_phy_idx = phy_index; 12602 if (phy_config_swapped) { 12603 if (phy_index == EXT_PHY1) 12604 actual_phy_idx = EXT_PHY2; 12605 else if (phy_index == EXT_PHY2) 12606 actual_phy_idx = EXT_PHY1; 12607 } 12608 DP(NETIF_MSG_LINK, "phy_config_swapped %x, phy_index %x," 12609 " actual_phy_idx %x\n", phy_config_swapped, 12610 phy_index, actual_phy_idx); 12611 phy = ¶ms->phy[actual_phy_idx]; 12612 if (bnx2x_populate_phy(bp, phy_index, params->shmem_base, 12613 params->shmem2_base, params->port, 12614 phy) != 0) { 12615 params->num_phys = 0; 12616 DP(NETIF_MSG_LINK, "phy probe failed in phy index %d\n", 12617 phy_index); 12618 for (phy_index = INT_PHY; 12619 phy_index < MAX_PHYS; 12620 phy_index++) 12621 *phy = phy_null; 12622 return -EINVAL; 12623 } 12624 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN) 12625 break; 12626 12627 if (params->feature_config_flags & 12628 FEATURE_CONFIG_DISABLE_REMOTE_FAULT_DET) 12629 phy->flags &= ~FLAGS_TX_ERROR_CHECK; 12630 12631 if (!(params->feature_config_flags & 12632 FEATURE_CONFIG_MT_SUPPORT)) 12633 phy->flags |= FLAGS_MDC_MDIO_WA_G; 12634 12635 sync_offset = params->shmem_base + 12636 offsetof(struct shmem_region, 12637 dev_info.port_hw_config[params->port].media_type); 12638 media_types = REG_RD(bp, sync_offset); 12639 12640 /* Update media type for non-PMF sync only for the first time 12641 * In case the media type changes afterwards, it will be updated 12642 * using the update_status function 12643 */ 12644 if ((media_types & (PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK << 12645 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * 12646 actual_phy_idx))) == 0) { 12647 media_types |= ((phy->media_type & 12648 PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) << 12649 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * 12650 actual_phy_idx)); 12651 } 12652 REG_WR(bp, sync_offset, media_types); 12653 12654 bnx2x_phy_def_cfg(params, phy, phy_index); 12655 params->num_phys++; 12656 } 12657 12658 DP(NETIF_MSG_LINK, "End phy probe. #phys found %x\n", params->num_phys); 12659 return 0; 12660 } 12661 12662 static void bnx2x_init_bmac_loopback(struct link_params *params, 12663 struct link_vars *vars) 12664 { 12665 struct bnx2x *bp = params->bp; 12666 vars->link_up = 1; 12667 vars->line_speed = SPEED_10000; 12668 vars->duplex = DUPLEX_FULL; 12669 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; 12670 vars->mac_type = MAC_TYPE_BMAC; 12671 12672 vars->phy_flags = PHY_XGXS_FLAG; 12673 12674 bnx2x_xgxs_deassert(params); 12675 12676 /* Set bmac loopback */ 12677 bnx2x_bmac_enable(params, vars, 1, 1); 12678 12679 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0); 12680 } 12681 12682 static void bnx2x_init_emac_loopback(struct link_params *params, 12683 struct link_vars *vars) 12684 { 12685 struct bnx2x *bp = params->bp; 12686 vars->link_up = 1; 12687 vars->line_speed = SPEED_1000; 12688 vars->duplex = DUPLEX_FULL; 12689 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; 12690 vars->mac_type = MAC_TYPE_EMAC; 12691 12692 vars->phy_flags = PHY_XGXS_FLAG; 12693 12694 bnx2x_xgxs_deassert(params); 12695 /* Set bmac loopback */ 12696 bnx2x_emac_enable(params, vars, 1); 12697 bnx2x_emac_program(params, vars); 12698 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0); 12699 } 12700 12701 static void bnx2x_init_xmac_loopback(struct link_params *params, 12702 struct link_vars *vars) 12703 { 12704 struct bnx2x *bp = params->bp; 12705 vars->link_up = 1; 12706 if (!params->req_line_speed[0]) 12707 vars->line_speed = SPEED_10000; 12708 else 12709 vars->line_speed = params->req_line_speed[0]; 12710 vars->duplex = DUPLEX_FULL; 12711 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; 12712 vars->mac_type = MAC_TYPE_XMAC; 12713 vars->phy_flags = PHY_XGXS_FLAG; 12714 /* Set WC to loopback mode since link is required to provide clock 12715 * to the XMAC in 20G mode 12716 */ 12717 bnx2x_set_aer_mmd(params, ¶ms->phy[0]); 12718 bnx2x_warpcore_reset_lane(bp, ¶ms->phy[0], 0); 12719 params->phy[INT_PHY].config_loopback( 12720 ¶ms->phy[INT_PHY], 12721 params); 12722 12723 bnx2x_xmac_enable(params, vars, 1); 12724 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); 12725 } 12726 12727 static void bnx2x_init_umac_loopback(struct link_params *params, 12728 struct link_vars *vars) 12729 { 12730 struct bnx2x *bp = params->bp; 12731 vars->link_up = 1; 12732 vars->line_speed = SPEED_1000; 12733 vars->duplex = DUPLEX_FULL; 12734 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; 12735 vars->mac_type = MAC_TYPE_UMAC; 12736 vars->phy_flags = PHY_XGXS_FLAG; 12737 bnx2x_umac_enable(params, vars, 1); 12738 12739 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); 12740 } 12741 12742 static void bnx2x_init_xgxs_loopback(struct link_params *params, 12743 struct link_vars *vars) 12744 { 12745 struct bnx2x *bp = params->bp; 12746 struct bnx2x_phy *int_phy = ¶ms->phy[INT_PHY]; 12747 vars->link_up = 1; 12748 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; 12749 vars->duplex = DUPLEX_FULL; 12750 if (params->req_line_speed[0] == SPEED_1000) 12751 vars->line_speed = SPEED_1000; 12752 else if ((params->req_line_speed[0] == SPEED_20000) || 12753 (int_phy->flags & FLAGS_WC_DUAL_MODE)) 12754 vars->line_speed = SPEED_20000; 12755 else 12756 vars->line_speed = SPEED_10000; 12757 12758 if (!USES_WARPCORE(bp)) 12759 bnx2x_xgxs_deassert(params); 12760 bnx2x_link_initialize(params, vars); 12761 12762 if (params->req_line_speed[0] == SPEED_1000) { 12763 if (USES_WARPCORE(bp)) 12764 bnx2x_umac_enable(params, vars, 0); 12765 else { 12766 bnx2x_emac_program(params, vars); 12767 bnx2x_emac_enable(params, vars, 0); 12768 } 12769 } else { 12770 if (USES_WARPCORE(bp)) 12771 bnx2x_xmac_enable(params, vars, 0); 12772 else 12773 bnx2x_bmac_enable(params, vars, 0, 1); 12774 } 12775 12776 if (params->loopback_mode == LOOPBACK_XGXS) { 12777 /* Set 10G XGXS loopback */ 12778 int_phy->config_loopback(int_phy, params); 12779 } else { 12780 /* Set external phy loopback */ 12781 u8 phy_index; 12782 for (phy_index = EXT_PHY1; 12783 phy_index < params->num_phys; phy_index++) 12784 if (params->phy[phy_index].config_loopback) 12785 params->phy[phy_index].config_loopback( 12786 ¶ms->phy[phy_index], 12787 params); 12788 } 12789 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); 12790 12791 bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed); 12792 } 12793 12794 void bnx2x_set_rx_filter(struct link_params *params, u8 en) 12795 { 12796 struct bnx2x *bp = params->bp; 12797 u8 val = en * 0x1F; 12798 12799 /* Open / close the gate between the NIG and the BRB */ 12800 if (!CHIP_IS_E1x(bp)) 12801 val |= en * 0x20; 12802 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + params->port*4, val); 12803 12804 if (!CHIP_IS_E1(bp)) { 12805 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + params->port*4, 12806 en*0x3); 12807 } 12808 12809 REG_WR(bp, (params->port ? NIG_REG_LLH1_BRB1_NOT_MCP : 12810 NIG_REG_LLH0_BRB1_NOT_MCP), en); 12811 } 12812 static int bnx2x_avoid_link_flap(struct link_params *params, 12813 struct link_vars *vars) 12814 { 12815 u32 phy_idx; 12816 u32 dont_clear_stat, lfa_sts; 12817 struct bnx2x *bp = params->bp; 12818 12819 bnx2x_set_mdio_emac_per_phy(bp, params); 12820 /* Sync the link parameters */ 12821 bnx2x_link_status_update(params, vars); 12822 12823 /* 12824 * The module verification was already done by previous link owner, 12825 * so this call is meant only to get warning message 12826 */ 12827 12828 for (phy_idx = INT_PHY; phy_idx < params->num_phys; phy_idx++) { 12829 struct bnx2x_phy *phy = ¶ms->phy[phy_idx]; 12830 if (phy->phy_specific_func) { 12831 DP(NETIF_MSG_LINK, "Calling PHY specific func\n"); 12832 phy->phy_specific_func(phy, params, PHY_INIT); 12833 } 12834 if ((phy->media_type == ETH_PHY_SFPP_10G_FIBER) || 12835 (phy->media_type == ETH_PHY_SFP_1G_FIBER) || 12836 (phy->media_type == ETH_PHY_DA_TWINAX)) 12837 bnx2x_verify_sfp_module(phy, params); 12838 } 12839 lfa_sts = REG_RD(bp, params->lfa_base + 12840 offsetof(struct shmem_lfa, 12841 lfa_sts)); 12842 12843 dont_clear_stat = lfa_sts & SHMEM_LFA_DONT_CLEAR_STAT; 12844 12845 /* Re-enable the NIG/MAC */ 12846 if (CHIP_IS_E3(bp)) { 12847 if (!dont_clear_stat) { 12848 REG_WR(bp, GRCBASE_MISC + 12849 MISC_REGISTERS_RESET_REG_2_CLEAR, 12850 (MISC_REGISTERS_RESET_REG_2_MSTAT0 << 12851 params->port)); 12852 REG_WR(bp, GRCBASE_MISC + 12853 MISC_REGISTERS_RESET_REG_2_SET, 12854 (MISC_REGISTERS_RESET_REG_2_MSTAT0 << 12855 params->port)); 12856 } 12857 if (vars->line_speed < SPEED_10000) 12858 bnx2x_umac_enable(params, vars, 0); 12859 else 12860 bnx2x_xmac_enable(params, vars, 0); 12861 } else { 12862 if (vars->line_speed < SPEED_10000) 12863 bnx2x_emac_enable(params, vars, 0); 12864 else 12865 bnx2x_bmac_enable(params, vars, 0, !dont_clear_stat); 12866 } 12867 12868 /* Increment LFA count */ 12869 lfa_sts = ((lfa_sts & ~LINK_FLAP_AVOIDANCE_COUNT_MASK) | 12870 (((((lfa_sts & LINK_FLAP_AVOIDANCE_COUNT_MASK) >> 12871 LINK_FLAP_AVOIDANCE_COUNT_OFFSET) + 1) & 0xff) 12872 << LINK_FLAP_AVOIDANCE_COUNT_OFFSET)); 12873 /* Clear link flap reason */ 12874 lfa_sts &= ~LFA_LINK_FLAP_REASON_MASK; 12875 12876 REG_WR(bp, params->lfa_base + 12877 offsetof(struct shmem_lfa, lfa_sts), lfa_sts); 12878 12879 /* Disable NIG DRAIN */ 12880 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); 12881 12882 /* Enable interrupts */ 12883 bnx2x_link_int_enable(params); 12884 return 0; 12885 } 12886 12887 static void bnx2x_cannot_avoid_link_flap(struct link_params *params, 12888 struct link_vars *vars, 12889 int lfa_status) 12890 { 12891 u32 lfa_sts, cfg_idx, tmp_val; 12892 struct bnx2x *bp = params->bp; 12893 12894 bnx2x_link_reset(params, vars, 1); 12895 12896 if (!params->lfa_base) 12897 return; 12898 /* Store the new link parameters */ 12899 REG_WR(bp, params->lfa_base + 12900 offsetof(struct shmem_lfa, req_duplex), 12901 params->req_duplex[0] | (params->req_duplex[1] << 16)); 12902 12903 REG_WR(bp, params->lfa_base + 12904 offsetof(struct shmem_lfa, req_flow_ctrl), 12905 params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16)); 12906 12907 REG_WR(bp, params->lfa_base + 12908 offsetof(struct shmem_lfa, req_line_speed), 12909 params->req_line_speed[0] | (params->req_line_speed[1] << 16)); 12910 12911 for (cfg_idx = 0; cfg_idx < SHMEM_LINK_CONFIG_SIZE; cfg_idx++) { 12912 REG_WR(bp, params->lfa_base + 12913 offsetof(struct shmem_lfa, 12914 speed_cap_mask[cfg_idx]), 12915 params->speed_cap_mask[cfg_idx]); 12916 } 12917 12918 tmp_val = REG_RD(bp, params->lfa_base + 12919 offsetof(struct shmem_lfa, additional_config)); 12920 tmp_val &= ~REQ_FC_AUTO_ADV_MASK; 12921 tmp_val |= params->req_fc_auto_adv; 12922 12923 REG_WR(bp, params->lfa_base + 12924 offsetof(struct shmem_lfa, additional_config), tmp_val); 12925 12926 lfa_sts = REG_RD(bp, params->lfa_base + 12927 offsetof(struct shmem_lfa, lfa_sts)); 12928 12929 /* Clear the "Don't Clear Statistics" bit, and set reason */ 12930 lfa_sts &= ~SHMEM_LFA_DONT_CLEAR_STAT; 12931 12932 /* Set link flap reason */ 12933 lfa_sts &= ~LFA_LINK_FLAP_REASON_MASK; 12934 lfa_sts |= ((lfa_status & LFA_LINK_FLAP_REASON_MASK) << 12935 LFA_LINK_FLAP_REASON_OFFSET); 12936 12937 /* Increment link flap counter */ 12938 lfa_sts = ((lfa_sts & ~LINK_FLAP_COUNT_MASK) | 12939 (((((lfa_sts & LINK_FLAP_COUNT_MASK) >> 12940 LINK_FLAP_COUNT_OFFSET) + 1) & 0xff) 12941 << LINK_FLAP_COUNT_OFFSET)); 12942 REG_WR(bp, params->lfa_base + 12943 offsetof(struct shmem_lfa, lfa_sts), lfa_sts); 12944 /* Proceed with regular link initialization */ 12945 } 12946 12947 int bnx2x_phy_init(struct link_params *params, struct link_vars *vars) 12948 { 12949 int lfa_status; 12950 struct bnx2x *bp = params->bp; 12951 DP(NETIF_MSG_LINK, "Phy Initialization started\n"); 12952 DP(NETIF_MSG_LINK, "(1) req_speed %d, req_flowctrl %d\n", 12953 params->req_line_speed[0], params->req_flow_ctrl[0]); 12954 DP(NETIF_MSG_LINK, "(2) req_speed %d, req_flowctrl %d\n", 12955 params->req_line_speed[1], params->req_flow_ctrl[1]); 12956 DP(NETIF_MSG_LINK, "req_adv_flow_ctrl 0x%x\n", params->req_fc_auto_adv); 12957 vars->link_status = 0; 12958 vars->phy_link_up = 0; 12959 vars->link_up = 0; 12960 vars->line_speed = 0; 12961 vars->duplex = DUPLEX_FULL; 12962 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; 12963 vars->mac_type = MAC_TYPE_NONE; 12964 vars->phy_flags = 0; 12965 vars->check_kr2_recovery_cnt = 0; 12966 params->link_flags = PHY_INITIALIZED; 12967 /* Driver opens NIG-BRB filters */ 12968 bnx2x_set_rx_filter(params, 1); 12969 bnx2x_chng_link_count(params, true); 12970 /* Check if link flap can be avoided */ 12971 lfa_status = bnx2x_check_lfa(params); 12972 12973 if (lfa_status == 0) { 12974 DP(NETIF_MSG_LINK, "Link Flap Avoidance in progress\n"); 12975 return bnx2x_avoid_link_flap(params, vars); 12976 } 12977 12978 DP(NETIF_MSG_LINK, "Cannot avoid link flap lfa_sta=0x%x\n", 12979 lfa_status); 12980 bnx2x_cannot_avoid_link_flap(params, vars, lfa_status); 12981 12982 /* Disable attentions */ 12983 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4, 12984 (NIG_MASK_XGXS0_LINK_STATUS | 12985 NIG_MASK_XGXS0_LINK10G | 12986 NIG_MASK_SERDES0_LINK_STATUS | 12987 NIG_MASK_MI_INT)); 12988 12989 bnx2x_emac_init(params, vars); 12990 12991 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) 12992 vars->link_status |= LINK_STATUS_PFC_ENABLED; 12993 12994 if (params->num_phys == 0) { 12995 DP(NETIF_MSG_LINK, "No phy found for initialization !!\n"); 12996 return -EINVAL; 12997 } 12998 set_phy_vars(params, vars); 12999 13000 DP(NETIF_MSG_LINK, "Num of phys on board: %d\n", params->num_phys); 13001 switch (params->loopback_mode) { 13002 case LOOPBACK_BMAC: 13003 bnx2x_init_bmac_loopback(params, vars); 13004 break; 13005 case LOOPBACK_EMAC: 13006 bnx2x_init_emac_loopback(params, vars); 13007 break; 13008 case LOOPBACK_XMAC: 13009 bnx2x_init_xmac_loopback(params, vars); 13010 break; 13011 case LOOPBACK_UMAC: 13012 bnx2x_init_umac_loopback(params, vars); 13013 break; 13014 case LOOPBACK_XGXS: 13015 case LOOPBACK_EXT_PHY: 13016 bnx2x_init_xgxs_loopback(params, vars); 13017 break; 13018 default: 13019 if (!CHIP_IS_E3(bp)) { 13020 if (params->switch_cfg == SWITCH_CFG_10G) 13021 bnx2x_xgxs_deassert(params); 13022 else 13023 bnx2x_serdes_deassert(bp, params->port); 13024 } 13025 bnx2x_link_initialize(params, vars); 13026 msleep(30); 13027 bnx2x_link_int_enable(params); 13028 break; 13029 } 13030 bnx2x_update_mng(params, vars->link_status); 13031 13032 bnx2x_update_mng_eee(params, vars->eee_status); 13033 return 0; 13034 } 13035 13036 int bnx2x_link_reset(struct link_params *params, struct link_vars *vars, 13037 u8 reset_ext_phy) 13038 { 13039 struct bnx2x *bp = params->bp; 13040 u8 phy_index, port = params->port, clear_latch_ind = 0; 13041 DP(NETIF_MSG_LINK, "Resetting the link of port %d\n", port); 13042 /* Disable attentions */ 13043 vars->link_status = 0; 13044 bnx2x_chng_link_count(params, true); 13045 bnx2x_update_mng(params, vars->link_status); 13046 vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK | 13047 SHMEM_EEE_ACTIVE_BIT); 13048 bnx2x_update_mng_eee(params, vars->eee_status); 13049 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 13050 (NIG_MASK_XGXS0_LINK_STATUS | 13051 NIG_MASK_XGXS0_LINK10G | 13052 NIG_MASK_SERDES0_LINK_STATUS | 13053 NIG_MASK_MI_INT)); 13054 13055 /* Activate nig drain */ 13056 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1); 13057 13058 /* Disable nig egress interface */ 13059 if (!CHIP_IS_E3(bp)) { 13060 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0); 13061 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0); 13062 } 13063 13064 if (!CHIP_IS_E3(bp)) { 13065 bnx2x_set_bmac_rx(bp, params->chip_id, port, 0); 13066 } else { 13067 bnx2x_set_xmac_rxtx(params, 0); 13068 bnx2x_set_umac_rxtx(params, 0); 13069 } 13070 /* Disable emac */ 13071 if (!CHIP_IS_E3(bp)) 13072 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0); 13073 13074 usleep_range(10000, 20000); 13075 /* The PHY reset is controlled by GPIO 1 13076 * Hold it as vars low 13077 */ 13078 /* Clear link led */ 13079 bnx2x_set_mdio_emac_per_phy(bp, params); 13080 bnx2x_set_led(params, vars, LED_MODE_OFF, 0); 13081 13082 if (reset_ext_phy) { 13083 for (phy_index = EXT_PHY1; phy_index < params->num_phys; 13084 phy_index++) { 13085 if (params->phy[phy_index].link_reset) { 13086 bnx2x_set_aer_mmd(params, 13087 ¶ms->phy[phy_index]); 13088 params->phy[phy_index].link_reset( 13089 ¶ms->phy[phy_index], 13090 params); 13091 } 13092 if (params->phy[phy_index].flags & 13093 FLAGS_REARM_LATCH_SIGNAL) 13094 clear_latch_ind = 1; 13095 } 13096 } 13097 13098 if (clear_latch_ind) { 13099 /* Clear latching indication */ 13100 bnx2x_rearm_latch_signal(bp, port, 0); 13101 bnx2x_bits_dis(bp, NIG_REG_LATCH_BC_0 + port*4, 13102 1 << NIG_LATCH_BC_ENABLE_MI_INT); 13103 } 13104 if (params->phy[INT_PHY].link_reset) 13105 params->phy[INT_PHY].link_reset( 13106 ¶ms->phy[INT_PHY], params); 13107 13108 /* Disable nig ingress interface */ 13109 if (!CHIP_IS_E3(bp)) { 13110 /* Reset BigMac */ 13111 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 13112 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); 13113 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0); 13114 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0); 13115 } else { 13116 u32 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; 13117 bnx2x_set_xumac_nig(params, 0, 0); 13118 if (REG_RD(bp, MISC_REG_RESET_REG_2) & 13119 MISC_REGISTERS_RESET_REG_2_XMAC) 13120 REG_WR(bp, xmac_base + XMAC_REG_CTRL, 13121 XMAC_CTRL_REG_SOFT_RESET); 13122 } 13123 vars->link_up = 0; 13124 vars->phy_flags = 0; 13125 return 0; 13126 } 13127 int bnx2x_lfa_reset(struct link_params *params, 13128 struct link_vars *vars) 13129 { 13130 struct bnx2x *bp = params->bp; 13131 vars->link_up = 0; 13132 vars->phy_flags = 0; 13133 params->link_flags &= ~PHY_INITIALIZED; 13134 if (!params->lfa_base) 13135 return bnx2x_link_reset(params, vars, 1); 13136 /* 13137 * Activate NIG drain so that during this time the device won't send 13138 * anything while it is unable to response. 13139 */ 13140 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1); 13141 13142 /* 13143 * Close gracefully the gate from BMAC to NIG such that no half packets 13144 * are passed. 13145 */ 13146 if (!CHIP_IS_E3(bp)) 13147 bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 0); 13148 13149 if (CHIP_IS_E3(bp)) { 13150 bnx2x_set_xmac_rxtx(params, 0); 13151 bnx2x_set_umac_rxtx(params, 0); 13152 } 13153 /* Wait 10ms for the pipe to clean up*/ 13154 usleep_range(10000, 20000); 13155 13156 /* Clean the NIG-BRB using the network filters in a way that will 13157 * not cut a packet in the middle. 13158 */ 13159 bnx2x_set_rx_filter(params, 0); 13160 13161 /* 13162 * Re-open the gate between the BMAC and the NIG, after verifying the 13163 * gate to the BRB is closed, otherwise packets may arrive to the 13164 * firmware before driver had initialized it. The target is to achieve 13165 * minimum management protocol down time. 13166 */ 13167 if (!CHIP_IS_E3(bp)) 13168 bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 1); 13169 13170 if (CHIP_IS_E3(bp)) { 13171 bnx2x_set_xmac_rxtx(params, 1); 13172 bnx2x_set_umac_rxtx(params, 1); 13173 } 13174 /* Disable NIG drain */ 13175 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); 13176 return 0; 13177 } 13178 13179 /****************************************************************************/ 13180 /* Common function */ 13181 /****************************************************************************/ 13182 static int bnx2x_8073_common_init_phy(struct bnx2x *bp, 13183 u32 shmem_base_path[], 13184 u32 shmem2_base_path[], u8 phy_index, 13185 u32 chip_id) 13186 { 13187 struct bnx2x_phy phy[PORT_MAX]; 13188 struct bnx2x_phy *phy_blk[PORT_MAX]; 13189 u16 val; 13190 s8 port = 0; 13191 s8 port_of_path = 0; 13192 u32 swap_val, swap_override; 13193 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); 13194 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); 13195 port ^= (swap_val && swap_override); 13196 bnx2x_ext_phy_hw_reset(bp, port); 13197 /* PART1 - Reset both phys */ 13198 for (port = PORT_MAX - 1; port >= PORT_0; port--) { 13199 u32 shmem_base, shmem2_base; 13200 /* In E2, same phy is using for port0 of the two paths */ 13201 if (CHIP_IS_E1x(bp)) { 13202 shmem_base = shmem_base_path[0]; 13203 shmem2_base = shmem2_base_path[0]; 13204 port_of_path = port; 13205 } else { 13206 shmem_base = shmem_base_path[port]; 13207 shmem2_base = shmem2_base_path[port]; 13208 port_of_path = 0; 13209 } 13210 13211 /* Extract the ext phy address for the port */ 13212 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base, 13213 port_of_path, &phy[port]) != 13214 0) { 13215 DP(NETIF_MSG_LINK, "populate_phy failed\n"); 13216 return -EINVAL; 13217 } 13218 /* Disable attentions */ 13219 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + 13220 port_of_path*4, 13221 (NIG_MASK_XGXS0_LINK_STATUS | 13222 NIG_MASK_XGXS0_LINK10G | 13223 NIG_MASK_SERDES0_LINK_STATUS | 13224 NIG_MASK_MI_INT)); 13225 13226 /* Need to take the phy out of low power mode in order 13227 * to write to access its registers 13228 */ 13229 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 13230 MISC_REGISTERS_GPIO_OUTPUT_HIGH, 13231 port); 13232 13233 /* Reset the phy */ 13234 bnx2x_cl45_write(bp, &phy[port], 13235 MDIO_PMA_DEVAD, 13236 MDIO_PMA_REG_CTRL, 13237 1<<15); 13238 } 13239 13240 /* Add delay of 150ms after reset */ 13241 msleep(150); 13242 13243 if (phy[PORT_0].addr & 0x1) { 13244 phy_blk[PORT_0] = &(phy[PORT_1]); 13245 phy_blk[PORT_1] = &(phy[PORT_0]); 13246 } else { 13247 phy_blk[PORT_0] = &(phy[PORT_0]); 13248 phy_blk[PORT_1] = &(phy[PORT_1]); 13249 } 13250 13251 /* PART2 - Download firmware to both phys */ 13252 for (port = PORT_MAX - 1; port >= PORT_0; port--) { 13253 if (CHIP_IS_E1x(bp)) 13254 port_of_path = port; 13255 else 13256 port_of_path = 0; 13257 13258 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n", 13259 phy_blk[port]->addr); 13260 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port], 13261 port_of_path)) 13262 return -EINVAL; 13263 13264 /* Only set bit 10 = 1 (Tx power down) */ 13265 bnx2x_cl45_read(bp, phy_blk[port], 13266 MDIO_PMA_DEVAD, 13267 MDIO_PMA_REG_TX_POWER_DOWN, &val); 13268 13269 /* Phase1 of TX_POWER_DOWN reset */ 13270 bnx2x_cl45_write(bp, phy_blk[port], 13271 MDIO_PMA_DEVAD, 13272 MDIO_PMA_REG_TX_POWER_DOWN, 13273 (val | 1<<10)); 13274 } 13275 13276 /* Toggle Transmitter: Power down and then up with 600ms delay 13277 * between 13278 */ 13279 msleep(600); 13280 13281 /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */ 13282 for (port = PORT_MAX - 1; port >= PORT_0; port--) { 13283 /* Phase2 of POWER_DOWN_RESET */ 13284 /* Release bit 10 (Release Tx power down) */ 13285 bnx2x_cl45_read(bp, phy_blk[port], 13286 MDIO_PMA_DEVAD, 13287 MDIO_PMA_REG_TX_POWER_DOWN, &val); 13288 13289 bnx2x_cl45_write(bp, phy_blk[port], 13290 MDIO_PMA_DEVAD, 13291 MDIO_PMA_REG_TX_POWER_DOWN, (val & (~(1<<10)))); 13292 usleep_range(15000, 30000); 13293 13294 /* Read modify write the SPI-ROM version select register */ 13295 bnx2x_cl45_read(bp, phy_blk[port], 13296 MDIO_PMA_DEVAD, 13297 MDIO_PMA_REG_EDC_FFE_MAIN, &val); 13298 bnx2x_cl45_write(bp, phy_blk[port], 13299 MDIO_PMA_DEVAD, 13300 MDIO_PMA_REG_EDC_FFE_MAIN, (val | (1<<12))); 13301 13302 /* set GPIO2 back to LOW */ 13303 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 13304 MISC_REGISTERS_GPIO_OUTPUT_LOW, port); 13305 } 13306 return 0; 13307 } 13308 static int bnx2x_8726_common_init_phy(struct bnx2x *bp, 13309 u32 shmem_base_path[], 13310 u32 shmem2_base_path[], u8 phy_index, 13311 u32 chip_id) 13312 { 13313 u32 val; 13314 s8 port; 13315 struct bnx2x_phy phy; 13316 /* Use port1 because of the static port-swap */ 13317 /* Enable the module detection interrupt */ 13318 val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN); 13319 val |= ((1<<MISC_REGISTERS_GPIO_3)| 13320 (1<<(MISC_REGISTERS_GPIO_3 + MISC_REGISTERS_GPIO_PORT_SHIFT))); 13321 REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val); 13322 13323 bnx2x_ext_phy_hw_reset(bp, 0); 13324 usleep_range(5000, 10000); 13325 for (port = 0; port < PORT_MAX; port++) { 13326 u32 shmem_base, shmem2_base; 13327 13328 /* In E2, same phy is using for port0 of the two paths */ 13329 if (CHIP_IS_E1x(bp)) { 13330 shmem_base = shmem_base_path[0]; 13331 shmem2_base = shmem2_base_path[0]; 13332 } else { 13333 shmem_base = shmem_base_path[port]; 13334 shmem2_base = shmem2_base_path[port]; 13335 } 13336 /* Extract the ext phy address for the port */ 13337 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base, 13338 port, &phy) != 13339 0) { 13340 DP(NETIF_MSG_LINK, "populate phy failed\n"); 13341 return -EINVAL; 13342 } 13343 13344 /* Reset phy*/ 13345 bnx2x_cl45_write(bp, &phy, 13346 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001); 13347 13348 13349 /* Set fault module detected LED on */ 13350 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0, 13351 MISC_REGISTERS_GPIO_HIGH, 13352 port); 13353 } 13354 13355 return 0; 13356 } 13357 static void bnx2x_get_ext_phy_reset_gpio(struct bnx2x *bp, u32 shmem_base, 13358 u8 *io_gpio, u8 *io_port) 13359 { 13360 13361 u32 phy_gpio_reset = REG_RD(bp, shmem_base + 13362 offsetof(struct shmem_region, 13363 dev_info.port_hw_config[PORT_0].default_cfg)); 13364 switch (phy_gpio_reset) { 13365 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0: 13366 *io_gpio = 0; 13367 *io_port = 0; 13368 break; 13369 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0: 13370 *io_gpio = 1; 13371 *io_port = 0; 13372 break; 13373 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0: 13374 *io_gpio = 2; 13375 *io_port = 0; 13376 break; 13377 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0: 13378 *io_gpio = 3; 13379 *io_port = 0; 13380 break; 13381 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1: 13382 *io_gpio = 0; 13383 *io_port = 1; 13384 break; 13385 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1: 13386 *io_gpio = 1; 13387 *io_port = 1; 13388 break; 13389 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1: 13390 *io_gpio = 2; 13391 *io_port = 1; 13392 break; 13393 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1: 13394 *io_gpio = 3; 13395 *io_port = 1; 13396 break; 13397 default: 13398 /* Don't override the io_gpio and io_port */ 13399 break; 13400 } 13401 } 13402 13403 static int bnx2x_8727_common_init_phy(struct bnx2x *bp, 13404 u32 shmem_base_path[], 13405 u32 shmem2_base_path[], u8 phy_index, 13406 u32 chip_id) 13407 { 13408 s8 port, reset_gpio; 13409 u32 swap_val, swap_override; 13410 struct bnx2x_phy phy[PORT_MAX]; 13411 struct bnx2x_phy *phy_blk[PORT_MAX]; 13412 s8 port_of_path; 13413 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); 13414 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); 13415 13416 reset_gpio = MISC_REGISTERS_GPIO_1; 13417 port = 1; 13418 13419 /* Retrieve the reset gpio/port which control the reset. 13420 * Default is GPIO1, PORT1 13421 */ 13422 bnx2x_get_ext_phy_reset_gpio(bp, shmem_base_path[0], 13423 (u8 *)&reset_gpio, (u8 *)&port); 13424 13425 /* Calculate the port based on port swap */ 13426 port ^= (swap_val && swap_override); 13427 13428 /* Initiate PHY reset*/ 13429 bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_LOW, 13430 port); 13431 usleep_range(1000, 2000); 13432 bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_HIGH, 13433 port); 13434 13435 usleep_range(5000, 10000); 13436 13437 /* PART1 - Reset both phys */ 13438 for (port = PORT_MAX - 1; port >= PORT_0; port--) { 13439 u32 shmem_base, shmem2_base; 13440 13441 /* In E2, same phy is using for port0 of the two paths */ 13442 if (CHIP_IS_E1x(bp)) { 13443 shmem_base = shmem_base_path[0]; 13444 shmem2_base = shmem2_base_path[0]; 13445 port_of_path = port; 13446 } else { 13447 shmem_base = shmem_base_path[port]; 13448 shmem2_base = shmem2_base_path[port]; 13449 port_of_path = 0; 13450 } 13451 13452 /* Extract the ext phy address for the port */ 13453 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base, 13454 port_of_path, &phy[port]) != 13455 0) { 13456 DP(NETIF_MSG_LINK, "populate phy failed\n"); 13457 return -EINVAL; 13458 } 13459 /* disable attentions */ 13460 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + 13461 port_of_path*4, 13462 (NIG_MASK_XGXS0_LINK_STATUS | 13463 NIG_MASK_XGXS0_LINK10G | 13464 NIG_MASK_SERDES0_LINK_STATUS | 13465 NIG_MASK_MI_INT)); 13466 13467 13468 /* Reset the phy */ 13469 bnx2x_cl45_write(bp, &phy[port], 13470 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15); 13471 } 13472 13473 /* Add delay of 150ms after reset */ 13474 msleep(150); 13475 if (phy[PORT_0].addr & 0x1) { 13476 phy_blk[PORT_0] = &(phy[PORT_1]); 13477 phy_blk[PORT_1] = &(phy[PORT_0]); 13478 } else { 13479 phy_blk[PORT_0] = &(phy[PORT_0]); 13480 phy_blk[PORT_1] = &(phy[PORT_1]); 13481 } 13482 /* PART2 - Download firmware to both phys */ 13483 for (port = PORT_MAX - 1; port >= PORT_0; port--) { 13484 if (CHIP_IS_E1x(bp)) 13485 port_of_path = port; 13486 else 13487 port_of_path = 0; 13488 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n", 13489 phy_blk[port]->addr); 13490 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port], 13491 port_of_path)) 13492 return -EINVAL; 13493 /* Disable PHY transmitter output */ 13494 bnx2x_cl45_write(bp, phy_blk[port], 13495 MDIO_PMA_DEVAD, 13496 MDIO_PMA_REG_TX_DISABLE, 1); 13497 13498 } 13499 return 0; 13500 } 13501 13502 static int bnx2x_84833_common_init_phy(struct bnx2x *bp, 13503 u32 shmem_base_path[], 13504 u32 shmem2_base_path[], 13505 u8 phy_index, 13506 u32 chip_id) 13507 { 13508 u8 reset_gpios; 13509 reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path, chip_id); 13510 bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW); 13511 udelay(10); 13512 bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_HIGH); 13513 DP(NETIF_MSG_LINK, "84833 reset pulse on pin values 0x%x\n", 13514 reset_gpios); 13515 return 0; 13516 } 13517 13518 static int bnx2x_ext_phy_common_init(struct bnx2x *bp, u32 shmem_base_path[], 13519 u32 shmem2_base_path[], u8 phy_index, 13520 u32 ext_phy_type, u32 chip_id) 13521 { 13522 int rc = 0; 13523 13524 switch (ext_phy_type) { 13525 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073: 13526 rc = bnx2x_8073_common_init_phy(bp, shmem_base_path, 13527 shmem2_base_path, 13528 phy_index, chip_id); 13529 break; 13530 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722: 13531 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: 13532 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC: 13533 rc = bnx2x_8727_common_init_phy(bp, shmem_base_path, 13534 shmem2_base_path, 13535 phy_index, chip_id); 13536 break; 13537 13538 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: 13539 /* GPIO1 affects both ports, so there's need to pull 13540 * it for single port alone 13541 */ 13542 rc = bnx2x_8726_common_init_phy(bp, shmem_base_path, 13543 shmem2_base_path, 13544 phy_index, chip_id); 13545 break; 13546 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833: 13547 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834: 13548 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858: 13549 /* GPIO3's are linked, and so both need to be toggled 13550 * to obtain required 2us pulse. 13551 */ 13552 rc = bnx2x_84833_common_init_phy(bp, shmem_base_path, 13553 shmem2_base_path, 13554 phy_index, chip_id); 13555 break; 13556 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE: 13557 rc = -EINVAL; 13558 break; 13559 default: 13560 DP(NETIF_MSG_LINK, 13561 "ext_phy 0x%x common init not required\n", 13562 ext_phy_type); 13563 break; 13564 } 13565 13566 if (rc) 13567 netdev_err(bp->dev, "Warning: PHY was not initialized," 13568 " Port %d\n", 13569 0); 13570 return rc; 13571 } 13572 13573 int bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base_path[], 13574 u32 shmem2_base_path[], u32 chip_id) 13575 { 13576 int rc = 0; 13577 u32 phy_ver, val; 13578 u8 phy_index = 0; 13579 u32 ext_phy_type, ext_phy_config; 13580 13581 bnx2x_set_mdio_clk(bp, chip_id, GRCBASE_EMAC0); 13582 bnx2x_set_mdio_clk(bp, chip_id, GRCBASE_EMAC1); 13583 DP(NETIF_MSG_LINK, "Begin common phy init\n"); 13584 if (CHIP_IS_E3(bp)) { 13585 /* Enable EPIO */ 13586 val = REG_RD(bp, MISC_REG_GEN_PURP_HWG); 13587 REG_WR(bp, MISC_REG_GEN_PURP_HWG, val | 1); 13588 } 13589 /* Check if common init was already done */ 13590 phy_ver = REG_RD(bp, shmem_base_path[0] + 13591 offsetof(struct shmem_region, 13592 port_mb[PORT_0].ext_phy_fw_version)); 13593 if (phy_ver) { 13594 DP(NETIF_MSG_LINK, "Not doing common init; phy ver is 0x%x\n", 13595 phy_ver); 13596 return 0; 13597 } 13598 13599 /* Read the ext_phy_type for arbitrary port(0) */ 13600 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS; 13601 phy_index++) { 13602 ext_phy_config = bnx2x_get_ext_phy_config(bp, 13603 shmem_base_path[0], 13604 phy_index, 0); 13605 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config); 13606 rc |= bnx2x_ext_phy_common_init(bp, shmem_base_path, 13607 shmem2_base_path, 13608 phy_index, ext_phy_type, 13609 chip_id); 13610 } 13611 return rc; 13612 } 13613 13614 static void bnx2x_check_over_curr(struct link_params *params, 13615 struct link_vars *vars) 13616 { 13617 struct bnx2x *bp = params->bp; 13618 u32 cfg_pin; 13619 u8 port = params->port; 13620 u32 pin_val; 13621 13622 cfg_pin = (REG_RD(bp, params->shmem_base + 13623 offsetof(struct shmem_region, 13624 dev_info.port_hw_config[port].e3_cmn_pin_cfg1)) & 13625 PORT_HW_CFG_E3_OVER_CURRENT_MASK) >> 13626 PORT_HW_CFG_E3_OVER_CURRENT_SHIFT; 13627 13628 /* Ignore check if no external input PIN available */ 13629 if (bnx2x_get_cfg_pin(bp, cfg_pin, &pin_val) != 0) 13630 return; 13631 13632 if (!pin_val) { 13633 if ((vars->phy_flags & PHY_OVER_CURRENT_FLAG) == 0) { 13634 netdev_err(bp->dev, "Error: Power fault on Port %d has" 13635 " been detected and the power to " 13636 "that SFP+ module has been removed" 13637 " to prevent failure of the card." 13638 " Please remove the SFP+ module and" 13639 " restart the system to clear this" 13640 " error.\n", 13641 params->port); 13642 vars->phy_flags |= PHY_OVER_CURRENT_FLAG; 13643 bnx2x_warpcore_power_module(params, 0); 13644 } 13645 } else 13646 vars->phy_flags &= ~PHY_OVER_CURRENT_FLAG; 13647 } 13648 13649 /* Returns 0 if no change occurred since last check; 1 otherwise. */ 13650 static u8 bnx2x_analyze_link_error(struct link_params *params, 13651 struct link_vars *vars, u32 status, 13652 u32 phy_flag, u32 link_flag, u8 notify) 13653 { 13654 struct bnx2x *bp = params->bp; 13655 /* Compare new value with previous value */ 13656 u8 led_mode; 13657 u32 old_status = (vars->phy_flags & phy_flag) ? 1 : 0; 13658 13659 if ((status ^ old_status) == 0) 13660 return 0; 13661 13662 /* If values differ */ 13663 switch (phy_flag) { 13664 case PHY_HALF_OPEN_CONN_FLAG: 13665 DP(NETIF_MSG_LINK, "Analyze Remote Fault\n"); 13666 break; 13667 case PHY_SFP_TX_FAULT_FLAG: 13668 DP(NETIF_MSG_LINK, "Analyze TX Fault\n"); 13669 break; 13670 default: 13671 DP(NETIF_MSG_LINK, "Analyze UNKNOWN\n"); 13672 } 13673 DP(NETIF_MSG_LINK, "Link changed:[%x %x]->%x\n", vars->link_up, 13674 old_status, status); 13675 13676 /* Do not touch the link in case physical link down */ 13677 if ((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0) 13678 return 1; 13679 13680 /* a. Update shmem->link_status accordingly 13681 * b. Update link_vars->link_up 13682 */ 13683 if (status) { 13684 vars->link_status &= ~LINK_STATUS_LINK_UP; 13685 vars->link_status |= link_flag; 13686 vars->link_up = 0; 13687 vars->phy_flags |= phy_flag; 13688 13689 /* activate nig drain */ 13690 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1); 13691 /* Set LED mode to off since the PHY doesn't know about these 13692 * errors 13693 */ 13694 led_mode = LED_MODE_OFF; 13695 } else { 13696 vars->link_status |= LINK_STATUS_LINK_UP; 13697 vars->link_status &= ~link_flag; 13698 vars->link_up = 1; 13699 vars->phy_flags &= ~phy_flag; 13700 led_mode = LED_MODE_OPER; 13701 13702 /* Clear nig drain */ 13703 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); 13704 } 13705 bnx2x_sync_link(params, vars); 13706 /* Update the LED according to the link state */ 13707 bnx2x_set_led(params, vars, led_mode, SPEED_10000); 13708 13709 /* Update link status in the shared memory */ 13710 bnx2x_update_mng(params, vars->link_status); 13711 13712 /* C. Trigger General Attention */ 13713 vars->periodic_flags |= PERIODIC_FLAGS_LINK_EVENT; 13714 if (notify) 13715 bnx2x_notify_link_changed(bp); 13716 13717 return 1; 13718 } 13719 13720 /****************************************************************************** 13721 * Description: 13722 * This function checks for half opened connection change indication. 13723 * When such change occurs, it calls the bnx2x_analyze_link_error 13724 * to check if Remote Fault is set or cleared. Reception of remote fault 13725 * status message in the MAC indicates that the peer's MAC has detected 13726 * a fault, for example, due to break in the TX side of fiber. 13727 * 13728 ******************************************************************************/ 13729 static int bnx2x_check_half_open_conn(struct link_params *params, 13730 struct link_vars *vars, 13731 u8 notify) 13732 { 13733 struct bnx2x *bp = params->bp; 13734 u32 lss_status = 0; 13735 u32 mac_base; 13736 /* In case link status is physically up @ 10G do */ 13737 if (((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0) || 13738 (REG_RD(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4))) 13739 return 0; 13740 13741 if (CHIP_IS_E3(bp) && 13742 (REG_RD(bp, MISC_REG_RESET_REG_2) & 13743 (MISC_REGISTERS_RESET_REG_2_XMAC))) { 13744 /* Check E3 XMAC */ 13745 /* Note that link speed cannot be queried here, since it may be 13746 * zero while link is down. In case UMAC is active, LSS will 13747 * simply not be set 13748 */ 13749 mac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; 13750 13751 /* Clear stick bits (Requires rising edge) */ 13752 REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0); 13753 REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 13754 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS | 13755 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS); 13756 if (REG_RD(bp, mac_base + XMAC_REG_RX_LSS_STATUS)) 13757 lss_status = 1; 13758 13759 bnx2x_analyze_link_error(params, vars, lss_status, 13760 PHY_HALF_OPEN_CONN_FLAG, 13761 LINK_STATUS_NONE, notify); 13762 } else if (REG_RD(bp, MISC_REG_RESET_REG_2) & 13763 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port)) { 13764 /* Check E1X / E2 BMAC */ 13765 u32 lss_status_reg; 13766 u32 wb_data[2]; 13767 mac_base = params->port ? NIG_REG_INGRESS_BMAC1_MEM : 13768 NIG_REG_INGRESS_BMAC0_MEM; 13769 /* Read BIGMAC_REGISTER_RX_LSS_STATUS */ 13770 if (CHIP_IS_E2(bp)) 13771 lss_status_reg = BIGMAC2_REGISTER_RX_LSS_STAT; 13772 else 13773 lss_status_reg = BIGMAC_REGISTER_RX_LSS_STATUS; 13774 13775 REG_RD_DMAE(bp, mac_base + lss_status_reg, wb_data, 2); 13776 lss_status = (wb_data[0] > 0); 13777 13778 bnx2x_analyze_link_error(params, vars, lss_status, 13779 PHY_HALF_OPEN_CONN_FLAG, 13780 LINK_STATUS_NONE, notify); 13781 } 13782 return 0; 13783 } 13784 static void bnx2x_sfp_tx_fault_detection(struct bnx2x_phy *phy, 13785 struct link_params *params, 13786 struct link_vars *vars) 13787 { 13788 struct bnx2x *bp = params->bp; 13789 u32 cfg_pin, value = 0; 13790 u8 led_change, port = params->port; 13791 13792 /* Get The SFP+ TX_Fault controlling pin ([eg]pio) */ 13793 cfg_pin = (REG_RD(bp, params->shmem_base + offsetof(struct shmem_region, 13794 dev_info.port_hw_config[port].e3_cmn_pin_cfg)) & 13795 PORT_HW_CFG_E3_TX_FAULT_MASK) >> 13796 PORT_HW_CFG_E3_TX_FAULT_SHIFT; 13797 13798 if (bnx2x_get_cfg_pin(bp, cfg_pin, &value)) { 13799 DP(NETIF_MSG_LINK, "Failed to read pin 0x%02x\n", cfg_pin); 13800 return; 13801 } 13802 13803 led_change = bnx2x_analyze_link_error(params, vars, value, 13804 PHY_SFP_TX_FAULT_FLAG, 13805 LINK_STATUS_SFP_TX_FAULT, 1); 13806 13807 if (led_change) { 13808 /* Change TX_Fault led, set link status for further syncs */ 13809 u8 led_mode; 13810 13811 if (vars->phy_flags & PHY_SFP_TX_FAULT_FLAG) { 13812 led_mode = MISC_REGISTERS_GPIO_HIGH; 13813 vars->link_status |= LINK_STATUS_SFP_TX_FAULT; 13814 } else { 13815 led_mode = MISC_REGISTERS_GPIO_LOW; 13816 vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT; 13817 } 13818 13819 /* If module is unapproved, led should be on regardless */ 13820 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED)) { 13821 DP(NETIF_MSG_LINK, "Change TX_Fault LED: ->%x\n", 13822 led_mode); 13823 bnx2x_set_e3_module_fault_led(params, led_mode); 13824 } 13825 } 13826 } 13827 static void bnx2x_kr2_recovery(struct link_params *params, 13828 struct link_vars *vars, 13829 struct bnx2x_phy *phy) 13830 { 13831 struct bnx2x *bp = params->bp; 13832 DP(NETIF_MSG_LINK, "KR2 recovery\n"); 13833 bnx2x_warpcore_enable_AN_KR2(phy, params, vars); 13834 bnx2x_warpcore_restart_AN_KR(phy, params); 13835 } 13836 13837 static void bnx2x_check_kr2_wa(struct link_params *params, 13838 struct link_vars *vars, 13839 struct bnx2x_phy *phy) 13840 { 13841 struct bnx2x *bp = params->bp; 13842 u16 base_page, next_page, not_kr2_device, lane; 13843 int sigdet; 13844 13845 /* Once KR2 was disabled, wait 5 seconds before checking KR2 recovery 13846 * Since some switches tend to reinit the AN process and clear the 13847 * advertised BP/NP after ~2 seconds causing the KR2 to be disabled 13848 * and recovered many times 13849 */ 13850 if (vars->check_kr2_recovery_cnt > 0) { 13851 vars->check_kr2_recovery_cnt--; 13852 return; 13853 } 13854 13855 sigdet = bnx2x_warpcore_get_sigdet(phy, params); 13856 if (!sigdet) { 13857 if (!(params->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) { 13858 bnx2x_kr2_recovery(params, vars, phy); 13859 DP(NETIF_MSG_LINK, "No sigdet\n"); 13860 } 13861 return; 13862 } 13863 13864 lane = bnx2x_get_warpcore_lane(phy, params); 13865 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, 13866 MDIO_AER_BLOCK_AER_REG, lane); 13867 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, 13868 MDIO_AN_REG_LP_AUTO_NEG, &base_page); 13869 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, 13870 MDIO_AN_REG_LP_AUTO_NEG2, &next_page); 13871 bnx2x_set_aer_mmd(params, phy); 13872 13873 /* CL73 has not begun yet */ 13874 if (base_page == 0) { 13875 if (!(params->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) { 13876 bnx2x_kr2_recovery(params, vars, phy); 13877 DP(NETIF_MSG_LINK, "No BP\n"); 13878 } 13879 return; 13880 } 13881 13882 /* In case NP bit is not set in the BasePage, or it is set, 13883 * but only KX is advertised, declare this link partner as non-KR2 13884 * device. 13885 */ 13886 not_kr2_device = (((base_page & 0x8000) == 0) || 13887 (((base_page & 0x8000) && 13888 ((next_page & 0xe0) == 0x20)))); 13889 13890 /* In case KR2 is already disabled, check if we need to re-enable it */ 13891 if (!(params->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) { 13892 if (!not_kr2_device) { 13893 DP(NETIF_MSG_LINK, "BP=0x%x, NP=0x%x\n", base_page, 13894 next_page); 13895 bnx2x_kr2_recovery(params, vars, phy); 13896 } 13897 return; 13898 } 13899 /* KR2 is enabled, but not KR2 device */ 13900 if (not_kr2_device) { 13901 /* Disable KR2 on both lanes */ 13902 DP(NETIF_MSG_LINK, "BP=0x%x, NP=0x%x\n", base_page, next_page); 13903 bnx2x_disable_kr2(params, vars, phy); 13904 /* Restart AN on leading lane */ 13905 bnx2x_warpcore_restart_AN_KR(phy, params); 13906 return; 13907 } 13908 } 13909 13910 void bnx2x_period_func(struct link_params *params, struct link_vars *vars) 13911 { 13912 u16 phy_idx; 13913 struct bnx2x *bp = params->bp; 13914 for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) { 13915 if (params->phy[phy_idx].flags & FLAGS_TX_ERROR_CHECK) { 13916 bnx2x_set_aer_mmd(params, ¶ms->phy[phy_idx]); 13917 if (bnx2x_check_half_open_conn(params, vars, 1) != 13918 0) 13919 DP(NETIF_MSG_LINK, "Fault detection failed\n"); 13920 break; 13921 } 13922 } 13923 13924 if (CHIP_IS_E3(bp)) { 13925 struct bnx2x_phy *phy = ¶ms->phy[INT_PHY]; 13926 bnx2x_set_aer_mmd(params, phy); 13927 if (((phy->req_line_speed == SPEED_AUTO_NEG) && 13928 (phy->speed_cap_mask & 13929 PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) || 13930 (phy->req_line_speed == SPEED_20000)) 13931 bnx2x_check_kr2_wa(params, vars, phy); 13932 bnx2x_check_over_curr(params, vars); 13933 if (vars->rx_tx_asic_rst) 13934 bnx2x_warpcore_config_runtime(phy, params, vars); 13935 13936 if ((REG_RD(bp, params->shmem_base + 13937 offsetof(struct shmem_region, dev_info. 13938 port_hw_config[params->port].default_cfg)) 13939 & PORT_HW_CFG_NET_SERDES_IF_MASK) == 13940 PORT_HW_CFG_NET_SERDES_IF_SFI) { 13941 if (bnx2x_is_sfp_module_plugged(phy, params)) { 13942 bnx2x_sfp_tx_fault_detection(phy, params, vars); 13943 } else if (vars->link_status & 13944 LINK_STATUS_SFP_TX_FAULT) { 13945 /* Clean trail, interrupt corrects the leds */ 13946 vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT; 13947 vars->phy_flags &= ~PHY_SFP_TX_FAULT_FLAG; 13948 /* Update link status in the shared memory */ 13949 bnx2x_update_mng(params, vars->link_status); 13950 } 13951 } 13952 } 13953 } 13954 13955 u8 bnx2x_fan_failure_det_req(struct bnx2x *bp, 13956 u32 shmem_base, 13957 u32 shmem2_base, 13958 u8 port) 13959 { 13960 u8 phy_index, fan_failure_det_req = 0; 13961 struct bnx2x_phy phy; 13962 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS; 13963 phy_index++) { 13964 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base, 13965 port, &phy) 13966 != 0) { 13967 DP(NETIF_MSG_LINK, "populate phy failed\n"); 13968 return 0; 13969 } 13970 fan_failure_det_req |= (phy.flags & 13971 FLAGS_FAN_FAILURE_DET_REQ); 13972 } 13973 return fan_failure_det_req; 13974 } 13975 13976 void bnx2x_hw_reset_phy(struct link_params *params) 13977 { 13978 u8 phy_index; 13979 struct bnx2x *bp = params->bp; 13980 bnx2x_update_mng(params, 0); 13981 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4, 13982 (NIG_MASK_XGXS0_LINK_STATUS | 13983 NIG_MASK_XGXS0_LINK10G | 13984 NIG_MASK_SERDES0_LINK_STATUS | 13985 NIG_MASK_MI_INT)); 13986 13987 for (phy_index = INT_PHY; phy_index < MAX_PHYS; 13988 phy_index++) { 13989 if (params->phy[phy_index].hw_reset) { 13990 params->phy[phy_index].hw_reset( 13991 ¶ms->phy[phy_index], 13992 params); 13993 params->phy[phy_index] = phy_null; 13994 } 13995 } 13996 } 13997 13998 void bnx2x_init_mod_abs_int(struct bnx2x *bp, struct link_vars *vars, 13999 u32 chip_id, u32 shmem_base, u32 shmem2_base, 14000 u8 port) 14001 { 14002 u8 gpio_num = 0xff, gpio_port = 0xff, phy_index; 14003 u32 val; 14004 u32 offset, aeu_mask, swap_val, swap_override, sync_offset; 14005 if (CHIP_IS_E3(bp)) { 14006 if (bnx2x_get_mod_abs_int_cfg(bp, chip_id, 14007 shmem_base, 14008 port, 14009 &gpio_num, 14010 &gpio_port) != 0) 14011 return; 14012 } else { 14013 struct bnx2x_phy phy; 14014 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS; 14015 phy_index++) { 14016 if (bnx2x_populate_phy(bp, phy_index, shmem_base, 14017 shmem2_base, port, &phy) 14018 != 0) { 14019 DP(NETIF_MSG_LINK, "populate phy failed\n"); 14020 return; 14021 } 14022 if (phy.type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) { 14023 gpio_num = MISC_REGISTERS_GPIO_3; 14024 gpio_port = port; 14025 break; 14026 } 14027 } 14028 } 14029 14030 if (gpio_num == 0xff) 14031 return; 14032 14033 /* Set GPIO3 to trigger SFP+ module insertion/removal */ 14034 bnx2x_set_gpio(bp, gpio_num, MISC_REGISTERS_GPIO_INPUT_HI_Z, gpio_port); 14035 14036 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); 14037 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); 14038 gpio_port ^= (swap_val && swap_override); 14039 14040 vars->aeu_int_mask = AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 << 14041 (gpio_num + (gpio_port << 2)); 14042 14043 sync_offset = shmem_base + 14044 offsetof(struct shmem_region, 14045 dev_info.port_hw_config[port].aeu_int_mask); 14046 REG_WR(bp, sync_offset, vars->aeu_int_mask); 14047 14048 DP(NETIF_MSG_LINK, "Setting MOD_ABS (GPIO%d_P%d) AEU to 0x%x\n", 14049 gpio_num, gpio_port, vars->aeu_int_mask); 14050 14051 if (port == 0) 14052 offset = MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0; 14053 else 14054 offset = MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0; 14055 14056 /* Open appropriate AEU for interrupts */ 14057 aeu_mask = REG_RD(bp, offset); 14058 aeu_mask |= vars->aeu_int_mask; 14059 REG_WR(bp, offset, aeu_mask); 14060 14061 /* Enable the GPIO to trigger interrupt */ 14062 val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN); 14063 val |= 1 << (gpio_num + (gpio_port << 2)); 14064 REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val); 14065 } 14066