1 /* Copyright 2008-2013 Broadcom Corporation 2 * 3 * Unless you and Broadcom execute a separate written software license 4 * agreement governing use of this software, this software is licensed to you 5 * under the terms of the GNU General Public License version 2, available 6 * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL"). 7 * 8 * Notwithstanding the above, under no circumstances may you combine this 9 * software in any way with any other Broadcom software provided under a 10 * license other than the GPL, without Broadcom's express prior written 11 * consent. 12 * 13 * Written by Yaniv Rosner 14 * 15 */ 16 17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 18 19 #include <linux/kernel.h> 20 #include <linux/errno.h> 21 #include <linux/pci.h> 22 #include <linux/netdevice.h> 23 #include <linux/delay.h> 24 #include <linux/ethtool.h> 25 #include <linux/mutex.h> 26 27 #include "bnx2x.h" 28 #include "bnx2x_cmn.h" 29 30 typedef int (*read_sfp_module_eeprom_func_p)(struct bnx2x_phy *phy, 31 struct link_params *params, 32 u8 dev_addr, u16 addr, u8 byte_cnt, 33 u8 *o_buf, u8); 34 /********************************************************/ 35 #define ETH_HLEN 14 36 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */ 37 #define ETH_OVREHEAD (ETH_HLEN + 8 + 8) 38 #define ETH_MIN_PACKET_SIZE 60 39 #define ETH_MAX_PACKET_SIZE 1500 40 #define ETH_MAX_JUMBO_PACKET_SIZE 9600 41 #define MDIO_ACCESS_TIMEOUT 1000 42 #define WC_LANE_MAX 4 43 #define I2C_SWITCH_WIDTH 2 44 #define I2C_BSC0 0 45 #define I2C_BSC1 1 46 #define I2C_WA_RETRY_CNT 3 47 #define I2C_WA_PWR_ITER (I2C_WA_RETRY_CNT - 1) 48 #define MCPR_IMC_COMMAND_READ_OP 1 49 #define MCPR_IMC_COMMAND_WRITE_OP 2 50 51 /* LED Blink rate that will achieve ~15.9Hz */ 52 #define LED_BLINK_RATE_VAL_E3 354 53 #define LED_BLINK_RATE_VAL_E1X_E2 480 54 /***********************************************************/ 55 /* Shortcut definitions */ 56 /***********************************************************/ 57 58 #define NIG_LATCH_BC_ENABLE_MI_INT 0 59 60 #define NIG_STATUS_EMAC0_MI_INT \ 61 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT 62 #define NIG_STATUS_XGXS0_LINK10G \ 63 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G 64 #define NIG_STATUS_XGXS0_LINK_STATUS \ 65 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS 66 #define NIG_STATUS_XGXS0_LINK_STATUS_SIZE \ 67 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE 68 #define NIG_STATUS_SERDES0_LINK_STATUS \ 69 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS 70 #define NIG_MASK_MI_INT \ 71 NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT 72 #define NIG_MASK_XGXS0_LINK10G \ 73 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G 74 #define NIG_MASK_XGXS0_LINK_STATUS \ 75 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS 76 #define NIG_MASK_SERDES0_LINK_STATUS \ 77 NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS 78 79 #define MDIO_AN_CL73_OR_37_COMPLETE \ 80 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \ 81 MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE) 82 83 #define XGXS_RESET_BITS \ 84 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW | \ 85 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ | \ 86 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN | \ 87 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \ 88 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB) 89 90 #define SERDES_RESET_BITS \ 91 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \ 92 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ | \ 93 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN | \ 94 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD) 95 96 #define AUTONEG_CL37 SHARED_HW_CFG_AN_ENABLE_CL37 97 #define AUTONEG_CL73 SHARED_HW_CFG_AN_ENABLE_CL73 98 #define AUTONEG_BAM SHARED_HW_CFG_AN_ENABLE_BAM 99 #define AUTONEG_PARALLEL \ 100 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION 101 #define AUTONEG_SGMII_FIBER_AUTODET \ 102 SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT 103 #define AUTONEG_REMOTE_PHY SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY 104 105 #define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \ 106 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE 107 #define GP_STATUS_PAUSE_RSOLUTION_RXSIDE \ 108 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE 109 #define GP_STATUS_SPEED_MASK \ 110 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK 111 #define GP_STATUS_10M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M 112 #define GP_STATUS_100M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M 113 #define GP_STATUS_1G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G 114 #define GP_STATUS_2_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G 115 #define GP_STATUS_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G 116 #define GP_STATUS_6G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G 117 #define GP_STATUS_10G_HIG \ 118 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG 119 #define GP_STATUS_10G_CX4 \ 120 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4 121 #define GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX 122 #define GP_STATUS_10G_KX4 \ 123 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4 124 #define GP_STATUS_10G_KR MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR 125 #define GP_STATUS_10G_XFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI 126 #define GP_STATUS_20G_DXGXS MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS 127 #define GP_STATUS_10G_SFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI 128 #define GP_STATUS_20G_KR2 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_KR2 129 #define LINK_10THD LINK_STATUS_SPEED_AND_DUPLEX_10THD 130 #define LINK_10TFD LINK_STATUS_SPEED_AND_DUPLEX_10TFD 131 #define LINK_100TXHD LINK_STATUS_SPEED_AND_DUPLEX_100TXHD 132 #define LINK_100T4 LINK_STATUS_SPEED_AND_DUPLEX_100T4 133 #define LINK_100TXFD LINK_STATUS_SPEED_AND_DUPLEX_100TXFD 134 #define LINK_1000THD LINK_STATUS_SPEED_AND_DUPLEX_1000THD 135 #define LINK_1000TFD LINK_STATUS_SPEED_AND_DUPLEX_1000TFD 136 #define LINK_1000XFD LINK_STATUS_SPEED_AND_DUPLEX_1000XFD 137 #define LINK_2500THD LINK_STATUS_SPEED_AND_DUPLEX_2500THD 138 #define LINK_2500TFD LINK_STATUS_SPEED_AND_DUPLEX_2500TFD 139 #define LINK_2500XFD LINK_STATUS_SPEED_AND_DUPLEX_2500XFD 140 #define LINK_10GTFD LINK_STATUS_SPEED_AND_DUPLEX_10GTFD 141 #define LINK_10GXFD LINK_STATUS_SPEED_AND_DUPLEX_10GXFD 142 #define LINK_20GTFD LINK_STATUS_SPEED_AND_DUPLEX_20GTFD 143 #define LINK_20GXFD LINK_STATUS_SPEED_AND_DUPLEX_20GXFD 144 145 #define LINK_UPDATE_MASK \ 146 (LINK_STATUS_SPEED_AND_DUPLEX_MASK | \ 147 LINK_STATUS_LINK_UP | \ 148 LINK_STATUS_PHYSICAL_LINK_FLAG | \ 149 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE | \ 150 LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK | \ 151 LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK | \ 152 LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK | \ 153 LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE | \ 154 LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE) 155 156 #define SFP_EEPROM_CON_TYPE_ADDR 0x2 157 #define SFP_EEPROM_CON_TYPE_VAL_LC 0x7 158 #define SFP_EEPROM_CON_TYPE_VAL_COPPER 0x21 159 #define SFP_EEPROM_CON_TYPE_VAL_RJ45 0x22 160 161 162 #define SFP_EEPROM_COMP_CODE_ADDR 0x3 163 #define SFP_EEPROM_COMP_CODE_SR_MASK (1<<4) 164 #define SFP_EEPROM_COMP_CODE_LR_MASK (1<<5) 165 #define SFP_EEPROM_COMP_CODE_LRM_MASK (1<<6) 166 167 #define SFP_EEPROM_FC_TX_TECH_ADDR 0x8 168 #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4 169 #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE 0x8 170 171 #define SFP_EEPROM_OPTIONS_ADDR 0x40 172 #define SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1 173 #define SFP_EEPROM_OPTIONS_SIZE 2 174 175 #define EDC_MODE_LINEAR 0x0022 176 #define EDC_MODE_LIMITING 0x0044 177 #define EDC_MODE_PASSIVE_DAC 0x0055 178 179 /* ETS defines*/ 180 #define DCBX_INVALID_COS (0xFF) 181 182 #define ETS_BW_LIMIT_CREDIT_UPPER_BOUND (0x5000) 183 #define ETS_BW_LIMIT_CREDIT_WEIGHT (0x5000) 184 #define ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS (1360) 185 #define ETS_E3B0_NIG_MIN_W_VAL_20GBPS (2720) 186 #define ETS_E3B0_PBF_MIN_W_VAL (10000) 187 188 #define MAX_PACKET_SIZE (9700) 189 #define MAX_KR_LINK_RETRY 4 190 191 /**********************************************************/ 192 /* INTERFACE */ 193 /**********************************************************/ 194 195 #define CL22_WR_OVER_CL45(_bp, _phy, _bank, _addr, _val) \ 196 bnx2x_cl45_write(_bp, _phy, \ 197 (_phy)->def_md_devad, \ 198 (_bank + (_addr & 0xf)), \ 199 _val) 200 201 #define CL22_RD_OVER_CL45(_bp, _phy, _bank, _addr, _val) \ 202 bnx2x_cl45_read(_bp, _phy, \ 203 (_phy)->def_md_devad, \ 204 (_bank + (_addr & 0xf)), \ 205 _val) 206 207 static u32 bnx2x_bits_en(struct bnx2x *bp, u32 reg, u32 bits) 208 { 209 u32 val = REG_RD(bp, reg); 210 211 val |= bits; 212 REG_WR(bp, reg, val); 213 return val; 214 } 215 216 static u32 bnx2x_bits_dis(struct bnx2x *bp, u32 reg, u32 bits) 217 { 218 u32 val = REG_RD(bp, reg); 219 220 val &= ~bits; 221 REG_WR(bp, reg, val); 222 return val; 223 } 224 225 /* 226 * bnx2x_check_lfa - This function checks if link reinitialization is required, 227 * or link flap can be avoided. 228 * 229 * @params: link parameters 230 * Returns 0 if Link Flap Avoidance conditions are met otherwise, the failed 231 * condition code. 232 */ 233 static int bnx2x_check_lfa(struct link_params *params) 234 { 235 u32 link_status, cfg_idx, lfa_mask, cfg_size; 236 u32 cur_speed_cap_mask, cur_req_fc_auto_adv, additional_config; 237 u32 saved_val, req_val, eee_status; 238 struct bnx2x *bp = params->bp; 239 240 additional_config = 241 REG_RD(bp, params->lfa_base + 242 offsetof(struct shmem_lfa, additional_config)); 243 244 /* NOTE: must be first condition checked - 245 * to verify DCC bit is cleared in any case! 246 */ 247 if (additional_config & NO_LFA_DUE_TO_DCC_MASK) { 248 DP(NETIF_MSG_LINK, "No LFA due to DCC flap after clp exit\n"); 249 REG_WR(bp, params->lfa_base + 250 offsetof(struct shmem_lfa, additional_config), 251 additional_config & ~NO_LFA_DUE_TO_DCC_MASK); 252 return LFA_DCC_LFA_DISABLED; 253 } 254 255 /* Verify that link is up */ 256 link_status = REG_RD(bp, params->shmem_base + 257 offsetof(struct shmem_region, 258 port_mb[params->port].link_status)); 259 if (!(link_status & LINK_STATUS_LINK_UP)) 260 return LFA_LINK_DOWN; 261 262 /* if loaded after BOOT from SAN, don't flap the link in any case and 263 * rely on link set by preboot driver 264 */ 265 if (params->feature_config_flags & FEATURE_CONFIG_BOOT_FROM_SAN) 266 return 0; 267 268 /* Verify that loopback mode is not set */ 269 if (params->loopback_mode) 270 return LFA_LOOPBACK_ENABLED; 271 272 /* Verify that MFW supports LFA */ 273 if (!params->lfa_base) 274 return LFA_MFW_IS_TOO_OLD; 275 276 if (params->num_phys == 3) { 277 cfg_size = 2; 278 lfa_mask = 0xffffffff; 279 } else { 280 cfg_size = 1; 281 lfa_mask = 0xffff; 282 } 283 284 /* Compare Duplex */ 285 saved_val = REG_RD(bp, params->lfa_base + 286 offsetof(struct shmem_lfa, req_duplex)); 287 req_val = params->req_duplex[0] | (params->req_duplex[1] << 16); 288 if ((saved_val & lfa_mask) != (req_val & lfa_mask)) { 289 DP(NETIF_MSG_LINK, "Duplex mismatch %x vs. %x\n", 290 (saved_val & lfa_mask), (req_val & lfa_mask)); 291 return LFA_DUPLEX_MISMATCH; 292 } 293 /* Compare Flow Control */ 294 saved_val = REG_RD(bp, params->lfa_base + 295 offsetof(struct shmem_lfa, req_flow_ctrl)); 296 req_val = params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16); 297 if ((saved_val & lfa_mask) != (req_val & lfa_mask)) { 298 DP(NETIF_MSG_LINK, "Flow control mismatch %x vs. %x\n", 299 (saved_val & lfa_mask), (req_val & lfa_mask)); 300 return LFA_FLOW_CTRL_MISMATCH; 301 } 302 /* Compare Link Speed */ 303 saved_val = REG_RD(bp, params->lfa_base + 304 offsetof(struct shmem_lfa, req_line_speed)); 305 req_val = params->req_line_speed[0] | (params->req_line_speed[1] << 16); 306 if ((saved_val & lfa_mask) != (req_val & lfa_mask)) { 307 DP(NETIF_MSG_LINK, "Link speed mismatch %x vs. %x\n", 308 (saved_val & lfa_mask), (req_val & lfa_mask)); 309 return LFA_LINK_SPEED_MISMATCH; 310 } 311 312 for (cfg_idx = 0; cfg_idx < cfg_size; cfg_idx++) { 313 cur_speed_cap_mask = REG_RD(bp, params->lfa_base + 314 offsetof(struct shmem_lfa, 315 speed_cap_mask[cfg_idx])); 316 317 if (cur_speed_cap_mask != params->speed_cap_mask[cfg_idx]) { 318 DP(NETIF_MSG_LINK, "Speed Cap mismatch %x vs. %x\n", 319 cur_speed_cap_mask, 320 params->speed_cap_mask[cfg_idx]); 321 return LFA_SPEED_CAP_MISMATCH; 322 } 323 } 324 325 cur_req_fc_auto_adv = 326 REG_RD(bp, params->lfa_base + 327 offsetof(struct shmem_lfa, additional_config)) & 328 REQ_FC_AUTO_ADV_MASK; 329 330 if ((u16)cur_req_fc_auto_adv != params->req_fc_auto_adv) { 331 DP(NETIF_MSG_LINK, "Flow Ctrl AN mismatch %x vs. %x\n", 332 cur_req_fc_auto_adv, params->req_fc_auto_adv); 333 return LFA_FLOW_CTRL_MISMATCH; 334 } 335 336 eee_status = REG_RD(bp, params->shmem2_base + 337 offsetof(struct shmem2_region, 338 eee_status[params->port])); 339 340 if (((eee_status & SHMEM_EEE_LPI_REQUESTED_BIT) ^ 341 (params->eee_mode & EEE_MODE_ENABLE_LPI)) || 342 ((eee_status & SHMEM_EEE_REQUESTED_BIT) ^ 343 (params->eee_mode & EEE_MODE_ADV_LPI))) { 344 DP(NETIF_MSG_LINK, "EEE mismatch %x vs. %x\n", params->eee_mode, 345 eee_status); 346 return LFA_EEE_MISMATCH; 347 } 348 349 /* LFA conditions are met */ 350 return 0; 351 } 352 /******************************************************************/ 353 /* EPIO/GPIO section */ 354 /******************************************************************/ 355 static void bnx2x_get_epio(struct bnx2x *bp, u32 epio_pin, u32 *en) 356 { 357 u32 epio_mask, gp_oenable; 358 *en = 0; 359 /* Sanity check */ 360 if (epio_pin > 31) { 361 DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to get\n", epio_pin); 362 return; 363 } 364 365 epio_mask = 1 << epio_pin; 366 /* Set this EPIO to output */ 367 gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE); 368 REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable & ~epio_mask); 369 370 *en = (REG_RD(bp, MCP_REG_MCPR_GP_INPUTS) & epio_mask) >> epio_pin; 371 } 372 static void bnx2x_set_epio(struct bnx2x *bp, u32 epio_pin, u32 en) 373 { 374 u32 epio_mask, gp_output, gp_oenable; 375 376 /* Sanity check */ 377 if (epio_pin > 31) { 378 DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to set\n", epio_pin); 379 return; 380 } 381 DP(NETIF_MSG_LINK, "Setting EPIO pin %d to %d\n", epio_pin, en); 382 epio_mask = 1 << epio_pin; 383 /* Set this EPIO to output */ 384 gp_output = REG_RD(bp, MCP_REG_MCPR_GP_OUTPUTS); 385 if (en) 386 gp_output |= epio_mask; 387 else 388 gp_output &= ~epio_mask; 389 390 REG_WR(bp, MCP_REG_MCPR_GP_OUTPUTS, gp_output); 391 392 /* Set the value for this EPIO */ 393 gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE); 394 REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable | epio_mask); 395 } 396 397 static void bnx2x_set_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 val) 398 { 399 if (pin_cfg == PIN_CFG_NA) 400 return; 401 if (pin_cfg >= PIN_CFG_EPIO0) { 402 bnx2x_set_epio(bp, pin_cfg - PIN_CFG_EPIO0, val); 403 } else { 404 u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3; 405 u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2; 406 bnx2x_set_gpio(bp, gpio_num, (u8)val, gpio_port); 407 } 408 } 409 410 static u32 bnx2x_get_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 *val) 411 { 412 if (pin_cfg == PIN_CFG_NA) 413 return -EINVAL; 414 if (pin_cfg >= PIN_CFG_EPIO0) { 415 bnx2x_get_epio(bp, pin_cfg - PIN_CFG_EPIO0, val); 416 } else { 417 u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3; 418 u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2; 419 *val = bnx2x_get_gpio(bp, gpio_num, gpio_port); 420 } 421 return 0; 422 423 } 424 /******************************************************************/ 425 /* ETS section */ 426 /******************************************************************/ 427 static void bnx2x_ets_e2e3a0_disabled(struct link_params *params) 428 { 429 /* ETS disabled configuration*/ 430 struct bnx2x *bp = params->bp; 431 432 DP(NETIF_MSG_LINK, "ETS E2E3 disabled configuration\n"); 433 434 /* mapping between entry priority to client number (0,1,2 -debug and 435 * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST) 436 * 3bits client num. 437 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0 438 * cos1-100 cos0-011 dbg1-010 dbg0-001 MCP-000 439 */ 440 441 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, 0x4688); 442 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves 443 * as strict. Bits 0,1,2 - debug and management entries, 3 - 444 * COS0 entry, 4 - COS1 entry. 445 * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT 446 * bit4 bit3 bit2 bit1 bit0 447 * MCP and debug are strict 448 */ 449 450 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7); 451 /* defines which entries (clients) are subjected to WFQ arbitration */ 452 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0); 453 /* For strict priority entries defines the number of consecutive 454 * slots for the highest priority. 455 */ 456 REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100); 457 /* mapping between the CREDIT_WEIGHT registers and actual client 458 * numbers 459 */ 460 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0); 461 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0); 462 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0); 463 464 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 0); 465 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 0); 466 REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, 0); 467 /* ETS mode disable */ 468 REG_WR(bp, PBF_REG_ETS_ENABLED, 0); 469 /* If ETS mode is enabled (there is no strict priority) defines a WFQ 470 * weight for COS0/COS1. 471 */ 472 REG_WR(bp, PBF_REG_COS0_WEIGHT, 0x2710); 473 REG_WR(bp, PBF_REG_COS1_WEIGHT, 0x2710); 474 /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter */ 475 REG_WR(bp, PBF_REG_COS0_UPPER_BOUND, 0x989680); 476 REG_WR(bp, PBF_REG_COS1_UPPER_BOUND, 0x989680); 477 /* Defines the number of consecutive slots for the strict priority */ 478 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0); 479 } 480 /****************************************************************************** 481 * Description: 482 * Getting min_w_val will be set according to line speed . 483 *. 484 ******************************************************************************/ 485 static u32 bnx2x_ets_get_min_w_val_nig(const struct link_vars *vars) 486 { 487 u32 min_w_val = 0; 488 /* Calculate min_w_val.*/ 489 if (vars->link_up) { 490 if (vars->line_speed == SPEED_20000) 491 min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS; 492 else 493 min_w_val = ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS; 494 } else 495 min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS; 496 /* If the link isn't up (static configuration for example ) The 497 * link will be according to 20GBPS. 498 */ 499 return min_w_val; 500 } 501 /****************************************************************************** 502 * Description: 503 * Getting credit upper bound form min_w_val. 504 *. 505 ******************************************************************************/ 506 static u32 bnx2x_ets_get_credit_upper_bound(const u32 min_w_val) 507 { 508 const u32 credit_upper_bound = (u32)MAXVAL((150 * min_w_val), 509 MAX_PACKET_SIZE); 510 return credit_upper_bound; 511 } 512 /****************************************************************************** 513 * Description: 514 * Set credit upper bound for NIG. 515 *. 516 ******************************************************************************/ 517 static void bnx2x_ets_e3b0_set_credit_upper_bound_nig( 518 const struct link_params *params, 519 const u32 min_w_val) 520 { 521 struct bnx2x *bp = params->bp; 522 const u8 port = params->port; 523 const u32 credit_upper_bound = 524 bnx2x_ets_get_credit_upper_bound(min_w_val); 525 526 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 : 527 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, credit_upper_bound); 528 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 : 529 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, credit_upper_bound); 530 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 : 531 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_2, credit_upper_bound); 532 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 : 533 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_3, credit_upper_bound); 534 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 : 535 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_4, credit_upper_bound); 536 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 : 537 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_5, credit_upper_bound); 538 539 if (!port) { 540 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6, 541 credit_upper_bound); 542 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7, 543 credit_upper_bound); 544 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8, 545 credit_upper_bound); 546 } 547 } 548 /****************************************************************************** 549 * Description: 550 * Will return the NIG ETS registers to init values.Except 551 * credit_upper_bound. 552 * That isn't used in this configuration (No WFQ is enabled) and will be 553 * configured acording to spec 554 *. 555 ******************************************************************************/ 556 static void bnx2x_ets_e3b0_nig_disabled(const struct link_params *params, 557 const struct link_vars *vars) 558 { 559 struct bnx2x *bp = params->bp; 560 const u8 port = params->port; 561 const u32 min_w_val = bnx2x_ets_get_min_w_val_nig(vars); 562 /* Mapping between entry priority to client number (0,1,2 -debug and 563 * management clients, 3 - COS0 client, 4 - COS1, ... 8 - 564 * COS5)(HIGHEST) 4bits client num.TODO_ETS - Should be done by 565 * reset value or init tool 566 */ 567 if (port) { 568 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, 0x543210); 569 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB, 0x0); 570 } else { 571 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, 0x76543210); 572 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, 0x8); 573 } 574 /* For strict priority entries defines the number of consecutive 575 * slots for the highest priority. 576 */ 577 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS : 578 NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100); 579 /* Mapping between the CREDIT_WEIGHT registers and actual client 580 * numbers 581 */ 582 if (port) { 583 /*Port 1 has 6 COS*/ 584 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB, 0x210543); 585 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x0); 586 } else { 587 /*Port 0 has 9 COS*/ 588 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB, 589 0x43210876); 590 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x5); 591 } 592 593 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves 594 * as strict. Bits 0,1,2 - debug and management entries, 3 - 595 * COS0 entry, 4 - COS1 entry. 596 * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT 597 * bit4 bit3 bit2 bit1 bit0 598 * MCP and debug are strict 599 */ 600 if (port) 601 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT, 0x3f); 602 else 603 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1ff); 604 /* defines which entries (clients) are subjected to WFQ arbitration */ 605 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ : 606 NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0); 607 608 /* Please notice the register address are note continuous and a 609 * for here is note appropriate.In 2 port mode port0 only COS0-5 610 * can be used. DEBUG1,DEBUG1,MGMT are never used for WFQ* In 4 611 * port mode port1 only COS0-2 can be used. DEBUG1,DEBUG1,MGMT 612 * are never used for WFQ 613 */ 614 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 : 615 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0x0); 616 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 : 617 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0x0); 618 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 : 619 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2, 0x0); 620 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 : 621 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3, 0x0); 622 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 : 623 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4, 0x0); 624 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 : 625 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5, 0x0); 626 if (!port) { 627 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6, 0x0); 628 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7, 0x0); 629 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8, 0x0); 630 } 631 632 bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val); 633 } 634 /****************************************************************************** 635 * Description: 636 * Set credit upper bound for PBF. 637 *. 638 ******************************************************************************/ 639 static void bnx2x_ets_e3b0_set_credit_upper_bound_pbf( 640 const struct link_params *params, 641 const u32 min_w_val) 642 { 643 struct bnx2x *bp = params->bp; 644 const u32 credit_upper_bound = 645 bnx2x_ets_get_credit_upper_bound(min_w_val); 646 const u8 port = params->port; 647 u32 base_upper_bound = 0; 648 u8 max_cos = 0; 649 u8 i = 0; 650 /* In 2 port mode port0 has COS0-5 that can be used for WFQ.In 4 651 * port mode port1 has COS0-2 that can be used for WFQ. 652 */ 653 if (!port) { 654 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P0; 655 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0; 656 } else { 657 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P1; 658 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT1; 659 } 660 661 for (i = 0; i < max_cos; i++) 662 REG_WR(bp, base_upper_bound + (i << 2), credit_upper_bound); 663 } 664 665 /****************************************************************************** 666 * Description: 667 * Will return the PBF ETS registers to init values.Except 668 * credit_upper_bound. 669 * That isn't used in this configuration (No WFQ is enabled) and will be 670 * configured acording to spec 671 *. 672 ******************************************************************************/ 673 static void bnx2x_ets_e3b0_pbf_disabled(const struct link_params *params) 674 { 675 struct bnx2x *bp = params->bp; 676 const u8 port = params->port; 677 const u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL; 678 u8 i = 0; 679 u32 base_weight = 0; 680 u8 max_cos = 0; 681 682 /* Mapping between entry priority to client number 0 - COS0 683 * client, 2 - COS1, ... 5 - COS5)(HIGHEST) 4bits client num. 684 * TODO_ETS - Should be done by reset value or init tool 685 */ 686 if (port) 687 /* 0x688 (|011|0 10|00 1|000) */ 688 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , 0x688); 689 else 690 /* (10 1|100 |011|0 10|00 1|000) */ 691 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , 0x2C688); 692 693 /* TODO_ETS - Should be done by reset value or init tool */ 694 if (port) 695 /* 0x688 (|011|0 10|00 1|000)*/ 696 REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1, 0x688); 697 else 698 /* 0x2C688 (10 1|100 |011|0 10|00 1|000) */ 699 REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0, 0x2C688); 700 701 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 : 702 PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0 , 0x100); 703 704 705 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 : 706 PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , 0); 707 708 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 : 709 PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0 , 0); 710 /* In 2 port mode port0 has COS0-5 that can be used for WFQ. 711 * In 4 port mode port1 has COS0-2 that can be used for WFQ. 712 */ 713 if (!port) { 714 base_weight = PBF_REG_COS0_WEIGHT_P0; 715 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0; 716 } else { 717 base_weight = PBF_REG_COS0_WEIGHT_P1; 718 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT1; 719 } 720 721 for (i = 0; i < max_cos; i++) 722 REG_WR(bp, base_weight + (0x4 * i), 0); 723 724 bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf); 725 } 726 /****************************************************************************** 727 * Description: 728 * E3B0 disable will return basicly the values to init values. 729 *. 730 ******************************************************************************/ 731 static int bnx2x_ets_e3b0_disabled(const struct link_params *params, 732 const struct link_vars *vars) 733 { 734 struct bnx2x *bp = params->bp; 735 736 if (!CHIP_IS_E3B0(bp)) { 737 DP(NETIF_MSG_LINK, 738 "bnx2x_ets_e3b0_disabled the chip isn't E3B0\n"); 739 return -EINVAL; 740 } 741 742 bnx2x_ets_e3b0_nig_disabled(params, vars); 743 744 bnx2x_ets_e3b0_pbf_disabled(params); 745 746 return 0; 747 } 748 749 /****************************************************************************** 750 * Description: 751 * Disable will return basicly the values to init values. 752 * 753 ******************************************************************************/ 754 int bnx2x_ets_disabled(struct link_params *params, 755 struct link_vars *vars) 756 { 757 struct bnx2x *bp = params->bp; 758 int bnx2x_status = 0; 759 760 if ((CHIP_IS_E2(bp)) || (CHIP_IS_E3A0(bp))) 761 bnx2x_ets_e2e3a0_disabled(params); 762 else if (CHIP_IS_E3B0(bp)) 763 bnx2x_status = bnx2x_ets_e3b0_disabled(params, vars); 764 else { 765 DP(NETIF_MSG_LINK, "bnx2x_ets_disabled - chip not supported\n"); 766 return -EINVAL; 767 } 768 769 return bnx2x_status; 770 } 771 772 /****************************************************************************** 773 * Description 774 * Set the COS mappimg to SP and BW until this point all the COS are not 775 * set as SP or BW. 776 ******************************************************************************/ 777 static int bnx2x_ets_e3b0_cli_map(const struct link_params *params, 778 const struct bnx2x_ets_params *ets_params, 779 const u8 cos_sp_bitmap, 780 const u8 cos_bw_bitmap) 781 { 782 struct bnx2x *bp = params->bp; 783 const u8 port = params->port; 784 const u8 nig_cli_sp_bitmap = 0x7 | (cos_sp_bitmap << 3); 785 const u8 pbf_cli_sp_bitmap = cos_sp_bitmap; 786 const u8 nig_cli_subject2wfq_bitmap = cos_bw_bitmap << 3; 787 const u8 pbf_cli_subject2wfq_bitmap = cos_bw_bitmap; 788 789 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT : 790 NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, nig_cli_sp_bitmap); 791 792 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 : 793 PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , pbf_cli_sp_bitmap); 794 795 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ : 796 NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 797 nig_cli_subject2wfq_bitmap); 798 799 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 : 800 PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0, 801 pbf_cli_subject2wfq_bitmap); 802 803 return 0; 804 } 805 806 /****************************************************************************** 807 * Description: 808 * This function is needed because NIG ARB_CREDIT_WEIGHT_X are 809 * not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable. 810 ******************************************************************************/ 811 static int bnx2x_ets_e3b0_set_cos_bw(struct bnx2x *bp, 812 const u8 cos_entry, 813 const u32 min_w_val_nig, 814 const u32 min_w_val_pbf, 815 const u16 total_bw, 816 const u8 bw, 817 const u8 port) 818 { 819 u32 nig_reg_adress_crd_weight = 0; 820 u32 pbf_reg_adress_crd_weight = 0; 821 /* Calculate and set BW for this COS - use 1 instead of 0 for BW */ 822 const u32 cos_bw_nig = ((bw ? bw : 1) * min_w_val_nig) / total_bw; 823 const u32 cos_bw_pbf = ((bw ? bw : 1) * min_w_val_pbf) / total_bw; 824 825 switch (cos_entry) { 826 case 0: 827 nig_reg_adress_crd_weight = 828 (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 : 829 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0; 830 pbf_reg_adress_crd_weight = (port) ? 831 PBF_REG_COS0_WEIGHT_P1 : PBF_REG_COS0_WEIGHT_P0; 832 break; 833 case 1: 834 nig_reg_adress_crd_weight = (port) ? 835 NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 : 836 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1; 837 pbf_reg_adress_crd_weight = (port) ? 838 PBF_REG_COS1_WEIGHT_P1 : PBF_REG_COS1_WEIGHT_P0; 839 break; 840 case 2: 841 nig_reg_adress_crd_weight = (port) ? 842 NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 : 843 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2; 844 845 pbf_reg_adress_crd_weight = (port) ? 846 PBF_REG_COS2_WEIGHT_P1 : PBF_REG_COS2_WEIGHT_P0; 847 break; 848 case 3: 849 if (port) 850 return -EINVAL; 851 nig_reg_adress_crd_weight = 852 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3; 853 pbf_reg_adress_crd_weight = 854 PBF_REG_COS3_WEIGHT_P0; 855 break; 856 case 4: 857 if (port) 858 return -EINVAL; 859 nig_reg_adress_crd_weight = 860 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4; 861 pbf_reg_adress_crd_weight = PBF_REG_COS4_WEIGHT_P0; 862 break; 863 case 5: 864 if (port) 865 return -EINVAL; 866 nig_reg_adress_crd_weight = 867 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5; 868 pbf_reg_adress_crd_weight = PBF_REG_COS5_WEIGHT_P0; 869 break; 870 } 871 872 REG_WR(bp, nig_reg_adress_crd_weight, cos_bw_nig); 873 874 REG_WR(bp, pbf_reg_adress_crd_weight, cos_bw_pbf); 875 876 return 0; 877 } 878 /****************************************************************************** 879 * Description: 880 * Calculate the total BW.A value of 0 isn't legal. 881 * 882 ******************************************************************************/ 883 static int bnx2x_ets_e3b0_get_total_bw( 884 const struct link_params *params, 885 struct bnx2x_ets_params *ets_params, 886 u16 *total_bw) 887 { 888 struct bnx2x *bp = params->bp; 889 u8 cos_idx = 0; 890 u8 is_bw_cos_exist = 0; 891 892 *total_bw = 0 ; 893 /* Calculate total BW requested */ 894 for (cos_idx = 0; cos_idx < ets_params->num_of_cos; cos_idx++) { 895 if (ets_params->cos[cos_idx].state == bnx2x_cos_state_bw) { 896 is_bw_cos_exist = 1; 897 if (!ets_params->cos[cos_idx].params.bw_params.bw) { 898 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config BW" 899 "was set to 0\n"); 900 /* This is to prevent a state when ramrods 901 * can't be sent 902 */ 903 ets_params->cos[cos_idx].params.bw_params.bw 904 = 1; 905 } 906 *total_bw += 907 ets_params->cos[cos_idx].params.bw_params.bw; 908 } 909 } 910 911 /* Check total BW is valid */ 912 if ((is_bw_cos_exist == 1) && (*total_bw != 100)) { 913 if (*total_bw == 0) { 914 DP(NETIF_MSG_LINK, 915 "bnx2x_ets_E3B0_config total BW shouldn't be 0\n"); 916 return -EINVAL; 917 } 918 DP(NETIF_MSG_LINK, 919 "bnx2x_ets_E3B0_config total BW should be 100\n"); 920 /* We can handle a case whre the BW isn't 100 this can happen 921 * if the TC are joined. 922 */ 923 } 924 return 0; 925 } 926 927 /****************************************************************************** 928 * Description: 929 * Invalidate all the sp_pri_to_cos. 930 * 931 ******************************************************************************/ 932 static void bnx2x_ets_e3b0_sp_pri_to_cos_init(u8 *sp_pri_to_cos) 933 { 934 u8 pri = 0; 935 for (pri = 0; pri < DCBX_MAX_NUM_COS; pri++) 936 sp_pri_to_cos[pri] = DCBX_INVALID_COS; 937 } 938 /****************************************************************************** 939 * Description: 940 * Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers 941 * according to sp_pri_to_cos. 942 * 943 ******************************************************************************/ 944 static int bnx2x_ets_e3b0_sp_pri_to_cos_set(const struct link_params *params, 945 u8 *sp_pri_to_cos, const u8 pri, 946 const u8 cos_entry) 947 { 948 struct bnx2x *bp = params->bp; 949 const u8 port = params->port; 950 const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 : 951 DCBX_E3B0_MAX_NUM_COS_PORT0; 952 953 if (pri >= max_num_of_cos) { 954 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid " 955 "parameter Illegal strict priority\n"); 956 return -EINVAL; 957 } 958 959 if (sp_pri_to_cos[pri] != DCBX_INVALID_COS) { 960 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid " 961 "parameter There can't be two COS's with " 962 "the same strict pri\n"); 963 return -EINVAL; 964 } 965 966 sp_pri_to_cos[pri] = cos_entry; 967 return 0; 968 969 } 970 971 /****************************************************************************** 972 * Description: 973 * Returns the correct value according to COS and priority in 974 * the sp_pri_cli register. 975 * 976 ******************************************************************************/ 977 static u64 bnx2x_e3b0_sp_get_pri_cli_reg(const u8 cos, const u8 cos_offset, 978 const u8 pri_set, 979 const u8 pri_offset, 980 const u8 entry_size) 981 { 982 u64 pri_cli_nig = 0; 983 pri_cli_nig = ((u64)(cos + cos_offset)) << (entry_size * 984 (pri_set + pri_offset)); 985 986 return pri_cli_nig; 987 } 988 /****************************************************************************** 989 * Description: 990 * Returns the correct value according to COS and priority in the 991 * sp_pri_cli register for NIG. 992 * 993 ******************************************************************************/ 994 static u64 bnx2x_e3b0_sp_get_pri_cli_reg_nig(const u8 cos, const u8 pri_set) 995 { 996 /* MCP Dbg0 and dbg1 are always with higher strict pri*/ 997 const u8 nig_cos_offset = 3; 998 const u8 nig_pri_offset = 3; 999 1000 return bnx2x_e3b0_sp_get_pri_cli_reg(cos, nig_cos_offset, pri_set, 1001 nig_pri_offset, 4); 1002 1003 } 1004 /****************************************************************************** 1005 * Description: 1006 * Returns the correct value according to COS and priority in the 1007 * sp_pri_cli register for PBF. 1008 * 1009 ******************************************************************************/ 1010 static u64 bnx2x_e3b0_sp_get_pri_cli_reg_pbf(const u8 cos, const u8 pri_set) 1011 { 1012 const u8 pbf_cos_offset = 0; 1013 const u8 pbf_pri_offset = 0; 1014 1015 return bnx2x_e3b0_sp_get_pri_cli_reg(cos, pbf_cos_offset, pri_set, 1016 pbf_pri_offset, 3); 1017 1018 } 1019 1020 /****************************************************************************** 1021 * Description: 1022 * Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers 1023 * according to sp_pri_to_cos.(which COS has higher priority) 1024 * 1025 ******************************************************************************/ 1026 static int bnx2x_ets_e3b0_sp_set_pri_cli_reg(const struct link_params *params, 1027 u8 *sp_pri_to_cos) 1028 { 1029 struct bnx2x *bp = params->bp; 1030 u8 i = 0; 1031 const u8 port = params->port; 1032 /* MCP Dbg0 and dbg1 are always with higher strict pri*/ 1033 u64 pri_cli_nig = 0x210; 1034 u32 pri_cli_pbf = 0x0; 1035 u8 pri_set = 0; 1036 u8 pri_bitmask = 0; 1037 const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 : 1038 DCBX_E3B0_MAX_NUM_COS_PORT0; 1039 1040 u8 cos_bit_to_set = (1 << max_num_of_cos) - 1; 1041 1042 /* Set all the strict priority first */ 1043 for (i = 0; i < max_num_of_cos; i++) { 1044 if (sp_pri_to_cos[i] != DCBX_INVALID_COS) { 1045 if (sp_pri_to_cos[i] >= DCBX_MAX_NUM_COS) { 1046 DP(NETIF_MSG_LINK, 1047 "bnx2x_ets_e3b0_sp_set_pri_cli_reg " 1048 "invalid cos entry\n"); 1049 return -EINVAL; 1050 } 1051 1052 pri_cli_nig |= bnx2x_e3b0_sp_get_pri_cli_reg_nig( 1053 sp_pri_to_cos[i], pri_set); 1054 1055 pri_cli_pbf |= bnx2x_e3b0_sp_get_pri_cli_reg_pbf( 1056 sp_pri_to_cos[i], pri_set); 1057 pri_bitmask = 1 << sp_pri_to_cos[i]; 1058 /* COS is used remove it from bitmap.*/ 1059 if (!(pri_bitmask & cos_bit_to_set)) { 1060 DP(NETIF_MSG_LINK, 1061 "bnx2x_ets_e3b0_sp_set_pri_cli_reg " 1062 "invalid There can't be two COS's with" 1063 " the same strict pri\n"); 1064 return -EINVAL; 1065 } 1066 cos_bit_to_set &= ~pri_bitmask; 1067 pri_set++; 1068 } 1069 } 1070 1071 /* Set all the Non strict priority i= COS*/ 1072 for (i = 0; i < max_num_of_cos; i++) { 1073 pri_bitmask = 1 << i; 1074 /* Check if COS was already used for SP */ 1075 if (pri_bitmask & cos_bit_to_set) { 1076 /* COS wasn't used for SP */ 1077 pri_cli_nig |= bnx2x_e3b0_sp_get_pri_cli_reg_nig( 1078 i, pri_set); 1079 1080 pri_cli_pbf |= bnx2x_e3b0_sp_get_pri_cli_reg_pbf( 1081 i, pri_set); 1082 /* COS is used remove it from bitmap.*/ 1083 cos_bit_to_set &= ~pri_bitmask; 1084 pri_set++; 1085 } 1086 } 1087 1088 if (pri_set != max_num_of_cos) { 1089 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_set_pri_cli_reg not all " 1090 "entries were set\n"); 1091 return -EINVAL; 1092 } 1093 1094 if (port) { 1095 /* Only 6 usable clients*/ 1096 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, 1097 (u32)pri_cli_nig); 1098 1099 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , pri_cli_pbf); 1100 } else { 1101 /* Only 9 usable clients*/ 1102 const u32 pri_cli_nig_lsb = (u32) (pri_cli_nig); 1103 const u32 pri_cli_nig_msb = (u32) ((pri_cli_nig >> 32) & 0xF); 1104 1105 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, 1106 pri_cli_nig_lsb); 1107 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, 1108 pri_cli_nig_msb); 1109 1110 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , pri_cli_pbf); 1111 } 1112 return 0; 1113 } 1114 1115 /****************************************************************************** 1116 * Description: 1117 * Configure the COS to ETS according to BW and SP settings. 1118 ******************************************************************************/ 1119 int bnx2x_ets_e3b0_config(const struct link_params *params, 1120 const struct link_vars *vars, 1121 struct bnx2x_ets_params *ets_params) 1122 { 1123 struct bnx2x *bp = params->bp; 1124 int bnx2x_status = 0; 1125 const u8 port = params->port; 1126 u16 total_bw = 0; 1127 const u32 min_w_val_nig = bnx2x_ets_get_min_w_val_nig(vars); 1128 const u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL; 1129 u8 cos_bw_bitmap = 0; 1130 u8 cos_sp_bitmap = 0; 1131 u8 sp_pri_to_cos[DCBX_MAX_NUM_COS] = {0}; 1132 const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 : 1133 DCBX_E3B0_MAX_NUM_COS_PORT0; 1134 u8 cos_entry = 0; 1135 1136 if (!CHIP_IS_E3B0(bp)) { 1137 DP(NETIF_MSG_LINK, 1138 "bnx2x_ets_e3b0_disabled the chip isn't E3B0\n"); 1139 return -EINVAL; 1140 } 1141 1142 if ((ets_params->num_of_cos > max_num_of_cos)) { 1143 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config the number of COS " 1144 "isn't supported\n"); 1145 return -EINVAL; 1146 } 1147 1148 /* Prepare sp strict priority parameters*/ 1149 bnx2x_ets_e3b0_sp_pri_to_cos_init(sp_pri_to_cos); 1150 1151 /* Prepare BW parameters*/ 1152 bnx2x_status = bnx2x_ets_e3b0_get_total_bw(params, ets_params, 1153 &total_bw); 1154 if (bnx2x_status) { 1155 DP(NETIF_MSG_LINK, 1156 "bnx2x_ets_E3B0_config get_total_bw failed\n"); 1157 return -EINVAL; 1158 } 1159 1160 /* Upper bound is set according to current link speed (min_w_val 1161 * should be the same for upper bound and COS credit val). 1162 */ 1163 bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val_nig); 1164 bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf); 1165 1166 1167 for (cos_entry = 0; cos_entry < ets_params->num_of_cos; cos_entry++) { 1168 if (bnx2x_cos_state_bw == ets_params->cos[cos_entry].state) { 1169 cos_bw_bitmap |= (1 << cos_entry); 1170 /* The function also sets the BW in HW(not the mappin 1171 * yet) 1172 */ 1173 bnx2x_status = bnx2x_ets_e3b0_set_cos_bw( 1174 bp, cos_entry, min_w_val_nig, min_w_val_pbf, 1175 total_bw, 1176 ets_params->cos[cos_entry].params.bw_params.bw, 1177 port); 1178 } else if (bnx2x_cos_state_strict == 1179 ets_params->cos[cos_entry].state){ 1180 cos_sp_bitmap |= (1 << cos_entry); 1181 1182 bnx2x_status = bnx2x_ets_e3b0_sp_pri_to_cos_set( 1183 params, 1184 sp_pri_to_cos, 1185 ets_params->cos[cos_entry].params.sp_params.pri, 1186 cos_entry); 1187 1188 } else { 1189 DP(NETIF_MSG_LINK, 1190 "bnx2x_ets_e3b0_config cos state not valid\n"); 1191 return -EINVAL; 1192 } 1193 if (bnx2x_status) { 1194 DP(NETIF_MSG_LINK, 1195 "bnx2x_ets_e3b0_config set cos bw failed\n"); 1196 return bnx2x_status; 1197 } 1198 } 1199 1200 /* Set SP register (which COS has higher priority) */ 1201 bnx2x_status = bnx2x_ets_e3b0_sp_set_pri_cli_reg(params, 1202 sp_pri_to_cos); 1203 1204 if (bnx2x_status) { 1205 DP(NETIF_MSG_LINK, 1206 "bnx2x_ets_E3B0_config set_pri_cli_reg failed\n"); 1207 return bnx2x_status; 1208 } 1209 1210 /* Set client mapping of BW and strict */ 1211 bnx2x_status = bnx2x_ets_e3b0_cli_map(params, ets_params, 1212 cos_sp_bitmap, 1213 cos_bw_bitmap); 1214 1215 if (bnx2x_status) { 1216 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config SP failed\n"); 1217 return bnx2x_status; 1218 } 1219 return 0; 1220 } 1221 static void bnx2x_ets_bw_limit_common(const struct link_params *params) 1222 { 1223 /* ETS disabled configuration */ 1224 struct bnx2x *bp = params->bp; 1225 DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n"); 1226 /* Defines which entries (clients) are subjected to WFQ arbitration 1227 * COS0 0x8 1228 * COS1 0x10 1229 */ 1230 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0x18); 1231 /* Mapping between the ARB_CREDIT_WEIGHT registers and actual 1232 * client numbers (WEIGHT_0 does not actually have to represent 1233 * client 0) 1234 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0 1235 * cos1-001 cos0-000 dbg1-100 dbg0-011 MCP-010 1236 */ 1237 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0x111A); 1238 1239 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 1240 ETS_BW_LIMIT_CREDIT_UPPER_BOUND); 1241 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 1242 ETS_BW_LIMIT_CREDIT_UPPER_BOUND); 1243 1244 /* ETS mode enabled*/ 1245 REG_WR(bp, PBF_REG_ETS_ENABLED, 1); 1246 1247 /* Defines the number of consecutive slots for the strict priority */ 1248 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0); 1249 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves 1250 * as strict. Bits 0,1,2 - debug and management entries, 3 - COS0 1251 * entry, 4 - COS1 entry. 1252 * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT 1253 * bit4 bit3 bit2 bit1 bit0 1254 * MCP and debug are strict 1255 */ 1256 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7); 1257 1258 /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter.*/ 1259 REG_WR(bp, PBF_REG_COS0_UPPER_BOUND, 1260 ETS_BW_LIMIT_CREDIT_UPPER_BOUND); 1261 REG_WR(bp, PBF_REG_COS1_UPPER_BOUND, 1262 ETS_BW_LIMIT_CREDIT_UPPER_BOUND); 1263 } 1264 1265 void bnx2x_ets_bw_limit(const struct link_params *params, const u32 cos0_bw, 1266 const u32 cos1_bw) 1267 { 1268 /* ETS disabled configuration*/ 1269 struct bnx2x *bp = params->bp; 1270 const u32 total_bw = cos0_bw + cos1_bw; 1271 u32 cos0_credit_weight = 0; 1272 u32 cos1_credit_weight = 0; 1273 1274 DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n"); 1275 1276 if ((!total_bw) || 1277 (!cos0_bw) || 1278 (!cos1_bw)) { 1279 DP(NETIF_MSG_LINK, "Total BW can't be zero\n"); 1280 return; 1281 } 1282 1283 cos0_credit_weight = (cos0_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/ 1284 total_bw; 1285 cos1_credit_weight = (cos1_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/ 1286 total_bw; 1287 1288 bnx2x_ets_bw_limit_common(params); 1289 1290 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, cos0_credit_weight); 1291 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, cos1_credit_weight); 1292 1293 REG_WR(bp, PBF_REG_COS0_WEIGHT, cos0_credit_weight); 1294 REG_WR(bp, PBF_REG_COS1_WEIGHT, cos1_credit_weight); 1295 } 1296 1297 int bnx2x_ets_strict(const struct link_params *params, const u8 strict_cos) 1298 { 1299 /* ETS disabled configuration*/ 1300 struct bnx2x *bp = params->bp; 1301 u32 val = 0; 1302 1303 DP(NETIF_MSG_LINK, "ETS enabled strict configuration\n"); 1304 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves 1305 * as strict. Bits 0,1,2 - debug and management entries, 1306 * 3 - COS0 entry, 4 - COS1 entry. 1307 * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT 1308 * bit4 bit3 bit2 bit1 bit0 1309 * MCP and debug are strict 1310 */ 1311 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1F); 1312 /* For strict priority entries defines the number of consecutive slots 1313 * for the highest priority. 1314 */ 1315 REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100); 1316 /* ETS mode disable */ 1317 REG_WR(bp, PBF_REG_ETS_ENABLED, 0); 1318 /* Defines the number of consecutive slots for the strict priority */ 1319 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0x100); 1320 1321 /* Defines the number of consecutive slots for the strict priority */ 1322 REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, strict_cos); 1323 1324 /* Mapping between entry priority to client number (0,1,2 -debug and 1325 * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST) 1326 * 3bits client num. 1327 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0 1328 * dbg0-010 dbg1-001 cos1-100 cos0-011 MCP-000 1329 * dbg0-010 dbg1-001 cos0-011 cos1-100 MCP-000 1330 */ 1331 val = (!strict_cos) ? 0x2318 : 0x22E0; 1332 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, val); 1333 1334 return 0; 1335 } 1336 1337 /******************************************************************/ 1338 /* PFC section */ 1339 /******************************************************************/ 1340 static void bnx2x_update_pfc_xmac(struct link_params *params, 1341 struct link_vars *vars, 1342 u8 is_lb) 1343 { 1344 struct bnx2x *bp = params->bp; 1345 u32 xmac_base; 1346 u32 pause_val, pfc0_val, pfc1_val; 1347 1348 /* XMAC base adrr */ 1349 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; 1350 1351 /* Initialize pause and pfc registers */ 1352 pause_val = 0x18000; 1353 pfc0_val = 0xFFFF8000; 1354 pfc1_val = 0x2; 1355 1356 /* No PFC support */ 1357 if (!(params->feature_config_flags & 1358 FEATURE_CONFIG_PFC_ENABLED)) { 1359 1360 /* RX flow control - Process pause frame in receive direction 1361 */ 1362 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX) 1363 pause_val |= XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN; 1364 1365 /* TX flow control - Send pause packet when buffer is full */ 1366 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) 1367 pause_val |= XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN; 1368 } else {/* PFC support */ 1369 pfc1_val |= XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN | 1370 XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN | 1371 XMAC_PFC_CTRL_HI_REG_RX_PFC_EN | 1372 XMAC_PFC_CTRL_HI_REG_TX_PFC_EN | 1373 XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON; 1374 /* Write pause and PFC registers */ 1375 REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val); 1376 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val); 1377 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val); 1378 pfc1_val &= ~XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON; 1379 1380 } 1381 1382 /* Write pause and PFC registers */ 1383 REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val); 1384 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val); 1385 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val); 1386 1387 1388 /* Set MAC address for source TX Pause/PFC frames */ 1389 REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_LO, 1390 ((params->mac_addr[2] << 24) | 1391 (params->mac_addr[3] << 16) | 1392 (params->mac_addr[4] << 8) | 1393 (params->mac_addr[5]))); 1394 REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_HI, 1395 ((params->mac_addr[0] << 8) | 1396 (params->mac_addr[1]))); 1397 1398 udelay(30); 1399 } 1400 1401 1402 static void bnx2x_emac_get_pfc_stat(struct link_params *params, 1403 u32 pfc_frames_sent[2], 1404 u32 pfc_frames_received[2]) 1405 { 1406 /* Read pfc statistic */ 1407 struct bnx2x *bp = params->bp; 1408 u32 emac_base = params->port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; 1409 u32 val_xon = 0; 1410 u32 val_xoff = 0; 1411 1412 DP(NETIF_MSG_LINK, "pfc statistic read from EMAC\n"); 1413 1414 /* PFC received frames */ 1415 val_xoff = REG_RD(bp, emac_base + 1416 EMAC_REG_RX_PFC_STATS_XOFF_RCVD); 1417 val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_RCVD_COUNT; 1418 val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_RCVD); 1419 val_xon &= EMAC_REG_RX_PFC_STATS_XON_RCVD_COUNT; 1420 1421 pfc_frames_received[0] = val_xon + val_xoff; 1422 1423 /* PFC received sent */ 1424 val_xoff = REG_RD(bp, emac_base + 1425 EMAC_REG_RX_PFC_STATS_XOFF_SENT); 1426 val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_SENT_COUNT; 1427 val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_SENT); 1428 val_xon &= EMAC_REG_RX_PFC_STATS_XON_SENT_COUNT; 1429 1430 pfc_frames_sent[0] = val_xon + val_xoff; 1431 } 1432 1433 /* Read pfc statistic*/ 1434 void bnx2x_pfc_statistic(struct link_params *params, struct link_vars *vars, 1435 u32 pfc_frames_sent[2], 1436 u32 pfc_frames_received[2]) 1437 { 1438 /* Read pfc statistic */ 1439 struct bnx2x *bp = params->bp; 1440 1441 DP(NETIF_MSG_LINK, "pfc statistic\n"); 1442 1443 if (!vars->link_up) 1444 return; 1445 1446 if (vars->mac_type == MAC_TYPE_EMAC) { 1447 DP(NETIF_MSG_LINK, "About to read PFC stats from EMAC\n"); 1448 bnx2x_emac_get_pfc_stat(params, pfc_frames_sent, 1449 pfc_frames_received); 1450 } 1451 } 1452 /******************************************************************/ 1453 /* MAC/PBF section */ 1454 /******************************************************************/ 1455 static void bnx2x_set_mdio_clk(struct bnx2x *bp, u32 chip_id, 1456 u32 emac_base) 1457 { 1458 u32 new_mode, cur_mode; 1459 u32 clc_cnt; 1460 /* Set clause 45 mode, slow down the MDIO clock to 2.5MHz 1461 * (a value of 49==0x31) and make sure that the AUTO poll is off 1462 */ 1463 cur_mode = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE); 1464 1465 if (USES_WARPCORE(bp)) 1466 clc_cnt = 74L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT; 1467 else 1468 clc_cnt = 49L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT; 1469 1470 if (((cur_mode & EMAC_MDIO_MODE_CLOCK_CNT) == clc_cnt) && 1471 (cur_mode & (EMAC_MDIO_MODE_CLAUSE_45))) 1472 return; 1473 1474 new_mode = cur_mode & 1475 ~(EMAC_MDIO_MODE_AUTO_POLL | EMAC_MDIO_MODE_CLOCK_CNT); 1476 new_mode |= clc_cnt; 1477 new_mode |= (EMAC_MDIO_MODE_CLAUSE_45); 1478 1479 DP(NETIF_MSG_LINK, "Changing emac_mode from 0x%x to 0x%x\n", 1480 cur_mode, new_mode); 1481 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE, new_mode); 1482 udelay(40); 1483 } 1484 1485 static void bnx2x_set_mdio_emac_per_phy(struct bnx2x *bp, 1486 struct link_params *params) 1487 { 1488 u8 phy_index; 1489 /* Set mdio clock per phy */ 1490 for (phy_index = INT_PHY; phy_index < params->num_phys; 1491 phy_index++) 1492 bnx2x_set_mdio_clk(bp, params->chip_id, 1493 params->phy[phy_index].mdio_ctrl); 1494 } 1495 1496 static u8 bnx2x_is_4_port_mode(struct bnx2x *bp) 1497 { 1498 u32 port4mode_ovwr_val; 1499 /* Check 4-port override enabled */ 1500 port4mode_ovwr_val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR); 1501 if (port4mode_ovwr_val & (1<<0)) { 1502 /* Return 4-port mode override value */ 1503 return ((port4mode_ovwr_val & (1<<1)) == (1<<1)); 1504 } 1505 /* Return 4-port mode from input pin */ 1506 return (u8)REG_RD(bp, MISC_REG_PORT4MODE_EN); 1507 } 1508 1509 static void bnx2x_emac_init(struct link_params *params, 1510 struct link_vars *vars) 1511 { 1512 /* reset and unreset the emac core */ 1513 struct bnx2x *bp = params->bp; 1514 u8 port = params->port; 1515 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; 1516 u32 val; 1517 u16 timeout; 1518 1519 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 1520 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port)); 1521 udelay(5); 1522 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 1523 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port)); 1524 1525 /* init emac - use read-modify-write */ 1526 /* self clear reset */ 1527 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE); 1528 EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET)); 1529 1530 timeout = 200; 1531 do { 1532 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE); 1533 DP(NETIF_MSG_LINK, "EMAC reset reg is %u\n", val); 1534 if (!timeout) { 1535 DP(NETIF_MSG_LINK, "EMAC timeout!\n"); 1536 return; 1537 } 1538 timeout--; 1539 } while (val & EMAC_MODE_RESET); 1540 1541 bnx2x_set_mdio_emac_per_phy(bp, params); 1542 /* Set mac address */ 1543 val = ((params->mac_addr[0] << 8) | 1544 params->mac_addr[1]); 1545 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH, val); 1546 1547 val = ((params->mac_addr[2] << 24) | 1548 (params->mac_addr[3] << 16) | 1549 (params->mac_addr[4] << 8) | 1550 params->mac_addr[5]); 1551 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + 4, val); 1552 } 1553 1554 static void bnx2x_set_xumac_nig(struct link_params *params, 1555 u16 tx_pause_en, 1556 u8 enable) 1557 { 1558 struct bnx2x *bp = params->bp; 1559 1560 REG_WR(bp, params->port ? NIG_REG_P1_MAC_IN_EN : NIG_REG_P0_MAC_IN_EN, 1561 enable); 1562 REG_WR(bp, params->port ? NIG_REG_P1_MAC_OUT_EN : NIG_REG_P0_MAC_OUT_EN, 1563 enable); 1564 REG_WR(bp, params->port ? NIG_REG_P1_MAC_PAUSE_OUT_EN : 1565 NIG_REG_P0_MAC_PAUSE_OUT_EN, tx_pause_en); 1566 } 1567 1568 static void bnx2x_set_umac_rxtx(struct link_params *params, u8 en) 1569 { 1570 u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0; 1571 u32 val; 1572 struct bnx2x *bp = params->bp; 1573 if (!(REG_RD(bp, MISC_REG_RESET_REG_2) & 1574 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port))) 1575 return; 1576 val = REG_RD(bp, umac_base + UMAC_REG_COMMAND_CONFIG); 1577 if (en) 1578 val |= (UMAC_COMMAND_CONFIG_REG_TX_ENA | 1579 UMAC_COMMAND_CONFIG_REG_RX_ENA); 1580 else 1581 val &= ~(UMAC_COMMAND_CONFIG_REG_TX_ENA | 1582 UMAC_COMMAND_CONFIG_REG_RX_ENA); 1583 /* Disable RX and TX */ 1584 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val); 1585 } 1586 1587 static void bnx2x_umac_enable(struct link_params *params, 1588 struct link_vars *vars, u8 lb) 1589 { 1590 u32 val; 1591 u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0; 1592 struct bnx2x *bp = params->bp; 1593 /* Reset UMAC */ 1594 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 1595 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port)); 1596 usleep_range(1000, 2000); 1597 1598 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 1599 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port)); 1600 1601 DP(NETIF_MSG_LINK, "enabling UMAC\n"); 1602 1603 /* This register opens the gate for the UMAC despite its name */ 1604 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1); 1605 1606 val = UMAC_COMMAND_CONFIG_REG_PROMIS_EN | 1607 UMAC_COMMAND_CONFIG_REG_PAD_EN | 1608 UMAC_COMMAND_CONFIG_REG_SW_RESET | 1609 UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK; 1610 switch (vars->line_speed) { 1611 case SPEED_10: 1612 val |= (0<<2); 1613 break; 1614 case SPEED_100: 1615 val |= (1<<2); 1616 break; 1617 case SPEED_1000: 1618 val |= (2<<2); 1619 break; 1620 case SPEED_2500: 1621 val |= (3<<2); 1622 break; 1623 default: 1624 DP(NETIF_MSG_LINK, "Invalid speed for UMAC %d\n", 1625 vars->line_speed); 1626 break; 1627 } 1628 if (!(vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)) 1629 val |= UMAC_COMMAND_CONFIG_REG_IGNORE_TX_PAUSE; 1630 1631 if (!(vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)) 1632 val |= UMAC_COMMAND_CONFIG_REG_PAUSE_IGNORE; 1633 1634 if (vars->duplex == DUPLEX_HALF) 1635 val |= UMAC_COMMAND_CONFIG_REG_HD_ENA; 1636 1637 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val); 1638 udelay(50); 1639 1640 /* Configure UMAC for EEE */ 1641 if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) { 1642 DP(NETIF_MSG_LINK, "configured UMAC for EEE\n"); 1643 REG_WR(bp, umac_base + UMAC_REG_UMAC_EEE_CTRL, 1644 UMAC_UMAC_EEE_CTRL_REG_EEE_EN); 1645 REG_WR(bp, umac_base + UMAC_REG_EEE_WAKE_TIMER, 0x11); 1646 } else { 1647 REG_WR(bp, umac_base + UMAC_REG_UMAC_EEE_CTRL, 0x0); 1648 } 1649 1650 /* Set MAC address for source TX Pause/PFC frames (under SW reset) */ 1651 REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR0, 1652 ((params->mac_addr[2] << 24) | 1653 (params->mac_addr[3] << 16) | 1654 (params->mac_addr[4] << 8) | 1655 (params->mac_addr[5]))); 1656 REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR1, 1657 ((params->mac_addr[0] << 8) | 1658 (params->mac_addr[1]))); 1659 1660 /* Enable RX and TX */ 1661 val &= ~UMAC_COMMAND_CONFIG_REG_PAD_EN; 1662 val |= UMAC_COMMAND_CONFIG_REG_TX_ENA | 1663 UMAC_COMMAND_CONFIG_REG_RX_ENA; 1664 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val); 1665 udelay(50); 1666 1667 /* Remove SW Reset */ 1668 val &= ~UMAC_COMMAND_CONFIG_REG_SW_RESET; 1669 1670 /* Check loopback mode */ 1671 if (lb) 1672 val |= UMAC_COMMAND_CONFIG_REG_LOOP_ENA; 1673 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val); 1674 1675 /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame 1676 * length used by the MAC receive logic to check frames. 1677 */ 1678 REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710); 1679 bnx2x_set_xumac_nig(params, 1680 ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1); 1681 vars->mac_type = MAC_TYPE_UMAC; 1682 1683 } 1684 1685 /* Define the XMAC mode */ 1686 static void bnx2x_xmac_init(struct link_params *params, u32 max_speed) 1687 { 1688 struct bnx2x *bp = params->bp; 1689 u32 is_port4mode = bnx2x_is_4_port_mode(bp); 1690 1691 /* In 4-port mode, need to set the mode only once, so if XMAC is 1692 * already out of reset, it means the mode has already been set, 1693 * and it must not* reset the XMAC again, since it controls both 1694 * ports of the path 1695 */ 1696 1697 if (((CHIP_NUM(bp) == CHIP_NUM_57840_4_10) || 1698 (CHIP_NUM(bp) == CHIP_NUM_57840_2_20) || 1699 (CHIP_NUM(bp) == CHIP_NUM_57840_OBSOLETE)) && 1700 is_port4mode && 1701 (REG_RD(bp, MISC_REG_RESET_REG_2) & 1702 MISC_REGISTERS_RESET_REG_2_XMAC)) { 1703 DP(NETIF_MSG_LINK, 1704 "XMAC already out of reset in 4-port mode\n"); 1705 return; 1706 } 1707 1708 /* Hard reset */ 1709 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 1710 MISC_REGISTERS_RESET_REG_2_XMAC); 1711 usleep_range(1000, 2000); 1712 1713 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 1714 MISC_REGISTERS_RESET_REG_2_XMAC); 1715 if (is_port4mode) { 1716 DP(NETIF_MSG_LINK, "Init XMAC to 2 ports x 10G per path\n"); 1717 1718 /* Set the number of ports on the system side to up to 2 */ 1719 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 1); 1720 1721 /* Set the number of ports on the Warp Core to 10G */ 1722 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3); 1723 } else { 1724 /* Set the number of ports on the system side to 1 */ 1725 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 0); 1726 if (max_speed == SPEED_10000) { 1727 DP(NETIF_MSG_LINK, 1728 "Init XMAC to 10G x 1 port per path\n"); 1729 /* Set the number of ports on the Warp Core to 10G */ 1730 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3); 1731 } else { 1732 DP(NETIF_MSG_LINK, 1733 "Init XMAC to 20G x 2 ports per path\n"); 1734 /* Set the number of ports on the Warp Core to 20G */ 1735 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 1); 1736 } 1737 } 1738 /* Soft reset */ 1739 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 1740 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT); 1741 usleep_range(1000, 2000); 1742 1743 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 1744 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT); 1745 1746 } 1747 1748 static void bnx2x_set_xmac_rxtx(struct link_params *params, u8 en) 1749 { 1750 u8 port = params->port; 1751 struct bnx2x *bp = params->bp; 1752 u32 pfc_ctrl, xmac_base = (port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; 1753 u32 val; 1754 1755 if (REG_RD(bp, MISC_REG_RESET_REG_2) & 1756 MISC_REGISTERS_RESET_REG_2_XMAC) { 1757 /* Send an indication to change the state in the NIG back to XON 1758 * Clearing this bit enables the next set of this bit to get 1759 * rising edge 1760 */ 1761 pfc_ctrl = REG_RD(bp, xmac_base + XMAC_REG_PFC_CTRL_HI); 1762 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, 1763 (pfc_ctrl & ~(1<<1))); 1764 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, 1765 (pfc_ctrl | (1<<1))); 1766 DP(NETIF_MSG_LINK, "Disable XMAC on port %x\n", port); 1767 val = REG_RD(bp, xmac_base + XMAC_REG_CTRL); 1768 if (en) 1769 val |= (XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN); 1770 else 1771 val &= ~(XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN); 1772 REG_WR(bp, xmac_base + XMAC_REG_CTRL, val); 1773 } 1774 } 1775 1776 static int bnx2x_xmac_enable(struct link_params *params, 1777 struct link_vars *vars, u8 lb) 1778 { 1779 u32 val, xmac_base; 1780 struct bnx2x *bp = params->bp; 1781 DP(NETIF_MSG_LINK, "enabling XMAC\n"); 1782 1783 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; 1784 1785 bnx2x_xmac_init(params, vars->line_speed); 1786 1787 /* This register determines on which events the MAC will assert 1788 * error on the i/f to the NIG along w/ EOP. 1789 */ 1790 1791 /* This register tells the NIG whether to send traffic to UMAC 1792 * or XMAC 1793 */ 1794 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 0); 1795 1796 /* When XMAC is in XLGMII mode, disable sending idles for fault 1797 * detection. 1798 */ 1799 if (!(params->phy[INT_PHY].flags & FLAGS_TX_ERROR_CHECK)) { 1800 REG_WR(bp, xmac_base + XMAC_REG_RX_LSS_CTRL, 1801 (XMAC_RX_LSS_CTRL_REG_LOCAL_FAULT_DISABLE | 1802 XMAC_RX_LSS_CTRL_REG_REMOTE_FAULT_DISABLE)); 1803 REG_WR(bp, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0); 1804 REG_WR(bp, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 1805 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS | 1806 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS); 1807 } 1808 /* Set Max packet size */ 1809 REG_WR(bp, xmac_base + XMAC_REG_RX_MAX_SIZE, 0x2710); 1810 1811 /* CRC append for Tx packets */ 1812 REG_WR(bp, xmac_base + XMAC_REG_TX_CTRL, 0xC800); 1813 1814 /* update PFC */ 1815 bnx2x_update_pfc_xmac(params, vars, 0); 1816 1817 if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) { 1818 DP(NETIF_MSG_LINK, "Setting XMAC for EEE\n"); 1819 REG_WR(bp, xmac_base + XMAC_REG_EEE_TIMERS_HI, 0x1380008); 1820 REG_WR(bp, xmac_base + XMAC_REG_EEE_CTRL, 0x1); 1821 } else { 1822 REG_WR(bp, xmac_base + XMAC_REG_EEE_CTRL, 0x0); 1823 } 1824 1825 /* Enable TX and RX */ 1826 val = XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN; 1827 1828 /* Set MAC in XLGMII mode for dual-mode */ 1829 if ((vars->line_speed == SPEED_20000) && 1830 (params->phy[INT_PHY].supported & 1831 SUPPORTED_20000baseKR2_Full)) 1832 val |= XMAC_CTRL_REG_XLGMII_ALIGN_ENB; 1833 1834 /* Check loopback mode */ 1835 if (lb) 1836 val |= XMAC_CTRL_REG_LINE_LOCAL_LPBK; 1837 REG_WR(bp, xmac_base + XMAC_REG_CTRL, val); 1838 bnx2x_set_xumac_nig(params, 1839 ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1); 1840 1841 vars->mac_type = MAC_TYPE_XMAC; 1842 1843 return 0; 1844 } 1845 1846 static int bnx2x_emac_enable(struct link_params *params, 1847 struct link_vars *vars, u8 lb) 1848 { 1849 struct bnx2x *bp = params->bp; 1850 u8 port = params->port; 1851 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; 1852 u32 val; 1853 1854 DP(NETIF_MSG_LINK, "enabling EMAC\n"); 1855 1856 /* Disable BMAC */ 1857 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 1858 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); 1859 1860 /* enable emac and not bmac */ 1861 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 1); 1862 1863 /* ASIC */ 1864 if (vars->phy_flags & PHY_XGXS_FLAG) { 1865 u32 ser_lane = ((params->lane_config & 1866 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >> 1867 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT); 1868 1869 DP(NETIF_MSG_LINK, "XGXS\n"); 1870 /* select the master lanes (out of 0-3) */ 1871 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, ser_lane); 1872 /* select XGXS */ 1873 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1); 1874 1875 } else { /* SerDes */ 1876 DP(NETIF_MSG_LINK, "SerDes\n"); 1877 /* select SerDes */ 1878 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0); 1879 } 1880 1881 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_RX_MODE, 1882 EMAC_RX_MODE_RESET); 1883 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE, 1884 EMAC_TX_MODE_RESET); 1885 1886 /* pause enable/disable */ 1887 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_RX_MODE, 1888 EMAC_RX_MODE_FLOW_EN); 1889 1890 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_TX_MODE, 1891 (EMAC_TX_MODE_EXT_PAUSE_EN | 1892 EMAC_TX_MODE_FLOW_EN)); 1893 if (!(params->feature_config_flags & 1894 FEATURE_CONFIG_PFC_ENABLED)) { 1895 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX) 1896 bnx2x_bits_en(bp, emac_base + 1897 EMAC_REG_EMAC_RX_MODE, 1898 EMAC_RX_MODE_FLOW_EN); 1899 1900 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) 1901 bnx2x_bits_en(bp, emac_base + 1902 EMAC_REG_EMAC_TX_MODE, 1903 (EMAC_TX_MODE_EXT_PAUSE_EN | 1904 EMAC_TX_MODE_FLOW_EN)); 1905 } else 1906 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE, 1907 EMAC_TX_MODE_FLOW_EN); 1908 1909 /* KEEP_VLAN_TAG, promiscuous */ 1910 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE); 1911 val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS; 1912 1913 /* Setting this bit causes MAC control frames (except for pause 1914 * frames) to be passed on for processing. This setting has no 1915 * affect on the operation of the pause frames. This bit effects 1916 * all packets regardless of RX Parser packet sorting logic. 1917 * Turn the PFC off to make sure we are in Xon state before 1918 * enabling it. 1919 */ 1920 EMAC_WR(bp, EMAC_REG_RX_PFC_MODE, 0); 1921 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) { 1922 DP(NETIF_MSG_LINK, "PFC is enabled\n"); 1923 /* Enable PFC again */ 1924 EMAC_WR(bp, EMAC_REG_RX_PFC_MODE, 1925 EMAC_REG_RX_PFC_MODE_RX_EN | 1926 EMAC_REG_RX_PFC_MODE_TX_EN | 1927 EMAC_REG_RX_PFC_MODE_PRIORITIES); 1928 1929 EMAC_WR(bp, EMAC_REG_RX_PFC_PARAM, 1930 ((0x0101 << 1931 EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT) | 1932 (0x00ff << 1933 EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT))); 1934 val |= EMAC_RX_MODE_KEEP_MAC_CONTROL; 1935 } 1936 EMAC_WR(bp, EMAC_REG_EMAC_RX_MODE, val); 1937 1938 /* Set Loopback */ 1939 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE); 1940 if (lb) 1941 val |= 0x810; 1942 else 1943 val &= ~0x810; 1944 EMAC_WR(bp, EMAC_REG_EMAC_MODE, val); 1945 1946 /* Enable emac */ 1947 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 1); 1948 1949 /* Enable emac for jumbo packets */ 1950 EMAC_WR(bp, EMAC_REG_EMAC_RX_MTU_SIZE, 1951 (EMAC_RX_MTU_SIZE_JUMBO_ENA | 1952 (ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD))); 1953 1954 /* Strip CRC */ 1955 REG_WR(bp, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1); 1956 1957 /* Disable the NIG in/out to the bmac */ 1958 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x0); 1959 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0); 1960 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x0); 1961 1962 /* Enable the NIG in/out to the emac */ 1963 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x1); 1964 val = 0; 1965 if ((params->feature_config_flags & 1966 FEATURE_CONFIG_PFC_ENABLED) || 1967 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)) 1968 val = 1; 1969 1970 REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val); 1971 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1); 1972 1973 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x0); 1974 1975 vars->mac_type = MAC_TYPE_EMAC; 1976 return 0; 1977 } 1978 1979 static void bnx2x_update_pfc_bmac1(struct link_params *params, 1980 struct link_vars *vars) 1981 { 1982 u32 wb_data[2]; 1983 struct bnx2x *bp = params->bp; 1984 u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM : 1985 NIG_REG_INGRESS_BMAC0_MEM; 1986 1987 u32 val = 0x14; 1988 if ((!(params->feature_config_flags & 1989 FEATURE_CONFIG_PFC_ENABLED)) && 1990 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)) 1991 /* Enable BigMAC to react on received Pause packets */ 1992 val |= (1<<5); 1993 wb_data[0] = val; 1994 wb_data[1] = 0; 1995 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_CONTROL, wb_data, 2); 1996 1997 /* TX control */ 1998 val = 0xc0; 1999 if (!(params->feature_config_flags & 2000 FEATURE_CONFIG_PFC_ENABLED) && 2001 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)) 2002 val |= 0x800000; 2003 wb_data[0] = val; 2004 wb_data[1] = 0; 2005 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_CONTROL, wb_data, 2); 2006 } 2007 2008 static void bnx2x_update_pfc_bmac2(struct link_params *params, 2009 struct link_vars *vars, 2010 u8 is_lb) 2011 { 2012 /* Set rx control: Strip CRC and enable BigMAC to relay 2013 * control packets to the system as well 2014 */ 2015 u32 wb_data[2]; 2016 struct bnx2x *bp = params->bp; 2017 u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM : 2018 NIG_REG_INGRESS_BMAC0_MEM; 2019 u32 val = 0x14; 2020 2021 if ((!(params->feature_config_flags & 2022 FEATURE_CONFIG_PFC_ENABLED)) && 2023 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)) 2024 /* Enable BigMAC to react on received Pause packets */ 2025 val |= (1<<5); 2026 wb_data[0] = val; 2027 wb_data[1] = 0; 2028 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_CONTROL, wb_data, 2); 2029 udelay(30); 2030 2031 /* Tx control */ 2032 val = 0xc0; 2033 if (!(params->feature_config_flags & 2034 FEATURE_CONFIG_PFC_ENABLED) && 2035 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)) 2036 val |= 0x800000; 2037 wb_data[0] = val; 2038 wb_data[1] = 0; 2039 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_CONTROL, wb_data, 2); 2040 2041 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) { 2042 DP(NETIF_MSG_LINK, "PFC is enabled\n"); 2043 /* Enable PFC RX & TX & STATS and set 8 COS */ 2044 wb_data[0] = 0x0; 2045 wb_data[0] |= (1<<0); /* RX */ 2046 wb_data[0] |= (1<<1); /* TX */ 2047 wb_data[0] |= (1<<2); /* Force initial Xon */ 2048 wb_data[0] |= (1<<3); /* 8 cos */ 2049 wb_data[0] |= (1<<5); /* STATS */ 2050 wb_data[1] = 0; 2051 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, 2052 wb_data, 2); 2053 /* Clear the force Xon */ 2054 wb_data[0] &= ~(1<<2); 2055 } else { 2056 DP(NETIF_MSG_LINK, "PFC is disabled\n"); 2057 /* Disable PFC RX & TX & STATS and set 8 COS */ 2058 wb_data[0] = 0x8; 2059 wb_data[1] = 0; 2060 } 2061 2062 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, wb_data, 2); 2063 2064 /* Set Time (based unit is 512 bit time) between automatic 2065 * re-sending of PP packets amd enable automatic re-send of 2066 * Per-Priroity Packet as long as pp_gen is asserted and 2067 * pp_disable is low. 2068 */ 2069 val = 0x8000; 2070 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) 2071 val |= (1<<16); /* enable automatic re-send */ 2072 2073 wb_data[0] = val; 2074 wb_data[1] = 0; 2075 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_PAUSE_CONTROL, 2076 wb_data, 2); 2077 2078 /* mac control */ 2079 val = 0x3; /* Enable RX and TX */ 2080 if (is_lb) { 2081 val |= 0x4; /* Local loopback */ 2082 DP(NETIF_MSG_LINK, "enable bmac loopback\n"); 2083 } 2084 /* When PFC enabled, Pass pause frames towards the NIG. */ 2085 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) 2086 val |= ((1<<6)|(1<<5)); 2087 2088 wb_data[0] = val; 2089 wb_data[1] = 0; 2090 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2); 2091 } 2092 2093 /****************************************************************************** 2094 * Description: 2095 * This function is needed because NIG ARB_CREDIT_WEIGHT_X are 2096 * not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable. 2097 ******************************************************************************/ 2098 static int bnx2x_pfc_nig_rx_priority_mask(struct bnx2x *bp, 2099 u8 cos_entry, 2100 u32 priority_mask, u8 port) 2101 { 2102 u32 nig_reg_rx_priority_mask_add = 0; 2103 2104 switch (cos_entry) { 2105 case 0: 2106 nig_reg_rx_priority_mask_add = (port) ? 2107 NIG_REG_P1_RX_COS0_PRIORITY_MASK : 2108 NIG_REG_P0_RX_COS0_PRIORITY_MASK; 2109 break; 2110 case 1: 2111 nig_reg_rx_priority_mask_add = (port) ? 2112 NIG_REG_P1_RX_COS1_PRIORITY_MASK : 2113 NIG_REG_P0_RX_COS1_PRIORITY_MASK; 2114 break; 2115 case 2: 2116 nig_reg_rx_priority_mask_add = (port) ? 2117 NIG_REG_P1_RX_COS2_PRIORITY_MASK : 2118 NIG_REG_P0_RX_COS2_PRIORITY_MASK; 2119 break; 2120 case 3: 2121 if (port) 2122 return -EINVAL; 2123 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS3_PRIORITY_MASK; 2124 break; 2125 case 4: 2126 if (port) 2127 return -EINVAL; 2128 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS4_PRIORITY_MASK; 2129 break; 2130 case 5: 2131 if (port) 2132 return -EINVAL; 2133 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS5_PRIORITY_MASK; 2134 break; 2135 } 2136 2137 REG_WR(bp, nig_reg_rx_priority_mask_add, priority_mask); 2138 2139 return 0; 2140 } 2141 static void bnx2x_update_mng(struct link_params *params, u32 link_status) 2142 { 2143 struct bnx2x *bp = params->bp; 2144 2145 REG_WR(bp, params->shmem_base + 2146 offsetof(struct shmem_region, 2147 port_mb[params->port].link_status), link_status); 2148 } 2149 2150 static void bnx2x_update_link_attr(struct link_params *params, u32 link_attr) 2151 { 2152 struct bnx2x *bp = params->bp; 2153 2154 if (SHMEM2_HAS(bp, link_attr_sync)) 2155 REG_WR(bp, params->shmem2_base + 2156 offsetof(struct shmem2_region, 2157 link_attr_sync[params->port]), link_attr); 2158 } 2159 2160 static void bnx2x_update_pfc_nig(struct link_params *params, 2161 struct link_vars *vars, 2162 struct bnx2x_nig_brb_pfc_port_params *nig_params) 2163 { 2164 u32 xcm_mask = 0, ppp_enable = 0, pause_enable = 0, llfc_out_en = 0; 2165 u32 llfc_enable = 0, xcm_out_en = 0, hwpfc_enable = 0; 2166 u32 pkt_priority_to_cos = 0; 2167 struct bnx2x *bp = params->bp; 2168 u8 port = params->port; 2169 2170 int set_pfc = params->feature_config_flags & 2171 FEATURE_CONFIG_PFC_ENABLED; 2172 DP(NETIF_MSG_LINK, "updating pfc nig parameters\n"); 2173 2174 /* When NIG_LLH0_XCM_MASK_REG_LLHX_XCM_MASK_BCN bit is set 2175 * MAC control frames (that are not pause packets) 2176 * will be forwarded to the XCM. 2177 */ 2178 xcm_mask = REG_RD(bp, port ? NIG_REG_LLH1_XCM_MASK : 2179 NIG_REG_LLH0_XCM_MASK); 2180 /* NIG params will override non PFC params, since it's possible to 2181 * do transition from PFC to SAFC 2182 */ 2183 if (set_pfc) { 2184 pause_enable = 0; 2185 llfc_out_en = 0; 2186 llfc_enable = 0; 2187 if (CHIP_IS_E3(bp)) 2188 ppp_enable = 0; 2189 else 2190 ppp_enable = 1; 2191 xcm_mask &= ~(port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN : 2192 NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN); 2193 xcm_out_en = 0; 2194 hwpfc_enable = 1; 2195 } else { 2196 if (nig_params) { 2197 llfc_out_en = nig_params->llfc_out_en; 2198 llfc_enable = nig_params->llfc_enable; 2199 pause_enable = nig_params->pause_enable; 2200 } else /* Default non PFC mode - PAUSE */ 2201 pause_enable = 1; 2202 2203 xcm_mask |= (port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN : 2204 NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN); 2205 xcm_out_en = 1; 2206 } 2207 2208 if (CHIP_IS_E3(bp)) 2209 REG_WR(bp, port ? NIG_REG_BRB1_PAUSE_IN_EN : 2210 NIG_REG_BRB0_PAUSE_IN_EN, pause_enable); 2211 REG_WR(bp, port ? NIG_REG_LLFC_OUT_EN_1 : 2212 NIG_REG_LLFC_OUT_EN_0, llfc_out_en); 2213 REG_WR(bp, port ? NIG_REG_LLFC_ENABLE_1 : 2214 NIG_REG_LLFC_ENABLE_0, llfc_enable); 2215 REG_WR(bp, port ? NIG_REG_PAUSE_ENABLE_1 : 2216 NIG_REG_PAUSE_ENABLE_0, pause_enable); 2217 2218 REG_WR(bp, port ? NIG_REG_PPP_ENABLE_1 : 2219 NIG_REG_PPP_ENABLE_0, ppp_enable); 2220 2221 REG_WR(bp, port ? NIG_REG_LLH1_XCM_MASK : 2222 NIG_REG_LLH0_XCM_MASK, xcm_mask); 2223 2224 REG_WR(bp, port ? NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 : 2225 NIG_REG_LLFC_EGRESS_SRC_ENABLE_0, 0x7); 2226 2227 /* Output enable for RX_XCM # IF */ 2228 REG_WR(bp, port ? NIG_REG_XCM1_OUT_EN : 2229 NIG_REG_XCM0_OUT_EN, xcm_out_en); 2230 2231 /* HW PFC TX enable */ 2232 REG_WR(bp, port ? NIG_REG_P1_HWPFC_ENABLE : 2233 NIG_REG_P0_HWPFC_ENABLE, hwpfc_enable); 2234 2235 if (nig_params) { 2236 u8 i = 0; 2237 pkt_priority_to_cos = nig_params->pkt_priority_to_cos; 2238 2239 for (i = 0; i < nig_params->num_of_rx_cos_priority_mask; i++) 2240 bnx2x_pfc_nig_rx_priority_mask(bp, i, 2241 nig_params->rx_cos_priority_mask[i], port); 2242 2243 REG_WR(bp, port ? NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 : 2244 NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0, 2245 nig_params->llfc_high_priority_classes); 2246 2247 REG_WR(bp, port ? NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 : 2248 NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0, 2249 nig_params->llfc_low_priority_classes); 2250 } 2251 REG_WR(bp, port ? NIG_REG_P1_PKT_PRIORITY_TO_COS : 2252 NIG_REG_P0_PKT_PRIORITY_TO_COS, 2253 pkt_priority_to_cos); 2254 } 2255 2256 int bnx2x_update_pfc(struct link_params *params, 2257 struct link_vars *vars, 2258 struct bnx2x_nig_brb_pfc_port_params *pfc_params) 2259 { 2260 /* The PFC and pause are orthogonal to one another, meaning when 2261 * PFC is enabled, the pause are disabled, and when PFC is 2262 * disabled, pause are set according to the pause result. 2263 */ 2264 u32 val; 2265 struct bnx2x *bp = params->bp; 2266 int bnx2x_status = 0; 2267 u8 bmac_loopback = (params->loopback_mode == LOOPBACK_BMAC); 2268 2269 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) 2270 vars->link_status |= LINK_STATUS_PFC_ENABLED; 2271 else 2272 vars->link_status &= ~LINK_STATUS_PFC_ENABLED; 2273 2274 bnx2x_update_mng(params, vars->link_status); 2275 2276 /* Update NIG params */ 2277 bnx2x_update_pfc_nig(params, vars, pfc_params); 2278 2279 if (!vars->link_up) 2280 return bnx2x_status; 2281 2282 DP(NETIF_MSG_LINK, "About to update PFC in BMAC\n"); 2283 2284 if (CHIP_IS_E3(bp)) { 2285 if (vars->mac_type == MAC_TYPE_XMAC) 2286 bnx2x_update_pfc_xmac(params, vars, 0); 2287 } else { 2288 val = REG_RD(bp, MISC_REG_RESET_REG_2); 2289 if ((val & 2290 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port)) 2291 == 0) { 2292 DP(NETIF_MSG_LINK, "About to update PFC in EMAC\n"); 2293 bnx2x_emac_enable(params, vars, 0); 2294 return bnx2x_status; 2295 } 2296 if (CHIP_IS_E2(bp)) 2297 bnx2x_update_pfc_bmac2(params, vars, bmac_loopback); 2298 else 2299 bnx2x_update_pfc_bmac1(params, vars); 2300 2301 val = 0; 2302 if ((params->feature_config_flags & 2303 FEATURE_CONFIG_PFC_ENABLED) || 2304 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)) 2305 val = 1; 2306 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port*4, val); 2307 } 2308 return bnx2x_status; 2309 } 2310 2311 static int bnx2x_bmac1_enable(struct link_params *params, 2312 struct link_vars *vars, 2313 u8 is_lb) 2314 { 2315 struct bnx2x *bp = params->bp; 2316 u8 port = params->port; 2317 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM : 2318 NIG_REG_INGRESS_BMAC0_MEM; 2319 u32 wb_data[2]; 2320 u32 val; 2321 2322 DP(NETIF_MSG_LINK, "Enabling BigMAC1\n"); 2323 2324 /* XGXS control */ 2325 wb_data[0] = 0x3c; 2326 wb_data[1] = 0; 2327 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_XGXS_CONTROL, 2328 wb_data, 2); 2329 2330 /* TX MAC SA */ 2331 wb_data[0] = ((params->mac_addr[2] << 24) | 2332 (params->mac_addr[3] << 16) | 2333 (params->mac_addr[4] << 8) | 2334 params->mac_addr[5]); 2335 wb_data[1] = ((params->mac_addr[0] << 8) | 2336 params->mac_addr[1]); 2337 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR, wb_data, 2); 2338 2339 /* MAC control */ 2340 val = 0x3; 2341 if (is_lb) { 2342 val |= 0x4; 2343 DP(NETIF_MSG_LINK, "enable bmac loopback\n"); 2344 } 2345 wb_data[0] = val; 2346 wb_data[1] = 0; 2347 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL, wb_data, 2); 2348 2349 /* Set rx mtu */ 2350 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD; 2351 wb_data[1] = 0; 2352 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE, wb_data, 2); 2353 2354 bnx2x_update_pfc_bmac1(params, vars); 2355 2356 /* Set tx mtu */ 2357 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD; 2358 wb_data[1] = 0; 2359 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE, wb_data, 2); 2360 2361 /* Set cnt max size */ 2362 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD; 2363 wb_data[1] = 0; 2364 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE, wb_data, 2); 2365 2366 /* Configure SAFC */ 2367 wb_data[0] = 0x1000200; 2368 wb_data[1] = 0; 2369 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS, 2370 wb_data, 2); 2371 2372 return 0; 2373 } 2374 2375 static int bnx2x_bmac2_enable(struct link_params *params, 2376 struct link_vars *vars, 2377 u8 is_lb) 2378 { 2379 struct bnx2x *bp = params->bp; 2380 u8 port = params->port; 2381 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM : 2382 NIG_REG_INGRESS_BMAC0_MEM; 2383 u32 wb_data[2]; 2384 2385 DP(NETIF_MSG_LINK, "Enabling BigMAC2\n"); 2386 2387 wb_data[0] = 0; 2388 wb_data[1] = 0; 2389 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2); 2390 udelay(30); 2391 2392 /* XGXS control: Reset phy HW, MDIO registers, PHY PLL and BMAC */ 2393 wb_data[0] = 0x3c; 2394 wb_data[1] = 0; 2395 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_XGXS_CONTROL, 2396 wb_data, 2); 2397 2398 udelay(30); 2399 2400 /* TX MAC SA */ 2401 wb_data[0] = ((params->mac_addr[2] << 24) | 2402 (params->mac_addr[3] << 16) | 2403 (params->mac_addr[4] << 8) | 2404 params->mac_addr[5]); 2405 wb_data[1] = ((params->mac_addr[0] << 8) | 2406 params->mac_addr[1]); 2407 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_SOURCE_ADDR, 2408 wb_data, 2); 2409 2410 udelay(30); 2411 2412 /* Configure SAFC */ 2413 wb_data[0] = 0x1000200; 2414 wb_data[1] = 0; 2415 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS, 2416 wb_data, 2); 2417 udelay(30); 2418 2419 /* Set RX MTU */ 2420 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD; 2421 wb_data[1] = 0; 2422 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_MAX_SIZE, wb_data, 2); 2423 udelay(30); 2424 2425 /* Set TX MTU */ 2426 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD; 2427 wb_data[1] = 0; 2428 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_MAX_SIZE, wb_data, 2); 2429 udelay(30); 2430 /* Set cnt max size */ 2431 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD - 2; 2432 wb_data[1] = 0; 2433 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_CNT_MAX_SIZE, wb_data, 2); 2434 udelay(30); 2435 bnx2x_update_pfc_bmac2(params, vars, is_lb); 2436 2437 return 0; 2438 } 2439 2440 static int bnx2x_bmac_enable(struct link_params *params, 2441 struct link_vars *vars, 2442 u8 is_lb, u8 reset_bmac) 2443 { 2444 int rc = 0; 2445 u8 port = params->port; 2446 struct bnx2x *bp = params->bp; 2447 u32 val; 2448 /* Reset and unreset the BigMac */ 2449 if (reset_bmac) { 2450 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 2451 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); 2452 usleep_range(1000, 2000); 2453 } 2454 2455 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 2456 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); 2457 2458 /* Enable access for bmac registers */ 2459 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1); 2460 2461 /* Enable BMAC according to BMAC type*/ 2462 if (CHIP_IS_E2(bp)) 2463 rc = bnx2x_bmac2_enable(params, vars, is_lb); 2464 else 2465 rc = bnx2x_bmac1_enable(params, vars, is_lb); 2466 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1); 2467 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0); 2468 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0); 2469 val = 0; 2470 if ((params->feature_config_flags & 2471 FEATURE_CONFIG_PFC_ENABLED) || 2472 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)) 2473 val = 1; 2474 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val); 2475 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0); 2476 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x0); 2477 REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0); 2478 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x1); 2479 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x1); 2480 2481 vars->mac_type = MAC_TYPE_BMAC; 2482 return rc; 2483 } 2484 2485 static void bnx2x_set_bmac_rx(struct bnx2x *bp, u32 chip_id, u8 port, u8 en) 2486 { 2487 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM : 2488 NIG_REG_INGRESS_BMAC0_MEM; 2489 u32 wb_data[2]; 2490 u32 nig_bmac_enable = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4); 2491 2492 if (CHIP_IS_E2(bp)) 2493 bmac_addr += BIGMAC2_REGISTER_BMAC_CONTROL; 2494 else 2495 bmac_addr += BIGMAC_REGISTER_BMAC_CONTROL; 2496 /* Only if the bmac is out of reset */ 2497 if (REG_RD(bp, MISC_REG_RESET_REG_2) & 2498 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) && 2499 nig_bmac_enable) { 2500 /* Clear Rx Enable bit in BMAC_CONTROL register */ 2501 REG_RD_DMAE(bp, bmac_addr, wb_data, 2); 2502 if (en) 2503 wb_data[0] |= BMAC_CONTROL_RX_ENABLE; 2504 else 2505 wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE; 2506 REG_WR_DMAE(bp, bmac_addr, wb_data, 2); 2507 usleep_range(1000, 2000); 2508 } 2509 } 2510 2511 static int bnx2x_pbf_update(struct link_params *params, u32 flow_ctrl, 2512 u32 line_speed) 2513 { 2514 struct bnx2x *bp = params->bp; 2515 u8 port = params->port; 2516 u32 init_crd, crd; 2517 u32 count = 1000; 2518 2519 /* Disable port */ 2520 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1); 2521 2522 /* Wait for init credit */ 2523 init_crd = REG_RD(bp, PBF_REG_P0_INIT_CRD + port*4); 2524 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8); 2525 DP(NETIF_MSG_LINK, "init_crd 0x%x crd 0x%x\n", init_crd, crd); 2526 2527 while ((init_crd != crd) && count) { 2528 usleep_range(5000, 10000); 2529 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8); 2530 count--; 2531 } 2532 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8); 2533 if (init_crd != crd) { 2534 DP(NETIF_MSG_LINK, "BUG! init_crd 0x%x != crd 0x%x\n", 2535 init_crd, crd); 2536 return -EINVAL; 2537 } 2538 2539 if (flow_ctrl & BNX2X_FLOW_CTRL_RX || 2540 line_speed == SPEED_10 || 2541 line_speed == SPEED_100 || 2542 line_speed == SPEED_1000 || 2543 line_speed == SPEED_2500) { 2544 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 1); 2545 /* Update threshold */ 2546 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, 0); 2547 /* Update init credit */ 2548 init_crd = 778; /* (800-18-4) */ 2549 2550 } else { 2551 u32 thresh = (ETH_MAX_JUMBO_PACKET_SIZE + 2552 ETH_OVREHEAD)/16; 2553 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0); 2554 /* Update threshold */ 2555 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, thresh); 2556 /* Update init credit */ 2557 switch (line_speed) { 2558 case SPEED_10000: 2559 init_crd = thresh + 553 - 22; 2560 break; 2561 default: 2562 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n", 2563 line_speed); 2564 return -EINVAL; 2565 } 2566 } 2567 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, init_crd); 2568 DP(NETIF_MSG_LINK, "PBF updated to speed %d credit %d\n", 2569 line_speed, init_crd); 2570 2571 /* Probe the credit changes */ 2572 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x1); 2573 usleep_range(5000, 10000); 2574 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x0); 2575 2576 /* Enable port */ 2577 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0); 2578 return 0; 2579 } 2580 2581 /** 2582 * bnx2x_get_emac_base - retrive emac base address 2583 * 2584 * @bp: driver handle 2585 * @mdc_mdio_access: access type 2586 * @port: port id 2587 * 2588 * This function selects the MDC/MDIO access (through emac0 or 2589 * emac1) depend on the mdc_mdio_access, port, port swapped. Each 2590 * phy has a default access mode, which could also be overridden 2591 * by nvram configuration. This parameter, whether this is the 2592 * default phy configuration, or the nvram overrun 2593 * configuration, is passed here as mdc_mdio_access and selects 2594 * the emac_base for the CL45 read/writes operations 2595 */ 2596 static u32 bnx2x_get_emac_base(struct bnx2x *bp, 2597 u32 mdc_mdio_access, u8 port) 2598 { 2599 u32 emac_base = 0; 2600 switch (mdc_mdio_access) { 2601 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE: 2602 break; 2603 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0: 2604 if (REG_RD(bp, NIG_REG_PORT_SWAP)) 2605 emac_base = GRCBASE_EMAC1; 2606 else 2607 emac_base = GRCBASE_EMAC0; 2608 break; 2609 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1: 2610 if (REG_RD(bp, NIG_REG_PORT_SWAP)) 2611 emac_base = GRCBASE_EMAC0; 2612 else 2613 emac_base = GRCBASE_EMAC1; 2614 break; 2615 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH: 2616 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0; 2617 break; 2618 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED: 2619 emac_base = (port) ? GRCBASE_EMAC0 : GRCBASE_EMAC1; 2620 break; 2621 default: 2622 break; 2623 } 2624 return emac_base; 2625 2626 } 2627 2628 /******************************************************************/ 2629 /* CL22 access functions */ 2630 /******************************************************************/ 2631 static int bnx2x_cl22_write(struct bnx2x *bp, 2632 struct bnx2x_phy *phy, 2633 u16 reg, u16 val) 2634 { 2635 u32 tmp, mode; 2636 u8 i; 2637 int rc = 0; 2638 /* Switch to CL22 */ 2639 mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE); 2640 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, 2641 mode & ~EMAC_MDIO_MODE_CLAUSE_45); 2642 2643 /* Address */ 2644 tmp = ((phy->addr << 21) | (reg << 16) | val | 2645 EMAC_MDIO_COMM_COMMAND_WRITE_22 | 2646 EMAC_MDIO_COMM_START_BUSY); 2647 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); 2648 2649 for (i = 0; i < 50; i++) { 2650 udelay(10); 2651 2652 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); 2653 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) { 2654 udelay(5); 2655 break; 2656 } 2657 } 2658 if (tmp & EMAC_MDIO_COMM_START_BUSY) { 2659 DP(NETIF_MSG_LINK, "write phy register failed\n"); 2660 rc = -EFAULT; 2661 } 2662 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode); 2663 return rc; 2664 } 2665 2666 static int bnx2x_cl22_read(struct bnx2x *bp, 2667 struct bnx2x_phy *phy, 2668 u16 reg, u16 *ret_val) 2669 { 2670 u32 val, mode; 2671 u16 i; 2672 int rc = 0; 2673 2674 /* Switch to CL22 */ 2675 mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE); 2676 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, 2677 mode & ~EMAC_MDIO_MODE_CLAUSE_45); 2678 2679 /* Address */ 2680 val = ((phy->addr << 21) | (reg << 16) | 2681 EMAC_MDIO_COMM_COMMAND_READ_22 | 2682 EMAC_MDIO_COMM_START_BUSY); 2683 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); 2684 2685 for (i = 0; i < 50; i++) { 2686 udelay(10); 2687 2688 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); 2689 if (!(val & EMAC_MDIO_COMM_START_BUSY)) { 2690 *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA); 2691 udelay(5); 2692 break; 2693 } 2694 } 2695 if (val & EMAC_MDIO_COMM_START_BUSY) { 2696 DP(NETIF_MSG_LINK, "read phy register failed\n"); 2697 2698 *ret_val = 0; 2699 rc = -EFAULT; 2700 } 2701 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode); 2702 return rc; 2703 } 2704 2705 /******************************************************************/ 2706 /* CL45 access functions */ 2707 /******************************************************************/ 2708 static int bnx2x_cl45_read(struct bnx2x *bp, struct bnx2x_phy *phy, 2709 u8 devad, u16 reg, u16 *ret_val) 2710 { 2711 u32 val; 2712 u16 i; 2713 int rc = 0; 2714 u32 chip_id; 2715 if (phy->flags & FLAGS_MDC_MDIO_WA_G) { 2716 chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) | 2717 ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12); 2718 bnx2x_set_mdio_clk(bp, chip_id, phy->mdio_ctrl); 2719 } 2720 2721 if (phy->flags & FLAGS_MDC_MDIO_WA_B0) 2722 bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, 2723 EMAC_MDIO_STATUS_10MB); 2724 /* Address */ 2725 val = ((phy->addr << 21) | (devad << 16) | reg | 2726 EMAC_MDIO_COMM_COMMAND_ADDRESS | 2727 EMAC_MDIO_COMM_START_BUSY); 2728 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); 2729 2730 for (i = 0; i < 50; i++) { 2731 udelay(10); 2732 2733 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); 2734 if (!(val & EMAC_MDIO_COMM_START_BUSY)) { 2735 udelay(5); 2736 break; 2737 } 2738 } 2739 if (val & EMAC_MDIO_COMM_START_BUSY) { 2740 DP(NETIF_MSG_LINK, "read phy register failed\n"); 2741 netdev_err(bp->dev, "MDC/MDIO access timeout\n"); 2742 *ret_val = 0; 2743 rc = -EFAULT; 2744 } else { 2745 /* Data */ 2746 val = ((phy->addr << 21) | (devad << 16) | 2747 EMAC_MDIO_COMM_COMMAND_READ_45 | 2748 EMAC_MDIO_COMM_START_BUSY); 2749 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); 2750 2751 for (i = 0; i < 50; i++) { 2752 udelay(10); 2753 2754 val = REG_RD(bp, phy->mdio_ctrl + 2755 EMAC_REG_EMAC_MDIO_COMM); 2756 if (!(val & EMAC_MDIO_COMM_START_BUSY)) { 2757 *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA); 2758 break; 2759 } 2760 } 2761 if (val & EMAC_MDIO_COMM_START_BUSY) { 2762 DP(NETIF_MSG_LINK, "read phy register failed\n"); 2763 netdev_err(bp->dev, "MDC/MDIO access timeout\n"); 2764 *ret_val = 0; 2765 rc = -EFAULT; 2766 } 2767 } 2768 /* Work around for E3 A0 */ 2769 if (phy->flags & FLAGS_MDC_MDIO_WA) { 2770 phy->flags ^= FLAGS_DUMMY_READ; 2771 if (phy->flags & FLAGS_DUMMY_READ) { 2772 u16 temp_val; 2773 bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val); 2774 } 2775 } 2776 2777 if (phy->flags & FLAGS_MDC_MDIO_WA_B0) 2778 bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, 2779 EMAC_MDIO_STATUS_10MB); 2780 return rc; 2781 } 2782 2783 static int bnx2x_cl45_write(struct bnx2x *bp, struct bnx2x_phy *phy, 2784 u8 devad, u16 reg, u16 val) 2785 { 2786 u32 tmp; 2787 u8 i; 2788 int rc = 0; 2789 u32 chip_id; 2790 if (phy->flags & FLAGS_MDC_MDIO_WA_G) { 2791 chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) | 2792 ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12); 2793 bnx2x_set_mdio_clk(bp, chip_id, phy->mdio_ctrl); 2794 } 2795 2796 if (phy->flags & FLAGS_MDC_MDIO_WA_B0) 2797 bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, 2798 EMAC_MDIO_STATUS_10MB); 2799 2800 /* Address */ 2801 tmp = ((phy->addr << 21) | (devad << 16) | reg | 2802 EMAC_MDIO_COMM_COMMAND_ADDRESS | 2803 EMAC_MDIO_COMM_START_BUSY); 2804 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); 2805 2806 for (i = 0; i < 50; i++) { 2807 udelay(10); 2808 2809 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); 2810 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) { 2811 udelay(5); 2812 break; 2813 } 2814 } 2815 if (tmp & EMAC_MDIO_COMM_START_BUSY) { 2816 DP(NETIF_MSG_LINK, "write phy register failed\n"); 2817 netdev_err(bp->dev, "MDC/MDIO access timeout\n"); 2818 rc = -EFAULT; 2819 } else { 2820 /* Data */ 2821 tmp = ((phy->addr << 21) | (devad << 16) | val | 2822 EMAC_MDIO_COMM_COMMAND_WRITE_45 | 2823 EMAC_MDIO_COMM_START_BUSY); 2824 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); 2825 2826 for (i = 0; i < 50; i++) { 2827 udelay(10); 2828 2829 tmp = REG_RD(bp, phy->mdio_ctrl + 2830 EMAC_REG_EMAC_MDIO_COMM); 2831 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) { 2832 udelay(5); 2833 break; 2834 } 2835 } 2836 if (tmp & EMAC_MDIO_COMM_START_BUSY) { 2837 DP(NETIF_MSG_LINK, "write phy register failed\n"); 2838 netdev_err(bp->dev, "MDC/MDIO access timeout\n"); 2839 rc = -EFAULT; 2840 } 2841 } 2842 /* Work around for E3 A0 */ 2843 if (phy->flags & FLAGS_MDC_MDIO_WA) { 2844 phy->flags ^= FLAGS_DUMMY_READ; 2845 if (phy->flags & FLAGS_DUMMY_READ) { 2846 u16 temp_val; 2847 bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val); 2848 } 2849 } 2850 if (phy->flags & FLAGS_MDC_MDIO_WA_B0) 2851 bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, 2852 EMAC_MDIO_STATUS_10MB); 2853 return rc; 2854 } 2855 2856 /******************************************************************/ 2857 /* EEE section */ 2858 /******************************************************************/ 2859 static u8 bnx2x_eee_has_cap(struct link_params *params) 2860 { 2861 struct bnx2x *bp = params->bp; 2862 2863 if (REG_RD(bp, params->shmem2_base) <= 2864 offsetof(struct shmem2_region, eee_status[params->port])) 2865 return 0; 2866 2867 return 1; 2868 } 2869 2870 static int bnx2x_eee_nvram_to_time(u32 nvram_mode, u32 *idle_timer) 2871 { 2872 switch (nvram_mode) { 2873 case PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED: 2874 *idle_timer = EEE_MODE_NVRAM_BALANCED_TIME; 2875 break; 2876 case PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE: 2877 *idle_timer = EEE_MODE_NVRAM_AGGRESSIVE_TIME; 2878 break; 2879 case PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY: 2880 *idle_timer = EEE_MODE_NVRAM_LATENCY_TIME; 2881 break; 2882 default: 2883 *idle_timer = 0; 2884 break; 2885 } 2886 2887 return 0; 2888 } 2889 2890 static int bnx2x_eee_time_to_nvram(u32 idle_timer, u32 *nvram_mode) 2891 { 2892 switch (idle_timer) { 2893 case EEE_MODE_NVRAM_BALANCED_TIME: 2894 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED; 2895 break; 2896 case EEE_MODE_NVRAM_AGGRESSIVE_TIME: 2897 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE; 2898 break; 2899 case EEE_MODE_NVRAM_LATENCY_TIME: 2900 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY; 2901 break; 2902 default: 2903 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED; 2904 break; 2905 } 2906 2907 return 0; 2908 } 2909 2910 static u32 bnx2x_eee_calc_timer(struct link_params *params) 2911 { 2912 u32 eee_mode, eee_idle; 2913 struct bnx2x *bp = params->bp; 2914 2915 if (params->eee_mode & EEE_MODE_OVERRIDE_NVRAM) { 2916 if (params->eee_mode & EEE_MODE_OUTPUT_TIME) { 2917 /* time value in eee_mode --> used directly*/ 2918 eee_idle = params->eee_mode & EEE_MODE_TIMER_MASK; 2919 } else { 2920 /* hsi value in eee_mode --> time */ 2921 if (bnx2x_eee_nvram_to_time(params->eee_mode & 2922 EEE_MODE_NVRAM_MASK, 2923 &eee_idle)) 2924 return 0; 2925 } 2926 } else { 2927 /* hsi values in nvram --> time*/ 2928 eee_mode = ((REG_RD(bp, params->shmem_base + 2929 offsetof(struct shmem_region, dev_info. 2930 port_feature_config[params->port]. 2931 eee_power_mode)) & 2932 PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >> 2933 PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT); 2934 2935 if (bnx2x_eee_nvram_to_time(eee_mode, &eee_idle)) 2936 return 0; 2937 } 2938 2939 return eee_idle; 2940 } 2941 2942 static int bnx2x_eee_set_timers(struct link_params *params, 2943 struct link_vars *vars) 2944 { 2945 u32 eee_idle = 0, eee_mode; 2946 struct bnx2x *bp = params->bp; 2947 2948 eee_idle = bnx2x_eee_calc_timer(params); 2949 2950 if (eee_idle) { 2951 REG_WR(bp, MISC_REG_CPMU_LP_IDLE_THR_P0 + (params->port << 2), 2952 eee_idle); 2953 } else if ((params->eee_mode & EEE_MODE_ENABLE_LPI) && 2954 (params->eee_mode & EEE_MODE_OVERRIDE_NVRAM) && 2955 (params->eee_mode & EEE_MODE_OUTPUT_TIME)) { 2956 DP(NETIF_MSG_LINK, "Error: Tx LPI is enabled with timer 0\n"); 2957 return -EINVAL; 2958 } 2959 2960 vars->eee_status &= ~(SHMEM_EEE_TIMER_MASK | SHMEM_EEE_TIME_OUTPUT_BIT); 2961 if (params->eee_mode & EEE_MODE_OUTPUT_TIME) { 2962 /* eee_idle in 1u --> eee_status in 16u */ 2963 eee_idle >>= 4; 2964 vars->eee_status |= (eee_idle & SHMEM_EEE_TIMER_MASK) | 2965 SHMEM_EEE_TIME_OUTPUT_BIT; 2966 } else { 2967 if (bnx2x_eee_time_to_nvram(eee_idle, &eee_mode)) 2968 return -EINVAL; 2969 vars->eee_status |= eee_mode; 2970 } 2971 2972 return 0; 2973 } 2974 2975 static int bnx2x_eee_initial_config(struct link_params *params, 2976 struct link_vars *vars, u8 mode) 2977 { 2978 vars->eee_status |= ((u32) mode) << SHMEM_EEE_SUPPORTED_SHIFT; 2979 2980 /* Propogate params' bits --> vars (for migration exposure) */ 2981 if (params->eee_mode & EEE_MODE_ENABLE_LPI) 2982 vars->eee_status |= SHMEM_EEE_LPI_REQUESTED_BIT; 2983 else 2984 vars->eee_status &= ~SHMEM_EEE_LPI_REQUESTED_BIT; 2985 2986 if (params->eee_mode & EEE_MODE_ADV_LPI) 2987 vars->eee_status |= SHMEM_EEE_REQUESTED_BIT; 2988 else 2989 vars->eee_status &= ~SHMEM_EEE_REQUESTED_BIT; 2990 2991 return bnx2x_eee_set_timers(params, vars); 2992 } 2993 2994 static int bnx2x_eee_disable(struct bnx2x_phy *phy, 2995 struct link_params *params, 2996 struct link_vars *vars) 2997 { 2998 struct bnx2x *bp = params->bp; 2999 3000 /* Make Certain LPI is disabled */ 3001 REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2), 0); 3002 3003 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, 0x0); 3004 3005 vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK; 3006 3007 return 0; 3008 } 3009 3010 static int bnx2x_eee_advertise(struct bnx2x_phy *phy, 3011 struct link_params *params, 3012 struct link_vars *vars, u8 modes) 3013 { 3014 struct bnx2x *bp = params->bp; 3015 u16 val = 0; 3016 3017 /* Mask events preventing LPI generation */ 3018 REG_WR(bp, MISC_REG_CPMU_LP_MASK_EXT_P0 + (params->port << 2), 0xfc20); 3019 3020 if (modes & SHMEM_EEE_10G_ADV) { 3021 DP(NETIF_MSG_LINK, "Advertise 10GBase-T EEE\n"); 3022 val |= 0x8; 3023 } 3024 if (modes & SHMEM_EEE_1G_ADV) { 3025 DP(NETIF_MSG_LINK, "Advertise 1GBase-T EEE\n"); 3026 val |= 0x4; 3027 } 3028 3029 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, val); 3030 3031 vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK; 3032 vars->eee_status |= (modes << SHMEM_EEE_ADV_STATUS_SHIFT); 3033 3034 return 0; 3035 } 3036 3037 static void bnx2x_update_mng_eee(struct link_params *params, u32 eee_status) 3038 { 3039 struct bnx2x *bp = params->bp; 3040 3041 if (bnx2x_eee_has_cap(params)) 3042 REG_WR(bp, params->shmem2_base + 3043 offsetof(struct shmem2_region, 3044 eee_status[params->port]), eee_status); 3045 } 3046 3047 static void bnx2x_eee_an_resolve(struct bnx2x_phy *phy, 3048 struct link_params *params, 3049 struct link_vars *vars) 3050 { 3051 struct bnx2x *bp = params->bp; 3052 u16 adv = 0, lp = 0; 3053 u32 lp_adv = 0; 3054 u8 neg = 0; 3055 3056 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, &adv); 3057 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_LP_EEE_ADV, &lp); 3058 3059 if (lp & 0x2) { 3060 lp_adv |= SHMEM_EEE_100M_ADV; 3061 if (adv & 0x2) { 3062 if (vars->line_speed == SPEED_100) 3063 neg = 1; 3064 DP(NETIF_MSG_LINK, "EEE negotiated - 100M\n"); 3065 } 3066 } 3067 if (lp & 0x14) { 3068 lp_adv |= SHMEM_EEE_1G_ADV; 3069 if (adv & 0x14) { 3070 if (vars->line_speed == SPEED_1000) 3071 neg = 1; 3072 DP(NETIF_MSG_LINK, "EEE negotiated - 1G\n"); 3073 } 3074 } 3075 if (lp & 0x68) { 3076 lp_adv |= SHMEM_EEE_10G_ADV; 3077 if (adv & 0x68) { 3078 if (vars->line_speed == SPEED_10000) 3079 neg = 1; 3080 DP(NETIF_MSG_LINK, "EEE negotiated - 10G\n"); 3081 } 3082 } 3083 3084 vars->eee_status &= ~SHMEM_EEE_LP_ADV_STATUS_MASK; 3085 vars->eee_status |= (lp_adv << SHMEM_EEE_LP_ADV_STATUS_SHIFT); 3086 3087 if (neg) { 3088 DP(NETIF_MSG_LINK, "EEE is active\n"); 3089 vars->eee_status |= SHMEM_EEE_ACTIVE_BIT; 3090 } 3091 3092 } 3093 3094 /******************************************************************/ 3095 /* BSC access functions from E3 */ 3096 /******************************************************************/ 3097 static void bnx2x_bsc_module_sel(struct link_params *params) 3098 { 3099 int idx; 3100 u32 board_cfg, sfp_ctrl; 3101 u32 i2c_pins[I2C_SWITCH_WIDTH], i2c_val[I2C_SWITCH_WIDTH]; 3102 struct bnx2x *bp = params->bp; 3103 u8 port = params->port; 3104 /* Read I2C output PINs */ 3105 board_cfg = REG_RD(bp, params->shmem_base + 3106 offsetof(struct shmem_region, 3107 dev_info.shared_hw_config.board)); 3108 i2c_pins[I2C_BSC0] = board_cfg & SHARED_HW_CFG_E3_I2C_MUX0_MASK; 3109 i2c_pins[I2C_BSC1] = (board_cfg & SHARED_HW_CFG_E3_I2C_MUX1_MASK) >> 3110 SHARED_HW_CFG_E3_I2C_MUX1_SHIFT; 3111 3112 /* Read I2C output value */ 3113 sfp_ctrl = REG_RD(bp, params->shmem_base + 3114 offsetof(struct shmem_region, 3115 dev_info.port_hw_config[port].e3_cmn_pin_cfg)); 3116 i2c_val[I2C_BSC0] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX0_MASK) > 0; 3117 i2c_val[I2C_BSC1] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX1_MASK) > 0; 3118 DP(NETIF_MSG_LINK, "Setting BSC switch\n"); 3119 for (idx = 0; idx < I2C_SWITCH_WIDTH; idx++) 3120 bnx2x_set_cfg_pin(bp, i2c_pins[idx], i2c_val[idx]); 3121 } 3122 3123 static int bnx2x_bsc_read(struct link_params *params, 3124 struct bnx2x_phy *phy, 3125 u8 sl_devid, 3126 u16 sl_addr, 3127 u8 lc_addr, 3128 u8 xfer_cnt, 3129 u32 *data_array) 3130 { 3131 u32 val, i; 3132 int rc = 0; 3133 struct bnx2x *bp = params->bp; 3134 3135 if (xfer_cnt > 16) { 3136 DP(NETIF_MSG_LINK, "invalid xfer_cnt %d. Max is 16 bytes\n", 3137 xfer_cnt); 3138 return -EINVAL; 3139 } 3140 bnx2x_bsc_module_sel(params); 3141 3142 xfer_cnt = 16 - lc_addr; 3143 3144 /* Enable the engine */ 3145 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND); 3146 val |= MCPR_IMC_COMMAND_ENABLE; 3147 REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val); 3148 3149 /* Program slave device ID */ 3150 val = (sl_devid << 16) | sl_addr; 3151 REG_WR(bp, MCP_REG_MCPR_IMC_SLAVE_CONTROL, val); 3152 3153 /* Start xfer with 0 byte to update the address pointer ???*/ 3154 val = (MCPR_IMC_COMMAND_ENABLE) | 3155 (MCPR_IMC_COMMAND_WRITE_OP << 3156 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) | 3157 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) | (0); 3158 REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val); 3159 3160 /* Poll for completion */ 3161 i = 0; 3162 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND); 3163 while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) { 3164 udelay(10); 3165 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND); 3166 if (i++ > 1000) { 3167 DP(NETIF_MSG_LINK, "wr 0 byte timed out after %d try\n", 3168 i); 3169 rc = -EFAULT; 3170 break; 3171 } 3172 } 3173 if (rc == -EFAULT) 3174 return rc; 3175 3176 /* Start xfer with read op */ 3177 val = (MCPR_IMC_COMMAND_ENABLE) | 3178 (MCPR_IMC_COMMAND_READ_OP << 3179 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) | 3180 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) | 3181 (xfer_cnt); 3182 REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val); 3183 3184 /* Poll for completion */ 3185 i = 0; 3186 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND); 3187 while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) { 3188 udelay(10); 3189 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND); 3190 if (i++ > 1000) { 3191 DP(NETIF_MSG_LINK, "rd op timed out after %d try\n", i); 3192 rc = -EFAULT; 3193 break; 3194 } 3195 } 3196 if (rc == -EFAULT) 3197 return rc; 3198 3199 for (i = (lc_addr >> 2); i < 4; i++) { 3200 data_array[i] = REG_RD(bp, (MCP_REG_MCPR_IMC_DATAREG0 + i*4)); 3201 #ifdef __BIG_ENDIAN 3202 data_array[i] = ((data_array[i] & 0x000000ff) << 24) | 3203 ((data_array[i] & 0x0000ff00) << 8) | 3204 ((data_array[i] & 0x00ff0000) >> 8) | 3205 ((data_array[i] & 0xff000000) >> 24); 3206 #endif 3207 } 3208 return rc; 3209 } 3210 3211 static void bnx2x_cl45_read_or_write(struct bnx2x *bp, struct bnx2x_phy *phy, 3212 u8 devad, u16 reg, u16 or_val) 3213 { 3214 u16 val; 3215 bnx2x_cl45_read(bp, phy, devad, reg, &val); 3216 bnx2x_cl45_write(bp, phy, devad, reg, val | or_val); 3217 } 3218 3219 static void bnx2x_cl45_read_and_write(struct bnx2x *bp, 3220 struct bnx2x_phy *phy, 3221 u8 devad, u16 reg, u16 and_val) 3222 { 3223 u16 val; 3224 bnx2x_cl45_read(bp, phy, devad, reg, &val); 3225 bnx2x_cl45_write(bp, phy, devad, reg, val & and_val); 3226 } 3227 3228 int bnx2x_phy_read(struct link_params *params, u8 phy_addr, 3229 u8 devad, u16 reg, u16 *ret_val) 3230 { 3231 u8 phy_index; 3232 /* Probe for the phy according to the given phy_addr, and execute 3233 * the read request on it 3234 */ 3235 for (phy_index = 0; phy_index < params->num_phys; phy_index++) { 3236 if (params->phy[phy_index].addr == phy_addr) { 3237 return bnx2x_cl45_read(params->bp, 3238 ¶ms->phy[phy_index], devad, 3239 reg, ret_val); 3240 } 3241 } 3242 return -EINVAL; 3243 } 3244 3245 int bnx2x_phy_write(struct link_params *params, u8 phy_addr, 3246 u8 devad, u16 reg, u16 val) 3247 { 3248 u8 phy_index; 3249 /* Probe for the phy according to the given phy_addr, and execute 3250 * the write request on it 3251 */ 3252 for (phy_index = 0; phy_index < params->num_phys; phy_index++) { 3253 if (params->phy[phy_index].addr == phy_addr) { 3254 return bnx2x_cl45_write(params->bp, 3255 ¶ms->phy[phy_index], devad, 3256 reg, val); 3257 } 3258 } 3259 return -EINVAL; 3260 } 3261 static u8 bnx2x_get_warpcore_lane(struct bnx2x_phy *phy, 3262 struct link_params *params) 3263 { 3264 u8 lane = 0; 3265 struct bnx2x *bp = params->bp; 3266 u32 path_swap, path_swap_ovr; 3267 u8 path, port; 3268 3269 path = BP_PATH(bp); 3270 port = params->port; 3271 3272 if (bnx2x_is_4_port_mode(bp)) { 3273 u32 port_swap, port_swap_ovr; 3274 3275 /* Figure out path swap value */ 3276 path_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP_OVWR); 3277 if (path_swap_ovr & 0x1) 3278 path_swap = (path_swap_ovr & 0x2); 3279 else 3280 path_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP); 3281 3282 if (path_swap) 3283 path = path ^ 1; 3284 3285 /* Figure out port swap value */ 3286 port_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP_OVWR); 3287 if (port_swap_ovr & 0x1) 3288 port_swap = (port_swap_ovr & 0x2); 3289 else 3290 port_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP); 3291 3292 if (port_swap) 3293 port = port ^ 1; 3294 3295 lane = (port<<1) + path; 3296 } else { /* Two port mode - no port swap */ 3297 3298 /* Figure out path swap value */ 3299 path_swap_ovr = 3300 REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP_OVWR); 3301 if (path_swap_ovr & 0x1) { 3302 path_swap = (path_swap_ovr & 0x2); 3303 } else { 3304 path_swap = 3305 REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP); 3306 } 3307 if (path_swap) 3308 path = path ^ 1; 3309 3310 lane = path << 1 ; 3311 } 3312 return lane; 3313 } 3314 3315 static void bnx2x_set_aer_mmd(struct link_params *params, 3316 struct bnx2x_phy *phy) 3317 { 3318 u32 ser_lane; 3319 u16 offset, aer_val; 3320 struct bnx2x *bp = params->bp; 3321 ser_lane = ((params->lane_config & 3322 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >> 3323 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT); 3324 3325 offset = (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ? 3326 (phy->addr + ser_lane) : 0; 3327 3328 if (USES_WARPCORE(bp)) { 3329 aer_val = bnx2x_get_warpcore_lane(phy, params); 3330 /* In Dual-lane mode, two lanes are joined together, 3331 * so in order to configure them, the AER broadcast method is 3332 * used here. 3333 * 0x200 is the broadcast address for lanes 0,1 3334 * 0x201 is the broadcast address for lanes 2,3 3335 */ 3336 if (phy->flags & FLAGS_WC_DUAL_MODE) 3337 aer_val = (aer_val >> 1) | 0x200; 3338 } else if (CHIP_IS_E2(bp)) 3339 aer_val = 0x3800 + offset - 1; 3340 else 3341 aer_val = 0x3800 + offset; 3342 3343 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, 3344 MDIO_AER_BLOCK_AER_REG, aer_val); 3345 3346 } 3347 3348 /******************************************************************/ 3349 /* Internal phy section */ 3350 /******************************************************************/ 3351 3352 static void bnx2x_set_serdes_access(struct bnx2x *bp, u8 port) 3353 { 3354 u32 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0; 3355 3356 /* Set Clause 22 */ 3357 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 1); 3358 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000); 3359 udelay(500); 3360 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f); 3361 udelay(500); 3362 /* Set Clause 45 */ 3363 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 0); 3364 } 3365 3366 static void bnx2x_serdes_deassert(struct bnx2x *bp, u8 port) 3367 { 3368 u32 val; 3369 3370 DP(NETIF_MSG_LINK, "bnx2x_serdes_deassert\n"); 3371 3372 val = SERDES_RESET_BITS << (port*16); 3373 3374 /* Reset and unreset the SerDes/XGXS */ 3375 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val); 3376 udelay(500); 3377 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val); 3378 3379 bnx2x_set_serdes_access(bp, port); 3380 3381 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_DEVAD + port*0x10, 3382 DEFAULT_PHY_DEV_ADDR); 3383 } 3384 3385 static void bnx2x_xgxs_specific_func(struct bnx2x_phy *phy, 3386 struct link_params *params, 3387 u32 action) 3388 { 3389 struct bnx2x *bp = params->bp; 3390 switch (action) { 3391 case PHY_INIT: 3392 /* Set correct devad */ 3393 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_ST + params->port*0x18, 0); 3394 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + params->port*0x18, 3395 phy->def_md_devad); 3396 break; 3397 } 3398 } 3399 3400 static void bnx2x_xgxs_deassert(struct link_params *params) 3401 { 3402 struct bnx2x *bp = params->bp; 3403 u8 port; 3404 u32 val; 3405 DP(NETIF_MSG_LINK, "bnx2x_xgxs_deassert\n"); 3406 port = params->port; 3407 3408 val = XGXS_RESET_BITS << (port*16); 3409 3410 /* Reset and unreset the SerDes/XGXS */ 3411 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val); 3412 udelay(500); 3413 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val); 3414 bnx2x_xgxs_specific_func(¶ms->phy[INT_PHY], params, 3415 PHY_INIT); 3416 } 3417 3418 static void bnx2x_calc_ieee_aneg_adv(struct bnx2x_phy *phy, 3419 struct link_params *params, u16 *ieee_fc) 3420 { 3421 struct bnx2x *bp = params->bp; 3422 *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX; 3423 /* Resolve pause mode and advertisement Please refer to Table 3424 * 28B-3 of the 802.3ab-1999 spec 3425 */ 3426 3427 switch (phy->req_flow_ctrl) { 3428 case BNX2X_FLOW_CTRL_AUTO: 3429 switch (params->req_fc_auto_adv) { 3430 case BNX2X_FLOW_CTRL_BOTH: 3431 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; 3432 break; 3433 case BNX2X_FLOW_CTRL_RX: 3434 case BNX2X_FLOW_CTRL_TX: 3435 *ieee_fc |= 3436 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC; 3437 break; 3438 default: 3439 break; 3440 } 3441 break; 3442 case BNX2X_FLOW_CTRL_TX: 3443 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC; 3444 break; 3445 3446 case BNX2X_FLOW_CTRL_RX: 3447 case BNX2X_FLOW_CTRL_BOTH: 3448 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; 3449 break; 3450 3451 case BNX2X_FLOW_CTRL_NONE: 3452 default: 3453 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE; 3454 break; 3455 } 3456 DP(NETIF_MSG_LINK, "ieee_fc = 0x%x\n", *ieee_fc); 3457 } 3458 3459 static void set_phy_vars(struct link_params *params, 3460 struct link_vars *vars) 3461 { 3462 struct bnx2x *bp = params->bp; 3463 u8 actual_phy_idx, phy_index, link_cfg_idx; 3464 u8 phy_config_swapped = params->multi_phy_config & 3465 PORT_HW_CFG_PHY_SWAPPED_ENABLED; 3466 for (phy_index = INT_PHY; phy_index < params->num_phys; 3467 phy_index++) { 3468 link_cfg_idx = LINK_CONFIG_IDX(phy_index); 3469 actual_phy_idx = phy_index; 3470 if (phy_config_swapped) { 3471 if (phy_index == EXT_PHY1) 3472 actual_phy_idx = EXT_PHY2; 3473 else if (phy_index == EXT_PHY2) 3474 actual_phy_idx = EXT_PHY1; 3475 } 3476 params->phy[actual_phy_idx].req_flow_ctrl = 3477 params->req_flow_ctrl[link_cfg_idx]; 3478 3479 params->phy[actual_phy_idx].req_line_speed = 3480 params->req_line_speed[link_cfg_idx]; 3481 3482 params->phy[actual_phy_idx].speed_cap_mask = 3483 params->speed_cap_mask[link_cfg_idx]; 3484 3485 params->phy[actual_phy_idx].req_duplex = 3486 params->req_duplex[link_cfg_idx]; 3487 3488 if (params->req_line_speed[link_cfg_idx] == 3489 SPEED_AUTO_NEG) 3490 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED; 3491 3492 DP(NETIF_MSG_LINK, "req_flow_ctrl %x, req_line_speed %x," 3493 " speed_cap_mask %x\n", 3494 params->phy[actual_phy_idx].req_flow_ctrl, 3495 params->phy[actual_phy_idx].req_line_speed, 3496 params->phy[actual_phy_idx].speed_cap_mask); 3497 } 3498 } 3499 3500 static void bnx2x_ext_phy_set_pause(struct link_params *params, 3501 struct bnx2x_phy *phy, 3502 struct link_vars *vars) 3503 { 3504 u16 val; 3505 struct bnx2x *bp = params->bp; 3506 /* Read modify write pause advertizing */ 3507 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &val); 3508 3509 val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH; 3510 3511 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */ 3512 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); 3513 if ((vars->ieee_fc & 3514 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) == 3515 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) { 3516 val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC; 3517 } 3518 if ((vars->ieee_fc & 3519 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) == 3520 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) { 3521 val |= MDIO_AN_REG_ADV_PAUSE_PAUSE; 3522 } 3523 DP(NETIF_MSG_LINK, "Ext phy AN advertize 0x%x\n", val); 3524 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val); 3525 } 3526 3527 static void bnx2x_pause_resolve(struct link_vars *vars, u32 pause_result) 3528 { /* LD LP */ 3529 switch (pause_result) { /* ASYM P ASYM P */ 3530 case 0xb: /* 1 0 1 1 */ 3531 vars->flow_ctrl = BNX2X_FLOW_CTRL_TX; 3532 break; 3533 3534 case 0xe: /* 1 1 1 0 */ 3535 vars->flow_ctrl = BNX2X_FLOW_CTRL_RX; 3536 break; 3537 3538 case 0x5: /* 0 1 0 1 */ 3539 case 0x7: /* 0 1 1 1 */ 3540 case 0xd: /* 1 1 0 1 */ 3541 case 0xf: /* 1 1 1 1 */ 3542 vars->flow_ctrl = BNX2X_FLOW_CTRL_BOTH; 3543 break; 3544 3545 default: 3546 break; 3547 } 3548 if (pause_result & (1<<0)) 3549 vars->link_status |= LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE; 3550 if (pause_result & (1<<1)) 3551 vars->link_status |= LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE; 3552 3553 } 3554 3555 static void bnx2x_ext_phy_update_adv_fc(struct bnx2x_phy *phy, 3556 struct link_params *params, 3557 struct link_vars *vars) 3558 { 3559 u16 ld_pause; /* local */ 3560 u16 lp_pause; /* link partner */ 3561 u16 pause_result; 3562 struct bnx2x *bp = params->bp; 3563 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) { 3564 bnx2x_cl22_read(bp, phy, 0x4, &ld_pause); 3565 bnx2x_cl22_read(bp, phy, 0x5, &lp_pause); 3566 } else if (CHIP_IS_E3(bp) && 3567 SINGLE_MEDIA_DIRECT(params)) { 3568 u8 lane = bnx2x_get_warpcore_lane(phy, params); 3569 u16 gp_status, gp_mask; 3570 bnx2x_cl45_read(bp, phy, 3571 MDIO_AN_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_4, 3572 &gp_status); 3573 gp_mask = (MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL | 3574 MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP) << 3575 lane; 3576 if ((gp_status & gp_mask) == gp_mask) { 3577 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, 3578 MDIO_AN_REG_ADV_PAUSE, &ld_pause); 3579 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, 3580 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause); 3581 } else { 3582 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, 3583 MDIO_AN_REG_CL37_FC_LD, &ld_pause); 3584 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, 3585 MDIO_AN_REG_CL37_FC_LP, &lp_pause); 3586 ld_pause = ((ld_pause & 3587 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) 3588 << 3); 3589 lp_pause = ((lp_pause & 3590 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) 3591 << 3); 3592 } 3593 } else { 3594 bnx2x_cl45_read(bp, phy, 3595 MDIO_AN_DEVAD, 3596 MDIO_AN_REG_ADV_PAUSE, &ld_pause); 3597 bnx2x_cl45_read(bp, phy, 3598 MDIO_AN_DEVAD, 3599 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause); 3600 } 3601 pause_result = (ld_pause & 3602 MDIO_AN_REG_ADV_PAUSE_MASK) >> 8; 3603 pause_result |= (lp_pause & 3604 MDIO_AN_REG_ADV_PAUSE_MASK) >> 10; 3605 DP(NETIF_MSG_LINK, "Ext PHY pause result 0x%x\n", pause_result); 3606 bnx2x_pause_resolve(vars, pause_result); 3607 3608 } 3609 3610 static u8 bnx2x_ext_phy_resolve_fc(struct bnx2x_phy *phy, 3611 struct link_params *params, 3612 struct link_vars *vars) 3613 { 3614 u8 ret = 0; 3615 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; 3616 if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO) { 3617 /* Update the advertised flow-controled of LD/LP in AN */ 3618 if (phy->req_line_speed == SPEED_AUTO_NEG) 3619 bnx2x_ext_phy_update_adv_fc(phy, params, vars); 3620 /* But set the flow-control result as the requested one */ 3621 vars->flow_ctrl = phy->req_flow_ctrl; 3622 } else if (phy->req_line_speed != SPEED_AUTO_NEG) 3623 vars->flow_ctrl = params->req_fc_auto_adv; 3624 else if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) { 3625 ret = 1; 3626 bnx2x_ext_phy_update_adv_fc(phy, params, vars); 3627 } 3628 return ret; 3629 } 3630 /******************************************************************/ 3631 /* Warpcore section */ 3632 /******************************************************************/ 3633 /* The init_internal_warpcore should mirror the xgxs, 3634 * i.e. reset the lane (if needed), set aer for the 3635 * init configuration, and set/clear SGMII flag. Internal 3636 * phy init is done purely in phy_init stage. 3637 */ 3638 #define WC_TX_DRIVER(post2, idriver, ipre) \ 3639 ((post2 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) | \ 3640 (idriver << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) | \ 3641 (ipre << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET)) 3642 3643 #define WC_TX_FIR(post, main, pre) \ 3644 ((post << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) | \ 3645 (main << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) | \ 3646 (pre << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET)) 3647 3648 static void bnx2x_warpcore_enable_AN_KR2(struct bnx2x_phy *phy, 3649 struct link_params *params, 3650 struct link_vars *vars) 3651 { 3652 struct bnx2x *bp = params->bp; 3653 u16 i; 3654 static struct bnx2x_reg_set reg_set[] = { 3655 /* Step 1 - Program the TX/RX alignment markers */ 3656 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL5, 0xa157}, 3657 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL7, 0xcbe2}, 3658 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL6, 0x7537}, 3659 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL9, 0xa157}, 3660 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL11, 0xcbe2}, 3661 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL10, 0x7537}, 3662 /* Step 2 - Configure the NP registers */ 3663 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_USERB0_CTRL, 0x000a}, 3664 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL1, 0x6400}, 3665 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL3, 0x0620}, 3666 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CODE_FIELD, 0x0157}, 3667 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI1, 0x6464}, 3668 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI2, 0x3150}, 3669 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI3, 0x3150}, 3670 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0157}, 3671 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0620} 3672 }; 3673 DP(NETIF_MSG_LINK, "Enabling 20G-KR2\n"); 3674 3675 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 3676 MDIO_WC_REG_CL49_USERB0_CTRL, (3<<6)); 3677 3678 for (i = 0; i < ARRAY_SIZE(reg_set); i++) 3679 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg, 3680 reg_set[i].val); 3681 3682 /* Start KR2 work-around timer which handles BCM8073 link-parner */ 3683 vars->link_attr_sync |= LINK_ATTR_SYNC_KR2_ENABLE; 3684 bnx2x_update_link_attr(params, vars->link_attr_sync); 3685 } 3686 3687 static void bnx2x_warpcore_set_lpi_passthrough(struct bnx2x_phy *phy, 3688 struct link_params *params) 3689 { 3690 struct bnx2x *bp = params->bp; 3691 3692 DP(NETIF_MSG_LINK, "Configure WC for LPI pass through\n"); 3693 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3694 MDIO_WC_REG_EEE_COMBO_CONTROL0, 0x7c); 3695 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 3696 MDIO_WC_REG_DIGITAL4_MISC5, 0xc000); 3697 } 3698 3699 static void bnx2x_warpcore_restart_AN_KR(struct bnx2x_phy *phy, 3700 struct link_params *params) 3701 { 3702 /* Restart autoneg on the leading lane only */ 3703 struct bnx2x *bp = params->bp; 3704 u16 lane = bnx2x_get_warpcore_lane(phy, params); 3705 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, 3706 MDIO_AER_BLOCK_AER_REG, lane); 3707 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, 3708 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200); 3709 3710 /* Restore AER */ 3711 bnx2x_set_aer_mmd(params, phy); 3712 } 3713 3714 static void bnx2x_warpcore_enable_AN_KR(struct bnx2x_phy *phy, 3715 struct link_params *params, 3716 struct link_vars *vars) { 3717 u16 lane, i, cl72_ctrl, an_adv = 0; 3718 u16 ucode_ver; 3719 struct bnx2x *bp = params->bp; 3720 static struct bnx2x_reg_set reg_set[] = { 3721 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7}, 3722 {MDIO_PMA_DEVAD, MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0x0}, 3723 {MDIO_WC_DEVAD, MDIO_WC_REG_RX66_CONTROL, 0x7415}, 3724 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x6190}, 3725 /* Disable Autoneg: re-enable it after adv is done. */ 3726 {MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0}, 3727 {MDIO_PMA_DEVAD, MDIO_WC_REG_PMD_KR_CONTROL, 0x2}, 3728 {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP, 0}, 3729 }; 3730 DP(NETIF_MSG_LINK, "Enable Auto Negotiation for KR\n"); 3731 /* Set to default registers that may be overriden by 10G force */ 3732 for (i = 0; i < ARRAY_SIZE(reg_set); i++) 3733 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg, 3734 reg_set[i].val); 3735 3736 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 3737 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, &cl72_ctrl); 3738 cl72_ctrl &= 0x08ff; 3739 cl72_ctrl |= 0x3800; 3740 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3741 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, cl72_ctrl); 3742 3743 /* Check adding advertisement for 1G KX */ 3744 if (((vars->line_speed == SPEED_AUTO_NEG) && 3745 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) || 3746 (vars->line_speed == SPEED_1000)) { 3747 u16 addr = MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2; 3748 an_adv |= (1<<5); 3749 3750 /* Enable CL37 1G Parallel Detect */ 3751 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, addr, 0x1); 3752 DP(NETIF_MSG_LINK, "Advertize 1G\n"); 3753 } 3754 if (((vars->line_speed == SPEED_AUTO_NEG) && 3755 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) || 3756 (vars->line_speed == SPEED_10000)) { 3757 /* Check adding advertisement for 10G KR */ 3758 an_adv |= (1<<7); 3759 /* Enable 10G Parallel Detect */ 3760 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, 3761 MDIO_AER_BLOCK_AER_REG, 0); 3762 3763 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, 3764 MDIO_WC_REG_PAR_DET_10G_CTRL, 1); 3765 bnx2x_set_aer_mmd(params, phy); 3766 DP(NETIF_MSG_LINK, "Advertize 10G\n"); 3767 } 3768 3769 /* Set Transmit PMD settings */ 3770 lane = bnx2x_get_warpcore_lane(phy, params); 3771 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3772 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 3773 WC_TX_DRIVER(0x02, 0x06, 0x09)); 3774 /* Configure the next lane if dual mode */ 3775 if (phy->flags & FLAGS_WC_DUAL_MODE) 3776 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3777 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*(lane+1), 3778 WC_TX_DRIVER(0x02, 0x06, 0x09)); 3779 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3780 MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL, 3781 0x03f0); 3782 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3783 MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL, 3784 0x03f0); 3785 3786 /* Advertised speeds */ 3787 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, 3788 MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, an_adv); 3789 3790 /* Advertised and set FEC (Forward Error Correction) */ 3791 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, 3792 MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2, 3793 (MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY | 3794 MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ)); 3795 3796 /* Enable CL37 BAM */ 3797 if (REG_RD(bp, params->shmem_base + 3798 offsetof(struct shmem_region, dev_info. 3799 port_hw_config[params->port].default_cfg)) & 3800 PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) { 3801 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 3802 MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL, 3803 1); 3804 DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n"); 3805 } 3806 3807 /* Advertise pause */ 3808 bnx2x_ext_phy_set_pause(params, phy, vars); 3809 /* Set KR Autoneg Work-Around flag for Warpcore version older than D108 3810 */ 3811 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 3812 MDIO_WC_REG_UC_INFO_B1_VERSION, &ucode_ver); 3813 if (ucode_ver < 0xd108) { 3814 DP(NETIF_MSG_LINK, "Enable AN KR work-around. WC ver:0x%x\n", 3815 ucode_ver); 3816 vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY; 3817 } 3818 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 3819 MDIO_WC_REG_DIGITAL5_MISC7, 0x100); 3820 3821 /* Over 1G - AN local device user page 1 */ 3822 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3823 MDIO_WC_REG_DIGITAL3_UP1, 0x1f); 3824 3825 if (((phy->req_line_speed == SPEED_AUTO_NEG) && 3826 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) || 3827 (phy->req_line_speed == SPEED_20000)) { 3828 3829 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, 3830 MDIO_AER_BLOCK_AER_REG, lane); 3831 3832 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 3833 MDIO_WC_REG_RX1_PCI_CTRL + (0x10*lane), 3834 (1<<11)); 3835 3836 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3837 MDIO_WC_REG_XGXS_X2_CONTROL3, 0x7); 3838 bnx2x_set_aer_mmd(params, phy); 3839 3840 bnx2x_warpcore_enable_AN_KR2(phy, params, vars); 3841 } 3842 3843 /* Enable Autoneg: only on the main lane */ 3844 bnx2x_warpcore_restart_AN_KR(phy, params); 3845 } 3846 3847 static void bnx2x_warpcore_set_10G_KR(struct bnx2x_phy *phy, 3848 struct link_params *params, 3849 struct link_vars *vars) 3850 { 3851 struct bnx2x *bp = params->bp; 3852 u16 val16, i, lane; 3853 static struct bnx2x_reg_set reg_set[] = { 3854 /* Disable Autoneg */ 3855 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7}, 3856 {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, 3857 0x3f00}, 3858 {MDIO_AN_DEVAD, MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, 0}, 3859 {MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0}, 3860 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL3_UP1, 0x1}, 3861 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL5_MISC7, 0xa}, 3862 /* Leave cl72 training enable, needed for KR */ 3863 {MDIO_PMA_DEVAD, MDIO_WC_REG_PMD_KR_CONTROL, 0x2} 3864 }; 3865 3866 for (i = 0; i < ARRAY_SIZE(reg_set); i++) 3867 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg, 3868 reg_set[i].val); 3869 3870 lane = bnx2x_get_warpcore_lane(phy, params); 3871 /* Global registers */ 3872 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, 3873 MDIO_AER_BLOCK_AER_REG, 0); 3874 /* Disable CL36 PCS Tx */ 3875 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 3876 MDIO_WC_REG_XGXSBLK1_LANECTRL0, &val16); 3877 val16 &= ~(0x0011 << lane); 3878 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3879 MDIO_WC_REG_XGXSBLK1_LANECTRL0, val16); 3880 3881 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 3882 MDIO_WC_REG_XGXSBLK1_LANECTRL1, &val16); 3883 val16 |= (0x0303 << (lane << 1)); 3884 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3885 MDIO_WC_REG_XGXSBLK1_LANECTRL1, val16); 3886 /* Restore AER */ 3887 bnx2x_set_aer_mmd(params, phy); 3888 /* Set speed via PMA/PMD register */ 3889 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 3890 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040); 3891 3892 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 3893 MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0xB); 3894 3895 /* Enable encoded forced speed */ 3896 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3897 MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x30); 3898 3899 /* Turn TX scramble payload only the 64/66 scrambler */ 3900 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3901 MDIO_WC_REG_TX66_CONTROL, 0x9); 3902 3903 /* Turn RX scramble payload only the 64/66 scrambler */ 3904 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 3905 MDIO_WC_REG_RX66_CONTROL, 0xF9); 3906 3907 /* Set and clear loopback to cause a reset to 64/66 decoder */ 3908 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3909 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x4000); 3910 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3911 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0); 3912 3913 } 3914 3915 static void bnx2x_warpcore_set_10G_XFI(struct bnx2x_phy *phy, 3916 struct link_params *params, 3917 u8 is_xfi) 3918 { 3919 struct bnx2x *bp = params->bp; 3920 u16 misc1_val, tap_val, tx_driver_val, lane, val; 3921 u32 cfg_tap_val, tx_drv_brdct, tx_equal; 3922 3923 /* Hold rxSeqStart */ 3924 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 3925 MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x8000); 3926 3927 /* Hold tx_fifo_reset */ 3928 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 3929 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, 0x1); 3930 3931 /* Disable CL73 AN */ 3932 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0); 3933 3934 /* Disable 100FX Enable and Auto-Detect */ 3935 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, 3936 MDIO_WC_REG_FX100_CTRL1, 0xFFFA); 3937 3938 /* Disable 100FX Idle detect */ 3939 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 3940 MDIO_WC_REG_FX100_CTRL3, 0x0080); 3941 3942 /* Set Block address to Remote PHY & Clear forced_speed[5] */ 3943 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, 3944 MDIO_WC_REG_DIGITAL4_MISC3, 0xFF7F); 3945 3946 /* Turn off auto-detect & fiber mode */ 3947 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, 3948 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 3949 0xFFEE); 3950 3951 /* Set filter_force_link, disable_false_link and parallel_detect */ 3952 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 3953 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &val); 3954 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3955 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 3956 ((val | 0x0006) & 0xFFFE)); 3957 3958 /* Set XFI / SFI */ 3959 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 3960 MDIO_WC_REG_SERDESDIGITAL_MISC1, &misc1_val); 3961 3962 misc1_val &= ~(0x1f); 3963 3964 if (is_xfi) { 3965 misc1_val |= 0x5; 3966 tap_val = WC_TX_FIR(0x08, 0x37, 0x00); 3967 tx_driver_val = WC_TX_DRIVER(0x00, 0x02, 0x03); 3968 } else { 3969 cfg_tap_val = REG_RD(bp, params->shmem_base + 3970 offsetof(struct shmem_region, dev_info. 3971 port_hw_config[params->port]. 3972 sfi_tap_values)); 3973 3974 tx_equal = cfg_tap_val & PORT_HW_CFG_TX_EQUALIZATION_MASK; 3975 3976 tx_drv_brdct = (cfg_tap_val & 3977 PORT_HW_CFG_TX_DRV_BROADCAST_MASK) >> 3978 PORT_HW_CFG_TX_DRV_BROADCAST_SHIFT; 3979 3980 misc1_val |= 0x9; 3981 3982 /* TAP values are controlled by nvram, if value there isn't 0 */ 3983 if (tx_equal) 3984 tap_val = (u16)tx_equal; 3985 else 3986 tap_val = WC_TX_FIR(0x0f, 0x2b, 0x02); 3987 3988 if (tx_drv_brdct) 3989 tx_driver_val = WC_TX_DRIVER(0x03, (u16)tx_drv_brdct, 3990 0x06); 3991 else 3992 tx_driver_val = WC_TX_DRIVER(0x03, 0x02, 0x06); 3993 } 3994 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3995 MDIO_WC_REG_SERDESDIGITAL_MISC1, misc1_val); 3996 3997 /* Set Transmit PMD settings */ 3998 lane = bnx2x_get_warpcore_lane(phy, params); 3999 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4000 MDIO_WC_REG_TX_FIR_TAP, 4001 tap_val | MDIO_WC_REG_TX_FIR_TAP_ENABLE); 4002 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4003 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 4004 tx_driver_val); 4005 4006 /* Enable fiber mode, enable and invert sig_det */ 4007 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 4008 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0xd); 4009 4010 /* Set Block address to Remote PHY & Set forced_speed[5], 40bit mode */ 4011 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 4012 MDIO_WC_REG_DIGITAL4_MISC3, 0x8080); 4013 4014 bnx2x_warpcore_set_lpi_passthrough(phy, params); 4015 4016 /* 10G XFI Full Duplex */ 4017 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4018 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x100); 4019 4020 /* Release tx_fifo_reset */ 4021 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, 4022 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, 4023 0xFFFE); 4024 /* Release rxSeqStart */ 4025 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, 4026 MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x7FFF); 4027 } 4028 4029 static void bnx2x_warpcore_set_20G_force_KR2(struct bnx2x_phy *phy, 4030 struct link_params *params) 4031 { 4032 u16 val; 4033 struct bnx2x *bp = params->bp; 4034 /* Set global registers, so set AER lane to 0 */ 4035 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, 4036 MDIO_AER_BLOCK_AER_REG, 0); 4037 4038 /* Disable sequencer */ 4039 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, 4040 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, ~(1<<13)); 4041 4042 bnx2x_set_aer_mmd(params, phy); 4043 4044 bnx2x_cl45_read_and_write(bp, phy, MDIO_PMA_DEVAD, 4045 MDIO_WC_REG_PMD_KR_CONTROL, ~(1<<1)); 4046 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, 4047 MDIO_AN_REG_CTRL, 0); 4048 /* Turn off CL73 */ 4049 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 4050 MDIO_WC_REG_CL73_USERB0_CTRL, &val); 4051 val &= ~(1<<5); 4052 val |= (1<<6); 4053 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4054 MDIO_WC_REG_CL73_USERB0_CTRL, val); 4055 4056 /* Set 20G KR2 force speed */ 4057 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 4058 MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x1f); 4059 4060 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 4061 MDIO_WC_REG_DIGITAL4_MISC3, (1<<7)); 4062 4063 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 4064 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, &val); 4065 val &= ~(3<<14); 4066 val |= (1<<15); 4067 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4068 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, val); 4069 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4070 MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP, 0x835A); 4071 4072 /* Enable sequencer (over lane 0) */ 4073 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, 4074 MDIO_AER_BLOCK_AER_REG, 0); 4075 4076 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 4077 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, (1<<13)); 4078 4079 bnx2x_set_aer_mmd(params, phy); 4080 } 4081 4082 static void bnx2x_warpcore_set_20G_DXGXS(struct bnx2x *bp, 4083 struct bnx2x_phy *phy, 4084 u16 lane) 4085 { 4086 /* Rx0 anaRxControl1G */ 4087 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4088 MDIO_WC_REG_RX0_ANARXCONTROL1G, 0x90); 4089 4090 /* Rx2 anaRxControl1G */ 4091 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4092 MDIO_WC_REG_RX2_ANARXCONTROL1G, 0x90); 4093 4094 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4095 MDIO_WC_REG_RX66_SCW0, 0xE070); 4096 4097 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4098 MDIO_WC_REG_RX66_SCW1, 0xC0D0); 4099 4100 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4101 MDIO_WC_REG_RX66_SCW2, 0xA0B0); 4102 4103 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4104 MDIO_WC_REG_RX66_SCW3, 0x8090); 4105 4106 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4107 MDIO_WC_REG_RX66_SCW0_MASK, 0xF0F0); 4108 4109 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4110 MDIO_WC_REG_RX66_SCW1_MASK, 0xF0F0); 4111 4112 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4113 MDIO_WC_REG_RX66_SCW2_MASK, 0xF0F0); 4114 4115 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4116 MDIO_WC_REG_RX66_SCW3_MASK, 0xF0F0); 4117 4118 /* Serdes Digital Misc1 */ 4119 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4120 MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6008); 4121 4122 /* Serdes Digital4 Misc3 */ 4123 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4124 MDIO_WC_REG_DIGITAL4_MISC3, 0x8088); 4125 4126 /* Set Transmit PMD settings */ 4127 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4128 MDIO_WC_REG_TX_FIR_TAP, 4129 (WC_TX_FIR(0x12, 0x2d, 0x00) | 4130 MDIO_WC_REG_TX_FIR_TAP_ENABLE)); 4131 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4132 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 4133 WC_TX_DRIVER(0x02, 0x02, 0x02)); 4134 } 4135 4136 static void bnx2x_warpcore_set_sgmii_speed(struct bnx2x_phy *phy, 4137 struct link_params *params, 4138 u8 fiber_mode, 4139 u8 always_autoneg) 4140 { 4141 struct bnx2x *bp = params->bp; 4142 u16 val16, digctrl_kx1, digctrl_kx2; 4143 4144 /* Clear XFI clock comp in non-10G single lane mode. */ 4145 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, 4146 MDIO_WC_REG_RX66_CONTROL, ~(3<<13)); 4147 4148 bnx2x_warpcore_set_lpi_passthrough(phy, params); 4149 4150 if (always_autoneg || phy->req_line_speed == SPEED_AUTO_NEG) { 4151 /* SGMII Autoneg */ 4152 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 4153 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 4154 0x1000); 4155 DP(NETIF_MSG_LINK, "set SGMII AUTONEG\n"); 4156 } else { 4157 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 4158 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16); 4159 val16 &= 0xcebf; 4160 switch (phy->req_line_speed) { 4161 case SPEED_10: 4162 break; 4163 case SPEED_100: 4164 val16 |= 0x2000; 4165 break; 4166 case SPEED_1000: 4167 val16 |= 0x0040; 4168 break; 4169 default: 4170 DP(NETIF_MSG_LINK, 4171 "Speed not supported: 0x%x\n", phy->req_line_speed); 4172 return; 4173 } 4174 4175 if (phy->req_duplex == DUPLEX_FULL) 4176 val16 |= 0x0100; 4177 4178 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4179 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16); 4180 4181 DP(NETIF_MSG_LINK, "set SGMII force speed %d\n", 4182 phy->req_line_speed); 4183 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 4184 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16); 4185 DP(NETIF_MSG_LINK, " (readback) %x\n", val16); 4186 } 4187 4188 /* SGMII Slave mode and disable signal detect */ 4189 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 4190 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &digctrl_kx1); 4191 if (fiber_mode) 4192 digctrl_kx1 = 1; 4193 else 4194 digctrl_kx1 &= 0xff4a; 4195 4196 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4197 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 4198 digctrl_kx1); 4199 4200 /* Turn off parallel detect */ 4201 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 4202 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &digctrl_kx2); 4203 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4204 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 4205 (digctrl_kx2 & ~(1<<2))); 4206 4207 /* Re-enable parallel detect */ 4208 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4209 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 4210 (digctrl_kx2 | (1<<2))); 4211 4212 /* Enable autodet */ 4213 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4214 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 4215 (digctrl_kx1 | 0x10)); 4216 } 4217 4218 static void bnx2x_warpcore_reset_lane(struct bnx2x *bp, 4219 struct bnx2x_phy *phy, 4220 u8 reset) 4221 { 4222 u16 val; 4223 /* Take lane out of reset after configuration is finished */ 4224 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 4225 MDIO_WC_REG_DIGITAL5_MISC6, &val); 4226 if (reset) 4227 val |= 0xC000; 4228 else 4229 val &= 0x3FFF; 4230 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4231 MDIO_WC_REG_DIGITAL5_MISC6, val); 4232 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 4233 MDIO_WC_REG_DIGITAL5_MISC6, &val); 4234 } 4235 /* Clear SFI/XFI link settings registers */ 4236 static void bnx2x_warpcore_clear_regs(struct bnx2x_phy *phy, 4237 struct link_params *params, 4238 u16 lane) 4239 { 4240 struct bnx2x *bp = params->bp; 4241 u16 i; 4242 static struct bnx2x_reg_set wc_regs[] = { 4243 {MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0}, 4244 {MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL1, 0x014a}, 4245 {MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL3, 0x0800}, 4246 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL4_MISC3, 0x8008}, 4247 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 4248 0x0195}, 4249 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 4250 0x0007}, 4251 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, 4252 0x0002}, 4253 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6000}, 4254 {MDIO_WC_DEVAD, MDIO_WC_REG_TX_FIR_TAP, 0x0000}, 4255 {MDIO_WC_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040}, 4256 {MDIO_WC_DEVAD, MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0x0140} 4257 }; 4258 /* Set XFI clock comp as default. */ 4259 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 4260 MDIO_WC_REG_RX66_CONTROL, (3<<13)); 4261 4262 for (i = 0; i < ARRAY_SIZE(wc_regs); i++) 4263 bnx2x_cl45_write(bp, phy, wc_regs[i].devad, wc_regs[i].reg, 4264 wc_regs[i].val); 4265 4266 lane = bnx2x_get_warpcore_lane(phy, params); 4267 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4268 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 0x0990); 4269 4270 } 4271 4272 static int bnx2x_get_mod_abs_int_cfg(struct bnx2x *bp, 4273 u32 chip_id, 4274 u32 shmem_base, u8 port, 4275 u8 *gpio_num, u8 *gpio_port) 4276 { 4277 u32 cfg_pin; 4278 *gpio_num = 0; 4279 *gpio_port = 0; 4280 if (CHIP_IS_E3(bp)) { 4281 cfg_pin = (REG_RD(bp, shmem_base + 4282 offsetof(struct shmem_region, 4283 dev_info.port_hw_config[port].e3_sfp_ctrl)) & 4284 PORT_HW_CFG_E3_MOD_ABS_MASK) >> 4285 PORT_HW_CFG_E3_MOD_ABS_SHIFT; 4286 4287 /* Should not happen. This function called upon interrupt 4288 * triggered by GPIO ( since EPIO can only generate interrupts 4289 * to MCP). 4290 * So if this function was called and none of the GPIOs was set, 4291 * it means the shit hit the fan. 4292 */ 4293 if ((cfg_pin < PIN_CFG_GPIO0_P0) || 4294 (cfg_pin > PIN_CFG_GPIO3_P1)) { 4295 DP(NETIF_MSG_LINK, 4296 "No cfg pin %x for module detect indication\n", 4297 cfg_pin); 4298 return -EINVAL; 4299 } 4300 4301 *gpio_num = (cfg_pin - PIN_CFG_GPIO0_P0) & 0x3; 4302 *gpio_port = (cfg_pin - PIN_CFG_GPIO0_P0) >> 2; 4303 } else { 4304 *gpio_num = MISC_REGISTERS_GPIO_3; 4305 *gpio_port = port; 4306 } 4307 4308 return 0; 4309 } 4310 4311 static int bnx2x_is_sfp_module_plugged(struct bnx2x_phy *phy, 4312 struct link_params *params) 4313 { 4314 struct bnx2x *bp = params->bp; 4315 u8 gpio_num, gpio_port; 4316 u32 gpio_val; 4317 if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id, 4318 params->shmem_base, params->port, 4319 &gpio_num, &gpio_port) != 0) 4320 return 0; 4321 gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port); 4322 4323 /* Call the handling function in case module is detected */ 4324 if (gpio_val == 0) 4325 return 1; 4326 else 4327 return 0; 4328 } 4329 static int bnx2x_warpcore_get_sigdet(struct bnx2x_phy *phy, 4330 struct link_params *params) 4331 { 4332 u16 gp2_status_reg0, lane; 4333 struct bnx2x *bp = params->bp; 4334 4335 lane = bnx2x_get_warpcore_lane(phy, params); 4336 4337 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_0, 4338 &gp2_status_reg0); 4339 4340 return (gp2_status_reg0 >> (8+lane)) & 0x1; 4341 } 4342 4343 static void bnx2x_warpcore_config_runtime(struct bnx2x_phy *phy, 4344 struct link_params *params, 4345 struct link_vars *vars) 4346 { 4347 struct bnx2x *bp = params->bp; 4348 u32 serdes_net_if; 4349 u16 gp_status1 = 0, lnkup = 0, lnkup_kr = 0; 4350 u16 lane = bnx2x_get_warpcore_lane(phy, params); 4351 4352 vars->turn_to_run_wc_rt = vars->turn_to_run_wc_rt ? 0 : 1; 4353 4354 if (!vars->turn_to_run_wc_rt) 4355 return; 4356 4357 /* Return if there is no link partner */ 4358 if (!(bnx2x_warpcore_get_sigdet(phy, params))) { 4359 DP(NETIF_MSG_LINK, "bnx2x_warpcore_get_sigdet false\n"); 4360 return; 4361 } 4362 4363 if (vars->rx_tx_asic_rst) { 4364 serdes_net_if = (REG_RD(bp, params->shmem_base + 4365 offsetof(struct shmem_region, dev_info. 4366 port_hw_config[params->port].default_cfg)) & 4367 PORT_HW_CFG_NET_SERDES_IF_MASK); 4368 4369 switch (serdes_net_if) { 4370 case PORT_HW_CFG_NET_SERDES_IF_KR: 4371 /* Do we get link yet? */ 4372 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 0x81d1, 4373 &gp_status1); 4374 lnkup = (gp_status1 >> (8+lane)) & 0x1;/* 1G */ 4375 /*10G KR*/ 4376 lnkup_kr = (gp_status1 >> (12+lane)) & 0x1; 4377 4378 DP(NETIF_MSG_LINK, 4379 "gp_status1 0x%x\n", gp_status1); 4380 4381 if (lnkup_kr || lnkup) { 4382 vars->rx_tx_asic_rst = 0; 4383 DP(NETIF_MSG_LINK, 4384 "link up, rx_tx_asic_rst 0x%x\n", 4385 vars->rx_tx_asic_rst); 4386 } else { 4387 /* Reset the lane to see if link comes up.*/ 4388 bnx2x_warpcore_reset_lane(bp, phy, 1); 4389 bnx2x_warpcore_reset_lane(bp, phy, 0); 4390 4391 /* Restart Autoneg */ 4392 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, 4393 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200); 4394 4395 vars->rx_tx_asic_rst--; 4396 DP(NETIF_MSG_LINK, "0x%x retry left\n", 4397 vars->rx_tx_asic_rst); 4398 } 4399 break; 4400 4401 default: 4402 break; 4403 } 4404 4405 } /*params->rx_tx_asic_rst*/ 4406 4407 } 4408 static void bnx2x_warpcore_config_sfi(struct bnx2x_phy *phy, 4409 struct link_params *params) 4410 { 4411 u16 lane = bnx2x_get_warpcore_lane(phy, params); 4412 struct bnx2x *bp = params->bp; 4413 bnx2x_warpcore_clear_regs(phy, params, lane); 4414 if ((params->req_line_speed[LINK_CONFIG_IDX(INT_PHY)] == 4415 SPEED_10000) && 4416 (phy->media_type != ETH_PHY_SFP_1G_FIBER)) { 4417 DP(NETIF_MSG_LINK, "Setting 10G SFI\n"); 4418 bnx2x_warpcore_set_10G_XFI(phy, params, 0); 4419 } else { 4420 DP(NETIF_MSG_LINK, "Setting 1G Fiber\n"); 4421 bnx2x_warpcore_set_sgmii_speed(phy, params, 1, 0); 4422 } 4423 } 4424 4425 static void bnx2x_sfp_e3_set_transmitter(struct link_params *params, 4426 struct bnx2x_phy *phy, 4427 u8 tx_en) 4428 { 4429 struct bnx2x *bp = params->bp; 4430 u32 cfg_pin; 4431 u8 port = params->port; 4432 4433 cfg_pin = REG_RD(bp, params->shmem_base + 4434 offsetof(struct shmem_region, 4435 dev_info.port_hw_config[port].e3_sfp_ctrl)) & 4436 PORT_HW_CFG_E3_TX_LASER_MASK; 4437 /* Set the !tx_en since this pin is DISABLE_TX_LASER */ 4438 DP(NETIF_MSG_LINK, "Setting WC TX to %d\n", tx_en); 4439 4440 /* For 20G, the expected pin to be used is 3 pins after the current */ 4441 bnx2x_set_cfg_pin(bp, cfg_pin, tx_en ^ 1); 4442 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G) 4443 bnx2x_set_cfg_pin(bp, cfg_pin + 3, tx_en ^ 1); 4444 } 4445 4446 static void bnx2x_warpcore_config_init(struct bnx2x_phy *phy, 4447 struct link_params *params, 4448 struct link_vars *vars) 4449 { 4450 struct bnx2x *bp = params->bp; 4451 u32 serdes_net_if; 4452 u8 fiber_mode; 4453 u16 lane = bnx2x_get_warpcore_lane(phy, params); 4454 serdes_net_if = (REG_RD(bp, params->shmem_base + 4455 offsetof(struct shmem_region, dev_info. 4456 port_hw_config[params->port].default_cfg)) & 4457 PORT_HW_CFG_NET_SERDES_IF_MASK); 4458 DP(NETIF_MSG_LINK, "Begin Warpcore init, link_speed %d, " 4459 "serdes_net_if = 0x%x\n", 4460 vars->line_speed, serdes_net_if); 4461 bnx2x_set_aer_mmd(params, phy); 4462 bnx2x_warpcore_reset_lane(bp, phy, 1); 4463 vars->phy_flags |= PHY_XGXS_FLAG; 4464 if ((serdes_net_if == PORT_HW_CFG_NET_SERDES_IF_SGMII) || 4465 (phy->req_line_speed && 4466 ((phy->req_line_speed == SPEED_100) || 4467 (phy->req_line_speed == SPEED_10)))) { 4468 vars->phy_flags |= PHY_SGMII_FLAG; 4469 DP(NETIF_MSG_LINK, "Setting SGMII mode\n"); 4470 bnx2x_warpcore_clear_regs(phy, params, lane); 4471 bnx2x_warpcore_set_sgmii_speed(phy, params, 0, 1); 4472 } else { 4473 switch (serdes_net_if) { 4474 case PORT_HW_CFG_NET_SERDES_IF_KR: 4475 /* Enable KR Auto Neg */ 4476 if (params->loopback_mode != LOOPBACK_EXT) 4477 bnx2x_warpcore_enable_AN_KR(phy, params, vars); 4478 else { 4479 DP(NETIF_MSG_LINK, "Setting KR 10G-Force\n"); 4480 bnx2x_warpcore_set_10G_KR(phy, params, vars); 4481 } 4482 break; 4483 4484 case PORT_HW_CFG_NET_SERDES_IF_XFI: 4485 bnx2x_warpcore_clear_regs(phy, params, lane); 4486 if (vars->line_speed == SPEED_10000) { 4487 DP(NETIF_MSG_LINK, "Setting 10G XFI\n"); 4488 bnx2x_warpcore_set_10G_XFI(phy, params, 1); 4489 } else { 4490 if (SINGLE_MEDIA_DIRECT(params)) { 4491 DP(NETIF_MSG_LINK, "1G Fiber\n"); 4492 fiber_mode = 1; 4493 } else { 4494 DP(NETIF_MSG_LINK, "10/100/1G SGMII\n"); 4495 fiber_mode = 0; 4496 } 4497 bnx2x_warpcore_set_sgmii_speed(phy, 4498 params, 4499 fiber_mode, 4500 0); 4501 } 4502 4503 break; 4504 4505 case PORT_HW_CFG_NET_SERDES_IF_SFI: 4506 /* Issue Module detection if module is plugged, or 4507 * enabled transmitter to avoid current leakage in case 4508 * no module is connected 4509 */ 4510 if (bnx2x_is_sfp_module_plugged(phy, params)) 4511 bnx2x_sfp_module_detection(phy, params); 4512 else 4513 bnx2x_sfp_e3_set_transmitter(params, phy, 1); 4514 4515 bnx2x_warpcore_config_sfi(phy, params); 4516 break; 4517 4518 case PORT_HW_CFG_NET_SERDES_IF_DXGXS: 4519 if (vars->line_speed != SPEED_20000) { 4520 DP(NETIF_MSG_LINK, "Speed not supported yet\n"); 4521 return; 4522 } 4523 DP(NETIF_MSG_LINK, "Setting 20G DXGXS\n"); 4524 bnx2x_warpcore_set_20G_DXGXS(bp, phy, lane); 4525 /* Issue Module detection */ 4526 4527 bnx2x_sfp_module_detection(phy, params); 4528 break; 4529 case PORT_HW_CFG_NET_SERDES_IF_KR2: 4530 if (!params->loopback_mode) { 4531 bnx2x_warpcore_enable_AN_KR(phy, params, vars); 4532 } else { 4533 DP(NETIF_MSG_LINK, "Setting KR 20G-Force\n"); 4534 bnx2x_warpcore_set_20G_force_KR2(phy, params); 4535 } 4536 break; 4537 default: 4538 DP(NETIF_MSG_LINK, 4539 "Unsupported Serdes Net Interface 0x%x\n", 4540 serdes_net_if); 4541 return; 4542 } 4543 } 4544 4545 /* Take lane out of reset after configuration is finished */ 4546 bnx2x_warpcore_reset_lane(bp, phy, 0); 4547 DP(NETIF_MSG_LINK, "Exit config init\n"); 4548 } 4549 4550 static void bnx2x_warpcore_link_reset(struct bnx2x_phy *phy, 4551 struct link_params *params) 4552 { 4553 struct bnx2x *bp = params->bp; 4554 u16 val16, lane; 4555 bnx2x_sfp_e3_set_transmitter(params, phy, 0); 4556 bnx2x_set_mdio_emac_per_phy(bp, params); 4557 bnx2x_set_aer_mmd(params, phy); 4558 /* Global register */ 4559 bnx2x_warpcore_reset_lane(bp, phy, 1); 4560 4561 /* Clear loopback settings (if any) */ 4562 /* 10G & 20G */ 4563 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, 4564 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0xBFFF); 4565 4566 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, 4567 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0xfffe); 4568 4569 /* Update those 1-copy registers */ 4570 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, 4571 MDIO_AER_BLOCK_AER_REG, 0); 4572 /* Enable 1G MDIO (1-copy) */ 4573 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, 4574 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, 4575 ~0x10); 4576 4577 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, 4578 MDIO_WC_REG_XGXSBLK1_LANECTRL2, 0xff00); 4579 lane = bnx2x_get_warpcore_lane(phy, params); 4580 /* Disable CL36 PCS Tx */ 4581 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 4582 MDIO_WC_REG_XGXSBLK1_LANECTRL0, &val16); 4583 val16 |= (0x11 << lane); 4584 if (phy->flags & FLAGS_WC_DUAL_MODE) 4585 val16 |= (0x22 << lane); 4586 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4587 MDIO_WC_REG_XGXSBLK1_LANECTRL0, val16); 4588 4589 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 4590 MDIO_WC_REG_XGXSBLK1_LANECTRL1, &val16); 4591 val16 &= ~(0x0303 << (lane << 1)); 4592 val16 |= (0x0101 << (lane << 1)); 4593 if (phy->flags & FLAGS_WC_DUAL_MODE) { 4594 val16 &= ~(0x0c0c << (lane << 1)); 4595 val16 |= (0x0404 << (lane << 1)); 4596 } 4597 4598 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4599 MDIO_WC_REG_XGXSBLK1_LANECTRL1, val16); 4600 /* Restore AER */ 4601 bnx2x_set_aer_mmd(params, phy); 4602 4603 } 4604 4605 static void bnx2x_set_warpcore_loopback(struct bnx2x_phy *phy, 4606 struct link_params *params) 4607 { 4608 struct bnx2x *bp = params->bp; 4609 u16 val16; 4610 u32 lane; 4611 DP(NETIF_MSG_LINK, "Setting Warpcore loopback type %x, speed %d\n", 4612 params->loopback_mode, phy->req_line_speed); 4613 4614 if (phy->req_line_speed < SPEED_10000 || 4615 phy->supported & SUPPORTED_20000baseKR2_Full) { 4616 /* 10/100/1000/20G-KR2 */ 4617 4618 /* Update those 1-copy registers */ 4619 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, 4620 MDIO_AER_BLOCK_AER_REG, 0); 4621 /* Enable 1G MDIO (1-copy) */ 4622 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 4623 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, 4624 0x10); 4625 /* Set 1G loopback based on lane (1-copy) */ 4626 lane = bnx2x_get_warpcore_lane(phy, params); 4627 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 4628 MDIO_WC_REG_XGXSBLK1_LANECTRL2, &val16); 4629 val16 |= (1<<lane); 4630 if (phy->flags & FLAGS_WC_DUAL_MODE) 4631 val16 |= (2<<lane); 4632 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4633 MDIO_WC_REG_XGXSBLK1_LANECTRL2, 4634 val16); 4635 4636 /* Switch back to 4-copy registers */ 4637 bnx2x_set_aer_mmd(params, phy); 4638 } else { 4639 /* 10G / 20G-DXGXS */ 4640 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 4641 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 4642 0x4000); 4643 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 4644 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1); 4645 } 4646 } 4647 4648 4649 4650 static void bnx2x_sync_link(struct link_params *params, 4651 struct link_vars *vars) 4652 { 4653 struct bnx2x *bp = params->bp; 4654 u8 link_10g_plus; 4655 if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG) 4656 vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG; 4657 vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP); 4658 if (vars->link_up) { 4659 DP(NETIF_MSG_LINK, "phy link up\n"); 4660 4661 vars->phy_link_up = 1; 4662 vars->duplex = DUPLEX_FULL; 4663 switch (vars->link_status & 4664 LINK_STATUS_SPEED_AND_DUPLEX_MASK) { 4665 case LINK_10THD: 4666 vars->duplex = DUPLEX_HALF; 4667 /* Fall thru */ 4668 case LINK_10TFD: 4669 vars->line_speed = SPEED_10; 4670 break; 4671 4672 case LINK_100TXHD: 4673 vars->duplex = DUPLEX_HALF; 4674 /* Fall thru */ 4675 case LINK_100T4: 4676 case LINK_100TXFD: 4677 vars->line_speed = SPEED_100; 4678 break; 4679 4680 case LINK_1000THD: 4681 vars->duplex = DUPLEX_HALF; 4682 /* Fall thru */ 4683 case LINK_1000TFD: 4684 vars->line_speed = SPEED_1000; 4685 break; 4686 4687 case LINK_2500THD: 4688 vars->duplex = DUPLEX_HALF; 4689 /* Fall thru */ 4690 case LINK_2500TFD: 4691 vars->line_speed = SPEED_2500; 4692 break; 4693 4694 case LINK_10GTFD: 4695 vars->line_speed = SPEED_10000; 4696 break; 4697 case LINK_20GTFD: 4698 vars->line_speed = SPEED_20000; 4699 break; 4700 default: 4701 break; 4702 } 4703 vars->flow_ctrl = 0; 4704 if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED) 4705 vars->flow_ctrl |= BNX2X_FLOW_CTRL_TX; 4706 4707 if (vars->link_status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED) 4708 vars->flow_ctrl |= BNX2X_FLOW_CTRL_RX; 4709 4710 if (!vars->flow_ctrl) 4711 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; 4712 4713 if (vars->line_speed && 4714 ((vars->line_speed == SPEED_10) || 4715 (vars->line_speed == SPEED_100))) { 4716 vars->phy_flags |= PHY_SGMII_FLAG; 4717 } else { 4718 vars->phy_flags &= ~PHY_SGMII_FLAG; 4719 } 4720 if (vars->line_speed && 4721 USES_WARPCORE(bp) && 4722 (vars->line_speed == SPEED_1000)) 4723 vars->phy_flags |= PHY_SGMII_FLAG; 4724 /* Anything 10 and over uses the bmac */ 4725 link_10g_plus = (vars->line_speed >= SPEED_10000); 4726 4727 if (link_10g_plus) { 4728 if (USES_WARPCORE(bp)) 4729 vars->mac_type = MAC_TYPE_XMAC; 4730 else 4731 vars->mac_type = MAC_TYPE_BMAC; 4732 } else { 4733 if (USES_WARPCORE(bp)) 4734 vars->mac_type = MAC_TYPE_UMAC; 4735 else 4736 vars->mac_type = MAC_TYPE_EMAC; 4737 } 4738 } else { /* Link down */ 4739 DP(NETIF_MSG_LINK, "phy link down\n"); 4740 4741 vars->phy_link_up = 0; 4742 4743 vars->line_speed = 0; 4744 vars->duplex = DUPLEX_FULL; 4745 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; 4746 4747 /* Indicate no mac active */ 4748 vars->mac_type = MAC_TYPE_NONE; 4749 if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG) 4750 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG; 4751 if (vars->link_status & LINK_STATUS_SFP_TX_FAULT) 4752 vars->phy_flags |= PHY_SFP_TX_FAULT_FLAG; 4753 } 4754 } 4755 4756 void bnx2x_link_status_update(struct link_params *params, 4757 struct link_vars *vars) 4758 { 4759 struct bnx2x *bp = params->bp; 4760 u8 port = params->port; 4761 u32 sync_offset, media_types; 4762 /* Update PHY configuration */ 4763 set_phy_vars(params, vars); 4764 4765 vars->link_status = REG_RD(bp, params->shmem_base + 4766 offsetof(struct shmem_region, 4767 port_mb[port].link_status)); 4768 4769 /* Force link UP in non LOOPBACK_EXT loopback mode(s) */ 4770 if (params->loopback_mode != LOOPBACK_NONE && 4771 params->loopback_mode != LOOPBACK_EXT) 4772 vars->link_status |= LINK_STATUS_LINK_UP; 4773 4774 if (bnx2x_eee_has_cap(params)) 4775 vars->eee_status = REG_RD(bp, params->shmem2_base + 4776 offsetof(struct shmem2_region, 4777 eee_status[params->port])); 4778 4779 vars->phy_flags = PHY_XGXS_FLAG; 4780 bnx2x_sync_link(params, vars); 4781 /* Sync media type */ 4782 sync_offset = params->shmem_base + 4783 offsetof(struct shmem_region, 4784 dev_info.port_hw_config[port].media_type); 4785 media_types = REG_RD(bp, sync_offset); 4786 4787 params->phy[INT_PHY].media_type = 4788 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) >> 4789 PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT; 4790 params->phy[EXT_PHY1].media_type = 4791 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK) >> 4792 PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT; 4793 params->phy[EXT_PHY2].media_type = 4794 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK) >> 4795 PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT; 4796 DP(NETIF_MSG_LINK, "media_types = 0x%x\n", media_types); 4797 4798 /* Sync AEU offset */ 4799 sync_offset = params->shmem_base + 4800 offsetof(struct shmem_region, 4801 dev_info.port_hw_config[port].aeu_int_mask); 4802 4803 vars->aeu_int_mask = REG_RD(bp, sync_offset); 4804 4805 /* Sync PFC status */ 4806 if (vars->link_status & LINK_STATUS_PFC_ENABLED) 4807 params->feature_config_flags |= 4808 FEATURE_CONFIG_PFC_ENABLED; 4809 else 4810 params->feature_config_flags &= 4811 ~FEATURE_CONFIG_PFC_ENABLED; 4812 4813 if (SHMEM2_HAS(bp, link_attr_sync)) 4814 vars->link_attr_sync = SHMEM2_RD(bp, 4815 link_attr_sync[params->port]); 4816 4817 DP(NETIF_MSG_LINK, "link_status 0x%x phy_link_up %x int_mask 0x%x\n", 4818 vars->link_status, vars->phy_link_up, vars->aeu_int_mask); 4819 DP(NETIF_MSG_LINK, "line_speed %x duplex %x flow_ctrl 0x%x\n", 4820 vars->line_speed, vars->duplex, vars->flow_ctrl); 4821 } 4822 4823 static void bnx2x_set_master_ln(struct link_params *params, 4824 struct bnx2x_phy *phy) 4825 { 4826 struct bnx2x *bp = params->bp; 4827 u16 new_master_ln, ser_lane; 4828 ser_lane = ((params->lane_config & 4829 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >> 4830 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT); 4831 4832 /* Set the master_ln for AN */ 4833 CL22_RD_OVER_CL45(bp, phy, 4834 MDIO_REG_BANK_XGXS_BLOCK2, 4835 MDIO_XGXS_BLOCK2_TEST_MODE_LANE, 4836 &new_master_ln); 4837 4838 CL22_WR_OVER_CL45(bp, phy, 4839 MDIO_REG_BANK_XGXS_BLOCK2 , 4840 MDIO_XGXS_BLOCK2_TEST_MODE_LANE, 4841 (new_master_ln | ser_lane)); 4842 } 4843 4844 static int bnx2x_reset_unicore(struct link_params *params, 4845 struct bnx2x_phy *phy, 4846 u8 set_serdes) 4847 { 4848 struct bnx2x *bp = params->bp; 4849 u16 mii_control; 4850 u16 i; 4851 CL22_RD_OVER_CL45(bp, phy, 4852 MDIO_REG_BANK_COMBO_IEEE0, 4853 MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control); 4854 4855 /* Reset the unicore */ 4856 CL22_WR_OVER_CL45(bp, phy, 4857 MDIO_REG_BANK_COMBO_IEEE0, 4858 MDIO_COMBO_IEEE0_MII_CONTROL, 4859 (mii_control | 4860 MDIO_COMBO_IEEO_MII_CONTROL_RESET)); 4861 if (set_serdes) 4862 bnx2x_set_serdes_access(bp, params->port); 4863 4864 /* Wait for the reset to self clear */ 4865 for (i = 0; i < MDIO_ACCESS_TIMEOUT; i++) { 4866 udelay(5); 4867 4868 /* The reset erased the previous bank value */ 4869 CL22_RD_OVER_CL45(bp, phy, 4870 MDIO_REG_BANK_COMBO_IEEE0, 4871 MDIO_COMBO_IEEE0_MII_CONTROL, 4872 &mii_control); 4873 4874 if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) { 4875 udelay(5); 4876 return 0; 4877 } 4878 } 4879 4880 netdev_err(bp->dev, "Warning: PHY was not initialized," 4881 " Port %d\n", 4882 params->port); 4883 DP(NETIF_MSG_LINK, "BUG! XGXS is still in reset!\n"); 4884 return -EINVAL; 4885 4886 } 4887 4888 static void bnx2x_set_swap_lanes(struct link_params *params, 4889 struct bnx2x_phy *phy) 4890 { 4891 struct bnx2x *bp = params->bp; 4892 /* Each two bits represents a lane number: 4893 * No swap is 0123 => 0x1b no need to enable the swap 4894 */ 4895 u16 rx_lane_swap, tx_lane_swap; 4896 4897 rx_lane_swap = ((params->lane_config & 4898 PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >> 4899 PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT); 4900 tx_lane_swap = ((params->lane_config & 4901 PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >> 4902 PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT); 4903 4904 if (rx_lane_swap != 0x1b) { 4905 CL22_WR_OVER_CL45(bp, phy, 4906 MDIO_REG_BANK_XGXS_BLOCK2, 4907 MDIO_XGXS_BLOCK2_RX_LN_SWAP, 4908 (rx_lane_swap | 4909 MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE | 4910 MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE)); 4911 } else { 4912 CL22_WR_OVER_CL45(bp, phy, 4913 MDIO_REG_BANK_XGXS_BLOCK2, 4914 MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0); 4915 } 4916 4917 if (tx_lane_swap != 0x1b) { 4918 CL22_WR_OVER_CL45(bp, phy, 4919 MDIO_REG_BANK_XGXS_BLOCK2, 4920 MDIO_XGXS_BLOCK2_TX_LN_SWAP, 4921 (tx_lane_swap | 4922 MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE)); 4923 } else { 4924 CL22_WR_OVER_CL45(bp, phy, 4925 MDIO_REG_BANK_XGXS_BLOCK2, 4926 MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0); 4927 } 4928 } 4929 4930 static void bnx2x_set_parallel_detection(struct bnx2x_phy *phy, 4931 struct link_params *params) 4932 { 4933 struct bnx2x *bp = params->bp; 4934 u16 control2; 4935 CL22_RD_OVER_CL45(bp, phy, 4936 MDIO_REG_BANK_SERDES_DIGITAL, 4937 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2, 4938 &control2); 4939 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) 4940 control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN; 4941 else 4942 control2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN; 4943 DP(NETIF_MSG_LINK, "phy->speed_cap_mask = 0x%x, control2 = 0x%x\n", 4944 phy->speed_cap_mask, control2); 4945 CL22_WR_OVER_CL45(bp, phy, 4946 MDIO_REG_BANK_SERDES_DIGITAL, 4947 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2, 4948 control2); 4949 4950 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) && 4951 (phy->speed_cap_mask & 4952 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) { 4953 DP(NETIF_MSG_LINK, "XGXS\n"); 4954 4955 CL22_WR_OVER_CL45(bp, phy, 4956 MDIO_REG_BANK_10G_PARALLEL_DETECT, 4957 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK, 4958 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT); 4959 4960 CL22_RD_OVER_CL45(bp, phy, 4961 MDIO_REG_BANK_10G_PARALLEL_DETECT, 4962 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL, 4963 &control2); 4964 4965 4966 control2 |= 4967 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN; 4968 4969 CL22_WR_OVER_CL45(bp, phy, 4970 MDIO_REG_BANK_10G_PARALLEL_DETECT, 4971 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL, 4972 control2); 4973 4974 /* Disable parallel detection of HiG */ 4975 CL22_WR_OVER_CL45(bp, phy, 4976 MDIO_REG_BANK_XGXS_BLOCK2, 4977 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G, 4978 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS | 4979 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS); 4980 } 4981 } 4982 4983 static void bnx2x_set_autoneg(struct bnx2x_phy *phy, 4984 struct link_params *params, 4985 struct link_vars *vars, 4986 u8 enable_cl73) 4987 { 4988 struct bnx2x *bp = params->bp; 4989 u16 reg_val; 4990 4991 /* CL37 Autoneg */ 4992 CL22_RD_OVER_CL45(bp, phy, 4993 MDIO_REG_BANK_COMBO_IEEE0, 4994 MDIO_COMBO_IEEE0_MII_CONTROL, ®_val); 4995 4996 /* CL37 Autoneg Enabled */ 4997 if (vars->line_speed == SPEED_AUTO_NEG) 4998 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN; 4999 else /* CL37 Autoneg Disabled */ 5000 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN | 5001 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN); 5002 5003 CL22_WR_OVER_CL45(bp, phy, 5004 MDIO_REG_BANK_COMBO_IEEE0, 5005 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val); 5006 5007 /* Enable/Disable Autodetection */ 5008 5009 CL22_RD_OVER_CL45(bp, phy, 5010 MDIO_REG_BANK_SERDES_DIGITAL, 5011 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, ®_val); 5012 reg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN | 5013 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT); 5014 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE; 5015 if (vars->line_speed == SPEED_AUTO_NEG) 5016 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET; 5017 else 5018 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET; 5019 5020 CL22_WR_OVER_CL45(bp, phy, 5021 MDIO_REG_BANK_SERDES_DIGITAL, 5022 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val); 5023 5024 /* Enable TetonII and BAM autoneg */ 5025 CL22_RD_OVER_CL45(bp, phy, 5026 MDIO_REG_BANK_BAM_NEXT_PAGE, 5027 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL, 5028 ®_val); 5029 if (vars->line_speed == SPEED_AUTO_NEG) { 5030 /* Enable BAM aneg Mode and TetonII aneg Mode */ 5031 reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE | 5032 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN); 5033 } else { 5034 /* TetonII and BAM Autoneg Disabled */ 5035 reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE | 5036 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN); 5037 } 5038 CL22_WR_OVER_CL45(bp, phy, 5039 MDIO_REG_BANK_BAM_NEXT_PAGE, 5040 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL, 5041 reg_val); 5042 5043 if (enable_cl73) { 5044 /* Enable Cl73 FSM status bits */ 5045 CL22_WR_OVER_CL45(bp, phy, 5046 MDIO_REG_BANK_CL73_USERB0, 5047 MDIO_CL73_USERB0_CL73_UCTRL, 5048 0xe); 5049 5050 /* Enable BAM Station Manager*/ 5051 CL22_WR_OVER_CL45(bp, phy, 5052 MDIO_REG_BANK_CL73_USERB0, 5053 MDIO_CL73_USERB0_CL73_BAM_CTRL1, 5054 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN | 5055 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN | 5056 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN); 5057 5058 /* Advertise CL73 link speeds */ 5059 CL22_RD_OVER_CL45(bp, phy, 5060 MDIO_REG_BANK_CL73_IEEEB1, 5061 MDIO_CL73_IEEEB1_AN_ADV2, 5062 ®_val); 5063 if (phy->speed_cap_mask & 5064 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) 5065 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4; 5066 if (phy->speed_cap_mask & 5067 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) 5068 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX; 5069 5070 CL22_WR_OVER_CL45(bp, phy, 5071 MDIO_REG_BANK_CL73_IEEEB1, 5072 MDIO_CL73_IEEEB1_AN_ADV2, 5073 reg_val); 5074 5075 /* CL73 Autoneg Enabled */ 5076 reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN; 5077 5078 } else /* CL73 Autoneg Disabled */ 5079 reg_val = 0; 5080 5081 CL22_WR_OVER_CL45(bp, phy, 5082 MDIO_REG_BANK_CL73_IEEEB0, 5083 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val); 5084 } 5085 5086 /* Program SerDes, forced speed */ 5087 static void bnx2x_program_serdes(struct bnx2x_phy *phy, 5088 struct link_params *params, 5089 struct link_vars *vars) 5090 { 5091 struct bnx2x *bp = params->bp; 5092 u16 reg_val; 5093 5094 /* Program duplex, disable autoneg and sgmii*/ 5095 CL22_RD_OVER_CL45(bp, phy, 5096 MDIO_REG_BANK_COMBO_IEEE0, 5097 MDIO_COMBO_IEEE0_MII_CONTROL, ®_val); 5098 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX | 5099 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN | 5100 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK); 5101 if (phy->req_duplex == DUPLEX_FULL) 5102 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX; 5103 CL22_WR_OVER_CL45(bp, phy, 5104 MDIO_REG_BANK_COMBO_IEEE0, 5105 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val); 5106 5107 /* Program speed 5108 * - needed only if the speed is greater than 1G (2.5G or 10G) 5109 */ 5110 CL22_RD_OVER_CL45(bp, phy, 5111 MDIO_REG_BANK_SERDES_DIGITAL, 5112 MDIO_SERDES_DIGITAL_MISC1, ®_val); 5113 /* Clearing the speed value before setting the right speed */ 5114 DP(NETIF_MSG_LINK, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val); 5115 5116 reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK | 5117 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL); 5118 5119 if (!((vars->line_speed == SPEED_1000) || 5120 (vars->line_speed == SPEED_100) || 5121 (vars->line_speed == SPEED_10))) { 5122 5123 reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M | 5124 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL); 5125 if (vars->line_speed == SPEED_10000) 5126 reg_val |= 5127 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4; 5128 } 5129 5130 CL22_WR_OVER_CL45(bp, phy, 5131 MDIO_REG_BANK_SERDES_DIGITAL, 5132 MDIO_SERDES_DIGITAL_MISC1, reg_val); 5133 5134 } 5135 5136 static void bnx2x_set_brcm_cl37_advertisement(struct bnx2x_phy *phy, 5137 struct link_params *params) 5138 { 5139 struct bnx2x *bp = params->bp; 5140 u16 val = 0; 5141 5142 /* Set extended capabilities */ 5143 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) 5144 val |= MDIO_OVER_1G_UP1_2_5G; 5145 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) 5146 val |= MDIO_OVER_1G_UP1_10G; 5147 CL22_WR_OVER_CL45(bp, phy, 5148 MDIO_REG_BANK_OVER_1G, 5149 MDIO_OVER_1G_UP1, val); 5150 5151 CL22_WR_OVER_CL45(bp, phy, 5152 MDIO_REG_BANK_OVER_1G, 5153 MDIO_OVER_1G_UP3, 0x400); 5154 } 5155 5156 static void bnx2x_set_ieee_aneg_advertisement(struct bnx2x_phy *phy, 5157 struct link_params *params, 5158 u16 ieee_fc) 5159 { 5160 struct bnx2x *bp = params->bp; 5161 u16 val; 5162 /* For AN, we are always publishing full duplex */ 5163 5164 CL22_WR_OVER_CL45(bp, phy, 5165 MDIO_REG_BANK_COMBO_IEEE0, 5166 MDIO_COMBO_IEEE0_AUTO_NEG_ADV, ieee_fc); 5167 CL22_RD_OVER_CL45(bp, phy, 5168 MDIO_REG_BANK_CL73_IEEEB1, 5169 MDIO_CL73_IEEEB1_AN_ADV1, &val); 5170 val &= ~MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH; 5171 val |= ((ieee_fc<<3) & MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK); 5172 CL22_WR_OVER_CL45(bp, phy, 5173 MDIO_REG_BANK_CL73_IEEEB1, 5174 MDIO_CL73_IEEEB1_AN_ADV1, val); 5175 } 5176 5177 static void bnx2x_restart_autoneg(struct bnx2x_phy *phy, 5178 struct link_params *params, 5179 u8 enable_cl73) 5180 { 5181 struct bnx2x *bp = params->bp; 5182 u16 mii_control; 5183 5184 DP(NETIF_MSG_LINK, "bnx2x_restart_autoneg\n"); 5185 /* Enable and restart BAM/CL37 aneg */ 5186 5187 if (enable_cl73) { 5188 CL22_RD_OVER_CL45(bp, phy, 5189 MDIO_REG_BANK_CL73_IEEEB0, 5190 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, 5191 &mii_control); 5192 5193 CL22_WR_OVER_CL45(bp, phy, 5194 MDIO_REG_BANK_CL73_IEEEB0, 5195 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, 5196 (mii_control | 5197 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN | 5198 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN)); 5199 } else { 5200 5201 CL22_RD_OVER_CL45(bp, phy, 5202 MDIO_REG_BANK_COMBO_IEEE0, 5203 MDIO_COMBO_IEEE0_MII_CONTROL, 5204 &mii_control); 5205 DP(NETIF_MSG_LINK, 5206 "bnx2x_restart_autoneg mii_control before = 0x%x\n", 5207 mii_control); 5208 CL22_WR_OVER_CL45(bp, phy, 5209 MDIO_REG_BANK_COMBO_IEEE0, 5210 MDIO_COMBO_IEEE0_MII_CONTROL, 5211 (mii_control | 5212 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN | 5213 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN)); 5214 } 5215 } 5216 5217 static void bnx2x_initialize_sgmii_process(struct bnx2x_phy *phy, 5218 struct link_params *params, 5219 struct link_vars *vars) 5220 { 5221 struct bnx2x *bp = params->bp; 5222 u16 control1; 5223 5224 /* In SGMII mode, the unicore is always slave */ 5225 5226 CL22_RD_OVER_CL45(bp, phy, 5227 MDIO_REG_BANK_SERDES_DIGITAL, 5228 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, 5229 &control1); 5230 control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT; 5231 /* Set sgmii mode (and not fiber) */ 5232 control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE | 5233 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET | 5234 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE); 5235 CL22_WR_OVER_CL45(bp, phy, 5236 MDIO_REG_BANK_SERDES_DIGITAL, 5237 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, 5238 control1); 5239 5240 /* If forced speed */ 5241 if (!(vars->line_speed == SPEED_AUTO_NEG)) { 5242 /* Set speed, disable autoneg */ 5243 u16 mii_control; 5244 5245 CL22_RD_OVER_CL45(bp, phy, 5246 MDIO_REG_BANK_COMBO_IEEE0, 5247 MDIO_COMBO_IEEE0_MII_CONTROL, 5248 &mii_control); 5249 mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN | 5250 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK| 5251 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX); 5252 5253 switch (vars->line_speed) { 5254 case SPEED_100: 5255 mii_control |= 5256 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100; 5257 break; 5258 case SPEED_1000: 5259 mii_control |= 5260 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000; 5261 break; 5262 case SPEED_10: 5263 /* There is nothing to set for 10M */ 5264 break; 5265 default: 5266 /* Invalid speed for SGMII */ 5267 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n", 5268 vars->line_speed); 5269 break; 5270 } 5271 5272 /* Setting the full duplex */ 5273 if (phy->req_duplex == DUPLEX_FULL) 5274 mii_control |= 5275 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX; 5276 CL22_WR_OVER_CL45(bp, phy, 5277 MDIO_REG_BANK_COMBO_IEEE0, 5278 MDIO_COMBO_IEEE0_MII_CONTROL, 5279 mii_control); 5280 5281 } else { /* AN mode */ 5282 /* Enable and restart AN */ 5283 bnx2x_restart_autoneg(phy, params, 0); 5284 } 5285 } 5286 5287 /* Link management 5288 */ 5289 static int bnx2x_direct_parallel_detect_used(struct bnx2x_phy *phy, 5290 struct link_params *params) 5291 { 5292 struct bnx2x *bp = params->bp; 5293 u16 pd_10g, status2_1000x; 5294 if (phy->req_line_speed != SPEED_AUTO_NEG) 5295 return 0; 5296 CL22_RD_OVER_CL45(bp, phy, 5297 MDIO_REG_BANK_SERDES_DIGITAL, 5298 MDIO_SERDES_DIGITAL_A_1000X_STATUS2, 5299 &status2_1000x); 5300 CL22_RD_OVER_CL45(bp, phy, 5301 MDIO_REG_BANK_SERDES_DIGITAL, 5302 MDIO_SERDES_DIGITAL_A_1000X_STATUS2, 5303 &status2_1000x); 5304 if (status2_1000x & MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED) { 5305 DP(NETIF_MSG_LINK, "1G parallel detect link on port %d\n", 5306 params->port); 5307 return 1; 5308 } 5309 5310 CL22_RD_OVER_CL45(bp, phy, 5311 MDIO_REG_BANK_10G_PARALLEL_DETECT, 5312 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS, 5313 &pd_10g); 5314 5315 if (pd_10g & MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK) { 5316 DP(NETIF_MSG_LINK, "10G parallel detect link on port %d\n", 5317 params->port); 5318 return 1; 5319 } 5320 return 0; 5321 } 5322 5323 static void bnx2x_update_adv_fc(struct bnx2x_phy *phy, 5324 struct link_params *params, 5325 struct link_vars *vars, 5326 u32 gp_status) 5327 { 5328 u16 ld_pause; /* local driver */ 5329 u16 lp_pause; /* link partner */ 5330 u16 pause_result; 5331 struct bnx2x *bp = params->bp; 5332 if ((gp_status & 5333 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | 5334 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) == 5335 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | 5336 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) { 5337 5338 CL22_RD_OVER_CL45(bp, phy, 5339 MDIO_REG_BANK_CL73_IEEEB1, 5340 MDIO_CL73_IEEEB1_AN_ADV1, 5341 &ld_pause); 5342 CL22_RD_OVER_CL45(bp, phy, 5343 MDIO_REG_BANK_CL73_IEEEB1, 5344 MDIO_CL73_IEEEB1_AN_LP_ADV1, 5345 &lp_pause); 5346 pause_result = (ld_pause & 5347 MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK) >> 8; 5348 pause_result |= (lp_pause & 5349 MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK) >> 10; 5350 DP(NETIF_MSG_LINK, "pause_result CL73 0x%x\n", pause_result); 5351 } else { 5352 CL22_RD_OVER_CL45(bp, phy, 5353 MDIO_REG_BANK_COMBO_IEEE0, 5354 MDIO_COMBO_IEEE0_AUTO_NEG_ADV, 5355 &ld_pause); 5356 CL22_RD_OVER_CL45(bp, phy, 5357 MDIO_REG_BANK_COMBO_IEEE0, 5358 MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1, 5359 &lp_pause); 5360 pause_result = (ld_pause & 5361 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>5; 5362 pause_result |= (lp_pause & 5363 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7; 5364 DP(NETIF_MSG_LINK, "pause_result CL37 0x%x\n", pause_result); 5365 } 5366 bnx2x_pause_resolve(vars, pause_result); 5367 5368 } 5369 5370 static void bnx2x_flow_ctrl_resolve(struct bnx2x_phy *phy, 5371 struct link_params *params, 5372 struct link_vars *vars, 5373 u32 gp_status) 5374 { 5375 struct bnx2x *bp = params->bp; 5376 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; 5377 5378 /* Resolve from gp_status in case of AN complete and not sgmii */ 5379 if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO) { 5380 /* Update the advertised flow-controled of LD/LP in AN */ 5381 if (phy->req_line_speed == SPEED_AUTO_NEG) 5382 bnx2x_update_adv_fc(phy, params, vars, gp_status); 5383 /* But set the flow-control result as the requested one */ 5384 vars->flow_ctrl = phy->req_flow_ctrl; 5385 } else if (phy->req_line_speed != SPEED_AUTO_NEG) 5386 vars->flow_ctrl = params->req_fc_auto_adv; 5387 else if ((gp_status & MDIO_AN_CL73_OR_37_COMPLETE) && 5388 (!(vars->phy_flags & PHY_SGMII_FLAG))) { 5389 if (bnx2x_direct_parallel_detect_used(phy, params)) { 5390 vars->flow_ctrl = params->req_fc_auto_adv; 5391 return; 5392 } 5393 bnx2x_update_adv_fc(phy, params, vars, gp_status); 5394 } 5395 DP(NETIF_MSG_LINK, "flow_ctrl 0x%x\n", vars->flow_ctrl); 5396 } 5397 5398 static void bnx2x_check_fallback_to_cl37(struct bnx2x_phy *phy, 5399 struct link_params *params) 5400 { 5401 struct bnx2x *bp = params->bp; 5402 u16 rx_status, ustat_val, cl37_fsm_received; 5403 DP(NETIF_MSG_LINK, "bnx2x_check_fallback_to_cl37\n"); 5404 /* Step 1: Make sure signal is detected */ 5405 CL22_RD_OVER_CL45(bp, phy, 5406 MDIO_REG_BANK_RX0, 5407 MDIO_RX0_RX_STATUS, 5408 &rx_status); 5409 if ((rx_status & MDIO_RX0_RX_STATUS_SIGDET) != 5410 (MDIO_RX0_RX_STATUS_SIGDET)) { 5411 DP(NETIF_MSG_LINK, "Signal is not detected. Restoring CL73." 5412 "rx_status(0x80b0) = 0x%x\n", rx_status); 5413 CL22_WR_OVER_CL45(bp, phy, 5414 MDIO_REG_BANK_CL73_IEEEB0, 5415 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, 5416 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN); 5417 return; 5418 } 5419 /* Step 2: Check CL73 state machine */ 5420 CL22_RD_OVER_CL45(bp, phy, 5421 MDIO_REG_BANK_CL73_USERB0, 5422 MDIO_CL73_USERB0_CL73_USTAT1, 5423 &ustat_val); 5424 if ((ustat_val & 5425 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK | 5426 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) != 5427 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK | 5428 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) { 5429 DP(NETIF_MSG_LINK, "CL73 state-machine is not stable. " 5430 "ustat_val(0x8371) = 0x%x\n", ustat_val); 5431 return; 5432 } 5433 /* Step 3: Check CL37 Message Pages received to indicate LP 5434 * supports only CL37 5435 */ 5436 CL22_RD_OVER_CL45(bp, phy, 5437 MDIO_REG_BANK_REMOTE_PHY, 5438 MDIO_REMOTE_PHY_MISC_RX_STATUS, 5439 &cl37_fsm_received); 5440 if ((cl37_fsm_received & 5441 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG | 5442 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) != 5443 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG | 5444 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) { 5445 DP(NETIF_MSG_LINK, "No CL37 FSM were received. " 5446 "misc_rx_status(0x8330) = 0x%x\n", 5447 cl37_fsm_received); 5448 return; 5449 } 5450 /* The combined cl37/cl73 fsm state information indicating that 5451 * we are connected to a device which does not support cl73, but 5452 * does support cl37 BAM. In this case we disable cl73 and 5453 * restart cl37 auto-neg 5454 */ 5455 5456 /* Disable CL73 */ 5457 CL22_WR_OVER_CL45(bp, phy, 5458 MDIO_REG_BANK_CL73_IEEEB0, 5459 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, 5460 0); 5461 /* Restart CL37 autoneg */ 5462 bnx2x_restart_autoneg(phy, params, 0); 5463 DP(NETIF_MSG_LINK, "Disabling CL73, and restarting CL37 autoneg\n"); 5464 } 5465 5466 static void bnx2x_xgxs_an_resolve(struct bnx2x_phy *phy, 5467 struct link_params *params, 5468 struct link_vars *vars, 5469 u32 gp_status) 5470 { 5471 if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE) 5472 vars->link_status |= 5473 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; 5474 5475 if (bnx2x_direct_parallel_detect_used(phy, params)) 5476 vars->link_status |= 5477 LINK_STATUS_PARALLEL_DETECTION_USED; 5478 } 5479 static int bnx2x_get_link_speed_duplex(struct bnx2x_phy *phy, 5480 struct link_params *params, 5481 struct link_vars *vars, 5482 u16 is_link_up, 5483 u16 speed_mask, 5484 u16 is_duplex) 5485 { 5486 struct bnx2x *bp = params->bp; 5487 if (phy->req_line_speed == SPEED_AUTO_NEG) 5488 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED; 5489 if (is_link_up) { 5490 DP(NETIF_MSG_LINK, "phy link up\n"); 5491 5492 vars->phy_link_up = 1; 5493 vars->link_status |= LINK_STATUS_LINK_UP; 5494 5495 switch (speed_mask) { 5496 case GP_STATUS_10M: 5497 vars->line_speed = SPEED_10; 5498 if (is_duplex == DUPLEX_FULL) 5499 vars->link_status |= LINK_10TFD; 5500 else 5501 vars->link_status |= LINK_10THD; 5502 break; 5503 5504 case GP_STATUS_100M: 5505 vars->line_speed = SPEED_100; 5506 if (is_duplex == DUPLEX_FULL) 5507 vars->link_status |= LINK_100TXFD; 5508 else 5509 vars->link_status |= LINK_100TXHD; 5510 break; 5511 5512 case GP_STATUS_1G: 5513 case GP_STATUS_1G_KX: 5514 vars->line_speed = SPEED_1000; 5515 if (is_duplex == DUPLEX_FULL) 5516 vars->link_status |= LINK_1000TFD; 5517 else 5518 vars->link_status |= LINK_1000THD; 5519 break; 5520 5521 case GP_STATUS_2_5G: 5522 vars->line_speed = SPEED_2500; 5523 if (is_duplex == DUPLEX_FULL) 5524 vars->link_status |= LINK_2500TFD; 5525 else 5526 vars->link_status |= LINK_2500THD; 5527 break; 5528 5529 case GP_STATUS_5G: 5530 case GP_STATUS_6G: 5531 DP(NETIF_MSG_LINK, 5532 "link speed unsupported gp_status 0x%x\n", 5533 speed_mask); 5534 return -EINVAL; 5535 5536 case GP_STATUS_10G_KX4: 5537 case GP_STATUS_10G_HIG: 5538 case GP_STATUS_10G_CX4: 5539 case GP_STATUS_10G_KR: 5540 case GP_STATUS_10G_SFI: 5541 case GP_STATUS_10G_XFI: 5542 vars->line_speed = SPEED_10000; 5543 vars->link_status |= LINK_10GTFD; 5544 break; 5545 case GP_STATUS_20G_DXGXS: 5546 case GP_STATUS_20G_KR2: 5547 vars->line_speed = SPEED_20000; 5548 vars->link_status |= LINK_20GTFD; 5549 break; 5550 default: 5551 DP(NETIF_MSG_LINK, 5552 "link speed unsupported gp_status 0x%x\n", 5553 speed_mask); 5554 return -EINVAL; 5555 } 5556 } else { /* link_down */ 5557 DP(NETIF_MSG_LINK, "phy link down\n"); 5558 5559 vars->phy_link_up = 0; 5560 5561 vars->duplex = DUPLEX_FULL; 5562 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; 5563 vars->mac_type = MAC_TYPE_NONE; 5564 } 5565 DP(NETIF_MSG_LINK, " phy_link_up %x line_speed %d\n", 5566 vars->phy_link_up, vars->line_speed); 5567 return 0; 5568 } 5569 5570 static int bnx2x_link_settings_status(struct bnx2x_phy *phy, 5571 struct link_params *params, 5572 struct link_vars *vars) 5573 { 5574 struct bnx2x *bp = params->bp; 5575 5576 u16 gp_status, duplex = DUPLEX_HALF, link_up = 0, speed_mask; 5577 int rc = 0; 5578 5579 /* Read gp_status */ 5580 CL22_RD_OVER_CL45(bp, phy, 5581 MDIO_REG_BANK_GP_STATUS, 5582 MDIO_GP_STATUS_TOP_AN_STATUS1, 5583 &gp_status); 5584 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS) 5585 duplex = DUPLEX_FULL; 5586 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) 5587 link_up = 1; 5588 speed_mask = gp_status & GP_STATUS_SPEED_MASK; 5589 DP(NETIF_MSG_LINK, "gp_status 0x%x, is_link_up %d, speed_mask 0x%x\n", 5590 gp_status, link_up, speed_mask); 5591 rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, speed_mask, 5592 duplex); 5593 if (rc == -EINVAL) 5594 return rc; 5595 5596 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) { 5597 if (SINGLE_MEDIA_DIRECT(params)) { 5598 vars->duplex = duplex; 5599 bnx2x_flow_ctrl_resolve(phy, params, vars, gp_status); 5600 if (phy->req_line_speed == SPEED_AUTO_NEG) 5601 bnx2x_xgxs_an_resolve(phy, params, vars, 5602 gp_status); 5603 } 5604 } else { /* Link_down */ 5605 if ((phy->req_line_speed == SPEED_AUTO_NEG) && 5606 SINGLE_MEDIA_DIRECT(params)) { 5607 /* Check signal is detected */ 5608 bnx2x_check_fallback_to_cl37(phy, params); 5609 } 5610 } 5611 5612 /* Read LP advertised speeds*/ 5613 if (SINGLE_MEDIA_DIRECT(params) && 5614 (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)) { 5615 u16 val; 5616 5617 CL22_RD_OVER_CL45(bp, phy, MDIO_REG_BANK_CL73_IEEEB1, 5618 MDIO_CL73_IEEEB1_AN_LP_ADV2, &val); 5619 5620 if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX) 5621 vars->link_status |= 5622 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; 5623 if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 | 5624 MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR)) 5625 vars->link_status |= 5626 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; 5627 5628 CL22_RD_OVER_CL45(bp, phy, MDIO_REG_BANK_OVER_1G, 5629 MDIO_OVER_1G_LP_UP1, &val); 5630 5631 if (val & MDIO_OVER_1G_UP1_2_5G) 5632 vars->link_status |= 5633 LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE; 5634 if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH)) 5635 vars->link_status |= 5636 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; 5637 } 5638 5639 DP(NETIF_MSG_LINK, "duplex %x flow_ctrl 0x%x link_status 0x%x\n", 5640 vars->duplex, vars->flow_ctrl, vars->link_status); 5641 return rc; 5642 } 5643 5644 static int bnx2x_warpcore_read_status(struct bnx2x_phy *phy, 5645 struct link_params *params, 5646 struct link_vars *vars) 5647 { 5648 struct bnx2x *bp = params->bp; 5649 u8 lane; 5650 u16 gp_status1, gp_speed, link_up, duplex = DUPLEX_FULL; 5651 int rc = 0; 5652 lane = bnx2x_get_warpcore_lane(phy, params); 5653 /* Read gp_status */ 5654 if ((params->loopback_mode) && 5655 (phy->flags & FLAGS_WC_DUAL_MODE)) { 5656 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 5657 MDIO_WC_REG_DIGITAL5_LINK_STATUS, &link_up); 5658 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 5659 MDIO_WC_REG_DIGITAL5_LINK_STATUS, &link_up); 5660 link_up &= 0x1; 5661 } else if ((phy->req_line_speed > SPEED_10000) && 5662 (phy->supported & SUPPORTED_20000baseMLD2_Full)) { 5663 u16 temp_link_up; 5664 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 5665 1, &temp_link_up); 5666 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 5667 1, &link_up); 5668 DP(NETIF_MSG_LINK, "PCS RX link status = 0x%x-->0x%x\n", 5669 temp_link_up, link_up); 5670 link_up &= (1<<2); 5671 if (link_up) 5672 bnx2x_ext_phy_resolve_fc(phy, params, vars); 5673 } else { 5674 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 5675 MDIO_WC_REG_GP2_STATUS_GP_2_1, 5676 &gp_status1); 5677 DP(NETIF_MSG_LINK, "0x81d1 = 0x%x\n", gp_status1); 5678 /* Check for either KR, 1G, or AN up. */ 5679 link_up = ((gp_status1 >> 8) | 5680 (gp_status1 >> 12) | 5681 (gp_status1)) & 5682 (1 << lane); 5683 if (phy->supported & SUPPORTED_20000baseKR2_Full) { 5684 u16 an_link; 5685 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, 5686 MDIO_AN_REG_STATUS, &an_link); 5687 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, 5688 MDIO_AN_REG_STATUS, &an_link); 5689 link_up |= (an_link & (1<<2)); 5690 } 5691 if (link_up && SINGLE_MEDIA_DIRECT(params)) { 5692 u16 pd, gp_status4; 5693 if (phy->req_line_speed == SPEED_AUTO_NEG) { 5694 /* Check Autoneg complete */ 5695 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 5696 MDIO_WC_REG_GP2_STATUS_GP_2_4, 5697 &gp_status4); 5698 if (gp_status4 & ((1<<12)<<lane)) 5699 vars->link_status |= 5700 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; 5701 5702 /* Check parallel detect used */ 5703 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 5704 MDIO_WC_REG_PAR_DET_10G_STATUS, 5705 &pd); 5706 if (pd & (1<<15)) 5707 vars->link_status |= 5708 LINK_STATUS_PARALLEL_DETECTION_USED; 5709 } 5710 bnx2x_ext_phy_resolve_fc(phy, params, vars); 5711 vars->duplex = duplex; 5712 } 5713 } 5714 5715 if ((vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) && 5716 SINGLE_MEDIA_DIRECT(params)) { 5717 u16 val; 5718 5719 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, 5720 MDIO_AN_REG_LP_AUTO_NEG2, &val); 5721 5722 if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX) 5723 vars->link_status |= 5724 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; 5725 if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 | 5726 MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR)) 5727 vars->link_status |= 5728 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; 5729 5730 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 5731 MDIO_WC_REG_DIGITAL3_LP_UP1, &val); 5732 5733 if (val & MDIO_OVER_1G_UP1_2_5G) 5734 vars->link_status |= 5735 LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE; 5736 if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH)) 5737 vars->link_status |= 5738 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; 5739 5740 } 5741 5742 5743 if (lane < 2) { 5744 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 5745 MDIO_WC_REG_GP2_STATUS_GP_2_2, &gp_speed); 5746 } else { 5747 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 5748 MDIO_WC_REG_GP2_STATUS_GP_2_3, &gp_speed); 5749 } 5750 DP(NETIF_MSG_LINK, "lane %d gp_speed 0x%x\n", lane, gp_speed); 5751 5752 if ((lane & 1) == 0) 5753 gp_speed <<= 8; 5754 gp_speed &= 0x3f00; 5755 link_up = !!link_up; 5756 5757 rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, gp_speed, 5758 duplex); 5759 5760 DP(NETIF_MSG_LINK, "duplex %x flow_ctrl 0x%x link_status 0x%x\n", 5761 vars->duplex, vars->flow_ctrl, vars->link_status); 5762 return rc; 5763 } 5764 static void bnx2x_set_gmii_tx_driver(struct link_params *params) 5765 { 5766 struct bnx2x *bp = params->bp; 5767 struct bnx2x_phy *phy = ¶ms->phy[INT_PHY]; 5768 u16 lp_up2; 5769 u16 tx_driver; 5770 u16 bank; 5771 5772 /* Read precomp */ 5773 CL22_RD_OVER_CL45(bp, phy, 5774 MDIO_REG_BANK_OVER_1G, 5775 MDIO_OVER_1G_LP_UP2, &lp_up2); 5776 5777 /* Bits [10:7] at lp_up2, positioned at [15:12] */ 5778 lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >> 5779 MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) << 5780 MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT); 5781 5782 if (lp_up2 == 0) 5783 return; 5784 5785 for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3; 5786 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) { 5787 CL22_RD_OVER_CL45(bp, phy, 5788 bank, 5789 MDIO_TX0_TX_DRIVER, &tx_driver); 5790 5791 /* Replace tx_driver bits [15:12] */ 5792 if (lp_up2 != 5793 (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) { 5794 tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK; 5795 tx_driver |= lp_up2; 5796 CL22_WR_OVER_CL45(bp, phy, 5797 bank, 5798 MDIO_TX0_TX_DRIVER, tx_driver); 5799 } 5800 } 5801 } 5802 5803 static int bnx2x_emac_program(struct link_params *params, 5804 struct link_vars *vars) 5805 { 5806 struct bnx2x *bp = params->bp; 5807 u8 port = params->port; 5808 u16 mode = 0; 5809 5810 DP(NETIF_MSG_LINK, "setting link speed & duplex\n"); 5811 bnx2x_bits_dis(bp, GRCBASE_EMAC0 + port*0x400 + 5812 EMAC_REG_EMAC_MODE, 5813 (EMAC_MODE_25G_MODE | 5814 EMAC_MODE_PORT_MII_10M | 5815 EMAC_MODE_HALF_DUPLEX)); 5816 switch (vars->line_speed) { 5817 case SPEED_10: 5818 mode |= EMAC_MODE_PORT_MII_10M; 5819 break; 5820 5821 case SPEED_100: 5822 mode |= EMAC_MODE_PORT_MII; 5823 break; 5824 5825 case SPEED_1000: 5826 mode |= EMAC_MODE_PORT_GMII; 5827 break; 5828 5829 case SPEED_2500: 5830 mode |= (EMAC_MODE_25G_MODE | EMAC_MODE_PORT_GMII); 5831 break; 5832 5833 default: 5834 /* 10G not valid for EMAC */ 5835 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n", 5836 vars->line_speed); 5837 return -EINVAL; 5838 } 5839 5840 if (vars->duplex == DUPLEX_HALF) 5841 mode |= EMAC_MODE_HALF_DUPLEX; 5842 bnx2x_bits_en(bp, 5843 GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE, 5844 mode); 5845 5846 bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed); 5847 return 0; 5848 } 5849 5850 static void bnx2x_set_preemphasis(struct bnx2x_phy *phy, 5851 struct link_params *params) 5852 { 5853 5854 u16 bank, i = 0; 5855 struct bnx2x *bp = params->bp; 5856 5857 for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3; 5858 bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0), i++) { 5859 CL22_WR_OVER_CL45(bp, phy, 5860 bank, 5861 MDIO_RX0_RX_EQ_BOOST, 5862 phy->rx_preemphasis[i]); 5863 } 5864 5865 for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3; 5866 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) { 5867 CL22_WR_OVER_CL45(bp, phy, 5868 bank, 5869 MDIO_TX0_TX_DRIVER, 5870 phy->tx_preemphasis[i]); 5871 } 5872 } 5873 5874 static void bnx2x_xgxs_config_init(struct bnx2x_phy *phy, 5875 struct link_params *params, 5876 struct link_vars *vars) 5877 { 5878 struct bnx2x *bp = params->bp; 5879 u8 enable_cl73 = (SINGLE_MEDIA_DIRECT(params) || 5880 (params->loopback_mode == LOOPBACK_XGXS)); 5881 if (!(vars->phy_flags & PHY_SGMII_FLAG)) { 5882 if (SINGLE_MEDIA_DIRECT(params) && 5883 (params->feature_config_flags & 5884 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) 5885 bnx2x_set_preemphasis(phy, params); 5886 5887 /* Forced speed requested? */ 5888 if (vars->line_speed != SPEED_AUTO_NEG || 5889 (SINGLE_MEDIA_DIRECT(params) && 5890 params->loopback_mode == LOOPBACK_EXT)) { 5891 DP(NETIF_MSG_LINK, "not SGMII, no AN\n"); 5892 5893 /* Disable autoneg */ 5894 bnx2x_set_autoneg(phy, params, vars, 0); 5895 5896 /* Program speed and duplex */ 5897 bnx2x_program_serdes(phy, params, vars); 5898 5899 } else { /* AN_mode */ 5900 DP(NETIF_MSG_LINK, "not SGMII, AN\n"); 5901 5902 /* AN enabled */ 5903 bnx2x_set_brcm_cl37_advertisement(phy, params); 5904 5905 /* Program duplex & pause advertisement (for aneg) */ 5906 bnx2x_set_ieee_aneg_advertisement(phy, params, 5907 vars->ieee_fc); 5908 5909 /* Enable autoneg */ 5910 bnx2x_set_autoneg(phy, params, vars, enable_cl73); 5911 5912 /* Enable and restart AN */ 5913 bnx2x_restart_autoneg(phy, params, enable_cl73); 5914 } 5915 5916 } else { /* SGMII mode */ 5917 DP(NETIF_MSG_LINK, "SGMII\n"); 5918 5919 bnx2x_initialize_sgmii_process(phy, params, vars); 5920 } 5921 } 5922 5923 static int bnx2x_prepare_xgxs(struct bnx2x_phy *phy, 5924 struct link_params *params, 5925 struct link_vars *vars) 5926 { 5927 int rc; 5928 vars->phy_flags |= PHY_XGXS_FLAG; 5929 if ((phy->req_line_speed && 5930 ((phy->req_line_speed == SPEED_100) || 5931 (phy->req_line_speed == SPEED_10))) || 5932 (!phy->req_line_speed && 5933 (phy->speed_cap_mask >= 5934 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) && 5935 (phy->speed_cap_mask < 5936 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) || 5937 (phy->type == PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD)) 5938 vars->phy_flags |= PHY_SGMII_FLAG; 5939 else 5940 vars->phy_flags &= ~PHY_SGMII_FLAG; 5941 5942 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); 5943 bnx2x_set_aer_mmd(params, phy); 5944 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) 5945 bnx2x_set_master_ln(params, phy); 5946 5947 rc = bnx2x_reset_unicore(params, phy, 0); 5948 /* Reset the SerDes and wait for reset bit return low */ 5949 if (rc) 5950 return rc; 5951 5952 bnx2x_set_aer_mmd(params, phy); 5953 /* Setting the masterLn_def again after the reset */ 5954 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) { 5955 bnx2x_set_master_ln(params, phy); 5956 bnx2x_set_swap_lanes(params, phy); 5957 } 5958 5959 return rc; 5960 } 5961 5962 static u16 bnx2x_wait_reset_complete(struct bnx2x *bp, 5963 struct bnx2x_phy *phy, 5964 struct link_params *params) 5965 { 5966 u16 cnt, ctrl; 5967 /* Wait for soft reset to get cleared up to 1 sec */ 5968 for (cnt = 0; cnt < 1000; cnt++) { 5969 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) 5970 bnx2x_cl22_read(bp, phy, 5971 MDIO_PMA_REG_CTRL, &ctrl); 5972 else 5973 bnx2x_cl45_read(bp, phy, 5974 MDIO_PMA_DEVAD, 5975 MDIO_PMA_REG_CTRL, &ctrl); 5976 if (!(ctrl & (1<<15))) 5977 break; 5978 usleep_range(1000, 2000); 5979 } 5980 5981 if (cnt == 1000) 5982 netdev_err(bp->dev, "Warning: PHY was not initialized," 5983 " Port %d\n", 5984 params->port); 5985 DP(NETIF_MSG_LINK, "control reg 0x%x (after %d ms)\n", ctrl, cnt); 5986 return cnt; 5987 } 5988 5989 static void bnx2x_link_int_enable(struct link_params *params) 5990 { 5991 u8 port = params->port; 5992 u32 mask; 5993 struct bnx2x *bp = params->bp; 5994 5995 /* Setting the status to report on link up for either XGXS or SerDes */ 5996 if (CHIP_IS_E3(bp)) { 5997 mask = NIG_MASK_XGXS0_LINK_STATUS; 5998 if (!(SINGLE_MEDIA_DIRECT(params))) 5999 mask |= NIG_MASK_MI_INT; 6000 } else if (params->switch_cfg == SWITCH_CFG_10G) { 6001 mask = (NIG_MASK_XGXS0_LINK10G | 6002 NIG_MASK_XGXS0_LINK_STATUS); 6003 DP(NETIF_MSG_LINK, "enabled XGXS interrupt\n"); 6004 if (!(SINGLE_MEDIA_DIRECT(params)) && 6005 params->phy[INT_PHY].type != 6006 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) { 6007 mask |= NIG_MASK_MI_INT; 6008 DP(NETIF_MSG_LINK, "enabled external phy int\n"); 6009 } 6010 6011 } else { /* SerDes */ 6012 mask = NIG_MASK_SERDES0_LINK_STATUS; 6013 DP(NETIF_MSG_LINK, "enabled SerDes interrupt\n"); 6014 if (!(SINGLE_MEDIA_DIRECT(params)) && 6015 params->phy[INT_PHY].type != 6016 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN) { 6017 mask |= NIG_MASK_MI_INT; 6018 DP(NETIF_MSG_LINK, "enabled external phy int\n"); 6019 } 6020 } 6021 bnx2x_bits_en(bp, 6022 NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 6023 mask); 6024 6025 DP(NETIF_MSG_LINK, "port %x, is_xgxs %x, int_status 0x%x\n", port, 6026 (params->switch_cfg == SWITCH_CFG_10G), 6027 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4)); 6028 DP(NETIF_MSG_LINK, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x\n", 6029 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4), 6030 REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18), 6031 REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS+port*0x3c)); 6032 DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n", 6033 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68), 6034 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68)); 6035 } 6036 6037 static void bnx2x_rearm_latch_signal(struct bnx2x *bp, u8 port, 6038 u8 exp_mi_int) 6039 { 6040 u32 latch_status = 0; 6041 6042 /* Disable the MI INT ( external phy int ) by writing 1 to the 6043 * status register. Link down indication is high-active-signal, 6044 * so in this case we need to write the status to clear the XOR 6045 */ 6046 /* Read Latched signals */ 6047 latch_status = REG_RD(bp, 6048 NIG_REG_LATCH_STATUS_0 + port*8); 6049 DP(NETIF_MSG_LINK, "latch_status = 0x%x\n", latch_status); 6050 /* Handle only those with latched-signal=up.*/ 6051 if (exp_mi_int) 6052 bnx2x_bits_en(bp, 6053 NIG_REG_STATUS_INTERRUPT_PORT0 6054 + port*4, 6055 NIG_STATUS_EMAC0_MI_INT); 6056 else 6057 bnx2x_bits_dis(bp, 6058 NIG_REG_STATUS_INTERRUPT_PORT0 6059 + port*4, 6060 NIG_STATUS_EMAC0_MI_INT); 6061 6062 if (latch_status & 1) { 6063 6064 /* For all latched-signal=up : Re-Arm Latch signals */ 6065 REG_WR(bp, NIG_REG_LATCH_STATUS_0 + port*8, 6066 (latch_status & 0xfffe) | (latch_status & 1)); 6067 } 6068 /* For all latched-signal=up,Write original_signal to status */ 6069 } 6070 6071 static void bnx2x_link_int_ack(struct link_params *params, 6072 struct link_vars *vars, u8 is_10g_plus) 6073 { 6074 struct bnx2x *bp = params->bp; 6075 u8 port = params->port; 6076 u32 mask; 6077 /* First reset all status we assume only one line will be 6078 * change at a time 6079 */ 6080 bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4, 6081 (NIG_STATUS_XGXS0_LINK10G | 6082 NIG_STATUS_XGXS0_LINK_STATUS | 6083 NIG_STATUS_SERDES0_LINK_STATUS)); 6084 if (vars->phy_link_up) { 6085 if (USES_WARPCORE(bp)) 6086 mask = NIG_STATUS_XGXS0_LINK_STATUS; 6087 else { 6088 if (is_10g_plus) 6089 mask = NIG_STATUS_XGXS0_LINK10G; 6090 else if (params->switch_cfg == SWITCH_CFG_10G) { 6091 /* Disable the link interrupt by writing 1 to 6092 * the relevant lane in the status register 6093 */ 6094 u32 ser_lane = 6095 ((params->lane_config & 6096 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >> 6097 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT); 6098 mask = ((1 << ser_lane) << 6099 NIG_STATUS_XGXS0_LINK_STATUS_SIZE); 6100 } else 6101 mask = NIG_STATUS_SERDES0_LINK_STATUS; 6102 } 6103 DP(NETIF_MSG_LINK, "Ack link up interrupt with mask 0x%x\n", 6104 mask); 6105 bnx2x_bits_en(bp, 6106 NIG_REG_STATUS_INTERRUPT_PORT0 + port*4, 6107 mask); 6108 } 6109 } 6110 6111 static int bnx2x_format_ver(u32 num, u8 *str, u16 *len) 6112 { 6113 u8 *str_ptr = str; 6114 u32 mask = 0xf0000000; 6115 u8 shift = 8*4; 6116 u8 digit; 6117 u8 remove_leading_zeros = 1; 6118 if (*len < 10) { 6119 /* Need more than 10chars for this format */ 6120 *str_ptr = '\0'; 6121 (*len)--; 6122 return -EINVAL; 6123 } 6124 while (shift > 0) { 6125 6126 shift -= 4; 6127 digit = ((num & mask) >> shift); 6128 if (digit == 0 && remove_leading_zeros) { 6129 mask = mask >> 4; 6130 continue; 6131 } else if (digit < 0xa) 6132 *str_ptr = digit + '0'; 6133 else 6134 *str_ptr = digit - 0xa + 'a'; 6135 remove_leading_zeros = 0; 6136 str_ptr++; 6137 (*len)--; 6138 mask = mask >> 4; 6139 if (shift == 4*4) { 6140 *str_ptr = '.'; 6141 str_ptr++; 6142 (*len)--; 6143 remove_leading_zeros = 1; 6144 } 6145 } 6146 return 0; 6147 } 6148 6149 6150 static int bnx2x_null_format_ver(u32 spirom_ver, u8 *str, u16 *len) 6151 { 6152 str[0] = '\0'; 6153 (*len)--; 6154 return 0; 6155 } 6156 6157 int bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 *version, 6158 u16 len) 6159 { 6160 struct bnx2x *bp; 6161 u32 spirom_ver = 0; 6162 int status = 0; 6163 u8 *ver_p = version; 6164 u16 remain_len = len; 6165 if (version == NULL || params == NULL) 6166 return -EINVAL; 6167 bp = params->bp; 6168 6169 /* Extract first external phy*/ 6170 version[0] = '\0'; 6171 spirom_ver = REG_RD(bp, params->phy[EXT_PHY1].ver_addr); 6172 6173 if (params->phy[EXT_PHY1].format_fw_ver) { 6174 status |= params->phy[EXT_PHY1].format_fw_ver(spirom_ver, 6175 ver_p, 6176 &remain_len); 6177 ver_p += (len - remain_len); 6178 } 6179 if ((params->num_phys == MAX_PHYS) && 6180 (params->phy[EXT_PHY2].ver_addr != 0)) { 6181 spirom_ver = REG_RD(bp, params->phy[EXT_PHY2].ver_addr); 6182 if (params->phy[EXT_PHY2].format_fw_ver) { 6183 *ver_p = '/'; 6184 ver_p++; 6185 remain_len--; 6186 status |= params->phy[EXT_PHY2].format_fw_ver( 6187 spirom_ver, 6188 ver_p, 6189 &remain_len); 6190 ver_p = version + (len - remain_len); 6191 } 6192 } 6193 *ver_p = '\0'; 6194 return status; 6195 } 6196 6197 static void bnx2x_set_xgxs_loopback(struct bnx2x_phy *phy, 6198 struct link_params *params) 6199 { 6200 u8 port = params->port; 6201 struct bnx2x *bp = params->bp; 6202 6203 if (phy->req_line_speed != SPEED_1000) { 6204 u32 md_devad = 0; 6205 6206 DP(NETIF_MSG_LINK, "XGXS 10G loopback enable\n"); 6207 6208 if (!CHIP_IS_E3(bp)) { 6209 /* Change the uni_phy_addr in the nig */ 6210 md_devad = REG_RD(bp, (NIG_REG_XGXS0_CTRL_MD_DEVAD + 6211 port*0x18)); 6212 6213 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, 6214 0x5); 6215 } 6216 6217 bnx2x_cl45_write(bp, phy, 6218 5, 6219 (MDIO_REG_BANK_AER_BLOCK + 6220 (MDIO_AER_BLOCK_AER_REG & 0xf)), 6221 0x2800); 6222 6223 bnx2x_cl45_write(bp, phy, 6224 5, 6225 (MDIO_REG_BANK_CL73_IEEEB0 + 6226 (MDIO_CL73_IEEEB0_CL73_AN_CONTROL & 0xf)), 6227 0x6041); 6228 msleep(200); 6229 /* Set aer mmd back */ 6230 bnx2x_set_aer_mmd(params, phy); 6231 6232 if (!CHIP_IS_E3(bp)) { 6233 /* And md_devad */ 6234 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, 6235 md_devad); 6236 } 6237 } else { 6238 u16 mii_ctrl; 6239 DP(NETIF_MSG_LINK, "XGXS 1G loopback enable\n"); 6240 bnx2x_cl45_read(bp, phy, 5, 6241 (MDIO_REG_BANK_COMBO_IEEE0 + 6242 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)), 6243 &mii_ctrl); 6244 bnx2x_cl45_write(bp, phy, 5, 6245 (MDIO_REG_BANK_COMBO_IEEE0 + 6246 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)), 6247 mii_ctrl | 6248 MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK); 6249 } 6250 } 6251 6252 int bnx2x_set_led(struct link_params *params, 6253 struct link_vars *vars, u8 mode, u32 speed) 6254 { 6255 u8 port = params->port; 6256 u16 hw_led_mode = params->hw_led_mode; 6257 int rc = 0; 6258 u8 phy_idx; 6259 u32 tmp; 6260 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; 6261 struct bnx2x *bp = params->bp; 6262 DP(NETIF_MSG_LINK, "bnx2x_set_led: port %x, mode %d\n", port, mode); 6263 DP(NETIF_MSG_LINK, "speed 0x%x, hw_led_mode 0x%x\n", 6264 speed, hw_led_mode); 6265 /* In case */ 6266 for (phy_idx = EXT_PHY1; phy_idx < MAX_PHYS; phy_idx++) { 6267 if (params->phy[phy_idx].set_link_led) { 6268 params->phy[phy_idx].set_link_led( 6269 ¶ms->phy[phy_idx], params, mode); 6270 } 6271 } 6272 6273 switch (mode) { 6274 case LED_MODE_FRONT_PANEL_OFF: 6275 case LED_MODE_OFF: 6276 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 0); 6277 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 6278 SHARED_HW_CFG_LED_MAC1); 6279 6280 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED); 6281 if (params->phy[EXT_PHY1].type == 6282 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) 6283 tmp &= ~(EMAC_LED_1000MB_OVERRIDE | 6284 EMAC_LED_100MB_OVERRIDE | 6285 EMAC_LED_10MB_OVERRIDE); 6286 else 6287 tmp |= EMAC_LED_OVERRIDE; 6288 6289 EMAC_WR(bp, EMAC_REG_EMAC_LED, tmp); 6290 break; 6291 6292 case LED_MODE_OPER: 6293 /* For all other phys, OPER mode is same as ON, so in case 6294 * link is down, do nothing 6295 */ 6296 if (!vars->link_up) 6297 break; 6298 case LED_MODE_ON: 6299 if (((params->phy[EXT_PHY1].type == 6300 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) || 6301 (params->phy[EXT_PHY1].type == 6302 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722)) && 6303 CHIP_IS_E2(bp) && params->num_phys == 2) { 6304 /* This is a work-around for E2+8727 Configurations */ 6305 if (mode == LED_MODE_ON || 6306 speed == SPEED_10000){ 6307 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0); 6308 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1); 6309 6310 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED); 6311 EMAC_WR(bp, EMAC_REG_EMAC_LED, 6312 (tmp | EMAC_LED_OVERRIDE)); 6313 /* Return here without enabling traffic 6314 * LED blink and setting rate in ON mode. 6315 * In oper mode, enabling LED blink 6316 * and setting rate is needed. 6317 */ 6318 if (mode == LED_MODE_ON) 6319 return rc; 6320 } 6321 } else if (SINGLE_MEDIA_DIRECT(params)) { 6322 /* This is a work-around for HW issue found when link 6323 * is up in CL73 6324 */ 6325 if ((!CHIP_IS_E3(bp)) || 6326 (CHIP_IS_E3(bp) && 6327 mode == LED_MODE_ON)) 6328 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1); 6329 6330 if (CHIP_IS_E1x(bp) || 6331 CHIP_IS_E2(bp) || 6332 (mode == LED_MODE_ON)) 6333 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0); 6334 else 6335 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 6336 hw_led_mode); 6337 } else if ((params->phy[EXT_PHY1].type == 6338 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) && 6339 (mode == LED_MODE_ON)) { 6340 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0); 6341 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED); 6342 EMAC_WR(bp, EMAC_REG_EMAC_LED, tmp | 6343 EMAC_LED_OVERRIDE | EMAC_LED_1000MB_OVERRIDE); 6344 /* Break here; otherwise, it'll disable the 6345 * intended override. 6346 */ 6347 break; 6348 } else 6349 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 6350 hw_led_mode); 6351 6352 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 0); 6353 /* Set blinking rate to ~15.9Hz */ 6354 if (CHIP_IS_E3(bp)) 6355 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4, 6356 LED_BLINK_RATE_VAL_E3); 6357 else 6358 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4, 6359 LED_BLINK_RATE_VAL_E1X_E2); 6360 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 + 6361 port*4, 1); 6362 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED); 6363 EMAC_WR(bp, EMAC_REG_EMAC_LED, 6364 (tmp & (~EMAC_LED_OVERRIDE))); 6365 6366 if (CHIP_IS_E1(bp) && 6367 ((speed == SPEED_2500) || 6368 (speed == SPEED_1000) || 6369 (speed == SPEED_100) || 6370 (speed == SPEED_10))) { 6371 /* For speeds less than 10G LED scheme is different */ 6372 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 6373 + port*4, 1); 6374 REG_WR(bp, NIG_REG_LED_CONTROL_TRAFFIC_P0 + 6375 port*4, 0); 6376 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 + 6377 port*4, 1); 6378 } 6379 break; 6380 6381 default: 6382 rc = -EINVAL; 6383 DP(NETIF_MSG_LINK, "bnx2x_set_led: Invalid led mode %d\n", 6384 mode); 6385 break; 6386 } 6387 return rc; 6388 6389 } 6390 6391 /* This function comes to reflect the actual link state read DIRECTLY from the 6392 * HW 6393 */ 6394 int bnx2x_test_link(struct link_params *params, struct link_vars *vars, 6395 u8 is_serdes) 6396 { 6397 struct bnx2x *bp = params->bp; 6398 u16 gp_status = 0, phy_index = 0; 6399 u8 ext_phy_link_up = 0, serdes_phy_type; 6400 struct link_vars temp_vars; 6401 struct bnx2x_phy *int_phy = ¶ms->phy[INT_PHY]; 6402 6403 if (CHIP_IS_E3(bp)) { 6404 u16 link_up; 6405 if (params->req_line_speed[LINK_CONFIG_IDX(INT_PHY)] 6406 > SPEED_10000) { 6407 /* Check 20G link */ 6408 bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD, 6409 1, &link_up); 6410 bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD, 6411 1, &link_up); 6412 link_up &= (1<<2); 6413 } else { 6414 /* Check 10G link and below*/ 6415 u8 lane = bnx2x_get_warpcore_lane(int_phy, params); 6416 bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD, 6417 MDIO_WC_REG_GP2_STATUS_GP_2_1, 6418 &gp_status); 6419 gp_status = ((gp_status >> 8) & 0xf) | 6420 ((gp_status >> 12) & 0xf); 6421 link_up = gp_status & (1 << lane); 6422 } 6423 if (!link_up) 6424 return -ESRCH; 6425 } else { 6426 CL22_RD_OVER_CL45(bp, int_phy, 6427 MDIO_REG_BANK_GP_STATUS, 6428 MDIO_GP_STATUS_TOP_AN_STATUS1, 6429 &gp_status); 6430 /* Link is up only if both local phy and external phy are up */ 6431 if (!(gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS)) 6432 return -ESRCH; 6433 } 6434 /* In XGXS loopback mode, do not check external PHY */ 6435 if (params->loopback_mode == LOOPBACK_XGXS) 6436 return 0; 6437 6438 switch (params->num_phys) { 6439 case 1: 6440 /* No external PHY */ 6441 return 0; 6442 case 2: 6443 ext_phy_link_up = params->phy[EXT_PHY1].read_status( 6444 ¶ms->phy[EXT_PHY1], 6445 params, &temp_vars); 6446 break; 6447 case 3: /* Dual Media */ 6448 for (phy_index = EXT_PHY1; phy_index < params->num_phys; 6449 phy_index++) { 6450 serdes_phy_type = ((params->phy[phy_index].media_type == 6451 ETH_PHY_SFPP_10G_FIBER) || 6452 (params->phy[phy_index].media_type == 6453 ETH_PHY_SFP_1G_FIBER) || 6454 (params->phy[phy_index].media_type == 6455 ETH_PHY_XFP_FIBER) || 6456 (params->phy[phy_index].media_type == 6457 ETH_PHY_DA_TWINAX)); 6458 6459 if (is_serdes != serdes_phy_type) 6460 continue; 6461 if (params->phy[phy_index].read_status) { 6462 ext_phy_link_up |= 6463 params->phy[phy_index].read_status( 6464 ¶ms->phy[phy_index], 6465 params, &temp_vars); 6466 } 6467 } 6468 break; 6469 } 6470 if (ext_phy_link_up) 6471 return 0; 6472 return -ESRCH; 6473 } 6474 6475 static int bnx2x_link_initialize(struct link_params *params, 6476 struct link_vars *vars) 6477 { 6478 int rc = 0; 6479 u8 phy_index, non_ext_phy; 6480 struct bnx2x *bp = params->bp; 6481 /* In case of external phy existence, the line speed would be the 6482 * line speed linked up by the external phy. In case it is direct 6483 * only, then the line_speed during initialization will be 6484 * equal to the req_line_speed 6485 */ 6486 vars->line_speed = params->phy[INT_PHY].req_line_speed; 6487 6488 /* Initialize the internal phy in case this is a direct board 6489 * (no external phys), or this board has external phy which requires 6490 * to first. 6491 */ 6492 if (!USES_WARPCORE(bp)) 6493 bnx2x_prepare_xgxs(¶ms->phy[INT_PHY], params, vars); 6494 /* init ext phy and enable link state int */ 6495 non_ext_phy = (SINGLE_MEDIA_DIRECT(params) || 6496 (params->loopback_mode == LOOPBACK_XGXS)); 6497 6498 if (non_ext_phy || 6499 (params->phy[EXT_PHY1].flags & FLAGS_INIT_XGXS_FIRST) || 6500 (params->loopback_mode == LOOPBACK_EXT_PHY)) { 6501 struct bnx2x_phy *phy = ¶ms->phy[INT_PHY]; 6502 if (vars->line_speed == SPEED_AUTO_NEG && 6503 (CHIP_IS_E1x(bp) || 6504 CHIP_IS_E2(bp))) 6505 bnx2x_set_parallel_detection(phy, params); 6506 if (params->phy[INT_PHY].config_init) 6507 params->phy[INT_PHY].config_init(phy, params, vars); 6508 } 6509 6510 /* Init external phy*/ 6511 if (non_ext_phy) { 6512 if (params->phy[INT_PHY].supported & 6513 SUPPORTED_FIBRE) 6514 vars->link_status |= LINK_STATUS_SERDES_LINK; 6515 } else { 6516 for (phy_index = EXT_PHY1; phy_index < params->num_phys; 6517 phy_index++) { 6518 /* No need to initialize second phy in case of first 6519 * phy only selection. In case of second phy, we do 6520 * need to initialize the first phy, since they are 6521 * connected. 6522 */ 6523 if (params->phy[phy_index].supported & 6524 SUPPORTED_FIBRE) 6525 vars->link_status |= LINK_STATUS_SERDES_LINK; 6526 6527 if (phy_index == EXT_PHY2 && 6528 (bnx2x_phy_selection(params) == 6529 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY)) { 6530 DP(NETIF_MSG_LINK, 6531 "Not initializing second phy\n"); 6532 continue; 6533 } 6534 params->phy[phy_index].config_init( 6535 ¶ms->phy[phy_index], 6536 params, vars); 6537 } 6538 } 6539 /* Reset the interrupt indication after phy was initialized */ 6540 bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + 6541 params->port*4, 6542 (NIG_STATUS_XGXS0_LINK10G | 6543 NIG_STATUS_XGXS0_LINK_STATUS | 6544 NIG_STATUS_SERDES0_LINK_STATUS | 6545 NIG_MASK_MI_INT)); 6546 return rc; 6547 } 6548 6549 static void bnx2x_int_link_reset(struct bnx2x_phy *phy, 6550 struct link_params *params) 6551 { 6552 /* Reset the SerDes/XGXS */ 6553 REG_WR(params->bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, 6554 (0x1ff << (params->port*16))); 6555 } 6556 6557 static void bnx2x_common_ext_link_reset(struct bnx2x_phy *phy, 6558 struct link_params *params) 6559 { 6560 struct bnx2x *bp = params->bp; 6561 u8 gpio_port; 6562 /* HW reset */ 6563 if (CHIP_IS_E2(bp)) 6564 gpio_port = BP_PATH(bp); 6565 else 6566 gpio_port = params->port; 6567 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, 6568 MISC_REGISTERS_GPIO_OUTPUT_LOW, 6569 gpio_port); 6570 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 6571 MISC_REGISTERS_GPIO_OUTPUT_LOW, 6572 gpio_port); 6573 DP(NETIF_MSG_LINK, "reset external PHY\n"); 6574 } 6575 6576 static int bnx2x_update_link_down(struct link_params *params, 6577 struct link_vars *vars) 6578 { 6579 struct bnx2x *bp = params->bp; 6580 u8 port = params->port; 6581 6582 DP(NETIF_MSG_LINK, "Port %x: Link is down\n", port); 6583 bnx2x_set_led(params, vars, LED_MODE_OFF, 0); 6584 vars->phy_flags &= ~PHY_PHYSICAL_LINK_FLAG; 6585 /* Indicate no mac active */ 6586 vars->mac_type = MAC_TYPE_NONE; 6587 6588 /* Update shared memory */ 6589 vars->link_status &= ~LINK_UPDATE_MASK; 6590 vars->line_speed = 0; 6591 bnx2x_update_mng(params, vars->link_status); 6592 6593 /* Activate nig drain */ 6594 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1); 6595 6596 /* Disable emac */ 6597 if (!CHIP_IS_E3(bp)) 6598 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0); 6599 6600 usleep_range(10000, 20000); 6601 /* Reset BigMac/Xmac */ 6602 if (CHIP_IS_E1x(bp) || 6603 CHIP_IS_E2(bp)) 6604 bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 0); 6605 6606 if (CHIP_IS_E3(bp)) { 6607 /* Prevent LPI Generation by chip */ 6608 REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2), 6609 0); 6610 REG_WR(bp, MISC_REG_CPMU_LP_MASK_ENT_P0 + (params->port << 2), 6611 0); 6612 vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK | 6613 SHMEM_EEE_ACTIVE_BIT); 6614 6615 bnx2x_update_mng_eee(params, vars->eee_status); 6616 bnx2x_set_xmac_rxtx(params, 0); 6617 bnx2x_set_umac_rxtx(params, 0); 6618 } 6619 6620 return 0; 6621 } 6622 6623 static int bnx2x_update_link_up(struct link_params *params, 6624 struct link_vars *vars, 6625 u8 link_10g) 6626 { 6627 struct bnx2x *bp = params->bp; 6628 u8 phy_idx, port = params->port; 6629 int rc = 0; 6630 6631 vars->link_status |= (LINK_STATUS_LINK_UP | 6632 LINK_STATUS_PHYSICAL_LINK_FLAG); 6633 vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG; 6634 6635 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) 6636 vars->link_status |= 6637 LINK_STATUS_TX_FLOW_CONTROL_ENABLED; 6638 6639 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX) 6640 vars->link_status |= 6641 LINK_STATUS_RX_FLOW_CONTROL_ENABLED; 6642 if (USES_WARPCORE(bp)) { 6643 if (link_10g) { 6644 if (bnx2x_xmac_enable(params, vars, 0) == 6645 -ESRCH) { 6646 DP(NETIF_MSG_LINK, "Found errors on XMAC\n"); 6647 vars->link_up = 0; 6648 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG; 6649 vars->link_status &= ~LINK_STATUS_LINK_UP; 6650 } 6651 } else 6652 bnx2x_umac_enable(params, vars, 0); 6653 bnx2x_set_led(params, vars, 6654 LED_MODE_OPER, vars->line_speed); 6655 6656 if ((vars->eee_status & SHMEM_EEE_ACTIVE_BIT) && 6657 (vars->eee_status & SHMEM_EEE_LPI_REQUESTED_BIT)) { 6658 DP(NETIF_MSG_LINK, "Enabling LPI assertion\n"); 6659 REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + 6660 (params->port << 2), 1); 6661 REG_WR(bp, MISC_REG_CPMU_LP_DR_ENABLE, 1); 6662 REG_WR(bp, MISC_REG_CPMU_LP_MASK_ENT_P0 + 6663 (params->port << 2), 0xfc20); 6664 } 6665 } 6666 if ((CHIP_IS_E1x(bp) || 6667 CHIP_IS_E2(bp))) { 6668 if (link_10g) { 6669 if (bnx2x_bmac_enable(params, vars, 0, 1) == 6670 -ESRCH) { 6671 DP(NETIF_MSG_LINK, "Found errors on BMAC\n"); 6672 vars->link_up = 0; 6673 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG; 6674 vars->link_status &= ~LINK_STATUS_LINK_UP; 6675 } 6676 6677 bnx2x_set_led(params, vars, 6678 LED_MODE_OPER, SPEED_10000); 6679 } else { 6680 rc = bnx2x_emac_program(params, vars); 6681 bnx2x_emac_enable(params, vars, 0); 6682 6683 /* AN complete? */ 6684 if ((vars->link_status & 6685 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) 6686 && (!(vars->phy_flags & PHY_SGMII_FLAG)) && 6687 SINGLE_MEDIA_DIRECT(params)) 6688 bnx2x_set_gmii_tx_driver(params); 6689 } 6690 } 6691 6692 /* PBF - link up */ 6693 if (CHIP_IS_E1x(bp)) 6694 rc |= bnx2x_pbf_update(params, vars->flow_ctrl, 6695 vars->line_speed); 6696 6697 /* Disable drain */ 6698 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0); 6699 6700 /* Update shared memory */ 6701 bnx2x_update_mng(params, vars->link_status); 6702 bnx2x_update_mng_eee(params, vars->eee_status); 6703 /* Check remote fault */ 6704 for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) { 6705 if (params->phy[phy_idx].flags & FLAGS_TX_ERROR_CHECK) { 6706 bnx2x_check_half_open_conn(params, vars, 0); 6707 break; 6708 } 6709 } 6710 msleep(20); 6711 return rc; 6712 } 6713 /* The bnx2x_link_update function should be called upon link 6714 * interrupt. 6715 * Link is considered up as follows: 6716 * - DIRECT_SINGLE_MEDIA - Only XGXS link (internal link) needs 6717 * to be up 6718 * - SINGLE_MEDIA - The link between the 577xx and the external 6719 * phy (XGXS) need to up as well as the external link of the 6720 * phy (PHY_EXT1) 6721 * - DUAL_MEDIA - The link between the 577xx and the first 6722 * external phy needs to be up, and at least one of the 2 6723 * external phy link must be up. 6724 */ 6725 int bnx2x_link_update(struct link_params *params, struct link_vars *vars) 6726 { 6727 struct bnx2x *bp = params->bp; 6728 struct link_vars phy_vars[MAX_PHYS]; 6729 u8 port = params->port; 6730 u8 link_10g_plus, phy_index; 6731 u8 ext_phy_link_up = 0, cur_link_up; 6732 int rc = 0; 6733 u8 is_mi_int = 0; 6734 u16 ext_phy_line_speed = 0, prev_line_speed = vars->line_speed; 6735 u8 active_external_phy = INT_PHY; 6736 vars->phy_flags &= ~PHY_HALF_OPEN_CONN_FLAG; 6737 vars->link_status &= ~LINK_UPDATE_MASK; 6738 for (phy_index = INT_PHY; phy_index < params->num_phys; 6739 phy_index++) { 6740 phy_vars[phy_index].flow_ctrl = 0; 6741 phy_vars[phy_index].link_status = 0; 6742 phy_vars[phy_index].line_speed = 0; 6743 phy_vars[phy_index].duplex = DUPLEX_FULL; 6744 phy_vars[phy_index].phy_link_up = 0; 6745 phy_vars[phy_index].link_up = 0; 6746 phy_vars[phy_index].fault_detected = 0; 6747 /* different consideration, since vars holds inner state */ 6748 phy_vars[phy_index].eee_status = vars->eee_status; 6749 } 6750 6751 if (USES_WARPCORE(bp)) 6752 bnx2x_set_aer_mmd(params, ¶ms->phy[INT_PHY]); 6753 6754 DP(NETIF_MSG_LINK, "port %x, XGXS?%x, int_status 0x%x\n", 6755 port, (vars->phy_flags & PHY_XGXS_FLAG), 6756 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4)); 6757 6758 is_mi_int = (u8)(REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + 6759 port*0x18) > 0); 6760 DP(NETIF_MSG_LINK, "int_mask 0x%x MI_INT %x, SERDES_LINK %x\n", 6761 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4), 6762 is_mi_int, 6763 REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c)); 6764 6765 DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n", 6766 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68), 6767 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68)); 6768 6769 /* Disable emac */ 6770 if (!CHIP_IS_E3(bp)) 6771 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0); 6772 6773 /* Step 1: 6774 * Check external link change only for external phys, and apply 6775 * priority selection between them in case the link on both phys 6776 * is up. Note that instead of the common vars, a temporary 6777 * vars argument is used since each phy may have different link/ 6778 * speed/duplex result 6779 */ 6780 for (phy_index = EXT_PHY1; phy_index < params->num_phys; 6781 phy_index++) { 6782 struct bnx2x_phy *phy = ¶ms->phy[phy_index]; 6783 if (!phy->read_status) 6784 continue; 6785 /* Read link status and params of this ext phy */ 6786 cur_link_up = phy->read_status(phy, params, 6787 &phy_vars[phy_index]); 6788 if (cur_link_up) { 6789 DP(NETIF_MSG_LINK, "phy in index %d link is up\n", 6790 phy_index); 6791 } else { 6792 DP(NETIF_MSG_LINK, "phy in index %d link is down\n", 6793 phy_index); 6794 continue; 6795 } 6796 6797 if (!ext_phy_link_up) { 6798 ext_phy_link_up = 1; 6799 active_external_phy = phy_index; 6800 } else { 6801 switch (bnx2x_phy_selection(params)) { 6802 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT: 6803 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY: 6804 /* In this option, the first PHY makes sure to pass the 6805 * traffic through itself only. 6806 * Its not clear how to reset the link on the second phy 6807 */ 6808 active_external_phy = EXT_PHY1; 6809 break; 6810 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY: 6811 /* In this option, the first PHY makes sure to pass the 6812 * traffic through the second PHY. 6813 */ 6814 active_external_phy = EXT_PHY2; 6815 break; 6816 default: 6817 /* Link indication on both PHYs with the following cases 6818 * is invalid: 6819 * - FIRST_PHY means that second phy wasn't initialized, 6820 * hence its link is expected to be down 6821 * - SECOND_PHY means that first phy should not be able 6822 * to link up by itself (using configuration) 6823 * - DEFAULT should be overriden during initialiazation 6824 */ 6825 DP(NETIF_MSG_LINK, "Invalid link indication" 6826 "mpc=0x%x. DISABLING LINK !!!\n", 6827 params->multi_phy_config); 6828 ext_phy_link_up = 0; 6829 break; 6830 } 6831 } 6832 } 6833 prev_line_speed = vars->line_speed; 6834 /* Step 2: 6835 * Read the status of the internal phy. In case of 6836 * DIRECT_SINGLE_MEDIA board, this link is the external link, 6837 * otherwise this is the link between the 577xx and the first 6838 * external phy 6839 */ 6840 if (params->phy[INT_PHY].read_status) 6841 params->phy[INT_PHY].read_status( 6842 ¶ms->phy[INT_PHY], 6843 params, vars); 6844 /* The INT_PHY flow control reside in the vars. This include the 6845 * case where the speed or flow control are not set to AUTO. 6846 * Otherwise, the active external phy flow control result is set 6847 * to the vars. The ext_phy_line_speed is needed to check if the 6848 * speed is different between the internal phy and external phy. 6849 * This case may be result of intermediate link speed change. 6850 */ 6851 if (active_external_phy > INT_PHY) { 6852 vars->flow_ctrl = phy_vars[active_external_phy].flow_ctrl; 6853 /* Link speed is taken from the XGXS. AN and FC result from 6854 * the external phy. 6855 */ 6856 vars->link_status |= phy_vars[active_external_phy].link_status; 6857 6858 /* if active_external_phy is first PHY and link is up - disable 6859 * disable TX on second external PHY 6860 */ 6861 if (active_external_phy == EXT_PHY1) { 6862 if (params->phy[EXT_PHY2].phy_specific_func) { 6863 DP(NETIF_MSG_LINK, 6864 "Disabling TX on EXT_PHY2\n"); 6865 params->phy[EXT_PHY2].phy_specific_func( 6866 ¶ms->phy[EXT_PHY2], 6867 params, DISABLE_TX); 6868 } 6869 } 6870 6871 ext_phy_line_speed = phy_vars[active_external_phy].line_speed; 6872 vars->duplex = phy_vars[active_external_phy].duplex; 6873 if (params->phy[active_external_phy].supported & 6874 SUPPORTED_FIBRE) 6875 vars->link_status |= LINK_STATUS_SERDES_LINK; 6876 else 6877 vars->link_status &= ~LINK_STATUS_SERDES_LINK; 6878 6879 vars->eee_status = phy_vars[active_external_phy].eee_status; 6880 6881 DP(NETIF_MSG_LINK, "Active external phy selected: %x\n", 6882 active_external_phy); 6883 } 6884 6885 for (phy_index = EXT_PHY1; phy_index < params->num_phys; 6886 phy_index++) { 6887 if (params->phy[phy_index].flags & 6888 FLAGS_REARM_LATCH_SIGNAL) { 6889 bnx2x_rearm_latch_signal(bp, port, 6890 phy_index == 6891 active_external_phy); 6892 break; 6893 } 6894 } 6895 DP(NETIF_MSG_LINK, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x," 6896 " ext_phy_line_speed = %d\n", vars->flow_ctrl, 6897 vars->link_status, ext_phy_line_speed); 6898 /* Upon link speed change set the NIG into drain mode. Comes to 6899 * deals with possible FIFO glitch due to clk change when speed 6900 * is decreased without link down indicator 6901 */ 6902 6903 if (vars->phy_link_up) { 6904 if (!(SINGLE_MEDIA_DIRECT(params)) && ext_phy_link_up && 6905 (ext_phy_line_speed != vars->line_speed)) { 6906 DP(NETIF_MSG_LINK, "Internal link speed %d is" 6907 " different than the external" 6908 " link speed %d\n", vars->line_speed, 6909 ext_phy_line_speed); 6910 vars->phy_link_up = 0; 6911 } else if (prev_line_speed != vars->line_speed) { 6912 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 6913 0); 6914 usleep_range(1000, 2000); 6915 } 6916 } 6917 6918 /* Anything 10 and over uses the bmac */ 6919 link_10g_plus = (vars->line_speed >= SPEED_10000); 6920 6921 bnx2x_link_int_ack(params, vars, link_10g_plus); 6922 6923 /* In case external phy link is up, and internal link is down 6924 * (not initialized yet probably after link initialization, it 6925 * needs to be initialized. 6926 * Note that after link down-up as result of cable plug, the xgxs 6927 * link would probably become up again without the need 6928 * initialize it 6929 */ 6930 if (!(SINGLE_MEDIA_DIRECT(params))) { 6931 DP(NETIF_MSG_LINK, "ext_phy_link_up = %d, int_link_up = %d," 6932 " init_preceding = %d\n", ext_phy_link_up, 6933 vars->phy_link_up, 6934 params->phy[EXT_PHY1].flags & 6935 FLAGS_INIT_XGXS_FIRST); 6936 if (!(params->phy[EXT_PHY1].flags & 6937 FLAGS_INIT_XGXS_FIRST) 6938 && ext_phy_link_up && !vars->phy_link_up) { 6939 vars->line_speed = ext_phy_line_speed; 6940 if (vars->line_speed < SPEED_1000) 6941 vars->phy_flags |= PHY_SGMII_FLAG; 6942 else 6943 vars->phy_flags &= ~PHY_SGMII_FLAG; 6944 6945 if (params->phy[INT_PHY].config_init) 6946 params->phy[INT_PHY].config_init( 6947 ¶ms->phy[INT_PHY], params, 6948 vars); 6949 } 6950 } 6951 /* Link is up only if both local phy and external phy (in case of 6952 * non-direct board) are up and no fault detected on active PHY. 6953 */ 6954 vars->link_up = (vars->phy_link_up && 6955 (ext_phy_link_up || 6956 SINGLE_MEDIA_DIRECT(params)) && 6957 (phy_vars[active_external_phy].fault_detected == 0)); 6958 6959 /* Update the PFC configuration in case it was changed */ 6960 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) 6961 vars->link_status |= LINK_STATUS_PFC_ENABLED; 6962 else 6963 vars->link_status &= ~LINK_STATUS_PFC_ENABLED; 6964 6965 if (vars->link_up) 6966 rc = bnx2x_update_link_up(params, vars, link_10g_plus); 6967 else 6968 rc = bnx2x_update_link_down(params, vars); 6969 6970 /* Update MCP link status was changed */ 6971 if (params->feature_config_flags & FEATURE_CONFIG_BC_SUPPORTS_AFEX) 6972 bnx2x_fw_command(bp, DRV_MSG_CODE_LINK_STATUS_CHANGED, 0); 6973 6974 return rc; 6975 } 6976 6977 /*****************************************************************************/ 6978 /* External Phy section */ 6979 /*****************************************************************************/ 6980 void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port) 6981 { 6982 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, 6983 MISC_REGISTERS_GPIO_OUTPUT_LOW, port); 6984 usleep_range(1000, 2000); 6985 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, 6986 MISC_REGISTERS_GPIO_OUTPUT_HIGH, port); 6987 } 6988 6989 static void bnx2x_save_spirom_version(struct bnx2x *bp, u8 port, 6990 u32 spirom_ver, u32 ver_addr) 6991 { 6992 DP(NETIF_MSG_LINK, "FW version 0x%x:0x%x for port %d\n", 6993 (u16)(spirom_ver>>16), (u16)spirom_ver, port); 6994 6995 if (ver_addr) 6996 REG_WR(bp, ver_addr, spirom_ver); 6997 } 6998 6999 static void bnx2x_save_bcm_spirom_ver(struct bnx2x *bp, 7000 struct bnx2x_phy *phy, 7001 u8 port) 7002 { 7003 u16 fw_ver1, fw_ver2; 7004 7005 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 7006 MDIO_PMA_REG_ROM_VER1, &fw_ver1); 7007 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 7008 MDIO_PMA_REG_ROM_VER2, &fw_ver2); 7009 bnx2x_save_spirom_version(bp, port, (u32)(fw_ver1<<16 | fw_ver2), 7010 phy->ver_addr); 7011 } 7012 7013 static void bnx2x_ext_phy_10G_an_resolve(struct bnx2x *bp, 7014 struct bnx2x_phy *phy, 7015 struct link_vars *vars) 7016 { 7017 u16 val; 7018 bnx2x_cl45_read(bp, phy, 7019 MDIO_AN_DEVAD, 7020 MDIO_AN_REG_STATUS, &val); 7021 bnx2x_cl45_read(bp, phy, 7022 MDIO_AN_DEVAD, 7023 MDIO_AN_REG_STATUS, &val); 7024 if (val & (1<<5)) 7025 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; 7026 if ((val & (1<<0)) == 0) 7027 vars->link_status |= LINK_STATUS_PARALLEL_DETECTION_USED; 7028 } 7029 7030 /******************************************************************/ 7031 /* common BCM8073/BCM8727 PHY SECTION */ 7032 /******************************************************************/ 7033 static void bnx2x_8073_resolve_fc(struct bnx2x_phy *phy, 7034 struct link_params *params, 7035 struct link_vars *vars) 7036 { 7037 struct bnx2x *bp = params->bp; 7038 if (phy->req_line_speed == SPEED_10 || 7039 phy->req_line_speed == SPEED_100) { 7040 vars->flow_ctrl = phy->req_flow_ctrl; 7041 return; 7042 } 7043 7044 if (bnx2x_ext_phy_resolve_fc(phy, params, vars) && 7045 (vars->flow_ctrl == BNX2X_FLOW_CTRL_NONE)) { 7046 u16 pause_result; 7047 u16 ld_pause; /* local */ 7048 u16 lp_pause; /* link partner */ 7049 bnx2x_cl45_read(bp, phy, 7050 MDIO_AN_DEVAD, 7051 MDIO_AN_REG_CL37_FC_LD, &ld_pause); 7052 7053 bnx2x_cl45_read(bp, phy, 7054 MDIO_AN_DEVAD, 7055 MDIO_AN_REG_CL37_FC_LP, &lp_pause); 7056 pause_result = (ld_pause & 7057 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 5; 7058 pause_result |= (lp_pause & 7059 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 7; 7060 7061 bnx2x_pause_resolve(vars, pause_result); 7062 DP(NETIF_MSG_LINK, "Ext PHY CL37 pause result 0x%x\n", 7063 pause_result); 7064 } 7065 } 7066 static int bnx2x_8073_8727_external_rom_boot(struct bnx2x *bp, 7067 struct bnx2x_phy *phy, 7068 u8 port) 7069 { 7070 u32 count = 0; 7071 u16 fw_ver1, fw_msgout; 7072 int rc = 0; 7073 7074 /* Boot port from external ROM */ 7075 /* EDC grst */ 7076 bnx2x_cl45_write(bp, phy, 7077 MDIO_PMA_DEVAD, 7078 MDIO_PMA_REG_GEN_CTRL, 7079 0x0001); 7080 7081 /* Ucode reboot and rst */ 7082 bnx2x_cl45_write(bp, phy, 7083 MDIO_PMA_DEVAD, 7084 MDIO_PMA_REG_GEN_CTRL, 7085 0x008c); 7086 7087 bnx2x_cl45_write(bp, phy, 7088 MDIO_PMA_DEVAD, 7089 MDIO_PMA_REG_MISC_CTRL1, 0x0001); 7090 7091 /* Reset internal microprocessor */ 7092 bnx2x_cl45_write(bp, phy, 7093 MDIO_PMA_DEVAD, 7094 MDIO_PMA_REG_GEN_CTRL, 7095 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET); 7096 7097 /* Release srst bit */ 7098 bnx2x_cl45_write(bp, phy, 7099 MDIO_PMA_DEVAD, 7100 MDIO_PMA_REG_GEN_CTRL, 7101 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP); 7102 7103 /* Delay 100ms per the PHY specifications */ 7104 msleep(100); 7105 7106 /* 8073 sometimes taking longer to download */ 7107 do { 7108 count++; 7109 if (count > 300) { 7110 DP(NETIF_MSG_LINK, 7111 "bnx2x_8073_8727_external_rom_boot port %x:" 7112 "Download failed. fw version = 0x%x\n", 7113 port, fw_ver1); 7114 rc = -EINVAL; 7115 break; 7116 } 7117 7118 bnx2x_cl45_read(bp, phy, 7119 MDIO_PMA_DEVAD, 7120 MDIO_PMA_REG_ROM_VER1, &fw_ver1); 7121 bnx2x_cl45_read(bp, phy, 7122 MDIO_PMA_DEVAD, 7123 MDIO_PMA_REG_M8051_MSGOUT_REG, &fw_msgout); 7124 7125 usleep_range(1000, 2000); 7126 } while (fw_ver1 == 0 || fw_ver1 == 0x4321 || 7127 ((fw_msgout & 0xff) != 0x03 && (phy->type == 7128 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073))); 7129 7130 /* Clear ser_boot_ctl bit */ 7131 bnx2x_cl45_write(bp, phy, 7132 MDIO_PMA_DEVAD, 7133 MDIO_PMA_REG_MISC_CTRL1, 0x0000); 7134 bnx2x_save_bcm_spirom_ver(bp, phy, port); 7135 7136 DP(NETIF_MSG_LINK, 7137 "bnx2x_8073_8727_external_rom_boot port %x:" 7138 "Download complete. fw version = 0x%x\n", 7139 port, fw_ver1); 7140 7141 return rc; 7142 } 7143 7144 /******************************************************************/ 7145 /* BCM8073 PHY SECTION */ 7146 /******************************************************************/ 7147 static int bnx2x_8073_is_snr_needed(struct bnx2x *bp, struct bnx2x_phy *phy) 7148 { 7149 /* This is only required for 8073A1, version 102 only */ 7150 u16 val; 7151 7152 /* Read 8073 HW revision*/ 7153 bnx2x_cl45_read(bp, phy, 7154 MDIO_PMA_DEVAD, 7155 MDIO_PMA_REG_8073_CHIP_REV, &val); 7156 7157 if (val != 1) { 7158 /* No need to workaround in 8073 A1 */ 7159 return 0; 7160 } 7161 7162 bnx2x_cl45_read(bp, phy, 7163 MDIO_PMA_DEVAD, 7164 MDIO_PMA_REG_ROM_VER2, &val); 7165 7166 /* SNR should be applied only for version 0x102 */ 7167 if (val != 0x102) 7168 return 0; 7169 7170 return 1; 7171 } 7172 7173 static int bnx2x_8073_xaui_wa(struct bnx2x *bp, struct bnx2x_phy *phy) 7174 { 7175 u16 val, cnt, cnt1 ; 7176 7177 bnx2x_cl45_read(bp, phy, 7178 MDIO_PMA_DEVAD, 7179 MDIO_PMA_REG_8073_CHIP_REV, &val); 7180 7181 if (val > 0) { 7182 /* No need to workaround in 8073 A1 */ 7183 return 0; 7184 } 7185 /* XAUI workaround in 8073 A0: */ 7186 7187 /* After loading the boot ROM and restarting Autoneg, poll 7188 * Dev1, Reg $C820: 7189 */ 7190 7191 for (cnt = 0; cnt < 1000; cnt++) { 7192 bnx2x_cl45_read(bp, phy, 7193 MDIO_PMA_DEVAD, 7194 MDIO_PMA_REG_8073_SPEED_LINK_STATUS, 7195 &val); 7196 /* If bit [14] = 0 or bit [13] = 0, continue on with 7197 * system initialization (XAUI work-around not required, as 7198 * these bits indicate 2.5G or 1G link up). 7199 */ 7200 if (!(val & (1<<14)) || !(val & (1<<13))) { 7201 DP(NETIF_MSG_LINK, "XAUI work-around not required\n"); 7202 return 0; 7203 } else if (!(val & (1<<15))) { 7204 DP(NETIF_MSG_LINK, "bit 15 went off\n"); 7205 /* If bit 15 is 0, then poll Dev1, Reg $C841 until it's 7206 * MSB (bit15) goes to 1 (indicating that the XAUI 7207 * workaround has completed), then continue on with 7208 * system initialization. 7209 */ 7210 for (cnt1 = 0; cnt1 < 1000; cnt1++) { 7211 bnx2x_cl45_read(bp, phy, 7212 MDIO_PMA_DEVAD, 7213 MDIO_PMA_REG_8073_XAUI_WA, &val); 7214 if (val & (1<<15)) { 7215 DP(NETIF_MSG_LINK, 7216 "XAUI workaround has completed\n"); 7217 return 0; 7218 } 7219 usleep_range(3000, 6000); 7220 } 7221 break; 7222 } 7223 usleep_range(3000, 6000); 7224 } 7225 DP(NETIF_MSG_LINK, "Warning: XAUI work-around timeout !!!\n"); 7226 return -EINVAL; 7227 } 7228 7229 static void bnx2x_807x_force_10G(struct bnx2x *bp, struct bnx2x_phy *phy) 7230 { 7231 /* Force KR or KX */ 7232 bnx2x_cl45_write(bp, phy, 7233 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040); 7234 bnx2x_cl45_write(bp, phy, 7235 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0x000b); 7236 bnx2x_cl45_write(bp, phy, 7237 MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0000); 7238 bnx2x_cl45_write(bp, phy, 7239 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000); 7240 } 7241 7242 static void bnx2x_8073_set_pause_cl37(struct link_params *params, 7243 struct bnx2x_phy *phy, 7244 struct link_vars *vars) 7245 { 7246 u16 cl37_val; 7247 struct bnx2x *bp = params->bp; 7248 bnx2x_cl45_read(bp, phy, 7249 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &cl37_val); 7250 7251 cl37_val &= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; 7252 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */ 7253 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); 7254 if ((vars->ieee_fc & 7255 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) == 7256 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) { 7257 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC; 7258 } 7259 if ((vars->ieee_fc & 7260 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) == 7261 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) { 7262 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC; 7263 } 7264 if ((vars->ieee_fc & 7265 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) == 7266 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) { 7267 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; 7268 } 7269 DP(NETIF_MSG_LINK, 7270 "Ext phy AN advertize cl37 0x%x\n", cl37_val); 7271 7272 bnx2x_cl45_write(bp, phy, 7273 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, cl37_val); 7274 msleep(500); 7275 } 7276 7277 static void bnx2x_8073_specific_func(struct bnx2x_phy *phy, 7278 struct link_params *params, 7279 u32 action) 7280 { 7281 struct bnx2x *bp = params->bp; 7282 switch (action) { 7283 case PHY_INIT: 7284 /* Enable LASI */ 7285 bnx2x_cl45_write(bp, phy, 7286 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, (1<<2)); 7287 bnx2x_cl45_write(bp, phy, 7288 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0004); 7289 break; 7290 } 7291 } 7292 7293 static int bnx2x_8073_config_init(struct bnx2x_phy *phy, 7294 struct link_params *params, 7295 struct link_vars *vars) 7296 { 7297 struct bnx2x *bp = params->bp; 7298 u16 val = 0, tmp1; 7299 u8 gpio_port; 7300 DP(NETIF_MSG_LINK, "Init 8073\n"); 7301 7302 if (CHIP_IS_E2(bp)) 7303 gpio_port = BP_PATH(bp); 7304 else 7305 gpio_port = params->port; 7306 /* Restore normal power mode*/ 7307 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 7308 MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port); 7309 7310 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, 7311 MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port); 7312 7313 bnx2x_8073_specific_func(phy, params, PHY_INIT); 7314 bnx2x_8073_set_pause_cl37(params, phy, vars); 7315 7316 bnx2x_cl45_read(bp, phy, 7317 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1); 7318 7319 bnx2x_cl45_read(bp, phy, 7320 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1); 7321 7322 DP(NETIF_MSG_LINK, "Before rom RX_ALARM(port1): 0x%x\n", tmp1); 7323 7324 /* Swap polarity if required - Must be done only in non-1G mode */ 7325 if (params->lane_config & PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) { 7326 /* Configure the 8073 to swap _P and _N of the KR lines */ 7327 DP(NETIF_MSG_LINK, "Swapping polarity for the 8073\n"); 7328 /* 10G Rx/Tx and 1G Tx signal polarity swap */ 7329 bnx2x_cl45_read(bp, phy, 7330 MDIO_PMA_DEVAD, 7331 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL, &val); 7332 bnx2x_cl45_write(bp, phy, 7333 MDIO_PMA_DEVAD, 7334 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL, 7335 (val | (3<<9))); 7336 } 7337 7338 7339 /* Enable CL37 BAM */ 7340 if (REG_RD(bp, params->shmem_base + 7341 offsetof(struct shmem_region, dev_info. 7342 port_hw_config[params->port].default_cfg)) & 7343 PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) { 7344 7345 bnx2x_cl45_read(bp, phy, 7346 MDIO_AN_DEVAD, 7347 MDIO_AN_REG_8073_BAM, &val); 7348 bnx2x_cl45_write(bp, phy, 7349 MDIO_AN_DEVAD, 7350 MDIO_AN_REG_8073_BAM, val | 1); 7351 DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n"); 7352 } 7353 if (params->loopback_mode == LOOPBACK_EXT) { 7354 bnx2x_807x_force_10G(bp, phy); 7355 DP(NETIF_MSG_LINK, "Forced speed 10G on 807X\n"); 7356 return 0; 7357 } else { 7358 bnx2x_cl45_write(bp, phy, 7359 MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0002); 7360 } 7361 if (phy->req_line_speed != SPEED_AUTO_NEG) { 7362 if (phy->req_line_speed == SPEED_10000) { 7363 val = (1<<7); 7364 } else if (phy->req_line_speed == SPEED_2500) { 7365 val = (1<<5); 7366 /* Note that 2.5G works only when used with 1G 7367 * advertisement 7368 */ 7369 } else 7370 val = (1<<5); 7371 } else { 7372 val = 0; 7373 if (phy->speed_cap_mask & 7374 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) 7375 val |= (1<<7); 7376 7377 /* Note that 2.5G works only when used with 1G advertisement */ 7378 if (phy->speed_cap_mask & 7379 (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G | 7380 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) 7381 val |= (1<<5); 7382 DP(NETIF_MSG_LINK, "807x autoneg val = 0x%x\n", val); 7383 } 7384 7385 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val); 7386 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, &tmp1); 7387 7388 if (((phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) && 7389 (phy->req_line_speed == SPEED_AUTO_NEG)) || 7390 (phy->req_line_speed == SPEED_2500)) { 7391 u16 phy_ver; 7392 /* Allow 2.5G for A1 and above */ 7393 bnx2x_cl45_read(bp, phy, 7394 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV, 7395 &phy_ver); 7396 DP(NETIF_MSG_LINK, "Add 2.5G\n"); 7397 if (phy_ver > 0) 7398 tmp1 |= 1; 7399 else 7400 tmp1 &= 0xfffe; 7401 } else { 7402 DP(NETIF_MSG_LINK, "Disable 2.5G\n"); 7403 tmp1 &= 0xfffe; 7404 } 7405 7406 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, tmp1); 7407 /* Add support for CL37 (passive mode) II */ 7408 7409 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &tmp1); 7410 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, 7411 (tmp1 | ((phy->req_duplex == DUPLEX_FULL) ? 7412 0x20 : 0x40))); 7413 7414 /* Add support for CL37 (passive mode) III */ 7415 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000); 7416 7417 /* The SNR will improve about 2db by changing BW and FEE main 7418 * tap. Rest commands are executed after link is up 7419 * Change FFE main cursor to 5 in EDC register 7420 */ 7421 if (bnx2x_8073_is_snr_needed(bp, phy)) 7422 bnx2x_cl45_write(bp, phy, 7423 MDIO_PMA_DEVAD, MDIO_PMA_REG_EDC_FFE_MAIN, 7424 0xFB0C); 7425 7426 /* Enable FEC (Forware Error Correction) Request in the AN */ 7427 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, &tmp1); 7428 tmp1 |= (1<<15); 7429 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, tmp1); 7430 7431 bnx2x_ext_phy_set_pause(params, phy, vars); 7432 7433 /* Restart autoneg */ 7434 msleep(500); 7435 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200); 7436 DP(NETIF_MSG_LINK, "807x Autoneg Restart: Advertise 1G=%x, 10G=%x\n", 7437 ((val & (1<<5)) > 0), ((val & (1<<7)) > 0)); 7438 return 0; 7439 } 7440 7441 static u8 bnx2x_8073_read_status(struct bnx2x_phy *phy, 7442 struct link_params *params, 7443 struct link_vars *vars) 7444 { 7445 struct bnx2x *bp = params->bp; 7446 u8 link_up = 0; 7447 u16 val1, val2; 7448 u16 link_status = 0; 7449 u16 an1000_status = 0; 7450 7451 bnx2x_cl45_read(bp, phy, 7452 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1); 7453 7454 DP(NETIF_MSG_LINK, "8703 LASI status 0x%x\n", val1); 7455 7456 /* Clear the interrupt LASI status register */ 7457 bnx2x_cl45_read(bp, phy, 7458 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2); 7459 bnx2x_cl45_read(bp, phy, 7460 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val1); 7461 DP(NETIF_MSG_LINK, "807x PCS status 0x%x->0x%x\n", val2, val1); 7462 /* Clear MSG-OUT */ 7463 bnx2x_cl45_read(bp, phy, 7464 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1); 7465 7466 /* Check the LASI */ 7467 bnx2x_cl45_read(bp, phy, 7468 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2); 7469 7470 DP(NETIF_MSG_LINK, "KR 0x9003 0x%x\n", val2); 7471 7472 /* Check the link status */ 7473 bnx2x_cl45_read(bp, phy, 7474 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2); 7475 DP(NETIF_MSG_LINK, "KR PCS status 0x%x\n", val2); 7476 7477 bnx2x_cl45_read(bp, phy, 7478 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2); 7479 bnx2x_cl45_read(bp, phy, 7480 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1); 7481 link_up = ((val1 & 4) == 4); 7482 DP(NETIF_MSG_LINK, "PMA_REG_STATUS=0x%x\n", val1); 7483 7484 if (link_up && 7485 ((phy->req_line_speed != SPEED_10000))) { 7486 if (bnx2x_8073_xaui_wa(bp, phy) != 0) 7487 return 0; 7488 } 7489 bnx2x_cl45_read(bp, phy, 7490 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status); 7491 bnx2x_cl45_read(bp, phy, 7492 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status); 7493 7494 /* Check the link status on 1.1.2 */ 7495 bnx2x_cl45_read(bp, phy, 7496 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2); 7497 bnx2x_cl45_read(bp, phy, 7498 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1); 7499 DP(NETIF_MSG_LINK, "KR PMA status 0x%x->0x%x," 7500 "an_link_status=0x%x\n", val2, val1, an1000_status); 7501 7502 link_up = (((val1 & 4) == 4) || (an1000_status & (1<<1))); 7503 if (link_up && bnx2x_8073_is_snr_needed(bp, phy)) { 7504 /* The SNR will improve about 2dbby changing the BW and FEE main 7505 * tap. The 1st write to change FFE main tap is set before 7506 * restart AN. Change PLL Bandwidth in EDC register 7507 */ 7508 bnx2x_cl45_write(bp, phy, 7509 MDIO_PMA_DEVAD, MDIO_PMA_REG_PLL_BANDWIDTH, 7510 0x26BC); 7511 7512 /* Change CDR Bandwidth in EDC register */ 7513 bnx2x_cl45_write(bp, phy, 7514 MDIO_PMA_DEVAD, MDIO_PMA_REG_CDR_BANDWIDTH, 7515 0x0333); 7516 } 7517 bnx2x_cl45_read(bp, phy, 7518 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_SPEED_LINK_STATUS, 7519 &link_status); 7520 7521 /* Bits 0..2 --> speed detected, bits 13..15--> link is down */ 7522 if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) { 7523 link_up = 1; 7524 vars->line_speed = SPEED_10000; 7525 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n", 7526 params->port); 7527 } else if ((link_status & (1<<1)) && (!(link_status & (1<<14)))) { 7528 link_up = 1; 7529 vars->line_speed = SPEED_2500; 7530 DP(NETIF_MSG_LINK, "port %x: External link up in 2.5G\n", 7531 params->port); 7532 } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) { 7533 link_up = 1; 7534 vars->line_speed = SPEED_1000; 7535 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n", 7536 params->port); 7537 } else { 7538 link_up = 0; 7539 DP(NETIF_MSG_LINK, "port %x: External link is down\n", 7540 params->port); 7541 } 7542 7543 if (link_up) { 7544 /* Swap polarity if required */ 7545 if (params->lane_config & 7546 PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) { 7547 /* Configure the 8073 to swap P and N of the KR lines */ 7548 bnx2x_cl45_read(bp, phy, 7549 MDIO_XS_DEVAD, 7550 MDIO_XS_REG_8073_RX_CTRL_PCIE, &val1); 7551 /* Set bit 3 to invert Rx in 1G mode and clear this bit 7552 * when it`s in 10G mode. 7553 */ 7554 if (vars->line_speed == SPEED_1000) { 7555 DP(NETIF_MSG_LINK, "Swapping 1G polarity for" 7556 "the 8073\n"); 7557 val1 |= (1<<3); 7558 } else 7559 val1 &= ~(1<<3); 7560 7561 bnx2x_cl45_write(bp, phy, 7562 MDIO_XS_DEVAD, 7563 MDIO_XS_REG_8073_RX_CTRL_PCIE, 7564 val1); 7565 } 7566 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars); 7567 bnx2x_8073_resolve_fc(phy, params, vars); 7568 vars->duplex = DUPLEX_FULL; 7569 } 7570 7571 if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) { 7572 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, 7573 MDIO_AN_REG_LP_AUTO_NEG2, &val1); 7574 7575 if (val1 & (1<<5)) 7576 vars->link_status |= 7577 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; 7578 if (val1 & (1<<7)) 7579 vars->link_status |= 7580 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; 7581 } 7582 7583 return link_up; 7584 } 7585 7586 static void bnx2x_8073_link_reset(struct bnx2x_phy *phy, 7587 struct link_params *params) 7588 { 7589 struct bnx2x *bp = params->bp; 7590 u8 gpio_port; 7591 if (CHIP_IS_E2(bp)) 7592 gpio_port = BP_PATH(bp); 7593 else 7594 gpio_port = params->port; 7595 DP(NETIF_MSG_LINK, "Setting 8073 port %d into low power mode\n", 7596 gpio_port); 7597 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 7598 MISC_REGISTERS_GPIO_OUTPUT_LOW, 7599 gpio_port); 7600 } 7601 7602 /******************************************************************/ 7603 /* BCM8705 PHY SECTION */ 7604 /******************************************************************/ 7605 static int bnx2x_8705_config_init(struct bnx2x_phy *phy, 7606 struct link_params *params, 7607 struct link_vars *vars) 7608 { 7609 struct bnx2x *bp = params->bp; 7610 DP(NETIF_MSG_LINK, "init 8705\n"); 7611 /* Restore normal power mode*/ 7612 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 7613 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); 7614 /* HW reset */ 7615 bnx2x_ext_phy_hw_reset(bp, params->port); 7616 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040); 7617 bnx2x_wait_reset_complete(bp, phy, params); 7618 7619 bnx2x_cl45_write(bp, phy, 7620 MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL, 0x8288); 7621 bnx2x_cl45_write(bp, phy, 7622 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 0x7fbf); 7623 bnx2x_cl45_write(bp, phy, 7624 MDIO_PMA_DEVAD, MDIO_PMA_REG_CMU_PLL_BYPASS, 0x0100); 7625 bnx2x_cl45_write(bp, phy, 7626 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_CNTL, 0x1); 7627 /* BCM8705 doesn't have microcode, hence the 0 */ 7628 bnx2x_save_spirom_version(bp, params->port, params->shmem_base, 0); 7629 return 0; 7630 } 7631 7632 static u8 bnx2x_8705_read_status(struct bnx2x_phy *phy, 7633 struct link_params *params, 7634 struct link_vars *vars) 7635 { 7636 u8 link_up = 0; 7637 u16 val1, rx_sd; 7638 struct bnx2x *bp = params->bp; 7639 DP(NETIF_MSG_LINK, "read status 8705\n"); 7640 bnx2x_cl45_read(bp, phy, 7641 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1); 7642 DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1); 7643 7644 bnx2x_cl45_read(bp, phy, 7645 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1); 7646 DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1); 7647 7648 bnx2x_cl45_read(bp, phy, 7649 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd); 7650 7651 bnx2x_cl45_read(bp, phy, 7652 MDIO_PMA_DEVAD, 0xc809, &val1); 7653 bnx2x_cl45_read(bp, phy, 7654 MDIO_PMA_DEVAD, 0xc809, &val1); 7655 7656 DP(NETIF_MSG_LINK, "8705 1.c809 val=0x%x\n", val1); 7657 link_up = ((rx_sd & 0x1) && (val1 & (1<<9)) && ((val1 & (1<<8)) == 0)); 7658 if (link_up) { 7659 vars->line_speed = SPEED_10000; 7660 bnx2x_ext_phy_resolve_fc(phy, params, vars); 7661 } 7662 return link_up; 7663 } 7664 7665 /******************************************************************/ 7666 /* SFP+ module Section */ 7667 /******************************************************************/ 7668 static void bnx2x_set_disable_pmd_transmit(struct link_params *params, 7669 struct bnx2x_phy *phy, 7670 u8 pmd_dis) 7671 { 7672 struct bnx2x *bp = params->bp; 7673 /* Disable transmitter only for bootcodes which can enable it afterwards 7674 * (for D3 link) 7675 */ 7676 if (pmd_dis) { 7677 if (params->feature_config_flags & 7678 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED) 7679 DP(NETIF_MSG_LINK, "Disabling PMD transmitter\n"); 7680 else { 7681 DP(NETIF_MSG_LINK, "NOT disabling PMD transmitter\n"); 7682 return; 7683 } 7684 } else 7685 DP(NETIF_MSG_LINK, "Enabling PMD transmitter\n"); 7686 bnx2x_cl45_write(bp, phy, 7687 MDIO_PMA_DEVAD, 7688 MDIO_PMA_REG_TX_DISABLE, pmd_dis); 7689 } 7690 7691 static u8 bnx2x_get_gpio_port(struct link_params *params) 7692 { 7693 u8 gpio_port; 7694 u32 swap_val, swap_override; 7695 struct bnx2x *bp = params->bp; 7696 if (CHIP_IS_E2(bp)) 7697 gpio_port = BP_PATH(bp); 7698 else 7699 gpio_port = params->port; 7700 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); 7701 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); 7702 return gpio_port ^ (swap_val && swap_override); 7703 } 7704 7705 static void bnx2x_sfp_e1e2_set_transmitter(struct link_params *params, 7706 struct bnx2x_phy *phy, 7707 u8 tx_en) 7708 { 7709 u16 val; 7710 u8 port = params->port; 7711 struct bnx2x *bp = params->bp; 7712 u32 tx_en_mode; 7713 7714 /* Disable/Enable transmitter ( TX laser of the SFP+ module.)*/ 7715 tx_en_mode = REG_RD(bp, params->shmem_base + 7716 offsetof(struct shmem_region, 7717 dev_info.port_hw_config[port].sfp_ctrl)) & 7718 PORT_HW_CFG_TX_LASER_MASK; 7719 DP(NETIF_MSG_LINK, "Setting transmitter tx_en=%x for port %x " 7720 "mode = %x\n", tx_en, port, tx_en_mode); 7721 switch (tx_en_mode) { 7722 case PORT_HW_CFG_TX_LASER_MDIO: 7723 7724 bnx2x_cl45_read(bp, phy, 7725 MDIO_PMA_DEVAD, 7726 MDIO_PMA_REG_PHY_IDENTIFIER, 7727 &val); 7728 7729 if (tx_en) 7730 val &= ~(1<<15); 7731 else 7732 val |= (1<<15); 7733 7734 bnx2x_cl45_write(bp, phy, 7735 MDIO_PMA_DEVAD, 7736 MDIO_PMA_REG_PHY_IDENTIFIER, 7737 val); 7738 break; 7739 case PORT_HW_CFG_TX_LASER_GPIO0: 7740 case PORT_HW_CFG_TX_LASER_GPIO1: 7741 case PORT_HW_CFG_TX_LASER_GPIO2: 7742 case PORT_HW_CFG_TX_LASER_GPIO3: 7743 { 7744 u16 gpio_pin; 7745 u8 gpio_port, gpio_mode; 7746 if (tx_en) 7747 gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_HIGH; 7748 else 7749 gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_LOW; 7750 7751 gpio_pin = tx_en_mode - PORT_HW_CFG_TX_LASER_GPIO0; 7752 gpio_port = bnx2x_get_gpio_port(params); 7753 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port); 7754 break; 7755 } 7756 default: 7757 DP(NETIF_MSG_LINK, "Invalid TX_LASER_MDIO 0x%x\n", tx_en_mode); 7758 break; 7759 } 7760 } 7761 7762 static void bnx2x_sfp_set_transmitter(struct link_params *params, 7763 struct bnx2x_phy *phy, 7764 u8 tx_en) 7765 { 7766 struct bnx2x *bp = params->bp; 7767 DP(NETIF_MSG_LINK, "Setting SFP+ transmitter to %d\n", tx_en); 7768 if (CHIP_IS_E3(bp)) 7769 bnx2x_sfp_e3_set_transmitter(params, phy, tx_en); 7770 else 7771 bnx2x_sfp_e1e2_set_transmitter(params, phy, tx_en); 7772 } 7773 7774 static int bnx2x_8726_read_sfp_module_eeprom(struct bnx2x_phy *phy, 7775 struct link_params *params, 7776 u8 dev_addr, u16 addr, u8 byte_cnt, 7777 u8 *o_buf, u8 is_init) 7778 { 7779 struct bnx2x *bp = params->bp; 7780 u16 val = 0; 7781 u16 i; 7782 if (byte_cnt > SFP_EEPROM_PAGE_SIZE) { 7783 DP(NETIF_MSG_LINK, 7784 "Reading from eeprom is limited to 0xf\n"); 7785 return -EINVAL; 7786 } 7787 /* Set the read command byte count */ 7788 bnx2x_cl45_write(bp, phy, 7789 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT, 7790 (byte_cnt | (dev_addr << 8))); 7791 7792 /* Set the read command address */ 7793 bnx2x_cl45_write(bp, phy, 7794 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR, 7795 addr); 7796 7797 /* Activate read command */ 7798 bnx2x_cl45_write(bp, phy, 7799 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, 7800 0x2c0f); 7801 7802 /* Wait up to 500us for command complete status */ 7803 for (i = 0; i < 100; i++) { 7804 bnx2x_cl45_read(bp, phy, 7805 MDIO_PMA_DEVAD, 7806 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); 7807 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == 7808 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) 7809 break; 7810 udelay(5); 7811 } 7812 7813 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) != 7814 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) { 7815 DP(NETIF_MSG_LINK, 7816 "Got bad status 0x%x when reading from SFP+ EEPROM\n", 7817 (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK)); 7818 return -EINVAL; 7819 } 7820 7821 /* Read the buffer */ 7822 for (i = 0; i < byte_cnt; i++) { 7823 bnx2x_cl45_read(bp, phy, 7824 MDIO_PMA_DEVAD, 7825 MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i, &val); 7826 o_buf[i] = (u8)(val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK); 7827 } 7828 7829 for (i = 0; i < 100; i++) { 7830 bnx2x_cl45_read(bp, phy, 7831 MDIO_PMA_DEVAD, 7832 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); 7833 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == 7834 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE) 7835 return 0; 7836 usleep_range(1000, 2000); 7837 } 7838 return -EINVAL; 7839 } 7840 7841 static void bnx2x_warpcore_power_module(struct link_params *params, 7842 u8 power) 7843 { 7844 u32 pin_cfg; 7845 struct bnx2x *bp = params->bp; 7846 7847 pin_cfg = (REG_RD(bp, params->shmem_base + 7848 offsetof(struct shmem_region, 7849 dev_info.port_hw_config[params->port].e3_sfp_ctrl)) & 7850 PORT_HW_CFG_E3_PWR_DIS_MASK) >> 7851 PORT_HW_CFG_E3_PWR_DIS_SHIFT; 7852 7853 if (pin_cfg == PIN_CFG_NA) 7854 return; 7855 DP(NETIF_MSG_LINK, "Setting SFP+ module power to %d using pin cfg %d\n", 7856 power, pin_cfg); 7857 /* Low ==> corresponding SFP+ module is powered 7858 * high ==> the SFP+ module is powered down 7859 */ 7860 bnx2x_set_cfg_pin(bp, pin_cfg, power ^ 1); 7861 } 7862 static int bnx2x_warpcore_read_sfp_module_eeprom(struct bnx2x_phy *phy, 7863 struct link_params *params, 7864 u8 dev_addr, 7865 u16 addr, u8 byte_cnt, 7866 u8 *o_buf, u8 is_init) 7867 { 7868 int rc = 0; 7869 u8 i, j = 0, cnt = 0; 7870 u32 data_array[4]; 7871 u16 addr32; 7872 struct bnx2x *bp = params->bp; 7873 7874 if (byte_cnt > SFP_EEPROM_PAGE_SIZE) { 7875 DP(NETIF_MSG_LINK, 7876 "Reading from eeprom is limited to 16 bytes\n"); 7877 return -EINVAL; 7878 } 7879 7880 /* 4 byte aligned address */ 7881 addr32 = addr & (~0x3); 7882 do { 7883 if ((!is_init) && (cnt == I2C_WA_PWR_ITER)) { 7884 bnx2x_warpcore_power_module(params, 0); 7885 /* Note that 100us are not enough here */ 7886 usleep_range(1000, 2000); 7887 bnx2x_warpcore_power_module(params, 1); 7888 } 7889 rc = bnx2x_bsc_read(params, phy, dev_addr, addr32, 0, byte_cnt, 7890 data_array); 7891 } while ((rc != 0) && (++cnt < I2C_WA_RETRY_CNT)); 7892 7893 if (rc == 0) { 7894 for (i = (addr - addr32); i < byte_cnt + (addr - addr32); i++) { 7895 o_buf[j] = *((u8 *)data_array + i); 7896 j++; 7897 } 7898 } 7899 7900 return rc; 7901 } 7902 7903 static int bnx2x_8727_read_sfp_module_eeprom(struct bnx2x_phy *phy, 7904 struct link_params *params, 7905 u8 dev_addr, u16 addr, u8 byte_cnt, 7906 u8 *o_buf, u8 is_init) 7907 { 7908 struct bnx2x *bp = params->bp; 7909 u16 val, i; 7910 7911 if (byte_cnt > SFP_EEPROM_PAGE_SIZE) { 7912 DP(NETIF_MSG_LINK, 7913 "Reading from eeprom is limited to 0xf\n"); 7914 return -EINVAL; 7915 } 7916 7917 /* Set 2-wire transfer rate of SFP+ module EEPROM 7918 * to 100Khz since some DACs(direct attached cables) do 7919 * not work at 400Khz. 7920 */ 7921 bnx2x_cl45_write(bp, phy, 7922 MDIO_PMA_DEVAD, 7923 MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR, 7924 ((dev_addr << 8) | 1)); 7925 7926 /* Need to read from 1.8000 to clear it */ 7927 bnx2x_cl45_read(bp, phy, 7928 MDIO_PMA_DEVAD, 7929 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, 7930 &val); 7931 7932 /* Set the read command byte count */ 7933 bnx2x_cl45_write(bp, phy, 7934 MDIO_PMA_DEVAD, 7935 MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT, 7936 ((byte_cnt < 2) ? 2 : byte_cnt)); 7937 7938 /* Set the read command address */ 7939 bnx2x_cl45_write(bp, phy, 7940 MDIO_PMA_DEVAD, 7941 MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR, 7942 addr); 7943 /* Set the destination address */ 7944 bnx2x_cl45_write(bp, phy, 7945 MDIO_PMA_DEVAD, 7946 0x8004, 7947 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF); 7948 7949 /* Activate read command */ 7950 bnx2x_cl45_write(bp, phy, 7951 MDIO_PMA_DEVAD, 7952 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, 7953 0x8002); 7954 /* Wait appropriate time for two-wire command to finish before 7955 * polling the status register 7956 */ 7957 usleep_range(1000, 2000); 7958 7959 /* Wait up to 500us for command complete status */ 7960 for (i = 0; i < 100; i++) { 7961 bnx2x_cl45_read(bp, phy, 7962 MDIO_PMA_DEVAD, 7963 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); 7964 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == 7965 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) 7966 break; 7967 udelay(5); 7968 } 7969 7970 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) != 7971 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) { 7972 DP(NETIF_MSG_LINK, 7973 "Got bad status 0x%x when reading from SFP+ EEPROM\n", 7974 (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK)); 7975 return -EFAULT; 7976 } 7977 7978 /* Read the buffer */ 7979 for (i = 0; i < byte_cnt; i++) { 7980 bnx2x_cl45_read(bp, phy, 7981 MDIO_PMA_DEVAD, 7982 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF + i, &val); 7983 o_buf[i] = (u8)(val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK); 7984 } 7985 7986 for (i = 0; i < 100; i++) { 7987 bnx2x_cl45_read(bp, phy, 7988 MDIO_PMA_DEVAD, 7989 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); 7990 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == 7991 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE) 7992 return 0; 7993 usleep_range(1000, 2000); 7994 } 7995 7996 return -EINVAL; 7997 } 7998 int bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy, 7999 struct link_params *params, u8 dev_addr, 8000 u16 addr, u16 byte_cnt, u8 *o_buf) 8001 { 8002 int rc = 0; 8003 struct bnx2x *bp = params->bp; 8004 u8 xfer_size; 8005 u8 *user_data = o_buf; 8006 read_sfp_module_eeprom_func_p read_func; 8007 8008 if ((dev_addr != 0xa0) && (dev_addr != 0xa2)) { 8009 DP(NETIF_MSG_LINK, "invalid dev_addr 0x%x\n", dev_addr); 8010 return -EINVAL; 8011 } 8012 8013 switch (phy->type) { 8014 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: 8015 read_func = bnx2x_8726_read_sfp_module_eeprom; 8016 break; 8017 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: 8018 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722: 8019 read_func = bnx2x_8727_read_sfp_module_eeprom; 8020 break; 8021 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT: 8022 read_func = bnx2x_warpcore_read_sfp_module_eeprom; 8023 break; 8024 default: 8025 return -EOPNOTSUPP; 8026 } 8027 8028 while (!rc && (byte_cnt > 0)) { 8029 xfer_size = (byte_cnt > SFP_EEPROM_PAGE_SIZE) ? 8030 SFP_EEPROM_PAGE_SIZE : byte_cnt; 8031 rc = read_func(phy, params, dev_addr, addr, xfer_size, 8032 user_data, 0); 8033 byte_cnt -= xfer_size; 8034 user_data += xfer_size; 8035 addr += xfer_size; 8036 } 8037 return rc; 8038 } 8039 8040 static int bnx2x_get_edc_mode(struct bnx2x_phy *phy, 8041 struct link_params *params, 8042 u16 *edc_mode) 8043 { 8044 struct bnx2x *bp = params->bp; 8045 u32 sync_offset = 0, phy_idx, media_types; 8046 u8 gport, val[2], check_limiting_mode = 0; 8047 *edc_mode = EDC_MODE_LIMITING; 8048 phy->media_type = ETH_PHY_UNSPECIFIED; 8049 /* First check for copper cable */ 8050 if (bnx2x_read_sfp_module_eeprom(phy, 8051 params, 8052 I2C_DEV_ADDR_A0, 8053 SFP_EEPROM_CON_TYPE_ADDR, 8054 2, 8055 (u8 *)val) != 0) { 8056 DP(NETIF_MSG_LINK, "Failed to read from SFP+ module EEPROM\n"); 8057 return -EINVAL; 8058 } 8059 8060 switch (val[0]) { 8061 case SFP_EEPROM_CON_TYPE_VAL_COPPER: 8062 { 8063 u8 copper_module_type; 8064 phy->media_type = ETH_PHY_DA_TWINAX; 8065 /* Check if its active cable (includes SFP+ module) 8066 * of passive cable 8067 */ 8068 if (bnx2x_read_sfp_module_eeprom(phy, 8069 params, 8070 I2C_DEV_ADDR_A0, 8071 SFP_EEPROM_FC_TX_TECH_ADDR, 8072 1, 8073 &copper_module_type) != 0) { 8074 DP(NETIF_MSG_LINK, 8075 "Failed to read copper-cable-type" 8076 " from SFP+ EEPROM\n"); 8077 return -EINVAL; 8078 } 8079 8080 if (copper_module_type & 8081 SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) { 8082 DP(NETIF_MSG_LINK, "Active Copper cable detected\n"); 8083 check_limiting_mode = 1; 8084 } else if (copper_module_type & 8085 SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE) { 8086 DP(NETIF_MSG_LINK, 8087 "Passive Copper cable detected\n"); 8088 *edc_mode = 8089 EDC_MODE_PASSIVE_DAC; 8090 } else { 8091 DP(NETIF_MSG_LINK, 8092 "Unknown copper-cable-type 0x%x !!!\n", 8093 copper_module_type); 8094 return -EINVAL; 8095 } 8096 break; 8097 } 8098 case SFP_EEPROM_CON_TYPE_VAL_LC: 8099 case SFP_EEPROM_CON_TYPE_VAL_RJ45: 8100 check_limiting_mode = 1; 8101 if ((val[1] & (SFP_EEPROM_COMP_CODE_SR_MASK | 8102 SFP_EEPROM_COMP_CODE_LR_MASK | 8103 SFP_EEPROM_COMP_CODE_LRM_MASK)) == 0) { 8104 DP(NETIF_MSG_LINK, "1G SFP module detected\n"); 8105 gport = params->port; 8106 phy->media_type = ETH_PHY_SFP_1G_FIBER; 8107 if (phy->req_line_speed != SPEED_1000) { 8108 phy->req_line_speed = SPEED_1000; 8109 if (!CHIP_IS_E1x(bp)) { 8110 gport = BP_PATH(bp) + 8111 (params->port << 1); 8112 } 8113 netdev_err(bp->dev, 8114 "Warning: Link speed was forced to 1000Mbps. Current SFP module in port %d is not compliant with 10G Ethernet\n", 8115 gport); 8116 } 8117 } else { 8118 int idx, cfg_idx = 0; 8119 DP(NETIF_MSG_LINK, "10G Optic module detected\n"); 8120 for (idx = INT_PHY; idx < MAX_PHYS; idx++) { 8121 if (params->phy[idx].type == phy->type) { 8122 cfg_idx = LINK_CONFIG_IDX(idx); 8123 break; 8124 } 8125 } 8126 phy->media_type = ETH_PHY_SFPP_10G_FIBER; 8127 phy->req_line_speed = params->req_line_speed[cfg_idx]; 8128 } 8129 break; 8130 default: 8131 DP(NETIF_MSG_LINK, "Unable to determine module type 0x%x !!!\n", 8132 val[0]); 8133 return -EINVAL; 8134 } 8135 sync_offset = params->shmem_base + 8136 offsetof(struct shmem_region, 8137 dev_info.port_hw_config[params->port].media_type); 8138 media_types = REG_RD(bp, sync_offset); 8139 /* Update media type for non-PMF sync */ 8140 for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) { 8141 if (&(params->phy[phy_idx]) == phy) { 8142 media_types &= ~(PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK << 8143 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx)); 8144 media_types |= ((phy->media_type & 8145 PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) << 8146 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx)); 8147 break; 8148 } 8149 } 8150 REG_WR(bp, sync_offset, media_types); 8151 if (check_limiting_mode) { 8152 u8 options[SFP_EEPROM_OPTIONS_SIZE]; 8153 if (bnx2x_read_sfp_module_eeprom(phy, 8154 params, 8155 I2C_DEV_ADDR_A0, 8156 SFP_EEPROM_OPTIONS_ADDR, 8157 SFP_EEPROM_OPTIONS_SIZE, 8158 options) != 0) { 8159 DP(NETIF_MSG_LINK, 8160 "Failed to read Option field from module EEPROM\n"); 8161 return -EINVAL; 8162 } 8163 if ((options[0] & SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK)) 8164 *edc_mode = EDC_MODE_LINEAR; 8165 else 8166 *edc_mode = EDC_MODE_LIMITING; 8167 } 8168 DP(NETIF_MSG_LINK, "EDC mode is set to 0x%x\n", *edc_mode); 8169 return 0; 8170 } 8171 /* This function read the relevant field from the module (SFP+), and verify it 8172 * is compliant with this board 8173 */ 8174 static int bnx2x_verify_sfp_module(struct bnx2x_phy *phy, 8175 struct link_params *params) 8176 { 8177 struct bnx2x *bp = params->bp; 8178 u32 val, cmd; 8179 u32 fw_resp, fw_cmd_param; 8180 char vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE+1]; 8181 char vendor_pn[SFP_EEPROM_PART_NO_SIZE+1]; 8182 phy->flags &= ~FLAGS_SFP_NOT_APPROVED; 8183 val = REG_RD(bp, params->shmem_base + 8184 offsetof(struct shmem_region, dev_info. 8185 port_feature_config[params->port].config)); 8186 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == 8187 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT) { 8188 DP(NETIF_MSG_LINK, "NOT enforcing module verification\n"); 8189 return 0; 8190 } 8191 8192 if (params->feature_config_flags & 8193 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY) { 8194 /* Use specific phy request */ 8195 cmd = DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL; 8196 } else if (params->feature_config_flags & 8197 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY) { 8198 /* Use first phy request only in case of non-dual media*/ 8199 if (DUAL_MEDIA(params)) { 8200 DP(NETIF_MSG_LINK, 8201 "FW does not support OPT MDL verification\n"); 8202 return -EINVAL; 8203 } 8204 cmd = DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL; 8205 } else { 8206 /* No support in OPT MDL detection */ 8207 DP(NETIF_MSG_LINK, 8208 "FW does not support OPT MDL verification\n"); 8209 return -EINVAL; 8210 } 8211 8212 fw_cmd_param = FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl); 8213 fw_resp = bnx2x_fw_command(bp, cmd, fw_cmd_param); 8214 if (fw_resp == FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS) { 8215 DP(NETIF_MSG_LINK, "Approved module\n"); 8216 return 0; 8217 } 8218 8219 /* Format the warning message */ 8220 if (bnx2x_read_sfp_module_eeprom(phy, 8221 params, 8222 I2C_DEV_ADDR_A0, 8223 SFP_EEPROM_VENDOR_NAME_ADDR, 8224 SFP_EEPROM_VENDOR_NAME_SIZE, 8225 (u8 *)vendor_name)) 8226 vendor_name[0] = '\0'; 8227 else 8228 vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE] = '\0'; 8229 if (bnx2x_read_sfp_module_eeprom(phy, 8230 params, 8231 I2C_DEV_ADDR_A0, 8232 SFP_EEPROM_PART_NO_ADDR, 8233 SFP_EEPROM_PART_NO_SIZE, 8234 (u8 *)vendor_pn)) 8235 vendor_pn[0] = '\0'; 8236 else 8237 vendor_pn[SFP_EEPROM_PART_NO_SIZE] = '\0'; 8238 8239 netdev_err(bp->dev, "Warning: Unqualified SFP+ module detected," 8240 " Port %d from %s part number %s\n", 8241 params->port, vendor_name, vendor_pn); 8242 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) != 8243 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG) 8244 phy->flags |= FLAGS_SFP_NOT_APPROVED; 8245 return -EINVAL; 8246 } 8247 8248 static int bnx2x_wait_for_sfp_module_initialized(struct bnx2x_phy *phy, 8249 struct link_params *params) 8250 8251 { 8252 u8 val; 8253 int rc; 8254 struct bnx2x *bp = params->bp; 8255 u16 timeout; 8256 /* Initialization time after hot-plug may take up to 300ms for 8257 * some phys type ( e.g. JDSU ) 8258 */ 8259 8260 for (timeout = 0; timeout < 60; timeout++) { 8261 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) 8262 rc = bnx2x_warpcore_read_sfp_module_eeprom( 8263 phy, params, I2C_DEV_ADDR_A0, 1, 1, &val, 8264 1); 8265 else 8266 rc = bnx2x_read_sfp_module_eeprom(phy, params, 8267 I2C_DEV_ADDR_A0, 8268 1, 1, &val); 8269 if (rc == 0) { 8270 DP(NETIF_MSG_LINK, 8271 "SFP+ module initialization took %d ms\n", 8272 timeout * 5); 8273 return 0; 8274 } 8275 usleep_range(5000, 10000); 8276 } 8277 rc = bnx2x_read_sfp_module_eeprom(phy, params, I2C_DEV_ADDR_A0, 8278 1, 1, &val); 8279 return rc; 8280 } 8281 8282 static void bnx2x_8727_power_module(struct bnx2x *bp, 8283 struct bnx2x_phy *phy, 8284 u8 is_power_up) { 8285 /* Make sure GPIOs are not using for LED mode */ 8286 u16 val; 8287 /* In the GPIO register, bit 4 is use to determine if the GPIOs are 8288 * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for 8289 * output 8290 * Bits 0-1 determine the GPIOs value for OUTPUT in case bit 4 val is 0 8291 * Bits 8-9 determine the GPIOs value for INPUT in case bit 4 val is 1 8292 * where the 1st bit is the over-current(only input), and 2nd bit is 8293 * for power( only output ) 8294 * 8295 * In case of NOC feature is disabled and power is up, set GPIO control 8296 * as input to enable listening of over-current indication 8297 */ 8298 if (phy->flags & FLAGS_NOC) 8299 return; 8300 if (is_power_up) 8301 val = (1<<4); 8302 else 8303 /* Set GPIO control to OUTPUT, and set the power bit 8304 * to according to the is_power_up 8305 */ 8306 val = (1<<1); 8307 8308 bnx2x_cl45_write(bp, phy, 8309 MDIO_PMA_DEVAD, 8310 MDIO_PMA_REG_8727_GPIO_CTRL, 8311 val); 8312 } 8313 8314 static int bnx2x_8726_set_limiting_mode(struct bnx2x *bp, 8315 struct bnx2x_phy *phy, 8316 u16 edc_mode) 8317 { 8318 u16 cur_limiting_mode; 8319 8320 bnx2x_cl45_read(bp, phy, 8321 MDIO_PMA_DEVAD, 8322 MDIO_PMA_REG_ROM_VER2, 8323 &cur_limiting_mode); 8324 DP(NETIF_MSG_LINK, "Current Limiting mode is 0x%x\n", 8325 cur_limiting_mode); 8326 8327 if (edc_mode == EDC_MODE_LIMITING) { 8328 DP(NETIF_MSG_LINK, "Setting LIMITING MODE\n"); 8329 bnx2x_cl45_write(bp, phy, 8330 MDIO_PMA_DEVAD, 8331 MDIO_PMA_REG_ROM_VER2, 8332 EDC_MODE_LIMITING); 8333 } else { /* LRM mode ( default )*/ 8334 8335 DP(NETIF_MSG_LINK, "Setting LRM MODE\n"); 8336 8337 /* Changing to LRM mode takes quite few seconds. So do it only 8338 * if current mode is limiting (default is LRM) 8339 */ 8340 if (cur_limiting_mode != EDC_MODE_LIMITING) 8341 return 0; 8342 8343 bnx2x_cl45_write(bp, phy, 8344 MDIO_PMA_DEVAD, 8345 MDIO_PMA_REG_LRM_MODE, 8346 0); 8347 bnx2x_cl45_write(bp, phy, 8348 MDIO_PMA_DEVAD, 8349 MDIO_PMA_REG_ROM_VER2, 8350 0x128); 8351 bnx2x_cl45_write(bp, phy, 8352 MDIO_PMA_DEVAD, 8353 MDIO_PMA_REG_MISC_CTRL0, 8354 0x4008); 8355 bnx2x_cl45_write(bp, phy, 8356 MDIO_PMA_DEVAD, 8357 MDIO_PMA_REG_LRM_MODE, 8358 0xaaaa); 8359 } 8360 return 0; 8361 } 8362 8363 static int bnx2x_8727_set_limiting_mode(struct bnx2x *bp, 8364 struct bnx2x_phy *phy, 8365 u16 edc_mode) 8366 { 8367 u16 phy_identifier; 8368 u16 rom_ver2_val; 8369 bnx2x_cl45_read(bp, phy, 8370 MDIO_PMA_DEVAD, 8371 MDIO_PMA_REG_PHY_IDENTIFIER, 8372 &phy_identifier); 8373 8374 bnx2x_cl45_write(bp, phy, 8375 MDIO_PMA_DEVAD, 8376 MDIO_PMA_REG_PHY_IDENTIFIER, 8377 (phy_identifier & ~(1<<9))); 8378 8379 bnx2x_cl45_read(bp, phy, 8380 MDIO_PMA_DEVAD, 8381 MDIO_PMA_REG_ROM_VER2, 8382 &rom_ver2_val); 8383 /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */ 8384 bnx2x_cl45_write(bp, phy, 8385 MDIO_PMA_DEVAD, 8386 MDIO_PMA_REG_ROM_VER2, 8387 (rom_ver2_val & 0xff00) | (edc_mode & 0x00ff)); 8388 8389 bnx2x_cl45_write(bp, phy, 8390 MDIO_PMA_DEVAD, 8391 MDIO_PMA_REG_PHY_IDENTIFIER, 8392 (phy_identifier | (1<<9))); 8393 8394 return 0; 8395 } 8396 8397 static void bnx2x_8727_specific_func(struct bnx2x_phy *phy, 8398 struct link_params *params, 8399 u32 action) 8400 { 8401 struct bnx2x *bp = params->bp; 8402 u16 val; 8403 switch (action) { 8404 case DISABLE_TX: 8405 bnx2x_sfp_set_transmitter(params, phy, 0); 8406 break; 8407 case ENABLE_TX: 8408 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED)) 8409 bnx2x_sfp_set_transmitter(params, phy, 1); 8410 break; 8411 case PHY_INIT: 8412 bnx2x_cl45_write(bp, phy, 8413 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, 8414 (1<<2) | (1<<5)); 8415 bnx2x_cl45_write(bp, phy, 8416 MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL, 8417 0); 8418 bnx2x_cl45_write(bp, phy, 8419 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0006); 8420 /* Make MOD_ABS give interrupt on change */ 8421 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 8422 MDIO_PMA_REG_8727_PCS_OPT_CTRL, 8423 &val); 8424 val |= (1<<12); 8425 if (phy->flags & FLAGS_NOC) 8426 val |= (3<<5); 8427 /* Set 8727 GPIOs to input to allow reading from the 8727 GPIO0 8428 * status which reflect SFP+ module over-current 8429 */ 8430 if (!(phy->flags & FLAGS_NOC)) 8431 val &= 0xff8f; /* Reset bits 4-6 */ 8432 bnx2x_cl45_write(bp, phy, 8433 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL, 8434 val); 8435 break; 8436 default: 8437 DP(NETIF_MSG_LINK, "Function 0x%x not supported by 8727\n", 8438 action); 8439 return; 8440 } 8441 } 8442 8443 static void bnx2x_set_e1e2_module_fault_led(struct link_params *params, 8444 u8 gpio_mode) 8445 { 8446 struct bnx2x *bp = params->bp; 8447 8448 u32 fault_led_gpio = REG_RD(bp, params->shmem_base + 8449 offsetof(struct shmem_region, 8450 dev_info.port_hw_config[params->port].sfp_ctrl)) & 8451 PORT_HW_CFG_FAULT_MODULE_LED_MASK; 8452 switch (fault_led_gpio) { 8453 case PORT_HW_CFG_FAULT_MODULE_LED_DISABLED: 8454 return; 8455 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO0: 8456 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO1: 8457 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO2: 8458 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO3: 8459 { 8460 u8 gpio_port = bnx2x_get_gpio_port(params); 8461 u16 gpio_pin = fault_led_gpio - 8462 PORT_HW_CFG_FAULT_MODULE_LED_GPIO0; 8463 DP(NETIF_MSG_LINK, "Set fault module-detected led " 8464 "pin %x port %x mode %x\n", 8465 gpio_pin, gpio_port, gpio_mode); 8466 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port); 8467 } 8468 break; 8469 default: 8470 DP(NETIF_MSG_LINK, "Error: Invalid fault led mode 0x%x\n", 8471 fault_led_gpio); 8472 } 8473 } 8474 8475 static void bnx2x_set_e3_module_fault_led(struct link_params *params, 8476 u8 gpio_mode) 8477 { 8478 u32 pin_cfg; 8479 u8 port = params->port; 8480 struct bnx2x *bp = params->bp; 8481 pin_cfg = (REG_RD(bp, params->shmem_base + 8482 offsetof(struct shmem_region, 8483 dev_info.port_hw_config[port].e3_sfp_ctrl)) & 8484 PORT_HW_CFG_E3_FAULT_MDL_LED_MASK) >> 8485 PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT; 8486 DP(NETIF_MSG_LINK, "Setting Fault LED to %d using pin cfg %d\n", 8487 gpio_mode, pin_cfg); 8488 bnx2x_set_cfg_pin(bp, pin_cfg, gpio_mode); 8489 } 8490 8491 static void bnx2x_set_sfp_module_fault_led(struct link_params *params, 8492 u8 gpio_mode) 8493 { 8494 struct bnx2x *bp = params->bp; 8495 DP(NETIF_MSG_LINK, "Setting SFP+ module fault LED to %d\n", gpio_mode); 8496 if (CHIP_IS_E3(bp)) { 8497 /* Low ==> if SFP+ module is supported otherwise 8498 * High ==> if SFP+ module is not on the approved vendor list 8499 */ 8500 bnx2x_set_e3_module_fault_led(params, gpio_mode); 8501 } else 8502 bnx2x_set_e1e2_module_fault_led(params, gpio_mode); 8503 } 8504 8505 static void bnx2x_warpcore_hw_reset(struct bnx2x_phy *phy, 8506 struct link_params *params) 8507 { 8508 struct bnx2x *bp = params->bp; 8509 bnx2x_warpcore_power_module(params, 0); 8510 /* Put Warpcore in low power mode */ 8511 REG_WR(bp, MISC_REG_WC0_RESET, 0x0c0e); 8512 8513 /* Put LCPLL in low power mode */ 8514 REG_WR(bp, MISC_REG_LCPLL_E40_PWRDWN, 1); 8515 REG_WR(bp, MISC_REG_LCPLL_E40_RESETB_ANA, 0); 8516 REG_WR(bp, MISC_REG_LCPLL_E40_RESETB_DIG, 0); 8517 } 8518 8519 static void bnx2x_power_sfp_module(struct link_params *params, 8520 struct bnx2x_phy *phy, 8521 u8 power) 8522 { 8523 struct bnx2x *bp = params->bp; 8524 DP(NETIF_MSG_LINK, "Setting SFP+ power to %x\n", power); 8525 8526 switch (phy->type) { 8527 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: 8528 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722: 8529 bnx2x_8727_power_module(params->bp, phy, power); 8530 break; 8531 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT: 8532 bnx2x_warpcore_power_module(params, power); 8533 break; 8534 default: 8535 break; 8536 } 8537 } 8538 static void bnx2x_warpcore_set_limiting_mode(struct link_params *params, 8539 struct bnx2x_phy *phy, 8540 u16 edc_mode) 8541 { 8542 u16 val = 0; 8543 u16 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT; 8544 struct bnx2x *bp = params->bp; 8545 8546 u8 lane = bnx2x_get_warpcore_lane(phy, params); 8547 /* This is a global register which controls all lanes */ 8548 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 8549 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val); 8550 val &= ~(0xf << (lane << 2)); 8551 8552 switch (edc_mode) { 8553 case EDC_MODE_LINEAR: 8554 case EDC_MODE_LIMITING: 8555 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT; 8556 break; 8557 case EDC_MODE_PASSIVE_DAC: 8558 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC; 8559 break; 8560 default: 8561 break; 8562 } 8563 8564 val |= (mode << (lane << 2)); 8565 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 8566 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, val); 8567 /* A must read */ 8568 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 8569 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val); 8570 8571 /* Restart microcode to re-read the new mode */ 8572 bnx2x_warpcore_reset_lane(bp, phy, 1); 8573 bnx2x_warpcore_reset_lane(bp, phy, 0); 8574 8575 } 8576 8577 static void bnx2x_set_limiting_mode(struct link_params *params, 8578 struct bnx2x_phy *phy, 8579 u16 edc_mode) 8580 { 8581 switch (phy->type) { 8582 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: 8583 bnx2x_8726_set_limiting_mode(params->bp, phy, edc_mode); 8584 break; 8585 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: 8586 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722: 8587 bnx2x_8727_set_limiting_mode(params->bp, phy, edc_mode); 8588 break; 8589 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT: 8590 bnx2x_warpcore_set_limiting_mode(params, phy, edc_mode); 8591 break; 8592 } 8593 } 8594 8595 int bnx2x_sfp_module_detection(struct bnx2x_phy *phy, 8596 struct link_params *params) 8597 { 8598 struct bnx2x *bp = params->bp; 8599 u16 edc_mode; 8600 int rc = 0; 8601 8602 u32 val = REG_RD(bp, params->shmem_base + 8603 offsetof(struct shmem_region, dev_info. 8604 port_feature_config[params->port].config)); 8605 /* Enabled transmitter by default */ 8606 bnx2x_sfp_set_transmitter(params, phy, 1); 8607 DP(NETIF_MSG_LINK, "SFP+ module plugged in/out detected on port %d\n", 8608 params->port); 8609 /* Power up module */ 8610 bnx2x_power_sfp_module(params, phy, 1); 8611 if (bnx2x_get_edc_mode(phy, params, &edc_mode) != 0) { 8612 DP(NETIF_MSG_LINK, "Failed to get valid module type\n"); 8613 return -EINVAL; 8614 } else if (bnx2x_verify_sfp_module(phy, params) != 0) { 8615 /* Check SFP+ module compatibility */ 8616 DP(NETIF_MSG_LINK, "Module verification failed!!\n"); 8617 rc = -EINVAL; 8618 /* Turn on fault module-detected led */ 8619 bnx2x_set_sfp_module_fault_led(params, 8620 MISC_REGISTERS_GPIO_HIGH); 8621 8622 /* Check if need to power down the SFP+ module */ 8623 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == 8624 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN) { 8625 DP(NETIF_MSG_LINK, "Shutdown SFP+ module!!\n"); 8626 bnx2x_power_sfp_module(params, phy, 0); 8627 return rc; 8628 } 8629 } else { 8630 /* Turn off fault module-detected led */ 8631 bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_LOW); 8632 } 8633 8634 /* Check and set limiting mode / LRM mode on 8726. On 8727 it 8635 * is done automatically 8636 */ 8637 bnx2x_set_limiting_mode(params, phy, edc_mode); 8638 8639 /* Disable transmit for this module if the module is not approved, and 8640 * laser needs to be disabled. 8641 */ 8642 if ((rc) && 8643 ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == 8644 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)) 8645 bnx2x_sfp_set_transmitter(params, phy, 0); 8646 8647 return rc; 8648 } 8649 8650 void bnx2x_handle_module_detect_int(struct link_params *params) 8651 { 8652 struct bnx2x *bp = params->bp; 8653 struct bnx2x_phy *phy; 8654 u32 gpio_val; 8655 u8 gpio_num, gpio_port; 8656 if (CHIP_IS_E3(bp)) { 8657 phy = ¶ms->phy[INT_PHY]; 8658 /* Always enable TX laser,will be disabled in case of fault */ 8659 bnx2x_sfp_set_transmitter(params, phy, 1); 8660 } else { 8661 phy = ¶ms->phy[EXT_PHY1]; 8662 } 8663 if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id, params->shmem_base, 8664 params->port, &gpio_num, &gpio_port) == 8665 -EINVAL) { 8666 DP(NETIF_MSG_LINK, "Failed to get MOD_ABS interrupt config\n"); 8667 return; 8668 } 8669 8670 /* Set valid module led off */ 8671 bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_HIGH); 8672 8673 /* Get current gpio val reflecting module plugged in / out*/ 8674 gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port); 8675 8676 /* Call the handling function in case module is detected */ 8677 if (gpio_val == 0) { 8678 bnx2x_set_mdio_emac_per_phy(bp, params); 8679 bnx2x_set_aer_mmd(params, phy); 8680 8681 bnx2x_power_sfp_module(params, phy, 1); 8682 bnx2x_set_gpio_int(bp, gpio_num, 8683 MISC_REGISTERS_GPIO_INT_OUTPUT_CLR, 8684 gpio_port); 8685 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0) { 8686 bnx2x_sfp_module_detection(phy, params); 8687 if (CHIP_IS_E3(bp)) { 8688 u16 rx_tx_in_reset; 8689 /* In case WC is out of reset, reconfigure the 8690 * link speed while taking into account 1G 8691 * module limitation. 8692 */ 8693 bnx2x_cl45_read(bp, phy, 8694 MDIO_WC_DEVAD, 8695 MDIO_WC_REG_DIGITAL5_MISC6, 8696 &rx_tx_in_reset); 8697 if ((!rx_tx_in_reset) && 8698 (params->link_flags & 8699 PHY_INITIALIZED)) { 8700 bnx2x_warpcore_reset_lane(bp, phy, 1); 8701 bnx2x_warpcore_config_sfi(phy, params); 8702 bnx2x_warpcore_reset_lane(bp, phy, 0); 8703 } 8704 } 8705 } else { 8706 DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n"); 8707 } 8708 } else { 8709 bnx2x_set_gpio_int(bp, gpio_num, 8710 MISC_REGISTERS_GPIO_INT_OUTPUT_SET, 8711 gpio_port); 8712 /* Module was plugged out. 8713 * Disable transmit for this module 8714 */ 8715 phy->media_type = ETH_PHY_NOT_PRESENT; 8716 } 8717 } 8718 8719 /******************************************************************/ 8720 /* Used by 8706 and 8727 */ 8721 /******************************************************************/ 8722 static void bnx2x_sfp_mask_fault(struct bnx2x *bp, 8723 struct bnx2x_phy *phy, 8724 u16 alarm_status_offset, 8725 u16 alarm_ctrl_offset) 8726 { 8727 u16 alarm_status, val; 8728 bnx2x_cl45_read(bp, phy, 8729 MDIO_PMA_DEVAD, alarm_status_offset, 8730 &alarm_status); 8731 bnx2x_cl45_read(bp, phy, 8732 MDIO_PMA_DEVAD, alarm_status_offset, 8733 &alarm_status); 8734 /* Mask or enable the fault event. */ 8735 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, &val); 8736 if (alarm_status & (1<<0)) 8737 val &= ~(1<<0); 8738 else 8739 val |= (1<<0); 8740 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, val); 8741 } 8742 /******************************************************************/ 8743 /* common BCM8706/BCM8726 PHY SECTION */ 8744 /******************************************************************/ 8745 static u8 bnx2x_8706_8726_read_status(struct bnx2x_phy *phy, 8746 struct link_params *params, 8747 struct link_vars *vars) 8748 { 8749 u8 link_up = 0; 8750 u16 val1, val2, rx_sd, pcs_status; 8751 struct bnx2x *bp = params->bp; 8752 DP(NETIF_MSG_LINK, "XGXS 8706/8726\n"); 8753 /* Clear RX Alarm*/ 8754 bnx2x_cl45_read(bp, phy, 8755 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2); 8756 8757 bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT, 8758 MDIO_PMA_LASI_TXCTRL); 8759 8760 /* Clear LASI indication*/ 8761 bnx2x_cl45_read(bp, phy, 8762 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1); 8763 bnx2x_cl45_read(bp, phy, 8764 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2); 8765 DP(NETIF_MSG_LINK, "8706/8726 LASI status 0x%x--> 0x%x\n", val1, val2); 8766 8767 bnx2x_cl45_read(bp, phy, 8768 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd); 8769 bnx2x_cl45_read(bp, phy, 8770 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &pcs_status); 8771 bnx2x_cl45_read(bp, phy, 8772 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2); 8773 bnx2x_cl45_read(bp, phy, 8774 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2); 8775 8776 DP(NETIF_MSG_LINK, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps" 8777 " link_status 0x%x\n", rx_sd, pcs_status, val2); 8778 /* Link is up if both bit 0 of pmd_rx_sd and bit 0 of pcs_status 8779 * are set, or if the autoneg bit 1 is set 8780 */ 8781 link_up = ((rx_sd & pcs_status & 0x1) || (val2 & (1<<1))); 8782 if (link_up) { 8783 if (val2 & (1<<1)) 8784 vars->line_speed = SPEED_1000; 8785 else 8786 vars->line_speed = SPEED_10000; 8787 bnx2x_ext_phy_resolve_fc(phy, params, vars); 8788 vars->duplex = DUPLEX_FULL; 8789 } 8790 8791 /* Capture 10G link fault. Read twice to clear stale value. */ 8792 if (vars->line_speed == SPEED_10000) { 8793 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 8794 MDIO_PMA_LASI_TXSTAT, &val1); 8795 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 8796 MDIO_PMA_LASI_TXSTAT, &val1); 8797 if (val1 & (1<<0)) 8798 vars->fault_detected = 1; 8799 } 8800 8801 return link_up; 8802 } 8803 8804 /******************************************************************/ 8805 /* BCM8706 PHY SECTION */ 8806 /******************************************************************/ 8807 static u8 bnx2x_8706_config_init(struct bnx2x_phy *phy, 8808 struct link_params *params, 8809 struct link_vars *vars) 8810 { 8811 u32 tx_en_mode; 8812 u16 cnt, val, tmp1; 8813 struct bnx2x *bp = params->bp; 8814 8815 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 8816 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); 8817 /* HW reset */ 8818 bnx2x_ext_phy_hw_reset(bp, params->port); 8819 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040); 8820 bnx2x_wait_reset_complete(bp, phy, params); 8821 8822 /* Wait until fw is loaded */ 8823 for (cnt = 0; cnt < 100; cnt++) { 8824 bnx2x_cl45_read(bp, phy, 8825 MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER1, &val); 8826 if (val) 8827 break; 8828 usleep_range(10000, 20000); 8829 } 8830 DP(NETIF_MSG_LINK, "XGXS 8706 is initialized after %d ms\n", cnt); 8831 if ((params->feature_config_flags & 8832 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) { 8833 u8 i; 8834 u16 reg; 8835 for (i = 0; i < 4; i++) { 8836 reg = MDIO_XS_8706_REG_BANK_RX0 + 8837 i*(MDIO_XS_8706_REG_BANK_RX1 - 8838 MDIO_XS_8706_REG_BANK_RX0); 8839 bnx2x_cl45_read(bp, phy, MDIO_XS_DEVAD, reg, &val); 8840 /* Clear first 3 bits of the control */ 8841 val &= ~0x7; 8842 /* Set control bits according to configuration */ 8843 val |= (phy->rx_preemphasis[i] & 0x7); 8844 DP(NETIF_MSG_LINK, "Setting RX Equalizer to BCM8706" 8845 " reg 0x%x <-- val 0x%x\n", reg, val); 8846 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, reg, val); 8847 } 8848 } 8849 /* Force speed */ 8850 if (phy->req_line_speed == SPEED_10000) { 8851 DP(NETIF_MSG_LINK, "XGXS 8706 force 10Gbps\n"); 8852 8853 bnx2x_cl45_write(bp, phy, 8854 MDIO_PMA_DEVAD, 8855 MDIO_PMA_REG_DIGITAL_CTRL, 0x400); 8856 bnx2x_cl45_write(bp, phy, 8857 MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL, 8858 0); 8859 /* Arm LASI for link and Tx fault. */ 8860 bnx2x_cl45_write(bp, phy, 8861 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 3); 8862 } else { 8863 /* Force 1Gbps using autoneg with 1G advertisement */ 8864 8865 /* Allow CL37 through CL73 */ 8866 DP(NETIF_MSG_LINK, "XGXS 8706 AutoNeg\n"); 8867 bnx2x_cl45_write(bp, phy, 8868 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c); 8869 8870 /* Enable Full-Duplex advertisement on CL37 */ 8871 bnx2x_cl45_write(bp, phy, 8872 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LP, 0x0020); 8873 /* Enable CL37 AN */ 8874 bnx2x_cl45_write(bp, phy, 8875 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000); 8876 /* 1G support */ 8877 bnx2x_cl45_write(bp, phy, 8878 MDIO_AN_DEVAD, MDIO_AN_REG_ADV, (1<<5)); 8879 8880 /* Enable clause 73 AN */ 8881 bnx2x_cl45_write(bp, phy, 8882 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200); 8883 bnx2x_cl45_write(bp, phy, 8884 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, 8885 0x0400); 8886 bnx2x_cl45_write(bp, phy, 8887 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 8888 0x0004); 8889 } 8890 bnx2x_save_bcm_spirom_ver(bp, phy, params->port); 8891 8892 /* If TX Laser is controlled by GPIO_0, do not let PHY go into low 8893 * power mode, if TX Laser is disabled 8894 */ 8895 8896 tx_en_mode = REG_RD(bp, params->shmem_base + 8897 offsetof(struct shmem_region, 8898 dev_info.port_hw_config[params->port].sfp_ctrl)) 8899 & PORT_HW_CFG_TX_LASER_MASK; 8900 8901 if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) { 8902 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n"); 8903 bnx2x_cl45_read(bp, phy, 8904 MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, &tmp1); 8905 tmp1 |= 0x1; 8906 bnx2x_cl45_write(bp, phy, 8907 MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, tmp1); 8908 } 8909 8910 return 0; 8911 } 8912 8913 static int bnx2x_8706_read_status(struct bnx2x_phy *phy, 8914 struct link_params *params, 8915 struct link_vars *vars) 8916 { 8917 return bnx2x_8706_8726_read_status(phy, params, vars); 8918 } 8919 8920 /******************************************************************/ 8921 /* BCM8726 PHY SECTION */ 8922 /******************************************************************/ 8923 static void bnx2x_8726_config_loopback(struct bnx2x_phy *phy, 8924 struct link_params *params) 8925 { 8926 struct bnx2x *bp = params->bp; 8927 DP(NETIF_MSG_LINK, "PMA/PMD ext_phy_loopback: 8726\n"); 8928 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001); 8929 } 8930 8931 static void bnx2x_8726_external_rom_boot(struct bnx2x_phy *phy, 8932 struct link_params *params) 8933 { 8934 struct bnx2x *bp = params->bp; 8935 /* Need to wait 100ms after reset */ 8936 msleep(100); 8937 8938 /* Micro controller re-boot */ 8939 bnx2x_cl45_write(bp, phy, 8940 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x018B); 8941 8942 /* Set soft reset */ 8943 bnx2x_cl45_write(bp, phy, 8944 MDIO_PMA_DEVAD, 8945 MDIO_PMA_REG_GEN_CTRL, 8946 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET); 8947 8948 bnx2x_cl45_write(bp, phy, 8949 MDIO_PMA_DEVAD, 8950 MDIO_PMA_REG_MISC_CTRL1, 0x0001); 8951 8952 bnx2x_cl45_write(bp, phy, 8953 MDIO_PMA_DEVAD, 8954 MDIO_PMA_REG_GEN_CTRL, 8955 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP); 8956 8957 /* Wait for 150ms for microcode load */ 8958 msleep(150); 8959 8960 /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */ 8961 bnx2x_cl45_write(bp, phy, 8962 MDIO_PMA_DEVAD, 8963 MDIO_PMA_REG_MISC_CTRL1, 0x0000); 8964 8965 msleep(200); 8966 bnx2x_save_bcm_spirom_ver(bp, phy, params->port); 8967 } 8968 8969 static u8 bnx2x_8726_read_status(struct bnx2x_phy *phy, 8970 struct link_params *params, 8971 struct link_vars *vars) 8972 { 8973 struct bnx2x *bp = params->bp; 8974 u16 val1; 8975 u8 link_up = bnx2x_8706_8726_read_status(phy, params, vars); 8976 if (link_up) { 8977 bnx2x_cl45_read(bp, phy, 8978 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 8979 &val1); 8980 if (val1 & (1<<15)) { 8981 DP(NETIF_MSG_LINK, "Tx is disabled\n"); 8982 link_up = 0; 8983 vars->line_speed = 0; 8984 } 8985 } 8986 return link_up; 8987 } 8988 8989 8990 static int bnx2x_8726_config_init(struct bnx2x_phy *phy, 8991 struct link_params *params, 8992 struct link_vars *vars) 8993 { 8994 struct bnx2x *bp = params->bp; 8995 DP(NETIF_MSG_LINK, "Initializing BCM8726\n"); 8996 8997 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15); 8998 bnx2x_wait_reset_complete(bp, phy, params); 8999 9000 bnx2x_8726_external_rom_boot(phy, params); 9001 9002 /* Need to call module detected on initialization since the module 9003 * detection triggered by actual module insertion might occur before 9004 * driver is loaded, and when driver is loaded, it reset all 9005 * registers, including the transmitter 9006 */ 9007 bnx2x_sfp_module_detection(phy, params); 9008 9009 if (phy->req_line_speed == SPEED_1000) { 9010 DP(NETIF_MSG_LINK, "Setting 1G force\n"); 9011 bnx2x_cl45_write(bp, phy, 9012 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40); 9013 bnx2x_cl45_write(bp, phy, 9014 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD); 9015 bnx2x_cl45_write(bp, phy, 9016 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x5); 9017 bnx2x_cl45_write(bp, phy, 9018 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, 9019 0x400); 9020 } else if ((phy->req_line_speed == SPEED_AUTO_NEG) && 9021 (phy->speed_cap_mask & 9022 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) && 9023 ((phy->speed_cap_mask & 9024 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) != 9025 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) { 9026 DP(NETIF_MSG_LINK, "Setting 1G clause37\n"); 9027 /* Set Flow control */ 9028 bnx2x_ext_phy_set_pause(params, phy, vars); 9029 bnx2x_cl45_write(bp, phy, 9030 MDIO_AN_DEVAD, MDIO_AN_REG_ADV, 0x20); 9031 bnx2x_cl45_write(bp, phy, 9032 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c); 9033 bnx2x_cl45_write(bp, phy, 9034 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, 0x0020); 9035 bnx2x_cl45_write(bp, phy, 9036 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000); 9037 bnx2x_cl45_write(bp, phy, 9038 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200); 9039 /* Enable RX-ALARM control to receive interrupt for 1G speed 9040 * change 9041 */ 9042 bnx2x_cl45_write(bp, phy, 9043 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x4); 9044 bnx2x_cl45_write(bp, phy, 9045 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, 9046 0x400); 9047 9048 } else { /* Default 10G. Set only LASI control */ 9049 bnx2x_cl45_write(bp, phy, 9050 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 1); 9051 } 9052 9053 /* Set TX PreEmphasis if needed */ 9054 if ((params->feature_config_flags & 9055 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) { 9056 DP(NETIF_MSG_LINK, 9057 "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n", 9058 phy->tx_preemphasis[0], 9059 phy->tx_preemphasis[1]); 9060 bnx2x_cl45_write(bp, phy, 9061 MDIO_PMA_DEVAD, 9062 MDIO_PMA_REG_8726_TX_CTRL1, 9063 phy->tx_preemphasis[0]); 9064 9065 bnx2x_cl45_write(bp, phy, 9066 MDIO_PMA_DEVAD, 9067 MDIO_PMA_REG_8726_TX_CTRL2, 9068 phy->tx_preemphasis[1]); 9069 } 9070 9071 return 0; 9072 9073 } 9074 9075 static void bnx2x_8726_link_reset(struct bnx2x_phy *phy, 9076 struct link_params *params) 9077 { 9078 struct bnx2x *bp = params->bp; 9079 DP(NETIF_MSG_LINK, "bnx2x_8726_link_reset port %d\n", params->port); 9080 /* Set serial boot control for external load */ 9081 bnx2x_cl45_write(bp, phy, 9082 MDIO_PMA_DEVAD, 9083 MDIO_PMA_REG_GEN_CTRL, 0x0001); 9084 } 9085 9086 /******************************************************************/ 9087 /* BCM8727 PHY SECTION */ 9088 /******************************************************************/ 9089 9090 static void bnx2x_8727_set_link_led(struct bnx2x_phy *phy, 9091 struct link_params *params, u8 mode) 9092 { 9093 struct bnx2x *bp = params->bp; 9094 u16 led_mode_bitmask = 0; 9095 u16 gpio_pins_bitmask = 0; 9096 u16 val; 9097 /* Only NOC flavor requires to set the LED specifically */ 9098 if (!(phy->flags & FLAGS_NOC)) 9099 return; 9100 switch (mode) { 9101 case LED_MODE_FRONT_PANEL_OFF: 9102 case LED_MODE_OFF: 9103 led_mode_bitmask = 0; 9104 gpio_pins_bitmask = 0x03; 9105 break; 9106 case LED_MODE_ON: 9107 led_mode_bitmask = 0; 9108 gpio_pins_bitmask = 0x02; 9109 break; 9110 case LED_MODE_OPER: 9111 led_mode_bitmask = 0x60; 9112 gpio_pins_bitmask = 0x11; 9113 break; 9114 } 9115 bnx2x_cl45_read(bp, phy, 9116 MDIO_PMA_DEVAD, 9117 MDIO_PMA_REG_8727_PCS_OPT_CTRL, 9118 &val); 9119 val &= 0xff8f; 9120 val |= led_mode_bitmask; 9121 bnx2x_cl45_write(bp, phy, 9122 MDIO_PMA_DEVAD, 9123 MDIO_PMA_REG_8727_PCS_OPT_CTRL, 9124 val); 9125 bnx2x_cl45_read(bp, phy, 9126 MDIO_PMA_DEVAD, 9127 MDIO_PMA_REG_8727_GPIO_CTRL, 9128 &val); 9129 val &= 0xffe0; 9130 val |= gpio_pins_bitmask; 9131 bnx2x_cl45_write(bp, phy, 9132 MDIO_PMA_DEVAD, 9133 MDIO_PMA_REG_8727_GPIO_CTRL, 9134 val); 9135 } 9136 static void bnx2x_8727_hw_reset(struct bnx2x_phy *phy, 9137 struct link_params *params) { 9138 u32 swap_val, swap_override; 9139 u8 port; 9140 /* The PHY reset is controlled by GPIO 1. Fake the port number 9141 * to cancel the swap done in set_gpio() 9142 */ 9143 struct bnx2x *bp = params->bp; 9144 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); 9145 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); 9146 port = (swap_val && swap_override) ^ 1; 9147 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, 9148 MISC_REGISTERS_GPIO_OUTPUT_LOW, port); 9149 } 9150 9151 static void bnx2x_8727_config_speed(struct bnx2x_phy *phy, 9152 struct link_params *params) 9153 { 9154 struct bnx2x *bp = params->bp; 9155 u16 tmp1, val; 9156 /* Set option 1G speed */ 9157 if ((phy->req_line_speed == SPEED_1000) || 9158 (phy->media_type == ETH_PHY_SFP_1G_FIBER)) { 9159 DP(NETIF_MSG_LINK, "Setting 1G force\n"); 9160 bnx2x_cl45_write(bp, phy, 9161 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40); 9162 bnx2x_cl45_write(bp, phy, 9163 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD); 9164 bnx2x_cl45_read(bp, phy, 9165 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, &tmp1); 9166 DP(NETIF_MSG_LINK, "1.7 = 0x%x\n", tmp1); 9167 /* Power down the XAUI until link is up in case of dual-media 9168 * and 1G 9169 */ 9170 if (DUAL_MEDIA(params)) { 9171 bnx2x_cl45_read(bp, phy, 9172 MDIO_PMA_DEVAD, 9173 MDIO_PMA_REG_8727_PCS_GP, &val); 9174 val |= (3<<10); 9175 bnx2x_cl45_write(bp, phy, 9176 MDIO_PMA_DEVAD, 9177 MDIO_PMA_REG_8727_PCS_GP, val); 9178 } 9179 } else if ((phy->req_line_speed == SPEED_AUTO_NEG) && 9180 ((phy->speed_cap_mask & 9181 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) && 9182 ((phy->speed_cap_mask & 9183 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) != 9184 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) { 9185 9186 DP(NETIF_MSG_LINK, "Setting 1G clause37\n"); 9187 bnx2x_cl45_write(bp, phy, 9188 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 0); 9189 bnx2x_cl45_write(bp, phy, 9190 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1300); 9191 } else { 9192 /* Since the 8727 has only single reset pin, need to set the 10G 9193 * registers although it is default 9194 */ 9195 bnx2x_cl45_write(bp, phy, 9196 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 9197 0x0020); 9198 bnx2x_cl45_write(bp, phy, 9199 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x0100); 9200 bnx2x_cl45_write(bp, phy, 9201 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040); 9202 bnx2x_cl45_write(bp, phy, 9203 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 9204 0x0008); 9205 } 9206 } 9207 9208 static int bnx2x_8727_config_init(struct bnx2x_phy *phy, 9209 struct link_params *params, 9210 struct link_vars *vars) 9211 { 9212 u32 tx_en_mode; 9213 u16 tmp1, mod_abs, tmp2; 9214 struct bnx2x *bp = params->bp; 9215 /* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */ 9216 9217 bnx2x_wait_reset_complete(bp, phy, params); 9218 9219 DP(NETIF_MSG_LINK, "Initializing BCM8727\n"); 9220 9221 bnx2x_8727_specific_func(phy, params, PHY_INIT); 9222 /* Initially configure MOD_ABS to interrupt when module is 9223 * presence( bit 8) 9224 */ 9225 bnx2x_cl45_read(bp, phy, 9226 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs); 9227 /* Set EDC off by setting OPTXLOS signal input to low (bit 9). 9228 * When the EDC is off it locks onto a reference clock and avoids 9229 * becoming 'lost' 9230 */ 9231 mod_abs &= ~(1<<8); 9232 if (!(phy->flags & FLAGS_NOC)) 9233 mod_abs &= ~(1<<9); 9234 bnx2x_cl45_write(bp, phy, 9235 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs); 9236 9237 /* Enable/Disable PHY transmitter output */ 9238 bnx2x_set_disable_pmd_transmit(params, phy, 0); 9239 9240 bnx2x_8727_power_module(bp, phy, 1); 9241 9242 bnx2x_cl45_read(bp, phy, 9243 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1); 9244 9245 bnx2x_cl45_read(bp, phy, 9246 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1); 9247 9248 bnx2x_8727_config_speed(phy, params); 9249 9250 9251 /* Set TX PreEmphasis if needed */ 9252 if ((params->feature_config_flags & 9253 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) { 9254 DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n", 9255 phy->tx_preemphasis[0], 9256 phy->tx_preemphasis[1]); 9257 bnx2x_cl45_write(bp, phy, 9258 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL1, 9259 phy->tx_preemphasis[0]); 9260 9261 bnx2x_cl45_write(bp, phy, 9262 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL2, 9263 phy->tx_preemphasis[1]); 9264 } 9265 9266 /* If TX Laser is controlled by GPIO_0, do not let PHY go into low 9267 * power mode, if TX Laser is disabled 9268 */ 9269 tx_en_mode = REG_RD(bp, params->shmem_base + 9270 offsetof(struct shmem_region, 9271 dev_info.port_hw_config[params->port].sfp_ctrl)) 9272 & PORT_HW_CFG_TX_LASER_MASK; 9273 9274 if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) { 9275 9276 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n"); 9277 bnx2x_cl45_read(bp, phy, 9278 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, &tmp2); 9279 tmp2 |= 0x1000; 9280 tmp2 &= 0xFFEF; 9281 bnx2x_cl45_write(bp, phy, 9282 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, tmp2); 9283 bnx2x_cl45_read(bp, phy, 9284 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 9285 &tmp2); 9286 bnx2x_cl45_write(bp, phy, 9287 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 9288 (tmp2 & 0x7fff)); 9289 } 9290 9291 return 0; 9292 } 9293 9294 static void bnx2x_8727_handle_mod_abs(struct bnx2x_phy *phy, 9295 struct link_params *params) 9296 { 9297 struct bnx2x *bp = params->bp; 9298 u16 mod_abs, rx_alarm_status; 9299 u32 val = REG_RD(bp, params->shmem_base + 9300 offsetof(struct shmem_region, dev_info. 9301 port_feature_config[params->port]. 9302 config)); 9303 bnx2x_cl45_read(bp, phy, 9304 MDIO_PMA_DEVAD, 9305 MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs); 9306 if (mod_abs & (1<<8)) { 9307 9308 /* Module is absent */ 9309 DP(NETIF_MSG_LINK, 9310 "MOD_ABS indication show module is absent\n"); 9311 phy->media_type = ETH_PHY_NOT_PRESENT; 9312 /* 1. Set mod_abs to detect next module 9313 * presence event 9314 * 2. Set EDC off by setting OPTXLOS signal input to low 9315 * (bit 9). 9316 * When the EDC is off it locks onto a reference clock and 9317 * avoids becoming 'lost'. 9318 */ 9319 mod_abs &= ~(1<<8); 9320 if (!(phy->flags & FLAGS_NOC)) 9321 mod_abs &= ~(1<<9); 9322 bnx2x_cl45_write(bp, phy, 9323 MDIO_PMA_DEVAD, 9324 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs); 9325 9326 /* Clear RX alarm since it stays up as long as 9327 * the mod_abs wasn't changed 9328 */ 9329 bnx2x_cl45_read(bp, phy, 9330 MDIO_PMA_DEVAD, 9331 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status); 9332 9333 } else { 9334 /* Module is present */ 9335 DP(NETIF_MSG_LINK, 9336 "MOD_ABS indication show module is present\n"); 9337 /* First disable transmitter, and if the module is ok, the 9338 * module_detection will enable it 9339 * 1. Set mod_abs to detect next module absent event ( bit 8) 9340 * 2. Restore the default polarity of the OPRXLOS signal and 9341 * this signal will then correctly indicate the presence or 9342 * absence of the Rx signal. (bit 9) 9343 */ 9344 mod_abs |= (1<<8); 9345 if (!(phy->flags & FLAGS_NOC)) 9346 mod_abs |= (1<<9); 9347 bnx2x_cl45_write(bp, phy, 9348 MDIO_PMA_DEVAD, 9349 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs); 9350 9351 /* Clear RX alarm since it stays up as long as the mod_abs 9352 * wasn't changed. This is need to be done before calling the 9353 * module detection, otherwise it will clear* the link update 9354 * alarm 9355 */ 9356 bnx2x_cl45_read(bp, phy, 9357 MDIO_PMA_DEVAD, 9358 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status); 9359 9360 9361 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == 9362 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER) 9363 bnx2x_sfp_set_transmitter(params, phy, 0); 9364 9365 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0) 9366 bnx2x_sfp_module_detection(phy, params); 9367 else 9368 DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n"); 9369 9370 /* Reconfigure link speed based on module type limitations */ 9371 bnx2x_8727_config_speed(phy, params); 9372 } 9373 9374 DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n", 9375 rx_alarm_status); 9376 /* No need to check link status in case of module plugged in/out */ 9377 } 9378 9379 static u8 bnx2x_8727_read_status(struct bnx2x_phy *phy, 9380 struct link_params *params, 9381 struct link_vars *vars) 9382 9383 { 9384 struct bnx2x *bp = params->bp; 9385 u8 link_up = 0, oc_port = params->port; 9386 u16 link_status = 0; 9387 u16 rx_alarm_status, lasi_ctrl, val1; 9388 9389 /* If PHY is not initialized, do not check link status */ 9390 bnx2x_cl45_read(bp, phy, 9391 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 9392 &lasi_ctrl); 9393 if (!lasi_ctrl) 9394 return 0; 9395 9396 /* Check the LASI on Rx */ 9397 bnx2x_cl45_read(bp, phy, 9398 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, 9399 &rx_alarm_status); 9400 vars->line_speed = 0; 9401 DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n", rx_alarm_status); 9402 9403 bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT, 9404 MDIO_PMA_LASI_TXCTRL); 9405 9406 bnx2x_cl45_read(bp, phy, 9407 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1); 9408 9409 DP(NETIF_MSG_LINK, "8727 LASI status 0x%x\n", val1); 9410 9411 /* Clear MSG-OUT */ 9412 bnx2x_cl45_read(bp, phy, 9413 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1); 9414 9415 /* If a module is present and there is need to check 9416 * for over current 9417 */ 9418 if (!(phy->flags & FLAGS_NOC) && !(rx_alarm_status & (1<<5))) { 9419 /* Check over-current using 8727 GPIO0 input*/ 9420 bnx2x_cl45_read(bp, phy, 9421 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL, 9422 &val1); 9423 9424 if ((val1 & (1<<8)) == 0) { 9425 if (!CHIP_IS_E1x(bp)) 9426 oc_port = BP_PATH(bp) + (params->port << 1); 9427 DP(NETIF_MSG_LINK, 9428 "8727 Power fault has been detected on port %d\n", 9429 oc_port); 9430 netdev_err(bp->dev, "Error: Power fault on Port %d has " 9431 "been detected and the power to " 9432 "that SFP+ module has been removed " 9433 "to prevent failure of the card. " 9434 "Please remove the SFP+ module and " 9435 "restart the system to clear this " 9436 "error.\n", 9437 oc_port); 9438 /* Disable all RX_ALARMs except for mod_abs */ 9439 bnx2x_cl45_write(bp, phy, 9440 MDIO_PMA_DEVAD, 9441 MDIO_PMA_LASI_RXCTRL, (1<<5)); 9442 9443 bnx2x_cl45_read(bp, phy, 9444 MDIO_PMA_DEVAD, 9445 MDIO_PMA_REG_PHY_IDENTIFIER, &val1); 9446 /* Wait for module_absent_event */ 9447 val1 |= (1<<8); 9448 bnx2x_cl45_write(bp, phy, 9449 MDIO_PMA_DEVAD, 9450 MDIO_PMA_REG_PHY_IDENTIFIER, val1); 9451 /* Clear RX alarm */ 9452 bnx2x_cl45_read(bp, phy, 9453 MDIO_PMA_DEVAD, 9454 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status); 9455 bnx2x_8727_power_module(params->bp, phy, 0); 9456 return 0; 9457 } 9458 } /* Over current check */ 9459 9460 /* When module absent bit is set, check module */ 9461 if (rx_alarm_status & (1<<5)) { 9462 bnx2x_8727_handle_mod_abs(phy, params); 9463 /* Enable all mod_abs and link detection bits */ 9464 bnx2x_cl45_write(bp, phy, 9465 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, 9466 ((1<<5) | (1<<2))); 9467 } 9468 9469 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED)) { 9470 DP(NETIF_MSG_LINK, "Enabling 8727 TX laser\n"); 9471 bnx2x_sfp_set_transmitter(params, phy, 1); 9472 } else { 9473 DP(NETIF_MSG_LINK, "Tx is disabled\n"); 9474 return 0; 9475 } 9476 9477 bnx2x_cl45_read(bp, phy, 9478 MDIO_PMA_DEVAD, 9479 MDIO_PMA_REG_8073_SPEED_LINK_STATUS, &link_status); 9480 9481 /* Bits 0..2 --> speed detected, 9482 * Bits 13..15--> link is down 9483 */ 9484 if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) { 9485 link_up = 1; 9486 vars->line_speed = SPEED_10000; 9487 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n", 9488 params->port); 9489 } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) { 9490 link_up = 1; 9491 vars->line_speed = SPEED_1000; 9492 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n", 9493 params->port); 9494 } else { 9495 link_up = 0; 9496 DP(NETIF_MSG_LINK, "port %x: External link is down\n", 9497 params->port); 9498 } 9499 9500 /* Capture 10G link fault. */ 9501 if (vars->line_speed == SPEED_10000) { 9502 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 9503 MDIO_PMA_LASI_TXSTAT, &val1); 9504 9505 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 9506 MDIO_PMA_LASI_TXSTAT, &val1); 9507 9508 if (val1 & (1<<0)) { 9509 vars->fault_detected = 1; 9510 } 9511 } 9512 9513 if (link_up) { 9514 bnx2x_ext_phy_resolve_fc(phy, params, vars); 9515 vars->duplex = DUPLEX_FULL; 9516 DP(NETIF_MSG_LINK, "duplex = 0x%x\n", vars->duplex); 9517 } 9518 9519 if ((DUAL_MEDIA(params)) && 9520 (phy->req_line_speed == SPEED_1000)) { 9521 bnx2x_cl45_read(bp, phy, 9522 MDIO_PMA_DEVAD, 9523 MDIO_PMA_REG_8727_PCS_GP, &val1); 9524 /* In case of dual-media board and 1G, power up the XAUI side, 9525 * otherwise power it down. For 10G it is done automatically 9526 */ 9527 if (link_up) 9528 val1 &= ~(3<<10); 9529 else 9530 val1 |= (3<<10); 9531 bnx2x_cl45_write(bp, phy, 9532 MDIO_PMA_DEVAD, 9533 MDIO_PMA_REG_8727_PCS_GP, val1); 9534 } 9535 return link_up; 9536 } 9537 9538 static void bnx2x_8727_link_reset(struct bnx2x_phy *phy, 9539 struct link_params *params) 9540 { 9541 struct bnx2x *bp = params->bp; 9542 9543 /* Enable/Disable PHY transmitter output */ 9544 bnx2x_set_disable_pmd_transmit(params, phy, 1); 9545 9546 /* Disable Transmitter */ 9547 bnx2x_sfp_set_transmitter(params, phy, 0); 9548 /* Clear LASI */ 9549 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0); 9550 9551 } 9552 9553 /******************************************************************/ 9554 /* BCM8481/BCM84823/BCM84833 PHY SECTION */ 9555 /******************************************************************/ 9556 static void bnx2x_save_848xx_spirom_version(struct bnx2x_phy *phy, 9557 struct bnx2x *bp, 9558 u8 port) 9559 { 9560 u16 val, fw_ver2, cnt, i; 9561 static struct bnx2x_reg_set reg_set[] = { 9562 {MDIO_PMA_DEVAD, 0xA819, 0x0014}, 9563 {MDIO_PMA_DEVAD, 0xA81A, 0xc200}, 9564 {MDIO_PMA_DEVAD, 0xA81B, 0x0000}, 9565 {MDIO_PMA_DEVAD, 0xA81C, 0x0300}, 9566 {MDIO_PMA_DEVAD, 0xA817, 0x0009} 9567 }; 9568 u16 fw_ver1; 9569 9570 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) || 9571 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) { 9572 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 0x400f, &fw_ver1); 9573 bnx2x_save_spirom_version(bp, port, fw_ver1 & 0xfff, 9574 phy->ver_addr); 9575 } else { 9576 /* For 32-bit registers in 848xx, access via MDIO2ARM i/f. */ 9577 /* (1) set reg 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */ 9578 for (i = 0; i < ARRAY_SIZE(reg_set); i++) 9579 bnx2x_cl45_write(bp, phy, reg_set[i].devad, 9580 reg_set[i].reg, reg_set[i].val); 9581 9582 for (cnt = 0; cnt < 100; cnt++) { 9583 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val); 9584 if (val & 1) 9585 break; 9586 udelay(5); 9587 } 9588 if (cnt == 100) { 9589 DP(NETIF_MSG_LINK, "Unable to read 848xx " 9590 "phy fw version(1)\n"); 9591 bnx2x_save_spirom_version(bp, port, 0, 9592 phy->ver_addr); 9593 return; 9594 } 9595 9596 9597 /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */ 9598 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0000); 9599 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200); 9600 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x000A); 9601 for (cnt = 0; cnt < 100; cnt++) { 9602 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val); 9603 if (val & 1) 9604 break; 9605 udelay(5); 9606 } 9607 if (cnt == 100) { 9608 DP(NETIF_MSG_LINK, "Unable to read 848xx phy fw " 9609 "version(2)\n"); 9610 bnx2x_save_spirom_version(bp, port, 0, 9611 phy->ver_addr); 9612 return; 9613 } 9614 9615 /* lower 16 bits of the register SPI_FW_STATUS */ 9616 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81B, &fw_ver1); 9617 /* upper 16 bits of register SPI_FW_STATUS */ 9618 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81C, &fw_ver2); 9619 9620 bnx2x_save_spirom_version(bp, port, (fw_ver2<<16) | fw_ver1, 9621 phy->ver_addr); 9622 } 9623 9624 } 9625 static void bnx2x_848xx_set_led(struct bnx2x *bp, 9626 struct bnx2x_phy *phy) 9627 { 9628 u16 val, offset, i; 9629 static struct bnx2x_reg_set reg_set[] = { 9630 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED1_MASK, 0x0080}, 9631 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED2_MASK, 0x0018}, 9632 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED3_MASK, 0x0006}, 9633 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED3_BLINK, 0x0000}, 9634 {MDIO_PMA_DEVAD, MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH, 9635 MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ}, 9636 {MDIO_AN_DEVAD, 0xFFFB, 0xFFFD} 9637 }; 9638 /* PHYC_CTL_LED_CTL */ 9639 bnx2x_cl45_read(bp, phy, 9640 MDIO_PMA_DEVAD, 9641 MDIO_PMA_REG_8481_LINK_SIGNAL, &val); 9642 val &= 0xFE00; 9643 val |= 0x0092; 9644 9645 bnx2x_cl45_write(bp, phy, 9646 MDIO_PMA_DEVAD, 9647 MDIO_PMA_REG_8481_LINK_SIGNAL, val); 9648 9649 for (i = 0; i < ARRAY_SIZE(reg_set); i++) 9650 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg, 9651 reg_set[i].val); 9652 9653 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) || 9654 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) 9655 offset = MDIO_PMA_REG_84833_CTL_LED_CTL_1; 9656 else 9657 offset = MDIO_PMA_REG_84823_CTL_LED_CTL_1; 9658 9659 /* stretch_en for LED3*/ 9660 bnx2x_cl45_read_or_write(bp, phy, 9661 MDIO_PMA_DEVAD, offset, 9662 MDIO_PMA_REG_84823_LED3_STRETCH_EN); 9663 } 9664 9665 static void bnx2x_848xx_specific_func(struct bnx2x_phy *phy, 9666 struct link_params *params, 9667 u32 action) 9668 { 9669 struct bnx2x *bp = params->bp; 9670 switch (action) { 9671 case PHY_INIT: 9672 if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) && 9673 (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) { 9674 /* Save spirom version */ 9675 bnx2x_save_848xx_spirom_version(phy, bp, params->port); 9676 } 9677 /* This phy uses the NIG latch mechanism since link indication 9678 * arrives through its LED4 and not via its LASI signal, so we 9679 * get steady signal instead of clear on read 9680 */ 9681 bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4, 9682 1 << NIG_LATCH_BC_ENABLE_MI_INT); 9683 9684 bnx2x_848xx_set_led(bp, phy); 9685 break; 9686 } 9687 } 9688 9689 static int bnx2x_848xx_cmn_config_init(struct bnx2x_phy *phy, 9690 struct link_params *params, 9691 struct link_vars *vars) 9692 { 9693 struct bnx2x *bp = params->bp; 9694 u16 autoneg_val, an_1000_val, an_10_100_val; 9695 9696 bnx2x_848xx_specific_func(phy, params, PHY_INIT); 9697 bnx2x_cl45_write(bp, phy, 9698 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0000); 9699 9700 /* set 1000 speed advertisement */ 9701 bnx2x_cl45_read(bp, phy, 9702 MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL, 9703 &an_1000_val); 9704 9705 bnx2x_ext_phy_set_pause(params, phy, vars); 9706 bnx2x_cl45_read(bp, phy, 9707 MDIO_AN_DEVAD, 9708 MDIO_AN_REG_8481_LEGACY_AN_ADV, 9709 &an_10_100_val); 9710 bnx2x_cl45_read(bp, phy, 9711 MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_MII_CTRL, 9712 &autoneg_val); 9713 /* Disable forced speed */ 9714 autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13)); 9715 an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8)); 9716 9717 if (((phy->req_line_speed == SPEED_AUTO_NEG) && 9718 (phy->speed_cap_mask & 9719 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) || 9720 (phy->req_line_speed == SPEED_1000)) { 9721 an_1000_val |= (1<<8); 9722 autoneg_val |= (1<<9 | 1<<12); 9723 if (phy->req_duplex == DUPLEX_FULL) 9724 an_1000_val |= (1<<9); 9725 DP(NETIF_MSG_LINK, "Advertising 1G\n"); 9726 } else 9727 an_1000_val &= ~((1<<8) | (1<<9)); 9728 9729 bnx2x_cl45_write(bp, phy, 9730 MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL, 9731 an_1000_val); 9732 9733 /* set 100 speed advertisement */ 9734 if ((phy->req_line_speed == SPEED_AUTO_NEG) && 9735 (phy->speed_cap_mask & 9736 (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL | 9737 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))) { 9738 an_10_100_val |= (1<<7); 9739 /* Enable autoneg and restart autoneg for legacy speeds */ 9740 autoneg_val |= (1<<9 | 1<<12); 9741 9742 if (phy->req_duplex == DUPLEX_FULL) 9743 an_10_100_val |= (1<<8); 9744 DP(NETIF_MSG_LINK, "Advertising 100M\n"); 9745 } 9746 /* set 10 speed advertisement */ 9747 if (((phy->req_line_speed == SPEED_AUTO_NEG) && 9748 (phy->speed_cap_mask & 9749 (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL | 9750 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) && 9751 (phy->supported & 9752 (SUPPORTED_10baseT_Half | 9753 SUPPORTED_10baseT_Full)))) { 9754 an_10_100_val |= (1<<5); 9755 autoneg_val |= (1<<9 | 1<<12); 9756 if (phy->req_duplex == DUPLEX_FULL) 9757 an_10_100_val |= (1<<6); 9758 DP(NETIF_MSG_LINK, "Advertising 10M\n"); 9759 } 9760 9761 /* Only 10/100 are allowed to work in FORCE mode */ 9762 if ((phy->req_line_speed == SPEED_100) && 9763 (phy->supported & 9764 (SUPPORTED_100baseT_Half | 9765 SUPPORTED_100baseT_Full))) { 9766 autoneg_val |= (1<<13); 9767 /* Enabled AUTO-MDIX when autoneg is disabled */ 9768 bnx2x_cl45_write(bp, phy, 9769 MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL, 9770 (1<<15 | 1<<9 | 7<<0)); 9771 /* The PHY needs this set even for forced link. */ 9772 an_10_100_val |= (1<<8) | (1<<7); 9773 DP(NETIF_MSG_LINK, "Setting 100M force\n"); 9774 } 9775 if ((phy->req_line_speed == SPEED_10) && 9776 (phy->supported & 9777 (SUPPORTED_10baseT_Half | 9778 SUPPORTED_10baseT_Full))) { 9779 /* Enabled AUTO-MDIX when autoneg is disabled */ 9780 bnx2x_cl45_write(bp, phy, 9781 MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL, 9782 (1<<15 | 1<<9 | 7<<0)); 9783 DP(NETIF_MSG_LINK, "Setting 10M force\n"); 9784 } 9785 9786 bnx2x_cl45_write(bp, phy, 9787 MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_AN_ADV, 9788 an_10_100_val); 9789 9790 if (phy->req_duplex == DUPLEX_FULL) 9791 autoneg_val |= (1<<8); 9792 9793 /* Always write this if this is not 84833/4. 9794 * For 84833/4, write it only when it's a forced speed. 9795 */ 9796 if (((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) && 9797 (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) || 9798 ((autoneg_val & (1<<12)) == 0)) 9799 bnx2x_cl45_write(bp, phy, 9800 MDIO_AN_DEVAD, 9801 MDIO_AN_REG_8481_LEGACY_MII_CTRL, autoneg_val); 9802 9803 if (((phy->req_line_speed == SPEED_AUTO_NEG) && 9804 (phy->speed_cap_mask & 9805 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) || 9806 (phy->req_line_speed == SPEED_10000)) { 9807 DP(NETIF_MSG_LINK, "Advertising 10G\n"); 9808 /* Restart autoneg for 10G*/ 9809 9810 bnx2x_cl45_read_or_write( 9811 bp, phy, 9812 MDIO_AN_DEVAD, 9813 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL, 9814 0x1000); 9815 bnx2x_cl45_write(bp, phy, 9816 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 9817 0x3200); 9818 } else 9819 bnx2x_cl45_write(bp, phy, 9820 MDIO_AN_DEVAD, 9821 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL, 9822 1); 9823 9824 return 0; 9825 } 9826 9827 static int bnx2x_8481_config_init(struct bnx2x_phy *phy, 9828 struct link_params *params, 9829 struct link_vars *vars) 9830 { 9831 struct bnx2x *bp = params->bp; 9832 /* Restore normal power mode*/ 9833 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 9834 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); 9835 9836 /* HW reset */ 9837 bnx2x_ext_phy_hw_reset(bp, params->port); 9838 bnx2x_wait_reset_complete(bp, phy, params); 9839 9840 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15); 9841 return bnx2x_848xx_cmn_config_init(phy, params, vars); 9842 } 9843 9844 #define PHY84833_CMDHDLR_WAIT 300 9845 #define PHY84833_CMDHDLR_MAX_ARGS 5 9846 static int bnx2x_84833_cmd_hdlr(struct bnx2x_phy *phy, 9847 struct link_params *params, u16 fw_cmd, 9848 u16 cmd_args[], int argc) 9849 { 9850 int idx; 9851 u16 val; 9852 struct bnx2x *bp = params->bp; 9853 /* Write CMD_OPEN_OVERRIDE to STATUS reg */ 9854 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, 9855 MDIO_84833_CMD_HDLR_STATUS, 9856 PHY84833_STATUS_CMD_OPEN_OVERRIDE); 9857 for (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) { 9858 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 9859 MDIO_84833_CMD_HDLR_STATUS, &val); 9860 if (val == PHY84833_STATUS_CMD_OPEN_FOR_CMDS) 9861 break; 9862 usleep_range(1000, 2000); 9863 } 9864 if (idx >= PHY84833_CMDHDLR_WAIT) { 9865 DP(NETIF_MSG_LINK, "FW cmd: FW not ready.\n"); 9866 return -EINVAL; 9867 } 9868 9869 /* Prepare argument(s) and issue command */ 9870 for (idx = 0; idx < argc; idx++) { 9871 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, 9872 MDIO_84833_CMD_HDLR_DATA1 + idx, 9873 cmd_args[idx]); 9874 } 9875 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, 9876 MDIO_84833_CMD_HDLR_COMMAND, fw_cmd); 9877 for (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) { 9878 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 9879 MDIO_84833_CMD_HDLR_STATUS, &val); 9880 if ((val == PHY84833_STATUS_CMD_COMPLETE_PASS) || 9881 (val == PHY84833_STATUS_CMD_COMPLETE_ERROR)) 9882 break; 9883 usleep_range(1000, 2000); 9884 } 9885 if ((idx >= PHY84833_CMDHDLR_WAIT) || 9886 (val == PHY84833_STATUS_CMD_COMPLETE_ERROR)) { 9887 DP(NETIF_MSG_LINK, "FW cmd failed.\n"); 9888 return -EINVAL; 9889 } 9890 /* Gather returning data */ 9891 for (idx = 0; idx < argc; idx++) { 9892 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 9893 MDIO_84833_CMD_HDLR_DATA1 + idx, 9894 &cmd_args[idx]); 9895 } 9896 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, 9897 MDIO_84833_CMD_HDLR_STATUS, 9898 PHY84833_STATUS_CMD_CLEAR_COMPLETE); 9899 return 0; 9900 } 9901 9902 static int bnx2x_84833_pair_swap_cfg(struct bnx2x_phy *phy, 9903 struct link_params *params, 9904 struct link_vars *vars) 9905 { 9906 u32 pair_swap; 9907 u16 data[PHY84833_CMDHDLR_MAX_ARGS]; 9908 int status; 9909 struct bnx2x *bp = params->bp; 9910 9911 /* Check for configuration. */ 9912 pair_swap = REG_RD(bp, params->shmem_base + 9913 offsetof(struct shmem_region, 9914 dev_info.port_hw_config[params->port].xgbt_phy_cfg)) & 9915 PORT_HW_CFG_RJ45_PAIR_SWAP_MASK; 9916 9917 if (pair_swap == 0) 9918 return 0; 9919 9920 /* Only the second argument is used for this command */ 9921 data[1] = (u16)pair_swap; 9922 9923 status = bnx2x_84833_cmd_hdlr(phy, params, 9924 PHY84833_CMD_SET_PAIR_SWAP, data, PHY84833_CMDHDLR_MAX_ARGS); 9925 if (status == 0) 9926 DP(NETIF_MSG_LINK, "Pairswap OK, val=0x%x\n", data[1]); 9927 9928 return status; 9929 } 9930 9931 static u8 bnx2x_84833_get_reset_gpios(struct bnx2x *bp, 9932 u32 shmem_base_path[], 9933 u32 chip_id) 9934 { 9935 u32 reset_pin[2]; 9936 u32 idx; 9937 u8 reset_gpios; 9938 if (CHIP_IS_E3(bp)) { 9939 /* Assume that these will be GPIOs, not EPIOs. */ 9940 for (idx = 0; idx < 2; idx++) { 9941 /* Map config param to register bit. */ 9942 reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] + 9943 offsetof(struct shmem_region, 9944 dev_info.port_hw_config[0].e3_cmn_pin_cfg)); 9945 reset_pin[idx] = (reset_pin[idx] & 9946 PORT_HW_CFG_E3_PHY_RESET_MASK) >> 9947 PORT_HW_CFG_E3_PHY_RESET_SHIFT; 9948 reset_pin[idx] -= PIN_CFG_GPIO0_P0; 9949 reset_pin[idx] = (1 << reset_pin[idx]); 9950 } 9951 reset_gpios = (u8)(reset_pin[0] | reset_pin[1]); 9952 } else { 9953 /* E2, look from diff place of shmem. */ 9954 for (idx = 0; idx < 2; idx++) { 9955 reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] + 9956 offsetof(struct shmem_region, 9957 dev_info.port_hw_config[0].default_cfg)); 9958 reset_pin[idx] &= PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK; 9959 reset_pin[idx] -= PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0; 9960 reset_pin[idx] >>= PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT; 9961 reset_pin[idx] = (1 << reset_pin[idx]); 9962 } 9963 reset_gpios = (u8)(reset_pin[0] | reset_pin[1]); 9964 } 9965 9966 return reset_gpios; 9967 } 9968 9969 static int bnx2x_84833_hw_reset_phy(struct bnx2x_phy *phy, 9970 struct link_params *params) 9971 { 9972 struct bnx2x *bp = params->bp; 9973 u8 reset_gpios; 9974 u32 other_shmem_base_addr = REG_RD(bp, params->shmem2_base + 9975 offsetof(struct shmem2_region, 9976 other_shmem_base_addr)); 9977 9978 u32 shmem_base_path[2]; 9979 9980 /* Work around for 84833 LED failure inside RESET status */ 9981 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, 9982 MDIO_AN_REG_8481_LEGACY_MII_CTRL, 9983 MDIO_AN_REG_8481_MII_CTRL_FORCE_1G); 9984 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, 9985 MDIO_AN_REG_8481_1G_100T_EXT_CTRL, 9986 MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF); 9987 9988 shmem_base_path[0] = params->shmem_base; 9989 shmem_base_path[1] = other_shmem_base_addr; 9990 9991 reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path, 9992 params->chip_id); 9993 9994 bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW); 9995 udelay(10); 9996 DP(NETIF_MSG_LINK, "84833 hw reset on pin values 0x%x\n", 9997 reset_gpios); 9998 9999 return 0; 10000 } 10001 10002 static int bnx2x_8483x_disable_eee(struct bnx2x_phy *phy, 10003 struct link_params *params, 10004 struct link_vars *vars) 10005 { 10006 int rc; 10007 struct bnx2x *bp = params->bp; 10008 u16 cmd_args = 0; 10009 10010 DP(NETIF_MSG_LINK, "Don't Advertise 10GBase-T EEE\n"); 10011 10012 /* Prevent Phy from working in EEE and advertising it */ 10013 rc = bnx2x_84833_cmd_hdlr(phy, params, 10014 PHY84833_CMD_SET_EEE_MODE, &cmd_args, 1); 10015 if (rc) { 10016 DP(NETIF_MSG_LINK, "EEE disable failed.\n"); 10017 return rc; 10018 } 10019 10020 return bnx2x_eee_disable(phy, params, vars); 10021 } 10022 10023 static int bnx2x_8483x_enable_eee(struct bnx2x_phy *phy, 10024 struct link_params *params, 10025 struct link_vars *vars) 10026 { 10027 int rc; 10028 struct bnx2x *bp = params->bp; 10029 u16 cmd_args = 1; 10030 10031 rc = bnx2x_84833_cmd_hdlr(phy, params, 10032 PHY84833_CMD_SET_EEE_MODE, &cmd_args, 1); 10033 if (rc) { 10034 DP(NETIF_MSG_LINK, "EEE enable failed.\n"); 10035 return rc; 10036 } 10037 10038 return bnx2x_eee_advertise(phy, params, vars, SHMEM_EEE_10G_ADV); 10039 } 10040 10041 #define PHY84833_CONSTANT_LATENCY 1193 10042 static int bnx2x_848x3_config_init(struct bnx2x_phy *phy, 10043 struct link_params *params, 10044 struct link_vars *vars) 10045 { 10046 struct bnx2x *bp = params->bp; 10047 u8 port, initialize = 1; 10048 u16 val; 10049 u32 actual_phy_selection; 10050 u16 cmd_args[PHY84833_CMDHDLR_MAX_ARGS]; 10051 int rc = 0; 10052 10053 usleep_range(1000, 2000); 10054 10055 if (!(CHIP_IS_E1x(bp))) 10056 port = BP_PATH(bp); 10057 else 10058 port = params->port; 10059 10060 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) { 10061 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3, 10062 MISC_REGISTERS_GPIO_OUTPUT_HIGH, 10063 port); 10064 } else { 10065 /* MDIO reset */ 10066 bnx2x_cl45_write(bp, phy, 10067 MDIO_PMA_DEVAD, 10068 MDIO_PMA_REG_CTRL, 0x8000); 10069 } 10070 10071 bnx2x_wait_reset_complete(bp, phy, params); 10072 10073 /* Wait for GPHY to come out of reset */ 10074 msleep(50); 10075 if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) && 10076 (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) { 10077 /* BCM84823 requires that XGXS links up first @ 10G for normal 10078 * behavior. 10079 */ 10080 u16 temp; 10081 temp = vars->line_speed; 10082 vars->line_speed = SPEED_10000; 10083 bnx2x_set_autoneg(¶ms->phy[INT_PHY], params, vars, 0); 10084 bnx2x_program_serdes(¶ms->phy[INT_PHY], params, vars); 10085 vars->line_speed = temp; 10086 } 10087 10088 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 10089 MDIO_CTL_REG_84823_MEDIA, &val); 10090 val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK | 10091 MDIO_CTL_REG_84823_MEDIA_LINE_MASK | 10092 MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN | 10093 MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK | 10094 MDIO_CTL_REG_84823_MEDIA_FIBER_1G); 10095 10096 if (CHIP_IS_E3(bp)) { 10097 val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK | 10098 MDIO_CTL_REG_84823_MEDIA_LINE_MASK); 10099 } else { 10100 val |= (MDIO_CTL_REG_84823_CTRL_MAC_XFI | 10101 MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L); 10102 } 10103 10104 actual_phy_selection = bnx2x_phy_selection(params); 10105 10106 switch (actual_phy_selection) { 10107 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT: 10108 /* Do nothing. Essentially this is like the priority copper */ 10109 break; 10110 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY: 10111 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER; 10112 break; 10113 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY: 10114 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER; 10115 break; 10116 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY: 10117 /* Do nothing here. The first PHY won't be initialized at all */ 10118 break; 10119 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY: 10120 val |= MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN; 10121 initialize = 0; 10122 break; 10123 } 10124 if (params->phy[EXT_PHY2].req_line_speed == SPEED_1000) 10125 val |= MDIO_CTL_REG_84823_MEDIA_FIBER_1G; 10126 10127 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, 10128 MDIO_CTL_REG_84823_MEDIA, val); 10129 DP(NETIF_MSG_LINK, "Multi_phy config = 0x%x, Media control = 0x%x\n", 10130 params->multi_phy_config, val); 10131 10132 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) || 10133 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) { 10134 bnx2x_84833_pair_swap_cfg(phy, params, vars); 10135 10136 /* Keep AutogrEEEn disabled. */ 10137 cmd_args[0] = 0x0; 10138 cmd_args[1] = 0x0; 10139 cmd_args[2] = PHY84833_CONSTANT_LATENCY + 1; 10140 cmd_args[3] = PHY84833_CONSTANT_LATENCY; 10141 rc = bnx2x_84833_cmd_hdlr(phy, params, 10142 PHY84833_CMD_SET_EEE_MODE, cmd_args, 10143 PHY84833_CMDHDLR_MAX_ARGS); 10144 if (rc) 10145 DP(NETIF_MSG_LINK, "Cfg AutogrEEEn failed.\n"); 10146 } 10147 if (initialize) 10148 rc = bnx2x_848xx_cmn_config_init(phy, params, vars); 10149 else 10150 bnx2x_save_848xx_spirom_version(phy, bp, params->port); 10151 /* 84833 PHY has a better feature and doesn't need to support this. */ 10152 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) { 10153 u32 cms_enable = REG_RD(bp, params->shmem_base + 10154 offsetof(struct shmem_region, 10155 dev_info.port_hw_config[params->port].default_cfg)) & 10156 PORT_HW_CFG_ENABLE_CMS_MASK; 10157 10158 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 10159 MDIO_CTL_REG_84823_USER_CTRL_REG, &val); 10160 if (cms_enable) 10161 val |= MDIO_CTL_REG_84823_USER_CTRL_CMS; 10162 else 10163 val &= ~MDIO_CTL_REG_84823_USER_CTRL_CMS; 10164 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, 10165 MDIO_CTL_REG_84823_USER_CTRL_REG, val); 10166 } 10167 10168 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 10169 MDIO_84833_TOP_CFG_FW_REV, &val); 10170 10171 /* Configure EEE support */ 10172 if ((val >= MDIO_84833_TOP_CFG_FW_EEE) && 10173 (val != MDIO_84833_TOP_CFG_FW_NO_EEE) && 10174 bnx2x_eee_has_cap(params)) { 10175 rc = bnx2x_eee_initial_config(params, vars, SHMEM_EEE_10G_ADV); 10176 if (rc) { 10177 DP(NETIF_MSG_LINK, "Failed to configure EEE timers\n"); 10178 bnx2x_8483x_disable_eee(phy, params, vars); 10179 return rc; 10180 } 10181 10182 if ((phy->req_duplex == DUPLEX_FULL) && 10183 (params->eee_mode & EEE_MODE_ADV_LPI) && 10184 (bnx2x_eee_calc_timer(params) || 10185 !(params->eee_mode & EEE_MODE_ENABLE_LPI))) 10186 rc = bnx2x_8483x_enable_eee(phy, params, vars); 10187 else 10188 rc = bnx2x_8483x_disable_eee(phy, params, vars); 10189 if (rc) { 10190 DP(NETIF_MSG_LINK, "Failed to set EEE advertisement\n"); 10191 return rc; 10192 } 10193 } else { 10194 vars->eee_status &= ~SHMEM_EEE_SUPPORTED_MASK; 10195 } 10196 10197 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) || 10198 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) { 10199 /* Bring PHY out of super isolate mode as the final step. */ 10200 bnx2x_cl45_read_and_write(bp, phy, 10201 MDIO_CTL_DEVAD, 10202 MDIO_84833_TOP_CFG_XGPHY_STRAP1, 10203 (u16)~MDIO_84833_SUPER_ISOLATE); 10204 } 10205 return rc; 10206 } 10207 10208 static u8 bnx2x_848xx_read_status(struct bnx2x_phy *phy, 10209 struct link_params *params, 10210 struct link_vars *vars) 10211 { 10212 struct bnx2x *bp = params->bp; 10213 u16 val, val1, val2; 10214 u8 link_up = 0; 10215 10216 10217 /* Check 10G-BaseT link status */ 10218 /* Check PMD signal ok */ 10219 bnx2x_cl45_read(bp, phy, 10220 MDIO_AN_DEVAD, 0xFFFA, &val1); 10221 bnx2x_cl45_read(bp, phy, 10222 MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_PMD_SIGNAL, 10223 &val2); 10224 DP(NETIF_MSG_LINK, "BCM848xx: PMD_SIGNAL 1.a811 = 0x%x\n", val2); 10225 10226 /* Check link 10G */ 10227 if (val2 & (1<<11)) { 10228 vars->line_speed = SPEED_10000; 10229 vars->duplex = DUPLEX_FULL; 10230 link_up = 1; 10231 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars); 10232 } else { /* Check Legacy speed link */ 10233 u16 legacy_status, legacy_speed; 10234 10235 /* Enable expansion register 0x42 (Operation mode status) */ 10236 bnx2x_cl45_write(bp, phy, 10237 MDIO_AN_DEVAD, 10238 MDIO_AN_REG_8481_EXPANSION_REG_ACCESS, 0xf42); 10239 10240 /* Get legacy speed operation status */ 10241 bnx2x_cl45_read(bp, phy, 10242 MDIO_AN_DEVAD, 10243 MDIO_AN_REG_8481_EXPANSION_REG_RD_RW, 10244 &legacy_status); 10245 10246 DP(NETIF_MSG_LINK, "Legacy speed status = 0x%x\n", 10247 legacy_status); 10248 link_up = ((legacy_status & (1<<11)) == (1<<11)); 10249 legacy_speed = (legacy_status & (3<<9)); 10250 if (legacy_speed == (0<<9)) 10251 vars->line_speed = SPEED_10; 10252 else if (legacy_speed == (1<<9)) 10253 vars->line_speed = SPEED_100; 10254 else if (legacy_speed == (2<<9)) 10255 vars->line_speed = SPEED_1000; 10256 else { /* Should not happen: Treat as link down */ 10257 vars->line_speed = 0; 10258 link_up = 0; 10259 } 10260 10261 if (link_up) { 10262 if (legacy_status & (1<<8)) 10263 vars->duplex = DUPLEX_FULL; 10264 else 10265 vars->duplex = DUPLEX_HALF; 10266 10267 DP(NETIF_MSG_LINK, 10268 "Link is up in %dMbps, is_duplex_full= %d\n", 10269 vars->line_speed, 10270 (vars->duplex == DUPLEX_FULL)); 10271 /* Check legacy speed AN resolution */ 10272 bnx2x_cl45_read(bp, phy, 10273 MDIO_AN_DEVAD, 10274 MDIO_AN_REG_8481_LEGACY_MII_STATUS, 10275 &val); 10276 if (val & (1<<5)) 10277 vars->link_status |= 10278 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; 10279 bnx2x_cl45_read(bp, phy, 10280 MDIO_AN_DEVAD, 10281 MDIO_AN_REG_8481_LEGACY_AN_EXPANSION, 10282 &val); 10283 if ((val & (1<<0)) == 0) 10284 vars->link_status |= 10285 LINK_STATUS_PARALLEL_DETECTION_USED; 10286 } 10287 } 10288 if (link_up) { 10289 DP(NETIF_MSG_LINK, "BCM848x3: link speed is %d\n", 10290 vars->line_speed); 10291 bnx2x_ext_phy_resolve_fc(phy, params, vars); 10292 10293 /* Read LP advertised speeds */ 10294 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, 10295 MDIO_AN_REG_CL37_FC_LP, &val); 10296 if (val & (1<<5)) 10297 vars->link_status |= 10298 LINK_STATUS_LINK_PARTNER_10THD_CAPABLE; 10299 if (val & (1<<6)) 10300 vars->link_status |= 10301 LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE; 10302 if (val & (1<<7)) 10303 vars->link_status |= 10304 LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE; 10305 if (val & (1<<8)) 10306 vars->link_status |= 10307 LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE; 10308 if (val & (1<<9)) 10309 vars->link_status |= 10310 LINK_STATUS_LINK_PARTNER_100T4_CAPABLE; 10311 10312 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, 10313 MDIO_AN_REG_1000T_STATUS, &val); 10314 10315 if (val & (1<<10)) 10316 vars->link_status |= 10317 LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE; 10318 if (val & (1<<11)) 10319 vars->link_status |= 10320 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; 10321 10322 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, 10323 MDIO_AN_REG_MASTER_STATUS, &val); 10324 10325 if (val & (1<<11)) 10326 vars->link_status |= 10327 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; 10328 10329 /* Determine if EEE was negotiated */ 10330 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) || 10331 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) 10332 bnx2x_eee_an_resolve(phy, params, vars); 10333 } 10334 10335 return link_up; 10336 } 10337 10338 static int bnx2x_848xx_format_ver(u32 raw_ver, u8 *str, u16 *len) 10339 { 10340 int status = 0; 10341 u32 spirom_ver; 10342 spirom_ver = ((raw_ver & 0xF80) >> 7) << 16 | (raw_ver & 0x7F); 10343 status = bnx2x_format_ver(spirom_ver, str, len); 10344 return status; 10345 } 10346 10347 static void bnx2x_8481_hw_reset(struct bnx2x_phy *phy, 10348 struct link_params *params) 10349 { 10350 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1, 10351 MISC_REGISTERS_GPIO_OUTPUT_LOW, 0); 10352 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1, 10353 MISC_REGISTERS_GPIO_OUTPUT_LOW, 1); 10354 } 10355 10356 static void bnx2x_8481_link_reset(struct bnx2x_phy *phy, 10357 struct link_params *params) 10358 { 10359 bnx2x_cl45_write(params->bp, phy, 10360 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000); 10361 bnx2x_cl45_write(params->bp, phy, 10362 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1); 10363 } 10364 10365 static void bnx2x_848x3_link_reset(struct bnx2x_phy *phy, 10366 struct link_params *params) 10367 { 10368 struct bnx2x *bp = params->bp; 10369 u8 port; 10370 u16 val16; 10371 10372 if (!(CHIP_IS_E1x(bp))) 10373 port = BP_PATH(bp); 10374 else 10375 port = params->port; 10376 10377 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) { 10378 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3, 10379 MISC_REGISTERS_GPIO_OUTPUT_LOW, 10380 port); 10381 } else { 10382 bnx2x_cl45_read(bp, phy, 10383 MDIO_CTL_DEVAD, 10384 MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val16); 10385 val16 |= MDIO_84833_SUPER_ISOLATE; 10386 bnx2x_cl45_write(bp, phy, 10387 MDIO_CTL_DEVAD, 10388 MDIO_84833_TOP_CFG_XGPHY_STRAP1, val16); 10389 } 10390 } 10391 10392 static void bnx2x_848xx_set_link_led(struct bnx2x_phy *phy, 10393 struct link_params *params, u8 mode) 10394 { 10395 struct bnx2x *bp = params->bp; 10396 u16 val; 10397 u8 port; 10398 10399 if (!(CHIP_IS_E1x(bp))) 10400 port = BP_PATH(bp); 10401 else 10402 port = params->port; 10403 10404 switch (mode) { 10405 case LED_MODE_OFF: 10406 10407 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OFF\n", port); 10408 10409 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) == 10410 SHARED_HW_CFG_LED_EXTPHY1) { 10411 10412 /* Set LED masks */ 10413 bnx2x_cl45_write(bp, phy, 10414 MDIO_PMA_DEVAD, 10415 MDIO_PMA_REG_8481_LED1_MASK, 10416 0x0); 10417 10418 bnx2x_cl45_write(bp, phy, 10419 MDIO_PMA_DEVAD, 10420 MDIO_PMA_REG_8481_LED2_MASK, 10421 0x0); 10422 10423 bnx2x_cl45_write(bp, phy, 10424 MDIO_PMA_DEVAD, 10425 MDIO_PMA_REG_8481_LED3_MASK, 10426 0x0); 10427 10428 bnx2x_cl45_write(bp, phy, 10429 MDIO_PMA_DEVAD, 10430 MDIO_PMA_REG_8481_LED5_MASK, 10431 0x0); 10432 10433 } else { 10434 bnx2x_cl45_write(bp, phy, 10435 MDIO_PMA_DEVAD, 10436 MDIO_PMA_REG_8481_LED1_MASK, 10437 0x0); 10438 } 10439 break; 10440 case LED_MODE_FRONT_PANEL_OFF: 10441 10442 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE FRONT PANEL OFF\n", 10443 port); 10444 10445 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) == 10446 SHARED_HW_CFG_LED_EXTPHY1) { 10447 10448 /* Set LED masks */ 10449 bnx2x_cl45_write(bp, phy, 10450 MDIO_PMA_DEVAD, 10451 MDIO_PMA_REG_8481_LED1_MASK, 10452 0x0); 10453 10454 bnx2x_cl45_write(bp, phy, 10455 MDIO_PMA_DEVAD, 10456 MDIO_PMA_REG_8481_LED2_MASK, 10457 0x0); 10458 10459 bnx2x_cl45_write(bp, phy, 10460 MDIO_PMA_DEVAD, 10461 MDIO_PMA_REG_8481_LED3_MASK, 10462 0x0); 10463 10464 bnx2x_cl45_write(bp, phy, 10465 MDIO_PMA_DEVAD, 10466 MDIO_PMA_REG_8481_LED5_MASK, 10467 0x20); 10468 10469 } else { 10470 bnx2x_cl45_write(bp, phy, 10471 MDIO_PMA_DEVAD, 10472 MDIO_PMA_REG_8481_LED1_MASK, 10473 0x0); 10474 if (phy->type == 10475 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) { 10476 /* Disable MI_INT interrupt before setting LED4 10477 * source to constant off. 10478 */ 10479 if (REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + 10480 params->port*4) & 10481 NIG_MASK_MI_INT) { 10482 params->link_flags |= 10483 LINK_FLAGS_INT_DISABLED; 10484 10485 bnx2x_bits_dis( 10486 bp, 10487 NIG_REG_MASK_INTERRUPT_PORT0 + 10488 params->port*4, 10489 NIG_MASK_MI_INT); 10490 } 10491 bnx2x_cl45_write(bp, phy, 10492 MDIO_PMA_DEVAD, 10493 MDIO_PMA_REG_8481_SIGNAL_MASK, 10494 0x0); 10495 } 10496 } 10497 break; 10498 case LED_MODE_ON: 10499 10500 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE ON\n", port); 10501 10502 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) == 10503 SHARED_HW_CFG_LED_EXTPHY1) { 10504 /* Set control reg */ 10505 bnx2x_cl45_read(bp, phy, 10506 MDIO_PMA_DEVAD, 10507 MDIO_PMA_REG_8481_LINK_SIGNAL, 10508 &val); 10509 val &= 0x8000; 10510 val |= 0x2492; 10511 10512 bnx2x_cl45_write(bp, phy, 10513 MDIO_PMA_DEVAD, 10514 MDIO_PMA_REG_8481_LINK_SIGNAL, 10515 val); 10516 10517 /* Set LED masks */ 10518 bnx2x_cl45_write(bp, phy, 10519 MDIO_PMA_DEVAD, 10520 MDIO_PMA_REG_8481_LED1_MASK, 10521 0x0); 10522 10523 bnx2x_cl45_write(bp, phy, 10524 MDIO_PMA_DEVAD, 10525 MDIO_PMA_REG_8481_LED2_MASK, 10526 0x20); 10527 10528 bnx2x_cl45_write(bp, phy, 10529 MDIO_PMA_DEVAD, 10530 MDIO_PMA_REG_8481_LED3_MASK, 10531 0x20); 10532 10533 bnx2x_cl45_write(bp, phy, 10534 MDIO_PMA_DEVAD, 10535 MDIO_PMA_REG_8481_LED5_MASK, 10536 0x0); 10537 } else { 10538 bnx2x_cl45_write(bp, phy, 10539 MDIO_PMA_DEVAD, 10540 MDIO_PMA_REG_8481_LED1_MASK, 10541 0x20); 10542 if (phy->type == 10543 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) { 10544 /* Disable MI_INT interrupt before setting LED4 10545 * source to constant on. 10546 */ 10547 if (REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + 10548 params->port*4) & 10549 NIG_MASK_MI_INT) { 10550 params->link_flags |= 10551 LINK_FLAGS_INT_DISABLED; 10552 10553 bnx2x_bits_dis( 10554 bp, 10555 NIG_REG_MASK_INTERRUPT_PORT0 + 10556 params->port*4, 10557 NIG_MASK_MI_INT); 10558 } 10559 bnx2x_cl45_write(bp, phy, 10560 MDIO_PMA_DEVAD, 10561 MDIO_PMA_REG_8481_SIGNAL_MASK, 10562 0x20); 10563 } 10564 } 10565 break; 10566 10567 case LED_MODE_OPER: 10568 10569 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OPER\n", port); 10570 10571 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) == 10572 SHARED_HW_CFG_LED_EXTPHY1) { 10573 10574 /* Set control reg */ 10575 bnx2x_cl45_read(bp, phy, 10576 MDIO_PMA_DEVAD, 10577 MDIO_PMA_REG_8481_LINK_SIGNAL, 10578 &val); 10579 10580 if (!((val & 10581 MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK) 10582 >> MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT)) { 10583 DP(NETIF_MSG_LINK, "Setting LINK_SIGNAL\n"); 10584 bnx2x_cl45_write(bp, phy, 10585 MDIO_PMA_DEVAD, 10586 MDIO_PMA_REG_8481_LINK_SIGNAL, 10587 0xa492); 10588 } 10589 10590 /* Set LED masks */ 10591 bnx2x_cl45_write(bp, phy, 10592 MDIO_PMA_DEVAD, 10593 MDIO_PMA_REG_8481_LED1_MASK, 10594 0x10); 10595 10596 bnx2x_cl45_write(bp, phy, 10597 MDIO_PMA_DEVAD, 10598 MDIO_PMA_REG_8481_LED2_MASK, 10599 0x80); 10600 10601 bnx2x_cl45_write(bp, phy, 10602 MDIO_PMA_DEVAD, 10603 MDIO_PMA_REG_8481_LED3_MASK, 10604 0x98); 10605 10606 bnx2x_cl45_write(bp, phy, 10607 MDIO_PMA_DEVAD, 10608 MDIO_PMA_REG_8481_LED5_MASK, 10609 0x40); 10610 10611 } else { 10612 bnx2x_cl45_write(bp, phy, 10613 MDIO_PMA_DEVAD, 10614 MDIO_PMA_REG_8481_LED1_MASK, 10615 0x80); 10616 10617 /* Tell LED3 to blink on source */ 10618 bnx2x_cl45_read(bp, phy, 10619 MDIO_PMA_DEVAD, 10620 MDIO_PMA_REG_8481_LINK_SIGNAL, 10621 &val); 10622 val &= ~(7<<6); 10623 val |= (1<<6); /* A83B[8:6]= 1 */ 10624 bnx2x_cl45_write(bp, phy, 10625 MDIO_PMA_DEVAD, 10626 MDIO_PMA_REG_8481_LINK_SIGNAL, 10627 val); 10628 if (phy->type == 10629 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) { 10630 /* Restore LED4 source to external link, 10631 * and re-enable interrupts. 10632 */ 10633 bnx2x_cl45_write(bp, phy, 10634 MDIO_PMA_DEVAD, 10635 MDIO_PMA_REG_8481_SIGNAL_MASK, 10636 0x40); 10637 if (params->link_flags & 10638 LINK_FLAGS_INT_DISABLED) { 10639 bnx2x_link_int_enable(params); 10640 params->link_flags &= 10641 ~LINK_FLAGS_INT_DISABLED; 10642 } 10643 } 10644 } 10645 break; 10646 } 10647 10648 /* This is a workaround for E3+84833 until autoneg 10649 * restart is fixed in f/w 10650 */ 10651 if (CHIP_IS_E3(bp)) { 10652 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 10653 MDIO_WC_REG_GP2_STATUS_GP_2_1, &val); 10654 } 10655 } 10656 10657 /******************************************************************/ 10658 /* 54618SE PHY SECTION */ 10659 /******************************************************************/ 10660 static void bnx2x_54618se_specific_func(struct bnx2x_phy *phy, 10661 struct link_params *params, 10662 u32 action) 10663 { 10664 struct bnx2x *bp = params->bp; 10665 u16 temp; 10666 switch (action) { 10667 case PHY_INIT: 10668 /* Configure LED4: set to INTR (0x6). */ 10669 /* Accessing shadow register 0xe. */ 10670 bnx2x_cl22_write(bp, phy, 10671 MDIO_REG_GPHY_SHADOW, 10672 MDIO_REG_GPHY_SHADOW_LED_SEL2); 10673 bnx2x_cl22_read(bp, phy, 10674 MDIO_REG_GPHY_SHADOW, 10675 &temp); 10676 temp &= ~(0xf << 4); 10677 temp |= (0x6 << 4); 10678 bnx2x_cl22_write(bp, phy, 10679 MDIO_REG_GPHY_SHADOW, 10680 MDIO_REG_GPHY_SHADOW_WR_ENA | temp); 10681 /* Configure INTR based on link status change. */ 10682 bnx2x_cl22_write(bp, phy, 10683 MDIO_REG_INTR_MASK, 10684 ~MDIO_REG_INTR_MASK_LINK_STATUS); 10685 break; 10686 } 10687 } 10688 10689 static int bnx2x_54618se_config_init(struct bnx2x_phy *phy, 10690 struct link_params *params, 10691 struct link_vars *vars) 10692 { 10693 struct bnx2x *bp = params->bp; 10694 u8 port; 10695 u16 autoneg_val, an_1000_val, an_10_100_val, fc_val, temp; 10696 u32 cfg_pin; 10697 10698 DP(NETIF_MSG_LINK, "54618SE cfg init\n"); 10699 usleep_range(1000, 2000); 10700 10701 /* This works with E3 only, no need to check the chip 10702 * before determining the port. 10703 */ 10704 port = params->port; 10705 10706 cfg_pin = (REG_RD(bp, params->shmem_base + 10707 offsetof(struct shmem_region, 10708 dev_info.port_hw_config[port].e3_cmn_pin_cfg)) & 10709 PORT_HW_CFG_E3_PHY_RESET_MASK) >> 10710 PORT_HW_CFG_E3_PHY_RESET_SHIFT; 10711 10712 /* Drive pin high to bring the GPHY out of reset. */ 10713 bnx2x_set_cfg_pin(bp, cfg_pin, 1); 10714 10715 /* wait for GPHY to reset */ 10716 msleep(50); 10717 10718 /* reset phy */ 10719 bnx2x_cl22_write(bp, phy, 10720 MDIO_PMA_REG_CTRL, 0x8000); 10721 bnx2x_wait_reset_complete(bp, phy, params); 10722 10723 /* Wait for GPHY to reset */ 10724 msleep(50); 10725 10726 10727 bnx2x_54618se_specific_func(phy, params, PHY_INIT); 10728 /* Flip the signal detect polarity (set 0x1c.0x1e[8]). */ 10729 bnx2x_cl22_write(bp, phy, 10730 MDIO_REG_GPHY_SHADOW, 10731 MDIO_REG_GPHY_SHADOW_AUTO_DET_MED); 10732 bnx2x_cl22_read(bp, phy, 10733 MDIO_REG_GPHY_SHADOW, 10734 &temp); 10735 temp |= MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD; 10736 bnx2x_cl22_write(bp, phy, 10737 MDIO_REG_GPHY_SHADOW, 10738 MDIO_REG_GPHY_SHADOW_WR_ENA | temp); 10739 10740 /* Set up fc */ 10741 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */ 10742 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); 10743 fc_val = 0; 10744 if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) == 10745 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) 10746 fc_val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC; 10747 10748 if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) == 10749 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) 10750 fc_val |= MDIO_AN_REG_ADV_PAUSE_PAUSE; 10751 10752 /* Read all advertisement */ 10753 bnx2x_cl22_read(bp, phy, 10754 0x09, 10755 &an_1000_val); 10756 10757 bnx2x_cl22_read(bp, phy, 10758 0x04, 10759 &an_10_100_val); 10760 10761 bnx2x_cl22_read(bp, phy, 10762 MDIO_PMA_REG_CTRL, 10763 &autoneg_val); 10764 10765 /* Disable forced speed */ 10766 autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13)); 10767 an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8) | (1<<10) | 10768 (1<<11)); 10769 10770 if (((phy->req_line_speed == SPEED_AUTO_NEG) && 10771 (phy->speed_cap_mask & 10772 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) || 10773 (phy->req_line_speed == SPEED_1000)) { 10774 an_1000_val |= (1<<8); 10775 autoneg_val |= (1<<9 | 1<<12); 10776 if (phy->req_duplex == DUPLEX_FULL) 10777 an_1000_val |= (1<<9); 10778 DP(NETIF_MSG_LINK, "Advertising 1G\n"); 10779 } else 10780 an_1000_val &= ~((1<<8) | (1<<9)); 10781 10782 bnx2x_cl22_write(bp, phy, 10783 0x09, 10784 an_1000_val); 10785 bnx2x_cl22_read(bp, phy, 10786 0x09, 10787 &an_1000_val); 10788 10789 /* Set 100 speed advertisement */ 10790 if (((phy->req_line_speed == SPEED_AUTO_NEG) && 10791 (phy->speed_cap_mask & 10792 (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL | 10793 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)))) { 10794 an_10_100_val |= (1<<7); 10795 /* Enable autoneg and restart autoneg for legacy speeds */ 10796 autoneg_val |= (1<<9 | 1<<12); 10797 10798 if (phy->req_duplex == DUPLEX_FULL) 10799 an_10_100_val |= (1<<8); 10800 DP(NETIF_MSG_LINK, "Advertising 100M\n"); 10801 } 10802 10803 /* Set 10 speed advertisement */ 10804 if (((phy->req_line_speed == SPEED_AUTO_NEG) && 10805 (phy->speed_cap_mask & 10806 (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL | 10807 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)))) { 10808 an_10_100_val |= (1<<5); 10809 autoneg_val |= (1<<9 | 1<<12); 10810 if (phy->req_duplex == DUPLEX_FULL) 10811 an_10_100_val |= (1<<6); 10812 DP(NETIF_MSG_LINK, "Advertising 10M\n"); 10813 } 10814 10815 /* Only 10/100 are allowed to work in FORCE mode */ 10816 if (phy->req_line_speed == SPEED_100) { 10817 autoneg_val |= (1<<13); 10818 /* Enabled AUTO-MDIX when autoneg is disabled */ 10819 bnx2x_cl22_write(bp, phy, 10820 0x18, 10821 (1<<15 | 1<<9 | 7<<0)); 10822 DP(NETIF_MSG_LINK, "Setting 100M force\n"); 10823 } 10824 if (phy->req_line_speed == SPEED_10) { 10825 /* Enabled AUTO-MDIX when autoneg is disabled */ 10826 bnx2x_cl22_write(bp, phy, 10827 0x18, 10828 (1<<15 | 1<<9 | 7<<0)); 10829 DP(NETIF_MSG_LINK, "Setting 10M force\n"); 10830 } 10831 10832 if ((phy->flags & FLAGS_EEE) && bnx2x_eee_has_cap(params)) { 10833 int rc; 10834 10835 bnx2x_cl22_write(bp, phy, MDIO_REG_GPHY_EXP_ACCESS, 10836 MDIO_REG_GPHY_EXP_ACCESS_TOP | 10837 MDIO_REG_GPHY_EXP_TOP_2K_BUF); 10838 bnx2x_cl22_read(bp, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, &temp); 10839 temp &= 0xfffe; 10840 bnx2x_cl22_write(bp, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, temp); 10841 10842 rc = bnx2x_eee_initial_config(params, vars, SHMEM_EEE_1G_ADV); 10843 if (rc) { 10844 DP(NETIF_MSG_LINK, "Failed to configure EEE timers\n"); 10845 bnx2x_eee_disable(phy, params, vars); 10846 } else if ((params->eee_mode & EEE_MODE_ADV_LPI) && 10847 (phy->req_duplex == DUPLEX_FULL) && 10848 (bnx2x_eee_calc_timer(params) || 10849 !(params->eee_mode & EEE_MODE_ENABLE_LPI))) { 10850 /* Need to advertise EEE only when requested, 10851 * and either no LPI assertion was requested, 10852 * or it was requested and a valid timer was set. 10853 * Also notice full duplex is required for EEE. 10854 */ 10855 bnx2x_eee_advertise(phy, params, vars, 10856 SHMEM_EEE_1G_ADV); 10857 } else { 10858 DP(NETIF_MSG_LINK, "Don't Advertise 1GBase-T EEE\n"); 10859 bnx2x_eee_disable(phy, params, vars); 10860 } 10861 } else { 10862 vars->eee_status &= ~SHMEM_EEE_1G_ADV << 10863 SHMEM_EEE_SUPPORTED_SHIFT; 10864 10865 if (phy->flags & FLAGS_EEE) { 10866 /* Handle legacy auto-grEEEn */ 10867 if (params->feature_config_flags & 10868 FEATURE_CONFIG_AUTOGREEEN_ENABLED) { 10869 temp = 6; 10870 DP(NETIF_MSG_LINK, "Enabling Auto-GrEEEn\n"); 10871 } else { 10872 temp = 0; 10873 DP(NETIF_MSG_LINK, "Don't Adv. EEE\n"); 10874 } 10875 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, 10876 MDIO_AN_REG_EEE_ADV, temp); 10877 } 10878 } 10879 10880 bnx2x_cl22_write(bp, phy, 10881 0x04, 10882 an_10_100_val | fc_val); 10883 10884 if (phy->req_duplex == DUPLEX_FULL) 10885 autoneg_val |= (1<<8); 10886 10887 bnx2x_cl22_write(bp, phy, 10888 MDIO_PMA_REG_CTRL, autoneg_val); 10889 10890 return 0; 10891 } 10892 10893 10894 static void bnx2x_5461x_set_link_led(struct bnx2x_phy *phy, 10895 struct link_params *params, u8 mode) 10896 { 10897 struct bnx2x *bp = params->bp; 10898 u16 temp; 10899 10900 bnx2x_cl22_write(bp, phy, 10901 MDIO_REG_GPHY_SHADOW, 10902 MDIO_REG_GPHY_SHADOW_LED_SEL1); 10903 bnx2x_cl22_read(bp, phy, 10904 MDIO_REG_GPHY_SHADOW, 10905 &temp); 10906 temp &= 0xff00; 10907 10908 DP(NETIF_MSG_LINK, "54618x set link led (mode=%x)\n", mode); 10909 switch (mode) { 10910 case LED_MODE_FRONT_PANEL_OFF: 10911 case LED_MODE_OFF: 10912 temp |= 0x00ee; 10913 break; 10914 case LED_MODE_OPER: 10915 temp |= 0x0001; 10916 break; 10917 case LED_MODE_ON: 10918 temp |= 0x00ff; 10919 break; 10920 default: 10921 break; 10922 } 10923 bnx2x_cl22_write(bp, phy, 10924 MDIO_REG_GPHY_SHADOW, 10925 MDIO_REG_GPHY_SHADOW_WR_ENA | temp); 10926 return; 10927 } 10928 10929 10930 static void bnx2x_54618se_link_reset(struct bnx2x_phy *phy, 10931 struct link_params *params) 10932 { 10933 struct bnx2x *bp = params->bp; 10934 u32 cfg_pin; 10935 u8 port; 10936 10937 /* In case of no EPIO routed to reset the GPHY, put it 10938 * in low power mode. 10939 */ 10940 bnx2x_cl22_write(bp, phy, MDIO_PMA_REG_CTRL, 0x800); 10941 /* This works with E3 only, no need to check the chip 10942 * before determining the port. 10943 */ 10944 port = params->port; 10945 cfg_pin = (REG_RD(bp, params->shmem_base + 10946 offsetof(struct shmem_region, 10947 dev_info.port_hw_config[port].e3_cmn_pin_cfg)) & 10948 PORT_HW_CFG_E3_PHY_RESET_MASK) >> 10949 PORT_HW_CFG_E3_PHY_RESET_SHIFT; 10950 10951 /* Drive pin low to put GPHY in reset. */ 10952 bnx2x_set_cfg_pin(bp, cfg_pin, 0); 10953 } 10954 10955 static u8 bnx2x_54618se_read_status(struct bnx2x_phy *phy, 10956 struct link_params *params, 10957 struct link_vars *vars) 10958 { 10959 struct bnx2x *bp = params->bp; 10960 u16 val; 10961 u8 link_up = 0; 10962 u16 legacy_status, legacy_speed; 10963 10964 /* Get speed operation status */ 10965 bnx2x_cl22_read(bp, phy, 10966 MDIO_REG_GPHY_AUX_STATUS, 10967 &legacy_status); 10968 DP(NETIF_MSG_LINK, "54618SE read_status: 0x%x\n", legacy_status); 10969 10970 /* Read status to clear the PHY interrupt. */ 10971 bnx2x_cl22_read(bp, phy, 10972 MDIO_REG_INTR_STATUS, 10973 &val); 10974 10975 link_up = ((legacy_status & (1<<2)) == (1<<2)); 10976 10977 if (link_up) { 10978 legacy_speed = (legacy_status & (7<<8)); 10979 if (legacy_speed == (7<<8)) { 10980 vars->line_speed = SPEED_1000; 10981 vars->duplex = DUPLEX_FULL; 10982 } else if (legacy_speed == (6<<8)) { 10983 vars->line_speed = SPEED_1000; 10984 vars->duplex = DUPLEX_HALF; 10985 } else if (legacy_speed == (5<<8)) { 10986 vars->line_speed = SPEED_100; 10987 vars->duplex = DUPLEX_FULL; 10988 } 10989 /* Omitting 100Base-T4 for now */ 10990 else if (legacy_speed == (3<<8)) { 10991 vars->line_speed = SPEED_100; 10992 vars->duplex = DUPLEX_HALF; 10993 } else if (legacy_speed == (2<<8)) { 10994 vars->line_speed = SPEED_10; 10995 vars->duplex = DUPLEX_FULL; 10996 } else if (legacy_speed == (1<<8)) { 10997 vars->line_speed = SPEED_10; 10998 vars->duplex = DUPLEX_HALF; 10999 } else /* Should not happen */ 11000 vars->line_speed = 0; 11001 11002 DP(NETIF_MSG_LINK, 11003 "Link is up in %dMbps, is_duplex_full= %d\n", 11004 vars->line_speed, 11005 (vars->duplex == DUPLEX_FULL)); 11006 11007 /* Check legacy speed AN resolution */ 11008 bnx2x_cl22_read(bp, phy, 11009 0x01, 11010 &val); 11011 if (val & (1<<5)) 11012 vars->link_status |= 11013 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; 11014 bnx2x_cl22_read(bp, phy, 11015 0x06, 11016 &val); 11017 if ((val & (1<<0)) == 0) 11018 vars->link_status |= 11019 LINK_STATUS_PARALLEL_DETECTION_USED; 11020 11021 DP(NETIF_MSG_LINK, "BCM54618SE: link speed is %d\n", 11022 vars->line_speed); 11023 11024 bnx2x_ext_phy_resolve_fc(phy, params, vars); 11025 11026 if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) { 11027 /* Report LP advertised speeds */ 11028 bnx2x_cl22_read(bp, phy, 0x5, &val); 11029 11030 if (val & (1<<5)) 11031 vars->link_status |= 11032 LINK_STATUS_LINK_PARTNER_10THD_CAPABLE; 11033 if (val & (1<<6)) 11034 vars->link_status |= 11035 LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE; 11036 if (val & (1<<7)) 11037 vars->link_status |= 11038 LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE; 11039 if (val & (1<<8)) 11040 vars->link_status |= 11041 LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE; 11042 if (val & (1<<9)) 11043 vars->link_status |= 11044 LINK_STATUS_LINK_PARTNER_100T4_CAPABLE; 11045 11046 bnx2x_cl22_read(bp, phy, 0xa, &val); 11047 if (val & (1<<10)) 11048 vars->link_status |= 11049 LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE; 11050 if (val & (1<<11)) 11051 vars->link_status |= 11052 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; 11053 11054 if ((phy->flags & FLAGS_EEE) && 11055 bnx2x_eee_has_cap(params)) 11056 bnx2x_eee_an_resolve(phy, params, vars); 11057 } 11058 } 11059 return link_up; 11060 } 11061 11062 static void bnx2x_54618se_config_loopback(struct bnx2x_phy *phy, 11063 struct link_params *params) 11064 { 11065 struct bnx2x *bp = params->bp; 11066 u16 val; 11067 u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0; 11068 11069 DP(NETIF_MSG_LINK, "2PMA/PMD ext_phy_loopback: 54618se\n"); 11070 11071 /* Enable master/slave manual mmode and set to master */ 11072 /* mii write 9 [bits set 11 12] */ 11073 bnx2x_cl22_write(bp, phy, 0x09, 3<<11); 11074 11075 /* forced 1G and disable autoneg */ 11076 /* set val [mii read 0] */ 11077 /* set val [expr $val & [bits clear 6 12 13]] */ 11078 /* set val [expr $val | [bits set 6 8]] */ 11079 /* mii write 0 $val */ 11080 bnx2x_cl22_read(bp, phy, 0x00, &val); 11081 val &= ~((1<<6) | (1<<12) | (1<<13)); 11082 val |= (1<<6) | (1<<8); 11083 bnx2x_cl22_write(bp, phy, 0x00, val); 11084 11085 /* Set external loopback and Tx using 6dB coding */ 11086 /* mii write 0x18 7 */ 11087 /* set val [mii read 0x18] */ 11088 /* mii write 0x18 [expr $val | [bits set 10 15]] */ 11089 bnx2x_cl22_write(bp, phy, 0x18, 7); 11090 bnx2x_cl22_read(bp, phy, 0x18, &val); 11091 bnx2x_cl22_write(bp, phy, 0x18, val | (1<<10) | (1<<15)); 11092 11093 /* This register opens the gate for the UMAC despite its name */ 11094 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1); 11095 11096 /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame 11097 * length used by the MAC receive logic to check frames. 11098 */ 11099 REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710); 11100 } 11101 11102 /******************************************************************/ 11103 /* SFX7101 PHY SECTION */ 11104 /******************************************************************/ 11105 static void bnx2x_7101_config_loopback(struct bnx2x_phy *phy, 11106 struct link_params *params) 11107 { 11108 struct bnx2x *bp = params->bp; 11109 /* SFX7101_XGXS_TEST1 */ 11110 bnx2x_cl45_write(bp, phy, 11111 MDIO_XS_DEVAD, MDIO_XS_SFX7101_XGXS_TEST1, 0x100); 11112 } 11113 11114 static int bnx2x_7101_config_init(struct bnx2x_phy *phy, 11115 struct link_params *params, 11116 struct link_vars *vars) 11117 { 11118 u16 fw_ver1, fw_ver2, val; 11119 struct bnx2x *bp = params->bp; 11120 DP(NETIF_MSG_LINK, "Setting the SFX7101 LASI indication\n"); 11121 11122 /* Restore normal power mode*/ 11123 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 11124 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); 11125 /* HW reset */ 11126 bnx2x_ext_phy_hw_reset(bp, params->port); 11127 bnx2x_wait_reset_complete(bp, phy, params); 11128 11129 bnx2x_cl45_write(bp, phy, 11130 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x1); 11131 DP(NETIF_MSG_LINK, "Setting the SFX7101 LED to blink on traffic\n"); 11132 bnx2x_cl45_write(bp, phy, 11133 MDIO_PMA_DEVAD, MDIO_PMA_REG_7107_LED_CNTL, (1<<3)); 11134 11135 bnx2x_ext_phy_set_pause(params, phy, vars); 11136 /* Restart autoneg */ 11137 bnx2x_cl45_read(bp, phy, 11138 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, &val); 11139 val |= 0x200; 11140 bnx2x_cl45_write(bp, phy, 11141 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, val); 11142 11143 /* Save spirom version */ 11144 bnx2x_cl45_read(bp, phy, 11145 MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER1, &fw_ver1); 11146 11147 bnx2x_cl45_read(bp, phy, 11148 MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER2, &fw_ver2); 11149 bnx2x_save_spirom_version(bp, params->port, 11150 (u32)(fw_ver1<<16 | fw_ver2), phy->ver_addr); 11151 return 0; 11152 } 11153 11154 static u8 bnx2x_7101_read_status(struct bnx2x_phy *phy, 11155 struct link_params *params, 11156 struct link_vars *vars) 11157 { 11158 struct bnx2x *bp = params->bp; 11159 u8 link_up; 11160 u16 val1, val2; 11161 bnx2x_cl45_read(bp, phy, 11162 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2); 11163 bnx2x_cl45_read(bp, phy, 11164 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1); 11165 DP(NETIF_MSG_LINK, "10G-base-T LASI status 0x%x->0x%x\n", 11166 val2, val1); 11167 bnx2x_cl45_read(bp, phy, 11168 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2); 11169 bnx2x_cl45_read(bp, phy, 11170 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1); 11171 DP(NETIF_MSG_LINK, "10G-base-T PMA status 0x%x->0x%x\n", 11172 val2, val1); 11173 link_up = ((val1 & 4) == 4); 11174 /* If link is up print the AN outcome of the SFX7101 PHY */ 11175 if (link_up) { 11176 bnx2x_cl45_read(bp, phy, 11177 MDIO_AN_DEVAD, MDIO_AN_REG_MASTER_STATUS, 11178 &val2); 11179 vars->line_speed = SPEED_10000; 11180 vars->duplex = DUPLEX_FULL; 11181 DP(NETIF_MSG_LINK, "SFX7101 AN status 0x%x->Master=%x\n", 11182 val2, (val2 & (1<<14))); 11183 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars); 11184 bnx2x_ext_phy_resolve_fc(phy, params, vars); 11185 11186 /* Read LP advertised speeds */ 11187 if (val2 & (1<<11)) 11188 vars->link_status |= 11189 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; 11190 } 11191 return link_up; 11192 } 11193 11194 static int bnx2x_7101_format_ver(u32 spirom_ver, u8 *str, u16 *len) 11195 { 11196 if (*len < 5) 11197 return -EINVAL; 11198 str[0] = (spirom_ver & 0xFF); 11199 str[1] = (spirom_ver & 0xFF00) >> 8; 11200 str[2] = (spirom_ver & 0xFF0000) >> 16; 11201 str[3] = (spirom_ver & 0xFF000000) >> 24; 11202 str[4] = '\0'; 11203 *len -= 5; 11204 return 0; 11205 } 11206 11207 void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, struct bnx2x_phy *phy) 11208 { 11209 u16 val, cnt; 11210 11211 bnx2x_cl45_read(bp, phy, 11212 MDIO_PMA_DEVAD, 11213 MDIO_PMA_REG_7101_RESET, &val); 11214 11215 for (cnt = 0; cnt < 10; cnt++) { 11216 msleep(50); 11217 /* Writes a self-clearing reset */ 11218 bnx2x_cl45_write(bp, phy, 11219 MDIO_PMA_DEVAD, 11220 MDIO_PMA_REG_7101_RESET, 11221 (val | (1<<15))); 11222 /* Wait for clear */ 11223 bnx2x_cl45_read(bp, phy, 11224 MDIO_PMA_DEVAD, 11225 MDIO_PMA_REG_7101_RESET, &val); 11226 11227 if ((val & (1<<15)) == 0) 11228 break; 11229 } 11230 } 11231 11232 static void bnx2x_7101_hw_reset(struct bnx2x_phy *phy, 11233 struct link_params *params) { 11234 /* Low power mode is controlled by GPIO 2 */ 11235 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_2, 11236 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port); 11237 /* The PHY reset is controlled by GPIO 1 */ 11238 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1, 11239 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port); 11240 } 11241 11242 static void bnx2x_7101_set_link_led(struct bnx2x_phy *phy, 11243 struct link_params *params, u8 mode) 11244 { 11245 u16 val = 0; 11246 struct bnx2x *bp = params->bp; 11247 switch (mode) { 11248 case LED_MODE_FRONT_PANEL_OFF: 11249 case LED_MODE_OFF: 11250 val = 2; 11251 break; 11252 case LED_MODE_ON: 11253 val = 1; 11254 break; 11255 case LED_MODE_OPER: 11256 val = 0; 11257 break; 11258 } 11259 bnx2x_cl45_write(bp, phy, 11260 MDIO_PMA_DEVAD, 11261 MDIO_PMA_REG_7107_LINK_LED_CNTL, 11262 val); 11263 } 11264 11265 /******************************************************************/ 11266 /* STATIC PHY DECLARATION */ 11267 /******************************************************************/ 11268 11269 static const struct bnx2x_phy phy_null = { 11270 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN, 11271 .addr = 0, 11272 .def_md_devad = 0, 11273 .flags = FLAGS_INIT_XGXS_FIRST, 11274 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11275 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11276 .mdio_ctrl = 0, 11277 .supported = 0, 11278 .media_type = ETH_PHY_NOT_PRESENT, 11279 .ver_addr = 0, 11280 .req_flow_ctrl = 0, 11281 .req_line_speed = 0, 11282 .speed_cap_mask = 0, 11283 .req_duplex = 0, 11284 .rsrv = 0, 11285 .config_init = (config_init_t)NULL, 11286 .read_status = (read_status_t)NULL, 11287 .link_reset = (link_reset_t)NULL, 11288 .config_loopback = (config_loopback_t)NULL, 11289 .format_fw_ver = (format_fw_ver_t)NULL, 11290 .hw_reset = (hw_reset_t)NULL, 11291 .set_link_led = (set_link_led_t)NULL, 11292 .phy_specific_func = (phy_specific_func_t)NULL 11293 }; 11294 11295 static const struct bnx2x_phy phy_serdes = { 11296 .type = PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT, 11297 .addr = 0xff, 11298 .def_md_devad = 0, 11299 .flags = 0, 11300 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11301 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11302 .mdio_ctrl = 0, 11303 .supported = (SUPPORTED_10baseT_Half | 11304 SUPPORTED_10baseT_Full | 11305 SUPPORTED_100baseT_Half | 11306 SUPPORTED_100baseT_Full | 11307 SUPPORTED_1000baseT_Full | 11308 SUPPORTED_2500baseX_Full | 11309 SUPPORTED_TP | 11310 SUPPORTED_Autoneg | 11311 SUPPORTED_Pause | 11312 SUPPORTED_Asym_Pause), 11313 .media_type = ETH_PHY_BASE_T, 11314 .ver_addr = 0, 11315 .req_flow_ctrl = 0, 11316 .req_line_speed = 0, 11317 .speed_cap_mask = 0, 11318 .req_duplex = 0, 11319 .rsrv = 0, 11320 .config_init = (config_init_t)bnx2x_xgxs_config_init, 11321 .read_status = (read_status_t)bnx2x_link_settings_status, 11322 .link_reset = (link_reset_t)bnx2x_int_link_reset, 11323 .config_loopback = (config_loopback_t)NULL, 11324 .format_fw_ver = (format_fw_ver_t)NULL, 11325 .hw_reset = (hw_reset_t)NULL, 11326 .set_link_led = (set_link_led_t)NULL, 11327 .phy_specific_func = (phy_specific_func_t)NULL 11328 }; 11329 11330 static const struct bnx2x_phy phy_xgxs = { 11331 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT, 11332 .addr = 0xff, 11333 .def_md_devad = 0, 11334 .flags = 0, 11335 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11336 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11337 .mdio_ctrl = 0, 11338 .supported = (SUPPORTED_10baseT_Half | 11339 SUPPORTED_10baseT_Full | 11340 SUPPORTED_100baseT_Half | 11341 SUPPORTED_100baseT_Full | 11342 SUPPORTED_1000baseT_Full | 11343 SUPPORTED_2500baseX_Full | 11344 SUPPORTED_10000baseT_Full | 11345 SUPPORTED_FIBRE | 11346 SUPPORTED_Autoneg | 11347 SUPPORTED_Pause | 11348 SUPPORTED_Asym_Pause), 11349 .media_type = ETH_PHY_CX4, 11350 .ver_addr = 0, 11351 .req_flow_ctrl = 0, 11352 .req_line_speed = 0, 11353 .speed_cap_mask = 0, 11354 .req_duplex = 0, 11355 .rsrv = 0, 11356 .config_init = (config_init_t)bnx2x_xgxs_config_init, 11357 .read_status = (read_status_t)bnx2x_link_settings_status, 11358 .link_reset = (link_reset_t)bnx2x_int_link_reset, 11359 .config_loopback = (config_loopback_t)bnx2x_set_xgxs_loopback, 11360 .format_fw_ver = (format_fw_ver_t)NULL, 11361 .hw_reset = (hw_reset_t)NULL, 11362 .set_link_led = (set_link_led_t)NULL, 11363 .phy_specific_func = (phy_specific_func_t)bnx2x_xgxs_specific_func 11364 }; 11365 static const struct bnx2x_phy phy_warpcore = { 11366 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT, 11367 .addr = 0xff, 11368 .def_md_devad = 0, 11369 .flags = FLAGS_TX_ERROR_CHECK, 11370 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11371 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11372 .mdio_ctrl = 0, 11373 .supported = (SUPPORTED_10baseT_Half | 11374 SUPPORTED_10baseT_Full | 11375 SUPPORTED_100baseT_Half | 11376 SUPPORTED_100baseT_Full | 11377 SUPPORTED_1000baseT_Full | 11378 SUPPORTED_10000baseT_Full | 11379 SUPPORTED_20000baseKR2_Full | 11380 SUPPORTED_20000baseMLD2_Full | 11381 SUPPORTED_FIBRE | 11382 SUPPORTED_Autoneg | 11383 SUPPORTED_Pause | 11384 SUPPORTED_Asym_Pause), 11385 .media_type = ETH_PHY_UNSPECIFIED, 11386 .ver_addr = 0, 11387 .req_flow_ctrl = 0, 11388 .req_line_speed = 0, 11389 .speed_cap_mask = 0, 11390 /* req_duplex = */0, 11391 /* rsrv = */0, 11392 .config_init = (config_init_t)bnx2x_warpcore_config_init, 11393 .read_status = (read_status_t)bnx2x_warpcore_read_status, 11394 .link_reset = (link_reset_t)bnx2x_warpcore_link_reset, 11395 .config_loopback = (config_loopback_t)bnx2x_set_warpcore_loopback, 11396 .format_fw_ver = (format_fw_ver_t)NULL, 11397 .hw_reset = (hw_reset_t)bnx2x_warpcore_hw_reset, 11398 .set_link_led = (set_link_led_t)NULL, 11399 .phy_specific_func = (phy_specific_func_t)NULL 11400 }; 11401 11402 11403 static const struct bnx2x_phy phy_7101 = { 11404 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101, 11405 .addr = 0xff, 11406 .def_md_devad = 0, 11407 .flags = FLAGS_FAN_FAILURE_DET_REQ, 11408 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11409 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11410 .mdio_ctrl = 0, 11411 .supported = (SUPPORTED_10000baseT_Full | 11412 SUPPORTED_TP | 11413 SUPPORTED_Autoneg | 11414 SUPPORTED_Pause | 11415 SUPPORTED_Asym_Pause), 11416 .media_type = ETH_PHY_BASE_T, 11417 .ver_addr = 0, 11418 .req_flow_ctrl = 0, 11419 .req_line_speed = 0, 11420 .speed_cap_mask = 0, 11421 .req_duplex = 0, 11422 .rsrv = 0, 11423 .config_init = (config_init_t)bnx2x_7101_config_init, 11424 .read_status = (read_status_t)bnx2x_7101_read_status, 11425 .link_reset = (link_reset_t)bnx2x_common_ext_link_reset, 11426 .config_loopback = (config_loopback_t)bnx2x_7101_config_loopback, 11427 .format_fw_ver = (format_fw_ver_t)bnx2x_7101_format_ver, 11428 .hw_reset = (hw_reset_t)bnx2x_7101_hw_reset, 11429 .set_link_led = (set_link_led_t)bnx2x_7101_set_link_led, 11430 .phy_specific_func = (phy_specific_func_t)NULL 11431 }; 11432 static const struct bnx2x_phy phy_8073 = { 11433 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073, 11434 .addr = 0xff, 11435 .def_md_devad = 0, 11436 .flags = 0, 11437 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11438 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11439 .mdio_ctrl = 0, 11440 .supported = (SUPPORTED_10000baseT_Full | 11441 SUPPORTED_2500baseX_Full | 11442 SUPPORTED_1000baseT_Full | 11443 SUPPORTED_FIBRE | 11444 SUPPORTED_Autoneg | 11445 SUPPORTED_Pause | 11446 SUPPORTED_Asym_Pause), 11447 .media_type = ETH_PHY_KR, 11448 .ver_addr = 0, 11449 .req_flow_ctrl = 0, 11450 .req_line_speed = 0, 11451 .speed_cap_mask = 0, 11452 .req_duplex = 0, 11453 .rsrv = 0, 11454 .config_init = (config_init_t)bnx2x_8073_config_init, 11455 .read_status = (read_status_t)bnx2x_8073_read_status, 11456 .link_reset = (link_reset_t)bnx2x_8073_link_reset, 11457 .config_loopback = (config_loopback_t)NULL, 11458 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver, 11459 .hw_reset = (hw_reset_t)NULL, 11460 .set_link_led = (set_link_led_t)NULL, 11461 .phy_specific_func = (phy_specific_func_t)bnx2x_8073_specific_func 11462 }; 11463 static const struct bnx2x_phy phy_8705 = { 11464 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705, 11465 .addr = 0xff, 11466 .def_md_devad = 0, 11467 .flags = FLAGS_INIT_XGXS_FIRST, 11468 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11469 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11470 .mdio_ctrl = 0, 11471 .supported = (SUPPORTED_10000baseT_Full | 11472 SUPPORTED_FIBRE | 11473 SUPPORTED_Pause | 11474 SUPPORTED_Asym_Pause), 11475 .media_type = ETH_PHY_XFP_FIBER, 11476 .ver_addr = 0, 11477 .req_flow_ctrl = 0, 11478 .req_line_speed = 0, 11479 .speed_cap_mask = 0, 11480 .req_duplex = 0, 11481 .rsrv = 0, 11482 .config_init = (config_init_t)bnx2x_8705_config_init, 11483 .read_status = (read_status_t)bnx2x_8705_read_status, 11484 .link_reset = (link_reset_t)bnx2x_common_ext_link_reset, 11485 .config_loopback = (config_loopback_t)NULL, 11486 .format_fw_ver = (format_fw_ver_t)bnx2x_null_format_ver, 11487 .hw_reset = (hw_reset_t)NULL, 11488 .set_link_led = (set_link_led_t)NULL, 11489 .phy_specific_func = (phy_specific_func_t)NULL 11490 }; 11491 static const struct bnx2x_phy phy_8706 = { 11492 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706, 11493 .addr = 0xff, 11494 .def_md_devad = 0, 11495 .flags = FLAGS_INIT_XGXS_FIRST, 11496 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11497 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11498 .mdio_ctrl = 0, 11499 .supported = (SUPPORTED_10000baseT_Full | 11500 SUPPORTED_1000baseT_Full | 11501 SUPPORTED_FIBRE | 11502 SUPPORTED_Pause | 11503 SUPPORTED_Asym_Pause), 11504 .media_type = ETH_PHY_SFPP_10G_FIBER, 11505 .ver_addr = 0, 11506 .req_flow_ctrl = 0, 11507 .req_line_speed = 0, 11508 .speed_cap_mask = 0, 11509 .req_duplex = 0, 11510 .rsrv = 0, 11511 .config_init = (config_init_t)bnx2x_8706_config_init, 11512 .read_status = (read_status_t)bnx2x_8706_read_status, 11513 .link_reset = (link_reset_t)bnx2x_common_ext_link_reset, 11514 .config_loopback = (config_loopback_t)NULL, 11515 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver, 11516 .hw_reset = (hw_reset_t)NULL, 11517 .set_link_led = (set_link_led_t)NULL, 11518 .phy_specific_func = (phy_specific_func_t)NULL 11519 }; 11520 11521 static const struct bnx2x_phy phy_8726 = { 11522 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726, 11523 .addr = 0xff, 11524 .def_md_devad = 0, 11525 .flags = (FLAGS_INIT_XGXS_FIRST | 11526 FLAGS_TX_ERROR_CHECK), 11527 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11528 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11529 .mdio_ctrl = 0, 11530 .supported = (SUPPORTED_10000baseT_Full | 11531 SUPPORTED_1000baseT_Full | 11532 SUPPORTED_Autoneg | 11533 SUPPORTED_FIBRE | 11534 SUPPORTED_Pause | 11535 SUPPORTED_Asym_Pause), 11536 .media_type = ETH_PHY_NOT_PRESENT, 11537 .ver_addr = 0, 11538 .req_flow_ctrl = 0, 11539 .req_line_speed = 0, 11540 .speed_cap_mask = 0, 11541 .req_duplex = 0, 11542 .rsrv = 0, 11543 .config_init = (config_init_t)bnx2x_8726_config_init, 11544 .read_status = (read_status_t)bnx2x_8726_read_status, 11545 .link_reset = (link_reset_t)bnx2x_8726_link_reset, 11546 .config_loopback = (config_loopback_t)bnx2x_8726_config_loopback, 11547 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver, 11548 .hw_reset = (hw_reset_t)NULL, 11549 .set_link_led = (set_link_led_t)NULL, 11550 .phy_specific_func = (phy_specific_func_t)NULL 11551 }; 11552 11553 static const struct bnx2x_phy phy_8727 = { 11554 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727, 11555 .addr = 0xff, 11556 .def_md_devad = 0, 11557 .flags = (FLAGS_FAN_FAILURE_DET_REQ | 11558 FLAGS_TX_ERROR_CHECK), 11559 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11560 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11561 .mdio_ctrl = 0, 11562 .supported = (SUPPORTED_10000baseT_Full | 11563 SUPPORTED_1000baseT_Full | 11564 SUPPORTED_FIBRE | 11565 SUPPORTED_Pause | 11566 SUPPORTED_Asym_Pause), 11567 .media_type = ETH_PHY_NOT_PRESENT, 11568 .ver_addr = 0, 11569 .req_flow_ctrl = 0, 11570 .req_line_speed = 0, 11571 .speed_cap_mask = 0, 11572 .req_duplex = 0, 11573 .rsrv = 0, 11574 .config_init = (config_init_t)bnx2x_8727_config_init, 11575 .read_status = (read_status_t)bnx2x_8727_read_status, 11576 .link_reset = (link_reset_t)bnx2x_8727_link_reset, 11577 .config_loopback = (config_loopback_t)NULL, 11578 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver, 11579 .hw_reset = (hw_reset_t)bnx2x_8727_hw_reset, 11580 .set_link_led = (set_link_led_t)bnx2x_8727_set_link_led, 11581 .phy_specific_func = (phy_specific_func_t)bnx2x_8727_specific_func 11582 }; 11583 static const struct bnx2x_phy phy_8481 = { 11584 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481, 11585 .addr = 0xff, 11586 .def_md_devad = 0, 11587 .flags = FLAGS_FAN_FAILURE_DET_REQ | 11588 FLAGS_REARM_LATCH_SIGNAL, 11589 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11590 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11591 .mdio_ctrl = 0, 11592 .supported = (SUPPORTED_10baseT_Half | 11593 SUPPORTED_10baseT_Full | 11594 SUPPORTED_100baseT_Half | 11595 SUPPORTED_100baseT_Full | 11596 SUPPORTED_1000baseT_Full | 11597 SUPPORTED_10000baseT_Full | 11598 SUPPORTED_TP | 11599 SUPPORTED_Autoneg | 11600 SUPPORTED_Pause | 11601 SUPPORTED_Asym_Pause), 11602 .media_type = ETH_PHY_BASE_T, 11603 .ver_addr = 0, 11604 .req_flow_ctrl = 0, 11605 .req_line_speed = 0, 11606 .speed_cap_mask = 0, 11607 .req_duplex = 0, 11608 .rsrv = 0, 11609 .config_init = (config_init_t)bnx2x_8481_config_init, 11610 .read_status = (read_status_t)bnx2x_848xx_read_status, 11611 .link_reset = (link_reset_t)bnx2x_8481_link_reset, 11612 .config_loopback = (config_loopback_t)NULL, 11613 .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver, 11614 .hw_reset = (hw_reset_t)bnx2x_8481_hw_reset, 11615 .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led, 11616 .phy_specific_func = (phy_specific_func_t)NULL 11617 }; 11618 11619 static const struct bnx2x_phy phy_84823 = { 11620 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823, 11621 .addr = 0xff, 11622 .def_md_devad = 0, 11623 .flags = (FLAGS_FAN_FAILURE_DET_REQ | 11624 FLAGS_REARM_LATCH_SIGNAL | 11625 FLAGS_TX_ERROR_CHECK), 11626 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11627 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11628 .mdio_ctrl = 0, 11629 .supported = (SUPPORTED_10baseT_Half | 11630 SUPPORTED_10baseT_Full | 11631 SUPPORTED_100baseT_Half | 11632 SUPPORTED_100baseT_Full | 11633 SUPPORTED_1000baseT_Full | 11634 SUPPORTED_10000baseT_Full | 11635 SUPPORTED_TP | 11636 SUPPORTED_Autoneg | 11637 SUPPORTED_Pause | 11638 SUPPORTED_Asym_Pause), 11639 .media_type = ETH_PHY_BASE_T, 11640 .ver_addr = 0, 11641 .req_flow_ctrl = 0, 11642 .req_line_speed = 0, 11643 .speed_cap_mask = 0, 11644 .req_duplex = 0, 11645 .rsrv = 0, 11646 .config_init = (config_init_t)bnx2x_848x3_config_init, 11647 .read_status = (read_status_t)bnx2x_848xx_read_status, 11648 .link_reset = (link_reset_t)bnx2x_848x3_link_reset, 11649 .config_loopback = (config_loopback_t)NULL, 11650 .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver, 11651 .hw_reset = (hw_reset_t)NULL, 11652 .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led, 11653 .phy_specific_func = (phy_specific_func_t)bnx2x_848xx_specific_func 11654 }; 11655 11656 static const struct bnx2x_phy phy_84833 = { 11657 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833, 11658 .addr = 0xff, 11659 .def_md_devad = 0, 11660 .flags = (FLAGS_FAN_FAILURE_DET_REQ | 11661 FLAGS_REARM_LATCH_SIGNAL | 11662 FLAGS_TX_ERROR_CHECK), 11663 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11664 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11665 .mdio_ctrl = 0, 11666 .supported = (SUPPORTED_100baseT_Half | 11667 SUPPORTED_100baseT_Full | 11668 SUPPORTED_1000baseT_Full | 11669 SUPPORTED_10000baseT_Full | 11670 SUPPORTED_TP | 11671 SUPPORTED_Autoneg | 11672 SUPPORTED_Pause | 11673 SUPPORTED_Asym_Pause), 11674 .media_type = ETH_PHY_BASE_T, 11675 .ver_addr = 0, 11676 .req_flow_ctrl = 0, 11677 .req_line_speed = 0, 11678 .speed_cap_mask = 0, 11679 .req_duplex = 0, 11680 .rsrv = 0, 11681 .config_init = (config_init_t)bnx2x_848x3_config_init, 11682 .read_status = (read_status_t)bnx2x_848xx_read_status, 11683 .link_reset = (link_reset_t)bnx2x_848x3_link_reset, 11684 .config_loopback = (config_loopback_t)NULL, 11685 .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver, 11686 .hw_reset = (hw_reset_t)bnx2x_84833_hw_reset_phy, 11687 .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led, 11688 .phy_specific_func = (phy_specific_func_t)bnx2x_848xx_specific_func 11689 }; 11690 11691 static const struct bnx2x_phy phy_84834 = { 11692 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834, 11693 .addr = 0xff, 11694 .def_md_devad = 0, 11695 .flags = FLAGS_FAN_FAILURE_DET_REQ | 11696 FLAGS_REARM_LATCH_SIGNAL, 11697 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11698 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11699 .mdio_ctrl = 0, 11700 .supported = (SUPPORTED_100baseT_Half | 11701 SUPPORTED_100baseT_Full | 11702 SUPPORTED_1000baseT_Full | 11703 SUPPORTED_10000baseT_Full | 11704 SUPPORTED_TP | 11705 SUPPORTED_Autoneg | 11706 SUPPORTED_Pause | 11707 SUPPORTED_Asym_Pause), 11708 .media_type = ETH_PHY_BASE_T, 11709 .ver_addr = 0, 11710 .req_flow_ctrl = 0, 11711 .req_line_speed = 0, 11712 .speed_cap_mask = 0, 11713 .req_duplex = 0, 11714 .rsrv = 0, 11715 .config_init = (config_init_t)bnx2x_848x3_config_init, 11716 .read_status = (read_status_t)bnx2x_848xx_read_status, 11717 .link_reset = (link_reset_t)bnx2x_848x3_link_reset, 11718 .config_loopback = (config_loopback_t)NULL, 11719 .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver, 11720 .hw_reset = (hw_reset_t)bnx2x_84833_hw_reset_phy, 11721 .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led, 11722 .phy_specific_func = (phy_specific_func_t)bnx2x_848xx_specific_func 11723 }; 11724 11725 static const struct bnx2x_phy phy_54618se = { 11726 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE, 11727 .addr = 0xff, 11728 .def_md_devad = 0, 11729 .flags = FLAGS_INIT_XGXS_FIRST, 11730 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11731 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11732 .mdio_ctrl = 0, 11733 .supported = (SUPPORTED_10baseT_Half | 11734 SUPPORTED_10baseT_Full | 11735 SUPPORTED_100baseT_Half | 11736 SUPPORTED_100baseT_Full | 11737 SUPPORTED_1000baseT_Full | 11738 SUPPORTED_TP | 11739 SUPPORTED_Autoneg | 11740 SUPPORTED_Pause | 11741 SUPPORTED_Asym_Pause), 11742 .media_type = ETH_PHY_BASE_T, 11743 .ver_addr = 0, 11744 .req_flow_ctrl = 0, 11745 .req_line_speed = 0, 11746 .speed_cap_mask = 0, 11747 /* req_duplex = */0, 11748 /* rsrv = */0, 11749 .config_init = (config_init_t)bnx2x_54618se_config_init, 11750 .read_status = (read_status_t)bnx2x_54618se_read_status, 11751 .link_reset = (link_reset_t)bnx2x_54618se_link_reset, 11752 .config_loopback = (config_loopback_t)bnx2x_54618se_config_loopback, 11753 .format_fw_ver = (format_fw_ver_t)NULL, 11754 .hw_reset = (hw_reset_t)NULL, 11755 .set_link_led = (set_link_led_t)bnx2x_5461x_set_link_led, 11756 .phy_specific_func = (phy_specific_func_t)bnx2x_54618se_specific_func 11757 }; 11758 /*****************************************************************/ 11759 /* */ 11760 /* Populate the phy according. Main function: bnx2x_populate_phy */ 11761 /* */ 11762 /*****************************************************************/ 11763 11764 static void bnx2x_populate_preemphasis(struct bnx2x *bp, u32 shmem_base, 11765 struct bnx2x_phy *phy, u8 port, 11766 u8 phy_index) 11767 { 11768 /* Get the 4 lanes xgxs config rx and tx */ 11769 u32 rx = 0, tx = 0, i; 11770 for (i = 0; i < 2; i++) { 11771 /* INT_PHY and EXT_PHY1 share the same value location in 11772 * the shmem. When num_phys is greater than 1, than this value 11773 * applies only to EXT_PHY1 11774 */ 11775 if (phy_index == INT_PHY || phy_index == EXT_PHY1) { 11776 rx = REG_RD(bp, shmem_base + 11777 offsetof(struct shmem_region, 11778 dev_info.port_hw_config[port].xgxs_config_rx[i<<1])); 11779 11780 tx = REG_RD(bp, shmem_base + 11781 offsetof(struct shmem_region, 11782 dev_info.port_hw_config[port].xgxs_config_tx[i<<1])); 11783 } else { 11784 rx = REG_RD(bp, shmem_base + 11785 offsetof(struct shmem_region, 11786 dev_info.port_hw_config[port].xgxs_config2_rx[i<<1])); 11787 11788 tx = REG_RD(bp, shmem_base + 11789 offsetof(struct shmem_region, 11790 dev_info.port_hw_config[port].xgxs_config2_rx[i<<1])); 11791 } 11792 11793 phy->rx_preemphasis[i << 1] = ((rx>>16) & 0xffff); 11794 phy->rx_preemphasis[(i << 1) + 1] = (rx & 0xffff); 11795 11796 phy->tx_preemphasis[i << 1] = ((tx>>16) & 0xffff); 11797 phy->tx_preemphasis[(i << 1) + 1] = (tx & 0xffff); 11798 } 11799 } 11800 11801 static u32 bnx2x_get_ext_phy_config(struct bnx2x *bp, u32 shmem_base, 11802 u8 phy_index, u8 port) 11803 { 11804 u32 ext_phy_config = 0; 11805 switch (phy_index) { 11806 case EXT_PHY1: 11807 ext_phy_config = REG_RD(bp, shmem_base + 11808 offsetof(struct shmem_region, 11809 dev_info.port_hw_config[port].external_phy_config)); 11810 break; 11811 case EXT_PHY2: 11812 ext_phy_config = REG_RD(bp, shmem_base + 11813 offsetof(struct shmem_region, 11814 dev_info.port_hw_config[port].external_phy_config2)); 11815 break; 11816 default: 11817 DP(NETIF_MSG_LINK, "Invalid phy_index %d\n", phy_index); 11818 return -EINVAL; 11819 } 11820 11821 return ext_phy_config; 11822 } 11823 static int bnx2x_populate_int_phy(struct bnx2x *bp, u32 shmem_base, u8 port, 11824 struct bnx2x_phy *phy) 11825 { 11826 u32 phy_addr; 11827 u32 chip_id; 11828 u32 switch_cfg = (REG_RD(bp, shmem_base + 11829 offsetof(struct shmem_region, 11830 dev_info.port_feature_config[port].link_config)) & 11831 PORT_FEATURE_CONNECTED_SWITCH_MASK); 11832 chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) | 11833 ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12); 11834 11835 DP(NETIF_MSG_LINK, ":chip_id = 0x%x\n", chip_id); 11836 if (USES_WARPCORE(bp)) { 11837 u32 serdes_net_if; 11838 phy_addr = REG_RD(bp, 11839 MISC_REG_WC0_CTRL_PHY_ADDR); 11840 *phy = phy_warpcore; 11841 if (REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR) == 0x3) 11842 phy->flags |= FLAGS_4_PORT_MODE; 11843 else 11844 phy->flags &= ~FLAGS_4_PORT_MODE; 11845 /* Check Dual mode */ 11846 serdes_net_if = (REG_RD(bp, shmem_base + 11847 offsetof(struct shmem_region, dev_info. 11848 port_hw_config[port].default_cfg)) & 11849 PORT_HW_CFG_NET_SERDES_IF_MASK); 11850 /* Set the appropriate supported and flags indications per 11851 * interface type of the chip 11852 */ 11853 switch (serdes_net_if) { 11854 case PORT_HW_CFG_NET_SERDES_IF_SGMII: 11855 phy->supported &= (SUPPORTED_10baseT_Half | 11856 SUPPORTED_10baseT_Full | 11857 SUPPORTED_100baseT_Half | 11858 SUPPORTED_100baseT_Full | 11859 SUPPORTED_1000baseT_Full | 11860 SUPPORTED_FIBRE | 11861 SUPPORTED_Autoneg | 11862 SUPPORTED_Pause | 11863 SUPPORTED_Asym_Pause); 11864 phy->media_type = ETH_PHY_BASE_T; 11865 break; 11866 case PORT_HW_CFG_NET_SERDES_IF_XFI: 11867 phy->supported &= (SUPPORTED_1000baseT_Full | 11868 SUPPORTED_10000baseT_Full | 11869 SUPPORTED_FIBRE | 11870 SUPPORTED_Pause | 11871 SUPPORTED_Asym_Pause); 11872 phy->media_type = ETH_PHY_XFP_FIBER; 11873 break; 11874 case PORT_HW_CFG_NET_SERDES_IF_SFI: 11875 phy->supported &= (SUPPORTED_1000baseT_Full | 11876 SUPPORTED_10000baseT_Full | 11877 SUPPORTED_FIBRE | 11878 SUPPORTED_Pause | 11879 SUPPORTED_Asym_Pause); 11880 phy->media_type = ETH_PHY_SFPP_10G_FIBER; 11881 break; 11882 case PORT_HW_CFG_NET_SERDES_IF_KR: 11883 phy->media_type = ETH_PHY_KR; 11884 phy->supported &= (SUPPORTED_1000baseT_Full | 11885 SUPPORTED_10000baseT_Full | 11886 SUPPORTED_FIBRE | 11887 SUPPORTED_Autoneg | 11888 SUPPORTED_Pause | 11889 SUPPORTED_Asym_Pause); 11890 break; 11891 case PORT_HW_CFG_NET_SERDES_IF_DXGXS: 11892 phy->media_type = ETH_PHY_KR; 11893 phy->flags |= FLAGS_WC_DUAL_MODE; 11894 phy->supported &= (SUPPORTED_20000baseMLD2_Full | 11895 SUPPORTED_FIBRE | 11896 SUPPORTED_Pause | 11897 SUPPORTED_Asym_Pause); 11898 break; 11899 case PORT_HW_CFG_NET_SERDES_IF_KR2: 11900 phy->media_type = ETH_PHY_KR; 11901 phy->flags |= FLAGS_WC_DUAL_MODE; 11902 phy->supported &= (SUPPORTED_20000baseKR2_Full | 11903 SUPPORTED_10000baseT_Full | 11904 SUPPORTED_1000baseT_Full | 11905 SUPPORTED_Autoneg | 11906 SUPPORTED_FIBRE | 11907 SUPPORTED_Pause | 11908 SUPPORTED_Asym_Pause); 11909 phy->flags &= ~FLAGS_TX_ERROR_CHECK; 11910 break; 11911 default: 11912 DP(NETIF_MSG_LINK, "Unknown WC interface type 0x%x\n", 11913 serdes_net_if); 11914 break; 11915 } 11916 11917 /* Enable MDC/MDIO work-around for E3 A0 since free running MDC 11918 * was not set as expected. For B0, ECO will be enabled so there 11919 * won't be an issue there 11920 */ 11921 if (CHIP_REV(bp) == CHIP_REV_Ax) 11922 phy->flags |= FLAGS_MDC_MDIO_WA; 11923 else 11924 phy->flags |= FLAGS_MDC_MDIO_WA_B0; 11925 } else { 11926 switch (switch_cfg) { 11927 case SWITCH_CFG_1G: 11928 phy_addr = REG_RD(bp, 11929 NIG_REG_SERDES0_CTRL_PHY_ADDR + 11930 port * 0x10); 11931 *phy = phy_serdes; 11932 break; 11933 case SWITCH_CFG_10G: 11934 phy_addr = REG_RD(bp, 11935 NIG_REG_XGXS0_CTRL_PHY_ADDR + 11936 port * 0x18); 11937 *phy = phy_xgxs; 11938 break; 11939 default: 11940 DP(NETIF_MSG_LINK, "Invalid switch_cfg\n"); 11941 return -EINVAL; 11942 } 11943 } 11944 phy->addr = (u8)phy_addr; 11945 phy->mdio_ctrl = bnx2x_get_emac_base(bp, 11946 SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH, 11947 port); 11948 if (CHIP_IS_E2(bp)) 11949 phy->def_md_devad = E2_DEFAULT_PHY_DEV_ADDR; 11950 else 11951 phy->def_md_devad = DEFAULT_PHY_DEV_ADDR; 11952 11953 DP(NETIF_MSG_LINK, "Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x\n", 11954 port, phy->addr, phy->mdio_ctrl); 11955 11956 bnx2x_populate_preemphasis(bp, shmem_base, phy, port, INT_PHY); 11957 return 0; 11958 } 11959 11960 static int bnx2x_populate_ext_phy(struct bnx2x *bp, 11961 u8 phy_index, 11962 u32 shmem_base, 11963 u32 shmem2_base, 11964 u8 port, 11965 struct bnx2x_phy *phy) 11966 { 11967 u32 ext_phy_config, phy_type, config2; 11968 u32 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH; 11969 ext_phy_config = bnx2x_get_ext_phy_config(bp, shmem_base, 11970 phy_index, port); 11971 phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config); 11972 /* Select the phy type */ 11973 switch (phy_type) { 11974 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073: 11975 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED; 11976 *phy = phy_8073; 11977 break; 11978 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705: 11979 *phy = phy_8705; 11980 break; 11981 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706: 11982 *phy = phy_8706; 11983 break; 11984 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: 11985 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1; 11986 *phy = phy_8726; 11987 break; 11988 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC: 11989 /* BCM8727_NOC => BCM8727 no over current */ 11990 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1; 11991 *phy = phy_8727; 11992 phy->flags |= FLAGS_NOC; 11993 break; 11994 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722: 11995 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: 11996 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1; 11997 *phy = phy_8727; 11998 break; 11999 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481: 12000 *phy = phy_8481; 12001 break; 12002 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823: 12003 *phy = phy_84823; 12004 break; 12005 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833: 12006 *phy = phy_84833; 12007 break; 12008 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834: 12009 *phy = phy_84834; 12010 break; 12011 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616: 12012 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE: 12013 *phy = phy_54618se; 12014 if (phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) 12015 phy->flags |= FLAGS_EEE; 12016 break; 12017 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101: 12018 *phy = phy_7101; 12019 break; 12020 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE: 12021 *phy = phy_null; 12022 return -EINVAL; 12023 default: 12024 *phy = phy_null; 12025 /* In case external PHY wasn't found */ 12026 if ((phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) && 12027 (phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)) 12028 return -EINVAL; 12029 return 0; 12030 } 12031 12032 phy->addr = XGXS_EXT_PHY_ADDR(ext_phy_config); 12033 bnx2x_populate_preemphasis(bp, shmem_base, phy, port, phy_index); 12034 12035 /* The shmem address of the phy version is located on different 12036 * structures. In case this structure is too old, do not set 12037 * the address 12038 */ 12039 config2 = REG_RD(bp, shmem_base + offsetof(struct shmem_region, 12040 dev_info.shared_hw_config.config2)); 12041 if (phy_index == EXT_PHY1) { 12042 phy->ver_addr = shmem_base + offsetof(struct shmem_region, 12043 port_mb[port].ext_phy_fw_version); 12044 12045 /* Check specific mdc mdio settings */ 12046 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK) 12047 mdc_mdio_access = config2 & 12048 SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK; 12049 } else { 12050 u32 size = REG_RD(bp, shmem2_base); 12051 12052 if (size > 12053 offsetof(struct shmem2_region, ext_phy_fw_version2)) { 12054 phy->ver_addr = shmem2_base + 12055 offsetof(struct shmem2_region, 12056 ext_phy_fw_version2[port]); 12057 } 12058 /* Check specific mdc mdio settings */ 12059 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) 12060 mdc_mdio_access = (config2 & 12061 SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) >> 12062 (SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT - 12063 SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT); 12064 } 12065 phy->mdio_ctrl = bnx2x_get_emac_base(bp, mdc_mdio_access, port); 12066 12067 if (((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) || 12068 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) && 12069 (phy->ver_addr)) { 12070 /* Remove 100Mb link supported for BCM84833/4 when phy fw 12071 * version lower than or equal to 1.39 12072 */ 12073 u32 raw_ver = REG_RD(bp, phy->ver_addr); 12074 if (((raw_ver & 0x7F) <= 39) && 12075 (((raw_ver & 0xF80) >> 7) <= 1)) 12076 phy->supported &= ~(SUPPORTED_100baseT_Half | 12077 SUPPORTED_100baseT_Full); 12078 } 12079 12080 DP(NETIF_MSG_LINK, "phy_type 0x%x port %d found in index %d\n", 12081 phy_type, port, phy_index); 12082 DP(NETIF_MSG_LINK, " addr=0x%x, mdio_ctl=0x%x\n", 12083 phy->addr, phy->mdio_ctrl); 12084 return 0; 12085 } 12086 12087 static int bnx2x_populate_phy(struct bnx2x *bp, u8 phy_index, u32 shmem_base, 12088 u32 shmem2_base, u8 port, struct bnx2x_phy *phy) 12089 { 12090 int status = 0; 12091 phy->type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN; 12092 if (phy_index == INT_PHY) 12093 return bnx2x_populate_int_phy(bp, shmem_base, port, phy); 12094 status = bnx2x_populate_ext_phy(bp, phy_index, shmem_base, shmem2_base, 12095 port, phy); 12096 return status; 12097 } 12098 12099 static void bnx2x_phy_def_cfg(struct link_params *params, 12100 struct bnx2x_phy *phy, 12101 u8 phy_index) 12102 { 12103 struct bnx2x *bp = params->bp; 12104 u32 link_config; 12105 /* Populate the default phy configuration for MF mode */ 12106 if (phy_index == EXT_PHY2) { 12107 link_config = REG_RD(bp, params->shmem_base + 12108 offsetof(struct shmem_region, dev_info. 12109 port_feature_config[params->port].link_config2)); 12110 phy->speed_cap_mask = REG_RD(bp, params->shmem_base + 12111 offsetof(struct shmem_region, 12112 dev_info. 12113 port_hw_config[params->port].speed_capability_mask2)); 12114 } else { 12115 link_config = REG_RD(bp, params->shmem_base + 12116 offsetof(struct shmem_region, dev_info. 12117 port_feature_config[params->port].link_config)); 12118 phy->speed_cap_mask = REG_RD(bp, params->shmem_base + 12119 offsetof(struct shmem_region, 12120 dev_info. 12121 port_hw_config[params->port].speed_capability_mask)); 12122 } 12123 DP(NETIF_MSG_LINK, 12124 "Default config phy idx %x cfg 0x%x speed_cap_mask 0x%x\n", 12125 phy_index, link_config, phy->speed_cap_mask); 12126 12127 phy->req_duplex = DUPLEX_FULL; 12128 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) { 12129 case PORT_FEATURE_LINK_SPEED_10M_HALF: 12130 phy->req_duplex = DUPLEX_HALF; 12131 case PORT_FEATURE_LINK_SPEED_10M_FULL: 12132 phy->req_line_speed = SPEED_10; 12133 break; 12134 case PORT_FEATURE_LINK_SPEED_100M_HALF: 12135 phy->req_duplex = DUPLEX_HALF; 12136 case PORT_FEATURE_LINK_SPEED_100M_FULL: 12137 phy->req_line_speed = SPEED_100; 12138 break; 12139 case PORT_FEATURE_LINK_SPEED_1G: 12140 phy->req_line_speed = SPEED_1000; 12141 break; 12142 case PORT_FEATURE_LINK_SPEED_2_5G: 12143 phy->req_line_speed = SPEED_2500; 12144 break; 12145 case PORT_FEATURE_LINK_SPEED_10G_CX4: 12146 phy->req_line_speed = SPEED_10000; 12147 break; 12148 default: 12149 phy->req_line_speed = SPEED_AUTO_NEG; 12150 break; 12151 } 12152 12153 switch (link_config & PORT_FEATURE_FLOW_CONTROL_MASK) { 12154 case PORT_FEATURE_FLOW_CONTROL_AUTO: 12155 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_AUTO; 12156 break; 12157 case PORT_FEATURE_FLOW_CONTROL_TX: 12158 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_TX; 12159 break; 12160 case PORT_FEATURE_FLOW_CONTROL_RX: 12161 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_RX; 12162 break; 12163 case PORT_FEATURE_FLOW_CONTROL_BOTH: 12164 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_BOTH; 12165 break; 12166 default: 12167 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_NONE; 12168 break; 12169 } 12170 } 12171 12172 u32 bnx2x_phy_selection(struct link_params *params) 12173 { 12174 u32 phy_config_swapped, prio_cfg; 12175 u32 return_cfg = PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT; 12176 12177 phy_config_swapped = params->multi_phy_config & 12178 PORT_HW_CFG_PHY_SWAPPED_ENABLED; 12179 12180 prio_cfg = params->multi_phy_config & 12181 PORT_HW_CFG_PHY_SELECTION_MASK; 12182 12183 if (phy_config_swapped) { 12184 switch (prio_cfg) { 12185 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY: 12186 return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY; 12187 break; 12188 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY: 12189 return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY; 12190 break; 12191 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY: 12192 return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY; 12193 break; 12194 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY: 12195 return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY; 12196 break; 12197 } 12198 } else 12199 return_cfg = prio_cfg; 12200 12201 return return_cfg; 12202 } 12203 12204 int bnx2x_phy_probe(struct link_params *params) 12205 { 12206 u8 phy_index, actual_phy_idx; 12207 u32 phy_config_swapped, sync_offset, media_types; 12208 struct bnx2x *bp = params->bp; 12209 struct bnx2x_phy *phy; 12210 params->num_phys = 0; 12211 DP(NETIF_MSG_LINK, "Begin phy probe\n"); 12212 phy_config_swapped = params->multi_phy_config & 12213 PORT_HW_CFG_PHY_SWAPPED_ENABLED; 12214 12215 for (phy_index = INT_PHY; phy_index < MAX_PHYS; 12216 phy_index++) { 12217 actual_phy_idx = phy_index; 12218 if (phy_config_swapped) { 12219 if (phy_index == EXT_PHY1) 12220 actual_phy_idx = EXT_PHY2; 12221 else if (phy_index == EXT_PHY2) 12222 actual_phy_idx = EXT_PHY1; 12223 } 12224 DP(NETIF_MSG_LINK, "phy_config_swapped %x, phy_index %x," 12225 " actual_phy_idx %x\n", phy_config_swapped, 12226 phy_index, actual_phy_idx); 12227 phy = ¶ms->phy[actual_phy_idx]; 12228 if (bnx2x_populate_phy(bp, phy_index, params->shmem_base, 12229 params->shmem2_base, params->port, 12230 phy) != 0) { 12231 params->num_phys = 0; 12232 DP(NETIF_MSG_LINK, "phy probe failed in phy index %d\n", 12233 phy_index); 12234 for (phy_index = INT_PHY; 12235 phy_index < MAX_PHYS; 12236 phy_index++) 12237 *phy = phy_null; 12238 return -EINVAL; 12239 } 12240 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN) 12241 break; 12242 12243 if (params->feature_config_flags & 12244 FEATURE_CONFIG_DISABLE_REMOTE_FAULT_DET) 12245 phy->flags &= ~FLAGS_TX_ERROR_CHECK; 12246 12247 if (!(params->feature_config_flags & 12248 FEATURE_CONFIG_MT_SUPPORT)) 12249 phy->flags |= FLAGS_MDC_MDIO_WA_G; 12250 12251 sync_offset = params->shmem_base + 12252 offsetof(struct shmem_region, 12253 dev_info.port_hw_config[params->port].media_type); 12254 media_types = REG_RD(bp, sync_offset); 12255 12256 /* Update media type for non-PMF sync only for the first time 12257 * In case the media type changes afterwards, it will be updated 12258 * using the update_status function 12259 */ 12260 if ((media_types & (PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK << 12261 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * 12262 actual_phy_idx))) == 0) { 12263 media_types |= ((phy->media_type & 12264 PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) << 12265 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * 12266 actual_phy_idx)); 12267 } 12268 REG_WR(bp, sync_offset, media_types); 12269 12270 bnx2x_phy_def_cfg(params, phy, phy_index); 12271 params->num_phys++; 12272 } 12273 12274 DP(NETIF_MSG_LINK, "End phy probe. #phys found %x\n", params->num_phys); 12275 return 0; 12276 } 12277 12278 static void bnx2x_init_bmac_loopback(struct link_params *params, 12279 struct link_vars *vars) 12280 { 12281 struct bnx2x *bp = params->bp; 12282 vars->link_up = 1; 12283 vars->line_speed = SPEED_10000; 12284 vars->duplex = DUPLEX_FULL; 12285 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; 12286 vars->mac_type = MAC_TYPE_BMAC; 12287 12288 vars->phy_flags = PHY_XGXS_FLAG; 12289 12290 bnx2x_xgxs_deassert(params); 12291 12292 /* Set bmac loopback */ 12293 bnx2x_bmac_enable(params, vars, 1, 1); 12294 12295 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); 12296 } 12297 12298 static void bnx2x_init_emac_loopback(struct link_params *params, 12299 struct link_vars *vars) 12300 { 12301 struct bnx2x *bp = params->bp; 12302 vars->link_up = 1; 12303 vars->line_speed = SPEED_1000; 12304 vars->duplex = DUPLEX_FULL; 12305 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; 12306 vars->mac_type = MAC_TYPE_EMAC; 12307 12308 vars->phy_flags = PHY_XGXS_FLAG; 12309 12310 bnx2x_xgxs_deassert(params); 12311 /* Set bmac loopback */ 12312 bnx2x_emac_enable(params, vars, 1); 12313 bnx2x_emac_program(params, vars); 12314 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); 12315 } 12316 12317 static void bnx2x_init_xmac_loopback(struct link_params *params, 12318 struct link_vars *vars) 12319 { 12320 struct bnx2x *bp = params->bp; 12321 vars->link_up = 1; 12322 if (!params->req_line_speed[0]) 12323 vars->line_speed = SPEED_10000; 12324 else 12325 vars->line_speed = params->req_line_speed[0]; 12326 vars->duplex = DUPLEX_FULL; 12327 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; 12328 vars->mac_type = MAC_TYPE_XMAC; 12329 vars->phy_flags = PHY_XGXS_FLAG; 12330 /* Set WC to loopback mode since link is required to provide clock 12331 * to the XMAC in 20G mode 12332 */ 12333 bnx2x_set_aer_mmd(params, ¶ms->phy[0]); 12334 bnx2x_warpcore_reset_lane(bp, ¶ms->phy[0], 0); 12335 params->phy[INT_PHY].config_loopback( 12336 ¶ms->phy[INT_PHY], 12337 params); 12338 12339 bnx2x_xmac_enable(params, vars, 1); 12340 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); 12341 } 12342 12343 static void bnx2x_init_umac_loopback(struct link_params *params, 12344 struct link_vars *vars) 12345 { 12346 struct bnx2x *bp = params->bp; 12347 vars->link_up = 1; 12348 vars->line_speed = SPEED_1000; 12349 vars->duplex = DUPLEX_FULL; 12350 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; 12351 vars->mac_type = MAC_TYPE_UMAC; 12352 vars->phy_flags = PHY_XGXS_FLAG; 12353 bnx2x_umac_enable(params, vars, 1); 12354 12355 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); 12356 } 12357 12358 static void bnx2x_init_xgxs_loopback(struct link_params *params, 12359 struct link_vars *vars) 12360 { 12361 struct bnx2x *bp = params->bp; 12362 struct bnx2x_phy *int_phy = ¶ms->phy[INT_PHY]; 12363 vars->link_up = 1; 12364 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; 12365 vars->duplex = DUPLEX_FULL; 12366 if (params->req_line_speed[0] == SPEED_1000) 12367 vars->line_speed = SPEED_1000; 12368 else if ((params->req_line_speed[0] == SPEED_20000) || 12369 (int_phy->flags & FLAGS_WC_DUAL_MODE)) 12370 vars->line_speed = SPEED_20000; 12371 else 12372 vars->line_speed = SPEED_10000; 12373 12374 if (!USES_WARPCORE(bp)) 12375 bnx2x_xgxs_deassert(params); 12376 bnx2x_link_initialize(params, vars); 12377 12378 if (params->req_line_speed[0] == SPEED_1000) { 12379 if (USES_WARPCORE(bp)) 12380 bnx2x_umac_enable(params, vars, 0); 12381 else { 12382 bnx2x_emac_program(params, vars); 12383 bnx2x_emac_enable(params, vars, 0); 12384 } 12385 } else { 12386 if (USES_WARPCORE(bp)) 12387 bnx2x_xmac_enable(params, vars, 0); 12388 else 12389 bnx2x_bmac_enable(params, vars, 0, 1); 12390 } 12391 12392 if (params->loopback_mode == LOOPBACK_XGXS) { 12393 /* Set 10G XGXS loopback */ 12394 int_phy->config_loopback(int_phy, params); 12395 } else { 12396 /* Set external phy loopback */ 12397 u8 phy_index; 12398 for (phy_index = EXT_PHY1; 12399 phy_index < params->num_phys; phy_index++) 12400 if (params->phy[phy_index].config_loopback) 12401 params->phy[phy_index].config_loopback( 12402 ¶ms->phy[phy_index], 12403 params); 12404 } 12405 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); 12406 12407 bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed); 12408 } 12409 12410 void bnx2x_set_rx_filter(struct link_params *params, u8 en) 12411 { 12412 struct bnx2x *bp = params->bp; 12413 u8 val = en * 0x1F; 12414 12415 /* Open / close the gate between the NIG and the BRB */ 12416 if (!CHIP_IS_E1x(bp)) 12417 val |= en * 0x20; 12418 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + params->port*4, val); 12419 12420 if (!CHIP_IS_E1(bp)) { 12421 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + params->port*4, 12422 en*0x3); 12423 } 12424 12425 REG_WR(bp, (params->port ? NIG_REG_LLH1_BRB1_NOT_MCP : 12426 NIG_REG_LLH0_BRB1_NOT_MCP), en); 12427 } 12428 static int bnx2x_avoid_link_flap(struct link_params *params, 12429 struct link_vars *vars) 12430 { 12431 u32 phy_idx; 12432 u32 dont_clear_stat, lfa_sts; 12433 struct bnx2x *bp = params->bp; 12434 12435 /* Sync the link parameters */ 12436 bnx2x_link_status_update(params, vars); 12437 12438 /* 12439 * The module verification was already done by previous link owner, 12440 * so this call is meant only to get warning message 12441 */ 12442 12443 for (phy_idx = INT_PHY; phy_idx < params->num_phys; phy_idx++) { 12444 struct bnx2x_phy *phy = ¶ms->phy[phy_idx]; 12445 if (phy->phy_specific_func) { 12446 DP(NETIF_MSG_LINK, "Calling PHY specific func\n"); 12447 phy->phy_specific_func(phy, params, PHY_INIT); 12448 } 12449 if ((phy->media_type == ETH_PHY_SFPP_10G_FIBER) || 12450 (phy->media_type == ETH_PHY_SFP_1G_FIBER) || 12451 (phy->media_type == ETH_PHY_DA_TWINAX)) 12452 bnx2x_verify_sfp_module(phy, params); 12453 } 12454 lfa_sts = REG_RD(bp, params->lfa_base + 12455 offsetof(struct shmem_lfa, 12456 lfa_sts)); 12457 12458 dont_clear_stat = lfa_sts & SHMEM_LFA_DONT_CLEAR_STAT; 12459 12460 /* Re-enable the NIG/MAC */ 12461 if (CHIP_IS_E3(bp)) { 12462 if (!dont_clear_stat) { 12463 REG_WR(bp, GRCBASE_MISC + 12464 MISC_REGISTERS_RESET_REG_2_CLEAR, 12465 (MISC_REGISTERS_RESET_REG_2_MSTAT0 << 12466 params->port)); 12467 REG_WR(bp, GRCBASE_MISC + 12468 MISC_REGISTERS_RESET_REG_2_SET, 12469 (MISC_REGISTERS_RESET_REG_2_MSTAT0 << 12470 params->port)); 12471 } 12472 if (vars->line_speed < SPEED_10000) 12473 bnx2x_umac_enable(params, vars, 0); 12474 else 12475 bnx2x_xmac_enable(params, vars, 0); 12476 } else { 12477 if (vars->line_speed < SPEED_10000) 12478 bnx2x_emac_enable(params, vars, 0); 12479 else 12480 bnx2x_bmac_enable(params, vars, 0, !dont_clear_stat); 12481 } 12482 12483 /* Increment LFA count */ 12484 lfa_sts = ((lfa_sts & ~LINK_FLAP_AVOIDANCE_COUNT_MASK) | 12485 (((((lfa_sts & LINK_FLAP_AVOIDANCE_COUNT_MASK) >> 12486 LINK_FLAP_AVOIDANCE_COUNT_OFFSET) + 1) & 0xff) 12487 << LINK_FLAP_AVOIDANCE_COUNT_OFFSET)); 12488 /* Clear link flap reason */ 12489 lfa_sts &= ~LFA_LINK_FLAP_REASON_MASK; 12490 12491 REG_WR(bp, params->lfa_base + 12492 offsetof(struct shmem_lfa, lfa_sts), lfa_sts); 12493 12494 /* Disable NIG DRAIN */ 12495 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); 12496 12497 /* Enable interrupts */ 12498 bnx2x_link_int_enable(params); 12499 return 0; 12500 } 12501 12502 static void bnx2x_cannot_avoid_link_flap(struct link_params *params, 12503 struct link_vars *vars, 12504 int lfa_status) 12505 { 12506 u32 lfa_sts, cfg_idx, tmp_val; 12507 struct bnx2x *bp = params->bp; 12508 12509 bnx2x_link_reset(params, vars, 1); 12510 12511 if (!params->lfa_base) 12512 return; 12513 /* Store the new link parameters */ 12514 REG_WR(bp, params->lfa_base + 12515 offsetof(struct shmem_lfa, req_duplex), 12516 params->req_duplex[0] | (params->req_duplex[1] << 16)); 12517 12518 REG_WR(bp, params->lfa_base + 12519 offsetof(struct shmem_lfa, req_flow_ctrl), 12520 params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16)); 12521 12522 REG_WR(bp, params->lfa_base + 12523 offsetof(struct shmem_lfa, req_line_speed), 12524 params->req_line_speed[0] | (params->req_line_speed[1] << 16)); 12525 12526 for (cfg_idx = 0; cfg_idx < SHMEM_LINK_CONFIG_SIZE; cfg_idx++) { 12527 REG_WR(bp, params->lfa_base + 12528 offsetof(struct shmem_lfa, 12529 speed_cap_mask[cfg_idx]), 12530 params->speed_cap_mask[cfg_idx]); 12531 } 12532 12533 tmp_val = REG_RD(bp, params->lfa_base + 12534 offsetof(struct shmem_lfa, additional_config)); 12535 tmp_val &= ~REQ_FC_AUTO_ADV_MASK; 12536 tmp_val |= params->req_fc_auto_adv; 12537 12538 REG_WR(bp, params->lfa_base + 12539 offsetof(struct shmem_lfa, additional_config), tmp_val); 12540 12541 lfa_sts = REG_RD(bp, params->lfa_base + 12542 offsetof(struct shmem_lfa, lfa_sts)); 12543 12544 /* Clear the "Don't Clear Statistics" bit, and set reason */ 12545 lfa_sts &= ~SHMEM_LFA_DONT_CLEAR_STAT; 12546 12547 /* Set link flap reason */ 12548 lfa_sts &= ~LFA_LINK_FLAP_REASON_MASK; 12549 lfa_sts |= ((lfa_status & LFA_LINK_FLAP_REASON_MASK) << 12550 LFA_LINK_FLAP_REASON_OFFSET); 12551 12552 /* Increment link flap counter */ 12553 lfa_sts = ((lfa_sts & ~LINK_FLAP_COUNT_MASK) | 12554 (((((lfa_sts & LINK_FLAP_COUNT_MASK) >> 12555 LINK_FLAP_COUNT_OFFSET) + 1) & 0xff) 12556 << LINK_FLAP_COUNT_OFFSET)); 12557 REG_WR(bp, params->lfa_base + 12558 offsetof(struct shmem_lfa, lfa_sts), lfa_sts); 12559 /* Proceed with regular link initialization */ 12560 } 12561 12562 int bnx2x_phy_init(struct link_params *params, struct link_vars *vars) 12563 { 12564 int lfa_status; 12565 struct bnx2x *bp = params->bp; 12566 DP(NETIF_MSG_LINK, "Phy Initialization started\n"); 12567 DP(NETIF_MSG_LINK, "(1) req_speed %d, req_flowctrl %d\n", 12568 params->req_line_speed[0], params->req_flow_ctrl[0]); 12569 DP(NETIF_MSG_LINK, "(2) req_speed %d, req_flowctrl %d\n", 12570 params->req_line_speed[1], params->req_flow_ctrl[1]); 12571 DP(NETIF_MSG_LINK, "req_adv_flow_ctrl 0x%x\n", params->req_fc_auto_adv); 12572 vars->link_status = 0; 12573 vars->phy_link_up = 0; 12574 vars->link_up = 0; 12575 vars->line_speed = 0; 12576 vars->duplex = DUPLEX_FULL; 12577 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; 12578 vars->mac_type = MAC_TYPE_NONE; 12579 vars->phy_flags = 0; 12580 vars->check_kr2_recovery_cnt = 0; 12581 params->link_flags = PHY_INITIALIZED; 12582 /* Driver opens NIG-BRB filters */ 12583 bnx2x_set_rx_filter(params, 1); 12584 /* Check if link flap can be avoided */ 12585 lfa_status = bnx2x_check_lfa(params); 12586 12587 if (lfa_status == 0) { 12588 DP(NETIF_MSG_LINK, "Link Flap Avoidance in progress\n"); 12589 return bnx2x_avoid_link_flap(params, vars); 12590 } 12591 12592 DP(NETIF_MSG_LINK, "Cannot avoid link flap lfa_sta=0x%x\n", 12593 lfa_status); 12594 bnx2x_cannot_avoid_link_flap(params, vars, lfa_status); 12595 12596 /* Disable attentions */ 12597 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4, 12598 (NIG_MASK_XGXS0_LINK_STATUS | 12599 NIG_MASK_XGXS0_LINK10G | 12600 NIG_MASK_SERDES0_LINK_STATUS | 12601 NIG_MASK_MI_INT)); 12602 12603 bnx2x_emac_init(params, vars); 12604 12605 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) 12606 vars->link_status |= LINK_STATUS_PFC_ENABLED; 12607 12608 if (params->num_phys == 0) { 12609 DP(NETIF_MSG_LINK, "No phy found for initialization !!\n"); 12610 return -EINVAL; 12611 } 12612 set_phy_vars(params, vars); 12613 12614 DP(NETIF_MSG_LINK, "Num of phys on board: %d\n", params->num_phys); 12615 switch (params->loopback_mode) { 12616 case LOOPBACK_BMAC: 12617 bnx2x_init_bmac_loopback(params, vars); 12618 break; 12619 case LOOPBACK_EMAC: 12620 bnx2x_init_emac_loopback(params, vars); 12621 break; 12622 case LOOPBACK_XMAC: 12623 bnx2x_init_xmac_loopback(params, vars); 12624 break; 12625 case LOOPBACK_UMAC: 12626 bnx2x_init_umac_loopback(params, vars); 12627 break; 12628 case LOOPBACK_XGXS: 12629 case LOOPBACK_EXT_PHY: 12630 bnx2x_init_xgxs_loopback(params, vars); 12631 break; 12632 default: 12633 if (!CHIP_IS_E3(bp)) { 12634 if (params->switch_cfg == SWITCH_CFG_10G) 12635 bnx2x_xgxs_deassert(params); 12636 else 12637 bnx2x_serdes_deassert(bp, params->port); 12638 } 12639 bnx2x_link_initialize(params, vars); 12640 msleep(30); 12641 bnx2x_link_int_enable(params); 12642 break; 12643 } 12644 bnx2x_update_mng(params, vars->link_status); 12645 12646 bnx2x_update_mng_eee(params, vars->eee_status); 12647 return 0; 12648 } 12649 12650 int bnx2x_link_reset(struct link_params *params, struct link_vars *vars, 12651 u8 reset_ext_phy) 12652 { 12653 struct bnx2x *bp = params->bp; 12654 u8 phy_index, port = params->port, clear_latch_ind = 0; 12655 DP(NETIF_MSG_LINK, "Resetting the link of port %d\n", port); 12656 /* Disable attentions */ 12657 vars->link_status = 0; 12658 bnx2x_update_mng(params, vars->link_status); 12659 vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK | 12660 SHMEM_EEE_ACTIVE_BIT); 12661 bnx2x_update_mng_eee(params, vars->eee_status); 12662 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 12663 (NIG_MASK_XGXS0_LINK_STATUS | 12664 NIG_MASK_XGXS0_LINK10G | 12665 NIG_MASK_SERDES0_LINK_STATUS | 12666 NIG_MASK_MI_INT)); 12667 12668 /* Activate nig drain */ 12669 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1); 12670 12671 /* Disable nig egress interface */ 12672 if (!CHIP_IS_E3(bp)) { 12673 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0); 12674 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0); 12675 } 12676 12677 if (!CHIP_IS_E3(bp)) { 12678 bnx2x_set_bmac_rx(bp, params->chip_id, port, 0); 12679 } else { 12680 bnx2x_set_xmac_rxtx(params, 0); 12681 bnx2x_set_umac_rxtx(params, 0); 12682 } 12683 /* Disable emac */ 12684 if (!CHIP_IS_E3(bp)) 12685 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0); 12686 12687 usleep_range(10000, 20000); 12688 /* The PHY reset is controlled by GPIO 1 12689 * Hold it as vars low 12690 */ 12691 /* Clear link led */ 12692 bnx2x_set_mdio_emac_per_phy(bp, params); 12693 bnx2x_set_led(params, vars, LED_MODE_OFF, 0); 12694 12695 if (reset_ext_phy) { 12696 for (phy_index = EXT_PHY1; phy_index < params->num_phys; 12697 phy_index++) { 12698 if (params->phy[phy_index].link_reset) { 12699 bnx2x_set_aer_mmd(params, 12700 ¶ms->phy[phy_index]); 12701 params->phy[phy_index].link_reset( 12702 ¶ms->phy[phy_index], 12703 params); 12704 } 12705 if (params->phy[phy_index].flags & 12706 FLAGS_REARM_LATCH_SIGNAL) 12707 clear_latch_ind = 1; 12708 } 12709 } 12710 12711 if (clear_latch_ind) { 12712 /* Clear latching indication */ 12713 bnx2x_rearm_latch_signal(bp, port, 0); 12714 bnx2x_bits_dis(bp, NIG_REG_LATCH_BC_0 + port*4, 12715 1 << NIG_LATCH_BC_ENABLE_MI_INT); 12716 } 12717 if (params->phy[INT_PHY].link_reset) 12718 params->phy[INT_PHY].link_reset( 12719 ¶ms->phy[INT_PHY], params); 12720 12721 /* Disable nig ingress interface */ 12722 if (!CHIP_IS_E3(bp)) { 12723 /* Reset BigMac */ 12724 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 12725 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); 12726 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0); 12727 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0); 12728 } else { 12729 u32 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; 12730 bnx2x_set_xumac_nig(params, 0, 0); 12731 if (REG_RD(bp, MISC_REG_RESET_REG_2) & 12732 MISC_REGISTERS_RESET_REG_2_XMAC) 12733 REG_WR(bp, xmac_base + XMAC_REG_CTRL, 12734 XMAC_CTRL_REG_SOFT_RESET); 12735 } 12736 vars->link_up = 0; 12737 vars->phy_flags = 0; 12738 return 0; 12739 } 12740 int bnx2x_lfa_reset(struct link_params *params, 12741 struct link_vars *vars) 12742 { 12743 struct bnx2x *bp = params->bp; 12744 vars->link_up = 0; 12745 vars->phy_flags = 0; 12746 params->link_flags &= ~PHY_INITIALIZED; 12747 if (!params->lfa_base) 12748 return bnx2x_link_reset(params, vars, 1); 12749 /* 12750 * Activate NIG drain so that during this time the device won't send 12751 * anything while it is unable to response. 12752 */ 12753 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1); 12754 12755 /* 12756 * Close gracefully the gate from BMAC to NIG such that no half packets 12757 * are passed. 12758 */ 12759 if (!CHIP_IS_E3(bp)) 12760 bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 0); 12761 12762 if (CHIP_IS_E3(bp)) { 12763 bnx2x_set_xmac_rxtx(params, 0); 12764 bnx2x_set_umac_rxtx(params, 0); 12765 } 12766 /* Wait 10ms for the pipe to clean up*/ 12767 usleep_range(10000, 20000); 12768 12769 /* Clean the NIG-BRB using the network filters in a way that will 12770 * not cut a packet in the middle. 12771 */ 12772 bnx2x_set_rx_filter(params, 0); 12773 12774 /* 12775 * Re-open the gate between the BMAC and the NIG, after verifying the 12776 * gate to the BRB is closed, otherwise packets may arrive to the 12777 * firmware before driver had initialized it. The target is to achieve 12778 * minimum management protocol down time. 12779 */ 12780 if (!CHIP_IS_E3(bp)) 12781 bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 1); 12782 12783 if (CHIP_IS_E3(bp)) { 12784 bnx2x_set_xmac_rxtx(params, 1); 12785 bnx2x_set_umac_rxtx(params, 1); 12786 } 12787 /* Disable NIG drain */ 12788 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); 12789 return 0; 12790 } 12791 12792 /****************************************************************************/ 12793 /* Common function */ 12794 /****************************************************************************/ 12795 static int bnx2x_8073_common_init_phy(struct bnx2x *bp, 12796 u32 shmem_base_path[], 12797 u32 shmem2_base_path[], u8 phy_index, 12798 u32 chip_id) 12799 { 12800 struct bnx2x_phy phy[PORT_MAX]; 12801 struct bnx2x_phy *phy_blk[PORT_MAX]; 12802 u16 val; 12803 s8 port = 0; 12804 s8 port_of_path = 0; 12805 u32 swap_val, swap_override; 12806 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); 12807 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); 12808 port ^= (swap_val && swap_override); 12809 bnx2x_ext_phy_hw_reset(bp, port); 12810 /* PART1 - Reset both phys */ 12811 for (port = PORT_MAX - 1; port >= PORT_0; port--) { 12812 u32 shmem_base, shmem2_base; 12813 /* In E2, same phy is using for port0 of the two paths */ 12814 if (CHIP_IS_E1x(bp)) { 12815 shmem_base = shmem_base_path[0]; 12816 shmem2_base = shmem2_base_path[0]; 12817 port_of_path = port; 12818 } else { 12819 shmem_base = shmem_base_path[port]; 12820 shmem2_base = shmem2_base_path[port]; 12821 port_of_path = 0; 12822 } 12823 12824 /* Extract the ext phy address for the port */ 12825 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base, 12826 port_of_path, &phy[port]) != 12827 0) { 12828 DP(NETIF_MSG_LINK, "populate_phy failed\n"); 12829 return -EINVAL; 12830 } 12831 /* Disable attentions */ 12832 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + 12833 port_of_path*4, 12834 (NIG_MASK_XGXS0_LINK_STATUS | 12835 NIG_MASK_XGXS0_LINK10G | 12836 NIG_MASK_SERDES0_LINK_STATUS | 12837 NIG_MASK_MI_INT)); 12838 12839 /* Need to take the phy out of low power mode in order 12840 * to write to access its registers 12841 */ 12842 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 12843 MISC_REGISTERS_GPIO_OUTPUT_HIGH, 12844 port); 12845 12846 /* Reset the phy */ 12847 bnx2x_cl45_write(bp, &phy[port], 12848 MDIO_PMA_DEVAD, 12849 MDIO_PMA_REG_CTRL, 12850 1<<15); 12851 } 12852 12853 /* Add delay of 150ms after reset */ 12854 msleep(150); 12855 12856 if (phy[PORT_0].addr & 0x1) { 12857 phy_blk[PORT_0] = &(phy[PORT_1]); 12858 phy_blk[PORT_1] = &(phy[PORT_0]); 12859 } else { 12860 phy_blk[PORT_0] = &(phy[PORT_0]); 12861 phy_blk[PORT_1] = &(phy[PORT_1]); 12862 } 12863 12864 /* PART2 - Download firmware to both phys */ 12865 for (port = PORT_MAX - 1; port >= PORT_0; port--) { 12866 if (CHIP_IS_E1x(bp)) 12867 port_of_path = port; 12868 else 12869 port_of_path = 0; 12870 12871 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n", 12872 phy_blk[port]->addr); 12873 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port], 12874 port_of_path)) 12875 return -EINVAL; 12876 12877 /* Only set bit 10 = 1 (Tx power down) */ 12878 bnx2x_cl45_read(bp, phy_blk[port], 12879 MDIO_PMA_DEVAD, 12880 MDIO_PMA_REG_TX_POWER_DOWN, &val); 12881 12882 /* Phase1 of TX_POWER_DOWN reset */ 12883 bnx2x_cl45_write(bp, phy_blk[port], 12884 MDIO_PMA_DEVAD, 12885 MDIO_PMA_REG_TX_POWER_DOWN, 12886 (val | 1<<10)); 12887 } 12888 12889 /* Toggle Transmitter: Power down and then up with 600ms delay 12890 * between 12891 */ 12892 msleep(600); 12893 12894 /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */ 12895 for (port = PORT_MAX - 1; port >= PORT_0; port--) { 12896 /* Phase2 of POWER_DOWN_RESET */ 12897 /* Release bit 10 (Release Tx power down) */ 12898 bnx2x_cl45_read(bp, phy_blk[port], 12899 MDIO_PMA_DEVAD, 12900 MDIO_PMA_REG_TX_POWER_DOWN, &val); 12901 12902 bnx2x_cl45_write(bp, phy_blk[port], 12903 MDIO_PMA_DEVAD, 12904 MDIO_PMA_REG_TX_POWER_DOWN, (val & (~(1<<10)))); 12905 usleep_range(15000, 30000); 12906 12907 /* Read modify write the SPI-ROM version select register */ 12908 bnx2x_cl45_read(bp, phy_blk[port], 12909 MDIO_PMA_DEVAD, 12910 MDIO_PMA_REG_EDC_FFE_MAIN, &val); 12911 bnx2x_cl45_write(bp, phy_blk[port], 12912 MDIO_PMA_DEVAD, 12913 MDIO_PMA_REG_EDC_FFE_MAIN, (val | (1<<12))); 12914 12915 /* set GPIO2 back to LOW */ 12916 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 12917 MISC_REGISTERS_GPIO_OUTPUT_LOW, port); 12918 } 12919 return 0; 12920 } 12921 static int bnx2x_8726_common_init_phy(struct bnx2x *bp, 12922 u32 shmem_base_path[], 12923 u32 shmem2_base_path[], u8 phy_index, 12924 u32 chip_id) 12925 { 12926 u32 val; 12927 s8 port; 12928 struct bnx2x_phy phy; 12929 /* Use port1 because of the static port-swap */ 12930 /* Enable the module detection interrupt */ 12931 val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN); 12932 val |= ((1<<MISC_REGISTERS_GPIO_3)| 12933 (1<<(MISC_REGISTERS_GPIO_3 + MISC_REGISTERS_GPIO_PORT_SHIFT))); 12934 REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val); 12935 12936 bnx2x_ext_phy_hw_reset(bp, 0); 12937 usleep_range(5000, 10000); 12938 for (port = 0; port < PORT_MAX; port++) { 12939 u32 shmem_base, shmem2_base; 12940 12941 /* In E2, same phy is using for port0 of the two paths */ 12942 if (CHIP_IS_E1x(bp)) { 12943 shmem_base = shmem_base_path[0]; 12944 shmem2_base = shmem2_base_path[0]; 12945 } else { 12946 shmem_base = shmem_base_path[port]; 12947 shmem2_base = shmem2_base_path[port]; 12948 } 12949 /* Extract the ext phy address for the port */ 12950 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base, 12951 port, &phy) != 12952 0) { 12953 DP(NETIF_MSG_LINK, "populate phy failed\n"); 12954 return -EINVAL; 12955 } 12956 12957 /* Reset phy*/ 12958 bnx2x_cl45_write(bp, &phy, 12959 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001); 12960 12961 12962 /* Set fault module detected LED on */ 12963 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0, 12964 MISC_REGISTERS_GPIO_HIGH, 12965 port); 12966 } 12967 12968 return 0; 12969 } 12970 static void bnx2x_get_ext_phy_reset_gpio(struct bnx2x *bp, u32 shmem_base, 12971 u8 *io_gpio, u8 *io_port) 12972 { 12973 12974 u32 phy_gpio_reset = REG_RD(bp, shmem_base + 12975 offsetof(struct shmem_region, 12976 dev_info.port_hw_config[PORT_0].default_cfg)); 12977 switch (phy_gpio_reset) { 12978 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0: 12979 *io_gpio = 0; 12980 *io_port = 0; 12981 break; 12982 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0: 12983 *io_gpio = 1; 12984 *io_port = 0; 12985 break; 12986 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0: 12987 *io_gpio = 2; 12988 *io_port = 0; 12989 break; 12990 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0: 12991 *io_gpio = 3; 12992 *io_port = 0; 12993 break; 12994 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1: 12995 *io_gpio = 0; 12996 *io_port = 1; 12997 break; 12998 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1: 12999 *io_gpio = 1; 13000 *io_port = 1; 13001 break; 13002 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1: 13003 *io_gpio = 2; 13004 *io_port = 1; 13005 break; 13006 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1: 13007 *io_gpio = 3; 13008 *io_port = 1; 13009 break; 13010 default: 13011 /* Don't override the io_gpio and io_port */ 13012 break; 13013 } 13014 } 13015 13016 static int bnx2x_8727_common_init_phy(struct bnx2x *bp, 13017 u32 shmem_base_path[], 13018 u32 shmem2_base_path[], u8 phy_index, 13019 u32 chip_id) 13020 { 13021 s8 port, reset_gpio; 13022 u32 swap_val, swap_override; 13023 struct bnx2x_phy phy[PORT_MAX]; 13024 struct bnx2x_phy *phy_blk[PORT_MAX]; 13025 s8 port_of_path; 13026 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); 13027 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); 13028 13029 reset_gpio = MISC_REGISTERS_GPIO_1; 13030 port = 1; 13031 13032 /* Retrieve the reset gpio/port which control the reset. 13033 * Default is GPIO1, PORT1 13034 */ 13035 bnx2x_get_ext_phy_reset_gpio(bp, shmem_base_path[0], 13036 (u8 *)&reset_gpio, (u8 *)&port); 13037 13038 /* Calculate the port based on port swap */ 13039 port ^= (swap_val && swap_override); 13040 13041 /* Initiate PHY reset*/ 13042 bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_LOW, 13043 port); 13044 usleep_range(1000, 2000); 13045 bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_HIGH, 13046 port); 13047 13048 usleep_range(5000, 10000); 13049 13050 /* PART1 - Reset both phys */ 13051 for (port = PORT_MAX - 1; port >= PORT_0; port--) { 13052 u32 shmem_base, shmem2_base; 13053 13054 /* In E2, same phy is using for port0 of the two paths */ 13055 if (CHIP_IS_E1x(bp)) { 13056 shmem_base = shmem_base_path[0]; 13057 shmem2_base = shmem2_base_path[0]; 13058 port_of_path = port; 13059 } else { 13060 shmem_base = shmem_base_path[port]; 13061 shmem2_base = shmem2_base_path[port]; 13062 port_of_path = 0; 13063 } 13064 13065 /* Extract the ext phy address for the port */ 13066 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base, 13067 port_of_path, &phy[port]) != 13068 0) { 13069 DP(NETIF_MSG_LINK, "populate phy failed\n"); 13070 return -EINVAL; 13071 } 13072 /* disable attentions */ 13073 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + 13074 port_of_path*4, 13075 (NIG_MASK_XGXS0_LINK_STATUS | 13076 NIG_MASK_XGXS0_LINK10G | 13077 NIG_MASK_SERDES0_LINK_STATUS | 13078 NIG_MASK_MI_INT)); 13079 13080 13081 /* Reset the phy */ 13082 bnx2x_cl45_write(bp, &phy[port], 13083 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15); 13084 } 13085 13086 /* Add delay of 150ms after reset */ 13087 msleep(150); 13088 if (phy[PORT_0].addr & 0x1) { 13089 phy_blk[PORT_0] = &(phy[PORT_1]); 13090 phy_blk[PORT_1] = &(phy[PORT_0]); 13091 } else { 13092 phy_blk[PORT_0] = &(phy[PORT_0]); 13093 phy_blk[PORT_1] = &(phy[PORT_1]); 13094 } 13095 /* PART2 - Download firmware to both phys */ 13096 for (port = PORT_MAX - 1; port >= PORT_0; port--) { 13097 if (CHIP_IS_E1x(bp)) 13098 port_of_path = port; 13099 else 13100 port_of_path = 0; 13101 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n", 13102 phy_blk[port]->addr); 13103 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port], 13104 port_of_path)) 13105 return -EINVAL; 13106 /* Disable PHY transmitter output */ 13107 bnx2x_cl45_write(bp, phy_blk[port], 13108 MDIO_PMA_DEVAD, 13109 MDIO_PMA_REG_TX_DISABLE, 1); 13110 13111 } 13112 return 0; 13113 } 13114 13115 static int bnx2x_84833_common_init_phy(struct bnx2x *bp, 13116 u32 shmem_base_path[], 13117 u32 shmem2_base_path[], 13118 u8 phy_index, 13119 u32 chip_id) 13120 { 13121 u8 reset_gpios; 13122 reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path, chip_id); 13123 bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW); 13124 udelay(10); 13125 bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_HIGH); 13126 DP(NETIF_MSG_LINK, "84833 reset pulse on pin values 0x%x\n", 13127 reset_gpios); 13128 return 0; 13129 } 13130 13131 static int bnx2x_ext_phy_common_init(struct bnx2x *bp, u32 shmem_base_path[], 13132 u32 shmem2_base_path[], u8 phy_index, 13133 u32 ext_phy_type, u32 chip_id) 13134 { 13135 int rc = 0; 13136 13137 switch (ext_phy_type) { 13138 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073: 13139 rc = bnx2x_8073_common_init_phy(bp, shmem_base_path, 13140 shmem2_base_path, 13141 phy_index, chip_id); 13142 break; 13143 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722: 13144 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: 13145 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC: 13146 rc = bnx2x_8727_common_init_phy(bp, shmem_base_path, 13147 shmem2_base_path, 13148 phy_index, chip_id); 13149 break; 13150 13151 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: 13152 /* GPIO1 affects both ports, so there's need to pull 13153 * it for single port alone 13154 */ 13155 rc = bnx2x_8726_common_init_phy(bp, shmem_base_path, 13156 shmem2_base_path, 13157 phy_index, chip_id); 13158 break; 13159 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833: 13160 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834: 13161 /* GPIO3's are linked, and so both need to be toggled 13162 * to obtain required 2us pulse. 13163 */ 13164 rc = bnx2x_84833_common_init_phy(bp, shmem_base_path, 13165 shmem2_base_path, 13166 phy_index, chip_id); 13167 break; 13168 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE: 13169 rc = -EINVAL; 13170 break; 13171 default: 13172 DP(NETIF_MSG_LINK, 13173 "ext_phy 0x%x common init not required\n", 13174 ext_phy_type); 13175 break; 13176 } 13177 13178 if (rc) 13179 netdev_err(bp->dev, "Warning: PHY was not initialized," 13180 " Port %d\n", 13181 0); 13182 return rc; 13183 } 13184 13185 int bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base_path[], 13186 u32 shmem2_base_path[], u32 chip_id) 13187 { 13188 int rc = 0; 13189 u32 phy_ver, val; 13190 u8 phy_index = 0; 13191 u32 ext_phy_type, ext_phy_config; 13192 13193 bnx2x_set_mdio_clk(bp, chip_id, GRCBASE_EMAC0); 13194 bnx2x_set_mdio_clk(bp, chip_id, GRCBASE_EMAC1); 13195 DP(NETIF_MSG_LINK, "Begin common phy init\n"); 13196 if (CHIP_IS_E3(bp)) { 13197 /* Enable EPIO */ 13198 val = REG_RD(bp, MISC_REG_GEN_PURP_HWG); 13199 REG_WR(bp, MISC_REG_GEN_PURP_HWG, val | 1); 13200 } 13201 /* Check if common init was already done */ 13202 phy_ver = REG_RD(bp, shmem_base_path[0] + 13203 offsetof(struct shmem_region, 13204 port_mb[PORT_0].ext_phy_fw_version)); 13205 if (phy_ver) { 13206 DP(NETIF_MSG_LINK, "Not doing common init; phy ver is 0x%x\n", 13207 phy_ver); 13208 return 0; 13209 } 13210 13211 /* Read the ext_phy_type for arbitrary port(0) */ 13212 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS; 13213 phy_index++) { 13214 ext_phy_config = bnx2x_get_ext_phy_config(bp, 13215 shmem_base_path[0], 13216 phy_index, 0); 13217 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config); 13218 rc |= bnx2x_ext_phy_common_init(bp, shmem_base_path, 13219 shmem2_base_path, 13220 phy_index, ext_phy_type, 13221 chip_id); 13222 } 13223 return rc; 13224 } 13225 13226 static void bnx2x_check_over_curr(struct link_params *params, 13227 struct link_vars *vars) 13228 { 13229 struct bnx2x *bp = params->bp; 13230 u32 cfg_pin; 13231 u8 port = params->port; 13232 u32 pin_val; 13233 13234 cfg_pin = (REG_RD(bp, params->shmem_base + 13235 offsetof(struct shmem_region, 13236 dev_info.port_hw_config[port].e3_cmn_pin_cfg1)) & 13237 PORT_HW_CFG_E3_OVER_CURRENT_MASK) >> 13238 PORT_HW_CFG_E3_OVER_CURRENT_SHIFT; 13239 13240 /* Ignore check if no external input PIN available */ 13241 if (bnx2x_get_cfg_pin(bp, cfg_pin, &pin_val) != 0) 13242 return; 13243 13244 if (!pin_val) { 13245 if ((vars->phy_flags & PHY_OVER_CURRENT_FLAG) == 0) { 13246 netdev_err(bp->dev, "Error: Power fault on Port %d has" 13247 " been detected and the power to " 13248 "that SFP+ module has been removed" 13249 " to prevent failure of the card." 13250 " Please remove the SFP+ module and" 13251 " restart the system to clear this" 13252 " error.\n", 13253 params->port); 13254 vars->phy_flags |= PHY_OVER_CURRENT_FLAG; 13255 bnx2x_warpcore_power_module(params, 0); 13256 } 13257 } else 13258 vars->phy_flags &= ~PHY_OVER_CURRENT_FLAG; 13259 } 13260 13261 /* Returns 0 if no change occured since last check; 1 otherwise. */ 13262 static u8 bnx2x_analyze_link_error(struct link_params *params, 13263 struct link_vars *vars, u32 status, 13264 u32 phy_flag, u32 link_flag, u8 notify) 13265 { 13266 struct bnx2x *bp = params->bp; 13267 /* Compare new value with previous value */ 13268 u8 led_mode; 13269 u32 old_status = (vars->phy_flags & phy_flag) ? 1 : 0; 13270 13271 if ((status ^ old_status) == 0) 13272 return 0; 13273 13274 /* If values differ */ 13275 switch (phy_flag) { 13276 case PHY_HALF_OPEN_CONN_FLAG: 13277 DP(NETIF_MSG_LINK, "Analyze Remote Fault\n"); 13278 break; 13279 case PHY_SFP_TX_FAULT_FLAG: 13280 DP(NETIF_MSG_LINK, "Analyze TX Fault\n"); 13281 break; 13282 default: 13283 DP(NETIF_MSG_LINK, "Analyze UNKNOWN\n"); 13284 } 13285 DP(NETIF_MSG_LINK, "Link changed:[%x %x]->%x\n", vars->link_up, 13286 old_status, status); 13287 13288 /* a. Update shmem->link_status accordingly 13289 * b. Update link_vars->link_up 13290 */ 13291 if (status) { 13292 vars->link_status &= ~LINK_STATUS_LINK_UP; 13293 vars->link_status |= link_flag; 13294 vars->link_up = 0; 13295 vars->phy_flags |= phy_flag; 13296 13297 /* activate nig drain */ 13298 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1); 13299 /* Set LED mode to off since the PHY doesn't know about these 13300 * errors 13301 */ 13302 led_mode = LED_MODE_OFF; 13303 } else { 13304 vars->link_status |= LINK_STATUS_LINK_UP; 13305 vars->link_status &= ~link_flag; 13306 vars->link_up = 1; 13307 vars->phy_flags &= ~phy_flag; 13308 led_mode = LED_MODE_OPER; 13309 13310 /* Clear nig drain */ 13311 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); 13312 } 13313 bnx2x_sync_link(params, vars); 13314 /* Update the LED according to the link state */ 13315 bnx2x_set_led(params, vars, led_mode, SPEED_10000); 13316 13317 /* Update link status in the shared memory */ 13318 bnx2x_update_mng(params, vars->link_status); 13319 13320 /* C. Trigger General Attention */ 13321 vars->periodic_flags |= PERIODIC_FLAGS_LINK_EVENT; 13322 if (notify) 13323 bnx2x_notify_link_changed(bp); 13324 13325 return 1; 13326 } 13327 13328 /****************************************************************************** 13329 * Description: 13330 * This function checks for half opened connection change indication. 13331 * When such change occurs, it calls the bnx2x_analyze_link_error 13332 * to check if Remote Fault is set or cleared. Reception of remote fault 13333 * status message in the MAC indicates that the peer's MAC has detected 13334 * a fault, for example, due to break in the TX side of fiber. 13335 * 13336 ******************************************************************************/ 13337 int bnx2x_check_half_open_conn(struct link_params *params, 13338 struct link_vars *vars, 13339 u8 notify) 13340 { 13341 struct bnx2x *bp = params->bp; 13342 u32 lss_status = 0; 13343 u32 mac_base; 13344 /* In case link status is physically up @ 10G do */ 13345 if (((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0) || 13346 (REG_RD(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4))) 13347 return 0; 13348 13349 if (CHIP_IS_E3(bp) && 13350 (REG_RD(bp, MISC_REG_RESET_REG_2) & 13351 (MISC_REGISTERS_RESET_REG_2_XMAC))) { 13352 /* Check E3 XMAC */ 13353 /* Note that link speed cannot be queried here, since it may be 13354 * zero while link is down. In case UMAC is active, LSS will 13355 * simply not be set 13356 */ 13357 mac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; 13358 13359 /* Clear stick bits (Requires rising edge) */ 13360 REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0); 13361 REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 13362 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS | 13363 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS); 13364 if (REG_RD(bp, mac_base + XMAC_REG_RX_LSS_STATUS)) 13365 lss_status = 1; 13366 13367 bnx2x_analyze_link_error(params, vars, lss_status, 13368 PHY_HALF_OPEN_CONN_FLAG, 13369 LINK_STATUS_NONE, notify); 13370 } else if (REG_RD(bp, MISC_REG_RESET_REG_2) & 13371 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port)) { 13372 /* Check E1X / E2 BMAC */ 13373 u32 lss_status_reg; 13374 u32 wb_data[2]; 13375 mac_base = params->port ? NIG_REG_INGRESS_BMAC1_MEM : 13376 NIG_REG_INGRESS_BMAC0_MEM; 13377 /* Read BIGMAC_REGISTER_RX_LSS_STATUS */ 13378 if (CHIP_IS_E2(bp)) 13379 lss_status_reg = BIGMAC2_REGISTER_RX_LSS_STAT; 13380 else 13381 lss_status_reg = BIGMAC_REGISTER_RX_LSS_STATUS; 13382 13383 REG_RD_DMAE(bp, mac_base + lss_status_reg, wb_data, 2); 13384 lss_status = (wb_data[0] > 0); 13385 13386 bnx2x_analyze_link_error(params, vars, lss_status, 13387 PHY_HALF_OPEN_CONN_FLAG, 13388 LINK_STATUS_NONE, notify); 13389 } 13390 return 0; 13391 } 13392 static void bnx2x_sfp_tx_fault_detection(struct bnx2x_phy *phy, 13393 struct link_params *params, 13394 struct link_vars *vars) 13395 { 13396 struct bnx2x *bp = params->bp; 13397 u32 cfg_pin, value = 0; 13398 u8 led_change, port = params->port; 13399 13400 /* Get The SFP+ TX_Fault controlling pin ([eg]pio) */ 13401 cfg_pin = (REG_RD(bp, params->shmem_base + offsetof(struct shmem_region, 13402 dev_info.port_hw_config[port].e3_cmn_pin_cfg)) & 13403 PORT_HW_CFG_E3_TX_FAULT_MASK) >> 13404 PORT_HW_CFG_E3_TX_FAULT_SHIFT; 13405 13406 if (bnx2x_get_cfg_pin(bp, cfg_pin, &value)) { 13407 DP(NETIF_MSG_LINK, "Failed to read pin 0x%02x\n", cfg_pin); 13408 return; 13409 } 13410 13411 led_change = bnx2x_analyze_link_error(params, vars, value, 13412 PHY_SFP_TX_FAULT_FLAG, 13413 LINK_STATUS_SFP_TX_FAULT, 1); 13414 13415 if (led_change) { 13416 /* Change TX_Fault led, set link status for further syncs */ 13417 u8 led_mode; 13418 13419 if (vars->phy_flags & PHY_SFP_TX_FAULT_FLAG) { 13420 led_mode = MISC_REGISTERS_GPIO_HIGH; 13421 vars->link_status |= LINK_STATUS_SFP_TX_FAULT; 13422 } else { 13423 led_mode = MISC_REGISTERS_GPIO_LOW; 13424 vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT; 13425 } 13426 13427 /* If module is unapproved, led should be on regardless */ 13428 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED)) { 13429 DP(NETIF_MSG_LINK, "Change TX_Fault LED: ->%x\n", 13430 led_mode); 13431 bnx2x_set_e3_module_fault_led(params, led_mode); 13432 } 13433 } 13434 } 13435 static void bnx2x_disable_kr2(struct link_params *params, 13436 struct link_vars *vars, 13437 struct bnx2x_phy *phy) 13438 { 13439 struct bnx2x *bp = params->bp; 13440 int i; 13441 static struct bnx2x_reg_set reg_set[] = { 13442 /* Step 1 - Program the TX/RX alignment markers */ 13443 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL5, 0x7690}, 13444 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL7, 0xe647}, 13445 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL6, 0xc4f0}, 13446 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL9, 0x7690}, 13447 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL11, 0xe647}, 13448 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL10, 0xc4f0}, 13449 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_USERB0_CTRL, 0x000c}, 13450 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL1, 0x6000}, 13451 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL3, 0x0000}, 13452 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CODE_FIELD, 0x0002}, 13453 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI1, 0x0000}, 13454 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI2, 0x0af7}, 13455 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI3, 0x0af7}, 13456 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0002}, 13457 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0000} 13458 }; 13459 DP(NETIF_MSG_LINK, "Disabling 20G-KR2\n"); 13460 13461 for (i = 0; i < ARRAY_SIZE(reg_set); i++) 13462 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg, 13463 reg_set[i].val); 13464 vars->link_attr_sync &= ~LINK_ATTR_SYNC_KR2_ENABLE; 13465 bnx2x_update_link_attr(params, vars->link_attr_sync); 13466 13467 vars->check_kr2_recovery_cnt = CHECK_KR2_RECOVERY_CNT; 13468 /* Restart AN on leading lane */ 13469 bnx2x_warpcore_restart_AN_KR(phy, params); 13470 } 13471 13472 static void bnx2x_kr2_recovery(struct link_params *params, 13473 struct link_vars *vars, 13474 struct bnx2x_phy *phy) 13475 { 13476 struct bnx2x *bp = params->bp; 13477 DP(NETIF_MSG_LINK, "KR2 recovery\n"); 13478 bnx2x_warpcore_enable_AN_KR2(phy, params, vars); 13479 bnx2x_warpcore_restart_AN_KR(phy, params); 13480 } 13481 13482 static void bnx2x_check_kr2_wa(struct link_params *params, 13483 struct link_vars *vars, 13484 struct bnx2x_phy *phy) 13485 { 13486 struct bnx2x *bp = params->bp; 13487 u16 base_page, next_page, not_kr2_device, lane; 13488 int sigdet; 13489 13490 /* Once KR2 was disabled, wait 5 seconds before checking KR2 recovery 13491 * Since some switches tend to reinit the AN process and clear the 13492 * the advertised BP/NP after ~2 seconds causing the KR2 to be disabled 13493 * and recovered many times 13494 */ 13495 if (vars->check_kr2_recovery_cnt > 0) { 13496 vars->check_kr2_recovery_cnt--; 13497 return; 13498 } 13499 13500 sigdet = bnx2x_warpcore_get_sigdet(phy, params); 13501 if (!sigdet) { 13502 if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) { 13503 bnx2x_kr2_recovery(params, vars, phy); 13504 DP(NETIF_MSG_LINK, "No sigdet\n"); 13505 } 13506 return; 13507 } 13508 13509 lane = bnx2x_get_warpcore_lane(phy, params); 13510 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, 13511 MDIO_AER_BLOCK_AER_REG, lane); 13512 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, 13513 MDIO_AN_REG_LP_AUTO_NEG, &base_page); 13514 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, 13515 MDIO_AN_REG_LP_AUTO_NEG2, &next_page); 13516 bnx2x_set_aer_mmd(params, phy); 13517 13518 /* CL73 has not begun yet */ 13519 if (base_page == 0) { 13520 if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) { 13521 bnx2x_kr2_recovery(params, vars, phy); 13522 DP(NETIF_MSG_LINK, "No BP\n"); 13523 } 13524 return; 13525 } 13526 13527 /* In case NP bit is not set in the BasePage, or it is set, 13528 * but only KX is advertised, declare this link partner as non-KR2 13529 * device. 13530 */ 13531 not_kr2_device = (((base_page & 0x8000) == 0) || 13532 (((base_page & 0x8000) && 13533 ((next_page & 0xe0) == 0x2)))); 13534 13535 /* In case KR2 is already disabled, check if we need to re-enable it */ 13536 if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) { 13537 if (!not_kr2_device) { 13538 DP(NETIF_MSG_LINK, "BP=0x%x, NP=0x%x\n", base_page, 13539 next_page); 13540 bnx2x_kr2_recovery(params, vars, phy); 13541 } 13542 return; 13543 } 13544 /* KR2 is enabled, but not KR2 device */ 13545 if (not_kr2_device) { 13546 /* Disable KR2 on both lanes */ 13547 DP(NETIF_MSG_LINK, "BP=0x%x, NP=0x%x\n", base_page, next_page); 13548 bnx2x_disable_kr2(params, vars, phy); 13549 return; 13550 } 13551 } 13552 13553 void bnx2x_period_func(struct link_params *params, struct link_vars *vars) 13554 { 13555 u16 phy_idx; 13556 struct bnx2x *bp = params->bp; 13557 for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) { 13558 if (params->phy[phy_idx].flags & FLAGS_TX_ERROR_CHECK) { 13559 bnx2x_set_aer_mmd(params, ¶ms->phy[phy_idx]); 13560 if (bnx2x_check_half_open_conn(params, vars, 1) != 13561 0) 13562 DP(NETIF_MSG_LINK, "Fault detection failed\n"); 13563 break; 13564 } 13565 } 13566 13567 if (CHIP_IS_E3(bp)) { 13568 struct bnx2x_phy *phy = ¶ms->phy[INT_PHY]; 13569 bnx2x_set_aer_mmd(params, phy); 13570 if ((phy->supported & SUPPORTED_20000baseKR2_Full) && 13571 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) 13572 bnx2x_check_kr2_wa(params, vars, phy); 13573 bnx2x_check_over_curr(params, vars); 13574 if (vars->rx_tx_asic_rst) 13575 bnx2x_warpcore_config_runtime(phy, params, vars); 13576 13577 if ((REG_RD(bp, params->shmem_base + 13578 offsetof(struct shmem_region, dev_info. 13579 port_hw_config[params->port].default_cfg)) 13580 & PORT_HW_CFG_NET_SERDES_IF_MASK) == 13581 PORT_HW_CFG_NET_SERDES_IF_SFI) { 13582 if (bnx2x_is_sfp_module_plugged(phy, params)) { 13583 bnx2x_sfp_tx_fault_detection(phy, params, vars); 13584 } else if (vars->link_status & 13585 LINK_STATUS_SFP_TX_FAULT) { 13586 /* Clean trail, interrupt corrects the leds */ 13587 vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT; 13588 vars->phy_flags &= ~PHY_SFP_TX_FAULT_FLAG; 13589 /* Update link status in the shared memory */ 13590 bnx2x_update_mng(params, vars->link_status); 13591 } 13592 } 13593 } 13594 } 13595 13596 u8 bnx2x_fan_failure_det_req(struct bnx2x *bp, 13597 u32 shmem_base, 13598 u32 shmem2_base, 13599 u8 port) 13600 { 13601 u8 phy_index, fan_failure_det_req = 0; 13602 struct bnx2x_phy phy; 13603 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS; 13604 phy_index++) { 13605 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base, 13606 port, &phy) 13607 != 0) { 13608 DP(NETIF_MSG_LINK, "populate phy failed\n"); 13609 return 0; 13610 } 13611 fan_failure_det_req |= (phy.flags & 13612 FLAGS_FAN_FAILURE_DET_REQ); 13613 } 13614 return fan_failure_det_req; 13615 } 13616 13617 void bnx2x_hw_reset_phy(struct link_params *params) 13618 { 13619 u8 phy_index; 13620 struct bnx2x *bp = params->bp; 13621 bnx2x_update_mng(params, 0); 13622 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4, 13623 (NIG_MASK_XGXS0_LINK_STATUS | 13624 NIG_MASK_XGXS0_LINK10G | 13625 NIG_MASK_SERDES0_LINK_STATUS | 13626 NIG_MASK_MI_INT)); 13627 13628 for (phy_index = INT_PHY; phy_index < MAX_PHYS; 13629 phy_index++) { 13630 if (params->phy[phy_index].hw_reset) { 13631 params->phy[phy_index].hw_reset( 13632 ¶ms->phy[phy_index], 13633 params); 13634 params->phy[phy_index] = phy_null; 13635 } 13636 } 13637 } 13638 13639 void bnx2x_init_mod_abs_int(struct bnx2x *bp, struct link_vars *vars, 13640 u32 chip_id, u32 shmem_base, u32 shmem2_base, 13641 u8 port) 13642 { 13643 u8 gpio_num = 0xff, gpio_port = 0xff, phy_index; 13644 u32 val; 13645 u32 offset, aeu_mask, swap_val, swap_override, sync_offset; 13646 if (CHIP_IS_E3(bp)) { 13647 if (bnx2x_get_mod_abs_int_cfg(bp, chip_id, 13648 shmem_base, 13649 port, 13650 &gpio_num, 13651 &gpio_port) != 0) 13652 return; 13653 } else { 13654 struct bnx2x_phy phy; 13655 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS; 13656 phy_index++) { 13657 if (bnx2x_populate_phy(bp, phy_index, shmem_base, 13658 shmem2_base, port, &phy) 13659 != 0) { 13660 DP(NETIF_MSG_LINK, "populate phy failed\n"); 13661 return; 13662 } 13663 if (phy.type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) { 13664 gpio_num = MISC_REGISTERS_GPIO_3; 13665 gpio_port = port; 13666 break; 13667 } 13668 } 13669 } 13670 13671 if (gpio_num == 0xff) 13672 return; 13673 13674 /* Set GPIO3 to trigger SFP+ module insertion/removal */ 13675 bnx2x_set_gpio(bp, gpio_num, MISC_REGISTERS_GPIO_INPUT_HI_Z, gpio_port); 13676 13677 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); 13678 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); 13679 gpio_port ^= (swap_val && swap_override); 13680 13681 vars->aeu_int_mask = AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 << 13682 (gpio_num + (gpio_port << 2)); 13683 13684 sync_offset = shmem_base + 13685 offsetof(struct shmem_region, 13686 dev_info.port_hw_config[port].aeu_int_mask); 13687 REG_WR(bp, sync_offset, vars->aeu_int_mask); 13688 13689 DP(NETIF_MSG_LINK, "Setting MOD_ABS (GPIO%d_P%d) AEU to 0x%x\n", 13690 gpio_num, gpio_port, vars->aeu_int_mask); 13691 13692 if (port == 0) 13693 offset = MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0; 13694 else 13695 offset = MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0; 13696 13697 /* Open appropriate AEU for interrupts */ 13698 aeu_mask = REG_RD(bp, offset); 13699 aeu_mask |= vars->aeu_int_mask; 13700 REG_WR(bp, offset, aeu_mask); 13701 13702 /* Enable the GPIO to trigger interrupt */ 13703 val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN); 13704 val |= 1 << (gpio_num + (gpio_port << 2)); 13705 REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val); 13706 } 13707