1 /* Copyright 2008-2012 Broadcom Corporation 2 * 3 * Unless you and Broadcom execute a separate written software license 4 * agreement governing use of this software, this software is licensed to you 5 * under the terms of the GNU General Public License version 2, available 6 * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL"). 7 * 8 * Notwithstanding the above, under no circumstances may you combine this 9 * software in any way with any other Broadcom software provided under a 10 * license other than the GPL, without Broadcom's express prior written 11 * consent. 12 * 13 * Written by Yaniv Rosner 14 * 15 */ 16 17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 18 19 #include <linux/kernel.h> 20 #include <linux/errno.h> 21 #include <linux/pci.h> 22 #include <linux/netdevice.h> 23 #include <linux/delay.h> 24 #include <linux/ethtool.h> 25 #include <linux/mutex.h> 26 27 #include "bnx2x.h" 28 #include "bnx2x_cmn.h" 29 30 /********************************************************/ 31 #define ETH_HLEN 14 32 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */ 33 #define ETH_OVREHEAD (ETH_HLEN + 8 + 8) 34 #define ETH_MIN_PACKET_SIZE 60 35 #define ETH_MAX_PACKET_SIZE 1500 36 #define ETH_MAX_JUMBO_PACKET_SIZE 9600 37 #define MDIO_ACCESS_TIMEOUT 1000 38 #define WC_LANE_MAX 4 39 #define I2C_SWITCH_WIDTH 2 40 #define I2C_BSC0 0 41 #define I2C_BSC1 1 42 #define I2C_WA_RETRY_CNT 3 43 #define I2C_WA_PWR_ITER (I2C_WA_RETRY_CNT - 1) 44 #define MCPR_IMC_COMMAND_READ_OP 1 45 #define MCPR_IMC_COMMAND_WRITE_OP 2 46 47 /* LED Blink rate that will achieve ~15.9Hz */ 48 #define LED_BLINK_RATE_VAL_E3 354 49 #define LED_BLINK_RATE_VAL_E1X_E2 480 50 /***********************************************************/ 51 /* Shortcut definitions */ 52 /***********************************************************/ 53 54 #define NIG_LATCH_BC_ENABLE_MI_INT 0 55 56 #define NIG_STATUS_EMAC0_MI_INT \ 57 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT 58 #define NIG_STATUS_XGXS0_LINK10G \ 59 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G 60 #define NIG_STATUS_XGXS0_LINK_STATUS \ 61 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS 62 #define NIG_STATUS_XGXS0_LINK_STATUS_SIZE \ 63 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE 64 #define NIG_STATUS_SERDES0_LINK_STATUS \ 65 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS 66 #define NIG_MASK_MI_INT \ 67 NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT 68 #define NIG_MASK_XGXS0_LINK10G \ 69 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G 70 #define NIG_MASK_XGXS0_LINK_STATUS \ 71 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS 72 #define NIG_MASK_SERDES0_LINK_STATUS \ 73 NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS 74 75 #define MDIO_AN_CL73_OR_37_COMPLETE \ 76 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \ 77 MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE) 78 79 #define XGXS_RESET_BITS \ 80 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW | \ 81 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ | \ 82 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN | \ 83 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \ 84 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB) 85 86 #define SERDES_RESET_BITS \ 87 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \ 88 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ | \ 89 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN | \ 90 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD) 91 92 #define AUTONEG_CL37 SHARED_HW_CFG_AN_ENABLE_CL37 93 #define AUTONEG_CL73 SHARED_HW_CFG_AN_ENABLE_CL73 94 #define AUTONEG_BAM SHARED_HW_CFG_AN_ENABLE_BAM 95 #define AUTONEG_PARALLEL \ 96 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION 97 #define AUTONEG_SGMII_FIBER_AUTODET \ 98 SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT 99 #define AUTONEG_REMOTE_PHY SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY 100 101 #define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \ 102 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE 103 #define GP_STATUS_PAUSE_RSOLUTION_RXSIDE \ 104 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE 105 #define GP_STATUS_SPEED_MASK \ 106 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK 107 #define GP_STATUS_10M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M 108 #define GP_STATUS_100M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M 109 #define GP_STATUS_1G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G 110 #define GP_STATUS_2_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G 111 #define GP_STATUS_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G 112 #define GP_STATUS_6G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G 113 #define GP_STATUS_10G_HIG \ 114 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG 115 #define GP_STATUS_10G_CX4 \ 116 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4 117 #define GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX 118 #define GP_STATUS_10G_KX4 \ 119 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4 120 #define GP_STATUS_10G_KR MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR 121 #define GP_STATUS_10G_XFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI 122 #define GP_STATUS_20G_DXGXS MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS 123 #define GP_STATUS_10G_SFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI 124 #define LINK_10THD LINK_STATUS_SPEED_AND_DUPLEX_10THD 125 #define LINK_10TFD LINK_STATUS_SPEED_AND_DUPLEX_10TFD 126 #define LINK_100TXHD LINK_STATUS_SPEED_AND_DUPLEX_100TXHD 127 #define LINK_100T4 LINK_STATUS_SPEED_AND_DUPLEX_100T4 128 #define LINK_100TXFD LINK_STATUS_SPEED_AND_DUPLEX_100TXFD 129 #define LINK_1000THD LINK_STATUS_SPEED_AND_DUPLEX_1000THD 130 #define LINK_1000TFD LINK_STATUS_SPEED_AND_DUPLEX_1000TFD 131 #define LINK_1000XFD LINK_STATUS_SPEED_AND_DUPLEX_1000XFD 132 #define LINK_2500THD LINK_STATUS_SPEED_AND_DUPLEX_2500THD 133 #define LINK_2500TFD LINK_STATUS_SPEED_AND_DUPLEX_2500TFD 134 #define LINK_2500XFD LINK_STATUS_SPEED_AND_DUPLEX_2500XFD 135 #define LINK_10GTFD LINK_STATUS_SPEED_AND_DUPLEX_10GTFD 136 #define LINK_10GXFD LINK_STATUS_SPEED_AND_DUPLEX_10GXFD 137 #define LINK_20GTFD LINK_STATUS_SPEED_AND_DUPLEX_20GTFD 138 #define LINK_20GXFD LINK_STATUS_SPEED_AND_DUPLEX_20GXFD 139 140 #define LINK_UPDATE_MASK \ 141 (LINK_STATUS_SPEED_AND_DUPLEX_MASK | \ 142 LINK_STATUS_LINK_UP | \ 143 LINK_STATUS_PHYSICAL_LINK_FLAG | \ 144 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE | \ 145 LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK | \ 146 LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK | \ 147 LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK | \ 148 LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE | \ 149 LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE) 150 151 #define SFP_EEPROM_CON_TYPE_ADDR 0x2 152 #define SFP_EEPROM_CON_TYPE_VAL_LC 0x7 153 #define SFP_EEPROM_CON_TYPE_VAL_COPPER 0x21 154 155 156 #define SFP_EEPROM_COMP_CODE_ADDR 0x3 157 #define SFP_EEPROM_COMP_CODE_SR_MASK (1<<4) 158 #define SFP_EEPROM_COMP_CODE_LR_MASK (1<<5) 159 #define SFP_EEPROM_COMP_CODE_LRM_MASK (1<<6) 160 161 #define SFP_EEPROM_FC_TX_TECH_ADDR 0x8 162 #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4 163 #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE 0x8 164 165 #define SFP_EEPROM_OPTIONS_ADDR 0x40 166 #define SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1 167 #define SFP_EEPROM_OPTIONS_SIZE 2 168 169 #define EDC_MODE_LINEAR 0x0022 170 #define EDC_MODE_LIMITING 0x0044 171 #define EDC_MODE_PASSIVE_DAC 0x0055 172 173 /* ETS defines*/ 174 #define DCBX_INVALID_COS (0xFF) 175 176 #define ETS_BW_LIMIT_CREDIT_UPPER_BOUND (0x5000) 177 #define ETS_BW_LIMIT_CREDIT_WEIGHT (0x5000) 178 #define ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS (1360) 179 #define ETS_E3B0_NIG_MIN_W_VAL_20GBPS (2720) 180 #define ETS_E3B0_PBF_MIN_W_VAL (10000) 181 182 #define MAX_PACKET_SIZE (9700) 183 #define MAX_KR_LINK_RETRY 4 184 185 /**********************************************************/ 186 /* INTERFACE */ 187 /**********************************************************/ 188 189 #define CL22_WR_OVER_CL45(_bp, _phy, _bank, _addr, _val) \ 190 bnx2x_cl45_write(_bp, _phy, \ 191 (_phy)->def_md_devad, \ 192 (_bank + (_addr & 0xf)), \ 193 _val) 194 195 #define CL22_RD_OVER_CL45(_bp, _phy, _bank, _addr, _val) \ 196 bnx2x_cl45_read(_bp, _phy, \ 197 (_phy)->def_md_devad, \ 198 (_bank + (_addr & 0xf)), \ 199 _val) 200 201 static u32 bnx2x_bits_en(struct bnx2x *bp, u32 reg, u32 bits) 202 { 203 u32 val = REG_RD(bp, reg); 204 205 val |= bits; 206 REG_WR(bp, reg, val); 207 return val; 208 } 209 210 static u32 bnx2x_bits_dis(struct bnx2x *bp, u32 reg, u32 bits) 211 { 212 u32 val = REG_RD(bp, reg); 213 214 val &= ~bits; 215 REG_WR(bp, reg, val); 216 return val; 217 } 218 219 /* 220 * bnx2x_check_lfa - This function checks if link reinitialization is required, 221 * or link flap can be avoided. 222 * 223 * @params: link parameters 224 * Returns 0 if Link Flap Avoidance conditions are met otherwise, the failed 225 * condition code. 226 */ 227 static int bnx2x_check_lfa(struct link_params *params) 228 { 229 u32 link_status, cfg_idx, lfa_mask, cfg_size; 230 u32 cur_speed_cap_mask, cur_req_fc_auto_adv, additional_config; 231 u32 saved_val, req_val, eee_status; 232 struct bnx2x *bp = params->bp; 233 234 additional_config = 235 REG_RD(bp, params->lfa_base + 236 offsetof(struct shmem_lfa, additional_config)); 237 238 /* NOTE: must be first condition checked - 239 * to verify DCC bit is cleared in any case! 240 */ 241 if (additional_config & NO_LFA_DUE_TO_DCC_MASK) { 242 DP(NETIF_MSG_LINK, "No LFA due to DCC flap after clp exit\n"); 243 REG_WR(bp, params->lfa_base + 244 offsetof(struct shmem_lfa, additional_config), 245 additional_config & ~NO_LFA_DUE_TO_DCC_MASK); 246 return LFA_DCC_LFA_DISABLED; 247 } 248 249 /* Verify that link is up */ 250 link_status = REG_RD(bp, params->shmem_base + 251 offsetof(struct shmem_region, 252 port_mb[params->port].link_status)); 253 if (!(link_status & LINK_STATUS_LINK_UP)) 254 return LFA_LINK_DOWN; 255 256 /* Verify that loopback mode is not set */ 257 if (params->loopback_mode) 258 return LFA_LOOPBACK_ENABLED; 259 260 /* Verify that MFW supports LFA */ 261 if (!params->lfa_base) 262 return LFA_MFW_IS_TOO_OLD; 263 264 if (params->num_phys == 3) { 265 cfg_size = 2; 266 lfa_mask = 0xffffffff; 267 } else { 268 cfg_size = 1; 269 lfa_mask = 0xffff; 270 } 271 272 /* Compare Duplex */ 273 saved_val = REG_RD(bp, params->lfa_base + 274 offsetof(struct shmem_lfa, req_duplex)); 275 req_val = params->req_duplex[0] | (params->req_duplex[1] << 16); 276 if ((saved_val & lfa_mask) != (req_val & lfa_mask)) { 277 DP(NETIF_MSG_LINK, "Duplex mismatch %x vs. %x\n", 278 (saved_val & lfa_mask), (req_val & lfa_mask)); 279 return LFA_DUPLEX_MISMATCH; 280 } 281 /* Compare Flow Control */ 282 saved_val = REG_RD(bp, params->lfa_base + 283 offsetof(struct shmem_lfa, req_flow_ctrl)); 284 req_val = params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16); 285 if ((saved_val & lfa_mask) != (req_val & lfa_mask)) { 286 DP(NETIF_MSG_LINK, "Flow control mismatch %x vs. %x\n", 287 (saved_val & lfa_mask), (req_val & lfa_mask)); 288 return LFA_FLOW_CTRL_MISMATCH; 289 } 290 /* Compare Link Speed */ 291 saved_val = REG_RD(bp, params->lfa_base + 292 offsetof(struct shmem_lfa, req_line_speed)); 293 req_val = params->req_line_speed[0] | (params->req_line_speed[1] << 16); 294 if ((saved_val & lfa_mask) != (req_val & lfa_mask)) { 295 DP(NETIF_MSG_LINK, "Link speed mismatch %x vs. %x\n", 296 (saved_val & lfa_mask), (req_val & lfa_mask)); 297 return LFA_LINK_SPEED_MISMATCH; 298 } 299 300 for (cfg_idx = 0; cfg_idx < cfg_size; cfg_idx++) { 301 cur_speed_cap_mask = REG_RD(bp, params->lfa_base + 302 offsetof(struct shmem_lfa, 303 speed_cap_mask[cfg_idx])); 304 305 if (cur_speed_cap_mask != params->speed_cap_mask[cfg_idx]) { 306 DP(NETIF_MSG_LINK, "Speed Cap mismatch %x vs. %x\n", 307 cur_speed_cap_mask, 308 params->speed_cap_mask[cfg_idx]); 309 return LFA_SPEED_CAP_MISMATCH; 310 } 311 } 312 313 cur_req_fc_auto_adv = 314 REG_RD(bp, params->lfa_base + 315 offsetof(struct shmem_lfa, additional_config)) & 316 REQ_FC_AUTO_ADV_MASK; 317 318 if ((u16)cur_req_fc_auto_adv != params->req_fc_auto_adv) { 319 DP(NETIF_MSG_LINK, "Flow Ctrl AN mismatch %x vs. %x\n", 320 cur_req_fc_auto_adv, params->req_fc_auto_adv); 321 return LFA_FLOW_CTRL_MISMATCH; 322 } 323 324 eee_status = REG_RD(bp, params->shmem2_base + 325 offsetof(struct shmem2_region, 326 eee_status[params->port])); 327 328 if (((eee_status & SHMEM_EEE_LPI_REQUESTED_BIT) ^ 329 (params->eee_mode & EEE_MODE_ENABLE_LPI)) || 330 ((eee_status & SHMEM_EEE_REQUESTED_BIT) ^ 331 (params->eee_mode & EEE_MODE_ADV_LPI))) { 332 DP(NETIF_MSG_LINK, "EEE mismatch %x vs. %x\n", params->eee_mode, 333 eee_status); 334 return LFA_EEE_MISMATCH; 335 } 336 337 /* LFA conditions are met */ 338 return 0; 339 } 340 /******************************************************************/ 341 /* EPIO/GPIO section */ 342 /******************************************************************/ 343 static void bnx2x_get_epio(struct bnx2x *bp, u32 epio_pin, u32 *en) 344 { 345 u32 epio_mask, gp_oenable; 346 *en = 0; 347 /* Sanity check */ 348 if (epio_pin > 31) { 349 DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to get\n", epio_pin); 350 return; 351 } 352 353 epio_mask = 1 << epio_pin; 354 /* Set this EPIO to output */ 355 gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE); 356 REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable & ~epio_mask); 357 358 *en = (REG_RD(bp, MCP_REG_MCPR_GP_INPUTS) & epio_mask) >> epio_pin; 359 } 360 static void bnx2x_set_epio(struct bnx2x *bp, u32 epio_pin, u32 en) 361 { 362 u32 epio_mask, gp_output, gp_oenable; 363 364 /* Sanity check */ 365 if (epio_pin > 31) { 366 DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to set\n", epio_pin); 367 return; 368 } 369 DP(NETIF_MSG_LINK, "Setting EPIO pin %d to %d\n", epio_pin, en); 370 epio_mask = 1 << epio_pin; 371 /* Set this EPIO to output */ 372 gp_output = REG_RD(bp, MCP_REG_MCPR_GP_OUTPUTS); 373 if (en) 374 gp_output |= epio_mask; 375 else 376 gp_output &= ~epio_mask; 377 378 REG_WR(bp, MCP_REG_MCPR_GP_OUTPUTS, gp_output); 379 380 /* Set the value for this EPIO */ 381 gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE); 382 REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable | epio_mask); 383 } 384 385 static void bnx2x_set_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 val) 386 { 387 if (pin_cfg == PIN_CFG_NA) 388 return; 389 if (pin_cfg >= PIN_CFG_EPIO0) { 390 bnx2x_set_epio(bp, pin_cfg - PIN_CFG_EPIO0, val); 391 } else { 392 u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3; 393 u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2; 394 bnx2x_set_gpio(bp, gpio_num, (u8)val, gpio_port); 395 } 396 } 397 398 static u32 bnx2x_get_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 *val) 399 { 400 if (pin_cfg == PIN_CFG_NA) 401 return -EINVAL; 402 if (pin_cfg >= PIN_CFG_EPIO0) { 403 bnx2x_get_epio(bp, pin_cfg - PIN_CFG_EPIO0, val); 404 } else { 405 u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3; 406 u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2; 407 *val = bnx2x_get_gpio(bp, gpio_num, gpio_port); 408 } 409 return 0; 410 411 } 412 /******************************************************************/ 413 /* ETS section */ 414 /******************************************************************/ 415 static void bnx2x_ets_e2e3a0_disabled(struct link_params *params) 416 { 417 /* ETS disabled configuration*/ 418 struct bnx2x *bp = params->bp; 419 420 DP(NETIF_MSG_LINK, "ETS E2E3 disabled configuration\n"); 421 422 /* mapping between entry priority to client number (0,1,2 -debug and 423 * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST) 424 * 3bits client num. 425 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0 426 * cos1-100 cos0-011 dbg1-010 dbg0-001 MCP-000 427 */ 428 429 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, 0x4688); 430 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves 431 * as strict. Bits 0,1,2 - debug and management entries, 3 - 432 * COS0 entry, 4 - COS1 entry. 433 * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT 434 * bit4 bit3 bit2 bit1 bit0 435 * MCP and debug are strict 436 */ 437 438 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7); 439 /* defines which entries (clients) are subjected to WFQ arbitration */ 440 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0); 441 /* For strict priority entries defines the number of consecutive 442 * slots for the highest priority. 443 */ 444 REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100); 445 /* mapping between the CREDIT_WEIGHT registers and actual client 446 * numbers 447 */ 448 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0); 449 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0); 450 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0); 451 452 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 0); 453 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 0); 454 REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, 0); 455 /* ETS mode disable */ 456 REG_WR(bp, PBF_REG_ETS_ENABLED, 0); 457 /* If ETS mode is enabled (there is no strict priority) defines a WFQ 458 * weight for COS0/COS1. 459 */ 460 REG_WR(bp, PBF_REG_COS0_WEIGHT, 0x2710); 461 REG_WR(bp, PBF_REG_COS1_WEIGHT, 0x2710); 462 /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter */ 463 REG_WR(bp, PBF_REG_COS0_UPPER_BOUND, 0x989680); 464 REG_WR(bp, PBF_REG_COS1_UPPER_BOUND, 0x989680); 465 /* Defines the number of consecutive slots for the strict priority */ 466 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0); 467 } 468 /****************************************************************************** 469 * Description: 470 * Getting min_w_val will be set according to line speed . 471 *. 472 ******************************************************************************/ 473 static u32 bnx2x_ets_get_min_w_val_nig(const struct link_vars *vars) 474 { 475 u32 min_w_val = 0; 476 /* Calculate min_w_val.*/ 477 if (vars->link_up) { 478 if (vars->line_speed == SPEED_20000) 479 min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS; 480 else 481 min_w_val = ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS; 482 } else 483 min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS; 484 /* If the link isn't up (static configuration for example ) The 485 * link will be according to 20GBPS. 486 */ 487 return min_w_val; 488 } 489 /****************************************************************************** 490 * Description: 491 * Getting credit upper bound form min_w_val. 492 *. 493 ******************************************************************************/ 494 static u32 bnx2x_ets_get_credit_upper_bound(const u32 min_w_val) 495 { 496 const u32 credit_upper_bound = (u32)MAXVAL((150 * min_w_val), 497 MAX_PACKET_SIZE); 498 return credit_upper_bound; 499 } 500 /****************************************************************************** 501 * Description: 502 * Set credit upper bound for NIG. 503 *. 504 ******************************************************************************/ 505 static void bnx2x_ets_e3b0_set_credit_upper_bound_nig( 506 const struct link_params *params, 507 const u32 min_w_val) 508 { 509 struct bnx2x *bp = params->bp; 510 const u8 port = params->port; 511 const u32 credit_upper_bound = 512 bnx2x_ets_get_credit_upper_bound(min_w_val); 513 514 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 : 515 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, credit_upper_bound); 516 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 : 517 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, credit_upper_bound); 518 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 : 519 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_2, credit_upper_bound); 520 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 : 521 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_3, credit_upper_bound); 522 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 : 523 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_4, credit_upper_bound); 524 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 : 525 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_5, credit_upper_bound); 526 527 if (!port) { 528 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6, 529 credit_upper_bound); 530 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7, 531 credit_upper_bound); 532 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8, 533 credit_upper_bound); 534 } 535 } 536 /****************************************************************************** 537 * Description: 538 * Will return the NIG ETS registers to init values.Except 539 * credit_upper_bound. 540 * That isn't used in this configuration (No WFQ is enabled) and will be 541 * configured acording to spec 542 *. 543 ******************************************************************************/ 544 static void bnx2x_ets_e3b0_nig_disabled(const struct link_params *params, 545 const struct link_vars *vars) 546 { 547 struct bnx2x *bp = params->bp; 548 const u8 port = params->port; 549 const u32 min_w_val = bnx2x_ets_get_min_w_val_nig(vars); 550 /* Mapping between entry priority to client number (0,1,2 -debug and 551 * management clients, 3 - COS0 client, 4 - COS1, ... 8 - 552 * COS5)(HIGHEST) 4bits client num.TODO_ETS - Should be done by 553 * reset value or init tool 554 */ 555 if (port) { 556 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, 0x543210); 557 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB, 0x0); 558 } else { 559 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, 0x76543210); 560 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, 0x8); 561 } 562 /* For strict priority entries defines the number of consecutive 563 * slots for the highest priority. 564 */ 565 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS : 566 NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100); 567 /* Mapping between the CREDIT_WEIGHT registers and actual client 568 * numbers 569 */ 570 if (port) { 571 /*Port 1 has 6 COS*/ 572 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB, 0x210543); 573 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x0); 574 } else { 575 /*Port 0 has 9 COS*/ 576 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB, 577 0x43210876); 578 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x5); 579 } 580 581 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves 582 * as strict. Bits 0,1,2 - debug and management entries, 3 - 583 * COS0 entry, 4 - COS1 entry. 584 * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT 585 * bit4 bit3 bit2 bit1 bit0 586 * MCP and debug are strict 587 */ 588 if (port) 589 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT, 0x3f); 590 else 591 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1ff); 592 /* defines which entries (clients) are subjected to WFQ arbitration */ 593 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ : 594 NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0); 595 596 /* Please notice the register address are note continuous and a 597 * for here is note appropriate.In 2 port mode port0 only COS0-5 598 * can be used. DEBUG1,DEBUG1,MGMT are never used for WFQ* In 4 599 * port mode port1 only COS0-2 can be used. DEBUG1,DEBUG1,MGMT 600 * are never used for WFQ 601 */ 602 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 : 603 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0x0); 604 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 : 605 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0x0); 606 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 : 607 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2, 0x0); 608 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 : 609 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3, 0x0); 610 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 : 611 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4, 0x0); 612 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 : 613 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5, 0x0); 614 if (!port) { 615 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6, 0x0); 616 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7, 0x0); 617 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8, 0x0); 618 } 619 620 bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val); 621 } 622 /****************************************************************************** 623 * Description: 624 * Set credit upper bound for PBF. 625 *. 626 ******************************************************************************/ 627 static void bnx2x_ets_e3b0_set_credit_upper_bound_pbf( 628 const struct link_params *params, 629 const u32 min_w_val) 630 { 631 struct bnx2x *bp = params->bp; 632 const u32 credit_upper_bound = 633 bnx2x_ets_get_credit_upper_bound(min_w_val); 634 const u8 port = params->port; 635 u32 base_upper_bound = 0; 636 u8 max_cos = 0; 637 u8 i = 0; 638 /* In 2 port mode port0 has COS0-5 that can be used for WFQ.In 4 639 * port mode port1 has COS0-2 that can be used for WFQ. 640 */ 641 if (!port) { 642 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P0; 643 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0; 644 } else { 645 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P1; 646 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT1; 647 } 648 649 for (i = 0; i < max_cos; i++) 650 REG_WR(bp, base_upper_bound + (i << 2), credit_upper_bound); 651 } 652 653 /****************************************************************************** 654 * Description: 655 * Will return the PBF ETS registers to init values.Except 656 * credit_upper_bound. 657 * That isn't used in this configuration (No WFQ is enabled) and will be 658 * configured acording to spec 659 *. 660 ******************************************************************************/ 661 static void bnx2x_ets_e3b0_pbf_disabled(const struct link_params *params) 662 { 663 struct bnx2x *bp = params->bp; 664 const u8 port = params->port; 665 const u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL; 666 u8 i = 0; 667 u32 base_weight = 0; 668 u8 max_cos = 0; 669 670 /* Mapping between entry priority to client number 0 - COS0 671 * client, 2 - COS1, ... 5 - COS5)(HIGHEST) 4bits client num. 672 * TODO_ETS - Should be done by reset value or init tool 673 */ 674 if (port) 675 /* 0x688 (|011|0 10|00 1|000) */ 676 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , 0x688); 677 else 678 /* (10 1|100 |011|0 10|00 1|000) */ 679 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , 0x2C688); 680 681 /* TODO_ETS - Should be done by reset value or init tool */ 682 if (port) 683 /* 0x688 (|011|0 10|00 1|000)*/ 684 REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1, 0x688); 685 else 686 /* 0x2C688 (10 1|100 |011|0 10|00 1|000) */ 687 REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0, 0x2C688); 688 689 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 : 690 PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0 , 0x100); 691 692 693 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 : 694 PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , 0); 695 696 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 : 697 PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0 , 0); 698 /* In 2 port mode port0 has COS0-5 that can be used for WFQ. 699 * In 4 port mode port1 has COS0-2 that can be used for WFQ. 700 */ 701 if (!port) { 702 base_weight = PBF_REG_COS0_WEIGHT_P0; 703 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0; 704 } else { 705 base_weight = PBF_REG_COS0_WEIGHT_P1; 706 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT1; 707 } 708 709 for (i = 0; i < max_cos; i++) 710 REG_WR(bp, base_weight + (0x4 * i), 0); 711 712 bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf); 713 } 714 /****************************************************************************** 715 * Description: 716 * E3B0 disable will return basicly the values to init values. 717 *. 718 ******************************************************************************/ 719 static int bnx2x_ets_e3b0_disabled(const struct link_params *params, 720 const struct link_vars *vars) 721 { 722 struct bnx2x *bp = params->bp; 723 724 if (!CHIP_IS_E3B0(bp)) { 725 DP(NETIF_MSG_LINK, 726 "bnx2x_ets_e3b0_disabled the chip isn't E3B0\n"); 727 return -EINVAL; 728 } 729 730 bnx2x_ets_e3b0_nig_disabled(params, vars); 731 732 bnx2x_ets_e3b0_pbf_disabled(params); 733 734 return 0; 735 } 736 737 /****************************************************************************** 738 * Description: 739 * Disable will return basicly the values to init values. 740 * 741 ******************************************************************************/ 742 int bnx2x_ets_disabled(struct link_params *params, 743 struct link_vars *vars) 744 { 745 struct bnx2x *bp = params->bp; 746 int bnx2x_status = 0; 747 748 if ((CHIP_IS_E2(bp)) || (CHIP_IS_E3A0(bp))) 749 bnx2x_ets_e2e3a0_disabled(params); 750 else if (CHIP_IS_E3B0(bp)) 751 bnx2x_status = bnx2x_ets_e3b0_disabled(params, vars); 752 else { 753 DP(NETIF_MSG_LINK, "bnx2x_ets_disabled - chip not supported\n"); 754 return -EINVAL; 755 } 756 757 return bnx2x_status; 758 } 759 760 /****************************************************************************** 761 * Description 762 * Set the COS mappimg to SP and BW until this point all the COS are not 763 * set as SP or BW. 764 ******************************************************************************/ 765 static int bnx2x_ets_e3b0_cli_map(const struct link_params *params, 766 const struct bnx2x_ets_params *ets_params, 767 const u8 cos_sp_bitmap, 768 const u8 cos_bw_bitmap) 769 { 770 struct bnx2x *bp = params->bp; 771 const u8 port = params->port; 772 const u8 nig_cli_sp_bitmap = 0x7 | (cos_sp_bitmap << 3); 773 const u8 pbf_cli_sp_bitmap = cos_sp_bitmap; 774 const u8 nig_cli_subject2wfq_bitmap = cos_bw_bitmap << 3; 775 const u8 pbf_cli_subject2wfq_bitmap = cos_bw_bitmap; 776 777 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT : 778 NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, nig_cli_sp_bitmap); 779 780 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 : 781 PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , pbf_cli_sp_bitmap); 782 783 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ : 784 NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 785 nig_cli_subject2wfq_bitmap); 786 787 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 : 788 PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0, 789 pbf_cli_subject2wfq_bitmap); 790 791 return 0; 792 } 793 794 /****************************************************************************** 795 * Description: 796 * This function is needed because NIG ARB_CREDIT_WEIGHT_X are 797 * not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable. 798 ******************************************************************************/ 799 static int bnx2x_ets_e3b0_set_cos_bw(struct bnx2x *bp, 800 const u8 cos_entry, 801 const u32 min_w_val_nig, 802 const u32 min_w_val_pbf, 803 const u16 total_bw, 804 const u8 bw, 805 const u8 port) 806 { 807 u32 nig_reg_adress_crd_weight = 0; 808 u32 pbf_reg_adress_crd_weight = 0; 809 /* Calculate and set BW for this COS - use 1 instead of 0 for BW */ 810 const u32 cos_bw_nig = ((bw ? bw : 1) * min_w_val_nig) / total_bw; 811 const u32 cos_bw_pbf = ((bw ? bw : 1) * min_w_val_pbf) / total_bw; 812 813 switch (cos_entry) { 814 case 0: 815 nig_reg_adress_crd_weight = 816 (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 : 817 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0; 818 pbf_reg_adress_crd_weight = (port) ? 819 PBF_REG_COS0_WEIGHT_P1 : PBF_REG_COS0_WEIGHT_P0; 820 break; 821 case 1: 822 nig_reg_adress_crd_weight = (port) ? 823 NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 : 824 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1; 825 pbf_reg_adress_crd_weight = (port) ? 826 PBF_REG_COS1_WEIGHT_P1 : PBF_REG_COS1_WEIGHT_P0; 827 break; 828 case 2: 829 nig_reg_adress_crd_weight = (port) ? 830 NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 : 831 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2; 832 833 pbf_reg_adress_crd_weight = (port) ? 834 PBF_REG_COS2_WEIGHT_P1 : PBF_REG_COS2_WEIGHT_P0; 835 break; 836 case 3: 837 if (port) 838 return -EINVAL; 839 nig_reg_adress_crd_weight = 840 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3; 841 pbf_reg_adress_crd_weight = 842 PBF_REG_COS3_WEIGHT_P0; 843 break; 844 case 4: 845 if (port) 846 return -EINVAL; 847 nig_reg_adress_crd_weight = 848 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4; 849 pbf_reg_adress_crd_weight = PBF_REG_COS4_WEIGHT_P0; 850 break; 851 case 5: 852 if (port) 853 return -EINVAL; 854 nig_reg_adress_crd_weight = 855 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5; 856 pbf_reg_adress_crd_weight = PBF_REG_COS5_WEIGHT_P0; 857 break; 858 } 859 860 REG_WR(bp, nig_reg_adress_crd_weight, cos_bw_nig); 861 862 REG_WR(bp, pbf_reg_adress_crd_weight, cos_bw_pbf); 863 864 return 0; 865 } 866 /****************************************************************************** 867 * Description: 868 * Calculate the total BW.A value of 0 isn't legal. 869 * 870 ******************************************************************************/ 871 static int bnx2x_ets_e3b0_get_total_bw( 872 const struct link_params *params, 873 struct bnx2x_ets_params *ets_params, 874 u16 *total_bw) 875 { 876 struct bnx2x *bp = params->bp; 877 u8 cos_idx = 0; 878 u8 is_bw_cos_exist = 0; 879 880 *total_bw = 0 ; 881 /* Calculate total BW requested */ 882 for (cos_idx = 0; cos_idx < ets_params->num_of_cos; cos_idx++) { 883 if (ets_params->cos[cos_idx].state == bnx2x_cos_state_bw) { 884 is_bw_cos_exist = 1; 885 if (!ets_params->cos[cos_idx].params.bw_params.bw) { 886 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config BW" 887 "was set to 0\n"); 888 /* This is to prevent a state when ramrods 889 * can't be sent 890 */ 891 ets_params->cos[cos_idx].params.bw_params.bw 892 = 1; 893 } 894 *total_bw += 895 ets_params->cos[cos_idx].params.bw_params.bw; 896 } 897 } 898 899 /* Check total BW is valid */ 900 if ((is_bw_cos_exist == 1) && (*total_bw != 100)) { 901 if (*total_bw == 0) { 902 DP(NETIF_MSG_LINK, 903 "bnx2x_ets_E3B0_config total BW shouldn't be 0\n"); 904 return -EINVAL; 905 } 906 DP(NETIF_MSG_LINK, 907 "bnx2x_ets_E3B0_config total BW should be 100\n"); 908 /* We can handle a case whre the BW isn't 100 this can happen 909 * if the TC are joined. 910 */ 911 } 912 return 0; 913 } 914 915 /****************************************************************************** 916 * Description: 917 * Invalidate all the sp_pri_to_cos. 918 * 919 ******************************************************************************/ 920 static void bnx2x_ets_e3b0_sp_pri_to_cos_init(u8 *sp_pri_to_cos) 921 { 922 u8 pri = 0; 923 for (pri = 0; pri < DCBX_MAX_NUM_COS; pri++) 924 sp_pri_to_cos[pri] = DCBX_INVALID_COS; 925 } 926 /****************************************************************************** 927 * Description: 928 * Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers 929 * according to sp_pri_to_cos. 930 * 931 ******************************************************************************/ 932 static int bnx2x_ets_e3b0_sp_pri_to_cos_set(const struct link_params *params, 933 u8 *sp_pri_to_cos, const u8 pri, 934 const u8 cos_entry) 935 { 936 struct bnx2x *bp = params->bp; 937 const u8 port = params->port; 938 const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 : 939 DCBX_E3B0_MAX_NUM_COS_PORT0; 940 941 if (pri >= max_num_of_cos) { 942 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid " 943 "parameter Illegal strict priority\n"); 944 return -EINVAL; 945 } 946 947 if (sp_pri_to_cos[pri] != DCBX_INVALID_COS) { 948 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid " 949 "parameter There can't be two COS's with " 950 "the same strict pri\n"); 951 return -EINVAL; 952 } 953 954 sp_pri_to_cos[pri] = cos_entry; 955 return 0; 956 957 } 958 959 /****************************************************************************** 960 * Description: 961 * Returns the correct value according to COS and priority in 962 * the sp_pri_cli register. 963 * 964 ******************************************************************************/ 965 static u64 bnx2x_e3b0_sp_get_pri_cli_reg(const u8 cos, const u8 cos_offset, 966 const u8 pri_set, 967 const u8 pri_offset, 968 const u8 entry_size) 969 { 970 u64 pri_cli_nig = 0; 971 pri_cli_nig = ((u64)(cos + cos_offset)) << (entry_size * 972 (pri_set + pri_offset)); 973 974 return pri_cli_nig; 975 } 976 /****************************************************************************** 977 * Description: 978 * Returns the correct value according to COS and priority in the 979 * sp_pri_cli register for NIG. 980 * 981 ******************************************************************************/ 982 static u64 bnx2x_e3b0_sp_get_pri_cli_reg_nig(const u8 cos, const u8 pri_set) 983 { 984 /* MCP Dbg0 and dbg1 are always with higher strict pri*/ 985 const u8 nig_cos_offset = 3; 986 const u8 nig_pri_offset = 3; 987 988 return bnx2x_e3b0_sp_get_pri_cli_reg(cos, nig_cos_offset, pri_set, 989 nig_pri_offset, 4); 990 991 } 992 /****************************************************************************** 993 * Description: 994 * Returns the correct value according to COS and priority in the 995 * sp_pri_cli register for PBF. 996 * 997 ******************************************************************************/ 998 static u64 bnx2x_e3b0_sp_get_pri_cli_reg_pbf(const u8 cos, const u8 pri_set) 999 { 1000 const u8 pbf_cos_offset = 0; 1001 const u8 pbf_pri_offset = 0; 1002 1003 return bnx2x_e3b0_sp_get_pri_cli_reg(cos, pbf_cos_offset, pri_set, 1004 pbf_pri_offset, 3); 1005 1006 } 1007 1008 /****************************************************************************** 1009 * Description: 1010 * Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers 1011 * according to sp_pri_to_cos.(which COS has higher priority) 1012 * 1013 ******************************************************************************/ 1014 static int bnx2x_ets_e3b0_sp_set_pri_cli_reg(const struct link_params *params, 1015 u8 *sp_pri_to_cos) 1016 { 1017 struct bnx2x *bp = params->bp; 1018 u8 i = 0; 1019 const u8 port = params->port; 1020 /* MCP Dbg0 and dbg1 are always with higher strict pri*/ 1021 u64 pri_cli_nig = 0x210; 1022 u32 pri_cli_pbf = 0x0; 1023 u8 pri_set = 0; 1024 u8 pri_bitmask = 0; 1025 const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 : 1026 DCBX_E3B0_MAX_NUM_COS_PORT0; 1027 1028 u8 cos_bit_to_set = (1 << max_num_of_cos) - 1; 1029 1030 /* Set all the strict priority first */ 1031 for (i = 0; i < max_num_of_cos; i++) { 1032 if (sp_pri_to_cos[i] != DCBX_INVALID_COS) { 1033 if (sp_pri_to_cos[i] >= DCBX_MAX_NUM_COS) { 1034 DP(NETIF_MSG_LINK, 1035 "bnx2x_ets_e3b0_sp_set_pri_cli_reg " 1036 "invalid cos entry\n"); 1037 return -EINVAL; 1038 } 1039 1040 pri_cli_nig |= bnx2x_e3b0_sp_get_pri_cli_reg_nig( 1041 sp_pri_to_cos[i], pri_set); 1042 1043 pri_cli_pbf |= bnx2x_e3b0_sp_get_pri_cli_reg_pbf( 1044 sp_pri_to_cos[i], pri_set); 1045 pri_bitmask = 1 << sp_pri_to_cos[i]; 1046 /* COS is used remove it from bitmap.*/ 1047 if (!(pri_bitmask & cos_bit_to_set)) { 1048 DP(NETIF_MSG_LINK, 1049 "bnx2x_ets_e3b0_sp_set_pri_cli_reg " 1050 "invalid There can't be two COS's with" 1051 " the same strict pri\n"); 1052 return -EINVAL; 1053 } 1054 cos_bit_to_set &= ~pri_bitmask; 1055 pri_set++; 1056 } 1057 } 1058 1059 /* Set all the Non strict priority i= COS*/ 1060 for (i = 0; i < max_num_of_cos; i++) { 1061 pri_bitmask = 1 << i; 1062 /* Check if COS was already used for SP */ 1063 if (pri_bitmask & cos_bit_to_set) { 1064 /* COS wasn't used for SP */ 1065 pri_cli_nig |= bnx2x_e3b0_sp_get_pri_cli_reg_nig( 1066 i, pri_set); 1067 1068 pri_cli_pbf |= bnx2x_e3b0_sp_get_pri_cli_reg_pbf( 1069 i, pri_set); 1070 /* COS is used remove it from bitmap.*/ 1071 cos_bit_to_set &= ~pri_bitmask; 1072 pri_set++; 1073 } 1074 } 1075 1076 if (pri_set != max_num_of_cos) { 1077 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_set_pri_cli_reg not all " 1078 "entries were set\n"); 1079 return -EINVAL; 1080 } 1081 1082 if (port) { 1083 /* Only 6 usable clients*/ 1084 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, 1085 (u32)pri_cli_nig); 1086 1087 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , pri_cli_pbf); 1088 } else { 1089 /* Only 9 usable clients*/ 1090 const u32 pri_cli_nig_lsb = (u32) (pri_cli_nig); 1091 const u32 pri_cli_nig_msb = (u32) ((pri_cli_nig >> 32) & 0xF); 1092 1093 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, 1094 pri_cli_nig_lsb); 1095 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, 1096 pri_cli_nig_msb); 1097 1098 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , pri_cli_pbf); 1099 } 1100 return 0; 1101 } 1102 1103 /****************************************************************************** 1104 * Description: 1105 * Configure the COS to ETS according to BW and SP settings. 1106 ******************************************************************************/ 1107 int bnx2x_ets_e3b0_config(const struct link_params *params, 1108 const struct link_vars *vars, 1109 struct bnx2x_ets_params *ets_params) 1110 { 1111 struct bnx2x *bp = params->bp; 1112 int bnx2x_status = 0; 1113 const u8 port = params->port; 1114 u16 total_bw = 0; 1115 const u32 min_w_val_nig = bnx2x_ets_get_min_w_val_nig(vars); 1116 const u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL; 1117 u8 cos_bw_bitmap = 0; 1118 u8 cos_sp_bitmap = 0; 1119 u8 sp_pri_to_cos[DCBX_MAX_NUM_COS] = {0}; 1120 const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 : 1121 DCBX_E3B0_MAX_NUM_COS_PORT0; 1122 u8 cos_entry = 0; 1123 1124 if (!CHIP_IS_E3B0(bp)) { 1125 DP(NETIF_MSG_LINK, 1126 "bnx2x_ets_e3b0_disabled the chip isn't E3B0\n"); 1127 return -EINVAL; 1128 } 1129 1130 if ((ets_params->num_of_cos > max_num_of_cos)) { 1131 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config the number of COS " 1132 "isn't supported\n"); 1133 return -EINVAL; 1134 } 1135 1136 /* Prepare sp strict priority parameters*/ 1137 bnx2x_ets_e3b0_sp_pri_to_cos_init(sp_pri_to_cos); 1138 1139 /* Prepare BW parameters*/ 1140 bnx2x_status = bnx2x_ets_e3b0_get_total_bw(params, ets_params, 1141 &total_bw); 1142 if (bnx2x_status) { 1143 DP(NETIF_MSG_LINK, 1144 "bnx2x_ets_E3B0_config get_total_bw failed\n"); 1145 return -EINVAL; 1146 } 1147 1148 /* Upper bound is set according to current link speed (min_w_val 1149 * should be the same for upper bound and COS credit val). 1150 */ 1151 bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val_nig); 1152 bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf); 1153 1154 1155 for (cos_entry = 0; cos_entry < ets_params->num_of_cos; cos_entry++) { 1156 if (bnx2x_cos_state_bw == ets_params->cos[cos_entry].state) { 1157 cos_bw_bitmap |= (1 << cos_entry); 1158 /* The function also sets the BW in HW(not the mappin 1159 * yet) 1160 */ 1161 bnx2x_status = bnx2x_ets_e3b0_set_cos_bw( 1162 bp, cos_entry, min_w_val_nig, min_w_val_pbf, 1163 total_bw, 1164 ets_params->cos[cos_entry].params.bw_params.bw, 1165 port); 1166 } else if (bnx2x_cos_state_strict == 1167 ets_params->cos[cos_entry].state){ 1168 cos_sp_bitmap |= (1 << cos_entry); 1169 1170 bnx2x_status = bnx2x_ets_e3b0_sp_pri_to_cos_set( 1171 params, 1172 sp_pri_to_cos, 1173 ets_params->cos[cos_entry].params.sp_params.pri, 1174 cos_entry); 1175 1176 } else { 1177 DP(NETIF_MSG_LINK, 1178 "bnx2x_ets_e3b0_config cos state not valid\n"); 1179 return -EINVAL; 1180 } 1181 if (bnx2x_status) { 1182 DP(NETIF_MSG_LINK, 1183 "bnx2x_ets_e3b0_config set cos bw failed\n"); 1184 return bnx2x_status; 1185 } 1186 } 1187 1188 /* Set SP register (which COS has higher priority) */ 1189 bnx2x_status = bnx2x_ets_e3b0_sp_set_pri_cli_reg(params, 1190 sp_pri_to_cos); 1191 1192 if (bnx2x_status) { 1193 DP(NETIF_MSG_LINK, 1194 "bnx2x_ets_E3B0_config set_pri_cli_reg failed\n"); 1195 return bnx2x_status; 1196 } 1197 1198 /* Set client mapping of BW and strict */ 1199 bnx2x_status = bnx2x_ets_e3b0_cli_map(params, ets_params, 1200 cos_sp_bitmap, 1201 cos_bw_bitmap); 1202 1203 if (bnx2x_status) { 1204 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config SP failed\n"); 1205 return bnx2x_status; 1206 } 1207 return 0; 1208 } 1209 static void bnx2x_ets_bw_limit_common(const struct link_params *params) 1210 { 1211 /* ETS disabled configuration */ 1212 struct bnx2x *bp = params->bp; 1213 DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n"); 1214 /* Defines which entries (clients) are subjected to WFQ arbitration 1215 * COS0 0x8 1216 * COS1 0x10 1217 */ 1218 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0x18); 1219 /* Mapping between the ARB_CREDIT_WEIGHT registers and actual 1220 * client numbers (WEIGHT_0 does not actually have to represent 1221 * client 0) 1222 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0 1223 * cos1-001 cos0-000 dbg1-100 dbg0-011 MCP-010 1224 */ 1225 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0x111A); 1226 1227 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 1228 ETS_BW_LIMIT_CREDIT_UPPER_BOUND); 1229 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 1230 ETS_BW_LIMIT_CREDIT_UPPER_BOUND); 1231 1232 /* ETS mode enabled*/ 1233 REG_WR(bp, PBF_REG_ETS_ENABLED, 1); 1234 1235 /* Defines the number of consecutive slots for the strict priority */ 1236 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0); 1237 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves 1238 * as strict. Bits 0,1,2 - debug and management entries, 3 - COS0 1239 * entry, 4 - COS1 entry. 1240 * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT 1241 * bit4 bit3 bit2 bit1 bit0 1242 * MCP and debug are strict 1243 */ 1244 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7); 1245 1246 /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter.*/ 1247 REG_WR(bp, PBF_REG_COS0_UPPER_BOUND, 1248 ETS_BW_LIMIT_CREDIT_UPPER_BOUND); 1249 REG_WR(bp, PBF_REG_COS1_UPPER_BOUND, 1250 ETS_BW_LIMIT_CREDIT_UPPER_BOUND); 1251 } 1252 1253 void bnx2x_ets_bw_limit(const struct link_params *params, const u32 cos0_bw, 1254 const u32 cos1_bw) 1255 { 1256 /* ETS disabled configuration*/ 1257 struct bnx2x *bp = params->bp; 1258 const u32 total_bw = cos0_bw + cos1_bw; 1259 u32 cos0_credit_weight = 0; 1260 u32 cos1_credit_weight = 0; 1261 1262 DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n"); 1263 1264 if ((!total_bw) || 1265 (!cos0_bw) || 1266 (!cos1_bw)) { 1267 DP(NETIF_MSG_LINK, "Total BW can't be zero\n"); 1268 return; 1269 } 1270 1271 cos0_credit_weight = (cos0_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/ 1272 total_bw; 1273 cos1_credit_weight = (cos1_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/ 1274 total_bw; 1275 1276 bnx2x_ets_bw_limit_common(params); 1277 1278 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, cos0_credit_weight); 1279 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, cos1_credit_weight); 1280 1281 REG_WR(bp, PBF_REG_COS0_WEIGHT, cos0_credit_weight); 1282 REG_WR(bp, PBF_REG_COS1_WEIGHT, cos1_credit_weight); 1283 } 1284 1285 int bnx2x_ets_strict(const struct link_params *params, const u8 strict_cos) 1286 { 1287 /* ETS disabled configuration*/ 1288 struct bnx2x *bp = params->bp; 1289 u32 val = 0; 1290 1291 DP(NETIF_MSG_LINK, "ETS enabled strict configuration\n"); 1292 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves 1293 * as strict. Bits 0,1,2 - debug and management entries, 1294 * 3 - COS0 entry, 4 - COS1 entry. 1295 * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT 1296 * bit4 bit3 bit2 bit1 bit0 1297 * MCP and debug are strict 1298 */ 1299 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1F); 1300 /* For strict priority entries defines the number of consecutive slots 1301 * for the highest priority. 1302 */ 1303 REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100); 1304 /* ETS mode disable */ 1305 REG_WR(bp, PBF_REG_ETS_ENABLED, 0); 1306 /* Defines the number of consecutive slots for the strict priority */ 1307 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0x100); 1308 1309 /* Defines the number of consecutive slots for the strict priority */ 1310 REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, strict_cos); 1311 1312 /* Mapping between entry priority to client number (0,1,2 -debug and 1313 * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST) 1314 * 3bits client num. 1315 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0 1316 * dbg0-010 dbg1-001 cos1-100 cos0-011 MCP-000 1317 * dbg0-010 dbg1-001 cos0-011 cos1-100 MCP-000 1318 */ 1319 val = (!strict_cos) ? 0x2318 : 0x22E0; 1320 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, val); 1321 1322 return 0; 1323 } 1324 1325 /******************************************************************/ 1326 /* PFC section */ 1327 /******************************************************************/ 1328 static void bnx2x_update_pfc_xmac(struct link_params *params, 1329 struct link_vars *vars, 1330 u8 is_lb) 1331 { 1332 struct bnx2x *bp = params->bp; 1333 u32 xmac_base; 1334 u32 pause_val, pfc0_val, pfc1_val; 1335 1336 /* XMAC base adrr */ 1337 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; 1338 1339 /* Initialize pause and pfc registers */ 1340 pause_val = 0x18000; 1341 pfc0_val = 0xFFFF8000; 1342 pfc1_val = 0x2; 1343 1344 /* No PFC support */ 1345 if (!(params->feature_config_flags & 1346 FEATURE_CONFIG_PFC_ENABLED)) { 1347 1348 /* RX flow control - Process pause frame in receive direction 1349 */ 1350 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX) 1351 pause_val |= XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN; 1352 1353 /* TX flow control - Send pause packet when buffer is full */ 1354 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) 1355 pause_val |= XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN; 1356 } else {/* PFC support */ 1357 pfc1_val |= XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN | 1358 XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN | 1359 XMAC_PFC_CTRL_HI_REG_RX_PFC_EN | 1360 XMAC_PFC_CTRL_HI_REG_TX_PFC_EN | 1361 XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON; 1362 /* Write pause and PFC registers */ 1363 REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val); 1364 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val); 1365 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val); 1366 pfc1_val &= ~XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON; 1367 1368 } 1369 1370 /* Write pause and PFC registers */ 1371 REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val); 1372 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val); 1373 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val); 1374 1375 1376 /* Set MAC address for source TX Pause/PFC frames */ 1377 REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_LO, 1378 ((params->mac_addr[2] << 24) | 1379 (params->mac_addr[3] << 16) | 1380 (params->mac_addr[4] << 8) | 1381 (params->mac_addr[5]))); 1382 REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_HI, 1383 ((params->mac_addr[0] << 8) | 1384 (params->mac_addr[1]))); 1385 1386 udelay(30); 1387 } 1388 1389 1390 static void bnx2x_emac_get_pfc_stat(struct link_params *params, 1391 u32 pfc_frames_sent[2], 1392 u32 pfc_frames_received[2]) 1393 { 1394 /* Read pfc statistic */ 1395 struct bnx2x *bp = params->bp; 1396 u32 emac_base = params->port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; 1397 u32 val_xon = 0; 1398 u32 val_xoff = 0; 1399 1400 DP(NETIF_MSG_LINK, "pfc statistic read from EMAC\n"); 1401 1402 /* PFC received frames */ 1403 val_xoff = REG_RD(bp, emac_base + 1404 EMAC_REG_RX_PFC_STATS_XOFF_RCVD); 1405 val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_RCVD_COUNT; 1406 val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_RCVD); 1407 val_xon &= EMAC_REG_RX_PFC_STATS_XON_RCVD_COUNT; 1408 1409 pfc_frames_received[0] = val_xon + val_xoff; 1410 1411 /* PFC received sent */ 1412 val_xoff = REG_RD(bp, emac_base + 1413 EMAC_REG_RX_PFC_STATS_XOFF_SENT); 1414 val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_SENT_COUNT; 1415 val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_SENT); 1416 val_xon &= EMAC_REG_RX_PFC_STATS_XON_SENT_COUNT; 1417 1418 pfc_frames_sent[0] = val_xon + val_xoff; 1419 } 1420 1421 /* Read pfc statistic*/ 1422 void bnx2x_pfc_statistic(struct link_params *params, struct link_vars *vars, 1423 u32 pfc_frames_sent[2], 1424 u32 pfc_frames_received[2]) 1425 { 1426 /* Read pfc statistic */ 1427 struct bnx2x *bp = params->bp; 1428 1429 DP(NETIF_MSG_LINK, "pfc statistic\n"); 1430 1431 if (!vars->link_up) 1432 return; 1433 1434 if (vars->mac_type == MAC_TYPE_EMAC) { 1435 DP(NETIF_MSG_LINK, "About to read PFC stats from EMAC\n"); 1436 bnx2x_emac_get_pfc_stat(params, pfc_frames_sent, 1437 pfc_frames_received); 1438 } 1439 } 1440 /******************************************************************/ 1441 /* MAC/PBF section */ 1442 /******************************************************************/ 1443 static void bnx2x_set_mdio_clk(struct bnx2x *bp, u32 chip_id, u8 port) 1444 { 1445 u32 mode, emac_base; 1446 /* Set clause 45 mode, slow down the MDIO clock to 2.5MHz 1447 * (a value of 49==0x31) and make sure that the AUTO poll is off 1448 */ 1449 1450 if (CHIP_IS_E2(bp)) 1451 emac_base = GRCBASE_EMAC0; 1452 else 1453 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0; 1454 mode = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE); 1455 mode &= ~(EMAC_MDIO_MODE_AUTO_POLL | 1456 EMAC_MDIO_MODE_CLOCK_CNT); 1457 if (USES_WARPCORE(bp)) 1458 mode |= (74L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT); 1459 else 1460 mode |= (49L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT); 1461 1462 mode |= (EMAC_MDIO_MODE_CLAUSE_45); 1463 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE, mode); 1464 1465 udelay(40); 1466 } 1467 static u8 bnx2x_is_4_port_mode(struct bnx2x *bp) 1468 { 1469 u32 port4mode_ovwr_val; 1470 /* Check 4-port override enabled */ 1471 port4mode_ovwr_val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR); 1472 if (port4mode_ovwr_val & (1<<0)) { 1473 /* Return 4-port mode override value */ 1474 return ((port4mode_ovwr_val & (1<<1)) == (1<<1)); 1475 } 1476 /* Return 4-port mode from input pin */ 1477 return (u8)REG_RD(bp, MISC_REG_PORT4MODE_EN); 1478 } 1479 1480 static void bnx2x_emac_init(struct link_params *params, 1481 struct link_vars *vars) 1482 { 1483 /* reset and unreset the emac core */ 1484 struct bnx2x *bp = params->bp; 1485 u8 port = params->port; 1486 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; 1487 u32 val; 1488 u16 timeout; 1489 1490 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 1491 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port)); 1492 udelay(5); 1493 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 1494 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port)); 1495 1496 /* init emac - use read-modify-write */ 1497 /* self clear reset */ 1498 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE); 1499 EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET)); 1500 1501 timeout = 200; 1502 do { 1503 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE); 1504 DP(NETIF_MSG_LINK, "EMAC reset reg is %u\n", val); 1505 if (!timeout) { 1506 DP(NETIF_MSG_LINK, "EMAC timeout!\n"); 1507 return; 1508 } 1509 timeout--; 1510 } while (val & EMAC_MODE_RESET); 1511 bnx2x_set_mdio_clk(bp, params->chip_id, port); 1512 /* Set mac address */ 1513 val = ((params->mac_addr[0] << 8) | 1514 params->mac_addr[1]); 1515 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH, val); 1516 1517 val = ((params->mac_addr[2] << 24) | 1518 (params->mac_addr[3] << 16) | 1519 (params->mac_addr[4] << 8) | 1520 params->mac_addr[5]); 1521 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + 4, val); 1522 } 1523 1524 static void bnx2x_set_xumac_nig(struct link_params *params, 1525 u16 tx_pause_en, 1526 u8 enable) 1527 { 1528 struct bnx2x *bp = params->bp; 1529 1530 REG_WR(bp, params->port ? NIG_REG_P1_MAC_IN_EN : NIG_REG_P0_MAC_IN_EN, 1531 enable); 1532 REG_WR(bp, params->port ? NIG_REG_P1_MAC_OUT_EN : NIG_REG_P0_MAC_OUT_EN, 1533 enable); 1534 REG_WR(bp, params->port ? NIG_REG_P1_MAC_PAUSE_OUT_EN : 1535 NIG_REG_P0_MAC_PAUSE_OUT_EN, tx_pause_en); 1536 } 1537 1538 static void bnx2x_set_umac_rxtx(struct link_params *params, u8 en) 1539 { 1540 u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0; 1541 u32 val; 1542 struct bnx2x *bp = params->bp; 1543 if (!(REG_RD(bp, MISC_REG_RESET_REG_2) & 1544 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port))) 1545 return; 1546 val = REG_RD(bp, umac_base + UMAC_REG_COMMAND_CONFIG); 1547 if (en) 1548 val |= (UMAC_COMMAND_CONFIG_REG_TX_ENA | 1549 UMAC_COMMAND_CONFIG_REG_RX_ENA); 1550 else 1551 val &= ~(UMAC_COMMAND_CONFIG_REG_TX_ENA | 1552 UMAC_COMMAND_CONFIG_REG_RX_ENA); 1553 /* Disable RX and TX */ 1554 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val); 1555 } 1556 1557 static void bnx2x_umac_enable(struct link_params *params, 1558 struct link_vars *vars, u8 lb) 1559 { 1560 u32 val; 1561 u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0; 1562 struct bnx2x *bp = params->bp; 1563 /* Reset UMAC */ 1564 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 1565 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port)); 1566 usleep_range(1000, 2000); 1567 1568 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 1569 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port)); 1570 1571 DP(NETIF_MSG_LINK, "enabling UMAC\n"); 1572 1573 /* This register opens the gate for the UMAC despite its name */ 1574 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1); 1575 1576 val = UMAC_COMMAND_CONFIG_REG_PROMIS_EN | 1577 UMAC_COMMAND_CONFIG_REG_PAD_EN | 1578 UMAC_COMMAND_CONFIG_REG_SW_RESET | 1579 UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK; 1580 switch (vars->line_speed) { 1581 case SPEED_10: 1582 val |= (0<<2); 1583 break; 1584 case SPEED_100: 1585 val |= (1<<2); 1586 break; 1587 case SPEED_1000: 1588 val |= (2<<2); 1589 break; 1590 case SPEED_2500: 1591 val |= (3<<2); 1592 break; 1593 default: 1594 DP(NETIF_MSG_LINK, "Invalid speed for UMAC %d\n", 1595 vars->line_speed); 1596 break; 1597 } 1598 if (!(vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)) 1599 val |= UMAC_COMMAND_CONFIG_REG_IGNORE_TX_PAUSE; 1600 1601 if (!(vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)) 1602 val |= UMAC_COMMAND_CONFIG_REG_PAUSE_IGNORE; 1603 1604 if (vars->duplex == DUPLEX_HALF) 1605 val |= UMAC_COMMAND_CONFIG_REG_HD_ENA; 1606 1607 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val); 1608 udelay(50); 1609 1610 /* Configure UMAC for EEE */ 1611 if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) { 1612 DP(NETIF_MSG_LINK, "configured UMAC for EEE\n"); 1613 REG_WR(bp, umac_base + UMAC_REG_UMAC_EEE_CTRL, 1614 UMAC_UMAC_EEE_CTRL_REG_EEE_EN); 1615 REG_WR(bp, umac_base + UMAC_REG_EEE_WAKE_TIMER, 0x11); 1616 } else { 1617 REG_WR(bp, umac_base + UMAC_REG_UMAC_EEE_CTRL, 0x0); 1618 } 1619 1620 /* Set MAC address for source TX Pause/PFC frames (under SW reset) */ 1621 REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR0, 1622 ((params->mac_addr[2] << 24) | 1623 (params->mac_addr[3] << 16) | 1624 (params->mac_addr[4] << 8) | 1625 (params->mac_addr[5]))); 1626 REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR1, 1627 ((params->mac_addr[0] << 8) | 1628 (params->mac_addr[1]))); 1629 1630 /* Enable RX and TX */ 1631 val &= ~UMAC_COMMAND_CONFIG_REG_PAD_EN; 1632 val |= UMAC_COMMAND_CONFIG_REG_TX_ENA | 1633 UMAC_COMMAND_CONFIG_REG_RX_ENA; 1634 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val); 1635 udelay(50); 1636 1637 /* Remove SW Reset */ 1638 val &= ~UMAC_COMMAND_CONFIG_REG_SW_RESET; 1639 1640 /* Check loopback mode */ 1641 if (lb) 1642 val |= UMAC_COMMAND_CONFIG_REG_LOOP_ENA; 1643 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val); 1644 1645 /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame 1646 * length used by the MAC receive logic to check frames. 1647 */ 1648 REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710); 1649 bnx2x_set_xumac_nig(params, 1650 ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1); 1651 vars->mac_type = MAC_TYPE_UMAC; 1652 1653 } 1654 1655 /* Define the XMAC mode */ 1656 static void bnx2x_xmac_init(struct link_params *params, u32 max_speed) 1657 { 1658 struct bnx2x *bp = params->bp; 1659 u32 is_port4mode = bnx2x_is_4_port_mode(bp); 1660 1661 /* In 4-port mode, need to set the mode only once, so if XMAC is 1662 * already out of reset, it means the mode has already been set, 1663 * and it must not* reset the XMAC again, since it controls both 1664 * ports of the path 1665 */ 1666 1667 if ((CHIP_NUM(bp) == CHIP_NUM_57840_4_10) && 1668 (REG_RD(bp, MISC_REG_RESET_REG_2) & 1669 MISC_REGISTERS_RESET_REG_2_XMAC)) { 1670 DP(NETIF_MSG_LINK, 1671 "XMAC already out of reset in 4-port mode\n"); 1672 return; 1673 } 1674 1675 /* Hard reset */ 1676 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 1677 MISC_REGISTERS_RESET_REG_2_XMAC); 1678 usleep_range(1000, 2000); 1679 1680 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 1681 MISC_REGISTERS_RESET_REG_2_XMAC); 1682 if (is_port4mode) { 1683 DP(NETIF_MSG_LINK, "Init XMAC to 2 ports x 10G per path\n"); 1684 1685 /* Set the number of ports on the system side to up to 2 */ 1686 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 1); 1687 1688 /* Set the number of ports on the Warp Core to 10G */ 1689 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3); 1690 } else { 1691 /* Set the number of ports on the system side to 1 */ 1692 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 0); 1693 if (max_speed == SPEED_10000) { 1694 DP(NETIF_MSG_LINK, 1695 "Init XMAC to 10G x 1 port per path\n"); 1696 /* Set the number of ports on the Warp Core to 10G */ 1697 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3); 1698 } else { 1699 DP(NETIF_MSG_LINK, 1700 "Init XMAC to 20G x 2 ports per path\n"); 1701 /* Set the number of ports on the Warp Core to 20G */ 1702 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 1); 1703 } 1704 } 1705 /* Soft reset */ 1706 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 1707 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT); 1708 usleep_range(1000, 2000); 1709 1710 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 1711 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT); 1712 1713 } 1714 1715 static void bnx2x_set_xmac_rxtx(struct link_params *params, u8 en) 1716 { 1717 u8 port = params->port; 1718 struct bnx2x *bp = params->bp; 1719 u32 pfc_ctrl, xmac_base = (port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; 1720 u32 val; 1721 1722 if (REG_RD(bp, MISC_REG_RESET_REG_2) & 1723 MISC_REGISTERS_RESET_REG_2_XMAC) { 1724 /* Send an indication to change the state in the NIG back to XON 1725 * Clearing this bit enables the next set of this bit to get 1726 * rising edge 1727 */ 1728 pfc_ctrl = REG_RD(bp, xmac_base + XMAC_REG_PFC_CTRL_HI); 1729 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, 1730 (pfc_ctrl & ~(1<<1))); 1731 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, 1732 (pfc_ctrl | (1<<1))); 1733 DP(NETIF_MSG_LINK, "Disable XMAC on port %x\n", port); 1734 val = REG_RD(bp, xmac_base + XMAC_REG_CTRL); 1735 if (en) 1736 val |= (XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN); 1737 else 1738 val &= ~(XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN); 1739 REG_WR(bp, xmac_base + XMAC_REG_CTRL, val); 1740 } 1741 } 1742 1743 static int bnx2x_xmac_enable(struct link_params *params, 1744 struct link_vars *vars, u8 lb) 1745 { 1746 u32 val, xmac_base; 1747 struct bnx2x *bp = params->bp; 1748 DP(NETIF_MSG_LINK, "enabling XMAC\n"); 1749 1750 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; 1751 1752 bnx2x_xmac_init(params, vars->line_speed); 1753 1754 /* This register determines on which events the MAC will assert 1755 * error on the i/f to the NIG along w/ EOP. 1756 */ 1757 1758 /* This register tells the NIG whether to send traffic to UMAC 1759 * or XMAC 1760 */ 1761 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 0); 1762 1763 /* Set Max packet size */ 1764 REG_WR(bp, xmac_base + XMAC_REG_RX_MAX_SIZE, 0x2710); 1765 1766 /* CRC append for Tx packets */ 1767 REG_WR(bp, xmac_base + XMAC_REG_TX_CTRL, 0xC800); 1768 1769 /* update PFC */ 1770 bnx2x_update_pfc_xmac(params, vars, 0); 1771 1772 if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) { 1773 DP(NETIF_MSG_LINK, "Setting XMAC for EEE\n"); 1774 REG_WR(bp, xmac_base + XMAC_REG_EEE_TIMERS_HI, 0x1380008); 1775 REG_WR(bp, xmac_base + XMAC_REG_EEE_CTRL, 0x1); 1776 } else { 1777 REG_WR(bp, xmac_base + XMAC_REG_EEE_CTRL, 0x0); 1778 } 1779 1780 /* Enable TX and RX */ 1781 val = XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN; 1782 1783 /* Check loopback mode */ 1784 if (lb) 1785 val |= XMAC_CTRL_REG_LINE_LOCAL_LPBK; 1786 REG_WR(bp, xmac_base + XMAC_REG_CTRL, val); 1787 bnx2x_set_xumac_nig(params, 1788 ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1); 1789 1790 vars->mac_type = MAC_TYPE_XMAC; 1791 1792 return 0; 1793 } 1794 1795 static int bnx2x_emac_enable(struct link_params *params, 1796 struct link_vars *vars, u8 lb) 1797 { 1798 struct bnx2x *bp = params->bp; 1799 u8 port = params->port; 1800 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; 1801 u32 val; 1802 1803 DP(NETIF_MSG_LINK, "enabling EMAC\n"); 1804 1805 /* Disable BMAC */ 1806 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 1807 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); 1808 1809 /* enable emac and not bmac */ 1810 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 1); 1811 1812 /* ASIC */ 1813 if (vars->phy_flags & PHY_XGXS_FLAG) { 1814 u32 ser_lane = ((params->lane_config & 1815 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >> 1816 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT); 1817 1818 DP(NETIF_MSG_LINK, "XGXS\n"); 1819 /* select the master lanes (out of 0-3) */ 1820 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, ser_lane); 1821 /* select XGXS */ 1822 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1); 1823 1824 } else { /* SerDes */ 1825 DP(NETIF_MSG_LINK, "SerDes\n"); 1826 /* select SerDes */ 1827 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0); 1828 } 1829 1830 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_RX_MODE, 1831 EMAC_RX_MODE_RESET); 1832 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE, 1833 EMAC_TX_MODE_RESET); 1834 1835 /* pause enable/disable */ 1836 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_RX_MODE, 1837 EMAC_RX_MODE_FLOW_EN); 1838 1839 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_TX_MODE, 1840 (EMAC_TX_MODE_EXT_PAUSE_EN | 1841 EMAC_TX_MODE_FLOW_EN)); 1842 if (!(params->feature_config_flags & 1843 FEATURE_CONFIG_PFC_ENABLED)) { 1844 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX) 1845 bnx2x_bits_en(bp, emac_base + 1846 EMAC_REG_EMAC_RX_MODE, 1847 EMAC_RX_MODE_FLOW_EN); 1848 1849 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) 1850 bnx2x_bits_en(bp, emac_base + 1851 EMAC_REG_EMAC_TX_MODE, 1852 (EMAC_TX_MODE_EXT_PAUSE_EN | 1853 EMAC_TX_MODE_FLOW_EN)); 1854 } else 1855 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE, 1856 EMAC_TX_MODE_FLOW_EN); 1857 1858 /* KEEP_VLAN_TAG, promiscuous */ 1859 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE); 1860 val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS; 1861 1862 /* Setting this bit causes MAC control frames (except for pause 1863 * frames) to be passed on for processing. This setting has no 1864 * affect on the operation of the pause frames. This bit effects 1865 * all packets regardless of RX Parser packet sorting logic. 1866 * Turn the PFC off to make sure we are in Xon state before 1867 * enabling it. 1868 */ 1869 EMAC_WR(bp, EMAC_REG_RX_PFC_MODE, 0); 1870 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) { 1871 DP(NETIF_MSG_LINK, "PFC is enabled\n"); 1872 /* Enable PFC again */ 1873 EMAC_WR(bp, EMAC_REG_RX_PFC_MODE, 1874 EMAC_REG_RX_PFC_MODE_RX_EN | 1875 EMAC_REG_RX_PFC_MODE_TX_EN | 1876 EMAC_REG_RX_PFC_MODE_PRIORITIES); 1877 1878 EMAC_WR(bp, EMAC_REG_RX_PFC_PARAM, 1879 ((0x0101 << 1880 EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT) | 1881 (0x00ff << 1882 EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT))); 1883 val |= EMAC_RX_MODE_KEEP_MAC_CONTROL; 1884 } 1885 EMAC_WR(bp, EMAC_REG_EMAC_RX_MODE, val); 1886 1887 /* Set Loopback */ 1888 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE); 1889 if (lb) 1890 val |= 0x810; 1891 else 1892 val &= ~0x810; 1893 EMAC_WR(bp, EMAC_REG_EMAC_MODE, val); 1894 1895 /* Enable emac */ 1896 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 1); 1897 1898 /* Enable emac for jumbo packets */ 1899 EMAC_WR(bp, EMAC_REG_EMAC_RX_MTU_SIZE, 1900 (EMAC_RX_MTU_SIZE_JUMBO_ENA | 1901 (ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD))); 1902 1903 /* Strip CRC */ 1904 REG_WR(bp, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1); 1905 1906 /* Disable the NIG in/out to the bmac */ 1907 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x0); 1908 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0); 1909 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x0); 1910 1911 /* Enable the NIG in/out to the emac */ 1912 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x1); 1913 val = 0; 1914 if ((params->feature_config_flags & 1915 FEATURE_CONFIG_PFC_ENABLED) || 1916 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)) 1917 val = 1; 1918 1919 REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val); 1920 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1); 1921 1922 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x0); 1923 1924 vars->mac_type = MAC_TYPE_EMAC; 1925 return 0; 1926 } 1927 1928 static void bnx2x_update_pfc_bmac1(struct link_params *params, 1929 struct link_vars *vars) 1930 { 1931 u32 wb_data[2]; 1932 struct bnx2x *bp = params->bp; 1933 u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM : 1934 NIG_REG_INGRESS_BMAC0_MEM; 1935 1936 u32 val = 0x14; 1937 if ((!(params->feature_config_flags & 1938 FEATURE_CONFIG_PFC_ENABLED)) && 1939 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)) 1940 /* Enable BigMAC to react on received Pause packets */ 1941 val |= (1<<5); 1942 wb_data[0] = val; 1943 wb_data[1] = 0; 1944 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_CONTROL, wb_data, 2); 1945 1946 /* TX control */ 1947 val = 0xc0; 1948 if (!(params->feature_config_flags & 1949 FEATURE_CONFIG_PFC_ENABLED) && 1950 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)) 1951 val |= 0x800000; 1952 wb_data[0] = val; 1953 wb_data[1] = 0; 1954 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_CONTROL, wb_data, 2); 1955 } 1956 1957 static void bnx2x_update_pfc_bmac2(struct link_params *params, 1958 struct link_vars *vars, 1959 u8 is_lb) 1960 { 1961 /* Set rx control: Strip CRC and enable BigMAC to relay 1962 * control packets to the system as well 1963 */ 1964 u32 wb_data[2]; 1965 struct bnx2x *bp = params->bp; 1966 u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM : 1967 NIG_REG_INGRESS_BMAC0_MEM; 1968 u32 val = 0x14; 1969 1970 if ((!(params->feature_config_flags & 1971 FEATURE_CONFIG_PFC_ENABLED)) && 1972 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)) 1973 /* Enable BigMAC to react on received Pause packets */ 1974 val |= (1<<5); 1975 wb_data[0] = val; 1976 wb_data[1] = 0; 1977 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_CONTROL, wb_data, 2); 1978 udelay(30); 1979 1980 /* Tx control */ 1981 val = 0xc0; 1982 if (!(params->feature_config_flags & 1983 FEATURE_CONFIG_PFC_ENABLED) && 1984 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)) 1985 val |= 0x800000; 1986 wb_data[0] = val; 1987 wb_data[1] = 0; 1988 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_CONTROL, wb_data, 2); 1989 1990 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) { 1991 DP(NETIF_MSG_LINK, "PFC is enabled\n"); 1992 /* Enable PFC RX & TX & STATS and set 8 COS */ 1993 wb_data[0] = 0x0; 1994 wb_data[0] |= (1<<0); /* RX */ 1995 wb_data[0] |= (1<<1); /* TX */ 1996 wb_data[0] |= (1<<2); /* Force initial Xon */ 1997 wb_data[0] |= (1<<3); /* 8 cos */ 1998 wb_data[0] |= (1<<5); /* STATS */ 1999 wb_data[1] = 0; 2000 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, 2001 wb_data, 2); 2002 /* Clear the force Xon */ 2003 wb_data[0] &= ~(1<<2); 2004 } else { 2005 DP(NETIF_MSG_LINK, "PFC is disabled\n"); 2006 /* Disable PFC RX & TX & STATS and set 8 COS */ 2007 wb_data[0] = 0x8; 2008 wb_data[1] = 0; 2009 } 2010 2011 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, wb_data, 2); 2012 2013 /* Set Time (based unit is 512 bit time) between automatic 2014 * re-sending of PP packets amd enable automatic re-send of 2015 * Per-Priroity Packet as long as pp_gen is asserted and 2016 * pp_disable is low. 2017 */ 2018 val = 0x8000; 2019 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) 2020 val |= (1<<16); /* enable automatic re-send */ 2021 2022 wb_data[0] = val; 2023 wb_data[1] = 0; 2024 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_PAUSE_CONTROL, 2025 wb_data, 2); 2026 2027 /* mac control */ 2028 val = 0x3; /* Enable RX and TX */ 2029 if (is_lb) { 2030 val |= 0x4; /* Local loopback */ 2031 DP(NETIF_MSG_LINK, "enable bmac loopback\n"); 2032 } 2033 /* When PFC enabled, Pass pause frames towards the NIG. */ 2034 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) 2035 val |= ((1<<6)|(1<<5)); 2036 2037 wb_data[0] = val; 2038 wb_data[1] = 0; 2039 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2); 2040 } 2041 2042 /****************************************************************************** 2043 * Description: 2044 * This function is needed because NIG ARB_CREDIT_WEIGHT_X are 2045 * not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable. 2046 ******************************************************************************/ 2047 static int bnx2x_pfc_nig_rx_priority_mask(struct bnx2x *bp, 2048 u8 cos_entry, 2049 u32 priority_mask, u8 port) 2050 { 2051 u32 nig_reg_rx_priority_mask_add = 0; 2052 2053 switch (cos_entry) { 2054 case 0: 2055 nig_reg_rx_priority_mask_add = (port) ? 2056 NIG_REG_P1_RX_COS0_PRIORITY_MASK : 2057 NIG_REG_P0_RX_COS0_PRIORITY_MASK; 2058 break; 2059 case 1: 2060 nig_reg_rx_priority_mask_add = (port) ? 2061 NIG_REG_P1_RX_COS1_PRIORITY_MASK : 2062 NIG_REG_P0_RX_COS1_PRIORITY_MASK; 2063 break; 2064 case 2: 2065 nig_reg_rx_priority_mask_add = (port) ? 2066 NIG_REG_P1_RX_COS2_PRIORITY_MASK : 2067 NIG_REG_P0_RX_COS2_PRIORITY_MASK; 2068 break; 2069 case 3: 2070 if (port) 2071 return -EINVAL; 2072 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS3_PRIORITY_MASK; 2073 break; 2074 case 4: 2075 if (port) 2076 return -EINVAL; 2077 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS4_PRIORITY_MASK; 2078 break; 2079 case 5: 2080 if (port) 2081 return -EINVAL; 2082 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS5_PRIORITY_MASK; 2083 break; 2084 } 2085 2086 REG_WR(bp, nig_reg_rx_priority_mask_add, priority_mask); 2087 2088 return 0; 2089 } 2090 static void bnx2x_update_mng(struct link_params *params, u32 link_status) 2091 { 2092 struct bnx2x *bp = params->bp; 2093 2094 REG_WR(bp, params->shmem_base + 2095 offsetof(struct shmem_region, 2096 port_mb[params->port].link_status), link_status); 2097 } 2098 2099 static void bnx2x_update_pfc_nig(struct link_params *params, 2100 struct link_vars *vars, 2101 struct bnx2x_nig_brb_pfc_port_params *nig_params) 2102 { 2103 u32 xcm_mask = 0, ppp_enable = 0, pause_enable = 0, llfc_out_en = 0; 2104 u32 llfc_enable = 0, xcm_out_en = 0, hwpfc_enable = 0; 2105 u32 pkt_priority_to_cos = 0; 2106 struct bnx2x *bp = params->bp; 2107 u8 port = params->port; 2108 2109 int set_pfc = params->feature_config_flags & 2110 FEATURE_CONFIG_PFC_ENABLED; 2111 DP(NETIF_MSG_LINK, "updating pfc nig parameters\n"); 2112 2113 /* When NIG_LLH0_XCM_MASK_REG_LLHX_XCM_MASK_BCN bit is set 2114 * MAC control frames (that are not pause packets) 2115 * will be forwarded to the XCM. 2116 */ 2117 xcm_mask = REG_RD(bp, port ? NIG_REG_LLH1_XCM_MASK : 2118 NIG_REG_LLH0_XCM_MASK); 2119 /* NIG params will override non PFC params, since it's possible to 2120 * do transition from PFC to SAFC 2121 */ 2122 if (set_pfc) { 2123 pause_enable = 0; 2124 llfc_out_en = 0; 2125 llfc_enable = 0; 2126 if (CHIP_IS_E3(bp)) 2127 ppp_enable = 0; 2128 else 2129 ppp_enable = 1; 2130 xcm_mask &= ~(port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN : 2131 NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN); 2132 xcm_out_en = 0; 2133 hwpfc_enable = 1; 2134 } else { 2135 if (nig_params) { 2136 llfc_out_en = nig_params->llfc_out_en; 2137 llfc_enable = nig_params->llfc_enable; 2138 pause_enable = nig_params->pause_enable; 2139 } else /* Default non PFC mode - PAUSE */ 2140 pause_enable = 1; 2141 2142 xcm_mask |= (port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN : 2143 NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN); 2144 xcm_out_en = 1; 2145 } 2146 2147 if (CHIP_IS_E3(bp)) 2148 REG_WR(bp, port ? NIG_REG_BRB1_PAUSE_IN_EN : 2149 NIG_REG_BRB0_PAUSE_IN_EN, pause_enable); 2150 REG_WR(bp, port ? NIG_REG_LLFC_OUT_EN_1 : 2151 NIG_REG_LLFC_OUT_EN_0, llfc_out_en); 2152 REG_WR(bp, port ? NIG_REG_LLFC_ENABLE_1 : 2153 NIG_REG_LLFC_ENABLE_0, llfc_enable); 2154 REG_WR(bp, port ? NIG_REG_PAUSE_ENABLE_1 : 2155 NIG_REG_PAUSE_ENABLE_0, pause_enable); 2156 2157 REG_WR(bp, port ? NIG_REG_PPP_ENABLE_1 : 2158 NIG_REG_PPP_ENABLE_0, ppp_enable); 2159 2160 REG_WR(bp, port ? NIG_REG_LLH1_XCM_MASK : 2161 NIG_REG_LLH0_XCM_MASK, xcm_mask); 2162 2163 REG_WR(bp, port ? NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 : 2164 NIG_REG_LLFC_EGRESS_SRC_ENABLE_0, 0x7); 2165 2166 /* Output enable for RX_XCM # IF */ 2167 REG_WR(bp, port ? NIG_REG_XCM1_OUT_EN : 2168 NIG_REG_XCM0_OUT_EN, xcm_out_en); 2169 2170 /* HW PFC TX enable */ 2171 REG_WR(bp, port ? NIG_REG_P1_HWPFC_ENABLE : 2172 NIG_REG_P0_HWPFC_ENABLE, hwpfc_enable); 2173 2174 if (nig_params) { 2175 u8 i = 0; 2176 pkt_priority_to_cos = nig_params->pkt_priority_to_cos; 2177 2178 for (i = 0; i < nig_params->num_of_rx_cos_priority_mask; i++) 2179 bnx2x_pfc_nig_rx_priority_mask(bp, i, 2180 nig_params->rx_cos_priority_mask[i], port); 2181 2182 REG_WR(bp, port ? NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 : 2183 NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0, 2184 nig_params->llfc_high_priority_classes); 2185 2186 REG_WR(bp, port ? NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 : 2187 NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0, 2188 nig_params->llfc_low_priority_classes); 2189 } 2190 REG_WR(bp, port ? NIG_REG_P1_PKT_PRIORITY_TO_COS : 2191 NIG_REG_P0_PKT_PRIORITY_TO_COS, 2192 pkt_priority_to_cos); 2193 } 2194 2195 int bnx2x_update_pfc(struct link_params *params, 2196 struct link_vars *vars, 2197 struct bnx2x_nig_brb_pfc_port_params *pfc_params) 2198 { 2199 /* The PFC and pause are orthogonal to one another, meaning when 2200 * PFC is enabled, the pause are disabled, and when PFC is 2201 * disabled, pause are set according to the pause result. 2202 */ 2203 u32 val; 2204 struct bnx2x *bp = params->bp; 2205 int bnx2x_status = 0; 2206 u8 bmac_loopback = (params->loopback_mode == LOOPBACK_BMAC); 2207 2208 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) 2209 vars->link_status |= LINK_STATUS_PFC_ENABLED; 2210 else 2211 vars->link_status &= ~LINK_STATUS_PFC_ENABLED; 2212 2213 bnx2x_update_mng(params, vars->link_status); 2214 2215 /* Update NIG params */ 2216 bnx2x_update_pfc_nig(params, vars, pfc_params); 2217 2218 if (!vars->link_up) 2219 return bnx2x_status; 2220 2221 DP(NETIF_MSG_LINK, "About to update PFC in BMAC\n"); 2222 2223 if (CHIP_IS_E3(bp)) { 2224 if (vars->mac_type == MAC_TYPE_XMAC) 2225 bnx2x_update_pfc_xmac(params, vars, 0); 2226 } else { 2227 val = REG_RD(bp, MISC_REG_RESET_REG_2); 2228 if ((val & 2229 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port)) 2230 == 0) { 2231 DP(NETIF_MSG_LINK, "About to update PFC in EMAC\n"); 2232 bnx2x_emac_enable(params, vars, 0); 2233 return bnx2x_status; 2234 } 2235 if (CHIP_IS_E2(bp)) 2236 bnx2x_update_pfc_bmac2(params, vars, bmac_loopback); 2237 else 2238 bnx2x_update_pfc_bmac1(params, vars); 2239 2240 val = 0; 2241 if ((params->feature_config_flags & 2242 FEATURE_CONFIG_PFC_ENABLED) || 2243 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)) 2244 val = 1; 2245 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port*4, val); 2246 } 2247 return bnx2x_status; 2248 } 2249 2250 2251 static int bnx2x_bmac1_enable(struct link_params *params, 2252 struct link_vars *vars, 2253 u8 is_lb) 2254 { 2255 struct bnx2x *bp = params->bp; 2256 u8 port = params->port; 2257 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM : 2258 NIG_REG_INGRESS_BMAC0_MEM; 2259 u32 wb_data[2]; 2260 u32 val; 2261 2262 DP(NETIF_MSG_LINK, "Enabling BigMAC1\n"); 2263 2264 /* XGXS control */ 2265 wb_data[0] = 0x3c; 2266 wb_data[1] = 0; 2267 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_XGXS_CONTROL, 2268 wb_data, 2); 2269 2270 /* TX MAC SA */ 2271 wb_data[0] = ((params->mac_addr[2] << 24) | 2272 (params->mac_addr[3] << 16) | 2273 (params->mac_addr[4] << 8) | 2274 params->mac_addr[5]); 2275 wb_data[1] = ((params->mac_addr[0] << 8) | 2276 params->mac_addr[1]); 2277 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR, wb_data, 2); 2278 2279 /* MAC control */ 2280 val = 0x3; 2281 if (is_lb) { 2282 val |= 0x4; 2283 DP(NETIF_MSG_LINK, "enable bmac loopback\n"); 2284 } 2285 wb_data[0] = val; 2286 wb_data[1] = 0; 2287 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL, wb_data, 2); 2288 2289 /* Set rx mtu */ 2290 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD; 2291 wb_data[1] = 0; 2292 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE, wb_data, 2); 2293 2294 bnx2x_update_pfc_bmac1(params, vars); 2295 2296 /* Set tx mtu */ 2297 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD; 2298 wb_data[1] = 0; 2299 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE, wb_data, 2); 2300 2301 /* Set cnt max size */ 2302 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD; 2303 wb_data[1] = 0; 2304 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE, wb_data, 2); 2305 2306 /* Configure SAFC */ 2307 wb_data[0] = 0x1000200; 2308 wb_data[1] = 0; 2309 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS, 2310 wb_data, 2); 2311 2312 return 0; 2313 } 2314 2315 static int bnx2x_bmac2_enable(struct link_params *params, 2316 struct link_vars *vars, 2317 u8 is_lb) 2318 { 2319 struct bnx2x *bp = params->bp; 2320 u8 port = params->port; 2321 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM : 2322 NIG_REG_INGRESS_BMAC0_MEM; 2323 u32 wb_data[2]; 2324 2325 DP(NETIF_MSG_LINK, "Enabling BigMAC2\n"); 2326 2327 wb_data[0] = 0; 2328 wb_data[1] = 0; 2329 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2); 2330 udelay(30); 2331 2332 /* XGXS control: Reset phy HW, MDIO registers, PHY PLL and BMAC */ 2333 wb_data[0] = 0x3c; 2334 wb_data[1] = 0; 2335 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_XGXS_CONTROL, 2336 wb_data, 2); 2337 2338 udelay(30); 2339 2340 /* TX MAC SA */ 2341 wb_data[0] = ((params->mac_addr[2] << 24) | 2342 (params->mac_addr[3] << 16) | 2343 (params->mac_addr[4] << 8) | 2344 params->mac_addr[5]); 2345 wb_data[1] = ((params->mac_addr[0] << 8) | 2346 params->mac_addr[1]); 2347 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_SOURCE_ADDR, 2348 wb_data, 2); 2349 2350 udelay(30); 2351 2352 /* Configure SAFC */ 2353 wb_data[0] = 0x1000200; 2354 wb_data[1] = 0; 2355 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS, 2356 wb_data, 2); 2357 udelay(30); 2358 2359 /* Set RX MTU */ 2360 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD; 2361 wb_data[1] = 0; 2362 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_MAX_SIZE, wb_data, 2); 2363 udelay(30); 2364 2365 /* Set TX MTU */ 2366 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD; 2367 wb_data[1] = 0; 2368 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_MAX_SIZE, wb_data, 2); 2369 udelay(30); 2370 /* Set cnt max size */ 2371 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD - 2; 2372 wb_data[1] = 0; 2373 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_CNT_MAX_SIZE, wb_data, 2); 2374 udelay(30); 2375 bnx2x_update_pfc_bmac2(params, vars, is_lb); 2376 2377 return 0; 2378 } 2379 2380 static int bnx2x_bmac_enable(struct link_params *params, 2381 struct link_vars *vars, 2382 u8 is_lb, u8 reset_bmac) 2383 { 2384 int rc = 0; 2385 u8 port = params->port; 2386 struct bnx2x *bp = params->bp; 2387 u32 val; 2388 /* Reset and unreset the BigMac */ 2389 if (reset_bmac) { 2390 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 2391 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); 2392 usleep_range(1000, 2000); 2393 } 2394 2395 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 2396 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); 2397 2398 /* Enable access for bmac registers */ 2399 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1); 2400 2401 /* Enable BMAC according to BMAC type*/ 2402 if (CHIP_IS_E2(bp)) 2403 rc = bnx2x_bmac2_enable(params, vars, is_lb); 2404 else 2405 rc = bnx2x_bmac1_enable(params, vars, is_lb); 2406 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1); 2407 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0); 2408 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0); 2409 val = 0; 2410 if ((params->feature_config_flags & 2411 FEATURE_CONFIG_PFC_ENABLED) || 2412 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)) 2413 val = 1; 2414 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val); 2415 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0); 2416 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x0); 2417 REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0); 2418 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x1); 2419 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x1); 2420 2421 vars->mac_type = MAC_TYPE_BMAC; 2422 return rc; 2423 } 2424 2425 static void bnx2x_set_bmac_rx(struct bnx2x *bp, u32 chip_id, u8 port, u8 en) 2426 { 2427 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM : 2428 NIG_REG_INGRESS_BMAC0_MEM; 2429 u32 wb_data[2]; 2430 u32 nig_bmac_enable = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4); 2431 2432 if (CHIP_IS_E2(bp)) 2433 bmac_addr += BIGMAC2_REGISTER_BMAC_CONTROL; 2434 else 2435 bmac_addr += BIGMAC_REGISTER_BMAC_CONTROL; 2436 /* Only if the bmac is out of reset */ 2437 if (REG_RD(bp, MISC_REG_RESET_REG_2) & 2438 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) && 2439 nig_bmac_enable) { 2440 /* Clear Rx Enable bit in BMAC_CONTROL register */ 2441 REG_RD_DMAE(bp, bmac_addr, wb_data, 2); 2442 if (en) 2443 wb_data[0] |= BMAC_CONTROL_RX_ENABLE; 2444 else 2445 wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE; 2446 REG_WR_DMAE(bp, bmac_addr, wb_data, 2); 2447 usleep_range(1000, 2000); 2448 } 2449 } 2450 2451 static int bnx2x_pbf_update(struct link_params *params, u32 flow_ctrl, 2452 u32 line_speed) 2453 { 2454 struct bnx2x *bp = params->bp; 2455 u8 port = params->port; 2456 u32 init_crd, crd; 2457 u32 count = 1000; 2458 2459 /* Disable port */ 2460 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1); 2461 2462 /* Wait for init credit */ 2463 init_crd = REG_RD(bp, PBF_REG_P0_INIT_CRD + port*4); 2464 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8); 2465 DP(NETIF_MSG_LINK, "init_crd 0x%x crd 0x%x\n", init_crd, crd); 2466 2467 while ((init_crd != crd) && count) { 2468 usleep_range(5000, 10000); 2469 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8); 2470 count--; 2471 } 2472 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8); 2473 if (init_crd != crd) { 2474 DP(NETIF_MSG_LINK, "BUG! init_crd 0x%x != crd 0x%x\n", 2475 init_crd, crd); 2476 return -EINVAL; 2477 } 2478 2479 if (flow_ctrl & BNX2X_FLOW_CTRL_RX || 2480 line_speed == SPEED_10 || 2481 line_speed == SPEED_100 || 2482 line_speed == SPEED_1000 || 2483 line_speed == SPEED_2500) { 2484 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 1); 2485 /* Update threshold */ 2486 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, 0); 2487 /* Update init credit */ 2488 init_crd = 778; /* (800-18-4) */ 2489 2490 } else { 2491 u32 thresh = (ETH_MAX_JUMBO_PACKET_SIZE + 2492 ETH_OVREHEAD)/16; 2493 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0); 2494 /* Update threshold */ 2495 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, thresh); 2496 /* Update init credit */ 2497 switch (line_speed) { 2498 case SPEED_10000: 2499 init_crd = thresh + 553 - 22; 2500 break; 2501 default: 2502 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n", 2503 line_speed); 2504 return -EINVAL; 2505 } 2506 } 2507 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, init_crd); 2508 DP(NETIF_MSG_LINK, "PBF updated to speed %d credit %d\n", 2509 line_speed, init_crd); 2510 2511 /* Probe the credit changes */ 2512 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x1); 2513 usleep_range(5000, 10000); 2514 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x0); 2515 2516 /* Enable port */ 2517 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0); 2518 return 0; 2519 } 2520 2521 /** 2522 * bnx2x_get_emac_base - retrive emac base address 2523 * 2524 * @bp: driver handle 2525 * @mdc_mdio_access: access type 2526 * @port: port id 2527 * 2528 * This function selects the MDC/MDIO access (through emac0 or 2529 * emac1) depend on the mdc_mdio_access, port, port swapped. Each 2530 * phy has a default access mode, which could also be overridden 2531 * by nvram configuration. This parameter, whether this is the 2532 * default phy configuration, or the nvram overrun 2533 * configuration, is passed here as mdc_mdio_access and selects 2534 * the emac_base for the CL45 read/writes operations 2535 */ 2536 static u32 bnx2x_get_emac_base(struct bnx2x *bp, 2537 u32 mdc_mdio_access, u8 port) 2538 { 2539 u32 emac_base = 0; 2540 switch (mdc_mdio_access) { 2541 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE: 2542 break; 2543 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0: 2544 if (REG_RD(bp, NIG_REG_PORT_SWAP)) 2545 emac_base = GRCBASE_EMAC1; 2546 else 2547 emac_base = GRCBASE_EMAC0; 2548 break; 2549 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1: 2550 if (REG_RD(bp, NIG_REG_PORT_SWAP)) 2551 emac_base = GRCBASE_EMAC0; 2552 else 2553 emac_base = GRCBASE_EMAC1; 2554 break; 2555 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH: 2556 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0; 2557 break; 2558 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED: 2559 emac_base = (port) ? GRCBASE_EMAC0 : GRCBASE_EMAC1; 2560 break; 2561 default: 2562 break; 2563 } 2564 return emac_base; 2565 2566 } 2567 2568 /******************************************************************/ 2569 /* CL22 access functions */ 2570 /******************************************************************/ 2571 static int bnx2x_cl22_write(struct bnx2x *bp, 2572 struct bnx2x_phy *phy, 2573 u16 reg, u16 val) 2574 { 2575 u32 tmp, mode; 2576 u8 i; 2577 int rc = 0; 2578 /* Switch to CL22 */ 2579 mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE); 2580 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, 2581 mode & ~EMAC_MDIO_MODE_CLAUSE_45); 2582 2583 /* Address */ 2584 tmp = ((phy->addr << 21) | (reg << 16) | val | 2585 EMAC_MDIO_COMM_COMMAND_WRITE_22 | 2586 EMAC_MDIO_COMM_START_BUSY); 2587 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); 2588 2589 for (i = 0; i < 50; i++) { 2590 udelay(10); 2591 2592 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); 2593 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) { 2594 udelay(5); 2595 break; 2596 } 2597 } 2598 if (tmp & EMAC_MDIO_COMM_START_BUSY) { 2599 DP(NETIF_MSG_LINK, "write phy register failed\n"); 2600 rc = -EFAULT; 2601 } 2602 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode); 2603 return rc; 2604 } 2605 2606 static int bnx2x_cl22_read(struct bnx2x *bp, 2607 struct bnx2x_phy *phy, 2608 u16 reg, u16 *ret_val) 2609 { 2610 u32 val, mode; 2611 u16 i; 2612 int rc = 0; 2613 2614 /* Switch to CL22 */ 2615 mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE); 2616 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, 2617 mode & ~EMAC_MDIO_MODE_CLAUSE_45); 2618 2619 /* Address */ 2620 val = ((phy->addr << 21) | (reg << 16) | 2621 EMAC_MDIO_COMM_COMMAND_READ_22 | 2622 EMAC_MDIO_COMM_START_BUSY); 2623 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); 2624 2625 for (i = 0; i < 50; i++) { 2626 udelay(10); 2627 2628 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); 2629 if (!(val & EMAC_MDIO_COMM_START_BUSY)) { 2630 *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA); 2631 udelay(5); 2632 break; 2633 } 2634 } 2635 if (val & EMAC_MDIO_COMM_START_BUSY) { 2636 DP(NETIF_MSG_LINK, "read phy register failed\n"); 2637 2638 *ret_val = 0; 2639 rc = -EFAULT; 2640 } 2641 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode); 2642 return rc; 2643 } 2644 2645 /******************************************************************/ 2646 /* CL45 access functions */ 2647 /******************************************************************/ 2648 static int bnx2x_cl45_read(struct bnx2x *bp, struct bnx2x_phy *phy, 2649 u8 devad, u16 reg, u16 *ret_val) 2650 { 2651 u32 val; 2652 u16 i; 2653 int rc = 0; 2654 if (phy->flags & FLAGS_MDC_MDIO_WA_B0) 2655 bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, 2656 EMAC_MDIO_STATUS_10MB); 2657 /* Address */ 2658 val = ((phy->addr << 21) | (devad << 16) | reg | 2659 EMAC_MDIO_COMM_COMMAND_ADDRESS | 2660 EMAC_MDIO_COMM_START_BUSY); 2661 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); 2662 2663 for (i = 0; i < 50; i++) { 2664 udelay(10); 2665 2666 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); 2667 if (!(val & EMAC_MDIO_COMM_START_BUSY)) { 2668 udelay(5); 2669 break; 2670 } 2671 } 2672 if (val & EMAC_MDIO_COMM_START_BUSY) { 2673 DP(NETIF_MSG_LINK, "read phy register failed\n"); 2674 netdev_err(bp->dev, "MDC/MDIO access timeout\n"); 2675 *ret_val = 0; 2676 rc = -EFAULT; 2677 } else { 2678 /* Data */ 2679 val = ((phy->addr << 21) | (devad << 16) | 2680 EMAC_MDIO_COMM_COMMAND_READ_45 | 2681 EMAC_MDIO_COMM_START_BUSY); 2682 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); 2683 2684 for (i = 0; i < 50; i++) { 2685 udelay(10); 2686 2687 val = REG_RD(bp, phy->mdio_ctrl + 2688 EMAC_REG_EMAC_MDIO_COMM); 2689 if (!(val & EMAC_MDIO_COMM_START_BUSY)) { 2690 *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA); 2691 break; 2692 } 2693 } 2694 if (val & EMAC_MDIO_COMM_START_BUSY) { 2695 DP(NETIF_MSG_LINK, "read phy register failed\n"); 2696 netdev_err(bp->dev, "MDC/MDIO access timeout\n"); 2697 *ret_val = 0; 2698 rc = -EFAULT; 2699 } 2700 } 2701 /* Work around for E3 A0 */ 2702 if (phy->flags & FLAGS_MDC_MDIO_WA) { 2703 phy->flags ^= FLAGS_DUMMY_READ; 2704 if (phy->flags & FLAGS_DUMMY_READ) { 2705 u16 temp_val; 2706 bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val); 2707 } 2708 } 2709 2710 if (phy->flags & FLAGS_MDC_MDIO_WA_B0) 2711 bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, 2712 EMAC_MDIO_STATUS_10MB); 2713 return rc; 2714 } 2715 2716 static int bnx2x_cl45_write(struct bnx2x *bp, struct bnx2x_phy *phy, 2717 u8 devad, u16 reg, u16 val) 2718 { 2719 u32 tmp; 2720 u8 i; 2721 int rc = 0; 2722 if (phy->flags & FLAGS_MDC_MDIO_WA_B0) 2723 bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, 2724 EMAC_MDIO_STATUS_10MB); 2725 2726 /* Address */ 2727 tmp = ((phy->addr << 21) | (devad << 16) | reg | 2728 EMAC_MDIO_COMM_COMMAND_ADDRESS | 2729 EMAC_MDIO_COMM_START_BUSY); 2730 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); 2731 2732 for (i = 0; i < 50; i++) { 2733 udelay(10); 2734 2735 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); 2736 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) { 2737 udelay(5); 2738 break; 2739 } 2740 } 2741 if (tmp & EMAC_MDIO_COMM_START_BUSY) { 2742 DP(NETIF_MSG_LINK, "write phy register failed\n"); 2743 netdev_err(bp->dev, "MDC/MDIO access timeout\n"); 2744 rc = -EFAULT; 2745 } else { 2746 /* Data */ 2747 tmp = ((phy->addr << 21) | (devad << 16) | val | 2748 EMAC_MDIO_COMM_COMMAND_WRITE_45 | 2749 EMAC_MDIO_COMM_START_BUSY); 2750 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); 2751 2752 for (i = 0; i < 50; i++) { 2753 udelay(10); 2754 2755 tmp = REG_RD(bp, phy->mdio_ctrl + 2756 EMAC_REG_EMAC_MDIO_COMM); 2757 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) { 2758 udelay(5); 2759 break; 2760 } 2761 } 2762 if (tmp & EMAC_MDIO_COMM_START_BUSY) { 2763 DP(NETIF_MSG_LINK, "write phy register failed\n"); 2764 netdev_err(bp->dev, "MDC/MDIO access timeout\n"); 2765 rc = -EFAULT; 2766 } 2767 } 2768 /* Work around for E3 A0 */ 2769 if (phy->flags & FLAGS_MDC_MDIO_WA) { 2770 phy->flags ^= FLAGS_DUMMY_READ; 2771 if (phy->flags & FLAGS_DUMMY_READ) { 2772 u16 temp_val; 2773 bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val); 2774 } 2775 } 2776 if (phy->flags & FLAGS_MDC_MDIO_WA_B0) 2777 bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, 2778 EMAC_MDIO_STATUS_10MB); 2779 return rc; 2780 } 2781 2782 /******************************************************************/ 2783 /* EEE section */ 2784 /******************************************************************/ 2785 static u8 bnx2x_eee_has_cap(struct link_params *params) 2786 { 2787 struct bnx2x *bp = params->bp; 2788 2789 if (REG_RD(bp, params->shmem2_base) <= 2790 offsetof(struct shmem2_region, eee_status[params->port])) 2791 return 0; 2792 2793 return 1; 2794 } 2795 2796 static int bnx2x_eee_nvram_to_time(u32 nvram_mode, u32 *idle_timer) 2797 { 2798 switch (nvram_mode) { 2799 case PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED: 2800 *idle_timer = EEE_MODE_NVRAM_BALANCED_TIME; 2801 break; 2802 case PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE: 2803 *idle_timer = EEE_MODE_NVRAM_AGGRESSIVE_TIME; 2804 break; 2805 case PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY: 2806 *idle_timer = EEE_MODE_NVRAM_LATENCY_TIME; 2807 break; 2808 default: 2809 *idle_timer = 0; 2810 break; 2811 } 2812 2813 return 0; 2814 } 2815 2816 static int bnx2x_eee_time_to_nvram(u32 idle_timer, u32 *nvram_mode) 2817 { 2818 switch (idle_timer) { 2819 case EEE_MODE_NVRAM_BALANCED_TIME: 2820 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED; 2821 break; 2822 case EEE_MODE_NVRAM_AGGRESSIVE_TIME: 2823 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE; 2824 break; 2825 case EEE_MODE_NVRAM_LATENCY_TIME: 2826 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY; 2827 break; 2828 default: 2829 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED; 2830 break; 2831 } 2832 2833 return 0; 2834 } 2835 2836 static u32 bnx2x_eee_calc_timer(struct link_params *params) 2837 { 2838 u32 eee_mode, eee_idle; 2839 struct bnx2x *bp = params->bp; 2840 2841 if (params->eee_mode & EEE_MODE_OVERRIDE_NVRAM) { 2842 if (params->eee_mode & EEE_MODE_OUTPUT_TIME) { 2843 /* time value in eee_mode --> used directly*/ 2844 eee_idle = params->eee_mode & EEE_MODE_TIMER_MASK; 2845 } else { 2846 /* hsi value in eee_mode --> time */ 2847 if (bnx2x_eee_nvram_to_time(params->eee_mode & 2848 EEE_MODE_NVRAM_MASK, 2849 &eee_idle)) 2850 return 0; 2851 } 2852 } else { 2853 /* hsi values in nvram --> time*/ 2854 eee_mode = ((REG_RD(bp, params->shmem_base + 2855 offsetof(struct shmem_region, dev_info. 2856 port_feature_config[params->port]. 2857 eee_power_mode)) & 2858 PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >> 2859 PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT); 2860 2861 if (bnx2x_eee_nvram_to_time(eee_mode, &eee_idle)) 2862 return 0; 2863 } 2864 2865 return eee_idle; 2866 } 2867 2868 static int bnx2x_eee_set_timers(struct link_params *params, 2869 struct link_vars *vars) 2870 { 2871 u32 eee_idle = 0, eee_mode; 2872 struct bnx2x *bp = params->bp; 2873 2874 eee_idle = bnx2x_eee_calc_timer(params); 2875 2876 if (eee_idle) { 2877 REG_WR(bp, MISC_REG_CPMU_LP_IDLE_THR_P0 + (params->port << 2), 2878 eee_idle); 2879 } else if ((params->eee_mode & EEE_MODE_ENABLE_LPI) && 2880 (params->eee_mode & EEE_MODE_OVERRIDE_NVRAM) && 2881 (params->eee_mode & EEE_MODE_OUTPUT_TIME)) { 2882 DP(NETIF_MSG_LINK, "Error: Tx LPI is enabled with timer 0\n"); 2883 return -EINVAL; 2884 } 2885 2886 vars->eee_status &= ~(SHMEM_EEE_TIMER_MASK | SHMEM_EEE_TIME_OUTPUT_BIT); 2887 if (params->eee_mode & EEE_MODE_OUTPUT_TIME) { 2888 /* eee_idle in 1u --> eee_status in 16u */ 2889 eee_idle >>= 4; 2890 vars->eee_status |= (eee_idle & SHMEM_EEE_TIMER_MASK) | 2891 SHMEM_EEE_TIME_OUTPUT_BIT; 2892 } else { 2893 if (bnx2x_eee_time_to_nvram(eee_idle, &eee_mode)) 2894 return -EINVAL; 2895 vars->eee_status |= eee_mode; 2896 } 2897 2898 return 0; 2899 } 2900 2901 static int bnx2x_eee_initial_config(struct link_params *params, 2902 struct link_vars *vars, u8 mode) 2903 { 2904 vars->eee_status |= ((u32) mode) << SHMEM_EEE_SUPPORTED_SHIFT; 2905 2906 /* Propogate params' bits --> vars (for migration exposure) */ 2907 if (params->eee_mode & EEE_MODE_ENABLE_LPI) 2908 vars->eee_status |= SHMEM_EEE_LPI_REQUESTED_BIT; 2909 else 2910 vars->eee_status &= ~SHMEM_EEE_LPI_REQUESTED_BIT; 2911 2912 if (params->eee_mode & EEE_MODE_ADV_LPI) 2913 vars->eee_status |= SHMEM_EEE_REQUESTED_BIT; 2914 else 2915 vars->eee_status &= ~SHMEM_EEE_REQUESTED_BIT; 2916 2917 return bnx2x_eee_set_timers(params, vars); 2918 } 2919 2920 static int bnx2x_eee_disable(struct bnx2x_phy *phy, 2921 struct link_params *params, 2922 struct link_vars *vars) 2923 { 2924 struct bnx2x *bp = params->bp; 2925 2926 /* Make Certain LPI is disabled */ 2927 REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2), 0); 2928 2929 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, 0x0); 2930 2931 vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK; 2932 2933 return 0; 2934 } 2935 2936 static int bnx2x_eee_advertise(struct bnx2x_phy *phy, 2937 struct link_params *params, 2938 struct link_vars *vars, u8 modes) 2939 { 2940 struct bnx2x *bp = params->bp; 2941 u16 val = 0; 2942 2943 /* Mask events preventing LPI generation */ 2944 REG_WR(bp, MISC_REG_CPMU_LP_MASK_EXT_P0 + (params->port << 2), 0xfc20); 2945 2946 if (modes & SHMEM_EEE_10G_ADV) { 2947 DP(NETIF_MSG_LINK, "Advertise 10GBase-T EEE\n"); 2948 val |= 0x8; 2949 } 2950 if (modes & SHMEM_EEE_1G_ADV) { 2951 DP(NETIF_MSG_LINK, "Advertise 1GBase-T EEE\n"); 2952 val |= 0x4; 2953 } 2954 2955 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, val); 2956 2957 vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK; 2958 vars->eee_status |= (modes << SHMEM_EEE_ADV_STATUS_SHIFT); 2959 2960 return 0; 2961 } 2962 2963 static void bnx2x_update_mng_eee(struct link_params *params, u32 eee_status) 2964 { 2965 struct bnx2x *bp = params->bp; 2966 2967 if (bnx2x_eee_has_cap(params)) 2968 REG_WR(bp, params->shmem2_base + 2969 offsetof(struct shmem2_region, 2970 eee_status[params->port]), eee_status); 2971 } 2972 2973 static void bnx2x_eee_an_resolve(struct bnx2x_phy *phy, 2974 struct link_params *params, 2975 struct link_vars *vars) 2976 { 2977 struct bnx2x *bp = params->bp; 2978 u16 adv = 0, lp = 0; 2979 u32 lp_adv = 0; 2980 u8 neg = 0; 2981 2982 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, &adv); 2983 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_LP_EEE_ADV, &lp); 2984 2985 if (lp & 0x2) { 2986 lp_adv |= SHMEM_EEE_100M_ADV; 2987 if (adv & 0x2) { 2988 if (vars->line_speed == SPEED_100) 2989 neg = 1; 2990 DP(NETIF_MSG_LINK, "EEE negotiated - 100M\n"); 2991 } 2992 } 2993 if (lp & 0x14) { 2994 lp_adv |= SHMEM_EEE_1G_ADV; 2995 if (adv & 0x14) { 2996 if (vars->line_speed == SPEED_1000) 2997 neg = 1; 2998 DP(NETIF_MSG_LINK, "EEE negotiated - 1G\n"); 2999 } 3000 } 3001 if (lp & 0x68) { 3002 lp_adv |= SHMEM_EEE_10G_ADV; 3003 if (adv & 0x68) { 3004 if (vars->line_speed == SPEED_10000) 3005 neg = 1; 3006 DP(NETIF_MSG_LINK, "EEE negotiated - 10G\n"); 3007 } 3008 } 3009 3010 vars->eee_status &= ~SHMEM_EEE_LP_ADV_STATUS_MASK; 3011 vars->eee_status |= (lp_adv << SHMEM_EEE_LP_ADV_STATUS_SHIFT); 3012 3013 if (neg) { 3014 DP(NETIF_MSG_LINK, "EEE is active\n"); 3015 vars->eee_status |= SHMEM_EEE_ACTIVE_BIT; 3016 } 3017 3018 } 3019 3020 /******************************************************************/ 3021 /* BSC access functions from E3 */ 3022 /******************************************************************/ 3023 static void bnx2x_bsc_module_sel(struct link_params *params) 3024 { 3025 int idx; 3026 u32 board_cfg, sfp_ctrl; 3027 u32 i2c_pins[I2C_SWITCH_WIDTH], i2c_val[I2C_SWITCH_WIDTH]; 3028 struct bnx2x *bp = params->bp; 3029 u8 port = params->port; 3030 /* Read I2C output PINs */ 3031 board_cfg = REG_RD(bp, params->shmem_base + 3032 offsetof(struct shmem_region, 3033 dev_info.shared_hw_config.board)); 3034 i2c_pins[I2C_BSC0] = board_cfg & SHARED_HW_CFG_E3_I2C_MUX0_MASK; 3035 i2c_pins[I2C_BSC1] = (board_cfg & SHARED_HW_CFG_E3_I2C_MUX1_MASK) >> 3036 SHARED_HW_CFG_E3_I2C_MUX1_SHIFT; 3037 3038 /* Read I2C output value */ 3039 sfp_ctrl = REG_RD(bp, params->shmem_base + 3040 offsetof(struct shmem_region, 3041 dev_info.port_hw_config[port].e3_cmn_pin_cfg)); 3042 i2c_val[I2C_BSC0] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX0_MASK) > 0; 3043 i2c_val[I2C_BSC1] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX1_MASK) > 0; 3044 DP(NETIF_MSG_LINK, "Setting BSC switch\n"); 3045 for (idx = 0; idx < I2C_SWITCH_WIDTH; idx++) 3046 bnx2x_set_cfg_pin(bp, i2c_pins[idx], i2c_val[idx]); 3047 } 3048 3049 static int bnx2x_bsc_read(struct link_params *params, 3050 struct bnx2x_phy *phy, 3051 u8 sl_devid, 3052 u16 sl_addr, 3053 u8 lc_addr, 3054 u8 xfer_cnt, 3055 u32 *data_array) 3056 { 3057 u32 val, i; 3058 int rc = 0; 3059 struct bnx2x *bp = params->bp; 3060 3061 if ((sl_devid != 0xa0) && (sl_devid != 0xa2)) { 3062 DP(NETIF_MSG_LINK, "invalid sl_devid 0x%x\n", sl_devid); 3063 return -EINVAL; 3064 } 3065 3066 if (xfer_cnt > 16) { 3067 DP(NETIF_MSG_LINK, "invalid xfer_cnt %d. Max is 16 bytes\n", 3068 xfer_cnt); 3069 return -EINVAL; 3070 } 3071 bnx2x_bsc_module_sel(params); 3072 3073 xfer_cnt = 16 - lc_addr; 3074 3075 /* Enable the engine */ 3076 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND); 3077 val |= MCPR_IMC_COMMAND_ENABLE; 3078 REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val); 3079 3080 /* Program slave device ID */ 3081 val = (sl_devid << 16) | sl_addr; 3082 REG_WR(bp, MCP_REG_MCPR_IMC_SLAVE_CONTROL, val); 3083 3084 /* Start xfer with 0 byte to update the address pointer ???*/ 3085 val = (MCPR_IMC_COMMAND_ENABLE) | 3086 (MCPR_IMC_COMMAND_WRITE_OP << 3087 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) | 3088 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) | (0); 3089 REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val); 3090 3091 /* Poll for completion */ 3092 i = 0; 3093 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND); 3094 while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) { 3095 udelay(10); 3096 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND); 3097 if (i++ > 1000) { 3098 DP(NETIF_MSG_LINK, "wr 0 byte timed out after %d try\n", 3099 i); 3100 rc = -EFAULT; 3101 break; 3102 } 3103 } 3104 if (rc == -EFAULT) 3105 return rc; 3106 3107 /* Start xfer with read op */ 3108 val = (MCPR_IMC_COMMAND_ENABLE) | 3109 (MCPR_IMC_COMMAND_READ_OP << 3110 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) | 3111 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) | 3112 (xfer_cnt); 3113 REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val); 3114 3115 /* Poll for completion */ 3116 i = 0; 3117 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND); 3118 while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) { 3119 udelay(10); 3120 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND); 3121 if (i++ > 1000) { 3122 DP(NETIF_MSG_LINK, "rd op timed out after %d try\n", i); 3123 rc = -EFAULT; 3124 break; 3125 } 3126 } 3127 if (rc == -EFAULT) 3128 return rc; 3129 3130 for (i = (lc_addr >> 2); i < 4; i++) { 3131 data_array[i] = REG_RD(bp, (MCP_REG_MCPR_IMC_DATAREG0 + i*4)); 3132 #ifdef __BIG_ENDIAN 3133 data_array[i] = ((data_array[i] & 0x000000ff) << 24) | 3134 ((data_array[i] & 0x0000ff00) << 8) | 3135 ((data_array[i] & 0x00ff0000) >> 8) | 3136 ((data_array[i] & 0xff000000) >> 24); 3137 #endif 3138 } 3139 return rc; 3140 } 3141 3142 static void bnx2x_cl45_read_or_write(struct bnx2x *bp, struct bnx2x_phy *phy, 3143 u8 devad, u16 reg, u16 or_val) 3144 { 3145 u16 val; 3146 bnx2x_cl45_read(bp, phy, devad, reg, &val); 3147 bnx2x_cl45_write(bp, phy, devad, reg, val | or_val); 3148 } 3149 3150 int bnx2x_phy_read(struct link_params *params, u8 phy_addr, 3151 u8 devad, u16 reg, u16 *ret_val) 3152 { 3153 u8 phy_index; 3154 /* Probe for the phy according to the given phy_addr, and execute 3155 * the read request on it 3156 */ 3157 for (phy_index = 0; phy_index < params->num_phys; phy_index++) { 3158 if (params->phy[phy_index].addr == phy_addr) { 3159 return bnx2x_cl45_read(params->bp, 3160 ¶ms->phy[phy_index], devad, 3161 reg, ret_val); 3162 } 3163 } 3164 return -EINVAL; 3165 } 3166 3167 int bnx2x_phy_write(struct link_params *params, u8 phy_addr, 3168 u8 devad, u16 reg, u16 val) 3169 { 3170 u8 phy_index; 3171 /* Probe for the phy according to the given phy_addr, and execute 3172 * the write request on it 3173 */ 3174 for (phy_index = 0; phy_index < params->num_phys; phy_index++) { 3175 if (params->phy[phy_index].addr == phy_addr) { 3176 return bnx2x_cl45_write(params->bp, 3177 ¶ms->phy[phy_index], devad, 3178 reg, val); 3179 } 3180 } 3181 return -EINVAL; 3182 } 3183 static u8 bnx2x_get_warpcore_lane(struct bnx2x_phy *phy, 3184 struct link_params *params) 3185 { 3186 u8 lane = 0; 3187 struct bnx2x *bp = params->bp; 3188 u32 path_swap, path_swap_ovr; 3189 u8 path, port; 3190 3191 path = BP_PATH(bp); 3192 port = params->port; 3193 3194 if (bnx2x_is_4_port_mode(bp)) { 3195 u32 port_swap, port_swap_ovr; 3196 3197 /* Figure out path swap value */ 3198 path_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP_OVWR); 3199 if (path_swap_ovr & 0x1) 3200 path_swap = (path_swap_ovr & 0x2); 3201 else 3202 path_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP); 3203 3204 if (path_swap) 3205 path = path ^ 1; 3206 3207 /* Figure out port swap value */ 3208 port_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP_OVWR); 3209 if (port_swap_ovr & 0x1) 3210 port_swap = (port_swap_ovr & 0x2); 3211 else 3212 port_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP); 3213 3214 if (port_swap) 3215 port = port ^ 1; 3216 3217 lane = (port<<1) + path; 3218 } else { /* Two port mode - no port swap */ 3219 3220 /* Figure out path swap value */ 3221 path_swap_ovr = 3222 REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP_OVWR); 3223 if (path_swap_ovr & 0x1) { 3224 path_swap = (path_swap_ovr & 0x2); 3225 } else { 3226 path_swap = 3227 REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP); 3228 } 3229 if (path_swap) 3230 path = path ^ 1; 3231 3232 lane = path << 1 ; 3233 } 3234 return lane; 3235 } 3236 3237 static void bnx2x_set_aer_mmd(struct link_params *params, 3238 struct bnx2x_phy *phy) 3239 { 3240 u32 ser_lane; 3241 u16 offset, aer_val; 3242 struct bnx2x *bp = params->bp; 3243 ser_lane = ((params->lane_config & 3244 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >> 3245 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT); 3246 3247 offset = (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ? 3248 (phy->addr + ser_lane) : 0; 3249 3250 if (USES_WARPCORE(bp)) { 3251 aer_val = bnx2x_get_warpcore_lane(phy, params); 3252 /* In Dual-lane mode, two lanes are joined together, 3253 * so in order to configure them, the AER broadcast method is 3254 * used here. 3255 * 0x200 is the broadcast address for lanes 0,1 3256 * 0x201 is the broadcast address for lanes 2,3 3257 */ 3258 if (phy->flags & FLAGS_WC_DUAL_MODE) 3259 aer_val = (aer_val >> 1) | 0x200; 3260 } else if (CHIP_IS_E2(bp)) 3261 aer_val = 0x3800 + offset - 1; 3262 else 3263 aer_val = 0x3800 + offset; 3264 3265 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, 3266 MDIO_AER_BLOCK_AER_REG, aer_val); 3267 3268 } 3269 3270 /******************************************************************/ 3271 /* Internal phy section */ 3272 /******************************************************************/ 3273 3274 static void bnx2x_set_serdes_access(struct bnx2x *bp, u8 port) 3275 { 3276 u32 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0; 3277 3278 /* Set Clause 22 */ 3279 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 1); 3280 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000); 3281 udelay(500); 3282 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f); 3283 udelay(500); 3284 /* Set Clause 45 */ 3285 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 0); 3286 } 3287 3288 static void bnx2x_serdes_deassert(struct bnx2x *bp, u8 port) 3289 { 3290 u32 val; 3291 3292 DP(NETIF_MSG_LINK, "bnx2x_serdes_deassert\n"); 3293 3294 val = SERDES_RESET_BITS << (port*16); 3295 3296 /* Reset and unreset the SerDes/XGXS */ 3297 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val); 3298 udelay(500); 3299 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val); 3300 3301 bnx2x_set_serdes_access(bp, port); 3302 3303 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_DEVAD + port*0x10, 3304 DEFAULT_PHY_DEV_ADDR); 3305 } 3306 3307 static void bnx2x_xgxs_specific_func(struct bnx2x_phy *phy, 3308 struct link_params *params, 3309 u32 action) 3310 { 3311 struct bnx2x *bp = params->bp; 3312 switch (action) { 3313 case PHY_INIT: 3314 /* Set correct devad */ 3315 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_ST + params->port*0x18, 0); 3316 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + params->port*0x18, 3317 phy->def_md_devad); 3318 break; 3319 } 3320 } 3321 3322 static void bnx2x_xgxs_deassert(struct link_params *params) 3323 { 3324 struct bnx2x *bp = params->bp; 3325 u8 port; 3326 u32 val; 3327 DP(NETIF_MSG_LINK, "bnx2x_xgxs_deassert\n"); 3328 port = params->port; 3329 3330 val = XGXS_RESET_BITS << (port*16); 3331 3332 /* Reset and unreset the SerDes/XGXS */ 3333 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val); 3334 udelay(500); 3335 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val); 3336 bnx2x_xgxs_specific_func(¶ms->phy[INT_PHY], params, 3337 PHY_INIT); 3338 } 3339 3340 static void bnx2x_calc_ieee_aneg_adv(struct bnx2x_phy *phy, 3341 struct link_params *params, u16 *ieee_fc) 3342 { 3343 struct bnx2x *bp = params->bp; 3344 *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX; 3345 /* Resolve pause mode and advertisement Please refer to Table 3346 * 28B-3 of the 802.3ab-1999 spec 3347 */ 3348 3349 switch (phy->req_flow_ctrl) { 3350 case BNX2X_FLOW_CTRL_AUTO: 3351 if (params->req_fc_auto_adv == BNX2X_FLOW_CTRL_BOTH) 3352 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; 3353 else 3354 *ieee_fc |= 3355 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC; 3356 break; 3357 3358 case BNX2X_FLOW_CTRL_TX: 3359 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC; 3360 break; 3361 3362 case BNX2X_FLOW_CTRL_RX: 3363 case BNX2X_FLOW_CTRL_BOTH: 3364 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; 3365 break; 3366 3367 case BNX2X_FLOW_CTRL_NONE: 3368 default: 3369 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE; 3370 break; 3371 } 3372 DP(NETIF_MSG_LINK, "ieee_fc = 0x%x\n", *ieee_fc); 3373 } 3374 3375 static void set_phy_vars(struct link_params *params, 3376 struct link_vars *vars) 3377 { 3378 struct bnx2x *bp = params->bp; 3379 u8 actual_phy_idx, phy_index, link_cfg_idx; 3380 u8 phy_config_swapped = params->multi_phy_config & 3381 PORT_HW_CFG_PHY_SWAPPED_ENABLED; 3382 for (phy_index = INT_PHY; phy_index < params->num_phys; 3383 phy_index++) { 3384 link_cfg_idx = LINK_CONFIG_IDX(phy_index); 3385 actual_phy_idx = phy_index; 3386 if (phy_config_swapped) { 3387 if (phy_index == EXT_PHY1) 3388 actual_phy_idx = EXT_PHY2; 3389 else if (phy_index == EXT_PHY2) 3390 actual_phy_idx = EXT_PHY1; 3391 } 3392 params->phy[actual_phy_idx].req_flow_ctrl = 3393 params->req_flow_ctrl[link_cfg_idx]; 3394 3395 params->phy[actual_phy_idx].req_line_speed = 3396 params->req_line_speed[link_cfg_idx]; 3397 3398 params->phy[actual_phy_idx].speed_cap_mask = 3399 params->speed_cap_mask[link_cfg_idx]; 3400 3401 params->phy[actual_phy_idx].req_duplex = 3402 params->req_duplex[link_cfg_idx]; 3403 3404 if (params->req_line_speed[link_cfg_idx] == 3405 SPEED_AUTO_NEG) 3406 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED; 3407 3408 DP(NETIF_MSG_LINK, "req_flow_ctrl %x, req_line_speed %x," 3409 " speed_cap_mask %x\n", 3410 params->phy[actual_phy_idx].req_flow_ctrl, 3411 params->phy[actual_phy_idx].req_line_speed, 3412 params->phy[actual_phy_idx].speed_cap_mask); 3413 } 3414 } 3415 3416 static void bnx2x_ext_phy_set_pause(struct link_params *params, 3417 struct bnx2x_phy *phy, 3418 struct link_vars *vars) 3419 { 3420 u16 val; 3421 struct bnx2x *bp = params->bp; 3422 /* Read modify write pause advertizing */ 3423 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &val); 3424 3425 val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH; 3426 3427 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */ 3428 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); 3429 if ((vars->ieee_fc & 3430 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) == 3431 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) { 3432 val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC; 3433 } 3434 if ((vars->ieee_fc & 3435 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) == 3436 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) { 3437 val |= MDIO_AN_REG_ADV_PAUSE_PAUSE; 3438 } 3439 DP(NETIF_MSG_LINK, "Ext phy AN advertize 0x%x\n", val); 3440 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val); 3441 } 3442 3443 static void bnx2x_pause_resolve(struct link_vars *vars, u32 pause_result) 3444 { /* LD LP */ 3445 switch (pause_result) { /* ASYM P ASYM P */ 3446 case 0xb: /* 1 0 1 1 */ 3447 vars->flow_ctrl = BNX2X_FLOW_CTRL_TX; 3448 break; 3449 3450 case 0xe: /* 1 1 1 0 */ 3451 vars->flow_ctrl = BNX2X_FLOW_CTRL_RX; 3452 break; 3453 3454 case 0x5: /* 0 1 0 1 */ 3455 case 0x7: /* 0 1 1 1 */ 3456 case 0xd: /* 1 1 0 1 */ 3457 case 0xf: /* 1 1 1 1 */ 3458 vars->flow_ctrl = BNX2X_FLOW_CTRL_BOTH; 3459 break; 3460 3461 default: 3462 break; 3463 } 3464 if (pause_result & (1<<0)) 3465 vars->link_status |= LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE; 3466 if (pause_result & (1<<1)) 3467 vars->link_status |= LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE; 3468 3469 } 3470 3471 static void bnx2x_ext_phy_update_adv_fc(struct bnx2x_phy *phy, 3472 struct link_params *params, 3473 struct link_vars *vars) 3474 { 3475 u16 ld_pause; /* local */ 3476 u16 lp_pause; /* link partner */ 3477 u16 pause_result; 3478 struct bnx2x *bp = params->bp; 3479 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) { 3480 bnx2x_cl22_read(bp, phy, 0x4, &ld_pause); 3481 bnx2x_cl22_read(bp, phy, 0x5, &lp_pause); 3482 } else if (CHIP_IS_E3(bp) && 3483 SINGLE_MEDIA_DIRECT(params)) { 3484 u8 lane = bnx2x_get_warpcore_lane(phy, params); 3485 u16 gp_status, gp_mask; 3486 bnx2x_cl45_read(bp, phy, 3487 MDIO_AN_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_4, 3488 &gp_status); 3489 gp_mask = (MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL | 3490 MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP) << 3491 lane; 3492 if ((gp_status & gp_mask) == gp_mask) { 3493 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, 3494 MDIO_AN_REG_ADV_PAUSE, &ld_pause); 3495 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, 3496 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause); 3497 } else { 3498 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, 3499 MDIO_AN_REG_CL37_FC_LD, &ld_pause); 3500 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, 3501 MDIO_AN_REG_CL37_FC_LP, &lp_pause); 3502 ld_pause = ((ld_pause & 3503 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) 3504 << 3); 3505 lp_pause = ((lp_pause & 3506 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) 3507 << 3); 3508 } 3509 } else { 3510 bnx2x_cl45_read(bp, phy, 3511 MDIO_AN_DEVAD, 3512 MDIO_AN_REG_ADV_PAUSE, &ld_pause); 3513 bnx2x_cl45_read(bp, phy, 3514 MDIO_AN_DEVAD, 3515 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause); 3516 } 3517 pause_result = (ld_pause & 3518 MDIO_AN_REG_ADV_PAUSE_MASK) >> 8; 3519 pause_result |= (lp_pause & 3520 MDIO_AN_REG_ADV_PAUSE_MASK) >> 10; 3521 DP(NETIF_MSG_LINK, "Ext PHY pause result 0x%x\n", pause_result); 3522 bnx2x_pause_resolve(vars, pause_result); 3523 3524 } 3525 3526 static u8 bnx2x_ext_phy_resolve_fc(struct bnx2x_phy *phy, 3527 struct link_params *params, 3528 struct link_vars *vars) 3529 { 3530 u8 ret = 0; 3531 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; 3532 if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO) { 3533 /* Update the advertised flow-controled of LD/LP in AN */ 3534 if (phy->req_line_speed == SPEED_AUTO_NEG) 3535 bnx2x_ext_phy_update_adv_fc(phy, params, vars); 3536 /* But set the flow-control result as the requested one */ 3537 vars->flow_ctrl = phy->req_flow_ctrl; 3538 } else if (phy->req_line_speed != SPEED_AUTO_NEG) 3539 vars->flow_ctrl = params->req_fc_auto_adv; 3540 else if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) { 3541 ret = 1; 3542 bnx2x_ext_phy_update_adv_fc(phy, params, vars); 3543 } 3544 return ret; 3545 } 3546 /******************************************************************/ 3547 /* Warpcore section */ 3548 /******************************************************************/ 3549 /* The init_internal_warpcore should mirror the xgxs, 3550 * i.e. reset the lane (if needed), set aer for the 3551 * init configuration, and set/clear SGMII flag. Internal 3552 * phy init is done purely in phy_init stage. 3553 */ 3554 3555 static void bnx2x_warpcore_set_lpi_passthrough(struct bnx2x_phy *phy, 3556 struct link_params *params) 3557 { 3558 struct bnx2x *bp = params->bp; 3559 3560 DP(NETIF_MSG_LINK, "Configure WC for LPI pass through\n"); 3561 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3562 MDIO_WC_REG_EEE_COMBO_CONTROL0, 0x7c); 3563 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 3564 MDIO_WC_REG_DIGITAL4_MISC5, 0xc000); 3565 } 3566 3567 static void bnx2x_warpcore_enable_AN_KR(struct bnx2x_phy *phy, 3568 struct link_params *params, 3569 struct link_vars *vars) { 3570 u16 lane, i, cl72_ctrl, an_adv = 0; 3571 u16 ucode_ver; 3572 struct bnx2x *bp = params->bp; 3573 static struct bnx2x_reg_set reg_set[] = { 3574 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7}, 3575 {MDIO_PMA_DEVAD, MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0x0}, 3576 {MDIO_WC_DEVAD, MDIO_WC_REG_RX66_CONTROL, 0x7415}, 3577 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x6190}, 3578 /* Disable Autoneg: re-enable it after adv is done. */ 3579 {MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0} 3580 }; 3581 DP(NETIF_MSG_LINK, "Enable Auto Negotiation for KR\n"); 3582 /* Set to default registers that may be overriden by 10G force */ 3583 for (i = 0; i < sizeof(reg_set)/sizeof(struct bnx2x_reg_set); i++) 3584 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg, 3585 reg_set[i].val); 3586 3587 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 3588 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, &cl72_ctrl); 3589 cl72_ctrl &= 0xf8ff; 3590 cl72_ctrl |= 0x3800; 3591 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3592 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, cl72_ctrl); 3593 3594 /* Check adding advertisement for 1G KX */ 3595 if (((vars->line_speed == SPEED_AUTO_NEG) && 3596 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) || 3597 (vars->line_speed == SPEED_1000)) { 3598 u32 addr = MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2; 3599 an_adv |= (1<<5); 3600 3601 /* Enable CL37 1G Parallel Detect */ 3602 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, addr, 0x1); 3603 DP(NETIF_MSG_LINK, "Advertize 1G\n"); 3604 } 3605 if (((vars->line_speed == SPEED_AUTO_NEG) && 3606 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) || 3607 (vars->line_speed == SPEED_10000)) { 3608 /* Check adding advertisement for 10G KR */ 3609 an_adv |= (1<<7); 3610 /* Enable 10G Parallel Detect */ 3611 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, 3612 MDIO_AER_BLOCK_AER_REG, 0); 3613 3614 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, 3615 MDIO_WC_REG_PAR_DET_10G_CTRL, 1); 3616 bnx2x_set_aer_mmd(params, phy); 3617 DP(NETIF_MSG_LINK, "Advertize 10G\n"); 3618 } 3619 3620 /* Set Transmit PMD settings */ 3621 lane = bnx2x_get_warpcore_lane(phy, params); 3622 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3623 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 3624 ((0x02 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) | 3625 (0x06 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) | 3626 (0x09 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET))); 3627 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3628 MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL, 3629 0x03f0); 3630 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3631 MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL, 3632 0x03f0); 3633 3634 /* Advertised speeds */ 3635 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, 3636 MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, an_adv); 3637 3638 /* Advertised and set FEC (Forward Error Correction) */ 3639 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, 3640 MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2, 3641 (MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY | 3642 MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ)); 3643 3644 /* Enable CL37 BAM */ 3645 if (REG_RD(bp, params->shmem_base + 3646 offsetof(struct shmem_region, dev_info. 3647 port_hw_config[params->port].default_cfg)) & 3648 PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) { 3649 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 3650 MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL, 3651 1); 3652 DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n"); 3653 } 3654 3655 /* Advertise pause */ 3656 bnx2x_ext_phy_set_pause(params, phy, vars); 3657 /* Set KR Autoneg Work-Around flag for Warpcore version older than D108 3658 */ 3659 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 3660 MDIO_WC_REG_UC_INFO_B1_VERSION, &ucode_ver); 3661 if (ucode_ver < 0xd108) { 3662 DP(NETIF_MSG_LINK, "Enable AN KR work-around. WC ver:0x%x\n", 3663 ucode_ver); 3664 vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY; 3665 } 3666 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 3667 MDIO_WC_REG_DIGITAL5_MISC7, 0x100); 3668 3669 /* Over 1G - AN local device user page 1 */ 3670 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3671 MDIO_WC_REG_DIGITAL3_UP1, 0x1f); 3672 3673 /* Enable Autoneg */ 3674 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, 3675 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200); 3676 3677 } 3678 3679 static void bnx2x_warpcore_set_10G_KR(struct bnx2x_phy *phy, 3680 struct link_params *params, 3681 struct link_vars *vars) 3682 { 3683 struct bnx2x *bp = params->bp; 3684 u16 val16, i, lane; 3685 static struct bnx2x_reg_set reg_set[] = { 3686 /* Disable Autoneg */ 3687 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7}, 3688 {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, 3689 0x3f00}, 3690 {MDIO_AN_DEVAD, MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, 0}, 3691 {MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0}, 3692 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL3_UP1, 0x1}, 3693 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL5_MISC7, 0xa}, 3694 /* Leave cl72 training enable, needed for KR */ 3695 {MDIO_PMA_DEVAD, 3696 MDIO_WC_REG_PMD_IEEE9BLK_TENGBASE_KR_PMD_CONTROL_REGISTER_150, 3697 0x2} 3698 }; 3699 3700 for (i = 0; i < sizeof(reg_set)/sizeof(struct bnx2x_reg_set); i++) 3701 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg, 3702 reg_set[i].val); 3703 3704 lane = bnx2x_get_warpcore_lane(phy, params); 3705 /* Global registers */ 3706 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, 3707 MDIO_AER_BLOCK_AER_REG, 0); 3708 /* Disable CL36 PCS Tx */ 3709 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 3710 MDIO_WC_REG_XGXSBLK1_LANECTRL0, &val16); 3711 val16 &= ~(0x0011 << lane); 3712 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3713 MDIO_WC_REG_XGXSBLK1_LANECTRL0, val16); 3714 3715 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 3716 MDIO_WC_REG_XGXSBLK1_LANECTRL1, &val16); 3717 val16 |= (0x0303 << (lane << 1)); 3718 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3719 MDIO_WC_REG_XGXSBLK1_LANECTRL1, val16); 3720 /* Restore AER */ 3721 bnx2x_set_aer_mmd(params, phy); 3722 /* Set speed via PMA/PMD register */ 3723 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 3724 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040); 3725 3726 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 3727 MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0xB); 3728 3729 /* Enable encoded forced speed */ 3730 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3731 MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x30); 3732 3733 /* Turn TX scramble payload only the 64/66 scrambler */ 3734 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3735 MDIO_WC_REG_TX66_CONTROL, 0x9); 3736 3737 /* Turn RX scramble payload only the 64/66 scrambler */ 3738 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 3739 MDIO_WC_REG_RX66_CONTROL, 0xF9); 3740 3741 /* Set and clear loopback to cause a reset to 64/66 decoder */ 3742 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3743 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x4000); 3744 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3745 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0); 3746 3747 } 3748 3749 static void bnx2x_warpcore_set_10G_XFI(struct bnx2x_phy *phy, 3750 struct link_params *params, 3751 u8 is_xfi) 3752 { 3753 struct bnx2x *bp = params->bp; 3754 u16 misc1_val, tap_val, tx_driver_val, lane, val; 3755 /* Hold rxSeqStart */ 3756 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 3757 MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x8000); 3758 3759 /* Hold tx_fifo_reset */ 3760 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 3761 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, 0x1); 3762 3763 /* Disable CL73 AN */ 3764 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0); 3765 3766 /* Disable 100FX Enable and Auto-Detect */ 3767 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 3768 MDIO_WC_REG_FX100_CTRL1, &val); 3769 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3770 MDIO_WC_REG_FX100_CTRL1, (val & 0xFFFA)); 3771 3772 /* Disable 100FX Idle detect */ 3773 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 3774 MDIO_WC_REG_FX100_CTRL3, 0x0080); 3775 3776 /* Set Block address to Remote PHY & Clear forced_speed[5] */ 3777 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 3778 MDIO_WC_REG_DIGITAL4_MISC3, &val); 3779 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3780 MDIO_WC_REG_DIGITAL4_MISC3, (val & 0xFF7F)); 3781 3782 /* Turn off auto-detect & fiber mode */ 3783 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 3784 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &val); 3785 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3786 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 3787 (val & 0xFFEE)); 3788 3789 /* Set filter_force_link, disable_false_link and parallel_detect */ 3790 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 3791 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &val); 3792 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3793 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 3794 ((val | 0x0006) & 0xFFFE)); 3795 3796 /* Set XFI / SFI */ 3797 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 3798 MDIO_WC_REG_SERDESDIGITAL_MISC1, &misc1_val); 3799 3800 misc1_val &= ~(0x1f); 3801 3802 if (is_xfi) { 3803 misc1_val |= 0x5; 3804 tap_val = ((0x08 << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) | 3805 (0x37 << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) | 3806 (0x00 << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET)); 3807 tx_driver_val = 3808 ((0x00 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) | 3809 (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) | 3810 (0x03 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET)); 3811 3812 } else { 3813 misc1_val |= 0x9; 3814 tap_val = ((0x0f << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) | 3815 (0x2b << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) | 3816 (0x02 << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET)); 3817 tx_driver_val = 3818 ((0x03 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) | 3819 (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) | 3820 (0x06 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET)); 3821 } 3822 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3823 MDIO_WC_REG_SERDESDIGITAL_MISC1, misc1_val); 3824 3825 /* Set Transmit PMD settings */ 3826 lane = bnx2x_get_warpcore_lane(phy, params); 3827 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3828 MDIO_WC_REG_TX_FIR_TAP, 3829 tap_val | MDIO_WC_REG_TX_FIR_TAP_ENABLE); 3830 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3831 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 3832 tx_driver_val); 3833 3834 /* Enable fiber mode, enable and invert sig_det */ 3835 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 3836 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0xd); 3837 3838 /* Set Block address to Remote PHY & Set forced_speed[5], 40bit mode */ 3839 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 3840 MDIO_WC_REG_DIGITAL4_MISC3, 0x8080); 3841 3842 bnx2x_warpcore_set_lpi_passthrough(phy, params); 3843 3844 /* 10G XFI Full Duplex */ 3845 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3846 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x100); 3847 3848 /* Release tx_fifo_reset */ 3849 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 3850 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, &val); 3851 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3852 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, val & 0xFFFE); 3853 3854 /* Release rxSeqStart */ 3855 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 3856 MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, &val); 3857 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3858 MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, (val & 0x7FFF)); 3859 } 3860 3861 static void bnx2x_warpcore_set_20G_KR2(struct bnx2x *bp, 3862 struct bnx2x_phy *phy) 3863 { 3864 DP(NETIF_MSG_LINK, "KR2 still not supported !!!\n"); 3865 } 3866 3867 static void bnx2x_warpcore_set_20G_DXGXS(struct bnx2x *bp, 3868 struct bnx2x_phy *phy, 3869 u16 lane) 3870 { 3871 /* Rx0 anaRxControl1G */ 3872 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3873 MDIO_WC_REG_RX0_ANARXCONTROL1G, 0x90); 3874 3875 /* Rx2 anaRxControl1G */ 3876 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3877 MDIO_WC_REG_RX2_ANARXCONTROL1G, 0x90); 3878 3879 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3880 MDIO_WC_REG_RX66_SCW0, 0xE070); 3881 3882 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3883 MDIO_WC_REG_RX66_SCW1, 0xC0D0); 3884 3885 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3886 MDIO_WC_REG_RX66_SCW2, 0xA0B0); 3887 3888 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3889 MDIO_WC_REG_RX66_SCW3, 0x8090); 3890 3891 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3892 MDIO_WC_REG_RX66_SCW0_MASK, 0xF0F0); 3893 3894 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3895 MDIO_WC_REG_RX66_SCW1_MASK, 0xF0F0); 3896 3897 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3898 MDIO_WC_REG_RX66_SCW2_MASK, 0xF0F0); 3899 3900 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3901 MDIO_WC_REG_RX66_SCW3_MASK, 0xF0F0); 3902 3903 /* Serdes Digital Misc1 */ 3904 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3905 MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6008); 3906 3907 /* Serdes Digital4 Misc3 */ 3908 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3909 MDIO_WC_REG_DIGITAL4_MISC3, 0x8088); 3910 3911 /* Set Transmit PMD settings */ 3912 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3913 MDIO_WC_REG_TX_FIR_TAP, 3914 ((0x12 << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) | 3915 (0x2d << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) | 3916 (0x00 << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET) | 3917 MDIO_WC_REG_TX_FIR_TAP_ENABLE)); 3918 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3919 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 3920 ((0x02 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) | 3921 (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) | 3922 (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET))); 3923 } 3924 3925 static void bnx2x_warpcore_set_sgmii_speed(struct bnx2x_phy *phy, 3926 struct link_params *params, 3927 u8 fiber_mode, 3928 u8 always_autoneg) 3929 { 3930 struct bnx2x *bp = params->bp; 3931 u16 val16, digctrl_kx1, digctrl_kx2; 3932 3933 /* Clear XFI clock comp in non-10G single lane mode. */ 3934 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 3935 MDIO_WC_REG_RX66_CONTROL, &val16); 3936 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3937 MDIO_WC_REG_RX66_CONTROL, val16 & ~(3<<13)); 3938 3939 bnx2x_warpcore_set_lpi_passthrough(phy, params); 3940 3941 if (always_autoneg || phy->req_line_speed == SPEED_AUTO_NEG) { 3942 /* SGMII Autoneg */ 3943 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 3944 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16); 3945 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3946 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 3947 val16 | 0x1000); 3948 DP(NETIF_MSG_LINK, "set SGMII AUTONEG\n"); 3949 } else { 3950 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 3951 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16); 3952 val16 &= 0xcebf; 3953 switch (phy->req_line_speed) { 3954 case SPEED_10: 3955 break; 3956 case SPEED_100: 3957 val16 |= 0x2000; 3958 break; 3959 case SPEED_1000: 3960 val16 |= 0x0040; 3961 break; 3962 default: 3963 DP(NETIF_MSG_LINK, 3964 "Speed not supported: 0x%x\n", phy->req_line_speed); 3965 return; 3966 } 3967 3968 if (phy->req_duplex == DUPLEX_FULL) 3969 val16 |= 0x0100; 3970 3971 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3972 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16); 3973 3974 DP(NETIF_MSG_LINK, "set SGMII force speed %d\n", 3975 phy->req_line_speed); 3976 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 3977 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16); 3978 DP(NETIF_MSG_LINK, " (readback) %x\n", val16); 3979 } 3980 3981 /* SGMII Slave mode and disable signal detect */ 3982 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 3983 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &digctrl_kx1); 3984 if (fiber_mode) 3985 digctrl_kx1 = 1; 3986 else 3987 digctrl_kx1 &= 0xff4a; 3988 3989 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3990 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 3991 digctrl_kx1); 3992 3993 /* Turn off parallel detect */ 3994 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 3995 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &digctrl_kx2); 3996 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3997 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 3998 (digctrl_kx2 & ~(1<<2))); 3999 4000 /* Re-enable parallel detect */ 4001 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4002 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 4003 (digctrl_kx2 | (1<<2))); 4004 4005 /* Enable autodet */ 4006 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4007 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 4008 (digctrl_kx1 | 0x10)); 4009 } 4010 4011 static void bnx2x_warpcore_reset_lane(struct bnx2x *bp, 4012 struct bnx2x_phy *phy, 4013 u8 reset) 4014 { 4015 u16 val; 4016 /* Take lane out of reset after configuration is finished */ 4017 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 4018 MDIO_WC_REG_DIGITAL5_MISC6, &val); 4019 if (reset) 4020 val |= 0xC000; 4021 else 4022 val &= 0x3FFF; 4023 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4024 MDIO_WC_REG_DIGITAL5_MISC6, val); 4025 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 4026 MDIO_WC_REG_DIGITAL5_MISC6, &val); 4027 } 4028 /* Clear SFI/XFI link settings registers */ 4029 static void bnx2x_warpcore_clear_regs(struct bnx2x_phy *phy, 4030 struct link_params *params, 4031 u16 lane) 4032 { 4033 struct bnx2x *bp = params->bp; 4034 u16 i; 4035 static struct bnx2x_reg_set wc_regs[] = { 4036 {MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0}, 4037 {MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL1, 0x014a}, 4038 {MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL3, 0x0800}, 4039 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL4_MISC3, 0x8008}, 4040 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 4041 0x0195}, 4042 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 4043 0x0007}, 4044 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, 4045 0x0002}, 4046 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6000}, 4047 {MDIO_WC_DEVAD, MDIO_WC_REG_TX_FIR_TAP, 0x0000}, 4048 {MDIO_WC_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040}, 4049 {MDIO_WC_DEVAD, MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0x0140} 4050 }; 4051 /* Set XFI clock comp as default. */ 4052 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 4053 MDIO_WC_REG_RX66_CONTROL, (3<<13)); 4054 4055 for (i = 0; i < sizeof(wc_regs)/sizeof(struct bnx2x_reg_set); i++) 4056 bnx2x_cl45_write(bp, phy, wc_regs[i].devad, wc_regs[i].reg, 4057 wc_regs[i].val); 4058 4059 lane = bnx2x_get_warpcore_lane(phy, params); 4060 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4061 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 0x0990); 4062 4063 } 4064 4065 static int bnx2x_get_mod_abs_int_cfg(struct bnx2x *bp, 4066 u32 chip_id, 4067 u32 shmem_base, u8 port, 4068 u8 *gpio_num, u8 *gpio_port) 4069 { 4070 u32 cfg_pin; 4071 *gpio_num = 0; 4072 *gpio_port = 0; 4073 if (CHIP_IS_E3(bp)) { 4074 cfg_pin = (REG_RD(bp, shmem_base + 4075 offsetof(struct shmem_region, 4076 dev_info.port_hw_config[port].e3_sfp_ctrl)) & 4077 PORT_HW_CFG_E3_MOD_ABS_MASK) >> 4078 PORT_HW_CFG_E3_MOD_ABS_SHIFT; 4079 4080 /* Should not happen. This function called upon interrupt 4081 * triggered by GPIO ( since EPIO can only generate interrupts 4082 * to MCP). 4083 * So if this function was called and none of the GPIOs was set, 4084 * it means the shit hit the fan. 4085 */ 4086 if ((cfg_pin < PIN_CFG_GPIO0_P0) || 4087 (cfg_pin > PIN_CFG_GPIO3_P1)) { 4088 DP(NETIF_MSG_LINK, 4089 "ERROR: Invalid cfg pin %x for module detect indication\n", 4090 cfg_pin); 4091 return -EINVAL; 4092 } 4093 4094 *gpio_num = (cfg_pin - PIN_CFG_GPIO0_P0) & 0x3; 4095 *gpio_port = (cfg_pin - PIN_CFG_GPIO0_P0) >> 2; 4096 } else { 4097 *gpio_num = MISC_REGISTERS_GPIO_3; 4098 *gpio_port = port; 4099 } 4100 DP(NETIF_MSG_LINK, "MOD_ABS int GPIO%d_P%d\n", *gpio_num, *gpio_port); 4101 return 0; 4102 } 4103 4104 static int bnx2x_is_sfp_module_plugged(struct bnx2x_phy *phy, 4105 struct link_params *params) 4106 { 4107 struct bnx2x *bp = params->bp; 4108 u8 gpio_num, gpio_port; 4109 u32 gpio_val; 4110 if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id, 4111 params->shmem_base, params->port, 4112 &gpio_num, &gpio_port) != 0) 4113 return 0; 4114 gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port); 4115 4116 /* Call the handling function in case module is detected */ 4117 if (gpio_val == 0) 4118 return 1; 4119 else 4120 return 0; 4121 } 4122 static int bnx2x_warpcore_get_sigdet(struct bnx2x_phy *phy, 4123 struct link_params *params) 4124 { 4125 u16 gp2_status_reg0, lane; 4126 struct bnx2x *bp = params->bp; 4127 4128 lane = bnx2x_get_warpcore_lane(phy, params); 4129 4130 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_0, 4131 &gp2_status_reg0); 4132 4133 return (gp2_status_reg0 >> (8+lane)) & 0x1; 4134 } 4135 4136 static void bnx2x_warpcore_config_runtime(struct bnx2x_phy *phy, 4137 struct link_params *params, 4138 struct link_vars *vars) 4139 { 4140 struct bnx2x *bp = params->bp; 4141 u32 serdes_net_if; 4142 u16 gp_status1 = 0, lnkup = 0, lnkup_kr = 0; 4143 u16 lane = bnx2x_get_warpcore_lane(phy, params); 4144 4145 vars->turn_to_run_wc_rt = vars->turn_to_run_wc_rt ? 0 : 1; 4146 4147 if (!vars->turn_to_run_wc_rt) 4148 return; 4149 4150 /* Return if there is no link partner */ 4151 if (!(bnx2x_warpcore_get_sigdet(phy, params))) { 4152 DP(NETIF_MSG_LINK, "bnx2x_warpcore_get_sigdet false\n"); 4153 return; 4154 } 4155 4156 if (vars->rx_tx_asic_rst) { 4157 serdes_net_if = (REG_RD(bp, params->shmem_base + 4158 offsetof(struct shmem_region, dev_info. 4159 port_hw_config[params->port].default_cfg)) & 4160 PORT_HW_CFG_NET_SERDES_IF_MASK); 4161 4162 switch (serdes_net_if) { 4163 case PORT_HW_CFG_NET_SERDES_IF_KR: 4164 /* Do we get link yet? */ 4165 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 0x81d1, 4166 &gp_status1); 4167 lnkup = (gp_status1 >> (8+lane)) & 0x1;/* 1G */ 4168 /*10G KR*/ 4169 lnkup_kr = (gp_status1 >> (12+lane)) & 0x1; 4170 4171 DP(NETIF_MSG_LINK, 4172 "gp_status1 0x%x\n", gp_status1); 4173 4174 if (lnkup_kr || lnkup) { 4175 vars->rx_tx_asic_rst = 0; 4176 DP(NETIF_MSG_LINK, 4177 "link up, rx_tx_asic_rst 0x%x\n", 4178 vars->rx_tx_asic_rst); 4179 } else { 4180 /* Reset the lane to see if link comes up.*/ 4181 bnx2x_warpcore_reset_lane(bp, phy, 1); 4182 bnx2x_warpcore_reset_lane(bp, phy, 0); 4183 4184 /* Restart Autoneg */ 4185 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, 4186 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200); 4187 4188 vars->rx_tx_asic_rst--; 4189 DP(NETIF_MSG_LINK, "0x%x retry left\n", 4190 vars->rx_tx_asic_rst); 4191 } 4192 break; 4193 4194 default: 4195 break; 4196 } 4197 4198 } /*params->rx_tx_asic_rst*/ 4199 4200 } 4201 static void bnx2x_warpcore_config_sfi(struct bnx2x_phy *phy, 4202 struct link_params *params) 4203 { 4204 u16 lane = bnx2x_get_warpcore_lane(phy, params); 4205 struct bnx2x *bp = params->bp; 4206 bnx2x_warpcore_clear_regs(phy, params, lane); 4207 if ((params->req_line_speed[LINK_CONFIG_IDX(INT_PHY)] == 4208 SPEED_10000) && 4209 (phy->media_type != ETH_PHY_SFP_1G_FIBER)) { 4210 DP(NETIF_MSG_LINK, "Setting 10G SFI\n"); 4211 bnx2x_warpcore_set_10G_XFI(phy, params, 0); 4212 } else { 4213 DP(NETIF_MSG_LINK, "Setting 1G Fiber\n"); 4214 bnx2x_warpcore_set_sgmii_speed(phy, params, 1, 0); 4215 } 4216 } 4217 4218 static void bnx2x_warpcore_config_init(struct bnx2x_phy *phy, 4219 struct link_params *params, 4220 struct link_vars *vars) 4221 { 4222 struct bnx2x *bp = params->bp; 4223 u32 serdes_net_if; 4224 u8 fiber_mode; 4225 u16 lane = bnx2x_get_warpcore_lane(phy, params); 4226 serdes_net_if = (REG_RD(bp, params->shmem_base + 4227 offsetof(struct shmem_region, dev_info. 4228 port_hw_config[params->port].default_cfg)) & 4229 PORT_HW_CFG_NET_SERDES_IF_MASK); 4230 DP(NETIF_MSG_LINK, "Begin Warpcore init, link_speed %d, " 4231 "serdes_net_if = 0x%x\n", 4232 vars->line_speed, serdes_net_if); 4233 bnx2x_set_aer_mmd(params, phy); 4234 bnx2x_warpcore_reset_lane(bp, phy, 1); 4235 vars->phy_flags |= PHY_XGXS_FLAG; 4236 if ((serdes_net_if == PORT_HW_CFG_NET_SERDES_IF_SGMII) || 4237 (phy->req_line_speed && 4238 ((phy->req_line_speed == SPEED_100) || 4239 (phy->req_line_speed == SPEED_10)))) { 4240 vars->phy_flags |= PHY_SGMII_FLAG; 4241 DP(NETIF_MSG_LINK, "Setting SGMII mode\n"); 4242 bnx2x_warpcore_clear_regs(phy, params, lane); 4243 bnx2x_warpcore_set_sgmii_speed(phy, params, 0, 1); 4244 } else { 4245 switch (serdes_net_if) { 4246 case PORT_HW_CFG_NET_SERDES_IF_KR: 4247 /* Enable KR Auto Neg */ 4248 if (params->loopback_mode != LOOPBACK_EXT) 4249 bnx2x_warpcore_enable_AN_KR(phy, params, vars); 4250 else { 4251 DP(NETIF_MSG_LINK, "Setting KR 10G-Force\n"); 4252 bnx2x_warpcore_set_10G_KR(phy, params, vars); 4253 } 4254 break; 4255 4256 case PORT_HW_CFG_NET_SERDES_IF_XFI: 4257 bnx2x_warpcore_clear_regs(phy, params, lane); 4258 if (vars->line_speed == SPEED_10000) { 4259 DP(NETIF_MSG_LINK, "Setting 10G XFI\n"); 4260 bnx2x_warpcore_set_10G_XFI(phy, params, 1); 4261 } else { 4262 if (SINGLE_MEDIA_DIRECT(params)) { 4263 DP(NETIF_MSG_LINK, "1G Fiber\n"); 4264 fiber_mode = 1; 4265 } else { 4266 DP(NETIF_MSG_LINK, "10/100/1G SGMII\n"); 4267 fiber_mode = 0; 4268 } 4269 bnx2x_warpcore_set_sgmii_speed(phy, 4270 params, 4271 fiber_mode, 4272 0); 4273 } 4274 4275 break; 4276 4277 case PORT_HW_CFG_NET_SERDES_IF_SFI: 4278 /* Issue Module detection */ 4279 if (bnx2x_is_sfp_module_plugged(phy, params)) 4280 bnx2x_sfp_module_detection(phy, params); 4281 4282 bnx2x_warpcore_config_sfi(phy, params); 4283 break; 4284 4285 case PORT_HW_CFG_NET_SERDES_IF_DXGXS: 4286 if (vars->line_speed != SPEED_20000) { 4287 DP(NETIF_MSG_LINK, "Speed not supported yet\n"); 4288 return; 4289 } 4290 DP(NETIF_MSG_LINK, "Setting 20G DXGXS\n"); 4291 bnx2x_warpcore_set_20G_DXGXS(bp, phy, lane); 4292 /* Issue Module detection */ 4293 4294 bnx2x_sfp_module_detection(phy, params); 4295 break; 4296 4297 case PORT_HW_CFG_NET_SERDES_IF_KR2: 4298 if (vars->line_speed != SPEED_20000) { 4299 DP(NETIF_MSG_LINK, "Speed not supported yet\n"); 4300 return; 4301 } 4302 DP(NETIF_MSG_LINK, "Setting 20G KR2\n"); 4303 bnx2x_warpcore_set_20G_KR2(bp, phy); 4304 break; 4305 4306 default: 4307 DP(NETIF_MSG_LINK, 4308 "Unsupported Serdes Net Interface 0x%x\n", 4309 serdes_net_if); 4310 return; 4311 } 4312 } 4313 4314 /* Take lane out of reset after configuration is finished */ 4315 bnx2x_warpcore_reset_lane(bp, phy, 0); 4316 DP(NETIF_MSG_LINK, "Exit config init\n"); 4317 } 4318 4319 static void bnx2x_sfp_e3_set_transmitter(struct link_params *params, 4320 struct bnx2x_phy *phy, 4321 u8 tx_en) 4322 { 4323 struct bnx2x *bp = params->bp; 4324 u32 cfg_pin; 4325 u8 port = params->port; 4326 4327 cfg_pin = REG_RD(bp, params->shmem_base + 4328 offsetof(struct shmem_region, 4329 dev_info.port_hw_config[port].e3_sfp_ctrl)) & 4330 PORT_HW_CFG_TX_LASER_MASK; 4331 /* Set the !tx_en since this pin is DISABLE_TX_LASER */ 4332 DP(NETIF_MSG_LINK, "Setting WC TX to %d\n", tx_en); 4333 /* For 20G, the expected pin to be used is 3 pins after the current */ 4334 4335 bnx2x_set_cfg_pin(bp, cfg_pin, tx_en ^ 1); 4336 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G) 4337 bnx2x_set_cfg_pin(bp, cfg_pin + 3, tx_en ^ 1); 4338 } 4339 4340 static void bnx2x_warpcore_link_reset(struct bnx2x_phy *phy, 4341 struct link_params *params) 4342 { 4343 struct bnx2x *bp = params->bp; 4344 u16 val16, lane; 4345 bnx2x_sfp_e3_set_transmitter(params, phy, 0); 4346 bnx2x_set_mdio_clk(bp, params->chip_id, params->port); 4347 bnx2x_set_aer_mmd(params, phy); 4348 /* Global register */ 4349 bnx2x_warpcore_reset_lane(bp, phy, 1); 4350 4351 /* Clear loopback settings (if any) */ 4352 /* 10G & 20G */ 4353 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 4354 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16); 4355 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4356 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16 & 4357 0xBFFF); 4358 4359 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 4360 MDIO_WC_REG_IEEE0BLK_MIICNTL, &val16); 4361 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4362 MDIO_WC_REG_IEEE0BLK_MIICNTL, val16 & 0xfffe); 4363 4364 /* Update those 1-copy registers */ 4365 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, 4366 MDIO_AER_BLOCK_AER_REG, 0); 4367 /* Enable 1G MDIO (1-copy) */ 4368 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 4369 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, 4370 &val16); 4371 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4372 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, 4373 val16 & ~0x10); 4374 4375 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 4376 MDIO_WC_REG_XGXSBLK1_LANECTRL2, &val16); 4377 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4378 MDIO_WC_REG_XGXSBLK1_LANECTRL2, 4379 val16 & 0xff00); 4380 4381 lane = bnx2x_get_warpcore_lane(phy, params); 4382 /* Disable CL36 PCS Tx */ 4383 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 4384 MDIO_WC_REG_XGXSBLK1_LANECTRL0, &val16); 4385 val16 |= (0x11 << lane); 4386 if (phy->flags & FLAGS_WC_DUAL_MODE) 4387 val16 |= (0x22 << lane); 4388 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4389 MDIO_WC_REG_XGXSBLK1_LANECTRL0, val16); 4390 4391 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 4392 MDIO_WC_REG_XGXSBLK1_LANECTRL1, &val16); 4393 val16 &= ~(0x0303 << (lane << 1)); 4394 val16 |= (0x0101 << (lane << 1)); 4395 if (phy->flags & FLAGS_WC_DUAL_MODE) { 4396 val16 &= ~(0x0c0c << (lane << 1)); 4397 val16 |= (0x0404 << (lane << 1)); 4398 } 4399 4400 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4401 MDIO_WC_REG_XGXSBLK1_LANECTRL1, val16); 4402 /* Restore AER */ 4403 bnx2x_set_aer_mmd(params, phy); 4404 4405 } 4406 4407 static void bnx2x_set_warpcore_loopback(struct bnx2x_phy *phy, 4408 struct link_params *params) 4409 { 4410 struct bnx2x *bp = params->bp; 4411 u16 val16; 4412 u32 lane; 4413 DP(NETIF_MSG_LINK, "Setting Warpcore loopback type %x, speed %d\n", 4414 params->loopback_mode, phy->req_line_speed); 4415 4416 if (phy->req_line_speed < SPEED_10000) { 4417 /* 10/100/1000 */ 4418 4419 /* Update those 1-copy registers */ 4420 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, 4421 MDIO_AER_BLOCK_AER_REG, 0); 4422 /* Enable 1G MDIO (1-copy) */ 4423 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 4424 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, 4425 0x10); 4426 /* Set 1G loopback based on lane (1-copy) */ 4427 lane = bnx2x_get_warpcore_lane(phy, params); 4428 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 4429 MDIO_WC_REG_XGXSBLK1_LANECTRL2, &val16); 4430 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4431 MDIO_WC_REG_XGXSBLK1_LANECTRL2, 4432 val16 | (1<<lane)); 4433 4434 /* Switch back to 4-copy registers */ 4435 bnx2x_set_aer_mmd(params, phy); 4436 } else { 4437 /* 10G & 20G */ 4438 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 4439 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 4440 0x4000); 4441 4442 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 4443 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1); 4444 } 4445 } 4446 4447 4448 4449 static void bnx2x_sync_link(struct link_params *params, 4450 struct link_vars *vars) 4451 { 4452 struct bnx2x *bp = params->bp; 4453 u8 link_10g_plus; 4454 if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG) 4455 vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG; 4456 vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP); 4457 if (vars->link_up) { 4458 DP(NETIF_MSG_LINK, "phy link up\n"); 4459 4460 vars->phy_link_up = 1; 4461 vars->duplex = DUPLEX_FULL; 4462 switch (vars->link_status & 4463 LINK_STATUS_SPEED_AND_DUPLEX_MASK) { 4464 case LINK_10THD: 4465 vars->duplex = DUPLEX_HALF; 4466 /* Fall thru */ 4467 case LINK_10TFD: 4468 vars->line_speed = SPEED_10; 4469 break; 4470 4471 case LINK_100TXHD: 4472 vars->duplex = DUPLEX_HALF; 4473 /* Fall thru */ 4474 case LINK_100T4: 4475 case LINK_100TXFD: 4476 vars->line_speed = SPEED_100; 4477 break; 4478 4479 case LINK_1000THD: 4480 vars->duplex = DUPLEX_HALF; 4481 /* Fall thru */ 4482 case LINK_1000TFD: 4483 vars->line_speed = SPEED_1000; 4484 break; 4485 4486 case LINK_2500THD: 4487 vars->duplex = DUPLEX_HALF; 4488 /* Fall thru */ 4489 case LINK_2500TFD: 4490 vars->line_speed = SPEED_2500; 4491 break; 4492 4493 case LINK_10GTFD: 4494 vars->line_speed = SPEED_10000; 4495 break; 4496 case LINK_20GTFD: 4497 vars->line_speed = SPEED_20000; 4498 break; 4499 default: 4500 break; 4501 } 4502 vars->flow_ctrl = 0; 4503 if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED) 4504 vars->flow_ctrl |= BNX2X_FLOW_CTRL_TX; 4505 4506 if (vars->link_status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED) 4507 vars->flow_ctrl |= BNX2X_FLOW_CTRL_RX; 4508 4509 if (!vars->flow_ctrl) 4510 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; 4511 4512 if (vars->line_speed && 4513 ((vars->line_speed == SPEED_10) || 4514 (vars->line_speed == SPEED_100))) { 4515 vars->phy_flags |= PHY_SGMII_FLAG; 4516 } else { 4517 vars->phy_flags &= ~PHY_SGMII_FLAG; 4518 } 4519 if (vars->line_speed && 4520 USES_WARPCORE(bp) && 4521 (vars->line_speed == SPEED_1000)) 4522 vars->phy_flags |= PHY_SGMII_FLAG; 4523 /* Anything 10 and over uses the bmac */ 4524 link_10g_plus = (vars->line_speed >= SPEED_10000); 4525 4526 if (link_10g_plus) { 4527 if (USES_WARPCORE(bp)) 4528 vars->mac_type = MAC_TYPE_XMAC; 4529 else 4530 vars->mac_type = MAC_TYPE_BMAC; 4531 } else { 4532 if (USES_WARPCORE(bp)) 4533 vars->mac_type = MAC_TYPE_UMAC; 4534 else 4535 vars->mac_type = MAC_TYPE_EMAC; 4536 } 4537 } else { /* Link down */ 4538 DP(NETIF_MSG_LINK, "phy link down\n"); 4539 4540 vars->phy_link_up = 0; 4541 4542 vars->line_speed = 0; 4543 vars->duplex = DUPLEX_FULL; 4544 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; 4545 4546 /* Indicate no mac active */ 4547 vars->mac_type = MAC_TYPE_NONE; 4548 if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG) 4549 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG; 4550 if (vars->link_status & LINK_STATUS_SFP_TX_FAULT) 4551 vars->phy_flags |= PHY_SFP_TX_FAULT_FLAG; 4552 } 4553 } 4554 4555 void bnx2x_link_status_update(struct link_params *params, 4556 struct link_vars *vars) 4557 { 4558 struct bnx2x *bp = params->bp; 4559 u8 port = params->port; 4560 u32 sync_offset, media_types; 4561 /* Update PHY configuration */ 4562 set_phy_vars(params, vars); 4563 4564 vars->link_status = REG_RD(bp, params->shmem_base + 4565 offsetof(struct shmem_region, 4566 port_mb[port].link_status)); 4567 if (bnx2x_eee_has_cap(params)) 4568 vars->eee_status = REG_RD(bp, params->shmem2_base + 4569 offsetof(struct shmem2_region, 4570 eee_status[params->port])); 4571 4572 vars->phy_flags = PHY_XGXS_FLAG; 4573 bnx2x_sync_link(params, vars); 4574 /* Sync media type */ 4575 sync_offset = params->shmem_base + 4576 offsetof(struct shmem_region, 4577 dev_info.port_hw_config[port].media_type); 4578 media_types = REG_RD(bp, sync_offset); 4579 4580 params->phy[INT_PHY].media_type = 4581 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) >> 4582 PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT; 4583 params->phy[EXT_PHY1].media_type = 4584 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK) >> 4585 PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT; 4586 params->phy[EXT_PHY2].media_type = 4587 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK) >> 4588 PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT; 4589 DP(NETIF_MSG_LINK, "media_types = 0x%x\n", media_types); 4590 4591 /* Sync AEU offset */ 4592 sync_offset = params->shmem_base + 4593 offsetof(struct shmem_region, 4594 dev_info.port_hw_config[port].aeu_int_mask); 4595 4596 vars->aeu_int_mask = REG_RD(bp, sync_offset); 4597 4598 /* Sync PFC status */ 4599 if (vars->link_status & LINK_STATUS_PFC_ENABLED) 4600 params->feature_config_flags |= 4601 FEATURE_CONFIG_PFC_ENABLED; 4602 else 4603 params->feature_config_flags &= 4604 ~FEATURE_CONFIG_PFC_ENABLED; 4605 4606 DP(NETIF_MSG_LINK, "link_status 0x%x phy_link_up %x int_mask 0x%x\n", 4607 vars->link_status, vars->phy_link_up, vars->aeu_int_mask); 4608 DP(NETIF_MSG_LINK, "line_speed %x duplex %x flow_ctrl 0x%x\n", 4609 vars->line_speed, vars->duplex, vars->flow_ctrl); 4610 } 4611 4612 static void bnx2x_set_master_ln(struct link_params *params, 4613 struct bnx2x_phy *phy) 4614 { 4615 struct bnx2x *bp = params->bp; 4616 u16 new_master_ln, ser_lane; 4617 ser_lane = ((params->lane_config & 4618 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >> 4619 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT); 4620 4621 /* Set the master_ln for AN */ 4622 CL22_RD_OVER_CL45(bp, phy, 4623 MDIO_REG_BANK_XGXS_BLOCK2, 4624 MDIO_XGXS_BLOCK2_TEST_MODE_LANE, 4625 &new_master_ln); 4626 4627 CL22_WR_OVER_CL45(bp, phy, 4628 MDIO_REG_BANK_XGXS_BLOCK2 , 4629 MDIO_XGXS_BLOCK2_TEST_MODE_LANE, 4630 (new_master_ln | ser_lane)); 4631 } 4632 4633 static int bnx2x_reset_unicore(struct link_params *params, 4634 struct bnx2x_phy *phy, 4635 u8 set_serdes) 4636 { 4637 struct bnx2x *bp = params->bp; 4638 u16 mii_control; 4639 u16 i; 4640 CL22_RD_OVER_CL45(bp, phy, 4641 MDIO_REG_BANK_COMBO_IEEE0, 4642 MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control); 4643 4644 /* Reset the unicore */ 4645 CL22_WR_OVER_CL45(bp, phy, 4646 MDIO_REG_BANK_COMBO_IEEE0, 4647 MDIO_COMBO_IEEE0_MII_CONTROL, 4648 (mii_control | 4649 MDIO_COMBO_IEEO_MII_CONTROL_RESET)); 4650 if (set_serdes) 4651 bnx2x_set_serdes_access(bp, params->port); 4652 4653 /* Wait for the reset to self clear */ 4654 for (i = 0; i < MDIO_ACCESS_TIMEOUT; i++) { 4655 udelay(5); 4656 4657 /* The reset erased the previous bank value */ 4658 CL22_RD_OVER_CL45(bp, phy, 4659 MDIO_REG_BANK_COMBO_IEEE0, 4660 MDIO_COMBO_IEEE0_MII_CONTROL, 4661 &mii_control); 4662 4663 if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) { 4664 udelay(5); 4665 return 0; 4666 } 4667 } 4668 4669 netdev_err(bp->dev, "Warning: PHY was not initialized," 4670 " Port %d\n", 4671 params->port); 4672 DP(NETIF_MSG_LINK, "BUG! XGXS is still in reset!\n"); 4673 return -EINVAL; 4674 4675 } 4676 4677 static void bnx2x_set_swap_lanes(struct link_params *params, 4678 struct bnx2x_phy *phy) 4679 { 4680 struct bnx2x *bp = params->bp; 4681 /* Each two bits represents a lane number: 4682 * No swap is 0123 => 0x1b no need to enable the swap 4683 */ 4684 u16 rx_lane_swap, tx_lane_swap; 4685 4686 rx_lane_swap = ((params->lane_config & 4687 PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >> 4688 PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT); 4689 tx_lane_swap = ((params->lane_config & 4690 PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >> 4691 PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT); 4692 4693 if (rx_lane_swap != 0x1b) { 4694 CL22_WR_OVER_CL45(bp, phy, 4695 MDIO_REG_BANK_XGXS_BLOCK2, 4696 MDIO_XGXS_BLOCK2_RX_LN_SWAP, 4697 (rx_lane_swap | 4698 MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE | 4699 MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE)); 4700 } else { 4701 CL22_WR_OVER_CL45(bp, phy, 4702 MDIO_REG_BANK_XGXS_BLOCK2, 4703 MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0); 4704 } 4705 4706 if (tx_lane_swap != 0x1b) { 4707 CL22_WR_OVER_CL45(bp, phy, 4708 MDIO_REG_BANK_XGXS_BLOCK2, 4709 MDIO_XGXS_BLOCK2_TX_LN_SWAP, 4710 (tx_lane_swap | 4711 MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE)); 4712 } else { 4713 CL22_WR_OVER_CL45(bp, phy, 4714 MDIO_REG_BANK_XGXS_BLOCK2, 4715 MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0); 4716 } 4717 } 4718 4719 static void bnx2x_set_parallel_detection(struct bnx2x_phy *phy, 4720 struct link_params *params) 4721 { 4722 struct bnx2x *bp = params->bp; 4723 u16 control2; 4724 CL22_RD_OVER_CL45(bp, phy, 4725 MDIO_REG_BANK_SERDES_DIGITAL, 4726 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2, 4727 &control2); 4728 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) 4729 control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN; 4730 else 4731 control2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN; 4732 DP(NETIF_MSG_LINK, "phy->speed_cap_mask = 0x%x, control2 = 0x%x\n", 4733 phy->speed_cap_mask, control2); 4734 CL22_WR_OVER_CL45(bp, phy, 4735 MDIO_REG_BANK_SERDES_DIGITAL, 4736 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2, 4737 control2); 4738 4739 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) && 4740 (phy->speed_cap_mask & 4741 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) { 4742 DP(NETIF_MSG_LINK, "XGXS\n"); 4743 4744 CL22_WR_OVER_CL45(bp, phy, 4745 MDIO_REG_BANK_10G_PARALLEL_DETECT, 4746 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK, 4747 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT); 4748 4749 CL22_RD_OVER_CL45(bp, phy, 4750 MDIO_REG_BANK_10G_PARALLEL_DETECT, 4751 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL, 4752 &control2); 4753 4754 4755 control2 |= 4756 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN; 4757 4758 CL22_WR_OVER_CL45(bp, phy, 4759 MDIO_REG_BANK_10G_PARALLEL_DETECT, 4760 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL, 4761 control2); 4762 4763 /* Disable parallel detection of HiG */ 4764 CL22_WR_OVER_CL45(bp, phy, 4765 MDIO_REG_BANK_XGXS_BLOCK2, 4766 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G, 4767 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS | 4768 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS); 4769 } 4770 } 4771 4772 static void bnx2x_set_autoneg(struct bnx2x_phy *phy, 4773 struct link_params *params, 4774 struct link_vars *vars, 4775 u8 enable_cl73) 4776 { 4777 struct bnx2x *bp = params->bp; 4778 u16 reg_val; 4779 4780 /* CL37 Autoneg */ 4781 CL22_RD_OVER_CL45(bp, phy, 4782 MDIO_REG_BANK_COMBO_IEEE0, 4783 MDIO_COMBO_IEEE0_MII_CONTROL, ®_val); 4784 4785 /* CL37 Autoneg Enabled */ 4786 if (vars->line_speed == SPEED_AUTO_NEG) 4787 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN; 4788 else /* CL37 Autoneg Disabled */ 4789 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN | 4790 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN); 4791 4792 CL22_WR_OVER_CL45(bp, phy, 4793 MDIO_REG_BANK_COMBO_IEEE0, 4794 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val); 4795 4796 /* Enable/Disable Autodetection */ 4797 4798 CL22_RD_OVER_CL45(bp, phy, 4799 MDIO_REG_BANK_SERDES_DIGITAL, 4800 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, ®_val); 4801 reg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN | 4802 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT); 4803 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE; 4804 if (vars->line_speed == SPEED_AUTO_NEG) 4805 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET; 4806 else 4807 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET; 4808 4809 CL22_WR_OVER_CL45(bp, phy, 4810 MDIO_REG_BANK_SERDES_DIGITAL, 4811 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val); 4812 4813 /* Enable TetonII and BAM autoneg */ 4814 CL22_RD_OVER_CL45(bp, phy, 4815 MDIO_REG_BANK_BAM_NEXT_PAGE, 4816 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL, 4817 ®_val); 4818 if (vars->line_speed == SPEED_AUTO_NEG) { 4819 /* Enable BAM aneg Mode and TetonII aneg Mode */ 4820 reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE | 4821 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN); 4822 } else { 4823 /* TetonII and BAM Autoneg Disabled */ 4824 reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE | 4825 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN); 4826 } 4827 CL22_WR_OVER_CL45(bp, phy, 4828 MDIO_REG_BANK_BAM_NEXT_PAGE, 4829 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL, 4830 reg_val); 4831 4832 if (enable_cl73) { 4833 /* Enable Cl73 FSM status bits */ 4834 CL22_WR_OVER_CL45(bp, phy, 4835 MDIO_REG_BANK_CL73_USERB0, 4836 MDIO_CL73_USERB0_CL73_UCTRL, 4837 0xe); 4838 4839 /* Enable BAM Station Manager*/ 4840 CL22_WR_OVER_CL45(bp, phy, 4841 MDIO_REG_BANK_CL73_USERB0, 4842 MDIO_CL73_USERB0_CL73_BAM_CTRL1, 4843 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN | 4844 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN | 4845 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN); 4846 4847 /* Advertise CL73 link speeds */ 4848 CL22_RD_OVER_CL45(bp, phy, 4849 MDIO_REG_BANK_CL73_IEEEB1, 4850 MDIO_CL73_IEEEB1_AN_ADV2, 4851 ®_val); 4852 if (phy->speed_cap_mask & 4853 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) 4854 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4; 4855 if (phy->speed_cap_mask & 4856 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) 4857 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX; 4858 4859 CL22_WR_OVER_CL45(bp, phy, 4860 MDIO_REG_BANK_CL73_IEEEB1, 4861 MDIO_CL73_IEEEB1_AN_ADV2, 4862 reg_val); 4863 4864 /* CL73 Autoneg Enabled */ 4865 reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN; 4866 4867 } else /* CL73 Autoneg Disabled */ 4868 reg_val = 0; 4869 4870 CL22_WR_OVER_CL45(bp, phy, 4871 MDIO_REG_BANK_CL73_IEEEB0, 4872 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val); 4873 } 4874 4875 /* Program SerDes, forced speed */ 4876 static void bnx2x_program_serdes(struct bnx2x_phy *phy, 4877 struct link_params *params, 4878 struct link_vars *vars) 4879 { 4880 struct bnx2x *bp = params->bp; 4881 u16 reg_val; 4882 4883 /* Program duplex, disable autoneg and sgmii*/ 4884 CL22_RD_OVER_CL45(bp, phy, 4885 MDIO_REG_BANK_COMBO_IEEE0, 4886 MDIO_COMBO_IEEE0_MII_CONTROL, ®_val); 4887 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX | 4888 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN | 4889 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK); 4890 if (phy->req_duplex == DUPLEX_FULL) 4891 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX; 4892 CL22_WR_OVER_CL45(bp, phy, 4893 MDIO_REG_BANK_COMBO_IEEE0, 4894 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val); 4895 4896 /* Program speed 4897 * - needed only if the speed is greater than 1G (2.5G or 10G) 4898 */ 4899 CL22_RD_OVER_CL45(bp, phy, 4900 MDIO_REG_BANK_SERDES_DIGITAL, 4901 MDIO_SERDES_DIGITAL_MISC1, ®_val); 4902 /* Clearing the speed value before setting the right speed */ 4903 DP(NETIF_MSG_LINK, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val); 4904 4905 reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK | 4906 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL); 4907 4908 if (!((vars->line_speed == SPEED_1000) || 4909 (vars->line_speed == SPEED_100) || 4910 (vars->line_speed == SPEED_10))) { 4911 4912 reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M | 4913 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL); 4914 if (vars->line_speed == SPEED_10000) 4915 reg_val |= 4916 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4; 4917 } 4918 4919 CL22_WR_OVER_CL45(bp, phy, 4920 MDIO_REG_BANK_SERDES_DIGITAL, 4921 MDIO_SERDES_DIGITAL_MISC1, reg_val); 4922 4923 } 4924 4925 static void bnx2x_set_brcm_cl37_advertisement(struct bnx2x_phy *phy, 4926 struct link_params *params) 4927 { 4928 struct bnx2x *bp = params->bp; 4929 u16 val = 0; 4930 4931 /* Set extended capabilities */ 4932 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) 4933 val |= MDIO_OVER_1G_UP1_2_5G; 4934 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) 4935 val |= MDIO_OVER_1G_UP1_10G; 4936 CL22_WR_OVER_CL45(bp, phy, 4937 MDIO_REG_BANK_OVER_1G, 4938 MDIO_OVER_1G_UP1, val); 4939 4940 CL22_WR_OVER_CL45(bp, phy, 4941 MDIO_REG_BANK_OVER_1G, 4942 MDIO_OVER_1G_UP3, 0x400); 4943 } 4944 4945 static void bnx2x_set_ieee_aneg_advertisement(struct bnx2x_phy *phy, 4946 struct link_params *params, 4947 u16 ieee_fc) 4948 { 4949 struct bnx2x *bp = params->bp; 4950 u16 val; 4951 /* For AN, we are always publishing full duplex */ 4952 4953 CL22_WR_OVER_CL45(bp, phy, 4954 MDIO_REG_BANK_COMBO_IEEE0, 4955 MDIO_COMBO_IEEE0_AUTO_NEG_ADV, ieee_fc); 4956 CL22_RD_OVER_CL45(bp, phy, 4957 MDIO_REG_BANK_CL73_IEEEB1, 4958 MDIO_CL73_IEEEB1_AN_ADV1, &val); 4959 val &= ~MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH; 4960 val |= ((ieee_fc<<3) & MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK); 4961 CL22_WR_OVER_CL45(bp, phy, 4962 MDIO_REG_BANK_CL73_IEEEB1, 4963 MDIO_CL73_IEEEB1_AN_ADV1, val); 4964 } 4965 4966 static void bnx2x_restart_autoneg(struct bnx2x_phy *phy, 4967 struct link_params *params, 4968 u8 enable_cl73) 4969 { 4970 struct bnx2x *bp = params->bp; 4971 u16 mii_control; 4972 4973 DP(NETIF_MSG_LINK, "bnx2x_restart_autoneg\n"); 4974 /* Enable and restart BAM/CL37 aneg */ 4975 4976 if (enable_cl73) { 4977 CL22_RD_OVER_CL45(bp, phy, 4978 MDIO_REG_BANK_CL73_IEEEB0, 4979 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, 4980 &mii_control); 4981 4982 CL22_WR_OVER_CL45(bp, phy, 4983 MDIO_REG_BANK_CL73_IEEEB0, 4984 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, 4985 (mii_control | 4986 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN | 4987 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN)); 4988 } else { 4989 4990 CL22_RD_OVER_CL45(bp, phy, 4991 MDIO_REG_BANK_COMBO_IEEE0, 4992 MDIO_COMBO_IEEE0_MII_CONTROL, 4993 &mii_control); 4994 DP(NETIF_MSG_LINK, 4995 "bnx2x_restart_autoneg mii_control before = 0x%x\n", 4996 mii_control); 4997 CL22_WR_OVER_CL45(bp, phy, 4998 MDIO_REG_BANK_COMBO_IEEE0, 4999 MDIO_COMBO_IEEE0_MII_CONTROL, 5000 (mii_control | 5001 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN | 5002 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN)); 5003 } 5004 } 5005 5006 static void bnx2x_initialize_sgmii_process(struct bnx2x_phy *phy, 5007 struct link_params *params, 5008 struct link_vars *vars) 5009 { 5010 struct bnx2x *bp = params->bp; 5011 u16 control1; 5012 5013 /* In SGMII mode, the unicore is always slave */ 5014 5015 CL22_RD_OVER_CL45(bp, phy, 5016 MDIO_REG_BANK_SERDES_DIGITAL, 5017 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, 5018 &control1); 5019 control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT; 5020 /* Set sgmii mode (and not fiber) */ 5021 control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE | 5022 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET | 5023 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE); 5024 CL22_WR_OVER_CL45(bp, phy, 5025 MDIO_REG_BANK_SERDES_DIGITAL, 5026 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, 5027 control1); 5028 5029 /* If forced speed */ 5030 if (!(vars->line_speed == SPEED_AUTO_NEG)) { 5031 /* Set speed, disable autoneg */ 5032 u16 mii_control; 5033 5034 CL22_RD_OVER_CL45(bp, phy, 5035 MDIO_REG_BANK_COMBO_IEEE0, 5036 MDIO_COMBO_IEEE0_MII_CONTROL, 5037 &mii_control); 5038 mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN | 5039 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK| 5040 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX); 5041 5042 switch (vars->line_speed) { 5043 case SPEED_100: 5044 mii_control |= 5045 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100; 5046 break; 5047 case SPEED_1000: 5048 mii_control |= 5049 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000; 5050 break; 5051 case SPEED_10: 5052 /* There is nothing to set for 10M */ 5053 break; 5054 default: 5055 /* Invalid speed for SGMII */ 5056 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n", 5057 vars->line_speed); 5058 break; 5059 } 5060 5061 /* Setting the full duplex */ 5062 if (phy->req_duplex == DUPLEX_FULL) 5063 mii_control |= 5064 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX; 5065 CL22_WR_OVER_CL45(bp, phy, 5066 MDIO_REG_BANK_COMBO_IEEE0, 5067 MDIO_COMBO_IEEE0_MII_CONTROL, 5068 mii_control); 5069 5070 } else { /* AN mode */ 5071 /* Enable and restart AN */ 5072 bnx2x_restart_autoneg(phy, params, 0); 5073 } 5074 } 5075 5076 /* Link management 5077 */ 5078 static int bnx2x_direct_parallel_detect_used(struct bnx2x_phy *phy, 5079 struct link_params *params) 5080 { 5081 struct bnx2x *bp = params->bp; 5082 u16 pd_10g, status2_1000x; 5083 if (phy->req_line_speed != SPEED_AUTO_NEG) 5084 return 0; 5085 CL22_RD_OVER_CL45(bp, phy, 5086 MDIO_REG_BANK_SERDES_DIGITAL, 5087 MDIO_SERDES_DIGITAL_A_1000X_STATUS2, 5088 &status2_1000x); 5089 CL22_RD_OVER_CL45(bp, phy, 5090 MDIO_REG_BANK_SERDES_DIGITAL, 5091 MDIO_SERDES_DIGITAL_A_1000X_STATUS2, 5092 &status2_1000x); 5093 if (status2_1000x & MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED) { 5094 DP(NETIF_MSG_LINK, "1G parallel detect link on port %d\n", 5095 params->port); 5096 return 1; 5097 } 5098 5099 CL22_RD_OVER_CL45(bp, phy, 5100 MDIO_REG_BANK_10G_PARALLEL_DETECT, 5101 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS, 5102 &pd_10g); 5103 5104 if (pd_10g & MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK) { 5105 DP(NETIF_MSG_LINK, "10G parallel detect link on port %d\n", 5106 params->port); 5107 return 1; 5108 } 5109 return 0; 5110 } 5111 5112 static void bnx2x_update_adv_fc(struct bnx2x_phy *phy, 5113 struct link_params *params, 5114 struct link_vars *vars, 5115 u32 gp_status) 5116 { 5117 u16 ld_pause; /* local driver */ 5118 u16 lp_pause; /* link partner */ 5119 u16 pause_result; 5120 struct bnx2x *bp = params->bp; 5121 if ((gp_status & 5122 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | 5123 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) == 5124 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | 5125 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) { 5126 5127 CL22_RD_OVER_CL45(bp, phy, 5128 MDIO_REG_BANK_CL73_IEEEB1, 5129 MDIO_CL73_IEEEB1_AN_ADV1, 5130 &ld_pause); 5131 CL22_RD_OVER_CL45(bp, phy, 5132 MDIO_REG_BANK_CL73_IEEEB1, 5133 MDIO_CL73_IEEEB1_AN_LP_ADV1, 5134 &lp_pause); 5135 pause_result = (ld_pause & 5136 MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK) >> 8; 5137 pause_result |= (lp_pause & 5138 MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK) >> 10; 5139 DP(NETIF_MSG_LINK, "pause_result CL73 0x%x\n", pause_result); 5140 } else { 5141 CL22_RD_OVER_CL45(bp, phy, 5142 MDIO_REG_BANK_COMBO_IEEE0, 5143 MDIO_COMBO_IEEE0_AUTO_NEG_ADV, 5144 &ld_pause); 5145 CL22_RD_OVER_CL45(bp, phy, 5146 MDIO_REG_BANK_COMBO_IEEE0, 5147 MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1, 5148 &lp_pause); 5149 pause_result = (ld_pause & 5150 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>5; 5151 pause_result |= (lp_pause & 5152 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7; 5153 DP(NETIF_MSG_LINK, "pause_result CL37 0x%x\n", pause_result); 5154 } 5155 bnx2x_pause_resolve(vars, pause_result); 5156 5157 } 5158 5159 static void bnx2x_flow_ctrl_resolve(struct bnx2x_phy *phy, 5160 struct link_params *params, 5161 struct link_vars *vars, 5162 u32 gp_status) 5163 { 5164 struct bnx2x *bp = params->bp; 5165 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; 5166 5167 /* Resolve from gp_status in case of AN complete and not sgmii */ 5168 if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO) { 5169 /* Update the advertised flow-controled of LD/LP in AN */ 5170 if (phy->req_line_speed == SPEED_AUTO_NEG) 5171 bnx2x_update_adv_fc(phy, params, vars, gp_status); 5172 /* But set the flow-control result as the requested one */ 5173 vars->flow_ctrl = phy->req_flow_ctrl; 5174 } else if (phy->req_line_speed != SPEED_AUTO_NEG) 5175 vars->flow_ctrl = params->req_fc_auto_adv; 5176 else if ((gp_status & MDIO_AN_CL73_OR_37_COMPLETE) && 5177 (!(vars->phy_flags & PHY_SGMII_FLAG))) { 5178 if (bnx2x_direct_parallel_detect_used(phy, params)) { 5179 vars->flow_ctrl = params->req_fc_auto_adv; 5180 return; 5181 } 5182 bnx2x_update_adv_fc(phy, params, vars, gp_status); 5183 } 5184 DP(NETIF_MSG_LINK, "flow_ctrl 0x%x\n", vars->flow_ctrl); 5185 } 5186 5187 static void bnx2x_check_fallback_to_cl37(struct bnx2x_phy *phy, 5188 struct link_params *params) 5189 { 5190 struct bnx2x *bp = params->bp; 5191 u16 rx_status, ustat_val, cl37_fsm_received; 5192 DP(NETIF_MSG_LINK, "bnx2x_check_fallback_to_cl37\n"); 5193 /* Step 1: Make sure signal is detected */ 5194 CL22_RD_OVER_CL45(bp, phy, 5195 MDIO_REG_BANK_RX0, 5196 MDIO_RX0_RX_STATUS, 5197 &rx_status); 5198 if ((rx_status & MDIO_RX0_RX_STATUS_SIGDET) != 5199 (MDIO_RX0_RX_STATUS_SIGDET)) { 5200 DP(NETIF_MSG_LINK, "Signal is not detected. Restoring CL73." 5201 "rx_status(0x80b0) = 0x%x\n", rx_status); 5202 CL22_WR_OVER_CL45(bp, phy, 5203 MDIO_REG_BANK_CL73_IEEEB0, 5204 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, 5205 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN); 5206 return; 5207 } 5208 /* Step 2: Check CL73 state machine */ 5209 CL22_RD_OVER_CL45(bp, phy, 5210 MDIO_REG_BANK_CL73_USERB0, 5211 MDIO_CL73_USERB0_CL73_USTAT1, 5212 &ustat_val); 5213 if ((ustat_val & 5214 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK | 5215 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) != 5216 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK | 5217 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) { 5218 DP(NETIF_MSG_LINK, "CL73 state-machine is not stable. " 5219 "ustat_val(0x8371) = 0x%x\n", ustat_val); 5220 return; 5221 } 5222 /* Step 3: Check CL37 Message Pages received to indicate LP 5223 * supports only CL37 5224 */ 5225 CL22_RD_OVER_CL45(bp, phy, 5226 MDIO_REG_BANK_REMOTE_PHY, 5227 MDIO_REMOTE_PHY_MISC_RX_STATUS, 5228 &cl37_fsm_received); 5229 if ((cl37_fsm_received & 5230 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG | 5231 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) != 5232 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG | 5233 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) { 5234 DP(NETIF_MSG_LINK, "No CL37 FSM were received. " 5235 "misc_rx_status(0x8330) = 0x%x\n", 5236 cl37_fsm_received); 5237 return; 5238 } 5239 /* The combined cl37/cl73 fsm state information indicating that 5240 * we are connected to a device which does not support cl73, but 5241 * does support cl37 BAM. In this case we disable cl73 and 5242 * restart cl37 auto-neg 5243 */ 5244 5245 /* Disable CL73 */ 5246 CL22_WR_OVER_CL45(bp, phy, 5247 MDIO_REG_BANK_CL73_IEEEB0, 5248 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, 5249 0); 5250 /* Restart CL37 autoneg */ 5251 bnx2x_restart_autoneg(phy, params, 0); 5252 DP(NETIF_MSG_LINK, "Disabling CL73, and restarting CL37 autoneg\n"); 5253 } 5254 5255 static void bnx2x_xgxs_an_resolve(struct bnx2x_phy *phy, 5256 struct link_params *params, 5257 struct link_vars *vars, 5258 u32 gp_status) 5259 { 5260 if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE) 5261 vars->link_status |= 5262 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; 5263 5264 if (bnx2x_direct_parallel_detect_used(phy, params)) 5265 vars->link_status |= 5266 LINK_STATUS_PARALLEL_DETECTION_USED; 5267 } 5268 static int bnx2x_get_link_speed_duplex(struct bnx2x_phy *phy, 5269 struct link_params *params, 5270 struct link_vars *vars, 5271 u16 is_link_up, 5272 u16 speed_mask, 5273 u16 is_duplex) 5274 { 5275 struct bnx2x *bp = params->bp; 5276 if (phy->req_line_speed == SPEED_AUTO_NEG) 5277 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED; 5278 if (is_link_up) { 5279 DP(NETIF_MSG_LINK, "phy link up\n"); 5280 5281 vars->phy_link_up = 1; 5282 vars->link_status |= LINK_STATUS_LINK_UP; 5283 5284 switch (speed_mask) { 5285 case GP_STATUS_10M: 5286 vars->line_speed = SPEED_10; 5287 if (is_duplex == DUPLEX_FULL) 5288 vars->link_status |= LINK_10TFD; 5289 else 5290 vars->link_status |= LINK_10THD; 5291 break; 5292 5293 case GP_STATUS_100M: 5294 vars->line_speed = SPEED_100; 5295 if (is_duplex == DUPLEX_FULL) 5296 vars->link_status |= LINK_100TXFD; 5297 else 5298 vars->link_status |= LINK_100TXHD; 5299 break; 5300 5301 case GP_STATUS_1G: 5302 case GP_STATUS_1G_KX: 5303 vars->line_speed = SPEED_1000; 5304 if (is_duplex == DUPLEX_FULL) 5305 vars->link_status |= LINK_1000TFD; 5306 else 5307 vars->link_status |= LINK_1000THD; 5308 break; 5309 5310 case GP_STATUS_2_5G: 5311 vars->line_speed = SPEED_2500; 5312 if (is_duplex == DUPLEX_FULL) 5313 vars->link_status |= LINK_2500TFD; 5314 else 5315 vars->link_status |= LINK_2500THD; 5316 break; 5317 5318 case GP_STATUS_5G: 5319 case GP_STATUS_6G: 5320 DP(NETIF_MSG_LINK, 5321 "link speed unsupported gp_status 0x%x\n", 5322 speed_mask); 5323 return -EINVAL; 5324 5325 case GP_STATUS_10G_KX4: 5326 case GP_STATUS_10G_HIG: 5327 case GP_STATUS_10G_CX4: 5328 case GP_STATUS_10G_KR: 5329 case GP_STATUS_10G_SFI: 5330 case GP_STATUS_10G_XFI: 5331 vars->line_speed = SPEED_10000; 5332 vars->link_status |= LINK_10GTFD; 5333 break; 5334 case GP_STATUS_20G_DXGXS: 5335 vars->line_speed = SPEED_20000; 5336 vars->link_status |= LINK_20GTFD; 5337 break; 5338 default: 5339 DP(NETIF_MSG_LINK, 5340 "link speed unsupported gp_status 0x%x\n", 5341 speed_mask); 5342 return -EINVAL; 5343 } 5344 } else { /* link_down */ 5345 DP(NETIF_MSG_LINK, "phy link down\n"); 5346 5347 vars->phy_link_up = 0; 5348 5349 vars->duplex = DUPLEX_FULL; 5350 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; 5351 vars->mac_type = MAC_TYPE_NONE; 5352 } 5353 DP(NETIF_MSG_LINK, " phy_link_up %x line_speed %d\n", 5354 vars->phy_link_up, vars->line_speed); 5355 return 0; 5356 } 5357 5358 static int bnx2x_link_settings_status(struct bnx2x_phy *phy, 5359 struct link_params *params, 5360 struct link_vars *vars) 5361 { 5362 struct bnx2x *bp = params->bp; 5363 5364 u16 gp_status, duplex = DUPLEX_HALF, link_up = 0, speed_mask; 5365 int rc = 0; 5366 5367 /* Read gp_status */ 5368 CL22_RD_OVER_CL45(bp, phy, 5369 MDIO_REG_BANK_GP_STATUS, 5370 MDIO_GP_STATUS_TOP_AN_STATUS1, 5371 &gp_status); 5372 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS) 5373 duplex = DUPLEX_FULL; 5374 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) 5375 link_up = 1; 5376 speed_mask = gp_status & GP_STATUS_SPEED_MASK; 5377 DP(NETIF_MSG_LINK, "gp_status 0x%x, is_link_up %d, speed_mask 0x%x\n", 5378 gp_status, link_up, speed_mask); 5379 rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, speed_mask, 5380 duplex); 5381 if (rc == -EINVAL) 5382 return rc; 5383 5384 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) { 5385 if (SINGLE_MEDIA_DIRECT(params)) { 5386 vars->duplex = duplex; 5387 bnx2x_flow_ctrl_resolve(phy, params, vars, gp_status); 5388 if (phy->req_line_speed == SPEED_AUTO_NEG) 5389 bnx2x_xgxs_an_resolve(phy, params, vars, 5390 gp_status); 5391 } 5392 } else { /* Link_down */ 5393 if ((phy->req_line_speed == SPEED_AUTO_NEG) && 5394 SINGLE_MEDIA_DIRECT(params)) { 5395 /* Check signal is detected */ 5396 bnx2x_check_fallback_to_cl37(phy, params); 5397 } 5398 } 5399 5400 /* Read LP advertised speeds*/ 5401 if (SINGLE_MEDIA_DIRECT(params) && 5402 (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)) { 5403 u16 val; 5404 5405 CL22_RD_OVER_CL45(bp, phy, MDIO_REG_BANK_CL73_IEEEB1, 5406 MDIO_CL73_IEEEB1_AN_LP_ADV2, &val); 5407 5408 if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX) 5409 vars->link_status |= 5410 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; 5411 if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 | 5412 MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR)) 5413 vars->link_status |= 5414 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; 5415 5416 CL22_RD_OVER_CL45(bp, phy, MDIO_REG_BANK_OVER_1G, 5417 MDIO_OVER_1G_LP_UP1, &val); 5418 5419 if (val & MDIO_OVER_1G_UP1_2_5G) 5420 vars->link_status |= 5421 LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE; 5422 if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH)) 5423 vars->link_status |= 5424 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; 5425 } 5426 5427 DP(NETIF_MSG_LINK, "duplex %x flow_ctrl 0x%x link_status 0x%x\n", 5428 vars->duplex, vars->flow_ctrl, vars->link_status); 5429 return rc; 5430 } 5431 5432 static int bnx2x_warpcore_read_status(struct bnx2x_phy *phy, 5433 struct link_params *params, 5434 struct link_vars *vars) 5435 { 5436 struct bnx2x *bp = params->bp; 5437 u8 lane; 5438 u16 gp_status1, gp_speed, link_up, duplex = DUPLEX_FULL; 5439 int rc = 0; 5440 lane = bnx2x_get_warpcore_lane(phy, params); 5441 /* Read gp_status */ 5442 if (phy->req_line_speed > SPEED_10000) { 5443 u16 temp_link_up; 5444 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 5445 1, &temp_link_up); 5446 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 5447 1, &link_up); 5448 DP(NETIF_MSG_LINK, "PCS RX link status = 0x%x-->0x%x\n", 5449 temp_link_up, link_up); 5450 link_up &= (1<<2); 5451 if (link_up) 5452 bnx2x_ext_phy_resolve_fc(phy, params, vars); 5453 } else { 5454 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 5455 MDIO_WC_REG_GP2_STATUS_GP_2_1, &gp_status1); 5456 DP(NETIF_MSG_LINK, "0x81d1 = 0x%x\n", gp_status1); 5457 /* Check for either KR or generic link up. */ 5458 gp_status1 = ((gp_status1 >> 8) & 0xf) | 5459 ((gp_status1 >> 12) & 0xf); 5460 link_up = gp_status1 & (1 << lane); 5461 if (link_up && SINGLE_MEDIA_DIRECT(params)) { 5462 u16 pd, gp_status4; 5463 if (phy->req_line_speed == SPEED_AUTO_NEG) { 5464 /* Check Autoneg complete */ 5465 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 5466 MDIO_WC_REG_GP2_STATUS_GP_2_4, 5467 &gp_status4); 5468 if (gp_status4 & ((1<<12)<<lane)) 5469 vars->link_status |= 5470 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; 5471 5472 /* Check parallel detect used */ 5473 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 5474 MDIO_WC_REG_PAR_DET_10G_STATUS, 5475 &pd); 5476 if (pd & (1<<15)) 5477 vars->link_status |= 5478 LINK_STATUS_PARALLEL_DETECTION_USED; 5479 } 5480 bnx2x_ext_phy_resolve_fc(phy, params, vars); 5481 vars->duplex = duplex; 5482 } 5483 } 5484 5485 if ((vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) && 5486 SINGLE_MEDIA_DIRECT(params)) { 5487 u16 val; 5488 5489 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, 5490 MDIO_AN_REG_LP_AUTO_NEG2, &val); 5491 5492 if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX) 5493 vars->link_status |= 5494 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; 5495 if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 | 5496 MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR)) 5497 vars->link_status |= 5498 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; 5499 5500 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 5501 MDIO_WC_REG_DIGITAL3_LP_UP1, &val); 5502 5503 if (val & MDIO_OVER_1G_UP1_2_5G) 5504 vars->link_status |= 5505 LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE; 5506 if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH)) 5507 vars->link_status |= 5508 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; 5509 5510 } 5511 5512 5513 if (lane < 2) { 5514 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 5515 MDIO_WC_REG_GP2_STATUS_GP_2_2, &gp_speed); 5516 } else { 5517 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 5518 MDIO_WC_REG_GP2_STATUS_GP_2_3, &gp_speed); 5519 } 5520 DP(NETIF_MSG_LINK, "lane %d gp_speed 0x%x\n", lane, gp_speed); 5521 5522 if ((lane & 1) == 0) 5523 gp_speed <<= 8; 5524 gp_speed &= 0x3f00; 5525 5526 5527 rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, gp_speed, 5528 duplex); 5529 5530 DP(NETIF_MSG_LINK, "duplex %x flow_ctrl 0x%x link_status 0x%x\n", 5531 vars->duplex, vars->flow_ctrl, vars->link_status); 5532 return rc; 5533 } 5534 static void bnx2x_set_gmii_tx_driver(struct link_params *params) 5535 { 5536 struct bnx2x *bp = params->bp; 5537 struct bnx2x_phy *phy = ¶ms->phy[INT_PHY]; 5538 u16 lp_up2; 5539 u16 tx_driver; 5540 u16 bank; 5541 5542 /* Read precomp */ 5543 CL22_RD_OVER_CL45(bp, phy, 5544 MDIO_REG_BANK_OVER_1G, 5545 MDIO_OVER_1G_LP_UP2, &lp_up2); 5546 5547 /* Bits [10:7] at lp_up2, positioned at [15:12] */ 5548 lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >> 5549 MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) << 5550 MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT); 5551 5552 if (lp_up2 == 0) 5553 return; 5554 5555 for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3; 5556 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) { 5557 CL22_RD_OVER_CL45(bp, phy, 5558 bank, 5559 MDIO_TX0_TX_DRIVER, &tx_driver); 5560 5561 /* Replace tx_driver bits [15:12] */ 5562 if (lp_up2 != 5563 (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) { 5564 tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK; 5565 tx_driver |= lp_up2; 5566 CL22_WR_OVER_CL45(bp, phy, 5567 bank, 5568 MDIO_TX0_TX_DRIVER, tx_driver); 5569 } 5570 } 5571 } 5572 5573 static int bnx2x_emac_program(struct link_params *params, 5574 struct link_vars *vars) 5575 { 5576 struct bnx2x *bp = params->bp; 5577 u8 port = params->port; 5578 u16 mode = 0; 5579 5580 DP(NETIF_MSG_LINK, "setting link speed & duplex\n"); 5581 bnx2x_bits_dis(bp, GRCBASE_EMAC0 + port*0x400 + 5582 EMAC_REG_EMAC_MODE, 5583 (EMAC_MODE_25G_MODE | 5584 EMAC_MODE_PORT_MII_10M | 5585 EMAC_MODE_HALF_DUPLEX)); 5586 switch (vars->line_speed) { 5587 case SPEED_10: 5588 mode |= EMAC_MODE_PORT_MII_10M; 5589 break; 5590 5591 case SPEED_100: 5592 mode |= EMAC_MODE_PORT_MII; 5593 break; 5594 5595 case SPEED_1000: 5596 mode |= EMAC_MODE_PORT_GMII; 5597 break; 5598 5599 case SPEED_2500: 5600 mode |= (EMAC_MODE_25G_MODE | EMAC_MODE_PORT_GMII); 5601 break; 5602 5603 default: 5604 /* 10G not valid for EMAC */ 5605 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n", 5606 vars->line_speed); 5607 return -EINVAL; 5608 } 5609 5610 if (vars->duplex == DUPLEX_HALF) 5611 mode |= EMAC_MODE_HALF_DUPLEX; 5612 bnx2x_bits_en(bp, 5613 GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE, 5614 mode); 5615 5616 bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed); 5617 return 0; 5618 } 5619 5620 static void bnx2x_set_preemphasis(struct bnx2x_phy *phy, 5621 struct link_params *params) 5622 { 5623 5624 u16 bank, i = 0; 5625 struct bnx2x *bp = params->bp; 5626 5627 for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3; 5628 bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0), i++) { 5629 CL22_WR_OVER_CL45(bp, phy, 5630 bank, 5631 MDIO_RX0_RX_EQ_BOOST, 5632 phy->rx_preemphasis[i]); 5633 } 5634 5635 for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3; 5636 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) { 5637 CL22_WR_OVER_CL45(bp, phy, 5638 bank, 5639 MDIO_TX0_TX_DRIVER, 5640 phy->tx_preemphasis[i]); 5641 } 5642 } 5643 5644 static void bnx2x_xgxs_config_init(struct bnx2x_phy *phy, 5645 struct link_params *params, 5646 struct link_vars *vars) 5647 { 5648 struct bnx2x *bp = params->bp; 5649 u8 enable_cl73 = (SINGLE_MEDIA_DIRECT(params) || 5650 (params->loopback_mode == LOOPBACK_XGXS)); 5651 if (!(vars->phy_flags & PHY_SGMII_FLAG)) { 5652 if (SINGLE_MEDIA_DIRECT(params) && 5653 (params->feature_config_flags & 5654 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) 5655 bnx2x_set_preemphasis(phy, params); 5656 5657 /* Forced speed requested? */ 5658 if (vars->line_speed != SPEED_AUTO_NEG || 5659 (SINGLE_MEDIA_DIRECT(params) && 5660 params->loopback_mode == LOOPBACK_EXT)) { 5661 DP(NETIF_MSG_LINK, "not SGMII, no AN\n"); 5662 5663 /* Disable autoneg */ 5664 bnx2x_set_autoneg(phy, params, vars, 0); 5665 5666 /* Program speed and duplex */ 5667 bnx2x_program_serdes(phy, params, vars); 5668 5669 } else { /* AN_mode */ 5670 DP(NETIF_MSG_LINK, "not SGMII, AN\n"); 5671 5672 /* AN enabled */ 5673 bnx2x_set_brcm_cl37_advertisement(phy, params); 5674 5675 /* Program duplex & pause advertisement (for aneg) */ 5676 bnx2x_set_ieee_aneg_advertisement(phy, params, 5677 vars->ieee_fc); 5678 5679 /* Enable autoneg */ 5680 bnx2x_set_autoneg(phy, params, vars, enable_cl73); 5681 5682 /* Enable and restart AN */ 5683 bnx2x_restart_autoneg(phy, params, enable_cl73); 5684 } 5685 5686 } else { /* SGMII mode */ 5687 DP(NETIF_MSG_LINK, "SGMII\n"); 5688 5689 bnx2x_initialize_sgmii_process(phy, params, vars); 5690 } 5691 } 5692 5693 static int bnx2x_prepare_xgxs(struct bnx2x_phy *phy, 5694 struct link_params *params, 5695 struct link_vars *vars) 5696 { 5697 int rc; 5698 vars->phy_flags |= PHY_XGXS_FLAG; 5699 if ((phy->req_line_speed && 5700 ((phy->req_line_speed == SPEED_100) || 5701 (phy->req_line_speed == SPEED_10))) || 5702 (!phy->req_line_speed && 5703 (phy->speed_cap_mask >= 5704 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) && 5705 (phy->speed_cap_mask < 5706 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) || 5707 (phy->type == PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD)) 5708 vars->phy_flags |= PHY_SGMII_FLAG; 5709 else 5710 vars->phy_flags &= ~PHY_SGMII_FLAG; 5711 5712 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); 5713 bnx2x_set_aer_mmd(params, phy); 5714 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) 5715 bnx2x_set_master_ln(params, phy); 5716 5717 rc = bnx2x_reset_unicore(params, phy, 0); 5718 /* Reset the SerDes and wait for reset bit return low */ 5719 if (rc) 5720 return rc; 5721 5722 bnx2x_set_aer_mmd(params, phy); 5723 /* Setting the masterLn_def again after the reset */ 5724 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) { 5725 bnx2x_set_master_ln(params, phy); 5726 bnx2x_set_swap_lanes(params, phy); 5727 } 5728 5729 return rc; 5730 } 5731 5732 static u16 bnx2x_wait_reset_complete(struct bnx2x *bp, 5733 struct bnx2x_phy *phy, 5734 struct link_params *params) 5735 { 5736 u16 cnt, ctrl; 5737 /* Wait for soft reset to get cleared up to 1 sec */ 5738 for (cnt = 0; cnt < 1000; cnt++) { 5739 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) 5740 bnx2x_cl22_read(bp, phy, 5741 MDIO_PMA_REG_CTRL, &ctrl); 5742 else 5743 bnx2x_cl45_read(bp, phy, 5744 MDIO_PMA_DEVAD, 5745 MDIO_PMA_REG_CTRL, &ctrl); 5746 if (!(ctrl & (1<<15))) 5747 break; 5748 usleep_range(1000, 2000); 5749 } 5750 5751 if (cnt == 1000) 5752 netdev_err(bp->dev, "Warning: PHY was not initialized," 5753 " Port %d\n", 5754 params->port); 5755 DP(NETIF_MSG_LINK, "control reg 0x%x (after %d ms)\n", ctrl, cnt); 5756 return cnt; 5757 } 5758 5759 static void bnx2x_link_int_enable(struct link_params *params) 5760 { 5761 u8 port = params->port; 5762 u32 mask; 5763 struct bnx2x *bp = params->bp; 5764 5765 /* Setting the status to report on link up for either XGXS or SerDes */ 5766 if (CHIP_IS_E3(bp)) { 5767 mask = NIG_MASK_XGXS0_LINK_STATUS; 5768 if (!(SINGLE_MEDIA_DIRECT(params))) 5769 mask |= NIG_MASK_MI_INT; 5770 } else if (params->switch_cfg == SWITCH_CFG_10G) { 5771 mask = (NIG_MASK_XGXS0_LINK10G | 5772 NIG_MASK_XGXS0_LINK_STATUS); 5773 DP(NETIF_MSG_LINK, "enabled XGXS interrupt\n"); 5774 if (!(SINGLE_MEDIA_DIRECT(params)) && 5775 params->phy[INT_PHY].type != 5776 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) { 5777 mask |= NIG_MASK_MI_INT; 5778 DP(NETIF_MSG_LINK, "enabled external phy int\n"); 5779 } 5780 5781 } else { /* SerDes */ 5782 mask = NIG_MASK_SERDES0_LINK_STATUS; 5783 DP(NETIF_MSG_LINK, "enabled SerDes interrupt\n"); 5784 if (!(SINGLE_MEDIA_DIRECT(params)) && 5785 params->phy[INT_PHY].type != 5786 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN) { 5787 mask |= NIG_MASK_MI_INT; 5788 DP(NETIF_MSG_LINK, "enabled external phy int\n"); 5789 } 5790 } 5791 bnx2x_bits_en(bp, 5792 NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 5793 mask); 5794 5795 DP(NETIF_MSG_LINK, "port %x, is_xgxs %x, int_status 0x%x\n", port, 5796 (params->switch_cfg == SWITCH_CFG_10G), 5797 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4)); 5798 DP(NETIF_MSG_LINK, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x\n", 5799 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4), 5800 REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18), 5801 REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS+port*0x3c)); 5802 DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n", 5803 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68), 5804 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68)); 5805 } 5806 5807 static void bnx2x_rearm_latch_signal(struct bnx2x *bp, u8 port, 5808 u8 exp_mi_int) 5809 { 5810 u32 latch_status = 0; 5811 5812 /* Disable the MI INT ( external phy int ) by writing 1 to the 5813 * status register. Link down indication is high-active-signal, 5814 * so in this case we need to write the status to clear the XOR 5815 */ 5816 /* Read Latched signals */ 5817 latch_status = REG_RD(bp, 5818 NIG_REG_LATCH_STATUS_0 + port*8); 5819 DP(NETIF_MSG_LINK, "latch_status = 0x%x\n", latch_status); 5820 /* Handle only those with latched-signal=up.*/ 5821 if (exp_mi_int) 5822 bnx2x_bits_en(bp, 5823 NIG_REG_STATUS_INTERRUPT_PORT0 5824 + port*4, 5825 NIG_STATUS_EMAC0_MI_INT); 5826 else 5827 bnx2x_bits_dis(bp, 5828 NIG_REG_STATUS_INTERRUPT_PORT0 5829 + port*4, 5830 NIG_STATUS_EMAC0_MI_INT); 5831 5832 if (latch_status & 1) { 5833 5834 /* For all latched-signal=up : Re-Arm Latch signals */ 5835 REG_WR(bp, NIG_REG_LATCH_STATUS_0 + port*8, 5836 (latch_status & 0xfffe) | (latch_status & 1)); 5837 } 5838 /* For all latched-signal=up,Write original_signal to status */ 5839 } 5840 5841 static void bnx2x_link_int_ack(struct link_params *params, 5842 struct link_vars *vars, u8 is_10g_plus) 5843 { 5844 struct bnx2x *bp = params->bp; 5845 u8 port = params->port; 5846 u32 mask; 5847 /* First reset all status we assume only one line will be 5848 * change at a time 5849 */ 5850 bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4, 5851 (NIG_STATUS_XGXS0_LINK10G | 5852 NIG_STATUS_XGXS0_LINK_STATUS | 5853 NIG_STATUS_SERDES0_LINK_STATUS)); 5854 if (vars->phy_link_up) { 5855 if (USES_WARPCORE(bp)) 5856 mask = NIG_STATUS_XGXS0_LINK_STATUS; 5857 else { 5858 if (is_10g_plus) 5859 mask = NIG_STATUS_XGXS0_LINK10G; 5860 else if (params->switch_cfg == SWITCH_CFG_10G) { 5861 /* Disable the link interrupt by writing 1 to 5862 * the relevant lane in the status register 5863 */ 5864 u32 ser_lane = 5865 ((params->lane_config & 5866 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >> 5867 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT); 5868 mask = ((1 << ser_lane) << 5869 NIG_STATUS_XGXS0_LINK_STATUS_SIZE); 5870 } else 5871 mask = NIG_STATUS_SERDES0_LINK_STATUS; 5872 } 5873 DP(NETIF_MSG_LINK, "Ack link up interrupt with mask 0x%x\n", 5874 mask); 5875 bnx2x_bits_en(bp, 5876 NIG_REG_STATUS_INTERRUPT_PORT0 + port*4, 5877 mask); 5878 } 5879 } 5880 5881 static int bnx2x_format_ver(u32 num, u8 *str, u16 *len) 5882 { 5883 u8 *str_ptr = str; 5884 u32 mask = 0xf0000000; 5885 u8 shift = 8*4; 5886 u8 digit; 5887 u8 remove_leading_zeros = 1; 5888 if (*len < 10) { 5889 /* Need more than 10chars for this format */ 5890 *str_ptr = '\0'; 5891 (*len)--; 5892 return -EINVAL; 5893 } 5894 while (shift > 0) { 5895 5896 shift -= 4; 5897 digit = ((num & mask) >> shift); 5898 if (digit == 0 && remove_leading_zeros) { 5899 mask = mask >> 4; 5900 continue; 5901 } else if (digit < 0xa) 5902 *str_ptr = digit + '0'; 5903 else 5904 *str_ptr = digit - 0xa + 'a'; 5905 remove_leading_zeros = 0; 5906 str_ptr++; 5907 (*len)--; 5908 mask = mask >> 4; 5909 if (shift == 4*4) { 5910 *str_ptr = '.'; 5911 str_ptr++; 5912 (*len)--; 5913 remove_leading_zeros = 1; 5914 } 5915 } 5916 return 0; 5917 } 5918 5919 5920 static int bnx2x_null_format_ver(u32 spirom_ver, u8 *str, u16 *len) 5921 { 5922 str[0] = '\0'; 5923 (*len)--; 5924 return 0; 5925 } 5926 5927 int bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 *version, 5928 u16 len) 5929 { 5930 struct bnx2x *bp; 5931 u32 spirom_ver = 0; 5932 int status = 0; 5933 u8 *ver_p = version; 5934 u16 remain_len = len; 5935 if (version == NULL || params == NULL) 5936 return -EINVAL; 5937 bp = params->bp; 5938 5939 /* Extract first external phy*/ 5940 version[0] = '\0'; 5941 spirom_ver = REG_RD(bp, params->phy[EXT_PHY1].ver_addr); 5942 5943 if (params->phy[EXT_PHY1].format_fw_ver) { 5944 status |= params->phy[EXT_PHY1].format_fw_ver(spirom_ver, 5945 ver_p, 5946 &remain_len); 5947 ver_p += (len - remain_len); 5948 } 5949 if ((params->num_phys == MAX_PHYS) && 5950 (params->phy[EXT_PHY2].ver_addr != 0)) { 5951 spirom_ver = REG_RD(bp, params->phy[EXT_PHY2].ver_addr); 5952 if (params->phy[EXT_PHY2].format_fw_ver) { 5953 *ver_p = '/'; 5954 ver_p++; 5955 remain_len--; 5956 status |= params->phy[EXT_PHY2].format_fw_ver( 5957 spirom_ver, 5958 ver_p, 5959 &remain_len); 5960 ver_p = version + (len - remain_len); 5961 } 5962 } 5963 *ver_p = '\0'; 5964 return status; 5965 } 5966 5967 static void bnx2x_set_xgxs_loopback(struct bnx2x_phy *phy, 5968 struct link_params *params) 5969 { 5970 u8 port = params->port; 5971 struct bnx2x *bp = params->bp; 5972 5973 if (phy->req_line_speed != SPEED_1000) { 5974 u32 md_devad = 0; 5975 5976 DP(NETIF_MSG_LINK, "XGXS 10G loopback enable\n"); 5977 5978 if (!CHIP_IS_E3(bp)) { 5979 /* Change the uni_phy_addr in the nig */ 5980 md_devad = REG_RD(bp, (NIG_REG_XGXS0_CTRL_MD_DEVAD + 5981 port*0x18)); 5982 5983 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, 5984 0x5); 5985 } 5986 5987 bnx2x_cl45_write(bp, phy, 5988 5, 5989 (MDIO_REG_BANK_AER_BLOCK + 5990 (MDIO_AER_BLOCK_AER_REG & 0xf)), 5991 0x2800); 5992 5993 bnx2x_cl45_write(bp, phy, 5994 5, 5995 (MDIO_REG_BANK_CL73_IEEEB0 + 5996 (MDIO_CL73_IEEEB0_CL73_AN_CONTROL & 0xf)), 5997 0x6041); 5998 msleep(200); 5999 /* Set aer mmd back */ 6000 bnx2x_set_aer_mmd(params, phy); 6001 6002 if (!CHIP_IS_E3(bp)) { 6003 /* And md_devad */ 6004 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, 6005 md_devad); 6006 } 6007 } else { 6008 u16 mii_ctrl; 6009 DP(NETIF_MSG_LINK, "XGXS 1G loopback enable\n"); 6010 bnx2x_cl45_read(bp, phy, 5, 6011 (MDIO_REG_BANK_COMBO_IEEE0 + 6012 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)), 6013 &mii_ctrl); 6014 bnx2x_cl45_write(bp, phy, 5, 6015 (MDIO_REG_BANK_COMBO_IEEE0 + 6016 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)), 6017 mii_ctrl | 6018 MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK); 6019 } 6020 } 6021 6022 int bnx2x_set_led(struct link_params *params, 6023 struct link_vars *vars, u8 mode, u32 speed) 6024 { 6025 u8 port = params->port; 6026 u16 hw_led_mode = params->hw_led_mode; 6027 int rc = 0; 6028 u8 phy_idx; 6029 u32 tmp; 6030 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; 6031 struct bnx2x *bp = params->bp; 6032 DP(NETIF_MSG_LINK, "bnx2x_set_led: port %x, mode %d\n", port, mode); 6033 DP(NETIF_MSG_LINK, "speed 0x%x, hw_led_mode 0x%x\n", 6034 speed, hw_led_mode); 6035 /* In case */ 6036 for (phy_idx = EXT_PHY1; phy_idx < MAX_PHYS; phy_idx++) { 6037 if (params->phy[phy_idx].set_link_led) { 6038 params->phy[phy_idx].set_link_led( 6039 ¶ms->phy[phy_idx], params, mode); 6040 } 6041 } 6042 6043 switch (mode) { 6044 case LED_MODE_FRONT_PANEL_OFF: 6045 case LED_MODE_OFF: 6046 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 0); 6047 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 6048 SHARED_HW_CFG_LED_MAC1); 6049 6050 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED); 6051 if (params->phy[EXT_PHY1].type == 6052 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) 6053 tmp &= ~(EMAC_LED_1000MB_OVERRIDE | 6054 EMAC_LED_100MB_OVERRIDE | 6055 EMAC_LED_10MB_OVERRIDE); 6056 else 6057 tmp |= EMAC_LED_OVERRIDE; 6058 6059 EMAC_WR(bp, EMAC_REG_EMAC_LED, tmp); 6060 break; 6061 6062 case LED_MODE_OPER: 6063 /* For all other phys, OPER mode is same as ON, so in case 6064 * link is down, do nothing 6065 */ 6066 if (!vars->link_up) 6067 break; 6068 case LED_MODE_ON: 6069 if (((params->phy[EXT_PHY1].type == 6070 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) || 6071 (params->phy[EXT_PHY1].type == 6072 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722)) && 6073 CHIP_IS_E2(bp) && params->num_phys == 2) { 6074 /* This is a work-around for E2+8727 Configurations */ 6075 if (mode == LED_MODE_ON || 6076 speed == SPEED_10000){ 6077 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0); 6078 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1); 6079 6080 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED); 6081 EMAC_WR(bp, EMAC_REG_EMAC_LED, 6082 (tmp | EMAC_LED_OVERRIDE)); 6083 /* Return here without enabling traffic 6084 * LED blink and setting rate in ON mode. 6085 * In oper mode, enabling LED blink 6086 * and setting rate is needed. 6087 */ 6088 if (mode == LED_MODE_ON) 6089 return rc; 6090 } 6091 } else if (SINGLE_MEDIA_DIRECT(params)) { 6092 /* This is a work-around for HW issue found when link 6093 * is up in CL73 6094 */ 6095 if ((!CHIP_IS_E3(bp)) || 6096 (CHIP_IS_E3(bp) && 6097 mode == LED_MODE_ON)) 6098 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1); 6099 6100 if (CHIP_IS_E1x(bp) || 6101 CHIP_IS_E2(bp) || 6102 (mode == LED_MODE_ON)) 6103 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0); 6104 else 6105 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 6106 hw_led_mode); 6107 } else if ((params->phy[EXT_PHY1].type == 6108 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) && 6109 (mode == LED_MODE_ON)) { 6110 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0); 6111 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED); 6112 EMAC_WR(bp, EMAC_REG_EMAC_LED, tmp | 6113 EMAC_LED_OVERRIDE | EMAC_LED_1000MB_OVERRIDE); 6114 /* Break here; otherwise, it'll disable the 6115 * intended override. 6116 */ 6117 break; 6118 } else 6119 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 6120 hw_led_mode); 6121 6122 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 0); 6123 /* Set blinking rate to ~15.9Hz */ 6124 if (CHIP_IS_E3(bp)) 6125 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4, 6126 LED_BLINK_RATE_VAL_E3); 6127 else 6128 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4, 6129 LED_BLINK_RATE_VAL_E1X_E2); 6130 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 + 6131 port*4, 1); 6132 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED); 6133 EMAC_WR(bp, EMAC_REG_EMAC_LED, 6134 (tmp & (~EMAC_LED_OVERRIDE))); 6135 6136 if (CHIP_IS_E1(bp) && 6137 ((speed == SPEED_2500) || 6138 (speed == SPEED_1000) || 6139 (speed == SPEED_100) || 6140 (speed == SPEED_10))) { 6141 /* For speeds less than 10G LED scheme is different */ 6142 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 6143 + port*4, 1); 6144 REG_WR(bp, NIG_REG_LED_CONTROL_TRAFFIC_P0 + 6145 port*4, 0); 6146 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 + 6147 port*4, 1); 6148 } 6149 break; 6150 6151 default: 6152 rc = -EINVAL; 6153 DP(NETIF_MSG_LINK, "bnx2x_set_led: Invalid led mode %d\n", 6154 mode); 6155 break; 6156 } 6157 return rc; 6158 6159 } 6160 6161 /* This function comes to reflect the actual link state read DIRECTLY from the 6162 * HW 6163 */ 6164 int bnx2x_test_link(struct link_params *params, struct link_vars *vars, 6165 u8 is_serdes) 6166 { 6167 struct bnx2x *bp = params->bp; 6168 u16 gp_status = 0, phy_index = 0; 6169 u8 ext_phy_link_up = 0, serdes_phy_type; 6170 struct link_vars temp_vars; 6171 struct bnx2x_phy *int_phy = ¶ms->phy[INT_PHY]; 6172 6173 if (CHIP_IS_E3(bp)) { 6174 u16 link_up; 6175 if (params->req_line_speed[LINK_CONFIG_IDX(INT_PHY)] 6176 > SPEED_10000) { 6177 /* Check 20G link */ 6178 bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD, 6179 1, &link_up); 6180 bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD, 6181 1, &link_up); 6182 link_up &= (1<<2); 6183 } else { 6184 /* Check 10G link and below*/ 6185 u8 lane = bnx2x_get_warpcore_lane(int_phy, params); 6186 bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD, 6187 MDIO_WC_REG_GP2_STATUS_GP_2_1, 6188 &gp_status); 6189 gp_status = ((gp_status >> 8) & 0xf) | 6190 ((gp_status >> 12) & 0xf); 6191 link_up = gp_status & (1 << lane); 6192 } 6193 if (!link_up) 6194 return -ESRCH; 6195 } else { 6196 CL22_RD_OVER_CL45(bp, int_phy, 6197 MDIO_REG_BANK_GP_STATUS, 6198 MDIO_GP_STATUS_TOP_AN_STATUS1, 6199 &gp_status); 6200 /* Link is up only if both local phy and external phy are up */ 6201 if (!(gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS)) 6202 return -ESRCH; 6203 } 6204 /* In XGXS loopback mode, do not check external PHY */ 6205 if (params->loopback_mode == LOOPBACK_XGXS) 6206 return 0; 6207 6208 switch (params->num_phys) { 6209 case 1: 6210 /* No external PHY */ 6211 return 0; 6212 case 2: 6213 ext_phy_link_up = params->phy[EXT_PHY1].read_status( 6214 ¶ms->phy[EXT_PHY1], 6215 params, &temp_vars); 6216 break; 6217 case 3: /* Dual Media */ 6218 for (phy_index = EXT_PHY1; phy_index < params->num_phys; 6219 phy_index++) { 6220 serdes_phy_type = ((params->phy[phy_index].media_type == 6221 ETH_PHY_SFPP_10G_FIBER) || 6222 (params->phy[phy_index].media_type == 6223 ETH_PHY_SFP_1G_FIBER) || 6224 (params->phy[phy_index].media_type == 6225 ETH_PHY_XFP_FIBER) || 6226 (params->phy[phy_index].media_type == 6227 ETH_PHY_DA_TWINAX)); 6228 6229 if (is_serdes != serdes_phy_type) 6230 continue; 6231 if (params->phy[phy_index].read_status) { 6232 ext_phy_link_up |= 6233 params->phy[phy_index].read_status( 6234 ¶ms->phy[phy_index], 6235 params, &temp_vars); 6236 } 6237 } 6238 break; 6239 } 6240 if (ext_phy_link_up) 6241 return 0; 6242 return -ESRCH; 6243 } 6244 6245 static int bnx2x_link_initialize(struct link_params *params, 6246 struct link_vars *vars) 6247 { 6248 int rc = 0; 6249 u8 phy_index, non_ext_phy; 6250 struct bnx2x *bp = params->bp; 6251 /* In case of external phy existence, the line speed would be the 6252 * line speed linked up by the external phy. In case it is direct 6253 * only, then the line_speed during initialization will be 6254 * equal to the req_line_speed 6255 */ 6256 vars->line_speed = params->phy[INT_PHY].req_line_speed; 6257 6258 /* Initialize the internal phy in case this is a direct board 6259 * (no external phys), or this board has external phy which requires 6260 * to first. 6261 */ 6262 if (!USES_WARPCORE(bp)) 6263 bnx2x_prepare_xgxs(¶ms->phy[INT_PHY], params, vars); 6264 /* init ext phy and enable link state int */ 6265 non_ext_phy = (SINGLE_MEDIA_DIRECT(params) || 6266 (params->loopback_mode == LOOPBACK_XGXS)); 6267 6268 if (non_ext_phy || 6269 (params->phy[EXT_PHY1].flags & FLAGS_INIT_XGXS_FIRST) || 6270 (params->loopback_mode == LOOPBACK_EXT_PHY)) { 6271 struct bnx2x_phy *phy = ¶ms->phy[INT_PHY]; 6272 if (vars->line_speed == SPEED_AUTO_NEG && 6273 (CHIP_IS_E1x(bp) || 6274 CHIP_IS_E2(bp))) 6275 bnx2x_set_parallel_detection(phy, params); 6276 if (params->phy[INT_PHY].config_init) 6277 params->phy[INT_PHY].config_init(phy, 6278 params, 6279 vars); 6280 } 6281 6282 /* Init external phy*/ 6283 if (non_ext_phy) { 6284 if (params->phy[INT_PHY].supported & 6285 SUPPORTED_FIBRE) 6286 vars->link_status |= LINK_STATUS_SERDES_LINK; 6287 } else { 6288 for (phy_index = EXT_PHY1; phy_index < params->num_phys; 6289 phy_index++) { 6290 /* No need to initialize second phy in case of first 6291 * phy only selection. In case of second phy, we do 6292 * need to initialize the first phy, since they are 6293 * connected. 6294 */ 6295 if (params->phy[phy_index].supported & 6296 SUPPORTED_FIBRE) 6297 vars->link_status |= LINK_STATUS_SERDES_LINK; 6298 6299 if (phy_index == EXT_PHY2 && 6300 (bnx2x_phy_selection(params) == 6301 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY)) { 6302 DP(NETIF_MSG_LINK, 6303 "Not initializing second phy\n"); 6304 continue; 6305 } 6306 params->phy[phy_index].config_init( 6307 ¶ms->phy[phy_index], 6308 params, vars); 6309 } 6310 } 6311 /* Reset the interrupt indication after phy was initialized */ 6312 bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + 6313 params->port*4, 6314 (NIG_STATUS_XGXS0_LINK10G | 6315 NIG_STATUS_XGXS0_LINK_STATUS | 6316 NIG_STATUS_SERDES0_LINK_STATUS | 6317 NIG_MASK_MI_INT)); 6318 return rc; 6319 } 6320 6321 static void bnx2x_int_link_reset(struct bnx2x_phy *phy, 6322 struct link_params *params) 6323 { 6324 /* Reset the SerDes/XGXS */ 6325 REG_WR(params->bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, 6326 (0x1ff << (params->port*16))); 6327 } 6328 6329 static void bnx2x_common_ext_link_reset(struct bnx2x_phy *phy, 6330 struct link_params *params) 6331 { 6332 struct bnx2x *bp = params->bp; 6333 u8 gpio_port; 6334 /* HW reset */ 6335 if (CHIP_IS_E2(bp)) 6336 gpio_port = BP_PATH(bp); 6337 else 6338 gpio_port = params->port; 6339 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, 6340 MISC_REGISTERS_GPIO_OUTPUT_LOW, 6341 gpio_port); 6342 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 6343 MISC_REGISTERS_GPIO_OUTPUT_LOW, 6344 gpio_port); 6345 DP(NETIF_MSG_LINK, "reset external PHY\n"); 6346 } 6347 6348 static int bnx2x_update_link_down(struct link_params *params, 6349 struct link_vars *vars) 6350 { 6351 struct bnx2x *bp = params->bp; 6352 u8 port = params->port; 6353 6354 DP(NETIF_MSG_LINK, "Port %x: Link is down\n", port); 6355 bnx2x_set_led(params, vars, LED_MODE_OFF, 0); 6356 vars->phy_flags &= ~PHY_PHYSICAL_LINK_FLAG; 6357 /* Indicate no mac active */ 6358 vars->mac_type = MAC_TYPE_NONE; 6359 6360 /* Update shared memory */ 6361 vars->link_status &= ~LINK_UPDATE_MASK; 6362 vars->line_speed = 0; 6363 bnx2x_update_mng(params, vars->link_status); 6364 6365 /* Activate nig drain */ 6366 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1); 6367 6368 /* Disable emac */ 6369 if (!CHIP_IS_E3(bp)) 6370 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0); 6371 6372 usleep_range(10000, 20000); 6373 /* Reset BigMac/Xmac */ 6374 if (CHIP_IS_E1x(bp) || 6375 CHIP_IS_E2(bp)) 6376 bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 0); 6377 6378 if (CHIP_IS_E3(bp)) { 6379 /* Prevent LPI Generation by chip */ 6380 REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2), 6381 0); 6382 REG_WR(bp, MISC_REG_CPMU_LP_MASK_ENT_P0 + (params->port << 2), 6383 0); 6384 vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK | 6385 SHMEM_EEE_ACTIVE_BIT); 6386 6387 bnx2x_update_mng_eee(params, vars->eee_status); 6388 bnx2x_set_xmac_rxtx(params, 0); 6389 bnx2x_set_umac_rxtx(params, 0); 6390 } 6391 6392 return 0; 6393 } 6394 6395 static int bnx2x_update_link_up(struct link_params *params, 6396 struct link_vars *vars, 6397 u8 link_10g) 6398 { 6399 struct bnx2x *bp = params->bp; 6400 u8 phy_idx, port = params->port; 6401 int rc = 0; 6402 6403 vars->link_status |= (LINK_STATUS_LINK_UP | 6404 LINK_STATUS_PHYSICAL_LINK_FLAG); 6405 vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG; 6406 6407 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) 6408 vars->link_status |= 6409 LINK_STATUS_TX_FLOW_CONTROL_ENABLED; 6410 6411 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX) 6412 vars->link_status |= 6413 LINK_STATUS_RX_FLOW_CONTROL_ENABLED; 6414 if (USES_WARPCORE(bp)) { 6415 if (link_10g) { 6416 if (bnx2x_xmac_enable(params, vars, 0) == 6417 -ESRCH) { 6418 DP(NETIF_MSG_LINK, "Found errors on XMAC\n"); 6419 vars->link_up = 0; 6420 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG; 6421 vars->link_status &= ~LINK_STATUS_LINK_UP; 6422 } 6423 } else 6424 bnx2x_umac_enable(params, vars, 0); 6425 bnx2x_set_led(params, vars, 6426 LED_MODE_OPER, vars->line_speed); 6427 6428 if ((vars->eee_status & SHMEM_EEE_ACTIVE_BIT) && 6429 (vars->eee_status & SHMEM_EEE_LPI_REQUESTED_BIT)) { 6430 DP(NETIF_MSG_LINK, "Enabling LPI assertion\n"); 6431 REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + 6432 (params->port << 2), 1); 6433 REG_WR(bp, MISC_REG_CPMU_LP_DR_ENABLE, 1); 6434 REG_WR(bp, MISC_REG_CPMU_LP_MASK_ENT_P0 + 6435 (params->port << 2), 0xfc20); 6436 } 6437 } 6438 if ((CHIP_IS_E1x(bp) || 6439 CHIP_IS_E2(bp))) { 6440 if (link_10g) { 6441 if (bnx2x_bmac_enable(params, vars, 0, 1) == 6442 -ESRCH) { 6443 DP(NETIF_MSG_LINK, "Found errors on BMAC\n"); 6444 vars->link_up = 0; 6445 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG; 6446 vars->link_status &= ~LINK_STATUS_LINK_UP; 6447 } 6448 6449 bnx2x_set_led(params, vars, 6450 LED_MODE_OPER, SPEED_10000); 6451 } else { 6452 rc = bnx2x_emac_program(params, vars); 6453 bnx2x_emac_enable(params, vars, 0); 6454 6455 /* AN complete? */ 6456 if ((vars->link_status & 6457 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) 6458 && (!(vars->phy_flags & PHY_SGMII_FLAG)) && 6459 SINGLE_MEDIA_DIRECT(params)) 6460 bnx2x_set_gmii_tx_driver(params); 6461 } 6462 } 6463 6464 /* PBF - link up */ 6465 if (CHIP_IS_E1x(bp)) 6466 rc |= bnx2x_pbf_update(params, vars->flow_ctrl, 6467 vars->line_speed); 6468 6469 /* Disable drain */ 6470 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0); 6471 6472 /* Update shared memory */ 6473 bnx2x_update_mng(params, vars->link_status); 6474 bnx2x_update_mng_eee(params, vars->eee_status); 6475 /* Check remote fault */ 6476 for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) { 6477 if (params->phy[phy_idx].flags & FLAGS_TX_ERROR_CHECK) { 6478 bnx2x_check_half_open_conn(params, vars, 0); 6479 break; 6480 } 6481 } 6482 msleep(20); 6483 return rc; 6484 } 6485 /* The bnx2x_link_update function should be called upon link 6486 * interrupt. 6487 * Link is considered up as follows: 6488 * - DIRECT_SINGLE_MEDIA - Only XGXS link (internal link) needs 6489 * to be up 6490 * - SINGLE_MEDIA - The link between the 577xx and the external 6491 * phy (XGXS) need to up as well as the external link of the 6492 * phy (PHY_EXT1) 6493 * - DUAL_MEDIA - The link between the 577xx and the first 6494 * external phy needs to be up, and at least one of the 2 6495 * external phy link must be up. 6496 */ 6497 int bnx2x_link_update(struct link_params *params, struct link_vars *vars) 6498 { 6499 struct bnx2x *bp = params->bp; 6500 struct link_vars phy_vars[MAX_PHYS]; 6501 u8 port = params->port; 6502 u8 link_10g_plus, phy_index; 6503 u8 ext_phy_link_up = 0, cur_link_up; 6504 int rc = 0; 6505 u8 is_mi_int = 0; 6506 u16 ext_phy_line_speed = 0, prev_line_speed = vars->line_speed; 6507 u8 active_external_phy = INT_PHY; 6508 vars->phy_flags &= ~PHY_HALF_OPEN_CONN_FLAG; 6509 vars->link_status &= ~LINK_UPDATE_MASK; 6510 for (phy_index = INT_PHY; phy_index < params->num_phys; 6511 phy_index++) { 6512 phy_vars[phy_index].flow_ctrl = 0; 6513 phy_vars[phy_index].link_status = 0; 6514 phy_vars[phy_index].line_speed = 0; 6515 phy_vars[phy_index].duplex = DUPLEX_FULL; 6516 phy_vars[phy_index].phy_link_up = 0; 6517 phy_vars[phy_index].link_up = 0; 6518 phy_vars[phy_index].fault_detected = 0; 6519 /* different consideration, since vars holds inner state */ 6520 phy_vars[phy_index].eee_status = vars->eee_status; 6521 } 6522 6523 if (USES_WARPCORE(bp)) 6524 bnx2x_set_aer_mmd(params, ¶ms->phy[INT_PHY]); 6525 6526 DP(NETIF_MSG_LINK, "port %x, XGXS?%x, int_status 0x%x\n", 6527 port, (vars->phy_flags & PHY_XGXS_FLAG), 6528 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4)); 6529 6530 is_mi_int = (u8)(REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + 6531 port*0x18) > 0); 6532 DP(NETIF_MSG_LINK, "int_mask 0x%x MI_INT %x, SERDES_LINK %x\n", 6533 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4), 6534 is_mi_int, 6535 REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c)); 6536 6537 DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n", 6538 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68), 6539 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68)); 6540 6541 /* Disable emac */ 6542 if (!CHIP_IS_E3(bp)) 6543 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0); 6544 6545 /* Step 1: 6546 * Check external link change only for external phys, and apply 6547 * priority selection between them in case the link on both phys 6548 * is up. Note that instead of the common vars, a temporary 6549 * vars argument is used since each phy may have different link/ 6550 * speed/duplex result 6551 */ 6552 for (phy_index = EXT_PHY1; phy_index < params->num_phys; 6553 phy_index++) { 6554 struct bnx2x_phy *phy = ¶ms->phy[phy_index]; 6555 if (!phy->read_status) 6556 continue; 6557 /* Read link status and params of this ext phy */ 6558 cur_link_up = phy->read_status(phy, params, 6559 &phy_vars[phy_index]); 6560 if (cur_link_up) { 6561 DP(NETIF_MSG_LINK, "phy in index %d link is up\n", 6562 phy_index); 6563 } else { 6564 DP(NETIF_MSG_LINK, "phy in index %d link is down\n", 6565 phy_index); 6566 continue; 6567 } 6568 6569 if (!ext_phy_link_up) { 6570 ext_phy_link_up = 1; 6571 active_external_phy = phy_index; 6572 } else { 6573 switch (bnx2x_phy_selection(params)) { 6574 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT: 6575 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY: 6576 /* In this option, the first PHY makes sure to pass the 6577 * traffic through itself only. 6578 * Its not clear how to reset the link on the second phy 6579 */ 6580 active_external_phy = EXT_PHY1; 6581 break; 6582 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY: 6583 /* In this option, the first PHY makes sure to pass the 6584 * traffic through the second PHY. 6585 */ 6586 active_external_phy = EXT_PHY2; 6587 break; 6588 default: 6589 /* Link indication on both PHYs with the following cases 6590 * is invalid: 6591 * - FIRST_PHY means that second phy wasn't initialized, 6592 * hence its link is expected to be down 6593 * - SECOND_PHY means that first phy should not be able 6594 * to link up by itself (using configuration) 6595 * - DEFAULT should be overriden during initialiazation 6596 */ 6597 DP(NETIF_MSG_LINK, "Invalid link indication" 6598 "mpc=0x%x. DISABLING LINK !!!\n", 6599 params->multi_phy_config); 6600 ext_phy_link_up = 0; 6601 break; 6602 } 6603 } 6604 } 6605 prev_line_speed = vars->line_speed; 6606 /* Step 2: 6607 * Read the status of the internal phy. In case of 6608 * DIRECT_SINGLE_MEDIA board, this link is the external link, 6609 * otherwise this is the link between the 577xx and the first 6610 * external phy 6611 */ 6612 if (params->phy[INT_PHY].read_status) 6613 params->phy[INT_PHY].read_status( 6614 ¶ms->phy[INT_PHY], 6615 params, vars); 6616 /* The INT_PHY flow control reside in the vars. This include the 6617 * case where the speed or flow control are not set to AUTO. 6618 * Otherwise, the active external phy flow control result is set 6619 * to the vars. The ext_phy_line_speed is needed to check if the 6620 * speed is different between the internal phy and external phy. 6621 * This case may be result of intermediate link speed change. 6622 */ 6623 if (active_external_phy > INT_PHY) { 6624 vars->flow_ctrl = phy_vars[active_external_phy].flow_ctrl; 6625 /* Link speed is taken from the XGXS. AN and FC result from 6626 * the external phy. 6627 */ 6628 vars->link_status |= phy_vars[active_external_phy].link_status; 6629 6630 /* if active_external_phy is first PHY and link is up - disable 6631 * disable TX on second external PHY 6632 */ 6633 if (active_external_phy == EXT_PHY1) { 6634 if (params->phy[EXT_PHY2].phy_specific_func) { 6635 DP(NETIF_MSG_LINK, 6636 "Disabling TX on EXT_PHY2\n"); 6637 params->phy[EXT_PHY2].phy_specific_func( 6638 ¶ms->phy[EXT_PHY2], 6639 params, DISABLE_TX); 6640 } 6641 } 6642 6643 ext_phy_line_speed = phy_vars[active_external_phy].line_speed; 6644 vars->duplex = phy_vars[active_external_phy].duplex; 6645 if (params->phy[active_external_phy].supported & 6646 SUPPORTED_FIBRE) 6647 vars->link_status |= LINK_STATUS_SERDES_LINK; 6648 else 6649 vars->link_status &= ~LINK_STATUS_SERDES_LINK; 6650 6651 vars->eee_status = phy_vars[active_external_phy].eee_status; 6652 6653 DP(NETIF_MSG_LINK, "Active external phy selected: %x\n", 6654 active_external_phy); 6655 } 6656 6657 for (phy_index = EXT_PHY1; phy_index < params->num_phys; 6658 phy_index++) { 6659 if (params->phy[phy_index].flags & 6660 FLAGS_REARM_LATCH_SIGNAL) { 6661 bnx2x_rearm_latch_signal(bp, port, 6662 phy_index == 6663 active_external_phy); 6664 break; 6665 } 6666 } 6667 DP(NETIF_MSG_LINK, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x," 6668 " ext_phy_line_speed = %d\n", vars->flow_ctrl, 6669 vars->link_status, ext_phy_line_speed); 6670 /* Upon link speed change set the NIG into drain mode. Comes to 6671 * deals with possible FIFO glitch due to clk change when speed 6672 * is decreased without link down indicator 6673 */ 6674 6675 if (vars->phy_link_up) { 6676 if (!(SINGLE_MEDIA_DIRECT(params)) && ext_phy_link_up && 6677 (ext_phy_line_speed != vars->line_speed)) { 6678 DP(NETIF_MSG_LINK, "Internal link speed %d is" 6679 " different than the external" 6680 " link speed %d\n", vars->line_speed, 6681 ext_phy_line_speed); 6682 vars->phy_link_up = 0; 6683 } else if (prev_line_speed != vars->line_speed) { 6684 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 6685 0); 6686 usleep_range(1000, 2000); 6687 } 6688 } 6689 6690 /* Anything 10 and over uses the bmac */ 6691 link_10g_plus = (vars->line_speed >= SPEED_10000); 6692 6693 bnx2x_link_int_ack(params, vars, link_10g_plus); 6694 6695 /* In case external phy link is up, and internal link is down 6696 * (not initialized yet probably after link initialization, it 6697 * needs to be initialized. 6698 * Note that after link down-up as result of cable plug, the xgxs 6699 * link would probably become up again without the need 6700 * initialize it 6701 */ 6702 if (!(SINGLE_MEDIA_DIRECT(params))) { 6703 DP(NETIF_MSG_LINK, "ext_phy_link_up = %d, int_link_up = %d," 6704 " init_preceding = %d\n", ext_phy_link_up, 6705 vars->phy_link_up, 6706 params->phy[EXT_PHY1].flags & 6707 FLAGS_INIT_XGXS_FIRST); 6708 if (!(params->phy[EXT_PHY1].flags & 6709 FLAGS_INIT_XGXS_FIRST) 6710 && ext_phy_link_up && !vars->phy_link_up) { 6711 vars->line_speed = ext_phy_line_speed; 6712 if (vars->line_speed < SPEED_1000) 6713 vars->phy_flags |= PHY_SGMII_FLAG; 6714 else 6715 vars->phy_flags &= ~PHY_SGMII_FLAG; 6716 6717 if (params->phy[INT_PHY].config_init) 6718 params->phy[INT_PHY].config_init( 6719 ¶ms->phy[INT_PHY], params, 6720 vars); 6721 } 6722 } 6723 /* Link is up only if both local phy and external phy (in case of 6724 * non-direct board) are up and no fault detected on active PHY. 6725 */ 6726 vars->link_up = (vars->phy_link_up && 6727 (ext_phy_link_up || 6728 SINGLE_MEDIA_DIRECT(params)) && 6729 (phy_vars[active_external_phy].fault_detected == 0)); 6730 6731 /* Update the PFC configuration in case it was changed */ 6732 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) 6733 vars->link_status |= LINK_STATUS_PFC_ENABLED; 6734 else 6735 vars->link_status &= ~LINK_STATUS_PFC_ENABLED; 6736 6737 if (vars->link_up) 6738 rc = bnx2x_update_link_up(params, vars, link_10g_plus); 6739 else 6740 rc = bnx2x_update_link_down(params, vars); 6741 6742 /* Update MCP link status was changed */ 6743 if (params->feature_config_flags & FEATURE_CONFIG_BC_SUPPORTS_AFEX) 6744 bnx2x_fw_command(bp, DRV_MSG_CODE_LINK_STATUS_CHANGED, 0); 6745 6746 return rc; 6747 } 6748 6749 /*****************************************************************************/ 6750 /* External Phy section */ 6751 /*****************************************************************************/ 6752 void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port) 6753 { 6754 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, 6755 MISC_REGISTERS_GPIO_OUTPUT_LOW, port); 6756 usleep_range(1000, 2000); 6757 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, 6758 MISC_REGISTERS_GPIO_OUTPUT_HIGH, port); 6759 } 6760 6761 static void bnx2x_save_spirom_version(struct bnx2x *bp, u8 port, 6762 u32 spirom_ver, u32 ver_addr) 6763 { 6764 DP(NETIF_MSG_LINK, "FW version 0x%x:0x%x for port %d\n", 6765 (u16)(spirom_ver>>16), (u16)spirom_ver, port); 6766 6767 if (ver_addr) 6768 REG_WR(bp, ver_addr, spirom_ver); 6769 } 6770 6771 static void bnx2x_save_bcm_spirom_ver(struct bnx2x *bp, 6772 struct bnx2x_phy *phy, 6773 u8 port) 6774 { 6775 u16 fw_ver1, fw_ver2; 6776 6777 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 6778 MDIO_PMA_REG_ROM_VER1, &fw_ver1); 6779 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 6780 MDIO_PMA_REG_ROM_VER2, &fw_ver2); 6781 bnx2x_save_spirom_version(bp, port, (u32)(fw_ver1<<16 | fw_ver2), 6782 phy->ver_addr); 6783 } 6784 6785 static void bnx2x_ext_phy_10G_an_resolve(struct bnx2x *bp, 6786 struct bnx2x_phy *phy, 6787 struct link_vars *vars) 6788 { 6789 u16 val; 6790 bnx2x_cl45_read(bp, phy, 6791 MDIO_AN_DEVAD, 6792 MDIO_AN_REG_STATUS, &val); 6793 bnx2x_cl45_read(bp, phy, 6794 MDIO_AN_DEVAD, 6795 MDIO_AN_REG_STATUS, &val); 6796 if (val & (1<<5)) 6797 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; 6798 if ((val & (1<<0)) == 0) 6799 vars->link_status |= LINK_STATUS_PARALLEL_DETECTION_USED; 6800 } 6801 6802 /******************************************************************/ 6803 /* common BCM8073/BCM8727 PHY SECTION */ 6804 /******************************************************************/ 6805 static void bnx2x_8073_resolve_fc(struct bnx2x_phy *phy, 6806 struct link_params *params, 6807 struct link_vars *vars) 6808 { 6809 struct bnx2x *bp = params->bp; 6810 if (phy->req_line_speed == SPEED_10 || 6811 phy->req_line_speed == SPEED_100) { 6812 vars->flow_ctrl = phy->req_flow_ctrl; 6813 return; 6814 } 6815 6816 if (bnx2x_ext_phy_resolve_fc(phy, params, vars) && 6817 (vars->flow_ctrl == BNX2X_FLOW_CTRL_NONE)) { 6818 u16 pause_result; 6819 u16 ld_pause; /* local */ 6820 u16 lp_pause; /* link partner */ 6821 bnx2x_cl45_read(bp, phy, 6822 MDIO_AN_DEVAD, 6823 MDIO_AN_REG_CL37_FC_LD, &ld_pause); 6824 6825 bnx2x_cl45_read(bp, phy, 6826 MDIO_AN_DEVAD, 6827 MDIO_AN_REG_CL37_FC_LP, &lp_pause); 6828 pause_result = (ld_pause & 6829 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 5; 6830 pause_result |= (lp_pause & 6831 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 7; 6832 6833 bnx2x_pause_resolve(vars, pause_result); 6834 DP(NETIF_MSG_LINK, "Ext PHY CL37 pause result 0x%x\n", 6835 pause_result); 6836 } 6837 } 6838 static int bnx2x_8073_8727_external_rom_boot(struct bnx2x *bp, 6839 struct bnx2x_phy *phy, 6840 u8 port) 6841 { 6842 u32 count = 0; 6843 u16 fw_ver1, fw_msgout; 6844 int rc = 0; 6845 6846 /* Boot port from external ROM */ 6847 /* EDC grst */ 6848 bnx2x_cl45_write(bp, phy, 6849 MDIO_PMA_DEVAD, 6850 MDIO_PMA_REG_GEN_CTRL, 6851 0x0001); 6852 6853 /* Ucode reboot and rst */ 6854 bnx2x_cl45_write(bp, phy, 6855 MDIO_PMA_DEVAD, 6856 MDIO_PMA_REG_GEN_CTRL, 6857 0x008c); 6858 6859 bnx2x_cl45_write(bp, phy, 6860 MDIO_PMA_DEVAD, 6861 MDIO_PMA_REG_MISC_CTRL1, 0x0001); 6862 6863 /* Reset internal microprocessor */ 6864 bnx2x_cl45_write(bp, phy, 6865 MDIO_PMA_DEVAD, 6866 MDIO_PMA_REG_GEN_CTRL, 6867 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET); 6868 6869 /* Release srst bit */ 6870 bnx2x_cl45_write(bp, phy, 6871 MDIO_PMA_DEVAD, 6872 MDIO_PMA_REG_GEN_CTRL, 6873 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP); 6874 6875 /* Delay 100ms per the PHY specifications */ 6876 msleep(100); 6877 6878 /* 8073 sometimes taking longer to download */ 6879 do { 6880 count++; 6881 if (count > 300) { 6882 DP(NETIF_MSG_LINK, 6883 "bnx2x_8073_8727_external_rom_boot port %x:" 6884 "Download failed. fw version = 0x%x\n", 6885 port, fw_ver1); 6886 rc = -EINVAL; 6887 break; 6888 } 6889 6890 bnx2x_cl45_read(bp, phy, 6891 MDIO_PMA_DEVAD, 6892 MDIO_PMA_REG_ROM_VER1, &fw_ver1); 6893 bnx2x_cl45_read(bp, phy, 6894 MDIO_PMA_DEVAD, 6895 MDIO_PMA_REG_M8051_MSGOUT_REG, &fw_msgout); 6896 6897 usleep_range(1000, 2000); 6898 } while (fw_ver1 == 0 || fw_ver1 == 0x4321 || 6899 ((fw_msgout & 0xff) != 0x03 && (phy->type == 6900 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073))); 6901 6902 /* Clear ser_boot_ctl bit */ 6903 bnx2x_cl45_write(bp, phy, 6904 MDIO_PMA_DEVAD, 6905 MDIO_PMA_REG_MISC_CTRL1, 0x0000); 6906 bnx2x_save_bcm_spirom_ver(bp, phy, port); 6907 6908 DP(NETIF_MSG_LINK, 6909 "bnx2x_8073_8727_external_rom_boot port %x:" 6910 "Download complete. fw version = 0x%x\n", 6911 port, fw_ver1); 6912 6913 return rc; 6914 } 6915 6916 /******************************************************************/ 6917 /* BCM8073 PHY SECTION */ 6918 /******************************************************************/ 6919 static int bnx2x_8073_is_snr_needed(struct bnx2x *bp, struct bnx2x_phy *phy) 6920 { 6921 /* This is only required for 8073A1, version 102 only */ 6922 u16 val; 6923 6924 /* Read 8073 HW revision*/ 6925 bnx2x_cl45_read(bp, phy, 6926 MDIO_PMA_DEVAD, 6927 MDIO_PMA_REG_8073_CHIP_REV, &val); 6928 6929 if (val != 1) { 6930 /* No need to workaround in 8073 A1 */ 6931 return 0; 6932 } 6933 6934 bnx2x_cl45_read(bp, phy, 6935 MDIO_PMA_DEVAD, 6936 MDIO_PMA_REG_ROM_VER2, &val); 6937 6938 /* SNR should be applied only for version 0x102 */ 6939 if (val != 0x102) 6940 return 0; 6941 6942 return 1; 6943 } 6944 6945 static int bnx2x_8073_xaui_wa(struct bnx2x *bp, struct bnx2x_phy *phy) 6946 { 6947 u16 val, cnt, cnt1 ; 6948 6949 bnx2x_cl45_read(bp, phy, 6950 MDIO_PMA_DEVAD, 6951 MDIO_PMA_REG_8073_CHIP_REV, &val); 6952 6953 if (val > 0) { 6954 /* No need to workaround in 8073 A1 */ 6955 return 0; 6956 } 6957 /* XAUI workaround in 8073 A0: */ 6958 6959 /* After loading the boot ROM and restarting Autoneg, poll 6960 * Dev1, Reg $C820: 6961 */ 6962 6963 for (cnt = 0; cnt < 1000; cnt++) { 6964 bnx2x_cl45_read(bp, phy, 6965 MDIO_PMA_DEVAD, 6966 MDIO_PMA_REG_8073_SPEED_LINK_STATUS, 6967 &val); 6968 /* If bit [14] = 0 or bit [13] = 0, continue on with 6969 * system initialization (XAUI work-around not required, as 6970 * these bits indicate 2.5G or 1G link up). 6971 */ 6972 if (!(val & (1<<14)) || !(val & (1<<13))) { 6973 DP(NETIF_MSG_LINK, "XAUI work-around not required\n"); 6974 return 0; 6975 } else if (!(val & (1<<15))) { 6976 DP(NETIF_MSG_LINK, "bit 15 went off\n"); 6977 /* If bit 15 is 0, then poll Dev1, Reg $C841 until it's 6978 * MSB (bit15) goes to 1 (indicating that the XAUI 6979 * workaround has completed), then continue on with 6980 * system initialization. 6981 */ 6982 for (cnt1 = 0; cnt1 < 1000; cnt1++) { 6983 bnx2x_cl45_read(bp, phy, 6984 MDIO_PMA_DEVAD, 6985 MDIO_PMA_REG_8073_XAUI_WA, &val); 6986 if (val & (1<<15)) { 6987 DP(NETIF_MSG_LINK, 6988 "XAUI workaround has completed\n"); 6989 return 0; 6990 } 6991 usleep_range(3000, 6000); 6992 } 6993 break; 6994 } 6995 usleep_range(3000, 6000); 6996 } 6997 DP(NETIF_MSG_LINK, "Warning: XAUI work-around timeout !!!\n"); 6998 return -EINVAL; 6999 } 7000 7001 static void bnx2x_807x_force_10G(struct bnx2x *bp, struct bnx2x_phy *phy) 7002 { 7003 /* Force KR or KX */ 7004 bnx2x_cl45_write(bp, phy, 7005 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040); 7006 bnx2x_cl45_write(bp, phy, 7007 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0x000b); 7008 bnx2x_cl45_write(bp, phy, 7009 MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0000); 7010 bnx2x_cl45_write(bp, phy, 7011 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000); 7012 } 7013 7014 static void bnx2x_8073_set_pause_cl37(struct link_params *params, 7015 struct bnx2x_phy *phy, 7016 struct link_vars *vars) 7017 { 7018 u16 cl37_val; 7019 struct bnx2x *bp = params->bp; 7020 bnx2x_cl45_read(bp, phy, 7021 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &cl37_val); 7022 7023 cl37_val &= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; 7024 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */ 7025 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); 7026 if ((vars->ieee_fc & 7027 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) == 7028 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) { 7029 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC; 7030 } 7031 if ((vars->ieee_fc & 7032 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) == 7033 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) { 7034 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC; 7035 } 7036 if ((vars->ieee_fc & 7037 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) == 7038 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) { 7039 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; 7040 } 7041 DP(NETIF_MSG_LINK, 7042 "Ext phy AN advertize cl37 0x%x\n", cl37_val); 7043 7044 bnx2x_cl45_write(bp, phy, 7045 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, cl37_val); 7046 msleep(500); 7047 } 7048 7049 static void bnx2x_8073_specific_func(struct bnx2x_phy *phy, 7050 struct link_params *params, 7051 u32 action) 7052 { 7053 struct bnx2x *bp = params->bp; 7054 switch (action) { 7055 case PHY_INIT: 7056 /* Enable LASI */ 7057 bnx2x_cl45_write(bp, phy, 7058 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, (1<<2)); 7059 bnx2x_cl45_write(bp, phy, 7060 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0004); 7061 break; 7062 } 7063 } 7064 7065 static int bnx2x_8073_config_init(struct bnx2x_phy *phy, 7066 struct link_params *params, 7067 struct link_vars *vars) 7068 { 7069 struct bnx2x *bp = params->bp; 7070 u16 val = 0, tmp1; 7071 u8 gpio_port; 7072 DP(NETIF_MSG_LINK, "Init 8073\n"); 7073 7074 if (CHIP_IS_E2(bp)) 7075 gpio_port = BP_PATH(bp); 7076 else 7077 gpio_port = params->port; 7078 /* Restore normal power mode*/ 7079 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 7080 MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port); 7081 7082 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, 7083 MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port); 7084 7085 bnx2x_8073_specific_func(phy, params, PHY_INIT); 7086 bnx2x_8073_set_pause_cl37(params, phy, vars); 7087 7088 bnx2x_cl45_read(bp, phy, 7089 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1); 7090 7091 bnx2x_cl45_read(bp, phy, 7092 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1); 7093 7094 DP(NETIF_MSG_LINK, "Before rom RX_ALARM(port1): 0x%x\n", tmp1); 7095 7096 /* Swap polarity if required - Must be done only in non-1G mode */ 7097 if (params->lane_config & PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) { 7098 /* Configure the 8073 to swap _P and _N of the KR lines */ 7099 DP(NETIF_MSG_LINK, "Swapping polarity for the 8073\n"); 7100 /* 10G Rx/Tx and 1G Tx signal polarity swap */ 7101 bnx2x_cl45_read(bp, phy, 7102 MDIO_PMA_DEVAD, 7103 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL, &val); 7104 bnx2x_cl45_write(bp, phy, 7105 MDIO_PMA_DEVAD, 7106 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL, 7107 (val | (3<<9))); 7108 } 7109 7110 7111 /* Enable CL37 BAM */ 7112 if (REG_RD(bp, params->shmem_base + 7113 offsetof(struct shmem_region, dev_info. 7114 port_hw_config[params->port].default_cfg)) & 7115 PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) { 7116 7117 bnx2x_cl45_read(bp, phy, 7118 MDIO_AN_DEVAD, 7119 MDIO_AN_REG_8073_BAM, &val); 7120 bnx2x_cl45_write(bp, phy, 7121 MDIO_AN_DEVAD, 7122 MDIO_AN_REG_8073_BAM, val | 1); 7123 DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n"); 7124 } 7125 if (params->loopback_mode == LOOPBACK_EXT) { 7126 bnx2x_807x_force_10G(bp, phy); 7127 DP(NETIF_MSG_LINK, "Forced speed 10G on 807X\n"); 7128 return 0; 7129 } else { 7130 bnx2x_cl45_write(bp, phy, 7131 MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0002); 7132 } 7133 if (phy->req_line_speed != SPEED_AUTO_NEG) { 7134 if (phy->req_line_speed == SPEED_10000) { 7135 val = (1<<7); 7136 } else if (phy->req_line_speed == SPEED_2500) { 7137 val = (1<<5); 7138 /* Note that 2.5G works only when used with 1G 7139 * advertisement 7140 */ 7141 } else 7142 val = (1<<5); 7143 } else { 7144 val = 0; 7145 if (phy->speed_cap_mask & 7146 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) 7147 val |= (1<<7); 7148 7149 /* Note that 2.5G works only when used with 1G advertisement */ 7150 if (phy->speed_cap_mask & 7151 (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G | 7152 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) 7153 val |= (1<<5); 7154 DP(NETIF_MSG_LINK, "807x autoneg val = 0x%x\n", val); 7155 } 7156 7157 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val); 7158 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, &tmp1); 7159 7160 if (((phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) && 7161 (phy->req_line_speed == SPEED_AUTO_NEG)) || 7162 (phy->req_line_speed == SPEED_2500)) { 7163 u16 phy_ver; 7164 /* Allow 2.5G for A1 and above */ 7165 bnx2x_cl45_read(bp, phy, 7166 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV, 7167 &phy_ver); 7168 DP(NETIF_MSG_LINK, "Add 2.5G\n"); 7169 if (phy_ver > 0) 7170 tmp1 |= 1; 7171 else 7172 tmp1 &= 0xfffe; 7173 } else { 7174 DP(NETIF_MSG_LINK, "Disable 2.5G\n"); 7175 tmp1 &= 0xfffe; 7176 } 7177 7178 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, tmp1); 7179 /* Add support for CL37 (passive mode) II */ 7180 7181 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &tmp1); 7182 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, 7183 (tmp1 | ((phy->req_duplex == DUPLEX_FULL) ? 7184 0x20 : 0x40))); 7185 7186 /* Add support for CL37 (passive mode) III */ 7187 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000); 7188 7189 /* The SNR will improve about 2db by changing BW and FEE main 7190 * tap. Rest commands are executed after link is up 7191 * Change FFE main cursor to 5 in EDC register 7192 */ 7193 if (bnx2x_8073_is_snr_needed(bp, phy)) 7194 bnx2x_cl45_write(bp, phy, 7195 MDIO_PMA_DEVAD, MDIO_PMA_REG_EDC_FFE_MAIN, 7196 0xFB0C); 7197 7198 /* Enable FEC (Forware Error Correction) Request in the AN */ 7199 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, &tmp1); 7200 tmp1 |= (1<<15); 7201 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, tmp1); 7202 7203 bnx2x_ext_phy_set_pause(params, phy, vars); 7204 7205 /* Restart autoneg */ 7206 msleep(500); 7207 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200); 7208 DP(NETIF_MSG_LINK, "807x Autoneg Restart: Advertise 1G=%x, 10G=%x\n", 7209 ((val & (1<<5)) > 0), ((val & (1<<7)) > 0)); 7210 return 0; 7211 } 7212 7213 static u8 bnx2x_8073_read_status(struct bnx2x_phy *phy, 7214 struct link_params *params, 7215 struct link_vars *vars) 7216 { 7217 struct bnx2x *bp = params->bp; 7218 u8 link_up = 0; 7219 u16 val1, val2; 7220 u16 link_status = 0; 7221 u16 an1000_status = 0; 7222 7223 bnx2x_cl45_read(bp, phy, 7224 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1); 7225 7226 DP(NETIF_MSG_LINK, "8703 LASI status 0x%x\n", val1); 7227 7228 /* Clear the interrupt LASI status register */ 7229 bnx2x_cl45_read(bp, phy, 7230 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2); 7231 bnx2x_cl45_read(bp, phy, 7232 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val1); 7233 DP(NETIF_MSG_LINK, "807x PCS status 0x%x->0x%x\n", val2, val1); 7234 /* Clear MSG-OUT */ 7235 bnx2x_cl45_read(bp, phy, 7236 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1); 7237 7238 /* Check the LASI */ 7239 bnx2x_cl45_read(bp, phy, 7240 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2); 7241 7242 DP(NETIF_MSG_LINK, "KR 0x9003 0x%x\n", val2); 7243 7244 /* Check the link status */ 7245 bnx2x_cl45_read(bp, phy, 7246 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2); 7247 DP(NETIF_MSG_LINK, "KR PCS status 0x%x\n", val2); 7248 7249 bnx2x_cl45_read(bp, phy, 7250 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2); 7251 bnx2x_cl45_read(bp, phy, 7252 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1); 7253 link_up = ((val1 & 4) == 4); 7254 DP(NETIF_MSG_LINK, "PMA_REG_STATUS=0x%x\n", val1); 7255 7256 if (link_up && 7257 ((phy->req_line_speed != SPEED_10000))) { 7258 if (bnx2x_8073_xaui_wa(bp, phy) != 0) 7259 return 0; 7260 } 7261 bnx2x_cl45_read(bp, phy, 7262 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status); 7263 bnx2x_cl45_read(bp, phy, 7264 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status); 7265 7266 /* Check the link status on 1.1.2 */ 7267 bnx2x_cl45_read(bp, phy, 7268 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2); 7269 bnx2x_cl45_read(bp, phy, 7270 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1); 7271 DP(NETIF_MSG_LINK, "KR PMA status 0x%x->0x%x," 7272 "an_link_status=0x%x\n", val2, val1, an1000_status); 7273 7274 link_up = (((val1 & 4) == 4) || (an1000_status & (1<<1))); 7275 if (link_up && bnx2x_8073_is_snr_needed(bp, phy)) { 7276 /* The SNR will improve about 2dbby changing the BW and FEE main 7277 * tap. The 1st write to change FFE main tap is set before 7278 * restart AN. Change PLL Bandwidth in EDC register 7279 */ 7280 bnx2x_cl45_write(bp, phy, 7281 MDIO_PMA_DEVAD, MDIO_PMA_REG_PLL_BANDWIDTH, 7282 0x26BC); 7283 7284 /* Change CDR Bandwidth in EDC register */ 7285 bnx2x_cl45_write(bp, phy, 7286 MDIO_PMA_DEVAD, MDIO_PMA_REG_CDR_BANDWIDTH, 7287 0x0333); 7288 } 7289 bnx2x_cl45_read(bp, phy, 7290 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_SPEED_LINK_STATUS, 7291 &link_status); 7292 7293 /* Bits 0..2 --> speed detected, bits 13..15--> link is down */ 7294 if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) { 7295 link_up = 1; 7296 vars->line_speed = SPEED_10000; 7297 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n", 7298 params->port); 7299 } else if ((link_status & (1<<1)) && (!(link_status & (1<<14)))) { 7300 link_up = 1; 7301 vars->line_speed = SPEED_2500; 7302 DP(NETIF_MSG_LINK, "port %x: External link up in 2.5G\n", 7303 params->port); 7304 } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) { 7305 link_up = 1; 7306 vars->line_speed = SPEED_1000; 7307 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n", 7308 params->port); 7309 } else { 7310 link_up = 0; 7311 DP(NETIF_MSG_LINK, "port %x: External link is down\n", 7312 params->port); 7313 } 7314 7315 if (link_up) { 7316 /* Swap polarity if required */ 7317 if (params->lane_config & 7318 PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) { 7319 /* Configure the 8073 to swap P and N of the KR lines */ 7320 bnx2x_cl45_read(bp, phy, 7321 MDIO_XS_DEVAD, 7322 MDIO_XS_REG_8073_RX_CTRL_PCIE, &val1); 7323 /* Set bit 3 to invert Rx in 1G mode and clear this bit 7324 * when it`s in 10G mode. 7325 */ 7326 if (vars->line_speed == SPEED_1000) { 7327 DP(NETIF_MSG_LINK, "Swapping 1G polarity for" 7328 "the 8073\n"); 7329 val1 |= (1<<3); 7330 } else 7331 val1 &= ~(1<<3); 7332 7333 bnx2x_cl45_write(bp, phy, 7334 MDIO_XS_DEVAD, 7335 MDIO_XS_REG_8073_RX_CTRL_PCIE, 7336 val1); 7337 } 7338 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars); 7339 bnx2x_8073_resolve_fc(phy, params, vars); 7340 vars->duplex = DUPLEX_FULL; 7341 } 7342 7343 if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) { 7344 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, 7345 MDIO_AN_REG_LP_AUTO_NEG2, &val1); 7346 7347 if (val1 & (1<<5)) 7348 vars->link_status |= 7349 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; 7350 if (val1 & (1<<7)) 7351 vars->link_status |= 7352 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; 7353 } 7354 7355 return link_up; 7356 } 7357 7358 static void bnx2x_8073_link_reset(struct bnx2x_phy *phy, 7359 struct link_params *params) 7360 { 7361 struct bnx2x *bp = params->bp; 7362 u8 gpio_port; 7363 if (CHIP_IS_E2(bp)) 7364 gpio_port = BP_PATH(bp); 7365 else 7366 gpio_port = params->port; 7367 DP(NETIF_MSG_LINK, "Setting 8073 port %d into low power mode\n", 7368 gpio_port); 7369 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 7370 MISC_REGISTERS_GPIO_OUTPUT_LOW, 7371 gpio_port); 7372 } 7373 7374 /******************************************************************/ 7375 /* BCM8705 PHY SECTION */ 7376 /******************************************************************/ 7377 static int bnx2x_8705_config_init(struct bnx2x_phy *phy, 7378 struct link_params *params, 7379 struct link_vars *vars) 7380 { 7381 struct bnx2x *bp = params->bp; 7382 DP(NETIF_MSG_LINK, "init 8705\n"); 7383 /* Restore normal power mode*/ 7384 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 7385 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); 7386 /* HW reset */ 7387 bnx2x_ext_phy_hw_reset(bp, params->port); 7388 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040); 7389 bnx2x_wait_reset_complete(bp, phy, params); 7390 7391 bnx2x_cl45_write(bp, phy, 7392 MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL, 0x8288); 7393 bnx2x_cl45_write(bp, phy, 7394 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 0x7fbf); 7395 bnx2x_cl45_write(bp, phy, 7396 MDIO_PMA_DEVAD, MDIO_PMA_REG_CMU_PLL_BYPASS, 0x0100); 7397 bnx2x_cl45_write(bp, phy, 7398 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_CNTL, 0x1); 7399 /* BCM8705 doesn't have microcode, hence the 0 */ 7400 bnx2x_save_spirom_version(bp, params->port, params->shmem_base, 0); 7401 return 0; 7402 } 7403 7404 static u8 bnx2x_8705_read_status(struct bnx2x_phy *phy, 7405 struct link_params *params, 7406 struct link_vars *vars) 7407 { 7408 u8 link_up = 0; 7409 u16 val1, rx_sd; 7410 struct bnx2x *bp = params->bp; 7411 DP(NETIF_MSG_LINK, "read status 8705\n"); 7412 bnx2x_cl45_read(bp, phy, 7413 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1); 7414 DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1); 7415 7416 bnx2x_cl45_read(bp, phy, 7417 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1); 7418 DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1); 7419 7420 bnx2x_cl45_read(bp, phy, 7421 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd); 7422 7423 bnx2x_cl45_read(bp, phy, 7424 MDIO_PMA_DEVAD, 0xc809, &val1); 7425 bnx2x_cl45_read(bp, phy, 7426 MDIO_PMA_DEVAD, 0xc809, &val1); 7427 7428 DP(NETIF_MSG_LINK, "8705 1.c809 val=0x%x\n", val1); 7429 link_up = ((rx_sd & 0x1) && (val1 & (1<<9)) && ((val1 & (1<<8)) == 0)); 7430 if (link_up) { 7431 vars->line_speed = SPEED_10000; 7432 bnx2x_ext_phy_resolve_fc(phy, params, vars); 7433 } 7434 return link_up; 7435 } 7436 7437 /******************************************************************/ 7438 /* SFP+ module Section */ 7439 /******************************************************************/ 7440 static void bnx2x_set_disable_pmd_transmit(struct link_params *params, 7441 struct bnx2x_phy *phy, 7442 u8 pmd_dis) 7443 { 7444 struct bnx2x *bp = params->bp; 7445 /* Disable transmitter only for bootcodes which can enable it afterwards 7446 * (for D3 link) 7447 */ 7448 if (pmd_dis) { 7449 if (params->feature_config_flags & 7450 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED) 7451 DP(NETIF_MSG_LINK, "Disabling PMD transmitter\n"); 7452 else { 7453 DP(NETIF_MSG_LINK, "NOT disabling PMD transmitter\n"); 7454 return; 7455 } 7456 } else 7457 DP(NETIF_MSG_LINK, "Enabling PMD transmitter\n"); 7458 bnx2x_cl45_write(bp, phy, 7459 MDIO_PMA_DEVAD, 7460 MDIO_PMA_REG_TX_DISABLE, pmd_dis); 7461 } 7462 7463 static u8 bnx2x_get_gpio_port(struct link_params *params) 7464 { 7465 u8 gpio_port; 7466 u32 swap_val, swap_override; 7467 struct bnx2x *bp = params->bp; 7468 if (CHIP_IS_E2(bp)) 7469 gpio_port = BP_PATH(bp); 7470 else 7471 gpio_port = params->port; 7472 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); 7473 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); 7474 return gpio_port ^ (swap_val && swap_override); 7475 } 7476 7477 static void bnx2x_sfp_e1e2_set_transmitter(struct link_params *params, 7478 struct bnx2x_phy *phy, 7479 u8 tx_en) 7480 { 7481 u16 val; 7482 u8 port = params->port; 7483 struct bnx2x *bp = params->bp; 7484 u32 tx_en_mode; 7485 7486 /* Disable/Enable transmitter ( TX laser of the SFP+ module.)*/ 7487 tx_en_mode = REG_RD(bp, params->shmem_base + 7488 offsetof(struct shmem_region, 7489 dev_info.port_hw_config[port].sfp_ctrl)) & 7490 PORT_HW_CFG_TX_LASER_MASK; 7491 DP(NETIF_MSG_LINK, "Setting transmitter tx_en=%x for port %x " 7492 "mode = %x\n", tx_en, port, tx_en_mode); 7493 switch (tx_en_mode) { 7494 case PORT_HW_CFG_TX_LASER_MDIO: 7495 7496 bnx2x_cl45_read(bp, phy, 7497 MDIO_PMA_DEVAD, 7498 MDIO_PMA_REG_PHY_IDENTIFIER, 7499 &val); 7500 7501 if (tx_en) 7502 val &= ~(1<<15); 7503 else 7504 val |= (1<<15); 7505 7506 bnx2x_cl45_write(bp, phy, 7507 MDIO_PMA_DEVAD, 7508 MDIO_PMA_REG_PHY_IDENTIFIER, 7509 val); 7510 break; 7511 case PORT_HW_CFG_TX_LASER_GPIO0: 7512 case PORT_HW_CFG_TX_LASER_GPIO1: 7513 case PORT_HW_CFG_TX_LASER_GPIO2: 7514 case PORT_HW_CFG_TX_LASER_GPIO3: 7515 { 7516 u16 gpio_pin; 7517 u8 gpio_port, gpio_mode; 7518 if (tx_en) 7519 gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_HIGH; 7520 else 7521 gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_LOW; 7522 7523 gpio_pin = tx_en_mode - PORT_HW_CFG_TX_LASER_GPIO0; 7524 gpio_port = bnx2x_get_gpio_port(params); 7525 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port); 7526 break; 7527 } 7528 default: 7529 DP(NETIF_MSG_LINK, "Invalid TX_LASER_MDIO 0x%x\n", tx_en_mode); 7530 break; 7531 } 7532 } 7533 7534 static void bnx2x_sfp_set_transmitter(struct link_params *params, 7535 struct bnx2x_phy *phy, 7536 u8 tx_en) 7537 { 7538 struct bnx2x *bp = params->bp; 7539 DP(NETIF_MSG_LINK, "Setting SFP+ transmitter to %d\n", tx_en); 7540 if (CHIP_IS_E3(bp)) 7541 bnx2x_sfp_e3_set_transmitter(params, phy, tx_en); 7542 else 7543 bnx2x_sfp_e1e2_set_transmitter(params, phy, tx_en); 7544 } 7545 7546 static int bnx2x_8726_read_sfp_module_eeprom(struct bnx2x_phy *phy, 7547 struct link_params *params, 7548 u16 addr, u8 byte_cnt, u8 *o_buf) 7549 { 7550 struct bnx2x *bp = params->bp; 7551 u16 val = 0; 7552 u16 i; 7553 if (byte_cnt > SFP_EEPROM_PAGE_SIZE) { 7554 DP(NETIF_MSG_LINK, 7555 "Reading from eeprom is limited to 0xf\n"); 7556 return -EINVAL; 7557 } 7558 /* Set the read command byte count */ 7559 bnx2x_cl45_write(bp, phy, 7560 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT, 7561 (byte_cnt | 0xa000)); 7562 7563 /* Set the read command address */ 7564 bnx2x_cl45_write(bp, phy, 7565 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR, 7566 addr); 7567 7568 /* Activate read command */ 7569 bnx2x_cl45_write(bp, phy, 7570 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, 7571 0x2c0f); 7572 7573 /* Wait up to 500us for command complete status */ 7574 for (i = 0; i < 100; i++) { 7575 bnx2x_cl45_read(bp, phy, 7576 MDIO_PMA_DEVAD, 7577 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); 7578 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == 7579 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) 7580 break; 7581 udelay(5); 7582 } 7583 7584 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) != 7585 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) { 7586 DP(NETIF_MSG_LINK, 7587 "Got bad status 0x%x when reading from SFP+ EEPROM\n", 7588 (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK)); 7589 return -EINVAL; 7590 } 7591 7592 /* Read the buffer */ 7593 for (i = 0; i < byte_cnt; i++) { 7594 bnx2x_cl45_read(bp, phy, 7595 MDIO_PMA_DEVAD, 7596 MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i, &val); 7597 o_buf[i] = (u8)(val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK); 7598 } 7599 7600 for (i = 0; i < 100; i++) { 7601 bnx2x_cl45_read(bp, phy, 7602 MDIO_PMA_DEVAD, 7603 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); 7604 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == 7605 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE) 7606 return 0; 7607 usleep_range(1000, 2000); 7608 } 7609 return -EINVAL; 7610 } 7611 7612 static void bnx2x_warpcore_power_module(struct link_params *params, 7613 struct bnx2x_phy *phy, 7614 u8 power) 7615 { 7616 u32 pin_cfg; 7617 struct bnx2x *bp = params->bp; 7618 7619 pin_cfg = (REG_RD(bp, params->shmem_base + 7620 offsetof(struct shmem_region, 7621 dev_info.port_hw_config[params->port].e3_sfp_ctrl)) & 7622 PORT_HW_CFG_E3_PWR_DIS_MASK) >> 7623 PORT_HW_CFG_E3_PWR_DIS_SHIFT; 7624 7625 if (pin_cfg == PIN_CFG_NA) 7626 return; 7627 DP(NETIF_MSG_LINK, "Setting SFP+ module power to %d using pin cfg %d\n", 7628 power, pin_cfg); 7629 /* Low ==> corresponding SFP+ module is powered 7630 * high ==> the SFP+ module is powered down 7631 */ 7632 bnx2x_set_cfg_pin(bp, pin_cfg, power ^ 1); 7633 } 7634 static int bnx2x_warpcore_read_sfp_module_eeprom(struct bnx2x_phy *phy, 7635 struct link_params *params, 7636 u16 addr, u8 byte_cnt, 7637 u8 *o_buf, u8 is_init) 7638 { 7639 int rc = 0; 7640 u8 i, j = 0, cnt = 0; 7641 u32 data_array[4]; 7642 u16 addr32; 7643 struct bnx2x *bp = params->bp; 7644 7645 if (byte_cnt > SFP_EEPROM_PAGE_SIZE) { 7646 DP(NETIF_MSG_LINK, 7647 "Reading from eeprom is limited to 16 bytes\n"); 7648 return -EINVAL; 7649 } 7650 7651 /* 4 byte aligned address */ 7652 addr32 = addr & (~0x3); 7653 do { 7654 if ((!is_init) && (cnt == I2C_WA_PWR_ITER)) { 7655 bnx2x_warpcore_power_module(params, phy, 0); 7656 /* Note that 100us are not enough here */ 7657 usleep_range(1000, 2000); 7658 bnx2x_warpcore_power_module(params, phy, 1); 7659 } 7660 rc = bnx2x_bsc_read(params, phy, 0xa0, addr32, 0, byte_cnt, 7661 data_array); 7662 } while ((rc != 0) && (++cnt < I2C_WA_RETRY_CNT)); 7663 7664 if (rc == 0) { 7665 for (i = (addr - addr32); i < byte_cnt + (addr - addr32); i++) { 7666 o_buf[j] = *((u8 *)data_array + i); 7667 j++; 7668 } 7669 } 7670 7671 return rc; 7672 } 7673 7674 static int bnx2x_8727_read_sfp_module_eeprom(struct bnx2x_phy *phy, 7675 struct link_params *params, 7676 u16 addr, u8 byte_cnt, u8 *o_buf) 7677 { 7678 struct bnx2x *bp = params->bp; 7679 u16 val, i; 7680 7681 if (byte_cnt > SFP_EEPROM_PAGE_SIZE) { 7682 DP(NETIF_MSG_LINK, 7683 "Reading from eeprom is limited to 0xf\n"); 7684 return -EINVAL; 7685 } 7686 7687 /* Need to read from 1.8000 to clear it */ 7688 bnx2x_cl45_read(bp, phy, 7689 MDIO_PMA_DEVAD, 7690 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, 7691 &val); 7692 7693 /* Set the read command byte count */ 7694 bnx2x_cl45_write(bp, phy, 7695 MDIO_PMA_DEVAD, 7696 MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT, 7697 ((byte_cnt < 2) ? 2 : byte_cnt)); 7698 7699 /* Set the read command address */ 7700 bnx2x_cl45_write(bp, phy, 7701 MDIO_PMA_DEVAD, 7702 MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR, 7703 addr); 7704 /* Set the destination address */ 7705 bnx2x_cl45_write(bp, phy, 7706 MDIO_PMA_DEVAD, 7707 0x8004, 7708 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF); 7709 7710 /* Activate read command */ 7711 bnx2x_cl45_write(bp, phy, 7712 MDIO_PMA_DEVAD, 7713 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, 7714 0x8002); 7715 /* Wait appropriate time for two-wire command to finish before 7716 * polling the status register 7717 */ 7718 usleep_range(1000, 2000); 7719 7720 /* Wait up to 500us for command complete status */ 7721 for (i = 0; i < 100; i++) { 7722 bnx2x_cl45_read(bp, phy, 7723 MDIO_PMA_DEVAD, 7724 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); 7725 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == 7726 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) 7727 break; 7728 udelay(5); 7729 } 7730 7731 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) != 7732 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) { 7733 DP(NETIF_MSG_LINK, 7734 "Got bad status 0x%x when reading from SFP+ EEPROM\n", 7735 (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK)); 7736 return -EFAULT; 7737 } 7738 7739 /* Read the buffer */ 7740 for (i = 0; i < byte_cnt; i++) { 7741 bnx2x_cl45_read(bp, phy, 7742 MDIO_PMA_DEVAD, 7743 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF + i, &val); 7744 o_buf[i] = (u8)(val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK); 7745 } 7746 7747 for (i = 0; i < 100; i++) { 7748 bnx2x_cl45_read(bp, phy, 7749 MDIO_PMA_DEVAD, 7750 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); 7751 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == 7752 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE) 7753 return 0; 7754 usleep_range(1000, 2000); 7755 } 7756 7757 return -EINVAL; 7758 } 7759 7760 int bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy, 7761 struct link_params *params, u16 addr, 7762 u8 byte_cnt, u8 *o_buf) 7763 { 7764 int rc = -EOPNOTSUPP; 7765 switch (phy->type) { 7766 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: 7767 rc = bnx2x_8726_read_sfp_module_eeprom(phy, params, addr, 7768 byte_cnt, o_buf); 7769 break; 7770 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: 7771 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722: 7772 rc = bnx2x_8727_read_sfp_module_eeprom(phy, params, addr, 7773 byte_cnt, o_buf); 7774 break; 7775 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT: 7776 rc = bnx2x_warpcore_read_sfp_module_eeprom(phy, params, addr, 7777 byte_cnt, o_buf, 0); 7778 break; 7779 } 7780 return rc; 7781 } 7782 7783 static int bnx2x_get_edc_mode(struct bnx2x_phy *phy, 7784 struct link_params *params, 7785 u16 *edc_mode) 7786 { 7787 struct bnx2x *bp = params->bp; 7788 u32 sync_offset = 0, phy_idx, media_types; 7789 u8 val[2], check_limiting_mode = 0; 7790 *edc_mode = EDC_MODE_LIMITING; 7791 7792 phy->media_type = ETH_PHY_UNSPECIFIED; 7793 /* First check for copper cable */ 7794 if (bnx2x_read_sfp_module_eeprom(phy, 7795 params, 7796 SFP_EEPROM_CON_TYPE_ADDR, 7797 2, 7798 (u8 *)val) != 0) { 7799 DP(NETIF_MSG_LINK, "Failed to read from SFP+ module EEPROM\n"); 7800 return -EINVAL; 7801 } 7802 7803 switch (val[0]) { 7804 case SFP_EEPROM_CON_TYPE_VAL_COPPER: 7805 { 7806 u8 copper_module_type; 7807 phy->media_type = ETH_PHY_DA_TWINAX; 7808 /* Check if its active cable (includes SFP+ module) 7809 * of passive cable 7810 */ 7811 if (bnx2x_read_sfp_module_eeprom(phy, 7812 params, 7813 SFP_EEPROM_FC_TX_TECH_ADDR, 7814 1, 7815 &copper_module_type) != 0) { 7816 DP(NETIF_MSG_LINK, 7817 "Failed to read copper-cable-type" 7818 " from SFP+ EEPROM\n"); 7819 return -EINVAL; 7820 } 7821 7822 if (copper_module_type & 7823 SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) { 7824 DP(NETIF_MSG_LINK, "Active Copper cable detected\n"); 7825 check_limiting_mode = 1; 7826 } else if (copper_module_type & 7827 SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE) { 7828 DP(NETIF_MSG_LINK, 7829 "Passive Copper cable detected\n"); 7830 *edc_mode = 7831 EDC_MODE_PASSIVE_DAC; 7832 } else { 7833 DP(NETIF_MSG_LINK, 7834 "Unknown copper-cable-type 0x%x !!!\n", 7835 copper_module_type); 7836 return -EINVAL; 7837 } 7838 break; 7839 } 7840 case SFP_EEPROM_CON_TYPE_VAL_LC: 7841 check_limiting_mode = 1; 7842 if ((val[1] & (SFP_EEPROM_COMP_CODE_SR_MASK | 7843 SFP_EEPROM_COMP_CODE_LR_MASK | 7844 SFP_EEPROM_COMP_CODE_LRM_MASK)) == 0) { 7845 DP(NETIF_MSG_LINK, "1G Optic module detected\n"); 7846 phy->media_type = ETH_PHY_SFP_1G_FIBER; 7847 phy->req_line_speed = SPEED_1000; 7848 } else { 7849 int idx, cfg_idx = 0; 7850 DP(NETIF_MSG_LINK, "10G Optic module detected\n"); 7851 for (idx = INT_PHY; idx < MAX_PHYS; idx++) { 7852 if (params->phy[idx].type == phy->type) { 7853 cfg_idx = LINK_CONFIG_IDX(idx); 7854 break; 7855 } 7856 } 7857 phy->media_type = ETH_PHY_SFPP_10G_FIBER; 7858 phy->req_line_speed = params->req_line_speed[cfg_idx]; 7859 } 7860 break; 7861 default: 7862 DP(NETIF_MSG_LINK, "Unable to determine module type 0x%x !!!\n", 7863 val[0]); 7864 return -EINVAL; 7865 } 7866 sync_offset = params->shmem_base + 7867 offsetof(struct shmem_region, 7868 dev_info.port_hw_config[params->port].media_type); 7869 media_types = REG_RD(bp, sync_offset); 7870 /* Update media type for non-PMF sync */ 7871 for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) { 7872 if (&(params->phy[phy_idx]) == phy) { 7873 media_types &= ~(PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK << 7874 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx)); 7875 media_types |= ((phy->media_type & 7876 PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) << 7877 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx)); 7878 break; 7879 } 7880 } 7881 REG_WR(bp, sync_offset, media_types); 7882 if (check_limiting_mode) { 7883 u8 options[SFP_EEPROM_OPTIONS_SIZE]; 7884 if (bnx2x_read_sfp_module_eeprom(phy, 7885 params, 7886 SFP_EEPROM_OPTIONS_ADDR, 7887 SFP_EEPROM_OPTIONS_SIZE, 7888 options) != 0) { 7889 DP(NETIF_MSG_LINK, 7890 "Failed to read Option field from module EEPROM\n"); 7891 return -EINVAL; 7892 } 7893 if ((options[0] & SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK)) 7894 *edc_mode = EDC_MODE_LINEAR; 7895 else 7896 *edc_mode = EDC_MODE_LIMITING; 7897 } 7898 DP(NETIF_MSG_LINK, "EDC mode is set to 0x%x\n", *edc_mode); 7899 return 0; 7900 } 7901 /* This function read the relevant field from the module (SFP+), and verify it 7902 * is compliant with this board 7903 */ 7904 static int bnx2x_verify_sfp_module(struct bnx2x_phy *phy, 7905 struct link_params *params) 7906 { 7907 struct bnx2x *bp = params->bp; 7908 u32 val, cmd; 7909 u32 fw_resp, fw_cmd_param; 7910 char vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE+1]; 7911 char vendor_pn[SFP_EEPROM_PART_NO_SIZE+1]; 7912 phy->flags &= ~FLAGS_SFP_NOT_APPROVED; 7913 val = REG_RD(bp, params->shmem_base + 7914 offsetof(struct shmem_region, dev_info. 7915 port_feature_config[params->port].config)); 7916 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == 7917 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT) { 7918 DP(NETIF_MSG_LINK, "NOT enforcing module verification\n"); 7919 return 0; 7920 } 7921 7922 if (params->feature_config_flags & 7923 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY) { 7924 /* Use specific phy request */ 7925 cmd = DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL; 7926 } else if (params->feature_config_flags & 7927 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY) { 7928 /* Use first phy request only in case of non-dual media*/ 7929 if (DUAL_MEDIA(params)) { 7930 DP(NETIF_MSG_LINK, 7931 "FW does not support OPT MDL verification\n"); 7932 return -EINVAL; 7933 } 7934 cmd = DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL; 7935 } else { 7936 /* No support in OPT MDL detection */ 7937 DP(NETIF_MSG_LINK, 7938 "FW does not support OPT MDL verification\n"); 7939 return -EINVAL; 7940 } 7941 7942 fw_cmd_param = FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl); 7943 fw_resp = bnx2x_fw_command(bp, cmd, fw_cmd_param); 7944 if (fw_resp == FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS) { 7945 DP(NETIF_MSG_LINK, "Approved module\n"); 7946 return 0; 7947 } 7948 7949 /* Format the warning message */ 7950 if (bnx2x_read_sfp_module_eeprom(phy, 7951 params, 7952 SFP_EEPROM_VENDOR_NAME_ADDR, 7953 SFP_EEPROM_VENDOR_NAME_SIZE, 7954 (u8 *)vendor_name)) 7955 vendor_name[0] = '\0'; 7956 else 7957 vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE] = '\0'; 7958 if (bnx2x_read_sfp_module_eeprom(phy, 7959 params, 7960 SFP_EEPROM_PART_NO_ADDR, 7961 SFP_EEPROM_PART_NO_SIZE, 7962 (u8 *)vendor_pn)) 7963 vendor_pn[0] = '\0'; 7964 else 7965 vendor_pn[SFP_EEPROM_PART_NO_SIZE] = '\0'; 7966 7967 netdev_err(bp->dev, "Warning: Unqualified SFP+ module detected," 7968 " Port %d from %s part number %s\n", 7969 params->port, vendor_name, vendor_pn); 7970 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) != 7971 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG) 7972 phy->flags |= FLAGS_SFP_NOT_APPROVED; 7973 return -EINVAL; 7974 } 7975 7976 static int bnx2x_wait_for_sfp_module_initialized(struct bnx2x_phy *phy, 7977 struct link_params *params) 7978 7979 { 7980 u8 val; 7981 int rc; 7982 struct bnx2x *bp = params->bp; 7983 u16 timeout; 7984 /* Initialization time after hot-plug may take up to 300ms for 7985 * some phys type ( e.g. JDSU ) 7986 */ 7987 7988 for (timeout = 0; timeout < 60; timeout++) { 7989 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) 7990 rc = bnx2x_warpcore_read_sfp_module_eeprom(phy, 7991 params, 1, 7992 1, &val, 1); 7993 else 7994 rc = bnx2x_read_sfp_module_eeprom(phy, params, 1, 1, 7995 &val); 7996 if (rc == 0) { 7997 DP(NETIF_MSG_LINK, 7998 "SFP+ module initialization took %d ms\n", 7999 timeout * 5); 8000 return 0; 8001 } 8002 usleep_range(5000, 10000); 8003 } 8004 rc = bnx2x_read_sfp_module_eeprom(phy, params, 1, 1, &val); 8005 return rc; 8006 } 8007 8008 static void bnx2x_8727_power_module(struct bnx2x *bp, 8009 struct bnx2x_phy *phy, 8010 u8 is_power_up) { 8011 /* Make sure GPIOs are not using for LED mode */ 8012 u16 val; 8013 /* In the GPIO register, bit 4 is use to determine if the GPIOs are 8014 * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for 8015 * output 8016 * Bits 0-1 determine the GPIOs value for OUTPUT in case bit 4 val is 0 8017 * Bits 8-9 determine the GPIOs value for INPUT in case bit 4 val is 1 8018 * where the 1st bit is the over-current(only input), and 2nd bit is 8019 * for power( only output ) 8020 * 8021 * In case of NOC feature is disabled and power is up, set GPIO control 8022 * as input to enable listening of over-current indication 8023 */ 8024 if (phy->flags & FLAGS_NOC) 8025 return; 8026 if (is_power_up) 8027 val = (1<<4); 8028 else 8029 /* Set GPIO control to OUTPUT, and set the power bit 8030 * to according to the is_power_up 8031 */ 8032 val = (1<<1); 8033 8034 bnx2x_cl45_write(bp, phy, 8035 MDIO_PMA_DEVAD, 8036 MDIO_PMA_REG_8727_GPIO_CTRL, 8037 val); 8038 } 8039 8040 static int bnx2x_8726_set_limiting_mode(struct bnx2x *bp, 8041 struct bnx2x_phy *phy, 8042 u16 edc_mode) 8043 { 8044 u16 cur_limiting_mode; 8045 8046 bnx2x_cl45_read(bp, phy, 8047 MDIO_PMA_DEVAD, 8048 MDIO_PMA_REG_ROM_VER2, 8049 &cur_limiting_mode); 8050 DP(NETIF_MSG_LINK, "Current Limiting mode is 0x%x\n", 8051 cur_limiting_mode); 8052 8053 if (edc_mode == EDC_MODE_LIMITING) { 8054 DP(NETIF_MSG_LINK, "Setting LIMITING MODE\n"); 8055 bnx2x_cl45_write(bp, phy, 8056 MDIO_PMA_DEVAD, 8057 MDIO_PMA_REG_ROM_VER2, 8058 EDC_MODE_LIMITING); 8059 } else { /* LRM mode ( default )*/ 8060 8061 DP(NETIF_MSG_LINK, "Setting LRM MODE\n"); 8062 8063 /* Changing to LRM mode takes quite few seconds. So do it only 8064 * if current mode is limiting (default is LRM) 8065 */ 8066 if (cur_limiting_mode != EDC_MODE_LIMITING) 8067 return 0; 8068 8069 bnx2x_cl45_write(bp, phy, 8070 MDIO_PMA_DEVAD, 8071 MDIO_PMA_REG_LRM_MODE, 8072 0); 8073 bnx2x_cl45_write(bp, phy, 8074 MDIO_PMA_DEVAD, 8075 MDIO_PMA_REG_ROM_VER2, 8076 0x128); 8077 bnx2x_cl45_write(bp, phy, 8078 MDIO_PMA_DEVAD, 8079 MDIO_PMA_REG_MISC_CTRL0, 8080 0x4008); 8081 bnx2x_cl45_write(bp, phy, 8082 MDIO_PMA_DEVAD, 8083 MDIO_PMA_REG_LRM_MODE, 8084 0xaaaa); 8085 } 8086 return 0; 8087 } 8088 8089 static int bnx2x_8727_set_limiting_mode(struct bnx2x *bp, 8090 struct bnx2x_phy *phy, 8091 u16 edc_mode) 8092 { 8093 u16 phy_identifier; 8094 u16 rom_ver2_val; 8095 bnx2x_cl45_read(bp, phy, 8096 MDIO_PMA_DEVAD, 8097 MDIO_PMA_REG_PHY_IDENTIFIER, 8098 &phy_identifier); 8099 8100 bnx2x_cl45_write(bp, phy, 8101 MDIO_PMA_DEVAD, 8102 MDIO_PMA_REG_PHY_IDENTIFIER, 8103 (phy_identifier & ~(1<<9))); 8104 8105 bnx2x_cl45_read(bp, phy, 8106 MDIO_PMA_DEVAD, 8107 MDIO_PMA_REG_ROM_VER2, 8108 &rom_ver2_val); 8109 /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */ 8110 bnx2x_cl45_write(bp, phy, 8111 MDIO_PMA_DEVAD, 8112 MDIO_PMA_REG_ROM_VER2, 8113 (rom_ver2_val & 0xff00) | (edc_mode & 0x00ff)); 8114 8115 bnx2x_cl45_write(bp, phy, 8116 MDIO_PMA_DEVAD, 8117 MDIO_PMA_REG_PHY_IDENTIFIER, 8118 (phy_identifier | (1<<9))); 8119 8120 return 0; 8121 } 8122 8123 static void bnx2x_8727_specific_func(struct bnx2x_phy *phy, 8124 struct link_params *params, 8125 u32 action) 8126 { 8127 struct bnx2x *bp = params->bp; 8128 u16 val; 8129 switch (action) { 8130 case DISABLE_TX: 8131 bnx2x_sfp_set_transmitter(params, phy, 0); 8132 break; 8133 case ENABLE_TX: 8134 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED)) 8135 bnx2x_sfp_set_transmitter(params, phy, 1); 8136 break; 8137 case PHY_INIT: 8138 bnx2x_cl45_write(bp, phy, 8139 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, 8140 (1<<2) | (1<<5)); 8141 bnx2x_cl45_write(bp, phy, 8142 MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL, 8143 0); 8144 bnx2x_cl45_write(bp, phy, 8145 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0006); 8146 /* Make MOD_ABS give interrupt on change */ 8147 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 8148 MDIO_PMA_REG_8727_PCS_OPT_CTRL, 8149 &val); 8150 val |= (1<<12); 8151 if (phy->flags & FLAGS_NOC) 8152 val |= (3<<5); 8153 /* Set 8727 GPIOs to input to allow reading from the 8727 GPIO0 8154 * status which reflect SFP+ module over-current 8155 */ 8156 if (!(phy->flags & FLAGS_NOC)) 8157 val &= 0xff8f; /* Reset bits 4-6 */ 8158 bnx2x_cl45_write(bp, phy, 8159 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL, 8160 val); 8161 8162 /* Set 2-wire transfer rate of SFP+ module EEPROM 8163 * to 100Khz since some DACs(direct attached cables) do 8164 * not work at 400Khz. 8165 */ 8166 bnx2x_cl45_write(bp, phy, 8167 MDIO_PMA_DEVAD, 8168 MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR, 8169 0xa001); 8170 break; 8171 default: 8172 DP(NETIF_MSG_LINK, "Function 0x%x not supported by 8727\n", 8173 action); 8174 return; 8175 } 8176 } 8177 8178 static void bnx2x_set_e1e2_module_fault_led(struct link_params *params, 8179 u8 gpio_mode) 8180 { 8181 struct bnx2x *bp = params->bp; 8182 8183 u32 fault_led_gpio = REG_RD(bp, params->shmem_base + 8184 offsetof(struct shmem_region, 8185 dev_info.port_hw_config[params->port].sfp_ctrl)) & 8186 PORT_HW_CFG_FAULT_MODULE_LED_MASK; 8187 switch (fault_led_gpio) { 8188 case PORT_HW_CFG_FAULT_MODULE_LED_DISABLED: 8189 return; 8190 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO0: 8191 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO1: 8192 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO2: 8193 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO3: 8194 { 8195 u8 gpio_port = bnx2x_get_gpio_port(params); 8196 u16 gpio_pin = fault_led_gpio - 8197 PORT_HW_CFG_FAULT_MODULE_LED_GPIO0; 8198 DP(NETIF_MSG_LINK, "Set fault module-detected led " 8199 "pin %x port %x mode %x\n", 8200 gpio_pin, gpio_port, gpio_mode); 8201 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port); 8202 } 8203 break; 8204 default: 8205 DP(NETIF_MSG_LINK, "Error: Invalid fault led mode 0x%x\n", 8206 fault_led_gpio); 8207 } 8208 } 8209 8210 static void bnx2x_set_e3_module_fault_led(struct link_params *params, 8211 u8 gpio_mode) 8212 { 8213 u32 pin_cfg; 8214 u8 port = params->port; 8215 struct bnx2x *bp = params->bp; 8216 pin_cfg = (REG_RD(bp, params->shmem_base + 8217 offsetof(struct shmem_region, 8218 dev_info.port_hw_config[port].e3_sfp_ctrl)) & 8219 PORT_HW_CFG_E3_FAULT_MDL_LED_MASK) >> 8220 PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT; 8221 DP(NETIF_MSG_LINK, "Setting Fault LED to %d using pin cfg %d\n", 8222 gpio_mode, pin_cfg); 8223 bnx2x_set_cfg_pin(bp, pin_cfg, gpio_mode); 8224 } 8225 8226 static void bnx2x_set_sfp_module_fault_led(struct link_params *params, 8227 u8 gpio_mode) 8228 { 8229 struct bnx2x *bp = params->bp; 8230 DP(NETIF_MSG_LINK, "Setting SFP+ module fault LED to %d\n", gpio_mode); 8231 if (CHIP_IS_E3(bp)) { 8232 /* Low ==> if SFP+ module is supported otherwise 8233 * High ==> if SFP+ module is not on the approved vendor list 8234 */ 8235 bnx2x_set_e3_module_fault_led(params, gpio_mode); 8236 } else 8237 bnx2x_set_e1e2_module_fault_led(params, gpio_mode); 8238 } 8239 8240 static void bnx2x_warpcore_hw_reset(struct bnx2x_phy *phy, 8241 struct link_params *params) 8242 { 8243 struct bnx2x *bp = params->bp; 8244 bnx2x_warpcore_power_module(params, phy, 0); 8245 /* Put Warpcore in low power mode */ 8246 REG_WR(bp, MISC_REG_WC0_RESET, 0x0c0e); 8247 8248 /* Put LCPLL in low power mode */ 8249 REG_WR(bp, MISC_REG_LCPLL_E40_PWRDWN, 1); 8250 REG_WR(bp, MISC_REG_LCPLL_E40_RESETB_ANA, 0); 8251 REG_WR(bp, MISC_REG_LCPLL_E40_RESETB_DIG, 0); 8252 } 8253 8254 static void bnx2x_power_sfp_module(struct link_params *params, 8255 struct bnx2x_phy *phy, 8256 u8 power) 8257 { 8258 struct bnx2x *bp = params->bp; 8259 DP(NETIF_MSG_LINK, "Setting SFP+ power to %x\n", power); 8260 8261 switch (phy->type) { 8262 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: 8263 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722: 8264 bnx2x_8727_power_module(params->bp, phy, power); 8265 break; 8266 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT: 8267 bnx2x_warpcore_power_module(params, phy, power); 8268 break; 8269 default: 8270 break; 8271 } 8272 } 8273 static void bnx2x_warpcore_set_limiting_mode(struct link_params *params, 8274 struct bnx2x_phy *phy, 8275 u16 edc_mode) 8276 { 8277 u16 val = 0; 8278 u16 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT; 8279 struct bnx2x *bp = params->bp; 8280 8281 u8 lane = bnx2x_get_warpcore_lane(phy, params); 8282 /* This is a global register which controls all lanes */ 8283 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 8284 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val); 8285 val &= ~(0xf << (lane << 2)); 8286 8287 switch (edc_mode) { 8288 case EDC_MODE_LINEAR: 8289 case EDC_MODE_LIMITING: 8290 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT; 8291 break; 8292 case EDC_MODE_PASSIVE_DAC: 8293 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC; 8294 break; 8295 default: 8296 break; 8297 } 8298 8299 val |= (mode << (lane << 2)); 8300 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 8301 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, val); 8302 /* A must read */ 8303 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 8304 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val); 8305 8306 /* Restart microcode to re-read the new mode */ 8307 bnx2x_warpcore_reset_lane(bp, phy, 1); 8308 bnx2x_warpcore_reset_lane(bp, phy, 0); 8309 8310 } 8311 8312 static void bnx2x_set_limiting_mode(struct link_params *params, 8313 struct bnx2x_phy *phy, 8314 u16 edc_mode) 8315 { 8316 switch (phy->type) { 8317 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: 8318 bnx2x_8726_set_limiting_mode(params->bp, phy, edc_mode); 8319 break; 8320 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: 8321 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722: 8322 bnx2x_8727_set_limiting_mode(params->bp, phy, edc_mode); 8323 break; 8324 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT: 8325 bnx2x_warpcore_set_limiting_mode(params, phy, edc_mode); 8326 break; 8327 } 8328 } 8329 8330 int bnx2x_sfp_module_detection(struct bnx2x_phy *phy, 8331 struct link_params *params) 8332 { 8333 struct bnx2x *bp = params->bp; 8334 u16 edc_mode; 8335 int rc = 0; 8336 8337 u32 val = REG_RD(bp, params->shmem_base + 8338 offsetof(struct shmem_region, dev_info. 8339 port_feature_config[params->port].config)); 8340 8341 DP(NETIF_MSG_LINK, "SFP+ module plugged in/out detected on port %d\n", 8342 params->port); 8343 /* Power up module */ 8344 bnx2x_power_sfp_module(params, phy, 1); 8345 if (bnx2x_get_edc_mode(phy, params, &edc_mode) != 0) { 8346 DP(NETIF_MSG_LINK, "Failed to get valid module type\n"); 8347 return -EINVAL; 8348 } else if (bnx2x_verify_sfp_module(phy, params) != 0) { 8349 /* Check SFP+ module compatibility */ 8350 DP(NETIF_MSG_LINK, "Module verification failed!!\n"); 8351 rc = -EINVAL; 8352 /* Turn on fault module-detected led */ 8353 bnx2x_set_sfp_module_fault_led(params, 8354 MISC_REGISTERS_GPIO_HIGH); 8355 8356 /* Check if need to power down the SFP+ module */ 8357 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == 8358 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN) { 8359 DP(NETIF_MSG_LINK, "Shutdown SFP+ module!!\n"); 8360 bnx2x_power_sfp_module(params, phy, 0); 8361 return rc; 8362 } 8363 } else { 8364 /* Turn off fault module-detected led */ 8365 bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_LOW); 8366 } 8367 8368 /* Check and set limiting mode / LRM mode on 8726. On 8727 it 8369 * is done automatically 8370 */ 8371 bnx2x_set_limiting_mode(params, phy, edc_mode); 8372 8373 /* Enable transmit for this module if the module is approved, or 8374 * if unapproved modules should also enable the Tx laser 8375 */ 8376 if (rc == 0 || 8377 (val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) != 8378 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER) 8379 bnx2x_sfp_set_transmitter(params, phy, 1); 8380 else 8381 bnx2x_sfp_set_transmitter(params, phy, 0); 8382 8383 return rc; 8384 } 8385 8386 void bnx2x_handle_module_detect_int(struct link_params *params) 8387 { 8388 struct bnx2x *bp = params->bp; 8389 struct bnx2x_phy *phy; 8390 u32 gpio_val; 8391 u8 gpio_num, gpio_port; 8392 if (CHIP_IS_E3(bp)) 8393 phy = ¶ms->phy[INT_PHY]; 8394 else 8395 phy = ¶ms->phy[EXT_PHY1]; 8396 8397 if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id, params->shmem_base, 8398 params->port, &gpio_num, &gpio_port) == 8399 -EINVAL) { 8400 DP(NETIF_MSG_LINK, "Failed to get MOD_ABS interrupt config\n"); 8401 return; 8402 } 8403 8404 /* Set valid module led off */ 8405 bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_HIGH); 8406 8407 /* Get current gpio val reflecting module plugged in / out*/ 8408 gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port); 8409 8410 /* Call the handling function in case module is detected */ 8411 if (gpio_val == 0) { 8412 bnx2x_set_mdio_clk(bp, params->chip_id, params->port); 8413 bnx2x_set_aer_mmd(params, phy); 8414 8415 bnx2x_power_sfp_module(params, phy, 1); 8416 bnx2x_set_gpio_int(bp, gpio_num, 8417 MISC_REGISTERS_GPIO_INT_OUTPUT_CLR, 8418 gpio_port); 8419 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0) { 8420 bnx2x_sfp_module_detection(phy, params); 8421 if (CHIP_IS_E3(bp)) { 8422 u16 rx_tx_in_reset; 8423 /* In case WC is out of reset, reconfigure the 8424 * link speed while taking into account 1G 8425 * module limitation. 8426 */ 8427 bnx2x_cl45_read(bp, phy, 8428 MDIO_WC_DEVAD, 8429 MDIO_WC_REG_DIGITAL5_MISC6, 8430 &rx_tx_in_reset); 8431 if (!rx_tx_in_reset) { 8432 bnx2x_warpcore_reset_lane(bp, phy, 1); 8433 bnx2x_warpcore_config_sfi(phy, params); 8434 bnx2x_warpcore_reset_lane(bp, phy, 0); 8435 } 8436 } 8437 } else { 8438 DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n"); 8439 } 8440 } else { 8441 u32 val = REG_RD(bp, params->shmem_base + 8442 offsetof(struct shmem_region, dev_info. 8443 port_feature_config[params->port]. 8444 config)); 8445 bnx2x_set_gpio_int(bp, gpio_num, 8446 MISC_REGISTERS_GPIO_INT_OUTPUT_SET, 8447 gpio_port); 8448 /* Module was plugged out. 8449 * Disable transmit for this module 8450 */ 8451 phy->media_type = ETH_PHY_NOT_PRESENT; 8452 if (((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == 8453 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER) || 8454 CHIP_IS_E3(bp)) 8455 bnx2x_sfp_set_transmitter(params, phy, 0); 8456 } 8457 } 8458 8459 /******************************************************************/ 8460 /* Used by 8706 and 8727 */ 8461 /******************************************************************/ 8462 static void bnx2x_sfp_mask_fault(struct bnx2x *bp, 8463 struct bnx2x_phy *phy, 8464 u16 alarm_status_offset, 8465 u16 alarm_ctrl_offset) 8466 { 8467 u16 alarm_status, val; 8468 bnx2x_cl45_read(bp, phy, 8469 MDIO_PMA_DEVAD, alarm_status_offset, 8470 &alarm_status); 8471 bnx2x_cl45_read(bp, phy, 8472 MDIO_PMA_DEVAD, alarm_status_offset, 8473 &alarm_status); 8474 /* Mask or enable the fault event. */ 8475 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, &val); 8476 if (alarm_status & (1<<0)) 8477 val &= ~(1<<0); 8478 else 8479 val |= (1<<0); 8480 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, val); 8481 } 8482 /******************************************************************/ 8483 /* common BCM8706/BCM8726 PHY SECTION */ 8484 /******************************************************************/ 8485 static u8 bnx2x_8706_8726_read_status(struct bnx2x_phy *phy, 8486 struct link_params *params, 8487 struct link_vars *vars) 8488 { 8489 u8 link_up = 0; 8490 u16 val1, val2, rx_sd, pcs_status; 8491 struct bnx2x *bp = params->bp; 8492 DP(NETIF_MSG_LINK, "XGXS 8706/8726\n"); 8493 /* Clear RX Alarm*/ 8494 bnx2x_cl45_read(bp, phy, 8495 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2); 8496 8497 bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT, 8498 MDIO_PMA_LASI_TXCTRL); 8499 8500 /* Clear LASI indication*/ 8501 bnx2x_cl45_read(bp, phy, 8502 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1); 8503 bnx2x_cl45_read(bp, phy, 8504 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2); 8505 DP(NETIF_MSG_LINK, "8706/8726 LASI status 0x%x--> 0x%x\n", val1, val2); 8506 8507 bnx2x_cl45_read(bp, phy, 8508 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd); 8509 bnx2x_cl45_read(bp, phy, 8510 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &pcs_status); 8511 bnx2x_cl45_read(bp, phy, 8512 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2); 8513 bnx2x_cl45_read(bp, phy, 8514 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2); 8515 8516 DP(NETIF_MSG_LINK, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps" 8517 " link_status 0x%x\n", rx_sd, pcs_status, val2); 8518 /* Link is up if both bit 0 of pmd_rx_sd and bit 0 of pcs_status 8519 * are set, or if the autoneg bit 1 is set 8520 */ 8521 link_up = ((rx_sd & pcs_status & 0x1) || (val2 & (1<<1))); 8522 if (link_up) { 8523 if (val2 & (1<<1)) 8524 vars->line_speed = SPEED_1000; 8525 else 8526 vars->line_speed = SPEED_10000; 8527 bnx2x_ext_phy_resolve_fc(phy, params, vars); 8528 vars->duplex = DUPLEX_FULL; 8529 } 8530 8531 /* Capture 10G link fault. Read twice to clear stale value. */ 8532 if (vars->line_speed == SPEED_10000) { 8533 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 8534 MDIO_PMA_LASI_TXSTAT, &val1); 8535 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 8536 MDIO_PMA_LASI_TXSTAT, &val1); 8537 if (val1 & (1<<0)) 8538 vars->fault_detected = 1; 8539 } 8540 8541 return link_up; 8542 } 8543 8544 /******************************************************************/ 8545 /* BCM8706 PHY SECTION */ 8546 /******************************************************************/ 8547 static u8 bnx2x_8706_config_init(struct bnx2x_phy *phy, 8548 struct link_params *params, 8549 struct link_vars *vars) 8550 { 8551 u32 tx_en_mode; 8552 u16 cnt, val, tmp1; 8553 struct bnx2x *bp = params->bp; 8554 8555 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 8556 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); 8557 /* HW reset */ 8558 bnx2x_ext_phy_hw_reset(bp, params->port); 8559 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040); 8560 bnx2x_wait_reset_complete(bp, phy, params); 8561 8562 /* Wait until fw is loaded */ 8563 for (cnt = 0; cnt < 100; cnt++) { 8564 bnx2x_cl45_read(bp, phy, 8565 MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER1, &val); 8566 if (val) 8567 break; 8568 usleep_range(10000, 20000); 8569 } 8570 DP(NETIF_MSG_LINK, "XGXS 8706 is initialized after %d ms\n", cnt); 8571 if ((params->feature_config_flags & 8572 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) { 8573 u8 i; 8574 u16 reg; 8575 for (i = 0; i < 4; i++) { 8576 reg = MDIO_XS_8706_REG_BANK_RX0 + 8577 i*(MDIO_XS_8706_REG_BANK_RX1 - 8578 MDIO_XS_8706_REG_BANK_RX0); 8579 bnx2x_cl45_read(bp, phy, MDIO_XS_DEVAD, reg, &val); 8580 /* Clear first 3 bits of the control */ 8581 val &= ~0x7; 8582 /* Set control bits according to configuration */ 8583 val |= (phy->rx_preemphasis[i] & 0x7); 8584 DP(NETIF_MSG_LINK, "Setting RX Equalizer to BCM8706" 8585 " reg 0x%x <-- val 0x%x\n", reg, val); 8586 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, reg, val); 8587 } 8588 } 8589 /* Force speed */ 8590 if (phy->req_line_speed == SPEED_10000) { 8591 DP(NETIF_MSG_LINK, "XGXS 8706 force 10Gbps\n"); 8592 8593 bnx2x_cl45_write(bp, phy, 8594 MDIO_PMA_DEVAD, 8595 MDIO_PMA_REG_DIGITAL_CTRL, 0x400); 8596 bnx2x_cl45_write(bp, phy, 8597 MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL, 8598 0); 8599 /* Arm LASI for link and Tx fault. */ 8600 bnx2x_cl45_write(bp, phy, 8601 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 3); 8602 } else { 8603 /* Force 1Gbps using autoneg with 1G advertisement */ 8604 8605 /* Allow CL37 through CL73 */ 8606 DP(NETIF_MSG_LINK, "XGXS 8706 AutoNeg\n"); 8607 bnx2x_cl45_write(bp, phy, 8608 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c); 8609 8610 /* Enable Full-Duplex advertisement on CL37 */ 8611 bnx2x_cl45_write(bp, phy, 8612 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LP, 0x0020); 8613 /* Enable CL37 AN */ 8614 bnx2x_cl45_write(bp, phy, 8615 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000); 8616 /* 1G support */ 8617 bnx2x_cl45_write(bp, phy, 8618 MDIO_AN_DEVAD, MDIO_AN_REG_ADV, (1<<5)); 8619 8620 /* Enable clause 73 AN */ 8621 bnx2x_cl45_write(bp, phy, 8622 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200); 8623 bnx2x_cl45_write(bp, phy, 8624 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, 8625 0x0400); 8626 bnx2x_cl45_write(bp, phy, 8627 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 8628 0x0004); 8629 } 8630 bnx2x_save_bcm_spirom_ver(bp, phy, params->port); 8631 8632 /* If TX Laser is controlled by GPIO_0, do not let PHY go into low 8633 * power mode, if TX Laser is disabled 8634 */ 8635 8636 tx_en_mode = REG_RD(bp, params->shmem_base + 8637 offsetof(struct shmem_region, 8638 dev_info.port_hw_config[params->port].sfp_ctrl)) 8639 & PORT_HW_CFG_TX_LASER_MASK; 8640 8641 if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) { 8642 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n"); 8643 bnx2x_cl45_read(bp, phy, 8644 MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, &tmp1); 8645 tmp1 |= 0x1; 8646 bnx2x_cl45_write(bp, phy, 8647 MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, tmp1); 8648 } 8649 8650 return 0; 8651 } 8652 8653 static int bnx2x_8706_read_status(struct bnx2x_phy *phy, 8654 struct link_params *params, 8655 struct link_vars *vars) 8656 { 8657 return bnx2x_8706_8726_read_status(phy, params, vars); 8658 } 8659 8660 /******************************************************************/ 8661 /* BCM8726 PHY SECTION */ 8662 /******************************************************************/ 8663 static void bnx2x_8726_config_loopback(struct bnx2x_phy *phy, 8664 struct link_params *params) 8665 { 8666 struct bnx2x *bp = params->bp; 8667 DP(NETIF_MSG_LINK, "PMA/PMD ext_phy_loopback: 8726\n"); 8668 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001); 8669 } 8670 8671 static void bnx2x_8726_external_rom_boot(struct bnx2x_phy *phy, 8672 struct link_params *params) 8673 { 8674 struct bnx2x *bp = params->bp; 8675 /* Need to wait 100ms after reset */ 8676 msleep(100); 8677 8678 /* Micro controller re-boot */ 8679 bnx2x_cl45_write(bp, phy, 8680 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x018B); 8681 8682 /* Set soft reset */ 8683 bnx2x_cl45_write(bp, phy, 8684 MDIO_PMA_DEVAD, 8685 MDIO_PMA_REG_GEN_CTRL, 8686 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET); 8687 8688 bnx2x_cl45_write(bp, phy, 8689 MDIO_PMA_DEVAD, 8690 MDIO_PMA_REG_MISC_CTRL1, 0x0001); 8691 8692 bnx2x_cl45_write(bp, phy, 8693 MDIO_PMA_DEVAD, 8694 MDIO_PMA_REG_GEN_CTRL, 8695 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP); 8696 8697 /* Wait for 150ms for microcode load */ 8698 msleep(150); 8699 8700 /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */ 8701 bnx2x_cl45_write(bp, phy, 8702 MDIO_PMA_DEVAD, 8703 MDIO_PMA_REG_MISC_CTRL1, 0x0000); 8704 8705 msleep(200); 8706 bnx2x_save_bcm_spirom_ver(bp, phy, params->port); 8707 } 8708 8709 static u8 bnx2x_8726_read_status(struct bnx2x_phy *phy, 8710 struct link_params *params, 8711 struct link_vars *vars) 8712 { 8713 struct bnx2x *bp = params->bp; 8714 u16 val1; 8715 u8 link_up = bnx2x_8706_8726_read_status(phy, params, vars); 8716 if (link_up) { 8717 bnx2x_cl45_read(bp, phy, 8718 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 8719 &val1); 8720 if (val1 & (1<<15)) { 8721 DP(NETIF_MSG_LINK, "Tx is disabled\n"); 8722 link_up = 0; 8723 vars->line_speed = 0; 8724 } 8725 } 8726 return link_up; 8727 } 8728 8729 8730 static int bnx2x_8726_config_init(struct bnx2x_phy *phy, 8731 struct link_params *params, 8732 struct link_vars *vars) 8733 { 8734 struct bnx2x *bp = params->bp; 8735 DP(NETIF_MSG_LINK, "Initializing BCM8726\n"); 8736 8737 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15); 8738 bnx2x_wait_reset_complete(bp, phy, params); 8739 8740 bnx2x_8726_external_rom_boot(phy, params); 8741 8742 /* Need to call module detected on initialization since the module 8743 * detection triggered by actual module insertion might occur before 8744 * driver is loaded, and when driver is loaded, it reset all 8745 * registers, including the transmitter 8746 */ 8747 bnx2x_sfp_module_detection(phy, params); 8748 8749 if (phy->req_line_speed == SPEED_1000) { 8750 DP(NETIF_MSG_LINK, "Setting 1G force\n"); 8751 bnx2x_cl45_write(bp, phy, 8752 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40); 8753 bnx2x_cl45_write(bp, phy, 8754 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD); 8755 bnx2x_cl45_write(bp, phy, 8756 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x5); 8757 bnx2x_cl45_write(bp, phy, 8758 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, 8759 0x400); 8760 } else if ((phy->req_line_speed == SPEED_AUTO_NEG) && 8761 (phy->speed_cap_mask & 8762 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) && 8763 ((phy->speed_cap_mask & 8764 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) != 8765 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) { 8766 DP(NETIF_MSG_LINK, "Setting 1G clause37\n"); 8767 /* Set Flow control */ 8768 bnx2x_ext_phy_set_pause(params, phy, vars); 8769 bnx2x_cl45_write(bp, phy, 8770 MDIO_AN_DEVAD, MDIO_AN_REG_ADV, 0x20); 8771 bnx2x_cl45_write(bp, phy, 8772 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c); 8773 bnx2x_cl45_write(bp, phy, 8774 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, 0x0020); 8775 bnx2x_cl45_write(bp, phy, 8776 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000); 8777 bnx2x_cl45_write(bp, phy, 8778 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200); 8779 /* Enable RX-ALARM control to receive interrupt for 1G speed 8780 * change 8781 */ 8782 bnx2x_cl45_write(bp, phy, 8783 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x4); 8784 bnx2x_cl45_write(bp, phy, 8785 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, 8786 0x400); 8787 8788 } else { /* Default 10G. Set only LASI control */ 8789 bnx2x_cl45_write(bp, phy, 8790 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 1); 8791 } 8792 8793 /* Set TX PreEmphasis if needed */ 8794 if ((params->feature_config_flags & 8795 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) { 8796 DP(NETIF_MSG_LINK, 8797 "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n", 8798 phy->tx_preemphasis[0], 8799 phy->tx_preemphasis[1]); 8800 bnx2x_cl45_write(bp, phy, 8801 MDIO_PMA_DEVAD, 8802 MDIO_PMA_REG_8726_TX_CTRL1, 8803 phy->tx_preemphasis[0]); 8804 8805 bnx2x_cl45_write(bp, phy, 8806 MDIO_PMA_DEVAD, 8807 MDIO_PMA_REG_8726_TX_CTRL2, 8808 phy->tx_preemphasis[1]); 8809 } 8810 8811 return 0; 8812 8813 } 8814 8815 static void bnx2x_8726_link_reset(struct bnx2x_phy *phy, 8816 struct link_params *params) 8817 { 8818 struct bnx2x *bp = params->bp; 8819 DP(NETIF_MSG_LINK, "bnx2x_8726_link_reset port %d\n", params->port); 8820 /* Set serial boot control for external load */ 8821 bnx2x_cl45_write(bp, phy, 8822 MDIO_PMA_DEVAD, 8823 MDIO_PMA_REG_GEN_CTRL, 0x0001); 8824 } 8825 8826 /******************************************************************/ 8827 /* BCM8727 PHY SECTION */ 8828 /******************************************************************/ 8829 8830 static void bnx2x_8727_set_link_led(struct bnx2x_phy *phy, 8831 struct link_params *params, u8 mode) 8832 { 8833 struct bnx2x *bp = params->bp; 8834 u16 led_mode_bitmask = 0; 8835 u16 gpio_pins_bitmask = 0; 8836 u16 val; 8837 /* Only NOC flavor requires to set the LED specifically */ 8838 if (!(phy->flags & FLAGS_NOC)) 8839 return; 8840 switch (mode) { 8841 case LED_MODE_FRONT_PANEL_OFF: 8842 case LED_MODE_OFF: 8843 led_mode_bitmask = 0; 8844 gpio_pins_bitmask = 0x03; 8845 break; 8846 case LED_MODE_ON: 8847 led_mode_bitmask = 0; 8848 gpio_pins_bitmask = 0x02; 8849 break; 8850 case LED_MODE_OPER: 8851 led_mode_bitmask = 0x60; 8852 gpio_pins_bitmask = 0x11; 8853 break; 8854 } 8855 bnx2x_cl45_read(bp, phy, 8856 MDIO_PMA_DEVAD, 8857 MDIO_PMA_REG_8727_PCS_OPT_CTRL, 8858 &val); 8859 val &= 0xff8f; 8860 val |= led_mode_bitmask; 8861 bnx2x_cl45_write(bp, phy, 8862 MDIO_PMA_DEVAD, 8863 MDIO_PMA_REG_8727_PCS_OPT_CTRL, 8864 val); 8865 bnx2x_cl45_read(bp, phy, 8866 MDIO_PMA_DEVAD, 8867 MDIO_PMA_REG_8727_GPIO_CTRL, 8868 &val); 8869 val &= 0xffe0; 8870 val |= gpio_pins_bitmask; 8871 bnx2x_cl45_write(bp, phy, 8872 MDIO_PMA_DEVAD, 8873 MDIO_PMA_REG_8727_GPIO_CTRL, 8874 val); 8875 } 8876 static void bnx2x_8727_hw_reset(struct bnx2x_phy *phy, 8877 struct link_params *params) { 8878 u32 swap_val, swap_override; 8879 u8 port; 8880 /* The PHY reset is controlled by GPIO 1. Fake the port number 8881 * to cancel the swap done in set_gpio() 8882 */ 8883 struct bnx2x *bp = params->bp; 8884 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); 8885 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); 8886 port = (swap_val && swap_override) ^ 1; 8887 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, 8888 MISC_REGISTERS_GPIO_OUTPUT_LOW, port); 8889 } 8890 8891 static void bnx2x_8727_config_speed(struct bnx2x_phy *phy, 8892 struct link_params *params) 8893 { 8894 struct bnx2x *bp = params->bp; 8895 u16 tmp1, val; 8896 /* Set option 1G speed */ 8897 if ((phy->req_line_speed == SPEED_1000) || 8898 (phy->media_type == ETH_PHY_SFP_1G_FIBER)) { 8899 DP(NETIF_MSG_LINK, "Setting 1G force\n"); 8900 bnx2x_cl45_write(bp, phy, 8901 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40); 8902 bnx2x_cl45_write(bp, phy, 8903 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD); 8904 bnx2x_cl45_read(bp, phy, 8905 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, &tmp1); 8906 DP(NETIF_MSG_LINK, "1.7 = 0x%x\n", tmp1); 8907 /* Power down the XAUI until link is up in case of dual-media 8908 * and 1G 8909 */ 8910 if (DUAL_MEDIA(params)) { 8911 bnx2x_cl45_read(bp, phy, 8912 MDIO_PMA_DEVAD, 8913 MDIO_PMA_REG_8727_PCS_GP, &val); 8914 val |= (3<<10); 8915 bnx2x_cl45_write(bp, phy, 8916 MDIO_PMA_DEVAD, 8917 MDIO_PMA_REG_8727_PCS_GP, val); 8918 } 8919 } else if ((phy->req_line_speed == SPEED_AUTO_NEG) && 8920 ((phy->speed_cap_mask & 8921 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) && 8922 ((phy->speed_cap_mask & 8923 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) != 8924 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) { 8925 8926 DP(NETIF_MSG_LINK, "Setting 1G clause37\n"); 8927 bnx2x_cl45_write(bp, phy, 8928 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 0); 8929 bnx2x_cl45_write(bp, phy, 8930 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1300); 8931 } else { 8932 /* Since the 8727 has only single reset pin, need to set the 10G 8933 * registers although it is default 8934 */ 8935 bnx2x_cl45_write(bp, phy, 8936 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 8937 0x0020); 8938 bnx2x_cl45_write(bp, phy, 8939 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x0100); 8940 bnx2x_cl45_write(bp, phy, 8941 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040); 8942 bnx2x_cl45_write(bp, phy, 8943 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 8944 0x0008); 8945 } 8946 } 8947 8948 static int bnx2x_8727_config_init(struct bnx2x_phy *phy, 8949 struct link_params *params, 8950 struct link_vars *vars) 8951 { 8952 u32 tx_en_mode; 8953 u16 tmp1, mod_abs, tmp2; 8954 struct bnx2x *bp = params->bp; 8955 /* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */ 8956 8957 bnx2x_wait_reset_complete(bp, phy, params); 8958 8959 DP(NETIF_MSG_LINK, "Initializing BCM8727\n"); 8960 8961 bnx2x_8727_specific_func(phy, params, PHY_INIT); 8962 /* Initially configure MOD_ABS to interrupt when module is 8963 * presence( bit 8) 8964 */ 8965 bnx2x_cl45_read(bp, phy, 8966 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs); 8967 /* Set EDC off by setting OPTXLOS signal input to low (bit 9). 8968 * When the EDC is off it locks onto a reference clock and avoids 8969 * becoming 'lost' 8970 */ 8971 mod_abs &= ~(1<<8); 8972 if (!(phy->flags & FLAGS_NOC)) 8973 mod_abs &= ~(1<<9); 8974 bnx2x_cl45_write(bp, phy, 8975 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs); 8976 8977 /* Enable/Disable PHY transmitter output */ 8978 bnx2x_set_disable_pmd_transmit(params, phy, 0); 8979 8980 bnx2x_8727_power_module(bp, phy, 1); 8981 8982 bnx2x_cl45_read(bp, phy, 8983 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1); 8984 8985 bnx2x_cl45_read(bp, phy, 8986 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1); 8987 8988 bnx2x_8727_config_speed(phy, params); 8989 8990 8991 /* Set TX PreEmphasis if needed */ 8992 if ((params->feature_config_flags & 8993 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) { 8994 DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n", 8995 phy->tx_preemphasis[0], 8996 phy->tx_preemphasis[1]); 8997 bnx2x_cl45_write(bp, phy, 8998 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL1, 8999 phy->tx_preemphasis[0]); 9000 9001 bnx2x_cl45_write(bp, phy, 9002 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL2, 9003 phy->tx_preemphasis[1]); 9004 } 9005 9006 /* If TX Laser is controlled by GPIO_0, do not let PHY go into low 9007 * power mode, if TX Laser is disabled 9008 */ 9009 tx_en_mode = REG_RD(bp, params->shmem_base + 9010 offsetof(struct shmem_region, 9011 dev_info.port_hw_config[params->port].sfp_ctrl)) 9012 & PORT_HW_CFG_TX_LASER_MASK; 9013 9014 if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) { 9015 9016 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n"); 9017 bnx2x_cl45_read(bp, phy, 9018 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, &tmp2); 9019 tmp2 |= 0x1000; 9020 tmp2 &= 0xFFEF; 9021 bnx2x_cl45_write(bp, phy, 9022 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, tmp2); 9023 bnx2x_cl45_read(bp, phy, 9024 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 9025 &tmp2); 9026 bnx2x_cl45_write(bp, phy, 9027 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 9028 (tmp2 & 0x7fff)); 9029 } 9030 9031 return 0; 9032 } 9033 9034 static void bnx2x_8727_handle_mod_abs(struct bnx2x_phy *phy, 9035 struct link_params *params) 9036 { 9037 struct bnx2x *bp = params->bp; 9038 u16 mod_abs, rx_alarm_status; 9039 u32 val = REG_RD(bp, params->shmem_base + 9040 offsetof(struct shmem_region, dev_info. 9041 port_feature_config[params->port]. 9042 config)); 9043 bnx2x_cl45_read(bp, phy, 9044 MDIO_PMA_DEVAD, 9045 MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs); 9046 if (mod_abs & (1<<8)) { 9047 9048 /* Module is absent */ 9049 DP(NETIF_MSG_LINK, 9050 "MOD_ABS indication show module is absent\n"); 9051 phy->media_type = ETH_PHY_NOT_PRESENT; 9052 /* 1. Set mod_abs to detect next module 9053 * presence event 9054 * 2. Set EDC off by setting OPTXLOS signal input to low 9055 * (bit 9). 9056 * When the EDC is off it locks onto a reference clock and 9057 * avoids becoming 'lost'. 9058 */ 9059 mod_abs &= ~(1<<8); 9060 if (!(phy->flags & FLAGS_NOC)) 9061 mod_abs &= ~(1<<9); 9062 bnx2x_cl45_write(bp, phy, 9063 MDIO_PMA_DEVAD, 9064 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs); 9065 9066 /* Clear RX alarm since it stays up as long as 9067 * the mod_abs wasn't changed 9068 */ 9069 bnx2x_cl45_read(bp, phy, 9070 MDIO_PMA_DEVAD, 9071 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status); 9072 9073 } else { 9074 /* Module is present */ 9075 DP(NETIF_MSG_LINK, 9076 "MOD_ABS indication show module is present\n"); 9077 /* First disable transmitter, and if the module is ok, the 9078 * module_detection will enable it 9079 * 1. Set mod_abs to detect next module absent event ( bit 8) 9080 * 2. Restore the default polarity of the OPRXLOS signal and 9081 * this signal will then correctly indicate the presence or 9082 * absence of the Rx signal. (bit 9) 9083 */ 9084 mod_abs |= (1<<8); 9085 if (!(phy->flags & FLAGS_NOC)) 9086 mod_abs |= (1<<9); 9087 bnx2x_cl45_write(bp, phy, 9088 MDIO_PMA_DEVAD, 9089 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs); 9090 9091 /* Clear RX alarm since it stays up as long as the mod_abs 9092 * wasn't changed. This is need to be done before calling the 9093 * module detection, otherwise it will clear* the link update 9094 * alarm 9095 */ 9096 bnx2x_cl45_read(bp, phy, 9097 MDIO_PMA_DEVAD, 9098 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status); 9099 9100 9101 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == 9102 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER) 9103 bnx2x_sfp_set_transmitter(params, phy, 0); 9104 9105 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0) 9106 bnx2x_sfp_module_detection(phy, params); 9107 else 9108 DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n"); 9109 9110 /* Reconfigure link speed based on module type limitations */ 9111 bnx2x_8727_config_speed(phy, params); 9112 } 9113 9114 DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n", 9115 rx_alarm_status); 9116 /* No need to check link status in case of module plugged in/out */ 9117 } 9118 9119 static u8 bnx2x_8727_read_status(struct bnx2x_phy *phy, 9120 struct link_params *params, 9121 struct link_vars *vars) 9122 9123 { 9124 struct bnx2x *bp = params->bp; 9125 u8 link_up = 0, oc_port = params->port; 9126 u16 link_status = 0; 9127 u16 rx_alarm_status, lasi_ctrl, val1; 9128 9129 /* If PHY is not initialized, do not check link status */ 9130 bnx2x_cl45_read(bp, phy, 9131 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 9132 &lasi_ctrl); 9133 if (!lasi_ctrl) 9134 return 0; 9135 9136 /* Check the LASI on Rx */ 9137 bnx2x_cl45_read(bp, phy, 9138 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, 9139 &rx_alarm_status); 9140 vars->line_speed = 0; 9141 DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n", rx_alarm_status); 9142 9143 bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT, 9144 MDIO_PMA_LASI_TXCTRL); 9145 9146 bnx2x_cl45_read(bp, phy, 9147 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1); 9148 9149 DP(NETIF_MSG_LINK, "8727 LASI status 0x%x\n", val1); 9150 9151 /* Clear MSG-OUT */ 9152 bnx2x_cl45_read(bp, phy, 9153 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1); 9154 9155 /* If a module is present and there is need to check 9156 * for over current 9157 */ 9158 if (!(phy->flags & FLAGS_NOC) && !(rx_alarm_status & (1<<5))) { 9159 /* Check over-current using 8727 GPIO0 input*/ 9160 bnx2x_cl45_read(bp, phy, 9161 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL, 9162 &val1); 9163 9164 if ((val1 & (1<<8)) == 0) { 9165 if (!CHIP_IS_E1x(bp)) 9166 oc_port = BP_PATH(bp) + (params->port << 1); 9167 DP(NETIF_MSG_LINK, 9168 "8727 Power fault has been detected on port %d\n", 9169 oc_port); 9170 netdev_err(bp->dev, "Error: Power fault on Port %d has " 9171 "been detected and the power to " 9172 "that SFP+ module has been removed " 9173 "to prevent failure of the card. " 9174 "Please remove the SFP+ module and " 9175 "restart the system to clear this " 9176 "error.\n", 9177 oc_port); 9178 /* Disable all RX_ALARMs except for mod_abs */ 9179 bnx2x_cl45_write(bp, phy, 9180 MDIO_PMA_DEVAD, 9181 MDIO_PMA_LASI_RXCTRL, (1<<5)); 9182 9183 bnx2x_cl45_read(bp, phy, 9184 MDIO_PMA_DEVAD, 9185 MDIO_PMA_REG_PHY_IDENTIFIER, &val1); 9186 /* Wait for module_absent_event */ 9187 val1 |= (1<<8); 9188 bnx2x_cl45_write(bp, phy, 9189 MDIO_PMA_DEVAD, 9190 MDIO_PMA_REG_PHY_IDENTIFIER, val1); 9191 /* Clear RX alarm */ 9192 bnx2x_cl45_read(bp, phy, 9193 MDIO_PMA_DEVAD, 9194 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status); 9195 return 0; 9196 } 9197 } /* Over current check */ 9198 9199 /* When module absent bit is set, check module */ 9200 if (rx_alarm_status & (1<<5)) { 9201 bnx2x_8727_handle_mod_abs(phy, params); 9202 /* Enable all mod_abs and link detection bits */ 9203 bnx2x_cl45_write(bp, phy, 9204 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, 9205 ((1<<5) | (1<<2))); 9206 } 9207 9208 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED)) { 9209 DP(NETIF_MSG_LINK, "Enabling 8727 TX laser\n"); 9210 bnx2x_sfp_set_transmitter(params, phy, 1); 9211 } else { 9212 DP(NETIF_MSG_LINK, "Tx is disabled\n"); 9213 return 0; 9214 } 9215 9216 bnx2x_cl45_read(bp, phy, 9217 MDIO_PMA_DEVAD, 9218 MDIO_PMA_REG_8073_SPEED_LINK_STATUS, &link_status); 9219 9220 /* Bits 0..2 --> speed detected, 9221 * Bits 13..15--> link is down 9222 */ 9223 if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) { 9224 link_up = 1; 9225 vars->line_speed = SPEED_10000; 9226 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n", 9227 params->port); 9228 } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) { 9229 link_up = 1; 9230 vars->line_speed = SPEED_1000; 9231 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n", 9232 params->port); 9233 } else { 9234 link_up = 0; 9235 DP(NETIF_MSG_LINK, "port %x: External link is down\n", 9236 params->port); 9237 } 9238 9239 /* Capture 10G link fault. */ 9240 if (vars->line_speed == SPEED_10000) { 9241 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 9242 MDIO_PMA_LASI_TXSTAT, &val1); 9243 9244 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 9245 MDIO_PMA_LASI_TXSTAT, &val1); 9246 9247 if (val1 & (1<<0)) { 9248 vars->fault_detected = 1; 9249 } 9250 } 9251 9252 if (link_up) { 9253 bnx2x_ext_phy_resolve_fc(phy, params, vars); 9254 vars->duplex = DUPLEX_FULL; 9255 DP(NETIF_MSG_LINK, "duplex = 0x%x\n", vars->duplex); 9256 } 9257 9258 if ((DUAL_MEDIA(params)) && 9259 (phy->req_line_speed == SPEED_1000)) { 9260 bnx2x_cl45_read(bp, phy, 9261 MDIO_PMA_DEVAD, 9262 MDIO_PMA_REG_8727_PCS_GP, &val1); 9263 /* In case of dual-media board and 1G, power up the XAUI side, 9264 * otherwise power it down. For 10G it is done automatically 9265 */ 9266 if (link_up) 9267 val1 &= ~(3<<10); 9268 else 9269 val1 |= (3<<10); 9270 bnx2x_cl45_write(bp, phy, 9271 MDIO_PMA_DEVAD, 9272 MDIO_PMA_REG_8727_PCS_GP, val1); 9273 } 9274 return link_up; 9275 } 9276 9277 static void bnx2x_8727_link_reset(struct bnx2x_phy *phy, 9278 struct link_params *params) 9279 { 9280 struct bnx2x *bp = params->bp; 9281 9282 /* Enable/Disable PHY transmitter output */ 9283 bnx2x_set_disable_pmd_transmit(params, phy, 1); 9284 9285 /* Disable Transmitter */ 9286 bnx2x_sfp_set_transmitter(params, phy, 0); 9287 /* Clear LASI */ 9288 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0); 9289 9290 } 9291 9292 /******************************************************************/ 9293 /* BCM8481/BCM84823/BCM84833 PHY SECTION */ 9294 /******************************************************************/ 9295 static void bnx2x_save_848xx_spirom_version(struct bnx2x_phy *phy, 9296 struct bnx2x *bp, 9297 u8 port) 9298 { 9299 u16 val, fw_ver1, fw_ver2, cnt; 9300 9301 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) { 9302 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 0x400f, &fw_ver1); 9303 bnx2x_save_spirom_version(bp, port, fw_ver1 & 0xfff, 9304 phy->ver_addr); 9305 } else { 9306 /* For 32-bit registers in 848xx, access via MDIO2ARM i/f. */ 9307 /* (1) set reg 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */ 9308 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0014); 9309 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200); 9310 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81B, 0x0000); 9311 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81C, 0x0300); 9312 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x0009); 9313 9314 for (cnt = 0; cnt < 100; cnt++) { 9315 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val); 9316 if (val & 1) 9317 break; 9318 udelay(5); 9319 } 9320 if (cnt == 100) { 9321 DP(NETIF_MSG_LINK, "Unable to read 848xx " 9322 "phy fw version(1)\n"); 9323 bnx2x_save_spirom_version(bp, port, 0, 9324 phy->ver_addr); 9325 return; 9326 } 9327 9328 9329 /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */ 9330 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0000); 9331 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200); 9332 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x000A); 9333 for (cnt = 0; cnt < 100; cnt++) { 9334 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val); 9335 if (val & 1) 9336 break; 9337 udelay(5); 9338 } 9339 if (cnt == 100) { 9340 DP(NETIF_MSG_LINK, "Unable to read 848xx phy fw " 9341 "version(2)\n"); 9342 bnx2x_save_spirom_version(bp, port, 0, 9343 phy->ver_addr); 9344 return; 9345 } 9346 9347 /* lower 16 bits of the register SPI_FW_STATUS */ 9348 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81B, &fw_ver1); 9349 /* upper 16 bits of register SPI_FW_STATUS */ 9350 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81C, &fw_ver2); 9351 9352 bnx2x_save_spirom_version(bp, port, (fw_ver2<<16) | fw_ver1, 9353 phy->ver_addr); 9354 } 9355 9356 } 9357 static void bnx2x_848xx_set_led(struct bnx2x *bp, 9358 struct bnx2x_phy *phy) 9359 { 9360 u16 val, offset; 9361 9362 /* PHYC_CTL_LED_CTL */ 9363 bnx2x_cl45_read(bp, phy, 9364 MDIO_PMA_DEVAD, 9365 MDIO_PMA_REG_8481_LINK_SIGNAL, &val); 9366 val &= 0xFE00; 9367 val |= 0x0092; 9368 9369 bnx2x_cl45_write(bp, phy, 9370 MDIO_PMA_DEVAD, 9371 MDIO_PMA_REG_8481_LINK_SIGNAL, val); 9372 9373 bnx2x_cl45_write(bp, phy, 9374 MDIO_PMA_DEVAD, 9375 MDIO_PMA_REG_8481_LED1_MASK, 9376 0x80); 9377 9378 bnx2x_cl45_write(bp, phy, 9379 MDIO_PMA_DEVAD, 9380 MDIO_PMA_REG_8481_LED2_MASK, 9381 0x18); 9382 9383 /* Select activity source by Tx and Rx, as suggested by PHY AE */ 9384 bnx2x_cl45_write(bp, phy, 9385 MDIO_PMA_DEVAD, 9386 MDIO_PMA_REG_8481_LED3_MASK, 9387 0x0006); 9388 9389 /* Select the closest activity blink rate to that in 10/100/1000 */ 9390 bnx2x_cl45_write(bp, phy, 9391 MDIO_PMA_DEVAD, 9392 MDIO_PMA_REG_8481_LED3_BLINK, 9393 0); 9394 9395 /* Configure the blink rate to ~15.9 Hz */ 9396 bnx2x_cl45_write(bp, phy, 9397 MDIO_PMA_DEVAD, 9398 MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH, 9399 MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ); 9400 9401 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) 9402 offset = MDIO_PMA_REG_84833_CTL_LED_CTL_1; 9403 else 9404 offset = MDIO_PMA_REG_84823_CTL_LED_CTL_1; 9405 9406 bnx2x_cl45_read(bp, phy, 9407 MDIO_PMA_DEVAD, offset, &val); 9408 val |= MDIO_PMA_REG_84823_LED3_STRETCH_EN; /* stretch_en for LED3*/ 9409 bnx2x_cl45_write(bp, phy, 9410 MDIO_PMA_DEVAD, offset, val); 9411 9412 /* 'Interrupt Mask' */ 9413 bnx2x_cl45_write(bp, phy, 9414 MDIO_AN_DEVAD, 9415 0xFFFB, 0xFFFD); 9416 } 9417 9418 static void bnx2x_848xx_specific_func(struct bnx2x_phy *phy, 9419 struct link_params *params, 9420 u32 action) 9421 { 9422 struct bnx2x *bp = params->bp; 9423 switch (action) { 9424 case PHY_INIT: 9425 if (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) { 9426 /* Save spirom version */ 9427 bnx2x_save_848xx_spirom_version(phy, bp, params->port); 9428 } 9429 /* This phy uses the NIG latch mechanism since link indication 9430 * arrives through its LED4 and not via its LASI signal, so we 9431 * get steady signal instead of clear on read 9432 */ 9433 bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4, 9434 1 << NIG_LATCH_BC_ENABLE_MI_INT); 9435 9436 bnx2x_848xx_set_led(bp, phy); 9437 break; 9438 } 9439 } 9440 9441 static int bnx2x_848xx_cmn_config_init(struct bnx2x_phy *phy, 9442 struct link_params *params, 9443 struct link_vars *vars) 9444 { 9445 struct bnx2x *bp = params->bp; 9446 u16 autoneg_val, an_1000_val, an_10_100_val, an_10g_val; 9447 9448 bnx2x_848xx_specific_func(phy, params, PHY_INIT); 9449 bnx2x_cl45_write(bp, phy, 9450 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0000); 9451 9452 /* set 1000 speed advertisement */ 9453 bnx2x_cl45_read(bp, phy, 9454 MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL, 9455 &an_1000_val); 9456 9457 bnx2x_ext_phy_set_pause(params, phy, vars); 9458 bnx2x_cl45_read(bp, phy, 9459 MDIO_AN_DEVAD, 9460 MDIO_AN_REG_8481_LEGACY_AN_ADV, 9461 &an_10_100_val); 9462 bnx2x_cl45_read(bp, phy, 9463 MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_MII_CTRL, 9464 &autoneg_val); 9465 /* Disable forced speed */ 9466 autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13)); 9467 an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8)); 9468 9469 if (((phy->req_line_speed == SPEED_AUTO_NEG) && 9470 (phy->speed_cap_mask & 9471 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) || 9472 (phy->req_line_speed == SPEED_1000)) { 9473 an_1000_val |= (1<<8); 9474 autoneg_val |= (1<<9 | 1<<12); 9475 if (phy->req_duplex == DUPLEX_FULL) 9476 an_1000_val |= (1<<9); 9477 DP(NETIF_MSG_LINK, "Advertising 1G\n"); 9478 } else 9479 an_1000_val &= ~((1<<8) | (1<<9)); 9480 9481 bnx2x_cl45_write(bp, phy, 9482 MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL, 9483 an_1000_val); 9484 9485 /* set 100 speed advertisement */ 9486 if ((phy->req_line_speed == SPEED_AUTO_NEG) && 9487 (phy->speed_cap_mask & 9488 (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL | 9489 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))) { 9490 an_10_100_val |= (1<<7); 9491 /* Enable autoneg and restart autoneg for legacy speeds */ 9492 autoneg_val |= (1<<9 | 1<<12); 9493 9494 if (phy->req_duplex == DUPLEX_FULL) 9495 an_10_100_val |= (1<<8); 9496 DP(NETIF_MSG_LINK, "Advertising 100M\n"); 9497 } 9498 /* set 10 speed advertisement */ 9499 if (((phy->req_line_speed == SPEED_AUTO_NEG) && 9500 (phy->speed_cap_mask & 9501 (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL | 9502 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) && 9503 (phy->supported & 9504 (SUPPORTED_10baseT_Half | 9505 SUPPORTED_10baseT_Full)))) { 9506 an_10_100_val |= (1<<5); 9507 autoneg_val |= (1<<9 | 1<<12); 9508 if (phy->req_duplex == DUPLEX_FULL) 9509 an_10_100_val |= (1<<6); 9510 DP(NETIF_MSG_LINK, "Advertising 10M\n"); 9511 } 9512 9513 /* Only 10/100 are allowed to work in FORCE mode */ 9514 if ((phy->req_line_speed == SPEED_100) && 9515 (phy->supported & 9516 (SUPPORTED_100baseT_Half | 9517 SUPPORTED_100baseT_Full))) { 9518 autoneg_val |= (1<<13); 9519 /* Enabled AUTO-MDIX when autoneg is disabled */ 9520 bnx2x_cl45_write(bp, phy, 9521 MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL, 9522 (1<<15 | 1<<9 | 7<<0)); 9523 /* The PHY needs this set even for forced link. */ 9524 an_10_100_val |= (1<<8) | (1<<7); 9525 DP(NETIF_MSG_LINK, "Setting 100M force\n"); 9526 } 9527 if ((phy->req_line_speed == SPEED_10) && 9528 (phy->supported & 9529 (SUPPORTED_10baseT_Half | 9530 SUPPORTED_10baseT_Full))) { 9531 /* Enabled AUTO-MDIX when autoneg is disabled */ 9532 bnx2x_cl45_write(bp, phy, 9533 MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL, 9534 (1<<15 | 1<<9 | 7<<0)); 9535 DP(NETIF_MSG_LINK, "Setting 10M force\n"); 9536 } 9537 9538 bnx2x_cl45_write(bp, phy, 9539 MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_AN_ADV, 9540 an_10_100_val); 9541 9542 if (phy->req_duplex == DUPLEX_FULL) 9543 autoneg_val |= (1<<8); 9544 9545 /* Always write this if this is not 84833. 9546 * For 84833, write it only when it's a forced speed. 9547 */ 9548 if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) || 9549 ((autoneg_val & (1<<12)) == 0)) 9550 bnx2x_cl45_write(bp, phy, 9551 MDIO_AN_DEVAD, 9552 MDIO_AN_REG_8481_LEGACY_MII_CTRL, autoneg_val); 9553 9554 if (((phy->req_line_speed == SPEED_AUTO_NEG) && 9555 (phy->speed_cap_mask & 9556 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) || 9557 (phy->req_line_speed == SPEED_10000)) { 9558 DP(NETIF_MSG_LINK, "Advertising 10G\n"); 9559 /* Restart autoneg for 10G*/ 9560 9561 bnx2x_cl45_read(bp, phy, 9562 MDIO_AN_DEVAD, 9563 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL, 9564 &an_10g_val); 9565 bnx2x_cl45_write(bp, phy, 9566 MDIO_AN_DEVAD, 9567 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL, 9568 an_10g_val | 0x1000); 9569 bnx2x_cl45_write(bp, phy, 9570 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 9571 0x3200); 9572 } else 9573 bnx2x_cl45_write(bp, phy, 9574 MDIO_AN_DEVAD, 9575 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL, 9576 1); 9577 9578 return 0; 9579 } 9580 9581 static int bnx2x_8481_config_init(struct bnx2x_phy *phy, 9582 struct link_params *params, 9583 struct link_vars *vars) 9584 { 9585 struct bnx2x *bp = params->bp; 9586 /* Restore normal power mode*/ 9587 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 9588 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); 9589 9590 /* HW reset */ 9591 bnx2x_ext_phy_hw_reset(bp, params->port); 9592 bnx2x_wait_reset_complete(bp, phy, params); 9593 9594 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15); 9595 return bnx2x_848xx_cmn_config_init(phy, params, vars); 9596 } 9597 9598 #define PHY84833_CMDHDLR_WAIT 300 9599 #define PHY84833_CMDHDLR_MAX_ARGS 5 9600 static int bnx2x_84833_cmd_hdlr(struct bnx2x_phy *phy, 9601 struct link_params *params, 9602 u16 fw_cmd, 9603 u16 cmd_args[], int argc) 9604 { 9605 int idx; 9606 u16 val; 9607 struct bnx2x *bp = params->bp; 9608 /* Write CMD_OPEN_OVERRIDE to STATUS reg */ 9609 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, 9610 MDIO_84833_CMD_HDLR_STATUS, 9611 PHY84833_STATUS_CMD_OPEN_OVERRIDE); 9612 for (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) { 9613 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 9614 MDIO_84833_CMD_HDLR_STATUS, &val); 9615 if (val == PHY84833_STATUS_CMD_OPEN_FOR_CMDS) 9616 break; 9617 usleep_range(1000, 2000); 9618 } 9619 if (idx >= PHY84833_CMDHDLR_WAIT) { 9620 DP(NETIF_MSG_LINK, "FW cmd: FW not ready.\n"); 9621 return -EINVAL; 9622 } 9623 9624 /* Prepare argument(s) and issue command */ 9625 for (idx = 0; idx < argc; idx++) { 9626 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, 9627 MDIO_84833_CMD_HDLR_DATA1 + idx, 9628 cmd_args[idx]); 9629 } 9630 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, 9631 MDIO_84833_CMD_HDLR_COMMAND, fw_cmd); 9632 for (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) { 9633 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 9634 MDIO_84833_CMD_HDLR_STATUS, &val); 9635 if ((val == PHY84833_STATUS_CMD_COMPLETE_PASS) || 9636 (val == PHY84833_STATUS_CMD_COMPLETE_ERROR)) 9637 break; 9638 usleep_range(1000, 2000); 9639 } 9640 if ((idx >= PHY84833_CMDHDLR_WAIT) || 9641 (val == PHY84833_STATUS_CMD_COMPLETE_ERROR)) { 9642 DP(NETIF_MSG_LINK, "FW cmd failed.\n"); 9643 return -EINVAL; 9644 } 9645 /* Gather returning data */ 9646 for (idx = 0; idx < argc; idx++) { 9647 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 9648 MDIO_84833_CMD_HDLR_DATA1 + idx, 9649 &cmd_args[idx]); 9650 } 9651 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, 9652 MDIO_84833_CMD_HDLR_STATUS, 9653 PHY84833_STATUS_CMD_CLEAR_COMPLETE); 9654 return 0; 9655 } 9656 9657 9658 static int bnx2x_84833_pair_swap_cfg(struct bnx2x_phy *phy, 9659 struct link_params *params, 9660 struct link_vars *vars) 9661 { 9662 u32 pair_swap; 9663 u16 data[PHY84833_CMDHDLR_MAX_ARGS]; 9664 int status; 9665 struct bnx2x *bp = params->bp; 9666 9667 /* Check for configuration. */ 9668 pair_swap = REG_RD(bp, params->shmem_base + 9669 offsetof(struct shmem_region, 9670 dev_info.port_hw_config[params->port].xgbt_phy_cfg)) & 9671 PORT_HW_CFG_RJ45_PAIR_SWAP_MASK; 9672 9673 if (pair_swap == 0) 9674 return 0; 9675 9676 /* Only the second argument is used for this command */ 9677 data[1] = (u16)pair_swap; 9678 9679 status = bnx2x_84833_cmd_hdlr(phy, params, 9680 PHY84833_CMD_SET_PAIR_SWAP, data, PHY84833_CMDHDLR_MAX_ARGS); 9681 if (status == 0) 9682 DP(NETIF_MSG_LINK, "Pairswap OK, val=0x%x\n", data[1]); 9683 9684 return status; 9685 } 9686 9687 static u8 bnx2x_84833_get_reset_gpios(struct bnx2x *bp, 9688 u32 shmem_base_path[], 9689 u32 chip_id) 9690 { 9691 u32 reset_pin[2]; 9692 u32 idx; 9693 u8 reset_gpios; 9694 if (CHIP_IS_E3(bp)) { 9695 /* Assume that these will be GPIOs, not EPIOs. */ 9696 for (idx = 0; idx < 2; idx++) { 9697 /* Map config param to register bit. */ 9698 reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] + 9699 offsetof(struct shmem_region, 9700 dev_info.port_hw_config[0].e3_cmn_pin_cfg)); 9701 reset_pin[idx] = (reset_pin[idx] & 9702 PORT_HW_CFG_E3_PHY_RESET_MASK) >> 9703 PORT_HW_CFG_E3_PHY_RESET_SHIFT; 9704 reset_pin[idx] -= PIN_CFG_GPIO0_P0; 9705 reset_pin[idx] = (1 << reset_pin[idx]); 9706 } 9707 reset_gpios = (u8)(reset_pin[0] | reset_pin[1]); 9708 } else { 9709 /* E2, look from diff place of shmem. */ 9710 for (idx = 0; idx < 2; idx++) { 9711 reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] + 9712 offsetof(struct shmem_region, 9713 dev_info.port_hw_config[0].default_cfg)); 9714 reset_pin[idx] &= PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK; 9715 reset_pin[idx] -= PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0; 9716 reset_pin[idx] >>= PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT; 9717 reset_pin[idx] = (1 << reset_pin[idx]); 9718 } 9719 reset_gpios = (u8)(reset_pin[0] | reset_pin[1]); 9720 } 9721 9722 return reset_gpios; 9723 } 9724 9725 static int bnx2x_84833_hw_reset_phy(struct bnx2x_phy *phy, 9726 struct link_params *params) 9727 { 9728 struct bnx2x *bp = params->bp; 9729 u8 reset_gpios; 9730 u32 other_shmem_base_addr = REG_RD(bp, params->shmem2_base + 9731 offsetof(struct shmem2_region, 9732 other_shmem_base_addr)); 9733 9734 u32 shmem_base_path[2]; 9735 9736 /* Work around for 84833 LED failure inside RESET status */ 9737 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, 9738 MDIO_AN_REG_8481_LEGACY_MII_CTRL, 9739 MDIO_AN_REG_8481_MII_CTRL_FORCE_1G); 9740 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, 9741 MDIO_AN_REG_8481_1G_100T_EXT_CTRL, 9742 MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF); 9743 9744 shmem_base_path[0] = params->shmem_base; 9745 shmem_base_path[1] = other_shmem_base_addr; 9746 9747 reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path, 9748 params->chip_id); 9749 9750 bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW); 9751 udelay(10); 9752 DP(NETIF_MSG_LINK, "84833 hw reset on pin values 0x%x\n", 9753 reset_gpios); 9754 9755 return 0; 9756 } 9757 9758 static int bnx2x_8483x_disable_eee(struct bnx2x_phy *phy, 9759 struct link_params *params, 9760 struct link_vars *vars) 9761 { 9762 int rc; 9763 struct bnx2x *bp = params->bp; 9764 u16 cmd_args = 0; 9765 9766 DP(NETIF_MSG_LINK, "Don't Advertise 10GBase-T EEE\n"); 9767 9768 /* Prevent Phy from working in EEE and advertising it */ 9769 rc = bnx2x_84833_cmd_hdlr(phy, params, 9770 PHY84833_CMD_SET_EEE_MODE, &cmd_args, 1); 9771 if (rc) { 9772 DP(NETIF_MSG_LINK, "EEE disable failed.\n"); 9773 return rc; 9774 } 9775 9776 return bnx2x_eee_disable(phy, params, vars); 9777 } 9778 9779 static int bnx2x_8483x_enable_eee(struct bnx2x_phy *phy, 9780 struct link_params *params, 9781 struct link_vars *vars) 9782 { 9783 int rc; 9784 struct bnx2x *bp = params->bp; 9785 u16 cmd_args = 1; 9786 9787 rc = bnx2x_84833_cmd_hdlr(phy, params, 9788 PHY84833_CMD_SET_EEE_MODE, &cmd_args, 1); 9789 if (rc) { 9790 DP(NETIF_MSG_LINK, "EEE enable failed.\n"); 9791 return rc; 9792 } 9793 9794 return bnx2x_eee_advertise(phy, params, vars, SHMEM_EEE_10G_ADV); 9795 } 9796 9797 #define PHY84833_CONSTANT_LATENCY 1193 9798 static int bnx2x_848x3_config_init(struct bnx2x_phy *phy, 9799 struct link_params *params, 9800 struct link_vars *vars) 9801 { 9802 struct bnx2x *bp = params->bp; 9803 u8 port, initialize = 1; 9804 u16 val; 9805 u32 actual_phy_selection, cms_enable; 9806 u16 cmd_args[PHY84833_CMDHDLR_MAX_ARGS]; 9807 int rc = 0; 9808 9809 usleep_range(1000, 2000); 9810 9811 if (!(CHIP_IS_E1x(bp))) 9812 port = BP_PATH(bp); 9813 else 9814 port = params->port; 9815 9816 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) { 9817 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3, 9818 MISC_REGISTERS_GPIO_OUTPUT_HIGH, 9819 port); 9820 } else { 9821 /* MDIO reset */ 9822 bnx2x_cl45_write(bp, phy, 9823 MDIO_PMA_DEVAD, 9824 MDIO_PMA_REG_CTRL, 0x8000); 9825 } 9826 9827 bnx2x_wait_reset_complete(bp, phy, params); 9828 9829 /* Wait for GPHY to come out of reset */ 9830 msleep(50); 9831 if (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) { 9832 /* BCM84823 requires that XGXS links up first @ 10G for normal 9833 * behavior. 9834 */ 9835 u16 temp; 9836 temp = vars->line_speed; 9837 vars->line_speed = SPEED_10000; 9838 bnx2x_set_autoneg(¶ms->phy[INT_PHY], params, vars, 0); 9839 bnx2x_program_serdes(¶ms->phy[INT_PHY], params, vars); 9840 vars->line_speed = temp; 9841 } 9842 9843 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 9844 MDIO_CTL_REG_84823_MEDIA, &val); 9845 val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK | 9846 MDIO_CTL_REG_84823_MEDIA_LINE_MASK | 9847 MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN | 9848 MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK | 9849 MDIO_CTL_REG_84823_MEDIA_FIBER_1G); 9850 9851 if (CHIP_IS_E3(bp)) { 9852 val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK | 9853 MDIO_CTL_REG_84823_MEDIA_LINE_MASK); 9854 } else { 9855 val |= (MDIO_CTL_REG_84823_CTRL_MAC_XFI | 9856 MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L); 9857 } 9858 9859 actual_phy_selection = bnx2x_phy_selection(params); 9860 9861 switch (actual_phy_selection) { 9862 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT: 9863 /* Do nothing. Essentially this is like the priority copper */ 9864 break; 9865 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY: 9866 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER; 9867 break; 9868 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY: 9869 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER; 9870 break; 9871 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY: 9872 /* Do nothing here. The first PHY won't be initialized at all */ 9873 break; 9874 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY: 9875 val |= MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN; 9876 initialize = 0; 9877 break; 9878 } 9879 if (params->phy[EXT_PHY2].req_line_speed == SPEED_1000) 9880 val |= MDIO_CTL_REG_84823_MEDIA_FIBER_1G; 9881 9882 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, 9883 MDIO_CTL_REG_84823_MEDIA, val); 9884 DP(NETIF_MSG_LINK, "Multi_phy config = 0x%x, Media control = 0x%x\n", 9885 params->multi_phy_config, val); 9886 9887 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) { 9888 bnx2x_84833_pair_swap_cfg(phy, params, vars); 9889 9890 /* Keep AutogrEEEn disabled. */ 9891 cmd_args[0] = 0x0; 9892 cmd_args[1] = 0x0; 9893 cmd_args[2] = PHY84833_CONSTANT_LATENCY + 1; 9894 cmd_args[3] = PHY84833_CONSTANT_LATENCY; 9895 rc = bnx2x_84833_cmd_hdlr(phy, params, 9896 PHY84833_CMD_SET_EEE_MODE, cmd_args, 9897 PHY84833_CMDHDLR_MAX_ARGS); 9898 if (rc) 9899 DP(NETIF_MSG_LINK, "Cfg AutogrEEEn failed.\n"); 9900 } 9901 if (initialize) 9902 rc = bnx2x_848xx_cmn_config_init(phy, params, vars); 9903 else 9904 bnx2x_save_848xx_spirom_version(phy, bp, params->port); 9905 /* 84833 PHY has a better feature and doesn't need to support this. */ 9906 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) { 9907 cms_enable = REG_RD(bp, params->shmem_base + 9908 offsetof(struct shmem_region, 9909 dev_info.port_hw_config[params->port].default_cfg)) & 9910 PORT_HW_CFG_ENABLE_CMS_MASK; 9911 9912 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 9913 MDIO_CTL_REG_84823_USER_CTRL_REG, &val); 9914 if (cms_enable) 9915 val |= MDIO_CTL_REG_84823_USER_CTRL_CMS; 9916 else 9917 val &= ~MDIO_CTL_REG_84823_USER_CTRL_CMS; 9918 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, 9919 MDIO_CTL_REG_84823_USER_CTRL_REG, val); 9920 } 9921 9922 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 9923 MDIO_84833_TOP_CFG_FW_REV, &val); 9924 9925 /* Configure EEE support */ 9926 if ((val >= MDIO_84833_TOP_CFG_FW_EEE) && 9927 (val != MDIO_84833_TOP_CFG_FW_NO_EEE) && 9928 bnx2x_eee_has_cap(params)) { 9929 rc = bnx2x_eee_initial_config(params, vars, SHMEM_EEE_10G_ADV); 9930 if (rc) { 9931 DP(NETIF_MSG_LINK, "Failed to configure EEE timers\n"); 9932 bnx2x_8483x_disable_eee(phy, params, vars); 9933 return rc; 9934 } 9935 9936 if ((params->req_duplex[actual_phy_selection] == DUPLEX_FULL) && 9937 (params->eee_mode & EEE_MODE_ADV_LPI) && 9938 (bnx2x_eee_calc_timer(params) || 9939 !(params->eee_mode & EEE_MODE_ENABLE_LPI))) 9940 rc = bnx2x_8483x_enable_eee(phy, params, vars); 9941 else 9942 rc = bnx2x_8483x_disable_eee(phy, params, vars); 9943 if (rc) { 9944 DP(NETIF_MSG_LINK, "Failed to set EEE advertisement\n"); 9945 return rc; 9946 } 9947 } else { 9948 vars->eee_status &= ~SHMEM_EEE_SUPPORTED_MASK; 9949 } 9950 9951 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) { 9952 /* Bring PHY out of super isolate mode as the final step. */ 9953 bnx2x_cl45_read(bp, phy, 9954 MDIO_CTL_DEVAD, 9955 MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val); 9956 val &= ~MDIO_84833_SUPER_ISOLATE; 9957 bnx2x_cl45_write(bp, phy, 9958 MDIO_CTL_DEVAD, 9959 MDIO_84833_TOP_CFG_XGPHY_STRAP1, val); 9960 } 9961 return rc; 9962 } 9963 9964 static u8 bnx2x_848xx_read_status(struct bnx2x_phy *phy, 9965 struct link_params *params, 9966 struct link_vars *vars) 9967 { 9968 struct bnx2x *bp = params->bp; 9969 u16 val, val1, val2; 9970 u8 link_up = 0; 9971 9972 9973 /* Check 10G-BaseT link status */ 9974 /* Check PMD signal ok */ 9975 bnx2x_cl45_read(bp, phy, 9976 MDIO_AN_DEVAD, 0xFFFA, &val1); 9977 bnx2x_cl45_read(bp, phy, 9978 MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_PMD_SIGNAL, 9979 &val2); 9980 DP(NETIF_MSG_LINK, "BCM848xx: PMD_SIGNAL 1.a811 = 0x%x\n", val2); 9981 9982 /* Check link 10G */ 9983 if (val2 & (1<<11)) { 9984 vars->line_speed = SPEED_10000; 9985 vars->duplex = DUPLEX_FULL; 9986 link_up = 1; 9987 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars); 9988 } else { /* Check Legacy speed link */ 9989 u16 legacy_status, legacy_speed; 9990 9991 /* Enable expansion register 0x42 (Operation mode status) */ 9992 bnx2x_cl45_write(bp, phy, 9993 MDIO_AN_DEVAD, 9994 MDIO_AN_REG_8481_EXPANSION_REG_ACCESS, 0xf42); 9995 9996 /* Get legacy speed operation status */ 9997 bnx2x_cl45_read(bp, phy, 9998 MDIO_AN_DEVAD, 9999 MDIO_AN_REG_8481_EXPANSION_REG_RD_RW, 10000 &legacy_status); 10001 10002 DP(NETIF_MSG_LINK, "Legacy speed status = 0x%x\n", 10003 legacy_status); 10004 link_up = ((legacy_status & (1<<11)) == (1<<11)); 10005 legacy_speed = (legacy_status & (3<<9)); 10006 if (legacy_speed == (0<<9)) 10007 vars->line_speed = SPEED_10; 10008 else if (legacy_speed == (1<<9)) 10009 vars->line_speed = SPEED_100; 10010 else if (legacy_speed == (2<<9)) 10011 vars->line_speed = SPEED_1000; 10012 else { /* Should not happen: Treat as link down */ 10013 vars->line_speed = 0; 10014 link_up = 0; 10015 } 10016 10017 if (link_up) { 10018 if (legacy_status & (1<<8)) 10019 vars->duplex = DUPLEX_FULL; 10020 else 10021 vars->duplex = DUPLEX_HALF; 10022 10023 DP(NETIF_MSG_LINK, 10024 "Link is up in %dMbps, is_duplex_full= %d\n", 10025 vars->line_speed, 10026 (vars->duplex == DUPLEX_FULL)); 10027 /* Check legacy speed AN resolution */ 10028 bnx2x_cl45_read(bp, phy, 10029 MDIO_AN_DEVAD, 10030 MDIO_AN_REG_8481_LEGACY_MII_STATUS, 10031 &val); 10032 if (val & (1<<5)) 10033 vars->link_status |= 10034 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; 10035 bnx2x_cl45_read(bp, phy, 10036 MDIO_AN_DEVAD, 10037 MDIO_AN_REG_8481_LEGACY_AN_EXPANSION, 10038 &val); 10039 if ((val & (1<<0)) == 0) 10040 vars->link_status |= 10041 LINK_STATUS_PARALLEL_DETECTION_USED; 10042 } 10043 } 10044 if (link_up) { 10045 DP(NETIF_MSG_LINK, "BCM848x3: link speed is %d\n", 10046 vars->line_speed); 10047 bnx2x_ext_phy_resolve_fc(phy, params, vars); 10048 10049 /* Read LP advertised speeds */ 10050 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, 10051 MDIO_AN_REG_CL37_FC_LP, &val); 10052 if (val & (1<<5)) 10053 vars->link_status |= 10054 LINK_STATUS_LINK_PARTNER_10THD_CAPABLE; 10055 if (val & (1<<6)) 10056 vars->link_status |= 10057 LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE; 10058 if (val & (1<<7)) 10059 vars->link_status |= 10060 LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE; 10061 if (val & (1<<8)) 10062 vars->link_status |= 10063 LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE; 10064 if (val & (1<<9)) 10065 vars->link_status |= 10066 LINK_STATUS_LINK_PARTNER_100T4_CAPABLE; 10067 10068 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, 10069 MDIO_AN_REG_1000T_STATUS, &val); 10070 10071 if (val & (1<<10)) 10072 vars->link_status |= 10073 LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE; 10074 if (val & (1<<11)) 10075 vars->link_status |= 10076 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; 10077 10078 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, 10079 MDIO_AN_REG_MASTER_STATUS, &val); 10080 10081 if (val & (1<<11)) 10082 vars->link_status |= 10083 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; 10084 10085 /* Determine if EEE was negotiated */ 10086 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) 10087 bnx2x_eee_an_resolve(phy, params, vars); 10088 } 10089 10090 return link_up; 10091 } 10092 10093 10094 static int bnx2x_848xx_format_ver(u32 raw_ver, u8 *str, u16 *len) 10095 { 10096 int status = 0; 10097 u32 spirom_ver; 10098 spirom_ver = ((raw_ver & 0xF80) >> 7) << 16 | (raw_ver & 0x7F); 10099 status = bnx2x_format_ver(spirom_ver, str, len); 10100 return status; 10101 } 10102 10103 static void bnx2x_8481_hw_reset(struct bnx2x_phy *phy, 10104 struct link_params *params) 10105 { 10106 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1, 10107 MISC_REGISTERS_GPIO_OUTPUT_LOW, 0); 10108 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1, 10109 MISC_REGISTERS_GPIO_OUTPUT_LOW, 1); 10110 } 10111 10112 static void bnx2x_8481_link_reset(struct bnx2x_phy *phy, 10113 struct link_params *params) 10114 { 10115 bnx2x_cl45_write(params->bp, phy, 10116 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000); 10117 bnx2x_cl45_write(params->bp, phy, 10118 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1); 10119 } 10120 10121 static void bnx2x_848x3_link_reset(struct bnx2x_phy *phy, 10122 struct link_params *params) 10123 { 10124 struct bnx2x *bp = params->bp; 10125 u8 port; 10126 u16 val16; 10127 10128 if (!(CHIP_IS_E1x(bp))) 10129 port = BP_PATH(bp); 10130 else 10131 port = params->port; 10132 10133 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) { 10134 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3, 10135 MISC_REGISTERS_GPIO_OUTPUT_LOW, 10136 port); 10137 } else { 10138 bnx2x_cl45_read(bp, phy, 10139 MDIO_CTL_DEVAD, 10140 MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val16); 10141 val16 |= MDIO_84833_SUPER_ISOLATE; 10142 bnx2x_cl45_write(bp, phy, 10143 MDIO_CTL_DEVAD, 10144 MDIO_84833_TOP_CFG_XGPHY_STRAP1, val16); 10145 } 10146 } 10147 10148 static void bnx2x_848xx_set_link_led(struct bnx2x_phy *phy, 10149 struct link_params *params, u8 mode) 10150 { 10151 struct bnx2x *bp = params->bp; 10152 u16 val; 10153 u8 port; 10154 10155 if (!(CHIP_IS_E1x(bp))) 10156 port = BP_PATH(bp); 10157 else 10158 port = params->port; 10159 10160 switch (mode) { 10161 case LED_MODE_OFF: 10162 10163 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OFF\n", port); 10164 10165 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) == 10166 SHARED_HW_CFG_LED_EXTPHY1) { 10167 10168 /* Set LED masks */ 10169 bnx2x_cl45_write(bp, phy, 10170 MDIO_PMA_DEVAD, 10171 MDIO_PMA_REG_8481_LED1_MASK, 10172 0x0); 10173 10174 bnx2x_cl45_write(bp, phy, 10175 MDIO_PMA_DEVAD, 10176 MDIO_PMA_REG_8481_LED2_MASK, 10177 0x0); 10178 10179 bnx2x_cl45_write(bp, phy, 10180 MDIO_PMA_DEVAD, 10181 MDIO_PMA_REG_8481_LED3_MASK, 10182 0x0); 10183 10184 bnx2x_cl45_write(bp, phy, 10185 MDIO_PMA_DEVAD, 10186 MDIO_PMA_REG_8481_LED5_MASK, 10187 0x0); 10188 10189 } else { 10190 bnx2x_cl45_write(bp, phy, 10191 MDIO_PMA_DEVAD, 10192 MDIO_PMA_REG_8481_LED1_MASK, 10193 0x0); 10194 } 10195 break; 10196 case LED_MODE_FRONT_PANEL_OFF: 10197 10198 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE FRONT PANEL OFF\n", 10199 port); 10200 10201 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) == 10202 SHARED_HW_CFG_LED_EXTPHY1) { 10203 10204 /* Set LED masks */ 10205 bnx2x_cl45_write(bp, phy, 10206 MDIO_PMA_DEVAD, 10207 MDIO_PMA_REG_8481_LED1_MASK, 10208 0x0); 10209 10210 bnx2x_cl45_write(bp, phy, 10211 MDIO_PMA_DEVAD, 10212 MDIO_PMA_REG_8481_LED2_MASK, 10213 0x0); 10214 10215 bnx2x_cl45_write(bp, phy, 10216 MDIO_PMA_DEVAD, 10217 MDIO_PMA_REG_8481_LED3_MASK, 10218 0x0); 10219 10220 bnx2x_cl45_write(bp, phy, 10221 MDIO_PMA_DEVAD, 10222 MDIO_PMA_REG_8481_LED5_MASK, 10223 0x20); 10224 10225 } else { 10226 bnx2x_cl45_write(bp, phy, 10227 MDIO_PMA_DEVAD, 10228 MDIO_PMA_REG_8481_LED1_MASK, 10229 0x0); 10230 } 10231 break; 10232 case LED_MODE_ON: 10233 10234 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE ON\n", port); 10235 10236 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) == 10237 SHARED_HW_CFG_LED_EXTPHY1) { 10238 /* Set control reg */ 10239 bnx2x_cl45_read(bp, phy, 10240 MDIO_PMA_DEVAD, 10241 MDIO_PMA_REG_8481_LINK_SIGNAL, 10242 &val); 10243 val &= 0x8000; 10244 val |= 0x2492; 10245 10246 bnx2x_cl45_write(bp, phy, 10247 MDIO_PMA_DEVAD, 10248 MDIO_PMA_REG_8481_LINK_SIGNAL, 10249 val); 10250 10251 /* Set LED masks */ 10252 bnx2x_cl45_write(bp, phy, 10253 MDIO_PMA_DEVAD, 10254 MDIO_PMA_REG_8481_LED1_MASK, 10255 0x0); 10256 10257 bnx2x_cl45_write(bp, phy, 10258 MDIO_PMA_DEVAD, 10259 MDIO_PMA_REG_8481_LED2_MASK, 10260 0x20); 10261 10262 bnx2x_cl45_write(bp, phy, 10263 MDIO_PMA_DEVAD, 10264 MDIO_PMA_REG_8481_LED3_MASK, 10265 0x20); 10266 10267 bnx2x_cl45_write(bp, phy, 10268 MDIO_PMA_DEVAD, 10269 MDIO_PMA_REG_8481_LED5_MASK, 10270 0x0); 10271 } else { 10272 bnx2x_cl45_write(bp, phy, 10273 MDIO_PMA_DEVAD, 10274 MDIO_PMA_REG_8481_LED1_MASK, 10275 0x20); 10276 } 10277 break; 10278 10279 case LED_MODE_OPER: 10280 10281 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OPER\n", port); 10282 10283 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) == 10284 SHARED_HW_CFG_LED_EXTPHY1) { 10285 10286 /* Set control reg */ 10287 bnx2x_cl45_read(bp, phy, 10288 MDIO_PMA_DEVAD, 10289 MDIO_PMA_REG_8481_LINK_SIGNAL, 10290 &val); 10291 10292 if (!((val & 10293 MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK) 10294 >> MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT)) { 10295 DP(NETIF_MSG_LINK, "Setting LINK_SIGNAL\n"); 10296 bnx2x_cl45_write(bp, phy, 10297 MDIO_PMA_DEVAD, 10298 MDIO_PMA_REG_8481_LINK_SIGNAL, 10299 0xa492); 10300 } 10301 10302 /* Set LED masks */ 10303 bnx2x_cl45_write(bp, phy, 10304 MDIO_PMA_DEVAD, 10305 MDIO_PMA_REG_8481_LED1_MASK, 10306 0x10); 10307 10308 bnx2x_cl45_write(bp, phy, 10309 MDIO_PMA_DEVAD, 10310 MDIO_PMA_REG_8481_LED2_MASK, 10311 0x80); 10312 10313 bnx2x_cl45_write(bp, phy, 10314 MDIO_PMA_DEVAD, 10315 MDIO_PMA_REG_8481_LED3_MASK, 10316 0x98); 10317 10318 bnx2x_cl45_write(bp, phy, 10319 MDIO_PMA_DEVAD, 10320 MDIO_PMA_REG_8481_LED5_MASK, 10321 0x40); 10322 10323 } else { 10324 bnx2x_cl45_write(bp, phy, 10325 MDIO_PMA_DEVAD, 10326 MDIO_PMA_REG_8481_LED1_MASK, 10327 0x80); 10328 10329 /* Tell LED3 to blink on source */ 10330 bnx2x_cl45_read(bp, phy, 10331 MDIO_PMA_DEVAD, 10332 MDIO_PMA_REG_8481_LINK_SIGNAL, 10333 &val); 10334 val &= ~(7<<6); 10335 val |= (1<<6); /* A83B[8:6]= 1 */ 10336 bnx2x_cl45_write(bp, phy, 10337 MDIO_PMA_DEVAD, 10338 MDIO_PMA_REG_8481_LINK_SIGNAL, 10339 val); 10340 } 10341 break; 10342 } 10343 10344 /* This is a workaround for E3+84833 until autoneg 10345 * restart is fixed in f/w 10346 */ 10347 if (CHIP_IS_E3(bp)) { 10348 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 10349 MDIO_WC_REG_GP2_STATUS_GP_2_1, &val); 10350 } 10351 } 10352 10353 /******************************************************************/ 10354 /* 54618SE PHY SECTION */ 10355 /******************************************************************/ 10356 static void bnx2x_54618se_specific_func(struct bnx2x_phy *phy, 10357 struct link_params *params, 10358 u32 action) 10359 { 10360 struct bnx2x *bp = params->bp; 10361 u16 temp; 10362 switch (action) { 10363 case PHY_INIT: 10364 /* Configure LED4: set to INTR (0x6). */ 10365 /* Accessing shadow register 0xe. */ 10366 bnx2x_cl22_write(bp, phy, 10367 MDIO_REG_GPHY_SHADOW, 10368 MDIO_REG_GPHY_SHADOW_LED_SEL2); 10369 bnx2x_cl22_read(bp, phy, 10370 MDIO_REG_GPHY_SHADOW, 10371 &temp); 10372 temp &= ~(0xf << 4); 10373 temp |= (0x6 << 4); 10374 bnx2x_cl22_write(bp, phy, 10375 MDIO_REG_GPHY_SHADOW, 10376 MDIO_REG_GPHY_SHADOW_WR_ENA | temp); 10377 /* Configure INTR based on link status change. */ 10378 bnx2x_cl22_write(bp, phy, 10379 MDIO_REG_INTR_MASK, 10380 ~MDIO_REG_INTR_MASK_LINK_STATUS); 10381 break; 10382 } 10383 } 10384 10385 static int bnx2x_54618se_config_init(struct bnx2x_phy *phy, 10386 struct link_params *params, 10387 struct link_vars *vars) 10388 { 10389 struct bnx2x *bp = params->bp; 10390 u8 port; 10391 u16 autoneg_val, an_1000_val, an_10_100_val, fc_val, temp; 10392 u32 cfg_pin; 10393 10394 DP(NETIF_MSG_LINK, "54618SE cfg init\n"); 10395 usleep_range(1000, 2000); 10396 10397 /* This works with E3 only, no need to check the chip 10398 * before determining the port. 10399 */ 10400 port = params->port; 10401 10402 cfg_pin = (REG_RD(bp, params->shmem_base + 10403 offsetof(struct shmem_region, 10404 dev_info.port_hw_config[port].e3_cmn_pin_cfg)) & 10405 PORT_HW_CFG_E3_PHY_RESET_MASK) >> 10406 PORT_HW_CFG_E3_PHY_RESET_SHIFT; 10407 10408 /* Drive pin high to bring the GPHY out of reset. */ 10409 bnx2x_set_cfg_pin(bp, cfg_pin, 1); 10410 10411 /* wait for GPHY to reset */ 10412 msleep(50); 10413 10414 /* reset phy */ 10415 bnx2x_cl22_write(bp, phy, 10416 MDIO_PMA_REG_CTRL, 0x8000); 10417 bnx2x_wait_reset_complete(bp, phy, params); 10418 10419 /* Wait for GPHY to reset */ 10420 msleep(50); 10421 10422 10423 bnx2x_54618se_specific_func(phy, params, PHY_INIT); 10424 /* Flip the signal detect polarity (set 0x1c.0x1e[8]). */ 10425 bnx2x_cl22_write(bp, phy, 10426 MDIO_REG_GPHY_SHADOW, 10427 MDIO_REG_GPHY_SHADOW_AUTO_DET_MED); 10428 bnx2x_cl22_read(bp, phy, 10429 MDIO_REG_GPHY_SHADOW, 10430 &temp); 10431 temp |= MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD; 10432 bnx2x_cl22_write(bp, phy, 10433 MDIO_REG_GPHY_SHADOW, 10434 MDIO_REG_GPHY_SHADOW_WR_ENA | temp); 10435 10436 /* Set up fc */ 10437 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */ 10438 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); 10439 fc_val = 0; 10440 if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) == 10441 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) 10442 fc_val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC; 10443 10444 if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) == 10445 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) 10446 fc_val |= MDIO_AN_REG_ADV_PAUSE_PAUSE; 10447 10448 /* Read all advertisement */ 10449 bnx2x_cl22_read(bp, phy, 10450 0x09, 10451 &an_1000_val); 10452 10453 bnx2x_cl22_read(bp, phy, 10454 0x04, 10455 &an_10_100_val); 10456 10457 bnx2x_cl22_read(bp, phy, 10458 MDIO_PMA_REG_CTRL, 10459 &autoneg_val); 10460 10461 /* Disable forced speed */ 10462 autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13)); 10463 an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8) | (1<<10) | 10464 (1<<11)); 10465 10466 if (((phy->req_line_speed == SPEED_AUTO_NEG) && 10467 (phy->speed_cap_mask & 10468 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) || 10469 (phy->req_line_speed == SPEED_1000)) { 10470 an_1000_val |= (1<<8); 10471 autoneg_val |= (1<<9 | 1<<12); 10472 if (phy->req_duplex == DUPLEX_FULL) 10473 an_1000_val |= (1<<9); 10474 DP(NETIF_MSG_LINK, "Advertising 1G\n"); 10475 } else 10476 an_1000_val &= ~((1<<8) | (1<<9)); 10477 10478 bnx2x_cl22_write(bp, phy, 10479 0x09, 10480 an_1000_val); 10481 bnx2x_cl22_read(bp, phy, 10482 0x09, 10483 &an_1000_val); 10484 10485 /* Set 100 speed advertisement */ 10486 if (((phy->req_line_speed == SPEED_AUTO_NEG) && 10487 (phy->speed_cap_mask & 10488 (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL | 10489 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)))) { 10490 an_10_100_val |= (1<<7); 10491 /* Enable autoneg and restart autoneg for legacy speeds */ 10492 autoneg_val |= (1<<9 | 1<<12); 10493 10494 if (phy->req_duplex == DUPLEX_FULL) 10495 an_10_100_val |= (1<<8); 10496 DP(NETIF_MSG_LINK, "Advertising 100M\n"); 10497 } 10498 10499 /* Set 10 speed advertisement */ 10500 if (((phy->req_line_speed == SPEED_AUTO_NEG) && 10501 (phy->speed_cap_mask & 10502 (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL | 10503 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)))) { 10504 an_10_100_val |= (1<<5); 10505 autoneg_val |= (1<<9 | 1<<12); 10506 if (phy->req_duplex == DUPLEX_FULL) 10507 an_10_100_val |= (1<<6); 10508 DP(NETIF_MSG_LINK, "Advertising 10M\n"); 10509 } 10510 10511 /* Only 10/100 are allowed to work in FORCE mode */ 10512 if (phy->req_line_speed == SPEED_100) { 10513 autoneg_val |= (1<<13); 10514 /* Enabled AUTO-MDIX when autoneg is disabled */ 10515 bnx2x_cl22_write(bp, phy, 10516 0x18, 10517 (1<<15 | 1<<9 | 7<<0)); 10518 DP(NETIF_MSG_LINK, "Setting 100M force\n"); 10519 } 10520 if (phy->req_line_speed == SPEED_10) { 10521 /* Enabled AUTO-MDIX when autoneg is disabled */ 10522 bnx2x_cl22_write(bp, phy, 10523 0x18, 10524 (1<<15 | 1<<9 | 7<<0)); 10525 DP(NETIF_MSG_LINK, "Setting 10M force\n"); 10526 } 10527 10528 if ((phy->flags & FLAGS_EEE) && bnx2x_eee_has_cap(params)) { 10529 int rc; 10530 10531 bnx2x_cl22_write(bp, phy, MDIO_REG_GPHY_EXP_ACCESS, 10532 MDIO_REG_GPHY_EXP_ACCESS_TOP | 10533 MDIO_REG_GPHY_EXP_TOP_2K_BUF); 10534 bnx2x_cl22_read(bp, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, &temp); 10535 temp &= 0xfffe; 10536 bnx2x_cl22_write(bp, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, temp); 10537 10538 rc = bnx2x_eee_initial_config(params, vars, SHMEM_EEE_1G_ADV); 10539 if (rc) { 10540 DP(NETIF_MSG_LINK, "Failed to configure EEE timers\n"); 10541 bnx2x_eee_disable(phy, params, vars); 10542 } else if ((params->eee_mode & EEE_MODE_ADV_LPI) && 10543 (phy->req_duplex == DUPLEX_FULL) && 10544 (bnx2x_eee_calc_timer(params) || 10545 !(params->eee_mode & EEE_MODE_ENABLE_LPI))) { 10546 /* Need to advertise EEE only when requested, 10547 * and either no LPI assertion was requested, 10548 * or it was requested and a valid timer was set. 10549 * Also notice full duplex is required for EEE. 10550 */ 10551 bnx2x_eee_advertise(phy, params, vars, 10552 SHMEM_EEE_1G_ADV); 10553 } else { 10554 DP(NETIF_MSG_LINK, "Don't Advertise 1GBase-T EEE\n"); 10555 bnx2x_eee_disable(phy, params, vars); 10556 } 10557 } else { 10558 vars->eee_status &= ~SHMEM_EEE_1G_ADV << 10559 SHMEM_EEE_SUPPORTED_SHIFT; 10560 10561 if (phy->flags & FLAGS_EEE) { 10562 /* Handle legacy auto-grEEEn */ 10563 if (params->feature_config_flags & 10564 FEATURE_CONFIG_AUTOGREEEN_ENABLED) { 10565 temp = 6; 10566 DP(NETIF_MSG_LINK, "Enabling Auto-GrEEEn\n"); 10567 } else { 10568 temp = 0; 10569 DP(NETIF_MSG_LINK, "Don't Adv. EEE\n"); 10570 } 10571 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, 10572 MDIO_AN_REG_EEE_ADV, temp); 10573 } 10574 } 10575 10576 bnx2x_cl22_write(bp, phy, 10577 0x04, 10578 an_10_100_val | fc_val); 10579 10580 if (phy->req_duplex == DUPLEX_FULL) 10581 autoneg_val |= (1<<8); 10582 10583 bnx2x_cl22_write(bp, phy, 10584 MDIO_PMA_REG_CTRL, autoneg_val); 10585 10586 return 0; 10587 } 10588 10589 10590 static void bnx2x_5461x_set_link_led(struct bnx2x_phy *phy, 10591 struct link_params *params, u8 mode) 10592 { 10593 struct bnx2x *bp = params->bp; 10594 u16 temp; 10595 10596 bnx2x_cl22_write(bp, phy, 10597 MDIO_REG_GPHY_SHADOW, 10598 MDIO_REG_GPHY_SHADOW_LED_SEL1); 10599 bnx2x_cl22_read(bp, phy, 10600 MDIO_REG_GPHY_SHADOW, 10601 &temp); 10602 temp &= 0xff00; 10603 10604 DP(NETIF_MSG_LINK, "54618x set link led (mode=%x)\n", mode); 10605 switch (mode) { 10606 case LED_MODE_FRONT_PANEL_OFF: 10607 case LED_MODE_OFF: 10608 temp |= 0x00ee; 10609 break; 10610 case LED_MODE_OPER: 10611 temp |= 0x0001; 10612 break; 10613 case LED_MODE_ON: 10614 temp |= 0x00ff; 10615 break; 10616 default: 10617 break; 10618 } 10619 bnx2x_cl22_write(bp, phy, 10620 MDIO_REG_GPHY_SHADOW, 10621 MDIO_REG_GPHY_SHADOW_WR_ENA | temp); 10622 return; 10623 } 10624 10625 10626 static void bnx2x_54618se_link_reset(struct bnx2x_phy *phy, 10627 struct link_params *params) 10628 { 10629 struct bnx2x *bp = params->bp; 10630 u32 cfg_pin; 10631 u8 port; 10632 10633 /* In case of no EPIO routed to reset the GPHY, put it 10634 * in low power mode. 10635 */ 10636 bnx2x_cl22_write(bp, phy, MDIO_PMA_REG_CTRL, 0x800); 10637 /* This works with E3 only, no need to check the chip 10638 * before determining the port. 10639 */ 10640 port = params->port; 10641 cfg_pin = (REG_RD(bp, params->shmem_base + 10642 offsetof(struct shmem_region, 10643 dev_info.port_hw_config[port].e3_cmn_pin_cfg)) & 10644 PORT_HW_CFG_E3_PHY_RESET_MASK) >> 10645 PORT_HW_CFG_E3_PHY_RESET_SHIFT; 10646 10647 /* Drive pin low to put GPHY in reset. */ 10648 bnx2x_set_cfg_pin(bp, cfg_pin, 0); 10649 } 10650 10651 static u8 bnx2x_54618se_read_status(struct bnx2x_phy *phy, 10652 struct link_params *params, 10653 struct link_vars *vars) 10654 { 10655 struct bnx2x *bp = params->bp; 10656 u16 val; 10657 u8 link_up = 0; 10658 u16 legacy_status, legacy_speed; 10659 10660 /* Get speed operation status */ 10661 bnx2x_cl22_read(bp, phy, 10662 MDIO_REG_GPHY_AUX_STATUS, 10663 &legacy_status); 10664 DP(NETIF_MSG_LINK, "54618SE read_status: 0x%x\n", legacy_status); 10665 10666 /* Read status to clear the PHY interrupt. */ 10667 bnx2x_cl22_read(bp, phy, 10668 MDIO_REG_INTR_STATUS, 10669 &val); 10670 10671 link_up = ((legacy_status & (1<<2)) == (1<<2)); 10672 10673 if (link_up) { 10674 legacy_speed = (legacy_status & (7<<8)); 10675 if (legacy_speed == (7<<8)) { 10676 vars->line_speed = SPEED_1000; 10677 vars->duplex = DUPLEX_FULL; 10678 } else if (legacy_speed == (6<<8)) { 10679 vars->line_speed = SPEED_1000; 10680 vars->duplex = DUPLEX_HALF; 10681 } else if (legacy_speed == (5<<8)) { 10682 vars->line_speed = SPEED_100; 10683 vars->duplex = DUPLEX_FULL; 10684 } 10685 /* Omitting 100Base-T4 for now */ 10686 else if (legacy_speed == (3<<8)) { 10687 vars->line_speed = SPEED_100; 10688 vars->duplex = DUPLEX_HALF; 10689 } else if (legacy_speed == (2<<8)) { 10690 vars->line_speed = SPEED_10; 10691 vars->duplex = DUPLEX_FULL; 10692 } else if (legacy_speed == (1<<8)) { 10693 vars->line_speed = SPEED_10; 10694 vars->duplex = DUPLEX_HALF; 10695 } else /* Should not happen */ 10696 vars->line_speed = 0; 10697 10698 DP(NETIF_MSG_LINK, 10699 "Link is up in %dMbps, is_duplex_full= %d\n", 10700 vars->line_speed, 10701 (vars->duplex == DUPLEX_FULL)); 10702 10703 /* Check legacy speed AN resolution */ 10704 bnx2x_cl22_read(bp, phy, 10705 0x01, 10706 &val); 10707 if (val & (1<<5)) 10708 vars->link_status |= 10709 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; 10710 bnx2x_cl22_read(bp, phy, 10711 0x06, 10712 &val); 10713 if ((val & (1<<0)) == 0) 10714 vars->link_status |= 10715 LINK_STATUS_PARALLEL_DETECTION_USED; 10716 10717 DP(NETIF_MSG_LINK, "BCM54618SE: link speed is %d\n", 10718 vars->line_speed); 10719 10720 bnx2x_ext_phy_resolve_fc(phy, params, vars); 10721 10722 if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) { 10723 /* Report LP advertised speeds */ 10724 bnx2x_cl22_read(bp, phy, 0x5, &val); 10725 10726 if (val & (1<<5)) 10727 vars->link_status |= 10728 LINK_STATUS_LINK_PARTNER_10THD_CAPABLE; 10729 if (val & (1<<6)) 10730 vars->link_status |= 10731 LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE; 10732 if (val & (1<<7)) 10733 vars->link_status |= 10734 LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE; 10735 if (val & (1<<8)) 10736 vars->link_status |= 10737 LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE; 10738 if (val & (1<<9)) 10739 vars->link_status |= 10740 LINK_STATUS_LINK_PARTNER_100T4_CAPABLE; 10741 10742 bnx2x_cl22_read(bp, phy, 0xa, &val); 10743 if (val & (1<<10)) 10744 vars->link_status |= 10745 LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE; 10746 if (val & (1<<11)) 10747 vars->link_status |= 10748 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; 10749 10750 if ((phy->flags & FLAGS_EEE) && 10751 bnx2x_eee_has_cap(params)) 10752 bnx2x_eee_an_resolve(phy, params, vars); 10753 } 10754 } 10755 return link_up; 10756 } 10757 10758 static void bnx2x_54618se_config_loopback(struct bnx2x_phy *phy, 10759 struct link_params *params) 10760 { 10761 struct bnx2x *bp = params->bp; 10762 u16 val; 10763 u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0; 10764 10765 DP(NETIF_MSG_LINK, "2PMA/PMD ext_phy_loopback: 54618se\n"); 10766 10767 /* Enable master/slave manual mmode and set to master */ 10768 /* mii write 9 [bits set 11 12] */ 10769 bnx2x_cl22_write(bp, phy, 0x09, 3<<11); 10770 10771 /* forced 1G and disable autoneg */ 10772 /* set val [mii read 0] */ 10773 /* set val [expr $val & [bits clear 6 12 13]] */ 10774 /* set val [expr $val | [bits set 6 8]] */ 10775 /* mii write 0 $val */ 10776 bnx2x_cl22_read(bp, phy, 0x00, &val); 10777 val &= ~((1<<6) | (1<<12) | (1<<13)); 10778 val |= (1<<6) | (1<<8); 10779 bnx2x_cl22_write(bp, phy, 0x00, val); 10780 10781 /* Set external loopback and Tx using 6dB coding */ 10782 /* mii write 0x18 7 */ 10783 /* set val [mii read 0x18] */ 10784 /* mii write 0x18 [expr $val | [bits set 10 15]] */ 10785 bnx2x_cl22_write(bp, phy, 0x18, 7); 10786 bnx2x_cl22_read(bp, phy, 0x18, &val); 10787 bnx2x_cl22_write(bp, phy, 0x18, val | (1<<10) | (1<<15)); 10788 10789 /* This register opens the gate for the UMAC despite its name */ 10790 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1); 10791 10792 /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame 10793 * length used by the MAC receive logic to check frames. 10794 */ 10795 REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710); 10796 } 10797 10798 /******************************************************************/ 10799 /* SFX7101 PHY SECTION */ 10800 /******************************************************************/ 10801 static void bnx2x_7101_config_loopback(struct bnx2x_phy *phy, 10802 struct link_params *params) 10803 { 10804 struct bnx2x *bp = params->bp; 10805 /* SFX7101_XGXS_TEST1 */ 10806 bnx2x_cl45_write(bp, phy, 10807 MDIO_XS_DEVAD, MDIO_XS_SFX7101_XGXS_TEST1, 0x100); 10808 } 10809 10810 static int bnx2x_7101_config_init(struct bnx2x_phy *phy, 10811 struct link_params *params, 10812 struct link_vars *vars) 10813 { 10814 u16 fw_ver1, fw_ver2, val; 10815 struct bnx2x *bp = params->bp; 10816 DP(NETIF_MSG_LINK, "Setting the SFX7101 LASI indication\n"); 10817 10818 /* Restore normal power mode*/ 10819 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 10820 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); 10821 /* HW reset */ 10822 bnx2x_ext_phy_hw_reset(bp, params->port); 10823 bnx2x_wait_reset_complete(bp, phy, params); 10824 10825 bnx2x_cl45_write(bp, phy, 10826 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x1); 10827 DP(NETIF_MSG_LINK, "Setting the SFX7101 LED to blink on traffic\n"); 10828 bnx2x_cl45_write(bp, phy, 10829 MDIO_PMA_DEVAD, MDIO_PMA_REG_7107_LED_CNTL, (1<<3)); 10830 10831 bnx2x_ext_phy_set_pause(params, phy, vars); 10832 /* Restart autoneg */ 10833 bnx2x_cl45_read(bp, phy, 10834 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, &val); 10835 val |= 0x200; 10836 bnx2x_cl45_write(bp, phy, 10837 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, val); 10838 10839 /* Save spirom version */ 10840 bnx2x_cl45_read(bp, phy, 10841 MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER1, &fw_ver1); 10842 10843 bnx2x_cl45_read(bp, phy, 10844 MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER2, &fw_ver2); 10845 bnx2x_save_spirom_version(bp, params->port, 10846 (u32)(fw_ver1<<16 | fw_ver2), phy->ver_addr); 10847 return 0; 10848 } 10849 10850 static u8 bnx2x_7101_read_status(struct bnx2x_phy *phy, 10851 struct link_params *params, 10852 struct link_vars *vars) 10853 { 10854 struct bnx2x *bp = params->bp; 10855 u8 link_up; 10856 u16 val1, val2; 10857 bnx2x_cl45_read(bp, phy, 10858 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2); 10859 bnx2x_cl45_read(bp, phy, 10860 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1); 10861 DP(NETIF_MSG_LINK, "10G-base-T LASI status 0x%x->0x%x\n", 10862 val2, val1); 10863 bnx2x_cl45_read(bp, phy, 10864 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2); 10865 bnx2x_cl45_read(bp, phy, 10866 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1); 10867 DP(NETIF_MSG_LINK, "10G-base-T PMA status 0x%x->0x%x\n", 10868 val2, val1); 10869 link_up = ((val1 & 4) == 4); 10870 /* If link is up print the AN outcome of the SFX7101 PHY */ 10871 if (link_up) { 10872 bnx2x_cl45_read(bp, phy, 10873 MDIO_AN_DEVAD, MDIO_AN_REG_MASTER_STATUS, 10874 &val2); 10875 vars->line_speed = SPEED_10000; 10876 vars->duplex = DUPLEX_FULL; 10877 DP(NETIF_MSG_LINK, "SFX7101 AN status 0x%x->Master=%x\n", 10878 val2, (val2 & (1<<14))); 10879 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars); 10880 bnx2x_ext_phy_resolve_fc(phy, params, vars); 10881 10882 /* Read LP advertised speeds */ 10883 if (val2 & (1<<11)) 10884 vars->link_status |= 10885 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; 10886 } 10887 return link_up; 10888 } 10889 10890 static int bnx2x_7101_format_ver(u32 spirom_ver, u8 *str, u16 *len) 10891 { 10892 if (*len < 5) 10893 return -EINVAL; 10894 str[0] = (spirom_ver & 0xFF); 10895 str[1] = (spirom_ver & 0xFF00) >> 8; 10896 str[2] = (spirom_ver & 0xFF0000) >> 16; 10897 str[3] = (spirom_ver & 0xFF000000) >> 24; 10898 str[4] = '\0'; 10899 *len -= 5; 10900 return 0; 10901 } 10902 10903 void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, struct bnx2x_phy *phy) 10904 { 10905 u16 val, cnt; 10906 10907 bnx2x_cl45_read(bp, phy, 10908 MDIO_PMA_DEVAD, 10909 MDIO_PMA_REG_7101_RESET, &val); 10910 10911 for (cnt = 0; cnt < 10; cnt++) { 10912 msleep(50); 10913 /* Writes a self-clearing reset */ 10914 bnx2x_cl45_write(bp, phy, 10915 MDIO_PMA_DEVAD, 10916 MDIO_PMA_REG_7101_RESET, 10917 (val | (1<<15))); 10918 /* Wait for clear */ 10919 bnx2x_cl45_read(bp, phy, 10920 MDIO_PMA_DEVAD, 10921 MDIO_PMA_REG_7101_RESET, &val); 10922 10923 if ((val & (1<<15)) == 0) 10924 break; 10925 } 10926 } 10927 10928 static void bnx2x_7101_hw_reset(struct bnx2x_phy *phy, 10929 struct link_params *params) { 10930 /* Low power mode is controlled by GPIO 2 */ 10931 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_2, 10932 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port); 10933 /* The PHY reset is controlled by GPIO 1 */ 10934 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1, 10935 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port); 10936 } 10937 10938 static void bnx2x_7101_set_link_led(struct bnx2x_phy *phy, 10939 struct link_params *params, u8 mode) 10940 { 10941 u16 val = 0; 10942 struct bnx2x *bp = params->bp; 10943 switch (mode) { 10944 case LED_MODE_FRONT_PANEL_OFF: 10945 case LED_MODE_OFF: 10946 val = 2; 10947 break; 10948 case LED_MODE_ON: 10949 val = 1; 10950 break; 10951 case LED_MODE_OPER: 10952 val = 0; 10953 break; 10954 } 10955 bnx2x_cl45_write(bp, phy, 10956 MDIO_PMA_DEVAD, 10957 MDIO_PMA_REG_7107_LINK_LED_CNTL, 10958 val); 10959 } 10960 10961 /******************************************************************/ 10962 /* STATIC PHY DECLARATION */ 10963 /******************************************************************/ 10964 10965 static struct bnx2x_phy phy_null = { 10966 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN, 10967 .addr = 0, 10968 .def_md_devad = 0, 10969 .flags = FLAGS_INIT_XGXS_FIRST, 10970 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 10971 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 10972 .mdio_ctrl = 0, 10973 .supported = 0, 10974 .media_type = ETH_PHY_NOT_PRESENT, 10975 .ver_addr = 0, 10976 .req_flow_ctrl = 0, 10977 .req_line_speed = 0, 10978 .speed_cap_mask = 0, 10979 .req_duplex = 0, 10980 .rsrv = 0, 10981 .config_init = (config_init_t)NULL, 10982 .read_status = (read_status_t)NULL, 10983 .link_reset = (link_reset_t)NULL, 10984 .config_loopback = (config_loopback_t)NULL, 10985 .format_fw_ver = (format_fw_ver_t)NULL, 10986 .hw_reset = (hw_reset_t)NULL, 10987 .set_link_led = (set_link_led_t)NULL, 10988 .phy_specific_func = (phy_specific_func_t)NULL 10989 }; 10990 10991 static struct bnx2x_phy phy_serdes = { 10992 .type = PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT, 10993 .addr = 0xff, 10994 .def_md_devad = 0, 10995 .flags = 0, 10996 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 10997 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 10998 .mdio_ctrl = 0, 10999 .supported = (SUPPORTED_10baseT_Half | 11000 SUPPORTED_10baseT_Full | 11001 SUPPORTED_100baseT_Half | 11002 SUPPORTED_100baseT_Full | 11003 SUPPORTED_1000baseT_Full | 11004 SUPPORTED_2500baseX_Full | 11005 SUPPORTED_TP | 11006 SUPPORTED_Autoneg | 11007 SUPPORTED_Pause | 11008 SUPPORTED_Asym_Pause), 11009 .media_type = ETH_PHY_BASE_T, 11010 .ver_addr = 0, 11011 .req_flow_ctrl = 0, 11012 .req_line_speed = 0, 11013 .speed_cap_mask = 0, 11014 .req_duplex = 0, 11015 .rsrv = 0, 11016 .config_init = (config_init_t)bnx2x_xgxs_config_init, 11017 .read_status = (read_status_t)bnx2x_link_settings_status, 11018 .link_reset = (link_reset_t)bnx2x_int_link_reset, 11019 .config_loopback = (config_loopback_t)NULL, 11020 .format_fw_ver = (format_fw_ver_t)NULL, 11021 .hw_reset = (hw_reset_t)NULL, 11022 .set_link_led = (set_link_led_t)NULL, 11023 .phy_specific_func = (phy_specific_func_t)NULL 11024 }; 11025 11026 static struct bnx2x_phy phy_xgxs = { 11027 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT, 11028 .addr = 0xff, 11029 .def_md_devad = 0, 11030 .flags = 0, 11031 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11032 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11033 .mdio_ctrl = 0, 11034 .supported = (SUPPORTED_10baseT_Half | 11035 SUPPORTED_10baseT_Full | 11036 SUPPORTED_100baseT_Half | 11037 SUPPORTED_100baseT_Full | 11038 SUPPORTED_1000baseT_Full | 11039 SUPPORTED_2500baseX_Full | 11040 SUPPORTED_10000baseT_Full | 11041 SUPPORTED_FIBRE | 11042 SUPPORTED_Autoneg | 11043 SUPPORTED_Pause | 11044 SUPPORTED_Asym_Pause), 11045 .media_type = ETH_PHY_CX4, 11046 .ver_addr = 0, 11047 .req_flow_ctrl = 0, 11048 .req_line_speed = 0, 11049 .speed_cap_mask = 0, 11050 .req_duplex = 0, 11051 .rsrv = 0, 11052 .config_init = (config_init_t)bnx2x_xgxs_config_init, 11053 .read_status = (read_status_t)bnx2x_link_settings_status, 11054 .link_reset = (link_reset_t)bnx2x_int_link_reset, 11055 .config_loopback = (config_loopback_t)bnx2x_set_xgxs_loopback, 11056 .format_fw_ver = (format_fw_ver_t)NULL, 11057 .hw_reset = (hw_reset_t)NULL, 11058 .set_link_led = (set_link_led_t)NULL, 11059 .phy_specific_func = (phy_specific_func_t)bnx2x_xgxs_specific_func 11060 }; 11061 static struct bnx2x_phy phy_warpcore = { 11062 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT, 11063 .addr = 0xff, 11064 .def_md_devad = 0, 11065 .flags = (FLAGS_HW_LOCK_REQUIRED | 11066 FLAGS_TX_ERROR_CHECK), 11067 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11068 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11069 .mdio_ctrl = 0, 11070 .supported = (SUPPORTED_10baseT_Half | 11071 SUPPORTED_10baseT_Full | 11072 SUPPORTED_100baseT_Half | 11073 SUPPORTED_100baseT_Full | 11074 SUPPORTED_1000baseT_Full | 11075 SUPPORTED_10000baseT_Full | 11076 SUPPORTED_20000baseKR2_Full | 11077 SUPPORTED_20000baseMLD2_Full | 11078 SUPPORTED_FIBRE | 11079 SUPPORTED_Autoneg | 11080 SUPPORTED_Pause | 11081 SUPPORTED_Asym_Pause), 11082 .media_type = ETH_PHY_UNSPECIFIED, 11083 .ver_addr = 0, 11084 .req_flow_ctrl = 0, 11085 .req_line_speed = 0, 11086 .speed_cap_mask = 0, 11087 /* req_duplex = */0, 11088 /* rsrv = */0, 11089 .config_init = (config_init_t)bnx2x_warpcore_config_init, 11090 .read_status = (read_status_t)bnx2x_warpcore_read_status, 11091 .link_reset = (link_reset_t)bnx2x_warpcore_link_reset, 11092 .config_loopback = (config_loopback_t)bnx2x_set_warpcore_loopback, 11093 .format_fw_ver = (format_fw_ver_t)NULL, 11094 .hw_reset = (hw_reset_t)bnx2x_warpcore_hw_reset, 11095 .set_link_led = (set_link_led_t)NULL, 11096 .phy_specific_func = (phy_specific_func_t)NULL 11097 }; 11098 11099 11100 static struct bnx2x_phy phy_7101 = { 11101 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101, 11102 .addr = 0xff, 11103 .def_md_devad = 0, 11104 .flags = FLAGS_FAN_FAILURE_DET_REQ, 11105 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11106 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11107 .mdio_ctrl = 0, 11108 .supported = (SUPPORTED_10000baseT_Full | 11109 SUPPORTED_TP | 11110 SUPPORTED_Autoneg | 11111 SUPPORTED_Pause | 11112 SUPPORTED_Asym_Pause), 11113 .media_type = ETH_PHY_BASE_T, 11114 .ver_addr = 0, 11115 .req_flow_ctrl = 0, 11116 .req_line_speed = 0, 11117 .speed_cap_mask = 0, 11118 .req_duplex = 0, 11119 .rsrv = 0, 11120 .config_init = (config_init_t)bnx2x_7101_config_init, 11121 .read_status = (read_status_t)bnx2x_7101_read_status, 11122 .link_reset = (link_reset_t)bnx2x_common_ext_link_reset, 11123 .config_loopback = (config_loopback_t)bnx2x_7101_config_loopback, 11124 .format_fw_ver = (format_fw_ver_t)bnx2x_7101_format_ver, 11125 .hw_reset = (hw_reset_t)bnx2x_7101_hw_reset, 11126 .set_link_led = (set_link_led_t)bnx2x_7101_set_link_led, 11127 .phy_specific_func = (phy_specific_func_t)NULL 11128 }; 11129 static struct bnx2x_phy phy_8073 = { 11130 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073, 11131 .addr = 0xff, 11132 .def_md_devad = 0, 11133 .flags = FLAGS_HW_LOCK_REQUIRED, 11134 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11135 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11136 .mdio_ctrl = 0, 11137 .supported = (SUPPORTED_10000baseT_Full | 11138 SUPPORTED_2500baseX_Full | 11139 SUPPORTED_1000baseT_Full | 11140 SUPPORTED_FIBRE | 11141 SUPPORTED_Autoneg | 11142 SUPPORTED_Pause | 11143 SUPPORTED_Asym_Pause), 11144 .media_type = ETH_PHY_KR, 11145 .ver_addr = 0, 11146 .req_flow_ctrl = 0, 11147 .req_line_speed = 0, 11148 .speed_cap_mask = 0, 11149 .req_duplex = 0, 11150 .rsrv = 0, 11151 .config_init = (config_init_t)bnx2x_8073_config_init, 11152 .read_status = (read_status_t)bnx2x_8073_read_status, 11153 .link_reset = (link_reset_t)bnx2x_8073_link_reset, 11154 .config_loopback = (config_loopback_t)NULL, 11155 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver, 11156 .hw_reset = (hw_reset_t)NULL, 11157 .set_link_led = (set_link_led_t)NULL, 11158 .phy_specific_func = (phy_specific_func_t)bnx2x_8073_specific_func 11159 }; 11160 static struct bnx2x_phy phy_8705 = { 11161 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705, 11162 .addr = 0xff, 11163 .def_md_devad = 0, 11164 .flags = FLAGS_INIT_XGXS_FIRST, 11165 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11166 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11167 .mdio_ctrl = 0, 11168 .supported = (SUPPORTED_10000baseT_Full | 11169 SUPPORTED_FIBRE | 11170 SUPPORTED_Pause | 11171 SUPPORTED_Asym_Pause), 11172 .media_type = ETH_PHY_XFP_FIBER, 11173 .ver_addr = 0, 11174 .req_flow_ctrl = 0, 11175 .req_line_speed = 0, 11176 .speed_cap_mask = 0, 11177 .req_duplex = 0, 11178 .rsrv = 0, 11179 .config_init = (config_init_t)bnx2x_8705_config_init, 11180 .read_status = (read_status_t)bnx2x_8705_read_status, 11181 .link_reset = (link_reset_t)bnx2x_common_ext_link_reset, 11182 .config_loopback = (config_loopback_t)NULL, 11183 .format_fw_ver = (format_fw_ver_t)bnx2x_null_format_ver, 11184 .hw_reset = (hw_reset_t)NULL, 11185 .set_link_led = (set_link_led_t)NULL, 11186 .phy_specific_func = (phy_specific_func_t)NULL 11187 }; 11188 static struct bnx2x_phy phy_8706 = { 11189 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706, 11190 .addr = 0xff, 11191 .def_md_devad = 0, 11192 .flags = FLAGS_INIT_XGXS_FIRST, 11193 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11194 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11195 .mdio_ctrl = 0, 11196 .supported = (SUPPORTED_10000baseT_Full | 11197 SUPPORTED_1000baseT_Full | 11198 SUPPORTED_FIBRE | 11199 SUPPORTED_Pause | 11200 SUPPORTED_Asym_Pause), 11201 .media_type = ETH_PHY_SFPP_10G_FIBER, 11202 .ver_addr = 0, 11203 .req_flow_ctrl = 0, 11204 .req_line_speed = 0, 11205 .speed_cap_mask = 0, 11206 .req_duplex = 0, 11207 .rsrv = 0, 11208 .config_init = (config_init_t)bnx2x_8706_config_init, 11209 .read_status = (read_status_t)bnx2x_8706_read_status, 11210 .link_reset = (link_reset_t)bnx2x_common_ext_link_reset, 11211 .config_loopback = (config_loopback_t)NULL, 11212 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver, 11213 .hw_reset = (hw_reset_t)NULL, 11214 .set_link_led = (set_link_led_t)NULL, 11215 .phy_specific_func = (phy_specific_func_t)NULL 11216 }; 11217 11218 static struct bnx2x_phy phy_8726 = { 11219 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726, 11220 .addr = 0xff, 11221 .def_md_devad = 0, 11222 .flags = (FLAGS_HW_LOCK_REQUIRED | 11223 FLAGS_INIT_XGXS_FIRST | 11224 FLAGS_TX_ERROR_CHECK), 11225 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11226 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11227 .mdio_ctrl = 0, 11228 .supported = (SUPPORTED_10000baseT_Full | 11229 SUPPORTED_1000baseT_Full | 11230 SUPPORTED_Autoneg | 11231 SUPPORTED_FIBRE | 11232 SUPPORTED_Pause | 11233 SUPPORTED_Asym_Pause), 11234 .media_type = ETH_PHY_NOT_PRESENT, 11235 .ver_addr = 0, 11236 .req_flow_ctrl = 0, 11237 .req_line_speed = 0, 11238 .speed_cap_mask = 0, 11239 .req_duplex = 0, 11240 .rsrv = 0, 11241 .config_init = (config_init_t)bnx2x_8726_config_init, 11242 .read_status = (read_status_t)bnx2x_8726_read_status, 11243 .link_reset = (link_reset_t)bnx2x_8726_link_reset, 11244 .config_loopback = (config_loopback_t)bnx2x_8726_config_loopback, 11245 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver, 11246 .hw_reset = (hw_reset_t)NULL, 11247 .set_link_led = (set_link_led_t)NULL, 11248 .phy_specific_func = (phy_specific_func_t)NULL 11249 }; 11250 11251 static struct bnx2x_phy phy_8727 = { 11252 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727, 11253 .addr = 0xff, 11254 .def_md_devad = 0, 11255 .flags = (FLAGS_FAN_FAILURE_DET_REQ | 11256 FLAGS_TX_ERROR_CHECK), 11257 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11258 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11259 .mdio_ctrl = 0, 11260 .supported = (SUPPORTED_10000baseT_Full | 11261 SUPPORTED_1000baseT_Full | 11262 SUPPORTED_FIBRE | 11263 SUPPORTED_Pause | 11264 SUPPORTED_Asym_Pause), 11265 .media_type = ETH_PHY_NOT_PRESENT, 11266 .ver_addr = 0, 11267 .req_flow_ctrl = 0, 11268 .req_line_speed = 0, 11269 .speed_cap_mask = 0, 11270 .req_duplex = 0, 11271 .rsrv = 0, 11272 .config_init = (config_init_t)bnx2x_8727_config_init, 11273 .read_status = (read_status_t)bnx2x_8727_read_status, 11274 .link_reset = (link_reset_t)bnx2x_8727_link_reset, 11275 .config_loopback = (config_loopback_t)NULL, 11276 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver, 11277 .hw_reset = (hw_reset_t)bnx2x_8727_hw_reset, 11278 .set_link_led = (set_link_led_t)bnx2x_8727_set_link_led, 11279 .phy_specific_func = (phy_specific_func_t)bnx2x_8727_specific_func 11280 }; 11281 static struct bnx2x_phy phy_8481 = { 11282 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481, 11283 .addr = 0xff, 11284 .def_md_devad = 0, 11285 .flags = FLAGS_FAN_FAILURE_DET_REQ | 11286 FLAGS_REARM_LATCH_SIGNAL, 11287 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11288 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11289 .mdio_ctrl = 0, 11290 .supported = (SUPPORTED_10baseT_Half | 11291 SUPPORTED_10baseT_Full | 11292 SUPPORTED_100baseT_Half | 11293 SUPPORTED_100baseT_Full | 11294 SUPPORTED_1000baseT_Full | 11295 SUPPORTED_10000baseT_Full | 11296 SUPPORTED_TP | 11297 SUPPORTED_Autoneg | 11298 SUPPORTED_Pause | 11299 SUPPORTED_Asym_Pause), 11300 .media_type = ETH_PHY_BASE_T, 11301 .ver_addr = 0, 11302 .req_flow_ctrl = 0, 11303 .req_line_speed = 0, 11304 .speed_cap_mask = 0, 11305 .req_duplex = 0, 11306 .rsrv = 0, 11307 .config_init = (config_init_t)bnx2x_8481_config_init, 11308 .read_status = (read_status_t)bnx2x_848xx_read_status, 11309 .link_reset = (link_reset_t)bnx2x_8481_link_reset, 11310 .config_loopback = (config_loopback_t)NULL, 11311 .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver, 11312 .hw_reset = (hw_reset_t)bnx2x_8481_hw_reset, 11313 .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led, 11314 .phy_specific_func = (phy_specific_func_t)NULL 11315 }; 11316 11317 static struct bnx2x_phy phy_84823 = { 11318 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823, 11319 .addr = 0xff, 11320 .def_md_devad = 0, 11321 .flags = (FLAGS_FAN_FAILURE_DET_REQ | 11322 FLAGS_REARM_LATCH_SIGNAL | 11323 FLAGS_TX_ERROR_CHECK), 11324 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11325 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11326 .mdio_ctrl = 0, 11327 .supported = (SUPPORTED_10baseT_Half | 11328 SUPPORTED_10baseT_Full | 11329 SUPPORTED_100baseT_Half | 11330 SUPPORTED_100baseT_Full | 11331 SUPPORTED_1000baseT_Full | 11332 SUPPORTED_10000baseT_Full | 11333 SUPPORTED_TP | 11334 SUPPORTED_Autoneg | 11335 SUPPORTED_Pause | 11336 SUPPORTED_Asym_Pause), 11337 .media_type = ETH_PHY_BASE_T, 11338 .ver_addr = 0, 11339 .req_flow_ctrl = 0, 11340 .req_line_speed = 0, 11341 .speed_cap_mask = 0, 11342 .req_duplex = 0, 11343 .rsrv = 0, 11344 .config_init = (config_init_t)bnx2x_848x3_config_init, 11345 .read_status = (read_status_t)bnx2x_848xx_read_status, 11346 .link_reset = (link_reset_t)bnx2x_848x3_link_reset, 11347 .config_loopback = (config_loopback_t)NULL, 11348 .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver, 11349 .hw_reset = (hw_reset_t)NULL, 11350 .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led, 11351 .phy_specific_func = (phy_specific_func_t)bnx2x_848xx_specific_func 11352 }; 11353 11354 static struct bnx2x_phy phy_84833 = { 11355 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833, 11356 .addr = 0xff, 11357 .def_md_devad = 0, 11358 .flags = (FLAGS_FAN_FAILURE_DET_REQ | 11359 FLAGS_REARM_LATCH_SIGNAL | 11360 FLAGS_TX_ERROR_CHECK), 11361 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11362 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11363 .mdio_ctrl = 0, 11364 .supported = (SUPPORTED_100baseT_Half | 11365 SUPPORTED_100baseT_Full | 11366 SUPPORTED_1000baseT_Full | 11367 SUPPORTED_10000baseT_Full | 11368 SUPPORTED_TP | 11369 SUPPORTED_Autoneg | 11370 SUPPORTED_Pause | 11371 SUPPORTED_Asym_Pause), 11372 .media_type = ETH_PHY_BASE_T, 11373 .ver_addr = 0, 11374 .req_flow_ctrl = 0, 11375 .req_line_speed = 0, 11376 .speed_cap_mask = 0, 11377 .req_duplex = 0, 11378 .rsrv = 0, 11379 .config_init = (config_init_t)bnx2x_848x3_config_init, 11380 .read_status = (read_status_t)bnx2x_848xx_read_status, 11381 .link_reset = (link_reset_t)bnx2x_848x3_link_reset, 11382 .config_loopback = (config_loopback_t)NULL, 11383 .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver, 11384 .hw_reset = (hw_reset_t)bnx2x_84833_hw_reset_phy, 11385 .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led, 11386 .phy_specific_func = (phy_specific_func_t)bnx2x_848xx_specific_func 11387 }; 11388 11389 static struct bnx2x_phy phy_54618se = { 11390 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE, 11391 .addr = 0xff, 11392 .def_md_devad = 0, 11393 .flags = FLAGS_INIT_XGXS_FIRST, 11394 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11395 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11396 .mdio_ctrl = 0, 11397 .supported = (SUPPORTED_10baseT_Half | 11398 SUPPORTED_10baseT_Full | 11399 SUPPORTED_100baseT_Half | 11400 SUPPORTED_100baseT_Full | 11401 SUPPORTED_1000baseT_Full | 11402 SUPPORTED_TP | 11403 SUPPORTED_Autoneg | 11404 SUPPORTED_Pause | 11405 SUPPORTED_Asym_Pause), 11406 .media_type = ETH_PHY_BASE_T, 11407 .ver_addr = 0, 11408 .req_flow_ctrl = 0, 11409 .req_line_speed = 0, 11410 .speed_cap_mask = 0, 11411 /* req_duplex = */0, 11412 /* rsrv = */0, 11413 .config_init = (config_init_t)bnx2x_54618se_config_init, 11414 .read_status = (read_status_t)bnx2x_54618se_read_status, 11415 .link_reset = (link_reset_t)bnx2x_54618se_link_reset, 11416 .config_loopback = (config_loopback_t)bnx2x_54618se_config_loopback, 11417 .format_fw_ver = (format_fw_ver_t)NULL, 11418 .hw_reset = (hw_reset_t)NULL, 11419 .set_link_led = (set_link_led_t)bnx2x_5461x_set_link_led, 11420 .phy_specific_func = (phy_specific_func_t)bnx2x_54618se_specific_func 11421 }; 11422 /*****************************************************************/ 11423 /* */ 11424 /* Populate the phy according. Main function: bnx2x_populate_phy */ 11425 /* */ 11426 /*****************************************************************/ 11427 11428 static void bnx2x_populate_preemphasis(struct bnx2x *bp, u32 shmem_base, 11429 struct bnx2x_phy *phy, u8 port, 11430 u8 phy_index) 11431 { 11432 /* Get the 4 lanes xgxs config rx and tx */ 11433 u32 rx = 0, tx = 0, i; 11434 for (i = 0; i < 2; i++) { 11435 /* INT_PHY and EXT_PHY1 share the same value location in 11436 * the shmem. When num_phys is greater than 1, than this value 11437 * applies only to EXT_PHY1 11438 */ 11439 if (phy_index == INT_PHY || phy_index == EXT_PHY1) { 11440 rx = REG_RD(bp, shmem_base + 11441 offsetof(struct shmem_region, 11442 dev_info.port_hw_config[port].xgxs_config_rx[i<<1])); 11443 11444 tx = REG_RD(bp, shmem_base + 11445 offsetof(struct shmem_region, 11446 dev_info.port_hw_config[port].xgxs_config_tx[i<<1])); 11447 } else { 11448 rx = REG_RD(bp, shmem_base + 11449 offsetof(struct shmem_region, 11450 dev_info.port_hw_config[port].xgxs_config2_rx[i<<1])); 11451 11452 tx = REG_RD(bp, shmem_base + 11453 offsetof(struct shmem_region, 11454 dev_info.port_hw_config[port].xgxs_config2_rx[i<<1])); 11455 } 11456 11457 phy->rx_preemphasis[i << 1] = ((rx>>16) & 0xffff); 11458 phy->rx_preemphasis[(i << 1) + 1] = (rx & 0xffff); 11459 11460 phy->tx_preemphasis[i << 1] = ((tx>>16) & 0xffff); 11461 phy->tx_preemphasis[(i << 1) + 1] = (tx & 0xffff); 11462 } 11463 } 11464 11465 static u32 bnx2x_get_ext_phy_config(struct bnx2x *bp, u32 shmem_base, 11466 u8 phy_index, u8 port) 11467 { 11468 u32 ext_phy_config = 0; 11469 switch (phy_index) { 11470 case EXT_PHY1: 11471 ext_phy_config = REG_RD(bp, shmem_base + 11472 offsetof(struct shmem_region, 11473 dev_info.port_hw_config[port].external_phy_config)); 11474 break; 11475 case EXT_PHY2: 11476 ext_phy_config = REG_RD(bp, shmem_base + 11477 offsetof(struct shmem_region, 11478 dev_info.port_hw_config[port].external_phy_config2)); 11479 break; 11480 default: 11481 DP(NETIF_MSG_LINK, "Invalid phy_index %d\n", phy_index); 11482 return -EINVAL; 11483 } 11484 11485 return ext_phy_config; 11486 } 11487 static int bnx2x_populate_int_phy(struct bnx2x *bp, u32 shmem_base, u8 port, 11488 struct bnx2x_phy *phy) 11489 { 11490 u32 phy_addr; 11491 u32 chip_id; 11492 u32 switch_cfg = (REG_RD(bp, shmem_base + 11493 offsetof(struct shmem_region, 11494 dev_info.port_feature_config[port].link_config)) & 11495 PORT_FEATURE_CONNECTED_SWITCH_MASK); 11496 chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) | 11497 ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12); 11498 11499 DP(NETIF_MSG_LINK, ":chip_id = 0x%x\n", chip_id); 11500 if (USES_WARPCORE(bp)) { 11501 u32 serdes_net_if; 11502 phy_addr = REG_RD(bp, 11503 MISC_REG_WC0_CTRL_PHY_ADDR); 11504 *phy = phy_warpcore; 11505 if (REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR) == 0x3) 11506 phy->flags |= FLAGS_4_PORT_MODE; 11507 else 11508 phy->flags &= ~FLAGS_4_PORT_MODE; 11509 /* Check Dual mode */ 11510 serdes_net_if = (REG_RD(bp, shmem_base + 11511 offsetof(struct shmem_region, dev_info. 11512 port_hw_config[port].default_cfg)) & 11513 PORT_HW_CFG_NET_SERDES_IF_MASK); 11514 /* Set the appropriate supported and flags indications per 11515 * interface type of the chip 11516 */ 11517 switch (serdes_net_if) { 11518 case PORT_HW_CFG_NET_SERDES_IF_SGMII: 11519 phy->supported &= (SUPPORTED_10baseT_Half | 11520 SUPPORTED_10baseT_Full | 11521 SUPPORTED_100baseT_Half | 11522 SUPPORTED_100baseT_Full | 11523 SUPPORTED_1000baseT_Full | 11524 SUPPORTED_FIBRE | 11525 SUPPORTED_Autoneg | 11526 SUPPORTED_Pause | 11527 SUPPORTED_Asym_Pause); 11528 phy->media_type = ETH_PHY_BASE_T; 11529 break; 11530 case PORT_HW_CFG_NET_SERDES_IF_XFI: 11531 phy->supported &= (SUPPORTED_1000baseT_Full | 11532 SUPPORTED_10000baseT_Full | 11533 SUPPORTED_FIBRE | 11534 SUPPORTED_Pause | 11535 SUPPORTED_Asym_Pause); 11536 phy->media_type = ETH_PHY_XFP_FIBER; 11537 break; 11538 case PORT_HW_CFG_NET_SERDES_IF_SFI: 11539 phy->supported &= (SUPPORTED_1000baseT_Full | 11540 SUPPORTED_10000baseT_Full | 11541 SUPPORTED_FIBRE | 11542 SUPPORTED_Pause | 11543 SUPPORTED_Asym_Pause); 11544 phy->media_type = ETH_PHY_SFPP_10G_FIBER; 11545 break; 11546 case PORT_HW_CFG_NET_SERDES_IF_KR: 11547 phy->media_type = ETH_PHY_KR; 11548 phy->supported &= (SUPPORTED_1000baseT_Full | 11549 SUPPORTED_10000baseT_Full | 11550 SUPPORTED_FIBRE | 11551 SUPPORTED_Autoneg | 11552 SUPPORTED_Pause | 11553 SUPPORTED_Asym_Pause); 11554 break; 11555 case PORT_HW_CFG_NET_SERDES_IF_DXGXS: 11556 phy->media_type = ETH_PHY_KR; 11557 phy->flags |= FLAGS_WC_DUAL_MODE; 11558 phy->supported &= (SUPPORTED_20000baseMLD2_Full | 11559 SUPPORTED_FIBRE | 11560 SUPPORTED_Pause | 11561 SUPPORTED_Asym_Pause); 11562 break; 11563 case PORT_HW_CFG_NET_SERDES_IF_KR2: 11564 phy->media_type = ETH_PHY_KR; 11565 phy->flags |= FLAGS_WC_DUAL_MODE; 11566 phy->supported &= (SUPPORTED_20000baseKR2_Full | 11567 SUPPORTED_FIBRE | 11568 SUPPORTED_Pause | 11569 SUPPORTED_Asym_Pause); 11570 break; 11571 default: 11572 DP(NETIF_MSG_LINK, "Unknown WC interface type 0x%x\n", 11573 serdes_net_if); 11574 break; 11575 } 11576 11577 /* Enable MDC/MDIO work-around for E3 A0 since free running MDC 11578 * was not set as expected. For B0, ECO will be enabled so there 11579 * won't be an issue there 11580 */ 11581 if (CHIP_REV(bp) == CHIP_REV_Ax) 11582 phy->flags |= FLAGS_MDC_MDIO_WA; 11583 else 11584 phy->flags |= FLAGS_MDC_MDIO_WA_B0; 11585 } else { 11586 switch (switch_cfg) { 11587 case SWITCH_CFG_1G: 11588 phy_addr = REG_RD(bp, 11589 NIG_REG_SERDES0_CTRL_PHY_ADDR + 11590 port * 0x10); 11591 *phy = phy_serdes; 11592 break; 11593 case SWITCH_CFG_10G: 11594 phy_addr = REG_RD(bp, 11595 NIG_REG_XGXS0_CTRL_PHY_ADDR + 11596 port * 0x18); 11597 *phy = phy_xgxs; 11598 break; 11599 default: 11600 DP(NETIF_MSG_LINK, "Invalid switch_cfg\n"); 11601 return -EINVAL; 11602 } 11603 } 11604 phy->addr = (u8)phy_addr; 11605 phy->mdio_ctrl = bnx2x_get_emac_base(bp, 11606 SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH, 11607 port); 11608 if (CHIP_IS_E2(bp)) 11609 phy->def_md_devad = E2_DEFAULT_PHY_DEV_ADDR; 11610 else 11611 phy->def_md_devad = DEFAULT_PHY_DEV_ADDR; 11612 11613 DP(NETIF_MSG_LINK, "Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x\n", 11614 port, phy->addr, phy->mdio_ctrl); 11615 11616 bnx2x_populate_preemphasis(bp, shmem_base, phy, port, INT_PHY); 11617 return 0; 11618 } 11619 11620 static int bnx2x_populate_ext_phy(struct bnx2x *bp, 11621 u8 phy_index, 11622 u32 shmem_base, 11623 u32 shmem2_base, 11624 u8 port, 11625 struct bnx2x_phy *phy) 11626 { 11627 u32 ext_phy_config, phy_type, config2; 11628 u32 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH; 11629 ext_phy_config = bnx2x_get_ext_phy_config(bp, shmem_base, 11630 phy_index, port); 11631 phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config); 11632 /* Select the phy type */ 11633 switch (phy_type) { 11634 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073: 11635 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED; 11636 *phy = phy_8073; 11637 break; 11638 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705: 11639 *phy = phy_8705; 11640 break; 11641 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706: 11642 *phy = phy_8706; 11643 break; 11644 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: 11645 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1; 11646 *phy = phy_8726; 11647 break; 11648 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC: 11649 /* BCM8727_NOC => BCM8727 no over current */ 11650 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1; 11651 *phy = phy_8727; 11652 phy->flags |= FLAGS_NOC; 11653 break; 11654 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722: 11655 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: 11656 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1; 11657 *phy = phy_8727; 11658 break; 11659 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481: 11660 *phy = phy_8481; 11661 break; 11662 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823: 11663 *phy = phy_84823; 11664 break; 11665 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833: 11666 *phy = phy_84833; 11667 break; 11668 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616: 11669 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE: 11670 *phy = phy_54618se; 11671 if (phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) 11672 phy->flags |= FLAGS_EEE; 11673 break; 11674 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101: 11675 *phy = phy_7101; 11676 break; 11677 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE: 11678 *phy = phy_null; 11679 return -EINVAL; 11680 default: 11681 *phy = phy_null; 11682 /* In case external PHY wasn't found */ 11683 if ((phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) && 11684 (phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)) 11685 return -EINVAL; 11686 return 0; 11687 } 11688 11689 phy->addr = XGXS_EXT_PHY_ADDR(ext_phy_config); 11690 bnx2x_populate_preemphasis(bp, shmem_base, phy, port, phy_index); 11691 11692 /* The shmem address of the phy version is located on different 11693 * structures. In case this structure is too old, do not set 11694 * the address 11695 */ 11696 config2 = REG_RD(bp, shmem_base + offsetof(struct shmem_region, 11697 dev_info.shared_hw_config.config2)); 11698 if (phy_index == EXT_PHY1) { 11699 phy->ver_addr = shmem_base + offsetof(struct shmem_region, 11700 port_mb[port].ext_phy_fw_version); 11701 11702 /* Check specific mdc mdio settings */ 11703 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK) 11704 mdc_mdio_access = config2 & 11705 SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK; 11706 } else { 11707 u32 size = REG_RD(bp, shmem2_base); 11708 11709 if (size > 11710 offsetof(struct shmem2_region, ext_phy_fw_version2)) { 11711 phy->ver_addr = shmem2_base + 11712 offsetof(struct shmem2_region, 11713 ext_phy_fw_version2[port]); 11714 } 11715 /* Check specific mdc mdio settings */ 11716 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) 11717 mdc_mdio_access = (config2 & 11718 SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) >> 11719 (SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT - 11720 SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT); 11721 } 11722 phy->mdio_ctrl = bnx2x_get_emac_base(bp, mdc_mdio_access, port); 11723 11724 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) && 11725 (phy->ver_addr)) { 11726 /* Remove 100Mb link supported for BCM84833 when phy fw 11727 * version lower than or equal to 1.39 11728 */ 11729 u32 raw_ver = REG_RD(bp, phy->ver_addr); 11730 if (((raw_ver & 0x7F) <= 39) && 11731 (((raw_ver & 0xF80) >> 7) <= 1)) 11732 phy->supported &= ~(SUPPORTED_100baseT_Half | 11733 SUPPORTED_100baseT_Full); 11734 } 11735 11736 /* In case mdc/mdio_access of the external phy is different than the 11737 * mdc/mdio access of the XGXS, a HW lock must be taken in each access 11738 * to prevent one port interfere with another port's CL45 operations. 11739 */ 11740 if (mdc_mdio_access != SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH) 11741 phy->flags |= FLAGS_HW_LOCK_REQUIRED; 11742 DP(NETIF_MSG_LINK, "phy_type 0x%x port %d found in index %d\n", 11743 phy_type, port, phy_index); 11744 DP(NETIF_MSG_LINK, " addr=0x%x, mdio_ctl=0x%x\n", 11745 phy->addr, phy->mdio_ctrl); 11746 return 0; 11747 } 11748 11749 static int bnx2x_populate_phy(struct bnx2x *bp, u8 phy_index, u32 shmem_base, 11750 u32 shmem2_base, u8 port, struct bnx2x_phy *phy) 11751 { 11752 int status = 0; 11753 phy->type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN; 11754 if (phy_index == INT_PHY) 11755 return bnx2x_populate_int_phy(bp, shmem_base, port, phy); 11756 status = bnx2x_populate_ext_phy(bp, phy_index, shmem_base, shmem2_base, 11757 port, phy); 11758 return status; 11759 } 11760 11761 static void bnx2x_phy_def_cfg(struct link_params *params, 11762 struct bnx2x_phy *phy, 11763 u8 phy_index) 11764 { 11765 struct bnx2x *bp = params->bp; 11766 u32 link_config; 11767 /* Populate the default phy configuration for MF mode */ 11768 if (phy_index == EXT_PHY2) { 11769 link_config = REG_RD(bp, params->shmem_base + 11770 offsetof(struct shmem_region, dev_info. 11771 port_feature_config[params->port].link_config2)); 11772 phy->speed_cap_mask = REG_RD(bp, params->shmem_base + 11773 offsetof(struct shmem_region, 11774 dev_info. 11775 port_hw_config[params->port].speed_capability_mask2)); 11776 } else { 11777 link_config = REG_RD(bp, params->shmem_base + 11778 offsetof(struct shmem_region, dev_info. 11779 port_feature_config[params->port].link_config)); 11780 phy->speed_cap_mask = REG_RD(bp, params->shmem_base + 11781 offsetof(struct shmem_region, 11782 dev_info. 11783 port_hw_config[params->port].speed_capability_mask)); 11784 } 11785 DP(NETIF_MSG_LINK, 11786 "Default config phy idx %x cfg 0x%x speed_cap_mask 0x%x\n", 11787 phy_index, link_config, phy->speed_cap_mask); 11788 11789 phy->req_duplex = DUPLEX_FULL; 11790 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) { 11791 case PORT_FEATURE_LINK_SPEED_10M_HALF: 11792 phy->req_duplex = DUPLEX_HALF; 11793 case PORT_FEATURE_LINK_SPEED_10M_FULL: 11794 phy->req_line_speed = SPEED_10; 11795 break; 11796 case PORT_FEATURE_LINK_SPEED_100M_HALF: 11797 phy->req_duplex = DUPLEX_HALF; 11798 case PORT_FEATURE_LINK_SPEED_100M_FULL: 11799 phy->req_line_speed = SPEED_100; 11800 break; 11801 case PORT_FEATURE_LINK_SPEED_1G: 11802 phy->req_line_speed = SPEED_1000; 11803 break; 11804 case PORT_FEATURE_LINK_SPEED_2_5G: 11805 phy->req_line_speed = SPEED_2500; 11806 break; 11807 case PORT_FEATURE_LINK_SPEED_10G_CX4: 11808 phy->req_line_speed = SPEED_10000; 11809 break; 11810 default: 11811 phy->req_line_speed = SPEED_AUTO_NEG; 11812 break; 11813 } 11814 11815 switch (link_config & PORT_FEATURE_FLOW_CONTROL_MASK) { 11816 case PORT_FEATURE_FLOW_CONTROL_AUTO: 11817 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_AUTO; 11818 break; 11819 case PORT_FEATURE_FLOW_CONTROL_TX: 11820 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_TX; 11821 break; 11822 case PORT_FEATURE_FLOW_CONTROL_RX: 11823 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_RX; 11824 break; 11825 case PORT_FEATURE_FLOW_CONTROL_BOTH: 11826 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_BOTH; 11827 break; 11828 default: 11829 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_NONE; 11830 break; 11831 } 11832 } 11833 11834 u32 bnx2x_phy_selection(struct link_params *params) 11835 { 11836 u32 phy_config_swapped, prio_cfg; 11837 u32 return_cfg = PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT; 11838 11839 phy_config_swapped = params->multi_phy_config & 11840 PORT_HW_CFG_PHY_SWAPPED_ENABLED; 11841 11842 prio_cfg = params->multi_phy_config & 11843 PORT_HW_CFG_PHY_SELECTION_MASK; 11844 11845 if (phy_config_swapped) { 11846 switch (prio_cfg) { 11847 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY: 11848 return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY; 11849 break; 11850 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY: 11851 return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY; 11852 break; 11853 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY: 11854 return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY; 11855 break; 11856 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY: 11857 return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY; 11858 break; 11859 } 11860 } else 11861 return_cfg = prio_cfg; 11862 11863 return return_cfg; 11864 } 11865 11866 11867 int bnx2x_phy_probe(struct link_params *params) 11868 { 11869 u8 phy_index, actual_phy_idx; 11870 u32 phy_config_swapped, sync_offset, media_types; 11871 struct bnx2x *bp = params->bp; 11872 struct bnx2x_phy *phy; 11873 params->num_phys = 0; 11874 DP(NETIF_MSG_LINK, "Begin phy probe\n"); 11875 phy_config_swapped = params->multi_phy_config & 11876 PORT_HW_CFG_PHY_SWAPPED_ENABLED; 11877 11878 for (phy_index = INT_PHY; phy_index < MAX_PHYS; 11879 phy_index++) { 11880 actual_phy_idx = phy_index; 11881 if (phy_config_swapped) { 11882 if (phy_index == EXT_PHY1) 11883 actual_phy_idx = EXT_PHY2; 11884 else if (phy_index == EXT_PHY2) 11885 actual_phy_idx = EXT_PHY1; 11886 } 11887 DP(NETIF_MSG_LINK, "phy_config_swapped %x, phy_index %x," 11888 " actual_phy_idx %x\n", phy_config_swapped, 11889 phy_index, actual_phy_idx); 11890 phy = ¶ms->phy[actual_phy_idx]; 11891 if (bnx2x_populate_phy(bp, phy_index, params->shmem_base, 11892 params->shmem2_base, params->port, 11893 phy) != 0) { 11894 params->num_phys = 0; 11895 DP(NETIF_MSG_LINK, "phy probe failed in phy index %d\n", 11896 phy_index); 11897 for (phy_index = INT_PHY; 11898 phy_index < MAX_PHYS; 11899 phy_index++) 11900 *phy = phy_null; 11901 return -EINVAL; 11902 } 11903 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN) 11904 break; 11905 11906 if (params->feature_config_flags & 11907 FEATURE_CONFIG_DISABLE_REMOTE_FAULT_DET) 11908 phy->flags &= ~FLAGS_TX_ERROR_CHECK; 11909 11910 sync_offset = params->shmem_base + 11911 offsetof(struct shmem_region, 11912 dev_info.port_hw_config[params->port].media_type); 11913 media_types = REG_RD(bp, sync_offset); 11914 11915 /* Update media type for non-PMF sync only for the first time 11916 * In case the media type changes afterwards, it will be updated 11917 * using the update_status function 11918 */ 11919 if ((media_types & (PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK << 11920 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * 11921 actual_phy_idx))) == 0) { 11922 media_types |= ((phy->media_type & 11923 PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) << 11924 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * 11925 actual_phy_idx)); 11926 } 11927 REG_WR(bp, sync_offset, media_types); 11928 11929 bnx2x_phy_def_cfg(params, phy, phy_index); 11930 params->num_phys++; 11931 } 11932 11933 DP(NETIF_MSG_LINK, "End phy probe. #phys found %x\n", params->num_phys); 11934 return 0; 11935 } 11936 11937 void bnx2x_init_bmac_loopback(struct link_params *params, 11938 struct link_vars *vars) 11939 { 11940 struct bnx2x *bp = params->bp; 11941 vars->link_up = 1; 11942 vars->line_speed = SPEED_10000; 11943 vars->duplex = DUPLEX_FULL; 11944 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; 11945 vars->mac_type = MAC_TYPE_BMAC; 11946 11947 vars->phy_flags = PHY_XGXS_FLAG; 11948 11949 bnx2x_xgxs_deassert(params); 11950 11951 /* set bmac loopback */ 11952 bnx2x_bmac_enable(params, vars, 1, 1); 11953 11954 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); 11955 } 11956 11957 void bnx2x_init_emac_loopback(struct link_params *params, 11958 struct link_vars *vars) 11959 { 11960 struct bnx2x *bp = params->bp; 11961 vars->link_up = 1; 11962 vars->line_speed = SPEED_1000; 11963 vars->duplex = DUPLEX_FULL; 11964 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; 11965 vars->mac_type = MAC_TYPE_EMAC; 11966 11967 vars->phy_flags = PHY_XGXS_FLAG; 11968 11969 bnx2x_xgxs_deassert(params); 11970 /* set bmac loopback */ 11971 bnx2x_emac_enable(params, vars, 1); 11972 bnx2x_emac_program(params, vars); 11973 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); 11974 } 11975 11976 void bnx2x_init_xmac_loopback(struct link_params *params, 11977 struct link_vars *vars) 11978 { 11979 struct bnx2x *bp = params->bp; 11980 vars->link_up = 1; 11981 if (!params->req_line_speed[0]) 11982 vars->line_speed = SPEED_10000; 11983 else 11984 vars->line_speed = params->req_line_speed[0]; 11985 vars->duplex = DUPLEX_FULL; 11986 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; 11987 vars->mac_type = MAC_TYPE_XMAC; 11988 vars->phy_flags = PHY_XGXS_FLAG; 11989 /* Set WC to loopback mode since link is required to provide clock 11990 * to the XMAC in 20G mode 11991 */ 11992 bnx2x_set_aer_mmd(params, ¶ms->phy[0]); 11993 bnx2x_warpcore_reset_lane(bp, ¶ms->phy[0], 0); 11994 params->phy[INT_PHY].config_loopback( 11995 ¶ms->phy[INT_PHY], 11996 params); 11997 11998 bnx2x_xmac_enable(params, vars, 1); 11999 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); 12000 } 12001 12002 void bnx2x_init_umac_loopback(struct link_params *params, 12003 struct link_vars *vars) 12004 { 12005 struct bnx2x *bp = params->bp; 12006 vars->link_up = 1; 12007 vars->line_speed = SPEED_1000; 12008 vars->duplex = DUPLEX_FULL; 12009 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; 12010 vars->mac_type = MAC_TYPE_UMAC; 12011 vars->phy_flags = PHY_XGXS_FLAG; 12012 bnx2x_umac_enable(params, vars, 1); 12013 12014 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); 12015 } 12016 12017 void bnx2x_init_xgxs_loopback(struct link_params *params, 12018 struct link_vars *vars) 12019 { 12020 struct bnx2x *bp = params->bp; 12021 vars->link_up = 1; 12022 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; 12023 vars->duplex = DUPLEX_FULL; 12024 if (params->req_line_speed[0] == SPEED_1000) 12025 vars->line_speed = SPEED_1000; 12026 else 12027 vars->line_speed = SPEED_10000; 12028 12029 if (!USES_WARPCORE(bp)) 12030 bnx2x_xgxs_deassert(params); 12031 bnx2x_link_initialize(params, vars); 12032 12033 if (params->req_line_speed[0] == SPEED_1000) { 12034 if (USES_WARPCORE(bp)) 12035 bnx2x_umac_enable(params, vars, 0); 12036 else { 12037 bnx2x_emac_program(params, vars); 12038 bnx2x_emac_enable(params, vars, 0); 12039 } 12040 } else { 12041 if (USES_WARPCORE(bp)) 12042 bnx2x_xmac_enable(params, vars, 0); 12043 else 12044 bnx2x_bmac_enable(params, vars, 0, 1); 12045 } 12046 12047 if (params->loopback_mode == LOOPBACK_XGXS) { 12048 /* set 10G XGXS loopback */ 12049 params->phy[INT_PHY].config_loopback( 12050 ¶ms->phy[INT_PHY], 12051 params); 12052 12053 } else { 12054 /* set external phy loopback */ 12055 u8 phy_index; 12056 for (phy_index = EXT_PHY1; 12057 phy_index < params->num_phys; phy_index++) { 12058 if (params->phy[phy_index].config_loopback) 12059 params->phy[phy_index].config_loopback( 12060 ¶ms->phy[phy_index], 12061 params); 12062 } 12063 } 12064 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); 12065 12066 bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed); 12067 } 12068 12069 static void bnx2x_set_rx_filter(struct link_params *params, u8 en) 12070 { 12071 struct bnx2x *bp = params->bp; 12072 u8 val = en * 0x1F; 12073 12074 /* Open the gate between the NIG to the BRB */ 12075 if (!CHIP_IS_E1x(bp)) 12076 val |= en * 0x20; 12077 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + params->port*4, val); 12078 12079 if (!CHIP_IS_E1(bp)) { 12080 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + params->port*4, 12081 en*0x3); 12082 } 12083 12084 REG_WR(bp, (params->port ? NIG_REG_LLH1_BRB1_NOT_MCP : 12085 NIG_REG_LLH0_BRB1_NOT_MCP), en); 12086 } 12087 static int bnx2x_avoid_link_flap(struct link_params *params, 12088 struct link_vars *vars) 12089 { 12090 u32 phy_idx; 12091 u32 dont_clear_stat, lfa_sts; 12092 struct bnx2x *bp = params->bp; 12093 12094 /* Sync the link parameters */ 12095 bnx2x_link_status_update(params, vars); 12096 12097 /* 12098 * The module verification was already done by previous link owner, 12099 * so this call is meant only to get warning message 12100 */ 12101 12102 for (phy_idx = INT_PHY; phy_idx < params->num_phys; phy_idx++) { 12103 struct bnx2x_phy *phy = ¶ms->phy[phy_idx]; 12104 if (phy->phy_specific_func) { 12105 DP(NETIF_MSG_LINK, "Calling PHY specific func\n"); 12106 phy->phy_specific_func(phy, params, PHY_INIT); 12107 } 12108 if ((phy->media_type == ETH_PHY_SFPP_10G_FIBER) || 12109 (phy->media_type == ETH_PHY_SFP_1G_FIBER) || 12110 (phy->media_type == ETH_PHY_DA_TWINAX)) 12111 bnx2x_verify_sfp_module(phy, params); 12112 } 12113 lfa_sts = REG_RD(bp, params->lfa_base + 12114 offsetof(struct shmem_lfa, 12115 lfa_sts)); 12116 12117 dont_clear_stat = lfa_sts & SHMEM_LFA_DONT_CLEAR_STAT; 12118 12119 /* Re-enable the NIG/MAC */ 12120 if (CHIP_IS_E3(bp)) { 12121 if (!dont_clear_stat) { 12122 REG_WR(bp, GRCBASE_MISC + 12123 MISC_REGISTERS_RESET_REG_2_CLEAR, 12124 (MISC_REGISTERS_RESET_REG_2_MSTAT0 << 12125 params->port)); 12126 REG_WR(bp, GRCBASE_MISC + 12127 MISC_REGISTERS_RESET_REG_2_SET, 12128 (MISC_REGISTERS_RESET_REG_2_MSTAT0 << 12129 params->port)); 12130 } 12131 if (vars->line_speed < SPEED_10000) 12132 bnx2x_umac_enable(params, vars, 0); 12133 else 12134 bnx2x_xmac_enable(params, vars, 0); 12135 } else { 12136 if (vars->line_speed < SPEED_10000) 12137 bnx2x_emac_enable(params, vars, 0); 12138 else 12139 bnx2x_bmac_enable(params, vars, 0, !dont_clear_stat); 12140 } 12141 12142 /* Increment LFA count */ 12143 lfa_sts = ((lfa_sts & ~LINK_FLAP_AVOIDANCE_COUNT_MASK) | 12144 (((((lfa_sts & LINK_FLAP_AVOIDANCE_COUNT_MASK) >> 12145 LINK_FLAP_AVOIDANCE_COUNT_OFFSET) + 1) & 0xff) 12146 << LINK_FLAP_AVOIDANCE_COUNT_OFFSET)); 12147 /* Clear link flap reason */ 12148 lfa_sts &= ~LFA_LINK_FLAP_REASON_MASK; 12149 12150 REG_WR(bp, params->lfa_base + 12151 offsetof(struct shmem_lfa, lfa_sts), lfa_sts); 12152 12153 /* Disable NIG DRAIN */ 12154 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); 12155 12156 /* Enable interrupts */ 12157 bnx2x_link_int_enable(params); 12158 return 0; 12159 } 12160 12161 static void bnx2x_cannot_avoid_link_flap(struct link_params *params, 12162 struct link_vars *vars, 12163 int lfa_status) 12164 { 12165 u32 lfa_sts, cfg_idx, tmp_val; 12166 struct bnx2x *bp = params->bp; 12167 12168 bnx2x_link_reset(params, vars, 1); 12169 12170 if (!params->lfa_base) 12171 return; 12172 /* Store the new link parameters */ 12173 REG_WR(bp, params->lfa_base + 12174 offsetof(struct shmem_lfa, req_duplex), 12175 params->req_duplex[0] | (params->req_duplex[1] << 16)); 12176 12177 REG_WR(bp, params->lfa_base + 12178 offsetof(struct shmem_lfa, req_flow_ctrl), 12179 params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16)); 12180 12181 REG_WR(bp, params->lfa_base + 12182 offsetof(struct shmem_lfa, req_line_speed), 12183 params->req_line_speed[0] | (params->req_line_speed[1] << 16)); 12184 12185 for (cfg_idx = 0; cfg_idx < SHMEM_LINK_CONFIG_SIZE; cfg_idx++) { 12186 REG_WR(bp, params->lfa_base + 12187 offsetof(struct shmem_lfa, 12188 speed_cap_mask[cfg_idx]), 12189 params->speed_cap_mask[cfg_idx]); 12190 } 12191 12192 tmp_val = REG_RD(bp, params->lfa_base + 12193 offsetof(struct shmem_lfa, additional_config)); 12194 tmp_val &= ~REQ_FC_AUTO_ADV_MASK; 12195 tmp_val |= params->req_fc_auto_adv; 12196 12197 REG_WR(bp, params->lfa_base + 12198 offsetof(struct shmem_lfa, additional_config), tmp_val); 12199 12200 lfa_sts = REG_RD(bp, params->lfa_base + 12201 offsetof(struct shmem_lfa, lfa_sts)); 12202 12203 /* Clear the "Don't Clear Statistics" bit, and set reason */ 12204 lfa_sts &= ~SHMEM_LFA_DONT_CLEAR_STAT; 12205 12206 /* Set link flap reason */ 12207 lfa_sts &= ~LFA_LINK_FLAP_REASON_MASK; 12208 lfa_sts |= ((lfa_status & LFA_LINK_FLAP_REASON_MASK) << 12209 LFA_LINK_FLAP_REASON_OFFSET); 12210 12211 /* Increment link flap counter */ 12212 lfa_sts = ((lfa_sts & ~LINK_FLAP_COUNT_MASK) | 12213 (((((lfa_sts & LINK_FLAP_COUNT_MASK) >> 12214 LINK_FLAP_COUNT_OFFSET) + 1) & 0xff) 12215 << LINK_FLAP_COUNT_OFFSET)); 12216 REG_WR(bp, params->lfa_base + 12217 offsetof(struct shmem_lfa, lfa_sts), lfa_sts); 12218 /* Proceed with regular link initialization */ 12219 } 12220 12221 int bnx2x_phy_init(struct link_params *params, struct link_vars *vars) 12222 { 12223 int lfa_status; 12224 struct bnx2x *bp = params->bp; 12225 DP(NETIF_MSG_LINK, "Phy Initialization started\n"); 12226 DP(NETIF_MSG_LINK, "(1) req_speed %d, req_flowctrl %d\n", 12227 params->req_line_speed[0], params->req_flow_ctrl[0]); 12228 DP(NETIF_MSG_LINK, "(2) req_speed %d, req_flowctrl %d\n", 12229 params->req_line_speed[1], params->req_flow_ctrl[1]); 12230 vars->link_status = 0; 12231 vars->phy_link_up = 0; 12232 vars->link_up = 0; 12233 vars->line_speed = 0; 12234 vars->duplex = DUPLEX_FULL; 12235 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; 12236 vars->mac_type = MAC_TYPE_NONE; 12237 vars->phy_flags = 0; 12238 /* Driver opens NIG-BRB filters */ 12239 bnx2x_set_rx_filter(params, 1); 12240 /* Check if link flap can be avoided */ 12241 lfa_status = bnx2x_check_lfa(params); 12242 12243 if (lfa_status == 0) { 12244 DP(NETIF_MSG_LINK, "Link Flap Avoidance in progress\n"); 12245 return bnx2x_avoid_link_flap(params, vars); 12246 } 12247 12248 DP(NETIF_MSG_LINK, "Cannot avoid link flap lfa_sta=0x%x\n", 12249 lfa_status); 12250 bnx2x_cannot_avoid_link_flap(params, vars, lfa_status); 12251 12252 /* Disable attentions */ 12253 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4, 12254 (NIG_MASK_XGXS0_LINK_STATUS | 12255 NIG_MASK_XGXS0_LINK10G | 12256 NIG_MASK_SERDES0_LINK_STATUS | 12257 NIG_MASK_MI_INT)); 12258 12259 bnx2x_emac_init(params, vars); 12260 12261 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) 12262 vars->link_status |= LINK_STATUS_PFC_ENABLED; 12263 12264 if (params->num_phys == 0) { 12265 DP(NETIF_MSG_LINK, "No phy found for initialization !!\n"); 12266 return -EINVAL; 12267 } 12268 set_phy_vars(params, vars); 12269 12270 DP(NETIF_MSG_LINK, "Num of phys on board: %d\n", params->num_phys); 12271 switch (params->loopback_mode) { 12272 case LOOPBACK_BMAC: 12273 bnx2x_init_bmac_loopback(params, vars); 12274 break; 12275 case LOOPBACK_EMAC: 12276 bnx2x_init_emac_loopback(params, vars); 12277 break; 12278 case LOOPBACK_XMAC: 12279 bnx2x_init_xmac_loopback(params, vars); 12280 break; 12281 case LOOPBACK_UMAC: 12282 bnx2x_init_umac_loopback(params, vars); 12283 break; 12284 case LOOPBACK_XGXS: 12285 case LOOPBACK_EXT_PHY: 12286 bnx2x_init_xgxs_loopback(params, vars); 12287 break; 12288 default: 12289 if (!CHIP_IS_E3(bp)) { 12290 if (params->switch_cfg == SWITCH_CFG_10G) 12291 bnx2x_xgxs_deassert(params); 12292 else 12293 bnx2x_serdes_deassert(bp, params->port); 12294 } 12295 bnx2x_link_initialize(params, vars); 12296 msleep(30); 12297 bnx2x_link_int_enable(params); 12298 break; 12299 } 12300 bnx2x_update_mng(params, vars->link_status); 12301 12302 bnx2x_update_mng_eee(params, vars->eee_status); 12303 return 0; 12304 } 12305 12306 int bnx2x_link_reset(struct link_params *params, struct link_vars *vars, 12307 u8 reset_ext_phy) 12308 { 12309 struct bnx2x *bp = params->bp; 12310 u8 phy_index, port = params->port, clear_latch_ind = 0; 12311 DP(NETIF_MSG_LINK, "Resetting the link of port %d\n", port); 12312 /* Disable attentions */ 12313 vars->link_status = 0; 12314 bnx2x_update_mng(params, vars->link_status); 12315 vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK | 12316 SHMEM_EEE_ACTIVE_BIT); 12317 bnx2x_update_mng_eee(params, vars->eee_status); 12318 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 12319 (NIG_MASK_XGXS0_LINK_STATUS | 12320 NIG_MASK_XGXS0_LINK10G | 12321 NIG_MASK_SERDES0_LINK_STATUS | 12322 NIG_MASK_MI_INT)); 12323 12324 /* Activate nig drain */ 12325 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1); 12326 12327 /* Disable nig egress interface */ 12328 if (!CHIP_IS_E3(bp)) { 12329 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0); 12330 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0); 12331 } 12332 12333 if (!CHIP_IS_E3(bp)) { 12334 bnx2x_set_bmac_rx(bp, params->chip_id, port, 0); 12335 } else { 12336 bnx2x_set_xmac_rxtx(params, 0); 12337 bnx2x_set_umac_rxtx(params, 0); 12338 } 12339 /* Disable emac */ 12340 if (!CHIP_IS_E3(bp)) 12341 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0); 12342 12343 usleep_range(10000, 20000); 12344 /* The PHY reset is controlled by GPIO 1 12345 * Hold it as vars low 12346 */ 12347 /* Clear link led */ 12348 bnx2x_set_mdio_clk(bp, params->chip_id, port); 12349 bnx2x_set_led(params, vars, LED_MODE_OFF, 0); 12350 12351 if (reset_ext_phy) { 12352 for (phy_index = EXT_PHY1; phy_index < params->num_phys; 12353 phy_index++) { 12354 if (params->phy[phy_index].link_reset) { 12355 bnx2x_set_aer_mmd(params, 12356 ¶ms->phy[phy_index]); 12357 params->phy[phy_index].link_reset( 12358 ¶ms->phy[phy_index], 12359 params); 12360 } 12361 if (params->phy[phy_index].flags & 12362 FLAGS_REARM_LATCH_SIGNAL) 12363 clear_latch_ind = 1; 12364 } 12365 } 12366 12367 if (clear_latch_ind) { 12368 /* Clear latching indication */ 12369 bnx2x_rearm_latch_signal(bp, port, 0); 12370 bnx2x_bits_dis(bp, NIG_REG_LATCH_BC_0 + port*4, 12371 1 << NIG_LATCH_BC_ENABLE_MI_INT); 12372 } 12373 if (params->phy[INT_PHY].link_reset) 12374 params->phy[INT_PHY].link_reset( 12375 ¶ms->phy[INT_PHY], params); 12376 12377 /* Disable nig ingress interface */ 12378 if (!CHIP_IS_E3(bp)) { 12379 /* Reset BigMac */ 12380 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 12381 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); 12382 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0); 12383 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0); 12384 } else { 12385 u32 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; 12386 bnx2x_set_xumac_nig(params, 0, 0); 12387 if (REG_RD(bp, MISC_REG_RESET_REG_2) & 12388 MISC_REGISTERS_RESET_REG_2_XMAC) 12389 REG_WR(bp, xmac_base + XMAC_REG_CTRL, 12390 XMAC_CTRL_REG_SOFT_RESET); 12391 } 12392 vars->link_up = 0; 12393 vars->phy_flags = 0; 12394 return 0; 12395 } 12396 int bnx2x_lfa_reset(struct link_params *params, 12397 struct link_vars *vars) 12398 { 12399 struct bnx2x *bp = params->bp; 12400 vars->link_up = 0; 12401 vars->phy_flags = 0; 12402 if (!params->lfa_base) 12403 return bnx2x_link_reset(params, vars, 1); 12404 /* 12405 * Activate NIG drain so that during this time the device won't send 12406 * anything while it is unable to response. 12407 */ 12408 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1); 12409 12410 /* 12411 * Close gracefully the gate from BMAC to NIG such that no half packets 12412 * are passed. 12413 */ 12414 if (!CHIP_IS_E3(bp)) 12415 bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 0); 12416 12417 if (CHIP_IS_E3(bp)) { 12418 bnx2x_set_xmac_rxtx(params, 0); 12419 bnx2x_set_umac_rxtx(params, 0); 12420 } 12421 /* Wait 10ms for the pipe to clean up*/ 12422 usleep_range(10000, 20000); 12423 12424 /* Clean the NIG-BRB using the network filters in a way that will 12425 * not cut a packet in the middle. 12426 */ 12427 bnx2x_set_rx_filter(params, 0); 12428 12429 /* 12430 * Re-open the gate between the BMAC and the NIG, after verifying the 12431 * gate to the BRB is closed, otherwise packets may arrive to the 12432 * firmware before driver had initialized it. The target is to achieve 12433 * minimum management protocol down time. 12434 */ 12435 if (!CHIP_IS_E3(bp)) 12436 bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 1); 12437 12438 if (CHIP_IS_E3(bp)) { 12439 bnx2x_set_xmac_rxtx(params, 1); 12440 bnx2x_set_umac_rxtx(params, 1); 12441 } 12442 /* Disable NIG drain */ 12443 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); 12444 return 0; 12445 } 12446 12447 /****************************************************************************/ 12448 /* Common function */ 12449 /****************************************************************************/ 12450 static int bnx2x_8073_common_init_phy(struct bnx2x *bp, 12451 u32 shmem_base_path[], 12452 u32 shmem2_base_path[], u8 phy_index, 12453 u32 chip_id) 12454 { 12455 struct bnx2x_phy phy[PORT_MAX]; 12456 struct bnx2x_phy *phy_blk[PORT_MAX]; 12457 u16 val; 12458 s8 port = 0; 12459 s8 port_of_path = 0; 12460 u32 swap_val, swap_override; 12461 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); 12462 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); 12463 port ^= (swap_val && swap_override); 12464 bnx2x_ext_phy_hw_reset(bp, port); 12465 /* PART1 - Reset both phys */ 12466 for (port = PORT_MAX - 1; port >= PORT_0; port--) { 12467 u32 shmem_base, shmem2_base; 12468 /* In E2, same phy is using for port0 of the two paths */ 12469 if (CHIP_IS_E1x(bp)) { 12470 shmem_base = shmem_base_path[0]; 12471 shmem2_base = shmem2_base_path[0]; 12472 port_of_path = port; 12473 } else { 12474 shmem_base = shmem_base_path[port]; 12475 shmem2_base = shmem2_base_path[port]; 12476 port_of_path = 0; 12477 } 12478 12479 /* Extract the ext phy address for the port */ 12480 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base, 12481 port_of_path, &phy[port]) != 12482 0) { 12483 DP(NETIF_MSG_LINK, "populate_phy failed\n"); 12484 return -EINVAL; 12485 } 12486 /* Disable attentions */ 12487 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + 12488 port_of_path*4, 12489 (NIG_MASK_XGXS0_LINK_STATUS | 12490 NIG_MASK_XGXS0_LINK10G | 12491 NIG_MASK_SERDES0_LINK_STATUS | 12492 NIG_MASK_MI_INT)); 12493 12494 /* Need to take the phy out of low power mode in order 12495 * to write to access its registers 12496 */ 12497 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 12498 MISC_REGISTERS_GPIO_OUTPUT_HIGH, 12499 port); 12500 12501 /* Reset the phy */ 12502 bnx2x_cl45_write(bp, &phy[port], 12503 MDIO_PMA_DEVAD, 12504 MDIO_PMA_REG_CTRL, 12505 1<<15); 12506 } 12507 12508 /* Add delay of 150ms after reset */ 12509 msleep(150); 12510 12511 if (phy[PORT_0].addr & 0x1) { 12512 phy_blk[PORT_0] = &(phy[PORT_1]); 12513 phy_blk[PORT_1] = &(phy[PORT_0]); 12514 } else { 12515 phy_blk[PORT_0] = &(phy[PORT_0]); 12516 phy_blk[PORT_1] = &(phy[PORT_1]); 12517 } 12518 12519 /* PART2 - Download firmware to both phys */ 12520 for (port = PORT_MAX - 1; port >= PORT_0; port--) { 12521 if (CHIP_IS_E1x(bp)) 12522 port_of_path = port; 12523 else 12524 port_of_path = 0; 12525 12526 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n", 12527 phy_blk[port]->addr); 12528 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port], 12529 port_of_path)) 12530 return -EINVAL; 12531 12532 /* Only set bit 10 = 1 (Tx power down) */ 12533 bnx2x_cl45_read(bp, phy_blk[port], 12534 MDIO_PMA_DEVAD, 12535 MDIO_PMA_REG_TX_POWER_DOWN, &val); 12536 12537 /* Phase1 of TX_POWER_DOWN reset */ 12538 bnx2x_cl45_write(bp, phy_blk[port], 12539 MDIO_PMA_DEVAD, 12540 MDIO_PMA_REG_TX_POWER_DOWN, 12541 (val | 1<<10)); 12542 } 12543 12544 /* Toggle Transmitter: Power down and then up with 600ms delay 12545 * between 12546 */ 12547 msleep(600); 12548 12549 /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */ 12550 for (port = PORT_MAX - 1; port >= PORT_0; port--) { 12551 /* Phase2 of POWER_DOWN_RESET */ 12552 /* Release bit 10 (Release Tx power down) */ 12553 bnx2x_cl45_read(bp, phy_blk[port], 12554 MDIO_PMA_DEVAD, 12555 MDIO_PMA_REG_TX_POWER_DOWN, &val); 12556 12557 bnx2x_cl45_write(bp, phy_blk[port], 12558 MDIO_PMA_DEVAD, 12559 MDIO_PMA_REG_TX_POWER_DOWN, (val & (~(1<<10)))); 12560 usleep_range(15000, 30000); 12561 12562 /* Read modify write the SPI-ROM version select register */ 12563 bnx2x_cl45_read(bp, phy_blk[port], 12564 MDIO_PMA_DEVAD, 12565 MDIO_PMA_REG_EDC_FFE_MAIN, &val); 12566 bnx2x_cl45_write(bp, phy_blk[port], 12567 MDIO_PMA_DEVAD, 12568 MDIO_PMA_REG_EDC_FFE_MAIN, (val | (1<<12))); 12569 12570 /* set GPIO2 back to LOW */ 12571 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 12572 MISC_REGISTERS_GPIO_OUTPUT_LOW, port); 12573 } 12574 return 0; 12575 } 12576 static int bnx2x_8726_common_init_phy(struct bnx2x *bp, 12577 u32 shmem_base_path[], 12578 u32 shmem2_base_path[], u8 phy_index, 12579 u32 chip_id) 12580 { 12581 u32 val; 12582 s8 port; 12583 struct bnx2x_phy phy; 12584 /* Use port1 because of the static port-swap */ 12585 /* Enable the module detection interrupt */ 12586 val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN); 12587 val |= ((1<<MISC_REGISTERS_GPIO_3)| 12588 (1<<(MISC_REGISTERS_GPIO_3 + MISC_REGISTERS_GPIO_PORT_SHIFT))); 12589 REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val); 12590 12591 bnx2x_ext_phy_hw_reset(bp, 0); 12592 usleep_range(5000, 10000); 12593 for (port = 0; port < PORT_MAX; port++) { 12594 u32 shmem_base, shmem2_base; 12595 12596 /* In E2, same phy is using for port0 of the two paths */ 12597 if (CHIP_IS_E1x(bp)) { 12598 shmem_base = shmem_base_path[0]; 12599 shmem2_base = shmem2_base_path[0]; 12600 } else { 12601 shmem_base = shmem_base_path[port]; 12602 shmem2_base = shmem2_base_path[port]; 12603 } 12604 /* Extract the ext phy address for the port */ 12605 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base, 12606 port, &phy) != 12607 0) { 12608 DP(NETIF_MSG_LINK, "populate phy failed\n"); 12609 return -EINVAL; 12610 } 12611 12612 /* Reset phy*/ 12613 bnx2x_cl45_write(bp, &phy, 12614 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001); 12615 12616 12617 /* Set fault module detected LED on */ 12618 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0, 12619 MISC_REGISTERS_GPIO_HIGH, 12620 port); 12621 } 12622 12623 return 0; 12624 } 12625 static void bnx2x_get_ext_phy_reset_gpio(struct bnx2x *bp, u32 shmem_base, 12626 u8 *io_gpio, u8 *io_port) 12627 { 12628 12629 u32 phy_gpio_reset = REG_RD(bp, shmem_base + 12630 offsetof(struct shmem_region, 12631 dev_info.port_hw_config[PORT_0].default_cfg)); 12632 switch (phy_gpio_reset) { 12633 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0: 12634 *io_gpio = 0; 12635 *io_port = 0; 12636 break; 12637 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0: 12638 *io_gpio = 1; 12639 *io_port = 0; 12640 break; 12641 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0: 12642 *io_gpio = 2; 12643 *io_port = 0; 12644 break; 12645 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0: 12646 *io_gpio = 3; 12647 *io_port = 0; 12648 break; 12649 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1: 12650 *io_gpio = 0; 12651 *io_port = 1; 12652 break; 12653 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1: 12654 *io_gpio = 1; 12655 *io_port = 1; 12656 break; 12657 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1: 12658 *io_gpio = 2; 12659 *io_port = 1; 12660 break; 12661 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1: 12662 *io_gpio = 3; 12663 *io_port = 1; 12664 break; 12665 default: 12666 /* Don't override the io_gpio and io_port */ 12667 break; 12668 } 12669 } 12670 12671 static int bnx2x_8727_common_init_phy(struct bnx2x *bp, 12672 u32 shmem_base_path[], 12673 u32 shmem2_base_path[], u8 phy_index, 12674 u32 chip_id) 12675 { 12676 s8 port, reset_gpio; 12677 u32 swap_val, swap_override; 12678 struct bnx2x_phy phy[PORT_MAX]; 12679 struct bnx2x_phy *phy_blk[PORT_MAX]; 12680 s8 port_of_path; 12681 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); 12682 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); 12683 12684 reset_gpio = MISC_REGISTERS_GPIO_1; 12685 port = 1; 12686 12687 /* Retrieve the reset gpio/port which control the reset. 12688 * Default is GPIO1, PORT1 12689 */ 12690 bnx2x_get_ext_phy_reset_gpio(bp, shmem_base_path[0], 12691 (u8 *)&reset_gpio, (u8 *)&port); 12692 12693 /* Calculate the port based on port swap */ 12694 port ^= (swap_val && swap_override); 12695 12696 /* Initiate PHY reset*/ 12697 bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_LOW, 12698 port); 12699 usleep_range(1000, 2000); 12700 bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_HIGH, 12701 port); 12702 12703 usleep_range(5000, 10000); 12704 12705 /* PART1 - Reset both phys */ 12706 for (port = PORT_MAX - 1; port >= PORT_0; port--) { 12707 u32 shmem_base, shmem2_base; 12708 12709 /* In E2, same phy is using for port0 of the two paths */ 12710 if (CHIP_IS_E1x(bp)) { 12711 shmem_base = shmem_base_path[0]; 12712 shmem2_base = shmem2_base_path[0]; 12713 port_of_path = port; 12714 } else { 12715 shmem_base = shmem_base_path[port]; 12716 shmem2_base = shmem2_base_path[port]; 12717 port_of_path = 0; 12718 } 12719 12720 /* Extract the ext phy address for the port */ 12721 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base, 12722 port_of_path, &phy[port]) != 12723 0) { 12724 DP(NETIF_MSG_LINK, "populate phy failed\n"); 12725 return -EINVAL; 12726 } 12727 /* disable attentions */ 12728 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + 12729 port_of_path*4, 12730 (NIG_MASK_XGXS0_LINK_STATUS | 12731 NIG_MASK_XGXS0_LINK10G | 12732 NIG_MASK_SERDES0_LINK_STATUS | 12733 NIG_MASK_MI_INT)); 12734 12735 12736 /* Reset the phy */ 12737 bnx2x_cl45_write(bp, &phy[port], 12738 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15); 12739 } 12740 12741 /* Add delay of 150ms after reset */ 12742 msleep(150); 12743 if (phy[PORT_0].addr & 0x1) { 12744 phy_blk[PORT_0] = &(phy[PORT_1]); 12745 phy_blk[PORT_1] = &(phy[PORT_0]); 12746 } else { 12747 phy_blk[PORT_0] = &(phy[PORT_0]); 12748 phy_blk[PORT_1] = &(phy[PORT_1]); 12749 } 12750 /* PART2 - Download firmware to both phys */ 12751 for (port = PORT_MAX - 1; port >= PORT_0; port--) { 12752 if (CHIP_IS_E1x(bp)) 12753 port_of_path = port; 12754 else 12755 port_of_path = 0; 12756 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n", 12757 phy_blk[port]->addr); 12758 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port], 12759 port_of_path)) 12760 return -EINVAL; 12761 /* Disable PHY transmitter output */ 12762 bnx2x_cl45_write(bp, phy_blk[port], 12763 MDIO_PMA_DEVAD, 12764 MDIO_PMA_REG_TX_DISABLE, 1); 12765 12766 } 12767 return 0; 12768 } 12769 12770 static int bnx2x_84833_common_init_phy(struct bnx2x *bp, 12771 u32 shmem_base_path[], 12772 u32 shmem2_base_path[], 12773 u8 phy_index, 12774 u32 chip_id) 12775 { 12776 u8 reset_gpios; 12777 reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path, chip_id); 12778 bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW); 12779 udelay(10); 12780 bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_HIGH); 12781 DP(NETIF_MSG_LINK, "84833 reset pulse on pin values 0x%x\n", 12782 reset_gpios); 12783 return 0; 12784 } 12785 12786 static int bnx2x_84833_pre_init_phy(struct bnx2x *bp, 12787 struct bnx2x_phy *phy) 12788 { 12789 u16 val, cnt; 12790 /* Wait for FW completing its initialization. */ 12791 for (cnt = 0; cnt < 1500; cnt++) { 12792 bnx2x_cl45_read(bp, phy, 12793 MDIO_PMA_DEVAD, 12794 MDIO_PMA_REG_CTRL, &val); 12795 if (!(val & (1<<15))) 12796 break; 12797 usleep_range(1000, 2000); 12798 } 12799 if (cnt >= 1500) { 12800 DP(NETIF_MSG_LINK, "84833 reset timeout\n"); 12801 return -EINVAL; 12802 } 12803 12804 /* Put the port in super isolate mode. */ 12805 bnx2x_cl45_read(bp, phy, 12806 MDIO_CTL_DEVAD, 12807 MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val); 12808 val |= MDIO_84833_SUPER_ISOLATE; 12809 bnx2x_cl45_write(bp, phy, 12810 MDIO_CTL_DEVAD, 12811 MDIO_84833_TOP_CFG_XGPHY_STRAP1, val); 12812 12813 /* Save spirom version */ 12814 bnx2x_save_848xx_spirom_version(phy, bp, PORT_0); 12815 return 0; 12816 } 12817 12818 int bnx2x_pre_init_phy(struct bnx2x *bp, 12819 u32 shmem_base, 12820 u32 shmem2_base, 12821 u32 chip_id) 12822 { 12823 int rc = 0; 12824 struct bnx2x_phy phy; 12825 bnx2x_set_mdio_clk(bp, chip_id, PORT_0); 12826 if (bnx2x_populate_phy(bp, EXT_PHY1, shmem_base, shmem2_base, 12827 PORT_0, &phy)) { 12828 DP(NETIF_MSG_LINK, "populate_phy failed\n"); 12829 return -EINVAL; 12830 } 12831 switch (phy.type) { 12832 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833: 12833 rc = bnx2x_84833_pre_init_phy(bp, &phy); 12834 break; 12835 default: 12836 break; 12837 } 12838 return rc; 12839 } 12840 12841 static int bnx2x_ext_phy_common_init(struct bnx2x *bp, u32 shmem_base_path[], 12842 u32 shmem2_base_path[], u8 phy_index, 12843 u32 ext_phy_type, u32 chip_id) 12844 { 12845 int rc = 0; 12846 12847 switch (ext_phy_type) { 12848 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073: 12849 rc = bnx2x_8073_common_init_phy(bp, shmem_base_path, 12850 shmem2_base_path, 12851 phy_index, chip_id); 12852 break; 12853 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722: 12854 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: 12855 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC: 12856 rc = bnx2x_8727_common_init_phy(bp, shmem_base_path, 12857 shmem2_base_path, 12858 phy_index, chip_id); 12859 break; 12860 12861 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: 12862 /* GPIO1 affects both ports, so there's need to pull 12863 * it for single port alone 12864 */ 12865 rc = bnx2x_8726_common_init_phy(bp, shmem_base_path, 12866 shmem2_base_path, 12867 phy_index, chip_id); 12868 break; 12869 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833: 12870 /* GPIO3's are linked, and so both need to be toggled 12871 * to obtain required 2us pulse. 12872 */ 12873 rc = bnx2x_84833_common_init_phy(bp, shmem_base_path, 12874 shmem2_base_path, 12875 phy_index, chip_id); 12876 break; 12877 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE: 12878 rc = -EINVAL; 12879 break; 12880 default: 12881 DP(NETIF_MSG_LINK, 12882 "ext_phy 0x%x common init not required\n", 12883 ext_phy_type); 12884 break; 12885 } 12886 12887 if (rc) 12888 netdev_err(bp->dev, "Warning: PHY was not initialized," 12889 " Port %d\n", 12890 0); 12891 return rc; 12892 } 12893 12894 int bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base_path[], 12895 u32 shmem2_base_path[], u32 chip_id) 12896 { 12897 int rc = 0; 12898 u32 phy_ver, val; 12899 u8 phy_index = 0; 12900 u32 ext_phy_type, ext_phy_config; 12901 bnx2x_set_mdio_clk(bp, chip_id, PORT_0); 12902 bnx2x_set_mdio_clk(bp, chip_id, PORT_1); 12903 DP(NETIF_MSG_LINK, "Begin common phy init\n"); 12904 if (CHIP_IS_E3(bp)) { 12905 /* Enable EPIO */ 12906 val = REG_RD(bp, MISC_REG_GEN_PURP_HWG); 12907 REG_WR(bp, MISC_REG_GEN_PURP_HWG, val | 1); 12908 } 12909 /* Check if common init was already done */ 12910 phy_ver = REG_RD(bp, shmem_base_path[0] + 12911 offsetof(struct shmem_region, 12912 port_mb[PORT_0].ext_phy_fw_version)); 12913 if (phy_ver) { 12914 DP(NETIF_MSG_LINK, "Not doing common init; phy ver is 0x%x\n", 12915 phy_ver); 12916 return 0; 12917 } 12918 12919 /* Read the ext_phy_type for arbitrary port(0) */ 12920 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS; 12921 phy_index++) { 12922 ext_phy_config = bnx2x_get_ext_phy_config(bp, 12923 shmem_base_path[0], 12924 phy_index, 0); 12925 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config); 12926 rc |= bnx2x_ext_phy_common_init(bp, shmem_base_path, 12927 shmem2_base_path, 12928 phy_index, ext_phy_type, 12929 chip_id); 12930 } 12931 return rc; 12932 } 12933 12934 static void bnx2x_check_over_curr(struct link_params *params, 12935 struct link_vars *vars) 12936 { 12937 struct bnx2x *bp = params->bp; 12938 u32 cfg_pin; 12939 u8 port = params->port; 12940 u32 pin_val; 12941 12942 cfg_pin = (REG_RD(bp, params->shmem_base + 12943 offsetof(struct shmem_region, 12944 dev_info.port_hw_config[port].e3_cmn_pin_cfg1)) & 12945 PORT_HW_CFG_E3_OVER_CURRENT_MASK) >> 12946 PORT_HW_CFG_E3_OVER_CURRENT_SHIFT; 12947 12948 /* Ignore check if no external input PIN available */ 12949 if (bnx2x_get_cfg_pin(bp, cfg_pin, &pin_val) != 0) 12950 return; 12951 12952 if (!pin_val) { 12953 if ((vars->phy_flags & PHY_OVER_CURRENT_FLAG) == 0) { 12954 netdev_err(bp->dev, "Error: Power fault on Port %d has" 12955 " been detected and the power to " 12956 "that SFP+ module has been removed" 12957 " to prevent failure of the card." 12958 " Please remove the SFP+ module and" 12959 " restart the system to clear this" 12960 " error.\n", 12961 params->port); 12962 vars->phy_flags |= PHY_OVER_CURRENT_FLAG; 12963 } 12964 } else 12965 vars->phy_flags &= ~PHY_OVER_CURRENT_FLAG; 12966 } 12967 12968 /* Returns 0 if no change occured since last check; 1 otherwise. */ 12969 static u8 bnx2x_analyze_link_error(struct link_params *params, 12970 struct link_vars *vars, u32 status, 12971 u32 phy_flag, u32 link_flag, u8 notify) 12972 { 12973 struct bnx2x *bp = params->bp; 12974 /* Compare new value with previous value */ 12975 u8 led_mode; 12976 u32 old_status = (vars->phy_flags & phy_flag) ? 1 : 0; 12977 12978 if ((status ^ old_status) == 0) 12979 return 0; 12980 12981 /* If values differ */ 12982 switch (phy_flag) { 12983 case PHY_HALF_OPEN_CONN_FLAG: 12984 DP(NETIF_MSG_LINK, "Analyze Remote Fault\n"); 12985 break; 12986 case PHY_SFP_TX_FAULT_FLAG: 12987 DP(NETIF_MSG_LINK, "Analyze TX Fault\n"); 12988 break; 12989 default: 12990 DP(NETIF_MSG_LINK, "Analyze UNKNOWN\n"); 12991 } 12992 DP(NETIF_MSG_LINK, "Link changed:[%x %x]->%x\n", vars->link_up, 12993 old_status, status); 12994 12995 /* a. Update shmem->link_status accordingly 12996 * b. Update link_vars->link_up 12997 */ 12998 if (status) { 12999 vars->link_status &= ~LINK_STATUS_LINK_UP; 13000 vars->link_status |= link_flag; 13001 vars->link_up = 0; 13002 vars->phy_flags |= phy_flag; 13003 13004 /* activate nig drain */ 13005 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1); 13006 /* Set LED mode to off since the PHY doesn't know about these 13007 * errors 13008 */ 13009 led_mode = LED_MODE_OFF; 13010 } else { 13011 vars->link_status |= LINK_STATUS_LINK_UP; 13012 vars->link_status &= ~link_flag; 13013 vars->link_up = 1; 13014 vars->phy_flags &= ~phy_flag; 13015 led_mode = LED_MODE_OPER; 13016 13017 /* Clear nig drain */ 13018 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); 13019 } 13020 bnx2x_sync_link(params, vars); 13021 /* Update the LED according to the link state */ 13022 bnx2x_set_led(params, vars, led_mode, SPEED_10000); 13023 13024 /* Update link status in the shared memory */ 13025 bnx2x_update_mng(params, vars->link_status); 13026 13027 /* C. Trigger General Attention */ 13028 vars->periodic_flags |= PERIODIC_FLAGS_LINK_EVENT; 13029 if (notify) 13030 bnx2x_notify_link_changed(bp); 13031 13032 return 1; 13033 } 13034 13035 /****************************************************************************** 13036 * Description: 13037 * This function checks for half opened connection change indication. 13038 * When such change occurs, it calls the bnx2x_analyze_link_error 13039 * to check if Remote Fault is set or cleared. Reception of remote fault 13040 * status message in the MAC indicates that the peer's MAC has detected 13041 * a fault, for example, due to break in the TX side of fiber. 13042 * 13043 ******************************************************************************/ 13044 int bnx2x_check_half_open_conn(struct link_params *params, 13045 struct link_vars *vars, 13046 u8 notify) 13047 { 13048 struct bnx2x *bp = params->bp; 13049 u32 lss_status = 0; 13050 u32 mac_base; 13051 /* In case link status is physically up @ 10G do */ 13052 if (((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0) || 13053 (REG_RD(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4))) 13054 return 0; 13055 13056 if (CHIP_IS_E3(bp) && 13057 (REG_RD(bp, MISC_REG_RESET_REG_2) & 13058 (MISC_REGISTERS_RESET_REG_2_XMAC))) { 13059 /* Check E3 XMAC */ 13060 /* Note that link speed cannot be queried here, since it may be 13061 * zero while link is down. In case UMAC is active, LSS will 13062 * simply not be set 13063 */ 13064 mac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; 13065 13066 /* Clear stick bits (Requires rising edge) */ 13067 REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0); 13068 REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 13069 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS | 13070 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS); 13071 if (REG_RD(bp, mac_base + XMAC_REG_RX_LSS_STATUS)) 13072 lss_status = 1; 13073 13074 bnx2x_analyze_link_error(params, vars, lss_status, 13075 PHY_HALF_OPEN_CONN_FLAG, 13076 LINK_STATUS_NONE, notify); 13077 } else if (REG_RD(bp, MISC_REG_RESET_REG_2) & 13078 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port)) { 13079 /* Check E1X / E2 BMAC */ 13080 u32 lss_status_reg; 13081 u32 wb_data[2]; 13082 mac_base = params->port ? NIG_REG_INGRESS_BMAC1_MEM : 13083 NIG_REG_INGRESS_BMAC0_MEM; 13084 /* Read BIGMAC_REGISTER_RX_LSS_STATUS */ 13085 if (CHIP_IS_E2(bp)) 13086 lss_status_reg = BIGMAC2_REGISTER_RX_LSS_STAT; 13087 else 13088 lss_status_reg = BIGMAC_REGISTER_RX_LSS_STATUS; 13089 13090 REG_RD_DMAE(bp, mac_base + lss_status_reg, wb_data, 2); 13091 lss_status = (wb_data[0] > 0); 13092 13093 bnx2x_analyze_link_error(params, vars, lss_status, 13094 PHY_HALF_OPEN_CONN_FLAG, 13095 LINK_STATUS_NONE, notify); 13096 } 13097 return 0; 13098 } 13099 static void bnx2x_sfp_tx_fault_detection(struct bnx2x_phy *phy, 13100 struct link_params *params, 13101 struct link_vars *vars) 13102 { 13103 struct bnx2x *bp = params->bp; 13104 u32 cfg_pin, value = 0; 13105 u8 led_change, port = params->port; 13106 13107 /* Get The SFP+ TX_Fault controlling pin ([eg]pio) */ 13108 cfg_pin = (REG_RD(bp, params->shmem_base + offsetof(struct shmem_region, 13109 dev_info.port_hw_config[port].e3_cmn_pin_cfg)) & 13110 PORT_HW_CFG_E3_TX_FAULT_MASK) >> 13111 PORT_HW_CFG_E3_TX_FAULT_SHIFT; 13112 13113 if (bnx2x_get_cfg_pin(bp, cfg_pin, &value)) { 13114 DP(NETIF_MSG_LINK, "Failed to read pin 0x%02x\n", cfg_pin); 13115 return; 13116 } 13117 13118 led_change = bnx2x_analyze_link_error(params, vars, value, 13119 PHY_SFP_TX_FAULT_FLAG, 13120 LINK_STATUS_SFP_TX_FAULT, 1); 13121 13122 if (led_change) { 13123 /* Change TX_Fault led, set link status for further syncs */ 13124 u8 led_mode; 13125 13126 if (vars->phy_flags & PHY_SFP_TX_FAULT_FLAG) { 13127 led_mode = MISC_REGISTERS_GPIO_HIGH; 13128 vars->link_status |= LINK_STATUS_SFP_TX_FAULT; 13129 } else { 13130 led_mode = MISC_REGISTERS_GPIO_LOW; 13131 vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT; 13132 } 13133 13134 /* If module is unapproved, led should be on regardless */ 13135 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED)) { 13136 DP(NETIF_MSG_LINK, "Change TX_Fault LED: ->%x\n", 13137 led_mode); 13138 bnx2x_set_e3_module_fault_led(params, led_mode); 13139 } 13140 } 13141 } 13142 void bnx2x_period_func(struct link_params *params, struct link_vars *vars) 13143 { 13144 u16 phy_idx; 13145 struct bnx2x *bp = params->bp; 13146 for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) { 13147 if (params->phy[phy_idx].flags & FLAGS_TX_ERROR_CHECK) { 13148 bnx2x_set_aer_mmd(params, ¶ms->phy[phy_idx]); 13149 if (bnx2x_check_half_open_conn(params, vars, 1) != 13150 0) 13151 DP(NETIF_MSG_LINK, "Fault detection failed\n"); 13152 break; 13153 } 13154 } 13155 13156 if (CHIP_IS_E3(bp)) { 13157 struct bnx2x_phy *phy = ¶ms->phy[INT_PHY]; 13158 bnx2x_set_aer_mmd(params, phy); 13159 bnx2x_check_over_curr(params, vars); 13160 if (vars->rx_tx_asic_rst) 13161 bnx2x_warpcore_config_runtime(phy, params, vars); 13162 13163 if ((REG_RD(bp, params->shmem_base + 13164 offsetof(struct shmem_region, dev_info. 13165 port_hw_config[params->port].default_cfg)) 13166 & PORT_HW_CFG_NET_SERDES_IF_MASK) == 13167 PORT_HW_CFG_NET_SERDES_IF_SFI) { 13168 if (bnx2x_is_sfp_module_plugged(phy, params)) { 13169 bnx2x_sfp_tx_fault_detection(phy, params, vars); 13170 } else if (vars->link_status & 13171 LINK_STATUS_SFP_TX_FAULT) { 13172 /* Clean trail, interrupt corrects the leds */ 13173 vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT; 13174 vars->phy_flags &= ~PHY_SFP_TX_FAULT_FLAG; 13175 /* Update link status in the shared memory */ 13176 bnx2x_update_mng(params, vars->link_status); 13177 } 13178 } 13179 13180 } 13181 13182 } 13183 13184 u8 bnx2x_hw_lock_required(struct bnx2x *bp, u32 shmem_base, u32 shmem2_base) 13185 { 13186 u8 phy_index; 13187 struct bnx2x_phy phy; 13188 for (phy_index = INT_PHY; phy_index < MAX_PHYS; 13189 phy_index++) { 13190 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base, 13191 0, &phy) != 0) { 13192 DP(NETIF_MSG_LINK, "populate phy failed\n"); 13193 return 0; 13194 } 13195 13196 if (phy.flags & FLAGS_HW_LOCK_REQUIRED) 13197 return 1; 13198 } 13199 return 0; 13200 } 13201 13202 u8 bnx2x_fan_failure_det_req(struct bnx2x *bp, 13203 u32 shmem_base, 13204 u32 shmem2_base, 13205 u8 port) 13206 { 13207 u8 phy_index, fan_failure_det_req = 0; 13208 struct bnx2x_phy phy; 13209 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS; 13210 phy_index++) { 13211 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base, 13212 port, &phy) 13213 != 0) { 13214 DP(NETIF_MSG_LINK, "populate phy failed\n"); 13215 return 0; 13216 } 13217 fan_failure_det_req |= (phy.flags & 13218 FLAGS_FAN_FAILURE_DET_REQ); 13219 } 13220 return fan_failure_det_req; 13221 } 13222 13223 void bnx2x_hw_reset_phy(struct link_params *params) 13224 { 13225 u8 phy_index; 13226 struct bnx2x *bp = params->bp; 13227 bnx2x_update_mng(params, 0); 13228 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4, 13229 (NIG_MASK_XGXS0_LINK_STATUS | 13230 NIG_MASK_XGXS0_LINK10G | 13231 NIG_MASK_SERDES0_LINK_STATUS | 13232 NIG_MASK_MI_INT)); 13233 13234 for (phy_index = INT_PHY; phy_index < MAX_PHYS; 13235 phy_index++) { 13236 if (params->phy[phy_index].hw_reset) { 13237 params->phy[phy_index].hw_reset( 13238 ¶ms->phy[phy_index], 13239 params); 13240 params->phy[phy_index] = phy_null; 13241 } 13242 } 13243 } 13244 13245 void bnx2x_init_mod_abs_int(struct bnx2x *bp, struct link_vars *vars, 13246 u32 chip_id, u32 shmem_base, u32 shmem2_base, 13247 u8 port) 13248 { 13249 u8 gpio_num = 0xff, gpio_port = 0xff, phy_index; 13250 u32 val; 13251 u32 offset, aeu_mask, swap_val, swap_override, sync_offset; 13252 if (CHIP_IS_E3(bp)) { 13253 if (bnx2x_get_mod_abs_int_cfg(bp, chip_id, 13254 shmem_base, 13255 port, 13256 &gpio_num, 13257 &gpio_port) != 0) 13258 return; 13259 } else { 13260 struct bnx2x_phy phy; 13261 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS; 13262 phy_index++) { 13263 if (bnx2x_populate_phy(bp, phy_index, shmem_base, 13264 shmem2_base, port, &phy) 13265 != 0) { 13266 DP(NETIF_MSG_LINK, "populate phy failed\n"); 13267 return; 13268 } 13269 if (phy.type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) { 13270 gpio_num = MISC_REGISTERS_GPIO_3; 13271 gpio_port = port; 13272 break; 13273 } 13274 } 13275 } 13276 13277 if (gpio_num == 0xff) 13278 return; 13279 13280 /* Set GPIO3 to trigger SFP+ module insertion/removal */ 13281 bnx2x_set_gpio(bp, gpio_num, MISC_REGISTERS_GPIO_INPUT_HI_Z, gpio_port); 13282 13283 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); 13284 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); 13285 gpio_port ^= (swap_val && swap_override); 13286 13287 vars->aeu_int_mask = AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 << 13288 (gpio_num + (gpio_port << 2)); 13289 13290 sync_offset = shmem_base + 13291 offsetof(struct shmem_region, 13292 dev_info.port_hw_config[port].aeu_int_mask); 13293 REG_WR(bp, sync_offset, vars->aeu_int_mask); 13294 13295 DP(NETIF_MSG_LINK, "Setting MOD_ABS (GPIO%d_P%d) AEU to 0x%x\n", 13296 gpio_num, gpio_port, vars->aeu_int_mask); 13297 13298 if (port == 0) 13299 offset = MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0; 13300 else 13301 offset = MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0; 13302 13303 /* Open appropriate AEU for interrupts */ 13304 aeu_mask = REG_RD(bp, offset); 13305 aeu_mask |= vars->aeu_int_mask; 13306 REG_WR(bp, offset, aeu_mask); 13307 13308 /* Enable the GPIO to trigger interrupt */ 13309 val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN); 13310 val |= 1 << (gpio_num + (gpio_port << 2)); 13311 REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val); 13312 } 13313