1 /* bnx2x_hsi.h: Broadcom Everest network driver. 2 * 3 * Copyright (c) 2007-2013 Broadcom Corporation 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation. 8 */ 9 #ifndef BNX2X_HSI_H 10 #define BNX2X_HSI_H 11 12 #include "bnx2x_fw_defs.h" 13 #include "bnx2x_mfw_req.h" 14 15 #define FW_ENCODE_32BIT_PATTERN 0x1e1e1e1e 16 17 struct license_key { 18 u32 reserved[6]; 19 20 u32 max_iscsi_conn; 21 #define BNX2X_MAX_ISCSI_TRGT_CONN_MASK 0xFFFF 22 #define BNX2X_MAX_ISCSI_TRGT_CONN_SHIFT 0 23 #define BNX2X_MAX_ISCSI_INIT_CONN_MASK 0xFFFF0000 24 #define BNX2X_MAX_ISCSI_INIT_CONN_SHIFT 16 25 26 u32 reserved_a; 27 28 u32 max_fcoe_conn; 29 #define BNX2X_MAX_FCOE_TRGT_CONN_MASK 0xFFFF 30 #define BNX2X_MAX_FCOE_TRGT_CONN_SHIFT 0 31 #define BNX2X_MAX_FCOE_INIT_CONN_MASK 0xFFFF0000 32 #define BNX2X_MAX_FCOE_INIT_CONN_SHIFT 16 33 34 u32 reserved_b[4]; 35 }; 36 37 /**************************************************************************** 38 * Shared HW configuration * 39 ****************************************************************************/ 40 #define PIN_CFG_NA 0x00000000 41 #define PIN_CFG_GPIO0_P0 0x00000001 42 #define PIN_CFG_GPIO1_P0 0x00000002 43 #define PIN_CFG_GPIO2_P0 0x00000003 44 #define PIN_CFG_GPIO3_P0 0x00000004 45 #define PIN_CFG_GPIO0_P1 0x00000005 46 #define PIN_CFG_GPIO1_P1 0x00000006 47 #define PIN_CFG_GPIO2_P1 0x00000007 48 #define PIN_CFG_GPIO3_P1 0x00000008 49 #define PIN_CFG_EPIO0 0x00000009 50 #define PIN_CFG_EPIO1 0x0000000a 51 #define PIN_CFG_EPIO2 0x0000000b 52 #define PIN_CFG_EPIO3 0x0000000c 53 #define PIN_CFG_EPIO4 0x0000000d 54 #define PIN_CFG_EPIO5 0x0000000e 55 #define PIN_CFG_EPIO6 0x0000000f 56 #define PIN_CFG_EPIO7 0x00000010 57 #define PIN_CFG_EPIO8 0x00000011 58 #define PIN_CFG_EPIO9 0x00000012 59 #define PIN_CFG_EPIO10 0x00000013 60 #define PIN_CFG_EPIO11 0x00000014 61 #define PIN_CFG_EPIO12 0x00000015 62 #define PIN_CFG_EPIO13 0x00000016 63 #define PIN_CFG_EPIO14 0x00000017 64 #define PIN_CFG_EPIO15 0x00000018 65 #define PIN_CFG_EPIO16 0x00000019 66 #define PIN_CFG_EPIO17 0x0000001a 67 #define PIN_CFG_EPIO18 0x0000001b 68 #define PIN_CFG_EPIO19 0x0000001c 69 #define PIN_CFG_EPIO20 0x0000001d 70 #define PIN_CFG_EPIO21 0x0000001e 71 #define PIN_CFG_EPIO22 0x0000001f 72 #define PIN_CFG_EPIO23 0x00000020 73 #define PIN_CFG_EPIO24 0x00000021 74 #define PIN_CFG_EPIO25 0x00000022 75 #define PIN_CFG_EPIO26 0x00000023 76 #define PIN_CFG_EPIO27 0x00000024 77 #define PIN_CFG_EPIO28 0x00000025 78 #define PIN_CFG_EPIO29 0x00000026 79 #define PIN_CFG_EPIO30 0x00000027 80 #define PIN_CFG_EPIO31 0x00000028 81 82 /* EPIO definition */ 83 #define EPIO_CFG_NA 0x00000000 84 #define EPIO_CFG_EPIO0 0x00000001 85 #define EPIO_CFG_EPIO1 0x00000002 86 #define EPIO_CFG_EPIO2 0x00000003 87 #define EPIO_CFG_EPIO3 0x00000004 88 #define EPIO_CFG_EPIO4 0x00000005 89 #define EPIO_CFG_EPIO5 0x00000006 90 #define EPIO_CFG_EPIO6 0x00000007 91 #define EPIO_CFG_EPIO7 0x00000008 92 #define EPIO_CFG_EPIO8 0x00000009 93 #define EPIO_CFG_EPIO9 0x0000000a 94 #define EPIO_CFG_EPIO10 0x0000000b 95 #define EPIO_CFG_EPIO11 0x0000000c 96 #define EPIO_CFG_EPIO12 0x0000000d 97 #define EPIO_CFG_EPIO13 0x0000000e 98 #define EPIO_CFG_EPIO14 0x0000000f 99 #define EPIO_CFG_EPIO15 0x00000010 100 #define EPIO_CFG_EPIO16 0x00000011 101 #define EPIO_CFG_EPIO17 0x00000012 102 #define EPIO_CFG_EPIO18 0x00000013 103 #define EPIO_CFG_EPIO19 0x00000014 104 #define EPIO_CFG_EPIO20 0x00000015 105 #define EPIO_CFG_EPIO21 0x00000016 106 #define EPIO_CFG_EPIO22 0x00000017 107 #define EPIO_CFG_EPIO23 0x00000018 108 #define EPIO_CFG_EPIO24 0x00000019 109 #define EPIO_CFG_EPIO25 0x0000001a 110 #define EPIO_CFG_EPIO26 0x0000001b 111 #define EPIO_CFG_EPIO27 0x0000001c 112 #define EPIO_CFG_EPIO28 0x0000001d 113 #define EPIO_CFG_EPIO29 0x0000001e 114 #define EPIO_CFG_EPIO30 0x0000001f 115 #define EPIO_CFG_EPIO31 0x00000020 116 117 struct mac_addr { 118 u32 upper; 119 u32 lower; 120 }; 121 122 struct shared_hw_cfg { /* NVRAM Offset */ 123 /* Up to 16 bytes of NULL-terminated string */ 124 u8 part_num[16]; /* 0x104 */ 125 126 u32 config; /* 0x114 */ 127 #define SHARED_HW_CFG_MDIO_VOLTAGE_MASK 0x00000001 128 #define SHARED_HW_CFG_MDIO_VOLTAGE_SHIFT 0 129 #define SHARED_HW_CFG_MDIO_VOLTAGE_1_2V 0x00000000 130 #define SHARED_HW_CFG_MDIO_VOLTAGE_2_5V 0x00000001 131 #define SHARED_HW_CFG_MCP_RST_ON_CORE_RST_EN 0x00000002 132 133 #define SHARED_HW_CFG_PORT_SWAP 0x00000004 134 135 #define SHARED_HW_CFG_BEACON_WOL_EN 0x00000008 136 137 #define SHARED_HW_CFG_PCIE_GEN3_DISABLED 0x00000000 138 #define SHARED_HW_CFG_PCIE_GEN3_ENABLED 0x00000010 139 140 #define SHARED_HW_CFG_MFW_SELECT_MASK 0x00000700 141 #define SHARED_HW_CFG_MFW_SELECT_SHIFT 8 142 /* Whatever MFW found in NVM 143 (if multiple found, priority order is: NC-SI, UMP, IPMI) */ 144 #define SHARED_HW_CFG_MFW_SELECT_DEFAULT 0x00000000 145 #define SHARED_HW_CFG_MFW_SELECT_NC_SI 0x00000100 146 #define SHARED_HW_CFG_MFW_SELECT_UMP 0x00000200 147 #define SHARED_HW_CFG_MFW_SELECT_IPMI 0x00000300 148 /* Use SPIO4 as an arbiter between: 0-NC_SI, 1-IPMI 149 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */ 150 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_IPMI 0x00000400 151 /* Use SPIO4 as an arbiter between: 0-UMP, 1-IPMI 152 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */ 153 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_UMP_IPMI 0x00000500 154 /* Use SPIO4 as an arbiter between: 0-NC-SI, 1-UMP 155 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */ 156 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_UMP 0x00000600 157 158 #define SHARED_HW_CFG_LED_MODE_MASK 0x000f0000 159 #define SHARED_HW_CFG_LED_MODE_SHIFT 16 160 #define SHARED_HW_CFG_LED_MAC1 0x00000000 161 #define SHARED_HW_CFG_LED_PHY1 0x00010000 162 #define SHARED_HW_CFG_LED_PHY2 0x00020000 163 #define SHARED_HW_CFG_LED_PHY3 0x00030000 164 #define SHARED_HW_CFG_LED_MAC2 0x00040000 165 #define SHARED_HW_CFG_LED_PHY4 0x00050000 166 #define SHARED_HW_CFG_LED_PHY5 0x00060000 167 #define SHARED_HW_CFG_LED_PHY6 0x00070000 168 #define SHARED_HW_CFG_LED_MAC3 0x00080000 169 #define SHARED_HW_CFG_LED_PHY7 0x00090000 170 #define SHARED_HW_CFG_LED_PHY9 0x000a0000 171 #define SHARED_HW_CFG_LED_PHY11 0x000b0000 172 #define SHARED_HW_CFG_LED_MAC4 0x000c0000 173 #define SHARED_HW_CFG_LED_PHY8 0x000d0000 174 #define SHARED_HW_CFG_LED_EXTPHY1 0x000e0000 175 176 177 #define SHARED_HW_CFG_AN_ENABLE_MASK 0x3f000000 178 #define SHARED_HW_CFG_AN_ENABLE_SHIFT 24 179 #define SHARED_HW_CFG_AN_ENABLE_CL37 0x01000000 180 #define SHARED_HW_CFG_AN_ENABLE_CL73 0x02000000 181 #define SHARED_HW_CFG_AN_ENABLE_BAM 0x04000000 182 #define SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION 0x08000000 183 #define SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT 0x10000000 184 #define SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY 0x20000000 185 186 #define SHARED_HW_CFG_SRIOV_MASK 0x40000000 187 #define SHARED_HW_CFG_SRIOV_DISABLED 0x00000000 188 #define SHARED_HW_CFG_SRIOV_ENABLED 0x40000000 189 190 #define SHARED_HW_CFG_ATC_MASK 0x80000000 191 #define SHARED_HW_CFG_ATC_DISABLED 0x00000000 192 #define SHARED_HW_CFG_ATC_ENABLED 0x80000000 193 194 u32 config2; /* 0x118 */ 195 /* one time auto detect grace period (in sec) */ 196 #define SHARED_HW_CFG_GRACE_PERIOD_MASK 0x000000ff 197 #define SHARED_HW_CFG_GRACE_PERIOD_SHIFT 0 198 199 #define SHARED_HW_CFG_PCIE_GEN2_ENABLED 0x00000100 200 #define SHARED_HW_CFG_PCIE_GEN2_DISABLED 0x00000000 201 202 /* The default value for the core clock is 250MHz and it is 203 achieved by setting the clock change to 4 */ 204 #define SHARED_HW_CFG_CLOCK_CHANGE_MASK 0x00000e00 205 #define SHARED_HW_CFG_CLOCK_CHANGE_SHIFT 9 206 207 #define SHARED_HW_CFG_SMBUS_TIMING_MASK 0x00001000 208 #define SHARED_HW_CFG_SMBUS_TIMING_100KHZ 0x00000000 209 #define SHARED_HW_CFG_SMBUS_TIMING_400KHZ 0x00001000 210 211 #define SHARED_HW_CFG_HIDE_PORT1 0x00002000 212 213 #define SHARED_HW_CFG_WOL_CAPABLE_MASK 0x00004000 214 #define SHARED_HW_CFG_WOL_CAPABLE_DISABLED 0x00000000 215 #define SHARED_HW_CFG_WOL_CAPABLE_ENABLED 0x00004000 216 217 /* Output low when PERST is asserted */ 218 #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_MASK 0x00008000 219 #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_DISABLED 0x00000000 220 #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_ENABLED 0x00008000 221 222 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_MASK 0x00070000 223 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_SHIFT 16 224 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_HW 0x00000000 225 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_0DB 0x00010000 226 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_3_5DB 0x00020000 227 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_6_0DB 0x00030000 228 229 /* The fan failure mechanism is usually related to the PHY type 230 since the power consumption of the board is determined by the PHY. 231 Currently, fan is required for most designs with SFX7101, BCM8727 232 and BCM8481. If a fan is not required for a board which uses one 233 of those PHYs, this field should be set to "Disabled". If a fan is 234 required for a different PHY type, this option should be set to 235 "Enabled". The fan failure indication is expected on SPIO5 */ 236 #define SHARED_HW_CFG_FAN_FAILURE_MASK 0x00180000 237 #define SHARED_HW_CFG_FAN_FAILURE_SHIFT 19 238 #define SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE 0x00000000 239 #define SHARED_HW_CFG_FAN_FAILURE_DISABLED 0x00080000 240 #define SHARED_HW_CFG_FAN_FAILURE_ENABLED 0x00100000 241 242 /* ASPM Power Management support */ 243 #define SHARED_HW_CFG_ASPM_SUPPORT_MASK 0x00600000 244 #define SHARED_HW_CFG_ASPM_SUPPORT_SHIFT 21 245 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_ENABLED 0x00000000 246 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_DISABLED 0x00200000 247 #define SHARED_HW_CFG_ASPM_SUPPORT_L1_DISABLED 0x00400000 248 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_DISABLED 0x00600000 249 250 /* The value of PM_TL_IGNORE_REQS (bit0) in PCI register 251 tl_control_0 (register 0x2800) */ 252 #define SHARED_HW_CFG_PREVENT_L1_ENTRY_MASK 0x00800000 253 #define SHARED_HW_CFG_PREVENT_L1_ENTRY_DISABLED 0x00000000 254 #define SHARED_HW_CFG_PREVENT_L1_ENTRY_ENABLED 0x00800000 255 256 #define SHARED_HW_CFG_PORT_MODE_MASK 0x01000000 257 #define SHARED_HW_CFG_PORT_MODE_2 0x00000000 258 #define SHARED_HW_CFG_PORT_MODE_4 0x01000000 259 260 #define SHARED_HW_CFG_PATH_SWAP_MASK 0x02000000 261 #define SHARED_HW_CFG_PATH_SWAP_DISABLED 0x00000000 262 #define SHARED_HW_CFG_PATH_SWAP_ENABLED 0x02000000 263 264 /* Set the MDC/MDIO access for the first external phy */ 265 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK 0x1C000000 266 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT 26 267 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE 0x00000000 268 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0 0x04000000 269 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1 0x08000000 270 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH 0x0c000000 271 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED 0x10000000 272 273 /* Set the MDC/MDIO access for the second external phy */ 274 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK 0xE0000000 275 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT 29 276 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_PHY_TYPE 0x00000000 277 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC0 0x20000000 278 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC1 0x40000000 279 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_BOTH 0x60000000 280 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SWAPPED 0x80000000 281 282 283 u32 power_dissipated; /* 0x11c */ 284 #define SHARED_HW_CFG_POWER_MGNT_SCALE_MASK 0x00ff0000 285 #define SHARED_HW_CFG_POWER_MGNT_SCALE_SHIFT 16 286 #define SHARED_HW_CFG_POWER_MGNT_UNKNOWN_SCALE 0x00000000 287 #define SHARED_HW_CFG_POWER_MGNT_DOT_1_WATT 0x00010000 288 #define SHARED_HW_CFG_POWER_MGNT_DOT_01_WATT 0x00020000 289 #define SHARED_HW_CFG_POWER_MGNT_DOT_001_WATT 0x00030000 290 291 #define SHARED_HW_CFG_POWER_DIS_CMN_MASK 0xff000000 292 #define SHARED_HW_CFG_POWER_DIS_CMN_SHIFT 24 293 294 u32 ump_nc_si_config; /* 0x120 */ 295 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MASK 0x00000003 296 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_SHIFT 0 297 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MAC 0x00000000 298 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_PHY 0x00000001 299 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MII 0x00000000 300 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_RMII 0x00000002 301 302 #define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_MASK 0x00000f00 303 #define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_SHIFT 8 304 305 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_MASK 0x00ff0000 306 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_SHIFT 16 307 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_NONE 0x00000000 308 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_BCM5221 0x00010000 309 310 u32 board; /* 0x124 */ 311 #define SHARED_HW_CFG_E3_I2C_MUX0_MASK 0x0000003F 312 #define SHARED_HW_CFG_E3_I2C_MUX0_SHIFT 0 313 #define SHARED_HW_CFG_E3_I2C_MUX1_MASK 0x00000FC0 314 #define SHARED_HW_CFG_E3_I2C_MUX1_SHIFT 6 315 /* Use the PIN_CFG_XXX defines on top */ 316 #define SHARED_HW_CFG_BOARD_REV_MASK 0x00ff0000 317 #define SHARED_HW_CFG_BOARD_REV_SHIFT 16 318 319 #define SHARED_HW_CFG_BOARD_MAJOR_VER_MASK 0x0f000000 320 #define SHARED_HW_CFG_BOARD_MAJOR_VER_SHIFT 24 321 322 #define SHARED_HW_CFG_BOARD_MINOR_VER_MASK 0xf0000000 323 #define SHARED_HW_CFG_BOARD_MINOR_VER_SHIFT 28 324 325 u32 wc_lane_config; /* 0x128 */ 326 #define SHARED_HW_CFG_LANE_SWAP_CFG_MASK 0x0000FFFF 327 #define SHARED_HW_CFG_LANE_SWAP_CFG_SHIFT 0 328 #define SHARED_HW_CFG_LANE_SWAP_CFG_32103210 0x00001b1b 329 #define SHARED_HW_CFG_LANE_SWAP_CFG_32100123 0x00001be4 330 #define SHARED_HW_CFG_LANE_SWAP_CFG_01233210 0x0000e41b 331 #define SHARED_HW_CFG_LANE_SWAP_CFG_01230123 0x0000e4e4 332 #define SHARED_HW_CFG_LANE_SWAP_CFG_TX_MASK 0x000000FF 333 #define SHARED_HW_CFG_LANE_SWAP_CFG_TX_SHIFT 0 334 #define SHARED_HW_CFG_LANE_SWAP_CFG_RX_MASK 0x0000FF00 335 #define SHARED_HW_CFG_LANE_SWAP_CFG_RX_SHIFT 8 336 337 /* TX lane Polarity swap */ 338 #define SHARED_HW_CFG_TX_LANE0_POL_FLIP_ENABLED 0x00010000 339 #define SHARED_HW_CFG_TX_LANE1_POL_FLIP_ENABLED 0x00020000 340 #define SHARED_HW_CFG_TX_LANE2_POL_FLIP_ENABLED 0x00040000 341 #define SHARED_HW_CFG_TX_LANE3_POL_FLIP_ENABLED 0x00080000 342 /* TX lane Polarity swap */ 343 #define SHARED_HW_CFG_RX_LANE0_POL_FLIP_ENABLED 0x00100000 344 #define SHARED_HW_CFG_RX_LANE1_POL_FLIP_ENABLED 0x00200000 345 #define SHARED_HW_CFG_RX_LANE2_POL_FLIP_ENABLED 0x00400000 346 #define SHARED_HW_CFG_RX_LANE3_POL_FLIP_ENABLED 0x00800000 347 348 /* Selects the port layout of the board */ 349 #define SHARED_HW_CFG_E3_PORT_LAYOUT_MASK 0x0F000000 350 #define SHARED_HW_CFG_E3_PORT_LAYOUT_SHIFT 24 351 #define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_01 0x00000000 352 #define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_10 0x01000000 353 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_0123 0x02000000 354 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_1032 0x03000000 355 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_2301 0x04000000 356 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_3210 0x05000000 357 }; 358 359 360 /**************************************************************************** 361 * Port HW configuration * 362 ****************************************************************************/ 363 struct port_hw_cfg { /* port 0: 0x12c port 1: 0x2bc */ 364 365 u32 pci_id; 366 #define PORT_HW_CFG_PCI_VENDOR_ID_MASK 0xffff0000 367 #define PORT_HW_CFG_PCI_DEVICE_ID_MASK 0x0000ffff 368 369 u32 pci_sub_id; 370 #define PORT_HW_CFG_PCI_SUBSYS_DEVICE_ID_MASK 0xffff0000 371 #define PORT_HW_CFG_PCI_SUBSYS_VENDOR_ID_MASK 0x0000ffff 372 373 u32 power_dissipated; 374 #define PORT_HW_CFG_POWER_DIS_D0_MASK 0x000000ff 375 #define PORT_HW_CFG_POWER_DIS_D0_SHIFT 0 376 #define PORT_HW_CFG_POWER_DIS_D1_MASK 0x0000ff00 377 #define PORT_HW_CFG_POWER_DIS_D1_SHIFT 8 378 #define PORT_HW_CFG_POWER_DIS_D2_MASK 0x00ff0000 379 #define PORT_HW_CFG_POWER_DIS_D2_SHIFT 16 380 #define PORT_HW_CFG_POWER_DIS_D3_MASK 0xff000000 381 #define PORT_HW_CFG_POWER_DIS_D3_SHIFT 24 382 383 u32 power_consumed; 384 #define PORT_HW_CFG_POWER_CONS_D0_MASK 0x000000ff 385 #define PORT_HW_CFG_POWER_CONS_D0_SHIFT 0 386 #define PORT_HW_CFG_POWER_CONS_D1_MASK 0x0000ff00 387 #define PORT_HW_CFG_POWER_CONS_D1_SHIFT 8 388 #define PORT_HW_CFG_POWER_CONS_D2_MASK 0x00ff0000 389 #define PORT_HW_CFG_POWER_CONS_D2_SHIFT 16 390 #define PORT_HW_CFG_POWER_CONS_D3_MASK 0xff000000 391 #define PORT_HW_CFG_POWER_CONS_D3_SHIFT 24 392 393 u32 mac_upper; 394 #define PORT_HW_CFG_UPPERMAC_MASK 0x0000ffff 395 #define PORT_HW_CFG_UPPERMAC_SHIFT 0 396 u32 mac_lower; 397 398 u32 iscsi_mac_upper; /* Upper 16 bits are always zeroes */ 399 u32 iscsi_mac_lower; 400 401 u32 rdma_mac_upper; /* Upper 16 bits are always zeroes */ 402 u32 rdma_mac_lower; 403 404 u32 serdes_config; 405 #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_MASK 0x0000ffff 406 #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_SHIFT 0 407 408 #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK 0xffff0000 409 #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT 16 410 411 412 /* Default values: 2P-64, 4P-32 */ 413 u32 pf_config; /* 0x158 */ 414 #define PORT_HW_CFG_PF_NUM_VF_MASK 0x0000007F 415 #define PORT_HW_CFG_PF_NUM_VF_SHIFT 0 416 417 /* Default values: 17 */ 418 #define PORT_HW_CFG_PF_NUM_MSIX_VECTORS_MASK 0x00007F00 419 #define PORT_HW_CFG_PF_NUM_MSIX_VECTORS_SHIFT 8 420 421 #define PORT_HW_CFG_ENABLE_FLR_MASK 0x00010000 422 #define PORT_HW_CFG_FLR_ENABLED 0x00010000 423 424 u32 vf_config; /* 0x15C */ 425 #define PORT_HW_CFG_VF_NUM_MSIX_VECTORS_MASK 0x0000007F 426 #define PORT_HW_CFG_VF_NUM_MSIX_VECTORS_SHIFT 0 427 428 #define PORT_HW_CFG_VF_PCI_DEVICE_ID_MASK 0xFFFF0000 429 #define PORT_HW_CFG_VF_PCI_DEVICE_ID_SHIFT 16 430 431 u32 mf_pci_id; /* 0x160 */ 432 #define PORT_HW_CFG_MF_PCI_DEVICE_ID_MASK 0x0000FFFF 433 #define PORT_HW_CFG_MF_PCI_DEVICE_ID_SHIFT 0 434 435 /* Controls the TX laser of the SFP+ module */ 436 u32 sfp_ctrl; /* 0x164 */ 437 #define PORT_HW_CFG_TX_LASER_MASK 0x000000FF 438 #define PORT_HW_CFG_TX_LASER_SHIFT 0 439 #define PORT_HW_CFG_TX_LASER_MDIO 0x00000000 440 #define PORT_HW_CFG_TX_LASER_GPIO0 0x00000001 441 #define PORT_HW_CFG_TX_LASER_GPIO1 0x00000002 442 #define PORT_HW_CFG_TX_LASER_GPIO2 0x00000003 443 #define PORT_HW_CFG_TX_LASER_GPIO3 0x00000004 444 445 /* Controls the fault module LED of the SFP+ */ 446 #define PORT_HW_CFG_FAULT_MODULE_LED_MASK 0x0000FF00 447 #define PORT_HW_CFG_FAULT_MODULE_LED_SHIFT 8 448 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO0 0x00000000 449 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO1 0x00000100 450 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO2 0x00000200 451 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO3 0x00000300 452 #define PORT_HW_CFG_FAULT_MODULE_LED_DISABLED 0x00000400 453 454 /* The output pin TX_DIS that controls the TX laser of the SFP+ 455 module. Use the PIN_CFG_XXX defines on top */ 456 u32 e3_sfp_ctrl; /* 0x168 */ 457 #define PORT_HW_CFG_E3_TX_LASER_MASK 0x000000FF 458 #define PORT_HW_CFG_E3_TX_LASER_SHIFT 0 459 460 /* The output pin for SFPP_TYPE which turns on the Fault module LED */ 461 #define PORT_HW_CFG_E3_FAULT_MDL_LED_MASK 0x0000FF00 462 #define PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT 8 463 464 /* The input pin MOD_ABS that indicates whether SFP+ module is 465 present or not. Use the PIN_CFG_XXX defines on top */ 466 #define PORT_HW_CFG_E3_MOD_ABS_MASK 0x00FF0000 467 #define PORT_HW_CFG_E3_MOD_ABS_SHIFT 16 468 469 /* The output pin PWRDIS_SFP_X which disable the power of the SFP+ 470 module. Use the PIN_CFG_XXX defines on top */ 471 #define PORT_HW_CFG_E3_PWR_DIS_MASK 0xFF000000 472 #define PORT_HW_CFG_E3_PWR_DIS_SHIFT 24 473 474 /* 475 * The input pin which signals module transmit fault. Use the 476 * PIN_CFG_XXX defines on top 477 */ 478 u32 e3_cmn_pin_cfg; /* 0x16C */ 479 #define PORT_HW_CFG_E3_TX_FAULT_MASK 0x000000FF 480 #define PORT_HW_CFG_E3_TX_FAULT_SHIFT 0 481 482 /* The output pin which reset the PHY. Use the PIN_CFG_XXX defines on 483 top */ 484 #define PORT_HW_CFG_E3_PHY_RESET_MASK 0x0000FF00 485 #define PORT_HW_CFG_E3_PHY_RESET_SHIFT 8 486 487 /* 488 * The output pin which powers down the PHY. Use the PIN_CFG_XXX 489 * defines on top 490 */ 491 #define PORT_HW_CFG_E3_PWR_DOWN_MASK 0x00FF0000 492 #define PORT_HW_CFG_E3_PWR_DOWN_SHIFT 16 493 494 /* The output pin values BSC_SEL which selects the I2C for this port 495 in the I2C Mux */ 496 #define PORT_HW_CFG_E3_I2C_MUX0_MASK 0x01000000 497 #define PORT_HW_CFG_E3_I2C_MUX1_MASK 0x02000000 498 499 500 /* 501 * The input pin I_FAULT which indicate over-current has occurred. 502 * Use the PIN_CFG_XXX defines on top 503 */ 504 u32 e3_cmn_pin_cfg1; /* 0x170 */ 505 #define PORT_HW_CFG_E3_OVER_CURRENT_MASK 0x000000FF 506 #define PORT_HW_CFG_E3_OVER_CURRENT_SHIFT 0 507 508 /* pause on host ring */ 509 u32 generic_features; /* 0x174 */ 510 #define PORT_HW_CFG_PAUSE_ON_HOST_RING_MASK 0x00000001 511 #define PORT_HW_CFG_PAUSE_ON_HOST_RING_SHIFT 0 512 #define PORT_HW_CFG_PAUSE_ON_HOST_RING_DISABLED 0x00000000 513 #define PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED 0x00000001 514 515 /* SFP+ Tx Equalization: NIC recommended and tested value is 0xBEB2 516 * LOM recommended and tested value is 0xBEB2. Using a different 517 * value means using a value not tested by BRCM 518 */ 519 u32 sfi_tap_values; /* 0x178 */ 520 #define PORT_HW_CFG_TX_EQUALIZATION_MASK 0x0000FFFF 521 #define PORT_HW_CFG_TX_EQUALIZATION_SHIFT 0 522 523 /* SFP+ Tx driver broadcast IDRIVER: NIC recommended and tested 524 * value is 0x2. LOM recommended and tested value is 0x2. Using a 525 * different value means using a value not tested by BRCM 526 */ 527 #define PORT_HW_CFG_TX_DRV_BROADCAST_MASK 0x000F0000 528 #define PORT_HW_CFG_TX_DRV_BROADCAST_SHIFT 16 529 530 u32 reserved0[5]; /* 0x17c */ 531 532 u32 aeu_int_mask; /* 0x190 */ 533 534 u32 media_type; /* 0x194 */ 535 #define PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK 0x000000FF 536 #define PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT 0 537 538 #define PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK 0x0000FF00 539 #define PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT 8 540 541 #define PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK 0x00FF0000 542 #define PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT 16 543 544 /* 4 times 16 bits for all 4 lanes. In case external PHY is present 545 (not direct mode), those values will not take effect on the 4 XGXS 546 lanes. For some external PHYs (such as 8706 and 8726) the values 547 will be used to configure the external PHY in those cases, not 548 all 4 values are needed. */ 549 u16 xgxs_config_rx[4]; /* 0x198 */ 550 u16 xgxs_config_tx[4]; /* 0x1A0 */ 551 552 /* For storing FCOE mac on shared memory */ 553 u32 fcoe_fip_mac_upper; 554 #define PORT_HW_CFG_FCOE_UPPERMAC_MASK 0x0000ffff 555 #define PORT_HW_CFG_FCOE_UPPERMAC_SHIFT 0 556 u32 fcoe_fip_mac_lower; 557 558 u32 fcoe_wwn_port_name_upper; 559 u32 fcoe_wwn_port_name_lower; 560 561 u32 fcoe_wwn_node_name_upper; 562 u32 fcoe_wwn_node_name_lower; 563 564 u32 Reserved1[49]; /* 0x1C0 */ 565 566 /* Enable RJ45 magjack pair swapping on 10GBase-T PHY (0=default), 567 84833 only */ 568 u32 xgbt_phy_cfg; /* 0x284 */ 569 #define PORT_HW_CFG_RJ45_PAIR_SWAP_MASK 0x000000FF 570 #define PORT_HW_CFG_RJ45_PAIR_SWAP_SHIFT 0 571 572 u32 default_cfg; /* 0x288 */ 573 #define PORT_HW_CFG_GPIO0_CONFIG_MASK 0x00000003 574 #define PORT_HW_CFG_GPIO0_CONFIG_SHIFT 0 575 #define PORT_HW_CFG_GPIO0_CONFIG_NA 0x00000000 576 #define PORT_HW_CFG_GPIO0_CONFIG_LOW 0x00000001 577 #define PORT_HW_CFG_GPIO0_CONFIG_HIGH 0x00000002 578 #define PORT_HW_CFG_GPIO0_CONFIG_INPUT 0x00000003 579 580 #define PORT_HW_CFG_GPIO1_CONFIG_MASK 0x0000000C 581 #define PORT_HW_CFG_GPIO1_CONFIG_SHIFT 2 582 #define PORT_HW_CFG_GPIO1_CONFIG_NA 0x00000000 583 #define PORT_HW_CFG_GPIO1_CONFIG_LOW 0x00000004 584 #define PORT_HW_CFG_GPIO1_CONFIG_HIGH 0x00000008 585 #define PORT_HW_CFG_GPIO1_CONFIG_INPUT 0x0000000c 586 587 #define PORT_HW_CFG_GPIO2_CONFIG_MASK 0x00000030 588 #define PORT_HW_CFG_GPIO2_CONFIG_SHIFT 4 589 #define PORT_HW_CFG_GPIO2_CONFIG_NA 0x00000000 590 #define PORT_HW_CFG_GPIO2_CONFIG_LOW 0x00000010 591 #define PORT_HW_CFG_GPIO2_CONFIG_HIGH 0x00000020 592 #define PORT_HW_CFG_GPIO2_CONFIG_INPUT 0x00000030 593 594 #define PORT_HW_CFG_GPIO3_CONFIG_MASK 0x000000C0 595 #define PORT_HW_CFG_GPIO3_CONFIG_SHIFT 6 596 #define PORT_HW_CFG_GPIO3_CONFIG_NA 0x00000000 597 #define PORT_HW_CFG_GPIO3_CONFIG_LOW 0x00000040 598 #define PORT_HW_CFG_GPIO3_CONFIG_HIGH 0x00000080 599 #define PORT_HW_CFG_GPIO3_CONFIG_INPUT 0x000000c0 600 601 /* When KR link is required to be set to force which is not 602 KR-compliant, this parameter determine what is the trigger for it. 603 When GPIO is selected, low input will force the speed. Currently 604 default speed is 1G. In the future, it may be widen to select the 605 forced speed in with another parameter. Note when force-1G is 606 enabled, it override option 56: Link Speed option. */ 607 #define PORT_HW_CFG_FORCE_KR_ENABLER_MASK 0x00000F00 608 #define PORT_HW_CFG_FORCE_KR_ENABLER_SHIFT 8 609 #define PORT_HW_CFG_FORCE_KR_ENABLER_NOT_FORCED 0x00000000 610 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P0 0x00000100 611 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P0 0x00000200 612 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P0 0x00000300 613 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P0 0x00000400 614 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P1 0x00000500 615 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P1 0x00000600 616 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P1 0x00000700 617 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P1 0x00000800 618 #define PORT_HW_CFG_FORCE_KR_ENABLER_FORCED 0x00000900 619 /* Enable to determine with which GPIO to reset the external phy */ 620 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK 0x000F0000 621 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT 16 622 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_PHY_TYPE 0x00000000 623 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0 0x00010000 624 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0 0x00020000 625 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0 0x00030000 626 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0 0x00040000 627 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1 0x00050000 628 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1 0x00060000 629 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1 0x00070000 630 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1 0x00080000 631 632 /* Enable BAM on KR */ 633 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_MASK 0x00100000 634 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_SHIFT 20 635 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_DISABLED 0x00000000 636 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED 0x00100000 637 638 /* Enable Common Mode Sense */ 639 #define PORT_HW_CFG_ENABLE_CMS_MASK 0x00200000 640 #define PORT_HW_CFG_ENABLE_CMS_SHIFT 21 641 #define PORT_HW_CFG_ENABLE_CMS_DISABLED 0x00000000 642 #define PORT_HW_CFG_ENABLE_CMS_ENABLED 0x00200000 643 644 /* Determine the Serdes electrical interface */ 645 #define PORT_HW_CFG_NET_SERDES_IF_MASK 0x0F000000 646 #define PORT_HW_CFG_NET_SERDES_IF_SHIFT 24 647 #define PORT_HW_CFG_NET_SERDES_IF_SGMII 0x00000000 648 #define PORT_HW_CFG_NET_SERDES_IF_XFI 0x01000000 649 #define PORT_HW_CFG_NET_SERDES_IF_SFI 0x02000000 650 #define PORT_HW_CFG_NET_SERDES_IF_KR 0x03000000 651 #define PORT_HW_CFG_NET_SERDES_IF_DXGXS 0x04000000 652 #define PORT_HW_CFG_NET_SERDES_IF_KR2 0x05000000 653 654 655 u32 speed_capability_mask2; /* 0x28C */ 656 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_MASK 0x0000FFFF 657 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_SHIFT 0 658 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10M_FULL 0x00000001 659 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3__ 0x00000002 660 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3___ 0x00000004 661 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_100M_FULL 0x00000008 662 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_1G 0x00000010 663 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_2_DOT_5G 0x00000020 664 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10G 0x00000040 665 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_20G 0x00000080 666 667 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_MASK 0xFFFF0000 668 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_SHIFT 16 669 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10M_FULL 0x00010000 670 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0__ 0x00020000 671 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0___ 0x00040000 672 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_100M_FULL 0x00080000 673 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_1G 0x00100000 674 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_2_DOT_5G 0x00200000 675 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10G 0x00400000 676 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_20G 0x00800000 677 678 679 /* In the case where two media types (e.g. copper and fiber) are 680 present and electrically active at the same time, PHY Selection 681 will determine which of the two PHYs will be designated as the 682 Active PHY and used for a connection to the network. */ 683 u32 multi_phy_config; /* 0x290 */ 684 #define PORT_HW_CFG_PHY_SELECTION_MASK 0x00000007 685 #define PORT_HW_CFG_PHY_SELECTION_SHIFT 0 686 #define PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT 0x00000000 687 #define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY 0x00000001 688 #define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY 0x00000002 689 #define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY 0x00000003 690 #define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY 0x00000004 691 692 /* When enabled, all second phy nvram parameters will be swapped 693 with the first phy parameters */ 694 #define PORT_HW_CFG_PHY_SWAPPED_MASK 0x00000008 695 #define PORT_HW_CFG_PHY_SWAPPED_SHIFT 3 696 #define PORT_HW_CFG_PHY_SWAPPED_DISABLED 0x00000000 697 #define PORT_HW_CFG_PHY_SWAPPED_ENABLED 0x00000008 698 699 700 /* Address of the second external phy */ 701 u32 external_phy_config2; /* 0x294 */ 702 #define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_MASK 0x000000FF 703 #define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_SHIFT 0 704 705 /* The second XGXS external PHY type */ 706 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_MASK 0x0000FF00 707 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SHIFT 8 708 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_DIRECT 0x00000000 709 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8071 0x00000100 710 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8072 0x00000200 711 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8073 0x00000300 712 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8705 0x00000400 713 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8706 0x00000500 714 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8726 0x00000600 715 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8481 0x00000700 716 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SFX7101 0x00000800 717 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727 0x00000900 718 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727_NOC 0x00000a00 719 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84823 0x00000b00 720 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54640 0x00000c00 721 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84833 0x00000d00 722 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54618SE 0x00000e00 723 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8722 0x00000f00 724 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54616 0x00001000 725 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84834 0x00001100 726 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_FAILURE 0x0000fd00 727 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_NOT_CONN 0x0000ff00 728 729 730 /* 4 times 16 bits for all 4 lanes. For some external PHYs (such as 731 8706, 8726 and 8727) not all 4 values are needed. */ 732 u16 xgxs_config2_rx[4]; /* 0x296 */ 733 u16 xgxs_config2_tx[4]; /* 0x2A0 */ 734 735 u32 lane_config; 736 #define PORT_HW_CFG_LANE_SWAP_CFG_MASK 0x0000ffff 737 #define PORT_HW_CFG_LANE_SWAP_CFG_SHIFT 0 738 /* AN and forced */ 739 #define PORT_HW_CFG_LANE_SWAP_CFG_01230123 0x00001b1b 740 /* forced only */ 741 #define PORT_HW_CFG_LANE_SWAP_CFG_01233210 0x00001be4 742 /* forced only */ 743 #define PORT_HW_CFG_LANE_SWAP_CFG_31203120 0x0000d8d8 744 /* forced only */ 745 #define PORT_HW_CFG_LANE_SWAP_CFG_32103210 0x0000e4e4 746 #define PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK 0x000000ff 747 #define PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT 0 748 #define PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK 0x0000ff00 749 #define PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT 8 750 #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK 0x0000c000 751 #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT 14 752 753 /* Indicate whether to swap the external phy polarity */ 754 #define PORT_HW_CFG_SWAP_PHY_POLARITY_MASK 0x00010000 755 #define PORT_HW_CFG_SWAP_PHY_POLARITY_DISABLED 0x00000000 756 #define PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED 0x00010000 757 758 759 u32 external_phy_config; 760 #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK 0x000000ff 761 #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT 0 762 763 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK 0x0000ff00 764 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SHIFT 8 765 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT 0x00000000 766 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8071 0x00000100 767 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072 0x00000200 768 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073 0x00000300 769 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705 0x00000400 770 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706 0x00000500 771 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726 0x00000600 772 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481 0x00000700 773 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101 0x00000800 774 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727 0x00000900 775 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC 0x00000a00 776 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823 0x00000b00 777 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54640 0x00000c00 778 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833 0x00000d00 779 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE 0x00000e00 780 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722 0x00000f00 781 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616 0x00001000 782 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834 0x00001100 783 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT_WC 0x0000fc00 784 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE 0x0000fd00 785 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN 0x0000ff00 786 787 #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK 0x00ff0000 788 #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_SHIFT 16 789 790 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK 0xff000000 791 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_SHIFT 24 792 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT 0x00000000 793 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482 0x01000000 794 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD 0x02000000 795 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN 0xff000000 796 797 u32 speed_capability_mask; 798 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_MASK 0x0000ffff 799 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_SHIFT 0 800 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_FULL 0x00000001 801 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_HALF 0x00000002 802 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_HALF 0x00000004 803 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_FULL 0x00000008 804 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_1G 0x00000010 805 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_2_5G 0x00000020 806 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10G 0x00000040 807 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_20G 0x00000080 808 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_RESERVED 0x0000f000 809 810 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK 0xffff0000 811 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_SHIFT 16 812 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL 0x00010000 813 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF 0x00020000 814 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF 0x00040000 815 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL 0x00080000 816 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_1G 0x00100000 817 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G 0x00200000 818 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10G 0x00400000 819 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_20G 0x00800000 820 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_RESERVED 0xf0000000 821 822 /* A place to hold the original MAC address as a backup */ 823 u32 backup_mac_upper; /* 0x2B4 */ 824 u32 backup_mac_lower; /* 0x2B8 */ 825 826 }; 827 828 829 /**************************************************************************** 830 * Shared Feature configuration * 831 ****************************************************************************/ 832 struct shared_feat_cfg { /* NVRAM Offset */ 833 834 u32 config; /* 0x450 */ 835 #define SHARED_FEATURE_BMC_ECHO_MODE_EN 0x00000001 836 837 /* Use NVRAM values instead of HW default values */ 838 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_MASK \ 839 0x00000002 840 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_DISABLED \ 841 0x00000000 842 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED \ 843 0x00000002 844 845 #define SHARED_FEAT_CFG_NCSI_ID_METHOD_MASK 0x00000008 846 #define SHARED_FEAT_CFG_NCSI_ID_METHOD_SPIO 0x00000000 847 #define SHARED_FEAT_CFG_NCSI_ID_METHOD_NVRAM 0x00000008 848 849 #define SHARED_FEAT_CFG_NCSI_ID_MASK 0x00000030 850 #define SHARED_FEAT_CFG_NCSI_ID_SHIFT 4 851 852 /* Override the OTP back to single function mode. When using GPIO, 853 high means only SF, 0 is according to CLP configuration */ 854 #define SHARED_FEAT_CFG_FORCE_SF_MODE_MASK 0x00000700 855 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SHIFT 8 856 #define SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED 0x00000000 857 #define SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF 0x00000100 858 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4 0x00000200 859 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT 0x00000300 860 #define SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE 0x00000400 861 862 /* The interval in seconds between sending LLDP packets. Set to zero 863 to disable the feature */ 864 #define SHARED_FEAT_CFG_LLDP_XMIT_INTERVAL_MASK 0x00ff0000 865 #define SHARED_FEAT_CFG_LLDP_XMIT_INTERVAL_SHIFT 16 866 867 /* The assigned device type ID for LLDP usage */ 868 #define SHARED_FEAT_CFG_LLDP_DEVICE_TYPE_ID_MASK 0xff000000 869 #define SHARED_FEAT_CFG_LLDP_DEVICE_TYPE_ID_SHIFT 24 870 871 }; 872 873 874 /**************************************************************************** 875 * Port Feature configuration * 876 ****************************************************************************/ 877 struct port_feat_cfg { /* port 0: 0x454 port 1: 0x4c8 */ 878 879 u32 config; 880 #define PORT_FEATURE_BAR1_SIZE_MASK 0x0000000f 881 #define PORT_FEATURE_BAR1_SIZE_SHIFT 0 882 #define PORT_FEATURE_BAR1_SIZE_DISABLED 0x00000000 883 #define PORT_FEATURE_BAR1_SIZE_64K 0x00000001 884 #define PORT_FEATURE_BAR1_SIZE_128K 0x00000002 885 #define PORT_FEATURE_BAR1_SIZE_256K 0x00000003 886 #define PORT_FEATURE_BAR1_SIZE_512K 0x00000004 887 #define PORT_FEATURE_BAR1_SIZE_1M 0x00000005 888 #define PORT_FEATURE_BAR1_SIZE_2M 0x00000006 889 #define PORT_FEATURE_BAR1_SIZE_4M 0x00000007 890 #define PORT_FEATURE_BAR1_SIZE_8M 0x00000008 891 #define PORT_FEATURE_BAR1_SIZE_16M 0x00000009 892 #define PORT_FEATURE_BAR1_SIZE_32M 0x0000000a 893 #define PORT_FEATURE_BAR1_SIZE_64M 0x0000000b 894 #define PORT_FEATURE_BAR1_SIZE_128M 0x0000000c 895 #define PORT_FEATURE_BAR1_SIZE_256M 0x0000000d 896 #define PORT_FEATURE_BAR1_SIZE_512M 0x0000000e 897 #define PORT_FEATURE_BAR1_SIZE_1G 0x0000000f 898 #define PORT_FEATURE_BAR2_SIZE_MASK 0x000000f0 899 #define PORT_FEATURE_BAR2_SIZE_SHIFT 4 900 #define PORT_FEATURE_BAR2_SIZE_DISABLED 0x00000000 901 #define PORT_FEATURE_BAR2_SIZE_64K 0x00000010 902 #define PORT_FEATURE_BAR2_SIZE_128K 0x00000020 903 #define PORT_FEATURE_BAR2_SIZE_256K 0x00000030 904 #define PORT_FEATURE_BAR2_SIZE_512K 0x00000040 905 #define PORT_FEATURE_BAR2_SIZE_1M 0x00000050 906 #define PORT_FEATURE_BAR2_SIZE_2M 0x00000060 907 #define PORT_FEATURE_BAR2_SIZE_4M 0x00000070 908 #define PORT_FEATURE_BAR2_SIZE_8M 0x00000080 909 #define PORT_FEATURE_BAR2_SIZE_16M 0x00000090 910 #define PORT_FEATURE_BAR2_SIZE_32M 0x000000a0 911 #define PORT_FEATURE_BAR2_SIZE_64M 0x000000b0 912 #define PORT_FEATURE_BAR2_SIZE_128M 0x000000c0 913 #define PORT_FEATURE_BAR2_SIZE_256M 0x000000d0 914 #define PORT_FEATURE_BAR2_SIZE_512M 0x000000e0 915 #define PORT_FEATURE_BAR2_SIZE_1G 0x000000f0 916 917 #define PORT_FEAT_CFG_DCBX_MASK 0x00000100 918 #define PORT_FEAT_CFG_DCBX_DISABLED 0x00000000 919 #define PORT_FEAT_CFG_DCBX_ENABLED 0x00000100 920 921 #define PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK 0x00000C00 922 #define PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE 0x00000400 923 #define PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI 0x00000800 924 925 #define PORT_FEATURE_EN_SIZE_MASK 0x0f000000 926 #define PORT_FEATURE_EN_SIZE_SHIFT 24 927 #define PORT_FEATURE_WOL_ENABLED 0x01000000 928 #define PORT_FEATURE_MBA_ENABLED 0x02000000 929 #define PORT_FEATURE_MFW_ENABLED 0x04000000 930 931 /* Advertise expansion ROM even if MBA is disabled */ 932 #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_MASK 0x08000000 933 #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_DISABLED 0x00000000 934 #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_ENABLED 0x08000000 935 936 /* Check the optic vendor via i2c against a list of approved modules 937 in a separate nvram image */ 938 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK 0xe0000000 939 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_SHIFT 29 940 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT \ 941 0x00000000 942 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER \ 943 0x20000000 944 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG 0x40000000 945 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN 0x60000000 946 947 u32 wol_config; 948 /* Default is used when driver sets to "auto" mode */ 949 #define PORT_FEATURE_WOL_DEFAULT_MASK 0x00000003 950 #define PORT_FEATURE_WOL_DEFAULT_SHIFT 0 951 #define PORT_FEATURE_WOL_DEFAULT_DISABLE 0x00000000 952 #define PORT_FEATURE_WOL_DEFAULT_MAGIC 0x00000001 953 #define PORT_FEATURE_WOL_DEFAULT_ACPI 0x00000002 954 #define PORT_FEATURE_WOL_DEFAULT_MAGIC_AND_ACPI 0x00000003 955 #define PORT_FEATURE_WOL_RES_PAUSE_CAP 0x00000004 956 #define PORT_FEATURE_WOL_RES_ASYM_PAUSE_CAP 0x00000008 957 #define PORT_FEATURE_WOL_ACPI_UPON_MGMT 0x00000010 958 959 u32 mba_config; 960 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK 0x00000007 961 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT 0 962 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE 0x00000000 963 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL 0x00000001 964 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP 0x00000002 965 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB 0x00000003 966 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT 0x00000004 967 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE 0x00000007 968 969 #define PORT_FEATURE_MBA_BOOT_RETRY_MASK 0x00000038 970 #define PORT_FEATURE_MBA_BOOT_RETRY_SHIFT 3 971 972 #define PORT_FEATURE_MBA_RES_PAUSE_CAP 0x00000100 973 #define PORT_FEATURE_MBA_RES_ASYM_PAUSE_CAP 0x00000200 974 #define PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE 0x00000400 975 #define PORT_FEATURE_MBA_HOTKEY_MASK 0x00000800 976 #define PORT_FEATURE_MBA_HOTKEY_CTRL_S 0x00000000 977 #define PORT_FEATURE_MBA_HOTKEY_CTRL_B 0x00000800 978 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK 0x000ff000 979 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT 12 980 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED 0x00000000 981 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2K 0x00001000 982 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4K 0x00002000 983 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8K 0x00003000 984 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16K 0x00004000 985 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32K 0x00005000 986 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_64K 0x00006000 987 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_128K 0x00007000 988 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_256K 0x00008000 989 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_512K 0x00009000 990 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_1M 0x0000a000 991 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2M 0x0000b000 992 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4M 0x0000c000 993 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8M 0x0000d000 994 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16M 0x0000e000 995 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32M 0x0000f000 996 #define PORT_FEATURE_MBA_MSG_TIMEOUT_MASK 0x00f00000 997 #define PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT 20 998 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK 0x03000000 999 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT 24 1000 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO 0x00000000 1001 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS 0x01000000 1002 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H 0x02000000 1003 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H 0x03000000 1004 #define PORT_FEATURE_MBA_LINK_SPEED_MASK 0x3c000000 1005 #define PORT_FEATURE_MBA_LINK_SPEED_SHIFT 26 1006 #define PORT_FEATURE_MBA_LINK_SPEED_AUTO 0x00000000 1007 #define PORT_FEATURE_MBA_LINK_SPEED_10HD 0x04000000 1008 #define PORT_FEATURE_MBA_LINK_SPEED_10FD 0x08000000 1009 #define PORT_FEATURE_MBA_LINK_SPEED_100HD 0x0c000000 1010 #define PORT_FEATURE_MBA_LINK_SPEED_100FD 0x10000000 1011 #define PORT_FEATURE_MBA_LINK_SPEED_1GBPS 0x14000000 1012 #define PORT_FEATURE_MBA_LINK_SPEED_2_5GBPS 0x18000000 1013 #define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_CX4 0x1c000000 1014 #define PORT_FEATURE_MBA_LINK_SPEED_20GBPS 0x20000000 1015 u32 bmc_config; 1016 #define PORT_FEATURE_BMC_LINK_OVERRIDE_MASK 0x00000001 1017 #define PORT_FEATURE_BMC_LINK_OVERRIDE_DEFAULT 0x00000000 1018 #define PORT_FEATURE_BMC_LINK_OVERRIDE_EN 0x00000001 1019 1020 u32 mba_vlan_cfg; 1021 #define PORT_FEATURE_MBA_VLAN_TAG_MASK 0x0000ffff 1022 #define PORT_FEATURE_MBA_VLAN_TAG_SHIFT 0 1023 #define PORT_FEATURE_MBA_VLAN_EN 0x00010000 1024 1025 u32 resource_cfg; 1026 #define PORT_FEATURE_RESOURCE_CFG_VALID 0x00000001 1027 #define PORT_FEATURE_RESOURCE_CFG_DIAG 0x00000002 1028 #define PORT_FEATURE_RESOURCE_CFG_L2 0x00000004 1029 #define PORT_FEATURE_RESOURCE_CFG_ISCSI 0x00000008 1030 #define PORT_FEATURE_RESOURCE_CFG_RDMA 0x00000010 1031 1032 u32 smbus_config; 1033 #define PORT_FEATURE_SMBUS_ADDR_MASK 0x000000fe 1034 #define PORT_FEATURE_SMBUS_ADDR_SHIFT 1 1035 1036 u32 vf_config; 1037 #define PORT_FEAT_CFG_VF_BAR2_SIZE_MASK 0x0000000f 1038 #define PORT_FEAT_CFG_VF_BAR2_SIZE_SHIFT 0 1039 #define PORT_FEAT_CFG_VF_BAR2_SIZE_DISABLED 0x00000000 1040 #define PORT_FEAT_CFG_VF_BAR2_SIZE_4K 0x00000001 1041 #define PORT_FEAT_CFG_VF_BAR2_SIZE_8K 0x00000002 1042 #define PORT_FEAT_CFG_VF_BAR2_SIZE_16K 0x00000003 1043 #define PORT_FEAT_CFG_VF_BAR2_SIZE_32K 0x00000004 1044 #define PORT_FEAT_CFG_VF_BAR2_SIZE_64K 0x00000005 1045 #define PORT_FEAT_CFG_VF_BAR2_SIZE_128K 0x00000006 1046 #define PORT_FEAT_CFG_VF_BAR2_SIZE_256K 0x00000007 1047 #define PORT_FEAT_CFG_VF_BAR2_SIZE_512K 0x00000008 1048 #define PORT_FEAT_CFG_VF_BAR2_SIZE_1M 0x00000009 1049 #define PORT_FEAT_CFG_VF_BAR2_SIZE_2M 0x0000000a 1050 #define PORT_FEAT_CFG_VF_BAR2_SIZE_4M 0x0000000b 1051 #define PORT_FEAT_CFG_VF_BAR2_SIZE_8M 0x0000000c 1052 #define PORT_FEAT_CFG_VF_BAR2_SIZE_16M 0x0000000d 1053 #define PORT_FEAT_CFG_VF_BAR2_SIZE_32M 0x0000000e 1054 #define PORT_FEAT_CFG_VF_BAR2_SIZE_64M 0x0000000f 1055 1056 u32 link_config; /* Used as HW defaults for the driver */ 1057 #define PORT_FEATURE_CONNECTED_SWITCH_MASK 0x03000000 1058 #define PORT_FEATURE_CONNECTED_SWITCH_SHIFT 24 1059 /* (forced) low speed switch (< 10G) */ 1060 #define PORT_FEATURE_CON_SWITCH_1G_SWITCH 0x00000000 1061 /* (forced) high speed switch (>= 10G) */ 1062 #define PORT_FEATURE_CON_SWITCH_10G_SWITCH 0x01000000 1063 #define PORT_FEATURE_CON_SWITCH_AUTO_DETECT 0x02000000 1064 #define PORT_FEATURE_CON_SWITCH_ONE_TIME_DETECT 0x03000000 1065 1066 #define PORT_FEATURE_LINK_SPEED_MASK 0x000f0000 1067 #define PORT_FEATURE_LINK_SPEED_SHIFT 16 1068 #define PORT_FEATURE_LINK_SPEED_AUTO 0x00000000 1069 #define PORT_FEATURE_LINK_SPEED_10M_FULL 0x00010000 1070 #define PORT_FEATURE_LINK_SPEED_10M_HALF 0x00020000 1071 #define PORT_FEATURE_LINK_SPEED_100M_HALF 0x00030000 1072 #define PORT_FEATURE_LINK_SPEED_100M_FULL 0x00040000 1073 #define PORT_FEATURE_LINK_SPEED_1G 0x00050000 1074 #define PORT_FEATURE_LINK_SPEED_2_5G 0x00060000 1075 #define PORT_FEATURE_LINK_SPEED_10G_CX4 0x00070000 1076 #define PORT_FEATURE_LINK_SPEED_20G 0x00080000 1077 1078 #define PORT_FEATURE_FLOW_CONTROL_MASK 0x00000700 1079 #define PORT_FEATURE_FLOW_CONTROL_SHIFT 8 1080 #define PORT_FEATURE_FLOW_CONTROL_AUTO 0x00000000 1081 #define PORT_FEATURE_FLOW_CONTROL_TX 0x00000100 1082 #define PORT_FEATURE_FLOW_CONTROL_RX 0x00000200 1083 #define PORT_FEATURE_FLOW_CONTROL_BOTH 0x00000300 1084 #define PORT_FEATURE_FLOW_CONTROL_NONE 0x00000400 1085 1086 /* The default for MCP link configuration, 1087 uses the same defines as link_config */ 1088 u32 mfw_wol_link_cfg; 1089 1090 /* The default for the driver of the second external phy, 1091 uses the same defines as link_config */ 1092 u32 link_config2; /* 0x47C */ 1093 1094 /* The default for MCP of the second external phy, 1095 uses the same defines as link_config */ 1096 u32 mfw_wol_link_cfg2; /* 0x480 */ 1097 1098 1099 /* EEE power saving mode */ 1100 u32 eee_power_mode; /* 0x484 */ 1101 #define PORT_FEAT_CFG_EEE_POWER_MODE_MASK 0x000000FF 1102 #define PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT 0 1103 #define PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED 0x00000000 1104 #define PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED 0x00000001 1105 #define PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE 0x00000002 1106 #define PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY 0x00000003 1107 1108 1109 u32 Reserved2[16]; /* 0x488 */ 1110 }; 1111 1112 1113 /**************************************************************************** 1114 * Device Information * 1115 ****************************************************************************/ 1116 struct shm_dev_info { /* size */ 1117 1118 u32 bc_rev; /* 8 bits each: major, minor, build */ /* 4 */ 1119 1120 struct shared_hw_cfg shared_hw_config; /* 40 */ 1121 1122 struct port_hw_cfg port_hw_config[PORT_MAX]; /* 400*2=800 */ 1123 1124 struct shared_feat_cfg shared_feature_config; /* 4 */ 1125 1126 struct port_feat_cfg port_feature_config[PORT_MAX];/* 116*2=232 */ 1127 1128 }; 1129 1130 1131 #if !defined(__LITTLE_ENDIAN) && !defined(__BIG_ENDIAN) 1132 #error "Missing either LITTLE_ENDIAN or BIG_ENDIAN definition." 1133 #endif 1134 1135 #define FUNC_0 0 1136 #define FUNC_1 1 1137 #define FUNC_2 2 1138 #define FUNC_3 3 1139 #define FUNC_4 4 1140 #define FUNC_5 5 1141 #define FUNC_6 6 1142 #define FUNC_7 7 1143 #define E1_FUNC_MAX 2 1144 #define E1H_FUNC_MAX 8 1145 #define E2_FUNC_MAX 4 /* per path */ 1146 1147 #define VN_0 0 1148 #define VN_1 1 1149 #define VN_2 2 1150 #define VN_3 3 1151 #define E1VN_MAX 1 1152 #define E1HVN_MAX 4 1153 1154 #define E2_VF_MAX 64 /* HC_REG_VF_CONFIGURATION_SIZE */ 1155 /* This value (in milliseconds) determines the frequency of the driver 1156 * issuing the PULSE message code. The firmware monitors this periodic 1157 * pulse to determine when to switch to an OS-absent mode. */ 1158 #define DRV_PULSE_PERIOD_MS 250 1159 1160 /* This value (in milliseconds) determines how long the driver should 1161 * wait for an acknowledgement from the firmware before timing out. Once 1162 * the firmware has timed out, the driver will assume there is no firmware 1163 * running and there won't be any firmware-driver synchronization during a 1164 * driver reset. */ 1165 #define FW_ACK_TIME_OUT_MS 5000 1166 1167 #define FW_ACK_POLL_TIME_MS 1 1168 1169 #define FW_ACK_NUM_OF_POLL (FW_ACK_TIME_OUT_MS/FW_ACK_POLL_TIME_MS) 1170 1171 #define MFW_TRACE_SIGNATURE 0x54524342 1172 1173 /**************************************************************************** 1174 * Driver <-> FW Mailbox * 1175 ****************************************************************************/ 1176 struct drv_port_mb { 1177 1178 u32 link_status; 1179 /* Driver should update this field on any link change event */ 1180 1181 #define LINK_STATUS_NONE (0<<0) 1182 #define LINK_STATUS_LINK_FLAG_MASK 0x00000001 1183 #define LINK_STATUS_LINK_UP 0x00000001 1184 #define LINK_STATUS_SPEED_AND_DUPLEX_MASK 0x0000001E 1185 #define LINK_STATUS_SPEED_AND_DUPLEX_AN_NOT_COMPLETE (0<<1) 1186 #define LINK_STATUS_SPEED_AND_DUPLEX_10THD (1<<1) 1187 #define LINK_STATUS_SPEED_AND_DUPLEX_10TFD (2<<1) 1188 #define LINK_STATUS_SPEED_AND_DUPLEX_100TXHD (3<<1) 1189 #define LINK_STATUS_SPEED_AND_DUPLEX_100T4 (4<<1) 1190 #define LINK_STATUS_SPEED_AND_DUPLEX_100TXFD (5<<1) 1191 #define LINK_STATUS_SPEED_AND_DUPLEX_1000THD (6<<1) 1192 #define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD (7<<1) 1193 #define LINK_STATUS_SPEED_AND_DUPLEX_1000XFD (7<<1) 1194 #define LINK_STATUS_SPEED_AND_DUPLEX_2500THD (8<<1) 1195 #define LINK_STATUS_SPEED_AND_DUPLEX_2500TFD (9<<1) 1196 #define LINK_STATUS_SPEED_AND_DUPLEX_2500XFD (9<<1) 1197 #define LINK_STATUS_SPEED_AND_DUPLEX_10GTFD (10<<1) 1198 #define LINK_STATUS_SPEED_AND_DUPLEX_10GXFD (10<<1) 1199 #define LINK_STATUS_SPEED_AND_DUPLEX_20GTFD (11<<1) 1200 #define LINK_STATUS_SPEED_AND_DUPLEX_20GXFD (11<<1) 1201 1202 #define LINK_STATUS_AUTO_NEGOTIATE_FLAG_MASK 0x00000020 1203 #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED 0x00000020 1204 1205 #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE 0x00000040 1206 #define LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK 0x00000080 1207 #define LINK_STATUS_PARALLEL_DETECTION_USED 0x00000080 1208 1209 #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200 1210 #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400 1211 #define LINK_STATUS_LINK_PARTNER_100T4_CAPABLE 0x00000800 1212 #define LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE 0x00001000 1213 #define LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE 0x00002000 1214 #define LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE 0x00004000 1215 #define LINK_STATUS_LINK_PARTNER_10THD_CAPABLE 0x00008000 1216 1217 #define LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK 0x00010000 1218 #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED 0x00010000 1219 1220 #define LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK 0x00020000 1221 #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED 0x00020000 1222 1223 #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK 0x000C0000 1224 #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE (0<<18) 1225 #define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE (1<<18) 1226 #define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE (2<<18) 1227 #define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE (3<<18) 1228 1229 #define LINK_STATUS_SERDES_LINK 0x00100000 1230 1231 #define LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE 0x00200000 1232 #define LINK_STATUS_LINK_PARTNER_2500XHD_CAPABLE 0x00400000 1233 #define LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE 0x00800000 1234 #define LINK_STATUS_LINK_PARTNER_20GXFD_CAPABLE 0x10000000 1235 1236 #define LINK_STATUS_PFC_ENABLED 0x20000000 1237 1238 #define LINK_STATUS_PHYSICAL_LINK_FLAG 0x40000000 1239 #define LINK_STATUS_SFP_TX_FAULT 0x80000000 1240 1241 u32 port_stx; 1242 1243 u32 stat_nig_timer; 1244 1245 /* MCP firmware does not use this field */ 1246 u32 ext_phy_fw_version; 1247 1248 }; 1249 1250 1251 struct drv_func_mb { 1252 1253 u32 drv_mb_header; 1254 #define DRV_MSG_CODE_MASK 0xffff0000 1255 #define DRV_MSG_CODE_LOAD_REQ 0x10000000 1256 #define DRV_MSG_CODE_LOAD_DONE 0x11000000 1257 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_EN 0x20000000 1258 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS 0x20010000 1259 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP 0x20020000 1260 #define DRV_MSG_CODE_UNLOAD_DONE 0x21000000 1261 #define DRV_MSG_CODE_DCC_OK 0x30000000 1262 #define DRV_MSG_CODE_DCC_FAILURE 0x31000000 1263 #define DRV_MSG_CODE_DIAG_ENTER_REQ 0x50000000 1264 #define DRV_MSG_CODE_DIAG_EXIT_REQ 0x60000000 1265 #define DRV_MSG_CODE_VALIDATE_KEY 0x70000000 1266 #define DRV_MSG_CODE_GET_CURR_KEY 0x80000000 1267 #define DRV_MSG_CODE_GET_UPGRADE_KEY 0x81000000 1268 #define DRV_MSG_CODE_GET_MANUF_KEY 0x82000000 1269 #define DRV_MSG_CODE_LOAD_L2B_PRAM 0x90000000 1270 /* 1271 * The optic module verification command requires bootcode 1272 * v5.0.6 or later, te specific optic module verification command 1273 * requires bootcode v5.2.12 or later 1274 */ 1275 #define DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL 0xa0000000 1276 #define REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL 0x00050006 1277 #define DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL 0xa1000000 1278 #define REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL 0x00050234 1279 #define DRV_MSG_CODE_VRFY_AFEX_SUPPORTED 0xa2000000 1280 #define REQ_BC_VER_4_VRFY_AFEX_SUPPORTED 0x00070002 1281 #define REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED 0x00070014 1282 #define REQ_BC_VER_4_MT_SUPPORTED 0x00070201 1283 #define REQ_BC_VER_4_PFC_STATS_SUPPORTED 0x00070201 1284 #define REQ_BC_VER_4_FCOE_FEATURES 0x00070209 1285 1286 #define DRV_MSG_CODE_DCBX_ADMIN_PMF_MSG 0xb0000000 1287 #define DRV_MSG_CODE_DCBX_PMF_DRV_OK 0xb2000000 1288 #define REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF 0x00070401 1289 1290 #define DRV_MSG_CODE_VF_DISABLED_DONE 0xc0000000 1291 1292 #define DRV_MSG_CODE_AFEX_DRIVER_SETMAC 0xd0000000 1293 #define DRV_MSG_CODE_AFEX_LISTGET_ACK 0xd1000000 1294 #define DRV_MSG_CODE_AFEX_LISTSET_ACK 0xd2000000 1295 #define DRV_MSG_CODE_AFEX_STATSGET_ACK 0xd3000000 1296 #define DRV_MSG_CODE_AFEX_VIFSET_ACK 0xd4000000 1297 1298 #define DRV_MSG_CODE_DRV_INFO_ACK 0xd8000000 1299 #define DRV_MSG_CODE_DRV_INFO_NACK 0xd9000000 1300 1301 #define DRV_MSG_CODE_EEE_RESULTS_ACK 0xda000000 1302 1303 #define DRV_MSG_CODE_SET_MF_BW 0xe0000000 1304 #define REQ_BC_VER_4_SET_MF_BW 0x00060202 1305 #define DRV_MSG_CODE_SET_MF_BW_ACK 0xe1000000 1306 1307 #define DRV_MSG_CODE_LINK_STATUS_CHANGED 0x01000000 1308 1309 #define DRV_MSG_CODE_INITIATE_FLR 0x02000000 1310 #define REQ_BC_VER_4_INITIATE_FLR 0x00070213 1311 1312 #define BIOS_MSG_CODE_LIC_CHALLENGE 0xff010000 1313 #define BIOS_MSG_CODE_LIC_RESPONSE 0xff020000 1314 #define BIOS_MSG_CODE_VIRT_MAC_PRIM 0xff030000 1315 #define BIOS_MSG_CODE_VIRT_MAC_ISCSI 0xff040000 1316 1317 #define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff 1318 1319 u32 drv_mb_param; 1320 #define DRV_MSG_CODE_SET_MF_BW_MIN_MASK 0x00ff0000 1321 #define DRV_MSG_CODE_SET_MF_BW_MAX_MASK 0xff000000 1322 1323 #define DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET 0x00000002 1324 1325 #define DRV_MSG_CODE_LOAD_REQ_WITH_LFA 0x0000100a 1326 u32 fw_mb_header; 1327 #define FW_MSG_CODE_MASK 0xffff0000 1328 #define FW_MSG_CODE_DRV_LOAD_COMMON 0x10100000 1329 #define FW_MSG_CODE_DRV_LOAD_PORT 0x10110000 1330 #define FW_MSG_CODE_DRV_LOAD_FUNCTION 0x10120000 1331 /* Load common chip is supported from bc 6.0.0 */ 1332 #define REQ_BC_VER_4_DRV_LOAD_COMMON_CHIP 0x00060000 1333 #define FW_MSG_CODE_DRV_LOAD_COMMON_CHIP 0x10130000 1334 1335 #define FW_MSG_CODE_DRV_LOAD_REFUSED 0x10200000 1336 #define FW_MSG_CODE_DRV_LOAD_DONE 0x11100000 1337 #define FW_MSG_CODE_DRV_UNLOAD_COMMON 0x20100000 1338 #define FW_MSG_CODE_DRV_UNLOAD_PORT 0x20110000 1339 #define FW_MSG_CODE_DRV_UNLOAD_FUNCTION 0x20120000 1340 #define FW_MSG_CODE_DRV_UNLOAD_DONE 0x21100000 1341 #define FW_MSG_CODE_DCC_DONE 0x30100000 1342 #define FW_MSG_CODE_LLDP_DONE 0x40100000 1343 #define FW_MSG_CODE_DIAG_ENTER_DONE 0x50100000 1344 #define FW_MSG_CODE_DIAG_REFUSE 0x50200000 1345 #define FW_MSG_CODE_DIAG_EXIT_DONE 0x60100000 1346 #define FW_MSG_CODE_VALIDATE_KEY_SUCCESS 0x70100000 1347 #define FW_MSG_CODE_VALIDATE_KEY_FAILURE 0x70200000 1348 #define FW_MSG_CODE_GET_KEY_DONE 0x80100000 1349 #define FW_MSG_CODE_NO_KEY 0x80f00000 1350 #define FW_MSG_CODE_LIC_INFO_NOT_READY 0x80f80000 1351 #define FW_MSG_CODE_L2B_PRAM_LOADED 0x90100000 1352 #define FW_MSG_CODE_L2B_PRAM_T_LOAD_FAILURE 0x90210000 1353 #define FW_MSG_CODE_L2B_PRAM_C_LOAD_FAILURE 0x90220000 1354 #define FW_MSG_CODE_L2B_PRAM_X_LOAD_FAILURE 0x90230000 1355 #define FW_MSG_CODE_L2B_PRAM_U_LOAD_FAILURE 0x90240000 1356 #define FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS 0xa0100000 1357 #define FW_MSG_CODE_VRFY_OPT_MDL_INVLD_IMG 0xa0200000 1358 #define FW_MSG_CODE_VRFY_OPT_MDL_UNAPPROVED 0xa0300000 1359 #define FW_MSG_CODE_VF_DISABLED_DONE 0xb0000000 1360 #define FW_MSG_CODE_HW_SET_INVALID_IMAGE 0xb0100000 1361 1362 #define FW_MSG_CODE_AFEX_DRIVER_SETMAC_DONE 0xd0100000 1363 #define FW_MSG_CODE_AFEX_LISTGET_ACK 0xd1100000 1364 #define FW_MSG_CODE_AFEX_LISTSET_ACK 0xd2100000 1365 #define FW_MSG_CODE_AFEX_STATSGET_ACK 0xd3100000 1366 #define FW_MSG_CODE_AFEX_VIFSET_ACK 0xd4100000 1367 1368 #define FW_MSG_CODE_DRV_INFO_ACK 0xd8100000 1369 #define FW_MSG_CODE_DRV_INFO_NACK 0xd9100000 1370 1371 #define FW_MSG_CODE_EEE_RESULS_ACK 0xda100000 1372 1373 #define FW_MSG_CODE_SET_MF_BW_SENT 0xe0000000 1374 #define FW_MSG_CODE_SET_MF_BW_DONE 0xe1000000 1375 1376 #define FW_MSG_CODE_LINK_CHANGED_ACK 0x01100000 1377 1378 #define FW_MSG_CODE_LIC_CHALLENGE 0xff010000 1379 #define FW_MSG_CODE_LIC_RESPONSE 0xff020000 1380 #define FW_MSG_CODE_VIRT_MAC_PRIM 0xff030000 1381 #define FW_MSG_CODE_VIRT_MAC_ISCSI 0xff040000 1382 1383 #define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff 1384 1385 u32 fw_mb_param; 1386 1387 u32 drv_pulse_mb; 1388 #define DRV_PULSE_SEQ_MASK 0x00007fff 1389 #define DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000 1390 /* 1391 * The system time is in the format of 1392 * (year-2001)*12*32 + month*32 + day. 1393 */ 1394 #define DRV_PULSE_ALWAYS_ALIVE 0x00008000 1395 /* 1396 * Indicate to the firmware not to go into the 1397 * OS-absent when it is not getting driver pulse. 1398 * This is used for debugging as well for PXE(MBA). 1399 */ 1400 1401 u32 mcp_pulse_mb; 1402 #define MCP_PULSE_SEQ_MASK 0x00007fff 1403 #define MCP_PULSE_ALWAYS_ALIVE 0x00008000 1404 /* Indicates to the driver not to assert due to lack 1405 * of MCP response */ 1406 #define MCP_EVENT_MASK 0xffff0000 1407 #define MCP_EVENT_OTHER_DRIVER_RESET_REQ 0x00010000 1408 1409 u32 iscsi_boot_signature; 1410 u32 iscsi_boot_block_offset; 1411 1412 u32 drv_status; 1413 #define DRV_STATUS_PMF 0x00000001 1414 #define DRV_STATUS_VF_DISABLED 0x00000002 1415 #define DRV_STATUS_SET_MF_BW 0x00000004 1416 #define DRV_STATUS_LINK_EVENT 0x00000008 1417 1418 #define DRV_STATUS_DCC_EVENT_MASK 0x0000ff00 1419 #define DRV_STATUS_DCC_DISABLE_ENABLE_PF 0x00000100 1420 #define DRV_STATUS_DCC_BANDWIDTH_ALLOCATION 0x00000200 1421 #define DRV_STATUS_DCC_CHANGE_MAC_ADDRESS 0x00000400 1422 #define DRV_STATUS_DCC_RESERVED1 0x00000800 1423 #define DRV_STATUS_DCC_SET_PROTOCOL 0x00001000 1424 #define DRV_STATUS_DCC_SET_PRIORITY 0x00002000 1425 1426 #define DRV_STATUS_DCBX_EVENT_MASK 0x000f0000 1427 #define DRV_STATUS_DCBX_NEGOTIATION_RESULTS 0x00010000 1428 #define DRV_STATUS_AFEX_EVENT_MASK 0x03f00000 1429 #define DRV_STATUS_AFEX_LISTGET_REQ 0x00100000 1430 #define DRV_STATUS_AFEX_LISTSET_REQ 0x00200000 1431 #define DRV_STATUS_AFEX_STATSGET_REQ 0x00400000 1432 #define DRV_STATUS_AFEX_VIFSET_REQ 0x00800000 1433 1434 #define DRV_STATUS_DRV_INFO_REQ 0x04000000 1435 1436 #define DRV_STATUS_EEE_NEGOTIATION_RESULTS 0x08000000 1437 1438 u32 virt_mac_upper; 1439 #define VIRT_MAC_SIGN_MASK 0xffff0000 1440 #define VIRT_MAC_SIGNATURE 0x564d0000 1441 u32 virt_mac_lower; 1442 1443 }; 1444 1445 1446 /**************************************************************************** 1447 * Management firmware state * 1448 ****************************************************************************/ 1449 /* Allocate 440 bytes for management firmware */ 1450 #define MGMTFW_STATE_WORD_SIZE 110 1451 1452 struct mgmtfw_state { 1453 u32 opaque[MGMTFW_STATE_WORD_SIZE]; 1454 }; 1455 1456 1457 /**************************************************************************** 1458 * Multi-Function configuration * 1459 ****************************************************************************/ 1460 struct shared_mf_cfg { 1461 1462 u32 clp_mb; 1463 #define SHARED_MF_CLP_SET_DEFAULT 0x00000000 1464 /* set by CLP */ 1465 #define SHARED_MF_CLP_EXIT 0x00000001 1466 /* set by MCP */ 1467 #define SHARED_MF_CLP_EXIT_DONE 0x00010000 1468 1469 }; 1470 1471 struct port_mf_cfg { 1472 1473 u32 dynamic_cfg; /* device control channel */ 1474 #define PORT_MF_CFG_E1HOV_TAG_MASK 0x0000ffff 1475 #define PORT_MF_CFG_E1HOV_TAG_SHIFT 0 1476 #define PORT_MF_CFG_E1HOV_TAG_DEFAULT PORT_MF_CFG_E1HOV_TAG_MASK 1477 1478 u32 reserved[1]; 1479 1480 }; 1481 1482 struct func_mf_cfg { 1483 1484 u32 config; 1485 /* E/R/I/D */ 1486 /* function 0 of each port cannot be hidden */ 1487 #define FUNC_MF_CFG_FUNC_HIDE 0x00000001 1488 1489 #define FUNC_MF_CFG_PROTOCOL_MASK 0x00000006 1490 #define FUNC_MF_CFG_PROTOCOL_FCOE 0x00000000 1491 #define FUNC_MF_CFG_PROTOCOL_ETHERNET 0x00000002 1492 #define FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA 0x00000004 1493 #define FUNC_MF_CFG_PROTOCOL_ISCSI 0x00000006 1494 #define FUNC_MF_CFG_PROTOCOL_DEFAULT \ 1495 FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA 1496 1497 #define FUNC_MF_CFG_FUNC_DISABLED 0x00000008 1498 #define FUNC_MF_CFG_FUNC_DELETED 0x00000010 1499 1500 /* PRI */ 1501 /* 0 - low priority, 3 - high priority */ 1502 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK 0x00000300 1503 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT 8 1504 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_DEFAULT 0x00000000 1505 1506 /* MINBW, MAXBW */ 1507 /* value range - 0..100, increments in 100Mbps */ 1508 #define FUNC_MF_CFG_MIN_BW_MASK 0x00ff0000 1509 #define FUNC_MF_CFG_MIN_BW_SHIFT 16 1510 #define FUNC_MF_CFG_MIN_BW_DEFAULT 0x00000000 1511 #define FUNC_MF_CFG_MAX_BW_MASK 0xff000000 1512 #define FUNC_MF_CFG_MAX_BW_SHIFT 24 1513 #define FUNC_MF_CFG_MAX_BW_DEFAULT 0x64000000 1514 1515 u32 mac_upper; /* MAC */ 1516 #define FUNC_MF_CFG_UPPERMAC_MASK 0x0000ffff 1517 #define FUNC_MF_CFG_UPPERMAC_SHIFT 0 1518 #define FUNC_MF_CFG_UPPERMAC_DEFAULT FUNC_MF_CFG_UPPERMAC_MASK 1519 u32 mac_lower; 1520 #define FUNC_MF_CFG_LOWERMAC_DEFAULT 0xffffffff 1521 1522 u32 e1hov_tag; /* VNI */ 1523 #define FUNC_MF_CFG_E1HOV_TAG_MASK 0x0000ffff 1524 #define FUNC_MF_CFG_E1HOV_TAG_SHIFT 0 1525 #define FUNC_MF_CFG_E1HOV_TAG_DEFAULT FUNC_MF_CFG_E1HOV_TAG_MASK 1526 1527 /* afex default VLAN ID - 12 bits */ 1528 #define FUNC_MF_CFG_AFEX_VLAN_MASK 0x0fff0000 1529 #define FUNC_MF_CFG_AFEX_VLAN_SHIFT 16 1530 1531 u32 afex_config; 1532 #define FUNC_MF_CFG_AFEX_COS_FILTER_MASK 0x000000ff 1533 #define FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT 0 1534 #define FUNC_MF_CFG_AFEX_MBA_ENABLED_MASK 0x0000ff00 1535 #define FUNC_MF_CFG_AFEX_MBA_ENABLED_SHIFT 8 1536 #define FUNC_MF_CFG_AFEX_MBA_ENABLED_VAL 0x00000100 1537 #define FUNC_MF_CFG_AFEX_VLAN_MODE_MASK 0x000f0000 1538 #define FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT 16 1539 1540 u32 reserved; 1541 }; 1542 1543 enum mf_cfg_afex_vlan_mode { 1544 FUNC_MF_CFG_AFEX_VLAN_TRUNK_MODE = 0, 1545 FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE, 1546 FUNC_MF_CFG_AFEX_VLAN_TRUNK_TAG_NATIVE_MODE 1547 }; 1548 1549 /* This structure is not applicable and should not be accessed on 57711 */ 1550 struct func_ext_cfg { 1551 u32 func_cfg; 1552 #define MACP_FUNC_CFG_FLAGS_MASK 0x0000007F 1553 #define MACP_FUNC_CFG_FLAGS_SHIFT 0 1554 #define MACP_FUNC_CFG_FLAGS_ENABLED 0x00000001 1555 #define MACP_FUNC_CFG_FLAGS_ETHERNET 0x00000002 1556 #define MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD 0x00000004 1557 #define MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD 0x00000008 1558 #define MACP_FUNC_CFG_PAUSE_ON_HOST_RING 0x00000080 1559 1560 u32 iscsi_mac_addr_upper; 1561 u32 iscsi_mac_addr_lower; 1562 1563 u32 fcoe_mac_addr_upper; 1564 u32 fcoe_mac_addr_lower; 1565 1566 u32 fcoe_wwn_port_name_upper; 1567 u32 fcoe_wwn_port_name_lower; 1568 1569 u32 fcoe_wwn_node_name_upper; 1570 u32 fcoe_wwn_node_name_lower; 1571 1572 u32 preserve_data; 1573 #define MF_FUNC_CFG_PRESERVE_L2_MAC (1<<0) 1574 #define MF_FUNC_CFG_PRESERVE_ISCSI_MAC (1<<1) 1575 #define MF_FUNC_CFG_PRESERVE_FCOE_MAC (1<<2) 1576 #define MF_FUNC_CFG_PRESERVE_FCOE_WWN_P (1<<3) 1577 #define MF_FUNC_CFG_PRESERVE_FCOE_WWN_N (1<<4) 1578 #define MF_FUNC_CFG_PRESERVE_TX_BW (1<<5) 1579 }; 1580 1581 struct mf_cfg { 1582 1583 struct shared_mf_cfg shared_mf_config; /* 0x4 */ 1584 /* 0x8*2*2=0x20 */ 1585 struct port_mf_cfg port_mf_config[NVM_PATH_MAX][PORT_MAX]; 1586 /* for all chips, there are 8 mf functions */ 1587 struct func_mf_cfg func_mf_config[E1H_FUNC_MAX]; /* 0x18 * 8 = 0xc0 */ 1588 /* 1589 * Extended configuration per function - this array does not exist and 1590 * should not be accessed on 57711 1591 */ 1592 struct func_ext_cfg func_ext_config[E1H_FUNC_MAX]; /* 0x28 * 8 = 0x140*/ 1593 }; /* 0x224 */ 1594 1595 /**************************************************************************** 1596 * Shared Memory Region * 1597 ****************************************************************************/ 1598 struct shmem_region { /* SharedMem Offset (size) */ 1599 1600 u32 validity_map[PORT_MAX]; /* 0x0 (4*2 = 0x8) */ 1601 #define SHR_MEM_FORMAT_REV_MASK 0xff000000 1602 #define SHR_MEM_FORMAT_REV_ID ('A'<<24) 1603 /* validity bits */ 1604 #define SHR_MEM_VALIDITY_PCI_CFG 0x00100000 1605 #define SHR_MEM_VALIDITY_MB 0x00200000 1606 #define SHR_MEM_VALIDITY_DEV_INFO 0x00400000 1607 #define SHR_MEM_VALIDITY_RESERVED 0x00000007 1608 /* One licensing bit should be set */ 1609 #define SHR_MEM_VALIDITY_LIC_KEY_IN_EFFECT_MASK 0x00000038 1610 #define SHR_MEM_VALIDITY_LIC_MANUF_KEY_IN_EFFECT 0x00000008 1611 #define SHR_MEM_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT 0x00000010 1612 #define SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT 0x00000020 1613 /* Active MFW */ 1614 #define SHR_MEM_VALIDITY_ACTIVE_MFW_UNKNOWN 0x00000000 1615 #define SHR_MEM_VALIDITY_ACTIVE_MFW_MASK 0x000001c0 1616 #define SHR_MEM_VALIDITY_ACTIVE_MFW_IPMI 0x00000040 1617 #define SHR_MEM_VALIDITY_ACTIVE_MFW_UMP 0x00000080 1618 #define SHR_MEM_VALIDITY_ACTIVE_MFW_NCSI 0x000000c0 1619 #define SHR_MEM_VALIDITY_ACTIVE_MFW_NONE 0x000001c0 1620 1621 struct shm_dev_info dev_info; /* 0x8 (0x438) */ 1622 1623 struct license_key drv_lic_key[PORT_MAX]; /* 0x440 (52*2=0x68) */ 1624 1625 /* FW information (for internal FW use) */ 1626 u32 fw_info_fio_offset; /* 0x4a8 (0x4) */ 1627 struct mgmtfw_state mgmtfw_state; /* 0x4ac (0x1b8) */ 1628 1629 struct drv_port_mb port_mb[PORT_MAX]; /* 0x664 (16*2=0x20) */ 1630 1631 #ifdef BMAPI 1632 /* This is a variable length array */ 1633 /* the number of function depends on the chip type */ 1634 struct drv_func_mb func_mb[1]; /* 0x684 (44*2/4/8=0x58/0xb0/0x160) */ 1635 #else 1636 /* the number of function depends on the chip type */ 1637 struct drv_func_mb func_mb[]; /* 0x684 (44*2/4/8=0x58/0xb0/0x160) */ 1638 #endif /* BMAPI */ 1639 1640 }; /* 57710 = 0x6dc | 57711 = 0x7E4 | 57712 = 0x734 */ 1641 1642 /**************************************************************************** 1643 * Shared Memory 2 Region * 1644 ****************************************************************************/ 1645 /* The fw_flr_ack is actually built in the following way: */ 1646 /* 8 bit: PF ack */ 1647 /* 64 bit: VF ack */ 1648 /* 8 bit: ios_dis_ack */ 1649 /* In order to maintain endianity in the mailbox hsi, we want to keep using */ 1650 /* u32. The fw must have the VF right after the PF since this is how it */ 1651 /* access arrays(it expects always the VF to reside after the PF, and that */ 1652 /* makes the calculation much easier for it. ) */ 1653 /* In order to answer both limitations, and keep the struct small, the code */ 1654 /* will abuse the structure defined here to achieve the actual partition */ 1655 /* above */ 1656 /****************************************************************************/ 1657 struct fw_flr_ack { 1658 u32 pf_ack; 1659 u32 vf_ack[1]; 1660 u32 iov_dis_ack; 1661 }; 1662 1663 struct fw_flr_mb { 1664 u32 aggint; 1665 u32 opgen_addr; 1666 struct fw_flr_ack ack; 1667 }; 1668 1669 struct eee_remote_vals { 1670 u32 tx_tw; 1671 u32 rx_tw; 1672 }; 1673 1674 /**** SUPPORT FOR SHMEM ARRRAYS *** 1675 * The SHMEM HSI is aligned on 32 bit boundaries which makes it difficult to 1676 * define arrays with storage types smaller then unsigned dwords. 1677 * The macros below add generic support for SHMEM arrays with numeric elements 1678 * that can span 2,4,8 or 16 bits. The array underlying type is a 32 bit dword 1679 * array with individual bit-filed elements accessed using shifts and masks. 1680 * 1681 */ 1682 1683 /* eb is the bitwidth of a single element */ 1684 #define SHMEM_ARRAY_MASK(eb) ((1<<(eb))-1) 1685 #define SHMEM_ARRAY_ENTRY(i, eb) ((i)/(32/(eb))) 1686 1687 /* the bit-position macro allows the used to flip the order of the arrays 1688 * elements on a per byte or word boundary. 1689 * 1690 * example: an array with 8 entries each 4 bit wide. This array will fit into 1691 * a single dword. The diagrmas below show the array order of the nibbles. 1692 * 1693 * SHMEM_ARRAY_BITPOS(i, 4, 4) defines the stadard ordering: 1694 * 1695 * | | | | 1696 * 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 1697 * | | | | 1698 * 1699 * SHMEM_ARRAY_BITPOS(i, 4, 8) defines a flip ordering per byte: 1700 * 1701 * | | | | 1702 * 1 | 0 | 3 | 2 | 5 | 4 | 7 | 6 | 1703 * | | | | 1704 * 1705 * SHMEM_ARRAY_BITPOS(i, 4, 16) defines a flip ordering per word: 1706 * 1707 * | | | | 1708 * 3 | 2 | 1 | 0 | 7 | 6 | 5 | 4 | 1709 * | | | | 1710 */ 1711 #define SHMEM_ARRAY_BITPOS(i, eb, fb) \ 1712 ((((32/(fb)) - 1 - ((i)/((fb)/(eb))) % (32/(fb))) * (fb)) + \ 1713 (((i)%((fb)/(eb))) * (eb))) 1714 1715 #define SHMEM_ARRAY_GET(a, i, eb, fb) \ 1716 ((a[SHMEM_ARRAY_ENTRY(i, eb)] >> SHMEM_ARRAY_BITPOS(i, eb, fb)) & \ 1717 SHMEM_ARRAY_MASK(eb)) 1718 1719 #define SHMEM_ARRAY_SET(a, i, eb, fb, val) \ 1720 do { \ 1721 a[SHMEM_ARRAY_ENTRY(i, eb)] &= ~(SHMEM_ARRAY_MASK(eb) << \ 1722 SHMEM_ARRAY_BITPOS(i, eb, fb)); \ 1723 a[SHMEM_ARRAY_ENTRY(i, eb)] |= (((val) & SHMEM_ARRAY_MASK(eb)) << \ 1724 SHMEM_ARRAY_BITPOS(i, eb, fb)); \ 1725 } while (0) 1726 1727 1728 /****START OF DCBX STRUCTURES DECLARATIONS****/ 1729 #define DCBX_MAX_NUM_PRI_PG_ENTRIES 8 1730 #define DCBX_PRI_PG_BITWIDTH 4 1731 #define DCBX_PRI_PG_FBITS 8 1732 #define DCBX_PRI_PG_GET(a, i) \ 1733 SHMEM_ARRAY_GET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS) 1734 #define DCBX_PRI_PG_SET(a, i, val) \ 1735 SHMEM_ARRAY_SET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS, val) 1736 #define DCBX_MAX_NUM_PG_BW_ENTRIES 8 1737 #define DCBX_BW_PG_BITWIDTH 8 1738 #define DCBX_PG_BW_GET(a, i) \ 1739 SHMEM_ARRAY_GET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH) 1740 #define DCBX_PG_BW_SET(a, i, val) \ 1741 SHMEM_ARRAY_SET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH, val) 1742 #define DCBX_STRICT_PRI_PG 15 1743 #define DCBX_MAX_APP_PROTOCOL 16 1744 #define FCOE_APP_IDX 0 1745 #define ISCSI_APP_IDX 1 1746 #define PREDEFINED_APP_IDX_MAX 2 1747 1748 1749 /* Big/Little endian have the same representation. */ 1750 struct dcbx_ets_feature { 1751 /* 1752 * For Admin MIB - is this feature supported by the 1753 * driver | For Local MIB - should this feature be enabled. 1754 */ 1755 u32 enabled; 1756 u32 pg_bw_tbl[2]; 1757 u32 pri_pg_tbl[1]; 1758 }; 1759 1760 /* Driver structure in LE */ 1761 struct dcbx_pfc_feature { 1762 #ifdef __BIG_ENDIAN 1763 u8 pri_en_bitmap; 1764 #define DCBX_PFC_PRI_0 0x01 1765 #define DCBX_PFC_PRI_1 0x02 1766 #define DCBX_PFC_PRI_2 0x04 1767 #define DCBX_PFC_PRI_3 0x08 1768 #define DCBX_PFC_PRI_4 0x10 1769 #define DCBX_PFC_PRI_5 0x20 1770 #define DCBX_PFC_PRI_6 0x40 1771 #define DCBX_PFC_PRI_7 0x80 1772 u8 pfc_caps; 1773 u8 reserved; 1774 u8 enabled; 1775 #elif defined(__LITTLE_ENDIAN) 1776 u8 enabled; 1777 u8 reserved; 1778 u8 pfc_caps; 1779 u8 pri_en_bitmap; 1780 #define DCBX_PFC_PRI_0 0x01 1781 #define DCBX_PFC_PRI_1 0x02 1782 #define DCBX_PFC_PRI_2 0x04 1783 #define DCBX_PFC_PRI_3 0x08 1784 #define DCBX_PFC_PRI_4 0x10 1785 #define DCBX_PFC_PRI_5 0x20 1786 #define DCBX_PFC_PRI_6 0x40 1787 #define DCBX_PFC_PRI_7 0x80 1788 #endif 1789 }; 1790 1791 struct dcbx_app_priority_entry { 1792 #ifdef __BIG_ENDIAN 1793 u16 app_id; 1794 u8 pri_bitmap; 1795 u8 appBitfield; 1796 #define DCBX_APP_ENTRY_VALID 0x01 1797 #define DCBX_APP_ENTRY_SF_MASK 0x30 1798 #define DCBX_APP_ENTRY_SF_SHIFT 4 1799 #define DCBX_APP_SF_ETH_TYPE 0x10 1800 #define DCBX_APP_SF_PORT 0x20 1801 #elif defined(__LITTLE_ENDIAN) 1802 u8 appBitfield; 1803 #define DCBX_APP_ENTRY_VALID 0x01 1804 #define DCBX_APP_ENTRY_SF_MASK 0x30 1805 #define DCBX_APP_ENTRY_SF_SHIFT 4 1806 #define DCBX_APP_SF_ETH_TYPE 0x10 1807 #define DCBX_APP_SF_PORT 0x20 1808 u8 pri_bitmap; 1809 u16 app_id; 1810 #endif 1811 }; 1812 1813 1814 /* FW structure in BE */ 1815 struct dcbx_app_priority_feature { 1816 #ifdef __BIG_ENDIAN 1817 u8 reserved; 1818 u8 default_pri; 1819 u8 tc_supported; 1820 u8 enabled; 1821 #elif defined(__LITTLE_ENDIAN) 1822 u8 enabled; 1823 u8 tc_supported; 1824 u8 default_pri; 1825 u8 reserved; 1826 #endif 1827 struct dcbx_app_priority_entry app_pri_tbl[DCBX_MAX_APP_PROTOCOL]; 1828 }; 1829 1830 /* FW structure in BE */ 1831 struct dcbx_features { 1832 /* PG feature */ 1833 struct dcbx_ets_feature ets; 1834 /* PFC feature */ 1835 struct dcbx_pfc_feature pfc; 1836 /* APP feature */ 1837 struct dcbx_app_priority_feature app; 1838 }; 1839 1840 /* LLDP protocol parameters */ 1841 /* FW structure in BE */ 1842 struct lldp_params { 1843 #ifdef __BIG_ENDIAN 1844 u8 msg_fast_tx_interval; 1845 u8 msg_tx_hold; 1846 u8 msg_tx_interval; 1847 u8 admin_status; 1848 #define LLDP_TX_ONLY 0x01 1849 #define LLDP_RX_ONLY 0x02 1850 #define LLDP_TX_RX 0x03 1851 #define LLDP_DISABLED 0x04 1852 u8 reserved1; 1853 u8 tx_fast; 1854 u8 tx_crd_max; 1855 u8 tx_crd; 1856 #elif defined(__LITTLE_ENDIAN) 1857 u8 admin_status; 1858 #define LLDP_TX_ONLY 0x01 1859 #define LLDP_RX_ONLY 0x02 1860 #define LLDP_TX_RX 0x03 1861 #define LLDP_DISABLED 0x04 1862 u8 msg_tx_interval; 1863 u8 msg_tx_hold; 1864 u8 msg_fast_tx_interval; 1865 u8 tx_crd; 1866 u8 tx_crd_max; 1867 u8 tx_fast; 1868 u8 reserved1; 1869 #endif 1870 #define REM_CHASSIS_ID_STAT_LEN 4 1871 #define REM_PORT_ID_STAT_LEN 4 1872 /* Holds remote Chassis ID TLV header, subtype and 9B of payload. */ 1873 u32 peer_chassis_id[REM_CHASSIS_ID_STAT_LEN]; 1874 /* Holds remote Port ID TLV header, subtype and 9B of payload. */ 1875 u32 peer_port_id[REM_PORT_ID_STAT_LEN]; 1876 }; 1877 1878 struct lldp_dcbx_stat { 1879 #define LOCAL_CHASSIS_ID_STAT_LEN 2 1880 #define LOCAL_PORT_ID_STAT_LEN 2 1881 /* Holds local Chassis ID 8B payload of constant subtype 4. */ 1882 u32 local_chassis_id[LOCAL_CHASSIS_ID_STAT_LEN]; 1883 /* Holds local Port ID 8B payload of constant subtype 3. */ 1884 u32 local_port_id[LOCAL_PORT_ID_STAT_LEN]; 1885 /* Number of DCBX frames transmitted. */ 1886 u32 num_tx_dcbx_pkts; 1887 /* Number of DCBX frames received. */ 1888 u32 num_rx_dcbx_pkts; 1889 }; 1890 1891 /* ADMIN MIB - DCBX local machine default configuration. */ 1892 struct lldp_admin_mib { 1893 u32 ver_cfg_flags; 1894 #define DCBX_ETS_CONFIG_TX_ENABLED 0x00000001 1895 #define DCBX_PFC_CONFIG_TX_ENABLED 0x00000002 1896 #define DCBX_APP_CONFIG_TX_ENABLED 0x00000004 1897 #define DCBX_ETS_RECO_TX_ENABLED 0x00000008 1898 #define DCBX_ETS_RECO_VALID 0x00000010 1899 #define DCBX_ETS_WILLING 0x00000020 1900 #define DCBX_PFC_WILLING 0x00000040 1901 #define DCBX_APP_WILLING 0x00000080 1902 #define DCBX_VERSION_CEE 0x00000100 1903 #define DCBX_VERSION_IEEE 0x00000200 1904 #define DCBX_DCBX_ENABLED 0x00000400 1905 #define DCBX_CEE_VERSION_MASK 0x0000f000 1906 #define DCBX_CEE_VERSION_SHIFT 12 1907 #define DCBX_CEE_MAX_VERSION_MASK 0x000f0000 1908 #define DCBX_CEE_MAX_VERSION_SHIFT 16 1909 struct dcbx_features features; 1910 }; 1911 1912 /* REMOTE MIB - remote machine DCBX configuration. */ 1913 struct lldp_remote_mib { 1914 u32 prefix_seq_num; 1915 u32 flags; 1916 #define DCBX_ETS_TLV_RX 0x00000001 1917 #define DCBX_PFC_TLV_RX 0x00000002 1918 #define DCBX_APP_TLV_RX 0x00000004 1919 #define DCBX_ETS_RX_ERROR 0x00000010 1920 #define DCBX_PFC_RX_ERROR 0x00000020 1921 #define DCBX_APP_RX_ERROR 0x00000040 1922 #define DCBX_ETS_REM_WILLING 0x00000100 1923 #define DCBX_PFC_REM_WILLING 0x00000200 1924 #define DCBX_APP_REM_WILLING 0x00000400 1925 #define DCBX_REMOTE_ETS_RECO_VALID 0x00001000 1926 #define DCBX_REMOTE_MIB_VALID 0x00002000 1927 struct dcbx_features features; 1928 u32 suffix_seq_num; 1929 }; 1930 1931 /* LOCAL MIB - operational DCBX configuration - transmitted on Tx LLDPDU. */ 1932 struct lldp_local_mib { 1933 u32 prefix_seq_num; 1934 /* Indicates if there is mismatch with negotiation results. */ 1935 u32 error; 1936 #define DCBX_LOCAL_ETS_ERROR 0x00000001 1937 #define DCBX_LOCAL_PFC_ERROR 0x00000002 1938 #define DCBX_LOCAL_APP_ERROR 0x00000004 1939 #define DCBX_LOCAL_PFC_MISMATCH 0x00000010 1940 #define DCBX_LOCAL_APP_MISMATCH 0x00000020 1941 #define DCBX_REMOTE_MIB_ERROR 0x00000040 1942 #define DCBX_REMOTE_ETS_TLV_NOT_FOUND 0x00000080 1943 #define DCBX_REMOTE_PFC_TLV_NOT_FOUND 0x00000100 1944 #define DCBX_REMOTE_APP_TLV_NOT_FOUND 0x00000200 1945 struct dcbx_features features; 1946 u32 suffix_seq_num; 1947 }; 1948 /***END OF DCBX STRUCTURES DECLARATIONS***/ 1949 1950 /***********************************************************/ 1951 /* Elink section */ 1952 /***********************************************************/ 1953 #define SHMEM_LINK_CONFIG_SIZE 2 1954 struct shmem_lfa { 1955 u32 req_duplex; 1956 #define REQ_DUPLEX_PHY0_MASK 0x0000ffff 1957 #define REQ_DUPLEX_PHY0_SHIFT 0 1958 #define REQ_DUPLEX_PHY1_MASK 0xffff0000 1959 #define REQ_DUPLEX_PHY1_SHIFT 16 1960 u32 req_flow_ctrl; 1961 #define REQ_FLOW_CTRL_PHY0_MASK 0x0000ffff 1962 #define REQ_FLOW_CTRL_PHY0_SHIFT 0 1963 #define REQ_FLOW_CTRL_PHY1_MASK 0xffff0000 1964 #define REQ_FLOW_CTRL_PHY1_SHIFT 16 1965 u32 req_line_speed; /* Also determine AutoNeg */ 1966 #define REQ_LINE_SPD_PHY0_MASK 0x0000ffff 1967 #define REQ_LINE_SPD_PHY0_SHIFT 0 1968 #define REQ_LINE_SPD_PHY1_MASK 0xffff0000 1969 #define REQ_LINE_SPD_PHY1_SHIFT 16 1970 u32 speed_cap_mask[SHMEM_LINK_CONFIG_SIZE]; 1971 u32 additional_config; 1972 #define REQ_FC_AUTO_ADV_MASK 0x0000ffff 1973 #define REQ_FC_AUTO_ADV0_SHIFT 0 1974 #define NO_LFA_DUE_TO_DCC_MASK 0x00010000 1975 u32 lfa_sts; 1976 #define LFA_LINK_FLAP_REASON_OFFSET 0 1977 #define LFA_LINK_FLAP_REASON_MASK 0x000000ff 1978 #define LFA_LINK_DOWN 0x1 1979 #define LFA_LOOPBACK_ENABLED 0x2 1980 #define LFA_DUPLEX_MISMATCH 0x3 1981 #define LFA_MFW_IS_TOO_OLD 0x4 1982 #define LFA_LINK_SPEED_MISMATCH 0x5 1983 #define LFA_FLOW_CTRL_MISMATCH 0x6 1984 #define LFA_SPEED_CAP_MISMATCH 0x7 1985 #define LFA_DCC_LFA_DISABLED 0x8 1986 #define LFA_EEE_MISMATCH 0x9 1987 1988 #define LINK_FLAP_AVOIDANCE_COUNT_OFFSET 8 1989 #define LINK_FLAP_AVOIDANCE_COUNT_MASK 0x0000ff00 1990 1991 #define LINK_FLAP_COUNT_OFFSET 16 1992 #define LINK_FLAP_COUNT_MASK 0x00ff0000 1993 1994 #define LFA_FLAGS_MASK 0xff000000 1995 #define SHMEM_LFA_DONT_CLEAR_STAT (1<<24) 1996 }; 1997 1998 struct ncsi_oem_fcoe_features { 1999 u32 fcoe_features1; 2000 #define FCOE_FEATURES1_IOS_PER_CONNECTION_MASK 0x0000FFFF 2001 #define FCOE_FEATURES1_IOS_PER_CONNECTION_OFFSET 0 2002 2003 #define FCOE_FEATURES1_LOGINS_PER_PORT_MASK 0xFFFF0000 2004 #define FCOE_FEATURES1_LOGINS_PER_PORT_OFFSET 16 2005 2006 u32 fcoe_features2; 2007 #define FCOE_FEATURES2_EXCHANGES_MASK 0x0000FFFF 2008 #define FCOE_FEATURES2_EXCHANGES_OFFSET 0 2009 2010 #define FCOE_FEATURES2_NPIV_WWN_PER_PORT_MASK 0xFFFF0000 2011 #define FCOE_FEATURES2_NPIV_WWN_PER_PORT_OFFSET 16 2012 2013 u32 fcoe_features3; 2014 #define FCOE_FEATURES3_TARGETS_SUPPORTED_MASK 0x0000FFFF 2015 #define FCOE_FEATURES3_TARGETS_SUPPORTED_OFFSET 0 2016 2017 #define FCOE_FEATURES3_OUTSTANDING_COMMANDS_MASK 0xFFFF0000 2018 #define FCOE_FEATURES3_OUTSTANDING_COMMANDS_OFFSET 16 2019 2020 u32 fcoe_features4; 2021 #define FCOE_FEATURES4_FEATURE_SETTINGS_MASK 0x0000000F 2022 #define FCOE_FEATURES4_FEATURE_SETTINGS_OFFSET 0 2023 }; 2024 2025 struct ncsi_oem_data { 2026 u32 driver_version[4]; 2027 struct ncsi_oem_fcoe_features ncsi_oem_fcoe_features; 2028 }; 2029 2030 struct shmem2_region { 2031 2032 u32 size; /* 0x0000 */ 2033 2034 u32 dcc_support; /* 0x0004 */ 2035 #define SHMEM_DCC_SUPPORT_NONE 0x00000000 2036 #define SHMEM_DCC_SUPPORT_DISABLE_ENABLE_PF_TLV 0x00000001 2037 #define SHMEM_DCC_SUPPORT_BANDWIDTH_ALLOCATION_TLV 0x00000004 2038 #define SHMEM_DCC_SUPPORT_CHANGE_MAC_ADDRESS_TLV 0x00000008 2039 #define SHMEM_DCC_SUPPORT_SET_PROTOCOL_TLV 0x00000040 2040 #define SHMEM_DCC_SUPPORT_SET_PRIORITY_TLV 0x00000080 2041 2042 u32 ext_phy_fw_version2[PORT_MAX]; /* 0x0008 */ 2043 /* 2044 * For backwards compatibility, if the mf_cfg_addr does not exist 2045 * (the size filed is smaller than 0xc) the mf_cfg resides at the 2046 * end of struct shmem_region 2047 */ 2048 u32 mf_cfg_addr; /* 0x0010 */ 2049 #define SHMEM_MF_CFG_ADDR_NONE 0x00000000 2050 2051 struct fw_flr_mb flr_mb; /* 0x0014 */ 2052 u32 dcbx_lldp_params_offset; /* 0x0028 */ 2053 #define SHMEM_LLDP_DCBX_PARAMS_NONE 0x00000000 2054 u32 dcbx_neg_res_offset; /* 0x002c */ 2055 #define SHMEM_DCBX_NEG_RES_NONE 0x00000000 2056 u32 dcbx_remote_mib_offset; /* 0x0030 */ 2057 #define SHMEM_DCBX_REMOTE_MIB_NONE 0x00000000 2058 /* 2059 * The other shmemX_base_addr holds the other path's shmem address 2060 * required for example in case of common phy init, or for path1 to know 2061 * the address of mcp debug trace which is located in offset from shmem 2062 * of path0 2063 */ 2064 u32 other_shmem_base_addr; /* 0x0034 */ 2065 u32 other_shmem2_base_addr; /* 0x0038 */ 2066 /* 2067 * mcp_vf_disabled is set by the MCP to indicate the driver about VFs 2068 * which were disabled/flred 2069 */ 2070 u32 mcp_vf_disabled[E2_VF_MAX / 32]; /* 0x003c */ 2071 2072 /* 2073 * drv_ack_vf_disabled is set by the PF driver to ack handled disabled 2074 * VFs 2075 */ 2076 u32 drv_ack_vf_disabled[E2_FUNC_MAX][E2_VF_MAX / 32]; /* 0x0044 */ 2077 2078 u32 dcbx_lldp_dcbx_stat_offset; /* 0x0064 */ 2079 #define SHMEM_LLDP_DCBX_STAT_NONE 0x00000000 2080 2081 /* 2082 * edebug_driver_if field is used to transfer messages between edebug 2083 * app to the driver through shmem2. 2084 * 2085 * message format: 2086 * bits 0-2 - function number / instance of driver to perform request 2087 * bits 3-5 - op code / is_ack? 2088 * bits 6-63 - data 2089 */ 2090 u32 edebug_driver_if[2]; /* 0x0068 */ 2091 #define EDEBUG_DRIVER_IF_OP_CODE_GET_PHYS_ADDR 1 2092 #define EDEBUG_DRIVER_IF_OP_CODE_GET_BUS_ADDR 2 2093 #define EDEBUG_DRIVER_IF_OP_CODE_DISABLE_STAT 3 2094 2095 u32 nvm_retain_bitmap_addr; /* 0x0070 */ 2096 2097 /* afex support of that driver */ 2098 u32 afex_driver_support; /* 0x0074 */ 2099 #define SHMEM_AFEX_VERSION_MASK 0x100f 2100 #define SHMEM_AFEX_SUPPORTED_VERSION_ONE 0x1001 2101 #define SHMEM_AFEX_REDUCED_DRV_LOADED 0x8000 2102 2103 /* driver receives addr in scratchpad to which it should respond */ 2104 u32 afex_scratchpad_addr_to_write[E2_FUNC_MAX]; 2105 2106 /* generic params from MCP to driver (value depends on the msg sent 2107 * to driver 2108 */ 2109 u32 afex_param1_to_driver[E2_FUNC_MAX]; /* 0x0088 */ 2110 u32 afex_param2_to_driver[E2_FUNC_MAX]; /* 0x0098 */ 2111 2112 u32 swim_base_addr; /* 0x0108 */ 2113 u32 swim_funcs; 2114 u32 swim_main_cb; 2115 2116 /* bitmap notifying which VIF profiles stored in nvram are enabled by 2117 * switch 2118 */ 2119 u32 afex_profiles_enabled[2]; 2120 2121 /* generic flags controlled by the driver */ 2122 u32 drv_flags; 2123 #define DRV_FLAGS_DCB_CONFIGURED 0x0 2124 #define DRV_FLAGS_DCB_CONFIGURATION_ABORTED 0x1 2125 #define DRV_FLAGS_DCB_MFW_CONFIGURED 0x2 2126 2127 #define DRV_FLAGS_PORT_MASK ((1 << DRV_FLAGS_DCB_CONFIGURED) | \ 2128 (1 << DRV_FLAGS_DCB_CONFIGURATION_ABORTED) | \ 2129 (1 << DRV_FLAGS_DCB_MFW_CONFIGURED)) 2130 /* pointer to extended dev_info shared data copied from nvm image */ 2131 u32 extended_dev_info_shared_addr; 2132 u32 ncsi_oem_data_addr; 2133 2134 u32 ocsd_host_addr; /* initialized by option ROM */ 2135 u32 ocbb_host_addr; /* initialized by option ROM */ 2136 u32 ocsd_req_update_interval; /* initialized by option ROM */ 2137 u32 temperature_in_half_celsius; 2138 u32 glob_struct_in_host; 2139 2140 u32 dcbx_neg_res_ext_offset; 2141 #define SHMEM_DCBX_NEG_RES_EXT_NONE 0x00000000 2142 2143 u32 drv_capabilities_flag[E2_FUNC_MAX]; 2144 #define DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED 0x00000001 2145 #define DRV_FLAGS_CAPABILITIES_LOADED_L2 0x00000002 2146 #define DRV_FLAGS_CAPABILITIES_LOADED_FCOE 0x00000004 2147 #define DRV_FLAGS_CAPABILITIES_LOADED_ISCSI 0x00000008 2148 2149 u32 extended_dev_info_shared_cfg_size; 2150 2151 u32 dcbx_en[PORT_MAX]; 2152 2153 /* The offset points to the multi threaded meta structure */ 2154 u32 multi_thread_data_offset; 2155 2156 /* address of DMAable host address holding values from the drivers */ 2157 u32 drv_info_host_addr_lo; 2158 u32 drv_info_host_addr_hi; 2159 2160 /* general values written by the MFW (such as current version) */ 2161 u32 drv_info_control; 2162 #define DRV_INFO_CONTROL_VER_MASK 0x000000ff 2163 #define DRV_INFO_CONTROL_VER_SHIFT 0 2164 #define DRV_INFO_CONTROL_OP_CODE_MASK 0x0000ff00 2165 #define DRV_INFO_CONTROL_OP_CODE_SHIFT 8 2166 u32 ibft_host_addr; /* initialized by option ROM */ 2167 struct eee_remote_vals eee_remote_vals[PORT_MAX]; 2168 u32 reserved[E2_FUNC_MAX]; 2169 2170 2171 /* the status of EEE auto-negotiation 2172 * bits 15:0 the configured tx-lpi entry timer value. Depends on bit 31. 2173 * bits 19:16 the supported modes for EEE. 2174 * bits 23:20 the speeds advertised for EEE. 2175 * bits 27:24 the speeds the Link partner advertised for EEE. 2176 * The supported/adv. modes in bits 27:19 originate from the 2177 * SHMEM_EEE_XXX_ADV definitions (where XXX is replaced by speed). 2178 * bit 28 when 1'b1 EEE was requested. 2179 * bit 29 when 1'b1 tx lpi was requested. 2180 * bit 30 when 1'b1 EEE was negotiated. Tx lpi will be asserted iff 2181 * 30:29 are 2'b11. 2182 * bit 31 when 1'b0 bits 15:0 contain a PORT_FEAT_CFG_EEE_ define as 2183 * value. When 1'b1 those bits contains a value times 16 microseconds. 2184 */ 2185 u32 eee_status[PORT_MAX]; 2186 #define SHMEM_EEE_TIMER_MASK 0x0000ffff 2187 #define SHMEM_EEE_SUPPORTED_MASK 0x000f0000 2188 #define SHMEM_EEE_SUPPORTED_SHIFT 16 2189 #define SHMEM_EEE_ADV_STATUS_MASK 0x00f00000 2190 #define SHMEM_EEE_100M_ADV (1<<0) 2191 #define SHMEM_EEE_1G_ADV (1<<1) 2192 #define SHMEM_EEE_10G_ADV (1<<2) 2193 #define SHMEM_EEE_ADV_STATUS_SHIFT 20 2194 #define SHMEM_EEE_LP_ADV_STATUS_MASK 0x0f000000 2195 #define SHMEM_EEE_LP_ADV_STATUS_SHIFT 24 2196 #define SHMEM_EEE_REQUESTED_BIT 0x10000000 2197 #define SHMEM_EEE_LPI_REQUESTED_BIT 0x20000000 2198 #define SHMEM_EEE_ACTIVE_BIT 0x40000000 2199 #define SHMEM_EEE_TIME_OUTPUT_BIT 0x80000000 2200 2201 u32 sizeof_port_stats; 2202 2203 /* Link Flap Avoidance */ 2204 u32 lfa_host_addr[PORT_MAX]; 2205 u32 reserved1; 2206 2207 u32 reserved2; /* Offset 0x148 */ 2208 u32 reserved3; /* Offset 0x14C */ 2209 u32 reserved4; /* Offset 0x150 */ 2210 u32 link_attr_sync[PORT_MAX]; /* Offset 0x154 */ 2211 #define LINK_ATTR_SYNC_KR2_ENABLE (1<<0) 2212 }; 2213 2214 2215 struct emac_stats { 2216 u32 rx_stat_ifhcinoctets; 2217 u32 rx_stat_ifhcinbadoctets; 2218 u32 rx_stat_etherstatsfragments; 2219 u32 rx_stat_ifhcinucastpkts; 2220 u32 rx_stat_ifhcinmulticastpkts; 2221 u32 rx_stat_ifhcinbroadcastpkts; 2222 u32 rx_stat_dot3statsfcserrors; 2223 u32 rx_stat_dot3statsalignmenterrors; 2224 u32 rx_stat_dot3statscarriersenseerrors; 2225 u32 rx_stat_xonpauseframesreceived; 2226 u32 rx_stat_xoffpauseframesreceived; 2227 u32 rx_stat_maccontrolframesreceived; 2228 u32 rx_stat_xoffstateentered; 2229 u32 rx_stat_dot3statsframestoolong; 2230 u32 rx_stat_etherstatsjabbers; 2231 u32 rx_stat_etherstatsundersizepkts; 2232 u32 rx_stat_etherstatspkts64octets; 2233 u32 rx_stat_etherstatspkts65octetsto127octets; 2234 u32 rx_stat_etherstatspkts128octetsto255octets; 2235 u32 rx_stat_etherstatspkts256octetsto511octets; 2236 u32 rx_stat_etherstatspkts512octetsto1023octets; 2237 u32 rx_stat_etherstatspkts1024octetsto1522octets; 2238 u32 rx_stat_etherstatspktsover1522octets; 2239 2240 u32 rx_stat_falsecarriererrors; 2241 2242 u32 tx_stat_ifhcoutoctets; 2243 u32 tx_stat_ifhcoutbadoctets; 2244 u32 tx_stat_etherstatscollisions; 2245 u32 tx_stat_outxonsent; 2246 u32 tx_stat_outxoffsent; 2247 u32 tx_stat_flowcontroldone; 2248 u32 tx_stat_dot3statssinglecollisionframes; 2249 u32 tx_stat_dot3statsmultiplecollisionframes; 2250 u32 tx_stat_dot3statsdeferredtransmissions; 2251 u32 tx_stat_dot3statsexcessivecollisions; 2252 u32 tx_stat_dot3statslatecollisions; 2253 u32 tx_stat_ifhcoutucastpkts; 2254 u32 tx_stat_ifhcoutmulticastpkts; 2255 u32 tx_stat_ifhcoutbroadcastpkts; 2256 u32 tx_stat_etherstatspkts64octets; 2257 u32 tx_stat_etherstatspkts65octetsto127octets; 2258 u32 tx_stat_etherstatspkts128octetsto255octets; 2259 u32 tx_stat_etherstatspkts256octetsto511octets; 2260 u32 tx_stat_etherstatspkts512octetsto1023octets; 2261 u32 tx_stat_etherstatspkts1024octetsto1522octets; 2262 u32 tx_stat_etherstatspktsover1522octets; 2263 u32 tx_stat_dot3statsinternalmactransmiterrors; 2264 }; 2265 2266 2267 struct bmac1_stats { 2268 u32 tx_stat_gtpkt_lo; 2269 u32 tx_stat_gtpkt_hi; 2270 u32 tx_stat_gtxpf_lo; 2271 u32 tx_stat_gtxpf_hi; 2272 u32 tx_stat_gtfcs_lo; 2273 u32 tx_stat_gtfcs_hi; 2274 u32 tx_stat_gtmca_lo; 2275 u32 tx_stat_gtmca_hi; 2276 u32 tx_stat_gtbca_lo; 2277 u32 tx_stat_gtbca_hi; 2278 u32 tx_stat_gtfrg_lo; 2279 u32 tx_stat_gtfrg_hi; 2280 u32 tx_stat_gtovr_lo; 2281 u32 tx_stat_gtovr_hi; 2282 u32 tx_stat_gt64_lo; 2283 u32 tx_stat_gt64_hi; 2284 u32 tx_stat_gt127_lo; 2285 u32 tx_stat_gt127_hi; 2286 u32 tx_stat_gt255_lo; 2287 u32 tx_stat_gt255_hi; 2288 u32 tx_stat_gt511_lo; 2289 u32 tx_stat_gt511_hi; 2290 u32 tx_stat_gt1023_lo; 2291 u32 tx_stat_gt1023_hi; 2292 u32 tx_stat_gt1518_lo; 2293 u32 tx_stat_gt1518_hi; 2294 u32 tx_stat_gt2047_lo; 2295 u32 tx_stat_gt2047_hi; 2296 u32 tx_stat_gt4095_lo; 2297 u32 tx_stat_gt4095_hi; 2298 u32 tx_stat_gt9216_lo; 2299 u32 tx_stat_gt9216_hi; 2300 u32 tx_stat_gt16383_lo; 2301 u32 tx_stat_gt16383_hi; 2302 u32 tx_stat_gtmax_lo; 2303 u32 tx_stat_gtmax_hi; 2304 u32 tx_stat_gtufl_lo; 2305 u32 tx_stat_gtufl_hi; 2306 u32 tx_stat_gterr_lo; 2307 u32 tx_stat_gterr_hi; 2308 u32 tx_stat_gtbyt_lo; 2309 u32 tx_stat_gtbyt_hi; 2310 2311 u32 rx_stat_gr64_lo; 2312 u32 rx_stat_gr64_hi; 2313 u32 rx_stat_gr127_lo; 2314 u32 rx_stat_gr127_hi; 2315 u32 rx_stat_gr255_lo; 2316 u32 rx_stat_gr255_hi; 2317 u32 rx_stat_gr511_lo; 2318 u32 rx_stat_gr511_hi; 2319 u32 rx_stat_gr1023_lo; 2320 u32 rx_stat_gr1023_hi; 2321 u32 rx_stat_gr1518_lo; 2322 u32 rx_stat_gr1518_hi; 2323 u32 rx_stat_gr2047_lo; 2324 u32 rx_stat_gr2047_hi; 2325 u32 rx_stat_gr4095_lo; 2326 u32 rx_stat_gr4095_hi; 2327 u32 rx_stat_gr9216_lo; 2328 u32 rx_stat_gr9216_hi; 2329 u32 rx_stat_gr16383_lo; 2330 u32 rx_stat_gr16383_hi; 2331 u32 rx_stat_grmax_lo; 2332 u32 rx_stat_grmax_hi; 2333 u32 rx_stat_grpkt_lo; 2334 u32 rx_stat_grpkt_hi; 2335 u32 rx_stat_grfcs_lo; 2336 u32 rx_stat_grfcs_hi; 2337 u32 rx_stat_grmca_lo; 2338 u32 rx_stat_grmca_hi; 2339 u32 rx_stat_grbca_lo; 2340 u32 rx_stat_grbca_hi; 2341 u32 rx_stat_grxcf_lo; 2342 u32 rx_stat_grxcf_hi; 2343 u32 rx_stat_grxpf_lo; 2344 u32 rx_stat_grxpf_hi; 2345 u32 rx_stat_grxuo_lo; 2346 u32 rx_stat_grxuo_hi; 2347 u32 rx_stat_grjbr_lo; 2348 u32 rx_stat_grjbr_hi; 2349 u32 rx_stat_grovr_lo; 2350 u32 rx_stat_grovr_hi; 2351 u32 rx_stat_grflr_lo; 2352 u32 rx_stat_grflr_hi; 2353 u32 rx_stat_grmeg_lo; 2354 u32 rx_stat_grmeg_hi; 2355 u32 rx_stat_grmeb_lo; 2356 u32 rx_stat_grmeb_hi; 2357 u32 rx_stat_grbyt_lo; 2358 u32 rx_stat_grbyt_hi; 2359 u32 rx_stat_grund_lo; 2360 u32 rx_stat_grund_hi; 2361 u32 rx_stat_grfrg_lo; 2362 u32 rx_stat_grfrg_hi; 2363 u32 rx_stat_grerb_lo; 2364 u32 rx_stat_grerb_hi; 2365 u32 rx_stat_grfre_lo; 2366 u32 rx_stat_grfre_hi; 2367 u32 rx_stat_gripj_lo; 2368 u32 rx_stat_gripj_hi; 2369 }; 2370 2371 struct bmac2_stats { 2372 u32 tx_stat_gtpk_lo; /* gtpok */ 2373 u32 tx_stat_gtpk_hi; /* gtpok */ 2374 u32 tx_stat_gtxpf_lo; /* gtpf */ 2375 u32 tx_stat_gtxpf_hi; /* gtpf */ 2376 u32 tx_stat_gtpp_lo; /* NEW BMAC2 */ 2377 u32 tx_stat_gtpp_hi; /* NEW BMAC2 */ 2378 u32 tx_stat_gtfcs_lo; 2379 u32 tx_stat_gtfcs_hi; 2380 u32 tx_stat_gtuca_lo; /* NEW BMAC2 */ 2381 u32 tx_stat_gtuca_hi; /* NEW BMAC2 */ 2382 u32 tx_stat_gtmca_lo; 2383 u32 tx_stat_gtmca_hi; 2384 u32 tx_stat_gtbca_lo; 2385 u32 tx_stat_gtbca_hi; 2386 u32 tx_stat_gtovr_lo; 2387 u32 tx_stat_gtovr_hi; 2388 u32 tx_stat_gtfrg_lo; 2389 u32 tx_stat_gtfrg_hi; 2390 u32 tx_stat_gtpkt1_lo; /* gtpkt */ 2391 u32 tx_stat_gtpkt1_hi; /* gtpkt */ 2392 u32 tx_stat_gt64_lo; 2393 u32 tx_stat_gt64_hi; 2394 u32 tx_stat_gt127_lo; 2395 u32 tx_stat_gt127_hi; 2396 u32 tx_stat_gt255_lo; 2397 u32 tx_stat_gt255_hi; 2398 u32 tx_stat_gt511_lo; 2399 u32 tx_stat_gt511_hi; 2400 u32 tx_stat_gt1023_lo; 2401 u32 tx_stat_gt1023_hi; 2402 u32 tx_stat_gt1518_lo; 2403 u32 tx_stat_gt1518_hi; 2404 u32 tx_stat_gt2047_lo; 2405 u32 tx_stat_gt2047_hi; 2406 u32 tx_stat_gt4095_lo; 2407 u32 tx_stat_gt4095_hi; 2408 u32 tx_stat_gt9216_lo; 2409 u32 tx_stat_gt9216_hi; 2410 u32 tx_stat_gt16383_lo; 2411 u32 tx_stat_gt16383_hi; 2412 u32 tx_stat_gtmax_lo; 2413 u32 tx_stat_gtmax_hi; 2414 u32 tx_stat_gtufl_lo; 2415 u32 tx_stat_gtufl_hi; 2416 u32 tx_stat_gterr_lo; 2417 u32 tx_stat_gterr_hi; 2418 u32 tx_stat_gtbyt_lo; 2419 u32 tx_stat_gtbyt_hi; 2420 2421 u32 rx_stat_gr64_lo; 2422 u32 rx_stat_gr64_hi; 2423 u32 rx_stat_gr127_lo; 2424 u32 rx_stat_gr127_hi; 2425 u32 rx_stat_gr255_lo; 2426 u32 rx_stat_gr255_hi; 2427 u32 rx_stat_gr511_lo; 2428 u32 rx_stat_gr511_hi; 2429 u32 rx_stat_gr1023_lo; 2430 u32 rx_stat_gr1023_hi; 2431 u32 rx_stat_gr1518_lo; 2432 u32 rx_stat_gr1518_hi; 2433 u32 rx_stat_gr2047_lo; 2434 u32 rx_stat_gr2047_hi; 2435 u32 rx_stat_gr4095_lo; 2436 u32 rx_stat_gr4095_hi; 2437 u32 rx_stat_gr9216_lo; 2438 u32 rx_stat_gr9216_hi; 2439 u32 rx_stat_gr16383_lo; 2440 u32 rx_stat_gr16383_hi; 2441 u32 rx_stat_grmax_lo; 2442 u32 rx_stat_grmax_hi; 2443 u32 rx_stat_grpkt_lo; 2444 u32 rx_stat_grpkt_hi; 2445 u32 rx_stat_grfcs_lo; 2446 u32 rx_stat_grfcs_hi; 2447 u32 rx_stat_gruca_lo; 2448 u32 rx_stat_gruca_hi; 2449 u32 rx_stat_grmca_lo; 2450 u32 rx_stat_grmca_hi; 2451 u32 rx_stat_grbca_lo; 2452 u32 rx_stat_grbca_hi; 2453 u32 rx_stat_grxpf_lo; /* grpf */ 2454 u32 rx_stat_grxpf_hi; /* grpf */ 2455 u32 rx_stat_grpp_lo; 2456 u32 rx_stat_grpp_hi; 2457 u32 rx_stat_grxuo_lo; /* gruo */ 2458 u32 rx_stat_grxuo_hi; /* gruo */ 2459 u32 rx_stat_grjbr_lo; 2460 u32 rx_stat_grjbr_hi; 2461 u32 rx_stat_grovr_lo; 2462 u32 rx_stat_grovr_hi; 2463 u32 rx_stat_grxcf_lo; /* grcf */ 2464 u32 rx_stat_grxcf_hi; /* grcf */ 2465 u32 rx_stat_grflr_lo; 2466 u32 rx_stat_grflr_hi; 2467 u32 rx_stat_grpok_lo; 2468 u32 rx_stat_grpok_hi; 2469 u32 rx_stat_grmeg_lo; 2470 u32 rx_stat_grmeg_hi; 2471 u32 rx_stat_grmeb_lo; 2472 u32 rx_stat_grmeb_hi; 2473 u32 rx_stat_grbyt_lo; 2474 u32 rx_stat_grbyt_hi; 2475 u32 rx_stat_grund_lo; 2476 u32 rx_stat_grund_hi; 2477 u32 rx_stat_grfrg_lo; 2478 u32 rx_stat_grfrg_hi; 2479 u32 rx_stat_grerb_lo; /* grerrbyt */ 2480 u32 rx_stat_grerb_hi; /* grerrbyt */ 2481 u32 rx_stat_grfre_lo; /* grfrerr */ 2482 u32 rx_stat_grfre_hi; /* grfrerr */ 2483 u32 rx_stat_gripj_lo; 2484 u32 rx_stat_gripj_hi; 2485 }; 2486 2487 struct mstat_stats { 2488 struct { 2489 /* OTE MSTAT on E3 has a bug where this register's contents are 2490 * actually tx_gtxpok + tx_gtxpf + (possibly)tx_gtxpp 2491 */ 2492 u32 tx_gtxpok_lo; 2493 u32 tx_gtxpok_hi; 2494 u32 tx_gtxpf_lo; 2495 u32 tx_gtxpf_hi; 2496 u32 tx_gtxpp_lo; 2497 u32 tx_gtxpp_hi; 2498 u32 tx_gtfcs_lo; 2499 u32 tx_gtfcs_hi; 2500 u32 tx_gtuca_lo; 2501 u32 tx_gtuca_hi; 2502 u32 tx_gtmca_lo; 2503 u32 tx_gtmca_hi; 2504 u32 tx_gtgca_lo; 2505 u32 tx_gtgca_hi; 2506 u32 tx_gtpkt_lo; 2507 u32 tx_gtpkt_hi; 2508 u32 tx_gt64_lo; 2509 u32 tx_gt64_hi; 2510 u32 tx_gt127_lo; 2511 u32 tx_gt127_hi; 2512 u32 tx_gt255_lo; 2513 u32 tx_gt255_hi; 2514 u32 tx_gt511_lo; 2515 u32 tx_gt511_hi; 2516 u32 tx_gt1023_lo; 2517 u32 tx_gt1023_hi; 2518 u32 tx_gt1518_lo; 2519 u32 tx_gt1518_hi; 2520 u32 tx_gt2047_lo; 2521 u32 tx_gt2047_hi; 2522 u32 tx_gt4095_lo; 2523 u32 tx_gt4095_hi; 2524 u32 tx_gt9216_lo; 2525 u32 tx_gt9216_hi; 2526 u32 tx_gt16383_lo; 2527 u32 tx_gt16383_hi; 2528 u32 tx_gtufl_lo; 2529 u32 tx_gtufl_hi; 2530 u32 tx_gterr_lo; 2531 u32 tx_gterr_hi; 2532 u32 tx_gtbyt_lo; 2533 u32 tx_gtbyt_hi; 2534 u32 tx_collisions_lo; 2535 u32 tx_collisions_hi; 2536 u32 tx_singlecollision_lo; 2537 u32 tx_singlecollision_hi; 2538 u32 tx_multiplecollisions_lo; 2539 u32 tx_multiplecollisions_hi; 2540 u32 tx_deferred_lo; 2541 u32 tx_deferred_hi; 2542 u32 tx_excessivecollisions_lo; 2543 u32 tx_excessivecollisions_hi; 2544 u32 tx_latecollisions_lo; 2545 u32 tx_latecollisions_hi; 2546 } stats_tx; 2547 2548 struct { 2549 u32 rx_gr64_lo; 2550 u32 rx_gr64_hi; 2551 u32 rx_gr127_lo; 2552 u32 rx_gr127_hi; 2553 u32 rx_gr255_lo; 2554 u32 rx_gr255_hi; 2555 u32 rx_gr511_lo; 2556 u32 rx_gr511_hi; 2557 u32 rx_gr1023_lo; 2558 u32 rx_gr1023_hi; 2559 u32 rx_gr1518_lo; 2560 u32 rx_gr1518_hi; 2561 u32 rx_gr2047_lo; 2562 u32 rx_gr2047_hi; 2563 u32 rx_gr4095_lo; 2564 u32 rx_gr4095_hi; 2565 u32 rx_gr9216_lo; 2566 u32 rx_gr9216_hi; 2567 u32 rx_gr16383_lo; 2568 u32 rx_gr16383_hi; 2569 u32 rx_grpkt_lo; 2570 u32 rx_grpkt_hi; 2571 u32 rx_grfcs_lo; 2572 u32 rx_grfcs_hi; 2573 u32 rx_gruca_lo; 2574 u32 rx_gruca_hi; 2575 u32 rx_grmca_lo; 2576 u32 rx_grmca_hi; 2577 u32 rx_grbca_lo; 2578 u32 rx_grbca_hi; 2579 u32 rx_grxpf_lo; 2580 u32 rx_grxpf_hi; 2581 u32 rx_grxpp_lo; 2582 u32 rx_grxpp_hi; 2583 u32 rx_grxuo_lo; 2584 u32 rx_grxuo_hi; 2585 u32 rx_grovr_lo; 2586 u32 rx_grovr_hi; 2587 u32 rx_grxcf_lo; 2588 u32 rx_grxcf_hi; 2589 u32 rx_grflr_lo; 2590 u32 rx_grflr_hi; 2591 u32 rx_grpok_lo; 2592 u32 rx_grpok_hi; 2593 u32 rx_grbyt_lo; 2594 u32 rx_grbyt_hi; 2595 u32 rx_grund_lo; 2596 u32 rx_grund_hi; 2597 u32 rx_grfrg_lo; 2598 u32 rx_grfrg_hi; 2599 u32 rx_grerb_lo; 2600 u32 rx_grerb_hi; 2601 u32 rx_grfre_lo; 2602 u32 rx_grfre_hi; 2603 2604 u32 rx_alignmenterrors_lo; 2605 u32 rx_alignmenterrors_hi; 2606 u32 rx_falsecarrier_lo; 2607 u32 rx_falsecarrier_hi; 2608 u32 rx_llfcmsgcnt_lo; 2609 u32 rx_llfcmsgcnt_hi; 2610 } stats_rx; 2611 }; 2612 2613 union mac_stats { 2614 struct emac_stats emac_stats; 2615 struct bmac1_stats bmac1_stats; 2616 struct bmac2_stats bmac2_stats; 2617 struct mstat_stats mstat_stats; 2618 }; 2619 2620 2621 struct mac_stx { 2622 /* in_bad_octets */ 2623 u32 rx_stat_ifhcinbadoctets_hi; 2624 u32 rx_stat_ifhcinbadoctets_lo; 2625 2626 /* out_bad_octets */ 2627 u32 tx_stat_ifhcoutbadoctets_hi; 2628 u32 tx_stat_ifhcoutbadoctets_lo; 2629 2630 /* crc_receive_errors */ 2631 u32 rx_stat_dot3statsfcserrors_hi; 2632 u32 rx_stat_dot3statsfcserrors_lo; 2633 /* alignment_errors */ 2634 u32 rx_stat_dot3statsalignmenterrors_hi; 2635 u32 rx_stat_dot3statsalignmenterrors_lo; 2636 /* carrier_sense_errors */ 2637 u32 rx_stat_dot3statscarriersenseerrors_hi; 2638 u32 rx_stat_dot3statscarriersenseerrors_lo; 2639 /* false_carrier_detections */ 2640 u32 rx_stat_falsecarriererrors_hi; 2641 u32 rx_stat_falsecarriererrors_lo; 2642 2643 /* runt_packets_received */ 2644 u32 rx_stat_etherstatsundersizepkts_hi; 2645 u32 rx_stat_etherstatsundersizepkts_lo; 2646 /* jabber_packets_received */ 2647 u32 rx_stat_dot3statsframestoolong_hi; 2648 u32 rx_stat_dot3statsframestoolong_lo; 2649 2650 /* error_runt_packets_received */ 2651 u32 rx_stat_etherstatsfragments_hi; 2652 u32 rx_stat_etherstatsfragments_lo; 2653 /* error_jabber_packets_received */ 2654 u32 rx_stat_etherstatsjabbers_hi; 2655 u32 rx_stat_etherstatsjabbers_lo; 2656 2657 /* control_frames_received */ 2658 u32 rx_stat_maccontrolframesreceived_hi; 2659 u32 rx_stat_maccontrolframesreceived_lo; 2660 u32 rx_stat_mac_xpf_hi; 2661 u32 rx_stat_mac_xpf_lo; 2662 u32 rx_stat_mac_xcf_hi; 2663 u32 rx_stat_mac_xcf_lo; 2664 2665 /* xoff_state_entered */ 2666 u32 rx_stat_xoffstateentered_hi; 2667 u32 rx_stat_xoffstateentered_lo; 2668 /* pause_xon_frames_received */ 2669 u32 rx_stat_xonpauseframesreceived_hi; 2670 u32 rx_stat_xonpauseframesreceived_lo; 2671 /* pause_xoff_frames_received */ 2672 u32 rx_stat_xoffpauseframesreceived_hi; 2673 u32 rx_stat_xoffpauseframesreceived_lo; 2674 /* pause_xon_frames_transmitted */ 2675 u32 tx_stat_outxonsent_hi; 2676 u32 tx_stat_outxonsent_lo; 2677 /* pause_xoff_frames_transmitted */ 2678 u32 tx_stat_outxoffsent_hi; 2679 u32 tx_stat_outxoffsent_lo; 2680 /* flow_control_done */ 2681 u32 tx_stat_flowcontroldone_hi; 2682 u32 tx_stat_flowcontroldone_lo; 2683 2684 /* ether_stats_collisions */ 2685 u32 tx_stat_etherstatscollisions_hi; 2686 u32 tx_stat_etherstatscollisions_lo; 2687 /* single_collision_transmit_frames */ 2688 u32 tx_stat_dot3statssinglecollisionframes_hi; 2689 u32 tx_stat_dot3statssinglecollisionframes_lo; 2690 /* multiple_collision_transmit_frames */ 2691 u32 tx_stat_dot3statsmultiplecollisionframes_hi; 2692 u32 tx_stat_dot3statsmultiplecollisionframes_lo; 2693 /* deferred_transmissions */ 2694 u32 tx_stat_dot3statsdeferredtransmissions_hi; 2695 u32 tx_stat_dot3statsdeferredtransmissions_lo; 2696 /* excessive_collision_frames */ 2697 u32 tx_stat_dot3statsexcessivecollisions_hi; 2698 u32 tx_stat_dot3statsexcessivecollisions_lo; 2699 /* late_collision_frames */ 2700 u32 tx_stat_dot3statslatecollisions_hi; 2701 u32 tx_stat_dot3statslatecollisions_lo; 2702 2703 /* frames_transmitted_64_bytes */ 2704 u32 tx_stat_etherstatspkts64octets_hi; 2705 u32 tx_stat_etherstatspkts64octets_lo; 2706 /* frames_transmitted_65_127_bytes */ 2707 u32 tx_stat_etherstatspkts65octetsto127octets_hi; 2708 u32 tx_stat_etherstatspkts65octetsto127octets_lo; 2709 /* frames_transmitted_128_255_bytes */ 2710 u32 tx_stat_etherstatspkts128octetsto255octets_hi; 2711 u32 tx_stat_etherstatspkts128octetsto255octets_lo; 2712 /* frames_transmitted_256_511_bytes */ 2713 u32 tx_stat_etherstatspkts256octetsto511octets_hi; 2714 u32 tx_stat_etherstatspkts256octetsto511octets_lo; 2715 /* frames_transmitted_512_1023_bytes */ 2716 u32 tx_stat_etherstatspkts512octetsto1023octets_hi; 2717 u32 tx_stat_etherstatspkts512octetsto1023octets_lo; 2718 /* frames_transmitted_1024_1522_bytes */ 2719 u32 tx_stat_etherstatspkts1024octetsto1522octets_hi; 2720 u32 tx_stat_etherstatspkts1024octetsto1522octets_lo; 2721 /* frames_transmitted_1523_9022_bytes */ 2722 u32 tx_stat_etherstatspktsover1522octets_hi; 2723 u32 tx_stat_etherstatspktsover1522octets_lo; 2724 u32 tx_stat_mac_2047_hi; 2725 u32 tx_stat_mac_2047_lo; 2726 u32 tx_stat_mac_4095_hi; 2727 u32 tx_stat_mac_4095_lo; 2728 u32 tx_stat_mac_9216_hi; 2729 u32 tx_stat_mac_9216_lo; 2730 u32 tx_stat_mac_16383_hi; 2731 u32 tx_stat_mac_16383_lo; 2732 2733 /* internal_mac_transmit_errors */ 2734 u32 tx_stat_dot3statsinternalmactransmiterrors_hi; 2735 u32 tx_stat_dot3statsinternalmactransmiterrors_lo; 2736 2737 /* if_out_discards */ 2738 u32 tx_stat_mac_ufl_hi; 2739 u32 tx_stat_mac_ufl_lo; 2740 }; 2741 2742 2743 #define MAC_STX_IDX_MAX 2 2744 2745 struct host_port_stats { 2746 u32 host_port_stats_counter; 2747 2748 struct mac_stx mac_stx[MAC_STX_IDX_MAX]; 2749 2750 u32 brb_drop_hi; 2751 u32 brb_drop_lo; 2752 2753 u32 not_used; /* obsolete */ 2754 u32 pfc_frames_tx_hi; 2755 u32 pfc_frames_tx_lo; 2756 u32 pfc_frames_rx_hi; 2757 u32 pfc_frames_rx_lo; 2758 2759 u32 eee_lpi_count_hi; 2760 u32 eee_lpi_count_lo; 2761 }; 2762 2763 2764 struct host_func_stats { 2765 u32 host_func_stats_start; 2766 2767 u32 total_bytes_received_hi; 2768 u32 total_bytes_received_lo; 2769 2770 u32 total_bytes_transmitted_hi; 2771 u32 total_bytes_transmitted_lo; 2772 2773 u32 total_unicast_packets_received_hi; 2774 u32 total_unicast_packets_received_lo; 2775 2776 u32 total_multicast_packets_received_hi; 2777 u32 total_multicast_packets_received_lo; 2778 2779 u32 total_broadcast_packets_received_hi; 2780 u32 total_broadcast_packets_received_lo; 2781 2782 u32 total_unicast_packets_transmitted_hi; 2783 u32 total_unicast_packets_transmitted_lo; 2784 2785 u32 total_multicast_packets_transmitted_hi; 2786 u32 total_multicast_packets_transmitted_lo; 2787 2788 u32 total_broadcast_packets_transmitted_hi; 2789 u32 total_broadcast_packets_transmitted_lo; 2790 2791 u32 valid_bytes_received_hi; 2792 u32 valid_bytes_received_lo; 2793 2794 u32 host_func_stats_end; 2795 }; 2796 2797 /* VIC definitions */ 2798 #define VICSTATST_UIF_INDEX 2 2799 2800 2801 /* stats collected for afex. 2802 * NOTE: structure is exactly as expected to be received by the switch. 2803 * order must remain exactly as is unless protocol changes ! 2804 */ 2805 struct afex_stats { 2806 u32 tx_unicast_frames_hi; 2807 u32 tx_unicast_frames_lo; 2808 u32 tx_unicast_bytes_hi; 2809 u32 tx_unicast_bytes_lo; 2810 u32 tx_multicast_frames_hi; 2811 u32 tx_multicast_frames_lo; 2812 u32 tx_multicast_bytes_hi; 2813 u32 tx_multicast_bytes_lo; 2814 u32 tx_broadcast_frames_hi; 2815 u32 tx_broadcast_frames_lo; 2816 u32 tx_broadcast_bytes_hi; 2817 u32 tx_broadcast_bytes_lo; 2818 u32 tx_frames_discarded_hi; 2819 u32 tx_frames_discarded_lo; 2820 u32 tx_frames_dropped_hi; 2821 u32 tx_frames_dropped_lo; 2822 2823 u32 rx_unicast_frames_hi; 2824 u32 rx_unicast_frames_lo; 2825 u32 rx_unicast_bytes_hi; 2826 u32 rx_unicast_bytes_lo; 2827 u32 rx_multicast_frames_hi; 2828 u32 rx_multicast_frames_lo; 2829 u32 rx_multicast_bytes_hi; 2830 u32 rx_multicast_bytes_lo; 2831 u32 rx_broadcast_frames_hi; 2832 u32 rx_broadcast_frames_lo; 2833 u32 rx_broadcast_bytes_hi; 2834 u32 rx_broadcast_bytes_lo; 2835 u32 rx_frames_discarded_hi; 2836 u32 rx_frames_discarded_lo; 2837 u32 rx_frames_dropped_hi; 2838 u32 rx_frames_dropped_lo; 2839 }; 2840 2841 #define BCM_5710_FW_MAJOR_VERSION 7 2842 #define BCM_5710_FW_MINOR_VERSION 8 2843 #define BCM_5710_FW_REVISION_VERSION 17 2844 #define BCM_5710_FW_ENGINEERING_VERSION 0 2845 #define BCM_5710_FW_COMPILE_FLAGS 1 2846 2847 2848 /* 2849 * attention bits 2850 */ 2851 struct atten_sp_status_block { 2852 __le32 attn_bits; 2853 __le32 attn_bits_ack; 2854 u8 status_block_id; 2855 u8 reserved0; 2856 __le16 attn_bits_index; 2857 __le32 reserved1; 2858 }; 2859 2860 2861 /* 2862 * The eth aggregative context of Cstorm 2863 */ 2864 struct cstorm_eth_ag_context { 2865 u32 __reserved0[10]; 2866 }; 2867 2868 2869 /* 2870 * dmae command structure 2871 */ 2872 struct dmae_command { 2873 u32 opcode; 2874 #define DMAE_COMMAND_SRC (0x1<<0) 2875 #define DMAE_COMMAND_SRC_SHIFT 0 2876 #define DMAE_COMMAND_DST (0x3<<1) 2877 #define DMAE_COMMAND_DST_SHIFT 1 2878 #define DMAE_COMMAND_C_DST (0x1<<3) 2879 #define DMAE_COMMAND_C_DST_SHIFT 3 2880 #define DMAE_COMMAND_C_TYPE_ENABLE (0x1<<4) 2881 #define DMAE_COMMAND_C_TYPE_ENABLE_SHIFT 4 2882 #define DMAE_COMMAND_C_TYPE_CRC_ENABLE (0x1<<5) 2883 #define DMAE_COMMAND_C_TYPE_CRC_ENABLE_SHIFT 5 2884 #define DMAE_COMMAND_C_TYPE_CRC_OFFSET (0x7<<6) 2885 #define DMAE_COMMAND_C_TYPE_CRC_OFFSET_SHIFT 6 2886 #define DMAE_COMMAND_ENDIANITY (0x3<<9) 2887 #define DMAE_COMMAND_ENDIANITY_SHIFT 9 2888 #define DMAE_COMMAND_PORT (0x1<<11) 2889 #define DMAE_COMMAND_PORT_SHIFT 11 2890 #define DMAE_COMMAND_CRC_RESET (0x1<<12) 2891 #define DMAE_COMMAND_CRC_RESET_SHIFT 12 2892 #define DMAE_COMMAND_SRC_RESET (0x1<<13) 2893 #define DMAE_COMMAND_SRC_RESET_SHIFT 13 2894 #define DMAE_COMMAND_DST_RESET (0x1<<14) 2895 #define DMAE_COMMAND_DST_RESET_SHIFT 14 2896 #define DMAE_COMMAND_E1HVN (0x3<<15) 2897 #define DMAE_COMMAND_E1HVN_SHIFT 15 2898 #define DMAE_COMMAND_DST_VN (0x3<<17) 2899 #define DMAE_COMMAND_DST_VN_SHIFT 17 2900 #define DMAE_COMMAND_C_FUNC (0x1<<19) 2901 #define DMAE_COMMAND_C_FUNC_SHIFT 19 2902 #define DMAE_COMMAND_ERR_POLICY (0x3<<20) 2903 #define DMAE_COMMAND_ERR_POLICY_SHIFT 20 2904 #define DMAE_COMMAND_RESERVED0 (0x3FF<<22) 2905 #define DMAE_COMMAND_RESERVED0_SHIFT 22 2906 u32 src_addr_lo; 2907 u32 src_addr_hi; 2908 u32 dst_addr_lo; 2909 u32 dst_addr_hi; 2910 #if defined(__BIG_ENDIAN) 2911 u16 opcode_iov; 2912 #define DMAE_COMMAND_SRC_VFID (0x3F<<0) 2913 #define DMAE_COMMAND_SRC_VFID_SHIFT 0 2914 #define DMAE_COMMAND_SRC_VFPF (0x1<<6) 2915 #define DMAE_COMMAND_SRC_VFPF_SHIFT 6 2916 #define DMAE_COMMAND_RESERVED1 (0x1<<7) 2917 #define DMAE_COMMAND_RESERVED1_SHIFT 7 2918 #define DMAE_COMMAND_DST_VFID (0x3F<<8) 2919 #define DMAE_COMMAND_DST_VFID_SHIFT 8 2920 #define DMAE_COMMAND_DST_VFPF (0x1<<14) 2921 #define DMAE_COMMAND_DST_VFPF_SHIFT 14 2922 #define DMAE_COMMAND_RESERVED2 (0x1<<15) 2923 #define DMAE_COMMAND_RESERVED2_SHIFT 15 2924 u16 len; 2925 #elif defined(__LITTLE_ENDIAN) 2926 u16 len; 2927 u16 opcode_iov; 2928 #define DMAE_COMMAND_SRC_VFID (0x3F<<0) 2929 #define DMAE_COMMAND_SRC_VFID_SHIFT 0 2930 #define DMAE_COMMAND_SRC_VFPF (0x1<<6) 2931 #define DMAE_COMMAND_SRC_VFPF_SHIFT 6 2932 #define DMAE_COMMAND_RESERVED1 (0x1<<7) 2933 #define DMAE_COMMAND_RESERVED1_SHIFT 7 2934 #define DMAE_COMMAND_DST_VFID (0x3F<<8) 2935 #define DMAE_COMMAND_DST_VFID_SHIFT 8 2936 #define DMAE_COMMAND_DST_VFPF (0x1<<14) 2937 #define DMAE_COMMAND_DST_VFPF_SHIFT 14 2938 #define DMAE_COMMAND_RESERVED2 (0x1<<15) 2939 #define DMAE_COMMAND_RESERVED2_SHIFT 15 2940 #endif 2941 u32 comp_addr_lo; 2942 u32 comp_addr_hi; 2943 u32 comp_val; 2944 u32 crc32; 2945 u32 crc32_c; 2946 #if defined(__BIG_ENDIAN) 2947 u16 crc16_c; 2948 u16 crc16; 2949 #elif defined(__LITTLE_ENDIAN) 2950 u16 crc16; 2951 u16 crc16_c; 2952 #endif 2953 #if defined(__BIG_ENDIAN) 2954 u16 reserved3; 2955 u16 crc_t10; 2956 #elif defined(__LITTLE_ENDIAN) 2957 u16 crc_t10; 2958 u16 reserved3; 2959 #endif 2960 #if defined(__BIG_ENDIAN) 2961 u16 xsum8; 2962 u16 xsum16; 2963 #elif defined(__LITTLE_ENDIAN) 2964 u16 xsum16; 2965 u16 xsum8; 2966 #endif 2967 }; 2968 2969 2970 /* 2971 * common data for all protocols 2972 */ 2973 struct doorbell_hdr { 2974 u8 header; 2975 #define DOORBELL_HDR_RX (0x1<<0) 2976 #define DOORBELL_HDR_RX_SHIFT 0 2977 #define DOORBELL_HDR_DB_TYPE (0x1<<1) 2978 #define DOORBELL_HDR_DB_TYPE_SHIFT 1 2979 #define DOORBELL_HDR_DPM_SIZE (0x3<<2) 2980 #define DOORBELL_HDR_DPM_SIZE_SHIFT 2 2981 #define DOORBELL_HDR_CONN_TYPE (0xF<<4) 2982 #define DOORBELL_HDR_CONN_TYPE_SHIFT 4 2983 }; 2984 2985 /* 2986 * Ethernet doorbell 2987 */ 2988 struct eth_tx_doorbell { 2989 #if defined(__BIG_ENDIAN) 2990 u16 npackets; 2991 u8 params; 2992 #define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0) 2993 #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0 2994 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6) 2995 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6 2996 #define ETH_TX_DOORBELL_SPARE (0x1<<7) 2997 #define ETH_TX_DOORBELL_SPARE_SHIFT 7 2998 struct doorbell_hdr hdr; 2999 #elif defined(__LITTLE_ENDIAN) 3000 struct doorbell_hdr hdr; 3001 u8 params; 3002 #define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0) 3003 #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0 3004 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6) 3005 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6 3006 #define ETH_TX_DOORBELL_SPARE (0x1<<7) 3007 #define ETH_TX_DOORBELL_SPARE_SHIFT 7 3008 u16 npackets; 3009 #endif 3010 }; 3011 3012 3013 /* 3014 * 3 lines. status block 3015 */ 3016 struct hc_status_block_e1x { 3017 __le16 index_values[HC_SB_MAX_INDICES_E1X]; 3018 __le16 running_index[HC_SB_MAX_SM]; 3019 __le32 rsrv[11]; 3020 }; 3021 3022 /* 3023 * host status block 3024 */ 3025 struct host_hc_status_block_e1x { 3026 struct hc_status_block_e1x sb; 3027 }; 3028 3029 3030 /* 3031 * 3 lines. status block 3032 */ 3033 struct hc_status_block_e2 { 3034 __le16 index_values[HC_SB_MAX_INDICES_E2]; 3035 __le16 running_index[HC_SB_MAX_SM]; 3036 __le32 reserved[11]; 3037 }; 3038 3039 /* 3040 * host status block 3041 */ 3042 struct host_hc_status_block_e2 { 3043 struct hc_status_block_e2 sb; 3044 }; 3045 3046 3047 /* 3048 * 5 lines. slow-path status block 3049 */ 3050 struct hc_sp_status_block { 3051 __le16 index_values[HC_SP_SB_MAX_INDICES]; 3052 __le16 running_index; 3053 __le16 rsrv; 3054 u32 rsrv1; 3055 }; 3056 3057 /* 3058 * host status block 3059 */ 3060 struct host_sp_status_block { 3061 struct atten_sp_status_block atten_status_block; 3062 struct hc_sp_status_block sp_sb; 3063 }; 3064 3065 3066 /* 3067 * IGU driver acknowledgment register 3068 */ 3069 struct igu_ack_register { 3070 #if defined(__BIG_ENDIAN) 3071 u16 sb_id_and_flags; 3072 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0) 3073 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0 3074 #define IGU_ACK_REGISTER_STORM_ID (0x7<<5) 3075 #define IGU_ACK_REGISTER_STORM_ID_SHIFT 5 3076 #define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8) 3077 #define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8 3078 #define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9) 3079 #define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9 3080 #define IGU_ACK_REGISTER_RESERVED (0x1F<<11) 3081 #define IGU_ACK_REGISTER_RESERVED_SHIFT 11 3082 u16 status_block_index; 3083 #elif defined(__LITTLE_ENDIAN) 3084 u16 status_block_index; 3085 u16 sb_id_and_flags; 3086 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0) 3087 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0 3088 #define IGU_ACK_REGISTER_STORM_ID (0x7<<5) 3089 #define IGU_ACK_REGISTER_STORM_ID_SHIFT 5 3090 #define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8) 3091 #define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8 3092 #define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9) 3093 #define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9 3094 #define IGU_ACK_REGISTER_RESERVED (0x1F<<11) 3095 #define IGU_ACK_REGISTER_RESERVED_SHIFT 11 3096 #endif 3097 }; 3098 3099 3100 /* 3101 * IGU driver acknowledgement register 3102 */ 3103 struct igu_backward_compatible { 3104 u32 sb_id_and_flags; 3105 #define IGU_BACKWARD_COMPATIBLE_SB_INDEX (0xFFFF<<0) 3106 #define IGU_BACKWARD_COMPATIBLE_SB_INDEX_SHIFT 0 3107 #define IGU_BACKWARD_COMPATIBLE_SB_SELECT (0x1F<<16) 3108 #define IGU_BACKWARD_COMPATIBLE_SB_SELECT_SHIFT 16 3109 #define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS (0x7<<21) 3110 #define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS_SHIFT 21 3111 #define IGU_BACKWARD_COMPATIBLE_BUPDATE (0x1<<24) 3112 #define IGU_BACKWARD_COMPATIBLE_BUPDATE_SHIFT 24 3113 #define IGU_BACKWARD_COMPATIBLE_ENABLE_INT (0x3<<25) 3114 #define IGU_BACKWARD_COMPATIBLE_ENABLE_INT_SHIFT 25 3115 #define IGU_BACKWARD_COMPATIBLE_RESERVED_0 (0x1F<<27) 3116 #define IGU_BACKWARD_COMPATIBLE_RESERVED_0_SHIFT 27 3117 u32 reserved_2; 3118 }; 3119 3120 3121 /* 3122 * IGU driver acknowledgement register 3123 */ 3124 struct igu_regular { 3125 u32 sb_id_and_flags; 3126 #define IGU_REGULAR_SB_INDEX (0xFFFFF<<0) 3127 #define IGU_REGULAR_SB_INDEX_SHIFT 0 3128 #define IGU_REGULAR_RESERVED0 (0x1<<20) 3129 #define IGU_REGULAR_RESERVED0_SHIFT 20 3130 #define IGU_REGULAR_SEGMENT_ACCESS (0x7<<21) 3131 #define IGU_REGULAR_SEGMENT_ACCESS_SHIFT 21 3132 #define IGU_REGULAR_BUPDATE (0x1<<24) 3133 #define IGU_REGULAR_BUPDATE_SHIFT 24 3134 #define IGU_REGULAR_ENABLE_INT (0x3<<25) 3135 #define IGU_REGULAR_ENABLE_INT_SHIFT 25 3136 #define IGU_REGULAR_RESERVED_1 (0x1<<27) 3137 #define IGU_REGULAR_RESERVED_1_SHIFT 27 3138 #define IGU_REGULAR_CLEANUP_TYPE (0x3<<28) 3139 #define IGU_REGULAR_CLEANUP_TYPE_SHIFT 28 3140 #define IGU_REGULAR_CLEANUP_SET (0x1<<30) 3141 #define IGU_REGULAR_CLEANUP_SET_SHIFT 30 3142 #define IGU_REGULAR_BCLEANUP (0x1<<31) 3143 #define IGU_REGULAR_BCLEANUP_SHIFT 31 3144 u32 reserved_2; 3145 }; 3146 3147 /* 3148 * IGU driver acknowledgement register 3149 */ 3150 union igu_consprod_reg { 3151 struct igu_regular regular; 3152 struct igu_backward_compatible backward_compatible; 3153 }; 3154 3155 3156 /* 3157 * Igu control commands 3158 */ 3159 enum igu_ctrl_cmd { 3160 IGU_CTRL_CMD_TYPE_RD, 3161 IGU_CTRL_CMD_TYPE_WR, 3162 MAX_IGU_CTRL_CMD 3163 }; 3164 3165 3166 /* 3167 * Control register for the IGU command register 3168 */ 3169 struct igu_ctrl_reg { 3170 u32 ctrl_data; 3171 #define IGU_CTRL_REG_ADDRESS (0xFFF<<0) 3172 #define IGU_CTRL_REG_ADDRESS_SHIFT 0 3173 #define IGU_CTRL_REG_FID (0x7F<<12) 3174 #define IGU_CTRL_REG_FID_SHIFT 12 3175 #define IGU_CTRL_REG_RESERVED (0x1<<19) 3176 #define IGU_CTRL_REG_RESERVED_SHIFT 19 3177 #define IGU_CTRL_REG_TYPE (0x1<<20) 3178 #define IGU_CTRL_REG_TYPE_SHIFT 20 3179 #define IGU_CTRL_REG_UNUSED (0x7FF<<21) 3180 #define IGU_CTRL_REG_UNUSED_SHIFT 21 3181 }; 3182 3183 3184 /* 3185 * Igu interrupt command 3186 */ 3187 enum igu_int_cmd { 3188 IGU_INT_ENABLE, 3189 IGU_INT_DISABLE, 3190 IGU_INT_NOP, 3191 IGU_INT_NOP2, 3192 MAX_IGU_INT_CMD 3193 }; 3194 3195 3196 /* 3197 * Igu segments 3198 */ 3199 enum igu_seg_access { 3200 IGU_SEG_ACCESS_NORM, 3201 IGU_SEG_ACCESS_DEF, 3202 IGU_SEG_ACCESS_ATTN, 3203 MAX_IGU_SEG_ACCESS 3204 }; 3205 3206 3207 /* 3208 * Parser parsing flags field 3209 */ 3210 struct parsing_flags { 3211 __le16 flags; 3212 #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE (0x1<<0) 3213 #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE_SHIFT 0 3214 #define PARSING_FLAGS_VLAN (0x1<<1) 3215 #define PARSING_FLAGS_VLAN_SHIFT 1 3216 #define PARSING_FLAGS_EXTRA_VLAN (0x1<<2) 3217 #define PARSING_FLAGS_EXTRA_VLAN_SHIFT 2 3218 #define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL (0x3<<3) 3219 #define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT 3 3220 #define PARSING_FLAGS_IP_OPTIONS (0x1<<5) 3221 #define PARSING_FLAGS_IP_OPTIONS_SHIFT 5 3222 #define PARSING_FLAGS_FRAGMENTATION_STATUS (0x1<<6) 3223 #define PARSING_FLAGS_FRAGMENTATION_STATUS_SHIFT 6 3224 #define PARSING_FLAGS_OVER_IP_PROTOCOL (0x3<<7) 3225 #define PARSING_FLAGS_OVER_IP_PROTOCOL_SHIFT 7 3226 #define PARSING_FLAGS_PURE_ACK_INDICATION (0x1<<9) 3227 #define PARSING_FLAGS_PURE_ACK_INDICATION_SHIFT 9 3228 #define PARSING_FLAGS_TCP_OPTIONS_EXIST (0x1<<10) 3229 #define PARSING_FLAGS_TCP_OPTIONS_EXIST_SHIFT 10 3230 #define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG (0x1<<11) 3231 #define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG_SHIFT 11 3232 #define PARSING_FLAGS_CONNECTION_MATCH (0x1<<12) 3233 #define PARSING_FLAGS_CONNECTION_MATCH_SHIFT 12 3234 #define PARSING_FLAGS_LLC_SNAP (0x1<<13) 3235 #define PARSING_FLAGS_LLC_SNAP_SHIFT 13 3236 #define PARSING_FLAGS_RESERVED0 (0x3<<14) 3237 #define PARSING_FLAGS_RESERVED0_SHIFT 14 3238 }; 3239 3240 3241 /* 3242 * Parsing flags for TCP ACK type 3243 */ 3244 enum prs_flags_ack_type { 3245 PRS_FLAG_PUREACK_PIGGY, 3246 PRS_FLAG_PUREACK_PURE, 3247 MAX_PRS_FLAGS_ACK_TYPE 3248 }; 3249 3250 3251 /* 3252 * Parsing flags for Ethernet address type 3253 */ 3254 enum prs_flags_eth_addr_type { 3255 PRS_FLAG_ETHTYPE_NON_UNICAST, 3256 PRS_FLAG_ETHTYPE_UNICAST, 3257 MAX_PRS_FLAGS_ETH_ADDR_TYPE 3258 }; 3259 3260 3261 /* 3262 * Parsing flags for over-ethernet protocol 3263 */ 3264 enum prs_flags_over_eth { 3265 PRS_FLAG_OVERETH_UNKNOWN, 3266 PRS_FLAG_OVERETH_IPV4, 3267 PRS_FLAG_OVERETH_IPV6, 3268 PRS_FLAG_OVERETH_LLCSNAP_UNKNOWN, 3269 MAX_PRS_FLAGS_OVER_ETH 3270 }; 3271 3272 3273 /* 3274 * Parsing flags for over-IP protocol 3275 */ 3276 enum prs_flags_over_ip { 3277 PRS_FLAG_OVERIP_UNKNOWN, 3278 PRS_FLAG_OVERIP_TCP, 3279 PRS_FLAG_OVERIP_UDP, 3280 MAX_PRS_FLAGS_OVER_IP 3281 }; 3282 3283 3284 /* 3285 * SDM operation gen command (generate aggregative interrupt) 3286 */ 3287 struct sdm_op_gen { 3288 __le32 command; 3289 #define SDM_OP_GEN_COMP_PARAM (0x1F<<0) 3290 #define SDM_OP_GEN_COMP_PARAM_SHIFT 0 3291 #define SDM_OP_GEN_COMP_TYPE (0x7<<5) 3292 #define SDM_OP_GEN_COMP_TYPE_SHIFT 5 3293 #define SDM_OP_GEN_AGG_VECT_IDX (0xFF<<8) 3294 #define SDM_OP_GEN_AGG_VECT_IDX_SHIFT 8 3295 #define SDM_OP_GEN_AGG_VECT_IDX_VALID (0x1<<16) 3296 #define SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT 16 3297 #define SDM_OP_GEN_RESERVED (0x7FFF<<17) 3298 #define SDM_OP_GEN_RESERVED_SHIFT 17 3299 }; 3300 3301 3302 /* 3303 * Timers connection context 3304 */ 3305 struct timers_block_context { 3306 u32 __reserved_0; 3307 u32 __reserved_1; 3308 u32 __reserved_2; 3309 u32 flags; 3310 #define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS (0x3<<0) 3311 #define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS_SHIFT 0 3312 #define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG (0x1<<2) 3313 #define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG_SHIFT 2 3314 #define __TIMERS_BLOCK_CONTEXT_RESERVED0 (0x1FFFFFFF<<3) 3315 #define __TIMERS_BLOCK_CONTEXT_RESERVED0_SHIFT 3 3316 }; 3317 3318 3319 /* 3320 * The eth aggregative context of Tstorm 3321 */ 3322 struct tstorm_eth_ag_context { 3323 u32 __reserved0[14]; 3324 }; 3325 3326 3327 /* 3328 * The eth aggregative context of Ustorm 3329 */ 3330 struct ustorm_eth_ag_context { 3331 u32 __reserved0; 3332 #if defined(__BIG_ENDIAN) 3333 u8 cdu_usage; 3334 u8 __reserved2; 3335 u16 __reserved1; 3336 #elif defined(__LITTLE_ENDIAN) 3337 u16 __reserved1; 3338 u8 __reserved2; 3339 u8 cdu_usage; 3340 #endif 3341 u32 __reserved3[6]; 3342 }; 3343 3344 3345 /* 3346 * The eth aggregative context of Xstorm 3347 */ 3348 struct xstorm_eth_ag_context { 3349 u32 reserved0; 3350 #if defined(__BIG_ENDIAN) 3351 u8 cdu_reserved; 3352 u8 reserved2; 3353 u16 reserved1; 3354 #elif defined(__LITTLE_ENDIAN) 3355 u16 reserved1; 3356 u8 reserved2; 3357 u8 cdu_reserved; 3358 #endif 3359 u32 reserved3[30]; 3360 }; 3361 3362 3363 /* 3364 * doorbell message sent to the chip 3365 */ 3366 struct doorbell { 3367 #if defined(__BIG_ENDIAN) 3368 u16 zero_fill2; 3369 u8 zero_fill1; 3370 struct doorbell_hdr header; 3371 #elif defined(__LITTLE_ENDIAN) 3372 struct doorbell_hdr header; 3373 u8 zero_fill1; 3374 u16 zero_fill2; 3375 #endif 3376 }; 3377 3378 3379 /* 3380 * doorbell message sent to the chip 3381 */ 3382 struct doorbell_set_prod { 3383 #if defined(__BIG_ENDIAN) 3384 u16 prod; 3385 u8 zero_fill1; 3386 struct doorbell_hdr header; 3387 #elif defined(__LITTLE_ENDIAN) 3388 struct doorbell_hdr header; 3389 u8 zero_fill1; 3390 u16 prod; 3391 #endif 3392 }; 3393 3394 3395 struct regpair { 3396 __le32 lo; 3397 __le32 hi; 3398 }; 3399 3400 struct regpair_native { 3401 u32 lo; 3402 u32 hi; 3403 }; 3404 3405 /* 3406 * Classify rule opcodes in E2/E3 3407 */ 3408 enum classify_rule { 3409 CLASSIFY_RULE_OPCODE_MAC, 3410 CLASSIFY_RULE_OPCODE_VLAN, 3411 CLASSIFY_RULE_OPCODE_PAIR, 3412 MAX_CLASSIFY_RULE 3413 }; 3414 3415 3416 /* 3417 * Classify rule types in E2/E3 3418 */ 3419 enum classify_rule_action_type { 3420 CLASSIFY_RULE_REMOVE, 3421 CLASSIFY_RULE_ADD, 3422 MAX_CLASSIFY_RULE_ACTION_TYPE 3423 }; 3424 3425 3426 /* 3427 * client init ramrod data 3428 */ 3429 struct client_init_general_data { 3430 u8 client_id; 3431 u8 statistics_counter_id; 3432 u8 statistics_en_flg; 3433 u8 is_fcoe_flg; 3434 u8 activate_flg; 3435 u8 sp_client_id; 3436 __le16 mtu; 3437 u8 statistics_zero_flg; 3438 u8 func_id; 3439 u8 cos; 3440 u8 traffic_type; 3441 u32 reserved0; 3442 }; 3443 3444 3445 /* 3446 * client init rx data 3447 */ 3448 struct client_init_rx_data { 3449 u8 tpa_en; 3450 #define CLIENT_INIT_RX_DATA_TPA_EN_IPV4 (0x1<<0) 3451 #define CLIENT_INIT_RX_DATA_TPA_EN_IPV4_SHIFT 0 3452 #define CLIENT_INIT_RX_DATA_TPA_EN_IPV6 (0x1<<1) 3453 #define CLIENT_INIT_RX_DATA_TPA_EN_IPV6_SHIFT 1 3454 #define CLIENT_INIT_RX_DATA_TPA_MODE (0x1<<2) 3455 #define CLIENT_INIT_RX_DATA_TPA_MODE_SHIFT 2 3456 #define CLIENT_INIT_RX_DATA_RESERVED5 (0x1F<<3) 3457 #define CLIENT_INIT_RX_DATA_RESERVED5_SHIFT 3 3458 u8 vmqueue_mode_en_flg; 3459 u8 extra_data_over_sgl_en_flg; 3460 u8 cache_line_alignment_log_size; 3461 u8 enable_dynamic_hc; 3462 u8 max_sges_for_packet; 3463 u8 client_qzone_id; 3464 u8 drop_ip_cs_err_flg; 3465 u8 drop_tcp_cs_err_flg; 3466 u8 drop_ttl0_flg; 3467 u8 drop_udp_cs_err_flg; 3468 u8 inner_vlan_removal_enable_flg; 3469 u8 outer_vlan_removal_enable_flg; 3470 u8 status_block_id; 3471 u8 rx_sb_index_number; 3472 u8 dont_verify_rings_pause_thr_flg; 3473 u8 max_tpa_queues; 3474 u8 silent_vlan_removal_flg; 3475 __le16 max_bytes_on_bd; 3476 __le16 sge_buff_size; 3477 u8 approx_mcast_engine_id; 3478 u8 rss_engine_id; 3479 struct regpair bd_page_base; 3480 struct regpair sge_page_base; 3481 struct regpair cqe_page_base; 3482 u8 is_leading_rss; 3483 u8 is_approx_mcast; 3484 __le16 max_agg_size; 3485 __le16 state; 3486 #define CLIENT_INIT_RX_DATA_UCAST_DROP_ALL (0x1<<0) 3487 #define CLIENT_INIT_RX_DATA_UCAST_DROP_ALL_SHIFT 0 3488 #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL (0x1<<1) 3489 #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL_SHIFT 1 3490 #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED (0x1<<2) 3491 #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED_SHIFT 2 3492 #define CLIENT_INIT_RX_DATA_MCAST_DROP_ALL (0x1<<3) 3493 #define CLIENT_INIT_RX_DATA_MCAST_DROP_ALL_SHIFT 3 3494 #define CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL (0x1<<4) 3495 #define CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL_SHIFT 4 3496 #define CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL (0x1<<5) 3497 #define CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL_SHIFT 5 3498 #define CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN (0x1<<6) 3499 #define CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN_SHIFT 6 3500 #define CLIENT_INIT_RX_DATA_RESERVED2 (0x1FF<<7) 3501 #define CLIENT_INIT_RX_DATA_RESERVED2_SHIFT 7 3502 __le16 cqe_pause_thr_low; 3503 __le16 cqe_pause_thr_high; 3504 __le16 bd_pause_thr_low; 3505 __le16 bd_pause_thr_high; 3506 __le16 sge_pause_thr_low; 3507 __le16 sge_pause_thr_high; 3508 __le16 rx_cos_mask; 3509 __le16 silent_vlan_value; 3510 __le16 silent_vlan_mask; 3511 __le32 reserved6[2]; 3512 }; 3513 3514 /* 3515 * client init tx data 3516 */ 3517 struct client_init_tx_data { 3518 u8 enforce_security_flg; 3519 u8 tx_status_block_id; 3520 u8 tx_sb_index_number; 3521 u8 tss_leading_client_id; 3522 u8 tx_switching_flg; 3523 u8 anti_spoofing_flg; 3524 __le16 default_vlan; 3525 struct regpair tx_bd_page_base; 3526 __le16 state; 3527 #define CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL (0x1<<0) 3528 #define CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL_SHIFT 0 3529 #define CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL (0x1<<1) 3530 #define CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL_SHIFT 1 3531 #define CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL (0x1<<2) 3532 #define CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL_SHIFT 2 3533 #define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN (0x1<<3) 3534 #define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN_SHIFT 3 3535 #define CLIENT_INIT_TX_DATA_RESERVED0 (0xFFF<<4) 3536 #define CLIENT_INIT_TX_DATA_RESERVED0_SHIFT 4 3537 u8 default_vlan_flg; 3538 u8 force_default_pri_flg; 3539 u8 tunnel_lso_inc_ip_id; 3540 u8 refuse_outband_vlan_flg; 3541 u8 tunnel_non_lso_pcsum_location; 3542 u8 reserved1; 3543 }; 3544 3545 /* 3546 * client init ramrod data 3547 */ 3548 struct client_init_ramrod_data { 3549 struct client_init_general_data general; 3550 struct client_init_rx_data rx; 3551 struct client_init_tx_data tx; 3552 }; 3553 3554 3555 /* 3556 * client update ramrod data 3557 */ 3558 struct client_update_ramrod_data { 3559 u8 client_id; 3560 u8 func_id; 3561 u8 inner_vlan_removal_enable_flg; 3562 u8 inner_vlan_removal_change_flg; 3563 u8 outer_vlan_removal_enable_flg; 3564 u8 outer_vlan_removal_change_flg; 3565 u8 anti_spoofing_enable_flg; 3566 u8 anti_spoofing_change_flg; 3567 u8 activate_flg; 3568 u8 activate_change_flg; 3569 __le16 default_vlan; 3570 u8 default_vlan_enable_flg; 3571 u8 default_vlan_change_flg; 3572 __le16 silent_vlan_value; 3573 __le16 silent_vlan_mask; 3574 u8 silent_vlan_removal_flg; 3575 u8 silent_vlan_change_flg; 3576 u8 refuse_outband_vlan_flg; 3577 u8 refuse_outband_vlan_change_flg; 3578 u8 tx_switching_flg; 3579 u8 tx_switching_change_flg; 3580 __le32 reserved1; 3581 __le32 echo; 3582 }; 3583 3584 3585 /* 3586 * The eth storm context of Cstorm 3587 */ 3588 struct cstorm_eth_st_context { 3589 u32 __reserved0[4]; 3590 }; 3591 3592 3593 struct double_regpair { 3594 u32 regpair0_lo; 3595 u32 regpair0_hi; 3596 u32 regpair1_lo; 3597 u32 regpair1_hi; 3598 }; 3599 3600 3601 /* 3602 * Ethernet address typesm used in ethernet tx BDs 3603 */ 3604 enum eth_addr_type { 3605 UNKNOWN_ADDRESS, 3606 UNICAST_ADDRESS, 3607 MULTICAST_ADDRESS, 3608 BROADCAST_ADDRESS, 3609 MAX_ETH_ADDR_TYPE 3610 }; 3611 3612 3613 /* 3614 * 3615 */ 3616 struct eth_classify_cmd_header { 3617 u8 cmd_general_data; 3618 #define ETH_CLASSIFY_CMD_HEADER_RX_CMD (0x1<<0) 3619 #define ETH_CLASSIFY_CMD_HEADER_RX_CMD_SHIFT 0 3620 #define ETH_CLASSIFY_CMD_HEADER_TX_CMD (0x1<<1) 3621 #define ETH_CLASSIFY_CMD_HEADER_TX_CMD_SHIFT 1 3622 #define ETH_CLASSIFY_CMD_HEADER_OPCODE (0x3<<2) 3623 #define ETH_CLASSIFY_CMD_HEADER_OPCODE_SHIFT 2 3624 #define ETH_CLASSIFY_CMD_HEADER_IS_ADD (0x1<<4) 3625 #define ETH_CLASSIFY_CMD_HEADER_IS_ADD_SHIFT 4 3626 #define ETH_CLASSIFY_CMD_HEADER_RESERVED0 (0x7<<5) 3627 #define ETH_CLASSIFY_CMD_HEADER_RESERVED0_SHIFT 5 3628 u8 func_id; 3629 u8 client_id; 3630 u8 reserved1; 3631 }; 3632 3633 3634 /* 3635 * header for eth classification config ramrod 3636 */ 3637 struct eth_classify_header { 3638 u8 rule_cnt; 3639 u8 reserved0; 3640 __le16 reserved1; 3641 __le32 echo; 3642 }; 3643 3644 3645 /* 3646 * Command for adding/removing a MAC classification rule 3647 */ 3648 struct eth_classify_mac_cmd { 3649 struct eth_classify_cmd_header header; 3650 __le16 reserved0; 3651 __le16 inner_mac; 3652 __le16 mac_lsb; 3653 __le16 mac_mid; 3654 __le16 mac_msb; 3655 __le16 reserved1; 3656 }; 3657 3658 3659 /* 3660 * Command for adding/removing a MAC-VLAN pair classification rule 3661 */ 3662 struct eth_classify_pair_cmd { 3663 struct eth_classify_cmd_header header; 3664 __le16 reserved0; 3665 __le16 inner_mac; 3666 __le16 mac_lsb; 3667 __le16 mac_mid; 3668 __le16 mac_msb; 3669 __le16 vlan; 3670 }; 3671 3672 3673 /* 3674 * Command for adding/removing a VLAN classification rule 3675 */ 3676 struct eth_classify_vlan_cmd { 3677 struct eth_classify_cmd_header header; 3678 __le32 reserved0; 3679 __le32 reserved1; 3680 __le16 reserved2; 3681 __le16 vlan; 3682 }; 3683 3684 /* 3685 * union for eth classification rule 3686 */ 3687 union eth_classify_rule_cmd { 3688 struct eth_classify_mac_cmd mac; 3689 struct eth_classify_vlan_cmd vlan; 3690 struct eth_classify_pair_cmd pair; 3691 }; 3692 3693 /* 3694 * parameters for eth classification configuration ramrod 3695 */ 3696 struct eth_classify_rules_ramrod_data { 3697 struct eth_classify_header header; 3698 union eth_classify_rule_cmd rules[CLASSIFY_RULES_COUNT]; 3699 }; 3700 3701 3702 /* 3703 * The data contain client ID need to the ramrod 3704 */ 3705 struct eth_common_ramrod_data { 3706 __le32 client_id; 3707 __le32 reserved1; 3708 }; 3709 3710 3711 /* 3712 * The eth storm context of Ustorm 3713 */ 3714 struct ustorm_eth_st_context { 3715 u32 reserved0[52]; 3716 }; 3717 3718 /* 3719 * The eth storm context of Tstorm 3720 */ 3721 struct tstorm_eth_st_context { 3722 u32 __reserved0[28]; 3723 }; 3724 3725 /* 3726 * The eth storm context of Xstorm 3727 */ 3728 struct xstorm_eth_st_context { 3729 u32 reserved0[60]; 3730 }; 3731 3732 /* 3733 * Ethernet connection context 3734 */ 3735 struct eth_context { 3736 struct ustorm_eth_st_context ustorm_st_context; 3737 struct tstorm_eth_st_context tstorm_st_context; 3738 struct xstorm_eth_ag_context xstorm_ag_context; 3739 struct tstorm_eth_ag_context tstorm_ag_context; 3740 struct cstorm_eth_ag_context cstorm_ag_context; 3741 struct ustorm_eth_ag_context ustorm_ag_context; 3742 struct timers_block_context timers_context; 3743 struct xstorm_eth_st_context xstorm_st_context; 3744 struct cstorm_eth_st_context cstorm_st_context; 3745 }; 3746 3747 3748 /* 3749 * union for sgl and raw data. 3750 */ 3751 union eth_sgl_or_raw_data { 3752 __le16 sgl[8]; 3753 u32 raw_data[4]; 3754 }; 3755 3756 /* 3757 * eth FP end aggregation CQE parameters struct 3758 */ 3759 struct eth_end_agg_rx_cqe { 3760 u8 type_error_flags; 3761 #define ETH_END_AGG_RX_CQE_TYPE (0x3<<0) 3762 #define ETH_END_AGG_RX_CQE_TYPE_SHIFT 0 3763 #define ETH_END_AGG_RX_CQE_SGL_RAW_SEL (0x1<<2) 3764 #define ETH_END_AGG_RX_CQE_SGL_RAW_SEL_SHIFT 2 3765 #define ETH_END_AGG_RX_CQE_RESERVED0 (0x1F<<3) 3766 #define ETH_END_AGG_RX_CQE_RESERVED0_SHIFT 3 3767 u8 reserved1; 3768 u8 queue_index; 3769 u8 reserved2; 3770 __le32 timestamp_delta; 3771 __le16 num_of_coalesced_segs; 3772 __le16 pkt_len; 3773 u8 pure_ack_count; 3774 u8 reserved3; 3775 __le16 reserved4; 3776 union eth_sgl_or_raw_data sgl_or_raw_data; 3777 __le32 reserved5[8]; 3778 }; 3779 3780 3781 /* 3782 * regular eth FP CQE parameters struct 3783 */ 3784 struct eth_fast_path_rx_cqe { 3785 u8 type_error_flags; 3786 #define ETH_FAST_PATH_RX_CQE_TYPE (0x3<<0) 3787 #define ETH_FAST_PATH_RX_CQE_TYPE_SHIFT 0 3788 #define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL (0x1<<2) 3789 #define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL_SHIFT 2 3790 #define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG (0x1<<3) 3791 #define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG_SHIFT 3 3792 #define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG (0x1<<4) 3793 #define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG_SHIFT 4 3794 #define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG (0x1<<5) 3795 #define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG_SHIFT 5 3796 #define ETH_FAST_PATH_RX_CQE_RESERVED0 (0x3<<6) 3797 #define ETH_FAST_PATH_RX_CQE_RESERVED0_SHIFT 6 3798 u8 status_flags; 3799 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE (0x7<<0) 3800 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE_SHIFT 0 3801 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG (0x1<<3) 3802 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG_SHIFT 3 3803 #define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG (0x1<<4) 3804 #define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG_SHIFT 4 3805 #define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG (0x1<<5) 3806 #define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG_SHIFT 5 3807 #define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG (0x1<<6) 3808 #define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG_SHIFT 6 3809 #define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG (0x1<<7) 3810 #define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG_SHIFT 7 3811 u8 queue_index; 3812 u8 placement_offset; 3813 __le32 rss_hash_result; 3814 __le16 vlan_tag; 3815 __le16 pkt_len_or_gro_seg_len; 3816 __le16 len_on_bd; 3817 struct parsing_flags pars_flags; 3818 union eth_sgl_or_raw_data sgl_or_raw_data; 3819 __le32 reserved1[8]; 3820 }; 3821 3822 3823 /* 3824 * Command for setting classification flags for a client 3825 */ 3826 struct eth_filter_rules_cmd { 3827 u8 cmd_general_data; 3828 #define ETH_FILTER_RULES_CMD_RX_CMD (0x1<<0) 3829 #define ETH_FILTER_RULES_CMD_RX_CMD_SHIFT 0 3830 #define ETH_FILTER_RULES_CMD_TX_CMD (0x1<<1) 3831 #define ETH_FILTER_RULES_CMD_TX_CMD_SHIFT 1 3832 #define ETH_FILTER_RULES_CMD_RESERVED0 (0x3F<<2) 3833 #define ETH_FILTER_RULES_CMD_RESERVED0_SHIFT 2 3834 u8 func_id; 3835 u8 client_id; 3836 u8 reserved1; 3837 __le16 state; 3838 #define ETH_FILTER_RULES_CMD_UCAST_DROP_ALL (0x1<<0) 3839 #define ETH_FILTER_RULES_CMD_UCAST_DROP_ALL_SHIFT 0 3840 #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL (0x1<<1) 3841 #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL_SHIFT 1 3842 #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED (0x1<<2) 3843 #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED_SHIFT 2 3844 #define ETH_FILTER_RULES_CMD_MCAST_DROP_ALL (0x1<<3) 3845 #define ETH_FILTER_RULES_CMD_MCAST_DROP_ALL_SHIFT 3 3846 #define ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL (0x1<<4) 3847 #define ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL_SHIFT 4 3848 #define ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL (0x1<<5) 3849 #define ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL_SHIFT 5 3850 #define ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN (0x1<<6) 3851 #define ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN_SHIFT 6 3852 #define ETH_FILTER_RULES_CMD_RESERVED2 (0x1FF<<7) 3853 #define ETH_FILTER_RULES_CMD_RESERVED2_SHIFT 7 3854 __le16 reserved3; 3855 struct regpair reserved4; 3856 }; 3857 3858 3859 /* 3860 * parameters for eth classification filters ramrod 3861 */ 3862 struct eth_filter_rules_ramrod_data { 3863 struct eth_classify_header header; 3864 struct eth_filter_rules_cmd rules[FILTER_RULES_COUNT]; 3865 }; 3866 3867 3868 /* 3869 * parameters for eth classification configuration ramrod 3870 */ 3871 struct eth_general_rules_ramrod_data { 3872 struct eth_classify_header header; 3873 union eth_classify_rule_cmd rules[CLASSIFY_RULES_COUNT]; 3874 }; 3875 3876 3877 /* 3878 * The data for Halt ramrod 3879 */ 3880 struct eth_halt_ramrod_data { 3881 __le32 client_id; 3882 __le32 reserved0; 3883 }; 3884 3885 3886 /* 3887 * destination and source mac address. 3888 */ 3889 struct eth_mac_addresses { 3890 #if defined(__BIG_ENDIAN) 3891 __le16 dst_mid; 3892 __le16 dst_lo; 3893 #elif defined(__LITTLE_ENDIAN) 3894 __le16 dst_lo; 3895 __le16 dst_mid; 3896 #endif 3897 #if defined(__BIG_ENDIAN) 3898 __le16 src_lo; 3899 __le16 dst_hi; 3900 #elif defined(__LITTLE_ENDIAN) 3901 __le16 dst_hi; 3902 __le16 src_lo; 3903 #endif 3904 #if defined(__BIG_ENDIAN) 3905 __le16 src_hi; 3906 __le16 src_mid; 3907 #elif defined(__LITTLE_ENDIAN) 3908 __le16 src_mid; 3909 __le16 src_hi; 3910 #endif 3911 }; 3912 3913 /* tunneling related data */ 3914 struct eth_tunnel_data { 3915 #if defined(__BIG_ENDIAN) 3916 __le16 dst_mid; 3917 __le16 dst_lo; 3918 #elif defined(__LITTLE_ENDIAN) 3919 __le16 dst_lo; 3920 __le16 dst_mid; 3921 #endif 3922 #if defined(__BIG_ENDIAN) 3923 __le16 reserved0; 3924 __le16 dst_hi; 3925 #elif defined(__LITTLE_ENDIAN) 3926 __le16 dst_hi; 3927 __le16 reserved0; 3928 #endif 3929 #if defined(__BIG_ENDIAN) 3930 u8 reserved1; 3931 u8 ip_hdr_start_inner_w; 3932 __le16 pseudo_csum; 3933 #elif defined(__LITTLE_ENDIAN) 3934 __le16 pseudo_csum; 3935 u8 ip_hdr_start_inner_w; 3936 u8 reserved1; 3937 #endif 3938 }; 3939 3940 /* union for mac addresses and for tunneling data. 3941 * considered as tunneling data only if (tunnel_exist == 1). 3942 */ 3943 union eth_mac_addr_or_tunnel_data { 3944 struct eth_mac_addresses mac_addr; 3945 struct eth_tunnel_data tunnel_data; 3946 }; 3947 3948 /*Command for setting multicast classification for a client */ 3949 struct eth_multicast_rules_cmd { 3950 u8 cmd_general_data; 3951 #define ETH_MULTICAST_RULES_CMD_RX_CMD (0x1<<0) 3952 #define ETH_MULTICAST_RULES_CMD_RX_CMD_SHIFT 0 3953 #define ETH_MULTICAST_RULES_CMD_TX_CMD (0x1<<1) 3954 #define ETH_MULTICAST_RULES_CMD_TX_CMD_SHIFT 1 3955 #define ETH_MULTICAST_RULES_CMD_IS_ADD (0x1<<2) 3956 #define ETH_MULTICAST_RULES_CMD_IS_ADD_SHIFT 2 3957 #define ETH_MULTICAST_RULES_CMD_RESERVED0 (0x1F<<3) 3958 #define ETH_MULTICAST_RULES_CMD_RESERVED0_SHIFT 3 3959 u8 func_id; 3960 u8 bin_id; 3961 u8 engine_id; 3962 __le32 reserved2; 3963 struct regpair reserved3; 3964 }; 3965 3966 /* 3967 * parameters for multicast classification ramrod 3968 */ 3969 struct eth_multicast_rules_ramrod_data { 3970 struct eth_classify_header header; 3971 struct eth_multicast_rules_cmd rules[MULTICAST_RULES_COUNT]; 3972 }; 3973 3974 /* 3975 * Place holder for ramrods protocol specific data 3976 */ 3977 struct ramrod_data { 3978 __le32 data_lo; 3979 __le32 data_hi; 3980 }; 3981 3982 /* 3983 * union for ramrod data for Ethernet protocol (CQE) (force size of 16 bits) 3984 */ 3985 union eth_ramrod_data { 3986 struct ramrod_data general; 3987 }; 3988 3989 3990 /* 3991 * RSS toeplitz hash type, as reported in CQE 3992 */ 3993 enum eth_rss_hash_type { 3994 DEFAULT_HASH_TYPE, 3995 IPV4_HASH_TYPE, 3996 TCP_IPV4_HASH_TYPE, 3997 IPV6_HASH_TYPE, 3998 TCP_IPV6_HASH_TYPE, 3999 VLAN_PRI_HASH_TYPE, 4000 E1HOV_PRI_HASH_TYPE, 4001 DSCP_HASH_TYPE, 4002 MAX_ETH_RSS_HASH_TYPE 4003 }; 4004 4005 4006 /* 4007 * Ethernet RSS mode 4008 */ 4009 enum eth_rss_mode { 4010 ETH_RSS_MODE_DISABLED, 4011 ETH_RSS_MODE_REGULAR, 4012 ETH_RSS_MODE_VLAN_PRI, 4013 ETH_RSS_MODE_E1HOV_PRI, 4014 ETH_RSS_MODE_IP_DSCP, 4015 MAX_ETH_RSS_MODE 4016 }; 4017 4018 4019 /* 4020 * parameters for RSS update ramrod (E2) 4021 */ 4022 struct eth_rss_update_ramrod_data { 4023 u8 rss_engine_id; 4024 u8 capabilities; 4025 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY (0x1<<0) 4026 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY_SHIFT 0 4027 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY (0x1<<1) 4028 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY_SHIFT 1 4029 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY (0x1<<2) 4030 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY_SHIFT 2 4031 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY (0x1<<3) 4032 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY_SHIFT 3 4033 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY (0x1<<4) 4034 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY_SHIFT 4 4035 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY (0x1<<5) 4036 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY_SHIFT 5 4037 #define ETH_RSS_UPDATE_RAMROD_DATA_EN_5_TUPLE_CAPABILITY (0x1<<6) 4038 #define ETH_RSS_UPDATE_RAMROD_DATA_EN_5_TUPLE_CAPABILITY_SHIFT 6 4039 #define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY (0x1<<7) 4040 #define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY_SHIFT 7 4041 u8 rss_result_mask; 4042 u8 rss_mode; 4043 __le16 udp_4tuple_dst_port_mask; 4044 __le16 udp_4tuple_dst_port_value; 4045 u8 indirection_table[T_ETH_INDIRECTION_TABLE_SIZE]; 4046 __le32 rss_key[T_ETH_RSS_KEY]; 4047 __le32 echo; 4048 __le32 reserved3; 4049 }; 4050 4051 4052 /* 4053 * The eth Rx Buffer Descriptor 4054 */ 4055 struct eth_rx_bd { 4056 __le32 addr_lo; 4057 __le32 addr_hi; 4058 }; 4059 4060 4061 /* 4062 * Eth Rx Cqe structure- general structure for ramrods 4063 */ 4064 struct common_ramrod_eth_rx_cqe { 4065 u8 ramrod_type; 4066 #define COMMON_RAMROD_ETH_RX_CQE_TYPE (0x3<<0) 4067 #define COMMON_RAMROD_ETH_RX_CQE_TYPE_SHIFT 0 4068 #define COMMON_RAMROD_ETH_RX_CQE_ERROR (0x1<<2) 4069 #define COMMON_RAMROD_ETH_RX_CQE_ERROR_SHIFT 2 4070 #define COMMON_RAMROD_ETH_RX_CQE_RESERVED0 (0x1F<<3) 4071 #define COMMON_RAMROD_ETH_RX_CQE_RESERVED0_SHIFT 3 4072 u8 conn_type; 4073 __le16 reserved1; 4074 __le32 conn_and_cmd_data; 4075 #define COMMON_RAMROD_ETH_RX_CQE_CID (0xFFFFFF<<0) 4076 #define COMMON_RAMROD_ETH_RX_CQE_CID_SHIFT 0 4077 #define COMMON_RAMROD_ETH_RX_CQE_CMD_ID (0xFF<<24) 4078 #define COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT 24 4079 struct ramrod_data protocol_data; 4080 __le32 echo; 4081 __le32 reserved2[11]; 4082 }; 4083 4084 /* 4085 * Rx Last CQE in page (in ETH) 4086 */ 4087 struct eth_rx_cqe_next_page { 4088 __le32 addr_lo; 4089 __le32 addr_hi; 4090 __le32 reserved[14]; 4091 }; 4092 4093 /* 4094 * union for all eth rx cqe types (fix their sizes) 4095 */ 4096 union eth_rx_cqe { 4097 struct eth_fast_path_rx_cqe fast_path_cqe; 4098 struct common_ramrod_eth_rx_cqe ramrod_cqe; 4099 struct eth_rx_cqe_next_page next_page_cqe; 4100 struct eth_end_agg_rx_cqe end_agg_cqe; 4101 }; 4102 4103 4104 /* 4105 * Values for RX ETH CQE type field 4106 */ 4107 enum eth_rx_cqe_type { 4108 RX_ETH_CQE_TYPE_ETH_FASTPATH, 4109 RX_ETH_CQE_TYPE_ETH_RAMROD, 4110 RX_ETH_CQE_TYPE_ETH_START_AGG, 4111 RX_ETH_CQE_TYPE_ETH_STOP_AGG, 4112 MAX_ETH_RX_CQE_TYPE 4113 }; 4114 4115 4116 /* 4117 * Type of SGL/Raw field in ETH RX fast path CQE 4118 */ 4119 enum eth_rx_fp_sel { 4120 ETH_FP_CQE_REGULAR, 4121 ETH_FP_CQE_RAW, 4122 MAX_ETH_RX_FP_SEL 4123 }; 4124 4125 4126 /* 4127 * The eth Rx SGE Descriptor 4128 */ 4129 struct eth_rx_sge { 4130 __le32 addr_lo; 4131 __le32 addr_hi; 4132 }; 4133 4134 4135 /* 4136 * common data for all protocols 4137 */ 4138 struct spe_hdr { 4139 __le32 conn_and_cmd_data; 4140 #define SPE_HDR_CID (0xFFFFFF<<0) 4141 #define SPE_HDR_CID_SHIFT 0 4142 #define SPE_HDR_CMD_ID (0xFF<<24) 4143 #define SPE_HDR_CMD_ID_SHIFT 24 4144 __le16 type; 4145 #define SPE_HDR_CONN_TYPE (0xFF<<0) 4146 #define SPE_HDR_CONN_TYPE_SHIFT 0 4147 #define SPE_HDR_FUNCTION_ID (0xFF<<8) 4148 #define SPE_HDR_FUNCTION_ID_SHIFT 8 4149 __le16 reserved1; 4150 }; 4151 4152 /* 4153 * specific data for ethernet slow path element 4154 */ 4155 union eth_specific_data { 4156 u8 protocol_data[8]; 4157 struct regpair client_update_ramrod_data; 4158 struct regpair client_init_ramrod_init_data; 4159 struct eth_halt_ramrod_data halt_ramrod_data; 4160 struct regpair update_data_addr; 4161 struct eth_common_ramrod_data common_ramrod_data; 4162 struct regpair classify_cfg_addr; 4163 struct regpair filter_cfg_addr; 4164 struct regpair mcast_cfg_addr; 4165 }; 4166 4167 /* 4168 * Ethernet slow path element 4169 */ 4170 struct eth_spe { 4171 struct spe_hdr hdr; 4172 union eth_specific_data data; 4173 }; 4174 4175 4176 /* 4177 * Ethernet command ID for slow path elements 4178 */ 4179 enum eth_spqe_cmd_id { 4180 RAMROD_CMD_ID_ETH_UNUSED, 4181 RAMROD_CMD_ID_ETH_CLIENT_SETUP, 4182 RAMROD_CMD_ID_ETH_HALT, 4183 RAMROD_CMD_ID_ETH_FORWARD_SETUP, 4184 RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP, 4185 RAMROD_CMD_ID_ETH_CLIENT_UPDATE, 4186 RAMROD_CMD_ID_ETH_EMPTY, 4187 RAMROD_CMD_ID_ETH_TERMINATE, 4188 RAMROD_CMD_ID_ETH_TPA_UPDATE, 4189 RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES, 4190 RAMROD_CMD_ID_ETH_FILTER_RULES, 4191 RAMROD_CMD_ID_ETH_MULTICAST_RULES, 4192 RAMROD_CMD_ID_ETH_RSS_UPDATE, 4193 RAMROD_CMD_ID_ETH_SET_MAC, 4194 MAX_ETH_SPQE_CMD_ID 4195 }; 4196 4197 4198 /* 4199 * eth tpa update command 4200 */ 4201 enum eth_tpa_update_command { 4202 TPA_UPDATE_NONE_COMMAND, 4203 TPA_UPDATE_ENABLE_COMMAND, 4204 TPA_UPDATE_DISABLE_COMMAND, 4205 MAX_ETH_TPA_UPDATE_COMMAND 4206 }; 4207 4208 /* In case of LSO over IPv4 tunnel, whether to increment 4209 * IP ID on external IP header or internal IP header 4210 */ 4211 enum eth_tunnel_lso_inc_ip_id { 4212 EXT_HEADER, 4213 INT_HEADER, 4214 MAX_ETH_TUNNEL_LSO_INC_IP_ID 4215 }; 4216 4217 /* In case tunnel exist and L4 checksum offload, 4218 * the pseudo checksum location, on packet or on BD. 4219 */ 4220 enum eth_tunnel_non_lso_pcsum_location { 4221 PCSUM_ON_PKT, 4222 PCSUM_ON_BD, 4223 MAX_ETH_TUNNEL_NON_LSO_PCSUM_LOCATION 4224 }; 4225 4226 /* 4227 * Tx regular BD structure 4228 */ 4229 struct eth_tx_bd { 4230 __le32 addr_lo; 4231 __le32 addr_hi; 4232 __le16 total_pkt_bytes; 4233 __le16 nbytes; 4234 u8 reserved[4]; 4235 }; 4236 4237 4238 /* 4239 * structure for easy accessibility to assembler 4240 */ 4241 struct eth_tx_bd_flags { 4242 u8 as_bitfield; 4243 #define ETH_TX_BD_FLAGS_IP_CSUM (0x1<<0) 4244 #define ETH_TX_BD_FLAGS_IP_CSUM_SHIFT 0 4245 #define ETH_TX_BD_FLAGS_L4_CSUM (0x1<<1) 4246 #define ETH_TX_BD_FLAGS_L4_CSUM_SHIFT 1 4247 #define ETH_TX_BD_FLAGS_VLAN_MODE (0x3<<2) 4248 #define ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT 2 4249 #define ETH_TX_BD_FLAGS_START_BD (0x1<<4) 4250 #define ETH_TX_BD_FLAGS_START_BD_SHIFT 4 4251 #define ETH_TX_BD_FLAGS_IS_UDP (0x1<<5) 4252 #define ETH_TX_BD_FLAGS_IS_UDP_SHIFT 5 4253 #define ETH_TX_BD_FLAGS_SW_LSO (0x1<<6) 4254 #define ETH_TX_BD_FLAGS_SW_LSO_SHIFT 6 4255 #define ETH_TX_BD_FLAGS_IPV6 (0x1<<7) 4256 #define ETH_TX_BD_FLAGS_IPV6_SHIFT 7 4257 }; 4258 4259 /* 4260 * The eth Tx Buffer Descriptor 4261 */ 4262 struct eth_tx_start_bd { 4263 __le32 addr_lo; 4264 __le32 addr_hi; 4265 __le16 nbd; 4266 __le16 nbytes; 4267 __le16 vlan_or_ethertype; 4268 struct eth_tx_bd_flags bd_flags; 4269 u8 general_data; 4270 #define ETH_TX_START_BD_HDR_NBDS (0xF<<0) 4271 #define ETH_TX_START_BD_HDR_NBDS_SHIFT 0 4272 #define ETH_TX_START_BD_FORCE_VLAN_MODE (0x1<<4) 4273 #define ETH_TX_START_BD_FORCE_VLAN_MODE_SHIFT 4 4274 #define ETH_TX_START_BD_PARSE_NBDS (0x3<<5) 4275 #define ETH_TX_START_BD_PARSE_NBDS_SHIFT 5 4276 #define ETH_TX_START_BD_TUNNEL_EXIST (0x1<<7) 4277 #define ETH_TX_START_BD_TUNNEL_EXIST_SHIFT 7 4278 }; 4279 4280 /* 4281 * Tx parsing BD structure for ETH E1/E1h 4282 */ 4283 struct eth_tx_parse_bd_e1x { 4284 __le16 global_data; 4285 #define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W (0xF<<0) 4286 #define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W_SHIFT 0 4287 #define ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE (0x3<<4) 4288 #define ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE_SHIFT 4 4289 #define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN (0x1<<6) 4290 #define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN_SHIFT 6 4291 #define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN (0x1<<7) 4292 #define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN_SHIFT 7 4293 #define ETH_TX_PARSE_BD_E1X_NS_FLG (0x1<<8) 4294 #define ETH_TX_PARSE_BD_E1X_NS_FLG_SHIFT 8 4295 #define ETH_TX_PARSE_BD_E1X_RESERVED0 (0x7F<<9) 4296 #define ETH_TX_PARSE_BD_E1X_RESERVED0_SHIFT 9 4297 u8 tcp_flags; 4298 #define ETH_TX_PARSE_BD_E1X_FIN_FLG (0x1<<0) 4299 #define ETH_TX_PARSE_BD_E1X_FIN_FLG_SHIFT 0 4300 #define ETH_TX_PARSE_BD_E1X_SYN_FLG (0x1<<1) 4301 #define ETH_TX_PARSE_BD_E1X_SYN_FLG_SHIFT 1 4302 #define ETH_TX_PARSE_BD_E1X_RST_FLG (0x1<<2) 4303 #define ETH_TX_PARSE_BD_E1X_RST_FLG_SHIFT 2 4304 #define ETH_TX_PARSE_BD_E1X_PSH_FLG (0x1<<3) 4305 #define ETH_TX_PARSE_BD_E1X_PSH_FLG_SHIFT 3 4306 #define ETH_TX_PARSE_BD_E1X_ACK_FLG (0x1<<4) 4307 #define ETH_TX_PARSE_BD_E1X_ACK_FLG_SHIFT 4 4308 #define ETH_TX_PARSE_BD_E1X_URG_FLG (0x1<<5) 4309 #define ETH_TX_PARSE_BD_E1X_URG_FLG_SHIFT 5 4310 #define ETH_TX_PARSE_BD_E1X_ECE_FLG (0x1<<6) 4311 #define ETH_TX_PARSE_BD_E1X_ECE_FLG_SHIFT 6 4312 #define ETH_TX_PARSE_BD_E1X_CWR_FLG (0x1<<7) 4313 #define ETH_TX_PARSE_BD_E1X_CWR_FLG_SHIFT 7 4314 u8 ip_hlen_w; 4315 __le16 total_hlen_w; 4316 __le16 tcp_pseudo_csum; 4317 __le16 lso_mss; 4318 __le16 ip_id; 4319 __le32 tcp_send_seq; 4320 }; 4321 4322 /* 4323 * Tx parsing BD structure for ETH E2 4324 */ 4325 struct eth_tx_parse_bd_e2 { 4326 union eth_mac_addr_or_tunnel_data data; 4327 __le32 parsing_data; 4328 #define ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W (0x7FF<<0) 4329 #define ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W_SHIFT 0 4330 #define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW (0xF<<11) 4331 #define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW_SHIFT 11 4332 #define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR (0x1<<15) 4333 #define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR_SHIFT 15 4334 #define ETH_TX_PARSE_BD_E2_LSO_MSS (0x3FFF<<16) 4335 #define ETH_TX_PARSE_BD_E2_LSO_MSS_SHIFT 16 4336 #define ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE (0x3<<30) 4337 #define ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE_SHIFT 30 4338 }; 4339 4340 /* 4341 * Tx 2nd parsing BD structure for ETH packet 4342 */ 4343 struct eth_tx_parse_2nd_bd { 4344 __le16 global_data; 4345 #define ETH_TX_PARSE_2ND_BD_IP_HDR_START_OUTER_W (0xF<<0) 4346 #define ETH_TX_PARSE_2ND_BD_IP_HDR_START_OUTER_W_SHIFT 0 4347 #define ETH_TX_PARSE_2ND_BD_IP_HDR_TYPE_OUTER (0x1<<4) 4348 #define ETH_TX_PARSE_2ND_BD_IP_HDR_TYPE_OUTER_SHIFT 4 4349 #define ETH_TX_PARSE_2ND_BD_LLC_SNAP_EN (0x1<<5) 4350 #define ETH_TX_PARSE_2ND_BD_LLC_SNAP_EN_SHIFT 5 4351 #define ETH_TX_PARSE_2ND_BD_NS_FLG (0x1<<6) 4352 #define ETH_TX_PARSE_2ND_BD_NS_FLG_SHIFT 6 4353 #define ETH_TX_PARSE_2ND_BD_TUNNEL_UDP_EXIST (0x1<<7) 4354 #define ETH_TX_PARSE_2ND_BD_TUNNEL_UDP_EXIST_SHIFT 7 4355 #define ETH_TX_PARSE_2ND_BD_IP_HDR_LEN_OUTER_W (0x1F<<8) 4356 #define ETH_TX_PARSE_2ND_BD_IP_HDR_LEN_OUTER_W_SHIFT 8 4357 #define ETH_TX_PARSE_2ND_BD_RESERVED0 (0x7<<13) 4358 #define ETH_TX_PARSE_2ND_BD_RESERVED0_SHIFT 13 4359 __le16 reserved1; 4360 u8 tcp_flags; 4361 #define ETH_TX_PARSE_2ND_BD_FIN_FLG (0x1<<0) 4362 #define ETH_TX_PARSE_2ND_BD_FIN_FLG_SHIFT 0 4363 #define ETH_TX_PARSE_2ND_BD_SYN_FLG (0x1<<1) 4364 #define ETH_TX_PARSE_2ND_BD_SYN_FLG_SHIFT 1 4365 #define ETH_TX_PARSE_2ND_BD_RST_FLG (0x1<<2) 4366 #define ETH_TX_PARSE_2ND_BD_RST_FLG_SHIFT 2 4367 #define ETH_TX_PARSE_2ND_BD_PSH_FLG (0x1<<3) 4368 #define ETH_TX_PARSE_2ND_BD_PSH_FLG_SHIFT 3 4369 #define ETH_TX_PARSE_2ND_BD_ACK_FLG (0x1<<4) 4370 #define ETH_TX_PARSE_2ND_BD_ACK_FLG_SHIFT 4 4371 #define ETH_TX_PARSE_2ND_BD_URG_FLG (0x1<<5) 4372 #define ETH_TX_PARSE_2ND_BD_URG_FLG_SHIFT 5 4373 #define ETH_TX_PARSE_2ND_BD_ECE_FLG (0x1<<6) 4374 #define ETH_TX_PARSE_2ND_BD_ECE_FLG_SHIFT 6 4375 #define ETH_TX_PARSE_2ND_BD_CWR_FLG (0x1<<7) 4376 #define ETH_TX_PARSE_2ND_BD_CWR_FLG_SHIFT 7 4377 u8 reserved2; 4378 u8 tunnel_udp_hdr_start_w; 4379 u8 fw_ip_hdr_to_payload_w; 4380 __le16 fw_ip_csum_wo_len_flags_frag; 4381 __le16 hw_ip_id; 4382 __le32 tcp_send_seq; 4383 }; 4384 4385 /* The last BD in the BD memory will hold a pointer to the next BD memory */ 4386 struct eth_tx_next_bd { 4387 __le32 addr_lo; 4388 __le32 addr_hi; 4389 u8 reserved[8]; 4390 }; 4391 4392 /* 4393 * union for 4 Bd types 4394 */ 4395 union eth_tx_bd_types { 4396 struct eth_tx_start_bd start_bd; 4397 struct eth_tx_bd reg_bd; 4398 struct eth_tx_parse_bd_e1x parse_bd_e1x; 4399 struct eth_tx_parse_bd_e2 parse_bd_e2; 4400 struct eth_tx_parse_2nd_bd parse_2nd_bd; 4401 struct eth_tx_next_bd next_bd; 4402 }; 4403 4404 /* 4405 * array of 13 bds as appears in the eth xstorm context 4406 */ 4407 struct eth_tx_bds_array { 4408 union eth_tx_bd_types bds[13]; 4409 }; 4410 4411 4412 /* 4413 * VLAN mode on TX BDs 4414 */ 4415 enum eth_tx_vlan_type { 4416 X_ETH_NO_VLAN, 4417 X_ETH_OUTBAND_VLAN, 4418 X_ETH_INBAND_VLAN, 4419 X_ETH_FW_ADDED_VLAN, 4420 MAX_ETH_TX_VLAN_TYPE 4421 }; 4422 4423 4424 /* 4425 * Ethernet VLAN filtering mode in E1x 4426 */ 4427 enum eth_vlan_filter_mode { 4428 ETH_VLAN_FILTER_ANY_VLAN, 4429 ETH_VLAN_FILTER_SPECIFIC_VLAN, 4430 ETH_VLAN_FILTER_CLASSIFY, 4431 MAX_ETH_VLAN_FILTER_MODE 4432 }; 4433 4434 4435 /* 4436 * MAC filtering configuration command header 4437 */ 4438 struct mac_configuration_hdr { 4439 u8 length; 4440 u8 offset; 4441 __le16 client_id; 4442 __le32 echo; 4443 }; 4444 4445 /* 4446 * MAC address in list for ramrod 4447 */ 4448 struct mac_configuration_entry { 4449 __le16 lsb_mac_addr; 4450 __le16 middle_mac_addr; 4451 __le16 msb_mac_addr; 4452 __le16 vlan_id; 4453 u8 pf_id; 4454 u8 flags; 4455 #define MAC_CONFIGURATION_ENTRY_ACTION_TYPE (0x1<<0) 4456 #define MAC_CONFIGURATION_ENTRY_ACTION_TYPE_SHIFT 0 4457 #define MAC_CONFIGURATION_ENTRY_RDMA_MAC (0x1<<1) 4458 #define MAC_CONFIGURATION_ENTRY_RDMA_MAC_SHIFT 1 4459 #define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE (0x3<<2) 4460 #define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE_SHIFT 2 4461 #define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL (0x1<<4) 4462 #define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL_SHIFT 4 4463 #define MAC_CONFIGURATION_ENTRY_BROADCAST (0x1<<5) 4464 #define MAC_CONFIGURATION_ENTRY_BROADCAST_SHIFT 5 4465 #define MAC_CONFIGURATION_ENTRY_RESERVED1 (0x3<<6) 4466 #define MAC_CONFIGURATION_ENTRY_RESERVED1_SHIFT 6 4467 __le16 reserved0; 4468 __le32 clients_bit_vector; 4469 }; 4470 4471 /* 4472 * MAC filtering configuration command 4473 */ 4474 struct mac_configuration_cmd { 4475 struct mac_configuration_hdr hdr; 4476 struct mac_configuration_entry config_table[64]; 4477 }; 4478 4479 4480 /* 4481 * Set-MAC command type (in E1x) 4482 */ 4483 enum set_mac_action_type { 4484 T_ETH_MAC_COMMAND_INVALIDATE, 4485 T_ETH_MAC_COMMAND_SET, 4486 MAX_SET_MAC_ACTION_TYPE 4487 }; 4488 4489 4490 /* 4491 * Ethernet TPA Modes 4492 */ 4493 enum tpa_mode { 4494 TPA_LRO, 4495 TPA_GRO, 4496 MAX_TPA_MODE}; 4497 4498 4499 /* 4500 * tpa update ramrod data 4501 */ 4502 struct tpa_update_ramrod_data { 4503 u8 update_ipv4; 4504 u8 update_ipv6; 4505 u8 client_id; 4506 u8 max_tpa_queues; 4507 u8 max_sges_for_packet; 4508 u8 complete_on_both_clients; 4509 u8 dont_verify_rings_pause_thr_flg; 4510 u8 tpa_mode; 4511 __le16 sge_buff_size; 4512 __le16 max_agg_size; 4513 __le32 sge_page_base_lo; 4514 __le32 sge_page_base_hi; 4515 __le16 sge_pause_thr_low; 4516 __le16 sge_pause_thr_high; 4517 }; 4518 4519 4520 /* 4521 * approximate-match multicast filtering for E1H per function in Tstorm 4522 */ 4523 struct tstorm_eth_approximate_match_multicast_filtering { 4524 u32 mcast_add_hash_bit_array[8]; 4525 }; 4526 4527 4528 /* 4529 * Common configuration parameters per function in Tstorm 4530 */ 4531 struct tstorm_eth_function_common_config { 4532 __le16 config_flags; 4533 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0) 4534 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0 4535 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1) 4536 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1 4537 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1<<2) 4538 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2 4539 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3) 4540 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3 4541 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE (0x7<<4) 4542 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT 4 4543 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE (0x1<<7) 4544 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE_SHIFT 7 4545 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0xFF<<8) 4546 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 8 4547 u8 rss_result_mask; 4548 u8 reserved1; 4549 __le16 vlan_id[2]; 4550 }; 4551 4552 4553 /* 4554 * MAC filtering configuration parameters per port in Tstorm 4555 */ 4556 struct tstorm_eth_mac_filter_config { 4557 u32 ucast_drop_all; 4558 u32 ucast_accept_all; 4559 u32 mcast_drop_all; 4560 u32 mcast_accept_all; 4561 u32 bcast_accept_all; 4562 u32 vlan_filter[2]; 4563 u32 unmatched_unicast; 4564 }; 4565 4566 4567 /* 4568 * tx only queue init ramrod data 4569 */ 4570 struct tx_queue_init_ramrod_data { 4571 struct client_init_general_data general; 4572 struct client_init_tx_data tx; 4573 }; 4574 4575 4576 /* 4577 * Three RX producers for ETH 4578 */ 4579 struct ustorm_eth_rx_producers { 4580 #if defined(__BIG_ENDIAN) 4581 u16 bd_prod; 4582 u16 cqe_prod; 4583 #elif defined(__LITTLE_ENDIAN) 4584 u16 cqe_prod; 4585 u16 bd_prod; 4586 #endif 4587 #if defined(__BIG_ENDIAN) 4588 u16 reserved; 4589 u16 sge_prod; 4590 #elif defined(__LITTLE_ENDIAN) 4591 u16 sge_prod; 4592 u16 reserved; 4593 #endif 4594 }; 4595 4596 4597 /* 4598 * FCoE RX statistics parameters section#0 4599 */ 4600 struct fcoe_rx_stat_params_section0 { 4601 __le32 fcoe_rx_pkt_cnt; 4602 __le32 fcoe_rx_byte_cnt; 4603 }; 4604 4605 4606 /* 4607 * FCoE RX statistics parameters section#1 4608 */ 4609 struct fcoe_rx_stat_params_section1 { 4610 __le32 fcoe_ver_cnt; 4611 __le32 fcoe_rx_drop_pkt_cnt; 4612 }; 4613 4614 4615 /* 4616 * FCoE RX statistics parameters section#2 4617 */ 4618 struct fcoe_rx_stat_params_section2 { 4619 __le32 fc_crc_cnt; 4620 __le32 eofa_del_cnt; 4621 __le32 miss_frame_cnt; 4622 __le32 seq_timeout_cnt; 4623 __le32 drop_seq_cnt; 4624 __le32 fcoe_rx_drop_pkt_cnt; 4625 __le32 fcp_rx_pkt_cnt; 4626 __le32 reserved0; 4627 }; 4628 4629 4630 /* 4631 * FCoE TX statistics parameters 4632 */ 4633 struct fcoe_tx_stat_params { 4634 __le32 fcoe_tx_pkt_cnt; 4635 __le32 fcoe_tx_byte_cnt; 4636 __le32 fcp_tx_pkt_cnt; 4637 __le32 reserved0; 4638 }; 4639 4640 /* 4641 * FCoE statistics parameters 4642 */ 4643 struct fcoe_statistics_params { 4644 struct fcoe_tx_stat_params tx_stat; 4645 struct fcoe_rx_stat_params_section0 rx_stat0; 4646 struct fcoe_rx_stat_params_section1 rx_stat1; 4647 struct fcoe_rx_stat_params_section2 rx_stat2; 4648 }; 4649 4650 4651 /* 4652 * The data afex vif list ramrod need 4653 */ 4654 struct afex_vif_list_ramrod_data { 4655 u8 afex_vif_list_command; 4656 u8 func_bit_map; 4657 __le16 vif_list_index; 4658 u8 func_to_clear; 4659 u8 echo; 4660 __le16 reserved1; 4661 }; 4662 4663 4664 /* 4665 * cfc delete event data 4666 */ 4667 struct cfc_del_event_data { 4668 u32 cid; 4669 u32 reserved0; 4670 u32 reserved1; 4671 }; 4672 4673 4674 /* 4675 * per-port SAFC demo variables 4676 */ 4677 struct cmng_flags_per_port { 4678 u32 cmng_enables; 4679 #define CMNG_FLAGS_PER_PORT_FAIRNESS_VN (0x1<<0) 4680 #define CMNG_FLAGS_PER_PORT_FAIRNESS_VN_SHIFT 0 4681 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN (0x1<<1) 4682 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN_SHIFT 1 4683 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS (0x1<<2) 4684 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_SHIFT 2 4685 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE (0x1<<3) 4686 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE_SHIFT 3 4687 #define __CMNG_FLAGS_PER_PORT_RESERVED0 (0xFFFFFFF<<4) 4688 #define __CMNG_FLAGS_PER_PORT_RESERVED0_SHIFT 4 4689 u32 __reserved1; 4690 }; 4691 4692 4693 /* 4694 * per-port rate shaping variables 4695 */ 4696 struct rate_shaping_vars_per_port { 4697 u32 rs_periodic_timeout; 4698 u32 rs_threshold; 4699 }; 4700 4701 /* 4702 * per-port fairness variables 4703 */ 4704 struct fairness_vars_per_port { 4705 u32 upper_bound; 4706 u32 fair_threshold; 4707 u32 fairness_timeout; 4708 u32 reserved0; 4709 }; 4710 4711 /* 4712 * per-port SAFC variables 4713 */ 4714 struct safc_struct_per_port { 4715 #if defined(__BIG_ENDIAN) 4716 u16 __reserved1; 4717 u8 __reserved0; 4718 u8 safc_timeout_usec; 4719 #elif defined(__LITTLE_ENDIAN) 4720 u8 safc_timeout_usec; 4721 u8 __reserved0; 4722 u16 __reserved1; 4723 #endif 4724 u8 cos_to_traffic_types[MAX_COS_NUMBER]; 4725 u16 cos_to_pause_mask[NUM_OF_SAFC_BITS]; 4726 }; 4727 4728 /* 4729 * Per-port congestion management variables 4730 */ 4731 struct cmng_struct_per_port { 4732 struct rate_shaping_vars_per_port rs_vars; 4733 struct fairness_vars_per_port fair_vars; 4734 struct safc_struct_per_port safc_vars; 4735 struct cmng_flags_per_port flags; 4736 }; 4737 4738 /* 4739 * a single rate shaping counter. can be used as protocol or vnic counter 4740 */ 4741 struct rate_shaping_counter { 4742 u32 quota; 4743 #if defined(__BIG_ENDIAN) 4744 u16 __reserved0; 4745 u16 rate; 4746 #elif defined(__LITTLE_ENDIAN) 4747 u16 rate; 4748 u16 __reserved0; 4749 #endif 4750 }; 4751 4752 /* 4753 * per-vnic rate shaping variables 4754 */ 4755 struct rate_shaping_vars_per_vn { 4756 struct rate_shaping_counter vn_counter; 4757 }; 4758 4759 /* 4760 * per-vnic fairness variables 4761 */ 4762 struct fairness_vars_per_vn { 4763 u32 cos_credit_delta[MAX_COS_NUMBER]; 4764 u32 vn_credit_delta; 4765 u32 __reserved0; 4766 }; 4767 4768 /* 4769 * cmng port init state 4770 */ 4771 struct cmng_vnic { 4772 struct rate_shaping_vars_per_vn vnic_max_rate[4]; 4773 struct fairness_vars_per_vn vnic_min_rate[4]; 4774 }; 4775 4776 /* 4777 * cmng port init state 4778 */ 4779 struct cmng_init { 4780 struct cmng_struct_per_port port; 4781 struct cmng_vnic vnic; 4782 }; 4783 4784 4785 /* 4786 * driver parameters for congestion management init, all rates are in Mbps 4787 */ 4788 struct cmng_init_input { 4789 u32 port_rate; 4790 u16 vnic_min_rate[4]; 4791 u16 vnic_max_rate[4]; 4792 u16 cos_min_rate[MAX_COS_NUMBER]; 4793 u16 cos_to_pause_mask[MAX_COS_NUMBER]; 4794 struct cmng_flags_per_port flags; 4795 }; 4796 4797 4798 /* 4799 * Protocol-common command ID for slow path elements 4800 */ 4801 enum common_spqe_cmd_id { 4802 RAMROD_CMD_ID_COMMON_UNUSED, 4803 RAMROD_CMD_ID_COMMON_FUNCTION_START, 4804 RAMROD_CMD_ID_COMMON_FUNCTION_STOP, 4805 RAMROD_CMD_ID_COMMON_FUNCTION_UPDATE, 4806 RAMROD_CMD_ID_COMMON_CFC_DEL, 4807 RAMROD_CMD_ID_COMMON_CFC_DEL_WB, 4808 RAMROD_CMD_ID_COMMON_STAT_QUERY, 4809 RAMROD_CMD_ID_COMMON_STOP_TRAFFIC, 4810 RAMROD_CMD_ID_COMMON_START_TRAFFIC, 4811 RAMROD_CMD_ID_COMMON_AFEX_VIF_LISTS, 4812 RAMROD_CMD_ID_COMMON_SET_TIMESYNC, 4813 MAX_COMMON_SPQE_CMD_ID 4814 }; 4815 4816 /* 4817 * Per-protocol connection types 4818 */ 4819 enum connection_type { 4820 ETH_CONNECTION_TYPE, 4821 TOE_CONNECTION_TYPE, 4822 RDMA_CONNECTION_TYPE, 4823 ISCSI_CONNECTION_TYPE, 4824 FCOE_CONNECTION_TYPE, 4825 RESERVED_CONNECTION_TYPE_0, 4826 RESERVED_CONNECTION_TYPE_1, 4827 RESERVED_CONNECTION_TYPE_2, 4828 NONE_CONNECTION_TYPE, 4829 MAX_CONNECTION_TYPE 4830 }; 4831 4832 4833 /* 4834 * Cos modes 4835 */ 4836 enum cos_mode { 4837 OVERRIDE_COS, 4838 STATIC_COS, 4839 FW_WRR, 4840 MAX_COS_MODE 4841 }; 4842 4843 4844 /* 4845 * Dynamic HC counters set by the driver 4846 */ 4847 struct hc_dynamic_drv_counter { 4848 u32 val[HC_SB_MAX_DYNAMIC_INDICES]; 4849 }; 4850 4851 /* 4852 * zone A per-queue data 4853 */ 4854 struct cstorm_queue_zone_data { 4855 struct hc_dynamic_drv_counter hc_dyn_drv_cnt; 4856 struct regpair reserved[2]; 4857 }; 4858 4859 4860 /* 4861 * Vf-PF channel data in cstorm ram (non-triggered zone) 4862 */ 4863 struct vf_pf_channel_zone_data { 4864 u32 msg_addr_lo; 4865 u32 msg_addr_hi; 4866 }; 4867 4868 /* 4869 * zone for VF non-triggered data 4870 */ 4871 struct non_trigger_vf_zone { 4872 struct vf_pf_channel_zone_data vf_pf_channel; 4873 }; 4874 4875 /* 4876 * Vf-PF channel trigger zone in cstorm ram 4877 */ 4878 struct vf_pf_channel_zone_trigger { 4879 u8 addr_valid; 4880 }; 4881 4882 /* 4883 * zone that triggers the in-bound interrupt 4884 */ 4885 struct trigger_vf_zone { 4886 #if defined(__BIG_ENDIAN) 4887 u16 reserved1; 4888 u8 reserved0; 4889 struct vf_pf_channel_zone_trigger vf_pf_channel; 4890 #elif defined(__LITTLE_ENDIAN) 4891 struct vf_pf_channel_zone_trigger vf_pf_channel; 4892 u8 reserved0; 4893 u16 reserved1; 4894 #endif 4895 u32 reserved2; 4896 }; 4897 4898 /* 4899 * zone B per-VF data 4900 */ 4901 struct cstorm_vf_zone_data { 4902 struct non_trigger_vf_zone non_trigger; 4903 struct trigger_vf_zone trigger; 4904 }; 4905 4906 4907 /* 4908 * Dynamic host coalescing init parameters, per state machine 4909 */ 4910 struct dynamic_hc_sm_config { 4911 u32 threshold[3]; 4912 u8 shift_per_protocol[HC_SB_MAX_DYNAMIC_INDICES]; 4913 u8 hc_timeout0[HC_SB_MAX_DYNAMIC_INDICES]; 4914 u8 hc_timeout1[HC_SB_MAX_DYNAMIC_INDICES]; 4915 u8 hc_timeout2[HC_SB_MAX_DYNAMIC_INDICES]; 4916 u8 hc_timeout3[HC_SB_MAX_DYNAMIC_INDICES]; 4917 }; 4918 4919 /* 4920 * Dynamic host coalescing init parameters 4921 */ 4922 struct dynamic_hc_config { 4923 struct dynamic_hc_sm_config sm_config[HC_SB_MAX_SM]; 4924 }; 4925 4926 4927 struct e2_integ_data { 4928 #if defined(__BIG_ENDIAN) 4929 u8 flags; 4930 #define E2_INTEG_DATA_TESTING_EN (0x1<<0) 4931 #define E2_INTEG_DATA_TESTING_EN_SHIFT 0 4932 #define E2_INTEG_DATA_LB_TX (0x1<<1) 4933 #define E2_INTEG_DATA_LB_TX_SHIFT 1 4934 #define E2_INTEG_DATA_COS_TX (0x1<<2) 4935 #define E2_INTEG_DATA_COS_TX_SHIFT 2 4936 #define E2_INTEG_DATA_OPPORTUNISTICQM (0x1<<3) 4937 #define E2_INTEG_DATA_OPPORTUNISTICQM_SHIFT 3 4938 #define E2_INTEG_DATA_DPMTESTRELEASEDQ (0x1<<4) 4939 #define E2_INTEG_DATA_DPMTESTRELEASEDQ_SHIFT 4 4940 #define E2_INTEG_DATA_RESERVED (0x7<<5) 4941 #define E2_INTEG_DATA_RESERVED_SHIFT 5 4942 u8 cos; 4943 u8 voq; 4944 u8 pbf_queue; 4945 #elif defined(__LITTLE_ENDIAN) 4946 u8 pbf_queue; 4947 u8 voq; 4948 u8 cos; 4949 u8 flags; 4950 #define E2_INTEG_DATA_TESTING_EN (0x1<<0) 4951 #define E2_INTEG_DATA_TESTING_EN_SHIFT 0 4952 #define E2_INTEG_DATA_LB_TX (0x1<<1) 4953 #define E2_INTEG_DATA_LB_TX_SHIFT 1 4954 #define E2_INTEG_DATA_COS_TX (0x1<<2) 4955 #define E2_INTEG_DATA_COS_TX_SHIFT 2 4956 #define E2_INTEG_DATA_OPPORTUNISTICQM (0x1<<3) 4957 #define E2_INTEG_DATA_OPPORTUNISTICQM_SHIFT 3 4958 #define E2_INTEG_DATA_DPMTESTRELEASEDQ (0x1<<4) 4959 #define E2_INTEG_DATA_DPMTESTRELEASEDQ_SHIFT 4 4960 #define E2_INTEG_DATA_RESERVED (0x7<<5) 4961 #define E2_INTEG_DATA_RESERVED_SHIFT 5 4962 #endif 4963 #if defined(__BIG_ENDIAN) 4964 u16 reserved3; 4965 u8 reserved2; 4966 u8 ramEn; 4967 #elif defined(__LITTLE_ENDIAN) 4968 u8 ramEn; 4969 u8 reserved2; 4970 u16 reserved3; 4971 #endif 4972 }; 4973 4974 4975 /* 4976 * set mac event data 4977 */ 4978 struct eth_event_data { 4979 u32 echo; 4980 u32 reserved0; 4981 u32 reserved1; 4982 }; 4983 4984 4985 /* 4986 * pf-vf event data 4987 */ 4988 struct vf_pf_event_data { 4989 u8 vf_id; 4990 u8 reserved0; 4991 u16 reserved1; 4992 u32 msg_addr_lo; 4993 u32 msg_addr_hi; 4994 }; 4995 4996 /* 4997 * VF FLR event data 4998 */ 4999 struct vf_flr_event_data { 5000 u8 vf_id; 5001 u8 reserved0; 5002 u16 reserved1; 5003 u32 reserved2; 5004 u32 reserved3; 5005 }; 5006 5007 /* 5008 * malicious VF event data 5009 */ 5010 struct malicious_vf_event_data { 5011 u8 vf_id; 5012 u8 err_id; 5013 u16 reserved1; 5014 u32 reserved2; 5015 u32 reserved3; 5016 }; 5017 5018 /* 5019 * vif list event data 5020 */ 5021 struct vif_list_event_data { 5022 u8 func_bit_map; 5023 u8 echo; 5024 __le16 reserved0; 5025 __le32 reserved1; 5026 __le32 reserved2; 5027 }; 5028 5029 /* function update event data */ 5030 struct function_update_event_data { 5031 u8 echo; 5032 u8 reserved; 5033 __le16 reserved0; 5034 __le32 reserved1; 5035 __le32 reserved2; 5036 }; 5037 5038 5039 /* union for all event ring message types */ 5040 union event_data { 5041 struct vf_pf_event_data vf_pf_event; 5042 struct eth_event_data eth_event; 5043 struct cfc_del_event_data cfc_del_event; 5044 struct vf_flr_event_data vf_flr_event; 5045 struct malicious_vf_event_data malicious_vf_event; 5046 struct vif_list_event_data vif_list_event; 5047 struct function_update_event_data function_update_event; 5048 }; 5049 5050 5051 /* 5052 * per PF event ring data 5053 */ 5054 struct event_ring_data { 5055 struct regpair_native base_addr; 5056 #if defined(__BIG_ENDIAN) 5057 u8 index_id; 5058 u8 sb_id; 5059 u16 producer; 5060 #elif defined(__LITTLE_ENDIAN) 5061 u16 producer; 5062 u8 sb_id; 5063 u8 index_id; 5064 #endif 5065 u32 reserved0; 5066 }; 5067 5068 5069 /* 5070 * event ring message element (each element is 128 bits) 5071 */ 5072 struct event_ring_msg { 5073 u8 opcode; 5074 u8 error; 5075 u16 reserved1; 5076 union event_data data; 5077 }; 5078 5079 /* 5080 * event ring next page element (128 bits) 5081 */ 5082 struct event_ring_next { 5083 struct regpair addr; 5084 u32 reserved[2]; 5085 }; 5086 5087 /* 5088 * union for event ring element types (each element is 128 bits) 5089 */ 5090 union event_ring_elem { 5091 struct event_ring_msg message; 5092 struct event_ring_next next_page; 5093 }; 5094 5095 5096 /* 5097 * Common event ring opcodes 5098 */ 5099 enum event_ring_opcode { 5100 EVENT_RING_OPCODE_VF_PF_CHANNEL, 5101 EVENT_RING_OPCODE_FUNCTION_START, 5102 EVENT_RING_OPCODE_FUNCTION_STOP, 5103 EVENT_RING_OPCODE_CFC_DEL, 5104 EVENT_RING_OPCODE_CFC_DEL_WB, 5105 EVENT_RING_OPCODE_STAT_QUERY, 5106 EVENT_RING_OPCODE_STOP_TRAFFIC, 5107 EVENT_RING_OPCODE_START_TRAFFIC, 5108 EVENT_RING_OPCODE_VF_FLR, 5109 EVENT_RING_OPCODE_MALICIOUS_VF, 5110 EVENT_RING_OPCODE_FORWARD_SETUP, 5111 EVENT_RING_OPCODE_RSS_UPDATE_RULES, 5112 EVENT_RING_OPCODE_FUNCTION_UPDATE, 5113 EVENT_RING_OPCODE_AFEX_VIF_LISTS, 5114 EVENT_RING_OPCODE_SET_MAC, 5115 EVENT_RING_OPCODE_CLASSIFICATION_RULES, 5116 EVENT_RING_OPCODE_FILTERS_RULES, 5117 EVENT_RING_OPCODE_MULTICAST_RULES, 5118 EVENT_RING_OPCODE_SET_TIMESYNC, 5119 MAX_EVENT_RING_OPCODE 5120 }; 5121 5122 /* 5123 * Modes for fairness algorithm 5124 */ 5125 enum fairness_mode { 5126 FAIRNESS_COS_WRR_MODE, 5127 FAIRNESS_COS_ETS_MODE, 5128 MAX_FAIRNESS_MODE 5129 }; 5130 5131 5132 /* 5133 * Priority and cos 5134 */ 5135 struct priority_cos { 5136 u8 priority; 5137 u8 cos; 5138 __le16 reserved1; 5139 }; 5140 5141 /* 5142 * The data for flow control configuration 5143 */ 5144 struct flow_control_configuration { 5145 struct priority_cos traffic_type_to_priority_cos[MAX_TRAFFIC_TYPES]; 5146 u8 dcb_enabled; 5147 u8 dcb_version; 5148 u8 dont_add_pri_0_en; 5149 u8 reserved1; 5150 __le32 reserved2; 5151 }; 5152 5153 5154 /* 5155 * 5156 */ 5157 struct function_start_data { 5158 u8 function_mode; 5159 u8 allow_npar_tx_switching; 5160 __le16 sd_vlan_tag; 5161 __le16 vif_id; 5162 u8 path_id; 5163 u8 network_cos_mode; 5164 u8 dmae_cmd_id; 5165 u8 gre_tunnel_mode; 5166 u8 gre_tunnel_rss; 5167 u8 nvgre_clss_en; 5168 __le16 reserved1[2]; 5169 }; 5170 5171 struct function_update_data { 5172 u8 vif_id_change_flg; 5173 u8 afex_default_vlan_change_flg; 5174 u8 allowed_priorities_change_flg; 5175 u8 network_cos_mode_change_flg; 5176 __le16 vif_id; 5177 __le16 afex_default_vlan; 5178 u8 allowed_priorities; 5179 u8 network_cos_mode; 5180 u8 lb_mode_en_change_flg; 5181 u8 lb_mode_en; 5182 u8 tx_switch_suspend_change_flg; 5183 u8 tx_switch_suspend; 5184 u8 echo; 5185 u8 reserved1; 5186 u8 update_gre_cfg_flg; 5187 u8 gre_tunnel_mode; 5188 u8 gre_tunnel_rss; 5189 u8 nvgre_clss_en; 5190 u32 reserved3; 5191 }; 5192 5193 /* 5194 * FW version stored in the Xstorm RAM 5195 */ 5196 struct fw_version { 5197 #if defined(__BIG_ENDIAN) 5198 u8 engineering; 5199 u8 revision; 5200 u8 minor; 5201 u8 major; 5202 #elif defined(__LITTLE_ENDIAN) 5203 u8 major; 5204 u8 minor; 5205 u8 revision; 5206 u8 engineering; 5207 #endif 5208 u32 flags; 5209 #define FW_VERSION_OPTIMIZED (0x1<<0) 5210 #define FW_VERSION_OPTIMIZED_SHIFT 0 5211 #define FW_VERSION_BIG_ENDIEN (0x1<<1) 5212 #define FW_VERSION_BIG_ENDIEN_SHIFT 1 5213 #define FW_VERSION_CHIP_VERSION (0x3<<2) 5214 #define FW_VERSION_CHIP_VERSION_SHIFT 2 5215 #define __FW_VERSION_RESERVED (0xFFFFFFF<<4) 5216 #define __FW_VERSION_RESERVED_SHIFT 4 5217 }; 5218 5219 /* GRE RSS Mode */ 5220 enum gre_rss_mode { 5221 GRE_OUTER_HEADERS_RSS, 5222 GRE_INNER_HEADERS_RSS, 5223 NVGRE_KEY_ENTROPY_RSS, 5224 MAX_GRE_RSS_MODE 5225 }; 5226 5227 /* GRE Tunnel Mode */ 5228 enum gre_tunnel_type { 5229 NO_GRE_TUNNEL, 5230 NVGRE_TUNNEL, 5231 L2GRE_TUNNEL, 5232 IPGRE_TUNNEL, 5233 MAX_GRE_TUNNEL_TYPE 5234 }; 5235 5236 /* 5237 * Dynamic Host-Coalescing - Driver(host) counters 5238 */ 5239 struct hc_dynamic_sb_drv_counters { 5240 u32 dynamic_hc_drv_counter[HC_SB_MAX_DYNAMIC_INDICES]; 5241 }; 5242 5243 5244 /* 5245 * 2 bytes. configuration/state parameters for a single protocol index 5246 */ 5247 struct hc_index_data { 5248 #if defined(__BIG_ENDIAN) 5249 u8 flags; 5250 #define HC_INDEX_DATA_SM_ID (0x1<<0) 5251 #define HC_INDEX_DATA_SM_ID_SHIFT 0 5252 #define HC_INDEX_DATA_HC_ENABLED (0x1<<1) 5253 #define HC_INDEX_DATA_HC_ENABLED_SHIFT 1 5254 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2) 5255 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2 5256 #define HC_INDEX_DATA_RESERVE (0x1F<<3) 5257 #define HC_INDEX_DATA_RESERVE_SHIFT 3 5258 u8 timeout; 5259 #elif defined(__LITTLE_ENDIAN) 5260 u8 timeout; 5261 u8 flags; 5262 #define HC_INDEX_DATA_SM_ID (0x1<<0) 5263 #define HC_INDEX_DATA_SM_ID_SHIFT 0 5264 #define HC_INDEX_DATA_HC_ENABLED (0x1<<1) 5265 #define HC_INDEX_DATA_HC_ENABLED_SHIFT 1 5266 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2) 5267 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2 5268 #define HC_INDEX_DATA_RESERVE (0x1F<<3) 5269 #define HC_INDEX_DATA_RESERVE_SHIFT 3 5270 #endif 5271 }; 5272 5273 5274 /* 5275 * HC state-machine 5276 */ 5277 struct hc_status_block_sm { 5278 #if defined(__BIG_ENDIAN) 5279 u8 igu_seg_id; 5280 u8 igu_sb_id; 5281 u8 timer_value; 5282 u8 __flags; 5283 #elif defined(__LITTLE_ENDIAN) 5284 u8 __flags; 5285 u8 timer_value; 5286 u8 igu_sb_id; 5287 u8 igu_seg_id; 5288 #endif 5289 u32 time_to_expire; 5290 }; 5291 5292 /* 5293 * hold PCI identification variables- used in various places in firmware 5294 */ 5295 struct pci_entity { 5296 #if defined(__BIG_ENDIAN) 5297 u8 vf_valid; 5298 u8 vf_id; 5299 u8 vnic_id; 5300 u8 pf_id; 5301 #elif defined(__LITTLE_ENDIAN) 5302 u8 pf_id; 5303 u8 vnic_id; 5304 u8 vf_id; 5305 u8 vf_valid; 5306 #endif 5307 }; 5308 5309 /* 5310 * The fast-path status block meta-data, common to all chips 5311 */ 5312 struct hc_sb_data { 5313 struct regpair_native host_sb_addr; 5314 struct hc_status_block_sm state_machine[HC_SB_MAX_SM]; 5315 struct pci_entity p_func; 5316 #if defined(__BIG_ENDIAN) 5317 u8 rsrv0; 5318 u8 state; 5319 u8 dhc_qzone_id; 5320 u8 same_igu_sb_1b; 5321 #elif defined(__LITTLE_ENDIAN) 5322 u8 same_igu_sb_1b; 5323 u8 dhc_qzone_id; 5324 u8 state; 5325 u8 rsrv0; 5326 #endif 5327 struct regpair_native rsrv1[2]; 5328 }; 5329 5330 5331 /* 5332 * Segment types for host coaslescing 5333 */ 5334 enum hc_segment { 5335 HC_REGULAR_SEGMENT, 5336 HC_DEFAULT_SEGMENT, 5337 MAX_HC_SEGMENT 5338 }; 5339 5340 5341 /* 5342 * The fast-path status block meta-data 5343 */ 5344 struct hc_sp_status_block_data { 5345 struct regpair_native host_sb_addr; 5346 #if defined(__BIG_ENDIAN) 5347 u8 rsrv1; 5348 u8 state; 5349 u8 igu_seg_id; 5350 u8 igu_sb_id; 5351 #elif defined(__LITTLE_ENDIAN) 5352 u8 igu_sb_id; 5353 u8 igu_seg_id; 5354 u8 state; 5355 u8 rsrv1; 5356 #endif 5357 struct pci_entity p_func; 5358 }; 5359 5360 5361 /* 5362 * The fast-path status block meta-data 5363 */ 5364 struct hc_status_block_data_e1x { 5365 struct hc_index_data index_data[HC_SB_MAX_INDICES_E1X]; 5366 struct hc_sb_data common; 5367 }; 5368 5369 5370 /* 5371 * The fast-path status block meta-data 5372 */ 5373 struct hc_status_block_data_e2 { 5374 struct hc_index_data index_data[HC_SB_MAX_INDICES_E2]; 5375 struct hc_sb_data common; 5376 }; 5377 5378 5379 /* 5380 * IGU block operartion modes (in Everest2) 5381 */ 5382 enum igu_mode { 5383 HC_IGU_BC_MODE, 5384 HC_IGU_NBC_MODE, 5385 MAX_IGU_MODE 5386 }; 5387 5388 5389 /* 5390 * IP versions 5391 */ 5392 enum ip_ver { 5393 IP_V4, 5394 IP_V6, 5395 MAX_IP_VER 5396 }; 5397 5398 /* 5399 * Malicious VF error ID 5400 */ 5401 enum malicious_vf_error_id { 5402 VF_PF_CHANNEL_NOT_READY, 5403 ETH_ILLEGAL_BD_LENGTHS, 5404 ETH_PACKET_TOO_SHORT, 5405 ETH_PAYLOAD_TOO_BIG, 5406 ETH_ILLEGAL_ETH_TYPE, 5407 ETH_ILLEGAL_LSO_HDR_LEN, 5408 ETH_TOO_MANY_BDS, 5409 ETH_ZERO_HDR_NBDS, 5410 ETH_START_BD_NOT_SET, 5411 ETH_ILLEGAL_PARSE_NBDS, 5412 ETH_IPV6_AND_CHECKSUM, 5413 ETH_VLAN_FLG_INCORRECT, 5414 ETH_ILLEGAL_LSO_MSS, 5415 ETH_TUNNEL_NOT_SUPPORTED, 5416 MAX_MALICIOUS_VF_ERROR_ID 5417 }; 5418 5419 /* 5420 * Multi-function modes 5421 */ 5422 enum mf_mode { 5423 SINGLE_FUNCTION, 5424 MULTI_FUNCTION_SD, 5425 MULTI_FUNCTION_SI, 5426 MULTI_FUNCTION_AFEX, 5427 MAX_MF_MODE 5428 }; 5429 5430 /* 5431 * Protocol-common statistics collected by the Tstorm (per pf) 5432 */ 5433 struct tstorm_per_pf_stats { 5434 struct regpair rcv_error_bytes; 5435 }; 5436 5437 /* 5438 * 5439 */ 5440 struct per_pf_stats { 5441 struct tstorm_per_pf_stats tstorm_pf_statistics; 5442 }; 5443 5444 5445 /* 5446 * Protocol-common statistics collected by the Tstorm (per port) 5447 */ 5448 struct tstorm_per_port_stats { 5449 __le32 mac_discard; 5450 __le32 mac_filter_discard; 5451 __le32 brb_truncate_discard; 5452 __le32 mf_tag_discard; 5453 __le32 packet_drop; 5454 __le32 reserved; 5455 }; 5456 5457 /* 5458 * 5459 */ 5460 struct per_port_stats { 5461 struct tstorm_per_port_stats tstorm_port_statistics; 5462 }; 5463 5464 5465 /* 5466 * Protocol-common statistics collected by the Tstorm (per client) 5467 */ 5468 struct tstorm_per_queue_stats { 5469 struct regpair rcv_ucast_bytes; 5470 __le32 rcv_ucast_pkts; 5471 __le32 checksum_discard; 5472 struct regpair rcv_bcast_bytes; 5473 __le32 rcv_bcast_pkts; 5474 __le32 pkts_too_big_discard; 5475 struct regpair rcv_mcast_bytes; 5476 __le32 rcv_mcast_pkts; 5477 __le32 ttl0_discard; 5478 __le16 no_buff_discard; 5479 __le16 reserved0; 5480 __le32 reserved1; 5481 }; 5482 5483 /* 5484 * Protocol-common statistics collected by the Ustorm (per client) 5485 */ 5486 struct ustorm_per_queue_stats { 5487 struct regpair ucast_no_buff_bytes; 5488 struct regpair mcast_no_buff_bytes; 5489 struct regpair bcast_no_buff_bytes; 5490 __le32 ucast_no_buff_pkts; 5491 __le32 mcast_no_buff_pkts; 5492 __le32 bcast_no_buff_pkts; 5493 __le32 coalesced_pkts; 5494 struct regpair coalesced_bytes; 5495 __le32 coalesced_events; 5496 __le32 coalesced_aborts; 5497 }; 5498 5499 /* 5500 * Protocol-common statistics collected by the Xstorm (per client) 5501 */ 5502 struct xstorm_per_queue_stats { 5503 struct regpair ucast_bytes_sent; 5504 struct regpair mcast_bytes_sent; 5505 struct regpair bcast_bytes_sent; 5506 __le32 ucast_pkts_sent; 5507 __le32 mcast_pkts_sent; 5508 __le32 bcast_pkts_sent; 5509 __le32 error_drop_pkts; 5510 }; 5511 5512 /* 5513 * 5514 */ 5515 struct per_queue_stats { 5516 struct tstorm_per_queue_stats tstorm_queue_statistics; 5517 struct ustorm_per_queue_stats ustorm_queue_statistics; 5518 struct xstorm_per_queue_stats xstorm_queue_statistics; 5519 }; 5520 5521 5522 /* 5523 * FW version stored in first line of pram 5524 */ 5525 struct pram_fw_version { 5526 u8 major; 5527 u8 minor; 5528 u8 revision; 5529 u8 engineering; 5530 u8 flags; 5531 #define PRAM_FW_VERSION_OPTIMIZED (0x1<<0) 5532 #define PRAM_FW_VERSION_OPTIMIZED_SHIFT 0 5533 #define PRAM_FW_VERSION_STORM_ID (0x3<<1) 5534 #define PRAM_FW_VERSION_STORM_ID_SHIFT 1 5535 #define PRAM_FW_VERSION_BIG_ENDIEN (0x1<<3) 5536 #define PRAM_FW_VERSION_BIG_ENDIEN_SHIFT 3 5537 #define PRAM_FW_VERSION_CHIP_VERSION (0x3<<4) 5538 #define PRAM_FW_VERSION_CHIP_VERSION_SHIFT 4 5539 #define __PRAM_FW_VERSION_RESERVED0 (0x3<<6) 5540 #define __PRAM_FW_VERSION_RESERVED0_SHIFT 6 5541 }; 5542 5543 5544 /* 5545 * Ethernet slow path element 5546 */ 5547 union protocol_common_specific_data { 5548 u8 protocol_data[8]; 5549 struct regpair phy_address; 5550 struct regpair mac_config_addr; 5551 struct afex_vif_list_ramrod_data afex_vif_list_data; 5552 }; 5553 5554 /* 5555 * The send queue element 5556 */ 5557 struct protocol_common_spe { 5558 struct spe_hdr hdr; 5559 union protocol_common_specific_data data; 5560 }; 5561 5562 /* 5563 * The send queue element 5564 */ 5565 struct slow_path_element { 5566 struct spe_hdr hdr; 5567 struct regpair protocol_data; 5568 }; 5569 5570 5571 /* 5572 * Protocol-common statistics counter 5573 */ 5574 struct stats_counter { 5575 __le16 xstats_counter; 5576 __le16 reserved0; 5577 __le32 reserved1; 5578 __le16 tstats_counter; 5579 __le16 reserved2; 5580 __le32 reserved3; 5581 __le16 ustats_counter; 5582 __le16 reserved4; 5583 __le32 reserved5; 5584 __le16 cstats_counter; 5585 __le16 reserved6; 5586 __le32 reserved7; 5587 }; 5588 5589 5590 /* 5591 * 5592 */ 5593 struct stats_query_entry { 5594 u8 kind; 5595 u8 index; 5596 __le16 funcID; 5597 __le32 reserved; 5598 struct regpair address; 5599 }; 5600 5601 /* 5602 * statistic command 5603 */ 5604 struct stats_query_cmd_group { 5605 struct stats_query_entry query[STATS_QUERY_CMD_COUNT]; 5606 }; 5607 5608 5609 /* 5610 * statistic command header 5611 */ 5612 struct stats_query_header { 5613 u8 cmd_num; 5614 u8 reserved0; 5615 __le16 drv_stats_counter; 5616 __le32 reserved1; 5617 struct regpair stats_counters_addrs; 5618 }; 5619 5620 5621 /* 5622 * Types of statistcis query entry 5623 */ 5624 enum stats_query_type { 5625 STATS_TYPE_QUEUE, 5626 STATS_TYPE_PORT, 5627 STATS_TYPE_PF, 5628 STATS_TYPE_TOE, 5629 STATS_TYPE_FCOE, 5630 MAX_STATS_QUERY_TYPE 5631 }; 5632 5633 5634 /* 5635 * Indicate of the function status block state 5636 */ 5637 enum status_block_state { 5638 SB_DISABLED, 5639 SB_ENABLED, 5640 SB_CLEANED, 5641 MAX_STATUS_BLOCK_STATE 5642 }; 5643 5644 5645 /* 5646 * Storm IDs (including attentions for IGU related enums) 5647 */ 5648 enum storm_id { 5649 USTORM_ID, 5650 CSTORM_ID, 5651 XSTORM_ID, 5652 TSTORM_ID, 5653 ATTENTION_ID, 5654 MAX_STORM_ID 5655 }; 5656 5657 5658 /* 5659 * Taffic types used in ETS and flow control algorithms 5660 */ 5661 enum traffic_type { 5662 LLFC_TRAFFIC_TYPE_NW, 5663 LLFC_TRAFFIC_TYPE_FCOE, 5664 LLFC_TRAFFIC_TYPE_ISCSI, 5665 MAX_TRAFFIC_TYPE 5666 }; 5667 5668 5669 /* 5670 * zone A per-queue data 5671 */ 5672 struct tstorm_queue_zone_data { 5673 struct regpair reserved[4]; 5674 }; 5675 5676 5677 /* 5678 * zone B per-VF data 5679 */ 5680 struct tstorm_vf_zone_data { 5681 struct regpair reserved; 5682 }; 5683 5684 5685 /* 5686 * zone A per-queue data 5687 */ 5688 struct ustorm_queue_zone_data { 5689 struct ustorm_eth_rx_producers eth_rx_producers; 5690 struct regpair reserved[3]; 5691 }; 5692 5693 5694 /* 5695 * zone B per-VF data 5696 */ 5697 struct ustorm_vf_zone_data { 5698 struct regpair reserved; 5699 }; 5700 5701 5702 /* 5703 * data per VF-PF channel 5704 */ 5705 struct vf_pf_channel_data { 5706 #if defined(__BIG_ENDIAN) 5707 u16 reserved0; 5708 u8 valid; 5709 u8 state; 5710 #elif defined(__LITTLE_ENDIAN) 5711 u8 state; 5712 u8 valid; 5713 u16 reserved0; 5714 #endif 5715 u32 reserved1; 5716 }; 5717 5718 5719 /* 5720 * State of VF-PF channel 5721 */ 5722 enum vf_pf_channel_state { 5723 VF_PF_CHANNEL_STATE_READY, 5724 VF_PF_CHANNEL_STATE_WAITING_FOR_ACK, 5725 MAX_VF_PF_CHANNEL_STATE 5726 }; 5727 5728 5729 /* 5730 * vif_list_rule_kind 5731 */ 5732 enum vif_list_rule_kind { 5733 VIF_LIST_RULE_SET, 5734 VIF_LIST_RULE_GET, 5735 VIF_LIST_RULE_CLEAR_ALL, 5736 VIF_LIST_RULE_CLEAR_FUNC, 5737 MAX_VIF_LIST_RULE_KIND 5738 }; 5739 5740 5741 /* 5742 * zone A per-queue data 5743 */ 5744 struct xstorm_queue_zone_data { 5745 struct regpair reserved[4]; 5746 }; 5747 5748 5749 /* 5750 * zone B per-VF data 5751 */ 5752 struct xstorm_vf_zone_data { 5753 struct regpair reserved; 5754 }; 5755 5756 #endif /* BNX2X_HSI_H */ 5757