1 /* bnx2x_hsi.h: Broadcom Everest network driver.
2  *
3  * Copyright (c) 2007-2013 Broadcom Corporation
4  *
5  * This program is free software; you can redistribute it and/or modify
6  * it under the terms of the GNU General Public License as published by
7  * the Free Software Foundation.
8  */
9 #ifndef BNX2X_HSI_H
10 #define BNX2X_HSI_H
11 
12 #include "bnx2x_fw_defs.h"
13 #include "bnx2x_mfw_req.h"
14 
15 #define FW_ENCODE_32BIT_PATTERN         0x1e1e1e1e
16 
17 struct license_key {
18 	u32 reserved[6];
19 
20 	u32 max_iscsi_conn;
21 #define BNX2X_MAX_ISCSI_TRGT_CONN_MASK	0xFFFF
22 #define BNX2X_MAX_ISCSI_TRGT_CONN_SHIFT	0
23 #define BNX2X_MAX_ISCSI_INIT_CONN_MASK	0xFFFF0000
24 #define BNX2X_MAX_ISCSI_INIT_CONN_SHIFT	16
25 
26 	u32 reserved_a;
27 
28 	u32 max_fcoe_conn;
29 #define BNX2X_MAX_FCOE_TRGT_CONN_MASK	0xFFFF
30 #define BNX2X_MAX_FCOE_TRGT_CONN_SHIFT	0
31 #define BNX2X_MAX_FCOE_INIT_CONN_MASK	0xFFFF0000
32 #define BNX2X_MAX_FCOE_INIT_CONN_SHIFT	16
33 
34 	u32 reserved_b[4];
35 };
36 
37 /****************************************************************************
38  * Shared HW configuration                                                  *
39  ****************************************************************************/
40 #define PIN_CFG_NA                          0x00000000
41 #define PIN_CFG_GPIO0_P0                    0x00000001
42 #define PIN_CFG_GPIO1_P0                    0x00000002
43 #define PIN_CFG_GPIO2_P0                    0x00000003
44 #define PIN_CFG_GPIO3_P0                    0x00000004
45 #define PIN_CFG_GPIO0_P1                    0x00000005
46 #define PIN_CFG_GPIO1_P1                    0x00000006
47 #define PIN_CFG_GPIO2_P1                    0x00000007
48 #define PIN_CFG_GPIO3_P1                    0x00000008
49 #define PIN_CFG_EPIO0                       0x00000009
50 #define PIN_CFG_EPIO1                       0x0000000a
51 #define PIN_CFG_EPIO2                       0x0000000b
52 #define PIN_CFG_EPIO3                       0x0000000c
53 #define PIN_CFG_EPIO4                       0x0000000d
54 #define PIN_CFG_EPIO5                       0x0000000e
55 #define PIN_CFG_EPIO6                       0x0000000f
56 #define PIN_CFG_EPIO7                       0x00000010
57 #define PIN_CFG_EPIO8                       0x00000011
58 #define PIN_CFG_EPIO9                       0x00000012
59 #define PIN_CFG_EPIO10                      0x00000013
60 #define PIN_CFG_EPIO11                      0x00000014
61 #define PIN_CFG_EPIO12                      0x00000015
62 #define PIN_CFG_EPIO13                      0x00000016
63 #define PIN_CFG_EPIO14                      0x00000017
64 #define PIN_CFG_EPIO15                      0x00000018
65 #define PIN_CFG_EPIO16                      0x00000019
66 #define PIN_CFG_EPIO17                      0x0000001a
67 #define PIN_CFG_EPIO18                      0x0000001b
68 #define PIN_CFG_EPIO19                      0x0000001c
69 #define PIN_CFG_EPIO20                      0x0000001d
70 #define PIN_CFG_EPIO21                      0x0000001e
71 #define PIN_CFG_EPIO22                      0x0000001f
72 #define PIN_CFG_EPIO23                      0x00000020
73 #define PIN_CFG_EPIO24                      0x00000021
74 #define PIN_CFG_EPIO25                      0x00000022
75 #define PIN_CFG_EPIO26                      0x00000023
76 #define PIN_CFG_EPIO27                      0x00000024
77 #define PIN_CFG_EPIO28                      0x00000025
78 #define PIN_CFG_EPIO29                      0x00000026
79 #define PIN_CFG_EPIO30                      0x00000027
80 #define PIN_CFG_EPIO31                      0x00000028
81 
82 /* EPIO definition */
83 #define EPIO_CFG_NA                         0x00000000
84 #define EPIO_CFG_EPIO0                      0x00000001
85 #define EPIO_CFG_EPIO1                      0x00000002
86 #define EPIO_CFG_EPIO2                      0x00000003
87 #define EPIO_CFG_EPIO3                      0x00000004
88 #define EPIO_CFG_EPIO4                      0x00000005
89 #define EPIO_CFG_EPIO5                      0x00000006
90 #define EPIO_CFG_EPIO6                      0x00000007
91 #define EPIO_CFG_EPIO7                      0x00000008
92 #define EPIO_CFG_EPIO8                      0x00000009
93 #define EPIO_CFG_EPIO9                      0x0000000a
94 #define EPIO_CFG_EPIO10                     0x0000000b
95 #define EPIO_CFG_EPIO11                     0x0000000c
96 #define EPIO_CFG_EPIO12                     0x0000000d
97 #define EPIO_CFG_EPIO13                     0x0000000e
98 #define EPIO_CFG_EPIO14                     0x0000000f
99 #define EPIO_CFG_EPIO15                     0x00000010
100 #define EPIO_CFG_EPIO16                     0x00000011
101 #define EPIO_CFG_EPIO17                     0x00000012
102 #define EPIO_CFG_EPIO18                     0x00000013
103 #define EPIO_CFG_EPIO19                     0x00000014
104 #define EPIO_CFG_EPIO20                     0x00000015
105 #define EPIO_CFG_EPIO21                     0x00000016
106 #define EPIO_CFG_EPIO22                     0x00000017
107 #define EPIO_CFG_EPIO23                     0x00000018
108 #define EPIO_CFG_EPIO24                     0x00000019
109 #define EPIO_CFG_EPIO25                     0x0000001a
110 #define EPIO_CFG_EPIO26                     0x0000001b
111 #define EPIO_CFG_EPIO27                     0x0000001c
112 #define EPIO_CFG_EPIO28                     0x0000001d
113 #define EPIO_CFG_EPIO29                     0x0000001e
114 #define EPIO_CFG_EPIO30                     0x0000001f
115 #define EPIO_CFG_EPIO31                     0x00000020
116 
117 struct mac_addr {
118 	u32 upper;
119 	u32 lower;
120 };
121 
122 struct shared_hw_cfg {			 /* NVRAM Offset */
123 	/* Up to 16 bytes of NULL-terminated string */
124 	u8  part_num[16];		    /* 0x104 */
125 
126 	u32 config;			/* 0x114 */
127 	#define SHARED_HW_CFG_MDIO_VOLTAGE_MASK             0x00000001
128 		#define SHARED_HW_CFG_MDIO_VOLTAGE_SHIFT             0
129 		#define SHARED_HW_CFG_MDIO_VOLTAGE_1_2V              0x00000000
130 		#define SHARED_HW_CFG_MDIO_VOLTAGE_2_5V              0x00000001
131 	#define SHARED_HW_CFG_MCP_RST_ON_CORE_RST_EN        0x00000002
132 
133 	#define SHARED_HW_CFG_PORT_SWAP                     0x00000004
134 
135 	#define SHARED_HW_CFG_BEACON_WOL_EN                 0x00000008
136 
137 	#define SHARED_HW_CFG_PCIE_GEN3_DISABLED            0x00000000
138 	#define SHARED_HW_CFG_PCIE_GEN3_ENABLED             0x00000010
139 
140 	#define SHARED_HW_CFG_MFW_SELECT_MASK               0x00000700
141 		#define SHARED_HW_CFG_MFW_SELECT_SHIFT               8
142 	/* Whatever MFW found in NVM
143 	   (if multiple found, priority order is: NC-SI, UMP, IPMI) */
144 		#define SHARED_HW_CFG_MFW_SELECT_DEFAULT             0x00000000
145 		#define SHARED_HW_CFG_MFW_SELECT_NC_SI               0x00000100
146 		#define SHARED_HW_CFG_MFW_SELECT_UMP                 0x00000200
147 		#define SHARED_HW_CFG_MFW_SELECT_IPMI                0x00000300
148 	/* Use SPIO4 as an arbiter between: 0-NC_SI, 1-IPMI
149 	  (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
150 		#define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_IPMI    0x00000400
151 	/* Use SPIO4 as an arbiter between: 0-UMP, 1-IPMI
152 	  (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
153 		#define SHARED_HW_CFG_MFW_SELECT_SPIO4_UMP_IPMI      0x00000500
154 	/* Use SPIO4 as an arbiter between: 0-NC-SI, 1-UMP
155 	  (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
156 		#define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_UMP     0x00000600
157 
158 	#define SHARED_HW_CFG_LED_MODE_MASK                 0x000f0000
159 		#define SHARED_HW_CFG_LED_MODE_SHIFT                 16
160 		#define SHARED_HW_CFG_LED_MAC1                       0x00000000
161 		#define SHARED_HW_CFG_LED_PHY1                       0x00010000
162 		#define SHARED_HW_CFG_LED_PHY2                       0x00020000
163 		#define SHARED_HW_CFG_LED_PHY3                       0x00030000
164 		#define SHARED_HW_CFG_LED_MAC2                       0x00040000
165 		#define SHARED_HW_CFG_LED_PHY4                       0x00050000
166 		#define SHARED_HW_CFG_LED_PHY5                       0x00060000
167 		#define SHARED_HW_CFG_LED_PHY6                       0x00070000
168 		#define SHARED_HW_CFG_LED_MAC3                       0x00080000
169 		#define SHARED_HW_CFG_LED_PHY7                       0x00090000
170 		#define SHARED_HW_CFG_LED_PHY9                       0x000a0000
171 		#define SHARED_HW_CFG_LED_PHY11                      0x000b0000
172 		#define SHARED_HW_CFG_LED_MAC4                       0x000c0000
173 		#define SHARED_HW_CFG_LED_PHY8                       0x000d0000
174 		#define SHARED_HW_CFG_LED_EXTPHY1                    0x000e0000
175 		#define SHARED_HW_CFG_LED_EXTPHY2                    0x000f0000
176 
177 
178 	#define SHARED_HW_CFG_AN_ENABLE_MASK                0x3f000000
179 		#define SHARED_HW_CFG_AN_ENABLE_SHIFT                24
180 		#define SHARED_HW_CFG_AN_ENABLE_CL37                 0x01000000
181 		#define SHARED_HW_CFG_AN_ENABLE_CL73                 0x02000000
182 		#define SHARED_HW_CFG_AN_ENABLE_BAM                  0x04000000
183 		#define SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION   0x08000000
184 		#define SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT  0x10000000
185 		#define SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY           0x20000000
186 
187 	#define SHARED_HW_CFG_SRIOV_MASK                    0x40000000
188 		#define SHARED_HW_CFG_SRIOV_DISABLED                 0x00000000
189 		#define SHARED_HW_CFG_SRIOV_ENABLED                  0x40000000
190 
191 	#define SHARED_HW_CFG_ATC_MASK                      0x80000000
192 		#define SHARED_HW_CFG_ATC_DISABLED                   0x00000000
193 		#define SHARED_HW_CFG_ATC_ENABLED                    0x80000000
194 
195 	u32 config2;			    /* 0x118 */
196 	/* one time auto detect grace period (in sec) */
197 	#define SHARED_HW_CFG_GRACE_PERIOD_MASK             0x000000ff
198 	#define SHARED_HW_CFG_GRACE_PERIOD_SHIFT                     0
199 
200 	#define SHARED_HW_CFG_PCIE_GEN2_ENABLED             0x00000100
201 	#define SHARED_HW_CFG_PCIE_GEN2_DISABLED            0x00000000
202 
203 	/* The default value for the core clock is 250MHz and it is
204 	   achieved by setting the clock change to 4 */
205 	#define SHARED_HW_CFG_CLOCK_CHANGE_MASK             0x00000e00
206 	#define SHARED_HW_CFG_CLOCK_CHANGE_SHIFT                     9
207 
208 	#define SHARED_HW_CFG_SMBUS_TIMING_MASK             0x00001000
209 		#define SHARED_HW_CFG_SMBUS_TIMING_100KHZ            0x00000000
210 		#define SHARED_HW_CFG_SMBUS_TIMING_400KHZ            0x00001000
211 
212 	#define SHARED_HW_CFG_HIDE_PORT1                    0x00002000
213 
214 	#define SHARED_HW_CFG_WOL_CAPABLE_MASK              0x00004000
215 		#define SHARED_HW_CFG_WOL_CAPABLE_DISABLED           0x00000000
216 		#define SHARED_HW_CFG_WOL_CAPABLE_ENABLED            0x00004000
217 
218 		/* Output low when PERST is asserted */
219 	#define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_MASK       0x00008000
220 		#define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_DISABLED    0x00000000
221 		#define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_ENABLED     0x00008000
222 
223 	#define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_MASK    0x00070000
224 		#define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_SHIFT    16
225 		#define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_HW       0x00000000
226 		#define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_0DB      0x00010000
227 		#define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_3_5DB    0x00020000
228 		#define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_6_0DB    0x00030000
229 
230 	/*  The fan failure mechanism is usually related to the PHY type
231 	      since the power consumption of the board is determined by the PHY.
232 	      Currently, fan is required for most designs with SFX7101, BCM8727
233 	      and BCM8481. If a fan is not required for a board which uses one
234 	      of those PHYs, this field should be set to "Disabled". If a fan is
235 	      required for a different PHY type, this option should be set to
236 	      "Enabled". The fan failure indication is expected on SPIO5 */
237 	#define SHARED_HW_CFG_FAN_FAILURE_MASK              0x00180000
238 		#define SHARED_HW_CFG_FAN_FAILURE_SHIFT              19
239 		#define SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE           0x00000000
240 		#define SHARED_HW_CFG_FAN_FAILURE_DISABLED           0x00080000
241 		#define SHARED_HW_CFG_FAN_FAILURE_ENABLED            0x00100000
242 
243 		/* ASPM Power Management support */
244 	#define SHARED_HW_CFG_ASPM_SUPPORT_MASK             0x00600000
245 		#define SHARED_HW_CFG_ASPM_SUPPORT_SHIFT             21
246 		#define SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_ENABLED    0x00000000
247 		#define SHARED_HW_CFG_ASPM_SUPPORT_L0S_DISABLED      0x00200000
248 		#define SHARED_HW_CFG_ASPM_SUPPORT_L1_DISABLED       0x00400000
249 		#define SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_DISABLED   0x00600000
250 
251 	/* The value of PM_TL_IGNORE_REQS (bit0) in PCI register
252 	   tl_control_0 (register 0x2800) */
253 	#define SHARED_HW_CFG_PREVENT_L1_ENTRY_MASK         0x00800000
254 		#define SHARED_HW_CFG_PREVENT_L1_ENTRY_DISABLED      0x00000000
255 		#define SHARED_HW_CFG_PREVENT_L1_ENTRY_ENABLED       0x00800000
256 
257 	#define SHARED_HW_CFG_PORT_MODE_MASK                0x01000000
258 		#define SHARED_HW_CFG_PORT_MODE_2                    0x00000000
259 		#define SHARED_HW_CFG_PORT_MODE_4                    0x01000000
260 
261 	#define SHARED_HW_CFG_PATH_SWAP_MASK                0x02000000
262 		#define SHARED_HW_CFG_PATH_SWAP_DISABLED             0x00000000
263 		#define SHARED_HW_CFG_PATH_SWAP_ENABLED              0x02000000
264 
265 	/*  Set the MDC/MDIO access for the first external phy */
266 	#define SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK         0x1C000000
267 		#define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT         26
268 		#define SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE      0x00000000
269 		#define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0         0x04000000
270 		#define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1         0x08000000
271 		#define SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH          0x0c000000
272 		#define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED       0x10000000
273 
274 	/*  Set the MDC/MDIO access for the second external phy */
275 	#define SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK         0xE0000000
276 		#define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT         29
277 		#define SHARED_HW_CFG_MDC_MDIO_ACCESS2_PHY_TYPE      0x00000000
278 		#define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC0         0x20000000
279 		#define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC1         0x40000000
280 		#define SHARED_HW_CFG_MDC_MDIO_ACCESS2_BOTH          0x60000000
281 		#define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SWAPPED       0x80000000
282 
283 	u32 config_3;				/* 0x11C */
284 	#define SHARED_HW_CFG_EXTENDED_MF_MODE_MASK         0x00000F00
285 		#define SHARED_HW_CFG_EXTENDED_MF_MODE_SHIFT              8
286 		#define SHARED_HW_CFG_EXTENDED_MF_MODE_NPAR1_DOT_5        0x00000000
287 		#define SHARED_HW_CFG_EXTENDED_MF_MODE_NPAR2_DOT_0        0x00000100
288 
289 	u32 ump_nc_si_config;			/* 0x120 */
290 	#define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MASK       0x00000003
291 		#define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_SHIFT       0
292 		#define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MAC         0x00000000
293 		#define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_PHY         0x00000001
294 		#define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MII         0x00000000
295 		#define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_RMII        0x00000002
296 
297 	#define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_MASK       0x00000f00
298 		#define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_SHIFT       8
299 
300 	#define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_MASK   0x00ff0000
301 		#define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_SHIFT   16
302 		#define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_NONE    0x00000000
303 		#define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_BCM5221 0x00010000
304 
305 	u32 board;			/* 0x124 */
306 	#define SHARED_HW_CFG_E3_I2C_MUX0_MASK              0x0000003F
307 	#define SHARED_HW_CFG_E3_I2C_MUX0_SHIFT                      0
308 	#define SHARED_HW_CFG_E3_I2C_MUX1_MASK              0x00000FC0
309 	#define SHARED_HW_CFG_E3_I2C_MUX1_SHIFT                      6
310 	/* Use the PIN_CFG_XXX defines on top */
311 	#define SHARED_HW_CFG_BOARD_REV_MASK                0x00ff0000
312 	#define SHARED_HW_CFG_BOARD_REV_SHIFT                        16
313 
314 	#define SHARED_HW_CFG_BOARD_MAJOR_VER_MASK          0x0f000000
315 	#define SHARED_HW_CFG_BOARD_MAJOR_VER_SHIFT                  24
316 
317 	#define SHARED_HW_CFG_BOARD_MINOR_VER_MASK          0xf0000000
318 	#define SHARED_HW_CFG_BOARD_MINOR_VER_SHIFT                  28
319 
320 	u32 wc_lane_config;				    /* 0x128 */
321 	#define SHARED_HW_CFG_LANE_SWAP_CFG_MASK            0x0000FFFF
322 		#define SHARED_HW_CFG_LANE_SWAP_CFG_SHIFT            0
323 		#define SHARED_HW_CFG_LANE_SWAP_CFG_32103210         0x00001b1b
324 		#define SHARED_HW_CFG_LANE_SWAP_CFG_32100123         0x00001be4
325 		#define SHARED_HW_CFG_LANE_SWAP_CFG_01233210         0x0000e41b
326 		#define SHARED_HW_CFG_LANE_SWAP_CFG_01230123         0x0000e4e4
327 	#define SHARED_HW_CFG_LANE_SWAP_CFG_TX_MASK         0x000000FF
328 	#define SHARED_HW_CFG_LANE_SWAP_CFG_TX_SHIFT                 0
329 	#define SHARED_HW_CFG_LANE_SWAP_CFG_RX_MASK         0x0000FF00
330 	#define SHARED_HW_CFG_LANE_SWAP_CFG_RX_SHIFT                 8
331 
332 	/* TX lane Polarity swap */
333 	#define SHARED_HW_CFG_TX_LANE0_POL_FLIP_ENABLED     0x00010000
334 	#define SHARED_HW_CFG_TX_LANE1_POL_FLIP_ENABLED     0x00020000
335 	#define SHARED_HW_CFG_TX_LANE2_POL_FLIP_ENABLED     0x00040000
336 	#define SHARED_HW_CFG_TX_LANE3_POL_FLIP_ENABLED     0x00080000
337 	/* TX lane Polarity swap */
338 	#define SHARED_HW_CFG_RX_LANE0_POL_FLIP_ENABLED     0x00100000
339 	#define SHARED_HW_CFG_RX_LANE1_POL_FLIP_ENABLED     0x00200000
340 	#define SHARED_HW_CFG_RX_LANE2_POL_FLIP_ENABLED     0x00400000
341 	#define SHARED_HW_CFG_RX_LANE3_POL_FLIP_ENABLED     0x00800000
342 
343 	/*  Selects the port layout of the board */
344 	#define SHARED_HW_CFG_E3_PORT_LAYOUT_MASK           0x0F000000
345 		#define SHARED_HW_CFG_E3_PORT_LAYOUT_SHIFT           24
346 		#define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_01           0x00000000
347 		#define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_10           0x01000000
348 		#define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_0123         0x02000000
349 		#define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_1032         0x03000000
350 		#define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_2301         0x04000000
351 		#define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_3210         0x05000000
352 };
353 
354 
355 /****************************************************************************
356  * Port HW configuration                                                    *
357  ****************************************************************************/
358 struct port_hw_cfg {		    /* port 0: 0x12c  port 1: 0x2bc */
359 
360 	u32 pci_id;
361 	#define PORT_HW_CFG_PCI_VENDOR_ID_MASK              0xffff0000
362 	#define PORT_HW_CFG_PCI_DEVICE_ID_MASK              0x0000ffff
363 
364 	u32 pci_sub_id;
365 	#define PORT_HW_CFG_PCI_SUBSYS_DEVICE_ID_MASK       0xffff0000
366 	#define PORT_HW_CFG_PCI_SUBSYS_VENDOR_ID_MASK       0x0000ffff
367 
368 	u32 power_dissipated;
369 	#define PORT_HW_CFG_POWER_DIS_D0_MASK               0x000000ff
370 	#define PORT_HW_CFG_POWER_DIS_D0_SHIFT                       0
371 	#define PORT_HW_CFG_POWER_DIS_D1_MASK               0x0000ff00
372 	#define PORT_HW_CFG_POWER_DIS_D1_SHIFT                       8
373 	#define PORT_HW_CFG_POWER_DIS_D2_MASK               0x00ff0000
374 	#define PORT_HW_CFG_POWER_DIS_D2_SHIFT                       16
375 	#define PORT_HW_CFG_POWER_DIS_D3_MASK               0xff000000
376 	#define PORT_HW_CFG_POWER_DIS_D3_SHIFT                       24
377 
378 	u32 power_consumed;
379 	#define PORT_HW_CFG_POWER_CONS_D0_MASK              0x000000ff
380 	#define PORT_HW_CFG_POWER_CONS_D0_SHIFT                      0
381 	#define PORT_HW_CFG_POWER_CONS_D1_MASK              0x0000ff00
382 	#define PORT_HW_CFG_POWER_CONS_D1_SHIFT                      8
383 	#define PORT_HW_CFG_POWER_CONS_D2_MASK              0x00ff0000
384 	#define PORT_HW_CFG_POWER_CONS_D2_SHIFT                      16
385 	#define PORT_HW_CFG_POWER_CONS_D3_MASK              0xff000000
386 	#define PORT_HW_CFG_POWER_CONS_D3_SHIFT                      24
387 
388 	u32 mac_upper;
389 	#define PORT_HW_CFG_UPPERMAC_MASK                   0x0000ffff
390 	#define PORT_HW_CFG_UPPERMAC_SHIFT                           0
391 	u32 mac_lower;
392 
393 	u32 iscsi_mac_upper;  /* Upper 16 bits are always zeroes */
394 	u32 iscsi_mac_lower;
395 
396 	u32 rdma_mac_upper;   /* Upper 16 bits are always zeroes */
397 	u32 rdma_mac_lower;
398 
399 	u32 serdes_config;
400 	#define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_MASK 0x0000ffff
401 	#define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_SHIFT         0
402 
403 	#define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK    0xffff0000
404 	#define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT            16
405 
406 
407 	/*  Default values: 2P-64, 4P-32 */
408 	u32 pf_config;					    /* 0x158 */
409 	#define PORT_HW_CFG_PF_NUM_VF_MASK                  0x0000007F
410 	#define PORT_HW_CFG_PF_NUM_VF_SHIFT                          0
411 
412 	/*  Default values: 17 */
413 	#define PORT_HW_CFG_PF_NUM_MSIX_VECTORS_MASK        0x00007F00
414 	#define PORT_HW_CFG_PF_NUM_MSIX_VECTORS_SHIFT                8
415 
416 	#define PORT_HW_CFG_ENABLE_FLR_MASK                 0x00010000
417 	#define PORT_HW_CFG_FLR_ENABLED                     0x00010000
418 
419 	u32 vf_config;					    /* 0x15C */
420 	#define PORT_HW_CFG_VF_NUM_MSIX_VECTORS_MASK        0x0000007F
421 	#define PORT_HW_CFG_VF_NUM_MSIX_VECTORS_SHIFT                0
422 
423 	#define PORT_HW_CFG_VF_PCI_DEVICE_ID_MASK           0xFFFF0000
424 	#define PORT_HW_CFG_VF_PCI_DEVICE_ID_SHIFT                   16
425 
426 	u32 mf_pci_id;					    /* 0x160 */
427 	#define PORT_HW_CFG_MF_PCI_DEVICE_ID_MASK           0x0000FFFF
428 	#define PORT_HW_CFG_MF_PCI_DEVICE_ID_SHIFT                   0
429 
430 	/*  Controls the TX laser of the SFP+ module */
431 	u32 sfp_ctrl;					    /* 0x164 */
432 	#define PORT_HW_CFG_TX_LASER_MASK                   0x000000FF
433 		#define PORT_HW_CFG_TX_LASER_SHIFT                   0
434 		#define PORT_HW_CFG_TX_LASER_MDIO                    0x00000000
435 		#define PORT_HW_CFG_TX_LASER_GPIO0                   0x00000001
436 		#define PORT_HW_CFG_TX_LASER_GPIO1                   0x00000002
437 		#define PORT_HW_CFG_TX_LASER_GPIO2                   0x00000003
438 		#define PORT_HW_CFG_TX_LASER_GPIO3                   0x00000004
439 
440 	/*  Controls the fault module LED of the SFP+ */
441 	#define PORT_HW_CFG_FAULT_MODULE_LED_MASK           0x0000FF00
442 		#define PORT_HW_CFG_FAULT_MODULE_LED_SHIFT           8
443 		#define PORT_HW_CFG_FAULT_MODULE_LED_GPIO0           0x00000000
444 		#define PORT_HW_CFG_FAULT_MODULE_LED_GPIO1           0x00000100
445 		#define PORT_HW_CFG_FAULT_MODULE_LED_GPIO2           0x00000200
446 		#define PORT_HW_CFG_FAULT_MODULE_LED_GPIO3           0x00000300
447 		#define PORT_HW_CFG_FAULT_MODULE_LED_DISABLED        0x00000400
448 
449 	/*  The output pin TX_DIS that controls the TX laser of the SFP+
450 	  module. Use the PIN_CFG_XXX defines on top */
451 	u32 e3_sfp_ctrl;				    /* 0x168 */
452 	#define PORT_HW_CFG_E3_TX_LASER_MASK                0x000000FF
453 	#define PORT_HW_CFG_E3_TX_LASER_SHIFT                        0
454 
455 	/*  The output pin for SFPP_TYPE which turns on the Fault module LED */
456 	#define PORT_HW_CFG_E3_FAULT_MDL_LED_MASK           0x0000FF00
457 	#define PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT                   8
458 
459 	/*  The input pin MOD_ABS that indicates whether SFP+ module is
460 	  present or not. Use the PIN_CFG_XXX defines on top */
461 	#define PORT_HW_CFG_E3_MOD_ABS_MASK                 0x00FF0000
462 	#define PORT_HW_CFG_E3_MOD_ABS_SHIFT                         16
463 
464 	/*  The output pin PWRDIS_SFP_X which disable the power of the SFP+
465 	  module. Use the PIN_CFG_XXX defines on top */
466 	#define PORT_HW_CFG_E3_PWR_DIS_MASK                 0xFF000000
467 	#define PORT_HW_CFG_E3_PWR_DIS_SHIFT                         24
468 
469 	/*
470 	 * The input pin which signals module transmit fault. Use the
471 	 * PIN_CFG_XXX defines on top
472 	 */
473 	u32 e3_cmn_pin_cfg;				    /* 0x16C */
474 	#define PORT_HW_CFG_E3_TX_FAULT_MASK                0x000000FF
475 	#define PORT_HW_CFG_E3_TX_FAULT_SHIFT                        0
476 
477 	/*  The output pin which reset the PHY. Use the PIN_CFG_XXX defines on
478 	 top */
479 	#define PORT_HW_CFG_E3_PHY_RESET_MASK               0x0000FF00
480 	#define PORT_HW_CFG_E3_PHY_RESET_SHIFT                       8
481 
482 	/*
483 	 * The output pin which powers down the PHY. Use the PIN_CFG_XXX
484 	 * defines on top
485 	 */
486 	#define PORT_HW_CFG_E3_PWR_DOWN_MASK                0x00FF0000
487 	#define PORT_HW_CFG_E3_PWR_DOWN_SHIFT                        16
488 
489 	/*  The output pin values BSC_SEL which selects the I2C for this port
490 	  in the I2C Mux */
491 	#define PORT_HW_CFG_E3_I2C_MUX0_MASK                0x01000000
492 	#define PORT_HW_CFG_E3_I2C_MUX1_MASK                0x02000000
493 
494 
495 	/*
496 	 * The input pin I_FAULT which indicate over-current has occurred.
497 	 * Use the PIN_CFG_XXX defines on top
498 	 */
499 	u32 e3_cmn_pin_cfg1;				    /* 0x170 */
500 	#define PORT_HW_CFG_E3_OVER_CURRENT_MASK            0x000000FF
501 	#define PORT_HW_CFG_E3_OVER_CURRENT_SHIFT                    0
502 
503 	/*  pause on host ring */
504 	u32 generic_features;                               /* 0x174 */
505 	#define PORT_HW_CFG_PAUSE_ON_HOST_RING_MASK                   0x00000001
506 	#define PORT_HW_CFG_PAUSE_ON_HOST_RING_SHIFT                  0
507 	#define PORT_HW_CFG_PAUSE_ON_HOST_RING_DISABLED               0x00000000
508 	#define PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED                0x00000001
509 
510 	/* SFP+ Tx Equalization: NIC recommended and tested value is 0xBEB2
511 	 * LOM recommended and tested value is 0xBEB2. Using a different
512 	 * value means using a value not tested by BRCM
513 	 */
514 	u32 sfi_tap_values;                                 /* 0x178 */
515 	#define PORT_HW_CFG_TX_EQUALIZATION_MASK                      0x0000FFFF
516 	#define PORT_HW_CFG_TX_EQUALIZATION_SHIFT                     0
517 
518 	/* SFP+ Tx driver broadcast IDRIVER: NIC recommended and tested
519 	 * value is 0x2. LOM recommended and tested value is 0x2. Using a
520 	 * different value means using a value not tested by BRCM
521 	 */
522 	#define PORT_HW_CFG_TX_DRV_BROADCAST_MASK                     0x000F0000
523 	#define PORT_HW_CFG_TX_DRV_BROADCAST_SHIFT                    16
524 	/*  Set non-default values for TXFIR in SFP mode. */
525 	#define PORT_HW_CFG_TX_DRV_IFIR_MASK                          0x00F00000
526 	#define PORT_HW_CFG_TX_DRV_IFIR_SHIFT                         20
527 
528 	/*  Set non-default values for IPREDRIVER in SFP mode. */
529 	#define PORT_HW_CFG_TX_DRV_IPREDRIVER_MASK                    0x0F000000
530 	#define PORT_HW_CFG_TX_DRV_IPREDRIVER_SHIFT                   24
531 
532 	/*  Set non-default values for POST2 in SFP mode. */
533 	#define PORT_HW_CFG_TX_DRV_POST2_MASK                         0xF0000000
534 	#define PORT_HW_CFG_TX_DRV_POST2_SHIFT                        28
535 
536 	u32 reserved0[5];				    /* 0x17c */
537 
538 	u32 aeu_int_mask;				    /* 0x190 */
539 
540 	u32 media_type;					    /* 0x194 */
541 	#define PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK            0x000000FF
542 	#define PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT                    0
543 
544 	#define PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK            0x0000FF00
545 	#define PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT                    8
546 
547 	#define PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK            0x00FF0000
548 	#define PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT                    16
549 
550 	/*  4 times 16 bits for all 4 lanes. In case external PHY is present
551 	      (not direct mode), those values will not take effect on the 4 XGXS
552 	      lanes. For some external PHYs (such as 8706 and 8726) the values
553 	      will be used to configure the external PHY  in those cases, not
554 	      all 4 values are needed. */
555 	u16 xgxs_config_rx[4];			/* 0x198 */
556 	u16 xgxs_config_tx[4];			/* 0x1A0 */
557 
558 	/* For storing FCOE mac on shared memory */
559 	u32 fcoe_fip_mac_upper;
560 	#define PORT_HW_CFG_FCOE_UPPERMAC_MASK              0x0000ffff
561 	#define PORT_HW_CFG_FCOE_UPPERMAC_SHIFT                      0
562 	u32 fcoe_fip_mac_lower;
563 
564 	u32 fcoe_wwn_port_name_upper;
565 	u32 fcoe_wwn_port_name_lower;
566 
567 	u32 fcoe_wwn_node_name_upper;
568 	u32 fcoe_wwn_node_name_lower;
569 
570 	u32 Reserved1[49];				    /* 0x1C0 */
571 
572 	/*  Enable RJ45 magjack pair swapping on 10GBase-T PHY (0=default),
573 	      84833 only */
574 	u32 xgbt_phy_cfg;				    /* 0x284 */
575 	#define PORT_HW_CFG_RJ45_PAIR_SWAP_MASK             0x000000FF
576 	#define PORT_HW_CFG_RJ45_PAIR_SWAP_SHIFT                     0
577 
578 		u32 default_cfg;			    /* 0x288 */
579 	#define PORT_HW_CFG_GPIO0_CONFIG_MASK               0x00000003
580 		#define PORT_HW_CFG_GPIO0_CONFIG_SHIFT               0
581 		#define PORT_HW_CFG_GPIO0_CONFIG_NA                  0x00000000
582 		#define PORT_HW_CFG_GPIO0_CONFIG_LOW                 0x00000001
583 		#define PORT_HW_CFG_GPIO0_CONFIG_HIGH                0x00000002
584 		#define PORT_HW_CFG_GPIO0_CONFIG_INPUT               0x00000003
585 
586 	#define PORT_HW_CFG_GPIO1_CONFIG_MASK               0x0000000C
587 		#define PORT_HW_CFG_GPIO1_CONFIG_SHIFT               2
588 		#define PORT_HW_CFG_GPIO1_CONFIG_NA                  0x00000000
589 		#define PORT_HW_CFG_GPIO1_CONFIG_LOW                 0x00000004
590 		#define PORT_HW_CFG_GPIO1_CONFIG_HIGH                0x00000008
591 		#define PORT_HW_CFG_GPIO1_CONFIG_INPUT               0x0000000c
592 
593 	#define PORT_HW_CFG_GPIO2_CONFIG_MASK               0x00000030
594 		#define PORT_HW_CFG_GPIO2_CONFIG_SHIFT               4
595 		#define PORT_HW_CFG_GPIO2_CONFIG_NA                  0x00000000
596 		#define PORT_HW_CFG_GPIO2_CONFIG_LOW                 0x00000010
597 		#define PORT_HW_CFG_GPIO2_CONFIG_HIGH                0x00000020
598 		#define PORT_HW_CFG_GPIO2_CONFIG_INPUT               0x00000030
599 
600 	#define PORT_HW_CFG_GPIO3_CONFIG_MASK               0x000000C0
601 		#define PORT_HW_CFG_GPIO3_CONFIG_SHIFT               6
602 		#define PORT_HW_CFG_GPIO3_CONFIG_NA                  0x00000000
603 		#define PORT_HW_CFG_GPIO3_CONFIG_LOW                 0x00000040
604 		#define PORT_HW_CFG_GPIO3_CONFIG_HIGH                0x00000080
605 		#define PORT_HW_CFG_GPIO3_CONFIG_INPUT               0x000000c0
606 
607 	/*  When KR link is required to be set to force which is not
608 	      KR-compliant, this parameter determine what is the trigger for it.
609 	      When GPIO is selected, low input will force the speed. Currently
610 	      default speed is 1G. In the future, it may be widen to select the
611 	      forced speed in with another parameter. Note when force-1G is
612 	      enabled, it override option 56: Link Speed option. */
613 	#define PORT_HW_CFG_FORCE_KR_ENABLER_MASK           0x00000F00
614 		#define PORT_HW_CFG_FORCE_KR_ENABLER_SHIFT           8
615 		#define PORT_HW_CFG_FORCE_KR_ENABLER_NOT_FORCED      0x00000000
616 		#define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P0        0x00000100
617 		#define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P0        0x00000200
618 		#define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P0        0x00000300
619 		#define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P0        0x00000400
620 		#define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P1        0x00000500
621 		#define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P1        0x00000600
622 		#define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P1        0x00000700
623 		#define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P1        0x00000800
624 		#define PORT_HW_CFG_FORCE_KR_ENABLER_FORCED          0x00000900
625 	/*  Enable to determine with which GPIO to reset the external phy */
626 	#define PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK           0x000F0000
627 		#define PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT           16
628 		#define PORT_HW_CFG_EXT_PHY_GPIO_RST_PHY_TYPE        0x00000000
629 		#define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0        0x00010000
630 		#define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0        0x00020000
631 		#define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0        0x00030000
632 		#define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0        0x00040000
633 		#define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1        0x00050000
634 		#define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1        0x00060000
635 		#define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1        0x00070000
636 		#define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1        0x00080000
637 
638 	/*  Enable BAM on KR */
639 	#define PORT_HW_CFG_ENABLE_BAM_ON_KR_MASK           0x00100000
640 	#define PORT_HW_CFG_ENABLE_BAM_ON_KR_SHIFT                   20
641 	#define PORT_HW_CFG_ENABLE_BAM_ON_KR_DISABLED                0x00000000
642 	#define PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED                 0x00100000
643 
644 	/*  Enable Common Mode Sense */
645 	#define PORT_HW_CFG_ENABLE_CMS_MASK                 0x00200000
646 	#define PORT_HW_CFG_ENABLE_CMS_SHIFT                         21
647 	#define PORT_HW_CFG_ENABLE_CMS_DISABLED                      0x00000000
648 	#define PORT_HW_CFG_ENABLE_CMS_ENABLED                       0x00200000
649 
650 	/*  Determine the Serdes electrical interface   */
651 	#define PORT_HW_CFG_NET_SERDES_IF_MASK              0x0F000000
652 	#define PORT_HW_CFG_NET_SERDES_IF_SHIFT                      24
653 	#define PORT_HW_CFG_NET_SERDES_IF_SGMII                      0x00000000
654 	#define PORT_HW_CFG_NET_SERDES_IF_XFI                        0x01000000
655 	#define PORT_HW_CFG_NET_SERDES_IF_SFI                        0x02000000
656 	#define PORT_HW_CFG_NET_SERDES_IF_KR                         0x03000000
657 	#define PORT_HW_CFG_NET_SERDES_IF_DXGXS                      0x04000000
658 	#define PORT_HW_CFG_NET_SERDES_IF_KR2                        0x05000000
659 
660 
661 	u32 speed_capability_mask2;			    /* 0x28C */
662 	#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_MASK       0x0000FFFF
663 		#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_SHIFT       0
664 		#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10M_FULL    0x00000001
665 		#define PORT_HW_CFG_SPEED_CAPABILITY2_D3__           0x00000002
666 		#define PORT_HW_CFG_SPEED_CAPABILITY2_D3___          0x00000004
667 		#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_100M_FULL   0x00000008
668 		#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_1G          0x00000010
669 		#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_2_DOT_5G    0x00000020
670 		#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10G         0x00000040
671 		#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_20G         0x00000080
672 
673 	#define PORT_HW_CFG_SPEED_CAPABILITY2_D0_MASK       0xFFFF0000
674 		#define PORT_HW_CFG_SPEED_CAPABILITY2_D0_SHIFT       16
675 		#define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10M_FULL    0x00010000
676 		#define PORT_HW_CFG_SPEED_CAPABILITY2_D0__           0x00020000
677 		#define PORT_HW_CFG_SPEED_CAPABILITY2_D0___          0x00040000
678 		#define PORT_HW_CFG_SPEED_CAPABILITY2_D0_100M_FULL   0x00080000
679 		#define PORT_HW_CFG_SPEED_CAPABILITY2_D0_1G          0x00100000
680 		#define PORT_HW_CFG_SPEED_CAPABILITY2_D0_2_DOT_5G    0x00200000
681 		#define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10G         0x00400000
682 		#define PORT_HW_CFG_SPEED_CAPABILITY2_D0_20G         0x00800000
683 
684 
685 	/*  In the case where two media types (e.g. copper and fiber) are
686 	      present and electrically active at the same time, PHY Selection
687 	      will determine which of the two PHYs will be designated as the
688 	      Active PHY and used for a connection to the network.  */
689 	u32 multi_phy_config;				    /* 0x290 */
690 	#define PORT_HW_CFG_PHY_SELECTION_MASK              0x00000007
691 		#define PORT_HW_CFG_PHY_SELECTION_SHIFT              0
692 		#define PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT   0x00000000
693 		#define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY          0x00000001
694 		#define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY         0x00000002
695 		#define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY 0x00000003
696 		#define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY 0x00000004
697 
698 	/*  When enabled, all second phy nvram parameters will be swapped
699 	      with the first phy parameters */
700 	#define PORT_HW_CFG_PHY_SWAPPED_MASK                0x00000008
701 		#define PORT_HW_CFG_PHY_SWAPPED_SHIFT                3
702 		#define PORT_HW_CFG_PHY_SWAPPED_DISABLED             0x00000000
703 		#define PORT_HW_CFG_PHY_SWAPPED_ENABLED              0x00000008
704 
705 
706 	/*  Address of the second external phy */
707 	u32 external_phy_config2;			    /* 0x294 */
708 	#define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_MASK         0x000000FF
709 	#define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_SHIFT                 0
710 
711 	/*  The second XGXS external PHY type */
712 	#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_MASK         0x0000FF00
713 		#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SHIFT         8
714 		#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_DIRECT        0x00000000
715 		#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8071       0x00000100
716 		#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8072       0x00000200
717 		#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8073       0x00000300
718 		#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8705       0x00000400
719 		#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8706       0x00000500
720 		#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8726       0x00000600
721 		#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8481       0x00000700
722 		#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SFX7101       0x00000800
723 		#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727       0x00000900
724 		#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727_NOC   0x00000a00
725 		#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84823      0x00000b00
726 		#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54640      0x00000c00
727 		#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84833      0x00000d00
728 		#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54618SE    0x00000e00
729 		#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8722       0x00000f00
730 		#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54616      0x00001000
731 		#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84834      0x00001100
732 		#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_FAILURE       0x0000fd00
733 		#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_NOT_CONN      0x0000ff00
734 
735 
736 	/*  4 times 16 bits for all 4 lanes. For some external PHYs (such as
737 	      8706, 8726 and 8727) not all 4 values are needed. */
738 	u16 xgxs_config2_rx[4];				    /* 0x296 */
739 	u16 xgxs_config2_tx[4];				    /* 0x2A0 */
740 
741 	u32 lane_config;
742 	#define PORT_HW_CFG_LANE_SWAP_CFG_MASK              0x0000ffff
743 		#define PORT_HW_CFG_LANE_SWAP_CFG_SHIFT              0
744 		/* AN and forced */
745 		#define PORT_HW_CFG_LANE_SWAP_CFG_01230123           0x00001b1b
746 		/* forced only */
747 		#define PORT_HW_CFG_LANE_SWAP_CFG_01233210           0x00001be4
748 		/* forced only */
749 		#define PORT_HW_CFG_LANE_SWAP_CFG_31203120           0x0000d8d8
750 		/* forced only */
751 		#define PORT_HW_CFG_LANE_SWAP_CFG_32103210           0x0000e4e4
752 	#define PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK           0x000000ff
753 	#define PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT                   0
754 	#define PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK           0x0000ff00
755 	#define PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT                   8
756 	#define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK       0x0000c000
757 	#define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT               14
758 
759 	/*  Indicate whether to swap the external phy polarity */
760 	#define PORT_HW_CFG_SWAP_PHY_POLARITY_MASK          0x00010000
761 		#define PORT_HW_CFG_SWAP_PHY_POLARITY_DISABLED       0x00000000
762 		#define PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED        0x00010000
763 
764 
765 	u32 external_phy_config;
766 	#define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK          0x000000ff
767 	#define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT                  0
768 
769 	#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK          0x0000ff00
770 		#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SHIFT          8
771 		#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT         0x00000000
772 		#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8071        0x00000100
773 		#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072        0x00000200
774 		#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073        0x00000300
775 		#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705        0x00000400
776 		#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706        0x00000500
777 		#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726        0x00000600
778 		#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481        0x00000700
779 		#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101        0x00000800
780 		#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727        0x00000900
781 		#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC    0x00000a00
782 		#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823       0x00000b00
783 		#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54640       0x00000c00
784 		#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833       0x00000d00
785 		#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE     0x00000e00
786 		#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722        0x00000f00
787 		#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616       0x00001000
788 		#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834       0x00001100
789 		#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT_WC      0x0000fc00
790 		#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE        0x0000fd00
791 		#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN       0x0000ff00
792 
793 	#define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK        0x00ff0000
794 	#define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_SHIFT                16
795 
796 	#define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK        0xff000000
797 		#define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_SHIFT        24
798 		#define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT       0x00000000
799 		#define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482      0x01000000
800 		#define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD    0x02000000
801 		#define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN     0xff000000
802 
803 	u32 speed_capability_mask;
804 	#define PORT_HW_CFG_SPEED_CAPABILITY_D3_MASK        0x0000ffff
805 		#define PORT_HW_CFG_SPEED_CAPABILITY_D3_SHIFT        0
806 		#define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_FULL     0x00000001
807 		#define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_HALF     0x00000002
808 		#define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_HALF    0x00000004
809 		#define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_FULL    0x00000008
810 		#define PORT_HW_CFG_SPEED_CAPABILITY_D3_1G           0x00000010
811 		#define PORT_HW_CFG_SPEED_CAPABILITY_D3_2_5G         0x00000020
812 		#define PORT_HW_CFG_SPEED_CAPABILITY_D3_10G          0x00000040
813 		#define PORT_HW_CFG_SPEED_CAPABILITY_D3_20G          0x00000080
814 		#define PORT_HW_CFG_SPEED_CAPABILITY_D3_RESERVED     0x0000f000
815 
816 	#define PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK        0xffff0000
817 		#define PORT_HW_CFG_SPEED_CAPABILITY_D0_SHIFT        16
818 		#define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL     0x00010000
819 		#define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF     0x00020000
820 		#define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF    0x00040000
821 		#define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL    0x00080000
822 		#define PORT_HW_CFG_SPEED_CAPABILITY_D0_1G           0x00100000
823 		#define PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G         0x00200000
824 		#define PORT_HW_CFG_SPEED_CAPABILITY_D0_10G          0x00400000
825 		#define PORT_HW_CFG_SPEED_CAPABILITY_D0_20G          0x00800000
826 		#define PORT_HW_CFG_SPEED_CAPABILITY_D0_RESERVED     0xf0000000
827 
828 	/*  A place to hold the original MAC address as a backup */
829 	u32 backup_mac_upper;			/* 0x2B4 */
830 	u32 backup_mac_lower;			/* 0x2B8 */
831 
832 };
833 
834 
835 /****************************************************************************
836  * Shared Feature configuration                                             *
837  ****************************************************************************/
838 struct shared_feat_cfg {		 /* NVRAM Offset */
839 
840 	u32 config;			/* 0x450 */
841 	#define SHARED_FEATURE_BMC_ECHO_MODE_EN             0x00000001
842 
843 	/* Use NVRAM values instead of HW default values */
844 	#define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_MASK \
845 							    0x00000002
846 		#define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_DISABLED \
847 								     0x00000000
848 		#define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED \
849 								     0x00000002
850 
851 	#define SHARED_FEAT_CFG_NCSI_ID_METHOD_MASK         0x00000008
852 		#define SHARED_FEAT_CFG_NCSI_ID_METHOD_SPIO          0x00000000
853 		#define SHARED_FEAT_CFG_NCSI_ID_METHOD_NVRAM         0x00000008
854 
855 	#define SHARED_FEAT_CFG_NCSI_ID_MASK                0x00000030
856 	#define SHARED_FEAT_CFG_NCSI_ID_SHIFT                        4
857 
858 	/*  Override the OTP back to single function mode. When using GPIO,
859 	      high means only SF, 0 is according to CLP configuration */
860 	#define SHARED_FEAT_CFG_FORCE_SF_MODE_MASK          0x00000700
861 		#define SHARED_FEAT_CFG_FORCE_SF_MODE_SHIFT          8
862 		#define SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED     0x00000000
863 		#define SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF      0x00000100
864 		#define SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4          0x00000200
865 		#define SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT  0x00000300
866 		#define SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE      0x00000400
867 		#define SHARED_FEAT_CFG_FORCE_SF_MODE_UFP_MODE       0x00000600
868 		#define SHARED_FEAT_CFG_FORCE_SF_MODE_EXTENDED_MODE  0x00000700
869 
870 	/* The interval in seconds between sending LLDP packets. Set to zero
871 	   to disable the feature */
872 	#define SHARED_FEAT_CFG_LLDP_XMIT_INTERVAL_MASK     0x00ff0000
873 	#define SHARED_FEAT_CFG_LLDP_XMIT_INTERVAL_SHIFT             16
874 
875 	/* The assigned device type ID for LLDP usage */
876 	#define SHARED_FEAT_CFG_LLDP_DEVICE_TYPE_ID_MASK    0xff000000
877 	#define SHARED_FEAT_CFG_LLDP_DEVICE_TYPE_ID_SHIFT            24
878 
879 };
880 
881 
882 /****************************************************************************
883  * Port Feature configuration                                               *
884  ****************************************************************************/
885 struct port_feat_cfg {		    /* port 0: 0x454  port 1: 0x4c8 */
886 
887 	u32 config;
888 	#define PORT_FEATURE_BAR1_SIZE_MASK                 0x0000000f
889 		#define PORT_FEATURE_BAR1_SIZE_SHIFT                 0
890 		#define PORT_FEATURE_BAR1_SIZE_DISABLED              0x00000000
891 		#define PORT_FEATURE_BAR1_SIZE_64K                   0x00000001
892 		#define PORT_FEATURE_BAR1_SIZE_128K                  0x00000002
893 		#define PORT_FEATURE_BAR1_SIZE_256K                  0x00000003
894 		#define PORT_FEATURE_BAR1_SIZE_512K                  0x00000004
895 		#define PORT_FEATURE_BAR1_SIZE_1M                    0x00000005
896 		#define PORT_FEATURE_BAR1_SIZE_2M                    0x00000006
897 		#define PORT_FEATURE_BAR1_SIZE_4M                    0x00000007
898 		#define PORT_FEATURE_BAR1_SIZE_8M                    0x00000008
899 		#define PORT_FEATURE_BAR1_SIZE_16M                   0x00000009
900 		#define PORT_FEATURE_BAR1_SIZE_32M                   0x0000000a
901 		#define PORT_FEATURE_BAR1_SIZE_64M                   0x0000000b
902 		#define PORT_FEATURE_BAR1_SIZE_128M                  0x0000000c
903 		#define PORT_FEATURE_BAR1_SIZE_256M                  0x0000000d
904 		#define PORT_FEATURE_BAR1_SIZE_512M                  0x0000000e
905 		#define PORT_FEATURE_BAR1_SIZE_1G                    0x0000000f
906 	#define PORT_FEATURE_BAR2_SIZE_MASK                 0x000000f0
907 		#define PORT_FEATURE_BAR2_SIZE_SHIFT                 4
908 		#define PORT_FEATURE_BAR2_SIZE_DISABLED              0x00000000
909 		#define PORT_FEATURE_BAR2_SIZE_64K                   0x00000010
910 		#define PORT_FEATURE_BAR2_SIZE_128K                  0x00000020
911 		#define PORT_FEATURE_BAR2_SIZE_256K                  0x00000030
912 		#define PORT_FEATURE_BAR2_SIZE_512K                  0x00000040
913 		#define PORT_FEATURE_BAR2_SIZE_1M                    0x00000050
914 		#define PORT_FEATURE_BAR2_SIZE_2M                    0x00000060
915 		#define PORT_FEATURE_BAR2_SIZE_4M                    0x00000070
916 		#define PORT_FEATURE_BAR2_SIZE_8M                    0x00000080
917 		#define PORT_FEATURE_BAR2_SIZE_16M                   0x00000090
918 		#define PORT_FEATURE_BAR2_SIZE_32M                   0x000000a0
919 		#define PORT_FEATURE_BAR2_SIZE_64M                   0x000000b0
920 		#define PORT_FEATURE_BAR2_SIZE_128M                  0x000000c0
921 		#define PORT_FEATURE_BAR2_SIZE_256M                  0x000000d0
922 		#define PORT_FEATURE_BAR2_SIZE_512M                  0x000000e0
923 		#define PORT_FEATURE_BAR2_SIZE_1G                    0x000000f0
924 
925 	#define PORT_FEAT_CFG_DCBX_MASK                     0x00000100
926 		#define PORT_FEAT_CFG_DCBX_DISABLED                  0x00000000
927 		#define PORT_FEAT_CFG_DCBX_ENABLED                   0x00000100
928 
929 		#define PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK        0x00000C00
930 		#define PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE        0x00000400
931 		#define PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI       0x00000800
932 
933 	#define PORT_FEATURE_EN_SIZE_MASK                   0x0f000000
934 	#define PORT_FEATURE_EN_SIZE_SHIFT                           24
935 	#define PORT_FEATURE_WOL_ENABLED                             0x01000000
936 	#define PORT_FEATURE_MBA_ENABLED                             0x02000000
937 	#define PORT_FEATURE_MFW_ENABLED                             0x04000000
938 
939 	/* Advertise expansion ROM even if MBA is disabled */
940 	#define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_MASK        0x08000000
941 		#define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_DISABLED     0x00000000
942 		#define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_ENABLED      0x08000000
943 
944 	/* Check the optic vendor via i2c against a list of approved modules
945 	   in a separate nvram image */
946 	#define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK         0xe0000000
947 		#define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_SHIFT         29
948 		#define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT \
949 								     0x00000000
950 		#define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER \
951 								     0x20000000
952 		#define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG   0x40000000
953 		#define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN    0x60000000
954 
955 	u32 wol_config;
956 	/* Default is used when driver sets to "auto" mode */
957 	#define PORT_FEATURE_WOL_DEFAULT_MASK               0x00000003
958 		#define PORT_FEATURE_WOL_DEFAULT_SHIFT               0
959 		#define PORT_FEATURE_WOL_DEFAULT_DISABLE             0x00000000
960 		#define PORT_FEATURE_WOL_DEFAULT_MAGIC               0x00000001
961 		#define PORT_FEATURE_WOL_DEFAULT_ACPI                0x00000002
962 		#define PORT_FEATURE_WOL_DEFAULT_MAGIC_AND_ACPI      0x00000003
963 	#define PORT_FEATURE_WOL_RES_PAUSE_CAP              0x00000004
964 	#define PORT_FEATURE_WOL_RES_ASYM_PAUSE_CAP         0x00000008
965 	#define PORT_FEATURE_WOL_ACPI_UPON_MGMT             0x00000010
966 
967 	u32 mba_config;
968 	#define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK       0x00000007
969 		#define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT       0
970 		#define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE         0x00000000
971 		#define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL         0x00000001
972 		#define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP       0x00000002
973 		#define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB      0x00000003
974 		#define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT   0x00000004
975 		#define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE        0x00000007
976 
977 	#define PORT_FEATURE_MBA_BOOT_RETRY_MASK            0x00000038
978 	#define PORT_FEATURE_MBA_BOOT_RETRY_SHIFT                    3
979 
980 	#define PORT_FEATURE_MBA_RES_PAUSE_CAP              0x00000100
981 	#define PORT_FEATURE_MBA_RES_ASYM_PAUSE_CAP         0x00000200
982 	#define PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE        0x00000400
983 	#define PORT_FEATURE_MBA_HOTKEY_MASK                0x00000800
984 		#define PORT_FEATURE_MBA_HOTKEY_CTRL_S               0x00000000
985 		#define PORT_FEATURE_MBA_HOTKEY_CTRL_B               0x00000800
986 	#define PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK          0x000ff000
987 		#define PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT          12
988 		#define PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED       0x00000000
989 		#define PORT_FEATURE_MBA_EXP_ROM_SIZE_2K             0x00001000
990 		#define PORT_FEATURE_MBA_EXP_ROM_SIZE_4K             0x00002000
991 		#define PORT_FEATURE_MBA_EXP_ROM_SIZE_8K             0x00003000
992 		#define PORT_FEATURE_MBA_EXP_ROM_SIZE_16K            0x00004000
993 		#define PORT_FEATURE_MBA_EXP_ROM_SIZE_32K            0x00005000
994 		#define PORT_FEATURE_MBA_EXP_ROM_SIZE_64K            0x00006000
995 		#define PORT_FEATURE_MBA_EXP_ROM_SIZE_128K           0x00007000
996 		#define PORT_FEATURE_MBA_EXP_ROM_SIZE_256K           0x00008000
997 		#define PORT_FEATURE_MBA_EXP_ROM_SIZE_512K           0x00009000
998 		#define PORT_FEATURE_MBA_EXP_ROM_SIZE_1M             0x0000a000
999 		#define PORT_FEATURE_MBA_EXP_ROM_SIZE_2M             0x0000b000
1000 		#define PORT_FEATURE_MBA_EXP_ROM_SIZE_4M             0x0000c000
1001 		#define PORT_FEATURE_MBA_EXP_ROM_SIZE_8M             0x0000d000
1002 		#define PORT_FEATURE_MBA_EXP_ROM_SIZE_16M            0x0000e000
1003 		#define PORT_FEATURE_MBA_EXP_ROM_SIZE_32M            0x0000f000
1004 	#define PORT_FEATURE_MBA_MSG_TIMEOUT_MASK           0x00f00000
1005 	#define PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT                   20
1006 	#define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK        0x03000000
1007 		#define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT        24
1008 		#define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO         0x00000000
1009 		#define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS          0x01000000
1010 		#define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H       0x02000000
1011 		#define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H       0x03000000
1012 	#define PORT_FEATURE_MBA_LINK_SPEED_MASK            0x3c000000
1013 		#define PORT_FEATURE_MBA_LINK_SPEED_SHIFT            26
1014 		#define PORT_FEATURE_MBA_LINK_SPEED_AUTO             0x00000000
1015 		#define PORT_FEATURE_MBA_LINK_SPEED_10HD             0x04000000
1016 		#define PORT_FEATURE_MBA_LINK_SPEED_10FD             0x08000000
1017 		#define PORT_FEATURE_MBA_LINK_SPEED_100HD            0x0c000000
1018 		#define PORT_FEATURE_MBA_LINK_SPEED_100FD            0x10000000
1019 		#define PORT_FEATURE_MBA_LINK_SPEED_1GBPS            0x14000000
1020 		#define PORT_FEATURE_MBA_LINK_SPEED_2_5GBPS          0x18000000
1021 		#define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_CX4       0x1c000000
1022 		#define PORT_FEATURE_MBA_LINK_SPEED_20GBPS           0x20000000
1023 	u32 bmc_config;
1024 	#define PORT_FEATURE_BMC_LINK_OVERRIDE_MASK         0x00000001
1025 		#define PORT_FEATURE_BMC_LINK_OVERRIDE_DEFAULT       0x00000000
1026 		#define PORT_FEATURE_BMC_LINK_OVERRIDE_EN            0x00000001
1027 
1028 	u32 mba_vlan_cfg;
1029 	#define PORT_FEATURE_MBA_VLAN_TAG_MASK              0x0000ffff
1030 	#define PORT_FEATURE_MBA_VLAN_TAG_SHIFT                      0
1031 	#define PORT_FEATURE_MBA_VLAN_EN                    0x00010000
1032 
1033 	u32 resource_cfg;
1034 	#define PORT_FEATURE_RESOURCE_CFG_VALID             0x00000001
1035 	#define PORT_FEATURE_RESOURCE_CFG_DIAG              0x00000002
1036 	#define PORT_FEATURE_RESOURCE_CFG_L2                0x00000004
1037 	#define PORT_FEATURE_RESOURCE_CFG_ISCSI             0x00000008
1038 	#define PORT_FEATURE_RESOURCE_CFG_RDMA              0x00000010
1039 
1040 	u32 smbus_config;
1041 	#define PORT_FEATURE_SMBUS_ADDR_MASK                0x000000fe
1042 	#define PORT_FEATURE_SMBUS_ADDR_SHIFT                        1
1043 
1044 	u32 vf_config;
1045 	#define PORT_FEAT_CFG_VF_BAR2_SIZE_MASK             0x0000000f
1046 		#define PORT_FEAT_CFG_VF_BAR2_SIZE_SHIFT             0
1047 		#define PORT_FEAT_CFG_VF_BAR2_SIZE_DISABLED          0x00000000
1048 		#define PORT_FEAT_CFG_VF_BAR2_SIZE_4K                0x00000001
1049 		#define PORT_FEAT_CFG_VF_BAR2_SIZE_8K                0x00000002
1050 		#define PORT_FEAT_CFG_VF_BAR2_SIZE_16K               0x00000003
1051 		#define PORT_FEAT_CFG_VF_BAR2_SIZE_32K               0x00000004
1052 		#define PORT_FEAT_CFG_VF_BAR2_SIZE_64K               0x00000005
1053 		#define PORT_FEAT_CFG_VF_BAR2_SIZE_128K              0x00000006
1054 		#define PORT_FEAT_CFG_VF_BAR2_SIZE_256K              0x00000007
1055 		#define PORT_FEAT_CFG_VF_BAR2_SIZE_512K              0x00000008
1056 		#define PORT_FEAT_CFG_VF_BAR2_SIZE_1M                0x00000009
1057 		#define PORT_FEAT_CFG_VF_BAR2_SIZE_2M                0x0000000a
1058 		#define PORT_FEAT_CFG_VF_BAR2_SIZE_4M                0x0000000b
1059 		#define PORT_FEAT_CFG_VF_BAR2_SIZE_8M                0x0000000c
1060 		#define PORT_FEAT_CFG_VF_BAR2_SIZE_16M               0x0000000d
1061 		#define PORT_FEAT_CFG_VF_BAR2_SIZE_32M               0x0000000e
1062 		#define PORT_FEAT_CFG_VF_BAR2_SIZE_64M               0x0000000f
1063 
1064 	u32 link_config;    /* Used as HW defaults for the driver */
1065 	#define PORT_FEATURE_CONNECTED_SWITCH_MASK          0x03000000
1066 		#define PORT_FEATURE_CONNECTED_SWITCH_SHIFT          24
1067 		/* (forced) low speed switch (< 10G) */
1068 		#define PORT_FEATURE_CON_SWITCH_1G_SWITCH            0x00000000
1069 		/* (forced) high speed switch (>= 10G) */
1070 		#define PORT_FEATURE_CON_SWITCH_10G_SWITCH           0x01000000
1071 		#define PORT_FEATURE_CON_SWITCH_AUTO_DETECT          0x02000000
1072 		#define PORT_FEATURE_CON_SWITCH_ONE_TIME_DETECT      0x03000000
1073 
1074 	#define PORT_FEATURE_LINK_SPEED_MASK                0x000f0000
1075 		#define PORT_FEATURE_LINK_SPEED_SHIFT                16
1076 		#define PORT_FEATURE_LINK_SPEED_AUTO                 0x00000000
1077 		#define PORT_FEATURE_LINK_SPEED_10M_FULL             0x00010000
1078 		#define PORT_FEATURE_LINK_SPEED_10M_HALF             0x00020000
1079 		#define PORT_FEATURE_LINK_SPEED_100M_HALF            0x00030000
1080 		#define PORT_FEATURE_LINK_SPEED_100M_FULL            0x00040000
1081 		#define PORT_FEATURE_LINK_SPEED_1G                   0x00050000
1082 		#define PORT_FEATURE_LINK_SPEED_2_5G                 0x00060000
1083 		#define PORT_FEATURE_LINK_SPEED_10G_CX4              0x00070000
1084 		#define PORT_FEATURE_LINK_SPEED_20G                  0x00080000
1085 
1086 	#define PORT_FEATURE_FLOW_CONTROL_MASK              0x00000700
1087 		#define PORT_FEATURE_FLOW_CONTROL_SHIFT              8
1088 		#define PORT_FEATURE_FLOW_CONTROL_AUTO               0x00000000
1089 		#define PORT_FEATURE_FLOW_CONTROL_TX                 0x00000100
1090 		#define PORT_FEATURE_FLOW_CONTROL_RX                 0x00000200
1091 		#define PORT_FEATURE_FLOW_CONTROL_BOTH               0x00000300
1092 		#define PORT_FEATURE_FLOW_CONTROL_NONE               0x00000400
1093 
1094 	/* The default for MCP link configuration,
1095 	   uses the same defines as link_config */
1096 	u32 mfw_wol_link_cfg;
1097 
1098 	/* The default for the driver of the second external phy,
1099 	   uses the same defines as link_config */
1100 	u32 link_config2;				    /* 0x47C */
1101 
1102 	/* The default for MCP of the second external phy,
1103 	   uses the same defines as link_config */
1104 	u32 mfw_wol_link_cfg2;				    /* 0x480 */
1105 
1106 
1107 	/*  EEE power saving mode */
1108 	u32 eee_power_mode;                                 /* 0x484 */
1109 	#define PORT_FEAT_CFG_EEE_POWER_MODE_MASK                     0x000000FF
1110 	#define PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT                    0
1111 	#define PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED                 0x00000000
1112 	#define PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED                 0x00000001
1113 	#define PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE               0x00000002
1114 	#define PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY              0x00000003
1115 
1116 
1117 	u32 Reserved2[16];                                  /* 0x488 */
1118 };
1119 
1120 
1121 /****************************************************************************
1122  * Device Information                                                       *
1123  ****************************************************************************/
1124 struct shm_dev_info {				/* size */
1125 
1126 	u32    bc_rev; /* 8 bits each: major, minor, build */	       /* 4 */
1127 
1128 	struct shared_hw_cfg     shared_hw_config;	      /* 40 */
1129 
1130 	struct port_hw_cfg       port_hw_config[PORT_MAX];     /* 400*2=800 */
1131 
1132 	struct shared_feat_cfg   shared_feature_config;		   /* 4 */
1133 
1134 	struct port_feat_cfg     port_feature_config[PORT_MAX];/* 116*2=232 */
1135 
1136 };
1137 
1138 
1139 #if !defined(__LITTLE_ENDIAN) && !defined(__BIG_ENDIAN)
1140 	#error "Missing either LITTLE_ENDIAN or BIG_ENDIAN definition."
1141 #endif
1142 
1143 #define FUNC_0              0
1144 #define FUNC_1              1
1145 #define FUNC_2              2
1146 #define FUNC_3              3
1147 #define FUNC_4              4
1148 #define FUNC_5              5
1149 #define FUNC_6              6
1150 #define FUNC_7              7
1151 #define E1_FUNC_MAX         2
1152 #define E1H_FUNC_MAX            8
1153 #define E2_FUNC_MAX         4   /* per path */
1154 
1155 #define VN_0                0
1156 #define VN_1                1
1157 #define VN_2                2
1158 #define VN_3                3
1159 #define E1VN_MAX            1
1160 #define E1HVN_MAX           4
1161 
1162 #define E2_VF_MAX           64  /* HC_REG_VF_CONFIGURATION_SIZE */
1163 /* This value (in milliseconds) determines the frequency of the driver
1164  * issuing the PULSE message code.  The firmware monitors this periodic
1165  * pulse to determine when to switch to an OS-absent mode. */
1166 #define DRV_PULSE_PERIOD_MS     250
1167 
1168 /* This value (in milliseconds) determines how long the driver should
1169  * wait for an acknowledgement from the firmware before timing out.  Once
1170  * the firmware has timed out, the driver will assume there is no firmware
1171  * running and there won't be any firmware-driver synchronization during a
1172  * driver reset. */
1173 #define FW_ACK_TIME_OUT_MS      5000
1174 
1175 #define FW_ACK_POLL_TIME_MS     1
1176 
1177 #define FW_ACK_NUM_OF_POLL  (FW_ACK_TIME_OUT_MS/FW_ACK_POLL_TIME_MS)
1178 
1179 #define MFW_TRACE_SIGNATURE     0x54524342
1180 
1181 /****************************************************************************
1182  * Driver <-> FW Mailbox                                                    *
1183  ****************************************************************************/
1184 struct drv_port_mb {
1185 
1186 	u32 link_status;
1187 	/* Driver should update this field on any link change event */
1188 
1189 	#define LINK_STATUS_NONE				(0<<0)
1190 	#define LINK_STATUS_LINK_FLAG_MASK			0x00000001
1191 	#define LINK_STATUS_LINK_UP				0x00000001
1192 	#define LINK_STATUS_SPEED_AND_DUPLEX_MASK		0x0000001E
1193 	#define LINK_STATUS_SPEED_AND_DUPLEX_AN_NOT_COMPLETE	(0<<1)
1194 	#define LINK_STATUS_SPEED_AND_DUPLEX_10THD		(1<<1)
1195 	#define LINK_STATUS_SPEED_AND_DUPLEX_10TFD		(2<<1)
1196 	#define LINK_STATUS_SPEED_AND_DUPLEX_100TXHD		(3<<1)
1197 	#define LINK_STATUS_SPEED_AND_DUPLEX_100T4		(4<<1)
1198 	#define LINK_STATUS_SPEED_AND_DUPLEX_100TXFD		(5<<1)
1199 	#define LINK_STATUS_SPEED_AND_DUPLEX_1000THD		(6<<1)
1200 	#define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD		(7<<1)
1201 	#define LINK_STATUS_SPEED_AND_DUPLEX_1000XFD		(7<<1)
1202 	#define LINK_STATUS_SPEED_AND_DUPLEX_2500THD		(8<<1)
1203 	#define LINK_STATUS_SPEED_AND_DUPLEX_2500TFD		(9<<1)
1204 	#define LINK_STATUS_SPEED_AND_DUPLEX_2500XFD		(9<<1)
1205 	#define LINK_STATUS_SPEED_AND_DUPLEX_10GTFD		(10<<1)
1206 	#define LINK_STATUS_SPEED_AND_DUPLEX_10GXFD		(10<<1)
1207 	#define LINK_STATUS_SPEED_AND_DUPLEX_20GTFD		(11<<1)
1208 	#define LINK_STATUS_SPEED_AND_DUPLEX_20GXFD		(11<<1)
1209 
1210 	#define LINK_STATUS_AUTO_NEGOTIATE_FLAG_MASK		0x00000020
1211 	#define LINK_STATUS_AUTO_NEGOTIATE_ENABLED		0x00000020
1212 
1213 	#define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE		0x00000040
1214 	#define LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK	0x00000080
1215 	#define LINK_STATUS_PARALLEL_DETECTION_USED		0x00000080
1216 
1217 	#define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE	0x00000200
1218 	#define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE	0x00000400
1219 	#define LINK_STATUS_LINK_PARTNER_100T4_CAPABLE		0x00000800
1220 	#define LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE	0x00001000
1221 	#define LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE	0x00002000
1222 	#define LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE		0x00004000
1223 	#define LINK_STATUS_LINK_PARTNER_10THD_CAPABLE		0x00008000
1224 
1225 	#define LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK		0x00010000
1226 	#define LINK_STATUS_TX_FLOW_CONTROL_ENABLED		0x00010000
1227 
1228 	#define LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK		0x00020000
1229 	#define LINK_STATUS_RX_FLOW_CONTROL_ENABLED		0x00020000
1230 
1231 	#define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK	0x000C0000
1232 	#define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE	(0<<18)
1233 	#define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE	(1<<18)
1234 	#define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE	(2<<18)
1235 	#define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE		(3<<18)
1236 
1237 	#define LINK_STATUS_SERDES_LINK				0x00100000
1238 
1239 	#define LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE	0x00200000
1240 	#define LINK_STATUS_LINK_PARTNER_2500XHD_CAPABLE	0x00400000
1241 	#define LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE		0x00800000
1242 	#define LINK_STATUS_LINK_PARTNER_20GXFD_CAPABLE		0x10000000
1243 
1244 	#define LINK_STATUS_PFC_ENABLED				0x20000000
1245 
1246 	#define LINK_STATUS_PHYSICAL_LINK_FLAG			0x40000000
1247 	#define LINK_STATUS_SFP_TX_FAULT			0x80000000
1248 
1249 	u32 port_stx;
1250 
1251 	u32 stat_nig_timer;
1252 
1253 	/* MCP firmware does not use this field */
1254 	u32 ext_phy_fw_version;
1255 
1256 };
1257 
1258 
1259 struct drv_func_mb {
1260 
1261 	u32 drv_mb_header;
1262 	#define DRV_MSG_CODE_MASK                       0xffff0000
1263 	#define DRV_MSG_CODE_LOAD_REQ                   0x10000000
1264 	#define DRV_MSG_CODE_LOAD_DONE                  0x11000000
1265 	#define DRV_MSG_CODE_UNLOAD_REQ_WOL_EN          0x20000000
1266 	#define DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS         0x20010000
1267 	#define DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP         0x20020000
1268 	#define DRV_MSG_CODE_UNLOAD_DONE                0x21000000
1269 	#define DRV_MSG_CODE_DCC_OK                     0x30000000
1270 	#define DRV_MSG_CODE_DCC_FAILURE                0x31000000
1271 	#define DRV_MSG_CODE_DIAG_ENTER_REQ             0x50000000
1272 	#define DRV_MSG_CODE_DIAG_EXIT_REQ              0x60000000
1273 	#define DRV_MSG_CODE_VALIDATE_KEY               0x70000000
1274 	#define DRV_MSG_CODE_GET_CURR_KEY               0x80000000
1275 	#define DRV_MSG_CODE_GET_UPGRADE_KEY            0x81000000
1276 	#define DRV_MSG_CODE_GET_MANUF_KEY              0x82000000
1277 	#define DRV_MSG_CODE_LOAD_L2B_PRAM              0x90000000
1278 	#define DRV_MSG_CODE_OEM_OK			0x00010000
1279 	#define DRV_MSG_CODE_OEM_FAILURE		0x00020000
1280 	#define DRV_MSG_CODE_OEM_UPDATE_SVID_OK		0x00030000
1281 	#define DRV_MSG_CODE_OEM_UPDATE_SVID_FAILURE	0x00040000
1282 	/*
1283 	 * The optic module verification command requires bootcode
1284 	 * v5.0.6 or later, te specific optic module verification command
1285 	 * requires bootcode v5.2.12 or later
1286 	 */
1287 	#define DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL     0xa0000000
1288 	#define REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL     0x00050006
1289 	#define DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL  0xa1000000
1290 	#define REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL  0x00050234
1291 	#define DRV_MSG_CODE_VRFY_AFEX_SUPPORTED        0xa2000000
1292 	#define REQ_BC_VER_4_VRFY_AFEX_SUPPORTED        0x00070002
1293 	#define REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED   0x00070014
1294 	#define REQ_BC_VER_4_MT_SUPPORTED               0x00070201
1295 	#define REQ_BC_VER_4_PFC_STATS_SUPPORTED        0x00070201
1296 	#define REQ_BC_VER_4_FCOE_FEATURES              0x00070209
1297 
1298 	#define DRV_MSG_CODE_DCBX_ADMIN_PMF_MSG         0xb0000000
1299 	#define DRV_MSG_CODE_DCBX_PMF_DRV_OK            0xb2000000
1300 	#define REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF     0x00070401
1301 
1302 	#define DRV_MSG_CODE_VF_DISABLED_DONE           0xc0000000
1303 
1304 	#define DRV_MSG_CODE_AFEX_DRIVER_SETMAC         0xd0000000
1305 	#define DRV_MSG_CODE_AFEX_LISTGET_ACK           0xd1000000
1306 	#define DRV_MSG_CODE_AFEX_LISTSET_ACK           0xd2000000
1307 	#define DRV_MSG_CODE_AFEX_STATSGET_ACK          0xd3000000
1308 	#define DRV_MSG_CODE_AFEX_VIFSET_ACK            0xd4000000
1309 
1310 	#define DRV_MSG_CODE_DRV_INFO_ACK               0xd8000000
1311 	#define DRV_MSG_CODE_DRV_INFO_NACK              0xd9000000
1312 
1313 	#define DRV_MSG_CODE_EEE_RESULTS_ACK            0xda000000
1314 
1315 	#define DRV_MSG_CODE_RMMOD                      0xdb000000
1316 	#define REQ_BC_VER_4_RMMOD_CMD                  0x0007080f
1317 
1318 	#define DRV_MSG_CODE_SET_MF_BW                  0xe0000000
1319 	#define REQ_BC_VER_4_SET_MF_BW                  0x00060202
1320 	#define DRV_MSG_CODE_SET_MF_BW_ACK              0xe1000000
1321 
1322 	#define DRV_MSG_CODE_LINK_STATUS_CHANGED        0x01000000
1323 
1324 	#define DRV_MSG_CODE_INITIATE_FLR               0x02000000
1325 	#define REQ_BC_VER_4_INITIATE_FLR               0x00070213
1326 
1327 	#define BIOS_MSG_CODE_LIC_CHALLENGE             0xff010000
1328 	#define BIOS_MSG_CODE_LIC_RESPONSE              0xff020000
1329 	#define BIOS_MSG_CODE_VIRT_MAC_PRIM             0xff030000
1330 	#define BIOS_MSG_CODE_VIRT_MAC_ISCSI            0xff040000
1331 
1332 	#define DRV_MSG_SEQ_NUMBER_MASK                 0x0000ffff
1333 
1334 	u32 drv_mb_param;
1335 	#define DRV_MSG_CODE_SET_MF_BW_MIN_MASK         0x00ff0000
1336 	#define DRV_MSG_CODE_SET_MF_BW_MAX_MASK         0xff000000
1337 
1338 	#define DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET     0x00000002
1339 
1340 	#define DRV_MSG_CODE_LOAD_REQ_WITH_LFA          0x0000100a
1341 	#define DRV_MSG_CODE_LOAD_REQ_FORCE_LFA         0x00002000
1342 
1343 	u32 fw_mb_header;
1344 	#define FW_MSG_CODE_MASK                        0xffff0000
1345 	#define FW_MSG_CODE_DRV_LOAD_COMMON             0x10100000
1346 	#define FW_MSG_CODE_DRV_LOAD_PORT               0x10110000
1347 	#define FW_MSG_CODE_DRV_LOAD_FUNCTION           0x10120000
1348 	/* Load common chip is supported from bc 6.0.0  */
1349 	#define REQ_BC_VER_4_DRV_LOAD_COMMON_CHIP       0x00060000
1350 	#define FW_MSG_CODE_DRV_LOAD_COMMON_CHIP        0x10130000
1351 
1352 	#define FW_MSG_CODE_DRV_LOAD_REFUSED            0x10200000
1353 	#define FW_MSG_CODE_DRV_LOAD_DONE               0x11100000
1354 	#define FW_MSG_CODE_DRV_UNLOAD_COMMON           0x20100000
1355 	#define FW_MSG_CODE_DRV_UNLOAD_PORT             0x20110000
1356 	#define FW_MSG_CODE_DRV_UNLOAD_FUNCTION         0x20120000
1357 	#define FW_MSG_CODE_DRV_UNLOAD_DONE             0x21100000
1358 	#define FW_MSG_CODE_DCC_DONE                    0x30100000
1359 	#define FW_MSG_CODE_LLDP_DONE                   0x40100000
1360 	#define FW_MSG_CODE_DIAG_ENTER_DONE             0x50100000
1361 	#define FW_MSG_CODE_DIAG_REFUSE                 0x50200000
1362 	#define FW_MSG_CODE_DIAG_EXIT_DONE              0x60100000
1363 	#define FW_MSG_CODE_VALIDATE_KEY_SUCCESS        0x70100000
1364 	#define FW_MSG_CODE_VALIDATE_KEY_FAILURE        0x70200000
1365 	#define FW_MSG_CODE_GET_KEY_DONE                0x80100000
1366 	#define FW_MSG_CODE_NO_KEY                      0x80f00000
1367 	#define FW_MSG_CODE_LIC_INFO_NOT_READY          0x80f80000
1368 	#define FW_MSG_CODE_L2B_PRAM_LOADED             0x90100000
1369 	#define FW_MSG_CODE_L2B_PRAM_T_LOAD_FAILURE     0x90210000
1370 	#define FW_MSG_CODE_L2B_PRAM_C_LOAD_FAILURE     0x90220000
1371 	#define FW_MSG_CODE_L2B_PRAM_X_LOAD_FAILURE     0x90230000
1372 	#define FW_MSG_CODE_L2B_PRAM_U_LOAD_FAILURE     0x90240000
1373 	#define FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS        0xa0100000
1374 	#define FW_MSG_CODE_VRFY_OPT_MDL_INVLD_IMG      0xa0200000
1375 	#define FW_MSG_CODE_VRFY_OPT_MDL_UNAPPROVED     0xa0300000
1376 	#define FW_MSG_CODE_VF_DISABLED_DONE            0xb0000000
1377 	#define FW_MSG_CODE_HW_SET_INVALID_IMAGE        0xb0100000
1378 
1379 	#define FW_MSG_CODE_AFEX_DRIVER_SETMAC_DONE     0xd0100000
1380 	#define FW_MSG_CODE_AFEX_LISTGET_ACK            0xd1100000
1381 	#define FW_MSG_CODE_AFEX_LISTSET_ACK            0xd2100000
1382 	#define FW_MSG_CODE_AFEX_STATSGET_ACK           0xd3100000
1383 	#define FW_MSG_CODE_AFEX_VIFSET_ACK             0xd4100000
1384 
1385 	#define FW_MSG_CODE_DRV_INFO_ACK                0xd8100000
1386 	#define FW_MSG_CODE_DRV_INFO_NACK               0xd9100000
1387 
1388 	#define FW_MSG_CODE_EEE_RESULS_ACK              0xda100000
1389 
1390 	#define FW_MSG_CODE_RMMOD_ACK                   0xdb100000
1391 
1392 	#define FW_MSG_CODE_SET_MF_BW_SENT              0xe0000000
1393 	#define FW_MSG_CODE_SET_MF_BW_DONE              0xe1000000
1394 
1395 	#define FW_MSG_CODE_LINK_CHANGED_ACK            0x01100000
1396 
1397 	#define FW_MSG_CODE_LIC_CHALLENGE               0xff010000
1398 	#define FW_MSG_CODE_LIC_RESPONSE                0xff020000
1399 	#define FW_MSG_CODE_VIRT_MAC_PRIM               0xff030000
1400 	#define FW_MSG_CODE_VIRT_MAC_ISCSI              0xff040000
1401 
1402 	#define FW_MSG_SEQ_NUMBER_MASK                  0x0000ffff
1403 
1404 	u32 fw_mb_param;
1405 
1406 	u32 drv_pulse_mb;
1407 	#define DRV_PULSE_SEQ_MASK                      0x00007fff
1408 	#define DRV_PULSE_SYSTEM_TIME_MASK              0xffff0000
1409 	/*
1410 	 * The system time is in the format of
1411 	 * (year-2001)*12*32 + month*32 + day.
1412 	 */
1413 	#define DRV_PULSE_ALWAYS_ALIVE                  0x00008000
1414 	/*
1415 	 * Indicate to the firmware not to go into the
1416 	 * OS-absent when it is not getting driver pulse.
1417 	 * This is used for debugging as well for PXE(MBA).
1418 	 */
1419 
1420 	u32 mcp_pulse_mb;
1421 	#define MCP_PULSE_SEQ_MASK                      0x00007fff
1422 	#define MCP_PULSE_ALWAYS_ALIVE                  0x00008000
1423 	/* Indicates to the driver not to assert due to lack
1424 	 * of MCP response */
1425 	#define MCP_EVENT_MASK                          0xffff0000
1426 	#define MCP_EVENT_OTHER_DRIVER_RESET_REQ        0x00010000
1427 
1428 	u32 iscsi_boot_signature;
1429 	u32 iscsi_boot_block_offset;
1430 
1431 	u32 drv_status;
1432 	#define DRV_STATUS_PMF                          0x00000001
1433 	#define DRV_STATUS_VF_DISABLED                  0x00000002
1434 	#define DRV_STATUS_SET_MF_BW                    0x00000004
1435 	#define DRV_STATUS_LINK_EVENT                   0x00000008
1436 
1437 	#define DRV_STATUS_OEM_EVENT_MASK               0x00000070
1438 	#define DRV_STATUS_OEM_DISABLE_ENABLE_PF        0x00000010
1439 	#define DRV_STATUS_OEM_BANDWIDTH_ALLOCATION     0x00000020
1440 
1441 	#define DRV_STATUS_OEM_UPDATE_SVID              0x00000080
1442 
1443 	#define DRV_STATUS_DCC_EVENT_MASK               0x0000ff00
1444 	#define DRV_STATUS_DCC_DISABLE_ENABLE_PF        0x00000100
1445 	#define DRV_STATUS_DCC_BANDWIDTH_ALLOCATION     0x00000200
1446 	#define DRV_STATUS_DCC_CHANGE_MAC_ADDRESS       0x00000400
1447 	#define DRV_STATUS_DCC_RESERVED1                0x00000800
1448 	#define DRV_STATUS_DCC_SET_PROTOCOL             0x00001000
1449 	#define DRV_STATUS_DCC_SET_PRIORITY             0x00002000
1450 
1451 	#define DRV_STATUS_DCBX_EVENT_MASK              0x000f0000
1452 	#define DRV_STATUS_DCBX_NEGOTIATION_RESULTS     0x00010000
1453 	#define DRV_STATUS_AFEX_EVENT_MASK              0x03f00000
1454 	#define DRV_STATUS_AFEX_LISTGET_REQ             0x00100000
1455 	#define DRV_STATUS_AFEX_LISTSET_REQ             0x00200000
1456 	#define DRV_STATUS_AFEX_STATSGET_REQ            0x00400000
1457 	#define DRV_STATUS_AFEX_VIFSET_REQ              0x00800000
1458 
1459 	#define DRV_STATUS_DRV_INFO_REQ                 0x04000000
1460 
1461 	#define DRV_STATUS_EEE_NEGOTIATION_RESULTS      0x08000000
1462 
1463 	u32 virt_mac_upper;
1464 	#define VIRT_MAC_SIGN_MASK                      0xffff0000
1465 	#define VIRT_MAC_SIGNATURE                      0x564d0000
1466 	u32 virt_mac_lower;
1467 
1468 };
1469 
1470 
1471 /****************************************************************************
1472  * Management firmware state                                                *
1473  ****************************************************************************/
1474 /* Allocate 440 bytes for management firmware */
1475 #define MGMTFW_STATE_WORD_SIZE                          110
1476 
1477 struct mgmtfw_state {
1478 	u32 opaque[MGMTFW_STATE_WORD_SIZE];
1479 };
1480 
1481 
1482 /****************************************************************************
1483  * Multi-Function configuration                                             *
1484  ****************************************************************************/
1485 struct shared_mf_cfg {
1486 
1487 	u32 clp_mb;
1488 	#define SHARED_MF_CLP_SET_DEFAULT               0x00000000
1489 	/* set by CLP */
1490 	#define SHARED_MF_CLP_EXIT                      0x00000001
1491 	/* set by MCP */
1492 	#define SHARED_MF_CLP_EXIT_DONE                 0x00010000
1493 
1494 };
1495 
1496 struct port_mf_cfg {
1497 
1498 	u32 dynamic_cfg;    /* device control channel */
1499 	#define PORT_MF_CFG_E1HOV_TAG_MASK              0x0000ffff
1500 	#define PORT_MF_CFG_E1HOV_TAG_SHIFT             0
1501 	#define PORT_MF_CFG_E1HOV_TAG_DEFAULT         PORT_MF_CFG_E1HOV_TAG_MASK
1502 
1503 	u32 reserved[1];
1504 
1505 };
1506 
1507 struct func_mf_cfg {
1508 
1509 	u32 config;
1510 	/* E/R/I/D */
1511 	/* function 0 of each port cannot be hidden */
1512 	#define FUNC_MF_CFG_FUNC_HIDE                   0x00000001
1513 
1514 	#define FUNC_MF_CFG_PROTOCOL_MASK               0x00000006
1515 	#define FUNC_MF_CFG_PROTOCOL_FCOE               0x00000000
1516 	#define FUNC_MF_CFG_PROTOCOL_ETHERNET           0x00000002
1517 	#define FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA 0x00000004
1518 	#define FUNC_MF_CFG_PROTOCOL_ISCSI              0x00000006
1519 	#define FUNC_MF_CFG_PROTOCOL_DEFAULT \
1520 				FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA
1521 
1522 	#define FUNC_MF_CFG_FUNC_DISABLED               0x00000008
1523 	#define FUNC_MF_CFG_FUNC_DELETED                0x00000010
1524 
1525 	/* PRI */
1526 	/* 0 - low priority, 3 - high priority */
1527 	#define FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK      0x00000300
1528 	#define FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT     8
1529 	#define FUNC_MF_CFG_TRANSMIT_PRIORITY_DEFAULT   0x00000000
1530 
1531 	/* MINBW, MAXBW */
1532 	/* value range - 0..100, increments in 100Mbps */
1533 	#define FUNC_MF_CFG_MIN_BW_MASK                 0x00ff0000
1534 	#define FUNC_MF_CFG_MIN_BW_SHIFT                16
1535 	#define FUNC_MF_CFG_MIN_BW_DEFAULT              0x00000000
1536 	#define FUNC_MF_CFG_MAX_BW_MASK                 0xff000000
1537 	#define FUNC_MF_CFG_MAX_BW_SHIFT                24
1538 	#define FUNC_MF_CFG_MAX_BW_DEFAULT              0x64000000
1539 
1540 	u32 mac_upper;	    /* MAC */
1541 	#define FUNC_MF_CFG_UPPERMAC_MASK               0x0000ffff
1542 	#define FUNC_MF_CFG_UPPERMAC_SHIFT              0
1543 	#define FUNC_MF_CFG_UPPERMAC_DEFAULT           FUNC_MF_CFG_UPPERMAC_MASK
1544 	u32 mac_lower;
1545 	#define FUNC_MF_CFG_LOWERMAC_DEFAULT            0xffffffff
1546 
1547 	u32 e1hov_tag;	/* VNI */
1548 	#define FUNC_MF_CFG_E1HOV_TAG_MASK              0x0000ffff
1549 	#define FUNC_MF_CFG_E1HOV_TAG_SHIFT             0
1550 	#define FUNC_MF_CFG_E1HOV_TAG_DEFAULT         FUNC_MF_CFG_E1HOV_TAG_MASK
1551 
1552 	/* afex default VLAN ID - 12 bits */
1553 	#define FUNC_MF_CFG_AFEX_VLAN_MASK              0x0fff0000
1554 	#define FUNC_MF_CFG_AFEX_VLAN_SHIFT             16
1555 
1556 	u32 afex_config;
1557 	#define FUNC_MF_CFG_AFEX_COS_FILTER_MASK                     0x000000ff
1558 	#define FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT                    0
1559 	#define FUNC_MF_CFG_AFEX_MBA_ENABLED_MASK                    0x0000ff00
1560 	#define FUNC_MF_CFG_AFEX_MBA_ENABLED_SHIFT                   8
1561 	#define FUNC_MF_CFG_AFEX_MBA_ENABLED_VAL                     0x00000100
1562 	#define FUNC_MF_CFG_AFEX_VLAN_MODE_MASK                      0x000f0000
1563 	#define FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT                     16
1564 
1565 	u32 reserved;
1566 };
1567 
1568 enum mf_cfg_afex_vlan_mode {
1569 	FUNC_MF_CFG_AFEX_VLAN_TRUNK_MODE = 0,
1570 	FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE,
1571 	FUNC_MF_CFG_AFEX_VLAN_TRUNK_TAG_NATIVE_MODE
1572 };
1573 
1574 /* This structure is not applicable and should not be accessed on 57711 */
1575 struct func_ext_cfg {
1576 	u32 func_cfg;
1577 	#define MACP_FUNC_CFG_FLAGS_MASK                0x0000007F
1578 	#define MACP_FUNC_CFG_FLAGS_SHIFT               0
1579 	#define MACP_FUNC_CFG_FLAGS_ENABLED             0x00000001
1580 	#define MACP_FUNC_CFG_FLAGS_ETHERNET            0x00000002
1581 	#define MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD       0x00000004
1582 	#define MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD        0x00000008
1583 	#define MACP_FUNC_CFG_PAUSE_ON_HOST_RING        0x00000080
1584 
1585 	u32 iscsi_mac_addr_upper;
1586 	u32 iscsi_mac_addr_lower;
1587 
1588 	u32 fcoe_mac_addr_upper;
1589 	u32 fcoe_mac_addr_lower;
1590 
1591 	u32 fcoe_wwn_port_name_upper;
1592 	u32 fcoe_wwn_port_name_lower;
1593 
1594 	u32 fcoe_wwn_node_name_upper;
1595 	u32 fcoe_wwn_node_name_lower;
1596 
1597 	u32 preserve_data;
1598 	#define MF_FUNC_CFG_PRESERVE_L2_MAC             (1<<0)
1599 	#define MF_FUNC_CFG_PRESERVE_ISCSI_MAC          (1<<1)
1600 	#define MF_FUNC_CFG_PRESERVE_FCOE_MAC           (1<<2)
1601 	#define MF_FUNC_CFG_PRESERVE_FCOE_WWN_P         (1<<3)
1602 	#define MF_FUNC_CFG_PRESERVE_FCOE_WWN_N         (1<<4)
1603 	#define MF_FUNC_CFG_PRESERVE_TX_BW              (1<<5)
1604 };
1605 
1606 struct mf_cfg {
1607 
1608 	struct shared_mf_cfg    shared_mf_config;       /* 0x4 */
1609 							/* 0x8*2*2=0x20 */
1610 	struct port_mf_cfg  port_mf_config[NVM_PATH_MAX][PORT_MAX];
1611 	/* for all chips, there are 8 mf functions */
1612 	struct func_mf_cfg  func_mf_config[E1H_FUNC_MAX]; /* 0x18 * 8 = 0xc0 */
1613 	/*
1614 	 * Extended configuration per function  - this array does not exist and
1615 	 * should not be accessed on 57711
1616 	 */
1617 	struct func_ext_cfg func_ext_config[E1H_FUNC_MAX]; /* 0x28 * 8 = 0x140*/
1618 }; /* 0x224 */
1619 
1620 /****************************************************************************
1621  * Shared Memory Region                                                     *
1622  ****************************************************************************/
1623 struct shmem_region {		       /*   SharedMem Offset (size) */
1624 
1625 	u32         validity_map[PORT_MAX];  /* 0x0 (4*2 = 0x8) */
1626 	#define SHR_MEM_FORMAT_REV_MASK                     0xff000000
1627 	#define SHR_MEM_FORMAT_REV_ID                       ('A'<<24)
1628 	/* validity bits */
1629 	#define SHR_MEM_VALIDITY_PCI_CFG                    0x00100000
1630 	#define SHR_MEM_VALIDITY_MB                         0x00200000
1631 	#define SHR_MEM_VALIDITY_DEV_INFO                   0x00400000
1632 	#define SHR_MEM_VALIDITY_RESERVED                   0x00000007
1633 	/* One licensing bit should be set */
1634 	#define SHR_MEM_VALIDITY_LIC_KEY_IN_EFFECT_MASK     0x00000038
1635 	#define SHR_MEM_VALIDITY_LIC_MANUF_KEY_IN_EFFECT    0x00000008
1636 	#define SHR_MEM_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT  0x00000010
1637 	#define SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT       0x00000020
1638 	/* Active MFW */
1639 	#define SHR_MEM_VALIDITY_ACTIVE_MFW_UNKNOWN         0x00000000
1640 	#define SHR_MEM_VALIDITY_ACTIVE_MFW_MASK            0x000001c0
1641 	#define SHR_MEM_VALIDITY_ACTIVE_MFW_IPMI            0x00000040
1642 	#define SHR_MEM_VALIDITY_ACTIVE_MFW_UMP             0x00000080
1643 	#define SHR_MEM_VALIDITY_ACTIVE_MFW_NCSI            0x000000c0
1644 	#define SHR_MEM_VALIDITY_ACTIVE_MFW_NONE            0x000001c0
1645 
1646 	struct shm_dev_info dev_info;	     /* 0x8     (0x438) */
1647 
1648 	struct license_key       drv_lic_key[PORT_MAX]; /* 0x440 (52*2=0x68) */
1649 
1650 	/* FW information (for internal FW use) */
1651 	u32         fw_info_fio_offset;		/* 0x4a8       (0x4) */
1652 	struct mgmtfw_state mgmtfw_state;	/* 0x4ac     (0x1b8) */
1653 
1654 	struct drv_port_mb  port_mb[PORT_MAX];	/* 0x664 (16*2=0x20) */
1655 
1656 #ifdef BMAPI
1657 	/* This is a variable length array */
1658 	/* the number of function depends on the chip type */
1659 	struct drv_func_mb func_mb[1];	/* 0x684 (44*2/4/8=0x58/0xb0/0x160) */
1660 #else
1661 	/* the number of function depends on the chip type */
1662 	struct drv_func_mb  func_mb[];	/* 0x684 (44*2/4/8=0x58/0xb0/0x160) */
1663 #endif /* BMAPI */
1664 
1665 }; /* 57710 = 0x6dc | 57711 = 0x7E4 | 57712 = 0x734 */
1666 
1667 /****************************************************************************
1668  * Shared Memory 2 Region                                                   *
1669  ****************************************************************************/
1670 /* The fw_flr_ack is actually built in the following way:                   */
1671 /* 8 bit:  PF ack                                                           */
1672 /* 64 bit: VF ack                                                           */
1673 /* 8 bit:  ios_dis_ack                                                      */
1674 /* In order to maintain endianity in the mailbox hsi, we want to keep using */
1675 /* u32. The fw must have the VF right after the PF since this is how it     */
1676 /* access arrays(it expects always the VF to reside after the PF, and that  */
1677 /* makes the calculation much easier for it. )                              */
1678 /* In order to answer both limitations, and keep the struct small, the code */
1679 /* will abuse the structure defined here to achieve the actual partition    */
1680 /* above                                                                    */
1681 /****************************************************************************/
1682 struct fw_flr_ack {
1683 	u32         pf_ack;
1684 	u32         vf_ack[1];
1685 	u32         iov_dis_ack;
1686 };
1687 
1688 struct fw_flr_mb {
1689 	u32         aggint;
1690 	u32         opgen_addr;
1691 	struct fw_flr_ack ack;
1692 };
1693 
1694 struct eee_remote_vals {
1695 	u32         tx_tw;
1696 	u32         rx_tw;
1697 };
1698 
1699 /**** SUPPORT FOR SHMEM ARRRAYS ***
1700  * The SHMEM HSI is aligned on 32 bit boundaries which makes it difficult to
1701  * define arrays with storage types smaller then unsigned dwords.
1702  * The macros below add generic support for SHMEM arrays with numeric elements
1703  * that can span 2,4,8 or 16 bits. The array underlying type is a 32 bit dword
1704  * array with individual bit-filed elements accessed using shifts and masks.
1705  *
1706  */
1707 
1708 /* eb is the bitwidth of a single element */
1709 #define SHMEM_ARRAY_MASK(eb)		((1<<(eb))-1)
1710 #define SHMEM_ARRAY_ENTRY(i, eb)	((i)/(32/(eb)))
1711 
1712 /* the bit-position macro allows the used to flip the order of the arrays
1713  * elements on a per byte or word boundary.
1714  *
1715  * example: an array with 8 entries each 4 bit wide. This array will fit into
1716  * a single dword. The diagrmas below show the array order of the nibbles.
1717  *
1718  * SHMEM_ARRAY_BITPOS(i, 4, 4) defines the stadard ordering:
1719  *
1720  *                |                |                |               |
1721  *   0    |   1   |   2    |   3   |   4    |   5   |   6   |   7   |
1722  *                |                |                |               |
1723  *
1724  * SHMEM_ARRAY_BITPOS(i, 4, 8) defines a flip ordering per byte:
1725  *
1726  *                |                |                |               |
1727  *   1   |   0    |   3    |   2   |   5    |   4   |   7   |   6   |
1728  *                |                |                |               |
1729  *
1730  * SHMEM_ARRAY_BITPOS(i, 4, 16) defines a flip ordering per word:
1731  *
1732  *                |                |                |               |
1733  *   3   |   2    |   1   |   0    |   7   |   6    |   5   |   4   |
1734  *                |                |                |               |
1735  */
1736 #define SHMEM_ARRAY_BITPOS(i, eb, fb)	\
1737 	((((32/(fb)) - 1 - ((i)/((fb)/(eb))) % (32/(fb))) * (fb)) + \
1738 	(((i)%((fb)/(eb))) * (eb)))
1739 
1740 #define SHMEM_ARRAY_GET(a, i, eb, fb)					\
1741 	((a[SHMEM_ARRAY_ENTRY(i, eb)] >> SHMEM_ARRAY_BITPOS(i, eb, fb)) &  \
1742 	SHMEM_ARRAY_MASK(eb))
1743 
1744 #define SHMEM_ARRAY_SET(a, i, eb, fb, val)				\
1745 do {									   \
1746 	a[SHMEM_ARRAY_ENTRY(i, eb)] &= ~(SHMEM_ARRAY_MASK(eb) <<	   \
1747 	SHMEM_ARRAY_BITPOS(i, eb, fb));					   \
1748 	a[SHMEM_ARRAY_ENTRY(i, eb)] |= (((val) & SHMEM_ARRAY_MASK(eb)) <<  \
1749 	SHMEM_ARRAY_BITPOS(i, eb, fb));					   \
1750 } while (0)
1751 
1752 
1753 /****START OF DCBX STRUCTURES DECLARATIONS****/
1754 #define DCBX_MAX_NUM_PRI_PG_ENTRIES	8
1755 #define DCBX_PRI_PG_BITWIDTH		4
1756 #define DCBX_PRI_PG_FBITS		8
1757 #define DCBX_PRI_PG_GET(a, i)		\
1758 	SHMEM_ARRAY_GET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS)
1759 #define DCBX_PRI_PG_SET(a, i, val)	\
1760 	SHMEM_ARRAY_SET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS, val)
1761 #define DCBX_MAX_NUM_PG_BW_ENTRIES	8
1762 #define DCBX_BW_PG_BITWIDTH		8
1763 #define DCBX_PG_BW_GET(a, i)		\
1764 	SHMEM_ARRAY_GET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH)
1765 #define DCBX_PG_BW_SET(a, i, val)	\
1766 	SHMEM_ARRAY_SET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH, val)
1767 #define DCBX_STRICT_PRI_PG		15
1768 #define DCBX_MAX_APP_PROTOCOL		16
1769 #define FCOE_APP_IDX			0
1770 #define ISCSI_APP_IDX			1
1771 #define PREDEFINED_APP_IDX_MAX		2
1772 
1773 
1774 /* Big/Little endian have the same representation. */
1775 struct dcbx_ets_feature {
1776 	/*
1777 	 * For Admin MIB - is this feature supported by the
1778 	 * driver | For Local MIB - should this feature be enabled.
1779 	 */
1780 	u32 enabled;
1781 	u32  pg_bw_tbl[2];
1782 	u32  pri_pg_tbl[1];
1783 };
1784 
1785 /* Driver structure in LE */
1786 struct dcbx_pfc_feature {
1787 #ifdef __BIG_ENDIAN
1788 	u8 pri_en_bitmap;
1789 	#define DCBX_PFC_PRI_0 0x01
1790 	#define DCBX_PFC_PRI_1 0x02
1791 	#define DCBX_PFC_PRI_2 0x04
1792 	#define DCBX_PFC_PRI_3 0x08
1793 	#define DCBX_PFC_PRI_4 0x10
1794 	#define DCBX_PFC_PRI_5 0x20
1795 	#define DCBX_PFC_PRI_6 0x40
1796 	#define DCBX_PFC_PRI_7 0x80
1797 	u8 pfc_caps;
1798 	u8 reserved;
1799 	u8 enabled;
1800 #elif defined(__LITTLE_ENDIAN)
1801 	u8 enabled;
1802 	u8 reserved;
1803 	u8 pfc_caps;
1804 	u8 pri_en_bitmap;
1805 	#define DCBX_PFC_PRI_0 0x01
1806 	#define DCBX_PFC_PRI_1 0x02
1807 	#define DCBX_PFC_PRI_2 0x04
1808 	#define DCBX_PFC_PRI_3 0x08
1809 	#define DCBX_PFC_PRI_4 0x10
1810 	#define DCBX_PFC_PRI_5 0x20
1811 	#define DCBX_PFC_PRI_6 0x40
1812 	#define DCBX_PFC_PRI_7 0x80
1813 #endif
1814 };
1815 
1816 struct dcbx_app_priority_entry {
1817 #ifdef __BIG_ENDIAN
1818 	u16  app_id;
1819 	u8  pri_bitmap;
1820 	u8  appBitfield;
1821 	#define DCBX_APP_ENTRY_VALID         0x01
1822 	#define DCBX_APP_ENTRY_SF_MASK       0x30
1823 	#define DCBX_APP_ENTRY_SF_SHIFT      4
1824 	#define DCBX_APP_SF_ETH_TYPE         0x10
1825 	#define DCBX_APP_SF_PORT             0x20
1826 #elif defined(__LITTLE_ENDIAN)
1827 	u8 appBitfield;
1828 	#define DCBX_APP_ENTRY_VALID         0x01
1829 	#define DCBX_APP_ENTRY_SF_MASK       0x30
1830 	#define DCBX_APP_ENTRY_SF_SHIFT      4
1831 	#define DCBX_APP_SF_ETH_TYPE         0x10
1832 	#define DCBX_APP_SF_PORT             0x20
1833 	u8  pri_bitmap;
1834 	u16  app_id;
1835 #endif
1836 };
1837 
1838 
1839 /* FW structure in BE */
1840 struct dcbx_app_priority_feature {
1841 #ifdef __BIG_ENDIAN
1842 	u8 reserved;
1843 	u8 default_pri;
1844 	u8 tc_supported;
1845 	u8 enabled;
1846 #elif defined(__LITTLE_ENDIAN)
1847 	u8 enabled;
1848 	u8 tc_supported;
1849 	u8 default_pri;
1850 	u8 reserved;
1851 #endif
1852 	struct dcbx_app_priority_entry  app_pri_tbl[DCBX_MAX_APP_PROTOCOL];
1853 };
1854 
1855 /* FW structure in BE */
1856 struct dcbx_features {
1857 	/* PG feature */
1858 	struct dcbx_ets_feature ets;
1859 	/* PFC feature */
1860 	struct dcbx_pfc_feature pfc;
1861 	/* APP feature */
1862 	struct dcbx_app_priority_feature app;
1863 };
1864 
1865 /* LLDP protocol parameters */
1866 /* FW structure in BE */
1867 struct lldp_params {
1868 #ifdef __BIG_ENDIAN
1869 	u8  msg_fast_tx_interval;
1870 	u8  msg_tx_hold;
1871 	u8  msg_tx_interval;
1872 	u8  admin_status;
1873 	#define LLDP_TX_ONLY  0x01
1874 	#define LLDP_RX_ONLY  0x02
1875 	#define LLDP_TX_RX    0x03
1876 	#define LLDP_DISABLED 0x04
1877 	u8  reserved1;
1878 	u8  tx_fast;
1879 	u8  tx_crd_max;
1880 	u8  tx_crd;
1881 #elif defined(__LITTLE_ENDIAN)
1882 	u8  admin_status;
1883 	#define LLDP_TX_ONLY  0x01
1884 	#define LLDP_RX_ONLY  0x02
1885 	#define LLDP_TX_RX    0x03
1886 	#define LLDP_DISABLED 0x04
1887 	u8  msg_tx_interval;
1888 	u8  msg_tx_hold;
1889 	u8  msg_fast_tx_interval;
1890 	u8  tx_crd;
1891 	u8  tx_crd_max;
1892 	u8  tx_fast;
1893 	u8  reserved1;
1894 #endif
1895 	#define REM_CHASSIS_ID_STAT_LEN 4
1896 	#define REM_PORT_ID_STAT_LEN 4
1897 	/* Holds remote Chassis ID TLV header, subtype and 9B of payload. */
1898 	u32 peer_chassis_id[REM_CHASSIS_ID_STAT_LEN];
1899 	/* Holds remote Port ID TLV header, subtype and 9B of payload. */
1900 	u32 peer_port_id[REM_PORT_ID_STAT_LEN];
1901 };
1902 
1903 struct lldp_dcbx_stat {
1904 	#define LOCAL_CHASSIS_ID_STAT_LEN 2
1905 	#define LOCAL_PORT_ID_STAT_LEN 2
1906 	/* Holds local Chassis ID 8B payload of constant subtype 4. */
1907 	u32 local_chassis_id[LOCAL_CHASSIS_ID_STAT_LEN];
1908 	/* Holds local Port ID 8B payload of constant subtype 3. */
1909 	u32 local_port_id[LOCAL_PORT_ID_STAT_LEN];
1910 	/* Number of DCBX frames transmitted. */
1911 	u32 num_tx_dcbx_pkts;
1912 	/* Number of DCBX frames received. */
1913 	u32 num_rx_dcbx_pkts;
1914 };
1915 
1916 /* ADMIN MIB - DCBX local machine default configuration. */
1917 struct lldp_admin_mib {
1918 	u32     ver_cfg_flags;
1919 	#define DCBX_ETS_CONFIG_TX_ENABLED       0x00000001
1920 	#define DCBX_PFC_CONFIG_TX_ENABLED       0x00000002
1921 	#define DCBX_APP_CONFIG_TX_ENABLED       0x00000004
1922 	#define DCBX_ETS_RECO_TX_ENABLED         0x00000008
1923 	#define DCBX_ETS_RECO_VALID              0x00000010
1924 	#define DCBX_ETS_WILLING                 0x00000020
1925 	#define DCBX_PFC_WILLING                 0x00000040
1926 	#define DCBX_APP_WILLING                 0x00000080
1927 	#define DCBX_VERSION_CEE                 0x00000100
1928 	#define DCBX_VERSION_IEEE                0x00000200
1929 	#define DCBX_DCBX_ENABLED                0x00000400
1930 	#define DCBX_CEE_VERSION_MASK            0x0000f000
1931 	#define DCBX_CEE_VERSION_SHIFT           12
1932 	#define DCBX_CEE_MAX_VERSION_MASK        0x000f0000
1933 	#define DCBX_CEE_MAX_VERSION_SHIFT       16
1934 	struct dcbx_features     features;
1935 };
1936 
1937 /* REMOTE MIB - remote machine DCBX configuration. */
1938 struct lldp_remote_mib {
1939 	u32 prefix_seq_num;
1940 	u32 flags;
1941 	#define DCBX_ETS_TLV_RX                  0x00000001
1942 	#define DCBX_PFC_TLV_RX                  0x00000002
1943 	#define DCBX_APP_TLV_RX                  0x00000004
1944 	#define DCBX_ETS_RX_ERROR                0x00000010
1945 	#define DCBX_PFC_RX_ERROR                0x00000020
1946 	#define DCBX_APP_RX_ERROR                0x00000040
1947 	#define DCBX_ETS_REM_WILLING             0x00000100
1948 	#define DCBX_PFC_REM_WILLING             0x00000200
1949 	#define DCBX_APP_REM_WILLING             0x00000400
1950 	#define DCBX_REMOTE_ETS_RECO_VALID       0x00001000
1951 	#define DCBX_REMOTE_MIB_VALID            0x00002000
1952 	struct dcbx_features features;
1953 	u32 suffix_seq_num;
1954 };
1955 
1956 /* LOCAL MIB - operational DCBX configuration - transmitted on Tx LLDPDU. */
1957 struct lldp_local_mib {
1958 	u32 prefix_seq_num;
1959 	/* Indicates if there is mismatch with negotiation results. */
1960 	u32 error;
1961 	#define DCBX_LOCAL_ETS_ERROR             0x00000001
1962 	#define DCBX_LOCAL_PFC_ERROR             0x00000002
1963 	#define DCBX_LOCAL_APP_ERROR             0x00000004
1964 	#define DCBX_LOCAL_PFC_MISMATCH          0x00000010
1965 	#define DCBX_LOCAL_APP_MISMATCH          0x00000020
1966 	#define DCBX_REMOTE_MIB_ERROR		 0x00000040
1967 	#define DCBX_REMOTE_ETS_TLV_NOT_FOUND    0x00000080
1968 	#define DCBX_REMOTE_PFC_TLV_NOT_FOUND    0x00000100
1969 	#define DCBX_REMOTE_APP_TLV_NOT_FOUND    0x00000200
1970 	struct dcbx_features   features;
1971 	u32 suffix_seq_num;
1972 };
1973 /***END OF DCBX STRUCTURES DECLARATIONS***/
1974 
1975 /***********************************************************/
1976 /*                         Elink section                   */
1977 /***********************************************************/
1978 #define SHMEM_LINK_CONFIG_SIZE 2
1979 struct shmem_lfa {
1980 	u32 req_duplex;
1981 	#define REQ_DUPLEX_PHY0_MASK        0x0000ffff
1982 	#define REQ_DUPLEX_PHY0_SHIFT       0
1983 	#define REQ_DUPLEX_PHY1_MASK        0xffff0000
1984 	#define REQ_DUPLEX_PHY1_SHIFT       16
1985 	u32 req_flow_ctrl;
1986 	#define REQ_FLOW_CTRL_PHY0_MASK     0x0000ffff
1987 	#define REQ_FLOW_CTRL_PHY0_SHIFT    0
1988 	#define REQ_FLOW_CTRL_PHY1_MASK     0xffff0000
1989 	#define REQ_FLOW_CTRL_PHY1_SHIFT    16
1990 	u32 req_line_speed; /* Also determine AutoNeg */
1991 	#define REQ_LINE_SPD_PHY0_MASK      0x0000ffff
1992 	#define REQ_LINE_SPD_PHY0_SHIFT     0
1993 	#define REQ_LINE_SPD_PHY1_MASK      0xffff0000
1994 	#define REQ_LINE_SPD_PHY1_SHIFT     16
1995 	u32 speed_cap_mask[SHMEM_LINK_CONFIG_SIZE];
1996 	u32 additional_config;
1997 	#define REQ_FC_AUTO_ADV_MASK        0x0000ffff
1998 	#define REQ_FC_AUTO_ADV0_SHIFT      0
1999 	#define NO_LFA_DUE_TO_DCC_MASK      0x00010000
2000 	u32 lfa_sts;
2001 	#define LFA_LINK_FLAP_REASON_OFFSET		0
2002 	#define LFA_LINK_FLAP_REASON_MASK		0x000000ff
2003 		#define LFA_LINK_DOWN			    0x1
2004 		#define LFA_LOOPBACK_ENABLED		0x2
2005 		#define LFA_DUPLEX_MISMATCH		    0x3
2006 		#define LFA_MFW_IS_TOO_OLD		    0x4
2007 		#define LFA_LINK_SPEED_MISMATCH		0x5
2008 		#define LFA_FLOW_CTRL_MISMATCH		0x6
2009 		#define LFA_SPEED_CAP_MISMATCH		0x7
2010 		#define LFA_DCC_LFA_DISABLED		0x8
2011 		#define LFA_EEE_MISMATCH		0x9
2012 
2013 	#define LINK_FLAP_AVOIDANCE_COUNT_OFFSET	8
2014 	#define LINK_FLAP_AVOIDANCE_COUNT_MASK		0x0000ff00
2015 
2016 	#define LINK_FLAP_COUNT_OFFSET			16
2017 	#define LINK_FLAP_COUNT_MASK			0x00ff0000
2018 
2019 	#define LFA_FLAGS_MASK				0xff000000
2020 	#define SHMEM_LFA_DONT_CLEAR_STAT		(1<<24)
2021 };
2022 
2023 /* Used to support NSCI get OS driver version
2024  * on driver load the version value will be set
2025  * on driver unload driver value of 0x0 will be set.
2026  */
2027 struct os_drv_ver {
2028 #define DRV_VER_NOT_LOADED			0
2029 
2030 	/* personalties order is important */
2031 #define DRV_PERS_ETHERNET			0
2032 #define DRV_PERS_ISCSI				1
2033 #define DRV_PERS_FCOE				2
2034 
2035 	/* shmem2 struct is constant can't add more personalties here */
2036 #define MAX_DRV_PERS				3
2037 	u32 versions[MAX_DRV_PERS];
2038 };
2039 
2040 struct ncsi_oem_fcoe_features {
2041 	u32 fcoe_features1;
2042 	#define FCOE_FEATURES1_IOS_PER_CONNECTION_MASK          0x0000FFFF
2043 	#define FCOE_FEATURES1_IOS_PER_CONNECTION_OFFSET        0
2044 
2045 	#define FCOE_FEATURES1_LOGINS_PER_PORT_MASK             0xFFFF0000
2046 	#define FCOE_FEATURES1_LOGINS_PER_PORT_OFFSET           16
2047 
2048 	u32 fcoe_features2;
2049 	#define FCOE_FEATURES2_EXCHANGES_MASK                   0x0000FFFF
2050 	#define FCOE_FEATURES2_EXCHANGES_OFFSET                 0
2051 
2052 	#define FCOE_FEATURES2_NPIV_WWN_PER_PORT_MASK           0xFFFF0000
2053 	#define FCOE_FEATURES2_NPIV_WWN_PER_PORT_OFFSET         16
2054 
2055 	u32 fcoe_features3;
2056 	#define FCOE_FEATURES3_TARGETS_SUPPORTED_MASK           0x0000FFFF
2057 	#define FCOE_FEATURES3_TARGETS_SUPPORTED_OFFSET         0
2058 
2059 	#define FCOE_FEATURES3_OUTSTANDING_COMMANDS_MASK        0xFFFF0000
2060 	#define FCOE_FEATURES3_OUTSTANDING_COMMANDS_OFFSET      16
2061 
2062 	u32 fcoe_features4;
2063 	#define FCOE_FEATURES4_FEATURE_SETTINGS_MASK            0x0000000F
2064 	#define FCOE_FEATURES4_FEATURE_SETTINGS_OFFSET          0
2065 };
2066 
2067 struct ncsi_oem_data {
2068 	u32 driver_version[4];
2069 	struct ncsi_oem_fcoe_features ncsi_oem_fcoe_features;
2070 };
2071 
2072 struct shmem2_region {
2073 
2074 	u32 size;					/* 0x0000 */
2075 
2076 	u32 dcc_support;				/* 0x0004 */
2077 	#define SHMEM_DCC_SUPPORT_NONE                      0x00000000
2078 	#define SHMEM_DCC_SUPPORT_DISABLE_ENABLE_PF_TLV     0x00000001
2079 	#define SHMEM_DCC_SUPPORT_BANDWIDTH_ALLOCATION_TLV  0x00000004
2080 	#define SHMEM_DCC_SUPPORT_CHANGE_MAC_ADDRESS_TLV    0x00000008
2081 	#define SHMEM_DCC_SUPPORT_SET_PROTOCOL_TLV          0x00000040
2082 	#define SHMEM_DCC_SUPPORT_SET_PRIORITY_TLV          0x00000080
2083 
2084 	u32 ext_phy_fw_version2[PORT_MAX];		/* 0x0008 */
2085 	/*
2086 	 * For backwards compatibility, if the mf_cfg_addr does not exist
2087 	 * (the size filed is smaller than 0xc) the mf_cfg resides at the
2088 	 * end of struct shmem_region
2089 	 */
2090 	u32 mf_cfg_addr;				/* 0x0010 */
2091 	#define SHMEM_MF_CFG_ADDR_NONE                  0x00000000
2092 
2093 	struct fw_flr_mb flr_mb;			/* 0x0014 */
2094 	u32 dcbx_lldp_params_offset;			/* 0x0028 */
2095 	#define SHMEM_LLDP_DCBX_PARAMS_NONE             0x00000000
2096 	u32 dcbx_neg_res_offset;			/* 0x002c */
2097 	#define SHMEM_DCBX_NEG_RES_NONE			0x00000000
2098 	u32 dcbx_remote_mib_offset;			/* 0x0030 */
2099 	#define SHMEM_DCBX_REMOTE_MIB_NONE              0x00000000
2100 	/*
2101 	 * The other shmemX_base_addr holds the other path's shmem address
2102 	 * required for example in case of common phy init, or for path1 to know
2103 	 * the address of mcp debug trace which is located in offset from shmem
2104 	 * of path0
2105 	 */
2106 	u32 other_shmem_base_addr;			/* 0x0034 */
2107 	u32 other_shmem2_base_addr;			/* 0x0038 */
2108 	/*
2109 	 * mcp_vf_disabled is set by the MCP to indicate the driver about VFs
2110 	 * which were disabled/flred
2111 	 */
2112 	u32 mcp_vf_disabled[E2_VF_MAX / 32];		/* 0x003c */
2113 
2114 	/*
2115 	 * drv_ack_vf_disabled is set by the PF driver to ack handled disabled
2116 	 * VFs
2117 	 */
2118 	u32 drv_ack_vf_disabled[E2_FUNC_MAX][E2_VF_MAX / 32]; /* 0x0044 */
2119 
2120 	u32 dcbx_lldp_dcbx_stat_offset;			/* 0x0064 */
2121 	#define SHMEM_LLDP_DCBX_STAT_NONE               0x00000000
2122 
2123 	/*
2124 	 * edebug_driver_if field is used to transfer messages between edebug
2125 	 * app to the driver through shmem2.
2126 	 *
2127 	 * message format:
2128 	 * bits 0-2 -  function number / instance of driver to perform request
2129 	 * bits 3-5 -  op code / is_ack?
2130 	 * bits 6-63 - data
2131 	 */
2132 	u32 edebug_driver_if[2];			/* 0x0068 */
2133 	#define EDEBUG_DRIVER_IF_OP_CODE_GET_PHYS_ADDR  1
2134 	#define EDEBUG_DRIVER_IF_OP_CODE_GET_BUS_ADDR   2
2135 	#define EDEBUG_DRIVER_IF_OP_CODE_DISABLE_STAT   3
2136 
2137 	u32 nvm_retain_bitmap_addr;			/* 0x0070 */
2138 
2139 	/* afex support of that driver */
2140 	u32 afex_driver_support;			/* 0x0074 */
2141 	#define SHMEM_AFEX_VERSION_MASK                  0x100f
2142 	#define SHMEM_AFEX_SUPPORTED_VERSION_ONE         0x1001
2143 	#define SHMEM_AFEX_REDUCED_DRV_LOADED            0x8000
2144 
2145 	/* driver receives addr in scratchpad to which it should respond */
2146 	u32 afex_scratchpad_addr_to_write[E2_FUNC_MAX];
2147 
2148 	/* generic params from MCP to driver (value depends on the msg sent
2149 	 * to driver
2150 	 */
2151 	u32 afex_param1_to_driver[E2_FUNC_MAX];		/* 0x0088 */
2152 	u32 afex_param2_to_driver[E2_FUNC_MAX];		/* 0x0098 */
2153 
2154 	u32 swim_base_addr;				/* 0x0108 */
2155 	u32 swim_funcs;
2156 	u32 swim_main_cb;
2157 
2158 	/* bitmap notifying which VIF profiles stored in nvram are enabled by
2159 	 * switch
2160 	 */
2161 	u32 afex_profiles_enabled[2];
2162 
2163 	/* generic flags controlled by the driver */
2164 	u32 drv_flags;
2165 	#define DRV_FLAGS_DCB_CONFIGURED		0x0
2166 	#define DRV_FLAGS_DCB_CONFIGURATION_ABORTED	0x1
2167 	#define DRV_FLAGS_DCB_MFW_CONFIGURED	0x2
2168 
2169 	#define DRV_FLAGS_PORT_MASK	((1 << DRV_FLAGS_DCB_CONFIGURED) | \
2170 			(1 << DRV_FLAGS_DCB_CONFIGURATION_ABORTED) | \
2171 			(1 << DRV_FLAGS_DCB_MFW_CONFIGURED))
2172 	/* pointer to extended dev_info shared data copied from nvm image */
2173 	u32 extended_dev_info_shared_addr;
2174 	u32 ncsi_oem_data_addr;
2175 
2176 	u32 ocsd_host_addr; /* initialized by option ROM */
2177 	u32 ocbb_host_addr; /* initialized by option ROM */
2178 	u32 ocsd_req_update_interval; /* initialized by option ROM */
2179 	u32 temperature_in_half_celsius;
2180 	u32 glob_struct_in_host;
2181 
2182 	u32 dcbx_neg_res_ext_offset;
2183 #define SHMEM_DCBX_NEG_RES_EXT_NONE			0x00000000
2184 
2185 	u32 drv_capabilities_flag[E2_FUNC_MAX];
2186 #define DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED 0x00000001
2187 #define DRV_FLAGS_CAPABILITIES_LOADED_L2        0x00000002
2188 #define DRV_FLAGS_CAPABILITIES_LOADED_FCOE      0x00000004
2189 #define DRV_FLAGS_CAPABILITIES_LOADED_ISCSI     0x00000008
2190 
2191 	u32 extended_dev_info_shared_cfg_size;
2192 
2193 	u32 dcbx_en[PORT_MAX];
2194 
2195 	/* The offset points to the multi threaded meta structure */
2196 	u32 multi_thread_data_offset;
2197 
2198 	/* address of DMAable host address holding values from the drivers */
2199 	u32 drv_info_host_addr_lo;
2200 	u32 drv_info_host_addr_hi;
2201 
2202 	/* general values written by the MFW (such as current version) */
2203 	u32 drv_info_control;
2204 #define DRV_INFO_CONTROL_VER_MASK          0x000000ff
2205 #define DRV_INFO_CONTROL_VER_SHIFT         0
2206 #define DRV_INFO_CONTROL_OP_CODE_MASK      0x0000ff00
2207 #define DRV_INFO_CONTROL_OP_CODE_SHIFT     8
2208 	u32 ibft_host_addr; /* initialized by option ROM */
2209 	struct eee_remote_vals eee_remote_vals[PORT_MAX];
2210 	u32 reserved[E2_FUNC_MAX];
2211 
2212 
2213 	/* the status of EEE auto-negotiation
2214 	 * bits 15:0 the configured tx-lpi entry timer value. Depends on bit 31.
2215 	 * bits 19:16 the supported modes for EEE.
2216 	 * bits 23:20 the speeds advertised for EEE.
2217 	 * bits 27:24 the speeds the Link partner advertised for EEE.
2218 	 * The supported/adv. modes in bits 27:19 originate from the
2219 	 * SHMEM_EEE_XXX_ADV definitions (where XXX is replaced by speed).
2220 	 * bit 28 when 1'b1 EEE was requested.
2221 	 * bit 29 when 1'b1 tx lpi was requested.
2222 	 * bit 30 when 1'b1 EEE was negotiated. Tx lpi will be asserted iff
2223 	 * 30:29 are 2'b11.
2224 	 * bit 31 when 1'b0 bits 15:0 contain a PORT_FEAT_CFG_EEE_ define as
2225 	 * value. When 1'b1 those bits contains a value times 16 microseconds.
2226 	 */
2227 	u32 eee_status[PORT_MAX];
2228 	#define SHMEM_EEE_TIMER_MASK		   0x0000ffff
2229 	#define SHMEM_EEE_SUPPORTED_MASK	   0x000f0000
2230 	#define SHMEM_EEE_SUPPORTED_SHIFT	   16
2231 	#define SHMEM_EEE_ADV_STATUS_MASK	   0x00f00000
2232 		#define SHMEM_EEE_100M_ADV	   (1<<0)
2233 		#define SHMEM_EEE_1G_ADV	   (1<<1)
2234 		#define SHMEM_EEE_10G_ADV	   (1<<2)
2235 	#define SHMEM_EEE_ADV_STATUS_SHIFT	   20
2236 	#define	SHMEM_EEE_LP_ADV_STATUS_MASK	   0x0f000000
2237 	#define SHMEM_EEE_LP_ADV_STATUS_SHIFT	   24
2238 	#define SHMEM_EEE_REQUESTED_BIT		   0x10000000
2239 	#define SHMEM_EEE_LPI_REQUESTED_BIT	   0x20000000
2240 	#define SHMEM_EEE_ACTIVE_BIT		   0x40000000
2241 	#define SHMEM_EEE_TIME_OUTPUT_BIT	   0x80000000
2242 
2243 	u32 sizeof_port_stats;
2244 
2245 	/* Link Flap Avoidance */
2246 	u32 lfa_host_addr[PORT_MAX];
2247 	u32 reserved1;
2248 
2249 	u32 reserved2;				/* Offset 0x148 */
2250 	u32 reserved3;				/* Offset 0x14C */
2251 	u32 reserved4;				/* Offset 0x150 */
2252 	u32 link_attr_sync[PORT_MAX];		/* Offset 0x154 */
2253 	#define LINK_ATTR_SYNC_KR2_ENABLE	0x00000001
2254 	#define LINK_SFP_EEPROM_COMP_CODE_MASK	0x0000ff00
2255 	#define LINK_SFP_EEPROM_COMP_CODE_SHIFT		 8
2256 	#define LINK_SFP_EEPROM_COMP_CODE_SR	0x00001000
2257 	#define LINK_SFP_EEPROM_COMP_CODE_LR	0x00002000
2258 	#define LINK_SFP_EEPROM_COMP_CODE_LRM	0x00004000
2259 
2260 	u32 reserved5[2];
2261 	u32 link_change_count[PORT_MAX];        /* Offset 0x160-0x164 */
2262 	#define LINK_CHANGE_COUNT_MASK 0xff     /* Offset 0x168 */
2263 	/* driver version for each personality */
2264 	struct os_drv_ver func_os_drv_ver[E2_FUNC_MAX]; /* Offset 0x16c */
2265 
2266 	/* Flag to the driver that PF's drv_info_host_addr buffer was read  */
2267 	u32 mfw_drv_indication;
2268 
2269 	/* We use indication for each PF (0..3) */
2270 #define MFW_DRV_IND_READ_DONE_OFFSET(_pf_) (1 << (_pf_))
2271 };
2272 
2273 
2274 struct emac_stats {
2275 	u32     rx_stat_ifhcinoctets;
2276 	u32     rx_stat_ifhcinbadoctets;
2277 	u32     rx_stat_etherstatsfragments;
2278 	u32     rx_stat_ifhcinucastpkts;
2279 	u32     rx_stat_ifhcinmulticastpkts;
2280 	u32     rx_stat_ifhcinbroadcastpkts;
2281 	u32     rx_stat_dot3statsfcserrors;
2282 	u32     rx_stat_dot3statsalignmenterrors;
2283 	u32     rx_stat_dot3statscarriersenseerrors;
2284 	u32     rx_stat_xonpauseframesreceived;
2285 	u32     rx_stat_xoffpauseframesreceived;
2286 	u32     rx_stat_maccontrolframesreceived;
2287 	u32     rx_stat_xoffstateentered;
2288 	u32     rx_stat_dot3statsframestoolong;
2289 	u32     rx_stat_etherstatsjabbers;
2290 	u32     rx_stat_etherstatsundersizepkts;
2291 	u32     rx_stat_etherstatspkts64octets;
2292 	u32     rx_stat_etherstatspkts65octetsto127octets;
2293 	u32     rx_stat_etherstatspkts128octetsto255octets;
2294 	u32     rx_stat_etherstatspkts256octetsto511octets;
2295 	u32     rx_stat_etherstatspkts512octetsto1023octets;
2296 	u32     rx_stat_etherstatspkts1024octetsto1522octets;
2297 	u32     rx_stat_etherstatspktsover1522octets;
2298 
2299 	u32     rx_stat_falsecarriererrors;
2300 
2301 	u32     tx_stat_ifhcoutoctets;
2302 	u32     tx_stat_ifhcoutbadoctets;
2303 	u32     tx_stat_etherstatscollisions;
2304 	u32     tx_stat_outxonsent;
2305 	u32     tx_stat_outxoffsent;
2306 	u32     tx_stat_flowcontroldone;
2307 	u32     tx_stat_dot3statssinglecollisionframes;
2308 	u32     tx_stat_dot3statsmultiplecollisionframes;
2309 	u32     tx_stat_dot3statsdeferredtransmissions;
2310 	u32     tx_stat_dot3statsexcessivecollisions;
2311 	u32     tx_stat_dot3statslatecollisions;
2312 	u32     tx_stat_ifhcoutucastpkts;
2313 	u32     tx_stat_ifhcoutmulticastpkts;
2314 	u32     tx_stat_ifhcoutbroadcastpkts;
2315 	u32     tx_stat_etherstatspkts64octets;
2316 	u32     tx_stat_etherstatspkts65octetsto127octets;
2317 	u32     tx_stat_etherstatspkts128octetsto255octets;
2318 	u32     tx_stat_etherstatspkts256octetsto511octets;
2319 	u32     tx_stat_etherstatspkts512octetsto1023octets;
2320 	u32     tx_stat_etherstatspkts1024octetsto1522octets;
2321 	u32     tx_stat_etherstatspktsover1522octets;
2322 	u32     tx_stat_dot3statsinternalmactransmiterrors;
2323 };
2324 
2325 
2326 struct bmac1_stats {
2327 	u32	tx_stat_gtpkt_lo;
2328 	u32	tx_stat_gtpkt_hi;
2329 	u32	tx_stat_gtxpf_lo;
2330 	u32	tx_stat_gtxpf_hi;
2331 	u32	tx_stat_gtfcs_lo;
2332 	u32	tx_stat_gtfcs_hi;
2333 	u32	tx_stat_gtmca_lo;
2334 	u32	tx_stat_gtmca_hi;
2335 	u32	tx_stat_gtbca_lo;
2336 	u32	tx_stat_gtbca_hi;
2337 	u32	tx_stat_gtfrg_lo;
2338 	u32	tx_stat_gtfrg_hi;
2339 	u32	tx_stat_gtovr_lo;
2340 	u32	tx_stat_gtovr_hi;
2341 	u32	tx_stat_gt64_lo;
2342 	u32	tx_stat_gt64_hi;
2343 	u32	tx_stat_gt127_lo;
2344 	u32	tx_stat_gt127_hi;
2345 	u32	tx_stat_gt255_lo;
2346 	u32	tx_stat_gt255_hi;
2347 	u32	tx_stat_gt511_lo;
2348 	u32	tx_stat_gt511_hi;
2349 	u32	tx_stat_gt1023_lo;
2350 	u32	tx_stat_gt1023_hi;
2351 	u32	tx_stat_gt1518_lo;
2352 	u32	tx_stat_gt1518_hi;
2353 	u32	tx_stat_gt2047_lo;
2354 	u32	tx_stat_gt2047_hi;
2355 	u32	tx_stat_gt4095_lo;
2356 	u32	tx_stat_gt4095_hi;
2357 	u32	tx_stat_gt9216_lo;
2358 	u32	tx_stat_gt9216_hi;
2359 	u32	tx_stat_gt16383_lo;
2360 	u32	tx_stat_gt16383_hi;
2361 	u32	tx_stat_gtmax_lo;
2362 	u32	tx_stat_gtmax_hi;
2363 	u32	tx_stat_gtufl_lo;
2364 	u32	tx_stat_gtufl_hi;
2365 	u32	tx_stat_gterr_lo;
2366 	u32	tx_stat_gterr_hi;
2367 	u32	tx_stat_gtbyt_lo;
2368 	u32	tx_stat_gtbyt_hi;
2369 
2370 	u32	rx_stat_gr64_lo;
2371 	u32	rx_stat_gr64_hi;
2372 	u32	rx_stat_gr127_lo;
2373 	u32	rx_stat_gr127_hi;
2374 	u32	rx_stat_gr255_lo;
2375 	u32	rx_stat_gr255_hi;
2376 	u32	rx_stat_gr511_lo;
2377 	u32	rx_stat_gr511_hi;
2378 	u32	rx_stat_gr1023_lo;
2379 	u32	rx_stat_gr1023_hi;
2380 	u32	rx_stat_gr1518_lo;
2381 	u32	rx_stat_gr1518_hi;
2382 	u32	rx_stat_gr2047_lo;
2383 	u32	rx_stat_gr2047_hi;
2384 	u32	rx_stat_gr4095_lo;
2385 	u32	rx_stat_gr4095_hi;
2386 	u32	rx_stat_gr9216_lo;
2387 	u32	rx_stat_gr9216_hi;
2388 	u32	rx_stat_gr16383_lo;
2389 	u32	rx_stat_gr16383_hi;
2390 	u32	rx_stat_grmax_lo;
2391 	u32	rx_stat_grmax_hi;
2392 	u32	rx_stat_grpkt_lo;
2393 	u32	rx_stat_grpkt_hi;
2394 	u32	rx_stat_grfcs_lo;
2395 	u32	rx_stat_grfcs_hi;
2396 	u32	rx_stat_grmca_lo;
2397 	u32	rx_stat_grmca_hi;
2398 	u32	rx_stat_grbca_lo;
2399 	u32	rx_stat_grbca_hi;
2400 	u32	rx_stat_grxcf_lo;
2401 	u32	rx_stat_grxcf_hi;
2402 	u32	rx_stat_grxpf_lo;
2403 	u32	rx_stat_grxpf_hi;
2404 	u32	rx_stat_grxuo_lo;
2405 	u32	rx_stat_grxuo_hi;
2406 	u32	rx_stat_grjbr_lo;
2407 	u32	rx_stat_grjbr_hi;
2408 	u32	rx_stat_grovr_lo;
2409 	u32	rx_stat_grovr_hi;
2410 	u32	rx_stat_grflr_lo;
2411 	u32	rx_stat_grflr_hi;
2412 	u32	rx_stat_grmeg_lo;
2413 	u32	rx_stat_grmeg_hi;
2414 	u32	rx_stat_grmeb_lo;
2415 	u32	rx_stat_grmeb_hi;
2416 	u32	rx_stat_grbyt_lo;
2417 	u32	rx_stat_grbyt_hi;
2418 	u32	rx_stat_grund_lo;
2419 	u32	rx_stat_grund_hi;
2420 	u32	rx_stat_grfrg_lo;
2421 	u32	rx_stat_grfrg_hi;
2422 	u32	rx_stat_grerb_lo;
2423 	u32	rx_stat_grerb_hi;
2424 	u32	rx_stat_grfre_lo;
2425 	u32	rx_stat_grfre_hi;
2426 	u32	rx_stat_gripj_lo;
2427 	u32	rx_stat_gripj_hi;
2428 };
2429 
2430 struct bmac2_stats {
2431 	u32	tx_stat_gtpk_lo; /* gtpok */
2432 	u32	tx_stat_gtpk_hi; /* gtpok */
2433 	u32	tx_stat_gtxpf_lo; /* gtpf */
2434 	u32	tx_stat_gtxpf_hi; /* gtpf */
2435 	u32	tx_stat_gtpp_lo; /* NEW BMAC2 */
2436 	u32	tx_stat_gtpp_hi; /* NEW BMAC2 */
2437 	u32	tx_stat_gtfcs_lo;
2438 	u32	tx_stat_gtfcs_hi;
2439 	u32	tx_stat_gtuca_lo; /* NEW BMAC2 */
2440 	u32	tx_stat_gtuca_hi; /* NEW BMAC2 */
2441 	u32	tx_stat_gtmca_lo;
2442 	u32	tx_stat_gtmca_hi;
2443 	u32	tx_stat_gtbca_lo;
2444 	u32	tx_stat_gtbca_hi;
2445 	u32	tx_stat_gtovr_lo;
2446 	u32	tx_stat_gtovr_hi;
2447 	u32	tx_stat_gtfrg_lo;
2448 	u32	tx_stat_gtfrg_hi;
2449 	u32	tx_stat_gtpkt1_lo; /* gtpkt */
2450 	u32	tx_stat_gtpkt1_hi; /* gtpkt */
2451 	u32	tx_stat_gt64_lo;
2452 	u32	tx_stat_gt64_hi;
2453 	u32	tx_stat_gt127_lo;
2454 	u32	tx_stat_gt127_hi;
2455 	u32	tx_stat_gt255_lo;
2456 	u32	tx_stat_gt255_hi;
2457 	u32	tx_stat_gt511_lo;
2458 	u32	tx_stat_gt511_hi;
2459 	u32	tx_stat_gt1023_lo;
2460 	u32	tx_stat_gt1023_hi;
2461 	u32	tx_stat_gt1518_lo;
2462 	u32	tx_stat_gt1518_hi;
2463 	u32	tx_stat_gt2047_lo;
2464 	u32	tx_stat_gt2047_hi;
2465 	u32	tx_stat_gt4095_lo;
2466 	u32	tx_stat_gt4095_hi;
2467 	u32	tx_stat_gt9216_lo;
2468 	u32	tx_stat_gt9216_hi;
2469 	u32	tx_stat_gt16383_lo;
2470 	u32	tx_stat_gt16383_hi;
2471 	u32	tx_stat_gtmax_lo;
2472 	u32	tx_stat_gtmax_hi;
2473 	u32	tx_stat_gtufl_lo;
2474 	u32	tx_stat_gtufl_hi;
2475 	u32	tx_stat_gterr_lo;
2476 	u32	tx_stat_gterr_hi;
2477 	u32	tx_stat_gtbyt_lo;
2478 	u32	tx_stat_gtbyt_hi;
2479 
2480 	u32	rx_stat_gr64_lo;
2481 	u32	rx_stat_gr64_hi;
2482 	u32	rx_stat_gr127_lo;
2483 	u32	rx_stat_gr127_hi;
2484 	u32	rx_stat_gr255_lo;
2485 	u32	rx_stat_gr255_hi;
2486 	u32	rx_stat_gr511_lo;
2487 	u32	rx_stat_gr511_hi;
2488 	u32	rx_stat_gr1023_lo;
2489 	u32	rx_stat_gr1023_hi;
2490 	u32	rx_stat_gr1518_lo;
2491 	u32	rx_stat_gr1518_hi;
2492 	u32	rx_stat_gr2047_lo;
2493 	u32	rx_stat_gr2047_hi;
2494 	u32	rx_stat_gr4095_lo;
2495 	u32	rx_stat_gr4095_hi;
2496 	u32	rx_stat_gr9216_lo;
2497 	u32	rx_stat_gr9216_hi;
2498 	u32	rx_stat_gr16383_lo;
2499 	u32	rx_stat_gr16383_hi;
2500 	u32	rx_stat_grmax_lo;
2501 	u32	rx_stat_grmax_hi;
2502 	u32	rx_stat_grpkt_lo;
2503 	u32	rx_stat_grpkt_hi;
2504 	u32	rx_stat_grfcs_lo;
2505 	u32	rx_stat_grfcs_hi;
2506 	u32	rx_stat_gruca_lo;
2507 	u32	rx_stat_gruca_hi;
2508 	u32	rx_stat_grmca_lo;
2509 	u32	rx_stat_grmca_hi;
2510 	u32	rx_stat_grbca_lo;
2511 	u32	rx_stat_grbca_hi;
2512 	u32	rx_stat_grxpf_lo; /* grpf */
2513 	u32	rx_stat_grxpf_hi; /* grpf */
2514 	u32	rx_stat_grpp_lo;
2515 	u32	rx_stat_grpp_hi;
2516 	u32	rx_stat_grxuo_lo; /* gruo */
2517 	u32	rx_stat_grxuo_hi; /* gruo */
2518 	u32	rx_stat_grjbr_lo;
2519 	u32	rx_stat_grjbr_hi;
2520 	u32	rx_stat_grovr_lo;
2521 	u32	rx_stat_grovr_hi;
2522 	u32	rx_stat_grxcf_lo; /* grcf */
2523 	u32	rx_stat_grxcf_hi; /* grcf */
2524 	u32	rx_stat_grflr_lo;
2525 	u32	rx_stat_grflr_hi;
2526 	u32	rx_stat_grpok_lo;
2527 	u32	rx_stat_grpok_hi;
2528 	u32	rx_stat_grmeg_lo;
2529 	u32	rx_stat_grmeg_hi;
2530 	u32	rx_stat_grmeb_lo;
2531 	u32	rx_stat_grmeb_hi;
2532 	u32	rx_stat_grbyt_lo;
2533 	u32	rx_stat_grbyt_hi;
2534 	u32	rx_stat_grund_lo;
2535 	u32	rx_stat_grund_hi;
2536 	u32	rx_stat_grfrg_lo;
2537 	u32	rx_stat_grfrg_hi;
2538 	u32	rx_stat_grerb_lo; /* grerrbyt */
2539 	u32	rx_stat_grerb_hi; /* grerrbyt */
2540 	u32	rx_stat_grfre_lo; /* grfrerr */
2541 	u32	rx_stat_grfre_hi; /* grfrerr */
2542 	u32	rx_stat_gripj_lo;
2543 	u32	rx_stat_gripj_hi;
2544 };
2545 
2546 struct mstat_stats {
2547 	struct {
2548 		/* OTE MSTAT on E3 has a bug where this register's contents are
2549 		 * actually tx_gtxpok + tx_gtxpf + (possibly)tx_gtxpp
2550 		 */
2551 		u32 tx_gtxpok_lo;
2552 		u32 tx_gtxpok_hi;
2553 		u32 tx_gtxpf_lo;
2554 		u32 tx_gtxpf_hi;
2555 		u32 tx_gtxpp_lo;
2556 		u32 tx_gtxpp_hi;
2557 		u32 tx_gtfcs_lo;
2558 		u32 tx_gtfcs_hi;
2559 		u32 tx_gtuca_lo;
2560 		u32 tx_gtuca_hi;
2561 		u32 tx_gtmca_lo;
2562 		u32 tx_gtmca_hi;
2563 		u32 tx_gtgca_lo;
2564 		u32 tx_gtgca_hi;
2565 		u32 tx_gtpkt_lo;
2566 		u32 tx_gtpkt_hi;
2567 		u32 tx_gt64_lo;
2568 		u32 tx_gt64_hi;
2569 		u32 tx_gt127_lo;
2570 		u32 tx_gt127_hi;
2571 		u32 tx_gt255_lo;
2572 		u32 tx_gt255_hi;
2573 		u32 tx_gt511_lo;
2574 		u32 tx_gt511_hi;
2575 		u32 tx_gt1023_lo;
2576 		u32 tx_gt1023_hi;
2577 		u32 tx_gt1518_lo;
2578 		u32 tx_gt1518_hi;
2579 		u32 tx_gt2047_lo;
2580 		u32 tx_gt2047_hi;
2581 		u32 tx_gt4095_lo;
2582 		u32 tx_gt4095_hi;
2583 		u32 tx_gt9216_lo;
2584 		u32 tx_gt9216_hi;
2585 		u32 tx_gt16383_lo;
2586 		u32 tx_gt16383_hi;
2587 		u32 tx_gtufl_lo;
2588 		u32 tx_gtufl_hi;
2589 		u32 tx_gterr_lo;
2590 		u32 tx_gterr_hi;
2591 		u32 tx_gtbyt_lo;
2592 		u32 tx_gtbyt_hi;
2593 		u32 tx_collisions_lo;
2594 		u32 tx_collisions_hi;
2595 		u32 tx_singlecollision_lo;
2596 		u32 tx_singlecollision_hi;
2597 		u32 tx_multiplecollisions_lo;
2598 		u32 tx_multiplecollisions_hi;
2599 		u32 tx_deferred_lo;
2600 		u32 tx_deferred_hi;
2601 		u32 tx_excessivecollisions_lo;
2602 		u32 tx_excessivecollisions_hi;
2603 		u32 tx_latecollisions_lo;
2604 		u32 tx_latecollisions_hi;
2605 	} stats_tx;
2606 
2607 	struct {
2608 		u32 rx_gr64_lo;
2609 		u32 rx_gr64_hi;
2610 		u32 rx_gr127_lo;
2611 		u32 rx_gr127_hi;
2612 		u32 rx_gr255_lo;
2613 		u32 rx_gr255_hi;
2614 		u32 rx_gr511_lo;
2615 		u32 rx_gr511_hi;
2616 		u32 rx_gr1023_lo;
2617 		u32 rx_gr1023_hi;
2618 		u32 rx_gr1518_lo;
2619 		u32 rx_gr1518_hi;
2620 		u32 rx_gr2047_lo;
2621 		u32 rx_gr2047_hi;
2622 		u32 rx_gr4095_lo;
2623 		u32 rx_gr4095_hi;
2624 		u32 rx_gr9216_lo;
2625 		u32 rx_gr9216_hi;
2626 		u32 rx_gr16383_lo;
2627 		u32 rx_gr16383_hi;
2628 		u32 rx_grpkt_lo;
2629 		u32 rx_grpkt_hi;
2630 		u32 rx_grfcs_lo;
2631 		u32 rx_grfcs_hi;
2632 		u32 rx_gruca_lo;
2633 		u32 rx_gruca_hi;
2634 		u32 rx_grmca_lo;
2635 		u32 rx_grmca_hi;
2636 		u32 rx_grbca_lo;
2637 		u32 rx_grbca_hi;
2638 		u32 rx_grxpf_lo;
2639 		u32 rx_grxpf_hi;
2640 		u32 rx_grxpp_lo;
2641 		u32 rx_grxpp_hi;
2642 		u32 rx_grxuo_lo;
2643 		u32 rx_grxuo_hi;
2644 		u32 rx_grovr_lo;
2645 		u32 rx_grovr_hi;
2646 		u32 rx_grxcf_lo;
2647 		u32 rx_grxcf_hi;
2648 		u32 rx_grflr_lo;
2649 		u32 rx_grflr_hi;
2650 		u32 rx_grpok_lo;
2651 		u32 rx_grpok_hi;
2652 		u32 rx_grbyt_lo;
2653 		u32 rx_grbyt_hi;
2654 		u32 rx_grund_lo;
2655 		u32 rx_grund_hi;
2656 		u32 rx_grfrg_lo;
2657 		u32 rx_grfrg_hi;
2658 		u32 rx_grerb_lo;
2659 		u32 rx_grerb_hi;
2660 		u32 rx_grfre_lo;
2661 		u32 rx_grfre_hi;
2662 
2663 		u32 rx_alignmenterrors_lo;
2664 		u32 rx_alignmenterrors_hi;
2665 		u32 rx_falsecarrier_lo;
2666 		u32 rx_falsecarrier_hi;
2667 		u32 rx_llfcmsgcnt_lo;
2668 		u32 rx_llfcmsgcnt_hi;
2669 	} stats_rx;
2670 };
2671 
2672 union mac_stats {
2673 	struct emac_stats	emac_stats;
2674 	struct bmac1_stats	bmac1_stats;
2675 	struct bmac2_stats	bmac2_stats;
2676 	struct mstat_stats	mstat_stats;
2677 };
2678 
2679 
2680 struct mac_stx {
2681 	/* in_bad_octets */
2682 	u32     rx_stat_ifhcinbadoctets_hi;
2683 	u32     rx_stat_ifhcinbadoctets_lo;
2684 
2685 	/* out_bad_octets */
2686 	u32     tx_stat_ifhcoutbadoctets_hi;
2687 	u32     tx_stat_ifhcoutbadoctets_lo;
2688 
2689 	/* crc_receive_errors */
2690 	u32     rx_stat_dot3statsfcserrors_hi;
2691 	u32     rx_stat_dot3statsfcserrors_lo;
2692 	/* alignment_errors */
2693 	u32     rx_stat_dot3statsalignmenterrors_hi;
2694 	u32     rx_stat_dot3statsalignmenterrors_lo;
2695 	/* carrier_sense_errors */
2696 	u32     rx_stat_dot3statscarriersenseerrors_hi;
2697 	u32     rx_stat_dot3statscarriersenseerrors_lo;
2698 	/* false_carrier_detections */
2699 	u32     rx_stat_falsecarriererrors_hi;
2700 	u32     rx_stat_falsecarriererrors_lo;
2701 
2702 	/* runt_packets_received */
2703 	u32     rx_stat_etherstatsundersizepkts_hi;
2704 	u32     rx_stat_etherstatsundersizepkts_lo;
2705 	/* jabber_packets_received */
2706 	u32     rx_stat_dot3statsframestoolong_hi;
2707 	u32     rx_stat_dot3statsframestoolong_lo;
2708 
2709 	/* error_runt_packets_received */
2710 	u32     rx_stat_etherstatsfragments_hi;
2711 	u32     rx_stat_etherstatsfragments_lo;
2712 	/* error_jabber_packets_received */
2713 	u32     rx_stat_etherstatsjabbers_hi;
2714 	u32     rx_stat_etherstatsjabbers_lo;
2715 
2716 	/* control_frames_received */
2717 	u32     rx_stat_maccontrolframesreceived_hi;
2718 	u32     rx_stat_maccontrolframesreceived_lo;
2719 	u32     rx_stat_mac_xpf_hi;
2720 	u32     rx_stat_mac_xpf_lo;
2721 	u32     rx_stat_mac_xcf_hi;
2722 	u32     rx_stat_mac_xcf_lo;
2723 
2724 	/* xoff_state_entered */
2725 	u32     rx_stat_xoffstateentered_hi;
2726 	u32     rx_stat_xoffstateentered_lo;
2727 	/* pause_xon_frames_received */
2728 	u32     rx_stat_xonpauseframesreceived_hi;
2729 	u32     rx_stat_xonpauseframesreceived_lo;
2730 	/* pause_xoff_frames_received */
2731 	u32     rx_stat_xoffpauseframesreceived_hi;
2732 	u32     rx_stat_xoffpauseframesreceived_lo;
2733 	/* pause_xon_frames_transmitted */
2734 	u32     tx_stat_outxonsent_hi;
2735 	u32     tx_stat_outxonsent_lo;
2736 	/* pause_xoff_frames_transmitted */
2737 	u32     tx_stat_outxoffsent_hi;
2738 	u32     tx_stat_outxoffsent_lo;
2739 	/* flow_control_done */
2740 	u32     tx_stat_flowcontroldone_hi;
2741 	u32     tx_stat_flowcontroldone_lo;
2742 
2743 	/* ether_stats_collisions */
2744 	u32     tx_stat_etherstatscollisions_hi;
2745 	u32     tx_stat_etherstatscollisions_lo;
2746 	/* single_collision_transmit_frames */
2747 	u32     tx_stat_dot3statssinglecollisionframes_hi;
2748 	u32     tx_stat_dot3statssinglecollisionframes_lo;
2749 	/* multiple_collision_transmit_frames */
2750 	u32     tx_stat_dot3statsmultiplecollisionframes_hi;
2751 	u32     tx_stat_dot3statsmultiplecollisionframes_lo;
2752 	/* deferred_transmissions */
2753 	u32     tx_stat_dot3statsdeferredtransmissions_hi;
2754 	u32     tx_stat_dot3statsdeferredtransmissions_lo;
2755 	/* excessive_collision_frames */
2756 	u32     tx_stat_dot3statsexcessivecollisions_hi;
2757 	u32     tx_stat_dot3statsexcessivecollisions_lo;
2758 	/* late_collision_frames */
2759 	u32     tx_stat_dot3statslatecollisions_hi;
2760 	u32     tx_stat_dot3statslatecollisions_lo;
2761 
2762 	/* frames_transmitted_64_bytes */
2763 	u32     tx_stat_etherstatspkts64octets_hi;
2764 	u32     tx_stat_etherstatspkts64octets_lo;
2765 	/* frames_transmitted_65_127_bytes */
2766 	u32     tx_stat_etherstatspkts65octetsto127octets_hi;
2767 	u32     tx_stat_etherstatspkts65octetsto127octets_lo;
2768 	/* frames_transmitted_128_255_bytes */
2769 	u32     tx_stat_etherstatspkts128octetsto255octets_hi;
2770 	u32     tx_stat_etherstatspkts128octetsto255octets_lo;
2771 	/* frames_transmitted_256_511_bytes */
2772 	u32     tx_stat_etherstatspkts256octetsto511octets_hi;
2773 	u32     tx_stat_etherstatspkts256octetsto511octets_lo;
2774 	/* frames_transmitted_512_1023_bytes */
2775 	u32     tx_stat_etherstatspkts512octetsto1023octets_hi;
2776 	u32     tx_stat_etherstatspkts512octetsto1023octets_lo;
2777 	/* frames_transmitted_1024_1522_bytes */
2778 	u32     tx_stat_etherstatspkts1024octetsto1522octets_hi;
2779 	u32     tx_stat_etherstatspkts1024octetsto1522octets_lo;
2780 	/* frames_transmitted_1523_9022_bytes */
2781 	u32     tx_stat_etherstatspktsover1522octets_hi;
2782 	u32     tx_stat_etherstatspktsover1522octets_lo;
2783 	u32     tx_stat_mac_2047_hi;
2784 	u32     tx_stat_mac_2047_lo;
2785 	u32     tx_stat_mac_4095_hi;
2786 	u32     tx_stat_mac_4095_lo;
2787 	u32     tx_stat_mac_9216_hi;
2788 	u32     tx_stat_mac_9216_lo;
2789 	u32     tx_stat_mac_16383_hi;
2790 	u32     tx_stat_mac_16383_lo;
2791 
2792 	/* internal_mac_transmit_errors */
2793 	u32     tx_stat_dot3statsinternalmactransmiterrors_hi;
2794 	u32     tx_stat_dot3statsinternalmactransmiterrors_lo;
2795 
2796 	/* if_out_discards */
2797 	u32     tx_stat_mac_ufl_hi;
2798 	u32     tx_stat_mac_ufl_lo;
2799 };
2800 
2801 
2802 #define MAC_STX_IDX_MAX                     2
2803 
2804 struct host_port_stats {
2805 	u32            host_port_stats_counter;
2806 
2807 	struct mac_stx mac_stx[MAC_STX_IDX_MAX];
2808 
2809 	u32            brb_drop_hi;
2810 	u32            brb_drop_lo;
2811 
2812 	u32            not_used; /* obsolete */
2813 	u32            pfc_frames_tx_hi;
2814 	u32            pfc_frames_tx_lo;
2815 	u32            pfc_frames_rx_hi;
2816 	u32            pfc_frames_rx_lo;
2817 
2818 	u32            eee_lpi_count_hi;
2819 	u32            eee_lpi_count_lo;
2820 };
2821 
2822 
2823 struct host_func_stats {
2824 	u32     host_func_stats_start;
2825 
2826 	u32     total_bytes_received_hi;
2827 	u32     total_bytes_received_lo;
2828 
2829 	u32     total_bytes_transmitted_hi;
2830 	u32     total_bytes_transmitted_lo;
2831 
2832 	u32     total_unicast_packets_received_hi;
2833 	u32     total_unicast_packets_received_lo;
2834 
2835 	u32     total_multicast_packets_received_hi;
2836 	u32     total_multicast_packets_received_lo;
2837 
2838 	u32     total_broadcast_packets_received_hi;
2839 	u32     total_broadcast_packets_received_lo;
2840 
2841 	u32     total_unicast_packets_transmitted_hi;
2842 	u32     total_unicast_packets_transmitted_lo;
2843 
2844 	u32     total_multicast_packets_transmitted_hi;
2845 	u32     total_multicast_packets_transmitted_lo;
2846 
2847 	u32     total_broadcast_packets_transmitted_hi;
2848 	u32     total_broadcast_packets_transmitted_lo;
2849 
2850 	u32     valid_bytes_received_hi;
2851 	u32     valid_bytes_received_lo;
2852 
2853 	u32     host_func_stats_end;
2854 };
2855 
2856 /* VIC definitions */
2857 #define VICSTATST_UIF_INDEX 2
2858 
2859 
2860 /* stats collected for afex.
2861  * NOTE: structure is exactly as expected to be received by the switch.
2862  *       order must remain exactly as is unless protocol changes !
2863  */
2864 struct afex_stats {
2865 	u32 tx_unicast_frames_hi;
2866 	u32 tx_unicast_frames_lo;
2867 	u32 tx_unicast_bytes_hi;
2868 	u32 tx_unicast_bytes_lo;
2869 	u32 tx_multicast_frames_hi;
2870 	u32 tx_multicast_frames_lo;
2871 	u32 tx_multicast_bytes_hi;
2872 	u32 tx_multicast_bytes_lo;
2873 	u32 tx_broadcast_frames_hi;
2874 	u32 tx_broadcast_frames_lo;
2875 	u32 tx_broadcast_bytes_hi;
2876 	u32 tx_broadcast_bytes_lo;
2877 	u32 tx_frames_discarded_hi;
2878 	u32 tx_frames_discarded_lo;
2879 	u32 tx_frames_dropped_hi;
2880 	u32 tx_frames_dropped_lo;
2881 
2882 	u32 rx_unicast_frames_hi;
2883 	u32 rx_unicast_frames_lo;
2884 	u32 rx_unicast_bytes_hi;
2885 	u32 rx_unicast_bytes_lo;
2886 	u32 rx_multicast_frames_hi;
2887 	u32 rx_multicast_frames_lo;
2888 	u32 rx_multicast_bytes_hi;
2889 	u32 rx_multicast_bytes_lo;
2890 	u32 rx_broadcast_frames_hi;
2891 	u32 rx_broadcast_frames_lo;
2892 	u32 rx_broadcast_bytes_hi;
2893 	u32 rx_broadcast_bytes_lo;
2894 	u32 rx_frames_discarded_hi;
2895 	u32 rx_frames_discarded_lo;
2896 	u32 rx_frames_dropped_hi;
2897 	u32 rx_frames_dropped_lo;
2898 };
2899 
2900 #define BCM_5710_FW_MAJOR_VERSION			7
2901 #define BCM_5710_FW_MINOR_VERSION			10
2902 #define BCM_5710_FW_REVISION_VERSION		51
2903 #define BCM_5710_FW_ENGINEERING_VERSION		0
2904 #define BCM_5710_FW_COMPILE_FLAGS			1
2905 
2906 
2907 /*
2908  * attention bits
2909  */
2910 struct atten_sp_status_block {
2911 	__le32 attn_bits;
2912 	__le32 attn_bits_ack;
2913 	u8 status_block_id;
2914 	u8 reserved0;
2915 	__le16 attn_bits_index;
2916 	__le32 reserved1;
2917 };
2918 
2919 
2920 /*
2921  * The eth aggregative context of Cstorm
2922  */
2923 struct cstorm_eth_ag_context {
2924 	u32 __reserved0[10];
2925 };
2926 
2927 
2928 /*
2929  * dmae command structure
2930  */
2931 struct dmae_command {
2932 	u32 opcode;
2933 #define DMAE_COMMAND_SRC (0x1<<0)
2934 #define DMAE_COMMAND_SRC_SHIFT 0
2935 #define DMAE_COMMAND_DST (0x3<<1)
2936 #define DMAE_COMMAND_DST_SHIFT 1
2937 #define DMAE_COMMAND_C_DST (0x1<<3)
2938 #define DMAE_COMMAND_C_DST_SHIFT 3
2939 #define DMAE_COMMAND_C_TYPE_ENABLE (0x1<<4)
2940 #define DMAE_COMMAND_C_TYPE_ENABLE_SHIFT 4
2941 #define DMAE_COMMAND_C_TYPE_CRC_ENABLE (0x1<<5)
2942 #define DMAE_COMMAND_C_TYPE_CRC_ENABLE_SHIFT 5
2943 #define DMAE_COMMAND_C_TYPE_CRC_OFFSET (0x7<<6)
2944 #define DMAE_COMMAND_C_TYPE_CRC_OFFSET_SHIFT 6
2945 #define DMAE_COMMAND_ENDIANITY (0x3<<9)
2946 #define DMAE_COMMAND_ENDIANITY_SHIFT 9
2947 #define DMAE_COMMAND_PORT (0x1<<11)
2948 #define DMAE_COMMAND_PORT_SHIFT 11
2949 #define DMAE_COMMAND_CRC_RESET (0x1<<12)
2950 #define DMAE_COMMAND_CRC_RESET_SHIFT 12
2951 #define DMAE_COMMAND_SRC_RESET (0x1<<13)
2952 #define DMAE_COMMAND_SRC_RESET_SHIFT 13
2953 #define DMAE_COMMAND_DST_RESET (0x1<<14)
2954 #define DMAE_COMMAND_DST_RESET_SHIFT 14
2955 #define DMAE_COMMAND_E1HVN (0x3<<15)
2956 #define DMAE_COMMAND_E1HVN_SHIFT 15
2957 #define DMAE_COMMAND_DST_VN (0x3<<17)
2958 #define DMAE_COMMAND_DST_VN_SHIFT 17
2959 #define DMAE_COMMAND_C_FUNC (0x1<<19)
2960 #define DMAE_COMMAND_C_FUNC_SHIFT 19
2961 #define DMAE_COMMAND_ERR_POLICY (0x3<<20)
2962 #define DMAE_COMMAND_ERR_POLICY_SHIFT 20
2963 #define DMAE_COMMAND_RESERVED0 (0x3FF<<22)
2964 #define DMAE_COMMAND_RESERVED0_SHIFT 22
2965 	u32 src_addr_lo;
2966 	u32 src_addr_hi;
2967 	u32 dst_addr_lo;
2968 	u32 dst_addr_hi;
2969 #if defined(__BIG_ENDIAN)
2970 	u16 opcode_iov;
2971 #define DMAE_COMMAND_SRC_VFID (0x3F<<0)
2972 #define DMAE_COMMAND_SRC_VFID_SHIFT 0
2973 #define DMAE_COMMAND_SRC_VFPF (0x1<<6)
2974 #define DMAE_COMMAND_SRC_VFPF_SHIFT 6
2975 #define DMAE_COMMAND_RESERVED1 (0x1<<7)
2976 #define DMAE_COMMAND_RESERVED1_SHIFT 7
2977 #define DMAE_COMMAND_DST_VFID (0x3F<<8)
2978 #define DMAE_COMMAND_DST_VFID_SHIFT 8
2979 #define DMAE_COMMAND_DST_VFPF (0x1<<14)
2980 #define DMAE_COMMAND_DST_VFPF_SHIFT 14
2981 #define DMAE_COMMAND_RESERVED2 (0x1<<15)
2982 #define DMAE_COMMAND_RESERVED2_SHIFT 15
2983 	u16 len;
2984 #elif defined(__LITTLE_ENDIAN)
2985 	u16 len;
2986 	u16 opcode_iov;
2987 #define DMAE_COMMAND_SRC_VFID (0x3F<<0)
2988 #define DMAE_COMMAND_SRC_VFID_SHIFT 0
2989 #define DMAE_COMMAND_SRC_VFPF (0x1<<6)
2990 #define DMAE_COMMAND_SRC_VFPF_SHIFT 6
2991 #define DMAE_COMMAND_RESERVED1 (0x1<<7)
2992 #define DMAE_COMMAND_RESERVED1_SHIFT 7
2993 #define DMAE_COMMAND_DST_VFID (0x3F<<8)
2994 #define DMAE_COMMAND_DST_VFID_SHIFT 8
2995 #define DMAE_COMMAND_DST_VFPF (0x1<<14)
2996 #define DMAE_COMMAND_DST_VFPF_SHIFT 14
2997 #define DMAE_COMMAND_RESERVED2 (0x1<<15)
2998 #define DMAE_COMMAND_RESERVED2_SHIFT 15
2999 #endif
3000 	u32 comp_addr_lo;
3001 	u32 comp_addr_hi;
3002 	u32 comp_val;
3003 	u32 crc32;
3004 	u32 crc32_c;
3005 #if defined(__BIG_ENDIAN)
3006 	u16 crc16_c;
3007 	u16 crc16;
3008 #elif defined(__LITTLE_ENDIAN)
3009 	u16 crc16;
3010 	u16 crc16_c;
3011 #endif
3012 #if defined(__BIG_ENDIAN)
3013 	u16 reserved3;
3014 	u16 crc_t10;
3015 #elif defined(__LITTLE_ENDIAN)
3016 	u16 crc_t10;
3017 	u16 reserved3;
3018 #endif
3019 #if defined(__BIG_ENDIAN)
3020 	u16 xsum8;
3021 	u16 xsum16;
3022 #elif defined(__LITTLE_ENDIAN)
3023 	u16 xsum16;
3024 	u16 xsum8;
3025 #endif
3026 };
3027 
3028 
3029 /*
3030  * common data for all protocols
3031  */
3032 struct doorbell_hdr {
3033 	u8 header;
3034 #define DOORBELL_HDR_RX (0x1<<0)
3035 #define DOORBELL_HDR_RX_SHIFT 0
3036 #define DOORBELL_HDR_DB_TYPE (0x1<<1)
3037 #define DOORBELL_HDR_DB_TYPE_SHIFT 1
3038 #define DOORBELL_HDR_DPM_SIZE (0x3<<2)
3039 #define DOORBELL_HDR_DPM_SIZE_SHIFT 2
3040 #define DOORBELL_HDR_CONN_TYPE (0xF<<4)
3041 #define DOORBELL_HDR_CONN_TYPE_SHIFT 4
3042 };
3043 
3044 /*
3045  * Ethernet doorbell
3046  */
3047 struct eth_tx_doorbell {
3048 #if defined(__BIG_ENDIAN)
3049 	u16 npackets;
3050 	u8 params;
3051 #define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0)
3052 #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0
3053 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6)
3054 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6
3055 #define ETH_TX_DOORBELL_SPARE (0x1<<7)
3056 #define ETH_TX_DOORBELL_SPARE_SHIFT 7
3057 	struct doorbell_hdr hdr;
3058 #elif defined(__LITTLE_ENDIAN)
3059 	struct doorbell_hdr hdr;
3060 	u8 params;
3061 #define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0)
3062 #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0
3063 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6)
3064 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6
3065 #define ETH_TX_DOORBELL_SPARE (0x1<<7)
3066 #define ETH_TX_DOORBELL_SPARE_SHIFT 7
3067 	u16 npackets;
3068 #endif
3069 };
3070 
3071 
3072 /*
3073  * 3 lines. status block
3074  */
3075 struct hc_status_block_e1x {
3076 	__le16 index_values[HC_SB_MAX_INDICES_E1X];
3077 	__le16 running_index[HC_SB_MAX_SM];
3078 	__le32 rsrv[11];
3079 };
3080 
3081 /*
3082  * host status block
3083  */
3084 struct host_hc_status_block_e1x {
3085 	struct hc_status_block_e1x sb;
3086 };
3087 
3088 
3089 /*
3090  * 3 lines. status block
3091  */
3092 struct hc_status_block_e2 {
3093 	__le16 index_values[HC_SB_MAX_INDICES_E2];
3094 	__le16 running_index[HC_SB_MAX_SM];
3095 	__le32 reserved[11];
3096 };
3097 
3098 /*
3099  * host status block
3100  */
3101 struct host_hc_status_block_e2 {
3102 	struct hc_status_block_e2 sb;
3103 };
3104 
3105 
3106 /*
3107  * 5 lines. slow-path status block
3108  */
3109 struct hc_sp_status_block {
3110 	__le16 index_values[HC_SP_SB_MAX_INDICES];
3111 	__le16 running_index;
3112 	__le16 rsrv;
3113 	u32 rsrv1;
3114 };
3115 
3116 /*
3117  * host status block
3118  */
3119 struct host_sp_status_block {
3120 	struct atten_sp_status_block atten_status_block;
3121 	struct hc_sp_status_block sp_sb;
3122 };
3123 
3124 
3125 /*
3126  * IGU driver acknowledgment register
3127  */
3128 struct igu_ack_register {
3129 #if defined(__BIG_ENDIAN)
3130 	u16 sb_id_and_flags;
3131 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0)
3132 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0
3133 #define IGU_ACK_REGISTER_STORM_ID (0x7<<5)
3134 #define IGU_ACK_REGISTER_STORM_ID_SHIFT 5
3135 #define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8)
3136 #define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8
3137 #define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9)
3138 #define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9
3139 #define IGU_ACK_REGISTER_RESERVED (0x1F<<11)
3140 #define IGU_ACK_REGISTER_RESERVED_SHIFT 11
3141 	u16 status_block_index;
3142 #elif defined(__LITTLE_ENDIAN)
3143 	u16 status_block_index;
3144 	u16 sb_id_and_flags;
3145 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0)
3146 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0
3147 #define IGU_ACK_REGISTER_STORM_ID (0x7<<5)
3148 #define IGU_ACK_REGISTER_STORM_ID_SHIFT 5
3149 #define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8)
3150 #define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8
3151 #define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9)
3152 #define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9
3153 #define IGU_ACK_REGISTER_RESERVED (0x1F<<11)
3154 #define IGU_ACK_REGISTER_RESERVED_SHIFT 11
3155 #endif
3156 };
3157 
3158 
3159 /*
3160  * IGU driver acknowledgement register
3161  */
3162 struct igu_backward_compatible {
3163 	u32 sb_id_and_flags;
3164 #define IGU_BACKWARD_COMPATIBLE_SB_INDEX (0xFFFF<<0)
3165 #define IGU_BACKWARD_COMPATIBLE_SB_INDEX_SHIFT 0
3166 #define IGU_BACKWARD_COMPATIBLE_SB_SELECT (0x1F<<16)
3167 #define IGU_BACKWARD_COMPATIBLE_SB_SELECT_SHIFT 16
3168 #define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS (0x7<<21)
3169 #define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS_SHIFT 21
3170 #define IGU_BACKWARD_COMPATIBLE_BUPDATE (0x1<<24)
3171 #define IGU_BACKWARD_COMPATIBLE_BUPDATE_SHIFT 24
3172 #define IGU_BACKWARD_COMPATIBLE_ENABLE_INT (0x3<<25)
3173 #define IGU_BACKWARD_COMPATIBLE_ENABLE_INT_SHIFT 25
3174 #define IGU_BACKWARD_COMPATIBLE_RESERVED_0 (0x1F<<27)
3175 #define IGU_BACKWARD_COMPATIBLE_RESERVED_0_SHIFT 27
3176 	u32 reserved_2;
3177 };
3178 
3179 
3180 /*
3181  * IGU driver acknowledgement register
3182  */
3183 struct igu_regular {
3184 	u32 sb_id_and_flags;
3185 #define IGU_REGULAR_SB_INDEX (0xFFFFF<<0)
3186 #define IGU_REGULAR_SB_INDEX_SHIFT 0
3187 #define IGU_REGULAR_RESERVED0 (0x1<<20)
3188 #define IGU_REGULAR_RESERVED0_SHIFT 20
3189 #define IGU_REGULAR_SEGMENT_ACCESS (0x7<<21)
3190 #define IGU_REGULAR_SEGMENT_ACCESS_SHIFT 21
3191 #define IGU_REGULAR_BUPDATE (0x1<<24)
3192 #define IGU_REGULAR_BUPDATE_SHIFT 24
3193 #define IGU_REGULAR_ENABLE_INT (0x3<<25)
3194 #define IGU_REGULAR_ENABLE_INT_SHIFT 25
3195 #define IGU_REGULAR_RESERVED_1 (0x1<<27)
3196 #define IGU_REGULAR_RESERVED_1_SHIFT 27
3197 #define IGU_REGULAR_CLEANUP_TYPE (0x3<<28)
3198 #define IGU_REGULAR_CLEANUP_TYPE_SHIFT 28
3199 #define IGU_REGULAR_CLEANUP_SET (0x1<<30)
3200 #define IGU_REGULAR_CLEANUP_SET_SHIFT 30
3201 #define IGU_REGULAR_BCLEANUP (0x1<<31)
3202 #define IGU_REGULAR_BCLEANUP_SHIFT 31
3203 	u32 reserved_2;
3204 };
3205 
3206 /*
3207  * IGU driver acknowledgement register
3208  */
3209 union igu_consprod_reg {
3210 	struct igu_regular regular;
3211 	struct igu_backward_compatible backward_compatible;
3212 };
3213 
3214 
3215 /*
3216  * Igu control commands
3217  */
3218 enum igu_ctrl_cmd {
3219 	IGU_CTRL_CMD_TYPE_RD,
3220 	IGU_CTRL_CMD_TYPE_WR,
3221 	MAX_IGU_CTRL_CMD
3222 };
3223 
3224 
3225 /*
3226  * Control register for the IGU command register
3227  */
3228 struct igu_ctrl_reg {
3229 	u32 ctrl_data;
3230 #define IGU_CTRL_REG_ADDRESS (0xFFF<<0)
3231 #define IGU_CTRL_REG_ADDRESS_SHIFT 0
3232 #define IGU_CTRL_REG_FID (0x7F<<12)
3233 #define IGU_CTRL_REG_FID_SHIFT 12
3234 #define IGU_CTRL_REG_RESERVED (0x1<<19)
3235 #define IGU_CTRL_REG_RESERVED_SHIFT 19
3236 #define IGU_CTRL_REG_TYPE (0x1<<20)
3237 #define IGU_CTRL_REG_TYPE_SHIFT 20
3238 #define IGU_CTRL_REG_UNUSED (0x7FF<<21)
3239 #define IGU_CTRL_REG_UNUSED_SHIFT 21
3240 };
3241 
3242 
3243 /*
3244  * Igu interrupt command
3245  */
3246 enum igu_int_cmd {
3247 	IGU_INT_ENABLE,
3248 	IGU_INT_DISABLE,
3249 	IGU_INT_NOP,
3250 	IGU_INT_NOP2,
3251 	MAX_IGU_INT_CMD
3252 };
3253 
3254 
3255 /*
3256  * Igu segments
3257  */
3258 enum igu_seg_access {
3259 	IGU_SEG_ACCESS_NORM,
3260 	IGU_SEG_ACCESS_DEF,
3261 	IGU_SEG_ACCESS_ATTN,
3262 	MAX_IGU_SEG_ACCESS
3263 };
3264 
3265 
3266 /*
3267  * Parser parsing flags field
3268  */
3269 struct parsing_flags {
3270 	__le16 flags;
3271 #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE (0x1<<0)
3272 #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE_SHIFT 0
3273 #define PARSING_FLAGS_VLAN (0x1<<1)
3274 #define PARSING_FLAGS_VLAN_SHIFT 1
3275 #define PARSING_FLAGS_EXTRA_VLAN (0x1<<2)
3276 #define PARSING_FLAGS_EXTRA_VLAN_SHIFT 2
3277 #define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL (0x3<<3)
3278 #define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT 3
3279 #define PARSING_FLAGS_IP_OPTIONS (0x1<<5)
3280 #define PARSING_FLAGS_IP_OPTIONS_SHIFT 5
3281 #define PARSING_FLAGS_FRAGMENTATION_STATUS (0x1<<6)
3282 #define PARSING_FLAGS_FRAGMENTATION_STATUS_SHIFT 6
3283 #define PARSING_FLAGS_OVER_IP_PROTOCOL (0x3<<7)
3284 #define PARSING_FLAGS_OVER_IP_PROTOCOL_SHIFT 7
3285 #define PARSING_FLAGS_PURE_ACK_INDICATION (0x1<<9)
3286 #define PARSING_FLAGS_PURE_ACK_INDICATION_SHIFT 9
3287 #define PARSING_FLAGS_TCP_OPTIONS_EXIST (0x1<<10)
3288 #define PARSING_FLAGS_TCP_OPTIONS_EXIST_SHIFT 10
3289 #define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG (0x1<<11)
3290 #define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG_SHIFT 11
3291 #define PARSING_FLAGS_CONNECTION_MATCH (0x1<<12)
3292 #define PARSING_FLAGS_CONNECTION_MATCH_SHIFT 12
3293 #define PARSING_FLAGS_LLC_SNAP (0x1<<13)
3294 #define PARSING_FLAGS_LLC_SNAP_SHIFT 13
3295 #define PARSING_FLAGS_RESERVED0 (0x3<<14)
3296 #define PARSING_FLAGS_RESERVED0_SHIFT 14
3297 };
3298 
3299 
3300 /*
3301  * Parsing flags for TCP ACK type
3302  */
3303 enum prs_flags_ack_type {
3304 	PRS_FLAG_PUREACK_PIGGY,
3305 	PRS_FLAG_PUREACK_PURE,
3306 	MAX_PRS_FLAGS_ACK_TYPE
3307 };
3308 
3309 
3310 /*
3311  * Parsing flags for Ethernet address type
3312  */
3313 enum prs_flags_eth_addr_type {
3314 	PRS_FLAG_ETHTYPE_NON_UNICAST,
3315 	PRS_FLAG_ETHTYPE_UNICAST,
3316 	MAX_PRS_FLAGS_ETH_ADDR_TYPE
3317 };
3318 
3319 
3320 /*
3321  * Parsing flags for over-ethernet protocol
3322  */
3323 enum prs_flags_over_eth {
3324 	PRS_FLAG_OVERETH_UNKNOWN,
3325 	PRS_FLAG_OVERETH_IPV4,
3326 	PRS_FLAG_OVERETH_IPV6,
3327 	PRS_FLAG_OVERETH_LLCSNAP_UNKNOWN,
3328 	MAX_PRS_FLAGS_OVER_ETH
3329 };
3330 
3331 
3332 /*
3333  * Parsing flags for over-IP protocol
3334  */
3335 enum prs_flags_over_ip {
3336 	PRS_FLAG_OVERIP_UNKNOWN,
3337 	PRS_FLAG_OVERIP_TCP,
3338 	PRS_FLAG_OVERIP_UDP,
3339 	MAX_PRS_FLAGS_OVER_IP
3340 };
3341 
3342 
3343 /*
3344  * SDM operation gen command (generate aggregative interrupt)
3345  */
3346 struct sdm_op_gen {
3347 	__le32 command;
3348 #define SDM_OP_GEN_COMP_PARAM (0x1F<<0)
3349 #define SDM_OP_GEN_COMP_PARAM_SHIFT 0
3350 #define SDM_OP_GEN_COMP_TYPE (0x7<<5)
3351 #define SDM_OP_GEN_COMP_TYPE_SHIFT 5
3352 #define SDM_OP_GEN_AGG_VECT_IDX (0xFF<<8)
3353 #define SDM_OP_GEN_AGG_VECT_IDX_SHIFT 8
3354 #define SDM_OP_GEN_AGG_VECT_IDX_VALID (0x1<<16)
3355 #define SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT 16
3356 #define SDM_OP_GEN_RESERVED (0x7FFF<<17)
3357 #define SDM_OP_GEN_RESERVED_SHIFT 17
3358 };
3359 
3360 
3361 /*
3362  * Timers connection context
3363  */
3364 struct timers_block_context {
3365 	u32 __reserved_0;
3366 	u32 __reserved_1;
3367 	u32 __reserved_2;
3368 	u32 flags;
3369 #define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS (0x3<<0)
3370 #define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS_SHIFT 0
3371 #define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG (0x1<<2)
3372 #define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG_SHIFT 2
3373 #define __TIMERS_BLOCK_CONTEXT_RESERVED0 (0x1FFFFFFF<<3)
3374 #define __TIMERS_BLOCK_CONTEXT_RESERVED0_SHIFT 3
3375 };
3376 
3377 
3378 /*
3379  * The eth aggregative context of Tstorm
3380  */
3381 struct tstorm_eth_ag_context {
3382 	u32 __reserved0[14];
3383 };
3384 
3385 
3386 /*
3387  * The eth aggregative context of Ustorm
3388  */
3389 struct ustorm_eth_ag_context {
3390 	u32 __reserved0;
3391 #if defined(__BIG_ENDIAN)
3392 	u8 cdu_usage;
3393 	u8 __reserved2;
3394 	u16 __reserved1;
3395 #elif defined(__LITTLE_ENDIAN)
3396 	u16 __reserved1;
3397 	u8 __reserved2;
3398 	u8 cdu_usage;
3399 #endif
3400 	u32 __reserved3[6];
3401 };
3402 
3403 
3404 /*
3405  * The eth aggregative context of Xstorm
3406  */
3407 struct xstorm_eth_ag_context {
3408 	u32 reserved0;
3409 #if defined(__BIG_ENDIAN)
3410 	u8 cdu_reserved;
3411 	u8 reserved2;
3412 	u16 reserved1;
3413 #elif defined(__LITTLE_ENDIAN)
3414 	u16 reserved1;
3415 	u8 reserved2;
3416 	u8 cdu_reserved;
3417 #endif
3418 	u32 reserved3[30];
3419 };
3420 
3421 
3422 /*
3423  * doorbell message sent to the chip
3424  */
3425 struct doorbell {
3426 #if defined(__BIG_ENDIAN)
3427 	u16 zero_fill2;
3428 	u8 zero_fill1;
3429 	struct doorbell_hdr header;
3430 #elif defined(__LITTLE_ENDIAN)
3431 	struct doorbell_hdr header;
3432 	u8 zero_fill1;
3433 	u16 zero_fill2;
3434 #endif
3435 };
3436 
3437 
3438 /*
3439  * doorbell message sent to the chip
3440  */
3441 struct doorbell_set_prod {
3442 #if defined(__BIG_ENDIAN)
3443 	u16 prod;
3444 	u8 zero_fill1;
3445 	struct doorbell_hdr header;
3446 #elif defined(__LITTLE_ENDIAN)
3447 	struct doorbell_hdr header;
3448 	u8 zero_fill1;
3449 	u16 prod;
3450 #endif
3451 };
3452 
3453 
3454 struct regpair {
3455 	__le32 lo;
3456 	__le32 hi;
3457 };
3458 
3459 struct regpair_native {
3460 	u32 lo;
3461 	u32 hi;
3462 };
3463 
3464 /*
3465  * Classify rule opcodes in E2/E3
3466  */
3467 enum classify_rule {
3468 	CLASSIFY_RULE_OPCODE_MAC,
3469 	CLASSIFY_RULE_OPCODE_VLAN,
3470 	CLASSIFY_RULE_OPCODE_PAIR,
3471 	CLASSIFY_RULE_OPCODE_VXLAN,
3472 	MAX_CLASSIFY_RULE
3473 };
3474 
3475 
3476 /*
3477  * Classify rule types in E2/E3
3478  */
3479 enum classify_rule_action_type {
3480 	CLASSIFY_RULE_REMOVE,
3481 	CLASSIFY_RULE_ADD,
3482 	MAX_CLASSIFY_RULE_ACTION_TYPE
3483 };
3484 
3485 
3486 /*
3487  * client init ramrod data
3488  */
3489 struct client_init_general_data {
3490 	u8 client_id;
3491 	u8 statistics_counter_id;
3492 	u8 statistics_en_flg;
3493 	u8 is_fcoe_flg;
3494 	u8 activate_flg;
3495 	u8 sp_client_id;
3496 	__le16 mtu;
3497 	u8 statistics_zero_flg;
3498 	u8 func_id;
3499 	u8 cos;
3500 	u8 traffic_type;
3501 	u8 fp_hsi_ver;
3502 	u8 reserved0[3];
3503 };
3504 
3505 
3506 /*
3507  * client init rx data
3508  */
3509 struct client_init_rx_data {
3510 	u8 tpa_en;
3511 #define CLIENT_INIT_RX_DATA_TPA_EN_IPV4 (0x1<<0)
3512 #define CLIENT_INIT_RX_DATA_TPA_EN_IPV4_SHIFT 0
3513 #define CLIENT_INIT_RX_DATA_TPA_EN_IPV6 (0x1<<1)
3514 #define CLIENT_INIT_RX_DATA_TPA_EN_IPV6_SHIFT 1
3515 #define CLIENT_INIT_RX_DATA_TPA_MODE (0x1<<2)
3516 #define CLIENT_INIT_RX_DATA_TPA_MODE_SHIFT 2
3517 #define CLIENT_INIT_RX_DATA_RESERVED5 (0x1F<<3)
3518 #define CLIENT_INIT_RX_DATA_RESERVED5_SHIFT 3
3519 	u8 vmqueue_mode_en_flg;
3520 	u8 extra_data_over_sgl_en_flg;
3521 	u8 cache_line_alignment_log_size;
3522 	u8 enable_dynamic_hc;
3523 	u8 max_sges_for_packet;
3524 	u8 client_qzone_id;
3525 	u8 drop_ip_cs_err_flg;
3526 	u8 drop_tcp_cs_err_flg;
3527 	u8 drop_ttl0_flg;
3528 	u8 drop_udp_cs_err_flg;
3529 	u8 inner_vlan_removal_enable_flg;
3530 	u8 outer_vlan_removal_enable_flg;
3531 	u8 status_block_id;
3532 	u8 rx_sb_index_number;
3533 	u8 dont_verify_rings_pause_thr_flg;
3534 	u8 max_tpa_queues;
3535 	u8 silent_vlan_removal_flg;
3536 	__le16 max_bytes_on_bd;
3537 	__le16 sge_buff_size;
3538 	u8 approx_mcast_engine_id;
3539 	u8 rss_engine_id;
3540 	struct regpair bd_page_base;
3541 	struct regpair sge_page_base;
3542 	struct regpair cqe_page_base;
3543 	u8 is_leading_rss;
3544 	u8 is_approx_mcast;
3545 	__le16 max_agg_size;
3546 	__le16 state;
3547 #define CLIENT_INIT_RX_DATA_UCAST_DROP_ALL (0x1<<0)
3548 #define CLIENT_INIT_RX_DATA_UCAST_DROP_ALL_SHIFT 0
3549 #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL (0x1<<1)
3550 #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL_SHIFT 1
3551 #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED (0x1<<2)
3552 #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED_SHIFT 2
3553 #define CLIENT_INIT_RX_DATA_MCAST_DROP_ALL (0x1<<3)
3554 #define CLIENT_INIT_RX_DATA_MCAST_DROP_ALL_SHIFT 3
3555 #define CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL (0x1<<4)
3556 #define CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL_SHIFT 4
3557 #define CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL (0x1<<5)
3558 #define CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL_SHIFT 5
3559 #define CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN (0x1<<6)
3560 #define CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN_SHIFT 6
3561 #define CLIENT_INIT_RX_DATA_RESERVED2 (0x1FF<<7)
3562 #define CLIENT_INIT_RX_DATA_RESERVED2_SHIFT 7
3563 	__le16 cqe_pause_thr_low;
3564 	__le16 cqe_pause_thr_high;
3565 	__le16 bd_pause_thr_low;
3566 	__le16 bd_pause_thr_high;
3567 	__le16 sge_pause_thr_low;
3568 	__le16 sge_pause_thr_high;
3569 	__le16 rx_cos_mask;
3570 	__le16 silent_vlan_value;
3571 	__le16 silent_vlan_mask;
3572 	u8 handle_ptp_pkts_flg;
3573 	u8 reserved6[3];
3574 	__le32 reserved7;
3575 };
3576 
3577 /*
3578  * client init tx data
3579  */
3580 struct client_init_tx_data {
3581 	u8 enforce_security_flg;
3582 	u8 tx_status_block_id;
3583 	u8 tx_sb_index_number;
3584 	u8 tss_leading_client_id;
3585 	u8 tx_switching_flg;
3586 	u8 anti_spoofing_flg;
3587 	__le16 default_vlan;
3588 	struct regpair tx_bd_page_base;
3589 	__le16 state;
3590 #define CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL (0x1<<0)
3591 #define CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL_SHIFT 0
3592 #define CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL (0x1<<1)
3593 #define CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL_SHIFT 1
3594 #define CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL (0x1<<2)
3595 #define CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL_SHIFT 2
3596 #define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN (0x1<<3)
3597 #define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN_SHIFT 3
3598 #define CLIENT_INIT_TX_DATA_RESERVED0 (0xFFF<<4)
3599 #define CLIENT_INIT_TX_DATA_RESERVED0_SHIFT 4
3600 	u8 default_vlan_flg;
3601 	u8 force_default_pri_flg;
3602 	u8 tunnel_lso_inc_ip_id;
3603 	u8 refuse_outband_vlan_flg;
3604 	u8 tunnel_non_lso_pcsum_location;
3605 	u8 tunnel_non_lso_outer_ip_csum_location;
3606 };
3607 
3608 /*
3609  * client init ramrod data
3610  */
3611 struct client_init_ramrod_data {
3612 	struct client_init_general_data general;
3613 	struct client_init_rx_data rx;
3614 	struct client_init_tx_data tx;
3615 };
3616 
3617 
3618 /*
3619  * client update ramrod data
3620  */
3621 struct client_update_ramrod_data {
3622 	u8 client_id;
3623 	u8 func_id;
3624 	u8 inner_vlan_removal_enable_flg;
3625 	u8 inner_vlan_removal_change_flg;
3626 	u8 outer_vlan_removal_enable_flg;
3627 	u8 outer_vlan_removal_change_flg;
3628 	u8 anti_spoofing_enable_flg;
3629 	u8 anti_spoofing_change_flg;
3630 	u8 activate_flg;
3631 	u8 activate_change_flg;
3632 	__le16 default_vlan;
3633 	u8 default_vlan_enable_flg;
3634 	u8 default_vlan_change_flg;
3635 	__le16 silent_vlan_value;
3636 	__le16 silent_vlan_mask;
3637 	u8 silent_vlan_removal_flg;
3638 	u8 silent_vlan_change_flg;
3639 	u8 refuse_outband_vlan_flg;
3640 	u8 refuse_outband_vlan_change_flg;
3641 	u8 tx_switching_flg;
3642 	u8 tx_switching_change_flg;
3643 	u8 handle_ptp_pkts_flg;
3644 	u8 handle_ptp_pkts_change_flg;
3645 	__le16 reserved1;
3646 	__le32 echo;
3647 };
3648 
3649 
3650 /*
3651  * The eth storm context of Cstorm
3652  */
3653 struct cstorm_eth_st_context {
3654 	u32 __reserved0[4];
3655 };
3656 
3657 
3658 struct double_regpair {
3659 	u32 regpair0_lo;
3660 	u32 regpair0_hi;
3661 	u32 regpair1_lo;
3662 	u32 regpair1_hi;
3663 };
3664 
3665 /* 2nd parse bd type used in ethernet tx BDs */
3666 enum eth_2nd_parse_bd_type {
3667 	ETH_2ND_PARSE_BD_TYPE_LSO_TUNNEL,
3668 	MAX_ETH_2ND_PARSE_BD_TYPE
3669 };
3670 
3671 /*
3672  * Ethernet address typesm used in ethernet tx BDs
3673  */
3674 enum eth_addr_type {
3675 	UNKNOWN_ADDRESS,
3676 	UNICAST_ADDRESS,
3677 	MULTICAST_ADDRESS,
3678 	BROADCAST_ADDRESS,
3679 	MAX_ETH_ADDR_TYPE
3680 };
3681 
3682 
3683 /*
3684  *
3685  */
3686 struct eth_classify_cmd_header {
3687 	u8 cmd_general_data;
3688 #define ETH_CLASSIFY_CMD_HEADER_RX_CMD (0x1<<0)
3689 #define ETH_CLASSIFY_CMD_HEADER_RX_CMD_SHIFT 0
3690 #define ETH_CLASSIFY_CMD_HEADER_TX_CMD (0x1<<1)
3691 #define ETH_CLASSIFY_CMD_HEADER_TX_CMD_SHIFT 1
3692 #define ETH_CLASSIFY_CMD_HEADER_OPCODE (0x3<<2)
3693 #define ETH_CLASSIFY_CMD_HEADER_OPCODE_SHIFT 2
3694 #define ETH_CLASSIFY_CMD_HEADER_IS_ADD (0x1<<4)
3695 #define ETH_CLASSIFY_CMD_HEADER_IS_ADD_SHIFT 4
3696 #define ETH_CLASSIFY_CMD_HEADER_RESERVED0 (0x7<<5)
3697 #define ETH_CLASSIFY_CMD_HEADER_RESERVED0_SHIFT 5
3698 	u8 func_id;
3699 	u8 client_id;
3700 	u8 reserved1;
3701 };
3702 
3703 
3704 /*
3705  * header for eth classification config ramrod
3706  */
3707 struct eth_classify_header {
3708 	u8 rule_cnt;
3709 	u8 reserved0;
3710 	__le16 reserved1;
3711 	__le32 echo;
3712 };
3713 
3714 
3715 /*
3716  * Command for adding/removing a MAC classification rule
3717  */
3718 struct eth_classify_mac_cmd {
3719 	struct eth_classify_cmd_header header;
3720 	__le16 reserved0;
3721 	__le16 inner_mac;
3722 	__le16 mac_lsb;
3723 	__le16 mac_mid;
3724 	__le16 mac_msb;
3725 	__le16 reserved1;
3726 };
3727 
3728 
3729 /*
3730  * Command for adding/removing a MAC-VLAN pair classification rule
3731  */
3732 struct eth_classify_pair_cmd {
3733 	struct eth_classify_cmd_header header;
3734 	__le16 reserved0;
3735 	__le16 inner_mac;
3736 	__le16 mac_lsb;
3737 	__le16 mac_mid;
3738 	__le16 mac_msb;
3739 	__le16 vlan;
3740 };
3741 
3742 
3743 /*
3744  * Command for adding/removing a VLAN classification rule
3745  */
3746 struct eth_classify_vlan_cmd {
3747 	struct eth_classify_cmd_header header;
3748 	__le32 reserved0;
3749 	__le32 reserved1;
3750 	__le16 reserved2;
3751 	__le16 vlan;
3752 };
3753 
3754 /*
3755  * Command for adding/removing a VXLAN classification rule
3756  */
3757 struct eth_classify_vxlan_cmd {
3758 	struct eth_classify_cmd_header header;
3759 	__le32 vni;
3760 	__le16 inner_mac_lsb;
3761 	__le16 inner_mac_mid;
3762 	__le16 inner_mac_msb;
3763 	__le16 reserved1;
3764 };
3765 
3766 /*
3767  * union for eth classification rule
3768  */
3769 union eth_classify_rule_cmd {
3770 	struct eth_classify_mac_cmd mac;
3771 	struct eth_classify_vlan_cmd vlan;
3772 	struct eth_classify_pair_cmd pair;
3773 	struct eth_classify_vxlan_cmd vxlan;
3774 };
3775 
3776 /*
3777  * parameters for eth classification configuration ramrod
3778  */
3779 struct eth_classify_rules_ramrod_data {
3780 	struct eth_classify_header header;
3781 	union eth_classify_rule_cmd rules[CLASSIFY_RULES_COUNT];
3782 };
3783 
3784 
3785 /*
3786  * The data contain client ID need to the ramrod
3787  */
3788 struct eth_common_ramrod_data {
3789 	__le32 client_id;
3790 	__le32 reserved1;
3791 };
3792 
3793 
3794 /*
3795  * The eth storm context of Ustorm
3796  */
3797 struct ustorm_eth_st_context {
3798 	u32 reserved0[52];
3799 };
3800 
3801 /*
3802  * The eth storm context of Tstorm
3803  */
3804 struct tstorm_eth_st_context {
3805 	u32 __reserved0[28];
3806 };
3807 
3808 /*
3809  * The eth storm context of Xstorm
3810  */
3811 struct xstorm_eth_st_context {
3812 	u32 reserved0[60];
3813 };
3814 
3815 /*
3816  * Ethernet connection context
3817  */
3818 struct eth_context {
3819 	struct ustorm_eth_st_context ustorm_st_context;
3820 	struct tstorm_eth_st_context tstorm_st_context;
3821 	struct xstorm_eth_ag_context xstorm_ag_context;
3822 	struct tstorm_eth_ag_context tstorm_ag_context;
3823 	struct cstorm_eth_ag_context cstorm_ag_context;
3824 	struct ustorm_eth_ag_context ustorm_ag_context;
3825 	struct timers_block_context timers_context;
3826 	struct xstorm_eth_st_context xstorm_st_context;
3827 	struct cstorm_eth_st_context cstorm_st_context;
3828 };
3829 
3830 
3831 /*
3832  * union for sgl and raw data.
3833  */
3834 union eth_sgl_or_raw_data {
3835 	__le16 sgl[8];
3836 	u32 raw_data[4];
3837 };
3838 
3839 /*
3840  * eth FP end aggregation CQE parameters struct
3841  */
3842 struct eth_end_agg_rx_cqe {
3843 	u8 type_error_flags;
3844 #define ETH_END_AGG_RX_CQE_TYPE (0x3<<0)
3845 #define ETH_END_AGG_RX_CQE_TYPE_SHIFT 0
3846 #define ETH_END_AGG_RX_CQE_SGL_RAW_SEL (0x1<<2)
3847 #define ETH_END_AGG_RX_CQE_SGL_RAW_SEL_SHIFT 2
3848 #define ETH_END_AGG_RX_CQE_RESERVED0 (0x1F<<3)
3849 #define ETH_END_AGG_RX_CQE_RESERVED0_SHIFT 3
3850 	u8 reserved1;
3851 	u8 queue_index;
3852 	u8 reserved2;
3853 	__le32 timestamp_delta;
3854 	__le16 num_of_coalesced_segs;
3855 	__le16 pkt_len;
3856 	u8 pure_ack_count;
3857 	u8 reserved3;
3858 	__le16 reserved4;
3859 	union eth_sgl_or_raw_data sgl_or_raw_data;
3860 	__le32 reserved5[8];
3861 };
3862 
3863 
3864 /*
3865  * regular eth FP CQE parameters struct
3866  */
3867 struct eth_fast_path_rx_cqe {
3868 	u8 type_error_flags;
3869 #define ETH_FAST_PATH_RX_CQE_TYPE (0x3<<0)
3870 #define ETH_FAST_PATH_RX_CQE_TYPE_SHIFT 0
3871 #define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL (0x1<<2)
3872 #define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL_SHIFT 2
3873 #define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG (0x1<<3)
3874 #define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG_SHIFT 3
3875 #define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG (0x1<<4)
3876 #define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG_SHIFT 4
3877 #define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG (0x1<<5)
3878 #define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG_SHIFT 5
3879 #define ETH_FAST_PATH_RX_CQE_PTP_PKT (0x1<<6)
3880 #define ETH_FAST_PATH_RX_CQE_PTP_PKT_SHIFT 6
3881 #define ETH_FAST_PATH_RX_CQE_RESERVED0 (0x1<<7)
3882 #define ETH_FAST_PATH_RX_CQE_RESERVED0_SHIFT 7
3883 	u8 status_flags;
3884 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE (0x7<<0)
3885 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE_SHIFT 0
3886 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG (0x1<<3)
3887 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG_SHIFT 3
3888 #define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG (0x1<<4)
3889 #define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG_SHIFT 4
3890 #define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG (0x1<<5)
3891 #define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG_SHIFT 5
3892 #define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG (0x1<<6)
3893 #define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG_SHIFT 6
3894 #define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG (0x1<<7)
3895 #define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG_SHIFT 7
3896 	u8 queue_index;
3897 	u8 placement_offset;
3898 	__le32 rss_hash_result;
3899 	__le16 vlan_tag;
3900 	__le16 pkt_len_or_gro_seg_len;
3901 	__le16 len_on_bd;
3902 	struct parsing_flags pars_flags;
3903 	union eth_sgl_or_raw_data sgl_or_raw_data;
3904 	__le32 reserved1[7];
3905 	u32 marker;
3906 };
3907 
3908 
3909 /*
3910  * Command for setting classification flags for a client
3911  */
3912 struct eth_filter_rules_cmd {
3913 	u8 cmd_general_data;
3914 #define ETH_FILTER_RULES_CMD_RX_CMD (0x1<<0)
3915 #define ETH_FILTER_RULES_CMD_RX_CMD_SHIFT 0
3916 #define ETH_FILTER_RULES_CMD_TX_CMD (0x1<<1)
3917 #define ETH_FILTER_RULES_CMD_TX_CMD_SHIFT 1
3918 #define ETH_FILTER_RULES_CMD_RESERVED0 (0x3F<<2)
3919 #define ETH_FILTER_RULES_CMD_RESERVED0_SHIFT 2
3920 	u8 func_id;
3921 	u8 client_id;
3922 	u8 reserved1;
3923 	__le16 state;
3924 #define ETH_FILTER_RULES_CMD_UCAST_DROP_ALL (0x1<<0)
3925 #define ETH_FILTER_RULES_CMD_UCAST_DROP_ALL_SHIFT 0
3926 #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL (0x1<<1)
3927 #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL_SHIFT 1
3928 #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED (0x1<<2)
3929 #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED_SHIFT 2
3930 #define ETH_FILTER_RULES_CMD_MCAST_DROP_ALL (0x1<<3)
3931 #define ETH_FILTER_RULES_CMD_MCAST_DROP_ALL_SHIFT 3
3932 #define ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL (0x1<<4)
3933 #define ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL_SHIFT 4
3934 #define ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL (0x1<<5)
3935 #define ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL_SHIFT 5
3936 #define ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN (0x1<<6)
3937 #define ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN_SHIFT 6
3938 #define ETH_FILTER_RULES_CMD_RESERVED2 (0x1FF<<7)
3939 #define ETH_FILTER_RULES_CMD_RESERVED2_SHIFT 7
3940 	__le16 reserved3;
3941 	struct regpair reserved4;
3942 };
3943 
3944 
3945 /*
3946  * parameters for eth classification filters ramrod
3947  */
3948 struct eth_filter_rules_ramrod_data {
3949 	struct eth_classify_header header;
3950 	struct eth_filter_rules_cmd rules[FILTER_RULES_COUNT];
3951 };
3952 
3953 /* Hsi version */
3954 enum eth_fp_hsi_ver {
3955 	ETH_FP_HSI_VER_0,
3956 	ETH_FP_HSI_VER_1,
3957 	ETH_FP_HSI_VER_2,
3958 	MAX_ETH_FP_HSI_VER
3959 };
3960 
3961 /*
3962  * parameters for eth classification configuration ramrod
3963  */
3964 struct eth_general_rules_ramrod_data {
3965 	struct eth_classify_header header;
3966 	union eth_classify_rule_cmd rules[CLASSIFY_RULES_COUNT];
3967 };
3968 
3969 
3970 /*
3971  * The data for Halt ramrod
3972  */
3973 struct eth_halt_ramrod_data {
3974 	__le32 client_id;
3975 	__le32 reserved0;
3976 };
3977 
3978 
3979 /*
3980  * destination and source mac address.
3981  */
3982 struct eth_mac_addresses {
3983 #if defined(__BIG_ENDIAN)
3984 	__le16 dst_mid;
3985 	__le16 dst_lo;
3986 #elif defined(__LITTLE_ENDIAN)
3987 	__le16 dst_lo;
3988 	__le16 dst_mid;
3989 #endif
3990 #if defined(__BIG_ENDIAN)
3991 	__le16 src_lo;
3992 	__le16 dst_hi;
3993 #elif defined(__LITTLE_ENDIAN)
3994 	__le16 dst_hi;
3995 	__le16 src_lo;
3996 #endif
3997 #if defined(__BIG_ENDIAN)
3998 	__le16 src_hi;
3999 	__le16 src_mid;
4000 #elif defined(__LITTLE_ENDIAN)
4001 	__le16 src_mid;
4002 	__le16 src_hi;
4003 #endif
4004 };
4005 
4006 /* tunneling related data */
4007 struct eth_tunnel_data {
4008 	__le16 dst_lo;
4009 	__le16 dst_mid;
4010 	__le16 dst_hi;
4011 	__le16 fw_ip_hdr_csum;
4012 	__le16 pseudo_csum;
4013 	u8 ip_hdr_start_inner_w;
4014 	u8 flags;
4015 #define ETH_TUNNEL_DATA_IP_HDR_TYPE_OUTER (0x1<<0)
4016 #define ETH_TUNNEL_DATA_IP_HDR_TYPE_OUTER_SHIFT 0
4017 #define ETH_TUNNEL_DATA_RESERVED (0x7F<<1)
4018 #define ETH_TUNNEL_DATA_RESERVED_SHIFT 1
4019 };
4020 
4021 /* union for mac addresses and for tunneling data.
4022  * considered as tunneling data only if (tunnel_exist == 1).
4023  */
4024 union eth_mac_addr_or_tunnel_data {
4025 	struct eth_mac_addresses mac_addr;
4026 	struct eth_tunnel_data tunnel_data;
4027 };
4028 
4029 /*Command for setting multicast classification for a client */
4030 struct eth_multicast_rules_cmd {
4031 	u8 cmd_general_data;
4032 #define ETH_MULTICAST_RULES_CMD_RX_CMD (0x1<<0)
4033 #define ETH_MULTICAST_RULES_CMD_RX_CMD_SHIFT 0
4034 #define ETH_MULTICAST_RULES_CMD_TX_CMD (0x1<<1)
4035 #define ETH_MULTICAST_RULES_CMD_TX_CMD_SHIFT 1
4036 #define ETH_MULTICAST_RULES_CMD_IS_ADD (0x1<<2)
4037 #define ETH_MULTICAST_RULES_CMD_IS_ADD_SHIFT 2
4038 #define ETH_MULTICAST_RULES_CMD_RESERVED0 (0x1F<<3)
4039 #define ETH_MULTICAST_RULES_CMD_RESERVED0_SHIFT 3
4040 	u8 func_id;
4041 	u8 bin_id;
4042 	u8 engine_id;
4043 	__le32 reserved2;
4044 	struct regpair reserved3;
4045 };
4046 
4047 /*
4048  * parameters for multicast classification ramrod
4049  */
4050 struct eth_multicast_rules_ramrod_data {
4051 	struct eth_classify_header header;
4052 	struct eth_multicast_rules_cmd rules[MULTICAST_RULES_COUNT];
4053 };
4054 
4055 /*
4056  * Place holder for ramrods protocol specific data
4057  */
4058 struct ramrod_data {
4059 	__le32 data_lo;
4060 	__le32 data_hi;
4061 };
4062 
4063 /*
4064  * union for ramrod data for Ethernet protocol (CQE) (force size of 16 bits)
4065  */
4066 union eth_ramrod_data {
4067 	struct ramrod_data general;
4068 };
4069 
4070 
4071 /*
4072  * RSS toeplitz hash type, as reported in CQE
4073  */
4074 enum eth_rss_hash_type {
4075 	DEFAULT_HASH_TYPE,
4076 	IPV4_HASH_TYPE,
4077 	TCP_IPV4_HASH_TYPE,
4078 	IPV6_HASH_TYPE,
4079 	TCP_IPV6_HASH_TYPE,
4080 	VLAN_PRI_HASH_TYPE,
4081 	E1HOV_PRI_HASH_TYPE,
4082 	DSCP_HASH_TYPE,
4083 	MAX_ETH_RSS_HASH_TYPE
4084 };
4085 
4086 
4087 /*
4088  * Ethernet RSS mode
4089  */
4090 enum eth_rss_mode {
4091 	ETH_RSS_MODE_DISABLED,
4092 	ETH_RSS_MODE_REGULAR,
4093 	ETH_RSS_MODE_VLAN_PRI,
4094 	ETH_RSS_MODE_E1HOV_PRI,
4095 	ETH_RSS_MODE_IP_DSCP,
4096 	MAX_ETH_RSS_MODE
4097 };
4098 
4099 
4100 /*
4101  * parameters for RSS update ramrod (E2)
4102  */
4103 struct eth_rss_update_ramrod_data {
4104 	u8 rss_engine_id;
4105 	u8 rss_mode;
4106 	__le16 capabilities;
4107 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY (0x1<<0)
4108 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY_SHIFT 0
4109 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY (0x1<<1)
4110 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY_SHIFT 1
4111 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY (0x1<<2)
4112 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY_SHIFT 2
4113 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_VXLAN_CAPABILITY (0x1<<3)
4114 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_VXLAN_CAPABILITY_SHIFT 3
4115 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY (0x1<<4)
4116 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY_SHIFT 4
4117 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY (0x1<<5)
4118 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY_SHIFT 5
4119 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY (0x1<<6)
4120 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY_SHIFT 6
4121 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_VXLAN_CAPABILITY (0x1<<7)
4122 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_VXLAN_CAPABILITY_SHIFT 7
4123 #define ETH_RSS_UPDATE_RAMROD_DATA_EN_5_TUPLE_CAPABILITY (0x1<<8)
4124 #define ETH_RSS_UPDATE_RAMROD_DATA_EN_5_TUPLE_CAPABILITY_SHIFT 8
4125 #define ETH_RSS_UPDATE_RAMROD_DATA_NVGRE_KEY_ENTROPY_CAPABILITY (0x1<<9)
4126 #define ETH_RSS_UPDATE_RAMROD_DATA_NVGRE_KEY_ENTROPY_CAPABILITY_SHIFT 9
4127 #define ETH_RSS_UPDATE_RAMROD_DATA_GRE_INNER_HDRS_CAPABILITY (0x1<<10)
4128 #define ETH_RSS_UPDATE_RAMROD_DATA_GRE_INNER_HDRS_CAPABILITY_SHIFT 10
4129 #define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY (0x1<<11)
4130 #define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY_SHIFT 11
4131 #define ETH_RSS_UPDATE_RAMROD_DATA_RESERVED (0xF<<12)
4132 #define ETH_RSS_UPDATE_RAMROD_DATA_RESERVED_SHIFT 12
4133 	u8 rss_result_mask;
4134 	u8 reserved3;
4135 	__le16 reserved4;
4136 	u8 indirection_table[T_ETH_INDIRECTION_TABLE_SIZE];
4137 	__le32 rss_key[T_ETH_RSS_KEY];
4138 	__le32 echo;
4139 	__le32 reserved5;
4140 };
4141 
4142 
4143 /*
4144  * The eth Rx Buffer Descriptor
4145  */
4146 struct eth_rx_bd {
4147 	__le32 addr_lo;
4148 	__le32 addr_hi;
4149 };
4150 
4151 
4152 /*
4153  * Eth Rx Cqe structure- general structure for ramrods
4154  */
4155 struct common_ramrod_eth_rx_cqe {
4156 	u8 ramrod_type;
4157 #define COMMON_RAMROD_ETH_RX_CQE_TYPE (0x3<<0)
4158 #define COMMON_RAMROD_ETH_RX_CQE_TYPE_SHIFT 0
4159 #define COMMON_RAMROD_ETH_RX_CQE_ERROR (0x1<<2)
4160 #define COMMON_RAMROD_ETH_RX_CQE_ERROR_SHIFT 2
4161 #define COMMON_RAMROD_ETH_RX_CQE_RESERVED0 (0x1F<<3)
4162 #define COMMON_RAMROD_ETH_RX_CQE_RESERVED0_SHIFT 3
4163 	u8 conn_type;
4164 	__le16 reserved1;
4165 	__le32 conn_and_cmd_data;
4166 #define COMMON_RAMROD_ETH_RX_CQE_CID (0xFFFFFF<<0)
4167 #define COMMON_RAMROD_ETH_RX_CQE_CID_SHIFT 0
4168 #define COMMON_RAMROD_ETH_RX_CQE_CMD_ID (0xFF<<24)
4169 #define COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT 24
4170 	struct ramrod_data protocol_data;
4171 	__le32 echo;
4172 	__le32 reserved2[11];
4173 };
4174 
4175 /*
4176  * Rx Last CQE in page (in ETH)
4177  */
4178 struct eth_rx_cqe_next_page {
4179 	__le32 addr_lo;
4180 	__le32 addr_hi;
4181 	__le32 reserved[14];
4182 };
4183 
4184 /*
4185  * union for all eth rx cqe types (fix their sizes)
4186  */
4187 union eth_rx_cqe {
4188 	struct eth_fast_path_rx_cqe fast_path_cqe;
4189 	struct common_ramrod_eth_rx_cqe ramrod_cqe;
4190 	struct eth_rx_cqe_next_page next_page_cqe;
4191 	struct eth_end_agg_rx_cqe end_agg_cqe;
4192 };
4193 
4194 
4195 /*
4196  * Values for RX ETH CQE type field
4197  */
4198 enum eth_rx_cqe_type {
4199 	RX_ETH_CQE_TYPE_ETH_FASTPATH,
4200 	RX_ETH_CQE_TYPE_ETH_RAMROD,
4201 	RX_ETH_CQE_TYPE_ETH_START_AGG,
4202 	RX_ETH_CQE_TYPE_ETH_STOP_AGG,
4203 	MAX_ETH_RX_CQE_TYPE
4204 };
4205 
4206 
4207 /*
4208  * Type of SGL/Raw field in ETH RX fast path CQE
4209  */
4210 enum eth_rx_fp_sel {
4211 	ETH_FP_CQE_REGULAR,
4212 	ETH_FP_CQE_RAW,
4213 	MAX_ETH_RX_FP_SEL
4214 };
4215 
4216 
4217 /*
4218  * The eth Rx SGE Descriptor
4219  */
4220 struct eth_rx_sge {
4221 	__le32 addr_lo;
4222 	__le32 addr_hi;
4223 };
4224 
4225 
4226 /*
4227  * common data for all protocols
4228  */
4229 struct spe_hdr {
4230 	__le32 conn_and_cmd_data;
4231 #define SPE_HDR_CID (0xFFFFFF<<0)
4232 #define SPE_HDR_CID_SHIFT 0
4233 #define SPE_HDR_CMD_ID (0xFF<<24)
4234 #define SPE_HDR_CMD_ID_SHIFT 24
4235 	__le16 type;
4236 #define SPE_HDR_CONN_TYPE (0xFF<<0)
4237 #define SPE_HDR_CONN_TYPE_SHIFT 0
4238 #define SPE_HDR_FUNCTION_ID (0xFF<<8)
4239 #define SPE_HDR_FUNCTION_ID_SHIFT 8
4240 	__le16 reserved1;
4241 };
4242 
4243 /*
4244  * specific data for ethernet slow path element
4245  */
4246 union eth_specific_data {
4247 	u8 protocol_data[8];
4248 	struct regpair client_update_ramrod_data;
4249 	struct regpair client_init_ramrod_init_data;
4250 	struct eth_halt_ramrod_data halt_ramrod_data;
4251 	struct regpair update_data_addr;
4252 	struct eth_common_ramrod_data common_ramrod_data;
4253 	struct regpair classify_cfg_addr;
4254 	struct regpair filter_cfg_addr;
4255 	struct regpair mcast_cfg_addr;
4256 };
4257 
4258 /*
4259  * Ethernet slow path element
4260  */
4261 struct eth_spe {
4262 	struct spe_hdr hdr;
4263 	union eth_specific_data data;
4264 };
4265 
4266 
4267 /*
4268  * Ethernet command ID for slow path elements
4269  */
4270 enum eth_spqe_cmd_id {
4271 	RAMROD_CMD_ID_ETH_UNUSED,
4272 	RAMROD_CMD_ID_ETH_CLIENT_SETUP,
4273 	RAMROD_CMD_ID_ETH_HALT,
4274 	RAMROD_CMD_ID_ETH_FORWARD_SETUP,
4275 	RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP,
4276 	RAMROD_CMD_ID_ETH_CLIENT_UPDATE,
4277 	RAMROD_CMD_ID_ETH_EMPTY,
4278 	RAMROD_CMD_ID_ETH_TERMINATE,
4279 	RAMROD_CMD_ID_ETH_TPA_UPDATE,
4280 	RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES,
4281 	RAMROD_CMD_ID_ETH_FILTER_RULES,
4282 	RAMROD_CMD_ID_ETH_MULTICAST_RULES,
4283 	RAMROD_CMD_ID_ETH_RSS_UPDATE,
4284 	RAMROD_CMD_ID_ETH_SET_MAC,
4285 	MAX_ETH_SPQE_CMD_ID
4286 };
4287 
4288 
4289 /*
4290  * eth tpa update command
4291  */
4292 enum eth_tpa_update_command {
4293 	TPA_UPDATE_NONE_COMMAND,
4294 	TPA_UPDATE_ENABLE_COMMAND,
4295 	TPA_UPDATE_DISABLE_COMMAND,
4296 	MAX_ETH_TPA_UPDATE_COMMAND
4297 };
4298 
4299 /* In case of LSO over IPv4 tunnel, whether to increment
4300  * IP ID on external IP header or internal IP header
4301  */
4302 enum eth_tunnel_lso_inc_ip_id {
4303 	EXT_HEADER,
4304 	INT_HEADER,
4305 	MAX_ETH_TUNNEL_LSO_INC_IP_ID
4306 };
4307 
4308 /* In case tunnel exist and L4 checksum offload,
4309  * the pseudo checksum location, on packet or on BD.
4310  */
4311 enum eth_tunnel_non_lso_csum_location {
4312 	CSUM_ON_PKT,
4313 	CSUM_ON_BD,
4314 	MAX_ETH_TUNNEL_NON_LSO_CSUM_LOCATION
4315 };
4316 
4317 /*
4318  * Tx regular BD structure
4319  */
4320 struct eth_tx_bd {
4321 	__le32 addr_lo;
4322 	__le32 addr_hi;
4323 	__le16 total_pkt_bytes;
4324 	__le16 nbytes;
4325 	u8 reserved[4];
4326 };
4327 
4328 
4329 /*
4330  * structure for easy accessibility to assembler
4331  */
4332 struct eth_tx_bd_flags {
4333 	u8 as_bitfield;
4334 #define ETH_TX_BD_FLAGS_IP_CSUM (0x1<<0)
4335 #define ETH_TX_BD_FLAGS_IP_CSUM_SHIFT 0
4336 #define ETH_TX_BD_FLAGS_L4_CSUM (0x1<<1)
4337 #define ETH_TX_BD_FLAGS_L4_CSUM_SHIFT 1
4338 #define ETH_TX_BD_FLAGS_VLAN_MODE (0x3<<2)
4339 #define ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT 2
4340 #define ETH_TX_BD_FLAGS_START_BD (0x1<<4)
4341 #define ETH_TX_BD_FLAGS_START_BD_SHIFT 4
4342 #define ETH_TX_BD_FLAGS_IS_UDP (0x1<<5)
4343 #define ETH_TX_BD_FLAGS_IS_UDP_SHIFT 5
4344 #define ETH_TX_BD_FLAGS_SW_LSO (0x1<<6)
4345 #define ETH_TX_BD_FLAGS_SW_LSO_SHIFT 6
4346 #define ETH_TX_BD_FLAGS_IPV6 (0x1<<7)
4347 #define ETH_TX_BD_FLAGS_IPV6_SHIFT 7
4348 };
4349 
4350 /*
4351  * The eth Tx Buffer Descriptor
4352  */
4353 struct eth_tx_start_bd {
4354 	__le32 addr_lo;
4355 	__le32 addr_hi;
4356 	__le16 nbd;
4357 	__le16 nbytes;
4358 	__le16 vlan_or_ethertype;
4359 	struct eth_tx_bd_flags bd_flags;
4360 	u8 general_data;
4361 #define ETH_TX_START_BD_HDR_NBDS (0x7<<0)
4362 #define ETH_TX_START_BD_HDR_NBDS_SHIFT 0
4363 #define ETH_TX_START_BD_NO_ADDED_TAGS (0x1<<3)
4364 #define ETH_TX_START_BD_NO_ADDED_TAGS_SHIFT 3
4365 #define ETH_TX_START_BD_FORCE_VLAN_MODE (0x1<<4)
4366 #define ETH_TX_START_BD_FORCE_VLAN_MODE_SHIFT 4
4367 #define ETH_TX_START_BD_PARSE_NBDS (0x3<<5)
4368 #define ETH_TX_START_BD_PARSE_NBDS_SHIFT 5
4369 #define ETH_TX_START_BD_TUNNEL_EXIST (0x1<<7)
4370 #define ETH_TX_START_BD_TUNNEL_EXIST_SHIFT 7
4371 };
4372 
4373 /*
4374  * Tx parsing BD structure for ETH E1/E1h
4375  */
4376 struct eth_tx_parse_bd_e1x {
4377 	__le16 global_data;
4378 #define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W (0xF<<0)
4379 #define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W_SHIFT 0
4380 #define ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE (0x3<<4)
4381 #define ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE_SHIFT 4
4382 #define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN (0x1<<6)
4383 #define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN_SHIFT 6
4384 #define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN (0x1<<7)
4385 #define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN_SHIFT 7
4386 #define ETH_TX_PARSE_BD_E1X_NS_FLG (0x1<<8)
4387 #define ETH_TX_PARSE_BD_E1X_NS_FLG_SHIFT 8
4388 #define ETH_TX_PARSE_BD_E1X_RESERVED0 (0x7F<<9)
4389 #define ETH_TX_PARSE_BD_E1X_RESERVED0_SHIFT 9
4390 	u8 tcp_flags;
4391 #define ETH_TX_PARSE_BD_E1X_FIN_FLG (0x1<<0)
4392 #define ETH_TX_PARSE_BD_E1X_FIN_FLG_SHIFT 0
4393 #define ETH_TX_PARSE_BD_E1X_SYN_FLG (0x1<<1)
4394 #define ETH_TX_PARSE_BD_E1X_SYN_FLG_SHIFT 1
4395 #define ETH_TX_PARSE_BD_E1X_RST_FLG (0x1<<2)
4396 #define ETH_TX_PARSE_BD_E1X_RST_FLG_SHIFT 2
4397 #define ETH_TX_PARSE_BD_E1X_PSH_FLG (0x1<<3)
4398 #define ETH_TX_PARSE_BD_E1X_PSH_FLG_SHIFT 3
4399 #define ETH_TX_PARSE_BD_E1X_ACK_FLG (0x1<<4)
4400 #define ETH_TX_PARSE_BD_E1X_ACK_FLG_SHIFT 4
4401 #define ETH_TX_PARSE_BD_E1X_URG_FLG (0x1<<5)
4402 #define ETH_TX_PARSE_BD_E1X_URG_FLG_SHIFT 5
4403 #define ETH_TX_PARSE_BD_E1X_ECE_FLG (0x1<<6)
4404 #define ETH_TX_PARSE_BD_E1X_ECE_FLG_SHIFT 6
4405 #define ETH_TX_PARSE_BD_E1X_CWR_FLG (0x1<<7)
4406 #define ETH_TX_PARSE_BD_E1X_CWR_FLG_SHIFT 7
4407 	u8 ip_hlen_w;
4408 	__le16 total_hlen_w;
4409 	__le16 tcp_pseudo_csum;
4410 	__le16 lso_mss;
4411 	__le16 ip_id;
4412 	__le32 tcp_send_seq;
4413 };
4414 
4415 /*
4416  * Tx parsing BD structure for ETH E2
4417  */
4418 struct eth_tx_parse_bd_e2 {
4419 	union eth_mac_addr_or_tunnel_data data;
4420 	__le32 parsing_data;
4421 #define ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W (0x7FF<<0)
4422 #define ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W_SHIFT 0
4423 #define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW (0xF<<11)
4424 #define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW_SHIFT 11
4425 #define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR (0x1<<15)
4426 #define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR_SHIFT 15
4427 #define ETH_TX_PARSE_BD_E2_LSO_MSS (0x3FFF<<16)
4428 #define ETH_TX_PARSE_BD_E2_LSO_MSS_SHIFT 16
4429 #define ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE (0x3<<30)
4430 #define ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE_SHIFT 30
4431 };
4432 
4433 /*
4434  * Tx 2nd parsing BD structure for ETH packet
4435  */
4436 struct eth_tx_parse_2nd_bd {
4437 	__le16 global_data;
4438 #define ETH_TX_PARSE_2ND_BD_IP_HDR_START_OUTER_W (0xF<<0)
4439 #define ETH_TX_PARSE_2ND_BD_IP_HDR_START_OUTER_W_SHIFT 0
4440 #define ETH_TX_PARSE_2ND_BD_RESERVED0 (0x1<<4)
4441 #define ETH_TX_PARSE_2ND_BD_RESERVED0_SHIFT 4
4442 #define ETH_TX_PARSE_2ND_BD_LLC_SNAP_EN (0x1<<5)
4443 #define ETH_TX_PARSE_2ND_BD_LLC_SNAP_EN_SHIFT 5
4444 #define ETH_TX_PARSE_2ND_BD_NS_FLG (0x1<<6)
4445 #define ETH_TX_PARSE_2ND_BD_NS_FLG_SHIFT 6
4446 #define ETH_TX_PARSE_2ND_BD_TUNNEL_UDP_EXIST (0x1<<7)
4447 #define ETH_TX_PARSE_2ND_BD_TUNNEL_UDP_EXIST_SHIFT 7
4448 #define ETH_TX_PARSE_2ND_BD_IP_HDR_LEN_OUTER_W (0x1F<<8)
4449 #define ETH_TX_PARSE_2ND_BD_IP_HDR_LEN_OUTER_W_SHIFT 8
4450 #define ETH_TX_PARSE_2ND_BD_RESERVED1 (0x7<<13)
4451 #define ETH_TX_PARSE_2ND_BD_RESERVED1_SHIFT 13
4452 	u8 bd_type;
4453 #define ETH_TX_PARSE_2ND_BD_TYPE (0xF<<0)
4454 #define ETH_TX_PARSE_2ND_BD_TYPE_SHIFT 0
4455 #define ETH_TX_PARSE_2ND_BD_RESERVED2 (0xF<<4)
4456 #define ETH_TX_PARSE_2ND_BD_RESERVED2_SHIFT 4
4457 	u8 reserved3;
4458 	u8 tcp_flags;
4459 #define ETH_TX_PARSE_2ND_BD_FIN_FLG (0x1<<0)
4460 #define ETH_TX_PARSE_2ND_BD_FIN_FLG_SHIFT 0
4461 #define ETH_TX_PARSE_2ND_BD_SYN_FLG (0x1<<1)
4462 #define ETH_TX_PARSE_2ND_BD_SYN_FLG_SHIFT 1
4463 #define ETH_TX_PARSE_2ND_BD_RST_FLG (0x1<<2)
4464 #define ETH_TX_PARSE_2ND_BD_RST_FLG_SHIFT 2
4465 #define ETH_TX_PARSE_2ND_BD_PSH_FLG (0x1<<3)
4466 #define ETH_TX_PARSE_2ND_BD_PSH_FLG_SHIFT 3
4467 #define ETH_TX_PARSE_2ND_BD_ACK_FLG (0x1<<4)
4468 #define ETH_TX_PARSE_2ND_BD_ACK_FLG_SHIFT 4
4469 #define ETH_TX_PARSE_2ND_BD_URG_FLG (0x1<<5)
4470 #define ETH_TX_PARSE_2ND_BD_URG_FLG_SHIFT 5
4471 #define ETH_TX_PARSE_2ND_BD_ECE_FLG (0x1<<6)
4472 #define ETH_TX_PARSE_2ND_BD_ECE_FLG_SHIFT 6
4473 #define ETH_TX_PARSE_2ND_BD_CWR_FLG (0x1<<7)
4474 #define ETH_TX_PARSE_2ND_BD_CWR_FLG_SHIFT 7
4475 	u8 reserved4;
4476 	u8 tunnel_udp_hdr_start_w;
4477 	u8 fw_ip_hdr_to_payload_w;
4478 	__le16 fw_ip_csum_wo_len_flags_frag;
4479 	__le16 hw_ip_id;
4480 	__le32 tcp_send_seq;
4481 };
4482 
4483 /* The last BD in the BD memory will hold a pointer to the next BD memory */
4484 struct eth_tx_next_bd {
4485 	__le32 addr_lo;
4486 	__le32 addr_hi;
4487 	u8 reserved[8];
4488 };
4489 
4490 /*
4491  * union for 4 Bd types
4492  */
4493 union eth_tx_bd_types {
4494 	struct eth_tx_start_bd start_bd;
4495 	struct eth_tx_bd reg_bd;
4496 	struct eth_tx_parse_bd_e1x parse_bd_e1x;
4497 	struct eth_tx_parse_bd_e2 parse_bd_e2;
4498 	struct eth_tx_parse_2nd_bd parse_2nd_bd;
4499 	struct eth_tx_next_bd next_bd;
4500 };
4501 
4502 /*
4503  * array of 13 bds as appears in the eth xstorm context
4504  */
4505 struct eth_tx_bds_array {
4506 	union eth_tx_bd_types bds[13];
4507 };
4508 
4509 
4510 /*
4511  * VLAN mode on TX BDs
4512  */
4513 enum eth_tx_vlan_type {
4514 	X_ETH_NO_VLAN,
4515 	X_ETH_OUTBAND_VLAN,
4516 	X_ETH_INBAND_VLAN,
4517 	X_ETH_FW_ADDED_VLAN,
4518 	MAX_ETH_TX_VLAN_TYPE
4519 };
4520 
4521 
4522 /*
4523  * Ethernet VLAN filtering mode in E1x
4524  */
4525 enum eth_vlan_filter_mode {
4526 	ETH_VLAN_FILTER_ANY_VLAN,
4527 	ETH_VLAN_FILTER_SPECIFIC_VLAN,
4528 	ETH_VLAN_FILTER_CLASSIFY,
4529 	MAX_ETH_VLAN_FILTER_MODE
4530 };
4531 
4532 
4533 /*
4534  * MAC filtering configuration command header
4535  */
4536 struct mac_configuration_hdr {
4537 	u8 length;
4538 	u8 offset;
4539 	__le16 client_id;
4540 	__le32 echo;
4541 };
4542 
4543 /*
4544  * MAC address in list for ramrod
4545  */
4546 struct mac_configuration_entry {
4547 	__le16 lsb_mac_addr;
4548 	__le16 middle_mac_addr;
4549 	__le16 msb_mac_addr;
4550 	__le16 vlan_id;
4551 	u8 pf_id;
4552 	u8 flags;
4553 #define MAC_CONFIGURATION_ENTRY_ACTION_TYPE (0x1<<0)
4554 #define MAC_CONFIGURATION_ENTRY_ACTION_TYPE_SHIFT 0
4555 #define MAC_CONFIGURATION_ENTRY_RDMA_MAC (0x1<<1)
4556 #define MAC_CONFIGURATION_ENTRY_RDMA_MAC_SHIFT 1
4557 #define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE (0x3<<2)
4558 #define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE_SHIFT 2
4559 #define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL (0x1<<4)
4560 #define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL_SHIFT 4
4561 #define MAC_CONFIGURATION_ENTRY_BROADCAST (0x1<<5)
4562 #define MAC_CONFIGURATION_ENTRY_BROADCAST_SHIFT 5
4563 #define MAC_CONFIGURATION_ENTRY_RESERVED1 (0x3<<6)
4564 #define MAC_CONFIGURATION_ENTRY_RESERVED1_SHIFT 6
4565 	__le16 reserved0;
4566 	__le32 clients_bit_vector;
4567 };
4568 
4569 /*
4570  * MAC filtering configuration command
4571  */
4572 struct mac_configuration_cmd {
4573 	struct mac_configuration_hdr hdr;
4574 	struct mac_configuration_entry config_table[64];
4575 };
4576 
4577 
4578 /*
4579  * Set-MAC command type (in E1x)
4580  */
4581 enum set_mac_action_type {
4582 	T_ETH_MAC_COMMAND_INVALIDATE,
4583 	T_ETH_MAC_COMMAND_SET,
4584 	MAX_SET_MAC_ACTION_TYPE
4585 };
4586 
4587 
4588 /*
4589  * Ethernet TPA Modes
4590  */
4591 enum tpa_mode {
4592 	TPA_LRO,
4593 	TPA_GRO,
4594 	MAX_TPA_MODE};
4595 
4596 
4597 /*
4598  * tpa update ramrod data
4599  */
4600 struct tpa_update_ramrod_data {
4601 	u8 update_ipv4;
4602 	u8 update_ipv6;
4603 	u8 client_id;
4604 	u8 max_tpa_queues;
4605 	u8 max_sges_for_packet;
4606 	u8 complete_on_both_clients;
4607 	u8 dont_verify_rings_pause_thr_flg;
4608 	u8 tpa_mode;
4609 	__le16 sge_buff_size;
4610 	__le16 max_agg_size;
4611 	__le32 sge_page_base_lo;
4612 	__le32 sge_page_base_hi;
4613 	__le16 sge_pause_thr_low;
4614 	__le16 sge_pause_thr_high;
4615 };
4616 
4617 
4618 /*
4619  * approximate-match multicast filtering for E1H per function in Tstorm
4620  */
4621 struct tstorm_eth_approximate_match_multicast_filtering {
4622 	u32 mcast_add_hash_bit_array[8];
4623 };
4624 
4625 
4626 /*
4627  * Common configuration parameters per function in Tstorm
4628  */
4629 struct tstorm_eth_function_common_config {
4630 	__le16 config_flags;
4631 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0)
4632 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0
4633 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1)
4634 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1
4635 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1<<2)
4636 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2
4637 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3)
4638 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3
4639 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE (0x7<<4)
4640 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT 4
4641 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE (0x1<<7)
4642 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE_SHIFT 7
4643 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0xFF<<8)
4644 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 8
4645 	u8 rss_result_mask;
4646 	u8 reserved1;
4647 	__le16 vlan_id[2];
4648 };
4649 
4650 
4651 /*
4652  * MAC filtering configuration parameters per port in Tstorm
4653  */
4654 struct tstorm_eth_mac_filter_config {
4655 	u32 ucast_drop_all;
4656 	u32 ucast_accept_all;
4657 	u32 mcast_drop_all;
4658 	u32 mcast_accept_all;
4659 	u32 bcast_accept_all;
4660 	u32 vlan_filter[2];
4661 	u32 unmatched_unicast;
4662 };
4663 
4664 
4665 /*
4666  * tx only queue init ramrod data
4667  */
4668 struct tx_queue_init_ramrod_data {
4669 	struct client_init_general_data general;
4670 	struct client_init_tx_data tx;
4671 };
4672 
4673 
4674 /*
4675  * Three RX producers for ETH
4676  */
4677 struct ustorm_eth_rx_producers {
4678 #if defined(__BIG_ENDIAN)
4679 	u16 bd_prod;
4680 	u16 cqe_prod;
4681 #elif defined(__LITTLE_ENDIAN)
4682 	u16 cqe_prod;
4683 	u16 bd_prod;
4684 #endif
4685 #if defined(__BIG_ENDIAN)
4686 	u16 reserved;
4687 	u16 sge_prod;
4688 #elif defined(__LITTLE_ENDIAN)
4689 	u16 sge_prod;
4690 	u16 reserved;
4691 #endif
4692 };
4693 
4694 
4695 /*
4696  * FCoE RX statistics parameters section#0
4697  */
4698 struct fcoe_rx_stat_params_section0 {
4699 	__le32 fcoe_rx_pkt_cnt;
4700 	__le32 fcoe_rx_byte_cnt;
4701 };
4702 
4703 
4704 /*
4705  * FCoE RX statistics parameters section#1
4706  */
4707 struct fcoe_rx_stat_params_section1 {
4708 	__le32 fcoe_ver_cnt;
4709 	__le32 fcoe_rx_drop_pkt_cnt;
4710 };
4711 
4712 
4713 /*
4714  * FCoE RX statistics parameters section#2
4715  */
4716 struct fcoe_rx_stat_params_section2 {
4717 	__le32 fc_crc_cnt;
4718 	__le32 eofa_del_cnt;
4719 	__le32 miss_frame_cnt;
4720 	__le32 seq_timeout_cnt;
4721 	__le32 drop_seq_cnt;
4722 	__le32 fcoe_rx_drop_pkt_cnt;
4723 	__le32 fcp_rx_pkt_cnt;
4724 	__le32 reserved0;
4725 };
4726 
4727 
4728 /*
4729  * FCoE TX statistics parameters
4730  */
4731 struct fcoe_tx_stat_params {
4732 	__le32 fcoe_tx_pkt_cnt;
4733 	__le32 fcoe_tx_byte_cnt;
4734 	__le32 fcp_tx_pkt_cnt;
4735 	__le32 reserved0;
4736 };
4737 
4738 /*
4739  * FCoE statistics parameters
4740  */
4741 struct fcoe_statistics_params {
4742 	struct fcoe_tx_stat_params tx_stat;
4743 	struct fcoe_rx_stat_params_section0 rx_stat0;
4744 	struct fcoe_rx_stat_params_section1 rx_stat1;
4745 	struct fcoe_rx_stat_params_section2 rx_stat2;
4746 };
4747 
4748 
4749 /*
4750  * The data afex vif list ramrod need
4751  */
4752 struct afex_vif_list_ramrod_data {
4753 	u8 afex_vif_list_command;
4754 	u8 func_bit_map;
4755 	__le16 vif_list_index;
4756 	u8 func_to_clear;
4757 	u8 echo;
4758 	__le16 reserved1;
4759 };
4760 
4761 
4762 /*
4763  * cfc delete event data
4764  */
4765 struct cfc_del_event_data {
4766 	u32 cid;
4767 	u32 reserved0;
4768 	u32 reserved1;
4769 };
4770 
4771 
4772 /*
4773  * per-port SAFC demo variables
4774  */
4775 struct cmng_flags_per_port {
4776 	u32 cmng_enables;
4777 #define CMNG_FLAGS_PER_PORT_FAIRNESS_VN (0x1<<0)
4778 #define CMNG_FLAGS_PER_PORT_FAIRNESS_VN_SHIFT 0
4779 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN (0x1<<1)
4780 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN_SHIFT 1
4781 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS (0x1<<2)
4782 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_SHIFT 2
4783 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE (0x1<<3)
4784 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE_SHIFT 3
4785 #define __CMNG_FLAGS_PER_PORT_RESERVED0 (0xFFFFFFF<<4)
4786 #define __CMNG_FLAGS_PER_PORT_RESERVED0_SHIFT 4
4787 	u32 __reserved1;
4788 };
4789 
4790 
4791 /*
4792  * per-port rate shaping variables
4793  */
4794 struct rate_shaping_vars_per_port {
4795 	u32 rs_periodic_timeout;
4796 	u32 rs_threshold;
4797 };
4798 
4799 /*
4800  * per-port fairness variables
4801  */
4802 struct fairness_vars_per_port {
4803 	u32 upper_bound;
4804 	u32 fair_threshold;
4805 	u32 fairness_timeout;
4806 	u32 reserved0;
4807 };
4808 
4809 /*
4810  * per-port SAFC variables
4811  */
4812 struct safc_struct_per_port {
4813 #if defined(__BIG_ENDIAN)
4814 	u16 __reserved1;
4815 	u8 __reserved0;
4816 	u8 safc_timeout_usec;
4817 #elif defined(__LITTLE_ENDIAN)
4818 	u8 safc_timeout_usec;
4819 	u8 __reserved0;
4820 	u16 __reserved1;
4821 #endif
4822 	u8 cos_to_traffic_types[MAX_COS_NUMBER];
4823 	u16 cos_to_pause_mask[NUM_OF_SAFC_BITS];
4824 };
4825 
4826 /*
4827  * Per-port congestion management variables
4828  */
4829 struct cmng_struct_per_port {
4830 	struct rate_shaping_vars_per_port rs_vars;
4831 	struct fairness_vars_per_port fair_vars;
4832 	struct safc_struct_per_port safc_vars;
4833 	struct cmng_flags_per_port flags;
4834 };
4835 
4836 /*
4837  * a single rate shaping counter. can be used as protocol or vnic counter
4838  */
4839 struct rate_shaping_counter {
4840 	u32 quota;
4841 #if defined(__BIG_ENDIAN)
4842 	u16 __reserved0;
4843 	u16 rate;
4844 #elif defined(__LITTLE_ENDIAN)
4845 	u16 rate;
4846 	u16 __reserved0;
4847 #endif
4848 };
4849 
4850 /*
4851  * per-vnic rate shaping variables
4852  */
4853 struct rate_shaping_vars_per_vn {
4854 	struct rate_shaping_counter vn_counter;
4855 };
4856 
4857 /*
4858  * per-vnic fairness variables
4859  */
4860 struct fairness_vars_per_vn {
4861 	u32 cos_credit_delta[MAX_COS_NUMBER];
4862 	u32 vn_credit_delta;
4863 	u32 __reserved0;
4864 };
4865 
4866 /*
4867  * cmng port init state
4868  */
4869 struct cmng_vnic {
4870 	struct rate_shaping_vars_per_vn vnic_max_rate[4];
4871 	struct fairness_vars_per_vn vnic_min_rate[4];
4872 };
4873 
4874 /*
4875  * cmng port init state
4876  */
4877 struct cmng_init {
4878 	struct cmng_struct_per_port port;
4879 	struct cmng_vnic vnic;
4880 };
4881 
4882 
4883 /*
4884  * driver parameters for congestion management init, all rates are in Mbps
4885  */
4886 struct cmng_init_input {
4887 	u32 port_rate;
4888 	u16 vnic_min_rate[4];
4889 	u16 vnic_max_rate[4];
4890 	u16 cos_min_rate[MAX_COS_NUMBER];
4891 	u16 cos_to_pause_mask[MAX_COS_NUMBER];
4892 	struct cmng_flags_per_port flags;
4893 };
4894 
4895 
4896 /*
4897  * Protocol-common command ID for slow path elements
4898  */
4899 enum common_spqe_cmd_id {
4900 	RAMROD_CMD_ID_COMMON_UNUSED,
4901 	RAMROD_CMD_ID_COMMON_FUNCTION_START,
4902 	RAMROD_CMD_ID_COMMON_FUNCTION_STOP,
4903 	RAMROD_CMD_ID_COMMON_FUNCTION_UPDATE,
4904 	RAMROD_CMD_ID_COMMON_CFC_DEL,
4905 	RAMROD_CMD_ID_COMMON_CFC_DEL_WB,
4906 	RAMROD_CMD_ID_COMMON_STAT_QUERY,
4907 	RAMROD_CMD_ID_COMMON_STOP_TRAFFIC,
4908 	RAMROD_CMD_ID_COMMON_START_TRAFFIC,
4909 	RAMROD_CMD_ID_COMMON_AFEX_VIF_LISTS,
4910 	RAMROD_CMD_ID_COMMON_SET_TIMESYNC,
4911 	MAX_COMMON_SPQE_CMD_ID
4912 };
4913 
4914 /*
4915  * Per-protocol connection types
4916  */
4917 enum connection_type {
4918 	ETH_CONNECTION_TYPE,
4919 	TOE_CONNECTION_TYPE,
4920 	RDMA_CONNECTION_TYPE,
4921 	ISCSI_CONNECTION_TYPE,
4922 	FCOE_CONNECTION_TYPE,
4923 	RESERVED_CONNECTION_TYPE_0,
4924 	RESERVED_CONNECTION_TYPE_1,
4925 	RESERVED_CONNECTION_TYPE_2,
4926 	NONE_CONNECTION_TYPE,
4927 	MAX_CONNECTION_TYPE
4928 };
4929 
4930 
4931 /*
4932  * Cos modes
4933  */
4934 enum cos_mode {
4935 	OVERRIDE_COS,
4936 	STATIC_COS,
4937 	FW_WRR,
4938 	MAX_COS_MODE
4939 };
4940 
4941 
4942 /*
4943  * Dynamic HC counters set by the driver
4944  */
4945 struct hc_dynamic_drv_counter {
4946 	u32 val[HC_SB_MAX_DYNAMIC_INDICES];
4947 };
4948 
4949 /*
4950  * zone A per-queue data
4951  */
4952 struct cstorm_queue_zone_data {
4953 	struct hc_dynamic_drv_counter hc_dyn_drv_cnt;
4954 	struct regpair reserved[2];
4955 };
4956 
4957 
4958 /*
4959  * Vf-PF channel data in cstorm ram (non-triggered zone)
4960  */
4961 struct vf_pf_channel_zone_data {
4962 	u32 msg_addr_lo;
4963 	u32 msg_addr_hi;
4964 };
4965 
4966 /*
4967  * zone for VF non-triggered data
4968  */
4969 struct non_trigger_vf_zone {
4970 	struct vf_pf_channel_zone_data vf_pf_channel;
4971 };
4972 
4973 /*
4974  * Vf-PF channel trigger zone in cstorm ram
4975  */
4976 struct vf_pf_channel_zone_trigger {
4977 	u8 addr_valid;
4978 };
4979 
4980 /*
4981  * zone that triggers the in-bound interrupt
4982  */
4983 struct trigger_vf_zone {
4984 #if defined(__BIG_ENDIAN)
4985 	u16 reserved1;
4986 	u8 reserved0;
4987 	struct vf_pf_channel_zone_trigger vf_pf_channel;
4988 #elif defined(__LITTLE_ENDIAN)
4989 	struct vf_pf_channel_zone_trigger vf_pf_channel;
4990 	u8 reserved0;
4991 	u16 reserved1;
4992 #endif
4993 	u32 reserved2;
4994 };
4995 
4996 /*
4997  * zone B per-VF data
4998  */
4999 struct cstorm_vf_zone_data {
5000 	struct non_trigger_vf_zone non_trigger;
5001 	struct trigger_vf_zone trigger;
5002 };
5003 
5004 
5005 /*
5006  * Dynamic host coalescing init parameters, per state machine
5007  */
5008 struct dynamic_hc_sm_config {
5009 	u32 threshold[3];
5010 	u8 shift_per_protocol[HC_SB_MAX_DYNAMIC_INDICES];
5011 	u8 hc_timeout0[HC_SB_MAX_DYNAMIC_INDICES];
5012 	u8 hc_timeout1[HC_SB_MAX_DYNAMIC_INDICES];
5013 	u8 hc_timeout2[HC_SB_MAX_DYNAMIC_INDICES];
5014 	u8 hc_timeout3[HC_SB_MAX_DYNAMIC_INDICES];
5015 };
5016 
5017 /*
5018  * Dynamic host coalescing init parameters
5019  */
5020 struct dynamic_hc_config {
5021 	struct dynamic_hc_sm_config sm_config[HC_SB_MAX_SM];
5022 };
5023 
5024 
5025 struct e2_integ_data {
5026 #if defined(__BIG_ENDIAN)
5027 	u8 flags;
5028 #define E2_INTEG_DATA_TESTING_EN (0x1<<0)
5029 #define E2_INTEG_DATA_TESTING_EN_SHIFT 0
5030 #define E2_INTEG_DATA_LB_TX (0x1<<1)
5031 #define E2_INTEG_DATA_LB_TX_SHIFT 1
5032 #define E2_INTEG_DATA_COS_TX (0x1<<2)
5033 #define E2_INTEG_DATA_COS_TX_SHIFT 2
5034 #define E2_INTEG_DATA_OPPORTUNISTICQM (0x1<<3)
5035 #define E2_INTEG_DATA_OPPORTUNISTICQM_SHIFT 3
5036 #define E2_INTEG_DATA_DPMTESTRELEASEDQ (0x1<<4)
5037 #define E2_INTEG_DATA_DPMTESTRELEASEDQ_SHIFT 4
5038 #define E2_INTEG_DATA_RESERVED (0x7<<5)
5039 #define E2_INTEG_DATA_RESERVED_SHIFT 5
5040 	u8 cos;
5041 	u8 voq;
5042 	u8 pbf_queue;
5043 #elif defined(__LITTLE_ENDIAN)
5044 	u8 pbf_queue;
5045 	u8 voq;
5046 	u8 cos;
5047 	u8 flags;
5048 #define E2_INTEG_DATA_TESTING_EN (0x1<<0)
5049 #define E2_INTEG_DATA_TESTING_EN_SHIFT 0
5050 #define E2_INTEG_DATA_LB_TX (0x1<<1)
5051 #define E2_INTEG_DATA_LB_TX_SHIFT 1
5052 #define E2_INTEG_DATA_COS_TX (0x1<<2)
5053 #define E2_INTEG_DATA_COS_TX_SHIFT 2
5054 #define E2_INTEG_DATA_OPPORTUNISTICQM (0x1<<3)
5055 #define E2_INTEG_DATA_OPPORTUNISTICQM_SHIFT 3
5056 #define E2_INTEG_DATA_DPMTESTRELEASEDQ (0x1<<4)
5057 #define E2_INTEG_DATA_DPMTESTRELEASEDQ_SHIFT 4
5058 #define E2_INTEG_DATA_RESERVED (0x7<<5)
5059 #define E2_INTEG_DATA_RESERVED_SHIFT 5
5060 #endif
5061 #if defined(__BIG_ENDIAN)
5062 	u16 reserved3;
5063 	u8 reserved2;
5064 	u8 ramEn;
5065 #elif defined(__LITTLE_ENDIAN)
5066 	u8 ramEn;
5067 	u8 reserved2;
5068 	u16 reserved3;
5069 #endif
5070 };
5071 
5072 
5073 /*
5074  * set mac event data
5075  */
5076 struct eth_event_data {
5077 	u32 echo;
5078 	u32 reserved0;
5079 	u32 reserved1;
5080 };
5081 
5082 
5083 /*
5084  * pf-vf event data
5085  */
5086 struct vf_pf_event_data {
5087 	u8 vf_id;
5088 	u8 reserved0;
5089 	u16 reserved1;
5090 	u32 msg_addr_lo;
5091 	u32 msg_addr_hi;
5092 };
5093 
5094 /*
5095  * VF FLR event data
5096  */
5097 struct vf_flr_event_data {
5098 	u8 vf_id;
5099 	u8 reserved0;
5100 	u16 reserved1;
5101 	u32 reserved2;
5102 	u32 reserved3;
5103 };
5104 
5105 /*
5106  * malicious VF event data
5107  */
5108 struct malicious_vf_event_data {
5109 	u8 vf_id;
5110 	u8 err_id;
5111 	u16 reserved1;
5112 	u32 reserved2;
5113 	u32 reserved3;
5114 };
5115 
5116 /*
5117  * vif list event data
5118  */
5119 struct vif_list_event_data {
5120 	u8 func_bit_map;
5121 	u8 echo;
5122 	__le16 reserved0;
5123 	__le32 reserved1;
5124 	__le32 reserved2;
5125 };
5126 
5127 /* function update event data */
5128 struct function_update_event_data {
5129 	u8 echo;
5130 	u8 reserved;
5131 	__le16 reserved0;
5132 	__le32 reserved1;
5133 	__le32 reserved2;
5134 };
5135 
5136 
5137 /* union for all event ring message types */
5138 union event_data {
5139 	struct vf_pf_event_data vf_pf_event;
5140 	struct eth_event_data eth_event;
5141 	struct cfc_del_event_data cfc_del_event;
5142 	struct vf_flr_event_data vf_flr_event;
5143 	struct malicious_vf_event_data malicious_vf_event;
5144 	struct vif_list_event_data vif_list_event;
5145 	struct function_update_event_data function_update_event;
5146 };
5147 
5148 
5149 /*
5150  * per PF event ring data
5151  */
5152 struct event_ring_data {
5153 	struct regpair_native base_addr;
5154 #if defined(__BIG_ENDIAN)
5155 	u8 index_id;
5156 	u8 sb_id;
5157 	u16 producer;
5158 #elif defined(__LITTLE_ENDIAN)
5159 	u16 producer;
5160 	u8 sb_id;
5161 	u8 index_id;
5162 #endif
5163 	u32 reserved0;
5164 };
5165 
5166 
5167 /*
5168  * event ring message element (each element is 128 bits)
5169  */
5170 struct event_ring_msg {
5171 	u8 opcode;
5172 	u8 error;
5173 	u16 reserved1;
5174 	union event_data data;
5175 };
5176 
5177 /*
5178  * event ring next page element (128 bits)
5179  */
5180 struct event_ring_next {
5181 	struct regpair addr;
5182 	u32 reserved[2];
5183 };
5184 
5185 /*
5186  * union for event ring element types (each element is 128 bits)
5187  */
5188 union event_ring_elem {
5189 	struct event_ring_msg message;
5190 	struct event_ring_next next_page;
5191 };
5192 
5193 
5194 /*
5195  * Common event ring opcodes
5196  */
5197 enum event_ring_opcode {
5198 	EVENT_RING_OPCODE_VF_PF_CHANNEL,
5199 	EVENT_RING_OPCODE_FUNCTION_START,
5200 	EVENT_RING_OPCODE_FUNCTION_STOP,
5201 	EVENT_RING_OPCODE_CFC_DEL,
5202 	EVENT_RING_OPCODE_CFC_DEL_WB,
5203 	EVENT_RING_OPCODE_STAT_QUERY,
5204 	EVENT_RING_OPCODE_STOP_TRAFFIC,
5205 	EVENT_RING_OPCODE_START_TRAFFIC,
5206 	EVENT_RING_OPCODE_VF_FLR,
5207 	EVENT_RING_OPCODE_MALICIOUS_VF,
5208 	EVENT_RING_OPCODE_FORWARD_SETUP,
5209 	EVENT_RING_OPCODE_RSS_UPDATE_RULES,
5210 	EVENT_RING_OPCODE_FUNCTION_UPDATE,
5211 	EVENT_RING_OPCODE_AFEX_VIF_LISTS,
5212 	EVENT_RING_OPCODE_SET_MAC,
5213 	EVENT_RING_OPCODE_CLASSIFICATION_RULES,
5214 	EVENT_RING_OPCODE_FILTERS_RULES,
5215 	EVENT_RING_OPCODE_MULTICAST_RULES,
5216 	EVENT_RING_OPCODE_SET_TIMESYNC,
5217 	MAX_EVENT_RING_OPCODE
5218 };
5219 
5220 /*
5221  * Modes for fairness algorithm
5222  */
5223 enum fairness_mode {
5224 	FAIRNESS_COS_WRR_MODE,
5225 	FAIRNESS_COS_ETS_MODE,
5226 	MAX_FAIRNESS_MODE
5227 };
5228 
5229 
5230 /*
5231  * Priority and cos
5232  */
5233 struct priority_cos {
5234 	u8 priority;
5235 	u8 cos;
5236 	__le16 reserved1;
5237 };
5238 
5239 /*
5240  * The data for flow control configuration
5241  */
5242 struct flow_control_configuration {
5243 	struct priority_cos traffic_type_to_priority_cos[MAX_TRAFFIC_TYPES];
5244 	u8 dcb_enabled;
5245 	u8 dcb_version;
5246 	u8 dont_add_pri_0_en;
5247 	u8 reserved1;
5248 	__le32 reserved2;
5249 };
5250 
5251 
5252 /*
5253  *
5254  */
5255 struct function_start_data {
5256 	u8 function_mode;
5257 	u8 allow_npar_tx_switching;
5258 	__le16 sd_vlan_tag;
5259 	__le16 vif_id;
5260 	u8 path_id;
5261 	u8 network_cos_mode;
5262 	u8 dmae_cmd_id;
5263 	u8 tunnel_mode;
5264 	u8 gre_tunnel_type;
5265 	u8 tunn_clss_en;
5266 	u8 inner_gre_rss_en;
5267 	u8 sd_accept_mf_clss_fail;
5268 	__le16 vxlan_dst_port;
5269 	__le16 sd_accept_mf_clss_fail_ethtype;
5270 	__le16 sd_vlan_eth_type;
5271 	u8 sd_vlan_force_pri_flg;
5272 	u8 sd_vlan_force_pri_val;
5273 	u8 sd_accept_mf_clss_fail_match_ethtype;
5274 	u8 no_added_tags;
5275 };
5276 
5277 struct function_update_data {
5278 	u8 vif_id_change_flg;
5279 	u8 afex_default_vlan_change_flg;
5280 	u8 allowed_priorities_change_flg;
5281 	u8 network_cos_mode_change_flg;
5282 	__le16 vif_id;
5283 	__le16 afex_default_vlan;
5284 	u8 allowed_priorities;
5285 	u8 network_cos_mode;
5286 	u8 lb_mode_en_change_flg;
5287 	u8 lb_mode_en;
5288 	u8 tx_switch_suspend_change_flg;
5289 	u8 tx_switch_suspend;
5290 	u8 echo;
5291 	u8 update_tunn_cfg_flg;
5292 	u8 tunnel_mode;
5293 	u8 gre_tunnel_type;
5294 	u8 tunn_clss_en;
5295 	u8 inner_gre_rss_en;
5296 	__le16 vxlan_dst_port;
5297 	u8 sd_vlan_force_pri_change_flg;
5298 	u8 sd_vlan_force_pri_flg;
5299 	u8 sd_vlan_force_pri_val;
5300 	u8 sd_vlan_tag_change_flg;
5301 	u8 sd_vlan_eth_type_change_flg;
5302 	u8 reserved1;
5303 	__le16 sd_vlan_tag;
5304 	__le16 sd_vlan_eth_type;
5305 };
5306 
5307 /*
5308  * FW version stored in the Xstorm RAM
5309  */
5310 struct fw_version {
5311 #if defined(__BIG_ENDIAN)
5312 	u8 engineering;
5313 	u8 revision;
5314 	u8 minor;
5315 	u8 major;
5316 #elif defined(__LITTLE_ENDIAN)
5317 	u8 major;
5318 	u8 minor;
5319 	u8 revision;
5320 	u8 engineering;
5321 #endif
5322 	u32 flags;
5323 #define FW_VERSION_OPTIMIZED (0x1<<0)
5324 #define FW_VERSION_OPTIMIZED_SHIFT 0
5325 #define FW_VERSION_BIG_ENDIEN (0x1<<1)
5326 #define FW_VERSION_BIG_ENDIEN_SHIFT 1
5327 #define FW_VERSION_CHIP_VERSION (0x3<<2)
5328 #define FW_VERSION_CHIP_VERSION_SHIFT 2
5329 #define __FW_VERSION_RESERVED (0xFFFFFFF<<4)
5330 #define __FW_VERSION_RESERVED_SHIFT 4
5331 };
5332 
5333 
5334 /* GRE Tunnel Mode */
5335 enum gre_tunnel_type {
5336 	NVGRE_TUNNEL,
5337 	L2GRE_TUNNEL,
5338 	IPGRE_TUNNEL,
5339 	MAX_GRE_TUNNEL_TYPE
5340 };
5341 
5342 /*
5343  * Dynamic Host-Coalescing - Driver(host) counters
5344  */
5345 struct hc_dynamic_sb_drv_counters {
5346 	u32 dynamic_hc_drv_counter[HC_SB_MAX_DYNAMIC_INDICES];
5347 };
5348 
5349 
5350 /*
5351  * 2 bytes. configuration/state parameters for a single protocol index
5352  */
5353 struct hc_index_data {
5354 #if defined(__BIG_ENDIAN)
5355 	u8 flags;
5356 #define HC_INDEX_DATA_SM_ID (0x1<<0)
5357 #define HC_INDEX_DATA_SM_ID_SHIFT 0
5358 #define HC_INDEX_DATA_HC_ENABLED (0x1<<1)
5359 #define HC_INDEX_DATA_HC_ENABLED_SHIFT 1
5360 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2)
5361 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2
5362 #define HC_INDEX_DATA_RESERVE (0x1F<<3)
5363 #define HC_INDEX_DATA_RESERVE_SHIFT 3
5364 	u8 timeout;
5365 #elif defined(__LITTLE_ENDIAN)
5366 	u8 timeout;
5367 	u8 flags;
5368 #define HC_INDEX_DATA_SM_ID (0x1<<0)
5369 #define HC_INDEX_DATA_SM_ID_SHIFT 0
5370 #define HC_INDEX_DATA_HC_ENABLED (0x1<<1)
5371 #define HC_INDEX_DATA_HC_ENABLED_SHIFT 1
5372 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2)
5373 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2
5374 #define HC_INDEX_DATA_RESERVE (0x1F<<3)
5375 #define HC_INDEX_DATA_RESERVE_SHIFT 3
5376 #endif
5377 };
5378 
5379 
5380 /*
5381  * HC state-machine
5382  */
5383 struct hc_status_block_sm {
5384 #if defined(__BIG_ENDIAN)
5385 	u8 igu_seg_id;
5386 	u8 igu_sb_id;
5387 	u8 timer_value;
5388 	u8 __flags;
5389 #elif defined(__LITTLE_ENDIAN)
5390 	u8 __flags;
5391 	u8 timer_value;
5392 	u8 igu_sb_id;
5393 	u8 igu_seg_id;
5394 #endif
5395 	u32 time_to_expire;
5396 };
5397 
5398 /*
5399  * hold PCI identification variables- used in various places in firmware
5400  */
5401 struct pci_entity {
5402 #if defined(__BIG_ENDIAN)
5403 	u8 vf_valid;
5404 	u8 vf_id;
5405 	u8 vnic_id;
5406 	u8 pf_id;
5407 #elif defined(__LITTLE_ENDIAN)
5408 	u8 pf_id;
5409 	u8 vnic_id;
5410 	u8 vf_id;
5411 	u8 vf_valid;
5412 #endif
5413 };
5414 
5415 /*
5416  * The fast-path status block meta-data, common to all chips
5417  */
5418 struct hc_sb_data {
5419 	struct regpair_native host_sb_addr;
5420 	struct hc_status_block_sm state_machine[HC_SB_MAX_SM];
5421 	struct pci_entity p_func;
5422 #if defined(__BIG_ENDIAN)
5423 	u8 rsrv0;
5424 	u8 state;
5425 	u8 dhc_qzone_id;
5426 	u8 same_igu_sb_1b;
5427 #elif defined(__LITTLE_ENDIAN)
5428 	u8 same_igu_sb_1b;
5429 	u8 dhc_qzone_id;
5430 	u8 state;
5431 	u8 rsrv0;
5432 #endif
5433 	struct regpair_native rsrv1[2];
5434 };
5435 
5436 
5437 /*
5438  * Segment types for host coaslescing
5439  */
5440 enum hc_segment {
5441 	HC_REGULAR_SEGMENT,
5442 	HC_DEFAULT_SEGMENT,
5443 	MAX_HC_SEGMENT
5444 };
5445 
5446 
5447 /*
5448  * The fast-path status block meta-data
5449  */
5450 struct hc_sp_status_block_data {
5451 	struct regpair_native host_sb_addr;
5452 #if defined(__BIG_ENDIAN)
5453 	u8 rsrv1;
5454 	u8 state;
5455 	u8 igu_seg_id;
5456 	u8 igu_sb_id;
5457 #elif defined(__LITTLE_ENDIAN)
5458 	u8 igu_sb_id;
5459 	u8 igu_seg_id;
5460 	u8 state;
5461 	u8 rsrv1;
5462 #endif
5463 	struct pci_entity p_func;
5464 };
5465 
5466 
5467 /*
5468  * The fast-path status block meta-data
5469  */
5470 struct hc_status_block_data_e1x {
5471 	struct hc_index_data index_data[HC_SB_MAX_INDICES_E1X];
5472 	struct hc_sb_data common;
5473 };
5474 
5475 
5476 /*
5477  * The fast-path status block meta-data
5478  */
5479 struct hc_status_block_data_e2 {
5480 	struct hc_index_data index_data[HC_SB_MAX_INDICES_E2];
5481 	struct hc_sb_data common;
5482 };
5483 
5484 
5485 /*
5486  * IGU block operartion modes (in Everest2)
5487  */
5488 enum igu_mode {
5489 	HC_IGU_BC_MODE,
5490 	HC_IGU_NBC_MODE,
5491 	MAX_IGU_MODE
5492 };
5493 
5494 
5495 /*
5496  * IP versions
5497  */
5498 enum ip_ver {
5499 	IP_V4,
5500 	IP_V6,
5501 	MAX_IP_VER
5502 };
5503 
5504 /*
5505  * Malicious VF error ID
5506  */
5507 enum malicious_vf_error_id {
5508 	MALICIOUS_VF_NO_ERROR,
5509 	VF_PF_CHANNEL_NOT_READY,
5510 	ETH_ILLEGAL_BD_LENGTHS,
5511 	ETH_PACKET_TOO_SHORT,
5512 	ETH_PAYLOAD_TOO_BIG,
5513 	ETH_ILLEGAL_ETH_TYPE,
5514 	ETH_ILLEGAL_LSO_HDR_LEN,
5515 	ETH_TOO_MANY_BDS,
5516 	ETH_ZERO_HDR_NBDS,
5517 	ETH_START_BD_NOT_SET,
5518 	ETH_ILLEGAL_PARSE_NBDS,
5519 	ETH_IPV6_AND_CHECKSUM,
5520 	ETH_VLAN_FLG_INCORRECT,
5521 	ETH_ILLEGAL_LSO_MSS,
5522 	ETH_TUNNEL_NOT_SUPPORTED,
5523 	MAX_MALICIOUS_VF_ERROR_ID
5524 };
5525 
5526 /*
5527  * Multi-function modes
5528  */
5529 enum mf_mode {
5530 	SINGLE_FUNCTION,
5531 	MULTI_FUNCTION_SD,
5532 	MULTI_FUNCTION_SI,
5533 	MULTI_FUNCTION_AFEX,
5534 	MAX_MF_MODE
5535 };
5536 
5537 /*
5538  * Protocol-common statistics collected by the Tstorm (per pf)
5539  */
5540 struct tstorm_per_pf_stats {
5541 	struct regpair rcv_error_bytes;
5542 };
5543 
5544 /*
5545  *
5546  */
5547 struct per_pf_stats {
5548 	struct tstorm_per_pf_stats tstorm_pf_statistics;
5549 };
5550 
5551 
5552 /*
5553  * Protocol-common statistics collected by the Tstorm (per port)
5554  */
5555 struct tstorm_per_port_stats {
5556 	__le32 mac_discard;
5557 	__le32 mac_filter_discard;
5558 	__le32 brb_truncate_discard;
5559 	__le32 mf_tag_discard;
5560 	__le32 packet_drop;
5561 	__le32 reserved;
5562 };
5563 
5564 /*
5565  *
5566  */
5567 struct per_port_stats {
5568 	struct tstorm_per_port_stats tstorm_port_statistics;
5569 };
5570 
5571 
5572 /*
5573  * Protocol-common statistics collected by the Tstorm (per client)
5574  */
5575 struct tstorm_per_queue_stats {
5576 	struct regpair rcv_ucast_bytes;
5577 	__le32 rcv_ucast_pkts;
5578 	__le32 checksum_discard;
5579 	struct regpair rcv_bcast_bytes;
5580 	__le32 rcv_bcast_pkts;
5581 	__le32 pkts_too_big_discard;
5582 	struct regpair rcv_mcast_bytes;
5583 	__le32 rcv_mcast_pkts;
5584 	__le32 ttl0_discard;
5585 	__le16 no_buff_discard;
5586 	__le16 reserved0;
5587 	__le32 reserved1;
5588 };
5589 
5590 /*
5591  * Protocol-common statistics collected by the Ustorm (per client)
5592  */
5593 struct ustorm_per_queue_stats {
5594 	struct regpair ucast_no_buff_bytes;
5595 	struct regpair mcast_no_buff_bytes;
5596 	struct regpair bcast_no_buff_bytes;
5597 	__le32 ucast_no_buff_pkts;
5598 	__le32 mcast_no_buff_pkts;
5599 	__le32 bcast_no_buff_pkts;
5600 	__le32 coalesced_pkts;
5601 	struct regpair coalesced_bytes;
5602 	__le32 coalesced_events;
5603 	__le32 coalesced_aborts;
5604 };
5605 
5606 /*
5607  * Protocol-common statistics collected by the Xstorm (per client)
5608  */
5609 struct xstorm_per_queue_stats {
5610 	struct regpair ucast_bytes_sent;
5611 	struct regpair mcast_bytes_sent;
5612 	struct regpair bcast_bytes_sent;
5613 	__le32 ucast_pkts_sent;
5614 	__le32 mcast_pkts_sent;
5615 	__le32 bcast_pkts_sent;
5616 	__le32 error_drop_pkts;
5617 };
5618 
5619 /*
5620  *
5621  */
5622 struct per_queue_stats {
5623 	struct tstorm_per_queue_stats tstorm_queue_statistics;
5624 	struct ustorm_per_queue_stats ustorm_queue_statistics;
5625 	struct xstorm_per_queue_stats xstorm_queue_statistics;
5626 };
5627 
5628 
5629 /*
5630  * FW version stored in first line of pram
5631  */
5632 struct pram_fw_version {
5633 	u8 major;
5634 	u8 minor;
5635 	u8 revision;
5636 	u8 engineering;
5637 	u8 flags;
5638 #define PRAM_FW_VERSION_OPTIMIZED (0x1<<0)
5639 #define PRAM_FW_VERSION_OPTIMIZED_SHIFT 0
5640 #define PRAM_FW_VERSION_STORM_ID (0x3<<1)
5641 #define PRAM_FW_VERSION_STORM_ID_SHIFT 1
5642 #define PRAM_FW_VERSION_BIG_ENDIEN (0x1<<3)
5643 #define PRAM_FW_VERSION_BIG_ENDIEN_SHIFT 3
5644 #define PRAM_FW_VERSION_CHIP_VERSION (0x3<<4)
5645 #define PRAM_FW_VERSION_CHIP_VERSION_SHIFT 4
5646 #define __PRAM_FW_VERSION_RESERVED0 (0x3<<6)
5647 #define __PRAM_FW_VERSION_RESERVED0_SHIFT 6
5648 };
5649 
5650 
5651 /*
5652  * Ethernet slow path element
5653  */
5654 union protocol_common_specific_data {
5655 	u8 protocol_data[8];
5656 	struct regpair phy_address;
5657 	struct regpair mac_config_addr;
5658 	struct afex_vif_list_ramrod_data afex_vif_list_data;
5659 };
5660 
5661 /*
5662  * The send queue element
5663  */
5664 struct protocol_common_spe {
5665 	struct spe_hdr hdr;
5666 	union protocol_common_specific_data data;
5667 };
5668 
5669 /* The data for the Set Timesync Ramrod */
5670 struct set_timesync_ramrod_data {
5671 	u8 drift_adjust_cmd;
5672 	u8 offset_cmd;
5673 	u8 add_sub_drift_adjust_value;
5674 	u8 drift_adjust_value;
5675 	u32 drift_adjust_period;
5676 	struct regpair offset_delta;
5677 };
5678 
5679 /*
5680  * The send queue element
5681  */
5682 struct slow_path_element {
5683 	struct spe_hdr hdr;
5684 	struct regpair protocol_data;
5685 };
5686 
5687 
5688 /*
5689  * Protocol-common statistics counter
5690  */
5691 struct stats_counter {
5692 	__le16 xstats_counter;
5693 	__le16 reserved0;
5694 	__le32 reserved1;
5695 	__le16 tstats_counter;
5696 	__le16 reserved2;
5697 	__le32 reserved3;
5698 	__le16 ustats_counter;
5699 	__le16 reserved4;
5700 	__le32 reserved5;
5701 	__le16 cstats_counter;
5702 	__le16 reserved6;
5703 	__le32 reserved7;
5704 };
5705 
5706 
5707 /*
5708  *
5709  */
5710 struct stats_query_entry {
5711 	u8 kind;
5712 	u8 index;
5713 	__le16 funcID;
5714 	__le32 reserved;
5715 	struct regpair address;
5716 };
5717 
5718 /*
5719  * statistic command
5720  */
5721 struct stats_query_cmd_group {
5722 	struct stats_query_entry query[STATS_QUERY_CMD_COUNT];
5723 };
5724 
5725 
5726 /*
5727  * statistic command header
5728  */
5729 struct stats_query_header {
5730 	u8 cmd_num;
5731 	u8 reserved0;
5732 	__le16 drv_stats_counter;
5733 	__le32 reserved1;
5734 	struct regpair stats_counters_addrs;
5735 };
5736 
5737 
5738 /*
5739  * Types of statistcis query entry
5740  */
5741 enum stats_query_type {
5742 	STATS_TYPE_QUEUE,
5743 	STATS_TYPE_PORT,
5744 	STATS_TYPE_PF,
5745 	STATS_TYPE_TOE,
5746 	STATS_TYPE_FCOE,
5747 	MAX_STATS_QUERY_TYPE
5748 };
5749 
5750 
5751 /*
5752  * Indicate of the function status block state
5753  */
5754 enum status_block_state {
5755 	SB_DISABLED,
5756 	SB_ENABLED,
5757 	SB_CLEANED,
5758 	MAX_STATUS_BLOCK_STATE
5759 };
5760 
5761 
5762 /*
5763  * Storm IDs (including attentions for IGU related enums)
5764  */
5765 enum storm_id {
5766 	USTORM_ID,
5767 	CSTORM_ID,
5768 	XSTORM_ID,
5769 	TSTORM_ID,
5770 	ATTENTION_ID,
5771 	MAX_STORM_ID
5772 };
5773 
5774 
5775 /*
5776  * Taffic types used in ETS and flow control algorithms
5777  */
5778 enum traffic_type {
5779 	LLFC_TRAFFIC_TYPE_NW,
5780 	LLFC_TRAFFIC_TYPE_FCOE,
5781 	LLFC_TRAFFIC_TYPE_ISCSI,
5782 	MAX_TRAFFIC_TYPE
5783 };
5784 
5785 
5786 /*
5787  * zone A per-queue data
5788  */
5789 struct tstorm_queue_zone_data {
5790 	struct regpair reserved[4];
5791 };
5792 
5793 
5794 /*
5795  * zone B per-VF data
5796  */
5797 struct tstorm_vf_zone_data {
5798 	struct regpair reserved;
5799 };
5800 
5801 /* Add or Subtract Value for Set Timesync Ramrod */
5802 enum ts_add_sub_value {
5803 	TS_SUB_VALUE,
5804 	TS_ADD_VALUE,
5805 	MAX_TS_ADD_SUB_VALUE
5806 };
5807 
5808 /* Drift-Adjust Commands for Set Timesync Ramrod */
5809 enum ts_drift_adjust_cmd {
5810 	TS_DRIFT_ADJUST_KEEP,
5811 	TS_DRIFT_ADJUST_SET,
5812 	TS_DRIFT_ADJUST_RESET,
5813 	MAX_TS_DRIFT_ADJUST_CMD
5814 };
5815 
5816 /* Offset Commands for Set Timesync Ramrod */
5817 enum ts_offset_cmd {
5818 	TS_OFFSET_KEEP,
5819 	TS_OFFSET_INC,
5820 	TS_OFFSET_DEC,
5821 	MAX_TS_OFFSET_CMD
5822 };
5823 
5824 /* Tunnel Mode */
5825 enum tunnel_mode {
5826 	TUNN_MODE_NONE,
5827 	TUNN_MODE_VXLAN,
5828 	TUNN_MODE_GRE,
5829 	MAX_TUNNEL_MODE
5830 };
5831 
5832  /* zone A per-queue data */
5833 struct ustorm_queue_zone_data {
5834 	struct ustorm_eth_rx_producers eth_rx_producers;
5835 	struct regpair reserved[3];
5836 };
5837 
5838 
5839 /*
5840  * zone B per-VF data
5841  */
5842 struct ustorm_vf_zone_data {
5843 	struct regpair reserved;
5844 };
5845 
5846 
5847 /*
5848  * data per VF-PF channel
5849  */
5850 struct vf_pf_channel_data {
5851 #if defined(__BIG_ENDIAN)
5852 	u16 reserved0;
5853 	u8 valid;
5854 	u8 state;
5855 #elif defined(__LITTLE_ENDIAN)
5856 	u8 state;
5857 	u8 valid;
5858 	u16 reserved0;
5859 #endif
5860 	u32 reserved1;
5861 };
5862 
5863 
5864 /*
5865  * State of VF-PF channel
5866  */
5867 enum vf_pf_channel_state {
5868 	VF_PF_CHANNEL_STATE_READY,
5869 	VF_PF_CHANNEL_STATE_WAITING_FOR_ACK,
5870 	MAX_VF_PF_CHANNEL_STATE
5871 };
5872 
5873 
5874 /*
5875  * vif_list_rule_kind
5876  */
5877 enum vif_list_rule_kind {
5878 	VIF_LIST_RULE_SET,
5879 	VIF_LIST_RULE_GET,
5880 	VIF_LIST_RULE_CLEAR_ALL,
5881 	VIF_LIST_RULE_CLEAR_FUNC,
5882 	MAX_VIF_LIST_RULE_KIND
5883 };
5884 
5885 
5886 /*
5887  * zone A per-queue data
5888  */
5889 struct xstorm_queue_zone_data {
5890 	struct regpair reserved[4];
5891 };
5892 
5893 
5894 /*
5895  * zone B per-VF data
5896  */
5897 struct xstorm_vf_zone_data {
5898 	struct regpair reserved;
5899 };
5900 
5901 #endif /* BNX2X_HSI_H */
5902