1 /* bnx2x_hsi.h: Broadcom Everest network driver. 2 * 3 * Copyright (c) 2007-2013 Broadcom Corporation 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation. 8 */ 9 #ifndef BNX2X_HSI_H 10 #define BNX2X_HSI_H 11 12 #include "bnx2x_fw_defs.h" 13 #include "bnx2x_mfw_req.h" 14 15 #define FW_ENCODE_32BIT_PATTERN 0x1e1e1e1e 16 17 struct license_key { 18 u32 reserved[6]; 19 20 u32 max_iscsi_conn; 21 #define BNX2X_MAX_ISCSI_TRGT_CONN_MASK 0xFFFF 22 #define BNX2X_MAX_ISCSI_TRGT_CONN_SHIFT 0 23 #define BNX2X_MAX_ISCSI_INIT_CONN_MASK 0xFFFF0000 24 #define BNX2X_MAX_ISCSI_INIT_CONN_SHIFT 16 25 26 u32 reserved_a; 27 28 u32 max_fcoe_conn; 29 #define BNX2X_MAX_FCOE_TRGT_CONN_MASK 0xFFFF 30 #define BNX2X_MAX_FCOE_TRGT_CONN_SHIFT 0 31 #define BNX2X_MAX_FCOE_INIT_CONN_MASK 0xFFFF0000 32 #define BNX2X_MAX_FCOE_INIT_CONN_SHIFT 16 33 34 u32 reserved_b[4]; 35 }; 36 37 /**************************************************************************** 38 * Shared HW configuration * 39 ****************************************************************************/ 40 #define PIN_CFG_NA 0x00000000 41 #define PIN_CFG_GPIO0_P0 0x00000001 42 #define PIN_CFG_GPIO1_P0 0x00000002 43 #define PIN_CFG_GPIO2_P0 0x00000003 44 #define PIN_CFG_GPIO3_P0 0x00000004 45 #define PIN_CFG_GPIO0_P1 0x00000005 46 #define PIN_CFG_GPIO1_P1 0x00000006 47 #define PIN_CFG_GPIO2_P1 0x00000007 48 #define PIN_CFG_GPIO3_P1 0x00000008 49 #define PIN_CFG_EPIO0 0x00000009 50 #define PIN_CFG_EPIO1 0x0000000a 51 #define PIN_CFG_EPIO2 0x0000000b 52 #define PIN_CFG_EPIO3 0x0000000c 53 #define PIN_CFG_EPIO4 0x0000000d 54 #define PIN_CFG_EPIO5 0x0000000e 55 #define PIN_CFG_EPIO6 0x0000000f 56 #define PIN_CFG_EPIO7 0x00000010 57 #define PIN_CFG_EPIO8 0x00000011 58 #define PIN_CFG_EPIO9 0x00000012 59 #define PIN_CFG_EPIO10 0x00000013 60 #define PIN_CFG_EPIO11 0x00000014 61 #define PIN_CFG_EPIO12 0x00000015 62 #define PIN_CFG_EPIO13 0x00000016 63 #define PIN_CFG_EPIO14 0x00000017 64 #define PIN_CFG_EPIO15 0x00000018 65 #define PIN_CFG_EPIO16 0x00000019 66 #define PIN_CFG_EPIO17 0x0000001a 67 #define PIN_CFG_EPIO18 0x0000001b 68 #define PIN_CFG_EPIO19 0x0000001c 69 #define PIN_CFG_EPIO20 0x0000001d 70 #define PIN_CFG_EPIO21 0x0000001e 71 #define PIN_CFG_EPIO22 0x0000001f 72 #define PIN_CFG_EPIO23 0x00000020 73 #define PIN_CFG_EPIO24 0x00000021 74 #define PIN_CFG_EPIO25 0x00000022 75 #define PIN_CFG_EPIO26 0x00000023 76 #define PIN_CFG_EPIO27 0x00000024 77 #define PIN_CFG_EPIO28 0x00000025 78 #define PIN_CFG_EPIO29 0x00000026 79 #define PIN_CFG_EPIO30 0x00000027 80 #define PIN_CFG_EPIO31 0x00000028 81 82 /* EPIO definition */ 83 #define EPIO_CFG_NA 0x00000000 84 #define EPIO_CFG_EPIO0 0x00000001 85 #define EPIO_CFG_EPIO1 0x00000002 86 #define EPIO_CFG_EPIO2 0x00000003 87 #define EPIO_CFG_EPIO3 0x00000004 88 #define EPIO_CFG_EPIO4 0x00000005 89 #define EPIO_CFG_EPIO5 0x00000006 90 #define EPIO_CFG_EPIO6 0x00000007 91 #define EPIO_CFG_EPIO7 0x00000008 92 #define EPIO_CFG_EPIO8 0x00000009 93 #define EPIO_CFG_EPIO9 0x0000000a 94 #define EPIO_CFG_EPIO10 0x0000000b 95 #define EPIO_CFG_EPIO11 0x0000000c 96 #define EPIO_CFG_EPIO12 0x0000000d 97 #define EPIO_CFG_EPIO13 0x0000000e 98 #define EPIO_CFG_EPIO14 0x0000000f 99 #define EPIO_CFG_EPIO15 0x00000010 100 #define EPIO_CFG_EPIO16 0x00000011 101 #define EPIO_CFG_EPIO17 0x00000012 102 #define EPIO_CFG_EPIO18 0x00000013 103 #define EPIO_CFG_EPIO19 0x00000014 104 #define EPIO_CFG_EPIO20 0x00000015 105 #define EPIO_CFG_EPIO21 0x00000016 106 #define EPIO_CFG_EPIO22 0x00000017 107 #define EPIO_CFG_EPIO23 0x00000018 108 #define EPIO_CFG_EPIO24 0x00000019 109 #define EPIO_CFG_EPIO25 0x0000001a 110 #define EPIO_CFG_EPIO26 0x0000001b 111 #define EPIO_CFG_EPIO27 0x0000001c 112 #define EPIO_CFG_EPIO28 0x0000001d 113 #define EPIO_CFG_EPIO29 0x0000001e 114 #define EPIO_CFG_EPIO30 0x0000001f 115 #define EPIO_CFG_EPIO31 0x00000020 116 117 struct mac_addr { 118 u32 upper; 119 u32 lower; 120 }; 121 122 struct shared_hw_cfg { /* NVRAM Offset */ 123 /* Up to 16 bytes of NULL-terminated string */ 124 u8 part_num[16]; /* 0x104 */ 125 126 u32 config; /* 0x114 */ 127 #define SHARED_HW_CFG_MDIO_VOLTAGE_MASK 0x00000001 128 #define SHARED_HW_CFG_MDIO_VOLTAGE_SHIFT 0 129 #define SHARED_HW_CFG_MDIO_VOLTAGE_1_2V 0x00000000 130 #define SHARED_HW_CFG_MDIO_VOLTAGE_2_5V 0x00000001 131 #define SHARED_HW_CFG_MCP_RST_ON_CORE_RST_EN 0x00000002 132 133 #define SHARED_HW_CFG_PORT_SWAP 0x00000004 134 135 #define SHARED_HW_CFG_BEACON_WOL_EN 0x00000008 136 137 #define SHARED_HW_CFG_PCIE_GEN3_DISABLED 0x00000000 138 #define SHARED_HW_CFG_PCIE_GEN3_ENABLED 0x00000010 139 140 #define SHARED_HW_CFG_MFW_SELECT_MASK 0x00000700 141 #define SHARED_HW_CFG_MFW_SELECT_SHIFT 8 142 /* Whatever MFW found in NVM 143 (if multiple found, priority order is: NC-SI, UMP, IPMI) */ 144 #define SHARED_HW_CFG_MFW_SELECT_DEFAULT 0x00000000 145 #define SHARED_HW_CFG_MFW_SELECT_NC_SI 0x00000100 146 #define SHARED_HW_CFG_MFW_SELECT_UMP 0x00000200 147 #define SHARED_HW_CFG_MFW_SELECT_IPMI 0x00000300 148 /* Use SPIO4 as an arbiter between: 0-NC_SI, 1-IPMI 149 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */ 150 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_IPMI 0x00000400 151 /* Use SPIO4 as an arbiter between: 0-UMP, 1-IPMI 152 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */ 153 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_UMP_IPMI 0x00000500 154 /* Use SPIO4 as an arbiter between: 0-NC-SI, 1-UMP 155 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */ 156 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_UMP 0x00000600 157 158 #define SHARED_HW_CFG_LED_MODE_MASK 0x000f0000 159 #define SHARED_HW_CFG_LED_MODE_SHIFT 16 160 #define SHARED_HW_CFG_LED_MAC1 0x00000000 161 #define SHARED_HW_CFG_LED_PHY1 0x00010000 162 #define SHARED_HW_CFG_LED_PHY2 0x00020000 163 #define SHARED_HW_CFG_LED_PHY3 0x00030000 164 #define SHARED_HW_CFG_LED_MAC2 0x00040000 165 #define SHARED_HW_CFG_LED_PHY4 0x00050000 166 #define SHARED_HW_CFG_LED_PHY5 0x00060000 167 #define SHARED_HW_CFG_LED_PHY6 0x00070000 168 #define SHARED_HW_CFG_LED_MAC3 0x00080000 169 #define SHARED_HW_CFG_LED_PHY7 0x00090000 170 #define SHARED_HW_CFG_LED_PHY9 0x000a0000 171 #define SHARED_HW_CFG_LED_PHY11 0x000b0000 172 #define SHARED_HW_CFG_LED_MAC4 0x000c0000 173 #define SHARED_HW_CFG_LED_PHY8 0x000d0000 174 #define SHARED_HW_CFG_LED_EXTPHY1 0x000e0000 175 176 177 #define SHARED_HW_CFG_AN_ENABLE_MASK 0x3f000000 178 #define SHARED_HW_CFG_AN_ENABLE_SHIFT 24 179 #define SHARED_HW_CFG_AN_ENABLE_CL37 0x01000000 180 #define SHARED_HW_CFG_AN_ENABLE_CL73 0x02000000 181 #define SHARED_HW_CFG_AN_ENABLE_BAM 0x04000000 182 #define SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION 0x08000000 183 #define SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT 0x10000000 184 #define SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY 0x20000000 185 186 #define SHARED_HW_CFG_SRIOV_MASK 0x40000000 187 #define SHARED_HW_CFG_SRIOV_DISABLED 0x00000000 188 #define SHARED_HW_CFG_SRIOV_ENABLED 0x40000000 189 190 #define SHARED_HW_CFG_ATC_MASK 0x80000000 191 #define SHARED_HW_CFG_ATC_DISABLED 0x00000000 192 #define SHARED_HW_CFG_ATC_ENABLED 0x80000000 193 194 u32 config2; /* 0x118 */ 195 /* one time auto detect grace period (in sec) */ 196 #define SHARED_HW_CFG_GRACE_PERIOD_MASK 0x000000ff 197 #define SHARED_HW_CFG_GRACE_PERIOD_SHIFT 0 198 199 #define SHARED_HW_CFG_PCIE_GEN2_ENABLED 0x00000100 200 #define SHARED_HW_CFG_PCIE_GEN2_DISABLED 0x00000000 201 202 /* The default value for the core clock is 250MHz and it is 203 achieved by setting the clock change to 4 */ 204 #define SHARED_HW_CFG_CLOCK_CHANGE_MASK 0x00000e00 205 #define SHARED_HW_CFG_CLOCK_CHANGE_SHIFT 9 206 207 #define SHARED_HW_CFG_SMBUS_TIMING_MASK 0x00001000 208 #define SHARED_HW_CFG_SMBUS_TIMING_100KHZ 0x00000000 209 #define SHARED_HW_CFG_SMBUS_TIMING_400KHZ 0x00001000 210 211 #define SHARED_HW_CFG_HIDE_PORT1 0x00002000 212 213 #define SHARED_HW_CFG_WOL_CAPABLE_MASK 0x00004000 214 #define SHARED_HW_CFG_WOL_CAPABLE_DISABLED 0x00000000 215 #define SHARED_HW_CFG_WOL_CAPABLE_ENABLED 0x00004000 216 217 /* Output low when PERST is asserted */ 218 #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_MASK 0x00008000 219 #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_DISABLED 0x00000000 220 #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_ENABLED 0x00008000 221 222 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_MASK 0x00070000 223 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_SHIFT 16 224 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_HW 0x00000000 225 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_0DB 0x00010000 226 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_3_5DB 0x00020000 227 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_6_0DB 0x00030000 228 229 /* The fan failure mechanism is usually related to the PHY type 230 since the power consumption of the board is determined by the PHY. 231 Currently, fan is required for most designs with SFX7101, BCM8727 232 and BCM8481. If a fan is not required for a board which uses one 233 of those PHYs, this field should be set to "Disabled". If a fan is 234 required for a different PHY type, this option should be set to 235 "Enabled". The fan failure indication is expected on SPIO5 */ 236 #define SHARED_HW_CFG_FAN_FAILURE_MASK 0x00180000 237 #define SHARED_HW_CFG_FAN_FAILURE_SHIFT 19 238 #define SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE 0x00000000 239 #define SHARED_HW_CFG_FAN_FAILURE_DISABLED 0x00080000 240 #define SHARED_HW_CFG_FAN_FAILURE_ENABLED 0x00100000 241 242 /* ASPM Power Management support */ 243 #define SHARED_HW_CFG_ASPM_SUPPORT_MASK 0x00600000 244 #define SHARED_HW_CFG_ASPM_SUPPORT_SHIFT 21 245 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_ENABLED 0x00000000 246 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_DISABLED 0x00200000 247 #define SHARED_HW_CFG_ASPM_SUPPORT_L1_DISABLED 0x00400000 248 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_DISABLED 0x00600000 249 250 /* The value of PM_TL_IGNORE_REQS (bit0) in PCI register 251 tl_control_0 (register 0x2800) */ 252 #define SHARED_HW_CFG_PREVENT_L1_ENTRY_MASK 0x00800000 253 #define SHARED_HW_CFG_PREVENT_L1_ENTRY_DISABLED 0x00000000 254 #define SHARED_HW_CFG_PREVENT_L1_ENTRY_ENABLED 0x00800000 255 256 #define SHARED_HW_CFG_PORT_MODE_MASK 0x01000000 257 #define SHARED_HW_CFG_PORT_MODE_2 0x00000000 258 #define SHARED_HW_CFG_PORT_MODE_4 0x01000000 259 260 #define SHARED_HW_CFG_PATH_SWAP_MASK 0x02000000 261 #define SHARED_HW_CFG_PATH_SWAP_DISABLED 0x00000000 262 #define SHARED_HW_CFG_PATH_SWAP_ENABLED 0x02000000 263 264 /* Set the MDC/MDIO access for the first external phy */ 265 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK 0x1C000000 266 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT 26 267 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE 0x00000000 268 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0 0x04000000 269 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1 0x08000000 270 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH 0x0c000000 271 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED 0x10000000 272 273 /* Set the MDC/MDIO access for the second external phy */ 274 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK 0xE0000000 275 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT 29 276 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_PHY_TYPE 0x00000000 277 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC0 0x20000000 278 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC1 0x40000000 279 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_BOTH 0x60000000 280 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SWAPPED 0x80000000 281 282 283 u32 power_dissipated; /* 0x11c */ 284 #define SHARED_HW_CFG_POWER_MGNT_SCALE_MASK 0x00ff0000 285 #define SHARED_HW_CFG_POWER_MGNT_SCALE_SHIFT 16 286 #define SHARED_HW_CFG_POWER_MGNT_UNKNOWN_SCALE 0x00000000 287 #define SHARED_HW_CFG_POWER_MGNT_DOT_1_WATT 0x00010000 288 #define SHARED_HW_CFG_POWER_MGNT_DOT_01_WATT 0x00020000 289 #define SHARED_HW_CFG_POWER_MGNT_DOT_001_WATT 0x00030000 290 291 #define SHARED_HW_CFG_POWER_DIS_CMN_MASK 0xff000000 292 #define SHARED_HW_CFG_POWER_DIS_CMN_SHIFT 24 293 294 u32 ump_nc_si_config; /* 0x120 */ 295 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MASK 0x00000003 296 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_SHIFT 0 297 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MAC 0x00000000 298 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_PHY 0x00000001 299 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MII 0x00000000 300 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_RMII 0x00000002 301 302 #define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_MASK 0x00000f00 303 #define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_SHIFT 8 304 305 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_MASK 0x00ff0000 306 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_SHIFT 16 307 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_NONE 0x00000000 308 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_BCM5221 0x00010000 309 310 u32 board; /* 0x124 */ 311 #define SHARED_HW_CFG_E3_I2C_MUX0_MASK 0x0000003F 312 #define SHARED_HW_CFG_E3_I2C_MUX0_SHIFT 0 313 #define SHARED_HW_CFG_E3_I2C_MUX1_MASK 0x00000FC0 314 #define SHARED_HW_CFG_E3_I2C_MUX1_SHIFT 6 315 /* Use the PIN_CFG_XXX defines on top */ 316 #define SHARED_HW_CFG_BOARD_REV_MASK 0x00ff0000 317 #define SHARED_HW_CFG_BOARD_REV_SHIFT 16 318 319 #define SHARED_HW_CFG_BOARD_MAJOR_VER_MASK 0x0f000000 320 #define SHARED_HW_CFG_BOARD_MAJOR_VER_SHIFT 24 321 322 #define SHARED_HW_CFG_BOARD_MINOR_VER_MASK 0xf0000000 323 #define SHARED_HW_CFG_BOARD_MINOR_VER_SHIFT 28 324 325 u32 wc_lane_config; /* 0x128 */ 326 #define SHARED_HW_CFG_LANE_SWAP_CFG_MASK 0x0000FFFF 327 #define SHARED_HW_CFG_LANE_SWAP_CFG_SHIFT 0 328 #define SHARED_HW_CFG_LANE_SWAP_CFG_32103210 0x00001b1b 329 #define SHARED_HW_CFG_LANE_SWAP_CFG_32100123 0x00001be4 330 #define SHARED_HW_CFG_LANE_SWAP_CFG_01233210 0x0000e41b 331 #define SHARED_HW_CFG_LANE_SWAP_CFG_01230123 0x0000e4e4 332 #define SHARED_HW_CFG_LANE_SWAP_CFG_TX_MASK 0x000000FF 333 #define SHARED_HW_CFG_LANE_SWAP_CFG_TX_SHIFT 0 334 #define SHARED_HW_CFG_LANE_SWAP_CFG_RX_MASK 0x0000FF00 335 #define SHARED_HW_CFG_LANE_SWAP_CFG_RX_SHIFT 8 336 337 /* TX lane Polarity swap */ 338 #define SHARED_HW_CFG_TX_LANE0_POL_FLIP_ENABLED 0x00010000 339 #define SHARED_HW_CFG_TX_LANE1_POL_FLIP_ENABLED 0x00020000 340 #define SHARED_HW_CFG_TX_LANE2_POL_FLIP_ENABLED 0x00040000 341 #define SHARED_HW_CFG_TX_LANE3_POL_FLIP_ENABLED 0x00080000 342 /* TX lane Polarity swap */ 343 #define SHARED_HW_CFG_RX_LANE0_POL_FLIP_ENABLED 0x00100000 344 #define SHARED_HW_CFG_RX_LANE1_POL_FLIP_ENABLED 0x00200000 345 #define SHARED_HW_CFG_RX_LANE2_POL_FLIP_ENABLED 0x00400000 346 #define SHARED_HW_CFG_RX_LANE3_POL_FLIP_ENABLED 0x00800000 347 348 /* Selects the port layout of the board */ 349 #define SHARED_HW_CFG_E3_PORT_LAYOUT_MASK 0x0F000000 350 #define SHARED_HW_CFG_E3_PORT_LAYOUT_SHIFT 24 351 #define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_01 0x00000000 352 #define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_10 0x01000000 353 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_0123 0x02000000 354 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_1032 0x03000000 355 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_2301 0x04000000 356 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_3210 0x05000000 357 }; 358 359 360 /**************************************************************************** 361 * Port HW configuration * 362 ****************************************************************************/ 363 struct port_hw_cfg { /* port 0: 0x12c port 1: 0x2bc */ 364 365 u32 pci_id; 366 #define PORT_HW_CFG_PCI_VENDOR_ID_MASK 0xffff0000 367 #define PORT_HW_CFG_PCI_DEVICE_ID_MASK 0x0000ffff 368 369 u32 pci_sub_id; 370 #define PORT_HW_CFG_PCI_SUBSYS_DEVICE_ID_MASK 0xffff0000 371 #define PORT_HW_CFG_PCI_SUBSYS_VENDOR_ID_MASK 0x0000ffff 372 373 u32 power_dissipated; 374 #define PORT_HW_CFG_POWER_DIS_D0_MASK 0x000000ff 375 #define PORT_HW_CFG_POWER_DIS_D0_SHIFT 0 376 #define PORT_HW_CFG_POWER_DIS_D1_MASK 0x0000ff00 377 #define PORT_HW_CFG_POWER_DIS_D1_SHIFT 8 378 #define PORT_HW_CFG_POWER_DIS_D2_MASK 0x00ff0000 379 #define PORT_HW_CFG_POWER_DIS_D2_SHIFT 16 380 #define PORT_HW_CFG_POWER_DIS_D3_MASK 0xff000000 381 #define PORT_HW_CFG_POWER_DIS_D3_SHIFT 24 382 383 u32 power_consumed; 384 #define PORT_HW_CFG_POWER_CONS_D0_MASK 0x000000ff 385 #define PORT_HW_CFG_POWER_CONS_D0_SHIFT 0 386 #define PORT_HW_CFG_POWER_CONS_D1_MASK 0x0000ff00 387 #define PORT_HW_CFG_POWER_CONS_D1_SHIFT 8 388 #define PORT_HW_CFG_POWER_CONS_D2_MASK 0x00ff0000 389 #define PORT_HW_CFG_POWER_CONS_D2_SHIFT 16 390 #define PORT_HW_CFG_POWER_CONS_D3_MASK 0xff000000 391 #define PORT_HW_CFG_POWER_CONS_D3_SHIFT 24 392 393 u32 mac_upper; 394 #define PORT_HW_CFG_UPPERMAC_MASK 0x0000ffff 395 #define PORT_HW_CFG_UPPERMAC_SHIFT 0 396 u32 mac_lower; 397 398 u32 iscsi_mac_upper; /* Upper 16 bits are always zeroes */ 399 u32 iscsi_mac_lower; 400 401 u32 rdma_mac_upper; /* Upper 16 bits are always zeroes */ 402 u32 rdma_mac_lower; 403 404 u32 serdes_config; 405 #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_MASK 0x0000ffff 406 #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_SHIFT 0 407 408 #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK 0xffff0000 409 #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT 16 410 411 412 /* Default values: 2P-64, 4P-32 */ 413 u32 pf_config; /* 0x158 */ 414 #define PORT_HW_CFG_PF_NUM_VF_MASK 0x0000007F 415 #define PORT_HW_CFG_PF_NUM_VF_SHIFT 0 416 417 /* Default values: 17 */ 418 #define PORT_HW_CFG_PF_NUM_MSIX_VECTORS_MASK 0x00007F00 419 #define PORT_HW_CFG_PF_NUM_MSIX_VECTORS_SHIFT 8 420 421 #define PORT_HW_CFG_ENABLE_FLR_MASK 0x00010000 422 #define PORT_HW_CFG_FLR_ENABLED 0x00010000 423 424 u32 vf_config; /* 0x15C */ 425 #define PORT_HW_CFG_VF_NUM_MSIX_VECTORS_MASK 0x0000007F 426 #define PORT_HW_CFG_VF_NUM_MSIX_VECTORS_SHIFT 0 427 428 #define PORT_HW_CFG_VF_PCI_DEVICE_ID_MASK 0xFFFF0000 429 #define PORT_HW_CFG_VF_PCI_DEVICE_ID_SHIFT 16 430 431 u32 mf_pci_id; /* 0x160 */ 432 #define PORT_HW_CFG_MF_PCI_DEVICE_ID_MASK 0x0000FFFF 433 #define PORT_HW_CFG_MF_PCI_DEVICE_ID_SHIFT 0 434 435 /* Controls the TX laser of the SFP+ module */ 436 u32 sfp_ctrl; /* 0x164 */ 437 #define PORT_HW_CFG_TX_LASER_MASK 0x000000FF 438 #define PORT_HW_CFG_TX_LASER_SHIFT 0 439 #define PORT_HW_CFG_TX_LASER_MDIO 0x00000000 440 #define PORT_HW_CFG_TX_LASER_GPIO0 0x00000001 441 #define PORT_HW_CFG_TX_LASER_GPIO1 0x00000002 442 #define PORT_HW_CFG_TX_LASER_GPIO2 0x00000003 443 #define PORT_HW_CFG_TX_LASER_GPIO3 0x00000004 444 445 /* Controls the fault module LED of the SFP+ */ 446 #define PORT_HW_CFG_FAULT_MODULE_LED_MASK 0x0000FF00 447 #define PORT_HW_CFG_FAULT_MODULE_LED_SHIFT 8 448 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO0 0x00000000 449 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO1 0x00000100 450 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO2 0x00000200 451 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO3 0x00000300 452 #define PORT_HW_CFG_FAULT_MODULE_LED_DISABLED 0x00000400 453 454 /* The output pin TX_DIS that controls the TX laser of the SFP+ 455 module. Use the PIN_CFG_XXX defines on top */ 456 u32 e3_sfp_ctrl; /* 0x168 */ 457 #define PORT_HW_CFG_E3_TX_LASER_MASK 0x000000FF 458 #define PORT_HW_CFG_E3_TX_LASER_SHIFT 0 459 460 /* The output pin for SFPP_TYPE which turns on the Fault module LED */ 461 #define PORT_HW_CFG_E3_FAULT_MDL_LED_MASK 0x0000FF00 462 #define PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT 8 463 464 /* The input pin MOD_ABS that indicates whether SFP+ module is 465 present or not. Use the PIN_CFG_XXX defines on top */ 466 #define PORT_HW_CFG_E3_MOD_ABS_MASK 0x00FF0000 467 #define PORT_HW_CFG_E3_MOD_ABS_SHIFT 16 468 469 /* The output pin PWRDIS_SFP_X which disable the power of the SFP+ 470 module. Use the PIN_CFG_XXX defines on top */ 471 #define PORT_HW_CFG_E3_PWR_DIS_MASK 0xFF000000 472 #define PORT_HW_CFG_E3_PWR_DIS_SHIFT 24 473 474 /* 475 * The input pin which signals module transmit fault. Use the 476 * PIN_CFG_XXX defines on top 477 */ 478 u32 e3_cmn_pin_cfg; /* 0x16C */ 479 #define PORT_HW_CFG_E3_TX_FAULT_MASK 0x000000FF 480 #define PORT_HW_CFG_E3_TX_FAULT_SHIFT 0 481 482 /* The output pin which reset the PHY. Use the PIN_CFG_XXX defines on 483 top */ 484 #define PORT_HW_CFG_E3_PHY_RESET_MASK 0x0000FF00 485 #define PORT_HW_CFG_E3_PHY_RESET_SHIFT 8 486 487 /* 488 * The output pin which powers down the PHY. Use the PIN_CFG_XXX 489 * defines on top 490 */ 491 #define PORT_HW_CFG_E3_PWR_DOWN_MASK 0x00FF0000 492 #define PORT_HW_CFG_E3_PWR_DOWN_SHIFT 16 493 494 /* The output pin values BSC_SEL which selects the I2C for this port 495 in the I2C Mux */ 496 #define PORT_HW_CFG_E3_I2C_MUX0_MASK 0x01000000 497 #define PORT_HW_CFG_E3_I2C_MUX1_MASK 0x02000000 498 499 500 /* 501 * The input pin I_FAULT which indicate over-current has occurred. 502 * Use the PIN_CFG_XXX defines on top 503 */ 504 u32 e3_cmn_pin_cfg1; /* 0x170 */ 505 #define PORT_HW_CFG_E3_OVER_CURRENT_MASK 0x000000FF 506 #define PORT_HW_CFG_E3_OVER_CURRENT_SHIFT 0 507 508 /* pause on host ring */ 509 u32 generic_features; /* 0x174 */ 510 #define PORT_HW_CFG_PAUSE_ON_HOST_RING_MASK 0x00000001 511 #define PORT_HW_CFG_PAUSE_ON_HOST_RING_SHIFT 0 512 #define PORT_HW_CFG_PAUSE_ON_HOST_RING_DISABLED 0x00000000 513 #define PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED 0x00000001 514 515 /* SFP+ Tx Equalization: NIC recommended and tested value is 0xBEB2 516 * LOM recommended and tested value is 0xBEB2. Using a different 517 * value means using a value not tested by BRCM 518 */ 519 u32 sfi_tap_values; /* 0x178 */ 520 #define PORT_HW_CFG_TX_EQUALIZATION_MASK 0x0000FFFF 521 #define PORT_HW_CFG_TX_EQUALIZATION_SHIFT 0 522 523 /* SFP+ Tx driver broadcast IDRIVER: NIC recommended and tested 524 * value is 0x2. LOM recommended and tested value is 0x2. Using a 525 * different value means using a value not tested by BRCM 526 */ 527 #define PORT_HW_CFG_TX_DRV_BROADCAST_MASK 0x000F0000 528 #define PORT_HW_CFG_TX_DRV_BROADCAST_SHIFT 16 529 530 u32 reserved0[5]; /* 0x17c */ 531 532 u32 aeu_int_mask; /* 0x190 */ 533 534 u32 media_type; /* 0x194 */ 535 #define PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK 0x000000FF 536 #define PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT 0 537 538 #define PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK 0x0000FF00 539 #define PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT 8 540 541 #define PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK 0x00FF0000 542 #define PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT 16 543 544 /* 4 times 16 bits for all 4 lanes. In case external PHY is present 545 (not direct mode), those values will not take effect on the 4 XGXS 546 lanes. For some external PHYs (such as 8706 and 8726) the values 547 will be used to configure the external PHY in those cases, not 548 all 4 values are needed. */ 549 u16 xgxs_config_rx[4]; /* 0x198 */ 550 u16 xgxs_config_tx[4]; /* 0x1A0 */ 551 552 /* For storing FCOE mac on shared memory */ 553 u32 fcoe_fip_mac_upper; 554 #define PORT_HW_CFG_FCOE_UPPERMAC_MASK 0x0000ffff 555 #define PORT_HW_CFG_FCOE_UPPERMAC_SHIFT 0 556 u32 fcoe_fip_mac_lower; 557 558 u32 fcoe_wwn_port_name_upper; 559 u32 fcoe_wwn_port_name_lower; 560 561 u32 fcoe_wwn_node_name_upper; 562 u32 fcoe_wwn_node_name_lower; 563 564 u32 Reserved1[49]; /* 0x1C0 */ 565 566 /* Enable RJ45 magjack pair swapping on 10GBase-T PHY (0=default), 567 84833 only */ 568 u32 xgbt_phy_cfg; /* 0x284 */ 569 #define PORT_HW_CFG_RJ45_PAIR_SWAP_MASK 0x000000FF 570 #define PORT_HW_CFG_RJ45_PAIR_SWAP_SHIFT 0 571 572 u32 default_cfg; /* 0x288 */ 573 #define PORT_HW_CFG_GPIO0_CONFIG_MASK 0x00000003 574 #define PORT_HW_CFG_GPIO0_CONFIG_SHIFT 0 575 #define PORT_HW_CFG_GPIO0_CONFIG_NA 0x00000000 576 #define PORT_HW_CFG_GPIO0_CONFIG_LOW 0x00000001 577 #define PORT_HW_CFG_GPIO0_CONFIG_HIGH 0x00000002 578 #define PORT_HW_CFG_GPIO0_CONFIG_INPUT 0x00000003 579 580 #define PORT_HW_CFG_GPIO1_CONFIG_MASK 0x0000000C 581 #define PORT_HW_CFG_GPIO1_CONFIG_SHIFT 2 582 #define PORT_HW_CFG_GPIO1_CONFIG_NA 0x00000000 583 #define PORT_HW_CFG_GPIO1_CONFIG_LOW 0x00000004 584 #define PORT_HW_CFG_GPIO1_CONFIG_HIGH 0x00000008 585 #define PORT_HW_CFG_GPIO1_CONFIG_INPUT 0x0000000c 586 587 #define PORT_HW_CFG_GPIO2_CONFIG_MASK 0x00000030 588 #define PORT_HW_CFG_GPIO2_CONFIG_SHIFT 4 589 #define PORT_HW_CFG_GPIO2_CONFIG_NA 0x00000000 590 #define PORT_HW_CFG_GPIO2_CONFIG_LOW 0x00000010 591 #define PORT_HW_CFG_GPIO2_CONFIG_HIGH 0x00000020 592 #define PORT_HW_CFG_GPIO2_CONFIG_INPUT 0x00000030 593 594 #define PORT_HW_CFG_GPIO3_CONFIG_MASK 0x000000C0 595 #define PORT_HW_CFG_GPIO3_CONFIG_SHIFT 6 596 #define PORT_HW_CFG_GPIO3_CONFIG_NA 0x00000000 597 #define PORT_HW_CFG_GPIO3_CONFIG_LOW 0x00000040 598 #define PORT_HW_CFG_GPIO3_CONFIG_HIGH 0x00000080 599 #define PORT_HW_CFG_GPIO3_CONFIG_INPUT 0x000000c0 600 601 /* When KR link is required to be set to force which is not 602 KR-compliant, this parameter determine what is the trigger for it. 603 When GPIO is selected, low input will force the speed. Currently 604 default speed is 1G. In the future, it may be widen to select the 605 forced speed in with another parameter. Note when force-1G is 606 enabled, it override option 56: Link Speed option. */ 607 #define PORT_HW_CFG_FORCE_KR_ENABLER_MASK 0x00000F00 608 #define PORT_HW_CFG_FORCE_KR_ENABLER_SHIFT 8 609 #define PORT_HW_CFG_FORCE_KR_ENABLER_NOT_FORCED 0x00000000 610 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P0 0x00000100 611 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P0 0x00000200 612 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P0 0x00000300 613 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P0 0x00000400 614 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P1 0x00000500 615 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P1 0x00000600 616 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P1 0x00000700 617 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P1 0x00000800 618 #define PORT_HW_CFG_FORCE_KR_ENABLER_FORCED 0x00000900 619 /* Enable to determine with which GPIO to reset the external phy */ 620 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK 0x000F0000 621 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT 16 622 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_PHY_TYPE 0x00000000 623 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0 0x00010000 624 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0 0x00020000 625 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0 0x00030000 626 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0 0x00040000 627 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1 0x00050000 628 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1 0x00060000 629 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1 0x00070000 630 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1 0x00080000 631 632 /* Enable BAM on KR */ 633 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_MASK 0x00100000 634 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_SHIFT 20 635 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_DISABLED 0x00000000 636 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED 0x00100000 637 638 /* Enable Common Mode Sense */ 639 #define PORT_HW_CFG_ENABLE_CMS_MASK 0x00200000 640 #define PORT_HW_CFG_ENABLE_CMS_SHIFT 21 641 #define PORT_HW_CFG_ENABLE_CMS_DISABLED 0x00000000 642 #define PORT_HW_CFG_ENABLE_CMS_ENABLED 0x00200000 643 644 /* Determine the Serdes electrical interface */ 645 #define PORT_HW_CFG_NET_SERDES_IF_MASK 0x0F000000 646 #define PORT_HW_CFG_NET_SERDES_IF_SHIFT 24 647 #define PORT_HW_CFG_NET_SERDES_IF_SGMII 0x00000000 648 #define PORT_HW_CFG_NET_SERDES_IF_XFI 0x01000000 649 #define PORT_HW_CFG_NET_SERDES_IF_SFI 0x02000000 650 #define PORT_HW_CFG_NET_SERDES_IF_KR 0x03000000 651 #define PORT_HW_CFG_NET_SERDES_IF_DXGXS 0x04000000 652 #define PORT_HW_CFG_NET_SERDES_IF_KR2 0x05000000 653 654 655 u32 speed_capability_mask2; /* 0x28C */ 656 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_MASK 0x0000FFFF 657 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_SHIFT 0 658 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10M_FULL 0x00000001 659 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3__ 0x00000002 660 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3___ 0x00000004 661 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_100M_FULL 0x00000008 662 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_1G 0x00000010 663 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_2_DOT_5G 0x00000020 664 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10G 0x00000040 665 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_20G 0x00000080 666 667 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_MASK 0xFFFF0000 668 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_SHIFT 16 669 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10M_FULL 0x00010000 670 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0__ 0x00020000 671 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0___ 0x00040000 672 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_100M_FULL 0x00080000 673 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_1G 0x00100000 674 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_2_DOT_5G 0x00200000 675 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10G 0x00400000 676 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_20G 0x00800000 677 678 679 /* In the case where two media types (e.g. copper and fiber) are 680 present and electrically active at the same time, PHY Selection 681 will determine which of the two PHYs will be designated as the 682 Active PHY and used for a connection to the network. */ 683 u32 multi_phy_config; /* 0x290 */ 684 #define PORT_HW_CFG_PHY_SELECTION_MASK 0x00000007 685 #define PORT_HW_CFG_PHY_SELECTION_SHIFT 0 686 #define PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT 0x00000000 687 #define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY 0x00000001 688 #define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY 0x00000002 689 #define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY 0x00000003 690 #define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY 0x00000004 691 692 /* When enabled, all second phy nvram parameters will be swapped 693 with the first phy parameters */ 694 #define PORT_HW_CFG_PHY_SWAPPED_MASK 0x00000008 695 #define PORT_HW_CFG_PHY_SWAPPED_SHIFT 3 696 #define PORT_HW_CFG_PHY_SWAPPED_DISABLED 0x00000000 697 #define PORT_HW_CFG_PHY_SWAPPED_ENABLED 0x00000008 698 699 700 /* Address of the second external phy */ 701 u32 external_phy_config2; /* 0x294 */ 702 #define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_MASK 0x000000FF 703 #define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_SHIFT 0 704 705 /* The second XGXS external PHY type */ 706 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_MASK 0x0000FF00 707 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SHIFT 8 708 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_DIRECT 0x00000000 709 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8071 0x00000100 710 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8072 0x00000200 711 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8073 0x00000300 712 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8705 0x00000400 713 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8706 0x00000500 714 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8726 0x00000600 715 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8481 0x00000700 716 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SFX7101 0x00000800 717 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727 0x00000900 718 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727_NOC 0x00000a00 719 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84823 0x00000b00 720 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54640 0x00000c00 721 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84833 0x00000d00 722 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54618SE 0x00000e00 723 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8722 0x00000f00 724 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54616 0x00001000 725 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84834 0x00001100 726 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_FAILURE 0x0000fd00 727 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_NOT_CONN 0x0000ff00 728 729 730 /* 4 times 16 bits for all 4 lanes. For some external PHYs (such as 731 8706, 8726 and 8727) not all 4 values are needed. */ 732 u16 xgxs_config2_rx[4]; /* 0x296 */ 733 u16 xgxs_config2_tx[4]; /* 0x2A0 */ 734 735 u32 lane_config; 736 #define PORT_HW_CFG_LANE_SWAP_CFG_MASK 0x0000ffff 737 #define PORT_HW_CFG_LANE_SWAP_CFG_SHIFT 0 738 /* AN and forced */ 739 #define PORT_HW_CFG_LANE_SWAP_CFG_01230123 0x00001b1b 740 /* forced only */ 741 #define PORT_HW_CFG_LANE_SWAP_CFG_01233210 0x00001be4 742 /* forced only */ 743 #define PORT_HW_CFG_LANE_SWAP_CFG_31203120 0x0000d8d8 744 /* forced only */ 745 #define PORT_HW_CFG_LANE_SWAP_CFG_32103210 0x0000e4e4 746 #define PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK 0x000000ff 747 #define PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT 0 748 #define PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK 0x0000ff00 749 #define PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT 8 750 #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK 0x0000c000 751 #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT 14 752 753 /* Indicate whether to swap the external phy polarity */ 754 #define PORT_HW_CFG_SWAP_PHY_POLARITY_MASK 0x00010000 755 #define PORT_HW_CFG_SWAP_PHY_POLARITY_DISABLED 0x00000000 756 #define PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED 0x00010000 757 758 759 u32 external_phy_config; 760 #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK 0x000000ff 761 #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT 0 762 763 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK 0x0000ff00 764 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SHIFT 8 765 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT 0x00000000 766 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8071 0x00000100 767 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072 0x00000200 768 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073 0x00000300 769 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705 0x00000400 770 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706 0x00000500 771 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726 0x00000600 772 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481 0x00000700 773 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101 0x00000800 774 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727 0x00000900 775 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC 0x00000a00 776 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823 0x00000b00 777 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54640 0x00000c00 778 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833 0x00000d00 779 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE 0x00000e00 780 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722 0x00000f00 781 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616 0x00001000 782 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834 0x00001100 783 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT_WC 0x0000fc00 784 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE 0x0000fd00 785 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN 0x0000ff00 786 787 #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK 0x00ff0000 788 #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_SHIFT 16 789 790 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK 0xff000000 791 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_SHIFT 24 792 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT 0x00000000 793 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482 0x01000000 794 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD 0x02000000 795 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN 0xff000000 796 797 u32 speed_capability_mask; 798 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_MASK 0x0000ffff 799 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_SHIFT 0 800 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_FULL 0x00000001 801 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_HALF 0x00000002 802 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_HALF 0x00000004 803 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_FULL 0x00000008 804 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_1G 0x00000010 805 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_2_5G 0x00000020 806 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10G 0x00000040 807 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_20G 0x00000080 808 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_RESERVED 0x0000f000 809 810 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK 0xffff0000 811 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_SHIFT 16 812 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL 0x00010000 813 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF 0x00020000 814 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF 0x00040000 815 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL 0x00080000 816 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_1G 0x00100000 817 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G 0x00200000 818 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10G 0x00400000 819 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_20G 0x00800000 820 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_RESERVED 0xf0000000 821 822 /* A place to hold the original MAC address as a backup */ 823 u32 backup_mac_upper; /* 0x2B4 */ 824 u32 backup_mac_lower; /* 0x2B8 */ 825 826 }; 827 828 829 /**************************************************************************** 830 * Shared Feature configuration * 831 ****************************************************************************/ 832 struct shared_feat_cfg { /* NVRAM Offset */ 833 834 u32 config; /* 0x450 */ 835 #define SHARED_FEATURE_BMC_ECHO_MODE_EN 0x00000001 836 837 /* Use NVRAM values instead of HW default values */ 838 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_MASK \ 839 0x00000002 840 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_DISABLED \ 841 0x00000000 842 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED \ 843 0x00000002 844 845 #define SHARED_FEAT_CFG_NCSI_ID_METHOD_MASK 0x00000008 846 #define SHARED_FEAT_CFG_NCSI_ID_METHOD_SPIO 0x00000000 847 #define SHARED_FEAT_CFG_NCSI_ID_METHOD_NVRAM 0x00000008 848 849 #define SHARED_FEAT_CFG_NCSI_ID_MASK 0x00000030 850 #define SHARED_FEAT_CFG_NCSI_ID_SHIFT 4 851 852 /* Override the OTP back to single function mode. When using GPIO, 853 high means only SF, 0 is according to CLP configuration */ 854 #define SHARED_FEAT_CFG_FORCE_SF_MODE_MASK 0x00000700 855 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SHIFT 8 856 #define SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED 0x00000000 857 #define SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF 0x00000100 858 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4 0x00000200 859 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT 0x00000300 860 #define SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE 0x00000400 861 862 /* The interval in seconds between sending LLDP packets. Set to zero 863 to disable the feature */ 864 #define SHARED_FEAT_CFG_LLDP_XMIT_INTERVAL_MASK 0x00ff0000 865 #define SHARED_FEAT_CFG_LLDP_XMIT_INTERVAL_SHIFT 16 866 867 /* The assigned device type ID for LLDP usage */ 868 #define SHARED_FEAT_CFG_LLDP_DEVICE_TYPE_ID_MASK 0xff000000 869 #define SHARED_FEAT_CFG_LLDP_DEVICE_TYPE_ID_SHIFT 24 870 871 }; 872 873 874 /**************************************************************************** 875 * Port Feature configuration * 876 ****************************************************************************/ 877 struct port_feat_cfg { /* port 0: 0x454 port 1: 0x4c8 */ 878 879 u32 config; 880 #define PORT_FEATURE_BAR1_SIZE_MASK 0x0000000f 881 #define PORT_FEATURE_BAR1_SIZE_SHIFT 0 882 #define PORT_FEATURE_BAR1_SIZE_DISABLED 0x00000000 883 #define PORT_FEATURE_BAR1_SIZE_64K 0x00000001 884 #define PORT_FEATURE_BAR1_SIZE_128K 0x00000002 885 #define PORT_FEATURE_BAR1_SIZE_256K 0x00000003 886 #define PORT_FEATURE_BAR1_SIZE_512K 0x00000004 887 #define PORT_FEATURE_BAR1_SIZE_1M 0x00000005 888 #define PORT_FEATURE_BAR1_SIZE_2M 0x00000006 889 #define PORT_FEATURE_BAR1_SIZE_4M 0x00000007 890 #define PORT_FEATURE_BAR1_SIZE_8M 0x00000008 891 #define PORT_FEATURE_BAR1_SIZE_16M 0x00000009 892 #define PORT_FEATURE_BAR1_SIZE_32M 0x0000000a 893 #define PORT_FEATURE_BAR1_SIZE_64M 0x0000000b 894 #define PORT_FEATURE_BAR1_SIZE_128M 0x0000000c 895 #define PORT_FEATURE_BAR1_SIZE_256M 0x0000000d 896 #define PORT_FEATURE_BAR1_SIZE_512M 0x0000000e 897 #define PORT_FEATURE_BAR1_SIZE_1G 0x0000000f 898 #define PORT_FEATURE_BAR2_SIZE_MASK 0x000000f0 899 #define PORT_FEATURE_BAR2_SIZE_SHIFT 4 900 #define PORT_FEATURE_BAR2_SIZE_DISABLED 0x00000000 901 #define PORT_FEATURE_BAR2_SIZE_64K 0x00000010 902 #define PORT_FEATURE_BAR2_SIZE_128K 0x00000020 903 #define PORT_FEATURE_BAR2_SIZE_256K 0x00000030 904 #define PORT_FEATURE_BAR2_SIZE_512K 0x00000040 905 #define PORT_FEATURE_BAR2_SIZE_1M 0x00000050 906 #define PORT_FEATURE_BAR2_SIZE_2M 0x00000060 907 #define PORT_FEATURE_BAR2_SIZE_4M 0x00000070 908 #define PORT_FEATURE_BAR2_SIZE_8M 0x00000080 909 #define PORT_FEATURE_BAR2_SIZE_16M 0x00000090 910 #define PORT_FEATURE_BAR2_SIZE_32M 0x000000a0 911 #define PORT_FEATURE_BAR2_SIZE_64M 0x000000b0 912 #define PORT_FEATURE_BAR2_SIZE_128M 0x000000c0 913 #define PORT_FEATURE_BAR2_SIZE_256M 0x000000d0 914 #define PORT_FEATURE_BAR2_SIZE_512M 0x000000e0 915 #define PORT_FEATURE_BAR2_SIZE_1G 0x000000f0 916 917 #define PORT_FEAT_CFG_DCBX_MASK 0x00000100 918 #define PORT_FEAT_CFG_DCBX_DISABLED 0x00000000 919 #define PORT_FEAT_CFG_DCBX_ENABLED 0x00000100 920 921 #define PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK 0x00000C00 922 #define PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE 0x00000400 923 #define PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI 0x00000800 924 925 #define PORT_FEATURE_EN_SIZE_MASK 0x0f000000 926 #define PORT_FEATURE_EN_SIZE_SHIFT 24 927 #define PORT_FEATURE_WOL_ENABLED 0x01000000 928 #define PORT_FEATURE_MBA_ENABLED 0x02000000 929 #define PORT_FEATURE_MFW_ENABLED 0x04000000 930 931 /* Advertise expansion ROM even if MBA is disabled */ 932 #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_MASK 0x08000000 933 #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_DISABLED 0x00000000 934 #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_ENABLED 0x08000000 935 936 /* Check the optic vendor via i2c against a list of approved modules 937 in a separate nvram image */ 938 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK 0xe0000000 939 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_SHIFT 29 940 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT \ 941 0x00000000 942 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER \ 943 0x20000000 944 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG 0x40000000 945 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN 0x60000000 946 947 u32 wol_config; 948 /* Default is used when driver sets to "auto" mode */ 949 #define PORT_FEATURE_WOL_DEFAULT_MASK 0x00000003 950 #define PORT_FEATURE_WOL_DEFAULT_SHIFT 0 951 #define PORT_FEATURE_WOL_DEFAULT_DISABLE 0x00000000 952 #define PORT_FEATURE_WOL_DEFAULT_MAGIC 0x00000001 953 #define PORT_FEATURE_WOL_DEFAULT_ACPI 0x00000002 954 #define PORT_FEATURE_WOL_DEFAULT_MAGIC_AND_ACPI 0x00000003 955 #define PORT_FEATURE_WOL_RES_PAUSE_CAP 0x00000004 956 #define PORT_FEATURE_WOL_RES_ASYM_PAUSE_CAP 0x00000008 957 #define PORT_FEATURE_WOL_ACPI_UPON_MGMT 0x00000010 958 959 u32 mba_config; 960 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK 0x00000007 961 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT 0 962 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE 0x00000000 963 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL 0x00000001 964 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP 0x00000002 965 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB 0x00000003 966 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT 0x00000004 967 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE 0x00000007 968 969 #define PORT_FEATURE_MBA_BOOT_RETRY_MASK 0x00000038 970 #define PORT_FEATURE_MBA_BOOT_RETRY_SHIFT 3 971 972 #define PORT_FEATURE_MBA_RES_PAUSE_CAP 0x00000100 973 #define PORT_FEATURE_MBA_RES_ASYM_PAUSE_CAP 0x00000200 974 #define PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE 0x00000400 975 #define PORT_FEATURE_MBA_HOTKEY_MASK 0x00000800 976 #define PORT_FEATURE_MBA_HOTKEY_CTRL_S 0x00000000 977 #define PORT_FEATURE_MBA_HOTKEY_CTRL_B 0x00000800 978 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK 0x000ff000 979 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT 12 980 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED 0x00000000 981 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2K 0x00001000 982 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4K 0x00002000 983 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8K 0x00003000 984 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16K 0x00004000 985 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32K 0x00005000 986 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_64K 0x00006000 987 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_128K 0x00007000 988 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_256K 0x00008000 989 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_512K 0x00009000 990 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_1M 0x0000a000 991 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2M 0x0000b000 992 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4M 0x0000c000 993 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8M 0x0000d000 994 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16M 0x0000e000 995 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32M 0x0000f000 996 #define PORT_FEATURE_MBA_MSG_TIMEOUT_MASK 0x00f00000 997 #define PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT 20 998 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK 0x03000000 999 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT 24 1000 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO 0x00000000 1001 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS 0x01000000 1002 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H 0x02000000 1003 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H 0x03000000 1004 #define PORT_FEATURE_MBA_LINK_SPEED_MASK 0x3c000000 1005 #define PORT_FEATURE_MBA_LINK_SPEED_SHIFT 26 1006 #define PORT_FEATURE_MBA_LINK_SPEED_AUTO 0x00000000 1007 #define PORT_FEATURE_MBA_LINK_SPEED_10HD 0x04000000 1008 #define PORT_FEATURE_MBA_LINK_SPEED_10FD 0x08000000 1009 #define PORT_FEATURE_MBA_LINK_SPEED_100HD 0x0c000000 1010 #define PORT_FEATURE_MBA_LINK_SPEED_100FD 0x10000000 1011 #define PORT_FEATURE_MBA_LINK_SPEED_1GBPS 0x14000000 1012 #define PORT_FEATURE_MBA_LINK_SPEED_2_5GBPS 0x18000000 1013 #define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_CX4 0x1c000000 1014 #define PORT_FEATURE_MBA_LINK_SPEED_20GBPS 0x20000000 1015 u32 bmc_config; 1016 #define PORT_FEATURE_BMC_LINK_OVERRIDE_MASK 0x00000001 1017 #define PORT_FEATURE_BMC_LINK_OVERRIDE_DEFAULT 0x00000000 1018 #define PORT_FEATURE_BMC_LINK_OVERRIDE_EN 0x00000001 1019 1020 u32 mba_vlan_cfg; 1021 #define PORT_FEATURE_MBA_VLAN_TAG_MASK 0x0000ffff 1022 #define PORT_FEATURE_MBA_VLAN_TAG_SHIFT 0 1023 #define PORT_FEATURE_MBA_VLAN_EN 0x00010000 1024 1025 u32 resource_cfg; 1026 #define PORT_FEATURE_RESOURCE_CFG_VALID 0x00000001 1027 #define PORT_FEATURE_RESOURCE_CFG_DIAG 0x00000002 1028 #define PORT_FEATURE_RESOURCE_CFG_L2 0x00000004 1029 #define PORT_FEATURE_RESOURCE_CFG_ISCSI 0x00000008 1030 #define PORT_FEATURE_RESOURCE_CFG_RDMA 0x00000010 1031 1032 u32 smbus_config; 1033 #define PORT_FEATURE_SMBUS_ADDR_MASK 0x000000fe 1034 #define PORT_FEATURE_SMBUS_ADDR_SHIFT 1 1035 1036 u32 vf_config; 1037 #define PORT_FEAT_CFG_VF_BAR2_SIZE_MASK 0x0000000f 1038 #define PORT_FEAT_CFG_VF_BAR2_SIZE_SHIFT 0 1039 #define PORT_FEAT_CFG_VF_BAR2_SIZE_DISABLED 0x00000000 1040 #define PORT_FEAT_CFG_VF_BAR2_SIZE_4K 0x00000001 1041 #define PORT_FEAT_CFG_VF_BAR2_SIZE_8K 0x00000002 1042 #define PORT_FEAT_CFG_VF_BAR2_SIZE_16K 0x00000003 1043 #define PORT_FEAT_CFG_VF_BAR2_SIZE_32K 0x00000004 1044 #define PORT_FEAT_CFG_VF_BAR2_SIZE_64K 0x00000005 1045 #define PORT_FEAT_CFG_VF_BAR2_SIZE_128K 0x00000006 1046 #define PORT_FEAT_CFG_VF_BAR2_SIZE_256K 0x00000007 1047 #define PORT_FEAT_CFG_VF_BAR2_SIZE_512K 0x00000008 1048 #define PORT_FEAT_CFG_VF_BAR2_SIZE_1M 0x00000009 1049 #define PORT_FEAT_CFG_VF_BAR2_SIZE_2M 0x0000000a 1050 #define PORT_FEAT_CFG_VF_BAR2_SIZE_4M 0x0000000b 1051 #define PORT_FEAT_CFG_VF_BAR2_SIZE_8M 0x0000000c 1052 #define PORT_FEAT_CFG_VF_BAR2_SIZE_16M 0x0000000d 1053 #define PORT_FEAT_CFG_VF_BAR2_SIZE_32M 0x0000000e 1054 #define PORT_FEAT_CFG_VF_BAR2_SIZE_64M 0x0000000f 1055 1056 u32 link_config; /* Used as HW defaults for the driver */ 1057 #define PORT_FEATURE_CONNECTED_SWITCH_MASK 0x03000000 1058 #define PORT_FEATURE_CONNECTED_SWITCH_SHIFT 24 1059 /* (forced) low speed switch (< 10G) */ 1060 #define PORT_FEATURE_CON_SWITCH_1G_SWITCH 0x00000000 1061 /* (forced) high speed switch (>= 10G) */ 1062 #define PORT_FEATURE_CON_SWITCH_10G_SWITCH 0x01000000 1063 #define PORT_FEATURE_CON_SWITCH_AUTO_DETECT 0x02000000 1064 #define PORT_FEATURE_CON_SWITCH_ONE_TIME_DETECT 0x03000000 1065 1066 #define PORT_FEATURE_LINK_SPEED_MASK 0x000f0000 1067 #define PORT_FEATURE_LINK_SPEED_SHIFT 16 1068 #define PORT_FEATURE_LINK_SPEED_AUTO 0x00000000 1069 #define PORT_FEATURE_LINK_SPEED_10M_FULL 0x00010000 1070 #define PORT_FEATURE_LINK_SPEED_10M_HALF 0x00020000 1071 #define PORT_FEATURE_LINK_SPEED_100M_HALF 0x00030000 1072 #define PORT_FEATURE_LINK_SPEED_100M_FULL 0x00040000 1073 #define PORT_FEATURE_LINK_SPEED_1G 0x00050000 1074 #define PORT_FEATURE_LINK_SPEED_2_5G 0x00060000 1075 #define PORT_FEATURE_LINK_SPEED_10G_CX4 0x00070000 1076 #define PORT_FEATURE_LINK_SPEED_20G 0x00080000 1077 1078 #define PORT_FEATURE_FLOW_CONTROL_MASK 0x00000700 1079 #define PORT_FEATURE_FLOW_CONTROL_SHIFT 8 1080 #define PORT_FEATURE_FLOW_CONTROL_AUTO 0x00000000 1081 #define PORT_FEATURE_FLOW_CONTROL_TX 0x00000100 1082 #define PORT_FEATURE_FLOW_CONTROL_RX 0x00000200 1083 #define PORT_FEATURE_FLOW_CONTROL_BOTH 0x00000300 1084 #define PORT_FEATURE_FLOW_CONTROL_NONE 0x00000400 1085 1086 /* The default for MCP link configuration, 1087 uses the same defines as link_config */ 1088 u32 mfw_wol_link_cfg; 1089 1090 /* The default for the driver of the second external phy, 1091 uses the same defines as link_config */ 1092 u32 link_config2; /* 0x47C */ 1093 1094 /* The default for MCP of the second external phy, 1095 uses the same defines as link_config */ 1096 u32 mfw_wol_link_cfg2; /* 0x480 */ 1097 1098 1099 /* EEE power saving mode */ 1100 u32 eee_power_mode; /* 0x484 */ 1101 #define PORT_FEAT_CFG_EEE_POWER_MODE_MASK 0x000000FF 1102 #define PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT 0 1103 #define PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED 0x00000000 1104 #define PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED 0x00000001 1105 #define PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE 0x00000002 1106 #define PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY 0x00000003 1107 1108 1109 u32 Reserved2[16]; /* 0x488 */ 1110 }; 1111 1112 1113 /**************************************************************************** 1114 * Device Information * 1115 ****************************************************************************/ 1116 struct shm_dev_info { /* size */ 1117 1118 u32 bc_rev; /* 8 bits each: major, minor, build */ /* 4 */ 1119 1120 struct shared_hw_cfg shared_hw_config; /* 40 */ 1121 1122 struct port_hw_cfg port_hw_config[PORT_MAX]; /* 400*2=800 */ 1123 1124 struct shared_feat_cfg shared_feature_config; /* 4 */ 1125 1126 struct port_feat_cfg port_feature_config[PORT_MAX];/* 116*2=232 */ 1127 1128 }; 1129 1130 1131 #if !defined(__LITTLE_ENDIAN) && !defined(__BIG_ENDIAN) 1132 #error "Missing either LITTLE_ENDIAN or BIG_ENDIAN definition." 1133 #endif 1134 1135 #define FUNC_0 0 1136 #define FUNC_1 1 1137 #define FUNC_2 2 1138 #define FUNC_3 3 1139 #define FUNC_4 4 1140 #define FUNC_5 5 1141 #define FUNC_6 6 1142 #define FUNC_7 7 1143 #define E1_FUNC_MAX 2 1144 #define E1H_FUNC_MAX 8 1145 #define E2_FUNC_MAX 4 /* per path */ 1146 1147 #define VN_0 0 1148 #define VN_1 1 1149 #define VN_2 2 1150 #define VN_3 3 1151 #define E1VN_MAX 1 1152 #define E1HVN_MAX 4 1153 1154 #define E2_VF_MAX 64 /* HC_REG_VF_CONFIGURATION_SIZE */ 1155 /* This value (in milliseconds) determines the frequency of the driver 1156 * issuing the PULSE message code. The firmware monitors this periodic 1157 * pulse to determine when to switch to an OS-absent mode. */ 1158 #define DRV_PULSE_PERIOD_MS 250 1159 1160 /* This value (in milliseconds) determines how long the driver should 1161 * wait for an acknowledgement from the firmware before timing out. Once 1162 * the firmware has timed out, the driver will assume there is no firmware 1163 * running and there won't be any firmware-driver synchronization during a 1164 * driver reset. */ 1165 #define FW_ACK_TIME_OUT_MS 5000 1166 1167 #define FW_ACK_POLL_TIME_MS 1 1168 1169 #define FW_ACK_NUM_OF_POLL (FW_ACK_TIME_OUT_MS/FW_ACK_POLL_TIME_MS) 1170 1171 #define MFW_TRACE_SIGNATURE 0x54524342 1172 1173 /**************************************************************************** 1174 * Driver <-> FW Mailbox * 1175 ****************************************************************************/ 1176 struct drv_port_mb { 1177 1178 u32 link_status; 1179 /* Driver should update this field on any link change event */ 1180 1181 #define LINK_STATUS_NONE (0<<0) 1182 #define LINK_STATUS_LINK_FLAG_MASK 0x00000001 1183 #define LINK_STATUS_LINK_UP 0x00000001 1184 #define LINK_STATUS_SPEED_AND_DUPLEX_MASK 0x0000001E 1185 #define LINK_STATUS_SPEED_AND_DUPLEX_AN_NOT_COMPLETE (0<<1) 1186 #define LINK_STATUS_SPEED_AND_DUPLEX_10THD (1<<1) 1187 #define LINK_STATUS_SPEED_AND_DUPLEX_10TFD (2<<1) 1188 #define LINK_STATUS_SPEED_AND_DUPLEX_100TXHD (3<<1) 1189 #define LINK_STATUS_SPEED_AND_DUPLEX_100T4 (4<<1) 1190 #define LINK_STATUS_SPEED_AND_DUPLEX_100TXFD (5<<1) 1191 #define LINK_STATUS_SPEED_AND_DUPLEX_1000THD (6<<1) 1192 #define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD (7<<1) 1193 #define LINK_STATUS_SPEED_AND_DUPLEX_1000XFD (7<<1) 1194 #define LINK_STATUS_SPEED_AND_DUPLEX_2500THD (8<<1) 1195 #define LINK_STATUS_SPEED_AND_DUPLEX_2500TFD (9<<1) 1196 #define LINK_STATUS_SPEED_AND_DUPLEX_2500XFD (9<<1) 1197 #define LINK_STATUS_SPEED_AND_DUPLEX_10GTFD (10<<1) 1198 #define LINK_STATUS_SPEED_AND_DUPLEX_10GXFD (10<<1) 1199 #define LINK_STATUS_SPEED_AND_DUPLEX_20GTFD (11<<1) 1200 #define LINK_STATUS_SPEED_AND_DUPLEX_20GXFD (11<<1) 1201 1202 #define LINK_STATUS_AUTO_NEGOTIATE_FLAG_MASK 0x00000020 1203 #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED 0x00000020 1204 1205 #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE 0x00000040 1206 #define LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK 0x00000080 1207 #define LINK_STATUS_PARALLEL_DETECTION_USED 0x00000080 1208 1209 #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200 1210 #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400 1211 #define LINK_STATUS_LINK_PARTNER_100T4_CAPABLE 0x00000800 1212 #define LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE 0x00001000 1213 #define LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE 0x00002000 1214 #define LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE 0x00004000 1215 #define LINK_STATUS_LINK_PARTNER_10THD_CAPABLE 0x00008000 1216 1217 #define LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK 0x00010000 1218 #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED 0x00010000 1219 1220 #define LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK 0x00020000 1221 #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED 0x00020000 1222 1223 #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK 0x000C0000 1224 #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE (0<<18) 1225 #define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE (1<<18) 1226 #define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE (2<<18) 1227 #define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE (3<<18) 1228 1229 #define LINK_STATUS_SERDES_LINK 0x00100000 1230 1231 #define LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE 0x00200000 1232 #define LINK_STATUS_LINK_PARTNER_2500XHD_CAPABLE 0x00400000 1233 #define LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE 0x00800000 1234 #define LINK_STATUS_LINK_PARTNER_20GXFD_CAPABLE 0x10000000 1235 1236 #define LINK_STATUS_PFC_ENABLED 0x20000000 1237 1238 #define LINK_STATUS_PHYSICAL_LINK_FLAG 0x40000000 1239 #define LINK_STATUS_SFP_TX_FAULT 0x80000000 1240 1241 u32 port_stx; 1242 1243 u32 stat_nig_timer; 1244 1245 /* MCP firmware does not use this field */ 1246 u32 ext_phy_fw_version; 1247 1248 }; 1249 1250 1251 struct drv_func_mb { 1252 1253 u32 drv_mb_header; 1254 #define DRV_MSG_CODE_MASK 0xffff0000 1255 #define DRV_MSG_CODE_LOAD_REQ 0x10000000 1256 #define DRV_MSG_CODE_LOAD_DONE 0x11000000 1257 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_EN 0x20000000 1258 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS 0x20010000 1259 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP 0x20020000 1260 #define DRV_MSG_CODE_UNLOAD_DONE 0x21000000 1261 #define DRV_MSG_CODE_DCC_OK 0x30000000 1262 #define DRV_MSG_CODE_DCC_FAILURE 0x31000000 1263 #define DRV_MSG_CODE_DIAG_ENTER_REQ 0x50000000 1264 #define DRV_MSG_CODE_DIAG_EXIT_REQ 0x60000000 1265 #define DRV_MSG_CODE_VALIDATE_KEY 0x70000000 1266 #define DRV_MSG_CODE_GET_CURR_KEY 0x80000000 1267 #define DRV_MSG_CODE_GET_UPGRADE_KEY 0x81000000 1268 #define DRV_MSG_CODE_GET_MANUF_KEY 0x82000000 1269 #define DRV_MSG_CODE_LOAD_L2B_PRAM 0x90000000 1270 /* 1271 * The optic module verification command requires bootcode 1272 * v5.0.6 or later, te specific optic module verification command 1273 * requires bootcode v5.2.12 or later 1274 */ 1275 #define DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL 0xa0000000 1276 #define REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL 0x00050006 1277 #define DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL 0xa1000000 1278 #define REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL 0x00050234 1279 #define DRV_MSG_CODE_VRFY_AFEX_SUPPORTED 0xa2000000 1280 #define REQ_BC_VER_4_VRFY_AFEX_SUPPORTED 0x00070002 1281 #define REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED 0x00070014 1282 #define REQ_BC_VER_4_MT_SUPPORTED 0x00070201 1283 #define REQ_BC_VER_4_PFC_STATS_SUPPORTED 0x00070201 1284 #define REQ_BC_VER_4_FCOE_FEATURES 0x00070209 1285 1286 #define DRV_MSG_CODE_DCBX_ADMIN_PMF_MSG 0xb0000000 1287 #define DRV_MSG_CODE_DCBX_PMF_DRV_OK 0xb2000000 1288 #define REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF 0x00070401 1289 1290 #define DRV_MSG_CODE_VF_DISABLED_DONE 0xc0000000 1291 1292 #define DRV_MSG_CODE_AFEX_DRIVER_SETMAC 0xd0000000 1293 #define DRV_MSG_CODE_AFEX_LISTGET_ACK 0xd1000000 1294 #define DRV_MSG_CODE_AFEX_LISTSET_ACK 0xd2000000 1295 #define DRV_MSG_CODE_AFEX_STATSGET_ACK 0xd3000000 1296 #define DRV_MSG_CODE_AFEX_VIFSET_ACK 0xd4000000 1297 1298 #define DRV_MSG_CODE_DRV_INFO_ACK 0xd8000000 1299 #define DRV_MSG_CODE_DRV_INFO_NACK 0xd9000000 1300 1301 #define DRV_MSG_CODE_EEE_RESULTS_ACK 0xda000000 1302 1303 #define DRV_MSG_CODE_RMMOD 0xdb000000 1304 #define REQ_BC_VER_4_RMMOD_CMD 0x0007080f 1305 1306 #define DRV_MSG_CODE_SET_MF_BW 0xe0000000 1307 #define REQ_BC_VER_4_SET_MF_BW 0x00060202 1308 #define DRV_MSG_CODE_SET_MF_BW_ACK 0xe1000000 1309 1310 #define DRV_MSG_CODE_LINK_STATUS_CHANGED 0x01000000 1311 1312 #define DRV_MSG_CODE_INITIATE_FLR 0x02000000 1313 #define REQ_BC_VER_4_INITIATE_FLR 0x00070213 1314 1315 #define BIOS_MSG_CODE_LIC_CHALLENGE 0xff010000 1316 #define BIOS_MSG_CODE_LIC_RESPONSE 0xff020000 1317 #define BIOS_MSG_CODE_VIRT_MAC_PRIM 0xff030000 1318 #define BIOS_MSG_CODE_VIRT_MAC_ISCSI 0xff040000 1319 1320 #define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff 1321 1322 u32 drv_mb_param; 1323 #define DRV_MSG_CODE_SET_MF_BW_MIN_MASK 0x00ff0000 1324 #define DRV_MSG_CODE_SET_MF_BW_MAX_MASK 0xff000000 1325 1326 #define DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET 0x00000002 1327 1328 #define DRV_MSG_CODE_LOAD_REQ_WITH_LFA 0x0000100a 1329 #define DRV_MSG_CODE_LOAD_REQ_FORCE_LFA 0x00002000 1330 1331 u32 fw_mb_header; 1332 #define FW_MSG_CODE_MASK 0xffff0000 1333 #define FW_MSG_CODE_DRV_LOAD_COMMON 0x10100000 1334 #define FW_MSG_CODE_DRV_LOAD_PORT 0x10110000 1335 #define FW_MSG_CODE_DRV_LOAD_FUNCTION 0x10120000 1336 /* Load common chip is supported from bc 6.0.0 */ 1337 #define REQ_BC_VER_4_DRV_LOAD_COMMON_CHIP 0x00060000 1338 #define FW_MSG_CODE_DRV_LOAD_COMMON_CHIP 0x10130000 1339 1340 #define FW_MSG_CODE_DRV_LOAD_REFUSED 0x10200000 1341 #define FW_MSG_CODE_DRV_LOAD_DONE 0x11100000 1342 #define FW_MSG_CODE_DRV_UNLOAD_COMMON 0x20100000 1343 #define FW_MSG_CODE_DRV_UNLOAD_PORT 0x20110000 1344 #define FW_MSG_CODE_DRV_UNLOAD_FUNCTION 0x20120000 1345 #define FW_MSG_CODE_DRV_UNLOAD_DONE 0x21100000 1346 #define FW_MSG_CODE_DCC_DONE 0x30100000 1347 #define FW_MSG_CODE_LLDP_DONE 0x40100000 1348 #define FW_MSG_CODE_DIAG_ENTER_DONE 0x50100000 1349 #define FW_MSG_CODE_DIAG_REFUSE 0x50200000 1350 #define FW_MSG_CODE_DIAG_EXIT_DONE 0x60100000 1351 #define FW_MSG_CODE_VALIDATE_KEY_SUCCESS 0x70100000 1352 #define FW_MSG_CODE_VALIDATE_KEY_FAILURE 0x70200000 1353 #define FW_MSG_CODE_GET_KEY_DONE 0x80100000 1354 #define FW_MSG_CODE_NO_KEY 0x80f00000 1355 #define FW_MSG_CODE_LIC_INFO_NOT_READY 0x80f80000 1356 #define FW_MSG_CODE_L2B_PRAM_LOADED 0x90100000 1357 #define FW_MSG_CODE_L2B_PRAM_T_LOAD_FAILURE 0x90210000 1358 #define FW_MSG_CODE_L2B_PRAM_C_LOAD_FAILURE 0x90220000 1359 #define FW_MSG_CODE_L2B_PRAM_X_LOAD_FAILURE 0x90230000 1360 #define FW_MSG_CODE_L2B_PRAM_U_LOAD_FAILURE 0x90240000 1361 #define FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS 0xa0100000 1362 #define FW_MSG_CODE_VRFY_OPT_MDL_INVLD_IMG 0xa0200000 1363 #define FW_MSG_CODE_VRFY_OPT_MDL_UNAPPROVED 0xa0300000 1364 #define FW_MSG_CODE_VF_DISABLED_DONE 0xb0000000 1365 #define FW_MSG_CODE_HW_SET_INVALID_IMAGE 0xb0100000 1366 1367 #define FW_MSG_CODE_AFEX_DRIVER_SETMAC_DONE 0xd0100000 1368 #define FW_MSG_CODE_AFEX_LISTGET_ACK 0xd1100000 1369 #define FW_MSG_CODE_AFEX_LISTSET_ACK 0xd2100000 1370 #define FW_MSG_CODE_AFEX_STATSGET_ACK 0xd3100000 1371 #define FW_MSG_CODE_AFEX_VIFSET_ACK 0xd4100000 1372 1373 #define FW_MSG_CODE_DRV_INFO_ACK 0xd8100000 1374 #define FW_MSG_CODE_DRV_INFO_NACK 0xd9100000 1375 1376 #define FW_MSG_CODE_EEE_RESULS_ACK 0xda100000 1377 1378 #define FW_MSG_CODE_RMMOD_ACK 0xdb100000 1379 1380 #define FW_MSG_CODE_SET_MF_BW_SENT 0xe0000000 1381 #define FW_MSG_CODE_SET_MF_BW_DONE 0xe1000000 1382 1383 #define FW_MSG_CODE_LINK_CHANGED_ACK 0x01100000 1384 1385 #define FW_MSG_CODE_LIC_CHALLENGE 0xff010000 1386 #define FW_MSG_CODE_LIC_RESPONSE 0xff020000 1387 #define FW_MSG_CODE_VIRT_MAC_PRIM 0xff030000 1388 #define FW_MSG_CODE_VIRT_MAC_ISCSI 0xff040000 1389 1390 #define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff 1391 1392 u32 fw_mb_param; 1393 1394 u32 drv_pulse_mb; 1395 #define DRV_PULSE_SEQ_MASK 0x00007fff 1396 #define DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000 1397 /* 1398 * The system time is in the format of 1399 * (year-2001)*12*32 + month*32 + day. 1400 */ 1401 #define DRV_PULSE_ALWAYS_ALIVE 0x00008000 1402 /* 1403 * Indicate to the firmware not to go into the 1404 * OS-absent when it is not getting driver pulse. 1405 * This is used for debugging as well for PXE(MBA). 1406 */ 1407 1408 u32 mcp_pulse_mb; 1409 #define MCP_PULSE_SEQ_MASK 0x00007fff 1410 #define MCP_PULSE_ALWAYS_ALIVE 0x00008000 1411 /* Indicates to the driver not to assert due to lack 1412 * of MCP response */ 1413 #define MCP_EVENT_MASK 0xffff0000 1414 #define MCP_EVENT_OTHER_DRIVER_RESET_REQ 0x00010000 1415 1416 u32 iscsi_boot_signature; 1417 u32 iscsi_boot_block_offset; 1418 1419 u32 drv_status; 1420 #define DRV_STATUS_PMF 0x00000001 1421 #define DRV_STATUS_VF_DISABLED 0x00000002 1422 #define DRV_STATUS_SET_MF_BW 0x00000004 1423 #define DRV_STATUS_LINK_EVENT 0x00000008 1424 1425 #define DRV_STATUS_DCC_EVENT_MASK 0x0000ff00 1426 #define DRV_STATUS_DCC_DISABLE_ENABLE_PF 0x00000100 1427 #define DRV_STATUS_DCC_BANDWIDTH_ALLOCATION 0x00000200 1428 #define DRV_STATUS_DCC_CHANGE_MAC_ADDRESS 0x00000400 1429 #define DRV_STATUS_DCC_RESERVED1 0x00000800 1430 #define DRV_STATUS_DCC_SET_PROTOCOL 0x00001000 1431 #define DRV_STATUS_DCC_SET_PRIORITY 0x00002000 1432 1433 #define DRV_STATUS_DCBX_EVENT_MASK 0x000f0000 1434 #define DRV_STATUS_DCBX_NEGOTIATION_RESULTS 0x00010000 1435 #define DRV_STATUS_AFEX_EVENT_MASK 0x03f00000 1436 #define DRV_STATUS_AFEX_LISTGET_REQ 0x00100000 1437 #define DRV_STATUS_AFEX_LISTSET_REQ 0x00200000 1438 #define DRV_STATUS_AFEX_STATSGET_REQ 0x00400000 1439 #define DRV_STATUS_AFEX_VIFSET_REQ 0x00800000 1440 1441 #define DRV_STATUS_DRV_INFO_REQ 0x04000000 1442 1443 #define DRV_STATUS_EEE_NEGOTIATION_RESULTS 0x08000000 1444 1445 u32 virt_mac_upper; 1446 #define VIRT_MAC_SIGN_MASK 0xffff0000 1447 #define VIRT_MAC_SIGNATURE 0x564d0000 1448 u32 virt_mac_lower; 1449 1450 }; 1451 1452 1453 /**************************************************************************** 1454 * Management firmware state * 1455 ****************************************************************************/ 1456 /* Allocate 440 bytes for management firmware */ 1457 #define MGMTFW_STATE_WORD_SIZE 110 1458 1459 struct mgmtfw_state { 1460 u32 opaque[MGMTFW_STATE_WORD_SIZE]; 1461 }; 1462 1463 1464 /**************************************************************************** 1465 * Multi-Function configuration * 1466 ****************************************************************************/ 1467 struct shared_mf_cfg { 1468 1469 u32 clp_mb; 1470 #define SHARED_MF_CLP_SET_DEFAULT 0x00000000 1471 /* set by CLP */ 1472 #define SHARED_MF_CLP_EXIT 0x00000001 1473 /* set by MCP */ 1474 #define SHARED_MF_CLP_EXIT_DONE 0x00010000 1475 1476 }; 1477 1478 struct port_mf_cfg { 1479 1480 u32 dynamic_cfg; /* device control channel */ 1481 #define PORT_MF_CFG_E1HOV_TAG_MASK 0x0000ffff 1482 #define PORT_MF_CFG_E1HOV_TAG_SHIFT 0 1483 #define PORT_MF_CFG_E1HOV_TAG_DEFAULT PORT_MF_CFG_E1HOV_TAG_MASK 1484 1485 u32 reserved[1]; 1486 1487 }; 1488 1489 struct func_mf_cfg { 1490 1491 u32 config; 1492 /* E/R/I/D */ 1493 /* function 0 of each port cannot be hidden */ 1494 #define FUNC_MF_CFG_FUNC_HIDE 0x00000001 1495 1496 #define FUNC_MF_CFG_PROTOCOL_MASK 0x00000006 1497 #define FUNC_MF_CFG_PROTOCOL_FCOE 0x00000000 1498 #define FUNC_MF_CFG_PROTOCOL_ETHERNET 0x00000002 1499 #define FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA 0x00000004 1500 #define FUNC_MF_CFG_PROTOCOL_ISCSI 0x00000006 1501 #define FUNC_MF_CFG_PROTOCOL_DEFAULT \ 1502 FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA 1503 1504 #define FUNC_MF_CFG_FUNC_DISABLED 0x00000008 1505 #define FUNC_MF_CFG_FUNC_DELETED 0x00000010 1506 1507 /* PRI */ 1508 /* 0 - low priority, 3 - high priority */ 1509 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK 0x00000300 1510 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT 8 1511 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_DEFAULT 0x00000000 1512 1513 /* MINBW, MAXBW */ 1514 /* value range - 0..100, increments in 100Mbps */ 1515 #define FUNC_MF_CFG_MIN_BW_MASK 0x00ff0000 1516 #define FUNC_MF_CFG_MIN_BW_SHIFT 16 1517 #define FUNC_MF_CFG_MIN_BW_DEFAULT 0x00000000 1518 #define FUNC_MF_CFG_MAX_BW_MASK 0xff000000 1519 #define FUNC_MF_CFG_MAX_BW_SHIFT 24 1520 #define FUNC_MF_CFG_MAX_BW_DEFAULT 0x64000000 1521 1522 u32 mac_upper; /* MAC */ 1523 #define FUNC_MF_CFG_UPPERMAC_MASK 0x0000ffff 1524 #define FUNC_MF_CFG_UPPERMAC_SHIFT 0 1525 #define FUNC_MF_CFG_UPPERMAC_DEFAULT FUNC_MF_CFG_UPPERMAC_MASK 1526 u32 mac_lower; 1527 #define FUNC_MF_CFG_LOWERMAC_DEFAULT 0xffffffff 1528 1529 u32 e1hov_tag; /* VNI */ 1530 #define FUNC_MF_CFG_E1HOV_TAG_MASK 0x0000ffff 1531 #define FUNC_MF_CFG_E1HOV_TAG_SHIFT 0 1532 #define FUNC_MF_CFG_E1HOV_TAG_DEFAULT FUNC_MF_CFG_E1HOV_TAG_MASK 1533 1534 /* afex default VLAN ID - 12 bits */ 1535 #define FUNC_MF_CFG_AFEX_VLAN_MASK 0x0fff0000 1536 #define FUNC_MF_CFG_AFEX_VLAN_SHIFT 16 1537 1538 u32 afex_config; 1539 #define FUNC_MF_CFG_AFEX_COS_FILTER_MASK 0x000000ff 1540 #define FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT 0 1541 #define FUNC_MF_CFG_AFEX_MBA_ENABLED_MASK 0x0000ff00 1542 #define FUNC_MF_CFG_AFEX_MBA_ENABLED_SHIFT 8 1543 #define FUNC_MF_CFG_AFEX_MBA_ENABLED_VAL 0x00000100 1544 #define FUNC_MF_CFG_AFEX_VLAN_MODE_MASK 0x000f0000 1545 #define FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT 16 1546 1547 u32 reserved; 1548 }; 1549 1550 enum mf_cfg_afex_vlan_mode { 1551 FUNC_MF_CFG_AFEX_VLAN_TRUNK_MODE = 0, 1552 FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE, 1553 FUNC_MF_CFG_AFEX_VLAN_TRUNK_TAG_NATIVE_MODE 1554 }; 1555 1556 /* This structure is not applicable and should not be accessed on 57711 */ 1557 struct func_ext_cfg { 1558 u32 func_cfg; 1559 #define MACP_FUNC_CFG_FLAGS_MASK 0x0000007F 1560 #define MACP_FUNC_CFG_FLAGS_SHIFT 0 1561 #define MACP_FUNC_CFG_FLAGS_ENABLED 0x00000001 1562 #define MACP_FUNC_CFG_FLAGS_ETHERNET 0x00000002 1563 #define MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD 0x00000004 1564 #define MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD 0x00000008 1565 #define MACP_FUNC_CFG_PAUSE_ON_HOST_RING 0x00000080 1566 1567 u32 iscsi_mac_addr_upper; 1568 u32 iscsi_mac_addr_lower; 1569 1570 u32 fcoe_mac_addr_upper; 1571 u32 fcoe_mac_addr_lower; 1572 1573 u32 fcoe_wwn_port_name_upper; 1574 u32 fcoe_wwn_port_name_lower; 1575 1576 u32 fcoe_wwn_node_name_upper; 1577 u32 fcoe_wwn_node_name_lower; 1578 1579 u32 preserve_data; 1580 #define MF_FUNC_CFG_PRESERVE_L2_MAC (1<<0) 1581 #define MF_FUNC_CFG_PRESERVE_ISCSI_MAC (1<<1) 1582 #define MF_FUNC_CFG_PRESERVE_FCOE_MAC (1<<2) 1583 #define MF_FUNC_CFG_PRESERVE_FCOE_WWN_P (1<<3) 1584 #define MF_FUNC_CFG_PRESERVE_FCOE_WWN_N (1<<4) 1585 #define MF_FUNC_CFG_PRESERVE_TX_BW (1<<5) 1586 }; 1587 1588 struct mf_cfg { 1589 1590 struct shared_mf_cfg shared_mf_config; /* 0x4 */ 1591 /* 0x8*2*2=0x20 */ 1592 struct port_mf_cfg port_mf_config[NVM_PATH_MAX][PORT_MAX]; 1593 /* for all chips, there are 8 mf functions */ 1594 struct func_mf_cfg func_mf_config[E1H_FUNC_MAX]; /* 0x18 * 8 = 0xc0 */ 1595 /* 1596 * Extended configuration per function - this array does not exist and 1597 * should not be accessed on 57711 1598 */ 1599 struct func_ext_cfg func_ext_config[E1H_FUNC_MAX]; /* 0x28 * 8 = 0x140*/ 1600 }; /* 0x224 */ 1601 1602 /**************************************************************************** 1603 * Shared Memory Region * 1604 ****************************************************************************/ 1605 struct shmem_region { /* SharedMem Offset (size) */ 1606 1607 u32 validity_map[PORT_MAX]; /* 0x0 (4*2 = 0x8) */ 1608 #define SHR_MEM_FORMAT_REV_MASK 0xff000000 1609 #define SHR_MEM_FORMAT_REV_ID ('A'<<24) 1610 /* validity bits */ 1611 #define SHR_MEM_VALIDITY_PCI_CFG 0x00100000 1612 #define SHR_MEM_VALIDITY_MB 0x00200000 1613 #define SHR_MEM_VALIDITY_DEV_INFO 0x00400000 1614 #define SHR_MEM_VALIDITY_RESERVED 0x00000007 1615 /* One licensing bit should be set */ 1616 #define SHR_MEM_VALIDITY_LIC_KEY_IN_EFFECT_MASK 0x00000038 1617 #define SHR_MEM_VALIDITY_LIC_MANUF_KEY_IN_EFFECT 0x00000008 1618 #define SHR_MEM_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT 0x00000010 1619 #define SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT 0x00000020 1620 /* Active MFW */ 1621 #define SHR_MEM_VALIDITY_ACTIVE_MFW_UNKNOWN 0x00000000 1622 #define SHR_MEM_VALIDITY_ACTIVE_MFW_MASK 0x000001c0 1623 #define SHR_MEM_VALIDITY_ACTIVE_MFW_IPMI 0x00000040 1624 #define SHR_MEM_VALIDITY_ACTIVE_MFW_UMP 0x00000080 1625 #define SHR_MEM_VALIDITY_ACTIVE_MFW_NCSI 0x000000c0 1626 #define SHR_MEM_VALIDITY_ACTIVE_MFW_NONE 0x000001c0 1627 1628 struct shm_dev_info dev_info; /* 0x8 (0x438) */ 1629 1630 struct license_key drv_lic_key[PORT_MAX]; /* 0x440 (52*2=0x68) */ 1631 1632 /* FW information (for internal FW use) */ 1633 u32 fw_info_fio_offset; /* 0x4a8 (0x4) */ 1634 struct mgmtfw_state mgmtfw_state; /* 0x4ac (0x1b8) */ 1635 1636 struct drv_port_mb port_mb[PORT_MAX]; /* 0x664 (16*2=0x20) */ 1637 1638 #ifdef BMAPI 1639 /* This is a variable length array */ 1640 /* the number of function depends on the chip type */ 1641 struct drv_func_mb func_mb[1]; /* 0x684 (44*2/4/8=0x58/0xb0/0x160) */ 1642 #else 1643 /* the number of function depends on the chip type */ 1644 struct drv_func_mb func_mb[]; /* 0x684 (44*2/4/8=0x58/0xb0/0x160) */ 1645 #endif /* BMAPI */ 1646 1647 }; /* 57710 = 0x6dc | 57711 = 0x7E4 | 57712 = 0x734 */ 1648 1649 /**************************************************************************** 1650 * Shared Memory 2 Region * 1651 ****************************************************************************/ 1652 /* The fw_flr_ack is actually built in the following way: */ 1653 /* 8 bit: PF ack */ 1654 /* 64 bit: VF ack */ 1655 /* 8 bit: ios_dis_ack */ 1656 /* In order to maintain endianity in the mailbox hsi, we want to keep using */ 1657 /* u32. The fw must have the VF right after the PF since this is how it */ 1658 /* access arrays(it expects always the VF to reside after the PF, and that */ 1659 /* makes the calculation much easier for it. ) */ 1660 /* In order to answer both limitations, and keep the struct small, the code */ 1661 /* will abuse the structure defined here to achieve the actual partition */ 1662 /* above */ 1663 /****************************************************************************/ 1664 struct fw_flr_ack { 1665 u32 pf_ack; 1666 u32 vf_ack[1]; 1667 u32 iov_dis_ack; 1668 }; 1669 1670 struct fw_flr_mb { 1671 u32 aggint; 1672 u32 opgen_addr; 1673 struct fw_flr_ack ack; 1674 }; 1675 1676 struct eee_remote_vals { 1677 u32 tx_tw; 1678 u32 rx_tw; 1679 }; 1680 1681 /**** SUPPORT FOR SHMEM ARRRAYS *** 1682 * The SHMEM HSI is aligned on 32 bit boundaries which makes it difficult to 1683 * define arrays with storage types smaller then unsigned dwords. 1684 * The macros below add generic support for SHMEM arrays with numeric elements 1685 * that can span 2,4,8 or 16 bits. The array underlying type is a 32 bit dword 1686 * array with individual bit-filed elements accessed using shifts and masks. 1687 * 1688 */ 1689 1690 /* eb is the bitwidth of a single element */ 1691 #define SHMEM_ARRAY_MASK(eb) ((1<<(eb))-1) 1692 #define SHMEM_ARRAY_ENTRY(i, eb) ((i)/(32/(eb))) 1693 1694 /* the bit-position macro allows the used to flip the order of the arrays 1695 * elements on a per byte or word boundary. 1696 * 1697 * example: an array with 8 entries each 4 bit wide. This array will fit into 1698 * a single dword. The diagrmas below show the array order of the nibbles. 1699 * 1700 * SHMEM_ARRAY_BITPOS(i, 4, 4) defines the stadard ordering: 1701 * 1702 * | | | | 1703 * 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 1704 * | | | | 1705 * 1706 * SHMEM_ARRAY_BITPOS(i, 4, 8) defines a flip ordering per byte: 1707 * 1708 * | | | | 1709 * 1 | 0 | 3 | 2 | 5 | 4 | 7 | 6 | 1710 * | | | | 1711 * 1712 * SHMEM_ARRAY_BITPOS(i, 4, 16) defines a flip ordering per word: 1713 * 1714 * | | | | 1715 * 3 | 2 | 1 | 0 | 7 | 6 | 5 | 4 | 1716 * | | | | 1717 */ 1718 #define SHMEM_ARRAY_BITPOS(i, eb, fb) \ 1719 ((((32/(fb)) - 1 - ((i)/((fb)/(eb))) % (32/(fb))) * (fb)) + \ 1720 (((i)%((fb)/(eb))) * (eb))) 1721 1722 #define SHMEM_ARRAY_GET(a, i, eb, fb) \ 1723 ((a[SHMEM_ARRAY_ENTRY(i, eb)] >> SHMEM_ARRAY_BITPOS(i, eb, fb)) & \ 1724 SHMEM_ARRAY_MASK(eb)) 1725 1726 #define SHMEM_ARRAY_SET(a, i, eb, fb, val) \ 1727 do { \ 1728 a[SHMEM_ARRAY_ENTRY(i, eb)] &= ~(SHMEM_ARRAY_MASK(eb) << \ 1729 SHMEM_ARRAY_BITPOS(i, eb, fb)); \ 1730 a[SHMEM_ARRAY_ENTRY(i, eb)] |= (((val) & SHMEM_ARRAY_MASK(eb)) << \ 1731 SHMEM_ARRAY_BITPOS(i, eb, fb)); \ 1732 } while (0) 1733 1734 1735 /****START OF DCBX STRUCTURES DECLARATIONS****/ 1736 #define DCBX_MAX_NUM_PRI_PG_ENTRIES 8 1737 #define DCBX_PRI_PG_BITWIDTH 4 1738 #define DCBX_PRI_PG_FBITS 8 1739 #define DCBX_PRI_PG_GET(a, i) \ 1740 SHMEM_ARRAY_GET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS) 1741 #define DCBX_PRI_PG_SET(a, i, val) \ 1742 SHMEM_ARRAY_SET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS, val) 1743 #define DCBX_MAX_NUM_PG_BW_ENTRIES 8 1744 #define DCBX_BW_PG_BITWIDTH 8 1745 #define DCBX_PG_BW_GET(a, i) \ 1746 SHMEM_ARRAY_GET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH) 1747 #define DCBX_PG_BW_SET(a, i, val) \ 1748 SHMEM_ARRAY_SET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH, val) 1749 #define DCBX_STRICT_PRI_PG 15 1750 #define DCBX_MAX_APP_PROTOCOL 16 1751 #define FCOE_APP_IDX 0 1752 #define ISCSI_APP_IDX 1 1753 #define PREDEFINED_APP_IDX_MAX 2 1754 1755 1756 /* Big/Little endian have the same representation. */ 1757 struct dcbx_ets_feature { 1758 /* 1759 * For Admin MIB - is this feature supported by the 1760 * driver | For Local MIB - should this feature be enabled. 1761 */ 1762 u32 enabled; 1763 u32 pg_bw_tbl[2]; 1764 u32 pri_pg_tbl[1]; 1765 }; 1766 1767 /* Driver structure in LE */ 1768 struct dcbx_pfc_feature { 1769 #ifdef __BIG_ENDIAN 1770 u8 pri_en_bitmap; 1771 #define DCBX_PFC_PRI_0 0x01 1772 #define DCBX_PFC_PRI_1 0x02 1773 #define DCBX_PFC_PRI_2 0x04 1774 #define DCBX_PFC_PRI_3 0x08 1775 #define DCBX_PFC_PRI_4 0x10 1776 #define DCBX_PFC_PRI_5 0x20 1777 #define DCBX_PFC_PRI_6 0x40 1778 #define DCBX_PFC_PRI_7 0x80 1779 u8 pfc_caps; 1780 u8 reserved; 1781 u8 enabled; 1782 #elif defined(__LITTLE_ENDIAN) 1783 u8 enabled; 1784 u8 reserved; 1785 u8 pfc_caps; 1786 u8 pri_en_bitmap; 1787 #define DCBX_PFC_PRI_0 0x01 1788 #define DCBX_PFC_PRI_1 0x02 1789 #define DCBX_PFC_PRI_2 0x04 1790 #define DCBX_PFC_PRI_3 0x08 1791 #define DCBX_PFC_PRI_4 0x10 1792 #define DCBX_PFC_PRI_5 0x20 1793 #define DCBX_PFC_PRI_6 0x40 1794 #define DCBX_PFC_PRI_7 0x80 1795 #endif 1796 }; 1797 1798 struct dcbx_app_priority_entry { 1799 #ifdef __BIG_ENDIAN 1800 u16 app_id; 1801 u8 pri_bitmap; 1802 u8 appBitfield; 1803 #define DCBX_APP_ENTRY_VALID 0x01 1804 #define DCBX_APP_ENTRY_SF_MASK 0x30 1805 #define DCBX_APP_ENTRY_SF_SHIFT 4 1806 #define DCBX_APP_SF_ETH_TYPE 0x10 1807 #define DCBX_APP_SF_PORT 0x20 1808 #elif defined(__LITTLE_ENDIAN) 1809 u8 appBitfield; 1810 #define DCBX_APP_ENTRY_VALID 0x01 1811 #define DCBX_APP_ENTRY_SF_MASK 0x30 1812 #define DCBX_APP_ENTRY_SF_SHIFT 4 1813 #define DCBX_APP_SF_ETH_TYPE 0x10 1814 #define DCBX_APP_SF_PORT 0x20 1815 u8 pri_bitmap; 1816 u16 app_id; 1817 #endif 1818 }; 1819 1820 1821 /* FW structure in BE */ 1822 struct dcbx_app_priority_feature { 1823 #ifdef __BIG_ENDIAN 1824 u8 reserved; 1825 u8 default_pri; 1826 u8 tc_supported; 1827 u8 enabled; 1828 #elif defined(__LITTLE_ENDIAN) 1829 u8 enabled; 1830 u8 tc_supported; 1831 u8 default_pri; 1832 u8 reserved; 1833 #endif 1834 struct dcbx_app_priority_entry app_pri_tbl[DCBX_MAX_APP_PROTOCOL]; 1835 }; 1836 1837 /* FW structure in BE */ 1838 struct dcbx_features { 1839 /* PG feature */ 1840 struct dcbx_ets_feature ets; 1841 /* PFC feature */ 1842 struct dcbx_pfc_feature pfc; 1843 /* APP feature */ 1844 struct dcbx_app_priority_feature app; 1845 }; 1846 1847 /* LLDP protocol parameters */ 1848 /* FW structure in BE */ 1849 struct lldp_params { 1850 #ifdef __BIG_ENDIAN 1851 u8 msg_fast_tx_interval; 1852 u8 msg_tx_hold; 1853 u8 msg_tx_interval; 1854 u8 admin_status; 1855 #define LLDP_TX_ONLY 0x01 1856 #define LLDP_RX_ONLY 0x02 1857 #define LLDP_TX_RX 0x03 1858 #define LLDP_DISABLED 0x04 1859 u8 reserved1; 1860 u8 tx_fast; 1861 u8 tx_crd_max; 1862 u8 tx_crd; 1863 #elif defined(__LITTLE_ENDIAN) 1864 u8 admin_status; 1865 #define LLDP_TX_ONLY 0x01 1866 #define LLDP_RX_ONLY 0x02 1867 #define LLDP_TX_RX 0x03 1868 #define LLDP_DISABLED 0x04 1869 u8 msg_tx_interval; 1870 u8 msg_tx_hold; 1871 u8 msg_fast_tx_interval; 1872 u8 tx_crd; 1873 u8 tx_crd_max; 1874 u8 tx_fast; 1875 u8 reserved1; 1876 #endif 1877 #define REM_CHASSIS_ID_STAT_LEN 4 1878 #define REM_PORT_ID_STAT_LEN 4 1879 /* Holds remote Chassis ID TLV header, subtype and 9B of payload. */ 1880 u32 peer_chassis_id[REM_CHASSIS_ID_STAT_LEN]; 1881 /* Holds remote Port ID TLV header, subtype and 9B of payload. */ 1882 u32 peer_port_id[REM_PORT_ID_STAT_LEN]; 1883 }; 1884 1885 struct lldp_dcbx_stat { 1886 #define LOCAL_CHASSIS_ID_STAT_LEN 2 1887 #define LOCAL_PORT_ID_STAT_LEN 2 1888 /* Holds local Chassis ID 8B payload of constant subtype 4. */ 1889 u32 local_chassis_id[LOCAL_CHASSIS_ID_STAT_LEN]; 1890 /* Holds local Port ID 8B payload of constant subtype 3. */ 1891 u32 local_port_id[LOCAL_PORT_ID_STAT_LEN]; 1892 /* Number of DCBX frames transmitted. */ 1893 u32 num_tx_dcbx_pkts; 1894 /* Number of DCBX frames received. */ 1895 u32 num_rx_dcbx_pkts; 1896 }; 1897 1898 /* ADMIN MIB - DCBX local machine default configuration. */ 1899 struct lldp_admin_mib { 1900 u32 ver_cfg_flags; 1901 #define DCBX_ETS_CONFIG_TX_ENABLED 0x00000001 1902 #define DCBX_PFC_CONFIG_TX_ENABLED 0x00000002 1903 #define DCBX_APP_CONFIG_TX_ENABLED 0x00000004 1904 #define DCBX_ETS_RECO_TX_ENABLED 0x00000008 1905 #define DCBX_ETS_RECO_VALID 0x00000010 1906 #define DCBX_ETS_WILLING 0x00000020 1907 #define DCBX_PFC_WILLING 0x00000040 1908 #define DCBX_APP_WILLING 0x00000080 1909 #define DCBX_VERSION_CEE 0x00000100 1910 #define DCBX_VERSION_IEEE 0x00000200 1911 #define DCBX_DCBX_ENABLED 0x00000400 1912 #define DCBX_CEE_VERSION_MASK 0x0000f000 1913 #define DCBX_CEE_VERSION_SHIFT 12 1914 #define DCBX_CEE_MAX_VERSION_MASK 0x000f0000 1915 #define DCBX_CEE_MAX_VERSION_SHIFT 16 1916 struct dcbx_features features; 1917 }; 1918 1919 /* REMOTE MIB - remote machine DCBX configuration. */ 1920 struct lldp_remote_mib { 1921 u32 prefix_seq_num; 1922 u32 flags; 1923 #define DCBX_ETS_TLV_RX 0x00000001 1924 #define DCBX_PFC_TLV_RX 0x00000002 1925 #define DCBX_APP_TLV_RX 0x00000004 1926 #define DCBX_ETS_RX_ERROR 0x00000010 1927 #define DCBX_PFC_RX_ERROR 0x00000020 1928 #define DCBX_APP_RX_ERROR 0x00000040 1929 #define DCBX_ETS_REM_WILLING 0x00000100 1930 #define DCBX_PFC_REM_WILLING 0x00000200 1931 #define DCBX_APP_REM_WILLING 0x00000400 1932 #define DCBX_REMOTE_ETS_RECO_VALID 0x00001000 1933 #define DCBX_REMOTE_MIB_VALID 0x00002000 1934 struct dcbx_features features; 1935 u32 suffix_seq_num; 1936 }; 1937 1938 /* LOCAL MIB - operational DCBX configuration - transmitted on Tx LLDPDU. */ 1939 struct lldp_local_mib { 1940 u32 prefix_seq_num; 1941 /* Indicates if there is mismatch with negotiation results. */ 1942 u32 error; 1943 #define DCBX_LOCAL_ETS_ERROR 0x00000001 1944 #define DCBX_LOCAL_PFC_ERROR 0x00000002 1945 #define DCBX_LOCAL_APP_ERROR 0x00000004 1946 #define DCBX_LOCAL_PFC_MISMATCH 0x00000010 1947 #define DCBX_LOCAL_APP_MISMATCH 0x00000020 1948 #define DCBX_REMOTE_MIB_ERROR 0x00000040 1949 #define DCBX_REMOTE_ETS_TLV_NOT_FOUND 0x00000080 1950 #define DCBX_REMOTE_PFC_TLV_NOT_FOUND 0x00000100 1951 #define DCBX_REMOTE_APP_TLV_NOT_FOUND 0x00000200 1952 struct dcbx_features features; 1953 u32 suffix_seq_num; 1954 }; 1955 /***END OF DCBX STRUCTURES DECLARATIONS***/ 1956 1957 /***********************************************************/ 1958 /* Elink section */ 1959 /***********************************************************/ 1960 #define SHMEM_LINK_CONFIG_SIZE 2 1961 struct shmem_lfa { 1962 u32 req_duplex; 1963 #define REQ_DUPLEX_PHY0_MASK 0x0000ffff 1964 #define REQ_DUPLEX_PHY0_SHIFT 0 1965 #define REQ_DUPLEX_PHY1_MASK 0xffff0000 1966 #define REQ_DUPLEX_PHY1_SHIFT 16 1967 u32 req_flow_ctrl; 1968 #define REQ_FLOW_CTRL_PHY0_MASK 0x0000ffff 1969 #define REQ_FLOW_CTRL_PHY0_SHIFT 0 1970 #define REQ_FLOW_CTRL_PHY1_MASK 0xffff0000 1971 #define REQ_FLOW_CTRL_PHY1_SHIFT 16 1972 u32 req_line_speed; /* Also determine AutoNeg */ 1973 #define REQ_LINE_SPD_PHY0_MASK 0x0000ffff 1974 #define REQ_LINE_SPD_PHY0_SHIFT 0 1975 #define REQ_LINE_SPD_PHY1_MASK 0xffff0000 1976 #define REQ_LINE_SPD_PHY1_SHIFT 16 1977 u32 speed_cap_mask[SHMEM_LINK_CONFIG_SIZE]; 1978 u32 additional_config; 1979 #define REQ_FC_AUTO_ADV_MASK 0x0000ffff 1980 #define REQ_FC_AUTO_ADV0_SHIFT 0 1981 #define NO_LFA_DUE_TO_DCC_MASK 0x00010000 1982 u32 lfa_sts; 1983 #define LFA_LINK_FLAP_REASON_OFFSET 0 1984 #define LFA_LINK_FLAP_REASON_MASK 0x000000ff 1985 #define LFA_LINK_DOWN 0x1 1986 #define LFA_LOOPBACK_ENABLED 0x2 1987 #define LFA_DUPLEX_MISMATCH 0x3 1988 #define LFA_MFW_IS_TOO_OLD 0x4 1989 #define LFA_LINK_SPEED_MISMATCH 0x5 1990 #define LFA_FLOW_CTRL_MISMATCH 0x6 1991 #define LFA_SPEED_CAP_MISMATCH 0x7 1992 #define LFA_DCC_LFA_DISABLED 0x8 1993 #define LFA_EEE_MISMATCH 0x9 1994 1995 #define LINK_FLAP_AVOIDANCE_COUNT_OFFSET 8 1996 #define LINK_FLAP_AVOIDANCE_COUNT_MASK 0x0000ff00 1997 1998 #define LINK_FLAP_COUNT_OFFSET 16 1999 #define LINK_FLAP_COUNT_MASK 0x00ff0000 2000 2001 #define LFA_FLAGS_MASK 0xff000000 2002 #define SHMEM_LFA_DONT_CLEAR_STAT (1<<24) 2003 }; 2004 2005 struct ncsi_oem_fcoe_features { 2006 u32 fcoe_features1; 2007 #define FCOE_FEATURES1_IOS_PER_CONNECTION_MASK 0x0000FFFF 2008 #define FCOE_FEATURES1_IOS_PER_CONNECTION_OFFSET 0 2009 2010 #define FCOE_FEATURES1_LOGINS_PER_PORT_MASK 0xFFFF0000 2011 #define FCOE_FEATURES1_LOGINS_PER_PORT_OFFSET 16 2012 2013 u32 fcoe_features2; 2014 #define FCOE_FEATURES2_EXCHANGES_MASK 0x0000FFFF 2015 #define FCOE_FEATURES2_EXCHANGES_OFFSET 0 2016 2017 #define FCOE_FEATURES2_NPIV_WWN_PER_PORT_MASK 0xFFFF0000 2018 #define FCOE_FEATURES2_NPIV_WWN_PER_PORT_OFFSET 16 2019 2020 u32 fcoe_features3; 2021 #define FCOE_FEATURES3_TARGETS_SUPPORTED_MASK 0x0000FFFF 2022 #define FCOE_FEATURES3_TARGETS_SUPPORTED_OFFSET 0 2023 2024 #define FCOE_FEATURES3_OUTSTANDING_COMMANDS_MASK 0xFFFF0000 2025 #define FCOE_FEATURES3_OUTSTANDING_COMMANDS_OFFSET 16 2026 2027 u32 fcoe_features4; 2028 #define FCOE_FEATURES4_FEATURE_SETTINGS_MASK 0x0000000F 2029 #define FCOE_FEATURES4_FEATURE_SETTINGS_OFFSET 0 2030 }; 2031 2032 struct ncsi_oem_data { 2033 u32 driver_version[4]; 2034 struct ncsi_oem_fcoe_features ncsi_oem_fcoe_features; 2035 }; 2036 2037 struct shmem2_region { 2038 2039 u32 size; /* 0x0000 */ 2040 2041 u32 dcc_support; /* 0x0004 */ 2042 #define SHMEM_DCC_SUPPORT_NONE 0x00000000 2043 #define SHMEM_DCC_SUPPORT_DISABLE_ENABLE_PF_TLV 0x00000001 2044 #define SHMEM_DCC_SUPPORT_BANDWIDTH_ALLOCATION_TLV 0x00000004 2045 #define SHMEM_DCC_SUPPORT_CHANGE_MAC_ADDRESS_TLV 0x00000008 2046 #define SHMEM_DCC_SUPPORT_SET_PROTOCOL_TLV 0x00000040 2047 #define SHMEM_DCC_SUPPORT_SET_PRIORITY_TLV 0x00000080 2048 2049 u32 ext_phy_fw_version2[PORT_MAX]; /* 0x0008 */ 2050 /* 2051 * For backwards compatibility, if the mf_cfg_addr does not exist 2052 * (the size filed is smaller than 0xc) the mf_cfg resides at the 2053 * end of struct shmem_region 2054 */ 2055 u32 mf_cfg_addr; /* 0x0010 */ 2056 #define SHMEM_MF_CFG_ADDR_NONE 0x00000000 2057 2058 struct fw_flr_mb flr_mb; /* 0x0014 */ 2059 u32 dcbx_lldp_params_offset; /* 0x0028 */ 2060 #define SHMEM_LLDP_DCBX_PARAMS_NONE 0x00000000 2061 u32 dcbx_neg_res_offset; /* 0x002c */ 2062 #define SHMEM_DCBX_NEG_RES_NONE 0x00000000 2063 u32 dcbx_remote_mib_offset; /* 0x0030 */ 2064 #define SHMEM_DCBX_REMOTE_MIB_NONE 0x00000000 2065 /* 2066 * The other shmemX_base_addr holds the other path's shmem address 2067 * required for example in case of common phy init, or for path1 to know 2068 * the address of mcp debug trace which is located in offset from shmem 2069 * of path0 2070 */ 2071 u32 other_shmem_base_addr; /* 0x0034 */ 2072 u32 other_shmem2_base_addr; /* 0x0038 */ 2073 /* 2074 * mcp_vf_disabled is set by the MCP to indicate the driver about VFs 2075 * which were disabled/flred 2076 */ 2077 u32 mcp_vf_disabled[E2_VF_MAX / 32]; /* 0x003c */ 2078 2079 /* 2080 * drv_ack_vf_disabled is set by the PF driver to ack handled disabled 2081 * VFs 2082 */ 2083 u32 drv_ack_vf_disabled[E2_FUNC_MAX][E2_VF_MAX / 32]; /* 0x0044 */ 2084 2085 u32 dcbx_lldp_dcbx_stat_offset; /* 0x0064 */ 2086 #define SHMEM_LLDP_DCBX_STAT_NONE 0x00000000 2087 2088 /* 2089 * edebug_driver_if field is used to transfer messages between edebug 2090 * app to the driver through shmem2. 2091 * 2092 * message format: 2093 * bits 0-2 - function number / instance of driver to perform request 2094 * bits 3-5 - op code / is_ack? 2095 * bits 6-63 - data 2096 */ 2097 u32 edebug_driver_if[2]; /* 0x0068 */ 2098 #define EDEBUG_DRIVER_IF_OP_CODE_GET_PHYS_ADDR 1 2099 #define EDEBUG_DRIVER_IF_OP_CODE_GET_BUS_ADDR 2 2100 #define EDEBUG_DRIVER_IF_OP_CODE_DISABLE_STAT 3 2101 2102 u32 nvm_retain_bitmap_addr; /* 0x0070 */ 2103 2104 /* afex support of that driver */ 2105 u32 afex_driver_support; /* 0x0074 */ 2106 #define SHMEM_AFEX_VERSION_MASK 0x100f 2107 #define SHMEM_AFEX_SUPPORTED_VERSION_ONE 0x1001 2108 #define SHMEM_AFEX_REDUCED_DRV_LOADED 0x8000 2109 2110 /* driver receives addr in scratchpad to which it should respond */ 2111 u32 afex_scratchpad_addr_to_write[E2_FUNC_MAX]; 2112 2113 /* generic params from MCP to driver (value depends on the msg sent 2114 * to driver 2115 */ 2116 u32 afex_param1_to_driver[E2_FUNC_MAX]; /* 0x0088 */ 2117 u32 afex_param2_to_driver[E2_FUNC_MAX]; /* 0x0098 */ 2118 2119 u32 swim_base_addr; /* 0x0108 */ 2120 u32 swim_funcs; 2121 u32 swim_main_cb; 2122 2123 /* bitmap notifying which VIF profiles stored in nvram are enabled by 2124 * switch 2125 */ 2126 u32 afex_profiles_enabled[2]; 2127 2128 /* generic flags controlled by the driver */ 2129 u32 drv_flags; 2130 #define DRV_FLAGS_DCB_CONFIGURED 0x0 2131 #define DRV_FLAGS_DCB_CONFIGURATION_ABORTED 0x1 2132 #define DRV_FLAGS_DCB_MFW_CONFIGURED 0x2 2133 2134 #define DRV_FLAGS_PORT_MASK ((1 << DRV_FLAGS_DCB_CONFIGURED) | \ 2135 (1 << DRV_FLAGS_DCB_CONFIGURATION_ABORTED) | \ 2136 (1 << DRV_FLAGS_DCB_MFW_CONFIGURED)) 2137 /* pointer to extended dev_info shared data copied from nvm image */ 2138 u32 extended_dev_info_shared_addr; 2139 u32 ncsi_oem_data_addr; 2140 2141 u32 ocsd_host_addr; /* initialized by option ROM */ 2142 u32 ocbb_host_addr; /* initialized by option ROM */ 2143 u32 ocsd_req_update_interval; /* initialized by option ROM */ 2144 u32 temperature_in_half_celsius; 2145 u32 glob_struct_in_host; 2146 2147 u32 dcbx_neg_res_ext_offset; 2148 #define SHMEM_DCBX_NEG_RES_EXT_NONE 0x00000000 2149 2150 u32 drv_capabilities_flag[E2_FUNC_MAX]; 2151 #define DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED 0x00000001 2152 #define DRV_FLAGS_CAPABILITIES_LOADED_L2 0x00000002 2153 #define DRV_FLAGS_CAPABILITIES_LOADED_FCOE 0x00000004 2154 #define DRV_FLAGS_CAPABILITIES_LOADED_ISCSI 0x00000008 2155 2156 u32 extended_dev_info_shared_cfg_size; 2157 2158 u32 dcbx_en[PORT_MAX]; 2159 2160 /* The offset points to the multi threaded meta structure */ 2161 u32 multi_thread_data_offset; 2162 2163 /* address of DMAable host address holding values from the drivers */ 2164 u32 drv_info_host_addr_lo; 2165 u32 drv_info_host_addr_hi; 2166 2167 /* general values written by the MFW (such as current version) */ 2168 u32 drv_info_control; 2169 #define DRV_INFO_CONTROL_VER_MASK 0x000000ff 2170 #define DRV_INFO_CONTROL_VER_SHIFT 0 2171 #define DRV_INFO_CONTROL_OP_CODE_MASK 0x0000ff00 2172 #define DRV_INFO_CONTROL_OP_CODE_SHIFT 8 2173 u32 ibft_host_addr; /* initialized by option ROM */ 2174 struct eee_remote_vals eee_remote_vals[PORT_MAX]; 2175 u32 reserved[E2_FUNC_MAX]; 2176 2177 2178 /* the status of EEE auto-negotiation 2179 * bits 15:0 the configured tx-lpi entry timer value. Depends on bit 31. 2180 * bits 19:16 the supported modes for EEE. 2181 * bits 23:20 the speeds advertised for EEE. 2182 * bits 27:24 the speeds the Link partner advertised for EEE. 2183 * The supported/adv. modes in bits 27:19 originate from the 2184 * SHMEM_EEE_XXX_ADV definitions (where XXX is replaced by speed). 2185 * bit 28 when 1'b1 EEE was requested. 2186 * bit 29 when 1'b1 tx lpi was requested. 2187 * bit 30 when 1'b1 EEE was negotiated. Tx lpi will be asserted iff 2188 * 30:29 are 2'b11. 2189 * bit 31 when 1'b0 bits 15:0 contain a PORT_FEAT_CFG_EEE_ define as 2190 * value. When 1'b1 those bits contains a value times 16 microseconds. 2191 */ 2192 u32 eee_status[PORT_MAX]; 2193 #define SHMEM_EEE_TIMER_MASK 0x0000ffff 2194 #define SHMEM_EEE_SUPPORTED_MASK 0x000f0000 2195 #define SHMEM_EEE_SUPPORTED_SHIFT 16 2196 #define SHMEM_EEE_ADV_STATUS_MASK 0x00f00000 2197 #define SHMEM_EEE_100M_ADV (1<<0) 2198 #define SHMEM_EEE_1G_ADV (1<<1) 2199 #define SHMEM_EEE_10G_ADV (1<<2) 2200 #define SHMEM_EEE_ADV_STATUS_SHIFT 20 2201 #define SHMEM_EEE_LP_ADV_STATUS_MASK 0x0f000000 2202 #define SHMEM_EEE_LP_ADV_STATUS_SHIFT 24 2203 #define SHMEM_EEE_REQUESTED_BIT 0x10000000 2204 #define SHMEM_EEE_LPI_REQUESTED_BIT 0x20000000 2205 #define SHMEM_EEE_ACTIVE_BIT 0x40000000 2206 #define SHMEM_EEE_TIME_OUTPUT_BIT 0x80000000 2207 2208 u32 sizeof_port_stats; 2209 2210 /* Link Flap Avoidance */ 2211 u32 lfa_host_addr[PORT_MAX]; 2212 u32 reserved1; 2213 2214 u32 reserved2; /* Offset 0x148 */ 2215 u32 reserved3; /* Offset 0x14C */ 2216 u32 reserved4; /* Offset 0x150 */ 2217 u32 link_attr_sync[PORT_MAX]; /* Offset 0x154 */ 2218 #define LINK_ATTR_SYNC_KR2_ENABLE (1<<0) 2219 }; 2220 2221 2222 struct emac_stats { 2223 u32 rx_stat_ifhcinoctets; 2224 u32 rx_stat_ifhcinbadoctets; 2225 u32 rx_stat_etherstatsfragments; 2226 u32 rx_stat_ifhcinucastpkts; 2227 u32 rx_stat_ifhcinmulticastpkts; 2228 u32 rx_stat_ifhcinbroadcastpkts; 2229 u32 rx_stat_dot3statsfcserrors; 2230 u32 rx_stat_dot3statsalignmenterrors; 2231 u32 rx_stat_dot3statscarriersenseerrors; 2232 u32 rx_stat_xonpauseframesreceived; 2233 u32 rx_stat_xoffpauseframesreceived; 2234 u32 rx_stat_maccontrolframesreceived; 2235 u32 rx_stat_xoffstateentered; 2236 u32 rx_stat_dot3statsframestoolong; 2237 u32 rx_stat_etherstatsjabbers; 2238 u32 rx_stat_etherstatsundersizepkts; 2239 u32 rx_stat_etherstatspkts64octets; 2240 u32 rx_stat_etherstatspkts65octetsto127octets; 2241 u32 rx_stat_etherstatspkts128octetsto255octets; 2242 u32 rx_stat_etherstatspkts256octetsto511octets; 2243 u32 rx_stat_etherstatspkts512octetsto1023octets; 2244 u32 rx_stat_etherstatspkts1024octetsto1522octets; 2245 u32 rx_stat_etherstatspktsover1522octets; 2246 2247 u32 rx_stat_falsecarriererrors; 2248 2249 u32 tx_stat_ifhcoutoctets; 2250 u32 tx_stat_ifhcoutbadoctets; 2251 u32 tx_stat_etherstatscollisions; 2252 u32 tx_stat_outxonsent; 2253 u32 tx_stat_outxoffsent; 2254 u32 tx_stat_flowcontroldone; 2255 u32 tx_stat_dot3statssinglecollisionframes; 2256 u32 tx_stat_dot3statsmultiplecollisionframes; 2257 u32 tx_stat_dot3statsdeferredtransmissions; 2258 u32 tx_stat_dot3statsexcessivecollisions; 2259 u32 tx_stat_dot3statslatecollisions; 2260 u32 tx_stat_ifhcoutucastpkts; 2261 u32 tx_stat_ifhcoutmulticastpkts; 2262 u32 tx_stat_ifhcoutbroadcastpkts; 2263 u32 tx_stat_etherstatspkts64octets; 2264 u32 tx_stat_etherstatspkts65octetsto127octets; 2265 u32 tx_stat_etherstatspkts128octetsto255octets; 2266 u32 tx_stat_etherstatspkts256octetsto511octets; 2267 u32 tx_stat_etherstatspkts512octetsto1023octets; 2268 u32 tx_stat_etherstatspkts1024octetsto1522octets; 2269 u32 tx_stat_etherstatspktsover1522octets; 2270 u32 tx_stat_dot3statsinternalmactransmiterrors; 2271 }; 2272 2273 2274 struct bmac1_stats { 2275 u32 tx_stat_gtpkt_lo; 2276 u32 tx_stat_gtpkt_hi; 2277 u32 tx_stat_gtxpf_lo; 2278 u32 tx_stat_gtxpf_hi; 2279 u32 tx_stat_gtfcs_lo; 2280 u32 tx_stat_gtfcs_hi; 2281 u32 tx_stat_gtmca_lo; 2282 u32 tx_stat_gtmca_hi; 2283 u32 tx_stat_gtbca_lo; 2284 u32 tx_stat_gtbca_hi; 2285 u32 tx_stat_gtfrg_lo; 2286 u32 tx_stat_gtfrg_hi; 2287 u32 tx_stat_gtovr_lo; 2288 u32 tx_stat_gtovr_hi; 2289 u32 tx_stat_gt64_lo; 2290 u32 tx_stat_gt64_hi; 2291 u32 tx_stat_gt127_lo; 2292 u32 tx_stat_gt127_hi; 2293 u32 tx_stat_gt255_lo; 2294 u32 tx_stat_gt255_hi; 2295 u32 tx_stat_gt511_lo; 2296 u32 tx_stat_gt511_hi; 2297 u32 tx_stat_gt1023_lo; 2298 u32 tx_stat_gt1023_hi; 2299 u32 tx_stat_gt1518_lo; 2300 u32 tx_stat_gt1518_hi; 2301 u32 tx_stat_gt2047_lo; 2302 u32 tx_stat_gt2047_hi; 2303 u32 tx_stat_gt4095_lo; 2304 u32 tx_stat_gt4095_hi; 2305 u32 tx_stat_gt9216_lo; 2306 u32 tx_stat_gt9216_hi; 2307 u32 tx_stat_gt16383_lo; 2308 u32 tx_stat_gt16383_hi; 2309 u32 tx_stat_gtmax_lo; 2310 u32 tx_stat_gtmax_hi; 2311 u32 tx_stat_gtufl_lo; 2312 u32 tx_stat_gtufl_hi; 2313 u32 tx_stat_gterr_lo; 2314 u32 tx_stat_gterr_hi; 2315 u32 tx_stat_gtbyt_lo; 2316 u32 tx_stat_gtbyt_hi; 2317 2318 u32 rx_stat_gr64_lo; 2319 u32 rx_stat_gr64_hi; 2320 u32 rx_stat_gr127_lo; 2321 u32 rx_stat_gr127_hi; 2322 u32 rx_stat_gr255_lo; 2323 u32 rx_stat_gr255_hi; 2324 u32 rx_stat_gr511_lo; 2325 u32 rx_stat_gr511_hi; 2326 u32 rx_stat_gr1023_lo; 2327 u32 rx_stat_gr1023_hi; 2328 u32 rx_stat_gr1518_lo; 2329 u32 rx_stat_gr1518_hi; 2330 u32 rx_stat_gr2047_lo; 2331 u32 rx_stat_gr2047_hi; 2332 u32 rx_stat_gr4095_lo; 2333 u32 rx_stat_gr4095_hi; 2334 u32 rx_stat_gr9216_lo; 2335 u32 rx_stat_gr9216_hi; 2336 u32 rx_stat_gr16383_lo; 2337 u32 rx_stat_gr16383_hi; 2338 u32 rx_stat_grmax_lo; 2339 u32 rx_stat_grmax_hi; 2340 u32 rx_stat_grpkt_lo; 2341 u32 rx_stat_grpkt_hi; 2342 u32 rx_stat_grfcs_lo; 2343 u32 rx_stat_grfcs_hi; 2344 u32 rx_stat_grmca_lo; 2345 u32 rx_stat_grmca_hi; 2346 u32 rx_stat_grbca_lo; 2347 u32 rx_stat_grbca_hi; 2348 u32 rx_stat_grxcf_lo; 2349 u32 rx_stat_grxcf_hi; 2350 u32 rx_stat_grxpf_lo; 2351 u32 rx_stat_grxpf_hi; 2352 u32 rx_stat_grxuo_lo; 2353 u32 rx_stat_grxuo_hi; 2354 u32 rx_stat_grjbr_lo; 2355 u32 rx_stat_grjbr_hi; 2356 u32 rx_stat_grovr_lo; 2357 u32 rx_stat_grovr_hi; 2358 u32 rx_stat_grflr_lo; 2359 u32 rx_stat_grflr_hi; 2360 u32 rx_stat_grmeg_lo; 2361 u32 rx_stat_grmeg_hi; 2362 u32 rx_stat_grmeb_lo; 2363 u32 rx_stat_grmeb_hi; 2364 u32 rx_stat_grbyt_lo; 2365 u32 rx_stat_grbyt_hi; 2366 u32 rx_stat_grund_lo; 2367 u32 rx_stat_grund_hi; 2368 u32 rx_stat_grfrg_lo; 2369 u32 rx_stat_grfrg_hi; 2370 u32 rx_stat_grerb_lo; 2371 u32 rx_stat_grerb_hi; 2372 u32 rx_stat_grfre_lo; 2373 u32 rx_stat_grfre_hi; 2374 u32 rx_stat_gripj_lo; 2375 u32 rx_stat_gripj_hi; 2376 }; 2377 2378 struct bmac2_stats { 2379 u32 tx_stat_gtpk_lo; /* gtpok */ 2380 u32 tx_stat_gtpk_hi; /* gtpok */ 2381 u32 tx_stat_gtxpf_lo; /* gtpf */ 2382 u32 tx_stat_gtxpf_hi; /* gtpf */ 2383 u32 tx_stat_gtpp_lo; /* NEW BMAC2 */ 2384 u32 tx_stat_gtpp_hi; /* NEW BMAC2 */ 2385 u32 tx_stat_gtfcs_lo; 2386 u32 tx_stat_gtfcs_hi; 2387 u32 tx_stat_gtuca_lo; /* NEW BMAC2 */ 2388 u32 tx_stat_gtuca_hi; /* NEW BMAC2 */ 2389 u32 tx_stat_gtmca_lo; 2390 u32 tx_stat_gtmca_hi; 2391 u32 tx_stat_gtbca_lo; 2392 u32 tx_stat_gtbca_hi; 2393 u32 tx_stat_gtovr_lo; 2394 u32 tx_stat_gtovr_hi; 2395 u32 tx_stat_gtfrg_lo; 2396 u32 tx_stat_gtfrg_hi; 2397 u32 tx_stat_gtpkt1_lo; /* gtpkt */ 2398 u32 tx_stat_gtpkt1_hi; /* gtpkt */ 2399 u32 tx_stat_gt64_lo; 2400 u32 tx_stat_gt64_hi; 2401 u32 tx_stat_gt127_lo; 2402 u32 tx_stat_gt127_hi; 2403 u32 tx_stat_gt255_lo; 2404 u32 tx_stat_gt255_hi; 2405 u32 tx_stat_gt511_lo; 2406 u32 tx_stat_gt511_hi; 2407 u32 tx_stat_gt1023_lo; 2408 u32 tx_stat_gt1023_hi; 2409 u32 tx_stat_gt1518_lo; 2410 u32 tx_stat_gt1518_hi; 2411 u32 tx_stat_gt2047_lo; 2412 u32 tx_stat_gt2047_hi; 2413 u32 tx_stat_gt4095_lo; 2414 u32 tx_stat_gt4095_hi; 2415 u32 tx_stat_gt9216_lo; 2416 u32 tx_stat_gt9216_hi; 2417 u32 tx_stat_gt16383_lo; 2418 u32 tx_stat_gt16383_hi; 2419 u32 tx_stat_gtmax_lo; 2420 u32 tx_stat_gtmax_hi; 2421 u32 tx_stat_gtufl_lo; 2422 u32 tx_stat_gtufl_hi; 2423 u32 tx_stat_gterr_lo; 2424 u32 tx_stat_gterr_hi; 2425 u32 tx_stat_gtbyt_lo; 2426 u32 tx_stat_gtbyt_hi; 2427 2428 u32 rx_stat_gr64_lo; 2429 u32 rx_stat_gr64_hi; 2430 u32 rx_stat_gr127_lo; 2431 u32 rx_stat_gr127_hi; 2432 u32 rx_stat_gr255_lo; 2433 u32 rx_stat_gr255_hi; 2434 u32 rx_stat_gr511_lo; 2435 u32 rx_stat_gr511_hi; 2436 u32 rx_stat_gr1023_lo; 2437 u32 rx_stat_gr1023_hi; 2438 u32 rx_stat_gr1518_lo; 2439 u32 rx_stat_gr1518_hi; 2440 u32 rx_stat_gr2047_lo; 2441 u32 rx_stat_gr2047_hi; 2442 u32 rx_stat_gr4095_lo; 2443 u32 rx_stat_gr4095_hi; 2444 u32 rx_stat_gr9216_lo; 2445 u32 rx_stat_gr9216_hi; 2446 u32 rx_stat_gr16383_lo; 2447 u32 rx_stat_gr16383_hi; 2448 u32 rx_stat_grmax_lo; 2449 u32 rx_stat_grmax_hi; 2450 u32 rx_stat_grpkt_lo; 2451 u32 rx_stat_grpkt_hi; 2452 u32 rx_stat_grfcs_lo; 2453 u32 rx_stat_grfcs_hi; 2454 u32 rx_stat_gruca_lo; 2455 u32 rx_stat_gruca_hi; 2456 u32 rx_stat_grmca_lo; 2457 u32 rx_stat_grmca_hi; 2458 u32 rx_stat_grbca_lo; 2459 u32 rx_stat_grbca_hi; 2460 u32 rx_stat_grxpf_lo; /* grpf */ 2461 u32 rx_stat_grxpf_hi; /* grpf */ 2462 u32 rx_stat_grpp_lo; 2463 u32 rx_stat_grpp_hi; 2464 u32 rx_stat_grxuo_lo; /* gruo */ 2465 u32 rx_stat_grxuo_hi; /* gruo */ 2466 u32 rx_stat_grjbr_lo; 2467 u32 rx_stat_grjbr_hi; 2468 u32 rx_stat_grovr_lo; 2469 u32 rx_stat_grovr_hi; 2470 u32 rx_stat_grxcf_lo; /* grcf */ 2471 u32 rx_stat_grxcf_hi; /* grcf */ 2472 u32 rx_stat_grflr_lo; 2473 u32 rx_stat_grflr_hi; 2474 u32 rx_stat_grpok_lo; 2475 u32 rx_stat_grpok_hi; 2476 u32 rx_stat_grmeg_lo; 2477 u32 rx_stat_grmeg_hi; 2478 u32 rx_stat_grmeb_lo; 2479 u32 rx_stat_grmeb_hi; 2480 u32 rx_stat_grbyt_lo; 2481 u32 rx_stat_grbyt_hi; 2482 u32 rx_stat_grund_lo; 2483 u32 rx_stat_grund_hi; 2484 u32 rx_stat_grfrg_lo; 2485 u32 rx_stat_grfrg_hi; 2486 u32 rx_stat_grerb_lo; /* grerrbyt */ 2487 u32 rx_stat_grerb_hi; /* grerrbyt */ 2488 u32 rx_stat_grfre_lo; /* grfrerr */ 2489 u32 rx_stat_grfre_hi; /* grfrerr */ 2490 u32 rx_stat_gripj_lo; 2491 u32 rx_stat_gripj_hi; 2492 }; 2493 2494 struct mstat_stats { 2495 struct { 2496 /* OTE MSTAT on E3 has a bug where this register's contents are 2497 * actually tx_gtxpok + tx_gtxpf + (possibly)tx_gtxpp 2498 */ 2499 u32 tx_gtxpok_lo; 2500 u32 tx_gtxpok_hi; 2501 u32 tx_gtxpf_lo; 2502 u32 tx_gtxpf_hi; 2503 u32 tx_gtxpp_lo; 2504 u32 tx_gtxpp_hi; 2505 u32 tx_gtfcs_lo; 2506 u32 tx_gtfcs_hi; 2507 u32 tx_gtuca_lo; 2508 u32 tx_gtuca_hi; 2509 u32 tx_gtmca_lo; 2510 u32 tx_gtmca_hi; 2511 u32 tx_gtgca_lo; 2512 u32 tx_gtgca_hi; 2513 u32 tx_gtpkt_lo; 2514 u32 tx_gtpkt_hi; 2515 u32 tx_gt64_lo; 2516 u32 tx_gt64_hi; 2517 u32 tx_gt127_lo; 2518 u32 tx_gt127_hi; 2519 u32 tx_gt255_lo; 2520 u32 tx_gt255_hi; 2521 u32 tx_gt511_lo; 2522 u32 tx_gt511_hi; 2523 u32 tx_gt1023_lo; 2524 u32 tx_gt1023_hi; 2525 u32 tx_gt1518_lo; 2526 u32 tx_gt1518_hi; 2527 u32 tx_gt2047_lo; 2528 u32 tx_gt2047_hi; 2529 u32 tx_gt4095_lo; 2530 u32 tx_gt4095_hi; 2531 u32 tx_gt9216_lo; 2532 u32 tx_gt9216_hi; 2533 u32 tx_gt16383_lo; 2534 u32 tx_gt16383_hi; 2535 u32 tx_gtufl_lo; 2536 u32 tx_gtufl_hi; 2537 u32 tx_gterr_lo; 2538 u32 tx_gterr_hi; 2539 u32 tx_gtbyt_lo; 2540 u32 tx_gtbyt_hi; 2541 u32 tx_collisions_lo; 2542 u32 tx_collisions_hi; 2543 u32 tx_singlecollision_lo; 2544 u32 tx_singlecollision_hi; 2545 u32 tx_multiplecollisions_lo; 2546 u32 tx_multiplecollisions_hi; 2547 u32 tx_deferred_lo; 2548 u32 tx_deferred_hi; 2549 u32 tx_excessivecollisions_lo; 2550 u32 tx_excessivecollisions_hi; 2551 u32 tx_latecollisions_lo; 2552 u32 tx_latecollisions_hi; 2553 } stats_tx; 2554 2555 struct { 2556 u32 rx_gr64_lo; 2557 u32 rx_gr64_hi; 2558 u32 rx_gr127_lo; 2559 u32 rx_gr127_hi; 2560 u32 rx_gr255_lo; 2561 u32 rx_gr255_hi; 2562 u32 rx_gr511_lo; 2563 u32 rx_gr511_hi; 2564 u32 rx_gr1023_lo; 2565 u32 rx_gr1023_hi; 2566 u32 rx_gr1518_lo; 2567 u32 rx_gr1518_hi; 2568 u32 rx_gr2047_lo; 2569 u32 rx_gr2047_hi; 2570 u32 rx_gr4095_lo; 2571 u32 rx_gr4095_hi; 2572 u32 rx_gr9216_lo; 2573 u32 rx_gr9216_hi; 2574 u32 rx_gr16383_lo; 2575 u32 rx_gr16383_hi; 2576 u32 rx_grpkt_lo; 2577 u32 rx_grpkt_hi; 2578 u32 rx_grfcs_lo; 2579 u32 rx_grfcs_hi; 2580 u32 rx_gruca_lo; 2581 u32 rx_gruca_hi; 2582 u32 rx_grmca_lo; 2583 u32 rx_grmca_hi; 2584 u32 rx_grbca_lo; 2585 u32 rx_grbca_hi; 2586 u32 rx_grxpf_lo; 2587 u32 rx_grxpf_hi; 2588 u32 rx_grxpp_lo; 2589 u32 rx_grxpp_hi; 2590 u32 rx_grxuo_lo; 2591 u32 rx_grxuo_hi; 2592 u32 rx_grovr_lo; 2593 u32 rx_grovr_hi; 2594 u32 rx_grxcf_lo; 2595 u32 rx_grxcf_hi; 2596 u32 rx_grflr_lo; 2597 u32 rx_grflr_hi; 2598 u32 rx_grpok_lo; 2599 u32 rx_grpok_hi; 2600 u32 rx_grbyt_lo; 2601 u32 rx_grbyt_hi; 2602 u32 rx_grund_lo; 2603 u32 rx_grund_hi; 2604 u32 rx_grfrg_lo; 2605 u32 rx_grfrg_hi; 2606 u32 rx_grerb_lo; 2607 u32 rx_grerb_hi; 2608 u32 rx_grfre_lo; 2609 u32 rx_grfre_hi; 2610 2611 u32 rx_alignmenterrors_lo; 2612 u32 rx_alignmenterrors_hi; 2613 u32 rx_falsecarrier_lo; 2614 u32 rx_falsecarrier_hi; 2615 u32 rx_llfcmsgcnt_lo; 2616 u32 rx_llfcmsgcnt_hi; 2617 } stats_rx; 2618 }; 2619 2620 union mac_stats { 2621 struct emac_stats emac_stats; 2622 struct bmac1_stats bmac1_stats; 2623 struct bmac2_stats bmac2_stats; 2624 struct mstat_stats mstat_stats; 2625 }; 2626 2627 2628 struct mac_stx { 2629 /* in_bad_octets */ 2630 u32 rx_stat_ifhcinbadoctets_hi; 2631 u32 rx_stat_ifhcinbadoctets_lo; 2632 2633 /* out_bad_octets */ 2634 u32 tx_stat_ifhcoutbadoctets_hi; 2635 u32 tx_stat_ifhcoutbadoctets_lo; 2636 2637 /* crc_receive_errors */ 2638 u32 rx_stat_dot3statsfcserrors_hi; 2639 u32 rx_stat_dot3statsfcserrors_lo; 2640 /* alignment_errors */ 2641 u32 rx_stat_dot3statsalignmenterrors_hi; 2642 u32 rx_stat_dot3statsalignmenterrors_lo; 2643 /* carrier_sense_errors */ 2644 u32 rx_stat_dot3statscarriersenseerrors_hi; 2645 u32 rx_stat_dot3statscarriersenseerrors_lo; 2646 /* false_carrier_detections */ 2647 u32 rx_stat_falsecarriererrors_hi; 2648 u32 rx_stat_falsecarriererrors_lo; 2649 2650 /* runt_packets_received */ 2651 u32 rx_stat_etherstatsundersizepkts_hi; 2652 u32 rx_stat_etherstatsundersizepkts_lo; 2653 /* jabber_packets_received */ 2654 u32 rx_stat_dot3statsframestoolong_hi; 2655 u32 rx_stat_dot3statsframestoolong_lo; 2656 2657 /* error_runt_packets_received */ 2658 u32 rx_stat_etherstatsfragments_hi; 2659 u32 rx_stat_etherstatsfragments_lo; 2660 /* error_jabber_packets_received */ 2661 u32 rx_stat_etherstatsjabbers_hi; 2662 u32 rx_stat_etherstatsjabbers_lo; 2663 2664 /* control_frames_received */ 2665 u32 rx_stat_maccontrolframesreceived_hi; 2666 u32 rx_stat_maccontrolframesreceived_lo; 2667 u32 rx_stat_mac_xpf_hi; 2668 u32 rx_stat_mac_xpf_lo; 2669 u32 rx_stat_mac_xcf_hi; 2670 u32 rx_stat_mac_xcf_lo; 2671 2672 /* xoff_state_entered */ 2673 u32 rx_stat_xoffstateentered_hi; 2674 u32 rx_stat_xoffstateentered_lo; 2675 /* pause_xon_frames_received */ 2676 u32 rx_stat_xonpauseframesreceived_hi; 2677 u32 rx_stat_xonpauseframesreceived_lo; 2678 /* pause_xoff_frames_received */ 2679 u32 rx_stat_xoffpauseframesreceived_hi; 2680 u32 rx_stat_xoffpauseframesreceived_lo; 2681 /* pause_xon_frames_transmitted */ 2682 u32 tx_stat_outxonsent_hi; 2683 u32 tx_stat_outxonsent_lo; 2684 /* pause_xoff_frames_transmitted */ 2685 u32 tx_stat_outxoffsent_hi; 2686 u32 tx_stat_outxoffsent_lo; 2687 /* flow_control_done */ 2688 u32 tx_stat_flowcontroldone_hi; 2689 u32 tx_stat_flowcontroldone_lo; 2690 2691 /* ether_stats_collisions */ 2692 u32 tx_stat_etherstatscollisions_hi; 2693 u32 tx_stat_etherstatscollisions_lo; 2694 /* single_collision_transmit_frames */ 2695 u32 tx_stat_dot3statssinglecollisionframes_hi; 2696 u32 tx_stat_dot3statssinglecollisionframes_lo; 2697 /* multiple_collision_transmit_frames */ 2698 u32 tx_stat_dot3statsmultiplecollisionframes_hi; 2699 u32 tx_stat_dot3statsmultiplecollisionframes_lo; 2700 /* deferred_transmissions */ 2701 u32 tx_stat_dot3statsdeferredtransmissions_hi; 2702 u32 tx_stat_dot3statsdeferredtransmissions_lo; 2703 /* excessive_collision_frames */ 2704 u32 tx_stat_dot3statsexcessivecollisions_hi; 2705 u32 tx_stat_dot3statsexcessivecollisions_lo; 2706 /* late_collision_frames */ 2707 u32 tx_stat_dot3statslatecollisions_hi; 2708 u32 tx_stat_dot3statslatecollisions_lo; 2709 2710 /* frames_transmitted_64_bytes */ 2711 u32 tx_stat_etherstatspkts64octets_hi; 2712 u32 tx_stat_etherstatspkts64octets_lo; 2713 /* frames_transmitted_65_127_bytes */ 2714 u32 tx_stat_etherstatspkts65octetsto127octets_hi; 2715 u32 tx_stat_etherstatspkts65octetsto127octets_lo; 2716 /* frames_transmitted_128_255_bytes */ 2717 u32 tx_stat_etherstatspkts128octetsto255octets_hi; 2718 u32 tx_stat_etherstatspkts128octetsto255octets_lo; 2719 /* frames_transmitted_256_511_bytes */ 2720 u32 tx_stat_etherstatspkts256octetsto511octets_hi; 2721 u32 tx_stat_etherstatspkts256octetsto511octets_lo; 2722 /* frames_transmitted_512_1023_bytes */ 2723 u32 tx_stat_etherstatspkts512octetsto1023octets_hi; 2724 u32 tx_stat_etherstatspkts512octetsto1023octets_lo; 2725 /* frames_transmitted_1024_1522_bytes */ 2726 u32 tx_stat_etherstatspkts1024octetsto1522octets_hi; 2727 u32 tx_stat_etherstatspkts1024octetsto1522octets_lo; 2728 /* frames_transmitted_1523_9022_bytes */ 2729 u32 tx_stat_etherstatspktsover1522octets_hi; 2730 u32 tx_stat_etherstatspktsover1522octets_lo; 2731 u32 tx_stat_mac_2047_hi; 2732 u32 tx_stat_mac_2047_lo; 2733 u32 tx_stat_mac_4095_hi; 2734 u32 tx_stat_mac_4095_lo; 2735 u32 tx_stat_mac_9216_hi; 2736 u32 tx_stat_mac_9216_lo; 2737 u32 tx_stat_mac_16383_hi; 2738 u32 tx_stat_mac_16383_lo; 2739 2740 /* internal_mac_transmit_errors */ 2741 u32 tx_stat_dot3statsinternalmactransmiterrors_hi; 2742 u32 tx_stat_dot3statsinternalmactransmiterrors_lo; 2743 2744 /* if_out_discards */ 2745 u32 tx_stat_mac_ufl_hi; 2746 u32 tx_stat_mac_ufl_lo; 2747 }; 2748 2749 2750 #define MAC_STX_IDX_MAX 2 2751 2752 struct host_port_stats { 2753 u32 host_port_stats_counter; 2754 2755 struct mac_stx mac_stx[MAC_STX_IDX_MAX]; 2756 2757 u32 brb_drop_hi; 2758 u32 brb_drop_lo; 2759 2760 u32 not_used; /* obsolete */ 2761 u32 pfc_frames_tx_hi; 2762 u32 pfc_frames_tx_lo; 2763 u32 pfc_frames_rx_hi; 2764 u32 pfc_frames_rx_lo; 2765 2766 u32 eee_lpi_count_hi; 2767 u32 eee_lpi_count_lo; 2768 }; 2769 2770 2771 struct host_func_stats { 2772 u32 host_func_stats_start; 2773 2774 u32 total_bytes_received_hi; 2775 u32 total_bytes_received_lo; 2776 2777 u32 total_bytes_transmitted_hi; 2778 u32 total_bytes_transmitted_lo; 2779 2780 u32 total_unicast_packets_received_hi; 2781 u32 total_unicast_packets_received_lo; 2782 2783 u32 total_multicast_packets_received_hi; 2784 u32 total_multicast_packets_received_lo; 2785 2786 u32 total_broadcast_packets_received_hi; 2787 u32 total_broadcast_packets_received_lo; 2788 2789 u32 total_unicast_packets_transmitted_hi; 2790 u32 total_unicast_packets_transmitted_lo; 2791 2792 u32 total_multicast_packets_transmitted_hi; 2793 u32 total_multicast_packets_transmitted_lo; 2794 2795 u32 total_broadcast_packets_transmitted_hi; 2796 u32 total_broadcast_packets_transmitted_lo; 2797 2798 u32 valid_bytes_received_hi; 2799 u32 valid_bytes_received_lo; 2800 2801 u32 host_func_stats_end; 2802 }; 2803 2804 /* VIC definitions */ 2805 #define VICSTATST_UIF_INDEX 2 2806 2807 2808 /* stats collected for afex. 2809 * NOTE: structure is exactly as expected to be received by the switch. 2810 * order must remain exactly as is unless protocol changes ! 2811 */ 2812 struct afex_stats { 2813 u32 tx_unicast_frames_hi; 2814 u32 tx_unicast_frames_lo; 2815 u32 tx_unicast_bytes_hi; 2816 u32 tx_unicast_bytes_lo; 2817 u32 tx_multicast_frames_hi; 2818 u32 tx_multicast_frames_lo; 2819 u32 tx_multicast_bytes_hi; 2820 u32 tx_multicast_bytes_lo; 2821 u32 tx_broadcast_frames_hi; 2822 u32 tx_broadcast_frames_lo; 2823 u32 tx_broadcast_bytes_hi; 2824 u32 tx_broadcast_bytes_lo; 2825 u32 tx_frames_discarded_hi; 2826 u32 tx_frames_discarded_lo; 2827 u32 tx_frames_dropped_hi; 2828 u32 tx_frames_dropped_lo; 2829 2830 u32 rx_unicast_frames_hi; 2831 u32 rx_unicast_frames_lo; 2832 u32 rx_unicast_bytes_hi; 2833 u32 rx_unicast_bytes_lo; 2834 u32 rx_multicast_frames_hi; 2835 u32 rx_multicast_frames_lo; 2836 u32 rx_multicast_bytes_hi; 2837 u32 rx_multicast_bytes_lo; 2838 u32 rx_broadcast_frames_hi; 2839 u32 rx_broadcast_frames_lo; 2840 u32 rx_broadcast_bytes_hi; 2841 u32 rx_broadcast_bytes_lo; 2842 u32 rx_frames_discarded_hi; 2843 u32 rx_frames_discarded_lo; 2844 u32 rx_frames_dropped_hi; 2845 u32 rx_frames_dropped_lo; 2846 }; 2847 2848 #define BCM_5710_FW_MAJOR_VERSION 7 2849 #define BCM_5710_FW_MINOR_VERSION 8 2850 #define BCM_5710_FW_REVISION_VERSION 17 2851 #define BCM_5710_FW_ENGINEERING_VERSION 0 2852 #define BCM_5710_FW_COMPILE_FLAGS 1 2853 2854 2855 /* 2856 * attention bits 2857 */ 2858 struct atten_sp_status_block { 2859 __le32 attn_bits; 2860 __le32 attn_bits_ack; 2861 u8 status_block_id; 2862 u8 reserved0; 2863 __le16 attn_bits_index; 2864 __le32 reserved1; 2865 }; 2866 2867 2868 /* 2869 * The eth aggregative context of Cstorm 2870 */ 2871 struct cstorm_eth_ag_context { 2872 u32 __reserved0[10]; 2873 }; 2874 2875 2876 /* 2877 * dmae command structure 2878 */ 2879 struct dmae_command { 2880 u32 opcode; 2881 #define DMAE_COMMAND_SRC (0x1<<0) 2882 #define DMAE_COMMAND_SRC_SHIFT 0 2883 #define DMAE_COMMAND_DST (0x3<<1) 2884 #define DMAE_COMMAND_DST_SHIFT 1 2885 #define DMAE_COMMAND_C_DST (0x1<<3) 2886 #define DMAE_COMMAND_C_DST_SHIFT 3 2887 #define DMAE_COMMAND_C_TYPE_ENABLE (0x1<<4) 2888 #define DMAE_COMMAND_C_TYPE_ENABLE_SHIFT 4 2889 #define DMAE_COMMAND_C_TYPE_CRC_ENABLE (0x1<<5) 2890 #define DMAE_COMMAND_C_TYPE_CRC_ENABLE_SHIFT 5 2891 #define DMAE_COMMAND_C_TYPE_CRC_OFFSET (0x7<<6) 2892 #define DMAE_COMMAND_C_TYPE_CRC_OFFSET_SHIFT 6 2893 #define DMAE_COMMAND_ENDIANITY (0x3<<9) 2894 #define DMAE_COMMAND_ENDIANITY_SHIFT 9 2895 #define DMAE_COMMAND_PORT (0x1<<11) 2896 #define DMAE_COMMAND_PORT_SHIFT 11 2897 #define DMAE_COMMAND_CRC_RESET (0x1<<12) 2898 #define DMAE_COMMAND_CRC_RESET_SHIFT 12 2899 #define DMAE_COMMAND_SRC_RESET (0x1<<13) 2900 #define DMAE_COMMAND_SRC_RESET_SHIFT 13 2901 #define DMAE_COMMAND_DST_RESET (0x1<<14) 2902 #define DMAE_COMMAND_DST_RESET_SHIFT 14 2903 #define DMAE_COMMAND_E1HVN (0x3<<15) 2904 #define DMAE_COMMAND_E1HVN_SHIFT 15 2905 #define DMAE_COMMAND_DST_VN (0x3<<17) 2906 #define DMAE_COMMAND_DST_VN_SHIFT 17 2907 #define DMAE_COMMAND_C_FUNC (0x1<<19) 2908 #define DMAE_COMMAND_C_FUNC_SHIFT 19 2909 #define DMAE_COMMAND_ERR_POLICY (0x3<<20) 2910 #define DMAE_COMMAND_ERR_POLICY_SHIFT 20 2911 #define DMAE_COMMAND_RESERVED0 (0x3FF<<22) 2912 #define DMAE_COMMAND_RESERVED0_SHIFT 22 2913 u32 src_addr_lo; 2914 u32 src_addr_hi; 2915 u32 dst_addr_lo; 2916 u32 dst_addr_hi; 2917 #if defined(__BIG_ENDIAN) 2918 u16 opcode_iov; 2919 #define DMAE_COMMAND_SRC_VFID (0x3F<<0) 2920 #define DMAE_COMMAND_SRC_VFID_SHIFT 0 2921 #define DMAE_COMMAND_SRC_VFPF (0x1<<6) 2922 #define DMAE_COMMAND_SRC_VFPF_SHIFT 6 2923 #define DMAE_COMMAND_RESERVED1 (0x1<<7) 2924 #define DMAE_COMMAND_RESERVED1_SHIFT 7 2925 #define DMAE_COMMAND_DST_VFID (0x3F<<8) 2926 #define DMAE_COMMAND_DST_VFID_SHIFT 8 2927 #define DMAE_COMMAND_DST_VFPF (0x1<<14) 2928 #define DMAE_COMMAND_DST_VFPF_SHIFT 14 2929 #define DMAE_COMMAND_RESERVED2 (0x1<<15) 2930 #define DMAE_COMMAND_RESERVED2_SHIFT 15 2931 u16 len; 2932 #elif defined(__LITTLE_ENDIAN) 2933 u16 len; 2934 u16 opcode_iov; 2935 #define DMAE_COMMAND_SRC_VFID (0x3F<<0) 2936 #define DMAE_COMMAND_SRC_VFID_SHIFT 0 2937 #define DMAE_COMMAND_SRC_VFPF (0x1<<6) 2938 #define DMAE_COMMAND_SRC_VFPF_SHIFT 6 2939 #define DMAE_COMMAND_RESERVED1 (0x1<<7) 2940 #define DMAE_COMMAND_RESERVED1_SHIFT 7 2941 #define DMAE_COMMAND_DST_VFID (0x3F<<8) 2942 #define DMAE_COMMAND_DST_VFID_SHIFT 8 2943 #define DMAE_COMMAND_DST_VFPF (0x1<<14) 2944 #define DMAE_COMMAND_DST_VFPF_SHIFT 14 2945 #define DMAE_COMMAND_RESERVED2 (0x1<<15) 2946 #define DMAE_COMMAND_RESERVED2_SHIFT 15 2947 #endif 2948 u32 comp_addr_lo; 2949 u32 comp_addr_hi; 2950 u32 comp_val; 2951 u32 crc32; 2952 u32 crc32_c; 2953 #if defined(__BIG_ENDIAN) 2954 u16 crc16_c; 2955 u16 crc16; 2956 #elif defined(__LITTLE_ENDIAN) 2957 u16 crc16; 2958 u16 crc16_c; 2959 #endif 2960 #if defined(__BIG_ENDIAN) 2961 u16 reserved3; 2962 u16 crc_t10; 2963 #elif defined(__LITTLE_ENDIAN) 2964 u16 crc_t10; 2965 u16 reserved3; 2966 #endif 2967 #if defined(__BIG_ENDIAN) 2968 u16 xsum8; 2969 u16 xsum16; 2970 #elif defined(__LITTLE_ENDIAN) 2971 u16 xsum16; 2972 u16 xsum8; 2973 #endif 2974 }; 2975 2976 2977 /* 2978 * common data for all protocols 2979 */ 2980 struct doorbell_hdr { 2981 u8 header; 2982 #define DOORBELL_HDR_RX (0x1<<0) 2983 #define DOORBELL_HDR_RX_SHIFT 0 2984 #define DOORBELL_HDR_DB_TYPE (0x1<<1) 2985 #define DOORBELL_HDR_DB_TYPE_SHIFT 1 2986 #define DOORBELL_HDR_DPM_SIZE (0x3<<2) 2987 #define DOORBELL_HDR_DPM_SIZE_SHIFT 2 2988 #define DOORBELL_HDR_CONN_TYPE (0xF<<4) 2989 #define DOORBELL_HDR_CONN_TYPE_SHIFT 4 2990 }; 2991 2992 /* 2993 * Ethernet doorbell 2994 */ 2995 struct eth_tx_doorbell { 2996 #if defined(__BIG_ENDIAN) 2997 u16 npackets; 2998 u8 params; 2999 #define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0) 3000 #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0 3001 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6) 3002 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6 3003 #define ETH_TX_DOORBELL_SPARE (0x1<<7) 3004 #define ETH_TX_DOORBELL_SPARE_SHIFT 7 3005 struct doorbell_hdr hdr; 3006 #elif defined(__LITTLE_ENDIAN) 3007 struct doorbell_hdr hdr; 3008 u8 params; 3009 #define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0) 3010 #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0 3011 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6) 3012 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6 3013 #define ETH_TX_DOORBELL_SPARE (0x1<<7) 3014 #define ETH_TX_DOORBELL_SPARE_SHIFT 7 3015 u16 npackets; 3016 #endif 3017 }; 3018 3019 3020 /* 3021 * 3 lines. status block 3022 */ 3023 struct hc_status_block_e1x { 3024 __le16 index_values[HC_SB_MAX_INDICES_E1X]; 3025 __le16 running_index[HC_SB_MAX_SM]; 3026 __le32 rsrv[11]; 3027 }; 3028 3029 /* 3030 * host status block 3031 */ 3032 struct host_hc_status_block_e1x { 3033 struct hc_status_block_e1x sb; 3034 }; 3035 3036 3037 /* 3038 * 3 lines. status block 3039 */ 3040 struct hc_status_block_e2 { 3041 __le16 index_values[HC_SB_MAX_INDICES_E2]; 3042 __le16 running_index[HC_SB_MAX_SM]; 3043 __le32 reserved[11]; 3044 }; 3045 3046 /* 3047 * host status block 3048 */ 3049 struct host_hc_status_block_e2 { 3050 struct hc_status_block_e2 sb; 3051 }; 3052 3053 3054 /* 3055 * 5 lines. slow-path status block 3056 */ 3057 struct hc_sp_status_block { 3058 __le16 index_values[HC_SP_SB_MAX_INDICES]; 3059 __le16 running_index; 3060 __le16 rsrv; 3061 u32 rsrv1; 3062 }; 3063 3064 /* 3065 * host status block 3066 */ 3067 struct host_sp_status_block { 3068 struct atten_sp_status_block atten_status_block; 3069 struct hc_sp_status_block sp_sb; 3070 }; 3071 3072 3073 /* 3074 * IGU driver acknowledgment register 3075 */ 3076 struct igu_ack_register { 3077 #if defined(__BIG_ENDIAN) 3078 u16 sb_id_and_flags; 3079 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0) 3080 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0 3081 #define IGU_ACK_REGISTER_STORM_ID (0x7<<5) 3082 #define IGU_ACK_REGISTER_STORM_ID_SHIFT 5 3083 #define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8) 3084 #define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8 3085 #define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9) 3086 #define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9 3087 #define IGU_ACK_REGISTER_RESERVED (0x1F<<11) 3088 #define IGU_ACK_REGISTER_RESERVED_SHIFT 11 3089 u16 status_block_index; 3090 #elif defined(__LITTLE_ENDIAN) 3091 u16 status_block_index; 3092 u16 sb_id_and_flags; 3093 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0) 3094 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0 3095 #define IGU_ACK_REGISTER_STORM_ID (0x7<<5) 3096 #define IGU_ACK_REGISTER_STORM_ID_SHIFT 5 3097 #define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8) 3098 #define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8 3099 #define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9) 3100 #define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9 3101 #define IGU_ACK_REGISTER_RESERVED (0x1F<<11) 3102 #define IGU_ACK_REGISTER_RESERVED_SHIFT 11 3103 #endif 3104 }; 3105 3106 3107 /* 3108 * IGU driver acknowledgement register 3109 */ 3110 struct igu_backward_compatible { 3111 u32 sb_id_and_flags; 3112 #define IGU_BACKWARD_COMPATIBLE_SB_INDEX (0xFFFF<<0) 3113 #define IGU_BACKWARD_COMPATIBLE_SB_INDEX_SHIFT 0 3114 #define IGU_BACKWARD_COMPATIBLE_SB_SELECT (0x1F<<16) 3115 #define IGU_BACKWARD_COMPATIBLE_SB_SELECT_SHIFT 16 3116 #define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS (0x7<<21) 3117 #define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS_SHIFT 21 3118 #define IGU_BACKWARD_COMPATIBLE_BUPDATE (0x1<<24) 3119 #define IGU_BACKWARD_COMPATIBLE_BUPDATE_SHIFT 24 3120 #define IGU_BACKWARD_COMPATIBLE_ENABLE_INT (0x3<<25) 3121 #define IGU_BACKWARD_COMPATIBLE_ENABLE_INT_SHIFT 25 3122 #define IGU_BACKWARD_COMPATIBLE_RESERVED_0 (0x1F<<27) 3123 #define IGU_BACKWARD_COMPATIBLE_RESERVED_0_SHIFT 27 3124 u32 reserved_2; 3125 }; 3126 3127 3128 /* 3129 * IGU driver acknowledgement register 3130 */ 3131 struct igu_regular { 3132 u32 sb_id_and_flags; 3133 #define IGU_REGULAR_SB_INDEX (0xFFFFF<<0) 3134 #define IGU_REGULAR_SB_INDEX_SHIFT 0 3135 #define IGU_REGULAR_RESERVED0 (0x1<<20) 3136 #define IGU_REGULAR_RESERVED0_SHIFT 20 3137 #define IGU_REGULAR_SEGMENT_ACCESS (0x7<<21) 3138 #define IGU_REGULAR_SEGMENT_ACCESS_SHIFT 21 3139 #define IGU_REGULAR_BUPDATE (0x1<<24) 3140 #define IGU_REGULAR_BUPDATE_SHIFT 24 3141 #define IGU_REGULAR_ENABLE_INT (0x3<<25) 3142 #define IGU_REGULAR_ENABLE_INT_SHIFT 25 3143 #define IGU_REGULAR_RESERVED_1 (0x1<<27) 3144 #define IGU_REGULAR_RESERVED_1_SHIFT 27 3145 #define IGU_REGULAR_CLEANUP_TYPE (0x3<<28) 3146 #define IGU_REGULAR_CLEANUP_TYPE_SHIFT 28 3147 #define IGU_REGULAR_CLEANUP_SET (0x1<<30) 3148 #define IGU_REGULAR_CLEANUP_SET_SHIFT 30 3149 #define IGU_REGULAR_BCLEANUP (0x1<<31) 3150 #define IGU_REGULAR_BCLEANUP_SHIFT 31 3151 u32 reserved_2; 3152 }; 3153 3154 /* 3155 * IGU driver acknowledgement register 3156 */ 3157 union igu_consprod_reg { 3158 struct igu_regular regular; 3159 struct igu_backward_compatible backward_compatible; 3160 }; 3161 3162 3163 /* 3164 * Igu control commands 3165 */ 3166 enum igu_ctrl_cmd { 3167 IGU_CTRL_CMD_TYPE_RD, 3168 IGU_CTRL_CMD_TYPE_WR, 3169 MAX_IGU_CTRL_CMD 3170 }; 3171 3172 3173 /* 3174 * Control register for the IGU command register 3175 */ 3176 struct igu_ctrl_reg { 3177 u32 ctrl_data; 3178 #define IGU_CTRL_REG_ADDRESS (0xFFF<<0) 3179 #define IGU_CTRL_REG_ADDRESS_SHIFT 0 3180 #define IGU_CTRL_REG_FID (0x7F<<12) 3181 #define IGU_CTRL_REG_FID_SHIFT 12 3182 #define IGU_CTRL_REG_RESERVED (0x1<<19) 3183 #define IGU_CTRL_REG_RESERVED_SHIFT 19 3184 #define IGU_CTRL_REG_TYPE (0x1<<20) 3185 #define IGU_CTRL_REG_TYPE_SHIFT 20 3186 #define IGU_CTRL_REG_UNUSED (0x7FF<<21) 3187 #define IGU_CTRL_REG_UNUSED_SHIFT 21 3188 }; 3189 3190 3191 /* 3192 * Igu interrupt command 3193 */ 3194 enum igu_int_cmd { 3195 IGU_INT_ENABLE, 3196 IGU_INT_DISABLE, 3197 IGU_INT_NOP, 3198 IGU_INT_NOP2, 3199 MAX_IGU_INT_CMD 3200 }; 3201 3202 3203 /* 3204 * Igu segments 3205 */ 3206 enum igu_seg_access { 3207 IGU_SEG_ACCESS_NORM, 3208 IGU_SEG_ACCESS_DEF, 3209 IGU_SEG_ACCESS_ATTN, 3210 MAX_IGU_SEG_ACCESS 3211 }; 3212 3213 3214 /* 3215 * Parser parsing flags field 3216 */ 3217 struct parsing_flags { 3218 __le16 flags; 3219 #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE (0x1<<0) 3220 #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE_SHIFT 0 3221 #define PARSING_FLAGS_VLAN (0x1<<1) 3222 #define PARSING_FLAGS_VLAN_SHIFT 1 3223 #define PARSING_FLAGS_EXTRA_VLAN (0x1<<2) 3224 #define PARSING_FLAGS_EXTRA_VLAN_SHIFT 2 3225 #define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL (0x3<<3) 3226 #define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT 3 3227 #define PARSING_FLAGS_IP_OPTIONS (0x1<<5) 3228 #define PARSING_FLAGS_IP_OPTIONS_SHIFT 5 3229 #define PARSING_FLAGS_FRAGMENTATION_STATUS (0x1<<6) 3230 #define PARSING_FLAGS_FRAGMENTATION_STATUS_SHIFT 6 3231 #define PARSING_FLAGS_OVER_IP_PROTOCOL (0x3<<7) 3232 #define PARSING_FLAGS_OVER_IP_PROTOCOL_SHIFT 7 3233 #define PARSING_FLAGS_PURE_ACK_INDICATION (0x1<<9) 3234 #define PARSING_FLAGS_PURE_ACK_INDICATION_SHIFT 9 3235 #define PARSING_FLAGS_TCP_OPTIONS_EXIST (0x1<<10) 3236 #define PARSING_FLAGS_TCP_OPTIONS_EXIST_SHIFT 10 3237 #define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG (0x1<<11) 3238 #define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG_SHIFT 11 3239 #define PARSING_FLAGS_CONNECTION_MATCH (0x1<<12) 3240 #define PARSING_FLAGS_CONNECTION_MATCH_SHIFT 12 3241 #define PARSING_FLAGS_LLC_SNAP (0x1<<13) 3242 #define PARSING_FLAGS_LLC_SNAP_SHIFT 13 3243 #define PARSING_FLAGS_RESERVED0 (0x3<<14) 3244 #define PARSING_FLAGS_RESERVED0_SHIFT 14 3245 }; 3246 3247 3248 /* 3249 * Parsing flags for TCP ACK type 3250 */ 3251 enum prs_flags_ack_type { 3252 PRS_FLAG_PUREACK_PIGGY, 3253 PRS_FLAG_PUREACK_PURE, 3254 MAX_PRS_FLAGS_ACK_TYPE 3255 }; 3256 3257 3258 /* 3259 * Parsing flags for Ethernet address type 3260 */ 3261 enum prs_flags_eth_addr_type { 3262 PRS_FLAG_ETHTYPE_NON_UNICAST, 3263 PRS_FLAG_ETHTYPE_UNICAST, 3264 MAX_PRS_FLAGS_ETH_ADDR_TYPE 3265 }; 3266 3267 3268 /* 3269 * Parsing flags for over-ethernet protocol 3270 */ 3271 enum prs_flags_over_eth { 3272 PRS_FLAG_OVERETH_UNKNOWN, 3273 PRS_FLAG_OVERETH_IPV4, 3274 PRS_FLAG_OVERETH_IPV6, 3275 PRS_FLAG_OVERETH_LLCSNAP_UNKNOWN, 3276 MAX_PRS_FLAGS_OVER_ETH 3277 }; 3278 3279 3280 /* 3281 * Parsing flags for over-IP protocol 3282 */ 3283 enum prs_flags_over_ip { 3284 PRS_FLAG_OVERIP_UNKNOWN, 3285 PRS_FLAG_OVERIP_TCP, 3286 PRS_FLAG_OVERIP_UDP, 3287 MAX_PRS_FLAGS_OVER_IP 3288 }; 3289 3290 3291 /* 3292 * SDM operation gen command (generate aggregative interrupt) 3293 */ 3294 struct sdm_op_gen { 3295 __le32 command; 3296 #define SDM_OP_GEN_COMP_PARAM (0x1F<<0) 3297 #define SDM_OP_GEN_COMP_PARAM_SHIFT 0 3298 #define SDM_OP_GEN_COMP_TYPE (0x7<<5) 3299 #define SDM_OP_GEN_COMP_TYPE_SHIFT 5 3300 #define SDM_OP_GEN_AGG_VECT_IDX (0xFF<<8) 3301 #define SDM_OP_GEN_AGG_VECT_IDX_SHIFT 8 3302 #define SDM_OP_GEN_AGG_VECT_IDX_VALID (0x1<<16) 3303 #define SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT 16 3304 #define SDM_OP_GEN_RESERVED (0x7FFF<<17) 3305 #define SDM_OP_GEN_RESERVED_SHIFT 17 3306 }; 3307 3308 3309 /* 3310 * Timers connection context 3311 */ 3312 struct timers_block_context { 3313 u32 __reserved_0; 3314 u32 __reserved_1; 3315 u32 __reserved_2; 3316 u32 flags; 3317 #define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS (0x3<<0) 3318 #define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS_SHIFT 0 3319 #define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG (0x1<<2) 3320 #define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG_SHIFT 2 3321 #define __TIMERS_BLOCK_CONTEXT_RESERVED0 (0x1FFFFFFF<<3) 3322 #define __TIMERS_BLOCK_CONTEXT_RESERVED0_SHIFT 3 3323 }; 3324 3325 3326 /* 3327 * The eth aggregative context of Tstorm 3328 */ 3329 struct tstorm_eth_ag_context { 3330 u32 __reserved0[14]; 3331 }; 3332 3333 3334 /* 3335 * The eth aggregative context of Ustorm 3336 */ 3337 struct ustorm_eth_ag_context { 3338 u32 __reserved0; 3339 #if defined(__BIG_ENDIAN) 3340 u8 cdu_usage; 3341 u8 __reserved2; 3342 u16 __reserved1; 3343 #elif defined(__LITTLE_ENDIAN) 3344 u16 __reserved1; 3345 u8 __reserved2; 3346 u8 cdu_usage; 3347 #endif 3348 u32 __reserved3[6]; 3349 }; 3350 3351 3352 /* 3353 * The eth aggregative context of Xstorm 3354 */ 3355 struct xstorm_eth_ag_context { 3356 u32 reserved0; 3357 #if defined(__BIG_ENDIAN) 3358 u8 cdu_reserved; 3359 u8 reserved2; 3360 u16 reserved1; 3361 #elif defined(__LITTLE_ENDIAN) 3362 u16 reserved1; 3363 u8 reserved2; 3364 u8 cdu_reserved; 3365 #endif 3366 u32 reserved3[30]; 3367 }; 3368 3369 3370 /* 3371 * doorbell message sent to the chip 3372 */ 3373 struct doorbell { 3374 #if defined(__BIG_ENDIAN) 3375 u16 zero_fill2; 3376 u8 zero_fill1; 3377 struct doorbell_hdr header; 3378 #elif defined(__LITTLE_ENDIAN) 3379 struct doorbell_hdr header; 3380 u8 zero_fill1; 3381 u16 zero_fill2; 3382 #endif 3383 }; 3384 3385 3386 /* 3387 * doorbell message sent to the chip 3388 */ 3389 struct doorbell_set_prod { 3390 #if defined(__BIG_ENDIAN) 3391 u16 prod; 3392 u8 zero_fill1; 3393 struct doorbell_hdr header; 3394 #elif defined(__LITTLE_ENDIAN) 3395 struct doorbell_hdr header; 3396 u8 zero_fill1; 3397 u16 prod; 3398 #endif 3399 }; 3400 3401 3402 struct regpair { 3403 __le32 lo; 3404 __le32 hi; 3405 }; 3406 3407 struct regpair_native { 3408 u32 lo; 3409 u32 hi; 3410 }; 3411 3412 /* 3413 * Classify rule opcodes in E2/E3 3414 */ 3415 enum classify_rule { 3416 CLASSIFY_RULE_OPCODE_MAC, 3417 CLASSIFY_RULE_OPCODE_VLAN, 3418 CLASSIFY_RULE_OPCODE_PAIR, 3419 MAX_CLASSIFY_RULE 3420 }; 3421 3422 3423 /* 3424 * Classify rule types in E2/E3 3425 */ 3426 enum classify_rule_action_type { 3427 CLASSIFY_RULE_REMOVE, 3428 CLASSIFY_RULE_ADD, 3429 MAX_CLASSIFY_RULE_ACTION_TYPE 3430 }; 3431 3432 3433 /* 3434 * client init ramrod data 3435 */ 3436 struct client_init_general_data { 3437 u8 client_id; 3438 u8 statistics_counter_id; 3439 u8 statistics_en_flg; 3440 u8 is_fcoe_flg; 3441 u8 activate_flg; 3442 u8 sp_client_id; 3443 __le16 mtu; 3444 u8 statistics_zero_flg; 3445 u8 func_id; 3446 u8 cos; 3447 u8 traffic_type; 3448 u32 reserved0; 3449 }; 3450 3451 3452 /* 3453 * client init rx data 3454 */ 3455 struct client_init_rx_data { 3456 u8 tpa_en; 3457 #define CLIENT_INIT_RX_DATA_TPA_EN_IPV4 (0x1<<0) 3458 #define CLIENT_INIT_RX_DATA_TPA_EN_IPV4_SHIFT 0 3459 #define CLIENT_INIT_RX_DATA_TPA_EN_IPV6 (0x1<<1) 3460 #define CLIENT_INIT_RX_DATA_TPA_EN_IPV6_SHIFT 1 3461 #define CLIENT_INIT_RX_DATA_TPA_MODE (0x1<<2) 3462 #define CLIENT_INIT_RX_DATA_TPA_MODE_SHIFT 2 3463 #define CLIENT_INIT_RX_DATA_RESERVED5 (0x1F<<3) 3464 #define CLIENT_INIT_RX_DATA_RESERVED5_SHIFT 3 3465 u8 vmqueue_mode_en_flg; 3466 u8 extra_data_over_sgl_en_flg; 3467 u8 cache_line_alignment_log_size; 3468 u8 enable_dynamic_hc; 3469 u8 max_sges_for_packet; 3470 u8 client_qzone_id; 3471 u8 drop_ip_cs_err_flg; 3472 u8 drop_tcp_cs_err_flg; 3473 u8 drop_ttl0_flg; 3474 u8 drop_udp_cs_err_flg; 3475 u8 inner_vlan_removal_enable_flg; 3476 u8 outer_vlan_removal_enable_flg; 3477 u8 status_block_id; 3478 u8 rx_sb_index_number; 3479 u8 dont_verify_rings_pause_thr_flg; 3480 u8 max_tpa_queues; 3481 u8 silent_vlan_removal_flg; 3482 __le16 max_bytes_on_bd; 3483 __le16 sge_buff_size; 3484 u8 approx_mcast_engine_id; 3485 u8 rss_engine_id; 3486 struct regpair bd_page_base; 3487 struct regpair sge_page_base; 3488 struct regpair cqe_page_base; 3489 u8 is_leading_rss; 3490 u8 is_approx_mcast; 3491 __le16 max_agg_size; 3492 __le16 state; 3493 #define CLIENT_INIT_RX_DATA_UCAST_DROP_ALL (0x1<<0) 3494 #define CLIENT_INIT_RX_DATA_UCAST_DROP_ALL_SHIFT 0 3495 #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL (0x1<<1) 3496 #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL_SHIFT 1 3497 #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED (0x1<<2) 3498 #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED_SHIFT 2 3499 #define CLIENT_INIT_RX_DATA_MCAST_DROP_ALL (0x1<<3) 3500 #define CLIENT_INIT_RX_DATA_MCAST_DROP_ALL_SHIFT 3 3501 #define CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL (0x1<<4) 3502 #define CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL_SHIFT 4 3503 #define CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL (0x1<<5) 3504 #define CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL_SHIFT 5 3505 #define CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN (0x1<<6) 3506 #define CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN_SHIFT 6 3507 #define CLIENT_INIT_RX_DATA_RESERVED2 (0x1FF<<7) 3508 #define CLIENT_INIT_RX_DATA_RESERVED2_SHIFT 7 3509 __le16 cqe_pause_thr_low; 3510 __le16 cqe_pause_thr_high; 3511 __le16 bd_pause_thr_low; 3512 __le16 bd_pause_thr_high; 3513 __le16 sge_pause_thr_low; 3514 __le16 sge_pause_thr_high; 3515 __le16 rx_cos_mask; 3516 __le16 silent_vlan_value; 3517 __le16 silent_vlan_mask; 3518 __le32 reserved6[2]; 3519 }; 3520 3521 /* 3522 * client init tx data 3523 */ 3524 struct client_init_tx_data { 3525 u8 enforce_security_flg; 3526 u8 tx_status_block_id; 3527 u8 tx_sb_index_number; 3528 u8 tss_leading_client_id; 3529 u8 tx_switching_flg; 3530 u8 anti_spoofing_flg; 3531 __le16 default_vlan; 3532 struct regpair tx_bd_page_base; 3533 __le16 state; 3534 #define CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL (0x1<<0) 3535 #define CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL_SHIFT 0 3536 #define CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL (0x1<<1) 3537 #define CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL_SHIFT 1 3538 #define CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL (0x1<<2) 3539 #define CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL_SHIFT 2 3540 #define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN (0x1<<3) 3541 #define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN_SHIFT 3 3542 #define CLIENT_INIT_TX_DATA_RESERVED0 (0xFFF<<4) 3543 #define CLIENT_INIT_TX_DATA_RESERVED0_SHIFT 4 3544 u8 default_vlan_flg; 3545 u8 force_default_pri_flg; 3546 u8 tunnel_lso_inc_ip_id; 3547 u8 refuse_outband_vlan_flg; 3548 u8 tunnel_non_lso_pcsum_location; 3549 u8 reserved1; 3550 }; 3551 3552 /* 3553 * client init ramrod data 3554 */ 3555 struct client_init_ramrod_data { 3556 struct client_init_general_data general; 3557 struct client_init_rx_data rx; 3558 struct client_init_tx_data tx; 3559 }; 3560 3561 3562 /* 3563 * client update ramrod data 3564 */ 3565 struct client_update_ramrod_data { 3566 u8 client_id; 3567 u8 func_id; 3568 u8 inner_vlan_removal_enable_flg; 3569 u8 inner_vlan_removal_change_flg; 3570 u8 outer_vlan_removal_enable_flg; 3571 u8 outer_vlan_removal_change_flg; 3572 u8 anti_spoofing_enable_flg; 3573 u8 anti_spoofing_change_flg; 3574 u8 activate_flg; 3575 u8 activate_change_flg; 3576 __le16 default_vlan; 3577 u8 default_vlan_enable_flg; 3578 u8 default_vlan_change_flg; 3579 __le16 silent_vlan_value; 3580 __le16 silent_vlan_mask; 3581 u8 silent_vlan_removal_flg; 3582 u8 silent_vlan_change_flg; 3583 u8 refuse_outband_vlan_flg; 3584 u8 refuse_outband_vlan_change_flg; 3585 u8 tx_switching_flg; 3586 u8 tx_switching_change_flg; 3587 __le32 reserved1; 3588 __le32 echo; 3589 }; 3590 3591 3592 /* 3593 * The eth storm context of Cstorm 3594 */ 3595 struct cstorm_eth_st_context { 3596 u32 __reserved0[4]; 3597 }; 3598 3599 3600 struct double_regpair { 3601 u32 regpair0_lo; 3602 u32 regpair0_hi; 3603 u32 regpair1_lo; 3604 u32 regpair1_hi; 3605 }; 3606 3607 3608 /* 3609 * Ethernet address typesm used in ethernet tx BDs 3610 */ 3611 enum eth_addr_type { 3612 UNKNOWN_ADDRESS, 3613 UNICAST_ADDRESS, 3614 MULTICAST_ADDRESS, 3615 BROADCAST_ADDRESS, 3616 MAX_ETH_ADDR_TYPE 3617 }; 3618 3619 3620 /* 3621 * 3622 */ 3623 struct eth_classify_cmd_header { 3624 u8 cmd_general_data; 3625 #define ETH_CLASSIFY_CMD_HEADER_RX_CMD (0x1<<0) 3626 #define ETH_CLASSIFY_CMD_HEADER_RX_CMD_SHIFT 0 3627 #define ETH_CLASSIFY_CMD_HEADER_TX_CMD (0x1<<1) 3628 #define ETH_CLASSIFY_CMD_HEADER_TX_CMD_SHIFT 1 3629 #define ETH_CLASSIFY_CMD_HEADER_OPCODE (0x3<<2) 3630 #define ETH_CLASSIFY_CMD_HEADER_OPCODE_SHIFT 2 3631 #define ETH_CLASSIFY_CMD_HEADER_IS_ADD (0x1<<4) 3632 #define ETH_CLASSIFY_CMD_HEADER_IS_ADD_SHIFT 4 3633 #define ETH_CLASSIFY_CMD_HEADER_RESERVED0 (0x7<<5) 3634 #define ETH_CLASSIFY_CMD_HEADER_RESERVED0_SHIFT 5 3635 u8 func_id; 3636 u8 client_id; 3637 u8 reserved1; 3638 }; 3639 3640 3641 /* 3642 * header for eth classification config ramrod 3643 */ 3644 struct eth_classify_header { 3645 u8 rule_cnt; 3646 u8 reserved0; 3647 __le16 reserved1; 3648 __le32 echo; 3649 }; 3650 3651 3652 /* 3653 * Command for adding/removing a MAC classification rule 3654 */ 3655 struct eth_classify_mac_cmd { 3656 struct eth_classify_cmd_header header; 3657 __le16 reserved0; 3658 __le16 inner_mac; 3659 __le16 mac_lsb; 3660 __le16 mac_mid; 3661 __le16 mac_msb; 3662 __le16 reserved1; 3663 }; 3664 3665 3666 /* 3667 * Command for adding/removing a MAC-VLAN pair classification rule 3668 */ 3669 struct eth_classify_pair_cmd { 3670 struct eth_classify_cmd_header header; 3671 __le16 reserved0; 3672 __le16 inner_mac; 3673 __le16 mac_lsb; 3674 __le16 mac_mid; 3675 __le16 mac_msb; 3676 __le16 vlan; 3677 }; 3678 3679 3680 /* 3681 * Command for adding/removing a VLAN classification rule 3682 */ 3683 struct eth_classify_vlan_cmd { 3684 struct eth_classify_cmd_header header; 3685 __le32 reserved0; 3686 __le32 reserved1; 3687 __le16 reserved2; 3688 __le16 vlan; 3689 }; 3690 3691 /* 3692 * union for eth classification rule 3693 */ 3694 union eth_classify_rule_cmd { 3695 struct eth_classify_mac_cmd mac; 3696 struct eth_classify_vlan_cmd vlan; 3697 struct eth_classify_pair_cmd pair; 3698 }; 3699 3700 /* 3701 * parameters for eth classification configuration ramrod 3702 */ 3703 struct eth_classify_rules_ramrod_data { 3704 struct eth_classify_header header; 3705 union eth_classify_rule_cmd rules[CLASSIFY_RULES_COUNT]; 3706 }; 3707 3708 3709 /* 3710 * The data contain client ID need to the ramrod 3711 */ 3712 struct eth_common_ramrod_data { 3713 __le32 client_id; 3714 __le32 reserved1; 3715 }; 3716 3717 3718 /* 3719 * The eth storm context of Ustorm 3720 */ 3721 struct ustorm_eth_st_context { 3722 u32 reserved0[52]; 3723 }; 3724 3725 /* 3726 * The eth storm context of Tstorm 3727 */ 3728 struct tstorm_eth_st_context { 3729 u32 __reserved0[28]; 3730 }; 3731 3732 /* 3733 * The eth storm context of Xstorm 3734 */ 3735 struct xstorm_eth_st_context { 3736 u32 reserved0[60]; 3737 }; 3738 3739 /* 3740 * Ethernet connection context 3741 */ 3742 struct eth_context { 3743 struct ustorm_eth_st_context ustorm_st_context; 3744 struct tstorm_eth_st_context tstorm_st_context; 3745 struct xstorm_eth_ag_context xstorm_ag_context; 3746 struct tstorm_eth_ag_context tstorm_ag_context; 3747 struct cstorm_eth_ag_context cstorm_ag_context; 3748 struct ustorm_eth_ag_context ustorm_ag_context; 3749 struct timers_block_context timers_context; 3750 struct xstorm_eth_st_context xstorm_st_context; 3751 struct cstorm_eth_st_context cstorm_st_context; 3752 }; 3753 3754 3755 /* 3756 * union for sgl and raw data. 3757 */ 3758 union eth_sgl_or_raw_data { 3759 __le16 sgl[8]; 3760 u32 raw_data[4]; 3761 }; 3762 3763 /* 3764 * eth FP end aggregation CQE parameters struct 3765 */ 3766 struct eth_end_agg_rx_cqe { 3767 u8 type_error_flags; 3768 #define ETH_END_AGG_RX_CQE_TYPE (0x3<<0) 3769 #define ETH_END_AGG_RX_CQE_TYPE_SHIFT 0 3770 #define ETH_END_AGG_RX_CQE_SGL_RAW_SEL (0x1<<2) 3771 #define ETH_END_AGG_RX_CQE_SGL_RAW_SEL_SHIFT 2 3772 #define ETH_END_AGG_RX_CQE_RESERVED0 (0x1F<<3) 3773 #define ETH_END_AGG_RX_CQE_RESERVED0_SHIFT 3 3774 u8 reserved1; 3775 u8 queue_index; 3776 u8 reserved2; 3777 __le32 timestamp_delta; 3778 __le16 num_of_coalesced_segs; 3779 __le16 pkt_len; 3780 u8 pure_ack_count; 3781 u8 reserved3; 3782 __le16 reserved4; 3783 union eth_sgl_or_raw_data sgl_or_raw_data; 3784 __le32 reserved5[8]; 3785 }; 3786 3787 3788 /* 3789 * regular eth FP CQE parameters struct 3790 */ 3791 struct eth_fast_path_rx_cqe { 3792 u8 type_error_flags; 3793 #define ETH_FAST_PATH_RX_CQE_TYPE (0x3<<0) 3794 #define ETH_FAST_PATH_RX_CQE_TYPE_SHIFT 0 3795 #define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL (0x1<<2) 3796 #define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL_SHIFT 2 3797 #define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG (0x1<<3) 3798 #define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG_SHIFT 3 3799 #define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG (0x1<<4) 3800 #define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG_SHIFT 4 3801 #define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG (0x1<<5) 3802 #define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG_SHIFT 5 3803 #define ETH_FAST_PATH_RX_CQE_RESERVED0 (0x3<<6) 3804 #define ETH_FAST_PATH_RX_CQE_RESERVED0_SHIFT 6 3805 u8 status_flags; 3806 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE (0x7<<0) 3807 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE_SHIFT 0 3808 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG (0x1<<3) 3809 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG_SHIFT 3 3810 #define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG (0x1<<4) 3811 #define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG_SHIFT 4 3812 #define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG (0x1<<5) 3813 #define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG_SHIFT 5 3814 #define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG (0x1<<6) 3815 #define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG_SHIFT 6 3816 #define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG (0x1<<7) 3817 #define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG_SHIFT 7 3818 u8 queue_index; 3819 u8 placement_offset; 3820 __le32 rss_hash_result; 3821 __le16 vlan_tag; 3822 __le16 pkt_len_or_gro_seg_len; 3823 __le16 len_on_bd; 3824 struct parsing_flags pars_flags; 3825 union eth_sgl_or_raw_data sgl_or_raw_data; 3826 __le32 reserved1[7]; 3827 u32 marker; 3828 }; 3829 3830 3831 /* 3832 * Command for setting classification flags for a client 3833 */ 3834 struct eth_filter_rules_cmd { 3835 u8 cmd_general_data; 3836 #define ETH_FILTER_RULES_CMD_RX_CMD (0x1<<0) 3837 #define ETH_FILTER_RULES_CMD_RX_CMD_SHIFT 0 3838 #define ETH_FILTER_RULES_CMD_TX_CMD (0x1<<1) 3839 #define ETH_FILTER_RULES_CMD_TX_CMD_SHIFT 1 3840 #define ETH_FILTER_RULES_CMD_RESERVED0 (0x3F<<2) 3841 #define ETH_FILTER_RULES_CMD_RESERVED0_SHIFT 2 3842 u8 func_id; 3843 u8 client_id; 3844 u8 reserved1; 3845 __le16 state; 3846 #define ETH_FILTER_RULES_CMD_UCAST_DROP_ALL (0x1<<0) 3847 #define ETH_FILTER_RULES_CMD_UCAST_DROP_ALL_SHIFT 0 3848 #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL (0x1<<1) 3849 #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL_SHIFT 1 3850 #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED (0x1<<2) 3851 #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED_SHIFT 2 3852 #define ETH_FILTER_RULES_CMD_MCAST_DROP_ALL (0x1<<3) 3853 #define ETH_FILTER_RULES_CMD_MCAST_DROP_ALL_SHIFT 3 3854 #define ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL (0x1<<4) 3855 #define ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL_SHIFT 4 3856 #define ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL (0x1<<5) 3857 #define ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL_SHIFT 5 3858 #define ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN (0x1<<6) 3859 #define ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN_SHIFT 6 3860 #define ETH_FILTER_RULES_CMD_RESERVED2 (0x1FF<<7) 3861 #define ETH_FILTER_RULES_CMD_RESERVED2_SHIFT 7 3862 __le16 reserved3; 3863 struct regpair reserved4; 3864 }; 3865 3866 3867 /* 3868 * parameters for eth classification filters ramrod 3869 */ 3870 struct eth_filter_rules_ramrod_data { 3871 struct eth_classify_header header; 3872 struct eth_filter_rules_cmd rules[FILTER_RULES_COUNT]; 3873 }; 3874 3875 3876 /* 3877 * parameters for eth classification configuration ramrod 3878 */ 3879 struct eth_general_rules_ramrod_data { 3880 struct eth_classify_header header; 3881 union eth_classify_rule_cmd rules[CLASSIFY_RULES_COUNT]; 3882 }; 3883 3884 3885 /* 3886 * The data for Halt ramrod 3887 */ 3888 struct eth_halt_ramrod_data { 3889 __le32 client_id; 3890 __le32 reserved0; 3891 }; 3892 3893 3894 /* 3895 * destination and source mac address. 3896 */ 3897 struct eth_mac_addresses { 3898 #if defined(__BIG_ENDIAN) 3899 __le16 dst_mid; 3900 __le16 dst_lo; 3901 #elif defined(__LITTLE_ENDIAN) 3902 __le16 dst_lo; 3903 __le16 dst_mid; 3904 #endif 3905 #if defined(__BIG_ENDIAN) 3906 __le16 src_lo; 3907 __le16 dst_hi; 3908 #elif defined(__LITTLE_ENDIAN) 3909 __le16 dst_hi; 3910 __le16 src_lo; 3911 #endif 3912 #if defined(__BIG_ENDIAN) 3913 __le16 src_hi; 3914 __le16 src_mid; 3915 #elif defined(__LITTLE_ENDIAN) 3916 __le16 src_mid; 3917 __le16 src_hi; 3918 #endif 3919 }; 3920 3921 /* tunneling related data */ 3922 struct eth_tunnel_data { 3923 #if defined(__BIG_ENDIAN) 3924 __le16 dst_mid; 3925 __le16 dst_lo; 3926 #elif defined(__LITTLE_ENDIAN) 3927 __le16 dst_lo; 3928 __le16 dst_mid; 3929 #endif 3930 #if defined(__BIG_ENDIAN) 3931 __le16 reserved0; 3932 __le16 dst_hi; 3933 #elif defined(__LITTLE_ENDIAN) 3934 __le16 dst_hi; 3935 __le16 reserved0; 3936 #endif 3937 #if defined(__BIG_ENDIAN) 3938 u8 reserved1; 3939 u8 ip_hdr_start_inner_w; 3940 __le16 pseudo_csum; 3941 #elif defined(__LITTLE_ENDIAN) 3942 __le16 pseudo_csum; 3943 u8 ip_hdr_start_inner_w; 3944 u8 reserved1; 3945 #endif 3946 }; 3947 3948 /* union for mac addresses and for tunneling data. 3949 * considered as tunneling data only if (tunnel_exist == 1). 3950 */ 3951 union eth_mac_addr_or_tunnel_data { 3952 struct eth_mac_addresses mac_addr; 3953 struct eth_tunnel_data tunnel_data; 3954 }; 3955 3956 /*Command for setting multicast classification for a client */ 3957 struct eth_multicast_rules_cmd { 3958 u8 cmd_general_data; 3959 #define ETH_MULTICAST_RULES_CMD_RX_CMD (0x1<<0) 3960 #define ETH_MULTICAST_RULES_CMD_RX_CMD_SHIFT 0 3961 #define ETH_MULTICAST_RULES_CMD_TX_CMD (0x1<<1) 3962 #define ETH_MULTICAST_RULES_CMD_TX_CMD_SHIFT 1 3963 #define ETH_MULTICAST_RULES_CMD_IS_ADD (0x1<<2) 3964 #define ETH_MULTICAST_RULES_CMD_IS_ADD_SHIFT 2 3965 #define ETH_MULTICAST_RULES_CMD_RESERVED0 (0x1F<<3) 3966 #define ETH_MULTICAST_RULES_CMD_RESERVED0_SHIFT 3 3967 u8 func_id; 3968 u8 bin_id; 3969 u8 engine_id; 3970 __le32 reserved2; 3971 struct regpair reserved3; 3972 }; 3973 3974 /* 3975 * parameters for multicast classification ramrod 3976 */ 3977 struct eth_multicast_rules_ramrod_data { 3978 struct eth_classify_header header; 3979 struct eth_multicast_rules_cmd rules[MULTICAST_RULES_COUNT]; 3980 }; 3981 3982 /* 3983 * Place holder for ramrods protocol specific data 3984 */ 3985 struct ramrod_data { 3986 __le32 data_lo; 3987 __le32 data_hi; 3988 }; 3989 3990 /* 3991 * union for ramrod data for Ethernet protocol (CQE) (force size of 16 bits) 3992 */ 3993 union eth_ramrod_data { 3994 struct ramrod_data general; 3995 }; 3996 3997 3998 /* 3999 * RSS toeplitz hash type, as reported in CQE 4000 */ 4001 enum eth_rss_hash_type { 4002 DEFAULT_HASH_TYPE, 4003 IPV4_HASH_TYPE, 4004 TCP_IPV4_HASH_TYPE, 4005 IPV6_HASH_TYPE, 4006 TCP_IPV6_HASH_TYPE, 4007 VLAN_PRI_HASH_TYPE, 4008 E1HOV_PRI_HASH_TYPE, 4009 DSCP_HASH_TYPE, 4010 MAX_ETH_RSS_HASH_TYPE 4011 }; 4012 4013 4014 /* 4015 * Ethernet RSS mode 4016 */ 4017 enum eth_rss_mode { 4018 ETH_RSS_MODE_DISABLED, 4019 ETH_RSS_MODE_REGULAR, 4020 ETH_RSS_MODE_VLAN_PRI, 4021 ETH_RSS_MODE_E1HOV_PRI, 4022 ETH_RSS_MODE_IP_DSCP, 4023 MAX_ETH_RSS_MODE 4024 }; 4025 4026 4027 /* 4028 * parameters for RSS update ramrod (E2) 4029 */ 4030 struct eth_rss_update_ramrod_data { 4031 u8 rss_engine_id; 4032 u8 capabilities; 4033 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY (0x1<<0) 4034 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY_SHIFT 0 4035 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY (0x1<<1) 4036 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY_SHIFT 1 4037 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY (0x1<<2) 4038 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY_SHIFT 2 4039 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY (0x1<<3) 4040 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY_SHIFT 3 4041 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY (0x1<<4) 4042 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY_SHIFT 4 4043 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY (0x1<<5) 4044 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY_SHIFT 5 4045 #define ETH_RSS_UPDATE_RAMROD_DATA_EN_5_TUPLE_CAPABILITY (0x1<<6) 4046 #define ETH_RSS_UPDATE_RAMROD_DATA_EN_5_TUPLE_CAPABILITY_SHIFT 6 4047 #define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY (0x1<<7) 4048 #define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY_SHIFT 7 4049 u8 rss_result_mask; 4050 u8 rss_mode; 4051 __le16 udp_4tuple_dst_port_mask; 4052 __le16 udp_4tuple_dst_port_value; 4053 u8 indirection_table[T_ETH_INDIRECTION_TABLE_SIZE]; 4054 __le32 rss_key[T_ETH_RSS_KEY]; 4055 __le32 echo; 4056 __le32 reserved3; 4057 }; 4058 4059 4060 /* 4061 * The eth Rx Buffer Descriptor 4062 */ 4063 struct eth_rx_bd { 4064 __le32 addr_lo; 4065 __le32 addr_hi; 4066 }; 4067 4068 4069 /* 4070 * Eth Rx Cqe structure- general structure for ramrods 4071 */ 4072 struct common_ramrod_eth_rx_cqe { 4073 u8 ramrod_type; 4074 #define COMMON_RAMROD_ETH_RX_CQE_TYPE (0x3<<0) 4075 #define COMMON_RAMROD_ETH_RX_CQE_TYPE_SHIFT 0 4076 #define COMMON_RAMROD_ETH_RX_CQE_ERROR (0x1<<2) 4077 #define COMMON_RAMROD_ETH_RX_CQE_ERROR_SHIFT 2 4078 #define COMMON_RAMROD_ETH_RX_CQE_RESERVED0 (0x1F<<3) 4079 #define COMMON_RAMROD_ETH_RX_CQE_RESERVED0_SHIFT 3 4080 u8 conn_type; 4081 __le16 reserved1; 4082 __le32 conn_and_cmd_data; 4083 #define COMMON_RAMROD_ETH_RX_CQE_CID (0xFFFFFF<<0) 4084 #define COMMON_RAMROD_ETH_RX_CQE_CID_SHIFT 0 4085 #define COMMON_RAMROD_ETH_RX_CQE_CMD_ID (0xFF<<24) 4086 #define COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT 24 4087 struct ramrod_data protocol_data; 4088 __le32 echo; 4089 __le32 reserved2[11]; 4090 }; 4091 4092 /* 4093 * Rx Last CQE in page (in ETH) 4094 */ 4095 struct eth_rx_cqe_next_page { 4096 __le32 addr_lo; 4097 __le32 addr_hi; 4098 __le32 reserved[14]; 4099 }; 4100 4101 /* 4102 * union for all eth rx cqe types (fix their sizes) 4103 */ 4104 union eth_rx_cqe { 4105 struct eth_fast_path_rx_cqe fast_path_cqe; 4106 struct common_ramrod_eth_rx_cqe ramrod_cqe; 4107 struct eth_rx_cqe_next_page next_page_cqe; 4108 struct eth_end_agg_rx_cqe end_agg_cqe; 4109 }; 4110 4111 4112 /* 4113 * Values for RX ETH CQE type field 4114 */ 4115 enum eth_rx_cqe_type { 4116 RX_ETH_CQE_TYPE_ETH_FASTPATH, 4117 RX_ETH_CQE_TYPE_ETH_RAMROD, 4118 RX_ETH_CQE_TYPE_ETH_START_AGG, 4119 RX_ETH_CQE_TYPE_ETH_STOP_AGG, 4120 MAX_ETH_RX_CQE_TYPE 4121 }; 4122 4123 4124 /* 4125 * Type of SGL/Raw field in ETH RX fast path CQE 4126 */ 4127 enum eth_rx_fp_sel { 4128 ETH_FP_CQE_REGULAR, 4129 ETH_FP_CQE_RAW, 4130 MAX_ETH_RX_FP_SEL 4131 }; 4132 4133 4134 /* 4135 * The eth Rx SGE Descriptor 4136 */ 4137 struct eth_rx_sge { 4138 __le32 addr_lo; 4139 __le32 addr_hi; 4140 }; 4141 4142 4143 /* 4144 * common data for all protocols 4145 */ 4146 struct spe_hdr { 4147 __le32 conn_and_cmd_data; 4148 #define SPE_HDR_CID (0xFFFFFF<<0) 4149 #define SPE_HDR_CID_SHIFT 0 4150 #define SPE_HDR_CMD_ID (0xFF<<24) 4151 #define SPE_HDR_CMD_ID_SHIFT 24 4152 __le16 type; 4153 #define SPE_HDR_CONN_TYPE (0xFF<<0) 4154 #define SPE_HDR_CONN_TYPE_SHIFT 0 4155 #define SPE_HDR_FUNCTION_ID (0xFF<<8) 4156 #define SPE_HDR_FUNCTION_ID_SHIFT 8 4157 __le16 reserved1; 4158 }; 4159 4160 /* 4161 * specific data for ethernet slow path element 4162 */ 4163 union eth_specific_data { 4164 u8 protocol_data[8]; 4165 struct regpair client_update_ramrod_data; 4166 struct regpair client_init_ramrod_init_data; 4167 struct eth_halt_ramrod_data halt_ramrod_data; 4168 struct regpair update_data_addr; 4169 struct eth_common_ramrod_data common_ramrod_data; 4170 struct regpair classify_cfg_addr; 4171 struct regpair filter_cfg_addr; 4172 struct regpair mcast_cfg_addr; 4173 }; 4174 4175 /* 4176 * Ethernet slow path element 4177 */ 4178 struct eth_spe { 4179 struct spe_hdr hdr; 4180 union eth_specific_data data; 4181 }; 4182 4183 4184 /* 4185 * Ethernet command ID for slow path elements 4186 */ 4187 enum eth_spqe_cmd_id { 4188 RAMROD_CMD_ID_ETH_UNUSED, 4189 RAMROD_CMD_ID_ETH_CLIENT_SETUP, 4190 RAMROD_CMD_ID_ETH_HALT, 4191 RAMROD_CMD_ID_ETH_FORWARD_SETUP, 4192 RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP, 4193 RAMROD_CMD_ID_ETH_CLIENT_UPDATE, 4194 RAMROD_CMD_ID_ETH_EMPTY, 4195 RAMROD_CMD_ID_ETH_TERMINATE, 4196 RAMROD_CMD_ID_ETH_TPA_UPDATE, 4197 RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES, 4198 RAMROD_CMD_ID_ETH_FILTER_RULES, 4199 RAMROD_CMD_ID_ETH_MULTICAST_RULES, 4200 RAMROD_CMD_ID_ETH_RSS_UPDATE, 4201 RAMROD_CMD_ID_ETH_SET_MAC, 4202 MAX_ETH_SPQE_CMD_ID 4203 }; 4204 4205 4206 /* 4207 * eth tpa update command 4208 */ 4209 enum eth_tpa_update_command { 4210 TPA_UPDATE_NONE_COMMAND, 4211 TPA_UPDATE_ENABLE_COMMAND, 4212 TPA_UPDATE_DISABLE_COMMAND, 4213 MAX_ETH_TPA_UPDATE_COMMAND 4214 }; 4215 4216 /* In case of LSO over IPv4 tunnel, whether to increment 4217 * IP ID on external IP header or internal IP header 4218 */ 4219 enum eth_tunnel_lso_inc_ip_id { 4220 EXT_HEADER, 4221 INT_HEADER, 4222 MAX_ETH_TUNNEL_LSO_INC_IP_ID 4223 }; 4224 4225 /* In case tunnel exist and L4 checksum offload, 4226 * the pseudo checksum location, on packet or on BD. 4227 */ 4228 enum eth_tunnel_non_lso_pcsum_location { 4229 PCSUM_ON_PKT, 4230 PCSUM_ON_BD, 4231 MAX_ETH_TUNNEL_NON_LSO_PCSUM_LOCATION 4232 }; 4233 4234 /* 4235 * Tx regular BD structure 4236 */ 4237 struct eth_tx_bd { 4238 __le32 addr_lo; 4239 __le32 addr_hi; 4240 __le16 total_pkt_bytes; 4241 __le16 nbytes; 4242 u8 reserved[4]; 4243 }; 4244 4245 4246 /* 4247 * structure for easy accessibility to assembler 4248 */ 4249 struct eth_tx_bd_flags { 4250 u8 as_bitfield; 4251 #define ETH_TX_BD_FLAGS_IP_CSUM (0x1<<0) 4252 #define ETH_TX_BD_FLAGS_IP_CSUM_SHIFT 0 4253 #define ETH_TX_BD_FLAGS_L4_CSUM (0x1<<1) 4254 #define ETH_TX_BD_FLAGS_L4_CSUM_SHIFT 1 4255 #define ETH_TX_BD_FLAGS_VLAN_MODE (0x3<<2) 4256 #define ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT 2 4257 #define ETH_TX_BD_FLAGS_START_BD (0x1<<4) 4258 #define ETH_TX_BD_FLAGS_START_BD_SHIFT 4 4259 #define ETH_TX_BD_FLAGS_IS_UDP (0x1<<5) 4260 #define ETH_TX_BD_FLAGS_IS_UDP_SHIFT 5 4261 #define ETH_TX_BD_FLAGS_SW_LSO (0x1<<6) 4262 #define ETH_TX_BD_FLAGS_SW_LSO_SHIFT 6 4263 #define ETH_TX_BD_FLAGS_IPV6 (0x1<<7) 4264 #define ETH_TX_BD_FLAGS_IPV6_SHIFT 7 4265 }; 4266 4267 /* 4268 * The eth Tx Buffer Descriptor 4269 */ 4270 struct eth_tx_start_bd { 4271 __le32 addr_lo; 4272 __le32 addr_hi; 4273 __le16 nbd; 4274 __le16 nbytes; 4275 __le16 vlan_or_ethertype; 4276 struct eth_tx_bd_flags bd_flags; 4277 u8 general_data; 4278 #define ETH_TX_START_BD_HDR_NBDS (0xF<<0) 4279 #define ETH_TX_START_BD_HDR_NBDS_SHIFT 0 4280 #define ETH_TX_START_BD_FORCE_VLAN_MODE (0x1<<4) 4281 #define ETH_TX_START_BD_FORCE_VLAN_MODE_SHIFT 4 4282 #define ETH_TX_START_BD_PARSE_NBDS (0x3<<5) 4283 #define ETH_TX_START_BD_PARSE_NBDS_SHIFT 5 4284 #define ETH_TX_START_BD_TUNNEL_EXIST (0x1<<7) 4285 #define ETH_TX_START_BD_TUNNEL_EXIST_SHIFT 7 4286 }; 4287 4288 /* 4289 * Tx parsing BD structure for ETH E1/E1h 4290 */ 4291 struct eth_tx_parse_bd_e1x { 4292 __le16 global_data; 4293 #define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W (0xF<<0) 4294 #define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W_SHIFT 0 4295 #define ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE (0x3<<4) 4296 #define ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE_SHIFT 4 4297 #define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN (0x1<<6) 4298 #define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN_SHIFT 6 4299 #define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN (0x1<<7) 4300 #define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN_SHIFT 7 4301 #define ETH_TX_PARSE_BD_E1X_NS_FLG (0x1<<8) 4302 #define ETH_TX_PARSE_BD_E1X_NS_FLG_SHIFT 8 4303 #define ETH_TX_PARSE_BD_E1X_RESERVED0 (0x7F<<9) 4304 #define ETH_TX_PARSE_BD_E1X_RESERVED0_SHIFT 9 4305 u8 tcp_flags; 4306 #define ETH_TX_PARSE_BD_E1X_FIN_FLG (0x1<<0) 4307 #define ETH_TX_PARSE_BD_E1X_FIN_FLG_SHIFT 0 4308 #define ETH_TX_PARSE_BD_E1X_SYN_FLG (0x1<<1) 4309 #define ETH_TX_PARSE_BD_E1X_SYN_FLG_SHIFT 1 4310 #define ETH_TX_PARSE_BD_E1X_RST_FLG (0x1<<2) 4311 #define ETH_TX_PARSE_BD_E1X_RST_FLG_SHIFT 2 4312 #define ETH_TX_PARSE_BD_E1X_PSH_FLG (0x1<<3) 4313 #define ETH_TX_PARSE_BD_E1X_PSH_FLG_SHIFT 3 4314 #define ETH_TX_PARSE_BD_E1X_ACK_FLG (0x1<<4) 4315 #define ETH_TX_PARSE_BD_E1X_ACK_FLG_SHIFT 4 4316 #define ETH_TX_PARSE_BD_E1X_URG_FLG (0x1<<5) 4317 #define ETH_TX_PARSE_BD_E1X_URG_FLG_SHIFT 5 4318 #define ETH_TX_PARSE_BD_E1X_ECE_FLG (0x1<<6) 4319 #define ETH_TX_PARSE_BD_E1X_ECE_FLG_SHIFT 6 4320 #define ETH_TX_PARSE_BD_E1X_CWR_FLG (0x1<<7) 4321 #define ETH_TX_PARSE_BD_E1X_CWR_FLG_SHIFT 7 4322 u8 ip_hlen_w; 4323 __le16 total_hlen_w; 4324 __le16 tcp_pseudo_csum; 4325 __le16 lso_mss; 4326 __le16 ip_id; 4327 __le32 tcp_send_seq; 4328 }; 4329 4330 /* 4331 * Tx parsing BD structure for ETH E2 4332 */ 4333 struct eth_tx_parse_bd_e2 { 4334 union eth_mac_addr_or_tunnel_data data; 4335 __le32 parsing_data; 4336 #define ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W (0x7FF<<0) 4337 #define ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W_SHIFT 0 4338 #define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW (0xF<<11) 4339 #define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW_SHIFT 11 4340 #define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR (0x1<<15) 4341 #define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR_SHIFT 15 4342 #define ETH_TX_PARSE_BD_E2_LSO_MSS (0x3FFF<<16) 4343 #define ETH_TX_PARSE_BD_E2_LSO_MSS_SHIFT 16 4344 #define ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE (0x3<<30) 4345 #define ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE_SHIFT 30 4346 }; 4347 4348 /* 4349 * Tx 2nd parsing BD structure for ETH packet 4350 */ 4351 struct eth_tx_parse_2nd_bd { 4352 __le16 global_data; 4353 #define ETH_TX_PARSE_2ND_BD_IP_HDR_START_OUTER_W (0xF<<0) 4354 #define ETH_TX_PARSE_2ND_BD_IP_HDR_START_OUTER_W_SHIFT 0 4355 #define ETH_TX_PARSE_2ND_BD_IP_HDR_TYPE_OUTER (0x1<<4) 4356 #define ETH_TX_PARSE_2ND_BD_IP_HDR_TYPE_OUTER_SHIFT 4 4357 #define ETH_TX_PARSE_2ND_BD_LLC_SNAP_EN (0x1<<5) 4358 #define ETH_TX_PARSE_2ND_BD_LLC_SNAP_EN_SHIFT 5 4359 #define ETH_TX_PARSE_2ND_BD_NS_FLG (0x1<<6) 4360 #define ETH_TX_PARSE_2ND_BD_NS_FLG_SHIFT 6 4361 #define ETH_TX_PARSE_2ND_BD_TUNNEL_UDP_EXIST (0x1<<7) 4362 #define ETH_TX_PARSE_2ND_BD_TUNNEL_UDP_EXIST_SHIFT 7 4363 #define ETH_TX_PARSE_2ND_BD_IP_HDR_LEN_OUTER_W (0x1F<<8) 4364 #define ETH_TX_PARSE_2ND_BD_IP_HDR_LEN_OUTER_W_SHIFT 8 4365 #define ETH_TX_PARSE_2ND_BD_RESERVED0 (0x7<<13) 4366 #define ETH_TX_PARSE_2ND_BD_RESERVED0_SHIFT 13 4367 __le16 reserved1; 4368 u8 tcp_flags; 4369 #define ETH_TX_PARSE_2ND_BD_FIN_FLG (0x1<<0) 4370 #define ETH_TX_PARSE_2ND_BD_FIN_FLG_SHIFT 0 4371 #define ETH_TX_PARSE_2ND_BD_SYN_FLG (0x1<<1) 4372 #define ETH_TX_PARSE_2ND_BD_SYN_FLG_SHIFT 1 4373 #define ETH_TX_PARSE_2ND_BD_RST_FLG (0x1<<2) 4374 #define ETH_TX_PARSE_2ND_BD_RST_FLG_SHIFT 2 4375 #define ETH_TX_PARSE_2ND_BD_PSH_FLG (0x1<<3) 4376 #define ETH_TX_PARSE_2ND_BD_PSH_FLG_SHIFT 3 4377 #define ETH_TX_PARSE_2ND_BD_ACK_FLG (0x1<<4) 4378 #define ETH_TX_PARSE_2ND_BD_ACK_FLG_SHIFT 4 4379 #define ETH_TX_PARSE_2ND_BD_URG_FLG (0x1<<5) 4380 #define ETH_TX_PARSE_2ND_BD_URG_FLG_SHIFT 5 4381 #define ETH_TX_PARSE_2ND_BD_ECE_FLG (0x1<<6) 4382 #define ETH_TX_PARSE_2ND_BD_ECE_FLG_SHIFT 6 4383 #define ETH_TX_PARSE_2ND_BD_CWR_FLG (0x1<<7) 4384 #define ETH_TX_PARSE_2ND_BD_CWR_FLG_SHIFT 7 4385 u8 reserved2; 4386 u8 tunnel_udp_hdr_start_w; 4387 u8 fw_ip_hdr_to_payload_w; 4388 __le16 fw_ip_csum_wo_len_flags_frag; 4389 __le16 hw_ip_id; 4390 __le32 tcp_send_seq; 4391 }; 4392 4393 /* The last BD in the BD memory will hold a pointer to the next BD memory */ 4394 struct eth_tx_next_bd { 4395 __le32 addr_lo; 4396 __le32 addr_hi; 4397 u8 reserved[8]; 4398 }; 4399 4400 /* 4401 * union for 4 Bd types 4402 */ 4403 union eth_tx_bd_types { 4404 struct eth_tx_start_bd start_bd; 4405 struct eth_tx_bd reg_bd; 4406 struct eth_tx_parse_bd_e1x parse_bd_e1x; 4407 struct eth_tx_parse_bd_e2 parse_bd_e2; 4408 struct eth_tx_parse_2nd_bd parse_2nd_bd; 4409 struct eth_tx_next_bd next_bd; 4410 }; 4411 4412 /* 4413 * array of 13 bds as appears in the eth xstorm context 4414 */ 4415 struct eth_tx_bds_array { 4416 union eth_tx_bd_types bds[13]; 4417 }; 4418 4419 4420 /* 4421 * VLAN mode on TX BDs 4422 */ 4423 enum eth_tx_vlan_type { 4424 X_ETH_NO_VLAN, 4425 X_ETH_OUTBAND_VLAN, 4426 X_ETH_INBAND_VLAN, 4427 X_ETH_FW_ADDED_VLAN, 4428 MAX_ETH_TX_VLAN_TYPE 4429 }; 4430 4431 4432 /* 4433 * Ethernet VLAN filtering mode in E1x 4434 */ 4435 enum eth_vlan_filter_mode { 4436 ETH_VLAN_FILTER_ANY_VLAN, 4437 ETH_VLAN_FILTER_SPECIFIC_VLAN, 4438 ETH_VLAN_FILTER_CLASSIFY, 4439 MAX_ETH_VLAN_FILTER_MODE 4440 }; 4441 4442 4443 /* 4444 * MAC filtering configuration command header 4445 */ 4446 struct mac_configuration_hdr { 4447 u8 length; 4448 u8 offset; 4449 __le16 client_id; 4450 __le32 echo; 4451 }; 4452 4453 /* 4454 * MAC address in list for ramrod 4455 */ 4456 struct mac_configuration_entry { 4457 __le16 lsb_mac_addr; 4458 __le16 middle_mac_addr; 4459 __le16 msb_mac_addr; 4460 __le16 vlan_id; 4461 u8 pf_id; 4462 u8 flags; 4463 #define MAC_CONFIGURATION_ENTRY_ACTION_TYPE (0x1<<0) 4464 #define MAC_CONFIGURATION_ENTRY_ACTION_TYPE_SHIFT 0 4465 #define MAC_CONFIGURATION_ENTRY_RDMA_MAC (0x1<<1) 4466 #define MAC_CONFIGURATION_ENTRY_RDMA_MAC_SHIFT 1 4467 #define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE (0x3<<2) 4468 #define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE_SHIFT 2 4469 #define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL (0x1<<4) 4470 #define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL_SHIFT 4 4471 #define MAC_CONFIGURATION_ENTRY_BROADCAST (0x1<<5) 4472 #define MAC_CONFIGURATION_ENTRY_BROADCAST_SHIFT 5 4473 #define MAC_CONFIGURATION_ENTRY_RESERVED1 (0x3<<6) 4474 #define MAC_CONFIGURATION_ENTRY_RESERVED1_SHIFT 6 4475 __le16 reserved0; 4476 __le32 clients_bit_vector; 4477 }; 4478 4479 /* 4480 * MAC filtering configuration command 4481 */ 4482 struct mac_configuration_cmd { 4483 struct mac_configuration_hdr hdr; 4484 struct mac_configuration_entry config_table[64]; 4485 }; 4486 4487 4488 /* 4489 * Set-MAC command type (in E1x) 4490 */ 4491 enum set_mac_action_type { 4492 T_ETH_MAC_COMMAND_INVALIDATE, 4493 T_ETH_MAC_COMMAND_SET, 4494 MAX_SET_MAC_ACTION_TYPE 4495 }; 4496 4497 4498 /* 4499 * Ethernet TPA Modes 4500 */ 4501 enum tpa_mode { 4502 TPA_LRO, 4503 TPA_GRO, 4504 MAX_TPA_MODE}; 4505 4506 4507 /* 4508 * tpa update ramrod data 4509 */ 4510 struct tpa_update_ramrod_data { 4511 u8 update_ipv4; 4512 u8 update_ipv6; 4513 u8 client_id; 4514 u8 max_tpa_queues; 4515 u8 max_sges_for_packet; 4516 u8 complete_on_both_clients; 4517 u8 dont_verify_rings_pause_thr_flg; 4518 u8 tpa_mode; 4519 __le16 sge_buff_size; 4520 __le16 max_agg_size; 4521 __le32 sge_page_base_lo; 4522 __le32 sge_page_base_hi; 4523 __le16 sge_pause_thr_low; 4524 __le16 sge_pause_thr_high; 4525 }; 4526 4527 4528 /* 4529 * approximate-match multicast filtering for E1H per function in Tstorm 4530 */ 4531 struct tstorm_eth_approximate_match_multicast_filtering { 4532 u32 mcast_add_hash_bit_array[8]; 4533 }; 4534 4535 4536 /* 4537 * Common configuration parameters per function in Tstorm 4538 */ 4539 struct tstorm_eth_function_common_config { 4540 __le16 config_flags; 4541 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0) 4542 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0 4543 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1) 4544 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1 4545 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1<<2) 4546 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2 4547 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3) 4548 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3 4549 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE (0x7<<4) 4550 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT 4 4551 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE (0x1<<7) 4552 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE_SHIFT 7 4553 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0xFF<<8) 4554 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 8 4555 u8 rss_result_mask; 4556 u8 reserved1; 4557 __le16 vlan_id[2]; 4558 }; 4559 4560 4561 /* 4562 * MAC filtering configuration parameters per port in Tstorm 4563 */ 4564 struct tstorm_eth_mac_filter_config { 4565 u32 ucast_drop_all; 4566 u32 ucast_accept_all; 4567 u32 mcast_drop_all; 4568 u32 mcast_accept_all; 4569 u32 bcast_accept_all; 4570 u32 vlan_filter[2]; 4571 u32 unmatched_unicast; 4572 }; 4573 4574 4575 /* 4576 * tx only queue init ramrod data 4577 */ 4578 struct tx_queue_init_ramrod_data { 4579 struct client_init_general_data general; 4580 struct client_init_tx_data tx; 4581 }; 4582 4583 4584 /* 4585 * Three RX producers for ETH 4586 */ 4587 struct ustorm_eth_rx_producers { 4588 #if defined(__BIG_ENDIAN) 4589 u16 bd_prod; 4590 u16 cqe_prod; 4591 #elif defined(__LITTLE_ENDIAN) 4592 u16 cqe_prod; 4593 u16 bd_prod; 4594 #endif 4595 #if defined(__BIG_ENDIAN) 4596 u16 reserved; 4597 u16 sge_prod; 4598 #elif defined(__LITTLE_ENDIAN) 4599 u16 sge_prod; 4600 u16 reserved; 4601 #endif 4602 }; 4603 4604 4605 /* 4606 * FCoE RX statistics parameters section#0 4607 */ 4608 struct fcoe_rx_stat_params_section0 { 4609 __le32 fcoe_rx_pkt_cnt; 4610 __le32 fcoe_rx_byte_cnt; 4611 }; 4612 4613 4614 /* 4615 * FCoE RX statistics parameters section#1 4616 */ 4617 struct fcoe_rx_stat_params_section1 { 4618 __le32 fcoe_ver_cnt; 4619 __le32 fcoe_rx_drop_pkt_cnt; 4620 }; 4621 4622 4623 /* 4624 * FCoE RX statistics parameters section#2 4625 */ 4626 struct fcoe_rx_stat_params_section2 { 4627 __le32 fc_crc_cnt; 4628 __le32 eofa_del_cnt; 4629 __le32 miss_frame_cnt; 4630 __le32 seq_timeout_cnt; 4631 __le32 drop_seq_cnt; 4632 __le32 fcoe_rx_drop_pkt_cnt; 4633 __le32 fcp_rx_pkt_cnt; 4634 __le32 reserved0; 4635 }; 4636 4637 4638 /* 4639 * FCoE TX statistics parameters 4640 */ 4641 struct fcoe_tx_stat_params { 4642 __le32 fcoe_tx_pkt_cnt; 4643 __le32 fcoe_tx_byte_cnt; 4644 __le32 fcp_tx_pkt_cnt; 4645 __le32 reserved0; 4646 }; 4647 4648 /* 4649 * FCoE statistics parameters 4650 */ 4651 struct fcoe_statistics_params { 4652 struct fcoe_tx_stat_params tx_stat; 4653 struct fcoe_rx_stat_params_section0 rx_stat0; 4654 struct fcoe_rx_stat_params_section1 rx_stat1; 4655 struct fcoe_rx_stat_params_section2 rx_stat2; 4656 }; 4657 4658 4659 /* 4660 * The data afex vif list ramrod need 4661 */ 4662 struct afex_vif_list_ramrod_data { 4663 u8 afex_vif_list_command; 4664 u8 func_bit_map; 4665 __le16 vif_list_index; 4666 u8 func_to_clear; 4667 u8 echo; 4668 __le16 reserved1; 4669 }; 4670 4671 4672 /* 4673 * cfc delete event data 4674 */ 4675 struct cfc_del_event_data { 4676 u32 cid; 4677 u32 reserved0; 4678 u32 reserved1; 4679 }; 4680 4681 4682 /* 4683 * per-port SAFC demo variables 4684 */ 4685 struct cmng_flags_per_port { 4686 u32 cmng_enables; 4687 #define CMNG_FLAGS_PER_PORT_FAIRNESS_VN (0x1<<0) 4688 #define CMNG_FLAGS_PER_PORT_FAIRNESS_VN_SHIFT 0 4689 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN (0x1<<1) 4690 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN_SHIFT 1 4691 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS (0x1<<2) 4692 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_SHIFT 2 4693 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE (0x1<<3) 4694 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE_SHIFT 3 4695 #define __CMNG_FLAGS_PER_PORT_RESERVED0 (0xFFFFFFF<<4) 4696 #define __CMNG_FLAGS_PER_PORT_RESERVED0_SHIFT 4 4697 u32 __reserved1; 4698 }; 4699 4700 4701 /* 4702 * per-port rate shaping variables 4703 */ 4704 struct rate_shaping_vars_per_port { 4705 u32 rs_periodic_timeout; 4706 u32 rs_threshold; 4707 }; 4708 4709 /* 4710 * per-port fairness variables 4711 */ 4712 struct fairness_vars_per_port { 4713 u32 upper_bound; 4714 u32 fair_threshold; 4715 u32 fairness_timeout; 4716 u32 reserved0; 4717 }; 4718 4719 /* 4720 * per-port SAFC variables 4721 */ 4722 struct safc_struct_per_port { 4723 #if defined(__BIG_ENDIAN) 4724 u16 __reserved1; 4725 u8 __reserved0; 4726 u8 safc_timeout_usec; 4727 #elif defined(__LITTLE_ENDIAN) 4728 u8 safc_timeout_usec; 4729 u8 __reserved0; 4730 u16 __reserved1; 4731 #endif 4732 u8 cos_to_traffic_types[MAX_COS_NUMBER]; 4733 u16 cos_to_pause_mask[NUM_OF_SAFC_BITS]; 4734 }; 4735 4736 /* 4737 * Per-port congestion management variables 4738 */ 4739 struct cmng_struct_per_port { 4740 struct rate_shaping_vars_per_port rs_vars; 4741 struct fairness_vars_per_port fair_vars; 4742 struct safc_struct_per_port safc_vars; 4743 struct cmng_flags_per_port flags; 4744 }; 4745 4746 /* 4747 * a single rate shaping counter. can be used as protocol or vnic counter 4748 */ 4749 struct rate_shaping_counter { 4750 u32 quota; 4751 #if defined(__BIG_ENDIAN) 4752 u16 __reserved0; 4753 u16 rate; 4754 #elif defined(__LITTLE_ENDIAN) 4755 u16 rate; 4756 u16 __reserved0; 4757 #endif 4758 }; 4759 4760 /* 4761 * per-vnic rate shaping variables 4762 */ 4763 struct rate_shaping_vars_per_vn { 4764 struct rate_shaping_counter vn_counter; 4765 }; 4766 4767 /* 4768 * per-vnic fairness variables 4769 */ 4770 struct fairness_vars_per_vn { 4771 u32 cos_credit_delta[MAX_COS_NUMBER]; 4772 u32 vn_credit_delta; 4773 u32 __reserved0; 4774 }; 4775 4776 /* 4777 * cmng port init state 4778 */ 4779 struct cmng_vnic { 4780 struct rate_shaping_vars_per_vn vnic_max_rate[4]; 4781 struct fairness_vars_per_vn vnic_min_rate[4]; 4782 }; 4783 4784 /* 4785 * cmng port init state 4786 */ 4787 struct cmng_init { 4788 struct cmng_struct_per_port port; 4789 struct cmng_vnic vnic; 4790 }; 4791 4792 4793 /* 4794 * driver parameters for congestion management init, all rates are in Mbps 4795 */ 4796 struct cmng_init_input { 4797 u32 port_rate; 4798 u16 vnic_min_rate[4]; 4799 u16 vnic_max_rate[4]; 4800 u16 cos_min_rate[MAX_COS_NUMBER]; 4801 u16 cos_to_pause_mask[MAX_COS_NUMBER]; 4802 struct cmng_flags_per_port flags; 4803 }; 4804 4805 4806 /* 4807 * Protocol-common command ID for slow path elements 4808 */ 4809 enum common_spqe_cmd_id { 4810 RAMROD_CMD_ID_COMMON_UNUSED, 4811 RAMROD_CMD_ID_COMMON_FUNCTION_START, 4812 RAMROD_CMD_ID_COMMON_FUNCTION_STOP, 4813 RAMROD_CMD_ID_COMMON_FUNCTION_UPDATE, 4814 RAMROD_CMD_ID_COMMON_CFC_DEL, 4815 RAMROD_CMD_ID_COMMON_CFC_DEL_WB, 4816 RAMROD_CMD_ID_COMMON_STAT_QUERY, 4817 RAMROD_CMD_ID_COMMON_STOP_TRAFFIC, 4818 RAMROD_CMD_ID_COMMON_START_TRAFFIC, 4819 RAMROD_CMD_ID_COMMON_AFEX_VIF_LISTS, 4820 RAMROD_CMD_ID_COMMON_SET_TIMESYNC, 4821 MAX_COMMON_SPQE_CMD_ID 4822 }; 4823 4824 /* 4825 * Per-protocol connection types 4826 */ 4827 enum connection_type { 4828 ETH_CONNECTION_TYPE, 4829 TOE_CONNECTION_TYPE, 4830 RDMA_CONNECTION_TYPE, 4831 ISCSI_CONNECTION_TYPE, 4832 FCOE_CONNECTION_TYPE, 4833 RESERVED_CONNECTION_TYPE_0, 4834 RESERVED_CONNECTION_TYPE_1, 4835 RESERVED_CONNECTION_TYPE_2, 4836 NONE_CONNECTION_TYPE, 4837 MAX_CONNECTION_TYPE 4838 }; 4839 4840 4841 /* 4842 * Cos modes 4843 */ 4844 enum cos_mode { 4845 OVERRIDE_COS, 4846 STATIC_COS, 4847 FW_WRR, 4848 MAX_COS_MODE 4849 }; 4850 4851 4852 /* 4853 * Dynamic HC counters set by the driver 4854 */ 4855 struct hc_dynamic_drv_counter { 4856 u32 val[HC_SB_MAX_DYNAMIC_INDICES]; 4857 }; 4858 4859 /* 4860 * zone A per-queue data 4861 */ 4862 struct cstorm_queue_zone_data { 4863 struct hc_dynamic_drv_counter hc_dyn_drv_cnt; 4864 struct regpair reserved[2]; 4865 }; 4866 4867 4868 /* 4869 * Vf-PF channel data in cstorm ram (non-triggered zone) 4870 */ 4871 struct vf_pf_channel_zone_data { 4872 u32 msg_addr_lo; 4873 u32 msg_addr_hi; 4874 }; 4875 4876 /* 4877 * zone for VF non-triggered data 4878 */ 4879 struct non_trigger_vf_zone { 4880 struct vf_pf_channel_zone_data vf_pf_channel; 4881 }; 4882 4883 /* 4884 * Vf-PF channel trigger zone in cstorm ram 4885 */ 4886 struct vf_pf_channel_zone_trigger { 4887 u8 addr_valid; 4888 }; 4889 4890 /* 4891 * zone that triggers the in-bound interrupt 4892 */ 4893 struct trigger_vf_zone { 4894 #if defined(__BIG_ENDIAN) 4895 u16 reserved1; 4896 u8 reserved0; 4897 struct vf_pf_channel_zone_trigger vf_pf_channel; 4898 #elif defined(__LITTLE_ENDIAN) 4899 struct vf_pf_channel_zone_trigger vf_pf_channel; 4900 u8 reserved0; 4901 u16 reserved1; 4902 #endif 4903 u32 reserved2; 4904 }; 4905 4906 /* 4907 * zone B per-VF data 4908 */ 4909 struct cstorm_vf_zone_data { 4910 struct non_trigger_vf_zone non_trigger; 4911 struct trigger_vf_zone trigger; 4912 }; 4913 4914 4915 /* 4916 * Dynamic host coalescing init parameters, per state machine 4917 */ 4918 struct dynamic_hc_sm_config { 4919 u32 threshold[3]; 4920 u8 shift_per_protocol[HC_SB_MAX_DYNAMIC_INDICES]; 4921 u8 hc_timeout0[HC_SB_MAX_DYNAMIC_INDICES]; 4922 u8 hc_timeout1[HC_SB_MAX_DYNAMIC_INDICES]; 4923 u8 hc_timeout2[HC_SB_MAX_DYNAMIC_INDICES]; 4924 u8 hc_timeout3[HC_SB_MAX_DYNAMIC_INDICES]; 4925 }; 4926 4927 /* 4928 * Dynamic host coalescing init parameters 4929 */ 4930 struct dynamic_hc_config { 4931 struct dynamic_hc_sm_config sm_config[HC_SB_MAX_SM]; 4932 }; 4933 4934 4935 struct e2_integ_data { 4936 #if defined(__BIG_ENDIAN) 4937 u8 flags; 4938 #define E2_INTEG_DATA_TESTING_EN (0x1<<0) 4939 #define E2_INTEG_DATA_TESTING_EN_SHIFT 0 4940 #define E2_INTEG_DATA_LB_TX (0x1<<1) 4941 #define E2_INTEG_DATA_LB_TX_SHIFT 1 4942 #define E2_INTEG_DATA_COS_TX (0x1<<2) 4943 #define E2_INTEG_DATA_COS_TX_SHIFT 2 4944 #define E2_INTEG_DATA_OPPORTUNISTICQM (0x1<<3) 4945 #define E2_INTEG_DATA_OPPORTUNISTICQM_SHIFT 3 4946 #define E2_INTEG_DATA_DPMTESTRELEASEDQ (0x1<<4) 4947 #define E2_INTEG_DATA_DPMTESTRELEASEDQ_SHIFT 4 4948 #define E2_INTEG_DATA_RESERVED (0x7<<5) 4949 #define E2_INTEG_DATA_RESERVED_SHIFT 5 4950 u8 cos; 4951 u8 voq; 4952 u8 pbf_queue; 4953 #elif defined(__LITTLE_ENDIAN) 4954 u8 pbf_queue; 4955 u8 voq; 4956 u8 cos; 4957 u8 flags; 4958 #define E2_INTEG_DATA_TESTING_EN (0x1<<0) 4959 #define E2_INTEG_DATA_TESTING_EN_SHIFT 0 4960 #define E2_INTEG_DATA_LB_TX (0x1<<1) 4961 #define E2_INTEG_DATA_LB_TX_SHIFT 1 4962 #define E2_INTEG_DATA_COS_TX (0x1<<2) 4963 #define E2_INTEG_DATA_COS_TX_SHIFT 2 4964 #define E2_INTEG_DATA_OPPORTUNISTICQM (0x1<<3) 4965 #define E2_INTEG_DATA_OPPORTUNISTICQM_SHIFT 3 4966 #define E2_INTEG_DATA_DPMTESTRELEASEDQ (0x1<<4) 4967 #define E2_INTEG_DATA_DPMTESTRELEASEDQ_SHIFT 4 4968 #define E2_INTEG_DATA_RESERVED (0x7<<5) 4969 #define E2_INTEG_DATA_RESERVED_SHIFT 5 4970 #endif 4971 #if defined(__BIG_ENDIAN) 4972 u16 reserved3; 4973 u8 reserved2; 4974 u8 ramEn; 4975 #elif defined(__LITTLE_ENDIAN) 4976 u8 ramEn; 4977 u8 reserved2; 4978 u16 reserved3; 4979 #endif 4980 }; 4981 4982 4983 /* 4984 * set mac event data 4985 */ 4986 struct eth_event_data { 4987 u32 echo; 4988 u32 reserved0; 4989 u32 reserved1; 4990 }; 4991 4992 4993 /* 4994 * pf-vf event data 4995 */ 4996 struct vf_pf_event_data { 4997 u8 vf_id; 4998 u8 reserved0; 4999 u16 reserved1; 5000 u32 msg_addr_lo; 5001 u32 msg_addr_hi; 5002 }; 5003 5004 /* 5005 * VF FLR event data 5006 */ 5007 struct vf_flr_event_data { 5008 u8 vf_id; 5009 u8 reserved0; 5010 u16 reserved1; 5011 u32 reserved2; 5012 u32 reserved3; 5013 }; 5014 5015 /* 5016 * malicious VF event data 5017 */ 5018 struct malicious_vf_event_data { 5019 u8 vf_id; 5020 u8 err_id; 5021 u16 reserved1; 5022 u32 reserved2; 5023 u32 reserved3; 5024 }; 5025 5026 /* 5027 * vif list event data 5028 */ 5029 struct vif_list_event_data { 5030 u8 func_bit_map; 5031 u8 echo; 5032 __le16 reserved0; 5033 __le32 reserved1; 5034 __le32 reserved2; 5035 }; 5036 5037 /* function update event data */ 5038 struct function_update_event_data { 5039 u8 echo; 5040 u8 reserved; 5041 __le16 reserved0; 5042 __le32 reserved1; 5043 __le32 reserved2; 5044 }; 5045 5046 5047 /* union for all event ring message types */ 5048 union event_data { 5049 struct vf_pf_event_data vf_pf_event; 5050 struct eth_event_data eth_event; 5051 struct cfc_del_event_data cfc_del_event; 5052 struct vf_flr_event_data vf_flr_event; 5053 struct malicious_vf_event_data malicious_vf_event; 5054 struct vif_list_event_data vif_list_event; 5055 struct function_update_event_data function_update_event; 5056 }; 5057 5058 5059 /* 5060 * per PF event ring data 5061 */ 5062 struct event_ring_data { 5063 struct regpair_native base_addr; 5064 #if defined(__BIG_ENDIAN) 5065 u8 index_id; 5066 u8 sb_id; 5067 u16 producer; 5068 #elif defined(__LITTLE_ENDIAN) 5069 u16 producer; 5070 u8 sb_id; 5071 u8 index_id; 5072 #endif 5073 u32 reserved0; 5074 }; 5075 5076 5077 /* 5078 * event ring message element (each element is 128 bits) 5079 */ 5080 struct event_ring_msg { 5081 u8 opcode; 5082 u8 error; 5083 u16 reserved1; 5084 union event_data data; 5085 }; 5086 5087 /* 5088 * event ring next page element (128 bits) 5089 */ 5090 struct event_ring_next { 5091 struct regpair addr; 5092 u32 reserved[2]; 5093 }; 5094 5095 /* 5096 * union for event ring element types (each element is 128 bits) 5097 */ 5098 union event_ring_elem { 5099 struct event_ring_msg message; 5100 struct event_ring_next next_page; 5101 }; 5102 5103 5104 /* 5105 * Common event ring opcodes 5106 */ 5107 enum event_ring_opcode { 5108 EVENT_RING_OPCODE_VF_PF_CHANNEL, 5109 EVENT_RING_OPCODE_FUNCTION_START, 5110 EVENT_RING_OPCODE_FUNCTION_STOP, 5111 EVENT_RING_OPCODE_CFC_DEL, 5112 EVENT_RING_OPCODE_CFC_DEL_WB, 5113 EVENT_RING_OPCODE_STAT_QUERY, 5114 EVENT_RING_OPCODE_STOP_TRAFFIC, 5115 EVENT_RING_OPCODE_START_TRAFFIC, 5116 EVENT_RING_OPCODE_VF_FLR, 5117 EVENT_RING_OPCODE_MALICIOUS_VF, 5118 EVENT_RING_OPCODE_FORWARD_SETUP, 5119 EVENT_RING_OPCODE_RSS_UPDATE_RULES, 5120 EVENT_RING_OPCODE_FUNCTION_UPDATE, 5121 EVENT_RING_OPCODE_AFEX_VIF_LISTS, 5122 EVENT_RING_OPCODE_SET_MAC, 5123 EVENT_RING_OPCODE_CLASSIFICATION_RULES, 5124 EVENT_RING_OPCODE_FILTERS_RULES, 5125 EVENT_RING_OPCODE_MULTICAST_RULES, 5126 EVENT_RING_OPCODE_SET_TIMESYNC, 5127 MAX_EVENT_RING_OPCODE 5128 }; 5129 5130 /* 5131 * Modes for fairness algorithm 5132 */ 5133 enum fairness_mode { 5134 FAIRNESS_COS_WRR_MODE, 5135 FAIRNESS_COS_ETS_MODE, 5136 MAX_FAIRNESS_MODE 5137 }; 5138 5139 5140 /* 5141 * Priority and cos 5142 */ 5143 struct priority_cos { 5144 u8 priority; 5145 u8 cos; 5146 __le16 reserved1; 5147 }; 5148 5149 /* 5150 * The data for flow control configuration 5151 */ 5152 struct flow_control_configuration { 5153 struct priority_cos traffic_type_to_priority_cos[MAX_TRAFFIC_TYPES]; 5154 u8 dcb_enabled; 5155 u8 dcb_version; 5156 u8 dont_add_pri_0_en; 5157 u8 reserved1; 5158 __le32 reserved2; 5159 }; 5160 5161 5162 /* 5163 * 5164 */ 5165 struct function_start_data { 5166 u8 function_mode; 5167 u8 allow_npar_tx_switching; 5168 __le16 sd_vlan_tag; 5169 __le16 vif_id; 5170 u8 path_id; 5171 u8 network_cos_mode; 5172 u8 dmae_cmd_id; 5173 u8 gre_tunnel_mode; 5174 u8 gre_tunnel_rss; 5175 u8 nvgre_clss_en; 5176 __le16 reserved1[2]; 5177 }; 5178 5179 struct function_update_data { 5180 u8 vif_id_change_flg; 5181 u8 afex_default_vlan_change_flg; 5182 u8 allowed_priorities_change_flg; 5183 u8 network_cos_mode_change_flg; 5184 __le16 vif_id; 5185 __le16 afex_default_vlan; 5186 u8 allowed_priorities; 5187 u8 network_cos_mode; 5188 u8 lb_mode_en_change_flg; 5189 u8 lb_mode_en; 5190 u8 tx_switch_suspend_change_flg; 5191 u8 tx_switch_suspend; 5192 u8 echo; 5193 u8 reserved1; 5194 u8 update_gre_cfg_flg; 5195 u8 gre_tunnel_mode; 5196 u8 gre_tunnel_rss; 5197 u8 nvgre_clss_en; 5198 u32 reserved3; 5199 }; 5200 5201 /* 5202 * FW version stored in the Xstorm RAM 5203 */ 5204 struct fw_version { 5205 #if defined(__BIG_ENDIAN) 5206 u8 engineering; 5207 u8 revision; 5208 u8 minor; 5209 u8 major; 5210 #elif defined(__LITTLE_ENDIAN) 5211 u8 major; 5212 u8 minor; 5213 u8 revision; 5214 u8 engineering; 5215 #endif 5216 u32 flags; 5217 #define FW_VERSION_OPTIMIZED (0x1<<0) 5218 #define FW_VERSION_OPTIMIZED_SHIFT 0 5219 #define FW_VERSION_BIG_ENDIEN (0x1<<1) 5220 #define FW_VERSION_BIG_ENDIEN_SHIFT 1 5221 #define FW_VERSION_CHIP_VERSION (0x3<<2) 5222 #define FW_VERSION_CHIP_VERSION_SHIFT 2 5223 #define __FW_VERSION_RESERVED (0xFFFFFFF<<4) 5224 #define __FW_VERSION_RESERVED_SHIFT 4 5225 }; 5226 5227 /* GRE RSS Mode */ 5228 enum gre_rss_mode { 5229 GRE_OUTER_HEADERS_RSS, 5230 GRE_INNER_HEADERS_RSS, 5231 NVGRE_KEY_ENTROPY_RSS, 5232 MAX_GRE_RSS_MODE 5233 }; 5234 5235 /* GRE Tunnel Mode */ 5236 enum gre_tunnel_type { 5237 NO_GRE_TUNNEL, 5238 NVGRE_TUNNEL, 5239 L2GRE_TUNNEL, 5240 IPGRE_TUNNEL, 5241 MAX_GRE_TUNNEL_TYPE 5242 }; 5243 5244 /* 5245 * Dynamic Host-Coalescing - Driver(host) counters 5246 */ 5247 struct hc_dynamic_sb_drv_counters { 5248 u32 dynamic_hc_drv_counter[HC_SB_MAX_DYNAMIC_INDICES]; 5249 }; 5250 5251 5252 /* 5253 * 2 bytes. configuration/state parameters for a single protocol index 5254 */ 5255 struct hc_index_data { 5256 #if defined(__BIG_ENDIAN) 5257 u8 flags; 5258 #define HC_INDEX_DATA_SM_ID (0x1<<0) 5259 #define HC_INDEX_DATA_SM_ID_SHIFT 0 5260 #define HC_INDEX_DATA_HC_ENABLED (0x1<<1) 5261 #define HC_INDEX_DATA_HC_ENABLED_SHIFT 1 5262 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2) 5263 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2 5264 #define HC_INDEX_DATA_RESERVE (0x1F<<3) 5265 #define HC_INDEX_DATA_RESERVE_SHIFT 3 5266 u8 timeout; 5267 #elif defined(__LITTLE_ENDIAN) 5268 u8 timeout; 5269 u8 flags; 5270 #define HC_INDEX_DATA_SM_ID (0x1<<0) 5271 #define HC_INDEX_DATA_SM_ID_SHIFT 0 5272 #define HC_INDEX_DATA_HC_ENABLED (0x1<<1) 5273 #define HC_INDEX_DATA_HC_ENABLED_SHIFT 1 5274 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2) 5275 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2 5276 #define HC_INDEX_DATA_RESERVE (0x1F<<3) 5277 #define HC_INDEX_DATA_RESERVE_SHIFT 3 5278 #endif 5279 }; 5280 5281 5282 /* 5283 * HC state-machine 5284 */ 5285 struct hc_status_block_sm { 5286 #if defined(__BIG_ENDIAN) 5287 u8 igu_seg_id; 5288 u8 igu_sb_id; 5289 u8 timer_value; 5290 u8 __flags; 5291 #elif defined(__LITTLE_ENDIAN) 5292 u8 __flags; 5293 u8 timer_value; 5294 u8 igu_sb_id; 5295 u8 igu_seg_id; 5296 #endif 5297 u32 time_to_expire; 5298 }; 5299 5300 /* 5301 * hold PCI identification variables- used in various places in firmware 5302 */ 5303 struct pci_entity { 5304 #if defined(__BIG_ENDIAN) 5305 u8 vf_valid; 5306 u8 vf_id; 5307 u8 vnic_id; 5308 u8 pf_id; 5309 #elif defined(__LITTLE_ENDIAN) 5310 u8 pf_id; 5311 u8 vnic_id; 5312 u8 vf_id; 5313 u8 vf_valid; 5314 #endif 5315 }; 5316 5317 /* 5318 * The fast-path status block meta-data, common to all chips 5319 */ 5320 struct hc_sb_data { 5321 struct regpair_native host_sb_addr; 5322 struct hc_status_block_sm state_machine[HC_SB_MAX_SM]; 5323 struct pci_entity p_func; 5324 #if defined(__BIG_ENDIAN) 5325 u8 rsrv0; 5326 u8 state; 5327 u8 dhc_qzone_id; 5328 u8 same_igu_sb_1b; 5329 #elif defined(__LITTLE_ENDIAN) 5330 u8 same_igu_sb_1b; 5331 u8 dhc_qzone_id; 5332 u8 state; 5333 u8 rsrv0; 5334 #endif 5335 struct regpair_native rsrv1[2]; 5336 }; 5337 5338 5339 /* 5340 * Segment types for host coaslescing 5341 */ 5342 enum hc_segment { 5343 HC_REGULAR_SEGMENT, 5344 HC_DEFAULT_SEGMENT, 5345 MAX_HC_SEGMENT 5346 }; 5347 5348 5349 /* 5350 * The fast-path status block meta-data 5351 */ 5352 struct hc_sp_status_block_data { 5353 struct regpair_native host_sb_addr; 5354 #if defined(__BIG_ENDIAN) 5355 u8 rsrv1; 5356 u8 state; 5357 u8 igu_seg_id; 5358 u8 igu_sb_id; 5359 #elif defined(__LITTLE_ENDIAN) 5360 u8 igu_sb_id; 5361 u8 igu_seg_id; 5362 u8 state; 5363 u8 rsrv1; 5364 #endif 5365 struct pci_entity p_func; 5366 }; 5367 5368 5369 /* 5370 * The fast-path status block meta-data 5371 */ 5372 struct hc_status_block_data_e1x { 5373 struct hc_index_data index_data[HC_SB_MAX_INDICES_E1X]; 5374 struct hc_sb_data common; 5375 }; 5376 5377 5378 /* 5379 * The fast-path status block meta-data 5380 */ 5381 struct hc_status_block_data_e2 { 5382 struct hc_index_data index_data[HC_SB_MAX_INDICES_E2]; 5383 struct hc_sb_data common; 5384 }; 5385 5386 5387 /* 5388 * IGU block operartion modes (in Everest2) 5389 */ 5390 enum igu_mode { 5391 HC_IGU_BC_MODE, 5392 HC_IGU_NBC_MODE, 5393 MAX_IGU_MODE 5394 }; 5395 5396 5397 /* 5398 * IP versions 5399 */ 5400 enum ip_ver { 5401 IP_V4, 5402 IP_V6, 5403 MAX_IP_VER 5404 }; 5405 5406 /* 5407 * Malicious VF error ID 5408 */ 5409 enum malicious_vf_error_id { 5410 VF_PF_CHANNEL_NOT_READY, 5411 ETH_ILLEGAL_BD_LENGTHS, 5412 ETH_PACKET_TOO_SHORT, 5413 ETH_PAYLOAD_TOO_BIG, 5414 ETH_ILLEGAL_ETH_TYPE, 5415 ETH_ILLEGAL_LSO_HDR_LEN, 5416 ETH_TOO_MANY_BDS, 5417 ETH_ZERO_HDR_NBDS, 5418 ETH_START_BD_NOT_SET, 5419 ETH_ILLEGAL_PARSE_NBDS, 5420 ETH_IPV6_AND_CHECKSUM, 5421 ETH_VLAN_FLG_INCORRECT, 5422 ETH_ILLEGAL_LSO_MSS, 5423 ETH_TUNNEL_NOT_SUPPORTED, 5424 MAX_MALICIOUS_VF_ERROR_ID 5425 }; 5426 5427 /* 5428 * Multi-function modes 5429 */ 5430 enum mf_mode { 5431 SINGLE_FUNCTION, 5432 MULTI_FUNCTION_SD, 5433 MULTI_FUNCTION_SI, 5434 MULTI_FUNCTION_AFEX, 5435 MAX_MF_MODE 5436 }; 5437 5438 /* 5439 * Protocol-common statistics collected by the Tstorm (per pf) 5440 */ 5441 struct tstorm_per_pf_stats { 5442 struct regpair rcv_error_bytes; 5443 }; 5444 5445 /* 5446 * 5447 */ 5448 struct per_pf_stats { 5449 struct tstorm_per_pf_stats tstorm_pf_statistics; 5450 }; 5451 5452 5453 /* 5454 * Protocol-common statistics collected by the Tstorm (per port) 5455 */ 5456 struct tstorm_per_port_stats { 5457 __le32 mac_discard; 5458 __le32 mac_filter_discard; 5459 __le32 brb_truncate_discard; 5460 __le32 mf_tag_discard; 5461 __le32 packet_drop; 5462 __le32 reserved; 5463 }; 5464 5465 /* 5466 * 5467 */ 5468 struct per_port_stats { 5469 struct tstorm_per_port_stats tstorm_port_statistics; 5470 }; 5471 5472 5473 /* 5474 * Protocol-common statistics collected by the Tstorm (per client) 5475 */ 5476 struct tstorm_per_queue_stats { 5477 struct regpair rcv_ucast_bytes; 5478 __le32 rcv_ucast_pkts; 5479 __le32 checksum_discard; 5480 struct regpair rcv_bcast_bytes; 5481 __le32 rcv_bcast_pkts; 5482 __le32 pkts_too_big_discard; 5483 struct regpair rcv_mcast_bytes; 5484 __le32 rcv_mcast_pkts; 5485 __le32 ttl0_discard; 5486 __le16 no_buff_discard; 5487 __le16 reserved0; 5488 __le32 reserved1; 5489 }; 5490 5491 /* 5492 * Protocol-common statistics collected by the Ustorm (per client) 5493 */ 5494 struct ustorm_per_queue_stats { 5495 struct regpair ucast_no_buff_bytes; 5496 struct regpair mcast_no_buff_bytes; 5497 struct regpair bcast_no_buff_bytes; 5498 __le32 ucast_no_buff_pkts; 5499 __le32 mcast_no_buff_pkts; 5500 __le32 bcast_no_buff_pkts; 5501 __le32 coalesced_pkts; 5502 struct regpair coalesced_bytes; 5503 __le32 coalesced_events; 5504 __le32 coalesced_aborts; 5505 }; 5506 5507 /* 5508 * Protocol-common statistics collected by the Xstorm (per client) 5509 */ 5510 struct xstorm_per_queue_stats { 5511 struct regpair ucast_bytes_sent; 5512 struct regpair mcast_bytes_sent; 5513 struct regpair bcast_bytes_sent; 5514 __le32 ucast_pkts_sent; 5515 __le32 mcast_pkts_sent; 5516 __le32 bcast_pkts_sent; 5517 __le32 error_drop_pkts; 5518 }; 5519 5520 /* 5521 * 5522 */ 5523 struct per_queue_stats { 5524 struct tstorm_per_queue_stats tstorm_queue_statistics; 5525 struct ustorm_per_queue_stats ustorm_queue_statistics; 5526 struct xstorm_per_queue_stats xstorm_queue_statistics; 5527 }; 5528 5529 5530 /* 5531 * FW version stored in first line of pram 5532 */ 5533 struct pram_fw_version { 5534 u8 major; 5535 u8 minor; 5536 u8 revision; 5537 u8 engineering; 5538 u8 flags; 5539 #define PRAM_FW_VERSION_OPTIMIZED (0x1<<0) 5540 #define PRAM_FW_VERSION_OPTIMIZED_SHIFT 0 5541 #define PRAM_FW_VERSION_STORM_ID (0x3<<1) 5542 #define PRAM_FW_VERSION_STORM_ID_SHIFT 1 5543 #define PRAM_FW_VERSION_BIG_ENDIEN (0x1<<3) 5544 #define PRAM_FW_VERSION_BIG_ENDIEN_SHIFT 3 5545 #define PRAM_FW_VERSION_CHIP_VERSION (0x3<<4) 5546 #define PRAM_FW_VERSION_CHIP_VERSION_SHIFT 4 5547 #define __PRAM_FW_VERSION_RESERVED0 (0x3<<6) 5548 #define __PRAM_FW_VERSION_RESERVED0_SHIFT 6 5549 }; 5550 5551 5552 /* 5553 * Ethernet slow path element 5554 */ 5555 union protocol_common_specific_data { 5556 u8 protocol_data[8]; 5557 struct regpair phy_address; 5558 struct regpair mac_config_addr; 5559 struct afex_vif_list_ramrod_data afex_vif_list_data; 5560 }; 5561 5562 /* 5563 * The send queue element 5564 */ 5565 struct protocol_common_spe { 5566 struct spe_hdr hdr; 5567 union protocol_common_specific_data data; 5568 }; 5569 5570 /* 5571 * The send queue element 5572 */ 5573 struct slow_path_element { 5574 struct spe_hdr hdr; 5575 struct regpair protocol_data; 5576 }; 5577 5578 5579 /* 5580 * Protocol-common statistics counter 5581 */ 5582 struct stats_counter { 5583 __le16 xstats_counter; 5584 __le16 reserved0; 5585 __le32 reserved1; 5586 __le16 tstats_counter; 5587 __le16 reserved2; 5588 __le32 reserved3; 5589 __le16 ustats_counter; 5590 __le16 reserved4; 5591 __le32 reserved5; 5592 __le16 cstats_counter; 5593 __le16 reserved6; 5594 __le32 reserved7; 5595 }; 5596 5597 5598 /* 5599 * 5600 */ 5601 struct stats_query_entry { 5602 u8 kind; 5603 u8 index; 5604 __le16 funcID; 5605 __le32 reserved; 5606 struct regpair address; 5607 }; 5608 5609 /* 5610 * statistic command 5611 */ 5612 struct stats_query_cmd_group { 5613 struct stats_query_entry query[STATS_QUERY_CMD_COUNT]; 5614 }; 5615 5616 5617 /* 5618 * statistic command header 5619 */ 5620 struct stats_query_header { 5621 u8 cmd_num; 5622 u8 reserved0; 5623 __le16 drv_stats_counter; 5624 __le32 reserved1; 5625 struct regpair stats_counters_addrs; 5626 }; 5627 5628 5629 /* 5630 * Types of statistcis query entry 5631 */ 5632 enum stats_query_type { 5633 STATS_TYPE_QUEUE, 5634 STATS_TYPE_PORT, 5635 STATS_TYPE_PF, 5636 STATS_TYPE_TOE, 5637 STATS_TYPE_FCOE, 5638 MAX_STATS_QUERY_TYPE 5639 }; 5640 5641 5642 /* 5643 * Indicate of the function status block state 5644 */ 5645 enum status_block_state { 5646 SB_DISABLED, 5647 SB_ENABLED, 5648 SB_CLEANED, 5649 MAX_STATUS_BLOCK_STATE 5650 }; 5651 5652 5653 /* 5654 * Storm IDs (including attentions for IGU related enums) 5655 */ 5656 enum storm_id { 5657 USTORM_ID, 5658 CSTORM_ID, 5659 XSTORM_ID, 5660 TSTORM_ID, 5661 ATTENTION_ID, 5662 MAX_STORM_ID 5663 }; 5664 5665 5666 /* 5667 * Taffic types used in ETS and flow control algorithms 5668 */ 5669 enum traffic_type { 5670 LLFC_TRAFFIC_TYPE_NW, 5671 LLFC_TRAFFIC_TYPE_FCOE, 5672 LLFC_TRAFFIC_TYPE_ISCSI, 5673 MAX_TRAFFIC_TYPE 5674 }; 5675 5676 5677 /* 5678 * zone A per-queue data 5679 */ 5680 struct tstorm_queue_zone_data { 5681 struct regpair reserved[4]; 5682 }; 5683 5684 5685 /* 5686 * zone B per-VF data 5687 */ 5688 struct tstorm_vf_zone_data { 5689 struct regpair reserved; 5690 }; 5691 5692 5693 /* 5694 * zone A per-queue data 5695 */ 5696 struct ustorm_queue_zone_data { 5697 struct ustorm_eth_rx_producers eth_rx_producers; 5698 struct regpair reserved[3]; 5699 }; 5700 5701 5702 /* 5703 * zone B per-VF data 5704 */ 5705 struct ustorm_vf_zone_data { 5706 struct regpair reserved; 5707 }; 5708 5709 5710 /* 5711 * data per VF-PF channel 5712 */ 5713 struct vf_pf_channel_data { 5714 #if defined(__BIG_ENDIAN) 5715 u16 reserved0; 5716 u8 valid; 5717 u8 state; 5718 #elif defined(__LITTLE_ENDIAN) 5719 u8 state; 5720 u8 valid; 5721 u16 reserved0; 5722 #endif 5723 u32 reserved1; 5724 }; 5725 5726 5727 /* 5728 * State of VF-PF channel 5729 */ 5730 enum vf_pf_channel_state { 5731 VF_PF_CHANNEL_STATE_READY, 5732 VF_PF_CHANNEL_STATE_WAITING_FOR_ACK, 5733 MAX_VF_PF_CHANNEL_STATE 5734 }; 5735 5736 5737 /* 5738 * vif_list_rule_kind 5739 */ 5740 enum vif_list_rule_kind { 5741 VIF_LIST_RULE_SET, 5742 VIF_LIST_RULE_GET, 5743 VIF_LIST_RULE_CLEAR_ALL, 5744 VIF_LIST_RULE_CLEAR_FUNC, 5745 MAX_VIF_LIST_RULE_KIND 5746 }; 5747 5748 5749 /* 5750 * zone A per-queue data 5751 */ 5752 struct xstorm_queue_zone_data { 5753 struct regpair reserved[4]; 5754 }; 5755 5756 5757 /* 5758 * zone B per-VF data 5759 */ 5760 struct xstorm_vf_zone_data { 5761 struct regpair reserved; 5762 }; 5763 5764 #endif /* BNX2X_HSI_H */ 5765