1 /* bnx2x_hsi.h: Broadcom Everest network driver.
2  *
3  * Copyright (c) 2007-2013 Broadcom Corporation
4  *
5  * This program is free software; you can redistribute it and/or modify
6  * it under the terms of the GNU General Public License as published by
7  * the Free Software Foundation.
8  */
9 #ifndef BNX2X_HSI_H
10 #define BNX2X_HSI_H
11 
12 #include "bnx2x_fw_defs.h"
13 #include "bnx2x_mfw_req.h"
14 
15 #define FW_ENCODE_32BIT_PATTERN         0x1e1e1e1e
16 
17 struct license_key {
18 	u32 reserved[6];
19 
20 	u32 max_iscsi_conn;
21 #define BNX2X_MAX_ISCSI_TRGT_CONN_MASK	0xFFFF
22 #define BNX2X_MAX_ISCSI_TRGT_CONN_SHIFT	0
23 #define BNX2X_MAX_ISCSI_INIT_CONN_MASK	0xFFFF0000
24 #define BNX2X_MAX_ISCSI_INIT_CONN_SHIFT	16
25 
26 	u32 reserved_a;
27 
28 	u32 max_fcoe_conn;
29 #define BNX2X_MAX_FCOE_TRGT_CONN_MASK	0xFFFF
30 #define BNX2X_MAX_FCOE_TRGT_CONN_SHIFT	0
31 #define BNX2X_MAX_FCOE_INIT_CONN_MASK	0xFFFF0000
32 #define BNX2X_MAX_FCOE_INIT_CONN_SHIFT	16
33 
34 	u32 reserved_b[4];
35 };
36 
37 /****************************************************************************
38  * Shared HW configuration                                                  *
39  ****************************************************************************/
40 #define PIN_CFG_NA                          0x00000000
41 #define PIN_CFG_GPIO0_P0                    0x00000001
42 #define PIN_CFG_GPIO1_P0                    0x00000002
43 #define PIN_CFG_GPIO2_P0                    0x00000003
44 #define PIN_CFG_GPIO3_P0                    0x00000004
45 #define PIN_CFG_GPIO0_P1                    0x00000005
46 #define PIN_CFG_GPIO1_P1                    0x00000006
47 #define PIN_CFG_GPIO2_P1                    0x00000007
48 #define PIN_CFG_GPIO3_P1                    0x00000008
49 #define PIN_CFG_EPIO0                       0x00000009
50 #define PIN_CFG_EPIO1                       0x0000000a
51 #define PIN_CFG_EPIO2                       0x0000000b
52 #define PIN_CFG_EPIO3                       0x0000000c
53 #define PIN_CFG_EPIO4                       0x0000000d
54 #define PIN_CFG_EPIO5                       0x0000000e
55 #define PIN_CFG_EPIO6                       0x0000000f
56 #define PIN_CFG_EPIO7                       0x00000010
57 #define PIN_CFG_EPIO8                       0x00000011
58 #define PIN_CFG_EPIO9                       0x00000012
59 #define PIN_CFG_EPIO10                      0x00000013
60 #define PIN_CFG_EPIO11                      0x00000014
61 #define PIN_CFG_EPIO12                      0x00000015
62 #define PIN_CFG_EPIO13                      0x00000016
63 #define PIN_CFG_EPIO14                      0x00000017
64 #define PIN_CFG_EPIO15                      0x00000018
65 #define PIN_CFG_EPIO16                      0x00000019
66 #define PIN_CFG_EPIO17                      0x0000001a
67 #define PIN_CFG_EPIO18                      0x0000001b
68 #define PIN_CFG_EPIO19                      0x0000001c
69 #define PIN_CFG_EPIO20                      0x0000001d
70 #define PIN_CFG_EPIO21                      0x0000001e
71 #define PIN_CFG_EPIO22                      0x0000001f
72 #define PIN_CFG_EPIO23                      0x00000020
73 #define PIN_CFG_EPIO24                      0x00000021
74 #define PIN_CFG_EPIO25                      0x00000022
75 #define PIN_CFG_EPIO26                      0x00000023
76 #define PIN_CFG_EPIO27                      0x00000024
77 #define PIN_CFG_EPIO28                      0x00000025
78 #define PIN_CFG_EPIO29                      0x00000026
79 #define PIN_CFG_EPIO30                      0x00000027
80 #define PIN_CFG_EPIO31                      0x00000028
81 
82 /* EPIO definition */
83 #define EPIO_CFG_NA                         0x00000000
84 #define EPIO_CFG_EPIO0                      0x00000001
85 #define EPIO_CFG_EPIO1                      0x00000002
86 #define EPIO_CFG_EPIO2                      0x00000003
87 #define EPIO_CFG_EPIO3                      0x00000004
88 #define EPIO_CFG_EPIO4                      0x00000005
89 #define EPIO_CFG_EPIO5                      0x00000006
90 #define EPIO_CFG_EPIO6                      0x00000007
91 #define EPIO_CFG_EPIO7                      0x00000008
92 #define EPIO_CFG_EPIO8                      0x00000009
93 #define EPIO_CFG_EPIO9                      0x0000000a
94 #define EPIO_CFG_EPIO10                     0x0000000b
95 #define EPIO_CFG_EPIO11                     0x0000000c
96 #define EPIO_CFG_EPIO12                     0x0000000d
97 #define EPIO_CFG_EPIO13                     0x0000000e
98 #define EPIO_CFG_EPIO14                     0x0000000f
99 #define EPIO_CFG_EPIO15                     0x00000010
100 #define EPIO_CFG_EPIO16                     0x00000011
101 #define EPIO_CFG_EPIO17                     0x00000012
102 #define EPIO_CFG_EPIO18                     0x00000013
103 #define EPIO_CFG_EPIO19                     0x00000014
104 #define EPIO_CFG_EPIO20                     0x00000015
105 #define EPIO_CFG_EPIO21                     0x00000016
106 #define EPIO_CFG_EPIO22                     0x00000017
107 #define EPIO_CFG_EPIO23                     0x00000018
108 #define EPIO_CFG_EPIO24                     0x00000019
109 #define EPIO_CFG_EPIO25                     0x0000001a
110 #define EPIO_CFG_EPIO26                     0x0000001b
111 #define EPIO_CFG_EPIO27                     0x0000001c
112 #define EPIO_CFG_EPIO28                     0x0000001d
113 #define EPIO_CFG_EPIO29                     0x0000001e
114 #define EPIO_CFG_EPIO30                     0x0000001f
115 #define EPIO_CFG_EPIO31                     0x00000020
116 
117 struct mac_addr {
118 	u32 upper;
119 	u32 lower;
120 };
121 
122 struct shared_hw_cfg {			 /* NVRAM Offset */
123 	/* Up to 16 bytes of NULL-terminated string */
124 	u8  part_num[16];		    /* 0x104 */
125 
126 	u32 config;			/* 0x114 */
127 	#define SHARED_HW_CFG_MDIO_VOLTAGE_MASK             0x00000001
128 		#define SHARED_HW_CFG_MDIO_VOLTAGE_SHIFT             0
129 		#define SHARED_HW_CFG_MDIO_VOLTAGE_1_2V              0x00000000
130 		#define SHARED_HW_CFG_MDIO_VOLTAGE_2_5V              0x00000001
131 	#define SHARED_HW_CFG_MCP_RST_ON_CORE_RST_EN        0x00000002
132 
133 	#define SHARED_HW_CFG_PORT_SWAP                     0x00000004
134 
135 	#define SHARED_HW_CFG_BEACON_WOL_EN                 0x00000008
136 
137 	#define SHARED_HW_CFG_PCIE_GEN3_DISABLED            0x00000000
138 	#define SHARED_HW_CFG_PCIE_GEN3_ENABLED             0x00000010
139 
140 	#define SHARED_HW_CFG_MFW_SELECT_MASK               0x00000700
141 		#define SHARED_HW_CFG_MFW_SELECT_SHIFT               8
142 	/* Whatever MFW found in NVM
143 	   (if multiple found, priority order is: NC-SI, UMP, IPMI) */
144 		#define SHARED_HW_CFG_MFW_SELECT_DEFAULT             0x00000000
145 		#define SHARED_HW_CFG_MFW_SELECT_NC_SI               0x00000100
146 		#define SHARED_HW_CFG_MFW_SELECT_UMP                 0x00000200
147 		#define SHARED_HW_CFG_MFW_SELECT_IPMI                0x00000300
148 	/* Use SPIO4 as an arbiter between: 0-NC_SI, 1-IPMI
149 	  (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
150 		#define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_IPMI    0x00000400
151 	/* Use SPIO4 as an arbiter between: 0-UMP, 1-IPMI
152 	  (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
153 		#define SHARED_HW_CFG_MFW_SELECT_SPIO4_UMP_IPMI      0x00000500
154 	/* Use SPIO4 as an arbiter between: 0-NC-SI, 1-UMP
155 	  (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
156 		#define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_UMP     0x00000600
157 
158 	#define SHARED_HW_CFG_LED_MODE_MASK                 0x000f0000
159 		#define SHARED_HW_CFG_LED_MODE_SHIFT                 16
160 		#define SHARED_HW_CFG_LED_MAC1                       0x00000000
161 		#define SHARED_HW_CFG_LED_PHY1                       0x00010000
162 		#define SHARED_HW_CFG_LED_PHY2                       0x00020000
163 		#define SHARED_HW_CFG_LED_PHY3                       0x00030000
164 		#define SHARED_HW_CFG_LED_MAC2                       0x00040000
165 		#define SHARED_HW_CFG_LED_PHY4                       0x00050000
166 		#define SHARED_HW_CFG_LED_PHY5                       0x00060000
167 		#define SHARED_HW_CFG_LED_PHY6                       0x00070000
168 		#define SHARED_HW_CFG_LED_MAC3                       0x00080000
169 		#define SHARED_HW_CFG_LED_PHY7                       0x00090000
170 		#define SHARED_HW_CFG_LED_PHY9                       0x000a0000
171 		#define SHARED_HW_CFG_LED_PHY11                      0x000b0000
172 		#define SHARED_HW_CFG_LED_MAC4                       0x000c0000
173 		#define SHARED_HW_CFG_LED_PHY8                       0x000d0000
174 		#define SHARED_HW_CFG_LED_EXTPHY1                    0x000e0000
175 		#define SHARED_HW_CFG_LED_EXTPHY2                    0x000f0000
176 
177 
178 	#define SHARED_HW_CFG_AN_ENABLE_MASK                0x3f000000
179 		#define SHARED_HW_CFG_AN_ENABLE_SHIFT                24
180 		#define SHARED_HW_CFG_AN_ENABLE_CL37                 0x01000000
181 		#define SHARED_HW_CFG_AN_ENABLE_CL73                 0x02000000
182 		#define SHARED_HW_CFG_AN_ENABLE_BAM                  0x04000000
183 		#define SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION   0x08000000
184 		#define SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT  0x10000000
185 		#define SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY           0x20000000
186 
187 	#define SHARED_HW_CFG_SRIOV_MASK                    0x40000000
188 		#define SHARED_HW_CFG_SRIOV_DISABLED                 0x00000000
189 		#define SHARED_HW_CFG_SRIOV_ENABLED                  0x40000000
190 
191 	#define SHARED_HW_CFG_ATC_MASK                      0x80000000
192 		#define SHARED_HW_CFG_ATC_DISABLED                   0x00000000
193 		#define SHARED_HW_CFG_ATC_ENABLED                    0x80000000
194 
195 	u32 config2;			    /* 0x118 */
196 	/* one time auto detect grace period (in sec) */
197 	#define SHARED_HW_CFG_GRACE_PERIOD_MASK             0x000000ff
198 	#define SHARED_HW_CFG_GRACE_PERIOD_SHIFT                     0
199 
200 	#define SHARED_HW_CFG_PCIE_GEN2_ENABLED             0x00000100
201 	#define SHARED_HW_CFG_PCIE_GEN2_DISABLED            0x00000000
202 
203 	/* The default value for the core clock is 250MHz and it is
204 	   achieved by setting the clock change to 4 */
205 	#define SHARED_HW_CFG_CLOCK_CHANGE_MASK             0x00000e00
206 	#define SHARED_HW_CFG_CLOCK_CHANGE_SHIFT                     9
207 
208 	#define SHARED_HW_CFG_SMBUS_TIMING_MASK             0x00001000
209 		#define SHARED_HW_CFG_SMBUS_TIMING_100KHZ            0x00000000
210 		#define SHARED_HW_CFG_SMBUS_TIMING_400KHZ            0x00001000
211 
212 	#define SHARED_HW_CFG_HIDE_PORT1                    0x00002000
213 
214 	#define SHARED_HW_CFG_WOL_CAPABLE_MASK              0x00004000
215 		#define SHARED_HW_CFG_WOL_CAPABLE_DISABLED           0x00000000
216 		#define SHARED_HW_CFG_WOL_CAPABLE_ENABLED            0x00004000
217 
218 		/* Output low when PERST is asserted */
219 	#define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_MASK       0x00008000
220 		#define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_DISABLED    0x00000000
221 		#define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_ENABLED     0x00008000
222 
223 	#define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_MASK    0x00070000
224 		#define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_SHIFT    16
225 		#define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_HW       0x00000000
226 		#define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_0DB      0x00010000
227 		#define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_3_5DB    0x00020000
228 		#define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_6_0DB    0x00030000
229 
230 	/*  The fan failure mechanism is usually related to the PHY type
231 	      since the power consumption of the board is determined by the PHY.
232 	      Currently, fan is required for most designs with SFX7101, BCM8727
233 	      and BCM8481. If a fan is not required for a board which uses one
234 	      of those PHYs, this field should be set to "Disabled". If a fan is
235 	      required for a different PHY type, this option should be set to
236 	      "Enabled". The fan failure indication is expected on SPIO5 */
237 	#define SHARED_HW_CFG_FAN_FAILURE_MASK              0x00180000
238 		#define SHARED_HW_CFG_FAN_FAILURE_SHIFT              19
239 		#define SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE           0x00000000
240 		#define SHARED_HW_CFG_FAN_FAILURE_DISABLED           0x00080000
241 		#define SHARED_HW_CFG_FAN_FAILURE_ENABLED            0x00100000
242 
243 		/* ASPM Power Management support */
244 	#define SHARED_HW_CFG_ASPM_SUPPORT_MASK             0x00600000
245 		#define SHARED_HW_CFG_ASPM_SUPPORT_SHIFT             21
246 		#define SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_ENABLED    0x00000000
247 		#define SHARED_HW_CFG_ASPM_SUPPORT_L0S_DISABLED      0x00200000
248 		#define SHARED_HW_CFG_ASPM_SUPPORT_L1_DISABLED       0x00400000
249 		#define SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_DISABLED   0x00600000
250 
251 	/* The value of PM_TL_IGNORE_REQS (bit0) in PCI register
252 	   tl_control_0 (register 0x2800) */
253 	#define SHARED_HW_CFG_PREVENT_L1_ENTRY_MASK         0x00800000
254 		#define SHARED_HW_CFG_PREVENT_L1_ENTRY_DISABLED      0x00000000
255 		#define SHARED_HW_CFG_PREVENT_L1_ENTRY_ENABLED       0x00800000
256 
257 	#define SHARED_HW_CFG_PORT_MODE_MASK                0x01000000
258 		#define SHARED_HW_CFG_PORT_MODE_2                    0x00000000
259 		#define SHARED_HW_CFG_PORT_MODE_4                    0x01000000
260 
261 	#define SHARED_HW_CFG_PATH_SWAP_MASK                0x02000000
262 		#define SHARED_HW_CFG_PATH_SWAP_DISABLED             0x00000000
263 		#define SHARED_HW_CFG_PATH_SWAP_ENABLED              0x02000000
264 
265 	/*  Set the MDC/MDIO access for the first external phy */
266 	#define SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK         0x1C000000
267 		#define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT         26
268 		#define SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE      0x00000000
269 		#define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0         0x04000000
270 		#define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1         0x08000000
271 		#define SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH          0x0c000000
272 		#define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED       0x10000000
273 
274 	/*  Set the MDC/MDIO access for the second external phy */
275 	#define SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK         0xE0000000
276 		#define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT         29
277 		#define SHARED_HW_CFG_MDC_MDIO_ACCESS2_PHY_TYPE      0x00000000
278 		#define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC0         0x20000000
279 		#define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC1         0x40000000
280 		#define SHARED_HW_CFG_MDC_MDIO_ACCESS2_BOTH          0x60000000
281 		#define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SWAPPED       0x80000000
282 
283 
284 	u32 power_dissipated;			/* 0x11c */
285 	#define SHARED_HW_CFG_POWER_MGNT_SCALE_MASK         0x00ff0000
286 		#define SHARED_HW_CFG_POWER_MGNT_SCALE_SHIFT         16
287 		#define SHARED_HW_CFG_POWER_MGNT_UNKNOWN_SCALE       0x00000000
288 		#define SHARED_HW_CFG_POWER_MGNT_DOT_1_WATT          0x00010000
289 		#define SHARED_HW_CFG_POWER_MGNT_DOT_01_WATT         0x00020000
290 		#define SHARED_HW_CFG_POWER_MGNT_DOT_001_WATT        0x00030000
291 
292 	#define SHARED_HW_CFG_POWER_DIS_CMN_MASK            0xff000000
293 	#define SHARED_HW_CFG_POWER_DIS_CMN_SHIFT                    24
294 
295 	u32 ump_nc_si_config;			/* 0x120 */
296 	#define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MASK       0x00000003
297 		#define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_SHIFT       0
298 		#define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MAC         0x00000000
299 		#define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_PHY         0x00000001
300 		#define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MII         0x00000000
301 		#define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_RMII        0x00000002
302 
303 	#define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_MASK       0x00000f00
304 		#define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_SHIFT       8
305 
306 	#define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_MASK   0x00ff0000
307 		#define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_SHIFT   16
308 		#define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_NONE    0x00000000
309 		#define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_BCM5221 0x00010000
310 
311 	u32 board;			/* 0x124 */
312 	#define SHARED_HW_CFG_E3_I2C_MUX0_MASK              0x0000003F
313 	#define SHARED_HW_CFG_E3_I2C_MUX0_SHIFT                      0
314 	#define SHARED_HW_CFG_E3_I2C_MUX1_MASK              0x00000FC0
315 	#define SHARED_HW_CFG_E3_I2C_MUX1_SHIFT                      6
316 	/* Use the PIN_CFG_XXX defines on top */
317 	#define SHARED_HW_CFG_BOARD_REV_MASK                0x00ff0000
318 	#define SHARED_HW_CFG_BOARD_REV_SHIFT                        16
319 
320 	#define SHARED_HW_CFG_BOARD_MAJOR_VER_MASK          0x0f000000
321 	#define SHARED_HW_CFG_BOARD_MAJOR_VER_SHIFT                  24
322 
323 	#define SHARED_HW_CFG_BOARD_MINOR_VER_MASK          0xf0000000
324 	#define SHARED_HW_CFG_BOARD_MINOR_VER_SHIFT                  28
325 
326 	u32 wc_lane_config;				    /* 0x128 */
327 	#define SHARED_HW_CFG_LANE_SWAP_CFG_MASK            0x0000FFFF
328 		#define SHARED_HW_CFG_LANE_SWAP_CFG_SHIFT            0
329 		#define SHARED_HW_CFG_LANE_SWAP_CFG_32103210         0x00001b1b
330 		#define SHARED_HW_CFG_LANE_SWAP_CFG_32100123         0x00001be4
331 		#define SHARED_HW_CFG_LANE_SWAP_CFG_01233210         0x0000e41b
332 		#define SHARED_HW_CFG_LANE_SWAP_CFG_01230123         0x0000e4e4
333 	#define SHARED_HW_CFG_LANE_SWAP_CFG_TX_MASK         0x000000FF
334 	#define SHARED_HW_CFG_LANE_SWAP_CFG_TX_SHIFT                 0
335 	#define SHARED_HW_CFG_LANE_SWAP_CFG_RX_MASK         0x0000FF00
336 	#define SHARED_HW_CFG_LANE_SWAP_CFG_RX_SHIFT                 8
337 
338 	/* TX lane Polarity swap */
339 	#define SHARED_HW_CFG_TX_LANE0_POL_FLIP_ENABLED     0x00010000
340 	#define SHARED_HW_CFG_TX_LANE1_POL_FLIP_ENABLED     0x00020000
341 	#define SHARED_HW_CFG_TX_LANE2_POL_FLIP_ENABLED     0x00040000
342 	#define SHARED_HW_CFG_TX_LANE3_POL_FLIP_ENABLED     0x00080000
343 	/* TX lane Polarity swap */
344 	#define SHARED_HW_CFG_RX_LANE0_POL_FLIP_ENABLED     0x00100000
345 	#define SHARED_HW_CFG_RX_LANE1_POL_FLIP_ENABLED     0x00200000
346 	#define SHARED_HW_CFG_RX_LANE2_POL_FLIP_ENABLED     0x00400000
347 	#define SHARED_HW_CFG_RX_LANE3_POL_FLIP_ENABLED     0x00800000
348 
349 	/*  Selects the port layout of the board */
350 	#define SHARED_HW_CFG_E3_PORT_LAYOUT_MASK           0x0F000000
351 		#define SHARED_HW_CFG_E3_PORT_LAYOUT_SHIFT           24
352 		#define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_01           0x00000000
353 		#define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_10           0x01000000
354 		#define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_0123         0x02000000
355 		#define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_1032         0x03000000
356 		#define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_2301         0x04000000
357 		#define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_3210         0x05000000
358 };
359 
360 
361 /****************************************************************************
362  * Port HW configuration                                                    *
363  ****************************************************************************/
364 struct port_hw_cfg {		    /* port 0: 0x12c  port 1: 0x2bc */
365 
366 	u32 pci_id;
367 	#define PORT_HW_CFG_PCI_VENDOR_ID_MASK              0xffff0000
368 	#define PORT_HW_CFG_PCI_DEVICE_ID_MASK              0x0000ffff
369 
370 	u32 pci_sub_id;
371 	#define PORT_HW_CFG_PCI_SUBSYS_DEVICE_ID_MASK       0xffff0000
372 	#define PORT_HW_CFG_PCI_SUBSYS_VENDOR_ID_MASK       0x0000ffff
373 
374 	u32 power_dissipated;
375 	#define PORT_HW_CFG_POWER_DIS_D0_MASK               0x000000ff
376 	#define PORT_HW_CFG_POWER_DIS_D0_SHIFT                       0
377 	#define PORT_HW_CFG_POWER_DIS_D1_MASK               0x0000ff00
378 	#define PORT_HW_CFG_POWER_DIS_D1_SHIFT                       8
379 	#define PORT_HW_CFG_POWER_DIS_D2_MASK               0x00ff0000
380 	#define PORT_HW_CFG_POWER_DIS_D2_SHIFT                       16
381 	#define PORT_HW_CFG_POWER_DIS_D3_MASK               0xff000000
382 	#define PORT_HW_CFG_POWER_DIS_D3_SHIFT                       24
383 
384 	u32 power_consumed;
385 	#define PORT_HW_CFG_POWER_CONS_D0_MASK              0x000000ff
386 	#define PORT_HW_CFG_POWER_CONS_D0_SHIFT                      0
387 	#define PORT_HW_CFG_POWER_CONS_D1_MASK              0x0000ff00
388 	#define PORT_HW_CFG_POWER_CONS_D1_SHIFT                      8
389 	#define PORT_HW_CFG_POWER_CONS_D2_MASK              0x00ff0000
390 	#define PORT_HW_CFG_POWER_CONS_D2_SHIFT                      16
391 	#define PORT_HW_CFG_POWER_CONS_D3_MASK              0xff000000
392 	#define PORT_HW_CFG_POWER_CONS_D3_SHIFT                      24
393 
394 	u32 mac_upper;
395 	#define PORT_HW_CFG_UPPERMAC_MASK                   0x0000ffff
396 	#define PORT_HW_CFG_UPPERMAC_SHIFT                           0
397 	u32 mac_lower;
398 
399 	u32 iscsi_mac_upper;  /* Upper 16 bits are always zeroes */
400 	u32 iscsi_mac_lower;
401 
402 	u32 rdma_mac_upper;   /* Upper 16 bits are always zeroes */
403 	u32 rdma_mac_lower;
404 
405 	u32 serdes_config;
406 	#define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_MASK 0x0000ffff
407 	#define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_SHIFT         0
408 
409 	#define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK    0xffff0000
410 	#define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT            16
411 
412 
413 	/*  Default values: 2P-64, 4P-32 */
414 	u32 pf_config;					    /* 0x158 */
415 	#define PORT_HW_CFG_PF_NUM_VF_MASK                  0x0000007F
416 	#define PORT_HW_CFG_PF_NUM_VF_SHIFT                          0
417 
418 	/*  Default values: 17 */
419 	#define PORT_HW_CFG_PF_NUM_MSIX_VECTORS_MASK        0x00007F00
420 	#define PORT_HW_CFG_PF_NUM_MSIX_VECTORS_SHIFT                8
421 
422 	#define PORT_HW_CFG_ENABLE_FLR_MASK                 0x00010000
423 	#define PORT_HW_CFG_FLR_ENABLED                     0x00010000
424 
425 	u32 vf_config;					    /* 0x15C */
426 	#define PORT_HW_CFG_VF_NUM_MSIX_VECTORS_MASK        0x0000007F
427 	#define PORT_HW_CFG_VF_NUM_MSIX_VECTORS_SHIFT                0
428 
429 	#define PORT_HW_CFG_VF_PCI_DEVICE_ID_MASK           0xFFFF0000
430 	#define PORT_HW_CFG_VF_PCI_DEVICE_ID_SHIFT                   16
431 
432 	u32 mf_pci_id;					    /* 0x160 */
433 	#define PORT_HW_CFG_MF_PCI_DEVICE_ID_MASK           0x0000FFFF
434 	#define PORT_HW_CFG_MF_PCI_DEVICE_ID_SHIFT                   0
435 
436 	/*  Controls the TX laser of the SFP+ module */
437 	u32 sfp_ctrl;					    /* 0x164 */
438 	#define PORT_HW_CFG_TX_LASER_MASK                   0x000000FF
439 		#define PORT_HW_CFG_TX_LASER_SHIFT                   0
440 		#define PORT_HW_CFG_TX_LASER_MDIO                    0x00000000
441 		#define PORT_HW_CFG_TX_LASER_GPIO0                   0x00000001
442 		#define PORT_HW_CFG_TX_LASER_GPIO1                   0x00000002
443 		#define PORT_HW_CFG_TX_LASER_GPIO2                   0x00000003
444 		#define PORT_HW_CFG_TX_LASER_GPIO3                   0x00000004
445 
446 	/*  Controls the fault module LED of the SFP+ */
447 	#define PORT_HW_CFG_FAULT_MODULE_LED_MASK           0x0000FF00
448 		#define PORT_HW_CFG_FAULT_MODULE_LED_SHIFT           8
449 		#define PORT_HW_CFG_FAULT_MODULE_LED_GPIO0           0x00000000
450 		#define PORT_HW_CFG_FAULT_MODULE_LED_GPIO1           0x00000100
451 		#define PORT_HW_CFG_FAULT_MODULE_LED_GPIO2           0x00000200
452 		#define PORT_HW_CFG_FAULT_MODULE_LED_GPIO3           0x00000300
453 		#define PORT_HW_CFG_FAULT_MODULE_LED_DISABLED        0x00000400
454 
455 	/*  The output pin TX_DIS that controls the TX laser of the SFP+
456 	  module. Use the PIN_CFG_XXX defines on top */
457 	u32 e3_sfp_ctrl;				    /* 0x168 */
458 	#define PORT_HW_CFG_E3_TX_LASER_MASK                0x000000FF
459 	#define PORT_HW_CFG_E3_TX_LASER_SHIFT                        0
460 
461 	/*  The output pin for SFPP_TYPE which turns on the Fault module LED */
462 	#define PORT_HW_CFG_E3_FAULT_MDL_LED_MASK           0x0000FF00
463 	#define PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT                   8
464 
465 	/*  The input pin MOD_ABS that indicates whether SFP+ module is
466 	  present or not. Use the PIN_CFG_XXX defines on top */
467 	#define PORT_HW_CFG_E3_MOD_ABS_MASK                 0x00FF0000
468 	#define PORT_HW_CFG_E3_MOD_ABS_SHIFT                         16
469 
470 	/*  The output pin PWRDIS_SFP_X which disable the power of the SFP+
471 	  module. Use the PIN_CFG_XXX defines on top */
472 	#define PORT_HW_CFG_E3_PWR_DIS_MASK                 0xFF000000
473 	#define PORT_HW_CFG_E3_PWR_DIS_SHIFT                         24
474 
475 	/*
476 	 * The input pin which signals module transmit fault. Use the
477 	 * PIN_CFG_XXX defines on top
478 	 */
479 	u32 e3_cmn_pin_cfg;				    /* 0x16C */
480 	#define PORT_HW_CFG_E3_TX_FAULT_MASK                0x000000FF
481 	#define PORT_HW_CFG_E3_TX_FAULT_SHIFT                        0
482 
483 	/*  The output pin which reset the PHY. Use the PIN_CFG_XXX defines on
484 	 top */
485 	#define PORT_HW_CFG_E3_PHY_RESET_MASK               0x0000FF00
486 	#define PORT_HW_CFG_E3_PHY_RESET_SHIFT                       8
487 
488 	/*
489 	 * The output pin which powers down the PHY. Use the PIN_CFG_XXX
490 	 * defines on top
491 	 */
492 	#define PORT_HW_CFG_E3_PWR_DOWN_MASK                0x00FF0000
493 	#define PORT_HW_CFG_E3_PWR_DOWN_SHIFT                        16
494 
495 	/*  The output pin values BSC_SEL which selects the I2C for this port
496 	  in the I2C Mux */
497 	#define PORT_HW_CFG_E3_I2C_MUX0_MASK                0x01000000
498 	#define PORT_HW_CFG_E3_I2C_MUX1_MASK                0x02000000
499 
500 
501 	/*
502 	 * The input pin I_FAULT which indicate over-current has occurred.
503 	 * Use the PIN_CFG_XXX defines on top
504 	 */
505 	u32 e3_cmn_pin_cfg1;				    /* 0x170 */
506 	#define PORT_HW_CFG_E3_OVER_CURRENT_MASK            0x000000FF
507 	#define PORT_HW_CFG_E3_OVER_CURRENT_SHIFT                    0
508 
509 	/*  pause on host ring */
510 	u32 generic_features;                               /* 0x174 */
511 	#define PORT_HW_CFG_PAUSE_ON_HOST_RING_MASK                   0x00000001
512 	#define PORT_HW_CFG_PAUSE_ON_HOST_RING_SHIFT                  0
513 	#define PORT_HW_CFG_PAUSE_ON_HOST_RING_DISABLED               0x00000000
514 	#define PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED                0x00000001
515 
516 	/* SFP+ Tx Equalization: NIC recommended and tested value is 0xBEB2
517 	 * LOM recommended and tested value is 0xBEB2. Using a different
518 	 * value means using a value not tested by BRCM
519 	 */
520 	u32 sfi_tap_values;                                 /* 0x178 */
521 	#define PORT_HW_CFG_TX_EQUALIZATION_MASK                      0x0000FFFF
522 	#define PORT_HW_CFG_TX_EQUALIZATION_SHIFT                     0
523 
524 	/* SFP+ Tx driver broadcast IDRIVER: NIC recommended and tested
525 	 * value is 0x2. LOM recommended and tested value is 0x2. Using a
526 	 * different value means using a value not tested by BRCM
527 	 */
528 	#define PORT_HW_CFG_TX_DRV_BROADCAST_MASK                     0x000F0000
529 	#define PORT_HW_CFG_TX_DRV_BROADCAST_SHIFT                    16
530 
531 	u32 reserved0[5];				    /* 0x17c */
532 
533 	u32 aeu_int_mask;				    /* 0x190 */
534 
535 	u32 media_type;					    /* 0x194 */
536 	#define PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK            0x000000FF
537 	#define PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT                    0
538 
539 	#define PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK            0x0000FF00
540 	#define PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT                    8
541 
542 	#define PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK            0x00FF0000
543 	#define PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT                    16
544 
545 	/*  4 times 16 bits for all 4 lanes. In case external PHY is present
546 	      (not direct mode), those values will not take effect on the 4 XGXS
547 	      lanes. For some external PHYs (such as 8706 and 8726) the values
548 	      will be used to configure the external PHY  in those cases, not
549 	      all 4 values are needed. */
550 	u16 xgxs_config_rx[4];			/* 0x198 */
551 	u16 xgxs_config_tx[4];			/* 0x1A0 */
552 
553 	/* For storing FCOE mac on shared memory */
554 	u32 fcoe_fip_mac_upper;
555 	#define PORT_HW_CFG_FCOE_UPPERMAC_MASK              0x0000ffff
556 	#define PORT_HW_CFG_FCOE_UPPERMAC_SHIFT                      0
557 	u32 fcoe_fip_mac_lower;
558 
559 	u32 fcoe_wwn_port_name_upper;
560 	u32 fcoe_wwn_port_name_lower;
561 
562 	u32 fcoe_wwn_node_name_upper;
563 	u32 fcoe_wwn_node_name_lower;
564 
565 	u32 Reserved1[49];				    /* 0x1C0 */
566 
567 	/*  Enable RJ45 magjack pair swapping on 10GBase-T PHY (0=default),
568 	      84833 only */
569 	u32 xgbt_phy_cfg;				    /* 0x284 */
570 	#define PORT_HW_CFG_RJ45_PAIR_SWAP_MASK             0x000000FF
571 	#define PORT_HW_CFG_RJ45_PAIR_SWAP_SHIFT                     0
572 
573 		u32 default_cfg;			    /* 0x288 */
574 	#define PORT_HW_CFG_GPIO0_CONFIG_MASK               0x00000003
575 		#define PORT_HW_CFG_GPIO0_CONFIG_SHIFT               0
576 		#define PORT_HW_CFG_GPIO0_CONFIG_NA                  0x00000000
577 		#define PORT_HW_CFG_GPIO0_CONFIG_LOW                 0x00000001
578 		#define PORT_HW_CFG_GPIO0_CONFIG_HIGH                0x00000002
579 		#define PORT_HW_CFG_GPIO0_CONFIG_INPUT               0x00000003
580 
581 	#define PORT_HW_CFG_GPIO1_CONFIG_MASK               0x0000000C
582 		#define PORT_HW_CFG_GPIO1_CONFIG_SHIFT               2
583 		#define PORT_HW_CFG_GPIO1_CONFIG_NA                  0x00000000
584 		#define PORT_HW_CFG_GPIO1_CONFIG_LOW                 0x00000004
585 		#define PORT_HW_CFG_GPIO1_CONFIG_HIGH                0x00000008
586 		#define PORT_HW_CFG_GPIO1_CONFIG_INPUT               0x0000000c
587 
588 	#define PORT_HW_CFG_GPIO2_CONFIG_MASK               0x00000030
589 		#define PORT_HW_CFG_GPIO2_CONFIG_SHIFT               4
590 		#define PORT_HW_CFG_GPIO2_CONFIG_NA                  0x00000000
591 		#define PORT_HW_CFG_GPIO2_CONFIG_LOW                 0x00000010
592 		#define PORT_HW_CFG_GPIO2_CONFIG_HIGH                0x00000020
593 		#define PORT_HW_CFG_GPIO2_CONFIG_INPUT               0x00000030
594 
595 	#define PORT_HW_CFG_GPIO3_CONFIG_MASK               0x000000C0
596 		#define PORT_HW_CFG_GPIO3_CONFIG_SHIFT               6
597 		#define PORT_HW_CFG_GPIO3_CONFIG_NA                  0x00000000
598 		#define PORT_HW_CFG_GPIO3_CONFIG_LOW                 0x00000040
599 		#define PORT_HW_CFG_GPIO3_CONFIG_HIGH                0x00000080
600 		#define PORT_HW_CFG_GPIO3_CONFIG_INPUT               0x000000c0
601 
602 	/*  When KR link is required to be set to force which is not
603 	      KR-compliant, this parameter determine what is the trigger for it.
604 	      When GPIO is selected, low input will force the speed. Currently
605 	      default speed is 1G. In the future, it may be widen to select the
606 	      forced speed in with another parameter. Note when force-1G is
607 	      enabled, it override option 56: Link Speed option. */
608 	#define PORT_HW_CFG_FORCE_KR_ENABLER_MASK           0x00000F00
609 		#define PORT_HW_CFG_FORCE_KR_ENABLER_SHIFT           8
610 		#define PORT_HW_CFG_FORCE_KR_ENABLER_NOT_FORCED      0x00000000
611 		#define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P0        0x00000100
612 		#define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P0        0x00000200
613 		#define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P0        0x00000300
614 		#define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P0        0x00000400
615 		#define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P1        0x00000500
616 		#define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P1        0x00000600
617 		#define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P1        0x00000700
618 		#define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P1        0x00000800
619 		#define PORT_HW_CFG_FORCE_KR_ENABLER_FORCED          0x00000900
620 	/*  Enable to determine with which GPIO to reset the external phy */
621 	#define PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK           0x000F0000
622 		#define PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT           16
623 		#define PORT_HW_CFG_EXT_PHY_GPIO_RST_PHY_TYPE        0x00000000
624 		#define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0        0x00010000
625 		#define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0        0x00020000
626 		#define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0        0x00030000
627 		#define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0        0x00040000
628 		#define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1        0x00050000
629 		#define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1        0x00060000
630 		#define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1        0x00070000
631 		#define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1        0x00080000
632 
633 	/*  Enable BAM on KR */
634 	#define PORT_HW_CFG_ENABLE_BAM_ON_KR_MASK           0x00100000
635 	#define PORT_HW_CFG_ENABLE_BAM_ON_KR_SHIFT                   20
636 	#define PORT_HW_CFG_ENABLE_BAM_ON_KR_DISABLED                0x00000000
637 	#define PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED                 0x00100000
638 
639 	/*  Enable Common Mode Sense */
640 	#define PORT_HW_CFG_ENABLE_CMS_MASK                 0x00200000
641 	#define PORT_HW_CFG_ENABLE_CMS_SHIFT                         21
642 	#define PORT_HW_CFG_ENABLE_CMS_DISABLED                      0x00000000
643 	#define PORT_HW_CFG_ENABLE_CMS_ENABLED                       0x00200000
644 
645 	/*  Determine the Serdes electrical interface   */
646 	#define PORT_HW_CFG_NET_SERDES_IF_MASK              0x0F000000
647 	#define PORT_HW_CFG_NET_SERDES_IF_SHIFT                      24
648 	#define PORT_HW_CFG_NET_SERDES_IF_SGMII                      0x00000000
649 	#define PORT_HW_CFG_NET_SERDES_IF_XFI                        0x01000000
650 	#define PORT_HW_CFG_NET_SERDES_IF_SFI                        0x02000000
651 	#define PORT_HW_CFG_NET_SERDES_IF_KR                         0x03000000
652 	#define PORT_HW_CFG_NET_SERDES_IF_DXGXS                      0x04000000
653 	#define PORT_HW_CFG_NET_SERDES_IF_KR2                        0x05000000
654 
655 
656 	u32 speed_capability_mask2;			    /* 0x28C */
657 	#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_MASK       0x0000FFFF
658 		#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_SHIFT       0
659 		#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10M_FULL    0x00000001
660 		#define PORT_HW_CFG_SPEED_CAPABILITY2_D3__           0x00000002
661 		#define PORT_HW_CFG_SPEED_CAPABILITY2_D3___          0x00000004
662 		#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_100M_FULL   0x00000008
663 		#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_1G          0x00000010
664 		#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_2_DOT_5G    0x00000020
665 		#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10G         0x00000040
666 		#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_20G         0x00000080
667 
668 	#define PORT_HW_CFG_SPEED_CAPABILITY2_D0_MASK       0xFFFF0000
669 		#define PORT_HW_CFG_SPEED_CAPABILITY2_D0_SHIFT       16
670 		#define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10M_FULL    0x00010000
671 		#define PORT_HW_CFG_SPEED_CAPABILITY2_D0__           0x00020000
672 		#define PORT_HW_CFG_SPEED_CAPABILITY2_D0___          0x00040000
673 		#define PORT_HW_CFG_SPEED_CAPABILITY2_D0_100M_FULL   0x00080000
674 		#define PORT_HW_CFG_SPEED_CAPABILITY2_D0_1G          0x00100000
675 		#define PORT_HW_CFG_SPEED_CAPABILITY2_D0_2_DOT_5G    0x00200000
676 		#define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10G         0x00400000
677 		#define PORT_HW_CFG_SPEED_CAPABILITY2_D0_20G         0x00800000
678 
679 
680 	/*  In the case where two media types (e.g. copper and fiber) are
681 	      present and electrically active at the same time, PHY Selection
682 	      will determine which of the two PHYs will be designated as the
683 	      Active PHY and used for a connection to the network.  */
684 	u32 multi_phy_config;				    /* 0x290 */
685 	#define PORT_HW_CFG_PHY_SELECTION_MASK              0x00000007
686 		#define PORT_HW_CFG_PHY_SELECTION_SHIFT              0
687 		#define PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT   0x00000000
688 		#define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY          0x00000001
689 		#define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY         0x00000002
690 		#define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY 0x00000003
691 		#define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY 0x00000004
692 
693 	/*  When enabled, all second phy nvram parameters will be swapped
694 	      with the first phy parameters */
695 	#define PORT_HW_CFG_PHY_SWAPPED_MASK                0x00000008
696 		#define PORT_HW_CFG_PHY_SWAPPED_SHIFT                3
697 		#define PORT_HW_CFG_PHY_SWAPPED_DISABLED             0x00000000
698 		#define PORT_HW_CFG_PHY_SWAPPED_ENABLED              0x00000008
699 
700 
701 	/*  Address of the second external phy */
702 	u32 external_phy_config2;			    /* 0x294 */
703 	#define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_MASK         0x000000FF
704 	#define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_SHIFT                 0
705 
706 	/*  The second XGXS external PHY type */
707 	#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_MASK         0x0000FF00
708 		#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SHIFT         8
709 		#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_DIRECT        0x00000000
710 		#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8071       0x00000100
711 		#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8072       0x00000200
712 		#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8073       0x00000300
713 		#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8705       0x00000400
714 		#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8706       0x00000500
715 		#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8726       0x00000600
716 		#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8481       0x00000700
717 		#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SFX7101       0x00000800
718 		#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727       0x00000900
719 		#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727_NOC   0x00000a00
720 		#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84823      0x00000b00
721 		#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54640      0x00000c00
722 		#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84833      0x00000d00
723 		#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54618SE    0x00000e00
724 		#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8722       0x00000f00
725 		#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54616      0x00001000
726 		#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84834      0x00001100
727 		#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_FAILURE       0x0000fd00
728 		#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_NOT_CONN      0x0000ff00
729 
730 
731 	/*  4 times 16 bits for all 4 lanes. For some external PHYs (such as
732 	      8706, 8726 and 8727) not all 4 values are needed. */
733 	u16 xgxs_config2_rx[4];				    /* 0x296 */
734 	u16 xgxs_config2_tx[4];				    /* 0x2A0 */
735 
736 	u32 lane_config;
737 	#define PORT_HW_CFG_LANE_SWAP_CFG_MASK              0x0000ffff
738 		#define PORT_HW_CFG_LANE_SWAP_CFG_SHIFT              0
739 		/* AN and forced */
740 		#define PORT_HW_CFG_LANE_SWAP_CFG_01230123           0x00001b1b
741 		/* forced only */
742 		#define PORT_HW_CFG_LANE_SWAP_CFG_01233210           0x00001be4
743 		/* forced only */
744 		#define PORT_HW_CFG_LANE_SWAP_CFG_31203120           0x0000d8d8
745 		/* forced only */
746 		#define PORT_HW_CFG_LANE_SWAP_CFG_32103210           0x0000e4e4
747 	#define PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK           0x000000ff
748 	#define PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT                   0
749 	#define PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK           0x0000ff00
750 	#define PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT                   8
751 	#define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK       0x0000c000
752 	#define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT               14
753 
754 	/*  Indicate whether to swap the external phy polarity */
755 	#define PORT_HW_CFG_SWAP_PHY_POLARITY_MASK          0x00010000
756 		#define PORT_HW_CFG_SWAP_PHY_POLARITY_DISABLED       0x00000000
757 		#define PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED        0x00010000
758 
759 
760 	u32 external_phy_config;
761 	#define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK          0x000000ff
762 	#define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT                  0
763 
764 	#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK          0x0000ff00
765 		#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SHIFT          8
766 		#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT         0x00000000
767 		#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8071        0x00000100
768 		#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072        0x00000200
769 		#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073        0x00000300
770 		#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705        0x00000400
771 		#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706        0x00000500
772 		#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726        0x00000600
773 		#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481        0x00000700
774 		#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101        0x00000800
775 		#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727        0x00000900
776 		#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC    0x00000a00
777 		#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823       0x00000b00
778 		#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54640       0x00000c00
779 		#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833       0x00000d00
780 		#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE     0x00000e00
781 		#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722        0x00000f00
782 		#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616       0x00001000
783 		#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834       0x00001100
784 		#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT_WC      0x0000fc00
785 		#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE        0x0000fd00
786 		#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN       0x0000ff00
787 
788 	#define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK        0x00ff0000
789 	#define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_SHIFT                16
790 
791 	#define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK        0xff000000
792 		#define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_SHIFT        24
793 		#define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT       0x00000000
794 		#define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482      0x01000000
795 		#define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD    0x02000000
796 		#define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN     0xff000000
797 
798 	u32 speed_capability_mask;
799 	#define PORT_HW_CFG_SPEED_CAPABILITY_D3_MASK        0x0000ffff
800 		#define PORT_HW_CFG_SPEED_CAPABILITY_D3_SHIFT        0
801 		#define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_FULL     0x00000001
802 		#define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_HALF     0x00000002
803 		#define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_HALF    0x00000004
804 		#define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_FULL    0x00000008
805 		#define PORT_HW_CFG_SPEED_CAPABILITY_D3_1G           0x00000010
806 		#define PORT_HW_CFG_SPEED_CAPABILITY_D3_2_5G         0x00000020
807 		#define PORT_HW_CFG_SPEED_CAPABILITY_D3_10G          0x00000040
808 		#define PORT_HW_CFG_SPEED_CAPABILITY_D3_20G          0x00000080
809 		#define PORT_HW_CFG_SPEED_CAPABILITY_D3_RESERVED     0x0000f000
810 
811 	#define PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK        0xffff0000
812 		#define PORT_HW_CFG_SPEED_CAPABILITY_D0_SHIFT        16
813 		#define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL     0x00010000
814 		#define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF     0x00020000
815 		#define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF    0x00040000
816 		#define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL    0x00080000
817 		#define PORT_HW_CFG_SPEED_CAPABILITY_D0_1G           0x00100000
818 		#define PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G         0x00200000
819 		#define PORT_HW_CFG_SPEED_CAPABILITY_D0_10G          0x00400000
820 		#define PORT_HW_CFG_SPEED_CAPABILITY_D0_20G          0x00800000
821 		#define PORT_HW_CFG_SPEED_CAPABILITY_D0_RESERVED     0xf0000000
822 
823 	/*  A place to hold the original MAC address as a backup */
824 	u32 backup_mac_upper;			/* 0x2B4 */
825 	u32 backup_mac_lower;			/* 0x2B8 */
826 
827 };
828 
829 
830 /****************************************************************************
831  * Shared Feature configuration                                             *
832  ****************************************************************************/
833 struct shared_feat_cfg {		 /* NVRAM Offset */
834 
835 	u32 config;			/* 0x450 */
836 	#define SHARED_FEATURE_BMC_ECHO_MODE_EN             0x00000001
837 
838 	/* Use NVRAM values instead of HW default values */
839 	#define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_MASK \
840 							    0x00000002
841 		#define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_DISABLED \
842 								     0x00000000
843 		#define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED \
844 								     0x00000002
845 
846 	#define SHARED_FEAT_CFG_NCSI_ID_METHOD_MASK         0x00000008
847 		#define SHARED_FEAT_CFG_NCSI_ID_METHOD_SPIO          0x00000000
848 		#define SHARED_FEAT_CFG_NCSI_ID_METHOD_NVRAM         0x00000008
849 
850 	#define SHARED_FEAT_CFG_NCSI_ID_MASK                0x00000030
851 	#define SHARED_FEAT_CFG_NCSI_ID_SHIFT                        4
852 
853 	/*  Override the OTP back to single function mode. When using GPIO,
854 	      high means only SF, 0 is according to CLP configuration */
855 	#define SHARED_FEAT_CFG_FORCE_SF_MODE_MASK          0x00000700
856 		#define SHARED_FEAT_CFG_FORCE_SF_MODE_SHIFT          8
857 		#define SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED     0x00000000
858 		#define SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF      0x00000100
859 		#define SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4          0x00000200
860 		#define SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT  0x00000300
861 		#define SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE      0x00000400
862 
863 	/* The interval in seconds between sending LLDP packets. Set to zero
864 	   to disable the feature */
865 	#define SHARED_FEAT_CFG_LLDP_XMIT_INTERVAL_MASK     0x00ff0000
866 	#define SHARED_FEAT_CFG_LLDP_XMIT_INTERVAL_SHIFT             16
867 
868 	/* The assigned device type ID for LLDP usage */
869 	#define SHARED_FEAT_CFG_LLDP_DEVICE_TYPE_ID_MASK    0xff000000
870 	#define SHARED_FEAT_CFG_LLDP_DEVICE_TYPE_ID_SHIFT            24
871 
872 };
873 
874 
875 /****************************************************************************
876  * Port Feature configuration                                               *
877  ****************************************************************************/
878 struct port_feat_cfg {		    /* port 0: 0x454  port 1: 0x4c8 */
879 
880 	u32 config;
881 	#define PORT_FEATURE_BAR1_SIZE_MASK                 0x0000000f
882 		#define PORT_FEATURE_BAR1_SIZE_SHIFT                 0
883 		#define PORT_FEATURE_BAR1_SIZE_DISABLED              0x00000000
884 		#define PORT_FEATURE_BAR1_SIZE_64K                   0x00000001
885 		#define PORT_FEATURE_BAR1_SIZE_128K                  0x00000002
886 		#define PORT_FEATURE_BAR1_SIZE_256K                  0x00000003
887 		#define PORT_FEATURE_BAR1_SIZE_512K                  0x00000004
888 		#define PORT_FEATURE_BAR1_SIZE_1M                    0x00000005
889 		#define PORT_FEATURE_BAR1_SIZE_2M                    0x00000006
890 		#define PORT_FEATURE_BAR1_SIZE_4M                    0x00000007
891 		#define PORT_FEATURE_BAR1_SIZE_8M                    0x00000008
892 		#define PORT_FEATURE_BAR1_SIZE_16M                   0x00000009
893 		#define PORT_FEATURE_BAR1_SIZE_32M                   0x0000000a
894 		#define PORT_FEATURE_BAR1_SIZE_64M                   0x0000000b
895 		#define PORT_FEATURE_BAR1_SIZE_128M                  0x0000000c
896 		#define PORT_FEATURE_BAR1_SIZE_256M                  0x0000000d
897 		#define PORT_FEATURE_BAR1_SIZE_512M                  0x0000000e
898 		#define PORT_FEATURE_BAR1_SIZE_1G                    0x0000000f
899 	#define PORT_FEATURE_BAR2_SIZE_MASK                 0x000000f0
900 		#define PORT_FEATURE_BAR2_SIZE_SHIFT                 4
901 		#define PORT_FEATURE_BAR2_SIZE_DISABLED              0x00000000
902 		#define PORT_FEATURE_BAR2_SIZE_64K                   0x00000010
903 		#define PORT_FEATURE_BAR2_SIZE_128K                  0x00000020
904 		#define PORT_FEATURE_BAR2_SIZE_256K                  0x00000030
905 		#define PORT_FEATURE_BAR2_SIZE_512K                  0x00000040
906 		#define PORT_FEATURE_BAR2_SIZE_1M                    0x00000050
907 		#define PORT_FEATURE_BAR2_SIZE_2M                    0x00000060
908 		#define PORT_FEATURE_BAR2_SIZE_4M                    0x00000070
909 		#define PORT_FEATURE_BAR2_SIZE_8M                    0x00000080
910 		#define PORT_FEATURE_BAR2_SIZE_16M                   0x00000090
911 		#define PORT_FEATURE_BAR2_SIZE_32M                   0x000000a0
912 		#define PORT_FEATURE_BAR2_SIZE_64M                   0x000000b0
913 		#define PORT_FEATURE_BAR2_SIZE_128M                  0x000000c0
914 		#define PORT_FEATURE_BAR2_SIZE_256M                  0x000000d0
915 		#define PORT_FEATURE_BAR2_SIZE_512M                  0x000000e0
916 		#define PORT_FEATURE_BAR2_SIZE_1G                    0x000000f0
917 
918 	#define PORT_FEAT_CFG_DCBX_MASK                     0x00000100
919 		#define PORT_FEAT_CFG_DCBX_DISABLED                  0x00000000
920 		#define PORT_FEAT_CFG_DCBX_ENABLED                   0x00000100
921 
922 		#define PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK        0x00000C00
923 		#define PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE        0x00000400
924 		#define PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI       0x00000800
925 
926 	#define PORT_FEATURE_EN_SIZE_MASK                   0x0f000000
927 	#define PORT_FEATURE_EN_SIZE_SHIFT                           24
928 	#define PORT_FEATURE_WOL_ENABLED                             0x01000000
929 	#define PORT_FEATURE_MBA_ENABLED                             0x02000000
930 	#define PORT_FEATURE_MFW_ENABLED                             0x04000000
931 
932 	/* Advertise expansion ROM even if MBA is disabled */
933 	#define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_MASK        0x08000000
934 		#define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_DISABLED     0x00000000
935 		#define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_ENABLED      0x08000000
936 
937 	/* Check the optic vendor via i2c against a list of approved modules
938 	   in a separate nvram image */
939 	#define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK         0xe0000000
940 		#define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_SHIFT         29
941 		#define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT \
942 								     0x00000000
943 		#define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER \
944 								     0x20000000
945 		#define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG   0x40000000
946 		#define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN    0x60000000
947 
948 	u32 wol_config;
949 	/* Default is used when driver sets to "auto" mode */
950 	#define PORT_FEATURE_WOL_DEFAULT_MASK               0x00000003
951 		#define PORT_FEATURE_WOL_DEFAULT_SHIFT               0
952 		#define PORT_FEATURE_WOL_DEFAULT_DISABLE             0x00000000
953 		#define PORT_FEATURE_WOL_DEFAULT_MAGIC               0x00000001
954 		#define PORT_FEATURE_WOL_DEFAULT_ACPI                0x00000002
955 		#define PORT_FEATURE_WOL_DEFAULT_MAGIC_AND_ACPI      0x00000003
956 	#define PORT_FEATURE_WOL_RES_PAUSE_CAP              0x00000004
957 	#define PORT_FEATURE_WOL_RES_ASYM_PAUSE_CAP         0x00000008
958 	#define PORT_FEATURE_WOL_ACPI_UPON_MGMT             0x00000010
959 
960 	u32 mba_config;
961 	#define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK       0x00000007
962 		#define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT       0
963 		#define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE         0x00000000
964 		#define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL         0x00000001
965 		#define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP       0x00000002
966 		#define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB      0x00000003
967 		#define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT   0x00000004
968 		#define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE        0x00000007
969 
970 	#define PORT_FEATURE_MBA_BOOT_RETRY_MASK            0x00000038
971 	#define PORT_FEATURE_MBA_BOOT_RETRY_SHIFT                    3
972 
973 	#define PORT_FEATURE_MBA_RES_PAUSE_CAP              0x00000100
974 	#define PORT_FEATURE_MBA_RES_ASYM_PAUSE_CAP         0x00000200
975 	#define PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE        0x00000400
976 	#define PORT_FEATURE_MBA_HOTKEY_MASK                0x00000800
977 		#define PORT_FEATURE_MBA_HOTKEY_CTRL_S               0x00000000
978 		#define PORT_FEATURE_MBA_HOTKEY_CTRL_B               0x00000800
979 	#define PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK          0x000ff000
980 		#define PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT          12
981 		#define PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED       0x00000000
982 		#define PORT_FEATURE_MBA_EXP_ROM_SIZE_2K             0x00001000
983 		#define PORT_FEATURE_MBA_EXP_ROM_SIZE_4K             0x00002000
984 		#define PORT_FEATURE_MBA_EXP_ROM_SIZE_8K             0x00003000
985 		#define PORT_FEATURE_MBA_EXP_ROM_SIZE_16K            0x00004000
986 		#define PORT_FEATURE_MBA_EXP_ROM_SIZE_32K            0x00005000
987 		#define PORT_FEATURE_MBA_EXP_ROM_SIZE_64K            0x00006000
988 		#define PORT_FEATURE_MBA_EXP_ROM_SIZE_128K           0x00007000
989 		#define PORT_FEATURE_MBA_EXP_ROM_SIZE_256K           0x00008000
990 		#define PORT_FEATURE_MBA_EXP_ROM_SIZE_512K           0x00009000
991 		#define PORT_FEATURE_MBA_EXP_ROM_SIZE_1M             0x0000a000
992 		#define PORT_FEATURE_MBA_EXP_ROM_SIZE_2M             0x0000b000
993 		#define PORT_FEATURE_MBA_EXP_ROM_SIZE_4M             0x0000c000
994 		#define PORT_FEATURE_MBA_EXP_ROM_SIZE_8M             0x0000d000
995 		#define PORT_FEATURE_MBA_EXP_ROM_SIZE_16M            0x0000e000
996 		#define PORT_FEATURE_MBA_EXP_ROM_SIZE_32M            0x0000f000
997 	#define PORT_FEATURE_MBA_MSG_TIMEOUT_MASK           0x00f00000
998 	#define PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT                   20
999 	#define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK        0x03000000
1000 		#define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT        24
1001 		#define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO         0x00000000
1002 		#define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS          0x01000000
1003 		#define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H       0x02000000
1004 		#define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H       0x03000000
1005 	#define PORT_FEATURE_MBA_LINK_SPEED_MASK            0x3c000000
1006 		#define PORT_FEATURE_MBA_LINK_SPEED_SHIFT            26
1007 		#define PORT_FEATURE_MBA_LINK_SPEED_AUTO             0x00000000
1008 		#define PORT_FEATURE_MBA_LINK_SPEED_10HD             0x04000000
1009 		#define PORT_FEATURE_MBA_LINK_SPEED_10FD             0x08000000
1010 		#define PORT_FEATURE_MBA_LINK_SPEED_100HD            0x0c000000
1011 		#define PORT_FEATURE_MBA_LINK_SPEED_100FD            0x10000000
1012 		#define PORT_FEATURE_MBA_LINK_SPEED_1GBPS            0x14000000
1013 		#define PORT_FEATURE_MBA_LINK_SPEED_2_5GBPS          0x18000000
1014 		#define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_CX4       0x1c000000
1015 		#define PORT_FEATURE_MBA_LINK_SPEED_20GBPS           0x20000000
1016 	u32 bmc_config;
1017 	#define PORT_FEATURE_BMC_LINK_OVERRIDE_MASK         0x00000001
1018 		#define PORT_FEATURE_BMC_LINK_OVERRIDE_DEFAULT       0x00000000
1019 		#define PORT_FEATURE_BMC_LINK_OVERRIDE_EN            0x00000001
1020 
1021 	u32 mba_vlan_cfg;
1022 	#define PORT_FEATURE_MBA_VLAN_TAG_MASK              0x0000ffff
1023 	#define PORT_FEATURE_MBA_VLAN_TAG_SHIFT                      0
1024 	#define PORT_FEATURE_MBA_VLAN_EN                    0x00010000
1025 
1026 	u32 resource_cfg;
1027 	#define PORT_FEATURE_RESOURCE_CFG_VALID             0x00000001
1028 	#define PORT_FEATURE_RESOURCE_CFG_DIAG              0x00000002
1029 	#define PORT_FEATURE_RESOURCE_CFG_L2                0x00000004
1030 	#define PORT_FEATURE_RESOURCE_CFG_ISCSI             0x00000008
1031 	#define PORT_FEATURE_RESOURCE_CFG_RDMA              0x00000010
1032 
1033 	u32 smbus_config;
1034 	#define PORT_FEATURE_SMBUS_ADDR_MASK                0x000000fe
1035 	#define PORT_FEATURE_SMBUS_ADDR_SHIFT                        1
1036 
1037 	u32 vf_config;
1038 	#define PORT_FEAT_CFG_VF_BAR2_SIZE_MASK             0x0000000f
1039 		#define PORT_FEAT_CFG_VF_BAR2_SIZE_SHIFT             0
1040 		#define PORT_FEAT_CFG_VF_BAR2_SIZE_DISABLED          0x00000000
1041 		#define PORT_FEAT_CFG_VF_BAR2_SIZE_4K                0x00000001
1042 		#define PORT_FEAT_CFG_VF_BAR2_SIZE_8K                0x00000002
1043 		#define PORT_FEAT_CFG_VF_BAR2_SIZE_16K               0x00000003
1044 		#define PORT_FEAT_CFG_VF_BAR2_SIZE_32K               0x00000004
1045 		#define PORT_FEAT_CFG_VF_BAR2_SIZE_64K               0x00000005
1046 		#define PORT_FEAT_CFG_VF_BAR2_SIZE_128K              0x00000006
1047 		#define PORT_FEAT_CFG_VF_BAR2_SIZE_256K              0x00000007
1048 		#define PORT_FEAT_CFG_VF_BAR2_SIZE_512K              0x00000008
1049 		#define PORT_FEAT_CFG_VF_BAR2_SIZE_1M                0x00000009
1050 		#define PORT_FEAT_CFG_VF_BAR2_SIZE_2M                0x0000000a
1051 		#define PORT_FEAT_CFG_VF_BAR2_SIZE_4M                0x0000000b
1052 		#define PORT_FEAT_CFG_VF_BAR2_SIZE_8M                0x0000000c
1053 		#define PORT_FEAT_CFG_VF_BAR2_SIZE_16M               0x0000000d
1054 		#define PORT_FEAT_CFG_VF_BAR2_SIZE_32M               0x0000000e
1055 		#define PORT_FEAT_CFG_VF_BAR2_SIZE_64M               0x0000000f
1056 
1057 	u32 link_config;    /* Used as HW defaults for the driver */
1058 	#define PORT_FEATURE_CONNECTED_SWITCH_MASK          0x03000000
1059 		#define PORT_FEATURE_CONNECTED_SWITCH_SHIFT          24
1060 		/* (forced) low speed switch (< 10G) */
1061 		#define PORT_FEATURE_CON_SWITCH_1G_SWITCH            0x00000000
1062 		/* (forced) high speed switch (>= 10G) */
1063 		#define PORT_FEATURE_CON_SWITCH_10G_SWITCH           0x01000000
1064 		#define PORT_FEATURE_CON_SWITCH_AUTO_DETECT          0x02000000
1065 		#define PORT_FEATURE_CON_SWITCH_ONE_TIME_DETECT      0x03000000
1066 
1067 	#define PORT_FEATURE_LINK_SPEED_MASK                0x000f0000
1068 		#define PORT_FEATURE_LINK_SPEED_SHIFT                16
1069 		#define PORT_FEATURE_LINK_SPEED_AUTO                 0x00000000
1070 		#define PORT_FEATURE_LINK_SPEED_10M_FULL             0x00010000
1071 		#define PORT_FEATURE_LINK_SPEED_10M_HALF             0x00020000
1072 		#define PORT_FEATURE_LINK_SPEED_100M_HALF            0x00030000
1073 		#define PORT_FEATURE_LINK_SPEED_100M_FULL            0x00040000
1074 		#define PORT_FEATURE_LINK_SPEED_1G                   0x00050000
1075 		#define PORT_FEATURE_LINK_SPEED_2_5G                 0x00060000
1076 		#define PORT_FEATURE_LINK_SPEED_10G_CX4              0x00070000
1077 		#define PORT_FEATURE_LINK_SPEED_20G                  0x00080000
1078 
1079 	#define PORT_FEATURE_FLOW_CONTROL_MASK              0x00000700
1080 		#define PORT_FEATURE_FLOW_CONTROL_SHIFT              8
1081 		#define PORT_FEATURE_FLOW_CONTROL_AUTO               0x00000000
1082 		#define PORT_FEATURE_FLOW_CONTROL_TX                 0x00000100
1083 		#define PORT_FEATURE_FLOW_CONTROL_RX                 0x00000200
1084 		#define PORT_FEATURE_FLOW_CONTROL_BOTH               0x00000300
1085 		#define PORT_FEATURE_FLOW_CONTROL_NONE               0x00000400
1086 
1087 	/* The default for MCP link configuration,
1088 	   uses the same defines as link_config */
1089 	u32 mfw_wol_link_cfg;
1090 
1091 	/* The default for the driver of the second external phy,
1092 	   uses the same defines as link_config */
1093 	u32 link_config2;				    /* 0x47C */
1094 
1095 	/* The default for MCP of the second external phy,
1096 	   uses the same defines as link_config */
1097 	u32 mfw_wol_link_cfg2;				    /* 0x480 */
1098 
1099 
1100 	/*  EEE power saving mode */
1101 	u32 eee_power_mode;                                 /* 0x484 */
1102 	#define PORT_FEAT_CFG_EEE_POWER_MODE_MASK                     0x000000FF
1103 	#define PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT                    0
1104 	#define PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED                 0x00000000
1105 	#define PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED                 0x00000001
1106 	#define PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE               0x00000002
1107 	#define PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY              0x00000003
1108 
1109 
1110 	u32 Reserved2[16];                                  /* 0x488 */
1111 };
1112 
1113 
1114 /****************************************************************************
1115  * Device Information                                                       *
1116  ****************************************************************************/
1117 struct shm_dev_info {				/* size */
1118 
1119 	u32    bc_rev; /* 8 bits each: major, minor, build */	       /* 4 */
1120 
1121 	struct shared_hw_cfg     shared_hw_config;	      /* 40 */
1122 
1123 	struct port_hw_cfg       port_hw_config[PORT_MAX];     /* 400*2=800 */
1124 
1125 	struct shared_feat_cfg   shared_feature_config;		   /* 4 */
1126 
1127 	struct port_feat_cfg     port_feature_config[PORT_MAX];/* 116*2=232 */
1128 
1129 };
1130 
1131 
1132 #if !defined(__LITTLE_ENDIAN) && !defined(__BIG_ENDIAN)
1133 	#error "Missing either LITTLE_ENDIAN or BIG_ENDIAN definition."
1134 #endif
1135 
1136 #define FUNC_0              0
1137 #define FUNC_1              1
1138 #define FUNC_2              2
1139 #define FUNC_3              3
1140 #define FUNC_4              4
1141 #define FUNC_5              5
1142 #define FUNC_6              6
1143 #define FUNC_7              7
1144 #define E1_FUNC_MAX         2
1145 #define E1H_FUNC_MAX            8
1146 #define E2_FUNC_MAX         4   /* per path */
1147 
1148 #define VN_0                0
1149 #define VN_1                1
1150 #define VN_2                2
1151 #define VN_3                3
1152 #define E1VN_MAX            1
1153 #define E1HVN_MAX           4
1154 
1155 #define E2_VF_MAX           64  /* HC_REG_VF_CONFIGURATION_SIZE */
1156 /* This value (in milliseconds) determines the frequency of the driver
1157  * issuing the PULSE message code.  The firmware monitors this periodic
1158  * pulse to determine when to switch to an OS-absent mode. */
1159 #define DRV_PULSE_PERIOD_MS     250
1160 
1161 /* This value (in milliseconds) determines how long the driver should
1162  * wait for an acknowledgement from the firmware before timing out.  Once
1163  * the firmware has timed out, the driver will assume there is no firmware
1164  * running and there won't be any firmware-driver synchronization during a
1165  * driver reset. */
1166 #define FW_ACK_TIME_OUT_MS      5000
1167 
1168 #define FW_ACK_POLL_TIME_MS     1
1169 
1170 #define FW_ACK_NUM_OF_POLL  (FW_ACK_TIME_OUT_MS/FW_ACK_POLL_TIME_MS)
1171 
1172 #define MFW_TRACE_SIGNATURE     0x54524342
1173 
1174 /****************************************************************************
1175  * Driver <-> FW Mailbox                                                    *
1176  ****************************************************************************/
1177 struct drv_port_mb {
1178 
1179 	u32 link_status;
1180 	/* Driver should update this field on any link change event */
1181 
1182 	#define LINK_STATUS_NONE				(0<<0)
1183 	#define LINK_STATUS_LINK_FLAG_MASK			0x00000001
1184 	#define LINK_STATUS_LINK_UP				0x00000001
1185 	#define LINK_STATUS_SPEED_AND_DUPLEX_MASK		0x0000001E
1186 	#define LINK_STATUS_SPEED_AND_DUPLEX_AN_NOT_COMPLETE	(0<<1)
1187 	#define LINK_STATUS_SPEED_AND_DUPLEX_10THD		(1<<1)
1188 	#define LINK_STATUS_SPEED_AND_DUPLEX_10TFD		(2<<1)
1189 	#define LINK_STATUS_SPEED_AND_DUPLEX_100TXHD		(3<<1)
1190 	#define LINK_STATUS_SPEED_AND_DUPLEX_100T4		(4<<1)
1191 	#define LINK_STATUS_SPEED_AND_DUPLEX_100TXFD		(5<<1)
1192 	#define LINK_STATUS_SPEED_AND_DUPLEX_1000THD		(6<<1)
1193 	#define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD		(7<<1)
1194 	#define LINK_STATUS_SPEED_AND_DUPLEX_1000XFD		(7<<1)
1195 	#define LINK_STATUS_SPEED_AND_DUPLEX_2500THD		(8<<1)
1196 	#define LINK_STATUS_SPEED_AND_DUPLEX_2500TFD		(9<<1)
1197 	#define LINK_STATUS_SPEED_AND_DUPLEX_2500XFD		(9<<1)
1198 	#define LINK_STATUS_SPEED_AND_DUPLEX_10GTFD		(10<<1)
1199 	#define LINK_STATUS_SPEED_AND_DUPLEX_10GXFD		(10<<1)
1200 	#define LINK_STATUS_SPEED_AND_DUPLEX_20GTFD		(11<<1)
1201 	#define LINK_STATUS_SPEED_AND_DUPLEX_20GXFD		(11<<1)
1202 
1203 	#define LINK_STATUS_AUTO_NEGOTIATE_FLAG_MASK		0x00000020
1204 	#define LINK_STATUS_AUTO_NEGOTIATE_ENABLED		0x00000020
1205 
1206 	#define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE		0x00000040
1207 	#define LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK	0x00000080
1208 	#define LINK_STATUS_PARALLEL_DETECTION_USED		0x00000080
1209 
1210 	#define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE	0x00000200
1211 	#define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE	0x00000400
1212 	#define LINK_STATUS_LINK_PARTNER_100T4_CAPABLE		0x00000800
1213 	#define LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE	0x00001000
1214 	#define LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE	0x00002000
1215 	#define LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE		0x00004000
1216 	#define LINK_STATUS_LINK_PARTNER_10THD_CAPABLE		0x00008000
1217 
1218 	#define LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK		0x00010000
1219 	#define LINK_STATUS_TX_FLOW_CONTROL_ENABLED		0x00010000
1220 
1221 	#define LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK		0x00020000
1222 	#define LINK_STATUS_RX_FLOW_CONTROL_ENABLED		0x00020000
1223 
1224 	#define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK	0x000C0000
1225 	#define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE	(0<<18)
1226 	#define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE	(1<<18)
1227 	#define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE	(2<<18)
1228 	#define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE		(3<<18)
1229 
1230 	#define LINK_STATUS_SERDES_LINK				0x00100000
1231 
1232 	#define LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE	0x00200000
1233 	#define LINK_STATUS_LINK_PARTNER_2500XHD_CAPABLE	0x00400000
1234 	#define LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE		0x00800000
1235 	#define LINK_STATUS_LINK_PARTNER_20GXFD_CAPABLE		0x10000000
1236 
1237 	#define LINK_STATUS_PFC_ENABLED				0x20000000
1238 
1239 	#define LINK_STATUS_PHYSICAL_LINK_FLAG			0x40000000
1240 	#define LINK_STATUS_SFP_TX_FAULT			0x80000000
1241 
1242 	u32 port_stx;
1243 
1244 	u32 stat_nig_timer;
1245 
1246 	/* MCP firmware does not use this field */
1247 	u32 ext_phy_fw_version;
1248 
1249 };
1250 
1251 
1252 struct drv_func_mb {
1253 
1254 	u32 drv_mb_header;
1255 	#define DRV_MSG_CODE_MASK                       0xffff0000
1256 	#define DRV_MSG_CODE_LOAD_REQ                   0x10000000
1257 	#define DRV_MSG_CODE_LOAD_DONE                  0x11000000
1258 	#define DRV_MSG_CODE_UNLOAD_REQ_WOL_EN          0x20000000
1259 	#define DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS         0x20010000
1260 	#define DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP         0x20020000
1261 	#define DRV_MSG_CODE_UNLOAD_DONE                0x21000000
1262 	#define DRV_MSG_CODE_DCC_OK                     0x30000000
1263 	#define DRV_MSG_CODE_DCC_FAILURE                0x31000000
1264 	#define DRV_MSG_CODE_DIAG_ENTER_REQ             0x50000000
1265 	#define DRV_MSG_CODE_DIAG_EXIT_REQ              0x60000000
1266 	#define DRV_MSG_CODE_VALIDATE_KEY               0x70000000
1267 	#define DRV_MSG_CODE_GET_CURR_KEY               0x80000000
1268 	#define DRV_MSG_CODE_GET_UPGRADE_KEY            0x81000000
1269 	#define DRV_MSG_CODE_GET_MANUF_KEY              0x82000000
1270 	#define DRV_MSG_CODE_LOAD_L2B_PRAM              0x90000000
1271 	/*
1272 	 * The optic module verification command requires bootcode
1273 	 * v5.0.6 or later, te specific optic module verification command
1274 	 * requires bootcode v5.2.12 or later
1275 	 */
1276 	#define DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL     0xa0000000
1277 	#define REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL     0x00050006
1278 	#define DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL  0xa1000000
1279 	#define REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL  0x00050234
1280 	#define DRV_MSG_CODE_VRFY_AFEX_SUPPORTED        0xa2000000
1281 	#define REQ_BC_VER_4_VRFY_AFEX_SUPPORTED        0x00070002
1282 	#define REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED   0x00070014
1283 	#define REQ_BC_VER_4_MT_SUPPORTED               0x00070201
1284 	#define REQ_BC_VER_4_PFC_STATS_SUPPORTED        0x00070201
1285 	#define REQ_BC_VER_4_FCOE_FEATURES              0x00070209
1286 
1287 	#define DRV_MSG_CODE_DCBX_ADMIN_PMF_MSG         0xb0000000
1288 	#define DRV_MSG_CODE_DCBX_PMF_DRV_OK            0xb2000000
1289 	#define REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF     0x00070401
1290 
1291 	#define DRV_MSG_CODE_VF_DISABLED_DONE           0xc0000000
1292 
1293 	#define DRV_MSG_CODE_AFEX_DRIVER_SETMAC         0xd0000000
1294 	#define DRV_MSG_CODE_AFEX_LISTGET_ACK           0xd1000000
1295 	#define DRV_MSG_CODE_AFEX_LISTSET_ACK           0xd2000000
1296 	#define DRV_MSG_CODE_AFEX_STATSGET_ACK          0xd3000000
1297 	#define DRV_MSG_CODE_AFEX_VIFSET_ACK            0xd4000000
1298 
1299 	#define DRV_MSG_CODE_DRV_INFO_ACK               0xd8000000
1300 	#define DRV_MSG_CODE_DRV_INFO_NACK              0xd9000000
1301 
1302 	#define DRV_MSG_CODE_EEE_RESULTS_ACK            0xda000000
1303 
1304 	#define DRV_MSG_CODE_RMMOD                      0xdb000000
1305 	#define REQ_BC_VER_4_RMMOD_CMD                  0x0007080f
1306 
1307 	#define DRV_MSG_CODE_SET_MF_BW                  0xe0000000
1308 	#define REQ_BC_VER_4_SET_MF_BW                  0x00060202
1309 	#define DRV_MSG_CODE_SET_MF_BW_ACK              0xe1000000
1310 
1311 	#define DRV_MSG_CODE_LINK_STATUS_CHANGED        0x01000000
1312 
1313 	#define DRV_MSG_CODE_INITIATE_FLR               0x02000000
1314 	#define REQ_BC_VER_4_INITIATE_FLR               0x00070213
1315 
1316 	#define BIOS_MSG_CODE_LIC_CHALLENGE             0xff010000
1317 	#define BIOS_MSG_CODE_LIC_RESPONSE              0xff020000
1318 	#define BIOS_MSG_CODE_VIRT_MAC_PRIM             0xff030000
1319 	#define BIOS_MSG_CODE_VIRT_MAC_ISCSI            0xff040000
1320 
1321 	#define DRV_MSG_SEQ_NUMBER_MASK                 0x0000ffff
1322 
1323 	u32 drv_mb_param;
1324 	#define DRV_MSG_CODE_SET_MF_BW_MIN_MASK         0x00ff0000
1325 	#define DRV_MSG_CODE_SET_MF_BW_MAX_MASK         0xff000000
1326 
1327 	#define DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET     0x00000002
1328 
1329 	#define DRV_MSG_CODE_LOAD_REQ_WITH_LFA          0x0000100a
1330 	#define DRV_MSG_CODE_LOAD_REQ_FORCE_LFA         0x00002000
1331 
1332 	u32 fw_mb_header;
1333 	#define FW_MSG_CODE_MASK                        0xffff0000
1334 	#define FW_MSG_CODE_DRV_LOAD_COMMON             0x10100000
1335 	#define FW_MSG_CODE_DRV_LOAD_PORT               0x10110000
1336 	#define FW_MSG_CODE_DRV_LOAD_FUNCTION           0x10120000
1337 	/* Load common chip is supported from bc 6.0.0  */
1338 	#define REQ_BC_VER_4_DRV_LOAD_COMMON_CHIP       0x00060000
1339 	#define FW_MSG_CODE_DRV_LOAD_COMMON_CHIP        0x10130000
1340 
1341 	#define FW_MSG_CODE_DRV_LOAD_REFUSED            0x10200000
1342 	#define FW_MSG_CODE_DRV_LOAD_DONE               0x11100000
1343 	#define FW_MSG_CODE_DRV_UNLOAD_COMMON           0x20100000
1344 	#define FW_MSG_CODE_DRV_UNLOAD_PORT             0x20110000
1345 	#define FW_MSG_CODE_DRV_UNLOAD_FUNCTION         0x20120000
1346 	#define FW_MSG_CODE_DRV_UNLOAD_DONE             0x21100000
1347 	#define FW_MSG_CODE_DCC_DONE                    0x30100000
1348 	#define FW_MSG_CODE_LLDP_DONE                   0x40100000
1349 	#define FW_MSG_CODE_DIAG_ENTER_DONE             0x50100000
1350 	#define FW_MSG_CODE_DIAG_REFUSE                 0x50200000
1351 	#define FW_MSG_CODE_DIAG_EXIT_DONE              0x60100000
1352 	#define FW_MSG_CODE_VALIDATE_KEY_SUCCESS        0x70100000
1353 	#define FW_MSG_CODE_VALIDATE_KEY_FAILURE        0x70200000
1354 	#define FW_MSG_CODE_GET_KEY_DONE                0x80100000
1355 	#define FW_MSG_CODE_NO_KEY                      0x80f00000
1356 	#define FW_MSG_CODE_LIC_INFO_NOT_READY          0x80f80000
1357 	#define FW_MSG_CODE_L2B_PRAM_LOADED             0x90100000
1358 	#define FW_MSG_CODE_L2B_PRAM_T_LOAD_FAILURE     0x90210000
1359 	#define FW_MSG_CODE_L2B_PRAM_C_LOAD_FAILURE     0x90220000
1360 	#define FW_MSG_CODE_L2B_PRAM_X_LOAD_FAILURE     0x90230000
1361 	#define FW_MSG_CODE_L2B_PRAM_U_LOAD_FAILURE     0x90240000
1362 	#define FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS        0xa0100000
1363 	#define FW_MSG_CODE_VRFY_OPT_MDL_INVLD_IMG      0xa0200000
1364 	#define FW_MSG_CODE_VRFY_OPT_MDL_UNAPPROVED     0xa0300000
1365 	#define FW_MSG_CODE_VF_DISABLED_DONE            0xb0000000
1366 	#define FW_MSG_CODE_HW_SET_INVALID_IMAGE        0xb0100000
1367 
1368 	#define FW_MSG_CODE_AFEX_DRIVER_SETMAC_DONE     0xd0100000
1369 	#define FW_MSG_CODE_AFEX_LISTGET_ACK            0xd1100000
1370 	#define FW_MSG_CODE_AFEX_LISTSET_ACK            0xd2100000
1371 	#define FW_MSG_CODE_AFEX_STATSGET_ACK           0xd3100000
1372 	#define FW_MSG_CODE_AFEX_VIFSET_ACK             0xd4100000
1373 
1374 	#define FW_MSG_CODE_DRV_INFO_ACK                0xd8100000
1375 	#define FW_MSG_CODE_DRV_INFO_NACK               0xd9100000
1376 
1377 	#define FW_MSG_CODE_EEE_RESULS_ACK              0xda100000
1378 
1379 	#define FW_MSG_CODE_RMMOD_ACK                   0xdb100000
1380 
1381 	#define FW_MSG_CODE_SET_MF_BW_SENT              0xe0000000
1382 	#define FW_MSG_CODE_SET_MF_BW_DONE              0xe1000000
1383 
1384 	#define FW_MSG_CODE_LINK_CHANGED_ACK            0x01100000
1385 
1386 	#define FW_MSG_CODE_LIC_CHALLENGE               0xff010000
1387 	#define FW_MSG_CODE_LIC_RESPONSE                0xff020000
1388 	#define FW_MSG_CODE_VIRT_MAC_PRIM               0xff030000
1389 	#define FW_MSG_CODE_VIRT_MAC_ISCSI              0xff040000
1390 
1391 	#define FW_MSG_SEQ_NUMBER_MASK                  0x0000ffff
1392 
1393 	u32 fw_mb_param;
1394 
1395 	u32 drv_pulse_mb;
1396 	#define DRV_PULSE_SEQ_MASK                      0x00007fff
1397 	#define DRV_PULSE_SYSTEM_TIME_MASK              0xffff0000
1398 	/*
1399 	 * The system time is in the format of
1400 	 * (year-2001)*12*32 + month*32 + day.
1401 	 */
1402 	#define DRV_PULSE_ALWAYS_ALIVE                  0x00008000
1403 	/*
1404 	 * Indicate to the firmware not to go into the
1405 	 * OS-absent when it is not getting driver pulse.
1406 	 * This is used for debugging as well for PXE(MBA).
1407 	 */
1408 
1409 	u32 mcp_pulse_mb;
1410 	#define MCP_PULSE_SEQ_MASK                      0x00007fff
1411 	#define MCP_PULSE_ALWAYS_ALIVE                  0x00008000
1412 	/* Indicates to the driver not to assert due to lack
1413 	 * of MCP response */
1414 	#define MCP_EVENT_MASK                          0xffff0000
1415 	#define MCP_EVENT_OTHER_DRIVER_RESET_REQ        0x00010000
1416 
1417 	u32 iscsi_boot_signature;
1418 	u32 iscsi_boot_block_offset;
1419 
1420 	u32 drv_status;
1421 	#define DRV_STATUS_PMF                          0x00000001
1422 	#define DRV_STATUS_VF_DISABLED                  0x00000002
1423 	#define DRV_STATUS_SET_MF_BW                    0x00000004
1424 	#define DRV_STATUS_LINK_EVENT                   0x00000008
1425 
1426 	#define DRV_STATUS_DCC_EVENT_MASK               0x0000ff00
1427 	#define DRV_STATUS_DCC_DISABLE_ENABLE_PF        0x00000100
1428 	#define DRV_STATUS_DCC_BANDWIDTH_ALLOCATION     0x00000200
1429 	#define DRV_STATUS_DCC_CHANGE_MAC_ADDRESS       0x00000400
1430 	#define DRV_STATUS_DCC_RESERVED1                0x00000800
1431 	#define DRV_STATUS_DCC_SET_PROTOCOL             0x00001000
1432 	#define DRV_STATUS_DCC_SET_PRIORITY             0x00002000
1433 
1434 	#define DRV_STATUS_DCBX_EVENT_MASK              0x000f0000
1435 	#define DRV_STATUS_DCBX_NEGOTIATION_RESULTS     0x00010000
1436 	#define DRV_STATUS_AFEX_EVENT_MASK              0x03f00000
1437 	#define DRV_STATUS_AFEX_LISTGET_REQ             0x00100000
1438 	#define DRV_STATUS_AFEX_LISTSET_REQ             0x00200000
1439 	#define DRV_STATUS_AFEX_STATSGET_REQ            0x00400000
1440 	#define DRV_STATUS_AFEX_VIFSET_REQ              0x00800000
1441 
1442 	#define DRV_STATUS_DRV_INFO_REQ                 0x04000000
1443 
1444 	#define DRV_STATUS_EEE_NEGOTIATION_RESULTS      0x08000000
1445 
1446 	u32 virt_mac_upper;
1447 	#define VIRT_MAC_SIGN_MASK                      0xffff0000
1448 	#define VIRT_MAC_SIGNATURE                      0x564d0000
1449 	u32 virt_mac_lower;
1450 
1451 };
1452 
1453 
1454 /****************************************************************************
1455  * Management firmware state                                                *
1456  ****************************************************************************/
1457 /* Allocate 440 bytes for management firmware */
1458 #define MGMTFW_STATE_WORD_SIZE                          110
1459 
1460 struct mgmtfw_state {
1461 	u32 opaque[MGMTFW_STATE_WORD_SIZE];
1462 };
1463 
1464 
1465 /****************************************************************************
1466  * Multi-Function configuration                                             *
1467  ****************************************************************************/
1468 struct shared_mf_cfg {
1469 
1470 	u32 clp_mb;
1471 	#define SHARED_MF_CLP_SET_DEFAULT               0x00000000
1472 	/* set by CLP */
1473 	#define SHARED_MF_CLP_EXIT                      0x00000001
1474 	/* set by MCP */
1475 	#define SHARED_MF_CLP_EXIT_DONE                 0x00010000
1476 
1477 };
1478 
1479 struct port_mf_cfg {
1480 
1481 	u32 dynamic_cfg;    /* device control channel */
1482 	#define PORT_MF_CFG_E1HOV_TAG_MASK              0x0000ffff
1483 	#define PORT_MF_CFG_E1HOV_TAG_SHIFT             0
1484 	#define PORT_MF_CFG_E1HOV_TAG_DEFAULT         PORT_MF_CFG_E1HOV_TAG_MASK
1485 
1486 	u32 reserved[1];
1487 
1488 };
1489 
1490 struct func_mf_cfg {
1491 
1492 	u32 config;
1493 	/* E/R/I/D */
1494 	/* function 0 of each port cannot be hidden */
1495 	#define FUNC_MF_CFG_FUNC_HIDE                   0x00000001
1496 
1497 	#define FUNC_MF_CFG_PROTOCOL_MASK               0x00000006
1498 	#define FUNC_MF_CFG_PROTOCOL_FCOE               0x00000000
1499 	#define FUNC_MF_CFG_PROTOCOL_ETHERNET           0x00000002
1500 	#define FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA 0x00000004
1501 	#define FUNC_MF_CFG_PROTOCOL_ISCSI              0x00000006
1502 	#define FUNC_MF_CFG_PROTOCOL_DEFAULT \
1503 				FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA
1504 
1505 	#define FUNC_MF_CFG_FUNC_DISABLED               0x00000008
1506 	#define FUNC_MF_CFG_FUNC_DELETED                0x00000010
1507 
1508 	/* PRI */
1509 	/* 0 - low priority, 3 - high priority */
1510 	#define FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK      0x00000300
1511 	#define FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT     8
1512 	#define FUNC_MF_CFG_TRANSMIT_PRIORITY_DEFAULT   0x00000000
1513 
1514 	/* MINBW, MAXBW */
1515 	/* value range - 0..100, increments in 100Mbps */
1516 	#define FUNC_MF_CFG_MIN_BW_MASK                 0x00ff0000
1517 	#define FUNC_MF_CFG_MIN_BW_SHIFT                16
1518 	#define FUNC_MF_CFG_MIN_BW_DEFAULT              0x00000000
1519 	#define FUNC_MF_CFG_MAX_BW_MASK                 0xff000000
1520 	#define FUNC_MF_CFG_MAX_BW_SHIFT                24
1521 	#define FUNC_MF_CFG_MAX_BW_DEFAULT              0x64000000
1522 
1523 	u32 mac_upper;	    /* MAC */
1524 	#define FUNC_MF_CFG_UPPERMAC_MASK               0x0000ffff
1525 	#define FUNC_MF_CFG_UPPERMAC_SHIFT              0
1526 	#define FUNC_MF_CFG_UPPERMAC_DEFAULT           FUNC_MF_CFG_UPPERMAC_MASK
1527 	u32 mac_lower;
1528 	#define FUNC_MF_CFG_LOWERMAC_DEFAULT            0xffffffff
1529 
1530 	u32 e1hov_tag;	/* VNI */
1531 	#define FUNC_MF_CFG_E1HOV_TAG_MASK              0x0000ffff
1532 	#define FUNC_MF_CFG_E1HOV_TAG_SHIFT             0
1533 	#define FUNC_MF_CFG_E1HOV_TAG_DEFAULT         FUNC_MF_CFG_E1HOV_TAG_MASK
1534 
1535 	/* afex default VLAN ID - 12 bits */
1536 	#define FUNC_MF_CFG_AFEX_VLAN_MASK              0x0fff0000
1537 	#define FUNC_MF_CFG_AFEX_VLAN_SHIFT             16
1538 
1539 	u32 afex_config;
1540 	#define FUNC_MF_CFG_AFEX_COS_FILTER_MASK                     0x000000ff
1541 	#define FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT                    0
1542 	#define FUNC_MF_CFG_AFEX_MBA_ENABLED_MASK                    0x0000ff00
1543 	#define FUNC_MF_CFG_AFEX_MBA_ENABLED_SHIFT                   8
1544 	#define FUNC_MF_CFG_AFEX_MBA_ENABLED_VAL                     0x00000100
1545 	#define FUNC_MF_CFG_AFEX_VLAN_MODE_MASK                      0x000f0000
1546 	#define FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT                     16
1547 
1548 	u32 reserved;
1549 };
1550 
1551 enum mf_cfg_afex_vlan_mode {
1552 	FUNC_MF_CFG_AFEX_VLAN_TRUNK_MODE = 0,
1553 	FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE,
1554 	FUNC_MF_CFG_AFEX_VLAN_TRUNK_TAG_NATIVE_MODE
1555 };
1556 
1557 /* This structure is not applicable and should not be accessed on 57711 */
1558 struct func_ext_cfg {
1559 	u32 func_cfg;
1560 	#define MACP_FUNC_CFG_FLAGS_MASK                0x0000007F
1561 	#define MACP_FUNC_CFG_FLAGS_SHIFT               0
1562 	#define MACP_FUNC_CFG_FLAGS_ENABLED             0x00000001
1563 	#define MACP_FUNC_CFG_FLAGS_ETHERNET            0x00000002
1564 	#define MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD       0x00000004
1565 	#define MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD        0x00000008
1566 	#define MACP_FUNC_CFG_PAUSE_ON_HOST_RING        0x00000080
1567 
1568 	u32 iscsi_mac_addr_upper;
1569 	u32 iscsi_mac_addr_lower;
1570 
1571 	u32 fcoe_mac_addr_upper;
1572 	u32 fcoe_mac_addr_lower;
1573 
1574 	u32 fcoe_wwn_port_name_upper;
1575 	u32 fcoe_wwn_port_name_lower;
1576 
1577 	u32 fcoe_wwn_node_name_upper;
1578 	u32 fcoe_wwn_node_name_lower;
1579 
1580 	u32 preserve_data;
1581 	#define MF_FUNC_CFG_PRESERVE_L2_MAC             (1<<0)
1582 	#define MF_FUNC_CFG_PRESERVE_ISCSI_MAC          (1<<1)
1583 	#define MF_FUNC_CFG_PRESERVE_FCOE_MAC           (1<<2)
1584 	#define MF_FUNC_CFG_PRESERVE_FCOE_WWN_P         (1<<3)
1585 	#define MF_FUNC_CFG_PRESERVE_FCOE_WWN_N         (1<<4)
1586 	#define MF_FUNC_CFG_PRESERVE_TX_BW              (1<<5)
1587 };
1588 
1589 struct mf_cfg {
1590 
1591 	struct shared_mf_cfg    shared_mf_config;       /* 0x4 */
1592 							/* 0x8*2*2=0x20 */
1593 	struct port_mf_cfg  port_mf_config[NVM_PATH_MAX][PORT_MAX];
1594 	/* for all chips, there are 8 mf functions */
1595 	struct func_mf_cfg  func_mf_config[E1H_FUNC_MAX]; /* 0x18 * 8 = 0xc0 */
1596 	/*
1597 	 * Extended configuration per function  - this array does not exist and
1598 	 * should not be accessed on 57711
1599 	 */
1600 	struct func_ext_cfg func_ext_config[E1H_FUNC_MAX]; /* 0x28 * 8 = 0x140*/
1601 }; /* 0x224 */
1602 
1603 /****************************************************************************
1604  * Shared Memory Region                                                     *
1605  ****************************************************************************/
1606 struct shmem_region {		       /*   SharedMem Offset (size) */
1607 
1608 	u32         validity_map[PORT_MAX];  /* 0x0 (4*2 = 0x8) */
1609 	#define SHR_MEM_FORMAT_REV_MASK                     0xff000000
1610 	#define SHR_MEM_FORMAT_REV_ID                       ('A'<<24)
1611 	/* validity bits */
1612 	#define SHR_MEM_VALIDITY_PCI_CFG                    0x00100000
1613 	#define SHR_MEM_VALIDITY_MB                         0x00200000
1614 	#define SHR_MEM_VALIDITY_DEV_INFO                   0x00400000
1615 	#define SHR_MEM_VALIDITY_RESERVED                   0x00000007
1616 	/* One licensing bit should be set */
1617 	#define SHR_MEM_VALIDITY_LIC_KEY_IN_EFFECT_MASK     0x00000038
1618 	#define SHR_MEM_VALIDITY_LIC_MANUF_KEY_IN_EFFECT    0x00000008
1619 	#define SHR_MEM_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT  0x00000010
1620 	#define SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT       0x00000020
1621 	/* Active MFW */
1622 	#define SHR_MEM_VALIDITY_ACTIVE_MFW_UNKNOWN         0x00000000
1623 	#define SHR_MEM_VALIDITY_ACTIVE_MFW_MASK            0x000001c0
1624 	#define SHR_MEM_VALIDITY_ACTIVE_MFW_IPMI            0x00000040
1625 	#define SHR_MEM_VALIDITY_ACTIVE_MFW_UMP             0x00000080
1626 	#define SHR_MEM_VALIDITY_ACTIVE_MFW_NCSI            0x000000c0
1627 	#define SHR_MEM_VALIDITY_ACTIVE_MFW_NONE            0x000001c0
1628 
1629 	struct shm_dev_info dev_info;	     /* 0x8     (0x438) */
1630 
1631 	struct license_key       drv_lic_key[PORT_MAX]; /* 0x440 (52*2=0x68) */
1632 
1633 	/* FW information (for internal FW use) */
1634 	u32         fw_info_fio_offset;		/* 0x4a8       (0x4) */
1635 	struct mgmtfw_state mgmtfw_state;	/* 0x4ac     (0x1b8) */
1636 
1637 	struct drv_port_mb  port_mb[PORT_MAX];	/* 0x664 (16*2=0x20) */
1638 
1639 #ifdef BMAPI
1640 	/* This is a variable length array */
1641 	/* the number of function depends on the chip type */
1642 	struct drv_func_mb func_mb[1];	/* 0x684 (44*2/4/8=0x58/0xb0/0x160) */
1643 #else
1644 	/* the number of function depends on the chip type */
1645 	struct drv_func_mb  func_mb[];	/* 0x684 (44*2/4/8=0x58/0xb0/0x160) */
1646 #endif /* BMAPI */
1647 
1648 }; /* 57710 = 0x6dc | 57711 = 0x7E4 | 57712 = 0x734 */
1649 
1650 /****************************************************************************
1651  * Shared Memory 2 Region                                                   *
1652  ****************************************************************************/
1653 /* The fw_flr_ack is actually built in the following way:                   */
1654 /* 8 bit:  PF ack                                                           */
1655 /* 64 bit: VF ack                                                           */
1656 /* 8 bit:  ios_dis_ack                                                      */
1657 /* In order to maintain endianity in the mailbox hsi, we want to keep using */
1658 /* u32. The fw must have the VF right after the PF since this is how it     */
1659 /* access arrays(it expects always the VF to reside after the PF, and that  */
1660 /* makes the calculation much easier for it. )                              */
1661 /* In order to answer both limitations, and keep the struct small, the code */
1662 /* will abuse the structure defined here to achieve the actual partition    */
1663 /* above                                                                    */
1664 /****************************************************************************/
1665 struct fw_flr_ack {
1666 	u32         pf_ack;
1667 	u32         vf_ack[1];
1668 	u32         iov_dis_ack;
1669 };
1670 
1671 struct fw_flr_mb {
1672 	u32         aggint;
1673 	u32         opgen_addr;
1674 	struct fw_flr_ack ack;
1675 };
1676 
1677 struct eee_remote_vals {
1678 	u32         tx_tw;
1679 	u32         rx_tw;
1680 };
1681 
1682 /**** SUPPORT FOR SHMEM ARRRAYS ***
1683  * The SHMEM HSI is aligned on 32 bit boundaries which makes it difficult to
1684  * define arrays with storage types smaller then unsigned dwords.
1685  * The macros below add generic support for SHMEM arrays with numeric elements
1686  * that can span 2,4,8 or 16 bits. The array underlying type is a 32 bit dword
1687  * array with individual bit-filed elements accessed using shifts and masks.
1688  *
1689  */
1690 
1691 /* eb is the bitwidth of a single element */
1692 #define SHMEM_ARRAY_MASK(eb)		((1<<(eb))-1)
1693 #define SHMEM_ARRAY_ENTRY(i, eb)	((i)/(32/(eb)))
1694 
1695 /* the bit-position macro allows the used to flip the order of the arrays
1696  * elements on a per byte or word boundary.
1697  *
1698  * example: an array with 8 entries each 4 bit wide. This array will fit into
1699  * a single dword. The diagrmas below show the array order of the nibbles.
1700  *
1701  * SHMEM_ARRAY_BITPOS(i, 4, 4) defines the stadard ordering:
1702  *
1703  *                |                |                |               |
1704  *   0    |   1   |   2    |   3   |   4    |   5   |   6   |   7   |
1705  *                |                |                |               |
1706  *
1707  * SHMEM_ARRAY_BITPOS(i, 4, 8) defines a flip ordering per byte:
1708  *
1709  *                |                |                |               |
1710  *   1   |   0    |   3    |   2   |   5    |   4   |   7   |   6   |
1711  *                |                |                |               |
1712  *
1713  * SHMEM_ARRAY_BITPOS(i, 4, 16) defines a flip ordering per word:
1714  *
1715  *                |                |                |               |
1716  *   3   |   2    |   1   |   0    |   7   |   6    |   5   |   4   |
1717  *                |                |                |               |
1718  */
1719 #define SHMEM_ARRAY_BITPOS(i, eb, fb)	\
1720 	((((32/(fb)) - 1 - ((i)/((fb)/(eb))) % (32/(fb))) * (fb)) + \
1721 	(((i)%((fb)/(eb))) * (eb)))
1722 
1723 #define SHMEM_ARRAY_GET(a, i, eb, fb)					\
1724 	((a[SHMEM_ARRAY_ENTRY(i, eb)] >> SHMEM_ARRAY_BITPOS(i, eb, fb)) &  \
1725 	SHMEM_ARRAY_MASK(eb))
1726 
1727 #define SHMEM_ARRAY_SET(a, i, eb, fb, val)				\
1728 do {									   \
1729 	a[SHMEM_ARRAY_ENTRY(i, eb)] &= ~(SHMEM_ARRAY_MASK(eb) <<	   \
1730 	SHMEM_ARRAY_BITPOS(i, eb, fb));					   \
1731 	a[SHMEM_ARRAY_ENTRY(i, eb)] |= (((val) & SHMEM_ARRAY_MASK(eb)) <<  \
1732 	SHMEM_ARRAY_BITPOS(i, eb, fb));					   \
1733 } while (0)
1734 
1735 
1736 /****START OF DCBX STRUCTURES DECLARATIONS****/
1737 #define DCBX_MAX_NUM_PRI_PG_ENTRIES	8
1738 #define DCBX_PRI_PG_BITWIDTH		4
1739 #define DCBX_PRI_PG_FBITS		8
1740 #define DCBX_PRI_PG_GET(a, i)		\
1741 	SHMEM_ARRAY_GET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS)
1742 #define DCBX_PRI_PG_SET(a, i, val)	\
1743 	SHMEM_ARRAY_SET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS, val)
1744 #define DCBX_MAX_NUM_PG_BW_ENTRIES	8
1745 #define DCBX_BW_PG_BITWIDTH		8
1746 #define DCBX_PG_BW_GET(a, i)		\
1747 	SHMEM_ARRAY_GET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH)
1748 #define DCBX_PG_BW_SET(a, i, val)	\
1749 	SHMEM_ARRAY_SET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH, val)
1750 #define DCBX_STRICT_PRI_PG		15
1751 #define DCBX_MAX_APP_PROTOCOL		16
1752 #define FCOE_APP_IDX			0
1753 #define ISCSI_APP_IDX			1
1754 #define PREDEFINED_APP_IDX_MAX		2
1755 
1756 
1757 /* Big/Little endian have the same representation. */
1758 struct dcbx_ets_feature {
1759 	/*
1760 	 * For Admin MIB - is this feature supported by the
1761 	 * driver | For Local MIB - should this feature be enabled.
1762 	 */
1763 	u32 enabled;
1764 	u32  pg_bw_tbl[2];
1765 	u32  pri_pg_tbl[1];
1766 };
1767 
1768 /* Driver structure in LE */
1769 struct dcbx_pfc_feature {
1770 #ifdef __BIG_ENDIAN
1771 	u8 pri_en_bitmap;
1772 	#define DCBX_PFC_PRI_0 0x01
1773 	#define DCBX_PFC_PRI_1 0x02
1774 	#define DCBX_PFC_PRI_2 0x04
1775 	#define DCBX_PFC_PRI_3 0x08
1776 	#define DCBX_PFC_PRI_4 0x10
1777 	#define DCBX_PFC_PRI_5 0x20
1778 	#define DCBX_PFC_PRI_6 0x40
1779 	#define DCBX_PFC_PRI_7 0x80
1780 	u8 pfc_caps;
1781 	u8 reserved;
1782 	u8 enabled;
1783 #elif defined(__LITTLE_ENDIAN)
1784 	u8 enabled;
1785 	u8 reserved;
1786 	u8 pfc_caps;
1787 	u8 pri_en_bitmap;
1788 	#define DCBX_PFC_PRI_0 0x01
1789 	#define DCBX_PFC_PRI_1 0x02
1790 	#define DCBX_PFC_PRI_2 0x04
1791 	#define DCBX_PFC_PRI_3 0x08
1792 	#define DCBX_PFC_PRI_4 0x10
1793 	#define DCBX_PFC_PRI_5 0x20
1794 	#define DCBX_PFC_PRI_6 0x40
1795 	#define DCBX_PFC_PRI_7 0x80
1796 #endif
1797 };
1798 
1799 struct dcbx_app_priority_entry {
1800 #ifdef __BIG_ENDIAN
1801 	u16  app_id;
1802 	u8  pri_bitmap;
1803 	u8  appBitfield;
1804 	#define DCBX_APP_ENTRY_VALID         0x01
1805 	#define DCBX_APP_ENTRY_SF_MASK       0x30
1806 	#define DCBX_APP_ENTRY_SF_SHIFT      4
1807 	#define DCBX_APP_SF_ETH_TYPE         0x10
1808 	#define DCBX_APP_SF_PORT             0x20
1809 #elif defined(__LITTLE_ENDIAN)
1810 	u8 appBitfield;
1811 	#define DCBX_APP_ENTRY_VALID         0x01
1812 	#define DCBX_APP_ENTRY_SF_MASK       0x30
1813 	#define DCBX_APP_ENTRY_SF_SHIFT      4
1814 	#define DCBX_APP_SF_ETH_TYPE         0x10
1815 	#define DCBX_APP_SF_PORT             0x20
1816 	u8  pri_bitmap;
1817 	u16  app_id;
1818 #endif
1819 };
1820 
1821 
1822 /* FW structure in BE */
1823 struct dcbx_app_priority_feature {
1824 #ifdef __BIG_ENDIAN
1825 	u8 reserved;
1826 	u8 default_pri;
1827 	u8 tc_supported;
1828 	u8 enabled;
1829 #elif defined(__LITTLE_ENDIAN)
1830 	u8 enabled;
1831 	u8 tc_supported;
1832 	u8 default_pri;
1833 	u8 reserved;
1834 #endif
1835 	struct dcbx_app_priority_entry  app_pri_tbl[DCBX_MAX_APP_PROTOCOL];
1836 };
1837 
1838 /* FW structure in BE */
1839 struct dcbx_features {
1840 	/* PG feature */
1841 	struct dcbx_ets_feature ets;
1842 	/* PFC feature */
1843 	struct dcbx_pfc_feature pfc;
1844 	/* APP feature */
1845 	struct dcbx_app_priority_feature app;
1846 };
1847 
1848 /* LLDP protocol parameters */
1849 /* FW structure in BE */
1850 struct lldp_params {
1851 #ifdef __BIG_ENDIAN
1852 	u8  msg_fast_tx_interval;
1853 	u8  msg_tx_hold;
1854 	u8  msg_tx_interval;
1855 	u8  admin_status;
1856 	#define LLDP_TX_ONLY  0x01
1857 	#define LLDP_RX_ONLY  0x02
1858 	#define LLDP_TX_RX    0x03
1859 	#define LLDP_DISABLED 0x04
1860 	u8  reserved1;
1861 	u8  tx_fast;
1862 	u8  tx_crd_max;
1863 	u8  tx_crd;
1864 #elif defined(__LITTLE_ENDIAN)
1865 	u8  admin_status;
1866 	#define LLDP_TX_ONLY  0x01
1867 	#define LLDP_RX_ONLY  0x02
1868 	#define LLDP_TX_RX    0x03
1869 	#define LLDP_DISABLED 0x04
1870 	u8  msg_tx_interval;
1871 	u8  msg_tx_hold;
1872 	u8  msg_fast_tx_interval;
1873 	u8  tx_crd;
1874 	u8  tx_crd_max;
1875 	u8  tx_fast;
1876 	u8  reserved1;
1877 #endif
1878 	#define REM_CHASSIS_ID_STAT_LEN 4
1879 	#define REM_PORT_ID_STAT_LEN 4
1880 	/* Holds remote Chassis ID TLV header, subtype and 9B of payload. */
1881 	u32 peer_chassis_id[REM_CHASSIS_ID_STAT_LEN];
1882 	/* Holds remote Port ID TLV header, subtype and 9B of payload. */
1883 	u32 peer_port_id[REM_PORT_ID_STAT_LEN];
1884 };
1885 
1886 struct lldp_dcbx_stat {
1887 	#define LOCAL_CHASSIS_ID_STAT_LEN 2
1888 	#define LOCAL_PORT_ID_STAT_LEN 2
1889 	/* Holds local Chassis ID 8B payload of constant subtype 4. */
1890 	u32 local_chassis_id[LOCAL_CHASSIS_ID_STAT_LEN];
1891 	/* Holds local Port ID 8B payload of constant subtype 3. */
1892 	u32 local_port_id[LOCAL_PORT_ID_STAT_LEN];
1893 	/* Number of DCBX frames transmitted. */
1894 	u32 num_tx_dcbx_pkts;
1895 	/* Number of DCBX frames received. */
1896 	u32 num_rx_dcbx_pkts;
1897 };
1898 
1899 /* ADMIN MIB - DCBX local machine default configuration. */
1900 struct lldp_admin_mib {
1901 	u32     ver_cfg_flags;
1902 	#define DCBX_ETS_CONFIG_TX_ENABLED       0x00000001
1903 	#define DCBX_PFC_CONFIG_TX_ENABLED       0x00000002
1904 	#define DCBX_APP_CONFIG_TX_ENABLED       0x00000004
1905 	#define DCBX_ETS_RECO_TX_ENABLED         0x00000008
1906 	#define DCBX_ETS_RECO_VALID              0x00000010
1907 	#define DCBX_ETS_WILLING                 0x00000020
1908 	#define DCBX_PFC_WILLING                 0x00000040
1909 	#define DCBX_APP_WILLING                 0x00000080
1910 	#define DCBX_VERSION_CEE                 0x00000100
1911 	#define DCBX_VERSION_IEEE                0x00000200
1912 	#define DCBX_DCBX_ENABLED                0x00000400
1913 	#define DCBX_CEE_VERSION_MASK            0x0000f000
1914 	#define DCBX_CEE_VERSION_SHIFT           12
1915 	#define DCBX_CEE_MAX_VERSION_MASK        0x000f0000
1916 	#define DCBX_CEE_MAX_VERSION_SHIFT       16
1917 	struct dcbx_features     features;
1918 };
1919 
1920 /* REMOTE MIB - remote machine DCBX configuration. */
1921 struct lldp_remote_mib {
1922 	u32 prefix_seq_num;
1923 	u32 flags;
1924 	#define DCBX_ETS_TLV_RX                  0x00000001
1925 	#define DCBX_PFC_TLV_RX                  0x00000002
1926 	#define DCBX_APP_TLV_RX                  0x00000004
1927 	#define DCBX_ETS_RX_ERROR                0x00000010
1928 	#define DCBX_PFC_RX_ERROR                0x00000020
1929 	#define DCBX_APP_RX_ERROR                0x00000040
1930 	#define DCBX_ETS_REM_WILLING             0x00000100
1931 	#define DCBX_PFC_REM_WILLING             0x00000200
1932 	#define DCBX_APP_REM_WILLING             0x00000400
1933 	#define DCBX_REMOTE_ETS_RECO_VALID       0x00001000
1934 	#define DCBX_REMOTE_MIB_VALID            0x00002000
1935 	struct dcbx_features features;
1936 	u32 suffix_seq_num;
1937 };
1938 
1939 /* LOCAL MIB - operational DCBX configuration - transmitted on Tx LLDPDU. */
1940 struct lldp_local_mib {
1941 	u32 prefix_seq_num;
1942 	/* Indicates if there is mismatch with negotiation results. */
1943 	u32 error;
1944 	#define DCBX_LOCAL_ETS_ERROR             0x00000001
1945 	#define DCBX_LOCAL_PFC_ERROR             0x00000002
1946 	#define DCBX_LOCAL_APP_ERROR             0x00000004
1947 	#define DCBX_LOCAL_PFC_MISMATCH          0x00000010
1948 	#define DCBX_LOCAL_APP_MISMATCH          0x00000020
1949 	#define DCBX_REMOTE_MIB_ERROR		 0x00000040
1950 	#define DCBX_REMOTE_ETS_TLV_NOT_FOUND    0x00000080
1951 	#define DCBX_REMOTE_PFC_TLV_NOT_FOUND    0x00000100
1952 	#define DCBX_REMOTE_APP_TLV_NOT_FOUND    0x00000200
1953 	struct dcbx_features   features;
1954 	u32 suffix_seq_num;
1955 };
1956 /***END OF DCBX STRUCTURES DECLARATIONS***/
1957 
1958 /***********************************************************/
1959 /*                         Elink section                   */
1960 /***********************************************************/
1961 #define SHMEM_LINK_CONFIG_SIZE 2
1962 struct shmem_lfa {
1963 	u32 req_duplex;
1964 	#define REQ_DUPLEX_PHY0_MASK        0x0000ffff
1965 	#define REQ_DUPLEX_PHY0_SHIFT       0
1966 	#define REQ_DUPLEX_PHY1_MASK        0xffff0000
1967 	#define REQ_DUPLEX_PHY1_SHIFT       16
1968 	u32 req_flow_ctrl;
1969 	#define REQ_FLOW_CTRL_PHY0_MASK     0x0000ffff
1970 	#define REQ_FLOW_CTRL_PHY0_SHIFT    0
1971 	#define REQ_FLOW_CTRL_PHY1_MASK     0xffff0000
1972 	#define REQ_FLOW_CTRL_PHY1_SHIFT    16
1973 	u32 req_line_speed; /* Also determine AutoNeg */
1974 	#define REQ_LINE_SPD_PHY0_MASK      0x0000ffff
1975 	#define REQ_LINE_SPD_PHY0_SHIFT     0
1976 	#define REQ_LINE_SPD_PHY1_MASK      0xffff0000
1977 	#define REQ_LINE_SPD_PHY1_SHIFT     16
1978 	u32 speed_cap_mask[SHMEM_LINK_CONFIG_SIZE];
1979 	u32 additional_config;
1980 	#define REQ_FC_AUTO_ADV_MASK        0x0000ffff
1981 	#define REQ_FC_AUTO_ADV0_SHIFT      0
1982 	#define NO_LFA_DUE_TO_DCC_MASK      0x00010000
1983 	u32 lfa_sts;
1984 	#define LFA_LINK_FLAP_REASON_OFFSET		0
1985 	#define LFA_LINK_FLAP_REASON_MASK		0x000000ff
1986 		#define LFA_LINK_DOWN			    0x1
1987 		#define LFA_LOOPBACK_ENABLED		0x2
1988 		#define LFA_DUPLEX_MISMATCH		    0x3
1989 		#define LFA_MFW_IS_TOO_OLD		    0x4
1990 		#define LFA_LINK_SPEED_MISMATCH		0x5
1991 		#define LFA_FLOW_CTRL_MISMATCH		0x6
1992 		#define LFA_SPEED_CAP_MISMATCH		0x7
1993 		#define LFA_DCC_LFA_DISABLED		0x8
1994 		#define LFA_EEE_MISMATCH		0x9
1995 
1996 	#define LINK_FLAP_AVOIDANCE_COUNT_OFFSET	8
1997 	#define LINK_FLAP_AVOIDANCE_COUNT_MASK		0x0000ff00
1998 
1999 	#define LINK_FLAP_COUNT_OFFSET			16
2000 	#define LINK_FLAP_COUNT_MASK			0x00ff0000
2001 
2002 	#define LFA_FLAGS_MASK				0xff000000
2003 	#define SHMEM_LFA_DONT_CLEAR_STAT		(1<<24)
2004 };
2005 
2006 /* Used to support NSCI get OS driver version
2007  * on driver load the version value will be set
2008  * on driver unload driver value of 0x0 will be set.
2009  */
2010 struct os_drv_ver {
2011 #define DRV_VER_NOT_LOADED			0
2012 
2013 	/* personalties order is important */
2014 #define DRV_PERS_ETHERNET			0
2015 #define DRV_PERS_ISCSI				1
2016 #define DRV_PERS_FCOE				2
2017 
2018 	/* shmem2 struct is constant can't add more personalties here */
2019 #define MAX_DRV_PERS				3
2020 	u32 versions[MAX_DRV_PERS];
2021 };
2022 
2023 struct ncsi_oem_fcoe_features {
2024 	u32 fcoe_features1;
2025 	#define FCOE_FEATURES1_IOS_PER_CONNECTION_MASK          0x0000FFFF
2026 	#define FCOE_FEATURES1_IOS_PER_CONNECTION_OFFSET        0
2027 
2028 	#define FCOE_FEATURES1_LOGINS_PER_PORT_MASK             0xFFFF0000
2029 	#define FCOE_FEATURES1_LOGINS_PER_PORT_OFFSET           16
2030 
2031 	u32 fcoe_features2;
2032 	#define FCOE_FEATURES2_EXCHANGES_MASK                   0x0000FFFF
2033 	#define FCOE_FEATURES2_EXCHANGES_OFFSET                 0
2034 
2035 	#define FCOE_FEATURES2_NPIV_WWN_PER_PORT_MASK           0xFFFF0000
2036 	#define FCOE_FEATURES2_NPIV_WWN_PER_PORT_OFFSET         16
2037 
2038 	u32 fcoe_features3;
2039 	#define FCOE_FEATURES3_TARGETS_SUPPORTED_MASK           0x0000FFFF
2040 	#define FCOE_FEATURES3_TARGETS_SUPPORTED_OFFSET         0
2041 
2042 	#define FCOE_FEATURES3_OUTSTANDING_COMMANDS_MASK        0xFFFF0000
2043 	#define FCOE_FEATURES3_OUTSTANDING_COMMANDS_OFFSET      16
2044 
2045 	u32 fcoe_features4;
2046 	#define FCOE_FEATURES4_FEATURE_SETTINGS_MASK            0x0000000F
2047 	#define FCOE_FEATURES4_FEATURE_SETTINGS_OFFSET          0
2048 };
2049 
2050 struct ncsi_oem_data {
2051 	u32 driver_version[4];
2052 	struct ncsi_oem_fcoe_features ncsi_oem_fcoe_features;
2053 };
2054 
2055 struct shmem2_region {
2056 
2057 	u32 size;					/* 0x0000 */
2058 
2059 	u32 dcc_support;				/* 0x0004 */
2060 	#define SHMEM_DCC_SUPPORT_NONE                      0x00000000
2061 	#define SHMEM_DCC_SUPPORT_DISABLE_ENABLE_PF_TLV     0x00000001
2062 	#define SHMEM_DCC_SUPPORT_BANDWIDTH_ALLOCATION_TLV  0x00000004
2063 	#define SHMEM_DCC_SUPPORT_CHANGE_MAC_ADDRESS_TLV    0x00000008
2064 	#define SHMEM_DCC_SUPPORT_SET_PROTOCOL_TLV          0x00000040
2065 	#define SHMEM_DCC_SUPPORT_SET_PRIORITY_TLV          0x00000080
2066 
2067 	u32 ext_phy_fw_version2[PORT_MAX];		/* 0x0008 */
2068 	/*
2069 	 * For backwards compatibility, if the mf_cfg_addr does not exist
2070 	 * (the size filed is smaller than 0xc) the mf_cfg resides at the
2071 	 * end of struct shmem_region
2072 	 */
2073 	u32 mf_cfg_addr;				/* 0x0010 */
2074 	#define SHMEM_MF_CFG_ADDR_NONE                  0x00000000
2075 
2076 	struct fw_flr_mb flr_mb;			/* 0x0014 */
2077 	u32 dcbx_lldp_params_offset;			/* 0x0028 */
2078 	#define SHMEM_LLDP_DCBX_PARAMS_NONE             0x00000000
2079 	u32 dcbx_neg_res_offset;			/* 0x002c */
2080 	#define SHMEM_DCBX_NEG_RES_NONE			0x00000000
2081 	u32 dcbx_remote_mib_offset;			/* 0x0030 */
2082 	#define SHMEM_DCBX_REMOTE_MIB_NONE              0x00000000
2083 	/*
2084 	 * The other shmemX_base_addr holds the other path's shmem address
2085 	 * required for example in case of common phy init, or for path1 to know
2086 	 * the address of mcp debug trace which is located in offset from shmem
2087 	 * of path0
2088 	 */
2089 	u32 other_shmem_base_addr;			/* 0x0034 */
2090 	u32 other_shmem2_base_addr;			/* 0x0038 */
2091 	/*
2092 	 * mcp_vf_disabled is set by the MCP to indicate the driver about VFs
2093 	 * which were disabled/flred
2094 	 */
2095 	u32 mcp_vf_disabled[E2_VF_MAX / 32];		/* 0x003c */
2096 
2097 	/*
2098 	 * drv_ack_vf_disabled is set by the PF driver to ack handled disabled
2099 	 * VFs
2100 	 */
2101 	u32 drv_ack_vf_disabled[E2_FUNC_MAX][E2_VF_MAX / 32]; /* 0x0044 */
2102 
2103 	u32 dcbx_lldp_dcbx_stat_offset;			/* 0x0064 */
2104 	#define SHMEM_LLDP_DCBX_STAT_NONE               0x00000000
2105 
2106 	/*
2107 	 * edebug_driver_if field is used to transfer messages between edebug
2108 	 * app to the driver through shmem2.
2109 	 *
2110 	 * message format:
2111 	 * bits 0-2 -  function number / instance of driver to perform request
2112 	 * bits 3-5 -  op code / is_ack?
2113 	 * bits 6-63 - data
2114 	 */
2115 	u32 edebug_driver_if[2];			/* 0x0068 */
2116 	#define EDEBUG_DRIVER_IF_OP_CODE_GET_PHYS_ADDR  1
2117 	#define EDEBUG_DRIVER_IF_OP_CODE_GET_BUS_ADDR   2
2118 	#define EDEBUG_DRIVER_IF_OP_CODE_DISABLE_STAT   3
2119 
2120 	u32 nvm_retain_bitmap_addr;			/* 0x0070 */
2121 
2122 	/* afex support of that driver */
2123 	u32 afex_driver_support;			/* 0x0074 */
2124 	#define SHMEM_AFEX_VERSION_MASK                  0x100f
2125 	#define SHMEM_AFEX_SUPPORTED_VERSION_ONE         0x1001
2126 	#define SHMEM_AFEX_REDUCED_DRV_LOADED            0x8000
2127 
2128 	/* driver receives addr in scratchpad to which it should respond */
2129 	u32 afex_scratchpad_addr_to_write[E2_FUNC_MAX];
2130 
2131 	/* generic params from MCP to driver (value depends on the msg sent
2132 	 * to driver
2133 	 */
2134 	u32 afex_param1_to_driver[E2_FUNC_MAX];		/* 0x0088 */
2135 	u32 afex_param2_to_driver[E2_FUNC_MAX];		/* 0x0098 */
2136 
2137 	u32 swim_base_addr;				/* 0x0108 */
2138 	u32 swim_funcs;
2139 	u32 swim_main_cb;
2140 
2141 	/* bitmap notifying which VIF profiles stored in nvram are enabled by
2142 	 * switch
2143 	 */
2144 	u32 afex_profiles_enabled[2];
2145 
2146 	/* generic flags controlled by the driver */
2147 	u32 drv_flags;
2148 	#define DRV_FLAGS_DCB_CONFIGURED		0x0
2149 	#define DRV_FLAGS_DCB_CONFIGURATION_ABORTED	0x1
2150 	#define DRV_FLAGS_DCB_MFW_CONFIGURED	0x2
2151 
2152 	#define DRV_FLAGS_PORT_MASK	((1 << DRV_FLAGS_DCB_CONFIGURED) | \
2153 			(1 << DRV_FLAGS_DCB_CONFIGURATION_ABORTED) | \
2154 			(1 << DRV_FLAGS_DCB_MFW_CONFIGURED))
2155 	/* pointer to extended dev_info shared data copied from nvm image */
2156 	u32 extended_dev_info_shared_addr;
2157 	u32 ncsi_oem_data_addr;
2158 
2159 	u32 ocsd_host_addr; /* initialized by option ROM */
2160 	u32 ocbb_host_addr; /* initialized by option ROM */
2161 	u32 ocsd_req_update_interval; /* initialized by option ROM */
2162 	u32 temperature_in_half_celsius;
2163 	u32 glob_struct_in_host;
2164 
2165 	u32 dcbx_neg_res_ext_offset;
2166 #define SHMEM_DCBX_NEG_RES_EXT_NONE			0x00000000
2167 
2168 	u32 drv_capabilities_flag[E2_FUNC_MAX];
2169 #define DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED 0x00000001
2170 #define DRV_FLAGS_CAPABILITIES_LOADED_L2        0x00000002
2171 #define DRV_FLAGS_CAPABILITIES_LOADED_FCOE      0x00000004
2172 #define DRV_FLAGS_CAPABILITIES_LOADED_ISCSI     0x00000008
2173 
2174 	u32 extended_dev_info_shared_cfg_size;
2175 
2176 	u32 dcbx_en[PORT_MAX];
2177 
2178 	/* The offset points to the multi threaded meta structure */
2179 	u32 multi_thread_data_offset;
2180 
2181 	/* address of DMAable host address holding values from the drivers */
2182 	u32 drv_info_host_addr_lo;
2183 	u32 drv_info_host_addr_hi;
2184 
2185 	/* general values written by the MFW (such as current version) */
2186 	u32 drv_info_control;
2187 #define DRV_INFO_CONTROL_VER_MASK          0x000000ff
2188 #define DRV_INFO_CONTROL_VER_SHIFT         0
2189 #define DRV_INFO_CONTROL_OP_CODE_MASK      0x0000ff00
2190 #define DRV_INFO_CONTROL_OP_CODE_SHIFT     8
2191 	u32 ibft_host_addr; /* initialized by option ROM */
2192 	struct eee_remote_vals eee_remote_vals[PORT_MAX];
2193 	u32 reserved[E2_FUNC_MAX];
2194 
2195 
2196 	/* the status of EEE auto-negotiation
2197 	 * bits 15:0 the configured tx-lpi entry timer value. Depends on bit 31.
2198 	 * bits 19:16 the supported modes for EEE.
2199 	 * bits 23:20 the speeds advertised for EEE.
2200 	 * bits 27:24 the speeds the Link partner advertised for EEE.
2201 	 * The supported/adv. modes in bits 27:19 originate from the
2202 	 * SHMEM_EEE_XXX_ADV definitions (where XXX is replaced by speed).
2203 	 * bit 28 when 1'b1 EEE was requested.
2204 	 * bit 29 when 1'b1 tx lpi was requested.
2205 	 * bit 30 when 1'b1 EEE was negotiated. Tx lpi will be asserted iff
2206 	 * 30:29 are 2'b11.
2207 	 * bit 31 when 1'b0 bits 15:0 contain a PORT_FEAT_CFG_EEE_ define as
2208 	 * value. When 1'b1 those bits contains a value times 16 microseconds.
2209 	 */
2210 	u32 eee_status[PORT_MAX];
2211 	#define SHMEM_EEE_TIMER_MASK		   0x0000ffff
2212 	#define SHMEM_EEE_SUPPORTED_MASK	   0x000f0000
2213 	#define SHMEM_EEE_SUPPORTED_SHIFT	   16
2214 	#define SHMEM_EEE_ADV_STATUS_MASK	   0x00f00000
2215 		#define SHMEM_EEE_100M_ADV	   (1<<0)
2216 		#define SHMEM_EEE_1G_ADV	   (1<<1)
2217 		#define SHMEM_EEE_10G_ADV	   (1<<2)
2218 	#define SHMEM_EEE_ADV_STATUS_SHIFT	   20
2219 	#define	SHMEM_EEE_LP_ADV_STATUS_MASK	   0x0f000000
2220 	#define SHMEM_EEE_LP_ADV_STATUS_SHIFT	   24
2221 	#define SHMEM_EEE_REQUESTED_BIT		   0x10000000
2222 	#define SHMEM_EEE_LPI_REQUESTED_BIT	   0x20000000
2223 	#define SHMEM_EEE_ACTIVE_BIT		   0x40000000
2224 	#define SHMEM_EEE_TIME_OUTPUT_BIT	   0x80000000
2225 
2226 	u32 sizeof_port_stats;
2227 
2228 	/* Link Flap Avoidance */
2229 	u32 lfa_host_addr[PORT_MAX];
2230 	u32 reserved1;
2231 
2232 	u32 reserved2;				/* Offset 0x148 */
2233 	u32 reserved3;				/* Offset 0x14C */
2234 	u32 reserved4;				/* Offset 0x150 */
2235 	u32 link_attr_sync[PORT_MAX];		/* Offset 0x154 */
2236 	#define LINK_ATTR_SYNC_KR2_ENABLE	(1<<0)
2237 
2238 	u32 reserved5[2];
2239 	u32 reserved6[PORT_MAX];
2240 
2241 	/* driver version for each personality */
2242 	struct os_drv_ver func_os_drv_ver[E2_FUNC_MAX]; /* Offset 0x16c */
2243 
2244 	/* Flag to the driver that PF's drv_info_host_addr buffer was read  */
2245 	u32 mfw_drv_indication;
2246 
2247 	/* We use indication for each PF (0..3) */
2248 #define MFW_DRV_IND_READ_DONE_OFFSET(_pf_) (1 << (_pf_))
2249 };
2250 
2251 
2252 struct emac_stats {
2253 	u32     rx_stat_ifhcinoctets;
2254 	u32     rx_stat_ifhcinbadoctets;
2255 	u32     rx_stat_etherstatsfragments;
2256 	u32     rx_stat_ifhcinucastpkts;
2257 	u32     rx_stat_ifhcinmulticastpkts;
2258 	u32     rx_stat_ifhcinbroadcastpkts;
2259 	u32     rx_stat_dot3statsfcserrors;
2260 	u32     rx_stat_dot3statsalignmenterrors;
2261 	u32     rx_stat_dot3statscarriersenseerrors;
2262 	u32     rx_stat_xonpauseframesreceived;
2263 	u32     rx_stat_xoffpauseframesreceived;
2264 	u32     rx_stat_maccontrolframesreceived;
2265 	u32     rx_stat_xoffstateentered;
2266 	u32     rx_stat_dot3statsframestoolong;
2267 	u32     rx_stat_etherstatsjabbers;
2268 	u32     rx_stat_etherstatsundersizepkts;
2269 	u32     rx_stat_etherstatspkts64octets;
2270 	u32     rx_stat_etherstatspkts65octetsto127octets;
2271 	u32     rx_stat_etherstatspkts128octetsto255octets;
2272 	u32     rx_stat_etherstatspkts256octetsto511octets;
2273 	u32     rx_stat_etherstatspkts512octetsto1023octets;
2274 	u32     rx_stat_etherstatspkts1024octetsto1522octets;
2275 	u32     rx_stat_etherstatspktsover1522octets;
2276 
2277 	u32     rx_stat_falsecarriererrors;
2278 
2279 	u32     tx_stat_ifhcoutoctets;
2280 	u32     tx_stat_ifhcoutbadoctets;
2281 	u32     tx_stat_etherstatscollisions;
2282 	u32     tx_stat_outxonsent;
2283 	u32     tx_stat_outxoffsent;
2284 	u32     tx_stat_flowcontroldone;
2285 	u32     tx_stat_dot3statssinglecollisionframes;
2286 	u32     tx_stat_dot3statsmultiplecollisionframes;
2287 	u32     tx_stat_dot3statsdeferredtransmissions;
2288 	u32     tx_stat_dot3statsexcessivecollisions;
2289 	u32     tx_stat_dot3statslatecollisions;
2290 	u32     tx_stat_ifhcoutucastpkts;
2291 	u32     tx_stat_ifhcoutmulticastpkts;
2292 	u32     tx_stat_ifhcoutbroadcastpkts;
2293 	u32     tx_stat_etherstatspkts64octets;
2294 	u32     tx_stat_etherstatspkts65octetsto127octets;
2295 	u32     tx_stat_etherstatspkts128octetsto255octets;
2296 	u32     tx_stat_etherstatspkts256octetsto511octets;
2297 	u32     tx_stat_etherstatspkts512octetsto1023octets;
2298 	u32     tx_stat_etherstatspkts1024octetsto1522octets;
2299 	u32     tx_stat_etherstatspktsover1522octets;
2300 	u32     tx_stat_dot3statsinternalmactransmiterrors;
2301 };
2302 
2303 
2304 struct bmac1_stats {
2305 	u32	tx_stat_gtpkt_lo;
2306 	u32	tx_stat_gtpkt_hi;
2307 	u32	tx_stat_gtxpf_lo;
2308 	u32	tx_stat_gtxpf_hi;
2309 	u32	tx_stat_gtfcs_lo;
2310 	u32	tx_stat_gtfcs_hi;
2311 	u32	tx_stat_gtmca_lo;
2312 	u32	tx_stat_gtmca_hi;
2313 	u32	tx_stat_gtbca_lo;
2314 	u32	tx_stat_gtbca_hi;
2315 	u32	tx_stat_gtfrg_lo;
2316 	u32	tx_stat_gtfrg_hi;
2317 	u32	tx_stat_gtovr_lo;
2318 	u32	tx_stat_gtovr_hi;
2319 	u32	tx_stat_gt64_lo;
2320 	u32	tx_stat_gt64_hi;
2321 	u32	tx_stat_gt127_lo;
2322 	u32	tx_stat_gt127_hi;
2323 	u32	tx_stat_gt255_lo;
2324 	u32	tx_stat_gt255_hi;
2325 	u32	tx_stat_gt511_lo;
2326 	u32	tx_stat_gt511_hi;
2327 	u32	tx_stat_gt1023_lo;
2328 	u32	tx_stat_gt1023_hi;
2329 	u32	tx_stat_gt1518_lo;
2330 	u32	tx_stat_gt1518_hi;
2331 	u32	tx_stat_gt2047_lo;
2332 	u32	tx_stat_gt2047_hi;
2333 	u32	tx_stat_gt4095_lo;
2334 	u32	tx_stat_gt4095_hi;
2335 	u32	tx_stat_gt9216_lo;
2336 	u32	tx_stat_gt9216_hi;
2337 	u32	tx_stat_gt16383_lo;
2338 	u32	tx_stat_gt16383_hi;
2339 	u32	tx_stat_gtmax_lo;
2340 	u32	tx_stat_gtmax_hi;
2341 	u32	tx_stat_gtufl_lo;
2342 	u32	tx_stat_gtufl_hi;
2343 	u32	tx_stat_gterr_lo;
2344 	u32	tx_stat_gterr_hi;
2345 	u32	tx_stat_gtbyt_lo;
2346 	u32	tx_stat_gtbyt_hi;
2347 
2348 	u32	rx_stat_gr64_lo;
2349 	u32	rx_stat_gr64_hi;
2350 	u32	rx_stat_gr127_lo;
2351 	u32	rx_stat_gr127_hi;
2352 	u32	rx_stat_gr255_lo;
2353 	u32	rx_stat_gr255_hi;
2354 	u32	rx_stat_gr511_lo;
2355 	u32	rx_stat_gr511_hi;
2356 	u32	rx_stat_gr1023_lo;
2357 	u32	rx_stat_gr1023_hi;
2358 	u32	rx_stat_gr1518_lo;
2359 	u32	rx_stat_gr1518_hi;
2360 	u32	rx_stat_gr2047_lo;
2361 	u32	rx_stat_gr2047_hi;
2362 	u32	rx_stat_gr4095_lo;
2363 	u32	rx_stat_gr4095_hi;
2364 	u32	rx_stat_gr9216_lo;
2365 	u32	rx_stat_gr9216_hi;
2366 	u32	rx_stat_gr16383_lo;
2367 	u32	rx_stat_gr16383_hi;
2368 	u32	rx_stat_grmax_lo;
2369 	u32	rx_stat_grmax_hi;
2370 	u32	rx_stat_grpkt_lo;
2371 	u32	rx_stat_grpkt_hi;
2372 	u32	rx_stat_grfcs_lo;
2373 	u32	rx_stat_grfcs_hi;
2374 	u32	rx_stat_grmca_lo;
2375 	u32	rx_stat_grmca_hi;
2376 	u32	rx_stat_grbca_lo;
2377 	u32	rx_stat_grbca_hi;
2378 	u32	rx_stat_grxcf_lo;
2379 	u32	rx_stat_grxcf_hi;
2380 	u32	rx_stat_grxpf_lo;
2381 	u32	rx_stat_grxpf_hi;
2382 	u32	rx_stat_grxuo_lo;
2383 	u32	rx_stat_grxuo_hi;
2384 	u32	rx_stat_grjbr_lo;
2385 	u32	rx_stat_grjbr_hi;
2386 	u32	rx_stat_grovr_lo;
2387 	u32	rx_stat_grovr_hi;
2388 	u32	rx_stat_grflr_lo;
2389 	u32	rx_stat_grflr_hi;
2390 	u32	rx_stat_grmeg_lo;
2391 	u32	rx_stat_grmeg_hi;
2392 	u32	rx_stat_grmeb_lo;
2393 	u32	rx_stat_grmeb_hi;
2394 	u32	rx_stat_grbyt_lo;
2395 	u32	rx_stat_grbyt_hi;
2396 	u32	rx_stat_grund_lo;
2397 	u32	rx_stat_grund_hi;
2398 	u32	rx_stat_grfrg_lo;
2399 	u32	rx_stat_grfrg_hi;
2400 	u32	rx_stat_grerb_lo;
2401 	u32	rx_stat_grerb_hi;
2402 	u32	rx_stat_grfre_lo;
2403 	u32	rx_stat_grfre_hi;
2404 	u32	rx_stat_gripj_lo;
2405 	u32	rx_stat_gripj_hi;
2406 };
2407 
2408 struct bmac2_stats {
2409 	u32	tx_stat_gtpk_lo; /* gtpok */
2410 	u32	tx_stat_gtpk_hi; /* gtpok */
2411 	u32	tx_stat_gtxpf_lo; /* gtpf */
2412 	u32	tx_stat_gtxpf_hi; /* gtpf */
2413 	u32	tx_stat_gtpp_lo; /* NEW BMAC2 */
2414 	u32	tx_stat_gtpp_hi; /* NEW BMAC2 */
2415 	u32	tx_stat_gtfcs_lo;
2416 	u32	tx_stat_gtfcs_hi;
2417 	u32	tx_stat_gtuca_lo; /* NEW BMAC2 */
2418 	u32	tx_stat_gtuca_hi; /* NEW BMAC2 */
2419 	u32	tx_stat_gtmca_lo;
2420 	u32	tx_stat_gtmca_hi;
2421 	u32	tx_stat_gtbca_lo;
2422 	u32	tx_stat_gtbca_hi;
2423 	u32	tx_stat_gtovr_lo;
2424 	u32	tx_stat_gtovr_hi;
2425 	u32	tx_stat_gtfrg_lo;
2426 	u32	tx_stat_gtfrg_hi;
2427 	u32	tx_stat_gtpkt1_lo; /* gtpkt */
2428 	u32	tx_stat_gtpkt1_hi; /* gtpkt */
2429 	u32	tx_stat_gt64_lo;
2430 	u32	tx_stat_gt64_hi;
2431 	u32	tx_stat_gt127_lo;
2432 	u32	tx_stat_gt127_hi;
2433 	u32	tx_stat_gt255_lo;
2434 	u32	tx_stat_gt255_hi;
2435 	u32	tx_stat_gt511_lo;
2436 	u32	tx_stat_gt511_hi;
2437 	u32	tx_stat_gt1023_lo;
2438 	u32	tx_stat_gt1023_hi;
2439 	u32	tx_stat_gt1518_lo;
2440 	u32	tx_stat_gt1518_hi;
2441 	u32	tx_stat_gt2047_lo;
2442 	u32	tx_stat_gt2047_hi;
2443 	u32	tx_stat_gt4095_lo;
2444 	u32	tx_stat_gt4095_hi;
2445 	u32	tx_stat_gt9216_lo;
2446 	u32	tx_stat_gt9216_hi;
2447 	u32	tx_stat_gt16383_lo;
2448 	u32	tx_stat_gt16383_hi;
2449 	u32	tx_stat_gtmax_lo;
2450 	u32	tx_stat_gtmax_hi;
2451 	u32	tx_stat_gtufl_lo;
2452 	u32	tx_stat_gtufl_hi;
2453 	u32	tx_stat_gterr_lo;
2454 	u32	tx_stat_gterr_hi;
2455 	u32	tx_stat_gtbyt_lo;
2456 	u32	tx_stat_gtbyt_hi;
2457 
2458 	u32	rx_stat_gr64_lo;
2459 	u32	rx_stat_gr64_hi;
2460 	u32	rx_stat_gr127_lo;
2461 	u32	rx_stat_gr127_hi;
2462 	u32	rx_stat_gr255_lo;
2463 	u32	rx_stat_gr255_hi;
2464 	u32	rx_stat_gr511_lo;
2465 	u32	rx_stat_gr511_hi;
2466 	u32	rx_stat_gr1023_lo;
2467 	u32	rx_stat_gr1023_hi;
2468 	u32	rx_stat_gr1518_lo;
2469 	u32	rx_stat_gr1518_hi;
2470 	u32	rx_stat_gr2047_lo;
2471 	u32	rx_stat_gr2047_hi;
2472 	u32	rx_stat_gr4095_lo;
2473 	u32	rx_stat_gr4095_hi;
2474 	u32	rx_stat_gr9216_lo;
2475 	u32	rx_stat_gr9216_hi;
2476 	u32	rx_stat_gr16383_lo;
2477 	u32	rx_stat_gr16383_hi;
2478 	u32	rx_stat_grmax_lo;
2479 	u32	rx_stat_grmax_hi;
2480 	u32	rx_stat_grpkt_lo;
2481 	u32	rx_stat_grpkt_hi;
2482 	u32	rx_stat_grfcs_lo;
2483 	u32	rx_stat_grfcs_hi;
2484 	u32	rx_stat_gruca_lo;
2485 	u32	rx_stat_gruca_hi;
2486 	u32	rx_stat_grmca_lo;
2487 	u32	rx_stat_grmca_hi;
2488 	u32	rx_stat_grbca_lo;
2489 	u32	rx_stat_grbca_hi;
2490 	u32	rx_stat_grxpf_lo; /* grpf */
2491 	u32	rx_stat_grxpf_hi; /* grpf */
2492 	u32	rx_stat_grpp_lo;
2493 	u32	rx_stat_grpp_hi;
2494 	u32	rx_stat_grxuo_lo; /* gruo */
2495 	u32	rx_stat_grxuo_hi; /* gruo */
2496 	u32	rx_stat_grjbr_lo;
2497 	u32	rx_stat_grjbr_hi;
2498 	u32	rx_stat_grovr_lo;
2499 	u32	rx_stat_grovr_hi;
2500 	u32	rx_stat_grxcf_lo; /* grcf */
2501 	u32	rx_stat_grxcf_hi; /* grcf */
2502 	u32	rx_stat_grflr_lo;
2503 	u32	rx_stat_grflr_hi;
2504 	u32	rx_stat_grpok_lo;
2505 	u32	rx_stat_grpok_hi;
2506 	u32	rx_stat_grmeg_lo;
2507 	u32	rx_stat_grmeg_hi;
2508 	u32	rx_stat_grmeb_lo;
2509 	u32	rx_stat_grmeb_hi;
2510 	u32	rx_stat_grbyt_lo;
2511 	u32	rx_stat_grbyt_hi;
2512 	u32	rx_stat_grund_lo;
2513 	u32	rx_stat_grund_hi;
2514 	u32	rx_stat_grfrg_lo;
2515 	u32	rx_stat_grfrg_hi;
2516 	u32	rx_stat_grerb_lo; /* grerrbyt */
2517 	u32	rx_stat_grerb_hi; /* grerrbyt */
2518 	u32	rx_stat_grfre_lo; /* grfrerr */
2519 	u32	rx_stat_grfre_hi; /* grfrerr */
2520 	u32	rx_stat_gripj_lo;
2521 	u32	rx_stat_gripj_hi;
2522 };
2523 
2524 struct mstat_stats {
2525 	struct {
2526 		/* OTE MSTAT on E3 has a bug where this register's contents are
2527 		 * actually tx_gtxpok + tx_gtxpf + (possibly)tx_gtxpp
2528 		 */
2529 		u32 tx_gtxpok_lo;
2530 		u32 tx_gtxpok_hi;
2531 		u32 tx_gtxpf_lo;
2532 		u32 tx_gtxpf_hi;
2533 		u32 tx_gtxpp_lo;
2534 		u32 tx_gtxpp_hi;
2535 		u32 tx_gtfcs_lo;
2536 		u32 tx_gtfcs_hi;
2537 		u32 tx_gtuca_lo;
2538 		u32 tx_gtuca_hi;
2539 		u32 tx_gtmca_lo;
2540 		u32 tx_gtmca_hi;
2541 		u32 tx_gtgca_lo;
2542 		u32 tx_gtgca_hi;
2543 		u32 tx_gtpkt_lo;
2544 		u32 tx_gtpkt_hi;
2545 		u32 tx_gt64_lo;
2546 		u32 tx_gt64_hi;
2547 		u32 tx_gt127_lo;
2548 		u32 tx_gt127_hi;
2549 		u32 tx_gt255_lo;
2550 		u32 tx_gt255_hi;
2551 		u32 tx_gt511_lo;
2552 		u32 tx_gt511_hi;
2553 		u32 tx_gt1023_lo;
2554 		u32 tx_gt1023_hi;
2555 		u32 tx_gt1518_lo;
2556 		u32 tx_gt1518_hi;
2557 		u32 tx_gt2047_lo;
2558 		u32 tx_gt2047_hi;
2559 		u32 tx_gt4095_lo;
2560 		u32 tx_gt4095_hi;
2561 		u32 tx_gt9216_lo;
2562 		u32 tx_gt9216_hi;
2563 		u32 tx_gt16383_lo;
2564 		u32 tx_gt16383_hi;
2565 		u32 tx_gtufl_lo;
2566 		u32 tx_gtufl_hi;
2567 		u32 tx_gterr_lo;
2568 		u32 tx_gterr_hi;
2569 		u32 tx_gtbyt_lo;
2570 		u32 tx_gtbyt_hi;
2571 		u32 tx_collisions_lo;
2572 		u32 tx_collisions_hi;
2573 		u32 tx_singlecollision_lo;
2574 		u32 tx_singlecollision_hi;
2575 		u32 tx_multiplecollisions_lo;
2576 		u32 tx_multiplecollisions_hi;
2577 		u32 tx_deferred_lo;
2578 		u32 tx_deferred_hi;
2579 		u32 tx_excessivecollisions_lo;
2580 		u32 tx_excessivecollisions_hi;
2581 		u32 tx_latecollisions_lo;
2582 		u32 tx_latecollisions_hi;
2583 	} stats_tx;
2584 
2585 	struct {
2586 		u32 rx_gr64_lo;
2587 		u32 rx_gr64_hi;
2588 		u32 rx_gr127_lo;
2589 		u32 rx_gr127_hi;
2590 		u32 rx_gr255_lo;
2591 		u32 rx_gr255_hi;
2592 		u32 rx_gr511_lo;
2593 		u32 rx_gr511_hi;
2594 		u32 rx_gr1023_lo;
2595 		u32 rx_gr1023_hi;
2596 		u32 rx_gr1518_lo;
2597 		u32 rx_gr1518_hi;
2598 		u32 rx_gr2047_lo;
2599 		u32 rx_gr2047_hi;
2600 		u32 rx_gr4095_lo;
2601 		u32 rx_gr4095_hi;
2602 		u32 rx_gr9216_lo;
2603 		u32 rx_gr9216_hi;
2604 		u32 rx_gr16383_lo;
2605 		u32 rx_gr16383_hi;
2606 		u32 rx_grpkt_lo;
2607 		u32 rx_grpkt_hi;
2608 		u32 rx_grfcs_lo;
2609 		u32 rx_grfcs_hi;
2610 		u32 rx_gruca_lo;
2611 		u32 rx_gruca_hi;
2612 		u32 rx_grmca_lo;
2613 		u32 rx_grmca_hi;
2614 		u32 rx_grbca_lo;
2615 		u32 rx_grbca_hi;
2616 		u32 rx_grxpf_lo;
2617 		u32 rx_grxpf_hi;
2618 		u32 rx_grxpp_lo;
2619 		u32 rx_grxpp_hi;
2620 		u32 rx_grxuo_lo;
2621 		u32 rx_grxuo_hi;
2622 		u32 rx_grovr_lo;
2623 		u32 rx_grovr_hi;
2624 		u32 rx_grxcf_lo;
2625 		u32 rx_grxcf_hi;
2626 		u32 rx_grflr_lo;
2627 		u32 rx_grflr_hi;
2628 		u32 rx_grpok_lo;
2629 		u32 rx_grpok_hi;
2630 		u32 rx_grbyt_lo;
2631 		u32 rx_grbyt_hi;
2632 		u32 rx_grund_lo;
2633 		u32 rx_grund_hi;
2634 		u32 rx_grfrg_lo;
2635 		u32 rx_grfrg_hi;
2636 		u32 rx_grerb_lo;
2637 		u32 rx_grerb_hi;
2638 		u32 rx_grfre_lo;
2639 		u32 rx_grfre_hi;
2640 
2641 		u32 rx_alignmenterrors_lo;
2642 		u32 rx_alignmenterrors_hi;
2643 		u32 rx_falsecarrier_lo;
2644 		u32 rx_falsecarrier_hi;
2645 		u32 rx_llfcmsgcnt_lo;
2646 		u32 rx_llfcmsgcnt_hi;
2647 	} stats_rx;
2648 };
2649 
2650 union mac_stats {
2651 	struct emac_stats	emac_stats;
2652 	struct bmac1_stats	bmac1_stats;
2653 	struct bmac2_stats	bmac2_stats;
2654 	struct mstat_stats	mstat_stats;
2655 };
2656 
2657 
2658 struct mac_stx {
2659 	/* in_bad_octets */
2660 	u32     rx_stat_ifhcinbadoctets_hi;
2661 	u32     rx_stat_ifhcinbadoctets_lo;
2662 
2663 	/* out_bad_octets */
2664 	u32     tx_stat_ifhcoutbadoctets_hi;
2665 	u32     tx_stat_ifhcoutbadoctets_lo;
2666 
2667 	/* crc_receive_errors */
2668 	u32     rx_stat_dot3statsfcserrors_hi;
2669 	u32     rx_stat_dot3statsfcserrors_lo;
2670 	/* alignment_errors */
2671 	u32     rx_stat_dot3statsalignmenterrors_hi;
2672 	u32     rx_stat_dot3statsalignmenterrors_lo;
2673 	/* carrier_sense_errors */
2674 	u32     rx_stat_dot3statscarriersenseerrors_hi;
2675 	u32     rx_stat_dot3statscarriersenseerrors_lo;
2676 	/* false_carrier_detections */
2677 	u32     rx_stat_falsecarriererrors_hi;
2678 	u32     rx_stat_falsecarriererrors_lo;
2679 
2680 	/* runt_packets_received */
2681 	u32     rx_stat_etherstatsundersizepkts_hi;
2682 	u32     rx_stat_etherstatsundersizepkts_lo;
2683 	/* jabber_packets_received */
2684 	u32     rx_stat_dot3statsframestoolong_hi;
2685 	u32     rx_stat_dot3statsframestoolong_lo;
2686 
2687 	/* error_runt_packets_received */
2688 	u32     rx_stat_etherstatsfragments_hi;
2689 	u32     rx_stat_etherstatsfragments_lo;
2690 	/* error_jabber_packets_received */
2691 	u32     rx_stat_etherstatsjabbers_hi;
2692 	u32     rx_stat_etherstatsjabbers_lo;
2693 
2694 	/* control_frames_received */
2695 	u32     rx_stat_maccontrolframesreceived_hi;
2696 	u32     rx_stat_maccontrolframesreceived_lo;
2697 	u32     rx_stat_mac_xpf_hi;
2698 	u32     rx_stat_mac_xpf_lo;
2699 	u32     rx_stat_mac_xcf_hi;
2700 	u32     rx_stat_mac_xcf_lo;
2701 
2702 	/* xoff_state_entered */
2703 	u32     rx_stat_xoffstateentered_hi;
2704 	u32     rx_stat_xoffstateentered_lo;
2705 	/* pause_xon_frames_received */
2706 	u32     rx_stat_xonpauseframesreceived_hi;
2707 	u32     rx_stat_xonpauseframesreceived_lo;
2708 	/* pause_xoff_frames_received */
2709 	u32     rx_stat_xoffpauseframesreceived_hi;
2710 	u32     rx_stat_xoffpauseframesreceived_lo;
2711 	/* pause_xon_frames_transmitted */
2712 	u32     tx_stat_outxonsent_hi;
2713 	u32     tx_stat_outxonsent_lo;
2714 	/* pause_xoff_frames_transmitted */
2715 	u32     tx_stat_outxoffsent_hi;
2716 	u32     tx_stat_outxoffsent_lo;
2717 	/* flow_control_done */
2718 	u32     tx_stat_flowcontroldone_hi;
2719 	u32     tx_stat_flowcontroldone_lo;
2720 
2721 	/* ether_stats_collisions */
2722 	u32     tx_stat_etherstatscollisions_hi;
2723 	u32     tx_stat_etherstatscollisions_lo;
2724 	/* single_collision_transmit_frames */
2725 	u32     tx_stat_dot3statssinglecollisionframes_hi;
2726 	u32     tx_stat_dot3statssinglecollisionframes_lo;
2727 	/* multiple_collision_transmit_frames */
2728 	u32     tx_stat_dot3statsmultiplecollisionframes_hi;
2729 	u32     tx_stat_dot3statsmultiplecollisionframes_lo;
2730 	/* deferred_transmissions */
2731 	u32     tx_stat_dot3statsdeferredtransmissions_hi;
2732 	u32     tx_stat_dot3statsdeferredtransmissions_lo;
2733 	/* excessive_collision_frames */
2734 	u32     tx_stat_dot3statsexcessivecollisions_hi;
2735 	u32     tx_stat_dot3statsexcessivecollisions_lo;
2736 	/* late_collision_frames */
2737 	u32     tx_stat_dot3statslatecollisions_hi;
2738 	u32     tx_stat_dot3statslatecollisions_lo;
2739 
2740 	/* frames_transmitted_64_bytes */
2741 	u32     tx_stat_etherstatspkts64octets_hi;
2742 	u32     tx_stat_etherstatspkts64octets_lo;
2743 	/* frames_transmitted_65_127_bytes */
2744 	u32     tx_stat_etherstatspkts65octetsto127octets_hi;
2745 	u32     tx_stat_etherstatspkts65octetsto127octets_lo;
2746 	/* frames_transmitted_128_255_bytes */
2747 	u32     tx_stat_etherstatspkts128octetsto255octets_hi;
2748 	u32     tx_stat_etherstatspkts128octetsto255octets_lo;
2749 	/* frames_transmitted_256_511_bytes */
2750 	u32     tx_stat_etherstatspkts256octetsto511octets_hi;
2751 	u32     tx_stat_etherstatspkts256octetsto511octets_lo;
2752 	/* frames_transmitted_512_1023_bytes */
2753 	u32     tx_stat_etherstatspkts512octetsto1023octets_hi;
2754 	u32     tx_stat_etherstatspkts512octetsto1023octets_lo;
2755 	/* frames_transmitted_1024_1522_bytes */
2756 	u32     tx_stat_etherstatspkts1024octetsto1522octets_hi;
2757 	u32     tx_stat_etherstatspkts1024octetsto1522octets_lo;
2758 	/* frames_transmitted_1523_9022_bytes */
2759 	u32     tx_stat_etherstatspktsover1522octets_hi;
2760 	u32     tx_stat_etherstatspktsover1522octets_lo;
2761 	u32     tx_stat_mac_2047_hi;
2762 	u32     tx_stat_mac_2047_lo;
2763 	u32     tx_stat_mac_4095_hi;
2764 	u32     tx_stat_mac_4095_lo;
2765 	u32     tx_stat_mac_9216_hi;
2766 	u32     tx_stat_mac_9216_lo;
2767 	u32     tx_stat_mac_16383_hi;
2768 	u32     tx_stat_mac_16383_lo;
2769 
2770 	/* internal_mac_transmit_errors */
2771 	u32     tx_stat_dot3statsinternalmactransmiterrors_hi;
2772 	u32     tx_stat_dot3statsinternalmactransmiterrors_lo;
2773 
2774 	/* if_out_discards */
2775 	u32     tx_stat_mac_ufl_hi;
2776 	u32     tx_stat_mac_ufl_lo;
2777 };
2778 
2779 
2780 #define MAC_STX_IDX_MAX                     2
2781 
2782 struct host_port_stats {
2783 	u32            host_port_stats_counter;
2784 
2785 	struct mac_stx mac_stx[MAC_STX_IDX_MAX];
2786 
2787 	u32            brb_drop_hi;
2788 	u32            brb_drop_lo;
2789 
2790 	u32            not_used; /* obsolete */
2791 	u32            pfc_frames_tx_hi;
2792 	u32            pfc_frames_tx_lo;
2793 	u32            pfc_frames_rx_hi;
2794 	u32            pfc_frames_rx_lo;
2795 
2796 	u32            eee_lpi_count_hi;
2797 	u32            eee_lpi_count_lo;
2798 };
2799 
2800 
2801 struct host_func_stats {
2802 	u32     host_func_stats_start;
2803 
2804 	u32     total_bytes_received_hi;
2805 	u32     total_bytes_received_lo;
2806 
2807 	u32     total_bytes_transmitted_hi;
2808 	u32     total_bytes_transmitted_lo;
2809 
2810 	u32     total_unicast_packets_received_hi;
2811 	u32     total_unicast_packets_received_lo;
2812 
2813 	u32     total_multicast_packets_received_hi;
2814 	u32     total_multicast_packets_received_lo;
2815 
2816 	u32     total_broadcast_packets_received_hi;
2817 	u32     total_broadcast_packets_received_lo;
2818 
2819 	u32     total_unicast_packets_transmitted_hi;
2820 	u32     total_unicast_packets_transmitted_lo;
2821 
2822 	u32     total_multicast_packets_transmitted_hi;
2823 	u32     total_multicast_packets_transmitted_lo;
2824 
2825 	u32     total_broadcast_packets_transmitted_hi;
2826 	u32     total_broadcast_packets_transmitted_lo;
2827 
2828 	u32     valid_bytes_received_hi;
2829 	u32     valid_bytes_received_lo;
2830 
2831 	u32     host_func_stats_end;
2832 };
2833 
2834 /* VIC definitions */
2835 #define VICSTATST_UIF_INDEX 2
2836 
2837 
2838 /* stats collected for afex.
2839  * NOTE: structure is exactly as expected to be received by the switch.
2840  *       order must remain exactly as is unless protocol changes !
2841  */
2842 struct afex_stats {
2843 	u32 tx_unicast_frames_hi;
2844 	u32 tx_unicast_frames_lo;
2845 	u32 tx_unicast_bytes_hi;
2846 	u32 tx_unicast_bytes_lo;
2847 	u32 tx_multicast_frames_hi;
2848 	u32 tx_multicast_frames_lo;
2849 	u32 tx_multicast_bytes_hi;
2850 	u32 tx_multicast_bytes_lo;
2851 	u32 tx_broadcast_frames_hi;
2852 	u32 tx_broadcast_frames_lo;
2853 	u32 tx_broadcast_bytes_hi;
2854 	u32 tx_broadcast_bytes_lo;
2855 	u32 tx_frames_discarded_hi;
2856 	u32 tx_frames_discarded_lo;
2857 	u32 tx_frames_dropped_hi;
2858 	u32 tx_frames_dropped_lo;
2859 
2860 	u32 rx_unicast_frames_hi;
2861 	u32 rx_unicast_frames_lo;
2862 	u32 rx_unicast_bytes_hi;
2863 	u32 rx_unicast_bytes_lo;
2864 	u32 rx_multicast_frames_hi;
2865 	u32 rx_multicast_frames_lo;
2866 	u32 rx_multicast_bytes_hi;
2867 	u32 rx_multicast_bytes_lo;
2868 	u32 rx_broadcast_frames_hi;
2869 	u32 rx_broadcast_frames_lo;
2870 	u32 rx_broadcast_bytes_hi;
2871 	u32 rx_broadcast_bytes_lo;
2872 	u32 rx_frames_discarded_hi;
2873 	u32 rx_frames_discarded_lo;
2874 	u32 rx_frames_dropped_hi;
2875 	u32 rx_frames_dropped_lo;
2876 };
2877 
2878 #define BCM_5710_FW_MAJOR_VERSION			7
2879 #define BCM_5710_FW_MINOR_VERSION			8
2880 #define BCM_5710_FW_REVISION_VERSION		19
2881 #define BCM_5710_FW_ENGINEERING_VERSION		0
2882 #define BCM_5710_FW_COMPILE_FLAGS			1
2883 
2884 
2885 /*
2886  * attention bits
2887  */
2888 struct atten_sp_status_block {
2889 	__le32 attn_bits;
2890 	__le32 attn_bits_ack;
2891 	u8 status_block_id;
2892 	u8 reserved0;
2893 	__le16 attn_bits_index;
2894 	__le32 reserved1;
2895 };
2896 
2897 
2898 /*
2899  * The eth aggregative context of Cstorm
2900  */
2901 struct cstorm_eth_ag_context {
2902 	u32 __reserved0[10];
2903 };
2904 
2905 
2906 /*
2907  * dmae command structure
2908  */
2909 struct dmae_command {
2910 	u32 opcode;
2911 #define DMAE_COMMAND_SRC (0x1<<0)
2912 #define DMAE_COMMAND_SRC_SHIFT 0
2913 #define DMAE_COMMAND_DST (0x3<<1)
2914 #define DMAE_COMMAND_DST_SHIFT 1
2915 #define DMAE_COMMAND_C_DST (0x1<<3)
2916 #define DMAE_COMMAND_C_DST_SHIFT 3
2917 #define DMAE_COMMAND_C_TYPE_ENABLE (0x1<<4)
2918 #define DMAE_COMMAND_C_TYPE_ENABLE_SHIFT 4
2919 #define DMAE_COMMAND_C_TYPE_CRC_ENABLE (0x1<<5)
2920 #define DMAE_COMMAND_C_TYPE_CRC_ENABLE_SHIFT 5
2921 #define DMAE_COMMAND_C_TYPE_CRC_OFFSET (0x7<<6)
2922 #define DMAE_COMMAND_C_TYPE_CRC_OFFSET_SHIFT 6
2923 #define DMAE_COMMAND_ENDIANITY (0x3<<9)
2924 #define DMAE_COMMAND_ENDIANITY_SHIFT 9
2925 #define DMAE_COMMAND_PORT (0x1<<11)
2926 #define DMAE_COMMAND_PORT_SHIFT 11
2927 #define DMAE_COMMAND_CRC_RESET (0x1<<12)
2928 #define DMAE_COMMAND_CRC_RESET_SHIFT 12
2929 #define DMAE_COMMAND_SRC_RESET (0x1<<13)
2930 #define DMAE_COMMAND_SRC_RESET_SHIFT 13
2931 #define DMAE_COMMAND_DST_RESET (0x1<<14)
2932 #define DMAE_COMMAND_DST_RESET_SHIFT 14
2933 #define DMAE_COMMAND_E1HVN (0x3<<15)
2934 #define DMAE_COMMAND_E1HVN_SHIFT 15
2935 #define DMAE_COMMAND_DST_VN (0x3<<17)
2936 #define DMAE_COMMAND_DST_VN_SHIFT 17
2937 #define DMAE_COMMAND_C_FUNC (0x1<<19)
2938 #define DMAE_COMMAND_C_FUNC_SHIFT 19
2939 #define DMAE_COMMAND_ERR_POLICY (0x3<<20)
2940 #define DMAE_COMMAND_ERR_POLICY_SHIFT 20
2941 #define DMAE_COMMAND_RESERVED0 (0x3FF<<22)
2942 #define DMAE_COMMAND_RESERVED0_SHIFT 22
2943 	u32 src_addr_lo;
2944 	u32 src_addr_hi;
2945 	u32 dst_addr_lo;
2946 	u32 dst_addr_hi;
2947 #if defined(__BIG_ENDIAN)
2948 	u16 opcode_iov;
2949 #define DMAE_COMMAND_SRC_VFID (0x3F<<0)
2950 #define DMAE_COMMAND_SRC_VFID_SHIFT 0
2951 #define DMAE_COMMAND_SRC_VFPF (0x1<<6)
2952 #define DMAE_COMMAND_SRC_VFPF_SHIFT 6
2953 #define DMAE_COMMAND_RESERVED1 (0x1<<7)
2954 #define DMAE_COMMAND_RESERVED1_SHIFT 7
2955 #define DMAE_COMMAND_DST_VFID (0x3F<<8)
2956 #define DMAE_COMMAND_DST_VFID_SHIFT 8
2957 #define DMAE_COMMAND_DST_VFPF (0x1<<14)
2958 #define DMAE_COMMAND_DST_VFPF_SHIFT 14
2959 #define DMAE_COMMAND_RESERVED2 (0x1<<15)
2960 #define DMAE_COMMAND_RESERVED2_SHIFT 15
2961 	u16 len;
2962 #elif defined(__LITTLE_ENDIAN)
2963 	u16 len;
2964 	u16 opcode_iov;
2965 #define DMAE_COMMAND_SRC_VFID (0x3F<<0)
2966 #define DMAE_COMMAND_SRC_VFID_SHIFT 0
2967 #define DMAE_COMMAND_SRC_VFPF (0x1<<6)
2968 #define DMAE_COMMAND_SRC_VFPF_SHIFT 6
2969 #define DMAE_COMMAND_RESERVED1 (0x1<<7)
2970 #define DMAE_COMMAND_RESERVED1_SHIFT 7
2971 #define DMAE_COMMAND_DST_VFID (0x3F<<8)
2972 #define DMAE_COMMAND_DST_VFID_SHIFT 8
2973 #define DMAE_COMMAND_DST_VFPF (0x1<<14)
2974 #define DMAE_COMMAND_DST_VFPF_SHIFT 14
2975 #define DMAE_COMMAND_RESERVED2 (0x1<<15)
2976 #define DMAE_COMMAND_RESERVED2_SHIFT 15
2977 #endif
2978 	u32 comp_addr_lo;
2979 	u32 comp_addr_hi;
2980 	u32 comp_val;
2981 	u32 crc32;
2982 	u32 crc32_c;
2983 #if defined(__BIG_ENDIAN)
2984 	u16 crc16_c;
2985 	u16 crc16;
2986 #elif defined(__LITTLE_ENDIAN)
2987 	u16 crc16;
2988 	u16 crc16_c;
2989 #endif
2990 #if defined(__BIG_ENDIAN)
2991 	u16 reserved3;
2992 	u16 crc_t10;
2993 #elif defined(__LITTLE_ENDIAN)
2994 	u16 crc_t10;
2995 	u16 reserved3;
2996 #endif
2997 #if defined(__BIG_ENDIAN)
2998 	u16 xsum8;
2999 	u16 xsum16;
3000 #elif defined(__LITTLE_ENDIAN)
3001 	u16 xsum16;
3002 	u16 xsum8;
3003 #endif
3004 };
3005 
3006 
3007 /*
3008  * common data for all protocols
3009  */
3010 struct doorbell_hdr {
3011 	u8 header;
3012 #define DOORBELL_HDR_RX (0x1<<0)
3013 #define DOORBELL_HDR_RX_SHIFT 0
3014 #define DOORBELL_HDR_DB_TYPE (0x1<<1)
3015 #define DOORBELL_HDR_DB_TYPE_SHIFT 1
3016 #define DOORBELL_HDR_DPM_SIZE (0x3<<2)
3017 #define DOORBELL_HDR_DPM_SIZE_SHIFT 2
3018 #define DOORBELL_HDR_CONN_TYPE (0xF<<4)
3019 #define DOORBELL_HDR_CONN_TYPE_SHIFT 4
3020 };
3021 
3022 /*
3023  * Ethernet doorbell
3024  */
3025 struct eth_tx_doorbell {
3026 #if defined(__BIG_ENDIAN)
3027 	u16 npackets;
3028 	u8 params;
3029 #define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0)
3030 #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0
3031 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6)
3032 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6
3033 #define ETH_TX_DOORBELL_SPARE (0x1<<7)
3034 #define ETH_TX_DOORBELL_SPARE_SHIFT 7
3035 	struct doorbell_hdr hdr;
3036 #elif defined(__LITTLE_ENDIAN)
3037 	struct doorbell_hdr hdr;
3038 	u8 params;
3039 #define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0)
3040 #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0
3041 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6)
3042 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6
3043 #define ETH_TX_DOORBELL_SPARE (0x1<<7)
3044 #define ETH_TX_DOORBELL_SPARE_SHIFT 7
3045 	u16 npackets;
3046 #endif
3047 };
3048 
3049 
3050 /*
3051  * 3 lines. status block
3052  */
3053 struct hc_status_block_e1x {
3054 	__le16 index_values[HC_SB_MAX_INDICES_E1X];
3055 	__le16 running_index[HC_SB_MAX_SM];
3056 	__le32 rsrv[11];
3057 };
3058 
3059 /*
3060  * host status block
3061  */
3062 struct host_hc_status_block_e1x {
3063 	struct hc_status_block_e1x sb;
3064 };
3065 
3066 
3067 /*
3068  * 3 lines. status block
3069  */
3070 struct hc_status_block_e2 {
3071 	__le16 index_values[HC_SB_MAX_INDICES_E2];
3072 	__le16 running_index[HC_SB_MAX_SM];
3073 	__le32 reserved[11];
3074 };
3075 
3076 /*
3077  * host status block
3078  */
3079 struct host_hc_status_block_e2 {
3080 	struct hc_status_block_e2 sb;
3081 };
3082 
3083 
3084 /*
3085  * 5 lines. slow-path status block
3086  */
3087 struct hc_sp_status_block {
3088 	__le16 index_values[HC_SP_SB_MAX_INDICES];
3089 	__le16 running_index;
3090 	__le16 rsrv;
3091 	u32 rsrv1;
3092 };
3093 
3094 /*
3095  * host status block
3096  */
3097 struct host_sp_status_block {
3098 	struct atten_sp_status_block atten_status_block;
3099 	struct hc_sp_status_block sp_sb;
3100 };
3101 
3102 
3103 /*
3104  * IGU driver acknowledgment register
3105  */
3106 struct igu_ack_register {
3107 #if defined(__BIG_ENDIAN)
3108 	u16 sb_id_and_flags;
3109 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0)
3110 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0
3111 #define IGU_ACK_REGISTER_STORM_ID (0x7<<5)
3112 #define IGU_ACK_REGISTER_STORM_ID_SHIFT 5
3113 #define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8)
3114 #define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8
3115 #define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9)
3116 #define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9
3117 #define IGU_ACK_REGISTER_RESERVED (0x1F<<11)
3118 #define IGU_ACK_REGISTER_RESERVED_SHIFT 11
3119 	u16 status_block_index;
3120 #elif defined(__LITTLE_ENDIAN)
3121 	u16 status_block_index;
3122 	u16 sb_id_and_flags;
3123 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0)
3124 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0
3125 #define IGU_ACK_REGISTER_STORM_ID (0x7<<5)
3126 #define IGU_ACK_REGISTER_STORM_ID_SHIFT 5
3127 #define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8)
3128 #define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8
3129 #define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9)
3130 #define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9
3131 #define IGU_ACK_REGISTER_RESERVED (0x1F<<11)
3132 #define IGU_ACK_REGISTER_RESERVED_SHIFT 11
3133 #endif
3134 };
3135 
3136 
3137 /*
3138  * IGU driver acknowledgement register
3139  */
3140 struct igu_backward_compatible {
3141 	u32 sb_id_and_flags;
3142 #define IGU_BACKWARD_COMPATIBLE_SB_INDEX (0xFFFF<<0)
3143 #define IGU_BACKWARD_COMPATIBLE_SB_INDEX_SHIFT 0
3144 #define IGU_BACKWARD_COMPATIBLE_SB_SELECT (0x1F<<16)
3145 #define IGU_BACKWARD_COMPATIBLE_SB_SELECT_SHIFT 16
3146 #define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS (0x7<<21)
3147 #define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS_SHIFT 21
3148 #define IGU_BACKWARD_COMPATIBLE_BUPDATE (0x1<<24)
3149 #define IGU_BACKWARD_COMPATIBLE_BUPDATE_SHIFT 24
3150 #define IGU_BACKWARD_COMPATIBLE_ENABLE_INT (0x3<<25)
3151 #define IGU_BACKWARD_COMPATIBLE_ENABLE_INT_SHIFT 25
3152 #define IGU_BACKWARD_COMPATIBLE_RESERVED_0 (0x1F<<27)
3153 #define IGU_BACKWARD_COMPATIBLE_RESERVED_0_SHIFT 27
3154 	u32 reserved_2;
3155 };
3156 
3157 
3158 /*
3159  * IGU driver acknowledgement register
3160  */
3161 struct igu_regular {
3162 	u32 sb_id_and_flags;
3163 #define IGU_REGULAR_SB_INDEX (0xFFFFF<<0)
3164 #define IGU_REGULAR_SB_INDEX_SHIFT 0
3165 #define IGU_REGULAR_RESERVED0 (0x1<<20)
3166 #define IGU_REGULAR_RESERVED0_SHIFT 20
3167 #define IGU_REGULAR_SEGMENT_ACCESS (0x7<<21)
3168 #define IGU_REGULAR_SEGMENT_ACCESS_SHIFT 21
3169 #define IGU_REGULAR_BUPDATE (0x1<<24)
3170 #define IGU_REGULAR_BUPDATE_SHIFT 24
3171 #define IGU_REGULAR_ENABLE_INT (0x3<<25)
3172 #define IGU_REGULAR_ENABLE_INT_SHIFT 25
3173 #define IGU_REGULAR_RESERVED_1 (0x1<<27)
3174 #define IGU_REGULAR_RESERVED_1_SHIFT 27
3175 #define IGU_REGULAR_CLEANUP_TYPE (0x3<<28)
3176 #define IGU_REGULAR_CLEANUP_TYPE_SHIFT 28
3177 #define IGU_REGULAR_CLEANUP_SET (0x1<<30)
3178 #define IGU_REGULAR_CLEANUP_SET_SHIFT 30
3179 #define IGU_REGULAR_BCLEANUP (0x1<<31)
3180 #define IGU_REGULAR_BCLEANUP_SHIFT 31
3181 	u32 reserved_2;
3182 };
3183 
3184 /*
3185  * IGU driver acknowledgement register
3186  */
3187 union igu_consprod_reg {
3188 	struct igu_regular regular;
3189 	struct igu_backward_compatible backward_compatible;
3190 };
3191 
3192 
3193 /*
3194  * Igu control commands
3195  */
3196 enum igu_ctrl_cmd {
3197 	IGU_CTRL_CMD_TYPE_RD,
3198 	IGU_CTRL_CMD_TYPE_WR,
3199 	MAX_IGU_CTRL_CMD
3200 };
3201 
3202 
3203 /*
3204  * Control register for the IGU command register
3205  */
3206 struct igu_ctrl_reg {
3207 	u32 ctrl_data;
3208 #define IGU_CTRL_REG_ADDRESS (0xFFF<<0)
3209 #define IGU_CTRL_REG_ADDRESS_SHIFT 0
3210 #define IGU_CTRL_REG_FID (0x7F<<12)
3211 #define IGU_CTRL_REG_FID_SHIFT 12
3212 #define IGU_CTRL_REG_RESERVED (0x1<<19)
3213 #define IGU_CTRL_REG_RESERVED_SHIFT 19
3214 #define IGU_CTRL_REG_TYPE (0x1<<20)
3215 #define IGU_CTRL_REG_TYPE_SHIFT 20
3216 #define IGU_CTRL_REG_UNUSED (0x7FF<<21)
3217 #define IGU_CTRL_REG_UNUSED_SHIFT 21
3218 };
3219 
3220 
3221 /*
3222  * Igu interrupt command
3223  */
3224 enum igu_int_cmd {
3225 	IGU_INT_ENABLE,
3226 	IGU_INT_DISABLE,
3227 	IGU_INT_NOP,
3228 	IGU_INT_NOP2,
3229 	MAX_IGU_INT_CMD
3230 };
3231 
3232 
3233 /*
3234  * Igu segments
3235  */
3236 enum igu_seg_access {
3237 	IGU_SEG_ACCESS_NORM,
3238 	IGU_SEG_ACCESS_DEF,
3239 	IGU_SEG_ACCESS_ATTN,
3240 	MAX_IGU_SEG_ACCESS
3241 };
3242 
3243 
3244 /*
3245  * Parser parsing flags field
3246  */
3247 struct parsing_flags {
3248 	__le16 flags;
3249 #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE (0x1<<0)
3250 #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE_SHIFT 0
3251 #define PARSING_FLAGS_VLAN (0x1<<1)
3252 #define PARSING_FLAGS_VLAN_SHIFT 1
3253 #define PARSING_FLAGS_EXTRA_VLAN (0x1<<2)
3254 #define PARSING_FLAGS_EXTRA_VLAN_SHIFT 2
3255 #define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL (0x3<<3)
3256 #define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT 3
3257 #define PARSING_FLAGS_IP_OPTIONS (0x1<<5)
3258 #define PARSING_FLAGS_IP_OPTIONS_SHIFT 5
3259 #define PARSING_FLAGS_FRAGMENTATION_STATUS (0x1<<6)
3260 #define PARSING_FLAGS_FRAGMENTATION_STATUS_SHIFT 6
3261 #define PARSING_FLAGS_OVER_IP_PROTOCOL (0x3<<7)
3262 #define PARSING_FLAGS_OVER_IP_PROTOCOL_SHIFT 7
3263 #define PARSING_FLAGS_PURE_ACK_INDICATION (0x1<<9)
3264 #define PARSING_FLAGS_PURE_ACK_INDICATION_SHIFT 9
3265 #define PARSING_FLAGS_TCP_OPTIONS_EXIST (0x1<<10)
3266 #define PARSING_FLAGS_TCP_OPTIONS_EXIST_SHIFT 10
3267 #define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG (0x1<<11)
3268 #define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG_SHIFT 11
3269 #define PARSING_FLAGS_CONNECTION_MATCH (0x1<<12)
3270 #define PARSING_FLAGS_CONNECTION_MATCH_SHIFT 12
3271 #define PARSING_FLAGS_LLC_SNAP (0x1<<13)
3272 #define PARSING_FLAGS_LLC_SNAP_SHIFT 13
3273 #define PARSING_FLAGS_RESERVED0 (0x3<<14)
3274 #define PARSING_FLAGS_RESERVED0_SHIFT 14
3275 };
3276 
3277 
3278 /*
3279  * Parsing flags for TCP ACK type
3280  */
3281 enum prs_flags_ack_type {
3282 	PRS_FLAG_PUREACK_PIGGY,
3283 	PRS_FLAG_PUREACK_PURE,
3284 	MAX_PRS_FLAGS_ACK_TYPE
3285 };
3286 
3287 
3288 /*
3289  * Parsing flags for Ethernet address type
3290  */
3291 enum prs_flags_eth_addr_type {
3292 	PRS_FLAG_ETHTYPE_NON_UNICAST,
3293 	PRS_FLAG_ETHTYPE_UNICAST,
3294 	MAX_PRS_FLAGS_ETH_ADDR_TYPE
3295 };
3296 
3297 
3298 /*
3299  * Parsing flags for over-ethernet protocol
3300  */
3301 enum prs_flags_over_eth {
3302 	PRS_FLAG_OVERETH_UNKNOWN,
3303 	PRS_FLAG_OVERETH_IPV4,
3304 	PRS_FLAG_OVERETH_IPV6,
3305 	PRS_FLAG_OVERETH_LLCSNAP_UNKNOWN,
3306 	MAX_PRS_FLAGS_OVER_ETH
3307 };
3308 
3309 
3310 /*
3311  * Parsing flags for over-IP protocol
3312  */
3313 enum prs_flags_over_ip {
3314 	PRS_FLAG_OVERIP_UNKNOWN,
3315 	PRS_FLAG_OVERIP_TCP,
3316 	PRS_FLAG_OVERIP_UDP,
3317 	MAX_PRS_FLAGS_OVER_IP
3318 };
3319 
3320 
3321 /*
3322  * SDM operation gen command (generate aggregative interrupt)
3323  */
3324 struct sdm_op_gen {
3325 	__le32 command;
3326 #define SDM_OP_GEN_COMP_PARAM (0x1F<<0)
3327 #define SDM_OP_GEN_COMP_PARAM_SHIFT 0
3328 #define SDM_OP_GEN_COMP_TYPE (0x7<<5)
3329 #define SDM_OP_GEN_COMP_TYPE_SHIFT 5
3330 #define SDM_OP_GEN_AGG_VECT_IDX (0xFF<<8)
3331 #define SDM_OP_GEN_AGG_VECT_IDX_SHIFT 8
3332 #define SDM_OP_GEN_AGG_VECT_IDX_VALID (0x1<<16)
3333 #define SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT 16
3334 #define SDM_OP_GEN_RESERVED (0x7FFF<<17)
3335 #define SDM_OP_GEN_RESERVED_SHIFT 17
3336 };
3337 
3338 
3339 /*
3340  * Timers connection context
3341  */
3342 struct timers_block_context {
3343 	u32 __reserved_0;
3344 	u32 __reserved_1;
3345 	u32 __reserved_2;
3346 	u32 flags;
3347 #define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS (0x3<<0)
3348 #define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS_SHIFT 0
3349 #define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG (0x1<<2)
3350 #define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG_SHIFT 2
3351 #define __TIMERS_BLOCK_CONTEXT_RESERVED0 (0x1FFFFFFF<<3)
3352 #define __TIMERS_BLOCK_CONTEXT_RESERVED0_SHIFT 3
3353 };
3354 
3355 
3356 /*
3357  * The eth aggregative context of Tstorm
3358  */
3359 struct tstorm_eth_ag_context {
3360 	u32 __reserved0[14];
3361 };
3362 
3363 
3364 /*
3365  * The eth aggregative context of Ustorm
3366  */
3367 struct ustorm_eth_ag_context {
3368 	u32 __reserved0;
3369 #if defined(__BIG_ENDIAN)
3370 	u8 cdu_usage;
3371 	u8 __reserved2;
3372 	u16 __reserved1;
3373 #elif defined(__LITTLE_ENDIAN)
3374 	u16 __reserved1;
3375 	u8 __reserved2;
3376 	u8 cdu_usage;
3377 #endif
3378 	u32 __reserved3[6];
3379 };
3380 
3381 
3382 /*
3383  * The eth aggregative context of Xstorm
3384  */
3385 struct xstorm_eth_ag_context {
3386 	u32 reserved0;
3387 #if defined(__BIG_ENDIAN)
3388 	u8 cdu_reserved;
3389 	u8 reserved2;
3390 	u16 reserved1;
3391 #elif defined(__LITTLE_ENDIAN)
3392 	u16 reserved1;
3393 	u8 reserved2;
3394 	u8 cdu_reserved;
3395 #endif
3396 	u32 reserved3[30];
3397 };
3398 
3399 
3400 /*
3401  * doorbell message sent to the chip
3402  */
3403 struct doorbell {
3404 #if defined(__BIG_ENDIAN)
3405 	u16 zero_fill2;
3406 	u8 zero_fill1;
3407 	struct doorbell_hdr header;
3408 #elif defined(__LITTLE_ENDIAN)
3409 	struct doorbell_hdr header;
3410 	u8 zero_fill1;
3411 	u16 zero_fill2;
3412 #endif
3413 };
3414 
3415 
3416 /*
3417  * doorbell message sent to the chip
3418  */
3419 struct doorbell_set_prod {
3420 #if defined(__BIG_ENDIAN)
3421 	u16 prod;
3422 	u8 zero_fill1;
3423 	struct doorbell_hdr header;
3424 #elif defined(__LITTLE_ENDIAN)
3425 	struct doorbell_hdr header;
3426 	u8 zero_fill1;
3427 	u16 prod;
3428 #endif
3429 };
3430 
3431 
3432 struct regpair {
3433 	__le32 lo;
3434 	__le32 hi;
3435 };
3436 
3437 struct regpair_native {
3438 	u32 lo;
3439 	u32 hi;
3440 };
3441 
3442 /*
3443  * Classify rule opcodes in E2/E3
3444  */
3445 enum classify_rule {
3446 	CLASSIFY_RULE_OPCODE_MAC,
3447 	CLASSIFY_RULE_OPCODE_VLAN,
3448 	CLASSIFY_RULE_OPCODE_PAIR,
3449 	MAX_CLASSIFY_RULE
3450 };
3451 
3452 
3453 /*
3454  * Classify rule types in E2/E3
3455  */
3456 enum classify_rule_action_type {
3457 	CLASSIFY_RULE_REMOVE,
3458 	CLASSIFY_RULE_ADD,
3459 	MAX_CLASSIFY_RULE_ACTION_TYPE
3460 };
3461 
3462 
3463 /*
3464  * client init ramrod data
3465  */
3466 struct client_init_general_data {
3467 	u8 client_id;
3468 	u8 statistics_counter_id;
3469 	u8 statistics_en_flg;
3470 	u8 is_fcoe_flg;
3471 	u8 activate_flg;
3472 	u8 sp_client_id;
3473 	__le16 mtu;
3474 	u8 statistics_zero_flg;
3475 	u8 func_id;
3476 	u8 cos;
3477 	u8 traffic_type;
3478 	u32 reserved0;
3479 };
3480 
3481 
3482 /*
3483  * client init rx data
3484  */
3485 struct client_init_rx_data {
3486 	u8 tpa_en;
3487 #define CLIENT_INIT_RX_DATA_TPA_EN_IPV4 (0x1<<0)
3488 #define CLIENT_INIT_RX_DATA_TPA_EN_IPV4_SHIFT 0
3489 #define CLIENT_INIT_RX_DATA_TPA_EN_IPV6 (0x1<<1)
3490 #define CLIENT_INIT_RX_DATA_TPA_EN_IPV6_SHIFT 1
3491 #define CLIENT_INIT_RX_DATA_TPA_MODE (0x1<<2)
3492 #define CLIENT_INIT_RX_DATA_TPA_MODE_SHIFT 2
3493 #define CLIENT_INIT_RX_DATA_RESERVED5 (0x1F<<3)
3494 #define CLIENT_INIT_RX_DATA_RESERVED5_SHIFT 3
3495 	u8 vmqueue_mode_en_flg;
3496 	u8 extra_data_over_sgl_en_flg;
3497 	u8 cache_line_alignment_log_size;
3498 	u8 enable_dynamic_hc;
3499 	u8 max_sges_for_packet;
3500 	u8 client_qzone_id;
3501 	u8 drop_ip_cs_err_flg;
3502 	u8 drop_tcp_cs_err_flg;
3503 	u8 drop_ttl0_flg;
3504 	u8 drop_udp_cs_err_flg;
3505 	u8 inner_vlan_removal_enable_flg;
3506 	u8 outer_vlan_removal_enable_flg;
3507 	u8 status_block_id;
3508 	u8 rx_sb_index_number;
3509 	u8 dont_verify_rings_pause_thr_flg;
3510 	u8 max_tpa_queues;
3511 	u8 silent_vlan_removal_flg;
3512 	__le16 max_bytes_on_bd;
3513 	__le16 sge_buff_size;
3514 	u8 approx_mcast_engine_id;
3515 	u8 rss_engine_id;
3516 	struct regpair bd_page_base;
3517 	struct regpair sge_page_base;
3518 	struct regpair cqe_page_base;
3519 	u8 is_leading_rss;
3520 	u8 is_approx_mcast;
3521 	__le16 max_agg_size;
3522 	__le16 state;
3523 #define CLIENT_INIT_RX_DATA_UCAST_DROP_ALL (0x1<<0)
3524 #define CLIENT_INIT_RX_DATA_UCAST_DROP_ALL_SHIFT 0
3525 #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL (0x1<<1)
3526 #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL_SHIFT 1
3527 #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED (0x1<<2)
3528 #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED_SHIFT 2
3529 #define CLIENT_INIT_RX_DATA_MCAST_DROP_ALL (0x1<<3)
3530 #define CLIENT_INIT_RX_DATA_MCAST_DROP_ALL_SHIFT 3
3531 #define CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL (0x1<<4)
3532 #define CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL_SHIFT 4
3533 #define CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL (0x1<<5)
3534 #define CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL_SHIFT 5
3535 #define CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN (0x1<<6)
3536 #define CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN_SHIFT 6
3537 #define CLIENT_INIT_RX_DATA_RESERVED2 (0x1FF<<7)
3538 #define CLIENT_INIT_RX_DATA_RESERVED2_SHIFT 7
3539 	__le16 cqe_pause_thr_low;
3540 	__le16 cqe_pause_thr_high;
3541 	__le16 bd_pause_thr_low;
3542 	__le16 bd_pause_thr_high;
3543 	__le16 sge_pause_thr_low;
3544 	__le16 sge_pause_thr_high;
3545 	__le16 rx_cos_mask;
3546 	__le16 silent_vlan_value;
3547 	__le16 silent_vlan_mask;
3548 	__le32 reserved6[2];
3549 };
3550 
3551 /*
3552  * client init tx data
3553  */
3554 struct client_init_tx_data {
3555 	u8 enforce_security_flg;
3556 	u8 tx_status_block_id;
3557 	u8 tx_sb_index_number;
3558 	u8 tss_leading_client_id;
3559 	u8 tx_switching_flg;
3560 	u8 anti_spoofing_flg;
3561 	__le16 default_vlan;
3562 	struct regpair tx_bd_page_base;
3563 	__le16 state;
3564 #define CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL (0x1<<0)
3565 #define CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL_SHIFT 0
3566 #define CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL (0x1<<1)
3567 #define CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL_SHIFT 1
3568 #define CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL (0x1<<2)
3569 #define CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL_SHIFT 2
3570 #define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN (0x1<<3)
3571 #define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN_SHIFT 3
3572 #define CLIENT_INIT_TX_DATA_RESERVED0 (0xFFF<<4)
3573 #define CLIENT_INIT_TX_DATA_RESERVED0_SHIFT 4
3574 	u8 default_vlan_flg;
3575 	u8 force_default_pri_flg;
3576 	u8 tunnel_lso_inc_ip_id;
3577 	u8 refuse_outband_vlan_flg;
3578 	u8 tunnel_non_lso_pcsum_location;
3579 	u8 reserved1;
3580 };
3581 
3582 /*
3583  * client init ramrod data
3584  */
3585 struct client_init_ramrod_data {
3586 	struct client_init_general_data general;
3587 	struct client_init_rx_data rx;
3588 	struct client_init_tx_data tx;
3589 };
3590 
3591 
3592 /*
3593  * client update ramrod data
3594  */
3595 struct client_update_ramrod_data {
3596 	u8 client_id;
3597 	u8 func_id;
3598 	u8 inner_vlan_removal_enable_flg;
3599 	u8 inner_vlan_removal_change_flg;
3600 	u8 outer_vlan_removal_enable_flg;
3601 	u8 outer_vlan_removal_change_flg;
3602 	u8 anti_spoofing_enable_flg;
3603 	u8 anti_spoofing_change_flg;
3604 	u8 activate_flg;
3605 	u8 activate_change_flg;
3606 	__le16 default_vlan;
3607 	u8 default_vlan_enable_flg;
3608 	u8 default_vlan_change_flg;
3609 	__le16 silent_vlan_value;
3610 	__le16 silent_vlan_mask;
3611 	u8 silent_vlan_removal_flg;
3612 	u8 silent_vlan_change_flg;
3613 	u8 refuse_outband_vlan_flg;
3614 	u8 refuse_outband_vlan_change_flg;
3615 	u8 tx_switching_flg;
3616 	u8 tx_switching_change_flg;
3617 	__le32 reserved1;
3618 	__le32 echo;
3619 };
3620 
3621 
3622 /*
3623  * The eth storm context of Cstorm
3624  */
3625 struct cstorm_eth_st_context {
3626 	u32 __reserved0[4];
3627 };
3628 
3629 
3630 struct double_regpair {
3631 	u32 regpair0_lo;
3632 	u32 regpair0_hi;
3633 	u32 regpair1_lo;
3634 	u32 regpair1_hi;
3635 };
3636 
3637 
3638 /*
3639  * Ethernet address typesm used in ethernet tx BDs
3640  */
3641 enum eth_addr_type {
3642 	UNKNOWN_ADDRESS,
3643 	UNICAST_ADDRESS,
3644 	MULTICAST_ADDRESS,
3645 	BROADCAST_ADDRESS,
3646 	MAX_ETH_ADDR_TYPE
3647 };
3648 
3649 
3650 /*
3651  *
3652  */
3653 struct eth_classify_cmd_header {
3654 	u8 cmd_general_data;
3655 #define ETH_CLASSIFY_CMD_HEADER_RX_CMD (0x1<<0)
3656 #define ETH_CLASSIFY_CMD_HEADER_RX_CMD_SHIFT 0
3657 #define ETH_CLASSIFY_CMD_HEADER_TX_CMD (0x1<<1)
3658 #define ETH_CLASSIFY_CMD_HEADER_TX_CMD_SHIFT 1
3659 #define ETH_CLASSIFY_CMD_HEADER_OPCODE (0x3<<2)
3660 #define ETH_CLASSIFY_CMD_HEADER_OPCODE_SHIFT 2
3661 #define ETH_CLASSIFY_CMD_HEADER_IS_ADD (0x1<<4)
3662 #define ETH_CLASSIFY_CMD_HEADER_IS_ADD_SHIFT 4
3663 #define ETH_CLASSIFY_CMD_HEADER_RESERVED0 (0x7<<5)
3664 #define ETH_CLASSIFY_CMD_HEADER_RESERVED0_SHIFT 5
3665 	u8 func_id;
3666 	u8 client_id;
3667 	u8 reserved1;
3668 };
3669 
3670 
3671 /*
3672  * header for eth classification config ramrod
3673  */
3674 struct eth_classify_header {
3675 	u8 rule_cnt;
3676 	u8 reserved0;
3677 	__le16 reserved1;
3678 	__le32 echo;
3679 };
3680 
3681 
3682 /*
3683  * Command for adding/removing a MAC classification rule
3684  */
3685 struct eth_classify_mac_cmd {
3686 	struct eth_classify_cmd_header header;
3687 	__le16 reserved0;
3688 	__le16 inner_mac;
3689 	__le16 mac_lsb;
3690 	__le16 mac_mid;
3691 	__le16 mac_msb;
3692 	__le16 reserved1;
3693 };
3694 
3695 
3696 /*
3697  * Command for adding/removing a MAC-VLAN pair classification rule
3698  */
3699 struct eth_classify_pair_cmd {
3700 	struct eth_classify_cmd_header header;
3701 	__le16 reserved0;
3702 	__le16 inner_mac;
3703 	__le16 mac_lsb;
3704 	__le16 mac_mid;
3705 	__le16 mac_msb;
3706 	__le16 vlan;
3707 };
3708 
3709 
3710 /*
3711  * Command for adding/removing a VLAN classification rule
3712  */
3713 struct eth_classify_vlan_cmd {
3714 	struct eth_classify_cmd_header header;
3715 	__le32 reserved0;
3716 	__le32 reserved1;
3717 	__le16 reserved2;
3718 	__le16 vlan;
3719 };
3720 
3721 /*
3722  * union for eth classification rule
3723  */
3724 union eth_classify_rule_cmd {
3725 	struct eth_classify_mac_cmd mac;
3726 	struct eth_classify_vlan_cmd vlan;
3727 	struct eth_classify_pair_cmd pair;
3728 };
3729 
3730 /*
3731  * parameters for eth classification configuration ramrod
3732  */
3733 struct eth_classify_rules_ramrod_data {
3734 	struct eth_classify_header header;
3735 	union eth_classify_rule_cmd rules[CLASSIFY_RULES_COUNT];
3736 };
3737 
3738 
3739 /*
3740  * The data contain client ID need to the ramrod
3741  */
3742 struct eth_common_ramrod_data {
3743 	__le32 client_id;
3744 	__le32 reserved1;
3745 };
3746 
3747 
3748 /*
3749  * The eth storm context of Ustorm
3750  */
3751 struct ustorm_eth_st_context {
3752 	u32 reserved0[52];
3753 };
3754 
3755 /*
3756  * The eth storm context of Tstorm
3757  */
3758 struct tstorm_eth_st_context {
3759 	u32 __reserved0[28];
3760 };
3761 
3762 /*
3763  * The eth storm context of Xstorm
3764  */
3765 struct xstorm_eth_st_context {
3766 	u32 reserved0[60];
3767 };
3768 
3769 /*
3770  * Ethernet connection context
3771  */
3772 struct eth_context {
3773 	struct ustorm_eth_st_context ustorm_st_context;
3774 	struct tstorm_eth_st_context tstorm_st_context;
3775 	struct xstorm_eth_ag_context xstorm_ag_context;
3776 	struct tstorm_eth_ag_context tstorm_ag_context;
3777 	struct cstorm_eth_ag_context cstorm_ag_context;
3778 	struct ustorm_eth_ag_context ustorm_ag_context;
3779 	struct timers_block_context timers_context;
3780 	struct xstorm_eth_st_context xstorm_st_context;
3781 	struct cstorm_eth_st_context cstorm_st_context;
3782 };
3783 
3784 
3785 /*
3786  * union for sgl and raw data.
3787  */
3788 union eth_sgl_or_raw_data {
3789 	__le16 sgl[8];
3790 	u32 raw_data[4];
3791 };
3792 
3793 /*
3794  * eth FP end aggregation CQE parameters struct
3795  */
3796 struct eth_end_agg_rx_cqe {
3797 	u8 type_error_flags;
3798 #define ETH_END_AGG_RX_CQE_TYPE (0x3<<0)
3799 #define ETH_END_AGG_RX_CQE_TYPE_SHIFT 0
3800 #define ETH_END_AGG_RX_CQE_SGL_RAW_SEL (0x1<<2)
3801 #define ETH_END_AGG_RX_CQE_SGL_RAW_SEL_SHIFT 2
3802 #define ETH_END_AGG_RX_CQE_RESERVED0 (0x1F<<3)
3803 #define ETH_END_AGG_RX_CQE_RESERVED0_SHIFT 3
3804 	u8 reserved1;
3805 	u8 queue_index;
3806 	u8 reserved2;
3807 	__le32 timestamp_delta;
3808 	__le16 num_of_coalesced_segs;
3809 	__le16 pkt_len;
3810 	u8 pure_ack_count;
3811 	u8 reserved3;
3812 	__le16 reserved4;
3813 	union eth_sgl_or_raw_data sgl_or_raw_data;
3814 	__le32 reserved5[8];
3815 };
3816 
3817 
3818 /*
3819  * regular eth FP CQE parameters struct
3820  */
3821 struct eth_fast_path_rx_cqe {
3822 	u8 type_error_flags;
3823 #define ETH_FAST_PATH_RX_CQE_TYPE (0x3<<0)
3824 #define ETH_FAST_PATH_RX_CQE_TYPE_SHIFT 0
3825 #define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL (0x1<<2)
3826 #define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL_SHIFT 2
3827 #define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG (0x1<<3)
3828 #define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG_SHIFT 3
3829 #define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG (0x1<<4)
3830 #define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG_SHIFT 4
3831 #define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG (0x1<<5)
3832 #define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG_SHIFT 5
3833 #define ETH_FAST_PATH_RX_CQE_RESERVED0 (0x3<<6)
3834 #define ETH_FAST_PATH_RX_CQE_RESERVED0_SHIFT 6
3835 	u8 status_flags;
3836 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE (0x7<<0)
3837 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE_SHIFT 0
3838 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG (0x1<<3)
3839 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG_SHIFT 3
3840 #define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG (0x1<<4)
3841 #define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG_SHIFT 4
3842 #define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG (0x1<<5)
3843 #define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG_SHIFT 5
3844 #define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG (0x1<<6)
3845 #define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG_SHIFT 6
3846 #define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG (0x1<<7)
3847 #define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG_SHIFT 7
3848 	u8 queue_index;
3849 	u8 placement_offset;
3850 	__le32 rss_hash_result;
3851 	__le16 vlan_tag;
3852 	__le16 pkt_len_or_gro_seg_len;
3853 	__le16 len_on_bd;
3854 	struct parsing_flags pars_flags;
3855 	union eth_sgl_or_raw_data sgl_or_raw_data;
3856 	__le32 reserved1[7];
3857 	u32 marker;
3858 };
3859 
3860 
3861 /*
3862  * Command for setting classification flags for a client
3863  */
3864 struct eth_filter_rules_cmd {
3865 	u8 cmd_general_data;
3866 #define ETH_FILTER_RULES_CMD_RX_CMD (0x1<<0)
3867 #define ETH_FILTER_RULES_CMD_RX_CMD_SHIFT 0
3868 #define ETH_FILTER_RULES_CMD_TX_CMD (0x1<<1)
3869 #define ETH_FILTER_RULES_CMD_TX_CMD_SHIFT 1
3870 #define ETH_FILTER_RULES_CMD_RESERVED0 (0x3F<<2)
3871 #define ETH_FILTER_RULES_CMD_RESERVED0_SHIFT 2
3872 	u8 func_id;
3873 	u8 client_id;
3874 	u8 reserved1;
3875 	__le16 state;
3876 #define ETH_FILTER_RULES_CMD_UCAST_DROP_ALL (0x1<<0)
3877 #define ETH_FILTER_RULES_CMD_UCAST_DROP_ALL_SHIFT 0
3878 #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL (0x1<<1)
3879 #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL_SHIFT 1
3880 #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED (0x1<<2)
3881 #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED_SHIFT 2
3882 #define ETH_FILTER_RULES_CMD_MCAST_DROP_ALL (0x1<<3)
3883 #define ETH_FILTER_RULES_CMD_MCAST_DROP_ALL_SHIFT 3
3884 #define ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL (0x1<<4)
3885 #define ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL_SHIFT 4
3886 #define ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL (0x1<<5)
3887 #define ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL_SHIFT 5
3888 #define ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN (0x1<<6)
3889 #define ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN_SHIFT 6
3890 #define ETH_FILTER_RULES_CMD_RESERVED2 (0x1FF<<7)
3891 #define ETH_FILTER_RULES_CMD_RESERVED2_SHIFT 7
3892 	__le16 reserved3;
3893 	struct regpair reserved4;
3894 };
3895 
3896 
3897 /*
3898  * parameters for eth classification filters ramrod
3899  */
3900 struct eth_filter_rules_ramrod_data {
3901 	struct eth_classify_header header;
3902 	struct eth_filter_rules_cmd rules[FILTER_RULES_COUNT];
3903 };
3904 
3905 
3906 /*
3907  * parameters for eth classification configuration ramrod
3908  */
3909 struct eth_general_rules_ramrod_data {
3910 	struct eth_classify_header header;
3911 	union eth_classify_rule_cmd rules[CLASSIFY_RULES_COUNT];
3912 };
3913 
3914 
3915 /*
3916  * The data for Halt ramrod
3917  */
3918 struct eth_halt_ramrod_data {
3919 	__le32 client_id;
3920 	__le32 reserved0;
3921 };
3922 
3923 
3924 /*
3925  * destination and source mac address.
3926  */
3927 struct eth_mac_addresses {
3928 #if defined(__BIG_ENDIAN)
3929 	__le16 dst_mid;
3930 	__le16 dst_lo;
3931 #elif defined(__LITTLE_ENDIAN)
3932 	__le16 dst_lo;
3933 	__le16 dst_mid;
3934 #endif
3935 #if defined(__BIG_ENDIAN)
3936 	__le16 src_lo;
3937 	__le16 dst_hi;
3938 #elif defined(__LITTLE_ENDIAN)
3939 	__le16 dst_hi;
3940 	__le16 src_lo;
3941 #endif
3942 #if defined(__BIG_ENDIAN)
3943 	__le16 src_hi;
3944 	__le16 src_mid;
3945 #elif defined(__LITTLE_ENDIAN)
3946 	__le16 src_mid;
3947 	__le16 src_hi;
3948 #endif
3949 };
3950 
3951 /* tunneling related data */
3952 struct eth_tunnel_data {
3953 #if defined(__BIG_ENDIAN)
3954 	__le16 dst_mid;
3955 	__le16 dst_lo;
3956 #elif defined(__LITTLE_ENDIAN)
3957 	__le16 dst_lo;
3958 	__le16 dst_mid;
3959 #endif
3960 #if defined(__BIG_ENDIAN)
3961 	__le16 reserved0;
3962 	__le16 dst_hi;
3963 #elif defined(__LITTLE_ENDIAN)
3964 	__le16 dst_hi;
3965 	__le16 reserved0;
3966 #endif
3967 #if defined(__BIG_ENDIAN)
3968 	u8 reserved1;
3969 	u8 ip_hdr_start_inner_w;
3970 	__le16 pseudo_csum;
3971 #elif defined(__LITTLE_ENDIAN)
3972 	__le16 pseudo_csum;
3973 	u8 ip_hdr_start_inner_w;
3974 	u8 reserved1;
3975 #endif
3976 };
3977 
3978 /* union for mac addresses and for tunneling data.
3979  * considered as tunneling data only if (tunnel_exist == 1).
3980  */
3981 union eth_mac_addr_or_tunnel_data {
3982 	struct eth_mac_addresses mac_addr;
3983 	struct eth_tunnel_data tunnel_data;
3984 };
3985 
3986 /*Command for setting multicast classification for a client */
3987 struct eth_multicast_rules_cmd {
3988 	u8 cmd_general_data;
3989 #define ETH_MULTICAST_RULES_CMD_RX_CMD (0x1<<0)
3990 #define ETH_MULTICAST_RULES_CMD_RX_CMD_SHIFT 0
3991 #define ETH_MULTICAST_RULES_CMD_TX_CMD (0x1<<1)
3992 #define ETH_MULTICAST_RULES_CMD_TX_CMD_SHIFT 1
3993 #define ETH_MULTICAST_RULES_CMD_IS_ADD (0x1<<2)
3994 #define ETH_MULTICAST_RULES_CMD_IS_ADD_SHIFT 2
3995 #define ETH_MULTICAST_RULES_CMD_RESERVED0 (0x1F<<3)
3996 #define ETH_MULTICAST_RULES_CMD_RESERVED0_SHIFT 3
3997 	u8 func_id;
3998 	u8 bin_id;
3999 	u8 engine_id;
4000 	__le32 reserved2;
4001 	struct regpair reserved3;
4002 };
4003 
4004 /*
4005  * parameters for multicast classification ramrod
4006  */
4007 struct eth_multicast_rules_ramrod_data {
4008 	struct eth_classify_header header;
4009 	struct eth_multicast_rules_cmd rules[MULTICAST_RULES_COUNT];
4010 };
4011 
4012 /*
4013  * Place holder for ramrods protocol specific data
4014  */
4015 struct ramrod_data {
4016 	__le32 data_lo;
4017 	__le32 data_hi;
4018 };
4019 
4020 /*
4021  * union for ramrod data for Ethernet protocol (CQE) (force size of 16 bits)
4022  */
4023 union eth_ramrod_data {
4024 	struct ramrod_data general;
4025 };
4026 
4027 
4028 /*
4029  * RSS toeplitz hash type, as reported in CQE
4030  */
4031 enum eth_rss_hash_type {
4032 	DEFAULT_HASH_TYPE,
4033 	IPV4_HASH_TYPE,
4034 	TCP_IPV4_HASH_TYPE,
4035 	IPV6_HASH_TYPE,
4036 	TCP_IPV6_HASH_TYPE,
4037 	VLAN_PRI_HASH_TYPE,
4038 	E1HOV_PRI_HASH_TYPE,
4039 	DSCP_HASH_TYPE,
4040 	MAX_ETH_RSS_HASH_TYPE
4041 };
4042 
4043 
4044 /*
4045  * Ethernet RSS mode
4046  */
4047 enum eth_rss_mode {
4048 	ETH_RSS_MODE_DISABLED,
4049 	ETH_RSS_MODE_REGULAR,
4050 	ETH_RSS_MODE_VLAN_PRI,
4051 	ETH_RSS_MODE_E1HOV_PRI,
4052 	ETH_RSS_MODE_IP_DSCP,
4053 	MAX_ETH_RSS_MODE
4054 };
4055 
4056 
4057 /*
4058  * parameters for RSS update ramrod (E2)
4059  */
4060 struct eth_rss_update_ramrod_data {
4061 	u8 rss_engine_id;
4062 	u8 capabilities;
4063 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY (0x1<<0)
4064 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY_SHIFT 0
4065 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY (0x1<<1)
4066 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY_SHIFT 1
4067 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY (0x1<<2)
4068 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY_SHIFT 2
4069 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY (0x1<<3)
4070 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY_SHIFT 3
4071 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY (0x1<<4)
4072 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY_SHIFT 4
4073 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY (0x1<<5)
4074 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY_SHIFT 5
4075 #define ETH_RSS_UPDATE_RAMROD_DATA_EN_5_TUPLE_CAPABILITY (0x1<<6)
4076 #define ETH_RSS_UPDATE_RAMROD_DATA_EN_5_TUPLE_CAPABILITY_SHIFT 6
4077 #define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY (0x1<<7)
4078 #define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY_SHIFT 7
4079 	u8 rss_result_mask;
4080 	u8 rss_mode;
4081 	__le16 udp_4tuple_dst_port_mask;
4082 	__le16 udp_4tuple_dst_port_value;
4083 	u8 indirection_table[T_ETH_INDIRECTION_TABLE_SIZE];
4084 	__le32 rss_key[T_ETH_RSS_KEY];
4085 	__le32 echo;
4086 	__le32 reserved3;
4087 };
4088 
4089 
4090 /*
4091  * The eth Rx Buffer Descriptor
4092  */
4093 struct eth_rx_bd {
4094 	__le32 addr_lo;
4095 	__le32 addr_hi;
4096 };
4097 
4098 
4099 /*
4100  * Eth Rx Cqe structure- general structure for ramrods
4101  */
4102 struct common_ramrod_eth_rx_cqe {
4103 	u8 ramrod_type;
4104 #define COMMON_RAMROD_ETH_RX_CQE_TYPE (0x3<<0)
4105 #define COMMON_RAMROD_ETH_RX_CQE_TYPE_SHIFT 0
4106 #define COMMON_RAMROD_ETH_RX_CQE_ERROR (0x1<<2)
4107 #define COMMON_RAMROD_ETH_RX_CQE_ERROR_SHIFT 2
4108 #define COMMON_RAMROD_ETH_RX_CQE_RESERVED0 (0x1F<<3)
4109 #define COMMON_RAMROD_ETH_RX_CQE_RESERVED0_SHIFT 3
4110 	u8 conn_type;
4111 	__le16 reserved1;
4112 	__le32 conn_and_cmd_data;
4113 #define COMMON_RAMROD_ETH_RX_CQE_CID (0xFFFFFF<<0)
4114 #define COMMON_RAMROD_ETH_RX_CQE_CID_SHIFT 0
4115 #define COMMON_RAMROD_ETH_RX_CQE_CMD_ID (0xFF<<24)
4116 #define COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT 24
4117 	struct ramrod_data protocol_data;
4118 	__le32 echo;
4119 	__le32 reserved2[11];
4120 };
4121 
4122 /*
4123  * Rx Last CQE in page (in ETH)
4124  */
4125 struct eth_rx_cqe_next_page {
4126 	__le32 addr_lo;
4127 	__le32 addr_hi;
4128 	__le32 reserved[14];
4129 };
4130 
4131 /*
4132  * union for all eth rx cqe types (fix their sizes)
4133  */
4134 union eth_rx_cqe {
4135 	struct eth_fast_path_rx_cqe fast_path_cqe;
4136 	struct common_ramrod_eth_rx_cqe ramrod_cqe;
4137 	struct eth_rx_cqe_next_page next_page_cqe;
4138 	struct eth_end_agg_rx_cqe end_agg_cqe;
4139 };
4140 
4141 
4142 /*
4143  * Values for RX ETH CQE type field
4144  */
4145 enum eth_rx_cqe_type {
4146 	RX_ETH_CQE_TYPE_ETH_FASTPATH,
4147 	RX_ETH_CQE_TYPE_ETH_RAMROD,
4148 	RX_ETH_CQE_TYPE_ETH_START_AGG,
4149 	RX_ETH_CQE_TYPE_ETH_STOP_AGG,
4150 	MAX_ETH_RX_CQE_TYPE
4151 };
4152 
4153 
4154 /*
4155  * Type of SGL/Raw field in ETH RX fast path CQE
4156  */
4157 enum eth_rx_fp_sel {
4158 	ETH_FP_CQE_REGULAR,
4159 	ETH_FP_CQE_RAW,
4160 	MAX_ETH_RX_FP_SEL
4161 };
4162 
4163 
4164 /*
4165  * The eth Rx SGE Descriptor
4166  */
4167 struct eth_rx_sge {
4168 	__le32 addr_lo;
4169 	__le32 addr_hi;
4170 };
4171 
4172 
4173 /*
4174  * common data for all protocols
4175  */
4176 struct spe_hdr {
4177 	__le32 conn_and_cmd_data;
4178 #define SPE_HDR_CID (0xFFFFFF<<0)
4179 #define SPE_HDR_CID_SHIFT 0
4180 #define SPE_HDR_CMD_ID (0xFF<<24)
4181 #define SPE_HDR_CMD_ID_SHIFT 24
4182 	__le16 type;
4183 #define SPE_HDR_CONN_TYPE (0xFF<<0)
4184 #define SPE_HDR_CONN_TYPE_SHIFT 0
4185 #define SPE_HDR_FUNCTION_ID (0xFF<<8)
4186 #define SPE_HDR_FUNCTION_ID_SHIFT 8
4187 	__le16 reserved1;
4188 };
4189 
4190 /*
4191  * specific data for ethernet slow path element
4192  */
4193 union eth_specific_data {
4194 	u8 protocol_data[8];
4195 	struct regpair client_update_ramrod_data;
4196 	struct regpair client_init_ramrod_init_data;
4197 	struct eth_halt_ramrod_data halt_ramrod_data;
4198 	struct regpair update_data_addr;
4199 	struct eth_common_ramrod_data common_ramrod_data;
4200 	struct regpair classify_cfg_addr;
4201 	struct regpair filter_cfg_addr;
4202 	struct regpair mcast_cfg_addr;
4203 };
4204 
4205 /*
4206  * Ethernet slow path element
4207  */
4208 struct eth_spe {
4209 	struct spe_hdr hdr;
4210 	union eth_specific_data data;
4211 };
4212 
4213 
4214 /*
4215  * Ethernet command ID for slow path elements
4216  */
4217 enum eth_spqe_cmd_id {
4218 	RAMROD_CMD_ID_ETH_UNUSED,
4219 	RAMROD_CMD_ID_ETH_CLIENT_SETUP,
4220 	RAMROD_CMD_ID_ETH_HALT,
4221 	RAMROD_CMD_ID_ETH_FORWARD_SETUP,
4222 	RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP,
4223 	RAMROD_CMD_ID_ETH_CLIENT_UPDATE,
4224 	RAMROD_CMD_ID_ETH_EMPTY,
4225 	RAMROD_CMD_ID_ETH_TERMINATE,
4226 	RAMROD_CMD_ID_ETH_TPA_UPDATE,
4227 	RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES,
4228 	RAMROD_CMD_ID_ETH_FILTER_RULES,
4229 	RAMROD_CMD_ID_ETH_MULTICAST_RULES,
4230 	RAMROD_CMD_ID_ETH_RSS_UPDATE,
4231 	RAMROD_CMD_ID_ETH_SET_MAC,
4232 	MAX_ETH_SPQE_CMD_ID
4233 };
4234 
4235 
4236 /*
4237  * eth tpa update command
4238  */
4239 enum eth_tpa_update_command {
4240 	TPA_UPDATE_NONE_COMMAND,
4241 	TPA_UPDATE_ENABLE_COMMAND,
4242 	TPA_UPDATE_DISABLE_COMMAND,
4243 	MAX_ETH_TPA_UPDATE_COMMAND
4244 };
4245 
4246 /* In case of LSO over IPv4 tunnel, whether to increment
4247  * IP ID on external IP header or internal IP header
4248  */
4249 enum eth_tunnel_lso_inc_ip_id {
4250 	EXT_HEADER,
4251 	INT_HEADER,
4252 	MAX_ETH_TUNNEL_LSO_INC_IP_ID
4253 };
4254 
4255 /* In case tunnel exist and L4 checksum offload,
4256  * the pseudo checksum location, on packet or on BD.
4257  */
4258 enum eth_tunnel_non_lso_pcsum_location {
4259 	PCSUM_ON_PKT,
4260 	PCSUM_ON_BD,
4261 	MAX_ETH_TUNNEL_NON_LSO_PCSUM_LOCATION
4262 };
4263 
4264 /*
4265  * Tx regular BD structure
4266  */
4267 struct eth_tx_bd {
4268 	__le32 addr_lo;
4269 	__le32 addr_hi;
4270 	__le16 total_pkt_bytes;
4271 	__le16 nbytes;
4272 	u8 reserved[4];
4273 };
4274 
4275 
4276 /*
4277  * structure for easy accessibility to assembler
4278  */
4279 struct eth_tx_bd_flags {
4280 	u8 as_bitfield;
4281 #define ETH_TX_BD_FLAGS_IP_CSUM (0x1<<0)
4282 #define ETH_TX_BD_FLAGS_IP_CSUM_SHIFT 0
4283 #define ETH_TX_BD_FLAGS_L4_CSUM (0x1<<1)
4284 #define ETH_TX_BD_FLAGS_L4_CSUM_SHIFT 1
4285 #define ETH_TX_BD_FLAGS_VLAN_MODE (0x3<<2)
4286 #define ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT 2
4287 #define ETH_TX_BD_FLAGS_START_BD (0x1<<4)
4288 #define ETH_TX_BD_FLAGS_START_BD_SHIFT 4
4289 #define ETH_TX_BD_FLAGS_IS_UDP (0x1<<5)
4290 #define ETH_TX_BD_FLAGS_IS_UDP_SHIFT 5
4291 #define ETH_TX_BD_FLAGS_SW_LSO (0x1<<6)
4292 #define ETH_TX_BD_FLAGS_SW_LSO_SHIFT 6
4293 #define ETH_TX_BD_FLAGS_IPV6 (0x1<<7)
4294 #define ETH_TX_BD_FLAGS_IPV6_SHIFT 7
4295 };
4296 
4297 /*
4298  * The eth Tx Buffer Descriptor
4299  */
4300 struct eth_tx_start_bd {
4301 	__le32 addr_lo;
4302 	__le32 addr_hi;
4303 	__le16 nbd;
4304 	__le16 nbytes;
4305 	__le16 vlan_or_ethertype;
4306 	struct eth_tx_bd_flags bd_flags;
4307 	u8 general_data;
4308 #define ETH_TX_START_BD_HDR_NBDS (0xF<<0)
4309 #define ETH_TX_START_BD_HDR_NBDS_SHIFT 0
4310 #define ETH_TX_START_BD_FORCE_VLAN_MODE (0x1<<4)
4311 #define ETH_TX_START_BD_FORCE_VLAN_MODE_SHIFT 4
4312 #define ETH_TX_START_BD_PARSE_NBDS (0x3<<5)
4313 #define ETH_TX_START_BD_PARSE_NBDS_SHIFT 5
4314 #define ETH_TX_START_BD_TUNNEL_EXIST (0x1<<7)
4315 #define ETH_TX_START_BD_TUNNEL_EXIST_SHIFT 7
4316 };
4317 
4318 /*
4319  * Tx parsing BD structure for ETH E1/E1h
4320  */
4321 struct eth_tx_parse_bd_e1x {
4322 	__le16 global_data;
4323 #define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W (0xF<<0)
4324 #define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W_SHIFT 0
4325 #define ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE (0x3<<4)
4326 #define ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE_SHIFT 4
4327 #define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN (0x1<<6)
4328 #define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN_SHIFT 6
4329 #define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN (0x1<<7)
4330 #define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN_SHIFT 7
4331 #define ETH_TX_PARSE_BD_E1X_NS_FLG (0x1<<8)
4332 #define ETH_TX_PARSE_BD_E1X_NS_FLG_SHIFT 8
4333 #define ETH_TX_PARSE_BD_E1X_RESERVED0 (0x7F<<9)
4334 #define ETH_TX_PARSE_BD_E1X_RESERVED0_SHIFT 9
4335 	u8 tcp_flags;
4336 #define ETH_TX_PARSE_BD_E1X_FIN_FLG (0x1<<0)
4337 #define ETH_TX_PARSE_BD_E1X_FIN_FLG_SHIFT 0
4338 #define ETH_TX_PARSE_BD_E1X_SYN_FLG (0x1<<1)
4339 #define ETH_TX_PARSE_BD_E1X_SYN_FLG_SHIFT 1
4340 #define ETH_TX_PARSE_BD_E1X_RST_FLG (0x1<<2)
4341 #define ETH_TX_PARSE_BD_E1X_RST_FLG_SHIFT 2
4342 #define ETH_TX_PARSE_BD_E1X_PSH_FLG (0x1<<3)
4343 #define ETH_TX_PARSE_BD_E1X_PSH_FLG_SHIFT 3
4344 #define ETH_TX_PARSE_BD_E1X_ACK_FLG (0x1<<4)
4345 #define ETH_TX_PARSE_BD_E1X_ACK_FLG_SHIFT 4
4346 #define ETH_TX_PARSE_BD_E1X_URG_FLG (0x1<<5)
4347 #define ETH_TX_PARSE_BD_E1X_URG_FLG_SHIFT 5
4348 #define ETH_TX_PARSE_BD_E1X_ECE_FLG (0x1<<6)
4349 #define ETH_TX_PARSE_BD_E1X_ECE_FLG_SHIFT 6
4350 #define ETH_TX_PARSE_BD_E1X_CWR_FLG (0x1<<7)
4351 #define ETH_TX_PARSE_BD_E1X_CWR_FLG_SHIFT 7
4352 	u8 ip_hlen_w;
4353 	__le16 total_hlen_w;
4354 	__le16 tcp_pseudo_csum;
4355 	__le16 lso_mss;
4356 	__le16 ip_id;
4357 	__le32 tcp_send_seq;
4358 };
4359 
4360 /*
4361  * Tx parsing BD structure for ETH E2
4362  */
4363 struct eth_tx_parse_bd_e2 {
4364 	union eth_mac_addr_or_tunnel_data data;
4365 	__le32 parsing_data;
4366 #define ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W (0x7FF<<0)
4367 #define ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W_SHIFT 0
4368 #define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW (0xF<<11)
4369 #define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW_SHIFT 11
4370 #define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR (0x1<<15)
4371 #define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR_SHIFT 15
4372 #define ETH_TX_PARSE_BD_E2_LSO_MSS (0x3FFF<<16)
4373 #define ETH_TX_PARSE_BD_E2_LSO_MSS_SHIFT 16
4374 #define ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE (0x3<<30)
4375 #define ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE_SHIFT 30
4376 };
4377 
4378 /*
4379  * Tx 2nd parsing BD structure for ETH packet
4380  */
4381 struct eth_tx_parse_2nd_bd {
4382 	__le16 global_data;
4383 #define ETH_TX_PARSE_2ND_BD_IP_HDR_START_OUTER_W (0xF<<0)
4384 #define ETH_TX_PARSE_2ND_BD_IP_HDR_START_OUTER_W_SHIFT 0
4385 #define ETH_TX_PARSE_2ND_BD_IP_HDR_TYPE_OUTER (0x1<<4)
4386 #define ETH_TX_PARSE_2ND_BD_IP_HDR_TYPE_OUTER_SHIFT 4
4387 #define ETH_TX_PARSE_2ND_BD_LLC_SNAP_EN (0x1<<5)
4388 #define ETH_TX_PARSE_2ND_BD_LLC_SNAP_EN_SHIFT 5
4389 #define ETH_TX_PARSE_2ND_BD_NS_FLG (0x1<<6)
4390 #define ETH_TX_PARSE_2ND_BD_NS_FLG_SHIFT 6
4391 #define ETH_TX_PARSE_2ND_BD_TUNNEL_UDP_EXIST (0x1<<7)
4392 #define ETH_TX_PARSE_2ND_BD_TUNNEL_UDP_EXIST_SHIFT 7
4393 #define ETH_TX_PARSE_2ND_BD_IP_HDR_LEN_OUTER_W (0x1F<<8)
4394 #define ETH_TX_PARSE_2ND_BD_IP_HDR_LEN_OUTER_W_SHIFT 8
4395 #define ETH_TX_PARSE_2ND_BD_RESERVED0 (0x7<<13)
4396 #define ETH_TX_PARSE_2ND_BD_RESERVED0_SHIFT 13
4397 	__le16 reserved1;
4398 	u8 tcp_flags;
4399 #define ETH_TX_PARSE_2ND_BD_FIN_FLG (0x1<<0)
4400 #define ETH_TX_PARSE_2ND_BD_FIN_FLG_SHIFT 0
4401 #define ETH_TX_PARSE_2ND_BD_SYN_FLG (0x1<<1)
4402 #define ETH_TX_PARSE_2ND_BD_SYN_FLG_SHIFT 1
4403 #define ETH_TX_PARSE_2ND_BD_RST_FLG (0x1<<2)
4404 #define ETH_TX_PARSE_2ND_BD_RST_FLG_SHIFT 2
4405 #define ETH_TX_PARSE_2ND_BD_PSH_FLG (0x1<<3)
4406 #define ETH_TX_PARSE_2ND_BD_PSH_FLG_SHIFT 3
4407 #define ETH_TX_PARSE_2ND_BD_ACK_FLG (0x1<<4)
4408 #define ETH_TX_PARSE_2ND_BD_ACK_FLG_SHIFT 4
4409 #define ETH_TX_PARSE_2ND_BD_URG_FLG (0x1<<5)
4410 #define ETH_TX_PARSE_2ND_BD_URG_FLG_SHIFT 5
4411 #define ETH_TX_PARSE_2ND_BD_ECE_FLG (0x1<<6)
4412 #define ETH_TX_PARSE_2ND_BD_ECE_FLG_SHIFT 6
4413 #define ETH_TX_PARSE_2ND_BD_CWR_FLG (0x1<<7)
4414 #define ETH_TX_PARSE_2ND_BD_CWR_FLG_SHIFT 7
4415 	u8 reserved2;
4416 	u8 tunnel_udp_hdr_start_w;
4417 	u8 fw_ip_hdr_to_payload_w;
4418 	__le16 fw_ip_csum_wo_len_flags_frag;
4419 	__le16 hw_ip_id;
4420 	__le32 tcp_send_seq;
4421 };
4422 
4423 /* The last BD in the BD memory will hold a pointer to the next BD memory */
4424 struct eth_tx_next_bd {
4425 	__le32 addr_lo;
4426 	__le32 addr_hi;
4427 	u8 reserved[8];
4428 };
4429 
4430 /*
4431  * union for 4 Bd types
4432  */
4433 union eth_tx_bd_types {
4434 	struct eth_tx_start_bd start_bd;
4435 	struct eth_tx_bd reg_bd;
4436 	struct eth_tx_parse_bd_e1x parse_bd_e1x;
4437 	struct eth_tx_parse_bd_e2 parse_bd_e2;
4438 	struct eth_tx_parse_2nd_bd parse_2nd_bd;
4439 	struct eth_tx_next_bd next_bd;
4440 };
4441 
4442 /*
4443  * array of 13 bds as appears in the eth xstorm context
4444  */
4445 struct eth_tx_bds_array {
4446 	union eth_tx_bd_types bds[13];
4447 };
4448 
4449 
4450 /*
4451  * VLAN mode on TX BDs
4452  */
4453 enum eth_tx_vlan_type {
4454 	X_ETH_NO_VLAN,
4455 	X_ETH_OUTBAND_VLAN,
4456 	X_ETH_INBAND_VLAN,
4457 	X_ETH_FW_ADDED_VLAN,
4458 	MAX_ETH_TX_VLAN_TYPE
4459 };
4460 
4461 
4462 /*
4463  * Ethernet VLAN filtering mode in E1x
4464  */
4465 enum eth_vlan_filter_mode {
4466 	ETH_VLAN_FILTER_ANY_VLAN,
4467 	ETH_VLAN_FILTER_SPECIFIC_VLAN,
4468 	ETH_VLAN_FILTER_CLASSIFY,
4469 	MAX_ETH_VLAN_FILTER_MODE
4470 };
4471 
4472 
4473 /*
4474  * MAC filtering configuration command header
4475  */
4476 struct mac_configuration_hdr {
4477 	u8 length;
4478 	u8 offset;
4479 	__le16 client_id;
4480 	__le32 echo;
4481 };
4482 
4483 /*
4484  * MAC address in list for ramrod
4485  */
4486 struct mac_configuration_entry {
4487 	__le16 lsb_mac_addr;
4488 	__le16 middle_mac_addr;
4489 	__le16 msb_mac_addr;
4490 	__le16 vlan_id;
4491 	u8 pf_id;
4492 	u8 flags;
4493 #define MAC_CONFIGURATION_ENTRY_ACTION_TYPE (0x1<<0)
4494 #define MAC_CONFIGURATION_ENTRY_ACTION_TYPE_SHIFT 0
4495 #define MAC_CONFIGURATION_ENTRY_RDMA_MAC (0x1<<1)
4496 #define MAC_CONFIGURATION_ENTRY_RDMA_MAC_SHIFT 1
4497 #define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE (0x3<<2)
4498 #define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE_SHIFT 2
4499 #define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL (0x1<<4)
4500 #define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL_SHIFT 4
4501 #define MAC_CONFIGURATION_ENTRY_BROADCAST (0x1<<5)
4502 #define MAC_CONFIGURATION_ENTRY_BROADCAST_SHIFT 5
4503 #define MAC_CONFIGURATION_ENTRY_RESERVED1 (0x3<<6)
4504 #define MAC_CONFIGURATION_ENTRY_RESERVED1_SHIFT 6
4505 	__le16 reserved0;
4506 	__le32 clients_bit_vector;
4507 };
4508 
4509 /*
4510  * MAC filtering configuration command
4511  */
4512 struct mac_configuration_cmd {
4513 	struct mac_configuration_hdr hdr;
4514 	struct mac_configuration_entry config_table[64];
4515 };
4516 
4517 
4518 /*
4519  * Set-MAC command type (in E1x)
4520  */
4521 enum set_mac_action_type {
4522 	T_ETH_MAC_COMMAND_INVALIDATE,
4523 	T_ETH_MAC_COMMAND_SET,
4524 	MAX_SET_MAC_ACTION_TYPE
4525 };
4526 
4527 
4528 /*
4529  * Ethernet TPA Modes
4530  */
4531 enum tpa_mode {
4532 	TPA_LRO,
4533 	TPA_GRO,
4534 	MAX_TPA_MODE};
4535 
4536 
4537 /*
4538  * tpa update ramrod data
4539  */
4540 struct tpa_update_ramrod_data {
4541 	u8 update_ipv4;
4542 	u8 update_ipv6;
4543 	u8 client_id;
4544 	u8 max_tpa_queues;
4545 	u8 max_sges_for_packet;
4546 	u8 complete_on_both_clients;
4547 	u8 dont_verify_rings_pause_thr_flg;
4548 	u8 tpa_mode;
4549 	__le16 sge_buff_size;
4550 	__le16 max_agg_size;
4551 	__le32 sge_page_base_lo;
4552 	__le32 sge_page_base_hi;
4553 	__le16 sge_pause_thr_low;
4554 	__le16 sge_pause_thr_high;
4555 };
4556 
4557 
4558 /*
4559  * approximate-match multicast filtering for E1H per function in Tstorm
4560  */
4561 struct tstorm_eth_approximate_match_multicast_filtering {
4562 	u32 mcast_add_hash_bit_array[8];
4563 };
4564 
4565 
4566 /*
4567  * Common configuration parameters per function in Tstorm
4568  */
4569 struct tstorm_eth_function_common_config {
4570 	__le16 config_flags;
4571 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0)
4572 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0
4573 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1)
4574 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1
4575 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1<<2)
4576 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2
4577 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3)
4578 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3
4579 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE (0x7<<4)
4580 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT 4
4581 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE (0x1<<7)
4582 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE_SHIFT 7
4583 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0xFF<<8)
4584 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 8
4585 	u8 rss_result_mask;
4586 	u8 reserved1;
4587 	__le16 vlan_id[2];
4588 };
4589 
4590 
4591 /*
4592  * MAC filtering configuration parameters per port in Tstorm
4593  */
4594 struct tstorm_eth_mac_filter_config {
4595 	u32 ucast_drop_all;
4596 	u32 ucast_accept_all;
4597 	u32 mcast_drop_all;
4598 	u32 mcast_accept_all;
4599 	u32 bcast_accept_all;
4600 	u32 vlan_filter[2];
4601 	u32 unmatched_unicast;
4602 };
4603 
4604 
4605 /*
4606  * tx only queue init ramrod data
4607  */
4608 struct tx_queue_init_ramrod_data {
4609 	struct client_init_general_data general;
4610 	struct client_init_tx_data tx;
4611 };
4612 
4613 
4614 /*
4615  * Three RX producers for ETH
4616  */
4617 struct ustorm_eth_rx_producers {
4618 #if defined(__BIG_ENDIAN)
4619 	u16 bd_prod;
4620 	u16 cqe_prod;
4621 #elif defined(__LITTLE_ENDIAN)
4622 	u16 cqe_prod;
4623 	u16 bd_prod;
4624 #endif
4625 #if defined(__BIG_ENDIAN)
4626 	u16 reserved;
4627 	u16 sge_prod;
4628 #elif defined(__LITTLE_ENDIAN)
4629 	u16 sge_prod;
4630 	u16 reserved;
4631 #endif
4632 };
4633 
4634 
4635 /*
4636  * FCoE RX statistics parameters section#0
4637  */
4638 struct fcoe_rx_stat_params_section0 {
4639 	__le32 fcoe_rx_pkt_cnt;
4640 	__le32 fcoe_rx_byte_cnt;
4641 };
4642 
4643 
4644 /*
4645  * FCoE RX statistics parameters section#1
4646  */
4647 struct fcoe_rx_stat_params_section1 {
4648 	__le32 fcoe_ver_cnt;
4649 	__le32 fcoe_rx_drop_pkt_cnt;
4650 };
4651 
4652 
4653 /*
4654  * FCoE RX statistics parameters section#2
4655  */
4656 struct fcoe_rx_stat_params_section2 {
4657 	__le32 fc_crc_cnt;
4658 	__le32 eofa_del_cnt;
4659 	__le32 miss_frame_cnt;
4660 	__le32 seq_timeout_cnt;
4661 	__le32 drop_seq_cnt;
4662 	__le32 fcoe_rx_drop_pkt_cnt;
4663 	__le32 fcp_rx_pkt_cnt;
4664 	__le32 reserved0;
4665 };
4666 
4667 
4668 /*
4669  * FCoE TX statistics parameters
4670  */
4671 struct fcoe_tx_stat_params {
4672 	__le32 fcoe_tx_pkt_cnt;
4673 	__le32 fcoe_tx_byte_cnt;
4674 	__le32 fcp_tx_pkt_cnt;
4675 	__le32 reserved0;
4676 };
4677 
4678 /*
4679  * FCoE statistics parameters
4680  */
4681 struct fcoe_statistics_params {
4682 	struct fcoe_tx_stat_params tx_stat;
4683 	struct fcoe_rx_stat_params_section0 rx_stat0;
4684 	struct fcoe_rx_stat_params_section1 rx_stat1;
4685 	struct fcoe_rx_stat_params_section2 rx_stat2;
4686 };
4687 
4688 
4689 /*
4690  * The data afex vif list ramrod need
4691  */
4692 struct afex_vif_list_ramrod_data {
4693 	u8 afex_vif_list_command;
4694 	u8 func_bit_map;
4695 	__le16 vif_list_index;
4696 	u8 func_to_clear;
4697 	u8 echo;
4698 	__le16 reserved1;
4699 };
4700 
4701 
4702 /*
4703  * cfc delete event data
4704  */
4705 struct cfc_del_event_data {
4706 	u32 cid;
4707 	u32 reserved0;
4708 	u32 reserved1;
4709 };
4710 
4711 
4712 /*
4713  * per-port SAFC demo variables
4714  */
4715 struct cmng_flags_per_port {
4716 	u32 cmng_enables;
4717 #define CMNG_FLAGS_PER_PORT_FAIRNESS_VN (0x1<<0)
4718 #define CMNG_FLAGS_PER_PORT_FAIRNESS_VN_SHIFT 0
4719 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN (0x1<<1)
4720 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN_SHIFT 1
4721 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS (0x1<<2)
4722 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_SHIFT 2
4723 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE (0x1<<3)
4724 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE_SHIFT 3
4725 #define __CMNG_FLAGS_PER_PORT_RESERVED0 (0xFFFFFFF<<4)
4726 #define __CMNG_FLAGS_PER_PORT_RESERVED0_SHIFT 4
4727 	u32 __reserved1;
4728 };
4729 
4730 
4731 /*
4732  * per-port rate shaping variables
4733  */
4734 struct rate_shaping_vars_per_port {
4735 	u32 rs_periodic_timeout;
4736 	u32 rs_threshold;
4737 };
4738 
4739 /*
4740  * per-port fairness variables
4741  */
4742 struct fairness_vars_per_port {
4743 	u32 upper_bound;
4744 	u32 fair_threshold;
4745 	u32 fairness_timeout;
4746 	u32 reserved0;
4747 };
4748 
4749 /*
4750  * per-port SAFC variables
4751  */
4752 struct safc_struct_per_port {
4753 #if defined(__BIG_ENDIAN)
4754 	u16 __reserved1;
4755 	u8 __reserved0;
4756 	u8 safc_timeout_usec;
4757 #elif defined(__LITTLE_ENDIAN)
4758 	u8 safc_timeout_usec;
4759 	u8 __reserved0;
4760 	u16 __reserved1;
4761 #endif
4762 	u8 cos_to_traffic_types[MAX_COS_NUMBER];
4763 	u16 cos_to_pause_mask[NUM_OF_SAFC_BITS];
4764 };
4765 
4766 /*
4767  * Per-port congestion management variables
4768  */
4769 struct cmng_struct_per_port {
4770 	struct rate_shaping_vars_per_port rs_vars;
4771 	struct fairness_vars_per_port fair_vars;
4772 	struct safc_struct_per_port safc_vars;
4773 	struct cmng_flags_per_port flags;
4774 };
4775 
4776 /*
4777  * a single rate shaping counter. can be used as protocol or vnic counter
4778  */
4779 struct rate_shaping_counter {
4780 	u32 quota;
4781 #if defined(__BIG_ENDIAN)
4782 	u16 __reserved0;
4783 	u16 rate;
4784 #elif defined(__LITTLE_ENDIAN)
4785 	u16 rate;
4786 	u16 __reserved0;
4787 #endif
4788 };
4789 
4790 /*
4791  * per-vnic rate shaping variables
4792  */
4793 struct rate_shaping_vars_per_vn {
4794 	struct rate_shaping_counter vn_counter;
4795 };
4796 
4797 /*
4798  * per-vnic fairness variables
4799  */
4800 struct fairness_vars_per_vn {
4801 	u32 cos_credit_delta[MAX_COS_NUMBER];
4802 	u32 vn_credit_delta;
4803 	u32 __reserved0;
4804 };
4805 
4806 /*
4807  * cmng port init state
4808  */
4809 struct cmng_vnic {
4810 	struct rate_shaping_vars_per_vn vnic_max_rate[4];
4811 	struct fairness_vars_per_vn vnic_min_rate[4];
4812 };
4813 
4814 /*
4815  * cmng port init state
4816  */
4817 struct cmng_init {
4818 	struct cmng_struct_per_port port;
4819 	struct cmng_vnic vnic;
4820 };
4821 
4822 
4823 /*
4824  * driver parameters for congestion management init, all rates are in Mbps
4825  */
4826 struct cmng_init_input {
4827 	u32 port_rate;
4828 	u16 vnic_min_rate[4];
4829 	u16 vnic_max_rate[4];
4830 	u16 cos_min_rate[MAX_COS_NUMBER];
4831 	u16 cos_to_pause_mask[MAX_COS_NUMBER];
4832 	struct cmng_flags_per_port flags;
4833 };
4834 
4835 
4836 /*
4837  * Protocol-common command ID for slow path elements
4838  */
4839 enum common_spqe_cmd_id {
4840 	RAMROD_CMD_ID_COMMON_UNUSED,
4841 	RAMROD_CMD_ID_COMMON_FUNCTION_START,
4842 	RAMROD_CMD_ID_COMMON_FUNCTION_STOP,
4843 	RAMROD_CMD_ID_COMMON_FUNCTION_UPDATE,
4844 	RAMROD_CMD_ID_COMMON_CFC_DEL,
4845 	RAMROD_CMD_ID_COMMON_CFC_DEL_WB,
4846 	RAMROD_CMD_ID_COMMON_STAT_QUERY,
4847 	RAMROD_CMD_ID_COMMON_STOP_TRAFFIC,
4848 	RAMROD_CMD_ID_COMMON_START_TRAFFIC,
4849 	RAMROD_CMD_ID_COMMON_AFEX_VIF_LISTS,
4850 	RAMROD_CMD_ID_COMMON_SET_TIMESYNC,
4851 	MAX_COMMON_SPQE_CMD_ID
4852 };
4853 
4854 /*
4855  * Per-protocol connection types
4856  */
4857 enum connection_type {
4858 	ETH_CONNECTION_TYPE,
4859 	TOE_CONNECTION_TYPE,
4860 	RDMA_CONNECTION_TYPE,
4861 	ISCSI_CONNECTION_TYPE,
4862 	FCOE_CONNECTION_TYPE,
4863 	RESERVED_CONNECTION_TYPE_0,
4864 	RESERVED_CONNECTION_TYPE_1,
4865 	RESERVED_CONNECTION_TYPE_2,
4866 	NONE_CONNECTION_TYPE,
4867 	MAX_CONNECTION_TYPE
4868 };
4869 
4870 
4871 /*
4872  * Cos modes
4873  */
4874 enum cos_mode {
4875 	OVERRIDE_COS,
4876 	STATIC_COS,
4877 	FW_WRR,
4878 	MAX_COS_MODE
4879 };
4880 
4881 
4882 /*
4883  * Dynamic HC counters set by the driver
4884  */
4885 struct hc_dynamic_drv_counter {
4886 	u32 val[HC_SB_MAX_DYNAMIC_INDICES];
4887 };
4888 
4889 /*
4890  * zone A per-queue data
4891  */
4892 struct cstorm_queue_zone_data {
4893 	struct hc_dynamic_drv_counter hc_dyn_drv_cnt;
4894 	struct regpair reserved[2];
4895 };
4896 
4897 
4898 /*
4899  * Vf-PF channel data in cstorm ram (non-triggered zone)
4900  */
4901 struct vf_pf_channel_zone_data {
4902 	u32 msg_addr_lo;
4903 	u32 msg_addr_hi;
4904 };
4905 
4906 /*
4907  * zone for VF non-triggered data
4908  */
4909 struct non_trigger_vf_zone {
4910 	struct vf_pf_channel_zone_data vf_pf_channel;
4911 };
4912 
4913 /*
4914  * Vf-PF channel trigger zone in cstorm ram
4915  */
4916 struct vf_pf_channel_zone_trigger {
4917 	u8 addr_valid;
4918 };
4919 
4920 /*
4921  * zone that triggers the in-bound interrupt
4922  */
4923 struct trigger_vf_zone {
4924 #if defined(__BIG_ENDIAN)
4925 	u16 reserved1;
4926 	u8 reserved0;
4927 	struct vf_pf_channel_zone_trigger vf_pf_channel;
4928 #elif defined(__LITTLE_ENDIAN)
4929 	struct vf_pf_channel_zone_trigger vf_pf_channel;
4930 	u8 reserved0;
4931 	u16 reserved1;
4932 #endif
4933 	u32 reserved2;
4934 };
4935 
4936 /*
4937  * zone B per-VF data
4938  */
4939 struct cstorm_vf_zone_data {
4940 	struct non_trigger_vf_zone non_trigger;
4941 	struct trigger_vf_zone trigger;
4942 };
4943 
4944 
4945 /*
4946  * Dynamic host coalescing init parameters, per state machine
4947  */
4948 struct dynamic_hc_sm_config {
4949 	u32 threshold[3];
4950 	u8 shift_per_protocol[HC_SB_MAX_DYNAMIC_INDICES];
4951 	u8 hc_timeout0[HC_SB_MAX_DYNAMIC_INDICES];
4952 	u8 hc_timeout1[HC_SB_MAX_DYNAMIC_INDICES];
4953 	u8 hc_timeout2[HC_SB_MAX_DYNAMIC_INDICES];
4954 	u8 hc_timeout3[HC_SB_MAX_DYNAMIC_INDICES];
4955 };
4956 
4957 /*
4958  * Dynamic host coalescing init parameters
4959  */
4960 struct dynamic_hc_config {
4961 	struct dynamic_hc_sm_config sm_config[HC_SB_MAX_SM];
4962 };
4963 
4964 
4965 struct e2_integ_data {
4966 #if defined(__BIG_ENDIAN)
4967 	u8 flags;
4968 #define E2_INTEG_DATA_TESTING_EN (0x1<<0)
4969 #define E2_INTEG_DATA_TESTING_EN_SHIFT 0
4970 #define E2_INTEG_DATA_LB_TX (0x1<<1)
4971 #define E2_INTEG_DATA_LB_TX_SHIFT 1
4972 #define E2_INTEG_DATA_COS_TX (0x1<<2)
4973 #define E2_INTEG_DATA_COS_TX_SHIFT 2
4974 #define E2_INTEG_DATA_OPPORTUNISTICQM (0x1<<3)
4975 #define E2_INTEG_DATA_OPPORTUNISTICQM_SHIFT 3
4976 #define E2_INTEG_DATA_DPMTESTRELEASEDQ (0x1<<4)
4977 #define E2_INTEG_DATA_DPMTESTRELEASEDQ_SHIFT 4
4978 #define E2_INTEG_DATA_RESERVED (0x7<<5)
4979 #define E2_INTEG_DATA_RESERVED_SHIFT 5
4980 	u8 cos;
4981 	u8 voq;
4982 	u8 pbf_queue;
4983 #elif defined(__LITTLE_ENDIAN)
4984 	u8 pbf_queue;
4985 	u8 voq;
4986 	u8 cos;
4987 	u8 flags;
4988 #define E2_INTEG_DATA_TESTING_EN (0x1<<0)
4989 #define E2_INTEG_DATA_TESTING_EN_SHIFT 0
4990 #define E2_INTEG_DATA_LB_TX (0x1<<1)
4991 #define E2_INTEG_DATA_LB_TX_SHIFT 1
4992 #define E2_INTEG_DATA_COS_TX (0x1<<2)
4993 #define E2_INTEG_DATA_COS_TX_SHIFT 2
4994 #define E2_INTEG_DATA_OPPORTUNISTICQM (0x1<<3)
4995 #define E2_INTEG_DATA_OPPORTUNISTICQM_SHIFT 3
4996 #define E2_INTEG_DATA_DPMTESTRELEASEDQ (0x1<<4)
4997 #define E2_INTEG_DATA_DPMTESTRELEASEDQ_SHIFT 4
4998 #define E2_INTEG_DATA_RESERVED (0x7<<5)
4999 #define E2_INTEG_DATA_RESERVED_SHIFT 5
5000 #endif
5001 #if defined(__BIG_ENDIAN)
5002 	u16 reserved3;
5003 	u8 reserved2;
5004 	u8 ramEn;
5005 #elif defined(__LITTLE_ENDIAN)
5006 	u8 ramEn;
5007 	u8 reserved2;
5008 	u16 reserved3;
5009 #endif
5010 };
5011 
5012 
5013 /*
5014  * set mac event data
5015  */
5016 struct eth_event_data {
5017 	u32 echo;
5018 	u32 reserved0;
5019 	u32 reserved1;
5020 };
5021 
5022 
5023 /*
5024  * pf-vf event data
5025  */
5026 struct vf_pf_event_data {
5027 	u8 vf_id;
5028 	u8 reserved0;
5029 	u16 reserved1;
5030 	u32 msg_addr_lo;
5031 	u32 msg_addr_hi;
5032 };
5033 
5034 /*
5035  * VF FLR event data
5036  */
5037 struct vf_flr_event_data {
5038 	u8 vf_id;
5039 	u8 reserved0;
5040 	u16 reserved1;
5041 	u32 reserved2;
5042 	u32 reserved3;
5043 };
5044 
5045 /*
5046  * malicious VF event data
5047  */
5048 struct malicious_vf_event_data {
5049 	u8 vf_id;
5050 	u8 err_id;
5051 	u16 reserved1;
5052 	u32 reserved2;
5053 	u32 reserved3;
5054 };
5055 
5056 /*
5057  * vif list event data
5058  */
5059 struct vif_list_event_data {
5060 	u8 func_bit_map;
5061 	u8 echo;
5062 	__le16 reserved0;
5063 	__le32 reserved1;
5064 	__le32 reserved2;
5065 };
5066 
5067 /* function update event data */
5068 struct function_update_event_data {
5069 	u8 echo;
5070 	u8 reserved;
5071 	__le16 reserved0;
5072 	__le32 reserved1;
5073 	__le32 reserved2;
5074 };
5075 
5076 
5077 /* union for all event ring message types */
5078 union event_data {
5079 	struct vf_pf_event_data vf_pf_event;
5080 	struct eth_event_data eth_event;
5081 	struct cfc_del_event_data cfc_del_event;
5082 	struct vf_flr_event_data vf_flr_event;
5083 	struct malicious_vf_event_data malicious_vf_event;
5084 	struct vif_list_event_data vif_list_event;
5085 	struct function_update_event_data function_update_event;
5086 };
5087 
5088 
5089 /*
5090  * per PF event ring data
5091  */
5092 struct event_ring_data {
5093 	struct regpair_native base_addr;
5094 #if defined(__BIG_ENDIAN)
5095 	u8 index_id;
5096 	u8 sb_id;
5097 	u16 producer;
5098 #elif defined(__LITTLE_ENDIAN)
5099 	u16 producer;
5100 	u8 sb_id;
5101 	u8 index_id;
5102 #endif
5103 	u32 reserved0;
5104 };
5105 
5106 
5107 /*
5108  * event ring message element (each element is 128 bits)
5109  */
5110 struct event_ring_msg {
5111 	u8 opcode;
5112 	u8 error;
5113 	u16 reserved1;
5114 	union event_data data;
5115 };
5116 
5117 /*
5118  * event ring next page element (128 bits)
5119  */
5120 struct event_ring_next {
5121 	struct regpair addr;
5122 	u32 reserved[2];
5123 };
5124 
5125 /*
5126  * union for event ring element types (each element is 128 bits)
5127  */
5128 union event_ring_elem {
5129 	struct event_ring_msg message;
5130 	struct event_ring_next next_page;
5131 };
5132 
5133 
5134 /*
5135  * Common event ring opcodes
5136  */
5137 enum event_ring_opcode {
5138 	EVENT_RING_OPCODE_VF_PF_CHANNEL,
5139 	EVENT_RING_OPCODE_FUNCTION_START,
5140 	EVENT_RING_OPCODE_FUNCTION_STOP,
5141 	EVENT_RING_OPCODE_CFC_DEL,
5142 	EVENT_RING_OPCODE_CFC_DEL_WB,
5143 	EVENT_RING_OPCODE_STAT_QUERY,
5144 	EVENT_RING_OPCODE_STOP_TRAFFIC,
5145 	EVENT_RING_OPCODE_START_TRAFFIC,
5146 	EVENT_RING_OPCODE_VF_FLR,
5147 	EVENT_RING_OPCODE_MALICIOUS_VF,
5148 	EVENT_RING_OPCODE_FORWARD_SETUP,
5149 	EVENT_RING_OPCODE_RSS_UPDATE_RULES,
5150 	EVENT_RING_OPCODE_FUNCTION_UPDATE,
5151 	EVENT_RING_OPCODE_AFEX_VIF_LISTS,
5152 	EVENT_RING_OPCODE_SET_MAC,
5153 	EVENT_RING_OPCODE_CLASSIFICATION_RULES,
5154 	EVENT_RING_OPCODE_FILTERS_RULES,
5155 	EVENT_RING_OPCODE_MULTICAST_RULES,
5156 	EVENT_RING_OPCODE_SET_TIMESYNC,
5157 	MAX_EVENT_RING_OPCODE
5158 };
5159 
5160 /*
5161  * Modes for fairness algorithm
5162  */
5163 enum fairness_mode {
5164 	FAIRNESS_COS_WRR_MODE,
5165 	FAIRNESS_COS_ETS_MODE,
5166 	MAX_FAIRNESS_MODE
5167 };
5168 
5169 
5170 /*
5171  * Priority and cos
5172  */
5173 struct priority_cos {
5174 	u8 priority;
5175 	u8 cos;
5176 	__le16 reserved1;
5177 };
5178 
5179 /*
5180  * The data for flow control configuration
5181  */
5182 struct flow_control_configuration {
5183 	struct priority_cos traffic_type_to_priority_cos[MAX_TRAFFIC_TYPES];
5184 	u8 dcb_enabled;
5185 	u8 dcb_version;
5186 	u8 dont_add_pri_0_en;
5187 	u8 reserved1;
5188 	__le32 reserved2;
5189 };
5190 
5191 
5192 /*
5193  *
5194  */
5195 struct function_start_data {
5196 	u8 function_mode;
5197 	u8 allow_npar_tx_switching;
5198 	__le16 sd_vlan_tag;
5199 	__le16 vif_id;
5200 	u8 path_id;
5201 	u8 network_cos_mode;
5202 	u8 dmae_cmd_id;
5203 	u8 gre_tunnel_mode;
5204 	u8 gre_tunnel_rss;
5205 	u8 nvgre_clss_en;
5206 	__le16 reserved1[2];
5207 };
5208 
5209 struct function_update_data {
5210 	u8 vif_id_change_flg;
5211 	u8 afex_default_vlan_change_flg;
5212 	u8 allowed_priorities_change_flg;
5213 	u8 network_cos_mode_change_flg;
5214 	__le16 vif_id;
5215 	__le16 afex_default_vlan;
5216 	u8 allowed_priorities;
5217 	u8 network_cos_mode;
5218 	u8 lb_mode_en_change_flg;
5219 	u8 lb_mode_en;
5220 	u8 tx_switch_suspend_change_flg;
5221 	u8 tx_switch_suspend;
5222 	u8 echo;
5223 	u8 reserved1;
5224 	u8 update_gre_cfg_flg;
5225 	u8 gre_tunnel_mode;
5226 	u8 gre_tunnel_rss;
5227 	u8 nvgre_clss_en;
5228 	u32 reserved3;
5229 };
5230 
5231 /*
5232  * FW version stored in the Xstorm RAM
5233  */
5234 struct fw_version {
5235 #if defined(__BIG_ENDIAN)
5236 	u8 engineering;
5237 	u8 revision;
5238 	u8 minor;
5239 	u8 major;
5240 #elif defined(__LITTLE_ENDIAN)
5241 	u8 major;
5242 	u8 minor;
5243 	u8 revision;
5244 	u8 engineering;
5245 #endif
5246 	u32 flags;
5247 #define FW_VERSION_OPTIMIZED (0x1<<0)
5248 #define FW_VERSION_OPTIMIZED_SHIFT 0
5249 #define FW_VERSION_BIG_ENDIEN (0x1<<1)
5250 #define FW_VERSION_BIG_ENDIEN_SHIFT 1
5251 #define FW_VERSION_CHIP_VERSION (0x3<<2)
5252 #define FW_VERSION_CHIP_VERSION_SHIFT 2
5253 #define __FW_VERSION_RESERVED (0xFFFFFFF<<4)
5254 #define __FW_VERSION_RESERVED_SHIFT 4
5255 };
5256 
5257 /* GRE RSS Mode */
5258 enum gre_rss_mode {
5259 	GRE_OUTER_HEADERS_RSS,
5260 	GRE_INNER_HEADERS_RSS,
5261 	NVGRE_KEY_ENTROPY_RSS,
5262 	MAX_GRE_RSS_MODE
5263 };
5264 
5265 /* GRE Tunnel Mode */
5266 enum gre_tunnel_type {
5267 	NO_GRE_TUNNEL,
5268 	NVGRE_TUNNEL,
5269 	L2GRE_TUNNEL,
5270 	IPGRE_TUNNEL,
5271 	MAX_GRE_TUNNEL_TYPE
5272 };
5273 
5274 /*
5275  * Dynamic Host-Coalescing - Driver(host) counters
5276  */
5277 struct hc_dynamic_sb_drv_counters {
5278 	u32 dynamic_hc_drv_counter[HC_SB_MAX_DYNAMIC_INDICES];
5279 };
5280 
5281 
5282 /*
5283  * 2 bytes. configuration/state parameters for a single protocol index
5284  */
5285 struct hc_index_data {
5286 #if defined(__BIG_ENDIAN)
5287 	u8 flags;
5288 #define HC_INDEX_DATA_SM_ID (0x1<<0)
5289 #define HC_INDEX_DATA_SM_ID_SHIFT 0
5290 #define HC_INDEX_DATA_HC_ENABLED (0x1<<1)
5291 #define HC_INDEX_DATA_HC_ENABLED_SHIFT 1
5292 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2)
5293 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2
5294 #define HC_INDEX_DATA_RESERVE (0x1F<<3)
5295 #define HC_INDEX_DATA_RESERVE_SHIFT 3
5296 	u8 timeout;
5297 #elif defined(__LITTLE_ENDIAN)
5298 	u8 timeout;
5299 	u8 flags;
5300 #define HC_INDEX_DATA_SM_ID (0x1<<0)
5301 #define HC_INDEX_DATA_SM_ID_SHIFT 0
5302 #define HC_INDEX_DATA_HC_ENABLED (0x1<<1)
5303 #define HC_INDEX_DATA_HC_ENABLED_SHIFT 1
5304 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2)
5305 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2
5306 #define HC_INDEX_DATA_RESERVE (0x1F<<3)
5307 #define HC_INDEX_DATA_RESERVE_SHIFT 3
5308 #endif
5309 };
5310 
5311 
5312 /*
5313  * HC state-machine
5314  */
5315 struct hc_status_block_sm {
5316 #if defined(__BIG_ENDIAN)
5317 	u8 igu_seg_id;
5318 	u8 igu_sb_id;
5319 	u8 timer_value;
5320 	u8 __flags;
5321 #elif defined(__LITTLE_ENDIAN)
5322 	u8 __flags;
5323 	u8 timer_value;
5324 	u8 igu_sb_id;
5325 	u8 igu_seg_id;
5326 #endif
5327 	u32 time_to_expire;
5328 };
5329 
5330 /*
5331  * hold PCI identification variables- used in various places in firmware
5332  */
5333 struct pci_entity {
5334 #if defined(__BIG_ENDIAN)
5335 	u8 vf_valid;
5336 	u8 vf_id;
5337 	u8 vnic_id;
5338 	u8 pf_id;
5339 #elif defined(__LITTLE_ENDIAN)
5340 	u8 pf_id;
5341 	u8 vnic_id;
5342 	u8 vf_id;
5343 	u8 vf_valid;
5344 #endif
5345 };
5346 
5347 /*
5348  * The fast-path status block meta-data, common to all chips
5349  */
5350 struct hc_sb_data {
5351 	struct regpair_native host_sb_addr;
5352 	struct hc_status_block_sm state_machine[HC_SB_MAX_SM];
5353 	struct pci_entity p_func;
5354 #if defined(__BIG_ENDIAN)
5355 	u8 rsrv0;
5356 	u8 state;
5357 	u8 dhc_qzone_id;
5358 	u8 same_igu_sb_1b;
5359 #elif defined(__LITTLE_ENDIAN)
5360 	u8 same_igu_sb_1b;
5361 	u8 dhc_qzone_id;
5362 	u8 state;
5363 	u8 rsrv0;
5364 #endif
5365 	struct regpair_native rsrv1[2];
5366 };
5367 
5368 
5369 /*
5370  * Segment types for host coaslescing
5371  */
5372 enum hc_segment {
5373 	HC_REGULAR_SEGMENT,
5374 	HC_DEFAULT_SEGMENT,
5375 	MAX_HC_SEGMENT
5376 };
5377 
5378 
5379 /*
5380  * The fast-path status block meta-data
5381  */
5382 struct hc_sp_status_block_data {
5383 	struct regpair_native host_sb_addr;
5384 #if defined(__BIG_ENDIAN)
5385 	u8 rsrv1;
5386 	u8 state;
5387 	u8 igu_seg_id;
5388 	u8 igu_sb_id;
5389 #elif defined(__LITTLE_ENDIAN)
5390 	u8 igu_sb_id;
5391 	u8 igu_seg_id;
5392 	u8 state;
5393 	u8 rsrv1;
5394 #endif
5395 	struct pci_entity p_func;
5396 };
5397 
5398 
5399 /*
5400  * The fast-path status block meta-data
5401  */
5402 struct hc_status_block_data_e1x {
5403 	struct hc_index_data index_data[HC_SB_MAX_INDICES_E1X];
5404 	struct hc_sb_data common;
5405 };
5406 
5407 
5408 /*
5409  * The fast-path status block meta-data
5410  */
5411 struct hc_status_block_data_e2 {
5412 	struct hc_index_data index_data[HC_SB_MAX_INDICES_E2];
5413 	struct hc_sb_data common;
5414 };
5415 
5416 
5417 /*
5418  * IGU block operartion modes (in Everest2)
5419  */
5420 enum igu_mode {
5421 	HC_IGU_BC_MODE,
5422 	HC_IGU_NBC_MODE,
5423 	MAX_IGU_MODE
5424 };
5425 
5426 
5427 /*
5428  * IP versions
5429  */
5430 enum ip_ver {
5431 	IP_V4,
5432 	IP_V6,
5433 	MAX_IP_VER
5434 };
5435 
5436 /*
5437  * Malicious VF error ID
5438  */
5439 enum malicious_vf_error_id {
5440 	VF_PF_CHANNEL_NOT_READY,
5441 	ETH_ILLEGAL_BD_LENGTHS,
5442 	ETH_PACKET_TOO_SHORT,
5443 	ETH_PAYLOAD_TOO_BIG,
5444 	ETH_ILLEGAL_ETH_TYPE,
5445 	ETH_ILLEGAL_LSO_HDR_LEN,
5446 	ETH_TOO_MANY_BDS,
5447 	ETH_ZERO_HDR_NBDS,
5448 	ETH_START_BD_NOT_SET,
5449 	ETH_ILLEGAL_PARSE_NBDS,
5450 	ETH_IPV6_AND_CHECKSUM,
5451 	ETH_VLAN_FLG_INCORRECT,
5452 	ETH_ILLEGAL_LSO_MSS,
5453 	ETH_TUNNEL_NOT_SUPPORTED,
5454 	MAX_MALICIOUS_VF_ERROR_ID
5455 };
5456 
5457 /*
5458  * Multi-function modes
5459  */
5460 enum mf_mode {
5461 	SINGLE_FUNCTION,
5462 	MULTI_FUNCTION_SD,
5463 	MULTI_FUNCTION_SI,
5464 	MULTI_FUNCTION_AFEX,
5465 	MAX_MF_MODE
5466 };
5467 
5468 /*
5469  * Protocol-common statistics collected by the Tstorm (per pf)
5470  */
5471 struct tstorm_per_pf_stats {
5472 	struct regpair rcv_error_bytes;
5473 };
5474 
5475 /*
5476  *
5477  */
5478 struct per_pf_stats {
5479 	struct tstorm_per_pf_stats tstorm_pf_statistics;
5480 };
5481 
5482 
5483 /*
5484  * Protocol-common statistics collected by the Tstorm (per port)
5485  */
5486 struct tstorm_per_port_stats {
5487 	__le32 mac_discard;
5488 	__le32 mac_filter_discard;
5489 	__le32 brb_truncate_discard;
5490 	__le32 mf_tag_discard;
5491 	__le32 packet_drop;
5492 	__le32 reserved;
5493 };
5494 
5495 /*
5496  *
5497  */
5498 struct per_port_stats {
5499 	struct tstorm_per_port_stats tstorm_port_statistics;
5500 };
5501 
5502 
5503 /*
5504  * Protocol-common statistics collected by the Tstorm (per client)
5505  */
5506 struct tstorm_per_queue_stats {
5507 	struct regpair rcv_ucast_bytes;
5508 	__le32 rcv_ucast_pkts;
5509 	__le32 checksum_discard;
5510 	struct regpair rcv_bcast_bytes;
5511 	__le32 rcv_bcast_pkts;
5512 	__le32 pkts_too_big_discard;
5513 	struct regpair rcv_mcast_bytes;
5514 	__le32 rcv_mcast_pkts;
5515 	__le32 ttl0_discard;
5516 	__le16 no_buff_discard;
5517 	__le16 reserved0;
5518 	__le32 reserved1;
5519 };
5520 
5521 /*
5522  * Protocol-common statistics collected by the Ustorm (per client)
5523  */
5524 struct ustorm_per_queue_stats {
5525 	struct regpair ucast_no_buff_bytes;
5526 	struct regpair mcast_no_buff_bytes;
5527 	struct regpair bcast_no_buff_bytes;
5528 	__le32 ucast_no_buff_pkts;
5529 	__le32 mcast_no_buff_pkts;
5530 	__le32 bcast_no_buff_pkts;
5531 	__le32 coalesced_pkts;
5532 	struct regpair coalesced_bytes;
5533 	__le32 coalesced_events;
5534 	__le32 coalesced_aborts;
5535 };
5536 
5537 /*
5538  * Protocol-common statistics collected by the Xstorm (per client)
5539  */
5540 struct xstorm_per_queue_stats {
5541 	struct regpair ucast_bytes_sent;
5542 	struct regpair mcast_bytes_sent;
5543 	struct regpair bcast_bytes_sent;
5544 	__le32 ucast_pkts_sent;
5545 	__le32 mcast_pkts_sent;
5546 	__le32 bcast_pkts_sent;
5547 	__le32 error_drop_pkts;
5548 };
5549 
5550 /*
5551  *
5552  */
5553 struct per_queue_stats {
5554 	struct tstorm_per_queue_stats tstorm_queue_statistics;
5555 	struct ustorm_per_queue_stats ustorm_queue_statistics;
5556 	struct xstorm_per_queue_stats xstorm_queue_statistics;
5557 };
5558 
5559 
5560 /*
5561  * FW version stored in first line of pram
5562  */
5563 struct pram_fw_version {
5564 	u8 major;
5565 	u8 minor;
5566 	u8 revision;
5567 	u8 engineering;
5568 	u8 flags;
5569 #define PRAM_FW_VERSION_OPTIMIZED (0x1<<0)
5570 #define PRAM_FW_VERSION_OPTIMIZED_SHIFT 0
5571 #define PRAM_FW_VERSION_STORM_ID (0x3<<1)
5572 #define PRAM_FW_VERSION_STORM_ID_SHIFT 1
5573 #define PRAM_FW_VERSION_BIG_ENDIEN (0x1<<3)
5574 #define PRAM_FW_VERSION_BIG_ENDIEN_SHIFT 3
5575 #define PRAM_FW_VERSION_CHIP_VERSION (0x3<<4)
5576 #define PRAM_FW_VERSION_CHIP_VERSION_SHIFT 4
5577 #define __PRAM_FW_VERSION_RESERVED0 (0x3<<6)
5578 #define __PRAM_FW_VERSION_RESERVED0_SHIFT 6
5579 };
5580 
5581 
5582 /*
5583  * Ethernet slow path element
5584  */
5585 union protocol_common_specific_data {
5586 	u8 protocol_data[8];
5587 	struct regpair phy_address;
5588 	struct regpair mac_config_addr;
5589 	struct afex_vif_list_ramrod_data afex_vif_list_data;
5590 };
5591 
5592 /*
5593  * The send queue element
5594  */
5595 struct protocol_common_spe {
5596 	struct spe_hdr hdr;
5597 	union protocol_common_specific_data data;
5598 };
5599 
5600 /*
5601  * The send queue element
5602  */
5603 struct slow_path_element {
5604 	struct spe_hdr hdr;
5605 	struct regpair protocol_data;
5606 };
5607 
5608 
5609 /*
5610  * Protocol-common statistics counter
5611  */
5612 struct stats_counter {
5613 	__le16 xstats_counter;
5614 	__le16 reserved0;
5615 	__le32 reserved1;
5616 	__le16 tstats_counter;
5617 	__le16 reserved2;
5618 	__le32 reserved3;
5619 	__le16 ustats_counter;
5620 	__le16 reserved4;
5621 	__le32 reserved5;
5622 	__le16 cstats_counter;
5623 	__le16 reserved6;
5624 	__le32 reserved7;
5625 };
5626 
5627 
5628 /*
5629  *
5630  */
5631 struct stats_query_entry {
5632 	u8 kind;
5633 	u8 index;
5634 	__le16 funcID;
5635 	__le32 reserved;
5636 	struct regpair address;
5637 };
5638 
5639 /*
5640  * statistic command
5641  */
5642 struct stats_query_cmd_group {
5643 	struct stats_query_entry query[STATS_QUERY_CMD_COUNT];
5644 };
5645 
5646 
5647 /*
5648  * statistic command header
5649  */
5650 struct stats_query_header {
5651 	u8 cmd_num;
5652 	u8 reserved0;
5653 	__le16 drv_stats_counter;
5654 	__le32 reserved1;
5655 	struct regpair stats_counters_addrs;
5656 };
5657 
5658 
5659 /*
5660  * Types of statistcis query entry
5661  */
5662 enum stats_query_type {
5663 	STATS_TYPE_QUEUE,
5664 	STATS_TYPE_PORT,
5665 	STATS_TYPE_PF,
5666 	STATS_TYPE_TOE,
5667 	STATS_TYPE_FCOE,
5668 	MAX_STATS_QUERY_TYPE
5669 };
5670 
5671 
5672 /*
5673  * Indicate of the function status block state
5674  */
5675 enum status_block_state {
5676 	SB_DISABLED,
5677 	SB_ENABLED,
5678 	SB_CLEANED,
5679 	MAX_STATUS_BLOCK_STATE
5680 };
5681 
5682 
5683 /*
5684  * Storm IDs (including attentions for IGU related enums)
5685  */
5686 enum storm_id {
5687 	USTORM_ID,
5688 	CSTORM_ID,
5689 	XSTORM_ID,
5690 	TSTORM_ID,
5691 	ATTENTION_ID,
5692 	MAX_STORM_ID
5693 };
5694 
5695 
5696 /*
5697  * Taffic types used in ETS and flow control algorithms
5698  */
5699 enum traffic_type {
5700 	LLFC_TRAFFIC_TYPE_NW,
5701 	LLFC_TRAFFIC_TYPE_FCOE,
5702 	LLFC_TRAFFIC_TYPE_ISCSI,
5703 	MAX_TRAFFIC_TYPE
5704 };
5705 
5706 
5707 /*
5708  * zone A per-queue data
5709  */
5710 struct tstorm_queue_zone_data {
5711 	struct regpair reserved[4];
5712 };
5713 
5714 
5715 /*
5716  * zone B per-VF data
5717  */
5718 struct tstorm_vf_zone_data {
5719 	struct regpair reserved;
5720 };
5721 
5722 
5723 /*
5724  * zone A per-queue data
5725  */
5726 struct ustorm_queue_zone_data {
5727 	struct ustorm_eth_rx_producers eth_rx_producers;
5728 	struct regpair reserved[3];
5729 };
5730 
5731 
5732 /*
5733  * zone B per-VF data
5734  */
5735 struct ustorm_vf_zone_data {
5736 	struct regpair reserved;
5737 };
5738 
5739 
5740 /*
5741  * data per VF-PF channel
5742  */
5743 struct vf_pf_channel_data {
5744 #if defined(__BIG_ENDIAN)
5745 	u16 reserved0;
5746 	u8 valid;
5747 	u8 state;
5748 #elif defined(__LITTLE_ENDIAN)
5749 	u8 state;
5750 	u8 valid;
5751 	u16 reserved0;
5752 #endif
5753 	u32 reserved1;
5754 };
5755 
5756 
5757 /*
5758  * State of VF-PF channel
5759  */
5760 enum vf_pf_channel_state {
5761 	VF_PF_CHANNEL_STATE_READY,
5762 	VF_PF_CHANNEL_STATE_WAITING_FOR_ACK,
5763 	MAX_VF_PF_CHANNEL_STATE
5764 };
5765 
5766 
5767 /*
5768  * vif_list_rule_kind
5769  */
5770 enum vif_list_rule_kind {
5771 	VIF_LIST_RULE_SET,
5772 	VIF_LIST_RULE_GET,
5773 	VIF_LIST_RULE_CLEAR_ALL,
5774 	VIF_LIST_RULE_CLEAR_FUNC,
5775 	MAX_VIF_LIST_RULE_KIND
5776 };
5777 
5778 
5779 /*
5780  * zone A per-queue data
5781  */
5782 struct xstorm_queue_zone_data {
5783 	struct regpair reserved[4];
5784 };
5785 
5786 
5787 /*
5788  * zone B per-VF data
5789  */
5790 struct xstorm_vf_zone_data {
5791 	struct regpair reserved;
5792 };
5793 
5794 #endif /* BNX2X_HSI_H */
5795