1 /* bnx2x_hsi.h: Broadcom Everest network driver. 2 * 3 * Copyright (c) 2007-2012 Broadcom Corporation 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation. 8 */ 9 #ifndef BNX2X_HSI_H 10 #define BNX2X_HSI_H 11 12 #include "bnx2x_fw_defs.h" 13 #include "bnx2x_mfw_req.h" 14 15 #define FW_ENCODE_32BIT_PATTERN 0x1e1e1e1e 16 17 struct license_key { 18 u32 reserved[6]; 19 20 u32 max_iscsi_conn; 21 #define BNX2X_MAX_ISCSI_TRGT_CONN_MASK 0xFFFF 22 #define BNX2X_MAX_ISCSI_TRGT_CONN_SHIFT 0 23 #define BNX2X_MAX_ISCSI_INIT_CONN_MASK 0xFFFF0000 24 #define BNX2X_MAX_ISCSI_INIT_CONN_SHIFT 16 25 26 u32 reserved_a; 27 28 u32 max_fcoe_conn; 29 #define BNX2X_MAX_FCOE_TRGT_CONN_MASK 0xFFFF 30 #define BNX2X_MAX_FCOE_TRGT_CONN_SHIFT 0 31 #define BNX2X_MAX_FCOE_INIT_CONN_MASK 0xFFFF0000 32 #define BNX2X_MAX_FCOE_INIT_CONN_SHIFT 16 33 34 u32 reserved_b[4]; 35 }; 36 37 /**************************************************************************** 38 * Shared HW configuration * 39 ****************************************************************************/ 40 #define PIN_CFG_NA 0x00000000 41 #define PIN_CFG_GPIO0_P0 0x00000001 42 #define PIN_CFG_GPIO1_P0 0x00000002 43 #define PIN_CFG_GPIO2_P0 0x00000003 44 #define PIN_CFG_GPIO3_P0 0x00000004 45 #define PIN_CFG_GPIO0_P1 0x00000005 46 #define PIN_CFG_GPIO1_P1 0x00000006 47 #define PIN_CFG_GPIO2_P1 0x00000007 48 #define PIN_CFG_GPIO3_P1 0x00000008 49 #define PIN_CFG_EPIO0 0x00000009 50 #define PIN_CFG_EPIO1 0x0000000a 51 #define PIN_CFG_EPIO2 0x0000000b 52 #define PIN_CFG_EPIO3 0x0000000c 53 #define PIN_CFG_EPIO4 0x0000000d 54 #define PIN_CFG_EPIO5 0x0000000e 55 #define PIN_CFG_EPIO6 0x0000000f 56 #define PIN_CFG_EPIO7 0x00000010 57 #define PIN_CFG_EPIO8 0x00000011 58 #define PIN_CFG_EPIO9 0x00000012 59 #define PIN_CFG_EPIO10 0x00000013 60 #define PIN_CFG_EPIO11 0x00000014 61 #define PIN_CFG_EPIO12 0x00000015 62 #define PIN_CFG_EPIO13 0x00000016 63 #define PIN_CFG_EPIO14 0x00000017 64 #define PIN_CFG_EPIO15 0x00000018 65 #define PIN_CFG_EPIO16 0x00000019 66 #define PIN_CFG_EPIO17 0x0000001a 67 #define PIN_CFG_EPIO18 0x0000001b 68 #define PIN_CFG_EPIO19 0x0000001c 69 #define PIN_CFG_EPIO20 0x0000001d 70 #define PIN_CFG_EPIO21 0x0000001e 71 #define PIN_CFG_EPIO22 0x0000001f 72 #define PIN_CFG_EPIO23 0x00000020 73 #define PIN_CFG_EPIO24 0x00000021 74 #define PIN_CFG_EPIO25 0x00000022 75 #define PIN_CFG_EPIO26 0x00000023 76 #define PIN_CFG_EPIO27 0x00000024 77 #define PIN_CFG_EPIO28 0x00000025 78 #define PIN_CFG_EPIO29 0x00000026 79 #define PIN_CFG_EPIO30 0x00000027 80 #define PIN_CFG_EPIO31 0x00000028 81 82 /* EPIO definition */ 83 #define EPIO_CFG_NA 0x00000000 84 #define EPIO_CFG_EPIO0 0x00000001 85 #define EPIO_CFG_EPIO1 0x00000002 86 #define EPIO_CFG_EPIO2 0x00000003 87 #define EPIO_CFG_EPIO3 0x00000004 88 #define EPIO_CFG_EPIO4 0x00000005 89 #define EPIO_CFG_EPIO5 0x00000006 90 #define EPIO_CFG_EPIO6 0x00000007 91 #define EPIO_CFG_EPIO7 0x00000008 92 #define EPIO_CFG_EPIO8 0x00000009 93 #define EPIO_CFG_EPIO9 0x0000000a 94 #define EPIO_CFG_EPIO10 0x0000000b 95 #define EPIO_CFG_EPIO11 0x0000000c 96 #define EPIO_CFG_EPIO12 0x0000000d 97 #define EPIO_CFG_EPIO13 0x0000000e 98 #define EPIO_CFG_EPIO14 0x0000000f 99 #define EPIO_CFG_EPIO15 0x00000010 100 #define EPIO_CFG_EPIO16 0x00000011 101 #define EPIO_CFG_EPIO17 0x00000012 102 #define EPIO_CFG_EPIO18 0x00000013 103 #define EPIO_CFG_EPIO19 0x00000014 104 #define EPIO_CFG_EPIO20 0x00000015 105 #define EPIO_CFG_EPIO21 0x00000016 106 #define EPIO_CFG_EPIO22 0x00000017 107 #define EPIO_CFG_EPIO23 0x00000018 108 #define EPIO_CFG_EPIO24 0x00000019 109 #define EPIO_CFG_EPIO25 0x0000001a 110 #define EPIO_CFG_EPIO26 0x0000001b 111 #define EPIO_CFG_EPIO27 0x0000001c 112 #define EPIO_CFG_EPIO28 0x0000001d 113 #define EPIO_CFG_EPIO29 0x0000001e 114 #define EPIO_CFG_EPIO30 0x0000001f 115 #define EPIO_CFG_EPIO31 0x00000020 116 117 118 struct shared_hw_cfg { /* NVRAM Offset */ 119 /* Up to 16 bytes of NULL-terminated string */ 120 u8 part_num[16]; /* 0x104 */ 121 122 u32 config; /* 0x114 */ 123 #define SHARED_HW_CFG_MDIO_VOLTAGE_MASK 0x00000001 124 #define SHARED_HW_CFG_MDIO_VOLTAGE_SHIFT 0 125 #define SHARED_HW_CFG_MDIO_VOLTAGE_1_2V 0x00000000 126 #define SHARED_HW_CFG_MDIO_VOLTAGE_2_5V 0x00000001 127 #define SHARED_HW_CFG_MCP_RST_ON_CORE_RST_EN 0x00000002 128 129 #define SHARED_HW_CFG_PORT_SWAP 0x00000004 130 131 #define SHARED_HW_CFG_BEACON_WOL_EN 0x00000008 132 133 #define SHARED_HW_CFG_PCIE_GEN3_DISABLED 0x00000000 134 #define SHARED_HW_CFG_PCIE_GEN3_ENABLED 0x00000010 135 136 #define SHARED_HW_CFG_MFW_SELECT_MASK 0x00000700 137 #define SHARED_HW_CFG_MFW_SELECT_SHIFT 8 138 /* Whatever MFW found in NVM 139 (if multiple found, priority order is: NC-SI, UMP, IPMI) */ 140 #define SHARED_HW_CFG_MFW_SELECT_DEFAULT 0x00000000 141 #define SHARED_HW_CFG_MFW_SELECT_NC_SI 0x00000100 142 #define SHARED_HW_CFG_MFW_SELECT_UMP 0x00000200 143 #define SHARED_HW_CFG_MFW_SELECT_IPMI 0x00000300 144 /* Use SPIO4 as an arbiter between: 0-NC_SI, 1-IPMI 145 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */ 146 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_IPMI 0x00000400 147 /* Use SPIO4 as an arbiter between: 0-UMP, 1-IPMI 148 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */ 149 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_UMP_IPMI 0x00000500 150 /* Use SPIO4 as an arbiter between: 0-NC-SI, 1-UMP 151 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */ 152 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_UMP 0x00000600 153 154 #define SHARED_HW_CFG_LED_MODE_MASK 0x000f0000 155 #define SHARED_HW_CFG_LED_MODE_SHIFT 16 156 #define SHARED_HW_CFG_LED_MAC1 0x00000000 157 #define SHARED_HW_CFG_LED_PHY1 0x00010000 158 #define SHARED_HW_CFG_LED_PHY2 0x00020000 159 #define SHARED_HW_CFG_LED_PHY3 0x00030000 160 #define SHARED_HW_CFG_LED_MAC2 0x00040000 161 #define SHARED_HW_CFG_LED_PHY4 0x00050000 162 #define SHARED_HW_CFG_LED_PHY5 0x00060000 163 #define SHARED_HW_CFG_LED_PHY6 0x00070000 164 #define SHARED_HW_CFG_LED_MAC3 0x00080000 165 #define SHARED_HW_CFG_LED_PHY7 0x00090000 166 #define SHARED_HW_CFG_LED_PHY9 0x000a0000 167 #define SHARED_HW_CFG_LED_PHY11 0x000b0000 168 #define SHARED_HW_CFG_LED_MAC4 0x000c0000 169 #define SHARED_HW_CFG_LED_PHY8 0x000d0000 170 #define SHARED_HW_CFG_LED_EXTPHY1 0x000e0000 171 172 173 #define SHARED_HW_CFG_AN_ENABLE_MASK 0x3f000000 174 #define SHARED_HW_CFG_AN_ENABLE_SHIFT 24 175 #define SHARED_HW_CFG_AN_ENABLE_CL37 0x01000000 176 #define SHARED_HW_CFG_AN_ENABLE_CL73 0x02000000 177 #define SHARED_HW_CFG_AN_ENABLE_BAM 0x04000000 178 #define SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION 0x08000000 179 #define SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT 0x10000000 180 #define SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY 0x20000000 181 182 #define SHARED_HW_CFG_SRIOV_MASK 0x40000000 183 #define SHARED_HW_CFG_SRIOV_DISABLED 0x00000000 184 #define SHARED_HW_CFG_SRIOV_ENABLED 0x40000000 185 186 #define SHARED_HW_CFG_ATC_MASK 0x80000000 187 #define SHARED_HW_CFG_ATC_DISABLED 0x00000000 188 #define SHARED_HW_CFG_ATC_ENABLED 0x80000000 189 190 u32 config2; /* 0x118 */ 191 /* one time auto detect grace period (in sec) */ 192 #define SHARED_HW_CFG_GRACE_PERIOD_MASK 0x000000ff 193 #define SHARED_HW_CFG_GRACE_PERIOD_SHIFT 0 194 195 #define SHARED_HW_CFG_PCIE_GEN2_ENABLED 0x00000100 196 #define SHARED_HW_CFG_PCIE_GEN2_DISABLED 0x00000000 197 198 /* The default value for the core clock is 250MHz and it is 199 achieved by setting the clock change to 4 */ 200 #define SHARED_HW_CFG_CLOCK_CHANGE_MASK 0x00000e00 201 #define SHARED_HW_CFG_CLOCK_CHANGE_SHIFT 9 202 203 #define SHARED_HW_CFG_SMBUS_TIMING_MASK 0x00001000 204 #define SHARED_HW_CFG_SMBUS_TIMING_100KHZ 0x00000000 205 #define SHARED_HW_CFG_SMBUS_TIMING_400KHZ 0x00001000 206 207 #define SHARED_HW_CFG_HIDE_PORT1 0x00002000 208 209 #define SHARED_HW_CFG_WOL_CAPABLE_MASK 0x00004000 210 #define SHARED_HW_CFG_WOL_CAPABLE_DISABLED 0x00000000 211 #define SHARED_HW_CFG_WOL_CAPABLE_ENABLED 0x00004000 212 213 /* Output low when PERST is asserted */ 214 #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_MASK 0x00008000 215 #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_DISABLED 0x00000000 216 #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_ENABLED 0x00008000 217 218 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_MASK 0x00070000 219 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_SHIFT 16 220 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_HW 0x00000000 221 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_0DB 0x00010000 222 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_3_5DB 0x00020000 223 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_6_0DB 0x00030000 224 225 /* The fan failure mechanism is usually related to the PHY type 226 since the power consumption of the board is determined by the PHY. 227 Currently, fan is required for most designs with SFX7101, BCM8727 228 and BCM8481. If a fan is not required for a board which uses one 229 of those PHYs, this field should be set to "Disabled". If a fan is 230 required for a different PHY type, this option should be set to 231 "Enabled". The fan failure indication is expected on SPIO5 */ 232 #define SHARED_HW_CFG_FAN_FAILURE_MASK 0x00180000 233 #define SHARED_HW_CFG_FAN_FAILURE_SHIFT 19 234 #define SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE 0x00000000 235 #define SHARED_HW_CFG_FAN_FAILURE_DISABLED 0x00080000 236 #define SHARED_HW_CFG_FAN_FAILURE_ENABLED 0x00100000 237 238 /* ASPM Power Management support */ 239 #define SHARED_HW_CFG_ASPM_SUPPORT_MASK 0x00600000 240 #define SHARED_HW_CFG_ASPM_SUPPORT_SHIFT 21 241 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_ENABLED 0x00000000 242 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_DISABLED 0x00200000 243 #define SHARED_HW_CFG_ASPM_SUPPORT_L1_DISABLED 0x00400000 244 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_DISABLED 0x00600000 245 246 /* The value of PM_TL_IGNORE_REQS (bit0) in PCI register 247 tl_control_0 (register 0x2800) */ 248 #define SHARED_HW_CFG_PREVENT_L1_ENTRY_MASK 0x00800000 249 #define SHARED_HW_CFG_PREVENT_L1_ENTRY_DISABLED 0x00000000 250 #define SHARED_HW_CFG_PREVENT_L1_ENTRY_ENABLED 0x00800000 251 252 #define SHARED_HW_CFG_PORT_MODE_MASK 0x01000000 253 #define SHARED_HW_CFG_PORT_MODE_2 0x00000000 254 #define SHARED_HW_CFG_PORT_MODE_4 0x01000000 255 256 #define SHARED_HW_CFG_PATH_SWAP_MASK 0x02000000 257 #define SHARED_HW_CFG_PATH_SWAP_DISABLED 0x00000000 258 #define SHARED_HW_CFG_PATH_SWAP_ENABLED 0x02000000 259 260 /* Set the MDC/MDIO access for the first external phy */ 261 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK 0x1C000000 262 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT 26 263 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE 0x00000000 264 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0 0x04000000 265 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1 0x08000000 266 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH 0x0c000000 267 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED 0x10000000 268 269 /* Set the MDC/MDIO access for the second external phy */ 270 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK 0xE0000000 271 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT 29 272 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_PHY_TYPE 0x00000000 273 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC0 0x20000000 274 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC1 0x40000000 275 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_BOTH 0x60000000 276 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SWAPPED 0x80000000 277 278 279 u32 power_dissipated; /* 0x11c */ 280 #define SHARED_HW_CFG_POWER_MGNT_SCALE_MASK 0x00ff0000 281 #define SHARED_HW_CFG_POWER_MGNT_SCALE_SHIFT 16 282 #define SHARED_HW_CFG_POWER_MGNT_UNKNOWN_SCALE 0x00000000 283 #define SHARED_HW_CFG_POWER_MGNT_DOT_1_WATT 0x00010000 284 #define SHARED_HW_CFG_POWER_MGNT_DOT_01_WATT 0x00020000 285 #define SHARED_HW_CFG_POWER_MGNT_DOT_001_WATT 0x00030000 286 287 #define SHARED_HW_CFG_POWER_DIS_CMN_MASK 0xff000000 288 #define SHARED_HW_CFG_POWER_DIS_CMN_SHIFT 24 289 290 u32 ump_nc_si_config; /* 0x120 */ 291 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MASK 0x00000003 292 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_SHIFT 0 293 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MAC 0x00000000 294 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_PHY 0x00000001 295 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MII 0x00000000 296 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_RMII 0x00000002 297 298 #define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_MASK 0x00000f00 299 #define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_SHIFT 8 300 301 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_MASK 0x00ff0000 302 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_SHIFT 16 303 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_NONE 0x00000000 304 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_BCM5221 0x00010000 305 306 u32 board; /* 0x124 */ 307 #define SHARED_HW_CFG_E3_I2C_MUX0_MASK 0x0000003F 308 #define SHARED_HW_CFG_E3_I2C_MUX0_SHIFT 0 309 #define SHARED_HW_CFG_E3_I2C_MUX1_MASK 0x00000FC0 310 #define SHARED_HW_CFG_E3_I2C_MUX1_SHIFT 6 311 /* Use the PIN_CFG_XXX defines on top */ 312 #define SHARED_HW_CFG_BOARD_REV_MASK 0x00ff0000 313 #define SHARED_HW_CFG_BOARD_REV_SHIFT 16 314 315 #define SHARED_HW_CFG_BOARD_MAJOR_VER_MASK 0x0f000000 316 #define SHARED_HW_CFG_BOARD_MAJOR_VER_SHIFT 24 317 318 #define SHARED_HW_CFG_BOARD_MINOR_VER_MASK 0xf0000000 319 #define SHARED_HW_CFG_BOARD_MINOR_VER_SHIFT 28 320 321 u32 wc_lane_config; /* 0x128 */ 322 #define SHARED_HW_CFG_LANE_SWAP_CFG_MASK 0x0000FFFF 323 #define SHARED_HW_CFG_LANE_SWAP_CFG_SHIFT 0 324 #define SHARED_HW_CFG_LANE_SWAP_CFG_32103210 0x00001b1b 325 #define SHARED_HW_CFG_LANE_SWAP_CFG_32100123 0x00001be4 326 #define SHARED_HW_CFG_LANE_SWAP_CFG_01233210 0x0000e41b 327 #define SHARED_HW_CFG_LANE_SWAP_CFG_01230123 0x0000e4e4 328 #define SHARED_HW_CFG_LANE_SWAP_CFG_TX_MASK 0x000000FF 329 #define SHARED_HW_CFG_LANE_SWAP_CFG_TX_SHIFT 0 330 #define SHARED_HW_CFG_LANE_SWAP_CFG_RX_MASK 0x0000FF00 331 #define SHARED_HW_CFG_LANE_SWAP_CFG_RX_SHIFT 8 332 333 /* TX lane Polarity swap */ 334 #define SHARED_HW_CFG_TX_LANE0_POL_FLIP_ENABLED 0x00010000 335 #define SHARED_HW_CFG_TX_LANE1_POL_FLIP_ENABLED 0x00020000 336 #define SHARED_HW_CFG_TX_LANE2_POL_FLIP_ENABLED 0x00040000 337 #define SHARED_HW_CFG_TX_LANE3_POL_FLIP_ENABLED 0x00080000 338 /* TX lane Polarity swap */ 339 #define SHARED_HW_CFG_RX_LANE0_POL_FLIP_ENABLED 0x00100000 340 #define SHARED_HW_CFG_RX_LANE1_POL_FLIP_ENABLED 0x00200000 341 #define SHARED_HW_CFG_RX_LANE2_POL_FLIP_ENABLED 0x00400000 342 #define SHARED_HW_CFG_RX_LANE3_POL_FLIP_ENABLED 0x00800000 343 344 /* Selects the port layout of the board */ 345 #define SHARED_HW_CFG_E3_PORT_LAYOUT_MASK 0x0F000000 346 #define SHARED_HW_CFG_E3_PORT_LAYOUT_SHIFT 24 347 #define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_01 0x00000000 348 #define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_10 0x01000000 349 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_0123 0x02000000 350 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_1032 0x03000000 351 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_2301 0x04000000 352 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_3210 0x05000000 353 }; 354 355 356 /**************************************************************************** 357 * Port HW configuration * 358 ****************************************************************************/ 359 struct port_hw_cfg { /* port 0: 0x12c port 1: 0x2bc */ 360 361 u32 pci_id; 362 #define PORT_HW_CFG_PCI_VENDOR_ID_MASK 0xffff0000 363 #define PORT_HW_CFG_PCI_DEVICE_ID_MASK 0x0000ffff 364 365 u32 pci_sub_id; 366 #define PORT_HW_CFG_PCI_SUBSYS_DEVICE_ID_MASK 0xffff0000 367 #define PORT_HW_CFG_PCI_SUBSYS_VENDOR_ID_MASK 0x0000ffff 368 369 u32 power_dissipated; 370 #define PORT_HW_CFG_POWER_DIS_D0_MASK 0x000000ff 371 #define PORT_HW_CFG_POWER_DIS_D0_SHIFT 0 372 #define PORT_HW_CFG_POWER_DIS_D1_MASK 0x0000ff00 373 #define PORT_HW_CFG_POWER_DIS_D1_SHIFT 8 374 #define PORT_HW_CFG_POWER_DIS_D2_MASK 0x00ff0000 375 #define PORT_HW_CFG_POWER_DIS_D2_SHIFT 16 376 #define PORT_HW_CFG_POWER_DIS_D3_MASK 0xff000000 377 #define PORT_HW_CFG_POWER_DIS_D3_SHIFT 24 378 379 u32 power_consumed; 380 #define PORT_HW_CFG_POWER_CONS_D0_MASK 0x000000ff 381 #define PORT_HW_CFG_POWER_CONS_D0_SHIFT 0 382 #define PORT_HW_CFG_POWER_CONS_D1_MASK 0x0000ff00 383 #define PORT_HW_CFG_POWER_CONS_D1_SHIFT 8 384 #define PORT_HW_CFG_POWER_CONS_D2_MASK 0x00ff0000 385 #define PORT_HW_CFG_POWER_CONS_D2_SHIFT 16 386 #define PORT_HW_CFG_POWER_CONS_D3_MASK 0xff000000 387 #define PORT_HW_CFG_POWER_CONS_D3_SHIFT 24 388 389 u32 mac_upper; 390 #define PORT_HW_CFG_UPPERMAC_MASK 0x0000ffff 391 #define PORT_HW_CFG_UPPERMAC_SHIFT 0 392 u32 mac_lower; 393 394 u32 iscsi_mac_upper; /* Upper 16 bits are always zeroes */ 395 u32 iscsi_mac_lower; 396 397 u32 rdma_mac_upper; /* Upper 16 bits are always zeroes */ 398 u32 rdma_mac_lower; 399 400 u32 serdes_config; 401 #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_MASK 0x0000ffff 402 #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_SHIFT 0 403 404 #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK 0xffff0000 405 #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT 16 406 407 408 /* Default values: 2P-64, 4P-32 */ 409 u32 pf_config; /* 0x158 */ 410 #define PORT_HW_CFG_PF_NUM_VF_MASK 0x0000007F 411 #define PORT_HW_CFG_PF_NUM_VF_SHIFT 0 412 413 /* Default values: 17 */ 414 #define PORT_HW_CFG_PF_NUM_MSIX_VECTORS_MASK 0x00007F00 415 #define PORT_HW_CFG_PF_NUM_MSIX_VECTORS_SHIFT 8 416 417 #define PORT_HW_CFG_ENABLE_FLR_MASK 0x00010000 418 #define PORT_HW_CFG_FLR_ENABLED 0x00010000 419 420 u32 vf_config; /* 0x15C */ 421 #define PORT_HW_CFG_VF_NUM_MSIX_VECTORS_MASK 0x0000007F 422 #define PORT_HW_CFG_VF_NUM_MSIX_VECTORS_SHIFT 0 423 424 #define PORT_HW_CFG_VF_PCI_DEVICE_ID_MASK 0xFFFF0000 425 #define PORT_HW_CFG_VF_PCI_DEVICE_ID_SHIFT 16 426 427 u32 mf_pci_id; /* 0x160 */ 428 #define PORT_HW_CFG_MF_PCI_DEVICE_ID_MASK 0x0000FFFF 429 #define PORT_HW_CFG_MF_PCI_DEVICE_ID_SHIFT 0 430 431 /* Controls the TX laser of the SFP+ module */ 432 u32 sfp_ctrl; /* 0x164 */ 433 #define PORT_HW_CFG_TX_LASER_MASK 0x000000FF 434 #define PORT_HW_CFG_TX_LASER_SHIFT 0 435 #define PORT_HW_CFG_TX_LASER_MDIO 0x00000000 436 #define PORT_HW_CFG_TX_LASER_GPIO0 0x00000001 437 #define PORT_HW_CFG_TX_LASER_GPIO1 0x00000002 438 #define PORT_HW_CFG_TX_LASER_GPIO2 0x00000003 439 #define PORT_HW_CFG_TX_LASER_GPIO3 0x00000004 440 441 /* Controls the fault module LED of the SFP+ */ 442 #define PORT_HW_CFG_FAULT_MODULE_LED_MASK 0x0000FF00 443 #define PORT_HW_CFG_FAULT_MODULE_LED_SHIFT 8 444 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO0 0x00000000 445 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO1 0x00000100 446 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO2 0x00000200 447 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO3 0x00000300 448 #define PORT_HW_CFG_FAULT_MODULE_LED_DISABLED 0x00000400 449 450 /* The output pin TX_DIS that controls the TX laser of the SFP+ 451 module. Use the PIN_CFG_XXX defines on top */ 452 u32 e3_sfp_ctrl; /* 0x168 */ 453 #define PORT_HW_CFG_E3_TX_LASER_MASK 0x000000FF 454 #define PORT_HW_CFG_E3_TX_LASER_SHIFT 0 455 456 /* The output pin for SFPP_TYPE which turns on the Fault module LED */ 457 #define PORT_HW_CFG_E3_FAULT_MDL_LED_MASK 0x0000FF00 458 #define PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT 8 459 460 /* The input pin MOD_ABS that indicates whether SFP+ module is 461 present or not. Use the PIN_CFG_XXX defines on top */ 462 #define PORT_HW_CFG_E3_MOD_ABS_MASK 0x00FF0000 463 #define PORT_HW_CFG_E3_MOD_ABS_SHIFT 16 464 465 /* The output pin PWRDIS_SFP_X which disable the power of the SFP+ 466 module. Use the PIN_CFG_XXX defines on top */ 467 #define PORT_HW_CFG_E3_PWR_DIS_MASK 0xFF000000 468 #define PORT_HW_CFG_E3_PWR_DIS_SHIFT 24 469 470 /* 471 * The input pin which signals module transmit fault. Use the 472 * PIN_CFG_XXX defines on top 473 */ 474 u32 e3_cmn_pin_cfg; /* 0x16C */ 475 #define PORT_HW_CFG_E3_TX_FAULT_MASK 0x000000FF 476 #define PORT_HW_CFG_E3_TX_FAULT_SHIFT 0 477 478 /* The output pin which reset the PHY. Use the PIN_CFG_XXX defines on 479 top */ 480 #define PORT_HW_CFG_E3_PHY_RESET_MASK 0x0000FF00 481 #define PORT_HW_CFG_E3_PHY_RESET_SHIFT 8 482 483 /* 484 * The output pin which powers down the PHY. Use the PIN_CFG_XXX 485 * defines on top 486 */ 487 #define PORT_HW_CFG_E3_PWR_DOWN_MASK 0x00FF0000 488 #define PORT_HW_CFG_E3_PWR_DOWN_SHIFT 16 489 490 /* The output pin values BSC_SEL which selects the I2C for this port 491 in the I2C Mux */ 492 #define PORT_HW_CFG_E3_I2C_MUX0_MASK 0x01000000 493 #define PORT_HW_CFG_E3_I2C_MUX1_MASK 0x02000000 494 495 496 /* 497 * The input pin I_FAULT which indicate over-current has occurred. 498 * Use the PIN_CFG_XXX defines on top 499 */ 500 u32 e3_cmn_pin_cfg1; /* 0x170 */ 501 #define PORT_HW_CFG_E3_OVER_CURRENT_MASK 0x000000FF 502 #define PORT_HW_CFG_E3_OVER_CURRENT_SHIFT 0 503 u32 reserved0[7]; /* 0x174 */ 504 505 u32 aeu_int_mask; /* 0x190 */ 506 507 u32 media_type; /* 0x194 */ 508 #define PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK 0x000000FF 509 #define PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT 0 510 511 #define PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK 0x0000FF00 512 #define PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT 8 513 514 #define PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK 0x00FF0000 515 #define PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT 16 516 517 /* 4 times 16 bits for all 4 lanes. In case external PHY is present 518 (not direct mode), those values will not take effect on the 4 XGXS 519 lanes. For some external PHYs (such as 8706 and 8726) the values 520 will be used to configure the external PHY in those cases, not 521 all 4 values are needed. */ 522 u16 xgxs_config_rx[4]; /* 0x198 */ 523 u16 xgxs_config_tx[4]; /* 0x1A0 */ 524 525 /* For storing FCOE mac on shared memory */ 526 u32 fcoe_fip_mac_upper; 527 #define PORT_HW_CFG_FCOE_UPPERMAC_MASK 0x0000ffff 528 #define PORT_HW_CFG_FCOE_UPPERMAC_SHIFT 0 529 u32 fcoe_fip_mac_lower; 530 531 u32 fcoe_wwn_port_name_upper; 532 u32 fcoe_wwn_port_name_lower; 533 534 u32 fcoe_wwn_node_name_upper; 535 u32 fcoe_wwn_node_name_lower; 536 537 u32 Reserved1[49]; /* 0x1C0 */ 538 539 /* Enable RJ45 magjack pair swapping on 10GBase-T PHY (0=default), 540 84833 only */ 541 u32 xgbt_phy_cfg; /* 0x284 */ 542 #define PORT_HW_CFG_RJ45_PAIR_SWAP_MASK 0x000000FF 543 #define PORT_HW_CFG_RJ45_PAIR_SWAP_SHIFT 0 544 545 u32 default_cfg; /* 0x288 */ 546 #define PORT_HW_CFG_GPIO0_CONFIG_MASK 0x00000003 547 #define PORT_HW_CFG_GPIO0_CONFIG_SHIFT 0 548 #define PORT_HW_CFG_GPIO0_CONFIG_NA 0x00000000 549 #define PORT_HW_CFG_GPIO0_CONFIG_LOW 0x00000001 550 #define PORT_HW_CFG_GPIO0_CONFIG_HIGH 0x00000002 551 #define PORT_HW_CFG_GPIO0_CONFIG_INPUT 0x00000003 552 553 #define PORT_HW_CFG_GPIO1_CONFIG_MASK 0x0000000C 554 #define PORT_HW_CFG_GPIO1_CONFIG_SHIFT 2 555 #define PORT_HW_CFG_GPIO1_CONFIG_NA 0x00000000 556 #define PORT_HW_CFG_GPIO1_CONFIG_LOW 0x00000004 557 #define PORT_HW_CFG_GPIO1_CONFIG_HIGH 0x00000008 558 #define PORT_HW_CFG_GPIO1_CONFIG_INPUT 0x0000000c 559 560 #define PORT_HW_CFG_GPIO2_CONFIG_MASK 0x00000030 561 #define PORT_HW_CFG_GPIO2_CONFIG_SHIFT 4 562 #define PORT_HW_CFG_GPIO2_CONFIG_NA 0x00000000 563 #define PORT_HW_CFG_GPIO2_CONFIG_LOW 0x00000010 564 #define PORT_HW_CFG_GPIO2_CONFIG_HIGH 0x00000020 565 #define PORT_HW_CFG_GPIO2_CONFIG_INPUT 0x00000030 566 567 #define PORT_HW_CFG_GPIO3_CONFIG_MASK 0x000000C0 568 #define PORT_HW_CFG_GPIO3_CONFIG_SHIFT 6 569 #define PORT_HW_CFG_GPIO3_CONFIG_NA 0x00000000 570 #define PORT_HW_CFG_GPIO3_CONFIG_LOW 0x00000040 571 #define PORT_HW_CFG_GPIO3_CONFIG_HIGH 0x00000080 572 #define PORT_HW_CFG_GPIO3_CONFIG_INPUT 0x000000c0 573 574 /* When KR link is required to be set to force which is not 575 KR-compliant, this parameter determine what is the trigger for it. 576 When GPIO is selected, low input will force the speed. Currently 577 default speed is 1G. In the future, it may be widen to select the 578 forced speed in with another parameter. Note when force-1G is 579 enabled, it override option 56: Link Speed option. */ 580 #define PORT_HW_CFG_FORCE_KR_ENABLER_MASK 0x00000F00 581 #define PORT_HW_CFG_FORCE_KR_ENABLER_SHIFT 8 582 #define PORT_HW_CFG_FORCE_KR_ENABLER_NOT_FORCED 0x00000000 583 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P0 0x00000100 584 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P0 0x00000200 585 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P0 0x00000300 586 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P0 0x00000400 587 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P1 0x00000500 588 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P1 0x00000600 589 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P1 0x00000700 590 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P1 0x00000800 591 #define PORT_HW_CFG_FORCE_KR_ENABLER_FORCED 0x00000900 592 /* Enable to determine with which GPIO to reset the external phy */ 593 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK 0x000F0000 594 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT 16 595 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_PHY_TYPE 0x00000000 596 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0 0x00010000 597 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0 0x00020000 598 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0 0x00030000 599 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0 0x00040000 600 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1 0x00050000 601 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1 0x00060000 602 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1 0x00070000 603 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1 0x00080000 604 605 /* Enable BAM on KR */ 606 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_MASK 0x00100000 607 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_SHIFT 20 608 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_DISABLED 0x00000000 609 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED 0x00100000 610 611 /* Enable Common Mode Sense */ 612 #define PORT_HW_CFG_ENABLE_CMS_MASK 0x00200000 613 #define PORT_HW_CFG_ENABLE_CMS_SHIFT 21 614 #define PORT_HW_CFG_ENABLE_CMS_DISABLED 0x00000000 615 #define PORT_HW_CFG_ENABLE_CMS_ENABLED 0x00200000 616 617 /* Determine the Serdes electrical interface */ 618 #define PORT_HW_CFG_NET_SERDES_IF_MASK 0x0F000000 619 #define PORT_HW_CFG_NET_SERDES_IF_SHIFT 24 620 #define PORT_HW_CFG_NET_SERDES_IF_SGMII 0x00000000 621 #define PORT_HW_CFG_NET_SERDES_IF_XFI 0x01000000 622 #define PORT_HW_CFG_NET_SERDES_IF_SFI 0x02000000 623 #define PORT_HW_CFG_NET_SERDES_IF_KR 0x03000000 624 #define PORT_HW_CFG_NET_SERDES_IF_DXGXS 0x04000000 625 #define PORT_HW_CFG_NET_SERDES_IF_KR2 0x05000000 626 627 628 u32 speed_capability_mask2; /* 0x28C */ 629 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_MASK 0x0000FFFF 630 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_SHIFT 0 631 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10M_FULL 0x00000001 632 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3__ 0x00000002 633 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3___ 0x00000004 634 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_100M_FULL 0x00000008 635 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_1G 0x00000010 636 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_2_DOT_5G 0x00000020 637 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10G 0x00000040 638 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_20G 0x00000080 639 640 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_MASK 0xFFFF0000 641 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_SHIFT 16 642 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10M_FULL 0x00010000 643 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0__ 0x00020000 644 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0___ 0x00040000 645 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_100M_FULL 0x00080000 646 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_1G 0x00100000 647 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_2_DOT_5G 0x00200000 648 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10G 0x00400000 649 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_20G 0x00800000 650 651 652 /* In the case where two media types (e.g. copper and fiber) are 653 present and electrically active at the same time, PHY Selection 654 will determine which of the two PHYs will be designated as the 655 Active PHY and used for a connection to the network. */ 656 u32 multi_phy_config; /* 0x290 */ 657 #define PORT_HW_CFG_PHY_SELECTION_MASK 0x00000007 658 #define PORT_HW_CFG_PHY_SELECTION_SHIFT 0 659 #define PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT 0x00000000 660 #define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY 0x00000001 661 #define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY 0x00000002 662 #define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY 0x00000003 663 #define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY 0x00000004 664 665 /* When enabled, all second phy nvram parameters will be swapped 666 with the first phy parameters */ 667 #define PORT_HW_CFG_PHY_SWAPPED_MASK 0x00000008 668 #define PORT_HW_CFG_PHY_SWAPPED_SHIFT 3 669 #define PORT_HW_CFG_PHY_SWAPPED_DISABLED 0x00000000 670 #define PORT_HW_CFG_PHY_SWAPPED_ENABLED 0x00000008 671 672 673 /* Address of the second external phy */ 674 u32 external_phy_config2; /* 0x294 */ 675 #define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_MASK 0x000000FF 676 #define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_SHIFT 0 677 678 /* The second XGXS external PHY type */ 679 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_MASK 0x0000FF00 680 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SHIFT 8 681 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_DIRECT 0x00000000 682 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8071 0x00000100 683 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8072 0x00000200 684 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8073 0x00000300 685 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8705 0x00000400 686 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8706 0x00000500 687 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8726 0x00000600 688 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8481 0x00000700 689 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SFX7101 0x00000800 690 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727 0x00000900 691 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727_NOC 0x00000a00 692 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84823 0x00000b00 693 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54640 0x00000c00 694 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84833 0x00000d00 695 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54618SE 0x00000e00 696 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8722 0x00000f00 697 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54616 0x00001000 698 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_FAILURE 0x0000fd00 699 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_NOT_CONN 0x0000ff00 700 701 702 /* 4 times 16 bits for all 4 lanes. For some external PHYs (such as 703 8706, 8726 and 8727) not all 4 values are needed. */ 704 u16 xgxs_config2_rx[4]; /* 0x296 */ 705 u16 xgxs_config2_tx[4]; /* 0x2A0 */ 706 707 u32 lane_config; 708 #define PORT_HW_CFG_LANE_SWAP_CFG_MASK 0x0000ffff 709 #define PORT_HW_CFG_LANE_SWAP_CFG_SHIFT 0 710 /* AN and forced */ 711 #define PORT_HW_CFG_LANE_SWAP_CFG_01230123 0x00001b1b 712 /* forced only */ 713 #define PORT_HW_CFG_LANE_SWAP_CFG_01233210 0x00001be4 714 /* forced only */ 715 #define PORT_HW_CFG_LANE_SWAP_CFG_31203120 0x0000d8d8 716 /* forced only */ 717 #define PORT_HW_CFG_LANE_SWAP_CFG_32103210 0x0000e4e4 718 #define PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK 0x000000ff 719 #define PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT 0 720 #define PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK 0x0000ff00 721 #define PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT 8 722 #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK 0x0000c000 723 #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT 14 724 725 /* Indicate whether to swap the external phy polarity */ 726 #define PORT_HW_CFG_SWAP_PHY_POLARITY_MASK 0x00010000 727 #define PORT_HW_CFG_SWAP_PHY_POLARITY_DISABLED 0x00000000 728 #define PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED 0x00010000 729 730 731 u32 external_phy_config; 732 #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK 0x000000ff 733 #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT 0 734 735 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK 0x0000ff00 736 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SHIFT 8 737 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT 0x00000000 738 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8071 0x00000100 739 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072 0x00000200 740 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073 0x00000300 741 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705 0x00000400 742 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706 0x00000500 743 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726 0x00000600 744 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481 0x00000700 745 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101 0x00000800 746 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727 0x00000900 747 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC 0x00000a00 748 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823 0x00000b00 749 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54640 0x00000c00 750 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833 0x00000d00 751 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE 0x00000e00 752 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722 0x00000f00 753 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616 0x00001000 754 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT_WC 0x0000fc00 755 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE 0x0000fd00 756 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN 0x0000ff00 757 758 #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK 0x00ff0000 759 #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_SHIFT 16 760 761 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK 0xff000000 762 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_SHIFT 24 763 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT 0x00000000 764 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482 0x01000000 765 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD 0x02000000 766 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN 0xff000000 767 768 u32 speed_capability_mask; 769 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_MASK 0x0000ffff 770 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_SHIFT 0 771 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_FULL 0x00000001 772 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_HALF 0x00000002 773 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_HALF 0x00000004 774 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_FULL 0x00000008 775 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_1G 0x00000010 776 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_2_5G 0x00000020 777 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10G 0x00000040 778 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_20G 0x00000080 779 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_RESERVED 0x0000f000 780 781 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK 0xffff0000 782 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_SHIFT 16 783 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL 0x00010000 784 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF 0x00020000 785 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF 0x00040000 786 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL 0x00080000 787 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_1G 0x00100000 788 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G 0x00200000 789 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10G 0x00400000 790 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_20G 0x00800000 791 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_RESERVED 0xf0000000 792 793 /* A place to hold the original MAC address as a backup */ 794 u32 backup_mac_upper; /* 0x2B4 */ 795 u32 backup_mac_lower; /* 0x2B8 */ 796 797 }; 798 799 800 /**************************************************************************** 801 * Shared Feature configuration * 802 ****************************************************************************/ 803 struct shared_feat_cfg { /* NVRAM Offset */ 804 805 u32 config; /* 0x450 */ 806 #define SHARED_FEATURE_BMC_ECHO_MODE_EN 0x00000001 807 808 /* Use NVRAM values instead of HW default values */ 809 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_MASK \ 810 0x00000002 811 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_DISABLED \ 812 0x00000000 813 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED \ 814 0x00000002 815 816 #define SHARED_FEAT_CFG_NCSI_ID_METHOD_MASK 0x00000008 817 #define SHARED_FEAT_CFG_NCSI_ID_METHOD_SPIO 0x00000000 818 #define SHARED_FEAT_CFG_NCSI_ID_METHOD_NVRAM 0x00000008 819 820 #define SHARED_FEAT_CFG_NCSI_ID_MASK 0x00000030 821 #define SHARED_FEAT_CFG_NCSI_ID_SHIFT 4 822 823 /* Override the OTP back to single function mode. When using GPIO, 824 high means only SF, 0 is according to CLP configuration */ 825 #define SHARED_FEAT_CFG_FORCE_SF_MODE_MASK 0x00000700 826 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SHIFT 8 827 #define SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED 0x00000000 828 #define SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF 0x00000100 829 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4 0x00000200 830 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT 0x00000300 831 #define SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE 0x00000400 832 833 /* The interval in seconds between sending LLDP packets. Set to zero 834 to disable the feature */ 835 #define SHARED_FEAT_CFG_LLDP_XMIT_INTERVAL_MASK 0x00ff0000 836 #define SHARED_FEAT_CFG_LLDP_XMIT_INTERVAL_SHIFT 16 837 838 /* The assigned device type ID for LLDP usage */ 839 #define SHARED_FEAT_CFG_LLDP_DEVICE_TYPE_ID_MASK 0xff000000 840 #define SHARED_FEAT_CFG_LLDP_DEVICE_TYPE_ID_SHIFT 24 841 842 }; 843 844 845 /**************************************************************************** 846 * Port Feature configuration * 847 ****************************************************************************/ 848 struct port_feat_cfg { /* port 0: 0x454 port 1: 0x4c8 */ 849 850 u32 config; 851 #define PORT_FEATURE_BAR1_SIZE_MASK 0x0000000f 852 #define PORT_FEATURE_BAR1_SIZE_SHIFT 0 853 #define PORT_FEATURE_BAR1_SIZE_DISABLED 0x00000000 854 #define PORT_FEATURE_BAR1_SIZE_64K 0x00000001 855 #define PORT_FEATURE_BAR1_SIZE_128K 0x00000002 856 #define PORT_FEATURE_BAR1_SIZE_256K 0x00000003 857 #define PORT_FEATURE_BAR1_SIZE_512K 0x00000004 858 #define PORT_FEATURE_BAR1_SIZE_1M 0x00000005 859 #define PORT_FEATURE_BAR1_SIZE_2M 0x00000006 860 #define PORT_FEATURE_BAR1_SIZE_4M 0x00000007 861 #define PORT_FEATURE_BAR1_SIZE_8M 0x00000008 862 #define PORT_FEATURE_BAR1_SIZE_16M 0x00000009 863 #define PORT_FEATURE_BAR1_SIZE_32M 0x0000000a 864 #define PORT_FEATURE_BAR1_SIZE_64M 0x0000000b 865 #define PORT_FEATURE_BAR1_SIZE_128M 0x0000000c 866 #define PORT_FEATURE_BAR1_SIZE_256M 0x0000000d 867 #define PORT_FEATURE_BAR1_SIZE_512M 0x0000000e 868 #define PORT_FEATURE_BAR1_SIZE_1G 0x0000000f 869 #define PORT_FEATURE_BAR2_SIZE_MASK 0x000000f0 870 #define PORT_FEATURE_BAR2_SIZE_SHIFT 4 871 #define PORT_FEATURE_BAR2_SIZE_DISABLED 0x00000000 872 #define PORT_FEATURE_BAR2_SIZE_64K 0x00000010 873 #define PORT_FEATURE_BAR2_SIZE_128K 0x00000020 874 #define PORT_FEATURE_BAR2_SIZE_256K 0x00000030 875 #define PORT_FEATURE_BAR2_SIZE_512K 0x00000040 876 #define PORT_FEATURE_BAR2_SIZE_1M 0x00000050 877 #define PORT_FEATURE_BAR2_SIZE_2M 0x00000060 878 #define PORT_FEATURE_BAR2_SIZE_4M 0x00000070 879 #define PORT_FEATURE_BAR2_SIZE_8M 0x00000080 880 #define PORT_FEATURE_BAR2_SIZE_16M 0x00000090 881 #define PORT_FEATURE_BAR2_SIZE_32M 0x000000a0 882 #define PORT_FEATURE_BAR2_SIZE_64M 0x000000b0 883 #define PORT_FEATURE_BAR2_SIZE_128M 0x000000c0 884 #define PORT_FEATURE_BAR2_SIZE_256M 0x000000d0 885 #define PORT_FEATURE_BAR2_SIZE_512M 0x000000e0 886 #define PORT_FEATURE_BAR2_SIZE_1G 0x000000f0 887 888 #define PORT_FEAT_CFG_DCBX_MASK 0x00000100 889 #define PORT_FEAT_CFG_DCBX_DISABLED 0x00000000 890 #define PORT_FEAT_CFG_DCBX_ENABLED 0x00000100 891 892 #define PORT_FEATURE_EN_SIZE_MASK 0x0f000000 893 #define PORT_FEATURE_EN_SIZE_SHIFT 24 894 #define PORT_FEATURE_WOL_ENABLED 0x01000000 895 #define PORT_FEATURE_MBA_ENABLED 0x02000000 896 #define PORT_FEATURE_MFW_ENABLED 0x04000000 897 898 /* Advertise expansion ROM even if MBA is disabled */ 899 #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_MASK 0x08000000 900 #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_DISABLED 0x00000000 901 #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_ENABLED 0x08000000 902 903 /* Check the optic vendor via i2c against a list of approved modules 904 in a separate nvram image */ 905 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK 0xe0000000 906 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_SHIFT 29 907 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT \ 908 0x00000000 909 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER \ 910 0x20000000 911 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG 0x40000000 912 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN 0x60000000 913 914 u32 wol_config; 915 /* Default is used when driver sets to "auto" mode */ 916 #define PORT_FEATURE_WOL_DEFAULT_MASK 0x00000003 917 #define PORT_FEATURE_WOL_DEFAULT_SHIFT 0 918 #define PORT_FEATURE_WOL_DEFAULT_DISABLE 0x00000000 919 #define PORT_FEATURE_WOL_DEFAULT_MAGIC 0x00000001 920 #define PORT_FEATURE_WOL_DEFAULT_ACPI 0x00000002 921 #define PORT_FEATURE_WOL_DEFAULT_MAGIC_AND_ACPI 0x00000003 922 #define PORT_FEATURE_WOL_RES_PAUSE_CAP 0x00000004 923 #define PORT_FEATURE_WOL_RES_ASYM_PAUSE_CAP 0x00000008 924 #define PORT_FEATURE_WOL_ACPI_UPON_MGMT 0x00000010 925 926 u32 mba_config; 927 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK 0x00000007 928 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT 0 929 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE 0x00000000 930 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL 0x00000001 931 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP 0x00000002 932 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB 0x00000003 933 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT 0x00000004 934 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE 0x00000007 935 936 #define PORT_FEATURE_MBA_BOOT_RETRY_MASK 0x00000038 937 #define PORT_FEATURE_MBA_BOOT_RETRY_SHIFT 3 938 939 #define PORT_FEATURE_MBA_RES_PAUSE_CAP 0x00000100 940 #define PORT_FEATURE_MBA_RES_ASYM_PAUSE_CAP 0x00000200 941 #define PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE 0x00000400 942 #define PORT_FEATURE_MBA_HOTKEY_MASK 0x00000800 943 #define PORT_FEATURE_MBA_HOTKEY_CTRL_S 0x00000000 944 #define PORT_FEATURE_MBA_HOTKEY_CTRL_B 0x00000800 945 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK 0x000ff000 946 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT 12 947 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED 0x00000000 948 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2K 0x00001000 949 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4K 0x00002000 950 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8K 0x00003000 951 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16K 0x00004000 952 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32K 0x00005000 953 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_64K 0x00006000 954 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_128K 0x00007000 955 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_256K 0x00008000 956 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_512K 0x00009000 957 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_1M 0x0000a000 958 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2M 0x0000b000 959 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4M 0x0000c000 960 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8M 0x0000d000 961 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16M 0x0000e000 962 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32M 0x0000f000 963 #define PORT_FEATURE_MBA_MSG_TIMEOUT_MASK 0x00f00000 964 #define PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT 20 965 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK 0x03000000 966 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT 24 967 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO 0x00000000 968 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS 0x01000000 969 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H 0x02000000 970 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H 0x03000000 971 #define PORT_FEATURE_MBA_LINK_SPEED_MASK 0x3c000000 972 #define PORT_FEATURE_MBA_LINK_SPEED_SHIFT 26 973 #define PORT_FEATURE_MBA_LINK_SPEED_AUTO 0x00000000 974 #define PORT_FEATURE_MBA_LINK_SPEED_10HD 0x04000000 975 #define PORT_FEATURE_MBA_LINK_SPEED_10FD 0x08000000 976 #define PORT_FEATURE_MBA_LINK_SPEED_100HD 0x0c000000 977 #define PORT_FEATURE_MBA_LINK_SPEED_100FD 0x10000000 978 #define PORT_FEATURE_MBA_LINK_SPEED_1GBPS 0x14000000 979 #define PORT_FEATURE_MBA_LINK_SPEED_2_5GBPS 0x18000000 980 #define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_CX4 0x1c000000 981 #define PORT_FEATURE_MBA_LINK_SPEED_20GBPS 0x20000000 982 u32 bmc_config; 983 #define PORT_FEATURE_BMC_LINK_OVERRIDE_MASK 0x00000001 984 #define PORT_FEATURE_BMC_LINK_OVERRIDE_DEFAULT 0x00000000 985 #define PORT_FEATURE_BMC_LINK_OVERRIDE_EN 0x00000001 986 987 u32 mba_vlan_cfg; 988 #define PORT_FEATURE_MBA_VLAN_TAG_MASK 0x0000ffff 989 #define PORT_FEATURE_MBA_VLAN_TAG_SHIFT 0 990 #define PORT_FEATURE_MBA_VLAN_EN 0x00010000 991 992 u32 resource_cfg; 993 #define PORT_FEATURE_RESOURCE_CFG_VALID 0x00000001 994 #define PORT_FEATURE_RESOURCE_CFG_DIAG 0x00000002 995 #define PORT_FEATURE_RESOURCE_CFG_L2 0x00000004 996 #define PORT_FEATURE_RESOURCE_CFG_ISCSI 0x00000008 997 #define PORT_FEATURE_RESOURCE_CFG_RDMA 0x00000010 998 999 u32 smbus_config; 1000 #define PORT_FEATURE_SMBUS_ADDR_MASK 0x000000fe 1001 #define PORT_FEATURE_SMBUS_ADDR_SHIFT 1 1002 1003 u32 vf_config; 1004 #define PORT_FEAT_CFG_VF_BAR2_SIZE_MASK 0x0000000f 1005 #define PORT_FEAT_CFG_VF_BAR2_SIZE_SHIFT 0 1006 #define PORT_FEAT_CFG_VF_BAR2_SIZE_DISABLED 0x00000000 1007 #define PORT_FEAT_CFG_VF_BAR2_SIZE_4K 0x00000001 1008 #define PORT_FEAT_CFG_VF_BAR2_SIZE_8K 0x00000002 1009 #define PORT_FEAT_CFG_VF_BAR2_SIZE_16K 0x00000003 1010 #define PORT_FEAT_CFG_VF_BAR2_SIZE_32K 0x00000004 1011 #define PORT_FEAT_CFG_VF_BAR2_SIZE_64K 0x00000005 1012 #define PORT_FEAT_CFG_VF_BAR2_SIZE_128K 0x00000006 1013 #define PORT_FEAT_CFG_VF_BAR2_SIZE_256K 0x00000007 1014 #define PORT_FEAT_CFG_VF_BAR2_SIZE_512K 0x00000008 1015 #define PORT_FEAT_CFG_VF_BAR2_SIZE_1M 0x00000009 1016 #define PORT_FEAT_CFG_VF_BAR2_SIZE_2M 0x0000000a 1017 #define PORT_FEAT_CFG_VF_BAR2_SIZE_4M 0x0000000b 1018 #define PORT_FEAT_CFG_VF_BAR2_SIZE_8M 0x0000000c 1019 #define PORT_FEAT_CFG_VF_BAR2_SIZE_16M 0x0000000d 1020 #define PORT_FEAT_CFG_VF_BAR2_SIZE_32M 0x0000000e 1021 #define PORT_FEAT_CFG_VF_BAR2_SIZE_64M 0x0000000f 1022 1023 u32 link_config; /* Used as HW defaults for the driver */ 1024 #define PORT_FEATURE_CONNECTED_SWITCH_MASK 0x03000000 1025 #define PORT_FEATURE_CONNECTED_SWITCH_SHIFT 24 1026 /* (forced) low speed switch (< 10G) */ 1027 #define PORT_FEATURE_CON_SWITCH_1G_SWITCH 0x00000000 1028 /* (forced) high speed switch (>= 10G) */ 1029 #define PORT_FEATURE_CON_SWITCH_10G_SWITCH 0x01000000 1030 #define PORT_FEATURE_CON_SWITCH_AUTO_DETECT 0x02000000 1031 #define PORT_FEATURE_CON_SWITCH_ONE_TIME_DETECT 0x03000000 1032 1033 #define PORT_FEATURE_LINK_SPEED_MASK 0x000f0000 1034 #define PORT_FEATURE_LINK_SPEED_SHIFT 16 1035 #define PORT_FEATURE_LINK_SPEED_AUTO 0x00000000 1036 #define PORT_FEATURE_LINK_SPEED_10M_FULL 0x00010000 1037 #define PORT_FEATURE_LINK_SPEED_10M_HALF 0x00020000 1038 #define PORT_FEATURE_LINK_SPEED_100M_HALF 0x00030000 1039 #define PORT_FEATURE_LINK_SPEED_100M_FULL 0x00040000 1040 #define PORT_FEATURE_LINK_SPEED_1G 0x00050000 1041 #define PORT_FEATURE_LINK_SPEED_2_5G 0x00060000 1042 #define PORT_FEATURE_LINK_SPEED_10G_CX4 0x00070000 1043 #define PORT_FEATURE_LINK_SPEED_20G 0x00080000 1044 1045 #define PORT_FEATURE_FLOW_CONTROL_MASK 0x00000700 1046 #define PORT_FEATURE_FLOW_CONTROL_SHIFT 8 1047 #define PORT_FEATURE_FLOW_CONTROL_AUTO 0x00000000 1048 #define PORT_FEATURE_FLOW_CONTROL_TX 0x00000100 1049 #define PORT_FEATURE_FLOW_CONTROL_RX 0x00000200 1050 #define PORT_FEATURE_FLOW_CONTROL_BOTH 0x00000300 1051 #define PORT_FEATURE_FLOW_CONTROL_NONE 0x00000400 1052 1053 /* The default for MCP link configuration, 1054 uses the same defines as link_config */ 1055 u32 mfw_wol_link_cfg; 1056 1057 /* The default for the driver of the second external phy, 1058 uses the same defines as link_config */ 1059 u32 link_config2; /* 0x47C */ 1060 1061 /* The default for MCP of the second external phy, 1062 uses the same defines as link_config */ 1063 u32 mfw_wol_link_cfg2; /* 0x480 */ 1064 1065 1066 /* EEE power saving mode */ 1067 u32 eee_power_mode; /* 0x484 */ 1068 #define PORT_FEAT_CFG_EEE_POWER_MODE_MASK 0x000000FF 1069 #define PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT 0 1070 #define PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED 0x00000000 1071 #define PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED 0x00000001 1072 #define PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE 0x00000002 1073 #define PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY 0x00000003 1074 1075 1076 u32 Reserved2[16]; /* 0x488 */ 1077 }; 1078 1079 1080 /**************************************************************************** 1081 * Device Information * 1082 ****************************************************************************/ 1083 struct shm_dev_info { /* size */ 1084 1085 u32 bc_rev; /* 8 bits each: major, minor, build */ /* 4 */ 1086 1087 struct shared_hw_cfg shared_hw_config; /* 40 */ 1088 1089 struct port_hw_cfg port_hw_config[PORT_MAX]; /* 400*2=800 */ 1090 1091 struct shared_feat_cfg shared_feature_config; /* 4 */ 1092 1093 struct port_feat_cfg port_feature_config[PORT_MAX];/* 116*2=232 */ 1094 1095 }; 1096 1097 1098 #if !defined(__LITTLE_ENDIAN) && !defined(__BIG_ENDIAN) 1099 #error "Missing either LITTLE_ENDIAN or BIG_ENDIAN definition." 1100 #endif 1101 1102 #define FUNC_0 0 1103 #define FUNC_1 1 1104 #define FUNC_2 2 1105 #define FUNC_3 3 1106 #define FUNC_4 4 1107 #define FUNC_5 5 1108 #define FUNC_6 6 1109 #define FUNC_7 7 1110 #define E1_FUNC_MAX 2 1111 #define E1H_FUNC_MAX 8 1112 #define E2_FUNC_MAX 4 /* per path */ 1113 1114 #define VN_0 0 1115 #define VN_1 1 1116 #define VN_2 2 1117 #define VN_3 3 1118 #define E1VN_MAX 1 1119 #define E1HVN_MAX 4 1120 1121 #define E2_VF_MAX 64 /* HC_REG_VF_CONFIGURATION_SIZE */ 1122 /* This value (in milliseconds) determines the frequency of the driver 1123 * issuing the PULSE message code. The firmware monitors this periodic 1124 * pulse to determine when to switch to an OS-absent mode. */ 1125 #define DRV_PULSE_PERIOD_MS 250 1126 1127 /* This value (in milliseconds) determines how long the driver should 1128 * wait for an acknowledgement from the firmware before timing out. Once 1129 * the firmware has timed out, the driver will assume there is no firmware 1130 * running and there won't be any firmware-driver synchronization during a 1131 * driver reset. */ 1132 #define FW_ACK_TIME_OUT_MS 5000 1133 1134 #define FW_ACK_POLL_TIME_MS 1 1135 1136 #define FW_ACK_NUM_OF_POLL (FW_ACK_TIME_OUT_MS/FW_ACK_POLL_TIME_MS) 1137 1138 #define MFW_TRACE_SIGNATURE 0x54524342 1139 1140 /**************************************************************************** 1141 * Driver <-> FW Mailbox * 1142 ****************************************************************************/ 1143 struct drv_port_mb { 1144 1145 u32 link_status; 1146 /* Driver should update this field on any link change event */ 1147 1148 #define LINK_STATUS_NONE (0<<0) 1149 #define LINK_STATUS_LINK_FLAG_MASK 0x00000001 1150 #define LINK_STATUS_LINK_UP 0x00000001 1151 #define LINK_STATUS_SPEED_AND_DUPLEX_MASK 0x0000001E 1152 #define LINK_STATUS_SPEED_AND_DUPLEX_AN_NOT_COMPLETE (0<<1) 1153 #define LINK_STATUS_SPEED_AND_DUPLEX_10THD (1<<1) 1154 #define LINK_STATUS_SPEED_AND_DUPLEX_10TFD (2<<1) 1155 #define LINK_STATUS_SPEED_AND_DUPLEX_100TXHD (3<<1) 1156 #define LINK_STATUS_SPEED_AND_DUPLEX_100T4 (4<<1) 1157 #define LINK_STATUS_SPEED_AND_DUPLEX_100TXFD (5<<1) 1158 #define LINK_STATUS_SPEED_AND_DUPLEX_1000THD (6<<1) 1159 #define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD (7<<1) 1160 #define LINK_STATUS_SPEED_AND_DUPLEX_1000XFD (7<<1) 1161 #define LINK_STATUS_SPEED_AND_DUPLEX_2500THD (8<<1) 1162 #define LINK_STATUS_SPEED_AND_DUPLEX_2500TFD (9<<1) 1163 #define LINK_STATUS_SPEED_AND_DUPLEX_2500XFD (9<<1) 1164 #define LINK_STATUS_SPEED_AND_DUPLEX_10GTFD (10<<1) 1165 #define LINK_STATUS_SPEED_AND_DUPLEX_10GXFD (10<<1) 1166 #define LINK_STATUS_SPEED_AND_DUPLEX_20GTFD (11<<1) 1167 #define LINK_STATUS_SPEED_AND_DUPLEX_20GXFD (11<<1) 1168 1169 #define LINK_STATUS_AUTO_NEGOTIATE_FLAG_MASK 0x00000020 1170 #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED 0x00000020 1171 1172 #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE 0x00000040 1173 #define LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK 0x00000080 1174 #define LINK_STATUS_PARALLEL_DETECTION_USED 0x00000080 1175 1176 #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200 1177 #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400 1178 #define LINK_STATUS_LINK_PARTNER_100T4_CAPABLE 0x00000800 1179 #define LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE 0x00001000 1180 #define LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE 0x00002000 1181 #define LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE 0x00004000 1182 #define LINK_STATUS_LINK_PARTNER_10THD_CAPABLE 0x00008000 1183 1184 #define LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK 0x00010000 1185 #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED 0x00010000 1186 1187 #define LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK 0x00020000 1188 #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED 0x00020000 1189 1190 #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK 0x000C0000 1191 #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE (0<<18) 1192 #define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE (1<<18) 1193 #define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE (2<<18) 1194 #define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE (3<<18) 1195 1196 #define LINK_STATUS_SERDES_LINK 0x00100000 1197 1198 #define LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE 0x00200000 1199 #define LINK_STATUS_LINK_PARTNER_2500XHD_CAPABLE 0x00400000 1200 #define LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE 0x00800000 1201 #define LINK_STATUS_LINK_PARTNER_20GXFD_CAPABLE 0x10000000 1202 1203 #define LINK_STATUS_PFC_ENABLED 0x20000000 1204 1205 #define LINK_STATUS_PHYSICAL_LINK_FLAG 0x40000000 1206 #define LINK_STATUS_SFP_TX_FAULT 0x80000000 1207 1208 u32 port_stx; 1209 1210 u32 stat_nig_timer; 1211 1212 /* MCP firmware does not use this field */ 1213 u32 ext_phy_fw_version; 1214 1215 }; 1216 1217 1218 struct drv_func_mb { 1219 1220 u32 drv_mb_header; 1221 #define DRV_MSG_CODE_MASK 0xffff0000 1222 #define DRV_MSG_CODE_LOAD_REQ 0x10000000 1223 #define DRV_MSG_CODE_LOAD_DONE 0x11000000 1224 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_EN 0x20000000 1225 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS 0x20010000 1226 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP 0x20020000 1227 #define DRV_MSG_CODE_UNLOAD_DONE 0x21000000 1228 #define DRV_MSG_CODE_DCC_OK 0x30000000 1229 #define DRV_MSG_CODE_DCC_FAILURE 0x31000000 1230 #define DRV_MSG_CODE_DIAG_ENTER_REQ 0x50000000 1231 #define DRV_MSG_CODE_DIAG_EXIT_REQ 0x60000000 1232 #define DRV_MSG_CODE_VALIDATE_KEY 0x70000000 1233 #define DRV_MSG_CODE_GET_CURR_KEY 0x80000000 1234 #define DRV_MSG_CODE_GET_UPGRADE_KEY 0x81000000 1235 #define DRV_MSG_CODE_GET_MANUF_KEY 0x82000000 1236 #define DRV_MSG_CODE_LOAD_L2B_PRAM 0x90000000 1237 /* 1238 * The optic module verification command requires bootcode 1239 * v5.0.6 or later, te specific optic module verification command 1240 * requires bootcode v5.2.12 or later 1241 */ 1242 #define DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL 0xa0000000 1243 #define REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL 0x00050006 1244 #define DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL 0xa1000000 1245 #define REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL 0x00050234 1246 #define DRV_MSG_CODE_VRFY_AFEX_SUPPORTED 0xa2000000 1247 #define REQ_BC_VER_4_VRFY_AFEX_SUPPORTED 0x00070002 1248 #define REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED 0x00070014 1249 #define REQ_BC_VER_4_PFC_STATS_SUPPORTED 0x00070201 1250 #define REQ_BC_VER_4_FCOE_FEATURES 0x00070209 1251 1252 #define DRV_MSG_CODE_DCBX_ADMIN_PMF_MSG 0xb0000000 1253 #define DRV_MSG_CODE_DCBX_PMF_DRV_OK 0xb2000000 1254 #define REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF 0x00070401 1255 1256 #define DRV_MSG_CODE_VF_DISABLED_DONE 0xc0000000 1257 1258 #define DRV_MSG_CODE_AFEX_DRIVER_SETMAC 0xd0000000 1259 #define DRV_MSG_CODE_AFEX_LISTGET_ACK 0xd1000000 1260 #define DRV_MSG_CODE_AFEX_LISTSET_ACK 0xd2000000 1261 #define DRV_MSG_CODE_AFEX_STATSGET_ACK 0xd3000000 1262 #define DRV_MSG_CODE_AFEX_VIFSET_ACK 0xd4000000 1263 1264 #define DRV_MSG_CODE_DRV_INFO_ACK 0xd8000000 1265 #define DRV_MSG_CODE_DRV_INFO_NACK 0xd9000000 1266 1267 #define DRV_MSG_CODE_EEE_RESULTS_ACK 0xda000000 1268 1269 #define DRV_MSG_CODE_SET_MF_BW 0xe0000000 1270 #define REQ_BC_VER_4_SET_MF_BW 0x00060202 1271 #define DRV_MSG_CODE_SET_MF_BW_ACK 0xe1000000 1272 1273 #define DRV_MSG_CODE_LINK_STATUS_CHANGED 0x01000000 1274 1275 #define DRV_MSG_CODE_INITIATE_FLR 0x02000000 1276 #define REQ_BC_VER_4_INITIATE_FLR 0x00070213 1277 1278 #define BIOS_MSG_CODE_LIC_CHALLENGE 0xff010000 1279 #define BIOS_MSG_CODE_LIC_RESPONSE 0xff020000 1280 #define BIOS_MSG_CODE_VIRT_MAC_PRIM 0xff030000 1281 #define BIOS_MSG_CODE_VIRT_MAC_ISCSI 0xff040000 1282 1283 #define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff 1284 1285 u32 drv_mb_param; 1286 #define DRV_MSG_CODE_SET_MF_BW_MIN_MASK 0x00ff0000 1287 #define DRV_MSG_CODE_SET_MF_BW_MAX_MASK 0xff000000 1288 1289 u32 fw_mb_header; 1290 #define FW_MSG_CODE_MASK 0xffff0000 1291 #define FW_MSG_CODE_DRV_LOAD_COMMON 0x10100000 1292 #define FW_MSG_CODE_DRV_LOAD_PORT 0x10110000 1293 #define FW_MSG_CODE_DRV_LOAD_FUNCTION 0x10120000 1294 /* Load common chip is supported from bc 6.0.0 */ 1295 #define REQ_BC_VER_4_DRV_LOAD_COMMON_CHIP 0x00060000 1296 #define FW_MSG_CODE_DRV_LOAD_COMMON_CHIP 0x10130000 1297 1298 #define FW_MSG_CODE_DRV_LOAD_REFUSED 0x10200000 1299 #define FW_MSG_CODE_DRV_LOAD_DONE 0x11100000 1300 #define FW_MSG_CODE_DRV_UNLOAD_COMMON 0x20100000 1301 #define FW_MSG_CODE_DRV_UNLOAD_PORT 0x20110000 1302 #define FW_MSG_CODE_DRV_UNLOAD_FUNCTION 0x20120000 1303 #define FW_MSG_CODE_DRV_UNLOAD_DONE 0x21100000 1304 #define FW_MSG_CODE_DCC_DONE 0x30100000 1305 #define FW_MSG_CODE_LLDP_DONE 0x40100000 1306 #define FW_MSG_CODE_DIAG_ENTER_DONE 0x50100000 1307 #define FW_MSG_CODE_DIAG_REFUSE 0x50200000 1308 #define FW_MSG_CODE_DIAG_EXIT_DONE 0x60100000 1309 #define FW_MSG_CODE_VALIDATE_KEY_SUCCESS 0x70100000 1310 #define FW_MSG_CODE_VALIDATE_KEY_FAILURE 0x70200000 1311 #define FW_MSG_CODE_GET_KEY_DONE 0x80100000 1312 #define FW_MSG_CODE_NO_KEY 0x80f00000 1313 #define FW_MSG_CODE_LIC_INFO_NOT_READY 0x80f80000 1314 #define FW_MSG_CODE_L2B_PRAM_LOADED 0x90100000 1315 #define FW_MSG_CODE_L2B_PRAM_T_LOAD_FAILURE 0x90210000 1316 #define FW_MSG_CODE_L2B_PRAM_C_LOAD_FAILURE 0x90220000 1317 #define FW_MSG_CODE_L2B_PRAM_X_LOAD_FAILURE 0x90230000 1318 #define FW_MSG_CODE_L2B_PRAM_U_LOAD_FAILURE 0x90240000 1319 #define FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS 0xa0100000 1320 #define FW_MSG_CODE_VRFY_OPT_MDL_INVLD_IMG 0xa0200000 1321 #define FW_MSG_CODE_VRFY_OPT_MDL_UNAPPROVED 0xa0300000 1322 #define FW_MSG_CODE_VF_DISABLED_DONE 0xb0000000 1323 #define FW_MSG_CODE_HW_SET_INVALID_IMAGE 0xb0100000 1324 1325 #define FW_MSG_CODE_AFEX_DRIVER_SETMAC_DONE 0xd0100000 1326 #define FW_MSG_CODE_AFEX_LISTGET_ACK 0xd1100000 1327 #define FW_MSG_CODE_AFEX_LISTSET_ACK 0xd2100000 1328 #define FW_MSG_CODE_AFEX_STATSGET_ACK 0xd3100000 1329 #define FW_MSG_CODE_AFEX_VIFSET_ACK 0xd4100000 1330 1331 #define FW_MSG_CODE_DRV_INFO_ACK 0xd8100000 1332 #define FW_MSG_CODE_DRV_INFO_NACK 0xd9100000 1333 1334 #define FW_MSG_CODE_EEE_RESULS_ACK 0xda100000 1335 1336 #define FW_MSG_CODE_SET_MF_BW_SENT 0xe0000000 1337 #define FW_MSG_CODE_SET_MF_BW_DONE 0xe1000000 1338 1339 #define FW_MSG_CODE_LINK_CHANGED_ACK 0x01100000 1340 1341 #define FW_MSG_CODE_LIC_CHALLENGE 0xff010000 1342 #define FW_MSG_CODE_LIC_RESPONSE 0xff020000 1343 #define FW_MSG_CODE_VIRT_MAC_PRIM 0xff030000 1344 #define FW_MSG_CODE_VIRT_MAC_ISCSI 0xff040000 1345 1346 #define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff 1347 1348 u32 fw_mb_param; 1349 1350 u32 drv_pulse_mb; 1351 #define DRV_PULSE_SEQ_MASK 0x00007fff 1352 #define DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000 1353 /* 1354 * The system time is in the format of 1355 * (year-2001)*12*32 + month*32 + day. 1356 */ 1357 #define DRV_PULSE_ALWAYS_ALIVE 0x00008000 1358 /* 1359 * Indicate to the firmware not to go into the 1360 * OS-absent when it is not getting driver pulse. 1361 * This is used for debugging as well for PXE(MBA). 1362 */ 1363 1364 u32 mcp_pulse_mb; 1365 #define MCP_PULSE_SEQ_MASK 0x00007fff 1366 #define MCP_PULSE_ALWAYS_ALIVE 0x00008000 1367 /* Indicates to the driver not to assert due to lack 1368 * of MCP response */ 1369 #define MCP_EVENT_MASK 0xffff0000 1370 #define MCP_EVENT_OTHER_DRIVER_RESET_REQ 0x00010000 1371 1372 u32 iscsi_boot_signature; 1373 u32 iscsi_boot_block_offset; 1374 1375 u32 drv_status; 1376 #define DRV_STATUS_PMF 0x00000001 1377 #define DRV_STATUS_VF_DISABLED 0x00000002 1378 #define DRV_STATUS_SET_MF_BW 0x00000004 1379 #define DRV_STATUS_LINK_EVENT 0x00000008 1380 1381 #define DRV_STATUS_DCC_EVENT_MASK 0x0000ff00 1382 #define DRV_STATUS_DCC_DISABLE_ENABLE_PF 0x00000100 1383 #define DRV_STATUS_DCC_BANDWIDTH_ALLOCATION 0x00000200 1384 #define DRV_STATUS_DCC_CHANGE_MAC_ADDRESS 0x00000400 1385 #define DRV_STATUS_DCC_RESERVED1 0x00000800 1386 #define DRV_STATUS_DCC_SET_PROTOCOL 0x00001000 1387 #define DRV_STATUS_DCC_SET_PRIORITY 0x00002000 1388 1389 #define DRV_STATUS_DCBX_EVENT_MASK 0x000f0000 1390 #define DRV_STATUS_DCBX_NEGOTIATION_RESULTS 0x00010000 1391 #define DRV_STATUS_AFEX_EVENT_MASK 0x03f00000 1392 #define DRV_STATUS_AFEX_LISTGET_REQ 0x00100000 1393 #define DRV_STATUS_AFEX_LISTSET_REQ 0x00200000 1394 #define DRV_STATUS_AFEX_STATSGET_REQ 0x00400000 1395 #define DRV_STATUS_AFEX_VIFSET_REQ 0x00800000 1396 1397 #define DRV_STATUS_DRV_INFO_REQ 0x04000000 1398 1399 #define DRV_STATUS_EEE_NEGOTIATION_RESULTS 0x08000000 1400 1401 u32 virt_mac_upper; 1402 #define VIRT_MAC_SIGN_MASK 0xffff0000 1403 #define VIRT_MAC_SIGNATURE 0x564d0000 1404 u32 virt_mac_lower; 1405 1406 }; 1407 1408 1409 /**************************************************************************** 1410 * Management firmware state * 1411 ****************************************************************************/ 1412 /* Allocate 440 bytes for management firmware */ 1413 #define MGMTFW_STATE_WORD_SIZE 110 1414 1415 struct mgmtfw_state { 1416 u32 opaque[MGMTFW_STATE_WORD_SIZE]; 1417 }; 1418 1419 1420 /**************************************************************************** 1421 * Multi-Function configuration * 1422 ****************************************************************************/ 1423 struct shared_mf_cfg { 1424 1425 u32 clp_mb; 1426 #define SHARED_MF_CLP_SET_DEFAULT 0x00000000 1427 /* set by CLP */ 1428 #define SHARED_MF_CLP_EXIT 0x00000001 1429 /* set by MCP */ 1430 #define SHARED_MF_CLP_EXIT_DONE 0x00010000 1431 1432 }; 1433 1434 struct port_mf_cfg { 1435 1436 u32 dynamic_cfg; /* device control channel */ 1437 #define PORT_MF_CFG_E1HOV_TAG_MASK 0x0000ffff 1438 #define PORT_MF_CFG_E1HOV_TAG_SHIFT 0 1439 #define PORT_MF_CFG_E1HOV_TAG_DEFAULT PORT_MF_CFG_E1HOV_TAG_MASK 1440 1441 u32 reserved[1]; 1442 1443 }; 1444 1445 struct func_mf_cfg { 1446 1447 u32 config; 1448 /* E/R/I/D */ 1449 /* function 0 of each port cannot be hidden */ 1450 #define FUNC_MF_CFG_FUNC_HIDE 0x00000001 1451 1452 #define FUNC_MF_CFG_PROTOCOL_MASK 0x00000006 1453 #define FUNC_MF_CFG_PROTOCOL_FCOE 0x00000000 1454 #define FUNC_MF_CFG_PROTOCOL_ETHERNET 0x00000002 1455 #define FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA 0x00000004 1456 #define FUNC_MF_CFG_PROTOCOL_ISCSI 0x00000006 1457 #define FUNC_MF_CFG_PROTOCOL_DEFAULT \ 1458 FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA 1459 1460 #define FUNC_MF_CFG_FUNC_DISABLED 0x00000008 1461 #define FUNC_MF_CFG_FUNC_DELETED 0x00000010 1462 1463 /* PRI */ 1464 /* 0 - low priority, 3 - high priority */ 1465 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK 0x00000300 1466 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT 8 1467 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_DEFAULT 0x00000000 1468 1469 /* MINBW, MAXBW */ 1470 /* value range - 0..100, increments in 100Mbps */ 1471 #define FUNC_MF_CFG_MIN_BW_MASK 0x00ff0000 1472 #define FUNC_MF_CFG_MIN_BW_SHIFT 16 1473 #define FUNC_MF_CFG_MIN_BW_DEFAULT 0x00000000 1474 #define FUNC_MF_CFG_MAX_BW_MASK 0xff000000 1475 #define FUNC_MF_CFG_MAX_BW_SHIFT 24 1476 #define FUNC_MF_CFG_MAX_BW_DEFAULT 0x64000000 1477 1478 u32 mac_upper; /* MAC */ 1479 #define FUNC_MF_CFG_UPPERMAC_MASK 0x0000ffff 1480 #define FUNC_MF_CFG_UPPERMAC_SHIFT 0 1481 #define FUNC_MF_CFG_UPPERMAC_DEFAULT FUNC_MF_CFG_UPPERMAC_MASK 1482 u32 mac_lower; 1483 #define FUNC_MF_CFG_LOWERMAC_DEFAULT 0xffffffff 1484 1485 u32 e1hov_tag; /* VNI */ 1486 #define FUNC_MF_CFG_E1HOV_TAG_MASK 0x0000ffff 1487 #define FUNC_MF_CFG_E1HOV_TAG_SHIFT 0 1488 #define FUNC_MF_CFG_E1HOV_TAG_DEFAULT FUNC_MF_CFG_E1HOV_TAG_MASK 1489 1490 /* afex default VLAN ID - 12 bits */ 1491 #define FUNC_MF_CFG_AFEX_VLAN_MASK 0x0fff0000 1492 #define FUNC_MF_CFG_AFEX_VLAN_SHIFT 16 1493 1494 u32 afex_config; 1495 #define FUNC_MF_CFG_AFEX_COS_FILTER_MASK 0x000000ff 1496 #define FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT 0 1497 #define FUNC_MF_CFG_AFEX_MBA_ENABLED_MASK 0x0000ff00 1498 #define FUNC_MF_CFG_AFEX_MBA_ENABLED_SHIFT 8 1499 #define FUNC_MF_CFG_AFEX_MBA_ENABLED_VAL 0x00000100 1500 #define FUNC_MF_CFG_AFEX_VLAN_MODE_MASK 0x000f0000 1501 #define FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT 16 1502 1503 u32 reserved; 1504 }; 1505 1506 enum mf_cfg_afex_vlan_mode { 1507 FUNC_MF_CFG_AFEX_VLAN_TRUNK_MODE = 0, 1508 FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE, 1509 FUNC_MF_CFG_AFEX_VLAN_TRUNK_TAG_NATIVE_MODE 1510 }; 1511 1512 /* This structure is not applicable and should not be accessed on 57711 */ 1513 struct func_ext_cfg { 1514 u32 func_cfg; 1515 #define MACP_FUNC_CFG_FLAGS_MASK 0x000000FF 1516 #define MACP_FUNC_CFG_FLAGS_SHIFT 0 1517 #define MACP_FUNC_CFG_FLAGS_ENABLED 0x00000001 1518 #define MACP_FUNC_CFG_FLAGS_ETHERNET 0x00000002 1519 #define MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD 0x00000004 1520 #define MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD 0x00000008 1521 1522 u32 iscsi_mac_addr_upper; 1523 u32 iscsi_mac_addr_lower; 1524 1525 u32 fcoe_mac_addr_upper; 1526 u32 fcoe_mac_addr_lower; 1527 1528 u32 fcoe_wwn_port_name_upper; 1529 u32 fcoe_wwn_port_name_lower; 1530 1531 u32 fcoe_wwn_node_name_upper; 1532 u32 fcoe_wwn_node_name_lower; 1533 1534 u32 preserve_data; 1535 #define MF_FUNC_CFG_PRESERVE_L2_MAC (1<<0) 1536 #define MF_FUNC_CFG_PRESERVE_ISCSI_MAC (1<<1) 1537 #define MF_FUNC_CFG_PRESERVE_FCOE_MAC (1<<2) 1538 #define MF_FUNC_CFG_PRESERVE_FCOE_WWN_P (1<<3) 1539 #define MF_FUNC_CFG_PRESERVE_FCOE_WWN_N (1<<4) 1540 #define MF_FUNC_CFG_PRESERVE_TX_BW (1<<5) 1541 }; 1542 1543 struct mf_cfg { 1544 1545 struct shared_mf_cfg shared_mf_config; /* 0x4 */ 1546 /* 0x8*2*2=0x20 */ 1547 struct port_mf_cfg port_mf_config[NVM_PATH_MAX][PORT_MAX]; 1548 /* for all chips, there are 8 mf functions */ 1549 struct func_mf_cfg func_mf_config[E1H_FUNC_MAX]; /* 0x18 * 8 = 0xc0 */ 1550 /* 1551 * Extended configuration per function - this array does not exist and 1552 * should not be accessed on 57711 1553 */ 1554 struct func_ext_cfg func_ext_config[E1H_FUNC_MAX]; /* 0x28 * 8 = 0x140*/ 1555 }; /* 0x224 */ 1556 1557 /**************************************************************************** 1558 * Shared Memory Region * 1559 ****************************************************************************/ 1560 struct shmem_region { /* SharedMem Offset (size) */ 1561 1562 u32 validity_map[PORT_MAX]; /* 0x0 (4*2 = 0x8) */ 1563 #define SHR_MEM_FORMAT_REV_MASK 0xff000000 1564 #define SHR_MEM_FORMAT_REV_ID ('A'<<24) 1565 /* validity bits */ 1566 #define SHR_MEM_VALIDITY_PCI_CFG 0x00100000 1567 #define SHR_MEM_VALIDITY_MB 0x00200000 1568 #define SHR_MEM_VALIDITY_DEV_INFO 0x00400000 1569 #define SHR_MEM_VALIDITY_RESERVED 0x00000007 1570 /* One licensing bit should be set */ 1571 #define SHR_MEM_VALIDITY_LIC_KEY_IN_EFFECT_MASK 0x00000038 1572 #define SHR_MEM_VALIDITY_LIC_MANUF_KEY_IN_EFFECT 0x00000008 1573 #define SHR_MEM_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT 0x00000010 1574 #define SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT 0x00000020 1575 /* Active MFW */ 1576 #define SHR_MEM_VALIDITY_ACTIVE_MFW_UNKNOWN 0x00000000 1577 #define SHR_MEM_VALIDITY_ACTIVE_MFW_MASK 0x000001c0 1578 #define SHR_MEM_VALIDITY_ACTIVE_MFW_IPMI 0x00000040 1579 #define SHR_MEM_VALIDITY_ACTIVE_MFW_UMP 0x00000080 1580 #define SHR_MEM_VALIDITY_ACTIVE_MFW_NCSI 0x000000c0 1581 #define SHR_MEM_VALIDITY_ACTIVE_MFW_NONE 0x000001c0 1582 1583 struct shm_dev_info dev_info; /* 0x8 (0x438) */ 1584 1585 struct license_key drv_lic_key[PORT_MAX]; /* 0x440 (52*2=0x68) */ 1586 1587 /* FW information (for internal FW use) */ 1588 u32 fw_info_fio_offset; /* 0x4a8 (0x4) */ 1589 struct mgmtfw_state mgmtfw_state; /* 0x4ac (0x1b8) */ 1590 1591 struct drv_port_mb port_mb[PORT_MAX]; /* 0x664 (16*2=0x20) */ 1592 1593 #ifdef BMAPI 1594 /* This is a variable length array */ 1595 /* the number of function depends on the chip type */ 1596 struct drv_func_mb func_mb[1]; /* 0x684 (44*2/4/8=0x58/0xb0/0x160) */ 1597 #else 1598 /* the number of function depends on the chip type */ 1599 struct drv_func_mb func_mb[]; /* 0x684 (44*2/4/8=0x58/0xb0/0x160) */ 1600 #endif /* BMAPI */ 1601 1602 }; /* 57710 = 0x6dc | 57711 = 0x7E4 | 57712 = 0x734 */ 1603 1604 /**************************************************************************** 1605 * Shared Memory 2 Region * 1606 ****************************************************************************/ 1607 /* The fw_flr_ack is actually built in the following way: */ 1608 /* 8 bit: PF ack */ 1609 /* 64 bit: VF ack */ 1610 /* 8 bit: ios_dis_ack */ 1611 /* In order to maintain endianity in the mailbox hsi, we want to keep using */ 1612 /* u32. The fw must have the VF right after the PF since this is how it */ 1613 /* access arrays(it expects always the VF to reside after the PF, and that */ 1614 /* makes the calculation much easier for it. ) */ 1615 /* In order to answer both limitations, and keep the struct small, the code */ 1616 /* will abuse the structure defined here to achieve the actual partition */ 1617 /* above */ 1618 /****************************************************************************/ 1619 struct fw_flr_ack { 1620 u32 pf_ack; 1621 u32 vf_ack[1]; 1622 u32 iov_dis_ack; 1623 }; 1624 1625 struct fw_flr_mb { 1626 u32 aggint; 1627 u32 opgen_addr; 1628 struct fw_flr_ack ack; 1629 }; 1630 1631 struct eee_remote_vals { 1632 u32 tx_tw; 1633 u32 rx_tw; 1634 }; 1635 1636 /**** SUPPORT FOR SHMEM ARRRAYS *** 1637 * The SHMEM HSI is aligned on 32 bit boundaries which makes it difficult to 1638 * define arrays with storage types smaller then unsigned dwords. 1639 * The macros below add generic support for SHMEM arrays with numeric elements 1640 * that can span 2,4,8 or 16 bits. The array underlying type is a 32 bit dword 1641 * array with individual bit-filed elements accessed using shifts and masks. 1642 * 1643 */ 1644 1645 /* eb is the bitwidth of a single element */ 1646 #define SHMEM_ARRAY_MASK(eb) ((1<<(eb))-1) 1647 #define SHMEM_ARRAY_ENTRY(i, eb) ((i)/(32/(eb))) 1648 1649 /* the bit-position macro allows the used to flip the order of the arrays 1650 * elements on a per byte or word boundary. 1651 * 1652 * example: an array with 8 entries each 4 bit wide. This array will fit into 1653 * a single dword. The diagrmas below show the array order of the nibbles. 1654 * 1655 * SHMEM_ARRAY_BITPOS(i, 4, 4) defines the stadard ordering: 1656 * 1657 * | | | | 1658 * 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 1659 * | | | | 1660 * 1661 * SHMEM_ARRAY_BITPOS(i, 4, 8) defines a flip ordering per byte: 1662 * 1663 * | | | | 1664 * 1 | 0 | 3 | 2 | 5 | 4 | 7 | 6 | 1665 * | | | | 1666 * 1667 * SHMEM_ARRAY_BITPOS(i, 4, 16) defines a flip ordering per word: 1668 * 1669 * | | | | 1670 * 3 | 2 | 1 | 0 | 7 | 6 | 5 | 4 | 1671 * | | | | 1672 */ 1673 #define SHMEM_ARRAY_BITPOS(i, eb, fb) \ 1674 ((((32/(fb)) - 1 - ((i)/((fb)/(eb))) % (32/(fb))) * (fb)) + \ 1675 (((i)%((fb)/(eb))) * (eb))) 1676 1677 #define SHMEM_ARRAY_GET(a, i, eb, fb) \ 1678 ((a[SHMEM_ARRAY_ENTRY(i, eb)] >> SHMEM_ARRAY_BITPOS(i, eb, fb)) & \ 1679 SHMEM_ARRAY_MASK(eb)) 1680 1681 #define SHMEM_ARRAY_SET(a, i, eb, fb, val) \ 1682 do { \ 1683 a[SHMEM_ARRAY_ENTRY(i, eb)] &= ~(SHMEM_ARRAY_MASK(eb) << \ 1684 SHMEM_ARRAY_BITPOS(i, eb, fb)); \ 1685 a[SHMEM_ARRAY_ENTRY(i, eb)] |= (((val) & SHMEM_ARRAY_MASK(eb)) << \ 1686 SHMEM_ARRAY_BITPOS(i, eb, fb)); \ 1687 } while (0) 1688 1689 1690 /****START OF DCBX STRUCTURES DECLARATIONS****/ 1691 #define DCBX_MAX_NUM_PRI_PG_ENTRIES 8 1692 #define DCBX_PRI_PG_BITWIDTH 4 1693 #define DCBX_PRI_PG_FBITS 8 1694 #define DCBX_PRI_PG_GET(a, i) \ 1695 SHMEM_ARRAY_GET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS) 1696 #define DCBX_PRI_PG_SET(a, i, val) \ 1697 SHMEM_ARRAY_SET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS, val) 1698 #define DCBX_MAX_NUM_PG_BW_ENTRIES 8 1699 #define DCBX_BW_PG_BITWIDTH 8 1700 #define DCBX_PG_BW_GET(a, i) \ 1701 SHMEM_ARRAY_GET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH) 1702 #define DCBX_PG_BW_SET(a, i, val) \ 1703 SHMEM_ARRAY_SET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH, val) 1704 #define DCBX_STRICT_PRI_PG 15 1705 #define DCBX_MAX_APP_PROTOCOL 16 1706 #define FCOE_APP_IDX 0 1707 #define ISCSI_APP_IDX 1 1708 #define PREDEFINED_APP_IDX_MAX 2 1709 1710 1711 /* Big/Little endian have the same representation. */ 1712 struct dcbx_ets_feature { 1713 /* 1714 * For Admin MIB - is this feature supported by the 1715 * driver | For Local MIB - should this feature be enabled. 1716 */ 1717 u32 enabled; 1718 u32 pg_bw_tbl[2]; 1719 u32 pri_pg_tbl[1]; 1720 }; 1721 1722 /* Driver structure in LE */ 1723 struct dcbx_pfc_feature { 1724 #ifdef __BIG_ENDIAN 1725 u8 pri_en_bitmap; 1726 #define DCBX_PFC_PRI_0 0x01 1727 #define DCBX_PFC_PRI_1 0x02 1728 #define DCBX_PFC_PRI_2 0x04 1729 #define DCBX_PFC_PRI_3 0x08 1730 #define DCBX_PFC_PRI_4 0x10 1731 #define DCBX_PFC_PRI_5 0x20 1732 #define DCBX_PFC_PRI_6 0x40 1733 #define DCBX_PFC_PRI_7 0x80 1734 u8 pfc_caps; 1735 u8 reserved; 1736 u8 enabled; 1737 #elif defined(__LITTLE_ENDIAN) 1738 u8 enabled; 1739 u8 reserved; 1740 u8 pfc_caps; 1741 u8 pri_en_bitmap; 1742 #define DCBX_PFC_PRI_0 0x01 1743 #define DCBX_PFC_PRI_1 0x02 1744 #define DCBX_PFC_PRI_2 0x04 1745 #define DCBX_PFC_PRI_3 0x08 1746 #define DCBX_PFC_PRI_4 0x10 1747 #define DCBX_PFC_PRI_5 0x20 1748 #define DCBX_PFC_PRI_6 0x40 1749 #define DCBX_PFC_PRI_7 0x80 1750 #endif 1751 }; 1752 1753 struct dcbx_app_priority_entry { 1754 #ifdef __BIG_ENDIAN 1755 u16 app_id; 1756 u8 pri_bitmap; 1757 u8 appBitfield; 1758 #define DCBX_APP_ENTRY_VALID 0x01 1759 #define DCBX_APP_ENTRY_SF_MASK 0x30 1760 #define DCBX_APP_ENTRY_SF_SHIFT 4 1761 #define DCBX_APP_SF_ETH_TYPE 0x10 1762 #define DCBX_APP_SF_PORT 0x20 1763 #elif defined(__LITTLE_ENDIAN) 1764 u8 appBitfield; 1765 #define DCBX_APP_ENTRY_VALID 0x01 1766 #define DCBX_APP_ENTRY_SF_MASK 0x30 1767 #define DCBX_APP_ENTRY_SF_SHIFT 4 1768 #define DCBX_APP_SF_ETH_TYPE 0x10 1769 #define DCBX_APP_SF_PORT 0x20 1770 u8 pri_bitmap; 1771 u16 app_id; 1772 #endif 1773 }; 1774 1775 1776 /* FW structure in BE */ 1777 struct dcbx_app_priority_feature { 1778 #ifdef __BIG_ENDIAN 1779 u8 reserved; 1780 u8 default_pri; 1781 u8 tc_supported; 1782 u8 enabled; 1783 #elif defined(__LITTLE_ENDIAN) 1784 u8 enabled; 1785 u8 tc_supported; 1786 u8 default_pri; 1787 u8 reserved; 1788 #endif 1789 struct dcbx_app_priority_entry app_pri_tbl[DCBX_MAX_APP_PROTOCOL]; 1790 }; 1791 1792 /* FW structure in BE */ 1793 struct dcbx_features { 1794 /* PG feature */ 1795 struct dcbx_ets_feature ets; 1796 /* PFC feature */ 1797 struct dcbx_pfc_feature pfc; 1798 /* APP feature */ 1799 struct dcbx_app_priority_feature app; 1800 }; 1801 1802 /* LLDP protocol parameters */ 1803 /* FW structure in BE */ 1804 struct lldp_params { 1805 #ifdef __BIG_ENDIAN 1806 u8 msg_fast_tx_interval; 1807 u8 msg_tx_hold; 1808 u8 msg_tx_interval; 1809 u8 admin_status; 1810 #define LLDP_TX_ONLY 0x01 1811 #define LLDP_RX_ONLY 0x02 1812 #define LLDP_TX_RX 0x03 1813 #define LLDP_DISABLED 0x04 1814 u8 reserved1; 1815 u8 tx_fast; 1816 u8 tx_crd_max; 1817 u8 tx_crd; 1818 #elif defined(__LITTLE_ENDIAN) 1819 u8 admin_status; 1820 #define LLDP_TX_ONLY 0x01 1821 #define LLDP_RX_ONLY 0x02 1822 #define LLDP_TX_RX 0x03 1823 #define LLDP_DISABLED 0x04 1824 u8 msg_tx_interval; 1825 u8 msg_tx_hold; 1826 u8 msg_fast_tx_interval; 1827 u8 tx_crd; 1828 u8 tx_crd_max; 1829 u8 tx_fast; 1830 u8 reserved1; 1831 #endif 1832 #define REM_CHASSIS_ID_STAT_LEN 4 1833 #define REM_PORT_ID_STAT_LEN 4 1834 /* Holds remote Chassis ID TLV header, subtype and 9B of payload. */ 1835 u32 peer_chassis_id[REM_CHASSIS_ID_STAT_LEN]; 1836 /* Holds remote Port ID TLV header, subtype and 9B of payload. */ 1837 u32 peer_port_id[REM_PORT_ID_STAT_LEN]; 1838 }; 1839 1840 struct lldp_dcbx_stat { 1841 #define LOCAL_CHASSIS_ID_STAT_LEN 2 1842 #define LOCAL_PORT_ID_STAT_LEN 2 1843 /* Holds local Chassis ID 8B payload of constant subtype 4. */ 1844 u32 local_chassis_id[LOCAL_CHASSIS_ID_STAT_LEN]; 1845 /* Holds local Port ID 8B payload of constant subtype 3. */ 1846 u32 local_port_id[LOCAL_PORT_ID_STAT_LEN]; 1847 /* Number of DCBX frames transmitted. */ 1848 u32 num_tx_dcbx_pkts; 1849 /* Number of DCBX frames received. */ 1850 u32 num_rx_dcbx_pkts; 1851 }; 1852 1853 /* ADMIN MIB - DCBX local machine default configuration. */ 1854 struct lldp_admin_mib { 1855 u32 ver_cfg_flags; 1856 #define DCBX_ETS_CONFIG_TX_ENABLED 0x00000001 1857 #define DCBX_PFC_CONFIG_TX_ENABLED 0x00000002 1858 #define DCBX_APP_CONFIG_TX_ENABLED 0x00000004 1859 #define DCBX_ETS_RECO_TX_ENABLED 0x00000008 1860 #define DCBX_ETS_RECO_VALID 0x00000010 1861 #define DCBX_ETS_WILLING 0x00000020 1862 #define DCBX_PFC_WILLING 0x00000040 1863 #define DCBX_APP_WILLING 0x00000080 1864 #define DCBX_VERSION_CEE 0x00000100 1865 #define DCBX_VERSION_IEEE 0x00000200 1866 #define DCBX_DCBX_ENABLED 0x00000400 1867 #define DCBX_CEE_VERSION_MASK 0x0000f000 1868 #define DCBX_CEE_VERSION_SHIFT 12 1869 #define DCBX_CEE_MAX_VERSION_MASK 0x000f0000 1870 #define DCBX_CEE_MAX_VERSION_SHIFT 16 1871 struct dcbx_features features; 1872 }; 1873 1874 /* REMOTE MIB - remote machine DCBX configuration. */ 1875 struct lldp_remote_mib { 1876 u32 prefix_seq_num; 1877 u32 flags; 1878 #define DCBX_ETS_TLV_RX 0x00000001 1879 #define DCBX_PFC_TLV_RX 0x00000002 1880 #define DCBX_APP_TLV_RX 0x00000004 1881 #define DCBX_ETS_RX_ERROR 0x00000010 1882 #define DCBX_PFC_RX_ERROR 0x00000020 1883 #define DCBX_APP_RX_ERROR 0x00000040 1884 #define DCBX_ETS_REM_WILLING 0x00000100 1885 #define DCBX_PFC_REM_WILLING 0x00000200 1886 #define DCBX_APP_REM_WILLING 0x00000400 1887 #define DCBX_REMOTE_ETS_RECO_VALID 0x00001000 1888 #define DCBX_REMOTE_MIB_VALID 0x00002000 1889 struct dcbx_features features; 1890 u32 suffix_seq_num; 1891 }; 1892 1893 /* LOCAL MIB - operational DCBX configuration - transmitted on Tx LLDPDU. */ 1894 struct lldp_local_mib { 1895 u32 prefix_seq_num; 1896 /* Indicates if there is mismatch with negotiation results. */ 1897 u32 error; 1898 #define DCBX_LOCAL_ETS_ERROR 0x00000001 1899 #define DCBX_LOCAL_PFC_ERROR 0x00000002 1900 #define DCBX_LOCAL_APP_ERROR 0x00000004 1901 #define DCBX_LOCAL_PFC_MISMATCH 0x00000010 1902 #define DCBX_LOCAL_APP_MISMATCH 0x00000020 1903 #define DCBX_REMOTE_MIB_ERROR 0x00000040 1904 #define DCBX_REMOTE_ETS_TLV_NOT_FOUND 0x00000080 1905 #define DCBX_REMOTE_PFC_TLV_NOT_FOUND 0x00000100 1906 #define DCBX_REMOTE_APP_TLV_NOT_FOUND 0x00000200 1907 struct dcbx_features features; 1908 u32 suffix_seq_num; 1909 }; 1910 /***END OF DCBX STRUCTURES DECLARATIONS***/ 1911 1912 struct ncsi_oem_fcoe_features { 1913 u32 fcoe_features1; 1914 #define FCOE_FEATURES1_IOS_PER_CONNECTION_MASK 0x0000FFFF 1915 #define FCOE_FEATURES1_IOS_PER_CONNECTION_OFFSET 0 1916 1917 #define FCOE_FEATURES1_LOGINS_PER_PORT_MASK 0xFFFF0000 1918 #define FCOE_FEATURES1_LOGINS_PER_PORT_OFFSET 16 1919 1920 u32 fcoe_features2; 1921 #define FCOE_FEATURES2_EXCHANGES_MASK 0x0000FFFF 1922 #define FCOE_FEATURES2_EXCHANGES_OFFSET 0 1923 1924 #define FCOE_FEATURES2_NPIV_WWN_PER_PORT_MASK 0xFFFF0000 1925 #define FCOE_FEATURES2_NPIV_WWN_PER_PORT_OFFSET 16 1926 1927 u32 fcoe_features3; 1928 #define FCOE_FEATURES3_TARGETS_SUPPORTED_MASK 0x0000FFFF 1929 #define FCOE_FEATURES3_TARGETS_SUPPORTED_OFFSET 0 1930 1931 #define FCOE_FEATURES3_OUTSTANDING_COMMANDS_MASK 0xFFFF0000 1932 #define FCOE_FEATURES3_OUTSTANDING_COMMANDS_OFFSET 16 1933 1934 u32 fcoe_features4; 1935 #define FCOE_FEATURES4_FEATURE_SETTINGS_MASK 0x0000000F 1936 #define FCOE_FEATURES4_FEATURE_SETTINGS_OFFSET 0 1937 }; 1938 1939 struct ncsi_oem_data { 1940 u32 driver_version[4]; 1941 struct ncsi_oem_fcoe_features ncsi_oem_fcoe_features; 1942 }; 1943 1944 struct shmem2_region { 1945 1946 u32 size; /* 0x0000 */ 1947 1948 u32 dcc_support; /* 0x0004 */ 1949 #define SHMEM_DCC_SUPPORT_NONE 0x00000000 1950 #define SHMEM_DCC_SUPPORT_DISABLE_ENABLE_PF_TLV 0x00000001 1951 #define SHMEM_DCC_SUPPORT_BANDWIDTH_ALLOCATION_TLV 0x00000004 1952 #define SHMEM_DCC_SUPPORT_CHANGE_MAC_ADDRESS_TLV 0x00000008 1953 #define SHMEM_DCC_SUPPORT_SET_PROTOCOL_TLV 0x00000040 1954 #define SHMEM_DCC_SUPPORT_SET_PRIORITY_TLV 0x00000080 1955 1956 u32 ext_phy_fw_version2[PORT_MAX]; /* 0x0008 */ 1957 /* 1958 * For backwards compatibility, if the mf_cfg_addr does not exist 1959 * (the size filed is smaller than 0xc) the mf_cfg resides at the 1960 * end of struct shmem_region 1961 */ 1962 u32 mf_cfg_addr; /* 0x0010 */ 1963 #define SHMEM_MF_CFG_ADDR_NONE 0x00000000 1964 1965 struct fw_flr_mb flr_mb; /* 0x0014 */ 1966 u32 dcbx_lldp_params_offset; /* 0x0028 */ 1967 #define SHMEM_LLDP_DCBX_PARAMS_NONE 0x00000000 1968 u32 dcbx_neg_res_offset; /* 0x002c */ 1969 #define SHMEM_DCBX_NEG_RES_NONE 0x00000000 1970 u32 dcbx_remote_mib_offset; /* 0x0030 */ 1971 #define SHMEM_DCBX_REMOTE_MIB_NONE 0x00000000 1972 /* 1973 * The other shmemX_base_addr holds the other path's shmem address 1974 * required for example in case of common phy init, or for path1 to know 1975 * the address of mcp debug trace which is located in offset from shmem 1976 * of path0 1977 */ 1978 u32 other_shmem_base_addr; /* 0x0034 */ 1979 u32 other_shmem2_base_addr; /* 0x0038 */ 1980 /* 1981 * mcp_vf_disabled is set by the MCP to indicate the driver about VFs 1982 * which were disabled/flred 1983 */ 1984 u32 mcp_vf_disabled[E2_VF_MAX / 32]; /* 0x003c */ 1985 1986 /* 1987 * drv_ack_vf_disabled is set by the PF driver to ack handled disabled 1988 * VFs 1989 */ 1990 u32 drv_ack_vf_disabled[E2_FUNC_MAX][E2_VF_MAX / 32]; /* 0x0044 */ 1991 1992 u32 dcbx_lldp_dcbx_stat_offset; /* 0x0064 */ 1993 #define SHMEM_LLDP_DCBX_STAT_NONE 0x00000000 1994 1995 /* 1996 * edebug_driver_if field is used to transfer messages between edebug 1997 * app to the driver through shmem2. 1998 * 1999 * message format: 2000 * bits 0-2 - function number / instance of driver to perform request 2001 * bits 3-5 - op code / is_ack? 2002 * bits 6-63 - data 2003 */ 2004 u32 edebug_driver_if[2]; /* 0x0068 */ 2005 #define EDEBUG_DRIVER_IF_OP_CODE_GET_PHYS_ADDR 1 2006 #define EDEBUG_DRIVER_IF_OP_CODE_GET_BUS_ADDR 2 2007 #define EDEBUG_DRIVER_IF_OP_CODE_DISABLE_STAT 3 2008 2009 u32 nvm_retain_bitmap_addr; /* 0x0070 */ 2010 2011 /* afex support of that driver */ 2012 u32 afex_driver_support; /* 0x0074 */ 2013 #define SHMEM_AFEX_VERSION_MASK 0x100f 2014 #define SHMEM_AFEX_SUPPORTED_VERSION_ONE 0x1001 2015 #define SHMEM_AFEX_REDUCED_DRV_LOADED 0x8000 2016 2017 /* driver receives addr in scratchpad to which it should respond */ 2018 u32 afex_scratchpad_addr_to_write[E2_FUNC_MAX]; 2019 2020 /* generic params from MCP to driver (value depends on the msg sent 2021 * to driver 2022 */ 2023 u32 afex_param1_to_driver[E2_FUNC_MAX]; /* 0x0088 */ 2024 u32 afex_param2_to_driver[E2_FUNC_MAX]; /* 0x0098 */ 2025 2026 u32 swim_base_addr; /* 0x0108 */ 2027 u32 swim_funcs; 2028 u32 swim_main_cb; 2029 2030 /* bitmap notifying which VIF profiles stored in nvram are enabled by 2031 * switch 2032 */ 2033 u32 afex_profiles_enabled[2]; 2034 2035 /* generic flags controlled by the driver */ 2036 u32 drv_flags; 2037 #define DRV_FLAGS_DCB_CONFIGURED 0x1 2038 2039 /* pointer to extended dev_info shared data copied from nvm image */ 2040 u32 extended_dev_info_shared_addr; 2041 u32 ncsi_oem_data_addr; 2042 2043 u32 ocsd_host_addr; /* initialized by option ROM */ 2044 u32 ocbb_host_addr; /* initialized by option ROM */ 2045 u32 ocsd_req_update_interval; /* initialized by option ROM */ 2046 u32 temperature_in_half_celsius; 2047 u32 glob_struct_in_host; 2048 2049 u32 dcbx_neg_res_ext_offset; 2050 #define SHMEM_DCBX_NEG_RES_EXT_NONE 0x00000000 2051 2052 u32 drv_capabilities_flag[E2_FUNC_MAX]; 2053 #define DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED 0x00000001 2054 #define DRV_FLAGS_CAPABILITIES_LOADED_L2 0x00000002 2055 #define DRV_FLAGS_CAPABILITIES_LOADED_FCOE 0x00000004 2056 #define DRV_FLAGS_CAPABILITIES_LOADED_ISCSI 0x00000008 2057 2058 u32 extended_dev_info_shared_cfg_size; 2059 2060 u32 dcbx_en[PORT_MAX]; 2061 2062 /* The offset points to the multi threaded meta structure */ 2063 u32 multi_thread_data_offset; 2064 2065 /* address of DMAable host address holding values from the drivers */ 2066 u32 drv_info_host_addr_lo; 2067 u32 drv_info_host_addr_hi; 2068 2069 /* general values written by the MFW (such as current version) */ 2070 u32 drv_info_control; 2071 #define DRV_INFO_CONTROL_VER_MASK 0x000000ff 2072 #define DRV_INFO_CONTROL_VER_SHIFT 0 2073 #define DRV_INFO_CONTROL_OP_CODE_MASK 0x0000ff00 2074 #define DRV_INFO_CONTROL_OP_CODE_SHIFT 8 2075 u32 ibft_host_addr; /* initialized by option ROM */ 2076 struct eee_remote_vals eee_remote_vals[PORT_MAX]; 2077 u32 reserved[E2_FUNC_MAX]; 2078 2079 2080 /* the status of EEE auto-negotiation 2081 * bits 15:0 the configured tx-lpi entry timer value. Depends on bit 31. 2082 * bits 19:16 the supported modes for EEE. 2083 * bits 23:20 the speeds advertised for EEE. 2084 * bits 27:24 the speeds the Link partner advertised for EEE. 2085 * The supported/adv. modes in bits 27:19 originate from the 2086 * SHMEM_EEE_XXX_ADV definitions (where XXX is replaced by speed). 2087 * bit 28 when 1'b1 EEE was requested. 2088 * bit 29 when 1'b1 tx lpi was requested. 2089 * bit 30 when 1'b1 EEE was negotiated. Tx lpi will be asserted iff 2090 * 30:29 are 2'b11. 2091 * bit 31 when 1'b0 bits 15:0 contain a PORT_FEAT_CFG_EEE_ define as 2092 * value. When 1'b1 those bits contains a value times 16 microseconds. 2093 */ 2094 u32 eee_status[PORT_MAX]; 2095 #define SHMEM_EEE_TIMER_MASK 0x0000ffff 2096 #define SHMEM_EEE_SUPPORTED_MASK 0x000f0000 2097 #define SHMEM_EEE_SUPPORTED_SHIFT 16 2098 #define SHMEM_EEE_ADV_STATUS_MASK 0x00f00000 2099 #define SHMEM_EEE_100M_ADV (1<<0) 2100 #define SHMEM_EEE_1G_ADV (1<<1) 2101 #define SHMEM_EEE_10G_ADV (1<<2) 2102 #define SHMEM_EEE_ADV_STATUS_SHIFT 20 2103 #define SHMEM_EEE_LP_ADV_STATUS_MASK 0x0f000000 2104 #define SHMEM_EEE_LP_ADV_STATUS_SHIFT 24 2105 #define SHMEM_EEE_REQUESTED_BIT 0x10000000 2106 #define SHMEM_EEE_LPI_REQUESTED_BIT 0x20000000 2107 #define SHMEM_EEE_ACTIVE_BIT 0x40000000 2108 #define SHMEM_EEE_TIME_OUTPUT_BIT 0x80000000 2109 2110 u32 sizeof_port_stats; 2111 }; 2112 2113 2114 struct emac_stats { 2115 u32 rx_stat_ifhcinoctets; 2116 u32 rx_stat_ifhcinbadoctets; 2117 u32 rx_stat_etherstatsfragments; 2118 u32 rx_stat_ifhcinucastpkts; 2119 u32 rx_stat_ifhcinmulticastpkts; 2120 u32 rx_stat_ifhcinbroadcastpkts; 2121 u32 rx_stat_dot3statsfcserrors; 2122 u32 rx_stat_dot3statsalignmenterrors; 2123 u32 rx_stat_dot3statscarriersenseerrors; 2124 u32 rx_stat_xonpauseframesreceived; 2125 u32 rx_stat_xoffpauseframesreceived; 2126 u32 rx_stat_maccontrolframesreceived; 2127 u32 rx_stat_xoffstateentered; 2128 u32 rx_stat_dot3statsframestoolong; 2129 u32 rx_stat_etherstatsjabbers; 2130 u32 rx_stat_etherstatsundersizepkts; 2131 u32 rx_stat_etherstatspkts64octets; 2132 u32 rx_stat_etherstatspkts65octetsto127octets; 2133 u32 rx_stat_etherstatspkts128octetsto255octets; 2134 u32 rx_stat_etherstatspkts256octetsto511octets; 2135 u32 rx_stat_etherstatspkts512octetsto1023octets; 2136 u32 rx_stat_etherstatspkts1024octetsto1522octets; 2137 u32 rx_stat_etherstatspktsover1522octets; 2138 2139 u32 rx_stat_falsecarriererrors; 2140 2141 u32 tx_stat_ifhcoutoctets; 2142 u32 tx_stat_ifhcoutbadoctets; 2143 u32 tx_stat_etherstatscollisions; 2144 u32 tx_stat_outxonsent; 2145 u32 tx_stat_outxoffsent; 2146 u32 tx_stat_flowcontroldone; 2147 u32 tx_stat_dot3statssinglecollisionframes; 2148 u32 tx_stat_dot3statsmultiplecollisionframes; 2149 u32 tx_stat_dot3statsdeferredtransmissions; 2150 u32 tx_stat_dot3statsexcessivecollisions; 2151 u32 tx_stat_dot3statslatecollisions; 2152 u32 tx_stat_ifhcoutucastpkts; 2153 u32 tx_stat_ifhcoutmulticastpkts; 2154 u32 tx_stat_ifhcoutbroadcastpkts; 2155 u32 tx_stat_etherstatspkts64octets; 2156 u32 tx_stat_etherstatspkts65octetsto127octets; 2157 u32 tx_stat_etherstatspkts128octetsto255octets; 2158 u32 tx_stat_etherstatspkts256octetsto511octets; 2159 u32 tx_stat_etherstatspkts512octetsto1023octets; 2160 u32 tx_stat_etherstatspkts1024octetsto1522octets; 2161 u32 tx_stat_etherstatspktsover1522octets; 2162 u32 tx_stat_dot3statsinternalmactransmiterrors; 2163 }; 2164 2165 2166 struct bmac1_stats { 2167 u32 tx_stat_gtpkt_lo; 2168 u32 tx_stat_gtpkt_hi; 2169 u32 tx_stat_gtxpf_lo; 2170 u32 tx_stat_gtxpf_hi; 2171 u32 tx_stat_gtfcs_lo; 2172 u32 tx_stat_gtfcs_hi; 2173 u32 tx_stat_gtmca_lo; 2174 u32 tx_stat_gtmca_hi; 2175 u32 tx_stat_gtbca_lo; 2176 u32 tx_stat_gtbca_hi; 2177 u32 tx_stat_gtfrg_lo; 2178 u32 tx_stat_gtfrg_hi; 2179 u32 tx_stat_gtovr_lo; 2180 u32 tx_stat_gtovr_hi; 2181 u32 tx_stat_gt64_lo; 2182 u32 tx_stat_gt64_hi; 2183 u32 tx_stat_gt127_lo; 2184 u32 tx_stat_gt127_hi; 2185 u32 tx_stat_gt255_lo; 2186 u32 tx_stat_gt255_hi; 2187 u32 tx_stat_gt511_lo; 2188 u32 tx_stat_gt511_hi; 2189 u32 tx_stat_gt1023_lo; 2190 u32 tx_stat_gt1023_hi; 2191 u32 tx_stat_gt1518_lo; 2192 u32 tx_stat_gt1518_hi; 2193 u32 tx_stat_gt2047_lo; 2194 u32 tx_stat_gt2047_hi; 2195 u32 tx_stat_gt4095_lo; 2196 u32 tx_stat_gt4095_hi; 2197 u32 tx_stat_gt9216_lo; 2198 u32 tx_stat_gt9216_hi; 2199 u32 tx_stat_gt16383_lo; 2200 u32 tx_stat_gt16383_hi; 2201 u32 tx_stat_gtmax_lo; 2202 u32 tx_stat_gtmax_hi; 2203 u32 tx_stat_gtufl_lo; 2204 u32 tx_stat_gtufl_hi; 2205 u32 tx_stat_gterr_lo; 2206 u32 tx_stat_gterr_hi; 2207 u32 tx_stat_gtbyt_lo; 2208 u32 tx_stat_gtbyt_hi; 2209 2210 u32 rx_stat_gr64_lo; 2211 u32 rx_stat_gr64_hi; 2212 u32 rx_stat_gr127_lo; 2213 u32 rx_stat_gr127_hi; 2214 u32 rx_stat_gr255_lo; 2215 u32 rx_stat_gr255_hi; 2216 u32 rx_stat_gr511_lo; 2217 u32 rx_stat_gr511_hi; 2218 u32 rx_stat_gr1023_lo; 2219 u32 rx_stat_gr1023_hi; 2220 u32 rx_stat_gr1518_lo; 2221 u32 rx_stat_gr1518_hi; 2222 u32 rx_stat_gr2047_lo; 2223 u32 rx_stat_gr2047_hi; 2224 u32 rx_stat_gr4095_lo; 2225 u32 rx_stat_gr4095_hi; 2226 u32 rx_stat_gr9216_lo; 2227 u32 rx_stat_gr9216_hi; 2228 u32 rx_stat_gr16383_lo; 2229 u32 rx_stat_gr16383_hi; 2230 u32 rx_stat_grmax_lo; 2231 u32 rx_stat_grmax_hi; 2232 u32 rx_stat_grpkt_lo; 2233 u32 rx_stat_grpkt_hi; 2234 u32 rx_stat_grfcs_lo; 2235 u32 rx_stat_grfcs_hi; 2236 u32 rx_stat_grmca_lo; 2237 u32 rx_stat_grmca_hi; 2238 u32 rx_stat_grbca_lo; 2239 u32 rx_stat_grbca_hi; 2240 u32 rx_stat_grxcf_lo; 2241 u32 rx_stat_grxcf_hi; 2242 u32 rx_stat_grxpf_lo; 2243 u32 rx_stat_grxpf_hi; 2244 u32 rx_stat_grxuo_lo; 2245 u32 rx_stat_grxuo_hi; 2246 u32 rx_stat_grjbr_lo; 2247 u32 rx_stat_grjbr_hi; 2248 u32 rx_stat_grovr_lo; 2249 u32 rx_stat_grovr_hi; 2250 u32 rx_stat_grflr_lo; 2251 u32 rx_stat_grflr_hi; 2252 u32 rx_stat_grmeg_lo; 2253 u32 rx_stat_grmeg_hi; 2254 u32 rx_stat_grmeb_lo; 2255 u32 rx_stat_grmeb_hi; 2256 u32 rx_stat_grbyt_lo; 2257 u32 rx_stat_grbyt_hi; 2258 u32 rx_stat_grund_lo; 2259 u32 rx_stat_grund_hi; 2260 u32 rx_stat_grfrg_lo; 2261 u32 rx_stat_grfrg_hi; 2262 u32 rx_stat_grerb_lo; 2263 u32 rx_stat_grerb_hi; 2264 u32 rx_stat_grfre_lo; 2265 u32 rx_stat_grfre_hi; 2266 u32 rx_stat_gripj_lo; 2267 u32 rx_stat_gripj_hi; 2268 }; 2269 2270 struct bmac2_stats { 2271 u32 tx_stat_gtpk_lo; /* gtpok */ 2272 u32 tx_stat_gtpk_hi; /* gtpok */ 2273 u32 tx_stat_gtxpf_lo; /* gtpf */ 2274 u32 tx_stat_gtxpf_hi; /* gtpf */ 2275 u32 tx_stat_gtpp_lo; /* NEW BMAC2 */ 2276 u32 tx_stat_gtpp_hi; /* NEW BMAC2 */ 2277 u32 tx_stat_gtfcs_lo; 2278 u32 tx_stat_gtfcs_hi; 2279 u32 tx_stat_gtuca_lo; /* NEW BMAC2 */ 2280 u32 tx_stat_gtuca_hi; /* NEW BMAC2 */ 2281 u32 tx_stat_gtmca_lo; 2282 u32 tx_stat_gtmca_hi; 2283 u32 tx_stat_gtbca_lo; 2284 u32 tx_stat_gtbca_hi; 2285 u32 tx_stat_gtovr_lo; 2286 u32 tx_stat_gtovr_hi; 2287 u32 tx_stat_gtfrg_lo; 2288 u32 tx_stat_gtfrg_hi; 2289 u32 tx_stat_gtpkt1_lo; /* gtpkt */ 2290 u32 tx_stat_gtpkt1_hi; /* gtpkt */ 2291 u32 tx_stat_gt64_lo; 2292 u32 tx_stat_gt64_hi; 2293 u32 tx_stat_gt127_lo; 2294 u32 tx_stat_gt127_hi; 2295 u32 tx_stat_gt255_lo; 2296 u32 tx_stat_gt255_hi; 2297 u32 tx_stat_gt511_lo; 2298 u32 tx_stat_gt511_hi; 2299 u32 tx_stat_gt1023_lo; 2300 u32 tx_stat_gt1023_hi; 2301 u32 tx_stat_gt1518_lo; 2302 u32 tx_stat_gt1518_hi; 2303 u32 tx_stat_gt2047_lo; 2304 u32 tx_stat_gt2047_hi; 2305 u32 tx_stat_gt4095_lo; 2306 u32 tx_stat_gt4095_hi; 2307 u32 tx_stat_gt9216_lo; 2308 u32 tx_stat_gt9216_hi; 2309 u32 tx_stat_gt16383_lo; 2310 u32 tx_stat_gt16383_hi; 2311 u32 tx_stat_gtmax_lo; 2312 u32 tx_stat_gtmax_hi; 2313 u32 tx_stat_gtufl_lo; 2314 u32 tx_stat_gtufl_hi; 2315 u32 tx_stat_gterr_lo; 2316 u32 tx_stat_gterr_hi; 2317 u32 tx_stat_gtbyt_lo; 2318 u32 tx_stat_gtbyt_hi; 2319 2320 u32 rx_stat_gr64_lo; 2321 u32 rx_stat_gr64_hi; 2322 u32 rx_stat_gr127_lo; 2323 u32 rx_stat_gr127_hi; 2324 u32 rx_stat_gr255_lo; 2325 u32 rx_stat_gr255_hi; 2326 u32 rx_stat_gr511_lo; 2327 u32 rx_stat_gr511_hi; 2328 u32 rx_stat_gr1023_lo; 2329 u32 rx_stat_gr1023_hi; 2330 u32 rx_stat_gr1518_lo; 2331 u32 rx_stat_gr1518_hi; 2332 u32 rx_stat_gr2047_lo; 2333 u32 rx_stat_gr2047_hi; 2334 u32 rx_stat_gr4095_lo; 2335 u32 rx_stat_gr4095_hi; 2336 u32 rx_stat_gr9216_lo; 2337 u32 rx_stat_gr9216_hi; 2338 u32 rx_stat_gr16383_lo; 2339 u32 rx_stat_gr16383_hi; 2340 u32 rx_stat_grmax_lo; 2341 u32 rx_stat_grmax_hi; 2342 u32 rx_stat_grpkt_lo; 2343 u32 rx_stat_grpkt_hi; 2344 u32 rx_stat_grfcs_lo; 2345 u32 rx_stat_grfcs_hi; 2346 u32 rx_stat_gruca_lo; 2347 u32 rx_stat_gruca_hi; 2348 u32 rx_stat_grmca_lo; 2349 u32 rx_stat_grmca_hi; 2350 u32 rx_stat_grbca_lo; 2351 u32 rx_stat_grbca_hi; 2352 u32 rx_stat_grxpf_lo; /* grpf */ 2353 u32 rx_stat_grxpf_hi; /* grpf */ 2354 u32 rx_stat_grpp_lo; 2355 u32 rx_stat_grpp_hi; 2356 u32 rx_stat_grxuo_lo; /* gruo */ 2357 u32 rx_stat_grxuo_hi; /* gruo */ 2358 u32 rx_stat_grjbr_lo; 2359 u32 rx_stat_grjbr_hi; 2360 u32 rx_stat_grovr_lo; 2361 u32 rx_stat_grovr_hi; 2362 u32 rx_stat_grxcf_lo; /* grcf */ 2363 u32 rx_stat_grxcf_hi; /* grcf */ 2364 u32 rx_stat_grflr_lo; 2365 u32 rx_stat_grflr_hi; 2366 u32 rx_stat_grpok_lo; 2367 u32 rx_stat_grpok_hi; 2368 u32 rx_stat_grmeg_lo; 2369 u32 rx_stat_grmeg_hi; 2370 u32 rx_stat_grmeb_lo; 2371 u32 rx_stat_grmeb_hi; 2372 u32 rx_stat_grbyt_lo; 2373 u32 rx_stat_grbyt_hi; 2374 u32 rx_stat_grund_lo; 2375 u32 rx_stat_grund_hi; 2376 u32 rx_stat_grfrg_lo; 2377 u32 rx_stat_grfrg_hi; 2378 u32 rx_stat_grerb_lo; /* grerrbyt */ 2379 u32 rx_stat_grerb_hi; /* grerrbyt */ 2380 u32 rx_stat_grfre_lo; /* grfrerr */ 2381 u32 rx_stat_grfre_hi; /* grfrerr */ 2382 u32 rx_stat_gripj_lo; 2383 u32 rx_stat_gripj_hi; 2384 }; 2385 2386 struct mstat_stats { 2387 struct { 2388 /* OTE MSTAT on E3 has a bug where this register's contents are 2389 * actually tx_gtxpok + tx_gtxpf + (possibly)tx_gtxpp 2390 */ 2391 u32 tx_gtxpok_lo; 2392 u32 tx_gtxpok_hi; 2393 u32 tx_gtxpf_lo; 2394 u32 tx_gtxpf_hi; 2395 u32 tx_gtxpp_lo; 2396 u32 tx_gtxpp_hi; 2397 u32 tx_gtfcs_lo; 2398 u32 tx_gtfcs_hi; 2399 u32 tx_gtuca_lo; 2400 u32 tx_gtuca_hi; 2401 u32 tx_gtmca_lo; 2402 u32 tx_gtmca_hi; 2403 u32 tx_gtgca_lo; 2404 u32 tx_gtgca_hi; 2405 u32 tx_gtpkt_lo; 2406 u32 tx_gtpkt_hi; 2407 u32 tx_gt64_lo; 2408 u32 tx_gt64_hi; 2409 u32 tx_gt127_lo; 2410 u32 tx_gt127_hi; 2411 u32 tx_gt255_lo; 2412 u32 tx_gt255_hi; 2413 u32 tx_gt511_lo; 2414 u32 tx_gt511_hi; 2415 u32 tx_gt1023_lo; 2416 u32 tx_gt1023_hi; 2417 u32 tx_gt1518_lo; 2418 u32 tx_gt1518_hi; 2419 u32 tx_gt2047_lo; 2420 u32 tx_gt2047_hi; 2421 u32 tx_gt4095_lo; 2422 u32 tx_gt4095_hi; 2423 u32 tx_gt9216_lo; 2424 u32 tx_gt9216_hi; 2425 u32 tx_gt16383_lo; 2426 u32 tx_gt16383_hi; 2427 u32 tx_gtufl_lo; 2428 u32 tx_gtufl_hi; 2429 u32 tx_gterr_lo; 2430 u32 tx_gterr_hi; 2431 u32 tx_gtbyt_lo; 2432 u32 tx_gtbyt_hi; 2433 u32 tx_collisions_lo; 2434 u32 tx_collisions_hi; 2435 u32 tx_singlecollision_lo; 2436 u32 tx_singlecollision_hi; 2437 u32 tx_multiplecollisions_lo; 2438 u32 tx_multiplecollisions_hi; 2439 u32 tx_deferred_lo; 2440 u32 tx_deferred_hi; 2441 u32 tx_excessivecollisions_lo; 2442 u32 tx_excessivecollisions_hi; 2443 u32 tx_latecollisions_lo; 2444 u32 tx_latecollisions_hi; 2445 } stats_tx; 2446 2447 struct { 2448 u32 rx_gr64_lo; 2449 u32 rx_gr64_hi; 2450 u32 rx_gr127_lo; 2451 u32 rx_gr127_hi; 2452 u32 rx_gr255_lo; 2453 u32 rx_gr255_hi; 2454 u32 rx_gr511_lo; 2455 u32 rx_gr511_hi; 2456 u32 rx_gr1023_lo; 2457 u32 rx_gr1023_hi; 2458 u32 rx_gr1518_lo; 2459 u32 rx_gr1518_hi; 2460 u32 rx_gr2047_lo; 2461 u32 rx_gr2047_hi; 2462 u32 rx_gr4095_lo; 2463 u32 rx_gr4095_hi; 2464 u32 rx_gr9216_lo; 2465 u32 rx_gr9216_hi; 2466 u32 rx_gr16383_lo; 2467 u32 rx_gr16383_hi; 2468 u32 rx_grpkt_lo; 2469 u32 rx_grpkt_hi; 2470 u32 rx_grfcs_lo; 2471 u32 rx_grfcs_hi; 2472 u32 rx_gruca_lo; 2473 u32 rx_gruca_hi; 2474 u32 rx_grmca_lo; 2475 u32 rx_grmca_hi; 2476 u32 rx_grbca_lo; 2477 u32 rx_grbca_hi; 2478 u32 rx_grxpf_lo; 2479 u32 rx_grxpf_hi; 2480 u32 rx_grxpp_lo; 2481 u32 rx_grxpp_hi; 2482 u32 rx_grxuo_lo; 2483 u32 rx_grxuo_hi; 2484 u32 rx_grovr_lo; 2485 u32 rx_grovr_hi; 2486 u32 rx_grxcf_lo; 2487 u32 rx_grxcf_hi; 2488 u32 rx_grflr_lo; 2489 u32 rx_grflr_hi; 2490 u32 rx_grpok_lo; 2491 u32 rx_grpok_hi; 2492 u32 rx_grbyt_lo; 2493 u32 rx_grbyt_hi; 2494 u32 rx_grund_lo; 2495 u32 rx_grund_hi; 2496 u32 rx_grfrg_lo; 2497 u32 rx_grfrg_hi; 2498 u32 rx_grerb_lo; 2499 u32 rx_grerb_hi; 2500 u32 rx_grfre_lo; 2501 u32 rx_grfre_hi; 2502 2503 u32 rx_alignmenterrors_lo; 2504 u32 rx_alignmenterrors_hi; 2505 u32 rx_falsecarrier_lo; 2506 u32 rx_falsecarrier_hi; 2507 u32 rx_llfcmsgcnt_lo; 2508 u32 rx_llfcmsgcnt_hi; 2509 } stats_rx; 2510 }; 2511 2512 union mac_stats { 2513 struct emac_stats emac_stats; 2514 struct bmac1_stats bmac1_stats; 2515 struct bmac2_stats bmac2_stats; 2516 struct mstat_stats mstat_stats; 2517 }; 2518 2519 2520 struct mac_stx { 2521 /* in_bad_octets */ 2522 u32 rx_stat_ifhcinbadoctets_hi; 2523 u32 rx_stat_ifhcinbadoctets_lo; 2524 2525 /* out_bad_octets */ 2526 u32 tx_stat_ifhcoutbadoctets_hi; 2527 u32 tx_stat_ifhcoutbadoctets_lo; 2528 2529 /* crc_receive_errors */ 2530 u32 rx_stat_dot3statsfcserrors_hi; 2531 u32 rx_stat_dot3statsfcserrors_lo; 2532 /* alignment_errors */ 2533 u32 rx_stat_dot3statsalignmenterrors_hi; 2534 u32 rx_stat_dot3statsalignmenterrors_lo; 2535 /* carrier_sense_errors */ 2536 u32 rx_stat_dot3statscarriersenseerrors_hi; 2537 u32 rx_stat_dot3statscarriersenseerrors_lo; 2538 /* false_carrier_detections */ 2539 u32 rx_stat_falsecarriererrors_hi; 2540 u32 rx_stat_falsecarriererrors_lo; 2541 2542 /* runt_packets_received */ 2543 u32 rx_stat_etherstatsundersizepkts_hi; 2544 u32 rx_stat_etherstatsundersizepkts_lo; 2545 /* jabber_packets_received */ 2546 u32 rx_stat_dot3statsframestoolong_hi; 2547 u32 rx_stat_dot3statsframestoolong_lo; 2548 2549 /* error_runt_packets_received */ 2550 u32 rx_stat_etherstatsfragments_hi; 2551 u32 rx_stat_etherstatsfragments_lo; 2552 /* error_jabber_packets_received */ 2553 u32 rx_stat_etherstatsjabbers_hi; 2554 u32 rx_stat_etherstatsjabbers_lo; 2555 2556 /* control_frames_received */ 2557 u32 rx_stat_maccontrolframesreceived_hi; 2558 u32 rx_stat_maccontrolframesreceived_lo; 2559 u32 rx_stat_mac_xpf_hi; 2560 u32 rx_stat_mac_xpf_lo; 2561 u32 rx_stat_mac_xcf_hi; 2562 u32 rx_stat_mac_xcf_lo; 2563 2564 /* xoff_state_entered */ 2565 u32 rx_stat_xoffstateentered_hi; 2566 u32 rx_stat_xoffstateentered_lo; 2567 /* pause_xon_frames_received */ 2568 u32 rx_stat_xonpauseframesreceived_hi; 2569 u32 rx_stat_xonpauseframesreceived_lo; 2570 /* pause_xoff_frames_received */ 2571 u32 rx_stat_xoffpauseframesreceived_hi; 2572 u32 rx_stat_xoffpauseframesreceived_lo; 2573 /* pause_xon_frames_transmitted */ 2574 u32 tx_stat_outxonsent_hi; 2575 u32 tx_stat_outxonsent_lo; 2576 /* pause_xoff_frames_transmitted */ 2577 u32 tx_stat_outxoffsent_hi; 2578 u32 tx_stat_outxoffsent_lo; 2579 /* flow_control_done */ 2580 u32 tx_stat_flowcontroldone_hi; 2581 u32 tx_stat_flowcontroldone_lo; 2582 2583 /* ether_stats_collisions */ 2584 u32 tx_stat_etherstatscollisions_hi; 2585 u32 tx_stat_etherstatscollisions_lo; 2586 /* single_collision_transmit_frames */ 2587 u32 tx_stat_dot3statssinglecollisionframes_hi; 2588 u32 tx_stat_dot3statssinglecollisionframes_lo; 2589 /* multiple_collision_transmit_frames */ 2590 u32 tx_stat_dot3statsmultiplecollisionframes_hi; 2591 u32 tx_stat_dot3statsmultiplecollisionframes_lo; 2592 /* deferred_transmissions */ 2593 u32 tx_stat_dot3statsdeferredtransmissions_hi; 2594 u32 tx_stat_dot3statsdeferredtransmissions_lo; 2595 /* excessive_collision_frames */ 2596 u32 tx_stat_dot3statsexcessivecollisions_hi; 2597 u32 tx_stat_dot3statsexcessivecollisions_lo; 2598 /* late_collision_frames */ 2599 u32 tx_stat_dot3statslatecollisions_hi; 2600 u32 tx_stat_dot3statslatecollisions_lo; 2601 2602 /* frames_transmitted_64_bytes */ 2603 u32 tx_stat_etherstatspkts64octets_hi; 2604 u32 tx_stat_etherstatspkts64octets_lo; 2605 /* frames_transmitted_65_127_bytes */ 2606 u32 tx_stat_etherstatspkts65octetsto127octets_hi; 2607 u32 tx_stat_etherstatspkts65octetsto127octets_lo; 2608 /* frames_transmitted_128_255_bytes */ 2609 u32 tx_stat_etherstatspkts128octetsto255octets_hi; 2610 u32 tx_stat_etherstatspkts128octetsto255octets_lo; 2611 /* frames_transmitted_256_511_bytes */ 2612 u32 tx_stat_etherstatspkts256octetsto511octets_hi; 2613 u32 tx_stat_etherstatspkts256octetsto511octets_lo; 2614 /* frames_transmitted_512_1023_bytes */ 2615 u32 tx_stat_etherstatspkts512octetsto1023octets_hi; 2616 u32 tx_stat_etherstatspkts512octetsto1023octets_lo; 2617 /* frames_transmitted_1024_1522_bytes */ 2618 u32 tx_stat_etherstatspkts1024octetsto1522octets_hi; 2619 u32 tx_stat_etherstatspkts1024octetsto1522octets_lo; 2620 /* frames_transmitted_1523_9022_bytes */ 2621 u32 tx_stat_etherstatspktsover1522octets_hi; 2622 u32 tx_stat_etherstatspktsover1522octets_lo; 2623 u32 tx_stat_mac_2047_hi; 2624 u32 tx_stat_mac_2047_lo; 2625 u32 tx_stat_mac_4095_hi; 2626 u32 tx_stat_mac_4095_lo; 2627 u32 tx_stat_mac_9216_hi; 2628 u32 tx_stat_mac_9216_lo; 2629 u32 tx_stat_mac_16383_hi; 2630 u32 tx_stat_mac_16383_lo; 2631 2632 /* internal_mac_transmit_errors */ 2633 u32 tx_stat_dot3statsinternalmactransmiterrors_hi; 2634 u32 tx_stat_dot3statsinternalmactransmiterrors_lo; 2635 2636 /* if_out_discards */ 2637 u32 tx_stat_mac_ufl_hi; 2638 u32 tx_stat_mac_ufl_lo; 2639 }; 2640 2641 2642 #define MAC_STX_IDX_MAX 2 2643 2644 struct host_port_stats { 2645 u32 host_port_stats_counter; 2646 2647 struct mac_stx mac_stx[MAC_STX_IDX_MAX]; 2648 2649 u32 brb_drop_hi; 2650 u32 brb_drop_lo; 2651 2652 u32 not_used; /* obsolete */ 2653 u32 pfc_frames_tx_hi; 2654 u32 pfc_frames_tx_lo; 2655 u32 pfc_frames_rx_hi; 2656 u32 pfc_frames_rx_lo; 2657 2658 u32 eee_lpi_count_hi; 2659 u32 eee_lpi_count_lo; 2660 }; 2661 2662 2663 struct host_func_stats { 2664 u32 host_func_stats_start; 2665 2666 u32 total_bytes_received_hi; 2667 u32 total_bytes_received_lo; 2668 2669 u32 total_bytes_transmitted_hi; 2670 u32 total_bytes_transmitted_lo; 2671 2672 u32 total_unicast_packets_received_hi; 2673 u32 total_unicast_packets_received_lo; 2674 2675 u32 total_multicast_packets_received_hi; 2676 u32 total_multicast_packets_received_lo; 2677 2678 u32 total_broadcast_packets_received_hi; 2679 u32 total_broadcast_packets_received_lo; 2680 2681 u32 total_unicast_packets_transmitted_hi; 2682 u32 total_unicast_packets_transmitted_lo; 2683 2684 u32 total_multicast_packets_transmitted_hi; 2685 u32 total_multicast_packets_transmitted_lo; 2686 2687 u32 total_broadcast_packets_transmitted_hi; 2688 u32 total_broadcast_packets_transmitted_lo; 2689 2690 u32 valid_bytes_received_hi; 2691 u32 valid_bytes_received_lo; 2692 2693 u32 host_func_stats_end; 2694 }; 2695 2696 /* VIC definitions */ 2697 #define VICSTATST_UIF_INDEX 2 2698 2699 2700 /* stats collected for afex. 2701 * NOTE: structure is exactly as expected to be received by the switch. 2702 * order must remain exactly as is unless protocol changes ! 2703 */ 2704 struct afex_stats { 2705 u32 tx_unicast_frames_hi; 2706 u32 tx_unicast_frames_lo; 2707 u32 tx_unicast_bytes_hi; 2708 u32 tx_unicast_bytes_lo; 2709 u32 tx_multicast_frames_hi; 2710 u32 tx_multicast_frames_lo; 2711 u32 tx_multicast_bytes_hi; 2712 u32 tx_multicast_bytes_lo; 2713 u32 tx_broadcast_frames_hi; 2714 u32 tx_broadcast_frames_lo; 2715 u32 tx_broadcast_bytes_hi; 2716 u32 tx_broadcast_bytes_lo; 2717 u32 tx_frames_discarded_hi; 2718 u32 tx_frames_discarded_lo; 2719 u32 tx_frames_dropped_hi; 2720 u32 tx_frames_dropped_lo; 2721 2722 u32 rx_unicast_frames_hi; 2723 u32 rx_unicast_frames_lo; 2724 u32 rx_unicast_bytes_hi; 2725 u32 rx_unicast_bytes_lo; 2726 u32 rx_multicast_frames_hi; 2727 u32 rx_multicast_frames_lo; 2728 u32 rx_multicast_bytes_hi; 2729 u32 rx_multicast_bytes_lo; 2730 u32 rx_broadcast_frames_hi; 2731 u32 rx_broadcast_frames_lo; 2732 u32 rx_broadcast_bytes_hi; 2733 u32 rx_broadcast_bytes_lo; 2734 u32 rx_frames_discarded_hi; 2735 u32 rx_frames_discarded_lo; 2736 u32 rx_frames_dropped_hi; 2737 u32 rx_frames_dropped_lo; 2738 }; 2739 2740 #define BCM_5710_FW_MAJOR_VERSION 7 2741 #define BCM_5710_FW_MINOR_VERSION 2 2742 #define BCM_5710_FW_REVISION_VERSION 51 2743 #define BCM_5710_FW_ENGINEERING_VERSION 0 2744 #define BCM_5710_FW_COMPILE_FLAGS 1 2745 2746 2747 /* 2748 * attention bits 2749 */ 2750 struct atten_sp_status_block { 2751 __le32 attn_bits; 2752 __le32 attn_bits_ack; 2753 u8 status_block_id; 2754 u8 reserved0; 2755 __le16 attn_bits_index; 2756 __le32 reserved1; 2757 }; 2758 2759 2760 /* 2761 * The eth aggregative context of Cstorm 2762 */ 2763 struct cstorm_eth_ag_context { 2764 u32 __reserved0[10]; 2765 }; 2766 2767 2768 /* 2769 * dmae command structure 2770 */ 2771 struct dmae_command { 2772 u32 opcode; 2773 #define DMAE_COMMAND_SRC (0x1<<0) 2774 #define DMAE_COMMAND_SRC_SHIFT 0 2775 #define DMAE_COMMAND_DST (0x3<<1) 2776 #define DMAE_COMMAND_DST_SHIFT 1 2777 #define DMAE_COMMAND_C_DST (0x1<<3) 2778 #define DMAE_COMMAND_C_DST_SHIFT 3 2779 #define DMAE_COMMAND_C_TYPE_ENABLE (0x1<<4) 2780 #define DMAE_COMMAND_C_TYPE_ENABLE_SHIFT 4 2781 #define DMAE_COMMAND_C_TYPE_CRC_ENABLE (0x1<<5) 2782 #define DMAE_COMMAND_C_TYPE_CRC_ENABLE_SHIFT 5 2783 #define DMAE_COMMAND_C_TYPE_CRC_OFFSET (0x7<<6) 2784 #define DMAE_COMMAND_C_TYPE_CRC_OFFSET_SHIFT 6 2785 #define DMAE_COMMAND_ENDIANITY (0x3<<9) 2786 #define DMAE_COMMAND_ENDIANITY_SHIFT 9 2787 #define DMAE_COMMAND_PORT (0x1<<11) 2788 #define DMAE_COMMAND_PORT_SHIFT 11 2789 #define DMAE_COMMAND_CRC_RESET (0x1<<12) 2790 #define DMAE_COMMAND_CRC_RESET_SHIFT 12 2791 #define DMAE_COMMAND_SRC_RESET (0x1<<13) 2792 #define DMAE_COMMAND_SRC_RESET_SHIFT 13 2793 #define DMAE_COMMAND_DST_RESET (0x1<<14) 2794 #define DMAE_COMMAND_DST_RESET_SHIFT 14 2795 #define DMAE_COMMAND_E1HVN (0x3<<15) 2796 #define DMAE_COMMAND_E1HVN_SHIFT 15 2797 #define DMAE_COMMAND_DST_VN (0x3<<17) 2798 #define DMAE_COMMAND_DST_VN_SHIFT 17 2799 #define DMAE_COMMAND_C_FUNC (0x1<<19) 2800 #define DMAE_COMMAND_C_FUNC_SHIFT 19 2801 #define DMAE_COMMAND_ERR_POLICY (0x3<<20) 2802 #define DMAE_COMMAND_ERR_POLICY_SHIFT 20 2803 #define DMAE_COMMAND_RESERVED0 (0x3FF<<22) 2804 #define DMAE_COMMAND_RESERVED0_SHIFT 22 2805 u32 src_addr_lo; 2806 u32 src_addr_hi; 2807 u32 dst_addr_lo; 2808 u32 dst_addr_hi; 2809 #if defined(__BIG_ENDIAN) 2810 u16 opcode_iov; 2811 #define DMAE_COMMAND_SRC_VFID (0x3F<<0) 2812 #define DMAE_COMMAND_SRC_VFID_SHIFT 0 2813 #define DMAE_COMMAND_SRC_VFPF (0x1<<6) 2814 #define DMAE_COMMAND_SRC_VFPF_SHIFT 6 2815 #define DMAE_COMMAND_RESERVED1 (0x1<<7) 2816 #define DMAE_COMMAND_RESERVED1_SHIFT 7 2817 #define DMAE_COMMAND_DST_VFID (0x3F<<8) 2818 #define DMAE_COMMAND_DST_VFID_SHIFT 8 2819 #define DMAE_COMMAND_DST_VFPF (0x1<<14) 2820 #define DMAE_COMMAND_DST_VFPF_SHIFT 14 2821 #define DMAE_COMMAND_RESERVED2 (0x1<<15) 2822 #define DMAE_COMMAND_RESERVED2_SHIFT 15 2823 u16 len; 2824 #elif defined(__LITTLE_ENDIAN) 2825 u16 len; 2826 u16 opcode_iov; 2827 #define DMAE_COMMAND_SRC_VFID (0x3F<<0) 2828 #define DMAE_COMMAND_SRC_VFID_SHIFT 0 2829 #define DMAE_COMMAND_SRC_VFPF (0x1<<6) 2830 #define DMAE_COMMAND_SRC_VFPF_SHIFT 6 2831 #define DMAE_COMMAND_RESERVED1 (0x1<<7) 2832 #define DMAE_COMMAND_RESERVED1_SHIFT 7 2833 #define DMAE_COMMAND_DST_VFID (0x3F<<8) 2834 #define DMAE_COMMAND_DST_VFID_SHIFT 8 2835 #define DMAE_COMMAND_DST_VFPF (0x1<<14) 2836 #define DMAE_COMMAND_DST_VFPF_SHIFT 14 2837 #define DMAE_COMMAND_RESERVED2 (0x1<<15) 2838 #define DMAE_COMMAND_RESERVED2_SHIFT 15 2839 #endif 2840 u32 comp_addr_lo; 2841 u32 comp_addr_hi; 2842 u32 comp_val; 2843 u32 crc32; 2844 u32 crc32_c; 2845 #if defined(__BIG_ENDIAN) 2846 u16 crc16_c; 2847 u16 crc16; 2848 #elif defined(__LITTLE_ENDIAN) 2849 u16 crc16; 2850 u16 crc16_c; 2851 #endif 2852 #if defined(__BIG_ENDIAN) 2853 u16 reserved3; 2854 u16 crc_t10; 2855 #elif defined(__LITTLE_ENDIAN) 2856 u16 crc_t10; 2857 u16 reserved3; 2858 #endif 2859 #if defined(__BIG_ENDIAN) 2860 u16 xsum8; 2861 u16 xsum16; 2862 #elif defined(__LITTLE_ENDIAN) 2863 u16 xsum16; 2864 u16 xsum8; 2865 #endif 2866 }; 2867 2868 2869 /* 2870 * common data for all protocols 2871 */ 2872 struct doorbell_hdr { 2873 u8 header; 2874 #define DOORBELL_HDR_RX (0x1<<0) 2875 #define DOORBELL_HDR_RX_SHIFT 0 2876 #define DOORBELL_HDR_DB_TYPE (0x1<<1) 2877 #define DOORBELL_HDR_DB_TYPE_SHIFT 1 2878 #define DOORBELL_HDR_DPM_SIZE (0x3<<2) 2879 #define DOORBELL_HDR_DPM_SIZE_SHIFT 2 2880 #define DOORBELL_HDR_CONN_TYPE (0xF<<4) 2881 #define DOORBELL_HDR_CONN_TYPE_SHIFT 4 2882 }; 2883 2884 /* 2885 * Ethernet doorbell 2886 */ 2887 struct eth_tx_doorbell { 2888 #if defined(__BIG_ENDIAN) 2889 u16 npackets; 2890 u8 params; 2891 #define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0) 2892 #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0 2893 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6) 2894 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6 2895 #define ETH_TX_DOORBELL_SPARE (0x1<<7) 2896 #define ETH_TX_DOORBELL_SPARE_SHIFT 7 2897 struct doorbell_hdr hdr; 2898 #elif defined(__LITTLE_ENDIAN) 2899 struct doorbell_hdr hdr; 2900 u8 params; 2901 #define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0) 2902 #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0 2903 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6) 2904 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6 2905 #define ETH_TX_DOORBELL_SPARE (0x1<<7) 2906 #define ETH_TX_DOORBELL_SPARE_SHIFT 7 2907 u16 npackets; 2908 #endif 2909 }; 2910 2911 2912 /* 2913 * 3 lines. status block 2914 */ 2915 struct hc_status_block_e1x { 2916 __le16 index_values[HC_SB_MAX_INDICES_E1X]; 2917 __le16 running_index[HC_SB_MAX_SM]; 2918 __le32 rsrv[11]; 2919 }; 2920 2921 /* 2922 * host status block 2923 */ 2924 struct host_hc_status_block_e1x { 2925 struct hc_status_block_e1x sb; 2926 }; 2927 2928 2929 /* 2930 * 3 lines. status block 2931 */ 2932 struct hc_status_block_e2 { 2933 __le16 index_values[HC_SB_MAX_INDICES_E2]; 2934 __le16 running_index[HC_SB_MAX_SM]; 2935 __le32 reserved[11]; 2936 }; 2937 2938 /* 2939 * host status block 2940 */ 2941 struct host_hc_status_block_e2 { 2942 struct hc_status_block_e2 sb; 2943 }; 2944 2945 2946 /* 2947 * 5 lines. slow-path status block 2948 */ 2949 struct hc_sp_status_block { 2950 __le16 index_values[HC_SP_SB_MAX_INDICES]; 2951 __le16 running_index; 2952 __le16 rsrv; 2953 u32 rsrv1; 2954 }; 2955 2956 /* 2957 * host status block 2958 */ 2959 struct host_sp_status_block { 2960 struct atten_sp_status_block atten_status_block; 2961 struct hc_sp_status_block sp_sb; 2962 }; 2963 2964 2965 /* 2966 * IGU driver acknowledgment register 2967 */ 2968 struct igu_ack_register { 2969 #if defined(__BIG_ENDIAN) 2970 u16 sb_id_and_flags; 2971 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0) 2972 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0 2973 #define IGU_ACK_REGISTER_STORM_ID (0x7<<5) 2974 #define IGU_ACK_REGISTER_STORM_ID_SHIFT 5 2975 #define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8) 2976 #define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8 2977 #define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9) 2978 #define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9 2979 #define IGU_ACK_REGISTER_RESERVED (0x1F<<11) 2980 #define IGU_ACK_REGISTER_RESERVED_SHIFT 11 2981 u16 status_block_index; 2982 #elif defined(__LITTLE_ENDIAN) 2983 u16 status_block_index; 2984 u16 sb_id_and_flags; 2985 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0) 2986 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0 2987 #define IGU_ACK_REGISTER_STORM_ID (0x7<<5) 2988 #define IGU_ACK_REGISTER_STORM_ID_SHIFT 5 2989 #define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8) 2990 #define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8 2991 #define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9) 2992 #define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9 2993 #define IGU_ACK_REGISTER_RESERVED (0x1F<<11) 2994 #define IGU_ACK_REGISTER_RESERVED_SHIFT 11 2995 #endif 2996 }; 2997 2998 2999 /* 3000 * IGU driver acknowledgement register 3001 */ 3002 struct igu_backward_compatible { 3003 u32 sb_id_and_flags; 3004 #define IGU_BACKWARD_COMPATIBLE_SB_INDEX (0xFFFF<<0) 3005 #define IGU_BACKWARD_COMPATIBLE_SB_INDEX_SHIFT 0 3006 #define IGU_BACKWARD_COMPATIBLE_SB_SELECT (0x1F<<16) 3007 #define IGU_BACKWARD_COMPATIBLE_SB_SELECT_SHIFT 16 3008 #define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS (0x7<<21) 3009 #define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS_SHIFT 21 3010 #define IGU_BACKWARD_COMPATIBLE_BUPDATE (0x1<<24) 3011 #define IGU_BACKWARD_COMPATIBLE_BUPDATE_SHIFT 24 3012 #define IGU_BACKWARD_COMPATIBLE_ENABLE_INT (0x3<<25) 3013 #define IGU_BACKWARD_COMPATIBLE_ENABLE_INT_SHIFT 25 3014 #define IGU_BACKWARD_COMPATIBLE_RESERVED_0 (0x1F<<27) 3015 #define IGU_BACKWARD_COMPATIBLE_RESERVED_0_SHIFT 27 3016 u32 reserved_2; 3017 }; 3018 3019 3020 /* 3021 * IGU driver acknowledgement register 3022 */ 3023 struct igu_regular { 3024 u32 sb_id_and_flags; 3025 #define IGU_REGULAR_SB_INDEX (0xFFFFF<<0) 3026 #define IGU_REGULAR_SB_INDEX_SHIFT 0 3027 #define IGU_REGULAR_RESERVED0 (0x1<<20) 3028 #define IGU_REGULAR_RESERVED0_SHIFT 20 3029 #define IGU_REGULAR_SEGMENT_ACCESS (0x7<<21) 3030 #define IGU_REGULAR_SEGMENT_ACCESS_SHIFT 21 3031 #define IGU_REGULAR_BUPDATE (0x1<<24) 3032 #define IGU_REGULAR_BUPDATE_SHIFT 24 3033 #define IGU_REGULAR_ENABLE_INT (0x3<<25) 3034 #define IGU_REGULAR_ENABLE_INT_SHIFT 25 3035 #define IGU_REGULAR_RESERVED_1 (0x1<<27) 3036 #define IGU_REGULAR_RESERVED_1_SHIFT 27 3037 #define IGU_REGULAR_CLEANUP_TYPE (0x3<<28) 3038 #define IGU_REGULAR_CLEANUP_TYPE_SHIFT 28 3039 #define IGU_REGULAR_CLEANUP_SET (0x1<<30) 3040 #define IGU_REGULAR_CLEANUP_SET_SHIFT 30 3041 #define IGU_REGULAR_BCLEANUP (0x1<<31) 3042 #define IGU_REGULAR_BCLEANUP_SHIFT 31 3043 u32 reserved_2; 3044 }; 3045 3046 /* 3047 * IGU driver acknowledgement register 3048 */ 3049 union igu_consprod_reg { 3050 struct igu_regular regular; 3051 struct igu_backward_compatible backward_compatible; 3052 }; 3053 3054 3055 /* 3056 * Igu control commands 3057 */ 3058 enum igu_ctrl_cmd { 3059 IGU_CTRL_CMD_TYPE_RD, 3060 IGU_CTRL_CMD_TYPE_WR, 3061 MAX_IGU_CTRL_CMD 3062 }; 3063 3064 3065 /* 3066 * Control register for the IGU command register 3067 */ 3068 struct igu_ctrl_reg { 3069 u32 ctrl_data; 3070 #define IGU_CTRL_REG_ADDRESS (0xFFF<<0) 3071 #define IGU_CTRL_REG_ADDRESS_SHIFT 0 3072 #define IGU_CTRL_REG_FID (0x7F<<12) 3073 #define IGU_CTRL_REG_FID_SHIFT 12 3074 #define IGU_CTRL_REG_RESERVED (0x1<<19) 3075 #define IGU_CTRL_REG_RESERVED_SHIFT 19 3076 #define IGU_CTRL_REG_TYPE (0x1<<20) 3077 #define IGU_CTRL_REG_TYPE_SHIFT 20 3078 #define IGU_CTRL_REG_UNUSED (0x7FF<<21) 3079 #define IGU_CTRL_REG_UNUSED_SHIFT 21 3080 }; 3081 3082 3083 /* 3084 * Igu interrupt command 3085 */ 3086 enum igu_int_cmd { 3087 IGU_INT_ENABLE, 3088 IGU_INT_DISABLE, 3089 IGU_INT_NOP, 3090 IGU_INT_NOP2, 3091 MAX_IGU_INT_CMD 3092 }; 3093 3094 3095 /* 3096 * Igu segments 3097 */ 3098 enum igu_seg_access { 3099 IGU_SEG_ACCESS_NORM, 3100 IGU_SEG_ACCESS_DEF, 3101 IGU_SEG_ACCESS_ATTN, 3102 MAX_IGU_SEG_ACCESS 3103 }; 3104 3105 3106 /* 3107 * Parser parsing flags field 3108 */ 3109 struct parsing_flags { 3110 __le16 flags; 3111 #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE (0x1<<0) 3112 #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE_SHIFT 0 3113 #define PARSING_FLAGS_VLAN (0x1<<1) 3114 #define PARSING_FLAGS_VLAN_SHIFT 1 3115 #define PARSING_FLAGS_EXTRA_VLAN (0x1<<2) 3116 #define PARSING_FLAGS_EXTRA_VLAN_SHIFT 2 3117 #define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL (0x3<<3) 3118 #define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT 3 3119 #define PARSING_FLAGS_IP_OPTIONS (0x1<<5) 3120 #define PARSING_FLAGS_IP_OPTIONS_SHIFT 5 3121 #define PARSING_FLAGS_FRAGMENTATION_STATUS (0x1<<6) 3122 #define PARSING_FLAGS_FRAGMENTATION_STATUS_SHIFT 6 3123 #define PARSING_FLAGS_OVER_IP_PROTOCOL (0x3<<7) 3124 #define PARSING_FLAGS_OVER_IP_PROTOCOL_SHIFT 7 3125 #define PARSING_FLAGS_PURE_ACK_INDICATION (0x1<<9) 3126 #define PARSING_FLAGS_PURE_ACK_INDICATION_SHIFT 9 3127 #define PARSING_FLAGS_TCP_OPTIONS_EXIST (0x1<<10) 3128 #define PARSING_FLAGS_TCP_OPTIONS_EXIST_SHIFT 10 3129 #define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG (0x1<<11) 3130 #define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG_SHIFT 11 3131 #define PARSING_FLAGS_CONNECTION_MATCH (0x1<<12) 3132 #define PARSING_FLAGS_CONNECTION_MATCH_SHIFT 12 3133 #define PARSING_FLAGS_LLC_SNAP (0x1<<13) 3134 #define PARSING_FLAGS_LLC_SNAP_SHIFT 13 3135 #define PARSING_FLAGS_RESERVED0 (0x3<<14) 3136 #define PARSING_FLAGS_RESERVED0_SHIFT 14 3137 }; 3138 3139 3140 /* 3141 * Parsing flags for TCP ACK type 3142 */ 3143 enum prs_flags_ack_type { 3144 PRS_FLAG_PUREACK_PIGGY, 3145 PRS_FLAG_PUREACK_PURE, 3146 MAX_PRS_FLAGS_ACK_TYPE 3147 }; 3148 3149 3150 /* 3151 * Parsing flags for Ethernet address type 3152 */ 3153 enum prs_flags_eth_addr_type { 3154 PRS_FLAG_ETHTYPE_NON_UNICAST, 3155 PRS_FLAG_ETHTYPE_UNICAST, 3156 MAX_PRS_FLAGS_ETH_ADDR_TYPE 3157 }; 3158 3159 3160 /* 3161 * Parsing flags for over-ethernet protocol 3162 */ 3163 enum prs_flags_over_eth { 3164 PRS_FLAG_OVERETH_UNKNOWN, 3165 PRS_FLAG_OVERETH_IPV4, 3166 PRS_FLAG_OVERETH_IPV6, 3167 PRS_FLAG_OVERETH_LLCSNAP_UNKNOWN, 3168 MAX_PRS_FLAGS_OVER_ETH 3169 }; 3170 3171 3172 /* 3173 * Parsing flags for over-IP protocol 3174 */ 3175 enum prs_flags_over_ip { 3176 PRS_FLAG_OVERIP_UNKNOWN, 3177 PRS_FLAG_OVERIP_TCP, 3178 PRS_FLAG_OVERIP_UDP, 3179 MAX_PRS_FLAGS_OVER_IP 3180 }; 3181 3182 3183 /* 3184 * SDM operation gen command (generate aggregative interrupt) 3185 */ 3186 struct sdm_op_gen { 3187 __le32 command; 3188 #define SDM_OP_GEN_COMP_PARAM (0x1F<<0) 3189 #define SDM_OP_GEN_COMP_PARAM_SHIFT 0 3190 #define SDM_OP_GEN_COMP_TYPE (0x7<<5) 3191 #define SDM_OP_GEN_COMP_TYPE_SHIFT 5 3192 #define SDM_OP_GEN_AGG_VECT_IDX (0xFF<<8) 3193 #define SDM_OP_GEN_AGG_VECT_IDX_SHIFT 8 3194 #define SDM_OP_GEN_AGG_VECT_IDX_VALID (0x1<<16) 3195 #define SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT 16 3196 #define SDM_OP_GEN_RESERVED (0x7FFF<<17) 3197 #define SDM_OP_GEN_RESERVED_SHIFT 17 3198 }; 3199 3200 3201 /* 3202 * Timers connection context 3203 */ 3204 struct timers_block_context { 3205 u32 __reserved_0; 3206 u32 __reserved_1; 3207 u32 __reserved_2; 3208 u32 flags; 3209 #define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS (0x3<<0) 3210 #define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS_SHIFT 0 3211 #define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG (0x1<<2) 3212 #define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG_SHIFT 2 3213 #define __TIMERS_BLOCK_CONTEXT_RESERVED0 (0x1FFFFFFF<<3) 3214 #define __TIMERS_BLOCK_CONTEXT_RESERVED0_SHIFT 3 3215 }; 3216 3217 3218 /* 3219 * The eth aggregative context of Tstorm 3220 */ 3221 struct tstorm_eth_ag_context { 3222 u32 __reserved0[14]; 3223 }; 3224 3225 3226 /* 3227 * The eth aggregative context of Ustorm 3228 */ 3229 struct ustorm_eth_ag_context { 3230 u32 __reserved0; 3231 #if defined(__BIG_ENDIAN) 3232 u8 cdu_usage; 3233 u8 __reserved2; 3234 u16 __reserved1; 3235 #elif defined(__LITTLE_ENDIAN) 3236 u16 __reserved1; 3237 u8 __reserved2; 3238 u8 cdu_usage; 3239 #endif 3240 u32 __reserved3[6]; 3241 }; 3242 3243 3244 /* 3245 * The eth aggregative context of Xstorm 3246 */ 3247 struct xstorm_eth_ag_context { 3248 u32 reserved0; 3249 #if defined(__BIG_ENDIAN) 3250 u8 cdu_reserved; 3251 u8 reserved2; 3252 u16 reserved1; 3253 #elif defined(__LITTLE_ENDIAN) 3254 u16 reserved1; 3255 u8 reserved2; 3256 u8 cdu_reserved; 3257 #endif 3258 u32 reserved3[30]; 3259 }; 3260 3261 3262 /* 3263 * doorbell message sent to the chip 3264 */ 3265 struct doorbell { 3266 #if defined(__BIG_ENDIAN) 3267 u16 zero_fill2; 3268 u8 zero_fill1; 3269 struct doorbell_hdr header; 3270 #elif defined(__LITTLE_ENDIAN) 3271 struct doorbell_hdr header; 3272 u8 zero_fill1; 3273 u16 zero_fill2; 3274 #endif 3275 }; 3276 3277 3278 /* 3279 * doorbell message sent to the chip 3280 */ 3281 struct doorbell_set_prod { 3282 #if defined(__BIG_ENDIAN) 3283 u16 prod; 3284 u8 zero_fill1; 3285 struct doorbell_hdr header; 3286 #elif defined(__LITTLE_ENDIAN) 3287 struct doorbell_hdr header; 3288 u8 zero_fill1; 3289 u16 prod; 3290 #endif 3291 }; 3292 3293 3294 struct regpair { 3295 __le32 lo; 3296 __le32 hi; 3297 }; 3298 3299 3300 /* 3301 * Classify rule opcodes in E2/E3 3302 */ 3303 enum classify_rule { 3304 CLASSIFY_RULE_OPCODE_MAC, 3305 CLASSIFY_RULE_OPCODE_VLAN, 3306 CLASSIFY_RULE_OPCODE_PAIR, 3307 MAX_CLASSIFY_RULE 3308 }; 3309 3310 3311 /* 3312 * Classify rule types in E2/E3 3313 */ 3314 enum classify_rule_action_type { 3315 CLASSIFY_RULE_REMOVE, 3316 CLASSIFY_RULE_ADD, 3317 MAX_CLASSIFY_RULE_ACTION_TYPE 3318 }; 3319 3320 3321 /* 3322 * client init ramrod data 3323 */ 3324 struct client_init_general_data { 3325 u8 client_id; 3326 u8 statistics_counter_id; 3327 u8 statistics_en_flg; 3328 u8 is_fcoe_flg; 3329 u8 activate_flg; 3330 u8 sp_client_id; 3331 __le16 mtu; 3332 u8 statistics_zero_flg; 3333 u8 func_id; 3334 u8 cos; 3335 u8 traffic_type; 3336 u32 reserved0; 3337 }; 3338 3339 3340 /* 3341 * client init rx data 3342 */ 3343 struct client_init_rx_data { 3344 u8 tpa_en; 3345 #define CLIENT_INIT_RX_DATA_TPA_EN_IPV4 (0x1<<0) 3346 #define CLIENT_INIT_RX_DATA_TPA_EN_IPV4_SHIFT 0 3347 #define CLIENT_INIT_RX_DATA_TPA_EN_IPV6 (0x1<<1) 3348 #define CLIENT_INIT_RX_DATA_TPA_EN_IPV6_SHIFT 1 3349 #define CLIENT_INIT_RX_DATA_TPA_MODE (0x1<<2) 3350 #define CLIENT_INIT_RX_DATA_TPA_MODE_SHIFT 2 3351 #define CLIENT_INIT_RX_DATA_RESERVED5 (0x1F<<3) 3352 #define CLIENT_INIT_RX_DATA_RESERVED5_SHIFT 3 3353 u8 vmqueue_mode_en_flg; 3354 u8 extra_data_over_sgl_en_flg; 3355 u8 cache_line_alignment_log_size; 3356 u8 enable_dynamic_hc; 3357 u8 max_sges_for_packet; 3358 u8 client_qzone_id; 3359 u8 drop_ip_cs_err_flg; 3360 u8 drop_tcp_cs_err_flg; 3361 u8 drop_ttl0_flg; 3362 u8 drop_udp_cs_err_flg; 3363 u8 inner_vlan_removal_enable_flg; 3364 u8 outer_vlan_removal_enable_flg; 3365 u8 status_block_id; 3366 u8 rx_sb_index_number; 3367 u8 dont_verify_rings_pause_thr_flg; 3368 u8 max_tpa_queues; 3369 u8 silent_vlan_removal_flg; 3370 __le16 max_bytes_on_bd; 3371 __le16 sge_buff_size; 3372 u8 approx_mcast_engine_id; 3373 u8 rss_engine_id; 3374 struct regpair bd_page_base; 3375 struct regpair sge_page_base; 3376 struct regpair cqe_page_base; 3377 u8 is_leading_rss; 3378 u8 is_approx_mcast; 3379 __le16 max_agg_size; 3380 __le16 state; 3381 #define CLIENT_INIT_RX_DATA_UCAST_DROP_ALL (0x1<<0) 3382 #define CLIENT_INIT_RX_DATA_UCAST_DROP_ALL_SHIFT 0 3383 #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL (0x1<<1) 3384 #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL_SHIFT 1 3385 #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED (0x1<<2) 3386 #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED_SHIFT 2 3387 #define CLIENT_INIT_RX_DATA_MCAST_DROP_ALL (0x1<<3) 3388 #define CLIENT_INIT_RX_DATA_MCAST_DROP_ALL_SHIFT 3 3389 #define CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL (0x1<<4) 3390 #define CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL_SHIFT 4 3391 #define CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL (0x1<<5) 3392 #define CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL_SHIFT 5 3393 #define CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN (0x1<<6) 3394 #define CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN_SHIFT 6 3395 #define CLIENT_INIT_RX_DATA_RESERVED2 (0x1FF<<7) 3396 #define CLIENT_INIT_RX_DATA_RESERVED2_SHIFT 7 3397 __le16 cqe_pause_thr_low; 3398 __le16 cqe_pause_thr_high; 3399 __le16 bd_pause_thr_low; 3400 __le16 bd_pause_thr_high; 3401 __le16 sge_pause_thr_low; 3402 __le16 sge_pause_thr_high; 3403 __le16 rx_cos_mask; 3404 __le16 silent_vlan_value; 3405 __le16 silent_vlan_mask; 3406 __le32 reserved6[2]; 3407 }; 3408 3409 /* 3410 * client init tx data 3411 */ 3412 struct client_init_tx_data { 3413 u8 enforce_security_flg; 3414 u8 tx_status_block_id; 3415 u8 tx_sb_index_number; 3416 u8 tss_leading_client_id; 3417 u8 tx_switching_flg; 3418 u8 anti_spoofing_flg; 3419 __le16 default_vlan; 3420 struct regpair tx_bd_page_base; 3421 __le16 state; 3422 #define CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL (0x1<<0) 3423 #define CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL_SHIFT 0 3424 #define CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL (0x1<<1) 3425 #define CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL_SHIFT 1 3426 #define CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL (0x1<<2) 3427 #define CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL_SHIFT 2 3428 #define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN (0x1<<3) 3429 #define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN_SHIFT 3 3430 #define CLIENT_INIT_TX_DATA_RESERVED1 (0xFFF<<4) 3431 #define CLIENT_INIT_TX_DATA_RESERVED1_SHIFT 4 3432 u8 default_vlan_flg; 3433 u8 force_default_pri_flg; 3434 __le32 reserved3; 3435 }; 3436 3437 /* 3438 * client init ramrod data 3439 */ 3440 struct client_init_ramrod_data { 3441 struct client_init_general_data general; 3442 struct client_init_rx_data rx; 3443 struct client_init_tx_data tx; 3444 }; 3445 3446 3447 /* 3448 * client update ramrod data 3449 */ 3450 struct client_update_ramrod_data { 3451 u8 client_id; 3452 u8 func_id; 3453 u8 inner_vlan_removal_enable_flg; 3454 u8 inner_vlan_removal_change_flg; 3455 u8 outer_vlan_removal_enable_flg; 3456 u8 outer_vlan_removal_change_flg; 3457 u8 anti_spoofing_enable_flg; 3458 u8 anti_spoofing_change_flg; 3459 u8 activate_flg; 3460 u8 activate_change_flg; 3461 __le16 default_vlan; 3462 u8 default_vlan_enable_flg; 3463 u8 default_vlan_change_flg; 3464 __le16 silent_vlan_value; 3465 __le16 silent_vlan_mask; 3466 u8 silent_vlan_removal_flg; 3467 u8 silent_vlan_change_flg; 3468 __le32 echo; 3469 }; 3470 3471 3472 /* 3473 * The eth storm context of Cstorm 3474 */ 3475 struct cstorm_eth_st_context { 3476 u32 __reserved0[4]; 3477 }; 3478 3479 3480 struct double_regpair { 3481 u32 regpair0_lo; 3482 u32 regpair0_hi; 3483 u32 regpair1_lo; 3484 u32 regpair1_hi; 3485 }; 3486 3487 3488 /* 3489 * Ethernet address typesm used in ethernet tx BDs 3490 */ 3491 enum eth_addr_type { 3492 UNKNOWN_ADDRESS, 3493 UNICAST_ADDRESS, 3494 MULTICAST_ADDRESS, 3495 BROADCAST_ADDRESS, 3496 MAX_ETH_ADDR_TYPE 3497 }; 3498 3499 3500 /* 3501 * 3502 */ 3503 struct eth_classify_cmd_header { 3504 u8 cmd_general_data; 3505 #define ETH_CLASSIFY_CMD_HEADER_RX_CMD (0x1<<0) 3506 #define ETH_CLASSIFY_CMD_HEADER_RX_CMD_SHIFT 0 3507 #define ETH_CLASSIFY_CMD_HEADER_TX_CMD (0x1<<1) 3508 #define ETH_CLASSIFY_CMD_HEADER_TX_CMD_SHIFT 1 3509 #define ETH_CLASSIFY_CMD_HEADER_OPCODE (0x3<<2) 3510 #define ETH_CLASSIFY_CMD_HEADER_OPCODE_SHIFT 2 3511 #define ETH_CLASSIFY_CMD_HEADER_IS_ADD (0x1<<4) 3512 #define ETH_CLASSIFY_CMD_HEADER_IS_ADD_SHIFT 4 3513 #define ETH_CLASSIFY_CMD_HEADER_RESERVED0 (0x7<<5) 3514 #define ETH_CLASSIFY_CMD_HEADER_RESERVED0_SHIFT 5 3515 u8 func_id; 3516 u8 client_id; 3517 u8 reserved1; 3518 }; 3519 3520 3521 /* 3522 * header for eth classification config ramrod 3523 */ 3524 struct eth_classify_header { 3525 u8 rule_cnt; 3526 u8 reserved0; 3527 __le16 reserved1; 3528 __le32 echo; 3529 }; 3530 3531 3532 /* 3533 * Command for adding/removing a MAC classification rule 3534 */ 3535 struct eth_classify_mac_cmd { 3536 struct eth_classify_cmd_header header; 3537 __le32 reserved0; 3538 __le16 mac_lsb; 3539 __le16 mac_mid; 3540 __le16 mac_msb; 3541 __le16 reserved1; 3542 }; 3543 3544 3545 /* 3546 * Command for adding/removing a MAC-VLAN pair classification rule 3547 */ 3548 struct eth_classify_pair_cmd { 3549 struct eth_classify_cmd_header header; 3550 __le32 reserved0; 3551 __le16 mac_lsb; 3552 __le16 mac_mid; 3553 __le16 mac_msb; 3554 __le16 vlan; 3555 }; 3556 3557 3558 /* 3559 * Command for adding/removing a VLAN classification rule 3560 */ 3561 struct eth_classify_vlan_cmd { 3562 struct eth_classify_cmd_header header; 3563 __le32 reserved0; 3564 __le32 reserved1; 3565 __le16 reserved2; 3566 __le16 vlan; 3567 }; 3568 3569 /* 3570 * union for eth classification rule 3571 */ 3572 union eth_classify_rule_cmd { 3573 struct eth_classify_mac_cmd mac; 3574 struct eth_classify_vlan_cmd vlan; 3575 struct eth_classify_pair_cmd pair; 3576 }; 3577 3578 /* 3579 * parameters for eth classification configuration ramrod 3580 */ 3581 struct eth_classify_rules_ramrod_data { 3582 struct eth_classify_header header; 3583 union eth_classify_rule_cmd rules[CLASSIFY_RULES_COUNT]; 3584 }; 3585 3586 3587 /* 3588 * The data contain client ID need to the ramrod 3589 */ 3590 struct eth_common_ramrod_data { 3591 __le32 client_id; 3592 __le32 reserved1; 3593 }; 3594 3595 3596 /* 3597 * The eth storm context of Ustorm 3598 */ 3599 struct ustorm_eth_st_context { 3600 u32 reserved0[52]; 3601 }; 3602 3603 /* 3604 * The eth storm context of Tstorm 3605 */ 3606 struct tstorm_eth_st_context { 3607 u32 __reserved0[28]; 3608 }; 3609 3610 /* 3611 * The eth storm context of Xstorm 3612 */ 3613 struct xstorm_eth_st_context { 3614 u32 reserved0[60]; 3615 }; 3616 3617 /* 3618 * Ethernet connection context 3619 */ 3620 struct eth_context { 3621 struct ustorm_eth_st_context ustorm_st_context; 3622 struct tstorm_eth_st_context tstorm_st_context; 3623 struct xstorm_eth_ag_context xstorm_ag_context; 3624 struct tstorm_eth_ag_context tstorm_ag_context; 3625 struct cstorm_eth_ag_context cstorm_ag_context; 3626 struct ustorm_eth_ag_context ustorm_ag_context; 3627 struct timers_block_context timers_context; 3628 struct xstorm_eth_st_context xstorm_st_context; 3629 struct cstorm_eth_st_context cstorm_st_context; 3630 }; 3631 3632 3633 /* 3634 * union for sgl and raw data. 3635 */ 3636 union eth_sgl_or_raw_data { 3637 __le16 sgl[8]; 3638 u32 raw_data[4]; 3639 }; 3640 3641 /* 3642 * eth FP end aggregation CQE parameters struct 3643 */ 3644 struct eth_end_agg_rx_cqe { 3645 u8 type_error_flags; 3646 #define ETH_END_AGG_RX_CQE_TYPE (0x3<<0) 3647 #define ETH_END_AGG_RX_CQE_TYPE_SHIFT 0 3648 #define ETH_END_AGG_RX_CQE_SGL_RAW_SEL (0x1<<2) 3649 #define ETH_END_AGG_RX_CQE_SGL_RAW_SEL_SHIFT 2 3650 #define ETH_END_AGG_RX_CQE_RESERVED0 (0x1F<<3) 3651 #define ETH_END_AGG_RX_CQE_RESERVED0_SHIFT 3 3652 u8 reserved1; 3653 u8 queue_index; 3654 u8 reserved2; 3655 __le32 timestamp_delta; 3656 __le16 num_of_coalesced_segs; 3657 __le16 pkt_len; 3658 u8 pure_ack_count; 3659 u8 reserved3; 3660 __le16 reserved4; 3661 union eth_sgl_or_raw_data sgl_or_raw_data; 3662 __le32 reserved5[8]; 3663 }; 3664 3665 3666 /* 3667 * regular eth FP CQE parameters struct 3668 */ 3669 struct eth_fast_path_rx_cqe { 3670 u8 type_error_flags; 3671 #define ETH_FAST_PATH_RX_CQE_TYPE (0x3<<0) 3672 #define ETH_FAST_PATH_RX_CQE_TYPE_SHIFT 0 3673 #define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL (0x1<<2) 3674 #define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL_SHIFT 2 3675 #define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG (0x1<<3) 3676 #define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG_SHIFT 3 3677 #define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG (0x1<<4) 3678 #define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG_SHIFT 4 3679 #define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG (0x1<<5) 3680 #define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG_SHIFT 5 3681 #define ETH_FAST_PATH_RX_CQE_RESERVED0 (0x3<<6) 3682 #define ETH_FAST_PATH_RX_CQE_RESERVED0_SHIFT 6 3683 u8 status_flags; 3684 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE (0x7<<0) 3685 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE_SHIFT 0 3686 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG (0x1<<3) 3687 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG_SHIFT 3 3688 #define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG (0x1<<4) 3689 #define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG_SHIFT 4 3690 #define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG (0x1<<5) 3691 #define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG_SHIFT 5 3692 #define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG (0x1<<6) 3693 #define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG_SHIFT 6 3694 #define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG (0x1<<7) 3695 #define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG_SHIFT 7 3696 u8 queue_index; 3697 u8 placement_offset; 3698 __le32 rss_hash_result; 3699 __le16 vlan_tag; 3700 __le16 pkt_len_or_gro_seg_len; 3701 __le16 len_on_bd; 3702 struct parsing_flags pars_flags; 3703 union eth_sgl_or_raw_data sgl_or_raw_data; 3704 __le32 reserved1[8]; 3705 }; 3706 3707 3708 /* 3709 * Command for setting classification flags for a client 3710 */ 3711 struct eth_filter_rules_cmd { 3712 u8 cmd_general_data; 3713 #define ETH_FILTER_RULES_CMD_RX_CMD (0x1<<0) 3714 #define ETH_FILTER_RULES_CMD_RX_CMD_SHIFT 0 3715 #define ETH_FILTER_RULES_CMD_TX_CMD (0x1<<1) 3716 #define ETH_FILTER_RULES_CMD_TX_CMD_SHIFT 1 3717 #define ETH_FILTER_RULES_CMD_RESERVED0 (0x3F<<2) 3718 #define ETH_FILTER_RULES_CMD_RESERVED0_SHIFT 2 3719 u8 func_id; 3720 u8 client_id; 3721 u8 reserved1; 3722 __le16 state; 3723 #define ETH_FILTER_RULES_CMD_UCAST_DROP_ALL (0x1<<0) 3724 #define ETH_FILTER_RULES_CMD_UCAST_DROP_ALL_SHIFT 0 3725 #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL (0x1<<1) 3726 #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL_SHIFT 1 3727 #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED (0x1<<2) 3728 #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED_SHIFT 2 3729 #define ETH_FILTER_RULES_CMD_MCAST_DROP_ALL (0x1<<3) 3730 #define ETH_FILTER_RULES_CMD_MCAST_DROP_ALL_SHIFT 3 3731 #define ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL (0x1<<4) 3732 #define ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL_SHIFT 4 3733 #define ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL (0x1<<5) 3734 #define ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL_SHIFT 5 3735 #define ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN (0x1<<6) 3736 #define ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN_SHIFT 6 3737 #define ETH_FILTER_RULES_CMD_RESERVED2 (0x1FF<<7) 3738 #define ETH_FILTER_RULES_CMD_RESERVED2_SHIFT 7 3739 __le16 reserved3; 3740 struct regpair reserved4; 3741 }; 3742 3743 3744 /* 3745 * parameters for eth classification filters ramrod 3746 */ 3747 struct eth_filter_rules_ramrod_data { 3748 struct eth_classify_header header; 3749 struct eth_filter_rules_cmd rules[FILTER_RULES_COUNT]; 3750 }; 3751 3752 3753 /* 3754 * parameters for eth classification configuration ramrod 3755 */ 3756 struct eth_general_rules_ramrod_data { 3757 struct eth_classify_header header; 3758 union eth_classify_rule_cmd rules[CLASSIFY_RULES_COUNT]; 3759 }; 3760 3761 3762 /* 3763 * The data for Halt ramrod 3764 */ 3765 struct eth_halt_ramrod_data { 3766 __le32 client_id; 3767 __le32 reserved0; 3768 }; 3769 3770 3771 /* 3772 * Command for setting multicast classification for a client 3773 */ 3774 struct eth_multicast_rules_cmd { 3775 u8 cmd_general_data; 3776 #define ETH_MULTICAST_RULES_CMD_RX_CMD (0x1<<0) 3777 #define ETH_MULTICAST_RULES_CMD_RX_CMD_SHIFT 0 3778 #define ETH_MULTICAST_RULES_CMD_TX_CMD (0x1<<1) 3779 #define ETH_MULTICAST_RULES_CMD_TX_CMD_SHIFT 1 3780 #define ETH_MULTICAST_RULES_CMD_IS_ADD (0x1<<2) 3781 #define ETH_MULTICAST_RULES_CMD_IS_ADD_SHIFT 2 3782 #define ETH_MULTICAST_RULES_CMD_RESERVED0 (0x1F<<3) 3783 #define ETH_MULTICAST_RULES_CMD_RESERVED0_SHIFT 3 3784 u8 func_id; 3785 u8 bin_id; 3786 u8 engine_id; 3787 __le32 reserved2; 3788 struct regpair reserved3; 3789 }; 3790 3791 3792 /* 3793 * parameters for multicast classification ramrod 3794 */ 3795 struct eth_multicast_rules_ramrod_data { 3796 struct eth_classify_header header; 3797 struct eth_multicast_rules_cmd rules[MULTICAST_RULES_COUNT]; 3798 }; 3799 3800 3801 /* 3802 * Place holder for ramrods protocol specific data 3803 */ 3804 struct ramrod_data { 3805 __le32 data_lo; 3806 __le32 data_hi; 3807 }; 3808 3809 /* 3810 * union for ramrod data for Ethernet protocol (CQE) (force size of 16 bits) 3811 */ 3812 union eth_ramrod_data { 3813 struct ramrod_data general; 3814 }; 3815 3816 3817 /* 3818 * RSS toeplitz hash type, as reported in CQE 3819 */ 3820 enum eth_rss_hash_type { 3821 DEFAULT_HASH_TYPE, 3822 IPV4_HASH_TYPE, 3823 TCP_IPV4_HASH_TYPE, 3824 IPV6_HASH_TYPE, 3825 TCP_IPV6_HASH_TYPE, 3826 VLAN_PRI_HASH_TYPE, 3827 E1HOV_PRI_HASH_TYPE, 3828 DSCP_HASH_TYPE, 3829 MAX_ETH_RSS_HASH_TYPE 3830 }; 3831 3832 3833 /* 3834 * Ethernet RSS mode 3835 */ 3836 enum eth_rss_mode { 3837 ETH_RSS_MODE_DISABLED, 3838 ETH_RSS_MODE_REGULAR, 3839 ETH_RSS_MODE_VLAN_PRI, 3840 ETH_RSS_MODE_E1HOV_PRI, 3841 ETH_RSS_MODE_IP_DSCP, 3842 MAX_ETH_RSS_MODE 3843 }; 3844 3845 3846 /* 3847 * parameters for RSS update ramrod (E2) 3848 */ 3849 struct eth_rss_update_ramrod_data { 3850 u8 rss_engine_id; 3851 u8 capabilities; 3852 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY (0x1<<0) 3853 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY_SHIFT 0 3854 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY (0x1<<1) 3855 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY_SHIFT 1 3856 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY (0x1<<2) 3857 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY_SHIFT 2 3858 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY (0x1<<3) 3859 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY_SHIFT 3 3860 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY (0x1<<4) 3861 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY_SHIFT 4 3862 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY (0x1<<5) 3863 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY_SHIFT 5 3864 #define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY (0x1<<6) 3865 #define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY_SHIFT 6 3866 #define __ETH_RSS_UPDATE_RAMROD_DATA_RESERVED0 (0x1<<7) 3867 #define __ETH_RSS_UPDATE_RAMROD_DATA_RESERVED0_SHIFT 7 3868 u8 rss_result_mask; 3869 u8 rss_mode; 3870 __le32 __reserved2; 3871 u8 indirection_table[T_ETH_INDIRECTION_TABLE_SIZE]; 3872 __le32 rss_key[T_ETH_RSS_KEY]; 3873 __le32 echo; 3874 __le32 reserved3; 3875 }; 3876 3877 3878 /* 3879 * The eth Rx Buffer Descriptor 3880 */ 3881 struct eth_rx_bd { 3882 __le32 addr_lo; 3883 __le32 addr_hi; 3884 }; 3885 3886 3887 /* 3888 * Eth Rx Cqe structure- general structure for ramrods 3889 */ 3890 struct common_ramrod_eth_rx_cqe { 3891 u8 ramrod_type; 3892 #define COMMON_RAMROD_ETH_RX_CQE_TYPE (0x3<<0) 3893 #define COMMON_RAMROD_ETH_RX_CQE_TYPE_SHIFT 0 3894 #define COMMON_RAMROD_ETH_RX_CQE_ERROR (0x1<<2) 3895 #define COMMON_RAMROD_ETH_RX_CQE_ERROR_SHIFT 2 3896 #define COMMON_RAMROD_ETH_RX_CQE_RESERVED0 (0x1F<<3) 3897 #define COMMON_RAMROD_ETH_RX_CQE_RESERVED0_SHIFT 3 3898 u8 conn_type; 3899 __le16 reserved1; 3900 __le32 conn_and_cmd_data; 3901 #define COMMON_RAMROD_ETH_RX_CQE_CID (0xFFFFFF<<0) 3902 #define COMMON_RAMROD_ETH_RX_CQE_CID_SHIFT 0 3903 #define COMMON_RAMROD_ETH_RX_CQE_CMD_ID (0xFF<<24) 3904 #define COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT 24 3905 struct ramrod_data protocol_data; 3906 __le32 echo; 3907 __le32 reserved2[11]; 3908 }; 3909 3910 /* 3911 * Rx Last CQE in page (in ETH) 3912 */ 3913 struct eth_rx_cqe_next_page { 3914 __le32 addr_lo; 3915 __le32 addr_hi; 3916 __le32 reserved[14]; 3917 }; 3918 3919 /* 3920 * union for all eth rx cqe types (fix their sizes) 3921 */ 3922 union eth_rx_cqe { 3923 struct eth_fast_path_rx_cqe fast_path_cqe; 3924 struct common_ramrod_eth_rx_cqe ramrod_cqe; 3925 struct eth_rx_cqe_next_page next_page_cqe; 3926 struct eth_end_agg_rx_cqe end_agg_cqe; 3927 }; 3928 3929 3930 /* 3931 * Values for RX ETH CQE type field 3932 */ 3933 enum eth_rx_cqe_type { 3934 RX_ETH_CQE_TYPE_ETH_FASTPATH, 3935 RX_ETH_CQE_TYPE_ETH_RAMROD, 3936 RX_ETH_CQE_TYPE_ETH_START_AGG, 3937 RX_ETH_CQE_TYPE_ETH_STOP_AGG, 3938 MAX_ETH_RX_CQE_TYPE 3939 }; 3940 3941 3942 /* 3943 * Type of SGL/Raw field in ETH RX fast path CQE 3944 */ 3945 enum eth_rx_fp_sel { 3946 ETH_FP_CQE_REGULAR, 3947 ETH_FP_CQE_RAW, 3948 MAX_ETH_RX_FP_SEL 3949 }; 3950 3951 3952 /* 3953 * The eth Rx SGE Descriptor 3954 */ 3955 struct eth_rx_sge { 3956 __le32 addr_lo; 3957 __le32 addr_hi; 3958 }; 3959 3960 3961 /* 3962 * common data for all protocols 3963 */ 3964 struct spe_hdr { 3965 __le32 conn_and_cmd_data; 3966 #define SPE_HDR_CID (0xFFFFFF<<0) 3967 #define SPE_HDR_CID_SHIFT 0 3968 #define SPE_HDR_CMD_ID (0xFF<<24) 3969 #define SPE_HDR_CMD_ID_SHIFT 24 3970 __le16 type; 3971 #define SPE_HDR_CONN_TYPE (0xFF<<0) 3972 #define SPE_HDR_CONN_TYPE_SHIFT 0 3973 #define SPE_HDR_FUNCTION_ID (0xFF<<8) 3974 #define SPE_HDR_FUNCTION_ID_SHIFT 8 3975 __le16 reserved1; 3976 }; 3977 3978 /* 3979 * specific data for ethernet slow path element 3980 */ 3981 union eth_specific_data { 3982 u8 protocol_data[8]; 3983 struct regpair client_update_ramrod_data; 3984 struct regpair client_init_ramrod_init_data; 3985 struct eth_halt_ramrod_data halt_ramrod_data; 3986 struct regpair update_data_addr; 3987 struct eth_common_ramrod_data common_ramrod_data; 3988 struct regpair classify_cfg_addr; 3989 struct regpair filter_cfg_addr; 3990 struct regpair mcast_cfg_addr; 3991 }; 3992 3993 /* 3994 * Ethernet slow path element 3995 */ 3996 struct eth_spe { 3997 struct spe_hdr hdr; 3998 union eth_specific_data data; 3999 }; 4000 4001 4002 /* 4003 * Ethernet command ID for slow path elements 4004 */ 4005 enum eth_spqe_cmd_id { 4006 RAMROD_CMD_ID_ETH_UNUSED, 4007 RAMROD_CMD_ID_ETH_CLIENT_SETUP, 4008 RAMROD_CMD_ID_ETH_HALT, 4009 RAMROD_CMD_ID_ETH_FORWARD_SETUP, 4010 RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP, 4011 RAMROD_CMD_ID_ETH_CLIENT_UPDATE, 4012 RAMROD_CMD_ID_ETH_EMPTY, 4013 RAMROD_CMD_ID_ETH_TERMINATE, 4014 RAMROD_CMD_ID_ETH_TPA_UPDATE, 4015 RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES, 4016 RAMROD_CMD_ID_ETH_FILTER_RULES, 4017 RAMROD_CMD_ID_ETH_MULTICAST_RULES, 4018 RAMROD_CMD_ID_ETH_RSS_UPDATE, 4019 RAMROD_CMD_ID_ETH_SET_MAC, 4020 MAX_ETH_SPQE_CMD_ID 4021 }; 4022 4023 4024 /* 4025 * eth tpa update command 4026 */ 4027 enum eth_tpa_update_command { 4028 TPA_UPDATE_NONE_COMMAND, 4029 TPA_UPDATE_ENABLE_COMMAND, 4030 TPA_UPDATE_DISABLE_COMMAND, 4031 MAX_ETH_TPA_UPDATE_COMMAND 4032 }; 4033 4034 4035 /* 4036 * Tx regular BD structure 4037 */ 4038 struct eth_tx_bd { 4039 __le32 addr_lo; 4040 __le32 addr_hi; 4041 __le16 total_pkt_bytes; 4042 __le16 nbytes; 4043 u8 reserved[4]; 4044 }; 4045 4046 4047 /* 4048 * structure for easy accessibility to assembler 4049 */ 4050 struct eth_tx_bd_flags { 4051 u8 as_bitfield; 4052 #define ETH_TX_BD_FLAGS_IP_CSUM (0x1<<0) 4053 #define ETH_TX_BD_FLAGS_IP_CSUM_SHIFT 0 4054 #define ETH_TX_BD_FLAGS_L4_CSUM (0x1<<1) 4055 #define ETH_TX_BD_FLAGS_L4_CSUM_SHIFT 1 4056 #define ETH_TX_BD_FLAGS_VLAN_MODE (0x3<<2) 4057 #define ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT 2 4058 #define ETH_TX_BD_FLAGS_START_BD (0x1<<4) 4059 #define ETH_TX_BD_FLAGS_START_BD_SHIFT 4 4060 #define ETH_TX_BD_FLAGS_IS_UDP (0x1<<5) 4061 #define ETH_TX_BD_FLAGS_IS_UDP_SHIFT 5 4062 #define ETH_TX_BD_FLAGS_SW_LSO (0x1<<6) 4063 #define ETH_TX_BD_FLAGS_SW_LSO_SHIFT 6 4064 #define ETH_TX_BD_FLAGS_IPV6 (0x1<<7) 4065 #define ETH_TX_BD_FLAGS_IPV6_SHIFT 7 4066 }; 4067 4068 /* 4069 * The eth Tx Buffer Descriptor 4070 */ 4071 struct eth_tx_start_bd { 4072 __le32 addr_lo; 4073 __le32 addr_hi; 4074 __le16 nbd; 4075 __le16 nbytes; 4076 __le16 vlan_or_ethertype; 4077 struct eth_tx_bd_flags bd_flags; 4078 u8 general_data; 4079 #define ETH_TX_START_BD_HDR_NBDS (0xF<<0) 4080 #define ETH_TX_START_BD_HDR_NBDS_SHIFT 0 4081 #define ETH_TX_START_BD_FORCE_VLAN_MODE (0x1<<4) 4082 #define ETH_TX_START_BD_FORCE_VLAN_MODE_SHIFT 4 4083 #define ETH_TX_START_BD_RESREVED (0x1<<5) 4084 #define ETH_TX_START_BD_RESREVED_SHIFT 5 4085 #define ETH_TX_START_BD_ETH_ADDR_TYPE (0x3<<6) 4086 #define ETH_TX_START_BD_ETH_ADDR_TYPE_SHIFT 6 4087 }; 4088 4089 /* 4090 * Tx parsing BD structure for ETH E1/E1h 4091 */ 4092 struct eth_tx_parse_bd_e1x { 4093 u8 global_data; 4094 #define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W (0xF<<0) 4095 #define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W_SHIFT 0 4096 #define ETH_TX_PARSE_BD_E1X_RESERVED0 (0x1<<4) 4097 #define ETH_TX_PARSE_BD_E1X_RESERVED0_SHIFT 4 4098 #define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN (0x1<<5) 4099 #define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN_SHIFT 5 4100 #define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN (0x1<<6) 4101 #define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN_SHIFT 6 4102 #define ETH_TX_PARSE_BD_E1X_NS_FLG (0x1<<7) 4103 #define ETH_TX_PARSE_BD_E1X_NS_FLG_SHIFT 7 4104 u8 tcp_flags; 4105 #define ETH_TX_PARSE_BD_E1X_FIN_FLG (0x1<<0) 4106 #define ETH_TX_PARSE_BD_E1X_FIN_FLG_SHIFT 0 4107 #define ETH_TX_PARSE_BD_E1X_SYN_FLG (0x1<<1) 4108 #define ETH_TX_PARSE_BD_E1X_SYN_FLG_SHIFT 1 4109 #define ETH_TX_PARSE_BD_E1X_RST_FLG (0x1<<2) 4110 #define ETH_TX_PARSE_BD_E1X_RST_FLG_SHIFT 2 4111 #define ETH_TX_PARSE_BD_E1X_PSH_FLG (0x1<<3) 4112 #define ETH_TX_PARSE_BD_E1X_PSH_FLG_SHIFT 3 4113 #define ETH_TX_PARSE_BD_E1X_ACK_FLG (0x1<<4) 4114 #define ETH_TX_PARSE_BD_E1X_ACK_FLG_SHIFT 4 4115 #define ETH_TX_PARSE_BD_E1X_URG_FLG (0x1<<5) 4116 #define ETH_TX_PARSE_BD_E1X_URG_FLG_SHIFT 5 4117 #define ETH_TX_PARSE_BD_E1X_ECE_FLG (0x1<<6) 4118 #define ETH_TX_PARSE_BD_E1X_ECE_FLG_SHIFT 6 4119 #define ETH_TX_PARSE_BD_E1X_CWR_FLG (0x1<<7) 4120 #define ETH_TX_PARSE_BD_E1X_CWR_FLG_SHIFT 7 4121 u8 ip_hlen_w; 4122 s8 reserved; 4123 __le16 total_hlen_w; 4124 __le16 tcp_pseudo_csum; 4125 __le16 lso_mss; 4126 __le16 ip_id; 4127 __le32 tcp_send_seq; 4128 }; 4129 4130 /* 4131 * Tx parsing BD structure for ETH E2 4132 */ 4133 struct eth_tx_parse_bd_e2 { 4134 __le16 dst_mac_addr_lo; 4135 __le16 dst_mac_addr_mid; 4136 __le16 dst_mac_addr_hi; 4137 __le16 src_mac_addr_lo; 4138 __le16 src_mac_addr_mid; 4139 __le16 src_mac_addr_hi; 4140 __le32 parsing_data; 4141 #define ETH_TX_PARSE_BD_E2_TCP_HDR_START_OFFSET_W (0x1FFF<<0) 4142 #define ETH_TX_PARSE_BD_E2_TCP_HDR_START_OFFSET_W_SHIFT 0 4143 #define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW (0xF<<13) 4144 #define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW_SHIFT 13 4145 #define ETH_TX_PARSE_BD_E2_LSO_MSS (0x3FFF<<17) 4146 #define ETH_TX_PARSE_BD_E2_LSO_MSS_SHIFT 17 4147 #define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR (0x1<<31) 4148 #define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR_SHIFT 31 4149 }; 4150 4151 /* 4152 * The last BD in the BD memory will hold a pointer to the next BD memory 4153 */ 4154 struct eth_tx_next_bd { 4155 __le32 addr_lo; 4156 __le32 addr_hi; 4157 u8 reserved[8]; 4158 }; 4159 4160 /* 4161 * union for 4 Bd types 4162 */ 4163 union eth_tx_bd_types { 4164 struct eth_tx_start_bd start_bd; 4165 struct eth_tx_bd reg_bd; 4166 struct eth_tx_parse_bd_e1x parse_bd_e1x; 4167 struct eth_tx_parse_bd_e2 parse_bd_e2; 4168 struct eth_tx_next_bd next_bd; 4169 }; 4170 4171 /* 4172 * array of 13 bds as appears in the eth xstorm context 4173 */ 4174 struct eth_tx_bds_array { 4175 union eth_tx_bd_types bds[13]; 4176 }; 4177 4178 4179 /* 4180 * VLAN mode on TX BDs 4181 */ 4182 enum eth_tx_vlan_type { 4183 X_ETH_NO_VLAN, 4184 X_ETH_OUTBAND_VLAN, 4185 X_ETH_INBAND_VLAN, 4186 X_ETH_FW_ADDED_VLAN, 4187 MAX_ETH_TX_VLAN_TYPE 4188 }; 4189 4190 4191 /* 4192 * Ethernet VLAN filtering mode in E1x 4193 */ 4194 enum eth_vlan_filter_mode { 4195 ETH_VLAN_FILTER_ANY_VLAN, 4196 ETH_VLAN_FILTER_SPECIFIC_VLAN, 4197 ETH_VLAN_FILTER_CLASSIFY, 4198 MAX_ETH_VLAN_FILTER_MODE 4199 }; 4200 4201 4202 /* 4203 * MAC filtering configuration command header 4204 */ 4205 struct mac_configuration_hdr { 4206 u8 length; 4207 u8 offset; 4208 __le16 client_id; 4209 __le32 echo; 4210 }; 4211 4212 /* 4213 * MAC address in list for ramrod 4214 */ 4215 struct mac_configuration_entry { 4216 __le16 lsb_mac_addr; 4217 __le16 middle_mac_addr; 4218 __le16 msb_mac_addr; 4219 __le16 vlan_id; 4220 u8 pf_id; 4221 u8 flags; 4222 #define MAC_CONFIGURATION_ENTRY_ACTION_TYPE (0x1<<0) 4223 #define MAC_CONFIGURATION_ENTRY_ACTION_TYPE_SHIFT 0 4224 #define MAC_CONFIGURATION_ENTRY_RDMA_MAC (0x1<<1) 4225 #define MAC_CONFIGURATION_ENTRY_RDMA_MAC_SHIFT 1 4226 #define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE (0x3<<2) 4227 #define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE_SHIFT 2 4228 #define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL (0x1<<4) 4229 #define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL_SHIFT 4 4230 #define MAC_CONFIGURATION_ENTRY_BROADCAST (0x1<<5) 4231 #define MAC_CONFIGURATION_ENTRY_BROADCAST_SHIFT 5 4232 #define MAC_CONFIGURATION_ENTRY_RESERVED1 (0x3<<6) 4233 #define MAC_CONFIGURATION_ENTRY_RESERVED1_SHIFT 6 4234 __le16 reserved0; 4235 __le32 clients_bit_vector; 4236 }; 4237 4238 /* 4239 * MAC filtering configuration command 4240 */ 4241 struct mac_configuration_cmd { 4242 struct mac_configuration_hdr hdr; 4243 struct mac_configuration_entry config_table[64]; 4244 }; 4245 4246 4247 /* 4248 * Set-MAC command type (in E1x) 4249 */ 4250 enum set_mac_action_type { 4251 T_ETH_MAC_COMMAND_INVALIDATE, 4252 T_ETH_MAC_COMMAND_SET, 4253 MAX_SET_MAC_ACTION_TYPE 4254 }; 4255 4256 4257 /* 4258 * Ethernet TPA Modes 4259 */ 4260 enum tpa_mode { 4261 TPA_LRO, 4262 TPA_GRO, 4263 MAX_TPA_MODE}; 4264 4265 4266 /* 4267 * tpa update ramrod data 4268 */ 4269 struct tpa_update_ramrod_data { 4270 u8 update_ipv4; 4271 u8 update_ipv6; 4272 u8 client_id; 4273 u8 max_tpa_queues; 4274 u8 max_sges_for_packet; 4275 u8 complete_on_both_clients; 4276 u8 dont_verify_rings_pause_thr_flg; 4277 u8 tpa_mode; 4278 __le16 sge_buff_size; 4279 __le16 max_agg_size; 4280 __le32 sge_page_base_lo; 4281 __le32 sge_page_base_hi; 4282 __le16 sge_pause_thr_low; 4283 __le16 sge_pause_thr_high; 4284 }; 4285 4286 4287 /* 4288 * approximate-match multicast filtering for E1H per function in Tstorm 4289 */ 4290 struct tstorm_eth_approximate_match_multicast_filtering { 4291 u32 mcast_add_hash_bit_array[8]; 4292 }; 4293 4294 4295 /* 4296 * Common configuration parameters per function in Tstorm 4297 */ 4298 struct tstorm_eth_function_common_config { 4299 __le16 config_flags; 4300 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0) 4301 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0 4302 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1) 4303 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1 4304 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1<<2) 4305 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2 4306 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3) 4307 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3 4308 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE (0x7<<4) 4309 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT 4 4310 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE (0x1<<7) 4311 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE_SHIFT 7 4312 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0xFF<<8) 4313 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 8 4314 u8 rss_result_mask; 4315 u8 reserved1; 4316 __le16 vlan_id[2]; 4317 }; 4318 4319 4320 /* 4321 * MAC filtering configuration parameters per port in Tstorm 4322 */ 4323 struct tstorm_eth_mac_filter_config { 4324 __le32 ucast_drop_all; 4325 __le32 ucast_accept_all; 4326 __le32 mcast_drop_all; 4327 __le32 mcast_accept_all; 4328 __le32 bcast_accept_all; 4329 __le32 vlan_filter[2]; 4330 __le32 unmatched_unicast; 4331 }; 4332 4333 4334 /* 4335 * tx only queue init ramrod data 4336 */ 4337 struct tx_queue_init_ramrod_data { 4338 struct client_init_general_data general; 4339 struct client_init_tx_data tx; 4340 }; 4341 4342 4343 /* 4344 * Three RX producers for ETH 4345 */ 4346 struct ustorm_eth_rx_producers { 4347 #if defined(__BIG_ENDIAN) 4348 u16 bd_prod; 4349 u16 cqe_prod; 4350 #elif defined(__LITTLE_ENDIAN) 4351 u16 cqe_prod; 4352 u16 bd_prod; 4353 #endif 4354 #if defined(__BIG_ENDIAN) 4355 u16 reserved; 4356 u16 sge_prod; 4357 #elif defined(__LITTLE_ENDIAN) 4358 u16 sge_prod; 4359 u16 reserved; 4360 #endif 4361 }; 4362 4363 4364 /* 4365 * FCoE RX statistics parameters section#0 4366 */ 4367 struct fcoe_rx_stat_params_section0 { 4368 __le32 fcoe_rx_pkt_cnt; 4369 __le32 fcoe_rx_byte_cnt; 4370 }; 4371 4372 4373 /* 4374 * FCoE RX statistics parameters section#1 4375 */ 4376 struct fcoe_rx_stat_params_section1 { 4377 __le32 fcoe_ver_cnt; 4378 __le32 fcoe_rx_drop_pkt_cnt; 4379 }; 4380 4381 4382 /* 4383 * FCoE RX statistics parameters section#2 4384 */ 4385 struct fcoe_rx_stat_params_section2 { 4386 __le32 fc_crc_cnt; 4387 __le32 eofa_del_cnt; 4388 __le32 miss_frame_cnt; 4389 __le32 seq_timeout_cnt; 4390 __le32 drop_seq_cnt; 4391 __le32 fcoe_rx_drop_pkt_cnt; 4392 __le32 fcp_rx_pkt_cnt; 4393 __le32 reserved0; 4394 }; 4395 4396 4397 /* 4398 * FCoE TX statistics parameters 4399 */ 4400 struct fcoe_tx_stat_params { 4401 __le32 fcoe_tx_pkt_cnt; 4402 __le32 fcoe_tx_byte_cnt; 4403 __le32 fcp_tx_pkt_cnt; 4404 __le32 reserved0; 4405 }; 4406 4407 /* 4408 * FCoE statistics parameters 4409 */ 4410 struct fcoe_statistics_params { 4411 struct fcoe_tx_stat_params tx_stat; 4412 struct fcoe_rx_stat_params_section0 rx_stat0; 4413 struct fcoe_rx_stat_params_section1 rx_stat1; 4414 struct fcoe_rx_stat_params_section2 rx_stat2; 4415 }; 4416 4417 4418 /* 4419 * The data afex vif list ramrod need 4420 */ 4421 struct afex_vif_list_ramrod_data { 4422 u8 afex_vif_list_command; 4423 u8 func_bit_map; 4424 __le16 vif_list_index; 4425 u8 func_to_clear; 4426 u8 echo; 4427 __le16 reserved1; 4428 }; 4429 4430 4431 /* 4432 * cfc delete event data 4433 */ 4434 struct cfc_del_event_data { 4435 u32 cid; 4436 u32 reserved0; 4437 u32 reserved1; 4438 }; 4439 4440 4441 /* 4442 * per-port SAFC demo variables 4443 */ 4444 struct cmng_flags_per_port { 4445 u32 cmng_enables; 4446 #define CMNG_FLAGS_PER_PORT_FAIRNESS_VN (0x1<<0) 4447 #define CMNG_FLAGS_PER_PORT_FAIRNESS_VN_SHIFT 0 4448 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN (0x1<<1) 4449 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN_SHIFT 1 4450 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS (0x1<<2) 4451 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_SHIFT 2 4452 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE (0x1<<3) 4453 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE_SHIFT 3 4454 #define __CMNG_FLAGS_PER_PORT_RESERVED0 (0xFFFFFFF<<4) 4455 #define __CMNG_FLAGS_PER_PORT_RESERVED0_SHIFT 4 4456 u32 __reserved1; 4457 }; 4458 4459 4460 /* 4461 * per-port rate shaping variables 4462 */ 4463 struct rate_shaping_vars_per_port { 4464 u32 rs_periodic_timeout; 4465 u32 rs_threshold; 4466 }; 4467 4468 /* 4469 * per-port fairness variables 4470 */ 4471 struct fairness_vars_per_port { 4472 u32 upper_bound; 4473 u32 fair_threshold; 4474 u32 fairness_timeout; 4475 u32 reserved0; 4476 }; 4477 4478 /* 4479 * per-port SAFC variables 4480 */ 4481 struct safc_struct_per_port { 4482 #if defined(__BIG_ENDIAN) 4483 u16 __reserved1; 4484 u8 __reserved0; 4485 u8 safc_timeout_usec; 4486 #elif defined(__LITTLE_ENDIAN) 4487 u8 safc_timeout_usec; 4488 u8 __reserved0; 4489 u16 __reserved1; 4490 #endif 4491 u8 cos_to_traffic_types[MAX_COS_NUMBER]; 4492 u16 cos_to_pause_mask[NUM_OF_SAFC_BITS]; 4493 }; 4494 4495 /* 4496 * Per-port congestion management variables 4497 */ 4498 struct cmng_struct_per_port { 4499 struct rate_shaping_vars_per_port rs_vars; 4500 struct fairness_vars_per_port fair_vars; 4501 struct safc_struct_per_port safc_vars; 4502 struct cmng_flags_per_port flags; 4503 }; 4504 4505 /* 4506 * a single rate shaping counter. can be used as protocol or vnic counter 4507 */ 4508 struct rate_shaping_counter { 4509 u32 quota; 4510 #if defined(__BIG_ENDIAN) 4511 u16 __reserved0; 4512 u16 rate; 4513 #elif defined(__LITTLE_ENDIAN) 4514 u16 rate; 4515 u16 __reserved0; 4516 #endif 4517 }; 4518 4519 /* 4520 * per-vnic rate shaping variables 4521 */ 4522 struct rate_shaping_vars_per_vn { 4523 struct rate_shaping_counter vn_counter; 4524 }; 4525 4526 /* 4527 * per-vnic fairness variables 4528 */ 4529 struct fairness_vars_per_vn { 4530 u32 cos_credit_delta[MAX_COS_NUMBER]; 4531 u32 vn_credit_delta; 4532 u32 __reserved0; 4533 }; 4534 4535 /* 4536 * cmng port init state 4537 */ 4538 struct cmng_vnic { 4539 struct rate_shaping_vars_per_vn vnic_max_rate[4]; 4540 struct fairness_vars_per_vn vnic_min_rate[4]; 4541 }; 4542 4543 /* 4544 * cmng port init state 4545 */ 4546 struct cmng_init { 4547 struct cmng_struct_per_port port; 4548 struct cmng_vnic vnic; 4549 }; 4550 4551 4552 /* 4553 * driver parameters for congestion management init, all rates are in Mbps 4554 */ 4555 struct cmng_init_input { 4556 u32 port_rate; 4557 u16 vnic_min_rate[4]; 4558 u16 vnic_max_rate[4]; 4559 u16 cos_min_rate[MAX_COS_NUMBER]; 4560 u16 cos_to_pause_mask[MAX_COS_NUMBER]; 4561 struct cmng_flags_per_port flags; 4562 }; 4563 4564 4565 /* 4566 * Protocol-common command ID for slow path elements 4567 */ 4568 enum common_spqe_cmd_id { 4569 RAMROD_CMD_ID_COMMON_UNUSED, 4570 RAMROD_CMD_ID_COMMON_FUNCTION_START, 4571 RAMROD_CMD_ID_COMMON_FUNCTION_STOP, 4572 RAMROD_CMD_ID_COMMON_FUNCTION_UPDATE, 4573 RAMROD_CMD_ID_COMMON_CFC_DEL, 4574 RAMROD_CMD_ID_COMMON_CFC_DEL_WB, 4575 RAMROD_CMD_ID_COMMON_STAT_QUERY, 4576 RAMROD_CMD_ID_COMMON_STOP_TRAFFIC, 4577 RAMROD_CMD_ID_COMMON_START_TRAFFIC, 4578 RAMROD_CMD_ID_COMMON_AFEX_VIF_LISTS, 4579 MAX_COMMON_SPQE_CMD_ID 4580 }; 4581 4582 4583 /* 4584 * Per-protocol connection types 4585 */ 4586 enum connection_type { 4587 ETH_CONNECTION_TYPE, 4588 TOE_CONNECTION_TYPE, 4589 RDMA_CONNECTION_TYPE, 4590 ISCSI_CONNECTION_TYPE, 4591 FCOE_CONNECTION_TYPE, 4592 RESERVED_CONNECTION_TYPE_0, 4593 RESERVED_CONNECTION_TYPE_1, 4594 RESERVED_CONNECTION_TYPE_2, 4595 NONE_CONNECTION_TYPE, 4596 MAX_CONNECTION_TYPE 4597 }; 4598 4599 4600 /* 4601 * Cos modes 4602 */ 4603 enum cos_mode { 4604 OVERRIDE_COS, 4605 STATIC_COS, 4606 FW_WRR, 4607 MAX_COS_MODE 4608 }; 4609 4610 4611 /* 4612 * Dynamic HC counters set by the driver 4613 */ 4614 struct hc_dynamic_drv_counter { 4615 u32 val[HC_SB_MAX_DYNAMIC_INDICES]; 4616 }; 4617 4618 /* 4619 * zone A per-queue data 4620 */ 4621 struct cstorm_queue_zone_data { 4622 struct hc_dynamic_drv_counter hc_dyn_drv_cnt; 4623 struct regpair reserved[2]; 4624 }; 4625 4626 4627 /* 4628 * Vf-PF channel data in cstorm ram (non-triggered zone) 4629 */ 4630 struct vf_pf_channel_zone_data { 4631 u32 msg_addr_lo; 4632 u32 msg_addr_hi; 4633 }; 4634 4635 /* 4636 * zone for VF non-triggered data 4637 */ 4638 struct non_trigger_vf_zone { 4639 struct vf_pf_channel_zone_data vf_pf_channel; 4640 }; 4641 4642 /* 4643 * Vf-PF channel trigger zone in cstorm ram 4644 */ 4645 struct vf_pf_channel_zone_trigger { 4646 u8 addr_valid; 4647 }; 4648 4649 /* 4650 * zone that triggers the in-bound interrupt 4651 */ 4652 struct trigger_vf_zone { 4653 #if defined(__BIG_ENDIAN) 4654 u16 reserved1; 4655 u8 reserved0; 4656 struct vf_pf_channel_zone_trigger vf_pf_channel; 4657 #elif defined(__LITTLE_ENDIAN) 4658 struct vf_pf_channel_zone_trigger vf_pf_channel; 4659 u8 reserved0; 4660 u16 reserved1; 4661 #endif 4662 u32 reserved2; 4663 }; 4664 4665 /* 4666 * zone B per-VF data 4667 */ 4668 struct cstorm_vf_zone_data { 4669 struct non_trigger_vf_zone non_trigger; 4670 struct trigger_vf_zone trigger; 4671 }; 4672 4673 4674 /* 4675 * Dynamic host coalescing init parameters, per state machine 4676 */ 4677 struct dynamic_hc_sm_config { 4678 u32 threshold[3]; 4679 u8 shift_per_protocol[HC_SB_MAX_DYNAMIC_INDICES]; 4680 u8 hc_timeout0[HC_SB_MAX_DYNAMIC_INDICES]; 4681 u8 hc_timeout1[HC_SB_MAX_DYNAMIC_INDICES]; 4682 u8 hc_timeout2[HC_SB_MAX_DYNAMIC_INDICES]; 4683 u8 hc_timeout3[HC_SB_MAX_DYNAMIC_INDICES]; 4684 }; 4685 4686 /* 4687 * Dynamic host coalescing init parameters 4688 */ 4689 struct dynamic_hc_config { 4690 struct dynamic_hc_sm_config sm_config[HC_SB_MAX_SM]; 4691 }; 4692 4693 4694 struct e2_integ_data { 4695 #if defined(__BIG_ENDIAN) 4696 u8 flags; 4697 #define E2_INTEG_DATA_TESTING_EN (0x1<<0) 4698 #define E2_INTEG_DATA_TESTING_EN_SHIFT 0 4699 #define E2_INTEG_DATA_LB_TX (0x1<<1) 4700 #define E2_INTEG_DATA_LB_TX_SHIFT 1 4701 #define E2_INTEG_DATA_COS_TX (0x1<<2) 4702 #define E2_INTEG_DATA_COS_TX_SHIFT 2 4703 #define E2_INTEG_DATA_OPPORTUNISTICQM (0x1<<3) 4704 #define E2_INTEG_DATA_OPPORTUNISTICQM_SHIFT 3 4705 #define E2_INTEG_DATA_DPMTESTRELEASEDQ (0x1<<4) 4706 #define E2_INTEG_DATA_DPMTESTRELEASEDQ_SHIFT 4 4707 #define E2_INTEG_DATA_RESERVED (0x7<<5) 4708 #define E2_INTEG_DATA_RESERVED_SHIFT 5 4709 u8 cos; 4710 u8 voq; 4711 u8 pbf_queue; 4712 #elif defined(__LITTLE_ENDIAN) 4713 u8 pbf_queue; 4714 u8 voq; 4715 u8 cos; 4716 u8 flags; 4717 #define E2_INTEG_DATA_TESTING_EN (0x1<<0) 4718 #define E2_INTEG_DATA_TESTING_EN_SHIFT 0 4719 #define E2_INTEG_DATA_LB_TX (0x1<<1) 4720 #define E2_INTEG_DATA_LB_TX_SHIFT 1 4721 #define E2_INTEG_DATA_COS_TX (0x1<<2) 4722 #define E2_INTEG_DATA_COS_TX_SHIFT 2 4723 #define E2_INTEG_DATA_OPPORTUNISTICQM (0x1<<3) 4724 #define E2_INTEG_DATA_OPPORTUNISTICQM_SHIFT 3 4725 #define E2_INTEG_DATA_DPMTESTRELEASEDQ (0x1<<4) 4726 #define E2_INTEG_DATA_DPMTESTRELEASEDQ_SHIFT 4 4727 #define E2_INTEG_DATA_RESERVED (0x7<<5) 4728 #define E2_INTEG_DATA_RESERVED_SHIFT 5 4729 #endif 4730 #if defined(__BIG_ENDIAN) 4731 u16 reserved3; 4732 u8 reserved2; 4733 u8 ramEn; 4734 #elif defined(__LITTLE_ENDIAN) 4735 u8 ramEn; 4736 u8 reserved2; 4737 u16 reserved3; 4738 #endif 4739 }; 4740 4741 4742 /* 4743 * set mac event data 4744 */ 4745 struct eth_event_data { 4746 u32 echo; 4747 u32 reserved0; 4748 u32 reserved1; 4749 }; 4750 4751 4752 /* 4753 * pf-vf event data 4754 */ 4755 struct vf_pf_event_data { 4756 u8 vf_id; 4757 u8 reserved0; 4758 u16 reserved1; 4759 u32 msg_addr_lo; 4760 u32 msg_addr_hi; 4761 }; 4762 4763 /* 4764 * VF FLR event data 4765 */ 4766 struct vf_flr_event_data { 4767 u8 vf_id; 4768 u8 reserved0; 4769 u16 reserved1; 4770 u32 reserved2; 4771 u32 reserved3; 4772 }; 4773 4774 /* 4775 * malicious VF event data 4776 */ 4777 struct malicious_vf_event_data { 4778 u8 vf_id; 4779 u8 reserved0; 4780 u16 reserved1; 4781 u32 reserved2; 4782 u32 reserved3; 4783 }; 4784 4785 /* 4786 * vif list event data 4787 */ 4788 struct vif_list_event_data { 4789 u8 func_bit_map; 4790 u8 echo; 4791 __le16 reserved0; 4792 __le32 reserved1; 4793 __le32 reserved2; 4794 }; 4795 4796 /* 4797 * union for all event ring message types 4798 */ 4799 union event_data { 4800 struct vf_pf_event_data vf_pf_event; 4801 struct eth_event_data eth_event; 4802 struct cfc_del_event_data cfc_del_event; 4803 struct vf_flr_event_data vf_flr_event; 4804 struct malicious_vf_event_data malicious_vf_event; 4805 struct vif_list_event_data vif_list_event; 4806 }; 4807 4808 4809 /* 4810 * per PF event ring data 4811 */ 4812 struct event_ring_data { 4813 struct regpair base_addr; 4814 #if defined(__BIG_ENDIAN) 4815 u8 index_id; 4816 u8 sb_id; 4817 u16 producer; 4818 #elif defined(__LITTLE_ENDIAN) 4819 u16 producer; 4820 u8 sb_id; 4821 u8 index_id; 4822 #endif 4823 u32 reserved0; 4824 }; 4825 4826 4827 /* 4828 * event ring message element (each element is 128 bits) 4829 */ 4830 struct event_ring_msg { 4831 u8 opcode; 4832 u8 error; 4833 u16 reserved1; 4834 union event_data data; 4835 }; 4836 4837 /* 4838 * event ring next page element (128 bits) 4839 */ 4840 struct event_ring_next { 4841 struct regpair addr; 4842 u32 reserved[2]; 4843 }; 4844 4845 /* 4846 * union for event ring element types (each element is 128 bits) 4847 */ 4848 union event_ring_elem { 4849 struct event_ring_msg message; 4850 struct event_ring_next next_page; 4851 }; 4852 4853 4854 /* 4855 * Common event ring opcodes 4856 */ 4857 enum event_ring_opcode { 4858 EVENT_RING_OPCODE_VF_PF_CHANNEL, 4859 EVENT_RING_OPCODE_FUNCTION_START, 4860 EVENT_RING_OPCODE_FUNCTION_STOP, 4861 EVENT_RING_OPCODE_CFC_DEL, 4862 EVENT_RING_OPCODE_CFC_DEL_WB, 4863 EVENT_RING_OPCODE_STAT_QUERY, 4864 EVENT_RING_OPCODE_STOP_TRAFFIC, 4865 EVENT_RING_OPCODE_START_TRAFFIC, 4866 EVENT_RING_OPCODE_VF_FLR, 4867 EVENT_RING_OPCODE_MALICIOUS_VF, 4868 EVENT_RING_OPCODE_FORWARD_SETUP, 4869 EVENT_RING_OPCODE_RSS_UPDATE_RULES, 4870 EVENT_RING_OPCODE_FUNCTION_UPDATE, 4871 EVENT_RING_OPCODE_AFEX_VIF_LISTS, 4872 EVENT_RING_OPCODE_SET_MAC, 4873 EVENT_RING_OPCODE_CLASSIFICATION_RULES, 4874 EVENT_RING_OPCODE_FILTERS_RULES, 4875 EVENT_RING_OPCODE_MULTICAST_RULES, 4876 MAX_EVENT_RING_OPCODE 4877 }; 4878 4879 4880 /* 4881 * Modes for fairness algorithm 4882 */ 4883 enum fairness_mode { 4884 FAIRNESS_COS_WRR_MODE, 4885 FAIRNESS_COS_ETS_MODE, 4886 MAX_FAIRNESS_MODE 4887 }; 4888 4889 4890 /* 4891 * Priority and cos 4892 */ 4893 struct priority_cos { 4894 u8 priority; 4895 u8 cos; 4896 __le16 reserved1; 4897 }; 4898 4899 /* 4900 * The data for flow control configuration 4901 */ 4902 struct flow_control_configuration { 4903 struct priority_cos traffic_type_to_priority_cos[MAX_TRAFFIC_TYPES]; 4904 u8 dcb_enabled; 4905 u8 dcb_version; 4906 u8 dont_add_pri_0_en; 4907 u8 reserved1; 4908 __le32 reserved2; 4909 }; 4910 4911 4912 /* 4913 * 4914 */ 4915 struct function_start_data { 4916 __le16 function_mode; 4917 __le16 sd_vlan_tag; 4918 __le16 vif_id; 4919 u8 path_id; 4920 u8 network_cos_mode; 4921 }; 4922 4923 4924 struct function_update_data { 4925 u8 vif_id_change_flg; 4926 u8 afex_default_vlan_change_flg; 4927 u8 allowed_priorities_change_flg; 4928 u8 network_cos_mode_change_flg; 4929 __le16 vif_id; 4930 __le16 afex_default_vlan; 4931 u8 allowed_priorities; 4932 u8 network_cos_mode; 4933 u8 lb_mode_en; 4934 u8 reserved0; 4935 __le32 reserved1; 4936 }; 4937 4938 4939 /* 4940 * FW version stored in the Xstorm RAM 4941 */ 4942 struct fw_version { 4943 #if defined(__BIG_ENDIAN) 4944 u8 engineering; 4945 u8 revision; 4946 u8 minor; 4947 u8 major; 4948 #elif defined(__LITTLE_ENDIAN) 4949 u8 major; 4950 u8 minor; 4951 u8 revision; 4952 u8 engineering; 4953 #endif 4954 u32 flags; 4955 #define FW_VERSION_OPTIMIZED (0x1<<0) 4956 #define FW_VERSION_OPTIMIZED_SHIFT 0 4957 #define FW_VERSION_BIG_ENDIEN (0x1<<1) 4958 #define FW_VERSION_BIG_ENDIEN_SHIFT 1 4959 #define FW_VERSION_CHIP_VERSION (0x3<<2) 4960 #define FW_VERSION_CHIP_VERSION_SHIFT 2 4961 #define __FW_VERSION_RESERVED (0xFFFFFFF<<4) 4962 #define __FW_VERSION_RESERVED_SHIFT 4 4963 }; 4964 4965 4966 /* 4967 * Dynamic Host-Coalescing - Driver(host) counters 4968 */ 4969 struct hc_dynamic_sb_drv_counters { 4970 u32 dynamic_hc_drv_counter[HC_SB_MAX_DYNAMIC_INDICES]; 4971 }; 4972 4973 4974 /* 4975 * 2 bytes. configuration/state parameters for a single protocol index 4976 */ 4977 struct hc_index_data { 4978 #if defined(__BIG_ENDIAN) 4979 u8 flags; 4980 #define HC_INDEX_DATA_SM_ID (0x1<<0) 4981 #define HC_INDEX_DATA_SM_ID_SHIFT 0 4982 #define HC_INDEX_DATA_HC_ENABLED (0x1<<1) 4983 #define HC_INDEX_DATA_HC_ENABLED_SHIFT 1 4984 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2) 4985 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2 4986 #define HC_INDEX_DATA_RESERVE (0x1F<<3) 4987 #define HC_INDEX_DATA_RESERVE_SHIFT 3 4988 u8 timeout; 4989 #elif defined(__LITTLE_ENDIAN) 4990 u8 timeout; 4991 u8 flags; 4992 #define HC_INDEX_DATA_SM_ID (0x1<<0) 4993 #define HC_INDEX_DATA_SM_ID_SHIFT 0 4994 #define HC_INDEX_DATA_HC_ENABLED (0x1<<1) 4995 #define HC_INDEX_DATA_HC_ENABLED_SHIFT 1 4996 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2) 4997 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2 4998 #define HC_INDEX_DATA_RESERVE (0x1F<<3) 4999 #define HC_INDEX_DATA_RESERVE_SHIFT 3 5000 #endif 5001 }; 5002 5003 5004 /* 5005 * HC state-machine 5006 */ 5007 struct hc_status_block_sm { 5008 #if defined(__BIG_ENDIAN) 5009 u8 igu_seg_id; 5010 u8 igu_sb_id; 5011 u8 timer_value; 5012 u8 __flags; 5013 #elif defined(__LITTLE_ENDIAN) 5014 u8 __flags; 5015 u8 timer_value; 5016 u8 igu_sb_id; 5017 u8 igu_seg_id; 5018 #endif 5019 u32 time_to_expire; 5020 }; 5021 5022 /* 5023 * hold PCI identification variables- used in various places in firmware 5024 */ 5025 struct pci_entity { 5026 #if defined(__BIG_ENDIAN) 5027 u8 vf_valid; 5028 u8 vf_id; 5029 u8 vnic_id; 5030 u8 pf_id; 5031 #elif defined(__LITTLE_ENDIAN) 5032 u8 pf_id; 5033 u8 vnic_id; 5034 u8 vf_id; 5035 u8 vf_valid; 5036 #endif 5037 }; 5038 5039 /* 5040 * The fast-path status block meta-data, common to all chips 5041 */ 5042 struct hc_sb_data { 5043 struct regpair host_sb_addr; 5044 struct hc_status_block_sm state_machine[HC_SB_MAX_SM]; 5045 struct pci_entity p_func; 5046 #if defined(__BIG_ENDIAN) 5047 u8 rsrv0; 5048 u8 state; 5049 u8 dhc_qzone_id; 5050 u8 same_igu_sb_1b; 5051 #elif defined(__LITTLE_ENDIAN) 5052 u8 same_igu_sb_1b; 5053 u8 dhc_qzone_id; 5054 u8 state; 5055 u8 rsrv0; 5056 #endif 5057 struct regpair rsrv1[2]; 5058 }; 5059 5060 5061 /* 5062 * Segment types for host coaslescing 5063 */ 5064 enum hc_segment { 5065 HC_REGULAR_SEGMENT, 5066 HC_DEFAULT_SEGMENT, 5067 MAX_HC_SEGMENT 5068 }; 5069 5070 5071 /* 5072 * The fast-path status block meta-data 5073 */ 5074 struct hc_sp_status_block_data { 5075 struct regpair host_sb_addr; 5076 #if defined(__BIG_ENDIAN) 5077 u8 rsrv1; 5078 u8 state; 5079 u8 igu_seg_id; 5080 u8 igu_sb_id; 5081 #elif defined(__LITTLE_ENDIAN) 5082 u8 igu_sb_id; 5083 u8 igu_seg_id; 5084 u8 state; 5085 u8 rsrv1; 5086 #endif 5087 struct pci_entity p_func; 5088 }; 5089 5090 5091 /* 5092 * The fast-path status block meta-data 5093 */ 5094 struct hc_status_block_data_e1x { 5095 struct hc_index_data index_data[HC_SB_MAX_INDICES_E1X]; 5096 struct hc_sb_data common; 5097 }; 5098 5099 5100 /* 5101 * The fast-path status block meta-data 5102 */ 5103 struct hc_status_block_data_e2 { 5104 struct hc_index_data index_data[HC_SB_MAX_INDICES_E2]; 5105 struct hc_sb_data common; 5106 }; 5107 5108 5109 /* 5110 * IGU block operartion modes (in Everest2) 5111 */ 5112 enum igu_mode { 5113 HC_IGU_BC_MODE, 5114 HC_IGU_NBC_MODE, 5115 MAX_IGU_MODE 5116 }; 5117 5118 5119 /* 5120 * IP versions 5121 */ 5122 enum ip_ver { 5123 IP_V4, 5124 IP_V6, 5125 MAX_IP_VER 5126 }; 5127 5128 5129 /* 5130 * Multi-function modes 5131 */ 5132 enum mf_mode { 5133 SINGLE_FUNCTION, 5134 MULTI_FUNCTION_SD, 5135 MULTI_FUNCTION_SI, 5136 MULTI_FUNCTION_AFEX, 5137 MAX_MF_MODE 5138 }; 5139 5140 /* 5141 * Protocol-common statistics collected by the Tstorm (per pf) 5142 */ 5143 struct tstorm_per_pf_stats { 5144 struct regpair rcv_error_bytes; 5145 }; 5146 5147 /* 5148 * 5149 */ 5150 struct per_pf_stats { 5151 struct tstorm_per_pf_stats tstorm_pf_statistics; 5152 }; 5153 5154 5155 /* 5156 * Protocol-common statistics collected by the Tstorm (per port) 5157 */ 5158 struct tstorm_per_port_stats { 5159 __le32 mac_discard; 5160 __le32 mac_filter_discard; 5161 __le32 brb_truncate_discard; 5162 __le32 mf_tag_discard; 5163 __le32 packet_drop; 5164 __le32 reserved; 5165 }; 5166 5167 /* 5168 * 5169 */ 5170 struct per_port_stats { 5171 struct tstorm_per_port_stats tstorm_port_statistics; 5172 }; 5173 5174 5175 /* 5176 * Protocol-common statistics collected by the Tstorm (per client) 5177 */ 5178 struct tstorm_per_queue_stats { 5179 struct regpair rcv_ucast_bytes; 5180 __le32 rcv_ucast_pkts; 5181 __le32 checksum_discard; 5182 struct regpair rcv_bcast_bytes; 5183 __le32 rcv_bcast_pkts; 5184 __le32 pkts_too_big_discard; 5185 struct regpair rcv_mcast_bytes; 5186 __le32 rcv_mcast_pkts; 5187 __le32 ttl0_discard; 5188 __le16 no_buff_discard; 5189 __le16 reserved0; 5190 __le32 reserved1; 5191 }; 5192 5193 /* 5194 * Protocol-common statistics collected by the Ustorm (per client) 5195 */ 5196 struct ustorm_per_queue_stats { 5197 struct regpair ucast_no_buff_bytes; 5198 struct regpair mcast_no_buff_bytes; 5199 struct regpair bcast_no_buff_bytes; 5200 __le32 ucast_no_buff_pkts; 5201 __le32 mcast_no_buff_pkts; 5202 __le32 bcast_no_buff_pkts; 5203 __le32 coalesced_pkts; 5204 struct regpair coalesced_bytes; 5205 __le32 coalesced_events; 5206 __le32 coalesced_aborts; 5207 }; 5208 5209 /* 5210 * Protocol-common statistics collected by the Xstorm (per client) 5211 */ 5212 struct xstorm_per_queue_stats { 5213 struct regpair ucast_bytes_sent; 5214 struct regpair mcast_bytes_sent; 5215 struct regpair bcast_bytes_sent; 5216 __le32 ucast_pkts_sent; 5217 __le32 mcast_pkts_sent; 5218 __le32 bcast_pkts_sent; 5219 __le32 error_drop_pkts; 5220 }; 5221 5222 /* 5223 * 5224 */ 5225 struct per_queue_stats { 5226 struct tstorm_per_queue_stats tstorm_queue_statistics; 5227 struct ustorm_per_queue_stats ustorm_queue_statistics; 5228 struct xstorm_per_queue_stats xstorm_queue_statistics; 5229 }; 5230 5231 5232 /* 5233 * FW version stored in first line of pram 5234 */ 5235 struct pram_fw_version { 5236 u8 major; 5237 u8 minor; 5238 u8 revision; 5239 u8 engineering; 5240 u8 flags; 5241 #define PRAM_FW_VERSION_OPTIMIZED (0x1<<0) 5242 #define PRAM_FW_VERSION_OPTIMIZED_SHIFT 0 5243 #define PRAM_FW_VERSION_STORM_ID (0x3<<1) 5244 #define PRAM_FW_VERSION_STORM_ID_SHIFT 1 5245 #define PRAM_FW_VERSION_BIG_ENDIEN (0x1<<3) 5246 #define PRAM_FW_VERSION_BIG_ENDIEN_SHIFT 3 5247 #define PRAM_FW_VERSION_CHIP_VERSION (0x3<<4) 5248 #define PRAM_FW_VERSION_CHIP_VERSION_SHIFT 4 5249 #define __PRAM_FW_VERSION_RESERVED0 (0x3<<6) 5250 #define __PRAM_FW_VERSION_RESERVED0_SHIFT 6 5251 }; 5252 5253 5254 /* 5255 * Ethernet slow path element 5256 */ 5257 union protocol_common_specific_data { 5258 u8 protocol_data[8]; 5259 struct regpair phy_address; 5260 struct regpair mac_config_addr; 5261 struct afex_vif_list_ramrod_data afex_vif_list_data; 5262 }; 5263 5264 /* 5265 * The send queue element 5266 */ 5267 struct protocol_common_spe { 5268 struct spe_hdr hdr; 5269 union protocol_common_specific_data data; 5270 }; 5271 5272 5273 /* 5274 * The send queue element 5275 */ 5276 struct slow_path_element { 5277 struct spe_hdr hdr; 5278 struct regpair protocol_data; 5279 }; 5280 5281 5282 /* 5283 * Protocol-common statistics counter 5284 */ 5285 struct stats_counter { 5286 __le16 xstats_counter; 5287 __le16 reserved0; 5288 __le32 reserved1; 5289 __le16 tstats_counter; 5290 __le16 reserved2; 5291 __le32 reserved3; 5292 __le16 ustats_counter; 5293 __le16 reserved4; 5294 __le32 reserved5; 5295 __le16 cstats_counter; 5296 __le16 reserved6; 5297 __le32 reserved7; 5298 }; 5299 5300 5301 /* 5302 * 5303 */ 5304 struct stats_query_entry { 5305 u8 kind; 5306 u8 index; 5307 __le16 funcID; 5308 __le32 reserved; 5309 struct regpair address; 5310 }; 5311 5312 /* 5313 * statistic command 5314 */ 5315 struct stats_query_cmd_group { 5316 struct stats_query_entry query[STATS_QUERY_CMD_COUNT]; 5317 }; 5318 5319 5320 /* 5321 * statistic command header 5322 */ 5323 struct stats_query_header { 5324 u8 cmd_num; 5325 u8 reserved0; 5326 __le16 drv_stats_counter; 5327 __le32 reserved1; 5328 struct regpair stats_counters_addrs; 5329 }; 5330 5331 5332 /* 5333 * Types of statistcis query entry 5334 */ 5335 enum stats_query_type { 5336 STATS_TYPE_QUEUE, 5337 STATS_TYPE_PORT, 5338 STATS_TYPE_PF, 5339 STATS_TYPE_TOE, 5340 STATS_TYPE_FCOE, 5341 MAX_STATS_QUERY_TYPE 5342 }; 5343 5344 5345 /* 5346 * Indicate of the function status block state 5347 */ 5348 enum status_block_state { 5349 SB_DISABLED, 5350 SB_ENABLED, 5351 SB_CLEANED, 5352 MAX_STATUS_BLOCK_STATE 5353 }; 5354 5355 5356 /* 5357 * Storm IDs (including attentions for IGU related enums) 5358 */ 5359 enum storm_id { 5360 USTORM_ID, 5361 CSTORM_ID, 5362 XSTORM_ID, 5363 TSTORM_ID, 5364 ATTENTION_ID, 5365 MAX_STORM_ID 5366 }; 5367 5368 5369 /* 5370 * Taffic types used in ETS and flow control algorithms 5371 */ 5372 enum traffic_type { 5373 LLFC_TRAFFIC_TYPE_NW, 5374 LLFC_TRAFFIC_TYPE_FCOE, 5375 LLFC_TRAFFIC_TYPE_ISCSI, 5376 MAX_TRAFFIC_TYPE 5377 }; 5378 5379 5380 /* 5381 * zone A per-queue data 5382 */ 5383 struct tstorm_queue_zone_data { 5384 struct regpair reserved[4]; 5385 }; 5386 5387 5388 /* 5389 * zone B per-VF data 5390 */ 5391 struct tstorm_vf_zone_data { 5392 struct regpair reserved; 5393 }; 5394 5395 5396 /* 5397 * zone A per-queue data 5398 */ 5399 struct ustorm_queue_zone_data { 5400 struct ustorm_eth_rx_producers eth_rx_producers; 5401 struct regpair reserved[3]; 5402 }; 5403 5404 5405 /* 5406 * zone B per-VF data 5407 */ 5408 struct ustorm_vf_zone_data { 5409 struct regpair reserved; 5410 }; 5411 5412 5413 /* 5414 * data per VF-PF channel 5415 */ 5416 struct vf_pf_channel_data { 5417 #if defined(__BIG_ENDIAN) 5418 u16 reserved0; 5419 u8 valid; 5420 u8 state; 5421 #elif defined(__LITTLE_ENDIAN) 5422 u8 state; 5423 u8 valid; 5424 u16 reserved0; 5425 #endif 5426 u32 reserved1; 5427 }; 5428 5429 5430 /* 5431 * State of VF-PF channel 5432 */ 5433 enum vf_pf_channel_state { 5434 VF_PF_CHANNEL_STATE_READY, 5435 VF_PF_CHANNEL_STATE_WAITING_FOR_ACK, 5436 MAX_VF_PF_CHANNEL_STATE 5437 }; 5438 5439 5440 /* 5441 * vif_list_rule_kind 5442 */ 5443 enum vif_list_rule_kind { 5444 VIF_LIST_RULE_SET, 5445 VIF_LIST_RULE_GET, 5446 VIF_LIST_RULE_CLEAR_ALL, 5447 VIF_LIST_RULE_CLEAR_FUNC, 5448 MAX_VIF_LIST_RULE_KIND 5449 }; 5450 5451 5452 /* 5453 * zone A per-queue data 5454 */ 5455 struct xstorm_queue_zone_data { 5456 struct regpair reserved[4]; 5457 }; 5458 5459 5460 /* 5461 * zone B per-VF data 5462 */ 5463 struct xstorm_vf_zone_data { 5464 struct regpair reserved; 5465 }; 5466 5467 #endif /* BNX2X_HSI_H */ 5468