1 /* bnx2x_hsi.h: Broadcom Everest network driver. 2 * 3 * Copyright (c) 2007-2013 Broadcom Corporation 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation. 8 */ 9 #ifndef BNX2X_HSI_H 10 #define BNX2X_HSI_H 11 12 #include "bnx2x_fw_defs.h" 13 #include "bnx2x_mfw_req.h" 14 15 #define FW_ENCODE_32BIT_PATTERN 0x1e1e1e1e 16 17 struct license_key { 18 u32 reserved[6]; 19 20 u32 max_iscsi_conn; 21 #define BNX2X_MAX_ISCSI_TRGT_CONN_MASK 0xFFFF 22 #define BNX2X_MAX_ISCSI_TRGT_CONN_SHIFT 0 23 #define BNX2X_MAX_ISCSI_INIT_CONN_MASK 0xFFFF0000 24 #define BNX2X_MAX_ISCSI_INIT_CONN_SHIFT 16 25 26 u32 reserved_a; 27 28 u32 max_fcoe_conn; 29 #define BNX2X_MAX_FCOE_TRGT_CONN_MASK 0xFFFF 30 #define BNX2X_MAX_FCOE_TRGT_CONN_SHIFT 0 31 #define BNX2X_MAX_FCOE_INIT_CONN_MASK 0xFFFF0000 32 #define BNX2X_MAX_FCOE_INIT_CONN_SHIFT 16 33 34 u32 reserved_b[4]; 35 }; 36 37 /**************************************************************************** 38 * Shared HW configuration * 39 ****************************************************************************/ 40 #define PIN_CFG_NA 0x00000000 41 #define PIN_CFG_GPIO0_P0 0x00000001 42 #define PIN_CFG_GPIO1_P0 0x00000002 43 #define PIN_CFG_GPIO2_P0 0x00000003 44 #define PIN_CFG_GPIO3_P0 0x00000004 45 #define PIN_CFG_GPIO0_P1 0x00000005 46 #define PIN_CFG_GPIO1_P1 0x00000006 47 #define PIN_CFG_GPIO2_P1 0x00000007 48 #define PIN_CFG_GPIO3_P1 0x00000008 49 #define PIN_CFG_EPIO0 0x00000009 50 #define PIN_CFG_EPIO1 0x0000000a 51 #define PIN_CFG_EPIO2 0x0000000b 52 #define PIN_CFG_EPIO3 0x0000000c 53 #define PIN_CFG_EPIO4 0x0000000d 54 #define PIN_CFG_EPIO5 0x0000000e 55 #define PIN_CFG_EPIO6 0x0000000f 56 #define PIN_CFG_EPIO7 0x00000010 57 #define PIN_CFG_EPIO8 0x00000011 58 #define PIN_CFG_EPIO9 0x00000012 59 #define PIN_CFG_EPIO10 0x00000013 60 #define PIN_CFG_EPIO11 0x00000014 61 #define PIN_CFG_EPIO12 0x00000015 62 #define PIN_CFG_EPIO13 0x00000016 63 #define PIN_CFG_EPIO14 0x00000017 64 #define PIN_CFG_EPIO15 0x00000018 65 #define PIN_CFG_EPIO16 0x00000019 66 #define PIN_CFG_EPIO17 0x0000001a 67 #define PIN_CFG_EPIO18 0x0000001b 68 #define PIN_CFG_EPIO19 0x0000001c 69 #define PIN_CFG_EPIO20 0x0000001d 70 #define PIN_CFG_EPIO21 0x0000001e 71 #define PIN_CFG_EPIO22 0x0000001f 72 #define PIN_CFG_EPIO23 0x00000020 73 #define PIN_CFG_EPIO24 0x00000021 74 #define PIN_CFG_EPIO25 0x00000022 75 #define PIN_CFG_EPIO26 0x00000023 76 #define PIN_CFG_EPIO27 0x00000024 77 #define PIN_CFG_EPIO28 0x00000025 78 #define PIN_CFG_EPIO29 0x00000026 79 #define PIN_CFG_EPIO30 0x00000027 80 #define PIN_CFG_EPIO31 0x00000028 81 82 /* EPIO definition */ 83 #define EPIO_CFG_NA 0x00000000 84 #define EPIO_CFG_EPIO0 0x00000001 85 #define EPIO_CFG_EPIO1 0x00000002 86 #define EPIO_CFG_EPIO2 0x00000003 87 #define EPIO_CFG_EPIO3 0x00000004 88 #define EPIO_CFG_EPIO4 0x00000005 89 #define EPIO_CFG_EPIO5 0x00000006 90 #define EPIO_CFG_EPIO6 0x00000007 91 #define EPIO_CFG_EPIO7 0x00000008 92 #define EPIO_CFG_EPIO8 0x00000009 93 #define EPIO_CFG_EPIO9 0x0000000a 94 #define EPIO_CFG_EPIO10 0x0000000b 95 #define EPIO_CFG_EPIO11 0x0000000c 96 #define EPIO_CFG_EPIO12 0x0000000d 97 #define EPIO_CFG_EPIO13 0x0000000e 98 #define EPIO_CFG_EPIO14 0x0000000f 99 #define EPIO_CFG_EPIO15 0x00000010 100 #define EPIO_CFG_EPIO16 0x00000011 101 #define EPIO_CFG_EPIO17 0x00000012 102 #define EPIO_CFG_EPIO18 0x00000013 103 #define EPIO_CFG_EPIO19 0x00000014 104 #define EPIO_CFG_EPIO20 0x00000015 105 #define EPIO_CFG_EPIO21 0x00000016 106 #define EPIO_CFG_EPIO22 0x00000017 107 #define EPIO_CFG_EPIO23 0x00000018 108 #define EPIO_CFG_EPIO24 0x00000019 109 #define EPIO_CFG_EPIO25 0x0000001a 110 #define EPIO_CFG_EPIO26 0x0000001b 111 #define EPIO_CFG_EPIO27 0x0000001c 112 #define EPIO_CFG_EPIO28 0x0000001d 113 #define EPIO_CFG_EPIO29 0x0000001e 114 #define EPIO_CFG_EPIO30 0x0000001f 115 #define EPIO_CFG_EPIO31 0x00000020 116 117 struct mac_addr { 118 u32 upper; 119 u32 lower; 120 }; 121 122 struct shared_hw_cfg { /* NVRAM Offset */ 123 /* Up to 16 bytes of NULL-terminated string */ 124 u8 part_num[16]; /* 0x104 */ 125 126 u32 config; /* 0x114 */ 127 #define SHARED_HW_CFG_MDIO_VOLTAGE_MASK 0x00000001 128 #define SHARED_HW_CFG_MDIO_VOLTAGE_SHIFT 0 129 #define SHARED_HW_CFG_MDIO_VOLTAGE_1_2V 0x00000000 130 #define SHARED_HW_CFG_MDIO_VOLTAGE_2_5V 0x00000001 131 #define SHARED_HW_CFG_MCP_RST_ON_CORE_RST_EN 0x00000002 132 133 #define SHARED_HW_CFG_PORT_SWAP 0x00000004 134 135 #define SHARED_HW_CFG_BEACON_WOL_EN 0x00000008 136 137 #define SHARED_HW_CFG_PCIE_GEN3_DISABLED 0x00000000 138 #define SHARED_HW_CFG_PCIE_GEN3_ENABLED 0x00000010 139 140 #define SHARED_HW_CFG_MFW_SELECT_MASK 0x00000700 141 #define SHARED_HW_CFG_MFW_SELECT_SHIFT 8 142 /* Whatever MFW found in NVM 143 (if multiple found, priority order is: NC-SI, UMP, IPMI) */ 144 #define SHARED_HW_CFG_MFW_SELECT_DEFAULT 0x00000000 145 #define SHARED_HW_CFG_MFW_SELECT_NC_SI 0x00000100 146 #define SHARED_HW_CFG_MFW_SELECT_UMP 0x00000200 147 #define SHARED_HW_CFG_MFW_SELECT_IPMI 0x00000300 148 /* Use SPIO4 as an arbiter between: 0-NC_SI, 1-IPMI 149 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */ 150 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_IPMI 0x00000400 151 /* Use SPIO4 as an arbiter between: 0-UMP, 1-IPMI 152 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */ 153 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_UMP_IPMI 0x00000500 154 /* Use SPIO4 as an arbiter between: 0-NC-SI, 1-UMP 155 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */ 156 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_UMP 0x00000600 157 158 #define SHARED_HW_CFG_LED_MODE_MASK 0x000f0000 159 #define SHARED_HW_CFG_LED_MODE_SHIFT 16 160 #define SHARED_HW_CFG_LED_MAC1 0x00000000 161 #define SHARED_HW_CFG_LED_PHY1 0x00010000 162 #define SHARED_HW_CFG_LED_PHY2 0x00020000 163 #define SHARED_HW_CFG_LED_PHY3 0x00030000 164 #define SHARED_HW_CFG_LED_MAC2 0x00040000 165 #define SHARED_HW_CFG_LED_PHY4 0x00050000 166 #define SHARED_HW_CFG_LED_PHY5 0x00060000 167 #define SHARED_HW_CFG_LED_PHY6 0x00070000 168 #define SHARED_HW_CFG_LED_MAC3 0x00080000 169 #define SHARED_HW_CFG_LED_PHY7 0x00090000 170 #define SHARED_HW_CFG_LED_PHY9 0x000a0000 171 #define SHARED_HW_CFG_LED_PHY11 0x000b0000 172 #define SHARED_HW_CFG_LED_MAC4 0x000c0000 173 #define SHARED_HW_CFG_LED_PHY8 0x000d0000 174 #define SHARED_HW_CFG_LED_EXTPHY1 0x000e0000 175 #define SHARED_HW_CFG_LED_EXTPHY2 0x000f0000 176 177 178 #define SHARED_HW_CFG_AN_ENABLE_MASK 0x3f000000 179 #define SHARED_HW_CFG_AN_ENABLE_SHIFT 24 180 #define SHARED_HW_CFG_AN_ENABLE_CL37 0x01000000 181 #define SHARED_HW_CFG_AN_ENABLE_CL73 0x02000000 182 #define SHARED_HW_CFG_AN_ENABLE_BAM 0x04000000 183 #define SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION 0x08000000 184 #define SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT 0x10000000 185 #define SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY 0x20000000 186 187 #define SHARED_HW_CFG_SRIOV_MASK 0x40000000 188 #define SHARED_HW_CFG_SRIOV_DISABLED 0x00000000 189 #define SHARED_HW_CFG_SRIOV_ENABLED 0x40000000 190 191 #define SHARED_HW_CFG_ATC_MASK 0x80000000 192 #define SHARED_HW_CFG_ATC_DISABLED 0x00000000 193 #define SHARED_HW_CFG_ATC_ENABLED 0x80000000 194 195 u32 config2; /* 0x118 */ 196 /* one time auto detect grace period (in sec) */ 197 #define SHARED_HW_CFG_GRACE_PERIOD_MASK 0x000000ff 198 #define SHARED_HW_CFG_GRACE_PERIOD_SHIFT 0 199 200 #define SHARED_HW_CFG_PCIE_GEN2_ENABLED 0x00000100 201 #define SHARED_HW_CFG_PCIE_GEN2_DISABLED 0x00000000 202 203 /* The default value for the core clock is 250MHz and it is 204 achieved by setting the clock change to 4 */ 205 #define SHARED_HW_CFG_CLOCK_CHANGE_MASK 0x00000e00 206 #define SHARED_HW_CFG_CLOCK_CHANGE_SHIFT 9 207 208 #define SHARED_HW_CFG_SMBUS_TIMING_MASK 0x00001000 209 #define SHARED_HW_CFG_SMBUS_TIMING_100KHZ 0x00000000 210 #define SHARED_HW_CFG_SMBUS_TIMING_400KHZ 0x00001000 211 212 #define SHARED_HW_CFG_HIDE_PORT1 0x00002000 213 214 #define SHARED_HW_CFG_WOL_CAPABLE_MASK 0x00004000 215 #define SHARED_HW_CFG_WOL_CAPABLE_DISABLED 0x00000000 216 #define SHARED_HW_CFG_WOL_CAPABLE_ENABLED 0x00004000 217 218 /* Output low when PERST is asserted */ 219 #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_MASK 0x00008000 220 #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_DISABLED 0x00000000 221 #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_ENABLED 0x00008000 222 223 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_MASK 0x00070000 224 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_SHIFT 16 225 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_HW 0x00000000 226 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_0DB 0x00010000 227 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_3_5DB 0x00020000 228 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_6_0DB 0x00030000 229 230 /* The fan failure mechanism is usually related to the PHY type 231 since the power consumption of the board is determined by the PHY. 232 Currently, fan is required for most designs with SFX7101, BCM8727 233 and BCM8481. If a fan is not required for a board which uses one 234 of those PHYs, this field should be set to "Disabled". If a fan is 235 required for a different PHY type, this option should be set to 236 "Enabled". The fan failure indication is expected on SPIO5 */ 237 #define SHARED_HW_CFG_FAN_FAILURE_MASK 0x00180000 238 #define SHARED_HW_CFG_FAN_FAILURE_SHIFT 19 239 #define SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE 0x00000000 240 #define SHARED_HW_CFG_FAN_FAILURE_DISABLED 0x00080000 241 #define SHARED_HW_CFG_FAN_FAILURE_ENABLED 0x00100000 242 243 /* ASPM Power Management support */ 244 #define SHARED_HW_CFG_ASPM_SUPPORT_MASK 0x00600000 245 #define SHARED_HW_CFG_ASPM_SUPPORT_SHIFT 21 246 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_ENABLED 0x00000000 247 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_DISABLED 0x00200000 248 #define SHARED_HW_CFG_ASPM_SUPPORT_L1_DISABLED 0x00400000 249 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_DISABLED 0x00600000 250 251 /* The value of PM_TL_IGNORE_REQS (bit0) in PCI register 252 tl_control_0 (register 0x2800) */ 253 #define SHARED_HW_CFG_PREVENT_L1_ENTRY_MASK 0x00800000 254 #define SHARED_HW_CFG_PREVENT_L1_ENTRY_DISABLED 0x00000000 255 #define SHARED_HW_CFG_PREVENT_L1_ENTRY_ENABLED 0x00800000 256 257 #define SHARED_HW_CFG_PORT_MODE_MASK 0x01000000 258 #define SHARED_HW_CFG_PORT_MODE_2 0x00000000 259 #define SHARED_HW_CFG_PORT_MODE_4 0x01000000 260 261 #define SHARED_HW_CFG_PATH_SWAP_MASK 0x02000000 262 #define SHARED_HW_CFG_PATH_SWAP_DISABLED 0x00000000 263 #define SHARED_HW_CFG_PATH_SWAP_ENABLED 0x02000000 264 265 /* Set the MDC/MDIO access for the first external phy */ 266 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK 0x1C000000 267 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT 26 268 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE 0x00000000 269 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0 0x04000000 270 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1 0x08000000 271 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH 0x0c000000 272 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED 0x10000000 273 274 /* Set the MDC/MDIO access for the second external phy */ 275 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK 0xE0000000 276 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT 29 277 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_PHY_TYPE 0x00000000 278 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC0 0x20000000 279 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC1 0x40000000 280 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_BOTH 0x60000000 281 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SWAPPED 0x80000000 282 283 284 u32 power_dissipated; /* 0x11c */ 285 #define SHARED_HW_CFG_POWER_MGNT_SCALE_MASK 0x00ff0000 286 #define SHARED_HW_CFG_POWER_MGNT_SCALE_SHIFT 16 287 #define SHARED_HW_CFG_POWER_MGNT_UNKNOWN_SCALE 0x00000000 288 #define SHARED_HW_CFG_POWER_MGNT_DOT_1_WATT 0x00010000 289 #define SHARED_HW_CFG_POWER_MGNT_DOT_01_WATT 0x00020000 290 #define SHARED_HW_CFG_POWER_MGNT_DOT_001_WATT 0x00030000 291 292 #define SHARED_HW_CFG_POWER_DIS_CMN_MASK 0xff000000 293 #define SHARED_HW_CFG_POWER_DIS_CMN_SHIFT 24 294 295 u32 ump_nc_si_config; /* 0x120 */ 296 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MASK 0x00000003 297 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_SHIFT 0 298 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MAC 0x00000000 299 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_PHY 0x00000001 300 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MII 0x00000000 301 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_RMII 0x00000002 302 303 #define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_MASK 0x00000f00 304 #define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_SHIFT 8 305 306 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_MASK 0x00ff0000 307 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_SHIFT 16 308 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_NONE 0x00000000 309 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_BCM5221 0x00010000 310 311 u32 board; /* 0x124 */ 312 #define SHARED_HW_CFG_E3_I2C_MUX0_MASK 0x0000003F 313 #define SHARED_HW_CFG_E3_I2C_MUX0_SHIFT 0 314 #define SHARED_HW_CFG_E3_I2C_MUX1_MASK 0x00000FC0 315 #define SHARED_HW_CFG_E3_I2C_MUX1_SHIFT 6 316 /* Use the PIN_CFG_XXX defines on top */ 317 #define SHARED_HW_CFG_BOARD_REV_MASK 0x00ff0000 318 #define SHARED_HW_CFG_BOARD_REV_SHIFT 16 319 320 #define SHARED_HW_CFG_BOARD_MAJOR_VER_MASK 0x0f000000 321 #define SHARED_HW_CFG_BOARD_MAJOR_VER_SHIFT 24 322 323 #define SHARED_HW_CFG_BOARD_MINOR_VER_MASK 0xf0000000 324 #define SHARED_HW_CFG_BOARD_MINOR_VER_SHIFT 28 325 326 u32 wc_lane_config; /* 0x128 */ 327 #define SHARED_HW_CFG_LANE_SWAP_CFG_MASK 0x0000FFFF 328 #define SHARED_HW_CFG_LANE_SWAP_CFG_SHIFT 0 329 #define SHARED_HW_CFG_LANE_SWAP_CFG_32103210 0x00001b1b 330 #define SHARED_HW_CFG_LANE_SWAP_CFG_32100123 0x00001be4 331 #define SHARED_HW_CFG_LANE_SWAP_CFG_01233210 0x0000e41b 332 #define SHARED_HW_CFG_LANE_SWAP_CFG_01230123 0x0000e4e4 333 #define SHARED_HW_CFG_LANE_SWAP_CFG_TX_MASK 0x000000FF 334 #define SHARED_HW_CFG_LANE_SWAP_CFG_TX_SHIFT 0 335 #define SHARED_HW_CFG_LANE_SWAP_CFG_RX_MASK 0x0000FF00 336 #define SHARED_HW_CFG_LANE_SWAP_CFG_RX_SHIFT 8 337 338 /* TX lane Polarity swap */ 339 #define SHARED_HW_CFG_TX_LANE0_POL_FLIP_ENABLED 0x00010000 340 #define SHARED_HW_CFG_TX_LANE1_POL_FLIP_ENABLED 0x00020000 341 #define SHARED_HW_CFG_TX_LANE2_POL_FLIP_ENABLED 0x00040000 342 #define SHARED_HW_CFG_TX_LANE3_POL_FLIP_ENABLED 0x00080000 343 /* TX lane Polarity swap */ 344 #define SHARED_HW_CFG_RX_LANE0_POL_FLIP_ENABLED 0x00100000 345 #define SHARED_HW_CFG_RX_LANE1_POL_FLIP_ENABLED 0x00200000 346 #define SHARED_HW_CFG_RX_LANE2_POL_FLIP_ENABLED 0x00400000 347 #define SHARED_HW_CFG_RX_LANE3_POL_FLIP_ENABLED 0x00800000 348 349 /* Selects the port layout of the board */ 350 #define SHARED_HW_CFG_E3_PORT_LAYOUT_MASK 0x0F000000 351 #define SHARED_HW_CFG_E3_PORT_LAYOUT_SHIFT 24 352 #define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_01 0x00000000 353 #define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_10 0x01000000 354 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_0123 0x02000000 355 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_1032 0x03000000 356 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_2301 0x04000000 357 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_3210 0x05000000 358 }; 359 360 361 /**************************************************************************** 362 * Port HW configuration * 363 ****************************************************************************/ 364 struct port_hw_cfg { /* port 0: 0x12c port 1: 0x2bc */ 365 366 u32 pci_id; 367 #define PORT_HW_CFG_PCI_VENDOR_ID_MASK 0xffff0000 368 #define PORT_HW_CFG_PCI_DEVICE_ID_MASK 0x0000ffff 369 370 u32 pci_sub_id; 371 #define PORT_HW_CFG_PCI_SUBSYS_DEVICE_ID_MASK 0xffff0000 372 #define PORT_HW_CFG_PCI_SUBSYS_VENDOR_ID_MASK 0x0000ffff 373 374 u32 power_dissipated; 375 #define PORT_HW_CFG_POWER_DIS_D0_MASK 0x000000ff 376 #define PORT_HW_CFG_POWER_DIS_D0_SHIFT 0 377 #define PORT_HW_CFG_POWER_DIS_D1_MASK 0x0000ff00 378 #define PORT_HW_CFG_POWER_DIS_D1_SHIFT 8 379 #define PORT_HW_CFG_POWER_DIS_D2_MASK 0x00ff0000 380 #define PORT_HW_CFG_POWER_DIS_D2_SHIFT 16 381 #define PORT_HW_CFG_POWER_DIS_D3_MASK 0xff000000 382 #define PORT_HW_CFG_POWER_DIS_D3_SHIFT 24 383 384 u32 power_consumed; 385 #define PORT_HW_CFG_POWER_CONS_D0_MASK 0x000000ff 386 #define PORT_HW_CFG_POWER_CONS_D0_SHIFT 0 387 #define PORT_HW_CFG_POWER_CONS_D1_MASK 0x0000ff00 388 #define PORT_HW_CFG_POWER_CONS_D1_SHIFT 8 389 #define PORT_HW_CFG_POWER_CONS_D2_MASK 0x00ff0000 390 #define PORT_HW_CFG_POWER_CONS_D2_SHIFT 16 391 #define PORT_HW_CFG_POWER_CONS_D3_MASK 0xff000000 392 #define PORT_HW_CFG_POWER_CONS_D3_SHIFT 24 393 394 u32 mac_upper; 395 #define PORT_HW_CFG_UPPERMAC_MASK 0x0000ffff 396 #define PORT_HW_CFG_UPPERMAC_SHIFT 0 397 u32 mac_lower; 398 399 u32 iscsi_mac_upper; /* Upper 16 bits are always zeroes */ 400 u32 iscsi_mac_lower; 401 402 u32 rdma_mac_upper; /* Upper 16 bits are always zeroes */ 403 u32 rdma_mac_lower; 404 405 u32 serdes_config; 406 #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_MASK 0x0000ffff 407 #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_SHIFT 0 408 409 #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK 0xffff0000 410 #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT 16 411 412 413 /* Default values: 2P-64, 4P-32 */ 414 u32 pf_config; /* 0x158 */ 415 #define PORT_HW_CFG_PF_NUM_VF_MASK 0x0000007F 416 #define PORT_HW_CFG_PF_NUM_VF_SHIFT 0 417 418 /* Default values: 17 */ 419 #define PORT_HW_CFG_PF_NUM_MSIX_VECTORS_MASK 0x00007F00 420 #define PORT_HW_CFG_PF_NUM_MSIX_VECTORS_SHIFT 8 421 422 #define PORT_HW_CFG_ENABLE_FLR_MASK 0x00010000 423 #define PORT_HW_CFG_FLR_ENABLED 0x00010000 424 425 u32 vf_config; /* 0x15C */ 426 #define PORT_HW_CFG_VF_NUM_MSIX_VECTORS_MASK 0x0000007F 427 #define PORT_HW_CFG_VF_NUM_MSIX_VECTORS_SHIFT 0 428 429 #define PORT_HW_CFG_VF_PCI_DEVICE_ID_MASK 0xFFFF0000 430 #define PORT_HW_CFG_VF_PCI_DEVICE_ID_SHIFT 16 431 432 u32 mf_pci_id; /* 0x160 */ 433 #define PORT_HW_CFG_MF_PCI_DEVICE_ID_MASK 0x0000FFFF 434 #define PORT_HW_CFG_MF_PCI_DEVICE_ID_SHIFT 0 435 436 /* Controls the TX laser of the SFP+ module */ 437 u32 sfp_ctrl; /* 0x164 */ 438 #define PORT_HW_CFG_TX_LASER_MASK 0x000000FF 439 #define PORT_HW_CFG_TX_LASER_SHIFT 0 440 #define PORT_HW_CFG_TX_LASER_MDIO 0x00000000 441 #define PORT_HW_CFG_TX_LASER_GPIO0 0x00000001 442 #define PORT_HW_CFG_TX_LASER_GPIO1 0x00000002 443 #define PORT_HW_CFG_TX_LASER_GPIO2 0x00000003 444 #define PORT_HW_CFG_TX_LASER_GPIO3 0x00000004 445 446 /* Controls the fault module LED of the SFP+ */ 447 #define PORT_HW_CFG_FAULT_MODULE_LED_MASK 0x0000FF00 448 #define PORT_HW_CFG_FAULT_MODULE_LED_SHIFT 8 449 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO0 0x00000000 450 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO1 0x00000100 451 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO2 0x00000200 452 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO3 0x00000300 453 #define PORT_HW_CFG_FAULT_MODULE_LED_DISABLED 0x00000400 454 455 /* The output pin TX_DIS that controls the TX laser of the SFP+ 456 module. Use the PIN_CFG_XXX defines on top */ 457 u32 e3_sfp_ctrl; /* 0x168 */ 458 #define PORT_HW_CFG_E3_TX_LASER_MASK 0x000000FF 459 #define PORT_HW_CFG_E3_TX_LASER_SHIFT 0 460 461 /* The output pin for SFPP_TYPE which turns on the Fault module LED */ 462 #define PORT_HW_CFG_E3_FAULT_MDL_LED_MASK 0x0000FF00 463 #define PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT 8 464 465 /* The input pin MOD_ABS that indicates whether SFP+ module is 466 present or not. Use the PIN_CFG_XXX defines on top */ 467 #define PORT_HW_CFG_E3_MOD_ABS_MASK 0x00FF0000 468 #define PORT_HW_CFG_E3_MOD_ABS_SHIFT 16 469 470 /* The output pin PWRDIS_SFP_X which disable the power of the SFP+ 471 module. Use the PIN_CFG_XXX defines on top */ 472 #define PORT_HW_CFG_E3_PWR_DIS_MASK 0xFF000000 473 #define PORT_HW_CFG_E3_PWR_DIS_SHIFT 24 474 475 /* 476 * The input pin which signals module transmit fault. Use the 477 * PIN_CFG_XXX defines on top 478 */ 479 u32 e3_cmn_pin_cfg; /* 0x16C */ 480 #define PORT_HW_CFG_E3_TX_FAULT_MASK 0x000000FF 481 #define PORT_HW_CFG_E3_TX_FAULT_SHIFT 0 482 483 /* The output pin which reset the PHY. Use the PIN_CFG_XXX defines on 484 top */ 485 #define PORT_HW_CFG_E3_PHY_RESET_MASK 0x0000FF00 486 #define PORT_HW_CFG_E3_PHY_RESET_SHIFT 8 487 488 /* 489 * The output pin which powers down the PHY. Use the PIN_CFG_XXX 490 * defines on top 491 */ 492 #define PORT_HW_CFG_E3_PWR_DOWN_MASK 0x00FF0000 493 #define PORT_HW_CFG_E3_PWR_DOWN_SHIFT 16 494 495 /* The output pin values BSC_SEL which selects the I2C for this port 496 in the I2C Mux */ 497 #define PORT_HW_CFG_E3_I2C_MUX0_MASK 0x01000000 498 #define PORT_HW_CFG_E3_I2C_MUX1_MASK 0x02000000 499 500 501 /* 502 * The input pin I_FAULT which indicate over-current has occurred. 503 * Use the PIN_CFG_XXX defines on top 504 */ 505 u32 e3_cmn_pin_cfg1; /* 0x170 */ 506 #define PORT_HW_CFG_E3_OVER_CURRENT_MASK 0x000000FF 507 #define PORT_HW_CFG_E3_OVER_CURRENT_SHIFT 0 508 509 /* pause on host ring */ 510 u32 generic_features; /* 0x174 */ 511 #define PORT_HW_CFG_PAUSE_ON_HOST_RING_MASK 0x00000001 512 #define PORT_HW_CFG_PAUSE_ON_HOST_RING_SHIFT 0 513 #define PORT_HW_CFG_PAUSE_ON_HOST_RING_DISABLED 0x00000000 514 #define PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED 0x00000001 515 516 /* SFP+ Tx Equalization: NIC recommended and tested value is 0xBEB2 517 * LOM recommended and tested value is 0xBEB2. Using a different 518 * value means using a value not tested by BRCM 519 */ 520 u32 sfi_tap_values; /* 0x178 */ 521 #define PORT_HW_CFG_TX_EQUALIZATION_MASK 0x0000FFFF 522 #define PORT_HW_CFG_TX_EQUALIZATION_SHIFT 0 523 524 /* SFP+ Tx driver broadcast IDRIVER: NIC recommended and tested 525 * value is 0x2. LOM recommended and tested value is 0x2. Using a 526 * different value means using a value not tested by BRCM 527 */ 528 #define PORT_HW_CFG_TX_DRV_BROADCAST_MASK 0x000F0000 529 #define PORT_HW_CFG_TX_DRV_BROADCAST_SHIFT 16 530 531 u32 reserved0[5]; /* 0x17c */ 532 533 u32 aeu_int_mask; /* 0x190 */ 534 535 u32 media_type; /* 0x194 */ 536 #define PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK 0x000000FF 537 #define PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT 0 538 539 #define PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK 0x0000FF00 540 #define PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT 8 541 542 #define PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK 0x00FF0000 543 #define PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT 16 544 545 /* 4 times 16 bits for all 4 lanes. In case external PHY is present 546 (not direct mode), those values will not take effect on the 4 XGXS 547 lanes. For some external PHYs (such as 8706 and 8726) the values 548 will be used to configure the external PHY in those cases, not 549 all 4 values are needed. */ 550 u16 xgxs_config_rx[4]; /* 0x198 */ 551 u16 xgxs_config_tx[4]; /* 0x1A0 */ 552 553 /* For storing FCOE mac on shared memory */ 554 u32 fcoe_fip_mac_upper; 555 #define PORT_HW_CFG_FCOE_UPPERMAC_MASK 0x0000ffff 556 #define PORT_HW_CFG_FCOE_UPPERMAC_SHIFT 0 557 u32 fcoe_fip_mac_lower; 558 559 u32 fcoe_wwn_port_name_upper; 560 u32 fcoe_wwn_port_name_lower; 561 562 u32 fcoe_wwn_node_name_upper; 563 u32 fcoe_wwn_node_name_lower; 564 565 u32 Reserved1[49]; /* 0x1C0 */ 566 567 /* Enable RJ45 magjack pair swapping on 10GBase-T PHY (0=default), 568 84833 only */ 569 u32 xgbt_phy_cfg; /* 0x284 */ 570 #define PORT_HW_CFG_RJ45_PAIR_SWAP_MASK 0x000000FF 571 #define PORT_HW_CFG_RJ45_PAIR_SWAP_SHIFT 0 572 573 u32 default_cfg; /* 0x288 */ 574 #define PORT_HW_CFG_GPIO0_CONFIG_MASK 0x00000003 575 #define PORT_HW_CFG_GPIO0_CONFIG_SHIFT 0 576 #define PORT_HW_CFG_GPIO0_CONFIG_NA 0x00000000 577 #define PORT_HW_CFG_GPIO0_CONFIG_LOW 0x00000001 578 #define PORT_HW_CFG_GPIO0_CONFIG_HIGH 0x00000002 579 #define PORT_HW_CFG_GPIO0_CONFIG_INPUT 0x00000003 580 581 #define PORT_HW_CFG_GPIO1_CONFIG_MASK 0x0000000C 582 #define PORT_HW_CFG_GPIO1_CONFIG_SHIFT 2 583 #define PORT_HW_CFG_GPIO1_CONFIG_NA 0x00000000 584 #define PORT_HW_CFG_GPIO1_CONFIG_LOW 0x00000004 585 #define PORT_HW_CFG_GPIO1_CONFIG_HIGH 0x00000008 586 #define PORT_HW_CFG_GPIO1_CONFIG_INPUT 0x0000000c 587 588 #define PORT_HW_CFG_GPIO2_CONFIG_MASK 0x00000030 589 #define PORT_HW_CFG_GPIO2_CONFIG_SHIFT 4 590 #define PORT_HW_CFG_GPIO2_CONFIG_NA 0x00000000 591 #define PORT_HW_CFG_GPIO2_CONFIG_LOW 0x00000010 592 #define PORT_HW_CFG_GPIO2_CONFIG_HIGH 0x00000020 593 #define PORT_HW_CFG_GPIO2_CONFIG_INPUT 0x00000030 594 595 #define PORT_HW_CFG_GPIO3_CONFIG_MASK 0x000000C0 596 #define PORT_HW_CFG_GPIO3_CONFIG_SHIFT 6 597 #define PORT_HW_CFG_GPIO3_CONFIG_NA 0x00000000 598 #define PORT_HW_CFG_GPIO3_CONFIG_LOW 0x00000040 599 #define PORT_HW_CFG_GPIO3_CONFIG_HIGH 0x00000080 600 #define PORT_HW_CFG_GPIO3_CONFIG_INPUT 0x000000c0 601 602 /* When KR link is required to be set to force which is not 603 KR-compliant, this parameter determine what is the trigger for it. 604 When GPIO is selected, low input will force the speed. Currently 605 default speed is 1G. In the future, it may be widen to select the 606 forced speed in with another parameter. Note when force-1G is 607 enabled, it override option 56: Link Speed option. */ 608 #define PORT_HW_CFG_FORCE_KR_ENABLER_MASK 0x00000F00 609 #define PORT_HW_CFG_FORCE_KR_ENABLER_SHIFT 8 610 #define PORT_HW_CFG_FORCE_KR_ENABLER_NOT_FORCED 0x00000000 611 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P0 0x00000100 612 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P0 0x00000200 613 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P0 0x00000300 614 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P0 0x00000400 615 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P1 0x00000500 616 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P1 0x00000600 617 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P1 0x00000700 618 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P1 0x00000800 619 #define PORT_HW_CFG_FORCE_KR_ENABLER_FORCED 0x00000900 620 /* Enable to determine with which GPIO to reset the external phy */ 621 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK 0x000F0000 622 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT 16 623 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_PHY_TYPE 0x00000000 624 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0 0x00010000 625 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0 0x00020000 626 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0 0x00030000 627 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0 0x00040000 628 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1 0x00050000 629 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1 0x00060000 630 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1 0x00070000 631 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1 0x00080000 632 633 /* Enable BAM on KR */ 634 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_MASK 0x00100000 635 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_SHIFT 20 636 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_DISABLED 0x00000000 637 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED 0x00100000 638 639 /* Enable Common Mode Sense */ 640 #define PORT_HW_CFG_ENABLE_CMS_MASK 0x00200000 641 #define PORT_HW_CFG_ENABLE_CMS_SHIFT 21 642 #define PORT_HW_CFG_ENABLE_CMS_DISABLED 0x00000000 643 #define PORT_HW_CFG_ENABLE_CMS_ENABLED 0x00200000 644 645 /* Determine the Serdes electrical interface */ 646 #define PORT_HW_CFG_NET_SERDES_IF_MASK 0x0F000000 647 #define PORT_HW_CFG_NET_SERDES_IF_SHIFT 24 648 #define PORT_HW_CFG_NET_SERDES_IF_SGMII 0x00000000 649 #define PORT_HW_CFG_NET_SERDES_IF_XFI 0x01000000 650 #define PORT_HW_CFG_NET_SERDES_IF_SFI 0x02000000 651 #define PORT_HW_CFG_NET_SERDES_IF_KR 0x03000000 652 #define PORT_HW_CFG_NET_SERDES_IF_DXGXS 0x04000000 653 #define PORT_HW_CFG_NET_SERDES_IF_KR2 0x05000000 654 655 656 u32 speed_capability_mask2; /* 0x28C */ 657 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_MASK 0x0000FFFF 658 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_SHIFT 0 659 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10M_FULL 0x00000001 660 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3__ 0x00000002 661 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3___ 0x00000004 662 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_100M_FULL 0x00000008 663 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_1G 0x00000010 664 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_2_DOT_5G 0x00000020 665 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10G 0x00000040 666 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_20G 0x00000080 667 668 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_MASK 0xFFFF0000 669 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_SHIFT 16 670 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10M_FULL 0x00010000 671 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0__ 0x00020000 672 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0___ 0x00040000 673 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_100M_FULL 0x00080000 674 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_1G 0x00100000 675 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_2_DOT_5G 0x00200000 676 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10G 0x00400000 677 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_20G 0x00800000 678 679 680 /* In the case where two media types (e.g. copper and fiber) are 681 present and electrically active at the same time, PHY Selection 682 will determine which of the two PHYs will be designated as the 683 Active PHY and used for a connection to the network. */ 684 u32 multi_phy_config; /* 0x290 */ 685 #define PORT_HW_CFG_PHY_SELECTION_MASK 0x00000007 686 #define PORT_HW_CFG_PHY_SELECTION_SHIFT 0 687 #define PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT 0x00000000 688 #define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY 0x00000001 689 #define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY 0x00000002 690 #define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY 0x00000003 691 #define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY 0x00000004 692 693 /* When enabled, all second phy nvram parameters will be swapped 694 with the first phy parameters */ 695 #define PORT_HW_CFG_PHY_SWAPPED_MASK 0x00000008 696 #define PORT_HW_CFG_PHY_SWAPPED_SHIFT 3 697 #define PORT_HW_CFG_PHY_SWAPPED_DISABLED 0x00000000 698 #define PORT_HW_CFG_PHY_SWAPPED_ENABLED 0x00000008 699 700 701 /* Address of the second external phy */ 702 u32 external_phy_config2; /* 0x294 */ 703 #define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_MASK 0x000000FF 704 #define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_SHIFT 0 705 706 /* The second XGXS external PHY type */ 707 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_MASK 0x0000FF00 708 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SHIFT 8 709 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_DIRECT 0x00000000 710 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8071 0x00000100 711 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8072 0x00000200 712 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8073 0x00000300 713 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8705 0x00000400 714 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8706 0x00000500 715 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8726 0x00000600 716 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8481 0x00000700 717 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SFX7101 0x00000800 718 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727 0x00000900 719 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727_NOC 0x00000a00 720 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84823 0x00000b00 721 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54640 0x00000c00 722 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84833 0x00000d00 723 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54618SE 0x00000e00 724 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8722 0x00000f00 725 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54616 0x00001000 726 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84834 0x00001100 727 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_FAILURE 0x0000fd00 728 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_NOT_CONN 0x0000ff00 729 730 731 /* 4 times 16 bits for all 4 lanes. For some external PHYs (such as 732 8706, 8726 and 8727) not all 4 values are needed. */ 733 u16 xgxs_config2_rx[4]; /* 0x296 */ 734 u16 xgxs_config2_tx[4]; /* 0x2A0 */ 735 736 u32 lane_config; 737 #define PORT_HW_CFG_LANE_SWAP_CFG_MASK 0x0000ffff 738 #define PORT_HW_CFG_LANE_SWAP_CFG_SHIFT 0 739 /* AN and forced */ 740 #define PORT_HW_CFG_LANE_SWAP_CFG_01230123 0x00001b1b 741 /* forced only */ 742 #define PORT_HW_CFG_LANE_SWAP_CFG_01233210 0x00001be4 743 /* forced only */ 744 #define PORT_HW_CFG_LANE_SWAP_CFG_31203120 0x0000d8d8 745 /* forced only */ 746 #define PORT_HW_CFG_LANE_SWAP_CFG_32103210 0x0000e4e4 747 #define PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK 0x000000ff 748 #define PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT 0 749 #define PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK 0x0000ff00 750 #define PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT 8 751 #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK 0x0000c000 752 #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT 14 753 754 /* Indicate whether to swap the external phy polarity */ 755 #define PORT_HW_CFG_SWAP_PHY_POLARITY_MASK 0x00010000 756 #define PORT_HW_CFG_SWAP_PHY_POLARITY_DISABLED 0x00000000 757 #define PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED 0x00010000 758 759 760 u32 external_phy_config; 761 #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK 0x000000ff 762 #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT 0 763 764 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK 0x0000ff00 765 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SHIFT 8 766 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT 0x00000000 767 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8071 0x00000100 768 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072 0x00000200 769 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073 0x00000300 770 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705 0x00000400 771 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706 0x00000500 772 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726 0x00000600 773 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481 0x00000700 774 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101 0x00000800 775 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727 0x00000900 776 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC 0x00000a00 777 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823 0x00000b00 778 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54640 0x00000c00 779 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833 0x00000d00 780 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE 0x00000e00 781 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722 0x00000f00 782 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616 0x00001000 783 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834 0x00001100 784 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT_WC 0x0000fc00 785 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE 0x0000fd00 786 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN 0x0000ff00 787 788 #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK 0x00ff0000 789 #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_SHIFT 16 790 791 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK 0xff000000 792 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_SHIFT 24 793 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT 0x00000000 794 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482 0x01000000 795 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD 0x02000000 796 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN 0xff000000 797 798 u32 speed_capability_mask; 799 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_MASK 0x0000ffff 800 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_SHIFT 0 801 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_FULL 0x00000001 802 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_HALF 0x00000002 803 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_HALF 0x00000004 804 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_FULL 0x00000008 805 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_1G 0x00000010 806 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_2_5G 0x00000020 807 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10G 0x00000040 808 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_20G 0x00000080 809 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_RESERVED 0x0000f000 810 811 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK 0xffff0000 812 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_SHIFT 16 813 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL 0x00010000 814 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF 0x00020000 815 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF 0x00040000 816 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL 0x00080000 817 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_1G 0x00100000 818 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G 0x00200000 819 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10G 0x00400000 820 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_20G 0x00800000 821 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_RESERVED 0xf0000000 822 823 /* A place to hold the original MAC address as a backup */ 824 u32 backup_mac_upper; /* 0x2B4 */ 825 u32 backup_mac_lower; /* 0x2B8 */ 826 827 }; 828 829 830 /**************************************************************************** 831 * Shared Feature configuration * 832 ****************************************************************************/ 833 struct shared_feat_cfg { /* NVRAM Offset */ 834 835 u32 config; /* 0x450 */ 836 #define SHARED_FEATURE_BMC_ECHO_MODE_EN 0x00000001 837 838 /* Use NVRAM values instead of HW default values */ 839 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_MASK \ 840 0x00000002 841 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_DISABLED \ 842 0x00000000 843 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED \ 844 0x00000002 845 846 #define SHARED_FEAT_CFG_NCSI_ID_METHOD_MASK 0x00000008 847 #define SHARED_FEAT_CFG_NCSI_ID_METHOD_SPIO 0x00000000 848 #define SHARED_FEAT_CFG_NCSI_ID_METHOD_NVRAM 0x00000008 849 850 #define SHARED_FEAT_CFG_NCSI_ID_MASK 0x00000030 851 #define SHARED_FEAT_CFG_NCSI_ID_SHIFT 4 852 853 /* Override the OTP back to single function mode. When using GPIO, 854 high means only SF, 0 is according to CLP configuration */ 855 #define SHARED_FEAT_CFG_FORCE_SF_MODE_MASK 0x00000700 856 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SHIFT 8 857 #define SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED 0x00000000 858 #define SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF 0x00000100 859 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4 0x00000200 860 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT 0x00000300 861 #define SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE 0x00000400 862 863 /* The interval in seconds between sending LLDP packets. Set to zero 864 to disable the feature */ 865 #define SHARED_FEAT_CFG_LLDP_XMIT_INTERVAL_MASK 0x00ff0000 866 #define SHARED_FEAT_CFG_LLDP_XMIT_INTERVAL_SHIFT 16 867 868 /* The assigned device type ID for LLDP usage */ 869 #define SHARED_FEAT_CFG_LLDP_DEVICE_TYPE_ID_MASK 0xff000000 870 #define SHARED_FEAT_CFG_LLDP_DEVICE_TYPE_ID_SHIFT 24 871 872 }; 873 874 875 /**************************************************************************** 876 * Port Feature configuration * 877 ****************************************************************************/ 878 struct port_feat_cfg { /* port 0: 0x454 port 1: 0x4c8 */ 879 880 u32 config; 881 #define PORT_FEATURE_BAR1_SIZE_MASK 0x0000000f 882 #define PORT_FEATURE_BAR1_SIZE_SHIFT 0 883 #define PORT_FEATURE_BAR1_SIZE_DISABLED 0x00000000 884 #define PORT_FEATURE_BAR1_SIZE_64K 0x00000001 885 #define PORT_FEATURE_BAR1_SIZE_128K 0x00000002 886 #define PORT_FEATURE_BAR1_SIZE_256K 0x00000003 887 #define PORT_FEATURE_BAR1_SIZE_512K 0x00000004 888 #define PORT_FEATURE_BAR1_SIZE_1M 0x00000005 889 #define PORT_FEATURE_BAR1_SIZE_2M 0x00000006 890 #define PORT_FEATURE_BAR1_SIZE_4M 0x00000007 891 #define PORT_FEATURE_BAR1_SIZE_8M 0x00000008 892 #define PORT_FEATURE_BAR1_SIZE_16M 0x00000009 893 #define PORT_FEATURE_BAR1_SIZE_32M 0x0000000a 894 #define PORT_FEATURE_BAR1_SIZE_64M 0x0000000b 895 #define PORT_FEATURE_BAR1_SIZE_128M 0x0000000c 896 #define PORT_FEATURE_BAR1_SIZE_256M 0x0000000d 897 #define PORT_FEATURE_BAR1_SIZE_512M 0x0000000e 898 #define PORT_FEATURE_BAR1_SIZE_1G 0x0000000f 899 #define PORT_FEATURE_BAR2_SIZE_MASK 0x000000f0 900 #define PORT_FEATURE_BAR2_SIZE_SHIFT 4 901 #define PORT_FEATURE_BAR2_SIZE_DISABLED 0x00000000 902 #define PORT_FEATURE_BAR2_SIZE_64K 0x00000010 903 #define PORT_FEATURE_BAR2_SIZE_128K 0x00000020 904 #define PORT_FEATURE_BAR2_SIZE_256K 0x00000030 905 #define PORT_FEATURE_BAR2_SIZE_512K 0x00000040 906 #define PORT_FEATURE_BAR2_SIZE_1M 0x00000050 907 #define PORT_FEATURE_BAR2_SIZE_2M 0x00000060 908 #define PORT_FEATURE_BAR2_SIZE_4M 0x00000070 909 #define PORT_FEATURE_BAR2_SIZE_8M 0x00000080 910 #define PORT_FEATURE_BAR2_SIZE_16M 0x00000090 911 #define PORT_FEATURE_BAR2_SIZE_32M 0x000000a0 912 #define PORT_FEATURE_BAR2_SIZE_64M 0x000000b0 913 #define PORT_FEATURE_BAR2_SIZE_128M 0x000000c0 914 #define PORT_FEATURE_BAR2_SIZE_256M 0x000000d0 915 #define PORT_FEATURE_BAR2_SIZE_512M 0x000000e0 916 #define PORT_FEATURE_BAR2_SIZE_1G 0x000000f0 917 918 #define PORT_FEAT_CFG_DCBX_MASK 0x00000100 919 #define PORT_FEAT_CFG_DCBX_DISABLED 0x00000000 920 #define PORT_FEAT_CFG_DCBX_ENABLED 0x00000100 921 922 #define PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK 0x00000C00 923 #define PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE 0x00000400 924 #define PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI 0x00000800 925 926 #define PORT_FEATURE_EN_SIZE_MASK 0x0f000000 927 #define PORT_FEATURE_EN_SIZE_SHIFT 24 928 #define PORT_FEATURE_WOL_ENABLED 0x01000000 929 #define PORT_FEATURE_MBA_ENABLED 0x02000000 930 #define PORT_FEATURE_MFW_ENABLED 0x04000000 931 932 /* Advertise expansion ROM even if MBA is disabled */ 933 #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_MASK 0x08000000 934 #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_DISABLED 0x00000000 935 #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_ENABLED 0x08000000 936 937 /* Check the optic vendor via i2c against a list of approved modules 938 in a separate nvram image */ 939 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK 0xe0000000 940 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_SHIFT 29 941 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT \ 942 0x00000000 943 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER \ 944 0x20000000 945 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG 0x40000000 946 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN 0x60000000 947 948 u32 wol_config; 949 /* Default is used when driver sets to "auto" mode */ 950 #define PORT_FEATURE_WOL_DEFAULT_MASK 0x00000003 951 #define PORT_FEATURE_WOL_DEFAULT_SHIFT 0 952 #define PORT_FEATURE_WOL_DEFAULT_DISABLE 0x00000000 953 #define PORT_FEATURE_WOL_DEFAULT_MAGIC 0x00000001 954 #define PORT_FEATURE_WOL_DEFAULT_ACPI 0x00000002 955 #define PORT_FEATURE_WOL_DEFAULT_MAGIC_AND_ACPI 0x00000003 956 #define PORT_FEATURE_WOL_RES_PAUSE_CAP 0x00000004 957 #define PORT_FEATURE_WOL_RES_ASYM_PAUSE_CAP 0x00000008 958 #define PORT_FEATURE_WOL_ACPI_UPON_MGMT 0x00000010 959 960 u32 mba_config; 961 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK 0x00000007 962 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT 0 963 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE 0x00000000 964 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL 0x00000001 965 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP 0x00000002 966 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB 0x00000003 967 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT 0x00000004 968 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE 0x00000007 969 970 #define PORT_FEATURE_MBA_BOOT_RETRY_MASK 0x00000038 971 #define PORT_FEATURE_MBA_BOOT_RETRY_SHIFT 3 972 973 #define PORT_FEATURE_MBA_RES_PAUSE_CAP 0x00000100 974 #define PORT_FEATURE_MBA_RES_ASYM_PAUSE_CAP 0x00000200 975 #define PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE 0x00000400 976 #define PORT_FEATURE_MBA_HOTKEY_MASK 0x00000800 977 #define PORT_FEATURE_MBA_HOTKEY_CTRL_S 0x00000000 978 #define PORT_FEATURE_MBA_HOTKEY_CTRL_B 0x00000800 979 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK 0x000ff000 980 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT 12 981 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED 0x00000000 982 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2K 0x00001000 983 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4K 0x00002000 984 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8K 0x00003000 985 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16K 0x00004000 986 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32K 0x00005000 987 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_64K 0x00006000 988 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_128K 0x00007000 989 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_256K 0x00008000 990 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_512K 0x00009000 991 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_1M 0x0000a000 992 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2M 0x0000b000 993 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4M 0x0000c000 994 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8M 0x0000d000 995 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16M 0x0000e000 996 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32M 0x0000f000 997 #define PORT_FEATURE_MBA_MSG_TIMEOUT_MASK 0x00f00000 998 #define PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT 20 999 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK 0x03000000 1000 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT 24 1001 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO 0x00000000 1002 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS 0x01000000 1003 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H 0x02000000 1004 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H 0x03000000 1005 #define PORT_FEATURE_MBA_LINK_SPEED_MASK 0x3c000000 1006 #define PORT_FEATURE_MBA_LINK_SPEED_SHIFT 26 1007 #define PORT_FEATURE_MBA_LINK_SPEED_AUTO 0x00000000 1008 #define PORT_FEATURE_MBA_LINK_SPEED_10HD 0x04000000 1009 #define PORT_FEATURE_MBA_LINK_SPEED_10FD 0x08000000 1010 #define PORT_FEATURE_MBA_LINK_SPEED_100HD 0x0c000000 1011 #define PORT_FEATURE_MBA_LINK_SPEED_100FD 0x10000000 1012 #define PORT_FEATURE_MBA_LINK_SPEED_1GBPS 0x14000000 1013 #define PORT_FEATURE_MBA_LINK_SPEED_2_5GBPS 0x18000000 1014 #define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_CX4 0x1c000000 1015 #define PORT_FEATURE_MBA_LINK_SPEED_20GBPS 0x20000000 1016 u32 bmc_config; 1017 #define PORT_FEATURE_BMC_LINK_OVERRIDE_MASK 0x00000001 1018 #define PORT_FEATURE_BMC_LINK_OVERRIDE_DEFAULT 0x00000000 1019 #define PORT_FEATURE_BMC_LINK_OVERRIDE_EN 0x00000001 1020 1021 u32 mba_vlan_cfg; 1022 #define PORT_FEATURE_MBA_VLAN_TAG_MASK 0x0000ffff 1023 #define PORT_FEATURE_MBA_VLAN_TAG_SHIFT 0 1024 #define PORT_FEATURE_MBA_VLAN_EN 0x00010000 1025 1026 u32 resource_cfg; 1027 #define PORT_FEATURE_RESOURCE_CFG_VALID 0x00000001 1028 #define PORT_FEATURE_RESOURCE_CFG_DIAG 0x00000002 1029 #define PORT_FEATURE_RESOURCE_CFG_L2 0x00000004 1030 #define PORT_FEATURE_RESOURCE_CFG_ISCSI 0x00000008 1031 #define PORT_FEATURE_RESOURCE_CFG_RDMA 0x00000010 1032 1033 u32 smbus_config; 1034 #define PORT_FEATURE_SMBUS_ADDR_MASK 0x000000fe 1035 #define PORT_FEATURE_SMBUS_ADDR_SHIFT 1 1036 1037 u32 vf_config; 1038 #define PORT_FEAT_CFG_VF_BAR2_SIZE_MASK 0x0000000f 1039 #define PORT_FEAT_CFG_VF_BAR2_SIZE_SHIFT 0 1040 #define PORT_FEAT_CFG_VF_BAR2_SIZE_DISABLED 0x00000000 1041 #define PORT_FEAT_CFG_VF_BAR2_SIZE_4K 0x00000001 1042 #define PORT_FEAT_CFG_VF_BAR2_SIZE_8K 0x00000002 1043 #define PORT_FEAT_CFG_VF_BAR2_SIZE_16K 0x00000003 1044 #define PORT_FEAT_CFG_VF_BAR2_SIZE_32K 0x00000004 1045 #define PORT_FEAT_CFG_VF_BAR2_SIZE_64K 0x00000005 1046 #define PORT_FEAT_CFG_VF_BAR2_SIZE_128K 0x00000006 1047 #define PORT_FEAT_CFG_VF_BAR2_SIZE_256K 0x00000007 1048 #define PORT_FEAT_CFG_VF_BAR2_SIZE_512K 0x00000008 1049 #define PORT_FEAT_CFG_VF_BAR2_SIZE_1M 0x00000009 1050 #define PORT_FEAT_CFG_VF_BAR2_SIZE_2M 0x0000000a 1051 #define PORT_FEAT_CFG_VF_BAR2_SIZE_4M 0x0000000b 1052 #define PORT_FEAT_CFG_VF_BAR2_SIZE_8M 0x0000000c 1053 #define PORT_FEAT_CFG_VF_BAR2_SIZE_16M 0x0000000d 1054 #define PORT_FEAT_CFG_VF_BAR2_SIZE_32M 0x0000000e 1055 #define PORT_FEAT_CFG_VF_BAR2_SIZE_64M 0x0000000f 1056 1057 u32 link_config; /* Used as HW defaults for the driver */ 1058 #define PORT_FEATURE_CONNECTED_SWITCH_MASK 0x03000000 1059 #define PORT_FEATURE_CONNECTED_SWITCH_SHIFT 24 1060 /* (forced) low speed switch (< 10G) */ 1061 #define PORT_FEATURE_CON_SWITCH_1G_SWITCH 0x00000000 1062 /* (forced) high speed switch (>= 10G) */ 1063 #define PORT_FEATURE_CON_SWITCH_10G_SWITCH 0x01000000 1064 #define PORT_FEATURE_CON_SWITCH_AUTO_DETECT 0x02000000 1065 #define PORT_FEATURE_CON_SWITCH_ONE_TIME_DETECT 0x03000000 1066 1067 #define PORT_FEATURE_LINK_SPEED_MASK 0x000f0000 1068 #define PORT_FEATURE_LINK_SPEED_SHIFT 16 1069 #define PORT_FEATURE_LINK_SPEED_AUTO 0x00000000 1070 #define PORT_FEATURE_LINK_SPEED_10M_FULL 0x00010000 1071 #define PORT_FEATURE_LINK_SPEED_10M_HALF 0x00020000 1072 #define PORT_FEATURE_LINK_SPEED_100M_HALF 0x00030000 1073 #define PORT_FEATURE_LINK_SPEED_100M_FULL 0x00040000 1074 #define PORT_FEATURE_LINK_SPEED_1G 0x00050000 1075 #define PORT_FEATURE_LINK_SPEED_2_5G 0x00060000 1076 #define PORT_FEATURE_LINK_SPEED_10G_CX4 0x00070000 1077 #define PORT_FEATURE_LINK_SPEED_20G 0x00080000 1078 1079 #define PORT_FEATURE_FLOW_CONTROL_MASK 0x00000700 1080 #define PORT_FEATURE_FLOW_CONTROL_SHIFT 8 1081 #define PORT_FEATURE_FLOW_CONTROL_AUTO 0x00000000 1082 #define PORT_FEATURE_FLOW_CONTROL_TX 0x00000100 1083 #define PORT_FEATURE_FLOW_CONTROL_RX 0x00000200 1084 #define PORT_FEATURE_FLOW_CONTROL_BOTH 0x00000300 1085 #define PORT_FEATURE_FLOW_CONTROL_NONE 0x00000400 1086 1087 /* The default for MCP link configuration, 1088 uses the same defines as link_config */ 1089 u32 mfw_wol_link_cfg; 1090 1091 /* The default for the driver of the second external phy, 1092 uses the same defines as link_config */ 1093 u32 link_config2; /* 0x47C */ 1094 1095 /* The default for MCP of the second external phy, 1096 uses the same defines as link_config */ 1097 u32 mfw_wol_link_cfg2; /* 0x480 */ 1098 1099 1100 /* EEE power saving mode */ 1101 u32 eee_power_mode; /* 0x484 */ 1102 #define PORT_FEAT_CFG_EEE_POWER_MODE_MASK 0x000000FF 1103 #define PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT 0 1104 #define PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED 0x00000000 1105 #define PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED 0x00000001 1106 #define PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE 0x00000002 1107 #define PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY 0x00000003 1108 1109 1110 u32 Reserved2[16]; /* 0x488 */ 1111 }; 1112 1113 1114 /**************************************************************************** 1115 * Device Information * 1116 ****************************************************************************/ 1117 struct shm_dev_info { /* size */ 1118 1119 u32 bc_rev; /* 8 bits each: major, minor, build */ /* 4 */ 1120 1121 struct shared_hw_cfg shared_hw_config; /* 40 */ 1122 1123 struct port_hw_cfg port_hw_config[PORT_MAX]; /* 400*2=800 */ 1124 1125 struct shared_feat_cfg shared_feature_config; /* 4 */ 1126 1127 struct port_feat_cfg port_feature_config[PORT_MAX];/* 116*2=232 */ 1128 1129 }; 1130 1131 1132 #if !defined(__LITTLE_ENDIAN) && !defined(__BIG_ENDIAN) 1133 #error "Missing either LITTLE_ENDIAN or BIG_ENDIAN definition." 1134 #endif 1135 1136 #define FUNC_0 0 1137 #define FUNC_1 1 1138 #define FUNC_2 2 1139 #define FUNC_3 3 1140 #define FUNC_4 4 1141 #define FUNC_5 5 1142 #define FUNC_6 6 1143 #define FUNC_7 7 1144 #define E1_FUNC_MAX 2 1145 #define E1H_FUNC_MAX 8 1146 #define E2_FUNC_MAX 4 /* per path */ 1147 1148 #define VN_0 0 1149 #define VN_1 1 1150 #define VN_2 2 1151 #define VN_3 3 1152 #define E1VN_MAX 1 1153 #define E1HVN_MAX 4 1154 1155 #define E2_VF_MAX 64 /* HC_REG_VF_CONFIGURATION_SIZE */ 1156 /* This value (in milliseconds) determines the frequency of the driver 1157 * issuing the PULSE message code. The firmware monitors this periodic 1158 * pulse to determine when to switch to an OS-absent mode. */ 1159 #define DRV_PULSE_PERIOD_MS 250 1160 1161 /* This value (in milliseconds) determines how long the driver should 1162 * wait for an acknowledgement from the firmware before timing out. Once 1163 * the firmware has timed out, the driver will assume there is no firmware 1164 * running and there won't be any firmware-driver synchronization during a 1165 * driver reset. */ 1166 #define FW_ACK_TIME_OUT_MS 5000 1167 1168 #define FW_ACK_POLL_TIME_MS 1 1169 1170 #define FW_ACK_NUM_OF_POLL (FW_ACK_TIME_OUT_MS/FW_ACK_POLL_TIME_MS) 1171 1172 #define MFW_TRACE_SIGNATURE 0x54524342 1173 1174 /**************************************************************************** 1175 * Driver <-> FW Mailbox * 1176 ****************************************************************************/ 1177 struct drv_port_mb { 1178 1179 u32 link_status; 1180 /* Driver should update this field on any link change event */ 1181 1182 #define LINK_STATUS_NONE (0<<0) 1183 #define LINK_STATUS_LINK_FLAG_MASK 0x00000001 1184 #define LINK_STATUS_LINK_UP 0x00000001 1185 #define LINK_STATUS_SPEED_AND_DUPLEX_MASK 0x0000001E 1186 #define LINK_STATUS_SPEED_AND_DUPLEX_AN_NOT_COMPLETE (0<<1) 1187 #define LINK_STATUS_SPEED_AND_DUPLEX_10THD (1<<1) 1188 #define LINK_STATUS_SPEED_AND_DUPLEX_10TFD (2<<1) 1189 #define LINK_STATUS_SPEED_AND_DUPLEX_100TXHD (3<<1) 1190 #define LINK_STATUS_SPEED_AND_DUPLEX_100T4 (4<<1) 1191 #define LINK_STATUS_SPEED_AND_DUPLEX_100TXFD (5<<1) 1192 #define LINK_STATUS_SPEED_AND_DUPLEX_1000THD (6<<1) 1193 #define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD (7<<1) 1194 #define LINK_STATUS_SPEED_AND_DUPLEX_1000XFD (7<<1) 1195 #define LINK_STATUS_SPEED_AND_DUPLEX_2500THD (8<<1) 1196 #define LINK_STATUS_SPEED_AND_DUPLEX_2500TFD (9<<1) 1197 #define LINK_STATUS_SPEED_AND_DUPLEX_2500XFD (9<<1) 1198 #define LINK_STATUS_SPEED_AND_DUPLEX_10GTFD (10<<1) 1199 #define LINK_STATUS_SPEED_AND_DUPLEX_10GXFD (10<<1) 1200 #define LINK_STATUS_SPEED_AND_DUPLEX_20GTFD (11<<1) 1201 #define LINK_STATUS_SPEED_AND_DUPLEX_20GXFD (11<<1) 1202 1203 #define LINK_STATUS_AUTO_NEGOTIATE_FLAG_MASK 0x00000020 1204 #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED 0x00000020 1205 1206 #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE 0x00000040 1207 #define LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK 0x00000080 1208 #define LINK_STATUS_PARALLEL_DETECTION_USED 0x00000080 1209 1210 #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200 1211 #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400 1212 #define LINK_STATUS_LINK_PARTNER_100T4_CAPABLE 0x00000800 1213 #define LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE 0x00001000 1214 #define LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE 0x00002000 1215 #define LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE 0x00004000 1216 #define LINK_STATUS_LINK_PARTNER_10THD_CAPABLE 0x00008000 1217 1218 #define LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK 0x00010000 1219 #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED 0x00010000 1220 1221 #define LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK 0x00020000 1222 #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED 0x00020000 1223 1224 #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK 0x000C0000 1225 #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE (0<<18) 1226 #define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE (1<<18) 1227 #define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE (2<<18) 1228 #define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE (3<<18) 1229 1230 #define LINK_STATUS_SERDES_LINK 0x00100000 1231 1232 #define LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE 0x00200000 1233 #define LINK_STATUS_LINK_PARTNER_2500XHD_CAPABLE 0x00400000 1234 #define LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE 0x00800000 1235 #define LINK_STATUS_LINK_PARTNER_20GXFD_CAPABLE 0x10000000 1236 1237 #define LINK_STATUS_PFC_ENABLED 0x20000000 1238 1239 #define LINK_STATUS_PHYSICAL_LINK_FLAG 0x40000000 1240 #define LINK_STATUS_SFP_TX_FAULT 0x80000000 1241 1242 u32 port_stx; 1243 1244 u32 stat_nig_timer; 1245 1246 /* MCP firmware does not use this field */ 1247 u32 ext_phy_fw_version; 1248 1249 }; 1250 1251 1252 struct drv_func_mb { 1253 1254 u32 drv_mb_header; 1255 #define DRV_MSG_CODE_MASK 0xffff0000 1256 #define DRV_MSG_CODE_LOAD_REQ 0x10000000 1257 #define DRV_MSG_CODE_LOAD_DONE 0x11000000 1258 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_EN 0x20000000 1259 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS 0x20010000 1260 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP 0x20020000 1261 #define DRV_MSG_CODE_UNLOAD_DONE 0x21000000 1262 #define DRV_MSG_CODE_DCC_OK 0x30000000 1263 #define DRV_MSG_CODE_DCC_FAILURE 0x31000000 1264 #define DRV_MSG_CODE_DIAG_ENTER_REQ 0x50000000 1265 #define DRV_MSG_CODE_DIAG_EXIT_REQ 0x60000000 1266 #define DRV_MSG_CODE_VALIDATE_KEY 0x70000000 1267 #define DRV_MSG_CODE_GET_CURR_KEY 0x80000000 1268 #define DRV_MSG_CODE_GET_UPGRADE_KEY 0x81000000 1269 #define DRV_MSG_CODE_GET_MANUF_KEY 0x82000000 1270 #define DRV_MSG_CODE_LOAD_L2B_PRAM 0x90000000 1271 /* 1272 * The optic module verification command requires bootcode 1273 * v5.0.6 or later, te specific optic module verification command 1274 * requires bootcode v5.2.12 or later 1275 */ 1276 #define DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL 0xa0000000 1277 #define REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL 0x00050006 1278 #define DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL 0xa1000000 1279 #define REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL 0x00050234 1280 #define DRV_MSG_CODE_VRFY_AFEX_SUPPORTED 0xa2000000 1281 #define REQ_BC_VER_4_VRFY_AFEX_SUPPORTED 0x00070002 1282 #define REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED 0x00070014 1283 #define REQ_BC_VER_4_MT_SUPPORTED 0x00070201 1284 #define REQ_BC_VER_4_PFC_STATS_SUPPORTED 0x00070201 1285 #define REQ_BC_VER_4_FCOE_FEATURES 0x00070209 1286 1287 #define DRV_MSG_CODE_DCBX_ADMIN_PMF_MSG 0xb0000000 1288 #define DRV_MSG_CODE_DCBX_PMF_DRV_OK 0xb2000000 1289 #define REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF 0x00070401 1290 1291 #define DRV_MSG_CODE_VF_DISABLED_DONE 0xc0000000 1292 1293 #define DRV_MSG_CODE_AFEX_DRIVER_SETMAC 0xd0000000 1294 #define DRV_MSG_CODE_AFEX_LISTGET_ACK 0xd1000000 1295 #define DRV_MSG_CODE_AFEX_LISTSET_ACK 0xd2000000 1296 #define DRV_MSG_CODE_AFEX_STATSGET_ACK 0xd3000000 1297 #define DRV_MSG_CODE_AFEX_VIFSET_ACK 0xd4000000 1298 1299 #define DRV_MSG_CODE_DRV_INFO_ACK 0xd8000000 1300 #define DRV_MSG_CODE_DRV_INFO_NACK 0xd9000000 1301 1302 #define DRV_MSG_CODE_EEE_RESULTS_ACK 0xda000000 1303 1304 #define DRV_MSG_CODE_RMMOD 0xdb000000 1305 #define REQ_BC_VER_4_RMMOD_CMD 0x0007080f 1306 1307 #define DRV_MSG_CODE_SET_MF_BW 0xe0000000 1308 #define REQ_BC_VER_4_SET_MF_BW 0x00060202 1309 #define DRV_MSG_CODE_SET_MF_BW_ACK 0xe1000000 1310 1311 #define DRV_MSG_CODE_LINK_STATUS_CHANGED 0x01000000 1312 1313 #define DRV_MSG_CODE_INITIATE_FLR 0x02000000 1314 #define REQ_BC_VER_4_INITIATE_FLR 0x00070213 1315 1316 #define BIOS_MSG_CODE_LIC_CHALLENGE 0xff010000 1317 #define BIOS_MSG_CODE_LIC_RESPONSE 0xff020000 1318 #define BIOS_MSG_CODE_VIRT_MAC_PRIM 0xff030000 1319 #define BIOS_MSG_CODE_VIRT_MAC_ISCSI 0xff040000 1320 1321 #define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff 1322 1323 u32 drv_mb_param; 1324 #define DRV_MSG_CODE_SET_MF_BW_MIN_MASK 0x00ff0000 1325 #define DRV_MSG_CODE_SET_MF_BW_MAX_MASK 0xff000000 1326 1327 #define DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET 0x00000002 1328 1329 #define DRV_MSG_CODE_LOAD_REQ_WITH_LFA 0x0000100a 1330 #define DRV_MSG_CODE_LOAD_REQ_FORCE_LFA 0x00002000 1331 1332 u32 fw_mb_header; 1333 #define FW_MSG_CODE_MASK 0xffff0000 1334 #define FW_MSG_CODE_DRV_LOAD_COMMON 0x10100000 1335 #define FW_MSG_CODE_DRV_LOAD_PORT 0x10110000 1336 #define FW_MSG_CODE_DRV_LOAD_FUNCTION 0x10120000 1337 /* Load common chip is supported from bc 6.0.0 */ 1338 #define REQ_BC_VER_4_DRV_LOAD_COMMON_CHIP 0x00060000 1339 #define FW_MSG_CODE_DRV_LOAD_COMMON_CHIP 0x10130000 1340 1341 #define FW_MSG_CODE_DRV_LOAD_REFUSED 0x10200000 1342 #define FW_MSG_CODE_DRV_LOAD_DONE 0x11100000 1343 #define FW_MSG_CODE_DRV_UNLOAD_COMMON 0x20100000 1344 #define FW_MSG_CODE_DRV_UNLOAD_PORT 0x20110000 1345 #define FW_MSG_CODE_DRV_UNLOAD_FUNCTION 0x20120000 1346 #define FW_MSG_CODE_DRV_UNLOAD_DONE 0x21100000 1347 #define FW_MSG_CODE_DCC_DONE 0x30100000 1348 #define FW_MSG_CODE_LLDP_DONE 0x40100000 1349 #define FW_MSG_CODE_DIAG_ENTER_DONE 0x50100000 1350 #define FW_MSG_CODE_DIAG_REFUSE 0x50200000 1351 #define FW_MSG_CODE_DIAG_EXIT_DONE 0x60100000 1352 #define FW_MSG_CODE_VALIDATE_KEY_SUCCESS 0x70100000 1353 #define FW_MSG_CODE_VALIDATE_KEY_FAILURE 0x70200000 1354 #define FW_MSG_CODE_GET_KEY_DONE 0x80100000 1355 #define FW_MSG_CODE_NO_KEY 0x80f00000 1356 #define FW_MSG_CODE_LIC_INFO_NOT_READY 0x80f80000 1357 #define FW_MSG_CODE_L2B_PRAM_LOADED 0x90100000 1358 #define FW_MSG_CODE_L2B_PRAM_T_LOAD_FAILURE 0x90210000 1359 #define FW_MSG_CODE_L2B_PRAM_C_LOAD_FAILURE 0x90220000 1360 #define FW_MSG_CODE_L2B_PRAM_X_LOAD_FAILURE 0x90230000 1361 #define FW_MSG_CODE_L2B_PRAM_U_LOAD_FAILURE 0x90240000 1362 #define FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS 0xa0100000 1363 #define FW_MSG_CODE_VRFY_OPT_MDL_INVLD_IMG 0xa0200000 1364 #define FW_MSG_CODE_VRFY_OPT_MDL_UNAPPROVED 0xa0300000 1365 #define FW_MSG_CODE_VF_DISABLED_DONE 0xb0000000 1366 #define FW_MSG_CODE_HW_SET_INVALID_IMAGE 0xb0100000 1367 1368 #define FW_MSG_CODE_AFEX_DRIVER_SETMAC_DONE 0xd0100000 1369 #define FW_MSG_CODE_AFEX_LISTGET_ACK 0xd1100000 1370 #define FW_MSG_CODE_AFEX_LISTSET_ACK 0xd2100000 1371 #define FW_MSG_CODE_AFEX_STATSGET_ACK 0xd3100000 1372 #define FW_MSG_CODE_AFEX_VIFSET_ACK 0xd4100000 1373 1374 #define FW_MSG_CODE_DRV_INFO_ACK 0xd8100000 1375 #define FW_MSG_CODE_DRV_INFO_NACK 0xd9100000 1376 1377 #define FW_MSG_CODE_EEE_RESULS_ACK 0xda100000 1378 1379 #define FW_MSG_CODE_RMMOD_ACK 0xdb100000 1380 1381 #define FW_MSG_CODE_SET_MF_BW_SENT 0xe0000000 1382 #define FW_MSG_CODE_SET_MF_BW_DONE 0xe1000000 1383 1384 #define FW_MSG_CODE_LINK_CHANGED_ACK 0x01100000 1385 1386 #define FW_MSG_CODE_LIC_CHALLENGE 0xff010000 1387 #define FW_MSG_CODE_LIC_RESPONSE 0xff020000 1388 #define FW_MSG_CODE_VIRT_MAC_PRIM 0xff030000 1389 #define FW_MSG_CODE_VIRT_MAC_ISCSI 0xff040000 1390 1391 #define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff 1392 1393 u32 fw_mb_param; 1394 1395 u32 drv_pulse_mb; 1396 #define DRV_PULSE_SEQ_MASK 0x00007fff 1397 #define DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000 1398 /* 1399 * The system time is in the format of 1400 * (year-2001)*12*32 + month*32 + day. 1401 */ 1402 #define DRV_PULSE_ALWAYS_ALIVE 0x00008000 1403 /* 1404 * Indicate to the firmware not to go into the 1405 * OS-absent when it is not getting driver pulse. 1406 * This is used for debugging as well for PXE(MBA). 1407 */ 1408 1409 u32 mcp_pulse_mb; 1410 #define MCP_PULSE_SEQ_MASK 0x00007fff 1411 #define MCP_PULSE_ALWAYS_ALIVE 0x00008000 1412 /* Indicates to the driver not to assert due to lack 1413 * of MCP response */ 1414 #define MCP_EVENT_MASK 0xffff0000 1415 #define MCP_EVENT_OTHER_DRIVER_RESET_REQ 0x00010000 1416 1417 u32 iscsi_boot_signature; 1418 u32 iscsi_boot_block_offset; 1419 1420 u32 drv_status; 1421 #define DRV_STATUS_PMF 0x00000001 1422 #define DRV_STATUS_VF_DISABLED 0x00000002 1423 #define DRV_STATUS_SET_MF_BW 0x00000004 1424 #define DRV_STATUS_LINK_EVENT 0x00000008 1425 1426 #define DRV_STATUS_DCC_EVENT_MASK 0x0000ff00 1427 #define DRV_STATUS_DCC_DISABLE_ENABLE_PF 0x00000100 1428 #define DRV_STATUS_DCC_BANDWIDTH_ALLOCATION 0x00000200 1429 #define DRV_STATUS_DCC_CHANGE_MAC_ADDRESS 0x00000400 1430 #define DRV_STATUS_DCC_RESERVED1 0x00000800 1431 #define DRV_STATUS_DCC_SET_PROTOCOL 0x00001000 1432 #define DRV_STATUS_DCC_SET_PRIORITY 0x00002000 1433 1434 #define DRV_STATUS_DCBX_EVENT_MASK 0x000f0000 1435 #define DRV_STATUS_DCBX_NEGOTIATION_RESULTS 0x00010000 1436 #define DRV_STATUS_AFEX_EVENT_MASK 0x03f00000 1437 #define DRV_STATUS_AFEX_LISTGET_REQ 0x00100000 1438 #define DRV_STATUS_AFEX_LISTSET_REQ 0x00200000 1439 #define DRV_STATUS_AFEX_STATSGET_REQ 0x00400000 1440 #define DRV_STATUS_AFEX_VIFSET_REQ 0x00800000 1441 1442 #define DRV_STATUS_DRV_INFO_REQ 0x04000000 1443 1444 #define DRV_STATUS_EEE_NEGOTIATION_RESULTS 0x08000000 1445 1446 u32 virt_mac_upper; 1447 #define VIRT_MAC_SIGN_MASK 0xffff0000 1448 #define VIRT_MAC_SIGNATURE 0x564d0000 1449 u32 virt_mac_lower; 1450 1451 }; 1452 1453 1454 /**************************************************************************** 1455 * Management firmware state * 1456 ****************************************************************************/ 1457 /* Allocate 440 bytes for management firmware */ 1458 #define MGMTFW_STATE_WORD_SIZE 110 1459 1460 struct mgmtfw_state { 1461 u32 opaque[MGMTFW_STATE_WORD_SIZE]; 1462 }; 1463 1464 1465 /**************************************************************************** 1466 * Multi-Function configuration * 1467 ****************************************************************************/ 1468 struct shared_mf_cfg { 1469 1470 u32 clp_mb; 1471 #define SHARED_MF_CLP_SET_DEFAULT 0x00000000 1472 /* set by CLP */ 1473 #define SHARED_MF_CLP_EXIT 0x00000001 1474 /* set by MCP */ 1475 #define SHARED_MF_CLP_EXIT_DONE 0x00010000 1476 1477 }; 1478 1479 struct port_mf_cfg { 1480 1481 u32 dynamic_cfg; /* device control channel */ 1482 #define PORT_MF_CFG_E1HOV_TAG_MASK 0x0000ffff 1483 #define PORT_MF_CFG_E1HOV_TAG_SHIFT 0 1484 #define PORT_MF_CFG_E1HOV_TAG_DEFAULT PORT_MF_CFG_E1HOV_TAG_MASK 1485 1486 u32 reserved[1]; 1487 1488 }; 1489 1490 struct func_mf_cfg { 1491 1492 u32 config; 1493 /* E/R/I/D */ 1494 /* function 0 of each port cannot be hidden */ 1495 #define FUNC_MF_CFG_FUNC_HIDE 0x00000001 1496 1497 #define FUNC_MF_CFG_PROTOCOL_MASK 0x00000006 1498 #define FUNC_MF_CFG_PROTOCOL_FCOE 0x00000000 1499 #define FUNC_MF_CFG_PROTOCOL_ETHERNET 0x00000002 1500 #define FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA 0x00000004 1501 #define FUNC_MF_CFG_PROTOCOL_ISCSI 0x00000006 1502 #define FUNC_MF_CFG_PROTOCOL_DEFAULT \ 1503 FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA 1504 1505 #define FUNC_MF_CFG_FUNC_DISABLED 0x00000008 1506 #define FUNC_MF_CFG_FUNC_DELETED 0x00000010 1507 1508 /* PRI */ 1509 /* 0 - low priority, 3 - high priority */ 1510 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK 0x00000300 1511 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT 8 1512 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_DEFAULT 0x00000000 1513 1514 /* MINBW, MAXBW */ 1515 /* value range - 0..100, increments in 100Mbps */ 1516 #define FUNC_MF_CFG_MIN_BW_MASK 0x00ff0000 1517 #define FUNC_MF_CFG_MIN_BW_SHIFT 16 1518 #define FUNC_MF_CFG_MIN_BW_DEFAULT 0x00000000 1519 #define FUNC_MF_CFG_MAX_BW_MASK 0xff000000 1520 #define FUNC_MF_CFG_MAX_BW_SHIFT 24 1521 #define FUNC_MF_CFG_MAX_BW_DEFAULT 0x64000000 1522 1523 u32 mac_upper; /* MAC */ 1524 #define FUNC_MF_CFG_UPPERMAC_MASK 0x0000ffff 1525 #define FUNC_MF_CFG_UPPERMAC_SHIFT 0 1526 #define FUNC_MF_CFG_UPPERMAC_DEFAULT FUNC_MF_CFG_UPPERMAC_MASK 1527 u32 mac_lower; 1528 #define FUNC_MF_CFG_LOWERMAC_DEFAULT 0xffffffff 1529 1530 u32 e1hov_tag; /* VNI */ 1531 #define FUNC_MF_CFG_E1HOV_TAG_MASK 0x0000ffff 1532 #define FUNC_MF_CFG_E1HOV_TAG_SHIFT 0 1533 #define FUNC_MF_CFG_E1HOV_TAG_DEFAULT FUNC_MF_CFG_E1HOV_TAG_MASK 1534 1535 /* afex default VLAN ID - 12 bits */ 1536 #define FUNC_MF_CFG_AFEX_VLAN_MASK 0x0fff0000 1537 #define FUNC_MF_CFG_AFEX_VLAN_SHIFT 16 1538 1539 u32 afex_config; 1540 #define FUNC_MF_CFG_AFEX_COS_FILTER_MASK 0x000000ff 1541 #define FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT 0 1542 #define FUNC_MF_CFG_AFEX_MBA_ENABLED_MASK 0x0000ff00 1543 #define FUNC_MF_CFG_AFEX_MBA_ENABLED_SHIFT 8 1544 #define FUNC_MF_CFG_AFEX_MBA_ENABLED_VAL 0x00000100 1545 #define FUNC_MF_CFG_AFEX_VLAN_MODE_MASK 0x000f0000 1546 #define FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT 16 1547 1548 u32 reserved; 1549 }; 1550 1551 enum mf_cfg_afex_vlan_mode { 1552 FUNC_MF_CFG_AFEX_VLAN_TRUNK_MODE = 0, 1553 FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE, 1554 FUNC_MF_CFG_AFEX_VLAN_TRUNK_TAG_NATIVE_MODE 1555 }; 1556 1557 /* This structure is not applicable and should not be accessed on 57711 */ 1558 struct func_ext_cfg { 1559 u32 func_cfg; 1560 #define MACP_FUNC_CFG_FLAGS_MASK 0x0000007F 1561 #define MACP_FUNC_CFG_FLAGS_SHIFT 0 1562 #define MACP_FUNC_CFG_FLAGS_ENABLED 0x00000001 1563 #define MACP_FUNC_CFG_FLAGS_ETHERNET 0x00000002 1564 #define MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD 0x00000004 1565 #define MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD 0x00000008 1566 #define MACP_FUNC_CFG_PAUSE_ON_HOST_RING 0x00000080 1567 1568 u32 iscsi_mac_addr_upper; 1569 u32 iscsi_mac_addr_lower; 1570 1571 u32 fcoe_mac_addr_upper; 1572 u32 fcoe_mac_addr_lower; 1573 1574 u32 fcoe_wwn_port_name_upper; 1575 u32 fcoe_wwn_port_name_lower; 1576 1577 u32 fcoe_wwn_node_name_upper; 1578 u32 fcoe_wwn_node_name_lower; 1579 1580 u32 preserve_data; 1581 #define MF_FUNC_CFG_PRESERVE_L2_MAC (1<<0) 1582 #define MF_FUNC_CFG_PRESERVE_ISCSI_MAC (1<<1) 1583 #define MF_FUNC_CFG_PRESERVE_FCOE_MAC (1<<2) 1584 #define MF_FUNC_CFG_PRESERVE_FCOE_WWN_P (1<<3) 1585 #define MF_FUNC_CFG_PRESERVE_FCOE_WWN_N (1<<4) 1586 #define MF_FUNC_CFG_PRESERVE_TX_BW (1<<5) 1587 }; 1588 1589 struct mf_cfg { 1590 1591 struct shared_mf_cfg shared_mf_config; /* 0x4 */ 1592 /* 0x8*2*2=0x20 */ 1593 struct port_mf_cfg port_mf_config[NVM_PATH_MAX][PORT_MAX]; 1594 /* for all chips, there are 8 mf functions */ 1595 struct func_mf_cfg func_mf_config[E1H_FUNC_MAX]; /* 0x18 * 8 = 0xc0 */ 1596 /* 1597 * Extended configuration per function - this array does not exist and 1598 * should not be accessed on 57711 1599 */ 1600 struct func_ext_cfg func_ext_config[E1H_FUNC_MAX]; /* 0x28 * 8 = 0x140*/ 1601 }; /* 0x224 */ 1602 1603 /**************************************************************************** 1604 * Shared Memory Region * 1605 ****************************************************************************/ 1606 struct shmem_region { /* SharedMem Offset (size) */ 1607 1608 u32 validity_map[PORT_MAX]; /* 0x0 (4*2 = 0x8) */ 1609 #define SHR_MEM_FORMAT_REV_MASK 0xff000000 1610 #define SHR_MEM_FORMAT_REV_ID ('A'<<24) 1611 /* validity bits */ 1612 #define SHR_MEM_VALIDITY_PCI_CFG 0x00100000 1613 #define SHR_MEM_VALIDITY_MB 0x00200000 1614 #define SHR_MEM_VALIDITY_DEV_INFO 0x00400000 1615 #define SHR_MEM_VALIDITY_RESERVED 0x00000007 1616 /* One licensing bit should be set */ 1617 #define SHR_MEM_VALIDITY_LIC_KEY_IN_EFFECT_MASK 0x00000038 1618 #define SHR_MEM_VALIDITY_LIC_MANUF_KEY_IN_EFFECT 0x00000008 1619 #define SHR_MEM_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT 0x00000010 1620 #define SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT 0x00000020 1621 /* Active MFW */ 1622 #define SHR_MEM_VALIDITY_ACTIVE_MFW_UNKNOWN 0x00000000 1623 #define SHR_MEM_VALIDITY_ACTIVE_MFW_MASK 0x000001c0 1624 #define SHR_MEM_VALIDITY_ACTIVE_MFW_IPMI 0x00000040 1625 #define SHR_MEM_VALIDITY_ACTIVE_MFW_UMP 0x00000080 1626 #define SHR_MEM_VALIDITY_ACTIVE_MFW_NCSI 0x000000c0 1627 #define SHR_MEM_VALIDITY_ACTIVE_MFW_NONE 0x000001c0 1628 1629 struct shm_dev_info dev_info; /* 0x8 (0x438) */ 1630 1631 struct license_key drv_lic_key[PORT_MAX]; /* 0x440 (52*2=0x68) */ 1632 1633 /* FW information (for internal FW use) */ 1634 u32 fw_info_fio_offset; /* 0x4a8 (0x4) */ 1635 struct mgmtfw_state mgmtfw_state; /* 0x4ac (0x1b8) */ 1636 1637 struct drv_port_mb port_mb[PORT_MAX]; /* 0x664 (16*2=0x20) */ 1638 1639 #ifdef BMAPI 1640 /* This is a variable length array */ 1641 /* the number of function depends on the chip type */ 1642 struct drv_func_mb func_mb[1]; /* 0x684 (44*2/4/8=0x58/0xb0/0x160) */ 1643 #else 1644 /* the number of function depends on the chip type */ 1645 struct drv_func_mb func_mb[]; /* 0x684 (44*2/4/8=0x58/0xb0/0x160) */ 1646 #endif /* BMAPI */ 1647 1648 }; /* 57710 = 0x6dc | 57711 = 0x7E4 | 57712 = 0x734 */ 1649 1650 /**************************************************************************** 1651 * Shared Memory 2 Region * 1652 ****************************************************************************/ 1653 /* The fw_flr_ack is actually built in the following way: */ 1654 /* 8 bit: PF ack */ 1655 /* 64 bit: VF ack */ 1656 /* 8 bit: ios_dis_ack */ 1657 /* In order to maintain endianity in the mailbox hsi, we want to keep using */ 1658 /* u32. The fw must have the VF right after the PF since this is how it */ 1659 /* access arrays(it expects always the VF to reside after the PF, and that */ 1660 /* makes the calculation much easier for it. ) */ 1661 /* In order to answer both limitations, and keep the struct small, the code */ 1662 /* will abuse the structure defined here to achieve the actual partition */ 1663 /* above */ 1664 /****************************************************************************/ 1665 struct fw_flr_ack { 1666 u32 pf_ack; 1667 u32 vf_ack[1]; 1668 u32 iov_dis_ack; 1669 }; 1670 1671 struct fw_flr_mb { 1672 u32 aggint; 1673 u32 opgen_addr; 1674 struct fw_flr_ack ack; 1675 }; 1676 1677 struct eee_remote_vals { 1678 u32 tx_tw; 1679 u32 rx_tw; 1680 }; 1681 1682 /**** SUPPORT FOR SHMEM ARRRAYS *** 1683 * The SHMEM HSI is aligned on 32 bit boundaries which makes it difficult to 1684 * define arrays with storage types smaller then unsigned dwords. 1685 * The macros below add generic support for SHMEM arrays with numeric elements 1686 * that can span 2,4,8 or 16 bits. The array underlying type is a 32 bit dword 1687 * array with individual bit-filed elements accessed using shifts and masks. 1688 * 1689 */ 1690 1691 /* eb is the bitwidth of a single element */ 1692 #define SHMEM_ARRAY_MASK(eb) ((1<<(eb))-1) 1693 #define SHMEM_ARRAY_ENTRY(i, eb) ((i)/(32/(eb))) 1694 1695 /* the bit-position macro allows the used to flip the order of the arrays 1696 * elements on a per byte or word boundary. 1697 * 1698 * example: an array with 8 entries each 4 bit wide. This array will fit into 1699 * a single dword. The diagrmas below show the array order of the nibbles. 1700 * 1701 * SHMEM_ARRAY_BITPOS(i, 4, 4) defines the stadard ordering: 1702 * 1703 * | | | | 1704 * 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 1705 * | | | | 1706 * 1707 * SHMEM_ARRAY_BITPOS(i, 4, 8) defines a flip ordering per byte: 1708 * 1709 * | | | | 1710 * 1 | 0 | 3 | 2 | 5 | 4 | 7 | 6 | 1711 * | | | | 1712 * 1713 * SHMEM_ARRAY_BITPOS(i, 4, 16) defines a flip ordering per word: 1714 * 1715 * | | | | 1716 * 3 | 2 | 1 | 0 | 7 | 6 | 5 | 4 | 1717 * | | | | 1718 */ 1719 #define SHMEM_ARRAY_BITPOS(i, eb, fb) \ 1720 ((((32/(fb)) - 1 - ((i)/((fb)/(eb))) % (32/(fb))) * (fb)) + \ 1721 (((i)%((fb)/(eb))) * (eb))) 1722 1723 #define SHMEM_ARRAY_GET(a, i, eb, fb) \ 1724 ((a[SHMEM_ARRAY_ENTRY(i, eb)] >> SHMEM_ARRAY_BITPOS(i, eb, fb)) & \ 1725 SHMEM_ARRAY_MASK(eb)) 1726 1727 #define SHMEM_ARRAY_SET(a, i, eb, fb, val) \ 1728 do { \ 1729 a[SHMEM_ARRAY_ENTRY(i, eb)] &= ~(SHMEM_ARRAY_MASK(eb) << \ 1730 SHMEM_ARRAY_BITPOS(i, eb, fb)); \ 1731 a[SHMEM_ARRAY_ENTRY(i, eb)] |= (((val) & SHMEM_ARRAY_MASK(eb)) << \ 1732 SHMEM_ARRAY_BITPOS(i, eb, fb)); \ 1733 } while (0) 1734 1735 1736 /****START OF DCBX STRUCTURES DECLARATIONS****/ 1737 #define DCBX_MAX_NUM_PRI_PG_ENTRIES 8 1738 #define DCBX_PRI_PG_BITWIDTH 4 1739 #define DCBX_PRI_PG_FBITS 8 1740 #define DCBX_PRI_PG_GET(a, i) \ 1741 SHMEM_ARRAY_GET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS) 1742 #define DCBX_PRI_PG_SET(a, i, val) \ 1743 SHMEM_ARRAY_SET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS, val) 1744 #define DCBX_MAX_NUM_PG_BW_ENTRIES 8 1745 #define DCBX_BW_PG_BITWIDTH 8 1746 #define DCBX_PG_BW_GET(a, i) \ 1747 SHMEM_ARRAY_GET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH) 1748 #define DCBX_PG_BW_SET(a, i, val) \ 1749 SHMEM_ARRAY_SET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH, val) 1750 #define DCBX_STRICT_PRI_PG 15 1751 #define DCBX_MAX_APP_PROTOCOL 16 1752 #define FCOE_APP_IDX 0 1753 #define ISCSI_APP_IDX 1 1754 #define PREDEFINED_APP_IDX_MAX 2 1755 1756 1757 /* Big/Little endian have the same representation. */ 1758 struct dcbx_ets_feature { 1759 /* 1760 * For Admin MIB - is this feature supported by the 1761 * driver | For Local MIB - should this feature be enabled. 1762 */ 1763 u32 enabled; 1764 u32 pg_bw_tbl[2]; 1765 u32 pri_pg_tbl[1]; 1766 }; 1767 1768 /* Driver structure in LE */ 1769 struct dcbx_pfc_feature { 1770 #ifdef __BIG_ENDIAN 1771 u8 pri_en_bitmap; 1772 #define DCBX_PFC_PRI_0 0x01 1773 #define DCBX_PFC_PRI_1 0x02 1774 #define DCBX_PFC_PRI_2 0x04 1775 #define DCBX_PFC_PRI_3 0x08 1776 #define DCBX_PFC_PRI_4 0x10 1777 #define DCBX_PFC_PRI_5 0x20 1778 #define DCBX_PFC_PRI_6 0x40 1779 #define DCBX_PFC_PRI_7 0x80 1780 u8 pfc_caps; 1781 u8 reserved; 1782 u8 enabled; 1783 #elif defined(__LITTLE_ENDIAN) 1784 u8 enabled; 1785 u8 reserved; 1786 u8 pfc_caps; 1787 u8 pri_en_bitmap; 1788 #define DCBX_PFC_PRI_0 0x01 1789 #define DCBX_PFC_PRI_1 0x02 1790 #define DCBX_PFC_PRI_2 0x04 1791 #define DCBX_PFC_PRI_3 0x08 1792 #define DCBX_PFC_PRI_4 0x10 1793 #define DCBX_PFC_PRI_5 0x20 1794 #define DCBX_PFC_PRI_6 0x40 1795 #define DCBX_PFC_PRI_7 0x80 1796 #endif 1797 }; 1798 1799 struct dcbx_app_priority_entry { 1800 #ifdef __BIG_ENDIAN 1801 u16 app_id; 1802 u8 pri_bitmap; 1803 u8 appBitfield; 1804 #define DCBX_APP_ENTRY_VALID 0x01 1805 #define DCBX_APP_ENTRY_SF_MASK 0x30 1806 #define DCBX_APP_ENTRY_SF_SHIFT 4 1807 #define DCBX_APP_SF_ETH_TYPE 0x10 1808 #define DCBX_APP_SF_PORT 0x20 1809 #elif defined(__LITTLE_ENDIAN) 1810 u8 appBitfield; 1811 #define DCBX_APP_ENTRY_VALID 0x01 1812 #define DCBX_APP_ENTRY_SF_MASK 0x30 1813 #define DCBX_APP_ENTRY_SF_SHIFT 4 1814 #define DCBX_APP_SF_ETH_TYPE 0x10 1815 #define DCBX_APP_SF_PORT 0x20 1816 u8 pri_bitmap; 1817 u16 app_id; 1818 #endif 1819 }; 1820 1821 1822 /* FW structure in BE */ 1823 struct dcbx_app_priority_feature { 1824 #ifdef __BIG_ENDIAN 1825 u8 reserved; 1826 u8 default_pri; 1827 u8 tc_supported; 1828 u8 enabled; 1829 #elif defined(__LITTLE_ENDIAN) 1830 u8 enabled; 1831 u8 tc_supported; 1832 u8 default_pri; 1833 u8 reserved; 1834 #endif 1835 struct dcbx_app_priority_entry app_pri_tbl[DCBX_MAX_APP_PROTOCOL]; 1836 }; 1837 1838 /* FW structure in BE */ 1839 struct dcbx_features { 1840 /* PG feature */ 1841 struct dcbx_ets_feature ets; 1842 /* PFC feature */ 1843 struct dcbx_pfc_feature pfc; 1844 /* APP feature */ 1845 struct dcbx_app_priority_feature app; 1846 }; 1847 1848 /* LLDP protocol parameters */ 1849 /* FW structure in BE */ 1850 struct lldp_params { 1851 #ifdef __BIG_ENDIAN 1852 u8 msg_fast_tx_interval; 1853 u8 msg_tx_hold; 1854 u8 msg_tx_interval; 1855 u8 admin_status; 1856 #define LLDP_TX_ONLY 0x01 1857 #define LLDP_RX_ONLY 0x02 1858 #define LLDP_TX_RX 0x03 1859 #define LLDP_DISABLED 0x04 1860 u8 reserved1; 1861 u8 tx_fast; 1862 u8 tx_crd_max; 1863 u8 tx_crd; 1864 #elif defined(__LITTLE_ENDIAN) 1865 u8 admin_status; 1866 #define LLDP_TX_ONLY 0x01 1867 #define LLDP_RX_ONLY 0x02 1868 #define LLDP_TX_RX 0x03 1869 #define LLDP_DISABLED 0x04 1870 u8 msg_tx_interval; 1871 u8 msg_tx_hold; 1872 u8 msg_fast_tx_interval; 1873 u8 tx_crd; 1874 u8 tx_crd_max; 1875 u8 tx_fast; 1876 u8 reserved1; 1877 #endif 1878 #define REM_CHASSIS_ID_STAT_LEN 4 1879 #define REM_PORT_ID_STAT_LEN 4 1880 /* Holds remote Chassis ID TLV header, subtype and 9B of payload. */ 1881 u32 peer_chassis_id[REM_CHASSIS_ID_STAT_LEN]; 1882 /* Holds remote Port ID TLV header, subtype and 9B of payload. */ 1883 u32 peer_port_id[REM_PORT_ID_STAT_LEN]; 1884 }; 1885 1886 struct lldp_dcbx_stat { 1887 #define LOCAL_CHASSIS_ID_STAT_LEN 2 1888 #define LOCAL_PORT_ID_STAT_LEN 2 1889 /* Holds local Chassis ID 8B payload of constant subtype 4. */ 1890 u32 local_chassis_id[LOCAL_CHASSIS_ID_STAT_LEN]; 1891 /* Holds local Port ID 8B payload of constant subtype 3. */ 1892 u32 local_port_id[LOCAL_PORT_ID_STAT_LEN]; 1893 /* Number of DCBX frames transmitted. */ 1894 u32 num_tx_dcbx_pkts; 1895 /* Number of DCBX frames received. */ 1896 u32 num_rx_dcbx_pkts; 1897 }; 1898 1899 /* ADMIN MIB - DCBX local machine default configuration. */ 1900 struct lldp_admin_mib { 1901 u32 ver_cfg_flags; 1902 #define DCBX_ETS_CONFIG_TX_ENABLED 0x00000001 1903 #define DCBX_PFC_CONFIG_TX_ENABLED 0x00000002 1904 #define DCBX_APP_CONFIG_TX_ENABLED 0x00000004 1905 #define DCBX_ETS_RECO_TX_ENABLED 0x00000008 1906 #define DCBX_ETS_RECO_VALID 0x00000010 1907 #define DCBX_ETS_WILLING 0x00000020 1908 #define DCBX_PFC_WILLING 0x00000040 1909 #define DCBX_APP_WILLING 0x00000080 1910 #define DCBX_VERSION_CEE 0x00000100 1911 #define DCBX_VERSION_IEEE 0x00000200 1912 #define DCBX_DCBX_ENABLED 0x00000400 1913 #define DCBX_CEE_VERSION_MASK 0x0000f000 1914 #define DCBX_CEE_VERSION_SHIFT 12 1915 #define DCBX_CEE_MAX_VERSION_MASK 0x000f0000 1916 #define DCBX_CEE_MAX_VERSION_SHIFT 16 1917 struct dcbx_features features; 1918 }; 1919 1920 /* REMOTE MIB - remote machine DCBX configuration. */ 1921 struct lldp_remote_mib { 1922 u32 prefix_seq_num; 1923 u32 flags; 1924 #define DCBX_ETS_TLV_RX 0x00000001 1925 #define DCBX_PFC_TLV_RX 0x00000002 1926 #define DCBX_APP_TLV_RX 0x00000004 1927 #define DCBX_ETS_RX_ERROR 0x00000010 1928 #define DCBX_PFC_RX_ERROR 0x00000020 1929 #define DCBX_APP_RX_ERROR 0x00000040 1930 #define DCBX_ETS_REM_WILLING 0x00000100 1931 #define DCBX_PFC_REM_WILLING 0x00000200 1932 #define DCBX_APP_REM_WILLING 0x00000400 1933 #define DCBX_REMOTE_ETS_RECO_VALID 0x00001000 1934 #define DCBX_REMOTE_MIB_VALID 0x00002000 1935 struct dcbx_features features; 1936 u32 suffix_seq_num; 1937 }; 1938 1939 /* LOCAL MIB - operational DCBX configuration - transmitted on Tx LLDPDU. */ 1940 struct lldp_local_mib { 1941 u32 prefix_seq_num; 1942 /* Indicates if there is mismatch with negotiation results. */ 1943 u32 error; 1944 #define DCBX_LOCAL_ETS_ERROR 0x00000001 1945 #define DCBX_LOCAL_PFC_ERROR 0x00000002 1946 #define DCBX_LOCAL_APP_ERROR 0x00000004 1947 #define DCBX_LOCAL_PFC_MISMATCH 0x00000010 1948 #define DCBX_LOCAL_APP_MISMATCH 0x00000020 1949 #define DCBX_REMOTE_MIB_ERROR 0x00000040 1950 #define DCBX_REMOTE_ETS_TLV_NOT_FOUND 0x00000080 1951 #define DCBX_REMOTE_PFC_TLV_NOT_FOUND 0x00000100 1952 #define DCBX_REMOTE_APP_TLV_NOT_FOUND 0x00000200 1953 struct dcbx_features features; 1954 u32 suffix_seq_num; 1955 }; 1956 /***END OF DCBX STRUCTURES DECLARATIONS***/ 1957 1958 /***********************************************************/ 1959 /* Elink section */ 1960 /***********************************************************/ 1961 #define SHMEM_LINK_CONFIG_SIZE 2 1962 struct shmem_lfa { 1963 u32 req_duplex; 1964 #define REQ_DUPLEX_PHY0_MASK 0x0000ffff 1965 #define REQ_DUPLEX_PHY0_SHIFT 0 1966 #define REQ_DUPLEX_PHY1_MASK 0xffff0000 1967 #define REQ_DUPLEX_PHY1_SHIFT 16 1968 u32 req_flow_ctrl; 1969 #define REQ_FLOW_CTRL_PHY0_MASK 0x0000ffff 1970 #define REQ_FLOW_CTRL_PHY0_SHIFT 0 1971 #define REQ_FLOW_CTRL_PHY1_MASK 0xffff0000 1972 #define REQ_FLOW_CTRL_PHY1_SHIFT 16 1973 u32 req_line_speed; /* Also determine AutoNeg */ 1974 #define REQ_LINE_SPD_PHY0_MASK 0x0000ffff 1975 #define REQ_LINE_SPD_PHY0_SHIFT 0 1976 #define REQ_LINE_SPD_PHY1_MASK 0xffff0000 1977 #define REQ_LINE_SPD_PHY1_SHIFT 16 1978 u32 speed_cap_mask[SHMEM_LINK_CONFIG_SIZE]; 1979 u32 additional_config; 1980 #define REQ_FC_AUTO_ADV_MASK 0x0000ffff 1981 #define REQ_FC_AUTO_ADV0_SHIFT 0 1982 #define NO_LFA_DUE_TO_DCC_MASK 0x00010000 1983 u32 lfa_sts; 1984 #define LFA_LINK_FLAP_REASON_OFFSET 0 1985 #define LFA_LINK_FLAP_REASON_MASK 0x000000ff 1986 #define LFA_LINK_DOWN 0x1 1987 #define LFA_LOOPBACK_ENABLED 0x2 1988 #define LFA_DUPLEX_MISMATCH 0x3 1989 #define LFA_MFW_IS_TOO_OLD 0x4 1990 #define LFA_LINK_SPEED_MISMATCH 0x5 1991 #define LFA_FLOW_CTRL_MISMATCH 0x6 1992 #define LFA_SPEED_CAP_MISMATCH 0x7 1993 #define LFA_DCC_LFA_DISABLED 0x8 1994 #define LFA_EEE_MISMATCH 0x9 1995 1996 #define LINK_FLAP_AVOIDANCE_COUNT_OFFSET 8 1997 #define LINK_FLAP_AVOIDANCE_COUNT_MASK 0x0000ff00 1998 1999 #define LINK_FLAP_COUNT_OFFSET 16 2000 #define LINK_FLAP_COUNT_MASK 0x00ff0000 2001 2002 #define LFA_FLAGS_MASK 0xff000000 2003 #define SHMEM_LFA_DONT_CLEAR_STAT (1<<24) 2004 }; 2005 2006 struct ncsi_oem_fcoe_features { 2007 u32 fcoe_features1; 2008 #define FCOE_FEATURES1_IOS_PER_CONNECTION_MASK 0x0000FFFF 2009 #define FCOE_FEATURES1_IOS_PER_CONNECTION_OFFSET 0 2010 2011 #define FCOE_FEATURES1_LOGINS_PER_PORT_MASK 0xFFFF0000 2012 #define FCOE_FEATURES1_LOGINS_PER_PORT_OFFSET 16 2013 2014 u32 fcoe_features2; 2015 #define FCOE_FEATURES2_EXCHANGES_MASK 0x0000FFFF 2016 #define FCOE_FEATURES2_EXCHANGES_OFFSET 0 2017 2018 #define FCOE_FEATURES2_NPIV_WWN_PER_PORT_MASK 0xFFFF0000 2019 #define FCOE_FEATURES2_NPIV_WWN_PER_PORT_OFFSET 16 2020 2021 u32 fcoe_features3; 2022 #define FCOE_FEATURES3_TARGETS_SUPPORTED_MASK 0x0000FFFF 2023 #define FCOE_FEATURES3_TARGETS_SUPPORTED_OFFSET 0 2024 2025 #define FCOE_FEATURES3_OUTSTANDING_COMMANDS_MASK 0xFFFF0000 2026 #define FCOE_FEATURES3_OUTSTANDING_COMMANDS_OFFSET 16 2027 2028 u32 fcoe_features4; 2029 #define FCOE_FEATURES4_FEATURE_SETTINGS_MASK 0x0000000F 2030 #define FCOE_FEATURES4_FEATURE_SETTINGS_OFFSET 0 2031 }; 2032 2033 struct ncsi_oem_data { 2034 u32 driver_version[4]; 2035 struct ncsi_oem_fcoe_features ncsi_oem_fcoe_features; 2036 }; 2037 2038 struct shmem2_region { 2039 2040 u32 size; /* 0x0000 */ 2041 2042 u32 dcc_support; /* 0x0004 */ 2043 #define SHMEM_DCC_SUPPORT_NONE 0x00000000 2044 #define SHMEM_DCC_SUPPORT_DISABLE_ENABLE_PF_TLV 0x00000001 2045 #define SHMEM_DCC_SUPPORT_BANDWIDTH_ALLOCATION_TLV 0x00000004 2046 #define SHMEM_DCC_SUPPORT_CHANGE_MAC_ADDRESS_TLV 0x00000008 2047 #define SHMEM_DCC_SUPPORT_SET_PROTOCOL_TLV 0x00000040 2048 #define SHMEM_DCC_SUPPORT_SET_PRIORITY_TLV 0x00000080 2049 2050 u32 ext_phy_fw_version2[PORT_MAX]; /* 0x0008 */ 2051 /* 2052 * For backwards compatibility, if the mf_cfg_addr does not exist 2053 * (the size filed is smaller than 0xc) the mf_cfg resides at the 2054 * end of struct shmem_region 2055 */ 2056 u32 mf_cfg_addr; /* 0x0010 */ 2057 #define SHMEM_MF_CFG_ADDR_NONE 0x00000000 2058 2059 struct fw_flr_mb flr_mb; /* 0x0014 */ 2060 u32 dcbx_lldp_params_offset; /* 0x0028 */ 2061 #define SHMEM_LLDP_DCBX_PARAMS_NONE 0x00000000 2062 u32 dcbx_neg_res_offset; /* 0x002c */ 2063 #define SHMEM_DCBX_NEG_RES_NONE 0x00000000 2064 u32 dcbx_remote_mib_offset; /* 0x0030 */ 2065 #define SHMEM_DCBX_REMOTE_MIB_NONE 0x00000000 2066 /* 2067 * The other shmemX_base_addr holds the other path's shmem address 2068 * required for example in case of common phy init, or for path1 to know 2069 * the address of mcp debug trace which is located in offset from shmem 2070 * of path0 2071 */ 2072 u32 other_shmem_base_addr; /* 0x0034 */ 2073 u32 other_shmem2_base_addr; /* 0x0038 */ 2074 /* 2075 * mcp_vf_disabled is set by the MCP to indicate the driver about VFs 2076 * which were disabled/flred 2077 */ 2078 u32 mcp_vf_disabled[E2_VF_MAX / 32]; /* 0x003c */ 2079 2080 /* 2081 * drv_ack_vf_disabled is set by the PF driver to ack handled disabled 2082 * VFs 2083 */ 2084 u32 drv_ack_vf_disabled[E2_FUNC_MAX][E2_VF_MAX / 32]; /* 0x0044 */ 2085 2086 u32 dcbx_lldp_dcbx_stat_offset; /* 0x0064 */ 2087 #define SHMEM_LLDP_DCBX_STAT_NONE 0x00000000 2088 2089 /* 2090 * edebug_driver_if field is used to transfer messages between edebug 2091 * app to the driver through shmem2. 2092 * 2093 * message format: 2094 * bits 0-2 - function number / instance of driver to perform request 2095 * bits 3-5 - op code / is_ack? 2096 * bits 6-63 - data 2097 */ 2098 u32 edebug_driver_if[2]; /* 0x0068 */ 2099 #define EDEBUG_DRIVER_IF_OP_CODE_GET_PHYS_ADDR 1 2100 #define EDEBUG_DRIVER_IF_OP_CODE_GET_BUS_ADDR 2 2101 #define EDEBUG_DRIVER_IF_OP_CODE_DISABLE_STAT 3 2102 2103 u32 nvm_retain_bitmap_addr; /* 0x0070 */ 2104 2105 /* afex support of that driver */ 2106 u32 afex_driver_support; /* 0x0074 */ 2107 #define SHMEM_AFEX_VERSION_MASK 0x100f 2108 #define SHMEM_AFEX_SUPPORTED_VERSION_ONE 0x1001 2109 #define SHMEM_AFEX_REDUCED_DRV_LOADED 0x8000 2110 2111 /* driver receives addr in scratchpad to which it should respond */ 2112 u32 afex_scratchpad_addr_to_write[E2_FUNC_MAX]; 2113 2114 /* generic params from MCP to driver (value depends on the msg sent 2115 * to driver 2116 */ 2117 u32 afex_param1_to_driver[E2_FUNC_MAX]; /* 0x0088 */ 2118 u32 afex_param2_to_driver[E2_FUNC_MAX]; /* 0x0098 */ 2119 2120 u32 swim_base_addr; /* 0x0108 */ 2121 u32 swim_funcs; 2122 u32 swim_main_cb; 2123 2124 /* bitmap notifying which VIF profiles stored in nvram are enabled by 2125 * switch 2126 */ 2127 u32 afex_profiles_enabled[2]; 2128 2129 /* generic flags controlled by the driver */ 2130 u32 drv_flags; 2131 #define DRV_FLAGS_DCB_CONFIGURED 0x0 2132 #define DRV_FLAGS_DCB_CONFIGURATION_ABORTED 0x1 2133 #define DRV_FLAGS_DCB_MFW_CONFIGURED 0x2 2134 2135 #define DRV_FLAGS_PORT_MASK ((1 << DRV_FLAGS_DCB_CONFIGURED) | \ 2136 (1 << DRV_FLAGS_DCB_CONFIGURATION_ABORTED) | \ 2137 (1 << DRV_FLAGS_DCB_MFW_CONFIGURED)) 2138 /* pointer to extended dev_info shared data copied from nvm image */ 2139 u32 extended_dev_info_shared_addr; 2140 u32 ncsi_oem_data_addr; 2141 2142 u32 ocsd_host_addr; /* initialized by option ROM */ 2143 u32 ocbb_host_addr; /* initialized by option ROM */ 2144 u32 ocsd_req_update_interval; /* initialized by option ROM */ 2145 u32 temperature_in_half_celsius; 2146 u32 glob_struct_in_host; 2147 2148 u32 dcbx_neg_res_ext_offset; 2149 #define SHMEM_DCBX_NEG_RES_EXT_NONE 0x00000000 2150 2151 u32 drv_capabilities_flag[E2_FUNC_MAX]; 2152 #define DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED 0x00000001 2153 #define DRV_FLAGS_CAPABILITIES_LOADED_L2 0x00000002 2154 #define DRV_FLAGS_CAPABILITIES_LOADED_FCOE 0x00000004 2155 #define DRV_FLAGS_CAPABILITIES_LOADED_ISCSI 0x00000008 2156 2157 u32 extended_dev_info_shared_cfg_size; 2158 2159 u32 dcbx_en[PORT_MAX]; 2160 2161 /* The offset points to the multi threaded meta structure */ 2162 u32 multi_thread_data_offset; 2163 2164 /* address of DMAable host address holding values from the drivers */ 2165 u32 drv_info_host_addr_lo; 2166 u32 drv_info_host_addr_hi; 2167 2168 /* general values written by the MFW (such as current version) */ 2169 u32 drv_info_control; 2170 #define DRV_INFO_CONTROL_VER_MASK 0x000000ff 2171 #define DRV_INFO_CONTROL_VER_SHIFT 0 2172 #define DRV_INFO_CONTROL_OP_CODE_MASK 0x0000ff00 2173 #define DRV_INFO_CONTROL_OP_CODE_SHIFT 8 2174 u32 ibft_host_addr; /* initialized by option ROM */ 2175 struct eee_remote_vals eee_remote_vals[PORT_MAX]; 2176 u32 reserved[E2_FUNC_MAX]; 2177 2178 2179 /* the status of EEE auto-negotiation 2180 * bits 15:0 the configured tx-lpi entry timer value. Depends on bit 31. 2181 * bits 19:16 the supported modes for EEE. 2182 * bits 23:20 the speeds advertised for EEE. 2183 * bits 27:24 the speeds the Link partner advertised for EEE. 2184 * The supported/adv. modes in bits 27:19 originate from the 2185 * SHMEM_EEE_XXX_ADV definitions (where XXX is replaced by speed). 2186 * bit 28 when 1'b1 EEE was requested. 2187 * bit 29 when 1'b1 tx lpi was requested. 2188 * bit 30 when 1'b1 EEE was negotiated. Tx lpi will be asserted iff 2189 * 30:29 are 2'b11. 2190 * bit 31 when 1'b0 bits 15:0 contain a PORT_FEAT_CFG_EEE_ define as 2191 * value. When 1'b1 those bits contains a value times 16 microseconds. 2192 */ 2193 u32 eee_status[PORT_MAX]; 2194 #define SHMEM_EEE_TIMER_MASK 0x0000ffff 2195 #define SHMEM_EEE_SUPPORTED_MASK 0x000f0000 2196 #define SHMEM_EEE_SUPPORTED_SHIFT 16 2197 #define SHMEM_EEE_ADV_STATUS_MASK 0x00f00000 2198 #define SHMEM_EEE_100M_ADV (1<<0) 2199 #define SHMEM_EEE_1G_ADV (1<<1) 2200 #define SHMEM_EEE_10G_ADV (1<<2) 2201 #define SHMEM_EEE_ADV_STATUS_SHIFT 20 2202 #define SHMEM_EEE_LP_ADV_STATUS_MASK 0x0f000000 2203 #define SHMEM_EEE_LP_ADV_STATUS_SHIFT 24 2204 #define SHMEM_EEE_REQUESTED_BIT 0x10000000 2205 #define SHMEM_EEE_LPI_REQUESTED_BIT 0x20000000 2206 #define SHMEM_EEE_ACTIVE_BIT 0x40000000 2207 #define SHMEM_EEE_TIME_OUTPUT_BIT 0x80000000 2208 2209 u32 sizeof_port_stats; 2210 2211 /* Link Flap Avoidance */ 2212 u32 lfa_host_addr[PORT_MAX]; 2213 u32 reserved1; 2214 2215 u32 reserved2; /* Offset 0x148 */ 2216 u32 reserved3; /* Offset 0x14C */ 2217 u32 reserved4; /* Offset 0x150 */ 2218 u32 link_attr_sync[PORT_MAX]; /* Offset 0x154 */ 2219 #define LINK_ATTR_SYNC_KR2_ENABLE (1<<0) 2220 }; 2221 2222 2223 struct emac_stats { 2224 u32 rx_stat_ifhcinoctets; 2225 u32 rx_stat_ifhcinbadoctets; 2226 u32 rx_stat_etherstatsfragments; 2227 u32 rx_stat_ifhcinucastpkts; 2228 u32 rx_stat_ifhcinmulticastpkts; 2229 u32 rx_stat_ifhcinbroadcastpkts; 2230 u32 rx_stat_dot3statsfcserrors; 2231 u32 rx_stat_dot3statsalignmenterrors; 2232 u32 rx_stat_dot3statscarriersenseerrors; 2233 u32 rx_stat_xonpauseframesreceived; 2234 u32 rx_stat_xoffpauseframesreceived; 2235 u32 rx_stat_maccontrolframesreceived; 2236 u32 rx_stat_xoffstateentered; 2237 u32 rx_stat_dot3statsframestoolong; 2238 u32 rx_stat_etherstatsjabbers; 2239 u32 rx_stat_etherstatsundersizepkts; 2240 u32 rx_stat_etherstatspkts64octets; 2241 u32 rx_stat_etherstatspkts65octetsto127octets; 2242 u32 rx_stat_etherstatspkts128octetsto255octets; 2243 u32 rx_stat_etherstatspkts256octetsto511octets; 2244 u32 rx_stat_etherstatspkts512octetsto1023octets; 2245 u32 rx_stat_etherstatspkts1024octetsto1522octets; 2246 u32 rx_stat_etherstatspktsover1522octets; 2247 2248 u32 rx_stat_falsecarriererrors; 2249 2250 u32 tx_stat_ifhcoutoctets; 2251 u32 tx_stat_ifhcoutbadoctets; 2252 u32 tx_stat_etherstatscollisions; 2253 u32 tx_stat_outxonsent; 2254 u32 tx_stat_outxoffsent; 2255 u32 tx_stat_flowcontroldone; 2256 u32 tx_stat_dot3statssinglecollisionframes; 2257 u32 tx_stat_dot3statsmultiplecollisionframes; 2258 u32 tx_stat_dot3statsdeferredtransmissions; 2259 u32 tx_stat_dot3statsexcessivecollisions; 2260 u32 tx_stat_dot3statslatecollisions; 2261 u32 tx_stat_ifhcoutucastpkts; 2262 u32 tx_stat_ifhcoutmulticastpkts; 2263 u32 tx_stat_ifhcoutbroadcastpkts; 2264 u32 tx_stat_etherstatspkts64octets; 2265 u32 tx_stat_etherstatspkts65octetsto127octets; 2266 u32 tx_stat_etherstatspkts128octetsto255octets; 2267 u32 tx_stat_etherstatspkts256octetsto511octets; 2268 u32 tx_stat_etherstatspkts512octetsto1023octets; 2269 u32 tx_stat_etherstatspkts1024octetsto1522octets; 2270 u32 tx_stat_etherstatspktsover1522octets; 2271 u32 tx_stat_dot3statsinternalmactransmiterrors; 2272 }; 2273 2274 2275 struct bmac1_stats { 2276 u32 tx_stat_gtpkt_lo; 2277 u32 tx_stat_gtpkt_hi; 2278 u32 tx_stat_gtxpf_lo; 2279 u32 tx_stat_gtxpf_hi; 2280 u32 tx_stat_gtfcs_lo; 2281 u32 tx_stat_gtfcs_hi; 2282 u32 tx_stat_gtmca_lo; 2283 u32 tx_stat_gtmca_hi; 2284 u32 tx_stat_gtbca_lo; 2285 u32 tx_stat_gtbca_hi; 2286 u32 tx_stat_gtfrg_lo; 2287 u32 tx_stat_gtfrg_hi; 2288 u32 tx_stat_gtovr_lo; 2289 u32 tx_stat_gtovr_hi; 2290 u32 tx_stat_gt64_lo; 2291 u32 tx_stat_gt64_hi; 2292 u32 tx_stat_gt127_lo; 2293 u32 tx_stat_gt127_hi; 2294 u32 tx_stat_gt255_lo; 2295 u32 tx_stat_gt255_hi; 2296 u32 tx_stat_gt511_lo; 2297 u32 tx_stat_gt511_hi; 2298 u32 tx_stat_gt1023_lo; 2299 u32 tx_stat_gt1023_hi; 2300 u32 tx_stat_gt1518_lo; 2301 u32 tx_stat_gt1518_hi; 2302 u32 tx_stat_gt2047_lo; 2303 u32 tx_stat_gt2047_hi; 2304 u32 tx_stat_gt4095_lo; 2305 u32 tx_stat_gt4095_hi; 2306 u32 tx_stat_gt9216_lo; 2307 u32 tx_stat_gt9216_hi; 2308 u32 tx_stat_gt16383_lo; 2309 u32 tx_stat_gt16383_hi; 2310 u32 tx_stat_gtmax_lo; 2311 u32 tx_stat_gtmax_hi; 2312 u32 tx_stat_gtufl_lo; 2313 u32 tx_stat_gtufl_hi; 2314 u32 tx_stat_gterr_lo; 2315 u32 tx_stat_gterr_hi; 2316 u32 tx_stat_gtbyt_lo; 2317 u32 tx_stat_gtbyt_hi; 2318 2319 u32 rx_stat_gr64_lo; 2320 u32 rx_stat_gr64_hi; 2321 u32 rx_stat_gr127_lo; 2322 u32 rx_stat_gr127_hi; 2323 u32 rx_stat_gr255_lo; 2324 u32 rx_stat_gr255_hi; 2325 u32 rx_stat_gr511_lo; 2326 u32 rx_stat_gr511_hi; 2327 u32 rx_stat_gr1023_lo; 2328 u32 rx_stat_gr1023_hi; 2329 u32 rx_stat_gr1518_lo; 2330 u32 rx_stat_gr1518_hi; 2331 u32 rx_stat_gr2047_lo; 2332 u32 rx_stat_gr2047_hi; 2333 u32 rx_stat_gr4095_lo; 2334 u32 rx_stat_gr4095_hi; 2335 u32 rx_stat_gr9216_lo; 2336 u32 rx_stat_gr9216_hi; 2337 u32 rx_stat_gr16383_lo; 2338 u32 rx_stat_gr16383_hi; 2339 u32 rx_stat_grmax_lo; 2340 u32 rx_stat_grmax_hi; 2341 u32 rx_stat_grpkt_lo; 2342 u32 rx_stat_grpkt_hi; 2343 u32 rx_stat_grfcs_lo; 2344 u32 rx_stat_grfcs_hi; 2345 u32 rx_stat_grmca_lo; 2346 u32 rx_stat_grmca_hi; 2347 u32 rx_stat_grbca_lo; 2348 u32 rx_stat_grbca_hi; 2349 u32 rx_stat_grxcf_lo; 2350 u32 rx_stat_grxcf_hi; 2351 u32 rx_stat_grxpf_lo; 2352 u32 rx_stat_grxpf_hi; 2353 u32 rx_stat_grxuo_lo; 2354 u32 rx_stat_grxuo_hi; 2355 u32 rx_stat_grjbr_lo; 2356 u32 rx_stat_grjbr_hi; 2357 u32 rx_stat_grovr_lo; 2358 u32 rx_stat_grovr_hi; 2359 u32 rx_stat_grflr_lo; 2360 u32 rx_stat_grflr_hi; 2361 u32 rx_stat_grmeg_lo; 2362 u32 rx_stat_grmeg_hi; 2363 u32 rx_stat_grmeb_lo; 2364 u32 rx_stat_grmeb_hi; 2365 u32 rx_stat_grbyt_lo; 2366 u32 rx_stat_grbyt_hi; 2367 u32 rx_stat_grund_lo; 2368 u32 rx_stat_grund_hi; 2369 u32 rx_stat_grfrg_lo; 2370 u32 rx_stat_grfrg_hi; 2371 u32 rx_stat_grerb_lo; 2372 u32 rx_stat_grerb_hi; 2373 u32 rx_stat_grfre_lo; 2374 u32 rx_stat_grfre_hi; 2375 u32 rx_stat_gripj_lo; 2376 u32 rx_stat_gripj_hi; 2377 }; 2378 2379 struct bmac2_stats { 2380 u32 tx_stat_gtpk_lo; /* gtpok */ 2381 u32 tx_stat_gtpk_hi; /* gtpok */ 2382 u32 tx_stat_gtxpf_lo; /* gtpf */ 2383 u32 tx_stat_gtxpf_hi; /* gtpf */ 2384 u32 tx_stat_gtpp_lo; /* NEW BMAC2 */ 2385 u32 tx_stat_gtpp_hi; /* NEW BMAC2 */ 2386 u32 tx_stat_gtfcs_lo; 2387 u32 tx_stat_gtfcs_hi; 2388 u32 tx_stat_gtuca_lo; /* NEW BMAC2 */ 2389 u32 tx_stat_gtuca_hi; /* NEW BMAC2 */ 2390 u32 tx_stat_gtmca_lo; 2391 u32 tx_stat_gtmca_hi; 2392 u32 tx_stat_gtbca_lo; 2393 u32 tx_stat_gtbca_hi; 2394 u32 tx_stat_gtovr_lo; 2395 u32 tx_stat_gtovr_hi; 2396 u32 tx_stat_gtfrg_lo; 2397 u32 tx_stat_gtfrg_hi; 2398 u32 tx_stat_gtpkt1_lo; /* gtpkt */ 2399 u32 tx_stat_gtpkt1_hi; /* gtpkt */ 2400 u32 tx_stat_gt64_lo; 2401 u32 tx_stat_gt64_hi; 2402 u32 tx_stat_gt127_lo; 2403 u32 tx_stat_gt127_hi; 2404 u32 tx_stat_gt255_lo; 2405 u32 tx_stat_gt255_hi; 2406 u32 tx_stat_gt511_lo; 2407 u32 tx_stat_gt511_hi; 2408 u32 tx_stat_gt1023_lo; 2409 u32 tx_stat_gt1023_hi; 2410 u32 tx_stat_gt1518_lo; 2411 u32 tx_stat_gt1518_hi; 2412 u32 tx_stat_gt2047_lo; 2413 u32 tx_stat_gt2047_hi; 2414 u32 tx_stat_gt4095_lo; 2415 u32 tx_stat_gt4095_hi; 2416 u32 tx_stat_gt9216_lo; 2417 u32 tx_stat_gt9216_hi; 2418 u32 tx_stat_gt16383_lo; 2419 u32 tx_stat_gt16383_hi; 2420 u32 tx_stat_gtmax_lo; 2421 u32 tx_stat_gtmax_hi; 2422 u32 tx_stat_gtufl_lo; 2423 u32 tx_stat_gtufl_hi; 2424 u32 tx_stat_gterr_lo; 2425 u32 tx_stat_gterr_hi; 2426 u32 tx_stat_gtbyt_lo; 2427 u32 tx_stat_gtbyt_hi; 2428 2429 u32 rx_stat_gr64_lo; 2430 u32 rx_stat_gr64_hi; 2431 u32 rx_stat_gr127_lo; 2432 u32 rx_stat_gr127_hi; 2433 u32 rx_stat_gr255_lo; 2434 u32 rx_stat_gr255_hi; 2435 u32 rx_stat_gr511_lo; 2436 u32 rx_stat_gr511_hi; 2437 u32 rx_stat_gr1023_lo; 2438 u32 rx_stat_gr1023_hi; 2439 u32 rx_stat_gr1518_lo; 2440 u32 rx_stat_gr1518_hi; 2441 u32 rx_stat_gr2047_lo; 2442 u32 rx_stat_gr2047_hi; 2443 u32 rx_stat_gr4095_lo; 2444 u32 rx_stat_gr4095_hi; 2445 u32 rx_stat_gr9216_lo; 2446 u32 rx_stat_gr9216_hi; 2447 u32 rx_stat_gr16383_lo; 2448 u32 rx_stat_gr16383_hi; 2449 u32 rx_stat_grmax_lo; 2450 u32 rx_stat_grmax_hi; 2451 u32 rx_stat_grpkt_lo; 2452 u32 rx_stat_grpkt_hi; 2453 u32 rx_stat_grfcs_lo; 2454 u32 rx_stat_grfcs_hi; 2455 u32 rx_stat_gruca_lo; 2456 u32 rx_stat_gruca_hi; 2457 u32 rx_stat_grmca_lo; 2458 u32 rx_stat_grmca_hi; 2459 u32 rx_stat_grbca_lo; 2460 u32 rx_stat_grbca_hi; 2461 u32 rx_stat_grxpf_lo; /* grpf */ 2462 u32 rx_stat_grxpf_hi; /* grpf */ 2463 u32 rx_stat_grpp_lo; 2464 u32 rx_stat_grpp_hi; 2465 u32 rx_stat_grxuo_lo; /* gruo */ 2466 u32 rx_stat_grxuo_hi; /* gruo */ 2467 u32 rx_stat_grjbr_lo; 2468 u32 rx_stat_grjbr_hi; 2469 u32 rx_stat_grovr_lo; 2470 u32 rx_stat_grovr_hi; 2471 u32 rx_stat_grxcf_lo; /* grcf */ 2472 u32 rx_stat_grxcf_hi; /* grcf */ 2473 u32 rx_stat_grflr_lo; 2474 u32 rx_stat_grflr_hi; 2475 u32 rx_stat_grpok_lo; 2476 u32 rx_stat_grpok_hi; 2477 u32 rx_stat_grmeg_lo; 2478 u32 rx_stat_grmeg_hi; 2479 u32 rx_stat_grmeb_lo; 2480 u32 rx_stat_grmeb_hi; 2481 u32 rx_stat_grbyt_lo; 2482 u32 rx_stat_grbyt_hi; 2483 u32 rx_stat_grund_lo; 2484 u32 rx_stat_grund_hi; 2485 u32 rx_stat_grfrg_lo; 2486 u32 rx_stat_grfrg_hi; 2487 u32 rx_stat_grerb_lo; /* grerrbyt */ 2488 u32 rx_stat_grerb_hi; /* grerrbyt */ 2489 u32 rx_stat_grfre_lo; /* grfrerr */ 2490 u32 rx_stat_grfre_hi; /* grfrerr */ 2491 u32 rx_stat_gripj_lo; 2492 u32 rx_stat_gripj_hi; 2493 }; 2494 2495 struct mstat_stats { 2496 struct { 2497 /* OTE MSTAT on E3 has a bug where this register's contents are 2498 * actually tx_gtxpok + tx_gtxpf + (possibly)tx_gtxpp 2499 */ 2500 u32 tx_gtxpok_lo; 2501 u32 tx_gtxpok_hi; 2502 u32 tx_gtxpf_lo; 2503 u32 tx_gtxpf_hi; 2504 u32 tx_gtxpp_lo; 2505 u32 tx_gtxpp_hi; 2506 u32 tx_gtfcs_lo; 2507 u32 tx_gtfcs_hi; 2508 u32 tx_gtuca_lo; 2509 u32 tx_gtuca_hi; 2510 u32 tx_gtmca_lo; 2511 u32 tx_gtmca_hi; 2512 u32 tx_gtgca_lo; 2513 u32 tx_gtgca_hi; 2514 u32 tx_gtpkt_lo; 2515 u32 tx_gtpkt_hi; 2516 u32 tx_gt64_lo; 2517 u32 tx_gt64_hi; 2518 u32 tx_gt127_lo; 2519 u32 tx_gt127_hi; 2520 u32 tx_gt255_lo; 2521 u32 tx_gt255_hi; 2522 u32 tx_gt511_lo; 2523 u32 tx_gt511_hi; 2524 u32 tx_gt1023_lo; 2525 u32 tx_gt1023_hi; 2526 u32 tx_gt1518_lo; 2527 u32 tx_gt1518_hi; 2528 u32 tx_gt2047_lo; 2529 u32 tx_gt2047_hi; 2530 u32 tx_gt4095_lo; 2531 u32 tx_gt4095_hi; 2532 u32 tx_gt9216_lo; 2533 u32 tx_gt9216_hi; 2534 u32 tx_gt16383_lo; 2535 u32 tx_gt16383_hi; 2536 u32 tx_gtufl_lo; 2537 u32 tx_gtufl_hi; 2538 u32 tx_gterr_lo; 2539 u32 tx_gterr_hi; 2540 u32 tx_gtbyt_lo; 2541 u32 tx_gtbyt_hi; 2542 u32 tx_collisions_lo; 2543 u32 tx_collisions_hi; 2544 u32 tx_singlecollision_lo; 2545 u32 tx_singlecollision_hi; 2546 u32 tx_multiplecollisions_lo; 2547 u32 tx_multiplecollisions_hi; 2548 u32 tx_deferred_lo; 2549 u32 tx_deferred_hi; 2550 u32 tx_excessivecollisions_lo; 2551 u32 tx_excessivecollisions_hi; 2552 u32 tx_latecollisions_lo; 2553 u32 tx_latecollisions_hi; 2554 } stats_tx; 2555 2556 struct { 2557 u32 rx_gr64_lo; 2558 u32 rx_gr64_hi; 2559 u32 rx_gr127_lo; 2560 u32 rx_gr127_hi; 2561 u32 rx_gr255_lo; 2562 u32 rx_gr255_hi; 2563 u32 rx_gr511_lo; 2564 u32 rx_gr511_hi; 2565 u32 rx_gr1023_lo; 2566 u32 rx_gr1023_hi; 2567 u32 rx_gr1518_lo; 2568 u32 rx_gr1518_hi; 2569 u32 rx_gr2047_lo; 2570 u32 rx_gr2047_hi; 2571 u32 rx_gr4095_lo; 2572 u32 rx_gr4095_hi; 2573 u32 rx_gr9216_lo; 2574 u32 rx_gr9216_hi; 2575 u32 rx_gr16383_lo; 2576 u32 rx_gr16383_hi; 2577 u32 rx_grpkt_lo; 2578 u32 rx_grpkt_hi; 2579 u32 rx_grfcs_lo; 2580 u32 rx_grfcs_hi; 2581 u32 rx_gruca_lo; 2582 u32 rx_gruca_hi; 2583 u32 rx_grmca_lo; 2584 u32 rx_grmca_hi; 2585 u32 rx_grbca_lo; 2586 u32 rx_grbca_hi; 2587 u32 rx_grxpf_lo; 2588 u32 rx_grxpf_hi; 2589 u32 rx_grxpp_lo; 2590 u32 rx_grxpp_hi; 2591 u32 rx_grxuo_lo; 2592 u32 rx_grxuo_hi; 2593 u32 rx_grovr_lo; 2594 u32 rx_grovr_hi; 2595 u32 rx_grxcf_lo; 2596 u32 rx_grxcf_hi; 2597 u32 rx_grflr_lo; 2598 u32 rx_grflr_hi; 2599 u32 rx_grpok_lo; 2600 u32 rx_grpok_hi; 2601 u32 rx_grbyt_lo; 2602 u32 rx_grbyt_hi; 2603 u32 rx_grund_lo; 2604 u32 rx_grund_hi; 2605 u32 rx_grfrg_lo; 2606 u32 rx_grfrg_hi; 2607 u32 rx_grerb_lo; 2608 u32 rx_grerb_hi; 2609 u32 rx_grfre_lo; 2610 u32 rx_grfre_hi; 2611 2612 u32 rx_alignmenterrors_lo; 2613 u32 rx_alignmenterrors_hi; 2614 u32 rx_falsecarrier_lo; 2615 u32 rx_falsecarrier_hi; 2616 u32 rx_llfcmsgcnt_lo; 2617 u32 rx_llfcmsgcnt_hi; 2618 } stats_rx; 2619 }; 2620 2621 union mac_stats { 2622 struct emac_stats emac_stats; 2623 struct bmac1_stats bmac1_stats; 2624 struct bmac2_stats bmac2_stats; 2625 struct mstat_stats mstat_stats; 2626 }; 2627 2628 2629 struct mac_stx { 2630 /* in_bad_octets */ 2631 u32 rx_stat_ifhcinbadoctets_hi; 2632 u32 rx_stat_ifhcinbadoctets_lo; 2633 2634 /* out_bad_octets */ 2635 u32 tx_stat_ifhcoutbadoctets_hi; 2636 u32 tx_stat_ifhcoutbadoctets_lo; 2637 2638 /* crc_receive_errors */ 2639 u32 rx_stat_dot3statsfcserrors_hi; 2640 u32 rx_stat_dot3statsfcserrors_lo; 2641 /* alignment_errors */ 2642 u32 rx_stat_dot3statsalignmenterrors_hi; 2643 u32 rx_stat_dot3statsalignmenterrors_lo; 2644 /* carrier_sense_errors */ 2645 u32 rx_stat_dot3statscarriersenseerrors_hi; 2646 u32 rx_stat_dot3statscarriersenseerrors_lo; 2647 /* false_carrier_detections */ 2648 u32 rx_stat_falsecarriererrors_hi; 2649 u32 rx_stat_falsecarriererrors_lo; 2650 2651 /* runt_packets_received */ 2652 u32 rx_stat_etherstatsundersizepkts_hi; 2653 u32 rx_stat_etherstatsundersizepkts_lo; 2654 /* jabber_packets_received */ 2655 u32 rx_stat_dot3statsframestoolong_hi; 2656 u32 rx_stat_dot3statsframestoolong_lo; 2657 2658 /* error_runt_packets_received */ 2659 u32 rx_stat_etherstatsfragments_hi; 2660 u32 rx_stat_etherstatsfragments_lo; 2661 /* error_jabber_packets_received */ 2662 u32 rx_stat_etherstatsjabbers_hi; 2663 u32 rx_stat_etherstatsjabbers_lo; 2664 2665 /* control_frames_received */ 2666 u32 rx_stat_maccontrolframesreceived_hi; 2667 u32 rx_stat_maccontrolframesreceived_lo; 2668 u32 rx_stat_mac_xpf_hi; 2669 u32 rx_stat_mac_xpf_lo; 2670 u32 rx_stat_mac_xcf_hi; 2671 u32 rx_stat_mac_xcf_lo; 2672 2673 /* xoff_state_entered */ 2674 u32 rx_stat_xoffstateentered_hi; 2675 u32 rx_stat_xoffstateentered_lo; 2676 /* pause_xon_frames_received */ 2677 u32 rx_stat_xonpauseframesreceived_hi; 2678 u32 rx_stat_xonpauseframesreceived_lo; 2679 /* pause_xoff_frames_received */ 2680 u32 rx_stat_xoffpauseframesreceived_hi; 2681 u32 rx_stat_xoffpauseframesreceived_lo; 2682 /* pause_xon_frames_transmitted */ 2683 u32 tx_stat_outxonsent_hi; 2684 u32 tx_stat_outxonsent_lo; 2685 /* pause_xoff_frames_transmitted */ 2686 u32 tx_stat_outxoffsent_hi; 2687 u32 tx_stat_outxoffsent_lo; 2688 /* flow_control_done */ 2689 u32 tx_stat_flowcontroldone_hi; 2690 u32 tx_stat_flowcontroldone_lo; 2691 2692 /* ether_stats_collisions */ 2693 u32 tx_stat_etherstatscollisions_hi; 2694 u32 tx_stat_etherstatscollisions_lo; 2695 /* single_collision_transmit_frames */ 2696 u32 tx_stat_dot3statssinglecollisionframes_hi; 2697 u32 tx_stat_dot3statssinglecollisionframes_lo; 2698 /* multiple_collision_transmit_frames */ 2699 u32 tx_stat_dot3statsmultiplecollisionframes_hi; 2700 u32 tx_stat_dot3statsmultiplecollisionframes_lo; 2701 /* deferred_transmissions */ 2702 u32 tx_stat_dot3statsdeferredtransmissions_hi; 2703 u32 tx_stat_dot3statsdeferredtransmissions_lo; 2704 /* excessive_collision_frames */ 2705 u32 tx_stat_dot3statsexcessivecollisions_hi; 2706 u32 tx_stat_dot3statsexcessivecollisions_lo; 2707 /* late_collision_frames */ 2708 u32 tx_stat_dot3statslatecollisions_hi; 2709 u32 tx_stat_dot3statslatecollisions_lo; 2710 2711 /* frames_transmitted_64_bytes */ 2712 u32 tx_stat_etherstatspkts64octets_hi; 2713 u32 tx_stat_etherstatspkts64octets_lo; 2714 /* frames_transmitted_65_127_bytes */ 2715 u32 tx_stat_etherstatspkts65octetsto127octets_hi; 2716 u32 tx_stat_etherstatspkts65octetsto127octets_lo; 2717 /* frames_transmitted_128_255_bytes */ 2718 u32 tx_stat_etherstatspkts128octetsto255octets_hi; 2719 u32 tx_stat_etherstatspkts128octetsto255octets_lo; 2720 /* frames_transmitted_256_511_bytes */ 2721 u32 tx_stat_etherstatspkts256octetsto511octets_hi; 2722 u32 tx_stat_etherstatspkts256octetsto511octets_lo; 2723 /* frames_transmitted_512_1023_bytes */ 2724 u32 tx_stat_etherstatspkts512octetsto1023octets_hi; 2725 u32 tx_stat_etherstatspkts512octetsto1023octets_lo; 2726 /* frames_transmitted_1024_1522_bytes */ 2727 u32 tx_stat_etherstatspkts1024octetsto1522octets_hi; 2728 u32 tx_stat_etherstatspkts1024octetsto1522octets_lo; 2729 /* frames_transmitted_1523_9022_bytes */ 2730 u32 tx_stat_etherstatspktsover1522octets_hi; 2731 u32 tx_stat_etherstatspktsover1522octets_lo; 2732 u32 tx_stat_mac_2047_hi; 2733 u32 tx_stat_mac_2047_lo; 2734 u32 tx_stat_mac_4095_hi; 2735 u32 tx_stat_mac_4095_lo; 2736 u32 tx_stat_mac_9216_hi; 2737 u32 tx_stat_mac_9216_lo; 2738 u32 tx_stat_mac_16383_hi; 2739 u32 tx_stat_mac_16383_lo; 2740 2741 /* internal_mac_transmit_errors */ 2742 u32 tx_stat_dot3statsinternalmactransmiterrors_hi; 2743 u32 tx_stat_dot3statsinternalmactransmiterrors_lo; 2744 2745 /* if_out_discards */ 2746 u32 tx_stat_mac_ufl_hi; 2747 u32 tx_stat_mac_ufl_lo; 2748 }; 2749 2750 2751 #define MAC_STX_IDX_MAX 2 2752 2753 struct host_port_stats { 2754 u32 host_port_stats_counter; 2755 2756 struct mac_stx mac_stx[MAC_STX_IDX_MAX]; 2757 2758 u32 brb_drop_hi; 2759 u32 brb_drop_lo; 2760 2761 u32 not_used; /* obsolete */ 2762 u32 pfc_frames_tx_hi; 2763 u32 pfc_frames_tx_lo; 2764 u32 pfc_frames_rx_hi; 2765 u32 pfc_frames_rx_lo; 2766 2767 u32 eee_lpi_count_hi; 2768 u32 eee_lpi_count_lo; 2769 }; 2770 2771 2772 struct host_func_stats { 2773 u32 host_func_stats_start; 2774 2775 u32 total_bytes_received_hi; 2776 u32 total_bytes_received_lo; 2777 2778 u32 total_bytes_transmitted_hi; 2779 u32 total_bytes_transmitted_lo; 2780 2781 u32 total_unicast_packets_received_hi; 2782 u32 total_unicast_packets_received_lo; 2783 2784 u32 total_multicast_packets_received_hi; 2785 u32 total_multicast_packets_received_lo; 2786 2787 u32 total_broadcast_packets_received_hi; 2788 u32 total_broadcast_packets_received_lo; 2789 2790 u32 total_unicast_packets_transmitted_hi; 2791 u32 total_unicast_packets_transmitted_lo; 2792 2793 u32 total_multicast_packets_transmitted_hi; 2794 u32 total_multicast_packets_transmitted_lo; 2795 2796 u32 total_broadcast_packets_transmitted_hi; 2797 u32 total_broadcast_packets_transmitted_lo; 2798 2799 u32 valid_bytes_received_hi; 2800 u32 valid_bytes_received_lo; 2801 2802 u32 host_func_stats_end; 2803 }; 2804 2805 /* VIC definitions */ 2806 #define VICSTATST_UIF_INDEX 2 2807 2808 2809 /* stats collected for afex. 2810 * NOTE: structure is exactly as expected to be received by the switch. 2811 * order must remain exactly as is unless protocol changes ! 2812 */ 2813 struct afex_stats { 2814 u32 tx_unicast_frames_hi; 2815 u32 tx_unicast_frames_lo; 2816 u32 tx_unicast_bytes_hi; 2817 u32 tx_unicast_bytes_lo; 2818 u32 tx_multicast_frames_hi; 2819 u32 tx_multicast_frames_lo; 2820 u32 tx_multicast_bytes_hi; 2821 u32 tx_multicast_bytes_lo; 2822 u32 tx_broadcast_frames_hi; 2823 u32 tx_broadcast_frames_lo; 2824 u32 tx_broadcast_bytes_hi; 2825 u32 tx_broadcast_bytes_lo; 2826 u32 tx_frames_discarded_hi; 2827 u32 tx_frames_discarded_lo; 2828 u32 tx_frames_dropped_hi; 2829 u32 tx_frames_dropped_lo; 2830 2831 u32 rx_unicast_frames_hi; 2832 u32 rx_unicast_frames_lo; 2833 u32 rx_unicast_bytes_hi; 2834 u32 rx_unicast_bytes_lo; 2835 u32 rx_multicast_frames_hi; 2836 u32 rx_multicast_frames_lo; 2837 u32 rx_multicast_bytes_hi; 2838 u32 rx_multicast_bytes_lo; 2839 u32 rx_broadcast_frames_hi; 2840 u32 rx_broadcast_frames_lo; 2841 u32 rx_broadcast_bytes_hi; 2842 u32 rx_broadcast_bytes_lo; 2843 u32 rx_frames_discarded_hi; 2844 u32 rx_frames_discarded_lo; 2845 u32 rx_frames_dropped_hi; 2846 u32 rx_frames_dropped_lo; 2847 }; 2848 2849 #define BCM_5710_FW_MAJOR_VERSION 7 2850 #define BCM_5710_FW_MINOR_VERSION 8 2851 #define BCM_5710_FW_REVISION_VERSION 17 2852 #define BCM_5710_FW_ENGINEERING_VERSION 0 2853 #define BCM_5710_FW_COMPILE_FLAGS 1 2854 2855 2856 /* 2857 * attention bits 2858 */ 2859 struct atten_sp_status_block { 2860 __le32 attn_bits; 2861 __le32 attn_bits_ack; 2862 u8 status_block_id; 2863 u8 reserved0; 2864 __le16 attn_bits_index; 2865 __le32 reserved1; 2866 }; 2867 2868 2869 /* 2870 * The eth aggregative context of Cstorm 2871 */ 2872 struct cstorm_eth_ag_context { 2873 u32 __reserved0[10]; 2874 }; 2875 2876 2877 /* 2878 * dmae command structure 2879 */ 2880 struct dmae_command { 2881 u32 opcode; 2882 #define DMAE_COMMAND_SRC (0x1<<0) 2883 #define DMAE_COMMAND_SRC_SHIFT 0 2884 #define DMAE_COMMAND_DST (0x3<<1) 2885 #define DMAE_COMMAND_DST_SHIFT 1 2886 #define DMAE_COMMAND_C_DST (0x1<<3) 2887 #define DMAE_COMMAND_C_DST_SHIFT 3 2888 #define DMAE_COMMAND_C_TYPE_ENABLE (0x1<<4) 2889 #define DMAE_COMMAND_C_TYPE_ENABLE_SHIFT 4 2890 #define DMAE_COMMAND_C_TYPE_CRC_ENABLE (0x1<<5) 2891 #define DMAE_COMMAND_C_TYPE_CRC_ENABLE_SHIFT 5 2892 #define DMAE_COMMAND_C_TYPE_CRC_OFFSET (0x7<<6) 2893 #define DMAE_COMMAND_C_TYPE_CRC_OFFSET_SHIFT 6 2894 #define DMAE_COMMAND_ENDIANITY (0x3<<9) 2895 #define DMAE_COMMAND_ENDIANITY_SHIFT 9 2896 #define DMAE_COMMAND_PORT (0x1<<11) 2897 #define DMAE_COMMAND_PORT_SHIFT 11 2898 #define DMAE_COMMAND_CRC_RESET (0x1<<12) 2899 #define DMAE_COMMAND_CRC_RESET_SHIFT 12 2900 #define DMAE_COMMAND_SRC_RESET (0x1<<13) 2901 #define DMAE_COMMAND_SRC_RESET_SHIFT 13 2902 #define DMAE_COMMAND_DST_RESET (0x1<<14) 2903 #define DMAE_COMMAND_DST_RESET_SHIFT 14 2904 #define DMAE_COMMAND_E1HVN (0x3<<15) 2905 #define DMAE_COMMAND_E1HVN_SHIFT 15 2906 #define DMAE_COMMAND_DST_VN (0x3<<17) 2907 #define DMAE_COMMAND_DST_VN_SHIFT 17 2908 #define DMAE_COMMAND_C_FUNC (0x1<<19) 2909 #define DMAE_COMMAND_C_FUNC_SHIFT 19 2910 #define DMAE_COMMAND_ERR_POLICY (0x3<<20) 2911 #define DMAE_COMMAND_ERR_POLICY_SHIFT 20 2912 #define DMAE_COMMAND_RESERVED0 (0x3FF<<22) 2913 #define DMAE_COMMAND_RESERVED0_SHIFT 22 2914 u32 src_addr_lo; 2915 u32 src_addr_hi; 2916 u32 dst_addr_lo; 2917 u32 dst_addr_hi; 2918 #if defined(__BIG_ENDIAN) 2919 u16 opcode_iov; 2920 #define DMAE_COMMAND_SRC_VFID (0x3F<<0) 2921 #define DMAE_COMMAND_SRC_VFID_SHIFT 0 2922 #define DMAE_COMMAND_SRC_VFPF (0x1<<6) 2923 #define DMAE_COMMAND_SRC_VFPF_SHIFT 6 2924 #define DMAE_COMMAND_RESERVED1 (0x1<<7) 2925 #define DMAE_COMMAND_RESERVED1_SHIFT 7 2926 #define DMAE_COMMAND_DST_VFID (0x3F<<8) 2927 #define DMAE_COMMAND_DST_VFID_SHIFT 8 2928 #define DMAE_COMMAND_DST_VFPF (0x1<<14) 2929 #define DMAE_COMMAND_DST_VFPF_SHIFT 14 2930 #define DMAE_COMMAND_RESERVED2 (0x1<<15) 2931 #define DMAE_COMMAND_RESERVED2_SHIFT 15 2932 u16 len; 2933 #elif defined(__LITTLE_ENDIAN) 2934 u16 len; 2935 u16 opcode_iov; 2936 #define DMAE_COMMAND_SRC_VFID (0x3F<<0) 2937 #define DMAE_COMMAND_SRC_VFID_SHIFT 0 2938 #define DMAE_COMMAND_SRC_VFPF (0x1<<6) 2939 #define DMAE_COMMAND_SRC_VFPF_SHIFT 6 2940 #define DMAE_COMMAND_RESERVED1 (0x1<<7) 2941 #define DMAE_COMMAND_RESERVED1_SHIFT 7 2942 #define DMAE_COMMAND_DST_VFID (0x3F<<8) 2943 #define DMAE_COMMAND_DST_VFID_SHIFT 8 2944 #define DMAE_COMMAND_DST_VFPF (0x1<<14) 2945 #define DMAE_COMMAND_DST_VFPF_SHIFT 14 2946 #define DMAE_COMMAND_RESERVED2 (0x1<<15) 2947 #define DMAE_COMMAND_RESERVED2_SHIFT 15 2948 #endif 2949 u32 comp_addr_lo; 2950 u32 comp_addr_hi; 2951 u32 comp_val; 2952 u32 crc32; 2953 u32 crc32_c; 2954 #if defined(__BIG_ENDIAN) 2955 u16 crc16_c; 2956 u16 crc16; 2957 #elif defined(__LITTLE_ENDIAN) 2958 u16 crc16; 2959 u16 crc16_c; 2960 #endif 2961 #if defined(__BIG_ENDIAN) 2962 u16 reserved3; 2963 u16 crc_t10; 2964 #elif defined(__LITTLE_ENDIAN) 2965 u16 crc_t10; 2966 u16 reserved3; 2967 #endif 2968 #if defined(__BIG_ENDIAN) 2969 u16 xsum8; 2970 u16 xsum16; 2971 #elif defined(__LITTLE_ENDIAN) 2972 u16 xsum16; 2973 u16 xsum8; 2974 #endif 2975 }; 2976 2977 2978 /* 2979 * common data for all protocols 2980 */ 2981 struct doorbell_hdr { 2982 u8 header; 2983 #define DOORBELL_HDR_RX (0x1<<0) 2984 #define DOORBELL_HDR_RX_SHIFT 0 2985 #define DOORBELL_HDR_DB_TYPE (0x1<<1) 2986 #define DOORBELL_HDR_DB_TYPE_SHIFT 1 2987 #define DOORBELL_HDR_DPM_SIZE (0x3<<2) 2988 #define DOORBELL_HDR_DPM_SIZE_SHIFT 2 2989 #define DOORBELL_HDR_CONN_TYPE (0xF<<4) 2990 #define DOORBELL_HDR_CONN_TYPE_SHIFT 4 2991 }; 2992 2993 /* 2994 * Ethernet doorbell 2995 */ 2996 struct eth_tx_doorbell { 2997 #if defined(__BIG_ENDIAN) 2998 u16 npackets; 2999 u8 params; 3000 #define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0) 3001 #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0 3002 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6) 3003 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6 3004 #define ETH_TX_DOORBELL_SPARE (0x1<<7) 3005 #define ETH_TX_DOORBELL_SPARE_SHIFT 7 3006 struct doorbell_hdr hdr; 3007 #elif defined(__LITTLE_ENDIAN) 3008 struct doorbell_hdr hdr; 3009 u8 params; 3010 #define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0) 3011 #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0 3012 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6) 3013 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6 3014 #define ETH_TX_DOORBELL_SPARE (0x1<<7) 3015 #define ETH_TX_DOORBELL_SPARE_SHIFT 7 3016 u16 npackets; 3017 #endif 3018 }; 3019 3020 3021 /* 3022 * 3 lines. status block 3023 */ 3024 struct hc_status_block_e1x { 3025 __le16 index_values[HC_SB_MAX_INDICES_E1X]; 3026 __le16 running_index[HC_SB_MAX_SM]; 3027 __le32 rsrv[11]; 3028 }; 3029 3030 /* 3031 * host status block 3032 */ 3033 struct host_hc_status_block_e1x { 3034 struct hc_status_block_e1x sb; 3035 }; 3036 3037 3038 /* 3039 * 3 lines. status block 3040 */ 3041 struct hc_status_block_e2 { 3042 __le16 index_values[HC_SB_MAX_INDICES_E2]; 3043 __le16 running_index[HC_SB_MAX_SM]; 3044 __le32 reserved[11]; 3045 }; 3046 3047 /* 3048 * host status block 3049 */ 3050 struct host_hc_status_block_e2 { 3051 struct hc_status_block_e2 sb; 3052 }; 3053 3054 3055 /* 3056 * 5 lines. slow-path status block 3057 */ 3058 struct hc_sp_status_block { 3059 __le16 index_values[HC_SP_SB_MAX_INDICES]; 3060 __le16 running_index; 3061 __le16 rsrv; 3062 u32 rsrv1; 3063 }; 3064 3065 /* 3066 * host status block 3067 */ 3068 struct host_sp_status_block { 3069 struct atten_sp_status_block atten_status_block; 3070 struct hc_sp_status_block sp_sb; 3071 }; 3072 3073 3074 /* 3075 * IGU driver acknowledgment register 3076 */ 3077 struct igu_ack_register { 3078 #if defined(__BIG_ENDIAN) 3079 u16 sb_id_and_flags; 3080 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0) 3081 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0 3082 #define IGU_ACK_REGISTER_STORM_ID (0x7<<5) 3083 #define IGU_ACK_REGISTER_STORM_ID_SHIFT 5 3084 #define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8) 3085 #define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8 3086 #define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9) 3087 #define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9 3088 #define IGU_ACK_REGISTER_RESERVED (0x1F<<11) 3089 #define IGU_ACK_REGISTER_RESERVED_SHIFT 11 3090 u16 status_block_index; 3091 #elif defined(__LITTLE_ENDIAN) 3092 u16 status_block_index; 3093 u16 sb_id_and_flags; 3094 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0) 3095 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0 3096 #define IGU_ACK_REGISTER_STORM_ID (0x7<<5) 3097 #define IGU_ACK_REGISTER_STORM_ID_SHIFT 5 3098 #define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8) 3099 #define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8 3100 #define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9) 3101 #define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9 3102 #define IGU_ACK_REGISTER_RESERVED (0x1F<<11) 3103 #define IGU_ACK_REGISTER_RESERVED_SHIFT 11 3104 #endif 3105 }; 3106 3107 3108 /* 3109 * IGU driver acknowledgement register 3110 */ 3111 struct igu_backward_compatible { 3112 u32 sb_id_and_flags; 3113 #define IGU_BACKWARD_COMPATIBLE_SB_INDEX (0xFFFF<<0) 3114 #define IGU_BACKWARD_COMPATIBLE_SB_INDEX_SHIFT 0 3115 #define IGU_BACKWARD_COMPATIBLE_SB_SELECT (0x1F<<16) 3116 #define IGU_BACKWARD_COMPATIBLE_SB_SELECT_SHIFT 16 3117 #define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS (0x7<<21) 3118 #define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS_SHIFT 21 3119 #define IGU_BACKWARD_COMPATIBLE_BUPDATE (0x1<<24) 3120 #define IGU_BACKWARD_COMPATIBLE_BUPDATE_SHIFT 24 3121 #define IGU_BACKWARD_COMPATIBLE_ENABLE_INT (0x3<<25) 3122 #define IGU_BACKWARD_COMPATIBLE_ENABLE_INT_SHIFT 25 3123 #define IGU_BACKWARD_COMPATIBLE_RESERVED_0 (0x1F<<27) 3124 #define IGU_BACKWARD_COMPATIBLE_RESERVED_0_SHIFT 27 3125 u32 reserved_2; 3126 }; 3127 3128 3129 /* 3130 * IGU driver acknowledgement register 3131 */ 3132 struct igu_regular { 3133 u32 sb_id_and_flags; 3134 #define IGU_REGULAR_SB_INDEX (0xFFFFF<<0) 3135 #define IGU_REGULAR_SB_INDEX_SHIFT 0 3136 #define IGU_REGULAR_RESERVED0 (0x1<<20) 3137 #define IGU_REGULAR_RESERVED0_SHIFT 20 3138 #define IGU_REGULAR_SEGMENT_ACCESS (0x7<<21) 3139 #define IGU_REGULAR_SEGMENT_ACCESS_SHIFT 21 3140 #define IGU_REGULAR_BUPDATE (0x1<<24) 3141 #define IGU_REGULAR_BUPDATE_SHIFT 24 3142 #define IGU_REGULAR_ENABLE_INT (0x3<<25) 3143 #define IGU_REGULAR_ENABLE_INT_SHIFT 25 3144 #define IGU_REGULAR_RESERVED_1 (0x1<<27) 3145 #define IGU_REGULAR_RESERVED_1_SHIFT 27 3146 #define IGU_REGULAR_CLEANUP_TYPE (0x3<<28) 3147 #define IGU_REGULAR_CLEANUP_TYPE_SHIFT 28 3148 #define IGU_REGULAR_CLEANUP_SET (0x1<<30) 3149 #define IGU_REGULAR_CLEANUP_SET_SHIFT 30 3150 #define IGU_REGULAR_BCLEANUP (0x1<<31) 3151 #define IGU_REGULAR_BCLEANUP_SHIFT 31 3152 u32 reserved_2; 3153 }; 3154 3155 /* 3156 * IGU driver acknowledgement register 3157 */ 3158 union igu_consprod_reg { 3159 struct igu_regular regular; 3160 struct igu_backward_compatible backward_compatible; 3161 }; 3162 3163 3164 /* 3165 * Igu control commands 3166 */ 3167 enum igu_ctrl_cmd { 3168 IGU_CTRL_CMD_TYPE_RD, 3169 IGU_CTRL_CMD_TYPE_WR, 3170 MAX_IGU_CTRL_CMD 3171 }; 3172 3173 3174 /* 3175 * Control register for the IGU command register 3176 */ 3177 struct igu_ctrl_reg { 3178 u32 ctrl_data; 3179 #define IGU_CTRL_REG_ADDRESS (0xFFF<<0) 3180 #define IGU_CTRL_REG_ADDRESS_SHIFT 0 3181 #define IGU_CTRL_REG_FID (0x7F<<12) 3182 #define IGU_CTRL_REG_FID_SHIFT 12 3183 #define IGU_CTRL_REG_RESERVED (0x1<<19) 3184 #define IGU_CTRL_REG_RESERVED_SHIFT 19 3185 #define IGU_CTRL_REG_TYPE (0x1<<20) 3186 #define IGU_CTRL_REG_TYPE_SHIFT 20 3187 #define IGU_CTRL_REG_UNUSED (0x7FF<<21) 3188 #define IGU_CTRL_REG_UNUSED_SHIFT 21 3189 }; 3190 3191 3192 /* 3193 * Igu interrupt command 3194 */ 3195 enum igu_int_cmd { 3196 IGU_INT_ENABLE, 3197 IGU_INT_DISABLE, 3198 IGU_INT_NOP, 3199 IGU_INT_NOP2, 3200 MAX_IGU_INT_CMD 3201 }; 3202 3203 3204 /* 3205 * Igu segments 3206 */ 3207 enum igu_seg_access { 3208 IGU_SEG_ACCESS_NORM, 3209 IGU_SEG_ACCESS_DEF, 3210 IGU_SEG_ACCESS_ATTN, 3211 MAX_IGU_SEG_ACCESS 3212 }; 3213 3214 3215 /* 3216 * Parser parsing flags field 3217 */ 3218 struct parsing_flags { 3219 __le16 flags; 3220 #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE (0x1<<0) 3221 #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE_SHIFT 0 3222 #define PARSING_FLAGS_VLAN (0x1<<1) 3223 #define PARSING_FLAGS_VLAN_SHIFT 1 3224 #define PARSING_FLAGS_EXTRA_VLAN (0x1<<2) 3225 #define PARSING_FLAGS_EXTRA_VLAN_SHIFT 2 3226 #define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL (0x3<<3) 3227 #define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT 3 3228 #define PARSING_FLAGS_IP_OPTIONS (0x1<<5) 3229 #define PARSING_FLAGS_IP_OPTIONS_SHIFT 5 3230 #define PARSING_FLAGS_FRAGMENTATION_STATUS (0x1<<6) 3231 #define PARSING_FLAGS_FRAGMENTATION_STATUS_SHIFT 6 3232 #define PARSING_FLAGS_OVER_IP_PROTOCOL (0x3<<7) 3233 #define PARSING_FLAGS_OVER_IP_PROTOCOL_SHIFT 7 3234 #define PARSING_FLAGS_PURE_ACK_INDICATION (0x1<<9) 3235 #define PARSING_FLAGS_PURE_ACK_INDICATION_SHIFT 9 3236 #define PARSING_FLAGS_TCP_OPTIONS_EXIST (0x1<<10) 3237 #define PARSING_FLAGS_TCP_OPTIONS_EXIST_SHIFT 10 3238 #define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG (0x1<<11) 3239 #define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG_SHIFT 11 3240 #define PARSING_FLAGS_CONNECTION_MATCH (0x1<<12) 3241 #define PARSING_FLAGS_CONNECTION_MATCH_SHIFT 12 3242 #define PARSING_FLAGS_LLC_SNAP (0x1<<13) 3243 #define PARSING_FLAGS_LLC_SNAP_SHIFT 13 3244 #define PARSING_FLAGS_RESERVED0 (0x3<<14) 3245 #define PARSING_FLAGS_RESERVED0_SHIFT 14 3246 }; 3247 3248 3249 /* 3250 * Parsing flags for TCP ACK type 3251 */ 3252 enum prs_flags_ack_type { 3253 PRS_FLAG_PUREACK_PIGGY, 3254 PRS_FLAG_PUREACK_PURE, 3255 MAX_PRS_FLAGS_ACK_TYPE 3256 }; 3257 3258 3259 /* 3260 * Parsing flags for Ethernet address type 3261 */ 3262 enum prs_flags_eth_addr_type { 3263 PRS_FLAG_ETHTYPE_NON_UNICAST, 3264 PRS_FLAG_ETHTYPE_UNICAST, 3265 MAX_PRS_FLAGS_ETH_ADDR_TYPE 3266 }; 3267 3268 3269 /* 3270 * Parsing flags for over-ethernet protocol 3271 */ 3272 enum prs_flags_over_eth { 3273 PRS_FLAG_OVERETH_UNKNOWN, 3274 PRS_FLAG_OVERETH_IPV4, 3275 PRS_FLAG_OVERETH_IPV6, 3276 PRS_FLAG_OVERETH_LLCSNAP_UNKNOWN, 3277 MAX_PRS_FLAGS_OVER_ETH 3278 }; 3279 3280 3281 /* 3282 * Parsing flags for over-IP protocol 3283 */ 3284 enum prs_flags_over_ip { 3285 PRS_FLAG_OVERIP_UNKNOWN, 3286 PRS_FLAG_OVERIP_TCP, 3287 PRS_FLAG_OVERIP_UDP, 3288 MAX_PRS_FLAGS_OVER_IP 3289 }; 3290 3291 3292 /* 3293 * SDM operation gen command (generate aggregative interrupt) 3294 */ 3295 struct sdm_op_gen { 3296 __le32 command; 3297 #define SDM_OP_GEN_COMP_PARAM (0x1F<<0) 3298 #define SDM_OP_GEN_COMP_PARAM_SHIFT 0 3299 #define SDM_OP_GEN_COMP_TYPE (0x7<<5) 3300 #define SDM_OP_GEN_COMP_TYPE_SHIFT 5 3301 #define SDM_OP_GEN_AGG_VECT_IDX (0xFF<<8) 3302 #define SDM_OP_GEN_AGG_VECT_IDX_SHIFT 8 3303 #define SDM_OP_GEN_AGG_VECT_IDX_VALID (0x1<<16) 3304 #define SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT 16 3305 #define SDM_OP_GEN_RESERVED (0x7FFF<<17) 3306 #define SDM_OP_GEN_RESERVED_SHIFT 17 3307 }; 3308 3309 3310 /* 3311 * Timers connection context 3312 */ 3313 struct timers_block_context { 3314 u32 __reserved_0; 3315 u32 __reserved_1; 3316 u32 __reserved_2; 3317 u32 flags; 3318 #define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS (0x3<<0) 3319 #define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS_SHIFT 0 3320 #define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG (0x1<<2) 3321 #define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG_SHIFT 2 3322 #define __TIMERS_BLOCK_CONTEXT_RESERVED0 (0x1FFFFFFF<<3) 3323 #define __TIMERS_BLOCK_CONTEXT_RESERVED0_SHIFT 3 3324 }; 3325 3326 3327 /* 3328 * The eth aggregative context of Tstorm 3329 */ 3330 struct tstorm_eth_ag_context { 3331 u32 __reserved0[14]; 3332 }; 3333 3334 3335 /* 3336 * The eth aggregative context of Ustorm 3337 */ 3338 struct ustorm_eth_ag_context { 3339 u32 __reserved0; 3340 #if defined(__BIG_ENDIAN) 3341 u8 cdu_usage; 3342 u8 __reserved2; 3343 u16 __reserved1; 3344 #elif defined(__LITTLE_ENDIAN) 3345 u16 __reserved1; 3346 u8 __reserved2; 3347 u8 cdu_usage; 3348 #endif 3349 u32 __reserved3[6]; 3350 }; 3351 3352 3353 /* 3354 * The eth aggregative context of Xstorm 3355 */ 3356 struct xstorm_eth_ag_context { 3357 u32 reserved0; 3358 #if defined(__BIG_ENDIAN) 3359 u8 cdu_reserved; 3360 u8 reserved2; 3361 u16 reserved1; 3362 #elif defined(__LITTLE_ENDIAN) 3363 u16 reserved1; 3364 u8 reserved2; 3365 u8 cdu_reserved; 3366 #endif 3367 u32 reserved3[30]; 3368 }; 3369 3370 3371 /* 3372 * doorbell message sent to the chip 3373 */ 3374 struct doorbell { 3375 #if defined(__BIG_ENDIAN) 3376 u16 zero_fill2; 3377 u8 zero_fill1; 3378 struct doorbell_hdr header; 3379 #elif defined(__LITTLE_ENDIAN) 3380 struct doorbell_hdr header; 3381 u8 zero_fill1; 3382 u16 zero_fill2; 3383 #endif 3384 }; 3385 3386 3387 /* 3388 * doorbell message sent to the chip 3389 */ 3390 struct doorbell_set_prod { 3391 #if defined(__BIG_ENDIAN) 3392 u16 prod; 3393 u8 zero_fill1; 3394 struct doorbell_hdr header; 3395 #elif defined(__LITTLE_ENDIAN) 3396 struct doorbell_hdr header; 3397 u8 zero_fill1; 3398 u16 prod; 3399 #endif 3400 }; 3401 3402 3403 struct regpair { 3404 __le32 lo; 3405 __le32 hi; 3406 }; 3407 3408 struct regpair_native { 3409 u32 lo; 3410 u32 hi; 3411 }; 3412 3413 /* 3414 * Classify rule opcodes in E2/E3 3415 */ 3416 enum classify_rule { 3417 CLASSIFY_RULE_OPCODE_MAC, 3418 CLASSIFY_RULE_OPCODE_VLAN, 3419 CLASSIFY_RULE_OPCODE_PAIR, 3420 MAX_CLASSIFY_RULE 3421 }; 3422 3423 3424 /* 3425 * Classify rule types in E2/E3 3426 */ 3427 enum classify_rule_action_type { 3428 CLASSIFY_RULE_REMOVE, 3429 CLASSIFY_RULE_ADD, 3430 MAX_CLASSIFY_RULE_ACTION_TYPE 3431 }; 3432 3433 3434 /* 3435 * client init ramrod data 3436 */ 3437 struct client_init_general_data { 3438 u8 client_id; 3439 u8 statistics_counter_id; 3440 u8 statistics_en_flg; 3441 u8 is_fcoe_flg; 3442 u8 activate_flg; 3443 u8 sp_client_id; 3444 __le16 mtu; 3445 u8 statistics_zero_flg; 3446 u8 func_id; 3447 u8 cos; 3448 u8 traffic_type; 3449 u32 reserved0; 3450 }; 3451 3452 3453 /* 3454 * client init rx data 3455 */ 3456 struct client_init_rx_data { 3457 u8 tpa_en; 3458 #define CLIENT_INIT_RX_DATA_TPA_EN_IPV4 (0x1<<0) 3459 #define CLIENT_INIT_RX_DATA_TPA_EN_IPV4_SHIFT 0 3460 #define CLIENT_INIT_RX_DATA_TPA_EN_IPV6 (0x1<<1) 3461 #define CLIENT_INIT_RX_DATA_TPA_EN_IPV6_SHIFT 1 3462 #define CLIENT_INIT_RX_DATA_TPA_MODE (0x1<<2) 3463 #define CLIENT_INIT_RX_DATA_TPA_MODE_SHIFT 2 3464 #define CLIENT_INIT_RX_DATA_RESERVED5 (0x1F<<3) 3465 #define CLIENT_INIT_RX_DATA_RESERVED5_SHIFT 3 3466 u8 vmqueue_mode_en_flg; 3467 u8 extra_data_over_sgl_en_flg; 3468 u8 cache_line_alignment_log_size; 3469 u8 enable_dynamic_hc; 3470 u8 max_sges_for_packet; 3471 u8 client_qzone_id; 3472 u8 drop_ip_cs_err_flg; 3473 u8 drop_tcp_cs_err_flg; 3474 u8 drop_ttl0_flg; 3475 u8 drop_udp_cs_err_flg; 3476 u8 inner_vlan_removal_enable_flg; 3477 u8 outer_vlan_removal_enable_flg; 3478 u8 status_block_id; 3479 u8 rx_sb_index_number; 3480 u8 dont_verify_rings_pause_thr_flg; 3481 u8 max_tpa_queues; 3482 u8 silent_vlan_removal_flg; 3483 __le16 max_bytes_on_bd; 3484 __le16 sge_buff_size; 3485 u8 approx_mcast_engine_id; 3486 u8 rss_engine_id; 3487 struct regpair bd_page_base; 3488 struct regpair sge_page_base; 3489 struct regpair cqe_page_base; 3490 u8 is_leading_rss; 3491 u8 is_approx_mcast; 3492 __le16 max_agg_size; 3493 __le16 state; 3494 #define CLIENT_INIT_RX_DATA_UCAST_DROP_ALL (0x1<<0) 3495 #define CLIENT_INIT_RX_DATA_UCAST_DROP_ALL_SHIFT 0 3496 #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL (0x1<<1) 3497 #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL_SHIFT 1 3498 #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED (0x1<<2) 3499 #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED_SHIFT 2 3500 #define CLIENT_INIT_RX_DATA_MCAST_DROP_ALL (0x1<<3) 3501 #define CLIENT_INIT_RX_DATA_MCAST_DROP_ALL_SHIFT 3 3502 #define CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL (0x1<<4) 3503 #define CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL_SHIFT 4 3504 #define CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL (0x1<<5) 3505 #define CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL_SHIFT 5 3506 #define CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN (0x1<<6) 3507 #define CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN_SHIFT 6 3508 #define CLIENT_INIT_RX_DATA_RESERVED2 (0x1FF<<7) 3509 #define CLIENT_INIT_RX_DATA_RESERVED2_SHIFT 7 3510 __le16 cqe_pause_thr_low; 3511 __le16 cqe_pause_thr_high; 3512 __le16 bd_pause_thr_low; 3513 __le16 bd_pause_thr_high; 3514 __le16 sge_pause_thr_low; 3515 __le16 sge_pause_thr_high; 3516 __le16 rx_cos_mask; 3517 __le16 silent_vlan_value; 3518 __le16 silent_vlan_mask; 3519 __le32 reserved6[2]; 3520 }; 3521 3522 /* 3523 * client init tx data 3524 */ 3525 struct client_init_tx_data { 3526 u8 enforce_security_flg; 3527 u8 tx_status_block_id; 3528 u8 tx_sb_index_number; 3529 u8 tss_leading_client_id; 3530 u8 tx_switching_flg; 3531 u8 anti_spoofing_flg; 3532 __le16 default_vlan; 3533 struct regpair tx_bd_page_base; 3534 __le16 state; 3535 #define CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL (0x1<<0) 3536 #define CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL_SHIFT 0 3537 #define CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL (0x1<<1) 3538 #define CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL_SHIFT 1 3539 #define CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL (0x1<<2) 3540 #define CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL_SHIFT 2 3541 #define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN (0x1<<3) 3542 #define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN_SHIFT 3 3543 #define CLIENT_INIT_TX_DATA_RESERVED0 (0xFFF<<4) 3544 #define CLIENT_INIT_TX_DATA_RESERVED0_SHIFT 4 3545 u8 default_vlan_flg; 3546 u8 force_default_pri_flg; 3547 u8 tunnel_lso_inc_ip_id; 3548 u8 refuse_outband_vlan_flg; 3549 u8 tunnel_non_lso_pcsum_location; 3550 u8 reserved1; 3551 }; 3552 3553 /* 3554 * client init ramrod data 3555 */ 3556 struct client_init_ramrod_data { 3557 struct client_init_general_data general; 3558 struct client_init_rx_data rx; 3559 struct client_init_tx_data tx; 3560 }; 3561 3562 3563 /* 3564 * client update ramrod data 3565 */ 3566 struct client_update_ramrod_data { 3567 u8 client_id; 3568 u8 func_id; 3569 u8 inner_vlan_removal_enable_flg; 3570 u8 inner_vlan_removal_change_flg; 3571 u8 outer_vlan_removal_enable_flg; 3572 u8 outer_vlan_removal_change_flg; 3573 u8 anti_spoofing_enable_flg; 3574 u8 anti_spoofing_change_flg; 3575 u8 activate_flg; 3576 u8 activate_change_flg; 3577 __le16 default_vlan; 3578 u8 default_vlan_enable_flg; 3579 u8 default_vlan_change_flg; 3580 __le16 silent_vlan_value; 3581 __le16 silent_vlan_mask; 3582 u8 silent_vlan_removal_flg; 3583 u8 silent_vlan_change_flg; 3584 u8 refuse_outband_vlan_flg; 3585 u8 refuse_outband_vlan_change_flg; 3586 u8 tx_switching_flg; 3587 u8 tx_switching_change_flg; 3588 __le32 reserved1; 3589 __le32 echo; 3590 }; 3591 3592 3593 /* 3594 * The eth storm context of Cstorm 3595 */ 3596 struct cstorm_eth_st_context { 3597 u32 __reserved0[4]; 3598 }; 3599 3600 3601 struct double_regpair { 3602 u32 regpair0_lo; 3603 u32 regpair0_hi; 3604 u32 regpair1_lo; 3605 u32 regpair1_hi; 3606 }; 3607 3608 3609 /* 3610 * Ethernet address typesm used in ethernet tx BDs 3611 */ 3612 enum eth_addr_type { 3613 UNKNOWN_ADDRESS, 3614 UNICAST_ADDRESS, 3615 MULTICAST_ADDRESS, 3616 BROADCAST_ADDRESS, 3617 MAX_ETH_ADDR_TYPE 3618 }; 3619 3620 3621 /* 3622 * 3623 */ 3624 struct eth_classify_cmd_header { 3625 u8 cmd_general_data; 3626 #define ETH_CLASSIFY_CMD_HEADER_RX_CMD (0x1<<0) 3627 #define ETH_CLASSIFY_CMD_HEADER_RX_CMD_SHIFT 0 3628 #define ETH_CLASSIFY_CMD_HEADER_TX_CMD (0x1<<1) 3629 #define ETH_CLASSIFY_CMD_HEADER_TX_CMD_SHIFT 1 3630 #define ETH_CLASSIFY_CMD_HEADER_OPCODE (0x3<<2) 3631 #define ETH_CLASSIFY_CMD_HEADER_OPCODE_SHIFT 2 3632 #define ETH_CLASSIFY_CMD_HEADER_IS_ADD (0x1<<4) 3633 #define ETH_CLASSIFY_CMD_HEADER_IS_ADD_SHIFT 4 3634 #define ETH_CLASSIFY_CMD_HEADER_RESERVED0 (0x7<<5) 3635 #define ETH_CLASSIFY_CMD_HEADER_RESERVED0_SHIFT 5 3636 u8 func_id; 3637 u8 client_id; 3638 u8 reserved1; 3639 }; 3640 3641 3642 /* 3643 * header for eth classification config ramrod 3644 */ 3645 struct eth_classify_header { 3646 u8 rule_cnt; 3647 u8 reserved0; 3648 __le16 reserved1; 3649 __le32 echo; 3650 }; 3651 3652 3653 /* 3654 * Command for adding/removing a MAC classification rule 3655 */ 3656 struct eth_classify_mac_cmd { 3657 struct eth_classify_cmd_header header; 3658 __le16 reserved0; 3659 __le16 inner_mac; 3660 __le16 mac_lsb; 3661 __le16 mac_mid; 3662 __le16 mac_msb; 3663 __le16 reserved1; 3664 }; 3665 3666 3667 /* 3668 * Command for adding/removing a MAC-VLAN pair classification rule 3669 */ 3670 struct eth_classify_pair_cmd { 3671 struct eth_classify_cmd_header header; 3672 __le16 reserved0; 3673 __le16 inner_mac; 3674 __le16 mac_lsb; 3675 __le16 mac_mid; 3676 __le16 mac_msb; 3677 __le16 vlan; 3678 }; 3679 3680 3681 /* 3682 * Command for adding/removing a VLAN classification rule 3683 */ 3684 struct eth_classify_vlan_cmd { 3685 struct eth_classify_cmd_header header; 3686 __le32 reserved0; 3687 __le32 reserved1; 3688 __le16 reserved2; 3689 __le16 vlan; 3690 }; 3691 3692 /* 3693 * union for eth classification rule 3694 */ 3695 union eth_classify_rule_cmd { 3696 struct eth_classify_mac_cmd mac; 3697 struct eth_classify_vlan_cmd vlan; 3698 struct eth_classify_pair_cmd pair; 3699 }; 3700 3701 /* 3702 * parameters for eth classification configuration ramrod 3703 */ 3704 struct eth_classify_rules_ramrod_data { 3705 struct eth_classify_header header; 3706 union eth_classify_rule_cmd rules[CLASSIFY_RULES_COUNT]; 3707 }; 3708 3709 3710 /* 3711 * The data contain client ID need to the ramrod 3712 */ 3713 struct eth_common_ramrod_data { 3714 __le32 client_id; 3715 __le32 reserved1; 3716 }; 3717 3718 3719 /* 3720 * The eth storm context of Ustorm 3721 */ 3722 struct ustorm_eth_st_context { 3723 u32 reserved0[52]; 3724 }; 3725 3726 /* 3727 * The eth storm context of Tstorm 3728 */ 3729 struct tstorm_eth_st_context { 3730 u32 __reserved0[28]; 3731 }; 3732 3733 /* 3734 * The eth storm context of Xstorm 3735 */ 3736 struct xstorm_eth_st_context { 3737 u32 reserved0[60]; 3738 }; 3739 3740 /* 3741 * Ethernet connection context 3742 */ 3743 struct eth_context { 3744 struct ustorm_eth_st_context ustorm_st_context; 3745 struct tstorm_eth_st_context tstorm_st_context; 3746 struct xstorm_eth_ag_context xstorm_ag_context; 3747 struct tstorm_eth_ag_context tstorm_ag_context; 3748 struct cstorm_eth_ag_context cstorm_ag_context; 3749 struct ustorm_eth_ag_context ustorm_ag_context; 3750 struct timers_block_context timers_context; 3751 struct xstorm_eth_st_context xstorm_st_context; 3752 struct cstorm_eth_st_context cstorm_st_context; 3753 }; 3754 3755 3756 /* 3757 * union for sgl and raw data. 3758 */ 3759 union eth_sgl_or_raw_data { 3760 __le16 sgl[8]; 3761 u32 raw_data[4]; 3762 }; 3763 3764 /* 3765 * eth FP end aggregation CQE parameters struct 3766 */ 3767 struct eth_end_agg_rx_cqe { 3768 u8 type_error_flags; 3769 #define ETH_END_AGG_RX_CQE_TYPE (0x3<<0) 3770 #define ETH_END_AGG_RX_CQE_TYPE_SHIFT 0 3771 #define ETH_END_AGG_RX_CQE_SGL_RAW_SEL (0x1<<2) 3772 #define ETH_END_AGG_RX_CQE_SGL_RAW_SEL_SHIFT 2 3773 #define ETH_END_AGG_RX_CQE_RESERVED0 (0x1F<<3) 3774 #define ETH_END_AGG_RX_CQE_RESERVED0_SHIFT 3 3775 u8 reserved1; 3776 u8 queue_index; 3777 u8 reserved2; 3778 __le32 timestamp_delta; 3779 __le16 num_of_coalesced_segs; 3780 __le16 pkt_len; 3781 u8 pure_ack_count; 3782 u8 reserved3; 3783 __le16 reserved4; 3784 union eth_sgl_or_raw_data sgl_or_raw_data; 3785 __le32 reserved5[8]; 3786 }; 3787 3788 3789 /* 3790 * regular eth FP CQE parameters struct 3791 */ 3792 struct eth_fast_path_rx_cqe { 3793 u8 type_error_flags; 3794 #define ETH_FAST_PATH_RX_CQE_TYPE (0x3<<0) 3795 #define ETH_FAST_PATH_RX_CQE_TYPE_SHIFT 0 3796 #define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL (0x1<<2) 3797 #define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL_SHIFT 2 3798 #define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG (0x1<<3) 3799 #define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG_SHIFT 3 3800 #define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG (0x1<<4) 3801 #define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG_SHIFT 4 3802 #define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG (0x1<<5) 3803 #define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG_SHIFT 5 3804 #define ETH_FAST_PATH_RX_CQE_RESERVED0 (0x3<<6) 3805 #define ETH_FAST_PATH_RX_CQE_RESERVED0_SHIFT 6 3806 u8 status_flags; 3807 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE (0x7<<0) 3808 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE_SHIFT 0 3809 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG (0x1<<3) 3810 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG_SHIFT 3 3811 #define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG (0x1<<4) 3812 #define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG_SHIFT 4 3813 #define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG (0x1<<5) 3814 #define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG_SHIFT 5 3815 #define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG (0x1<<6) 3816 #define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG_SHIFT 6 3817 #define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG (0x1<<7) 3818 #define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG_SHIFT 7 3819 u8 queue_index; 3820 u8 placement_offset; 3821 __le32 rss_hash_result; 3822 __le16 vlan_tag; 3823 __le16 pkt_len_or_gro_seg_len; 3824 __le16 len_on_bd; 3825 struct parsing_flags pars_flags; 3826 union eth_sgl_or_raw_data sgl_or_raw_data; 3827 __le32 reserved1[7]; 3828 u32 marker; 3829 }; 3830 3831 3832 /* 3833 * Command for setting classification flags for a client 3834 */ 3835 struct eth_filter_rules_cmd { 3836 u8 cmd_general_data; 3837 #define ETH_FILTER_RULES_CMD_RX_CMD (0x1<<0) 3838 #define ETH_FILTER_RULES_CMD_RX_CMD_SHIFT 0 3839 #define ETH_FILTER_RULES_CMD_TX_CMD (0x1<<1) 3840 #define ETH_FILTER_RULES_CMD_TX_CMD_SHIFT 1 3841 #define ETH_FILTER_RULES_CMD_RESERVED0 (0x3F<<2) 3842 #define ETH_FILTER_RULES_CMD_RESERVED0_SHIFT 2 3843 u8 func_id; 3844 u8 client_id; 3845 u8 reserved1; 3846 __le16 state; 3847 #define ETH_FILTER_RULES_CMD_UCAST_DROP_ALL (0x1<<0) 3848 #define ETH_FILTER_RULES_CMD_UCAST_DROP_ALL_SHIFT 0 3849 #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL (0x1<<1) 3850 #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL_SHIFT 1 3851 #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED (0x1<<2) 3852 #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED_SHIFT 2 3853 #define ETH_FILTER_RULES_CMD_MCAST_DROP_ALL (0x1<<3) 3854 #define ETH_FILTER_RULES_CMD_MCAST_DROP_ALL_SHIFT 3 3855 #define ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL (0x1<<4) 3856 #define ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL_SHIFT 4 3857 #define ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL (0x1<<5) 3858 #define ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL_SHIFT 5 3859 #define ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN (0x1<<6) 3860 #define ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN_SHIFT 6 3861 #define ETH_FILTER_RULES_CMD_RESERVED2 (0x1FF<<7) 3862 #define ETH_FILTER_RULES_CMD_RESERVED2_SHIFT 7 3863 __le16 reserved3; 3864 struct regpair reserved4; 3865 }; 3866 3867 3868 /* 3869 * parameters for eth classification filters ramrod 3870 */ 3871 struct eth_filter_rules_ramrod_data { 3872 struct eth_classify_header header; 3873 struct eth_filter_rules_cmd rules[FILTER_RULES_COUNT]; 3874 }; 3875 3876 3877 /* 3878 * parameters for eth classification configuration ramrod 3879 */ 3880 struct eth_general_rules_ramrod_data { 3881 struct eth_classify_header header; 3882 union eth_classify_rule_cmd rules[CLASSIFY_RULES_COUNT]; 3883 }; 3884 3885 3886 /* 3887 * The data for Halt ramrod 3888 */ 3889 struct eth_halt_ramrod_data { 3890 __le32 client_id; 3891 __le32 reserved0; 3892 }; 3893 3894 3895 /* 3896 * destination and source mac address. 3897 */ 3898 struct eth_mac_addresses { 3899 #if defined(__BIG_ENDIAN) 3900 __le16 dst_mid; 3901 __le16 dst_lo; 3902 #elif defined(__LITTLE_ENDIAN) 3903 __le16 dst_lo; 3904 __le16 dst_mid; 3905 #endif 3906 #if defined(__BIG_ENDIAN) 3907 __le16 src_lo; 3908 __le16 dst_hi; 3909 #elif defined(__LITTLE_ENDIAN) 3910 __le16 dst_hi; 3911 __le16 src_lo; 3912 #endif 3913 #if defined(__BIG_ENDIAN) 3914 __le16 src_hi; 3915 __le16 src_mid; 3916 #elif defined(__LITTLE_ENDIAN) 3917 __le16 src_mid; 3918 __le16 src_hi; 3919 #endif 3920 }; 3921 3922 /* tunneling related data */ 3923 struct eth_tunnel_data { 3924 #if defined(__BIG_ENDIAN) 3925 __le16 dst_mid; 3926 __le16 dst_lo; 3927 #elif defined(__LITTLE_ENDIAN) 3928 __le16 dst_lo; 3929 __le16 dst_mid; 3930 #endif 3931 #if defined(__BIG_ENDIAN) 3932 __le16 reserved0; 3933 __le16 dst_hi; 3934 #elif defined(__LITTLE_ENDIAN) 3935 __le16 dst_hi; 3936 __le16 reserved0; 3937 #endif 3938 #if defined(__BIG_ENDIAN) 3939 u8 reserved1; 3940 u8 ip_hdr_start_inner_w; 3941 __le16 pseudo_csum; 3942 #elif defined(__LITTLE_ENDIAN) 3943 __le16 pseudo_csum; 3944 u8 ip_hdr_start_inner_w; 3945 u8 reserved1; 3946 #endif 3947 }; 3948 3949 /* union for mac addresses and for tunneling data. 3950 * considered as tunneling data only if (tunnel_exist == 1). 3951 */ 3952 union eth_mac_addr_or_tunnel_data { 3953 struct eth_mac_addresses mac_addr; 3954 struct eth_tunnel_data tunnel_data; 3955 }; 3956 3957 /*Command for setting multicast classification for a client */ 3958 struct eth_multicast_rules_cmd { 3959 u8 cmd_general_data; 3960 #define ETH_MULTICAST_RULES_CMD_RX_CMD (0x1<<0) 3961 #define ETH_MULTICAST_RULES_CMD_RX_CMD_SHIFT 0 3962 #define ETH_MULTICAST_RULES_CMD_TX_CMD (0x1<<1) 3963 #define ETH_MULTICAST_RULES_CMD_TX_CMD_SHIFT 1 3964 #define ETH_MULTICAST_RULES_CMD_IS_ADD (0x1<<2) 3965 #define ETH_MULTICAST_RULES_CMD_IS_ADD_SHIFT 2 3966 #define ETH_MULTICAST_RULES_CMD_RESERVED0 (0x1F<<3) 3967 #define ETH_MULTICAST_RULES_CMD_RESERVED0_SHIFT 3 3968 u8 func_id; 3969 u8 bin_id; 3970 u8 engine_id; 3971 __le32 reserved2; 3972 struct regpair reserved3; 3973 }; 3974 3975 /* 3976 * parameters for multicast classification ramrod 3977 */ 3978 struct eth_multicast_rules_ramrod_data { 3979 struct eth_classify_header header; 3980 struct eth_multicast_rules_cmd rules[MULTICAST_RULES_COUNT]; 3981 }; 3982 3983 /* 3984 * Place holder for ramrods protocol specific data 3985 */ 3986 struct ramrod_data { 3987 __le32 data_lo; 3988 __le32 data_hi; 3989 }; 3990 3991 /* 3992 * union for ramrod data for Ethernet protocol (CQE) (force size of 16 bits) 3993 */ 3994 union eth_ramrod_data { 3995 struct ramrod_data general; 3996 }; 3997 3998 3999 /* 4000 * RSS toeplitz hash type, as reported in CQE 4001 */ 4002 enum eth_rss_hash_type { 4003 DEFAULT_HASH_TYPE, 4004 IPV4_HASH_TYPE, 4005 TCP_IPV4_HASH_TYPE, 4006 IPV6_HASH_TYPE, 4007 TCP_IPV6_HASH_TYPE, 4008 VLAN_PRI_HASH_TYPE, 4009 E1HOV_PRI_HASH_TYPE, 4010 DSCP_HASH_TYPE, 4011 MAX_ETH_RSS_HASH_TYPE 4012 }; 4013 4014 4015 /* 4016 * Ethernet RSS mode 4017 */ 4018 enum eth_rss_mode { 4019 ETH_RSS_MODE_DISABLED, 4020 ETH_RSS_MODE_REGULAR, 4021 ETH_RSS_MODE_VLAN_PRI, 4022 ETH_RSS_MODE_E1HOV_PRI, 4023 ETH_RSS_MODE_IP_DSCP, 4024 MAX_ETH_RSS_MODE 4025 }; 4026 4027 4028 /* 4029 * parameters for RSS update ramrod (E2) 4030 */ 4031 struct eth_rss_update_ramrod_data { 4032 u8 rss_engine_id; 4033 u8 capabilities; 4034 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY (0x1<<0) 4035 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY_SHIFT 0 4036 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY (0x1<<1) 4037 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY_SHIFT 1 4038 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY (0x1<<2) 4039 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY_SHIFT 2 4040 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY (0x1<<3) 4041 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY_SHIFT 3 4042 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY (0x1<<4) 4043 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY_SHIFT 4 4044 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY (0x1<<5) 4045 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY_SHIFT 5 4046 #define ETH_RSS_UPDATE_RAMROD_DATA_EN_5_TUPLE_CAPABILITY (0x1<<6) 4047 #define ETH_RSS_UPDATE_RAMROD_DATA_EN_5_TUPLE_CAPABILITY_SHIFT 6 4048 #define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY (0x1<<7) 4049 #define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY_SHIFT 7 4050 u8 rss_result_mask; 4051 u8 rss_mode; 4052 __le16 udp_4tuple_dst_port_mask; 4053 __le16 udp_4tuple_dst_port_value; 4054 u8 indirection_table[T_ETH_INDIRECTION_TABLE_SIZE]; 4055 __le32 rss_key[T_ETH_RSS_KEY]; 4056 __le32 echo; 4057 __le32 reserved3; 4058 }; 4059 4060 4061 /* 4062 * The eth Rx Buffer Descriptor 4063 */ 4064 struct eth_rx_bd { 4065 __le32 addr_lo; 4066 __le32 addr_hi; 4067 }; 4068 4069 4070 /* 4071 * Eth Rx Cqe structure- general structure for ramrods 4072 */ 4073 struct common_ramrod_eth_rx_cqe { 4074 u8 ramrod_type; 4075 #define COMMON_RAMROD_ETH_RX_CQE_TYPE (0x3<<0) 4076 #define COMMON_RAMROD_ETH_RX_CQE_TYPE_SHIFT 0 4077 #define COMMON_RAMROD_ETH_RX_CQE_ERROR (0x1<<2) 4078 #define COMMON_RAMROD_ETH_RX_CQE_ERROR_SHIFT 2 4079 #define COMMON_RAMROD_ETH_RX_CQE_RESERVED0 (0x1F<<3) 4080 #define COMMON_RAMROD_ETH_RX_CQE_RESERVED0_SHIFT 3 4081 u8 conn_type; 4082 __le16 reserved1; 4083 __le32 conn_and_cmd_data; 4084 #define COMMON_RAMROD_ETH_RX_CQE_CID (0xFFFFFF<<0) 4085 #define COMMON_RAMROD_ETH_RX_CQE_CID_SHIFT 0 4086 #define COMMON_RAMROD_ETH_RX_CQE_CMD_ID (0xFF<<24) 4087 #define COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT 24 4088 struct ramrod_data protocol_data; 4089 __le32 echo; 4090 __le32 reserved2[11]; 4091 }; 4092 4093 /* 4094 * Rx Last CQE in page (in ETH) 4095 */ 4096 struct eth_rx_cqe_next_page { 4097 __le32 addr_lo; 4098 __le32 addr_hi; 4099 __le32 reserved[14]; 4100 }; 4101 4102 /* 4103 * union for all eth rx cqe types (fix their sizes) 4104 */ 4105 union eth_rx_cqe { 4106 struct eth_fast_path_rx_cqe fast_path_cqe; 4107 struct common_ramrod_eth_rx_cqe ramrod_cqe; 4108 struct eth_rx_cqe_next_page next_page_cqe; 4109 struct eth_end_agg_rx_cqe end_agg_cqe; 4110 }; 4111 4112 4113 /* 4114 * Values for RX ETH CQE type field 4115 */ 4116 enum eth_rx_cqe_type { 4117 RX_ETH_CQE_TYPE_ETH_FASTPATH, 4118 RX_ETH_CQE_TYPE_ETH_RAMROD, 4119 RX_ETH_CQE_TYPE_ETH_START_AGG, 4120 RX_ETH_CQE_TYPE_ETH_STOP_AGG, 4121 MAX_ETH_RX_CQE_TYPE 4122 }; 4123 4124 4125 /* 4126 * Type of SGL/Raw field in ETH RX fast path CQE 4127 */ 4128 enum eth_rx_fp_sel { 4129 ETH_FP_CQE_REGULAR, 4130 ETH_FP_CQE_RAW, 4131 MAX_ETH_RX_FP_SEL 4132 }; 4133 4134 4135 /* 4136 * The eth Rx SGE Descriptor 4137 */ 4138 struct eth_rx_sge { 4139 __le32 addr_lo; 4140 __le32 addr_hi; 4141 }; 4142 4143 4144 /* 4145 * common data for all protocols 4146 */ 4147 struct spe_hdr { 4148 __le32 conn_and_cmd_data; 4149 #define SPE_HDR_CID (0xFFFFFF<<0) 4150 #define SPE_HDR_CID_SHIFT 0 4151 #define SPE_HDR_CMD_ID (0xFF<<24) 4152 #define SPE_HDR_CMD_ID_SHIFT 24 4153 __le16 type; 4154 #define SPE_HDR_CONN_TYPE (0xFF<<0) 4155 #define SPE_HDR_CONN_TYPE_SHIFT 0 4156 #define SPE_HDR_FUNCTION_ID (0xFF<<8) 4157 #define SPE_HDR_FUNCTION_ID_SHIFT 8 4158 __le16 reserved1; 4159 }; 4160 4161 /* 4162 * specific data for ethernet slow path element 4163 */ 4164 union eth_specific_data { 4165 u8 protocol_data[8]; 4166 struct regpair client_update_ramrod_data; 4167 struct regpair client_init_ramrod_init_data; 4168 struct eth_halt_ramrod_data halt_ramrod_data; 4169 struct regpair update_data_addr; 4170 struct eth_common_ramrod_data common_ramrod_data; 4171 struct regpair classify_cfg_addr; 4172 struct regpair filter_cfg_addr; 4173 struct regpair mcast_cfg_addr; 4174 }; 4175 4176 /* 4177 * Ethernet slow path element 4178 */ 4179 struct eth_spe { 4180 struct spe_hdr hdr; 4181 union eth_specific_data data; 4182 }; 4183 4184 4185 /* 4186 * Ethernet command ID for slow path elements 4187 */ 4188 enum eth_spqe_cmd_id { 4189 RAMROD_CMD_ID_ETH_UNUSED, 4190 RAMROD_CMD_ID_ETH_CLIENT_SETUP, 4191 RAMROD_CMD_ID_ETH_HALT, 4192 RAMROD_CMD_ID_ETH_FORWARD_SETUP, 4193 RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP, 4194 RAMROD_CMD_ID_ETH_CLIENT_UPDATE, 4195 RAMROD_CMD_ID_ETH_EMPTY, 4196 RAMROD_CMD_ID_ETH_TERMINATE, 4197 RAMROD_CMD_ID_ETH_TPA_UPDATE, 4198 RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES, 4199 RAMROD_CMD_ID_ETH_FILTER_RULES, 4200 RAMROD_CMD_ID_ETH_MULTICAST_RULES, 4201 RAMROD_CMD_ID_ETH_RSS_UPDATE, 4202 RAMROD_CMD_ID_ETH_SET_MAC, 4203 MAX_ETH_SPQE_CMD_ID 4204 }; 4205 4206 4207 /* 4208 * eth tpa update command 4209 */ 4210 enum eth_tpa_update_command { 4211 TPA_UPDATE_NONE_COMMAND, 4212 TPA_UPDATE_ENABLE_COMMAND, 4213 TPA_UPDATE_DISABLE_COMMAND, 4214 MAX_ETH_TPA_UPDATE_COMMAND 4215 }; 4216 4217 /* In case of LSO over IPv4 tunnel, whether to increment 4218 * IP ID on external IP header or internal IP header 4219 */ 4220 enum eth_tunnel_lso_inc_ip_id { 4221 EXT_HEADER, 4222 INT_HEADER, 4223 MAX_ETH_TUNNEL_LSO_INC_IP_ID 4224 }; 4225 4226 /* In case tunnel exist and L4 checksum offload, 4227 * the pseudo checksum location, on packet or on BD. 4228 */ 4229 enum eth_tunnel_non_lso_pcsum_location { 4230 PCSUM_ON_PKT, 4231 PCSUM_ON_BD, 4232 MAX_ETH_TUNNEL_NON_LSO_PCSUM_LOCATION 4233 }; 4234 4235 /* 4236 * Tx regular BD structure 4237 */ 4238 struct eth_tx_bd { 4239 __le32 addr_lo; 4240 __le32 addr_hi; 4241 __le16 total_pkt_bytes; 4242 __le16 nbytes; 4243 u8 reserved[4]; 4244 }; 4245 4246 4247 /* 4248 * structure for easy accessibility to assembler 4249 */ 4250 struct eth_tx_bd_flags { 4251 u8 as_bitfield; 4252 #define ETH_TX_BD_FLAGS_IP_CSUM (0x1<<0) 4253 #define ETH_TX_BD_FLAGS_IP_CSUM_SHIFT 0 4254 #define ETH_TX_BD_FLAGS_L4_CSUM (0x1<<1) 4255 #define ETH_TX_BD_FLAGS_L4_CSUM_SHIFT 1 4256 #define ETH_TX_BD_FLAGS_VLAN_MODE (0x3<<2) 4257 #define ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT 2 4258 #define ETH_TX_BD_FLAGS_START_BD (0x1<<4) 4259 #define ETH_TX_BD_FLAGS_START_BD_SHIFT 4 4260 #define ETH_TX_BD_FLAGS_IS_UDP (0x1<<5) 4261 #define ETH_TX_BD_FLAGS_IS_UDP_SHIFT 5 4262 #define ETH_TX_BD_FLAGS_SW_LSO (0x1<<6) 4263 #define ETH_TX_BD_FLAGS_SW_LSO_SHIFT 6 4264 #define ETH_TX_BD_FLAGS_IPV6 (0x1<<7) 4265 #define ETH_TX_BD_FLAGS_IPV6_SHIFT 7 4266 }; 4267 4268 /* 4269 * The eth Tx Buffer Descriptor 4270 */ 4271 struct eth_tx_start_bd { 4272 __le32 addr_lo; 4273 __le32 addr_hi; 4274 __le16 nbd; 4275 __le16 nbytes; 4276 __le16 vlan_or_ethertype; 4277 struct eth_tx_bd_flags bd_flags; 4278 u8 general_data; 4279 #define ETH_TX_START_BD_HDR_NBDS (0xF<<0) 4280 #define ETH_TX_START_BD_HDR_NBDS_SHIFT 0 4281 #define ETH_TX_START_BD_FORCE_VLAN_MODE (0x1<<4) 4282 #define ETH_TX_START_BD_FORCE_VLAN_MODE_SHIFT 4 4283 #define ETH_TX_START_BD_PARSE_NBDS (0x3<<5) 4284 #define ETH_TX_START_BD_PARSE_NBDS_SHIFT 5 4285 #define ETH_TX_START_BD_TUNNEL_EXIST (0x1<<7) 4286 #define ETH_TX_START_BD_TUNNEL_EXIST_SHIFT 7 4287 }; 4288 4289 /* 4290 * Tx parsing BD structure for ETH E1/E1h 4291 */ 4292 struct eth_tx_parse_bd_e1x { 4293 __le16 global_data; 4294 #define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W (0xF<<0) 4295 #define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W_SHIFT 0 4296 #define ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE (0x3<<4) 4297 #define ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE_SHIFT 4 4298 #define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN (0x1<<6) 4299 #define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN_SHIFT 6 4300 #define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN (0x1<<7) 4301 #define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN_SHIFT 7 4302 #define ETH_TX_PARSE_BD_E1X_NS_FLG (0x1<<8) 4303 #define ETH_TX_PARSE_BD_E1X_NS_FLG_SHIFT 8 4304 #define ETH_TX_PARSE_BD_E1X_RESERVED0 (0x7F<<9) 4305 #define ETH_TX_PARSE_BD_E1X_RESERVED0_SHIFT 9 4306 u8 tcp_flags; 4307 #define ETH_TX_PARSE_BD_E1X_FIN_FLG (0x1<<0) 4308 #define ETH_TX_PARSE_BD_E1X_FIN_FLG_SHIFT 0 4309 #define ETH_TX_PARSE_BD_E1X_SYN_FLG (0x1<<1) 4310 #define ETH_TX_PARSE_BD_E1X_SYN_FLG_SHIFT 1 4311 #define ETH_TX_PARSE_BD_E1X_RST_FLG (0x1<<2) 4312 #define ETH_TX_PARSE_BD_E1X_RST_FLG_SHIFT 2 4313 #define ETH_TX_PARSE_BD_E1X_PSH_FLG (0x1<<3) 4314 #define ETH_TX_PARSE_BD_E1X_PSH_FLG_SHIFT 3 4315 #define ETH_TX_PARSE_BD_E1X_ACK_FLG (0x1<<4) 4316 #define ETH_TX_PARSE_BD_E1X_ACK_FLG_SHIFT 4 4317 #define ETH_TX_PARSE_BD_E1X_URG_FLG (0x1<<5) 4318 #define ETH_TX_PARSE_BD_E1X_URG_FLG_SHIFT 5 4319 #define ETH_TX_PARSE_BD_E1X_ECE_FLG (0x1<<6) 4320 #define ETH_TX_PARSE_BD_E1X_ECE_FLG_SHIFT 6 4321 #define ETH_TX_PARSE_BD_E1X_CWR_FLG (0x1<<7) 4322 #define ETH_TX_PARSE_BD_E1X_CWR_FLG_SHIFT 7 4323 u8 ip_hlen_w; 4324 __le16 total_hlen_w; 4325 __le16 tcp_pseudo_csum; 4326 __le16 lso_mss; 4327 __le16 ip_id; 4328 __le32 tcp_send_seq; 4329 }; 4330 4331 /* 4332 * Tx parsing BD structure for ETH E2 4333 */ 4334 struct eth_tx_parse_bd_e2 { 4335 union eth_mac_addr_or_tunnel_data data; 4336 __le32 parsing_data; 4337 #define ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W (0x7FF<<0) 4338 #define ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W_SHIFT 0 4339 #define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW (0xF<<11) 4340 #define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW_SHIFT 11 4341 #define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR (0x1<<15) 4342 #define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR_SHIFT 15 4343 #define ETH_TX_PARSE_BD_E2_LSO_MSS (0x3FFF<<16) 4344 #define ETH_TX_PARSE_BD_E2_LSO_MSS_SHIFT 16 4345 #define ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE (0x3<<30) 4346 #define ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE_SHIFT 30 4347 }; 4348 4349 /* 4350 * Tx 2nd parsing BD structure for ETH packet 4351 */ 4352 struct eth_tx_parse_2nd_bd { 4353 __le16 global_data; 4354 #define ETH_TX_PARSE_2ND_BD_IP_HDR_START_OUTER_W (0xF<<0) 4355 #define ETH_TX_PARSE_2ND_BD_IP_HDR_START_OUTER_W_SHIFT 0 4356 #define ETH_TX_PARSE_2ND_BD_IP_HDR_TYPE_OUTER (0x1<<4) 4357 #define ETH_TX_PARSE_2ND_BD_IP_HDR_TYPE_OUTER_SHIFT 4 4358 #define ETH_TX_PARSE_2ND_BD_LLC_SNAP_EN (0x1<<5) 4359 #define ETH_TX_PARSE_2ND_BD_LLC_SNAP_EN_SHIFT 5 4360 #define ETH_TX_PARSE_2ND_BD_NS_FLG (0x1<<6) 4361 #define ETH_TX_PARSE_2ND_BD_NS_FLG_SHIFT 6 4362 #define ETH_TX_PARSE_2ND_BD_TUNNEL_UDP_EXIST (0x1<<7) 4363 #define ETH_TX_PARSE_2ND_BD_TUNNEL_UDP_EXIST_SHIFT 7 4364 #define ETH_TX_PARSE_2ND_BD_IP_HDR_LEN_OUTER_W (0x1F<<8) 4365 #define ETH_TX_PARSE_2ND_BD_IP_HDR_LEN_OUTER_W_SHIFT 8 4366 #define ETH_TX_PARSE_2ND_BD_RESERVED0 (0x7<<13) 4367 #define ETH_TX_PARSE_2ND_BD_RESERVED0_SHIFT 13 4368 __le16 reserved1; 4369 u8 tcp_flags; 4370 #define ETH_TX_PARSE_2ND_BD_FIN_FLG (0x1<<0) 4371 #define ETH_TX_PARSE_2ND_BD_FIN_FLG_SHIFT 0 4372 #define ETH_TX_PARSE_2ND_BD_SYN_FLG (0x1<<1) 4373 #define ETH_TX_PARSE_2ND_BD_SYN_FLG_SHIFT 1 4374 #define ETH_TX_PARSE_2ND_BD_RST_FLG (0x1<<2) 4375 #define ETH_TX_PARSE_2ND_BD_RST_FLG_SHIFT 2 4376 #define ETH_TX_PARSE_2ND_BD_PSH_FLG (0x1<<3) 4377 #define ETH_TX_PARSE_2ND_BD_PSH_FLG_SHIFT 3 4378 #define ETH_TX_PARSE_2ND_BD_ACK_FLG (0x1<<4) 4379 #define ETH_TX_PARSE_2ND_BD_ACK_FLG_SHIFT 4 4380 #define ETH_TX_PARSE_2ND_BD_URG_FLG (0x1<<5) 4381 #define ETH_TX_PARSE_2ND_BD_URG_FLG_SHIFT 5 4382 #define ETH_TX_PARSE_2ND_BD_ECE_FLG (0x1<<6) 4383 #define ETH_TX_PARSE_2ND_BD_ECE_FLG_SHIFT 6 4384 #define ETH_TX_PARSE_2ND_BD_CWR_FLG (0x1<<7) 4385 #define ETH_TX_PARSE_2ND_BD_CWR_FLG_SHIFT 7 4386 u8 reserved2; 4387 u8 tunnel_udp_hdr_start_w; 4388 u8 fw_ip_hdr_to_payload_w; 4389 __le16 fw_ip_csum_wo_len_flags_frag; 4390 __le16 hw_ip_id; 4391 __le32 tcp_send_seq; 4392 }; 4393 4394 /* The last BD in the BD memory will hold a pointer to the next BD memory */ 4395 struct eth_tx_next_bd { 4396 __le32 addr_lo; 4397 __le32 addr_hi; 4398 u8 reserved[8]; 4399 }; 4400 4401 /* 4402 * union for 4 Bd types 4403 */ 4404 union eth_tx_bd_types { 4405 struct eth_tx_start_bd start_bd; 4406 struct eth_tx_bd reg_bd; 4407 struct eth_tx_parse_bd_e1x parse_bd_e1x; 4408 struct eth_tx_parse_bd_e2 parse_bd_e2; 4409 struct eth_tx_parse_2nd_bd parse_2nd_bd; 4410 struct eth_tx_next_bd next_bd; 4411 }; 4412 4413 /* 4414 * array of 13 bds as appears in the eth xstorm context 4415 */ 4416 struct eth_tx_bds_array { 4417 union eth_tx_bd_types bds[13]; 4418 }; 4419 4420 4421 /* 4422 * VLAN mode on TX BDs 4423 */ 4424 enum eth_tx_vlan_type { 4425 X_ETH_NO_VLAN, 4426 X_ETH_OUTBAND_VLAN, 4427 X_ETH_INBAND_VLAN, 4428 X_ETH_FW_ADDED_VLAN, 4429 MAX_ETH_TX_VLAN_TYPE 4430 }; 4431 4432 4433 /* 4434 * Ethernet VLAN filtering mode in E1x 4435 */ 4436 enum eth_vlan_filter_mode { 4437 ETH_VLAN_FILTER_ANY_VLAN, 4438 ETH_VLAN_FILTER_SPECIFIC_VLAN, 4439 ETH_VLAN_FILTER_CLASSIFY, 4440 MAX_ETH_VLAN_FILTER_MODE 4441 }; 4442 4443 4444 /* 4445 * MAC filtering configuration command header 4446 */ 4447 struct mac_configuration_hdr { 4448 u8 length; 4449 u8 offset; 4450 __le16 client_id; 4451 __le32 echo; 4452 }; 4453 4454 /* 4455 * MAC address in list for ramrod 4456 */ 4457 struct mac_configuration_entry { 4458 __le16 lsb_mac_addr; 4459 __le16 middle_mac_addr; 4460 __le16 msb_mac_addr; 4461 __le16 vlan_id; 4462 u8 pf_id; 4463 u8 flags; 4464 #define MAC_CONFIGURATION_ENTRY_ACTION_TYPE (0x1<<0) 4465 #define MAC_CONFIGURATION_ENTRY_ACTION_TYPE_SHIFT 0 4466 #define MAC_CONFIGURATION_ENTRY_RDMA_MAC (0x1<<1) 4467 #define MAC_CONFIGURATION_ENTRY_RDMA_MAC_SHIFT 1 4468 #define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE (0x3<<2) 4469 #define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE_SHIFT 2 4470 #define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL (0x1<<4) 4471 #define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL_SHIFT 4 4472 #define MAC_CONFIGURATION_ENTRY_BROADCAST (0x1<<5) 4473 #define MAC_CONFIGURATION_ENTRY_BROADCAST_SHIFT 5 4474 #define MAC_CONFIGURATION_ENTRY_RESERVED1 (0x3<<6) 4475 #define MAC_CONFIGURATION_ENTRY_RESERVED1_SHIFT 6 4476 __le16 reserved0; 4477 __le32 clients_bit_vector; 4478 }; 4479 4480 /* 4481 * MAC filtering configuration command 4482 */ 4483 struct mac_configuration_cmd { 4484 struct mac_configuration_hdr hdr; 4485 struct mac_configuration_entry config_table[64]; 4486 }; 4487 4488 4489 /* 4490 * Set-MAC command type (in E1x) 4491 */ 4492 enum set_mac_action_type { 4493 T_ETH_MAC_COMMAND_INVALIDATE, 4494 T_ETH_MAC_COMMAND_SET, 4495 MAX_SET_MAC_ACTION_TYPE 4496 }; 4497 4498 4499 /* 4500 * Ethernet TPA Modes 4501 */ 4502 enum tpa_mode { 4503 TPA_LRO, 4504 TPA_GRO, 4505 MAX_TPA_MODE}; 4506 4507 4508 /* 4509 * tpa update ramrod data 4510 */ 4511 struct tpa_update_ramrod_data { 4512 u8 update_ipv4; 4513 u8 update_ipv6; 4514 u8 client_id; 4515 u8 max_tpa_queues; 4516 u8 max_sges_for_packet; 4517 u8 complete_on_both_clients; 4518 u8 dont_verify_rings_pause_thr_flg; 4519 u8 tpa_mode; 4520 __le16 sge_buff_size; 4521 __le16 max_agg_size; 4522 __le32 sge_page_base_lo; 4523 __le32 sge_page_base_hi; 4524 __le16 sge_pause_thr_low; 4525 __le16 sge_pause_thr_high; 4526 }; 4527 4528 4529 /* 4530 * approximate-match multicast filtering for E1H per function in Tstorm 4531 */ 4532 struct tstorm_eth_approximate_match_multicast_filtering { 4533 u32 mcast_add_hash_bit_array[8]; 4534 }; 4535 4536 4537 /* 4538 * Common configuration parameters per function in Tstorm 4539 */ 4540 struct tstorm_eth_function_common_config { 4541 __le16 config_flags; 4542 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0) 4543 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0 4544 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1) 4545 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1 4546 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1<<2) 4547 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2 4548 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3) 4549 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3 4550 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE (0x7<<4) 4551 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT 4 4552 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE (0x1<<7) 4553 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE_SHIFT 7 4554 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0xFF<<8) 4555 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 8 4556 u8 rss_result_mask; 4557 u8 reserved1; 4558 __le16 vlan_id[2]; 4559 }; 4560 4561 4562 /* 4563 * MAC filtering configuration parameters per port in Tstorm 4564 */ 4565 struct tstorm_eth_mac_filter_config { 4566 u32 ucast_drop_all; 4567 u32 ucast_accept_all; 4568 u32 mcast_drop_all; 4569 u32 mcast_accept_all; 4570 u32 bcast_accept_all; 4571 u32 vlan_filter[2]; 4572 u32 unmatched_unicast; 4573 }; 4574 4575 4576 /* 4577 * tx only queue init ramrod data 4578 */ 4579 struct tx_queue_init_ramrod_data { 4580 struct client_init_general_data general; 4581 struct client_init_tx_data tx; 4582 }; 4583 4584 4585 /* 4586 * Three RX producers for ETH 4587 */ 4588 struct ustorm_eth_rx_producers { 4589 #if defined(__BIG_ENDIAN) 4590 u16 bd_prod; 4591 u16 cqe_prod; 4592 #elif defined(__LITTLE_ENDIAN) 4593 u16 cqe_prod; 4594 u16 bd_prod; 4595 #endif 4596 #if defined(__BIG_ENDIAN) 4597 u16 reserved; 4598 u16 sge_prod; 4599 #elif defined(__LITTLE_ENDIAN) 4600 u16 sge_prod; 4601 u16 reserved; 4602 #endif 4603 }; 4604 4605 4606 /* 4607 * FCoE RX statistics parameters section#0 4608 */ 4609 struct fcoe_rx_stat_params_section0 { 4610 __le32 fcoe_rx_pkt_cnt; 4611 __le32 fcoe_rx_byte_cnt; 4612 }; 4613 4614 4615 /* 4616 * FCoE RX statistics parameters section#1 4617 */ 4618 struct fcoe_rx_stat_params_section1 { 4619 __le32 fcoe_ver_cnt; 4620 __le32 fcoe_rx_drop_pkt_cnt; 4621 }; 4622 4623 4624 /* 4625 * FCoE RX statistics parameters section#2 4626 */ 4627 struct fcoe_rx_stat_params_section2 { 4628 __le32 fc_crc_cnt; 4629 __le32 eofa_del_cnt; 4630 __le32 miss_frame_cnt; 4631 __le32 seq_timeout_cnt; 4632 __le32 drop_seq_cnt; 4633 __le32 fcoe_rx_drop_pkt_cnt; 4634 __le32 fcp_rx_pkt_cnt; 4635 __le32 reserved0; 4636 }; 4637 4638 4639 /* 4640 * FCoE TX statistics parameters 4641 */ 4642 struct fcoe_tx_stat_params { 4643 __le32 fcoe_tx_pkt_cnt; 4644 __le32 fcoe_tx_byte_cnt; 4645 __le32 fcp_tx_pkt_cnt; 4646 __le32 reserved0; 4647 }; 4648 4649 /* 4650 * FCoE statistics parameters 4651 */ 4652 struct fcoe_statistics_params { 4653 struct fcoe_tx_stat_params tx_stat; 4654 struct fcoe_rx_stat_params_section0 rx_stat0; 4655 struct fcoe_rx_stat_params_section1 rx_stat1; 4656 struct fcoe_rx_stat_params_section2 rx_stat2; 4657 }; 4658 4659 4660 /* 4661 * The data afex vif list ramrod need 4662 */ 4663 struct afex_vif_list_ramrod_data { 4664 u8 afex_vif_list_command; 4665 u8 func_bit_map; 4666 __le16 vif_list_index; 4667 u8 func_to_clear; 4668 u8 echo; 4669 __le16 reserved1; 4670 }; 4671 4672 4673 /* 4674 * cfc delete event data 4675 */ 4676 struct cfc_del_event_data { 4677 u32 cid; 4678 u32 reserved0; 4679 u32 reserved1; 4680 }; 4681 4682 4683 /* 4684 * per-port SAFC demo variables 4685 */ 4686 struct cmng_flags_per_port { 4687 u32 cmng_enables; 4688 #define CMNG_FLAGS_PER_PORT_FAIRNESS_VN (0x1<<0) 4689 #define CMNG_FLAGS_PER_PORT_FAIRNESS_VN_SHIFT 0 4690 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN (0x1<<1) 4691 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN_SHIFT 1 4692 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS (0x1<<2) 4693 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_SHIFT 2 4694 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE (0x1<<3) 4695 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE_SHIFT 3 4696 #define __CMNG_FLAGS_PER_PORT_RESERVED0 (0xFFFFFFF<<4) 4697 #define __CMNG_FLAGS_PER_PORT_RESERVED0_SHIFT 4 4698 u32 __reserved1; 4699 }; 4700 4701 4702 /* 4703 * per-port rate shaping variables 4704 */ 4705 struct rate_shaping_vars_per_port { 4706 u32 rs_periodic_timeout; 4707 u32 rs_threshold; 4708 }; 4709 4710 /* 4711 * per-port fairness variables 4712 */ 4713 struct fairness_vars_per_port { 4714 u32 upper_bound; 4715 u32 fair_threshold; 4716 u32 fairness_timeout; 4717 u32 reserved0; 4718 }; 4719 4720 /* 4721 * per-port SAFC variables 4722 */ 4723 struct safc_struct_per_port { 4724 #if defined(__BIG_ENDIAN) 4725 u16 __reserved1; 4726 u8 __reserved0; 4727 u8 safc_timeout_usec; 4728 #elif defined(__LITTLE_ENDIAN) 4729 u8 safc_timeout_usec; 4730 u8 __reserved0; 4731 u16 __reserved1; 4732 #endif 4733 u8 cos_to_traffic_types[MAX_COS_NUMBER]; 4734 u16 cos_to_pause_mask[NUM_OF_SAFC_BITS]; 4735 }; 4736 4737 /* 4738 * Per-port congestion management variables 4739 */ 4740 struct cmng_struct_per_port { 4741 struct rate_shaping_vars_per_port rs_vars; 4742 struct fairness_vars_per_port fair_vars; 4743 struct safc_struct_per_port safc_vars; 4744 struct cmng_flags_per_port flags; 4745 }; 4746 4747 /* 4748 * a single rate shaping counter. can be used as protocol or vnic counter 4749 */ 4750 struct rate_shaping_counter { 4751 u32 quota; 4752 #if defined(__BIG_ENDIAN) 4753 u16 __reserved0; 4754 u16 rate; 4755 #elif defined(__LITTLE_ENDIAN) 4756 u16 rate; 4757 u16 __reserved0; 4758 #endif 4759 }; 4760 4761 /* 4762 * per-vnic rate shaping variables 4763 */ 4764 struct rate_shaping_vars_per_vn { 4765 struct rate_shaping_counter vn_counter; 4766 }; 4767 4768 /* 4769 * per-vnic fairness variables 4770 */ 4771 struct fairness_vars_per_vn { 4772 u32 cos_credit_delta[MAX_COS_NUMBER]; 4773 u32 vn_credit_delta; 4774 u32 __reserved0; 4775 }; 4776 4777 /* 4778 * cmng port init state 4779 */ 4780 struct cmng_vnic { 4781 struct rate_shaping_vars_per_vn vnic_max_rate[4]; 4782 struct fairness_vars_per_vn vnic_min_rate[4]; 4783 }; 4784 4785 /* 4786 * cmng port init state 4787 */ 4788 struct cmng_init { 4789 struct cmng_struct_per_port port; 4790 struct cmng_vnic vnic; 4791 }; 4792 4793 4794 /* 4795 * driver parameters for congestion management init, all rates are in Mbps 4796 */ 4797 struct cmng_init_input { 4798 u32 port_rate; 4799 u16 vnic_min_rate[4]; 4800 u16 vnic_max_rate[4]; 4801 u16 cos_min_rate[MAX_COS_NUMBER]; 4802 u16 cos_to_pause_mask[MAX_COS_NUMBER]; 4803 struct cmng_flags_per_port flags; 4804 }; 4805 4806 4807 /* 4808 * Protocol-common command ID for slow path elements 4809 */ 4810 enum common_spqe_cmd_id { 4811 RAMROD_CMD_ID_COMMON_UNUSED, 4812 RAMROD_CMD_ID_COMMON_FUNCTION_START, 4813 RAMROD_CMD_ID_COMMON_FUNCTION_STOP, 4814 RAMROD_CMD_ID_COMMON_FUNCTION_UPDATE, 4815 RAMROD_CMD_ID_COMMON_CFC_DEL, 4816 RAMROD_CMD_ID_COMMON_CFC_DEL_WB, 4817 RAMROD_CMD_ID_COMMON_STAT_QUERY, 4818 RAMROD_CMD_ID_COMMON_STOP_TRAFFIC, 4819 RAMROD_CMD_ID_COMMON_START_TRAFFIC, 4820 RAMROD_CMD_ID_COMMON_AFEX_VIF_LISTS, 4821 RAMROD_CMD_ID_COMMON_SET_TIMESYNC, 4822 MAX_COMMON_SPQE_CMD_ID 4823 }; 4824 4825 /* 4826 * Per-protocol connection types 4827 */ 4828 enum connection_type { 4829 ETH_CONNECTION_TYPE, 4830 TOE_CONNECTION_TYPE, 4831 RDMA_CONNECTION_TYPE, 4832 ISCSI_CONNECTION_TYPE, 4833 FCOE_CONNECTION_TYPE, 4834 RESERVED_CONNECTION_TYPE_0, 4835 RESERVED_CONNECTION_TYPE_1, 4836 RESERVED_CONNECTION_TYPE_2, 4837 NONE_CONNECTION_TYPE, 4838 MAX_CONNECTION_TYPE 4839 }; 4840 4841 4842 /* 4843 * Cos modes 4844 */ 4845 enum cos_mode { 4846 OVERRIDE_COS, 4847 STATIC_COS, 4848 FW_WRR, 4849 MAX_COS_MODE 4850 }; 4851 4852 4853 /* 4854 * Dynamic HC counters set by the driver 4855 */ 4856 struct hc_dynamic_drv_counter { 4857 u32 val[HC_SB_MAX_DYNAMIC_INDICES]; 4858 }; 4859 4860 /* 4861 * zone A per-queue data 4862 */ 4863 struct cstorm_queue_zone_data { 4864 struct hc_dynamic_drv_counter hc_dyn_drv_cnt; 4865 struct regpair reserved[2]; 4866 }; 4867 4868 4869 /* 4870 * Vf-PF channel data in cstorm ram (non-triggered zone) 4871 */ 4872 struct vf_pf_channel_zone_data { 4873 u32 msg_addr_lo; 4874 u32 msg_addr_hi; 4875 }; 4876 4877 /* 4878 * zone for VF non-triggered data 4879 */ 4880 struct non_trigger_vf_zone { 4881 struct vf_pf_channel_zone_data vf_pf_channel; 4882 }; 4883 4884 /* 4885 * Vf-PF channel trigger zone in cstorm ram 4886 */ 4887 struct vf_pf_channel_zone_trigger { 4888 u8 addr_valid; 4889 }; 4890 4891 /* 4892 * zone that triggers the in-bound interrupt 4893 */ 4894 struct trigger_vf_zone { 4895 #if defined(__BIG_ENDIAN) 4896 u16 reserved1; 4897 u8 reserved0; 4898 struct vf_pf_channel_zone_trigger vf_pf_channel; 4899 #elif defined(__LITTLE_ENDIAN) 4900 struct vf_pf_channel_zone_trigger vf_pf_channel; 4901 u8 reserved0; 4902 u16 reserved1; 4903 #endif 4904 u32 reserved2; 4905 }; 4906 4907 /* 4908 * zone B per-VF data 4909 */ 4910 struct cstorm_vf_zone_data { 4911 struct non_trigger_vf_zone non_trigger; 4912 struct trigger_vf_zone trigger; 4913 }; 4914 4915 4916 /* 4917 * Dynamic host coalescing init parameters, per state machine 4918 */ 4919 struct dynamic_hc_sm_config { 4920 u32 threshold[3]; 4921 u8 shift_per_protocol[HC_SB_MAX_DYNAMIC_INDICES]; 4922 u8 hc_timeout0[HC_SB_MAX_DYNAMIC_INDICES]; 4923 u8 hc_timeout1[HC_SB_MAX_DYNAMIC_INDICES]; 4924 u8 hc_timeout2[HC_SB_MAX_DYNAMIC_INDICES]; 4925 u8 hc_timeout3[HC_SB_MAX_DYNAMIC_INDICES]; 4926 }; 4927 4928 /* 4929 * Dynamic host coalescing init parameters 4930 */ 4931 struct dynamic_hc_config { 4932 struct dynamic_hc_sm_config sm_config[HC_SB_MAX_SM]; 4933 }; 4934 4935 4936 struct e2_integ_data { 4937 #if defined(__BIG_ENDIAN) 4938 u8 flags; 4939 #define E2_INTEG_DATA_TESTING_EN (0x1<<0) 4940 #define E2_INTEG_DATA_TESTING_EN_SHIFT 0 4941 #define E2_INTEG_DATA_LB_TX (0x1<<1) 4942 #define E2_INTEG_DATA_LB_TX_SHIFT 1 4943 #define E2_INTEG_DATA_COS_TX (0x1<<2) 4944 #define E2_INTEG_DATA_COS_TX_SHIFT 2 4945 #define E2_INTEG_DATA_OPPORTUNISTICQM (0x1<<3) 4946 #define E2_INTEG_DATA_OPPORTUNISTICQM_SHIFT 3 4947 #define E2_INTEG_DATA_DPMTESTRELEASEDQ (0x1<<4) 4948 #define E2_INTEG_DATA_DPMTESTRELEASEDQ_SHIFT 4 4949 #define E2_INTEG_DATA_RESERVED (0x7<<5) 4950 #define E2_INTEG_DATA_RESERVED_SHIFT 5 4951 u8 cos; 4952 u8 voq; 4953 u8 pbf_queue; 4954 #elif defined(__LITTLE_ENDIAN) 4955 u8 pbf_queue; 4956 u8 voq; 4957 u8 cos; 4958 u8 flags; 4959 #define E2_INTEG_DATA_TESTING_EN (0x1<<0) 4960 #define E2_INTEG_DATA_TESTING_EN_SHIFT 0 4961 #define E2_INTEG_DATA_LB_TX (0x1<<1) 4962 #define E2_INTEG_DATA_LB_TX_SHIFT 1 4963 #define E2_INTEG_DATA_COS_TX (0x1<<2) 4964 #define E2_INTEG_DATA_COS_TX_SHIFT 2 4965 #define E2_INTEG_DATA_OPPORTUNISTICQM (0x1<<3) 4966 #define E2_INTEG_DATA_OPPORTUNISTICQM_SHIFT 3 4967 #define E2_INTEG_DATA_DPMTESTRELEASEDQ (0x1<<4) 4968 #define E2_INTEG_DATA_DPMTESTRELEASEDQ_SHIFT 4 4969 #define E2_INTEG_DATA_RESERVED (0x7<<5) 4970 #define E2_INTEG_DATA_RESERVED_SHIFT 5 4971 #endif 4972 #if defined(__BIG_ENDIAN) 4973 u16 reserved3; 4974 u8 reserved2; 4975 u8 ramEn; 4976 #elif defined(__LITTLE_ENDIAN) 4977 u8 ramEn; 4978 u8 reserved2; 4979 u16 reserved3; 4980 #endif 4981 }; 4982 4983 4984 /* 4985 * set mac event data 4986 */ 4987 struct eth_event_data { 4988 u32 echo; 4989 u32 reserved0; 4990 u32 reserved1; 4991 }; 4992 4993 4994 /* 4995 * pf-vf event data 4996 */ 4997 struct vf_pf_event_data { 4998 u8 vf_id; 4999 u8 reserved0; 5000 u16 reserved1; 5001 u32 msg_addr_lo; 5002 u32 msg_addr_hi; 5003 }; 5004 5005 /* 5006 * VF FLR event data 5007 */ 5008 struct vf_flr_event_data { 5009 u8 vf_id; 5010 u8 reserved0; 5011 u16 reserved1; 5012 u32 reserved2; 5013 u32 reserved3; 5014 }; 5015 5016 /* 5017 * malicious VF event data 5018 */ 5019 struct malicious_vf_event_data { 5020 u8 vf_id; 5021 u8 err_id; 5022 u16 reserved1; 5023 u32 reserved2; 5024 u32 reserved3; 5025 }; 5026 5027 /* 5028 * vif list event data 5029 */ 5030 struct vif_list_event_data { 5031 u8 func_bit_map; 5032 u8 echo; 5033 __le16 reserved0; 5034 __le32 reserved1; 5035 __le32 reserved2; 5036 }; 5037 5038 /* function update event data */ 5039 struct function_update_event_data { 5040 u8 echo; 5041 u8 reserved; 5042 __le16 reserved0; 5043 __le32 reserved1; 5044 __le32 reserved2; 5045 }; 5046 5047 5048 /* union for all event ring message types */ 5049 union event_data { 5050 struct vf_pf_event_data vf_pf_event; 5051 struct eth_event_data eth_event; 5052 struct cfc_del_event_data cfc_del_event; 5053 struct vf_flr_event_data vf_flr_event; 5054 struct malicious_vf_event_data malicious_vf_event; 5055 struct vif_list_event_data vif_list_event; 5056 struct function_update_event_data function_update_event; 5057 }; 5058 5059 5060 /* 5061 * per PF event ring data 5062 */ 5063 struct event_ring_data { 5064 struct regpair_native base_addr; 5065 #if defined(__BIG_ENDIAN) 5066 u8 index_id; 5067 u8 sb_id; 5068 u16 producer; 5069 #elif defined(__LITTLE_ENDIAN) 5070 u16 producer; 5071 u8 sb_id; 5072 u8 index_id; 5073 #endif 5074 u32 reserved0; 5075 }; 5076 5077 5078 /* 5079 * event ring message element (each element is 128 bits) 5080 */ 5081 struct event_ring_msg { 5082 u8 opcode; 5083 u8 error; 5084 u16 reserved1; 5085 union event_data data; 5086 }; 5087 5088 /* 5089 * event ring next page element (128 bits) 5090 */ 5091 struct event_ring_next { 5092 struct regpair addr; 5093 u32 reserved[2]; 5094 }; 5095 5096 /* 5097 * union for event ring element types (each element is 128 bits) 5098 */ 5099 union event_ring_elem { 5100 struct event_ring_msg message; 5101 struct event_ring_next next_page; 5102 }; 5103 5104 5105 /* 5106 * Common event ring opcodes 5107 */ 5108 enum event_ring_opcode { 5109 EVENT_RING_OPCODE_VF_PF_CHANNEL, 5110 EVENT_RING_OPCODE_FUNCTION_START, 5111 EVENT_RING_OPCODE_FUNCTION_STOP, 5112 EVENT_RING_OPCODE_CFC_DEL, 5113 EVENT_RING_OPCODE_CFC_DEL_WB, 5114 EVENT_RING_OPCODE_STAT_QUERY, 5115 EVENT_RING_OPCODE_STOP_TRAFFIC, 5116 EVENT_RING_OPCODE_START_TRAFFIC, 5117 EVENT_RING_OPCODE_VF_FLR, 5118 EVENT_RING_OPCODE_MALICIOUS_VF, 5119 EVENT_RING_OPCODE_FORWARD_SETUP, 5120 EVENT_RING_OPCODE_RSS_UPDATE_RULES, 5121 EVENT_RING_OPCODE_FUNCTION_UPDATE, 5122 EVENT_RING_OPCODE_AFEX_VIF_LISTS, 5123 EVENT_RING_OPCODE_SET_MAC, 5124 EVENT_RING_OPCODE_CLASSIFICATION_RULES, 5125 EVENT_RING_OPCODE_FILTERS_RULES, 5126 EVENT_RING_OPCODE_MULTICAST_RULES, 5127 EVENT_RING_OPCODE_SET_TIMESYNC, 5128 MAX_EVENT_RING_OPCODE 5129 }; 5130 5131 /* 5132 * Modes for fairness algorithm 5133 */ 5134 enum fairness_mode { 5135 FAIRNESS_COS_WRR_MODE, 5136 FAIRNESS_COS_ETS_MODE, 5137 MAX_FAIRNESS_MODE 5138 }; 5139 5140 5141 /* 5142 * Priority and cos 5143 */ 5144 struct priority_cos { 5145 u8 priority; 5146 u8 cos; 5147 __le16 reserved1; 5148 }; 5149 5150 /* 5151 * The data for flow control configuration 5152 */ 5153 struct flow_control_configuration { 5154 struct priority_cos traffic_type_to_priority_cos[MAX_TRAFFIC_TYPES]; 5155 u8 dcb_enabled; 5156 u8 dcb_version; 5157 u8 dont_add_pri_0_en; 5158 u8 reserved1; 5159 __le32 reserved2; 5160 }; 5161 5162 5163 /* 5164 * 5165 */ 5166 struct function_start_data { 5167 u8 function_mode; 5168 u8 allow_npar_tx_switching; 5169 __le16 sd_vlan_tag; 5170 __le16 vif_id; 5171 u8 path_id; 5172 u8 network_cos_mode; 5173 u8 dmae_cmd_id; 5174 u8 gre_tunnel_mode; 5175 u8 gre_tunnel_rss; 5176 u8 nvgre_clss_en; 5177 __le16 reserved1[2]; 5178 }; 5179 5180 struct function_update_data { 5181 u8 vif_id_change_flg; 5182 u8 afex_default_vlan_change_flg; 5183 u8 allowed_priorities_change_flg; 5184 u8 network_cos_mode_change_flg; 5185 __le16 vif_id; 5186 __le16 afex_default_vlan; 5187 u8 allowed_priorities; 5188 u8 network_cos_mode; 5189 u8 lb_mode_en_change_flg; 5190 u8 lb_mode_en; 5191 u8 tx_switch_suspend_change_flg; 5192 u8 tx_switch_suspend; 5193 u8 echo; 5194 u8 reserved1; 5195 u8 update_gre_cfg_flg; 5196 u8 gre_tunnel_mode; 5197 u8 gre_tunnel_rss; 5198 u8 nvgre_clss_en; 5199 u32 reserved3; 5200 }; 5201 5202 /* 5203 * FW version stored in the Xstorm RAM 5204 */ 5205 struct fw_version { 5206 #if defined(__BIG_ENDIAN) 5207 u8 engineering; 5208 u8 revision; 5209 u8 minor; 5210 u8 major; 5211 #elif defined(__LITTLE_ENDIAN) 5212 u8 major; 5213 u8 minor; 5214 u8 revision; 5215 u8 engineering; 5216 #endif 5217 u32 flags; 5218 #define FW_VERSION_OPTIMIZED (0x1<<0) 5219 #define FW_VERSION_OPTIMIZED_SHIFT 0 5220 #define FW_VERSION_BIG_ENDIEN (0x1<<1) 5221 #define FW_VERSION_BIG_ENDIEN_SHIFT 1 5222 #define FW_VERSION_CHIP_VERSION (0x3<<2) 5223 #define FW_VERSION_CHIP_VERSION_SHIFT 2 5224 #define __FW_VERSION_RESERVED (0xFFFFFFF<<4) 5225 #define __FW_VERSION_RESERVED_SHIFT 4 5226 }; 5227 5228 /* GRE RSS Mode */ 5229 enum gre_rss_mode { 5230 GRE_OUTER_HEADERS_RSS, 5231 GRE_INNER_HEADERS_RSS, 5232 NVGRE_KEY_ENTROPY_RSS, 5233 MAX_GRE_RSS_MODE 5234 }; 5235 5236 /* GRE Tunnel Mode */ 5237 enum gre_tunnel_type { 5238 NO_GRE_TUNNEL, 5239 NVGRE_TUNNEL, 5240 L2GRE_TUNNEL, 5241 IPGRE_TUNNEL, 5242 MAX_GRE_TUNNEL_TYPE 5243 }; 5244 5245 /* 5246 * Dynamic Host-Coalescing - Driver(host) counters 5247 */ 5248 struct hc_dynamic_sb_drv_counters { 5249 u32 dynamic_hc_drv_counter[HC_SB_MAX_DYNAMIC_INDICES]; 5250 }; 5251 5252 5253 /* 5254 * 2 bytes. configuration/state parameters for a single protocol index 5255 */ 5256 struct hc_index_data { 5257 #if defined(__BIG_ENDIAN) 5258 u8 flags; 5259 #define HC_INDEX_DATA_SM_ID (0x1<<0) 5260 #define HC_INDEX_DATA_SM_ID_SHIFT 0 5261 #define HC_INDEX_DATA_HC_ENABLED (0x1<<1) 5262 #define HC_INDEX_DATA_HC_ENABLED_SHIFT 1 5263 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2) 5264 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2 5265 #define HC_INDEX_DATA_RESERVE (0x1F<<3) 5266 #define HC_INDEX_DATA_RESERVE_SHIFT 3 5267 u8 timeout; 5268 #elif defined(__LITTLE_ENDIAN) 5269 u8 timeout; 5270 u8 flags; 5271 #define HC_INDEX_DATA_SM_ID (0x1<<0) 5272 #define HC_INDEX_DATA_SM_ID_SHIFT 0 5273 #define HC_INDEX_DATA_HC_ENABLED (0x1<<1) 5274 #define HC_INDEX_DATA_HC_ENABLED_SHIFT 1 5275 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2) 5276 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2 5277 #define HC_INDEX_DATA_RESERVE (0x1F<<3) 5278 #define HC_INDEX_DATA_RESERVE_SHIFT 3 5279 #endif 5280 }; 5281 5282 5283 /* 5284 * HC state-machine 5285 */ 5286 struct hc_status_block_sm { 5287 #if defined(__BIG_ENDIAN) 5288 u8 igu_seg_id; 5289 u8 igu_sb_id; 5290 u8 timer_value; 5291 u8 __flags; 5292 #elif defined(__LITTLE_ENDIAN) 5293 u8 __flags; 5294 u8 timer_value; 5295 u8 igu_sb_id; 5296 u8 igu_seg_id; 5297 #endif 5298 u32 time_to_expire; 5299 }; 5300 5301 /* 5302 * hold PCI identification variables- used in various places in firmware 5303 */ 5304 struct pci_entity { 5305 #if defined(__BIG_ENDIAN) 5306 u8 vf_valid; 5307 u8 vf_id; 5308 u8 vnic_id; 5309 u8 pf_id; 5310 #elif defined(__LITTLE_ENDIAN) 5311 u8 pf_id; 5312 u8 vnic_id; 5313 u8 vf_id; 5314 u8 vf_valid; 5315 #endif 5316 }; 5317 5318 /* 5319 * The fast-path status block meta-data, common to all chips 5320 */ 5321 struct hc_sb_data { 5322 struct regpair_native host_sb_addr; 5323 struct hc_status_block_sm state_machine[HC_SB_MAX_SM]; 5324 struct pci_entity p_func; 5325 #if defined(__BIG_ENDIAN) 5326 u8 rsrv0; 5327 u8 state; 5328 u8 dhc_qzone_id; 5329 u8 same_igu_sb_1b; 5330 #elif defined(__LITTLE_ENDIAN) 5331 u8 same_igu_sb_1b; 5332 u8 dhc_qzone_id; 5333 u8 state; 5334 u8 rsrv0; 5335 #endif 5336 struct regpair_native rsrv1[2]; 5337 }; 5338 5339 5340 /* 5341 * Segment types for host coaslescing 5342 */ 5343 enum hc_segment { 5344 HC_REGULAR_SEGMENT, 5345 HC_DEFAULT_SEGMENT, 5346 MAX_HC_SEGMENT 5347 }; 5348 5349 5350 /* 5351 * The fast-path status block meta-data 5352 */ 5353 struct hc_sp_status_block_data { 5354 struct regpair_native host_sb_addr; 5355 #if defined(__BIG_ENDIAN) 5356 u8 rsrv1; 5357 u8 state; 5358 u8 igu_seg_id; 5359 u8 igu_sb_id; 5360 #elif defined(__LITTLE_ENDIAN) 5361 u8 igu_sb_id; 5362 u8 igu_seg_id; 5363 u8 state; 5364 u8 rsrv1; 5365 #endif 5366 struct pci_entity p_func; 5367 }; 5368 5369 5370 /* 5371 * The fast-path status block meta-data 5372 */ 5373 struct hc_status_block_data_e1x { 5374 struct hc_index_data index_data[HC_SB_MAX_INDICES_E1X]; 5375 struct hc_sb_data common; 5376 }; 5377 5378 5379 /* 5380 * The fast-path status block meta-data 5381 */ 5382 struct hc_status_block_data_e2 { 5383 struct hc_index_data index_data[HC_SB_MAX_INDICES_E2]; 5384 struct hc_sb_data common; 5385 }; 5386 5387 5388 /* 5389 * IGU block operartion modes (in Everest2) 5390 */ 5391 enum igu_mode { 5392 HC_IGU_BC_MODE, 5393 HC_IGU_NBC_MODE, 5394 MAX_IGU_MODE 5395 }; 5396 5397 5398 /* 5399 * IP versions 5400 */ 5401 enum ip_ver { 5402 IP_V4, 5403 IP_V6, 5404 MAX_IP_VER 5405 }; 5406 5407 /* 5408 * Malicious VF error ID 5409 */ 5410 enum malicious_vf_error_id { 5411 VF_PF_CHANNEL_NOT_READY, 5412 ETH_ILLEGAL_BD_LENGTHS, 5413 ETH_PACKET_TOO_SHORT, 5414 ETH_PAYLOAD_TOO_BIG, 5415 ETH_ILLEGAL_ETH_TYPE, 5416 ETH_ILLEGAL_LSO_HDR_LEN, 5417 ETH_TOO_MANY_BDS, 5418 ETH_ZERO_HDR_NBDS, 5419 ETH_START_BD_NOT_SET, 5420 ETH_ILLEGAL_PARSE_NBDS, 5421 ETH_IPV6_AND_CHECKSUM, 5422 ETH_VLAN_FLG_INCORRECT, 5423 ETH_ILLEGAL_LSO_MSS, 5424 ETH_TUNNEL_NOT_SUPPORTED, 5425 MAX_MALICIOUS_VF_ERROR_ID 5426 }; 5427 5428 /* 5429 * Multi-function modes 5430 */ 5431 enum mf_mode { 5432 SINGLE_FUNCTION, 5433 MULTI_FUNCTION_SD, 5434 MULTI_FUNCTION_SI, 5435 MULTI_FUNCTION_AFEX, 5436 MAX_MF_MODE 5437 }; 5438 5439 /* 5440 * Protocol-common statistics collected by the Tstorm (per pf) 5441 */ 5442 struct tstorm_per_pf_stats { 5443 struct regpair rcv_error_bytes; 5444 }; 5445 5446 /* 5447 * 5448 */ 5449 struct per_pf_stats { 5450 struct tstorm_per_pf_stats tstorm_pf_statistics; 5451 }; 5452 5453 5454 /* 5455 * Protocol-common statistics collected by the Tstorm (per port) 5456 */ 5457 struct tstorm_per_port_stats { 5458 __le32 mac_discard; 5459 __le32 mac_filter_discard; 5460 __le32 brb_truncate_discard; 5461 __le32 mf_tag_discard; 5462 __le32 packet_drop; 5463 __le32 reserved; 5464 }; 5465 5466 /* 5467 * 5468 */ 5469 struct per_port_stats { 5470 struct tstorm_per_port_stats tstorm_port_statistics; 5471 }; 5472 5473 5474 /* 5475 * Protocol-common statistics collected by the Tstorm (per client) 5476 */ 5477 struct tstorm_per_queue_stats { 5478 struct regpair rcv_ucast_bytes; 5479 __le32 rcv_ucast_pkts; 5480 __le32 checksum_discard; 5481 struct regpair rcv_bcast_bytes; 5482 __le32 rcv_bcast_pkts; 5483 __le32 pkts_too_big_discard; 5484 struct regpair rcv_mcast_bytes; 5485 __le32 rcv_mcast_pkts; 5486 __le32 ttl0_discard; 5487 __le16 no_buff_discard; 5488 __le16 reserved0; 5489 __le32 reserved1; 5490 }; 5491 5492 /* 5493 * Protocol-common statistics collected by the Ustorm (per client) 5494 */ 5495 struct ustorm_per_queue_stats { 5496 struct regpair ucast_no_buff_bytes; 5497 struct regpair mcast_no_buff_bytes; 5498 struct regpair bcast_no_buff_bytes; 5499 __le32 ucast_no_buff_pkts; 5500 __le32 mcast_no_buff_pkts; 5501 __le32 bcast_no_buff_pkts; 5502 __le32 coalesced_pkts; 5503 struct regpair coalesced_bytes; 5504 __le32 coalesced_events; 5505 __le32 coalesced_aborts; 5506 }; 5507 5508 /* 5509 * Protocol-common statistics collected by the Xstorm (per client) 5510 */ 5511 struct xstorm_per_queue_stats { 5512 struct regpair ucast_bytes_sent; 5513 struct regpair mcast_bytes_sent; 5514 struct regpair bcast_bytes_sent; 5515 __le32 ucast_pkts_sent; 5516 __le32 mcast_pkts_sent; 5517 __le32 bcast_pkts_sent; 5518 __le32 error_drop_pkts; 5519 }; 5520 5521 /* 5522 * 5523 */ 5524 struct per_queue_stats { 5525 struct tstorm_per_queue_stats tstorm_queue_statistics; 5526 struct ustorm_per_queue_stats ustorm_queue_statistics; 5527 struct xstorm_per_queue_stats xstorm_queue_statistics; 5528 }; 5529 5530 5531 /* 5532 * FW version stored in first line of pram 5533 */ 5534 struct pram_fw_version { 5535 u8 major; 5536 u8 minor; 5537 u8 revision; 5538 u8 engineering; 5539 u8 flags; 5540 #define PRAM_FW_VERSION_OPTIMIZED (0x1<<0) 5541 #define PRAM_FW_VERSION_OPTIMIZED_SHIFT 0 5542 #define PRAM_FW_VERSION_STORM_ID (0x3<<1) 5543 #define PRAM_FW_VERSION_STORM_ID_SHIFT 1 5544 #define PRAM_FW_VERSION_BIG_ENDIEN (0x1<<3) 5545 #define PRAM_FW_VERSION_BIG_ENDIEN_SHIFT 3 5546 #define PRAM_FW_VERSION_CHIP_VERSION (0x3<<4) 5547 #define PRAM_FW_VERSION_CHIP_VERSION_SHIFT 4 5548 #define __PRAM_FW_VERSION_RESERVED0 (0x3<<6) 5549 #define __PRAM_FW_VERSION_RESERVED0_SHIFT 6 5550 }; 5551 5552 5553 /* 5554 * Ethernet slow path element 5555 */ 5556 union protocol_common_specific_data { 5557 u8 protocol_data[8]; 5558 struct regpair phy_address; 5559 struct regpair mac_config_addr; 5560 struct afex_vif_list_ramrod_data afex_vif_list_data; 5561 }; 5562 5563 /* 5564 * The send queue element 5565 */ 5566 struct protocol_common_spe { 5567 struct spe_hdr hdr; 5568 union protocol_common_specific_data data; 5569 }; 5570 5571 /* 5572 * The send queue element 5573 */ 5574 struct slow_path_element { 5575 struct spe_hdr hdr; 5576 struct regpair protocol_data; 5577 }; 5578 5579 5580 /* 5581 * Protocol-common statistics counter 5582 */ 5583 struct stats_counter { 5584 __le16 xstats_counter; 5585 __le16 reserved0; 5586 __le32 reserved1; 5587 __le16 tstats_counter; 5588 __le16 reserved2; 5589 __le32 reserved3; 5590 __le16 ustats_counter; 5591 __le16 reserved4; 5592 __le32 reserved5; 5593 __le16 cstats_counter; 5594 __le16 reserved6; 5595 __le32 reserved7; 5596 }; 5597 5598 5599 /* 5600 * 5601 */ 5602 struct stats_query_entry { 5603 u8 kind; 5604 u8 index; 5605 __le16 funcID; 5606 __le32 reserved; 5607 struct regpair address; 5608 }; 5609 5610 /* 5611 * statistic command 5612 */ 5613 struct stats_query_cmd_group { 5614 struct stats_query_entry query[STATS_QUERY_CMD_COUNT]; 5615 }; 5616 5617 5618 /* 5619 * statistic command header 5620 */ 5621 struct stats_query_header { 5622 u8 cmd_num; 5623 u8 reserved0; 5624 __le16 drv_stats_counter; 5625 __le32 reserved1; 5626 struct regpair stats_counters_addrs; 5627 }; 5628 5629 5630 /* 5631 * Types of statistcis query entry 5632 */ 5633 enum stats_query_type { 5634 STATS_TYPE_QUEUE, 5635 STATS_TYPE_PORT, 5636 STATS_TYPE_PF, 5637 STATS_TYPE_TOE, 5638 STATS_TYPE_FCOE, 5639 MAX_STATS_QUERY_TYPE 5640 }; 5641 5642 5643 /* 5644 * Indicate of the function status block state 5645 */ 5646 enum status_block_state { 5647 SB_DISABLED, 5648 SB_ENABLED, 5649 SB_CLEANED, 5650 MAX_STATUS_BLOCK_STATE 5651 }; 5652 5653 5654 /* 5655 * Storm IDs (including attentions for IGU related enums) 5656 */ 5657 enum storm_id { 5658 USTORM_ID, 5659 CSTORM_ID, 5660 XSTORM_ID, 5661 TSTORM_ID, 5662 ATTENTION_ID, 5663 MAX_STORM_ID 5664 }; 5665 5666 5667 /* 5668 * Taffic types used in ETS and flow control algorithms 5669 */ 5670 enum traffic_type { 5671 LLFC_TRAFFIC_TYPE_NW, 5672 LLFC_TRAFFIC_TYPE_FCOE, 5673 LLFC_TRAFFIC_TYPE_ISCSI, 5674 MAX_TRAFFIC_TYPE 5675 }; 5676 5677 5678 /* 5679 * zone A per-queue data 5680 */ 5681 struct tstorm_queue_zone_data { 5682 struct regpair reserved[4]; 5683 }; 5684 5685 5686 /* 5687 * zone B per-VF data 5688 */ 5689 struct tstorm_vf_zone_data { 5690 struct regpair reserved; 5691 }; 5692 5693 5694 /* 5695 * zone A per-queue data 5696 */ 5697 struct ustorm_queue_zone_data { 5698 struct ustorm_eth_rx_producers eth_rx_producers; 5699 struct regpair reserved[3]; 5700 }; 5701 5702 5703 /* 5704 * zone B per-VF data 5705 */ 5706 struct ustorm_vf_zone_data { 5707 struct regpair reserved; 5708 }; 5709 5710 5711 /* 5712 * data per VF-PF channel 5713 */ 5714 struct vf_pf_channel_data { 5715 #if defined(__BIG_ENDIAN) 5716 u16 reserved0; 5717 u8 valid; 5718 u8 state; 5719 #elif defined(__LITTLE_ENDIAN) 5720 u8 state; 5721 u8 valid; 5722 u16 reserved0; 5723 #endif 5724 u32 reserved1; 5725 }; 5726 5727 5728 /* 5729 * State of VF-PF channel 5730 */ 5731 enum vf_pf_channel_state { 5732 VF_PF_CHANNEL_STATE_READY, 5733 VF_PF_CHANNEL_STATE_WAITING_FOR_ACK, 5734 MAX_VF_PF_CHANNEL_STATE 5735 }; 5736 5737 5738 /* 5739 * vif_list_rule_kind 5740 */ 5741 enum vif_list_rule_kind { 5742 VIF_LIST_RULE_SET, 5743 VIF_LIST_RULE_GET, 5744 VIF_LIST_RULE_CLEAR_ALL, 5745 VIF_LIST_RULE_CLEAR_FUNC, 5746 MAX_VIF_LIST_RULE_KIND 5747 }; 5748 5749 5750 /* 5751 * zone A per-queue data 5752 */ 5753 struct xstorm_queue_zone_data { 5754 struct regpair reserved[4]; 5755 }; 5756 5757 5758 /* 5759 * zone B per-VF data 5760 */ 5761 struct xstorm_vf_zone_data { 5762 struct regpair reserved; 5763 }; 5764 5765 #endif /* BNX2X_HSI_H */ 5766