1 /* bnx2x_fw_defs.h: Broadcom Everest network driver. 2 * 3 * Copyright (c) 2007-2013 Broadcom Corporation 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation. 8 */ 9 10 #ifndef BNX2X_FW_DEFS_H 11 #define BNX2X_FW_DEFS_H 12 13 #define CSTORM_ASSERT_LIST_INDEX_OFFSET (IRO[152].base) 14 #define CSTORM_ASSERT_LIST_OFFSET(assertListEntry) \ 15 (IRO[151].base + ((assertListEntry) * IRO[151].m1)) 16 #define CSTORM_EVENT_RING_DATA_OFFSET(pfId) \ 17 (IRO[157].base + (((pfId)>>1) * IRO[157].m1) + (((pfId)&1) * \ 18 IRO[157].m2)) 19 #define CSTORM_EVENT_RING_PROD_OFFSET(pfId) \ 20 (IRO[158].base + (((pfId)>>1) * IRO[158].m1) + (((pfId)&1) * \ 21 IRO[158].m2)) 22 #define CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(funcId) \ 23 (IRO[163].base + ((funcId) * IRO[163].m1)) 24 #define CSTORM_FUNC_EN_OFFSET(funcId) \ 25 (IRO[153].base + ((funcId) * IRO[153].m1)) 26 #define CSTORM_HC_SYNC_LINE_INDEX_E1X_OFFSET(hcIndex, sbId) \ 27 (IRO[143].base + ((hcIndex) * IRO[143].m1) + ((sbId) * IRO[143].m2)) 28 #define CSTORM_HC_SYNC_LINE_INDEX_E2_OFFSET(hcIndex, sbId) \ 29 (IRO[142].base + (((hcIndex)>>2) * IRO[142].m1) + (((hcIndex)&3) \ 30 * IRO[142].m2) + ((sbId) * IRO[142].m3)) 31 #define CSTORM_IGU_MODE_OFFSET (IRO[161].base) 32 #define CSTORM_ISCSI_CQ_SIZE_OFFSET(pfId) \ 33 (IRO[323].base + ((pfId) * IRO[323].m1)) 34 #define CSTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfId) \ 35 (IRO[324].base + ((pfId) * IRO[324].m1)) 36 #define CSTORM_ISCSI_EQ_CONS_OFFSET(pfId, iscsiEqId) \ 37 (IRO[316].base + ((pfId) * IRO[316].m1) + ((iscsiEqId) * IRO[316].m2)) 38 #define CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfId, iscsiEqId) \ 39 (IRO[318].base + ((pfId) * IRO[318].m1) + ((iscsiEqId) * IRO[318].m2)) 40 #define CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfId, iscsiEqId) \ 41 (IRO[317].base + ((pfId) * IRO[317].m1) + ((iscsiEqId) * IRO[317].m2)) 42 #define CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_VALID_OFFSET(pfId, iscsiEqId) \ 43 (IRO[319].base + ((pfId) * IRO[319].m1) + ((iscsiEqId) * IRO[319].m2)) 44 #define CSTORM_ISCSI_EQ_PROD_OFFSET(pfId, iscsiEqId) \ 45 (IRO[315].base + ((pfId) * IRO[315].m1) + ((iscsiEqId) * IRO[315].m2)) 46 #define CSTORM_ISCSI_EQ_SB_INDEX_OFFSET(pfId, iscsiEqId) \ 47 (IRO[321].base + ((pfId) * IRO[321].m1) + ((iscsiEqId) * IRO[321].m2)) 48 #define CSTORM_ISCSI_EQ_SB_NUM_OFFSET(pfId, iscsiEqId) \ 49 (IRO[320].base + ((pfId) * IRO[320].m1) + ((iscsiEqId) * IRO[320].m2)) 50 #define CSTORM_ISCSI_HQ_SIZE_OFFSET(pfId) \ 51 (IRO[322].base + ((pfId) * IRO[322].m1)) 52 #define CSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) \ 53 (IRO[314].base + ((pfId) * IRO[314].m1)) 54 #define CSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) \ 55 (IRO[313].base + ((pfId) * IRO[313].m1)) 56 #define CSTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) \ 57 (IRO[312].base + ((pfId) * IRO[312].m1)) 58 #define CSTORM_RECORD_SLOW_PATH_OFFSET(funcId) \ 59 (IRO[155].base + ((funcId) * IRO[155].m1)) 60 #define CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(pfId) \ 61 (IRO[146].base + ((pfId) * IRO[146].m1)) 62 #define CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(pfId) \ 63 (IRO[147].base + ((pfId) * IRO[147].m1)) 64 #define CSTORM_SP_STATUS_BLOCK_OFFSET(pfId) \ 65 (IRO[145].base + ((pfId) * IRO[145].m1)) 66 #define CSTORM_SP_STATUS_BLOCK_SIZE (IRO[145].size) 67 #define CSTORM_SP_SYNC_BLOCK_OFFSET(pfId) \ 68 (IRO[148].base + ((pfId) * IRO[148].m1)) 69 #define CSTORM_SP_SYNC_BLOCK_SIZE (IRO[148].size) 70 #define CSTORM_STATUS_BLOCK_DATA_FLAGS_OFFSET(sbId, hcIndex) \ 71 (IRO[140].base + ((sbId) * IRO[140].m1) + ((hcIndex) * IRO[140].m2)) 72 #define CSTORM_STATUS_BLOCK_DATA_OFFSET(sbId) \ 73 (IRO[137].base + ((sbId) * IRO[137].m1)) 74 #define CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(sbId) \ 75 (IRO[138].base + ((sbId) * IRO[138].m1)) 76 #define CSTORM_STATUS_BLOCK_DATA_TIMEOUT_OFFSET(sbId, hcIndex) \ 77 (IRO[139].base + ((sbId) * IRO[139].m1) + ((hcIndex) * IRO[139].m2)) 78 #define CSTORM_STATUS_BLOCK_OFFSET(sbId) \ 79 (IRO[136].base + ((sbId) * IRO[136].m1)) 80 #define CSTORM_STATUS_BLOCK_SIZE (IRO[136].size) 81 #define CSTORM_SYNC_BLOCK_OFFSET(sbId) \ 82 (IRO[141].base + ((sbId) * IRO[141].m1)) 83 #define CSTORM_SYNC_BLOCK_SIZE (IRO[141].size) 84 #define CSTORM_VF_PF_CHANNEL_STATE_OFFSET(vfId) \ 85 (IRO[159].base + ((vfId) * IRO[159].m1)) 86 #define CSTORM_VF_PF_CHANNEL_VALID_OFFSET(vfId) \ 87 (IRO[160].base + ((vfId) * IRO[160].m1)) 88 #define CSTORM_VF_TO_PF_OFFSET(funcId) \ 89 (IRO[154].base + ((funcId) * IRO[154].m1)) 90 #define TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(pfId) \ 91 (IRO[207].base + ((pfId) * IRO[207].m1)) 92 #define TSTORM_ASSERT_LIST_INDEX_OFFSET (IRO[102].base) 93 #define TSTORM_ASSERT_LIST_OFFSET(assertListEntry) \ 94 (IRO[101].base + ((assertListEntry) * IRO[101].m1)) 95 #define TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(pfId) \ 96 (IRO[205].base + ((pfId) * IRO[205].m1)) 97 #define TSTORM_FUNC_EN_OFFSET(funcId) \ 98 (IRO[107].base + ((funcId) * IRO[107].m1)) 99 #define TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfId) \ 100 (IRO[278].base + ((pfId) * IRO[278].m1)) 101 #define TSTORM_ISCSI_L2_ISCSI_OOO_CID_TABLE_OFFSET(pfId) \ 102 (IRO[279].base + ((pfId) * IRO[279].m1)) 103 #define TSTORM_ISCSI_L2_ISCSI_OOO_CLIENT_ID_TABLE_OFFSET(pfId) \ 104 (IRO[280].base + ((pfId) * IRO[280].m1)) 105 #define TSTORM_ISCSI_L2_ISCSI_OOO_PROD_OFFSET(pfId) \ 106 (IRO[281].base + ((pfId) * IRO[281].m1)) 107 #define TSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) \ 108 (IRO[277].base + ((pfId) * IRO[277].m1)) 109 #define TSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) \ 110 (IRO[276].base + ((pfId) * IRO[276].m1)) 111 #define TSTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) \ 112 (IRO[275].base + ((pfId) * IRO[275].m1)) 113 #define TSTORM_ISCSI_RQ_SIZE_OFFSET(pfId) \ 114 (IRO[274].base + ((pfId) * IRO[274].m1)) 115 #define TSTORM_ISCSI_TCP_LOCAL_ADV_WND_OFFSET(pfId) \ 116 (IRO[284].base + ((pfId) * IRO[284].m1)) 117 #define TSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(pfId) \ 118 (IRO[270].base + ((pfId) * IRO[270].m1)) 119 #define TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfId) \ 120 (IRO[271].base + ((pfId) * IRO[271].m1)) 121 #define TSTORM_ISCSI_TCP_VARS_MID_LOCAL_MAC_ADDR_OFFSET(pfId) \ 122 (IRO[272].base + ((pfId) * IRO[272].m1)) 123 #define TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfId) \ 124 (IRO[273].base + ((pfId) * IRO[273].m1)) 125 #define TSTORM_MAC_FILTER_CONFIG_OFFSET(pfId) \ 126 (IRO[206].base + ((pfId) * IRO[206].m1)) 127 #define TSTORM_RECORD_SLOW_PATH_OFFSET(funcId) \ 128 (IRO[109].base + ((funcId) * IRO[109].m1)) 129 #define TSTORM_TCP_MAX_CWND_OFFSET(pfId) \ 130 (IRO[223].base + ((pfId) * IRO[223].m1)) 131 #define TSTORM_VF_TO_PF_OFFSET(funcId) \ 132 (IRO[108].base + ((funcId) * IRO[108].m1)) 133 #define USTORM_AGG_DATA_OFFSET (IRO[212].base) 134 #define USTORM_AGG_DATA_SIZE (IRO[212].size) 135 #define USTORM_ASSERT_LIST_INDEX_OFFSET (IRO[181].base) 136 #define USTORM_ASSERT_LIST_OFFSET(assertListEntry) \ 137 (IRO[180].base + ((assertListEntry) * IRO[180].m1)) 138 #define USTORM_ETH_PAUSE_ENABLED_OFFSET(portId) \ 139 (IRO[187].base + ((portId) * IRO[187].m1)) 140 #define USTORM_FCOE_EQ_PROD_OFFSET(pfId) \ 141 (IRO[325].base + ((pfId) * IRO[325].m1)) 142 #define USTORM_FUNC_EN_OFFSET(funcId) \ 143 (IRO[182].base + ((funcId) * IRO[182].m1)) 144 #define USTORM_ISCSI_CQ_SIZE_OFFSET(pfId) \ 145 (IRO[289].base + ((pfId) * IRO[289].m1)) 146 #define USTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfId) \ 147 (IRO[290].base + ((pfId) * IRO[290].m1)) 148 #define USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfId) \ 149 (IRO[294].base + ((pfId) * IRO[294].m1)) 150 #define USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfId) \ 151 (IRO[291].base + ((pfId) * IRO[291].m1)) 152 #define USTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) \ 153 (IRO[287].base + ((pfId) * IRO[287].m1)) 154 #define USTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) \ 155 (IRO[286].base + ((pfId) * IRO[286].m1)) 156 #define USTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) \ 157 (IRO[285].base + ((pfId) * IRO[285].m1)) 158 #define USTORM_ISCSI_R2TQ_SIZE_OFFSET(pfId) \ 159 (IRO[288].base + ((pfId) * IRO[288].m1)) 160 #define USTORM_ISCSI_RQ_BUFFER_SIZE_OFFSET(pfId) \ 161 (IRO[292].base + ((pfId) * IRO[292].m1)) 162 #define USTORM_ISCSI_RQ_SIZE_OFFSET(pfId) \ 163 (IRO[293].base + ((pfId) * IRO[293].m1)) 164 #define USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(pfId) \ 165 (IRO[186].base + ((pfId) * IRO[186].m1)) 166 #define USTORM_RECORD_SLOW_PATH_OFFSET(funcId) \ 167 (IRO[184].base + ((funcId) * IRO[184].m1)) 168 #define USTORM_RX_PRODS_E1X_OFFSET(portId, clientId) \ 169 (IRO[215].base + ((portId) * IRO[215].m1) + ((clientId) * \ 170 IRO[215].m2)) 171 #define USTORM_RX_PRODS_E2_OFFSET(qzoneId) \ 172 (IRO[216].base + ((qzoneId) * IRO[216].m1)) 173 #define USTORM_TPA_BTR_OFFSET (IRO[213].base) 174 #define USTORM_TPA_BTR_SIZE (IRO[213].size) 175 #define USTORM_VF_TO_PF_OFFSET(funcId) \ 176 (IRO[183].base + ((funcId) * IRO[183].m1)) 177 #define XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE (IRO[67].base) 178 #define XSTORM_AGG_INT_FINAL_CLEANUP_INDEX (IRO[66].base) 179 #define XSTORM_ASSERT_LIST_INDEX_OFFSET (IRO[51].base) 180 #define XSTORM_ASSERT_LIST_OFFSET(assertListEntry) \ 181 (IRO[50].base + ((assertListEntry) * IRO[50].m1)) 182 #define XSTORM_CMNG_PER_PORT_VARS_OFFSET(portId) \ 183 (IRO[43].base + ((portId) * IRO[43].m1)) 184 #define XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(pfId) \ 185 (IRO[45].base + ((pfId) * IRO[45].m1)) 186 #define XSTORM_FUNC_EN_OFFSET(funcId) \ 187 (IRO[47].base + ((funcId) * IRO[47].m1)) 188 #define XSTORM_ISCSI_HQ_SIZE_OFFSET(pfId) \ 189 (IRO[302].base + ((pfId) * IRO[302].m1)) 190 #define XSTORM_ISCSI_LOCAL_MAC_ADDR0_OFFSET(pfId) \ 191 (IRO[305].base + ((pfId) * IRO[305].m1)) 192 #define XSTORM_ISCSI_LOCAL_MAC_ADDR1_OFFSET(pfId) \ 193 (IRO[306].base + ((pfId) * IRO[306].m1)) 194 #define XSTORM_ISCSI_LOCAL_MAC_ADDR2_OFFSET(pfId) \ 195 (IRO[307].base + ((pfId) * IRO[307].m1)) 196 #define XSTORM_ISCSI_LOCAL_MAC_ADDR3_OFFSET(pfId) \ 197 (IRO[308].base + ((pfId) * IRO[308].m1)) 198 #define XSTORM_ISCSI_LOCAL_MAC_ADDR4_OFFSET(pfId) \ 199 (IRO[309].base + ((pfId) * IRO[309].m1)) 200 #define XSTORM_ISCSI_LOCAL_MAC_ADDR5_OFFSET(pfId) \ 201 (IRO[310].base + ((pfId) * IRO[310].m1)) 202 #define XSTORM_ISCSI_LOCAL_VLAN_OFFSET(pfId) \ 203 (IRO[311].base + ((pfId) * IRO[311].m1)) 204 #define XSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) \ 205 (IRO[301].base + ((pfId) * IRO[301].m1)) 206 #define XSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) \ 207 (IRO[300].base + ((pfId) * IRO[300].m1)) 208 #define XSTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) \ 209 (IRO[299].base + ((pfId) * IRO[299].m1)) 210 #define XSTORM_ISCSI_R2TQ_SIZE_OFFSET(pfId) \ 211 (IRO[304].base + ((pfId) * IRO[304].m1)) 212 #define XSTORM_ISCSI_SQ_SIZE_OFFSET(pfId) \ 213 (IRO[303].base + ((pfId) * IRO[303].m1)) 214 #define XSTORM_ISCSI_TCP_VARS_ADV_WND_SCL_OFFSET(pfId) \ 215 (IRO[298].base + ((pfId) * IRO[298].m1)) 216 #define XSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(pfId) \ 217 (IRO[297].base + ((pfId) * IRO[297].m1)) 218 #define XSTORM_ISCSI_TCP_VARS_TOS_OFFSET(pfId) \ 219 (IRO[296].base + ((pfId) * IRO[296].m1)) 220 #define XSTORM_ISCSI_TCP_VARS_TTL_OFFSET(pfId) \ 221 (IRO[295].base + ((pfId) * IRO[295].m1)) 222 #define XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(pfId) \ 223 (IRO[44].base + ((pfId) * IRO[44].m1)) 224 #define XSTORM_RECORD_SLOW_PATH_OFFSET(funcId) \ 225 (IRO[49].base + ((funcId) * IRO[49].m1)) 226 #define XSTORM_SPQ_DATA_OFFSET(funcId) \ 227 (IRO[32].base + ((funcId) * IRO[32].m1)) 228 #define XSTORM_SPQ_DATA_SIZE (IRO[32].size) 229 #define XSTORM_SPQ_PAGE_BASE_OFFSET(funcId) \ 230 (IRO[30].base + ((funcId) * IRO[30].m1)) 231 #define XSTORM_SPQ_PROD_OFFSET(funcId) \ 232 (IRO[31].base + ((funcId) * IRO[31].m1)) 233 #define XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_ENABLED_OFFSET(portId) \ 234 (IRO[217].base + ((portId) * IRO[217].m1)) 235 #define XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_MAX_COUNT_OFFSET(portId) \ 236 (IRO[218].base + ((portId) * IRO[218].m1)) 237 #define XSTORM_TCP_TX_SWS_TIMER_VAL_OFFSET(pfId) \ 238 (IRO[220].base + (((pfId)>>1) * IRO[220].m1) + (((pfId)&1) * \ 239 IRO[220].m2)) 240 #define XSTORM_VF_TO_PF_OFFSET(funcId) \ 241 (IRO[48].base + ((funcId) * IRO[48].m1)) 242 #define COMMON_ASM_INVALID_ASSERT_OPCODE 0x0 243 244 /* eth hsi version */ 245 #define ETH_FP_HSI_VERSION (ETH_FP_HSI_VER_2) 246 247 /* Ethernet Ring parameters */ 248 #define X_ETH_LOCAL_RING_SIZE 13 249 #define FIRST_BD_IN_PKT 0 250 #define PARSE_BD_INDEX 1 251 #define NUM_OF_ETH_BDS_IN_PAGE ((PAGE_SIZE)/(STRUCT_SIZE(eth_tx_bd)/8)) 252 #define U_ETH_NUM_OF_SGES_TO_FETCH 8 253 #define U_ETH_MAX_SGES_FOR_PACKET 3 254 255 /* Rx ring params */ 256 #define U_ETH_LOCAL_BD_RING_SIZE 8 257 #define U_ETH_LOCAL_SGE_RING_SIZE 10 258 #define U_ETH_SGL_SIZE 8 259 /* The fw will padd the buffer with this value, so the IP header \ 260 will be align to 4 Byte */ 261 #define IP_HEADER_ALIGNMENT_PADDING 2 262 263 #define U_ETH_SGES_PER_PAGE_INVERSE_MASK \ 264 (0xFFFF - ((PAGE_SIZE/((STRUCT_SIZE(eth_rx_sge))/8))-1)) 265 266 #define TU_ETH_CQES_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_cqe)/8)) 267 #define U_ETH_BDS_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_bd)/8)) 268 #define U_ETH_SGES_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_sge)/8)) 269 270 #define U_ETH_BDS_PER_PAGE_MASK (U_ETH_BDS_PER_PAGE-1) 271 #define U_ETH_CQE_PER_PAGE_MASK (TU_ETH_CQES_PER_PAGE-1) 272 #define U_ETH_SGES_PER_PAGE_MASK (U_ETH_SGES_PER_PAGE-1) 273 274 #define U_ETH_UNDEFINED_Q 0xFF 275 276 #define T_ETH_INDIRECTION_TABLE_SIZE 128 277 #define T_ETH_RSS_KEY 10 278 #define ETH_NUM_OF_RSS_ENGINES_E2 72 279 280 #define FILTER_RULES_COUNT 16 281 #define MULTICAST_RULES_COUNT 16 282 #define CLASSIFY_RULES_COUNT 16 283 284 /*The CRC32 seed, that is used for the hash(reduction) multicast address */ 285 #define ETH_CRC32_HASH_SEED 0x00000000 286 287 #define ETH_CRC32_HASH_BIT_SIZE (8) 288 #define ETH_CRC32_HASH_MASK EVAL((1<<ETH_CRC32_HASH_BIT_SIZE)-1) 289 290 /* Maximal L2 clients supported */ 291 #define ETH_MAX_RX_CLIENTS_E1 18 292 #define ETH_MAX_RX_CLIENTS_E1H 28 293 #define ETH_MAX_RX_CLIENTS_E2 152 294 295 /* Maximal statistics client Ids */ 296 #define MAX_STAT_COUNTER_ID_E1 36 297 #define MAX_STAT_COUNTER_ID_E1H 56 298 #define MAX_STAT_COUNTER_ID_E2 140 299 300 #define MAX_MAC_CREDIT_E1 192 /* Per Chip */ 301 #define MAX_MAC_CREDIT_E1H 256 /* Per Chip */ 302 #define MAX_MAC_CREDIT_E2 272 /* Per Path */ 303 #define MAX_VLAN_CREDIT_E1 0 /* Per Chip */ 304 #define MAX_VLAN_CREDIT_E1H 0 /* Per Chip */ 305 #define MAX_VLAN_CREDIT_E2 272 /* Per Path */ 306 307 /* Maximal aggregation queues supported */ 308 #define ETH_MAX_AGGREGATION_QUEUES_E1 32 309 #define ETH_MAX_AGGREGATION_QUEUES_E1H_E2 64 310 311 #define ETH_NUM_OF_MCAST_BINS 256 312 #define ETH_NUM_OF_MCAST_ENGINES_E2 72 313 314 #define ETH_MIN_RX_CQES_WITHOUT_TPA (MAX_RAMRODS_PER_PORT + 3) 315 #define ETH_MIN_RX_CQES_WITH_TPA_E1 \ 316 (ETH_MAX_AGGREGATION_QUEUES_E1 + ETH_MIN_RX_CQES_WITHOUT_TPA) 317 #define ETH_MIN_RX_CQES_WITH_TPA_E1H_E2 \ 318 (ETH_MAX_AGGREGATION_QUEUES_E1H_E2 + ETH_MIN_RX_CQES_WITHOUT_TPA) 319 320 #define DISABLE_STATISTIC_COUNTER_ID_VALUE 0 321 322 323 /* This file defines HSI constants common to all microcode flows */ 324 325 #define PROTOCOL_STATE_BIT_OFFSET 6 326 327 #define ETH_STATE (ETH_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET) 328 #define TOE_STATE (TOE_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET) 329 #define RDMA_STATE (RDMA_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET) 330 331 /* microcode fixed page page size 4K (chains and ring segments) */ 332 #define MC_PAGE_SIZE 4096 333 334 /* Number of indices per slow-path SB */ 335 #define HC_SP_SB_MAX_INDICES 16 336 337 /* Number of indices per SB */ 338 #define HC_SB_MAX_INDICES_E1X 8 339 #define HC_SB_MAX_INDICES_E2 8 340 341 #define HC_SB_MAX_SB_E1X 32 342 #define HC_SB_MAX_SB_E2 136 343 344 #define HC_SP_SB_ID 0xde 345 346 #define HC_SB_MAX_SM 2 347 348 #define HC_SB_MAX_DYNAMIC_INDICES 4 349 350 /* max number of slow path commands per port */ 351 #define MAX_RAMRODS_PER_PORT 8 352 353 /**** DEFINES FOR TIMERS/CLOCKS RESOLUTIONS ****/ 354 355 #define TIMERS_TICK_SIZE_CHIP (1e-3) 356 357 #define TSEMI_CLK1_RESUL_CHIP (1e-3) 358 359 #define XSEMI_CLK1_RESUL_CHIP (1e-3) 360 361 #define SDM_TIMER_TICK_RESUL_CHIP (4 * (1e-6)) 362 #define TSDM_TIMER_TICK_RESUL_CHIP (1 * (1e-6)) 363 364 /**** END DEFINES FOR TIMERS/CLOCKS RESOLUTIONS ****/ 365 366 #define XSTORM_IP_ID_ROLL_HALF 0x8000 367 #define XSTORM_IP_ID_ROLL_ALL 0 368 369 #define FW_LOG_LIST_SIZE 50 370 371 #define NUM_OF_SAFC_BITS 16 372 #define MAX_COS_NUMBER 4 373 #define MAX_TRAFFIC_TYPES 8 374 #define MAX_PFC_PRIORITIES 8 375 376 /* used by array traffic_type_to_priority[] to mark traffic type \ 377 that is not mapped to priority*/ 378 #define LLFC_TRAFFIC_TYPE_TO_PRIORITY_UNMAPPED 0xFF 379 380 #define C_ERES_PER_PAGE \ 381 (PAGE_SIZE / BITS_TO_BYTES(STRUCT_SIZE(event_ring_elem))) 382 #define C_ERE_PER_PAGE_MASK (C_ERES_PER_PAGE - 1) 383 384 #define STATS_QUERY_CMD_COUNT 16 385 386 #define AFEX_LIST_TABLE_SIZE 4096 387 388 #define INVALID_VNIC_ID 0xFF 389 390 #define UNDEF_IRO 0x80000000 391 392 /* used for defining the amount of FCoE tasks supported for PF */ 393 #define MAX_FCOE_FUNCS_PER_ENGINE 2 394 #define MAX_NUM_FCOE_TASKS_PER_ENGINE 4096 395 396 #endif /* BNX2X_FW_DEFS_H */ 397