1 /* bnx2x_cmn.h: Broadcom Everest network driver. 2 * 3 * Copyright (c) 2007-2013 Broadcom Corporation 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation. 8 * 9 * Maintained by: Eilon Greenstein <eilong@broadcom.com> 10 * Written by: Eliezer Tamir 11 * Based on code from Michael Chan's bnx2 driver 12 * UDP CSUM errata workaround by Arik Gendelman 13 * Slowpath and fastpath rework by Vladislav Zolotarov 14 * Statistics and Link management by Yitchak Gertner 15 * 16 */ 17 #ifndef BNX2X_CMN_H 18 #define BNX2X_CMN_H 19 20 #include <linux/types.h> 21 #include <linux/pci.h> 22 #include <linux/netdevice.h> 23 #include <linux/etherdevice.h> 24 25 26 #include "bnx2x.h" 27 #include "bnx2x_sriov.h" 28 29 /* This is used as a replacement for an MCP if it's not present */ 30 extern int load_count[2][3]; /* per-path: 0-common, 1-port0, 2-port1 */ 31 32 extern int num_queues; 33 extern int int_mode; 34 35 /************************ Macros ********************************/ 36 #define BNX2X_PCI_FREE(x, y, size) \ 37 do { \ 38 if (x) { \ 39 dma_free_coherent(&bp->pdev->dev, size, (void *)x, y); \ 40 x = NULL; \ 41 y = 0; \ 42 } \ 43 } while (0) 44 45 #define BNX2X_FREE(x) \ 46 do { \ 47 if (x) { \ 48 kfree((void *)x); \ 49 x = NULL; \ 50 } \ 51 } while (0) 52 53 #define BNX2X_PCI_ALLOC(x, y, size) \ 54 do { \ 55 x = dma_alloc_coherent(&bp->pdev->dev, size, y, \ 56 GFP_KERNEL | __GFP_ZERO); \ 57 if (x == NULL) \ 58 goto alloc_mem_err; \ 59 } while (0) 60 61 #define BNX2X_ALLOC(x, size) \ 62 do { \ 63 x = kzalloc(size, GFP_KERNEL); \ 64 if (x == NULL) \ 65 goto alloc_mem_err; \ 66 } while (0) 67 68 /*********************** Interfaces **************************** 69 * Functions that need to be implemented by each driver version 70 */ 71 /* Init */ 72 73 /** 74 * bnx2x_send_unload_req - request unload mode from the MCP. 75 * 76 * @bp: driver handle 77 * @unload_mode: requested function's unload mode 78 * 79 * Return unload mode returned by the MCP: COMMON, PORT or FUNC. 80 */ 81 u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode); 82 83 /** 84 * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP. 85 * 86 * @bp: driver handle 87 * @keep_link: true iff link should be kept up 88 */ 89 void bnx2x_send_unload_done(struct bnx2x *bp, bool keep_link); 90 91 /** 92 * bnx2x_config_rss_pf - configure RSS parameters in a PF. 93 * 94 * @bp: driver handle 95 * @rss_obj: RSS object to use 96 * @ind_table: indirection table to configure 97 * @config_hash: re-configure RSS hash keys configuration 98 */ 99 int bnx2x_config_rss_pf(struct bnx2x *bp, struct bnx2x_rss_config_obj *rss_obj, 100 bool config_hash); 101 102 /** 103 * bnx2x__init_func_obj - init function object 104 * 105 * @bp: driver handle 106 * 107 * Initializes the Function Object with the appropriate 108 * parameters which include a function slow path driver 109 * interface. 110 */ 111 void bnx2x__init_func_obj(struct bnx2x *bp); 112 113 /** 114 * bnx2x_setup_queue - setup eth queue. 115 * 116 * @bp: driver handle 117 * @fp: pointer to the fastpath structure 118 * @leading: boolean 119 * 120 */ 121 int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp, 122 bool leading); 123 124 /** 125 * bnx2x_setup_leading - bring up a leading eth queue. 126 * 127 * @bp: driver handle 128 */ 129 int bnx2x_setup_leading(struct bnx2x *bp); 130 131 /** 132 * bnx2x_fw_command - send the MCP a request 133 * 134 * @bp: driver handle 135 * @command: request 136 * @param: request's parameter 137 * 138 * block until there is a reply 139 */ 140 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param); 141 142 /** 143 * bnx2x_initial_phy_init - initialize link parameters structure variables. 144 * 145 * @bp: driver handle 146 * @load_mode: current mode 147 */ 148 int bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode); 149 150 /** 151 * bnx2x_link_set - configure hw according to link parameters structure. 152 * 153 * @bp: driver handle 154 */ 155 void bnx2x_link_set(struct bnx2x *bp); 156 157 /** 158 * bnx2x_force_link_reset - Forces link reset, and put the PHY 159 * in reset as well. 160 * 161 * @bp: driver handle 162 */ 163 void bnx2x_force_link_reset(struct bnx2x *bp); 164 165 /** 166 * bnx2x_link_test - query link status. 167 * 168 * @bp: driver handle 169 * @is_serdes: bool 170 * 171 * Returns 0 if link is UP. 172 */ 173 u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes); 174 175 /** 176 * bnx2x_drv_pulse - write driver pulse to shmem 177 * 178 * @bp: driver handle 179 * 180 * writes the value in bp->fw_drv_pulse_wr_seq to drv_pulse mbox 181 * in the shmem. 182 */ 183 void bnx2x_drv_pulse(struct bnx2x *bp); 184 185 /** 186 * bnx2x_igu_ack_sb - update IGU with current SB value 187 * 188 * @bp: driver handle 189 * @igu_sb_id: SB id 190 * @segment: SB segment 191 * @index: SB index 192 * @op: SB operation 193 * @update: is HW update required 194 */ 195 void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment, 196 u16 index, u8 op, u8 update); 197 198 /* Disable transactions from chip to host */ 199 void bnx2x_pf_disable(struct bnx2x *bp); 200 int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val); 201 202 /** 203 * bnx2x__link_status_update - handles link status change. 204 * 205 * @bp: driver handle 206 */ 207 void bnx2x__link_status_update(struct bnx2x *bp); 208 209 /** 210 * bnx2x_link_report - report link status to upper layer. 211 * 212 * @bp: driver handle 213 */ 214 void bnx2x_link_report(struct bnx2x *bp); 215 216 /* None-atomic version of bnx2x_link_report() */ 217 void __bnx2x_link_report(struct bnx2x *bp); 218 219 /** 220 * bnx2x_get_mf_speed - calculate MF speed. 221 * 222 * @bp: driver handle 223 * 224 * Takes into account current linespeed and MF configuration. 225 */ 226 u16 bnx2x_get_mf_speed(struct bnx2x *bp); 227 228 /** 229 * bnx2x_msix_sp_int - MSI-X slowpath interrupt handler 230 * 231 * @irq: irq number 232 * @dev_instance: private instance 233 */ 234 irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance); 235 236 /** 237 * bnx2x_interrupt - non MSI-X interrupt handler 238 * 239 * @irq: irq number 240 * @dev_instance: private instance 241 */ 242 irqreturn_t bnx2x_interrupt(int irq, void *dev_instance); 243 244 /** 245 * bnx2x_cnic_notify - send command to cnic driver 246 * 247 * @bp: driver handle 248 * @cmd: command 249 */ 250 int bnx2x_cnic_notify(struct bnx2x *bp, int cmd); 251 252 /** 253 * bnx2x_setup_cnic_irq_info - provides cnic with IRQ information 254 * 255 * @bp: driver handle 256 */ 257 void bnx2x_setup_cnic_irq_info(struct bnx2x *bp); 258 259 /** 260 * bnx2x_setup_cnic_info - provides cnic with updated info 261 * 262 * @bp: driver handle 263 */ 264 void bnx2x_setup_cnic_info(struct bnx2x *bp); 265 266 /** 267 * bnx2x_int_enable - enable HW interrupts. 268 * 269 * @bp: driver handle 270 */ 271 void bnx2x_int_enable(struct bnx2x *bp); 272 273 /** 274 * bnx2x_int_disable_sync - disable interrupts. 275 * 276 * @bp: driver handle 277 * @disable_hw: true, disable HW interrupts. 278 * 279 * This function ensures that there are no 280 * ISRs or SP DPCs (sp_task) are running after it returns. 281 */ 282 void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw); 283 284 /** 285 * bnx2x_nic_init_cnic - init driver internals for cnic. 286 * 287 * @bp: driver handle 288 * @load_code: COMMON, PORT or FUNCTION 289 * 290 * Initializes: 291 * - rings 292 * - status blocks 293 * - etc. 294 */ 295 void bnx2x_nic_init_cnic(struct bnx2x *bp); 296 297 /** 298 * bnx2x_preirq_nic_init - init driver internals. 299 * 300 * @bp: driver handle 301 * 302 * Initializes: 303 * - fastpath object 304 * - fastpath rings 305 * etc. 306 */ 307 void bnx2x_pre_irq_nic_init(struct bnx2x *bp); 308 309 /** 310 * bnx2x_postirq_nic_init - init driver internals. 311 * 312 * @bp: driver handle 313 * @load_code: COMMON, PORT or FUNCTION 314 * 315 * Initializes: 316 * - status blocks 317 * - slowpath rings 318 * - etc. 319 */ 320 void bnx2x_post_irq_nic_init(struct bnx2x *bp, u32 load_code); 321 /** 322 * bnx2x_alloc_mem_cnic - allocate driver's memory for cnic. 323 * 324 * @bp: driver handle 325 */ 326 int bnx2x_alloc_mem_cnic(struct bnx2x *bp); 327 /** 328 * bnx2x_alloc_mem - allocate driver's memory. 329 * 330 * @bp: driver handle 331 */ 332 int bnx2x_alloc_mem(struct bnx2x *bp); 333 334 /** 335 * bnx2x_free_mem_cnic - release driver's memory for cnic. 336 * 337 * @bp: driver handle 338 */ 339 void bnx2x_free_mem_cnic(struct bnx2x *bp); 340 /** 341 * bnx2x_free_mem - release driver's memory. 342 * 343 * @bp: driver handle 344 */ 345 void bnx2x_free_mem(struct bnx2x *bp); 346 347 /** 348 * bnx2x_set_num_queues - set number of queues according to mode. 349 * 350 * @bp: driver handle 351 */ 352 void bnx2x_set_num_queues(struct bnx2x *bp); 353 354 /** 355 * bnx2x_chip_cleanup - cleanup chip internals. 356 * 357 * @bp: driver handle 358 * @unload_mode: COMMON, PORT, FUNCTION 359 * @keep_link: true iff link should be kept up. 360 * 361 * - Cleanup MAC configuration. 362 * - Closes clients. 363 * - etc. 364 */ 365 void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode, bool keep_link); 366 367 /** 368 * bnx2x_acquire_hw_lock - acquire HW lock. 369 * 370 * @bp: driver handle 371 * @resource: resource bit which was locked 372 */ 373 int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource); 374 375 /** 376 * bnx2x_release_hw_lock - release HW lock. 377 * 378 * @bp: driver handle 379 * @resource: resource bit which was locked 380 */ 381 int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource); 382 383 /** 384 * bnx2x_release_leader_lock - release recovery leader lock 385 * 386 * @bp: driver handle 387 */ 388 int bnx2x_release_leader_lock(struct bnx2x *bp); 389 390 /** 391 * bnx2x_set_eth_mac - configure eth MAC address in the HW 392 * 393 * @bp: driver handle 394 * @set: set or clear 395 * 396 * Configures according to the value in netdev->dev_addr. 397 */ 398 int bnx2x_set_eth_mac(struct bnx2x *bp, bool set); 399 400 /** 401 * bnx2x_set_rx_mode - set MAC filtering configurations. 402 * 403 * @dev: netdevice 404 * 405 * called with netif_tx_lock from dev_mcast.c 406 * If bp->state is OPEN, should be called with 407 * netif_addr_lock_bh() 408 */ 409 void bnx2x_set_rx_mode(struct net_device *dev); 410 411 /** 412 * bnx2x_set_storm_rx_mode - configure MAC filtering rules in a FW. 413 * 414 * @bp: driver handle 415 * 416 * If bp->state is OPEN, should be called with 417 * netif_addr_lock_bh(). 418 */ 419 int bnx2x_set_storm_rx_mode(struct bnx2x *bp); 420 421 /** 422 * bnx2x_set_q_rx_mode - configures rx_mode for a single queue. 423 * 424 * @bp: driver handle 425 * @cl_id: client id 426 * @rx_mode_flags: rx mode configuration 427 * @rx_accept_flags: rx accept configuration 428 * @tx_accept_flags: tx accept configuration (tx switch) 429 * @ramrod_flags: ramrod configuration 430 */ 431 int bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id, 432 unsigned long rx_mode_flags, 433 unsigned long rx_accept_flags, 434 unsigned long tx_accept_flags, 435 unsigned long ramrod_flags); 436 437 /* Parity errors related */ 438 void bnx2x_set_pf_load(struct bnx2x *bp); 439 bool bnx2x_clear_pf_load(struct bnx2x *bp); 440 bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print); 441 bool bnx2x_reset_is_done(struct bnx2x *bp, int engine); 442 void bnx2x_set_reset_in_progress(struct bnx2x *bp); 443 void bnx2x_set_reset_global(struct bnx2x *bp); 444 void bnx2x_disable_close_the_gate(struct bnx2x *bp); 445 int bnx2x_init_hw_func_cnic(struct bnx2x *bp); 446 447 /** 448 * bnx2x_sp_event - handle ramrods completion. 449 * 450 * @fp: fastpath handle for the event 451 * @rr_cqe: eth_rx_cqe 452 */ 453 void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe); 454 455 /** 456 * bnx2x_ilt_set_info - prepare ILT configurations. 457 * 458 * @bp: driver handle 459 */ 460 void bnx2x_ilt_set_info(struct bnx2x *bp); 461 462 /** 463 * bnx2x_ilt_set_cnic_info - prepare ILT configurations for SRC 464 * and TM. 465 * 466 * @bp: driver handle 467 */ 468 void bnx2x_ilt_set_info_cnic(struct bnx2x *bp); 469 470 /** 471 * bnx2x_dcbx_init - initialize dcbx protocol. 472 * 473 * @bp: driver handle 474 */ 475 void bnx2x_dcbx_init(struct bnx2x *bp, bool update_shmem); 476 477 /** 478 * bnx2x_set_power_state - set power state to the requested value. 479 * 480 * @bp: driver handle 481 * @state: required state D0 or D3hot 482 * 483 * Currently only D0 and D3hot are supported. 484 */ 485 int bnx2x_set_power_state(struct bnx2x *bp, pci_power_t state); 486 487 /** 488 * bnx2x_update_max_mf_config - update MAX part of MF configuration in HW. 489 * 490 * @bp: driver handle 491 * @value: new value 492 */ 493 void bnx2x_update_max_mf_config(struct bnx2x *bp, u32 value); 494 /* Error handling */ 495 void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl); 496 497 /* validate currect fw is loaded */ 498 bool bnx2x_test_firmware_version(struct bnx2x *bp, bool is_err); 499 500 /* dev_close main block */ 501 int bnx2x_nic_unload(struct bnx2x *bp, int unload_mode, bool keep_link); 502 503 /* dev_open main block */ 504 int bnx2x_nic_load(struct bnx2x *bp, int load_mode); 505 506 /* hard_xmit callback */ 507 netdev_tx_t bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev); 508 509 /* setup_tc callback */ 510 int bnx2x_setup_tc(struct net_device *dev, u8 num_tc); 511 512 int bnx2x_get_vf_config(struct net_device *dev, int vf, 513 struct ifla_vf_info *ivi); 514 int bnx2x_set_vf_mac(struct net_device *dev, int queue, u8 *mac); 515 int bnx2x_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan, u8 qos); 516 517 /* select_queue callback */ 518 u16 bnx2x_select_queue(struct net_device *dev, struct sk_buff *skb); 519 520 static inline void bnx2x_update_rx_prod(struct bnx2x *bp, 521 struct bnx2x_fastpath *fp, 522 u16 bd_prod, u16 rx_comp_prod, 523 u16 rx_sge_prod) 524 { 525 struct ustorm_eth_rx_producers rx_prods = {0}; 526 u32 i; 527 528 /* Update producers */ 529 rx_prods.bd_prod = bd_prod; 530 rx_prods.cqe_prod = rx_comp_prod; 531 rx_prods.sge_prod = rx_sge_prod; 532 533 /* Make sure that the BD and SGE data is updated before updating the 534 * producers since FW might read the BD/SGE right after the producer 535 * is updated. 536 * This is only applicable for weak-ordered memory model archs such 537 * as IA-64. The following barrier is also mandatory since FW will 538 * assumes BDs must have buffers. 539 */ 540 wmb(); 541 542 for (i = 0; i < sizeof(rx_prods)/4; i++) 543 REG_WR(bp, fp->ustorm_rx_prods_offset + i*4, 544 ((u32 *)&rx_prods)[i]); 545 546 mmiowb(); /* keep prod updates ordered */ 547 548 DP(NETIF_MSG_RX_STATUS, 549 "queue[%d]: wrote bd_prod %u cqe_prod %u sge_prod %u\n", 550 fp->index, bd_prod, rx_comp_prod, rx_sge_prod); 551 } 552 553 /* reload helper */ 554 int bnx2x_reload_if_running(struct net_device *dev); 555 556 int bnx2x_change_mac_addr(struct net_device *dev, void *p); 557 558 /* NAPI poll Rx part */ 559 int bnx2x_rx_int(struct bnx2x_fastpath *fp, int budget); 560 561 /* NAPI poll Tx part */ 562 int bnx2x_tx_int(struct bnx2x *bp, struct bnx2x_fp_txdata *txdata); 563 564 /* suspend/resume callbacks */ 565 int bnx2x_suspend(struct pci_dev *pdev, pm_message_t state); 566 int bnx2x_resume(struct pci_dev *pdev); 567 568 /* Release IRQ vectors */ 569 void bnx2x_free_irq(struct bnx2x *bp); 570 571 void bnx2x_free_fp_mem_cnic(struct bnx2x *bp); 572 void bnx2x_free_fp_mem(struct bnx2x *bp); 573 int bnx2x_alloc_fp_mem_cnic(struct bnx2x *bp); 574 int bnx2x_alloc_fp_mem(struct bnx2x *bp); 575 void bnx2x_init_rx_rings(struct bnx2x *bp); 576 void bnx2x_init_rx_rings_cnic(struct bnx2x *bp); 577 void bnx2x_free_skbs_cnic(struct bnx2x *bp); 578 void bnx2x_free_skbs(struct bnx2x *bp); 579 void bnx2x_netif_stop(struct bnx2x *bp, int disable_hw); 580 void bnx2x_netif_start(struct bnx2x *bp); 581 int bnx2x_load_cnic(struct bnx2x *bp); 582 583 /** 584 * bnx2x_enable_msix - set msix configuration. 585 * 586 * @bp: driver handle 587 * 588 * fills msix_table, requests vectors, updates num_queues 589 * according to number of available vectors. 590 */ 591 int bnx2x_enable_msix(struct bnx2x *bp); 592 593 /** 594 * bnx2x_enable_msi - request msi mode from OS, updated internals accordingly 595 * 596 * @bp: driver handle 597 */ 598 int bnx2x_enable_msi(struct bnx2x *bp); 599 600 /** 601 * bnx2x_poll - NAPI callback 602 * 603 * @napi: napi structure 604 * @budget: 605 * 606 */ 607 int bnx2x_poll(struct napi_struct *napi, int budget); 608 609 /** 610 * bnx2x_alloc_mem_bp - allocate memories outsize main driver structure 611 * 612 * @bp: driver handle 613 */ 614 int bnx2x_alloc_mem_bp(struct bnx2x *bp); 615 616 /** 617 * bnx2x_free_mem_bp - release memories outsize main driver structure 618 * 619 * @bp: driver handle 620 */ 621 void bnx2x_free_mem_bp(struct bnx2x *bp); 622 623 /** 624 * bnx2x_change_mtu - change mtu netdev callback 625 * 626 * @dev: net device 627 * @new_mtu: requested mtu 628 * 629 */ 630 int bnx2x_change_mtu(struct net_device *dev, int new_mtu); 631 632 #ifdef NETDEV_FCOE_WWNN 633 /** 634 * bnx2x_fcoe_get_wwn - return the requested WWN value for this port 635 * 636 * @dev: net_device 637 * @wwn: output buffer 638 * @type: WWN type: NETDEV_FCOE_WWNN (node) or NETDEV_FCOE_WWPN (port) 639 * 640 */ 641 int bnx2x_fcoe_get_wwn(struct net_device *dev, u64 *wwn, int type); 642 #endif 643 644 netdev_features_t bnx2x_fix_features(struct net_device *dev, 645 netdev_features_t features); 646 int bnx2x_set_features(struct net_device *dev, netdev_features_t features); 647 648 /** 649 * bnx2x_tx_timeout - tx timeout netdev callback 650 * 651 * @dev: net device 652 */ 653 void bnx2x_tx_timeout(struct net_device *dev); 654 655 /*********************** Inlines **********************************/ 656 /*********************** Fast path ********************************/ 657 static inline void bnx2x_update_fpsb_idx(struct bnx2x_fastpath *fp) 658 { 659 barrier(); /* status block is written to by the chip */ 660 fp->fp_hc_idx = fp->sb_running_index[SM_RX_ID]; 661 } 662 663 static inline void bnx2x_igu_ack_sb_gen(struct bnx2x *bp, u8 igu_sb_id, 664 u8 segment, u16 index, u8 op, 665 u8 update, u32 igu_addr) 666 { 667 struct igu_regular cmd_data = {0}; 668 669 cmd_data.sb_id_and_flags = 670 ((index << IGU_REGULAR_SB_INDEX_SHIFT) | 671 (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) | 672 (update << IGU_REGULAR_BUPDATE_SHIFT) | 673 (op << IGU_REGULAR_ENABLE_INT_SHIFT)); 674 675 DP(NETIF_MSG_INTR, "write 0x%08x to IGU addr 0x%x\n", 676 cmd_data.sb_id_and_flags, igu_addr); 677 REG_WR(bp, igu_addr, cmd_data.sb_id_and_flags); 678 679 /* Make sure that ACK is written */ 680 mmiowb(); 681 barrier(); 682 } 683 684 static inline void bnx2x_hc_ack_sb(struct bnx2x *bp, u8 sb_id, 685 u8 storm, u16 index, u8 op, u8 update) 686 { 687 u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 + 688 COMMAND_REG_INT_ACK); 689 struct igu_ack_register igu_ack; 690 691 igu_ack.status_block_index = index; 692 igu_ack.sb_id_and_flags = 693 ((sb_id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) | 694 (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) | 695 (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) | 696 (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT)); 697 698 REG_WR(bp, hc_addr, (*(u32 *)&igu_ack)); 699 700 /* Make sure that ACK is written */ 701 mmiowb(); 702 barrier(); 703 } 704 705 static inline void bnx2x_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 storm, 706 u16 index, u8 op, u8 update) 707 { 708 if (bp->common.int_block == INT_BLOCK_HC) 709 bnx2x_hc_ack_sb(bp, igu_sb_id, storm, index, op, update); 710 else { 711 u8 segment; 712 713 if (CHIP_INT_MODE_IS_BC(bp)) 714 segment = storm; 715 else if (igu_sb_id != bp->igu_dsb_id) 716 segment = IGU_SEG_ACCESS_DEF; 717 else if (storm == ATTENTION_ID) 718 segment = IGU_SEG_ACCESS_ATTN; 719 else 720 segment = IGU_SEG_ACCESS_DEF; 721 bnx2x_igu_ack_sb(bp, igu_sb_id, segment, index, op, update); 722 } 723 } 724 725 static inline u16 bnx2x_hc_ack_int(struct bnx2x *bp) 726 { 727 u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 + 728 COMMAND_REG_SIMD_MASK); 729 u32 result = REG_RD(bp, hc_addr); 730 731 barrier(); 732 return result; 733 } 734 735 static inline u16 bnx2x_igu_ack_int(struct bnx2x *bp) 736 { 737 u32 igu_addr = (BAR_IGU_INTMEM + IGU_REG_SISR_MDPC_WMASK_LSB_UPPER*8); 738 u32 result = REG_RD(bp, igu_addr); 739 740 DP(NETIF_MSG_INTR, "read 0x%08x from IGU addr 0x%x\n", 741 result, igu_addr); 742 743 barrier(); 744 return result; 745 } 746 747 static inline u16 bnx2x_ack_int(struct bnx2x *bp) 748 { 749 barrier(); 750 if (bp->common.int_block == INT_BLOCK_HC) 751 return bnx2x_hc_ack_int(bp); 752 else 753 return bnx2x_igu_ack_int(bp); 754 } 755 756 static inline int bnx2x_has_tx_work_unload(struct bnx2x_fp_txdata *txdata) 757 { 758 /* Tell compiler that consumer and producer can change */ 759 barrier(); 760 return txdata->tx_pkt_prod != txdata->tx_pkt_cons; 761 } 762 763 static inline u16 bnx2x_tx_avail(struct bnx2x *bp, 764 struct bnx2x_fp_txdata *txdata) 765 { 766 s16 used; 767 u16 prod; 768 u16 cons; 769 770 prod = txdata->tx_bd_prod; 771 cons = txdata->tx_bd_cons; 772 773 used = SUB_S16(prod, cons); 774 775 #ifdef BNX2X_STOP_ON_ERROR 776 WARN_ON(used < 0); 777 WARN_ON(used > txdata->tx_ring_size); 778 WARN_ON((txdata->tx_ring_size - used) > MAX_TX_AVAIL); 779 #endif 780 781 return (s16)(txdata->tx_ring_size) - used; 782 } 783 784 static inline int bnx2x_tx_queue_has_work(struct bnx2x_fp_txdata *txdata) 785 { 786 u16 hw_cons; 787 788 /* Tell compiler that status block fields can change */ 789 barrier(); 790 hw_cons = le16_to_cpu(*txdata->tx_cons_sb); 791 return hw_cons != txdata->tx_pkt_cons; 792 } 793 794 static inline bool bnx2x_has_tx_work(struct bnx2x_fastpath *fp) 795 { 796 u8 cos; 797 for_each_cos_in_tx_queue(fp, cos) 798 if (bnx2x_tx_queue_has_work(fp->txdata_ptr[cos])) 799 return true; 800 return false; 801 } 802 803 static inline int bnx2x_has_rx_work(struct bnx2x_fastpath *fp) 804 { 805 u16 rx_cons_sb; 806 807 /* Tell compiler that status block fields can change */ 808 barrier(); 809 rx_cons_sb = le16_to_cpu(*fp->rx_cons_sb); 810 if ((rx_cons_sb & MAX_RCQ_DESC_CNT) == MAX_RCQ_DESC_CNT) 811 rx_cons_sb++; 812 return (fp->rx_comp_cons != rx_cons_sb); 813 } 814 815 /** 816 * bnx2x_tx_disable - disables tx from stack point of view 817 * 818 * @bp: driver handle 819 */ 820 static inline void bnx2x_tx_disable(struct bnx2x *bp) 821 { 822 netif_tx_disable(bp->dev); 823 netif_carrier_off(bp->dev); 824 } 825 826 static inline void bnx2x_free_rx_sge(struct bnx2x *bp, 827 struct bnx2x_fastpath *fp, u16 index) 828 { 829 struct sw_rx_page *sw_buf = &fp->rx_page_ring[index]; 830 struct page *page = sw_buf->page; 831 struct eth_rx_sge *sge = &fp->rx_sge_ring[index]; 832 833 /* Skip "next page" elements */ 834 if (!page) 835 return; 836 837 dma_unmap_page(&bp->pdev->dev, dma_unmap_addr(sw_buf, mapping), 838 SGE_PAGES, DMA_FROM_DEVICE); 839 __free_pages(page, PAGES_PER_SGE_SHIFT); 840 841 sw_buf->page = NULL; 842 sge->addr_hi = 0; 843 sge->addr_lo = 0; 844 } 845 846 static inline void bnx2x_add_all_napi_cnic(struct bnx2x *bp) 847 { 848 int i; 849 850 /* Add NAPI objects */ 851 for_each_rx_queue_cnic(bp, i) 852 netif_napi_add(bp->dev, &bnx2x_fp(bp, i, napi), 853 bnx2x_poll, NAPI_POLL_WEIGHT); 854 } 855 856 static inline void bnx2x_add_all_napi(struct bnx2x *bp) 857 { 858 int i; 859 860 /* Add NAPI objects */ 861 for_each_eth_queue(bp, i) 862 netif_napi_add(bp->dev, &bnx2x_fp(bp, i, napi), 863 bnx2x_poll, NAPI_POLL_WEIGHT); 864 } 865 866 static inline void bnx2x_del_all_napi_cnic(struct bnx2x *bp) 867 { 868 int i; 869 870 for_each_rx_queue_cnic(bp, i) 871 netif_napi_del(&bnx2x_fp(bp, i, napi)); 872 } 873 874 static inline void bnx2x_del_all_napi(struct bnx2x *bp) 875 { 876 int i; 877 878 for_each_eth_queue(bp, i) 879 netif_napi_del(&bnx2x_fp(bp, i, napi)); 880 } 881 882 int bnx2x_set_int_mode(struct bnx2x *bp); 883 884 static inline void bnx2x_disable_msi(struct bnx2x *bp) 885 { 886 if (bp->flags & USING_MSIX_FLAG) { 887 pci_disable_msix(bp->pdev); 888 bp->flags &= ~(USING_MSIX_FLAG | USING_SINGLE_MSIX_FLAG); 889 } else if (bp->flags & USING_MSI_FLAG) { 890 pci_disable_msi(bp->pdev); 891 bp->flags &= ~USING_MSI_FLAG; 892 } 893 } 894 895 static inline int bnx2x_calc_num_queues(struct bnx2x *bp) 896 { 897 return num_queues ? 898 min_t(int, num_queues, BNX2X_MAX_QUEUES(bp)) : 899 min_t(int, netif_get_num_default_rss_queues(), 900 BNX2X_MAX_QUEUES(bp)); 901 } 902 903 static inline void bnx2x_clear_sge_mask_next_elems(struct bnx2x_fastpath *fp) 904 { 905 int i, j; 906 907 for (i = 1; i <= NUM_RX_SGE_PAGES; i++) { 908 int idx = RX_SGE_CNT * i - 1; 909 910 for (j = 0; j < 2; j++) { 911 BIT_VEC64_CLEAR_BIT(fp->sge_mask, idx); 912 idx--; 913 } 914 } 915 } 916 917 static inline void bnx2x_init_sge_ring_bit_mask(struct bnx2x_fastpath *fp) 918 { 919 /* Set the mask to all 1-s: it's faster to compare to 0 than to 0xf-s */ 920 memset(fp->sge_mask, 0xff, sizeof(fp->sge_mask)); 921 922 /* Clear the two last indices in the page to 1: 923 these are the indices that correspond to the "next" element, 924 hence will never be indicated and should be removed from 925 the calculations. */ 926 bnx2x_clear_sge_mask_next_elems(fp); 927 } 928 929 /* note that we are not allocating a new buffer, 930 * we are just moving one from cons to prod 931 * we are not creating a new mapping, 932 * so there is no need to check for dma_mapping_error(). 933 */ 934 static inline void bnx2x_reuse_rx_data(struct bnx2x_fastpath *fp, 935 u16 cons, u16 prod) 936 { 937 struct sw_rx_bd *cons_rx_buf = &fp->rx_buf_ring[cons]; 938 struct sw_rx_bd *prod_rx_buf = &fp->rx_buf_ring[prod]; 939 struct eth_rx_bd *cons_bd = &fp->rx_desc_ring[cons]; 940 struct eth_rx_bd *prod_bd = &fp->rx_desc_ring[prod]; 941 942 dma_unmap_addr_set(prod_rx_buf, mapping, 943 dma_unmap_addr(cons_rx_buf, mapping)); 944 prod_rx_buf->data = cons_rx_buf->data; 945 *prod_bd = *cons_bd; 946 } 947 948 /************************* Init ******************************************/ 949 950 /* returns func by VN for current port */ 951 static inline int func_by_vn(struct bnx2x *bp, int vn) 952 { 953 return 2 * vn + BP_PORT(bp); 954 } 955 956 static inline int bnx2x_config_rss_eth(struct bnx2x *bp, bool config_hash) 957 { 958 return bnx2x_config_rss_pf(bp, &bp->rss_conf_obj, config_hash); 959 } 960 961 /** 962 * bnx2x_func_start - init function 963 * 964 * @bp: driver handle 965 * 966 * Must be called before sending CLIENT_SETUP for the first client. 967 */ 968 static inline int bnx2x_func_start(struct bnx2x *bp) 969 { 970 struct bnx2x_func_state_params func_params = {NULL}; 971 struct bnx2x_func_start_params *start_params = 972 &func_params.params.start; 973 974 /* Prepare parameters for function state transitions */ 975 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); 976 977 func_params.f_obj = &bp->func_obj; 978 func_params.cmd = BNX2X_F_CMD_START; 979 980 /* Function parameters */ 981 start_params->mf_mode = bp->mf_mode; 982 start_params->sd_vlan_tag = bp->mf_ov; 983 984 if (CHIP_IS_E2(bp) || CHIP_IS_E3(bp)) 985 start_params->network_cos_mode = STATIC_COS; 986 else /* CHIP_IS_E1X */ 987 start_params->network_cos_mode = FW_WRR; 988 989 start_params->gre_tunnel_mode = IPGRE_TUNNEL; 990 start_params->gre_tunnel_rss = GRE_INNER_HEADERS_RSS; 991 992 return bnx2x_func_state_change(bp, &func_params); 993 } 994 995 /** 996 * bnx2x_set_fw_mac_addr - fill in a MAC address in FW format 997 * 998 * @fw_hi: pointer to upper part 999 * @fw_mid: pointer to middle part 1000 * @fw_lo: pointer to lower part 1001 * @mac: pointer to MAC address 1002 */ 1003 static inline void bnx2x_set_fw_mac_addr(__le16 *fw_hi, __le16 *fw_mid, 1004 __le16 *fw_lo, u8 *mac) 1005 { 1006 ((u8 *)fw_hi)[0] = mac[1]; 1007 ((u8 *)fw_hi)[1] = mac[0]; 1008 ((u8 *)fw_mid)[0] = mac[3]; 1009 ((u8 *)fw_mid)[1] = mac[2]; 1010 ((u8 *)fw_lo)[0] = mac[5]; 1011 ((u8 *)fw_lo)[1] = mac[4]; 1012 } 1013 1014 static inline void bnx2x_free_rx_sge_range(struct bnx2x *bp, 1015 struct bnx2x_fastpath *fp, int last) 1016 { 1017 int i; 1018 1019 if (fp->disable_tpa) 1020 return; 1021 1022 for (i = 0; i < last; i++) 1023 bnx2x_free_rx_sge(bp, fp, i); 1024 } 1025 1026 static inline void bnx2x_set_next_page_rx_bd(struct bnx2x_fastpath *fp) 1027 { 1028 int i; 1029 1030 for (i = 1; i <= NUM_RX_RINGS; i++) { 1031 struct eth_rx_bd *rx_bd; 1032 1033 rx_bd = &fp->rx_desc_ring[RX_DESC_CNT * i - 2]; 1034 rx_bd->addr_hi = 1035 cpu_to_le32(U64_HI(fp->rx_desc_mapping + 1036 BCM_PAGE_SIZE*(i % NUM_RX_RINGS))); 1037 rx_bd->addr_lo = 1038 cpu_to_le32(U64_LO(fp->rx_desc_mapping + 1039 BCM_PAGE_SIZE*(i % NUM_RX_RINGS))); 1040 } 1041 } 1042 1043 /* Statistics ID are global per chip/path, while Client IDs for E1x are per 1044 * port. 1045 */ 1046 static inline u8 bnx2x_stats_id(struct bnx2x_fastpath *fp) 1047 { 1048 struct bnx2x *bp = fp->bp; 1049 if (!CHIP_IS_E1x(bp)) { 1050 /* there are special statistics counters for FCoE 136..140 */ 1051 if (IS_FCOE_FP(fp)) 1052 return bp->cnic_base_cl_id + (bp->pf_num >> 1); 1053 return fp->cl_id; 1054 } 1055 return fp->cl_id + BP_PORT(bp) * FP_SB_MAX_E1x; 1056 } 1057 1058 static inline void bnx2x_init_vlan_mac_fp_objs(struct bnx2x_fastpath *fp, 1059 bnx2x_obj_type obj_type) 1060 { 1061 struct bnx2x *bp = fp->bp; 1062 1063 /* Configure classification DBs */ 1064 bnx2x_init_mac_obj(bp, &bnx2x_sp_obj(bp, fp).mac_obj, fp->cl_id, 1065 fp->cid, BP_FUNC(bp), bnx2x_sp(bp, mac_rdata), 1066 bnx2x_sp_mapping(bp, mac_rdata), 1067 BNX2X_FILTER_MAC_PENDING, 1068 &bp->sp_state, obj_type, 1069 &bp->macs_pool); 1070 } 1071 1072 /** 1073 * bnx2x_get_path_func_num - get number of active functions 1074 * 1075 * @bp: driver handle 1076 * 1077 * Calculates the number of active (not hidden) functions on the 1078 * current path. 1079 */ 1080 static inline u8 bnx2x_get_path_func_num(struct bnx2x *bp) 1081 { 1082 u8 func_num = 0, i; 1083 1084 /* 57710 has only one function per-port */ 1085 if (CHIP_IS_E1(bp)) 1086 return 1; 1087 1088 /* Calculate a number of functions enabled on the current 1089 * PATH/PORT. 1090 */ 1091 if (CHIP_REV_IS_SLOW(bp)) { 1092 if (IS_MF(bp)) 1093 func_num = 4; 1094 else 1095 func_num = 2; 1096 } else { 1097 for (i = 0; i < E1H_FUNC_MAX / 2; i++) { 1098 u32 func_config = 1099 MF_CFG_RD(bp, 1100 func_mf_config[BP_PORT(bp) + 2 * i]. 1101 config); 1102 func_num += 1103 ((func_config & FUNC_MF_CFG_FUNC_HIDE) ? 0 : 1); 1104 } 1105 } 1106 1107 WARN_ON(!func_num); 1108 1109 return func_num; 1110 } 1111 1112 static inline void bnx2x_init_bp_objs(struct bnx2x *bp) 1113 { 1114 /* RX_MODE controlling object */ 1115 bnx2x_init_rx_mode_obj(bp, &bp->rx_mode_obj); 1116 1117 /* multicast configuration controlling object */ 1118 bnx2x_init_mcast_obj(bp, &bp->mcast_obj, bp->fp->cl_id, bp->fp->cid, 1119 BP_FUNC(bp), BP_FUNC(bp), 1120 bnx2x_sp(bp, mcast_rdata), 1121 bnx2x_sp_mapping(bp, mcast_rdata), 1122 BNX2X_FILTER_MCAST_PENDING, &bp->sp_state, 1123 BNX2X_OBJ_TYPE_RX); 1124 1125 /* Setup CAM credit pools */ 1126 bnx2x_init_mac_credit_pool(bp, &bp->macs_pool, BP_FUNC(bp), 1127 bnx2x_get_path_func_num(bp)); 1128 1129 bnx2x_init_vlan_credit_pool(bp, &bp->vlans_pool, BP_ABS_FUNC(bp)>>1, 1130 bnx2x_get_path_func_num(bp)); 1131 1132 /* RSS configuration object */ 1133 bnx2x_init_rss_config_obj(bp, &bp->rss_conf_obj, bp->fp->cl_id, 1134 bp->fp->cid, BP_FUNC(bp), BP_FUNC(bp), 1135 bnx2x_sp(bp, rss_rdata), 1136 bnx2x_sp_mapping(bp, rss_rdata), 1137 BNX2X_FILTER_RSS_CONF_PENDING, &bp->sp_state, 1138 BNX2X_OBJ_TYPE_RX); 1139 } 1140 1141 static inline u8 bnx2x_fp_qzone_id(struct bnx2x_fastpath *fp) 1142 { 1143 if (CHIP_IS_E1x(fp->bp)) 1144 return fp->cl_id + BP_PORT(fp->bp) * ETH_MAX_RX_CLIENTS_E1H; 1145 else 1146 return fp->cl_id; 1147 } 1148 1149 u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp); 1150 1151 static inline void bnx2x_init_txdata(struct bnx2x *bp, 1152 struct bnx2x_fp_txdata *txdata, u32 cid, 1153 int txq_index, __le16 *tx_cons_sb, 1154 struct bnx2x_fastpath *fp) 1155 { 1156 txdata->cid = cid; 1157 txdata->txq_index = txq_index; 1158 txdata->tx_cons_sb = tx_cons_sb; 1159 txdata->parent_fp = fp; 1160 txdata->tx_ring_size = IS_FCOE_FP(fp) ? MAX_TX_AVAIL : bp->tx_ring_size; 1161 1162 DP(NETIF_MSG_IFUP, "created tx data cid %d, txq %d\n", 1163 txdata->cid, txdata->txq_index); 1164 } 1165 1166 static inline u8 bnx2x_cnic_eth_cl_id(struct bnx2x *bp, u8 cl_idx) 1167 { 1168 return bp->cnic_base_cl_id + cl_idx + 1169 (bp->pf_num >> 1) * BNX2X_MAX_CNIC_ETH_CL_ID_IDX; 1170 } 1171 1172 static inline u8 bnx2x_cnic_fw_sb_id(struct bnx2x *bp) 1173 { 1174 1175 /* the 'first' id is allocated for the cnic */ 1176 return bp->base_fw_ndsb; 1177 } 1178 1179 static inline u8 bnx2x_cnic_igu_sb_id(struct bnx2x *bp) 1180 { 1181 return bp->igu_base_sb; 1182 } 1183 1184 1185 static inline void bnx2x_init_fcoe_fp(struct bnx2x *bp) 1186 { 1187 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp); 1188 unsigned long q_type = 0; 1189 1190 bnx2x_fcoe(bp, rx_queue) = BNX2X_NUM_ETH_QUEUES(bp); 1191 bnx2x_fcoe(bp, cl_id) = bnx2x_cnic_eth_cl_id(bp, 1192 BNX2X_FCOE_ETH_CL_ID_IDX); 1193 bnx2x_fcoe(bp, cid) = BNX2X_FCOE_ETH_CID(bp); 1194 bnx2x_fcoe(bp, fw_sb_id) = DEF_SB_ID; 1195 bnx2x_fcoe(bp, igu_sb_id) = bp->igu_dsb_id; 1196 bnx2x_fcoe(bp, rx_cons_sb) = BNX2X_FCOE_L2_RX_INDEX; 1197 bnx2x_init_txdata(bp, bnx2x_fcoe(bp, txdata_ptr[0]), 1198 fp->cid, FCOE_TXQ_IDX(bp), BNX2X_FCOE_L2_TX_INDEX, 1199 fp); 1200 1201 DP(NETIF_MSG_IFUP, "created fcoe tx data (fp index %d)\n", fp->index); 1202 1203 /* qZone id equals to FW (per path) client id */ 1204 bnx2x_fcoe(bp, cl_qzone_id) = bnx2x_fp_qzone_id(fp); 1205 /* init shortcut */ 1206 bnx2x_fcoe(bp, ustorm_rx_prods_offset) = 1207 bnx2x_rx_ustorm_prods_offset(fp); 1208 1209 /* Configure Queue State object */ 1210 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type); 1211 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type); 1212 1213 /* No multi-CoS for FCoE L2 client */ 1214 BUG_ON(fp->max_cos != 1); 1215 1216 bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, 1217 &fp->cid, 1, BP_FUNC(bp), bnx2x_sp(bp, q_rdata), 1218 bnx2x_sp_mapping(bp, q_rdata), q_type); 1219 1220 DP(NETIF_MSG_IFUP, 1221 "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n", 1222 fp->index, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id, 1223 fp->igu_sb_id); 1224 } 1225 1226 static inline int bnx2x_clean_tx_queue(struct bnx2x *bp, 1227 struct bnx2x_fp_txdata *txdata) 1228 { 1229 int cnt = 1000; 1230 1231 while (bnx2x_has_tx_work_unload(txdata)) { 1232 if (!cnt) { 1233 BNX2X_ERR("timeout waiting for queue[%d]: txdata->tx_pkt_prod(%d) != txdata->tx_pkt_cons(%d)\n", 1234 txdata->txq_index, txdata->tx_pkt_prod, 1235 txdata->tx_pkt_cons); 1236 #ifdef BNX2X_STOP_ON_ERROR 1237 bnx2x_panic(); 1238 return -EBUSY; 1239 #else 1240 break; 1241 #endif 1242 } 1243 cnt--; 1244 usleep_range(1000, 2000); 1245 } 1246 1247 return 0; 1248 } 1249 1250 int bnx2x_get_link_cfg_idx(struct bnx2x *bp); 1251 1252 static inline void __storm_memset_struct(struct bnx2x *bp, 1253 u32 addr, size_t size, u32 *data) 1254 { 1255 int i; 1256 for (i = 0; i < size/4; i++) 1257 REG_WR(bp, addr + (i * 4), data[i]); 1258 } 1259 1260 /** 1261 * bnx2x_wait_sp_comp - wait for the outstanding SP commands. 1262 * 1263 * @bp: driver handle 1264 * @mask: bits that need to be cleared 1265 */ 1266 static inline bool bnx2x_wait_sp_comp(struct bnx2x *bp, unsigned long mask) 1267 { 1268 int tout = 5000; /* Wait for 5 secs tops */ 1269 1270 while (tout--) { 1271 smp_mb(); 1272 netif_addr_lock_bh(bp->dev); 1273 if (!(bp->sp_state & mask)) { 1274 netif_addr_unlock_bh(bp->dev); 1275 return true; 1276 } 1277 netif_addr_unlock_bh(bp->dev); 1278 1279 usleep_range(1000, 2000); 1280 } 1281 1282 smp_mb(); 1283 1284 netif_addr_lock_bh(bp->dev); 1285 if (bp->sp_state & mask) { 1286 BNX2X_ERR("Filtering completion timed out. sp_state 0x%lx, mask 0x%lx\n", 1287 bp->sp_state, mask); 1288 netif_addr_unlock_bh(bp->dev); 1289 return false; 1290 } 1291 netif_addr_unlock_bh(bp->dev); 1292 1293 return true; 1294 } 1295 1296 /** 1297 * bnx2x_set_ctx_validation - set CDU context validation values 1298 * 1299 * @bp: driver handle 1300 * @cxt: context of the connection on the host memory 1301 * @cid: SW CID of the connection to be configured 1302 */ 1303 void bnx2x_set_ctx_validation(struct bnx2x *bp, struct eth_context *cxt, 1304 u32 cid); 1305 1306 void bnx2x_update_coalesce_sb_index(struct bnx2x *bp, u8 fw_sb_id, 1307 u8 sb_index, u8 disable, u16 usec); 1308 void bnx2x_acquire_phy_lock(struct bnx2x *bp); 1309 void bnx2x_release_phy_lock(struct bnx2x *bp); 1310 1311 /** 1312 * bnx2x_extract_max_cfg - extract MAX BW part from MF configuration. 1313 * 1314 * @bp: driver handle 1315 * @mf_cfg: MF configuration 1316 * 1317 */ 1318 static inline u16 bnx2x_extract_max_cfg(struct bnx2x *bp, u32 mf_cfg) 1319 { 1320 u16 max_cfg = (mf_cfg & FUNC_MF_CFG_MAX_BW_MASK) >> 1321 FUNC_MF_CFG_MAX_BW_SHIFT; 1322 if (!max_cfg) { 1323 DP(NETIF_MSG_IFUP | BNX2X_MSG_ETHTOOL, 1324 "Max BW configured to 0 - using 100 instead\n"); 1325 max_cfg = 100; 1326 } 1327 return max_cfg; 1328 } 1329 1330 /* checks if HW supports GRO for given MTU */ 1331 static inline bool bnx2x_mtu_allows_gro(int mtu) 1332 { 1333 /* gro frags per page */ 1334 int fpp = SGE_PAGE_SIZE / (mtu - ETH_MAX_TPA_HEADER_SIZE); 1335 1336 /* 1337 * 1. number of frags should not grow above MAX_SKB_FRAGS 1338 * 2. frag must fit the page 1339 */ 1340 return mtu <= SGE_PAGE_SIZE && (U_ETH_SGL_SIZE * fpp) <= MAX_SKB_FRAGS; 1341 } 1342 1343 /** 1344 * bnx2x_get_iscsi_info - update iSCSI params according to licensing info. 1345 * 1346 * @bp: driver handle 1347 * 1348 */ 1349 void bnx2x_get_iscsi_info(struct bnx2x *bp); 1350 1351 /** 1352 * bnx2x_link_sync_notify - send notification to other functions. 1353 * 1354 * @bp: driver handle 1355 * 1356 */ 1357 static inline void bnx2x_link_sync_notify(struct bnx2x *bp) 1358 { 1359 int func; 1360 int vn; 1361 1362 /* Set the attention towards other drivers on the same port */ 1363 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { 1364 if (vn == BP_VN(bp)) 1365 continue; 1366 1367 func = func_by_vn(bp, vn); 1368 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_0 + 1369 (LINK_SYNC_ATTENTION_BIT_FUNC_0 + func)*4, 1); 1370 } 1371 } 1372 1373 /** 1374 * bnx2x_update_drv_flags - update flags in shmem 1375 * 1376 * @bp: driver handle 1377 * @flags: flags to update 1378 * @set: set or clear 1379 * 1380 */ 1381 static inline void bnx2x_update_drv_flags(struct bnx2x *bp, u32 flags, u32 set) 1382 { 1383 if (SHMEM2_HAS(bp, drv_flags)) { 1384 u32 drv_flags; 1385 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_DRV_FLAGS); 1386 drv_flags = SHMEM2_RD(bp, drv_flags); 1387 1388 if (set) 1389 SET_FLAGS(drv_flags, flags); 1390 else 1391 RESET_FLAGS(drv_flags, flags); 1392 1393 SHMEM2_WR(bp, drv_flags, drv_flags); 1394 DP(NETIF_MSG_IFUP, "drv_flags 0x%08x\n", drv_flags); 1395 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_DRV_FLAGS); 1396 } 1397 } 1398 1399 static inline bool bnx2x_is_valid_ether_addr(struct bnx2x *bp, u8 *addr) 1400 { 1401 if (is_valid_ether_addr(addr) || 1402 (is_zero_ether_addr(addr) && 1403 (IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp)))) 1404 return true; 1405 1406 return false; 1407 } 1408 1409 /** 1410 * bnx2x_fill_fw_str - Fill buffer with FW version string 1411 * 1412 * @bp: driver handle 1413 * @buf: character buffer to fill with the fw name 1414 * @buf_len: length of the above buffer 1415 * 1416 */ 1417 void bnx2x_fill_fw_str(struct bnx2x *bp, char *buf, size_t buf_len); 1418 1419 int bnx2x_drain_tx_queues(struct bnx2x *bp); 1420 void bnx2x_squeeze_objects(struct bnx2x *bp); 1421 1422 #endif /* BNX2X_CMN_H */ 1423