1 /* bnx2x_cmn.h: Broadcom Everest network driver. 2 * 3 * Copyright (c) 2007-2013 Broadcom Corporation 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation. 8 * 9 * Maintained by: Eilon Greenstein <eilong@broadcom.com> 10 * Written by: Eliezer Tamir 11 * Based on code from Michael Chan's bnx2 driver 12 * UDP CSUM errata workaround by Arik Gendelman 13 * Slowpath and fastpath rework by Vladislav Zolotarov 14 * Statistics and Link management by Yitchak Gertner 15 * 16 */ 17 #ifndef BNX2X_CMN_H 18 #define BNX2X_CMN_H 19 20 #include <linux/types.h> 21 #include <linux/pci.h> 22 #include <linux/netdevice.h> 23 #include <linux/etherdevice.h> 24 25 26 #include "bnx2x.h" 27 #include "bnx2x_sriov.h" 28 29 /* This is used as a replacement for an MCP if it's not present */ 30 extern int load_count[2][3]; /* per-path: 0-common, 1-port0, 2-port1 */ 31 32 extern int num_queues; 33 extern int int_mode; 34 35 /************************ Macros ********************************/ 36 #define BNX2X_PCI_FREE(x, y, size) \ 37 do { \ 38 if (x) { \ 39 dma_free_coherent(&bp->pdev->dev, size, (void *)x, y); \ 40 x = NULL; \ 41 y = 0; \ 42 } \ 43 } while (0) 44 45 #define BNX2X_FREE(x) \ 46 do { \ 47 if (x) { \ 48 kfree((void *)x); \ 49 x = NULL; \ 50 } \ 51 } while (0) 52 53 #define BNX2X_PCI_ALLOC(x, y, size) \ 54 do { \ 55 x = dma_alloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL); \ 56 if (x == NULL) \ 57 goto alloc_mem_err; \ 58 memset((void *)x, 0, size); \ 59 } while (0) 60 61 #define BNX2X_ALLOC(x, size) \ 62 do { \ 63 x = kzalloc(size, GFP_KERNEL); \ 64 if (x == NULL) \ 65 goto alloc_mem_err; \ 66 } while (0) 67 68 /*********************** Interfaces **************************** 69 * Functions that need to be implemented by each driver version 70 */ 71 /* Init */ 72 73 /** 74 * bnx2x_send_unload_req - request unload mode from the MCP. 75 * 76 * @bp: driver handle 77 * @unload_mode: requested function's unload mode 78 * 79 * Return unload mode returned by the MCP: COMMON, PORT or FUNC. 80 */ 81 u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode); 82 83 /** 84 * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP. 85 * 86 * @bp: driver handle 87 * @keep_link: true iff link should be kept up 88 */ 89 void bnx2x_send_unload_done(struct bnx2x *bp, bool keep_link); 90 91 /** 92 * bnx2x_config_rss_pf - configure RSS parameters in a PF. 93 * 94 * @bp: driver handle 95 * @rss_obj: RSS object to use 96 * @ind_table: indirection table to configure 97 * @config_hash: re-configure RSS hash keys configuration 98 */ 99 int bnx2x_config_rss_pf(struct bnx2x *bp, struct bnx2x_rss_config_obj *rss_obj, 100 bool config_hash); 101 102 /** 103 * bnx2x__init_func_obj - init function object 104 * 105 * @bp: driver handle 106 * 107 * Initializes the Function Object with the appropriate 108 * parameters which include a function slow path driver 109 * interface. 110 */ 111 void bnx2x__init_func_obj(struct bnx2x *bp); 112 113 /** 114 * bnx2x_setup_queue - setup eth queue. 115 * 116 * @bp: driver handle 117 * @fp: pointer to the fastpath structure 118 * @leading: boolean 119 * 120 */ 121 int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp, 122 bool leading); 123 124 /** 125 * bnx2x_setup_leading - bring up a leading eth queue. 126 * 127 * @bp: driver handle 128 */ 129 int bnx2x_setup_leading(struct bnx2x *bp); 130 131 /** 132 * bnx2x_fw_command - send the MCP a request 133 * 134 * @bp: driver handle 135 * @command: request 136 * @param: request's parameter 137 * 138 * block until there is a reply 139 */ 140 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param); 141 142 /** 143 * bnx2x_initial_phy_init - initialize link parameters structure variables. 144 * 145 * @bp: driver handle 146 * @load_mode: current mode 147 */ 148 int bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode); 149 150 /** 151 * bnx2x_link_set - configure hw according to link parameters structure. 152 * 153 * @bp: driver handle 154 */ 155 void bnx2x_link_set(struct bnx2x *bp); 156 157 /** 158 * bnx2x_force_link_reset - Forces link reset, and put the PHY 159 * in reset as well. 160 * 161 * @bp: driver handle 162 */ 163 void bnx2x_force_link_reset(struct bnx2x *bp); 164 165 /** 166 * bnx2x_link_test - query link status. 167 * 168 * @bp: driver handle 169 * @is_serdes: bool 170 * 171 * Returns 0 if link is UP. 172 */ 173 u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes); 174 175 /** 176 * bnx2x_drv_pulse - write driver pulse to shmem 177 * 178 * @bp: driver handle 179 * 180 * writes the value in bp->fw_drv_pulse_wr_seq to drv_pulse mbox 181 * in the shmem. 182 */ 183 void bnx2x_drv_pulse(struct bnx2x *bp); 184 185 /** 186 * bnx2x_igu_ack_sb - update IGU with current SB value 187 * 188 * @bp: driver handle 189 * @igu_sb_id: SB id 190 * @segment: SB segment 191 * @index: SB index 192 * @op: SB operation 193 * @update: is HW update required 194 */ 195 void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment, 196 u16 index, u8 op, u8 update); 197 198 /* Disable transactions from chip to host */ 199 void bnx2x_pf_disable(struct bnx2x *bp); 200 int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val); 201 202 /** 203 * bnx2x__link_status_update - handles link status change. 204 * 205 * @bp: driver handle 206 */ 207 void bnx2x__link_status_update(struct bnx2x *bp); 208 209 /** 210 * bnx2x_link_report - report link status to upper layer. 211 * 212 * @bp: driver handle 213 */ 214 void bnx2x_link_report(struct bnx2x *bp); 215 216 /* None-atomic version of bnx2x_link_report() */ 217 void __bnx2x_link_report(struct bnx2x *bp); 218 219 /** 220 * bnx2x_get_mf_speed - calculate MF speed. 221 * 222 * @bp: driver handle 223 * 224 * Takes into account current linespeed and MF configuration. 225 */ 226 u16 bnx2x_get_mf_speed(struct bnx2x *bp); 227 228 /** 229 * bnx2x_msix_sp_int - MSI-X slowpath interrupt handler 230 * 231 * @irq: irq number 232 * @dev_instance: private instance 233 */ 234 irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance); 235 236 /** 237 * bnx2x_interrupt - non MSI-X interrupt handler 238 * 239 * @irq: irq number 240 * @dev_instance: private instance 241 */ 242 irqreturn_t bnx2x_interrupt(int irq, void *dev_instance); 243 244 /** 245 * bnx2x_cnic_notify - send command to cnic driver 246 * 247 * @bp: driver handle 248 * @cmd: command 249 */ 250 int bnx2x_cnic_notify(struct bnx2x *bp, int cmd); 251 252 /** 253 * bnx2x_setup_cnic_irq_info - provides cnic with IRQ information 254 * 255 * @bp: driver handle 256 */ 257 void bnx2x_setup_cnic_irq_info(struct bnx2x *bp); 258 259 /** 260 * bnx2x_setup_cnic_info - provides cnic with updated info 261 * 262 * @bp: driver handle 263 */ 264 void bnx2x_setup_cnic_info(struct bnx2x *bp); 265 266 /** 267 * bnx2x_int_enable - enable HW interrupts. 268 * 269 * @bp: driver handle 270 */ 271 void bnx2x_int_enable(struct bnx2x *bp); 272 273 /** 274 * bnx2x_int_disable_sync - disable interrupts. 275 * 276 * @bp: driver handle 277 * @disable_hw: true, disable HW interrupts. 278 * 279 * This function ensures that there are no 280 * ISRs or SP DPCs (sp_task) are running after it returns. 281 */ 282 void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw); 283 284 /** 285 * bnx2x_nic_init_cnic - init driver internals for cnic. 286 * 287 * @bp: driver handle 288 * @load_code: COMMON, PORT or FUNCTION 289 * 290 * Initializes: 291 * - rings 292 * - status blocks 293 * - etc. 294 */ 295 void bnx2x_nic_init_cnic(struct bnx2x *bp); 296 297 /** 298 * bnx2x_nic_init - init driver internals. 299 * 300 * @bp: driver handle 301 * 302 * Initializes: 303 * - rings 304 * - status blocks 305 * - etc. 306 */ 307 void bnx2x_nic_init(struct bnx2x *bp, u32 load_code); 308 /** 309 * bnx2x_alloc_mem_cnic - allocate driver's memory for cnic. 310 * 311 * @bp: driver handle 312 */ 313 int bnx2x_alloc_mem_cnic(struct bnx2x *bp); 314 /** 315 * bnx2x_alloc_mem - allocate driver's memory. 316 * 317 * @bp: driver handle 318 */ 319 int bnx2x_alloc_mem(struct bnx2x *bp); 320 321 /** 322 * bnx2x_free_mem_cnic - release driver's memory for cnic. 323 * 324 * @bp: driver handle 325 */ 326 void bnx2x_free_mem_cnic(struct bnx2x *bp); 327 /** 328 * bnx2x_free_mem - release driver's memory. 329 * 330 * @bp: driver handle 331 */ 332 void bnx2x_free_mem(struct bnx2x *bp); 333 334 /** 335 * bnx2x_set_num_queues - set number of queues according to mode. 336 * 337 * @bp: driver handle 338 */ 339 void bnx2x_set_num_queues(struct bnx2x *bp); 340 341 /** 342 * bnx2x_chip_cleanup - cleanup chip internals. 343 * 344 * @bp: driver handle 345 * @unload_mode: COMMON, PORT, FUNCTION 346 * @keep_link: true iff link should be kept up. 347 * 348 * - Cleanup MAC configuration. 349 * - Closes clients. 350 * - etc. 351 */ 352 void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode, bool keep_link); 353 354 /** 355 * bnx2x_acquire_hw_lock - acquire HW lock. 356 * 357 * @bp: driver handle 358 * @resource: resource bit which was locked 359 */ 360 int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource); 361 362 /** 363 * bnx2x_release_hw_lock - release HW lock. 364 * 365 * @bp: driver handle 366 * @resource: resource bit which was locked 367 */ 368 int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource); 369 370 /** 371 * bnx2x_release_leader_lock - release recovery leader lock 372 * 373 * @bp: driver handle 374 */ 375 int bnx2x_release_leader_lock(struct bnx2x *bp); 376 377 /** 378 * bnx2x_set_eth_mac - configure eth MAC address in the HW 379 * 380 * @bp: driver handle 381 * @set: set or clear 382 * 383 * Configures according to the value in netdev->dev_addr. 384 */ 385 int bnx2x_set_eth_mac(struct bnx2x *bp, bool set); 386 387 /** 388 * bnx2x_set_rx_mode - set MAC filtering configurations. 389 * 390 * @dev: netdevice 391 * 392 * called with netif_tx_lock from dev_mcast.c 393 * If bp->state is OPEN, should be called with 394 * netif_addr_lock_bh() 395 */ 396 void bnx2x_set_rx_mode(struct net_device *dev); 397 398 /** 399 * bnx2x_set_storm_rx_mode - configure MAC filtering rules in a FW. 400 * 401 * @bp: driver handle 402 * 403 * If bp->state is OPEN, should be called with 404 * netif_addr_lock_bh(). 405 */ 406 int bnx2x_set_storm_rx_mode(struct bnx2x *bp); 407 408 /** 409 * bnx2x_set_q_rx_mode - configures rx_mode for a single queue. 410 * 411 * @bp: driver handle 412 * @cl_id: client id 413 * @rx_mode_flags: rx mode configuration 414 * @rx_accept_flags: rx accept configuration 415 * @tx_accept_flags: tx accept configuration (tx switch) 416 * @ramrod_flags: ramrod configuration 417 */ 418 int bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id, 419 unsigned long rx_mode_flags, 420 unsigned long rx_accept_flags, 421 unsigned long tx_accept_flags, 422 unsigned long ramrod_flags); 423 424 /* Parity errors related */ 425 void bnx2x_set_pf_load(struct bnx2x *bp); 426 bool bnx2x_clear_pf_load(struct bnx2x *bp); 427 bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print); 428 bool bnx2x_reset_is_done(struct bnx2x *bp, int engine); 429 void bnx2x_set_reset_in_progress(struct bnx2x *bp); 430 void bnx2x_set_reset_global(struct bnx2x *bp); 431 void bnx2x_disable_close_the_gate(struct bnx2x *bp); 432 int bnx2x_init_hw_func_cnic(struct bnx2x *bp); 433 434 /** 435 * bnx2x_sp_event - handle ramrods completion. 436 * 437 * @fp: fastpath handle for the event 438 * @rr_cqe: eth_rx_cqe 439 */ 440 void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe); 441 442 /** 443 * bnx2x_ilt_set_info - prepare ILT configurations. 444 * 445 * @bp: driver handle 446 */ 447 void bnx2x_ilt_set_info(struct bnx2x *bp); 448 449 /** 450 * bnx2x_ilt_set_cnic_info - prepare ILT configurations for SRC 451 * and TM. 452 * 453 * @bp: driver handle 454 */ 455 void bnx2x_ilt_set_info_cnic(struct bnx2x *bp); 456 457 /** 458 * bnx2x_dcbx_init - initialize dcbx protocol. 459 * 460 * @bp: driver handle 461 */ 462 void bnx2x_dcbx_init(struct bnx2x *bp, bool update_shmem); 463 464 /** 465 * bnx2x_set_power_state - set power state to the requested value. 466 * 467 * @bp: driver handle 468 * @state: required state D0 or D3hot 469 * 470 * Currently only D0 and D3hot are supported. 471 */ 472 int bnx2x_set_power_state(struct bnx2x *bp, pci_power_t state); 473 474 /** 475 * bnx2x_update_max_mf_config - update MAX part of MF configuration in HW. 476 * 477 * @bp: driver handle 478 * @value: new value 479 */ 480 void bnx2x_update_max_mf_config(struct bnx2x *bp, u32 value); 481 /* Error handling */ 482 void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl); 483 484 /* validate currect fw is loaded */ 485 bool bnx2x_test_firmware_version(struct bnx2x *bp, bool is_err); 486 487 /* dev_close main block */ 488 int bnx2x_nic_unload(struct bnx2x *bp, int unload_mode, bool keep_link); 489 490 /* dev_open main block */ 491 int bnx2x_nic_load(struct bnx2x *bp, int load_mode); 492 493 /* hard_xmit callback */ 494 netdev_tx_t bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev); 495 496 /* setup_tc callback */ 497 int bnx2x_setup_tc(struct net_device *dev, u8 num_tc); 498 499 int bnx2x_set_vf_mac(struct net_device *dev, int queue, u8 *mac); 500 501 /* select_queue callback */ 502 u16 bnx2x_select_queue(struct net_device *dev, struct sk_buff *skb); 503 504 static inline void bnx2x_update_rx_prod(struct bnx2x *bp, 505 struct bnx2x_fastpath *fp, 506 u16 bd_prod, u16 rx_comp_prod, 507 u16 rx_sge_prod) 508 { 509 struct ustorm_eth_rx_producers rx_prods = {0}; 510 u32 i; 511 512 /* Update producers */ 513 rx_prods.bd_prod = bd_prod; 514 rx_prods.cqe_prod = rx_comp_prod; 515 rx_prods.sge_prod = rx_sge_prod; 516 517 /* Make sure that the BD and SGE data is updated before updating the 518 * producers since FW might read the BD/SGE right after the producer 519 * is updated. 520 * This is only applicable for weak-ordered memory model archs such 521 * as IA-64. The following barrier is also mandatory since FW will 522 * assumes BDs must have buffers. 523 */ 524 wmb(); 525 526 for (i = 0; i < sizeof(rx_prods)/4; i++) 527 REG_WR(bp, fp->ustorm_rx_prods_offset + i*4, 528 ((u32 *)&rx_prods)[i]); 529 530 mmiowb(); /* keep prod updates ordered */ 531 532 DP(NETIF_MSG_RX_STATUS, 533 "queue[%d]: wrote bd_prod %u cqe_prod %u sge_prod %u\n", 534 fp->index, bd_prod, rx_comp_prod, rx_sge_prod); 535 } 536 537 /* reload helper */ 538 int bnx2x_reload_if_running(struct net_device *dev); 539 540 int bnx2x_change_mac_addr(struct net_device *dev, void *p); 541 542 /* NAPI poll Rx part */ 543 int bnx2x_rx_int(struct bnx2x_fastpath *fp, int budget); 544 545 /* NAPI poll Tx part */ 546 int bnx2x_tx_int(struct bnx2x *bp, struct bnx2x_fp_txdata *txdata); 547 548 /* suspend/resume callbacks */ 549 int bnx2x_suspend(struct pci_dev *pdev, pm_message_t state); 550 int bnx2x_resume(struct pci_dev *pdev); 551 552 /* Release IRQ vectors */ 553 void bnx2x_free_irq(struct bnx2x *bp); 554 555 void bnx2x_free_fp_mem_cnic(struct bnx2x *bp); 556 void bnx2x_free_fp_mem(struct bnx2x *bp); 557 int bnx2x_alloc_fp_mem_cnic(struct bnx2x *bp); 558 int bnx2x_alloc_fp_mem(struct bnx2x *bp); 559 void bnx2x_init_rx_rings(struct bnx2x *bp); 560 void bnx2x_init_rx_rings_cnic(struct bnx2x *bp); 561 void bnx2x_free_skbs_cnic(struct bnx2x *bp); 562 void bnx2x_free_skbs(struct bnx2x *bp); 563 void bnx2x_netif_stop(struct bnx2x *bp, int disable_hw); 564 void bnx2x_netif_start(struct bnx2x *bp); 565 int bnx2x_load_cnic(struct bnx2x *bp); 566 567 /** 568 * bnx2x_enable_msix - set msix configuration. 569 * 570 * @bp: driver handle 571 * 572 * fills msix_table, requests vectors, updates num_queues 573 * according to number of available vectors. 574 */ 575 int bnx2x_enable_msix(struct bnx2x *bp); 576 577 /** 578 * bnx2x_enable_msi - request msi mode from OS, updated internals accordingly 579 * 580 * @bp: driver handle 581 */ 582 int bnx2x_enable_msi(struct bnx2x *bp); 583 584 /** 585 * bnx2x_poll - NAPI callback 586 * 587 * @napi: napi structure 588 * @budget: 589 * 590 */ 591 int bnx2x_poll(struct napi_struct *napi, int budget); 592 593 /** 594 * bnx2x_alloc_mem_bp - allocate memories outsize main driver structure 595 * 596 * @bp: driver handle 597 */ 598 int bnx2x_alloc_mem_bp(struct bnx2x *bp); 599 600 /** 601 * bnx2x_free_mem_bp - release memories outsize main driver structure 602 * 603 * @bp: driver handle 604 */ 605 void bnx2x_free_mem_bp(struct bnx2x *bp); 606 607 /** 608 * bnx2x_change_mtu - change mtu netdev callback 609 * 610 * @dev: net device 611 * @new_mtu: requested mtu 612 * 613 */ 614 int bnx2x_change_mtu(struct net_device *dev, int new_mtu); 615 616 #ifdef NETDEV_FCOE_WWNN 617 /** 618 * bnx2x_fcoe_get_wwn - return the requested WWN value for this port 619 * 620 * @dev: net_device 621 * @wwn: output buffer 622 * @type: WWN type: NETDEV_FCOE_WWNN (node) or NETDEV_FCOE_WWPN (port) 623 * 624 */ 625 int bnx2x_fcoe_get_wwn(struct net_device *dev, u64 *wwn, int type); 626 #endif 627 628 netdev_features_t bnx2x_fix_features(struct net_device *dev, 629 netdev_features_t features); 630 int bnx2x_set_features(struct net_device *dev, netdev_features_t features); 631 632 /** 633 * bnx2x_tx_timeout - tx timeout netdev callback 634 * 635 * @dev: net device 636 */ 637 void bnx2x_tx_timeout(struct net_device *dev); 638 639 /*********************** Inlines **********************************/ 640 /*********************** Fast path ********************************/ 641 static inline void bnx2x_update_fpsb_idx(struct bnx2x_fastpath *fp) 642 { 643 barrier(); /* status block is written to by the chip */ 644 fp->fp_hc_idx = fp->sb_running_index[SM_RX_ID]; 645 } 646 647 static inline void bnx2x_igu_ack_sb_gen(struct bnx2x *bp, u8 igu_sb_id, 648 u8 segment, u16 index, u8 op, 649 u8 update, u32 igu_addr) 650 { 651 struct igu_regular cmd_data = {0}; 652 653 cmd_data.sb_id_and_flags = 654 ((index << IGU_REGULAR_SB_INDEX_SHIFT) | 655 (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) | 656 (update << IGU_REGULAR_BUPDATE_SHIFT) | 657 (op << IGU_REGULAR_ENABLE_INT_SHIFT)); 658 659 DP(NETIF_MSG_INTR, "write 0x%08x to IGU addr 0x%x\n", 660 cmd_data.sb_id_and_flags, igu_addr); 661 REG_WR(bp, igu_addr, cmd_data.sb_id_and_flags); 662 663 /* Make sure that ACK is written */ 664 mmiowb(); 665 barrier(); 666 } 667 668 static inline void bnx2x_hc_ack_sb(struct bnx2x *bp, u8 sb_id, 669 u8 storm, u16 index, u8 op, u8 update) 670 { 671 u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 + 672 COMMAND_REG_INT_ACK); 673 struct igu_ack_register igu_ack; 674 675 igu_ack.status_block_index = index; 676 igu_ack.sb_id_and_flags = 677 ((sb_id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) | 678 (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) | 679 (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) | 680 (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT)); 681 682 REG_WR(bp, hc_addr, (*(u32 *)&igu_ack)); 683 684 /* Make sure that ACK is written */ 685 mmiowb(); 686 barrier(); 687 } 688 689 static inline void bnx2x_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 storm, 690 u16 index, u8 op, u8 update) 691 { 692 if (bp->common.int_block == INT_BLOCK_HC) 693 bnx2x_hc_ack_sb(bp, igu_sb_id, storm, index, op, update); 694 else { 695 u8 segment; 696 697 if (CHIP_INT_MODE_IS_BC(bp)) 698 segment = storm; 699 else if (igu_sb_id != bp->igu_dsb_id) 700 segment = IGU_SEG_ACCESS_DEF; 701 else if (storm == ATTENTION_ID) 702 segment = IGU_SEG_ACCESS_ATTN; 703 else 704 segment = IGU_SEG_ACCESS_DEF; 705 bnx2x_igu_ack_sb(bp, igu_sb_id, segment, index, op, update); 706 } 707 } 708 709 static inline u16 bnx2x_hc_ack_int(struct bnx2x *bp) 710 { 711 u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 + 712 COMMAND_REG_SIMD_MASK); 713 u32 result = REG_RD(bp, hc_addr); 714 715 barrier(); 716 return result; 717 } 718 719 static inline u16 bnx2x_igu_ack_int(struct bnx2x *bp) 720 { 721 u32 igu_addr = (BAR_IGU_INTMEM + IGU_REG_SISR_MDPC_WMASK_LSB_UPPER*8); 722 u32 result = REG_RD(bp, igu_addr); 723 724 DP(NETIF_MSG_INTR, "read 0x%08x from IGU addr 0x%x\n", 725 result, igu_addr); 726 727 barrier(); 728 return result; 729 } 730 731 static inline u16 bnx2x_ack_int(struct bnx2x *bp) 732 { 733 barrier(); 734 if (bp->common.int_block == INT_BLOCK_HC) 735 return bnx2x_hc_ack_int(bp); 736 else 737 return bnx2x_igu_ack_int(bp); 738 } 739 740 static inline int bnx2x_has_tx_work_unload(struct bnx2x_fp_txdata *txdata) 741 { 742 /* Tell compiler that consumer and producer can change */ 743 barrier(); 744 return txdata->tx_pkt_prod != txdata->tx_pkt_cons; 745 } 746 747 static inline u16 bnx2x_tx_avail(struct bnx2x *bp, 748 struct bnx2x_fp_txdata *txdata) 749 { 750 s16 used; 751 u16 prod; 752 u16 cons; 753 754 prod = txdata->tx_bd_prod; 755 cons = txdata->tx_bd_cons; 756 757 used = SUB_S16(prod, cons); 758 759 #ifdef BNX2X_STOP_ON_ERROR 760 WARN_ON(used < 0); 761 WARN_ON(used > txdata->tx_ring_size); 762 WARN_ON((txdata->tx_ring_size - used) > MAX_TX_AVAIL); 763 #endif 764 765 return (s16)(txdata->tx_ring_size) - used; 766 } 767 768 static inline int bnx2x_tx_queue_has_work(struct bnx2x_fp_txdata *txdata) 769 { 770 u16 hw_cons; 771 772 /* Tell compiler that status block fields can change */ 773 barrier(); 774 hw_cons = le16_to_cpu(*txdata->tx_cons_sb); 775 return hw_cons != txdata->tx_pkt_cons; 776 } 777 778 static inline bool bnx2x_has_tx_work(struct bnx2x_fastpath *fp) 779 { 780 u8 cos; 781 for_each_cos_in_tx_queue(fp, cos) 782 if (bnx2x_tx_queue_has_work(fp->txdata_ptr[cos])) 783 return true; 784 return false; 785 } 786 787 static inline int bnx2x_has_rx_work(struct bnx2x_fastpath *fp) 788 { 789 u16 rx_cons_sb; 790 791 /* Tell compiler that status block fields can change */ 792 barrier(); 793 rx_cons_sb = le16_to_cpu(*fp->rx_cons_sb); 794 if ((rx_cons_sb & MAX_RCQ_DESC_CNT) == MAX_RCQ_DESC_CNT) 795 rx_cons_sb++; 796 return (fp->rx_comp_cons != rx_cons_sb); 797 } 798 799 /** 800 * bnx2x_tx_disable - disables tx from stack point of view 801 * 802 * @bp: driver handle 803 */ 804 static inline void bnx2x_tx_disable(struct bnx2x *bp) 805 { 806 netif_tx_disable(bp->dev); 807 netif_carrier_off(bp->dev); 808 } 809 810 static inline void bnx2x_free_rx_sge(struct bnx2x *bp, 811 struct bnx2x_fastpath *fp, u16 index) 812 { 813 struct sw_rx_page *sw_buf = &fp->rx_page_ring[index]; 814 struct page *page = sw_buf->page; 815 struct eth_rx_sge *sge = &fp->rx_sge_ring[index]; 816 817 /* Skip "next page" elements */ 818 if (!page) 819 return; 820 821 dma_unmap_page(&bp->pdev->dev, dma_unmap_addr(sw_buf, mapping), 822 SGE_PAGES, DMA_FROM_DEVICE); 823 __free_pages(page, PAGES_PER_SGE_SHIFT); 824 825 sw_buf->page = NULL; 826 sge->addr_hi = 0; 827 sge->addr_lo = 0; 828 } 829 830 static inline void bnx2x_add_all_napi_cnic(struct bnx2x *bp) 831 { 832 int i; 833 834 /* Add NAPI objects */ 835 for_each_rx_queue_cnic(bp, i) 836 netif_napi_add(bp->dev, &bnx2x_fp(bp, i, napi), 837 bnx2x_poll, BNX2X_NAPI_WEIGHT); 838 } 839 840 static inline void bnx2x_add_all_napi(struct bnx2x *bp) 841 { 842 int i; 843 844 /* Add NAPI objects */ 845 for_each_eth_queue(bp, i) 846 netif_napi_add(bp->dev, &bnx2x_fp(bp, i, napi), 847 bnx2x_poll, BNX2X_NAPI_WEIGHT); 848 } 849 850 static inline void bnx2x_del_all_napi_cnic(struct bnx2x *bp) 851 { 852 int i; 853 854 for_each_rx_queue_cnic(bp, i) 855 netif_napi_del(&bnx2x_fp(bp, i, napi)); 856 } 857 858 static inline void bnx2x_del_all_napi(struct bnx2x *bp) 859 { 860 int i; 861 862 for_each_eth_queue(bp, i) 863 netif_napi_del(&bnx2x_fp(bp, i, napi)); 864 } 865 866 int bnx2x_set_int_mode(struct bnx2x *bp); 867 868 static inline void bnx2x_disable_msi(struct bnx2x *bp) 869 { 870 if (bp->flags & USING_MSIX_FLAG) { 871 pci_disable_msix(bp->pdev); 872 bp->flags &= ~(USING_MSIX_FLAG | USING_SINGLE_MSIX_FLAG); 873 } else if (bp->flags & USING_MSI_FLAG) { 874 pci_disable_msi(bp->pdev); 875 bp->flags &= ~USING_MSI_FLAG; 876 } 877 } 878 879 static inline int bnx2x_calc_num_queues(struct bnx2x *bp) 880 { 881 return num_queues ? 882 min_t(int, num_queues, BNX2X_MAX_QUEUES(bp)) : 883 min_t(int, netif_get_num_default_rss_queues(), 884 BNX2X_MAX_QUEUES(bp)); 885 } 886 887 static inline void bnx2x_clear_sge_mask_next_elems(struct bnx2x_fastpath *fp) 888 { 889 int i, j; 890 891 for (i = 1; i <= NUM_RX_SGE_PAGES; i++) { 892 int idx = RX_SGE_CNT * i - 1; 893 894 for (j = 0; j < 2; j++) { 895 BIT_VEC64_CLEAR_BIT(fp->sge_mask, idx); 896 idx--; 897 } 898 } 899 } 900 901 static inline void bnx2x_init_sge_ring_bit_mask(struct bnx2x_fastpath *fp) 902 { 903 /* Set the mask to all 1-s: it's faster to compare to 0 than to 0xf-s */ 904 memset(fp->sge_mask, 0xff, sizeof(fp->sge_mask)); 905 906 /* Clear the two last indices in the page to 1: 907 these are the indices that correspond to the "next" element, 908 hence will never be indicated and should be removed from 909 the calculations. */ 910 bnx2x_clear_sge_mask_next_elems(fp); 911 } 912 913 /* note that we are not allocating a new buffer, 914 * we are just moving one from cons to prod 915 * we are not creating a new mapping, 916 * so there is no need to check for dma_mapping_error(). 917 */ 918 static inline void bnx2x_reuse_rx_data(struct bnx2x_fastpath *fp, 919 u16 cons, u16 prod) 920 { 921 struct sw_rx_bd *cons_rx_buf = &fp->rx_buf_ring[cons]; 922 struct sw_rx_bd *prod_rx_buf = &fp->rx_buf_ring[prod]; 923 struct eth_rx_bd *cons_bd = &fp->rx_desc_ring[cons]; 924 struct eth_rx_bd *prod_bd = &fp->rx_desc_ring[prod]; 925 926 dma_unmap_addr_set(prod_rx_buf, mapping, 927 dma_unmap_addr(cons_rx_buf, mapping)); 928 prod_rx_buf->data = cons_rx_buf->data; 929 *prod_bd = *cons_bd; 930 } 931 932 /************************* Init ******************************************/ 933 934 /* returns func by VN for current port */ 935 static inline int func_by_vn(struct bnx2x *bp, int vn) 936 { 937 return 2 * vn + BP_PORT(bp); 938 } 939 940 static inline int bnx2x_config_rss_eth(struct bnx2x *bp, bool config_hash) 941 { 942 return bnx2x_config_rss_pf(bp, &bp->rss_conf_obj, config_hash); 943 } 944 945 /** 946 * bnx2x_func_start - init function 947 * 948 * @bp: driver handle 949 * 950 * Must be called before sending CLIENT_SETUP for the first client. 951 */ 952 static inline int bnx2x_func_start(struct bnx2x *bp) 953 { 954 struct bnx2x_func_state_params func_params = {NULL}; 955 struct bnx2x_func_start_params *start_params = 956 &func_params.params.start; 957 958 /* Prepare parameters for function state transitions */ 959 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); 960 961 func_params.f_obj = &bp->func_obj; 962 func_params.cmd = BNX2X_F_CMD_START; 963 964 /* Function parameters */ 965 start_params->mf_mode = bp->mf_mode; 966 start_params->sd_vlan_tag = bp->mf_ov; 967 968 if (CHIP_IS_E2(bp) || CHIP_IS_E3(bp)) 969 start_params->network_cos_mode = STATIC_COS; 970 else /* CHIP_IS_E1X */ 971 start_params->network_cos_mode = FW_WRR; 972 973 return bnx2x_func_state_change(bp, &func_params); 974 } 975 976 /** 977 * bnx2x_set_fw_mac_addr - fill in a MAC address in FW format 978 * 979 * @fw_hi: pointer to upper part 980 * @fw_mid: pointer to middle part 981 * @fw_lo: pointer to lower part 982 * @mac: pointer to MAC address 983 */ 984 static inline void bnx2x_set_fw_mac_addr(__le16 *fw_hi, __le16 *fw_mid, 985 __le16 *fw_lo, u8 *mac) 986 { 987 ((u8 *)fw_hi)[0] = mac[1]; 988 ((u8 *)fw_hi)[1] = mac[0]; 989 ((u8 *)fw_mid)[0] = mac[3]; 990 ((u8 *)fw_mid)[1] = mac[2]; 991 ((u8 *)fw_lo)[0] = mac[5]; 992 ((u8 *)fw_lo)[1] = mac[4]; 993 } 994 995 static inline void bnx2x_free_rx_sge_range(struct bnx2x *bp, 996 struct bnx2x_fastpath *fp, int last) 997 { 998 int i; 999 1000 if (fp->disable_tpa) 1001 return; 1002 1003 for (i = 0; i < last; i++) 1004 bnx2x_free_rx_sge(bp, fp, i); 1005 } 1006 1007 static inline void bnx2x_set_next_page_rx_bd(struct bnx2x_fastpath *fp) 1008 { 1009 int i; 1010 1011 for (i = 1; i <= NUM_RX_RINGS; i++) { 1012 struct eth_rx_bd *rx_bd; 1013 1014 rx_bd = &fp->rx_desc_ring[RX_DESC_CNT * i - 2]; 1015 rx_bd->addr_hi = 1016 cpu_to_le32(U64_HI(fp->rx_desc_mapping + 1017 BCM_PAGE_SIZE*(i % NUM_RX_RINGS))); 1018 rx_bd->addr_lo = 1019 cpu_to_le32(U64_LO(fp->rx_desc_mapping + 1020 BCM_PAGE_SIZE*(i % NUM_RX_RINGS))); 1021 } 1022 } 1023 1024 /* Statistics ID are global per chip/path, while Client IDs for E1x are per 1025 * port. 1026 */ 1027 static inline u8 bnx2x_stats_id(struct bnx2x_fastpath *fp) 1028 { 1029 struct bnx2x *bp = fp->bp; 1030 if (!CHIP_IS_E1x(bp)) { 1031 /* there are special statistics counters for FCoE 136..140 */ 1032 if (IS_FCOE_FP(fp)) 1033 return bp->cnic_base_cl_id + (bp->pf_num >> 1); 1034 return fp->cl_id; 1035 } 1036 return fp->cl_id + BP_PORT(bp) * FP_SB_MAX_E1x; 1037 } 1038 1039 static inline void bnx2x_init_vlan_mac_fp_objs(struct bnx2x_fastpath *fp, 1040 bnx2x_obj_type obj_type) 1041 { 1042 struct bnx2x *bp = fp->bp; 1043 1044 /* Configure classification DBs */ 1045 bnx2x_init_mac_obj(bp, &bnx2x_sp_obj(bp, fp).mac_obj, fp->cl_id, 1046 fp->cid, BP_FUNC(bp), bnx2x_sp(bp, mac_rdata), 1047 bnx2x_sp_mapping(bp, mac_rdata), 1048 BNX2X_FILTER_MAC_PENDING, 1049 &bp->sp_state, obj_type, 1050 &bp->macs_pool); 1051 } 1052 1053 /** 1054 * bnx2x_get_path_func_num - get number of active functions 1055 * 1056 * @bp: driver handle 1057 * 1058 * Calculates the number of active (not hidden) functions on the 1059 * current path. 1060 */ 1061 static inline u8 bnx2x_get_path_func_num(struct bnx2x *bp) 1062 { 1063 u8 func_num = 0, i; 1064 1065 /* 57710 has only one function per-port */ 1066 if (CHIP_IS_E1(bp)) 1067 return 1; 1068 1069 /* Calculate a number of functions enabled on the current 1070 * PATH/PORT. 1071 */ 1072 if (CHIP_REV_IS_SLOW(bp)) { 1073 if (IS_MF(bp)) 1074 func_num = 4; 1075 else 1076 func_num = 2; 1077 } else { 1078 for (i = 0; i < E1H_FUNC_MAX / 2; i++) { 1079 u32 func_config = 1080 MF_CFG_RD(bp, 1081 func_mf_config[BP_PORT(bp) + 2 * i]. 1082 config); 1083 func_num += 1084 ((func_config & FUNC_MF_CFG_FUNC_HIDE) ? 0 : 1); 1085 } 1086 } 1087 1088 WARN_ON(!func_num); 1089 1090 return func_num; 1091 } 1092 1093 static inline void bnx2x_init_bp_objs(struct bnx2x *bp) 1094 { 1095 /* RX_MODE controlling object */ 1096 bnx2x_init_rx_mode_obj(bp, &bp->rx_mode_obj); 1097 1098 /* multicast configuration controlling object */ 1099 bnx2x_init_mcast_obj(bp, &bp->mcast_obj, bp->fp->cl_id, bp->fp->cid, 1100 BP_FUNC(bp), BP_FUNC(bp), 1101 bnx2x_sp(bp, mcast_rdata), 1102 bnx2x_sp_mapping(bp, mcast_rdata), 1103 BNX2X_FILTER_MCAST_PENDING, &bp->sp_state, 1104 BNX2X_OBJ_TYPE_RX); 1105 1106 /* Setup CAM credit pools */ 1107 bnx2x_init_mac_credit_pool(bp, &bp->macs_pool, BP_FUNC(bp), 1108 bnx2x_get_path_func_num(bp)); 1109 1110 bnx2x_init_vlan_credit_pool(bp, &bp->vlans_pool, BP_ABS_FUNC(bp)>>1, 1111 bnx2x_get_path_func_num(bp)); 1112 1113 /* RSS configuration object */ 1114 bnx2x_init_rss_config_obj(bp, &bp->rss_conf_obj, bp->fp->cl_id, 1115 bp->fp->cid, BP_FUNC(bp), BP_FUNC(bp), 1116 bnx2x_sp(bp, rss_rdata), 1117 bnx2x_sp_mapping(bp, rss_rdata), 1118 BNX2X_FILTER_RSS_CONF_PENDING, &bp->sp_state, 1119 BNX2X_OBJ_TYPE_RX); 1120 } 1121 1122 static inline u8 bnx2x_fp_qzone_id(struct bnx2x_fastpath *fp) 1123 { 1124 if (CHIP_IS_E1x(fp->bp)) 1125 return fp->cl_id + BP_PORT(fp->bp) * ETH_MAX_RX_CLIENTS_E1H; 1126 else 1127 return fp->cl_id; 1128 } 1129 1130 u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp); 1131 1132 static inline void bnx2x_init_txdata(struct bnx2x *bp, 1133 struct bnx2x_fp_txdata *txdata, u32 cid, 1134 int txq_index, __le16 *tx_cons_sb, 1135 struct bnx2x_fastpath *fp) 1136 { 1137 txdata->cid = cid; 1138 txdata->txq_index = txq_index; 1139 txdata->tx_cons_sb = tx_cons_sb; 1140 txdata->parent_fp = fp; 1141 txdata->tx_ring_size = IS_FCOE_FP(fp) ? MAX_TX_AVAIL : bp->tx_ring_size; 1142 1143 DP(NETIF_MSG_IFUP, "created tx data cid %d, txq %d\n", 1144 txdata->cid, txdata->txq_index); 1145 } 1146 1147 static inline u8 bnx2x_cnic_eth_cl_id(struct bnx2x *bp, u8 cl_idx) 1148 { 1149 return bp->cnic_base_cl_id + cl_idx + 1150 (bp->pf_num >> 1) * BNX2X_MAX_CNIC_ETH_CL_ID_IDX; 1151 } 1152 1153 static inline u8 bnx2x_cnic_fw_sb_id(struct bnx2x *bp) 1154 { 1155 1156 /* the 'first' id is allocated for the cnic */ 1157 return bp->base_fw_ndsb; 1158 } 1159 1160 static inline u8 bnx2x_cnic_igu_sb_id(struct bnx2x *bp) 1161 { 1162 return bp->igu_base_sb; 1163 } 1164 1165 1166 static inline void bnx2x_init_fcoe_fp(struct bnx2x *bp) 1167 { 1168 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp); 1169 unsigned long q_type = 0; 1170 1171 bnx2x_fcoe(bp, rx_queue) = BNX2X_NUM_ETH_QUEUES(bp); 1172 bnx2x_fcoe(bp, cl_id) = bnx2x_cnic_eth_cl_id(bp, 1173 BNX2X_FCOE_ETH_CL_ID_IDX); 1174 bnx2x_fcoe(bp, cid) = BNX2X_FCOE_ETH_CID(bp); 1175 bnx2x_fcoe(bp, fw_sb_id) = DEF_SB_ID; 1176 bnx2x_fcoe(bp, igu_sb_id) = bp->igu_dsb_id; 1177 bnx2x_fcoe(bp, rx_cons_sb) = BNX2X_FCOE_L2_RX_INDEX; 1178 bnx2x_init_txdata(bp, bnx2x_fcoe(bp, txdata_ptr[0]), 1179 fp->cid, FCOE_TXQ_IDX(bp), BNX2X_FCOE_L2_TX_INDEX, 1180 fp); 1181 1182 DP(NETIF_MSG_IFUP, "created fcoe tx data (fp index %d)\n", fp->index); 1183 1184 /* qZone id equals to FW (per path) client id */ 1185 bnx2x_fcoe(bp, cl_qzone_id) = bnx2x_fp_qzone_id(fp); 1186 /* init shortcut */ 1187 bnx2x_fcoe(bp, ustorm_rx_prods_offset) = 1188 bnx2x_rx_ustorm_prods_offset(fp); 1189 1190 /* Configure Queue State object */ 1191 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type); 1192 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type); 1193 1194 /* No multi-CoS for FCoE L2 client */ 1195 BUG_ON(fp->max_cos != 1); 1196 1197 bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, 1198 &fp->cid, 1, BP_FUNC(bp), bnx2x_sp(bp, q_rdata), 1199 bnx2x_sp_mapping(bp, q_rdata), q_type); 1200 1201 DP(NETIF_MSG_IFUP, 1202 "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n", 1203 fp->index, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id, 1204 fp->igu_sb_id); 1205 } 1206 1207 static inline int bnx2x_clean_tx_queue(struct bnx2x *bp, 1208 struct bnx2x_fp_txdata *txdata) 1209 { 1210 int cnt = 1000; 1211 1212 while (bnx2x_has_tx_work_unload(txdata)) { 1213 if (!cnt) { 1214 BNX2X_ERR("timeout waiting for queue[%d]: txdata->tx_pkt_prod(%d) != txdata->tx_pkt_cons(%d)\n", 1215 txdata->txq_index, txdata->tx_pkt_prod, 1216 txdata->tx_pkt_cons); 1217 #ifdef BNX2X_STOP_ON_ERROR 1218 bnx2x_panic(); 1219 return -EBUSY; 1220 #else 1221 break; 1222 #endif 1223 } 1224 cnt--; 1225 usleep_range(1000, 2000); 1226 } 1227 1228 return 0; 1229 } 1230 1231 int bnx2x_get_link_cfg_idx(struct bnx2x *bp); 1232 1233 static inline void __storm_memset_struct(struct bnx2x *bp, 1234 u32 addr, size_t size, u32 *data) 1235 { 1236 int i; 1237 for (i = 0; i < size/4; i++) 1238 REG_WR(bp, addr + (i * 4), data[i]); 1239 } 1240 1241 /** 1242 * bnx2x_wait_sp_comp - wait for the outstanding SP commands. 1243 * 1244 * @bp: driver handle 1245 * @mask: bits that need to be cleared 1246 */ 1247 static inline bool bnx2x_wait_sp_comp(struct bnx2x *bp, unsigned long mask) 1248 { 1249 int tout = 5000; /* Wait for 5 secs tops */ 1250 1251 while (tout--) { 1252 smp_mb(); 1253 netif_addr_lock_bh(bp->dev); 1254 if (!(bp->sp_state & mask)) { 1255 netif_addr_unlock_bh(bp->dev); 1256 return true; 1257 } 1258 netif_addr_unlock_bh(bp->dev); 1259 1260 usleep_range(1000, 2000); 1261 } 1262 1263 smp_mb(); 1264 1265 netif_addr_lock_bh(bp->dev); 1266 if (bp->sp_state & mask) { 1267 BNX2X_ERR("Filtering completion timed out. sp_state 0x%lx, mask 0x%lx\n", 1268 bp->sp_state, mask); 1269 netif_addr_unlock_bh(bp->dev); 1270 return false; 1271 } 1272 netif_addr_unlock_bh(bp->dev); 1273 1274 return true; 1275 } 1276 1277 /** 1278 * bnx2x_set_ctx_validation - set CDU context validation values 1279 * 1280 * @bp: driver handle 1281 * @cxt: context of the connection on the host memory 1282 * @cid: SW CID of the connection to be configured 1283 */ 1284 void bnx2x_set_ctx_validation(struct bnx2x *bp, struct eth_context *cxt, 1285 u32 cid); 1286 1287 void bnx2x_update_coalesce_sb_index(struct bnx2x *bp, u8 fw_sb_id, 1288 u8 sb_index, u8 disable, u16 usec); 1289 void bnx2x_acquire_phy_lock(struct bnx2x *bp); 1290 void bnx2x_release_phy_lock(struct bnx2x *bp); 1291 1292 /** 1293 * bnx2x_extract_max_cfg - extract MAX BW part from MF configuration. 1294 * 1295 * @bp: driver handle 1296 * @mf_cfg: MF configuration 1297 * 1298 */ 1299 static inline u16 bnx2x_extract_max_cfg(struct bnx2x *bp, u32 mf_cfg) 1300 { 1301 u16 max_cfg = (mf_cfg & FUNC_MF_CFG_MAX_BW_MASK) >> 1302 FUNC_MF_CFG_MAX_BW_SHIFT; 1303 if (!max_cfg) { 1304 DP(NETIF_MSG_IFUP | BNX2X_MSG_ETHTOOL, 1305 "Max BW configured to 0 - using 100 instead\n"); 1306 max_cfg = 100; 1307 } 1308 return max_cfg; 1309 } 1310 1311 /* checks if HW supports GRO for given MTU */ 1312 static inline bool bnx2x_mtu_allows_gro(int mtu) 1313 { 1314 /* gro frags per page */ 1315 int fpp = SGE_PAGE_SIZE / (mtu - ETH_MAX_TPA_HEADER_SIZE); 1316 1317 /* 1318 * 1. number of frags should not grow above MAX_SKB_FRAGS 1319 * 2. frag must fit the page 1320 */ 1321 return mtu <= SGE_PAGE_SIZE && (U_ETH_SGL_SIZE * fpp) <= MAX_SKB_FRAGS; 1322 } 1323 1324 /** 1325 * bnx2x_get_iscsi_info - update iSCSI params according to licensing info. 1326 * 1327 * @bp: driver handle 1328 * 1329 */ 1330 void bnx2x_get_iscsi_info(struct bnx2x *bp); 1331 1332 /** 1333 * bnx2x_link_sync_notify - send notification to other functions. 1334 * 1335 * @bp: driver handle 1336 * 1337 */ 1338 static inline void bnx2x_link_sync_notify(struct bnx2x *bp) 1339 { 1340 int func; 1341 int vn; 1342 1343 /* Set the attention towards other drivers on the same port */ 1344 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { 1345 if (vn == BP_VN(bp)) 1346 continue; 1347 1348 func = func_by_vn(bp, vn); 1349 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_0 + 1350 (LINK_SYNC_ATTENTION_BIT_FUNC_0 + func)*4, 1); 1351 } 1352 } 1353 1354 /** 1355 * bnx2x_update_drv_flags - update flags in shmem 1356 * 1357 * @bp: driver handle 1358 * @flags: flags to update 1359 * @set: set or clear 1360 * 1361 */ 1362 static inline void bnx2x_update_drv_flags(struct bnx2x *bp, u32 flags, u32 set) 1363 { 1364 if (SHMEM2_HAS(bp, drv_flags)) { 1365 u32 drv_flags; 1366 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_DRV_FLAGS); 1367 drv_flags = SHMEM2_RD(bp, drv_flags); 1368 1369 if (set) 1370 SET_FLAGS(drv_flags, flags); 1371 else 1372 RESET_FLAGS(drv_flags, flags); 1373 1374 SHMEM2_WR(bp, drv_flags, drv_flags); 1375 DP(NETIF_MSG_IFUP, "drv_flags 0x%08x\n", drv_flags); 1376 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_DRV_FLAGS); 1377 } 1378 } 1379 1380 static inline bool bnx2x_is_valid_ether_addr(struct bnx2x *bp, u8 *addr) 1381 { 1382 if (is_valid_ether_addr(addr) || 1383 (is_zero_ether_addr(addr) && 1384 (IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp)))) 1385 return true; 1386 1387 return false; 1388 } 1389 1390 /** 1391 * bnx2x_fill_fw_str - Fill buffer with FW version string 1392 * 1393 * @bp: driver handle 1394 * @buf: character buffer to fill with the fw name 1395 * @buf_len: length of the above buffer 1396 * 1397 */ 1398 void bnx2x_fill_fw_str(struct bnx2x *bp, char *buf, size_t buf_len); 1399 #endif /* BNX2X_CMN_H */ 1400