1 /* bnx2x_cmn.h: Broadcom Everest network driver. 2 * 3 * Copyright (c) 2007-2013 Broadcom Corporation 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation. 8 * 9 * Maintained by: Eilon Greenstein <eilong@broadcom.com> 10 * Written by: Eliezer Tamir 11 * Based on code from Michael Chan's bnx2 driver 12 * UDP CSUM errata workaround by Arik Gendelman 13 * Slowpath and fastpath rework by Vladislav Zolotarov 14 * Statistics and Link management by Yitchak Gertner 15 * 16 */ 17 #ifndef BNX2X_CMN_H 18 #define BNX2X_CMN_H 19 20 #include <linux/types.h> 21 #include <linux/pci.h> 22 #include <linux/netdevice.h> 23 #include <linux/etherdevice.h> 24 25 #include "bnx2x.h" 26 #include "bnx2x_sriov.h" 27 28 /* This is used as a replacement for an MCP if it's not present */ 29 extern int load_count[2][3]; /* per-path: 0-common, 1-port0, 2-port1 */ 30 31 extern int num_queues; 32 extern int int_mode; 33 34 /************************ Macros ********************************/ 35 #define BNX2X_PCI_FREE(x, y, size) \ 36 do { \ 37 if (x) { \ 38 dma_free_coherent(&bp->pdev->dev, size, (void *)x, y); \ 39 x = NULL; \ 40 y = 0; \ 41 } \ 42 } while (0) 43 44 #define BNX2X_FREE(x) \ 45 do { \ 46 if (x) { \ 47 kfree((void *)x); \ 48 x = NULL; \ 49 } \ 50 } while (0) 51 52 #define BNX2X_PCI_ALLOC(x, y, size) \ 53 do { \ 54 x = dma_zalloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL); \ 55 if (x == NULL) \ 56 goto alloc_mem_err; \ 57 DP(NETIF_MSG_HW, "BNX2X_PCI_ALLOC: Physical %Lx Virtual %p\n", \ 58 (unsigned long long)(*y), x); \ 59 } while (0) 60 61 #define BNX2X_PCI_FALLOC(x, y, size) \ 62 do { \ 63 x = dma_alloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL); \ 64 if (x == NULL) \ 65 goto alloc_mem_err; \ 66 memset((void *)x, 0xFFFFFFFF, size); \ 67 DP(NETIF_MSG_HW, "BNX2X_PCI_FALLOC: Physical %Lx Virtual %p\n",\ 68 (unsigned long long)(*y), x); \ 69 } while (0) 70 71 #define BNX2X_ALLOC(x, size) \ 72 do { \ 73 x = kzalloc(size, GFP_KERNEL); \ 74 if (x == NULL) \ 75 goto alloc_mem_err; \ 76 } while (0) 77 78 /*********************** Interfaces **************************** 79 * Functions that need to be implemented by each driver version 80 */ 81 /* Init */ 82 83 /** 84 * bnx2x_send_unload_req - request unload mode from the MCP. 85 * 86 * @bp: driver handle 87 * @unload_mode: requested function's unload mode 88 * 89 * Return unload mode returned by the MCP: COMMON, PORT or FUNC. 90 */ 91 u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode); 92 93 /** 94 * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP. 95 * 96 * @bp: driver handle 97 * @keep_link: true iff link should be kept up 98 */ 99 void bnx2x_send_unload_done(struct bnx2x *bp, bool keep_link); 100 101 /** 102 * bnx2x_config_rss_pf - configure RSS parameters in a PF. 103 * 104 * @bp: driver handle 105 * @rss_obj: RSS object to use 106 * @ind_table: indirection table to configure 107 * @config_hash: re-configure RSS hash keys configuration 108 * @enable: enabled or disabled configuration 109 */ 110 int bnx2x_rss(struct bnx2x *bp, struct bnx2x_rss_config_obj *rss_obj, 111 bool config_hash, bool enable); 112 113 /** 114 * bnx2x__init_func_obj - init function object 115 * 116 * @bp: driver handle 117 * 118 * Initializes the Function Object with the appropriate 119 * parameters which include a function slow path driver 120 * interface. 121 */ 122 void bnx2x__init_func_obj(struct bnx2x *bp); 123 124 /** 125 * bnx2x_setup_queue - setup eth queue. 126 * 127 * @bp: driver handle 128 * @fp: pointer to the fastpath structure 129 * @leading: boolean 130 * 131 */ 132 int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp, 133 bool leading); 134 135 /** 136 * bnx2x_setup_leading - bring up a leading eth queue. 137 * 138 * @bp: driver handle 139 */ 140 int bnx2x_setup_leading(struct bnx2x *bp); 141 142 /** 143 * bnx2x_fw_command - send the MCP a request 144 * 145 * @bp: driver handle 146 * @command: request 147 * @param: request's parameter 148 * 149 * block until there is a reply 150 */ 151 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param); 152 153 /** 154 * bnx2x_initial_phy_init - initialize link parameters structure variables. 155 * 156 * @bp: driver handle 157 * @load_mode: current mode 158 */ 159 int bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode); 160 161 /** 162 * bnx2x_link_set - configure hw according to link parameters structure. 163 * 164 * @bp: driver handle 165 */ 166 void bnx2x_link_set(struct bnx2x *bp); 167 168 /** 169 * bnx2x_force_link_reset - Forces link reset, and put the PHY 170 * in reset as well. 171 * 172 * @bp: driver handle 173 */ 174 void bnx2x_force_link_reset(struct bnx2x *bp); 175 176 /** 177 * bnx2x_link_test - query link status. 178 * 179 * @bp: driver handle 180 * @is_serdes: bool 181 * 182 * Returns 0 if link is UP. 183 */ 184 u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes); 185 186 /** 187 * bnx2x_drv_pulse - write driver pulse to shmem 188 * 189 * @bp: driver handle 190 * 191 * writes the value in bp->fw_drv_pulse_wr_seq to drv_pulse mbox 192 * in the shmem. 193 */ 194 void bnx2x_drv_pulse(struct bnx2x *bp); 195 196 /** 197 * bnx2x_igu_ack_sb - update IGU with current SB value 198 * 199 * @bp: driver handle 200 * @igu_sb_id: SB id 201 * @segment: SB segment 202 * @index: SB index 203 * @op: SB operation 204 * @update: is HW update required 205 */ 206 void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment, 207 u16 index, u8 op, u8 update); 208 209 /* Disable transactions from chip to host */ 210 void bnx2x_pf_disable(struct bnx2x *bp); 211 int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val); 212 213 /** 214 * bnx2x__link_status_update - handles link status change. 215 * 216 * @bp: driver handle 217 */ 218 void bnx2x__link_status_update(struct bnx2x *bp); 219 220 /** 221 * bnx2x_link_report - report link status to upper layer. 222 * 223 * @bp: driver handle 224 */ 225 void bnx2x_link_report(struct bnx2x *bp); 226 227 /* None-atomic version of bnx2x_link_report() */ 228 void __bnx2x_link_report(struct bnx2x *bp); 229 230 /** 231 * bnx2x_get_mf_speed - calculate MF speed. 232 * 233 * @bp: driver handle 234 * 235 * Takes into account current linespeed and MF configuration. 236 */ 237 u16 bnx2x_get_mf_speed(struct bnx2x *bp); 238 239 /** 240 * bnx2x_msix_sp_int - MSI-X slowpath interrupt handler 241 * 242 * @irq: irq number 243 * @dev_instance: private instance 244 */ 245 irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance); 246 247 /** 248 * bnx2x_interrupt - non MSI-X interrupt handler 249 * 250 * @irq: irq number 251 * @dev_instance: private instance 252 */ 253 irqreturn_t bnx2x_interrupt(int irq, void *dev_instance); 254 255 /** 256 * bnx2x_cnic_notify - send command to cnic driver 257 * 258 * @bp: driver handle 259 * @cmd: command 260 */ 261 int bnx2x_cnic_notify(struct bnx2x *bp, int cmd); 262 263 /** 264 * bnx2x_setup_cnic_irq_info - provides cnic with IRQ information 265 * 266 * @bp: driver handle 267 */ 268 void bnx2x_setup_cnic_irq_info(struct bnx2x *bp); 269 270 /** 271 * bnx2x_setup_cnic_info - provides cnic with updated info 272 * 273 * @bp: driver handle 274 */ 275 void bnx2x_setup_cnic_info(struct bnx2x *bp); 276 277 /** 278 * bnx2x_int_enable - enable HW interrupts. 279 * 280 * @bp: driver handle 281 */ 282 void bnx2x_int_enable(struct bnx2x *bp); 283 284 /** 285 * bnx2x_int_disable_sync - disable interrupts. 286 * 287 * @bp: driver handle 288 * @disable_hw: true, disable HW interrupts. 289 * 290 * This function ensures that there are no 291 * ISRs or SP DPCs (sp_task) are running after it returns. 292 */ 293 void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw); 294 295 /** 296 * bnx2x_nic_init_cnic - init driver internals for cnic. 297 * 298 * @bp: driver handle 299 * @load_code: COMMON, PORT or FUNCTION 300 * 301 * Initializes: 302 * - rings 303 * - status blocks 304 * - etc. 305 */ 306 void bnx2x_nic_init_cnic(struct bnx2x *bp); 307 308 /** 309 * bnx2x_preirq_nic_init - init driver internals. 310 * 311 * @bp: driver handle 312 * 313 * Initializes: 314 * - fastpath object 315 * - fastpath rings 316 * etc. 317 */ 318 void bnx2x_pre_irq_nic_init(struct bnx2x *bp); 319 320 /** 321 * bnx2x_postirq_nic_init - init driver internals. 322 * 323 * @bp: driver handle 324 * @load_code: COMMON, PORT or FUNCTION 325 * 326 * Initializes: 327 * - status blocks 328 * - slowpath rings 329 * - etc. 330 */ 331 void bnx2x_post_irq_nic_init(struct bnx2x *bp, u32 load_code); 332 /** 333 * bnx2x_alloc_mem_cnic - allocate driver's memory for cnic. 334 * 335 * @bp: driver handle 336 */ 337 int bnx2x_alloc_mem_cnic(struct bnx2x *bp); 338 /** 339 * bnx2x_alloc_mem - allocate driver's memory. 340 * 341 * @bp: driver handle 342 */ 343 int bnx2x_alloc_mem(struct bnx2x *bp); 344 345 /** 346 * bnx2x_free_mem_cnic - release driver's memory for cnic. 347 * 348 * @bp: driver handle 349 */ 350 void bnx2x_free_mem_cnic(struct bnx2x *bp); 351 /** 352 * bnx2x_free_mem - release driver's memory. 353 * 354 * @bp: driver handle 355 */ 356 void bnx2x_free_mem(struct bnx2x *bp); 357 358 /** 359 * bnx2x_set_num_queues - set number of queues according to mode. 360 * 361 * @bp: driver handle 362 */ 363 void bnx2x_set_num_queues(struct bnx2x *bp); 364 365 /** 366 * bnx2x_chip_cleanup - cleanup chip internals. 367 * 368 * @bp: driver handle 369 * @unload_mode: COMMON, PORT, FUNCTION 370 * @keep_link: true iff link should be kept up. 371 * 372 * - Cleanup MAC configuration. 373 * - Closes clients. 374 * - etc. 375 */ 376 void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode, bool keep_link); 377 378 /** 379 * bnx2x_acquire_hw_lock - acquire HW lock. 380 * 381 * @bp: driver handle 382 * @resource: resource bit which was locked 383 */ 384 int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource); 385 386 /** 387 * bnx2x_release_hw_lock - release HW lock. 388 * 389 * @bp: driver handle 390 * @resource: resource bit which was locked 391 */ 392 int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource); 393 394 /** 395 * bnx2x_release_leader_lock - release recovery leader lock 396 * 397 * @bp: driver handle 398 */ 399 int bnx2x_release_leader_lock(struct bnx2x *bp); 400 401 /** 402 * bnx2x_set_eth_mac - configure eth MAC address in the HW 403 * 404 * @bp: driver handle 405 * @set: set or clear 406 * 407 * Configures according to the value in netdev->dev_addr. 408 */ 409 int bnx2x_set_eth_mac(struct bnx2x *bp, bool set); 410 411 /** 412 * bnx2x_set_rx_mode - set MAC filtering configurations. 413 * 414 * @dev: netdevice 415 * 416 * called with netif_tx_lock from dev_mcast.c 417 * If bp->state is OPEN, should be called with 418 * netif_addr_lock_bh() 419 */ 420 void bnx2x_set_rx_mode(struct net_device *dev); 421 void bnx2x_set_rx_mode_inner(struct bnx2x *bp); 422 423 /** 424 * bnx2x_set_storm_rx_mode - configure MAC filtering rules in a FW. 425 * 426 * @bp: driver handle 427 * 428 * If bp->state is OPEN, should be called with 429 * netif_addr_lock_bh(). 430 */ 431 int bnx2x_set_storm_rx_mode(struct bnx2x *bp); 432 433 /** 434 * bnx2x_set_q_rx_mode - configures rx_mode for a single queue. 435 * 436 * @bp: driver handle 437 * @cl_id: client id 438 * @rx_mode_flags: rx mode configuration 439 * @rx_accept_flags: rx accept configuration 440 * @tx_accept_flags: tx accept configuration (tx switch) 441 * @ramrod_flags: ramrod configuration 442 */ 443 int bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id, 444 unsigned long rx_mode_flags, 445 unsigned long rx_accept_flags, 446 unsigned long tx_accept_flags, 447 unsigned long ramrod_flags); 448 449 /* Parity errors related */ 450 void bnx2x_set_pf_load(struct bnx2x *bp); 451 bool bnx2x_clear_pf_load(struct bnx2x *bp); 452 bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print); 453 bool bnx2x_reset_is_done(struct bnx2x *bp, int engine); 454 void bnx2x_set_reset_in_progress(struct bnx2x *bp); 455 void bnx2x_set_reset_global(struct bnx2x *bp); 456 void bnx2x_disable_close_the_gate(struct bnx2x *bp); 457 int bnx2x_init_hw_func_cnic(struct bnx2x *bp); 458 459 /** 460 * bnx2x_sp_event - handle ramrods completion. 461 * 462 * @fp: fastpath handle for the event 463 * @rr_cqe: eth_rx_cqe 464 */ 465 void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe); 466 467 /** 468 * bnx2x_ilt_set_info - prepare ILT configurations. 469 * 470 * @bp: driver handle 471 */ 472 void bnx2x_ilt_set_info(struct bnx2x *bp); 473 474 /** 475 * bnx2x_ilt_set_cnic_info - prepare ILT configurations for SRC 476 * and TM. 477 * 478 * @bp: driver handle 479 */ 480 void bnx2x_ilt_set_info_cnic(struct bnx2x *bp); 481 482 /** 483 * bnx2x_dcbx_init - initialize dcbx protocol. 484 * 485 * @bp: driver handle 486 */ 487 void bnx2x_dcbx_init(struct bnx2x *bp, bool update_shmem); 488 489 /** 490 * bnx2x_set_power_state - set power state to the requested value. 491 * 492 * @bp: driver handle 493 * @state: required state D0 or D3hot 494 * 495 * Currently only D0 and D3hot are supported. 496 */ 497 int bnx2x_set_power_state(struct bnx2x *bp, pci_power_t state); 498 499 /** 500 * bnx2x_update_max_mf_config - update MAX part of MF configuration in HW. 501 * 502 * @bp: driver handle 503 * @value: new value 504 */ 505 void bnx2x_update_max_mf_config(struct bnx2x *bp, u32 value); 506 /* Error handling */ 507 void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl); 508 509 /* dev_close main block */ 510 int bnx2x_nic_unload(struct bnx2x *bp, int unload_mode, bool keep_link); 511 512 /* dev_open main block */ 513 int bnx2x_nic_load(struct bnx2x *bp, int load_mode); 514 515 /* hard_xmit callback */ 516 netdev_tx_t bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev); 517 518 /* setup_tc callback */ 519 int bnx2x_setup_tc(struct net_device *dev, u8 num_tc); 520 521 int bnx2x_get_vf_config(struct net_device *dev, int vf, 522 struct ifla_vf_info *ivi); 523 int bnx2x_set_vf_mac(struct net_device *dev, int queue, u8 *mac); 524 int bnx2x_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan, u8 qos); 525 526 /* select_queue callback */ 527 u16 bnx2x_select_queue(struct net_device *dev, struct sk_buff *skb); 528 529 static inline void bnx2x_update_rx_prod(struct bnx2x *bp, 530 struct bnx2x_fastpath *fp, 531 u16 bd_prod, u16 rx_comp_prod, 532 u16 rx_sge_prod) 533 { 534 struct ustorm_eth_rx_producers rx_prods = {0}; 535 u32 i; 536 537 /* Update producers */ 538 rx_prods.bd_prod = bd_prod; 539 rx_prods.cqe_prod = rx_comp_prod; 540 rx_prods.sge_prod = rx_sge_prod; 541 542 /* Make sure that the BD and SGE data is updated before updating the 543 * producers since FW might read the BD/SGE right after the producer 544 * is updated. 545 * This is only applicable for weak-ordered memory model archs such 546 * as IA-64. The following barrier is also mandatory since FW will 547 * assumes BDs must have buffers. 548 */ 549 wmb(); 550 551 for (i = 0; i < sizeof(rx_prods)/4; i++) 552 REG_WR(bp, fp->ustorm_rx_prods_offset + i*4, 553 ((u32 *)&rx_prods)[i]); 554 555 mmiowb(); /* keep prod updates ordered */ 556 557 DP(NETIF_MSG_RX_STATUS, 558 "queue[%d]: wrote bd_prod %u cqe_prod %u sge_prod %u\n", 559 fp->index, bd_prod, rx_comp_prod, rx_sge_prod); 560 } 561 562 /* reload helper */ 563 int bnx2x_reload_if_running(struct net_device *dev); 564 565 int bnx2x_change_mac_addr(struct net_device *dev, void *p); 566 567 /* NAPI poll Rx part */ 568 int bnx2x_rx_int(struct bnx2x_fastpath *fp, int budget); 569 570 /* NAPI poll Tx part */ 571 int bnx2x_tx_int(struct bnx2x *bp, struct bnx2x_fp_txdata *txdata); 572 573 /* suspend/resume callbacks */ 574 int bnx2x_suspend(struct pci_dev *pdev, pm_message_t state); 575 int bnx2x_resume(struct pci_dev *pdev); 576 577 /* Release IRQ vectors */ 578 void bnx2x_free_irq(struct bnx2x *bp); 579 580 void bnx2x_free_fp_mem_cnic(struct bnx2x *bp); 581 void bnx2x_free_fp_mem(struct bnx2x *bp); 582 int bnx2x_alloc_fp_mem_cnic(struct bnx2x *bp); 583 int bnx2x_alloc_fp_mem(struct bnx2x *bp); 584 void bnx2x_init_rx_rings(struct bnx2x *bp); 585 void bnx2x_init_rx_rings_cnic(struct bnx2x *bp); 586 void bnx2x_free_skbs_cnic(struct bnx2x *bp); 587 void bnx2x_free_skbs(struct bnx2x *bp); 588 void bnx2x_netif_stop(struct bnx2x *bp, int disable_hw); 589 void bnx2x_netif_start(struct bnx2x *bp); 590 int bnx2x_load_cnic(struct bnx2x *bp); 591 592 /** 593 * bnx2x_enable_msix - set msix configuration. 594 * 595 * @bp: driver handle 596 * 597 * fills msix_table, requests vectors, updates num_queues 598 * according to number of available vectors. 599 */ 600 int bnx2x_enable_msix(struct bnx2x *bp); 601 602 /** 603 * bnx2x_enable_msi - request msi mode from OS, updated internals accordingly 604 * 605 * @bp: driver handle 606 */ 607 int bnx2x_enable_msi(struct bnx2x *bp); 608 609 /** 610 * bnx2x_poll - NAPI callback 611 * 612 * @napi: napi structure 613 * @budget: 614 * 615 */ 616 int bnx2x_poll(struct napi_struct *napi, int budget); 617 618 /** 619 * bnx2x_low_latency_recv - LL callback 620 * 621 * @napi: napi structure 622 */ 623 int bnx2x_low_latency_recv(struct napi_struct *napi); 624 625 /** 626 * bnx2x_alloc_mem_bp - allocate memories outsize main driver structure 627 * 628 * @bp: driver handle 629 */ 630 int bnx2x_alloc_mem_bp(struct bnx2x *bp); 631 632 /** 633 * bnx2x_free_mem_bp - release memories outsize main driver structure 634 * 635 * @bp: driver handle 636 */ 637 void bnx2x_free_mem_bp(struct bnx2x *bp); 638 639 /** 640 * bnx2x_change_mtu - change mtu netdev callback 641 * 642 * @dev: net device 643 * @new_mtu: requested mtu 644 * 645 */ 646 int bnx2x_change_mtu(struct net_device *dev, int new_mtu); 647 648 #ifdef NETDEV_FCOE_WWNN 649 /** 650 * bnx2x_fcoe_get_wwn - return the requested WWN value for this port 651 * 652 * @dev: net_device 653 * @wwn: output buffer 654 * @type: WWN type: NETDEV_FCOE_WWNN (node) or NETDEV_FCOE_WWPN (port) 655 * 656 */ 657 int bnx2x_fcoe_get_wwn(struct net_device *dev, u64 *wwn, int type); 658 #endif 659 660 netdev_features_t bnx2x_fix_features(struct net_device *dev, 661 netdev_features_t features); 662 int bnx2x_set_features(struct net_device *dev, netdev_features_t features); 663 664 /** 665 * bnx2x_tx_timeout - tx timeout netdev callback 666 * 667 * @dev: net device 668 */ 669 void bnx2x_tx_timeout(struct net_device *dev); 670 671 /*********************** Inlines **********************************/ 672 /*********************** Fast path ********************************/ 673 static inline void bnx2x_update_fpsb_idx(struct bnx2x_fastpath *fp) 674 { 675 barrier(); /* status block is written to by the chip */ 676 fp->fp_hc_idx = fp->sb_running_index[SM_RX_ID]; 677 } 678 679 static inline void bnx2x_igu_ack_sb_gen(struct bnx2x *bp, u8 igu_sb_id, 680 u8 segment, u16 index, u8 op, 681 u8 update, u32 igu_addr) 682 { 683 struct igu_regular cmd_data = {0}; 684 685 cmd_data.sb_id_and_flags = 686 ((index << IGU_REGULAR_SB_INDEX_SHIFT) | 687 (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) | 688 (update << IGU_REGULAR_BUPDATE_SHIFT) | 689 (op << IGU_REGULAR_ENABLE_INT_SHIFT)); 690 691 DP(NETIF_MSG_INTR, "write 0x%08x to IGU addr 0x%x\n", 692 cmd_data.sb_id_and_flags, igu_addr); 693 REG_WR(bp, igu_addr, cmd_data.sb_id_and_flags); 694 695 /* Make sure that ACK is written */ 696 mmiowb(); 697 barrier(); 698 } 699 700 static inline void bnx2x_hc_ack_sb(struct bnx2x *bp, u8 sb_id, 701 u8 storm, u16 index, u8 op, u8 update) 702 { 703 u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 + 704 COMMAND_REG_INT_ACK); 705 struct igu_ack_register igu_ack; 706 707 igu_ack.status_block_index = index; 708 igu_ack.sb_id_and_flags = 709 ((sb_id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) | 710 (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) | 711 (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) | 712 (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT)); 713 714 REG_WR(bp, hc_addr, (*(u32 *)&igu_ack)); 715 716 /* Make sure that ACK is written */ 717 mmiowb(); 718 barrier(); 719 } 720 721 static inline void bnx2x_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 storm, 722 u16 index, u8 op, u8 update) 723 { 724 if (bp->common.int_block == INT_BLOCK_HC) 725 bnx2x_hc_ack_sb(bp, igu_sb_id, storm, index, op, update); 726 else { 727 u8 segment; 728 729 if (CHIP_INT_MODE_IS_BC(bp)) 730 segment = storm; 731 else if (igu_sb_id != bp->igu_dsb_id) 732 segment = IGU_SEG_ACCESS_DEF; 733 else if (storm == ATTENTION_ID) 734 segment = IGU_SEG_ACCESS_ATTN; 735 else 736 segment = IGU_SEG_ACCESS_DEF; 737 bnx2x_igu_ack_sb(bp, igu_sb_id, segment, index, op, update); 738 } 739 } 740 741 static inline u16 bnx2x_hc_ack_int(struct bnx2x *bp) 742 { 743 u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 + 744 COMMAND_REG_SIMD_MASK); 745 u32 result = REG_RD(bp, hc_addr); 746 747 barrier(); 748 return result; 749 } 750 751 static inline u16 bnx2x_igu_ack_int(struct bnx2x *bp) 752 { 753 u32 igu_addr = (BAR_IGU_INTMEM + IGU_REG_SISR_MDPC_WMASK_LSB_UPPER*8); 754 u32 result = REG_RD(bp, igu_addr); 755 756 DP(NETIF_MSG_INTR, "read 0x%08x from IGU addr 0x%x\n", 757 result, igu_addr); 758 759 barrier(); 760 return result; 761 } 762 763 static inline u16 bnx2x_ack_int(struct bnx2x *bp) 764 { 765 barrier(); 766 if (bp->common.int_block == INT_BLOCK_HC) 767 return bnx2x_hc_ack_int(bp); 768 else 769 return bnx2x_igu_ack_int(bp); 770 } 771 772 static inline int bnx2x_has_tx_work_unload(struct bnx2x_fp_txdata *txdata) 773 { 774 /* Tell compiler that consumer and producer can change */ 775 barrier(); 776 return txdata->tx_pkt_prod != txdata->tx_pkt_cons; 777 } 778 779 static inline u16 bnx2x_tx_avail(struct bnx2x *bp, 780 struct bnx2x_fp_txdata *txdata) 781 { 782 s16 used; 783 u16 prod; 784 u16 cons; 785 786 prod = txdata->tx_bd_prod; 787 cons = txdata->tx_bd_cons; 788 789 used = SUB_S16(prod, cons); 790 791 #ifdef BNX2X_STOP_ON_ERROR 792 WARN_ON(used < 0); 793 WARN_ON(used > txdata->tx_ring_size); 794 WARN_ON((txdata->tx_ring_size - used) > MAX_TX_AVAIL); 795 #endif 796 797 return (s16)(txdata->tx_ring_size) - used; 798 } 799 800 static inline int bnx2x_tx_queue_has_work(struct bnx2x_fp_txdata *txdata) 801 { 802 u16 hw_cons; 803 804 /* Tell compiler that status block fields can change */ 805 barrier(); 806 hw_cons = le16_to_cpu(*txdata->tx_cons_sb); 807 return hw_cons != txdata->tx_pkt_cons; 808 } 809 810 static inline bool bnx2x_has_tx_work(struct bnx2x_fastpath *fp) 811 { 812 u8 cos; 813 for_each_cos_in_tx_queue(fp, cos) 814 if (bnx2x_tx_queue_has_work(fp->txdata_ptr[cos])) 815 return true; 816 return false; 817 } 818 819 #define BNX2X_IS_CQE_COMPLETED(cqe_fp) (cqe_fp->marker == 0x0) 820 #define BNX2X_SEED_CQE(cqe_fp) (cqe_fp->marker = 0xFFFFFFFF) 821 static inline int bnx2x_has_rx_work(struct bnx2x_fastpath *fp) 822 { 823 u16 cons; 824 union eth_rx_cqe *cqe; 825 struct eth_fast_path_rx_cqe *cqe_fp; 826 827 cons = RCQ_BD(fp->rx_comp_cons); 828 cqe = &fp->rx_comp_ring[cons]; 829 cqe_fp = &cqe->fast_path_cqe; 830 return BNX2X_IS_CQE_COMPLETED(cqe_fp); 831 } 832 833 /** 834 * bnx2x_tx_disable - disables tx from stack point of view 835 * 836 * @bp: driver handle 837 */ 838 static inline void bnx2x_tx_disable(struct bnx2x *bp) 839 { 840 netif_tx_disable(bp->dev); 841 netif_carrier_off(bp->dev); 842 } 843 844 static inline void bnx2x_free_rx_sge(struct bnx2x *bp, 845 struct bnx2x_fastpath *fp, u16 index) 846 { 847 struct sw_rx_page *sw_buf = &fp->rx_page_ring[index]; 848 struct page *page = sw_buf->page; 849 struct eth_rx_sge *sge = &fp->rx_sge_ring[index]; 850 851 /* Skip "next page" elements */ 852 if (!page) 853 return; 854 855 dma_unmap_page(&bp->pdev->dev, dma_unmap_addr(sw_buf, mapping), 856 SGE_PAGES, DMA_FROM_DEVICE); 857 __free_pages(page, PAGES_PER_SGE_SHIFT); 858 859 sw_buf->page = NULL; 860 sge->addr_hi = 0; 861 sge->addr_lo = 0; 862 } 863 864 static inline void bnx2x_add_all_napi_cnic(struct bnx2x *bp) 865 { 866 int i; 867 868 /* Add NAPI objects */ 869 for_each_rx_queue_cnic(bp, i) { 870 netif_napi_add(bp->dev, &bnx2x_fp(bp, i, napi), 871 bnx2x_poll, NAPI_POLL_WEIGHT); 872 napi_hash_add(&bnx2x_fp(bp, i, napi)); 873 } 874 } 875 876 static inline void bnx2x_add_all_napi(struct bnx2x *bp) 877 { 878 int i; 879 880 /* Add NAPI objects */ 881 for_each_eth_queue(bp, i) { 882 netif_napi_add(bp->dev, &bnx2x_fp(bp, i, napi), 883 bnx2x_poll, NAPI_POLL_WEIGHT); 884 napi_hash_add(&bnx2x_fp(bp, i, napi)); 885 } 886 } 887 888 static inline void bnx2x_del_all_napi_cnic(struct bnx2x *bp) 889 { 890 int i; 891 892 for_each_rx_queue_cnic(bp, i) { 893 napi_hash_del(&bnx2x_fp(bp, i, napi)); 894 netif_napi_del(&bnx2x_fp(bp, i, napi)); 895 } 896 } 897 898 static inline void bnx2x_del_all_napi(struct bnx2x *bp) 899 { 900 int i; 901 902 for_each_eth_queue(bp, i) { 903 napi_hash_del(&bnx2x_fp(bp, i, napi)); 904 netif_napi_del(&bnx2x_fp(bp, i, napi)); 905 } 906 } 907 908 int bnx2x_set_int_mode(struct bnx2x *bp); 909 910 static inline void bnx2x_disable_msi(struct bnx2x *bp) 911 { 912 if (bp->flags & USING_MSIX_FLAG) { 913 pci_disable_msix(bp->pdev); 914 bp->flags &= ~(USING_MSIX_FLAG | USING_SINGLE_MSIX_FLAG); 915 } else if (bp->flags & USING_MSI_FLAG) { 916 pci_disable_msi(bp->pdev); 917 bp->flags &= ~USING_MSI_FLAG; 918 } 919 } 920 921 static inline int bnx2x_calc_num_queues(struct bnx2x *bp) 922 { 923 return num_queues ? 924 min_t(int, num_queues, BNX2X_MAX_QUEUES(bp)) : 925 min_t(int, netif_get_num_default_rss_queues(), 926 BNX2X_MAX_QUEUES(bp)); 927 } 928 929 static inline void bnx2x_clear_sge_mask_next_elems(struct bnx2x_fastpath *fp) 930 { 931 int i, j; 932 933 for (i = 1; i <= NUM_RX_SGE_PAGES; i++) { 934 int idx = RX_SGE_CNT * i - 1; 935 936 for (j = 0; j < 2; j++) { 937 BIT_VEC64_CLEAR_BIT(fp->sge_mask, idx); 938 idx--; 939 } 940 } 941 } 942 943 static inline void bnx2x_init_sge_ring_bit_mask(struct bnx2x_fastpath *fp) 944 { 945 /* Set the mask to all 1-s: it's faster to compare to 0 than to 0xf-s */ 946 memset(fp->sge_mask, 0xff, sizeof(fp->sge_mask)); 947 948 /* Clear the two last indices in the page to 1: 949 these are the indices that correspond to the "next" element, 950 hence will never be indicated and should be removed from 951 the calculations. */ 952 bnx2x_clear_sge_mask_next_elems(fp); 953 } 954 955 /* note that we are not allocating a new buffer, 956 * we are just moving one from cons to prod 957 * we are not creating a new mapping, 958 * so there is no need to check for dma_mapping_error(). 959 */ 960 static inline void bnx2x_reuse_rx_data(struct bnx2x_fastpath *fp, 961 u16 cons, u16 prod) 962 { 963 struct sw_rx_bd *cons_rx_buf = &fp->rx_buf_ring[cons]; 964 struct sw_rx_bd *prod_rx_buf = &fp->rx_buf_ring[prod]; 965 struct eth_rx_bd *cons_bd = &fp->rx_desc_ring[cons]; 966 struct eth_rx_bd *prod_bd = &fp->rx_desc_ring[prod]; 967 968 dma_unmap_addr_set(prod_rx_buf, mapping, 969 dma_unmap_addr(cons_rx_buf, mapping)); 970 prod_rx_buf->data = cons_rx_buf->data; 971 *prod_bd = *cons_bd; 972 } 973 974 /************************* Init ******************************************/ 975 976 /* returns func by VN for current port */ 977 static inline int func_by_vn(struct bnx2x *bp, int vn) 978 { 979 return 2 * vn + BP_PORT(bp); 980 } 981 982 static inline int bnx2x_config_rss_eth(struct bnx2x *bp, bool config_hash) 983 { 984 return bnx2x_rss(bp, &bp->rss_conf_obj, config_hash, true); 985 } 986 987 /** 988 * bnx2x_func_start - init function 989 * 990 * @bp: driver handle 991 * 992 * Must be called before sending CLIENT_SETUP for the first client. 993 */ 994 static inline int bnx2x_func_start(struct bnx2x *bp) 995 { 996 struct bnx2x_func_state_params func_params = {NULL}; 997 struct bnx2x_func_start_params *start_params = 998 &func_params.params.start; 999 1000 /* Prepare parameters for function state transitions */ 1001 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); 1002 1003 func_params.f_obj = &bp->func_obj; 1004 func_params.cmd = BNX2X_F_CMD_START; 1005 1006 /* Function parameters */ 1007 start_params->mf_mode = bp->mf_mode; 1008 start_params->sd_vlan_tag = bp->mf_ov; 1009 1010 if (CHIP_IS_E2(bp) || CHIP_IS_E3(bp)) 1011 start_params->network_cos_mode = STATIC_COS; 1012 else /* CHIP_IS_E1X */ 1013 start_params->network_cos_mode = FW_WRR; 1014 1015 start_params->gre_tunnel_mode = IPGRE_TUNNEL; 1016 start_params->gre_tunnel_rss = GRE_INNER_HEADERS_RSS; 1017 1018 return bnx2x_func_state_change(bp, &func_params); 1019 } 1020 1021 /** 1022 * bnx2x_set_fw_mac_addr - fill in a MAC address in FW format 1023 * 1024 * @fw_hi: pointer to upper part 1025 * @fw_mid: pointer to middle part 1026 * @fw_lo: pointer to lower part 1027 * @mac: pointer to MAC address 1028 */ 1029 static inline void bnx2x_set_fw_mac_addr(__le16 *fw_hi, __le16 *fw_mid, 1030 __le16 *fw_lo, u8 *mac) 1031 { 1032 ((u8 *)fw_hi)[0] = mac[1]; 1033 ((u8 *)fw_hi)[1] = mac[0]; 1034 ((u8 *)fw_mid)[0] = mac[3]; 1035 ((u8 *)fw_mid)[1] = mac[2]; 1036 ((u8 *)fw_lo)[0] = mac[5]; 1037 ((u8 *)fw_lo)[1] = mac[4]; 1038 } 1039 1040 static inline void bnx2x_free_rx_sge_range(struct bnx2x *bp, 1041 struct bnx2x_fastpath *fp, int last) 1042 { 1043 int i; 1044 1045 if (fp->disable_tpa) 1046 return; 1047 1048 for (i = 0; i < last; i++) 1049 bnx2x_free_rx_sge(bp, fp, i); 1050 } 1051 1052 static inline void bnx2x_set_next_page_rx_bd(struct bnx2x_fastpath *fp) 1053 { 1054 int i; 1055 1056 for (i = 1; i <= NUM_RX_RINGS; i++) { 1057 struct eth_rx_bd *rx_bd; 1058 1059 rx_bd = &fp->rx_desc_ring[RX_DESC_CNT * i - 2]; 1060 rx_bd->addr_hi = 1061 cpu_to_le32(U64_HI(fp->rx_desc_mapping + 1062 BCM_PAGE_SIZE*(i % NUM_RX_RINGS))); 1063 rx_bd->addr_lo = 1064 cpu_to_le32(U64_LO(fp->rx_desc_mapping + 1065 BCM_PAGE_SIZE*(i % NUM_RX_RINGS))); 1066 } 1067 } 1068 1069 /* Statistics ID are global per chip/path, while Client IDs for E1x are per 1070 * port. 1071 */ 1072 static inline u8 bnx2x_stats_id(struct bnx2x_fastpath *fp) 1073 { 1074 struct bnx2x *bp = fp->bp; 1075 if (!CHIP_IS_E1x(bp)) { 1076 /* there are special statistics counters for FCoE 136..140 */ 1077 if (IS_FCOE_FP(fp)) 1078 return bp->cnic_base_cl_id + (bp->pf_num >> 1); 1079 return fp->cl_id; 1080 } 1081 return fp->cl_id + BP_PORT(bp) * FP_SB_MAX_E1x; 1082 } 1083 1084 static inline void bnx2x_init_vlan_mac_fp_objs(struct bnx2x_fastpath *fp, 1085 bnx2x_obj_type obj_type) 1086 { 1087 struct bnx2x *bp = fp->bp; 1088 1089 /* Configure classification DBs */ 1090 bnx2x_init_mac_obj(bp, &bnx2x_sp_obj(bp, fp).mac_obj, fp->cl_id, 1091 fp->cid, BP_FUNC(bp), bnx2x_sp(bp, mac_rdata), 1092 bnx2x_sp_mapping(bp, mac_rdata), 1093 BNX2X_FILTER_MAC_PENDING, 1094 &bp->sp_state, obj_type, 1095 &bp->macs_pool); 1096 } 1097 1098 /** 1099 * bnx2x_get_path_func_num - get number of active functions 1100 * 1101 * @bp: driver handle 1102 * 1103 * Calculates the number of active (not hidden) functions on the 1104 * current path. 1105 */ 1106 static inline u8 bnx2x_get_path_func_num(struct bnx2x *bp) 1107 { 1108 u8 func_num = 0, i; 1109 1110 /* 57710 has only one function per-port */ 1111 if (CHIP_IS_E1(bp)) 1112 return 1; 1113 1114 /* Calculate a number of functions enabled on the current 1115 * PATH/PORT. 1116 */ 1117 if (CHIP_REV_IS_SLOW(bp)) { 1118 if (IS_MF(bp)) 1119 func_num = 4; 1120 else 1121 func_num = 2; 1122 } else { 1123 for (i = 0; i < E1H_FUNC_MAX / 2; i++) { 1124 u32 func_config = 1125 MF_CFG_RD(bp, 1126 func_mf_config[BP_PORT(bp) + 2 * i]. 1127 config); 1128 func_num += 1129 ((func_config & FUNC_MF_CFG_FUNC_HIDE) ? 0 : 1); 1130 } 1131 } 1132 1133 WARN_ON(!func_num); 1134 1135 return func_num; 1136 } 1137 1138 static inline void bnx2x_init_bp_objs(struct bnx2x *bp) 1139 { 1140 /* RX_MODE controlling object */ 1141 bnx2x_init_rx_mode_obj(bp, &bp->rx_mode_obj); 1142 1143 /* multicast configuration controlling object */ 1144 bnx2x_init_mcast_obj(bp, &bp->mcast_obj, bp->fp->cl_id, bp->fp->cid, 1145 BP_FUNC(bp), BP_FUNC(bp), 1146 bnx2x_sp(bp, mcast_rdata), 1147 bnx2x_sp_mapping(bp, mcast_rdata), 1148 BNX2X_FILTER_MCAST_PENDING, &bp->sp_state, 1149 BNX2X_OBJ_TYPE_RX); 1150 1151 /* Setup CAM credit pools */ 1152 bnx2x_init_mac_credit_pool(bp, &bp->macs_pool, BP_FUNC(bp), 1153 bnx2x_get_path_func_num(bp)); 1154 1155 bnx2x_init_vlan_credit_pool(bp, &bp->vlans_pool, BP_ABS_FUNC(bp)>>1, 1156 bnx2x_get_path_func_num(bp)); 1157 1158 /* RSS configuration object */ 1159 bnx2x_init_rss_config_obj(bp, &bp->rss_conf_obj, bp->fp->cl_id, 1160 bp->fp->cid, BP_FUNC(bp), BP_FUNC(bp), 1161 bnx2x_sp(bp, rss_rdata), 1162 bnx2x_sp_mapping(bp, rss_rdata), 1163 BNX2X_FILTER_RSS_CONF_PENDING, &bp->sp_state, 1164 BNX2X_OBJ_TYPE_RX); 1165 } 1166 1167 static inline u8 bnx2x_fp_qzone_id(struct bnx2x_fastpath *fp) 1168 { 1169 if (CHIP_IS_E1x(fp->bp)) 1170 return fp->cl_id + BP_PORT(fp->bp) * ETH_MAX_RX_CLIENTS_E1H; 1171 else 1172 return fp->cl_id; 1173 } 1174 1175 u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp); 1176 1177 static inline void bnx2x_init_txdata(struct bnx2x *bp, 1178 struct bnx2x_fp_txdata *txdata, u32 cid, 1179 int txq_index, __le16 *tx_cons_sb, 1180 struct bnx2x_fastpath *fp) 1181 { 1182 txdata->cid = cid; 1183 txdata->txq_index = txq_index; 1184 txdata->tx_cons_sb = tx_cons_sb; 1185 txdata->parent_fp = fp; 1186 txdata->tx_ring_size = IS_FCOE_FP(fp) ? MAX_TX_AVAIL : bp->tx_ring_size; 1187 1188 DP(NETIF_MSG_IFUP, "created tx data cid %d, txq %d\n", 1189 txdata->cid, txdata->txq_index); 1190 } 1191 1192 static inline u8 bnx2x_cnic_eth_cl_id(struct bnx2x *bp, u8 cl_idx) 1193 { 1194 return bp->cnic_base_cl_id + cl_idx + 1195 (bp->pf_num >> 1) * BNX2X_MAX_CNIC_ETH_CL_ID_IDX; 1196 } 1197 1198 static inline u8 bnx2x_cnic_fw_sb_id(struct bnx2x *bp) 1199 { 1200 /* the 'first' id is allocated for the cnic */ 1201 return bp->base_fw_ndsb; 1202 } 1203 1204 static inline u8 bnx2x_cnic_igu_sb_id(struct bnx2x *bp) 1205 { 1206 return bp->igu_base_sb; 1207 } 1208 1209 static inline void bnx2x_init_fcoe_fp(struct bnx2x *bp) 1210 { 1211 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp); 1212 unsigned long q_type = 0; 1213 1214 bnx2x_fcoe(bp, rx_queue) = BNX2X_NUM_ETH_QUEUES(bp); 1215 bnx2x_fcoe(bp, cl_id) = bnx2x_cnic_eth_cl_id(bp, 1216 BNX2X_FCOE_ETH_CL_ID_IDX); 1217 bnx2x_fcoe(bp, cid) = BNX2X_FCOE_ETH_CID(bp); 1218 bnx2x_fcoe(bp, fw_sb_id) = DEF_SB_ID; 1219 bnx2x_fcoe(bp, igu_sb_id) = bp->igu_dsb_id; 1220 bnx2x_fcoe(bp, rx_cons_sb) = BNX2X_FCOE_L2_RX_INDEX; 1221 bnx2x_init_txdata(bp, bnx2x_fcoe(bp, txdata_ptr[0]), 1222 fp->cid, FCOE_TXQ_IDX(bp), BNX2X_FCOE_L2_TX_INDEX, 1223 fp); 1224 1225 DP(NETIF_MSG_IFUP, "created fcoe tx data (fp index %d)\n", fp->index); 1226 1227 /* qZone id equals to FW (per path) client id */ 1228 bnx2x_fcoe(bp, cl_qzone_id) = bnx2x_fp_qzone_id(fp); 1229 /* init shortcut */ 1230 bnx2x_fcoe(bp, ustorm_rx_prods_offset) = 1231 bnx2x_rx_ustorm_prods_offset(fp); 1232 1233 /* Configure Queue State object */ 1234 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type); 1235 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type); 1236 1237 /* No multi-CoS for FCoE L2 client */ 1238 BUG_ON(fp->max_cos != 1); 1239 1240 bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, 1241 &fp->cid, 1, BP_FUNC(bp), bnx2x_sp(bp, q_rdata), 1242 bnx2x_sp_mapping(bp, q_rdata), q_type); 1243 1244 DP(NETIF_MSG_IFUP, 1245 "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n", 1246 fp->index, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id, 1247 fp->igu_sb_id); 1248 } 1249 1250 static inline int bnx2x_clean_tx_queue(struct bnx2x *bp, 1251 struct bnx2x_fp_txdata *txdata) 1252 { 1253 int cnt = 1000; 1254 1255 while (bnx2x_has_tx_work_unload(txdata)) { 1256 if (!cnt) { 1257 BNX2X_ERR("timeout waiting for queue[%d]: txdata->tx_pkt_prod(%d) != txdata->tx_pkt_cons(%d)\n", 1258 txdata->txq_index, txdata->tx_pkt_prod, 1259 txdata->tx_pkt_cons); 1260 #ifdef BNX2X_STOP_ON_ERROR 1261 bnx2x_panic(); 1262 return -EBUSY; 1263 #else 1264 break; 1265 #endif 1266 } 1267 cnt--; 1268 usleep_range(1000, 2000); 1269 } 1270 1271 return 0; 1272 } 1273 1274 int bnx2x_get_link_cfg_idx(struct bnx2x *bp); 1275 1276 static inline void __storm_memset_struct(struct bnx2x *bp, 1277 u32 addr, size_t size, u32 *data) 1278 { 1279 int i; 1280 for (i = 0; i < size/4; i++) 1281 REG_WR(bp, addr + (i * 4), data[i]); 1282 } 1283 1284 /** 1285 * bnx2x_wait_sp_comp - wait for the outstanding SP commands. 1286 * 1287 * @bp: driver handle 1288 * @mask: bits that need to be cleared 1289 */ 1290 static inline bool bnx2x_wait_sp_comp(struct bnx2x *bp, unsigned long mask) 1291 { 1292 int tout = 5000; /* Wait for 5 secs tops */ 1293 1294 while (tout--) { 1295 smp_mb(); 1296 netif_addr_lock_bh(bp->dev); 1297 if (!(bp->sp_state & mask)) { 1298 netif_addr_unlock_bh(bp->dev); 1299 return true; 1300 } 1301 netif_addr_unlock_bh(bp->dev); 1302 1303 usleep_range(1000, 2000); 1304 } 1305 1306 smp_mb(); 1307 1308 netif_addr_lock_bh(bp->dev); 1309 if (bp->sp_state & mask) { 1310 BNX2X_ERR("Filtering completion timed out. sp_state 0x%lx, mask 0x%lx\n", 1311 bp->sp_state, mask); 1312 netif_addr_unlock_bh(bp->dev); 1313 return false; 1314 } 1315 netif_addr_unlock_bh(bp->dev); 1316 1317 return true; 1318 } 1319 1320 /** 1321 * bnx2x_set_ctx_validation - set CDU context validation values 1322 * 1323 * @bp: driver handle 1324 * @cxt: context of the connection on the host memory 1325 * @cid: SW CID of the connection to be configured 1326 */ 1327 void bnx2x_set_ctx_validation(struct bnx2x *bp, struct eth_context *cxt, 1328 u32 cid); 1329 1330 void bnx2x_update_coalesce_sb_index(struct bnx2x *bp, u8 fw_sb_id, 1331 u8 sb_index, u8 disable, u16 usec); 1332 void bnx2x_acquire_phy_lock(struct bnx2x *bp); 1333 void bnx2x_release_phy_lock(struct bnx2x *bp); 1334 1335 /** 1336 * bnx2x_extract_max_cfg - extract MAX BW part from MF configuration. 1337 * 1338 * @bp: driver handle 1339 * @mf_cfg: MF configuration 1340 * 1341 */ 1342 static inline u16 bnx2x_extract_max_cfg(struct bnx2x *bp, u32 mf_cfg) 1343 { 1344 u16 max_cfg = (mf_cfg & FUNC_MF_CFG_MAX_BW_MASK) >> 1345 FUNC_MF_CFG_MAX_BW_SHIFT; 1346 if (!max_cfg) { 1347 DP(NETIF_MSG_IFUP | BNX2X_MSG_ETHTOOL, 1348 "Max BW configured to 0 - using 100 instead\n"); 1349 max_cfg = 100; 1350 } 1351 return max_cfg; 1352 } 1353 1354 /* checks if HW supports GRO for given MTU */ 1355 static inline bool bnx2x_mtu_allows_gro(int mtu) 1356 { 1357 /* gro frags per page */ 1358 int fpp = SGE_PAGE_SIZE / (mtu - ETH_MAX_TPA_HEADER_SIZE); 1359 1360 /* 1361 * 1. Number of frags should not grow above MAX_SKB_FRAGS 1362 * 2. Frag must fit the page 1363 */ 1364 return mtu <= SGE_PAGE_SIZE && (U_ETH_SGL_SIZE * fpp) <= MAX_SKB_FRAGS; 1365 } 1366 1367 /** 1368 * bnx2x_get_iscsi_info - update iSCSI params according to licensing info. 1369 * 1370 * @bp: driver handle 1371 * 1372 */ 1373 void bnx2x_get_iscsi_info(struct bnx2x *bp); 1374 1375 /** 1376 * bnx2x_link_sync_notify - send notification to other functions. 1377 * 1378 * @bp: driver handle 1379 * 1380 */ 1381 static inline void bnx2x_link_sync_notify(struct bnx2x *bp) 1382 { 1383 int func; 1384 int vn; 1385 1386 /* Set the attention towards other drivers on the same port */ 1387 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { 1388 if (vn == BP_VN(bp)) 1389 continue; 1390 1391 func = func_by_vn(bp, vn); 1392 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_0 + 1393 (LINK_SYNC_ATTENTION_BIT_FUNC_0 + func)*4, 1); 1394 } 1395 } 1396 1397 /** 1398 * bnx2x_update_drv_flags - update flags in shmem 1399 * 1400 * @bp: driver handle 1401 * @flags: flags to update 1402 * @set: set or clear 1403 * 1404 */ 1405 static inline void bnx2x_update_drv_flags(struct bnx2x *bp, u32 flags, u32 set) 1406 { 1407 if (SHMEM2_HAS(bp, drv_flags)) { 1408 u32 drv_flags; 1409 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_DRV_FLAGS); 1410 drv_flags = SHMEM2_RD(bp, drv_flags); 1411 1412 if (set) 1413 SET_FLAGS(drv_flags, flags); 1414 else 1415 RESET_FLAGS(drv_flags, flags); 1416 1417 SHMEM2_WR(bp, drv_flags, drv_flags); 1418 DP(NETIF_MSG_IFUP, "drv_flags 0x%08x\n", drv_flags); 1419 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_DRV_FLAGS); 1420 } 1421 } 1422 1423 static inline bool bnx2x_is_valid_ether_addr(struct bnx2x *bp, u8 *addr) 1424 { 1425 if (is_valid_ether_addr(addr) || 1426 (is_zero_ether_addr(addr) && 1427 (IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp)))) 1428 return true; 1429 1430 return false; 1431 } 1432 1433 /** 1434 * bnx2x_fill_fw_str - Fill buffer with FW version string 1435 * 1436 * @bp: driver handle 1437 * @buf: character buffer to fill with the fw name 1438 * @buf_len: length of the above buffer 1439 * 1440 */ 1441 void bnx2x_fill_fw_str(struct bnx2x *bp, char *buf, size_t buf_len); 1442 1443 int bnx2x_drain_tx_queues(struct bnx2x *bp); 1444 void bnx2x_squeeze_objects(struct bnx2x *bp); 1445 1446 #endif /* BNX2X_CMN_H */ 1447