1 /* bnx2x_cmn.h: Broadcom Everest network driver. 2 * 3 * Copyright (c) 2007-2013 Broadcom Corporation 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation. 8 * 9 * Maintained by: Eilon Greenstein <eilong@broadcom.com> 10 * Written by: Eliezer Tamir 11 * Based on code from Michael Chan's bnx2 driver 12 * UDP CSUM errata workaround by Arik Gendelman 13 * Slowpath and fastpath rework by Vladislav Zolotarov 14 * Statistics and Link management by Yitchak Gertner 15 * 16 */ 17 #ifndef BNX2X_CMN_H 18 #define BNX2X_CMN_H 19 20 #include <linux/types.h> 21 #include <linux/pci.h> 22 #include <linux/netdevice.h> 23 #include <linux/etherdevice.h> 24 25 #include "bnx2x.h" 26 #include "bnx2x_sriov.h" 27 28 /* This is used as a replacement for an MCP if it's not present */ 29 extern int load_count[2][3]; /* per-path: 0-common, 1-port0, 2-port1 */ 30 31 extern int num_queues; 32 extern int int_mode; 33 34 /************************ Macros ********************************/ 35 #define BNX2X_PCI_FREE(x, y, size) \ 36 do { \ 37 if (x) { \ 38 dma_free_coherent(&bp->pdev->dev, size, (void *)x, y); \ 39 x = NULL; \ 40 y = 0; \ 41 } \ 42 } while (0) 43 44 #define BNX2X_FREE(x) \ 45 do { \ 46 if (x) { \ 47 kfree((void *)x); \ 48 x = NULL; \ 49 } \ 50 } while (0) 51 52 #define BNX2X_PCI_ALLOC(x, y, size) \ 53 do { \ 54 x = dma_alloc_coherent(&bp->pdev->dev, size, y, \ 55 GFP_KERNEL | __GFP_ZERO); \ 56 if (x == NULL) \ 57 goto alloc_mem_err; \ 58 DP(NETIF_MSG_HW, "BNX2X_PCI_ALLOC: Physical %Lx Virtual %p\n", \ 59 (unsigned long long)(*y), x); \ 60 } while (0) 61 62 #define BNX2X_PCI_FALLOC(x, y, size) \ 63 do { \ 64 x = dma_alloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL); \ 65 if (x == NULL) \ 66 goto alloc_mem_err; \ 67 memset((void *)x, 0xFFFFFFFF, size); \ 68 DP(NETIF_MSG_HW, "BNX2X_PCI_FALLOC: Physical %Lx Virtual %p\n",\ 69 (unsigned long long)(*y), x); \ 70 } while (0) 71 72 #define BNX2X_ALLOC(x, size) \ 73 do { \ 74 x = kzalloc(size, GFP_KERNEL); \ 75 if (x == NULL) \ 76 goto alloc_mem_err; \ 77 } while (0) 78 79 /*********************** Interfaces **************************** 80 * Functions that need to be implemented by each driver version 81 */ 82 /* Init */ 83 84 /** 85 * bnx2x_send_unload_req - request unload mode from the MCP. 86 * 87 * @bp: driver handle 88 * @unload_mode: requested function's unload mode 89 * 90 * Return unload mode returned by the MCP: COMMON, PORT or FUNC. 91 */ 92 u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode); 93 94 /** 95 * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP. 96 * 97 * @bp: driver handle 98 * @keep_link: true iff link should be kept up 99 */ 100 void bnx2x_send_unload_done(struct bnx2x *bp, bool keep_link); 101 102 /** 103 * bnx2x_config_rss_pf - configure RSS parameters in a PF. 104 * 105 * @bp: driver handle 106 * @rss_obj: RSS object to use 107 * @ind_table: indirection table to configure 108 * @config_hash: re-configure RSS hash keys configuration 109 */ 110 int bnx2x_config_rss_pf(struct bnx2x *bp, struct bnx2x_rss_config_obj *rss_obj, 111 bool config_hash); 112 113 /** 114 * bnx2x__init_func_obj - init function object 115 * 116 * @bp: driver handle 117 * 118 * Initializes the Function Object with the appropriate 119 * parameters which include a function slow path driver 120 * interface. 121 */ 122 void bnx2x__init_func_obj(struct bnx2x *bp); 123 124 /** 125 * bnx2x_setup_queue - setup eth queue. 126 * 127 * @bp: driver handle 128 * @fp: pointer to the fastpath structure 129 * @leading: boolean 130 * 131 */ 132 int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp, 133 bool leading); 134 135 /** 136 * bnx2x_setup_leading - bring up a leading eth queue. 137 * 138 * @bp: driver handle 139 */ 140 int bnx2x_setup_leading(struct bnx2x *bp); 141 142 /** 143 * bnx2x_fw_command - send the MCP a request 144 * 145 * @bp: driver handle 146 * @command: request 147 * @param: request's parameter 148 * 149 * block until there is a reply 150 */ 151 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param); 152 153 /** 154 * bnx2x_initial_phy_init - initialize link parameters structure variables. 155 * 156 * @bp: driver handle 157 * @load_mode: current mode 158 */ 159 int bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode); 160 161 /** 162 * bnx2x_link_set - configure hw according to link parameters structure. 163 * 164 * @bp: driver handle 165 */ 166 void bnx2x_link_set(struct bnx2x *bp); 167 168 /** 169 * bnx2x_force_link_reset - Forces link reset, and put the PHY 170 * in reset as well. 171 * 172 * @bp: driver handle 173 */ 174 void bnx2x_force_link_reset(struct bnx2x *bp); 175 176 /** 177 * bnx2x_link_test - query link status. 178 * 179 * @bp: driver handle 180 * @is_serdes: bool 181 * 182 * Returns 0 if link is UP. 183 */ 184 u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes); 185 186 /** 187 * bnx2x_drv_pulse - write driver pulse to shmem 188 * 189 * @bp: driver handle 190 * 191 * writes the value in bp->fw_drv_pulse_wr_seq to drv_pulse mbox 192 * in the shmem. 193 */ 194 void bnx2x_drv_pulse(struct bnx2x *bp); 195 196 /** 197 * bnx2x_igu_ack_sb - update IGU with current SB value 198 * 199 * @bp: driver handle 200 * @igu_sb_id: SB id 201 * @segment: SB segment 202 * @index: SB index 203 * @op: SB operation 204 * @update: is HW update required 205 */ 206 void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment, 207 u16 index, u8 op, u8 update); 208 209 /* Disable transactions from chip to host */ 210 void bnx2x_pf_disable(struct bnx2x *bp); 211 int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val); 212 213 /** 214 * bnx2x__link_status_update - handles link status change. 215 * 216 * @bp: driver handle 217 */ 218 void bnx2x__link_status_update(struct bnx2x *bp); 219 220 /** 221 * bnx2x_link_report - report link status to upper layer. 222 * 223 * @bp: driver handle 224 */ 225 void bnx2x_link_report(struct bnx2x *bp); 226 227 /* None-atomic version of bnx2x_link_report() */ 228 void __bnx2x_link_report(struct bnx2x *bp); 229 230 /** 231 * bnx2x_get_mf_speed - calculate MF speed. 232 * 233 * @bp: driver handle 234 * 235 * Takes into account current linespeed and MF configuration. 236 */ 237 u16 bnx2x_get_mf_speed(struct bnx2x *bp); 238 239 /** 240 * bnx2x_msix_sp_int - MSI-X slowpath interrupt handler 241 * 242 * @irq: irq number 243 * @dev_instance: private instance 244 */ 245 irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance); 246 247 /** 248 * bnx2x_interrupt - non MSI-X interrupt handler 249 * 250 * @irq: irq number 251 * @dev_instance: private instance 252 */ 253 irqreturn_t bnx2x_interrupt(int irq, void *dev_instance); 254 255 /** 256 * bnx2x_cnic_notify - send command to cnic driver 257 * 258 * @bp: driver handle 259 * @cmd: command 260 */ 261 int bnx2x_cnic_notify(struct bnx2x *bp, int cmd); 262 263 /** 264 * bnx2x_setup_cnic_irq_info - provides cnic with IRQ information 265 * 266 * @bp: driver handle 267 */ 268 void bnx2x_setup_cnic_irq_info(struct bnx2x *bp); 269 270 /** 271 * bnx2x_setup_cnic_info - provides cnic with updated info 272 * 273 * @bp: driver handle 274 */ 275 void bnx2x_setup_cnic_info(struct bnx2x *bp); 276 277 /** 278 * bnx2x_int_enable - enable HW interrupts. 279 * 280 * @bp: driver handle 281 */ 282 void bnx2x_int_enable(struct bnx2x *bp); 283 284 /** 285 * bnx2x_int_disable_sync - disable interrupts. 286 * 287 * @bp: driver handle 288 * @disable_hw: true, disable HW interrupts. 289 * 290 * This function ensures that there are no 291 * ISRs or SP DPCs (sp_task) are running after it returns. 292 */ 293 void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw); 294 295 /** 296 * bnx2x_nic_init_cnic - init driver internals for cnic. 297 * 298 * @bp: driver handle 299 * @load_code: COMMON, PORT or FUNCTION 300 * 301 * Initializes: 302 * - rings 303 * - status blocks 304 * - etc. 305 */ 306 void bnx2x_nic_init_cnic(struct bnx2x *bp); 307 308 /** 309 * bnx2x_preirq_nic_init - init driver internals. 310 * 311 * @bp: driver handle 312 * 313 * Initializes: 314 * - fastpath object 315 * - fastpath rings 316 * etc. 317 */ 318 void bnx2x_pre_irq_nic_init(struct bnx2x *bp); 319 320 /** 321 * bnx2x_postirq_nic_init - init driver internals. 322 * 323 * @bp: driver handle 324 * @load_code: COMMON, PORT or FUNCTION 325 * 326 * Initializes: 327 * - status blocks 328 * - slowpath rings 329 * - etc. 330 */ 331 void bnx2x_post_irq_nic_init(struct bnx2x *bp, u32 load_code); 332 /** 333 * bnx2x_alloc_mem_cnic - allocate driver's memory for cnic. 334 * 335 * @bp: driver handle 336 */ 337 int bnx2x_alloc_mem_cnic(struct bnx2x *bp); 338 /** 339 * bnx2x_alloc_mem - allocate driver's memory. 340 * 341 * @bp: driver handle 342 */ 343 int bnx2x_alloc_mem(struct bnx2x *bp); 344 345 /** 346 * bnx2x_free_mem_cnic - release driver's memory for cnic. 347 * 348 * @bp: driver handle 349 */ 350 void bnx2x_free_mem_cnic(struct bnx2x *bp); 351 /** 352 * bnx2x_free_mem - release driver's memory. 353 * 354 * @bp: driver handle 355 */ 356 void bnx2x_free_mem(struct bnx2x *bp); 357 358 /** 359 * bnx2x_set_num_queues - set number of queues according to mode. 360 * 361 * @bp: driver handle 362 */ 363 void bnx2x_set_num_queues(struct bnx2x *bp); 364 365 /** 366 * bnx2x_chip_cleanup - cleanup chip internals. 367 * 368 * @bp: driver handle 369 * @unload_mode: COMMON, PORT, FUNCTION 370 * @keep_link: true iff link should be kept up. 371 * 372 * - Cleanup MAC configuration. 373 * - Closes clients. 374 * - etc. 375 */ 376 void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode, bool keep_link); 377 378 /** 379 * bnx2x_acquire_hw_lock - acquire HW lock. 380 * 381 * @bp: driver handle 382 * @resource: resource bit which was locked 383 */ 384 int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource); 385 386 /** 387 * bnx2x_release_hw_lock - release HW lock. 388 * 389 * @bp: driver handle 390 * @resource: resource bit which was locked 391 */ 392 int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource); 393 394 /** 395 * bnx2x_release_leader_lock - release recovery leader lock 396 * 397 * @bp: driver handle 398 */ 399 int bnx2x_release_leader_lock(struct bnx2x *bp); 400 401 /** 402 * bnx2x_set_eth_mac - configure eth MAC address in the HW 403 * 404 * @bp: driver handle 405 * @set: set or clear 406 * 407 * Configures according to the value in netdev->dev_addr. 408 */ 409 int bnx2x_set_eth_mac(struct bnx2x *bp, bool set); 410 411 /** 412 * bnx2x_set_rx_mode - set MAC filtering configurations. 413 * 414 * @dev: netdevice 415 * 416 * called with netif_tx_lock from dev_mcast.c 417 * If bp->state is OPEN, should be called with 418 * netif_addr_lock_bh() 419 */ 420 void bnx2x_set_rx_mode(struct net_device *dev); 421 422 /** 423 * bnx2x_set_storm_rx_mode - configure MAC filtering rules in a FW. 424 * 425 * @bp: driver handle 426 * 427 * If bp->state is OPEN, should be called with 428 * netif_addr_lock_bh(). 429 */ 430 int bnx2x_set_storm_rx_mode(struct bnx2x *bp); 431 432 /** 433 * bnx2x_set_q_rx_mode - configures rx_mode for a single queue. 434 * 435 * @bp: driver handle 436 * @cl_id: client id 437 * @rx_mode_flags: rx mode configuration 438 * @rx_accept_flags: rx accept configuration 439 * @tx_accept_flags: tx accept configuration (tx switch) 440 * @ramrod_flags: ramrod configuration 441 */ 442 int bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id, 443 unsigned long rx_mode_flags, 444 unsigned long rx_accept_flags, 445 unsigned long tx_accept_flags, 446 unsigned long ramrod_flags); 447 448 /* Parity errors related */ 449 void bnx2x_set_pf_load(struct bnx2x *bp); 450 bool bnx2x_clear_pf_load(struct bnx2x *bp); 451 bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print); 452 bool bnx2x_reset_is_done(struct bnx2x *bp, int engine); 453 void bnx2x_set_reset_in_progress(struct bnx2x *bp); 454 void bnx2x_set_reset_global(struct bnx2x *bp); 455 void bnx2x_disable_close_the_gate(struct bnx2x *bp); 456 int bnx2x_init_hw_func_cnic(struct bnx2x *bp); 457 458 /** 459 * bnx2x_sp_event - handle ramrods completion. 460 * 461 * @fp: fastpath handle for the event 462 * @rr_cqe: eth_rx_cqe 463 */ 464 void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe); 465 466 /** 467 * bnx2x_ilt_set_info - prepare ILT configurations. 468 * 469 * @bp: driver handle 470 */ 471 void bnx2x_ilt_set_info(struct bnx2x *bp); 472 473 /** 474 * bnx2x_ilt_set_cnic_info - prepare ILT configurations for SRC 475 * and TM. 476 * 477 * @bp: driver handle 478 */ 479 void bnx2x_ilt_set_info_cnic(struct bnx2x *bp); 480 481 /** 482 * bnx2x_dcbx_init - initialize dcbx protocol. 483 * 484 * @bp: driver handle 485 */ 486 void bnx2x_dcbx_init(struct bnx2x *bp, bool update_shmem); 487 488 /** 489 * bnx2x_set_power_state - set power state to the requested value. 490 * 491 * @bp: driver handle 492 * @state: required state D0 or D3hot 493 * 494 * Currently only D0 and D3hot are supported. 495 */ 496 int bnx2x_set_power_state(struct bnx2x *bp, pci_power_t state); 497 498 /** 499 * bnx2x_update_max_mf_config - update MAX part of MF configuration in HW. 500 * 501 * @bp: driver handle 502 * @value: new value 503 */ 504 void bnx2x_update_max_mf_config(struct bnx2x *bp, u32 value); 505 /* Error handling */ 506 void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl); 507 508 /* dev_close main block */ 509 int bnx2x_nic_unload(struct bnx2x *bp, int unload_mode, bool keep_link); 510 511 /* dev_open main block */ 512 int bnx2x_nic_load(struct bnx2x *bp, int load_mode); 513 514 /* hard_xmit callback */ 515 netdev_tx_t bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev); 516 517 /* setup_tc callback */ 518 int bnx2x_setup_tc(struct net_device *dev, u8 num_tc); 519 520 int bnx2x_get_vf_config(struct net_device *dev, int vf, 521 struct ifla_vf_info *ivi); 522 int bnx2x_set_vf_mac(struct net_device *dev, int queue, u8 *mac); 523 int bnx2x_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan, u8 qos); 524 525 /* select_queue callback */ 526 u16 bnx2x_select_queue(struct net_device *dev, struct sk_buff *skb); 527 528 static inline void bnx2x_update_rx_prod(struct bnx2x *bp, 529 struct bnx2x_fastpath *fp, 530 u16 bd_prod, u16 rx_comp_prod, 531 u16 rx_sge_prod) 532 { 533 struct ustorm_eth_rx_producers rx_prods = {0}; 534 u32 i; 535 536 /* Update producers */ 537 rx_prods.bd_prod = bd_prod; 538 rx_prods.cqe_prod = rx_comp_prod; 539 rx_prods.sge_prod = rx_sge_prod; 540 541 /* Make sure that the BD and SGE data is updated before updating the 542 * producers since FW might read the BD/SGE right after the producer 543 * is updated. 544 * This is only applicable for weak-ordered memory model archs such 545 * as IA-64. The following barrier is also mandatory since FW will 546 * assumes BDs must have buffers. 547 */ 548 wmb(); 549 550 for (i = 0; i < sizeof(rx_prods)/4; i++) 551 REG_WR(bp, fp->ustorm_rx_prods_offset + i*4, 552 ((u32 *)&rx_prods)[i]); 553 554 mmiowb(); /* keep prod updates ordered */ 555 556 DP(NETIF_MSG_RX_STATUS, 557 "queue[%d]: wrote bd_prod %u cqe_prod %u sge_prod %u\n", 558 fp->index, bd_prod, rx_comp_prod, rx_sge_prod); 559 } 560 561 /* reload helper */ 562 int bnx2x_reload_if_running(struct net_device *dev); 563 564 int bnx2x_change_mac_addr(struct net_device *dev, void *p); 565 566 /* NAPI poll Rx part */ 567 int bnx2x_rx_int(struct bnx2x_fastpath *fp, int budget); 568 569 /* NAPI poll Tx part */ 570 int bnx2x_tx_int(struct bnx2x *bp, struct bnx2x_fp_txdata *txdata); 571 572 /* suspend/resume callbacks */ 573 int bnx2x_suspend(struct pci_dev *pdev, pm_message_t state); 574 int bnx2x_resume(struct pci_dev *pdev); 575 576 /* Release IRQ vectors */ 577 void bnx2x_free_irq(struct bnx2x *bp); 578 579 void bnx2x_free_fp_mem_cnic(struct bnx2x *bp); 580 void bnx2x_free_fp_mem(struct bnx2x *bp); 581 int bnx2x_alloc_fp_mem_cnic(struct bnx2x *bp); 582 int bnx2x_alloc_fp_mem(struct bnx2x *bp); 583 void bnx2x_init_rx_rings(struct bnx2x *bp); 584 void bnx2x_init_rx_rings_cnic(struct bnx2x *bp); 585 void bnx2x_free_skbs_cnic(struct bnx2x *bp); 586 void bnx2x_free_skbs(struct bnx2x *bp); 587 void bnx2x_netif_stop(struct bnx2x *bp, int disable_hw); 588 void bnx2x_netif_start(struct bnx2x *bp); 589 int bnx2x_load_cnic(struct bnx2x *bp); 590 591 /** 592 * bnx2x_enable_msix - set msix configuration. 593 * 594 * @bp: driver handle 595 * 596 * fills msix_table, requests vectors, updates num_queues 597 * according to number of available vectors. 598 */ 599 int bnx2x_enable_msix(struct bnx2x *bp); 600 601 /** 602 * bnx2x_enable_msi - request msi mode from OS, updated internals accordingly 603 * 604 * @bp: driver handle 605 */ 606 int bnx2x_enable_msi(struct bnx2x *bp); 607 608 /** 609 * bnx2x_poll - NAPI callback 610 * 611 * @napi: napi structure 612 * @budget: 613 * 614 */ 615 int bnx2x_poll(struct napi_struct *napi, int budget); 616 617 /** 618 * bnx2x_low_latency_recv - LL callback 619 * 620 * @napi: napi structure 621 */ 622 int bnx2x_low_latency_recv(struct napi_struct *napi); 623 624 /** 625 * bnx2x_alloc_mem_bp - allocate memories outsize main driver structure 626 * 627 * @bp: driver handle 628 */ 629 int bnx2x_alloc_mem_bp(struct bnx2x *bp); 630 631 /** 632 * bnx2x_free_mem_bp - release memories outsize main driver structure 633 * 634 * @bp: driver handle 635 */ 636 void bnx2x_free_mem_bp(struct bnx2x *bp); 637 638 /** 639 * bnx2x_change_mtu - change mtu netdev callback 640 * 641 * @dev: net device 642 * @new_mtu: requested mtu 643 * 644 */ 645 int bnx2x_change_mtu(struct net_device *dev, int new_mtu); 646 647 #ifdef NETDEV_FCOE_WWNN 648 /** 649 * bnx2x_fcoe_get_wwn - return the requested WWN value for this port 650 * 651 * @dev: net_device 652 * @wwn: output buffer 653 * @type: WWN type: NETDEV_FCOE_WWNN (node) or NETDEV_FCOE_WWPN (port) 654 * 655 */ 656 int bnx2x_fcoe_get_wwn(struct net_device *dev, u64 *wwn, int type); 657 #endif 658 659 netdev_features_t bnx2x_fix_features(struct net_device *dev, 660 netdev_features_t features); 661 int bnx2x_set_features(struct net_device *dev, netdev_features_t features); 662 663 /** 664 * bnx2x_tx_timeout - tx timeout netdev callback 665 * 666 * @dev: net device 667 */ 668 void bnx2x_tx_timeout(struct net_device *dev); 669 670 /*********************** Inlines **********************************/ 671 /*********************** Fast path ********************************/ 672 static inline void bnx2x_update_fpsb_idx(struct bnx2x_fastpath *fp) 673 { 674 barrier(); /* status block is written to by the chip */ 675 fp->fp_hc_idx = fp->sb_running_index[SM_RX_ID]; 676 } 677 678 static inline void bnx2x_igu_ack_sb_gen(struct bnx2x *bp, u8 igu_sb_id, 679 u8 segment, u16 index, u8 op, 680 u8 update, u32 igu_addr) 681 { 682 struct igu_regular cmd_data = {0}; 683 684 cmd_data.sb_id_and_flags = 685 ((index << IGU_REGULAR_SB_INDEX_SHIFT) | 686 (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) | 687 (update << IGU_REGULAR_BUPDATE_SHIFT) | 688 (op << IGU_REGULAR_ENABLE_INT_SHIFT)); 689 690 DP(NETIF_MSG_INTR, "write 0x%08x to IGU addr 0x%x\n", 691 cmd_data.sb_id_and_flags, igu_addr); 692 REG_WR(bp, igu_addr, cmd_data.sb_id_and_flags); 693 694 /* Make sure that ACK is written */ 695 mmiowb(); 696 barrier(); 697 } 698 699 static inline void bnx2x_hc_ack_sb(struct bnx2x *bp, u8 sb_id, 700 u8 storm, u16 index, u8 op, u8 update) 701 { 702 u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 + 703 COMMAND_REG_INT_ACK); 704 struct igu_ack_register igu_ack; 705 706 igu_ack.status_block_index = index; 707 igu_ack.sb_id_and_flags = 708 ((sb_id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) | 709 (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) | 710 (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) | 711 (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT)); 712 713 REG_WR(bp, hc_addr, (*(u32 *)&igu_ack)); 714 715 /* Make sure that ACK is written */ 716 mmiowb(); 717 barrier(); 718 } 719 720 static inline void bnx2x_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 storm, 721 u16 index, u8 op, u8 update) 722 { 723 if (bp->common.int_block == INT_BLOCK_HC) 724 bnx2x_hc_ack_sb(bp, igu_sb_id, storm, index, op, update); 725 else { 726 u8 segment; 727 728 if (CHIP_INT_MODE_IS_BC(bp)) 729 segment = storm; 730 else if (igu_sb_id != bp->igu_dsb_id) 731 segment = IGU_SEG_ACCESS_DEF; 732 else if (storm == ATTENTION_ID) 733 segment = IGU_SEG_ACCESS_ATTN; 734 else 735 segment = IGU_SEG_ACCESS_DEF; 736 bnx2x_igu_ack_sb(bp, igu_sb_id, segment, index, op, update); 737 } 738 } 739 740 static inline u16 bnx2x_hc_ack_int(struct bnx2x *bp) 741 { 742 u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 + 743 COMMAND_REG_SIMD_MASK); 744 u32 result = REG_RD(bp, hc_addr); 745 746 barrier(); 747 return result; 748 } 749 750 static inline u16 bnx2x_igu_ack_int(struct bnx2x *bp) 751 { 752 u32 igu_addr = (BAR_IGU_INTMEM + IGU_REG_SISR_MDPC_WMASK_LSB_UPPER*8); 753 u32 result = REG_RD(bp, igu_addr); 754 755 DP(NETIF_MSG_INTR, "read 0x%08x from IGU addr 0x%x\n", 756 result, igu_addr); 757 758 barrier(); 759 return result; 760 } 761 762 static inline u16 bnx2x_ack_int(struct bnx2x *bp) 763 { 764 barrier(); 765 if (bp->common.int_block == INT_BLOCK_HC) 766 return bnx2x_hc_ack_int(bp); 767 else 768 return bnx2x_igu_ack_int(bp); 769 } 770 771 static inline int bnx2x_has_tx_work_unload(struct bnx2x_fp_txdata *txdata) 772 { 773 /* Tell compiler that consumer and producer can change */ 774 barrier(); 775 return txdata->tx_pkt_prod != txdata->tx_pkt_cons; 776 } 777 778 static inline u16 bnx2x_tx_avail(struct bnx2x *bp, 779 struct bnx2x_fp_txdata *txdata) 780 { 781 s16 used; 782 u16 prod; 783 u16 cons; 784 785 prod = txdata->tx_bd_prod; 786 cons = txdata->tx_bd_cons; 787 788 used = SUB_S16(prod, cons); 789 790 #ifdef BNX2X_STOP_ON_ERROR 791 WARN_ON(used < 0); 792 WARN_ON(used > txdata->tx_ring_size); 793 WARN_ON((txdata->tx_ring_size - used) > MAX_TX_AVAIL); 794 #endif 795 796 return (s16)(txdata->tx_ring_size) - used; 797 } 798 799 static inline int bnx2x_tx_queue_has_work(struct bnx2x_fp_txdata *txdata) 800 { 801 u16 hw_cons; 802 803 /* Tell compiler that status block fields can change */ 804 barrier(); 805 hw_cons = le16_to_cpu(*txdata->tx_cons_sb); 806 return hw_cons != txdata->tx_pkt_cons; 807 } 808 809 static inline bool bnx2x_has_tx_work(struct bnx2x_fastpath *fp) 810 { 811 u8 cos; 812 for_each_cos_in_tx_queue(fp, cos) 813 if (bnx2x_tx_queue_has_work(fp->txdata_ptr[cos])) 814 return true; 815 return false; 816 } 817 818 #define BNX2X_IS_CQE_COMPLETED(cqe_fp) (cqe_fp->marker == 0x0) 819 #define BNX2X_SEED_CQE(cqe_fp) (cqe_fp->marker = 0xFFFFFFFF) 820 static inline int bnx2x_has_rx_work(struct bnx2x_fastpath *fp) 821 { 822 u16 cons; 823 union eth_rx_cqe *cqe; 824 struct eth_fast_path_rx_cqe *cqe_fp; 825 826 cons = RCQ_BD(fp->rx_comp_cons); 827 cqe = &fp->rx_comp_ring[cons]; 828 cqe_fp = &cqe->fast_path_cqe; 829 return BNX2X_IS_CQE_COMPLETED(cqe_fp); 830 } 831 832 /** 833 * bnx2x_tx_disable - disables tx from stack point of view 834 * 835 * @bp: driver handle 836 */ 837 static inline void bnx2x_tx_disable(struct bnx2x *bp) 838 { 839 netif_tx_disable(bp->dev); 840 netif_carrier_off(bp->dev); 841 } 842 843 static inline void bnx2x_free_rx_sge(struct bnx2x *bp, 844 struct bnx2x_fastpath *fp, u16 index) 845 { 846 struct sw_rx_page *sw_buf = &fp->rx_page_ring[index]; 847 struct page *page = sw_buf->page; 848 struct eth_rx_sge *sge = &fp->rx_sge_ring[index]; 849 850 /* Skip "next page" elements */ 851 if (!page) 852 return; 853 854 dma_unmap_page(&bp->pdev->dev, dma_unmap_addr(sw_buf, mapping), 855 SGE_PAGES, DMA_FROM_DEVICE); 856 __free_pages(page, PAGES_PER_SGE_SHIFT); 857 858 sw_buf->page = NULL; 859 sge->addr_hi = 0; 860 sge->addr_lo = 0; 861 } 862 863 static inline void bnx2x_add_all_napi_cnic(struct bnx2x *bp) 864 { 865 int i; 866 867 /* Add NAPI objects */ 868 for_each_rx_queue_cnic(bp, i) { 869 netif_napi_add(bp->dev, &bnx2x_fp(bp, i, napi), 870 bnx2x_poll, NAPI_POLL_WEIGHT); 871 napi_hash_add(&bnx2x_fp(bp, i, napi)); 872 } 873 } 874 875 static inline void bnx2x_add_all_napi(struct bnx2x *bp) 876 { 877 int i; 878 879 /* Add NAPI objects */ 880 for_each_eth_queue(bp, i) { 881 netif_napi_add(bp->dev, &bnx2x_fp(bp, i, napi), 882 bnx2x_poll, NAPI_POLL_WEIGHT); 883 napi_hash_add(&bnx2x_fp(bp, i, napi)); 884 } 885 } 886 887 static inline void bnx2x_del_all_napi_cnic(struct bnx2x *bp) 888 { 889 int i; 890 891 for_each_rx_queue_cnic(bp, i) { 892 napi_hash_del(&bnx2x_fp(bp, i, napi)); 893 netif_napi_del(&bnx2x_fp(bp, i, napi)); 894 } 895 } 896 897 static inline void bnx2x_del_all_napi(struct bnx2x *bp) 898 { 899 int i; 900 901 for_each_eth_queue(bp, i) { 902 napi_hash_del(&bnx2x_fp(bp, i, napi)); 903 netif_napi_del(&bnx2x_fp(bp, i, napi)); 904 } 905 } 906 907 int bnx2x_set_int_mode(struct bnx2x *bp); 908 909 static inline void bnx2x_disable_msi(struct bnx2x *bp) 910 { 911 if (bp->flags & USING_MSIX_FLAG) { 912 pci_disable_msix(bp->pdev); 913 bp->flags &= ~(USING_MSIX_FLAG | USING_SINGLE_MSIX_FLAG); 914 } else if (bp->flags & USING_MSI_FLAG) { 915 pci_disable_msi(bp->pdev); 916 bp->flags &= ~USING_MSI_FLAG; 917 } 918 } 919 920 static inline int bnx2x_calc_num_queues(struct bnx2x *bp) 921 { 922 return num_queues ? 923 min_t(int, num_queues, BNX2X_MAX_QUEUES(bp)) : 924 min_t(int, netif_get_num_default_rss_queues(), 925 BNX2X_MAX_QUEUES(bp)); 926 } 927 928 static inline void bnx2x_clear_sge_mask_next_elems(struct bnx2x_fastpath *fp) 929 { 930 int i, j; 931 932 for (i = 1; i <= NUM_RX_SGE_PAGES; i++) { 933 int idx = RX_SGE_CNT * i - 1; 934 935 for (j = 0; j < 2; j++) { 936 BIT_VEC64_CLEAR_BIT(fp->sge_mask, idx); 937 idx--; 938 } 939 } 940 } 941 942 static inline void bnx2x_init_sge_ring_bit_mask(struct bnx2x_fastpath *fp) 943 { 944 /* Set the mask to all 1-s: it's faster to compare to 0 than to 0xf-s */ 945 memset(fp->sge_mask, 0xff, sizeof(fp->sge_mask)); 946 947 /* Clear the two last indices in the page to 1: 948 these are the indices that correspond to the "next" element, 949 hence will never be indicated and should be removed from 950 the calculations. */ 951 bnx2x_clear_sge_mask_next_elems(fp); 952 } 953 954 /* note that we are not allocating a new buffer, 955 * we are just moving one from cons to prod 956 * we are not creating a new mapping, 957 * so there is no need to check for dma_mapping_error(). 958 */ 959 static inline void bnx2x_reuse_rx_data(struct bnx2x_fastpath *fp, 960 u16 cons, u16 prod) 961 { 962 struct sw_rx_bd *cons_rx_buf = &fp->rx_buf_ring[cons]; 963 struct sw_rx_bd *prod_rx_buf = &fp->rx_buf_ring[prod]; 964 struct eth_rx_bd *cons_bd = &fp->rx_desc_ring[cons]; 965 struct eth_rx_bd *prod_bd = &fp->rx_desc_ring[prod]; 966 967 dma_unmap_addr_set(prod_rx_buf, mapping, 968 dma_unmap_addr(cons_rx_buf, mapping)); 969 prod_rx_buf->data = cons_rx_buf->data; 970 *prod_bd = *cons_bd; 971 } 972 973 /************************* Init ******************************************/ 974 975 /* returns func by VN for current port */ 976 static inline int func_by_vn(struct bnx2x *bp, int vn) 977 { 978 return 2 * vn + BP_PORT(bp); 979 } 980 981 static inline int bnx2x_config_rss_eth(struct bnx2x *bp, bool config_hash) 982 { 983 return bnx2x_config_rss_pf(bp, &bp->rss_conf_obj, config_hash); 984 } 985 986 /** 987 * bnx2x_func_start - init function 988 * 989 * @bp: driver handle 990 * 991 * Must be called before sending CLIENT_SETUP for the first client. 992 */ 993 static inline int bnx2x_func_start(struct bnx2x *bp) 994 { 995 struct bnx2x_func_state_params func_params = {NULL}; 996 struct bnx2x_func_start_params *start_params = 997 &func_params.params.start; 998 999 /* Prepare parameters for function state transitions */ 1000 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); 1001 1002 func_params.f_obj = &bp->func_obj; 1003 func_params.cmd = BNX2X_F_CMD_START; 1004 1005 /* Function parameters */ 1006 start_params->mf_mode = bp->mf_mode; 1007 start_params->sd_vlan_tag = bp->mf_ov; 1008 1009 if (CHIP_IS_E2(bp) || CHIP_IS_E3(bp)) 1010 start_params->network_cos_mode = STATIC_COS; 1011 else /* CHIP_IS_E1X */ 1012 start_params->network_cos_mode = FW_WRR; 1013 1014 start_params->gre_tunnel_mode = IPGRE_TUNNEL; 1015 start_params->gre_tunnel_rss = GRE_INNER_HEADERS_RSS; 1016 1017 return bnx2x_func_state_change(bp, &func_params); 1018 } 1019 1020 /** 1021 * bnx2x_set_fw_mac_addr - fill in a MAC address in FW format 1022 * 1023 * @fw_hi: pointer to upper part 1024 * @fw_mid: pointer to middle part 1025 * @fw_lo: pointer to lower part 1026 * @mac: pointer to MAC address 1027 */ 1028 static inline void bnx2x_set_fw_mac_addr(__le16 *fw_hi, __le16 *fw_mid, 1029 __le16 *fw_lo, u8 *mac) 1030 { 1031 ((u8 *)fw_hi)[0] = mac[1]; 1032 ((u8 *)fw_hi)[1] = mac[0]; 1033 ((u8 *)fw_mid)[0] = mac[3]; 1034 ((u8 *)fw_mid)[1] = mac[2]; 1035 ((u8 *)fw_lo)[0] = mac[5]; 1036 ((u8 *)fw_lo)[1] = mac[4]; 1037 } 1038 1039 static inline void bnx2x_free_rx_sge_range(struct bnx2x *bp, 1040 struct bnx2x_fastpath *fp, int last) 1041 { 1042 int i; 1043 1044 if (fp->disable_tpa) 1045 return; 1046 1047 for (i = 0; i < last; i++) 1048 bnx2x_free_rx_sge(bp, fp, i); 1049 } 1050 1051 static inline void bnx2x_set_next_page_rx_bd(struct bnx2x_fastpath *fp) 1052 { 1053 int i; 1054 1055 for (i = 1; i <= NUM_RX_RINGS; i++) { 1056 struct eth_rx_bd *rx_bd; 1057 1058 rx_bd = &fp->rx_desc_ring[RX_DESC_CNT * i - 2]; 1059 rx_bd->addr_hi = 1060 cpu_to_le32(U64_HI(fp->rx_desc_mapping + 1061 BCM_PAGE_SIZE*(i % NUM_RX_RINGS))); 1062 rx_bd->addr_lo = 1063 cpu_to_le32(U64_LO(fp->rx_desc_mapping + 1064 BCM_PAGE_SIZE*(i % NUM_RX_RINGS))); 1065 } 1066 } 1067 1068 /* Statistics ID are global per chip/path, while Client IDs for E1x are per 1069 * port. 1070 */ 1071 static inline u8 bnx2x_stats_id(struct bnx2x_fastpath *fp) 1072 { 1073 struct bnx2x *bp = fp->bp; 1074 if (!CHIP_IS_E1x(bp)) { 1075 /* there are special statistics counters for FCoE 136..140 */ 1076 if (IS_FCOE_FP(fp)) 1077 return bp->cnic_base_cl_id + (bp->pf_num >> 1); 1078 return fp->cl_id; 1079 } 1080 return fp->cl_id + BP_PORT(bp) * FP_SB_MAX_E1x; 1081 } 1082 1083 static inline void bnx2x_init_vlan_mac_fp_objs(struct bnx2x_fastpath *fp, 1084 bnx2x_obj_type obj_type) 1085 { 1086 struct bnx2x *bp = fp->bp; 1087 1088 /* Configure classification DBs */ 1089 bnx2x_init_mac_obj(bp, &bnx2x_sp_obj(bp, fp).mac_obj, fp->cl_id, 1090 fp->cid, BP_FUNC(bp), bnx2x_sp(bp, mac_rdata), 1091 bnx2x_sp_mapping(bp, mac_rdata), 1092 BNX2X_FILTER_MAC_PENDING, 1093 &bp->sp_state, obj_type, 1094 &bp->macs_pool); 1095 } 1096 1097 /** 1098 * bnx2x_get_path_func_num - get number of active functions 1099 * 1100 * @bp: driver handle 1101 * 1102 * Calculates the number of active (not hidden) functions on the 1103 * current path. 1104 */ 1105 static inline u8 bnx2x_get_path_func_num(struct bnx2x *bp) 1106 { 1107 u8 func_num = 0, i; 1108 1109 /* 57710 has only one function per-port */ 1110 if (CHIP_IS_E1(bp)) 1111 return 1; 1112 1113 /* Calculate a number of functions enabled on the current 1114 * PATH/PORT. 1115 */ 1116 if (CHIP_REV_IS_SLOW(bp)) { 1117 if (IS_MF(bp)) 1118 func_num = 4; 1119 else 1120 func_num = 2; 1121 } else { 1122 for (i = 0; i < E1H_FUNC_MAX / 2; i++) { 1123 u32 func_config = 1124 MF_CFG_RD(bp, 1125 func_mf_config[BP_PORT(bp) + 2 * i]. 1126 config); 1127 func_num += 1128 ((func_config & FUNC_MF_CFG_FUNC_HIDE) ? 0 : 1); 1129 } 1130 } 1131 1132 WARN_ON(!func_num); 1133 1134 return func_num; 1135 } 1136 1137 static inline void bnx2x_init_bp_objs(struct bnx2x *bp) 1138 { 1139 /* RX_MODE controlling object */ 1140 bnx2x_init_rx_mode_obj(bp, &bp->rx_mode_obj); 1141 1142 /* multicast configuration controlling object */ 1143 bnx2x_init_mcast_obj(bp, &bp->mcast_obj, bp->fp->cl_id, bp->fp->cid, 1144 BP_FUNC(bp), BP_FUNC(bp), 1145 bnx2x_sp(bp, mcast_rdata), 1146 bnx2x_sp_mapping(bp, mcast_rdata), 1147 BNX2X_FILTER_MCAST_PENDING, &bp->sp_state, 1148 BNX2X_OBJ_TYPE_RX); 1149 1150 /* Setup CAM credit pools */ 1151 bnx2x_init_mac_credit_pool(bp, &bp->macs_pool, BP_FUNC(bp), 1152 bnx2x_get_path_func_num(bp)); 1153 1154 bnx2x_init_vlan_credit_pool(bp, &bp->vlans_pool, BP_ABS_FUNC(bp)>>1, 1155 bnx2x_get_path_func_num(bp)); 1156 1157 /* RSS configuration object */ 1158 bnx2x_init_rss_config_obj(bp, &bp->rss_conf_obj, bp->fp->cl_id, 1159 bp->fp->cid, BP_FUNC(bp), BP_FUNC(bp), 1160 bnx2x_sp(bp, rss_rdata), 1161 bnx2x_sp_mapping(bp, rss_rdata), 1162 BNX2X_FILTER_RSS_CONF_PENDING, &bp->sp_state, 1163 BNX2X_OBJ_TYPE_RX); 1164 } 1165 1166 static inline u8 bnx2x_fp_qzone_id(struct bnx2x_fastpath *fp) 1167 { 1168 if (CHIP_IS_E1x(fp->bp)) 1169 return fp->cl_id + BP_PORT(fp->bp) * ETH_MAX_RX_CLIENTS_E1H; 1170 else 1171 return fp->cl_id; 1172 } 1173 1174 u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp); 1175 1176 static inline void bnx2x_init_txdata(struct bnx2x *bp, 1177 struct bnx2x_fp_txdata *txdata, u32 cid, 1178 int txq_index, __le16 *tx_cons_sb, 1179 struct bnx2x_fastpath *fp) 1180 { 1181 txdata->cid = cid; 1182 txdata->txq_index = txq_index; 1183 txdata->tx_cons_sb = tx_cons_sb; 1184 txdata->parent_fp = fp; 1185 txdata->tx_ring_size = IS_FCOE_FP(fp) ? MAX_TX_AVAIL : bp->tx_ring_size; 1186 1187 DP(NETIF_MSG_IFUP, "created tx data cid %d, txq %d\n", 1188 txdata->cid, txdata->txq_index); 1189 } 1190 1191 static inline u8 bnx2x_cnic_eth_cl_id(struct bnx2x *bp, u8 cl_idx) 1192 { 1193 return bp->cnic_base_cl_id + cl_idx + 1194 (bp->pf_num >> 1) * BNX2X_MAX_CNIC_ETH_CL_ID_IDX; 1195 } 1196 1197 static inline u8 bnx2x_cnic_fw_sb_id(struct bnx2x *bp) 1198 { 1199 /* the 'first' id is allocated for the cnic */ 1200 return bp->base_fw_ndsb; 1201 } 1202 1203 static inline u8 bnx2x_cnic_igu_sb_id(struct bnx2x *bp) 1204 { 1205 return bp->igu_base_sb; 1206 } 1207 1208 static inline void bnx2x_init_fcoe_fp(struct bnx2x *bp) 1209 { 1210 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp); 1211 unsigned long q_type = 0; 1212 1213 bnx2x_fcoe(bp, rx_queue) = BNX2X_NUM_ETH_QUEUES(bp); 1214 bnx2x_fcoe(bp, cl_id) = bnx2x_cnic_eth_cl_id(bp, 1215 BNX2X_FCOE_ETH_CL_ID_IDX); 1216 bnx2x_fcoe(bp, cid) = BNX2X_FCOE_ETH_CID(bp); 1217 bnx2x_fcoe(bp, fw_sb_id) = DEF_SB_ID; 1218 bnx2x_fcoe(bp, igu_sb_id) = bp->igu_dsb_id; 1219 bnx2x_fcoe(bp, rx_cons_sb) = BNX2X_FCOE_L2_RX_INDEX; 1220 bnx2x_init_txdata(bp, bnx2x_fcoe(bp, txdata_ptr[0]), 1221 fp->cid, FCOE_TXQ_IDX(bp), BNX2X_FCOE_L2_TX_INDEX, 1222 fp); 1223 1224 DP(NETIF_MSG_IFUP, "created fcoe tx data (fp index %d)\n", fp->index); 1225 1226 /* qZone id equals to FW (per path) client id */ 1227 bnx2x_fcoe(bp, cl_qzone_id) = bnx2x_fp_qzone_id(fp); 1228 /* init shortcut */ 1229 bnx2x_fcoe(bp, ustorm_rx_prods_offset) = 1230 bnx2x_rx_ustorm_prods_offset(fp); 1231 1232 /* Configure Queue State object */ 1233 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type); 1234 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type); 1235 1236 /* No multi-CoS for FCoE L2 client */ 1237 BUG_ON(fp->max_cos != 1); 1238 1239 bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, 1240 &fp->cid, 1, BP_FUNC(bp), bnx2x_sp(bp, q_rdata), 1241 bnx2x_sp_mapping(bp, q_rdata), q_type); 1242 1243 DP(NETIF_MSG_IFUP, 1244 "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n", 1245 fp->index, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id, 1246 fp->igu_sb_id); 1247 } 1248 1249 static inline int bnx2x_clean_tx_queue(struct bnx2x *bp, 1250 struct bnx2x_fp_txdata *txdata) 1251 { 1252 int cnt = 1000; 1253 1254 while (bnx2x_has_tx_work_unload(txdata)) { 1255 if (!cnt) { 1256 BNX2X_ERR("timeout waiting for queue[%d]: txdata->tx_pkt_prod(%d) != txdata->tx_pkt_cons(%d)\n", 1257 txdata->txq_index, txdata->tx_pkt_prod, 1258 txdata->tx_pkt_cons); 1259 #ifdef BNX2X_STOP_ON_ERROR 1260 bnx2x_panic(); 1261 return -EBUSY; 1262 #else 1263 break; 1264 #endif 1265 } 1266 cnt--; 1267 usleep_range(1000, 2000); 1268 } 1269 1270 return 0; 1271 } 1272 1273 int bnx2x_get_link_cfg_idx(struct bnx2x *bp); 1274 1275 static inline void __storm_memset_struct(struct bnx2x *bp, 1276 u32 addr, size_t size, u32 *data) 1277 { 1278 int i; 1279 for (i = 0; i < size/4; i++) 1280 REG_WR(bp, addr + (i * 4), data[i]); 1281 } 1282 1283 /** 1284 * bnx2x_wait_sp_comp - wait for the outstanding SP commands. 1285 * 1286 * @bp: driver handle 1287 * @mask: bits that need to be cleared 1288 */ 1289 static inline bool bnx2x_wait_sp_comp(struct bnx2x *bp, unsigned long mask) 1290 { 1291 int tout = 5000; /* Wait for 5 secs tops */ 1292 1293 while (tout--) { 1294 smp_mb(); 1295 netif_addr_lock_bh(bp->dev); 1296 if (!(bp->sp_state & mask)) { 1297 netif_addr_unlock_bh(bp->dev); 1298 return true; 1299 } 1300 netif_addr_unlock_bh(bp->dev); 1301 1302 usleep_range(1000, 2000); 1303 } 1304 1305 smp_mb(); 1306 1307 netif_addr_lock_bh(bp->dev); 1308 if (bp->sp_state & mask) { 1309 BNX2X_ERR("Filtering completion timed out. sp_state 0x%lx, mask 0x%lx\n", 1310 bp->sp_state, mask); 1311 netif_addr_unlock_bh(bp->dev); 1312 return false; 1313 } 1314 netif_addr_unlock_bh(bp->dev); 1315 1316 return true; 1317 } 1318 1319 /** 1320 * bnx2x_set_ctx_validation - set CDU context validation values 1321 * 1322 * @bp: driver handle 1323 * @cxt: context of the connection on the host memory 1324 * @cid: SW CID of the connection to be configured 1325 */ 1326 void bnx2x_set_ctx_validation(struct bnx2x *bp, struct eth_context *cxt, 1327 u32 cid); 1328 1329 void bnx2x_update_coalesce_sb_index(struct bnx2x *bp, u8 fw_sb_id, 1330 u8 sb_index, u8 disable, u16 usec); 1331 void bnx2x_acquire_phy_lock(struct bnx2x *bp); 1332 void bnx2x_release_phy_lock(struct bnx2x *bp); 1333 1334 /** 1335 * bnx2x_extract_max_cfg - extract MAX BW part from MF configuration. 1336 * 1337 * @bp: driver handle 1338 * @mf_cfg: MF configuration 1339 * 1340 */ 1341 static inline u16 bnx2x_extract_max_cfg(struct bnx2x *bp, u32 mf_cfg) 1342 { 1343 u16 max_cfg = (mf_cfg & FUNC_MF_CFG_MAX_BW_MASK) >> 1344 FUNC_MF_CFG_MAX_BW_SHIFT; 1345 if (!max_cfg) { 1346 DP(NETIF_MSG_IFUP | BNX2X_MSG_ETHTOOL, 1347 "Max BW configured to 0 - using 100 instead\n"); 1348 max_cfg = 100; 1349 } 1350 return max_cfg; 1351 } 1352 1353 /* checks if HW supports GRO for given MTU */ 1354 static inline bool bnx2x_mtu_allows_gro(int mtu) 1355 { 1356 /* gro frags per page */ 1357 int fpp = SGE_PAGE_SIZE / (mtu - ETH_MAX_TPA_HEADER_SIZE); 1358 1359 /* 1360 * 1. Number of frags should not grow above MAX_SKB_FRAGS 1361 * 2. Frag must fit the page 1362 */ 1363 return mtu <= SGE_PAGE_SIZE && (U_ETH_SGL_SIZE * fpp) <= MAX_SKB_FRAGS; 1364 } 1365 1366 /** 1367 * bnx2x_get_iscsi_info - update iSCSI params according to licensing info. 1368 * 1369 * @bp: driver handle 1370 * 1371 */ 1372 void bnx2x_get_iscsi_info(struct bnx2x *bp); 1373 1374 /** 1375 * bnx2x_link_sync_notify - send notification to other functions. 1376 * 1377 * @bp: driver handle 1378 * 1379 */ 1380 static inline void bnx2x_link_sync_notify(struct bnx2x *bp) 1381 { 1382 int func; 1383 int vn; 1384 1385 /* Set the attention towards other drivers on the same port */ 1386 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { 1387 if (vn == BP_VN(bp)) 1388 continue; 1389 1390 func = func_by_vn(bp, vn); 1391 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_0 + 1392 (LINK_SYNC_ATTENTION_BIT_FUNC_0 + func)*4, 1); 1393 } 1394 } 1395 1396 /** 1397 * bnx2x_update_drv_flags - update flags in shmem 1398 * 1399 * @bp: driver handle 1400 * @flags: flags to update 1401 * @set: set or clear 1402 * 1403 */ 1404 static inline void bnx2x_update_drv_flags(struct bnx2x *bp, u32 flags, u32 set) 1405 { 1406 if (SHMEM2_HAS(bp, drv_flags)) { 1407 u32 drv_flags; 1408 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_DRV_FLAGS); 1409 drv_flags = SHMEM2_RD(bp, drv_flags); 1410 1411 if (set) 1412 SET_FLAGS(drv_flags, flags); 1413 else 1414 RESET_FLAGS(drv_flags, flags); 1415 1416 SHMEM2_WR(bp, drv_flags, drv_flags); 1417 DP(NETIF_MSG_IFUP, "drv_flags 0x%08x\n", drv_flags); 1418 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_DRV_FLAGS); 1419 } 1420 } 1421 1422 static inline bool bnx2x_is_valid_ether_addr(struct bnx2x *bp, u8 *addr) 1423 { 1424 if (is_valid_ether_addr(addr) || 1425 (is_zero_ether_addr(addr) && 1426 (IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp)))) 1427 return true; 1428 1429 return false; 1430 } 1431 1432 /** 1433 * bnx2x_fill_fw_str - Fill buffer with FW version string 1434 * 1435 * @bp: driver handle 1436 * @buf: character buffer to fill with the fw name 1437 * @buf_len: length of the above buffer 1438 * 1439 */ 1440 void bnx2x_fill_fw_str(struct bnx2x *bp, char *buf, size_t buf_len); 1441 1442 int bnx2x_drain_tx_queues(struct bnx2x *bp); 1443 void bnx2x_squeeze_objects(struct bnx2x *bp); 1444 1445 #endif /* BNX2X_CMN_H */ 1446