1 /* bnx2x.h: Broadcom Everest network driver. 2 * 3 * Copyright (c) 2007-2013 Broadcom Corporation 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation. 8 * 9 * Maintained by: Ariel Elior <ariel.elior@qlogic.com> 10 * Written by: Eliezer Tamir 11 * Based on code from Michael Chan's bnx2 driver 12 */ 13 14 #ifndef BNX2X_H 15 #define BNX2X_H 16 17 #include <linux/pci.h> 18 #include <linux/netdevice.h> 19 #include <linux/dma-mapping.h> 20 #include <linux/types.h> 21 #include <linux/pci_regs.h> 22 23 /* compilation time flags */ 24 25 /* define this to make the driver freeze on error to allow getting debug info 26 * (you will need to reboot afterwards) */ 27 /* #define BNX2X_STOP_ON_ERROR */ 28 29 #define DRV_MODULE_VERSION "1.78.19-0" 30 #define DRV_MODULE_RELDATE "2014/02/10" 31 #define BNX2X_BC_VER 0x040200 32 33 #if defined(CONFIG_DCB) 34 #define BCM_DCBNL 35 #endif 36 37 #include "bnx2x_hsi.h" 38 39 #include "../cnic_if.h" 40 41 #define BNX2X_MIN_MSIX_VEC_CNT(bp) ((bp)->min_msix_vec_cnt) 42 43 #include <linux/mdio.h> 44 45 #include "bnx2x_reg.h" 46 #include "bnx2x_fw_defs.h" 47 #include "bnx2x_mfw_req.h" 48 #include "bnx2x_link.h" 49 #include "bnx2x_sp.h" 50 #include "bnx2x_dcb.h" 51 #include "bnx2x_stats.h" 52 #include "bnx2x_vfpf.h" 53 54 enum bnx2x_int_mode { 55 BNX2X_INT_MODE_MSIX, 56 BNX2X_INT_MODE_INTX, 57 BNX2X_INT_MODE_MSI 58 }; 59 60 /* error/debug prints */ 61 62 #define DRV_MODULE_NAME "bnx2x" 63 64 /* for messages that are currently off */ 65 #define BNX2X_MSG_OFF 0x0 66 #define BNX2X_MSG_MCP 0x0010000 /* was: NETIF_MSG_HW */ 67 #define BNX2X_MSG_STATS 0x0020000 /* was: NETIF_MSG_TIMER */ 68 #define BNX2X_MSG_NVM 0x0040000 /* was: NETIF_MSG_HW */ 69 #define BNX2X_MSG_DMAE 0x0080000 /* was: NETIF_MSG_HW */ 70 #define BNX2X_MSG_SP 0x0100000 /* was: NETIF_MSG_INTR */ 71 #define BNX2X_MSG_FP 0x0200000 /* was: NETIF_MSG_INTR */ 72 #define BNX2X_MSG_IOV 0x0800000 73 #define BNX2X_MSG_IDLE 0x2000000 /* used for idle check*/ 74 #define BNX2X_MSG_ETHTOOL 0x4000000 75 #define BNX2X_MSG_DCB 0x8000000 76 77 /* regular debug print */ 78 #define DP_INNER(fmt, ...) \ 79 pr_notice("[%s:%d(%s)]" fmt, \ 80 __func__, __LINE__, \ 81 bp->dev ? (bp->dev->name) : "?", \ 82 ##__VA_ARGS__); 83 84 #define DP(__mask, fmt, ...) \ 85 do { \ 86 if (unlikely(bp->msg_enable & (__mask))) \ 87 DP_INNER(fmt, ##__VA_ARGS__); \ 88 } while (0) 89 90 #define DP_AND(__mask, fmt, ...) \ 91 do { \ 92 if (unlikely((bp->msg_enable & (__mask)) == __mask)) \ 93 DP_INNER(fmt, ##__VA_ARGS__); \ 94 } while (0) 95 96 #define DP_CONT(__mask, fmt, ...) \ 97 do { \ 98 if (unlikely(bp->msg_enable & (__mask))) \ 99 pr_cont(fmt, ##__VA_ARGS__); \ 100 } while (0) 101 102 /* errors debug print */ 103 #define BNX2X_DBG_ERR(fmt, ...) \ 104 do { \ 105 if (unlikely(netif_msg_probe(bp))) \ 106 pr_err("[%s:%d(%s)]" fmt, \ 107 __func__, __LINE__, \ 108 bp->dev ? (bp->dev->name) : "?", \ 109 ##__VA_ARGS__); \ 110 } while (0) 111 112 /* for errors (never masked) */ 113 #define BNX2X_ERR(fmt, ...) \ 114 do { \ 115 pr_err("[%s:%d(%s)]" fmt, \ 116 __func__, __LINE__, \ 117 bp->dev ? (bp->dev->name) : "?", \ 118 ##__VA_ARGS__); \ 119 } while (0) 120 121 #define BNX2X_ERROR(fmt, ...) \ 122 pr_err("[%s:%d]" fmt, __func__, __LINE__, ##__VA_ARGS__) 123 124 /* before we have a dev->name use dev_info() */ 125 #define BNX2X_DEV_INFO(fmt, ...) \ 126 do { \ 127 if (unlikely(netif_msg_probe(bp))) \ 128 dev_info(&bp->pdev->dev, fmt, ##__VA_ARGS__); \ 129 } while (0) 130 131 /* Error handling */ 132 void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int); 133 #ifdef BNX2X_STOP_ON_ERROR 134 #define bnx2x_panic() \ 135 do { \ 136 bp->panic = 1; \ 137 BNX2X_ERR("driver assert\n"); \ 138 bnx2x_panic_dump(bp, true); \ 139 } while (0) 140 #else 141 #define bnx2x_panic() \ 142 do { \ 143 bp->panic = 1; \ 144 BNX2X_ERR("driver assert\n"); \ 145 bnx2x_panic_dump(bp, false); \ 146 } while (0) 147 #endif 148 149 #define bnx2x_mc_addr(ha) ((ha)->addr) 150 #define bnx2x_uc_addr(ha) ((ha)->addr) 151 152 #define U64_LO(x) ((u32)(((u64)(x)) & 0xffffffff)) 153 #define U64_HI(x) ((u32)(((u64)(x)) >> 32)) 154 #define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo)) 155 156 #define REG_ADDR(bp, offset) ((bp->regview) + (offset)) 157 158 #define REG_RD(bp, offset) readl(REG_ADDR(bp, offset)) 159 #define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset)) 160 #define REG_RD16(bp, offset) readw(REG_ADDR(bp, offset)) 161 162 #define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset)) 163 #define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset)) 164 #define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset)) 165 166 #define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset) 167 #define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val) 168 169 #define REG_RD_DMAE(bp, offset, valp, len32) \ 170 do { \ 171 bnx2x_read_dmae(bp, offset, len32);\ 172 memcpy(valp, bnx2x_sp(bp, wb_data[0]), (len32) * 4); \ 173 } while (0) 174 175 #define REG_WR_DMAE(bp, offset, valp, len32) \ 176 do { \ 177 memcpy(bnx2x_sp(bp, wb_data[0]), valp, (len32) * 4); \ 178 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \ 179 offset, len32); \ 180 } while (0) 181 182 #define REG_WR_DMAE_LEN(bp, offset, valp, len32) \ 183 REG_WR_DMAE(bp, offset, valp, len32) 184 185 #define VIRT_WR_DMAE_LEN(bp, data, addr, len32, le32_swap) \ 186 do { \ 187 memcpy(GUNZIP_BUF(bp), data, (len32) * 4); \ 188 bnx2x_write_big_buf_wb(bp, addr, len32); \ 189 } while (0) 190 191 #define SHMEM_ADDR(bp, field) (bp->common.shmem_base + \ 192 offsetof(struct shmem_region, field)) 193 #define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field)) 194 #define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val) 195 196 #define SHMEM2_ADDR(bp, field) (bp->common.shmem2_base + \ 197 offsetof(struct shmem2_region, field)) 198 #define SHMEM2_RD(bp, field) REG_RD(bp, SHMEM2_ADDR(bp, field)) 199 #define SHMEM2_WR(bp, field, val) REG_WR(bp, SHMEM2_ADDR(bp, field), val) 200 #define MF_CFG_ADDR(bp, field) (bp->common.mf_cfg_base + \ 201 offsetof(struct mf_cfg, field)) 202 #define MF2_CFG_ADDR(bp, field) (bp->common.mf2_cfg_base + \ 203 offsetof(struct mf2_cfg, field)) 204 205 #define MF_CFG_RD(bp, field) REG_RD(bp, MF_CFG_ADDR(bp, field)) 206 #define MF_CFG_WR(bp, field, val) REG_WR(bp,\ 207 MF_CFG_ADDR(bp, field), (val)) 208 #define MF2_CFG_RD(bp, field) REG_RD(bp, MF2_CFG_ADDR(bp, field)) 209 210 #define SHMEM2_HAS(bp, field) ((bp)->common.shmem2_base && \ 211 (SHMEM2_RD((bp), size) > \ 212 offsetof(struct shmem2_region, field))) 213 214 #define EMAC_RD(bp, reg) REG_RD(bp, emac_base + reg) 215 #define EMAC_WR(bp, reg, val) REG_WR(bp, emac_base + reg, val) 216 217 /* SP SB indices */ 218 219 /* General SP events - stats query, cfc delete, etc */ 220 #define HC_SP_INDEX_ETH_DEF_CONS 3 221 222 /* EQ completions */ 223 #define HC_SP_INDEX_EQ_CONS 7 224 225 /* FCoE L2 connection completions */ 226 #define HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS 6 227 #define HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS 4 228 /* iSCSI L2 */ 229 #define HC_SP_INDEX_ETH_ISCSI_CQ_CONS 5 230 #define HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS 1 231 232 /* Special clients parameters */ 233 234 /* SB indices */ 235 /* FCoE L2 */ 236 #define BNX2X_FCOE_L2_RX_INDEX \ 237 (&bp->def_status_blk->sp_sb.\ 238 index_values[HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS]) 239 240 #define BNX2X_FCOE_L2_TX_INDEX \ 241 (&bp->def_status_blk->sp_sb.\ 242 index_values[HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS]) 243 244 /** 245 * CIDs and CLIDs: 246 * CLIDs below is a CLID for func 0, then the CLID for other 247 * functions will be calculated by the formula: 248 * 249 * FUNC_N_CLID_X = N * NUM_SPECIAL_CLIENTS + FUNC_0_CLID_X 250 * 251 */ 252 enum { 253 BNX2X_ISCSI_ETH_CL_ID_IDX, 254 BNX2X_FCOE_ETH_CL_ID_IDX, 255 BNX2X_MAX_CNIC_ETH_CL_ID_IDX, 256 }; 257 258 /* use a value high enough to be above all the PFs, which has least significant 259 * nibble as 8, so when cnic needs to come up with a CID for UIO to use to 260 * calculate doorbell address according to old doorbell configuration scheme 261 * (db_msg_sz 1 << 7 * cid + 0x40 DPM offset) it can come up with a valid number 262 * We must avoid coming up with cid 8 for iscsi since according to this method 263 * the designated UIO cid will come out 0 and it has a special handling for that 264 * case which doesn't suit us. Therefore will will cieling to closes cid which 265 * has least signigifcant nibble 8 and if it is 8 we will move forward to 0x18. 266 */ 267 268 #define BNX2X_1st_NON_L2_ETH_CID(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) * \ 269 (bp)->max_cos) 270 /* amount of cids traversed by UIO's DPM addition to doorbell */ 271 #define UIO_DPM 8 272 /* roundup to DPM offset */ 273 #define UIO_ROUNDUP(bp) (roundup(BNX2X_1st_NON_L2_ETH_CID(bp), \ 274 UIO_DPM)) 275 /* offset to nearest value which has lsb nibble matching DPM */ 276 #define UIO_CID_OFFSET(bp) ((UIO_ROUNDUP(bp) + UIO_DPM) % \ 277 (UIO_DPM * 2)) 278 /* add offset to rounded-up cid to get a value which could be used with UIO */ 279 #define UIO_DPM_ALIGN(bp) (UIO_ROUNDUP(bp) + UIO_CID_OFFSET(bp)) 280 /* but wait - avoid UIO special case for cid 0 */ 281 #define UIO_DPM_CID0_OFFSET(bp) ((UIO_DPM * 2) * \ 282 (UIO_DPM_ALIGN(bp) == UIO_DPM)) 283 /* Properly DPM aligned CID dajusted to cid 0 secal case */ 284 #define BNX2X_CNIC_START_ETH_CID(bp) (UIO_DPM_ALIGN(bp) + \ 285 (UIO_DPM_CID0_OFFSET(bp))) 286 /* how many cids were wasted - need this value for cid allocation */ 287 #define UIO_CID_PAD(bp) (BNX2X_CNIC_START_ETH_CID(bp) - \ 288 BNX2X_1st_NON_L2_ETH_CID(bp)) 289 /* iSCSI L2 */ 290 #define BNX2X_ISCSI_ETH_CID(bp) (BNX2X_CNIC_START_ETH_CID(bp)) 291 /* FCoE L2 */ 292 #define BNX2X_FCOE_ETH_CID(bp) (BNX2X_CNIC_START_ETH_CID(bp) + 1) 293 294 #define CNIC_SUPPORT(bp) ((bp)->cnic_support) 295 #define CNIC_ENABLED(bp) ((bp)->cnic_enabled) 296 #define CNIC_LOADED(bp) ((bp)->cnic_loaded) 297 #define FCOE_INIT(bp) ((bp)->fcoe_init) 298 299 #define AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR \ 300 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR 301 302 #define SM_RX_ID 0 303 #define SM_TX_ID 1 304 305 /* defines for multiple tx priority indices */ 306 #define FIRST_TX_ONLY_COS_INDEX 1 307 #define FIRST_TX_COS_INDEX 0 308 309 /* rules for calculating the cids of tx-only connections */ 310 #define CID_TO_FP(cid, bp) ((cid) % BNX2X_NUM_NON_CNIC_QUEUES(bp)) 311 #define CID_COS_TO_TX_ONLY_CID(cid, cos, bp) \ 312 (cid + cos * BNX2X_NUM_NON_CNIC_QUEUES(bp)) 313 314 /* fp index inside class of service range */ 315 #define FP_COS_TO_TXQ(fp, cos, bp) \ 316 ((fp)->index + cos * BNX2X_NUM_NON_CNIC_QUEUES(bp)) 317 318 /* Indexes for transmission queues array: 319 * txdata for RSS i CoS j is at location i + (j * num of RSS) 320 * txdata for FCoE (if exist) is at location max cos * num of RSS 321 * txdata for FWD (if exist) is one location after FCoE 322 * txdata for OOO (if exist) is one location after FWD 323 */ 324 enum { 325 FCOE_TXQ_IDX_OFFSET, 326 FWD_TXQ_IDX_OFFSET, 327 OOO_TXQ_IDX_OFFSET, 328 }; 329 #define MAX_ETH_TXQ_IDX(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) * (bp)->max_cos) 330 #define FCOE_TXQ_IDX(bp) (MAX_ETH_TXQ_IDX(bp) + FCOE_TXQ_IDX_OFFSET) 331 332 /* fast path */ 333 /* 334 * This driver uses new build_skb() API : 335 * RX ring buffer contains pointer to kmalloc() data only, 336 * skb are built only after Hardware filled the frame. 337 */ 338 struct sw_rx_bd { 339 u8 *data; 340 DEFINE_DMA_UNMAP_ADDR(mapping); 341 }; 342 343 struct sw_tx_bd { 344 struct sk_buff *skb; 345 u16 first_bd; 346 u8 flags; 347 /* Set on the first BD descriptor when there is a split BD */ 348 #define BNX2X_TSO_SPLIT_BD (1<<0) 349 #define BNX2X_HAS_SECOND_PBD (1<<1) 350 }; 351 352 struct sw_rx_page { 353 struct page *page; 354 DEFINE_DMA_UNMAP_ADDR(mapping); 355 }; 356 357 union db_prod { 358 struct doorbell_set_prod data; 359 u32 raw; 360 }; 361 362 /* dropless fc FW/HW related params */ 363 #define BRB_SIZE(bp) (CHIP_IS_E3(bp) ? 1024 : 512) 364 #define MAX_AGG_QS(bp) (CHIP_IS_E1(bp) ? \ 365 ETH_MAX_AGGREGATION_QUEUES_E1 :\ 366 ETH_MAX_AGGREGATION_QUEUES_E1H_E2) 367 #define FW_DROP_LEVEL(bp) (3 + MAX_SPQ_PENDING + MAX_AGG_QS(bp)) 368 #define FW_PREFETCH_CNT 16 369 #define DROPLESS_FC_HEADROOM 100 370 371 /* MC hsi */ 372 #define BCM_PAGE_SHIFT 12 373 #define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT) 374 #define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1)) 375 #define BCM_PAGE_ALIGN(addr) (((addr) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK) 376 377 #define PAGES_PER_SGE_SHIFT 0 378 #define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT) 379 #define SGE_PAGE_SIZE PAGE_SIZE 380 #define SGE_PAGE_SHIFT PAGE_SHIFT 381 #define SGE_PAGE_ALIGN(addr) PAGE_ALIGN((typeof(PAGE_SIZE))(addr)) 382 #define SGE_PAGES (SGE_PAGE_SIZE * PAGES_PER_SGE) 383 #define TPA_AGG_SIZE min_t(u32, (min_t(u32, 8, MAX_SKB_FRAGS) * \ 384 SGE_PAGES), 0xffff) 385 386 /* SGE ring related macros */ 387 #define NUM_RX_SGE_PAGES 2 388 #define RX_SGE_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge)) 389 #define NEXT_PAGE_SGE_DESC_CNT 2 390 #define MAX_RX_SGE_CNT (RX_SGE_CNT - NEXT_PAGE_SGE_DESC_CNT) 391 /* RX_SGE_CNT is promised to be a power of 2 */ 392 #define RX_SGE_MASK (RX_SGE_CNT - 1) 393 #define NUM_RX_SGE (RX_SGE_CNT * NUM_RX_SGE_PAGES) 394 #define MAX_RX_SGE (NUM_RX_SGE - 1) 395 #define NEXT_SGE_IDX(x) ((((x) & RX_SGE_MASK) == \ 396 (MAX_RX_SGE_CNT - 1)) ? \ 397 (x) + 1 + NEXT_PAGE_SGE_DESC_CNT : \ 398 (x) + 1) 399 #define RX_SGE(x) ((x) & MAX_RX_SGE) 400 401 /* 402 * Number of required SGEs is the sum of two: 403 * 1. Number of possible opened aggregations (next packet for 404 * these aggregations will probably consume SGE immediately) 405 * 2. Rest of BRB blocks divided by 2 (block will consume new SGE only 406 * after placement on BD for new TPA aggregation) 407 * 408 * Takes into account NEXT_PAGE_SGE_DESC_CNT "next" elements on each page 409 */ 410 #define NUM_SGE_REQ (MAX_AGG_QS(bp) + \ 411 (BRB_SIZE(bp) - MAX_AGG_QS(bp)) / 2) 412 #define NUM_SGE_PG_REQ ((NUM_SGE_REQ + MAX_RX_SGE_CNT - 1) / \ 413 MAX_RX_SGE_CNT) 414 #define SGE_TH_LO(bp) (NUM_SGE_REQ + \ 415 NUM_SGE_PG_REQ * NEXT_PAGE_SGE_DESC_CNT) 416 #define SGE_TH_HI(bp) (SGE_TH_LO(bp) + DROPLESS_FC_HEADROOM) 417 418 /* Manipulate a bit vector defined as an array of u64 */ 419 420 /* Number of bits in one sge_mask array element */ 421 #define BIT_VEC64_ELEM_SZ 64 422 #define BIT_VEC64_ELEM_SHIFT 6 423 #define BIT_VEC64_ELEM_MASK ((u64)BIT_VEC64_ELEM_SZ - 1) 424 425 #define __BIT_VEC64_SET_BIT(el, bit) \ 426 do { \ 427 el = ((el) | ((u64)0x1 << (bit))); \ 428 } while (0) 429 430 #define __BIT_VEC64_CLEAR_BIT(el, bit) \ 431 do { \ 432 el = ((el) & (~((u64)0x1 << (bit)))); \ 433 } while (0) 434 435 #define BIT_VEC64_SET_BIT(vec64, idx) \ 436 __BIT_VEC64_SET_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \ 437 (idx) & BIT_VEC64_ELEM_MASK) 438 439 #define BIT_VEC64_CLEAR_BIT(vec64, idx) \ 440 __BIT_VEC64_CLEAR_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \ 441 (idx) & BIT_VEC64_ELEM_MASK) 442 443 #define BIT_VEC64_TEST_BIT(vec64, idx) \ 444 (((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT] >> \ 445 ((idx) & BIT_VEC64_ELEM_MASK)) & 0x1) 446 447 /* Creates a bitmask of all ones in less significant bits. 448 idx - index of the most significant bit in the created mask */ 449 #define BIT_VEC64_ONES_MASK(idx) \ 450 (((u64)0x1 << (((idx) & BIT_VEC64_ELEM_MASK) + 1)) - 1) 451 #define BIT_VEC64_ELEM_ONE_MASK ((u64)(~0)) 452 453 /*******************************************************/ 454 455 /* Number of u64 elements in SGE mask array */ 456 #define RX_SGE_MASK_LEN (NUM_RX_SGE / BIT_VEC64_ELEM_SZ) 457 #define RX_SGE_MASK_LEN_MASK (RX_SGE_MASK_LEN - 1) 458 #define NEXT_SGE_MASK_ELEM(el) (((el) + 1) & RX_SGE_MASK_LEN_MASK) 459 460 union host_hc_status_block { 461 /* pointer to fp status block e1x */ 462 struct host_hc_status_block_e1x *e1x_sb; 463 /* pointer to fp status block e2 */ 464 struct host_hc_status_block_e2 *e2_sb; 465 }; 466 467 struct bnx2x_agg_info { 468 /* 469 * First aggregation buffer is a data buffer, the following - are pages. 470 * We will preallocate the data buffer for each aggregation when 471 * we open the interface and will replace the BD at the consumer 472 * with this one when we receive the TPA_START CQE in order to 473 * keep the Rx BD ring consistent. 474 */ 475 struct sw_rx_bd first_buf; 476 u8 tpa_state; 477 #define BNX2X_TPA_START 1 478 #define BNX2X_TPA_STOP 2 479 #define BNX2X_TPA_ERROR 3 480 u8 placement_offset; 481 u16 parsing_flags; 482 u16 vlan_tag; 483 u16 len_on_bd; 484 u32 rxhash; 485 enum pkt_hash_types rxhash_type; 486 u16 gro_size; 487 u16 full_page; 488 }; 489 490 #define Q_STATS_OFFSET32(stat_name) \ 491 (offsetof(struct bnx2x_eth_q_stats, stat_name) / 4) 492 493 struct bnx2x_fp_txdata { 494 495 struct sw_tx_bd *tx_buf_ring; 496 497 union eth_tx_bd_types *tx_desc_ring; 498 dma_addr_t tx_desc_mapping; 499 500 u32 cid; 501 502 union db_prod tx_db; 503 504 u16 tx_pkt_prod; 505 u16 tx_pkt_cons; 506 u16 tx_bd_prod; 507 u16 tx_bd_cons; 508 509 unsigned long tx_pkt; 510 511 __le16 *tx_cons_sb; 512 513 int txq_index; 514 struct bnx2x_fastpath *parent_fp; 515 int tx_ring_size; 516 }; 517 518 enum bnx2x_tpa_mode_t { 519 TPA_MODE_LRO, 520 TPA_MODE_GRO 521 }; 522 523 struct bnx2x_fastpath { 524 struct bnx2x *bp; /* parent */ 525 526 struct napi_struct napi; 527 528 #ifdef CONFIG_NET_RX_BUSY_POLL 529 unsigned int state; 530 #define BNX2X_FP_STATE_IDLE 0 531 #define BNX2X_FP_STATE_NAPI (1 << 0) /* NAPI owns this FP */ 532 #define BNX2X_FP_STATE_POLL (1 << 1) /* poll owns this FP */ 533 #define BNX2X_FP_STATE_DISABLED (1 << 2) 534 #define BNX2X_FP_STATE_NAPI_YIELD (1 << 3) /* NAPI yielded this FP */ 535 #define BNX2X_FP_STATE_POLL_YIELD (1 << 4) /* poll yielded this FP */ 536 #define BNX2X_FP_OWNED (BNX2X_FP_STATE_NAPI | BNX2X_FP_STATE_POLL) 537 #define BNX2X_FP_YIELD (BNX2X_FP_STATE_NAPI_YIELD | BNX2X_FP_STATE_POLL_YIELD) 538 #define BNX2X_FP_LOCKED (BNX2X_FP_OWNED | BNX2X_FP_STATE_DISABLED) 539 #define BNX2X_FP_USER_PEND (BNX2X_FP_STATE_POLL | BNX2X_FP_STATE_POLL_YIELD) 540 /* protect state */ 541 spinlock_t lock; 542 #endif /* CONFIG_NET_RX_BUSY_POLL */ 543 544 union host_hc_status_block status_blk; 545 /* chip independent shortcuts into sb structure */ 546 __le16 *sb_index_values; 547 __le16 *sb_running_index; 548 /* chip independent shortcut into rx_prods_offset memory */ 549 u32 ustorm_rx_prods_offset; 550 551 u32 rx_buf_size; 552 u32 rx_frag_size; /* 0 if kmalloced(), or rx_buf_size + NET_SKB_PAD */ 553 dma_addr_t status_blk_mapping; 554 555 enum bnx2x_tpa_mode_t mode; 556 557 u8 max_cos; /* actual number of active tx coses */ 558 struct bnx2x_fp_txdata *txdata_ptr[BNX2X_MULTI_TX_COS]; 559 560 struct sw_rx_bd *rx_buf_ring; /* BDs mappings ring */ 561 struct sw_rx_page *rx_page_ring; /* SGE pages mappings ring */ 562 563 struct eth_rx_bd *rx_desc_ring; 564 dma_addr_t rx_desc_mapping; 565 566 union eth_rx_cqe *rx_comp_ring; 567 dma_addr_t rx_comp_mapping; 568 569 /* SGE ring */ 570 struct eth_rx_sge *rx_sge_ring; 571 dma_addr_t rx_sge_mapping; 572 573 u64 sge_mask[RX_SGE_MASK_LEN]; 574 575 u32 cid; 576 577 __le16 fp_hc_idx; 578 579 u8 index; /* number in fp array */ 580 u8 rx_queue; /* index for skb_record */ 581 u8 cl_id; /* eth client id */ 582 u8 cl_qzone_id; 583 u8 fw_sb_id; /* status block number in FW */ 584 u8 igu_sb_id; /* status block number in HW */ 585 586 u16 rx_bd_prod; 587 u16 rx_bd_cons; 588 u16 rx_comp_prod; 589 u16 rx_comp_cons; 590 u16 rx_sge_prod; 591 /* The last maximal completed SGE */ 592 u16 last_max_sge; 593 __le16 *rx_cons_sb; 594 unsigned long rx_pkt, 595 rx_calls; 596 597 /* TPA related */ 598 struct bnx2x_agg_info *tpa_info; 599 u8 disable_tpa; 600 #ifdef BNX2X_STOP_ON_ERROR 601 u64 tpa_queue_used; 602 #endif 603 /* The size is calculated using the following: 604 sizeof name field from netdev structure + 605 4 ('-Xx-' string) + 606 4 (for the digits and to make it DWORD aligned) */ 607 #define FP_NAME_SIZE (sizeof(((struct net_device *)0)->name) + 8) 608 char name[FP_NAME_SIZE]; 609 }; 610 611 #define bnx2x_fp(bp, nr, var) ((bp)->fp[(nr)].var) 612 #define bnx2x_sp_obj(bp, fp) ((bp)->sp_objs[(fp)->index]) 613 #define bnx2x_fp_stats(bp, fp) (&((bp)->fp_stats[(fp)->index])) 614 #define bnx2x_fp_qstats(bp, fp) (&((bp)->fp_stats[(fp)->index].eth_q_stats)) 615 616 #ifdef CONFIG_NET_RX_BUSY_POLL 617 static inline void bnx2x_fp_init_lock(struct bnx2x_fastpath *fp) 618 { 619 spin_lock_init(&fp->lock); 620 fp->state = BNX2X_FP_STATE_IDLE; 621 } 622 623 /* called from the device poll routine to get ownership of a FP */ 624 static inline bool bnx2x_fp_lock_napi(struct bnx2x_fastpath *fp) 625 { 626 bool rc = true; 627 628 spin_lock_bh(&fp->lock); 629 if (fp->state & BNX2X_FP_LOCKED) { 630 WARN_ON(fp->state & BNX2X_FP_STATE_NAPI); 631 fp->state |= BNX2X_FP_STATE_NAPI_YIELD; 632 rc = false; 633 } else { 634 /* we don't care if someone yielded */ 635 fp->state = BNX2X_FP_STATE_NAPI; 636 } 637 spin_unlock_bh(&fp->lock); 638 return rc; 639 } 640 641 /* returns true is someone tried to get the FP while napi had it */ 642 static inline bool bnx2x_fp_unlock_napi(struct bnx2x_fastpath *fp) 643 { 644 bool rc = false; 645 646 spin_lock_bh(&fp->lock); 647 WARN_ON(fp->state & 648 (BNX2X_FP_STATE_POLL | BNX2X_FP_STATE_NAPI_YIELD)); 649 650 if (fp->state & BNX2X_FP_STATE_POLL_YIELD) 651 rc = true; 652 653 /* state ==> idle, unless currently disabled */ 654 fp->state &= BNX2X_FP_STATE_DISABLED; 655 spin_unlock_bh(&fp->lock); 656 return rc; 657 } 658 659 /* called from bnx2x_low_latency_poll() */ 660 static inline bool bnx2x_fp_lock_poll(struct bnx2x_fastpath *fp) 661 { 662 bool rc = true; 663 664 spin_lock_bh(&fp->lock); 665 if ((fp->state & BNX2X_FP_LOCKED)) { 666 fp->state |= BNX2X_FP_STATE_POLL_YIELD; 667 rc = false; 668 } else { 669 /* preserve yield marks */ 670 fp->state |= BNX2X_FP_STATE_POLL; 671 } 672 spin_unlock_bh(&fp->lock); 673 return rc; 674 } 675 676 /* returns true if someone tried to get the FP while it was locked */ 677 static inline bool bnx2x_fp_unlock_poll(struct bnx2x_fastpath *fp) 678 { 679 bool rc = false; 680 681 spin_lock_bh(&fp->lock); 682 WARN_ON(fp->state & BNX2X_FP_STATE_NAPI); 683 684 if (fp->state & BNX2X_FP_STATE_POLL_YIELD) 685 rc = true; 686 687 /* state ==> idle, unless currently disabled */ 688 fp->state &= BNX2X_FP_STATE_DISABLED; 689 spin_unlock_bh(&fp->lock); 690 return rc; 691 } 692 693 /* true if a socket is polling, even if it did not get the lock */ 694 static inline bool bnx2x_fp_ll_polling(struct bnx2x_fastpath *fp) 695 { 696 WARN_ON(!(fp->state & BNX2X_FP_OWNED)); 697 return fp->state & BNX2X_FP_USER_PEND; 698 } 699 700 /* false if fp is currently owned */ 701 static inline bool bnx2x_fp_ll_disable(struct bnx2x_fastpath *fp) 702 { 703 int rc = true; 704 705 spin_lock_bh(&fp->lock); 706 if (fp->state & BNX2X_FP_OWNED) 707 rc = false; 708 fp->state |= BNX2X_FP_STATE_DISABLED; 709 spin_unlock_bh(&fp->lock); 710 711 return rc; 712 } 713 #else 714 static inline void bnx2x_fp_init_lock(struct bnx2x_fastpath *fp) 715 { 716 } 717 718 static inline bool bnx2x_fp_lock_napi(struct bnx2x_fastpath *fp) 719 { 720 return true; 721 } 722 723 static inline bool bnx2x_fp_unlock_napi(struct bnx2x_fastpath *fp) 724 { 725 return false; 726 } 727 728 static inline bool bnx2x_fp_lock_poll(struct bnx2x_fastpath *fp) 729 { 730 return false; 731 } 732 733 static inline bool bnx2x_fp_unlock_poll(struct bnx2x_fastpath *fp) 734 { 735 return false; 736 } 737 738 static inline bool bnx2x_fp_ll_polling(struct bnx2x_fastpath *fp) 739 { 740 return false; 741 } 742 static inline bool bnx2x_fp_ll_disable(struct bnx2x_fastpath *fp) 743 { 744 return true; 745 } 746 #endif /* CONFIG_NET_RX_BUSY_POLL */ 747 748 /* Use 2500 as a mini-jumbo MTU for FCoE */ 749 #define BNX2X_FCOE_MINI_JUMBO_MTU 2500 750 751 #define FCOE_IDX_OFFSET 0 752 753 #define FCOE_IDX(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) + \ 754 FCOE_IDX_OFFSET) 755 #define bnx2x_fcoe_fp(bp) (&bp->fp[FCOE_IDX(bp)]) 756 #define bnx2x_fcoe(bp, var) (bnx2x_fcoe_fp(bp)->var) 757 #define bnx2x_fcoe_inner_sp_obj(bp) (&bp->sp_objs[FCOE_IDX(bp)]) 758 #define bnx2x_fcoe_sp_obj(bp, var) (bnx2x_fcoe_inner_sp_obj(bp)->var) 759 #define bnx2x_fcoe_tx(bp, var) (bnx2x_fcoe_fp(bp)-> \ 760 txdata_ptr[FIRST_TX_COS_INDEX] \ 761 ->var) 762 763 #define IS_ETH_FP(fp) ((fp)->index < BNX2X_NUM_ETH_QUEUES((fp)->bp)) 764 #define IS_FCOE_FP(fp) ((fp)->index == FCOE_IDX((fp)->bp)) 765 #define IS_FCOE_IDX(idx) ((idx) == FCOE_IDX(bp)) 766 767 /* MC hsi */ 768 #define MAX_FETCH_BD 13 /* HW max BDs per packet */ 769 #define RX_COPY_THRESH 92 770 771 #define NUM_TX_RINGS 16 772 #define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types)) 773 #define NEXT_PAGE_TX_DESC_CNT 1 774 #define MAX_TX_DESC_CNT (TX_DESC_CNT - NEXT_PAGE_TX_DESC_CNT) 775 #define NUM_TX_BD (TX_DESC_CNT * NUM_TX_RINGS) 776 #define MAX_TX_BD (NUM_TX_BD - 1) 777 #define MAX_TX_AVAIL (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2) 778 #define NEXT_TX_IDX(x) ((((x) & MAX_TX_DESC_CNT) == \ 779 (MAX_TX_DESC_CNT - 1)) ? \ 780 (x) + 1 + NEXT_PAGE_TX_DESC_CNT : \ 781 (x) + 1) 782 #define TX_BD(x) ((x) & MAX_TX_BD) 783 #define TX_BD_POFF(x) ((x) & MAX_TX_DESC_CNT) 784 785 /* number of NEXT_PAGE descriptors may be required during placement */ 786 #define NEXT_CNT_PER_TX_PKT(bds) \ 787 (((bds) + MAX_TX_DESC_CNT - 1) / \ 788 MAX_TX_DESC_CNT * NEXT_PAGE_TX_DESC_CNT) 789 /* max BDs per tx packet w/o next_pages: 790 * START_BD - describes packed 791 * START_BD(splitted) - includes unpaged data segment for GSO 792 * PARSING_BD - for TSO and CSUM data 793 * PARSING_BD2 - for encapsulation data 794 * Frag BDs - describes pages for frags 795 */ 796 #define BDS_PER_TX_PKT 4 797 #define MAX_BDS_PER_TX_PKT (MAX_SKB_FRAGS + BDS_PER_TX_PKT) 798 /* max BDs per tx packet including next pages */ 799 #define MAX_DESC_PER_TX_PKT (MAX_BDS_PER_TX_PKT + \ 800 NEXT_CNT_PER_TX_PKT(MAX_BDS_PER_TX_PKT)) 801 802 /* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */ 803 #define NUM_RX_RINGS 8 804 #define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd)) 805 #define NEXT_PAGE_RX_DESC_CNT 2 806 #define MAX_RX_DESC_CNT (RX_DESC_CNT - NEXT_PAGE_RX_DESC_CNT) 807 #define RX_DESC_MASK (RX_DESC_CNT - 1) 808 #define NUM_RX_BD (RX_DESC_CNT * NUM_RX_RINGS) 809 #define MAX_RX_BD (NUM_RX_BD - 1) 810 #define MAX_RX_AVAIL (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2) 811 812 /* dropless fc calculations for BDs 813 * 814 * Number of BDs should as number of buffers in BRB: 815 * Low threshold takes into account NEXT_PAGE_RX_DESC_CNT 816 * "next" elements on each page 817 */ 818 #define NUM_BD_REQ BRB_SIZE(bp) 819 #define NUM_BD_PG_REQ ((NUM_BD_REQ + MAX_RX_DESC_CNT - 1) / \ 820 MAX_RX_DESC_CNT) 821 #define BD_TH_LO(bp) (NUM_BD_REQ + \ 822 NUM_BD_PG_REQ * NEXT_PAGE_RX_DESC_CNT + \ 823 FW_DROP_LEVEL(bp)) 824 #define BD_TH_HI(bp) (BD_TH_LO(bp) + DROPLESS_FC_HEADROOM) 825 826 #define MIN_RX_AVAIL ((bp)->dropless_fc ? BD_TH_HI(bp) + 128 : 128) 827 828 #define MIN_RX_SIZE_TPA_HW (CHIP_IS_E1(bp) ? \ 829 ETH_MIN_RX_CQES_WITH_TPA_E1 : \ 830 ETH_MIN_RX_CQES_WITH_TPA_E1H_E2) 831 #define MIN_RX_SIZE_NONTPA_HW ETH_MIN_RX_CQES_WITHOUT_TPA 832 #define MIN_RX_SIZE_TPA (max_t(u32, MIN_RX_SIZE_TPA_HW, MIN_RX_AVAIL)) 833 #define MIN_RX_SIZE_NONTPA (max_t(u32, MIN_RX_SIZE_NONTPA_HW,\ 834 MIN_RX_AVAIL)) 835 836 #define NEXT_RX_IDX(x) ((((x) & RX_DESC_MASK) == \ 837 (MAX_RX_DESC_CNT - 1)) ? \ 838 (x) + 1 + NEXT_PAGE_RX_DESC_CNT : \ 839 (x) + 1) 840 #define RX_BD(x) ((x) & MAX_RX_BD) 841 842 /* 843 * As long as CQE is X times bigger than BD entry we have to allocate X times 844 * more pages for CQ ring in order to keep it balanced with BD ring 845 */ 846 #define CQE_BD_REL (sizeof(union eth_rx_cqe) / sizeof(struct eth_rx_bd)) 847 #define NUM_RCQ_RINGS (NUM_RX_RINGS * CQE_BD_REL) 848 #define RCQ_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe)) 849 #define NEXT_PAGE_RCQ_DESC_CNT 1 850 #define MAX_RCQ_DESC_CNT (RCQ_DESC_CNT - NEXT_PAGE_RCQ_DESC_CNT) 851 #define NUM_RCQ_BD (RCQ_DESC_CNT * NUM_RCQ_RINGS) 852 #define MAX_RCQ_BD (NUM_RCQ_BD - 1) 853 #define MAX_RCQ_AVAIL (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2) 854 #define NEXT_RCQ_IDX(x) ((((x) & MAX_RCQ_DESC_CNT) == \ 855 (MAX_RCQ_DESC_CNT - 1)) ? \ 856 (x) + 1 + NEXT_PAGE_RCQ_DESC_CNT : \ 857 (x) + 1) 858 #define RCQ_BD(x) ((x) & MAX_RCQ_BD) 859 860 /* dropless fc calculations for RCQs 861 * 862 * Number of RCQs should be as number of buffers in BRB: 863 * Low threshold takes into account NEXT_PAGE_RCQ_DESC_CNT 864 * "next" elements on each page 865 */ 866 #define NUM_RCQ_REQ BRB_SIZE(bp) 867 #define NUM_RCQ_PG_REQ ((NUM_BD_REQ + MAX_RCQ_DESC_CNT - 1) / \ 868 MAX_RCQ_DESC_CNT) 869 #define RCQ_TH_LO(bp) (NUM_RCQ_REQ + \ 870 NUM_RCQ_PG_REQ * NEXT_PAGE_RCQ_DESC_CNT + \ 871 FW_DROP_LEVEL(bp)) 872 #define RCQ_TH_HI(bp) (RCQ_TH_LO(bp) + DROPLESS_FC_HEADROOM) 873 874 /* This is needed for determining of last_max */ 875 #define SUB_S16(a, b) (s16)((s16)(a) - (s16)(b)) 876 #define SUB_S32(a, b) (s32)((s32)(a) - (s32)(b)) 877 878 #define BNX2X_SWCID_SHIFT 17 879 #define BNX2X_SWCID_MASK ((0x1 << BNX2X_SWCID_SHIFT) - 1) 880 881 /* used on a CID received from the HW */ 882 #define SW_CID(x) (le32_to_cpu(x) & BNX2X_SWCID_MASK) 883 #define CQE_CMD(x) (le32_to_cpu(x) >> \ 884 COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT) 885 886 #define BD_UNMAP_ADDR(bd) HILO_U64(le32_to_cpu((bd)->addr_hi), \ 887 le32_to_cpu((bd)->addr_lo)) 888 #define BD_UNMAP_LEN(bd) (le16_to_cpu((bd)->nbytes)) 889 890 #define BNX2X_DB_MIN_SHIFT 3 /* 8 bytes */ 891 #define BNX2X_DB_SHIFT 3 /* 8 bytes*/ 892 #if (BNX2X_DB_SHIFT < BNX2X_DB_MIN_SHIFT) 893 #error "Min DB doorbell stride is 8" 894 #endif 895 #define DOORBELL(bp, cid, val) \ 896 do { \ 897 writel((u32)(val), bp->doorbells + (bp->db_size * (cid))); \ 898 } while (0) 899 900 /* TX CSUM helpers */ 901 #define SKB_CS_OFF(skb) (offsetof(struct tcphdr, check) - \ 902 skb->csum_offset) 903 #define SKB_CS(skb) (*(u16 *)(skb_transport_header(skb) + \ 904 skb->csum_offset)) 905 906 #define pbd_tcp_flags(tcp_hdr) (ntohl(tcp_flag_word(tcp_hdr))>>16 & 0xff) 907 908 #define XMIT_PLAIN 0 909 #define XMIT_CSUM_V4 (1 << 0) 910 #define XMIT_CSUM_V6 (1 << 1) 911 #define XMIT_CSUM_TCP (1 << 2) 912 #define XMIT_GSO_V4 (1 << 3) 913 #define XMIT_GSO_V6 (1 << 4) 914 #define XMIT_CSUM_ENC_V4 (1 << 5) 915 #define XMIT_CSUM_ENC_V6 (1 << 6) 916 #define XMIT_GSO_ENC_V4 (1 << 7) 917 #define XMIT_GSO_ENC_V6 (1 << 8) 918 919 #define XMIT_CSUM_ENC (XMIT_CSUM_ENC_V4 | XMIT_CSUM_ENC_V6) 920 #define XMIT_GSO_ENC (XMIT_GSO_ENC_V4 | XMIT_GSO_ENC_V6) 921 922 #define XMIT_CSUM (XMIT_CSUM_V4 | XMIT_CSUM_V6 | XMIT_CSUM_ENC) 923 #define XMIT_GSO (XMIT_GSO_V4 | XMIT_GSO_V6 | XMIT_GSO_ENC) 924 925 /* stuff added to make the code fit 80Col */ 926 #define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE) 927 #define CQE_TYPE_START(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_START_AGG) 928 #define CQE_TYPE_STOP(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_STOP_AGG) 929 #define CQE_TYPE_SLOW(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_RAMROD) 930 #define CQE_TYPE_FAST(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_FASTPATH) 931 932 #define ETH_RX_ERROR_FALGS ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG 933 934 #define BNX2X_PRS_FLAG_OVERETH_IPV4(flags) \ 935 (((le16_to_cpu(flags) & \ 936 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) >> \ 937 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT) \ 938 == PRS_FLAG_OVERETH_IPV4) 939 #define BNX2X_RX_SUM_FIX(cqe) \ 940 BNX2X_PRS_FLAG_OVERETH_IPV4(cqe->fast_path_cqe.pars_flags.flags) 941 942 #define FP_USB_FUNC_OFF \ 943 offsetof(struct cstorm_status_block_u, func) 944 #define FP_CSB_FUNC_OFF \ 945 offsetof(struct cstorm_status_block_c, func) 946 947 #define HC_INDEX_ETH_RX_CQ_CONS 1 948 949 #define HC_INDEX_OOO_TX_CQ_CONS 4 950 951 #define HC_INDEX_ETH_TX_CQ_CONS_COS0 5 952 953 #define HC_INDEX_ETH_TX_CQ_CONS_COS1 6 954 955 #define HC_INDEX_ETH_TX_CQ_CONS_COS2 7 956 957 #define HC_INDEX_ETH_FIRST_TX_CQ_CONS HC_INDEX_ETH_TX_CQ_CONS_COS0 958 959 #define BNX2X_RX_SB_INDEX \ 960 (&fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS]) 961 962 #define BNX2X_TX_SB_INDEX_BASE BNX2X_TX_SB_INDEX_COS0 963 964 #define BNX2X_TX_SB_INDEX_COS0 \ 965 (&fp->sb_index_values[HC_INDEX_ETH_TX_CQ_CONS_COS0]) 966 967 /* end of fast path */ 968 969 /* common */ 970 971 struct bnx2x_common { 972 973 u32 chip_id; 974 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */ 975 #define CHIP_ID(bp) (bp->common.chip_id & 0xfffffff0) 976 977 #define CHIP_NUM(bp) (bp->common.chip_id >> 16) 978 #define CHIP_NUM_57710 0x164e 979 #define CHIP_NUM_57711 0x164f 980 #define CHIP_NUM_57711E 0x1650 981 #define CHIP_NUM_57712 0x1662 982 #define CHIP_NUM_57712_MF 0x1663 983 #define CHIP_NUM_57712_VF 0x166f 984 #define CHIP_NUM_57713 0x1651 985 #define CHIP_NUM_57713E 0x1652 986 #define CHIP_NUM_57800 0x168a 987 #define CHIP_NUM_57800_MF 0x16a5 988 #define CHIP_NUM_57800_VF 0x16a9 989 #define CHIP_NUM_57810 0x168e 990 #define CHIP_NUM_57810_MF 0x16ae 991 #define CHIP_NUM_57810_VF 0x16af 992 #define CHIP_NUM_57811 0x163d 993 #define CHIP_NUM_57811_MF 0x163e 994 #define CHIP_NUM_57811_VF 0x163f 995 #define CHIP_NUM_57840_OBSOLETE 0x168d 996 #define CHIP_NUM_57840_MF_OBSOLETE 0x16ab 997 #define CHIP_NUM_57840_4_10 0x16a1 998 #define CHIP_NUM_57840_2_20 0x16a2 999 #define CHIP_NUM_57840_MF 0x16a4 1000 #define CHIP_NUM_57840_VF 0x16ad 1001 #define CHIP_IS_E1(bp) (CHIP_NUM(bp) == CHIP_NUM_57710) 1002 #define CHIP_IS_57711(bp) (CHIP_NUM(bp) == CHIP_NUM_57711) 1003 #define CHIP_IS_57711E(bp) (CHIP_NUM(bp) == CHIP_NUM_57711E) 1004 #define CHIP_IS_57712(bp) (CHIP_NUM(bp) == CHIP_NUM_57712) 1005 #define CHIP_IS_57712_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57712_VF) 1006 #define CHIP_IS_57712_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57712_MF) 1007 #define CHIP_IS_57800(bp) (CHIP_NUM(bp) == CHIP_NUM_57800) 1008 #define CHIP_IS_57800_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57800_MF) 1009 #define CHIP_IS_57800_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57800_VF) 1010 #define CHIP_IS_57810(bp) (CHIP_NUM(bp) == CHIP_NUM_57810) 1011 #define CHIP_IS_57810_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57810_MF) 1012 #define CHIP_IS_57810_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57810_VF) 1013 #define CHIP_IS_57811(bp) (CHIP_NUM(bp) == CHIP_NUM_57811) 1014 #define CHIP_IS_57811_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57811_MF) 1015 #define CHIP_IS_57811_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57811_VF) 1016 #define CHIP_IS_57840(bp) \ 1017 ((CHIP_NUM(bp) == CHIP_NUM_57840_4_10) || \ 1018 (CHIP_NUM(bp) == CHIP_NUM_57840_2_20) || \ 1019 (CHIP_NUM(bp) == CHIP_NUM_57840_OBSOLETE)) 1020 #define CHIP_IS_57840_MF(bp) ((CHIP_NUM(bp) == CHIP_NUM_57840_MF) || \ 1021 (CHIP_NUM(bp) == CHIP_NUM_57840_MF_OBSOLETE)) 1022 #define CHIP_IS_57840_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57840_VF) 1023 #define CHIP_IS_E1H(bp) (CHIP_IS_57711(bp) || \ 1024 CHIP_IS_57711E(bp)) 1025 #define CHIP_IS_57811xx(bp) (CHIP_IS_57811(bp) || \ 1026 CHIP_IS_57811_MF(bp) || \ 1027 CHIP_IS_57811_VF(bp)) 1028 #define CHIP_IS_E2(bp) (CHIP_IS_57712(bp) || \ 1029 CHIP_IS_57712_MF(bp) || \ 1030 CHIP_IS_57712_VF(bp)) 1031 #define CHIP_IS_E3(bp) (CHIP_IS_57800(bp) || \ 1032 CHIP_IS_57800_MF(bp) || \ 1033 CHIP_IS_57800_VF(bp) || \ 1034 CHIP_IS_57810(bp) || \ 1035 CHIP_IS_57810_MF(bp) || \ 1036 CHIP_IS_57810_VF(bp) || \ 1037 CHIP_IS_57811xx(bp) || \ 1038 CHIP_IS_57840(bp) || \ 1039 CHIP_IS_57840_MF(bp) || \ 1040 CHIP_IS_57840_VF(bp)) 1041 #define CHIP_IS_E1x(bp) (CHIP_IS_E1((bp)) || CHIP_IS_E1H((bp))) 1042 #define USES_WARPCORE(bp) (CHIP_IS_E3(bp)) 1043 #define IS_E1H_OFFSET (!CHIP_IS_E1(bp)) 1044 1045 #define CHIP_REV_SHIFT 12 1046 #define CHIP_REV_MASK (0xF << CHIP_REV_SHIFT) 1047 #define CHIP_REV_VAL(bp) (bp->common.chip_id & CHIP_REV_MASK) 1048 #define CHIP_REV_Ax (0x0 << CHIP_REV_SHIFT) 1049 #define CHIP_REV_Bx (0x1 << CHIP_REV_SHIFT) 1050 /* assume maximum 5 revisions */ 1051 #define CHIP_REV_IS_SLOW(bp) (CHIP_REV_VAL(bp) > 0x00005000) 1052 /* Emul versions are A=>0xe, B=>0xc, C=>0xa, D=>8, E=>6 */ 1053 #define CHIP_REV_IS_EMUL(bp) ((CHIP_REV_IS_SLOW(bp)) && \ 1054 !(CHIP_REV_VAL(bp) & 0x00001000)) 1055 /* FPGA versions are A=>0xf, B=>0xd, C=>0xb, D=>9, E=>7 */ 1056 #define CHIP_REV_IS_FPGA(bp) ((CHIP_REV_IS_SLOW(bp)) && \ 1057 (CHIP_REV_VAL(bp) & 0x00001000)) 1058 1059 #define CHIP_TIME(bp) ((CHIP_REV_IS_EMUL(bp)) ? 2000 : \ 1060 ((CHIP_REV_IS_FPGA(bp)) ? 200 : 1)) 1061 1062 #define CHIP_METAL(bp) (bp->common.chip_id & 0x00000ff0) 1063 #define CHIP_BOND_ID(bp) (bp->common.chip_id & 0x0000000f) 1064 #define CHIP_REV_SIM(bp) (((CHIP_REV_MASK - CHIP_REV_VAL(bp)) >>\ 1065 (CHIP_REV_SHIFT + 1)) \ 1066 << CHIP_REV_SHIFT) 1067 #define CHIP_REV(bp) (CHIP_REV_IS_SLOW(bp) ? \ 1068 CHIP_REV_SIM(bp) :\ 1069 CHIP_REV_VAL(bp)) 1070 #define CHIP_IS_E3B0(bp) (CHIP_IS_E3(bp) && \ 1071 (CHIP_REV(bp) == CHIP_REV_Bx)) 1072 #define CHIP_IS_E3A0(bp) (CHIP_IS_E3(bp) && \ 1073 (CHIP_REV(bp) == CHIP_REV_Ax)) 1074 /* This define is used in two main places: 1075 * 1. In the early stages of nic_load, to know if to configure Parser / Searcher 1076 * to nic-only mode or to offload mode. Offload mode is configured if either the 1077 * chip is E1x (where MIC_MODE register is not applicable), or if cnic already 1078 * registered for this port (which means that the user wants storage services). 1079 * 2. During cnic-related load, to know if offload mode is already configured in 1080 * the HW or needs to be configured. 1081 * Since the transition from nic-mode to offload-mode in HW causes traffic 1082 * corruption, nic-mode is configured only in ports on which storage services 1083 * where never requested. 1084 */ 1085 #define CONFIGURE_NIC_MODE(bp) (!CHIP_IS_E1x(bp) && !CNIC_ENABLED(bp)) 1086 1087 int flash_size; 1088 #define BNX2X_NVRAM_1MB_SIZE 0x20000 /* 1M bit in bytes */ 1089 #define BNX2X_NVRAM_TIMEOUT_COUNT 30000 1090 #define BNX2X_NVRAM_PAGE_SIZE 256 1091 1092 u32 shmem_base; 1093 u32 shmem2_base; 1094 u32 mf_cfg_base; 1095 u32 mf2_cfg_base; 1096 1097 u32 hw_config; 1098 1099 u32 bc_ver; 1100 1101 u8 int_block; 1102 #define INT_BLOCK_HC 0 1103 #define INT_BLOCK_IGU 1 1104 #define INT_BLOCK_MODE_NORMAL 0 1105 #define INT_BLOCK_MODE_BW_COMP 2 1106 #define CHIP_INT_MODE_IS_NBC(bp) \ 1107 (!CHIP_IS_E1x(bp) && \ 1108 !((bp)->common.int_block & INT_BLOCK_MODE_BW_COMP)) 1109 #define CHIP_INT_MODE_IS_BC(bp) (!CHIP_INT_MODE_IS_NBC(bp)) 1110 1111 u8 chip_port_mode; 1112 #define CHIP_4_PORT_MODE 0x0 1113 #define CHIP_2_PORT_MODE 0x1 1114 #define CHIP_PORT_MODE_NONE 0x2 1115 #define CHIP_MODE(bp) (bp->common.chip_port_mode) 1116 #define CHIP_MODE_IS_4_PORT(bp) (CHIP_MODE(bp) == CHIP_4_PORT_MODE) 1117 1118 u32 boot_mode; 1119 }; 1120 1121 /* IGU MSIX STATISTICS on 57712: 64 for VFs; 4 for PFs; 4 for Attentions */ 1122 #define BNX2X_IGU_STAS_MSG_VF_CNT 64 1123 #define BNX2X_IGU_STAS_MSG_PF_CNT 4 1124 1125 #define MAX_IGU_ATTN_ACK_TO 100 1126 /* end of common */ 1127 1128 /* port */ 1129 1130 struct bnx2x_port { 1131 u32 pmf; 1132 1133 u32 link_config[LINK_CONFIG_SIZE]; 1134 1135 u32 supported[LINK_CONFIG_SIZE]; 1136 /* link settings - missing defines */ 1137 #define SUPPORTED_2500baseX_Full (1 << 15) 1138 1139 u32 advertising[LINK_CONFIG_SIZE]; 1140 /* link settings - missing defines */ 1141 #define ADVERTISED_2500baseX_Full (1 << 15) 1142 1143 u32 phy_addr; 1144 1145 /* used to synchronize phy accesses */ 1146 struct mutex phy_mutex; 1147 1148 u32 port_stx; 1149 1150 struct nig_stats old_nig_stats; 1151 }; 1152 1153 /* end of port */ 1154 1155 #define STATS_OFFSET32(stat_name) \ 1156 (offsetof(struct bnx2x_eth_stats, stat_name) / 4) 1157 1158 /* slow path */ 1159 #define BNX2X_MAX_NUM_OF_VFS 64 1160 #define BNX2X_VF_CID_WND 4 /* log num of queues per VF. HW config. */ 1161 #define BNX2X_CIDS_PER_VF (1 << BNX2X_VF_CID_WND) 1162 1163 /* We need to reserve doorbell addresses for all VF and queue combinations */ 1164 #define BNX2X_VF_CIDS (BNX2X_MAX_NUM_OF_VFS * BNX2X_CIDS_PER_VF) 1165 1166 /* The doorbell is configured to have the same number of CIDs for PFs and for 1167 * VFs. For this reason the PF CID zone is as large as the VF zone. 1168 */ 1169 #define BNX2X_FIRST_VF_CID BNX2X_VF_CIDS 1170 #define BNX2X_MAX_NUM_VF_QUEUES 64 1171 #define BNX2X_VF_ID_INVALID 0xFF 1172 1173 /* the number of VF CIDS multiplied by the amount of bytes reserved for each 1174 * cid must not exceed the size of the VF doorbell 1175 */ 1176 #define BNX2X_VF_BAR_SIZE 512 1177 #if (BNX2X_VF_BAR_SIZE < BNX2X_CIDS_PER_VF * (1 << BNX2X_DB_SHIFT)) 1178 #error "VF doorbell bar size is 512" 1179 #endif 1180 1181 /* 1182 * The total number of L2 queues, MSIX vectors and HW contexts (CIDs) is 1183 * control by the number of fast-path status blocks supported by the 1184 * device (HW/FW). Each fast-path status block (FP-SB) aka non-default 1185 * status block represents an independent interrupts context that can 1186 * serve a regular L2 networking queue. However special L2 queues such 1187 * as the FCoE queue do not require a FP-SB and other components like 1188 * the CNIC may consume FP-SB reducing the number of possible L2 queues 1189 * 1190 * If the maximum number of FP-SB available is X then: 1191 * a. If CNIC is supported it consumes 1 FP-SB thus the max number of 1192 * regular L2 queues is Y=X-1 1193 * b. In MF mode the actual number of L2 queues is Y= (X-1/MF_factor) 1194 * c. If the FCoE L2 queue is supported the actual number of L2 queues 1195 * is Y+1 1196 * d. The number of irqs (MSIX vectors) is either Y+1 (one extra for 1197 * slow-path interrupts) or Y+2 if CNIC is supported (one additional 1198 * FP interrupt context for the CNIC). 1199 * e. The number of HW context (CID count) is always X or X+1 if FCoE 1200 * L2 queue is supported. The cid for the FCoE L2 queue is always X. 1201 */ 1202 1203 /* fast-path interrupt contexts E1x */ 1204 #define FP_SB_MAX_E1x 16 1205 /* fast-path interrupt contexts E2 */ 1206 #define FP_SB_MAX_E2 HC_SB_MAX_SB_E2 1207 1208 union cdu_context { 1209 struct eth_context eth; 1210 char pad[1024]; 1211 }; 1212 1213 /* CDU host DB constants */ 1214 #define CDU_ILT_PAGE_SZ_HW 2 1215 #define CDU_ILT_PAGE_SZ (8192 << CDU_ILT_PAGE_SZ_HW) /* 32K */ 1216 #define ILT_PAGE_CIDS (CDU_ILT_PAGE_SZ / sizeof(union cdu_context)) 1217 1218 #define CNIC_ISCSI_CID_MAX 256 1219 #define CNIC_FCOE_CID_MAX 2048 1220 #define CNIC_CID_MAX (CNIC_ISCSI_CID_MAX + CNIC_FCOE_CID_MAX) 1221 #define CNIC_ILT_LINES DIV_ROUND_UP(CNIC_CID_MAX, ILT_PAGE_CIDS) 1222 1223 #define QM_ILT_PAGE_SZ_HW 0 1224 #define QM_ILT_PAGE_SZ (4096 << QM_ILT_PAGE_SZ_HW) /* 4K */ 1225 #define QM_CID_ROUND 1024 1226 1227 /* TM (timers) host DB constants */ 1228 #define TM_ILT_PAGE_SZ_HW 0 1229 #define TM_ILT_PAGE_SZ (4096 << TM_ILT_PAGE_SZ_HW) /* 4K */ 1230 #define TM_CONN_NUM (BNX2X_FIRST_VF_CID + \ 1231 BNX2X_VF_CIDS + \ 1232 CNIC_ISCSI_CID_MAX) 1233 #define TM_ILT_SZ (8 * TM_CONN_NUM) 1234 #define TM_ILT_LINES DIV_ROUND_UP(TM_ILT_SZ, TM_ILT_PAGE_SZ) 1235 1236 /* SRC (Searcher) host DB constants */ 1237 #define SRC_ILT_PAGE_SZ_HW 0 1238 #define SRC_ILT_PAGE_SZ (4096 << SRC_ILT_PAGE_SZ_HW) /* 4K */ 1239 #define SRC_HASH_BITS 10 1240 #define SRC_CONN_NUM (1 << SRC_HASH_BITS) /* 1024 */ 1241 #define SRC_ILT_SZ (sizeof(struct src_ent) * SRC_CONN_NUM) 1242 #define SRC_T2_SZ SRC_ILT_SZ 1243 #define SRC_ILT_LINES DIV_ROUND_UP(SRC_ILT_SZ, SRC_ILT_PAGE_SZ) 1244 1245 #define MAX_DMAE_C 8 1246 1247 /* DMA memory not used in fastpath */ 1248 struct bnx2x_slowpath { 1249 union { 1250 struct mac_configuration_cmd e1x; 1251 struct eth_classify_rules_ramrod_data e2; 1252 } mac_rdata; 1253 1254 union { 1255 struct tstorm_eth_mac_filter_config e1x; 1256 struct eth_filter_rules_ramrod_data e2; 1257 } rx_mode_rdata; 1258 1259 union { 1260 struct mac_configuration_cmd e1; 1261 struct eth_multicast_rules_ramrod_data e2; 1262 } mcast_rdata; 1263 1264 struct eth_rss_update_ramrod_data rss_rdata; 1265 1266 /* Queue State related ramrods are always sent under rtnl_lock */ 1267 union { 1268 struct client_init_ramrod_data init_data; 1269 struct client_update_ramrod_data update_data; 1270 struct tpa_update_ramrod_data tpa_data; 1271 } q_rdata; 1272 1273 union { 1274 struct function_start_data func_start; 1275 /* pfc configuration for DCBX ramrod */ 1276 struct flow_control_configuration pfc_config; 1277 } func_rdata; 1278 1279 /* afex ramrod can not be a part of func_rdata union because these 1280 * events might arrive in parallel to other events from func_rdata. 1281 * Therefore, if they would have been defined in the same union, 1282 * data can get corrupted. 1283 */ 1284 union { 1285 struct afex_vif_list_ramrod_data viflist_data; 1286 struct function_update_data func_update; 1287 } func_afex_rdata; 1288 1289 /* used by dmae command executer */ 1290 struct dmae_command dmae[MAX_DMAE_C]; 1291 1292 u32 stats_comp; 1293 union mac_stats mac_stats; 1294 struct nig_stats nig_stats; 1295 struct host_port_stats port_stats; 1296 struct host_func_stats func_stats; 1297 1298 u32 wb_comp; 1299 u32 wb_data[4]; 1300 1301 union drv_info_to_mcp drv_info_to_mcp; 1302 }; 1303 1304 #define bnx2x_sp(bp, var) (&bp->slowpath->var) 1305 #define bnx2x_sp_mapping(bp, var) \ 1306 (bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var)) 1307 1308 /* attn group wiring */ 1309 #define MAX_DYNAMIC_ATTN_GRPS 8 1310 1311 struct attn_route { 1312 u32 sig[5]; 1313 }; 1314 1315 struct iro { 1316 u32 base; 1317 u16 m1; 1318 u16 m2; 1319 u16 m3; 1320 u16 size; 1321 }; 1322 1323 struct hw_context { 1324 union cdu_context *vcxt; 1325 dma_addr_t cxt_mapping; 1326 size_t size; 1327 }; 1328 1329 /* forward */ 1330 struct bnx2x_ilt; 1331 1332 struct bnx2x_vfdb; 1333 1334 enum bnx2x_recovery_state { 1335 BNX2X_RECOVERY_DONE, 1336 BNX2X_RECOVERY_INIT, 1337 BNX2X_RECOVERY_WAIT, 1338 BNX2X_RECOVERY_FAILED, 1339 BNX2X_RECOVERY_NIC_LOADING 1340 }; 1341 1342 /* 1343 * Event queue (EQ or event ring) MC hsi 1344 * NUM_EQ_PAGES and EQ_DESC_CNT_PAGE must be power of 2 1345 */ 1346 #define NUM_EQ_PAGES 1 1347 #define EQ_DESC_CNT_PAGE (BCM_PAGE_SIZE / sizeof(union event_ring_elem)) 1348 #define EQ_DESC_MAX_PAGE (EQ_DESC_CNT_PAGE - 1) 1349 #define NUM_EQ_DESC (EQ_DESC_CNT_PAGE * NUM_EQ_PAGES) 1350 #define EQ_DESC_MASK (NUM_EQ_DESC - 1) 1351 #define MAX_EQ_AVAIL (EQ_DESC_MAX_PAGE * NUM_EQ_PAGES - 2) 1352 1353 /* depends on EQ_DESC_CNT_PAGE being a power of 2 */ 1354 #define NEXT_EQ_IDX(x) ((((x) & EQ_DESC_MAX_PAGE) == \ 1355 (EQ_DESC_MAX_PAGE - 1)) ? (x) + 2 : (x) + 1) 1356 1357 /* depends on the above and on NUM_EQ_PAGES being a power of 2 */ 1358 #define EQ_DESC(x) ((x) & EQ_DESC_MASK) 1359 1360 #define BNX2X_EQ_INDEX \ 1361 (&bp->def_status_blk->sp_sb.\ 1362 index_values[HC_SP_INDEX_EQ_CONS]) 1363 1364 /* This is a data that will be used to create a link report message. 1365 * We will keep the data used for the last link report in order 1366 * to prevent reporting the same link parameters twice. 1367 */ 1368 struct bnx2x_link_report_data { 1369 u16 line_speed; /* Effective line speed */ 1370 unsigned long link_report_flags;/* BNX2X_LINK_REPORT_XXX flags */ 1371 }; 1372 1373 enum { 1374 BNX2X_LINK_REPORT_FD, /* Full DUPLEX */ 1375 BNX2X_LINK_REPORT_LINK_DOWN, 1376 BNX2X_LINK_REPORT_RX_FC_ON, 1377 BNX2X_LINK_REPORT_TX_FC_ON, 1378 }; 1379 1380 enum { 1381 BNX2X_PORT_QUERY_IDX, 1382 BNX2X_PF_QUERY_IDX, 1383 BNX2X_FCOE_QUERY_IDX, 1384 BNX2X_FIRST_QUEUE_QUERY_IDX, 1385 }; 1386 1387 struct bnx2x_fw_stats_req { 1388 struct stats_query_header hdr; 1389 struct stats_query_entry query[FP_SB_MAX_E1x+ 1390 BNX2X_FIRST_QUEUE_QUERY_IDX]; 1391 }; 1392 1393 struct bnx2x_fw_stats_data { 1394 struct stats_counter storm_counters; 1395 struct per_port_stats port; 1396 struct per_pf_stats pf; 1397 struct fcoe_statistics_params fcoe; 1398 struct per_queue_stats queue_stats[1]; 1399 }; 1400 1401 /* Public slow path states */ 1402 enum sp_rtnl_flag { 1403 BNX2X_SP_RTNL_SETUP_TC, 1404 BNX2X_SP_RTNL_TX_TIMEOUT, 1405 BNX2X_SP_RTNL_FAN_FAILURE, 1406 BNX2X_SP_RTNL_AFEX_F_UPDATE, 1407 BNX2X_SP_RTNL_ENABLE_SRIOV, 1408 BNX2X_SP_RTNL_VFPF_MCAST, 1409 BNX2X_SP_RTNL_VFPF_CHANNEL_DOWN, 1410 BNX2X_SP_RTNL_RX_MODE, 1411 BNX2X_SP_RTNL_HYPERVISOR_VLAN, 1412 BNX2X_SP_RTNL_TX_STOP, 1413 BNX2X_SP_RTNL_GET_DRV_VERSION, 1414 }; 1415 1416 enum bnx2x_iov_flag { 1417 BNX2X_IOV_HANDLE_VF_MSG, 1418 BNX2X_IOV_HANDLE_FLR, 1419 }; 1420 1421 struct bnx2x_prev_path_list { 1422 struct list_head list; 1423 u8 bus; 1424 u8 slot; 1425 u8 path; 1426 u8 aer; 1427 u8 undi; 1428 }; 1429 1430 struct bnx2x_sp_objs { 1431 /* MACs object */ 1432 struct bnx2x_vlan_mac_obj mac_obj; 1433 1434 /* Queue State object */ 1435 struct bnx2x_queue_sp_obj q_obj; 1436 }; 1437 1438 struct bnx2x_fp_stats { 1439 struct tstorm_per_queue_stats old_tclient; 1440 struct ustorm_per_queue_stats old_uclient; 1441 struct xstorm_per_queue_stats old_xclient; 1442 struct bnx2x_eth_q_stats eth_q_stats; 1443 struct bnx2x_eth_q_stats_old eth_q_stats_old; 1444 }; 1445 1446 struct bnx2x { 1447 /* Fields used in the tx and intr/napi performance paths 1448 * are grouped together in the beginning of the structure 1449 */ 1450 struct bnx2x_fastpath *fp; 1451 struct bnx2x_sp_objs *sp_objs; 1452 struct bnx2x_fp_stats *fp_stats; 1453 struct bnx2x_fp_txdata *bnx2x_txq; 1454 void __iomem *regview; 1455 void __iomem *doorbells; 1456 u16 db_size; 1457 1458 u8 pf_num; /* absolute PF number */ 1459 u8 pfid; /* per-path PF number */ 1460 int base_fw_ndsb; /**/ 1461 #define BP_PATH(bp) (CHIP_IS_E1x(bp) ? 0 : (bp->pf_num & 1)) 1462 #define BP_PORT(bp) (bp->pfid & 1) 1463 #define BP_FUNC(bp) (bp->pfid) 1464 #define BP_ABS_FUNC(bp) (bp->pf_num) 1465 #define BP_VN(bp) ((bp)->pfid >> 1) 1466 #define BP_MAX_VN_NUM(bp) (CHIP_MODE_IS_4_PORT(bp) ? 2 : 4) 1467 #define BP_L_ID(bp) (BP_VN(bp) << 2) 1468 #define BP_FW_MB_IDX_VN(bp, vn) (BP_PORT(bp) +\ 1469 (vn) * ((CHIP_IS_E1x(bp) || (CHIP_MODE_IS_4_PORT(bp))) ? 2 : 1)) 1470 #define BP_FW_MB_IDX(bp) BP_FW_MB_IDX_VN(bp, BP_VN(bp)) 1471 1472 #ifdef CONFIG_BNX2X_SRIOV 1473 /* protects vf2pf mailbox from simultaneous access */ 1474 struct mutex vf2pf_mutex; 1475 /* vf pf channel mailbox contains request and response buffers */ 1476 struct bnx2x_vf_mbx_msg *vf2pf_mbox; 1477 dma_addr_t vf2pf_mbox_mapping; 1478 1479 /* we set aside a copy of the acquire response */ 1480 struct pfvf_acquire_resp_tlv acquire_resp; 1481 1482 /* bulletin board for messages from pf to vf */ 1483 union pf_vf_bulletin *pf2vf_bulletin; 1484 dma_addr_t pf2vf_bulletin_mapping; 1485 1486 struct pf_vf_bulletin_content old_bulletin; 1487 1488 u16 requested_nr_virtfn; 1489 #endif /* CONFIG_BNX2X_SRIOV */ 1490 1491 struct net_device *dev; 1492 struct pci_dev *pdev; 1493 1494 const struct iro *iro_arr; 1495 #define IRO (bp->iro_arr) 1496 1497 enum bnx2x_recovery_state recovery_state; 1498 int is_leader; 1499 struct msix_entry *msix_table; 1500 1501 int tx_ring_size; 1502 1503 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */ 1504 #define ETH_OVREHEAD (ETH_HLEN + 8 + 8) 1505 #define ETH_MIN_PACKET_SIZE 60 1506 #define ETH_MAX_PACKET_SIZE 1500 1507 #define ETH_MAX_JUMBO_PACKET_SIZE 9600 1508 /* TCP with Timestamp Option (32) + IPv6 (40) */ 1509 #define ETH_MAX_TPA_HEADER_SIZE 72 1510 1511 /* Max supported alignment is 256 (8 shift) */ 1512 #define BNX2X_RX_ALIGN_SHIFT min(8, L1_CACHE_SHIFT) 1513 1514 /* FW uses 2 Cache lines Alignment for start packet and size 1515 * 1516 * We assume skb_build() uses sizeof(struct skb_shared_info) bytes 1517 * at the end of skb->data, to avoid wasting a full cache line. 1518 * This reduces memory use (skb->truesize). 1519 */ 1520 #define BNX2X_FW_RX_ALIGN_START (1UL << BNX2X_RX_ALIGN_SHIFT) 1521 1522 #define BNX2X_FW_RX_ALIGN_END \ 1523 max_t(u64, 1UL << BNX2X_RX_ALIGN_SHIFT, \ 1524 SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) 1525 1526 #define BNX2X_PXP_DRAM_ALIGN (BNX2X_RX_ALIGN_SHIFT - 5) 1527 1528 struct host_sp_status_block *def_status_blk; 1529 #define DEF_SB_IGU_ID 16 1530 #define DEF_SB_ID HC_SP_SB_ID 1531 __le16 def_idx; 1532 __le16 def_att_idx; 1533 u32 attn_state; 1534 struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS]; 1535 1536 /* slow path ring */ 1537 struct eth_spe *spq; 1538 dma_addr_t spq_mapping; 1539 u16 spq_prod_idx; 1540 struct eth_spe *spq_prod_bd; 1541 struct eth_spe *spq_last_bd; 1542 __le16 *dsb_sp_prod; 1543 atomic_t cq_spq_left; /* ETH_XXX ramrods credit */ 1544 /* used to synchronize spq accesses */ 1545 spinlock_t spq_lock; 1546 1547 /* event queue */ 1548 union event_ring_elem *eq_ring; 1549 dma_addr_t eq_mapping; 1550 u16 eq_prod; 1551 u16 eq_cons; 1552 __le16 *eq_cons_sb; 1553 atomic_t eq_spq_left; /* COMMON_XXX ramrods credit */ 1554 1555 /* Counter for marking that there is a STAT_QUERY ramrod pending */ 1556 u16 stats_pending; 1557 /* Counter for completed statistics ramrods */ 1558 u16 stats_comp; 1559 1560 /* End of fields used in the performance code paths */ 1561 1562 int panic; 1563 int msg_enable; 1564 1565 u32 flags; 1566 #define PCIX_FLAG (1 << 0) 1567 #define PCI_32BIT_FLAG (1 << 1) 1568 #define ONE_PORT_FLAG (1 << 2) 1569 #define NO_WOL_FLAG (1 << 3) 1570 #define USING_MSIX_FLAG (1 << 5) 1571 #define USING_MSI_FLAG (1 << 6) 1572 #define DISABLE_MSI_FLAG (1 << 7) 1573 #define TPA_ENABLE_FLAG (1 << 8) 1574 #define NO_MCP_FLAG (1 << 9) 1575 #define GRO_ENABLE_FLAG (1 << 10) 1576 #define MF_FUNC_DIS (1 << 11) 1577 #define OWN_CNIC_IRQ (1 << 12) 1578 #define NO_ISCSI_OOO_FLAG (1 << 13) 1579 #define NO_ISCSI_FLAG (1 << 14) 1580 #define NO_FCOE_FLAG (1 << 15) 1581 #define BC_SUPPORTS_PFC_STATS (1 << 17) 1582 #define TX_SWITCHING (1 << 18) 1583 #define BC_SUPPORTS_FCOE_FEATURES (1 << 19) 1584 #define USING_SINGLE_MSIX_FLAG (1 << 20) 1585 #define BC_SUPPORTS_DCBX_MSG_NON_PMF (1 << 21) 1586 #define IS_VF_FLAG (1 << 22) 1587 #define INTERRUPTS_ENABLED_FLAG (1 << 23) 1588 #define BC_SUPPORTS_RMMOD_CMD (1 << 24) 1589 #define HAS_PHYS_PORT_ID (1 << 25) 1590 #define AER_ENABLED (1 << 26) 1591 1592 #define BP_NOMCP(bp) ((bp)->flags & NO_MCP_FLAG) 1593 1594 #ifdef CONFIG_BNX2X_SRIOV 1595 #define IS_VF(bp) ((bp)->flags & IS_VF_FLAG) 1596 #define IS_PF(bp) (!((bp)->flags & IS_VF_FLAG)) 1597 #else 1598 #define IS_VF(bp) false 1599 #define IS_PF(bp) true 1600 #endif 1601 1602 #define NO_ISCSI(bp) ((bp)->flags & NO_ISCSI_FLAG) 1603 #define NO_ISCSI_OOO(bp) ((bp)->flags & NO_ISCSI_OOO_FLAG) 1604 #define NO_FCOE(bp) ((bp)->flags & NO_FCOE_FLAG) 1605 1606 u8 cnic_support; 1607 bool cnic_enabled; 1608 bool cnic_loaded; 1609 struct cnic_eth_dev *(*cnic_probe)(struct net_device *); 1610 1611 /* Flag that indicates that we can start looking for FCoE L2 queue 1612 * completions in the default status block. 1613 */ 1614 bool fcoe_init; 1615 1616 int mrrs; 1617 1618 struct delayed_work sp_task; 1619 struct delayed_work iov_task; 1620 1621 atomic_t interrupt_occurred; 1622 struct delayed_work sp_rtnl_task; 1623 1624 struct delayed_work period_task; 1625 struct timer_list timer; 1626 int current_interval; 1627 1628 u16 fw_seq; 1629 u16 fw_drv_pulse_wr_seq; 1630 u32 func_stx; 1631 1632 struct link_params link_params; 1633 struct link_vars link_vars; 1634 u32 link_cnt; 1635 struct bnx2x_link_report_data last_reported_link; 1636 1637 struct mdio_if_info mdio; 1638 1639 struct bnx2x_common common; 1640 struct bnx2x_port port; 1641 1642 struct cmng_init cmng; 1643 1644 u32 mf_config[E1HVN_MAX]; 1645 u32 mf_ext_config; 1646 u32 path_has_ovlan; /* E3 */ 1647 u16 mf_ov; 1648 u8 mf_mode; 1649 #define IS_MF(bp) (bp->mf_mode != 0) 1650 #define IS_MF_SI(bp) (bp->mf_mode == MULTI_FUNCTION_SI) 1651 #define IS_MF_SD(bp) (bp->mf_mode == MULTI_FUNCTION_SD) 1652 #define IS_MF_AFEX(bp) (bp->mf_mode == MULTI_FUNCTION_AFEX) 1653 1654 u8 wol; 1655 1656 int rx_ring_size; 1657 1658 u16 tx_quick_cons_trip_int; 1659 u16 tx_quick_cons_trip; 1660 u16 tx_ticks_int; 1661 u16 tx_ticks; 1662 1663 u16 rx_quick_cons_trip_int; 1664 u16 rx_quick_cons_trip; 1665 u16 rx_ticks_int; 1666 u16 rx_ticks; 1667 /* Maximal coalescing timeout in us */ 1668 #define BNX2X_MAX_COALESCE_TOUT (0xff*BNX2X_BTR) 1669 1670 u32 lin_cnt; 1671 1672 u16 state; 1673 #define BNX2X_STATE_CLOSED 0 1674 #define BNX2X_STATE_OPENING_WAIT4_LOAD 0x1000 1675 #define BNX2X_STATE_OPENING_WAIT4_PORT 0x2000 1676 #define BNX2X_STATE_OPEN 0x3000 1677 #define BNX2X_STATE_CLOSING_WAIT4_HALT 0x4000 1678 #define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000 1679 1680 #define BNX2X_STATE_DIAG 0xe000 1681 #define BNX2X_STATE_ERROR 0xf000 1682 1683 #define BNX2X_MAX_PRIORITY 8 1684 #define BNX2X_MAX_ENTRIES_PER_PRI 16 1685 #define BNX2X_MAX_COS 3 1686 #define BNX2X_MAX_TX_COS 2 1687 int num_queues; 1688 uint num_ethernet_queues; 1689 uint num_cnic_queues; 1690 int num_napi_queues; 1691 int disable_tpa; 1692 1693 u32 rx_mode; 1694 #define BNX2X_RX_MODE_NONE 0 1695 #define BNX2X_RX_MODE_NORMAL 1 1696 #define BNX2X_RX_MODE_ALLMULTI 2 1697 #define BNX2X_RX_MODE_PROMISC 3 1698 #define BNX2X_MAX_MULTICAST 64 1699 1700 u8 igu_dsb_id; 1701 u8 igu_base_sb; 1702 u8 igu_sb_cnt; 1703 u8 min_msix_vec_cnt; 1704 1705 u32 igu_base_addr; 1706 dma_addr_t def_status_blk_mapping; 1707 1708 struct bnx2x_slowpath *slowpath; 1709 dma_addr_t slowpath_mapping; 1710 1711 /* Mechanism protecting the drv_info_to_mcp */ 1712 struct mutex drv_info_mutex; 1713 bool drv_info_mng_owner; 1714 1715 /* Total number of FW statistics requests */ 1716 u8 fw_stats_num; 1717 1718 /* 1719 * This is a memory buffer that will contain both statistics 1720 * ramrod request and data. 1721 */ 1722 void *fw_stats; 1723 dma_addr_t fw_stats_mapping; 1724 1725 /* 1726 * FW statistics request shortcut (points at the 1727 * beginning of fw_stats buffer). 1728 */ 1729 struct bnx2x_fw_stats_req *fw_stats_req; 1730 dma_addr_t fw_stats_req_mapping; 1731 int fw_stats_req_sz; 1732 1733 /* 1734 * FW statistics data shortcut (points at the beginning of 1735 * fw_stats buffer + fw_stats_req_sz). 1736 */ 1737 struct bnx2x_fw_stats_data *fw_stats_data; 1738 dma_addr_t fw_stats_data_mapping; 1739 int fw_stats_data_sz; 1740 1741 /* For max 1024 cids (VF RSS), 32KB ILT page size and 1KB 1742 * context size we need 8 ILT entries. 1743 */ 1744 #define ILT_MAX_L2_LINES 32 1745 struct hw_context context[ILT_MAX_L2_LINES]; 1746 1747 struct bnx2x_ilt *ilt; 1748 #define BP_ILT(bp) ((bp)->ilt) 1749 #define ILT_MAX_LINES 256 1750 /* 1751 * Maximum supported number of RSS queues: number of IGU SBs minus one that goes 1752 * to CNIC. 1753 */ 1754 #define BNX2X_MAX_RSS_COUNT(bp) ((bp)->igu_sb_cnt - CNIC_SUPPORT(bp)) 1755 1756 /* 1757 * Maximum CID count that might be required by the bnx2x: 1758 * Max RSS * Max_Tx_Multi_Cos + FCoE + iSCSI 1759 */ 1760 1761 #define BNX2X_L2_CID_COUNT(bp) (BNX2X_NUM_ETH_QUEUES(bp) * BNX2X_MULTI_TX_COS \ 1762 + CNIC_SUPPORT(bp) * (2 + UIO_CID_PAD(bp))) 1763 #define BNX2X_L2_MAX_CID(bp) (BNX2X_MAX_RSS_COUNT(bp) * BNX2X_MULTI_TX_COS \ 1764 + CNIC_SUPPORT(bp) * (2 + UIO_CID_PAD(bp))) 1765 #define L2_ILT_LINES(bp) (DIV_ROUND_UP(BNX2X_L2_CID_COUNT(bp),\ 1766 ILT_PAGE_CIDS)) 1767 1768 int qm_cid_count; 1769 1770 bool dropless_fc; 1771 1772 void *t2; 1773 dma_addr_t t2_mapping; 1774 struct cnic_ops __rcu *cnic_ops; 1775 void *cnic_data; 1776 u32 cnic_tag; 1777 struct cnic_eth_dev cnic_eth_dev; 1778 union host_hc_status_block cnic_sb; 1779 dma_addr_t cnic_sb_mapping; 1780 struct eth_spe *cnic_kwq; 1781 struct eth_spe *cnic_kwq_prod; 1782 struct eth_spe *cnic_kwq_cons; 1783 struct eth_spe *cnic_kwq_last; 1784 u16 cnic_kwq_pending; 1785 u16 cnic_spq_pending; 1786 u8 fip_mac[ETH_ALEN]; 1787 struct mutex cnic_mutex; 1788 struct bnx2x_vlan_mac_obj iscsi_l2_mac_obj; 1789 1790 /* Start index of the "special" (CNIC related) L2 clients */ 1791 u8 cnic_base_cl_id; 1792 1793 int dmae_ready; 1794 /* used to synchronize dmae accesses */ 1795 spinlock_t dmae_lock; 1796 1797 /* used to protect the FW mail box */ 1798 struct mutex fw_mb_mutex; 1799 1800 /* used to synchronize stats collecting */ 1801 int stats_state; 1802 1803 /* used for synchronization of concurrent threads statistics handling */ 1804 spinlock_t stats_lock; 1805 1806 /* used by dmae command loader */ 1807 struct dmae_command stats_dmae; 1808 int executer_idx; 1809 1810 u16 stats_counter; 1811 struct bnx2x_eth_stats eth_stats; 1812 struct host_func_stats func_stats; 1813 struct bnx2x_eth_stats_old eth_stats_old; 1814 struct bnx2x_net_stats_old net_stats_old; 1815 struct bnx2x_fw_port_stats_old fw_stats_old; 1816 bool stats_init; 1817 1818 struct z_stream_s *strm; 1819 void *gunzip_buf; 1820 dma_addr_t gunzip_mapping; 1821 int gunzip_outlen; 1822 #define FW_BUF_SIZE 0x8000 1823 #define GUNZIP_BUF(bp) (bp->gunzip_buf) 1824 #define GUNZIP_PHYS(bp) (bp->gunzip_mapping) 1825 #define GUNZIP_OUTLEN(bp) (bp->gunzip_outlen) 1826 1827 struct raw_op *init_ops; 1828 /* Init blocks offsets inside init_ops */ 1829 u16 *init_ops_offsets; 1830 /* Data blob - has 32 bit granularity */ 1831 u32 *init_data; 1832 u32 init_mode_flags; 1833 #define INIT_MODE_FLAGS(bp) (bp->init_mode_flags) 1834 /* Zipped PRAM blobs - raw data */ 1835 const u8 *tsem_int_table_data; 1836 const u8 *tsem_pram_data; 1837 const u8 *usem_int_table_data; 1838 const u8 *usem_pram_data; 1839 const u8 *xsem_int_table_data; 1840 const u8 *xsem_pram_data; 1841 const u8 *csem_int_table_data; 1842 const u8 *csem_pram_data; 1843 #define INIT_OPS(bp) (bp->init_ops) 1844 #define INIT_OPS_OFFSETS(bp) (bp->init_ops_offsets) 1845 #define INIT_DATA(bp) (bp->init_data) 1846 #define INIT_TSEM_INT_TABLE_DATA(bp) (bp->tsem_int_table_data) 1847 #define INIT_TSEM_PRAM_DATA(bp) (bp->tsem_pram_data) 1848 #define INIT_USEM_INT_TABLE_DATA(bp) (bp->usem_int_table_data) 1849 #define INIT_USEM_PRAM_DATA(bp) (bp->usem_pram_data) 1850 #define INIT_XSEM_INT_TABLE_DATA(bp) (bp->xsem_int_table_data) 1851 #define INIT_XSEM_PRAM_DATA(bp) (bp->xsem_pram_data) 1852 #define INIT_CSEM_INT_TABLE_DATA(bp) (bp->csem_int_table_data) 1853 #define INIT_CSEM_PRAM_DATA(bp) (bp->csem_pram_data) 1854 1855 #define PHY_FW_VER_LEN 20 1856 char fw_ver[32]; 1857 const struct firmware *firmware; 1858 1859 struct bnx2x_vfdb *vfdb; 1860 #define IS_SRIOV(bp) ((bp)->vfdb) 1861 1862 /* DCB support on/off */ 1863 u16 dcb_state; 1864 #define BNX2X_DCB_STATE_OFF 0 1865 #define BNX2X_DCB_STATE_ON 1 1866 1867 /* DCBX engine mode */ 1868 int dcbx_enabled; 1869 #define BNX2X_DCBX_ENABLED_OFF 0 1870 #define BNX2X_DCBX_ENABLED_ON_NEG_OFF 1 1871 #define BNX2X_DCBX_ENABLED_ON_NEG_ON 2 1872 #define BNX2X_DCBX_ENABLED_INVALID (-1) 1873 1874 bool dcbx_mode_uset; 1875 1876 struct bnx2x_config_dcbx_params dcbx_config_params; 1877 struct bnx2x_dcbx_port_params dcbx_port_params; 1878 int dcb_version; 1879 1880 /* CAM credit pools */ 1881 1882 /* used only in sriov */ 1883 struct bnx2x_credit_pool_obj vlans_pool; 1884 1885 struct bnx2x_credit_pool_obj macs_pool; 1886 1887 /* RX_MODE object */ 1888 struct bnx2x_rx_mode_obj rx_mode_obj; 1889 1890 /* MCAST object */ 1891 struct bnx2x_mcast_obj mcast_obj; 1892 1893 /* RSS configuration object */ 1894 struct bnx2x_rss_config_obj rss_conf_obj; 1895 1896 /* Function State controlling object */ 1897 struct bnx2x_func_sp_obj func_obj; 1898 1899 unsigned long sp_state; 1900 1901 /* operation indication for the sp_rtnl task */ 1902 unsigned long sp_rtnl_state; 1903 1904 /* Indication of the IOV tasks */ 1905 unsigned long iov_task_state; 1906 1907 /* DCBX Negotiation results */ 1908 struct dcbx_features dcbx_local_feat; 1909 u32 dcbx_error; 1910 1911 #ifdef BCM_DCBNL 1912 struct dcbx_features dcbx_remote_feat; 1913 u32 dcbx_remote_flags; 1914 #endif 1915 /* AFEX: store default vlan used */ 1916 int afex_def_vlan_tag; 1917 enum mf_cfg_afex_vlan_mode afex_vlan_mode; 1918 u32 pending_max; 1919 1920 /* multiple tx classes of service */ 1921 u8 max_cos; 1922 1923 /* priority to cos mapping */ 1924 u8 prio_to_cos[8]; 1925 1926 int fp_array_size; 1927 u32 dump_preset_idx; 1928 bool stats_started; 1929 struct semaphore stats_sema; 1930 1931 u8 phys_port_id[ETH_ALEN]; 1932 }; 1933 1934 /* Tx queues may be less or equal to Rx queues */ 1935 extern int num_queues; 1936 #define BNX2X_NUM_QUEUES(bp) (bp->num_queues) 1937 #define BNX2X_NUM_ETH_QUEUES(bp) ((bp)->num_ethernet_queues) 1938 #define BNX2X_NUM_NON_CNIC_QUEUES(bp) (BNX2X_NUM_QUEUES(bp) - \ 1939 (bp)->num_cnic_queues) 1940 #define BNX2X_NUM_RX_QUEUES(bp) BNX2X_NUM_QUEUES(bp) 1941 1942 #define is_multi(bp) (BNX2X_NUM_QUEUES(bp) > 1) 1943 1944 #define BNX2X_MAX_QUEUES(bp) BNX2X_MAX_RSS_COUNT(bp) 1945 /* #define is_eth_multi(bp) (BNX2X_NUM_ETH_QUEUES(bp) > 1) */ 1946 1947 #define RSS_IPV4_CAP_MASK \ 1948 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY 1949 1950 #define RSS_IPV4_TCP_CAP_MASK \ 1951 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY 1952 1953 #define RSS_IPV6_CAP_MASK \ 1954 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY 1955 1956 #define RSS_IPV6_TCP_CAP_MASK \ 1957 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY 1958 1959 /* func init flags */ 1960 #define FUNC_FLG_RSS 0x0001 1961 #define FUNC_FLG_STATS 0x0002 1962 /* removed FUNC_FLG_UNMATCHED 0x0004 */ 1963 #define FUNC_FLG_TPA 0x0008 1964 #define FUNC_FLG_SPQ 0x0010 1965 #define FUNC_FLG_LEADING 0x0020 /* PF only */ 1966 #define FUNC_FLG_LEADING_STATS 0x0040 1967 struct bnx2x_func_init_params { 1968 /* dma */ 1969 dma_addr_t fw_stat_map; /* valid iff FUNC_FLG_STATS */ 1970 dma_addr_t spq_map; /* valid iff FUNC_FLG_SPQ */ 1971 1972 u16 func_flgs; 1973 u16 func_id; /* abs fid */ 1974 u16 pf_id; 1975 u16 spq_prod; /* valid iff FUNC_FLG_SPQ */ 1976 }; 1977 1978 #define for_each_cnic_queue(bp, var) \ 1979 for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \ 1980 (var)++) \ 1981 if (skip_queue(bp, var)) \ 1982 continue; \ 1983 else 1984 1985 #define for_each_eth_queue(bp, var) \ 1986 for ((var) = 0; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++) 1987 1988 #define for_each_nondefault_eth_queue(bp, var) \ 1989 for ((var) = 1; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++) 1990 1991 #define for_each_queue(bp, var) \ 1992 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \ 1993 if (skip_queue(bp, var)) \ 1994 continue; \ 1995 else 1996 1997 /* Skip forwarding FP */ 1998 #define for_each_valid_rx_queue(bp, var) \ 1999 for ((var) = 0; \ 2000 (var) < (CNIC_LOADED(bp) ? BNX2X_NUM_QUEUES(bp) : \ 2001 BNX2X_NUM_ETH_QUEUES(bp)); \ 2002 (var)++) \ 2003 if (skip_rx_queue(bp, var)) \ 2004 continue; \ 2005 else 2006 2007 #define for_each_rx_queue_cnic(bp, var) \ 2008 for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \ 2009 (var)++) \ 2010 if (skip_rx_queue(bp, var)) \ 2011 continue; \ 2012 else 2013 2014 #define for_each_rx_queue(bp, var) \ 2015 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \ 2016 if (skip_rx_queue(bp, var)) \ 2017 continue; \ 2018 else 2019 2020 /* Skip OOO FP */ 2021 #define for_each_valid_tx_queue(bp, var) \ 2022 for ((var) = 0; \ 2023 (var) < (CNIC_LOADED(bp) ? BNX2X_NUM_QUEUES(bp) : \ 2024 BNX2X_NUM_ETH_QUEUES(bp)); \ 2025 (var)++) \ 2026 if (skip_tx_queue(bp, var)) \ 2027 continue; \ 2028 else 2029 2030 #define for_each_tx_queue_cnic(bp, var) \ 2031 for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \ 2032 (var)++) \ 2033 if (skip_tx_queue(bp, var)) \ 2034 continue; \ 2035 else 2036 2037 #define for_each_tx_queue(bp, var) \ 2038 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \ 2039 if (skip_tx_queue(bp, var)) \ 2040 continue; \ 2041 else 2042 2043 #define for_each_nondefault_queue(bp, var) \ 2044 for ((var) = 1; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \ 2045 if (skip_queue(bp, var)) \ 2046 continue; \ 2047 else 2048 2049 #define for_each_cos_in_tx_queue(fp, var) \ 2050 for ((var) = 0; (var) < (fp)->max_cos; (var)++) 2051 2052 /* skip rx queue 2053 * if FCOE l2 support is disabled and this is the fcoe L2 queue 2054 */ 2055 #define skip_rx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx)) 2056 2057 /* skip tx queue 2058 * if FCOE l2 support is disabled and this is the fcoe L2 queue 2059 */ 2060 #define skip_tx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx)) 2061 2062 #define skip_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx)) 2063 2064 /** 2065 * bnx2x_set_mac_one - configure a single MAC address 2066 * 2067 * @bp: driver handle 2068 * @mac: MAC to configure 2069 * @obj: MAC object handle 2070 * @set: if 'true' add a new MAC, otherwise - delete 2071 * @mac_type: the type of the MAC to configure (e.g. ETH, UC list) 2072 * @ramrod_flags: RAMROD_XXX flags (e.g. RAMROD_CONT, RAMROD_COMP_WAIT) 2073 * 2074 * Configures one MAC according to provided parameters or continues the 2075 * execution of previously scheduled commands if RAMROD_CONT is set in 2076 * ramrod_flags. 2077 * 2078 * Returns zero if operation has successfully completed, a positive value if the 2079 * operation has been successfully scheduled and a negative - if a requested 2080 * operations has failed. 2081 */ 2082 int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac, 2083 struct bnx2x_vlan_mac_obj *obj, bool set, 2084 int mac_type, unsigned long *ramrod_flags); 2085 /** 2086 * bnx2x_del_all_macs - delete all MACs configured for the specific MAC object 2087 * 2088 * @bp: driver handle 2089 * @mac_obj: MAC object handle 2090 * @mac_type: type of the MACs to clear (BNX2X_XXX_MAC) 2091 * @wait_for_comp: if 'true' block until completion 2092 * 2093 * Deletes all MACs of the specific type (e.g. ETH, UC list). 2094 * 2095 * Returns zero if operation has successfully completed, a positive value if the 2096 * operation has been successfully scheduled and a negative - if a requested 2097 * operations has failed. 2098 */ 2099 int bnx2x_del_all_macs(struct bnx2x *bp, 2100 struct bnx2x_vlan_mac_obj *mac_obj, 2101 int mac_type, bool wait_for_comp); 2102 2103 /* Init Function API */ 2104 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p); 2105 void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid, 2106 u8 vf_valid, int fw_sb_id, int igu_sb_id); 2107 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port); 2108 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port); 2109 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode); 2110 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port); 2111 void bnx2x_read_mf_cfg(struct bnx2x *bp); 2112 2113 int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val); 2114 2115 /* dmae */ 2116 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32); 2117 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr, 2118 u32 len32); 2119 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx); 2120 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type); 2121 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode); 2122 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type, 2123 bool with_comp, u8 comp_type); 2124 2125 void bnx2x_prep_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae, 2126 u8 src_type, u8 dst_type); 2127 int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae, 2128 u32 *comp); 2129 2130 /* FLR related routines */ 2131 u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp); 2132 void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count); 2133 int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt); 2134 u8 bnx2x_is_pcie_pending(struct pci_dev *dev); 2135 int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg, 2136 char *msg, u32 poll_cnt); 2137 2138 void bnx2x_calc_fc_adv(struct bnx2x *bp); 2139 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid, 2140 u32 data_hi, u32 data_lo, int cmd_type); 2141 void bnx2x_update_coalesce(struct bnx2x *bp); 2142 int bnx2x_get_cur_phy_idx(struct bnx2x *bp); 2143 2144 bool bnx2x_port_after_undi(struct bnx2x *bp); 2145 2146 static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms, 2147 int wait) 2148 { 2149 u32 val; 2150 2151 do { 2152 val = REG_RD(bp, reg); 2153 if (val == expected) 2154 break; 2155 ms -= wait; 2156 msleep(wait); 2157 2158 } while (ms > 0); 2159 2160 return val; 2161 } 2162 2163 void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id, 2164 bool is_pf); 2165 2166 #define BNX2X_ILT_ZALLOC(x, y, size) \ 2167 x = dma_zalloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL) 2168 2169 #define BNX2X_ILT_FREE(x, y, size) \ 2170 do { \ 2171 if (x) { \ 2172 dma_free_coherent(&bp->pdev->dev, size, x, y); \ 2173 x = NULL; \ 2174 y = 0; \ 2175 } \ 2176 } while (0) 2177 2178 #define ILOG2(x) (ilog2((x))) 2179 2180 #define ILT_NUM_PAGE_ENTRIES (3072) 2181 /* In 57710/11 we use whole table since we have 8 func 2182 * In 57712 we have only 4 func, but use same size per func, then only half of 2183 * the table in use 2184 */ 2185 #define ILT_PER_FUNC (ILT_NUM_PAGE_ENTRIES/8) 2186 2187 #define FUNC_ILT_BASE(func) (func * ILT_PER_FUNC) 2188 /* 2189 * the phys address is shifted right 12 bits and has an added 2190 * 1=valid bit added to the 53rd bit 2191 * then since this is a wide register(TM) 2192 * we split it into two 32 bit writes 2193 */ 2194 #define ONCHIP_ADDR1(x) ((u32)(((u64)x >> 12) & 0xFFFFFFFF)) 2195 #define ONCHIP_ADDR2(x) ((u32)((1 << 20) | ((u64)x >> 44))) 2196 2197 /* load/unload mode */ 2198 #define LOAD_NORMAL 0 2199 #define LOAD_OPEN 1 2200 #define LOAD_DIAG 2 2201 #define LOAD_LOOPBACK_EXT 3 2202 #define UNLOAD_NORMAL 0 2203 #define UNLOAD_CLOSE 1 2204 #define UNLOAD_RECOVERY 2 2205 2206 /* DMAE command defines */ 2207 #define DMAE_TIMEOUT -1 2208 #define DMAE_PCI_ERROR -2 /* E2 and onward */ 2209 #define DMAE_NOT_RDY -3 2210 #define DMAE_PCI_ERR_FLAG 0x80000000 2211 2212 #define DMAE_SRC_PCI 0 2213 #define DMAE_SRC_GRC 1 2214 2215 #define DMAE_DST_NONE 0 2216 #define DMAE_DST_PCI 1 2217 #define DMAE_DST_GRC 2 2218 2219 #define DMAE_COMP_PCI 0 2220 #define DMAE_COMP_GRC 1 2221 2222 /* E2 and onward - PCI error handling in the completion */ 2223 2224 #define DMAE_COMP_REGULAR 0 2225 #define DMAE_COM_SET_ERR 1 2226 2227 #define DMAE_CMD_SRC_PCI (DMAE_SRC_PCI << \ 2228 DMAE_COMMAND_SRC_SHIFT) 2229 #define DMAE_CMD_SRC_GRC (DMAE_SRC_GRC << \ 2230 DMAE_COMMAND_SRC_SHIFT) 2231 2232 #define DMAE_CMD_DST_PCI (DMAE_DST_PCI << \ 2233 DMAE_COMMAND_DST_SHIFT) 2234 #define DMAE_CMD_DST_GRC (DMAE_DST_GRC << \ 2235 DMAE_COMMAND_DST_SHIFT) 2236 2237 #define DMAE_CMD_C_DST_PCI (DMAE_COMP_PCI << \ 2238 DMAE_COMMAND_C_DST_SHIFT) 2239 #define DMAE_CMD_C_DST_GRC (DMAE_COMP_GRC << \ 2240 DMAE_COMMAND_C_DST_SHIFT) 2241 2242 #define DMAE_CMD_C_ENABLE DMAE_COMMAND_C_TYPE_ENABLE 2243 2244 #define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT) 2245 #define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT) 2246 #define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT) 2247 #define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT) 2248 2249 #define DMAE_CMD_PORT_0 0 2250 #define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT 2251 2252 #define DMAE_CMD_SRC_RESET DMAE_COMMAND_SRC_RESET 2253 #define DMAE_CMD_DST_RESET DMAE_COMMAND_DST_RESET 2254 #define DMAE_CMD_E1HVN_SHIFT DMAE_COMMAND_E1HVN_SHIFT 2255 2256 #define DMAE_SRC_PF 0 2257 #define DMAE_SRC_VF 1 2258 2259 #define DMAE_DST_PF 0 2260 #define DMAE_DST_VF 1 2261 2262 #define DMAE_C_SRC 0 2263 #define DMAE_C_DST 1 2264 2265 #define DMAE_LEN32_RD_MAX 0x80 2266 #define DMAE_LEN32_WR_MAX(bp) (CHIP_IS_E1(bp) ? 0x400 : 0x2000) 2267 2268 #define DMAE_COMP_VAL 0x60d0d0ae /* E2 and on - upper bit 2269 * indicates error 2270 */ 2271 2272 #define MAX_DMAE_C_PER_PORT 8 2273 #define INIT_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \ 2274 BP_VN(bp)) 2275 #define PMF_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \ 2276 E1HVN_MAX) 2277 2278 /* PCIE link and speed */ 2279 #define PCICFG_LINK_WIDTH 0x1f00000 2280 #define PCICFG_LINK_WIDTH_SHIFT 20 2281 #define PCICFG_LINK_SPEED 0xf0000 2282 #define PCICFG_LINK_SPEED_SHIFT 16 2283 2284 #define BNX2X_NUM_TESTS_SF 7 2285 #define BNX2X_NUM_TESTS_MF 3 2286 #define BNX2X_NUM_TESTS(bp) (IS_MF(bp) ? BNX2X_NUM_TESTS_MF : \ 2287 IS_VF(bp) ? 0 : BNX2X_NUM_TESTS_SF) 2288 2289 #define BNX2X_PHY_LOOPBACK 0 2290 #define BNX2X_MAC_LOOPBACK 1 2291 #define BNX2X_EXT_LOOPBACK 2 2292 #define BNX2X_PHY_LOOPBACK_FAILED 1 2293 #define BNX2X_MAC_LOOPBACK_FAILED 2 2294 #define BNX2X_EXT_LOOPBACK_FAILED 3 2295 #define BNX2X_LOOPBACK_FAILED (BNX2X_MAC_LOOPBACK_FAILED | \ 2296 BNX2X_PHY_LOOPBACK_FAILED) 2297 2298 #define STROM_ASSERT_ARRAY_SIZE 50 2299 2300 /* must be used on a CID before placing it on a HW ring */ 2301 #define HW_CID(bp, x) ((BP_PORT(bp) << 23) | \ 2302 (BP_VN(bp) << BNX2X_SWCID_SHIFT) | \ 2303 (x)) 2304 2305 #define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe)) 2306 #define MAX_SP_DESC_CNT (SP_DESC_CNT - 1) 2307 2308 #define BNX2X_BTR 4 2309 #define MAX_SPQ_PENDING 8 2310 2311 /* CMNG constants, as derived from system spec calculations */ 2312 /* default MIN rate in case VNIC min rate is configured to zero - 100Mbps */ 2313 #define DEF_MIN_RATE 100 2314 /* resolution of the rate shaping timer - 400 usec */ 2315 #define RS_PERIODIC_TIMEOUT_USEC 400 2316 /* number of bytes in single QM arbitration cycle - 2317 * coefficient for calculating the fairness timer */ 2318 #define QM_ARB_BYTES 160000 2319 /* resolution of Min algorithm 1:100 */ 2320 #define MIN_RES 100 2321 /* how many bytes above threshold for the minimal credit of Min algorithm*/ 2322 #define MIN_ABOVE_THRESH 32768 2323 /* Fairness algorithm integration time coefficient - 2324 * for calculating the actual Tfair */ 2325 #define T_FAIR_COEF ((MIN_ABOVE_THRESH + QM_ARB_BYTES) * 8 * MIN_RES) 2326 /* Memory of fairness algorithm . 2 cycles */ 2327 #define FAIR_MEM 2 2328 2329 #define ATTN_NIG_FOR_FUNC (1L << 8) 2330 #define ATTN_SW_TIMER_4_FUNC (1L << 9) 2331 #define GPIO_2_FUNC (1L << 10) 2332 #define GPIO_3_FUNC (1L << 11) 2333 #define GPIO_4_FUNC (1L << 12) 2334 #define ATTN_GENERAL_ATTN_1 (1L << 13) 2335 #define ATTN_GENERAL_ATTN_2 (1L << 14) 2336 #define ATTN_GENERAL_ATTN_3 (1L << 15) 2337 #define ATTN_GENERAL_ATTN_4 (1L << 13) 2338 #define ATTN_GENERAL_ATTN_5 (1L << 14) 2339 #define ATTN_GENERAL_ATTN_6 (1L << 15) 2340 2341 #define ATTN_HARD_WIRED_MASK 0xff00 2342 #define ATTENTION_ID 4 2343 2344 #define IS_MF_STORAGE_ONLY(bp) (IS_MF_STORAGE_SD(bp) || \ 2345 IS_MF_FCOE_AFEX(bp)) 2346 2347 /* stuff added to make the code fit 80Col */ 2348 2349 #define BNX2X_PMF_LINK_ASSERT \ 2350 GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + BP_FUNC(bp)) 2351 2352 #define BNX2X_MC_ASSERT_BITS \ 2353 (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 2354 GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 2355 GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 2356 GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT)) 2357 2358 #define BNX2X_MCP_ASSERT \ 2359 GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT) 2360 2361 #define BNX2X_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC) 2362 #define BNX2X_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \ 2363 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \ 2364 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \ 2365 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \ 2366 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \ 2367 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC)) 2368 2369 #define HW_INTERRUT_ASSERT_SET_0 \ 2370 (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \ 2371 AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \ 2372 AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \ 2373 AEU_INPUTS_ATTN_BITS_BRB_HW_INTERRUPT | \ 2374 AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT) 2375 #define HW_PRTY_ASSERT_SET_0 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \ 2376 AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \ 2377 AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \ 2378 AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\ 2379 AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR |\ 2380 AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR |\ 2381 AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR) 2382 #define HW_INTERRUT_ASSERT_SET_1 \ 2383 (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \ 2384 AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \ 2385 AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \ 2386 AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \ 2387 AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \ 2388 AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \ 2389 AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \ 2390 AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \ 2391 AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \ 2392 AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \ 2393 AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT) 2394 #define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR |\ 2395 AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \ 2396 AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR |\ 2397 AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \ 2398 AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR |\ 2399 AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \ 2400 AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\ 2401 AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR |\ 2402 AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\ 2403 AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \ 2404 AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \ 2405 AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR |\ 2406 AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \ 2407 AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \ 2408 AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR |\ 2409 AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR) 2410 #define HW_INTERRUT_ASSERT_SET_2 \ 2411 (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \ 2412 AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \ 2413 AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \ 2414 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\ 2415 AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT) 2416 #define HW_PRTY_ASSERT_SET_2 (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \ 2417 AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \ 2418 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\ 2419 AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \ 2420 AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \ 2421 AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR |\ 2422 AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \ 2423 AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR) 2424 2425 #define HW_PRTY_ASSERT_SET_3 (AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \ 2426 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \ 2427 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY | \ 2428 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY) 2429 2430 #define HW_PRTY_ASSERT_SET_4 (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | \ 2431 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR) 2432 2433 #define MULTI_MASK 0x7f 2434 2435 #define DEF_USB_FUNC_OFF offsetof(struct cstorm_def_status_block_u, func) 2436 #define DEF_CSB_FUNC_OFF offsetof(struct cstorm_def_status_block_c, func) 2437 #define DEF_XSB_FUNC_OFF offsetof(struct xstorm_def_status_block, func) 2438 #define DEF_TSB_FUNC_OFF offsetof(struct tstorm_def_status_block, func) 2439 2440 #define DEF_USB_IGU_INDEX_OFF \ 2441 offsetof(struct cstorm_def_status_block_u, igu_index) 2442 #define DEF_CSB_IGU_INDEX_OFF \ 2443 offsetof(struct cstorm_def_status_block_c, igu_index) 2444 #define DEF_XSB_IGU_INDEX_OFF \ 2445 offsetof(struct xstorm_def_status_block, igu_index) 2446 #define DEF_TSB_IGU_INDEX_OFF \ 2447 offsetof(struct tstorm_def_status_block, igu_index) 2448 2449 #define DEF_USB_SEGMENT_OFF \ 2450 offsetof(struct cstorm_def_status_block_u, segment) 2451 #define DEF_CSB_SEGMENT_OFF \ 2452 offsetof(struct cstorm_def_status_block_c, segment) 2453 #define DEF_XSB_SEGMENT_OFF \ 2454 offsetof(struct xstorm_def_status_block, segment) 2455 #define DEF_TSB_SEGMENT_OFF \ 2456 offsetof(struct tstorm_def_status_block, segment) 2457 2458 #define BNX2X_SP_DSB_INDEX \ 2459 (&bp->def_status_blk->sp_sb.\ 2460 index_values[HC_SP_INDEX_ETH_DEF_CONS]) 2461 2462 #define CAM_IS_INVALID(x) \ 2463 (GET_FLAG(x.flags, \ 2464 MAC_CONFIGURATION_ENTRY_ACTION_TYPE) == \ 2465 (T_ETH_MAC_COMMAND_INVALIDATE)) 2466 2467 /* Number of u32 elements in MC hash array */ 2468 #define MC_HASH_SIZE 8 2469 #define MC_HASH_OFFSET(bp, i) (BAR_TSTRORM_INTMEM + \ 2470 TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(BP_FUNC(bp)) + i*4) 2471 2472 #ifndef PXP2_REG_PXP2_INT_STS 2473 #define PXP2_REG_PXP2_INT_STS PXP2_REG_PXP2_INT_STS_0 2474 #endif 2475 2476 #ifndef ETH_MAX_RX_CLIENTS_E2 2477 #define ETH_MAX_RX_CLIENTS_E2 ETH_MAX_RX_CLIENTS_E1H 2478 #endif 2479 2480 #define BNX2X_VPD_LEN 128 2481 #define VENDOR_ID_LEN 4 2482 2483 #define VF_ACQUIRE_THRESH 3 2484 #define VF_ACQUIRE_MAC_FILTERS 1 2485 #define VF_ACQUIRE_MC_FILTERS 10 2486 2487 #define GOOD_ME_REG(me_reg) (((me_reg) & ME_REG_VF_VALID) && \ 2488 (!((me_reg) & ME_REG_VF_ERR))) 2489 int bnx2x_compare_fw_ver(struct bnx2x *bp, u32 load_code, bool print_err); 2490 2491 /* Congestion management fairness mode */ 2492 #define CMNG_FNS_NONE 0 2493 #define CMNG_FNS_MINMAX 1 2494 2495 #define HC_SEG_ACCESS_DEF 0 /*Driver decision 0-3*/ 2496 #define HC_SEG_ACCESS_ATTN 4 2497 #define HC_SEG_ACCESS_NORM 0 /*Driver decision 0-1*/ 2498 2499 static const u32 dmae_reg_go_c[] = { 2500 DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3, 2501 DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7, 2502 DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11, 2503 DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15 2504 }; 2505 2506 void bnx2x_set_ethtool_ops(struct bnx2x *bp, struct net_device *netdev); 2507 void bnx2x_notify_link_changed(struct bnx2x *bp); 2508 2509 #define BNX2X_MF_SD_PROTOCOL(bp) \ 2510 ((bp)->mf_config[BP_VN(bp)] & FUNC_MF_CFG_PROTOCOL_MASK) 2511 2512 #define BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp) \ 2513 (BNX2X_MF_SD_PROTOCOL(bp) == FUNC_MF_CFG_PROTOCOL_ISCSI) 2514 2515 #define BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp) \ 2516 (BNX2X_MF_SD_PROTOCOL(bp) == FUNC_MF_CFG_PROTOCOL_FCOE) 2517 2518 #define IS_MF_ISCSI_SD(bp) (IS_MF_SD(bp) && BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) 2519 #define IS_MF_FCOE_SD(bp) (IS_MF_SD(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) 2520 2521 #define BNX2X_MF_EXT_PROTOCOL_FCOE(bp) ((bp)->mf_ext_config & \ 2522 MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) 2523 2524 #define IS_MF_FCOE_AFEX(bp) (IS_MF_AFEX(bp) && BNX2X_MF_EXT_PROTOCOL_FCOE(bp)) 2525 #define IS_MF_STORAGE_SD(bp) (IS_MF_SD(bp) && \ 2526 (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp) || \ 2527 BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp))) 2528 2529 #define SET_FLAG(value, mask, flag) \ 2530 do {\ 2531 (value) &= ~(mask);\ 2532 (value) |= ((flag) << (mask##_SHIFT));\ 2533 } while (0) 2534 2535 #define GET_FLAG(value, mask) \ 2536 (((value) & (mask)) >> (mask##_SHIFT)) 2537 2538 #define GET_FIELD(value, fname) \ 2539 (((value) & (fname##_MASK)) >> (fname##_SHIFT)) 2540 2541 enum { 2542 SWITCH_UPDATE, 2543 AFEX_UPDATE, 2544 }; 2545 2546 #define NUM_MACS 8 2547 2548 void bnx2x_set_local_cmng(struct bnx2x *bp); 2549 2550 void bnx2x_update_mng_version(struct bnx2x *bp); 2551 2552 #define MCPR_SCRATCH_BASE(bp) \ 2553 (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH) 2554 2555 #define E1H_MAX_MF_SB_COUNT (HC_SB_MAX_SB_E1X/(E1HVN_MAX * PORT_MAX)) 2556 2557 #endif /* bnx2x.h */ 2558