1 /* bnx2x.h: Broadcom Everest network driver. 2 * 3 * Copyright (c) 2007-2013 Broadcom Corporation 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation. 8 * 9 * Maintained by: Ariel Elior <ariel.elior@qlogic.com> 10 * Written by: Eliezer Tamir 11 * Based on code from Michael Chan's bnx2 driver 12 */ 13 14 #ifndef BNX2X_H 15 #define BNX2X_H 16 17 #include <linux/pci.h> 18 #include <linux/netdevice.h> 19 #include <linux/dma-mapping.h> 20 #include <linux/types.h> 21 #include <linux/pci_regs.h> 22 23 #include <linux/ptp_clock_kernel.h> 24 #include <linux/net_tstamp.h> 25 #include <linux/timecounter.h> 26 27 /* compilation time flags */ 28 29 /* define this to make the driver freeze on error to allow getting debug info 30 * (you will need to reboot afterwards) */ 31 /* #define BNX2X_STOP_ON_ERROR */ 32 33 #define DRV_MODULE_VERSION "1.710.51-0" 34 #define DRV_MODULE_RELDATE "2014/02/10" 35 #define BNX2X_BC_VER 0x040200 36 37 #if defined(CONFIG_DCB) 38 #define BCM_DCBNL 39 #endif 40 41 #include "bnx2x_hsi.h" 42 43 #include "../cnic_if.h" 44 45 #define BNX2X_MIN_MSIX_VEC_CNT(bp) ((bp)->min_msix_vec_cnt) 46 47 #include <linux/mdio.h> 48 49 #include "bnx2x_reg.h" 50 #include "bnx2x_fw_defs.h" 51 #include "bnx2x_mfw_req.h" 52 #include "bnx2x_link.h" 53 #include "bnx2x_sp.h" 54 #include "bnx2x_dcb.h" 55 #include "bnx2x_stats.h" 56 #include "bnx2x_vfpf.h" 57 58 enum bnx2x_int_mode { 59 BNX2X_INT_MODE_MSIX, 60 BNX2X_INT_MODE_INTX, 61 BNX2X_INT_MODE_MSI 62 }; 63 64 /* error/debug prints */ 65 66 #define DRV_MODULE_NAME "bnx2x" 67 68 /* for messages that are currently off */ 69 #define BNX2X_MSG_OFF 0x0 70 #define BNX2X_MSG_MCP 0x0010000 /* was: NETIF_MSG_HW */ 71 #define BNX2X_MSG_STATS 0x0020000 /* was: NETIF_MSG_TIMER */ 72 #define BNX2X_MSG_NVM 0x0040000 /* was: NETIF_MSG_HW */ 73 #define BNX2X_MSG_DMAE 0x0080000 /* was: NETIF_MSG_HW */ 74 #define BNX2X_MSG_SP 0x0100000 /* was: NETIF_MSG_INTR */ 75 #define BNX2X_MSG_FP 0x0200000 /* was: NETIF_MSG_INTR */ 76 #define BNX2X_MSG_IOV 0x0800000 77 #define BNX2X_MSG_PTP 0x1000000 78 #define BNX2X_MSG_IDLE 0x2000000 /* used for idle check*/ 79 #define BNX2X_MSG_ETHTOOL 0x4000000 80 #define BNX2X_MSG_DCB 0x8000000 81 82 /* regular debug print */ 83 #define DP_INNER(fmt, ...) \ 84 pr_notice("[%s:%d(%s)]" fmt, \ 85 __func__, __LINE__, \ 86 bp->dev ? (bp->dev->name) : "?", \ 87 ##__VA_ARGS__); 88 89 #define DP(__mask, fmt, ...) \ 90 do { \ 91 if (unlikely(bp->msg_enable & (__mask))) \ 92 DP_INNER(fmt, ##__VA_ARGS__); \ 93 } while (0) 94 95 #define DP_AND(__mask, fmt, ...) \ 96 do { \ 97 if (unlikely((bp->msg_enable & (__mask)) == __mask)) \ 98 DP_INNER(fmt, ##__VA_ARGS__); \ 99 } while (0) 100 101 #define DP_CONT(__mask, fmt, ...) \ 102 do { \ 103 if (unlikely(bp->msg_enable & (__mask))) \ 104 pr_cont(fmt, ##__VA_ARGS__); \ 105 } while (0) 106 107 /* errors debug print */ 108 #define BNX2X_DBG_ERR(fmt, ...) \ 109 do { \ 110 if (unlikely(netif_msg_probe(bp))) \ 111 pr_err("[%s:%d(%s)]" fmt, \ 112 __func__, __LINE__, \ 113 bp->dev ? (bp->dev->name) : "?", \ 114 ##__VA_ARGS__); \ 115 } while (0) 116 117 /* for errors (never masked) */ 118 #define BNX2X_ERR(fmt, ...) \ 119 do { \ 120 pr_err("[%s:%d(%s)]" fmt, \ 121 __func__, __LINE__, \ 122 bp->dev ? (bp->dev->name) : "?", \ 123 ##__VA_ARGS__); \ 124 } while (0) 125 126 #define BNX2X_ERROR(fmt, ...) \ 127 pr_err("[%s:%d]" fmt, __func__, __LINE__, ##__VA_ARGS__) 128 129 /* before we have a dev->name use dev_info() */ 130 #define BNX2X_DEV_INFO(fmt, ...) \ 131 do { \ 132 if (unlikely(netif_msg_probe(bp))) \ 133 dev_info(&bp->pdev->dev, fmt, ##__VA_ARGS__); \ 134 } while (0) 135 136 /* Error handling */ 137 void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int); 138 #ifdef BNX2X_STOP_ON_ERROR 139 #define bnx2x_panic() \ 140 do { \ 141 bp->panic = 1; \ 142 BNX2X_ERR("driver assert\n"); \ 143 bnx2x_panic_dump(bp, true); \ 144 } while (0) 145 #else 146 #define bnx2x_panic() \ 147 do { \ 148 bp->panic = 1; \ 149 BNX2X_ERR("driver assert\n"); \ 150 bnx2x_panic_dump(bp, false); \ 151 } while (0) 152 #endif 153 154 #define bnx2x_mc_addr(ha) ((ha)->addr) 155 #define bnx2x_uc_addr(ha) ((ha)->addr) 156 157 #define U64_LO(x) ((u32)(((u64)(x)) & 0xffffffff)) 158 #define U64_HI(x) ((u32)(((u64)(x)) >> 32)) 159 #define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo)) 160 161 #define REG_ADDR(bp, offset) ((bp->regview) + (offset)) 162 163 #define REG_RD(bp, offset) readl(REG_ADDR(bp, offset)) 164 #define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset)) 165 #define REG_RD16(bp, offset) readw(REG_ADDR(bp, offset)) 166 167 #define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset)) 168 #define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset)) 169 #define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset)) 170 171 #define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset) 172 #define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val) 173 174 #define REG_RD_DMAE(bp, offset, valp, len32) \ 175 do { \ 176 bnx2x_read_dmae(bp, offset, len32);\ 177 memcpy(valp, bnx2x_sp(bp, wb_data[0]), (len32) * 4); \ 178 } while (0) 179 180 #define REG_WR_DMAE(bp, offset, valp, len32) \ 181 do { \ 182 memcpy(bnx2x_sp(bp, wb_data[0]), valp, (len32) * 4); \ 183 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \ 184 offset, len32); \ 185 } while (0) 186 187 #define REG_WR_DMAE_LEN(bp, offset, valp, len32) \ 188 REG_WR_DMAE(bp, offset, valp, len32) 189 190 #define VIRT_WR_DMAE_LEN(bp, data, addr, len32, le32_swap) \ 191 do { \ 192 memcpy(GUNZIP_BUF(bp), data, (len32) * 4); \ 193 bnx2x_write_big_buf_wb(bp, addr, len32); \ 194 } while (0) 195 196 #define SHMEM_ADDR(bp, field) (bp->common.shmem_base + \ 197 offsetof(struct shmem_region, field)) 198 #define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field)) 199 #define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val) 200 201 #define SHMEM2_ADDR(bp, field) (bp->common.shmem2_base + \ 202 offsetof(struct shmem2_region, field)) 203 #define SHMEM2_RD(bp, field) REG_RD(bp, SHMEM2_ADDR(bp, field)) 204 #define SHMEM2_WR(bp, field, val) REG_WR(bp, SHMEM2_ADDR(bp, field), val) 205 #define MF_CFG_ADDR(bp, field) (bp->common.mf_cfg_base + \ 206 offsetof(struct mf_cfg, field)) 207 #define MF2_CFG_ADDR(bp, field) (bp->common.mf2_cfg_base + \ 208 offsetof(struct mf2_cfg, field)) 209 210 #define MF_CFG_RD(bp, field) REG_RD(bp, MF_CFG_ADDR(bp, field)) 211 #define MF_CFG_WR(bp, field, val) REG_WR(bp,\ 212 MF_CFG_ADDR(bp, field), (val)) 213 #define MF2_CFG_RD(bp, field) REG_RD(bp, MF2_CFG_ADDR(bp, field)) 214 215 #define SHMEM2_HAS(bp, field) ((bp)->common.shmem2_base && \ 216 (SHMEM2_RD((bp), size) > \ 217 offsetof(struct shmem2_region, field))) 218 219 #define EMAC_RD(bp, reg) REG_RD(bp, emac_base + reg) 220 #define EMAC_WR(bp, reg, val) REG_WR(bp, emac_base + reg, val) 221 222 /* SP SB indices */ 223 224 /* General SP events - stats query, cfc delete, etc */ 225 #define HC_SP_INDEX_ETH_DEF_CONS 3 226 227 /* EQ completions */ 228 #define HC_SP_INDEX_EQ_CONS 7 229 230 /* FCoE L2 connection completions */ 231 #define HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS 6 232 #define HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS 4 233 /* iSCSI L2 */ 234 #define HC_SP_INDEX_ETH_ISCSI_CQ_CONS 5 235 #define HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS 1 236 237 /* Special clients parameters */ 238 239 /* SB indices */ 240 /* FCoE L2 */ 241 #define BNX2X_FCOE_L2_RX_INDEX \ 242 (&bp->def_status_blk->sp_sb.\ 243 index_values[HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS]) 244 245 #define BNX2X_FCOE_L2_TX_INDEX \ 246 (&bp->def_status_blk->sp_sb.\ 247 index_values[HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS]) 248 249 /** 250 * CIDs and CLIDs: 251 * CLIDs below is a CLID for func 0, then the CLID for other 252 * functions will be calculated by the formula: 253 * 254 * FUNC_N_CLID_X = N * NUM_SPECIAL_CLIENTS + FUNC_0_CLID_X 255 * 256 */ 257 enum { 258 BNX2X_ISCSI_ETH_CL_ID_IDX, 259 BNX2X_FCOE_ETH_CL_ID_IDX, 260 BNX2X_MAX_CNIC_ETH_CL_ID_IDX, 261 }; 262 263 /* use a value high enough to be above all the PFs, which has least significant 264 * nibble as 8, so when cnic needs to come up with a CID for UIO to use to 265 * calculate doorbell address according to old doorbell configuration scheme 266 * (db_msg_sz 1 << 7 * cid + 0x40 DPM offset) it can come up with a valid number 267 * We must avoid coming up with cid 8 for iscsi since according to this method 268 * the designated UIO cid will come out 0 and it has a special handling for that 269 * case which doesn't suit us. Therefore will will cieling to closes cid which 270 * has least signigifcant nibble 8 and if it is 8 we will move forward to 0x18. 271 */ 272 273 #define BNX2X_1st_NON_L2_ETH_CID(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) * \ 274 (bp)->max_cos) 275 /* amount of cids traversed by UIO's DPM addition to doorbell */ 276 #define UIO_DPM 8 277 /* roundup to DPM offset */ 278 #define UIO_ROUNDUP(bp) (roundup(BNX2X_1st_NON_L2_ETH_CID(bp), \ 279 UIO_DPM)) 280 /* offset to nearest value which has lsb nibble matching DPM */ 281 #define UIO_CID_OFFSET(bp) ((UIO_ROUNDUP(bp) + UIO_DPM) % \ 282 (UIO_DPM * 2)) 283 /* add offset to rounded-up cid to get a value which could be used with UIO */ 284 #define UIO_DPM_ALIGN(bp) (UIO_ROUNDUP(bp) + UIO_CID_OFFSET(bp)) 285 /* but wait - avoid UIO special case for cid 0 */ 286 #define UIO_DPM_CID0_OFFSET(bp) ((UIO_DPM * 2) * \ 287 (UIO_DPM_ALIGN(bp) == UIO_DPM)) 288 /* Properly DPM aligned CID dajusted to cid 0 secal case */ 289 #define BNX2X_CNIC_START_ETH_CID(bp) (UIO_DPM_ALIGN(bp) + \ 290 (UIO_DPM_CID0_OFFSET(bp))) 291 /* how many cids were wasted - need this value for cid allocation */ 292 #define UIO_CID_PAD(bp) (BNX2X_CNIC_START_ETH_CID(bp) - \ 293 BNX2X_1st_NON_L2_ETH_CID(bp)) 294 /* iSCSI L2 */ 295 #define BNX2X_ISCSI_ETH_CID(bp) (BNX2X_CNIC_START_ETH_CID(bp)) 296 /* FCoE L2 */ 297 #define BNX2X_FCOE_ETH_CID(bp) (BNX2X_CNIC_START_ETH_CID(bp) + 1) 298 299 #define CNIC_SUPPORT(bp) ((bp)->cnic_support) 300 #define CNIC_ENABLED(bp) ((bp)->cnic_enabled) 301 #define CNIC_LOADED(bp) ((bp)->cnic_loaded) 302 #define FCOE_INIT(bp) ((bp)->fcoe_init) 303 304 #define AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR \ 305 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR 306 307 #define SM_RX_ID 0 308 #define SM_TX_ID 1 309 310 /* defines for multiple tx priority indices */ 311 #define FIRST_TX_ONLY_COS_INDEX 1 312 #define FIRST_TX_COS_INDEX 0 313 314 /* rules for calculating the cids of tx-only connections */ 315 #define CID_TO_FP(cid, bp) ((cid) % BNX2X_NUM_NON_CNIC_QUEUES(bp)) 316 #define CID_COS_TO_TX_ONLY_CID(cid, cos, bp) \ 317 (cid + cos * BNX2X_NUM_NON_CNIC_QUEUES(bp)) 318 319 /* fp index inside class of service range */ 320 #define FP_COS_TO_TXQ(fp, cos, bp) \ 321 ((fp)->index + cos * BNX2X_NUM_NON_CNIC_QUEUES(bp)) 322 323 /* Indexes for transmission queues array: 324 * txdata for RSS i CoS j is at location i + (j * num of RSS) 325 * txdata for FCoE (if exist) is at location max cos * num of RSS 326 * txdata for FWD (if exist) is one location after FCoE 327 * txdata for OOO (if exist) is one location after FWD 328 */ 329 enum { 330 FCOE_TXQ_IDX_OFFSET, 331 FWD_TXQ_IDX_OFFSET, 332 OOO_TXQ_IDX_OFFSET, 333 }; 334 #define MAX_ETH_TXQ_IDX(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) * (bp)->max_cos) 335 #define FCOE_TXQ_IDX(bp) (MAX_ETH_TXQ_IDX(bp) + FCOE_TXQ_IDX_OFFSET) 336 337 /* fast path */ 338 /* 339 * This driver uses new build_skb() API : 340 * RX ring buffer contains pointer to kmalloc() data only, 341 * skb are built only after Hardware filled the frame. 342 */ 343 struct sw_rx_bd { 344 u8 *data; 345 DEFINE_DMA_UNMAP_ADDR(mapping); 346 }; 347 348 struct sw_tx_bd { 349 struct sk_buff *skb; 350 u16 first_bd; 351 u8 flags; 352 /* Set on the first BD descriptor when there is a split BD */ 353 #define BNX2X_TSO_SPLIT_BD (1<<0) 354 #define BNX2X_HAS_SECOND_PBD (1<<1) 355 }; 356 357 struct sw_rx_page { 358 struct page *page; 359 DEFINE_DMA_UNMAP_ADDR(mapping); 360 unsigned int offset; 361 }; 362 363 union db_prod { 364 struct doorbell_set_prod data; 365 u32 raw; 366 }; 367 368 /* dropless fc FW/HW related params */ 369 #define BRB_SIZE(bp) (CHIP_IS_E3(bp) ? 1024 : 512) 370 #define MAX_AGG_QS(bp) (CHIP_IS_E1(bp) ? \ 371 ETH_MAX_AGGREGATION_QUEUES_E1 :\ 372 ETH_MAX_AGGREGATION_QUEUES_E1H_E2) 373 #define FW_DROP_LEVEL(bp) (3 + MAX_SPQ_PENDING + MAX_AGG_QS(bp)) 374 #define FW_PREFETCH_CNT 16 375 #define DROPLESS_FC_HEADROOM 100 376 377 /* MC hsi */ 378 #define BCM_PAGE_SHIFT 12 379 #define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT) 380 #define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1)) 381 #define BCM_PAGE_ALIGN(addr) (((addr) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK) 382 383 #define PAGES_PER_SGE_SHIFT 0 384 #define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT) 385 #define SGE_PAGE_SHIFT 12 386 #define SGE_PAGE_SIZE (1 << SGE_PAGE_SHIFT) 387 #define SGE_PAGE_MASK (~(SGE_PAGE_SIZE - 1)) 388 #define SGE_PAGE_ALIGN(addr) (((addr) + SGE_PAGE_SIZE - 1) & SGE_PAGE_MASK) 389 #define SGE_PAGES (SGE_PAGE_SIZE * PAGES_PER_SGE) 390 #define TPA_AGG_SIZE min_t(u32, (min_t(u32, 8, MAX_SKB_FRAGS) * \ 391 SGE_PAGES), 0xffff) 392 393 /* SGE ring related macros */ 394 #define NUM_RX_SGE_PAGES 2 395 #define RX_SGE_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge)) 396 #define NEXT_PAGE_SGE_DESC_CNT 2 397 #define MAX_RX_SGE_CNT (RX_SGE_CNT - NEXT_PAGE_SGE_DESC_CNT) 398 /* RX_SGE_CNT is promised to be a power of 2 */ 399 #define RX_SGE_MASK (RX_SGE_CNT - 1) 400 #define NUM_RX_SGE (RX_SGE_CNT * NUM_RX_SGE_PAGES) 401 #define MAX_RX_SGE (NUM_RX_SGE - 1) 402 #define NEXT_SGE_IDX(x) ((((x) & RX_SGE_MASK) == \ 403 (MAX_RX_SGE_CNT - 1)) ? \ 404 (x) + 1 + NEXT_PAGE_SGE_DESC_CNT : \ 405 (x) + 1) 406 #define RX_SGE(x) ((x) & MAX_RX_SGE) 407 408 /* 409 * Number of required SGEs is the sum of two: 410 * 1. Number of possible opened aggregations (next packet for 411 * these aggregations will probably consume SGE immediately) 412 * 2. Rest of BRB blocks divided by 2 (block will consume new SGE only 413 * after placement on BD for new TPA aggregation) 414 * 415 * Takes into account NEXT_PAGE_SGE_DESC_CNT "next" elements on each page 416 */ 417 #define NUM_SGE_REQ (MAX_AGG_QS(bp) + \ 418 (BRB_SIZE(bp) - MAX_AGG_QS(bp)) / 2) 419 #define NUM_SGE_PG_REQ ((NUM_SGE_REQ + MAX_RX_SGE_CNT - 1) / \ 420 MAX_RX_SGE_CNT) 421 #define SGE_TH_LO(bp) (NUM_SGE_REQ + \ 422 NUM_SGE_PG_REQ * NEXT_PAGE_SGE_DESC_CNT) 423 #define SGE_TH_HI(bp) (SGE_TH_LO(bp) + DROPLESS_FC_HEADROOM) 424 425 /* Manipulate a bit vector defined as an array of u64 */ 426 427 /* Number of bits in one sge_mask array element */ 428 #define BIT_VEC64_ELEM_SZ 64 429 #define BIT_VEC64_ELEM_SHIFT 6 430 #define BIT_VEC64_ELEM_MASK ((u64)BIT_VEC64_ELEM_SZ - 1) 431 432 #define __BIT_VEC64_SET_BIT(el, bit) \ 433 do { \ 434 el = ((el) | ((u64)0x1 << (bit))); \ 435 } while (0) 436 437 #define __BIT_VEC64_CLEAR_BIT(el, bit) \ 438 do { \ 439 el = ((el) & (~((u64)0x1 << (bit)))); \ 440 } while (0) 441 442 #define BIT_VEC64_SET_BIT(vec64, idx) \ 443 __BIT_VEC64_SET_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \ 444 (idx) & BIT_VEC64_ELEM_MASK) 445 446 #define BIT_VEC64_CLEAR_BIT(vec64, idx) \ 447 __BIT_VEC64_CLEAR_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \ 448 (idx) & BIT_VEC64_ELEM_MASK) 449 450 #define BIT_VEC64_TEST_BIT(vec64, idx) \ 451 (((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT] >> \ 452 ((idx) & BIT_VEC64_ELEM_MASK)) & 0x1) 453 454 /* Creates a bitmask of all ones in less significant bits. 455 idx - index of the most significant bit in the created mask */ 456 #define BIT_VEC64_ONES_MASK(idx) \ 457 (((u64)0x1 << (((idx) & BIT_VEC64_ELEM_MASK) + 1)) - 1) 458 #define BIT_VEC64_ELEM_ONE_MASK ((u64)(~0)) 459 460 /*******************************************************/ 461 462 /* Number of u64 elements in SGE mask array */ 463 #define RX_SGE_MASK_LEN (NUM_RX_SGE / BIT_VEC64_ELEM_SZ) 464 #define RX_SGE_MASK_LEN_MASK (RX_SGE_MASK_LEN - 1) 465 #define NEXT_SGE_MASK_ELEM(el) (((el) + 1) & RX_SGE_MASK_LEN_MASK) 466 467 union host_hc_status_block { 468 /* pointer to fp status block e1x */ 469 struct host_hc_status_block_e1x *e1x_sb; 470 /* pointer to fp status block e2 */ 471 struct host_hc_status_block_e2 *e2_sb; 472 }; 473 474 struct bnx2x_agg_info { 475 /* 476 * First aggregation buffer is a data buffer, the following - are pages. 477 * We will preallocate the data buffer for each aggregation when 478 * we open the interface and will replace the BD at the consumer 479 * with this one when we receive the TPA_START CQE in order to 480 * keep the Rx BD ring consistent. 481 */ 482 struct sw_rx_bd first_buf; 483 u8 tpa_state; 484 #define BNX2X_TPA_START 1 485 #define BNX2X_TPA_STOP 2 486 #define BNX2X_TPA_ERROR 3 487 u8 placement_offset; 488 u16 parsing_flags; 489 u16 vlan_tag; 490 u16 len_on_bd; 491 u32 rxhash; 492 enum pkt_hash_types rxhash_type; 493 u16 gro_size; 494 u16 full_page; 495 }; 496 497 #define Q_STATS_OFFSET32(stat_name) \ 498 (offsetof(struct bnx2x_eth_q_stats, stat_name) / 4) 499 500 struct bnx2x_fp_txdata { 501 502 struct sw_tx_bd *tx_buf_ring; 503 504 union eth_tx_bd_types *tx_desc_ring; 505 dma_addr_t tx_desc_mapping; 506 507 u32 cid; 508 509 union db_prod tx_db; 510 511 u16 tx_pkt_prod; 512 u16 tx_pkt_cons; 513 u16 tx_bd_prod; 514 u16 tx_bd_cons; 515 516 unsigned long tx_pkt; 517 518 __le16 *tx_cons_sb; 519 520 int txq_index; 521 struct bnx2x_fastpath *parent_fp; 522 int tx_ring_size; 523 }; 524 525 enum bnx2x_tpa_mode_t { 526 TPA_MODE_DISABLED, 527 TPA_MODE_LRO, 528 TPA_MODE_GRO 529 }; 530 531 struct bnx2x_alloc_pool { 532 struct page *page; 533 unsigned int offset; 534 }; 535 536 struct bnx2x_fastpath { 537 struct bnx2x *bp; /* parent */ 538 539 struct napi_struct napi; 540 541 #ifdef CONFIG_NET_RX_BUSY_POLL 542 unsigned long busy_poll_state; 543 #endif 544 545 union host_hc_status_block status_blk; 546 /* chip independent shortcuts into sb structure */ 547 __le16 *sb_index_values; 548 __le16 *sb_running_index; 549 /* chip independent shortcut into rx_prods_offset memory */ 550 u32 ustorm_rx_prods_offset; 551 552 u32 rx_buf_size; 553 u32 rx_frag_size; /* 0 if kmalloced(), or rx_buf_size + NET_SKB_PAD */ 554 dma_addr_t status_blk_mapping; 555 556 enum bnx2x_tpa_mode_t mode; 557 558 u8 max_cos; /* actual number of active tx coses */ 559 struct bnx2x_fp_txdata *txdata_ptr[BNX2X_MULTI_TX_COS]; 560 561 struct sw_rx_bd *rx_buf_ring; /* BDs mappings ring */ 562 struct sw_rx_page *rx_page_ring; /* SGE pages mappings ring */ 563 564 struct eth_rx_bd *rx_desc_ring; 565 dma_addr_t rx_desc_mapping; 566 567 union eth_rx_cqe *rx_comp_ring; 568 dma_addr_t rx_comp_mapping; 569 570 /* SGE ring */ 571 struct eth_rx_sge *rx_sge_ring; 572 dma_addr_t rx_sge_mapping; 573 574 u64 sge_mask[RX_SGE_MASK_LEN]; 575 576 u32 cid; 577 578 __le16 fp_hc_idx; 579 580 u8 index; /* number in fp array */ 581 u8 rx_queue; /* index for skb_record */ 582 u8 cl_id; /* eth client id */ 583 u8 cl_qzone_id; 584 u8 fw_sb_id; /* status block number in FW */ 585 u8 igu_sb_id; /* status block number in HW */ 586 587 u16 rx_bd_prod; 588 u16 rx_bd_cons; 589 u16 rx_comp_prod; 590 u16 rx_comp_cons; 591 u16 rx_sge_prod; 592 /* The last maximal completed SGE */ 593 u16 last_max_sge; 594 __le16 *rx_cons_sb; 595 unsigned long rx_pkt, 596 rx_calls; 597 598 /* TPA related */ 599 struct bnx2x_agg_info *tpa_info; 600 #ifdef BNX2X_STOP_ON_ERROR 601 u64 tpa_queue_used; 602 #endif 603 /* The size is calculated using the following: 604 sizeof name field from netdev structure + 605 4 ('-Xx-' string) + 606 4 (for the digits and to make it DWORD aligned) */ 607 #define FP_NAME_SIZE (sizeof(((struct net_device *)0)->name) + 8) 608 char name[FP_NAME_SIZE]; 609 610 struct bnx2x_alloc_pool page_pool; 611 }; 612 613 #define bnx2x_fp(bp, nr, var) ((bp)->fp[(nr)].var) 614 #define bnx2x_sp_obj(bp, fp) ((bp)->sp_objs[(fp)->index]) 615 #define bnx2x_fp_stats(bp, fp) (&((bp)->fp_stats[(fp)->index])) 616 #define bnx2x_fp_qstats(bp, fp) (&((bp)->fp_stats[(fp)->index].eth_q_stats)) 617 618 #ifdef CONFIG_NET_RX_BUSY_POLL 619 620 enum bnx2x_fp_state { 621 BNX2X_STATE_FP_NAPI = BIT(0), /* NAPI handler owns the queue */ 622 623 BNX2X_STATE_FP_NAPI_REQ_BIT = 1, /* NAPI would like to own the queue */ 624 BNX2X_STATE_FP_NAPI_REQ = BIT(1), 625 626 BNX2X_STATE_FP_POLL_BIT = 2, 627 BNX2X_STATE_FP_POLL = BIT(2), /* busy_poll owns the queue */ 628 629 BNX2X_STATE_FP_DISABLE_BIT = 3, /* queue is dismantled */ 630 }; 631 632 static inline void bnx2x_fp_busy_poll_init(struct bnx2x_fastpath *fp) 633 { 634 WRITE_ONCE(fp->busy_poll_state, 0); 635 } 636 637 /* called from the device poll routine to get ownership of a FP */ 638 static inline bool bnx2x_fp_lock_napi(struct bnx2x_fastpath *fp) 639 { 640 unsigned long prev, old = READ_ONCE(fp->busy_poll_state); 641 642 while (1) { 643 switch (old) { 644 case BNX2X_STATE_FP_POLL: 645 /* make sure bnx2x_fp_lock_poll() wont starve us */ 646 set_bit(BNX2X_STATE_FP_NAPI_REQ_BIT, 647 &fp->busy_poll_state); 648 /* fallthrough */ 649 case BNX2X_STATE_FP_POLL | BNX2X_STATE_FP_NAPI_REQ: 650 return false; 651 default: 652 break; 653 } 654 prev = cmpxchg(&fp->busy_poll_state, old, BNX2X_STATE_FP_NAPI); 655 if (unlikely(prev != old)) { 656 old = prev; 657 continue; 658 } 659 return true; 660 } 661 } 662 663 static inline void bnx2x_fp_unlock_napi(struct bnx2x_fastpath *fp) 664 { 665 smp_wmb(); 666 fp->busy_poll_state = 0; 667 } 668 669 /* called from bnx2x_low_latency_poll() */ 670 static inline bool bnx2x_fp_lock_poll(struct bnx2x_fastpath *fp) 671 { 672 return cmpxchg(&fp->busy_poll_state, 0, BNX2X_STATE_FP_POLL) == 0; 673 } 674 675 static inline void bnx2x_fp_unlock_poll(struct bnx2x_fastpath *fp) 676 { 677 smp_mb__before_atomic(); 678 clear_bit(BNX2X_STATE_FP_POLL_BIT, &fp->busy_poll_state); 679 } 680 681 /* true if a socket is polling */ 682 static inline bool bnx2x_fp_ll_polling(struct bnx2x_fastpath *fp) 683 { 684 return READ_ONCE(fp->busy_poll_state) & BNX2X_STATE_FP_POLL; 685 } 686 687 /* false if fp is currently owned */ 688 static inline bool bnx2x_fp_ll_disable(struct bnx2x_fastpath *fp) 689 { 690 set_bit(BNX2X_STATE_FP_DISABLE_BIT, &fp->busy_poll_state); 691 return !bnx2x_fp_ll_polling(fp); 692 693 } 694 #else 695 static inline void bnx2x_fp_busy_poll_init(struct bnx2x_fastpath *fp) 696 { 697 } 698 699 static inline bool bnx2x_fp_lock_napi(struct bnx2x_fastpath *fp) 700 { 701 return true; 702 } 703 704 static inline void bnx2x_fp_unlock_napi(struct bnx2x_fastpath *fp) 705 { 706 } 707 708 static inline bool bnx2x_fp_lock_poll(struct bnx2x_fastpath *fp) 709 { 710 return false; 711 } 712 713 static inline void bnx2x_fp_unlock_poll(struct bnx2x_fastpath *fp) 714 { 715 } 716 717 static inline bool bnx2x_fp_ll_polling(struct bnx2x_fastpath *fp) 718 { 719 return false; 720 } 721 static inline bool bnx2x_fp_ll_disable(struct bnx2x_fastpath *fp) 722 { 723 return true; 724 } 725 #endif /* CONFIG_NET_RX_BUSY_POLL */ 726 727 /* Use 2500 as a mini-jumbo MTU for FCoE */ 728 #define BNX2X_FCOE_MINI_JUMBO_MTU 2500 729 730 #define FCOE_IDX_OFFSET 0 731 732 #define FCOE_IDX(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) + \ 733 FCOE_IDX_OFFSET) 734 #define bnx2x_fcoe_fp(bp) (&bp->fp[FCOE_IDX(bp)]) 735 #define bnx2x_fcoe(bp, var) (bnx2x_fcoe_fp(bp)->var) 736 #define bnx2x_fcoe_inner_sp_obj(bp) (&bp->sp_objs[FCOE_IDX(bp)]) 737 #define bnx2x_fcoe_sp_obj(bp, var) (bnx2x_fcoe_inner_sp_obj(bp)->var) 738 #define bnx2x_fcoe_tx(bp, var) (bnx2x_fcoe_fp(bp)-> \ 739 txdata_ptr[FIRST_TX_COS_INDEX] \ 740 ->var) 741 742 #define IS_ETH_FP(fp) ((fp)->index < BNX2X_NUM_ETH_QUEUES((fp)->bp)) 743 #define IS_FCOE_FP(fp) ((fp)->index == FCOE_IDX((fp)->bp)) 744 #define IS_FCOE_IDX(idx) ((idx) == FCOE_IDX(bp)) 745 746 /* MC hsi */ 747 #define MAX_FETCH_BD 13 /* HW max BDs per packet */ 748 #define RX_COPY_THRESH 92 749 750 #define NUM_TX_RINGS 16 751 #define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types)) 752 #define NEXT_PAGE_TX_DESC_CNT 1 753 #define MAX_TX_DESC_CNT (TX_DESC_CNT - NEXT_PAGE_TX_DESC_CNT) 754 #define NUM_TX_BD (TX_DESC_CNT * NUM_TX_RINGS) 755 #define MAX_TX_BD (NUM_TX_BD - 1) 756 #define MAX_TX_AVAIL (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2) 757 #define NEXT_TX_IDX(x) ((((x) & MAX_TX_DESC_CNT) == \ 758 (MAX_TX_DESC_CNT - 1)) ? \ 759 (x) + 1 + NEXT_PAGE_TX_DESC_CNT : \ 760 (x) + 1) 761 #define TX_BD(x) ((x) & MAX_TX_BD) 762 #define TX_BD_POFF(x) ((x) & MAX_TX_DESC_CNT) 763 764 /* number of NEXT_PAGE descriptors may be required during placement */ 765 #define NEXT_CNT_PER_TX_PKT(bds) \ 766 (((bds) + MAX_TX_DESC_CNT - 1) / \ 767 MAX_TX_DESC_CNT * NEXT_PAGE_TX_DESC_CNT) 768 /* max BDs per tx packet w/o next_pages: 769 * START_BD - describes packed 770 * START_BD(splitted) - includes unpaged data segment for GSO 771 * PARSING_BD - for TSO and CSUM data 772 * PARSING_BD2 - for encapsulation data 773 * Frag BDs - describes pages for frags 774 */ 775 #define BDS_PER_TX_PKT 4 776 #define MAX_BDS_PER_TX_PKT (MAX_SKB_FRAGS + BDS_PER_TX_PKT) 777 /* max BDs per tx packet including next pages */ 778 #define MAX_DESC_PER_TX_PKT (MAX_BDS_PER_TX_PKT + \ 779 NEXT_CNT_PER_TX_PKT(MAX_BDS_PER_TX_PKT)) 780 781 /* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */ 782 #define NUM_RX_RINGS 8 783 #define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd)) 784 #define NEXT_PAGE_RX_DESC_CNT 2 785 #define MAX_RX_DESC_CNT (RX_DESC_CNT - NEXT_PAGE_RX_DESC_CNT) 786 #define RX_DESC_MASK (RX_DESC_CNT - 1) 787 #define NUM_RX_BD (RX_DESC_CNT * NUM_RX_RINGS) 788 #define MAX_RX_BD (NUM_RX_BD - 1) 789 #define MAX_RX_AVAIL (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2) 790 791 /* dropless fc calculations for BDs 792 * 793 * Number of BDs should as number of buffers in BRB: 794 * Low threshold takes into account NEXT_PAGE_RX_DESC_CNT 795 * "next" elements on each page 796 */ 797 #define NUM_BD_REQ BRB_SIZE(bp) 798 #define NUM_BD_PG_REQ ((NUM_BD_REQ + MAX_RX_DESC_CNT - 1) / \ 799 MAX_RX_DESC_CNT) 800 #define BD_TH_LO(bp) (NUM_BD_REQ + \ 801 NUM_BD_PG_REQ * NEXT_PAGE_RX_DESC_CNT + \ 802 FW_DROP_LEVEL(bp)) 803 #define BD_TH_HI(bp) (BD_TH_LO(bp) + DROPLESS_FC_HEADROOM) 804 805 #define MIN_RX_AVAIL ((bp)->dropless_fc ? BD_TH_HI(bp) + 128 : 128) 806 807 #define MIN_RX_SIZE_TPA_HW (CHIP_IS_E1(bp) ? \ 808 ETH_MIN_RX_CQES_WITH_TPA_E1 : \ 809 ETH_MIN_RX_CQES_WITH_TPA_E1H_E2) 810 #define MIN_RX_SIZE_NONTPA_HW ETH_MIN_RX_CQES_WITHOUT_TPA 811 #define MIN_RX_SIZE_TPA (max_t(u32, MIN_RX_SIZE_TPA_HW, MIN_RX_AVAIL)) 812 #define MIN_RX_SIZE_NONTPA (max_t(u32, MIN_RX_SIZE_NONTPA_HW,\ 813 MIN_RX_AVAIL)) 814 815 #define NEXT_RX_IDX(x) ((((x) & RX_DESC_MASK) == \ 816 (MAX_RX_DESC_CNT - 1)) ? \ 817 (x) + 1 + NEXT_PAGE_RX_DESC_CNT : \ 818 (x) + 1) 819 #define RX_BD(x) ((x) & MAX_RX_BD) 820 821 /* 822 * As long as CQE is X times bigger than BD entry we have to allocate X times 823 * more pages for CQ ring in order to keep it balanced with BD ring 824 */ 825 #define CQE_BD_REL (sizeof(union eth_rx_cqe) / sizeof(struct eth_rx_bd)) 826 #define NUM_RCQ_RINGS (NUM_RX_RINGS * CQE_BD_REL) 827 #define RCQ_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe)) 828 #define NEXT_PAGE_RCQ_DESC_CNT 1 829 #define MAX_RCQ_DESC_CNT (RCQ_DESC_CNT - NEXT_PAGE_RCQ_DESC_CNT) 830 #define NUM_RCQ_BD (RCQ_DESC_CNT * NUM_RCQ_RINGS) 831 #define MAX_RCQ_BD (NUM_RCQ_BD - 1) 832 #define MAX_RCQ_AVAIL (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2) 833 #define NEXT_RCQ_IDX(x) ((((x) & MAX_RCQ_DESC_CNT) == \ 834 (MAX_RCQ_DESC_CNT - 1)) ? \ 835 (x) + 1 + NEXT_PAGE_RCQ_DESC_CNT : \ 836 (x) + 1) 837 #define RCQ_BD(x) ((x) & MAX_RCQ_BD) 838 839 /* dropless fc calculations for RCQs 840 * 841 * Number of RCQs should be as number of buffers in BRB: 842 * Low threshold takes into account NEXT_PAGE_RCQ_DESC_CNT 843 * "next" elements on each page 844 */ 845 #define NUM_RCQ_REQ BRB_SIZE(bp) 846 #define NUM_RCQ_PG_REQ ((NUM_BD_REQ + MAX_RCQ_DESC_CNT - 1) / \ 847 MAX_RCQ_DESC_CNT) 848 #define RCQ_TH_LO(bp) (NUM_RCQ_REQ + \ 849 NUM_RCQ_PG_REQ * NEXT_PAGE_RCQ_DESC_CNT + \ 850 FW_DROP_LEVEL(bp)) 851 #define RCQ_TH_HI(bp) (RCQ_TH_LO(bp) + DROPLESS_FC_HEADROOM) 852 853 /* This is needed for determining of last_max */ 854 #define SUB_S16(a, b) (s16)((s16)(a) - (s16)(b)) 855 #define SUB_S32(a, b) (s32)((s32)(a) - (s32)(b)) 856 857 #define BNX2X_SWCID_SHIFT 17 858 #define BNX2X_SWCID_MASK ((0x1 << BNX2X_SWCID_SHIFT) - 1) 859 860 /* used on a CID received from the HW */ 861 #define SW_CID(x) (le32_to_cpu(x) & BNX2X_SWCID_MASK) 862 #define CQE_CMD(x) (le32_to_cpu(x) >> \ 863 COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT) 864 865 #define BD_UNMAP_ADDR(bd) HILO_U64(le32_to_cpu((bd)->addr_hi), \ 866 le32_to_cpu((bd)->addr_lo)) 867 #define BD_UNMAP_LEN(bd) (le16_to_cpu((bd)->nbytes)) 868 869 #define BNX2X_DB_MIN_SHIFT 3 /* 8 bytes */ 870 #define BNX2X_DB_SHIFT 3 /* 8 bytes*/ 871 #if (BNX2X_DB_SHIFT < BNX2X_DB_MIN_SHIFT) 872 #error "Min DB doorbell stride is 8" 873 #endif 874 #define DOORBELL(bp, cid, val) \ 875 do { \ 876 writel((u32)(val), bp->doorbells + (bp->db_size * (cid))); \ 877 } while (0) 878 879 /* TX CSUM helpers */ 880 #define SKB_CS_OFF(skb) (offsetof(struct tcphdr, check) - \ 881 skb->csum_offset) 882 #define SKB_CS(skb) (*(u16 *)(skb_transport_header(skb) + \ 883 skb->csum_offset)) 884 885 #define pbd_tcp_flags(tcp_hdr) (ntohl(tcp_flag_word(tcp_hdr))>>16 & 0xff) 886 887 #define XMIT_PLAIN 0 888 #define XMIT_CSUM_V4 (1 << 0) 889 #define XMIT_CSUM_V6 (1 << 1) 890 #define XMIT_CSUM_TCP (1 << 2) 891 #define XMIT_GSO_V4 (1 << 3) 892 #define XMIT_GSO_V6 (1 << 4) 893 #define XMIT_CSUM_ENC_V4 (1 << 5) 894 #define XMIT_CSUM_ENC_V6 (1 << 6) 895 #define XMIT_GSO_ENC_V4 (1 << 7) 896 #define XMIT_GSO_ENC_V6 (1 << 8) 897 898 #define XMIT_CSUM_ENC (XMIT_CSUM_ENC_V4 | XMIT_CSUM_ENC_V6) 899 #define XMIT_GSO_ENC (XMIT_GSO_ENC_V4 | XMIT_GSO_ENC_V6) 900 901 #define XMIT_CSUM (XMIT_CSUM_V4 | XMIT_CSUM_V6 | XMIT_CSUM_ENC) 902 #define XMIT_GSO (XMIT_GSO_V4 | XMIT_GSO_V6 | XMIT_GSO_ENC) 903 904 /* stuff added to make the code fit 80Col */ 905 #define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE) 906 #define CQE_TYPE_START(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_START_AGG) 907 #define CQE_TYPE_STOP(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_STOP_AGG) 908 #define CQE_TYPE_SLOW(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_RAMROD) 909 #define CQE_TYPE_FAST(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_FASTPATH) 910 911 #define ETH_RX_ERROR_FALGS ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG 912 913 #define BNX2X_PRS_FLAG_OVERETH_IPV4(flags) \ 914 (((le16_to_cpu(flags) & \ 915 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) >> \ 916 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT) \ 917 == PRS_FLAG_OVERETH_IPV4) 918 #define BNX2X_RX_SUM_FIX(cqe) \ 919 BNX2X_PRS_FLAG_OVERETH_IPV4(cqe->fast_path_cqe.pars_flags.flags) 920 921 #define FP_USB_FUNC_OFF \ 922 offsetof(struct cstorm_status_block_u, func) 923 #define FP_CSB_FUNC_OFF \ 924 offsetof(struct cstorm_status_block_c, func) 925 926 #define HC_INDEX_ETH_RX_CQ_CONS 1 927 928 #define HC_INDEX_OOO_TX_CQ_CONS 4 929 930 #define HC_INDEX_ETH_TX_CQ_CONS_COS0 5 931 932 #define HC_INDEX_ETH_TX_CQ_CONS_COS1 6 933 934 #define HC_INDEX_ETH_TX_CQ_CONS_COS2 7 935 936 #define HC_INDEX_ETH_FIRST_TX_CQ_CONS HC_INDEX_ETH_TX_CQ_CONS_COS0 937 938 #define BNX2X_RX_SB_INDEX \ 939 (&fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS]) 940 941 #define BNX2X_TX_SB_INDEX_BASE BNX2X_TX_SB_INDEX_COS0 942 943 #define BNX2X_TX_SB_INDEX_COS0 \ 944 (&fp->sb_index_values[HC_INDEX_ETH_TX_CQ_CONS_COS0]) 945 946 /* end of fast path */ 947 948 /* common */ 949 950 struct bnx2x_common { 951 952 u32 chip_id; 953 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */ 954 #define CHIP_ID(bp) (bp->common.chip_id & 0xfffffff0) 955 956 #define CHIP_NUM(bp) (bp->common.chip_id >> 16) 957 #define CHIP_NUM_57710 0x164e 958 #define CHIP_NUM_57711 0x164f 959 #define CHIP_NUM_57711E 0x1650 960 #define CHIP_NUM_57712 0x1662 961 #define CHIP_NUM_57712_MF 0x1663 962 #define CHIP_NUM_57712_VF 0x166f 963 #define CHIP_NUM_57713 0x1651 964 #define CHIP_NUM_57713E 0x1652 965 #define CHIP_NUM_57800 0x168a 966 #define CHIP_NUM_57800_MF 0x16a5 967 #define CHIP_NUM_57800_VF 0x16a9 968 #define CHIP_NUM_57810 0x168e 969 #define CHIP_NUM_57810_MF 0x16ae 970 #define CHIP_NUM_57810_VF 0x16af 971 #define CHIP_NUM_57811 0x163d 972 #define CHIP_NUM_57811_MF 0x163e 973 #define CHIP_NUM_57811_VF 0x163f 974 #define CHIP_NUM_57840_OBSOLETE 0x168d 975 #define CHIP_NUM_57840_MF_OBSOLETE 0x16ab 976 #define CHIP_NUM_57840_4_10 0x16a1 977 #define CHIP_NUM_57840_2_20 0x16a2 978 #define CHIP_NUM_57840_MF 0x16a4 979 #define CHIP_NUM_57840_VF 0x16ad 980 #define CHIP_IS_E1(bp) (CHIP_NUM(bp) == CHIP_NUM_57710) 981 #define CHIP_IS_57711(bp) (CHIP_NUM(bp) == CHIP_NUM_57711) 982 #define CHIP_IS_57711E(bp) (CHIP_NUM(bp) == CHIP_NUM_57711E) 983 #define CHIP_IS_57712(bp) (CHIP_NUM(bp) == CHIP_NUM_57712) 984 #define CHIP_IS_57712_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57712_VF) 985 #define CHIP_IS_57712_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57712_MF) 986 #define CHIP_IS_57800(bp) (CHIP_NUM(bp) == CHIP_NUM_57800) 987 #define CHIP_IS_57800_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57800_MF) 988 #define CHIP_IS_57800_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57800_VF) 989 #define CHIP_IS_57810(bp) (CHIP_NUM(bp) == CHIP_NUM_57810) 990 #define CHIP_IS_57810_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57810_MF) 991 #define CHIP_IS_57810_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57810_VF) 992 #define CHIP_IS_57811(bp) (CHIP_NUM(bp) == CHIP_NUM_57811) 993 #define CHIP_IS_57811_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57811_MF) 994 #define CHIP_IS_57811_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57811_VF) 995 #define CHIP_IS_57840(bp) \ 996 ((CHIP_NUM(bp) == CHIP_NUM_57840_4_10) || \ 997 (CHIP_NUM(bp) == CHIP_NUM_57840_2_20) || \ 998 (CHIP_NUM(bp) == CHIP_NUM_57840_OBSOLETE)) 999 #define CHIP_IS_57840_MF(bp) ((CHIP_NUM(bp) == CHIP_NUM_57840_MF) || \ 1000 (CHIP_NUM(bp) == CHIP_NUM_57840_MF_OBSOLETE)) 1001 #define CHIP_IS_57840_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57840_VF) 1002 #define CHIP_IS_E1H(bp) (CHIP_IS_57711(bp) || \ 1003 CHIP_IS_57711E(bp)) 1004 #define CHIP_IS_57811xx(bp) (CHIP_IS_57811(bp) || \ 1005 CHIP_IS_57811_MF(bp) || \ 1006 CHIP_IS_57811_VF(bp)) 1007 #define CHIP_IS_E2(bp) (CHIP_IS_57712(bp) || \ 1008 CHIP_IS_57712_MF(bp) || \ 1009 CHIP_IS_57712_VF(bp)) 1010 #define CHIP_IS_E3(bp) (CHIP_IS_57800(bp) || \ 1011 CHIP_IS_57800_MF(bp) || \ 1012 CHIP_IS_57800_VF(bp) || \ 1013 CHIP_IS_57810(bp) || \ 1014 CHIP_IS_57810_MF(bp) || \ 1015 CHIP_IS_57810_VF(bp) || \ 1016 CHIP_IS_57811xx(bp) || \ 1017 CHIP_IS_57840(bp) || \ 1018 CHIP_IS_57840_MF(bp) || \ 1019 CHIP_IS_57840_VF(bp)) 1020 #define CHIP_IS_E1x(bp) (CHIP_IS_E1((bp)) || CHIP_IS_E1H((bp))) 1021 #define USES_WARPCORE(bp) (CHIP_IS_E3(bp)) 1022 #define IS_E1H_OFFSET (!CHIP_IS_E1(bp)) 1023 1024 #define CHIP_REV_SHIFT 12 1025 #define CHIP_REV_MASK (0xF << CHIP_REV_SHIFT) 1026 #define CHIP_REV_VAL(bp) (bp->common.chip_id & CHIP_REV_MASK) 1027 #define CHIP_REV_Ax (0x0 << CHIP_REV_SHIFT) 1028 #define CHIP_REV_Bx (0x1 << CHIP_REV_SHIFT) 1029 /* assume maximum 5 revisions */ 1030 #define CHIP_REV_IS_SLOW(bp) (CHIP_REV_VAL(bp) > 0x00005000) 1031 /* Emul versions are A=>0xe, B=>0xc, C=>0xa, D=>8, E=>6 */ 1032 #define CHIP_REV_IS_EMUL(bp) ((CHIP_REV_IS_SLOW(bp)) && \ 1033 !(CHIP_REV_VAL(bp) & 0x00001000)) 1034 /* FPGA versions are A=>0xf, B=>0xd, C=>0xb, D=>9, E=>7 */ 1035 #define CHIP_REV_IS_FPGA(bp) ((CHIP_REV_IS_SLOW(bp)) && \ 1036 (CHIP_REV_VAL(bp) & 0x00001000)) 1037 1038 #define CHIP_TIME(bp) ((CHIP_REV_IS_EMUL(bp)) ? 2000 : \ 1039 ((CHIP_REV_IS_FPGA(bp)) ? 200 : 1)) 1040 1041 #define CHIP_METAL(bp) (bp->common.chip_id & 0x00000ff0) 1042 #define CHIP_BOND_ID(bp) (bp->common.chip_id & 0x0000000f) 1043 #define CHIP_REV_SIM(bp) (((CHIP_REV_MASK - CHIP_REV_VAL(bp)) >>\ 1044 (CHIP_REV_SHIFT + 1)) \ 1045 << CHIP_REV_SHIFT) 1046 #define CHIP_REV(bp) (CHIP_REV_IS_SLOW(bp) ? \ 1047 CHIP_REV_SIM(bp) :\ 1048 CHIP_REV_VAL(bp)) 1049 #define CHIP_IS_E3B0(bp) (CHIP_IS_E3(bp) && \ 1050 (CHIP_REV(bp) == CHIP_REV_Bx)) 1051 #define CHIP_IS_E3A0(bp) (CHIP_IS_E3(bp) && \ 1052 (CHIP_REV(bp) == CHIP_REV_Ax)) 1053 /* This define is used in two main places: 1054 * 1. In the early stages of nic_load, to know if to configure Parser / Searcher 1055 * to nic-only mode or to offload mode. Offload mode is configured if either the 1056 * chip is E1x (where MIC_MODE register is not applicable), or if cnic already 1057 * registered for this port (which means that the user wants storage services). 1058 * 2. During cnic-related load, to know if offload mode is already configured in 1059 * the HW or needs to be configured. 1060 * Since the transition from nic-mode to offload-mode in HW causes traffic 1061 * corruption, nic-mode is configured only in ports on which storage services 1062 * where never requested. 1063 */ 1064 #define CONFIGURE_NIC_MODE(bp) (!CHIP_IS_E1x(bp) && !CNIC_ENABLED(bp)) 1065 1066 int flash_size; 1067 #define BNX2X_NVRAM_1MB_SIZE 0x20000 /* 1M bit in bytes */ 1068 #define BNX2X_NVRAM_TIMEOUT_COUNT 30000 1069 #define BNX2X_NVRAM_PAGE_SIZE 256 1070 1071 u32 shmem_base; 1072 u32 shmem2_base; 1073 u32 mf_cfg_base; 1074 u32 mf2_cfg_base; 1075 1076 u32 hw_config; 1077 1078 u32 bc_ver; 1079 1080 u8 int_block; 1081 #define INT_BLOCK_HC 0 1082 #define INT_BLOCK_IGU 1 1083 #define INT_BLOCK_MODE_NORMAL 0 1084 #define INT_BLOCK_MODE_BW_COMP 2 1085 #define CHIP_INT_MODE_IS_NBC(bp) \ 1086 (!CHIP_IS_E1x(bp) && \ 1087 !((bp)->common.int_block & INT_BLOCK_MODE_BW_COMP)) 1088 #define CHIP_INT_MODE_IS_BC(bp) (!CHIP_INT_MODE_IS_NBC(bp)) 1089 1090 u8 chip_port_mode; 1091 #define CHIP_4_PORT_MODE 0x0 1092 #define CHIP_2_PORT_MODE 0x1 1093 #define CHIP_PORT_MODE_NONE 0x2 1094 #define CHIP_MODE(bp) (bp->common.chip_port_mode) 1095 #define CHIP_MODE_IS_4_PORT(bp) (CHIP_MODE(bp) == CHIP_4_PORT_MODE) 1096 1097 u32 boot_mode; 1098 }; 1099 1100 /* IGU MSIX STATISTICS on 57712: 64 for VFs; 4 for PFs; 4 for Attentions */ 1101 #define BNX2X_IGU_STAS_MSG_VF_CNT 64 1102 #define BNX2X_IGU_STAS_MSG_PF_CNT 4 1103 1104 #define MAX_IGU_ATTN_ACK_TO 100 1105 /* end of common */ 1106 1107 /* port */ 1108 1109 struct bnx2x_port { 1110 u32 pmf; 1111 1112 u32 link_config[LINK_CONFIG_SIZE]; 1113 1114 u32 supported[LINK_CONFIG_SIZE]; 1115 1116 u32 advertising[LINK_CONFIG_SIZE]; 1117 1118 u32 phy_addr; 1119 1120 /* used to synchronize phy accesses */ 1121 struct mutex phy_mutex; 1122 1123 u32 port_stx; 1124 1125 struct nig_stats old_nig_stats; 1126 }; 1127 1128 /* end of port */ 1129 1130 #define STATS_OFFSET32(stat_name) \ 1131 (offsetof(struct bnx2x_eth_stats, stat_name) / 4) 1132 1133 /* slow path */ 1134 #define BNX2X_MAX_NUM_OF_VFS 64 1135 #define BNX2X_VF_CID_WND 4 /* log num of queues per VF. HW config. */ 1136 #define BNX2X_CIDS_PER_VF (1 << BNX2X_VF_CID_WND) 1137 1138 /* We need to reserve doorbell addresses for all VF and queue combinations */ 1139 #define BNX2X_VF_CIDS (BNX2X_MAX_NUM_OF_VFS * BNX2X_CIDS_PER_VF) 1140 1141 /* The doorbell is configured to have the same number of CIDs for PFs and for 1142 * VFs. For this reason the PF CID zone is as large as the VF zone. 1143 */ 1144 #define BNX2X_FIRST_VF_CID BNX2X_VF_CIDS 1145 #define BNX2X_MAX_NUM_VF_QUEUES 64 1146 #define BNX2X_VF_ID_INVALID 0xFF 1147 1148 /* the number of VF CIDS multiplied by the amount of bytes reserved for each 1149 * cid must not exceed the size of the VF doorbell 1150 */ 1151 #define BNX2X_VF_BAR_SIZE 512 1152 #if (BNX2X_VF_BAR_SIZE < BNX2X_CIDS_PER_VF * (1 << BNX2X_DB_SHIFT)) 1153 #error "VF doorbell bar size is 512" 1154 #endif 1155 1156 /* 1157 * The total number of L2 queues, MSIX vectors and HW contexts (CIDs) is 1158 * control by the number of fast-path status blocks supported by the 1159 * device (HW/FW). Each fast-path status block (FP-SB) aka non-default 1160 * status block represents an independent interrupts context that can 1161 * serve a regular L2 networking queue. However special L2 queues such 1162 * as the FCoE queue do not require a FP-SB and other components like 1163 * the CNIC may consume FP-SB reducing the number of possible L2 queues 1164 * 1165 * If the maximum number of FP-SB available is X then: 1166 * a. If CNIC is supported it consumes 1 FP-SB thus the max number of 1167 * regular L2 queues is Y=X-1 1168 * b. In MF mode the actual number of L2 queues is Y= (X-1/MF_factor) 1169 * c. If the FCoE L2 queue is supported the actual number of L2 queues 1170 * is Y+1 1171 * d. The number of irqs (MSIX vectors) is either Y+1 (one extra for 1172 * slow-path interrupts) or Y+2 if CNIC is supported (one additional 1173 * FP interrupt context for the CNIC). 1174 * e. The number of HW context (CID count) is always X or X+1 if FCoE 1175 * L2 queue is supported. The cid for the FCoE L2 queue is always X. 1176 */ 1177 1178 /* fast-path interrupt contexts E1x */ 1179 #define FP_SB_MAX_E1x 16 1180 /* fast-path interrupt contexts E2 */ 1181 #define FP_SB_MAX_E2 HC_SB_MAX_SB_E2 1182 1183 union cdu_context { 1184 struct eth_context eth; 1185 char pad[1024]; 1186 }; 1187 1188 /* CDU host DB constants */ 1189 #define CDU_ILT_PAGE_SZ_HW 2 1190 #define CDU_ILT_PAGE_SZ (8192 << CDU_ILT_PAGE_SZ_HW) /* 32K */ 1191 #define ILT_PAGE_CIDS (CDU_ILT_PAGE_SZ / sizeof(union cdu_context)) 1192 1193 #define CNIC_ISCSI_CID_MAX 256 1194 #define CNIC_FCOE_CID_MAX 2048 1195 #define CNIC_CID_MAX (CNIC_ISCSI_CID_MAX + CNIC_FCOE_CID_MAX) 1196 #define CNIC_ILT_LINES DIV_ROUND_UP(CNIC_CID_MAX, ILT_PAGE_CIDS) 1197 1198 #define QM_ILT_PAGE_SZ_HW 0 1199 #define QM_ILT_PAGE_SZ (4096 << QM_ILT_PAGE_SZ_HW) /* 4K */ 1200 #define QM_CID_ROUND 1024 1201 1202 /* TM (timers) host DB constants */ 1203 #define TM_ILT_PAGE_SZ_HW 0 1204 #define TM_ILT_PAGE_SZ (4096 << TM_ILT_PAGE_SZ_HW) /* 4K */ 1205 #define TM_CONN_NUM (BNX2X_FIRST_VF_CID + \ 1206 BNX2X_VF_CIDS + \ 1207 CNIC_ISCSI_CID_MAX) 1208 #define TM_ILT_SZ (8 * TM_CONN_NUM) 1209 #define TM_ILT_LINES DIV_ROUND_UP(TM_ILT_SZ, TM_ILT_PAGE_SZ) 1210 1211 /* SRC (Searcher) host DB constants */ 1212 #define SRC_ILT_PAGE_SZ_HW 0 1213 #define SRC_ILT_PAGE_SZ (4096 << SRC_ILT_PAGE_SZ_HW) /* 4K */ 1214 #define SRC_HASH_BITS 10 1215 #define SRC_CONN_NUM (1 << SRC_HASH_BITS) /* 1024 */ 1216 #define SRC_ILT_SZ (sizeof(struct src_ent) * SRC_CONN_NUM) 1217 #define SRC_T2_SZ SRC_ILT_SZ 1218 #define SRC_ILT_LINES DIV_ROUND_UP(SRC_ILT_SZ, SRC_ILT_PAGE_SZ) 1219 1220 #define MAX_DMAE_C 8 1221 1222 /* DMA memory not used in fastpath */ 1223 struct bnx2x_slowpath { 1224 union { 1225 struct mac_configuration_cmd e1x; 1226 struct eth_classify_rules_ramrod_data e2; 1227 } mac_rdata; 1228 1229 union { 1230 struct tstorm_eth_mac_filter_config e1x; 1231 struct eth_filter_rules_ramrod_data e2; 1232 } rx_mode_rdata; 1233 1234 union { 1235 struct mac_configuration_cmd e1; 1236 struct eth_multicast_rules_ramrod_data e2; 1237 } mcast_rdata; 1238 1239 struct eth_rss_update_ramrod_data rss_rdata; 1240 1241 /* Queue State related ramrods are always sent under rtnl_lock */ 1242 union { 1243 struct client_init_ramrod_data init_data; 1244 struct client_update_ramrod_data update_data; 1245 struct tpa_update_ramrod_data tpa_data; 1246 } q_rdata; 1247 1248 union { 1249 struct function_start_data func_start; 1250 /* pfc configuration for DCBX ramrod */ 1251 struct flow_control_configuration pfc_config; 1252 } func_rdata; 1253 1254 /* afex ramrod can not be a part of func_rdata union because these 1255 * events might arrive in parallel to other events from func_rdata. 1256 * Therefore, if they would have been defined in the same union, 1257 * data can get corrupted. 1258 */ 1259 union { 1260 struct afex_vif_list_ramrod_data viflist_data; 1261 struct function_update_data func_update; 1262 } func_afex_rdata; 1263 1264 /* used by dmae command executer */ 1265 struct dmae_command dmae[MAX_DMAE_C]; 1266 1267 u32 stats_comp; 1268 union mac_stats mac_stats; 1269 struct nig_stats nig_stats; 1270 struct host_port_stats port_stats; 1271 struct host_func_stats func_stats; 1272 1273 u32 wb_comp; 1274 u32 wb_data[4]; 1275 1276 union drv_info_to_mcp drv_info_to_mcp; 1277 }; 1278 1279 #define bnx2x_sp(bp, var) (&bp->slowpath->var) 1280 #define bnx2x_sp_mapping(bp, var) \ 1281 (bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var)) 1282 1283 /* attn group wiring */ 1284 #define MAX_DYNAMIC_ATTN_GRPS 8 1285 1286 struct attn_route { 1287 u32 sig[5]; 1288 }; 1289 1290 struct iro { 1291 u32 base; 1292 u16 m1; 1293 u16 m2; 1294 u16 m3; 1295 u16 size; 1296 }; 1297 1298 struct hw_context { 1299 union cdu_context *vcxt; 1300 dma_addr_t cxt_mapping; 1301 size_t size; 1302 }; 1303 1304 /* forward */ 1305 struct bnx2x_ilt; 1306 1307 struct bnx2x_vfdb; 1308 1309 enum bnx2x_recovery_state { 1310 BNX2X_RECOVERY_DONE, 1311 BNX2X_RECOVERY_INIT, 1312 BNX2X_RECOVERY_WAIT, 1313 BNX2X_RECOVERY_FAILED, 1314 BNX2X_RECOVERY_NIC_LOADING 1315 }; 1316 1317 /* 1318 * Event queue (EQ or event ring) MC hsi 1319 * NUM_EQ_PAGES and EQ_DESC_CNT_PAGE must be power of 2 1320 */ 1321 #define NUM_EQ_PAGES 1 1322 #define EQ_DESC_CNT_PAGE (BCM_PAGE_SIZE / sizeof(union event_ring_elem)) 1323 #define EQ_DESC_MAX_PAGE (EQ_DESC_CNT_PAGE - 1) 1324 #define NUM_EQ_DESC (EQ_DESC_CNT_PAGE * NUM_EQ_PAGES) 1325 #define EQ_DESC_MASK (NUM_EQ_DESC - 1) 1326 #define MAX_EQ_AVAIL (EQ_DESC_MAX_PAGE * NUM_EQ_PAGES - 2) 1327 1328 /* depends on EQ_DESC_CNT_PAGE being a power of 2 */ 1329 #define NEXT_EQ_IDX(x) ((((x) & EQ_DESC_MAX_PAGE) == \ 1330 (EQ_DESC_MAX_PAGE - 1)) ? (x) + 2 : (x) + 1) 1331 1332 /* depends on the above and on NUM_EQ_PAGES being a power of 2 */ 1333 #define EQ_DESC(x) ((x) & EQ_DESC_MASK) 1334 1335 #define BNX2X_EQ_INDEX \ 1336 (&bp->def_status_blk->sp_sb.\ 1337 index_values[HC_SP_INDEX_EQ_CONS]) 1338 1339 /* This is a data that will be used to create a link report message. 1340 * We will keep the data used for the last link report in order 1341 * to prevent reporting the same link parameters twice. 1342 */ 1343 struct bnx2x_link_report_data { 1344 u16 line_speed; /* Effective line speed */ 1345 unsigned long link_report_flags;/* BNX2X_LINK_REPORT_XXX flags */ 1346 }; 1347 1348 enum { 1349 BNX2X_LINK_REPORT_FD, /* Full DUPLEX */ 1350 BNX2X_LINK_REPORT_LINK_DOWN, 1351 BNX2X_LINK_REPORT_RX_FC_ON, 1352 BNX2X_LINK_REPORT_TX_FC_ON, 1353 }; 1354 1355 enum { 1356 BNX2X_PORT_QUERY_IDX, 1357 BNX2X_PF_QUERY_IDX, 1358 BNX2X_FCOE_QUERY_IDX, 1359 BNX2X_FIRST_QUEUE_QUERY_IDX, 1360 }; 1361 1362 struct bnx2x_fw_stats_req { 1363 struct stats_query_header hdr; 1364 struct stats_query_entry query[FP_SB_MAX_E1x+ 1365 BNX2X_FIRST_QUEUE_QUERY_IDX]; 1366 }; 1367 1368 struct bnx2x_fw_stats_data { 1369 struct stats_counter storm_counters; 1370 struct per_port_stats port; 1371 struct per_pf_stats pf; 1372 struct fcoe_statistics_params fcoe; 1373 struct per_queue_stats queue_stats[1]; 1374 }; 1375 1376 /* Public slow path states */ 1377 enum sp_rtnl_flag { 1378 BNX2X_SP_RTNL_SETUP_TC, 1379 BNX2X_SP_RTNL_TX_TIMEOUT, 1380 BNX2X_SP_RTNL_FAN_FAILURE, 1381 BNX2X_SP_RTNL_AFEX_F_UPDATE, 1382 BNX2X_SP_RTNL_ENABLE_SRIOV, 1383 BNX2X_SP_RTNL_VFPF_MCAST, 1384 BNX2X_SP_RTNL_VFPF_CHANNEL_DOWN, 1385 BNX2X_SP_RTNL_RX_MODE, 1386 BNX2X_SP_RTNL_HYPERVISOR_VLAN, 1387 BNX2X_SP_RTNL_TX_STOP, 1388 BNX2X_SP_RTNL_GET_DRV_VERSION, 1389 }; 1390 1391 enum bnx2x_iov_flag { 1392 BNX2X_IOV_HANDLE_VF_MSG, 1393 BNX2X_IOV_HANDLE_FLR, 1394 }; 1395 1396 struct bnx2x_prev_path_list { 1397 struct list_head list; 1398 u8 bus; 1399 u8 slot; 1400 u8 path; 1401 u8 aer; 1402 u8 undi; 1403 }; 1404 1405 struct bnx2x_sp_objs { 1406 /* MACs object */ 1407 struct bnx2x_vlan_mac_obj mac_obj; 1408 1409 /* Queue State object */ 1410 struct bnx2x_queue_sp_obj q_obj; 1411 }; 1412 1413 struct bnx2x_fp_stats { 1414 struct tstorm_per_queue_stats old_tclient; 1415 struct ustorm_per_queue_stats old_uclient; 1416 struct xstorm_per_queue_stats old_xclient; 1417 struct bnx2x_eth_q_stats eth_q_stats; 1418 struct bnx2x_eth_q_stats_old eth_q_stats_old; 1419 }; 1420 1421 enum { 1422 SUB_MF_MODE_UNKNOWN = 0, 1423 SUB_MF_MODE_UFP, 1424 SUB_MF_MODE_NPAR1_DOT_5, 1425 }; 1426 1427 struct bnx2x { 1428 /* Fields used in the tx and intr/napi performance paths 1429 * are grouped together in the beginning of the structure 1430 */ 1431 struct bnx2x_fastpath *fp; 1432 struct bnx2x_sp_objs *sp_objs; 1433 struct bnx2x_fp_stats *fp_stats; 1434 struct bnx2x_fp_txdata *bnx2x_txq; 1435 void __iomem *regview; 1436 void __iomem *doorbells; 1437 u16 db_size; 1438 1439 u8 pf_num; /* absolute PF number */ 1440 u8 pfid; /* per-path PF number */ 1441 int base_fw_ndsb; /**/ 1442 #define BP_PATH(bp) (CHIP_IS_E1x(bp) ? 0 : (bp->pf_num & 1)) 1443 #define BP_PORT(bp) (bp->pfid & 1) 1444 #define BP_FUNC(bp) (bp->pfid) 1445 #define BP_ABS_FUNC(bp) (bp->pf_num) 1446 #define BP_VN(bp) ((bp)->pfid >> 1) 1447 #define BP_MAX_VN_NUM(bp) (CHIP_MODE_IS_4_PORT(bp) ? 2 : 4) 1448 #define BP_L_ID(bp) (BP_VN(bp) << 2) 1449 #define BP_FW_MB_IDX_VN(bp, vn) (BP_PORT(bp) +\ 1450 (vn) * ((CHIP_IS_E1x(bp) || (CHIP_MODE_IS_4_PORT(bp))) ? 2 : 1)) 1451 #define BP_FW_MB_IDX(bp) BP_FW_MB_IDX_VN(bp, BP_VN(bp)) 1452 1453 #ifdef CONFIG_BNX2X_SRIOV 1454 /* protects vf2pf mailbox from simultaneous access */ 1455 struct mutex vf2pf_mutex; 1456 /* vf pf channel mailbox contains request and response buffers */ 1457 struct bnx2x_vf_mbx_msg *vf2pf_mbox; 1458 dma_addr_t vf2pf_mbox_mapping; 1459 1460 /* we set aside a copy of the acquire response */ 1461 struct pfvf_acquire_resp_tlv acquire_resp; 1462 1463 /* bulletin board for messages from pf to vf */ 1464 union pf_vf_bulletin *pf2vf_bulletin; 1465 dma_addr_t pf2vf_bulletin_mapping; 1466 1467 union pf_vf_bulletin shadow_bulletin; 1468 struct pf_vf_bulletin_content old_bulletin; 1469 1470 u16 requested_nr_virtfn; 1471 #endif /* CONFIG_BNX2X_SRIOV */ 1472 1473 struct net_device *dev; 1474 struct pci_dev *pdev; 1475 1476 const struct iro *iro_arr; 1477 #define IRO (bp->iro_arr) 1478 1479 enum bnx2x_recovery_state recovery_state; 1480 int is_leader; 1481 struct msix_entry *msix_table; 1482 1483 int tx_ring_size; 1484 1485 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */ 1486 #define ETH_OVREHEAD (ETH_HLEN + 8 + 8) 1487 #define ETH_MIN_PACKET_SIZE 60 1488 #define ETH_MAX_PACKET_SIZE 1500 1489 #define ETH_MAX_JUMBO_PACKET_SIZE 9600 1490 /* TCP with Timestamp Option (32) + IPv6 (40) */ 1491 #define ETH_MAX_TPA_HEADER_SIZE 72 1492 1493 /* Max supported alignment is 256 (8 shift) 1494 * minimal alignment shift 6 is optimal for 57xxx HW performance 1495 */ 1496 #define BNX2X_RX_ALIGN_SHIFT max(6, min(8, L1_CACHE_SHIFT)) 1497 1498 /* FW uses 2 Cache lines Alignment for start packet and size 1499 * 1500 * We assume skb_build() uses sizeof(struct skb_shared_info) bytes 1501 * at the end of skb->data, to avoid wasting a full cache line. 1502 * This reduces memory use (skb->truesize). 1503 */ 1504 #define BNX2X_FW_RX_ALIGN_START (1UL << BNX2X_RX_ALIGN_SHIFT) 1505 1506 #define BNX2X_FW_RX_ALIGN_END \ 1507 max_t(u64, 1UL << BNX2X_RX_ALIGN_SHIFT, \ 1508 SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) 1509 1510 #define BNX2X_PXP_DRAM_ALIGN (BNX2X_RX_ALIGN_SHIFT - 5) 1511 1512 struct host_sp_status_block *def_status_blk; 1513 #define DEF_SB_IGU_ID 16 1514 #define DEF_SB_ID HC_SP_SB_ID 1515 __le16 def_idx; 1516 __le16 def_att_idx; 1517 u32 attn_state; 1518 struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS]; 1519 1520 /* slow path ring */ 1521 struct eth_spe *spq; 1522 dma_addr_t spq_mapping; 1523 u16 spq_prod_idx; 1524 struct eth_spe *spq_prod_bd; 1525 struct eth_spe *spq_last_bd; 1526 __le16 *dsb_sp_prod; 1527 atomic_t cq_spq_left; /* ETH_XXX ramrods credit */ 1528 /* used to synchronize spq accesses */ 1529 spinlock_t spq_lock; 1530 1531 /* event queue */ 1532 union event_ring_elem *eq_ring; 1533 dma_addr_t eq_mapping; 1534 u16 eq_prod; 1535 u16 eq_cons; 1536 __le16 *eq_cons_sb; 1537 atomic_t eq_spq_left; /* COMMON_XXX ramrods credit */ 1538 1539 /* Counter for marking that there is a STAT_QUERY ramrod pending */ 1540 u16 stats_pending; 1541 /* Counter for completed statistics ramrods */ 1542 u16 stats_comp; 1543 1544 /* End of fields used in the performance code paths */ 1545 1546 int panic; 1547 int msg_enable; 1548 1549 u32 flags; 1550 #define PCIX_FLAG (1 << 0) 1551 #define PCI_32BIT_FLAG (1 << 1) 1552 #define ONE_PORT_FLAG (1 << 2) 1553 #define NO_WOL_FLAG (1 << 3) 1554 #define USING_MSIX_FLAG (1 << 5) 1555 #define USING_MSI_FLAG (1 << 6) 1556 #define DISABLE_MSI_FLAG (1 << 7) 1557 #define NO_MCP_FLAG (1 << 9) 1558 #define MF_FUNC_DIS (1 << 11) 1559 #define OWN_CNIC_IRQ (1 << 12) 1560 #define NO_ISCSI_OOO_FLAG (1 << 13) 1561 #define NO_ISCSI_FLAG (1 << 14) 1562 #define NO_FCOE_FLAG (1 << 15) 1563 #define BC_SUPPORTS_PFC_STATS (1 << 17) 1564 #define TX_SWITCHING (1 << 18) 1565 #define BC_SUPPORTS_FCOE_FEATURES (1 << 19) 1566 #define USING_SINGLE_MSIX_FLAG (1 << 20) 1567 #define BC_SUPPORTS_DCBX_MSG_NON_PMF (1 << 21) 1568 #define IS_VF_FLAG (1 << 22) 1569 #define BC_SUPPORTS_RMMOD_CMD (1 << 23) 1570 #define HAS_PHYS_PORT_ID (1 << 24) 1571 #define AER_ENABLED (1 << 25) 1572 #define PTP_SUPPORTED (1 << 26) 1573 #define TX_TIMESTAMPING_EN (1 << 27) 1574 1575 #define BP_NOMCP(bp) ((bp)->flags & NO_MCP_FLAG) 1576 1577 #ifdef CONFIG_BNX2X_SRIOV 1578 #define IS_VF(bp) ((bp)->flags & IS_VF_FLAG) 1579 #define IS_PF(bp) (!((bp)->flags & IS_VF_FLAG)) 1580 #else 1581 #define IS_VF(bp) false 1582 #define IS_PF(bp) true 1583 #endif 1584 1585 #define NO_ISCSI(bp) ((bp)->flags & NO_ISCSI_FLAG) 1586 #define NO_ISCSI_OOO(bp) ((bp)->flags & NO_ISCSI_OOO_FLAG) 1587 #define NO_FCOE(bp) ((bp)->flags & NO_FCOE_FLAG) 1588 1589 u8 cnic_support; 1590 bool cnic_enabled; 1591 bool cnic_loaded; 1592 struct cnic_eth_dev *(*cnic_probe)(struct net_device *); 1593 1594 /* Flag that indicates that we can start looking for FCoE L2 queue 1595 * completions in the default status block. 1596 */ 1597 bool fcoe_init; 1598 1599 int mrrs; 1600 1601 struct delayed_work sp_task; 1602 struct delayed_work iov_task; 1603 1604 atomic_t interrupt_occurred; 1605 struct delayed_work sp_rtnl_task; 1606 1607 struct delayed_work period_task; 1608 struct timer_list timer; 1609 int current_interval; 1610 1611 u16 fw_seq; 1612 u16 fw_drv_pulse_wr_seq; 1613 u32 func_stx; 1614 1615 struct link_params link_params; 1616 struct link_vars link_vars; 1617 u32 link_cnt; 1618 struct bnx2x_link_report_data last_reported_link; 1619 1620 struct mdio_if_info mdio; 1621 1622 struct bnx2x_common common; 1623 struct bnx2x_port port; 1624 1625 struct cmng_init cmng; 1626 1627 u32 mf_config[E1HVN_MAX]; 1628 u32 mf_ext_config; 1629 u32 path_has_ovlan; /* E3 */ 1630 u16 mf_ov; 1631 u8 mf_mode; 1632 #define IS_MF(bp) (bp->mf_mode != 0) 1633 #define IS_MF_SI(bp) (bp->mf_mode == MULTI_FUNCTION_SI) 1634 #define IS_MF_SD(bp) (bp->mf_mode == MULTI_FUNCTION_SD) 1635 #define IS_MF_AFEX(bp) (bp->mf_mode == MULTI_FUNCTION_AFEX) 1636 u8 mf_sub_mode; 1637 #define IS_MF_UFP(bp) (IS_MF_SD(bp) && \ 1638 bp->mf_sub_mode == SUB_MF_MODE_UFP) 1639 1640 u8 wol; 1641 1642 int rx_ring_size; 1643 1644 u16 tx_quick_cons_trip_int; 1645 u16 tx_quick_cons_trip; 1646 u16 tx_ticks_int; 1647 u16 tx_ticks; 1648 1649 u16 rx_quick_cons_trip_int; 1650 u16 rx_quick_cons_trip; 1651 u16 rx_ticks_int; 1652 u16 rx_ticks; 1653 /* Maximal coalescing timeout in us */ 1654 #define BNX2X_MAX_COALESCE_TOUT (0xff*BNX2X_BTR) 1655 1656 u32 lin_cnt; 1657 1658 u16 state; 1659 #define BNX2X_STATE_CLOSED 0 1660 #define BNX2X_STATE_OPENING_WAIT4_LOAD 0x1000 1661 #define BNX2X_STATE_OPENING_WAIT4_PORT 0x2000 1662 #define BNX2X_STATE_OPEN 0x3000 1663 #define BNX2X_STATE_CLOSING_WAIT4_HALT 0x4000 1664 #define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000 1665 1666 #define BNX2X_STATE_DIAG 0xe000 1667 #define BNX2X_STATE_ERROR 0xf000 1668 1669 #define BNX2X_MAX_PRIORITY 8 1670 int num_queues; 1671 uint num_ethernet_queues; 1672 uint num_cnic_queues; 1673 int disable_tpa; 1674 1675 u32 rx_mode; 1676 #define BNX2X_RX_MODE_NONE 0 1677 #define BNX2X_RX_MODE_NORMAL 1 1678 #define BNX2X_RX_MODE_ALLMULTI 2 1679 #define BNX2X_RX_MODE_PROMISC 3 1680 #define BNX2X_MAX_MULTICAST 64 1681 1682 u8 igu_dsb_id; 1683 u8 igu_base_sb; 1684 u8 igu_sb_cnt; 1685 u8 min_msix_vec_cnt; 1686 1687 u32 igu_base_addr; 1688 dma_addr_t def_status_blk_mapping; 1689 1690 struct bnx2x_slowpath *slowpath; 1691 dma_addr_t slowpath_mapping; 1692 1693 /* Mechanism protecting the drv_info_to_mcp */ 1694 struct mutex drv_info_mutex; 1695 bool drv_info_mng_owner; 1696 1697 /* Total number of FW statistics requests */ 1698 u8 fw_stats_num; 1699 1700 /* 1701 * This is a memory buffer that will contain both statistics 1702 * ramrod request and data. 1703 */ 1704 void *fw_stats; 1705 dma_addr_t fw_stats_mapping; 1706 1707 /* 1708 * FW statistics request shortcut (points at the 1709 * beginning of fw_stats buffer). 1710 */ 1711 struct bnx2x_fw_stats_req *fw_stats_req; 1712 dma_addr_t fw_stats_req_mapping; 1713 int fw_stats_req_sz; 1714 1715 /* 1716 * FW statistics data shortcut (points at the beginning of 1717 * fw_stats buffer + fw_stats_req_sz). 1718 */ 1719 struct bnx2x_fw_stats_data *fw_stats_data; 1720 dma_addr_t fw_stats_data_mapping; 1721 int fw_stats_data_sz; 1722 1723 /* For max 1024 cids (VF RSS), 32KB ILT page size and 1KB 1724 * context size we need 8 ILT entries. 1725 */ 1726 #define ILT_MAX_L2_LINES 32 1727 struct hw_context context[ILT_MAX_L2_LINES]; 1728 1729 struct bnx2x_ilt *ilt; 1730 #define BP_ILT(bp) ((bp)->ilt) 1731 #define ILT_MAX_LINES 256 1732 /* 1733 * Maximum supported number of RSS queues: number of IGU SBs minus one that goes 1734 * to CNIC. 1735 */ 1736 #define BNX2X_MAX_RSS_COUNT(bp) ((bp)->igu_sb_cnt - CNIC_SUPPORT(bp)) 1737 1738 /* 1739 * Maximum CID count that might be required by the bnx2x: 1740 * Max RSS * Max_Tx_Multi_Cos + FCoE + iSCSI 1741 */ 1742 1743 #define BNX2X_L2_CID_COUNT(bp) (BNX2X_NUM_ETH_QUEUES(bp) * BNX2X_MULTI_TX_COS \ 1744 + CNIC_SUPPORT(bp) * (2 + UIO_CID_PAD(bp))) 1745 #define BNX2X_L2_MAX_CID(bp) (BNX2X_MAX_RSS_COUNT(bp) * BNX2X_MULTI_TX_COS \ 1746 + CNIC_SUPPORT(bp) * (2 + UIO_CID_PAD(bp))) 1747 #define L2_ILT_LINES(bp) (DIV_ROUND_UP(BNX2X_L2_CID_COUNT(bp),\ 1748 ILT_PAGE_CIDS)) 1749 1750 int qm_cid_count; 1751 1752 bool dropless_fc; 1753 1754 void *t2; 1755 dma_addr_t t2_mapping; 1756 struct cnic_ops __rcu *cnic_ops; 1757 void *cnic_data; 1758 u32 cnic_tag; 1759 struct cnic_eth_dev cnic_eth_dev; 1760 union host_hc_status_block cnic_sb; 1761 dma_addr_t cnic_sb_mapping; 1762 struct eth_spe *cnic_kwq; 1763 struct eth_spe *cnic_kwq_prod; 1764 struct eth_spe *cnic_kwq_cons; 1765 struct eth_spe *cnic_kwq_last; 1766 u16 cnic_kwq_pending; 1767 u16 cnic_spq_pending; 1768 u8 fip_mac[ETH_ALEN]; 1769 struct mutex cnic_mutex; 1770 struct bnx2x_vlan_mac_obj iscsi_l2_mac_obj; 1771 1772 /* Start index of the "special" (CNIC related) L2 clients */ 1773 u8 cnic_base_cl_id; 1774 1775 int dmae_ready; 1776 /* used to synchronize dmae accesses */ 1777 spinlock_t dmae_lock; 1778 1779 /* used to protect the FW mail box */ 1780 struct mutex fw_mb_mutex; 1781 1782 /* used to synchronize stats collecting */ 1783 int stats_state; 1784 1785 /* used for synchronization of concurrent threads statistics handling */ 1786 struct semaphore stats_lock; 1787 1788 /* used by dmae command loader */ 1789 struct dmae_command stats_dmae; 1790 int executer_idx; 1791 1792 u16 stats_counter; 1793 struct bnx2x_eth_stats eth_stats; 1794 struct host_func_stats func_stats; 1795 struct bnx2x_eth_stats_old eth_stats_old; 1796 struct bnx2x_net_stats_old net_stats_old; 1797 struct bnx2x_fw_port_stats_old fw_stats_old; 1798 bool stats_init; 1799 1800 struct z_stream_s *strm; 1801 void *gunzip_buf; 1802 dma_addr_t gunzip_mapping; 1803 int gunzip_outlen; 1804 #define FW_BUF_SIZE 0x8000 1805 #define GUNZIP_BUF(bp) (bp->gunzip_buf) 1806 #define GUNZIP_PHYS(bp) (bp->gunzip_mapping) 1807 #define GUNZIP_OUTLEN(bp) (bp->gunzip_outlen) 1808 1809 struct raw_op *init_ops; 1810 /* Init blocks offsets inside init_ops */ 1811 u16 *init_ops_offsets; 1812 /* Data blob - has 32 bit granularity */ 1813 u32 *init_data; 1814 u32 init_mode_flags; 1815 #define INIT_MODE_FLAGS(bp) (bp->init_mode_flags) 1816 /* Zipped PRAM blobs - raw data */ 1817 const u8 *tsem_int_table_data; 1818 const u8 *tsem_pram_data; 1819 const u8 *usem_int_table_data; 1820 const u8 *usem_pram_data; 1821 const u8 *xsem_int_table_data; 1822 const u8 *xsem_pram_data; 1823 const u8 *csem_int_table_data; 1824 const u8 *csem_pram_data; 1825 #define INIT_OPS(bp) (bp->init_ops) 1826 #define INIT_OPS_OFFSETS(bp) (bp->init_ops_offsets) 1827 #define INIT_DATA(bp) (bp->init_data) 1828 #define INIT_TSEM_INT_TABLE_DATA(bp) (bp->tsem_int_table_data) 1829 #define INIT_TSEM_PRAM_DATA(bp) (bp->tsem_pram_data) 1830 #define INIT_USEM_INT_TABLE_DATA(bp) (bp->usem_int_table_data) 1831 #define INIT_USEM_PRAM_DATA(bp) (bp->usem_pram_data) 1832 #define INIT_XSEM_INT_TABLE_DATA(bp) (bp->xsem_int_table_data) 1833 #define INIT_XSEM_PRAM_DATA(bp) (bp->xsem_pram_data) 1834 #define INIT_CSEM_INT_TABLE_DATA(bp) (bp->csem_int_table_data) 1835 #define INIT_CSEM_PRAM_DATA(bp) (bp->csem_pram_data) 1836 1837 #define PHY_FW_VER_LEN 20 1838 char fw_ver[32]; 1839 const struct firmware *firmware; 1840 1841 struct bnx2x_vfdb *vfdb; 1842 #define IS_SRIOV(bp) ((bp)->vfdb) 1843 1844 /* DCB support on/off */ 1845 u16 dcb_state; 1846 #define BNX2X_DCB_STATE_OFF 0 1847 #define BNX2X_DCB_STATE_ON 1 1848 1849 /* DCBX engine mode */ 1850 int dcbx_enabled; 1851 #define BNX2X_DCBX_ENABLED_OFF 0 1852 #define BNX2X_DCBX_ENABLED_ON_NEG_OFF 1 1853 #define BNX2X_DCBX_ENABLED_ON_NEG_ON 2 1854 #define BNX2X_DCBX_ENABLED_INVALID (-1) 1855 1856 bool dcbx_mode_uset; 1857 1858 struct bnx2x_config_dcbx_params dcbx_config_params; 1859 struct bnx2x_dcbx_port_params dcbx_port_params; 1860 int dcb_version; 1861 1862 /* CAM credit pools */ 1863 1864 /* used only in sriov */ 1865 struct bnx2x_credit_pool_obj vlans_pool; 1866 1867 struct bnx2x_credit_pool_obj macs_pool; 1868 1869 /* RX_MODE object */ 1870 struct bnx2x_rx_mode_obj rx_mode_obj; 1871 1872 /* MCAST object */ 1873 struct bnx2x_mcast_obj mcast_obj; 1874 1875 /* RSS configuration object */ 1876 struct bnx2x_rss_config_obj rss_conf_obj; 1877 1878 /* Function State controlling object */ 1879 struct bnx2x_func_sp_obj func_obj; 1880 1881 unsigned long sp_state; 1882 1883 /* operation indication for the sp_rtnl task */ 1884 unsigned long sp_rtnl_state; 1885 1886 /* Indication of the IOV tasks */ 1887 unsigned long iov_task_state; 1888 1889 /* DCBX Negotiation results */ 1890 struct dcbx_features dcbx_local_feat; 1891 u32 dcbx_error; 1892 1893 #ifdef BCM_DCBNL 1894 struct dcbx_features dcbx_remote_feat; 1895 u32 dcbx_remote_flags; 1896 #endif 1897 /* AFEX: store default vlan used */ 1898 int afex_def_vlan_tag; 1899 enum mf_cfg_afex_vlan_mode afex_vlan_mode; 1900 u32 pending_max; 1901 1902 /* multiple tx classes of service */ 1903 u8 max_cos; 1904 1905 /* priority to cos mapping */ 1906 u8 prio_to_cos[8]; 1907 1908 int fp_array_size; 1909 u32 dump_preset_idx; 1910 1911 u8 phys_port_id[ETH_ALEN]; 1912 1913 /* PTP related context */ 1914 struct ptp_clock *ptp_clock; 1915 struct ptp_clock_info ptp_clock_info; 1916 struct work_struct ptp_task; 1917 struct cyclecounter cyclecounter; 1918 struct timecounter timecounter; 1919 bool timecounter_init_done; 1920 struct sk_buff *ptp_tx_skb; 1921 unsigned long ptp_tx_start; 1922 bool hwtstamp_ioctl_called; 1923 u16 tx_type; 1924 u16 rx_filter; 1925 1926 struct bnx2x_link_report_data vf_link_vars; 1927 }; 1928 1929 /* Tx queues may be less or equal to Rx queues */ 1930 extern int num_queues; 1931 #define BNX2X_NUM_QUEUES(bp) (bp->num_queues) 1932 #define BNX2X_NUM_ETH_QUEUES(bp) ((bp)->num_ethernet_queues) 1933 #define BNX2X_NUM_NON_CNIC_QUEUES(bp) (BNX2X_NUM_QUEUES(bp) - \ 1934 (bp)->num_cnic_queues) 1935 #define BNX2X_NUM_RX_QUEUES(bp) BNX2X_NUM_QUEUES(bp) 1936 1937 #define is_multi(bp) (BNX2X_NUM_QUEUES(bp) > 1) 1938 1939 #define BNX2X_MAX_QUEUES(bp) BNX2X_MAX_RSS_COUNT(bp) 1940 /* #define is_eth_multi(bp) (BNX2X_NUM_ETH_QUEUES(bp) > 1) */ 1941 1942 #define RSS_IPV4_CAP_MASK \ 1943 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY 1944 1945 #define RSS_IPV4_TCP_CAP_MASK \ 1946 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY 1947 1948 #define RSS_IPV6_CAP_MASK \ 1949 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY 1950 1951 #define RSS_IPV6_TCP_CAP_MASK \ 1952 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY 1953 1954 /* func init flags */ 1955 #define FUNC_FLG_RSS 0x0001 1956 #define FUNC_FLG_STATS 0x0002 1957 /* removed FUNC_FLG_UNMATCHED 0x0004 */ 1958 #define FUNC_FLG_TPA 0x0008 1959 #define FUNC_FLG_SPQ 0x0010 1960 #define FUNC_FLG_LEADING 0x0020 /* PF only */ 1961 #define FUNC_FLG_LEADING_STATS 0x0040 1962 struct bnx2x_func_init_params { 1963 /* dma */ 1964 dma_addr_t fw_stat_map; /* valid iff FUNC_FLG_STATS */ 1965 dma_addr_t spq_map; /* valid iff FUNC_FLG_SPQ */ 1966 1967 u16 func_flgs; 1968 u16 func_id; /* abs fid */ 1969 u16 pf_id; 1970 u16 spq_prod; /* valid iff FUNC_FLG_SPQ */ 1971 }; 1972 1973 #define for_each_cnic_queue(bp, var) \ 1974 for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \ 1975 (var)++) \ 1976 if (skip_queue(bp, var)) \ 1977 continue; \ 1978 else 1979 1980 #define for_each_eth_queue(bp, var) \ 1981 for ((var) = 0; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++) 1982 1983 #define for_each_nondefault_eth_queue(bp, var) \ 1984 for ((var) = 1; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++) 1985 1986 #define for_each_queue(bp, var) \ 1987 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \ 1988 if (skip_queue(bp, var)) \ 1989 continue; \ 1990 else 1991 1992 /* Skip forwarding FP */ 1993 #define for_each_valid_rx_queue(bp, var) \ 1994 for ((var) = 0; \ 1995 (var) < (CNIC_LOADED(bp) ? BNX2X_NUM_QUEUES(bp) : \ 1996 BNX2X_NUM_ETH_QUEUES(bp)); \ 1997 (var)++) \ 1998 if (skip_rx_queue(bp, var)) \ 1999 continue; \ 2000 else 2001 2002 #define for_each_rx_queue_cnic(bp, var) \ 2003 for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \ 2004 (var)++) \ 2005 if (skip_rx_queue(bp, var)) \ 2006 continue; \ 2007 else 2008 2009 #define for_each_rx_queue(bp, var) \ 2010 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \ 2011 if (skip_rx_queue(bp, var)) \ 2012 continue; \ 2013 else 2014 2015 /* Skip OOO FP */ 2016 #define for_each_valid_tx_queue(bp, var) \ 2017 for ((var) = 0; \ 2018 (var) < (CNIC_LOADED(bp) ? BNX2X_NUM_QUEUES(bp) : \ 2019 BNX2X_NUM_ETH_QUEUES(bp)); \ 2020 (var)++) \ 2021 if (skip_tx_queue(bp, var)) \ 2022 continue; \ 2023 else 2024 2025 #define for_each_tx_queue_cnic(bp, var) \ 2026 for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \ 2027 (var)++) \ 2028 if (skip_tx_queue(bp, var)) \ 2029 continue; \ 2030 else 2031 2032 #define for_each_tx_queue(bp, var) \ 2033 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \ 2034 if (skip_tx_queue(bp, var)) \ 2035 continue; \ 2036 else 2037 2038 #define for_each_nondefault_queue(bp, var) \ 2039 for ((var) = 1; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \ 2040 if (skip_queue(bp, var)) \ 2041 continue; \ 2042 else 2043 2044 #define for_each_cos_in_tx_queue(fp, var) \ 2045 for ((var) = 0; (var) < (fp)->max_cos; (var)++) 2046 2047 /* skip rx queue 2048 * if FCOE l2 support is disabled and this is the fcoe L2 queue 2049 */ 2050 #define skip_rx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx)) 2051 2052 /* skip tx queue 2053 * if FCOE l2 support is disabled and this is the fcoe L2 queue 2054 */ 2055 #define skip_tx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx)) 2056 2057 #define skip_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx)) 2058 2059 /** 2060 * bnx2x_set_mac_one - configure a single MAC address 2061 * 2062 * @bp: driver handle 2063 * @mac: MAC to configure 2064 * @obj: MAC object handle 2065 * @set: if 'true' add a new MAC, otherwise - delete 2066 * @mac_type: the type of the MAC to configure (e.g. ETH, UC list) 2067 * @ramrod_flags: RAMROD_XXX flags (e.g. RAMROD_CONT, RAMROD_COMP_WAIT) 2068 * 2069 * Configures one MAC according to provided parameters or continues the 2070 * execution of previously scheduled commands if RAMROD_CONT is set in 2071 * ramrod_flags. 2072 * 2073 * Returns zero if operation has successfully completed, a positive value if the 2074 * operation has been successfully scheduled and a negative - if a requested 2075 * operations has failed. 2076 */ 2077 int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac, 2078 struct bnx2x_vlan_mac_obj *obj, bool set, 2079 int mac_type, unsigned long *ramrod_flags); 2080 /** 2081 * bnx2x_del_all_macs - delete all MACs configured for the specific MAC object 2082 * 2083 * @bp: driver handle 2084 * @mac_obj: MAC object handle 2085 * @mac_type: type of the MACs to clear (BNX2X_XXX_MAC) 2086 * @wait_for_comp: if 'true' block until completion 2087 * 2088 * Deletes all MACs of the specific type (e.g. ETH, UC list). 2089 * 2090 * Returns zero if operation has successfully completed, a positive value if the 2091 * operation has been successfully scheduled and a negative - if a requested 2092 * operations has failed. 2093 */ 2094 int bnx2x_del_all_macs(struct bnx2x *bp, 2095 struct bnx2x_vlan_mac_obj *mac_obj, 2096 int mac_type, bool wait_for_comp); 2097 2098 /* Init Function API */ 2099 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p); 2100 void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid, 2101 u8 vf_valid, int fw_sb_id, int igu_sb_id); 2102 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port); 2103 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port); 2104 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode); 2105 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port); 2106 void bnx2x_read_mf_cfg(struct bnx2x *bp); 2107 2108 int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val); 2109 2110 /* dmae */ 2111 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32); 2112 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr, 2113 u32 len32); 2114 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx); 2115 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type); 2116 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode); 2117 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type, 2118 bool with_comp, u8 comp_type); 2119 2120 void bnx2x_prep_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae, 2121 u8 src_type, u8 dst_type); 2122 int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae, 2123 u32 *comp); 2124 2125 /* FLR related routines */ 2126 u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp); 2127 void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count); 2128 int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt); 2129 u8 bnx2x_is_pcie_pending(struct pci_dev *dev); 2130 int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg, 2131 char *msg, u32 poll_cnt); 2132 2133 void bnx2x_calc_fc_adv(struct bnx2x *bp); 2134 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid, 2135 u32 data_hi, u32 data_lo, int cmd_type); 2136 void bnx2x_update_coalesce(struct bnx2x *bp); 2137 int bnx2x_get_cur_phy_idx(struct bnx2x *bp); 2138 2139 bool bnx2x_port_after_undi(struct bnx2x *bp); 2140 2141 static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms, 2142 int wait) 2143 { 2144 u32 val; 2145 2146 do { 2147 val = REG_RD(bp, reg); 2148 if (val == expected) 2149 break; 2150 ms -= wait; 2151 msleep(wait); 2152 2153 } while (ms > 0); 2154 2155 return val; 2156 } 2157 2158 void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id, 2159 bool is_pf); 2160 2161 #define BNX2X_ILT_ZALLOC(x, y, size) \ 2162 x = dma_zalloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL) 2163 2164 #define BNX2X_ILT_FREE(x, y, size) \ 2165 do { \ 2166 if (x) { \ 2167 dma_free_coherent(&bp->pdev->dev, size, x, y); \ 2168 x = NULL; \ 2169 y = 0; \ 2170 } \ 2171 } while (0) 2172 2173 #define ILOG2(x) (ilog2((x))) 2174 2175 #define ILT_NUM_PAGE_ENTRIES (3072) 2176 /* In 57710/11 we use whole table since we have 8 func 2177 * In 57712 we have only 4 func, but use same size per func, then only half of 2178 * the table in use 2179 */ 2180 #define ILT_PER_FUNC (ILT_NUM_PAGE_ENTRIES/8) 2181 2182 #define FUNC_ILT_BASE(func) (func * ILT_PER_FUNC) 2183 /* 2184 * the phys address is shifted right 12 bits and has an added 2185 * 1=valid bit added to the 53rd bit 2186 * then since this is a wide register(TM) 2187 * we split it into two 32 bit writes 2188 */ 2189 #define ONCHIP_ADDR1(x) ((u32)(((u64)x >> 12) & 0xFFFFFFFF)) 2190 #define ONCHIP_ADDR2(x) ((u32)((1 << 20) | ((u64)x >> 44))) 2191 2192 /* load/unload mode */ 2193 #define LOAD_NORMAL 0 2194 #define LOAD_OPEN 1 2195 #define LOAD_DIAG 2 2196 #define LOAD_LOOPBACK_EXT 3 2197 #define UNLOAD_NORMAL 0 2198 #define UNLOAD_CLOSE 1 2199 #define UNLOAD_RECOVERY 2 2200 2201 /* DMAE command defines */ 2202 #define DMAE_TIMEOUT -1 2203 #define DMAE_PCI_ERROR -2 /* E2 and onward */ 2204 #define DMAE_NOT_RDY -3 2205 #define DMAE_PCI_ERR_FLAG 0x80000000 2206 2207 #define DMAE_SRC_PCI 0 2208 #define DMAE_SRC_GRC 1 2209 2210 #define DMAE_DST_NONE 0 2211 #define DMAE_DST_PCI 1 2212 #define DMAE_DST_GRC 2 2213 2214 #define DMAE_COMP_PCI 0 2215 #define DMAE_COMP_GRC 1 2216 2217 /* E2 and onward - PCI error handling in the completion */ 2218 2219 #define DMAE_COMP_REGULAR 0 2220 #define DMAE_COM_SET_ERR 1 2221 2222 #define DMAE_CMD_SRC_PCI (DMAE_SRC_PCI << \ 2223 DMAE_COMMAND_SRC_SHIFT) 2224 #define DMAE_CMD_SRC_GRC (DMAE_SRC_GRC << \ 2225 DMAE_COMMAND_SRC_SHIFT) 2226 2227 #define DMAE_CMD_DST_PCI (DMAE_DST_PCI << \ 2228 DMAE_COMMAND_DST_SHIFT) 2229 #define DMAE_CMD_DST_GRC (DMAE_DST_GRC << \ 2230 DMAE_COMMAND_DST_SHIFT) 2231 2232 #define DMAE_CMD_C_DST_PCI (DMAE_COMP_PCI << \ 2233 DMAE_COMMAND_C_DST_SHIFT) 2234 #define DMAE_CMD_C_DST_GRC (DMAE_COMP_GRC << \ 2235 DMAE_COMMAND_C_DST_SHIFT) 2236 2237 #define DMAE_CMD_C_ENABLE DMAE_COMMAND_C_TYPE_ENABLE 2238 2239 #define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT) 2240 #define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT) 2241 #define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT) 2242 #define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT) 2243 2244 #define DMAE_CMD_PORT_0 0 2245 #define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT 2246 2247 #define DMAE_CMD_SRC_RESET DMAE_COMMAND_SRC_RESET 2248 #define DMAE_CMD_DST_RESET DMAE_COMMAND_DST_RESET 2249 #define DMAE_CMD_E1HVN_SHIFT DMAE_COMMAND_E1HVN_SHIFT 2250 2251 #define DMAE_SRC_PF 0 2252 #define DMAE_SRC_VF 1 2253 2254 #define DMAE_DST_PF 0 2255 #define DMAE_DST_VF 1 2256 2257 #define DMAE_C_SRC 0 2258 #define DMAE_C_DST 1 2259 2260 #define DMAE_LEN32_RD_MAX 0x80 2261 #define DMAE_LEN32_WR_MAX(bp) (CHIP_IS_E1(bp) ? 0x400 : 0x2000) 2262 2263 #define DMAE_COMP_VAL 0x60d0d0ae /* E2 and on - upper bit 2264 * indicates error 2265 */ 2266 2267 #define MAX_DMAE_C_PER_PORT 8 2268 #define INIT_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \ 2269 BP_VN(bp)) 2270 #define PMF_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \ 2271 E1HVN_MAX) 2272 2273 /* PCIE link and speed */ 2274 #define PCICFG_LINK_WIDTH 0x1f00000 2275 #define PCICFG_LINK_WIDTH_SHIFT 20 2276 #define PCICFG_LINK_SPEED 0xf0000 2277 #define PCICFG_LINK_SPEED_SHIFT 16 2278 2279 #define BNX2X_NUM_TESTS_SF 7 2280 #define BNX2X_NUM_TESTS_MF 3 2281 #define BNX2X_NUM_TESTS(bp) (IS_MF(bp) ? BNX2X_NUM_TESTS_MF : \ 2282 IS_VF(bp) ? 0 : BNX2X_NUM_TESTS_SF) 2283 2284 #define BNX2X_PHY_LOOPBACK 0 2285 #define BNX2X_MAC_LOOPBACK 1 2286 #define BNX2X_EXT_LOOPBACK 2 2287 #define BNX2X_PHY_LOOPBACK_FAILED 1 2288 #define BNX2X_MAC_LOOPBACK_FAILED 2 2289 #define BNX2X_EXT_LOOPBACK_FAILED 3 2290 #define BNX2X_LOOPBACK_FAILED (BNX2X_MAC_LOOPBACK_FAILED | \ 2291 BNX2X_PHY_LOOPBACK_FAILED) 2292 2293 #define STROM_ASSERT_ARRAY_SIZE 50 2294 2295 /* must be used on a CID before placing it on a HW ring */ 2296 #define HW_CID(bp, x) ((BP_PORT(bp) << 23) | \ 2297 (BP_VN(bp) << BNX2X_SWCID_SHIFT) | \ 2298 (x)) 2299 2300 #define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe)) 2301 #define MAX_SP_DESC_CNT (SP_DESC_CNT - 1) 2302 2303 #define BNX2X_BTR 4 2304 #define MAX_SPQ_PENDING 8 2305 2306 /* CMNG constants, as derived from system spec calculations */ 2307 /* default MIN rate in case VNIC min rate is configured to zero - 100Mbps */ 2308 #define DEF_MIN_RATE 100 2309 /* resolution of the rate shaping timer - 400 usec */ 2310 #define RS_PERIODIC_TIMEOUT_USEC 400 2311 /* number of bytes in single QM arbitration cycle - 2312 * coefficient for calculating the fairness timer */ 2313 #define QM_ARB_BYTES 160000 2314 /* resolution of Min algorithm 1:100 */ 2315 #define MIN_RES 100 2316 /* how many bytes above threshold for the minimal credit of Min algorithm*/ 2317 #define MIN_ABOVE_THRESH 32768 2318 /* Fairness algorithm integration time coefficient - 2319 * for calculating the actual Tfair */ 2320 #define T_FAIR_COEF ((MIN_ABOVE_THRESH + QM_ARB_BYTES) * 8 * MIN_RES) 2321 /* Memory of fairness algorithm . 2 cycles */ 2322 #define FAIR_MEM 2 2323 2324 #define ATTN_NIG_FOR_FUNC (1L << 8) 2325 #define ATTN_SW_TIMER_4_FUNC (1L << 9) 2326 #define GPIO_2_FUNC (1L << 10) 2327 #define GPIO_3_FUNC (1L << 11) 2328 #define GPIO_4_FUNC (1L << 12) 2329 #define ATTN_GENERAL_ATTN_1 (1L << 13) 2330 #define ATTN_GENERAL_ATTN_2 (1L << 14) 2331 #define ATTN_GENERAL_ATTN_3 (1L << 15) 2332 #define ATTN_GENERAL_ATTN_4 (1L << 13) 2333 #define ATTN_GENERAL_ATTN_5 (1L << 14) 2334 #define ATTN_GENERAL_ATTN_6 (1L << 15) 2335 2336 #define ATTN_HARD_WIRED_MASK 0xff00 2337 #define ATTENTION_ID 4 2338 2339 #define IS_MF_STORAGE_ONLY(bp) (IS_MF_STORAGE_PERSONALITY_ONLY(bp) || \ 2340 IS_MF_FCOE_AFEX(bp)) 2341 2342 /* stuff added to make the code fit 80Col */ 2343 2344 #define BNX2X_PMF_LINK_ASSERT \ 2345 GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + BP_FUNC(bp)) 2346 2347 #define BNX2X_MC_ASSERT_BITS \ 2348 (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 2349 GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 2350 GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 2351 GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT)) 2352 2353 #define BNX2X_MCP_ASSERT \ 2354 GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT) 2355 2356 #define BNX2X_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC) 2357 #define BNX2X_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \ 2358 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \ 2359 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \ 2360 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \ 2361 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \ 2362 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC)) 2363 2364 #define HW_INTERRUT_ASSERT_SET_0 \ 2365 (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \ 2366 AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \ 2367 AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \ 2368 AEU_INPUTS_ATTN_BITS_BRB_HW_INTERRUPT | \ 2369 AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT) 2370 #define HW_PRTY_ASSERT_SET_0 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \ 2371 AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \ 2372 AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \ 2373 AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\ 2374 AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR |\ 2375 AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR |\ 2376 AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR) 2377 #define HW_INTERRUT_ASSERT_SET_1 \ 2378 (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \ 2379 AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \ 2380 AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \ 2381 AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \ 2382 AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \ 2383 AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \ 2384 AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \ 2385 AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \ 2386 AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \ 2387 AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \ 2388 AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT) 2389 #define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR |\ 2390 AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \ 2391 AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR |\ 2392 AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \ 2393 AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR |\ 2394 AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \ 2395 AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\ 2396 AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR |\ 2397 AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\ 2398 AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \ 2399 AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \ 2400 AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR |\ 2401 AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \ 2402 AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \ 2403 AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR |\ 2404 AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR) 2405 #define HW_INTERRUT_ASSERT_SET_2 \ 2406 (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \ 2407 AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \ 2408 AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \ 2409 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\ 2410 AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT) 2411 #define HW_PRTY_ASSERT_SET_2 (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \ 2412 AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \ 2413 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\ 2414 AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \ 2415 AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \ 2416 AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR |\ 2417 AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \ 2418 AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR) 2419 2420 #define HW_PRTY_ASSERT_SET_3_WITHOUT_SCPAD \ 2421 (AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \ 2422 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \ 2423 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY) 2424 2425 #define HW_PRTY_ASSERT_SET_3 (HW_PRTY_ASSERT_SET_3_WITHOUT_SCPAD | \ 2426 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY) 2427 2428 #define HW_PRTY_ASSERT_SET_4 (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | \ 2429 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR) 2430 2431 #define MULTI_MASK 0x7f 2432 2433 #define DEF_USB_FUNC_OFF offsetof(struct cstorm_def_status_block_u, func) 2434 #define DEF_CSB_FUNC_OFF offsetof(struct cstorm_def_status_block_c, func) 2435 #define DEF_XSB_FUNC_OFF offsetof(struct xstorm_def_status_block, func) 2436 #define DEF_TSB_FUNC_OFF offsetof(struct tstorm_def_status_block, func) 2437 2438 #define DEF_USB_IGU_INDEX_OFF \ 2439 offsetof(struct cstorm_def_status_block_u, igu_index) 2440 #define DEF_CSB_IGU_INDEX_OFF \ 2441 offsetof(struct cstorm_def_status_block_c, igu_index) 2442 #define DEF_XSB_IGU_INDEX_OFF \ 2443 offsetof(struct xstorm_def_status_block, igu_index) 2444 #define DEF_TSB_IGU_INDEX_OFF \ 2445 offsetof(struct tstorm_def_status_block, igu_index) 2446 2447 #define DEF_USB_SEGMENT_OFF \ 2448 offsetof(struct cstorm_def_status_block_u, segment) 2449 #define DEF_CSB_SEGMENT_OFF \ 2450 offsetof(struct cstorm_def_status_block_c, segment) 2451 #define DEF_XSB_SEGMENT_OFF \ 2452 offsetof(struct xstorm_def_status_block, segment) 2453 #define DEF_TSB_SEGMENT_OFF \ 2454 offsetof(struct tstorm_def_status_block, segment) 2455 2456 #define BNX2X_SP_DSB_INDEX \ 2457 (&bp->def_status_blk->sp_sb.\ 2458 index_values[HC_SP_INDEX_ETH_DEF_CONS]) 2459 2460 #define CAM_IS_INVALID(x) \ 2461 (GET_FLAG(x.flags, \ 2462 MAC_CONFIGURATION_ENTRY_ACTION_TYPE) == \ 2463 (T_ETH_MAC_COMMAND_INVALIDATE)) 2464 2465 /* Number of u32 elements in MC hash array */ 2466 #define MC_HASH_SIZE 8 2467 #define MC_HASH_OFFSET(bp, i) (BAR_TSTRORM_INTMEM + \ 2468 TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(BP_FUNC(bp)) + i*4) 2469 2470 #ifndef PXP2_REG_PXP2_INT_STS 2471 #define PXP2_REG_PXP2_INT_STS PXP2_REG_PXP2_INT_STS_0 2472 #endif 2473 2474 #ifndef ETH_MAX_RX_CLIENTS_E2 2475 #define ETH_MAX_RX_CLIENTS_E2 ETH_MAX_RX_CLIENTS_E1H 2476 #endif 2477 2478 #define BNX2X_VPD_LEN 128 2479 #define VENDOR_ID_LEN 4 2480 2481 #define VF_ACQUIRE_THRESH 3 2482 #define VF_ACQUIRE_MAC_FILTERS 1 2483 #define VF_ACQUIRE_MC_FILTERS 10 2484 2485 #define GOOD_ME_REG(me_reg) (((me_reg) & ME_REG_VF_VALID) && \ 2486 (!((me_reg) & ME_REG_VF_ERR))) 2487 int bnx2x_compare_fw_ver(struct bnx2x *bp, u32 load_code, bool print_err); 2488 2489 /* Congestion management fairness mode */ 2490 #define CMNG_FNS_NONE 0 2491 #define CMNG_FNS_MINMAX 1 2492 2493 #define HC_SEG_ACCESS_DEF 0 /*Driver decision 0-3*/ 2494 #define HC_SEG_ACCESS_ATTN 4 2495 #define HC_SEG_ACCESS_NORM 0 /*Driver decision 0-1*/ 2496 2497 static const u32 dmae_reg_go_c[] = { 2498 DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3, 2499 DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7, 2500 DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11, 2501 DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15 2502 }; 2503 2504 void bnx2x_set_ethtool_ops(struct bnx2x *bp, struct net_device *netdev); 2505 void bnx2x_notify_link_changed(struct bnx2x *bp); 2506 2507 #define BNX2X_MF_SD_PROTOCOL(bp) \ 2508 ((bp)->mf_config[BP_VN(bp)] & FUNC_MF_CFG_PROTOCOL_MASK) 2509 2510 #define BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp) \ 2511 (BNX2X_MF_SD_PROTOCOL(bp) == FUNC_MF_CFG_PROTOCOL_ISCSI) 2512 2513 #define BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp) \ 2514 (BNX2X_MF_SD_PROTOCOL(bp) == FUNC_MF_CFG_PROTOCOL_FCOE) 2515 2516 #define IS_MF_ISCSI_SD(bp) (IS_MF_SD(bp) && BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) 2517 #define IS_MF_FCOE_SD(bp) (IS_MF_SD(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) 2518 #define IS_MF_ISCSI_SI(bp) (IS_MF_SI(bp) && BNX2X_IS_MF_EXT_PROTOCOL_ISCSI(bp)) 2519 2520 #define IS_MF_ISCSI_ONLY(bp) (IS_MF_ISCSI_SD(bp) || IS_MF_ISCSI_SI(bp)) 2521 2522 #define BNX2X_MF_EXT_PROTOCOL_MASK \ 2523 (MACP_FUNC_CFG_FLAGS_ETHERNET | \ 2524 MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD | \ 2525 MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) 2526 2527 #define BNX2X_MF_EXT_PROT(bp) ((bp)->mf_ext_config & \ 2528 BNX2X_MF_EXT_PROTOCOL_MASK) 2529 2530 #define BNX2X_HAS_MF_EXT_PROTOCOL_FCOE(bp) \ 2531 (BNX2X_MF_EXT_PROT(bp) & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) 2532 2533 #define BNX2X_IS_MF_EXT_PROTOCOL_FCOE(bp) \ 2534 (BNX2X_MF_EXT_PROT(bp) == MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) 2535 2536 #define BNX2X_IS_MF_EXT_PROTOCOL_ISCSI(bp) \ 2537 (BNX2X_MF_EXT_PROT(bp) == MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) 2538 2539 #define IS_MF_FCOE_AFEX(bp) \ 2540 (IS_MF_AFEX(bp) && BNX2X_IS_MF_EXT_PROTOCOL_FCOE(bp)) 2541 2542 #define IS_MF_SD_STORAGE_PERSONALITY_ONLY(bp) \ 2543 (IS_MF_SD(bp) && \ 2544 (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp) || \ 2545 BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp))) 2546 2547 #define IS_MF_SI_STORAGE_PERSONALITY_ONLY(bp) \ 2548 (IS_MF_SI(bp) && \ 2549 (BNX2X_IS_MF_EXT_PROTOCOL_ISCSI(bp) || \ 2550 BNX2X_IS_MF_EXT_PROTOCOL_FCOE(bp))) 2551 2552 #define IS_MF_STORAGE_PERSONALITY_ONLY(bp) \ 2553 (IS_MF_SD_STORAGE_PERSONALITY_ONLY(bp) || \ 2554 IS_MF_SI_STORAGE_PERSONALITY_ONLY(bp)) 2555 2556 2557 #define SET_FLAG(value, mask, flag) \ 2558 do {\ 2559 (value) &= ~(mask);\ 2560 (value) |= ((flag) << (mask##_SHIFT));\ 2561 } while (0) 2562 2563 #define GET_FLAG(value, mask) \ 2564 (((value) & (mask)) >> (mask##_SHIFT)) 2565 2566 #define GET_FIELD(value, fname) \ 2567 (((value) & (fname##_MASK)) >> (fname##_SHIFT)) 2568 2569 enum { 2570 SWITCH_UPDATE, 2571 AFEX_UPDATE, 2572 }; 2573 2574 #define NUM_MACS 8 2575 2576 void bnx2x_set_local_cmng(struct bnx2x *bp); 2577 2578 void bnx2x_update_mng_version(struct bnx2x *bp); 2579 2580 #define MCPR_SCRATCH_BASE(bp) \ 2581 (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH) 2582 2583 #define E1H_MAX_MF_SB_COUNT (HC_SB_MAX_SB_E1X/(E1HVN_MAX * PORT_MAX)) 2584 2585 void bnx2x_init_ptp(struct bnx2x *bp); 2586 int bnx2x_configure_ptp_filters(struct bnx2x *bp); 2587 void bnx2x_set_rx_ts(struct bnx2x *bp, struct sk_buff *skb); 2588 2589 #define BNX2X_MAX_PHC_DRIFT 31000000 2590 #define BNX2X_PTP_TX_TIMEOUT 2591 2592 #endif /* bnx2x.h */ 2593